From 50c4d632ea970d16cb1e321ec9b6e69f6d78ad93 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 15 Mar 2017 16:10:06 -0700 Subject: Use newer rocket regression spec without comb loop --- regress/rocket-firrtl.fir | 35444 --------- regress/rocket.0.fir | 32895 -------- regress/rocket.fir | 179205 +++++++++++++++++++++++++++++++++++-------- 3 files changed, 147233 insertions(+), 100311 deletions(-) delete mode 100644 regress/rocket-firrtl.fir delete mode 100644 regress/rocket.0.fir (limited to 'regress') diff --git a/regress/rocket-firrtl.fir b/regress/rocket-firrtl.fir deleted file mode 100644 index 6083af14..00000000 --- a/regress/rocket-firrtl.fir +++ /dev/null @@ -1,35444 +0,0 @@ -circuit Top : - module Htif : - input clk : Clock - input reset : UInt<1> - output io : { host : { clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, scr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - io.host.debug_stats_csr <= io.cpu[0].debug_stats_csr - reg rx_count : UInt<15>, clk with : - reset => (reset, UInt<15>("h0")) - reg rx_shifter : UInt<64>, clk with : - reset => (UInt<1>("h0"), rx_shifter) - node T_1212 = bits(rx_shifter, 63, 16) - node rx_shifter_in = cat(io.host.in.bits, T_1212) - node next_cmd = bits(rx_shifter_in, 3, 0) - reg cmd : UInt, clk with : - reset => (UInt<1>("h0"), cmd) - reg size : UInt, clk with : - reset => (UInt<1>("h0"), size) - reg pos : UInt, clk with : - reset => (UInt<1>("h0"), pos) - reg seqno : UInt, clk with : - reset => (UInt<1>("h0"), seqno) - reg addr : UInt, clk with : - reset => (UInt<1>("h0"), addr) - node T_1225 = and(io.host.in.valid, io.host.in.ready) - when T_1225 : - rx_shifter <= rx_shifter_in - node T_1227 = add(rx_count, UInt<1>("h1")) - node T_1228 = tail(T_1227, 1) - rx_count <= T_1228 - node T_1230 = eq(rx_count, UInt<2>("h3")) - when T_1230 : - cmd <= next_cmd - node T_1231 = bits(rx_shifter_in, 15, 4) - size <= T_1231 - node T_1232 = bits(rx_shifter_in, 15, 7) - pos <= T_1232 - node T_1233 = bits(rx_shifter_in, 23, 16) - seqno <= T_1233 - node T_1234 = bits(rx_shifter_in, 63, 24) - addr <= T_1234 - skip - skip - node rx_word_count = shr(rx_count, 2) - node T_1236 = bits(rx_count, 1, 0) - node T_1237 = not(T_1236) - node T_1239 = eq(T_1237, UInt<1>("h0")) - node rx_word_done = and(io.host.in.valid, T_1239) - mem packet_ram : - data-type => UInt<64> - depth => 8 - write-latency => 1 - read-latency => 0 - reader => csr_wdata - reader => T_1411 - reader => T_1419 - reader => T_1734 - writer => T_1249 - writer => T_1408 - writer => T_1416 - packet_ram.csr_wdata.addr is invalid - packet_ram.csr_wdata.clk <= clk - packet_ram.T_1411.addr is invalid - packet_ram.T_1411.clk <= clk - packet_ram.T_1419.addr is invalid - packet_ram.T_1419.clk <= clk - packet_ram.T_1734.addr is invalid - packet_ram.T_1734.clk <= clk - packet_ram.csr_wdata.en <= UInt<1>("h0") - packet_ram.T_1411.en <= UInt<1>("h0") - packet_ram.T_1419.en <= UInt<1>("h0") - packet_ram.T_1734.en <= UInt<1>("h0") - packet_ram.T_1249.addr is invalid - packet_ram.T_1249.clk <= clk - packet_ram.T_1408.addr is invalid - packet_ram.T_1408.clk <= clk - packet_ram.T_1416.addr is invalid - packet_ram.T_1416.clk <= clk - packet_ram.T_1249.en <= UInt<1>("h0") - packet_ram.T_1408.en <= UInt<1>("h0") - packet_ram.T_1416.en <= UInt<1>("h0") - packet_ram.T_1249.data is invalid - packet_ram.T_1249.mask <= UInt<1>("h0") - packet_ram.T_1408.data is invalid - packet_ram.T_1408.mask <= UInt<1>("h0") - packet_ram.T_1416.data is invalid - packet_ram.T_1416.mask <= UInt<1>("h0") - node T_1244 = and(rx_word_done, io.host.in.ready) - when T_1244 : - node T_1245 = bits(rx_word_count, 2, 0) - node T_1247 = sub(T_1245, UInt<1>("h1")) - node T_1248 = tail(T_1247, 1) - packet_ram.T_1249.addr <= T_1248 - packet_ram.T_1249.en <= UInt<1>("h1") - packet_ram.T_1249.data <= rx_shifter_in - packet_ram.T_1249.mask <= UInt<1>("h1") - skip - node csr_addr = bits(addr, 11, 0) - node csr_coreid = bits(addr, 21, 20) - packet_ram.csr_wdata.addr <= UInt<1>("h0") - packet_ram.csr_wdata.en <= UInt<1>("h1") - node T_1261 = bits(size, 2, 0) - node T_1263 = neq(T_1261, UInt<1>("h0")) - node T_1264 = bits(addr, 2, 0) - node T_1266 = neq(T_1264, UInt<1>("h0")) - node bad_mem_packet = or(T_1263, T_1266) - node T_1268 = eq(cmd, UInt<1>("h0")) - node T_1269 = eq(cmd, UInt<1>("h1")) - node T_1270 = or(T_1268, T_1269) - node T_1271 = eq(cmd, UInt<2>("h2")) - node T_1272 = eq(cmd, UInt<2>("h3")) - node T_1273 = or(T_1271, T_1272) - node T_1275 = neq(size, UInt<1>("h1")) - node T_1277 = mux(T_1273, T_1275, UInt<1>("h1")) - node nack = mux(T_1270, bad_mem_packet, T_1277) - reg tx_count : UInt<15>, clk with : - reset => (reset, UInt<15>("h0")) - node tx_subword_count = bits(tx_count, 1, 0) - node tx_word_count = bits(tx_count, 14, 2) - node T_1283 = bits(tx_word_count, 2, 0) - node T_1285 = sub(T_1283, UInt<1>("h1")) - node packet_ram_raddr = tail(T_1285, 1) - node T_1287 = and(io.host.out.valid, io.host.out.ready) - when T_1287 : - node T_1289 = add(tx_count, UInt<1>("h1")) - node T_1290 = tail(T_1289, 1) - tx_count <= T_1290 - skip - node T_1292 = eq(rx_word_count, UInt<1>("h0")) - node T_1293 = neq(next_cmd, UInt<1>("h1")) - node T_1294 = neq(next_cmd, UInt<2>("h3")) - node T_1295 = and(T_1293, T_1294) - node T_1296 = eq(rx_word_count, size) - node T_1297 = bits(rx_word_count, 2, 0) - node T_1299 = eq(T_1297, UInt<1>("h0")) - node T_1300 = or(T_1296, T_1299) - node T_1301 = mux(T_1292, T_1295, T_1300) - node rx_done = and(rx_word_done, T_1301) - node T_1304 = eq(nack, UInt<1>("h0")) - node T_1305 = eq(cmd, UInt<1>("h0")) - node T_1306 = eq(cmd, UInt<2>("h2")) - node T_1307 = or(T_1305, T_1306) - node T_1308 = eq(cmd, UInt<2>("h3")) - node T_1309 = or(T_1307, T_1308) - node T_1310 = and(T_1304, T_1309) - node tx_size = mux(T_1310, size, UInt<1>("h0")) - node T_1313 = not(tx_subword_count) - node T_1315 = eq(T_1313, UInt<1>("h0")) - node T_1316 = and(io.host.out.ready, T_1315) - node T_1317 = eq(tx_word_count, tx_size) - node T_1319 = gt(tx_word_count, UInt<1>("h0")) - node T_1320 = not(packet_ram_raddr) - node T_1322 = eq(T_1320, UInt<1>("h0")) - node T_1323 = and(T_1319, T_1322) - node T_1324 = or(T_1317, T_1323) - node tx_done = and(T_1316, T_1324) - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - node T_1336 = eq(state, UInt<3>("h4")) - node T_1337 = and(T_1336, io.mem.acquire.ready) - node T_1338 = eq(state, UInt<3>("h5")) - node T_1339 = and(T_1338, io.mem.grant.valid) - node T_1340 = or(T_1337, T_1339) - reg cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1340 : - node T_1344 = eq(cnt, UInt<2>("h3")) - node T_1346 = and(UInt<1>("h0"), T_1344) - node T_1349 = add(cnt, UInt<1>("h1")) - node T_1350 = tail(T_1349, 1) - node T_1351 = mux(T_1346, UInt<1>("h0"), T_1350) - cnt <= T_1351 - skip - node cnt_done = and(T_1340, T_1344) - node T_1354 = eq(rx_word_count, UInt<1>("h0")) - node rx_cmd = mux(T_1354, next_cmd, cmd) - node T_1356 = eq(state, UInt<1>("h0")) - node T_1357 = and(T_1356, rx_done) - when T_1357 : - node T_1358 = eq(rx_cmd, UInt<1>("h0")) - node T_1359 = eq(rx_cmd, UInt<1>("h1")) - node T_1360 = eq(rx_cmd, UInt<2>("h2")) - node T_1361 = eq(rx_cmd, UInt<2>("h3")) - node T_1362 = or(T_1360, T_1361) - node T_1363 = mux(T_1362, UInt<1>("h1"), UInt<3>("h7")) - node T_1364 = mux(T_1359, UInt<3>("h4"), T_1363) - node T_1365 = mux(T_1358, UInt<2>("h3"), T_1364) - state <= T_1365 - skip - node T_1366 = eq(state, UInt<3>("h4")) - when T_1366 : - when cnt_done : - state <= UInt<3>("h6") - skip - skip - node T_1367 = eq(state, UInt<2>("h3")) - when T_1367 : - when io.mem.acquire.ready : - state <= UInt<3>("h5") - skip - skip - node T_1368 = eq(state, UInt<3>("h6")) - node T_1369 = and(T_1368, io.mem.grant.valid) - when T_1369 : - node T_1370 = eq(cmd, UInt<1>("h0")) - node T_1372 = eq(pos, UInt<1>("h1")) - node T_1373 = or(T_1370, T_1372) - node T_1374 = mux(T_1373, UInt<3>("h7"), UInt<1>("h0")) - state <= T_1374 - node T_1376 = sub(pos, UInt<1>("h1")) - node T_1377 = tail(T_1376, 1) - pos <= T_1377 - node T_1379 = add(addr, UInt<4>("h8")) - node T_1380 = tail(T_1379, 1) - addr <= T_1380 - skip - node T_1381 = eq(state, UInt<3>("h5")) - node T_1382 = and(T_1381, cnt_done) - when T_1382 : - node T_1383 = eq(cmd, UInt<1>("h0")) - node T_1385 = eq(pos, UInt<1>("h1")) - node T_1386 = or(T_1383, T_1385) - node T_1387 = mux(T_1386, UInt<3>("h7"), UInt<1>("h0")) - state <= T_1387 - node T_1389 = sub(pos, UInt<1>("h1")) - node T_1390 = tail(T_1389, 1) - pos <= T_1390 - node T_1392 = add(addr, UInt<4>("h8")) - node T_1393 = tail(T_1392, 1) - addr <= T_1393 - skip - node T_1394 = eq(state, UInt<3>("h7")) - node T_1395 = and(T_1394, tx_done) - when T_1395 : - node T_1396 = eq(tx_word_count, tx_size) - when T_1396 : - rx_count <= UInt<1>("h0") - tx_count <= UInt<1>("h0") - skip - node T_1399 = eq(cmd, UInt<1>("h0")) - node T_1401 = neq(pos, UInt<1>("h0")) - node T_1402 = and(T_1399, T_1401) - node T_1403 = mux(T_1402, UInt<2>("h3"), UInt<1>("h0")) - state <= T_1403 - skip - node T_1405 = eq(state, UInt<3>("h5")) - node T_1406 = and(T_1405, io.mem.grant.valid) - when T_1406 : - node T_1407 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h0")) - packet_ram.T_1408.addr <= T_1407 - packet_ram.T_1408.en <= UInt<1>("h1") - node T_1409 = bits(io.mem.grant.bits.data, 63, 0) - packet_ram.T_1408.data <= T_1409 - packet_ram.T_1408.mask <= UInt<1>("h1") - skip - node T_1410 = cat(cnt, UInt<1>("h0")) - packet_ram.T_1411.addr <= T_1410 - packet_ram.T_1411.en <= UInt<1>("h1") - node T_1413 = eq(state, UInt<3>("h5")) - node T_1414 = and(T_1413, io.mem.grant.valid) - when T_1414 : - node T_1415 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h1")) - packet_ram.T_1416.addr <= T_1415 - packet_ram.T_1416.en <= UInt<1>("h1") - node T_1417 = bits(io.mem.grant.bits.data, 127, 64) - packet_ram.T_1416.data <= T_1417 - packet_ram.T_1416.mask <= UInt<1>("h1") - skip - node T_1418 = cat(cnt, UInt<1>("h1")) - packet_ram.T_1419.addr <= T_1418 - packet_ram.T_1419.en <= UInt<1>("h1") - node mem_req_data = cat(packet_ram.T_1419.data, packet_ram.T_1411.data) - node init_addr = shr(addr, 3) - node T_1422 = eq(state, UInt<2>("h3")) - node T_1423 = eq(state, UInt<3>("h4")) - node T_1424 = or(T_1422, T_1423) - io.mem.acquire.valid <= T_1424 - node T_1425 = eq(cmd, UInt<1>("h1")) - node T_1453 = asUInt(asSInt(UInt<16>("hffff"))) - node T_1459 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1460 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1461 = cat(T_1459, T_1460) - node T_1463 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1464 = cat(UInt<3>("h7"), T_1463) - node T_1466 = cat(T_1453, UInt<1>("h1")) - node T_1468 = cat(T_1453, UInt<1>("h1")) - node T_1470 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1471 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1472 = cat(T_1470, T_1471) - node T_1474 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1476 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_1477 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_1478 = mux(T_1477, T_1476, UInt<1>("h0")) - node T_1479 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_1480 = mux(T_1479, T_1474, T_1478) - node T_1481 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_1482 = mux(T_1481, T_1472, T_1480) - node T_1483 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_1484 = mux(T_1483, T_1468, T_1482) - node T_1485 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_1486 = mux(T_1485, T_1466, T_1484) - node T_1487 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_1488 = mux(T_1487, T_1464, T_1486) - node T_1489 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_1490 = mux(T_1489, T_1461, T_1488) - wire T_1522 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1522 is invalid - T_1522.is_builtin_type <= UInt<1>("h1") - T_1522.a_type <= UInt<3>("h3") - T_1522.client_xact_id <= UInt<1>("h0") - T_1522.addr_block <= init_addr - T_1522.addr_beat <= cnt - T_1522.data <= mem_req_data - T_1522.union <= T_1490 - node T_1563 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1564 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1565 = cat(T_1563, T_1564) - node T_1567 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1568 = cat(UInt<3>("h7"), T_1567) - node T_1570 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1572 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1574 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1575 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1576 = cat(T_1574, T_1575) - node T_1578 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1580 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_1581 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_1582 = mux(T_1581, T_1580, UInt<1>("h0")) - node T_1583 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_1584 = mux(T_1583, T_1578, T_1582) - node T_1585 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_1586 = mux(T_1585, T_1576, T_1584) - node T_1587 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_1588 = mux(T_1587, T_1572, T_1586) - node T_1589 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_1590 = mux(T_1589, T_1570, T_1588) - node T_1591 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_1592 = mux(T_1591, T_1568, T_1590) - node T_1593 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_1594 = mux(T_1593, T_1565, T_1592) - wire T_1626 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1626 is invalid - T_1626.is_builtin_type <= UInt<1>("h1") - T_1626.a_type <= UInt<3>("h1") - T_1626.client_xact_id <= UInt<1>("h0") - T_1626.addr_block <= init_addr - T_1626.addr_beat <= UInt<1>("h0") - T_1626.data <= UInt<1>("h0") - T_1626.union <= T_1594 - node T_1657 = mux(T_1425, T_1522, T_1626) - io.mem.acquire.bits <- T_1657 - io.mem.grant.ready <= UInt<1>("h1") - reg csrReadData : UInt<64>, clk with : - reset => (UInt<1>("h0"), csrReadData) - reg T_1692 : UInt<1>, clk with : - reset => (reset, UInt<1>("h1")) - node T_1694 = eq(csr_coreid, UInt<1>("h0")) - node T_1695 = eq(state, UInt<1>("h1")) - node T_1696 = and(T_1695, T_1694) - node T_1698 = neq(csr_addr, UInt<11>("h782")) - node T_1699 = and(T_1696, T_1698) - io.cpu[0].csr.req.valid <= T_1699 - node T_1700 = eq(cmd, UInt<2>("h3")) - io.cpu[0].csr.req.bits.rw <= T_1700 - io.cpu[0].csr.req.bits.addr <= csr_addr - io.cpu[0].csr.req.bits.data <= packet_ram.csr_wdata.data - io.cpu[0].reset <= T_1692 - node T_1701 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid) - when T_1701 : - state <= UInt<2>("h2") - skip - node T_1702 = eq(state, UInt<1>("h1")) - node T_1703 = and(T_1702, T_1694) - node T_1705 = eq(csr_addr, UInt<11>("h782")) - node T_1706 = and(T_1703, T_1705) - when T_1706 : - node T_1707 = eq(cmd, UInt<2>("h3")) - when T_1707 : - node T_1708 = bits(packet_ram.csr_wdata.data, 0, 0) - T_1692 <= T_1708 - skip - csrReadData <= T_1692 - state <= UInt<3>("h7") - skip - io.cpu[0].csr.resp.ready <= UInt<1>("h1") - node T_1710 = eq(state, UInt<2>("h2")) - node T_1711 = and(T_1710, io.cpu[0].csr.resp.valid) - when T_1711 : - csrReadData <= io.cpu[0].csr.resp.bits - state <= UInt<3>("h7") - skip - node T_1712 = eq(state, UInt<1>("h1")) - node T_1713 = not(csr_coreid) - node T_1715 = eq(T_1713, UInt<1>("h0")) - node T_1716 = and(T_1712, T_1715) - io.scr.req.valid <= T_1716 - node T_1717 = bits(addr, 5, 0) - io.scr.req.bits.addr <= T_1717 - io.scr.req.bits.data <= packet_ram.csr_wdata.data - node T_1718 = eq(cmd, UInt<2>("h3")) - io.scr.req.bits.rw <= T_1718 - io.scr.resp.ready <= UInt<1>("h1") - node T_1720 = and(io.scr.req.ready, io.scr.req.valid) - when T_1720 : - state <= UInt<2>("h2") - skip - node T_1721 = eq(state, UInt<2>("h2")) - node T_1722 = and(T_1721, io.scr.resp.valid) - when T_1722 : - csrReadData <= io.scr.resp.bits - state <= UInt<3>("h7") - skip - node tx_cmd = mux(nack, UInt<3>("h5"), UInt<3>("h4")) - node tx_cmd_ext = cat(UInt<1>("h0"), tx_cmd) - node T_1726 = cat(addr, seqno) - node T_1727 = cat(tx_size, tx_cmd_ext) - node tx_header = cat(T_1726, T_1727) - node T_1730 = eq(tx_word_count, UInt<1>("h0")) - node T_1731 = eq(cmd, UInt<2>("h2")) - node T_1732 = eq(cmd, UInt<2>("h3")) - node T_1733 = or(T_1731, T_1732) - packet_ram.T_1734.addr <= packet_ram_raddr - packet_ram.T_1734.en <= UInt<1>("h1") - node T_1735 = mux(T_1733, csrReadData, packet_ram.T_1734.data) - node tx_data = mux(T_1730, tx_header, T_1735) - node T_1737 = eq(state, UInt<1>("h0")) - io.host.in.ready <= T_1737 - node T_1738 = eq(state, UInt<3>("h7")) - io.host.out.valid <= T_1738 - node T_1739 = bits(tx_count, 1, 0) - node T_1741 = cat(T_1739, UInt<4>("h0")) - node T_1742 = dshr(tx_data, T_1741) - io.host.out.bits <= T_1742 - module ClientTileLinkIOWrapper : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io is invalid - io.out.acquire <- io.in.acquire - io.in.grant <- io.out.grant - io.out.probe.ready <= UInt<1>("h1") - io.out.release.valid <= UInt<1>("h0") - module FinishQueue : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { fin : { manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { fin : { manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>} - io is invalid - mem T_877 : - data-type => { fin : { manager_xact_id : UInt<4>}, dst : UInt<2>} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1025 - writer => T_900 - T_877.T_1025.addr is invalid - T_877.T_1025.clk <= clk - T_877.T_1025.en <= UInt<1>("h0") - T_877.T_900.addr is invalid - T_877.T_900.clk <= clk - T_877.T_900.en <= UInt<1>("h0") - T_877.T_900.data is invalid - T_877.T_900.mask.fin.manager_xact_id <= UInt<1>("h0") - T_877.T_900.mask.dst <= UInt<1>("h0") - reg T_879 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_881 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_883 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_884 = eq(T_879, T_881) - node T_886 = eq(T_883, UInt<1>("h0")) - node T_887 = and(T_884, T_886) - node T_888 = and(T_884, T_883) - node T_890 = and(UInt<1>("h0"), T_887) - node T_891 = and(T_890, io.deq.ready) - node T_892 = and(io.enq.ready, io.enq.valid) - node T_894 = eq(T_891, UInt<1>("h0")) - node T_895 = and(T_892, T_894) - node T_896 = and(io.deq.ready, io.deq.valid) - node T_898 = eq(T_891, UInt<1>("h0")) - node T_899 = and(T_896, T_898) - when T_895 : - T_877.T_900.addr <= T_879 - T_877.T_900.en <= UInt<1>("h1") - T_877.T_900.data <- io.enq.bits - T_877.T_900.mask.fin.manager_xact_id <= UInt<1>("h1") - T_877.T_900.mask.dst <= UInt<1>("h1") - node T_997 = eq(T_879, UInt<1>("h1")) - node T_999 = and(UInt<1>("h0"), T_997) - node T_1002 = add(T_879, UInt<1>("h1")) - node T_1003 = tail(T_1002, 1) - node T_1004 = mux(T_999, UInt<1>("h0"), T_1003) - T_879 <= T_1004 - skip - when T_899 : - node T_1006 = eq(T_881, UInt<1>("h1")) - node T_1008 = and(UInt<1>("h0"), T_1006) - node T_1011 = add(T_881, UInt<1>("h1")) - node T_1012 = tail(T_1011, 1) - node T_1013 = mux(T_1008, UInt<1>("h0"), T_1012) - T_881 <= T_1013 - skip - node T_1014 = neq(T_895, T_899) - when T_1014 : - T_883 <= T_895 - skip - node T_1016 = eq(T_887, UInt<1>("h0")) - node T_1018 = and(UInt<1>("h0"), io.enq.valid) - node T_1019 = or(T_1016, T_1018) - io.deq.valid <= T_1019 - node T_1021 = eq(T_888, UInt<1>("h0")) - node T_1023 = and(UInt<1>("h0"), io.deq.ready) - node T_1024 = or(T_1021, T_1023) - io.enq.ready <= T_1024 - T_877.T_1025.addr <= T_881 - T_877.T_1025.en <= UInt<1>("h1") - node T_1121 = mux(T_890, io.enq.bits, T_877.T_1025.data) - io.deq.bits <- T_1121 - node T_1217 = sub(T_879, T_881) - node T_1218 = tail(T_1217, 1) - node T_1219 = and(T_883, T_884) - node T_1220 = cat(T_1219, T_1218) - io.count <= T_1220 - module FinishUnit : - input clk : Clock - input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h5") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h0"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h0") - T_1190[1] <= UInt<1>("h1") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h0"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h1"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h3")) - node T_1207 = and(UInt<1>("h0"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h1")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h0"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h0")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h0")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h5") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h0"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h0") - T_1334[1] <= UInt<1>("h1") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h0"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h1"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h0")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : { manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<1>("h0") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h0")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h0")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h0")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h0")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - module ClientTileLinkNetworkPort : - input clk : Clock - input reset : UInt<1> - output io : {flip client : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - inst finisher of FinishUnit - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<1>("h0") - acq_with_header.bits.header.dst <= UInt<1>("h0") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<1>("h0") - rel_with_header.bits.header.dst <= UInt<1>("h0") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill - module Queue : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1337 - writer => T_1181 - ram.T_1337.addr is invalid - ram.T_1337.clk <= clk - ram.T_1337.en <= UInt<1>("h0") - ram.T_1181.addr is invalid - ram.T_1181.clk <= clk - ram.T_1181.en <= UInt<1>("h0") - ram.T_1181.data is invalid - ram.T_1181.mask.header.src <= UInt<1>("h0") - ram.T_1181.mask.header.dst <= UInt<1>("h0") - ram.T_1181.mask.payload.addr_block <= UInt<1>("h0") - ram.T_1181.mask.payload.client_xact_id <= UInt<1>("h0") - ram.T_1181.mask.payload.addr_beat <= UInt<1>("h0") - ram.T_1181.mask.payload.is_builtin_type <= UInt<1>("h0") - ram.T_1181.mask.payload.a_type <= UInt<1>("h0") - ram.T_1181.mask.payload.union <= UInt<1>("h0") - ram.T_1181.mask.payload.data <= UInt<1>("h0") - reg T_1160 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1162 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_1160, T_1162) - node T_1167 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1167) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1173 = and(io.enq.ready, io.enq.valid) - node T_1175 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1173, T_1175) - node T_1177 = and(io.deq.ready, io.deq.valid) - node T_1179 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1177, T_1179) - when do_enq : - ram.T_1181.addr <= T_1160 - ram.T_1181.en <= UInt<1>("h1") - ram.T_1181.data <- io.enq.bits - ram.T_1181.mask.header.src <= UInt<1>("h1") - ram.T_1181.mask.header.dst <= UInt<1>("h1") - ram.T_1181.mask.payload.addr_block <= UInt<1>("h1") - ram.T_1181.mask.payload.client_xact_id <= UInt<1>("h1") - ram.T_1181.mask.payload.addr_beat <= UInt<1>("h1") - ram.T_1181.mask.payload.is_builtin_type <= UInt<1>("h1") - ram.T_1181.mask.payload.a_type <= UInt<1>("h1") - ram.T_1181.mask.payload.union <= UInt<1>("h1") - ram.T_1181.mask.payload.data <= UInt<1>("h1") - node T_1309 = eq(T_1160, UInt<1>("h1")) - node T_1311 = and(UInt<1>("h0"), T_1309) - node T_1314 = add(T_1160, UInt<1>("h1")) - node T_1315 = tail(T_1314, 1) - node T_1316 = mux(T_1311, UInt<1>("h0"), T_1315) - T_1160 <= T_1316 - skip - when do_deq : - node T_1318 = eq(T_1162, UInt<1>("h1")) - node T_1320 = and(UInt<1>("h0"), T_1318) - node T_1323 = add(T_1162, UInt<1>("h1")) - node T_1324 = tail(T_1323, 1) - node T_1325 = mux(T_1320, UInt<1>("h0"), T_1324) - T_1162 <= T_1325 - skip - node T_1326 = neq(do_enq, do_deq) - when T_1326 : - maybe_full <= do_enq - skip - node T_1328 = eq(empty, UInt<1>("h0")) - node T_1330 = and(UInt<1>("h0"), io.enq.valid) - node T_1331 = or(T_1328, T_1330) - io.deq.valid <= T_1331 - node T_1333 = eq(full, UInt<1>("h0")) - node T_1335 = and(UInt<1>("h0"), io.deq.ready) - node T_1336 = or(T_1333, T_1335) - io.enq.ready <= T_1336 - ram.T_1337.addr <= T_1162 - ram.T_1337.en <= UInt<1>("h1") - node T_1464 = mux(maybe_flow, io.enq.bits, ram.T_1337.data) - io.deq.bits <- T_1464 - node T_1591 = sub(T_1160, T_1162) - node ptr_diff = tail(T_1591, 1) - node T_1593 = and(maybe_full, ptr_match) - node T_1594 = cat(T_1593, ptr_diff) - io.count <= T_1594 - module Queue_2 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1287 - writer => T_1136 - ram.T_1287.addr is invalid - ram.T_1287.clk <= clk - ram.T_1287.en <= UInt<1>("h0") - ram.T_1136.addr is invalid - ram.T_1136.clk <= clk - ram.T_1136.en <= UInt<1>("h0") - ram.T_1136.data is invalid - ram.T_1136.mask.header.src <= UInt<1>("h0") - ram.T_1136.mask.header.dst <= UInt<1>("h0") - ram.T_1136.mask.payload.addr_block <= UInt<1>("h0") - ram.T_1136.mask.payload.p_type <= UInt<1>("h0") - reg T_1115 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1117 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_1115, T_1117) - node T_1122 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1122) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1128 = and(io.enq.ready, io.enq.valid) - node T_1130 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1128, T_1130) - node T_1132 = and(io.deq.ready, io.deq.valid) - node T_1134 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1132, T_1134) - when do_enq : - ram.T_1136.addr <= T_1115 - ram.T_1136.en <= UInt<1>("h1") - ram.T_1136.data <- io.enq.bits - ram.T_1136.mask.header.src <= UInt<1>("h1") - ram.T_1136.mask.header.dst <= UInt<1>("h1") - ram.T_1136.mask.payload.addr_block <= UInt<1>("h1") - ram.T_1136.mask.payload.p_type <= UInt<1>("h1") - node T_1259 = eq(T_1115, UInt<1>("h1")) - node T_1261 = and(UInt<1>("h0"), T_1259) - node T_1264 = add(T_1115, UInt<1>("h1")) - node T_1265 = tail(T_1264, 1) - node T_1266 = mux(T_1261, UInt<1>("h0"), T_1265) - T_1115 <= T_1266 - skip - when do_deq : - node T_1268 = eq(T_1117, UInt<1>("h1")) - node T_1270 = and(UInt<1>("h0"), T_1268) - node T_1273 = add(T_1117, UInt<1>("h1")) - node T_1274 = tail(T_1273, 1) - node T_1275 = mux(T_1270, UInt<1>("h0"), T_1274) - T_1117 <= T_1275 - skip - node T_1276 = neq(do_enq, do_deq) - when T_1276 : - maybe_full <= do_enq - skip - node T_1278 = eq(empty, UInt<1>("h0")) - node T_1280 = and(UInt<1>("h0"), io.enq.valid) - node T_1281 = or(T_1278, T_1280) - io.deq.valid <= T_1281 - node T_1283 = eq(full, UInt<1>("h0")) - node T_1285 = and(UInt<1>("h0"), io.deq.ready) - node T_1286 = or(T_1283, T_1285) - io.enq.ready <= T_1286 - ram.T_1287.addr <= T_1117 - ram.T_1287.en <= UInt<1>("h1") - node T_1409 = mux(maybe_flow, io.enq.bits, ram.T_1287.data) - io.deq.bits <- T_1409 - node T_1531 = sub(T_1115, T_1117) - node ptr_diff = tail(T_1531, 1) - node T_1533 = and(maybe_full, ptr_match) - node T_1534 = cat(T_1533, ptr_diff) - io.count <= T_1534 - module Queue_3 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1327 - writer => T_1172 - ram.T_1327.addr is invalid - ram.T_1327.clk <= clk - ram.T_1327.en <= UInt<1>("h0") - ram.T_1172.addr is invalid - ram.T_1172.clk <= clk - ram.T_1172.en <= UInt<1>("h0") - ram.T_1172.data is invalid - ram.T_1172.mask.header.src <= UInt<1>("h0") - ram.T_1172.mask.header.dst <= UInt<1>("h0") - ram.T_1172.mask.payload.addr_beat <= UInt<1>("h0") - ram.T_1172.mask.payload.addr_block <= UInt<1>("h0") - ram.T_1172.mask.payload.client_xact_id <= UInt<1>("h0") - ram.T_1172.mask.payload.voluntary <= UInt<1>("h0") - ram.T_1172.mask.payload.r_type <= UInt<1>("h0") - ram.T_1172.mask.payload.data <= UInt<1>("h0") - reg T_1151 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1153 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_1151, T_1153) - node T_1158 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1158) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1164 = and(io.enq.ready, io.enq.valid) - node T_1166 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1164, T_1166) - node T_1168 = and(io.deq.ready, io.deq.valid) - node T_1170 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1168, T_1170) - when do_enq : - ram.T_1172.addr <= T_1151 - ram.T_1172.en <= UInt<1>("h1") - ram.T_1172.data <- io.enq.bits - ram.T_1172.mask.header.src <= UInt<1>("h1") - ram.T_1172.mask.header.dst <= UInt<1>("h1") - ram.T_1172.mask.payload.addr_beat <= UInt<1>("h1") - ram.T_1172.mask.payload.addr_block <= UInt<1>("h1") - ram.T_1172.mask.payload.client_xact_id <= UInt<1>("h1") - ram.T_1172.mask.payload.voluntary <= UInt<1>("h1") - ram.T_1172.mask.payload.r_type <= UInt<1>("h1") - ram.T_1172.mask.payload.data <= UInt<1>("h1") - node T_1299 = eq(T_1151, UInt<1>("h1")) - node T_1301 = and(UInt<1>("h0"), T_1299) - node T_1304 = add(T_1151, UInt<1>("h1")) - node T_1305 = tail(T_1304, 1) - node T_1306 = mux(T_1301, UInt<1>("h0"), T_1305) - T_1151 <= T_1306 - skip - when do_deq : - node T_1308 = eq(T_1153, UInt<1>("h1")) - node T_1310 = and(UInt<1>("h0"), T_1308) - node T_1313 = add(T_1153, UInt<1>("h1")) - node T_1314 = tail(T_1313, 1) - node T_1315 = mux(T_1310, UInt<1>("h0"), T_1314) - T_1153 <= T_1315 - skip - node T_1316 = neq(do_enq, do_deq) - when T_1316 : - maybe_full <= do_enq - skip - node T_1318 = eq(empty, UInt<1>("h0")) - node T_1320 = and(UInt<1>("h0"), io.enq.valid) - node T_1321 = or(T_1318, T_1320) - io.deq.valid <= T_1321 - node T_1323 = eq(full, UInt<1>("h0")) - node T_1325 = and(UInt<1>("h0"), io.deq.ready) - node T_1326 = or(T_1323, T_1325) - io.enq.ready <= T_1326 - ram.T_1327.addr <= T_1153 - ram.T_1327.en <= UInt<1>("h1") - node T_1453 = mux(maybe_flow, io.enq.bits, ram.T_1327.data) - io.deq.bits <- T_1453 - node T_1579 = sub(T_1151, T_1153) - node ptr_diff = tail(T_1579, 1) - node T_1581 = and(maybe_full, ptr_match) - node T_1582 = cat(T_1581, ptr_diff) - io.count <= T_1582 - module Queue_4 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1327 - writer => T_1172 - ram.T_1327.addr is invalid - ram.T_1327.clk <= clk - ram.T_1327.en <= UInt<1>("h0") - ram.T_1172.addr is invalid - ram.T_1172.clk <= clk - ram.T_1172.en <= UInt<1>("h0") - ram.T_1172.data is invalid - ram.T_1172.mask.header.src <= UInt<1>("h0") - ram.T_1172.mask.header.dst <= UInt<1>("h0") - ram.T_1172.mask.payload.addr_beat <= UInt<1>("h0") - ram.T_1172.mask.payload.client_xact_id <= UInt<1>("h0") - ram.T_1172.mask.payload.manager_xact_id <= UInt<1>("h0") - ram.T_1172.mask.payload.is_builtin_type <= UInt<1>("h0") - ram.T_1172.mask.payload.g_type <= UInt<1>("h0") - ram.T_1172.mask.payload.data <= UInt<1>("h0") - reg T_1151 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1153 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_1151, T_1153) - node T_1158 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1158) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1164 = and(io.enq.ready, io.enq.valid) - node T_1166 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1164, T_1166) - node T_1168 = and(io.deq.ready, io.deq.valid) - node T_1170 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1168, T_1170) - when do_enq : - ram.T_1172.addr <= T_1151 - ram.T_1172.en <= UInt<1>("h1") - ram.T_1172.data <- io.enq.bits - ram.T_1172.mask.header.src <= UInt<1>("h1") - ram.T_1172.mask.header.dst <= UInt<1>("h1") - ram.T_1172.mask.payload.addr_beat <= UInt<1>("h1") - ram.T_1172.mask.payload.client_xact_id <= UInt<1>("h1") - ram.T_1172.mask.payload.manager_xact_id <= UInt<1>("h1") - ram.T_1172.mask.payload.is_builtin_type <= UInt<1>("h1") - ram.T_1172.mask.payload.g_type <= UInt<1>("h1") - ram.T_1172.mask.payload.data <= UInt<1>("h1") - node T_1299 = eq(T_1151, UInt<1>("h1")) - node T_1301 = and(UInt<1>("h0"), T_1299) - node T_1304 = add(T_1151, UInt<1>("h1")) - node T_1305 = tail(T_1304, 1) - node T_1306 = mux(T_1301, UInt<1>("h0"), T_1305) - T_1151 <= T_1306 - skip - when do_deq : - node T_1308 = eq(T_1153, UInt<1>("h1")) - node T_1310 = and(UInt<1>("h0"), T_1308) - node T_1313 = add(T_1153, UInt<1>("h1")) - node T_1314 = tail(T_1313, 1) - node T_1315 = mux(T_1310, UInt<1>("h0"), T_1314) - T_1153 <= T_1315 - skip - node T_1316 = neq(do_enq, do_deq) - when T_1316 : - maybe_full <= do_enq - skip - node T_1318 = eq(empty, UInt<1>("h0")) - node T_1320 = and(UInt<1>("h0"), io.enq.valid) - node T_1321 = or(T_1318, T_1320) - io.deq.valid <= T_1321 - node T_1323 = eq(full, UInt<1>("h0")) - node T_1325 = and(UInt<1>("h0"), io.deq.ready) - node T_1326 = or(T_1323, T_1325) - io.enq.ready <= T_1326 - ram.T_1327.addr <= T_1153 - ram.T_1327.en <= UInt<1>("h1") - node T_1453 = mux(maybe_flow, io.enq.bits, ram.T_1327.data) - io.deq.bits <- T_1453 - node T_1579 = sub(T_1151, T_1153) - node ptr_diff = tail(T_1579, 1) - node T_1581 = and(maybe_full, ptr_match) - node T_1582 = cat(T_1581, ptr_diff) - io.count <= T_1582 - module Queue_5 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_1277 - writer => T_1127 - ram.T_1277.addr is invalid - ram.T_1277.clk <= clk - ram.T_1277.en <= UInt<1>("h0") - ram.T_1127.addr is invalid - ram.T_1127.clk <= clk - ram.T_1127.en <= UInt<1>("h0") - ram.T_1127.data is invalid - ram.T_1127.mask.header.src <= UInt<1>("h0") - ram.T_1127.mask.header.dst <= UInt<1>("h0") - ram.T_1127.mask.payload.manager_xact_id <= UInt<1>("h0") - reg T_1106 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1108 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_1106, T_1108) - node T_1113 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1113) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1119 = and(io.enq.ready, io.enq.valid) - node T_1121 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1119, T_1121) - node T_1123 = and(io.deq.ready, io.deq.valid) - node T_1125 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1123, T_1125) - when do_enq : - ram.T_1127.addr <= T_1106 - ram.T_1127.en <= UInt<1>("h1") - ram.T_1127.data <- io.enq.bits - ram.T_1127.mask.header.src <= UInt<1>("h1") - ram.T_1127.mask.header.dst <= UInt<1>("h1") - ram.T_1127.mask.payload.manager_xact_id <= UInt<1>("h1") - node T_1249 = eq(T_1106, UInt<1>("h1")) - node T_1251 = and(UInt<1>("h0"), T_1249) - node T_1254 = add(T_1106, UInt<1>("h1")) - node T_1255 = tail(T_1254, 1) - node T_1256 = mux(T_1251, UInt<1>("h0"), T_1255) - T_1106 <= T_1256 - skip - when do_deq : - node T_1258 = eq(T_1108, UInt<1>("h1")) - node T_1260 = and(UInt<1>("h0"), T_1258) - node T_1263 = add(T_1108, UInt<1>("h1")) - node T_1264 = tail(T_1263, 1) - node T_1265 = mux(T_1260, UInt<1>("h0"), T_1264) - T_1108 <= T_1265 - skip - node T_1266 = neq(do_enq, do_deq) - when T_1266 : - maybe_full <= do_enq - skip - node T_1268 = eq(empty, UInt<1>("h0")) - node T_1270 = and(UInt<1>("h0"), io.enq.valid) - node T_1271 = or(T_1268, T_1270) - io.deq.valid <= T_1271 - node T_1273 = eq(full, UInt<1>("h0")) - node T_1275 = and(UInt<1>("h0"), io.deq.ready) - node T_1276 = or(T_1273, T_1275) - io.enq.ready <= T_1276 - ram.T_1277.addr <= T_1108 - ram.T_1277.en <= UInt<1>("h1") - node T_1398 = mux(maybe_flow, io.enq.bits, ram.T_1277.data) - io.deq.bits <- T_1398 - node T_1519 = sub(T_1106, T_1108) - node ptr_diff = tail(T_1519, 1) - node T_1521 = and(maybe_full, ptr_match) - node T_1522 = cat(T_1521, ptr_diff) - io.count <= T_1522 - module TileLinkEnqueuer : - input clk : Clock - input reset : UInt<1> - output io : {flip client : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - inst T_7778 of Queue - T_7778.io is invalid - T_7778.clk <= clk - T_7778.reset <= reset - T_7778.io.enq.valid <= io.client.acquire.valid - T_7778.io.enq.bits <- io.client.acquire.bits - io.client.acquire.ready <= T_7778.io.enq.ready - io.manager.acquire <- T_7778.io.deq - inst T_7901 of Queue_2 - T_7901.io is invalid - T_7901.clk <= clk - T_7901.reset <= reset - T_7901.io.enq.valid <= io.manager.probe.valid - T_7901.io.enq.bits <- io.manager.probe.bits - io.manager.probe.ready <= T_7901.io.enq.ready - io.client.probe <- T_7901.io.deq - inst T_8028 of Queue_3 - T_8028.io is invalid - T_8028.clk <= clk - T_8028.reset <= reset - T_8028.io.enq.valid <= io.client.release.valid - T_8028.io.enq.bits <- io.client.release.bits - io.client.release.ready <= T_8028.io.enq.ready - io.manager.release <- T_8028.io.deq - inst T_8155 of Queue_4 - T_8155.io is invalid - T_8155.clk <= clk - T_8155.reset <= reset - T_8155.io.enq.valid <= io.manager.grant.valid - T_8155.io.enq.bits <- io.manager.grant.bits - io.manager.grant.ready <= T_8155.io.enq.ready - io.client.grant <- T_8155.io.deq - inst T_8277 of Queue_5 - T_8277.io is invalid - T_8277.clk <= clk - T_8277.reset <= reset - T_8277.io.enq.valid <= io.client.finish.valid - T_8277.io.enq.bits <- io.client.finish.bits - io.client.finish.ready <= T_8277.io.enq.ready - io.manager.finish <- T_8277.io.deq - module FinishUnit_7 : - input clk : Clock - input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h5") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h0"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h0") - T_1190[1] <= UInt<1>("h1") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h0"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h1"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h3")) - node T_1207 = and(UInt<1>("h0"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h1")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h0"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h0")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h0")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h5") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h0"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h0") - T_1334[1] <= UInt<1>("h1") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h0"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h1"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h0")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : { manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<1>("h1") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h0")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h0")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h0")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h0")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - module ClientTileLinkNetworkPort_6 : - input clk : Clock - input reset : UInt<1> - output io : {flip client : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - inst finisher of FinishUnit_7 - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<1>("h1") - acq_with_header.bits.header.dst <= UInt<1>("h0") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<1>("h1") - rel_with_header.bits.header.dst <= UInt<1>("h0") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill - module FinishUnit_16 : - input clk : Clock - input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h5") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h0"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h0") - T_1190[1] <= UInt<1>("h1") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h0"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h1"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h3")) - node T_1207 = and(UInt<1>("h0"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h1")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h0"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h0")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h0")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h5") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h0"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h0") - T_1334[1] <= UInt<1>("h1") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h0"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h1"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h0")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : { manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<2>("h2") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h0")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h0")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h0")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h0")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - module ClientTileLinkNetworkPort_15 : - input clk : Clock - input reset : UInt<1> - output io : {flip client : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - inst finisher of FinishUnit_16 - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<2>("h2") - acq_with_header.bits.header.dst <= UInt<1>("h0") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<2>("h2") - rel_with_header.bits.header.dst <= UInt<1>("h0") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill - module ManagerTileLinkNetworkPort : - input clk : Clock - input reset : UInt<1> - output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip network : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - wire T_6833 : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}} - T_6833 is invalid - T_6833.bits.payload <- io.manager.grant.bits - T_6833.bits.header.src <= UInt<1>("h0") - T_6833.bits.header.dst <= io.manager.grant.bits.client_id - T_6833.valid <= io.manager.grant.valid - io.manager.grant.ready <= T_6833.ready - io.network.grant <- T_6833 - wire T_7463 : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} - T_7463 is invalid - T_7463.bits.payload <- io.manager.probe.bits - T_7463.bits.header.src <= UInt<1>("h0") - T_7463.bits.header.dst <= io.manager.probe.bits.client_id - T_7463.valid <= io.manager.probe.valid - io.manager.probe.ready <= T_7463.ready - io.network.probe <- T_7463 - io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src - wire T_7778 : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} - T_7778 is invalid - T_7778.valid <= io.network.acquire.valid - T_7778.bits <- io.network.acquire.bits.payload - io.network.acquire.ready <= T_7778.ready - io.manager.acquire <- T_7778 - io.manager.release.bits.client_id <= io.network.release.bits.header.src - wire T_7906 : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - T_7906 is invalid - T_7906.valid <= io.network.release.valid - T_7906.bits <- io.network.release.bits.payload - io.network.release.ready <= T_7906.ready - io.manager.release <- T_7906 - wire T_8022 : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}} - T_8022 is invalid - T_8022.valid <= io.network.finish.valid - T_8022.bits <- io.network.finish.bits.payload - io.network.finish.ready <= T_8022.ready - io.manager.finish <- T_8022 - module Queue_25 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<1>} - io is invalid - mem ram : - data-type => { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - depth => 1 - write-latency => 1 - read-latency => 0 - reader => T_1309 - writer => T_1170 - ram.T_1309.addr is invalid - ram.T_1309.clk <= clk - ram.T_1309.en <= UInt<1>("h0") - ram.T_1170.addr is invalid - ram.T_1170.clk <= clk - ram.T_1170.en <= UInt<1>("h0") - ram.T_1170.data is invalid - ram.T_1170.mask.header.src <= UInt<1>("h0") - ram.T_1170.mask.header.dst <= UInt<1>("h0") - ram.T_1170.mask.payload.addr_beat <= UInt<1>("h0") - ram.T_1170.mask.payload.addr_block <= UInt<1>("h0") - ram.T_1170.mask.payload.client_xact_id <= UInt<1>("h0") - ram.T_1170.mask.payload.voluntary <= UInt<1>("h0") - ram.T_1170.mask.payload.r_type <= UInt<1>("h0") - ram.T_1170.mask.payload.data <= UInt<1>("h0") - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1156 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_1156) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1162 = and(io.enq.ready, io.enq.valid) - node T_1164 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_1162, T_1164) - node T_1166 = and(io.deq.ready, io.deq.valid) - node T_1168 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_1166, T_1168) - when do_enq : - ram.T_1170.addr <= UInt<1>("h0") - ram.T_1170.en <= UInt<1>("h1") - ram.T_1170.data <- io.enq.bits - ram.T_1170.mask.header.src <= UInt<1>("h1") - ram.T_1170.mask.header.dst <= UInt<1>("h1") - ram.T_1170.mask.payload.addr_beat <= UInt<1>("h1") - ram.T_1170.mask.payload.addr_block <= UInt<1>("h1") - ram.T_1170.mask.payload.client_xact_id <= UInt<1>("h1") - ram.T_1170.mask.payload.voluntary <= UInt<1>("h1") - ram.T_1170.mask.payload.r_type <= UInt<1>("h1") - ram.T_1170.mask.payload.data <= UInt<1>("h1") - skip - when do_deq : - skip - node T_1298 = neq(do_enq, do_deq) - when T_1298 : - maybe_full <= do_enq - skip - node T_1300 = eq(empty, UInt<1>("h0")) - node T_1302 = and(UInt<1>("h0"), io.enq.valid) - node T_1303 = or(T_1300, T_1302) - io.deq.valid <= T_1303 - node T_1305 = eq(full, UInt<1>("h0")) - node T_1307 = and(UInt<1>("h0"), io.deq.ready) - node T_1308 = or(T_1305, T_1307) - io.enq.ready <= T_1308 - ram.T_1309.addr <= UInt<1>("h0") - ram.T_1309.en <= UInt<1>("h1") - node T_1435 = mux(maybe_flow, io.enq.bits, ram.T_1309.data) - io.deq.bits <- T_1435 - node T_1561 = sub(UInt<1>("h0"), UInt<1>("h0")) - node ptr_diff = tail(T_1561, 1) - node T_1563 = and(maybe_full, ptr_match) - node T_1564 = cat(T_1563, ptr_diff) - io.count <= T_1564 - module TileLinkEnqueuer_24 : - input clk : Clock - input reset : UInt<1> - output io : {flip client : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io is invalid - io.manager.acquire <- io.client.acquire - io.client.probe <- io.manager.probe - inst T_7777 of Queue_25 - T_7777.io is invalid - T_7777.clk <= clk - T_7777.reset <= reset - T_7777.io.enq.valid <= io.client.release.valid - T_7777.io.enq.bits <- io.client.release.bits - io.client.release.ready <= T_7777.io.enq.ready - io.manager.release <- T_7777.io.deq - io.client.grant <- io.manager.grant - io.manager.finish <- io.client.finish - module LockingRRArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, chosen : UInt<2>} - io is invalid - reg T_3348 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_3350 : UInt, clk with : - reset => (reset, UInt<2>("h2")) - wire T_3352 : UInt<2> - T_3352 is invalid - io.out.valid <= io.in[T_3352].valid - io.out.bits <- io.in[T_3352].bits - io.chosen <= T_3352 - io.in[T_3352].ready <= UInt<1>("h0") - reg last_grant : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_4128 = gt(UInt<1>("h0"), last_grant) - node T_4129 = and(io.in[0].valid, T_4128) - node T_4131 = gt(UInt<1>("h1"), last_grant) - node T_4132 = and(io.in[1].valid, T_4131) - node T_4134 = gt(UInt<2>("h2"), last_grant) - node T_4135 = and(io.in[2].valid, T_4134) - node T_4138 = or(UInt<1>("h0"), T_4129) - node T_4140 = eq(T_4138, UInt<1>("h0")) - node T_4142 = or(UInt<1>("h0"), T_4129) - node T_4143 = or(T_4142, T_4132) - node T_4145 = eq(T_4143, UInt<1>("h0")) - node T_4147 = or(UInt<1>("h0"), T_4129) - node T_4148 = or(T_4147, T_4132) - node T_4149 = or(T_4148, T_4135) - node T_4151 = eq(T_4149, UInt<1>("h0")) - node T_4153 = or(UInt<1>("h0"), T_4129) - node T_4154 = or(T_4153, T_4132) - node T_4155 = or(T_4154, T_4135) - node T_4156 = or(T_4155, io.in[0].valid) - node T_4158 = eq(T_4156, UInt<1>("h0")) - node T_4160 = or(UInt<1>("h0"), T_4129) - node T_4161 = or(T_4160, T_4132) - node T_4162 = or(T_4161, T_4135) - node T_4163 = or(T_4162, io.in[0].valid) - node T_4164 = or(T_4163, io.in[1].valid) - node T_4166 = eq(T_4164, UInt<1>("h0")) - node T_4168 = gt(UInt<1>("h0"), last_grant) - node T_4169 = and(UInt<1>("h1"), T_4168) - node T_4170 = or(T_4169, T_4151) - node T_4172 = gt(UInt<1>("h1"), last_grant) - node T_4173 = and(T_4140, T_4172) - node T_4174 = or(T_4173, T_4158) - node T_4176 = gt(UInt<2>("h2"), last_grant) - node T_4177 = and(T_4145, T_4176) - node T_4178 = or(T_4177, T_4166) - node T_4180 = eq(T_3350, UInt<1>("h0")) - node T_4181 = mux(T_3348, T_4180, T_4170) - node T_4182 = and(T_4181, io.out.ready) - io.in[0].ready <= T_4182 - node T_4184 = eq(T_3350, UInt<1>("h1")) - node T_4185 = mux(T_3348, T_4184, T_4174) - node T_4186 = and(T_4185, io.out.ready) - io.in[1].ready <= T_4186 - node T_4188 = eq(T_3350, UInt<2>("h2")) - node T_4189 = mux(T_3348, T_4188, T_4178) - node T_4190 = and(T_4189, io.out.ready) - io.in[2].ready <= T_4190 - reg T_4192 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_4194 = add(T_4192, UInt<1>("h1")) - node T_4195 = tail(T_4194, 1) - node T_4196 = and(io.out.ready, io.out.valid) - when T_4196 : - node T_4198 = and(UInt<1>("h1"), io.out.bits.payload.is_builtin_type) - wire T_4201 : UInt<3>[1] - T_4201[0] <= UInt<3>("h3") - node T_4204 = eq(T_4201[0], io.out.bits.payload.a_type) - node T_4206 = or(UInt<1>("h0"), T_4204) - node T_4207 = and(T_4198, T_4206) - when T_4207 : - T_4192 <= T_4195 - node T_4209 = eq(T_3348, UInt<1>("h0")) - when T_4209 : - T_3348 <= UInt<1>("h1") - node T_4211 = and(io.in[0].ready, io.in[0].valid) - node T_4212 = and(io.in[1].ready, io.in[1].valid) - node T_4213 = and(io.in[2].ready, io.in[2].valid) - wire T_4215 : UInt<1>[3] - T_4215[0] <= T_4211 - T_4215[1] <= T_4212 - T_4215[2] <= T_4213 - node T_4223 = mux(T_4215[1], UInt<1>("h1"), UInt<2>("h2")) - node T_4224 = mux(T_4215[0], UInt<1>("h0"), T_4223) - T_3350 <= T_4224 - skip - skip - node T_4226 = eq(T_4195, UInt<1>("h0")) - when T_4226 : - T_3348 <= UInt<1>("h0") - skip - skip - node T_4230 = mux(io.in[1].valid, UInt<1>("h1"), UInt<2>("h2")) - node T_4232 = mux(io.in[0].valid, UInt<1>("h0"), T_4230) - node T_4234 = gt(UInt<2>("h2"), last_grant) - node T_4235 = and(io.in[2].valid, T_4234) - node T_4237 = mux(T_4235, UInt<2>("h2"), T_4232) - node T_4239 = gt(UInt<1>("h1"), last_grant) - node T_4240 = and(io.in[1].valid, T_4239) - node choose = mux(T_4240, UInt<1>("h1"), T_4237) - node T_4243 = mux(T_3348, T_3350, choose) - T_3352 <= T_4243 - node T_4244 = and(io.out.ready, io.out.valid) - when T_4244 : - last_grant <= T_3352 - skip - module LockingRRArbiter_26 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, chosen : UInt<2>} - io is invalid - reg T_3322 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_3324 : UInt, clk with : - reset => (reset, UInt<2>("h2")) - wire T_3326 : UInt<2> - T_3326 is invalid - io.out.valid <= io.in[T_3326].valid - io.out.bits <- io.in[T_3326].bits - io.chosen <= T_3326 - io.in[T_3326].ready <= UInt<1>("h0") - reg last_grant : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_4096 = gt(UInt<1>("h0"), last_grant) - node T_4097 = and(io.in[0].valid, T_4096) - node T_4099 = gt(UInt<1>("h1"), last_grant) - node T_4100 = and(io.in[1].valid, T_4099) - node T_4102 = gt(UInt<2>("h2"), last_grant) - node T_4103 = and(io.in[2].valid, T_4102) - node T_4106 = or(UInt<1>("h0"), T_4097) - node T_4108 = eq(T_4106, UInt<1>("h0")) - node T_4110 = or(UInt<1>("h0"), T_4097) - node T_4111 = or(T_4110, T_4100) - node T_4113 = eq(T_4111, UInt<1>("h0")) - node T_4115 = or(UInt<1>("h0"), T_4097) - node T_4116 = or(T_4115, T_4100) - node T_4117 = or(T_4116, T_4103) - node T_4119 = eq(T_4117, UInt<1>("h0")) - node T_4121 = or(UInt<1>("h0"), T_4097) - node T_4122 = or(T_4121, T_4100) - node T_4123 = or(T_4122, T_4103) - node T_4124 = or(T_4123, io.in[0].valid) - node T_4126 = eq(T_4124, UInt<1>("h0")) - node T_4128 = or(UInt<1>("h0"), T_4097) - node T_4129 = or(T_4128, T_4100) - node T_4130 = or(T_4129, T_4103) - node T_4131 = or(T_4130, io.in[0].valid) - node T_4132 = or(T_4131, io.in[1].valid) - node T_4134 = eq(T_4132, UInt<1>("h0")) - node T_4136 = gt(UInt<1>("h0"), last_grant) - node T_4137 = and(UInt<1>("h1"), T_4136) - node T_4138 = or(T_4137, T_4119) - node T_4140 = gt(UInt<1>("h1"), last_grant) - node T_4141 = and(T_4108, T_4140) - node T_4142 = or(T_4141, T_4126) - node T_4144 = gt(UInt<2>("h2"), last_grant) - node T_4145 = and(T_4113, T_4144) - node T_4146 = or(T_4145, T_4134) - node T_4148 = eq(T_3324, UInt<1>("h0")) - node T_4149 = mux(T_3322, T_4148, T_4138) - node T_4150 = and(T_4149, io.out.ready) - io.in[0].ready <= T_4150 - node T_4152 = eq(T_3324, UInt<1>("h1")) - node T_4153 = mux(T_3322, T_4152, T_4142) - node T_4154 = and(T_4153, io.out.ready) - io.in[1].ready <= T_4154 - node T_4156 = eq(T_3324, UInt<2>("h2")) - node T_4157 = mux(T_3322, T_4156, T_4146) - node T_4158 = and(T_4157, io.out.ready) - io.in[2].ready <= T_4158 - reg T_4160 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_4162 = add(T_4160, UInt<1>("h1")) - node T_4163 = tail(T_4162, 1) - node T_4164 = and(io.out.ready, io.out.valid) - when T_4164 : - wire T_4167 : UInt<2>[3] - T_4167[0] <= UInt<1>("h0") - T_4167[1] <= UInt<1>("h1") - T_4167[2] <= UInt<2>("h2") - node T_4172 = eq(T_4167[0], io.out.bits.payload.r_type) - node T_4173 = eq(T_4167[1], io.out.bits.payload.r_type) - node T_4174 = eq(T_4167[2], io.out.bits.payload.r_type) - node T_4176 = or(UInt<1>("h0"), T_4172) - node T_4177 = or(T_4176, T_4173) - node T_4178 = or(T_4177, T_4174) - node T_4179 = and(UInt<1>("h1"), T_4178) - when T_4179 : - T_4160 <= T_4163 - node T_4181 = eq(T_3322, UInt<1>("h0")) - when T_4181 : - T_3322 <= UInt<1>("h1") - node T_4183 = and(io.in[0].ready, io.in[0].valid) - node T_4184 = and(io.in[1].ready, io.in[1].valid) - node T_4185 = and(io.in[2].ready, io.in[2].valid) - wire T_4187 : UInt<1>[3] - T_4187[0] <= T_4183 - T_4187[1] <= T_4184 - T_4187[2] <= T_4185 - node T_4195 = mux(T_4187[1], UInt<1>("h1"), UInt<2>("h2")) - node T_4196 = mux(T_4187[0], UInt<1>("h0"), T_4195) - T_3324 <= T_4196 - skip - skip - node T_4198 = eq(T_4163, UInt<1>("h0")) - when T_4198 : - T_3322 <= UInt<1>("h0") - skip - skip - node T_4202 = mux(io.in[1].valid, UInt<1>("h1"), UInt<2>("h2")) - node T_4204 = mux(io.in[0].valid, UInt<1>("h0"), T_4202) - node T_4206 = gt(UInt<2>("h2"), last_grant) - node T_4207 = and(io.in[2].valid, T_4206) - node T_4209 = mux(T_4207, UInt<2>("h2"), T_4204) - node T_4211 = gt(UInt<1>("h1"), last_grant) - node T_4212 = and(io.in[1].valid, T_4211) - node choose = mux(T_4212, UInt<1>("h1"), T_4209) - node T_4215 = mux(T_3322, T_3324, choose) - T_3326 <= T_4215 - node T_4216 = and(io.out.ready, io.out.valid) - when T_4216 : - last_grant <= T_3326 - skip - module RRArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, chosen : UInt<2>} - io is invalid - wire T_3194 : UInt<2> - T_3194 is invalid - io.out.valid <= io.in[T_3194].valid - io.out.bits <- io.in[T_3194].bits - io.chosen <= T_3194 - io.in[T_3194].ready <= UInt<1>("h0") - reg T_3933 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_3934 = gt(UInt<1>("h0"), T_3933) - node T_3935 = and(io.in[0].valid, T_3934) - node T_3937 = gt(UInt<1>("h1"), T_3933) - node T_3938 = and(io.in[1].valid, T_3937) - node T_3940 = gt(UInt<2>("h2"), T_3933) - node T_3941 = and(io.in[2].valid, T_3940) - node T_3944 = or(UInt<1>("h0"), T_3935) - node T_3946 = eq(T_3944, UInt<1>("h0")) - node T_3948 = or(UInt<1>("h0"), T_3935) - node T_3949 = or(T_3948, T_3938) - node T_3951 = eq(T_3949, UInt<1>("h0")) - node T_3953 = or(UInt<1>("h0"), T_3935) - node T_3954 = or(T_3953, T_3938) - node T_3955 = or(T_3954, T_3941) - node T_3957 = eq(T_3955, UInt<1>("h0")) - node T_3959 = or(UInt<1>("h0"), T_3935) - node T_3960 = or(T_3959, T_3938) - node T_3961 = or(T_3960, T_3941) - node T_3962 = or(T_3961, io.in[0].valid) - node T_3964 = eq(T_3962, UInt<1>("h0")) - node T_3966 = or(UInt<1>("h0"), T_3935) - node T_3967 = or(T_3966, T_3938) - node T_3968 = or(T_3967, T_3941) - node T_3969 = or(T_3968, io.in[0].valid) - node T_3970 = or(T_3969, io.in[1].valid) - node T_3972 = eq(T_3970, UInt<1>("h0")) - node T_3974 = gt(UInt<1>("h0"), T_3933) - node T_3975 = and(UInt<1>("h1"), T_3974) - node T_3976 = or(T_3975, T_3957) - node T_3978 = gt(UInt<1>("h1"), T_3933) - node T_3979 = and(T_3946, T_3978) - node T_3980 = or(T_3979, T_3964) - node T_3982 = gt(UInt<2>("h2"), T_3933) - node T_3983 = and(T_3951, T_3982) - node T_3984 = or(T_3983, T_3972) - node T_3986 = eq(UInt<2>("h2"), UInt<1>("h0")) - node T_3987 = mux(UInt<1>("h0"), T_3986, T_3976) - node T_3988 = and(T_3987, io.out.ready) - io.in[0].ready <= T_3988 - node T_3990 = eq(UInt<2>("h2"), UInt<1>("h1")) - node T_3991 = mux(UInt<1>("h0"), T_3990, T_3980) - node T_3992 = and(T_3991, io.out.ready) - io.in[1].ready <= T_3992 - node T_3994 = eq(UInt<2>("h2"), UInt<2>("h2")) - node T_3995 = mux(UInt<1>("h0"), T_3994, T_3984) - node T_3996 = and(T_3995, io.out.ready) - io.in[2].ready <= T_3996 - node T_3999 = mux(io.in[1].valid, UInt<1>("h1"), UInt<2>("h2")) - node T_4001 = mux(io.in[0].valid, UInt<1>("h0"), T_3999) - node T_4003 = gt(UInt<2>("h2"), T_3933) - node T_4004 = and(io.in[2].valid, T_4003) - node T_4006 = mux(T_4004, UInt<2>("h2"), T_4001) - node T_4008 = gt(UInt<1>("h1"), T_3933) - node T_4009 = and(io.in[1].valid, T_4008) - node T_4011 = mux(T_4009, UInt<1>("h1"), T_4006) - node T_4012 = mux(UInt<1>("h0"), UInt<2>("h2"), T_4011) - T_3194 <= T_4012 - node T_4013 = and(io.out.ready, io.out.valid) - when T_4013 : - T_3933 <= T_3194 - skip - module RocketChipTileLinkArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip clients : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}[1]} - io is invalid - inst T_11386 of ClientTileLinkNetworkPort - T_11386.io is invalid - T_11386.clk <= clk - T_11386.reset <= reset - inst T_11387 of TileLinkEnqueuer - T_11387.io is invalid - T_11387.clk <= clk - T_11387.reset <= reset - T_11386.io.client <- io.clients[0] - T_11387.io.client <- T_11386.io.network - inst T_11388 of ClientTileLinkNetworkPort_6 - T_11388.io is invalid - T_11388.clk <= clk - T_11388.reset <= reset - inst T_11389 of TileLinkEnqueuer - T_11389.io is invalid - T_11389.clk <= clk - T_11389.reset <= reset - T_11388.io.client <- io.clients[1] - T_11389.io.client <- T_11388.io.network - inst T_11390 of ClientTileLinkNetworkPort_15 - T_11390.io is invalid - T_11390.clk <= clk - T_11390.reset <= reset - inst T_11391 of TileLinkEnqueuer - T_11391.io is invalid - T_11391.clk <= clk - T_11391.reset <= reset - T_11390.io.client <- io.clients[2] - T_11391.io.client <- T_11390.io.network - inst T_11392 of ManagerTileLinkNetworkPort - T_11392.io is invalid - T_11392.clk <= clk - T_11392.reset <= reset - inst T_11393 of TileLinkEnqueuer_24 - T_11393.io is invalid - T_11393.clk <= clk - T_11393.reset <= reset - T_11392.io.manager <- io.managers[0] - T_11392.io.network <- T_11393.io.manager - inst T_11394 of LockingRRArbiter - T_11394.io is invalid - T_11394.clk <= clk - T_11394.reset <= reset - T_11394.io.in[0].valid <= T_11387.io.manager.acquire.valid - T_11394.io.in[0].bits <- T_11387.io.manager.acquire.bits - T_11394.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.acquire.bits.payload.client_xact_id - T_11387.io.manager.acquire.ready <= T_11394.io.in[0].ready - T_11394.io.in[1].valid <= T_11389.io.manager.acquire.valid - T_11394.io.in[1].bits <- T_11389.io.manager.acquire.bits - T_11394.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.acquire.bits.payload.client_xact_id - T_11389.io.manager.acquire.ready <= T_11394.io.in[1].ready - T_11394.io.in[2].valid <= T_11391.io.manager.acquire.valid - T_11394.io.in[2].bits <- T_11391.io.manager.acquire.bits - T_11394.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.acquire.bits.payload.client_xact_id - T_11391.io.manager.acquire.ready <= T_11394.io.in[2].ready - T_11393.io.client.acquire <- T_11394.io.out - inst T_11395 of LockingRRArbiter_26 - T_11395.io is invalid - T_11395.clk <= clk - T_11395.reset <= reset - T_11395.io.in[0].valid <= T_11387.io.manager.release.valid - T_11395.io.in[0].bits <- T_11387.io.manager.release.bits - T_11395.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.release.bits.payload.client_xact_id - T_11387.io.manager.release.ready <= T_11395.io.in[0].ready - T_11395.io.in[1].valid <= T_11389.io.manager.release.valid - T_11395.io.in[1].bits <- T_11389.io.manager.release.bits - T_11395.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.release.bits.payload.client_xact_id - T_11389.io.manager.release.ready <= T_11395.io.in[1].ready - T_11395.io.in[2].valid <= T_11391.io.manager.release.valid - T_11395.io.in[2].bits <- T_11391.io.manager.release.bits - T_11395.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.release.bits.payload.client_xact_id - T_11391.io.manager.release.ready <= T_11395.io.in[2].ready - T_11393.io.client.release <- T_11395.io.out - inst T_11396 of RRArbiter - T_11396.io is invalid - T_11396.clk <= clk - T_11396.reset <= reset - T_11396.io.in[0] <- T_11387.io.manager.finish - T_11396.io.in[1] <- T_11389.io.manager.finish - T_11396.io.in[2] <- T_11391.io.manager.finish - T_11393.io.client.finish <- T_11396.io.out - T_11393.io.client.probe.ready <= UInt<1>("h0") - T_11387.io.manager.probe.valid <= UInt<1>("h0") - node T_11400 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h0")) - when T_11400 : - T_11387.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11387.io.manager.probe.ready - skip - T_11387.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11389.io.manager.probe.valid <= UInt<1>("h0") - node T_11403 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h1")) - when T_11403 : - T_11389.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11389.io.manager.probe.ready - skip - T_11389.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11391.io.manager.probe.valid <= UInt<1>("h0") - node T_11406 = eq(T_11393.io.client.probe.bits.header.dst, UInt<2>("h2")) - when T_11406 : - T_11391.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11391.io.manager.probe.ready - skip - T_11391.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11393.io.client.grant.ready <= UInt<1>("h0") - T_11387.io.manager.grant.valid <= UInt<1>("h0") - node T_11410 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h0")) - when T_11410 : - T_11387.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11387.io.manager.grant.ready - skip - T_11387.io.manager.grant.bits <- T_11393.io.client.grant.bits - T_11389.io.manager.grant.valid <= UInt<1>("h0") - node T_11413 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h1")) - when T_11413 : - T_11389.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11389.io.manager.grant.ready - skip - T_11389.io.manager.grant.bits <- T_11393.io.client.grant.bits - T_11391.io.manager.grant.valid <= UInt<1>("h0") - node T_11416 = eq(T_11393.io.client.grant.bits.header.dst, UInt<2>("h2")) - when T_11416 : - T_11391.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11391.io.manager.grant.ready - skip - T_11391.io.manager.grant.bits <- T_11393.io.client.grant.bits - module BroadcastVoluntaryReleaseTracker : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - reg collect_irel_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg irel_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_302 = and(io.inner.release.ready, io.inner.release.valid) - wire T_306 : UInt<2>[3] - T_306[0] <= UInt<1>("h0") - T_306[1] <= UInt<1>("h1") - T_306[2] <= UInt<2>("h2") - node T_311 = eq(T_306[0], io.inner.release.bits.r_type) - node T_312 = eq(T_306[1], io.inner.release.bits.r_type) - node T_313 = eq(T_306[2], io.inner.release.bits.r_type) - node T_315 = or(UInt<1>("h0"), T_311) - node T_316 = or(T_315, T_312) - node T_317 = or(T_316, T_313) - node T_318 = and(UInt<1>("h1"), T_317) - node T_319 = and(T_302, T_318) - reg T_321 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_319 : - node T_323 = eq(T_321, UInt<2>("h3")) - node T_325 = and(UInt<1>("h0"), T_323) - node T_328 = add(T_321, UInt<1>("h1")) - node T_329 = tail(T_328, 1) - node T_330 = mux(T_325, UInt<1>("h0"), T_329) - T_321 <= T_330 - skip - node T_331 = and(T_319, T_323) - node T_332 = mux(T_318, T_321, UInt<1>("h0")) - node irel_data_done = mux(T_318, T_331, T_302) - node T_335 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_337 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_340 : UInt<3>[1] - T_340[0] <= UInt<3>("h3") - node T_343 = eq(T_340[0], io.outer.acquire.bits.a_type) - node T_345 = or(UInt<1>("h0"), T_343) - node T_346 = and(T_337, T_345) - node T_347 = and(T_335, T_346) - reg T_349 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_347 : - node T_351 = eq(T_349, UInt<2>("h3")) - node T_353 = and(UInt<1>("h0"), T_351) - node T_356 = add(T_349, UInt<1>("h1")) - node T_357 = tail(T_356, 1) - node T_358 = mux(T_353, UInt<1>("h0"), T_357) - T_349 <= T_358 - skip - node T_359 = and(T_347, T_351) - node oacq_data_cnt = mux(T_346, T_349, UInt<1>("h0")) - node oacq_data_done = mux(T_346, T_359, T_335) - io.has_acquire_conflict <= UInt<1>("h0") - io.has_release_match <= io.inner.release.bits.voluntary - io.has_acquire_match <= UInt<1>("h0") - io.outer.acquire.valid <= UInt<1>("h0") - io.outer.grant.ready <= UInt<1>("h0") - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.grant.valid <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - wire T_384 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_384 is invalid - T_384.client_id <= xact.client_id - T_384.is_builtin_type <= UInt<1>("h1") - T_384.g_type <= UInt<3>("h0") - T_384.client_xact_id <= xact.client_xact_id - T_384.manager_xact_id <= UInt<1>("h0") - T_384.addr_beat <= UInt<1>("h0") - T_384.data <= UInt<1>("h0") - io.inner.grant.bits <- T_384 - node T_397 = asUInt(asSInt(UInt<16>("hffff"))) - node T_403 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_404 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_405 = cat(T_403, T_404) - node T_407 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_408 = cat(UInt<3>("h7"), T_407) - node T_410 = cat(T_397, UInt<1>("h1")) - node T_412 = cat(T_397, UInt<1>("h1")) - node T_414 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_415 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_416 = cat(T_414, T_415) - node T_418 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_420 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_421 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_422 = mux(T_421, T_420, UInt<1>("h0")) - node T_423 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_424 = mux(T_423, T_418, T_422) - node T_425 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_426 = mux(T_425, T_416, T_424) - node T_427 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_428 = mux(T_427, T_412, T_426) - node T_429 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_430 = mux(T_429, T_410, T_428) - node T_431 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_432 = mux(T_431, T_408, T_430) - node T_433 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_434 = mux(T_433, T_405, T_432) - wire T_443 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_443 is invalid - T_443.is_builtin_type <= UInt<1>("h1") - T_443.a_type <= UInt<3>("h3") - T_443.client_xact_id <= UInt<1>("h0") - T_443.addr_block <= xact.addr_block - T_443.addr_beat <= oacq_data_cnt - T_443.data <= xact.data_buffer[oacq_data_cnt] - T_443.union <= T_434 - io.outer.acquire.bits <- T_443 - when collect_irel_data : - io.inner.release.ready <= UInt<1>("h1") - when io.inner.release.valid : - xact.data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data - node T_455 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) - node T_456 = or(irel_data_valid, T_455) - node T_457 = not(irel_data_valid) - node T_458 = or(T_457, T_455) - node T_459 = not(T_458) - node T_460 = mux(UInt<1>("h1"), T_456, T_459) - irel_data_valid <= T_460 - skip - when irel_data_done : - collect_irel_data <= UInt<1>("h0") - skip - skip - node T_462 = eq(UInt<1>("h0"), state) - when T_462 : - io.inner.release.ready <= UInt<1>("h1") - when io.inner.release.valid : - xact <- io.inner.release.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.release.bits.data - wire T_468 : UInt<2>[3] - T_468[0] <= UInt<1>("h0") - T_468[1] <= UInt<1>("h1") - T_468[2] <= UInt<2>("h2") - node T_473 = eq(T_468[0], io.inner.release.bits.r_type) - node T_474 = eq(T_468[1], io.inner.release.bits.r_type) - node T_475 = eq(T_468[2], io.inner.release.bits.r_type) - node T_477 = or(UInt<1>("h0"), T_473) - node T_478 = or(T_477, T_474) - node T_479 = or(T_478, T_475) - node T_480 = and(UInt<1>("h1"), T_479) - collect_irel_data <= T_480 - wire T_482 : UInt<2>[3] - T_482[0] <= UInt<1>("h0") - T_482[1] <= UInt<1>("h1") - T_482[2] <= UInt<2>("h2") - node T_487 = eq(T_482[0], io.inner.release.bits.r_type) - node T_488 = eq(T_482[1], io.inner.release.bits.r_type) - node T_489 = eq(T_482[2], io.inner.release.bits.r_type) - node T_491 = or(UInt<1>("h0"), T_487) - node T_492 = or(T_491, T_488) - node T_493 = or(T_492, T_489) - node T_494 = dshl(T_493, io.inner.release.bits.addr_beat) - irel_data_valid <= T_494 - wire T_496 : UInt<2>[3] - T_496[0] <= UInt<1>("h0") - T_496[1] <= UInt<1>("h1") - T_496[2] <= UInt<2>("h2") - node T_501 = eq(T_496[0], io.inner.release.bits.r_type) - node T_502 = eq(T_496[1], io.inner.release.bits.r_type) - node T_503 = eq(T_496[2], io.inner.release.bits.r_type) - node T_505 = or(UInt<1>("h0"), T_501) - node T_506 = or(T_505, T_502) - node T_507 = or(T_506, T_503) - node T_510 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_511 = mux(T_510, UInt<2>("h3"), UInt<1>("h0")) - node T_512 = mux(T_507, UInt<1>("h1"), T_511) - state <= T_512 - skip - skip - node T_513 = eq(UInt<1>("h1"), state) - when T_513 : - node T_515 = eq(collect_irel_data, UInt<1>("h0")) - node T_516 = dshr(irel_data_valid, oacq_data_cnt) - node T_517 = bits(T_516, 0, 0) - node T_518 = or(T_515, T_517) - io.outer.acquire.valid <= T_518 - when oacq_data_done : - state <= UInt<2>("h2") - skip - skip - node T_519 = eq(UInt<2>("h2"), state) - when T_519 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - node T_520 = and(io.inner.grant.ready, io.inner.grant.valid) - when T_520 : - node T_523 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_525 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_526 = and(io.inner.grant.bits.is_builtin_type, T_525) - node T_528 = eq(T_526, UInt<1>("h0")) - node T_529 = and(T_523, T_528) - node T_530 = mux(T_529, UInt<2>("h3"), UInt<1>("h0")) - state <= T_530 - skip - skip - node T_531 = eq(UInt<2>("h3"), state) - when T_531 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<1>("h1") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<1>("h1") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<1>("h1") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<1>("h1") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<1>("h1") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<1>("h1") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<1>("h1") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_27 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<2>("h2") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<2>("h2") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<2>("h2") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<2>("h2") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<2>("h2") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<2>("h2") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<2>("h2") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_28 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<2>("h3") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<2>("h3") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<2>("h3") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<2>("h3") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<2>("h3") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<2>("h3") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<2>("h3") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_29 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h4") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<3>("h4") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<3>("h4") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<3>("h4") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<3>("h4") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<3>("h4") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h4") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_30 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h5") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<3>("h5") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<3>("h5") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<3>("h5") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<3>("h5") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<3>("h5") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h5") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_31 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h6") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<3>("h6") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<3>("h6") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<3>("h6") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<3>("h6") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<3>("h6") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h6") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module BroadcastAcquireTracker_32 : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg xact : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), xact) - wire coh : { sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h0") - node T_303 = neq(state, UInt<1>("h0")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h4") - T_309[1] <= UInt<3>("h5") - T_309[2] <= UInt<3>("h6") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h0"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h0")) - node T_325 = eq(reset, UInt<1>("h0")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h0")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h0")) - when T_329 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg release_count : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg pending_probes : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h1"))) - node T_344 = dshl(UInt<1>("h1"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h0"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg iacq_data_valid : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h3") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h0"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h3")) - node T_375 = and(UInt<1>("h0"), T_373) - node T_378 = add(T_371, UInt<1>("h1")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h0"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h0")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h0") - T_388[1] <= UInt<1>("h1") - T_388[2] <= UInt<2>("h2") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h0"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h1"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h3")) - node T_407 = and(UInt<1>("h0"), T_405) - node T_410 = add(T_403, UInt<1>("h1")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h0"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h0")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h5") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h0"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h0") - T_428[1] <= UInt<1>("h1") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h0"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h1"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h3")) - node T_445 = and(UInt<1>("h0"), T_443) - node T_448 = add(T_441, UInt<1>("h1")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h0"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h0")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h3") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h0"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h3")) - node T_473 = and(UInt<1>("h0"), T_471) - node T_476 = add(T_469, UInt<1>("h1")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h0"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h0")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h5") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h0"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h0") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h0"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h1"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h3")) - node T_508 = and(UInt<1>("h0"), T_506) - node T_511 = add(T_504, UInt<1>("h1")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h0"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h0")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h2") - T_523[1] <= UInt<3>("h3") - T_523[2] <= UInt<3>("h4") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h0"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h2") - T_540[1] <= UInt<3>("h3") - T_540[2] <= UInt<3>("h4") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h0"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h5") - T_556[1] <= UInt<3>("h4") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h0"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h0") - T_566[1] <= UInt<1>("h1") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h0"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h6"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h1"), UInt<3>("h3")) - node T_596 = eq(UInt<3>("h5"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h1"), T_595) - node T_598 = eq(UInt<3>("h4"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h4"), T_597) - node T_600 = eq(UInt<3>("h3"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h3"), T_599) - node T_602 = eq(UInt<3>("h2"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h3"), T_601) - node T_604 = eq(UInt<3>("h1"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h5"), T_603) - node T_606 = eq(UInt<3>("h0"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h4"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h0")) - node T_611 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_612 = mux(T_611, UInt<1>("h0"), UInt<1>("h1")) - node T_613 = mux(T_608, T_612, UInt<1>("h1")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h7") - T_623.addr_beat <= UInt<1>("h0") - T_623.data <= UInt<1>("h0") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h5") - T_634[1] <= UInt<3>("h4") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h0"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h0") - T_644[1] <= UInt<1>("h1") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h0"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h2") - T_658[1] <= UInt<3>("h0") - T_658[2] <= UInt<3>("h4") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h0"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h0")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h0")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h1")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("hffff"))) - node T_695 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_696 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_700 = cat(UInt<3>("h7"), T_699) - node T_702 = cat(T_689, UInt<1>("h1")) - node T_704 = cat(T_689, UInt<1>("h1")) - node T_706 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_707 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_712 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_713 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_714 = mux(T_713, T_712, UInt<1>("h0")) - node T_715 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h1") - oacq_probe.a_type <= UInt<3>("h3") - oacq_probe.client_xact_id <= UInt<3>("h7") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h1"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h4")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h0"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h0"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h3")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h2")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h0")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_789 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_793 = cat(UInt<3>("h7"), T_792) - node T_795 = cat(T_780, UInt<1>("h1")) - node T_797 = cat(T_780, UInt<1>("h1")) - node T_799 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_800 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_805 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_806 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_807 = mux(T_806, T_805, UInt<1>("h0")) - node T_808 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h1") - oacq_write_beat.a_type <= UInt<3>("h2") - oacq_write_beat.client_xact_id <= UInt<3>("h7") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_847 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_851 = cat(UInt<3>("h7"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h1")) - node T_857 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_858 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_863 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_864 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_865 = mux(T_864, T_863, UInt<1>("h0")) - node T_866 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h1") - oacq_write_block.a_type <= UInt<3>("h3") - oacq_write_block.client_xact_id <= UInt<3>("h7") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_913 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_921 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_922 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_923 = mux(T_922, T_921, UInt<1>("h0")) - node T_924 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h1") - oacq_read_beat.a_type <= UInt<3>("h0") - oacq_read_beat.client_xact_id <= UInt<3>("h7") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h0") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_963 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_967 = cat(UInt<3>("h7"), T_966) - node T_969 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_971 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_973 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_974 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_979 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_980 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_981 = mux(T_980, T_979, UInt<1>("h0")) - node T_982 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h1") - oacq_read_block.a_type <= UInt<3>("h1") - oacq_read_block.client_xact_id <= UInt<3>("h7") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h0") - oacq_read_block.data <= UInt<1>("h0") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h0") - node T_1011 = eq(state, UInt<1>("h1")) - node T_1012 = eq(state, UInt<2>("h3")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h0") - io.inner.probe.valid <= UInt<1>("h0") - node T_1054 = eq(UInt<3>("h4"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h0"), UInt<2>("h2")) - node T_1056 = eq(UInt<3>("h6"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h0"), T_1055) - node T_1058 = eq(UInt<3>("h5"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h2"), T_1057) - node T_1060 = eq(UInt<3>("h2"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h0"), T_1059) - node T_1062 = eq(UInt<3>("h0"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h2"), T_1061) - node T_1064 = eq(UInt<3>("h3"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h0"), T_1063) - node T_1066 = eq(UInt<3>("h1"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h2"), T_1065) - node T_1068 = eq(UInt<1>("h1"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h0"), UInt<2>("h2")) - node T_1070 = eq(UInt<1>("h0"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h1"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h0") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h0") - node T_1100 = eq(UInt<3>("h6"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h1"), UInt<3>("h3")) - node T_1102 = eq(UInt<3>("h5"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h1"), T_1101) - node T_1104 = eq(UInt<3>("h4"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h4"), T_1103) - node T_1106 = eq(UInt<3>("h3"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h3"), T_1105) - node T_1108 = eq(UInt<3>("h2"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h3"), T_1107) - node T_1110 = eq(UInt<3>("h1"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h5"), T_1109) - node T_1112 = eq(UInt<3>("h0"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h4"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h0")) - node T_1117 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1118 = mux(T_1117, UInt<1>("h0"), UInt<1>("h1")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h1")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h7") - T_1129.addr_beat <= UInt<1>("h0") - T_1129.data <= UInt<1>("h0") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h0") - io.inner.release.ready <= UInt<1>("h0") - io.inner.finish.ready <= UInt<1>("h0") - node T_1140 = neq(state, UInt<1>("h0")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h0")) - node T_1149 = eq(reset, UInt<1>("h0")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h0")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h0")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h0")) - node T_1163 = eq(reset, UInt<1>("h0")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h0")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h0")) - when T_1167 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h0")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h3") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h0"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h0")) - node T_1189 = eq(reset, UInt<1>("h0")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h0")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h0")) - when T_1193 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h1"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h0"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h0"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h0")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h1"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h0") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h1") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h0") - skip - skip - node T_1245 = eq(UInt<1>("h0"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h1") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h0")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h1"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h0"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h0"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h0")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h0")] <= T_1287 - node T_1289 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h3") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h0"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h2") - T_1303[1] <= UInt<3>("h3") - T_1303[2] <= UInt<3>("h4") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h0"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h0")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h0"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h0"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h0"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h2"), UInt<3>("h4")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h3"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h1"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h1"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h0")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h1"), UInt<1>("h0")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h0") - T_1346[1] <= UInt<1>("h1") - T_1346[2] <= UInt<2>("h2") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h0"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h0")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h0") - T_1362[1] <= UInt<1>("h1") - T_1362[2] <= UInt<2>("h2") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h0"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h1") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1377 = sub(release_count, UInt<1>("h1")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h1")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1382 = mux(pending_outer_write, UInt<2>("h3"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h0")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h1")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h1")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h4")) - node T_1391 = mux(pending_outer_write, UInt<2>("h3"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h3"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h0")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h0")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h1") - node T_1402 = mux(pending_outer_read, UInt<2>("h2"), UInt<3>("h5")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h2"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h0")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h5") - skip - skip - node T_1407 = eq(UInt<3>("h5"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h0")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h4"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h1") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h0")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h6"), UInt<1>("h0")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h6"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h1") - when io.inner.finish.valid : - state <= UInt<1>("h0") - skip - skip - module LockingRRArbiter_33 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, chosen : UInt<3>} - io is invalid - reg T_1502 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1504 : UInt, clk with : - reset => (reset, UInt<3>("h7")) - wire T_1506 : UInt<3> - T_1506 is invalid - io.out.valid <= io.in[T_1506].valid - io.out.bits <- io.in[T_1506].bits - io.chosen <= T_1506 - io.in[T_1506].ready <= UInt<1>("h0") - reg last_grant : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_1706 = gt(UInt<1>("h0"), last_grant) - node T_1707 = and(io.in[0].valid, T_1706) - node T_1709 = gt(UInt<1>("h1"), last_grant) - node T_1710 = and(io.in[1].valid, T_1709) - node T_1712 = gt(UInt<2>("h2"), last_grant) - node T_1713 = and(io.in[2].valid, T_1712) - node T_1715 = gt(UInt<2>("h3"), last_grant) - node T_1716 = and(io.in[3].valid, T_1715) - node T_1718 = gt(UInt<3>("h4"), last_grant) - node T_1719 = and(io.in[4].valid, T_1718) - node T_1721 = gt(UInt<3>("h5"), last_grant) - node T_1722 = and(io.in[5].valid, T_1721) - node T_1724 = gt(UInt<3>("h6"), last_grant) - node T_1725 = and(io.in[6].valid, T_1724) - node T_1727 = gt(UInt<3>("h7"), last_grant) - node T_1728 = and(io.in[7].valid, T_1727) - node T_1731 = or(UInt<1>("h0"), T_1707) - node T_1733 = eq(T_1731, UInt<1>("h0")) - node T_1735 = or(UInt<1>("h0"), T_1707) - node T_1736 = or(T_1735, T_1710) - node T_1738 = eq(T_1736, UInt<1>("h0")) - node T_1740 = or(UInt<1>("h0"), T_1707) - node T_1741 = or(T_1740, T_1710) - node T_1742 = or(T_1741, T_1713) - node T_1744 = eq(T_1742, UInt<1>("h0")) - node T_1746 = or(UInt<1>("h0"), T_1707) - node T_1747 = or(T_1746, T_1710) - node T_1748 = or(T_1747, T_1713) - node T_1749 = or(T_1748, T_1716) - node T_1751 = eq(T_1749, UInt<1>("h0")) - node T_1753 = or(UInt<1>("h0"), T_1707) - node T_1754 = or(T_1753, T_1710) - node T_1755 = or(T_1754, T_1713) - node T_1756 = or(T_1755, T_1716) - node T_1757 = or(T_1756, T_1719) - node T_1759 = eq(T_1757, UInt<1>("h0")) - node T_1761 = or(UInt<1>("h0"), T_1707) - node T_1762 = or(T_1761, T_1710) - node T_1763 = or(T_1762, T_1713) - node T_1764 = or(T_1763, T_1716) - node T_1765 = or(T_1764, T_1719) - node T_1766 = or(T_1765, T_1722) - node T_1768 = eq(T_1766, UInt<1>("h0")) - node T_1770 = or(UInt<1>("h0"), T_1707) - node T_1771 = or(T_1770, T_1710) - node T_1772 = or(T_1771, T_1713) - node T_1773 = or(T_1772, T_1716) - node T_1774 = or(T_1773, T_1719) - node T_1775 = or(T_1774, T_1722) - node T_1776 = or(T_1775, T_1725) - node T_1778 = eq(T_1776, UInt<1>("h0")) - node T_1780 = or(UInt<1>("h0"), T_1707) - node T_1781 = or(T_1780, T_1710) - node T_1782 = or(T_1781, T_1713) - node T_1783 = or(T_1782, T_1716) - node T_1784 = or(T_1783, T_1719) - node T_1785 = or(T_1784, T_1722) - node T_1786 = or(T_1785, T_1725) - node T_1787 = or(T_1786, T_1728) - node T_1789 = eq(T_1787, UInt<1>("h0")) - node T_1791 = or(UInt<1>("h0"), T_1707) - node T_1792 = or(T_1791, T_1710) - node T_1793 = or(T_1792, T_1713) - node T_1794 = or(T_1793, T_1716) - node T_1795 = or(T_1794, T_1719) - node T_1796 = or(T_1795, T_1722) - node T_1797 = or(T_1796, T_1725) - node T_1798 = or(T_1797, T_1728) - node T_1799 = or(T_1798, io.in[0].valid) - node T_1801 = eq(T_1799, UInt<1>("h0")) - node T_1803 = or(UInt<1>("h0"), T_1707) - node T_1804 = or(T_1803, T_1710) - node T_1805 = or(T_1804, T_1713) - node T_1806 = or(T_1805, T_1716) - node T_1807 = or(T_1806, T_1719) - node T_1808 = or(T_1807, T_1722) - node T_1809 = or(T_1808, T_1725) - node T_1810 = or(T_1809, T_1728) - node T_1811 = or(T_1810, io.in[0].valid) - node T_1812 = or(T_1811, io.in[1].valid) - node T_1814 = eq(T_1812, UInt<1>("h0")) - node T_1816 = or(UInt<1>("h0"), T_1707) - node T_1817 = or(T_1816, T_1710) - node T_1818 = or(T_1817, T_1713) - node T_1819 = or(T_1818, T_1716) - node T_1820 = or(T_1819, T_1719) - node T_1821 = or(T_1820, T_1722) - node T_1822 = or(T_1821, T_1725) - node T_1823 = or(T_1822, T_1728) - node T_1824 = or(T_1823, io.in[0].valid) - node T_1825 = or(T_1824, io.in[1].valid) - node T_1826 = or(T_1825, io.in[2].valid) - node T_1828 = eq(T_1826, UInt<1>("h0")) - node T_1830 = or(UInt<1>("h0"), T_1707) - node T_1831 = or(T_1830, T_1710) - node T_1832 = or(T_1831, T_1713) - node T_1833 = or(T_1832, T_1716) - node T_1834 = or(T_1833, T_1719) - node T_1835 = or(T_1834, T_1722) - node T_1836 = or(T_1835, T_1725) - node T_1837 = or(T_1836, T_1728) - node T_1838 = or(T_1837, io.in[0].valid) - node T_1839 = or(T_1838, io.in[1].valid) - node T_1840 = or(T_1839, io.in[2].valid) - node T_1841 = or(T_1840, io.in[3].valid) - node T_1843 = eq(T_1841, UInt<1>("h0")) - node T_1845 = or(UInt<1>("h0"), T_1707) - node T_1846 = or(T_1845, T_1710) - node T_1847 = or(T_1846, T_1713) - node T_1848 = or(T_1847, T_1716) - node T_1849 = or(T_1848, T_1719) - node T_1850 = or(T_1849, T_1722) - node T_1851 = or(T_1850, T_1725) - node T_1852 = or(T_1851, T_1728) - node T_1853 = or(T_1852, io.in[0].valid) - node T_1854 = or(T_1853, io.in[1].valid) - node T_1855 = or(T_1854, io.in[2].valid) - node T_1856 = or(T_1855, io.in[3].valid) - node T_1857 = or(T_1856, io.in[4].valid) - node T_1859 = eq(T_1857, UInt<1>("h0")) - node T_1861 = or(UInt<1>("h0"), T_1707) - node T_1862 = or(T_1861, T_1710) - node T_1863 = or(T_1862, T_1713) - node T_1864 = or(T_1863, T_1716) - node T_1865 = or(T_1864, T_1719) - node T_1866 = or(T_1865, T_1722) - node T_1867 = or(T_1866, T_1725) - node T_1868 = or(T_1867, T_1728) - node T_1869 = or(T_1868, io.in[0].valid) - node T_1870 = or(T_1869, io.in[1].valid) - node T_1871 = or(T_1870, io.in[2].valid) - node T_1872 = or(T_1871, io.in[3].valid) - node T_1873 = or(T_1872, io.in[4].valid) - node T_1874 = or(T_1873, io.in[5].valid) - node T_1876 = eq(T_1874, UInt<1>("h0")) - node T_1878 = or(UInt<1>("h0"), T_1707) - node T_1879 = or(T_1878, T_1710) - node T_1880 = or(T_1879, T_1713) - node T_1881 = or(T_1880, T_1716) - node T_1882 = or(T_1881, T_1719) - node T_1883 = or(T_1882, T_1722) - node T_1884 = or(T_1883, T_1725) - node T_1885 = or(T_1884, T_1728) - node T_1886 = or(T_1885, io.in[0].valid) - node T_1887 = or(T_1886, io.in[1].valid) - node T_1888 = or(T_1887, io.in[2].valid) - node T_1889 = or(T_1888, io.in[3].valid) - node T_1890 = or(T_1889, io.in[4].valid) - node T_1891 = or(T_1890, io.in[5].valid) - node T_1892 = or(T_1891, io.in[6].valid) - node T_1894 = eq(T_1892, UInt<1>("h0")) - node T_1896 = gt(UInt<1>("h0"), last_grant) - node T_1897 = and(UInt<1>("h1"), T_1896) - node T_1898 = or(T_1897, T_1789) - node T_1900 = gt(UInt<1>("h1"), last_grant) - node T_1901 = and(T_1733, T_1900) - node T_1902 = or(T_1901, T_1801) - node T_1904 = gt(UInt<2>("h2"), last_grant) - node T_1905 = and(T_1738, T_1904) - node T_1906 = or(T_1905, T_1814) - node T_1908 = gt(UInt<2>("h3"), last_grant) - node T_1909 = and(T_1744, T_1908) - node T_1910 = or(T_1909, T_1828) - node T_1912 = gt(UInt<3>("h4"), last_grant) - node T_1913 = and(T_1751, T_1912) - node T_1914 = or(T_1913, T_1843) - node T_1916 = gt(UInt<3>("h5"), last_grant) - node T_1917 = and(T_1759, T_1916) - node T_1918 = or(T_1917, T_1859) - node T_1920 = gt(UInt<3>("h6"), last_grant) - node T_1921 = and(T_1768, T_1920) - node T_1922 = or(T_1921, T_1876) - node T_1924 = gt(UInt<3>("h7"), last_grant) - node T_1925 = and(T_1778, T_1924) - node T_1926 = or(T_1925, T_1894) - node T_1928 = eq(T_1504, UInt<1>("h0")) - node T_1929 = mux(T_1502, T_1928, T_1898) - node T_1930 = and(T_1929, io.out.ready) - io.in[0].ready <= T_1930 - node T_1932 = eq(T_1504, UInt<1>("h1")) - node T_1933 = mux(T_1502, T_1932, T_1902) - node T_1934 = and(T_1933, io.out.ready) - io.in[1].ready <= T_1934 - node T_1936 = eq(T_1504, UInt<2>("h2")) - node T_1937 = mux(T_1502, T_1936, T_1906) - node T_1938 = and(T_1937, io.out.ready) - io.in[2].ready <= T_1938 - node T_1940 = eq(T_1504, UInt<2>("h3")) - node T_1941 = mux(T_1502, T_1940, T_1910) - node T_1942 = and(T_1941, io.out.ready) - io.in[3].ready <= T_1942 - node T_1944 = eq(T_1504, UInt<3>("h4")) - node T_1945 = mux(T_1502, T_1944, T_1914) - node T_1946 = and(T_1945, io.out.ready) - io.in[4].ready <= T_1946 - node T_1948 = eq(T_1504, UInt<3>("h5")) - node T_1949 = mux(T_1502, T_1948, T_1918) - node T_1950 = and(T_1949, io.out.ready) - io.in[5].ready <= T_1950 - node T_1952 = eq(T_1504, UInt<3>("h6")) - node T_1953 = mux(T_1502, T_1952, T_1922) - node T_1954 = and(T_1953, io.out.ready) - io.in[6].ready <= T_1954 - node T_1956 = eq(T_1504, UInt<3>("h7")) - node T_1957 = mux(T_1502, T_1956, T_1926) - node T_1958 = and(T_1957, io.out.ready) - io.in[7].ready <= T_1958 - reg T_1960 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_1962 = add(T_1960, UInt<1>("h1")) - node T_1963 = tail(T_1962, 1) - node T_1964 = and(io.out.ready, io.out.valid) - when T_1964 : - wire T_1968 : UInt<3>[1] - T_1968[0] <= UInt<3>("h5") - node T_1971 = eq(T_1968[0], io.out.bits.g_type) - node T_1973 = or(UInt<1>("h0"), T_1971) - wire T_1975 : UInt<1>[2] - T_1975[0] <= UInt<1>("h0") - T_1975[1] <= UInt<1>("h1") - node T_1979 = eq(T_1975[0], io.out.bits.g_type) - node T_1980 = eq(T_1975[1], io.out.bits.g_type) - node T_1982 = or(UInt<1>("h0"), T_1979) - node T_1983 = or(T_1982, T_1980) - node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983) - node T_1985 = and(UInt<1>("h1"), T_1984) - when T_1985 : - T_1960 <= T_1963 - node T_1987 = eq(T_1502, UInt<1>("h0")) - when T_1987 : - T_1502 <= UInt<1>("h1") - node T_1989 = and(io.in[0].ready, io.in[0].valid) - node T_1990 = and(io.in[1].ready, io.in[1].valid) - node T_1991 = and(io.in[2].ready, io.in[2].valid) - node T_1992 = and(io.in[3].ready, io.in[3].valid) - node T_1993 = and(io.in[4].ready, io.in[4].valid) - node T_1994 = and(io.in[5].ready, io.in[5].valid) - node T_1995 = and(io.in[6].ready, io.in[6].valid) - node T_1996 = and(io.in[7].ready, io.in[7].valid) - wire T_1998 : UInt<1>[8] - T_1998[0] <= T_1989 - T_1998[1] <= T_1990 - T_1998[2] <= T_1991 - T_1998[3] <= T_1992 - T_1998[4] <= T_1993 - T_1998[5] <= T_1994 - T_1998[6] <= T_1995 - T_1998[7] <= T_1996 - node T_2016 = mux(T_1998[6], UInt<3>("h6"), UInt<3>("h7")) - node T_2017 = mux(T_1998[5], UInt<3>("h5"), T_2016) - node T_2018 = mux(T_1998[4], UInt<3>("h4"), T_2017) - node T_2019 = mux(T_1998[3], UInt<2>("h3"), T_2018) - node T_2020 = mux(T_1998[2], UInt<2>("h2"), T_2019) - node T_2021 = mux(T_1998[1], UInt<1>("h1"), T_2020) - node T_2022 = mux(T_1998[0], UInt<1>("h0"), T_2021) - T_1504 <= T_2022 - skip - skip - node T_2024 = eq(T_1963, UInt<1>("h0")) - when T_2024 : - T_1502 <= UInt<1>("h0") - skip - skip - node T_2028 = mux(io.in[6].valid, UInt<3>("h6"), UInt<3>("h7")) - node T_2030 = mux(io.in[5].valid, UInt<3>("h5"), T_2028) - node T_2032 = mux(io.in[4].valid, UInt<3>("h4"), T_2030) - node T_2034 = mux(io.in[3].valid, UInt<2>("h3"), T_2032) - node T_2036 = mux(io.in[2].valid, UInt<2>("h2"), T_2034) - node T_2038 = mux(io.in[1].valid, UInt<1>("h1"), T_2036) - node T_2040 = mux(io.in[0].valid, UInt<1>("h0"), T_2038) - node T_2042 = gt(UInt<3>("h7"), last_grant) - node T_2043 = and(io.in[7].valid, T_2042) - node T_2045 = mux(T_2043, UInt<3>("h7"), T_2040) - node T_2047 = gt(UInt<3>("h6"), last_grant) - node T_2048 = and(io.in[6].valid, T_2047) - node T_2050 = mux(T_2048, UInt<3>("h6"), T_2045) - node T_2052 = gt(UInt<3>("h5"), last_grant) - node T_2053 = and(io.in[5].valid, T_2052) - node T_2055 = mux(T_2053, UInt<3>("h5"), T_2050) - node T_2057 = gt(UInt<3>("h4"), last_grant) - node T_2058 = and(io.in[4].valid, T_2057) - node T_2060 = mux(T_2058, UInt<3>("h4"), T_2055) - node T_2062 = gt(UInt<2>("h3"), last_grant) - node T_2063 = and(io.in[3].valid, T_2062) - node T_2065 = mux(T_2063, UInt<2>("h3"), T_2060) - node T_2067 = gt(UInt<2>("h2"), last_grant) - node T_2068 = and(io.in[2].valid, T_2067) - node T_2070 = mux(T_2068, UInt<2>("h2"), T_2065) - node T_2072 = gt(UInt<1>("h1"), last_grant) - node T_2073 = and(io.in[1].valid, T_2072) - node choose = mux(T_2073, UInt<1>("h1"), T_2070) - node T_2076 = mux(T_1502, T_1504, choose) - T_1506 <= T_2076 - node T_2077 = and(io.out.ready, io.out.valid) - when T_2077 : - last_grant <= T_1506 - skip - module LockingRRArbiter_34 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>} - io is invalid - reg T_1318 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1320 : UInt, clk with : - reset => (reset, UInt<3>("h7")) - wire T_1322 : UInt<3> - T_1322 is invalid - io.out.valid <= io.in[T_1322].valid - io.out.bits <- io.in[T_1322].bits - io.chosen <= T_1322 - io.in[T_1322].ready <= UInt<1>("h0") - reg last_grant : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_1498 = gt(UInt<1>("h0"), last_grant) - node T_1499 = and(io.in[0].valid, T_1498) - node T_1501 = gt(UInt<1>("h1"), last_grant) - node T_1502 = and(io.in[1].valid, T_1501) - node T_1504 = gt(UInt<2>("h2"), last_grant) - node T_1505 = and(io.in[2].valid, T_1504) - node T_1507 = gt(UInt<2>("h3"), last_grant) - node T_1508 = and(io.in[3].valid, T_1507) - node T_1510 = gt(UInt<3>("h4"), last_grant) - node T_1511 = and(io.in[4].valid, T_1510) - node T_1513 = gt(UInt<3>("h5"), last_grant) - node T_1514 = and(io.in[5].valid, T_1513) - node T_1516 = gt(UInt<3>("h6"), last_grant) - node T_1517 = and(io.in[6].valid, T_1516) - node T_1519 = gt(UInt<3>("h7"), last_grant) - node T_1520 = and(io.in[7].valid, T_1519) - node T_1523 = or(UInt<1>("h0"), T_1499) - node T_1525 = eq(T_1523, UInt<1>("h0")) - node T_1527 = or(UInt<1>("h0"), T_1499) - node T_1528 = or(T_1527, T_1502) - node T_1530 = eq(T_1528, UInt<1>("h0")) - node T_1532 = or(UInt<1>("h0"), T_1499) - node T_1533 = or(T_1532, T_1502) - node T_1534 = or(T_1533, T_1505) - node T_1536 = eq(T_1534, UInt<1>("h0")) - node T_1538 = or(UInt<1>("h0"), T_1499) - node T_1539 = or(T_1538, T_1502) - node T_1540 = or(T_1539, T_1505) - node T_1541 = or(T_1540, T_1508) - node T_1543 = eq(T_1541, UInt<1>("h0")) - node T_1545 = or(UInt<1>("h0"), T_1499) - node T_1546 = or(T_1545, T_1502) - node T_1547 = or(T_1546, T_1505) - node T_1548 = or(T_1547, T_1508) - node T_1549 = or(T_1548, T_1511) - node T_1551 = eq(T_1549, UInt<1>("h0")) - node T_1553 = or(UInt<1>("h0"), T_1499) - node T_1554 = or(T_1553, T_1502) - node T_1555 = or(T_1554, T_1505) - node T_1556 = or(T_1555, T_1508) - node T_1557 = or(T_1556, T_1511) - node T_1558 = or(T_1557, T_1514) - node T_1560 = eq(T_1558, UInt<1>("h0")) - node T_1562 = or(UInt<1>("h0"), T_1499) - node T_1563 = or(T_1562, T_1502) - node T_1564 = or(T_1563, T_1505) - node T_1565 = or(T_1564, T_1508) - node T_1566 = or(T_1565, T_1511) - node T_1567 = or(T_1566, T_1514) - node T_1568 = or(T_1567, T_1517) - node T_1570 = eq(T_1568, UInt<1>("h0")) - node T_1572 = or(UInt<1>("h0"), T_1499) - node T_1573 = or(T_1572, T_1502) - node T_1574 = or(T_1573, T_1505) - node T_1575 = or(T_1574, T_1508) - node T_1576 = or(T_1575, T_1511) - node T_1577 = or(T_1576, T_1514) - node T_1578 = or(T_1577, T_1517) - node T_1579 = or(T_1578, T_1520) - node T_1581 = eq(T_1579, UInt<1>("h0")) - node T_1583 = or(UInt<1>("h0"), T_1499) - node T_1584 = or(T_1583, T_1502) - node T_1585 = or(T_1584, T_1505) - node T_1586 = or(T_1585, T_1508) - node T_1587 = or(T_1586, T_1511) - node T_1588 = or(T_1587, T_1514) - node T_1589 = or(T_1588, T_1517) - node T_1590 = or(T_1589, T_1520) - node T_1591 = or(T_1590, io.in[0].valid) - node T_1593 = eq(T_1591, UInt<1>("h0")) - node T_1595 = or(UInt<1>("h0"), T_1499) - node T_1596 = or(T_1595, T_1502) - node T_1597 = or(T_1596, T_1505) - node T_1598 = or(T_1597, T_1508) - node T_1599 = or(T_1598, T_1511) - node T_1600 = or(T_1599, T_1514) - node T_1601 = or(T_1600, T_1517) - node T_1602 = or(T_1601, T_1520) - node T_1603 = or(T_1602, io.in[0].valid) - node T_1604 = or(T_1603, io.in[1].valid) - node T_1606 = eq(T_1604, UInt<1>("h0")) - node T_1608 = or(UInt<1>("h0"), T_1499) - node T_1609 = or(T_1608, T_1502) - node T_1610 = or(T_1609, T_1505) - node T_1611 = or(T_1610, T_1508) - node T_1612 = or(T_1611, T_1511) - node T_1613 = or(T_1612, T_1514) - node T_1614 = or(T_1613, T_1517) - node T_1615 = or(T_1614, T_1520) - node T_1616 = or(T_1615, io.in[0].valid) - node T_1617 = or(T_1616, io.in[1].valid) - node T_1618 = or(T_1617, io.in[2].valid) - node T_1620 = eq(T_1618, UInt<1>("h0")) - node T_1622 = or(UInt<1>("h0"), T_1499) - node T_1623 = or(T_1622, T_1502) - node T_1624 = or(T_1623, T_1505) - node T_1625 = or(T_1624, T_1508) - node T_1626 = or(T_1625, T_1511) - node T_1627 = or(T_1626, T_1514) - node T_1628 = or(T_1627, T_1517) - node T_1629 = or(T_1628, T_1520) - node T_1630 = or(T_1629, io.in[0].valid) - node T_1631 = or(T_1630, io.in[1].valid) - node T_1632 = or(T_1631, io.in[2].valid) - node T_1633 = or(T_1632, io.in[3].valid) - node T_1635 = eq(T_1633, UInt<1>("h0")) - node T_1637 = or(UInt<1>("h0"), T_1499) - node T_1638 = or(T_1637, T_1502) - node T_1639 = or(T_1638, T_1505) - node T_1640 = or(T_1639, T_1508) - node T_1641 = or(T_1640, T_1511) - node T_1642 = or(T_1641, T_1514) - node T_1643 = or(T_1642, T_1517) - node T_1644 = or(T_1643, T_1520) - node T_1645 = or(T_1644, io.in[0].valid) - node T_1646 = or(T_1645, io.in[1].valid) - node T_1647 = or(T_1646, io.in[2].valid) - node T_1648 = or(T_1647, io.in[3].valid) - node T_1649 = or(T_1648, io.in[4].valid) - node T_1651 = eq(T_1649, UInt<1>("h0")) - node T_1653 = or(UInt<1>("h0"), T_1499) - node T_1654 = or(T_1653, T_1502) - node T_1655 = or(T_1654, T_1505) - node T_1656 = or(T_1655, T_1508) - node T_1657 = or(T_1656, T_1511) - node T_1658 = or(T_1657, T_1514) - node T_1659 = or(T_1658, T_1517) - node T_1660 = or(T_1659, T_1520) - node T_1661 = or(T_1660, io.in[0].valid) - node T_1662 = or(T_1661, io.in[1].valid) - node T_1663 = or(T_1662, io.in[2].valid) - node T_1664 = or(T_1663, io.in[3].valid) - node T_1665 = or(T_1664, io.in[4].valid) - node T_1666 = or(T_1665, io.in[5].valid) - node T_1668 = eq(T_1666, UInt<1>("h0")) - node T_1670 = or(UInt<1>("h0"), T_1499) - node T_1671 = or(T_1670, T_1502) - node T_1672 = or(T_1671, T_1505) - node T_1673 = or(T_1672, T_1508) - node T_1674 = or(T_1673, T_1511) - node T_1675 = or(T_1674, T_1514) - node T_1676 = or(T_1675, T_1517) - node T_1677 = or(T_1676, T_1520) - node T_1678 = or(T_1677, io.in[0].valid) - node T_1679 = or(T_1678, io.in[1].valid) - node T_1680 = or(T_1679, io.in[2].valid) - node T_1681 = or(T_1680, io.in[3].valid) - node T_1682 = or(T_1681, io.in[4].valid) - node T_1683 = or(T_1682, io.in[5].valid) - node T_1684 = or(T_1683, io.in[6].valid) - node T_1686 = eq(T_1684, UInt<1>("h0")) - node T_1688 = gt(UInt<1>("h0"), last_grant) - node T_1689 = and(UInt<1>("h1"), T_1688) - node T_1690 = or(T_1689, T_1581) - node T_1692 = gt(UInt<1>("h1"), last_grant) - node T_1693 = and(T_1525, T_1692) - node T_1694 = or(T_1693, T_1593) - node T_1696 = gt(UInt<2>("h2"), last_grant) - node T_1697 = and(T_1530, T_1696) - node T_1698 = or(T_1697, T_1606) - node T_1700 = gt(UInt<2>("h3"), last_grant) - node T_1701 = and(T_1536, T_1700) - node T_1702 = or(T_1701, T_1620) - node T_1704 = gt(UInt<3>("h4"), last_grant) - node T_1705 = and(T_1543, T_1704) - node T_1706 = or(T_1705, T_1635) - node T_1708 = gt(UInt<3>("h5"), last_grant) - node T_1709 = and(T_1551, T_1708) - node T_1710 = or(T_1709, T_1651) - node T_1712 = gt(UInt<3>("h6"), last_grant) - node T_1713 = and(T_1560, T_1712) - node T_1714 = or(T_1713, T_1668) - node T_1716 = gt(UInt<3>("h7"), last_grant) - node T_1717 = and(T_1570, T_1716) - node T_1718 = or(T_1717, T_1686) - node T_1720 = eq(T_1320, UInt<1>("h0")) - node T_1721 = mux(T_1318, T_1720, T_1690) - node T_1722 = and(T_1721, io.out.ready) - io.in[0].ready <= T_1722 - node T_1724 = eq(T_1320, UInt<1>("h1")) - node T_1725 = mux(T_1318, T_1724, T_1694) - node T_1726 = and(T_1725, io.out.ready) - io.in[1].ready <= T_1726 - node T_1728 = eq(T_1320, UInt<2>("h2")) - node T_1729 = mux(T_1318, T_1728, T_1698) - node T_1730 = and(T_1729, io.out.ready) - io.in[2].ready <= T_1730 - node T_1732 = eq(T_1320, UInt<2>("h3")) - node T_1733 = mux(T_1318, T_1732, T_1702) - node T_1734 = and(T_1733, io.out.ready) - io.in[3].ready <= T_1734 - node T_1736 = eq(T_1320, UInt<3>("h4")) - node T_1737 = mux(T_1318, T_1736, T_1706) - node T_1738 = and(T_1737, io.out.ready) - io.in[4].ready <= T_1738 - node T_1740 = eq(T_1320, UInt<3>("h5")) - node T_1741 = mux(T_1318, T_1740, T_1710) - node T_1742 = and(T_1741, io.out.ready) - io.in[5].ready <= T_1742 - node T_1744 = eq(T_1320, UInt<3>("h6")) - node T_1745 = mux(T_1318, T_1744, T_1714) - node T_1746 = and(T_1745, io.out.ready) - io.in[6].ready <= T_1746 - node T_1748 = eq(T_1320, UInt<3>("h7")) - node T_1749 = mux(T_1318, T_1748, T_1718) - node T_1750 = and(T_1749, io.out.ready) - io.in[7].ready <= T_1750 - reg T_1752 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_1754 = add(T_1752, UInt<1>("h1")) - node T_1755 = tail(T_1754, 1) - node T_1756 = and(io.out.ready, io.out.valid) - when T_1756 : - when UInt<1>("h0") : - T_1752 <= T_1755 - node T_1759 = eq(T_1318, UInt<1>("h0")) - when T_1759 : - T_1318 <= UInt<1>("h1") - node T_1761 = and(io.in[0].ready, io.in[0].valid) - node T_1762 = and(io.in[1].ready, io.in[1].valid) - node T_1763 = and(io.in[2].ready, io.in[2].valid) - node T_1764 = and(io.in[3].ready, io.in[3].valid) - node T_1765 = and(io.in[4].ready, io.in[4].valid) - node T_1766 = and(io.in[5].ready, io.in[5].valid) - node T_1767 = and(io.in[6].ready, io.in[6].valid) - node T_1768 = and(io.in[7].ready, io.in[7].valid) - wire T_1770 : UInt<1>[8] - T_1770[0] <= T_1761 - T_1770[1] <= T_1762 - T_1770[2] <= T_1763 - T_1770[3] <= T_1764 - T_1770[4] <= T_1765 - T_1770[5] <= T_1766 - T_1770[6] <= T_1767 - T_1770[7] <= T_1768 - node T_1788 = mux(T_1770[6], UInt<3>("h6"), UInt<3>("h7")) - node T_1789 = mux(T_1770[5], UInt<3>("h5"), T_1788) - node T_1790 = mux(T_1770[4], UInt<3>("h4"), T_1789) - node T_1791 = mux(T_1770[3], UInt<2>("h3"), T_1790) - node T_1792 = mux(T_1770[2], UInt<2>("h2"), T_1791) - node T_1793 = mux(T_1770[1], UInt<1>("h1"), T_1792) - node T_1794 = mux(T_1770[0], UInt<1>("h0"), T_1793) - T_1320 <= T_1794 - skip - skip - node T_1796 = eq(T_1755, UInt<1>("h0")) - when T_1796 : - T_1318 <= UInt<1>("h0") - skip - skip - node T_1800 = mux(io.in[6].valid, UInt<3>("h6"), UInt<3>("h7")) - node T_1802 = mux(io.in[5].valid, UInt<3>("h5"), T_1800) - node T_1804 = mux(io.in[4].valid, UInt<3>("h4"), T_1802) - node T_1806 = mux(io.in[3].valid, UInt<2>("h3"), T_1804) - node T_1808 = mux(io.in[2].valid, UInt<2>("h2"), T_1806) - node T_1810 = mux(io.in[1].valid, UInt<1>("h1"), T_1808) - node T_1812 = mux(io.in[0].valid, UInt<1>("h0"), T_1810) - node T_1814 = gt(UInt<3>("h7"), last_grant) - node T_1815 = and(io.in[7].valid, T_1814) - node T_1817 = mux(T_1815, UInt<3>("h7"), T_1812) - node T_1819 = gt(UInt<3>("h6"), last_grant) - node T_1820 = and(io.in[6].valid, T_1819) - node T_1822 = mux(T_1820, UInt<3>("h6"), T_1817) - node T_1824 = gt(UInt<3>("h5"), last_grant) - node T_1825 = and(io.in[5].valid, T_1824) - node T_1827 = mux(T_1825, UInt<3>("h5"), T_1822) - node T_1829 = gt(UInt<3>("h4"), last_grant) - node T_1830 = and(io.in[4].valid, T_1829) - node T_1832 = mux(T_1830, UInt<3>("h4"), T_1827) - node T_1834 = gt(UInt<2>("h3"), last_grant) - node T_1835 = and(io.in[3].valid, T_1834) - node T_1837 = mux(T_1835, UInt<2>("h3"), T_1832) - node T_1839 = gt(UInt<2>("h2"), last_grant) - node T_1840 = and(io.in[2].valid, T_1839) - node T_1842 = mux(T_1840, UInt<2>("h2"), T_1837) - node T_1844 = gt(UInt<1>("h1"), last_grant) - node T_1845 = and(io.in[1].valid, T_1844) - node choose = mux(T_1845, UInt<1>("h1"), T_1842) - node T_1848 = mux(T_1318, T_1320, choose) - T_1322 <= T_1848 - node T_1849 = and(io.out.ready, io.out.valid) - when T_1849 : - last_grant <= T_1322 - skip - module LockingRRArbiter_35 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, chosen : UInt<3>} - io is invalid - reg T_444 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_446 : UInt, clk with : - reset => (reset, UInt<3>("h7")) - wire T_448 : UInt<3> - T_448 is invalid - io.out.valid <= io.in[T_448].valid - io.out.bits <- io.in[T_448].bits - io.chosen <= T_448 - io.in[T_448].ready <= UInt<1>("h0") - reg last_grant : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_510 = gt(UInt<1>("h0"), last_grant) - node T_511 = and(io.in[0].valid, T_510) - node T_513 = gt(UInt<1>("h1"), last_grant) - node T_514 = and(io.in[1].valid, T_513) - node T_516 = gt(UInt<2>("h2"), last_grant) - node T_517 = and(io.in[2].valid, T_516) - node T_519 = gt(UInt<2>("h3"), last_grant) - node T_520 = and(io.in[3].valid, T_519) - node T_522 = gt(UInt<3>("h4"), last_grant) - node T_523 = and(io.in[4].valid, T_522) - node T_525 = gt(UInt<3>("h5"), last_grant) - node T_526 = and(io.in[5].valid, T_525) - node T_528 = gt(UInt<3>("h6"), last_grant) - node T_529 = and(io.in[6].valid, T_528) - node T_531 = gt(UInt<3>("h7"), last_grant) - node T_532 = and(io.in[7].valid, T_531) - node T_535 = or(UInt<1>("h0"), T_511) - node T_537 = eq(T_535, UInt<1>("h0")) - node T_539 = or(UInt<1>("h0"), T_511) - node T_540 = or(T_539, T_514) - node T_542 = eq(T_540, UInt<1>("h0")) - node T_544 = or(UInt<1>("h0"), T_511) - node T_545 = or(T_544, T_514) - node T_546 = or(T_545, T_517) - node T_548 = eq(T_546, UInt<1>("h0")) - node T_550 = or(UInt<1>("h0"), T_511) - node T_551 = or(T_550, T_514) - node T_552 = or(T_551, T_517) - node T_553 = or(T_552, T_520) - node T_555 = eq(T_553, UInt<1>("h0")) - node T_557 = or(UInt<1>("h0"), T_511) - node T_558 = or(T_557, T_514) - node T_559 = or(T_558, T_517) - node T_560 = or(T_559, T_520) - node T_561 = or(T_560, T_523) - node T_563 = eq(T_561, UInt<1>("h0")) - node T_565 = or(UInt<1>("h0"), T_511) - node T_566 = or(T_565, T_514) - node T_567 = or(T_566, T_517) - node T_568 = or(T_567, T_520) - node T_569 = or(T_568, T_523) - node T_570 = or(T_569, T_526) - node T_572 = eq(T_570, UInt<1>("h0")) - node T_574 = or(UInt<1>("h0"), T_511) - node T_575 = or(T_574, T_514) - node T_576 = or(T_575, T_517) - node T_577 = or(T_576, T_520) - node T_578 = or(T_577, T_523) - node T_579 = or(T_578, T_526) - node T_580 = or(T_579, T_529) - node T_582 = eq(T_580, UInt<1>("h0")) - node T_584 = or(UInt<1>("h0"), T_511) - node T_585 = or(T_584, T_514) - node T_586 = or(T_585, T_517) - node T_587 = or(T_586, T_520) - node T_588 = or(T_587, T_523) - node T_589 = or(T_588, T_526) - node T_590 = or(T_589, T_529) - node T_591 = or(T_590, T_532) - node T_593 = eq(T_591, UInt<1>("h0")) - node T_595 = or(UInt<1>("h0"), T_511) - node T_596 = or(T_595, T_514) - node T_597 = or(T_596, T_517) - node T_598 = or(T_597, T_520) - node T_599 = or(T_598, T_523) - node T_600 = or(T_599, T_526) - node T_601 = or(T_600, T_529) - node T_602 = or(T_601, T_532) - node T_603 = or(T_602, io.in[0].valid) - node T_605 = eq(T_603, UInt<1>("h0")) - node T_607 = or(UInt<1>("h0"), T_511) - node T_608 = or(T_607, T_514) - node T_609 = or(T_608, T_517) - node T_610 = or(T_609, T_520) - node T_611 = or(T_610, T_523) - node T_612 = or(T_611, T_526) - node T_613 = or(T_612, T_529) - node T_614 = or(T_613, T_532) - node T_615 = or(T_614, io.in[0].valid) - node T_616 = or(T_615, io.in[1].valid) - node T_618 = eq(T_616, UInt<1>("h0")) - node T_620 = or(UInt<1>("h0"), T_511) - node T_621 = or(T_620, T_514) - node T_622 = or(T_621, T_517) - node T_623 = or(T_622, T_520) - node T_624 = or(T_623, T_523) - node T_625 = or(T_624, T_526) - node T_626 = or(T_625, T_529) - node T_627 = or(T_626, T_532) - node T_628 = or(T_627, io.in[0].valid) - node T_629 = or(T_628, io.in[1].valid) - node T_630 = or(T_629, io.in[2].valid) - node T_632 = eq(T_630, UInt<1>("h0")) - node T_634 = or(UInt<1>("h0"), T_511) - node T_635 = or(T_634, T_514) - node T_636 = or(T_635, T_517) - node T_637 = or(T_636, T_520) - node T_638 = or(T_637, T_523) - node T_639 = or(T_638, T_526) - node T_640 = or(T_639, T_529) - node T_641 = or(T_640, T_532) - node T_642 = or(T_641, io.in[0].valid) - node T_643 = or(T_642, io.in[1].valid) - node T_644 = or(T_643, io.in[2].valid) - node T_645 = or(T_644, io.in[3].valid) - node T_647 = eq(T_645, UInt<1>("h0")) - node T_649 = or(UInt<1>("h0"), T_511) - node T_650 = or(T_649, T_514) - node T_651 = or(T_650, T_517) - node T_652 = or(T_651, T_520) - node T_653 = or(T_652, T_523) - node T_654 = or(T_653, T_526) - node T_655 = or(T_654, T_529) - node T_656 = or(T_655, T_532) - node T_657 = or(T_656, io.in[0].valid) - node T_658 = or(T_657, io.in[1].valid) - node T_659 = or(T_658, io.in[2].valid) - node T_660 = or(T_659, io.in[3].valid) - node T_661 = or(T_660, io.in[4].valid) - node T_663 = eq(T_661, UInt<1>("h0")) - node T_665 = or(UInt<1>("h0"), T_511) - node T_666 = or(T_665, T_514) - node T_667 = or(T_666, T_517) - node T_668 = or(T_667, T_520) - node T_669 = or(T_668, T_523) - node T_670 = or(T_669, T_526) - node T_671 = or(T_670, T_529) - node T_672 = or(T_671, T_532) - node T_673 = or(T_672, io.in[0].valid) - node T_674 = or(T_673, io.in[1].valid) - node T_675 = or(T_674, io.in[2].valid) - node T_676 = or(T_675, io.in[3].valid) - node T_677 = or(T_676, io.in[4].valid) - node T_678 = or(T_677, io.in[5].valid) - node T_680 = eq(T_678, UInt<1>("h0")) - node T_682 = or(UInt<1>("h0"), T_511) - node T_683 = or(T_682, T_514) - node T_684 = or(T_683, T_517) - node T_685 = or(T_684, T_520) - node T_686 = or(T_685, T_523) - node T_687 = or(T_686, T_526) - node T_688 = or(T_687, T_529) - node T_689 = or(T_688, T_532) - node T_690 = or(T_689, io.in[0].valid) - node T_691 = or(T_690, io.in[1].valid) - node T_692 = or(T_691, io.in[2].valid) - node T_693 = or(T_692, io.in[3].valid) - node T_694 = or(T_693, io.in[4].valid) - node T_695 = or(T_694, io.in[5].valid) - node T_696 = or(T_695, io.in[6].valid) - node T_698 = eq(T_696, UInt<1>("h0")) - node T_700 = gt(UInt<1>("h0"), last_grant) - node T_701 = and(UInt<1>("h1"), T_700) - node T_702 = or(T_701, T_593) - node T_704 = gt(UInt<1>("h1"), last_grant) - node T_705 = and(T_537, T_704) - node T_706 = or(T_705, T_605) - node T_708 = gt(UInt<2>("h2"), last_grant) - node T_709 = and(T_542, T_708) - node T_710 = or(T_709, T_618) - node T_712 = gt(UInt<2>("h3"), last_grant) - node T_713 = and(T_548, T_712) - node T_714 = or(T_713, T_632) - node T_716 = gt(UInt<3>("h4"), last_grant) - node T_717 = and(T_555, T_716) - node T_718 = or(T_717, T_647) - node T_720 = gt(UInt<3>("h5"), last_grant) - node T_721 = and(T_563, T_720) - node T_722 = or(T_721, T_663) - node T_724 = gt(UInt<3>("h6"), last_grant) - node T_725 = and(T_572, T_724) - node T_726 = or(T_725, T_680) - node T_728 = gt(UInt<3>("h7"), last_grant) - node T_729 = and(T_582, T_728) - node T_730 = or(T_729, T_698) - node T_732 = eq(T_446, UInt<1>("h0")) - node T_733 = mux(T_444, T_732, T_702) - node T_734 = and(T_733, io.out.ready) - io.in[0].ready <= T_734 - node T_736 = eq(T_446, UInt<1>("h1")) - node T_737 = mux(T_444, T_736, T_706) - node T_738 = and(T_737, io.out.ready) - io.in[1].ready <= T_738 - node T_740 = eq(T_446, UInt<2>("h2")) - node T_741 = mux(T_444, T_740, T_710) - node T_742 = and(T_741, io.out.ready) - io.in[2].ready <= T_742 - node T_744 = eq(T_446, UInt<2>("h3")) - node T_745 = mux(T_444, T_744, T_714) - node T_746 = and(T_745, io.out.ready) - io.in[3].ready <= T_746 - node T_748 = eq(T_446, UInt<3>("h4")) - node T_749 = mux(T_444, T_748, T_718) - node T_750 = and(T_749, io.out.ready) - io.in[4].ready <= T_750 - node T_752 = eq(T_446, UInt<3>("h5")) - node T_753 = mux(T_444, T_752, T_722) - node T_754 = and(T_753, io.out.ready) - io.in[5].ready <= T_754 - node T_756 = eq(T_446, UInt<3>("h6")) - node T_757 = mux(T_444, T_756, T_726) - node T_758 = and(T_757, io.out.ready) - io.in[6].ready <= T_758 - node T_760 = eq(T_446, UInt<3>("h7")) - node T_761 = mux(T_444, T_760, T_730) - node T_762 = and(T_761, io.out.ready) - io.in[7].ready <= T_762 - reg T_764 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_766 = add(T_764, UInt<1>("h1")) - node T_767 = tail(T_766, 1) - node T_768 = and(io.out.ready, io.out.valid) - when T_768 : - node T_770 = and(UInt<1>("h1"), io.out.bits.is_builtin_type) - wire T_773 : UInt<3>[1] - T_773[0] <= UInt<3>("h3") - node T_776 = eq(T_773[0], io.out.bits.a_type) - node T_778 = or(UInt<1>("h0"), T_776) - node T_779 = and(T_770, T_778) - when T_779 : - T_764 <= T_767 - node T_781 = eq(T_444, UInt<1>("h0")) - when T_781 : - T_444 <= UInt<1>("h1") - node T_783 = and(io.in[0].ready, io.in[0].valid) - node T_784 = and(io.in[1].ready, io.in[1].valid) - node T_785 = and(io.in[2].ready, io.in[2].valid) - node T_786 = and(io.in[3].ready, io.in[3].valid) - node T_787 = and(io.in[4].ready, io.in[4].valid) - node T_788 = and(io.in[5].ready, io.in[5].valid) - node T_789 = and(io.in[6].ready, io.in[6].valid) - node T_790 = and(io.in[7].ready, io.in[7].valid) - wire T_792 : UInt<1>[8] - T_792[0] <= T_783 - T_792[1] <= T_784 - T_792[2] <= T_785 - T_792[3] <= T_786 - T_792[4] <= T_787 - T_792[5] <= T_788 - T_792[6] <= T_789 - T_792[7] <= T_790 - node T_810 = mux(T_792[6], UInt<3>("h6"), UInt<3>("h7")) - node T_811 = mux(T_792[5], UInt<3>("h5"), T_810) - node T_812 = mux(T_792[4], UInt<3>("h4"), T_811) - node T_813 = mux(T_792[3], UInt<2>("h3"), T_812) - node T_814 = mux(T_792[2], UInt<2>("h2"), T_813) - node T_815 = mux(T_792[1], UInt<1>("h1"), T_814) - node T_816 = mux(T_792[0], UInt<1>("h0"), T_815) - T_446 <= T_816 - skip - skip - node T_818 = eq(T_767, UInt<1>("h0")) - when T_818 : - T_444 <= UInt<1>("h0") - skip - skip - node T_822 = mux(io.in[6].valid, UInt<3>("h6"), UInt<3>("h7")) - node T_824 = mux(io.in[5].valid, UInt<3>("h5"), T_822) - node T_826 = mux(io.in[4].valid, UInt<3>("h4"), T_824) - node T_828 = mux(io.in[3].valid, UInt<2>("h3"), T_826) - node T_830 = mux(io.in[2].valid, UInt<2>("h2"), T_828) - node T_832 = mux(io.in[1].valid, UInt<1>("h1"), T_830) - node T_834 = mux(io.in[0].valid, UInt<1>("h0"), T_832) - node T_836 = gt(UInt<3>("h7"), last_grant) - node T_837 = and(io.in[7].valid, T_836) - node T_839 = mux(T_837, UInt<3>("h7"), T_834) - node T_841 = gt(UInt<3>("h6"), last_grant) - node T_842 = and(io.in[6].valid, T_841) - node T_844 = mux(T_842, UInt<3>("h6"), T_839) - node T_846 = gt(UInt<3>("h5"), last_grant) - node T_847 = and(io.in[5].valid, T_846) - node T_849 = mux(T_847, UInt<3>("h5"), T_844) - node T_851 = gt(UInt<3>("h4"), last_grant) - node T_852 = and(io.in[4].valid, T_851) - node T_854 = mux(T_852, UInt<3>("h4"), T_849) - node T_856 = gt(UInt<2>("h3"), last_grant) - node T_857 = and(io.in[3].valid, T_856) - node T_859 = mux(T_857, UInt<2>("h3"), T_854) - node T_861 = gt(UInt<2>("h2"), last_grant) - node T_862 = and(io.in[2].valid, T_861) - node T_864 = mux(T_862, UInt<2>("h2"), T_859) - node T_866 = gt(UInt<1>("h1"), last_grant) - node T_867 = and(io.in[1].valid, T_866) - node choose = mux(T_867, UInt<1>("h1"), T_864) - node T_870 = mux(T_444, T_446, choose) - T_448 <= T_870 - node T_871 = and(io.out.ready, io.out.valid) - when T_871 : - last_grant <= T_448 - skip - module ClientUncachedTileLinkIOArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}[8], out : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}} - io is invalid - inst T_1593 of LockingRRArbiter_35 - T_1593.io is invalid - T_1593.clk <= clk - T_1593.reset <= reset - T_1593.io.in[0].valid <= io.in[0].acquire.valid - T_1593.io.in[0].bits <- io.in[0].acquire.bits - node T_1595 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h0")) - T_1593.io.in[0].bits.client_xact_id <= T_1595 - io.in[0].acquire.ready <= T_1593.io.in[0].ready - T_1593.io.in[1].valid <= io.in[1].acquire.valid - T_1593.io.in[1].bits <- io.in[1].acquire.bits - node T_1597 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h1")) - T_1593.io.in[1].bits.client_xact_id <= T_1597 - io.in[1].acquire.ready <= T_1593.io.in[1].ready - T_1593.io.in[2].valid <= io.in[2].acquire.valid - T_1593.io.in[2].bits <- io.in[2].acquire.bits - node T_1599 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h2")) - T_1593.io.in[2].bits.client_xact_id <= T_1599 - io.in[2].acquire.ready <= T_1593.io.in[2].ready - T_1593.io.in[3].valid <= io.in[3].acquire.valid - T_1593.io.in[3].bits <- io.in[3].acquire.bits - node T_1601 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h3")) - T_1593.io.in[3].bits.client_xact_id <= T_1601 - io.in[3].acquire.ready <= T_1593.io.in[3].ready - T_1593.io.in[4].valid <= io.in[4].acquire.valid - T_1593.io.in[4].bits <- io.in[4].acquire.bits - node T_1603 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h4")) - T_1593.io.in[4].bits.client_xact_id <= T_1603 - io.in[4].acquire.ready <= T_1593.io.in[4].ready - T_1593.io.in[5].valid <= io.in[5].acquire.valid - T_1593.io.in[5].bits <- io.in[5].acquire.bits - node T_1605 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h5")) - T_1593.io.in[5].bits.client_xact_id <= T_1605 - io.in[5].acquire.ready <= T_1593.io.in[5].ready - T_1593.io.in[6].valid <= io.in[6].acquire.valid - T_1593.io.in[6].bits <- io.in[6].acquire.bits - node T_1607 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h6")) - T_1593.io.in[6].bits.client_xact_id <= T_1607 - io.in[6].acquire.ready <= T_1593.io.in[6].ready - T_1593.io.in[7].valid <= io.in[7].acquire.valid - T_1593.io.in[7].bits <- io.in[7].acquire.bits - node T_1609 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h7")) - T_1593.io.in[7].bits.client_xact_id <= T_1609 - io.in[7].acquire.ready <= T_1593.io.in[7].ready - io.out.acquire <- T_1593.io.out - io.out.grant.ready <= UInt<1>("h0") - io.in[0].grant.valid <= UInt<1>("h0") - node T_1612 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1614 = eq(T_1612, UInt<1>("h0")) - when T_1614 : - io.in[0].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[0].grant.ready - skip - io.in[0].grant.bits <- io.out.grant.bits - node T_1615 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[0].grant.bits.client_xact_id <= T_1615 - io.in[1].grant.valid <= UInt<1>("h0") - node T_1617 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1619 = eq(T_1617, UInt<1>("h1")) - when T_1619 : - io.in[1].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[1].grant.ready - skip - io.in[1].grant.bits <- io.out.grant.bits - node T_1620 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[1].grant.bits.client_xact_id <= T_1620 - io.in[2].grant.valid <= UInt<1>("h0") - node T_1622 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1624 = eq(T_1622, UInt<2>("h2")) - when T_1624 : - io.in[2].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[2].grant.ready - skip - io.in[2].grant.bits <- io.out.grant.bits - node T_1625 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[2].grant.bits.client_xact_id <= T_1625 - io.in[3].grant.valid <= UInt<1>("h0") - node T_1627 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1629 = eq(T_1627, UInt<2>("h3")) - when T_1629 : - io.in[3].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[3].grant.ready - skip - io.in[3].grant.bits <- io.out.grant.bits - node T_1630 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[3].grant.bits.client_xact_id <= T_1630 - io.in[4].grant.valid <= UInt<1>("h0") - node T_1632 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1634 = eq(T_1632, UInt<3>("h4")) - when T_1634 : - io.in[4].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[4].grant.ready - skip - io.in[4].grant.bits <- io.out.grant.bits - node T_1635 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[4].grant.bits.client_xact_id <= T_1635 - io.in[5].grant.valid <= UInt<1>("h0") - node T_1637 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1639 = eq(T_1637, UInt<3>("h5")) - when T_1639 : - io.in[5].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[5].grant.ready - skip - io.in[5].grant.bits <- io.out.grant.bits - node T_1640 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[5].grant.bits.client_xact_id <= T_1640 - io.in[6].grant.valid <= UInt<1>("h0") - node T_1642 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1644 = eq(T_1642, UInt<3>("h6")) - when T_1644 : - io.in[6].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[6].grant.ready - skip - io.in[6].grant.bits <- io.out.grant.bits - node T_1645 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[6].grant.bits.client_xact_id <= T_1645 - io.in[7].grant.valid <= UInt<1>("h0") - node T_1647 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1649 = eq(T_1647, UInt<3>("h7")) - when T_1649 : - io.in[7].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[7].grant.ready - skip - io.in[7].grant.bits <- io.out.grant.bits - node T_1650 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[7].grant.bits.client_xact_id <= T_1650 - module L2BroadcastHub : - input clk : Clock - input reset : UInt<1> - output io : { inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io is invalid - inst T_1060 of BroadcastVoluntaryReleaseTracker - T_1060.io is invalid - T_1060.clk <= clk - T_1060.reset <= reset - inst T_1061 of BroadcastAcquireTracker - T_1061.io is invalid - T_1061.clk <= clk - T_1061.reset <= reset - inst T_1062 of BroadcastAcquireTracker_27 - T_1062.io is invalid - T_1062.clk <= clk - T_1062.reset <= reset - inst T_1063 of BroadcastAcquireTracker_28 - T_1063.io is invalid - T_1063.clk <= clk - T_1063.reset <= reset - inst T_1064 of BroadcastAcquireTracker_29 - T_1064.io is invalid - T_1064.clk <= clk - T_1064.reset <= reset - inst T_1065 of BroadcastAcquireTracker_30 - T_1065.io is invalid - T_1065.clk <= clk - T_1065.reset <= reset - inst T_1066 of BroadcastAcquireTracker_31 - T_1066.io is invalid - T_1066.clk <= clk - T_1066.reset <= reset - inst T_1067 of BroadcastAcquireTracker_32 - T_1067.io is invalid - T_1067.clk <= clk - T_1067.reset <= reset - T_1060.io.incoherent <= io.incoherent - T_1061.io.incoherent <= io.incoherent - T_1062.io.incoherent <= io.incoherent - T_1063.io.incoherent <= io.incoherent - T_1064.io.incoherent <= io.incoherent - T_1065.io.incoherent <= io.incoherent - T_1066.io.incoherent <= io.incoherent - T_1067.io.incoherent <= io.incoherent - reg sdq : UInt<128>[4], clk with : - reset => (UInt<1>("h0"), sdq) - reg sdq_val : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - node T_1085 = not(sdq_val) - node T_1086 = bits(T_1085, 0, 0) - node T_1087 = bits(T_1085, 1, 1) - node T_1088 = bits(T_1085, 2, 2) - node T_1089 = bits(T_1085, 3, 3) - wire T_1091 : UInt<1>[4] - T_1091[0] <= T_1086 - T_1091[1] <= T_1087 - T_1091[2] <= T_1088 - T_1091[3] <= T_1089 - node T_1101 = mux(T_1091[2], UInt<2>("h2"), UInt<2>("h3")) - node T_1102 = mux(T_1091[1], UInt<1>("h1"), T_1101) - node sdq_alloc_id = mux(T_1091[0], UInt<1>("h0"), T_1102) - node T_1104 = not(sdq_val) - node T_1106 = eq(T_1104, UInt<1>("h0")) - node sdq_rdy = eq(T_1106, UInt<1>("h0")) - node T_1109 = and(io.inner.acquire.ready, io.inner.acquire.valid) - wire T_1114 : UInt<3>[3] - T_1114[0] <= UInt<3>("h2") - T_1114[1] <= UInt<3>("h3") - T_1114[2] <= UInt<3>("h4") - node T_1119 = eq(T_1114[0], io.inner.acquire.bits.a_type) - node T_1120 = eq(T_1114[1], io.inner.acquire.bits.a_type) - node T_1121 = eq(T_1114[2], io.inner.acquire.bits.a_type) - node T_1123 = or(UInt<1>("h0"), T_1119) - node T_1124 = or(T_1123, T_1120) - node T_1125 = or(T_1124, T_1121) - node T_1126 = and(io.inner.acquire.bits.is_builtin_type, T_1125) - node sdq_enq = and(T_1109, T_1126) - when sdq_enq : - sdq[sdq_alloc_id] <= io.inner.acquire.bits.data - skip - wire T_1130 : UInt<1>[8] - T_1130[0] <= T_1060.io.has_acquire_conflict - T_1130[1] <= T_1061.io.has_acquire_conflict - T_1130[2] <= T_1062.io.has_acquire_conflict - T_1130[3] <= T_1063.io.has_acquire_conflict - T_1130[4] <= T_1064.io.has_acquire_conflict - T_1130[5] <= T_1065.io.has_acquire_conflict - T_1130[6] <= T_1066.io.has_acquire_conflict - T_1130[7] <= T_1067.io.has_acquire_conflict - node T_1140 = cat(T_1130[7], T_1130[6]) - node T_1141 = cat(T_1130[5], T_1130[4]) - node T_1142 = cat(T_1140, T_1141) - node T_1143 = cat(T_1130[3], T_1130[2]) - node T_1144 = cat(T_1130[1], T_1130[0]) - node T_1145 = cat(T_1143, T_1144) - node acquireConflicts = cat(T_1142, T_1145) - wire T_1148 : UInt<1>[8] - T_1148[0] <= T_1060.io.has_acquire_match - T_1148[1] <= T_1061.io.has_acquire_match - T_1148[2] <= T_1062.io.has_acquire_match - T_1148[3] <= T_1063.io.has_acquire_match - T_1148[4] <= T_1064.io.has_acquire_match - T_1148[5] <= T_1065.io.has_acquire_match - T_1148[6] <= T_1066.io.has_acquire_match - T_1148[7] <= T_1067.io.has_acquire_match - node T_1158 = cat(T_1148[7], T_1148[6]) - node T_1159 = cat(T_1148[5], T_1148[4]) - node T_1160 = cat(T_1158, T_1159) - node T_1161 = cat(T_1148[3], T_1148[2]) - node T_1162 = cat(T_1148[1], T_1148[0]) - node T_1163 = cat(T_1161, T_1162) - node acquireMatches = cat(T_1160, T_1163) - wire T_1166 : UInt<1>[8] - T_1166[0] <= T_1060.io.inner.acquire.ready - T_1166[1] <= T_1061.io.inner.acquire.ready - T_1166[2] <= T_1062.io.inner.acquire.ready - T_1166[3] <= T_1063.io.inner.acquire.ready - T_1166[4] <= T_1064.io.inner.acquire.ready - T_1166[5] <= T_1065.io.inner.acquire.ready - T_1166[6] <= T_1066.io.inner.acquire.ready - T_1166[7] <= T_1067.io.inner.acquire.ready - node T_1176 = cat(T_1166[7], T_1166[6]) - node T_1177 = cat(T_1166[5], T_1166[4]) - node T_1178 = cat(T_1176, T_1177) - node T_1179 = cat(T_1166[3], T_1166[2]) - node T_1180 = cat(T_1166[1], T_1166[0]) - node T_1181 = cat(T_1179, T_1180) - node acquireReadys = cat(T_1178, T_1181) - node T_1184 = neq(acquireMatches, UInt<1>("h0")) - node T_1185 = bits(acquireMatches, 0, 0) - node T_1186 = bits(acquireMatches, 1, 1) - node T_1187 = bits(acquireMatches, 2, 2) - node T_1188 = bits(acquireMatches, 3, 3) - node T_1189 = bits(acquireMatches, 4, 4) - node T_1190 = bits(acquireMatches, 5, 5) - node T_1191 = bits(acquireMatches, 6, 6) - node T_1192 = bits(acquireMatches, 7, 7) - wire T_1194 : UInt<1>[8] - T_1194[0] <= T_1185 - T_1194[1] <= T_1186 - T_1194[2] <= T_1187 - T_1194[3] <= T_1188 - T_1194[4] <= T_1189 - T_1194[5] <= T_1190 - T_1194[6] <= T_1191 - T_1194[7] <= T_1192 - node T_1212 = mux(T_1194[6], UInt<3>("h6"), UInt<3>("h7")) - node T_1213 = mux(T_1194[5], UInt<3>("h5"), T_1212) - node T_1214 = mux(T_1194[4], UInt<3>("h4"), T_1213) - node T_1215 = mux(T_1194[3], UInt<2>("h3"), T_1214) - node T_1216 = mux(T_1194[2], UInt<2>("h2"), T_1215) - node T_1217 = mux(T_1194[1], UInt<1>("h1"), T_1216) - node T_1218 = mux(T_1194[0], UInt<1>("h0"), T_1217) - node T_1219 = bits(acquireReadys, 0, 0) - node T_1220 = bits(acquireReadys, 1, 1) - node T_1221 = bits(acquireReadys, 2, 2) - node T_1222 = bits(acquireReadys, 3, 3) - node T_1223 = bits(acquireReadys, 4, 4) - node T_1224 = bits(acquireReadys, 5, 5) - node T_1225 = bits(acquireReadys, 6, 6) - node T_1226 = bits(acquireReadys, 7, 7) - wire T_1228 : UInt<1>[8] - T_1228[0] <= T_1219 - T_1228[1] <= T_1220 - T_1228[2] <= T_1221 - T_1228[3] <= T_1222 - T_1228[4] <= T_1223 - T_1228[5] <= T_1224 - T_1228[6] <= T_1225 - T_1228[7] <= T_1226 - node T_1246 = mux(T_1228[6], UInt<3>("h6"), UInt<3>("h7")) - node T_1247 = mux(T_1228[5], UInt<3>("h5"), T_1246) - node T_1248 = mux(T_1228[4], UInt<3>("h4"), T_1247) - node T_1249 = mux(T_1228[3], UInt<2>("h3"), T_1248) - node T_1250 = mux(T_1228[2], UInt<2>("h2"), T_1249) - node T_1251 = mux(T_1228[1], UInt<1>("h1"), T_1250) - node T_1252 = mux(T_1228[0], UInt<1>("h0"), T_1251) - node acquire_idx = mux(T_1184, T_1218, T_1252) - node T_1255 = neq(acquireConflicts, UInt<1>("h0")) - node T_1257 = eq(sdq_rdy, UInt<1>("h0")) - node block_acquires = or(T_1255, T_1257) - node T_1260 = neq(acquireReadys, UInt<1>("h0")) - node T_1262 = eq(block_acquires, UInt<1>("h0")) - node T_1263 = and(T_1260, T_1262) - io.inner.acquire.ready <= T_1263 - T_1060.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1310 : { idx : UInt<2>, loc : UInt<2>} - T_1310 is invalid - T_1310.idx <= sdq_alloc_id - T_1310.loc <= UInt<1>("h0") - node T_1356 = cat(T_1310.idx, T_1310.loc) - T_1060.io.inner.acquire.bits.data <= T_1356 - node T_1358 = eq(block_acquires, UInt<1>("h0")) - node T_1359 = and(io.inner.acquire.valid, T_1358) - node T_1361 = eq(acquire_idx, UInt<1>("h0")) - node T_1362 = and(T_1359, T_1361) - T_1060.io.inner.acquire.valid <= T_1362 - T_1061.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1409 : { idx : UInt<2>, loc : UInt<2>} - T_1409 is invalid - T_1409.idx <= sdq_alloc_id - T_1409.loc <= UInt<1>("h0") - node T_1455 = cat(T_1409.idx, T_1409.loc) - T_1061.io.inner.acquire.bits.data <= T_1455 - node T_1457 = eq(block_acquires, UInt<1>("h0")) - node T_1458 = and(io.inner.acquire.valid, T_1457) - node T_1460 = eq(acquire_idx, UInt<1>("h1")) - node T_1461 = and(T_1458, T_1460) - T_1061.io.inner.acquire.valid <= T_1461 - T_1062.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1508 : { idx : UInt<2>, loc : UInt<2>} - T_1508 is invalid - T_1508.idx <= sdq_alloc_id - T_1508.loc <= UInt<1>("h0") - node T_1554 = cat(T_1508.idx, T_1508.loc) - T_1062.io.inner.acquire.bits.data <= T_1554 - node T_1556 = eq(block_acquires, UInt<1>("h0")) - node T_1557 = and(io.inner.acquire.valid, T_1556) - node T_1559 = eq(acquire_idx, UInt<2>("h2")) - node T_1560 = and(T_1557, T_1559) - T_1062.io.inner.acquire.valid <= T_1560 - T_1063.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1607 : { idx : UInt<2>, loc : UInt<2>} - T_1607 is invalid - T_1607.idx <= sdq_alloc_id - T_1607.loc <= UInt<1>("h0") - node T_1653 = cat(T_1607.idx, T_1607.loc) - T_1063.io.inner.acquire.bits.data <= T_1653 - node T_1655 = eq(block_acquires, UInt<1>("h0")) - node T_1656 = and(io.inner.acquire.valid, T_1655) - node T_1658 = eq(acquire_idx, UInt<2>("h3")) - node T_1659 = and(T_1656, T_1658) - T_1063.io.inner.acquire.valid <= T_1659 - T_1064.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1706 : { idx : UInt<2>, loc : UInt<2>} - T_1706 is invalid - T_1706.idx <= sdq_alloc_id - T_1706.loc <= UInt<1>("h0") - node T_1752 = cat(T_1706.idx, T_1706.loc) - T_1064.io.inner.acquire.bits.data <= T_1752 - node T_1754 = eq(block_acquires, UInt<1>("h0")) - node T_1755 = and(io.inner.acquire.valid, T_1754) - node T_1757 = eq(acquire_idx, UInt<3>("h4")) - node T_1758 = and(T_1755, T_1757) - T_1064.io.inner.acquire.valid <= T_1758 - T_1065.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1805 : { idx : UInt<2>, loc : UInt<2>} - T_1805 is invalid - T_1805.idx <= sdq_alloc_id - T_1805.loc <= UInt<1>("h0") - node T_1851 = cat(T_1805.idx, T_1805.loc) - T_1065.io.inner.acquire.bits.data <= T_1851 - node T_1853 = eq(block_acquires, UInt<1>("h0")) - node T_1854 = and(io.inner.acquire.valid, T_1853) - node T_1856 = eq(acquire_idx, UInt<3>("h5")) - node T_1857 = and(T_1854, T_1856) - T_1065.io.inner.acquire.valid <= T_1857 - T_1066.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1904 : { idx : UInt<2>, loc : UInt<2>} - T_1904 is invalid - T_1904.idx <= sdq_alloc_id - T_1904.loc <= UInt<1>("h0") - node T_1950 = cat(T_1904.idx, T_1904.loc) - T_1066.io.inner.acquire.bits.data <= T_1950 - node T_1952 = eq(block_acquires, UInt<1>("h0")) - node T_1953 = and(io.inner.acquire.valid, T_1952) - node T_1955 = eq(acquire_idx, UInt<3>("h6")) - node T_1956 = and(T_1953, T_1955) - T_1066.io.inner.acquire.valid <= T_1956 - T_1067.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_2003 : { idx : UInt<2>, loc : UInt<2>} - T_2003 is invalid - T_2003.idx <= sdq_alloc_id - T_2003.loc <= UInt<1>("h0") - node T_2049 = cat(T_2003.idx, T_2003.loc) - T_1067.io.inner.acquire.bits.data <= T_2049 - node T_2051 = eq(block_acquires, UInt<1>("h0")) - node T_2052 = and(io.inner.acquire.valid, T_2051) - node T_2054 = eq(acquire_idx, UInt<3>("h7")) - node T_2055 = and(T_2052, T_2054) - T_1067.io.inner.acquire.valid <= T_2055 - node T_2056 = and(io.inner.release.ready, io.inner.release.valid) - node T_2057 = and(T_2056, io.inner.release.bits.voluntary) - wire T_2059 : UInt<2>[3] - T_2059[0] <= UInt<1>("h0") - T_2059[1] <= UInt<1>("h1") - T_2059[2] <= UInt<2>("h2") - node T_2064 = eq(T_2059[0], io.inner.release.bits.r_type) - node T_2065 = eq(T_2059[1], io.inner.release.bits.r_type) - node T_2066 = eq(T_2059[2], io.inner.release.bits.r_type) - node T_2068 = or(UInt<1>("h0"), T_2064) - node T_2069 = or(T_2068, T_2065) - node T_2070 = or(T_2069, T_2066) - node vwbdq_enq = and(T_2057, T_2070) - reg rel_data_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when vwbdq_enq : - node T_2075 = eq(rel_data_cnt, UInt<2>("h3")) - node T_2077 = and(UInt<1>("h0"), T_2075) - node T_2080 = add(rel_data_cnt, UInt<1>("h1")) - node T_2081 = tail(T_2080, 1) - node T_2082 = mux(T_2077, UInt<1>("h0"), T_2081) - rel_data_cnt <= T_2082 - skip - node rel_data_done = and(vwbdq_enq, T_2075) - reg vwbdq : UInt<128>[4], clk with : - reset => (UInt<1>("h0"), vwbdq) - when vwbdq_enq : - vwbdq[rel_data_cnt] <= io.inner.release.bits.data - skip - wire T_2101 : UInt<1>[8] - T_2101[0] <= T_1060.io.inner.release.ready - T_2101[1] <= T_1061.io.inner.release.ready - T_2101[2] <= T_1062.io.inner.release.ready - T_2101[3] <= T_1063.io.inner.release.ready - T_2101[4] <= T_1064.io.inner.release.ready - T_2101[5] <= T_1065.io.inner.release.ready - T_2101[6] <= T_1066.io.inner.release.ready - T_2101[7] <= T_1067.io.inner.release.ready - node T_2111 = cat(T_2101[7], T_2101[6]) - node T_2112 = cat(T_2101[5], T_2101[4]) - node T_2113 = cat(T_2111, T_2112) - node T_2114 = cat(T_2101[3], T_2101[2]) - node T_2115 = cat(T_2101[1], T_2101[0]) - node T_2116 = cat(T_2114, T_2115) - node releaseReadys = cat(T_2113, T_2116) - wire T_2119 : UInt<1>[8] - T_2119[0] <= T_1060.io.has_release_match - T_2119[1] <= T_1061.io.has_release_match - T_2119[2] <= T_1062.io.has_release_match - T_2119[3] <= T_1063.io.has_release_match - T_2119[4] <= T_1064.io.has_release_match - T_2119[5] <= T_1065.io.has_release_match - T_2119[6] <= T_1066.io.has_release_match - T_2119[7] <= T_1067.io.has_release_match - node T_2129 = cat(T_2119[7], T_2119[6]) - node T_2130 = cat(T_2119[5], T_2119[4]) - node T_2131 = cat(T_2129, T_2130) - node T_2132 = cat(T_2119[3], T_2119[2]) - node T_2133 = cat(T_2119[1], T_2119[0]) - node T_2134 = cat(T_2132, T_2133) - node releaseMatches = cat(T_2131, T_2134) - node T_2136 = bits(releaseMatches, 0, 0) - node T_2137 = bits(releaseMatches, 1, 1) - node T_2138 = bits(releaseMatches, 2, 2) - node T_2139 = bits(releaseMatches, 3, 3) - node T_2140 = bits(releaseMatches, 4, 4) - node T_2141 = bits(releaseMatches, 5, 5) - node T_2142 = bits(releaseMatches, 6, 6) - node T_2143 = bits(releaseMatches, 7, 7) - wire T_2145 : UInt<1>[8] - T_2145[0] <= T_2136 - T_2145[1] <= T_2137 - T_2145[2] <= T_2138 - T_2145[3] <= T_2139 - T_2145[4] <= T_2140 - T_2145[5] <= T_2141 - T_2145[6] <= T_2142 - T_2145[7] <= T_2143 - node T_2163 = mux(T_2145[6], UInt<3>("h6"), UInt<3>("h7")) - node T_2164 = mux(T_2145[5], UInt<3>("h5"), T_2163) - node T_2165 = mux(T_2145[4], UInt<3>("h4"), T_2164) - node T_2166 = mux(T_2145[3], UInt<2>("h3"), T_2165) - node T_2167 = mux(T_2145[2], UInt<2>("h2"), T_2166) - node T_2168 = mux(T_2145[1], UInt<1>("h1"), T_2167) - node release_idx = mux(T_2145[0], UInt<1>("h0"), T_2168) - node T_2170 = dshr(releaseReadys, release_idx) - node T_2171 = bits(T_2170, 0, 0) - io.inner.release.ready <= T_2171 - node T_2173 = eq(release_idx, UInt<1>("h0")) - node T_2174 = and(io.inner.release.valid, T_2173) - T_1060.io.inner.release.valid <= T_2174 - T_1060.io.inner.release.bits <- io.inner.release.bits - wire T_2221 : { idx : UInt<2>, loc : UInt<2>} - T_2221 is invalid - T_2221.idx <= rel_data_cnt - T_2221.loc <= UInt<1>("h1") - node T_2267 = cat(T_2221.idx, T_2221.loc) - T_1060.io.inner.release.bits.data <= T_2267 - node T_2269 = eq(release_idx, UInt<1>("h1")) - node T_2270 = and(io.inner.release.valid, T_2269) - T_1061.io.inner.release.valid <= T_2270 - T_1061.io.inner.release.bits <- io.inner.release.bits - wire T_2317 : { idx : UInt<2>, loc : UInt<2>} - T_2317 is invalid - T_2317.idx <= rel_data_cnt - T_2317.loc <= UInt<2>("h2") - node T_2363 = cat(T_2317.idx, T_2317.loc) - T_1061.io.inner.release.bits.data <= T_2363 - node T_2365 = eq(release_idx, UInt<2>("h2")) - node T_2366 = and(io.inner.release.valid, T_2365) - T_1062.io.inner.release.valid <= T_2366 - T_1062.io.inner.release.bits <- io.inner.release.bits - wire T_2413 : { idx : UInt<2>, loc : UInt<2>} - T_2413 is invalid - T_2413.idx <= rel_data_cnt - T_2413.loc <= UInt<2>("h2") - node T_2459 = cat(T_2413.idx, T_2413.loc) - T_1062.io.inner.release.bits.data <= T_2459 - node T_2461 = eq(release_idx, UInt<2>("h3")) - node T_2462 = and(io.inner.release.valid, T_2461) - T_1063.io.inner.release.valid <= T_2462 - T_1063.io.inner.release.bits <- io.inner.release.bits - wire T_2509 : { idx : UInt<2>, loc : UInt<2>} - T_2509 is invalid - T_2509.idx <= rel_data_cnt - T_2509.loc <= UInt<2>("h2") - node T_2555 = cat(T_2509.idx, T_2509.loc) - T_1063.io.inner.release.bits.data <= T_2555 - node T_2557 = eq(release_idx, UInt<3>("h4")) - node T_2558 = and(io.inner.release.valid, T_2557) - T_1064.io.inner.release.valid <= T_2558 - T_1064.io.inner.release.bits <- io.inner.release.bits - wire T_2605 : { idx : UInt<2>, loc : UInt<2>} - T_2605 is invalid - T_2605.idx <= rel_data_cnt - T_2605.loc <= UInt<2>("h2") - node T_2651 = cat(T_2605.idx, T_2605.loc) - T_1064.io.inner.release.bits.data <= T_2651 - node T_2653 = eq(release_idx, UInt<3>("h5")) - node T_2654 = and(io.inner.release.valid, T_2653) - T_1065.io.inner.release.valid <= T_2654 - T_1065.io.inner.release.bits <- io.inner.release.bits - wire T_2701 : { idx : UInt<2>, loc : UInt<2>} - T_2701 is invalid - T_2701.idx <= rel_data_cnt - T_2701.loc <= UInt<2>("h2") - node T_2747 = cat(T_2701.idx, T_2701.loc) - T_1065.io.inner.release.bits.data <= T_2747 - node T_2749 = eq(release_idx, UInt<3>("h6")) - node T_2750 = and(io.inner.release.valid, T_2749) - T_1066.io.inner.release.valid <= T_2750 - T_1066.io.inner.release.bits <- io.inner.release.bits - wire T_2797 : { idx : UInt<2>, loc : UInt<2>} - T_2797 is invalid - T_2797.idx <= rel_data_cnt - T_2797.loc <= UInt<2>("h2") - node T_2843 = cat(T_2797.idx, T_2797.loc) - T_1066.io.inner.release.bits.data <= T_2843 - node T_2845 = eq(release_idx, UInt<3>("h7")) - node T_2846 = and(io.inner.release.valid, T_2845) - T_1067.io.inner.release.valid <= T_2846 - T_1067.io.inner.release.bits <- io.inner.release.bits - wire T_2893 : { idx : UInt<2>, loc : UInt<2>} - T_2893 is invalid - T_2893.idx <= rel_data_cnt - T_2893.loc <= UInt<2>("h2") - node T_2939 = cat(T_2893.idx, T_2893.loc) - T_1067.io.inner.release.bits.data <= T_2939 - node T_2941 = neq(releaseMatches, UInt<1>("h0")) - node T_2943 = eq(T_2941, UInt<1>("h0")) - node T_2944 = and(io.inner.release.valid, T_2943) - node T_2946 = eq(T_2944, UInt<1>("h0")) - node T_2948 = eq(reset, UInt<1>("h0")) - when T_2948 : - node T_2950 = eq(T_2946, UInt<1>("h0")) - when T_2950 : - node T_2952 = eq(reset, UInt<1>("h0")) - when T_2952 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - inst T_2953 of LockingRRArbiter_33 - T_2953.io is invalid - T_2953.clk <= clk - T_2953.reset <= reset - io.inner.grant <- T_2953.io.out - T_2953.io.in[0] <- T_1060.io.inner.grant - T_2953.io.in[1] <- T_1061.io.inner.grant - T_2953.io.in[2] <- T_1062.io.inner.grant - T_2953.io.in[3] <- T_1063.io.inner.grant - T_2953.io.in[4] <- T_1064.io.inner.grant - T_2953.io.in[5] <- T_1065.io.inner.grant - T_2953.io.in[6] <- T_1066.io.inner.grant - T_2953.io.in[7] <- T_1067.io.inner.grant - io.inner.grant.bits.data <= io.outer.grant.bits.data - io.inner.grant.bits.addr_beat <= io.outer.grant.bits.addr_beat - inst T_2954 of LockingRRArbiter_34 - T_2954.io is invalid - T_2954.clk <= clk - T_2954.reset <= reset - io.inner.probe <- T_2954.io.out - T_2954.io.in[0] <- T_1060.io.inner.probe - T_2954.io.in[1] <- T_1061.io.inner.probe - T_2954.io.in[2] <- T_1062.io.inner.probe - T_2954.io.in[3] <- T_1063.io.inner.probe - T_2954.io.in[4] <- T_1064.io.inner.probe - T_2954.io.in[5] <- T_1065.io.inner.probe - T_2954.io.in[6] <- T_1066.io.inner.probe - T_2954.io.in[7] <- T_1067.io.inner.probe - T_1060.io.inner.finish.bits <- io.inner.finish.bits - T_1061.io.inner.finish.bits <- io.inner.finish.bits - T_1062.io.inner.finish.bits <- io.inner.finish.bits - T_1063.io.inner.finish.bits <- io.inner.finish.bits - T_1064.io.inner.finish.bits <- io.inner.finish.bits - T_1065.io.inner.finish.bits <- io.inner.finish.bits - T_1066.io.inner.finish.bits <- io.inner.finish.bits - T_1067.io.inner.finish.bits <- io.inner.finish.bits - node T_2956 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h0")) - node T_2957 = and(io.inner.finish.valid, T_2956) - T_1060.io.inner.finish.valid <= T_2957 - node T_2959 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h1")) - node T_2960 = and(io.inner.finish.valid, T_2959) - T_1061.io.inner.finish.valid <= T_2960 - node T_2962 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h2")) - node T_2963 = and(io.inner.finish.valid, T_2962) - T_1062.io.inner.finish.valid <= T_2963 - node T_2965 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h3")) - node T_2966 = and(io.inner.finish.valid, T_2965) - T_1063.io.inner.finish.valid <= T_2966 - node T_2968 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h4")) - node T_2969 = and(io.inner.finish.valid, T_2968) - T_1064.io.inner.finish.valid <= T_2969 - node T_2971 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h5")) - node T_2972 = and(io.inner.finish.valid, T_2971) - T_1065.io.inner.finish.valid <= T_2972 - node T_2974 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h6")) - node T_2975 = and(io.inner.finish.valid, T_2974) - T_1066.io.inner.finish.valid <= T_2975 - node T_2977 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h7")) - node T_2978 = and(io.inner.finish.valid, T_2977) - T_1067.io.inner.finish.valid <= T_2978 - wire T_2980 : UInt<1>[8] - T_2980[0] <= T_1060.io.inner.finish.ready - T_2980[1] <= T_1061.io.inner.finish.ready - T_2980[2] <= T_1062.io.inner.finish.ready - T_2980[3] <= T_1063.io.inner.finish.ready - T_2980[4] <= T_1064.io.inner.finish.ready - T_2980[5] <= T_1065.io.inner.finish.ready - T_2980[6] <= T_1066.io.inner.finish.ready - T_2980[7] <= T_1067.io.inner.finish.ready - io.inner.finish.ready <= T_2980[io.inner.finish.bits.manager_xact_id] - inst outer_arb of ClientUncachedTileLinkIOArbiter - outer_arb.io is invalid - outer_arb.clk <= clk - outer_arb.reset <= reset - outer_arb.io.in[0] <- T_1060.io.outer - outer_arb.io.in[1] <- T_1061.io.outer - outer_arb.io.in[2] <- T_1062.io.outer - outer_arb.io.in[3] <- T_1063.io.outer - outer_arb.io.in[4] <- T_1064.io.outer - outer_arb.io.in[5] <- T_1065.io.outer - outer_arb.io.in[6] <- T_1066.io.outer - outer_arb.io.in[7] <- T_1067.io.outer - wire outer_data_ptr : { idx : UInt<2>, loc : UInt<2>} - outer_data_ptr is invalid - node T_3130 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) - outer_data_ptr.loc <= T_3130 - node T_3131 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) - outer_data_ptr.idx <= T_3131 - node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h0")) - node T_3133 = and(io.outer.acquire.ready, io.outer.acquire.valid) - wire T_3138 : UInt<3>[3] - T_3138[0] <= UInt<3>("h2") - T_3138[1] <= UInt<3>("h3") - T_3138[2] <= UInt<3>("h4") - node T_3143 = eq(T_3138[0], io.outer.acquire.bits.a_type) - node T_3144 = eq(T_3138[1], io.outer.acquire.bits.a_type) - node T_3145 = eq(T_3138[2], io.outer.acquire.bits.a_type) - node T_3147 = or(UInt<1>("h0"), T_3143) - node T_3148 = or(T_3147, T_3144) - node T_3149 = or(T_3148, T_3145) - node T_3150 = and(io.outer.acquire.bits.is_builtin_type, T_3149) - node T_3151 = and(T_3133, T_3150) - node T_3152 = eq(outer_data_ptr.loc, UInt<1>("h0")) - node free_sdq = and(T_3151, T_3152) - io.outer <- outer_arb.io.out - node T_3156 = eq(UInt<1>("h1"), outer_data_ptr.loc) - node T_3157 = mux(T_3156, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data) - node T_3158 = eq(UInt<1>("h0"), outer_data_ptr.loc) - node T_3159 = mux(T_3158, sdq[outer_data_ptr.idx], T_3157) - io.outer.acquire.bits.data <= T_3159 - node T_3160 = or(io.outer.acquire.valid, sdq_enq) - when T_3160 : - node T_3162 = dshl(UInt<1>("h1"), outer_data_ptr.idx) - node T_3164 = sub(UInt<4>("h0"), free_sdq) - node T_3165 = tail(T_3164, 1) - node T_3166 = and(T_3162, T_3165) - node T_3167 = not(T_3166) - node T_3168 = and(sdq_val, T_3167) - node T_3169 = bits(sdq_val, 3, 0) - node T_3170 = not(T_3169) - node T_3171 = bits(T_3170, 0, 0) - node T_3172 = bits(T_3170, 1, 1) - node T_3173 = bits(T_3170, 2, 2) - node T_3174 = bits(T_3170, 3, 3) - wire T_3180 : UInt<4>[4] - T_3180[0] <= UInt<4>("h1") - T_3180[1] <= UInt<4>("h2") - T_3180[2] <= UInt<4>("h4") - T_3180[3] <= UInt<4>("h8") - node T_3188 = mux(T_3174, T_3180[3], UInt<4>("h0")) - node T_3189 = mux(T_3173, T_3180[2], T_3188) - node T_3190 = mux(T_3172, T_3180[1], T_3189) - node T_3191 = mux(T_3171, T_3180[0], T_3190) - node T_3193 = sub(UInt<4>("h0"), sdq_enq) - node T_3194 = tail(T_3193, 1) - node T_3195 = and(T_3191, T_3194) - node T_3196 = or(T_3168, T_3195) - sdq_val <= T_3196 - skip - module Queue_36 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_187 - writer => T_146 - ram.T_187.addr is invalid - ram.T_187.clk <= clk - ram.T_187.en <= UInt<1>("h0") - ram.T_146.addr is invalid - ram.T_146.clk <= clk - ram.T_146.en <= UInt<1>("h0") - ram.T_146.data is invalid - ram.T_146.mask.addr <= UInt<1>("h0") - ram.T_146.mask.len <= UInt<1>("h0") - ram.T_146.mask.size <= UInt<1>("h0") - ram.T_146.mask.burst <= UInt<1>("h0") - ram.T_146.mask.lock <= UInt<1>("h0") - ram.T_146.mask.cache <= UInt<1>("h0") - ram.T_146.mask.prot <= UInt<1>("h0") - ram.T_146.mask.qos <= UInt<1>("h0") - ram.T_146.mask.region <= UInt<1>("h0") - ram.T_146.mask.id <= UInt<1>("h0") - ram.T_146.mask.user <= UInt<1>("h0") - reg T_125 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_127 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_125, T_127) - node T_132 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_132) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_138 = and(io.enq.ready, io.enq.valid) - node T_140 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_138, T_140) - node T_142 = and(io.deq.ready, io.deq.valid) - node T_144 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_142, T_144) - when do_enq : - ram.T_146.addr <= T_125 - ram.T_146.en <= UInt<1>("h1") - ram.T_146.data <- io.enq.bits - ram.T_146.mask.addr <= UInt<1>("h1") - ram.T_146.mask.len <= UInt<1>("h1") - ram.T_146.mask.size <= UInt<1>("h1") - ram.T_146.mask.burst <= UInt<1>("h1") - ram.T_146.mask.lock <= UInt<1>("h1") - ram.T_146.mask.cache <= UInt<1>("h1") - ram.T_146.mask.prot <= UInt<1>("h1") - ram.T_146.mask.qos <= UInt<1>("h1") - ram.T_146.mask.region <= UInt<1>("h1") - ram.T_146.mask.id <= UInt<1>("h1") - ram.T_146.mask.user <= UInt<1>("h1") - node T_159 = eq(T_125, UInt<1>("h1")) - node T_161 = and(UInt<1>("h0"), T_159) - node T_164 = add(T_125, UInt<1>("h1")) - node T_165 = tail(T_164, 1) - node T_166 = mux(T_161, UInt<1>("h0"), T_165) - T_125 <= T_166 - skip - when do_deq : - node T_168 = eq(T_127, UInt<1>("h1")) - node T_170 = and(UInt<1>("h0"), T_168) - node T_173 = add(T_127, UInt<1>("h1")) - node T_174 = tail(T_173, 1) - node T_175 = mux(T_170, UInt<1>("h0"), T_174) - T_127 <= T_175 - skip - node T_176 = neq(do_enq, do_deq) - when T_176 : - maybe_full <= do_enq - skip - node T_178 = eq(empty, UInt<1>("h0")) - node T_180 = and(UInt<1>("h0"), io.enq.valid) - node T_181 = or(T_178, T_180) - io.deq.valid <= T_181 - node T_183 = eq(full, UInt<1>("h0")) - node T_185 = and(UInt<1>("h0"), io.deq.ready) - node T_186 = or(T_183, T_185) - io.enq.ready <= T_186 - ram.T_187.addr <= T_127 - ram.T_187.en <= UInt<1>("h1") - node T_199 = mux(maybe_flow, io.enq.bits, ram.T_187.data) - io.deq.bits <- T_199 - node T_211 = sub(T_125, T_127) - node ptr_diff = tail(T_211, 1) - node T_213 = and(maybe_full, ptr_match) - node T_214 = cat(T_213, ptr_diff) - io.count <= T_214 - module Queue_37 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, count : UInt<2>} - io is invalid - mem ram : - data-type => UInt<5> - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_77 - writer => T_47 - ram.T_77.addr is invalid - ram.T_77.clk <= clk - ram.T_77.en <= UInt<1>("h0") - ram.T_47.addr is invalid - ram.T_47.clk <= clk - ram.T_47.en <= UInt<1>("h0") - ram.T_47.data is invalid - ram.T_47.mask <= UInt<1>("h0") - reg T_26 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_28 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_26, T_28) - node T_33 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_33) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_39 = and(io.enq.ready, io.enq.valid) - node T_41 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_39, T_41) - node T_43 = and(io.deq.ready, io.deq.valid) - node T_45 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_43, T_45) - when do_enq : - ram.T_47.addr <= T_26 - ram.T_47.en <= UInt<1>("h1") - ram.T_47.data <= io.enq.bits - ram.T_47.mask <= UInt<1>("h1") - node T_49 = eq(T_26, UInt<1>("h1")) - node T_51 = and(UInt<1>("h0"), T_49) - node T_54 = add(T_26, UInt<1>("h1")) - node T_55 = tail(T_54, 1) - node T_56 = mux(T_51, UInt<1>("h0"), T_55) - T_26 <= T_56 - skip - when do_deq : - node T_58 = eq(T_28, UInt<1>("h1")) - node T_60 = and(UInt<1>("h0"), T_58) - node T_63 = add(T_28, UInt<1>("h1")) - node T_64 = tail(T_63, 1) - node T_65 = mux(T_60, UInt<1>("h0"), T_64) - T_28 <= T_65 - skip - node T_66 = neq(do_enq, do_deq) - when T_66 : - maybe_full <= do_enq - skip - node T_68 = eq(empty, UInt<1>("h0")) - node T_70 = and(UInt<1>("h0"), io.enq.valid) - node T_71 = or(T_68, T_70) - io.deq.valid <= T_71 - node T_73 = eq(full, UInt<1>("h0")) - node T_75 = and(UInt<1>("h0"), io.deq.ready) - node T_76 = or(T_73, T_75) - io.enq.ready <= T_76 - ram.T_77.addr <= T_28 - ram.T_77.en <= UInt<1>("h1") - node T_78 = mux(maybe_flow, io.enq.bits, ram.T_77.data) - io.deq.bits <= T_78 - node T_79 = sub(T_26, T_28) - node ptr_diff = tail(T_79, 1) - node T_81 = and(maybe_full, ptr_match) - node T_82 = cat(T_81, ptr_diff) - io.count <= T_82 - module NastiErrorSlave : - input clk : Clock - input reset : UInt<1> - input io : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - node T_322 = and(io.ar.ready, io.ar.valid) - when T_322 : - node T_324 = eq(reset, UInt<1>("h0")) - when T_324 : - printf(clk, UInt<1>("h1"), "Invalid read address %x\n", io.ar.bits.addr) - skip - skip - node T_325 = and(io.aw.ready, io.aw.valid) - when T_325 : - node T_327 = eq(reset, UInt<1>("h0")) - when T_327 : - printf(clk, UInt<1>("h1"), "Invalid write address %x\n", io.aw.bits.addr) - skip - skip - inst r_queue of Queue_36 - r_queue.io is invalid - r_queue.clk <= clk - r_queue.reset <= reset - r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg beats_left : UInt<8>, clk with : - reset => (reset, UInt<8>("h0")) - node T_346 = eq(responding, UInt<1>("h0")) - node T_347 = and(T_346, r_queue.io.deq.valid) - when T_347 : - responding <= UInt<1>("h1") - beats_left <= r_queue.io.deq.bits.len - skip - node T_349 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_349 - io.r.bits.id <= r_queue.io.deq.bits.id - io.r.bits.data <= UInt<1>("h0") - io.r.bits.resp <= UInt<2>("h3") - node T_359 = eq(beats_left, UInt<1>("h0")) - io.r.bits.last <= T_359 - node T_360 = and(io.r.ready, io.r.valid) - node T_361 = and(T_360, io.r.bits.last) - r_queue.io.deq.ready <= T_361 - node T_362 = and(io.r.ready, io.r.valid) - when T_362 : - node T_364 = eq(beats_left, UInt<1>("h0")) - when T_364 : - responding <= UInt<1>("h0") - skip - node T_367 = eq(T_364, UInt<1>("h0")) - when T_367 : - node T_369 = sub(beats_left, UInt<1>("h1")) - node T_370 = tail(T_369, 1) - beats_left <= T_370 - skip - skip - reg draining : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - io.w.ready <= draining - node T_373 = and(io.aw.ready, io.aw.valid) - when T_373 : - draining <= UInt<1>("h1") - skip - node T_375 = and(io.w.ready, io.w.valid) - node T_376 = and(T_375, io.w.bits.last) - when T_376 : - draining <= UInt<1>("h0") - skip - inst b_queue of Queue_37 - b_queue.io is invalid - b_queue.clk <= clk - b_queue.reset <= reset - node T_381 = eq(draining, UInt<1>("h0")) - node T_382 = and(io.aw.valid, T_381) - b_queue.io.enq.valid <= T_382 - b_queue.io.enq.bits <= io.aw.bits.id - node T_384 = eq(draining, UInt<1>("h0")) - node T_385 = and(b_queue.io.enq.ready, T_384) - io.aw.ready <= T_385 - node T_387 = eq(draining, UInt<1>("h0")) - node T_388 = and(b_queue.io.deq.valid, T_387) - io.b.valid <= T_388 - io.b.bits.id <= b_queue.io.deq.bits - io.b.bits.resp <= UInt<2>("h3") - node T_391 = eq(draining, UInt<1>("h0")) - node T_392 = and(io.b.ready, T_391) - b_queue.io.deq.ready <= T_392 - module RRArbiter_38 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<3>} - io is invalid - wire T_196 : UInt<3> - T_196 is invalid - io.out.valid <= io.in[T_196].valid - io.out.bits <- io.in[T_196].bits - io.chosen <= T_196 - io.in[T_196].ready <= UInt<1>("h0") - reg T_233 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_234 = gt(UInt<1>("h0"), T_233) - node T_235 = and(io.in[0].valid, T_234) - node T_237 = gt(UInt<1>("h1"), T_233) - node T_238 = and(io.in[1].valid, T_237) - node T_240 = gt(UInt<2>("h2"), T_233) - node T_241 = and(io.in[2].valid, T_240) - node T_243 = gt(UInt<2>("h3"), T_233) - node T_244 = and(io.in[3].valid, T_243) - node T_246 = gt(UInt<3>("h4"), T_233) - node T_247 = and(io.in[4].valid, T_246) - node T_250 = or(UInt<1>("h0"), T_235) - node T_252 = eq(T_250, UInt<1>("h0")) - node T_254 = or(UInt<1>("h0"), T_235) - node T_255 = or(T_254, T_238) - node T_257 = eq(T_255, UInt<1>("h0")) - node T_259 = or(UInt<1>("h0"), T_235) - node T_260 = or(T_259, T_238) - node T_261 = or(T_260, T_241) - node T_263 = eq(T_261, UInt<1>("h0")) - node T_265 = or(UInt<1>("h0"), T_235) - node T_266 = or(T_265, T_238) - node T_267 = or(T_266, T_241) - node T_268 = or(T_267, T_244) - node T_270 = eq(T_268, UInt<1>("h0")) - node T_272 = or(UInt<1>("h0"), T_235) - node T_273 = or(T_272, T_238) - node T_274 = or(T_273, T_241) - node T_275 = or(T_274, T_244) - node T_276 = or(T_275, T_247) - node T_278 = eq(T_276, UInt<1>("h0")) - node T_280 = or(UInt<1>("h0"), T_235) - node T_281 = or(T_280, T_238) - node T_282 = or(T_281, T_241) - node T_283 = or(T_282, T_244) - node T_284 = or(T_283, T_247) - node T_285 = or(T_284, io.in[0].valid) - node T_287 = eq(T_285, UInt<1>("h0")) - node T_289 = or(UInt<1>("h0"), T_235) - node T_290 = or(T_289, T_238) - node T_291 = or(T_290, T_241) - node T_292 = or(T_291, T_244) - node T_293 = or(T_292, T_247) - node T_294 = or(T_293, io.in[0].valid) - node T_295 = or(T_294, io.in[1].valid) - node T_297 = eq(T_295, UInt<1>("h0")) - node T_299 = or(UInt<1>("h0"), T_235) - node T_300 = or(T_299, T_238) - node T_301 = or(T_300, T_241) - node T_302 = or(T_301, T_244) - node T_303 = or(T_302, T_247) - node T_304 = or(T_303, io.in[0].valid) - node T_305 = or(T_304, io.in[1].valid) - node T_306 = or(T_305, io.in[2].valid) - node T_308 = eq(T_306, UInt<1>("h0")) - node T_310 = or(UInt<1>("h0"), T_235) - node T_311 = or(T_310, T_238) - node T_312 = or(T_311, T_241) - node T_313 = or(T_312, T_244) - node T_314 = or(T_313, T_247) - node T_315 = or(T_314, io.in[0].valid) - node T_316 = or(T_315, io.in[1].valid) - node T_317 = or(T_316, io.in[2].valid) - node T_318 = or(T_317, io.in[3].valid) - node T_320 = eq(T_318, UInt<1>("h0")) - node T_322 = gt(UInt<1>("h0"), T_233) - node T_323 = and(UInt<1>("h1"), T_322) - node T_324 = or(T_323, T_278) - node T_326 = gt(UInt<1>("h1"), T_233) - node T_327 = and(T_252, T_326) - node T_328 = or(T_327, T_287) - node T_330 = gt(UInt<2>("h2"), T_233) - node T_331 = and(T_257, T_330) - node T_332 = or(T_331, T_297) - node T_334 = gt(UInt<2>("h3"), T_233) - node T_335 = and(T_263, T_334) - node T_336 = or(T_335, T_308) - node T_338 = gt(UInt<3>("h4"), T_233) - node T_339 = and(T_270, T_338) - node T_340 = or(T_339, T_320) - node T_342 = eq(UInt<3>("h4"), UInt<1>("h0")) - node T_343 = mux(UInt<1>("h0"), T_342, T_324) - node T_344 = and(T_343, io.out.ready) - io.in[0].ready <= T_344 - node T_346 = eq(UInt<3>("h4"), UInt<1>("h1")) - node T_347 = mux(UInt<1>("h0"), T_346, T_328) - node T_348 = and(T_347, io.out.ready) - io.in[1].ready <= T_348 - node T_350 = eq(UInt<3>("h4"), UInt<2>("h2")) - node T_351 = mux(UInt<1>("h0"), T_350, T_332) - node T_352 = and(T_351, io.out.ready) - io.in[2].ready <= T_352 - node T_354 = eq(UInt<3>("h4"), UInt<2>("h3")) - node T_355 = mux(UInt<1>("h0"), T_354, T_336) - node T_356 = and(T_355, io.out.ready) - io.in[3].ready <= T_356 - node T_358 = eq(UInt<3>("h4"), UInt<3>("h4")) - node T_359 = mux(UInt<1>("h0"), T_358, T_340) - node T_360 = and(T_359, io.out.ready) - io.in[4].ready <= T_360 - node T_363 = mux(io.in[3].valid, UInt<2>("h3"), UInt<3>("h4")) - node T_365 = mux(io.in[2].valid, UInt<2>("h2"), T_363) - node T_367 = mux(io.in[1].valid, UInt<1>("h1"), T_365) - node T_369 = mux(io.in[0].valid, UInt<1>("h0"), T_367) - node T_371 = gt(UInt<3>("h4"), T_233) - node T_372 = and(io.in[4].valid, T_371) - node T_374 = mux(T_372, UInt<3>("h4"), T_369) - node T_376 = gt(UInt<2>("h3"), T_233) - node T_377 = and(io.in[3].valid, T_376) - node T_379 = mux(T_377, UInt<2>("h3"), T_374) - node T_381 = gt(UInt<2>("h2"), T_233) - node T_382 = and(io.in[2].valid, T_381) - node T_384 = mux(T_382, UInt<2>("h2"), T_379) - node T_386 = gt(UInt<1>("h1"), T_233) - node T_387 = and(io.in[1].valid, T_386) - node T_389 = mux(T_387, UInt<1>("h1"), T_384) - node T_390 = mux(UInt<1>("h0"), UInt<3>("h4"), T_389) - T_196 <= T_390 - node T_391 = and(io.out.ready, io.out.valid) - when T_391 : - T_233 <= T_196 - skip - module JunctionsPeekingArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - reg T_273 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg T_275 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_277 : UInt<1>[5] - T_277[0] <= io.in[0].valid - T_277[1] <= io.in[1].valid - T_277[2] <= io.in[2].valid - T_277[3] <= io.in[3].valid - T_277[4] <= io.in[4].valid - node T_285 = add(T_273, UInt<1>("h1")) - node T_286 = tail(T_285, 1) - node T_288 = lt(T_286, UInt<3>("h5")) - node T_290 = add(UInt<1>("h0"), T_286) - node T_291 = tail(T_290, 1) - node T_294 = sub(T_286, UInt<3>("h5")) - node T_295 = tail(T_294, 1) - node T_297 = mux(T_288, T_277[T_291], T_277[T_295]) - node T_299 = lt(T_286, UInt<3>("h4")) - node T_301 = add(UInt<1>("h1"), T_286) - node T_302 = tail(T_301, 1) - node T_305 = sub(T_286, UInt<3>("h4")) - node T_306 = tail(T_305, 1) - node T_308 = mux(T_299, T_277[T_302], T_277[T_306]) - node T_310 = lt(T_286, UInt<2>("h3")) - node T_312 = add(UInt<2>("h2"), T_286) - node T_313 = tail(T_312, 1) - node T_316 = sub(T_286, UInt<2>("h3")) - node T_317 = tail(T_316, 1) - node T_319 = mux(T_310, T_277[T_313], T_277[T_317]) - node T_321 = lt(T_286, UInt<2>("h2")) - node T_323 = add(UInt<2>("h3"), T_286) - node T_324 = tail(T_323, 1) - node T_327 = sub(T_286, UInt<2>("h2")) - node T_328 = tail(T_327, 1) - node T_330 = mux(T_321, T_277[T_324], T_277[T_328]) - node T_332 = lt(T_286, UInt<1>("h1")) - node T_334 = add(UInt<3>("h4"), T_286) - node T_335 = tail(T_334, 1) - node T_338 = sub(T_286, UInt<1>("h1")) - node T_339 = tail(T_338, 1) - node T_341 = mux(T_332, T_277[T_335], T_277[T_339]) - wire T_343 : UInt<1>[5] - T_343[0] <= T_297 - T_343[1] <= T_308 - T_343[2] <= T_319 - T_343[3] <= T_330 - T_343[4] <= T_341 - wire T_356 : UInt<3>[5] - T_356[0] <= UInt<1>("h0") - T_356[1] <= UInt<1>("h1") - T_356[2] <= UInt<2>("h2") - T_356[3] <= UInt<2>("h3") - T_356[4] <= UInt<3>("h4") - node T_364 = add(T_273, UInt<1>("h1")) - node T_365 = tail(T_364, 1) - node T_367 = lt(T_365, UInt<3>("h5")) - node T_369 = add(UInt<1>("h0"), T_365) - node T_370 = tail(T_369, 1) - node T_373 = sub(T_365, UInt<3>("h5")) - node T_374 = tail(T_373, 1) - node T_376 = mux(T_367, T_356[T_370], T_356[T_374]) - node T_378 = lt(T_365, UInt<3>("h4")) - node T_380 = add(UInt<1>("h1"), T_365) - node T_381 = tail(T_380, 1) - node T_384 = sub(T_365, UInt<3>("h4")) - node T_385 = tail(T_384, 1) - node T_387 = mux(T_378, T_356[T_381], T_356[T_385]) - node T_389 = lt(T_365, UInt<2>("h3")) - node T_391 = add(UInt<2>("h2"), T_365) - node T_392 = tail(T_391, 1) - node T_395 = sub(T_365, UInt<2>("h3")) - node T_396 = tail(T_395, 1) - node T_398 = mux(T_389, T_356[T_392], T_356[T_396]) - node T_400 = lt(T_365, UInt<2>("h2")) - node T_402 = add(UInt<2>("h3"), T_365) - node T_403 = tail(T_402, 1) - node T_406 = sub(T_365, UInt<2>("h2")) - node T_407 = tail(T_406, 1) - node T_409 = mux(T_400, T_356[T_403], T_356[T_407]) - node T_411 = lt(T_365, UInt<1>("h1")) - node T_413 = add(UInt<3>("h4"), T_365) - node T_414 = tail(T_413, 1) - node T_417 = sub(T_365, UInt<1>("h1")) - node T_418 = tail(T_417, 1) - node T_420 = mux(T_411, T_356[T_414], T_356[T_418]) - wire T_422 : UInt<3>[5] - T_422[0] <= T_376 - T_422[1] <= T_387 - T_422[2] <= T_398 - T_422[3] <= T_409 - T_422[4] <= T_420 - node T_429 = mux(T_343[3], T_422[3], T_422[4]) - node T_430 = mux(T_343[2], T_422[2], T_429) - node T_431 = mux(T_343[1], T_422[1], T_430) - node T_432 = mux(T_343[0], T_422[0], T_431) - node T_433 = mux(T_275, T_273, T_432) - node T_435 = eq(T_433, UInt<1>("h0")) - node T_436 = and(io.out.ready, T_435) - io.in[0].ready <= T_436 - node T_438 = eq(T_433, UInt<1>("h1")) - node T_439 = and(io.out.ready, T_438) - io.in[1].ready <= T_439 - node T_441 = eq(T_433, UInt<2>("h2")) - node T_442 = and(io.out.ready, T_441) - io.in[2].ready <= T_442 - node T_444 = eq(T_433, UInt<2>("h3")) - node T_445 = and(io.out.ready, T_444) - io.in[3].ready <= T_445 - node T_447 = eq(T_433, UInt<3>("h4")) - node T_448 = and(io.out.ready, T_447) - io.in[4].ready <= T_448 - io.out.valid <= io.in[T_433].valid - io.out.bits <- io.in[T_433].bits - node T_479 = and(io.out.ready, io.out.valid) - when T_479 : - node T_481 = eq(T_275, UInt<1>("h0")) - node T_483 = and(T_481, UInt<1>("h1")) - when T_483 : - T_273 <= T_432 - T_275 <= UInt<1>("h1") - skip - when io.out.bits.last : - T_275 <= UInt<1>("h0") - skip - skip - module NastiRouter : - input clk : Clock - input reset : UInt<1> - output io : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io is invalid - node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h0")) - node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h40000000")) - node T_1440 = and(T_1437, T_1439) - node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h40000000")) - node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h60000000")) - node T_1445 = and(T_1442, T_1444) - node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h60000000")) - node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h80000000")) - node T_1450 = and(T_1447, T_1449) - node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h80000000")) - node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h100000000")) - node T_1455 = and(T_1452, T_1454) - wire T_1457 : UInt<1>[4] - T_1457[0] <= T_1440 - T_1457[1] <= T_1445 - T_1457[2] <= T_1450 - T_1457[3] <= T_1455 - node T_1463 = cat(T_1457[3], T_1457[2]) - node T_1464 = cat(T_1457[1], T_1457[0]) - node ar_route = cat(T_1463, T_1464) - node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h0")) - node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h40000000")) - node T_1470 = and(T_1467, T_1469) - node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h40000000")) - node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h60000000")) - node T_1475 = and(T_1472, T_1474) - node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h60000000")) - node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h80000000")) - node T_1480 = and(T_1477, T_1479) - node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h80000000")) - node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h100000000")) - node T_1485 = and(T_1482, T_1484) - wire T_1487 : UInt<1>[4] - T_1487[0] <= T_1470 - T_1487[1] <= T_1475 - T_1487[2] <= T_1480 - T_1487[3] <= T_1485 - node T_1493 = cat(T_1487[3], T_1487[2]) - node T_1494 = cat(T_1487[1], T_1487[0]) - node aw_route = cat(T_1493, T_1494) - node T_1499 = bits(ar_route, 0, 0) - node T_1500 = and(io.master.ar.valid, T_1499) - io.slave[0].ar.valid <= T_1500 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bits(ar_route, 0, 0) - node T_1502 = and(io.slave[0].ar.ready, T_1501) - node T_1503 = or(UInt<1>("h0"), T_1502) - node T_1504 = bits(aw_route, 0, 0) - node T_1505 = and(io.master.aw.valid, T_1504) - io.slave[0].aw.valid <= T_1505 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bits(aw_route, 0, 0) - node T_1507 = and(io.slave[0].aw.ready, T_1506) - node T_1508 = or(UInt<1>("h0"), T_1507) - reg T_1510 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1511 : - T_1510 <= UInt<1>("h1") - skip - node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1514 = and(T_1513, io.slave[0].w.bits.last) - when T_1514 : - T_1510 <= UInt<1>("h0") - skip - node T_1516 = and(io.master.w.valid, T_1510) - io.slave[0].w.valid <= T_1516 - io.slave[0].w.bits <- io.master.w.bits - node T_1517 = and(io.slave[0].w.ready, T_1510) - node T_1518 = or(UInt<1>("h0"), T_1517) - node T_1519 = bits(ar_route, 1, 1) - node T_1520 = and(io.master.ar.valid, T_1519) - io.slave[1].ar.valid <= T_1520 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bits(ar_route, 1, 1) - node T_1522 = and(io.slave[1].ar.ready, T_1521) - node T_1523 = or(T_1503, T_1522) - node T_1524 = bits(aw_route, 1, 1) - node T_1525 = and(io.master.aw.valid, T_1524) - io.slave[1].aw.valid <= T_1525 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bits(aw_route, 1, 1) - node T_1527 = and(io.slave[1].aw.ready, T_1526) - node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1531 : - T_1530 <= UInt<1>("h1") - skip - node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1534 = and(T_1533, io.slave[1].w.bits.last) - when T_1534 : - T_1530 <= UInt<1>("h0") - skip - node T_1536 = and(io.master.w.valid, T_1530) - io.slave[1].w.valid <= T_1536 - io.slave[1].w.bits <- io.master.w.bits - node T_1537 = and(io.slave[1].w.ready, T_1530) - node T_1538 = or(T_1518, T_1537) - node T_1539 = bits(ar_route, 2, 2) - node T_1540 = and(io.master.ar.valid, T_1539) - io.slave[2].ar.valid <= T_1540 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bits(ar_route, 2, 2) - node T_1542 = and(io.slave[2].ar.ready, T_1541) - node T_1543 = or(T_1523, T_1542) - node T_1544 = bits(aw_route, 2, 2) - node T_1545 = and(io.master.aw.valid, T_1544) - io.slave[2].aw.valid <= T_1545 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bits(aw_route, 2, 2) - node T_1547 = and(io.slave[2].aw.ready, T_1546) - node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1551 : - T_1550 <= UInt<1>("h1") - skip - node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1554 = and(T_1553, io.slave[2].w.bits.last) - when T_1554 : - T_1550 <= UInt<1>("h0") - skip - node T_1556 = and(io.master.w.valid, T_1550) - io.slave[2].w.valid <= T_1556 - io.slave[2].w.bits <- io.master.w.bits - node T_1557 = and(io.slave[2].w.ready, T_1550) - node T_1558 = or(T_1538, T_1557) - node T_1559 = bits(ar_route, 3, 3) - node T_1560 = and(io.master.ar.valid, T_1559) - io.slave[3].ar.valid <= T_1560 - io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bits(ar_route, 3, 3) - node T_1562 = and(io.slave[3].ar.ready, T_1561) - node ar_ready = or(T_1543, T_1562) - node T_1564 = bits(aw_route, 3, 3) - node T_1565 = and(io.master.aw.valid, T_1564) - io.slave[3].aw.valid <= T_1565 - io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bits(aw_route, 3, 3) - node T_1567 = and(io.slave[3].aw.ready, T_1566) - node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) - when T_1571 : - T_1570 <= UInt<1>("h1") - skip - node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) - node T_1574 = and(T_1573, io.slave[3].w.bits.last) - when T_1574 : - T_1570 <= UInt<1>("h0") - skip - node T_1576 = and(io.master.w.valid, T_1570) - io.slave[3].w.valid <= T_1576 - io.slave[3].w.bits <- io.master.w.bits - node T_1577 = and(io.slave[3].w.ready, T_1570) - node w_ready = or(T_1558, T_1577) - node T_1580 = neq(ar_route, UInt<1>("h0")) - node r_invalid = eq(T_1580, UInt<1>("h0")) - node T_1584 = neq(aw_route, UInt<1>("h0")) - node w_invalid = eq(T_1584, UInt<1>("h0")) - inst err_slave of NastiErrorSlave - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1588 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1588 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1589 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1589 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1590 = and(r_invalid, err_slave.io.ar.ready) - node T_1591 = or(ar_ready, T_1590) - io.master.ar.ready <= T_1591 - node T_1592 = and(w_invalid, err_slave.io.aw.ready) - node T_1593 = or(aw_ready, T_1592) - io.master.aw.ready <= T_1593 - node T_1594 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1594 - inst b_arb of RRArbiter_38 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- io.slave[3].b - r_arb.io.in[3] <- io.slave[3].r - b_arb.io.in[4] <- err_slave.io.b - r_arb.io.in[4] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - module NastiErrorSlave_40 : - input clk : Clock - input reset : UInt<1> - input io : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - node T_322 = and(io.ar.ready, io.ar.valid) - when T_322 : - node T_324 = eq(reset, UInt<1>("h0")) - when T_324 : - printf(clk, UInt<1>("h1"), "Invalid read address %x\n", io.ar.bits.addr) - skip - skip - node T_325 = and(io.aw.ready, io.aw.valid) - when T_325 : - node T_327 = eq(reset, UInt<1>("h0")) - when T_327 : - printf(clk, UInt<1>("h1"), "Invalid write address %x\n", io.aw.bits.addr) - skip - skip - inst r_queue of Queue_36 - r_queue.io is invalid - r_queue.clk <= clk - r_queue.reset <= reset - r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg beats_left : UInt<8>, clk with : - reset => (reset, UInt<8>("h0")) - node T_346 = eq(responding, UInt<1>("h0")) - node T_347 = and(T_346, r_queue.io.deq.valid) - when T_347 : - responding <= UInt<1>("h1") - beats_left <= r_queue.io.deq.bits.len - skip - node T_349 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_349 - io.r.bits.id <= r_queue.io.deq.bits.id - io.r.bits.data <= UInt<1>("h0") - io.r.bits.resp <= UInt<2>("h3") - node T_352 = eq(beats_left, UInt<1>("h0")) - io.r.bits.last <= T_352 - node T_353 = and(io.r.ready, io.r.valid) - node T_354 = and(T_353, io.r.bits.last) - r_queue.io.deq.ready <= T_354 - node T_355 = and(io.r.ready, io.r.valid) - when T_355 : - node T_357 = eq(beats_left, UInt<1>("h0")) - when T_357 : - responding <= UInt<1>("h0") - skip - node T_360 = eq(T_357, UInt<1>("h0")) - when T_360 : - node T_362 = sub(beats_left, UInt<1>("h1")) - node T_363 = tail(T_362, 1) - beats_left <= T_363 - skip - skip - reg draining : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - io.w.ready <= draining - node T_366 = and(io.aw.ready, io.aw.valid) - when T_366 : - draining <= UInt<1>("h1") - skip - node T_368 = and(io.w.ready, io.w.valid) - node T_369 = and(T_368, io.w.bits.last) - when T_369 : - draining <= UInt<1>("h0") - skip - inst b_queue of Queue_37 - b_queue.io is invalid - b_queue.clk <= clk - b_queue.reset <= reset - node T_374 = eq(draining, UInt<1>("h0")) - node T_375 = and(io.aw.valid, T_374) - b_queue.io.enq.valid <= T_375 - b_queue.io.enq.bits <= io.aw.bits.id - node T_377 = eq(draining, UInt<1>("h0")) - node T_378 = and(b_queue.io.enq.ready, T_377) - io.aw.ready <= T_378 - node T_380 = eq(draining, UInt<1>("h0")) - node T_381 = and(b_queue.io.deq.valid, T_380) - io.b.valid <= T_381 - io.b.bits.id <= b_queue.io.deq.bits - io.b.bits.resp <= UInt<2>("h3") - node T_384 = eq(draining, UInt<1>("h0")) - node T_385 = and(io.b.ready, T_384) - b_queue.io.deq.ready <= T_385 - module NastiRouter_39 : - input clk : Clock - input reset : UInt<1> - output io : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io is invalid - node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h0")) - node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h40000000")) - node T_1440 = and(T_1437, T_1439) - node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h40000000")) - node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h60000000")) - node T_1445 = and(T_1442, T_1444) - node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h60000000")) - node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h80000000")) - node T_1450 = and(T_1447, T_1449) - node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h80000000")) - node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h100000000")) - node T_1455 = and(T_1452, T_1454) - wire T_1457 : UInt<1>[4] - T_1457[0] <= T_1440 - T_1457[1] <= T_1445 - T_1457[2] <= T_1450 - T_1457[3] <= T_1455 - node T_1463 = cat(T_1457[3], T_1457[2]) - node T_1464 = cat(T_1457[1], T_1457[0]) - node ar_route = cat(T_1463, T_1464) - node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h0")) - node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h40000000")) - node T_1470 = and(T_1467, T_1469) - node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h40000000")) - node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h60000000")) - node T_1475 = and(T_1472, T_1474) - node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h60000000")) - node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h80000000")) - node T_1480 = and(T_1477, T_1479) - node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h80000000")) - node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h100000000")) - node T_1485 = and(T_1482, T_1484) - wire T_1487 : UInt<1>[4] - T_1487[0] <= T_1470 - T_1487[1] <= T_1475 - T_1487[2] <= T_1480 - T_1487[3] <= T_1485 - node T_1493 = cat(T_1487[3], T_1487[2]) - node T_1494 = cat(T_1487[1], T_1487[0]) - node aw_route = cat(T_1493, T_1494) - node T_1499 = bits(ar_route, 0, 0) - node T_1500 = and(io.master.ar.valid, T_1499) - io.slave[0].ar.valid <= T_1500 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bits(ar_route, 0, 0) - node T_1502 = and(io.slave[0].ar.ready, T_1501) - node T_1503 = or(UInt<1>("h0"), T_1502) - node T_1504 = bits(aw_route, 0, 0) - node T_1505 = and(io.master.aw.valid, T_1504) - io.slave[0].aw.valid <= T_1505 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bits(aw_route, 0, 0) - node T_1507 = and(io.slave[0].aw.ready, T_1506) - node T_1508 = or(UInt<1>("h0"), T_1507) - reg T_1510 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1511 : - T_1510 <= UInt<1>("h1") - skip - node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1514 = and(T_1513, io.slave[0].w.bits.last) - when T_1514 : - T_1510 <= UInt<1>("h0") - skip - node T_1516 = and(io.master.w.valid, T_1510) - io.slave[0].w.valid <= T_1516 - io.slave[0].w.bits <- io.master.w.bits - node T_1517 = and(io.slave[0].w.ready, T_1510) - node T_1518 = or(UInt<1>("h0"), T_1517) - node T_1519 = bits(ar_route, 1, 1) - node T_1520 = and(io.master.ar.valid, T_1519) - io.slave[1].ar.valid <= T_1520 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bits(ar_route, 1, 1) - node T_1522 = and(io.slave[1].ar.ready, T_1521) - node T_1523 = or(T_1503, T_1522) - node T_1524 = bits(aw_route, 1, 1) - node T_1525 = and(io.master.aw.valid, T_1524) - io.slave[1].aw.valid <= T_1525 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bits(aw_route, 1, 1) - node T_1527 = and(io.slave[1].aw.ready, T_1526) - node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1531 : - T_1530 <= UInt<1>("h1") - skip - node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1534 = and(T_1533, io.slave[1].w.bits.last) - when T_1534 : - T_1530 <= UInt<1>("h0") - skip - node T_1536 = and(io.master.w.valid, T_1530) - io.slave[1].w.valid <= T_1536 - io.slave[1].w.bits <- io.master.w.bits - node T_1537 = and(io.slave[1].w.ready, T_1530) - node T_1538 = or(T_1518, T_1537) - node T_1539 = bits(ar_route, 2, 2) - node T_1540 = and(io.master.ar.valid, T_1539) - io.slave[2].ar.valid <= T_1540 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bits(ar_route, 2, 2) - node T_1542 = and(io.slave[2].ar.ready, T_1541) - node T_1543 = or(T_1523, T_1542) - node T_1544 = bits(aw_route, 2, 2) - node T_1545 = and(io.master.aw.valid, T_1544) - io.slave[2].aw.valid <= T_1545 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bits(aw_route, 2, 2) - node T_1547 = and(io.slave[2].aw.ready, T_1546) - node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1551 : - T_1550 <= UInt<1>("h1") - skip - node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1554 = and(T_1553, io.slave[2].w.bits.last) - when T_1554 : - T_1550 <= UInt<1>("h0") - skip - node T_1556 = and(io.master.w.valid, T_1550) - io.slave[2].w.valid <= T_1556 - io.slave[2].w.bits <- io.master.w.bits - node T_1557 = and(io.slave[2].w.ready, T_1550) - node T_1558 = or(T_1538, T_1557) - node T_1559 = bits(ar_route, 3, 3) - node T_1560 = and(io.master.ar.valid, T_1559) - io.slave[3].ar.valid <= T_1560 - io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bits(ar_route, 3, 3) - node T_1562 = and(io.slave[3].ar.ready, T_1561) - node ar_ready = or(T_1543, T_1562) - node T_1564 = bits(aw_route, 3, 3) - node T_1565 = and(io.master.aw.valid, T_1564) - io.slave[3].aw.valid <= T_1565 - io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bits(aw_route, 3, 3) - node T_1567 = and(io.slave[3].aw.ready, T_1566) - node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) - when T_1571 : - T_1570 <= UInt<1>("h1") - skip - node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) - node T_1574 = and(T_1573, io.slave[3].w.bits.last) - when T_1574 : - T_1570 <= UInt<1>("h0") - skip - node T_1576 = and(io.master.w.valid, T_1570) - io.slave[3].w.valid <= T_1576 - io.slave[3].w.bits <- io.master.w.bits - node T_1577 = and(io.slave[3].w.ready, T_1570) - node w_ready = or(T_1558, T_1577) - node T_1580 = neq(ar_route, UInt<1>("h0")) - node r_invalid = eq(T_1580, UInt<1>("h0")) - node T_1584 = neq(aw_route, UInt<1>("h0")) - node w_invalid = eq(T_1584, UInt<1>("h0")) - inst err_slave of NastiErrorSlave_40 - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1588 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1588 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1589 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1589 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1590 = and(r_invalid, err_slave.io.ar.ready) - node T_1591 = or(ar_ready, T_1590) - io.master.ar.ready <= T_1591 - node T_1592 = and(w_invalid, err_slave.io.aw.ready) - node T_1593 = or(aw_ready, T_1592) - io.master.aw.ready <= T_1593 - node T_1594 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1594 - inst b_arb of RRArbiter_38 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- io.slave[3].b - r_arb.io.in[3] <- io.slave[3].r - b_arb.io.in[4] <- err_slave.io.b - r_arb.io.in[4] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - module RRArbiter_45 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<1>} - io is invalid - wire T_306 : UInt<1> - T_306 is invalid - io.out.valid <= io.in[T_306].valid - io.out.bits <- io.in[T_306].bits - io.chosen <= T_306 - io.in[T_306].ready <= UInt<1>("h0") - reg T_391 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_392 = gt(UInt<1>("h0"), T_391) - node T_393 = and(io.in[0].valid, T_392) - node T_395 = gt(UInt<1>("h1"), T_391) - node T_396 = and(io.in[1].valid, T_395) - node T_399 = or(UInt<1>("h0"), T_393) - node T_401 = eq(T_399, UInt<1>("h0")) - node T_403 = or(UInt<1>("h0"), T_393) - node T_404 = or(T_403, T_396) - node T_406 = eq(T_404, UInt<1>("h0")) - node T_408 = or(UInt<1>("h0"), T_393) - node T_409 = or(T_408, T_396) - node T_410 = or(T_409, io.in[0].valid) - node T_412 = eq(T_410, UInt<1>("h0")) - node T_414 = gt(UInt<1>("h0"), T_391) - node T_415 = and(UInt<1>("h1"), T_414) - node T_416 = or(T_415, T_406) - node T_418 = gt(UInt<1>("h1"), T_391) - node T_419 = and(T_401, T_418) - node T_420 = or(T_419, T_412) - node T_422 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_423 = mux(UInt<1>("h0"), T_422, T_416) - node T_424 = and(T_423, io.out.ready) - io.in[0].ready <= T_424 - node T_426 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_427 = mux(UInt<1>("h0"), T_426, T_420) - node T_428 = and(T_427, io.out.ready) - io.in[1].ready <= T_428 - node T_431 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_433 = gt(UInt<1>("h1"), T_391) - node T_434 = and(io.in[1].valid, T_433) - node T_436 = mux(T_434, UInt<1>("h1"), T_431) - node T_437 = mux(UInt<1>("h0"), UInt<1>("h1"), T_436) - T_306 <= T_437 - node T_438 = and(io.out.ready, io.out.valid) - when T_438 : - T_391 <= T_306 - skip - module NastiArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io is invalid - inst T_1767 of RRArbiter_45 - T_1767.io is invalid - T_1767.clk <= clk - T_1767.reset <= reset - inst T_1780 of RRArbiter_45 - T_1780.io is invalid - T_1780.clk <= clk - T_1780.reset <= reset - node T_1781 = bits(io.slave.r.bits.id, 0, 0) - node T_1782 = bits(io.slave.b.bits.id, 0, 0) - reg T_1784 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_1784) - reg T_1786 : UInt<1>, clk with : - reset => (reset, UInt<1>("h1")) - node T_1787 = and(T_1780.io.out.ready, T_1780.io.out.valid) - when T_1787 : - T_1784 <= T_1780.io.chosen - T_1786 <= UInt<1>("h0") - skip - node T_1789 = and(io.slave.w.ready, io.slave.w.valid) - node T_1790 = and(T_1789, io.slave.w.bits.last) - when T_1790 : - T_1786 <= UInt<1>("h1") - skip - T_1767.io.in[0] <- io.master[0].ar - node T_1793 = cat(io.master[0].ar.bits.id, UInt<1>("h0")) - T_1767.io.in[0].bits.id <= T_1793 - T_1780.io.in[0] <- io.master[0].aw - node T_1795 = cat(io.master[0].aw.bits.id, UInt<1>("h0")) - T_1780.io.in[0].bits.id <= T_1795 - node T_1797 = eq(T_1781, UInt<1>("h0")) - node T_1798 = and(io.slave.r.valid, T_1797) - io.master[0].r.valid <= T_1798 - io.master[0].r.bits <- io.slave.r.bits - node T_1800 = dshr(io.slave.r.bits.id, UInt<1>("h1")) - io.master[0].r.bits.id <= T_1800 - node T_1802 = eq(T_1782, UInt<1>("h0")) - node T_1803 = and(io.slave.b.valid, T_1802) - io.master[0].b.valid <= T_1803 - io.master[0].b.bits <- io.slave.b.bits - node T_1805 = dshr(io.slave.b.bits.id, UInt<1>("h1")) - io.master[0].b.bits.id <= T_1805 - node T_1807 = eq(T_1784, UInt<1>("h0")) - node T_1808 = and(io.slave.w.ready, T_1807) - node T_1810 = eq(T_1786, UInt<1>("h0")) - node T_1811 = and(T_1808, T_1810) - io.master[0].w.ready <= T_1811 - T_1767.io.in[1] <- io.master[1].ar - node T_1813 = cat(io.master[1].ar.bits.id, UInt<1>("h1")) - T_1767.io.in[1].bits.id <= T_1813 - T_1780.io.in[1] <- io.master[1].aw - node T_1815 = cat(io.master[1].aw.bits.id, UInt<1>("h1")) - T_1780.io.in[1].bits.id <= T_1815 - node T_1817 = eq(T_1781, UInt<1>("h1")) - node T_1818 = and(io.slave.r.valid, T_1817) - io.master[1].r.valid <= T_1818 - io.master[1].r.bits <- io.slave.r.bits - node T_1820 = dshr(io.slave.r.bits.id, UInt<1>("h1")) - io.master[1].r.bits.id <= T_1820 - node T_1822 = eq(T_1782, UInt<1>("h1")) - node T_1823 = and(io.slave.b.valid, T_1822) - io.master[1].b.valid <= T_1823 - io.master[1].b.bits <- io.slave.b.bits - node T_1825 = dshr(io.slave.b.bits.id, UInt<1>("h1")) - io.master[1].b.bits.id <= T_1825 - node T_1827 = eq(T_1784, UInt<1>("h1")) - node T_1828 = and(io.slave.w.ready, T_1827) - node T_1830 = eq(T_1786, UInt<1>("h0")) - node T_1831 = and(T_1828, T_1830) - io.master[1].w.ready <= T_1831 - io.slave.r.ready <= io.master[T_1781].r.ready - io.slave.b.ready <= io.master[T_1782].b.ready - io.slave.w.bits <- io.master[T_1784].w.bits - node T_2469 = eq(T_1786, UInt<1>("h0")) - node T_2470 = and(io.master[T_1784].w.valid, T_2469) - io.slave.w.valid <= T_2470 - io.slave.ar <- T_1767.io.out - io.slave.aw.bits <- T_1780.io.out.bits - node T_2471 = and(T_1780.io.out.valid, T_1786) - io.slave.aw.valid <= T_2471 - node T_2472 = and(io.slave.aw.ready, T_1786) - T_1780.io.out.ready <= T_2472 - module NastiCrossbar : - input clk : Clock - input reset : UInt<1> - output io : {flip masters : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io is invalid - inst T_2710 of NastiRouter - T_2710.io is invalid - T_2710.clk <= clk - T_2710.reset <= reset - inst T_2711 of NastiRouter_39 - T_2711.io is invalid - T_2711.clk <= clk - T_2711.reset <= reset - wire T_4146 : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2] - T_4146[0] <- T_2710.io - T_4146[1] <- T_2711.io - inst T_8449 of NastiArbiter - T_8449.io is invalid - T_8449.clk <= clk - T_8449.reset <= reset - inst T_8450 of NastiArbiter - T_8450.io is invalid - T_8450.clk <= clk - T_8450.reset <= reset - inst T_8451 of NastiArbiter - T_8451.io is invalid - T_8451.clk <= clk - T_8451.reset <= reset - inst T_8452 of NastiArbiter - T_8452.io is invalid - T_8452.clk <= clk - T_8452.reset <= reset - wire T_10206 : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4] - T_10206[0] <- T_8449.io - T_10206[1] <- T_8450.io - T_10206[2] <- T_8451.io - T_10206[3] <- T_8452.io - T_4146[0].master <- io.masters[0] - T_4146[1].master <- io.masters[1] - wire T_19131 : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_19131[0] <- T_4146[0].slave[0] - T_19131[1] <- T_4146[1].slave[0] - T_10206[0].master <= T_19131 - io.slaves[0] <- T_10206[0].slave - wire T_19768 : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_19768[0] <- T_4146[0].slave[1] - T_19768[1] <- T_4146[1].slave[1] - T_10206[1].master <= T_19768 - io.slaves[1] <- T_10206[1].slave - wire T_20405 : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_20405[0] <- T_4146[0].slave[2] - T_20405[1] <- T_4146[1].slave[2] - T_10206[2].master <= T_20405 - io.slaves[2] <- T_10206[2].slave - wire T_21042 : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_21042[0] <- T_4146[0].slave[3] - T_21042[1] <- T_4146[1].slave[3] - T_10206[3].master <= T_21042 - io.slaves[3] <- T_10206[3].slave - module RRArbiter_62 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<2>} - io is invalid - wire T_174 : UInt<2> - T_174 is invalid - io.out.valid <= io.in[T_174].valid - io.out.bits <- io.in[T_174].bits - io.chosen <= T_174 - io.in[T_174].ready <= UInt<1>("h0") - reg T_211 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_212 = gt(UInt<1>("h0"), T_211) - node T_213 = and(io.in[0].valid, T_212) - node T_215 = gt(UInt<1>("h1"), T_211) - node T_216 = and(io.in[1].valid, T_215) - node T_218 = gt(UInt<2>("h2"), T_211) - node T_219 = and(io.in[2].valid, T_218) - node T_221 = gt(UInt<2>("h3"), T_211) - node T_222 = and(io.in[3].valid, T_221) - node T_225 = or(UInt<1>("h0"), T_213) - node T_227 = eq(T_225, UInt<1>("h0")) - node T_229 = or(UInt<1>("h0"), T_213) - node T_230 = or(T_229, T_216) - node T_232 = eq(T_230, UInt<1>("h0")) - node T_234 = or(UInt<1>("h0"), T_213) - node T_235 = or(T_234, T_216) - node T_236 = or(T_235, T_219) - node T_238 = eq(T_236, UInt<1>("h0")) - node T_240 = or(UInt<1>("h0"), T_213) - node T_241 = or(T_240, T_216) - node T_242 = or(T_241, T_219) - node T_243 = or(T_242, T_222) - node T_245 = eq(T_243, UInt<1>("h0")) - node T_247 = or(UInt<1>("h0"), T_213) - node T_248 = or(T_247, T_216) - node T_249 = or(T_248, T_219) - node T_250 = or(T_249, T_222) - node T_251 = or(T_250, io.in[0].valid) - node T_253 = eq(T_251, UInt<1>("h0")) - node T_255 = or(UInt<1>("h0"), T_213) - node T_256 = or(T_255, T_216) - node T_257 = or(T_256, T_219) - node T_258 = or(T_257, T_222) - node T_259 = or(T_258, io.in[0].valid) - node T_260 = or(T_259, io.in[1].valid) - node T_262 = eq(T_260, UInt<1>("h0")) - node T_264 = or(UInt<1>("h0"), T_213) - node T_265 = or(T_264, T_216) - node T_266 = or(T_265, T_219) - node T_267 = or(T_266, T_222) - node T_268 = or(T_267, io.in[0].valid) - node T_269 = or(T_268, io.in[1].valid) - node T_270 = or(T_269, io.in[2].valid) - node T_272 = eq(T_270, UInt<1>("h0")) - node T_274 = gt(UInt<1>("h0"), T_211) - node T_275 = and(UInt<1>("h1"), T_274) - node T_276 = or(T_275, T_245) - node T_278 = gt(UInt<1>("h1"), T_211) - node T_279 = and(T_227, T_278) - node T_280 = or(T_279, T_253) - node T_282 = gt(UInt<2>("h2"), T_211) - node T_283 = and(T_232, T_282) - node T_284 = or(T_283, T_262) - node T_286 = gt(UInt<2>("h3"), T_211) - node T_287 = and(T_238, T_286) - node T_288 = or(T_287, T_272) - node T_290 = eq(UInt<2>("h3"), UInt<1>("h0")) - node T_291 = mux(UInt<1>("h0"), T_290, T_276) - node T_292 = and(T_291, io.out.ready) - io.in[0].ready <= T_292 - node T_294 = eq(UInt<2>("h3"), UInt<1>("h1")) - node T_295 = mux(UInt<1>("h0"), T_294, T_280) - node T_296 = and(T_295, io.out.ready) - io.in[1].ready <= T_296 - node T_298 = eq(UInt<2>("h3"), UInt<2>("h2")) - node T_299 = mux(UInt<1>("h0"), T_298, T_284) - node T_300 = and(T_299, io.out.ready) - io.in[2].ready <= T_300 - node T_302 = eq(UInt<2>("h3"), UInt<2>("h3")) - node T_303 = mux(UInt<1>("h0"), T_302, T_288) - node T_304 = and(T_303, io.out.ready) - io.in[3].ready <= T_304 - node T_307 = mux(io.in[2].valid, UInt<2>("h2"), UInt<2>("h3")) - node T_309 = mux(io.in[1].valid, UInt<1>("h1"), T_307) - node T_311 = mux(io.in[0].valid, UInt<1>("h0"), T_309) - node T_313 = gt(UInt<2>("h3"), T_211) - node T_314 = and(io.in[3].valid, T_313) - node T_316 = mux(T_314, UInt<2>("h3"), T_311) - node T_318 = gt(UInt<2>("h2"), T_211) - node T_319 = and(io.in[2].valid, T_318) - node T_321 = mux(T_319, UInt<2>("h2"), T_316) - node T_323 = gt(UInt<1>("h1"), T_211) - node T_324 = and(io.in[1].valid, T_323) - node T_326 = mux(T_324, UInt<1>("h1"), T_321) - node T_327 = mux(UInt<1>("h0"), UInt<2>("h3"), T_326) - T_174 <= T_327 - node T_328 = and(io.out.ready, io.out.valid) - when T_328 : - T_211 <= T_174 - skip - module JunctionsPeekingArbiter_63 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - reg T_243 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - reg T_245 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_247 : UInt<1>[4] - T_247[0] <= io.in[0].valid - T_247[1] <= io.in[1].valid - T_247[2] <= io.in[2].valid - T_247[3] <= io.in[3].valid - node T_254 = add(T_243, UInt<1>("h1")) - node T_255 = tail(T_254, 1) - node T_257 = lt(T_255, UInt<3>("h4")) - node T_259 = add(UInt<1>("h0"), T_255) - node T_260 = tail(T_259, 1) - node T_263 = sub(T_255, UInt<3>("h4")) - node T_264 = tail(T_263, 1) - node T_266 = mux(T_257, T_247[T_260], T_247[T_264]) - node T_268 = lt(T_255, UInt<2>("h3")) - node T_270 = add(UInt<1>("h1"), T_255) - node T_271 = tail(T_270, 1) - node T_274 = sub(T_255, UInt<2>("h3")) - node T_275 = tail(T_274, 1) - node T_277 = mux(T_268, T_247[T_271], T_247[T_275]) - node T_279 = lt(T_255, UInt<2>("h2")) - node T_281 = add(UInt<2>("h2"), T_255) - node T_282 = tail(T_281, 1) - node T_285 = sub(T_255, UInt<2>("h2")) - node T_286 = tail(T_285, 1) - node T_288 = mux(T_279, T_247[T_282], T_247[T_286]) - node T_290 = lt(T_255, UInt<1>("h1")) - node T_292 = add(UInt<2>("h3"), T_255) - node T_293 = tail(T_292, 1) - node T_296 = sub(T_255, UInt<1>("h1")) - node T_297 = tail(T_296, 1) - node T_299 = mux(T_290, T_247[T_293], T_247[T_297]) - wire T_301 : UInt<1>[4] - T_301[0] <= T_266 - T_301[1] <= T_277 - T_301[2] <= T_288 - T_301[3] <= T_299 - wire T_312 : UInt<2>[4] - T_312[0] <= UInt<1>("h0") - T_312[1] <= UInt<1>("h1") - T_312[2] <= UInt<2>("h2") - T_312[3] <= UInt<2>("h3") - node T_319 = add(T_243, UInt<1>("h1")) - node T_320 = tail(T_319, 1) - node T_322 = lt(T_320, UInt<3>("h4")) - node T_324 = add(UInt<1>("h0"), T_320) - node T_325 = tail(T_324, 1) - node T_328 = sub(T_320, UInt<3>("h4")) - node T_329 = tail(T_328, 1) - node T_331 = mux(T_322, T_312[T_325], T_312[T_329]) - node T_333 = lt(T_320, UInt<2>("h3")) - node T_335 = add(UInt<1>("h1"), T_320) - node T_336 = tail(T_335, 1) - node T_339 = sub(T_320, UInt<2>("h3")) - node T_340 = tail(T_339, 1) - node T_342 = mux(T_333, T_312[T_336], T_312[T_340]) - node T_344 = lt(T_320, UInt<2>("h2")) - node T_346 = add(UInt<2>("h2"), T_320) - node T_347 = tail(T_346, 1) - node T_350 = sub(T_320, UInt<2>("h2")) - node T_351 = tail(T_350, 1) - node T_353 = mux(T_344, T_312[T_347], T_312[T_351]) - node T_355 = lt(T_320, UInt<1>("h1")) - node T_357 = add(UInt<2>("h3"), T_320) - node T_358 = tail(T_357, 1) - node T_361 = sub(T_320, UInt<1>("h1")) - node T_362 = tail(T_361, 1) - node T_364 = mux(T_355, T_312[T_358], T_312[T_362]) - wire T_366 : UInt<2>[4] - T_366[0] <= T_331 - T_366[1] <= T_342 - T_366[2] <= T_353 - T_366[3] <= T_364 - node T_372 = mux(T_301[2], T_366[2], T_366[3]) - node T_373 = mux(T_301[1], T_366[1], T_372) - node T_374 = mux(T_301[0], T_366[0], T_373) - node T_375 = mux(T_245, T_243, T_374) - node T_377 = eq(T_375, UInt<1>("h0")) - node T_378 = and(io.out.ready, T_377) - io.in[0].ready <= T_378 - node T_380 = eq(T_375, UInt<1>("h1")) - node T_381 = and(io.out.ready, T_380) - io.in[1].ready <= T_381 - node T_383 = eq(T_375, UInt<2>("h2")) - node T_384 = and(io.out.ready, T_383) - io.in[2].ready <= T_384 - node T_386 = eq(T_375, UInt<2>("h3")) - node T_387 = and(io.out.ready, T_386) - io.in[3].ready <= T_387 - io.out.valid <= io.in[T_375].valid - io.out.bits <- io.in[T_375].bits - node T_418 = and(io.out.ready, io.out.valid) - when T_418 : - node T_420 = eq(T_245, UInt<1>("h0")) - node T_422 = and(T_420, UInt<1>("h1")) - when T_422 : - T_243 <= T_374 - T_245 <= UInt<1>("h1") - skip - when io.out.bits.last : - T_245 <= UInt<1>("h0") - skip - skip - module NastiRouter_58 : - input clk : Clock - input reset : UInt<1> - output io : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io is invalid - node T_1278 = geq(io.master.ar.bits.addr, UInt<31>("h40000000")) - node T_1280 = lt(io.master.ar.bits.addr, UInt<31>("h40008000")) - node T_1281 = and(T_1278, T_1280) - node T_1283 = geq(io.master.ar.bits.addr, UInt<31>("h40008000")) - node T_1285 = lt(io.master.ar.bits.addr, UInt<31>("h40010000")) - node T_1286 = and(T_1283, T_1285) - node T_1288 = geq(io.master.ar.bits.addr, UInt<31>("h40010000")) - node T_1290 = lt(io.master.ar.bits.addr, UInt<31>("h40010200")) - node T_1291 = and(T_1288, T_1290) - wire T_1293 : UInt<1>[3] - T_1293[0] <= T_1281 - T_1293[1] <= T_1286 - T_1293[2] <= T_1291 - node T_1298 = cat(T_1293[1], T_1293[0]) - node ar_route = cat(T_1293[2], T_1298) - node T_1301 = geq(io.master.aw.bits.addr, UInt<31>("h40000000")) - node T_1303 = lt(io.master.aw.bits.addr, UInt<31>("h40008000")) - node T_1304 = and(T_1301, T_1303) - node T_1306 = geq(io.master.aw.bits.addr, UInt<31>("h40008000")) - node T_1308 = lt(io.master.aw.bits.addr, UInt<31>("h40010000")) - node T_1309 = and(T_1306, T_1308) - node T_1311 = geq(io.master.aw.bits.addr, UInt<31>("h40010000")) - node T_1313 = lt(io.master.aw.bits.addr, UInt<31>("h40010200")) - node T_1314 = and(T_1311, T_1313) - wire T_1316 : UInt<1>[3] - T_1316[0] <= T_1304 - T_1316[1] <= T_1309 - T_1316[2] <= T_1314 - node T_1321 = cat(T_1316[1], T_1316[0]) - node aw_route = cat(T_1316[2], T_1321) - node T_1326 = bits(ar_route, 0, 0) - node T_1327 = and(io.master.ar.valid, T_1326) - io.slave[0].ar.valid <= T_1327 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1328 = bits(ar_route, 0, 0) - node T_1329 = and(io.slave[0].ar.ready, T_1328) - node T_1330 = or(UInt<1>("h0"), T_1329) - node T_1331 = bits(aw_route, 0, 0) - node T_1332 = and(io.master.aw.valid, T_1331) - io.slave[0].aw.valid <= T_1332 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1333 = bits(aw_route, 0, 0) - node T_1334 = and(io.slave[0].aw.ready, T_1333) - node T_1335 = or(UInt<1>("h0"), T_1334) - reg T_1337 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1338 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1338 : - T_1337 <= UInt<1>("h1") - skip - node T_1340 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1341 = and(T_1340, io.slave[0].w.bits.last) - when T_1341 : - T_1337 <= UInt<1>("h0") - skip - node T_1343 = and(io.master.w.valid, T_1337) - io.slave[0].w.valid <= T_1343 - io.slave[0].w.bits <- io.master.w.bits - node T_1344 = and(io.slave[0].w.ready, T_1337) - node T_1345 = or(UInt<1>("h0"), T_1344) - node T_1346 = bits(ar_route, 1, 1) - node T_1347 = and(io.master.ar.valid, T_1346) - io.slave[1].ar.valid <= T_1347 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1348 = bits(ar_route, 1, 1) - node T_1349 = and(io.slave[1].ar.ready, T_1348) - node T_1350 = or(T_1330, T_1349) - node T_1351 = bits(aw_route, 1, 1) - node T_1352 = and(io.master.aw.valid, T_1351) - io.slave[1].aw.valid <= T_1352 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1353 = bits(aw_route, 1, 1) - node T_1354 = and(io.slave[1].aw.ready, T_1353) - node T_1355 = or(T_1335, T_1354) - reg T_1357 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1358 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1358 : - T_1357 <= UInt<1>("h1") - skip - node T_1360 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1361 = and(T_1360, io.slave[1].w.bits.last) - when T_1361 : - T_1357 <= UInt<1>("h0") - skip - node T_1363 = and(io.master.w.valid, T_1357) - io.slave[1].w.valid <= T_1363 - io.slave[1].w.bits <- io.master.w.bits - node T_1364 = and(io.slave[1].w.ready, T_1357) - node T_1365 = or(T_1345, T_1364) - node T_1366 = bits(ar_route, 2, 2) - node T_1367 = and(io.master.ar.valid, T_1366) - io.slave[2].ar.valid <= T_1367 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1368 = bits(ar_route, 2, 2) - node T_1369 = and(io.slave[2].ar.ready, T_1368) - node ar_ready = or(T_1350, T_1369) - node T_1371 = bits(aw_route, 2, 2) - node T_1372 = and(io.master.aw.valid, T_1371) - io.slave[2].aw.valid <= T_1372 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1373 = bits(aw_route, 2, 2) - node T_1374 = and(io.slave[2].aw.ready, T_1373) - node aw_ready = or(T_1355, T_1374) - reg T_1377 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1378 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1378 : - T_1377 <= UInt<1>("h1") - skip - node T_1380 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1381 = and(T_1380, io.slave[2].w.bits.last) - when T_1381 : - T_1377 <= UInt<1>("h0") - skip - node T_1383 = and(io.master.w.valid, T_1377) - io.slave[2].w.valid <= T_1383 - io.slave[2].w.bits <- io.master.w.bits - node T_1384 = and(io.slave[2].w.ready, T_1377) - node w_ready = or(T_1365, T_1384) - node T_1387 = neq(ar_route, UInt<1>("h0")) - node r_invalid = eq(T_1387, UInt<1>("h0")) - node T_1391 = neq(aw_route, UInt<1>("h0")) - node w_invalid = eq(T_1391, UInt<1>("h0")) - inst err_slave of NastiErrorSlave_40 - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1395 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1395 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1396 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1396 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1397 = and(r_invalid, err_slave.io.ar.ready) - node T_1398 = or(ar_ready, T_1397) - io.master.ar.ready <= T_1398 - node T_1399 = and(w_invalid, err_slave.io.aw.ready) - node T_1400 = or(aw_ready, T_1399) - io.master.aw.ready <= T_1400 - node T_1401 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1401 - inst b_arb of RRArbiter_62 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter_63 - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- err_slave.io.b - r_arb.io.in[3] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - module NastiCrossbar_57 : - input clk : Clock - input reset : UInt<1> - output io : {flip masters : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io is invalid - inst T_2233 of NastiRouter_58 - T_2233.io is invalid - T_2233.clk <= clk - T_2233.reset <= reset - T_2233.io.master <- io.masters[0] - io.slaves <= T_2233.io.slave - module NastiRecursiveInterconnect_56 : - input clk : Clock - input reset : UInt<1> - output io : {flip masters : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io is invalid - inst xbar of NastiCrossbar_57 - xbar.io is invalid - xbar.clk <= clk - xbar.reset <= reset - xbar.io.masters <= io.masters - io.slaves[0] <- xbar.io.slaves[0] - io.slaves[1] <- xbar.io.slaves[1] - io.slaves[2] <- xbar.io.slaves[2] - module NastiRecursiveInterconnect : - input clk : Clock - input reset : UInt<1> - output io : {flip masters : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[5]} - io is invalid - inst xbar of NastiCrossbar - xbar.io is invalid - xbar.clk <= clk - xbar.reset <= reset - xbar.io.masters <= io.masters - io.slaves[0] <- xbar.io.slaves[0] - inst T_2869 of NastiRecursiveInterconnect_56 - T_2869.io is invalid - T_2869.clk <= clk - T_2869.reset <= reset - T_2869.io.masters[0] <- xbar.io.slaves[1] - io.slaves[1] <- T_2869.io.slaves[0] - io.slaves[2] <- T_2869.io.slaves[1] - io.slaves[3] <- T_2869.io.slaves[2] - inst T_2870 of NastiErrorSlave_40 - T_2870.io is invalid - T_2870.clk <= clk - T_2870.reset <= reset - T_2870.io <- xbar.io.slaves[2] - io.slaves[4] <- xbar.io.slaves[3] - module LockingRRArbiter_67 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<1>} - io is invalid - reg T_656 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_658 : UInt, clk with : - reset => (reset, UInt<1>("h1")) - wire T_660 : UInt<1> - T_660 is invalid - io.out.valid <= io.in[T_660].valid - io.out.bits <- io.in[T_660].bits - io.chosen <= T_660 - io.in[T_660].ready <= UInt<1>("h0") - reg last_grant : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_842 = gt(UInt<1>("h0"), last_grant) - node T_843 = and(io.in[0].valid, T_842) - node T_845 = gt(UInt<1>("h1"), last_grant) - node T_846 = and(io.in[1].valid, T_845) - node T_849 = or(UInt<1>("h0"), T_843) - node T_851 = eq(T_849, UInt<1>("h0")) - node T_853 = or(UInt<1>("h0"), T_843) - node T_854 = or(T_853, T_846) - node T_856 = eq(T_854, UInt<1>("h0")) - node T_858 = or(UInt<1>("h0"), T_843) - node T_859 = or(T_858, T_846) - node T_860 = or(T_859, io.in[0].valid) - node T_862 = eq(T_860, UInt<1>("h0")) - node T_864 = gt(UInt<1>("h0"), last_grant) - node T_865 = and(UInt<1>("h1"), T_864) - node T_866 = or(T_865, T_856) - node T_868 = gt(UInt<1>("h1"), last_grant) - node T_869 = and(T_851, T_868) - node T_870 = or(T_869, T_862) - node T_872 = eq(T_658, UInt<1>("h0")) - node T_873 = mux(T_656, T_872, T_866) - node T_874 = and(T_873, io.out.ready) - io.in[0].ready <= T_874 - node T_876 = eq(T_658, UInt<1>("h1")) - node T_877 = mux(T_656, T_876, T_870) - node T_878 = and(T_877, io.out.ready) - io.in[1].ready <= T_878 - reg T_880 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_882 = add(T_880, UInt<1>("h1")) - node T_883 = tail(T_882, 1) - node T_884 = and(io.out.ready, io.out.valid) - when T_884 : - node T_886 = and(UInt<1>("h1"), io.out.bits.is_builtin_type) - wire T_889 : UInt<3>[1] - T_889[0] <= UInt<3>("h3") - node T_892 = eq(T_889[0], io.out.bits.a_type) - node T_894 = or(UInt<1>("h0"), T_892) - node T_895 = and(T_886, T_894) - when T_895 : - T_880 <= T_883 - node T_897 = eq(T_656, UInt<1>("h0")) - when T_897 : - T_656 <= UInt<1>("h1") - node T_899 = and(io.in[0].ready, io.in[0].valid) - node T_900 = and(io.in[1].ready, io.in[1].valid) - wire T_902 : UInt<1>[2] - T_902[0] <= T_899 - T_902[1] <= T_900 - node T_908 = mux(T_902[0], UInt<1>("h0"), UInt<1>("h1")) - T_658 <= T_908 - skip - skip - node T_910 = eq(T_883, UInt<1>("h0")) - when T_910 : - T_656 <= UInt<1>("h0") - skip - skip - node T_914 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_916 = gt(UInt<1>("h1"), last_grant) - node T_917 = and(io.in[1].valid, T_916) - node choose = mux(T_917, UInt<1>("h1"), T_914) - node T_920 = mux(T_656, T_658, choose) - T_660 <= T_920 - node T_921 = and(io.out.ready, io.out.valid) - when T_921 : - last_grant <= T_660 - skip - module ReorderQueue : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} - io is invalid - reg roq_data : UInt<1>[9], clk with : - reset => (UInt<1>("h0"), roq_data) - reg roq_tags : UInt<4>[9], clk with : - reset => (UInt<1>("h0"), roq_tags) - wire T_96 : UInt<1>[9] - T_96[0] <= UInt<1>("h1") - T_96[1] <= UInt<1>("h1") - T_96[2] <= UInt<1>("h1") - T_96[3] <= UInt<1>("h1") - T_96[4] <= UInt<1>("h1") - T_96[5] <= UInt<1>("h1") - T_96[6] <= UInt<1>("h1") - T_96[7] <= UInt<1>("h1") - T_96[8] <= UInt<1>("h1") - reg roq_free : UInt<1>[9], clk with : - reset => (reset, T_96) - node T_129 = mux(roq_free[7], UInt<3>("h7"), UInt<4>("h8")) - node T_130 = mux(roq_free[6], UInt<3>("h6"), T_129) - node T_131 = mux(roq_free[5], UInt<3>("h5"), T_130) - node T_132 = mux(roq_free[4], UInt<3>("h4"), T_131) - node T_133 = mux(roq_free[3], UInt<2>("h3"), T_132) - node T_134 = mux(roq_free[2], UInt<2>("h2"), T_133) - node T_135 = mux(roq_free[1], UInt<1>("h1"), T_134) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h0"), T_135) - node T_137 = eq(roq_tags[0], io.deq.tag) - node T_139 = eq(roq_free[0], UInt<1>("h0")) - node T_140 = and(T_137, T_139) - node T_141 = eq(roq_tags[1], io.deq.tag) - node T_143 = eq(roq_free[1], UInt<1>("h0")) - node T_144 = and(T_141, T_143) - node T_145 = eq(roq_tags[2], io.deq.tag) - node T_147 = eq(roq_free[2], UInt<1>("h0")) - node T_148 = and(T_145, T_147) - node T_149 = eq(roq_tags[3], io.deq.tag) - node T_151 = eq(roq_free[3], UInt<1>("h0")) - node T_152 = and(T_149, T_151) - node T_153 = eq(roq_tags[4], io.deq.tag) - node T_155 = eq(roq_free[4], UInt<1>("h0")) - node T_156 = and(T_153, T_155) - node T_157 = eq(roq_tags[5], io.deq.tag) - node T_159 = eq(roq_free[5], UInt<1>("h0")) - node T_160 = and(T_157, T_159) - node T_161 = eq(roq_tags[6], io.deq.tag) - node T_163 = eq(roq_free[6], UInt<1>("h0")) - node T_164 = and(T_161, T_163) - node T_165 = eq(roq_tags[7], io.deq.tag) - node T_167 = eq(roq_free[7], UInt<1>("h0")) - node T_168 = and(T_165, T_167) - node T_169 = eq(roq_tags[8], io.deq.tag) - node T_171 = eq(roq_free[8], UInt<1>("h0")) - node T_172 = and(T_169, T_171) - node T_182 = mux(T_168, UInt<3>("h7"), UInt<4>("h8")) - node T_183 = mux(T_164, UInt<3>("h6"), T_182) - node T_184 = mux(T_160, UInt<3>("h5"), T_183) - node T_185 = mux(T_156, UInt<3>("h4"), T_184) - node T_186 = mux(T_152, UInt<2>("h3"), T_185) - node T_187 = mux(T_148, UInt<2>("h2"), T_186) - node T_188 = mux(T_144, UInt<1>("h1"), T_187) - node roq_deq_addr = mux(T_140, UInt<1>("h0"), T_188) - node T_190 = or(roq_free[0], roq_free[1]) - node T_191 = or(T_190, roq_free[2]) - node T_192 = or(T_191, roq_free[3]) - node T_193 = or(T_192, roq_free[4]) - node T_194 = or(T_193, roq_free[5]) - node T_195 = or(T_194, roq_free[6]) - node T_196 = or(T_195, roq_free[7]) - node T_197 = or(T_196, roq_free[8]) - io.enq.ready <= T_197 - io.deq.data <= roq_data[roq_deq_addr] - node T_199 = or(T_140, T_144) - node T_200 = or(T_199, T_148) - node T_201 = or(T_200, T_152) - node T_202 = or(T_201, T_156) - node T_203 = or(T_202, T_160) - node T_204 = or(T_203, T_164) - node T_205 = or(T_204, T_168) - node T_206 = or(T_205, T_172) - io.deq.matches <= T_206 - node T_207 = and(io.enq.valid, io.enq.ready) - when T_207 : - roq_data[roq_enq_addr] <= io.enq.bits.data - roq_tags[roq_enq_addr] <= io.enq.bits.tag - roq_free[roq_enq_addr] <= UInt<1>("h0") - skip - when io.deq.valid : - roq_free[roq_deq_addr] <= UInt<1>("h1") - skip - module ClientTileLinkIOUnwrapper : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, out : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io is invalid - inst acqArb of LockingRRArbiter_67 - acqArb.io is invalid - acqArb.clk <= clk - acqArb.reset <= reset - inst acqRoq of ReorderQueue - acqRoq.io is invalid - acqRoq.clk <= clk - acqRoq.reset <= reset - inst relRoq of ReorderQueue - relRoq.io is invalid - relRoq.clk <= clk - relRoq.reset <= reset - node T_1215 = and(UInt<1>("h1"), io.in.acquire.bits.is_builtin_type) - wire T_1218 : UInt<3>[1] - T_1218[0] <= UInt<3>("h3") - node T_1221 = eq(T_1218[0], io.in.acquire.bits.a_type) - node T_1223 = or(UInt<1>("h0"), T_1221) - node T_1224 = and(T_1215, T_1223) - node T_1226 = eq(T_1224, UInt<1>("h0")) - node T_1228 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h0")) - node acq_roq_enq = or(T_1226, T_1228) - wire T_1232 : UInt<2>[3] - T_1232[0] <= UInt<1>("h0") - T_1232[1] <= UInt<1>("h1") - T_1232[2] <= UInt<2>("h2") - node T_1237 = eq(T_1232[0], io.in.release.bits.r_type) - node T_1238 = eq(T_1232[1], io.in.release.bits.r_type) - node T_1239 = eq(T_1232[2], io.in.release.bits.r_type) - node T_1241 = or(UInt<1>("h0"), T_1237) - node T_1242 = or(T_1241, T_1238) - node T_1243 = or(T_1242, T_1239) - node T_1244 = and(UInt<1>("h1"), T_1243) - node T_1246 = eq(T_1244, UInt<1>("h0")) - node T_1248 = eq(io.in.release.bits.addr_beat, UInt<1>("h0")) - node rel_roq_enq = or(T_1246, T_1248) - node T_1251 = eq(acq_roq_enq, UInt<1>("h0")) - node acq_roq_ready = or(T_1251, acqRoq.io.enq.ready) - node T_1254 = eq(rel_roq_enq, UInt<1>("h0")) - node rel_roq_ready = or(T_1254, relRoq.io.enq.ready) - node T_1256 = and(io.in.acquire.valid, acqArb.io.in[0].ready) - node T_1257 = and(T_1256, acq_roq_enq) - acqRoq.io.enq.valid <= T_1257 - acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type - acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - node T_1258 = and(io.in.acquire.valid, acq_roq_ready) - acqArb.io.in[0].valid <= T_1258 - node T_1261 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h1")) - node T_1263 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1264 = cat(UInt<3>("h7"), T_1263) - node T_1265 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1264) - wire T_1294 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1294 is invalid - T_1294.is_builtin_type <= UInt<1>("h1") - T_1294.a_type <= T_1261 - T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1294.addr_block <= io.in.acquire.bits.addr_block - T_1294.addr_beat <= io.in.acquire.bits.addr_beat - T_1294.data <= io.in.acquire.bits.data - T_1294.union <= T_1265 - acqArb.io.in[0].bits <- T_1294 - node T_1322 = and(acq_roq_ready, acqArb.io.in[0].ready) - io.in.acquire.ready <= T_1322 - node T_1323 = and(io.in.release.valid, acqArb.io.in[1].ready) - node T_1324 = and(T_1323, rel_roq_enq) - relRoq.io.enq.valid <= T_1324 - relRoq.io.enq.bits.data <= io.in.release.bits.voluntary - relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id - node T_1325 = and(io.in.release.valid, rel_roq_ready) - acqArb.io.in[1].valid <= T_1325 - node T_1347 = asUInt(asSInt(UInt<16>("hffff"))) - node T_1355 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1356 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1357 = cat(T_1355, T_1356) - node T_1359 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1360 = cat(UInt<3>("h7"), T_1359) - node T_1362 = cat(T_1347, UInt<1>("h1")) - node T_1364 = cat(T_1347, UInt<1>("h1")) - node T_1366 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1367 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1368 = cat(T_1366, T_1367) - node T_1370 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1372 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_1373 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_1374 = mux(T_1373, T_1372, UInt<1>("h0")) - node T_1375 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_1376 = mux(T_1375, T_1370, T_1374) - node T_1377 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_1378 = mux(T_1377, T_1368, T_1376) - node T_1379 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_1380 = mux(T_1379, T_1364, T_1378) - node T_1381 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_1382 = mux(T_1381, T_1362, T_1380) - node T_1383 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_1384 = mux(T_1383, T_1360, T_1382) - node T_1385 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_1386 = mux(T_1385, T_1357, T_1384) - wire T_1415 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1415 is invalid - T_1415.is_builtin_type <= UInt<1>("h1") - T_1415.a_type <= UInt<3>("h3") - T_1415.client_xact_id <= io.in.release.bits.client_xact_id - T_1415.addr_block <= io.in.release.bits.addr_block - T_1415.addr_beat <= io.in.release.bits.addr_beat - T_1415.data <= io.in.release.bits.data - T_1415.union <= T_1386 - acqArb.io.in[1].bits <- T_1415 - node T_1443 = and(rel_roq_ready, acqArb.io.in[1].ready) - io.in.release.ready <= T_1443 - io.out.acquire <- acqArb.io.out - node T_1444 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1448 : UInt<3>[1] - T_1448[0] <= UInt<3>("h5") - node T_1451 = eq(T_1448[0], io.out.grant.bits.g_type) - node T_1453 = or(UInt<1>("h0"), T_1451) - wire T_1455 : UInt<1>[1] - T_1455[0] <= UInt<1>("h0") - node T_1458 = eq(T_1455[0], io.out.grant.bits.g_type) - node T_1460 = or(UInt<1>("h0"), T_1458) - node T_1461 = mux(io.out.grant.bits.is_builtin_type, T_1453, T_1460) - node T_1462 = and(UInt<1>("h1"), T_1461) - node T_1464 = eq(T_1462, UInt<1>("h0")) - node T_1466 = eq(io.out.grant.bits.addr_beat, UInt<2>("h3")) - node T_1467 = or(T_1464, T_1466) - node T_1468 = and(T_1444, T_1467) - acqRoq.io.deq.valid <= T_1468 - acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1469 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1473 : UInt<3>[1] - T_1473[0] <= UInt<3>("h5") - node T_1476 = eq(T_1473[0], io.out.grant.bits.g_type) - node T_1478 = or(UInt<1>("h0"), T_1476) - wire T_1480 : UInt<1>[1] - T_1480[0] <= UInt<1>("h0") - node T_1483 = eq(T_1480[0], io.out.grant.bits.g_type) - node T_1485 = or(UInt<1>("h0"), T_1483) - node T_1486 = mux(io.out.grant.bits.is_builtin_type, T_1478, T_1485) - node T_1487 = and(UInt<1>("h1"), T_1486) - node T_1489 = eq(T_1487, UInt<1>("h0")) - node T_1491 = eq(io.out.grant.bits.addr_beat, UInt<2>("h3")) - node T_1492 = or(T_1489, T_1491) - node T_1493 = and(T_1469, T_1492) - relRoq.io.deq.valid <= T_1493 - relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1494 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h0")) - wire acq_grant : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - acq_grant is invalid - acq_grant.is_builtin_type <= acqRoq.io.deq.data - acq_grant.g_type <= T_1494 - acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id - acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id - acq_grant.addr_beat <= io.out.grant.bits.addr_beat - acq_grant.data <= io.out.grant.bits.data - node T_1551 = mux(relRoq.io.deq.data, UInt<3>("h0"), io.out.grant.bits.g_type) - wire rel_grant : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - rel_grant is invalid - rel_grant.is_builtin_type <= UInt<1>("h1") - rel_grant.g_type <= T_1551 - rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id - rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id - rel_grant.addr_beat <= io.out.grant.bits.addr_beat - rel_grant.data <= io.out.grant.bits.data - io.in.grant.valid <= io.out.grant.valid - node T_1606 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant) - io.in.grant.bits <- T_1606 - io.out.grant.ready <= io.in.grant.ready - io.in.probe.valid <= UInt<1>("h0") - module TileLinkIONarrower : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - io is invalid - node T_815 = eq(io.in.acquire.bits.a_type, UInt<3>("h3")) - node T_817 = eq(io.in.acquire.bits.a_type, UInt<3>("h1")) - node T_819 = eq(io.in.acquire.bits.a_type, UInt<3>("h2")) - node T_821 = eq(io.in.acquire.bits.a_type, UInt<3>("h0")) - reg T_823 : UInt<128>, clk with : - reset => (UInt<1>("h0"), T_823) - reg T_825 : UInt<16>, clk with : - reset => (UInt<1>("h0"), T_825) - reg T_826 : UInt<4>, clk with : - reset => (UInt<1>("h0"), T_826) - reg T_827 : UInt<26>, clk with : - reset => (UInt<1>("h0"), T_827) - reg T_828 : UInt<2>, clk with : - reset => (UInt<1>("h0"), T_828) - reg T_830 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_831 = bits(io.in.acquire.bits.union, 12, 9) - node T_832 = cat(io.in.acquire.bits.addr_beat, T_831) - node T_833 = cat(io.in.acquire.bits.addr_block, T_832) - node T_834 = bits(T_833, 3, 3) - node T_835 = bits(io.in.acquire.bits.union, 12, 9) - node T_836 = cat(io.in.acquire.bits.addr_beat, T_835) - node T_837 = cat(io.in.acquire.bits.addr_block, T_836) - node T_838 = bits(T_837, 5, 3) - node T_839 = bits(io.in.acquire.bits.union, 12, 9) - node T_840 = cat(io.in.acquire.bits.addr_beat, T_839) - node T_841 = cat(io.in.acquire.bits.addr_block, T_840) - node T_842 = bits(T_841, 2, 0) - node T_843 = bits(io.in.acquire.bits.union, 12, 9) - node T_844 = bits(T_843, 3, 3) - node T_846 = dshl(UInt<1>("h1"), T_844) - node T_848 = eq(io.in.acquire.bits.a_type, UInt<3>("h4")) - node T_849 = and(io.in.acquire.bits.is_builtin_type, T_848) - node T_850 = bits(T_846, 0, 0) - node T_851 = bits(T_846, 1, 1) - wire T_853 : UInt<1>[2] - T_853[0] <= T_850 - T_853[1] <= T_851 - node T_858 = sub(UInt<8>("h0"), T_853[0]) - node T_859 = tail(T_858, 1) - node T_861 = sub(UInt<8>("h0"), T_853[1]) - node T_862 = tail(T_861, 1) - wire T_864 : UInt<8>[2] - T_864[0] <= T_859 - T_864[1] <= T_862 - node T_868 = cat(T_864[1], T_864[0]) - node T_870 = eq(io.in.acquire.bits.a_type, UInt<3>("h3")) - node T_871 = and(io.in.acquire.bits.is_builtin_type, T_870) - node T_873 = eq(io.in.acquire.bits.a_type, UInt<3>("h2")) - node T_874 = and(io.in.acquire.bits.is_builtin_type, T_873) - node T_875 = or(T_871, T_874) - node T_876 = bits(io.in.acquire.bits.union, 16, 1) - node T_878 = mux(T_875, T_876, UInt<16>("h0")) - node T_879 = mux(T_849, T_868, T_878) - node T_880 = bits(T_879, 7, 0) - node T_881 = bits(io.in.acquire.bits.union, 12, 9) - node T_882 = bits(T_881, 3, 3) - node T_884 = dshl(UInt<1>("h1"), T_882) - node T_886 = eq(io.in.acquire.bits.a_type, UInt<3>("h4")) - node T_887 = and(io.in.acquire.bits.is_builtin_type, T_886) - node T_888 = bits(T_884, 0, 0) - node T_889 = bits(T_884, 1, 1) - wire T_891 : UInt<1>[2] - T_891[0] <= T_888 - T_891[1] <= T_889 - node T_896 = sub(UInt<8>("h0"), T_891[0]) - node T_897 = tail(T_896, 1) - node T_899 = sub(UInt<8>("h0"), T_891[1]) - node T_900 = tail(T_899, 1) - wire T_902 : UInt<8>[2] - T_902[0] <= T_897 - T_902[1] <= T_900 - node T_906 = cat(T_902[1], T_902[0]) - node T_908 = eq(io.in.acquire.bits.a_type, UInt<3>("h3")) - node T_909 = and(io.in.acquire.bits.is_builtin_type, T_908) - node T_911 = eq(io.in.acquire.bits.a_type, UInt<3>("h2")) - node T_912 = and(io.in.acquire.bits.is_builtin_type, T_911) - node T_913 = or(T_909, T_912) - node T_914 = bits(io.in.acquire.bits.union, 16, 1) - node T_916 = mux(T_913, T_914, UInt<16>("h0")) - node T_917 = mux(T_887, T_906, T_916) - node T_918 = bits(T_917, 15, 8) - wire T_920 : UInt<8>[2] - T_920[0] <= T_880 - T_920[1] <= T_918 - node T_924 = bits(io.in.acquire.bits.data, 63, 0) - node T_925 = bits(io.in.acquire.bits.data, 127, 64) - wire T_927 : UInt<64>[2] - T_927[0] <= T_924 - T_927[1] <= T_925 - node T_932 = neq(T_920[0], UInt<1>("h0")) - node T_934 = neq(T_920[1], UInt<1>("h0")) - node T_935 = cat(T_934, T_932) - node T_936 = bits(T_935, 0, 0) - node T_937 = bits(T_935, 1, 1) - node T_939 = mux(T_936, T_927[0], UInt<1>("h0")) - node T_941 = mux(T_937, T_927[1], UInt<1>("h0")) - node T_943 = or(T_939, T_941) - wire T_944 : UInt<64> - T_944 is invalid - T_944 <= T_943 - node T_945 = bits(T_935, 0, 0) - node T_946 = bits(T_935, 1, 1) - node T_948 = mux(T_945, T_920[0], UInt<1>("h0")) - node T_950 = mux(T_946, T_920[1], UInt<1>("h0")) - node T_952 = or(T_948, T_950) - wire T_953 : UInt<8> - T_953 is invalid - T_953 <= T_952 - node T_954 = bits(T_935, 0, 0) - node T_955 = bits(T_935, 1, 1) - wire T_957 : UInt<1>[2] - T_957[0] <= T_954 - T_957[1] <= T_955 - node T_963 = mux(T_957[0], UInt<1>("h0"), UInt<1>("h1")) - node T_964 = cat(io.in.acquire.bits.addr_beat, T_963) - node T_966 = eq(io.in.acquire.valid, UInt<1>("h0")) - node T_968 = eq(T_819, UInt<1>("h0")) - node T_969 = or(T_966, T_968) - node T_970 = bits(T_935, 0, 0) - node T_971 = bits(T_935, 1, 1) - node T_973 = cat(UInt<1>("h0"), T_971) - node T_974 = add(T_970, T_973) - node T_975 = tail(T_974, 1) - node T_977 = leq(T_975, UInt<1>("h1")) - node T_978 = or(T_969, T_977) - node T_980 = eq(reset, UInt<1>("h0")) - when T_980 : - node T_982 = eq(T_978, UInt<1>("h0")) - when T_982 : - node T_984 = eq(reset, UInt<1>("h0")) - when T_984 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_985 = bits(io.in.acquire.bits.union, 8, 6) - node T_994 = eq(UInt<3>("h7"), T_985) - node T_995 = mux(T_994, UInt<1>("h0"), UInt<1>("h0")) - node T_996 = eq(UInt<3>("h3"), T_985) - node T_997 = mux(T_996, UInt<1>("h1"), T_995) - node T_998 = eq(UInt<3>("h2"), T_985) - node T_999 = mux(T_998, UInt<1>("h1"), T_997) - node T_1000 = eq(UInt<3>("h5"), T_985) - node T_1001 = mux(T_1000, UInt<1>("h1"), T_999) - node T_1002 = eq(UInt<3>("h1"), T_985) - node T_1003 = mux(T_1002, UInt<1>("h1"), T_1001) - node T_1004 = eq(UInt<3>("h4"), T_985) - node T_1005 = mux(T_1004, UInt<1>("h1"), T_1003) - node T_1006 = eq(UInt<3>("h0"), T_985) - node T_1007 = mux(T_1006, UInt<1>("h1"), T_1005) - node T_1009 = eq(io.in.acquire.valid, UInt<1>("h0")) - node T_1011 = eq(T_821, UInt<1>("h0")) - node T_1012 = or(T_1009, T_1011) - node T_1013 = or(T_1012, T_1007) - node T_1015 = eq(reset, UInt<1>("h0")) - when T_1015 : - node T_1017 = eq(T_1013, UInt<1>("h0")) - when T_1017 : - node T_1019 = eq(reset, UInt<1>("h0")) - when T_1019 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1020 = bits(io.in.acquire.bits.union, 0, 0) - node T_1029 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1030 = cat(UInt<5>("h0"), T_1020) - node T_1031 = cat(T_1029, T_1030) - node T_1033 = cat(UInt<5>("h0"), T_1020) - node T_1034 = cat(UInt<3>("h7"), T_1033) - node T_1036 = cat(UInt<1>("h0"), T_1020) - node T_1038 = cat(UInt<1>("h0"), T_1020) - node T_1040 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1041 = cat(UInt<5>("h0"), T_1020) - node T_1042 = cat(T_1040, T_1041) - node T_1044 = cat(UInt<5>("h0"), T_1020) - node T_1046 = cat(UInt<5>("h1"), T_1020) - node T_1047 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_1048 = mux(T_1047, T_1046, UInt<1>("h0")) - node T_1049 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_1050 = mux(T_1049, T_1044, T_1048) - node T_1051 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_1052 = mux(T_1051, T_1042, T_1050) - node T_1053 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_1054 = mux(T_1053, T_1038, T_1052) - node T_1055 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_1056 = mux(T_1055, T_1036, T_1054) - node T_1057 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_1058 = mux(T_1057, T_1034, T_1056) - node T_1059 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_1060 = mux(T_1059, T_1031, T_1058) - wire T_1089 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1089 is invalid - T_1089.is_builtin_type <= UInt<1>("h1") - T_1089.a_type <= UInt<3>("h1") - T_1089.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1089.addr_block <= io.in.acquire.bits.addr_block - T_1089.addr_beat <= UInt<1>("h0") - T_1089.data <= UInt<1>("h0") - T_1089.union <= T_1060 - node T_1117 = cat(T_828, T_830) - node T_1118 = bits(T_823, 63, 0) - node T_1119 = bits(T_825, 7, 0) - node T_1127 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1128 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1129 = cat(T_1127, T_1128) - node T_1131 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1132 = cat(UInt<3>("h7"), T_1131) - node T_1134 = cat(T_1119, UInt<1>("h1")) - node T_1136 = cat(T_1119, UInt<1>("h1")) - node T_1138 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1139 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1140 = cat(T_1138, T_1139) - node T_1142 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1144 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_1145 = eq(UInt<3>("h6"), UInt<3>("h3")) - node T_1146 = mux(T_1145, T_1144, UInt<1>("h0")) - node T_1147 = eq(UInt<3>("h5"), UInt<3>("h3")) - node T_1148 = mux(T_1147, T_1142, T_1146) - node T_1149 = eq(UInt<3>("h4"), UInt<3>("h3")) - node T_1150 = mux(T_1149, T_1140, T_1148) - node T_1151 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_1152 = mux(T_1151, T_1136, T_1150) - node T_1153 = eq(UInt<3>("h2"), UInt<3>("h3")) - node T_1154 = mux(T_1153, T_1134, T_1152) - node T_1155 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_1156 = mux(T_1155, T_1132, T_1154) - node T_1157 = eq(UInt<3>("h0"), UInt<3>("h3")) - node T_1158 = mux(T_1157, T_1129, T_1156) - wire T_1187 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1187 is invalid - T_1187.is_builtin_type <= UInt<1>("h1") - T_1187.a_type <= UInt<3>("h3") - T_1187.client_xact_id <= T_826 - T_1187.addr_block <= T_827 - T_1187.addr_beat <= T_1117 - T_1187.data <= T_1118 - T_1187.union <= T_1158 - node T_1215 = bits(io.in.acquire.bits.union, 8, 6) - node T_1216 = bits(io.in.acquire.bits.union, 0, 0) - node T_1223 = cat(T_842, T_1215) - node T_1224 = cat(UInt<5>("h0"), T_1216) - node T_1225 = cat(T_1223, T_1224) - node T_1227 = cat(UInt<5>("h0"), T_1216) - node T_1228 = cat(T_1215, T_1227) - node T_1230 = cat(UInt<1>("h0"), T_1216) - node T_1232 = cat(UInt<1>("h0"), T_1216) - node T_1234 = cat(T_842, T_1215) - node T_1235 = cat(UInt<5>("h0"), T_1216) - node T_1236 = cat(T_1234, T_1235) - node T_1238 = cat(UInt<5>("h0"), T_1216) - node T_1240 = cat(UInt<5>("h1"), T_1216) - node T_1241 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_1242 = mux(T_1241, T_1240, UInt<1>("h0")) - node T_1243 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_1244 = mux(T_1243, T_1238, T_1242) - node T_1245 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_1246 = mux(T_1245, T_1236, T_1244) - node T_1247 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_1248 = mux(T_1247, T_1232, T_1246) - node T_1249 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_1250 = mux(T_1249, T_1230, T_1248) - node T_1251 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_1252 = mux(T_1251, T_1228, T_1250) - node T_1253 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_1254 = mux(T_1253, T_1225, T_1252) - wire T_1283 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1283 is invalid - T_1283.is_builtin_type <= UInt<1>("h1") - T_1283.a_type <= UInt<3>("h0") - T_1283.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1283.addr_block <= io.in.acquire.bits.addr_block - T_1283.addr_beat <= T_838 - T_1283.data <= UInt<1>("h0") - T_1283.union <= T_1254 - node T_1318 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1319 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1320 = cat(T_1318, T_1319) - node T_1322 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1323 = cat(UInt<3>("h7"), T_1322) - node T_1325 = cat(T_953, UInt<1>("h1")) - node T_1327 = cat(T_953, UInt<1>("h1")) - node T_1329 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1330 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_1331 = cat(T_1329, T_1330) - node T_1333 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_1335 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_1336 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_1337 = mux(T_1336, T_1335, UInt<1>("h0")) - node T_1338 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_1339 = mux(T_1338, T_1333, T_1337) - node T_1340 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_1341 = mux(T_1340, T_1331, T_1339) - node T_1342 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_1343 = mux(T_1342, T_1327, T_1341) - node T_1344 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_1345 = mux(T_1344, T_1325, T_1343) - node T_1346 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_1347 = mux(T_1346, T_1323, T_1345) - node T_1348 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_1349 = mux(T_1348, T_1320, T_1347) - wire T_1378 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1378 is invalid - T_1378.is_builtin_type <= UInt<1>("h1") - T_1378.a_type <= UInt<3>("h2") - T_1378.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1378.addr_block <= io.in.acquire.bits.addr_block - T_1378.addr_beat <= T_964 - T_1378.data <= T_944 - T_1378.union <= T_1349 - reg T_1407 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1409 = eq(T_815, UInt<1>("h0")) - node T_1410 = and(io.in.acquire.valid, T_1409) - node T_1412 = eq(T_821, UInt<1>("h0")) - node T_1413 = and(T_1410, T_1412) - node T_1414 = and(T_821, io.in.acquire.valid) - inst T_1415 of ReorderQueue - T_1415.io is invalid - T_1415.clk <= clk - T_1415.reset <= reset - node T_1417 = eq(T_1407, UInt<1>("h0")) - node T_1418 = and(T_1414, io.out.acquire.ready) - node T_1419 = and(T_1418, T_1417) - T_1415.io.enq.valid <= T_1419 - T_1415.io.enq.bits.data <= T_834 - T_1415.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - wire T_1420 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1420 <- io.in.acquire.bits - node T_1448 = mux(T_821, T_1283, T_1420) - node T_1476 = mux(T_819, T_1378, T_1448) - node T_1504 = mux(T_817, T_1089, T_1476) - node T_1532 = mux(T_1407, T_1187, T_1504) - io.out.acquire.bits <- T_1532 - node T_1560 = or(T_1407, T_1413) - node T_1561 = and(T_1414, T_1415.io.enq.ready) - node T_1562 = or(T_1560, T_1561) - io.out.acquire.valid <= T_1562 - node T_1564 = eq(T_1407, UInt<1>("h0")) - node T_1566 = eq(T_821, UInt<1>("h0")) - node T_1567 = and(T_1566, io.out.acquire.ready) - node T_1568 = or(T_815, T_1567) - node T_1569 = and(T_1415.io.enq.ready, io.out.acquire.ready) - node T_1570 = or(T_1568, T_1569) - node T_1571 = and(T_1564, T_1570) - io.in.acquire.ready <= T_1571 - node T_1572 = and(io.in.acquire.ready, io.in.acquire.valid) - node T_1573 = and(T_1572, T_815) - when T_1573 : - T_823 <= io.in.acquire.bits.data - node T_1574 = bits(io.in.acquire.bits.union, 12, 9) - node T_1575 = bits(T_1574, 3, 3) - node T_1577 = dshl(UInt<1>("h1"), T_1575) - node T_1579 = eq(io.in.acquire.bits.a_type, UInt<3>("h4")) - node T_1580 = and(io.in.acquire.bits.is_builtin_type, T_1579) - node T_1581 = bits(T_1577, 0, 0) - node T_1582 = bits(T_1577, 1, 1) - wire T_1584 : UInt<1>[2] - T_1584[0] <= T_1581 - T_1584[1] <= T_1582 - node T_1589 = sub(UInt<8>("h0"), T_1584[0]) - node T_1590 = tail(T_1589, 1) - node T_1592 = sub(UInt<8>("h0"), T_1584[1]) - node T_1593 = tail(T_1592, 1) - wire T_1595 : UInt<8>[2] - T_1595[0] <= T_1590 - T_1595[1] <= T_1593 - node T_1599 = cat(T_1595[1], T_1595[0]) - node T_1601 = eq(io.in.acquire.bits.a_type, UInt<3>("h3")) - node T_1602 = and(io.in.acquire.bits.is_builtin_type, T_1601) - node T_1604 = eq(io.in.acquire.bits.a_type, UInt<3>("h2")) - node T_1605 = and(io.in.acquire.bits.is_builtin_type, T_1604) - node T_1606 = or(T_1602, T_1605) - node T_1607 = bits(io.in.acquire.bits.union, 16, 1) - node T_1609 = mux(T_1606, T_1607, UInt<16>("h0")) - node T_1610 = mux(T_1580, T_1599, T_1609) - T_825 <= T_1610 - T_826 <= io.in.acquire.bits.client_xact_id - T_827 <= io.in.acquire.bits.addr_block - T_828 <= io.in.acquire.bits.addr_beat - T_1407 <= UInt<1>("h1") - skip - node T_1612 = and(T_1407, io.out.acquire.ready) - when T_1612 : - node T_1613 = shr(T_823, 64) - T_823 <= T_1613 - node T_1614 = shr(T_825, 8) - T_825 <= T_1614 - node T_1616 = eq(T_830, UInt<1>("h1")) - node T_1618 = and(UInt<1>("h0"), T_1616) - node T_1621 = add(T_830, UInt<1>("h1")) - node T_1622 = tail(T_1621, 1) - node T_1623 = mux(T_1618, UInt<1>("h0"), T_1622) - T_830 <= T_1623 - when T_1616 : - T_1407 <= UInt<1>("h0") - skip - skip - wire T_1628 : UInt<3>[1] - T_1628[0] <= UInt<3>("h5") - node T_1631 = eq(T_1628[0], io.out.grant.bits.g_type) - node T_1633 = or(UInt<1>("h0"), T_1631) - wire T_1635 : UInt<1>[1] - T_1635[0] <= UInt<1>("h0") - node T_1638 = eq(T_1635[0], io.out.grant.bits.g_type) - node T_1640 = or(UInt<1>("h0"), T_1638) - node T_1641 = mux(io.out.grant.bits.is_builtin_type, T_1633, T_1640) - node T_1642 = and(UInt<1>("h1"), T_1641) - reg T_1651 : UInt<64>[2], clk with : - reset => (UInt<1>("h0"), T_1651) - reg T_1655 : UInt<4>, clk with : - reset => (UInt<1>("h0"), T_1655) - reg T_1656 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_1656) - reg T_1658 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - reg T_1660 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_1662 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_1665 = cat(T_1651[1], T_1651[0]) - wire T_1693 : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1693 is invalid - T_1693.is_builtin_type <= UInt<1>("h1") - T_1693.g_type <= UInt<3>("h5") - T_1693.client_xact_id <= T_1655 - T_1693.manager_xact_id <= T_1656 - T_1693.addr_beat <= T_1658 - T_1693.data <= T_1665 - node T_1721 = eq(io.out.grant.bits.g_type, UInt<3>("h4")) - node T_1723 = cat(T_1415.io.deq.data, UInt<6>("h0")) - node T_1724 = and(io.out.grant.ready, io.out.grant.valid) - node T_1725 = and(T_1724, T_1721) - T_1415.io.deq.valid <= T_1725 - T_1415.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1729 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h1")) - node T_1730 = dshl(io.out.grant.bits.data, T_1723) - wire T_1758 : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1758 is invalid - T_1758.is_builtin_type <= UInt<1>("h1") - T_1758.g_type <= UInt<3>("h4") - T_1758.client_xact_id <= io.out.grant.bits.client_xact_id - T_1758.manager_xact_id <= io.out.grant.bits.manager_xact_id - T_1758.addr_beat <= T_1729 - T_1758.data <= T_1730 - node T_1786 = eq(T_1642, UInt<1>("h0")) - node T_1787 = and(io.out.grant.valid, T_1786) - node T_1788 = or(T_1662, T_1787) - io.in.grant.valid <= T_1788 - node T_1790 = eq(T_1662, UInt<1>("h0")) - node T_1791 = or(T_1642, io.in.grant.ready) - node T_1792 = and(T_1790, T_1791) - io.out.grant.ready <= T_1792 - wire T_1793 : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1793 <- io.out.grant.bits - node T_1820 = mux(T_1721, T_1758, T_1793) - node T_1847 = mux(T_1662, T_1693, T_1820) - io.in.grant.bits <- T_1847 - node T_1874 = and(io.out.grant.valid, T_1642) - node T_1876 = eq(T_1662, UInt<1>("h0")) - node T_1877 = and(T_1874, T_1876) - when T_1877 : - T_1651[T_1660] <= io.out.grant.bits.data - node T_1880 = eq(T_1660, UInt<1>("h1")) - node T_1882 = and(UInt<1>("h0"), T_1880) - node T_1885 = add(T_1660, UInt<1>("h1")) - node T_1886 = tail(T_1885, 1) - node T_1887 = mux(T_1882, UInt<1>("h0"), T_1886) - T_1660 <= T_1887 - when T_1880 : - T_1655 <= io.out.grant.bits.client_xact_id - T_1656 <= io.out.grant.bits.manager_xact_id - T_1662 <= UInt<1>("h1") - skip - skip - node T_1889 = and(io.in.grant.ready, T_1662) - when T_1889 : - node T_1891 = eq(T_1658, UInt<2>("h3")) - node T_1893 = and(UInt<1>("h0"), T_1891) - node T_1896 = add(T_1658, UInt<1>("h1")) - node T_1897 = tail(T_1896, 1) - node T_1898 = mux(T_1893, UInt<1>("h0"), T_1897) - T_1658 <= T_1898 - T_1662 <= UInt<1>("h0") - skip - module ReorderQueue_70 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : { addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, tag : UInt<5>}}, deq : {flip valid : UInt<1>, flip tag : UInt<5>, data : { addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} - io is invalid - reg roq_data : { addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk with : - reset => (UInt<1>("h0"), roq_data) - reg roq_tags : UInt<5>[9], clk with : - reset => (UInt<1>("h0"), roq_tags) - wire T_832 : UInt<1>[9] - T_832[0] <= UInt<1>("h1") - T_832[1] <= UInt<1>("h1") - T_832[2] <= UInt<1>("h1") - T_832[3] <= UInt<1>("h1") - T_832[4] <= UInt<1>("h1") - T_832[5] <= UInt<1>("h1") - T_832[6] <= UInt<1>("h1") - T_832[7] <= UInt<1>("h1") - T_832[8] <= UInt<1>("h1") - reg roq_free : UInt<1>[9], clk with : - reset => (reset, T_832) - node T_865 = mux(roq_free[7], UInt<3>("h7"), UInt<4>("h8")) - node T_866 = mux(roq_free[6], UInt<3>("h6"), T_865) - node T_867 = mux(roq_free[5], UInt<3>("h5"), T_866) - node T_868 = mux(roq_free[4], UInt<3>("h4"), T_867) - node T_869 = mux(roq_free[3], UInt<2>("h3"), T_868) - node T_870 = mux(roq_free[2], UInt<2>("h2"), T_869) - node T_871 = mux(roq_free[1], UInt<1>("h1"), T_870) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h0"), T_871) - node T_873 = eq(roq_tags[0], io.deq.tag) - node T_875 = eq(roq_free[0], UInt<1>("h0")) - node T_876 = and(T_873, T_875) - node T_877 = eq(roq_tags[1], io.deq.tag) - node T_879 = eq(roq_free[1], UInt<1>("h0")) - node T_880 = and(T_877, T_879) - node T_881 = eq(roq_tags[2], io.deq.tag) - node T_883 = eq(roq_free[2], UInt<1>("h0")) - node T_884 = and(T_881, T_883) - node T_885 = eq(roq_tags[3], io.deq.tag) - node T_887 = eq(roq_free[3], UInt<1>("h0")) - node T_888 = and(T_885, T_887) - node T_889 = eq(roq_tags[4], io.deq.tag) - node T_891 = eq(roq_free[4], UInt<1>("h0")) - node T_892 = and(T_889, T_891) - node T_893 = eq(roq_tags[5], io.deq.tag) - node T_895 = eq(roq_free[5], UInt<1>("h0")) - node T_896 = and(T_893, T_895) - node T_897 = eq(roq_tags[6], io.deq.tag) - node T_899 = eq(roq_free[6], UInt<1>("h0")) - node T_900 = and(T_897, T_899) - node T_901 = eq(roq_tags[7], io.deq.tag) - node T_903 = eq(roq_free[7], UInt<1>("h0")) - node T_904 = and(T_901, T_903) - node T_905 = eq(roq_tags[8], io.deq.tag) - node T_907 = eq(roq_free[8], UInt<1>("h0")) - node T_908 = and(T_905, T_907) - node T_918 = mux(T_904, UInt<3>("h7"), UInt<4>("h8")) - node T_919 = mux(T_900, UInt<3>("h6"), T_918) - node T_920 = mux(T_896, UInt<3>("h5"), T_919) - node T_921 = mux(T_892, UInt<3>("h4"), T_920) - node T_922 = mux(T_888, UInt<2>("h3"), T_921) - node T_923 = mux(T_884, UInt<2>("h2"), T_922) - node T_924 = mux(T_880, UInt<1>("h1"), T_923) - node roq_deq_addr = mux(T_876, UInt<1>("h0"), T_924) - node T_926 = or(roq_free[0], roq_free[1]) - node T_927 = or(T_926, roq_free[2]) - node T_928 = or(T_927, roq_free[3]) - node T_929 = or(T_928, roq_free[4]) - node T_930 = or(T_929, roq_free[5]) - node T_931 = or(T_930, roq_free[6]) - node T_932 = or(T_931, roq_free[7]) - node T_933 = or(T_932, roq_free[8]) - io.enq.ready <= T_933 - io.deq.data <- roq_data[roq_deq_addr] - node T_958 = or(T_876, T_880) - node T_959 = or(T_958, T_884) - node T_960 = or(T_959, T_888) - node T_961 = or(T_960, T_892) - node T_962 = or(T_961, T_896) - node T_963 = or(T_962, T_900) - node T_964 = or(T_963, T_904) - node T_965 = or(T_964, T_908) - io.deq.matches <= T_965 - node T_966 = and(io.enq.valid, io.enq.ready) - when T_966 : - roq_data[roq_enq_addr] <- io.enq.bits.data - roq_tags[roq_enq_addr] <= io.enq.bits.tag - roq_free[roq_enq_addr] <= UInt<1>("h0") - skip - when io.deq.valid : - roq_free[roq_deq_addr] <= UInt<1>("h1") - skip - module Arbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} - io is invalid - wire T_658 : UInt<1> - T_658 is invalid - io.out.valid <= io.in[T_658].valid - io.out.bits <- io.in[T_658].bits - io.chosen <= T_658 - io.in[T_658].ready <= UInt<1>("h0") - node T_839 = or(UInt<1>("h0"), io.in[0].valid) - node T_841 = eq(T_839, UInt<1>("h0")) - node T_843 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_844 = mux(UInt<1>("h0"), T_843, UInt<1>("h1")) - node T_845 = and(T_844, io.out.ready) - io.in[0].ready <= T_845 - node T_847 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_848 = mux(UInt<1>("h0"), T_847, T_841) - node T_849 = and(T_848, io.out.ready) - io.in[1].ready <= T_849 - node T_852 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_853 = mux(UInt<1>("h0"), UInt<1>("h1"), T_852) - T_658 <= T_853 - module NastiIOTileLinkIOConverter : - input clk : Clock - input reset : UInt<1> - output io : {flip tl : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io is invalid - wire T_685 : UInt<3>[3] - T_685[0] <= UInt<3>("h2") - T_685[1] <= UInt<3>("h3") - T_685[2] <= UInt<3>("h4") - node T_690 = eq(T_685[0], io.tl.acquire.bits.a_type) - node T_691 = eq(T_685[1], io.tl.acquire.bits.a_type) - node T_692 = eq(T_685[2], io.tl.acquire.bits.a_type) - node T_694 = or(UInt<1>("h0"), T_690) - node T_695 = or(T_694, T_691) - node T_696 = or(T_695, T_692) - node has_data = and(io.tl.acquire.bits.is_builtin_type, T_696) - wire T_702 : UInt<3>[3] - T_702[0] <= UInt<3>("h2") - T_702[1] <= UInt<3>("h0") - T_702[2] <= UInt<3>("h4") - node T_707 = eq(T_702[0], io.tl.acquire.bits.a_type) - node T_708 = eq(T_702[1], io.tl.acquire.bits.a_type) - node T_709 = eq(T_702[2], io.tl.acquire.bits.a_type) - node T_711 = or(UInt<1>("h0"), T_707) - node T_712 = or(T_711, T_708) - node T_713 = or(T_712, T_709) - node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_713) - node T_716 = and(UInt<1>("h1"), io.tl.acquire.bits.is_builtin_type) - wire T_719 : UInt<3>[1] - T_719[0] <= UInt<3>("h3") - node T_722 = eq(T_719[0], io.tl.acquire.bits.a_type) - node T_724 = or(UInt<1>("h0"), T_722) - node is_multibeat = and(T_716, T_724) - node T_726 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_727 = and(T_726, is_multibeat) - reg tl_cnt_out : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - when T_727 : - node T_731 = eq(tl_cnt_out, UInt<3>("h7")) - node T_733 = and(UInt<1>("h0"), T_731) - node T_736 = add(tl_cnt_out, UInt<1>("h1")) - node T_737 = tail(T_736, 1) - node T_738 = mux(T_733, UInt<1>("h0"), T_737) - tl_cnt_out <= T_738 - skip - node tl_wrap_out = and(T_727, T_731) - node T_741 = eq(has_data, UInt<1>("h0")) - node get_valid = and(io.tl.acquire.valid, T_741) - node put_valid = and(io.tl.acquire.valid, has_data) - inst roq of ReorderQueue_70 - roq.io is invalid - roq.clk <= clk - roq.reset <= reset - reg w_inflight : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node aw_ready = or(w_inflight, io.nasti.aw.ready) - node T_772 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_774 = eq(roq.io.deq.data.subblock, UInt<1>("h0")) - node T_775 = and(T_772, T_774) - reg nasti_cnt_out : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - when T_775 : - node T_779 = eq(nasti_cnt_out, UInt<3>("h7")) - node T_781 = and(UInt<1>("h0"), T_779) - node T_784 = add(nasti_cnt_out, UInt<1>("h1")) - node T_785 = tail(T_784, 1) - node T_786 = mux(T_781, UInt<1>("h0"), T_785) - nasti_cnt_out <= T_786 - skip - node nasti_wrap_out = and(T_775, T_779) - node T_788 = and(get_valid, io.nasti.ar.ready) - roq.io.enq.valid <= T_788 - roq.io.enq.bits.tag <= io.nasti.ar.bits.id - roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat - node T_789 = bits(io.tl.acquire.bits.union, 11, 9) - roq.io.enq.bits.data.byteOff <= T_789 - roq.io.enq.bits.data.subblock <= is_subblock - node T_790 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_791 = or(nasti_wrap_out, roq.io.deq.data.subblock) - node T_792 = and(T_790, T_791) - roq.io.deq.valid <= T_792 - roq.io.deq.tag <= io.nasti.r.bits.id - node T_793 = and(get_valid, roq.io.enq.ready) - io.nasti.ar.valid <= T_793 - node T_794 = bits(io.tl.acquire.bits.union, 11, 9) - node T_795 = cat(io.tl.acquire.bits.addr_beat, T_794) - node T_796 = cat(io.tl.acquire.bits.addr_block, T_795) - node T_797 = bits(io.tl.acquire.bits.union, 8, 6) - node T_806 = eq(UInt<3>("h7"), T_797) - node T_807 = mux(T_806, UInt<2>("h3"), UInt<3>("h7")) - node T_808 = eq(UInt<3>("h3"), T_797) - node T_809 = mux(T_808, UInt<2>("h3"), T_807) - node T_810 = eq(UInt<3>("h2"), T_797) - node T_811 = mux(T_810, UInt<2>("h2"), T_809) - node T_812 = eq(UInt<3>("h5"), T_797) - node T_813 = mux(T_812, UInt<1>("h1"), T_811) - node T_814 = eq(UInt<3>("h1"), T_797) - node T_815 = mux(T_814, UInt<1>("h1"), T_813) - node T_816 = eq(UInt<3>("h4"), T_797) - node T_817 = mux(T_816, UInt<1>("h0"), T_815) - node T_818 = eq(UInt<3>("h0"), T_797) - node T_819 = mux(T_818, UInt<1>("h0"), T_817) - node T_821 = mux(is_subblock, T_819, UInt<2>("h3")) - node T_824 = mux(is_subblock, UInt<1>("h0"), UInt<3>("h7")) - wire T_837 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_837 is invalid - T_837.id <= io.tl.acquire.bits.client_xact_id - T_837.addr <= T_796 - T_837.len <= T_824 - T_837.size <= T_821 - T_837.burst <= UInt<2>("h1") - T_837.lock <= UInt<1>("h0") - T_837.cache <= UInt<1>("h0") - T_837.prot <= UInt<1>("h0") - T_837.qos <= UInt<1>("h0") - T_837.region <= UInt<1>("h0") - T_837.user <= UInt<1>("h0") - io.nasti.ar.bits <- T_837 - node T_856 = eq(w_inflight, UInt<1>("h0")) - node T_857 = and(put_valid, io.nasti.w.ready) - node T_858 = and(T_857, T_856) - io.nasti.aw.valid <= T_858 - node T_859 = bits(io.tl.acquire.bits.union, 11, 9) - node T_860 = cat(io.tl.acquire.bits.addr_beat, T_859) - node T_861 = cat(io.tl.acquire.bits.addr_block, T_860) - node T_865 = mux(is_multibeat, UInt<3>("h7"), UInt<1>("h0")) - wire T_878 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_878 is invalid - T_878.id <= io.tl.acquire.bits.client_xact_id - T_878.addr <= T_861 - T_878.len <= T_865 - T_878.size <= UInt<2>("h3") - T_878.burst <= UInt<2>("h1") - T_878.lock <= UInt<1>("h0") - T_878.cache <= UInt<4>("h0") - T_878.prot <= UInt<3>("h0") - T_878.qos <= UInt<4>("h0") - T_878.region <= UInt<4>("h0") - T_878.user <= UInt<1>("h0") - io.nasti.aw.bits <- T_878 - node T_896 = and(put_valid, aw_ready) - io.nasti.w.valid <= T_896 - node T_899 = eq(io.tl.acquire.bits.a_type, UInt<3>("h4")) - node T_900 = and(io.tl.acquire.bits.is_builtin_type, T_899) - wire T_903 : UInt<1>[1] - T_903[0] <= UInt<1>("h1") - node T_907 = sub(UInt<8>("h0"), T_903[0]) - node T_908 = tail(T_907, 1) - wire T_910 : UInt<8>[1] - T_910[0] <= T_908 - node T_914 = eq(io.tl.acquire.bits.a_type, UInt<3>("h3")) - node T_915 = and(io.tl.acquire.bits.is_builtin_type, T_914) - node T_917 = eq(io.tl.acquire.bits.a_type, UInt<3>("h2")) - node T_918 = and(io.tl.acquire.bits.is_builtin_type, T_917) - node T_919 = or(T_915, T_918) - node T_920 = bits(io.tl.acquire.bits.union, 8, 1) - node T_922 = mux(T_919, T_920, UInt<8>("h0")) - node T_923 = mux(T_900, T_910[0], T_922) - node T_924 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_925 = and(T_924, is_subblock) - node T_926 = or(tl_wrap_out, T_925) - wire T_932 : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_932 is invalid - node T_938 = cat(UInt<1>("h1"), UInt<1>("h1")) - node T_939 = cat(T_938, T_938) - node T_940 = cat(T_939, T_939) - T_932.strb <= T_940 - T_932.data <= io.tl.acquire.bits.data - T_932.last <= T_926 - T_932.user <= UInt<1>("h0") - T_932.strb <= T_923 - io.nasti.w.bits <- T_932 - node T_942 = and(aw_ready, io.nasti.w.ready) - node T_943 = and(roq.io.enq.ready, io.nasti.ar.ready) - node T_944 = mux(has_data, T_942, T_943) - io.tl.acquire.ready <= T_944 - node T_946 = eq(w_inflight, UInt<1>("h0")) - node T_947 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_948 = and(T_946, T_947) - node T_949 = and(T_948, is_multibeat) - when T_949 : - w_inflight <= UInt<1>("h1") - skip - when w_inflight : - when tl_wrap_out : - w_inflight <= UInt<1>("h0") - skip - skip - node T_952 = and(io.tl.grant.ready, io.tl.grant.valid) - wire T_956 : UInt<3>[1] - T_956[0] <= UInt<3>("h5") - node T_959 = eq(T_956[0], io.tl.grant.bits.g_type) - node T_961 = or(UInt<1>("h0"), T_959) - wire T_963 : UInt<1>[1] - T_963[0] <= UInt<1>("h0") - node T_966 = eq(T_963[0], io.tl.grant.bits.g_type) - node T_968 = or(UInt<1>("h0"), T_966) - node T_969 = mux(io.tl.grant.bits.is_builtin_type, T_961, T_968) - node T_970 = and(UInt<1>("h1"), T_969) - node T_971 = and(T_952, T_970) - reg tl_cnt_in : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - when T_971 : - node T_975 = eq(tl_cnt_in, UInt<3>("h7")) - node T_977 = and(UInt<1>("h0"), T_975) - node T_980 = add(tl_cnt_in, UInt<1>("h1")) - node T_981 = tail(T_980, 1) - node T_982 = mux(T_977, UInt<1>("h0"), T_981) - tl_cnt_in <= T_982 - skip - node tl_wrap_in = and(T_971, T_975) - inst gnt_arb of Arbiter - gnt_arb.io is invalid - gnt_arb.clk <= clk - gnt_arb.reset <= reset - io.tl.grant <- gnt_arb.io.out - node T_1014 = cat(roq.io.deq.data.byteOff, UInt<3>("h0")) - node T_1015 = dshl(io.nasti.r.bits.data, T_1014) - node r_aligned_data = mux(roq.io.deq.data.subblock, T_1015, io.nasti.r.bits.data) - gnt_arb.io.in[0].valid <= io.nasti.r.valid - io.nasti.r.ready <= gnt_arb.io.in[0].ready - node T_1020 = mux(roq.io.deq.data.subblock, UInt<3>("h4"), UInt<3>("h5")) - node T_1022 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) - wire T_1050 : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1050 is invalid - T_1050.is_builtin_type <= UInt<1>("h1") - T_1050.g_type <= T_1020 - T_1050.client_xact_id <= io.nasti.r.bits.id - T_1050.manager_xact_id <= UInt<1>("h0") - T_1050.addr_beat <= T_1022 - T_1050.data <= r_aligned_data - gnt_arb.io.in[0].bits <- T_1050 - gnt_arb.io.in[1].valid <= io.nasti.b.valid - io.nasti.b.ready <= gnt_arb.io.in[1].ready - wire T_1109 : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1109 is invalid - T_1109.is_builtin_type <= UInt<1>("h1") - T_1109.g_type <= UInt<3>("h3") - T_1109.client_xact_id <= io.nasti.b.bits.id - T_1109.manager_xact_id <= UInt<1>("h0") - T_1109.addr_beat <= UInt<1>("h0") - T_1109.data <= UInt<1>("h0") - gnt_arb.io.in[1].bits <- T_1109 - node T_1137 = eq(io.nasti.r.valid, UInt<1>("h0")) - node T_1139 = eq(io.nasti.r.bits.resp, UInt<1>("h0")) - node T_1140 = or(T_1137, T_1139) - node T_1142 = eq(reset, UInt<1>("h0")) - when T_1142 : - node T_1144 = eq(T_1140, UInt<1>("h0")) - when T_1144 : - node T_1146 = eq(reset, UInt<1>("h0")) - when T_1146 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): NASTI read error") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1148 = eq(io.nasti.b.valid, UInt<1>("h0")) - node T_1150 = eq(io.nasti.b.bits.resp, UInt<1>("h0")) - node T_1151 = or(T_1148, T_1150) - node T_1153 = eq(reset, UInt<1>("h0")) - when T_1153 : - node T_1155 = eq(T_1151, UInt<1>("h0")) - when T_1155 : - node T_1157 = eq(reset, UInt<1>("h0")) - when T_1157 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): NASTI write error") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - module ClientTileLinkIOWrapper_71 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io is invalid - io.out.acquire <- io.in.acquire - io.in.grant <- io.out.grant - io.out.probe.ready <= UInt<1>("h1") - io.out.release.valid <= UInt<1>("h0") - module ClientTileLinkEnqueuer : - input clk : Clock - input reset : UInt<1> - output io : {flip inner : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, outer : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io is invalid - io.outer.acquire <- io.inner.acquire - io.inner.probe <- io.outer.probe - io.outer.release <- io.inner.release - io.inner.grant <- io.outer.grant - module Queue_74 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, count : UInt<4>} - io is invalid - mem ram : - data-type => { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - depth => 8 - write-latency => 1 - read-latency => 0 - reader => T_117 - writer => T_83 - ram.T_117.addr is invalid - ram.T_117.clk <= clk - ram.T_117.en <= UInt<1>("h0") - ram.T_83.addr is invalid - ram.T_83.clk <= clk - ram.T_83.en <= UInt<1>("h0") - ram.T_83.data is invalid - ram.T_83.mask.data <= UInt<1>("h0") - ram.T_83.mask.last <= UInt<1>("h0") - ram.T_83.mask.strb <= UInt<1>("h0") - ram.T_83.mask.user <= UInt<1>("h0") - reg T_62 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg T_64 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_62, T_64) - node T_69 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_69) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_75 = and(io.enq.ready, io.enq.valid) - node T_77 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_75, T_77) - node T_79 = and(io.deq.ready, io.deq.valid) - node T_81 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_79, T_81) - when do_enq : - ram.T_83.addr <= T_62 - ram.T_83.en <= UInt<1>("h1") - ram.T_83.data <- io.enq.bits - ram.T_83.mask.data <= UInt<1>("h1") - ram.T_83.mask.last <= UInt<1>("h1") - ram.T_83.mask.strb <= UInt<1>("h1") - ram.T_83.mask.user <= UInt<1>("h1") - node T_89 = eq(T_62, UInt<3>("h7")) - node T_91 = and(UInt<1>("h0"), T_89) - node T_94 = add(T_62, UInt<1>("h1")) - node T_95 = tail(T_94, 1) - node T_96 = mux(T_91, UInt<1>("h0"), T_95) - T_62 <= T_96 - skip - when do_deq : - node T_98 = eq(T_64, UInt<3>("h7")) - node T_100 = and(UInt<1>("h0"), T_98) - node T_103 = add(T_64, UInt<1>("h1")) - node T_104 = tail(T_103, 1) - node T_105 = mux(T_100, UInt<1>("h0"), T_104) - T_64 <= T_105 - skip - node T_106 = neq(do_enq, do_deq) - when T_106 : - maybe_full <= do_enq - skip - node T_108 = eq(empty, UInt<1>("h0")) - node T_110 = and(UInt<1>("h0"), io.enq.valid) - node T_111 = or(T_108, T_110) - io.deq.valid <= T_111 - node T_113 = eq(full, UInt<1>("h0")) - node T_115 = and(UInt<1>("h0"), io.deq.ready) - node T_116 = or(T_113, T_115) - io.enq.ready <= T_116 - ram.T_117.addr <= T_64 - ram.T_117.en <= UInt<1>("h1") - node T_122 = mux(maybe_flow, io.enq.bits, ram.T_117.data) - io.deq.bits <- T_122 - node T_127 = sub(T_62, T_64) - node ptr_diff = tail(T_127, 1) - node T_129 = and(maybe_full, ptr_match) - node T_130 = cat(T_129, ptr_diff) - io.count <= T_130 - module Queue_75 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<4>} - io is invalid - mem ram : - data-type => { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - depth => 8 - write-latency => 1 - read-latency => 0 - reader => T_127 - writer => T_92 - ram.T_127.addr is invalid - ram.T_127.clk <= clk - ram.T_127.en <= UInt<1>("h0") - ram.T_92.addr is invalid - ram.T_92.clk <= clk - ram.T_92.en <= UInt<1>("h0") - ram.T_92.data is invalid - ram.T_92.mask.resp <= UInt<1>("h0") - ram.T_92.mask.data <= UInt<1>("h0") - ram.T_92.mask.last <= UInt<1>("h0") - ram.T_92.mask.id <= UInt<1>("h0") - ram.T_92.mask.user <= UInt<1>("h0") - reg T_71 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg T_73 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_71, T_73) - node T_78 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_78) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_84 = and(io.enq.ready, io.enq.valid) - node T_86 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_84, T_86) - node T_88 = and(io.deq.ready, io.deq.valid) - node T_90 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_88, T_90) - when do_enq : - ram.T_92.addr <= T_71 - ram.T_92.en <= UInt<1>("h1") - ram.T_92.data <- io.enq.bits - ram.T_92.mask.resp <= UInt<1>("h1") - ram.T_92.mask.data <= UInt<1>("h1") - ram.T_92.mask.last <= UInt<1>("h1") - ram.T_92.mask.id <= UInt<1>("h1") - ram.T_92.mask.user <= UInt<1>("h1") - node T_99 = eq(T_71, UInt<3>("h7")) - node T_101 = and(UInt<1>("h0"), T_99) - node T_104 = add(T_71, UInt<1>("h1")) - node T_105 = tail(T_104, 1) - node T_106 = mux(T_101, UInt<1>("h0"), T_105) - T_71 <= T_106 - skip - when do_deq : - node T_108 = eq(T_73, UInt<3>("h7")) - node T_110 = and(UInt<1>("h0"), T_108) - node T_113 = add(T_73, UInt<1>("h1")) - node T_114 = tail(T_113, 1) - node T_115 = mux(T_110, UInt<1>("h0"), T_114) - T_73 <= T_115 - skip - node T_116 = neq(do_enq, do_deq) - when T_116 : - maybe_full <= do_enq - skip - node T_118 = eq(empty, UInt<1>("h0")) - node T_120 = and(UInt<1>("h0"), io.enq.valid) - node T_121 = or(T_118, T_120) - io.deq.valid <= T_121 - node T_123 = eq(full, UInt<1>("h0")) - node T_125 = and(UInt<1>("h0"), io.deq.ready) - node T_126 = or(T_123, T_125) - io.enq.ready <= T_126 - ram.T_127.addr <= T_73 - ram.T_127.en <= UInt<1>("h1") - node T_133 = mux(maybe_flow, io.enq.bits, ram.T_127.data) - io.deq.bits <- T_133 - node T_139 = sub(T_71, T_73) - node ptr_diff = tail(T_139, 1) - node T_141 = and(maybe_full, ptr_match) - node T_142 = cat(T_141, ptr_diff) - io.count <= T_142 - module Queue_76 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { resp : UInt<2>, id : UInt<5>, user : UInt<1>} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_107 - writer => T_74 - ram.T_107.addr is invalid - ram.T_107.clk <= clk - ram.T_107.en <= UInt<1>("h0") - ram.T_74.addr is invalid - ram.T_74.clk <= clk - ram.T_74.en <= UInt<1>("h0") - ram.T_74.data is invalid - ram.T_74.mask.resp <= UInt<1>("h0") - ram.T_74.mask.id <= UInt<1>("h0") - ram.T_74.mask.user <= UInt<1>("h0") - reg T_53 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_55 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_53, T_55) - node T_60 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_60) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_66 = and(io.enq.ready, io.enq.valid) - node T_68 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_66, T_68) - node T_70 = and(io.deq.ready, io.deq.valid) - node T_72 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_70, T_72) - when do_enq : - ram.T_74.addr <= T_53 - ram.T_74.en <= UInt<1>("h1") - ram.T_74.data <- io.enq.bits - ram.T_74.mask.resp <= UInt<1>("h1") - ram.T_74.mask.id <= UInt<1>("h1") - ram.T_74.mask.user <= UInt<1>("h1") - node T_79 = eq(T_53, UInt<1>("h1")) - node T_81 = and(UInt<1>("h0"), T_79) - node T_84 = add(T_53, UInt<1>("h1")) - node T_85 = tail(T_84, 1) - node T_86 = mux(T_81, UInt<1>("h0"), T_85) - T_53 <= T_86 - skip - when do_deq : - node T_88 = eq(T_55, UInt<1>("h1")) - node T_90 = and(UInt<1>("h0"), T_88) - node T_93 = add(T_55, UInt<1>("h1")) - node T_94 = tail(T_93, 1) - node T_95 = mux(T_90, UInt<1>("h0"), T_94) - T_55 <= T_95 - skip - node T_96 = neq(do_enq, do_deq) - when T_96 : - maybe_full <= do_enq - skip - node T_98 = eq(empty, UInt<1>("h0")) - node T_100 = and(UInt<1>("h0"), io.enq.valid) - node T_101 = or(T_98, T_100) - io.deq.valid <= T_101 - node T_103 = eq(full, UInt<1>("h0")) - node T_105 = and(UInt<1>("h0"), io.deq.ready) - node T_106 = or(T_103, T_105) - io.enq.ready <= T_106 - ram.T_107.addr <= T_55 - ram.T_107.en <= UInt<1>("h1") - node T_111 = mux(maybe_flow, io.enq.bits, ram.T_107.data) - io.deq.bits <- T_111 - node T_115 = sub(T_53, T_55) - node ptr_diff = tail(T_115, 1) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - io.count <= T_118 - module RTC : - input clk : Clock - input reset : UInt<1> - output io : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - wire addrTable : UInt<31>[1] - addrTable[0] <= UInt<31>("h4000b808") - reg rtc : UInt<64>, clk with : - reset => (reset, UInt<64>("h0")) - reg T_217 : UInt<7>, clk with : - reset => (reset, UInt<7>("h0")) - node rtc_tick = eq(T_217, UInt<7>("h63")) - node T_221 = and(UInt<1>("h1"), rtc_tick) - node T_224 = add(T_217, UInt<1>("h1")) - node T_225 = tail(T_224, 1) - node T_226 = mux(T_221, UInt<1>("h0"), T_225) - T_217 <= T_226 - reg sending_addr : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sending_data : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_233 : UInt<1>[1] - T_233[0] <= UInt<1>("h1") - reg send_acked : UInt<1>[1], clk with : - reset => (reset, T_233) - wire coreId : UInt<1> - coreId is invalid - when rtc_tick : - node T_244 = add(rtc, UInt<1>("h1")) - node T_245 = tail(T_244, 1) - rtc <= T_245 - wire T_248 : UInt<1>[1] - T_248[0] <= UInt<1>("h0") - send_acked <= T_248 - sending_addr <= UInt<1>("h1") - sending_data <= UInt<1>("h1") - skip - node T_253 = and(io.aw.ready, io.aw.valid) - when T_253 : - sending_addr <= UInt<1>("h0") - skip - node T_255 = and(io.w.ready, io.w.valid) - when T_255 : - sending_addr <= UInt<1>("h0") - skip - coreId <= UInt<1>("h0") - node T_258 = and(io.b.ready, io.b.valid) - when T_258 : - send_acked[io.b.bits.id] <= UInt<1>("h1") - skip - io.aw.valid <= sending_addr - wire T_276 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_276 is invalid - T_276.id <= coreId - T_276.addr <= addrTable[coreId] - T_276.len <= UInt<1>("h0") - T_276.size <= UInt<2>("h3") - T_276.burst <= UInt<2>("h1") - T_276.lock <= UInt<1>("h0") - T_276.cache <= UInt<4>("h0") - T_276.prot <= UInt<3>("h0") - T_276.qos <= UInt<4>("h0") - T_276.region <= UInt<4>("h0") - T_276.user <= UInt<1>("h0") - io.aw.bits <- T_276 - io.w.valid <= sending_data - wire T_300 : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_300 is invalid - node T_306 = cat(UInt<1>("h1"), UInt<1>("h1")) - node T_307 = cat(T_306, T_306) - node T_308 = cat(T_307, T_307) - T_300.strb <= T_308 - T_300.data <= rtc - T_300.last <= UInt<1>("h1") - T_300.user <= UInt<1>("h0") - io.w.bits <- T_300 - io.b.ready <= UInt<1>("h1") - io.ar.valid <= UInt<1>("h0") - io.r.ready <= UInt<1>("h0") - node T_314 = eq(rtc_tick, UInt<1>("h0")) - node T_315 = or(T_314, send_acked[0]) - node T_317 = eq(reset, UInt<1>("h0")) - when T_317 : - node T_319 = eq(T_315, UInt<1>("h0")) - when T_319 : - node T_321 = eq(reset, UInt<1>("h0")) - when T_321 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - module SmiIONastiReadIOConverter : - input clk : Clock - input reset : UInt<1> - output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg nWords : UInt<1>, clk with : - reset => (UInt<1>("h0"), nWords) - reg nBeats : UInt<8>, clk with : - reset => (UInt<1>("h0"), nBeats) - reg addr : UInt<12>, clk with : - reset => (UInt<1>("h0"), addr) - reg id : UInt<5>, clk with : - reset => (UInt<1>("h0"), id) - reg byteOff : UInt<3>, clk with : - reset => (UInt<1>("h0"), byteOff) - reg sendInd : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg recvInd : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sendDone : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_141 : UInt<64>[1] - T_141[0] <= UInt<64>("h0") - reg buffer : UInt<64>[1], clk with : - reset => (reset, T_141) - node T_149 = eq(state, UInt<1>("h0")) - io.ar.ready <= T_149 - node T_150 = eq(state, UInt<1>("h1")) - node T_152 = eq(sendDone, UInt<1>("h0")) - node T_153 = and(T_150, T_152) - io.smi.req.valid <= T_153 - io.smi.req.bits.rw <= UInt<1>("h0") - io.smi.req.bits.addr <= addr - node T_155 = eq(state, UInt<1>("h1")) - io.smi.resp.ready <= T_155 - node T_156 = eq(state, UInt<2>("h2")) - io.r.valid <= T_156 - node T_158 = eq(nBeats, UInt<1>("h0")) - wire T_166 : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166 is invalid - T_166.id <= id - T_166.data <= buffer[0] - T_166.last <= T_158 - T_166.resp <= UInt<1>("h0") - T_166.user <= UInt<1>("h0") - io.r.bits <- T_166 - node T_173 = and(io.ar.ready, io.ar.valid) - when T_173 : - node T_175 = lt(io.ar.bits.size, UInt<2>("h3")) - when T_175 : - nWords <= UInt<1>("h0") - node T_177 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_177 - skip - node T_179 = eq(T_175, UInt<1>("h0")) - when T_179 : - node T_182 = sub(io.ar.bits.size, UInt<2>("h3")) - node T_183 = tail(T_182, 1) - node T_184 = dshl(UInt<1>("h1"), T_183) - node T_186 = sub(T_184, UInt<1>("h1")) - node T_187 = tail(T_186, 1) - nWords <= T_187 - byteOff <= UInt<1>("h0") - skip - nBeats <= io.ar.bits.len - node T_189 = bits(io.ar.bits.addr, 14, 3) - addr <= T_189 - id <= io.ar.bits.id - state <= UInt<1>("h1") - skip - node T_190 = and(io.smi.req.ready, io.smi.req.valid) - when T_190 : - node T_192 = add(addr, UInt<1>("h1")) - node T_193 = tail(T_192, 1) - addr <= T_193 - node T_195 = add(sendInd, UInt<1>("h1")) - node T_196 = tail(T_195, 1) - sendInd <= T_196 - node T_197 = eq(sendInd, nWords) - sendDone <= T_197 - skip - node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_198 : - node T_200 = add(recvInd, UInt<1>("h1")) - node T_201 = tail(T_200, 1) - recvInd <= T_201 - node T_204 = cat(byteOff, UInt<3>("h0")) - node T_205 = dshr(io.smi.resp.bits, T_204) - buffer[recvInd] <= T_205 - node T_206 = eq(recvInd, nWords) - when T_206 : - state <= UInt<2>("h2") - skip - skip - node T_207 = and(io.r.ready, io.r.valid) - when T_207 : - recvInd <= UInt<1>("h0") - sendInd <= UInt<1>("h0") - sendDone <= UInt<1>("h0") - buffer[0] <= UInt<1>("h0") - node T_213 = sub(nBeats, UInt<1>("h1")) - node T_214 = tail(T_213, 1) - nBeats <= T_214 - node T_215 = mux(io.r.bits.last, UInt<1>("h0"), UInt<1>("h1")) - state <= T_215 - skip - module SmiIONastiWriteIOConverter : - input clk : Clock - input reset : UInt<1> - output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - node T_144 = eq(io.aw.valid, UInt<1>("h0")) - node T_146 = geq(io.aw.bits.size, UInt<2>("h3")) - node T_147 = or(T_144, T_146) - node T_149 = eq(reset, UInt<1>("h0")) - when T_149 : - node T_151 = eq(T_147, UInt<1>("h0")) - when T_151 : - node T_153 = eq(reset, UInt<1>("h0")) - when T_153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg id : UInt<5>, clk with : - reset => (UInt<1>("h0"), id) - reg addr : UInt<12>, clk with : - reset => (UInt<1>("h0"), addr) - reg size : UInt<3>, clk with : - reset => (UInt<1>("h0"), size) - reg strb : UInt<1>, clk with : - reset => (UInt<1>("h0"), strb) - reg data : UInt<64>, clk with : - reset => (UInt<1>("h0"), data) - reg last : UInt<1>, clk with : - reset => (UInt<1>("h0"), last) - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - node T_173 = eq(state, UInt<1>("h0")) - io.aw.ready <= T_173 - node T_174 = eq(state, UInt<1>("h1")) - io.w.ready <= T_174 - node T_175 = eq(state, UInt<2>("h2")) - node T_176 = bits(strb, 0, 0) - node T_177 = and(T_175, T_176) - io.smi.req.valid <= T_177 - io.smi.req.bits.rw <= UInt<1>("h1") - io.smi.req.bits.addr <= addr - node T_179 = bits(data, 63, 0) - io.smi.req.bits.data <= T_179 - node T_180 = eq(state, UInt<2>("h3")) - io.smi.resp.ready <= T_180 - node T_181 = eq(state, UInt<3>("h4")) - io.b.valid <= T_181 - wire T_187 : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187 is invalid - T_187.id <= id - T_187.resp <= UInt<1>("h0") - T_187.user <= UInt<1>("h0") - io.b.bits <- T_187 - node T_193 = and(io.aw.ready, io.aw.valid) - when T_193 : - node T_194 = bits(io.aw.bits.addr, 14, 3) - addr <= T_194 - id <= io.aw.bits.id - size <= io.aw.bits.size - last <= UInt<1>("h0") - state <= UInt<1>("h1") - skip - node T_196 = and(io.w.ready, io.w.valid) - when T_196 : - last <= io.w.bits.last - node T_199 = dshl(UInt<1>("h1"), size) - node T_200 = dshl(UInt<1>("h1"), T_199) - node T_202 = sub(T_200, UInt<1>("h1")) - node T_203 = tail(T_202, 1) - node T_204 = and(T_203, io.w.bits.strb) - node T_205 = bits(T_204, 0, 0) - wire T_207 : UInt<1>[1] - T_207[0] <= T_205 - strb <= T_207[0] - data <= io.w.bits.data - state <= UInt<2>("h2") - skip - node T_210 = eq(state, UInt<2>("h2")) - when T_210 : - node T_212 = eq(strb, UInt<1>("h0")) - when T_212 : - node T_213 = mux(last, UInt<2>("h3"), UInt<1>("h1")) - state <= T_213 - skip - node T_214 = bits(strb, 0, 0) - node T_216 = eq(T_214, UInt<1>("h0")) - node T_217 = or(io.smi.req.ready, T_216) - node T_219 = eq(T_212, UInt<1>("h0")) - node T_220 = and(T_219, T_217) - when T_220 : - node T_221 = dshr(strb, UInt<1>("h1")) - strb <= T_221 - node T_223 = cat(UInt<1>("h1"), UInt<6>("h0")) - node T_224 = dshr(data, T_223) - data <= T_224 - node T_225 = add(addr, UInt<1>("h1")) - node T_226 = tail(T_225, 1) - addr <= T_226 - skip - skip - node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_227 : - state <= UInt<3>("h4") - skip - node T_228 = and(io.b.ready, io.b.valid) - when T_228 : - state <= UInt<1>("h0") - skip - module RRArbiter_77 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>} - io is invalid - wire T_130 : UInt<1> - T_130 is invalid - io.out.valid <= io.in[T_130].valid - io.out.bits <- io.in[T_130].bits - io.chosen <= T_130 - io.in[T_130].ready <= UInt<1>("h0") - reg T_167 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_168 = gt(UInt<1>("h0"), T_167) - node T_169 = and(io.in[0].valid, T_168) - node T_171 = gt(UInt<1>("h1"), T_167) - node T_172 = and(io.in[1].valid, T_171) - node T_175 = or(UInt<1>("h0"), T_169) - node T_177 = eq(T_175, UInt<1>("h0")) - node T_179 = or(UInt<1>("h0"), T_169) - node T_180 = or(T_179, T_172) - node T_182 = eq(T_180, UInt<1>("h0")) - node T_184 = or(UInt<1>("h0"), T_169) - node T_185 = or(T_184, T_172) - node T_186 = or(T_185, io.in[0].valid) - node T_188 = eq(T_186, UInt<1>("h0")) - node T_190 = gt(UInt<1>("h0"), T_167) - node T_191 = and(UInt<1>("h1"), T_190) - node T_192 = or(T_191, T_182) - node T_194 = gt(UInt<1>("h1"), T_167) - node T_195 = and(T_177, T_194) - node T_196 = or(T_195, T_188) - node T_198 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_199 = mux(UInt<1>("h0"), T_198, T_192) - node T_200 = and(T_199, io.out.ready) - io.in[0].ready <= T_200 - node T_202 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_203 = mux(UInt<1>("h0"), T_202, T_196) - node T_204 = and(T_203, io.out.ready) - io.in[1].ready <= T_204 - node T_207 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_209 = gt(UInt<1>("h1"), T_167) - node T_210 = and(io.in[1].valid, T_209) - node T_212 = mux(T_210, UInt<1>("h1"), T_207) - node T_213 = mux(UInt<1>("h0"), UInt<1>("h1"), T_212) - T_130 <= T_213 - node T_214 = and(io.out.ready, io.out.valid) - when T_214 : - T_167 <= T_130 - skip - module SmiArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - reg wait_resp : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg choice : UInt<1>, clk with : - reset => (UInt<1>("h0"), choice) - inst req_arb of RRArbiter_77 - req_arb.io is invalid - req_arb.clk <= clk - req_arb.reset <= reset - req_arb.io.in[0] <- io.in[0].req - req_arb.io.in[1] <- io.in[1].req - node T_313 = eq(wait_resp, UInt<1>("h0")) - node T_314 = and(io.out.req.ready, T_313) - req_arb.io.out.ready <= T_314 - io.out.req.bits <- req_arb.io.out.bits - node T_316 = eq(wait_resp, UInt<1>("h0")) - node T_317 = and(req_arb.io.out.valid, T_316) - io.out.req.valid <= T_317 - node T_318 = and(io.out.req.ready, io.out.req.valid) - when T_318 : - choice <= req_arb.io.chosen - wait_resp <= UInt<1>("h1") - skip - node T_320 = and(io.out.resp.ready, io.out.resp.valid) - when T_320 : - wait_resp <= UInt<1>("h0") - skip - io.in[0].resp.bits <= io.out.resp.bits - node T_323 = eq(choice, UInt<1>("h0")) - node T_324 = and(io.out.resp.valid, T_323) - io.in[0].resp.valid <= T_324 - io.in[1].resp.bits <= io.out.resp.bits - node T_326 = eq(choice, UInt<1>("h1")) - node T_327 = and(io.out.resp.valid, T_326) - io.in[1].resp.valid <= T_327 - io.out.resp.ready <= io.in[choice].resp.ready - module SmiIONastiIOConverter : - input clk : Clock - input reset : UInt<1> - output io : {flip nasti : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - inst reader of SmiIONastiReadIOConverter - reader.io is invalid - reader.clk <= clk - reader.reset <= reset - reader.io.ar <- io.nasti.ar - io.nasti.r <- reader.io.r - inst writer of SmiIONastiWriteIOConverter - writer.io is invalid - writer.clk <= clk - writer.reset <= reset - writer.io.aw <- io.nasti.aw - writer.io.w <- io.nasti.w - io.nasti.b <- writer.io.b - inst arb of SmiArbiter - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- reader.io.smi - arb.io.in[1] <- writer.io.smi - io.smi <- arb.io.out - module SmiIONastiReadIOConverter_79 : - input clk : Clock - input reset : UInt<1> - output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg nWords : UInt<1>, clk with : - reset => (UInt<1>("h0"), nWords) - reg nBeats : UInt<8>, clk with : - reset => (UInt<1>("h0"), nBeats) - reg addr : UInt<6>, clk with : - reset => (UInt<1>("h0"), addr) - reg id : UInt<5>, clk with : - reset => (UInt<1>("h0"), id) - reg byteOff : UInt<3>, clk with : - reset => (UInt<1>("h0"), byteOff) - reg sendInd : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg recvInd : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sendDone : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire T_141 : UInt<64>[1] - T_141[0] <= UInt<64>("h0") - reg buffer : UInt<64>[1], clk with : - reset => (reset, T_141) - node T_149 = eq(state, UInt<1>("h0")) - io.ar.ready <= T_149 - node T_150 = eq(state, UInt<1>("h1")) - node T_152 = eq(sendDone, UInt<1>("h0")) - node T_153 = and(T_150, T_152) - io.smi.req.valid <= T_153 - io.smi.req.bits.rw <= UInt<1>("h0") - io.smi.req.bits.addr <= addr - node T_155 = eq(state, UInt<1>("h1")) - io.smi.resp.ready <= T_155 - node T_156 = eq(state, UInt<2>("h2")) - io.r.valid <= T_156 - node T_158 = eq(nBeats, UInt<1>("h0")) - wire T_166 : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166 is invalid - T_166.id <= id - T_166.data <= buffer[0] - T_166.last <= T_158 - T_166.resp <= UInt<1>("h0") - T_166.user <= UInt<1>("h0") - io.r.bits <- T_166 - node T_173 = and(io.ar.ready, io.ar.valid) - when T_173 : - node T_175 = lt(io.ar.bits.size, UInt<2>("h3")) - when T_175 : - nWords <= UInt<1>("h0") - node T_177 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_177 - skip - node T_179 = eq(T_175, UInt<1>("h0")) - when T_179 : - node T_182 = sub(io.ar.bits.size, UInt<2>("h3")) - node T_183 = tail(T_182, 1) - node T_184 = dshl(UInt<1>("h1"), T_183) - node T_186 = sub(T_184, UInt<1>("h1")) - node T_187 = tail(T_186, 1) - nWords <= T_187 - byteOff <= UInt<1>("h0") - skip - nBeats <= io.ar.bits.len - node T_189 = bits(io.ar.bits.addr, 8, 3) - addr <= T_189 - id <= io.ar.bits.id - state <= UInt<1>("h1") - skip - node T_190 = and(io.smi.req.ready, io.smi.req.valid) - when T_190 : - node T_192 = add(addr, UInt<1>("h1")) - node T_193 = tail(T_192, 1) - addr <= T_193 - node T_195 = add(sendInd, UInt<1>("h1")) - node T_196 = tail(T_195, 1) - sendInd <= T_196 - node T_197 = eq(sendInd, nWords) - sendDone <= T_197 - skip - node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_198 : - node T_200 = add(recvInd, UInt<1>("h1")) - node T_201 = tail(T_200, 1) - recvInd <= T_201 - node T_204 = cat(byteOff, UInt<3>("h0")) - node T_205 = dshr(io.smi.resp.bits, T_204) - buffer[recvInd] <= T_205 - node T_206 = eq(recvInd, nWords) - when T_206 : - state <= UInt<2>("h2") - skip - skip - node T_207 = and(io.r.ready, io.r.valid) - when T_207 : - recvInd <= UInt<1>("h0") - sendInd <= UInt<1>("h0") - sendDone <= UInt<1>("h0") - buffer[0] <= UInt<1>("h0") - node T_213 = sub(nBeats, UInt<1>("h1")) - node T_214 = tail(T_213, 1) - nBeats <= T_214 - node T_215 = mux(io.r.bits.last, UInt<1>("h0"), UInt<1>("h1")) - state <= T_215 - skip - module SmiIONastiWriteIOConverter_80 : - input clk : Clock - input reset : UInt<1> - output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - node T_144 = eq(io.aw.valid, UInt<1>("h0")) - node T_146 = geq(io.aw.bits.size, UInt<2>("h3")) - node T_147 = or(T_144, T_146) - node T_149 = eq(reset, UInt<1>("h0")) - when T_149 : - node T_151 = eq(T_147, UInt<1>("h0")) - when T_151 : - node T_153 = eq(reset, UInt<1>("h0")) - when T_153 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg id : UInt<5>, clk with : - reset => (UInt<1>("h0"), id) - reg addr : UInt<6>, clk with : - reset => (UInt<1>("h0"), addr) - reg size : UInt<3>, clk with : - reset => (UInt<1>("h0"), size) - reg strb : UInt<1>, clk with : - reset => (UInt<1>("h0"), strb) - reg data : UInt<64>, clk with : - reset => (UInt<1>("h0"), data) - reg last : UInt<1>, clk with : - reset => (UInt<1>("h0"), last) - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - node T_173 = eq(state, UInt<1>("h0")) - io.aw.ready <= T_173 - node T_174 = eq(state, UInt<1>("h1")) - io.w.ready <= T_174 - node T_175 = eq(state, UInt<2>("h2")) - node T_176 = bits(strb, 0, 0) - node T_177 = and(T_175, T_176) - io.smi.req.valid <= T_177 - io.smi.req.bits.rw <= UInt<1>("h1") - io.smi.req.bits.addr <= addr - node T_179 = bits(data, 63, 0) - io.smi.req.bits.data <= T_179 - node T_180 = eq(state, UInt<2>("h3")) - io.smi.resp.ready <= T_180 - node T_181 = eq(state, UInt<3>("h4")) - io.b.valid <= T_181 - wire T_187 : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187 is invalid - T_187.id <= id - T_187.resp <= UInt<1>("h0") - T_187.user <= UInt<1>("h0") - io.b.bits <- T_187 - node T_193 = and(io.aw.ready, io.aw.valid) - when T_193 : - node T_194 = bits(io.aw.bits.addr, 8, 3) - addr <= T_194 - id <= io.aw.bits.id - size <= io.aw.bits.size - last <= UInt<1>("h0") - state <= UInt<1>("h1") - skip - node T_196 = and(io.w.ready, io.w.valid) - when T_196 : - last <= io.w.bits.last - node T_199 = dshl(UInt<1>("h1"), size) - node T_200 = dshl(UInt<1>("h1"), T_199) - node T_202 = sub(T_200, UInt<1>("h1")) - node T_203 = tail(T_202, 1) - node T_204 = and(T_203, io.w.bits.strb) - node T_205 = bits(T_204, 0, 0) - wire T_207 : UInt<1>[1] - T_207[0] <= T_205 - strb <= T_207[0] - data <= io.w.bits.data - state <= UInt<2>("h2") - skip - node T_210 = eq(state, UInt<2>("h2")) - when T_210 : - node T_212 = eq(strb, UInt<1>("h0")) - when T_212 : - node T_213 = mux(last, UInt<2>("h3"), UInt<1>("h1")) - state <= T_213 - skip - node T_214 = bits(strb, 0, 0) - node T_216 = eq(T_214, UInt<1>("h0")) - node T_217 = or(io.smi.req.ready, T_216) - node T_219 = eq(T_212, UInt<1>("h0")) - node T_220 = and(T_219, T_217) - when T_220 : - node T_221 = dshr(strb, UInt<1>("h1")) - strb <= T_221 - node T_223 = cat(UInt<1>("h1"), UInt<6>("h0")) - node T_224 = dshr(data, T_223) - data <= T_224 - node T_225 = add(addr, UInt<1>("h1")) - node T_226 = tail(T_225, 1) - addr <= T_226 - skip - skip - node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_227 : - state <= UInt<3>("h4") - skip - node T_228 = and(io.b.ready, io.b.valid) - when T_228 : - state <= UInt<1>("h0") - skip - module RRArbiter_82 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>} - io is invalid - wire T_130 : UInt<1> - T_130 is invalid - io.out.valid <= io.in[T_130].valid - io.out.bits <- io.in[T_130].bits - io.chosen <= T_130 - io.in[T_130].ready <= UInt<1>("h0") - reg T_167 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_168 = gt(UInt<1>("h0"), T_167) - node T_169 = and(io.in[0].valid, T_168) - node T_171 = gt(UInt<1>("h1"), T_167) - node T_172 = and(io.in[1].valid, T_171) - node T_175 = or(UInt<1>("h0"), T_169) - node T_177 = eq(T_175, UInt<1>("h0")) - node T_179 = or(UInt<1>("h0"), T_169) - node T_180 = or(T_179, T_172) - node T_182 = eq(T_180, UInt<1>("h0")) - node T_184 = or(UInt<1>("h0"), T_169) - node T_185 = or(T_184, T_172) - node T_186 = or(T_185, io.in[0].valid) - node T_188 = eq(T_186, UInt<1>("h0")) - node T_190 = gt(UInt<1>("h0"), T_167) - node T_191 = and(UInt<1>("h1"), T_190) - node T_192 = or(T_191, T_182) - node T_194 = gt(UInt<1>("h1"), T_167) - node T_195 = and(T_177, T_194) - node T_196 = or(T_195, T_188) - node T_198 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_199 = mux(UInt<1>("h0"), T_198, T_192) - node T_200 = and(T_199, io.out.ready) - io.in[0].ready <= T_200 - node T_202 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_203 = mux(UInt<1>("h0"), T_202, T_196) - node T_204 = and(T_203, io.out.ready) - io.in[1].ready <= T_204 - node T_207 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_209 = gt(UInt<1>("h1"), T_167) - node T_210 = and(io.in[1].valid, T_209) - node T_212 = mux(T_210, UInt<1>("h1"), T_207) - node T_213 = mux(UInt<1>("h0"), UInt<1>("h1"), T_212) - T_130 <= T_213 - node T_214 = and(io.out.ready, io.out.valid) - when T_214 : - T_167 <= T_130 - skip - module SmiArbiter_81 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - reg wait_resp : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg choice : UInt<1>, clk with : - reset => (UInt<1>("h0"), choice) - inst req_arb of RRArbiter_82 - req_arb.io is invalid - req_arb.clk <= clk - req_arb.reset <= reset - req_arb.io.in[0] <- io.in[0].req - req_arb.io.in[1] <- io.in[1].req - node T_313 = eq(wait_resp, UInt<1>("h0")) - node T_314 = and(io.out.req.ready, T_313) - req_arb.io.out.ready <= T_314 - io.out.req.bits <- req_arb.io.out.bits - node T_316 = eq(wait_resp, UInt<1>("h0")) - node T_317 = and(req_arb.io.out.valid, T_316) - io.out.req.valid <= T_317 - node T_318 = and(io.out.req.ready, io.out.req.valid) - when T_318 : - choice <= req_arb.io.chosen - wait_resp <= UInt<1>("h1") - skip - node T_320 = and(io.out.resp.ready, io.out.resp.valid) - when T_320 : - wait_resp <= UInt<1>("h0") - skip - io.in[0].resp.bits <= io.out.resp.bits - node T_323 = eq(choice, UInt<1>("h0")) - node T_324 = and(io.out.resp.valid, T_323) - io.in[0].resp.valid <= T_324 - io.in[1].resp.bits <= io.out.resp.bits - node T_326 = eq(choice, UInt<1>("h1")) - node T_327 = and(io.out.resp.valid, T_326) - io.in[1].resp.valid <= T_327 - io.out.resp.ready <= io.in[choice].resp.ready - module SmiIONastiIOConverter_78 : - input clk : Clock - input reset : UInt<1> - output io : {flip nasti : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io is invalid - inst reader of SmiIONastiReadIOConverter_79 - reader.io is invalid - reader.clk <= clk - reader.reset <= reset - reader.io.ar <- io.nasti.ar - io.nasti.r <- reader.io.r - inst writer of SmiIONastiWriteIOConverter_80 - writer.io is invalid - writer.clk <= clk - writer.reset <= reset - writer.io.aw <- io.nasti.aw - writer.io.w <- io.nasti.w - io.nasti.b <- writer.io.b - inst arb of SmiArbiter_81 - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- reader.io.smi - arb.io.in[1] <- writer.io.smi - io.smi <- arb.io.out - module NastiArbiter_83 : - input clk : Clock - input reset : UInt<1> - output io : {flip master : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slave : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io is invalid - io.slave <- io.master[0] - module MemIONastiIOConverter : - input clk : Clock - input reset : UInt<1> - output io : {flip nasti : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, mem : { req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}}} - io is invalid - node T_368 = and(io.mem.resp.ready, io.mem.resp.valid) - reg mif_cnt_out : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - when T_368 : - node T_372 = eq(mif_cnt_out, UInt<3>("h7")) - node T_374 = and(UInt<1>("h0"), T_372) - node T_377 = add(mif_cnt_out, UInt<1>("h1")) - node T_378 = tail(T_377, 1) - node T_379 = mux(T_374, UInt<1>("h0"), T_378) - mif_cnt_out <= T_379 - skip - node mif_wrap_out = and(T_368, T_372) - node T_382 = eq(io.nasti.aw.valid, UInt<1>("h0")) - node T_384 = eq(io.nasti.aw.bits.size, UInt<2>("h3")) - node T_385 = or(T_382, T_384) - node T_387 = eq(reset, UInt<1>("h0")) - when T_387 : - node T_389 = eq(T_385, UInt<1>("h0")) - when T_389 : - node T_391 = eq(reset, UInt<1>("h0")) - when T_391 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_393 = eq(io.nasti.ar.valid, UInt<1>("h0")) - node T_395 = eq(io.nasti.ar.bits.size, UInt<2>("h3")) - node T_396 = or(T_393, T_395) - node T_398 = eq(reset, UInt<1>("h0")) - when T_398 : - node T_400 = eq(T_396, UInt<1>("h0")) - when T_400 : - node T_402 = eq(reset, UInt<1>("h0")) - when T_402 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_404 = eq(io.nasti.aw.valid, UInt<1>("h0")) - node T_406 = eq(io.nasti.aw.bits.len, UInt<3>("h7")) - node T_407 = or(T_404, T_406) - node T_409 = eq(reset, UInt<1>("h0")) - when T_409 : - node T_411 = eq(T_407, UInt<1>("h0")) - when T_411 : - node T_413 = eq(reset, UInt<1>("h0")) - when T_413 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_415 = eq(io.nasti.ar.valid, UInt<1>("h0")) - node T_417 = eq(io.nasti.ar.bits.len, UInt<3>("h7")) - node T_418 = or(T_415, T_417) - node T_420 = eq(reset, UInt<1>("h0")) - when T_420 : - node T_422 = eq(T_418, UInt<1>("h0")) - when T_422 : - node T_424 = eq(reset, UInt<1>("h0")) - when T_424 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - reg b_ok : UInt<1>, clk with : - reset => (reset, UInt<1>("h1")) - node T_427 = and(io.nasti.aw.ready, io.nasti.aw.valid) - when T_427 : - b_ok <= UInt<1>("h0") - skip - node T_429 = and(io.nasti.w.ready, io.nasti.w.valid) - node T_430 = and(T_429, io.nasti.w.bits.last) - when T_430 : - b_ok <= UInt<1>("h1") - skip - inst id_q of Queue_37 - id_q.io is invalid - id_q.clk <= clk - id_q.reset <= reset - node T_434 = and(io.nasti.aw.valid, io.mem.req_cmd.ready) - id_q.io.enq.valid <= T_434 - id_q.io.enq.bits <= io.nasti.aw.bits.id - node T_435 = and(io.nasti.b.ready, b_ok) - id_q.io.deq.ready <= T_435 - node T_436 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) - node T_438 = dshr(T_436, UInt<3>("h6")) - io.mem.req_cmd.bits.addr <= T_438 - node T_439 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) - io.mem.req_cmd.bits.tag <= T_439 - io.mem.req_cmd.bits.rw <= io.nasti.aw.valid - node T_440 = and(io.nasti.aw.valid, id_q.io.enq.ready) - node T_441 = or(T_440, io.nasti.ar.valid) - io.mem.req_cmd.valid <= T_441 - node T_443 = eq(io.nasti.aw.valid, UInt<1>("h0")) - node T_444 = and(io.mem.req_cmd.ready, T_443) - io.nasti.ar.ready <= T_444 - node T_445 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) - io.nasti.aw.ready <= T_445 - node T_446 = and(id_q.io.deq.valid, b_ok) - io.nasti.b.valid <= T_446 - io.nasti.b.bits.id <= id_q.io.deq.bits - io.nasti.b.bits.resp <= UInt<1>("h0") - io.nasti.w.ready <= io.mem.req_data.ready - io.mem.req_data.valid <= io.nasti.w.valid - io.mem.req_data.bits.data <= io.nasti.w.bits.data - node T_449 = eq(io.nasti.w.valid, UInt<1>("h0")) - node T_450 = not(io.nasti.w.bits.strb) - node T_452 = eq(T_450, UInt<1>("h0")) - node T_453 = or(T_449, T_452) - node T_455 = eq(reset, UInt<1>("h0")) - when T_455 : - node T_457 = eq(T_453, UInt<1>("h0")) - when T_457 : - node T_459 = eq(reset, UInt<1>("h0")) - when T_459 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): MemIO must write full cache line") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - io.nasti.r.valid <= io.mem.resp.valid - io.nasti.r.bits.data <= io.mem.resp.bits.data - io.nasti.r.bits.last <= mif_wrap_out - io.nasti.r.bits.id <= io.mem.resp.bits.tag - io.nasti.r.bits.resp <= UInt<1>("h0") - io.mem.resp.ready <= io.nasti.r.ready - module MemSerdes : - input clk : Clock - input reset : UInt<1> - output io : {flip wide : { req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}}, narrow : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : { valid : UInt<1>, bits : UInt<16>}}} - io is invalid - node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) - node T_113 = cat(io.wide.req_cmd.bits.addr, T_112) - reg out_buf : UInt, clk with : - reset => (UInt<1>("h0"), out_buf) - reg in_buf : UInt, clk with : - reset => (UInt<1>("h0"), in_buf) - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg send_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - reg data_send_cnt : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_130 = eq(send_cnt, UInt<1>("h1")) - node adone = and(io.narrow.req.ready, T_130) - node T_133 = eq(send_cnt, UInt<2>("h3")) - node ddone = and(io.narrow.req.ready, T_133) - node T_135 = and(io.narrow.req.valid, io.narrow.req.ready) - when T_135 : - node T_137 = add(send_cnt, UInt<1>("h1")) - node T_138 = tail(T_137, 1) - send_cnt <= T_138 - node T_140 = dshr(out_buf, UInt<5>("h10")) - out_buf <= T_140 - skip - node T_141 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) - when T_141 : - node T_142 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) - node T_143 = cat(io.wide.req_cmd.bits.addr, T_142) - out_buf <= T_143 - skip - node T_144 = and(io.wide.req_data.valid, io.wide.req_data.ready) - when T_144 : - out_buf <= io.wide.req_data.bits.data - skip - node T_145 = eq(state, UInt<1>("h0")) - io.wide.req_cmd.ready <= T_145 - node T_146 = eq(state, UInt<2>("h3")) - io.wide.req_data.ready <= T_146 - node T_147 = eq(state, UInt<1>("h1")) - node T_148 = eq(state, UInt<2>("h2")) - node T_149 = or(T_147, T_148) - node T_150 = eq(state, UInt<3>("h4")) - node T_151 = or(T_149, T_150) - io.narrow.req.valid <= T_151 - io.narrow.req.bits <= out_buf - node T_152 = eq(state, UInt<1>("h0")) - node T_153 = and(T_152, io.wide.req_cmd.valid) - when T_153 : - node T_154 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h2"), UInt<1>("h1")) - state <= T_154 - skip - node T_155 = eq(state, UInt<1>("h1")) - node T_156 = and(T_155, adone) - when T_156 : - state <= UInt<1>("h0") - send_cnt <= UInt<1>("h0") - skip - node T_158 = eq(state, UInt<2>("h2")) - node T_159 = and(T_158, adone) - when T_159 : - state <= UInt<2>("h3") - send_cnt <= UInt<1>("h0") - skip - node T_161 = eq(state, UInt<2>("h3")) - node T_162 = and(T_161, io.wide.req_data.valid) - when T_162 : - state <= UInt<3>("h4") - skip - node T_163 = eq(state, UInt<3>("h4")) - node T_164 = and(T_163, ddone) - when T_164 : - node T_166 = add(data_send_cnt, UInt<1>("h1")) - node T_167 = tail(T_166, 1) - data_send_cnt <= T_167 - node T_169 = eq(data_send_cnt, UInt<3>("h7")) - node T_170 = mux(T_169, UInt<1>("h0"), UInt<2>("h3")) - state <= T_170 - send_cnt <= UInt<1>("h0") - skip - reg recv_cnt : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg data_recv_cnt : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg resp_val : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - resp_val <= UInt<1>("h0") - when io.narrow.resp.valid : - node T_180 = add(recv_cnt, UInt<1>("h1")) - node T_181 = tail(T_180, 1) - recv_cnt <= T_181 - node T_183 = eq(recv_cnt, UInt<3>("h4")) - when T_183 : - recv_cnt <= UInt<1>("h0") - node T_186 = add(data_recv_cnt, UInt<1>("h1")) - node T_187 = tail(T_186, 1) - data_recv_cnt <= T_187 - resp_val <= UInt<1>("h1") - skip - node T_189 = bits(in_buf, 79, 16) - node T_190 = cat(io.narrow.resp.bits, T_189) - in_buf <= T_190 - skip - io.wide.resp.valid <= resp_val - wire T_194 : { data : UInt<64>, tag : UInt<5>} - T_194 is invalid - node T_197 = bits(in_buf, 4, 0) - T_194.tag <= T_197 - node T_198 = bits(in_buf, 68, 5) - T_194.data <= T_198 - io.wide.resp.bits <- T_194 - module OuterMemorySystem : - input clk : Clock - input reset : UInt<1> - output io : {flip tiles_cached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif_uncached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, flip incoherent : UInt<1>[1], mem : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_backup : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : { valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, deviceTree : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, status : UInt<2>}}}} - io is invalid - inst T_8064 of ClientTileLinkIOWrapper - T_8064.io is invalid - T_8064.clk <= clk - T_8064.reset <= reset - T_8064.io.in <- io.tiles_uncached[0] - inst T_8065 of ClientTileLinkIOWrapper - T_8065.io is invalid - T_8065.clk <= clk - T_8065.reset <= reset - T_8065.io.in <- io.htif_uncached - inst l1tol2net of RocketChipTileLinkArbiter - l1tol2net.io is invalid - l1tol2net.clk <= clk - l1tol2net.reset <= reset - inst T_8067 of L2BroadcastHub - T_8067.io is invalid - T_8067.clk <= clk - T_8067.reset <= reset - T_8067.io.incoherent <= io.incoherent - l1tol2net.io.clients[0] <- io.tiles_cached[0] - l1tol2net.io.clients[1] <- T_8064.io.out - l1tol2net.io.clients[2] <- T_8065.io.out - l1tol2net.io.managers[0] <- T_8067.io.inner - inst interconnect of NastiRecursiveInterconnect - interconnect.io is invalid - interconnect.clk <= clk - interconnect.reset <= reset - inst T_8069 of ClientTileLinkIOUnwrapper - T_8069.io is invalid - T_8069.clk <= clk - T_8069.reset <= reset - inst T_8070 of TileLinkIONarrower - T_8070.io is invalid - T_8070.clk <= clk - T_8070.reset <= reset - inst T_8071 of NastiIOTileLinkIOConverter - T_8071.io is invalid - T_8071.clk <= clk - T_8071.reset <= reset - inst T_8072 of ClientTileLinkIOWrapper_71 - T_8072.io is invalid - T_8072.clk <= clk - T_8072.reset <= reset - T_8072.io.in <- T_8067.io.outer - inst T_8073 of ClientTileLinkEnqueuer - T_8073.io is invalid - T_8073.clk <= clk - T_8073.reset <= reset - T_8073.io.inner <- T_8072.io.out - T_8069.io.in <- T_8073.io.outer - T_8070.io.in <- T_8069.io.out - T_8071.io.tl <- T_8070.io.out - inst T_8086 of Queue_36 - T_8086.io is invalid - T_8086.clk <= clk - T_8086.reset <= reset - T_8086.io.enq.valid <= T_8071.io.nasti.ar.valid - T_8086.io.enq.bits <- T_8071.io.nasti.ar.bits - T_8071.io.nasti.ar.ready <= T_8086.io.enq.ready - interconnect.io.masters[0].ar <- T_8086.io.deq - inst T_8099 of Queue_36 - T_8099.io is invalid - T_8099.clk <= clk - T_8099.reset <= reset - T_8099.io.enq.valid <= T_8071.io.nasti.aw.valid - T_8099.io.enq.bits <- T_8071.io.nasti.aw.bits - T_8071.io.nasti.aw.ready <= T_8099.io.enq.ready - interconnect.io.masters[0].aw <- T_8099.io.deq - inst T_8105 of Queue_74 - T_8105.io is invalid - T_8105.clk <= clk - T_8105.reset <= reset - T_8105.io.enq.valid <= T_8071.io.nasti.w.valid - T_8105.io.enq.bits <- T_8071.io.nasti.w.bits - T_8071.io.nasti.w.ready <= T_8105.io.enq.ready - interconnect.io.masters[0].w <- T_8105.io.deq - inst T_8112 of Queue_75 - T_8112.io is invalid - T_8112.clk <= clk - T_8112.reset <= reset - T_8112.io.enq.valid <= interconnect.io.masters[0].r.valid - T_8112.io.enq.bits <- interconnect.io.masters[0].r.bits - interconnect.io.masters[0].r.ready <= T_8112.io.enq.ready - T_8071.io.nasti.r <- T_8112.io.deq - inst T_8117 of Queue_76 - T_8117.io is invalid - T_8117.clk <= clk - T_8117.reset <= reset - T_8117.io.enq.valid <= interconnect.io.masters[0].b.valid - T_8117.io.enq.bits <- interconnect.io.masters[0].b.bits - interconnect.io.masters[0].b.ready <= T_8117.io.enq.ready - T_8071.io.nasti.b <- T_8117.io.deq - inst rtc of RTC - rtc.io is invalid - rtc.clk <= clk - rtc.reset <= reset - interconnect.io.masters[1] <- rtc.io - inst T_8119 of SmiIONastiIOConverter - T_8119.io is invalid - T_8119.clk <= clk - T_8119.reset <= reset - T_8119.io.nasti <- interconnect.io.slaves[2] - io.csr[0] <- T_8119.io.smi - inst src_conv of SmiIONastiIOConverter_78 - src_conv.io is invalid - src_conv.clk <= clk - src_conv.reset <= reset - src_conv.io.nasti <- interconnect.io.slaves[3] - io.scr <- src_conv.io.smi - io.mmio <- interconnect.io.slaves[4] - io.deviceTree <- interconnect.io.slaves[1] - inst T_8121 of NastiArbiter_83 - T_8121.io is invalid - T_8121.clk <= clk - T_8121.reset <= reset - inst T_8122 of MemIONastiIOConverter - T_8122.io is invalid - T_8122.clk <= clk - T_8122.reset <= reset - inst T_8123 of MemSerdes - T_8123.io is invalid - T_8123.clk <= clk - T_8123.reset <= reset - T_8122.io.nasti <- T_8121.io.slave - T_8123.io.wide <- T_8122.io.mem - io.mem_backup <- T_8123.io.narrow - node T_8124 = mux(io.mem_backup_en, T_8121.io.master[0].ar.ready, io.mem[0].ar.ready) - interconnect.io.slaves[0].ar.ready <= T_8124 - node T_8126 = eq(io.mem_backup_en, UInt<1>("h0")) - node T_8127 = and(interconnect.io.slaves[0].ar.valid, T_8126) - io.mem[0].ar.valid <= T_8127 - io.mem[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8128 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) - T_8121.io.master[0].ar.valid <= T_8128 - T_8121.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8129 = mux(io.mem_backup_en, T_8121.io.master[0].aw.ready, io.mem[0].aw.ready) - interconnect.io.slaves[0].aw.ready <= T_8129 - node T_8131 = eq(io.mem_backup_en, UInt<1>("h0")) - node T_8132 = and(interconnect.io.slaves[0].aw.valid, T_8131) - io.mem[0].aw.valid <= T_8132 - io.mem[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8133 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) - T_8121.io.master[0].aw.valid <= T_8133 - T_8121.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8134 = mux(io.mem_backup_en, T_8121.io.master[0].w.ready, io.mem[0].w.ready) - interconnect.io.slaves[0].w.ready <= T_8134 - node T_8136 = eq(io.mem_backup_en, UInt<1>("h0")) - node T_8137 = and(interconnect.io.slaves[0].w.valid, T_8136) - io.mem[0].w.valid <= T_8137 - io.mem[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8138 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) - T_8121.io.master[0].w.valid <= T_8138 - T_8121.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8139 = mux(io.mem_backup_en, T_8121.io.master[0].b.valid, io.mem[0].b.valid) - interconnect.io.slaves[0].b.valid <= T_8139 - node T_8140 = mux(io.mem_backup_en, T_8121.io.master[0].b.bits, io.mem[0].b.bits) - interconnect.io.slaves[0].b.bits <- T_8140 - node T_8145 = eq(io.mem_backup_en, UInt<1>("h0")) - node T_8146 = and(interconnect.io.slaves[0].b.ready, T_8145) - io.mem[0].b.ready <= T_8146 - node T_8147 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) - T_8121.io.master[0].b.ready <= T_8147 - node T_8148 = mux(io.mem_backup_en, T_8121.io.master[0].r.valid, io.mem[0].r.valid) - interconnect.io.slaves[0].r.valid <= T_8148 - node T_8149 = mux(io.mem_backup_en, T_8121.io.master[0].r.bits, io.mem[0].r.bits) - interconnect.io.slaves[0].r.bits <- T_8149 - node T_8156 = eq(io.mem_backup_en, UInt<1>("h0")) - node T_8157 = and(interconnect.io.slaves[0].r.ready, T_8156) - io.mem[0].r.ready <= T_8157 - node T_8158 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) - T_8121.io.master[0].r.ready <= T_8158 - module SCRFile : - input clk : Clock - input reset : UInt<1> - output io : {flip smi : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}} - io is invalid - wire scr_rdata : UInt<64>[64] - scr_rdata is invalid - scr_rdata[0] <= io.scr.rdata[0] - scr_rdata[1] <= io.scr.rdata[1] - scr_rdata[2] <= io.scr.rdata[2] - scr_rdata[3] <= io.scr.rdata[3] - scr_rdata[4] <= io.scr.rdata[4] - scr_rdata[5] <= io.scr.rdata[5] - scr_rdata[6] <= io.scr.rdata[6] - scr_rdata[7] <= io.scr.rdata[7] - scr_rdata[8] <= io.scr.rdata[8] - scr_rdata[9] <= io.scr.rdata[9] - scr_rdata[10] <= io.scr.rdata[10] - scr_rdata[11] <= io.scr.rdata[11] - scr_rdata[12] <= io.scr.rdata[12] - scr_rdata[13] <= io.scr.rdata[13] - scr_rdata[14] <= io.scr.rdata[14] - scr_rdata[15] <= io.scr.rdata[15] - scr_rdata[16] <= io.scr.rdata[16] - scr_rdata[17] <= io.scr.rdata[17] - scr_rdata[18] <= io.scr.rdata[18] - scr_rdata[19] <= io.scr.rdata[19] - scr_rdata[20] <= io.scr.rdata[20] - scr_rdata[21] <= io.scr.rdata[21] - scr_rdata[22] <= io.scr.rdata[22] - scr_rdata[23] <= io.scr.rdata[23] - scr_rdata[24] <= io.scr.rdata[24] - scr_rdata[25] <= io.scr.rdata[25] - scr_rdata[26] <= io.scr.rdata[26] - scr_rdata[27] <= io.scr.rdata[27] - scr_rdata[28] <= io.scr.rdata[28] - scr_rdata[29] <= io.scr.rdata[29] - scr_rdata[30] <= io.scr.rdata[30] - scr_rdata[31] <= io.scr.rdata[31] - scr_rdata[32] <= io.scr.rdata[32] - scr_rdata[33] <= io.scr.rdata[33] - scr_rdata[34] <= io.scr.rdata[34] - scr_rdata[35] <= io.scr.rdata[35] - scr_rdata[36] <= io.scr.rdata[36] - scr_rdata[37] <= io.scr.rdata[37] - scr_rdata[38] <= io.scr.rdata[38] - scr_rdata[39] <= io.scr.rdata[39] - scr_rdata[40] <= io.scr.rdata[40] - scr_rdata[41] <= io.scr.rdata[41] - scr_rdata[42] <= io.scr.rdata[42] - scr_rdata[43] <= io.scr.rdata[43] - scr_rdata[44] <= io.scr.rdata[44] - scr_rdata[45] <= io.scr.rdata[45] - scr_rdata[46] <= io.scr.rdata[46] - scr_rdata[47] <= io.scr.rdata[47] - scr_rdata[48] <= io.scr.rdata[48] - scr_rdata[49] <= io.scr.rdata[49] - scr_rdata[50] <= io.scr.rdata[50] - scr_rdata[51] <= io.scr.rdata[51] - scr_rdata[52] <= io.scr.rdata[52] - scr_rdata[53] <= io.scr.rdata[53] - scr_rdata[54] <= io.scr.rdata[54] - scr_rdata[55] <= io.scr.rdata[55] - scr_rdata[56] <= io.scr.rdata[56] - scr_rdata[57] <= io.scr.rdata[57] - scr_rdata[58] <= io.scr.rdata[58] - scr_rdata[59] <= io.scr.rdata[59] - scr_rdata[60] <= io.scr.rdata[60] - scr_rdata[61] <= io.scr.rdata[61] - scr_rdata[62] <= io.scr.rdata[62] - scr_rdata[63] <= io.scr.rdata[63] - scr_rdata[0] <= UInt<1>("h1") - scr_rdata[1] <= UInt<11>("h400") - reg read_addr : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - reg resp_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_365 = eq(resp_valid, UInt<1>("h0")) - io.smi.req.ready <= T_365 - io.smi.resp.valid <= resp_valid - io.smi.resp.bits <= scr_rdata[read_addr] - node T_367 = and(io.smi.req.ready, io.smi.req.valid) - node T_368 = and(T_367, io.smi.req.bits.rw) - io.scr.wen <= T_368 - io.scr.wdata <= io.smi.req.bits.data - io.scr.waddr <= io.smi.req.bits.addr - node T_369 = and(io.smi.req.ready, io.smi.req.valid) - when T_369 : - read_addr <= io.smi.req.bits.addr - resp_valid <= UInt<1>("h1") - skip - node T_371 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_371 : - resp_valid <= UInt<1>("h0") - skip - module Queue_89 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} - io is invalid - mem ram : - data-type => { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - depth => 1 - write-latency => 1 - read-latency => 0 - reader => T_169 - writer => T_144 - ram.T_169.addr is invalid - ram.T_169.clk <= clk - ram.T_169.en <= UInt<1>("h0") - ram.T_144.addr is invalid - ram.T_144.clk <= clk - ram.T_144.en <= UInt<1>("h0") - ram.T_144.data is invalid - ram.T_144.mask.addr <= UInt<1>("h0") - ram.T_144.mask.len <= UInt<1>("h0") - ram.T_144.mask.size <= UInt<1>("h0") - ram.T_144.mask.burst <= UInt<1>("h0") - ram.T_144.mask.lock <= UInt<1>("h0") - ram.T_144.mask.cache <= UInt<1>("h0") - ram.T_144.mask.prot <= UInt<1>("h0") - ram.T_144.mask.qos <= UInt<1>("h0") - ram.T_144.mask.region <= UInt<1>("h0") - ram.T_144.mask.id <= UInt<1>("h0") - ram.T_144.mask.user <= UInt<1>("h0") - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_130 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_130) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_136 = and(io.enq.ready, io.enq.valid) - node T_138 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_136, T_138) - node T_140 = and(io.deq.ready, io.deq.valid) - node T_142 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_140, T_142) - when do_enq : - ram.T_144.addr <= UInt<1>("h0") - ram.T_144.en <= UInt<1>("h1") - ram.T_144.data <- io.enq.bits - ram.T_144.mask.addr <= UInt<1>("h1") - ram.T_144.mask.len <= UInt<1>("h1") - ram.T_144.mask.size <= UInt<1>("h1") - ram.T_144.mask.burst <= UInt<1>("h1") - ram.T_144.mask.lock <= UInt<1>("h1") - ram.T_144.mask.cache <= UInt<1>("h1") - ram.T_144.mask.prot <= UInt<1>("h1") - ram.T_144.mask.qos <= UInt<1>("h1") - ram.T_144.mask.region <= UInt<1>("h1") - ram.T_144.mask.id <= UInt<1>("h1") - ram.T_144.mask.user <= UInt<1>("h1") - skip - when do_deq : - skip - node T_158 = neq(do_enq, do_deq) - when T_158 : - maybe_full <= do_enq - skip - node T_160 = eq(empty, UInt<1>("h0")) - node T_162 = and(UInt<1>("h0"), io.enq.valid) - node T_163 = or(T_160, T_162) - io.deq.valid <= T_163 - node T_165 = eq(full, UInt<1>("h0")) - node T_167 = and(UInt<1>("h0"), io.deq.ready) - node T_168 = or(T_165, T_167) - io.enq.ready <= T_168 - ram.T_169.addr <= UInt<1>("h0") - ram.T_169.en <= UInt<1>("h1") - node T_181 = mux(maybe_flow, io.enq.bits, ram.T_169.data) - io.deq.bits <- T_181 - node T_193 = sub(UInt<1>("h0"), UInt<1>("h0")) - node ptr_diff = tail(T_193, 1) - node T_195 = and(maybe_full, ptr_match) - node T_196 = cat(T_195, ptr_diff) - io.count <= T_196 - module NastiROM : - input clk : Clock - input reset : UInt<1> - input io : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io is invalid - inst T_334 of Queue_89 - T_334.io is invalid - T_334.clk <= clk - T_334.reset <= reset - T_334.io.enq.valid <= io.ar.valid - T_334.io.enq.bits <- io.ar.bits - io.ar.ready <= T_334.io.enq.ready - when T_334.io.deq.valid : - node T_336 = eq(T_334.io.deq.bits.len, UInt<1>("h0")) - node T_338 = eq(reset, UInt<1>("h0")) - when T_338 : - node T_340 = eq(T_336, UInt<1>("h0")) - when T_340 : - node T_342 = eq(reset, UInt<1>("h0")) - when T_342 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - skip - node T_343 = or(io.aw.valid, io.w.valid) - node T_345 = eq(T_343, UInt<1>("h0")) - node T_347 = eq(reset, UInt<1>("h0")) - when T_347 : - node T_349 = eq(T_345, UInt<1>("h0")) - when T_349 : - node T_351 = eq(reset, UInt<1>("h0")) - when T_351 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): Can't write to NastiROM") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - io.aw.ready <= UInt<1>("h0") - io.w.ready <= UInt<1>("h0") - io.b.valid <= UInt<1>("h0") - wire rom : UInt<64>[67] - rom[0] <= UInt<60>("hb020000edfe0dd0") - rom[1] <= UInt<64>("hc001000038000000") - rom[2] <= UInt<61>("h1100000028000000") - rom[3] <= UInt<29>("h10000000") - rom[4] <= UInt<64>("h880100004b000000") - rom[5] <= UInt<1>("h0") - rom[6] <= UInt<1>("h0") - rom[7] <= UInt<25>("h1000000") - rom[8] <= UInt<59>("h400000003000000") - rom[9] <= UInt<58>("h200000000000000") - rom[10] <= UInt<59>("h400000003000000") - rom[11] <= UInt<58>("h20000000f000000") - rom[12] <= UInt<60>("hc00000003000000") - rom[13] <= UInt<63>("h6b636f521b000000") - rom[14] <= UInt<55>("h706968432d7465") - rom[15] <= UInt<63>("h6f6d656d01000000") - rom[16] <= UInt<30>("h30407972") - rom[17] <= UInt<59>("h700000003000000") - rom[18] <= UInt<63>("h6f6d656d21000000") - rom[19] <= UInt<58>("h300000000007972") - rom[20] <= UInt<62>("h2d00000010000000") - rom[21] <= UInt<1>("h0") - rom[22] <= UInt<39>("h4000000000") - rom[23] <= UInt<57>("h100000002000000") - rom[24] <= UInt<31>("h73757063") - rom[25] <= UInt<59>("h400000003000000") - rom[26] <= UInt<58>("h200000000000000") - rom[27] <= UInt<59>("h400000003000000") - rom[28] <= UInt<58>("h20000000f000000") - rom[29] <= UInt<63>("h4075706301000000") - rom[30] <= UInt<62>("h3030303830303034") - rom[31] <= UInt<58>("h300000000000000") - rom[32] <= UInt<62>("h2100000004000000") - rom[33] <= UInt<58>("h300000000757063") - rom[34] <= UInt<62>("h3100000006000000") - rom[35] <= UInt<39>("h7663736972") - rom[36] <= UInt<59>("h500000003000000") - rom[37] <= UInt<62>("h343676723c000000") - rom[38] <= UInt<58>("h300000000000000") - rom[39] <= UInt<62>("h2d00000008000000") - rom[40] <= UInt<56>("h80004000000000") - rom[41] <= UInt<58>("h200000002000000") - rom[42] <= UInt<63>("h4072637301000000") - rom[43] <= UInt<62>("h3030303031303034") - rom[44] <= UInt<58>("h300000000000000") - rom[45] <= UInt<62>("h2100000004000000") - rom[46] <= UInt<58>("h300000000726373") - rom[47] <= UInt<62>("h3100000006000000") - rom[48] <= UInt<39>("h7663736972") - rom[49] <= UInt<59>("h400000003000000") - rom[50] <= UInt<58>("h300000040000000") - rom[51] <= UInt<61>("h1000000003000000") - rom[52] <= UInt<30>("h2d000000") - rom[53] <= UInt<9>("h140") - rom[54] <= UInt<58>("h200000000020000") - rom[55] <= UInt<60>("h900000002000000") - rom[56] <= UInt<63>("h7373657264646123") - rom[57] <= UInt<62>("h2300736c6c65632d") - rom[58] <= UInt<63>("h6c65632d657a6973") - rom[59] <= UInt<63>("h6c65646f6d00736c") - rom[60] <= UInt<63>("h5f65636976656400") - rom[61] <= UInt<63>("h6765720065707974") - rom[62] <= UInt<63>("h697461706d6f6300") - rom[63] <= UInt<55>("h61736900656c62") - rom[64] <= UInt<63>("h69746365746f7270") - rom[65] <= UInt<15>("h6e6f") - rom[66] <= UInt<1>("h0") - node T_492 = bits(T_334.io.deq.bits.addr, 9, 3) - node T_495 = cat(UInt<1>("h1"), T_334.io.deq.bits.size) - node T_497 = bits(T_495, 1, 0) - node T_498 = asSInt(T_495) - node T_500 = geq(T_498, asSInt(UInt<1>("h0"))) - node T_501 = bits(T_334.io.deq.bits.addr, 2, 2) - node T_502 = bits(rom[T_492], 63, 32) - node T_503 = bits(rom[T_492], 31, 0) - node T_504 = mux(T_501, T_502, T_503) - node T_506 = and(UInt<1>("h0"), UInt<1>("h0")) - node T_508 = mux(T_506, UInt<1>("h0"), T_504) - node T_510 = eq(T_497, UInt<2>("h2")) - node T_511 = or(T_510, T_506) - node T_512 = bits(T_508, 31, 31) - node T_513 = and(T_500, T_512) - node T_515 = sub(UInt<32>("h0"), T_513) - node T_516 = tail(T_515, 1) - node T_517 = bits(rom[T_492], 63, 32) - node T_518 = mux(T_511, T_516, T_517) - node T_519 = cat(T_518, T_508) - node T_520 = bits(T_334.io.deq.bits.addr, 1, 1) - node T_521 = bits(T_519, 31, 16) - node T_522 = bits(T_519, 15, 0) - node T_523 = mux(T_520, T_521, T_522) - node T_525 = and(UInt<1>("h0"), UInt<1>("h0")) - node T_527 = mux(T_525, UInt<1>("h0"), T_523) - node T_529 = eq(T_497, UInt<1>("h1")) - node T_530 = or(T_529, T_525) - node T_531 = bits(T_527, 15, 15) - node T_532 = and(T_500, T_531) - node T_534 = sub(UInt<48>("h0"), T_532) - node T_535 = tail(T_534, 1) - node T_536 = bits(T_519, 63, 16) - node T_537 = mux(T_530, T_535, T_536) - node T_538 = cat(T_537, T_527) - node T_539 = bits(T_334.io.deq.bits.addr, 0, 0) - node T_540 = bits(T_538, 15, 8) - node T_541 = bits(T_538, 7, 0) - node T_542 = mux(T_539, T_540, T_541) - node T_544 = and(UInt<1>("h1"), UInt<1>("h0")) - node T_546 = mux(T_544, UInt<1>("h0"), T_542) - node T_548 = eq(T_497, UInt<1>("h0")) - node T_549 = or(T_548, T_544) - node T_550 = bits(T_546, 7, 7) - node T_551 = and(T_500, T_550) - node T_553 = sub(UInt<56>("h0"), T_551) - node T_554 = tail(T_553, 1) - node T_555 = bits(T_538, 63, 8) - node T_556 = mux(T_549, T_554, T_555) - node rdata = cat(T_556, T_546) - io.r <- T_334.io.deq - wire T_566 : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_566 is invalid - T_566.id <= T_334.io.deq.bits.id - T_566.data <= rdata - T_566.last <= UInt<1>("h1") - T_566.resp <= UInt<1>("h0") - T_566.user <= UInt<1>("h0") - io.r.bits <- T_566 - module Queue_90 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>} - io is invalid - mem ram : - data-type => UInt<17> - depth => 1 - write-latency => 1 - read-latency => 0 - reader => T_59 - writer => T_45 - ram.T_59.addr is invalid - ram.T_59.clk <= clk - ram.T_59.en <= UInt<1>("h0") - ram.T_45.addr is invalid - ram.T_45.clk <= clk - ram.T_45.en <= UInt<1>("h0") - ram.T_45.data is invalid - ram.T_45.mask <= UInt<1>("h0") - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_31 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_31) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_37 = and(io.enq.ready, io.enq.valid) - node T_39 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_37, T_39) - node T_41 = and(io.deq.ready, io.deq.valid) - node T_43 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_41, T_43) - when do_enq : - ram.T_45.addr <= UInt<1>("h0") - ram.T_45.en <= UInt<1>("h1") - ram.T_45.data <= io.enq.bits - ram.T_45.mask <= UInt<1>("h1") - skip - when do_deq : - skip - node T_48 = neq(do_enq, do_deq) - when T_48 : - maybe_full <= do_enq - skip - node T_50 = eq(empty, UInt<1>("h0")) - node T_52 = and(UInt<1>("h0"), io.enq.valid) - node T_53 = or(T_50, T_52) - io.deq.valid <= T_53 - node T_55 = eq(full, UInt<1>("h0")) - node T_57 = and(UInt<1>("h0"), io.deq.ready) - node T_58 = or(T_55, T_57) - io.enq.ready <= T_58 - ram.T_59.addr <= UInt<1>("h0") - ram.T_59.en <= UInt<1>("h1") - node T_60 = mux(maybe_flow, io.enq.bits, ram.T_59.data) - io.deq.bits <= T_60 - node T_61 = sub(UInt<1>("h0"), UInt<1>("h0")) - node ptr_diff = tail(T_61, 1) - node T_63 = and(maybe_full, ptr_match) - node T_64 = cat(T_63, ptr_diff) - io.count <= T_64 - module SlowIO : - input clk : Clock - input reset : UInt<1> - output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : { valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>} - io is invalid - reg divisor : UInt, clk with : - reset => (reset, UInt<9>("h1ff")) - reg d_shadow : UInt, clk with : - reset => (reset, UInt<9>("h1ff")) - reg hold : UInt, clk with : - reset => (reset, UInt<7>("h7f")) - reg h_shadow : UInt, clk with : - reset => (reset, UInt<7>("h7f")) - when io.set_divisor.valid : - node T_57 = bits(io.set_divisor.bits, 8, 0) - d_shadow <= T_57 - node T_58 = bits(io.set_divisor.bits, 24, 16) - h_shadow <= T_58 - skip - node T_59 = shl(hold, 16) - node T_60 = or(T_59, divisor) - io.divisor <= T_60 - reg count : UInt<9>, clk with : - reset => (UInt<1>("h0"), count) - reg myclock : UInt<1>, clk with : - reset => (UInt<1>("h0"), myclock) - node T_66 = add(count, UInt<1>("h1")) - node T_67 = tail(T_66, 1) - count <= T_67 - node T_68 = shr(divisor, 1) - node rising = eq(count, T_68) - node falling = eq(count, divisor) - node T_71 = shr(divisor, 1) - node T_72 = add(T_71, hold) - node T_73 = tail(T_72, 1) - node held = eq(count, T_73) - when falling : - divisor <= d_shadow - hold <= h_shadow - count <= UInt<1>("h0") - myclock <= UInt<1>("h0") - skip - when rising : - myclock <= UInt<1>("h1") - skip - reg in_slow_rdy : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg out_slow_val : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg out_slow_bits : UInt<17>, clk with : - reset => (UInt<1>("h0"), out_slow_bits) - inst fromhost_q of Queue_90 - fromhost_q.io is invalid - fromhost_q.clk <= clk - fromhost_q.reset <= reset - node T_86 = and(io.in_slow.valid, in_slow_rdy) - node T_87 = or(T_86, reset) - node T_88 = and(rising, T_87) - fromhost_q.io.enq.valid <= T_88 - fromhost_q.io.enq.bits <= io.in_slow.bits - io.in_fast <- fromhost_q.io.deq - inst tohost_q of Queue_90 - tohost_q.io is invalid - tohost_q.clk <= clk - tohost_q.reset <= reset - tohost_q.io.enq <- io.out_fast - node T_91 = and(rising, io.out_slow.ready) - node T_92 = and(T_91, out_slow_val) - tohost_q.io.deq.ready <= T_92 - when held : - in_slow_rdy <= fromhost_q.io.enq.ready - out_slow_val <= tohost_q.io.deq.valid - node T_93 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) - out_slow_bits <= T_93 - skip - io.in_slow.ready <= in_slow_rdy - io.out_slow.valid <= out_slow_val - io.out_slow.bits <= out_slow_bits - io.clk_slow <= myclock - module Uncore : - input clk : Clock - input reset : UInt<1> - output io : { host : { clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], flip tiles_cached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, status : UInt<2>}}}[1]} - io is invalid - inst htif of Htif - htif.io is invalid - htif.clk <= clk - htif.reset <= reset - inst outmemsys of OuterMemorySystem - outmemsys.io is invalid - outmemsys.clk <= clk - outmemsys.reset <= reset - outmemsys.io.incoherent[0] <= htif.io.cpu[0].reset - outmemsys.io.htif_uncached <- htif.io.mem - outmemsys.io.tiles_uncached <= io.tiles_uncached - outmemsys.io.tiles_cached <= io.tiles_cached - io.htif[0].reset <= htif.io.cpu[0].reset - io.htif[0].id <= htif.io.cpu[0].id - htif.io.cpu[0].debug_stats_csr <= io.htif[0].debug_stats_csr - inst T_8362 of SmiArbiter - T_8362.io is invalid - T_8362.clk <= clk - T_8362.reset <= reset - T_8362.io.in[0] <- htif.io.cpu[0].csr - T_8362.io.in[1] <- outmemsys.io.csr[0] - io.htif[0].csr <- T_8362.io.out - inst scrFile of SCRFile - scrFile.io is invalid - scrFile.clk <= clk - scrFile.reset <= reset - inst scrArb of SmiArbiter_81 - scrArb.io is invalid - scrArb.clk <= clk - scrArb.reset <= reset - scrArb.io.in[0] <- htif.io.scr - scrArb.io.in[1] <- outmemsys.io.scr - scrFile.io.smi <- scrArb.io.out - inst deviceTree of NastiROM - deviceTree.io is invalid - deviceTree.clk <= clk - deviceTree.reset <= reset - deviceTree.io <- outmemsys.io.deviceTree - io.host.debug_stats_csr <= htif.io.host.debug_stats_csr - io.mem <= outmemsys.io.mem - io.mmio <- outmemsys.io.mmio - outmemsys.io.mem_backup_en <= io.mem_backup_ctrl.en - inst T_8366 of SlowIO - T_8366.io is invalid - T_8366.clk <= clk - T_8366.reset <= reset - node T_8368 = eq(scrFile.io.scr.waddr, UInt<6>("h3f")) - node T_8369 = and(scrFile.io.scr.wen, T_8368) - T_8366.io.set_divisor.valid <= T_8369 - T_8366.io.set_divisor.bits <= scrFile.io.scr.wdata - scrFile.io.scr.rdata[63] <= T_8366.io.divisor - node T_8370 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) - T_8366.io.out_fast.valid <= T_8370 - node T_8371 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) - node T_8372 = cat(htif.io.host.out.valid, T_8371) - T_8366.io.out_fast.bits <= T_8372 - htif.io.host.out.ready <= T_8366.io.out_fast.ready - node T_8374 = eq(htif.io.host.out.valid, UInt<1>("h0")) - node T_8375 = and(T_8366.io.out_fast.ready, T_8374) - outmemsys.io.mem_backup.req.ready <= T_8375 - node T_8376 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8377 = and(T_8366.io.out_slow.valid, T_8376) - io.host.out.valid <= T_8377 - io.host.out.bits <= T_8366.io.out_slow.bits - node T_8378 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8380 = eq(T_8378, UInt<1>("h0")) - node T_8381 = and(T_8366.io.out_slow.valid, T_8380) - io.mem_backup_ctrl.out_valid <= T_8381 - node T_8382 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8383 = mux(T_8382, io.host.out.ready, io.mem_backup_ctrl.out_ready) - T_8366.io.out_slow.ready <= T_8383 - node T_8384 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) - node T_8385 = or(T_8384, io.host.in.valid) - T_8366.io.in_slow.valid <= T_8385 - node T_8386 = cat(T_8384, io.host.in.bits) - T_8366.io.in_slow.bits <= T_8386 - io.host.in.ready <= T_8366.io.in_slow.ready - node T_8387 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8388 = and(T_8366.io.in_fast.valid, T_8387) - outmemsys.io.mem_backup.resp.valid <= T_8388 - outmemsys.io.mem_backup.resp.bits <= T_8366.io.in_fast.bits - node T_8389 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8391 = eq(T_8389, UInt<1>("h0")) - node T_8392 = and(T_8366.io.in_fast.valid, T_8391) - htif.io.host.in.valid <= T_8392 - htif.io.host.in.bits <= T_8366.io.in_fast.bits - node T_8393 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8395 = mux(T_8393, UInt<1>("h1"), htif.io.host.in.ready) - T_8366.io.in_fast.ready <= T_8395 - io.host.clk <= T_8366.io.clk_slow - reg T_8396 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_8396) - T_8396 <= io.host.clk - node T_8398 = eq(T_8396, UInt<1>("h0")) - node T_8399 = and(io.host.clk, T_8398) - reg T_8400 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_8400) - T_8400 <= T_8399 - io.host.clk_edge <= T_8400 - module CSRFile : - input clk : Clock - input reset : UInt<1> - output io : { host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, status : UInt<2>}}}}, interrupt : UInt<1>, interrupt_cause : UInt<64>} - io is invalid - reg reg_mstatus : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk with : - reset => (UInt<1>("h0"), reg_mstatus) - wire T_4480 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_4480 is invalid - T_4480.usip <= UInt<1>("h0") - T_4480.ssip <= UInt<1>("h0") - T_4480.hsip <= UInt<1>("h0") - T_4480.msip <= UInt<1>("h0") - T_4480.utip <= UInt<1>("h0") - T_4480.stip <= UInt<1>("h0") - T_4480.htip <= UInt<1>("h0") - T_4480.mtip <= UInt<1>("h0") - reg reg_mie : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : - reset => (reset, T_4480) - wire T_4525 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_4525 is invalid - T_4525.usip <= UInt<1>("h0") - T_4525.ssip <= UInt<1>("h0") - T_4525.hsip <= UInt<1>("h0") - T_4525.msip <= UInt<1>("h0") - T_4525.utip <= UInt<1>("h0") - T_4525.stip <= UInt<1>("h0") - T_4525.htip <= UInt<1>("h0") - T_4525.mtip <= UInt<1>("h0") - reg reg_mip : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : - reset => (reset, T_4525) - reg reg_mepc : UInt<40>, clk with : - reset => (UInt<1>("h0"), reg_mepc) - reg reg_mcause : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_mcause) - reg reg_mbadaddr : UInt<40>, clk with : - reset => (UInt<1>("h0"), reg_mbadaddr) - reg reg_mscratch : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_mscratch) - reg reg_sepc : UInt<40>, clk with : - reset => (UInt<1>("h0"), reg_sepc) - reg reg_scause : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_scause) - reg reg_sbadaddr : UInt<40>, clk with : - reset => (UInt<1>("h0"), reg_sbadaddr) - reg reg_sscratch : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_sscratch) - reg reg_stvec : UInt<39>, clk with : - reset => (UInt<1>("h0"), reg_stvec) - reg reg_mtimecmp : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_mtimecmp) - reg reg_sptbr : UInt<32>, clk with : - reset => (UInt<1>("h0"), reg_sptbr) - reg reg_wfi : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg reg_tohost : UInt<64>, clk with : - reset => (reset, UInt<64>("h0")) - reg reg_fromhost : UInt<64>, clk with : - reset => (reset, UInt<64>("h0")) - reg reg_stats : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg reg_time : UInt<64>, clk with : - reset => (UInt<1>("h0"), reg_time) - reg T_4584 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4586 = neq(io.retire, UInt<1>("h0")) - node T_4588 = add(T_4584, UInt<7>("h1")) - node T_4589 = tail(T_4588, 1) - when T_4586 : - node T_4590 = bits(T_4589, 5, 0) - T_4584 <= T_4590 - skip - reg T_4592 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4593 = bits(T_4589, 6, 6) - node T_4594 = and(T_4586, T_4593) - when T_4594 : - node T_4596 = add(T_4592, UInt<1>("h1")) - node T_4597 = tail(T_4596, 1) - T_4592 <= T_4597 - skip - node T_4598 = cat(T_4592, T_4584) - reg T_4601 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4603 = neq(UInt<1>("h1"), UInt<1>("h0")) - node T_4605 = add(T_4601, UInt<7>("h1")) - node T_4606 = tail(T_4605, 1) - when T_4603 : - node T_4607 = bits(T_4606, 5, 0) - T_4601 <= T_4607 - skip - reg T_4609 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4610 = bits(T_4606, 6, 6) - node T_4611 = and(T_4603, T_4610) - when T_4611 : - node T_4613 = add(T_4609, UInt<1>("h1")) - node T_4614 = tail(T_4613, 1) - T_4609 <= T_4614 - skip - node T_4615 = cat(T_4609, T_4601) - reg T_4617 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4619 = neq(io.uarch_counters[0], UInt<1>("h0")) - node T_4621 = add(T_4617, UInt<7>("h1")) - node T_4622 = tail(T_4621, 1) - when T_4619 : - node T_4623 = bits(T_4622, 5, 0) - T_4617 <= T_4623 - skip - reg T_4625 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4626 = bits(T_4622, 6, 6) - node T_4627 = and(T_4619, T_4626) - when T_4627 : - node T_4629 = add(T_4625, UInt<1>("h1")) - node T_4630 = tail(T_4629, 1) - T_4625 <= T_4630 - skip - node T_4631 = cat(T_4625, T_4617) - reg T_4633 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4635 = neq(io.uarch_counters[1], UInt<1>("h0")) - node T_4637 = add(T_4633, UInt<7>("h1")) - node T_4638 = tail(T_4637, 1) - when T_4635 : - node T_4639 = bits(T_4638, 5, 0) - T_4633 <= T_4639 - skip - reg T_4641 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4642 = bits(T_4638, 6, 6) - node T_4643 = and(T_4635, T_4642) - when T_4643 : - node T_4645 = add(T_4641, UInt<1>("h1")) - node T_4646 = tail(T_4645, 1) - T_4641 <= T_4646 - skip - node T_4647 = cat(T_4641, T_4633) - reg T_4649 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4651 = neq(io.uarch_counters[2], UInt<1>("h0")) - node T_4653 = add(T_4649, UInt<7>("h1")) - node T_4654 = tail(T_4653, 1) - when T_4651 : - node T_4655 = bits(T_4654, 5, 0) - T_4649 <= T_4655 - skip - reg T_4657 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4658 = bits(T_4654, 6, 6) - node T_4659 = and(T_4651, T_4658) - when T_4659 : - node T_4661 = add(T_4657, UInt<1>("h1")) - node T_4662 = tail(T_4661, 1) - T_4657 <= T_4662 - skip - node T_4663 = cat(T_4657, T_4649) - reg T_4665 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4667 = neq(io.uarch_counters[3], UInt<1>("h0")) - node T_4669 = add(T_4665, UInt<7>("h1")) - node T_4670 = tail(T_4669, 1) - when T_4667 : - node T_4671 = bits(T_4670, 5, 0) - T_4665 <= T_4671 - skip - reg T_4673 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4674 = bits(T_4670, 6, 6) - node T_4675 = and(T_4667, T_4674) - when T_4675 : - node T_4677 = add(T_4673, UInt<1>("h1")) - node T_4678 = tail(T_4677, 1) - T_4673 <= T_4678 - skip - node T_4679 = cat(T_4673, T_4665) - reg T_4681 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4683 = neq(io.uarch_counters[4], UInt<1>("h0")) - node T_4685 = add(T_4681, UInt<7>("h1")) - node T_4686 = tail(T_4685, 1) - when T_4683 : - node T_4687 = bits(T_4686, 5, 0) - T_4681 <= T_4687 - skip - reg T_4689 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4690 = bits(T_4686, 6, 6) - node T_4691 = and(T_4683, T_4690) - when T_4691 : - node T_4693 = add(T_4689, UInt<1>("h1")) - node T_4694 = tail(T_4693, 1) - T_4689 <= T_4694 - skip - node T_4695 = cat(T_4689, T_4681) - reg T_4697 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4699 = neq(io.uarch_counters[5], UInt<1>("h0")) - node T_4701 = add(T_4697, UInt<7>("h1")) - node T_4702 = tail(T_4701, 1) - when T_4699 : - node T_4703 = bits(T_4702, 5, 0) - T_4697 <= T_4703 - skip - reg T_4705 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4706 = bits(T_4702, 6, 6) - node T_4707 = and(T_4699, T_4706) - when T_4707 : - node T_4709 = add(T_4705, UInt<1>("h1")) - node T_4710 = tail(T_4709, 1) - T_4705 <= T_4710 - skip - node T_4711 = cat(T_4705, T_4697) - reg T_4713 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4715 = neq(io.uarch_counters[6], UInt<1>("h0")) - node T_4717 = add(T_4713, UInt<7>("h1")) - node T_4718 = tail(T_4717, 1) - when T_4715 : - node T_4719 = bits(T_4718, 5, 0) - T_4713 <= T_4719 - skip - reg T_4721 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4722 = bits(T_4718, 6, 6) - node T_4723 = and(T_4715, T_4722) - when T_4723 : - node T_4725 = add(T_4721, UInt<1>("h1")) - node T_4726 = tail(T_4725, 1) - T_4721 <= T_4726 - skip - node T_4727 = cat(T_4721, T_4713) - reg T_4729 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4731 = neq(io.uarch_counters[7], UInt<1>("h0")) - node T_4733 = add(T_4729, UInt<7>("h1")) - node T_4734 = tail(T_4733, 1) - when T_4731 : - node T_4735 = bits(T_4734, 5, 0) - T_4729 <= T_4735 - skip - reg T_4737 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4738 = bits(T_4734, 6, 6) - node T_4739 = and(T_4731, T_4738) - when T_4739 : - node T_4741 = add(T_4737, UInt<1>("h1")) - node T_4742 = tail(T_4741, 1) - T_4737 <= T_4742 - skip - node T_4743 = cat(T_4737, T_4729) - reg T_4745 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4747 = neq(io.uarch_counters[8], UInt<1>("h0")) - node T_4749 = add(T_4745, UInt<7>("h1")) - node T_4750 = tail(T_4749, 1) - when T_4747 : - node T_4751 = bits(T_4750, 5, 0) - T_4745 <= T_4751 - skip - reg T_4753 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4754 = bits(T_4750, 6, 6) - node T_4755 = and(T_4747, T_4754) - when T_4755 : - node T_4757 = add(T_4753, UInt<1>("h1")) - node T_4758 = tail(T_4757, 1) - T_4753 <= T_4758 - skip - node T_4759 = cat(T_4753, T_4745) - reg T_4761 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4763 = neq(io.uarch_counters[9], UInt<1>("h0")) - node T_4765 = add(T_4761, UInt<7>("h1")) - node T_4766 = tail(T_4765, 1) - when T_4763 : - node T_4767 = bits(T_4766, 5, 0) - T_4761 <= T_4767 - skip - reg T_4769 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4770 = bits(T_4766, 6, 6) - node T_4771 = and(T_4763, T_4770) - when T_4771 : - node T_4773 = add(T_4769, UInt<1>("h1")) - node T_4774 = tail(T_4773, 1) - T_4769 <= T_4774 - skip - node T_4775 = cat(T_4769, T_4761) - reg T_4777 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4779 = neq(io.uarch_counters[10], UInt<1>("h0")) - node T_4781 = add(T_4777, UInt<7>("h1")) - node T_4782 = tail(T_4781, 1) - when T_4779 : - node T_4783 = bits(T_4782, 5, 0) - T_4777 <= T_4783 - skip - reg T_4785 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4786 = bits(T_4782, 6, 6) - node T_4787 = and(T_4779, T_4786) - when T_4787 : - node T_4789 = add(T_4785, UInt<1>("h1")) - node T_4790 = tail(T_4789, 1) - T_4785 <= T_4790 - skip - node T_4791 = cat(T_4785, T_4777) - reg T_4793 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4795 = neq(io.uarch_counters[11], UInt<1>("h0")) - node T_4797 = add(T_4793, UInt<7>("h1")) - node T_4798 = tail(T_4797, 1) - when T_4795 : - node T_4799 = bits(T_4798, 5, 0) - T_4793 <= T_4799 - skip - reg T_4801 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4802 = bits(T_4798, 6, 6) - node T_4803 = and(T_4795, T_4802) - when T_4803 : - node T_4805 = add(T_4801, UInt<1>("h1")) - node T_4806 = tail(T_4805, 1) - T_4801 <= T_4806 - skip - node T_4807 = cat(T_4801, T_4793) - reg T_4809 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4811 = neq(io.uarch_counters[12], UInt<1>("h0")) - node T_4813 = add(T_4809, UInt<7>("h1")) - node T_4814 = tail(T_4813, 1) - when T_4811 : - node T_4815 = bits(T_4814, 5, 0) - T_4809 <= T_4815 - skip - reg T_4817 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4818 = bits(T_4814, 6, 6) - node T_4819 = and(T_4811, T_4818) - when T_4819 : - node T_4821 = add(T_4817, UInt<1>("h1")) - node T_4822 = tail(T_4821, 1) - T_4817 <= T_4822 - skip - node T_4823 = cat(T_4817, T_4809) - reg T_4825 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4827 = neq(io.uarch_counters[13], UInt<1>("h0")) - node T_4829 = add(T_4825, UInt<7>("h1")) - node T_4830 = tail(T_4829, 1) - when T_4827 : - node T_4831 = bits(T_4830, 5, 0) - T_4825 <= T_4831 - skip - reg T_4833 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4834 = bits(T_4830, 6, 6) - node T_4835 = and(T_4827, T_4834) - when T_4835 : - node T_4837 = add(T_4833, UInt<1>("h1")) - node T_4838 = tail(T_4837, 1) - T_4833 <= T_4838 - skip - node T_4839 = cat(T_4833, T_4825) - reg T_4841 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4843 = neq(io.uarch_counters[14], UInt<1>("h0")) - node T_4845 = add(T_4841, UInt<7>("h1")) - node T_4846 = tail(T_4845, 1) - when T_4843 : - node T_4847 = bits(T_4846, 5, 0) - T_4841 <= T_4847 - skip - reg T_4849 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4850 = bits(T_4846, 6, 6) - node T_4851 = and(T_4843, T_4850) - when T_4851 : - node T_4853 = add(T_4849, UInt<1>("h1")) - node T_4854 = tail(T_4853, 1) - T_4849 <= T_4854 - skip - node T_4855 = cat(T_4849, T_4841) - reg T_4857 : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - node T_4859 = neq(io.uarch_counters[15], UInt<1>("h0")) - node T_4861 = add(T_4857, UInt<7>("h1")) - node T_4862 = tail(T_4861, 1) - when T_4859 : - node T_4863 = bits(T_4862, 5, 0) - T_4857 <= T_4863 - skip - reg T_4865 : UInt<58>, clk with : - reset => (reset, UInt<58>("h0")) - node T_4866 = bits(T_4862, 6, 6) - node T_4867 = and(T_4859, T_4866) - when T_4867 : - node T_4869 = add(T_4865, UInt<1>("h1")) - node T_4870 = tail(T_4869, 1) - T_4865 <= T_4870 - skip - node T_4871 = cat(T_4865, T_4857) - reg reg_fflags : UInt<5>, clk with : - reset => (UInt<1>("h0"), reg_fflags) - reg reg_frm : UInt<3>, clk with : - reset => (UInt<1>("h0"), reg_frm) - node irq_rocc = and(UInt<1>("h0"), io.rocc.interrupt) - io.interrupt_cause <= UInt<1>("h0") - node T_4879 = bits(io.interrupt_cause, 63, 63) - io.interrupt <= T_4879 - wire some_interrupt_pending : UInt<1> - some_interrupt_pending <= UInt<1>("h0") - node T_4883 = and(reg_mie.ssip, reg_mip.ssip) - node T_4884 = lt(reg_mstatus.prv, UInt<1>("h1")) - node T_4885 = eq(reg_mstatus.prv, UInt<1>("h1")) - node T_4886 = and(T_4885, reg_mstatus.ie) - node T_4887 = or(T_4884, T_4886) - node T_4888 = and(T_4883, T_4887) - when T_4888 : - io.interrupt_cause <= UInt<64>("h8000000000000000") - skip - node T_4890 = leq(reg_mstatus.prv, UInt<1>("h1")) - node T_4891 = and(T_4883, T_4890) - when T_4891 : - some_interrupt_pending <= UInt<1>("h1") - skip - node T_4894 = and(reg_mie.msip, reg_mip.msip) - node T_4895 = lt(reg_mstatus.prv, UInt<2>("h3")) - node T_4896 = eq(reg_mstatus.prv, UInt<2>("h3")) - node T_4897 = and(T_4896, reg_mstatus.ie) - node T_4898 = or(T_4895, T_4897) - node T_4899 = and(T_4894, T_4898) - when T_4899 : - io.interrupt_cause <= UInt<64>("h8000000000000000") - skip - node T_4901 = leq(reg_mstatus.prv, UInt<2>("h3")) - node T_4902 = and(T_4894, T_4901) - when T_4902 : - some_interrupt_pending <= UInt<1>("h1") - skip - node T_4905 = and(reg_mie.stip, reg_mip.stip) - node T_4906 = lt(reg_mstatus.prv, UInt<1>("h1")) - node T_4907 = eq(reg_mstatus.prv, UInt<1>("h1")) - node T_4908 = and(T_4907, reg_mstatus.ie) - node T_4909 = or(T_4906, T_4908) - node T_4910 = and(T_4905, T_4909) - when T_4910 : - io.interrupt_cause <= UInt<64>("h8000000000000001") - skip - node T_4912 = leq(reg_mstatus.prv, UInt<1>("h1")) - node T_4913 = and(T_4905, T_4912) - when T_4913 : - some_interrupt_pending <= UInt<1>("h1") - skip - node T_4916 = and(reg_mie.mtip, reg_mip.mtip) - node T_4917 = lt(reg_mstatus.prv, UInt<2>("h3")) - node T_4918 = eq(reg_mstatus.prv, UInt<2>("h3")) - node T_4919 = and(T_4918, reg_mstatus.ie) - node T_4920 = or(T_4917, T_4919) - node T_4921 = and(T_4916, T_4920) - when T_4921 : - io.interrupt_cause <= UInt<64>("h8000000000000001") - skip - node T_4923 = leq(reg_mstatus.prv, UInt<2>("h3")) - node T_4924 = and(T_4916, T_4923) - when T_4924 : - some_interrupt_pending <= UInt<1>("h1") - skip - node T_4928 = neq(reg_fromhost, UInt<1>("h0")) - node T_4929 = lt(reg_mstatus.prv, UInt<2>("h3")) - node T_4930 = eq(reg_mstatus.prv, UInt<2>("h3")) - node T_4931 = and(T_4930, reg_mstatus.ie) - node T_4932 = or(T_4929, T_4931) - node T_4933 = and(T_4928, T_4932) - when T_4933 : - io.interrupt_cause <= UInt<64>("h8000000000000002") - skip - node T_4935 = leq(reg_mstatus.prv, UInt<2>("h3")) - node T_4936 = and(T_4928, T_4935) - when T_4936 : - some_interrupt_pending <= UInt<1>("h1") - skip - node T_4939 = lt(reg_mstatus.prv, UInt<2>("h3")) - node T_4940 = eq(reg_mstatus.prv, UInt<2>("h3")) - node T_4941 = and(T_4940, reg_mstatus.ie) - node T_4942 = or(T_4939, T_4941) - node T_4943 = and(irq_rocc, T_4942) - when T_4943 : - io.interrupt_cause <= UInt<64>("h8000000000000003") - skip - node T_4945 = leq(reg_mstatus.prv, UInt<2>("h3")) - node T_4946 = and(irq_rocc, T_4945) - when T_4946 : - some_interrupt_pending <= UInt<1>("h1") - skip - node system_insn = eq(io.rw.cmd, UInt<3>("h4")) - node T_4949 = neq(io.rw.cmd, UInt<3>("h0")) - node T_4951 = eq(system_insn, UInt<1>("h0")) - node cpu_ren = and(T_4949, T_4951) - reg host_csr_req_valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), host_csr_req_valid) - node T_4956 = eq(cpu_ren, UInt<1>("h0")) - node host_csr_req_fire = and(host_csr_req_valid, T_4956) - reg host_csr_rep_valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), host_csr_rep_valid) - reg host_csr_bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), host_csr_bits) - node T_4965 = eq(host_csr_req_valid, UInt<1>("h0")) - node T_4967 = eq(host_csr_rep_valid, UInt<1>("h0")) - node T_4968 = and(T_4965, T_4967) - io.host.csr.req.ready <= T_4968 - io.host.csr.resp.valid <= host_csr_rep_valid - io.host.csr.resp.bits <= host_csr_bits.data - node T_4969 = and(io.host.csr.req.ready, io.host.csr.req.valid) - when T_4969 : - host_csr_req_valid <= UInt<1>("h1") - host_csr_bits <- io.host.csr.req.bits - skip - when host_csr_req_fire : - host_csr_req_valid <= UInt<1>("h0") - host_csr_rep_valid <= UInt<1>("h1") - host_csr_bits.data <= io.rw.rdata - skip - node T_4973 = and(io.host.csr.resp.ready, io.host.csr.resp.valid) - when T_4973 : - host_csr_rep_valid <= UInt<1>("h0") - skip - io.host.debug_stats_csr <= reg_stats - node T_4975 = cat(io.status.sd, io.status.zero2) - node T_4976 = cat(io.status.sd_rv32, io.status.zero1) - node T_4977 = cat(T_4975, T_4976) - node T_4978 = cat(io.status.vm, io.status.mprv) - node T_4979 = cat(io.status.xs, io.status.fs) - node T_4980 = cat(T_4978, T_4979) - node T_4981 = cat(T_4977, T_4980) - node T_4982 = cat(io.status.prv3, io.status.ie3) - node T_4983 = cat(io.status.prv2, io.status.ie2) - node T_4984 = cat(T_4982, T_4983) - node T_4985 = cat(io.status.prv1, io.status.ie1) - node T_4986 = cat(io.status.prv, io.status.ie) - node T_4987 = cat(T_4985, T_4986) - node T_4988 = cat(T_4984, T_4987) - node read_mstatus = cat(T_4981, T_4988) - node T_4990 = cat(reg_frm, reg_fflags) - node T_4998 = cat(reg_mip.mtip, reg_mip.htip) - node T_4999 = cat(reg_mip.stip, reg_mip.utip) - node T_5000 = cat(T_4998, T_4999) - node T_5001 = cat(reg_mip.msip, reg_mip.hsip) - node T_5002 = cat(reg_mip.ssip, reg_mip.usip) - node T_5003 = cat(T_5001, T_5002) - node T_5004 = cat(T_5000, T_5003) - node T_5005 = cat(reg_mie.mtip, reg_mie.htip) - node T_5006 = cat(reg_mie.stip, reg_mie.utip) - node T_5007 = cat(T_5005, T_5006) - node T_5008 = cat(reg_mie.msip, reg_mie.hsip) - node T_5009 = cat(reg_mie.ssip, reg_mie.usip) - node T_5010 = cat(T_5008, T_5009) - node T_5011 = cat(T_5007, T_5010) - node T_5012 = bits(reg_mepc, 39, 39) - node T_5014 = sub(UInt<24>("h0"), T_5012) - node T_5015 = tail(T_5014, 1) - node T_5016 = cat(T_5015, reg_mepc) - node T_5017 = bits(reg_mbadaddr, 39, 39) - node T_5019 = sub(UInt<24>("h0"), T_5017) - node T_5020 = tail(T_5019, 1) - node T_5021 = cat(T_5020, reg_mbadaddr) - wire T_5048 : { sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5048 is invalid - node T_5061 = bits(read_mstatus, 0, 0) - T_5048.ie <= T_5061 - node T_5062 = bits(read_mstatus, 2, 1) - T_5048.zero1 <= T_5062 - node T_5063 = bits(read_mstatus, 3, 3) - T_5048.pie <= T_5063 - node T_5064 = bits(read_mstatus, 4, 4) - T_5048.ps <= T_5064 - node T_5065 = bits(read_mstatus, 11, 5) - T_5048.zero2 <= T_5065 - node T_5066 = bits(read_mstatus, 13, 12) - T_5048.fs <= T_5066 - node T_5067 = bits(read_mstatus, 15, 14) - T_5048.xs <= T_5067 - node T_5068 = bits(read_mstatus, 16, 16) - T_5048.mprv <= T_5068 - node T_5069 = bits(read_mstatus, 30, 17) - T_5048.zero3 <= T_5069 - node T_5070 = bits(read_mstatus, 31, 31) - T_5048.sd_rv32 <= T_5070 - node T_5071 = bits(read_mstatus, 62, 32) - T_5048.zero4 <= T_5071 - node T_5072 = bits(read_mstatus, 63, 63) - T_5048.sd <= T_5072 - wire T_5073 : { sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5073 <- T_5048 - T_5073.zero1 <= UInt<1>("h0") - T_5073.zero2 <= UInt<1>("h0") - T_5073.zero3 <= UInt<1>("h0") - T_5073.zero4 <= UInt<1>("h0") - wire T_5109 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5109 is invalid - T_5109.usip <= UInt<1>("h0") - T_5109.ssip <= UInt<1>("h0") - T_5109.hsip <= UInt<1>("h0") - T_5109.msip <= UInt<1>("h0") - T_5109.utip <= UInt<1>("h0") - T_5109.stip <= UInt<1>("h0") - T_5109.htip <= UInt<1>("h0") - T_5109.mtip <= UInt<1>("h0") - wire T_5126 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5126 <- T_5109 - T_5126.ssip <= reg_mip.ssip - T_5126.stip <= reg_mip.stip - wire T_5154 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5154 is invalid - T_5154.usip <= UInt<1>("h0") - T_5154.ssip <= UInt<1>("h0") - T_5154.hsip <= UInt<1>("h0") - T_5154.msip <= UInt<1>("h0") - T_5154.utip <= UInt<1>("h0") - T_5154.stip <= UInt<1>("h0") - T_5154.htip <= UInt<1>("h0") - T_5154.mtip <= UInt<1>("h0") - wire T_5171 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5171 <- T_5154 - T_5171.ssip <= reg_mie.ssip - T_5171.stip <= reg_mie.stip - node T_5180 = cat(T_5073.zero4, T_5073.sd_rv32) - node T_5181 = cat(T_5073.sd, T_5180) - node T_5182 = cat(T_5073.mprv, T_5073.xs) - node T_5183 = cat(T_5073.zero3, T_5182) - node T_5184 = cat(T_5181, T_5183) - node T_5185 = cat(T_5073.zero2, T_5073.ps) - node T_5186 = cat(T_5073.fs, T_5185) - node T_5187 = cat(T_5073.zero1, T_5073.ie) - node T_5188 = cat(T_5073.pie, T_5187) - node T_5189 = cat(T_5186, T_5188) - node T_5190 = cat(T_5184, T_5189) - node T_5191 = cat(T_5126.mtip, T_5126.htip) - node T_5192 = cat(T_5126.stip, T_5126.utip) - node T_5193 = cat(T_5191, T_5192) - node T_5194 = cat(T_5126.msip, T_5126.hsip) - node T_5195 = cat(T_5126.ssip, T_5126.usip) - node T_5196 = cat(T_5194, T_5195) - node T_5197 = cat(T_5193, T_5196) - node T_5198 = cat(T_5171.mtip, T_5171.htip) - node T_5199 = cat(T_5171.stip, T_5171.utip) - node T_5200 = cat(T_5198, T_5199) - node T_5201 = cat(T_5171.msip, T_5171.hsip) - node T_5202 = cat(T_5171.ssip, T_5171.usip) - node T_5203 = cat(T_5201, T_5202) - node T_5204 = cat(T_5200, T_5203) - node T_5205 = bits(reg_sbadaddr, 39, 39) - node T_5207 = sub(UInt<24>("h0"), T_5205) - node T_5208 = tail(T_5207, 1) - node T_5209 = cat(T_5208, reg_sbadaddr) - node T_5211 = bits(reg_sepc, 39, 39) - node T_5213 = sub(UInt<24>("h0"), T_5211) - node T_5214 = tail(T_5213, 1) - node T_5215 = cat(T_5214, reg_sepc) - node T_5216 = bits(reg_stvec, 38, 38) - node T_5218 = sub(UInt<25>("h0"), T_5216) - node T_5219 = tail(T_5218, 1) - node T_5220 = cat(T_5219, reg_stvec) - node addr = mux(cpu_ren, io.rw.addr, host_csr_bits.addr) - node T_5223 = eq(addr, UInt<1>("h1")) - node T_5225 = eq(addr, UInt<2>("h2")) - node T_5227 = eq(addr, UInt<2>("h3")) - node T_5229 = eq(addr, UInt<12>("hc00")) - node T_5231 = eq(addr, UInt<12>("h900")) - node T_5233 = eq(addr, UInt<12>("hc01")) - node T_5235 = eq(addr, UInt<12>("h901")) - node T_5237 = eq(addr, UInt<12>("hd01")) - node T_5239 = eq(addr, UInt<12>("ha01")) - node T_5241 = eq(addr, UInt<11>("h701")) - node T_5243 = eq(addr, UInt<12>("hf00")) - node T_5245 = eq(addr, UInt<12>("hf01")) - node T_5247 = eq(addr, UInt<10>("h300")) - node T_5249 = eq(addr, UInt<10>("h302")) - node T_5251 = eq(addr, UInt<11>("h782")) - node T_5253 = eq(addr, UInt<10>("h301")) - node T_5255 = eq(addr, UInt<11>("h784")) - node T_5257 = eq(addr, UInt<11>("h783")) - node T_5259 = eq(addr, UInt<10>("h344")) - node T_5261 = eq(addr, UInt<10>("h304")) - node T_5263 = eq(addr, UInt<10>("h340")) - node T_5265 = eq(addr, UInt<10>("h341")) - node T_5267 = eq(addr, UInt<10>("h343")) - node T_5269 = eq(addr, UInt<10>("h342")) - node T_5271 = eq(addr, UInt<10>("h321")) - node T_5273 = eq(addr, UInt<12>("hf10")) - node T_5275 = eq(addr, UInt<8>("hc0")) - node T_5277 = eq(addr, UInt<11>("h780")) - node T_5279 = eq(addr, UInt<11>("h781")) - node T_5281 = eq(addr, UInt<12>("hc02")) - node T_5283 = eq(addr, UInt<12>("h902")) - node T_5285 = eq(addr, UInt<12>("hcc0")) - node T_5287 = eq(addr, UInt<12>("hcc1")) - node T_5289 = eq(addr, UInt<12>("hcc2")) - node T_5291 = eq(addr, UInt<12>("hcc3")) - node T_5293 = eq(addr, UInt<12>("hcc4")) - node T_5295 = eq(addr, UInt<12>("hcc5")) - node T_5297 = eq(addr, UInt<12>("hcc6")) - node T_5299 = eq(addr, UInt<12>("hcc7")) - node T_5301 = eq(addr, UInt<12>("hcc8")) - node T_5303 = eq(addr, UInt<12>("hcc9")) - node T_5305 = eq(addr, UInt<12>("hcca")) - node T_5307 = eq(addr, UInt<12>("hccb")) - node T_5309 = eq(addr, UInt<12>("hccc")) - node T_5311 = eq(addr, UInt<12>("hccd")) - node T_5313 = eq(addr, UInt<12>("hcce")) - node T_5315 = eq(addr, UInt<12>("hccf")) - node T_5317 = eq(addr, UInt<9>("h100")) - node T_5319 = eq(addr, UInt<9>("h144")) - node T_5321 = eq(addr, UInt<9>("h104")) - node T_5323 = eq(addr, UInt<9>("h140")) - node T_5325 = eq(addr, UInt<12>("hd42")) - node T_5327 = eq(addr, UInt<12>("hd43")) - node T_5329 = eq(addr, UInt<9>("h180")) - node T_5331 = eq(addr, UInt<9>("h181")) - node T_5333 = eq(addr, UInt<9>("h141")) - node T_5335 = eq(addr, UInt<9>("h101")) - node T_5336 = or(T_5223, T_5225) - node T_5337 = or(T_5336, T_5227) - node T_5338 = or(T_5337, T_5229) - node T_5339 = or(T_5338, T_5231) - node T_5340 = or(T_5339, T_5233) - node T_5341 = or(T_5340, T_5235) - node T_5342 = or(T_5341, T_5237) - node T_5343 = or(T_5342, T_5239) - node T_5344 = or(T_5343, T_5241) - node T_5345 = or(T_5344, T_5243) - node T_5346 = or(T_5345, T_5245) - node T_5347 = or(T_5346, T_5247) - node T_5348 = or(T_5347, T_5249) - node T_5349 = or(T_5348, T_5251) - node T_5350 = or(T_5349, T_5253) - node T_5351 = or(T_5350, T_5255) - node T_5352 = or(T_5351, T_5257) - node T_5353 = or(T_5352, T_5259) - node T_5354 = or(T_5353, T_5261) - node T_5355 = or(T_5354, T_5263) - node T_5356 = or(T_5355, T_5265) - node T_5357 = or(T_5356, T_5267) - node T_5358 = or(T_5357, T_5269) - node T_5359 = or(T_5358, T_5271) - node T_5360 = or(T_5359, T_5273) - node T_5361 = or(T_5360, T_5275) - node T_5362 = or(T_5361, T_5277) - node T_5363 = or(T_5362, T_5279) - node T_5364 = or(T_5363, T_5281) - node T_5365 = or(T_5364, T_5283) - node T_5366 = or(T_5365, T_5285) - node T_5367 = or(T_5366, T_5287) - node T_5368 = or(T_5367, T_5289) - node T_5369 = or(T_5368, T_5291) - node T_5370 = or(T_5369, T_5293) - node T_5371 = or(T_5370, T_5295) - node T_5372 = or(T_5371, T_5297) - node T_5373 = or(T_5372, T_5299) - node T_5374 = or(T_5373, T_5301) - node T_5375 = or(T_5374, T_5303) - node T_5376 = or(T_5375, T_5305) - node T_5377 = or(T_5376, T_5307) - node T_5378 = or(T_5377, T_5309) - node T_5379 = or(T_5378, T_5311) - node T_5380 = or(T_5379, T_5313) - node T_5381 = or(T_5380, T_5315) - node T_5382 = or(T_5381, T_5317) - node T_5383 = or(T_5382, T_5319) - node T_5384 = or(T_5383, T_5321) - node T_5385 = or(T_5384, T_5323) - node T_5386 = or(T_5385, T_5325) - node T_5387 = or(T_5386, T_5327) - node T_5388 = or(T_5387, T_5329) - node T_5389 = or(T_5388, T_5331) - node T_5390 = or(T_5389, T_5333) - node addr_valid = or(T_5390, T_5335) - node T_5392 = or(T_5223, T_5225) - node fp_csr = or(T_5392, T_5227) - node csr_addr_priv = bits(io.rw.addr, 9, 8) - node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) - node T_5396 = bits(io.rw.addr, 11, 10) - node T_5397 = not(T_5396) - node read_only = eq(T_5397, UInt<1>("h0")) - node T_5400 = neq(io.rw.cmd, UInt<3>("h5")) - node T_5401 = and(cpu_ren, T_5400) - node cpu_wen = and(T_5401, priv_sufficient) - node T_5404 = eq(read_only, UInt<1>("h0")) - node T_5405 = and(cpu_wen, T_5404) - node T_5406 = and(host_csr_req_fire, host_csr_bits.rw) - node wen = or(T_5405, T_5406) - node T_5408 = eq(io.rw.cmd, UInt<3>("h1")) - node T_5409 = eq(io.rw.cmd, UInt<3>("h3")) - node T_5410 = not(io.rw.wdata) - node T_5411 = and(io.rw.rdata, T_5410) - node T_5412 = eq(io.rw.cmd, UInt<3>("h2")) - node T_5413 = or(io.rw.rdata, io.rw.wdata) - node T_5414 = mux(T_5412, T_5413, host_csr_bits.data) - node T_5415 = mux(T_5409, T_5411, T_5414) - node wdata = mux(T_5408, io.rw.wdata, T_5415) - node T_5417 = bits(io.rw.addr, 8, 8) - node T_5419 = eq(T_5417, UInt<1>("h0")) - node T_5420 = bits(io.rw.addr, 0, 0) - node T_5422 = eq(T_5420, UInt<1>("h0")) - node T_5423 = and(T_5419, T_5422) - node insn_call = and(T_5423, system_insn) - node T_5425 = bits(io.rw.addr, 8, 8) - node T_5427 = eq(T_5425, UInt<1>("h0")) - node T_5428 = bits(io.rw.addr, 0, 0) - node T_5429 = and(T_5427, T_5428) - node insn_break = and(T_5429, system_insn) - node T_5431 = bits(io.rw.addr, 8, 8) - node T_5432 = bits(io.rw.addr, 1, 1) - node T_5434 = eq(T_5432, UInt<1>("h0")) - node T_5435 = and(T_5431, T_5434) - node T_5436 = bits(io.rw.addr, 0, 0) - node T_5438 = eq(T_5436, UInt<1>("h0")) - node T_5439 = and(T_5435, T_5438) - node T_5440 = and(T_5439, system_insn) - node insn_ret = and(T_5440, priv_sufficient) - node T_5442 = bits(io.rw.addr, 8, 8) - node T_5443 = bits(io.rw.addr, 1, 1) - node T_5445 = eq(T_5443, UInt<1>("h0")) - node T_5446 = and(T_5442, T_5445) - node T_5447 = bits(io.rw.addr, 0, 0) - node T_5448 = and(T_5446, T_5447) - node T_5449 = and(T_5448, system_insn) - node insn_sfence_vm = and(T_5449, priv_sufficient) - node T_5451 = bits(io.rw.addr, 2, 2) - node maybe_insn_redirect_trap = and(T_5451, system_insn) - node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) - node T_5454 = bits(io.rw.addr, 8, 8) - node T_5455 = bits(io.rw.addr, 1, 1) - node T_5456 = and(T_5454, T_5455) - node T_5457 = bits(io.rw.addr, 0, 0) - node T_5459 = eq(T_5457, UInt<1>("h0")) - node T_5460 = and(T_5456, T_5459) - node T_5461 = and(T_5460, system_insn) - node insn_wfi = and(T_5461, priv_sufficient) - node T_5463 = and(cpu_wen, read_only) - node T_5465 = eq(priv_sufficient, UInt<1>("h0")) - node T_5467 = eq(addr_valid, UInt<1>("h0")) - node T_5468 = or(T_5465, T_5467) - node T_5470 = neq(io.status.fs, UInt<1>("h0")) - node T_5472 = eq(T_5470, UInt<1>("h0")) - node T_5473 = and(fp_csr, T_5472) - node T_5474 = or(T_5468, T_5473) - node T_5475 = and(cpu_ren, T_5474) - node T_5476 = or(T_5463, T_5475) - node T_5478 = eq(priv_sufficient, UInt<1>("h0")) - node T_5479 = and(system_insn, T_5478) - node T_5480 = or(T_5476, T_5479) - node T_5481 = or(T_5480, insn_call) - node csr_xcpt = or(T_5481, insn_break) - when insn_wfi : - reg_wfi <= UInt<1>("h1") - skip - when some_interrupt_pending : - reg_wfi <= UInt<1>("h0") - skip - io.fatc <= insn_sfence_vm - node T_5485 = or(io.exception, csr_xcpt) - node T_5486 = shl(reg_mstatus.prv, 6) - node T_5488 = add(T_5486, UInt<9>("h100")) - node T_5489 = tail(T_5488, 1) - node T_5490 = bits(reg_stvec, 38, 38) - node T_5491 = cat(T_5490, reg_stvec) - node T_5492 = bits(reg_mstatus.prv, 1, 1) - node T_5494 = or(T_5492, UInt<1>("h0")) - node T_5495 = mux(T_5494, reg_mepc, reg_sepc) - node T_5496 = mux(maybe_insn_redirect_trap, T_5491, T_5495) - node T_5497 = mux(T_5485, T_5489, T_5496) - io.evec <= T_5497 - io.ptbr <= reg_sptbr - io.csr_xcpt <= csr_xcpt - node T_5498 = or(insn_ret, insn_redirect_trap) - io.eret <= T_5498 - io.status <- reg_mstatus - node T_5500 = neq(reg_mstatus.fs, UInt<1>("h0")) - node T_5502 = sub(UInt<2>("h0"), T_5500) - node T_5503 = tail(T_5502, 1) - io.status.fs <= T_5503 - node T_5505 = neq(reg_mstatus.xs, UInt<1>("h0")) - node T_5507 = sub(UInt<2>("h0"), T_5505) - node T_5508 = tail(T_5507, 1) - io.status.xs <= T_5508 - node T_5509 = not(io.status.fs) - node T_5511 = eq(T_5509, UInt<1>("h0")) - node T_5512 = not(io.status.xs) - node T_5514 = eq(T_5512, UInt<1>("h0")) - node T_5515 = or(T_5511, T_5514) - io.status.sd <= T_5515 - node T_5516 = or(io.exception, csr_xcpt) - when T_5516 : - reg_mstatus.ie <= UInt<1>("h0") - reg_mstatus.prv <= UInt<2>("h3") - reg_mstatus.mprv <= UInt<1>("h0") - reg_mstatus.prv1 <= reg_mstatus.prv - reg_mstatus.ie1 <= reg_mstatus.ie - reg_mstatus.prv2 <= reg_mstatus.prv1 - reg_mstatus.ie2 <= reg_mstatus.ie1 - node T_5520 = not(io.pc) - node T_5522 = or(T_5520, UInt<2>("h3")) - node T_5523 = not(T_5522) - reg_mepc <= T_5523 - reg_mcause <= io.cause - when csr_xcpt : - reg_mcause <= UInt<2>("h2") - when insn_break : - reg_mcause <= UInt<2>("h3") - skip - when insn_call : - node T_5527 = add(reg_mstatus.prv, UInt<4>("h8")) - node T_5528 = tail(T_5527, 1) - reg_mcause <= T_5528 - skip - skip - reg_mbadaddr <= io.pc - node T_5530 = eq(io.cause, UInt<3>("h5")) - node T_5532 = eq(io.cause, UInt<3>("h4")) - node T_5533 = or(T_5530, T_5532) - node T_5535 = eq(io.cause, UInt<3>("h7")) - node T_5536 = or(T_5533, T_5535) - node T_5538 = eq(io.cause, UInt<3>("h6")) - node T_5539 = or(T_5536, T_5538) - when T_5539 : - node T_5540 = bits(io.rw.wdata, 63, 39) - node T_5541 = bits(io.rw.wdata, 38, 0) - node T_5542 = asSInt(T_5541) - node T_5544 = lt(T_5542, asSInt(UInt<1>("h0"))) - node T_5545 = not(T_5540) - node T_5547 = eq(T_5545, UInt<1>("h0")) - node T_5549 = neq(T_5540, UInt<1>("h0")) - node T_5550 = mux(T_5544, T_5547, T_5549) - node T_5551 = cat(T_5550, T_5541) - reg_mbadaddr <= T_5551 - skip - skip - when insn_ret : - reg_mstatus.ie <= reg_mstatus.ie1 - reg_mstatus.prv <= reg_mstatus.prv1 - reg_mstatus.prv1 <= reg_mstatus.prv2 - reg_mstatus.ie1 <= reg_mstatus.ie2 - reg_mstatus.prv2 <= UInt<1>("h0") - reg_mstatus.ie2 <= UInt<1>("h1") - skip - when insn_redirect_trap : - reg_mstatus.prv <= UInt<1>("h1") - reg_sbadaddr <= reg_mbadaddr - reg_scause <= reg_mcause - reg_sepc <= reg_mepc - skip - node T_5556 = cat(UInt<1>("h0"), insn_redirect_trap) - node T_5557 = add(insn_ret, T_5556) - node T_5558 = tail(T_5557, 1) - node T_5561 = cat(UInt<1>("h0"), csr_xcpt) - node T_5562 = add(io.exception, T_5561) - node T_5563 = tail(T_5562, 1) - node T_5564 = cat(UInt<1>("h0"), T_5563) - node T_5565 = add(T_5558, T_5564) - node T_5566 = tail(T_5565, 1) - node T_5568 = leq(T_5566, UInt<1>("h1")) - node T_5570 = eq(reset, UInt<1>("h0")) - when T_5570 : - node T_5572 = eq(T_5568, UInt<1>("h0")) - when T_5572 : - node T_5574 = eq(reset, UInt<1>("h0")) - when T_5574 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_5575 = geq(reg_time, reg_mtimecmp) - when T_5575 : - reg_mip.mtip <= UInt<1>("h1") - skip - io.time <= T_4615 - io.csr_stall <= reg_wfi - node T_5578 = eq(host_csr_bits.rw, UInt<1>("h0")) - node T_5579 = and(host_csr_req_fire, T_5578) - node T_5580 = and(T_5579, T_5277) - when T_5580 : - reg_tohost <= UInt<1>("h0") - skip - node T_5583 = mux(T_5223, reg_fflags, UInt<1>("h0")) - node T_5585 = mux(T_5225, reg_frm, UInt<1>("h0")) - node T_5587 = mux(T_5227, T_4990, UInt<1>("h0")) - node T_5589 = mux(T_5229, T_4615, UInt<1>("h0")) - node T_5591 = mux(T_5231, T_4615, UInt<1>("h0")) - node T_5593 = mux(T_5233, reg_time, UInt<1>("h0")) - node T_5595 = mux(T_5235, reg_time, UInt<1>("h0")) - node T_5597 = mux(T_5237, reg_time, UInt<1>("h0")) - node T_5599 = mux(T_5239, reg_time, UInt<1>("h0")) - node T_5601 = mux(T_5241, reg_time, UInt<1>("h0")) - node T_5603 = mux(T_5243, UInt<64>("h8000000000041129"), UInt<1>("h0")) - node T_5605 = mux(T_5245, UInt<1>("h1"), UInt<1>("h0")) - node T_5607 = mux(T_5247, read_mstatus, UInt<1>("h0")) - node T_5609 = mux(T_5249, UInt<1>("h0"), UInt<1>("h0")) - node T_5611 = mux(T_5251, UInt<1>("h0"), UInt<1>("h0")) - node T_5613 = mux(T_5253, UInt<9>("h100"), UInt<1>("h0")) - node T_5615 = mux(T_5255, UInt<31>("h40000000"), UInt<1>("h0")) - node T_5617 = mux(T_5257, UInt<1>("h0"), UInt<1>("h0")) - node T_5619 = mux(T_5259, T_5004, UInt<1>("h0")) - node T_5621 = mux(T_5261, T_5011, UInt<1>("h0")) - node T_5623 = mux(T_5263, reg_mscratch, UInt<1>("h0")) - node T_5625 = mux(T_5265, T_5016, UInt<1>("h0")) - node T_5627 = mux(T_5267, T_5021, UInt<1>("h0")) - node T_5629 = mux(T_5269, reg_mcause, UInt<1>("h0")) - node T_5631 = mux(T_5271, reg_mtimecmp, UInt<1>("h0")) - node T_5633 = mux(T_5273, io.host.id, UInt<1>("h0")) - node T_5635 = shl(reg_stats, 0) - node T_5636 = mux(T_5275, T_5635, UInt<1>("h0")) - node T_5638 = mux(T_5277, reg_tohost, UInt<1>("h0")) - node T_5640 = mux(T_5279, reg_fromhost, UInt<1>("h0")) - node T_5642 = mux(T_5281, T_4598, UInt<1>("h0")) - node T_5644 = mux(T_5283, T_4598, UInt<1>("h0")) - node T_5646 = mux(T_5285, T_4631, UInt<1>("h0")) - node T_5648 = mux(T_5287, T_4647, UInt<1>("h0")) - node T_5650 = mux(T_5289, T_4663, UInt<1>("h0")) - node T_5652 = mux(T_5291, T_4679, UInt<1>("h0")) - node T_5654 = mux(T_5293, T_4695, UInt<1>("h0")) - node T_5656 = mux(T_5295, T_4711, UInt<1>("h0")) - node T_5658 = mux(T_5297, T_4727, UInt<1>("h0")) - node T_5660 = mux(T_5299, T_4743, UInt<1>("h0")) - node T_5662 = mux(T_5301, T_4759, UInt<1>("h0")) - node T_5664 = mux(T_5303, T_4775, UInt<1>("h0")) - node T_5666 = mux(T_5305, T_4791, UInt<1>("h0")) - node T_5668 = mux(T_5307, T_4807, UInt<1>("h0")) - node T_5670 = mux(T_5309, T_4823, UInt<1>("h0")) - node T_5672 = mux(T_5311, T_4839, UInt<1>("h0")) - node T_5674 = mux(T_5313, T_4855, UInt<1>("h0")) - node T_5676 = mux(T_5315, T_4871, UInt<1>("h0")) - node T_5678 = mux(T_5317, T_5190, UInt<1>("h0")) - node T_5680 = mux(T_5319, T_5197, UInt<1>("h0")) - node T_5682 = mux(T_5321, T_5204, UInt<1>("h0")) - node T_5684 = mux(T_5323, reg_sscratch, UInt<1>("h0")) - node T_5686 = mux(T_5325, reg_scause, UInt<1>("h0")) - node T_5688 = mux(T_5327, T_5209, UInt<1>("h0")) - node T_5690 = mux(T_5329, reg_sptbr, UInt<1>("h0")) - node T_5692 = mux(T_5331, UInt<1>("h0"), UInt<1>("h0")) - node T_5694 = mux(T_5333, T_5215, UInt<1>("h0")) - node T_5696 = mux(T_5335, T_5220, UInt<1>("h0")) - node T_5698 = or(T_5583, T_5585) - node T_5699 = or(T_5698, T_5587) - node T_5700 = or(T_5699, T_5589) - node T_5701 = or(T_5700, T_5591) - node T_5702 = or(T_5701, T_5593) - node T_5703 = or(T_5702, T_5595) - node T_5704 = or(T_5703, T_5597) - node T_5705 = or(T_5704, T_5599) - node T_5706 = or(T_5705, T_5601) - node T_5707 = or(T_5706, T_5603) - node T_5708 = or(T_5707, T_5605) - node T_5709 = or(T_5708, T_5607) - node T_5710 = or(T_5709, T_5609) - node T_5711 = or(T_5710, T_5611) - node T_5712 = or(T_5711, T_5613) - node T_5713 = or(T_5712, T_5615) - node T_5714 = or(T_5713, T_5617) - node T_5715 = or(T_5714, T_5619) - node T_5716 = or(T_5715, T_5621) - node T_5717 = or(T_5716, T_5623) - node T_5718 = or(T_5717, T_5625) - node T_5719 = or(T_5718, T_5627) - node T_5720 = or(T_5719, T_5629) - node T_5721 = or(T_5720, T_5631) - node T_5722 = or(T_5721, T_5633) - node T_5723 = or(T_5722, T_5636) - node T_5724 = or(T_5723, T_5638) - node T_5725 = or(T_5724, T_5640) - node T_5726 = or(T_5725, T_5642) - node T_5727 = or(T_5726, T_5644) - node T_5728 = or(T_5727, T_5646) - node T_5729 = or(T_5728, T_5648) - node T_5730 = or(T_5729, T_5650) - node T_5731 = or(T_5730, T_5652) - node T_5732 = or(T_5731, T_5654) - node T_5733 = or(T_5732, T_5656) - node T_5734 = or(T_5733, T_5658) - node T_5735 = or(T_5734, T_5660) - node T_5736 = or(T_5735, T_5662) - node T_5737 = or(T_5736, T_5664) - node T_5738 = or(T_5737, T_5666) - node T_5739 = or(T_5738, T_5668) - node T_5740 = or(T_5739, T_5670) - node T_5741 = or(T_5740, T_5672) - node T_5742 = or(T_5741, T_5674) - node T_5743 = or(T_5742, T_5676) - node T_5744 = or(T_5743, T_5678) - node T_5745 = or(T_5744, T_5680) - node T_5746 = or(T_5745, T_5682) - node T_5747 = or(T_5746, T_5684) - node T_5748 = or(T_5747, T_5686) - node T_5749 = or(T_5748, T_5688) - node T_5750 = or(T_5749, T_5690) - node T_5751 = or(T_5750, T_5692) - node T_5752 = or(T_5751, T_5694) - node T_5753 = or(T_5752, T_5696) - wire T_5754 : UInt<64> - T_5754 is invalid - T_5754 <= T_5753 - io.rw.rdata <= T_5754 - io.fcsr_rm <= reg_frm - when io.fcsr_flags.valid : - node T_5755 = or(reg_fflags, io.fcsr_flags.bits) - reg_fflags <= T_5755 - skip - when wen : - when T_5247 : - wire T_5790 : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} - T_5790 is invalid - node T_5807 = bits(wdata, 0, 0) - T_5790.ie <= T_5807 - node T_5808 = bits(wdata, 2, 1) - T_5790.prv <= T_5808 - node T_5809 = bits(wdata, 3, 3) - T_5790.ie1 <= T_5809 - node T_5810 = bits(wdata, 5, 4) - T_5790.prv1 <= T_5810 - node T_5811 = bits(wdata, 6, 6) - T_5790.ie2 <= T_5811 - node T_5812 = bits(wdata, 8, 7) - T_5790.prv2 <= T_5812 - node T_5813 = bits(wdata, 9, 9) - T_5790.ie3 <= T_5813 - node T_5814 = bits(wdata, 11, 10) - T_5790.prv3 <= T_5814 - node T_5815 = bits(wdata, 13, 12) - T_5790.fs <= T_5815 - node T_5816 = bits(wdata, 15, 14) - T_5790.xs <= T_5816 - node T_5817 = bits(wdata, 16, 16) - T_5790.mprv <= T_5817 - node T_5818 = bits(wdata, 21, 17) - T_5790.vm <= T_5818 - node T_5819 = bits(wdata, 30, 22) - T_5790.zero1 <= T_5819 - node T_5820 = bits(wdata, 31, 31) - T_5790.sd_rv32 <= T_5820 - node T_5821 = bits(wdata, 62, 32) - T_5790.zero2 <= T_5821 - node T_5822 = bits(wdata, 63, 63) - T_5790.sd <= T_5822 - reg_mstatus.ie <= T_5790.ie - reg_mstatus.ie1 <= T_5790.ie1 - wire T_5827 : UInt<2>[3] - T_5827[0] <= UInt<2>("h3") - T_5827[1] <= UInt<1>("h0") - T_5827[2] <= UInt<1>("h1") - reg_mstatus.mprv <= T_5790.mprv - node T_5832 = eq(T_5827[0], T_5790.prv) - node T_5833 = eq(T_5827[1], T_5790.prv) - node T_5834 = eq(T_5827[2], T_5790.prv) - node T_5836 = or(UInt<1>("h0"), T_5832) - node T_5837 = or(T_5836, T_5833) - node T_5838 = or(T_5837, T_5834) - when T_5838 : - reg_mstatus.prv <= T_5790.prv - skip - node T_5839 = eq(T_5827[0], T_5790.prv1) - node T_5840 = eq(T_5827[1], T_5790.prv1) - node T_5841 = eq(T_5827[2], T_5790.prv1) - node T_5843 = or(UInt<1>("h0"), T_5839) - node T_5844 = or(T_5843, T_5840) - node T_5845 = or(T_5844, T_5841) - when T_5845 : - reg_mstatus.prv1 <= T_5790.prv1 - skip - node T_5846 = eq(T_5827[0], T_5790.prv2) - node T_5847 = eq(T_5827[1], T_5790.prv2) - node T_5848 = eq(T_5827[2], T_5790.prv2) - node T_5850 = or(UInt<1>("h0"), T_5846) - node T_5851 = or(T_5850, T_5847) - node T_5852 = or(T_5851, T_5848) - when T_5852 : - reg_mstatus.prv2 <= T_5790.prv2 - skip - reg_mstatus.ie2 <= T_5790.ie2 - node T_5854 = eq(T_5790.vm, UInt<1>("h0")) - when T_5854 : - reg_mstatus.vm <= UInt<1>("h0") - skip - node T_5857 = eq(T_5790.vm, UInt<4>("h9")) - when T_5857 : - reg_mstatus.vm <= UInt<4>("h9") - skip - reg_mstatus.fs <= T_5790.fs - skip - when T_5259 : - wire T_5877 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5877 is invalid - node T_5886 = bits(wdata, 0, 0) - T_5877.usip <= T_5886 - node T_5887 = bits(wdata, 1, 1) - T_5877.ssip <= T_5887 - node T_5888 = bits(wdata, 2, 2) - T_5877.hsip <= T_5888 - node T_5889 = bits(wdata, 3, 3) - T_5877.msip <= T_5889 - node T_5890 = bits(wdata, 4, 4) - T_5877.utip <= T_5890 - node T_5891 = bits(wdata, 5, 5) - T_5877.stip <= T_5891 - node T_5892 = bits(wdata, 6, 6) - T_5877.htip <= T_5892 - node T_5893 = bits(wdata, 7, 7) - T_5877.mtip <= T_5893 - reg_mip.ssip <= T_5877.ssip - reg_mip.stip <= T_5877.stip - reg_mip.msip <= T_5877.msip - skip - when T_5257 : - node T_5894 = bits(wdata, 0, 0) - reg_mip.msip <= T_5894 - skip - when T_5261 : - wire T_5913 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5913 is invalid - node T_5922 = bits(wdata, 0, 0) - T_5913.usip <= T_5922 - node T_5923 = bits(wdata, 1, 1) - T_5913.ssip <= T_5923 - node T_5924 = bits(wdata, 2, 2) - T_5913.hsip <= T_5924 - node T_5925 = bits(wdata, 3, 3) - T_5913.msip <= T_5925 - node T_5926 = bits(wdata, 4, 4) - T_5913.utip <= T_5926 - node T_5927 = bits(wdata, 5, 5) - T_5913.stip <= T_5927 - node T_5928 = bits(wdata, 6, 6) - T_5913.htip <= T_5928 - node T_5929 = bits(wdata, 7, 7) - T_5913.mtip <= T_5929 - reg_mie.ssip <= T_5913.ssip - reg_mie.stip <= T_5913.stip - reg_mie.msip <= T_5913.msip - reg_mie.mtip <= T_5913.mtip - skip - when T_5223 : - reg_fflags <= wdata - skip - when T_5225 : - reg_frm <= wdata - skip - when T_5227 : - reg_fflags <= wdata - node T_5930 = shr(wdata, 5) - reg_frm <= T_5930 - skip - when T_5265 : - node T_5931 = not(wdata) - node T_5933 = or(T_5931, UInt<2>("h3")) - node T_5934 = not(T_5933) - reg_mepc <= T_5934 - skip - when T_5263 : - reg_mscratch <= wdata - skip - when T_5269 : - node T_5936 = and(wdata, UInt<64>("h800000000000001f")) - reg_mcause <= T_5936 - skip - when T_5267 : - node T_5937 = bits(wdata, 39, 0) - reg_mbadaddr <= T_5937 - skip - when T_5283 : - node T_5938 = bits(wdata, 5, 0) - T_4584 <= T_5938 - node T_5939 = bits(wdata, 63, 6) - T_4592 <= T_5939 - skip - when T_5271 : - reg_mtimecmp <= wdata - reg_mip.mtip <= UInt<1>("h0") - skip - when T_5241 : - reg_time <= wdata - skip - when T_5279 : - node T_5942 = eq(reg_fromhost, UInt<1>("h0")) - node T_5944 = eq(host_csr_req_fire, UInt<1>("h0")) - node T_5945 = or(T_5942, T_5944) - when T_5945 : - reg_fromhost <= wdata - skip - skip - when T_5277 : - node T_5947 = eq(reg_tohost, UInt<1>("h0")) - node T_5948 = or(T_5947, host_csr_req_fire) - when T_5948 : - reg_tohost <= wdata - skip - skip - when T_5275 : - node T_5949 = bits(wdata, 0, 0) - reg_stats <= T_5949 - skip - when T_5317 : - wire T_5976 : { sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5976 is invalid - node T_5989 = bits(wdata, 0, 0) - T_5976.ie <= T_5989 - node T_5990 = bits(wdata, 2, 1) - T_5976.zero1 <= T_5990 - node T_5991 = bits(wdata, 3, 3) - T_5976.pie <= T_5991 - node T_5992 = bits(wdata, 4, 4) - T_5976.ps <= T_5992 - node T_5993 = bits(wdata, 11, 5) - T_5976.zero2 <= T_5993 - node T_5994 = bits(wdata, 13, 12) - T_5976.fs <= T_5994 - node T_5995 = bits(wdata, 15, 14) - T_5976.xs <= T_5995 - node T_5996 = bits(wdata, 16, 16) - T_5976.mprv <= T_5996 - node T_5997 = bits(wdata, 30, 17) - T_5976.zero3 <= T_5997 - node T_5998 = bits(wdata, 31, 31) - T_5976.sd_rv32 <= T_5998 - node T_5999 = bits(wdata, 62, 32) - T_5976.zero4 <= T_5999 - node T_6000 = bits(wdata, 63, 63) - T_5976.sd <= T_6000 - reg_mstatus.ie <= T_5976.ie - reg_mstatus.ie1 <= T_5976.pie - node T_6003 = mux(T_5976.ps, UInt<1>("h1"), UInt<1>("h0")) - reg_mstatus.prv1 <= T_6003 - reg_mstatus.mprv <= T_5976.mprv - reg_mstatus.fs <= T_5976.fs - skip - when T_5319 : - wire T_6022 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6022 is invalid - node T_6031 = bits(wdata, 0, 0) - T_6022.usip <= T_6031 - node T_6032 = bits(wdata, 1, 1) - T_6022.ssip <= T_6032 - node T_6033 = bits(wdata, 2, 2) - T_6022.hsip <= T_6033 - node T_6034 = bits(wdata, 3, 3) - T_6022.msip <= T_6034 - node T_6035 = bits(wdata, 4, 4) - T_6022.utip <= T_6035 - node T_6036 = bits(wdata, 5, 5) - T_6022.stip <= T_6036 - node T_6037 = bits(wdata, 6, 6) - T_6022.htip <= T_6037 - node T_6038 = bits(wdata, 7, 7) - T_6022.mtip <= T_6038 - reg_mip.ssip <= T_6022.ssip - skip - when T_5321 : - wire T_6057 : { mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6057 is invalid - node T_6066 = bits(wdata, 0, 0) - T_6057.usip <= T_6066 - node T_6067 = bits(wdata, 1, 1) - T_6057.ssip <= T_6067 - node T_6068 = bits(wdata, 2, 2) - T_6057.hsip <= T_6068 - node T_6069 = bits(wdata, 3, 3) - T_6057.msip <= T_6069 - node T_6070 = bits(wdata, 4, 4) - T_6057.utip <= T_6070 - node T_6071 = bits(wdata, 5, 5) - T_6057.stip <= T_6071 - node T_6072 = bits(wdata, 6, 6) - T_6057.htip <= T_6072 - node T_6073 = bits(wdata, 7, 7) - T_6057.mtip <= T_6073 - reg_mie.ssip <= T_6057.ssip - reg_mie.stip <= T_6057.stip - skip - when T_5323 : - reg_sscratch <= wdata - skip - when T_5329 : - node T_6074 = bits(wdata, 31, 12) - node T_6076 = cat(T_6074, UInt<12>("h0")) - reg_sptbr <= T_6076 - skip - when T_5333 : - node T_6077 = not(wdata) - node T_6079 = or(T_6077, UInt<2>("h3")) - node T_6080 = not(T_6079) - reg_sepc <= T_6080 - skip - when T_5335 : - node T_6081 = not(wdata) - node T_6083 = or(T_6081, UInt<2>("h3")) - node T_6084 = not(T_6083) - reg_stvec <= T_6084 - skip - skip - when reset : - reg_mstatus.zero1 <= UInt<1>("h0") - reg_mstatus.zero2 <= UInt<1>("h0") - reg_mstatus.ie <= UInt<1>("h0") - reg_mstatus.prv <= UInt<2>("h3") - reg_mstatus.ie1 <= UInt<1>("h0") - reg_mstatus.prv1 <= UInt<2>("h3") - reg_mstatus.ie2 <= UInt<1>("h0") - reg_mstatus.prv2 <= UInt<1>("h0") - reg_mstatus.ie3 <= UInt<1>("h0") - reg_mstatus.prv3 <= UInt<1>("h0") - reg_mstatus.mprv <= UInt<1>("h0") - reg_mstatus.vm <= UInt<1>("h0") - reg_mstatus.fs <= UInt<1>("h0") - reg_mstatus.xs <= UInt<1>("h0") - reg_mstatus.sd_rv32 <= UInt<1>("h0") - reg_mstatus.sd <= UInt<1>("h0") - skip - module ALU : - input clk : Clock - input reset : UInt<1> - output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} - io is invalid - node T_11 = bits(io.fn, 3, 3) - node T_12 = not(io.in2) - node in2_inv = mux(T_11, T_12, io.in2) - node in1_xor_in2 = xor(io.in1, in2_inv) - node T_15 = add(io.in1, in2_inv) - node T_16 = tail(T_15, 1) - node T_17 = bits(io.fn, 3, 3) - node T_18 = add(T_16, T_17) - node T_19 = tail(T_18, 1) - io.adder_out <= T_19 - node T_20 = bits(io.fn, 0, 0) - node T_21 = bits(io.fn, 3, 3) - node T_23 = eq(T_21, UInt<1>("h0")) - node T_25 = eq(in1_xor_in2, UInt<1>("h0")) - node T_26 = bits(io.in1, 63, 63) - node T_27 = bits(io.in2, 63, 63) - node T_28 = eq(T_26, T_27) - node T_29 = bits(io.adder_out, 63, 63) - node T_30 = bits(io.fn, 1, 1) - node T_31 = bits(io.in2, 63, 63) - node T_32 = bits(io.in1, 63, 63) - node T_33 = mux(T_30, T_31, T_32) - node T_34 = mux(T_28, T_29, T_33) - node T_35 = mux(T_23, T_25, T_34) - node T_36 = xor(T_20, T_35) - io.cmp_out <= T_36 - node T_37 = bits(io.fn, 3, 3) - node T_38 = bits(io.in1, 31, 31) - node T_39 = and(T_37, T_38) - node T_41 = sub(UInt<32>("h0"), T_39) - node T_42 = tail(T_41, 1) - node T_45 = and(io.dw, UInt<1>("h1")) - node T_46 = eq(UInt<1>("h1"), T_45) - node T_47 = bits(io.in1, 63, 32) - node T_48 = mux(T_46, T_47, T_42) - node T_49 = bits(io.in2, 5, 5) - node T_52 = and(io.dw, UInt<1>("h1")) - node T_53 = eq(UInt<1>("h1"), T_52) - node T_54 = and(T_49, T_53) - node T_55 = bits(io.in2, 4, 0) - node shamt = cat(T_54, T_55) - node T_57 = bits(io.in1, 31, 0) - node shin_r = cat(T_48, T_57) - node T_59 = eq(io.fn, UInt<3>("h5")) - node T_60 = eq(io.fn, UInt<4>("hb")) - node T_61 = or(T_59, T_60) - node T_64 = shl(UInt<32>("hffffffff"), 32) - node T_65 = xor(UInt<64>("hffffffffffffffff"), T_64) - node T_66 = shr(shin_r, 32) - node T_67 = and(T_66, T_65) - node T_68 = bits(shin_r, 31, 0) - node T_69 = shl(T_68, 32) - node T_70 = not(T_65) - node T_71 = and(T_69, T_70) - node T_72 = or(T_67, T_71) - node T_73 = bits(T_65, 47, 0) - node T_74 = shl(T_73, 16) - node T_75 = xor(T_65, T_74) - node T_76 = shr(T_72, 16) - node T_77 = and(T_76, T_75) - node T_78 = bits(T_72, 47, 0) - node T_79 = shl(T_78, 16) - node T_80 = not(T_75) - node T_81 = and(T_79, T_80) - node T_82 = or(T_77, T_81) - node T_83 = bits(T_75, 55, 0) - node T_84 = shl(T_83, 8) - node T_85 = xor(T_75, T_84) - node T_86 = shr(T_82, 8) - node T_87 = and(T_86, T_85) - node T_88 = bits(T_82, 55, 0) - node T_89 = shl(T_88, 8) - node T_90 = not(T_85) - node T_91 = and(T_89, T_90) - node T_92 = or(T_87, T_91) - node T_93 = bits(T_85, 59, 0) - node T_94 = shl(T_93, 4) - node T_95 = xor(T_85, T_94) - node T_96 = shr(T_92, 4) - node T_97 = and(T_96, T_95) - node T_98 = bits(T_92, 59, 0) - node T_99 = shl(T_98, 4) - node T_100 = not(T_95) - node T_101 = and(T_99, T_100) - node T_102 = or(T_97, T_101) - node T_103 = bits(T_95, 61, 0) - node T_104 = shl(T_103, 2) - node T_105 = xor(T_95, T_104) - node T_106 = shr(T_102, 2) - node T_107 = and(T_106, T_105) - node T_108 = bits(T_102, 61, 0) - node T_109 = shl(T_108, 2) - node T_110 = not(T_105) - node T_111 = and(T_109, T_110) - node T_112 = or(T_107, T_111) - node T_113 = bits(T_105, 62, 0) - node T_114 = shl(T_113, 1) - node T_115 = xor(T_105, T_114) - node T_116 = shr(T_112, 1) - node T_117 = and(T_116, T_115) - node T_118 = bits(T_112, 62, 0) - node T_119 = shl(T_118, 1) - node T_120 = not(T_115) - node T_121 = and(T_119, T_120) - node T_122 = or(T_117, T_121) - node shin = mux(T_61, shin_r, T_122) - node T_124 = bits(io.fn, 3, 3) - node T_125 = bits(shin, 63, 63) - node T_126 = and(T_124, T_125) - node T_127 = cat(T_126, shin) - node T_128 = asSInt(T_127) - node T_129 = dshr(T_128, shamt) - node shout_r = bits(T_129, 63, 0) - node T_133 = shl(UInt<32>("hffffffff"), 32) - node T_134 = xor(UInt<64>("hffffffffffffffff"), T_133) - node T_135 = shr(shout_r, 32) - node T_136 = and(T_135, T_134) - node T_137 = bits(shout_r, 31, 0) - node T_138 = shl(T_137, 32) - node T_139 = not(T_134) - node T_140 = and(T_138, T_139) - node T_141 = or(T_136, T_140) - node T_142 = bits(T_134, 47, 0) - node T_143 = shl(T_142, 16) - node T_144 = xor(T_134, T_143) - node T_145 = shr(T_141, 16) - node T_146 = and(T_145, T_144) - node T_147 = bits(T_141, 47, 0) - node T_148 = shl(T_147, 16) - node T_149 = not(T_144) - node T_150 = and(T_148, T_149) - node T_151 = or(T_146, T_150) - node T_152 = bits(T_144, 55, 0) - node T_153 = shl(T_152, 8) - node T_154 = xor(T_144, T_153) - node T_155 = shr(T_151, 8) - node T_156 = and(T_155, T_154) - node T_157 = bits(T_151, 55, 0) - node T_158 = shl(T_157, 8) - node T_159 = not(T_154) - node T_160 = and(T_158, T_159) - node T_161 = or(T_156, T_160) - node T_162 = bits(T_154, 59, 0) - node T_163 = shl(T_162, 4) - node T_164 = xor(T_154, T_163) - node T_165 = shr(T_161, 4) - node T_166 = and(T_165, T_164) - node T_167 = bits(T_161, 59, 0) - node T_168 = shl(T_167, 4) - node T_169 = not(T_164) - node T_170 = and(T_168, T_169) - node T_171 = or(T_166, T_170) - node T_172 = bits(T_164, 61, 0) - node T_173 = shl(T_172, 2) - node T_174 = xor(T_164, T_173) - node T_175 = shr(T_171, 2) - node T_176 = and(T_175, T_174) - node T_177 = bits(T_171, 61, 0) - node T_178 = shl(T_177, 2) - node T_179 = not(T_174) - node T_180 = and(T_178, T_179) - node T_181 = or(T_176, T_180) - node T_182 = bits(T_174, 62, 0) - node T_183 = shl(T_182, 1) - node T_184 = xor(T_174, T_183) - node T_185 = shr(T_181, 1) - node T_186 = and(T_185, T_184) - node T_187 = bits(T_181, 62, 0) - node T_188 = shl(T_187, 1) - node T_189 = not(T_184) - node T_190 = and(T_188, T_189) - node shout_l = or(T_186, T_190) - node T_192 = eq(io.fn, UInt<3>("h5")) - node T_193 = eq(io.fn, UInt<4>("hb")) - node T_194 = or(T_192, T_193) - node T_196 = mux(T_194, shout_r, UInt<1>("h0")) - node T_197 = eq(io.fn, UInt<1>("h1")) - node T_199 = mux(T_197, shout_l, UInt<1>("h0")) - node shout = or(T_196, T_199) - node T_201 = eq(io.fn, UInt<3>("h4")) - node T_202 = eq(io.fn, UInt<3>("h6")) - node T_203 = or(T_201, T_202) - node T_205 = mux(T_203, in1_xor_in2, UInt<1>("h0")) - node T_206 = eq(io.fn, UInt<3>("h6")) - node T_207 = eq(io.fn, UInt<3>("h7")) - node T_208 = or(T_206, T_207) - node T_209 = and(io.in1, io.in2) - node T_211 = mux(T_208, T_209, UInt<1>("h0")) - node logic = or(T_205, T_211) - node T_213 = eq(io.fn, UInt<2>("h2")) - node T_214 = eq(io.fn, UInt<2>("h3")) - node T_215 = or(T_213, T_214) - node T_216 = geq(io.fn, UInt<4>("hc")) - node T_217 = or(T_215, T_216) - node T_218 = and(T_217, io.cmp_out) - node T_219 = or(T_218, logic) - node shift_logic = or(T_219, shout) - node T_221 = eq(io.fn, UInt<1>("h0")) - node T_222 = eq(io.fn, UInt<4>("ha")) - node T_223 = or(T_221, T_222) - node out = mux(T_223, io.adder_out, shift_logic) - io.out <= out - node T_227 = and(io.dw, UInt<1>("h1")) - node T_228 = eq(UInt<1>("h0"), T_227) - when T_228 : - node T_229 = bits(out, 31, 31) - node T_231 = sub(UInt<32>("h0"), T_229) - node T_232 = tail(T_231, 1) - node T_233 = bits(out, 31, 0) - node T_234 = cat(T_232, T_233) - io.out <= T_234 - skip - module MulDiv : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg req : { fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk with : - reset => (UInt<1>("h0"), req) - reg count : UInt<7>, clk with : - reset => (UInt<1>("h0"), count) - reg neg_out : UInt<1>, clk with : - reset => (UInt<1>("h0"), neg_out) - reg isMul : UInt<1>, clk with : - reset => (UInt<1>("h0"), isMul) - reg isHi : UInt<1>, clk with : - reset => (UInt<1>("h0"), isHi) - reg divisor : UInt<65>, clk with : - reset => (UInt<1>("h0"), divisor) - reg remainder : UInt<130>, clk with : - reset => (UInt<1>("h0"), remainder) - node T_81 = and(io.req.bits.fn, UInt<4>("h4")) - node T_83 = eq(T_81, UInt<4>("h0")) - node T_85 = and(io.req.bits.fn, UInt<4>("h8")) - node T_87 = eq(T_85, UInt<4>("h8")) - node T_89 = or(UInt<1>("h0"), T_83) - node T_90 = or(T_89, T_87) - node T_92 = and(io.req.bits.fn, UInt<4>("h5")) - node T_94 = eq(T_92, UInt<4>("h1")) - node T_96 = and(io.req.bits.fn, UInt<4>("h2")) - node T_98 = eq(T_96, UInt<4>("h2")) - node T_100 = or(UInt<1>("h0"), T_94) - node T_101 = or(T_100, T_98) - node T_102 = or(T_101, T_87) - node T_104 = and(io.req.bits.fn, UInt<4>("h9")) - node T_106 = eq(T_104, UInt<4>("h0")) - node T_108 = and(io.req.bits.fn, UInt<4>("h3")) - node T_110 = eq(T_108, UInt<4>("h0")) - node T_112 = or(UInt<1>("h0"), T_106) - node T_113 = or(T_112, T_83) - node T_114 = or(T_113, T_110) - node T_116 = or(UInt<1>("h0"), T_106) - node T_117 = or(T_116, T_83) - node cmdMul = bits(T_90, 0, 0) - node cmdHi = bits(T_102, 0, 0) - node lhsSigned = bits(T_114, 0, 0) - node rhsSigned = bits(T_117, 0, 0) - node T_124 = and(io.req.bits.dw, UInt<1>("h1")) - node T_125 = eq(UInt<1>("h1"), T_124) - node T_126 = bits(io.req.bits.in1, 63, 63) - node T_127 = bits(io.req.bits.in1, 31, 31) - node T_128 = mux(T_125, T_126, T_127) - node lhs_sign = and(lhsSigned, T_128) - node T_132 = and(io.req.bits.dw, UInt<1>("h1")) - node T_133 = eq(UInt<1>("h1"), T_132) - node T_134 = bits(io.req.bits.in1, 63, 32) - node T_136 = sub(UInt<32>("h0"), lhs_sign) - node T_137 = tail(T_136, 1) - node T_138 = mux(T_133, T_134, T_137) - node T_139 = bits(io.req.bits.in1, 31, 0) - node lhs_in = cat(T_138, T_139) - node T_143 = and(io.req.bits.dw, UInt<1>("h1")) - node T_144 = eq(UInt<1>("h1"), T_143) - node T_145 = bits(io.req.bits.in2, 63, 63) - node T_146 = bits(io.req.bits.in2, 31, 31) - node T_147 = mux(T_144, T_145, T_146) - node rhs_sign = and(rhsSigned, T_147) - node T_151 = and(io.req.bits.dw, UInt<1>("h1")) - node T_152 = eq(UInt<1>("h1"), T_151) - node T_153 = bits(io.req.bits.in2, 63, 32) - node T_155 = sub(UInt<32>("h0"), rhs_sign) - node T_156 = tail(T_155, 1) - node T_157 = mux(T_152, T_153, T_156) - node T_158 = bits(io.req.bits.in2, 31, 0) - node rhs_in = cat(T_157, T_158) - node T_160 = bits(remainder, 128, 64) - node T_161 = bits(divisor, 64, 0) - node T_162 = sub(T_160, T_161) - node subtractor = tail(T_162, 1) - node less = bits(subtractor, 64, 64) - node T_165 = bits(remainder, 63, 0) - node T_167 = sub(UInt<1>("h0"), T_165) - node negated_remainder = tail(T_167, 1) - node T_169 = eq(state, UInt<1>("h1")) - when T_169 : - node T_170 = bits(remainder, 63, 63) - node T_171 = or(T_170, isMul) - when T_171 : - remainder <= negated_remainder - skip - node T_172 = bits(divisor, 63, 63) - node T_173 = or(T_172, isMul) - when T_173 : - divisor <= subtractor - skip - state <= UInt<2>("h2") - skip - node T_174 = eq(state, UInt<3>("h4")) - when T_174 : - remainder <= negated_remainder - state <= UInt<3>("h5") - skip - node T_175 = eq(state, UInt<2>("h3")) - when T_175 : - node T_176 = bits(remainder, 128, 65) - remainder <= T_176 - node T_177 = mux(neg_out, UInt<3>("h4"), UInt<3>("h5")) - state <= T_177 - skip - node T_178 = eq(state, UInt<2>("h2")) - node T_179 = and(T_178, isMul) - when T_179 : - node T_180 = bits(remainder, 129, 65) - node T_181 = bits(remainder, 63, 0) - node T_182 = cat(T_180, T_181) - node T_183 = bits(T_182, 63, 0) - node T_184 = bits(T_182, 128, 64) - node T_185 = asSInt(T_184) - node T_186 = asSInt(divisor) - node T_187 = bits(T_183, 7, 0) - node T_188 = mul(T_186, T_187) - node T_189 = add(T_188, T_185) - node T_190 = tail(T_189, 1) - node T_191 = asSInt(T_190) - node T_192 = bits(T_183, 63, 8) - node T_193 = asUInt(T_191) - node T_194 = cat(T_193, T_192) - node T_197 = mul(count, UInt<4>("h8")) - node T_198 = bits(T_197, 5, 0) - node T_199 = dshr(asSInt(UInt<65>("h10000000000000000")), T_198) - node T_200 = bits(T_199, 63, 0) - node T_203 = neq(count, UInt<3>("h7")) - node T_204 = and(UInt<1>("h1"), T_203) - node T_206 = neq(count, UInt<1>("h0")) - node T_207 = and(T_204, T_206) - node T_209 = eq(isHi, UInt<1>("h0")) - node T_210 = and(T_207, T_209) - node T_211 = not(T_200) - node T_212 = and(T_183, T_211) - node T_214 = eq(T_212, UInt<1>("h0")) - node T_215 = and(T_210, T_214) - node T_218 = mul(count, UInt<4>("h8")) - node T_219 = sub(UInt<7>("h40"), T_218) - node T_220 = tail(T_219, 1) - node T_221 = bits(T_220, 5, 0) - node T_222 = dshr(T_182, T_221) - node T_223 = bits(T_194, 128, 64) - node T_224 = mux(T_215, T_222, T_194) - node T_225 = bits(T_224, 63, 0) - node T_226 = cat(T_223, T_225) - node T_227 = shr(T_226, 64) - node T_229 = bits(T_226, 63, 0) - node T_230 = cat(UInt<1>("h0"), T_229) - node T_231 = cat(T_227, T_230) - remainder <= T_231 - node T_233 = add(count, UInt<1>("h1")) - node T_234 = tail(T_233, 1) - count <= T_234 - node T_236 = eq(count, UInt<3>("h7")) - node T_237 = or(T_215, T_236) - when T_237 : - node T_238 = mux(isHi, UInt<2>("h3"), UInt<3>("h5")) - state <= T_238 - skip - skip - node T_239 = eq(state, UInt<2>("h2")) - node T_241 = eq(isMul, UInt<1>("h0")) - node T_242 = and(T_239, T_241) - when T_242 : - node T_244 = eq(count, UInt<7>("h40")) - when T_244 : - node T_245 = mux(neg_out, UInt<3>("h4"), UInt<3>("h5")) - node T_246 = mux(isHi, UInt<2>("h3"), T_245) - state <= T_246 - skip - node T_248 = add(count, UInt<1>("h1")) - node T_249 = tail(T_248, 1) - count <= T_249 - node T_250 = bits(remainder, 127, 64) - node T_251 = bits(subtractor, 63, 0) - node T_252 = mux(less, T_250, T_251) - node T_253 = bits(remainder, 63, 0) - node T_255 = eq(less, UInt<1>("h0")) - node T_256 = cat(T_253, T_255) - node T_257 = cat(T_252, T_256) - remainder <= T_257 - node T_258 = bits(divisor, 63, 0) - node T_259 = bits(T_258, 63, 63) - node T_261 = bits(T_258, 62, 62) - node T_263 = bits(T_258, 61, 61) - node T_265 = bits(T_258, 60, 60) - node T_267 = bits(T_258, 59, 59) - node T_269 = bits(T_258, 58, 58) - node T_271 = bits(T_258, 57, 57) - node T_273 = bits(T_258, 56, 56) - node T_275 = bits(T_258, 55, 55) - node T_277 = bits(T_258, 54, 54) - node T_279 = bits(T_258, 53, 53) - node T_281 = bits(T_258, 52, 52) - node T_283 = bits(T_258, 51, 51) - node T_285 = bits(T_258, 50, 50) - node T_287 = bits(T_258, 49, 49) - node T_289 = bits(T_258, 48, 48) - node T_291 = bits(T_258, 47, 47) - node T_293 = bits(T_258, 46, 46) - node T_295 = bits(T_258, 45, 45) - node T_297 = bits(T_258, 44, 44) - node T_299 = bits(T_258, 43, 43) - node T_301 = bits(T_258, 42, 42) - node T_303 = bits(T_258, 41, 41) - node T_305 = bits(T_258, 40, 40) - node T_307 = bits(T_258, 39, 39) - node T_309 = bits(T_258, 38, 38) - node T_311 = bits(T_258, 37, 37) - node T_313 = bits(T_258, 36, 36) - node T_315 = bits(T_258, 35, 35) - node T_317 = bits(T_258, 34, 34) - node T_319 = bits(T_258, 33, 33) - node T_321 = bits(T_258, 32, 32) - node T_323 = bits(T_258, 31, 31) - node T_325 = bits(T_258, 30, 30) - node T_327 = bits(T_258, 29, 29) - node T_329 = bits(T_258, 28, 28) - node T_331 = bits(T_258, 27, 27) - node T_333 = bits(T_258, 26, 26) - node T_335 = bits(T_258, 25, 25) - node T_337 = bits(T_258, 24, 24) - node T_339 = bits(T_258, 23, 23) - node T_341 = bits(T_258, 22, 22) - node T_343 = bits(T_258, 21, 21) - node T_345 = bits(T_258, 20, 20) - node T_347 = bits(T_258, 19, 19) - node T_349 = bits(T_258, 18, 18) - node T_351 = bits(T_258, 17, 17) - node T_353 = bits(T_258, 16, 16) - node T_355 = bits(T_258, 15, 15) - node T_357 = bits(T_258, 14, 14) - node T_359 = bits(T_258, 13, 13) - node T_361 = bits(T_258, 12, 12) - node T_363 = bits(T_258, 11, 11) - node T_365 = bits(T_258, 10, 10) - node T_367 = bits(T_258, 9, 9) - node T_369 = bits(T_258, 8, 8) - node T_371 = bits(T_258, 7, 7) - node T_373 = bits(T_258, 6, 6) - node T_375 = bits(T_258, 5, 5) - node T_377 = bits(T_258, 4, 4) - node T_379 = bits(T_258, 3, 3) - node T_381 = bits(T_258, 2, 2) - node T_383 = bits(T_258, 1, 1) - node T_384 = shl(T_383, 0) - node T_385 = mux(T_381, UInt<2>("h2"), T_384) - node T_386 = mux(T_379, UInt<2>("h3"), T_385) - node T_387 = mux(T_377, UInt<3>("h4"), T_386) - node T_388 = mux(T_375, UInt<3>("h5"), T_387) - node T_389 = mux(T_373, UInt<3>("h6"), T_388) - node T_390 = mux(T_371, UInt<3>("h7"), T_389) - node T_391 = mux(T_369, UInt<4>("h8"), T_390) - node T_392 = mux(T_367, UInt<4>("h9"), T_391) - node T_393 = mux(T_365, UInt<4>("ha"), T_392) - node T_394 = mux(T_363, UInt<4>("hb"), T_393) - node T_395 = mux(T_361, UInt<4>("hc"), T_394) - node T_396 = mux(T_359, UInt<4>("hd"), T_395) - node T_397 = mux(T_357, UInt<4>("he"), T_396) - node T_398 = mux(T_355, UInt<4>("hf"), T_397) - node T_399 = mux(T_353, UInt<5>("h10"), T_398) - node T_400 = mux(T_351, UInt<5>("h11"), T_399) - node T_401 = mux(T_349, UInt<5>("h12"), T_400) - node T_402 = mux(T_347, UInt<5>("h13"), T_401) - node T_403 = mux(T_345, UInt<5>("h14"), T_402) - node T_404 = mux(T_343, UInt<5>("h15"), T_403) - node T_405 = mux(T_341, UInt<5>("h16"), T_404) - node T_406 = mux(T_339, UInt<5>("h17"), T_405) - node T_407 = mux(T_337, UInt<5>("h18"), T_406) - node T_408 = mux(T_335, UInt<5>("h19"), T_407) - node T_409 = mux(T_333, UInt<5>("h1a"), T_408) - node T_410 = mux(T_331, UInt<5>("h1b"), T_409) - node T_411 = mux(T_329, UInt<5>("h1c"), T_410) - node T_412 = mux(T_327, UInt<5>("h1d"), T_411) - node T_413 = mux(T_325, UInt<5>("h1e"), T_412) - node T_414 = mux(T_323, UInt<5>("h1f"), T_413) - node T_415 = mux(T_321, UInt<6>("h20"), T_414) - node T_416 = mux(T_319, UInt<6>("h21"), T_415) - node T_417 = mux(T_317, UInt<6>("h22"), T_416) - node T_418 = mux(T_315, UInt<6>("h23"), T_417) - node T_419 = mux(T_313, UInt<6>("h24"), T_418) - node T_420 = mux(T_311, UInt<6>("h25"), T_419) - node T_421 = mux(T_309, UInt<6>("h26"), T_420) - node T_422 = mux(T_307, UInt<6>("h27"), T_421) - node T_423 = mux(T_305, UInt<6>("h28"), T_422) - node T_424 = mux(T_303, UInt<6>("h29"), T_423) - node T_425 = mux(T_301, UInt<6>("h2a"), T_424) - node T_426 = mux(T_299, UInt<6>("h2b"), T_425) - node T_427 = mux(T_297, UInt<6>("h2c"), T_426) - node T_428 = mux(T_295, UInt<6>("h2d"), T_427) - node T_429 = mux(T_293, UInt<6>("h2e"), T_428) - node T_430 = mux(T_291, UInt<6>("h2f"), T_429) - node T_431 = mux(T_289, UInt<6>("h30"), T_430) - node T_432 = mux(T_287, UInt<6>("h31"), T_431) - node T_433 = mux(T_285, UInt<6>("h32"), T_432) - node T_434 = mux(T_283, UInt<6>("h33"), T_433) - node T_435 = mux(T_281, UInt<6>("h34"), T_434) - node T_436 = mux(T_279, UInt<6>("h35"), T_435) - node T_437 = mux(T_277, UInt<6>("h36"), T_436) - node T_438 = mux(T_275, UInt<6>("h37"), T_437) - node T_439 = mux(T_273, UInt<6>("h38"), T_438) - node T_440 = mux(T_271, UInt<6>("h39"), T_439) - node T_441 = mux(T_269, UInt<6>("h3a"), T_440) - node T_442 = mux(T_267, UInt<6>("h3b"), T_441) - node T_443 = mux(T_265, UInt<6>("h3c"), T_442) - node T_444 = mux(T_263, UInt<6>("h3d"), T_443) - node T_445 = mux(T_261, UInt<6>("h3e"), T_444) - node T_446 = mux(T_259, UInt<6>("h3f"), T_445) - node T_447 = bits(remainder, 63, 0) - node T_448 = bits(T_447, 63, 63) - node T_450 = bits(T_447, 62, 62) - node T_452 = bits(T_447, 61, 61) - node T_454 = bits(T_447, 60, 60) - node T_456 = bits(T_447, 59, 59) - node T_458 = bits(T_447, 58, 58) - node T_460 = bits(T_447, 57, 57) - node T_462 = bits(T_447, 56, 56) - node T_464 = bits(T_447, 55, 55) - node T_466 = bits(T_447, 54, 54) - node T_468 = bits(T_447, 53, 53) - node T_470 = bits(T_447, 52, 52) - node T_472 = bits(T_447, 51, 51) - node T_474 = bits(T_447, 50, 50) - node T_476 = bits(T_447, 49, 49) - node T_478 = bits(T_447, 48, 48) - node T_480 = bits(T_447, 47, 47) - node T_482 = bits(T_447, 46, 46) - node T_484 = bits(T_447, 45, 45) - node T_486 = bits(T_447, 44, 44) - node T_488 = bits(T_447, 43, 43) - node T_490 = bits(T_447, 42, 42) - node T_492 = bits(T_447, 41, 41) - node T_494 = bits(T_447, 40, 40) - node T_496 = bits(T_447, 39, 39) - node T_498 = bits(T_447, 38, 38) - node T_500 = bits(T_447, 37, 37) - node T_502 = bits(T_447, 36, 36) - node T_504 = bits(T_447, 35, 35) - node T_506 = bits(T_447, 34, 34) - node T_508 = bits(T_447, 33, 33) - node T_510 = bits(T_447, 32, 32) - node T_512 = bits(T_447, 31, 31) - node T_514 = bits(T_447, 30, 30) - node T_516 = bits(T_447, 29, 29) - node T_518 = bits(T_447, 28, 28) - node T_520 = bits(T_447, 27, 27) - node T_522 = bits(T_447, 26, 26) - node T_524 = bits(T_447, 25, 25) - node T_526 = bits(T_447, 24, 24) - node T_528 = bits(T_447, 23, 23) - node T_530 = bits(T_447, 22, 22) - node T_532 = bits(T_447, 21, 21) - node T_534 = bits(T_447, 20, 20) - node T_536 = bits(T_447, 19, 19) - node T_538 = bits(T_447, 18, 18) - node T_540 = bits(T_447, 17, 17) - node T_542 = bits(T_447, 16, 16) - node T_544 = bits(T_447, 15, 15) - node T_546 = bits(T_447, 14, 14) - node T_548 = bits(T_447, 13, 13) - node T_550 = bits(T_447, 12, 12) - node T_552 = bits(T_447, 11, 11) - node T_554 = bits(T_447, 10, 10) - node T_556 = bits(T_447, 9, 9) - node T_558 = bits(T_447, 8, 8) - node T_560 = bits(T_447, 7, 7) - node T_562 = bits(T_447, 6, 6) - node T_564 = bits(T_447, 5, 5) - node T_566 = bits(T_447, 4, 4) - node T_568 = bits(T_447, 3, 3) - node T_570 = bits(T_447, 2, 2) - node T_572 = bits(T_447, 1, 1) - node T_573 = shl(T_572, 0) - node T_574 = mux(T_570, UInt<2>("h2"), T_573) - node T_575 = mux(T_568, UInt<2>("h3"), T_574) - node T_576 = mux(T_566, UInt<3>("h4"), T_575) - node T_577 = mux(T_564, UInt<3>("h5"), T_576) - node T_578 = mux(T_562, UInt<3>("h6"), T_577) - node T_579 = mux(T_560, UInt<3>("h7"), T_578) - node T_580 = mux(T_558, UInt<4>("h8"), T_579) - node T_581 = mux(T_556, UInt<4>("h9"), T_580) - node T_582 = mux(T_554, UInt<4>("ha"), T_581) - node T_583 = mux(T_552, UInt<4>("hb"), T_582) - node T_584 = mux(T_550, UInt<4>("hc"), T_583) - node T_585 = mux(T_548, UInt<4>("hd"), T_584) - node T_586 = mux(T_546, UInt<4>("he"), T_585) - node T_587 = mux(T_544, UInt<4>("hf"), T_586) - node T_588 = mux(T_542, UInt<5>("h10"), T_587) - node T_589 = mux(T_540, UInt<5>("h11"), T_588) - node T_590 = mux(T_538, UInt<5>("h12"), T_589) - node T_591 = mux(T_536, UInt<5>("h13"), T_590) - node T_592 = mux(T_534, UInt<5>("h14"), T_591) - node T_593 = mux(T_532, UInt<5>("h15"), T_592) - node T_594 = mux(T_530, UInt<5>("h16"), T_593) - node T_595 = mux(T_528, UInt<5>("h17"), T_594) - node T_596 = mux(T_526, UInt<5>("h18"), T_595) - node T_597 = mux(T_524, UInt<5>("h19"), T_596) - node T_598 = mux(T_522, UInt<5>("h1a"), T_597) - node T_599 = mux(T_520, UInt<5>("h1b"), T_598) - node T_600 = mux(T_518, UInt<5>("h1c"), T_599) - node T_601 = mux(T_516, UInt<5>("h1d"), T_600) - node T_602 = mux(T_514, UInt<5>("h1e"), T_601) - node T_603 = mux(T_512, UInt<5>("h1f"), T_602) - node T_604 = mux(T_510, UInt<6>("h20"), T_603) - node T_605 = mux(T_508, UInt<6>("h21"), T_604) - node T_606 = mux(T_506, UInt<6>("h22"), T_605) - node T_607 = mux(T_504, UInt<6>("h23"), T_606) - node T_608 = mux(T_502, UInt<6>("h24"), T_607) - node T_609 = mux(T_500, UInt<6>("h25"), T_608) - node T_610 = mux(T_498, UInt<6>("h26"), T_609) - node T_611 = mux(T_496, UInt<6>("h27"), T_610) - node T_612 = mux(T_494, UInt<6>("h28"), T_611) - node T_613 = mux(T_492, UInt<6>("h29"), T_612) - node T_614 = mux(T_490, UInt<6>("h2a"), T_613) - node T_615 = mux(T_488, UInt<6>("h2b"), T_614) - node T_616 = mux(T_486, UInt<6>("h2c"), T_615) - node T_617 = mux(T_484, UInt<6>("h2d"), T_616) - node T_618 = mux(T_482, UInt<6>("h2e"), T_617) - node T_619 = mux(T_480, UInt<6>("h2f"), T_618) - node T_620 = mux(T_478, UInt<6>("h30"), T_619) - node T_621 = mux(T_476, UInt<6>("h31"), T_620) - node T_622 = mux(T_474, UInt<6>("h32"), T_621) - node T_623 = mux(T_472, UInt<6>("h33"), T_622) - node T_624 = mux(T_470, UInt<6>("h34"), T_623) - node T_625 = mux(T_468, UInt<6>("h35"), T_624) - node T_626 = mux(T_466, UInt<6>("h36"), T_625) - node T_627 = mux(T_464, UInt<6>("h37"), T_626) - node T_628 = mux(T_462, UInt<6>("h38"), T_627) - node T_629 = mux(T_460, UInt<6>("h39"), T_628) - node T_630 = mux(T_458, UInt<6>("h3a"), T_629) - node T_631 = mux(T_456, UInt<6>("h3b"), T_630) - node T_632 = mux(T_454, UInt<6>("h3c"), T_631) - node T_633 = mux(T_452, UInt<6>("h3d"), T_632) - node T_634 = mux(T_450, UInt<6>("h3e"), T_633) - node T_635 = mux(T_448, UInt<6>("h3f"), T_634) - node T_637 = add(UInt<6>("h3f"), T_446) - node T_638 = tail(T_637, 1) - node T_639 = sub(T_638, T_635) - node T_640 = tail(T_639, 1) - node T_641 = gt(T_446, T_635) - node T_643 = eq(count, UInt<1>("h0")) - node T_644 = and(T_643, less) - node T_646 = gt(T_640, UInt<1>("h0")) - node T_647 = or(T_646, T_641) - node T_648 = and(T_644, T_647) - node T_650 = and(UInt<1>("h1"), T_648) - when T_650 : - node T_652 = bits(T_640, 5, 0) - node T_653 = mux(T_641, UInt<6>("h3f"), T_652) - node T_654 = bits(remainder, 63, 0) - node T_655 = dshl(T_654, T_653) - remainder <= T_655 - count <= T_653 - skip - node T_657 = eq(count, UInt<1>("h0")) - node T_659 = eq(less, UInt<1>("h0")) - node T_660 = and(T_657, T_659) - node T_662 = eq(isHi, UInt<1>("h0")) - node T_663 = and(T_660, T_662) - when T_663 : - neg_out <= UInt<1>("h0") - skip - skip - node T_665 = and(io.resp.ready, io.resp.valid) - node T_666 = or(T_665, io.kill) - when T_666 : - state <= UInt<1>("h0") - skip - node T_667 = and(io.req.ready, io.req.valid) - when T_667 : - node T_669 = eq(cmdMul, UInt<1>("h0")) - node T_670 = and(rhs_sign, T_669) - node T_671 = or(lhs_sign, T_670) - node T_672 = mux(T_671, UInt<1>("h1"), UInt<2>("h2")) - state <= T_672 - isMul <= cmdMul - isHi <= cmdHi - count <= UInt<1>("h0") - node T_675 = eq(cmdMul, UInt<1>("h0")) - node T_676 = neq(lhs_sign, rhs_sign) - node T_677 = mux(cmdHi, lhs_sign, T_676) - node T_678 = and(T_675, T_677) - neg_out <= T_678 - node T_679 = cat(rhs_sign, rhs_in) - divisor <= T_679 - remainder <= lhs_in - req <- io.req.bits - skip - io.resp.bits <- req - node T_682 = and(req.dw, UInt<1>("h1")) - node T_683 = eq(UInt<1>("h0"), T_682) - node T_684 = bits(remainder, 31, 31) - node T_686 = sub(UInt<32>("h0"), T_684) - node T_687 = tail(T_686, 1) - node T_688 = bits(remainder, 31, 0) - node T_689 = cat(T_687, T_688) - node T_690 = bits(remainder, 63, 0) - node T_691 = mux(T_683, T_689, T_690) - io.resp.bits.data <= T_691 - node T_692 = eq(state, UInt<3>("h5")) - io.resp.valid <= T_692 - node T_693 = eq(state, UInt<1>("h0")) - io.req.ready <= T_693 - module Rocket : - input clk : Clock - input reset : UInt<1> - output io : { host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, imem : { req : { valid : UInt<1>, bits : { pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, status : UInt<2>}}}}} - io is invalid - reg ex_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk with : - reset => (UInt<1>("h0"), ex_ctrl) - reg mem_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk with : - reset => (UInt<1>("h0"), mem_ctrl) - reg wb_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk with : - reset => (UInt<1>("h0"), wb_ctrl) - reg ex_reg_xcpt_interrupt : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_xcpt_interrupt) - reg ex_reg_valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_valid) - reg ex_reg_btb_hit : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_btb_hit) - reg ex_reg_btb_resp : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), ex_reg_btb_resp) - reg ex_reg_xcpt : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_xcpt) - reg ex_reg_flush_pipe : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_flush_pipe) - reg ex_reg_load_use : UInt<1>, clk with : - reset => (UInt<1>("h0"), ex_reg_load_use) - reg ex_reg_cause : UInt, clk with : - reset => (UInt<1>("h0"), ex_reg_cause) - reg ex_reg_pc : UInt, clk with : - reset => (UInt<1>("h0"), ex_reg_pc) - reg ex_reg_inst : UInt, clk with : - reset => (UInt<1>("h0"), ex_reg_inst) - reg mem_reg_xcpt_interrupt : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_xcpt_interrupt) - reg mem_reg_valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_valid) - reg mem_reg_btb_hit : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_btb_hit) - reg mem_reg_btb_resp : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), mem_reg_btb_resp) - reg mem_reg_xcpt : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_xcpt) - reg mem_reg_replay : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_replay) - reg mem_reg_flush_pipe : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_flush_pipe) - reg mem_reg_cause : UInt, clk with : - reset => (UInt<1>("h0"), mem_reg_cause) - reg mem_reg_slow_bypass : UInt<1>, clk with : - reset => (UInt<1>("h0"), mem_reg_slow_bypass) - reg mem_reg_pc : UInt, clk with : - reset => (UInt<1>("h0"), mem_reg_pc) - reg mem_reg_inst : UInt, clk with : - reset => (UInt<1>("h0"), mem_reg_inst) - reg mem_reg_wdata : UInt, clk with : - reset => (UInt<1>("h0"), mem_reg_wdata) - reg mem_reg_rs2 : UInt, clk with : - reset => (UInt<1>("h0"), mem_reg_rs2) - wire take_pc_mem : UInt<1> - take_pc_mem is invalid - reg wb_reg_valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), wb_reg_valid) - reg wb_reg_xcpt : UInt<1>, clk with : - reset => (UInt<1>("h0"), wb_reg_xcpt) - reg wb_reg_replay : UInt<1>, clk with : - reset => (UInt<1>("h0"), wb_reg_replay) - reg wb_reg_cause : UInt, clk with : - reset => (UInt<1>("h0"), wb_reg_cause) - reg wb_reg_rocc_pending : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg wb_reg_pc : UInt, clk with : - reset => (UInt<1>("h0"), wb_reg_pc) - reg wb_reg_inst : UInt, clk with : - reset => (UInt<1>("h0"), wb_reg_inst) - reg wb_reg_wdata : UInt, clk with : - reset => (UInt<1>("h0"), wb_reg_wdata) - reg wb_reg_rs2 : UInt, clk with : - reset => (UInt<1>("h0"), wb_reg_rs2) - wire take_pc_wb : UInt<1> - take_pc_wb is invalid - node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) - wire id_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} - id_ctrl is invalid - node T_6071 = and(io.imem.resp.bits.data[0], UInt<32>("h207f")) - node T_6073 = eq(T_6071, UInt<32>("h3")) - node T_6075 = and(io.imem.resp.bits.data[0], UInt<32>("h106f")) - node T_6077 = eq(T_6075, UInt<32>("h3")) - node T_6079 = and(io.imem.resp.bits.data[0], UInt<32>("h607f")) - node T_6081 = eq(T_6079, UInt<32>("hf")) - node T_6083 = and(io.imem.resp.bits.data[0], UInt<32>("h7077")) - node T_6085 = eq(T_6083, UInt<32>("h13")) - node T_6087 = and(io.imem.resp.bits.data[0], UInt<32>("h5f")) - node T_6089 = eq(T_6087, UInt<32>("h17")) - node T_6091 = and(io.imem.resp.bits.data[0], UInt<32>("hfc00007f")) - node T_6093 = eq(T_6091, UInt<32>("h33")) - node T_6095 = and(io.imem.resp.bits.data[0], UInt<32>("hbe007077")) - node T_6097 = eq(T_6095, UInt<32>("h33")) - node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h4000073")) - node T_6101 = eq(T_6099, UInt<32>("h43")) - node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("he400007f")) - node T_6105 = eq(T_6103, UInt<32>("h53")) - node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h707b")) - node T_6109 = eq(T_6107, UInt<32>("h63")) - node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h7f")) - node T_6113 = eq(T_6111, UInt<32>("h6f")) - node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("hffefffff")) - node T_6117 = eq(T_6115, UInt<32>("h73")) - node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("hfc00305f")) - node T_6121 = eq(T_6119, UInt<32>("h1013")) - node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("hfe00305f")) - node T_6125 = eq(T_6123, UInt<32>("h101b")) - node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h605b")) - node T_6129 = eq(T_6127, UInt<32>("h2003")) - node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h207f")) - node T_6133 = eq(T_6131, UInt<32>("h2013")) - node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h1800607f")) - node T_6137 = eq(T_6135, UInt<32>("h202f")) - node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h207f")) - node T_6141 = eq(T_6139, UInt<32>("h2073")) - node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("hbc00707f")) - node T_6145 = eq(T_6143, UInt<32>("h5013")) - node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("hbe00705f")) - node T_6149 = eq(T_6147, UInt<32>("h501b")) - node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("hbe007077")) - node T_6153 = eq(T_6151, UInt<32>("h5033")) - node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("hfe004077")) - node T_6157 = eq(T_6155, UInt<32>("h2004033")) - node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("he800607f")) - node T_6161 = eq(T_6159, UInt<32>("h800202f")) - node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("hffdfffff")) - node T_6165 = eq(T_6163, UInt<32>("h10000073")) - node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("hf9f0607f")) - node T_6169 = eq(T_6167, UInt<32>("h1000202f")) - node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("hfff07fff")) - node T_6173 = eq(T_6171, UInt<32>("h10100073")) - node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("hf400607f")) - node T_6177 = eq(T_6175, UInt<32>("h20000053")) - node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h7c00607f")) - node T_6181 = eq(T_6179, UInt<32>("h20000053")) - node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h7c00507f")) - node T_6185 = eq(T_6183, UInt<32>("h20000053")) - node T_6187 = eq(io.imem.resp.bits.data[0], UInt<32>("h30500073")) - node T_6189 = and(io.imem.resp.bits.data[0], UInt<32>("h7ff0007f")) - node T_6191 = eq(T_6189, UInt<32>("h40100053")) - node T_6193 = and(io.imem.resp.bits.data[0], UInt<32>("h7ff0007f")) - node T_6195 = eq(T_6193, UInt<32>("h42000053")) - node T_6197 = and(io.imem.resp.bits.data[0], UInt<32>("hfdf0007f")) - node T_6199 = eq(T_6197, UInt<32>("h58000053")) - node T_6201 = and(io.imem.resp.bits.data[0], UInt<32>("hedc0007f")) - node T_6203 = eq(T_6201, UInt<32>("hc0000053")) - node T_6205 = and(io.imem.resp.bits.data[0], UInt<32>("hfdf0607f")) - node T_6207 = eq(T_6205, UInt<32>("he0000053")) - node T_6209 = and(io.imem.resp.bits.data[0], UInt<32>("hedf0707f")) - node T_6211 = eq(T_6209, UInt<32>("he0000053")) - node T_6213 = and(io.imem.resp.bits.data[0], UInt<32>("h603f")) - node T_6215 = eq(T_6213, UInt<32>("h23")) - node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h306f")) - node T_6219 = eq(T_6217, UInt<32>("h1063")) - node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h407f")) - node T_6223 = eq(T_6221, UInt<32>("h4063")) - node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("hfc007077")) - node T_6227 = eq(T_6225, UInt<32>("h33")) - node T_6229 = or(UInt<1>("h0"), T_6073) - node T_6230 = or(T_6229, T_6077) - node T_6231 = or(T_6230, T_6081) - node T_6232 = or(T_6231, T_6085) - node T_6233 = or(T_6232, T_6089) - node T_6234 = or(T_6233, T_6093) - node T_6235 = or(T_6234, T_6097) - node T_6236 = or(T_6235, T_6101) - node T_6237 = or(T_6236, T_6105) - node T_6238 = or(T_6237, T_6109) - node T_6239 = or(T_6238, T_6113) - node T_6240 = or(T_6239, T_6117) - node T_6241 = or(T_6240, T_6121) - node T_6242 = or(T_6241, T_6125) - node T_6243 = or(T_6242, T_6129) - node T_6244 = or(T_6243, T_6133) - node T_6245 = or(T_6244, T_6137) - node T_6246 = or(T_6245, T_6141) - node T_6247 = or(T_6246, T_6145) - node T_6248 = or(T_6247, T_6149) - node T_6249 = or(T_6248, T_6153) - node T_6250 = or(T_6249, T_6157) - node T_6251 = or(T_6250, T_6161) - node T_6252 = or(T_6251, T_6165) - node T_6253 = or(T_6252, T_6169) - node T_6254 = or(T_6253, T_6173) - node T_6255 = or(T_6254, T_6177) - node T_6256 = or(T_6255, T_6181) - node T_6257 = or(T_6256, T_6185) - node T_6258 = or(T_6257, T_6187) - node T_6259 = or(T_6258, T_6191) - node T_6260 = or(T_6259, T_6195) - node T_6261 = or(T_6260, T_6199) - node T_6262 = or(T_6261, T_6203) - node T_6263 = or(T_6262, T_6207) - node T_6264 = or(T_6263, T_6211) - node T_6265 = or(T_6264, T_6215) - node T_6266 = or(T_6265, T_6219) - node T_6267 = or(T_6266, T_6223) - node T_6268 = or(T_6267, T_6227) - node T_6270 = and(io.imem.resp.bits.data[0], UInt<32>("h5c")) - node T_6272 = eq(T_6270, UInt<32>("h4")) - node T_6274 = and(io.imem.resp.bits.data[0], UInt<32>("h60")) - node T_6276 = eq(T_6274, UInt<32>("h40")) - node T_6278 = or(UInt<1>("h0"), T_6272) - node T_6279 = or(T_6278, T_6276) - node T_6282 = and(io.imem.resp.bits.data[0], UInt<32>("h74")) - node T_6284 = eq(T_6282, UInt<32>("h60")) - node T_6286 = or(UInt<1>("h0"), T_6284) - node T_6288 = and(io.imem.resp.bits.data[0], UInt<32>("h68")) - node T_6290 = eq(T_6288, UInt<32>("h68")) - node T_6292 = or(UInt<1>("h0"), T_6290) - node T_6294 = and(io.imem.resp.bits.data[0], UInt<32>("h203c")) - node T_6296 = eq(T_6294, UInt<32>("h24")) - node T_6298 = or(UInt<1>("h0"), T_6296) - node T_6300 = and(io.imem.resp.bits.data[0], UInt<32>("h64")) - node T_6302 = eq(T_6300, UInt<32>("h20")) - node T_6304 = and(io.imem.resp.bits.data[0], UInt<32>("h34")) - node T_6306 = eq(T_6304, UInt<32>("h20")) - node T_6308 = and(io.imem.resp.bits.data[0], UInt<32>("h2048")) - node T_6310 = eq(T_6308, UInt<32>("h2008")) - node T_6312 = or(UInt<1>("h0"), T_6302) - node T_6313 = or(T_6312, T_6306) - node T_6314 = or(T_6313, T_6310) - node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h44")) - node T_6318 = eq(T_6316, UInt<32>("h0")) - node T_6320 = and(io.imem.resp.bits.data[0], UInt<32>("h4024")) - node T_6322 = eq(T_6320, UInt<32>("h20")) - node T_6324 = and(io.imem.resp.bits.data[0], UInt<32>("h38")) - node T_6326 = eq(T_6324, UInt<32>("h20")) - node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h2050")) - node T_6330 = eq(T_6328, UInt<32>("h2000")) - node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h90000034")) - node T_6334 = eq(T_6332, UInt<32>("h90000010")) - node T_6336 = or(UInt<1>("h0"), T_6318) - node T_6337 = or(T_6336, T_6322) - node T_6338 = or(T_6337, T_6326) - node T_6339 = or(T_6338, T_6330) - node T_6340 = or(T_6339, T_6334) - node T_6342 = and(io.imem.resp.bits.data[0], UInt<32>("h58")) - node T_6344 = eq(T_6342, UInt<32>("h0")) - node T_6346 = and(io.imem.resp.bits.data[0], UInt<32>("h20")) - node T_6348 = eq(T_6346, UInt<32>("h0")) - node T_6350 = and(io.imem.resp.bits.data[0], UInt<32>("hc")) - node T_6352 = eq(T_6350, UInt<32>("h4")) - node T_6354 = and(io.imem.resp.bits.data[0], UInt<32>("h48")) - node T_6356 = eq(T_6354, UInt<32>("h48")) - node T_6358 = and(io.imem.resp.bits.data[0], UInt<32>("h4050")) - node T_6360 = eq(T_6358, UInt<32>("h4050")) - node T_6362 = or(UInt<1>("h0"), T_6344) - node T_6363 = or(T_6362, T_6348) - node T_6364 = or(T_6363, T_6352) - node T_6365 = or(T_6364, T_6356) - node T_6366 = or(T_6365, T_6360) - node T_6368 = and(io.imem.resp.bits.data[0], UInt<32>("h48")) - node T_6370 = eq(T_6368, UInt<32>("h0")) - node T_6372 = and(io.imem.resp.bits.data[0], UInt<32>("h18")) - node T_6374 = eq(T_6372, UInt<32>("h0")) - node T_6376 = and(io.imem.resp.bits.data[0], UInt<32>("h4008")) - node T_6378 = eq(T_6376, UInt<32>("h4000")) - node T_6380 = or(UInt<1>("h0"), T_6370) - node T_6381 = or(T_6380, T_6318) - node T_6382 = or(T_6381, T_6374) - node T_6383 = or(T_6382, T_6378) - node T_6384 = cat(T_6383, T_6366) - node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h4004")) - node T_6388 = eq(T_6386, UInt<32>("h0")) - node T_6390 = and(io.imem.resp.bits.data[0], UInt<32>("h50")) - node T_6392 = eq(T_6390, UInt<32>("h0")) - node T_6394 = and(io.imem.resp.bits.data[0], UInt<32>("h24")) - node T_6396 = eq(T_6394, UInt<32>("h0")) - node T_6398 = or(UInt<1>("h0"), T_6388) - node T_6399 = or(T_6398, T_6392) - node T_6400 = or(T_6399, T_6318) - node T_6401 = or(T_6400, T_6396) - node T_6402 = or(T_6401, T_6374) - node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h34")) - node T_6406 = eq(T_6404, UInt<32>("h14")) - node T_6408 = or(UInt<1>("h0"), T_6406) - node T_6409 = or(T_6408, T_6356) - node T_6410 = cat(T_6409, T_6402) - node T_6412 = and(io.imem.resp.bits.data[0], UInt<32>("h18")) - node T_6414 = eq(T_6412, UInt<32>("h8")) - node T_6416 = and(io.imem.resp.bits.data[0], UInt<32>("h44")) - node T_6418 = eq(T_6416, UInt<32>("h40")) - node T_6420 = or(UInt<1>("h0"), T_6414) - node T_6421 = or(T_6420, T_6418) - node T_6423 = and(io.imem.resp.bits.data[0], UInt<32>("h14")) - node T_6425 = eq(T_6423, UInt<32>("h14")) - node T_6427 = or(UInt<1>("h0"), T_6414) - node T_6428 = or(T_6427, T_6425) - node T_6430 = and(io.imem.resp.bits.data[0], UInt<32>("h30")) - node T_6432 = eq(T_6430, UInt<32>("h0")) - node T_6434 = and(io.imem.resp.bits.data[0], UInt<32>("h201c")) - node T_6436 = eq(T_6434, UInt<32>("h4")) - node T_6438 = and(io.imem.resp.bits.data[0], UInt<32>("h14")) - node T_6440 = eq(T_6438, UInt<32>("h10")) - node T_6442 = or(UInt<1>("h0"), T_6432) - node T_6443 = or(T_6442, T_6436) - node T_6444 = or(T_6443, T_6440) - node T_6445 = cat(T_6428, T_6421) - node T_6446 = cat(T_6444, T_6445) - node T_6448 = and(io.imem.resp.bits.data[0], UInt<32>("h10")) - node T_6450 = eq(T_6448, UInt<32>("h0")) - node T_6452 = and(io.imem.resp.bits.data[0], UInt<32>("h8")) - node T_6454 = eq(T_6452, UInt<32>("h0")) - node T_6456 = or(UInt<1>("h0"), T_6450) - node T_6457 = or(T_6456, T_6454) - node T_6459 = and(io.imem.resp.bits.data[0], UInt<32>("h3054")) - node T_6461 = eq(T_6459, UInt<32>("h1010")) - node T_6463 = and(io.imem.resp.bits.data[0], UInt<32>("h1058")) - node T_6465 = eq(T_6463, UInt<32>("h1040")) - node T_6467 = and(io.imem.resp.bits.data[0], UInt<32>("h7044")) - node T_6469 = eq(T_6467, UInt<32>("h7000")) - node T_6471 = or(UInt<1>("h0"), T_6461) - node T_6472 = or(T_6471, T_6465) - node T_6473 = or(T_6472, T_6469) - node T_6475 = and(io.imem.resp.bits.data[0], UInt<32>("h4054")) - node T_6477 = eq(T_6475, UInt<32>("h40")) - node T_6479 = and(io.imem.resp.bits.data[0], UInt<32>("h2058")) - node T_6481 = eq(T_6479, UInt<32>("h2040")) - node T_6483 = and(io.imem.resp.bits.data[0], UInt<32>("h3054")) - node T_6485 = eq(T_6483, UInt<32>("h3010")) - node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h6054")) - node T_6489 = eq(T_6487, UInt<32>("h6010")) - node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h40003034")) - node T_6493 = eq(T_6491, UInt<32>("h40000030")) - node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h40001054")) - node T_6497 = eq(T_6495, UInt<32>("h40001010")) - node T_6499 = or(UInt<1>("h0"), T_6477) - node T_6500 = or(T_6499, T_6481) - node T_6501 = or(T_6500, T_6485) - node T_6502 = or(T_6501, T_6489) - node T_6503 = or(T_6502, T_6493) - node T_6504 = or(T_6503, T_6497) - node T_6506 = and(io.imem.resp.bits.data[0], UInt<32>("h2054")) - node T_6508 = eq(T_6506, UInt<32>("h2010")) - node T_6510 = and(io.imem.resp.bits.data[0], UInt<32>("h40004054")) - node T_6512 = eq(T_6510, UInt<32>("h4010")) - node T_6514 = and(io.imem.resp.bits.data[0], UInt<32>("h5054")) - node T_6516 = eq(T_6514, UInt<32>("h4010")) - node T_6518 = and(io.imem.resp.bits.data[0], UInt<32>("h4058")) - node T_6520 = eq(T_6518, UInt<32>("h4040")) - node T_6522 = or(UInt<1>("h0"), T_6508) - node T_6523 = or(T_6522, T_6512) - node T_6524 = or(T_6523, T_6516) - node T_6525 = or(T_6524, T_6520) - node T_6527 = and(io.imem.resp.bits.data[0], UInt<32>("h6054")) - node T_6529 = eq(T_6527, UInt<32>("h2010")) - node T_6531 = and(io.imem.resp.bits.data[0], UInt<32>("h40003054")) - node T_6533 = eq(T_6531, UInt<32>("h40001010")) - node T_6535 = or(UInt<1>("h0"), T_6529) - node T_6536 = or(T_6535, T_6520) - node T_6537 = or(T_6536, T_6493) - node T_6538 = or(T_6537, T_6533) - node T_6539 = cat(T_6504, T_6473) - node T_6540 = cat(T_6525, T_6539) - node T_6541 = cat(T_6538, T_6540) - node T_6543 = and(io.imem.resp.bits.data[0], UInt<32>("h405f")) - node T_6545 = eq(T_6543, UInt<32>("h3")) - node T_6547 = and(io.imem.resp.bits.data[0], UInt<32>("h107f")) - node T_6549 = eq(T_6547, UInt<32>("h3")) - node T_6551 = or(UInt<1>("h0"), T_6545) - node T_6552 = or(T_6551, T_6073) - node T_6553 = or(T_6552, T_6549) - node T_6554 = or(T_6553, T_6129) - node T_6555 = or(T_6554, T_6137) - node T_6556 = or(T_6555, T_6161) - node T_6557 = or(T_6556, T_6169) - node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h28")) - node T_6561 = eq(T_6559, UInt<32>("h20")) - node T_6563 = and(io.imem.resp.bits.data[0], UInt<32>("h18000020")) - node T_6565 = eq(T_6563, UInt<32>("h18000020")) - node T_6567 = and(io.imem.resp.bits.data[0], UInt<32>("h20000020")) - node T_6569 = eq(T_6567, UInt<32>("h20000020")) - node T_6571 = or(UInt<1>("h0"), T_6561) - node T_6572 = or(T_6571, T_6565) - node T_6573 = or(T_6572, T_6569) - node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h10000008")) - node T_6577 = eq(T_6575, UInt<32>("h10000008")) - node T_6579 = and(io.imem.resp.bits.data[0], UInt<32>("h40000008")) - node T_6581 = eq(T_6579, UInt<32>("h40000008")) - node T_6583 = or(UInt<1>("h0"), T_6577) - node T_6584 = or(T_6583, T_6581) - node T_6586 = and(io.imem.resp.bits.data[0], UInt<32>("h8000008")) - node T_6588 = eq(T_6586, UInt<32>("h8000008")) - node T_6590 = and(io.imem.resp.bits.data[0], UInt<32>("h80000008")) - node T_6592 = eq(T_6590, UInt<32>("h80000008")) - node T_6594 = or(UInt<1>("h0"), T_6588) - node T_6595 = or(T_6594, T_6577) - node T_6596 = or(T_6595, T_6592) - node T_6598 = and(io.imem.resp.bits.data[0], UInt<32>("h18000008")) - node T_6600 = eq(T_6598, UInt<32>("h8")) - node T_6602 = or(UInt<1>("h0"), T_6600) - node T_6604 = cat(T_6584, T_6573) - node T_6605 = cat(T_6596, T_6604) - node T_6606 = cat(T_6602, T_6605) - node T_6607 = cat(UInt<1>("h0"), T_6606) - node T_6609 = and(io.imem.resp.bits.data[0], UInt<32>("h1000")) - node T_6611 = eq(T_6609, UInt<32>("h1000")) - node T_6613 = or(UInt<1>("h0"), T_6611) - node T_6615 = and(io.imem.resp.bits.data[0], UInt<32>("h2000")) - node T_6617 = eq(T_6615, UInt<32>("h2000")) - node T_6619 = or(UInt<1>("h0"), T_6617) - node T_6621 = and(io.imem.resp.bits.data[0], UInt<32>("h4000")) - node T_6623 = eq(T_6621, UInt<32>("h4000")) - node T_6625 = or(UInt<1>("h0"), T_6623) - node T_6626 = cat(T_6619, T_6613) - node T_6627 = cat(T_6625, T_6626) - node T_6629 = and(io.imem.resp.bits.data[0], UInt<32>("h80000060")) - node T_6631 = eq(T_6629, UInt<32>("h40")) - node T_6633 = and(io.imem.resp.bits.data[0], UInt<32>("h10000060")) - node T_6635 = eq(T_6633, UInt<32>("h40")) - node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h70")) - node T_6639 = eq(T_6637, UInt<32>("h40")) - node T_6641 = or(UInt<1>("h0"), T_6631) - node T_6642 = or(T_6641, T_6635) - node T_6643 = or(T_6642, T_6639) - node T_6645 = and(io.imem.resp.bits.data[0], UInt<32>("h7c")) - node T_6647 = eq(T_6645, UInt<32>("h24")) - node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h40000060")) - node T_6651 = eq(T_6649, UInt<32>("h40")) - node T_6653 = and(io.imem.resp.bits.data[0], UInt<32>("h90000060")) - node T_6655 = eq(T_6653, UInt<32>("h10000040")) - node T_6657 = or(UInt<1>("h0"), T_6647) - node T_6658 = or(T_6657, T_6651) - node T_6659 = or(T_6658, T_6639) - node T_6660 = or(T_6659, T_6655) - node T_6662 = or(UInt<1>("h0"), T_6639) - node T_6664 = and(io.imem.resp.bits.data[0], UInt<32>("h3c")) - node T_6666 = eq(T_6664, UInt<32>("h4")) - node T_6668 = and(io.imem.resp.bits.data[0], UInt<32>("h10000060")) - node T_6670 = eq(T_6668, UInt<32>("h10000040")) - node T_6672 = or(UInt<1>("h0"), T_6666) - node T_6673 = or(T_6672, T_6631) - node T_6674 = or(T_6673, T_6639) - node T_6675 = or(T_6674, T_6670) - node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h2000074")) - node T_6679 = eq(T_6677, UInt<32>("h2000030")) - node T_6681 = or(UInt<1>("h0"), T_6679) - node T_6683 = and(io.imem.resp.bits.data[0], UInt<32>("h64")) - node T_6685 = eq(T_6683, UInt<32>("h0")) - node T_6687 = and(io.imem.resp.bits.data[0], UInt<32>("h50")) - node T_6689 = eq(T_6687, UInt<32>("h10")) - node T_6691 = and(io.imem.resp.bits.data[0], UInt<32>("h2024")) - node T_6693 = eq(T_6691, UInt<32>("h24")) - node T_6695 = and(io.imem.resp.bits.data[0], UInt<32>("h28")) - node T_6697 = eq(T_6695, UInt<32>("h28")) - node T_6699 = and(io.imem.resp.bits.data[0], UInt<32>("h1030")) - node T_6701 = eq(T_6699, UInt<32>("h1030")) - node T_6703 = and(io.imem.resp.bits.data[0], UInt<32>("h2030")) - node T_6705 = eq(T_6703, UInt<32>("h2030")) - node T_6707 = and(io.imem.resp.bits.data[0], UInt<32>("h90000010")) - node T_6709 = eq(T_6707, UInt<32>("h80000010")) - node T_6711 = or(UInt<1>("h0"), T_6685) - node T_6712 = or(T_6711, T_6689) - node T_6713 = or(T_6712, T_6693) - node T_6714 = or(T_6713, T_6697) - node T_6715 = or(T_6714, T_6701) - node T_6716 = or(T_6715, T_6705) - node T_6717 = or(T_6716, T_6709) - node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h1070")) - node T_6721 = eq(T_6719, UInt<32>("h1070")) - node T_6723 = or(UInt<1>("h0"), T_6721) - node T_6725 = and(io.imem.resp.bits.data[0], UInt<32>("h2070")) - node T_6727 = eq(T_6725, UInt<32>("h2070")) - node T_6729 = or(UInt<1>("h0"), T_6727) - node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h3070")) - node T_6733 = eq(T_6731, UInt<32>("h70")) - node T_6735 = or(UInt<1>("h0"), T_6733) - node T_6736 = cat(T_6729, T_6723) - node T_6737 = cat(T_6735, T_6736) - node T_6739 = and(io.imem.resp.bits.data[0], UInt<32>("h3058")) - node T_6741 = eq(T_6739, UInt<32>("h1008")) - node T_6743 = or(UInt<1>("h0"), T_6741) - node T_6745 = and(io.imem.resp.bits.data[0], UInt<32>("h3058")) - node T_6747 = eq(T_6745, UInt<32>("h8")) - node T_6749 = or(UInt<1>("h0"), T_6747) - node T_6751 = and(io.imem.resp.bits.data[0], UInt<32>("h6048")) - node T_6753 = eq(T_6751, UInt<32>("h2008")) - node T_6755 = or(UInt<1>("h0"), T_6753) - id_ctrl.legal <= T_6268 - id_ctrl.fp <= T_6279 - id_ctrl.rocc <= UInt<1>("h0") - id_ctrl.branch <= T_6286 - id_ctrl.jal <= T_6292 - id_ctrl.jalr <= T_6298 - id_ctrl.rxs2 <= T_6314 - id_ctrl.rxs1 <= T_6340 - id_ctrl.sel_alu2 <= T_6384 - id_ctrl.sel_alu1 <= T_6410 - id_ctrl.sel_imm <= T_6446 - id_ctrl.alu_dw <= T_6457 - id_ctrl.alu_fn <= T_6541 - id_ctrl.mem <= T_6557 - id_ctrl.mem_cmd <= T_6607 - id_ctrl.mem_type <= T_6627 - id_ctrl.rfs1 <= T_6643 - id_ctrl.rfs2 <= T_6660 - id_ctrl.rfs3 <= T_6662 - id_ctrl.wfd <= T_6675 - id_ctrl.div <= T_6681 - id_ctrl.wxd <= T_6717 - id_ctrl.csr <= T_6737 - id_ctrl.fence_i <= T_6743 - id_ctrl.fence <= T_6749 - id_ctrl.amo <= T_6755 - node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27) - node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20) - node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15) - node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7) - wire id_load_use : UInt<1> - id_load_use is invalid - reg id_reg_fence : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - mem T_6766 : - data-type => UInt<64> - depth => 31 - write-latency => 1 - read-latency => 0 - reader => T_6776 - reader => T_6787 - writer => T_7490 - T_6766.T_6776.addr is invalid - T_6766.T_6776.clk <= clk - T_6766.T_6787.addr is invalid - T_6766.T_6787.clk <= clk - T_6766.T_6776.en <= UInt<1>("h0") - T_6766.T_6787.en <= UInt<1>("h0") - T_6766.T_7490.addr is invalid - T_6766.T_7490.clk <= clk - T_6766.T_7490.en <= UInt<1>("h0") - T_6766.T_7490.data is invalid - T_6766.T_7490.mask <= UInt<1>("h0") - wire T_6768 : UInt - T_6768 is invalid - node T_6771 = eq(id_raddr1, UInt<1>("h0")) - node T_6772 = and(UInt<1>("h0"), T_6771) - node T_6774 = bits(id_raddr1, 4, 0) - node T_6775 = not(T_6774) - T_6766.T_6776.addr <= T_6775 - T_6766.T_6776.en <= UInt<1>("h1") - node T_6777 = mux(T_6772, UInt<1>("h0"), T_6766.T_6776.data) - T_6768 <= T_6777 - wire T_6779 : UInt - T_6779 is invalid - node T_6782 = eq(id_raddr2, UInt<1>("h0")) - node T_6783 = and(UInt<1>("h0"), T_6782) - node T_6785 = bits(id_raddr2, 4, 0) - node T_6786 = not(T_6785) - T_6766.T_6787.addr <= T_6786 - T_6766.T_6787.en <= UInt<1>("h1") - node T_6788 = mux(T_6783, UInt<1>("h0"), T_6766.T_6787.data) - T_6779 <= T_6788 - wire ctrl_killd : UInt<1> - ctrl_killd is invalid - inst csr of CSRFile - csr.io is invalid - csr.clk <= clk - csr.reset <= reset - node id_csr_en = neq(id_ctrl.csr, UInt<3>("h0")) - node id_system_insn = eq(id_ctrl.csr, UInt<3>("h4")) - node T_6794 = eq(id_ctrl.csr, UInt<3>("h2")) - node T_6795 = eq(id_ctrl.csr, UInt<3>("h3")) - node T_6796 = or(T_6794, T_6795) - node T_6798 = eq(id_raddr1, UInt<1>("h0")) - node id_csr_ren = and(T_6796, T_6798) - node id_csr = mux(id_csr_ren, UInt<3>("h5"), id_ctrl.csr) - node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20) - node T_6803 = eq(id_csr_ren, UInt<1>("h0")) - node T_6804 = and(id_csr_en, T_6803) - node T_6863 = and(id_csr_addr, UInt<12>("h8c4")) - node T_6865 = eq(T_6863, UInt<12>("h40")) - node T_6867 = or(UInt<1>("h0"), T_6865) - node T_6868 = bits(T_6867, 0, 0) - node T_6870 = eq(T_6868, UInt<1>("h0")) - node T_6871 = and(T_6804, T_6870) - node id_csr_flush = or(id_system_insn, T_6871) - node T_6874 = eq(id_ctrl.legal, UInt<1>("h0")) - node T_6876 = neq(csr.io.status.fs, UInt<1>("h0")) - node T_6878 = eq(T_6876, UInt<1>("h0")) - node T_6879 = and(id_ctrl.fp, T_6878) - node T_6880 = or(T_6874, T_6879) - node T_6882 = neq(csr.io.status.xs, UInt<1>("h0")) - node T_6884 = eq(T_6882, UInt<1>("h0")) - node T_6885 = and(id_ctrl.rocc, T_6884) - node id_illegal_insn = or(T_6880, T_6885) - node id_amo_aq = bits(io.imem.resp.bits.data[0], 26, 26) - node id_amo_rl = bits(io.imem.resp.bits.data[0], 25, 25) - node T_6889 = and(id_ctrl.amo, id_amo_rl) - node id_fence_next = or(id_ctrl.fence, T_6889) - node T_6892 = eq(io.dmem.ordered, UInt<1>("h0")) - node id_mem_busy = or(T_6892, io.dmem.req.valid) - node T_6895 = and(ex_reg_valid, ex_ctrl.rocc) - node T_6896 = or(io.rocc.busy, T_6895) - node T_6897 = and(mem_reg_valid, mem_ctrl.rocc) - node T_6898 = or(T_6896, T_6897) - node T_6899 = and(wb_reg_valid, wb_ctrl.rocc) - node T_6900 = or(T_6898, T_6899) - node id_rocc_busy = and(UInt<1>("h0"), T_6900) - node T_6902 = and(id_reg_fence, id_mem_busy) - node T_6903 = or(id_fence_next, T_6902) - id_reg_fence <= T_6903 - node T_6904 = and(id_rocc_busy, id_ctrl.fence) - node T_6905 = and(id_ctrl.amo, id_amo_aq) - node T_6906 = or(T_6905, id_ctrl.fence_i) - node T_6907 = or(id_ctrl.mem, id_ctrl.rocc) - node T_6908 = and(id_reg_fence, T_6907) - node T_6909 = or(T_6906, T_6908) - node T_6910 = or(T_6909, id_csr_en) - node T_6911 = and(id_mem_busy, T_6910) - node id_do_fence = or(T_6904, T_6911) - node T_6915 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) - node id_xcpt = or(T_6915, id_illegal_insn) - node T_6917 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h1"), UInt<2>("h2")) - node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_6917) - node ex_waddr = bits(ex_reg_inst, 11, 7) - node mem_waddr = bits(mem_reg_inst, 11, 7) - node wb_waddr = bits(wb_reg_inst, 11, 7) - node T_6925 = and(ex_reg_valid, ex_ctrl.wxd) - node T_6926 = and(mem_reg_valid, mem_ctrl.wxd) - node T_6928 = eq(mem_ctrl.mem, UInt<1>("h0")) - node T_6929 = and(T_6926, T_6928) - node T_6930 = and(mem_reg_valid, mem_ctrl.wxd) - node T_6931 = eq(UInt<1>("h0"), id_raddr1) - node T_6932 = and(UInt<1>("h1"), T_6931) - node T_6933 = eq(ex_waddr, id_raddr1) - node T_6934 = and(T_6925, T_6933) - node T_6935 = eq(mem_waddr, id_raddr1) - node T_6936 = and(T_6929, T_6935) - node T_6937 = eq(mem_waddr, id_raddr1) - node T_6938 = and(T_6930, T_6937) - node T_6939 = eq(UInt<1>("h0"), id_raddr2) - node T_6940 = and(UInt<1>("h1"), T_6939) - node T_6941 = eq(ex_waddr, id_raddr2) - node T_6942 = and(T_6925, T_6941) - node T_6943 = eq(mem_waddr, id_raddr2) - node T_6944 = and(T_6929, T_6943) - node T_6945 = eq(mem_waddr, id_raddr2) - node T_6946 = and(T_6930, T_6945) - wire bypass_mux : UInt[4] - bypass_mux[0] <= UInt<1>("h0") - bypass_mux[1] <= mem_reg_wdata - bypass_mux[2] <= wb_reg_wdata - bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass - reg ex_reg_rs_bypass : UInt<1>[2], clk with : - reset => (UInt<1>("h0"), ex_reg_rs_bypass) - reg ex_reg_rs_lsb : UInt[2], clk with : - reset => (UInt<1>("h0"), ex_reg_rs_lsb) - reg ex_reg_rs_msb : UInt[2], clk with : - reset => (UInt<1>("h0"), ex_reg_rs_msb) - node T_6991 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) - node T_6992 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_6991) - node T_6994 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) - node T_6995 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_6994) - node T_6996 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) - node T_6998 = bits(ex_reg_inst, 31, 31) - node T_6999 = asSInt(T_6998) - node T_7000 = mux(T_6996, asSInt(UInt<1>("h0")), T_6999) - node T_7001 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) - node T_7002 = bits(ex_reg_inst, 30, 20) - node T_7003 = asSInt(T_7002) - node T_7004 = mux(T_7001, T_7003, T_7000) - node T_7005 = neq(ex_ctrl.sel_imm, UInt<3>("h2")) - node T_7006 = neq(ex_ctrl.sel_imm, UInt<3>("h3")) - node T_7007 = and(T_7005, T_7006) - node T_7008 = bits(ex_reg_inst, 19, 12) - node T_7009 = asSInt(T_7008) - node T_7010 = mux(T_7007, T_7000, T_7009) - node T_7011 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) - node T_7012 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) - node T_7013 = or(T_7011, T_7012) - node T_7015 = eq(ex_ctrl.sel_imm, UInt<3>("h3")) - node T_7016 = bits(ex_reg_inst, 20, 20) - node T_7017 = asSInt(T_7016) - node T_7018 = eq(ex_ctrl.sel_imm, UInt<3>("h1")) - node T_7019 = bits(ex_reg_inst, 7, 7) - node T_7020 = asSInt(T_7019) - node T_7021 = mux(T_7018, T_7020, T_7000) - node T_7022 = mux(T_7015, T_7017, T_7021) - node T_7023 = mux(T_7013, asSInt(UInt<1>("h0")), T_7022) - node T_7024 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) - node T_7025 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) - node T_7026 = or(T_7024, T_7025) - node T_7028 = bits(ex_reg_inst, 30, 25) - node T_7029 = mux(T_7026, UInt<1>("h0"), T_7028) - node T_7030 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) - node T_7032 = eq(ex_ctrl.sel_imm, UInt<3>("h0")) - node T_7033 = eq(ex_ctrl.sel_imm, UInt<3>("h1")) - node T_7034 = or(T_7032, T_7033) - node T_7035 = bits(ex_reg_inst, 11, 8) - node T_7036 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) - node T_7037 = bits(ex_reg_inst, 19, 16) - node T_7038 = bits(ex_reg_inst, 24, 21) - node T_7039 = mux(T_7036, T_7037, T_7038) - node T_7040 = mux(T_7034, T_7035, T_7039) - node T_7041 = mux(T_7030, UInt<1>("h0"), T_7040) - node T_7042 = eq(ex_ctrl.sel_imm, UInt<3>("h0")) - node T_7043 = bits(ex_reg_inst, 7, 7) - node T_7044 = eq(ex_ctrl.sel_imm, UInt<3>("h4")) - node T_7045 = bits(ex_reg_inst, 20, 20) - node T_7046 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) - node T_7047 = bits(ex_reg_inst, 15, 15) - node T_7049 = shl(T_7047, 0) - node T_7050 = mux(T_7046, T_7049, UInt<1>("h0")) - node T_7051 = shl(T_7045, 0) - node T_7052 = mux(T_7044, T_7051, T_7050) - node T_7053 = shl(T_7043, 0) - node T_7054 = mux(T_7042, T_7053, T_7052) - node T_7055 = asUInt(T_7000) - node T_7056 = asUInt(T_7004) - node T_7057 = asUInt(T_7010) - node T_7058 = cat(T_7056, T_7057) - node T_7059 = cat(T_7055, T_7058) - node T_7060 = asUInt(T_7023) - node T_7061 = cat(T_7060, T_7029) - node T_7062 = cat(T_7041, T_7054) - node T_7063 = cat(T_7061, T_7062) - node T_7064 = cat(T_7059, T_7063) - node ex_imm = asSInt(T_7064) - node T_7067 = asSInt(T_6992) - node T_7068 = asSInt(ex_reg_pc) - node T_7069 = eq(UInt<2>("h2"), ex_ctrl.sel_alu1) - node T_7070 = mux(T_7069, T_7068, asSInt(UInt<1>("h0"))) - node T_7071 = eq(UInt<2>("h1"), ex_ctrl.sel_alu1) - node ex_op1 = mux(T_7071, T_7067, T_7070) - node T_7074 = asSInt(T_6995) - node T_7076 = eq(UInt<2>("h1"), ex_ctrl.sel_alu2) - node T_7077 = mux(T_7076, asSInt(UInt<4>("h4")), asSInt(UInt<1>("h0"))) - node T_7078 = eq(UInt<2>("h3"), ex_ctrl.sel_alu2) - node T_7079 = mux(T_7078, ex_imm, T_7077) - node T_7080 = eq(UInt<2>("h2"), ex_ctrl.sel_alu2) - node ex_op2 = mux(T_7080, T_7074, T_7079) - inst alu of ALU - alu.io is invalid - alu.clk <= clk - alu.reset <= reset - alu.io.dw <= ex_ctrl.alu_dw - alu.io.fn <= ex_ctrl.alu_fn - node T_7083 = asUInt(ex_op2) - alu.io.in2 <= T_7083 - node T_7084 = asUInt(ex_op1) - alu.io.in1 <= T_7084 - inst div of MulDiv - div.io is invalid - div.clk <= clk - div.reset <= reset - node T_7086 = and(ex_reg_valid, ex_ctrl.div) - div.io.req.valid <= T_7086 - div.io.req.bits.dw <= ex_ctrl.alu_dw - div.io.req.bits.fn <= ex_ctrl.alu_fn - div.io.req.bits.in1 <= T_6992 - div.io.req.bits.in2 <= T_6995 - div.io.req.bits.tag <= ex_waddr - node T_7088 = eq(ctrl_killd, UInt<1>("h0")) - ex_reg_valid <= T_7088 - node T_7090 = eq(ctrl_killd, UInt<1>("h0")) - node T_7091 = and(T_7090, id_xcpt) - ex_reg_xcpt <= T_7091 - node T_7093 = eq(take_pc_mem_wb, UInt<1>("h0")) - node T_7094 = and(csr.io.interrupt, T_7093) - node T_7095 = and(T_7094, io.imem.resp.valid) - ex_reg_xcpt_interrupt <= T_7095 - when id_xcpt : - ex_reg_cause <= id_cause - skip - node T_7097 = eq(ctrl_killd, UInt<1>("h0")) - when T_7097 : - ex_ctrl <- id_ctrl - ex_ctrl.csr <= id_csr - ex_reg_btb_hit <= io.imem.btb_resp.valid - when io.imem.btb_resp.valid : - ex_reg_btb_resp <- io.imem.btb_resp.bits - skip - node T_7098 = or(id_ctrl.fence_i, id_csr_flush) - ex_reg_flush_pipe <= T_7098 - ex_reg_load_use <= id_load_use - node T_7099 = or(T_6932, T_6934) - node T_7100 = or(T_7099, T_6936) - node T_7101 = or(T_7100, T_6938) - node T_7106 = mux(T_6936, UInt<2>("h2"), UInt<2>("h3")) - node T_7107 = mux(T_6934, UInt<1>("h1"), T_7106) - node T_7108 = mux(T_6932, UInt<1>("h0"), T_7107) - ex_reg_rs_bypass[0] <= T_7101 - ex_reg_rs_lsb[0] <= T_7108 - node T_7110 = eq(T_7101, UInt<1>("h0")) - node T_7111 = and(id_ctrl.rxs1, T_7110) - when T_7111 : - node T_7112 = bits(T_6768, 1, 0) - ex_reg_rs_lsb[0] <= T_7112 - node T_7113 = shr(T_6768, 2) - ex_reg_rs_msb[0] <= T_7113 - skip - node T_7114 = or(T_6940, T_6942) - node T_7115 = or(T_7114, T_6944) - node T_7116 = or(T_7115, T_6946) - node T_7121 = mux(T_6944, UInt<2>("h2"), UInt<2>("h3")) - node T_7122 = mux(T_6942, UInt<1>("h1"), T_7121) - node T_7123 = mux(T_6940, UInt<1>("h0"), T_7122) - ex_reg_rs_bypass[1] <= T_7116 - ex_reg_rs_lsb[1] <= T_7123 - node T_7125 = eq(T_7116, UInt<1>("h0")) - node T_7126 = and(id_ctrl.rxs2, T_7125) - when T_7126 : - node T_7127 = bits(T_6779, 1, 0) - ex_reg_rs_lsb[1] <= T_7127 - node T_7128 = shr(T_6779, 2) - ex_reg_rs_msb[1] <= T_7128 - skip - skip - node T_7130 = eq(ctrl_killd, UInt<1>("h0")) - node T_7131 = or(T_7130, csr.io.interrupt) - when T_7131 : - ex_reg_inst <= io.imem.resp.bits.data[0] - ex_reg_pc <= io.imem.resp.bits.pc - skip - node T_7133 = eq(io.dmem.resp.valid, UInt<1>("h0")) - node wb_dcache_miss = and(wb_ctrl.mem, T_7133) - node T_7136 = eq(io.dmem.req.ready, UInt<1>("h0")) - node T_7137 = and(ex_ctrl.mem, T_7136) - node T_7139 = eq(div.io.req.ready, UInt<1>("h0")) - node T_7140 = and(ex_ctrl.div, T_7139) - node replay_ex_structural = or(T_7137, T_7140) - node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) - node T_7143 = or(replay_ex_structural, replay_ex_load_use) - node replay_ex = and(ex_reg_valid, T_7143) - node T_7145 = or(take_pc_mem_wb, replay_ex) - node T_7147 = eq(ex_reg_valid, UInt<1>("h0")) - node ctrl_killx = or(T_7145, T_7147) - node T_7149 = eq(ex_ctrl.mem_cmd, UInt<5>("h7")) - wire T_7151 : UInt<3>[4] - T_7151[0] <= UInt<3>("h0") - T_7151[1] <= UInt<3>("h4") - T_7151[2] <= UInt<3>("h1") - T_7151[3] <= UInt<3>("h5") - node T_7157 = eq(T_7151[0], ex_ctrl.mem_type) - node T_7158 = eq(T_7151[1], ex_ctrl.mem_type) - node T_7159 = eq(T_7151[2], ex_ctrl.mem_type) - node T_7160 = eq(T_7151[3], ex_ctrl.mem_type) - node T_7162 = or(UInt<1>("h0"), T_7157) - node T_7163 = or(T_7162, T_7158) - node T_7164 = or(T_7163, T_7159) - node T_7165 = or(T_7164, T_7160) - node ex_slow_bypass = or(T_7149, T_7165) - node T_7167 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) - node T_7168 = and(ex_ctrl.fp, io.fpu.illegal_rm) - node ex_xcpt = or(T_7167, T_7168) - node ex_cause = mux(T_7167, ex_reg_cause, UInt<2>("h2")) - node mem_br_taken = bits(mem_reg_wdata, 0, 0) - node T_7173 = asSInt(mem_reg_pc) - node T_7174 = and(mem_ctrl.branch, mem_br_taken) - node T_7175 = eq(UInt<3>("h1"), UInt<3>("h5")) - node T_7177 = bits(mem_reg_inst, 31, 31) - node T_7178 = asSInt(T_7177) - node T_7179 = mux(T_7175, asSInt(UInt<1>("h0")), T_7178) - node T_7180 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_7181 = bits(mem_reg_inst, 30, 20) - node T_7182 = asSInt(T_7181) - node T_7183 = mux(T_7180, T_7182, T_7179) - node T_7184 = neq(UInt<3>("h1"), UInt<3>("h2")) - node T_7185 = neq(UInt<3>("h1"), UInt<3>("h3")) - node T_7186 = and(T_7184, T_7185) - node T_7187 = bits(mem_reg_inst, 19, 12) - node T_7188 = asSInt(T_7187) - node T_7189 = mux(T_7186, T_7179, T_7188) - node T_7190 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_7191 = eq(UInt<3>("h1"), UInt<3>("h5")) - node T_7192 = or(T_7190, T_7191) - node T_7194 = eq(UInt<3>("h1"), UInt<3>("h3")) - node T_7195 = bits(mem_reg_inst, 20, 20) - node T_7196 = asSInt(T_7195) - node T_7197 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_7198 = bits(mem_reg_inst, 7, 7) - node T_7199 = asSInt(T_7198) - node T_7200 = mux(T_7197, T_7199, T_7179) - node T_7201 = mux(T_7194, T_7196, T_7200) - node T_7202 = mux(T_7192, asSInt(UInt<1>("h0")), T_7201) - node T_7203 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_7204 = eq(UInt<3>("h1"), UInt<3>("h5")) - node T_7205 = or(T_7203, T_7204) - node T_7207 = bits(mem_reg_inst, 30, 25) - node T_7208 = mux(T_7205, UInt<1>("h0"), T_7207) - node T_7209 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_7211 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_7212 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_7213 = or(T_7211, T_7212) - node T_7214 = bits(mem_reg_inst, 11, 8) - node T_7215 = eq(UInt<3>("h1"), UInt<3>("h5")) - node T_7216 = bits(mem_reg_inst, 19, 16) - node T_7217 = bits(mem_reg_inst, 24, 21) - node T_7218 = mux(T_7215, T_7216, T_7217) - node T_7219 = mux(T_7213, T_7214, T_7218) - node T_7220 = mux(T_7209, UInt<1>("h0"), T_7219) - node T_7221 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_7222 = bits(mem_reg_inst, 7, 7) - node T_7223 = eq(UInt<3>("h1"), UInt<3>("h4")) - node T_7224 = bits(mem_reg_inst, 20, 20) - node T_7225 = eq(UInt<3>("h1"), UInt<3>("h5")) - node T_7226 = bits(mem_reg_inst, 15, 15) - node T_7228 = shl(T_7226, 0) - node T_7229 = mux(T_7225, T_7228, UInt<1>("h0")) - node T_7230 = shl(T_7224, 0) - node T_7231 = mux(T_7223, T_7230, T_7229) - node T_7232 = shl(T_7222, 0) - node T_7233 = mux(T_7221, T_7232, T_7231) - node T_7234 = asUInt(T_7179) - node T_7235 = asUInt(T_7183) - node T_7236 = asUInt(T_7189) - node T_7237 = cat(T_7235, T_7236) - node T_7238 = cat(T_7234, T_7237) - node T_7239 = asUInt(T_7202) - node T_7240 = cat(T_7239, T_7208) - node T_7241 = cat(T_7220, T_7233) - node T_7242 = cat(T_7240, T_7241) - node T_7243 = cat(T_7238, T_7242) - node T_7244 = asSInt(T_7243) - node T_7245 = eq(UInt<3>("h3"), UInt<3>("h5")) - node T_7247 = bits(mem_reg_inst, 31, 31) - node T_7248 = asSInt(T_7247) - node T_7249 = mux(T_7245, asSInt(UInt<1>("h0")), T_7248) - node T_7250 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_7251 = bits(mem_reg_inst, 30, 20) - node T_7252 = asSInt(T_7251) - node T_7253 = mux(T_7250, T_7252, T_7249) - node T_7254 = neq(UInt<3>("h3"), UInt<3>("h2")) - node T_7255 = neq(UInt<3>("h3"), UInt<3>("h3")) - node T_7256 = and(T_7254, T_7255) - node T_7257 = bits(mem_reg_inst, 19, 12) - node T_7258 = asSInt(T_7257) - node T_7259 = mux(T_7256, T_7249, T_7258) - node T_7260 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_7261 = eq(UInt<3>("h3"), UInt<3>("h5")) - node T_7262 = or(T_7260, T_7261) - node T_7264 = eq(UInt<3>("h3"), UInt<3>("h3")) - node T_7265 = bits(mem_reg_inst, 20, 20) - node T_7266 = asSInt(T_7265) - node T_7267 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_7268 = bits(mem_reg_inst, 7, 7) - node T_7269 = asSInt(T_7268) - node T_7270 = mux(T_7267, T_7269, T_7249) - node T_7271 = mux(T_7264, T_7266, T_7270) - node T_7272 = mux(T_7262, asSInt(UInt<1>("h0")), T_7271) - node T_7273 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_7274 = eq(UInt<3>("h3"), UInt<3>("h5")) - node T_7275 = or(T_7273, T_7274) - node T_7277 = bits(mem_reg_inst, 30, 25) - node T_7278 = mux(T_7275, UInt<1>("h0"), T_7277) - node T_7279 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_7281 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_7282 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_7283 = or(T_7281, T_7282) - node T_7284 = bits(mem_reg_inst, 11, 8) - node T_7285 = eq(UInt<3>("h3"), UInt<3>("h5")) - node T_7286 = bits(mem_reg_inst, 19, 16) - node T_7287 = bits(mem_reg_inst, 24, 21) - node T_7288 = mux(T_7285, T_7286, T_7287) - node T_7289 = mux(T_7283, T_7284, T_7288) - node T_7290 = mux(T_7279, UInt<1>("h0"), T_7289) - node T_7291 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_7292 = bits(mem_reg_inst, 7, 7) - node T_7293 = eq(UInt<3>("h3"), UInt<3>("h4")) - node T_7294 = bits(mem_reg_inst, 20, 20) - node T_7295 = eq(UInt<3>("h3"), UInt<3>("h5")) - node T_7296 = bits(mem_reg_inst, 15, 15) - node T_7298 = shl(T_7296, 0) - node T_7299 = mux(T_7295, T_7298, UInt<1>("h0")) - node T_7300 = shl(T_7294, 0) - node T_7301 = mux(T_7293, T_7300, T_7299) - node T_7302 = shl(T_7292, 0) - node T_7303 = mux(T_7291, T_7302, T_7301) - node T_7304 = asUInt(T_7249) - node T_7305 = asUInt(T_7253) - node T_7306 = asUInt(T_7259) - node T_7307 = cat(T_7305, T_7306) - node T_7308 = cat(T_7304, T_7307) - node T_7309 = asUInt(T_7272) - node T_7310 = cat(T_7309, T_7278) - node T_7311 = cat(T_7290, T_7303) - node T_7312 = cat(T_7310, T_7311) - node T_7313 = cat(T_7308, T_7312) - node T_7314 = asSInt(T_7313) - node T_7316 = mux(mem_ctrl.jal, T_7314, asSInt(UInt<4>("h4"))) - node T_7317 = mux(T_7174, T_7244, T_7316) - node T_7318 = add(T_7173, T_7317) - node T_7319 = tail(T_7318, 1) - node mem_br_target = asSInt(T_7319) - node T_7321 = asSInt(mem_reg_wdata) - node T_7322 = mux(mem_ctrl.jalr, mem_br_target, T_7321) - node mem_int_wdata = asUInt(T_7322) - node T_7324 = shr(mem_reg_wdata, 38) - node T_7325 = bits(mem_reg_wdata, 39, 38) - node T_7327 = eq(T_7324, UInt<1>("h0")) - node T_7329 = eq(T_7324, UInt<1>("h1")) - node T_7330 = or(T_7327, T_7329) - node T_7332 = neq(T_7325, UInt<1>("h0")) - node T_7333 = asSInt(T_7324) - node T_7335 = eq(T_7333, asSInt(UInt<1>("h1"))) - node T_7336 = asSInt(T_7324) - node T_7338 = eq(T_7336, asSInt(UInt<2>("h2"))) - node T_7339 = or(T_7335, T_7338) - node T_7340 = asSInt(T_7325) - node T_7342 = eq(T_7340, asSInt(UInt<1>("h1"))) - node T_7343 = bits(T_7325, 0, 0) - node T_7344 = mux(T_7339, T_7342, T_7343) - node T_7345 = mux(T_7330, T_7332, T_7344) - node T_7346 = bits(mem_reg_wdata, 38, 0) - node T_7347 = cat(T_7345, T_7346) - node T_7348 = asSInt(T_7347) - node T_7349 = mux(mem_ctrl.jalr, T_7348, mem_br_target) - node T_7351 = and(T_7349, asSInt(UInt<2>("h2"))) - node T_7352 = asSInt(T_7351) - node mem_npc = asUInt(T_7352) - node T_7354 = neq(mem_npc, ex_reg_pc) - node T_7356 = eq(ex_reg_valid, UInt<1>("h0")) - node mem_wrong_npc = or(T_7354, T_7356) - node mem_npc_misaligned = bits(mem_npc, 1, 1) - node T_7359 = and(mem_wrong_npc, mem_reg_valid) - node T_7360 = or(mem_ctrl.branch, mem_ctrl.jalr) - node T_7361 = or(T_7360, mem_ctrl.jal) - node mem_misprediction = and(T_7359, T_7361) - node T_7363 = or(mem_misprediction, mem_reg_flush_pipe) - node want_take_pc_mem = and(mem_reg_valid, T_7363) - node T_7366 = eq(mem_npc_misaligned, UInt<1>("h0")) - node T_7367 = and(want_take_pc_mem, T_7366) - take_pc_mem <= T_7367 - node T_7369 = eq(ctrl_killx, UInt<1>("h0")) - mem_reg_valid <= T_7369 - node T_7371 = eq(take_pc_mem_wb, UInt<1>("h0")) - node T_7372 = and(T_7371, replay_ex) - mem_reg_replay <= T_7372 - node T_7374 = eq(ctrl_killx, UInt<1>("h0")) - node T_7375 = and(T_7374, ex_xcpt) - mem_reg_xcpt <= T_7375 - node T_7377 = eq(take_pc_mem_wb, UInt<1>("h0")) - node T_7378 = and(T_7377, ex_reg_xcpt_interrupt) - mem_reg_xcpt_interrupt <= T_7378 - when ex_xcpt : - mem_reg_cause <= ex_cause - skip - node T_7379 = or(ex_reg_valid, ex_reg_xcpt_interrupt) - when T_7379 : - mem_ctrl <- ex_ctrl - mem_reg_btb_hit <= ex_reg_btb_hit - when ex_reg_btb_hit : - mem_reg_btb_resp <- ex_reg_btb_resp - skip - mem_reg_flush_pipe <= ex_reg_flush_pipe - mem_reg_slow_bypass <= ex_slow_bypass - mem_reg_inst <= ex_reg_inst - mem_reg_pc <= ex_reg_pc - mem_reg_wdata <= alu.io.out - node T_7380 = or(ex_ctrl.mem, ex_ctrl.rocc) - node T_7381 = and(ex_ctrl.rxs2, T_7380) - when T_7381 : - mem_reg_rs2 <= T_6995 - skip - skip - node T_7382 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) - node T_7383 = and(want_take_pc_mem, mem_npc_misaligned) - node T_7385 = and(mem_reg_valid, mem_ctrl.mem) - node T_7386 = and(T_7385, io.dmem.xcpt.ma.st) - node T_7388 = and(mem_reg_valid, mem_ctrl.mem) - node T_7389 = and(T_7388, io.dmem.xcpt.ma.ld) - node T_7391 = and(mem_reg_valid, mem_ctrl.mem) - node T_7392 = and(T_7391, io.dmem.xcpt.pf.st) - node T_7394 = and(mem_reg_valid, mem_ctrl.mem) - node T_7395 = and(T_7394, io.dmem.xcpt.pf.ld) - node T_7397 = or(T_7382, T_7383) - node T_7398 = or(T_7397, T_7386) - node T_7399 = or(T_7398, T_7389) - node T_7400 = or(T_7399, T_7392) - node mem_xcpt = or(T_7400, T_7395) - node T_7402 = mux(T_7392, UInt<3>("h7"), UInt<3>("h5")) - node T_7403 = mux(T_7389, UInt<3>("h4"), T_7402) - node T_7404 = mux(T_7386, UInt<3>("h6"), T_7403) - node T_7405 = mux(T_7383, UInt<1>("h0"), T_7404) - node mem_cause = mux(T_7382, mem_reg_cause, T_7405) - node T_7407 = and(mem_reg_valid, mem_ctrl.wxd) - node dcache_kill_mem = and(T_7407, io.dmem.replay_next.valid) - node T_7409 = and(mem_reg_valid, mem_ctrl.fp) - node fpu_kill_mem = and(T_7409, io.fpu.nack_mem) - node T_7411 = or(dcache_kill_mem, mem_reg_replay) - node replay_mem = or(T_7411, fpu_kill_mem) - node T_7413 = or(dcache_kill_mem, take_pc_wb) - node T_7414 = or(T_7413, mem_reg_xcpt) - node T_7416 = eq(mem_reg_valid, UInt<1>("h0")) - node killm_common = or(T_7414, T_7416) - node T_7418 = and(div.io.req.ready, div.io.req.valid) - reg T_7419 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_7419) - T_7419 <= T_7418 - node T_7420 = and(killm_common, T_7419) - div.io.kill <= T_7420 - node T_7421 = or(killm_common, mem_xcpt) - node ctrl_killm = or(T_7421, fpu_kill_mem) - node T_7424 = eq(ctrl_killm, UInt<1>("h0")) - wb_reg_valid <= T_7424 - node T_7426 = eq(take_pc_wb, UInt<1>("h0")) - node T_7427 = and(replay_mem, T_7426) - wb_reg_replay <= T_7427 - node T_7429 = eq(take_pc_wb, UInt<1>("h0")) - node T_7430 = and(mem_xcpt, T_7429) - wb_reg_xcpt <= T_7430 - when mem_xcpt : - wb_reg_cause <= mem_cause - skip - node T_7431 = or(mem_reg_valid, mem_reg_replay) - node T_7432 = or(T_7431, mem_reg_xcpt_interrupt) - when T_7432 : - wb_ctrl <- mem_ctrl - node T_7433 = and(mem_ctrl.fp, mem_ctrl.wxd) - node T_7434 = mux(T_7433, io.fpu.toint_data, mem_int_wdata) - wb_reg_wdata <= T_7434 - when mem_ctrl.rocc : - wb_reg_rs2 <= mem_reg_rs2 - skip - wb_reg_inst <= mem_reg_inst - wb_reg_pc <= mem_reg_pc - skip - node T_7435 = or(wb_ctrl.div, wb_dcache_miss) - node wb_set_sboard = or(T_7435, wb_ctrl.rocc) - node replay_wb_common = or(io.dmem.resp.bits.nack, wb_reg_replay) - node T_7438 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7440 = eq(replay_wb_common, UInt<1>("h0")) - node wb_rocc_val = and(T_7438, T_7440) - node T_7442 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7444 = eq(io.rocc.cmd.ready, UInt<1>("h0")) - node T_7445 = and(T_7442, T_7444) - node replay_wb = or(replay_wb_common, T_7445) - node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) - node T_7448 = or(replay_wb, wb_xcpt) - node T_7449 = or(T_7448, csr.io.eret) - take_pc_wb <= T_7449 - when wb_rocc_val : - node T_7451 = eq(io.rocc.cmd.ready, UInt<1>("h0")) - wb_reg_rocc_pending <= T_7451 - skip - when wb_reg_xcpt : - wb_reg_rocc_pending <= UInt<1>("h0") - skip - node T_7453 = bits(io.dmem.resp.bits.tag, 0, 0) - node T_7454 = bits(T_7453, 0, 0) - node dmem_resp_xpu = eq(T_7454, UInt<1>("h0")) - node T_7457 = bits(io.dmem.resp.bits.tag, 0, 0) - node dmem_resp_fpu = bits(T_7457, 0, 0) - node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) - node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) - node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data) - node T_7462 = and(wb_reg_valid, wb_ctrl.wxd) - node T_7464 = eq(T_7462, UInt<1>("h0")) - div.io.resp.ready <= T_7464 - wire ll_wdata : UInt - ll_wdata <= div.io.resp.bits.data - wire ll_waddr : UInt - ll_waddr <= div.io.resp.bits.tag - node T_7467 = and(div.io.resp.ready, div.io.resp.valid) - wire ll_wen : UInt<1> - ll_wen <= T_7467 - node T_7469 = and(dmem_resp_replay, dmem_resp_xpu) - when T_7469 : - div.io.resp.ready <= UInt<1>("h0") - ll_waddr <= dmem_resp_waddr - ll_wen <= UInt<1>("h1") - skip - node T_7473 = eq(replay_wb, UInt<1>("h0")) - node T_7474 = and(wb_reg_valid, T_7473) - node T_7476 = eq(csr.io.csr_xcpt, UInt<1>("h0")) - node wb_valid = and(T_7474, T_7476) - node wb_wen = and(wb_valid, wb_ctrl.wxd) - node rf_wen = or(wb_wen, ll_wen) - node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) - node T_7481 = and(dmem_resp_valid, dmem_resp_xpu) - node T_7482 = neq(wb_ctrl.csr, UInt<3>("h0")) - node T_7483 = mux(T_7482, csr.io.rw.rdata, wb_reg_wdata) - node T_7484 = mux(ll_wen, ll_wdata, T_7483) - node rf_wdata = mux(T_7481, io.dmem.resp.bits.data, T_7484) - when rf_wen : - node T_7487 = neq(rf_waddr, UInt<1>("h0")) - when T_7487 : - node T_7488 = bits(rf_waddr, 4, 0) - node T_7489 = not(T_7488) - T_6766.T_7490.addr <= T_7489 - T_6766.T_7490.en <= UInt<1>("h1") - T_6766.T_7490.data <= rf_wdata - T_6766.T_7490.mask <= UInt<1>("h1") - node T_7491 = eq(rf_waddr, id_raddr1) - when T_7491 : - T_6768 <= rf_wdata - skip - node T_7492 = eq(rf_waddr, id_raddr2) - when T_7492 : - T_6779 <= rf_wdata - skip - skip - skip - csr.io.exception <= wb_reg_xcpt - csr.io.cause <= wb_reg_cause - csr.io.retire <= wb_valid - io.host <- csr.io.host - io.fpu.fcsr_rm <= csr.io.fcsr_rm - csr.io.fcsr_flags <- io.fpu.fcsr_flags - csr.io.rocc <- io.rocc - csr.io.pc <= wb_reg_pc - csr.io.uarch_counters[0] <= UInt<1>("h0") - csr.io.uarch_counters[1] <= UInt<1>("h0") - csr.io.uarch_counters[2] <= UInt<1>("h0") - csr.io.uarch_counters[3] <= UInt<1>("h0") - csr.io.uarch_counters[4] <= UInt<1>("h0") - csr.io.uarch_counters[5] <= UInt<1>("h0") - csr.io.uarch_counters[6] <= UInt<1>("h0") - csr.io.uarch_counters[7] <= UInt<1>("h0") - csr.io.uarch_counters[8] <= UInt<1>("h0") - csr.io.uarch_counters[9] <= UInt<1>("h0") - csr.io.uarch_counters[10] <= UInt<1>("h0") - csr.io.uarch_counters[11] <= UInt<1>("h0") - csr.io.uarch_counters[12] <= UInt<1>("h0") - csr.io.uarch_counters[13] <= UInt<1>("h0") - csr.io.uarch_counters[14] <= UInt<1>("h0") - csr.io.uarch_counters[15] <= UInt<1>("h0") - io.ptw.ptbr <= csr.io.ptbr - io.ptw.invalidate <= csr.io.fatc - io.ptw.status <- csr.io.status - node T_7509 = bits(wb_reg_inst, 31, 20) - csr.io.rw.addr <= T_7509 - node T_7510 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h0")) - csr.io.rw.cmd <= T_7510 - csr.io.rw.wdata <= wb_reg_wdata - node T_7512 = neq(id_raddr1, UInt<1>("h0")) - node T_7513 = and(id_ctrl.rxs1, T_7512) - node T_7515 = neq(id_raddr2, UInt<1>("h0")) - node T_7516 = and(id_ctrl.rxs2, T_7515) - node T_7518 = neq(id_waddr, UInt<1>("h0")) - node T_7519 = and(id_ctrl.wxd, T_7518) - reg T_7521 : UInt<32>, clk with : - reset => (reset, UInt<32>("h0")) - node T_7524 = dshl(UInt<1>("h1"), ll_waddr) - node T_7526 = mux(ll_wen, T_7524, UInt<1>("h0")) - node T_7527 = not(T_7526) - node T_7528 = and(T_7521, T_7527) - node T_7529 = or(UInt<1>("h0"), ll_wen) - when T_7529 : - T_7521 <= T_7528 - skip - node T_7530 = dshr(T_7528, id_raddr1) - node T_7531 = bits(T_7530, 0, 0) - node T_7532 = and(T_7513, T_7531) - node T_7533 = dshr(T_7528, id_raddr2) - node T_7534 = bits(T_7533, 0, 0) - node T_7535 = and(T_7516, T_7534) - node T_7536 = dshr(T_7528, id_waddr) - node T_7537 = bits(T_7536, 0, 0) - node T_7538 = and(T_7519, T_7537) - node T_7539 = or(T_7532, T_7535) - node id_sboard_hazard = or(T_7539, T_7538) - node T_7541 = and(wb_set_sboard, wb_wen) - node T_7543 = dshl(UInt<1>("h1"), wb_waddr) - node T_7545 = mux(T_7541, T_7543, UInt<1>("h0")) - node T_7546 = or(T_7528, T_7545) - node T_7547 = or(T_7529, T_7541) - when T_7547 : - T_7521 <= T_7546 - skip - node T_7548 = neq(ex_ctrl.csr, UInt<3>("h0")) - node T_7549 = or(T_7548, ex_ctrl.jalr) - node T_7550 = or(T_7549, ex_ctrl.mem) - node T_7551 = or(T_7550, ex_ctrl.div) - node T_7552 = or(T_7551, ex_ctrl.fp) - node ex_cannot_bypass = or(T_7552, ex_ctrl.rocc) - node T_7554 = eq(id_raddr1, ex_waddr) - node T_7555 = and(T_7513, T_7554) - node T_7556 = eq(id_raddr2, ex_waddr) - node T_7557 = and(T_7516, T_7556) - node T_7558 = eq(id_waddr, ex_waddr) - node T_7559 = and(T_7519, T_7558) - node T_7560 = or(T_7555, T_7557) - node T_7561 = or(T_7560, T_7559) - node data_hazard_ex = and(ex_ctrl.wxd, T_7561) - node T_7563 = eq(id_raddr1, ex_waddr) - node T_7564 = and(io.fpu.dec.ren1, T_7563) - node T_7565 = eq(id_raddr2, ex_waddr) - node T_7566 = and(io.fpu.dec.ren2, T_7565) - node T_7567 = eq(id_raddr3, ex_waddr) - node T_7568 = and(io.fpu.dec.ren3, T_7567) - node T_7569 = eq(id_waddr, ex_waddr) - node T_7570 = and(io.fpu.dec.wen, T_7569) - node T_7571 = or(T_7564, T_7566) - node T_7572 = or(T_7571, T_7568) - node T_7573 = or(T_7572, T_7570) - node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7573) - node T_7575 = and(data_hazard_ex, ex_cannot_bypass) - node T_7576 = or(T_7575, fp_data_hazard_ex) - node id_ex_hazard = and(ex_reg_valid, T_7576) - node mem_mem_cmd_bh = and(UInt<1>("h1"), mem_reg_slow_bypass) - node T_7580 = neq(mem_ctrl.csr, UInt<3>("h0")) - node T_7581 = and(mem_ctrl.mem, mem_mem_cmd_bh) - node T_7582 = or(T_7580, T_7581) - node T_7583 = or(T_7582, mem_ctrl.div) - node T_7584 = or(T_7583, mem_ctrl.fp) - node mem_cannot_bypass = or(T_7584, mem_ctrl.rocc) - node T_7586 = eq(id_raddr1, mem_waddr) - node T_7587 = and(T_7513, T_7586) - node T_7588 = eq(id_raddr2, mem_waddr) - node T_7589 = and(T_7516, T_7588) - node T_7590 = eq(id_waddr, mem_waddr) - node T_7591 = and(T_7519, T_7590) - node T_7592 = or(T_7587, T_7589) - node T_7593 = or(T_7592, T_7591) - node data_hazard_mem = and(mem_ctrl.wxd, T_7593) - node T_7595 = eq(id_raddr1, mem_waddr) - node T_7596 = and(io.fpu.dec.ren1, T_7595) - node T_7597 = eq(id_raddr2, mem_waddr) - node T_7598 = and(io.fpu.dec.ren2, T_7597) - node T_7599 = eq(id_raddr3, mem_waddr) - node T_7600 = and(io.fpu.dec.ren3, T_7599) - node T_7601 = eq(id_waddr, mem_waddr) - node T_7602 = and(io.fpu.dec.wen, T_7601) - node T_7603 = or(T_7596, T_7598) - node T_7604 = or(T_7603, T_7600) - node T_7605 = or(T_7604, T_7602) - node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7605) - node T_7607 = and(data_hazard_mem, mem_cannot_bypass) - node T_7608 = or(T_7607, fp_data_hazard_mem) - node id_mem_hazard = and(mem_reg_valid, T_7608) - node T_7610 = and(mem_reg_valid, data_hazard_mem) - node T_7611 = and(T_7610, mem_ctrl.mem) - id_load_use <= T_7611 - node T_7612 = eq(id_raddr1, wb_waddr) - node T_7613 = and(T_7513, T_7612) - node T_7614 = eq(id_raddr2, wb_waddr) - node T_7615 = and(T_7516, T_7614) - node T_7616 = eq(id_waddr, wb_waddr) - node T_7617 = and(T_7519, T_7616) - node T_7618 = or(T_7613, T_7615) - node T_7619 = or(T_7618, T_7617) - node data_hazard_wb = and(wb_ctrl.wxd, T_7619) - node T_7621 = eq(id_raddr1, wb_waddr) - node T_7622 = and(io.fpu.dec.ren1, T_7621) - node T_7623 = eq(id_raddr2, wb_waddr) - node T_7624 = and(io.fpu.dec.ren2, T_7623) - node T_7625 = eq(id_raddr3, wb_waddr) - node T_7626 = and(io.fpu.dec.ren3, T_7625) - node T_7627 = eq(id_waddr, wb_waddr) - node T_7628 = and(io.fpu.dec.wen, T_7627) - node T_7629 = or(T_7622, T_7624) - node T_7630 = or(T_7629, T_7626) - node T_7631 = or(T_7630, T_7628) - node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7631) - node T_7633 = and(data_hazard_wb, wb_set_sboard) - node T_7634 = or(T_7633, fp_data_hazard_wb) - node id_wb_hazard = and(wb_reg_valid, T_7634) - reg T_7637 : UInt<32>, clk with : - reset => (reset, UInt<32>("h0")) - node T_7639 = and(wb_dcache_miss, wb_ctrl.wfd) - node T_7640 = or(T_7639, io.fpu.sboard_set) - node T_7641 = and(T_7640, wb_valid) - node T_7643 = dshl(UInt<1>("h1"), wb_waddr) - node T_7645 = mux(T_7641, T_7643, UInt<1>("h0")) - node T_7646 = or(T_7637, T_7645) - node T_7647 = or(UInt<1>("h0"), T_7641) - when T_7647 : - T_7637 <= T_7646 - skip - node T_7648 = and(dmem_resp_replay, dmem_resp_fpu) - node T_7650 = dshl(UInt<1>("h1"), dmem_resp_waddr) - node T_7652 = mux(T_7648, T_7650, UInt<1>("h0")) - node T_7653 = not(T_7652) - node T_7654 = and(T_7646, T_7653) - node T_7655 = or(T_7647, T_7648) - when T_7655 : - T_7637 <= T_7654 - skip - node T_7657 = dshl(UInt<1>("h1"), io.fpu.sboard_clra) - node T_7659 = mux(io.fpu.sboard_clr, T_7657, UInt<1>("h0")) - node T_7660 = not(T_7659) - node T_7661 = and(T_7654, T_7660) - node T_7662 = or(T_7655, io.fpu.sboard_clr) - when T_7662 : - T_7637 <= T_7661 - skip - node T_7664 = eq(io.fpu.fcsr_rdy, UInt<1>("h0")) - node T_7665 = and(id_csr_en, T_7664) - node T_7666 = dshr(T_7637, id_raddr1) - node T_7667 = bits(T_7666, 0, 0) - node T_7668 = and(io.fpu.dec.ren1, T_7667) - node T_7669 = dshr(T_7637, id_raddr2) - node T_7670 = bits(T_7669, 0, 0) - node T_7671 = and(io.fpu.dec.ren2, T_7670) - node T_7672 = dshr(T_7637, id_raddr3) - node T_7673 = bits(T_7672, 0, 0) - node T_7674 = and(io.fpu.dec.ren3, T_7673) - node T_7675 = dshr(T_7637, id_waddr) - node T_7676 = bits(T_7675, 0, 0) - node T_7677 = and(io.fpu.dec.wen, T_7676) - node T_7678 = or(T_7668, T_7671) - node T_7679 = or(T_7678, T_7674) - node T_7680 = or(T_7679, T_7677) - node id_stall_fpu = or(T_7665, T_7680) - node T_7682 = or(id_ex_hazard, id_mem_hazard) - node T_7683 = or(T_7682, id_wb_hazard) - node T_7684 = or(T_7683, id_sboard_hazard) - node T_7685 = and(id_ctrl.fp, id_stall_fpu) - node T_7686 = or(T_7684, T_7685) - node T_7688 = eq(io.dmem.req.ready, UInt<1>("h0")) - node T_7689 = and(id_ctrl.mem, T_7688) - node T_7690 = or(T_7686, T_7689) - node T_7692 = and(UInt<1>("h0"), wb_reg_rocc_pending) - node T_7693 = and(T_7692, id_ctrl.rocc) - node T_7695 = eq(io.rocc.cmd.ready, UInt<1>("h0")) - node T_7696 = and(T_7693, T_7695) - node T_7697 = or(T_7690, T_7696) - node T_7698 = or(T_7697, id_do_fence) - node ctrl_stalld = or(T_7698, csr.io.csr_stall) - node T_7701 = eq(io.imem.resp.valid, UInt<1>("h0")) - node T_7702 = or(T_7701, take_pc_mem_wb) - node T_7703 = or(T_7702, ctrl_stalld) - node T_7704 = or(T_7703, csr.io.interrupt) - ctrl_killd <= T_7704 - io.imem.req.valid <= take_pc_mem_wb - node T_7705 = or(wb_xcpt, csr.io.eret) - node T_7706 = mux(replay_wb, wb_reg_pc, mem_npc) - node T_7707 = mux(T_7705, csr.io.evec, T_7706) - io.imem.req.bits.pc <= T_7707 - node T_7708 = and(wb_reg_valid, wb_ctrl.fence_i) - io.imem.invalidate <= T_7708 - node T_7710 = eq(ctrl_stalld, UInt<1>("h0")) - node T_7711 = or(T_7710, csr.io.interrupt) - io.imem.resp.ready <= T_7711 - node T_7713 = eq(mem_npc_misaligned, UInt<1>("h0")) - node T_7714 = and(mem_reg_valid, T_7713) - node T_7715 = and(T_7714, mem_wrong_npc) - node T_7716 = and(mem_ctrl.branch, mem_br_taken) - node T_7717 = or(T_7716, mem_ctrl.jalr) - node T_7718 = or(T_7717, mem_ctrl.jal) - node T_7719 = and(T_7715, T_7718) - node T_7721 = eq(take_pc_wb, UInt<1>("h0")) - node T_7722 = and(T_7719, T_7721) - io.imem.btb_update.valid <= T_7722 - node T_7723 = or(mem_ctrl.jal, mem_ctrl.jalr) - io.imem.btb_update.bits.isJump <= T_7723 - node T_7724 = bits(mem_reg_inst, 19, 15) - node T_7727 = and(T_7724, UInt<5>("h19")) - node T_7728 = eq(UInt<1>("h1"), T_7727) - node T_7729 = and(mem_ctrl.jalr, T_7728) - io.imem.btb_update.bits.isReturn <= T_7729 - io.imem.btb_update.bits.pc <= mem_reg_pc - io.imem.btb_update.bits.target <= io.imem.req.bits.pc - io.imem.btb_update.bits.br_pc <= mem_reg_pc - io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit - io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp - node T_7730 = and(mem_reg_valid, mem_ctrl.branch) - node T_7732 = eq(take_pc_wb, UInt<1>("h0")) - node T_7733 = and(T_7730, T_7732) - io.imem.bht_update.valid <= T_7733 - io.imem.bht_update.bits.pc <= mem_reg_pc - io.imem.bht_update.bits.taken <= mem_br_taken - io.imem.bht_update.bits.mispredict <= mem_wrong_npc - io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7734 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) - node T_7736 = eq(mem_npc_misaligned, UInt<1>("h0")) - node T_7737 = and(T_7734, T_7736) - node T_7739 = eq(take_pc_wb, UInt<1>("h0")) - node T_7740 = and(T_7737, T_7739) - io.imem.ras_update.valid <= T_7740 - io.imem.ras_update.bits.returnAddr <= mem_int_wdata - node T_7741 = bits(mem_waddr, 0, 0) - node T_7742 = and(mem_ctrl.wxd, T_7741) - io.imem.ras_update.bits.isCall <= T_7742 - io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn - io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7744 = eq(ctrl_killd, UInt<1>("h0")) - node T_7745 = and(T_7744, id_ctrl.fp) - io.fpu.valid <= T_7745 - io.fpu.killx <= ctrl_killx - io.fpu.killm <= killm_common - io.fpu.inst <= io.imem.resp.bits.data[0] - io.fpu.fromint_data <= T_6992 - node T_7746 = and(dmem_resp_valid, dmem_resp_fpu) - io.fpu.dmem_resp_val <= T_7746 - io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass - io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ - io.fpu.dmem_resp_tag <= dmem_resp_waddr - node T_7747 = and(ex_reg_valid, ex_ctrl.mem) - io.dmem.req.valid <= T_7747 - node T_7748 = or(killm_common, mem_xcpt) - io.dmem.req.bits.kill <= T_7748 - io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd - io.dmem.req.bits.typ <= ex_ctrl.mem_type - io.dmem.req.bits.phys <= UInt<1>("h0") - node T_7750 = shr(T_6992, 38) - node T_7751 = bits(alu.io.adder_out, 39, 38) - node T_7753 = eq(T_7750, UInt<1>("h0")) - node T_7755 = eq(T_7750, UInt<1>("h1")) - node T_7756 = or(T_7753, T_7755) - node T_7758 = neq(T_7751, UInt<1>("h0")) - node T_7759 = asSInt(T_7750) - node T_7761 = eq(T_7759, asSInt(UInt<1>("h1"))) - node T_7762 = asSInt(T_7750) - node T_7764 = eq(T_7762, asSInt(UInt<2>("h2"))) - node T_7765 = or(T_7761, T_7764) - node T_7766 = asSInt(T_7751) - node T_7768 = eq(T_7766, asSInt(UInt<1>("h1"))) - node T_7769 = bits(T_7751, 0, 0) - node T_7770 = mux(T_7765, T_7768, T_7769) - node T_7771 = mux(T_7756, T_7758, T_7770) - node T_7772 = bits(alu.io.adder_out, 38, 0) - node T_7773 = cat(T_7771, T_7772) - io.dmem.req.bits.addr <= T_7773 - node T_7774 = cat(ex_waddr, ex_ctrl.fp) - io.dmem.req.bits.tag <= T_7774 - node T_7775 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) - io.dmem.req.bits.data <= T_7775 - io.dmem.invalidate_lr <= wb_xcpt - io.rocc.cmd.valid <= wb_rocc_val - node T_7777 = neq(csr.io.status.xs, UInt<1>("h0")) - node T_7778 = and(wb_xcpt, T_7777) - io.rocc.exception <= T_7778 - node T_7780 = neq(csr.io.status.prv, UInt<1>("h0")) - io.rocc.s <= T_7780 - wire T_7799 : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} - T_7799 is invalid - node T_7808 = bits(wb_reg_inst, 6, 0) - T_7799.opcode <= T_7808 - node T_7809 = bits(wb_reg_inst, 11, 7) - T_7799.rd <= T_7809 - node T_7810 = bits(wb_reg_inst, 12, 12) - T_7799.xs2 <= T_7810 - node T_7811 = bits(wb_reg_inst, 13, 13) - T_7799.xs1 <= T_7811 - node T_7812 = bits(wb_reg_inst, 14, 14) - T_7799.xd <= T_7812 - node T_7813 = bits(wb_reg_inst, 19, 15) - T_7799.rs1 <= T_7813 - node T_7814 = bits(wb_reg_inst, 24, 20) - T_7799.rs2 <= T_7814 - node T_7815 = bits(wb_reg_inst, 31, 25) - T_7799.funct <= T_7815 - io.rocc.cmd.bits.inst <- T_7799 - io.rocc.cmd.bits.rs1 <= wb_reg_wdata - io.rocc.cmd.bits.rs2 <= wb_reg_rs2 - node T_7816 = bits(csr.io.time, 32, 0) - node T_7818 = mux(rf_wen, rf_waddr, UInt<1>("h0")) - node T_7819 = bits(wb_reg_inst, 19, 15) - reg T_7820 : UInt, clk with : - reset => (UInt<1>("h0"), T_7820) - T_7820 <= T_6992 - reg T_7821 : UInt, clk with : - reset => (UInt<1>("h0"), T_7821) - T_7821 <= T_7820 - node T_7822 = bits(wb_reg_inst, 24, 20) - reg T_7823 : UInt, clk with : - reset => (UInt<1>("h0"), T_7823) - T_7823 <= T_6995 - reg T_7824 : UInt, clk with : - reset => (UInt<1>("h0"), T_7824) - T_7824 <= T_7823 - node T_7826 = eq(reset, UInt<1>("h0")) - when T_7826 : - printf(clk, UInt<1>("h1"), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst) - skip - module BTB : - input clk : Clock - input reset : UInt<1> - output io : {flip req : { valid : UInt<1>, bits : { addr : UInt<39>}}, resp : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, flip btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>} - io is invalid - reg idxValid : UInt<62>, clk with : - reset => (reset, UInt<62>("h0")) - mem idxs : - data-type => UInt<12> - depth => 62 - write-latency => 1 - read-latency => 0 - reader => T_1699 - reader => T_1702 - reader => T_1705 - reader => T_1708 - reader => T_1711 - reader => T_1714 - reader => T_1717 - reader => T_1720 - reader => T_1723 - reader => T_1726 - reader => T_1729 - reader => T_1732 - reader => T_1735 - reader => T_1738 - reader => T_1741 - reader => T_1744 - reader => T_1747 - reader => T_1750 - reader => T_1753 - reader => T_1756 - reader => T_1759 - reader => T_1762 - reader => T_1765 - reader => T_1768 - reader => T_1771 - reader => T_1774 - reader => T_1777 - reader => T_1780 - reader => T_1783 - reader => T_1786 - reader => T_1789 - reader => T_1792 - reader => T_1795 - reader => T_1798 - reader => T_1801 - reader => T_1804 - reader => T_1807 - reader => T_1810 - reader => T_1813 - reader => T_1816 - reader => T_1819 - reader => T_1822 - reader => T_1825 - reader => T_1828 - reader => T_1831 - reader => T_1834 - reader => T_1837 - reader => T_1840 - reader => T_1843 - reader => T_1846 - reader => T_1849 - reader => T_1852 - reader => T_1855 - reader => T_1858 - reader => T_1861 - reader => T_1864 - reader => T_1867 - reader => T_1870 - reader => T_1873 - reader => T_1876 - reader => T_1879 - reader => T_1882 - reader => T_2360 - reader => T_2363 - reader => T_2366 - reader => T_2369 - reader => T_2372 - reader => T_2375 - reader => T_2378 - reader => T_2381 - reader => T_2384 - reader => T_2387 - reader => T_2390 - reader => T_2393 - reader => T_2396 - reader => T_2399 - reader => T_2402 - reader => T_2405 - reader => T_2408 - reader => T_2411 - reader => T_2414 - reader => T_2417 - reader => T_2420 - reader => T_2423 - reader => T_2426 - reader => T_2429 - reader => T_2432 - reader => T_2435 - reader => T_2438 - reader => T_2441 - reader => T_2444 - reader => T_2447 - reader => T_2450 - reader => T_2453 - reader => T_2456 - reader => T_2459 - reader => T_2462 - reader => T_2465 - reader => T_2468 - reader => T_2471 - reader => T_2474 - reader => T_2477 - reader => T_2480 - reader => T_2483 - reader => T_2486 - reader => T_2489 - reader => T_2492 - reader => T_2495 - reader => T_2498 - reader => T_2501 - reader => T_2504 - reader => T_2507 - reader => T_2510 - reader => T_2513 - reader => T_2516 - reader => T_2519 - reader => T_2522 - reader => T_2525 - reader => T_2528 - reader => T_2531 - reader => T_2534 - reader => T_2537 - reader => T_2540 - reader => T_2543 - writer => T_3470 - idxs.T_1699.addr is invalid - idxs.T_1699.clk <= clk - idxs.T_1702.addr is invalid - idxs.T_1702.clk <= clk - idxs.T_1705.addr is invalid - idxs.T_1705.clk <= clk - idxs.T_1708.addr is invalid - idxs.T_1708.clk <= clk - idxs.T_1711.addr is invalid - idxs.T_1711.clk <= clk - idxs.T_1714.addr is invalid - idxs.T_1714.clk <= clk - idxs.T_1717.addr is invalid - idxs.T_1717.clk <= clk - idxs.T_1720.addr is invalid - idxs.T_1720.clk <= clk - idxs.T_1723.addr is invalid - idxs.T_1723.clk <= clk - idxs.T_1726.addr is invalid - idxs.T_1726.clk <= clk - idxs.T_1729.addr is invalid - idxs.T_1729.clk <= clk - idxs.T_1732.addr is invalid - idxs.T_1732.clk <= clk - idxs.T_1735.addr is invalid - idxs.T_1735.clk <= clk - idxs.T_1738.addr is invalid - idxs.T_1738.clk <= clk - idxs.T_1741.addr is invalid - idxs.T_1741.clk <= clk - idxs.T_1744.addr is invalid - idxs.T_1744.clk <= clk - idxs.T_1747.addr is invalid - idxs.T_1747.clk <= clk - idxs.T_1750.addr is invalid - idxs.T_1750.clk <= clk - idxs.T_1753.addr is invalid - idxs.T_1753.clk <= clk - idxs.T_1756.addr is invalid - idxs.T_1756.clk <= clk - idxs.T_1759.addr is invalid - idxs.T_1759.clk <= clk - idxs.T_1762.addr is invalid - idxs.T_1762.clk <= clk - idxs.T_1765.addr is invalid - idxs.T_1765.clk <= clk - idxs.T_1768.addr is invalid - idxs.T_1768.clk <= clk - idxs.T_1771.addr is invalid - idxs.T_1771.clk <= clk - idxs.T_1774.addr is invalid - idxs.T_1774.clk <= clk - idxs.T_1777.addr is invalid - idxs.T_1777.clk <= clk - idxs.T_1780.addr is invalid - idxs.T_1780.clk <= clk - idxs.T_1783.addr is invalid - idxs.T_1783.clk <= clk - idxs.T_1786.addr is invalid - idxs.T_1786.clk <= clk - idxs.T_1789.addr is invalid - idxs.T_1789.clk <= clk - idxs.T_1792.addr is invalid - idxs.T_1792.clk <= clk - idxs.T_1795.addr is invalid - idxs.T_1795.clk <= clk - idxs.T_1798.addr is invalid - idxs.T_1798.clk <= clk - idxs.T_1801.addr is invalid - idxs.T_1801.clk <= clk - idxs.T_1804.addr is invalid - idxs.T_1804.clk <= clk - idxs.T_1807.addr is invalid - idxs.T_1807.clk <= clk - idxs.T_1810.addr is invalid - idxs.T_1810.clk <= clk - idxs.T_1813.addr is invalid - idxs.T_1813.clk <= clk - idxs.T_1816.addr is invalid - idxs.T_1816.clk <= clk - idxs.T_1819.addr is invalid - idxs.T_1819.clk <= clk - idxs.T_1822.addr is invalid - idxs.T_1822.clk <= clk - idxs.T_1825.addr is invalid - idxs.T_1825.clk <= clk - idxs.T_1828.addr is invalid - idxs.T_1828.clk <= clk - idxs.T_1831.addr is invalid - idxs.T_1831.clk <= clk - idxs.T_1834.addr is invalid - idxs.T_1834.clk <= clk - idxs.T_1837.addr is invalid - idxs.T_1837.clk <= clk - idxs.T_1840.addr is invalid - idxs.T_1840.clk <= clk - idxs.T_1843.addr is invalid - idxs.T_1843.clk <= clk - idxs.T_1846.addr is invalid - idxs.T_1846.clk <= clk - idxs.T_1849.addr is invalid - idxs.T_1849.clk <= clk - idxs.T_1852.addr is invalid - idxs.T_1852.clk <= clk - idxs.T_1855.addr is invalid - idxs.T_1855.clk <= clk - idxs.T_1858.addr is invalid - idxs.T_1858.clk <= clk - idxs.T_1861.addr is invalid - idxs.T_1861.clk <= clk - idxs.T_1864.addr is invalid - idxs.T_1864.clk <= clk - idxs.T_1867.addr is invalid - idxs.T_1867.clk <= clk - idxs.T_1870.addr is invalid - idxs.T_1870.clk <= clk - idxs.T_1873.addr is invalid - idxs.T_1873.clk <= clk - idxs.T_1876.addr is invalid - idxs.T_1876.clk <= clk - idxs.T_1879.addr is invalid - idxs.T_1879.clk <= clk - idxs.T_1882.addr is invalid - idxs.T_1882.clk <= clk - idxs.T_2360.addr is invalid - idxs.T_2360.clk <= clk - idxs.T_2363.addr is invalid - idxs.T_2363.clk <= clk - idxs.T_2366.addr is invalid - idxs.T_2366.clk <= clk - idxs.T_2369.addr is invalid - idxs.T_2369.clk <= clk - idxs.T_2372.addr is invalid - idxs.T_2372.clk <= clk - idxs.T_2375.addr is invalid - idxs.T_2375.clk <= clk - idxs.T_2378.addr is invalid - idxs.T_2378.clk <= clk - idxs.T_2381.addr is invalid - idxs.T_2381.clk <= clk - idxs.T_2384.addr is invalid - idxs.T_2384.clk <= clk - idxs.T_2387.addr is invalid - idxs.T_2387.clk <= clk - idxs.T_2390.addr is invalid - idxs.T_2390.clk <= clk - idxs.T_2393.addr is invalid - idxs.T_2393.clk <= clk - idxs.T_2396.addr is invalid - idxs.T_2396.clk <= clk - idxs.T_2399.addr is invalid - idxs.T_2399.clk <= clk - idxs.T_2402.addr is invalid - idxs.T_2402.clk <= clk - idxs.T_2405.addr is invalid - idxs.T_2405.clk <= clk - idxs.T_2408.addr is invalid - idxs.T_2408.clk <= clk - idxs.T_2411.addr is invalid - idxs.T_2411.clk <= clk - idxs.T_2414.addr is invalid - idxs.T_2414.clk <= clk - idxs.T_2417.addr is invalid - idxs.T_2417.clk <= clk - idxs.T_2420.addr is invalid - idxs.T_2420.clk <= clk - idxs.T_2423.addr is invalid - idxs.T_2423.clk <= clk - idxs.T_2426.addr is invalid - idxs.T_2426.clk <= clk - idxs.T_2429.addr is invalid - idxs.T_2429.clk <= clk - idxs.T_2432.addr is invalid - idxs.T_2432.clk <= clk - idxs.T_2435.addr is invalid - idxs.T_2435.clk <= clk - idxs.T_2438.addr is invalid - idxs.T_2438.clk <= clk - idxs.T_2441.addr is invalid - idxs.T_2441.clk <= clk - idxs.T_2444.addr is invalid - idxs.T_2444.clk <= clk - idxs.T_2447.addr is invalid - idxs.T_2447.clk <= clk - idxs.T_2450.addr is invalid - idxs.T_2450.clk <= clk - idxs.T_2453.addr is invalid - idxs.T_2453.clk <= clk - idxs.T_2456.addr is invalid - idxs.T_2456.clk <= clk - idxs.T_2459.addr is invalid - idxs.T_2459.clk <= clk - idxs.T_2462.addr is invalid - idxs.T_2462.clk <= clk - idxs.T_2465.addr is invalid - idxs.T_2465.clk <= clk - idxs.T_2468.addr is invalid - idxs.T_2468.clk <= clk - idxs.T_2471.addr is invalid - idxs.T_2471.clk <= clk - idxs.T_2474.addr is invalid - idxs.T_2474.clk <= clk - idxs.T_2477.addr is invalid - idxs.T_2477.clk <= clk - idxs.T_2480.addr is invalid - idxs.T_2480.clk <= clk - idxs.T_2483.addr is invalid - idxs.T_2483.clk <= clk - idxs.T_2486.addr is invalid - idxs.T_2486.clk <= clk - idxs.T_2489.addr is invalid - idxs.T_2489.clk <= clk - idxs.T_2492.addr is invalid - idxs.T_2492.clk <= clk - idxs.T_2495.addr is invalid - idxs.T_2495.clk <= clk - idxs.T_2498.addr is invalid - idxs.T_2498.clk <= clk - idxs.T_2501.addr is invalid - idxs.T_2501.clk <= clk - idxs.T_2504.addr is invalid - idxs.T_2504.clk <= clk - idxs.T_2507.addr is invalid - idxs.T_2507.clk <= clk - idxs.T_2510.addr is invalid - idxs.T_2510.clk <= clk - idxs.T_2513.addr is invalid - idxs.T_2513.clk <= clk - idxs.T_2516.addr is invalid - idxs.T_2516.clk <= clk - idxs.T_2519.addr is invalid - idxs.T_2519.clk <= clk - idxs.T_2522.addr is invalid - idxs.T_2522.clk <= clk - idxs.T_2525.addr is invalid - idxs.T_2525.clk <= clk - idxs.T_2528.addr is invalid - idxs.T_2528.clk <= clk - idxs.T_2531.addr is invalid - idxs.T_2531.clk <= clk - idxs.T_2534.addr is invalid - idxs.T_2534.clk <= clk - idxs.T_2537.addr is invalid - idxs.T_2537.clk <= clk - idxs.T_2540.addr is invalid - idxs.T_2540.clk <= clk - idxs.T_2543.addr is invalid - idxs.T_2543.clk <= clk - idxs.T_1699.en <= UInt<1>("h0") - idxs.T_1702.en <= UInt<1>("h0") - idxs.T_1705.en <= UInt<1>("h0") - idxs.T_1708.en <= UInt<1>("h0") - idxs.T_1711.en <= UInt<1>("h0") - idxs.T_1714.en <= UInt<1>("h0") - idxs.T_1717.en <= UInt<1>("h0") - idxs.T_1720.en <= UInt<1>("h0") - idxs.T_1723.en <= UInt<1>("h0") - idxs.T_1726.en <= UInt<1>("h0") - idxs.T_1729.en <= UInt<1>("h0") - idxs.T_1732.en <= UInt<1>("h0") - idxs.T_1735.en <= UInt<1>("h0") - idxs.T_1738.en <= UInt<1>("h0") - idxs.T_1741.en <= UInt<1>("h0") - idxs.T_1744.en <= UInt<1>("h0") - idxs.T_1747.en <= UInt<1>("h0") - idxs.T_1750.en <= UInt<1>("h0") - idxs.T_1753.en <= UInt<1>("h0") - idxs.T_1756.en <= UInt<1>("h0") - idxs.T_1759.en <= UInt<1>("h0") - idxs.T_1762.en <= UInt<1>("h0") - idxs.T_1765.en <= UInt<1>("h0") - idxs.T_1768.en <= UInt<1>("h0") - idxs.T_1771.en <= UInt<1>("h0") - idxs.T_1774.en <= UInt<1>("h0") - idxs.T_1777.en <= UInt<1>("h0") - idxs.T_1780.en <= UInt<1>("h0") - idxs.T_1783.en <= UInt<1>("h0") - idxs.T_1786.en <= UInt<1>("h0") - idxs.T_1789.en <= UInt<1>("h0") - idxs.T_1792.en <= UInt<1>("h0") - idxs.T_1795.en <= UInt<1>("h0") - idxs.T_1798.en <= UInt<1>("h0") - idxs.T_1801.en <= UInt<1>("h0") - idxs.T_1804.en <= UInt<1>("h0") - idxs.T_1807.en <= UInt<1>("h0") - idxs.T_1810.en <= UInt<1>("h0") - idxs.T_1813.en <= UInt<1>("h0") - idxs.T_1816.en <= UInt<1>("h0") - idxs.T_1819.en <= UInt<1>("h0") - idxs.T_1822.en <= UInt<1>("h0") - idxs.T_1825.en <= UInt<1>("h0") - idxs.T_1828.en <= UInt<1>("h0") - idxs.T_1831.en <= UInt<1>("h0") - idxs.T_1834.en <= UInt<1>("h0") - idxs.T_1837.en <= UInt<1>("h0") - idxs.T_1840.en <= UInt<1>("h0") - idxs.T_1843.en <= UInt<1>("h0") - idxs.T_1846.en <= UInt<1>("h0") - idxs.T_1849.en <= UInt<1>("h0") - idxs.T_1852.en <= UInt<1>("h0") - idxs.T_1855.en <= UInt<1>("h0") - idxs.T_1858.en <= UInt<1>("h0") - idxs.T_1861.en <= UInt<1>("h0") - idxs.T_1864.en <= UInt<1>("h0") - idxs.T_1867.en <= UInt<1>("h0") - idxs.T_1870.en <= UInt<1>("h0") - idxs.T_1873.en <= UInt<1>("h0") - idxs.T_1876.en <= UInt<1>("h0") - idxs.T_1879.en <= UInt<1>("h0") - idxs.T_1882.en <= UInt<1>("h0") - idxs.T_2360.en <= UInt<1>("h0") - idxs.T_2363.en <= UInt<1>("h0") - idxs.T_2366.en <= UInt<1>("h0") - idxs.T_2369.en <= UInt<1>("h0") - idxs.T_2372.en <= UInt<1>("h0") - idxs.T_2375.en <= UInt<1>("h0") - idxs.T_2378.en <= UInt<1>("h0") - idxs.T_2381.en <= UInt<1>("h0") - idxs.T_2384.en <= UInt<1>("h0") - idxs.T_2387.en <= UInt<1>("h0") - idxs.T_2390.en <= UInt<1>("h0") - idxs.T_2393.en <= UInt<1>("h0") - idxs.T_2396.en <= UInt<1>("h0") - idxs.T_2399.en <= UInt<1>("h0") - idxs.T_2402.en <= UInt<1>("h0") - idxs.T_2405.en <= UInt<1>("h0") - idxs.T_2408.en <= UInt<1>("h0") - idxs.T_2411.en <= UInt<1>("h0") - idxs.T_2414.en <= UInt<1>("h0") - idxs.T_2417.en <= UInt<1>("h0") - idxs.T_2420.en <= UInt<1>("h0") - idxs.T_2423.en <= UInt<1>("h0") - idxs.T_2426.en <= UInt<1>("h0") - idxs.T_2429.en <= UInt<1>("h0") - idxs.T_2432.en <= UInt<1>("h0") - idxs.T_2435.en <= UInt<1>("h0") - idxs.T_2438.en <= UInt<1>("h0") - idxs.T_2441.en <= UInt<1>("h0") - idxs.T_2444.en <= UInt<1>("h0") - idxs.T_2447.en <= UInt<1>("h0") - idxs.T_2450.en <= UInt<1>("h0") - idxs.T_2453.en <= UInt<1>("h0") - idxs.T_2456.en <= UInt<1>("h0") - idxs.T_2459.en <= UInt<1>("h0") - idxs.T_2462.en <= UInt<1>("h0") - idxs.T_2465.en <= UInt<1>("h0") - idxs.T_2468.en <= UInt<1>("h0") - idxs.T_2471.en <= UInt<1>("h0") - idxs.T_2474.en <= UInt<1>("h0") - idxs.T_2477.en <= UInt<1>("h0") - idxs.T_2480.en <= UInt<1>("h0") - idxs.T_2483.en <= UInt<1>("h0") - idxs.T_2486.en <= UInt<1>("h0") - idxs.T_2489.en <= UInt<1>("h0") - idxs.T_2492.en <= UInt<1>("h0") - idxs.T_2495.en <= UInt<1>("h0") - idxs.T_2498.en <= UInt<1>("h0") - idxs.T_2501.en <= UInt<1>("h0") - idxs.T_2504.en <= UInt<1>("h0") - idxs.T_2507.en <= UInt<1>("h0") - idxs.T_2510.en <= UInt<1>("h0") - idxs.T_2513.en <= UInt<1>("h0") - idxs.T_2516.en <= UInt<1>("h0") - idxs.T_2519.en <= UInt<1>("h0") - idxs.T_2522.en <= UInt<1>("h0") - idxs.T_2525.en <= UInt<1>("h0") - idxs.T_2528.en <= UInt<1>("h0") - idxs.T_2531.en <= UInt<1>("h0") - idxs.T_2534.en <= UInt<1>("h0") - idxs.T_2537.en <= UInt<1>("h0") - idxs.T_2540.en <= UInt<1>("h0") - idxs.T_2543.en <= UInt<1>("h0") - idxs.T_3470.addr is invalid - idxs.T_3470.clk <= clk - idxs.T_3470.en <= UInt<1>("h0") - idxs.T_3470.data is invalid - idxs.T_3470.mask <= UInt<1>("h0") - mem idxPages : - data-type => UInt<3> - depth => 62 - write-latency => 1 - read-latency => 0 - reader => T_590 - reader => T_595 - reader => T_600 - reader => T_605 - reader => T_610 - reader => T_615 - reader => T_620 - reader => T_625 - reader => T_630 - reader => T_635 - reader => T_640 - reader => T_645 - reader => T_650 - reader => T_655 - reader => T_660 - reader => T_665 - reader => T_670 - reader => T_675 - reader => T_680 - reader => T_685 - reader => T_690 - reader => T_695 - reader => T_700 - reader => T_705 - reader => T_710 - reader => T_715 - reader => T_720 - reader => T_725 - reader => T_730 - reader => T_735 - reader => T_740 - reader => T_745 - reader => T_750 - reader => T_755 - reader => T_760 - reader => T_765 - reader => T_770 - reader => T_775 - reader => T_780 - reader => T_785 - reader => T_790 - reader => T_795 - reader => T_800 - reader => T_805 - reader => T_810 - reader => T_815 - reader => T_820 - reader => T_825 - reader => T_830 - reader => T_835 - reader => T_840 - reader => T_845 - reader => T_850 - reader => T_855 - reader => T_860 - reader => T_865 - reader => T_870 - reader => T_875 - reader => T_880 - reader => T_885 - reader => T_890 - reader => T_895 - writer => T_3472 - idxPages.T_590.addr is invalid - idxPages.T_590.clk <= clk - idxPages.T_595.addr is invalid - idxPages.T_595.clk <= clk - idxPages.T_600.addr is invalid - idxPages.T_600.clk <= clk - idxPages.T_605.addr is invalid - idxPages.T_605.clk <= clk - idxPages.T_610.addr is invalid - idxPages.T_610.clk <= clk - idxPages.T_615.addr is invalid - idxPages.T_615.clk <= clk - idxPages.T_620.addr is invalid - idxPages.T_620.clk <= clk - idxPages.T_625.addr is invalid - idxPages.T_625.clk <= clk - idxPages.T_630.addr is invalid - idxPages.T_630.clk <= clk - idxPages.T_635.addr is invalid - idxPages.T_635.clk <= clk - idxPages.T_640.addr is invalid - idxPages.T_640.clk <= clk - idxPages.T_645.addr is invalid - idxPages.T_645.clk <= clk - idxPages.T_650.addr is invalid - idxPages.T_650.clk <= clk - idxPages.T_655.addr is invalid - idxPages.T_655.clk <= clk - idxPages.T_660.addr is invalid - idxPages.T_660.clk <= clk - idxPages.T_665.addr is invalid - idxPages.T_665.clk <= clk - idxPages.T_670.addr is invalid - idxPages.T_670.clk <= clk - idxPages.T_675.addr is invalid - idxPages.T_675.clk <= clk - idxPages.T_680.addr is invalid - idxPages.T_680.clk <= clk - idxPages.T_685.addr is invalid - idxPages.T_685.clk <= clk - idxPages.T_690.addr is invalid - idxPages.T_690.clk <= clk - idxPages.T_695.addr is invalid - idxPages.T_695.clk <= clk - idxPages.T_700.addr is invalid - idxPages.T_700.clk <= clk - idxPages.T_705.addr is invalid - idxPages.T_705.clk <= clk - idxPages.T_710.addr is invalid - idxPages.T_710.clk <= clk - idxPages.T_715.addr is invalid - idxPages.T_715.clk <= clk - idxPages.T_720.addr is invalid - idxPages.T_720.clk <= clk - idxPages.T_725.addr is invalid - idxPages.T_725.clk <= clk - idxPages.T_730.addr is invalid - idxPages.T_730.clk <= clk - idxPages.T_735.addr is invalid - idxPages.T_735.clk <= clk - idxPages.T_740.addr is invalid - idxPages.T_740.clk <= clk - idxPages.T_745.addr is invalid - idxPages.T_745.clk <= clk - idxPages.T_750.addr is invalid - idxPages.T_750.clk <= clk - idxPages.T_755.addr is invalid - idxPages.T_755.clk <= clk - idxPages.T_760.addr is invalid - idxPages.T_760.clk <= clk - idxPages.T_765.addr is invalid - idxPages.T_765.clk <= clk - idxPages.T_770.addr is invalid - idxPages.T_770.clk <= clk - idxPages.T_775.addr is invalid - idxPages.T_775.clk <= clk - idxPages.T_780.addr is invalid - idxPages.T_780.clk <= clk - idxPages.T_785.addr is invalid - idxPages.T_785.clk <= clk - idxPages.T_790.addr is invalid - idxPages.T_790.clk <= clk - idxPages.T_795.addr is invalid - idxPages.T_795.clk <= clk - idxPages.T_800.addr is invalid - idxPages.T_800.clk <= clk - idxPages.T_805.addr is invalid - idxPages.T_805.clk <= clk - idxPages.T_810.addr is invalid - idxPages.T_810.clk <= clk - idxPages.T_815.addr is invalid - idxPages.T_815.clk <= clk - idxPages.T_820.addr is invalid - idxPages.T_820.clk <= clk - idxPages.T_825.addr is invalid - idxPages.T_825.clk <= clk - idxPages.T_830.addr is invalid - idxPages.T_830.clk <= clk - idxPages.T_835.addr is invalid - idxPages.T_835.clk <= clk - idxPages.T_840.addr is invalid - idxPages.T_840.clk <= clk - idxPages.T_845.addr is invalid - idxPages.T_845.clk <= clk - idxPages.T_850.addr is invalid - idxPages.T_850.clk <= clk - idxPages.T_855.addr is invalid - idxPages.T_855.clk <= clk - idxPages.T_860.addr is invalid - idxPages.T_860.clk <= clk - idxPages.T_865.addr is invalid - idxPages.T_865.clk <= clk - idxPages.T_870.addr is invalid - idxPages.T_870.clk <= clk - idxPages.T_875.addr is invalid - idxPages.T_875.clk <= clk - idxPages.T_880.addr is invalid - idxPages.T_880.clk <= clk - idxPages.T_885.addr is invalid - idxPages.T_885.clk <= clk - idxPages.T_890.addr is invalid - idxPages.T_890.clk <= clk - idxPages.T_895.addr is invalid - idxPages.T_895.clk <= clk - idxPages.T_590.en <= UInt<1>("h0") - idxPages.T_595.en <= UInt<1>("h0") - idxPages.T_600.en <= UInt<1>("h0") - idxPages.T_605.en <= UInt<1>("h0") - idxPages.T_610.en <= UInt<1>("h0") - idxPages.T_615.en <= UInt<1>("h0") - idxPages.T_620.en <= UInt<1>("h0") - idxPages.T_625.en <= UInt<1>("h0") - idxPages.T_630.en <= UInt<1>("h0") - idxPages.T_635.en <= UInt<1>("h0") - idxPages.T_640.en <= UInt<1>("h0") - idxPages.T_645.en <= UInt<1>("h0") - idxPages.T_650.en <= UInt<1>("h0") - idxPages.T_655.en <= UInt<1>("h0") - idxPages.T_660.en <= UInt<1>("h0") - idxPages.T_665.en <= UInt<1>("h0") - idxPages.T_670.en <= UInt<1>("h0") - idxPages.T_675.en <= UInt<1>("h0") - idxPages.T_680.en <= UInt<1>("h0") - idxPages.T_685.en <= UInt<1>("h0") - idxPages.T_690.en <= UInt<1>("h0") - idxPages.T_695.en <= UInt<1>("h0") - idxPages.T_700.en <= UInt<1>("h0") - idxPages.T_705.en <= UInt<1>("h0") - idxPages.T_710.en <= UInt<1>("h0") - idxPages.T_715.en <= UInt<1>("h0") - idxPages.T_720.en <= UInt<1>("h0") - idxPages.T_725.en <= UInt<1>("h0") - idxPages.T_730.en <= UInt<1>("h0") - idxPages.T_735.en <= UInt<1>("h0") - idxPages.T_740.en <= UInt<1>("h0") - idxPages.T_745.en <= UInt<1>("h0") - idxPages.T_750.en <= UInt<1>("h0") - idxPages.T_755.en <= UInt<1>("h0") - idxPages.T_760.en <= UInt<1>("h0") - idxPages.T_765.en <= UInt<1>("h0") - idxPages.T_770.en <= UInt<1>("h0") - idxPages.T_775.en <= UInt<1>("h0") - idxPages.T_780.en <= UInt<1>("h0") - idxPages.T_785.en <= UInt<1>("h0") - idxPages.T_790.en <= UInt<1>("h0") - idxPages.T_795.en <= UInt<1>("h0") - idxPages.T_800.en <= UInt<1>("h0") - idxPages.T_805.en <= UInt<1>("h0") - idxPages.T_810.en <= UInt<1>("h0") - idxPages.T_815.en <= UInt<1>("h0") - idxPages.T_820.en <= UInt<1>("h0") - idxPages.T_825.en <= UInt<1>("h0") - idxPages.T_830.en <= UInt<1>("h0") - idxPages.T_835.en <= UInt<1>("h0") - idxPages.T_840.en <= UInt<1>("h0") - idxPages.T_845.en <= UInt<1>("h0") - idxPages.T_850.en <= UInt<1>("h0") - idxPages.T_855.en <= UInt<1>("h0") - idxPages.T_860.en <= UInt<1>("h0") - idxPages.T_865.en <= UInt<1>("h0") - idxPages.T_870.en <= UInt<1>("h0") - idxPages.T_875.en <= UInt<1>("h0") - idxPages.T_880.en <= UInt<1>("h0") - idxPages.T_885.en <= UInt<1>("h0") - idxPages.T_890.en <= UInt<1>("h0") - idxPages.T_895.en <= UInt<1>("h0") - idxPages.T_3472.addr is invalid - idxPages.T_3472.clk <= clk - idxPages.T_3472.en <= UInt<1>("h0") - idxPages.T_3472.data is invalid - idxPages.T_3472.mask <= UInt<1>("h0") - mem tgts : - data-type => UInt<12> - depth => 62 - write-latency => 1 - read-latency => 0 - reader => T_3870 - reader => T_3872 - reader => T_3874 - reader => T_3876 - reader => T_3878 - reader => T_3880 - reader => T_3882 - reader => T_3884 - reader => T_3886 - reader => T_3888 - reader => T_3890 - reader => T_3892 - reader => T_3894 - reader => T_3896 - reader => T_3898 - reader => T_3900 - reader => T_3902 - reader => T_3904 - reader => T_3906 - reader => T_3908 - reader => T_3910 - reader => T_3912 - reader => T_3914 - reader => T_3916 - reader => T_3918 - reader => T_3920 - reader => T_3922 - reader => T_3924 - reader => T_3926 - reader => T_3928 - reader => T_3930 - reader => T_3932 - reader => T_3934 - reader => T_3936 - reader => T_3938 - reader => T_3940 - reader => T_3942 - reader => T_3944 - reader => T_3946 - reader => T_3948 - reader => T_3950 - reader => T_3952 - reader => T_3954 - reader => T_3956 - reader => T_3958 - reader => T_3960 - reader => T_3962 - reader => T_3964 - reader => T_3966 - reader => T_3968 - reader => T_3970 - reader => T_3972 - reader => T_3974 - reader => T_3976 - reader => T_3978 - reader => T_3980 - reader => T_3982 - reader => T_3984 - reader => T_3986 - reader => T_3988 - reader => T_3990 - reader => T_3992 - writer => T_3471 - tgts.T_3870.addr is invalid - tgts.T_3870.clk <= clk - tgts.T_3872.addr is invalid - tgts.T_3872.clk <= clk - tgts.T_3874.addr is invalid - tgts.T_3874.clk <= clk - tgts.T_3876.addr is invalid - tgts.T_3876.clk <= clk - tgts.T_3878.addr is invalid - tgts.T_3878.clk <= clk - tgts.T_3880.addr is invalid - tgts.T_3880.clk <= clk - tgts.T_3882.addr is invalid - tgts.T_3882.clk <= clk - tgts.T_3884.addr is invalid - tgts.T_3884.clk <= clk - tgts.T_3886.addr is invalid - tgts.T_3886.clk <= clk - tgts.T_3888.addr is invalid - tgts.T_3888.clk <= clk - tgts.T_3890.addr is invalid - tgts.T_3890.clk <= clk - tgts.T_3892.addr is invalid - tgts.T_3892.clk <= clk - tgts.T_3894.addr is invalid - tgts.T_3894.clk <= clk - tgts.T_3896.addr is invalid - tgts.T_3896.clk <= clk - tgts.T_3898.addr is invalid - tgts.T_3898.clk <= clk - tgts.T_3900.addr is invalid - tgts.T_3900.clk <= clk - tgts.T_3902.addr is invalid - tgts.T_3902.clk <= clk - tgts.T_3904.addr is invalid - tgts.T_3904.clk <= clk - tgts.T_3906.addr is invalid - tgts.T_3906.clk <= clk - tgts.T_3908.addr is invalid - tgts.T_3908.clk <= clk - tgts.T_3910.addr is invalid - tgts.T_3910.clk <= clk - tgts.T_3912.addr is invalid - tgts.T_3912.clk <= clk - tgts.T_3914.addr is invalid - tgts.T_3914.clk <= clk - tgts.T_3916.addr is invalid - tgts.T_3916.clk <= clk - tgts.T_3918.addr is invalid - tgts.T_3918.clk <= clk - tgts.T_3920.addr is invalid - tgts.T_3920.clk <= clk - tgts.T_3922.addr is invalid - tgts.T_3922.clk <= clk - tgts.T_3924.addr is invalid - tgts.T_3924.clk <= clk - tgts.T_3926.addr is invalid - tgts.T_3926.clk <= clk - tgts.T_3928.addr is invalid - tgts.T_3928.clk <= clk - tgts.T_3930.addr is invalid - tgts.T_3930.clk <= clk - tgts.T_3932.addr is invalid - tgts.T_3932.clk <= clk - tgts.T_3934.addr is invalid - tgts.T_3934.clk <= clk - tgts.T_3936.addr is invalid - tgts.T_3936.clk <= clk - tgts.T_3938.addr is invalid - tgts.T_3938.clk <= clk - tgts.T_3940.addr is invalid - tgts.T_3940.clk <= clk - tgts.T_3942.addr is invalid - tgts.T_3942.clk <= clk - tgts.T_3944.addr is invalid - tgts.T_3944.clk <= clk - tgts.T_3946.addr is invalid - tgts.T_3946.clk <= clk - tgts.T_3948.addr is invalid - tgts.T_3948.clk <= clk - tgts.T_3950.addr is invalid - tgts.T_3950.clk <= clk - tgts.T_3952.addr is invalid - tgts.T_3952.clk <= clk - tgts.T_3954.addr is invalid - tgts.T_3954.clk <= clk - tgts.T_3956.addr is invalid - tgts.T_3956.clk <= clk - tgts.T_3958.addr is invalid - tgts.T_3958.clk <= clk - tgts.T_3960.addr is invalid - tgts.T_3960.clk <= clk - tgts.T_3962.addr is invalid - tgts.T_3962.clk <= clk - tgts.T_3964.addr is invalid - tgts.T_3964.clk <= clk - tgts.T_3966.addr is invalid - tgts.T_3966.clk <= clk - tgts.T_3968.addr is invalid - tgts.T_3968.clk <= clk - tgts.T_3970.addr is invalid - tgts.T_3970.clk <= clk - tgts.T_3972.addr is invalid - tgts.T_3972.clk <= clk - tgts.T_3974.addr is invalid - tgts.T_3974.clk <= clk - tgts.T_3976.addr is invalid - tgts.T_3976.clk <= clk - tgts.T_3978.addr is invalid - tgts.T_3978.clk <= clk - tgts.T_3980.addr is invalid - tgts.T_3980.clk <= clk - tgts.T_3982.addr is invalid - tgts.T_3982.clk <= clk - tgts.T_3984.addr is invalid - tgts.T_3984.clk <= clk - tgts.T_3986.addr is invalid - tgts.T_3986.clk <= clk - tgts.T_3988.addr is invalid - tgts.T_3988.clk <= clk - tgts.T_3990.addr is invalid - tgts.T_3990.clk <= clk - tgts.T_3992.addr is invalid - tgts.T_3992.clk <= clk - tgts.T_3870.en <= UInt<1>("h0") - tgts.T_3872.en <= UInt<1>("h0") - tgts.T_3874.en <= UInt<1>("h0") - tgts.T_3876.en <= UInt<1>("h0") - tgts.T_3878.en <= UInt<1>("h0") - tgts.T_3880.en <= UInt<1>("h0") - tgts.T_3882.en <= UInt<1>("h0") - tgts.T_3884.en <= UInt<1>("h0") - tgts.T_3886.en <= UInt<1>("h0") - tgts.T_3888.en <= UInt<1>("h0") - tgts.T_3890.en <= UInt<1>("h0") - tgts.T_3892.en <= UInt<1>("h0") - tgts.T_3894.en <= UInt<1>("h0") - tgts.T_3896.en <= UInt<1>("h0") - tgts.T_3898.en <= UInt<1>("h0") - tgts.T_3900.en <= UInt<1>("h0") - tgts.T_3902.en <= UInt<1>("h0") - tgts.T_3904.en <= UInt<1>("h0") - tgts.T_3906.en <= UInt<1>("h0") - tgts.T_3908.en <= UInt<1>("h0") - tgts.T_3910.en <= UInt<1>("h0") - tgts.T_3912.en <= UInt<1>("h0") - tgts.T_3914.en <= UInt<1>("h0") - tgts.T_3916.en <= UInt<1>("h0") - tgts.T_3918.en <= UInt<1>("h0") - tgts.T_3920.en <= UInt<1>("h0") - tgts.T_3922.en <= UInt<1>("h0") - tgts.T_3924.en <= UInt<1>("h0") - tgts.T_3926.en <= UInt<1>("h0") - tgts.T_3928.en <= UInt<1>("h0") - tgts.T_3930.en <= UInt<1>("h0") - tgts.T_3932.en <= UInt<1>("h0") - tgts.T_3934.en <= UInt<1>("h0") - tgts.T_3936.en <= UInt<1>("h0") - tgts.T_3938.en <= UInt<1>("h0") - tgts.T_3940.en <= UInt<1>("h0") - tgts.T_3942.en <= UInt<1>("h0") - tgts.T_3944.en <= UInt<1>("h0") - tgts.T_3946.en <= UInt<1>("h0") - tgts.T_3948.en <= UInt<1>("h0") - tgts.T_3950.en <= UInt<1>("h0") - tgts.T_3952.en <= UInt<1>("h0") - tgts.T_3954.en <= UInt<1>("h0") - tgts.T_3956.en <= UInt<1>("h0") - tgts.T_3958.en <= UInt<1>("h0") - tgts.T_3960.en <= UInt<1>("h0") - tgts.T_3962.en <= UInt<1>("h0") - tgts.T_3964.en <= UInt<1>("h0") - tgts.T_3966.en <= UInt<1>("h0") - tgts.T_3968.en <= UInt<1>("h0") - tgts.T_3970.en <= UInt<1>("h0") - tgts.T_3972.en <= UInt<1>("h0") - tgts.T_3974.en <= UInt<1>("h0") - tgts.T_3976.en <= UInt<1>("h0") - tgts.T_3978.en <= UInt<1>("h0") - tgts.T_3980.en <= UInt<1>("h0") - tgts.T_3982.en <= UInt<1>("h0") - tgts.T_3984.en <= UInt<1>("h0") - tgts.T_3986.en <= UInt<1>("h0") - tgts.T_3988.en <= UInt<1>("h0") - tgts.T_3990.en <= UInt<1>("h0") - tgts.T_3992.en <= UInt<1>("h0") - tgts.T_3471.addr is invalid - tgts.T_3471.clk <= clk - tgts.T_3471.en <= UInt<1>("h0") - tgts.T_3471.data is invalid - tgts.T_3471.mask <= UInt<1>("h0") - mem tgtPages : - data-type => UInt<3> - depth => 62 - write-latency => 1 - read-latency => 0 - reader => T_900 - reader => T_905 - reader => T_910 - reader => T_915 - reader => T_920 - reader => T_925 - reader => T_930 - reader => T_935 - reader => T_940 - reader => T_945 - reader => T_950 - reader => T_955 - reader => T_960 - reader => T_965 - reader => T_970 - reader => T_975 - reader => T_980 - reader => T_985 - reader => T_990 - reader => T_995 - reader => T_1000 - reader => T_1005 - reader => T_1010 - reader => T_1015 - reader => T_1020 - reader => T_1025 - reader => T_1030 - reader => T_1035 - reader => T_1040 - reader => T_1045 - reader => T_1050 - reader => T_1055 - reader => T_1060 - reader => T_1065 - reader => T_1070 - reader => T_1075 - reader => T_1080 - reader => T_1085 - reader => T_1090 - reader => T_1095 - reader => T_1100 - reader => T_1105 - reader => T_1110 - reader => T_1115 - reader => T_1120 - reader => T_1125 - reader => T_1130 - reader => T_1135 - reader => T_1140 - reader => T_1145 - reader => T_1150 - reader => T_1155 - reader => T_1160 - reader => T_1165 - reader => T_1170 - reader => T_1175 - reader => T_1180 - reader => T_1185 - reader => T_1190 - reader => T_1195 - reader => T_1200 - reader => T_1205 - writer => T_3473 - tgtPages.T_900.addr is invalid - tgtPages.T_900.clk <= clk - tgtPages.T_905.addr is invalid - tgtPages.T_905.clk <= clk - tgtPages.T_910.addr is invalid - tgtPages.T_910.clk <= clk - tgtPages.T_915.addr is invalid - tgtPages.T_915.clk <= clk - tgtPages.T_920.addr is invalid - tgtPages.T_920.clk <= clk - tgtPages.T_925.addr is invalid - tgtPages.T_925.clk <= clk - tgtPages.T_930.addr is invalid - tgtPages.T_930.clk <= clk - tgtPages.T_935.addr is invalid - tgtPages.T_935.clk <= clk - tgtPages.T_940.addr is invalid - tgtPages.T_940.clk <= clk - tgtPages.T_945.addr is invalid - tgtPages.T_945.clk <= clk - tgtPages.T_950.addr is invalid - tgtPages.T_950.clk <= clk - tgtPages.T_955.addr is invalid - tgtPages.T_955.clk <= clk - tgtPages.T_960.addr is invalid - tgtPages.T_960.clk <= clk - tgtPages.T_965.addr is invalid - tgtPages.T_965.clk <= clk - tgtPages.T_970.addr is invalid - tgtPages.T_970.clk <= clk - tgtPages.T_975.addr is invalid - tgtPages.T_975.clk <= clk - tgtPages.T_980.addr is invalid - tgtPages.T_980.clk <= clk - tgtPages.T_985.addr is invalid - tgtPages.T_985.clk <= clk - tgtPages.T_990.addr is invalid - tgtPages.T_990.clk <= clk - tgtPages.T_995.addr is invalid - tgtPages.T_995.clk <= clk - tgtPages.T_1000.addr is invalid - tgtPages.T_1000.clk <= clk - tgtPages.T_1005.addr is invalid - tgtPages.T_1005.clk <= clk - tgtPages.T_1010.addr is invalid - tgtPages.T_1010.clk <= clk - tgtPages.T_1015.addr is invalid - tgtPages.T_1015.clk <= clk - tgtPages.T_1020.addr is invalid - tgtPages.T_1020.clk <= clk - tgtPages.T_1025.addr is invalid - tgtPages.T_1025.clk <= clk - tgtPages.T_1030.addr is invalid - tgtPages.T_1030.clk <= clk - tgtPages.T_1035.addr is invalid - tgtPages.T_1035.clk <= clk - tgtPages.T_1040.addr is invalid - tgtPages.T_1040.clk <= clk - tgtPages.T_1045.addr is invalid - tgtPages.T_1045.clk <= clk - tgtPages.T_1050.addr is invalid - tgtPages.T_1050.clk <= clk - tgtPages.T_1055.addr is invalid - tgtPages.T_1055.clk <= clk - tgtPages.T_1060.addr is invalid - tgtPages.T_1060.clk <= clk - tgtPages.T_1065.addr is invalid - tgtPages.T_1065.clk <= clk - tgtPages.T_1070.addr is invalid - tgtPages.T_1070.clk <= clk - tgtPages.T_1075.addr is invalid - tgtPages.T_1075.clk <= clk - tgtPages.T_1080.addr is invalid - tgtPages.T_1080.clk <= clk - tgtPages.T_1085.addr is invalid - tgtPages.T_1085.clk <= clk - tgtPages.T_1090.addr is invalid - tgtPages.T_1090.clk <= clk - tgtPages.T_1095.addr is invalid - tgtPages.T_1095.clk <= clk - tgtPages.T_1100.addr is invalid - tgtPages.T_1100.clk <= clk - tgtPages.T_1105.addr is invalid - tgtPages.T_1105.clk <= clk - tgtPages.T_1110.addr is invalid - tgtPages.T_1110.clk <= clk - tgtPages.T_1115.addr is invalid - tgtPages.T_1115.clk <= clk - tgtPages.T_1120.addr is invalid - tgtPages.T_1120.clk <= clk - tgtPages.T_1125.addr is invalid - tgtPages.T_1125.clk <= clk - tgtPages.T_1130.addr is invalid - tgtPages.T_1130.clk <= clk - tgtPages.T_1135.addr is invalid - tgtPages.T_1135.clk <= clk - tgtPages.T_1140.addr is invalid - tgtPages.T_1140.clk <= clk - tgtPages.T_1145.addr is invalid - tgtPages.T_1145.clk <= clk - tgtPages.T_1150.addr is invalid - tgtPages.T_1150.clk <= clk - tgtPages.T_1155.addr is invalid - tgtPages.T_1155.clk <= clk - tgtPages.T_1160.addr is invalid - tgtPages.T_1160.clk <= clk - tgtPages.T_1165.addr is invalid - tgtPages.T_1165.clk <= clk - tgtPages.T_1170.addr is invalid - tgtPages.T_1170.clk <= clk - tgtPages.T_1175.addr is invalid - tgtPages.T_1175.clk <= clk - tgtPages.T_1180.addr is invalid - tgtPages.T_1180.clk <= clk - tgtPages.T_1185.addr is invalid - tgtPages.T_1185.clk <= clk - tgtPages.T_1190.addr is invalid - tgtPages.T_1190.clk <= clk - tgtPages.T_1195.addr is invalid - tgtPages.T_1195.clk <= clk - tgtPages.T_1200.addr is invalid - tgtPages.T_1200.clk <= clk - tgtPages.T_1205.addr is invalid - tgtPages.T_1205.clk <= clk - tgtPages.T_900.en <= UInt<1>("h0") - tgtPages.T_905.en <= UInt<1>("h0") - tgtPages.T_910.en <= UInt<1>("h0") - tgtPages.T_915.en <= UInt<1>("h0") - tgtPages.T_920.en <= UInt<1>("h0") - tgtPages.T_925.en <= UInt<1>("h0") - tgtPages.T_930.en <= UInt<1>("h0") - tgtPages.T_935.en <= UInt<1>("h0") - tgtPages.T_940.en <= UInt<1>("h0") - tgtPages.T_945.en <= UInt<1>("h0") - tgtPages.T_950.en <= UInt<1>("h0") - tgtPages.T_955.en <= UInt<1>("h0") - tgtPages.T_960.en <= UInt<1>("h0") - tgtPages.T_965.en <= UInt<1>("h0") - tgtPages.T_970.en <= UInt<1>("h0") - tgtPages.T_975.en <= UInt<1>("h0") - tgtPages.T_980.en <= UInt<1>("h0") - tgtPages.T_985.en <= UInt<1>("h0") - tgtPages.T_990.en <= UInt<1>("h0") - tgtPages.T_995.en <= UInt<1>("h0") - tgtPages.T_1000.en <= UInt<1>("h0") - tgtPages.T_1005.en <= UInt<1>("h0") - tgtPages.T_1010.en <= UInt<1>("h0") - tgtPages.T_1015.en <= UInt<1>("h0") - tgtPages.T_1020.en <= UInt<1>("h0") - tgtPages.T_1025.en <= UInt<1>("h0") - tgtPages.T_1030.en <= UInt<1>("h0") - tgtPages.T_1035.en <= UInt<1>("h0") - tgtPages.T_1040.en <= UInt<1>("h0") - tgtPages.T_1045.en <= UInt<1>("h0") - tgtPages.T_1050.en <= UInt<1>("h0") - tgtPages.T_1055.en <= UInt<1>("h0") - tgtPages.T_1060.en <= UInt<1>("h0") - tgtPages.T_1065.en <= UInt<1>("h0") - tgtPages.T_1070.en <= UInt<1>("h0") - tgtPages.T_1075.en <= UInt<1>("h0") - tgtPages.T_1080.en <= UInt<1>("h0") - tgtPages.T_1085.en <= UInt<1>("h0") - tgtPages.T_1090.en <= UInt<1>("h0") - tgtPages.T_1095.en <= UInt<1>("h0") - tgtPages.T_1100.en <= UInt<1>("h0") - tgtPages.T_1105.en <= UInt<1>("h0") - tgtPages.T_1110.en <= UInt<1>("h0") - tgtPages.T_1115.en <= UInt<1>("h0") - tgtPages.T_1120.en <= UInt<1>("h0") - tgtPages.T_1125.en <= UInt<1>("h0") - tgtPages.T_1130.en <= UInt<1>("h0") - tgtPages.T_1135.en <= UInt<1>("h0") - tgtPages.T_1140.en <= UInt<1>("h0") - tgtPages.T_1145.en <= UInt<1>("h0") - tgtPages.T_1150.en <= UInt<1>("h0") - tgtPages.T_1155.en <= UInt<1>("h0") - tgtPages.T_1160.en <= UInt<1>("h0") - tgtPages.T_1165.en <= UInt<1>("h0") - tgtPages.T_1170.en <= UInt<1>("h0") - tgtPages.T_1175.en <= UInt<1>("h0") - tgtPages.T_1180.en <= UInt<1>("h0") - tgtPages.T_1185.en <= UInt<1>("h0") - tgtPages.T_1190.en <= UInt<1>("h0") - tgtPages.T_1195.en <= UInt<1>("h0") - tgtPages.T_1200.en <= UInt<1>("h0") - tgtPages.T_1205.en <= UInt<1>("h0") - tgtPages.T_3473.addr is invalid - tgtPages.T_3473.clk <= clk - tgtPages.T_3473.en <= UInt<1>("h0") - tgtPages.T_3473.data is invalid - tgtPages.T_3473.mask <= UInt<1>("h0") - mem pages : - data-type => UInt<27> - depth => 6 - write-latency => 1 - read-latency => 0 - reader => T_1665 - reader => T_1668 - reader => T_1671 - reader => T_1674 - reader => T_1677 - reader => T_1680 - reader => T_2326 - reader => T_2329 - reader => T_2332 - reader => T_2335 - reader => T_2338 - reader => T_2341 - reader => T_3777 - reader => T_3779 - reader => T_3781 - reader => T_3783 - reader => T_3785 - reader => T_3787 - writer => T_3491 - writer => T_3495 - writer => T_3499 - writer => T_3507 - writer => T_3511 - writer => T_3515 - pages.T_1665.addr is invalid - pages.T_1665.clk <= clk - pages.T_1668.addr is invalid - pages.T_1668.clk <= clk - pages.T_1671.addr is invalid - pages.T_1671.clk <= clk - pages.T_1674.addr is invalid - pages.T_1674.clk <= clk - pages.T_1677.addr is invalid - pages.T_1677.clk <= clk - pages.T_1680.addr is invalid - pages.T_1680.clk <= clk - pages.T_2326.addr is invalid - pages.T_2326.clk <= clk - pages.T_2329.addr is invalid - pages.T_2329.clk <= clk - pages.T_2332.addr is invalid - pages.T_2332.clk <= clk - pages.T_2335.addr is invalid - pages.T_2335.clk <= clk - pages.T_2338.addr is invalid - pages.T_2338.clk <= clk - pages.T_2341.addr is invalid - pages.T_2341.clk <= clk - pages.T_3777.addr is invalid - pages.T_3777.clk <= clk - pages.T_3779.addr is invalid - pages.T_3779.clk <= clk - pages.T_3781.addr is invalid - pages.T_3781.clk <= clk - pages.T_3783.addr is invalid - pages.T_3783.clk <= clk - pages.T_3785.addr is invalid - pages.T_3785.clk <= clk - pages.T_3787.addr is invalid - pages.T_3787.clk <= clk - pages.T_1665.en <= UInt<1>("h0") - pages.T_1668.en <= UInt<1>("h0") - pages.T_1671.en <= UInt<1>("h0") - pages.T_1674.en <= UInt<1>("h0") - pages.T_1677.en <= UInt<1>("h0") - pages.T_1680.en <= UInt<1>("h0") - pages.T_2326.en <= UInt<1>("h0") - pages.T_2329.en <= UInt<1>("h0") - pages.T_2332.en <= UInt<1>("h0") - pages.T_2335.en <= UInt<1>("h0") - pages.T_2338.en <= UInt<1>("h0") - pages.T_2341.en <= UInt<1>("h0") - pages.T_3777.en <= UInt<1>("h0") - pages.T_3779.en <= UInt<1>("h0") - pages.T_3781.en <= UInt<1>("h0") - pages.T_3783.en <= UInt<1>("h0") - pages.T_3785.en <= UInt<1>("h0") - pages.T_3787.en <= UInt<1>("h0") - pages.T_3491.addr is invalid - pages.T_3491.clk <= clk - pages.T_3495.addr is invalid - pages.T_3495.clk <= clk - pages.T_3499.addr is invalid - pages.T_3499.clk <= clk - pages.T_3507.addr is invalid - pages.T_3507.clk <= clk - pages.T_3511.addr is invalid - pages.T_3511.clk <= clk - pages.T_3515.addr is invalid - pages.T_3515.clk <= clk - pages.T_3491.en <= UInt<1>("h0") - pages.T_3495.en <= UInt<1>("h0") - pages.T_3499.en <= UInt<1>("h0") - pages.T_3507.en <= UInt<1>("h0") - pages.T_3511.en <= UInt<1>("h0") - pages.T_3515.en <= UInt<1>("h0") - pages.T_3491.data is invalid - pages.T_3491.mask <= UInt<1>("h0") - pages.T_3495.data is invalid - pages.T_3495.mask <= UInt<1>("h0") - pages.T_3499.data is invalid - pages.T_3499.mask <= UInt<1>("h0") - pages.T_3507.data is invalid - pages.T_3507.mask <= UInt<1>("h0") - pages.T_3511.data is invalid - pages.T_3511.mask <= UInt<1>("h0") - pages.T_3515.data is invalid - pages.T_3515.mask <= UInt<1>("h0") - reg pageValid : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - idxPages.T_590.addr <= UInt<1>("h0") - idxPages.T_590.en <= UInt<1>("h1") - node T_592 = dshl(UInt<1>("h1"), idxPages.T_590.data) - node T_593 = bits(T_592, 5, 0) - idxPages.T_595.addr <= UInt<1>("h1") - idxPages.T_595.en <= UInt<1>("h1") - node T_597 = dshl(UInt<1>("h1"), idxPages.T_595.data) - node T_598 = bits(T_597, 5, 0) - idxPages.T_600.addr <= UInt<2>("h2") - idxPages.T_600.en <= UInt<1>("h1") - node T_602 = dshl(UInt<1>("h1"), idxPages.T_600.data) - node T_603 = bits(T_602, 5, 0) - idxPages.T_605.addr <= UInt<2>("h3") - idxPages.T_605.en <= UInt<1>("h1") - node T_607 = dshl(UInt<1>("h1"), idxPages.T_605.data) - node T_608 = bits(T_607, 5, 0) - idxPages.T_610.addr <= UInt<3>("h4") - idxPages.T_610.en <= UInt<1>("h1") - node T_612 = dshl(UInt<1>("h1"), idxPages.T_610.data) - node T_613 = bits(T_612, 5, 0) - idxPages.T_615.addr <= UInt<3>("h5") - idxPages.T_615.en <= UInt<1>("h1") - node T_617 = dshl(UInt<1>("h1"), idxPages.T_615.data) - node T_618 = bits(T_617, 5, 0) - idxPages.T_620.addr <= UInt<3>("h6") - idxPages.T_620.en <= UInt<1>("h1") - node T_622 = dshl(UInt<1>("h1"), idxPages.T_620.data) - node T_623 = bits(T_622, 5, 0) - idxPages.T_625.addr <= UInt<3>("h7") - idxPages.T_625.en <= UInt<1>("h1") - node T_627 = dshl(UInt<1>("h1"), idxPages.T_625.data) - node T_628 = bits(T_627, 5, 0) - idxPages.T_630.addr <= UInt<4>("h8") - idxPages.T_630.en <= UInt<1>("h1") - node T_632 = dshl(UInt<1>("h1"), idxPages.T_630.data) - node T_633 = bits(T_632, 5, 0) - idxPages.T_635.addr <= UInt<4>("h9") - idxPages.T_635.en <= UInt<1>("h1") - node T_637 = dshl(UInt<1>("h1"), idxPages.T_635.data) - node T_638 = bits(T_637, 5, 0) - idxPages.T_640.addr <= UInt<4>("ha") - idxPages.T_640.en <= UInt<1>("h1") - node T_642 = dshl(UInt<1>("h1"), idxPages.T_640.data) - node T_643 = bits(T_642, 5, 0) - idxPages.T_645.addr <= UInt<4>("hb") - idxPages.T_645.en <= UInt<1>("h1") - node T_647 = dshl(UInt<1>("h1"), idxPages.T_645.data) - node T_648 = bits(T_647, 5, 0) - idxPages.T_650.addr <= UInt<4>("hc") - idxPages.T_650.en <= UInt<1>("h1") - node T_652 = dshl(UInt<1>("h1"), idxPages.T_650.data) - node T_653 = bits(T_652, 5, 0) - idxPages.T_655.addr <= UInt<4>("hd") - idxPages.T_655.en <= UInt<1>("h1") - node T_657 = dshl(UInt<1>("h1"), idxPages.T_655.data) - node T_658 = bits(T_657, 5, 0) - idxPages.T_660.addr <= UInt<4>("he") - idxPages.T_660.en <= UInt<1>("h1") - node T_662 = dshl(UInt<1>("h1"), idxPages.T_660.data) - node T_663 = bits(T_662, 5, 0) - idxPages.T_665.addr <= UInt<4>("hf") - idxPages.T_665.en <= UInt<1>("h1") - node T_667 = dshl(UInt<1>("h1"), idxPages.T_665.data) - node T_668 = bits(T_667, 5, 0) - idxPages.T_670.addr <= UInt<5>("h10") - idxPages.T_670.en <= UInt<1>("h1") - node T_672 = dshl(UInt<1>("h1"), idxPages.T_670.data) - node T_673 = bits(T_672, 5, 0) - idxPages.T_675.addr <= UInt<5>("h11") - idxPages.T_675.en <= UInt<1>("h1") - node T_677 = dshl(UInt<1>("h1"), idxPages.T_675.data) - node T_678 = bits(T_677, 5, 0) - idxPages.T_680.addr <= UInt<5>("h12") - idxPages.T_680.en <= UInt<1>("h1") - node T_682 = dshl(UInt<1>("h1"), idxPages.T_680.data) - node T_683 = bits(T_682, 5, 0) - idxPages.T_685.addr <= UInt<5>("h13") - idxPages.T_685.en <= UInt<1>("h1") - node T_687 = dshl(UInt<1>("h1"), idxPages.T_685.data) - node T_688 = bits(T_687, 5, 0) - idxPages.T_690.addr <= UInt<5>("h14") - idxPages.T_690.en <= UInt<1>("h1") - node T_692 = dshl(UInt<1>("h1"), idxPages.T_690.data) - node T_693 = bits(T_692, 5, 0) - idxPages.T_695.addr <= UInt<5>("h15") - idxPages.T_695.en <= UInt<1>("h1") - node T_697 = dshl(UInt<1>("h1"), idxPages.T_695.data) - node T_698 = bits(T_697, 5, 0) - idxPages.T_700.addr <= UInt<5>("h16") - idxPages.T_700.en <= UInt<1>("h1") - node T_702 = dshl(UInt<1>("h1"), idxPages.T_700.data) - node T_703 = bits(T_702, 5, 0) - idxPages.T_705.addr <= UInt<5>("h17") - idxPages.T_705.en <= UInt<1>("h1") - node T_707 = dshl(UInt<1>("h1"), idxPages.T_705.data) - node T_708 = bits(T_707, 5, 0) - idxPages.T_710.addr <= UInt<5>("h18") - idxPages.T_710.en <= UInt<1>("h1") - node T_712 = dshl(UInt<1>("h1"), idxPages.T_710.data) - node T_713 = bits(T_712, 5, 0) - idxPages.T_715.addr <= UInt<5>("h19") - idxPages.T_715.en <= UInt<1>("h1") - node T_717 = dshl(UInt<1>("h1"), idxPages.T_715.data) - node T_718 = bits(T_717, 5, 0) - idxPages.T_720.addr <= UInt<5>("h1a") - idxPages.T_720.en <= UInt<1>("h1") - node T_722 = dshl(UInt<1>("h1"), idxPages.T_720.data) - node T_723 = bits(T_722, 5, 0) - idxPages.T_725.addr <= UInt<5>("h1b") - idxPages.T_725.en <= UInt<1>("h1") - node T_727 = dshl(UInt<1>("h1"), idxPages.T_725.data) - node T_728 = bits(T_727, 5, 0) - idxPages.T_730.addr <= UInt<5>("h1c") - idxPages.T_730.en <= UInt<1>("h1") - node T_732 = dshl(UInt<1>("h1"), idxPages.T_730.data) - node T_733 = bits(T_732, 5, 0) - idxPages.T_735.addr <= UInt<5>("h1d") - idxPages.T_735.en <= UInt<1>("h1") - node T_737 = dshl(UInt<1>("h1"), idxPages.T_735.data) - node T_738 = bits(T_737, 5, 0) - idxPages.T_740.addr <= UInt<5>("h1e") - idxPages.T_740.en <= UInt<1>("h1") - node T_742 = dshl(UInt<1>("h1"), idxPages.T_740.data) - node T_743 = bits(T_742, 5, 0) - idxPages.T_745.addr <= UInt<5>("h1f") - idxPages.T_745.en <= UInt<1>("h1") - node T_747 = dshl(UInt<1>("h1"), idxPages.T_745.data) - node T_748 = bits(T_747, 5, 0) - idxPages.T_750.addr <= UInt<6>("h20") - idxPages.T_750.en <= UInt<1>("h1") - node T_752 = dshl(UInt<1>("h1"), idxPages.T_750.data) - node T_753 = bits(T_752, 5, 0) - idxPages.T_755.addr <= UInt<6>("h21") - idxPages.T_755.en <= UInt<1>("h1") - node T_757 = dshl(UInt<1>("h1"), idxPages.T_755.data) - node T_758 = bits(T_757, 5, 0) - idxPages.T_760.addr <= UInt<6>("h22") - idxPages.T_760.en <= UInt<1>("h1") - node T_762 = dshl(UInt<1>("h1"), idxPages.T_760.data) - node T_763 = bits(T_762, 5, 0) - idxPages.T_765.addr <= UInt<6>("h23") - idxPages.T_765.en <= UInt<1>("h1") - node T_767 = dshl(UInt<1>("h1"), idxPages.T_765.data) - node T_768 = bits(T_767, 5, 0) - idxPages.T_770.addr <= UInt<6>("h24") - idxPages.T_770.en <= UInt<1>("h1") - node T_772 = dshl(UInt<1>("h1"), idxPages.T_770.data) - node T_773 = bits(T_772, 5, 0) - idxPages.T_775.addr <= UInt<6>("h25") - idxPages.T_775.en <= UInt<1>("h1") - node T_777 = dshl(UInt<1>("h1"), idxPages.T_775.data) - node T_778 = bits(T_777, 5, 0) - idxPages.T_780.addr <= UInt<6>("h26") - idxPages.T_780.en <= UInt<1>("h1") - node T_782 = dshl(UInt<1>("h1"), idxPages.T_780.data) - node T_783 = bits(T_782, 5, 0) - idxPages.T_785.addr <= UInt<6>("h27") - idxPages.T_785.en <= UInt<1>("h1") - node T_787 = dshl(UInt<1>("h1"), idxPages.T_785.data) - node T_788 = bits(T_787, 5, 0) - idxPages.T_790.addr <= UInt<6>("h28") - idxPages.T_790.en <= UInt<1>("h1") - node T_792 = dshl(UInt<1>("h1"), idxPages.T_790.data) - node T_793 = bits(T_792, 5, 0) - idxPages.T_795.addr <= UInt<6>("h29") - idxPages.T_795.en <= UInt<1>("h1") - node T_797 = dshl(UInt<1>("h1"), idxPages.T_795.data) - node T_798 = bits(T_797, 5, 0) - idxPages.T_800.addr <= UInt<6>("h2a") - idxPages.T_800.en <= UInt<1>("h1") - node T_802 = dshl(UInt<1>("h1"), idxPages.T_800.data) - node T_803 = bits(T_802, 5, 0) - idxPages.T_805.addr <= UInt<6>("h2b") - idxPages.T_805.en <= UInt<1>("h1") - node T_807 = dshl(UInt<1>("h1"), idxPages.T_805.data) - node T_808 = bits(T_807, 5, 0) - idxPages.T_810.addr <= UInt<6>("h2c") - idxPages.T_810.en <= UInt<1>("h1") - node T_812 = dshl(UInt<1>("h1"), idxPages.T_810.data) - node T_813 = bits(T_812, 5, 0) - idxPages.T_815.addr <= UInt<6>("h2d") - idxPages.T_815.en <= UInt<1>("h1") - node T_817 = dshl(UInt<1>("h1"), idxPages.T_815.data) - node T_818 = bits(T_817, 5, 0) - idxPages.T_820.addr <= UInt<6>("h2e") - idxPages.T_820.en <= UInt<1>("h1") - node T_822 = dshl(UInt<1>("h1"), idxPages.T_820.data) - node T_823 = bits(T_822, 5, 0) - idxPages.T_825.addr <= UInt<6>("h2f") - idxPages.T_825.en <= UInt<1>("h1") - node T_827 = dshl(UInt<1>("h1"), idxPages.T_825.data) - node T_828 = bits(T_827, 5, 0) - idxPages.T_830.addr <= UInt<6>("h30") - idxPages.T_830.en <= UInt<1>("h1") - node T_832 = dshl(UInt<1>("h1"), idxPages.T_830.data) - node T_833 = bits(T_832, 5, 0) - idxPages.T_835.addr <= UInt<6>("h31") - idxPages.T_835.en <= UInt<1>("h1") - node T_837 = dshl(UInt<1>("h1"), idxPages.T_835.data) - node T_838 = bits(T_837, 5, 0) - idxPages.T_840.addr <= UInt<6>("h32") - idxPages.T_840.en <= UInt<1>("h1") - node T_842 = dshl(UInt<1>("h1"), idxPages.T_840.data) - node T_843 = bits(T_842, 5, 0) - idxPages.T_845.addr <= UInt<6>("h33") - idxPages.T_845.en <= UInt<1>("h1") - node T_847 = dshl(UInt<1>("h1"), idxPages.T_845.data) - node T_848 = bits(T_847, 5, 0) - idxPages.T_850.addr <= UInt<6>("h34") - idxPages.T_850.en <= UInt<1>("h1") - node T_852 = dshl(UInt<1>("h1"), idxPages.T_850.data) - node T_853 = bits(T_852, 5, 0) - idxPages.T_855.addr <= UInt<6>("h35") - idxPages.T_855.en <= UInt<1>("h1") - node T_857 = dshl(UInt<1>("h1"), idxPages.T_855.data) - node T_858 = bits(T_857, 5, 0) - idxPages.T_860.addr <= UInt<6>("h36") - idxPages.T_860.en <= UInt<1>("h1") - node T_862 = dshl(UInt<1>("h1"), idxPages.T_860.data) - node T_863 = bits(T_862, 5, 0) - idxPages.T_865.addr <= UInt<6>("h37") - idxPages.T_865.en <= UInt<1>("h1") - node T_867 = dshl(UInt<1>("h1"), idxPages.T_865.data) - node T_868 = bits(T_867, 5, 0) - idxPages.T_870.addr <= UInt<6>("h38") - idxPages.T_870.en <= UInt<1>("h1") - node T_872 = dshl(UInt<1>("h1"), idxPages.T_870.data) - node T_873 = bits(T_872, 5, 0) - idxPages.T_875.addr <= UInt<6>("h39") - idxPages.T_875.en <= UInt<1>("h1") - node T_877 = dshl(UInt<1>("h1"), idxPages.T_875.data) - node T_878 = bits(T_877, 5, 0) - idxPages.T_880.addr <= UInt<6>("h3a") - idxPages.T_880.en <= UInt<1>("h1") - node T_882 = dshl(UInt<1>("h1"), idxPages.T_880.data) - node T_883 = bits(T_882, 5, 0) - idxPages.T_885.addr <= UInt<6>("h3b") - idxPages.T_885.en <= UInt<1>("h1") - node T_887 = dshl(UInt<1>("h1"), idxPages.T_885.data) - node T_888 = bits(T_887, 5, 0) - idxPages.T_890.addr <= UInt<6>("h3c") - idxPages.T_890.en <= UInt<1>("h1") - node T_892 = dshl(UInt<1>("h1"), idxPages.T_890.data) - node T_893 = bits(T_892, 5, 0) - idxPages.T_895.addr <= UInt<6>("h3d") - idxPages.T_895.en <= UInt<1>("h1") - node T_897 = dshl(UInt<1>("h1"), idxPages.T_895.data) - node T_898 = bits(T_897, 5, 0) - tgtPages.T_900.addr <= UInt<1>("h0") - tgtPages.T_900.en <= UInt<1>("h1") - node T_902 = dshl(UInt<1>("h1"), tgtPages.T_900.data) - node T_903 = bits(T_902, 5, 0) - tgtPages.T_905.addr <= UInt<1>("h1") - tgtPages.T_905.en <= UInt<1>("h1") - node T_907 = dshl(UInt<1>("h1"), tgtPages.T_905.data) - node T_908 = bits(T_907, 5, 0) - tgtPages.T_910.addr <= UInt<2>("h2") - tgtPages.T_910.en <= UInt<1>("h1") - node T_912 = dshl(UInt<1>("h1"), tgtPages.T_910.data) - node T_913 = bits(T_912, 5, 0) - tgtPages.T_915.addr <= UInt<2>("h3") - tgtPages.T_915.en <= UInt<1>("h1") - node T_917 = dshl(UInt<1>("h1"), tgtPages.T_915.data) - node T_918 = bits(T_917, 5, 0) - tgtPages.T_920.addr <= UInt<3>("h4") - tgtPages.T_920.en <= UInt<1>("h1") - node T_922 = dshl(UInt<1>("h1"), tgtPages.T_920.data) - node T_923 = bits(T_922, 5, 0) - tgtPages.T_925.addr <= UInt<3>("h5") - tgtPages.T_925.en <= UInt<1>("h1") - node T_927 = dshl(UInt<1>("h1"), tgtPages.T_925.data) - node T_928 = bits(T_927, 5, 0) - tgtPages.T_930.addr <= UInt<3>("h6") - tgtPages.T_930.en <= UInt<1>("h1") - node T_932 = dshl(UInt<1>("h1"), tgtPages.T_930.data) - node T_933 = bits(T_932, 5, 0) - tgtPages.T_935.addr <= UInt<3>("h7") - tgtPages.T_935.en <= UInt<1>("h1") - node T_937 = dshl(UInt<1>("h1"), tgtPages.T_935.data) - node T_938 = bits(T_937, 5, 0) - tgtPages.T_940.addr <= UInt<4>("h8") - tgtPages.T_940.en <= UInt<1>("h1") - node T_942 = dshl(UInt<1>("h1"), tgtPages.T_940.data) - node T_943 = bits(T_942, 5, 0) - tgtPages.T_945.addr <= UInt<4>("h9") - tgtPages.T_945.en <= UInt<1>("h1") - node T_947 = dshl(UInt<1>("h1"), tgtPages.T_945.data) - node T_948 = bits(T_947, 5, 0) - tgtPages.T_950.addr <= UInt<4>("ha") - tgtPages.T_950.en <= UInt<1>("h1") - node T_952 = dshl(UInt<1>("h1"), tgtPages.T_950.data) - node T_953 = bits(T_952, 5, 0) - tgtPages.T_955.addr <= UInt<4>("hb") - tgtPages.T_955.en <= UInt<1>("h1") - node T_957 = dshl(UInt<1>("h1"), tgtPages.T_955.data) - node T_958 = bits(T_957, 5, 0) - tgtPages.T_960.addr <= UInt<4>("hc") - tgtPages.T_960.en <= UInt<1>("h1") - node T_962 = dshl(UInt<1>("h1"), tgtPages.T_960.data) - node T_963 = bits(T_962, 5, 0) - tgtPages.T_965.addr <= UInt<4>("hd") - tgtPages.T_965.en <= UInt<1>("h1") - node T_967 = dshl(UInt<1>("h1"), tgtPages.T_965.data) - node T_968 = bits(T_967, 5, 0) - tgtPages.T_970.addr <= UInt<4>("he") - tgtPages.T_970.en <= UInt<1>("h1") - node T_972 = dshl(UInt<1>("h1"), tgtPages.T_970.data) - node T_973 = bits(T_972, 5, 0) - tgtPages.T_975.addr <= UInt<4>("hf") - tgtPages.T_975.en <= UInt<1>("h1") - node T_977 = dshl(UInt<1>("h1"), tgtPages.T_975.data) - node T_978 = bits(T_977, 5, 0) - tgtPages.T_980.addr <= UInt<5>("h10") - tgtPages.T_980.en <= UInt<1>("h1") - node T_982 = dshl(UInt<1>("h1"), tgtPages.T_980.data) - node T_983 = bits(T_982, 5, 0) - tgtPages.T_985.addr <= UInt<5>("h11") - tgtPages.T_985.en <= UInt<1>("h1") - node T_987 = dshl(UInt<1>("h1"), tgtPages.T_985.data) - node T_988 = bits(T_987, 5, 0) - tgtPages.T_990.addr <= UInt<5>("h12") - tgtPages.T_990.en <= UInt<1>("h1") - node T_992 = dshl(UInt<1>("h1"), tgtPages.T_990.data) - node T_993 = bits(T_992, 5, 0) - tgtPages.T_995.addr <= UInt<5>("h13") - tgtPages.T_995.en <= UInt<1>("h1") - node T_997 = dshl(UInt<1>("h1"), tgtPages.T_995.data) - node T_998 = bits(T_997, 5, 0) - tgtPages.T_1000.addr <= UInt<5>("h14") - tgtPages.T_1000.en <= UInt<1>("h1") - node T_1002 = dshl(UInt<1>("h1"), tgtPages.T_1000.data) - node T_1003 = bits(T_1002, 5, 0) - tgtPages.T_1005.addr <= UInt<5>("h15") - tgtPages.T_1005.en <= UInt<1>("h1") - node T_1007 = dshl(UInt<1>("h1"), tgtPages.T_1005.data) - node T_1008 = bits(T_1007, 5, 0) - tgtPages.T_1010.addr <= UInt<5>("h16") - tgtPages.T_1010.en <= UInt<1>("h1") - node T_1012 = dshl(UInt<1>("h1"), tgtPages.T_1010.data) - node T_1013 = bits(T_1012, 5, 0) - tgtPages.T_1015.addr <= UInt<5>("h17") - tgtPages.T_1015.en <= UInt<1>("h1") - node T_1017 = dshl(UInt<1>("h1"), tgtPages.T_1015.data) - node T_1018 = bits(T_1017, 5, 0) - tgtPages.T_1020.addr <= UInt<5>("h18") - tgtPages.T_1020.en <= UInt<1>("h1") - node T_1022 = dshl(UInt<1>("h1"), tgtPages.T_1020.data) - node T_1023 = bits(T_1022, 5, 0) - tgtPages.T_1025.addr <= UInt<5>("h19") - tgtPages.T_1025.en <= UInt<1>("h1") - node T_1027 = dshl(UInt<1>("h1"), tgtPages.T_1025.data) - node T_1028 = bits(T_1027, 5, 0) - tgtPages.T_1030.addr <= UInt<5>("h1a") - tgtPages.T_1030.en <= UInt<1>("h1") - node T_1032 = dshl(UInt<1>("h1"), tgtPages.T_1030.data) - node T_1033 = bits(T_1032, 5, 0) - tgtPages.T_1035.addr <= UInt<5>("h1b") - tgtPages.T_1035.en <= UInt<1>("h1") - node T_1037 = dshl(UInt<1>("h1"), tgtPages.T_1035.data) - node T_1038 = bits(T_1037, 5, 0) - tgtPages.T_1040.addr <= UInt<5>("h1c") - tgtPages.T_1040.en <= UInt<1>("h1") - node T_1042 = dshl(UInt<1>("h1"), tgtPages.T_1040.data) - node T_1043 = bits(T_1042, 5, 0) - tgtPages.T_1045.addr <= UInt<5>("h1d") - tgtPages.T_1045.en <= UInt<1>("h1") - node T_1047 = dshl(UInt<1>("h1"), tgtPages.T_1045.data) - node T_1048 = bits(T_1047, 5, 0) - tgtPages.T_1050.addr <= UInt<5>("h1e") - tgtPages.T_1050.en <= UInt<1>("h1") - node T_1052 = dshl(UInt<1>("h1"), tgtPages.T_1050.data) - node T_1053 = bits(T_1052, 5, 0) - tgtPages.T_1055.addr <= UInt<5>("h1f") - tgtPages.T_1055.en <= UInt<1>("h1") - node T_1057 = dshl(UInt<1>("h1"), tgtPages.T_1055.data) - node T_1058 = bits(T_1057, 5, 0) - tgtPages.T_1060.addr <= UInt<6>("h20") - tgtPages.T_1060.en <= UInt<1>("h1") - node T_1062 = dshl(UInt<1>("h1"), tgtPages.T_1060.data) - node T_1063 = bits(T_1062, 5, 0) - tgtPages.T_1065.addr <= UInt<6>("h21") - tgtPages.T_1065.en <= UInt<1>("h1") - node T_1067 = dshl(UInt<1>("h1"), tgtPages.T_1065.data) - node T_1068 = bits(T_1067, 5, 0) - tgtPages.T_1070.addr <= UInt<6>("h22") - tgtPages.T_1070.en <= UInt<1>("h1") - node T_1072 = dshl(UInt<1>("h1"), tgtPages.T_1070.data) - node T_1073 = bits(T_1072, 5, 0) - tgtPages.T_1075.addr <= UInt<6>("h23") - tgtPages.T_1075.en <= UInt<1>("h1") - node T_1077 = dshl(UInt<1>("h1"), tgtPages.T_1075.data) - node T_1078 = bits(T_1077, 5, 0) - tgtPages.T_1080.addr <= UInt<6>("h24") - tgtPages.T_1080.en <= UInt<1>("h1") - node T_1082 = dshl(UInt<1>("h1"), tgtPages.T_1080.data) - node T_1083 = bits(T_1082, 5, 0) - tgtPages.T_1085.addr <= UInt<6>("h25") - tgtPages.T_1085.en <= UInt<1>("h1") - node T_1087 = dshl(UInt<1>("h1"), tgtPages.T_1085.data) - node T_1088 = bits(T_1087, 5, 0) - tgtPages.T_1090.addr <= UInt<6>("h26") - tgtPages.T_1090.en <= UInt<1>("h1") - node T_1092 = dshl(UInt<1>("h1"), tgtPages.T_1090.data) - node T_1093 = bits(T_1092, 5, 0) - tgtPages.T_1095.addr <= UInt<6>("h27") - tgtPages.T_1095.en <= UInt<1>("h1") - node T_1097 = dshl(UInt<1>("h1"), tgtPages.T_1095.data) - node T_1098 = bits(T_1097, 5, 0) - tgtPages.T_1100.addr <= UInt<6>("h28") - tgtPages.T_1100.en <= UInt<1>("h1") - node T_1102 = dshl(UInt<1>("h1"), tgtPages.T_1100.data) - node T_1103 = bits(T_1102, 5, 0) - tgtPages.T_1105.addr <= UInt<6>("h29") - tgtPages.T_1105.en <= UInt<1>("h1") - node T_1107 = dshl(UInt<1>("h1"), tgtPages.T_1105.data) - node T_1108 = bits(T_1107, 5, 0) - tgtPages.T_1110.addr <= UInt<6>("h2a") - tgtPages.T_1110.en <= UInt<1>("h1") - node T_1112 = dshl(UInt<1>("h1"), tgtPages.T_1110.data) - node T_1113 = bits(T_1112, 5, 0) - tgtPages.T_1115.addr <= UInt<6>("h2b") - tgtPages.T_1115.en <= UInt<1>("h1") - node T_1117 = dshl(UInt<1>("h1"), tgtPages.T_1115.data) - node T_1118 = bits(T_1117, 5, 0) - tgtPages.T_1120.addr <= UInt<6>("h2c") - tgtPages.T_1120.en <= UInt<1>("h1") - node T_1122 = dshl(UInt<1>("h1"), tgtPages.T_1120.data) - node T_1123 = bits(T_1122, 5, 0) - tgtPages.T_1125.addr <= UInt<6>("h2d") - tgtPages.T_1125.en <= UInt<1>("h1") - node T_1127 = dshl(UInt<1>("h1"), tgtPages.T_1125.data) - node T_1128 = bits(T_1127, 5, 0) - tgtPages.T_1130.addr <= UInt<6>("h2e") - tgtPages.T_1130.en <= UInt<1>("h1") - node T_1132 = dshl(UInt<1>("h1"), tgtPages.T_1130.data) - node T_1133 = bits(T_1132, 5, 0) - tgtPages.T_1135.addr <= UInt<6>("h2f") - tgtPages.T_1135.en <= UInt<1>("h1") - node T_1137 = dshl(UInt<1>("h1"), tgtPages.T_1135.data) - node T_1138 = bits(T_1137, 5, 0) - tgtPages.T_1140.addr <= UInt<6>("h30") - tgtPages.T_1140.en <= UInt<1>("h1") - node T_1142 = dshl(UInt<1>("h1"), tgtPages.T_1140.data) - node T_1143 = bits(T_1142, 5, 0) - tgtPages.T_1145.addr <= UInt<6>("h31") - tgtPages.T_1145.en <= UInt<1>("h1") - node T_1147 = dshl(UInt<1>("h1"), tgtPages.T_1145.data) - node T_1148 = bits(T_1147, 5, 0) - tgtPages.T_1150.addr <= UInt<6>("h32") - tgtPages.T_1150.en <= UInt<1>("h1") - node T_1152 = dshl(UInt<1>("h1"), tgtPages.T_1150.data) - node T_1153 = bits(T_1152, 5, 0) - tgtPages.T_1155.addr <= UInt<6>("h33") - tgtPages.T_1155.en <= UInt<1>("h1") - node T_1157 = dshl(UInt<1>("h1"), tgtPages.T_1155.data) - node T_1158 = bits(T_1157, 5, 0) - tgtPages.T_1160.addr <= UInt<6>("h34") - tgtPages.T_1160.en <= UInt<1>("h1") - node T_1162 = dshl(UInt<1>("h1"), tgtPages.T_1160.data) - node T_1163 = bits(T_1162, 5, 0) - tgtPages.T_1165.addr <= UInt<6>("h35") - tgtPages.T_1165.en <= UInt<1>("h1") - node T_1167 = dshl(UInt<1>("h1"), tgtPages.T_1165.data) - node T_1168 = bits(T_1167, 5, 0) - tgtPages.T_1170.addr <= UInt<6>("h36") - tgtPages.T_1170.en <= UInt<1>("h1") - node T_1172 = dshl(UInt<1>("h1"), tgtPages.T_1170.data) - node T_1173 = bits(T_1172, 5, 0) - tgtPages.T_1175.addr <= UInt<6>("h37") - tgtPages.T_1175.en <= UInt<1>("h1") - node T_1177 = dshl(UInt<1>("h1"), tgtPages.T_1175.data) - node T_1178 = bits(T_1177, 5, 0) - tgtPages.T_1180.addr <= UInt<6>("h38") - tgtPages.T_1180.en <= UInt<1>("h1") - node T_1182 = dshl(UInt<1>("h1"), tgtPages.T_1180.data) - node T_1183 = bits(T_1182, 5, 0) - tgtPages.T_1185.addr <= UInt<6>("h39") - tgtPages.T_1185.en <= UInt<1>("h1") - node T_1187 = dshl(UInt<1>("h1"), tgtPages.T_1185.data) - node T_1188 = bits(T_1187, 5, 0) - tgtPages.T_1190.addr <= UInt<6>("h3a") - tgtPages.T_1190.en <= UInt<1>("h1") - node T_1192 = dshl(UInt<1>("h1"), tgtPages.T_1190.data) - node T_1193 = bits(T_1192, 5, 0) - tgtPages.T_1195.addr <= UInt<6>("h3b") - tgtPages.T_1195.en <= UInt<1>("h1") - node T_1197 = dshl(UInt<1>("h1"), tgtPages.T_1195.data) - node T_1198 = bits(T_1197, 5, 0) - tgtPages.T_1200.addr <= UInt<6>("h3c") - tgtPages.T_1200.en <= UInt<1>("h1") - node T_1202 = dshl(UInt<1>("h1"), tgtPages.T_1200.data) - node T_1203 = bits(T_1202, 5, 0) - tgtPages.T_1205.addr <= UInt<6>("h3d") - tgtPages.T_1205.en <= UInt<1>("h1") - node T_1207 = dshl(UInt<1>("h1"), tgtPages.T_1205.data) - node T_1208 = bits(T_1207, 5, 0) - reg useRAS : UInt<1>[62], clk with : - reset => (UInt<1>("h0"), useRAS) - reg isJump : UInt<1>[62], clk with : - reset => (UInt<1>("h0"), isJump) - mem brIdx : - data-type => UInt<1> - depth => 62 - write-latency => 1 - read-latency => 0 - reader => T_4212 - writer => T_3476 - brIdx.T_4212.addr is invalid - brIdx.T_4212.clk <= clk - brIdx.T_4212.en <= UInt<1>("h0") - brIdx.T_3476.addr is invalid - brIdx.T_3476.clk <= clk - brIdx.T_3476.en <= UInt<1>("h0") - brIdx.T_3476.data is invalid - brIdx.T_3476.mask <= UInt<1>("h0") - reg T_1478 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_1478 <= io.btb_update.valid - reg T_1479 : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk with : - reset => (UInt<1>("h0"), T_1479) - when io.btb_update.valid : - T_1479 <- io.btb_update.bits - skip - wire r_btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} - r_btb_update is invalid - r_btb_update.valid <= T_1478 - r_btb_update.bits <- T_1479 - node T_1663 = shr(io.req.bits.addr, 12) - pages.T_1665.addr <= UInt<1>("h0") - pages.T_1665.en <= UInt<1>("h1") - node T_1666 = eq(pages.T_1665.data, T_1663) - pages.T_1668.addr <= UInt<1>("h1") - pages.T_1668.en <= UInt<1>("h1") - node T_1669 = eq(pages.T_1668.data, T_1663) - pages.T_1671.addr <= UInt<2>("h2") - pages.T_1671.en <= UInt<1>("h1") - node T_1672 = eq(pages.T_1671.data, T_1663) - pages.T_1674.addr <= UInt<2>("h3") - pages.T_1674.en <= UInt<1>("h1") - node T_1675 = eq(pages.T_1674.data, T_1663) - pages.T_1677.addr <= UInt<3>("h4") - pages.T_1677.en <= UInt<1>("h1") - node T_1678 = eq(pages.T_1677.data, T_1663) - pages.T_1680.addr <= UInt<3>("h5") - pages.T_1680.en <= UInt<1>("h1") - node T_1681 = eq(pages.T_1680.data, T_1663) - wire T_1683 : UInt<1>[6] - T_1683[0] <= T_1666 - T_1683[1] <= T_1669 - T_1683[2] <= T_1672 - T_1683[3] <= T_1675 - T_1683[4] <= T_1678 - T_1683[5] <= T_1681 - node T_1691 = cat(T_1683[4], T_1683[3]) - node T_1692 = cat(T_1683[5], T_1691) - node T_1693 = cat(T_1683[1], T_1683[0]) - node T_1694 = cat(T_1683[2], T_1693) - node T_1695 = cat(T_1692, T_1694) - node pageHit = and(T_1695, pageValid) - node T_1697 = bits(io.req.bits.addr, 11, 0) - idxs.T_1699.addr <= UInt<1>("h0") - idxs.T_1699.en <= UInt<1>("h1") - node T_1700 = eq(idxs.T_1699.data, T_1697) - idxs.T_1702.addr <= UInt<1>("h1") - idxs.T_1702.en <= UInt<1>("h1") - node T_1703 = eq(idxs.T_1702.data, T_1697) - idxs.T_1705.addr <= UInt<2>("h2") - idxs.T_1705.en <= UInt<1>("h1") - node T_1706 = eq(idxs.T_1705.data, T_1697) - idxs.T_1708.addr <= UInt<2>("h3") - idxs.T_1708.en <= UInt<1>("h1") - node T_1709 = eq(idxs.T_1708.data, T_1697) - idxs.T_1711.addr <= UInt<3>("h4") - idxs.T_1711.en <= UInt<1>("h1") - node T_1712 = eq(idxs.T_1711.data, T_1697) - idxs.T_1714.addr <= UInt<3>("h5") - idxs.T_1714.en <= UInt<1>("h1") - node T_1715 = eq(idxs.T_1714.data, T_1697) - idxs.T_1717.addr <= UInt<3>("h6") - idxs.T_1717.en <= UInt<1>("h1") - node T_1718 = eq(idxs.T_1717.data, T_1697) - idxs.T_1720.addr <= UInt<3>("h7") - idxs.T_1720.en <= UInt<1>("h1") - node T_1721 = eq(idxs.T_1720.data, T_1697) - idxs.T_1723.addr <= UInt<4>("h8") - idxs.T_1723.en <= UInt<1>("h1") - node T_1724 = eq(idxs.T_1723.data, T_1697) - idxs.T_1726.addr <= UInt<4>("h9") - idxs.T_1726.en <= UInt<1>("h1") - node T_1727 = eq(idxs.T_1726.data, T_1697) - idxs.T_1729.addr <= UInt<4>("ha") - idxs.T_1729.en <= UInt<1>("h1") - node T_1730 = eq(idxs.T_1729.data, T_1697) - idxs.T_1732.addr <= UInt<4>("hb") - idxs.T_1732.en <= UInt<1>("h1") - node T_1733 = eq(idxs.T_1732.data, T_1697) - idxs.T_1735.addr <= UInt<4>("hc") - idxs.T_1735.en <= UInt<1>("h1") - node T_1736 = eq(idxs.T_1735.data, T_1697) - idxs.T_1738.addr <= UInt<4>("hd") - idxs.T_1738.en <= UInt<1>("h1") - node T_1739 = eq(idxs.T_1738.data, T_1697) - idxs.T_1741.addr <= UInt<4>("he") - idxs.T_1741.en <= UInt<1>("h1") - node T_1742 = eq(idxs.T_1741.data, T_1697) - idxs.T_1744.addr <= UInt<4>("hf") - idxs.T_1744.en <= UInt<1>("h1") - node T_1745 = eq(idxs.T_1744.data, T_1697) - idxs.T_1747.addr <= UInt<5>("h10") - idxs.T_1747.en <= UInt<1>("h1") - node T_1748 = eq(idxs.T_1747.data, T_1697) - idxs.T_1750.addr <= UInt<5>("h11") - idxs.T_1750.en <= UInt<1>("h1") - node T_1751 = eq(idxs.T_1750.data, T_1697) - idxs.T_1753.addr <= UInt<5>("h12") - idxs.T_1753.en <= UInt<1>("h1") - node T_1754 = eq(idxs.T_1753.data, T_1697) - idxs.T_1756.addr <= UInt<5>("h13") - idxs.T_1756.en <= UInt<1>("h1") - node T_1757 = eq(idxs.T_1756.data, T_1697) - idxs.T_1759.addr <= UInt<5>("h14") - idxs.T_1759.en <= UInt<1>("h1") - node T_1760 = eq(idxs.T_1759.data, T_1697) - idxs.T_1762.addr <= UInt<5>("h15") - idxs.T_1762.en <= UInt<1>("h1") - node T_1763 = eq(idxs.T_1762.data, T_1697) - idxs.T_1765.addr <= UInt<5>("h16") - idxs.T_1765.en <= UInt<1>("h1") - node T_1766 = eq(idxs.T_1765.data, T_1697) - idxs.T_1768.addr <= UInt<5>("h17") - idxs.T_1768.en <= UInt<1>("h1") - node T_1769 = eq(idxs.T_1768.data, T_1697) - idxs.T_1771.addr <= UInt<5>("h18") - idxs.T_1771.en <= UInt<1>("h1") - node T_1772 = eq(idxs.T_1771.data, T_1697) - idxs.T_1774.addr <= UInt<5>("h19") - idxs.T_1774.en <= UInt<1>("h1") - node T_1775 = eq(idxs.T_1774.data, T_1697) - idxs.T_1777.addr <= UInt<5>("h1a") - idxs.T_1777.en <= UInt<1>("h1") - node T_1778 = eq(idxs.T_1777.data, T_1697) - idxs.T_1780.addr <= UInt<5>("h1b") - idxs.T_1780.en <= UInt<1>("h1") - node T_1781 = eq(idxs.T_1780.data, T_1697) - idxs.T_1783.addr <= UInt<5>("h1c") - idxs.T_1783.en <= UInt<1>("h1") - node T_1784 = eq(idxs.T_1783.data, T_1697) - idxs.T_1786.addr <= UInt<5>("h1d") - idxs.T_1786.en <= UInt<1>("h1") - node T_1787 = eq(idxs.T_1786.data, T_1697) - idxs.T_1789.addr <= UInt<5>("h1e") - idxs.T_1789.en <= UInt<1>("h1") - node T_1790 = eq(idxs.T_1789.data, T_1697) - idxs.T_1792.addr <= UInt<5>("h1f") - idxs.T_1792.en <= UInt<1>("h1") - node T_1793 = eq(idxs.T_1792.data, T_1697) - idxs.T_1795.addr <= UInt<6>("h20") - idxs.T_1795.en <= UInt<1>("h1") - node T_1796 = eq(idxs.T_1795.data, T_1697) - idxs.T_1798.addr <= UInt<6>("h21") - idxs.T_1798.en <= UInt<1>("h1") - node T_1799 = eq(idxs.T_1798.data, T_1697) - idxs.T_1801.addr <= UInt<6>("h22") - idxs.T_1801.en <= UInt<1>("h1") - node T_1802 = eq(idxs.T_1801.data, T_1697) - idxs.T_1804.addr <= UInt<6>("h23") - idxs.T_1804.en <= UInt<1>("h1") - node T_1805 = eq(idxs.T_1804.data, T_1697) - idxs.T_1807.addr <= UInt<6>("h24") - idxs.T_1807.en <= UInt<1>("h1") - node T_1808 = eq(idxs.T_1807.data, T_1697) - idxs.T_1810.addr <= UInt<6>("h25") - idxs.T_1810.en <= UInt<1>("h1") - node T_1811 = eq(idxs.T_1810.data, T_1697) - idxs.T_1813.addr <= UInt<6>("h26") - idxs.T_1813.en <= UInt<1>("h1") - node T_1814 = eq(idxs.T_1813.data, T_1697) - idxs.T_1816.addr <= UInt<6>("h27") - idxs.T_1816.en <= UInt<1>("h1") - node T_1817 = eq(idxs.T_1816.data, T_1697) - idxs.T_1819.addr <= UInt<6>("h28") - idxs.T_1819.en <= UInt<1>("h1") - node T_1820 = eq(idxs.T_1819.data, T_1697) - idxs.T_1822.addr <= UInt<6>("h29") - idxs.T_1822.en <= UInt<1>("h1") - node T_1823 = eq(idxs.T_1822.data, T_1697) - idxs.T_1825.addr <= UInt<6>("h2a") - idxs.T_1825.en <= UInt<1>("h1") - node T_1826 = eq(idxs.T_1825.data, T_1697) - idxs.T_1828.addr <= UInt<6>("h2b") - idxs.T_1828.en <= UInt<1>("h1") - node T_1829 = eq(idxs.T_1828.data, T_1697) - idxs.T_1831.addr <= UInt<6>("h2c") - idxs.T_1831.en <= UInt<1>("h1") - node T_1832 = eq(idxs.T_1831.data, T_1697) - idxs.T_1834.addr <= UInt<6>("h2d") - idxs.T_1834.en <= UInt<1>("h1") - node T_1835 = eq(idxs.T_1834.data, T_1697) - idxs.T_1837.addr <= UInt<6>("h2e") - idxs.T_1837.en <= UInt<1>("h1") - node T_1838 = eq(idxs.T_1837.data, T_1697) - idxs.T_1840.addr <= UInt<6>("h2f") - idxs.T_1840.en <= UInt<1>("h1") - node T_1841 = eq(idxs.T_1840.data, T_1697) - idxs.T_1843.addr <= UInt<6>("h30") - idxs.T_1843.en <= UInt<1>("h1") - node T_1844 = eq(idxs.T_1843.data, T_1697) - idxs.T_1846.addr <= UInt<6>("h31") - idxs.T_1846.en <= UInt<1>("h1") - node T_1847 = eq(idxs.T_1846.data, T_1697) - idxs.T_1849.addr <= UInt<6>("h32") - idxs.T_1849.en <= UInt<1>("h1") - node T_1850 = eq(idxs.T_1849.data, T_1697) - idxs.T_1852.addr <= UInt<6>("h33") - idxs.T_1852.en <= UInt<1>("h1") - node T_1853 = eq(idxs.T_1852.data, T_1697) - idxs.T_1855.addr <= UInt<6>("h34") - idxs.T_1855.en <= UInt<1>("h1") - node T_1856 = eq(idxs.T_1855.data, T_1697) - idxs.T_1858.addr <= UInt<6>("h35") - idxs.T_1858.en <= UInt<1>("h1") - node T_1859 = eq(idxs.T_1858.data, T_1697) - idxs.T_1861.addr <= UInt<6>("h36") - idxs.T_1861.en <= UInt<1>("h1") - node T_1862 = eq(idxs.T_1861.data, T_1697) - idxs.T_1864.addr <= UInt<6>("h37") - idxs.T_1864.en <= UInt<1>("h1") - node T_1865 = eq(idxs.T_1864.data, T_1697) - idxs.T_1867.addr <= UInt<6>("h38") - idxs.T_1867.en <= UInt<1>("h1") - node T_1868 = eq(idxs.T_1867.data, T_1697) - idxs.T_1870.addr <= UInt<6>("h39") - idxs.T_1870.en <= UInt<1>("h1") - node T_1871 = eq(idxs.T_1870.data, T_1697) - idxs.T_1873.addr <= UInt<6>("h3a") - idxs.T_1873.en <= UInt<1>("h1") - node T_1874 = eq(idxs.T_1873.data, T_1697) - idxs.T_1876.addr <= UInt<6>("h3b") - idxs.T_1876.en <= UInt<1>("h1") - node T_1877 = eq(idxs.T_1876.data, T_1697) - idxs.T_1879.addr <= UInt<6>("h3c") - idxs.T_1879.en <= UInt<1>("h1") - node T_1880 = eq(idxs.T_1879.data, T_1697) - idxs.T_1882.addr <= UInt<6>("h3d") - idxs.T_1882.en <= UInt<1>("h1") - node T_1883 = eq(idxs.T_1882.data, T_1697) - wire T_1885 : UInt<1>[62] - T_1885[0] <= T_1700 - T_1885[1] <= T_1703 - T_1885[2] <= T_1706 - T_1885[3] <= T_1709 - T_1885[4] <= T_1712 - T_1885[5] <= T_1715 - T_1885[6] <= T_1718 - T_1885[7] <= T_1721 - T_1885[8] <= T_1724 - T_1885[9] <= T_1727 - T_1885[10] <= T_1730 - T_1885[11] <= T_1733 - T_1885[12] <= T_1736 - T_1885[13] <= T_1739 - T_1885[14] <= T_1742 - T_1885[15] <= T_1745 - T_1885[16] <= T_1748 - T_1885[17] <= T_1751 - T_1885[18] <= T_1754 - T_1885[19] <= T_1757 - T_1885[20] <= T_1760 - T_1885[21] <= T_1763 - T_1885[22] <= T_1766 - T_1885[23] <= T_1769 - T_1885[24] <= T_1772 - T_1885[25] <= T_1775 - T_1885[26] <= T_1778 - T_1885[27] <= T_1781 - T_1885[28] <= T_1784 - T_1885[29] <= T_1787 - T_1885[30] <= T_1790 - T_1885[31] <= T_1793 - T_1885[32] <= T_1796 - T_1885[33] <= T_1799 - T_1885[34] <= T_1802 - T_1885[35] <= T_1805 - T_1885[36] <= T_1808 - T_1885[37] <= T_1811 - T_1885[38] <= T_1814 - T_1885[39] <= T_1817 - T_1885[40] <= T_1820 - T_1885[41] <= T_1823 - T_1885[42] <= T_1826 - T_1885[43] <= T_1829 - T_1885[44] <= T_1832 - T_1885[45] <= T_1835 - T_1885[46] <= T_1838 - T_1885[47] <= T_1841 - T_1885[48] <= T_1844 - T_1885[49] <= T_1847 - T_1885[50] <= T_1850 - T_1885[51] <= T_1853 - T_1885[52] <= T_1856 - T_1885[53] <= T_1859 - T_1885[54] <= T_1862 - T_1885[55] <= T_1865 - T_1885[56] <= T_1868 - T_1885[57] <= T_1871 - T_1885[58] <= T_1874 - T_1885[59] <= T_1877 - T_1885[60] <= T_1880 - T_1885[61] <= T_1883 - node T_1949 = cat(T_1885[60], T_1885[59]) - node T_1950 = cat(T_1885[61], T_1949) - node T_1951 = cat(T_1885[58], T_1885[57]) - node T_1952 = cat(T_1885[56], T_1885[55]) - node T_1953 = cat(T_1951, T_1952) - node T_1954 = cat(T_1950, T_1953) - node T_1955 = cat(T_1885[54], T_1885[53]) - node T_1956 = cat(T_1885[52], T_1885[51]) - node T_1957 = cat(T_1955, T_1956) - node T_1958 = cat(T_1885[50], T_1885[49]) - node T_1959 = cat(T_1885[48], T_1885[47]) - node T_1960 = cat(T_1958, T_1959) - node T_1961 = cat(T_1957, T_1960) - node T_1962 = cat(T_1954, T_1961) - node T_1963 = cat(T_1885[46], T_1885[45]) - node T_1964 = cat(T_1885[44], T_1885[43]) - node T_1965 = cat(T_1963, T_1964) - node T_1966 = cat(T_1885[42], T_1885[41]) - node T_1967 = cat(T_1885[40], T_1885[39]) - node T_1968 = cat(T_1966, T_1967) - node T_1969 = cat(T_1965, T_1968) - node T_1970 = cat(T_1885[38], T_1885[37]) - node T_1971 = cat(T_1885[36], T_1885[35]) - node T_1972 = cat(T_1970, T_1971) - node T_1973 = cat(T_1885[34], T_1885[33]) - node T_1974 = cat(T_1885[32], T_1885[31]) - node T_1975 = cat(T_1973, T_1974) - node T_1976 = cat(T_1972, T_1975) - node T_1977 = cat(T_1969, T_1976) - node T_1978 = cat(T_1962, T_1977) - node T_1979 = cat(T_1885[29], T_1885[28]) - node T_1980 = cat(T_1885[30], T_1979) - node T_1981 = cat(T_1885[27], T_1885[26]) - node T_1982 = cat(T_1885[25], T_1885[24]) - node T_1983 = cat(T_1981, T_1982) - node T_1984 = cat(T_1980, T_1983) - node T_1985 = cat(T_1885[23], T_1885[22]) - node T_1986 = cat(T_1885[21], T_1885[20]) - node T_1987 = cat(T_1985, T_1986) - node T_1988 = cat(T_1885[19], T_1885[18]) - node T_1989 = cat(T_1885[17], T_1885[16]) - node T_1990 = cat(T_1988, T_1989) - node T_1991 = cat(T_1987, T_1990) - node T_1992 = cat(T_1984, T_1991) - node T_1993 = cat(T_1885[15], T_1885[14]) - node T_1994 = cat(T_1885[13], T_1885[12]) - node T_1995 = cat(T_1993, T_1994) - node T_1996 = cat(T_1885[11], T_1885[10]) - node T_1997 = cat(T_1885[9], T_1885[8]) - node T_1998 = cat(T_1996, T_1997) - node T_1999 = cat(T_1995, T_1998) - node T_2000 = cat(T_1885[7], T_1885[6]) - node T_2001 = cat(T_1885[5], T_1885[4]) - node T_2002 = cat(T_2000, T_2001) - node T_2003 = cat(T_1885[3], T_1885[2]) - node T_2004 = cat(T_1885[1], T_1885[0]) - node T_2005 = cat(T_2003, T_2004) - node T_2006 = cat(T_2002, T_2005) - node T_2007 = cat(T_1999, T_2006) - node T_2008 = cat(T_1992, T_2007) - node T_2009 = cat(T_1978, T_2008) - node T_2010 = and(T_593, pageHit) - node T_2011 = and(T_598, pageHit) - node T_2012 = and(T_603, pageHit) - node T_2013 = and(T_608, pageHit) - node T_2014 = and(T_613, pageHit) - node T_2015 = and(T_618, pageHit) - node T_2016 = and(T_623, pageHit) - node T_2017 = and(T_628, pageHit) - node T_2018 = and(T_633, pageHit) - node T_2019 = and(T_638, pageHit) - node T_2020 = and(T_643, pageHit) - node T_2021 = and(T_648, pageHit) - node T_2022 = and(T_653, pageHit) - node T_2023 = and(T_658, pageHit) - node T_2024 = and(T_663, pageHit) - node T_2025 = and(T_668, pageHit) - node T_2026 = and(T_673, pageHit) - node T_2027 = and(T_678, pageHit) - node T_2028 = and(T_683, pageHit) - node T_2029 = and(T_688, pageHit) - node T_2030 = and(T_693, pageHit) - node T_2031 = and(T_698, pageHit) - node T_2032 = and(T_703, pageHit) - node T_2033 = and(T_708, pageHit) - node T_2034 = and(T_713, pageHit) - node T_2035 = and(T_718, pageHit) - node T_2036 = and(T_723, pageHit) - node T_2037 = and(T_728, pageHit) - node T_2038 = and(T_733, pageHit) - node T_2039 = and(T_738, pageHit) - node T_2040 = and(T_743, pageHit) - node T_2041 = and(T_748, pageHit) - node T_2042 = and(T_753, pageHit) - node T_2043 = and(T_758, pageHit) - node T_2044 = and(T_763, pageHit) - node T_2045 = and(T_768, pageHit) - node T_2046 = and(T_773, pageHit) - node T_2047 = and(T_778, pageHit) - node T_2048 = and(T_783, pageHit) - node T_2049 = and(T_788, pageHit) - node T_2050 = and(T_793, pageHit) - node T_2051 = and(T_798, pageHit) - node T_2052 = and(T_803, pageHit) - node T_2053 = and(T_808, pageHit) - node T_2054 = and(T_813, pageHit) - node T_2055 = and(T_818, pageHit) - node T_2056 = and(T_823, pageHit) - node T_2057 = and(T_828, pageHit) - node T_2058 = and(T_833, pageHit) - node T_2059 = and(T_838, pageHit) - node T_2060 = and(T_843, pageHit) - node T_2061 = and(T_848, pageHit) - node T_2062 = and(T_853, pageHit) - node T_2063 = and(T_858, pageHit) - node T_2064 = and(T_863, pageHit) - node T_2065 = and(T_868, pageHit) - node T_2066 = and(T_873, pageHit) - node T_2067 = and(T_878, pageHit) - node T_2068 = and(T_883, pageHit) - node T_2069 = and(T_888, pageHit) - node T_2070 = and(T_893, pageHit) - node T_2071 = and(T_898, pageHit) - node T_2073 = neq(T_2010, UInt<1>("h0")) - node T_2075 = neq(T_2011, UInt<1>("h0")) - node T_2077 = neq(T_2012, UInt<1>("h0")) - node T_2079 = neq(T_2013, UInt<1>("h0")) - node T_2081 = neq(T_2014, UInt<1>("h0")) - node T_2083 = neq(T_2015, UInt<1>("h0")) - node T_2085 = neq(T_2016, UInt<1>("h0")) - node T_2087 = neq(T_2017, UInt<1>("h0")) - node T_2089 = neq(T_2018, UInt<1>("h0")) - node T_2091 = neq(T_2019, UInt<1>("h0")) - node T_2093 = neq(T_2020, UInt<1>("h0")) - node T_2095 = neq(T_2021, UInt<1>("h0")) - node T_2097 = neq(T_2022, UInt<1>("h0")) - node T_2099 = neq(T_2023, UInt<1>("h0")) - node T_2101 = neq(T_2024, UInt<1>("h0")) - node T_2103 = neq(T_2025, UInt<1>("h0")) - node T_2105 = neq(T_2026, UInt<1>("h0")) - node T_2107 = neq(T_2027, UInt<1>("h0")) - node T_2109 = neq(T_2028, UInt<1>("h0")) - node T_2111 = neq(T_2029, UInt<1>("h0")) - node T_2113 = neq(T_2030, UInt<1>("h0")) - node T_2115 = neq(T_2031, UInt<1>("h0")) - node T_2117 = neq(T_2032, UInt<1>("h0")) - node T_2119 = neq(T_2033, UInt<1>("h0")) - node T_2121 = neq(T_2034, UInt<1>("h0")) - node T_2123 = neq(T_2035, UInt<1>("h0")) - node T_2125 = neq(T_2036, UInt<1>("h0")) - node T_2127 = neq(T_2037, UInt<1>("h0")) - node T_2129 = neq(T_2038, UInt<1>("h0")) - node T_2131 = neq(T_2039, UInt<1>("h0")) - node T_2133 = neq(T_2040, UInt<1>("h0")) - node T_2135 = neq(T_2041, UInt<1>("h0")) - node T_2137 = neq(T_2042, UInt<1>("h0")) - node T_2139 = neq(T_2043, UInt<1>("h0")) - node T_2141 = neq(T_2044, UInt<1>("h0")) - node T_2143 = neq(T_2045, UInt<1>("h0")) - node T_2145 = neq(T_2046, UInt<1>("h0")) - node T_2147 = neq(T_2047, UInt<1>("h0")) - node T_2149 = neq(T_2048, UInt<1>("h0")) - node T_2151 = neq(T_2049, UInt<1>("h0")) - node T_2153 = neq(T_2050, UInt<1>("h0")) - node T_2155 = neq(T_2051, UInt<1>("h0")) - node T_2157 = neq(T_2052, UInt<1>("h0")) - node T_2159 = neq(T_2053, UInt<1>("h0")) - node T_2161 = neq(T_2054, UInt<1>("h0")) - node T_2163 = neq(T_2055, UInt<1>("h0")) - node T_2165 = neq(T_2056, UInt<1>("h0")) - node T_2167 = neq(T_2057, UInt<1>("h0")) - node T_2169 = neq(T_2058, UInt<1>("h0")) - node T_2171 = neq(T_2059, UInt<1>("h0")) - node T_2173 = neq(T_2060, UInt<1>("h0")) - node T_2175 = neq(T_2061, UInt<1>("h0")) - node T_2177 = neq(T_2062, UInt<1>("h0")) - node T_2179 = neq(T_2063, UInt<1>("h0")) - node T_2181 = neq(T_2064, UInt<1>("h0")) - node T_2183 = neq(T_2065, UInt<1>("h0")) - node T_2185 = neq(T_2066, UInt<1>("h0")) - node T_2187 = neq(T_2067, UInt<1>("h0")) - node T_2189 = neq(T_2068, UInt<1>("h0")) - node T_2191 = neq(T_2069, UInt<1>("h0")) - node T_2193 = neq(T_2070, UInt<1>("h0")) - node T_2195 = neq(T_2071, UInt<1>("h0")) - wire T_2197 : UInt<1>[62] - T_2197[0] <= T_2073 - T_2197[1] <= T_2075 - T_2197[2] <= T_2077 - T_2197[3] <= T_2079 - T_2197[4] <= T_2081 - T_2197[5] <= T_2083 - T_2197[6] <= T_2085 - T_2197[7] <= T_2087 - T_2197[8] <= T_2089 - T_2197[9] <= T_2091 - T_2197[10] <= T_2093 - T_2197[11] <= T_2095 - T_2197[12] <= T_2097 - T_2197[13] <= T_2099 - T_2197[14] <= T_2101 - T_2197[15] <= T_2103 - T_2197[16] <= T_2105 - T_2197[17] <= T_2107 - T_2197[18] <= T_2109 - T_2197[19] <= T_2111 - T_2197[20] <= T_2113 - T_2197[21] <= T_2115 - T_2197[22] <= T_2117 - T_2197[23] <= T_2119 - T_2197[24] <= T_2121 - T_2197[25] <= T_2123 - T_2197[26] <= T_2125 - T_2197[27] <= T_2127 - T_2197[28] <= T_2129 - T_2197[29] <= T_2131 - T_2197[30] <= T_2133 - T_2197[31] <= T_2135 - T_2197[32] <= T_2137 - T_2197[33] <= T_2139 - T_2197[34] <= T_2141 - T_2197[35] <= T_2143 - T_2197[36] <= T_2145 - T_2197[37] <= T_2147 - T_2197[38] <= T_2149 - T_2197[39] <= T_2151 - T_2197[40] <= T_2153 - T_2197[41] <= T_2155 - T_2197[42] <= T_2157 - T_2197[43] <= T_2159 - T_2197[44] <= T_2161 - T_2197[45] <= T_2163 - T_2197[46] <= T_2165 - T_2197[47] <= T_2167 - T_2197[48] <= T_2169 - T_2197[49] <= T_2171 - T_2197[50] <= T_2173 - T_2197[51] <= T_2175 - T_2197[52] <= T_2177 - T_2197[53] <= T_2179 - T_2197[54] <= T_2181 - T_2197[55] <= T_2183 - T_2197[56] <= T_2185 - T_2197[57] <= T_2187 - T_2197[58] <= T_2189 - T_2197[59] <= T_2191 - T_2197[60] <= T_2193 - T_2197[61] <= T_2195 - node T_2261 = cat(T_2197[60], T_2197[59]) - node T_2262 = cat(T_2197[61], T_2261) - node T_2263 = cat(T_2197[58], T_2197[57]) - node T_2264 = cat(T_2197[56], T_2197[55]) - node T_2265 = cat(T_2263, T_2264) - node T_2266 = cat(T_2262, T_2265) - node T_2267 = cat(T_2197[54], T_2197[53]) - node T_2268 = cat(T_2197[52], T_2197[51]) - node T_2269 = cat(T_2267, T_2268) - node T_2270 = cat(T_2197[50], T_2197[49]) - node T_2271 = cat(T_2197[48], T_2197[47]) - node T_2272 = cat(T_2270, T_2271) - node T_2273 = cat(T_2269, T_2272) - node T_2274 = cat(T_2266, T_2273) - node T_2275 = cat(T_2197[46], T_2197[45]) - node T_2276 = cat(T_2197[44], T_2197[43]) - node T_2277 = cat(T_2275, T_2276) - node T_2278 = cat(T_2197[42], T_2197[41]) - node T_2279 = cat(T_2197[40], T_2197[39]) - node T_2280 = cat(T_2278, T_2279) - node T_2281 = cat(T_2277, T_2280) - node T_2282 = cat(T_2197[38], T_2197[37]) - node T_2283 = cat(T_2197[36], T_2197[35]) - node T_2284 = cat(T_2282, T_2283) - node T_2285 = cat(T_2197[34], T_2197[33]) - node T_2286 = cat(T_2197[32], T_2197[31]) - node T_2287 = cat(T_2285, T_2286) - node T_2288 = cat(T_2284, T_2287) - node T_2289 = cat(T_2281, T_2288) - node T_2290 = cat(T_2274, T_2289) - node T_2291 = cat(T_2197[29], T_2197[28]) - node T_2292 = cat(T_2197[30], T_2291) - node T_2293 = cat(T_2197[27], T_2197[26]) - node T_2294 = cat(T_2197[25], T_2197[24]) - node T_2295 = cat(T_2293, T_2294) - node T_2296 = cat(T_2292, T_2295) - node T_2297 = cat(T_2197[23], T_2197[22]) - node T_2298 = cat(T_2197[21], T_2197[20]) - node T_2299 = cat(T_2297, T_2298) - node T_2300 = cat(T_2197[19], T_2197[18]) - node T_2301 = cat(T_2197[17], T_2197[16]) - node T_2302 = cat(T_2300, T_2301) - node T_2303 = cat(T_2299, T_2302) - node T_2304 = cat(T_2296, T_2303) - node T_2305 = cat(T_2197[15], T_2197[14]) - node T_2306 = cat(T_2197[13], T_2197[12]) - node T_2307 = cat(T_2305, T_2306) - node T_2308 = cat(T_2197[11], T_2197[10]) - node T_2309 = cat(T_2197[9], T_2197[8]) - node T_2310 = cat(T_2308, T_2309) - node T_2311 = cat(T_2307, T_2310) - node T_2312 = cat(T_2197[7], T_2197[6]) - node T_2313 = cat(T_2197[5], T_2197[4]) - node T_2314 = cat(T_2312, T_2313) - node T_2315 = cat(T_2197[3], T_2197[2]) - node T_2316 = cat(T_2197[1], T_2197[0]) - node T_2317 = cat(T_2315, T_2316) - node T_2318 = cat(T_2314, T_2317) - node T_2319 = cat(T_2311, T_2318) - node T_2320 = cat(T_2304, T_2319) - node T_2321 = cat(T_2290, T_2320) - node T_2322 = and(idxValid, T_2009) - node hits = and(T_2322, T_2321) - node T_2324 = shr(r_btb_update.bits.pc, 12) - pages.T_2326.addr <= UInt<1>("h0") - pages.T_2326.en <= UInt<1>("h1") - node T_2327 = eq(pages.T_2326.data, T_2324) - pages.T_2329.addr <= UInt<1>("h1") - pages.T_2329.en <= UInt<1>("h1") - node T_2330 = eq(pages.T_2329.data, T_2324) - pages.T_2332.addr <= UInt<2>("h2") - pages.T_2332.en <= UInt<1>("h1") - node T_2333 = eq(pages.T_2332.data, T_2324) - pages.T_2335.addr <= UInt<2>("h3") - pages.T_2335.en <= UInt<1>("h1") - node T_2336 = eq(pages.T_2335.data, T_2324) - pages.T_2338.addr <= UInt<3>("h4") - pages.T_2338.en <= UInt<1>("h1") - node T_2339 = eq(pages.T_2338.data, T_2324) - pages.T_2341.addr <= UInt<3>("h5") - pages.T_2341.en <= UInt<1>("h1") - node T_2342 = eq(pages.T_2341.data, T_2324) - wire T_2344 : UInt<1>[6] - T_2344[0] <= T_2327 - T_2344[1] <= T_2330 - T_2344[2] <= T_2333 - T_2344[3] <= T_2336 - T_2344[4] <= T_2339 - T_2344[5] <= T_2342 - node T_2352 = cat(T_2344[4], T_2344[3]) - node T_2353 = cat(T_2344[5], T_2352) - node T_2354 = cat(T_2344[1], T_2344[0]) - node T_2355 = cat(T_2344[2], T_2354) - node T_2356 = cat(T_2353, T_2355) - node updatePageHit = and(T_2356, pageValid) - node T_2358 = bits(r_btb_update.bits.pc, 11, 0) - idxs.T_2360.addr <= UInt<1>("h0") - idxs.T_2360.en <= UInt<1>("h1") - node T_2361 = eq(idxs.T_2360.data, T_2358) - idxs.T_2363.addr <= UInt<1>("h1") - idxs.T_2363.en <= UInt<1>("h1") - node T_2364 = eq(idxs.T_2363.data, T_2358) - idxs.T_2366.addr <= UInt<2>("h2") - idxs.T_2366.en <= UInt<1>("h1") - node T_2367 = eq(idxs.T_2366.data, T_2358) - idxs.T_2369.addr <= UInt<2>("h3") - idxs.T_2369.en <= UInt<1>("h1") - node T_2370 = eq(idxs.T_2369.data, T_2358) - idxs.T_2372.addr <= UInt<3>("h4") - idxs.T_2372.en <= UInt<1>("h1") - node T_2373 = eq(idxs.T_2372.data, T_2358) - idxs.T_2375.addr <= UInt<3>("h5") - idxs.T_2375.en <= UInt<1>("h1") - node T_2376 = eq(idxs.T_2375.data, T_2358) - idxs.T_2378.addr <= UInt<3>("h6") - idxs.T_2378.en <= UInt<1>("h1") - node T_2379 = eq(idxs.T_2378.data, T_2358) - idxs.T_2381.addr <= UInt<3>("h7") - idxs.T_2381.en <= UInt<1>("h1") - node T_2382 = eq(idxs.T_2381.data, T_2358) - idxs.T_2384.addr <= UInt<4>("h8") - idxs.T_2384.en <= UInt<1>("h1") - node T_2385 = eq(idxs.T_2384.data, T_2358) - idxs.T_2387.addr <= UInt<4>("h9") - idxs.T_2387.en <= UInt<1>("h1") - node T_2388 = eq(idxs.T_2387.data, T_2358) - idxs.T_2390.addr <= UInt<4>("ha") - idxs.T_2390.en <= UInt<1>("h1") - node T_2391 = eq(idxs.T_2390.data, T_2358) - idxs.T_2393.addr <= UInt<4>("hb") - idxs.T_2393.en <= UInt<1>("h1") - node T_2394 = eq(idxs.T_2393.data, T_2358) - idxs.T_2396.addr <= UInt<4>("hc") - idxs.T_2396.en <= UInt<1>("h1") - node T_2397 = eq(idxs.T_2396.data, T_2358) - idxs.T_2399.addr <= UInt<4>("hd") - idxs.T_2399.en <= UInt<1>("h1") - node T_2400 = eq(idxs.T_2399.data, T_2358) - idxs.T_2402.addr <= UInt<4>("he") - idxs.T_2402.en <= UInt<1>("h1") - node T_2403 = eq(idxs.T_2402.data, T_2358) - idxs.T_2405.addr <= UInt<4>("hf") - idxs.T_2405.en <= UInt<1>("h1") - node T_2406 = eq(idxs.T_2405.data, T_2358) - idxs.T_2408.addr <= UInt<5>("h10") - idxs.T_2408.en <= UInt<1>("h1") - node T_2409 = eq(idxs.T_2408.data, T_2358) - idxs.T_2411.addr <= UInt<5>("h11") - idxs.T_2411.en <= UInt<1>("h1") - node T_2412 = eq(idxs.T_2411.data, T_2358) - idxs.T_2414.addr <= UInt<5>("h12") - idxs.T_2414.en <= UInt<1>("h1") - node T_2415 = eq(idxs.T_2414.data, T_2358) - idxs.T_2417.addr <= UInt<5>("h13") - idxs.T_2417.en <= UInt<1>("h1") - node T_2418 = eq(idxs.T_2417.data, T_2358) - idxs.T_2420.addr <= UInt<5>("h14") - idxs.T_2420.en <= UInt<1>("h1") - node T_2421 = eq(idxs.T_2420.data, T_2358) - idxs.T_2423.addr <= UInt<5>("h15") - idxs.T_2423.en <= UInt<1>("h1") - node T_2424 = eq(idxs.T_2423.data, T_2358) - idxs.T_2426.addr <= UInt<5>("h16") - idxs.T_2426.en <= UInt<1>("h1") - node T_2427 = eq(idxs.T_2426.data, T_2358) - idxs.T_2429.addr <= UInt<5>("h17") - idxs.T_2429.en <= UInt<1>("h1") - node T_2430 = eq(idxs.T_2429.data, T_2358) - idxs.T_2432.addr <= UInt<5>("h18") - idxs.T_2432.en <= UInt<1>("h1") - node T_2433 = eq(idxs.T_2432.data, T_2358) - idxs.T_2435.addr <= UInt<5>("h19") - idxs.T_2435.en <= UInt<1>("h1") - node T_2436 = eq(idxs.T_2435.data, T_2358) - idxs.T_2438.addr <= UInt<5>("h1a") - idxs.T_2438.en <= UInt<1>("h1") - node T_2439 = eq(idxs.T_2438.data, T_2358) - idxs.T_2441.addr <= UInt<5>("h1b") - idxs.T_2441.en <= UInt<1>("h1") - node T_2442 = eq(idxs.T_2441.data, T_2358) - idxs.T_2444.addr <= UInt<5>("h1c") - idxs.T_2444.en <= UInt<1>("h1") - node T_2445 = eq(idxs.T_2444.data, T_2358) - idxs.T_2447.addr <= UInt<5>("h1d") - idxs.T_2447.en <= UInt<1>("h1") - node T_2448 = eq(idxs.T_2447.data, T_2358) - idxs.T_2450.addr <= UInt<5>("h1e") - idxs.T_2450.en <= UInt<1>("h1") - node T_2451 = eq(idxs.T_2450.data, T_2358) - idxs.T_2453.addr <= UInt<5>("h1f") - idxs.T_2453.en <= UInt<1>("h1") - node T_2454 = eq(idxs.T_2453.data, T_2358) - idxs.T_2456.addr <= UInt<6>("h20") - idxs.T_2456.en <= UInt<1>("h1") - node T_2457 = eq(idxs.T_2456.data, T_2358) - idxs.T_2459.addr <= UInt<6>("h21") - idxs.T_2459.en <= UInt<1>("h1") - node T_2460 = eq(idxs.T_2459.data, T_2358) - idxs.T_2462.addr <= UInt<6>("h22") - idxs.T_2462.en <= UInt<1>("h1") - node T_2463 = eq(idxs.T_2462.data, T_2358) - idxs.T_2465.addr <= UInt<6>("h23") - idxs.T_2465.en <= UInt<1>("h1") - node T_2466 = eq(idxs.T_2465.data, T_2358) - idxs.T_2468.addr <= UInt<6>("h24") - idxs.T_2468.en <= UInt<1>("h1") - node T_2469 = eq(idxs.T_2468.data, T_2358) - idxs.T_2471.addr <= UInt<6>("h25") - idxs.T_2471.en <= UInt<1>("h1") - node T_2472 = eq(idxs.T_2471.data, T_2358) - idxs.T_2474.addr <= UInt<6>("h26") - idxs.T_2474.en <= UInt<1>("h1") - node T_2475 = eq(idxs.T_2474.data, T_2358) - idxs.T_2477.addr <= UInt<6>("h27") - idxs.T_2477.en <= UInt<1>("h1") - node T_2478 = eq(idxs.T_2477.data, T_2358) - idxs.T_2480.addr <= UInt<6>("h28") - idxs.T_2480.en <= UInt<1>("h1") - node T_2481 = eq(idxs.T_2480.data, T_2358) - idxs.T_2483.addr <= UInt<6>("h29") - idxs.T_2483.en <= UInt<1>("h1") - node T_2484 = eq(idxs.T_2483.data, T_2358) - idxs.T_2486.addr <= UInt<6>("h2a") - idxs.T_2486.en <= UInt<1>("h1") - node T_2487 = eq(idxs.T_2486.data, T_2358) - idxs.T_2489.addr <= UInt<6>("h2b") - idxs.T_2489.en <= UInt<1>("h1") - node T_2490 = eq(idxs.T_2489.data, T_2358) - idxs.T_2492.addr <= UInt<6>("h2c") - idxs.T_2492.en <= UInt<1>("h1") - node T_2493 = eq(idxs.T_2492.data, T_2358) - idxs.T_2495.addr <= UInt<6>("h2d") - idxs.T_2495.en <= UInt<1>("h1") - node T_2496 = eq(idxs.T_2495.data, T_2358) - idxs.T_2498.addr <= UInt<6>("h2e") - idxs.T_2498.en <= UInt<1>("h1") - node T_2499 = eq(idxs.T_2498.data, T_2358) - idxs.T_2501.addr <= UInt<6>("h2f") - idxs.T_2501.en <= UInt<1>("h1") - node T_2502 = eq(idxs.T_2501.data, T_2358) - idxs.T_2504.addr <= UInt<6>("h30") - idxs.T_2504.en <= UInt<1>("h1") - node T_2505 = eq(idxs.T_2504.data, T_2358) - idxs.T_2507.addr <= UInt<6>("h31") - idxs.T_2507.en <= UInt<1>("h1") - node T_2508 = eq(idxs.T_2507.data, T_2358) - idxs.T_2510.addr <= UInt<6>("h32") - idxs.T_2510.en <= UInt<1>("h1") - node T_2511 = eq(idxs.T_2510.data, T_2358) - idxs.T_2513.addr <= UInt<6>("h33") - idxs.T_2513.en <= UInt<1>("h1") - node T_2514 = eq(idxs.T_2513.data, T_2358) - idxs.T_2516.addr <= UInt<6>("h34") - idxs.T_2516.en <= UInt<1>("h1") - node T_2517 = eq(idxs.T_2516.data, T_2358) - idxs.T_2519.addr <= UInt<6>("h35") - idxs.T_2519.en <= UInt<1>("h1") - node T_2520 = eq(idxs.T_2519.data, T_2358) - idxs.T_2522.addr <= UInt<6>("h36") - idxs.T_2522.en <= UInt<1>("h1") - node T_2523 = eq(idxs.T_2522.data, T_2358) - idxs.T_2525.addr <= UInt<6>("h37") - idxs.T_2525.en <= UInt<1>("h1") - node T_2526 = eq(idxs.T_2525.data, T_2358) - idxs.T_2528.addr <= UInt<6>("h38") - idxs.T_2528.en <= UInt<1>("h1") - node T_2529 = eq(idxs.T_2528.data, T_2358) - idxs.T_2531.addr <= UInt<6>("h39") - idxs.T_2531.en <= UInt<1>("h1") - node T_2532 = eq(idxs.T_2531.data, T_2358) - idxs.T_2534.addr <= UInt<6>("h3a") - idxs.T_2534.en <= UInt<1>("h1") - node T_2535 = eq(idxs.T_2534.data, T_2358) - idxs.T_2537.addr <= UInt<6>("h3b") - idxs.T_2537.en <= UInt<1>("h1") - node T_2538 = eq(idxs.T_2537.data, T_2358) - idxs.T_2540.addr <= UInt<6>("h3c") - idxs.T_2540.en <= UInt<1>("h1") - node T_2541 = eq(idxs.T_2540.data, T_2358) - idxs.T_2543.addr <= UInt<6>("h3d") - idxs.T_2543.en <= UInt<1>("h1") - node T_2544 = eq(idxs.T_2543.data, T_2358) - wire T_2546 : UInt<1>[62] - T_2546[0] <= T_2361 - T_2546[1] <= T_2364 - T_2546[2] <= T_2367 - T_2546[3] <= T_2370 - T_2546[4] <= T_2373 - T_2546[5] <= T_2376 - T_2546[6] <= T_2379 - T_2546[7] <= T_2382 - T_2546[8] <= T_2385 - T_2546[9] <= T_2388 - T_2546[10] <= T_2391 - T_2546[11] <= T_2394 - T_2546[12] <= T_2397 - T_2546[13] <= T_2400 - T_2546[14] <= T_2403 - T_2546[15] <= T_2406 - T_2546[16] <= T_2409 - T_2546[17] <= T_2412 - T_2546[18] <= T_2415 - T_2546[19] <= T_2418 - T_2546[20] <= T_2421 - T_2546[21] <= T_2424 - T_2546[22] <= T_2427 - T_2546[23] <= T_2430 - T_2546[24] <= T_2433 - T_2546[25] <= T_2436 - T_2546[26] <= T_2439 - T_2546[27] <= T_2442 - T_2546[28] <= T_2445 - T_2546[29] <= T_2448 - T_2546[30] <= T_2451 - T_2546[31] <= T_2454 - T_2546[32] <= T_2457 - T_2546[33] <= T_2460 - T_2546[34] <= T_2463 - T_2546[35] <= T_2466 - T_2546[36] <= T_2469 - T_2546[37] <= T_2472 - T_2546[38] <= T_2475 - T_2546[39] <= T_2478 - T_2546[40] <= T_2481 - T_2546[41] <= T_2484 - T_2546[42] <= T_2487 - T_2546[43] <= T_2490 - T_2546[44] <= T_2493 - T_2546[45] <= T_2496 - T_2546[46] <= T_2499 - T_2546[47] <= T_2502 - T_2546[48] <= T_2505 - T_2546[49] <= T_2508 - T_2546[50] <= T_2511 - T_2546[51] <= T_2514 - T_2546[52] <= T_2517 - T_2546[53] <= T_2520 - T_2546[54] <= T_2523 - T_2546[55] <= T_2526 - T_2546[56] <= T_2529 - T_2546[57] <= T_2532 - T_2546[58] <= T_2535 - T_2546[59] <= T_2538 - T_2546[60] <= T_2541 - T_2546[61] <= T_2544 - node T_2610 = cat(T_2546[60], T_2546[59]) - node T_2611 = cat(T_2546[61], T_2610) - node T_2612 = cat(T_2546[58], T_2546[57]) - node T_2613 = cat(T_2546[56], T_2546[55]) - node T_2614 = cat(T_2612, T_2613) - node T_2615 = cat(T_2611, T_2614) - node T_2616 = cat(T_2546[54], T_2546[53]) - node T_2617 = cat(T_2546[52], T_2546[51]) - node T_2618 = cat(T_2616, T_2617) - node T_2619 = cat(T_2546[50], T_2546[49]) - node T_2620 = cat(T_2546[48], T_2546[47]) - node T_2621 = cat(T_2619, T_2620) - node T_2622 = cat(T_2618, T_2621) - node T_2623 = cat(T_2615, T_2622) - node T_2624 = cat(T_2546[46], T_2546[45]) - node T_2625 = cat(T_2546[44], T_2546[43]) - node T_2626 = cat(T_2624, T_2625) - node T_2627 = cat(T_2546[42], T_2546[41]) - node T_2628 = cat(T_2546[40], T_2546[39]) - node T_2629 = cat(T_2627, T_2628) - node T_2630 = cat(T_2626, T_2629) - node T_2631 = cat(T_2546[38], T_2546[37]) - node T_2632 = cat(T_2546[36], T_2546[35]) - node T_2633 = cat(T_2631, T_2632) - node T_2634 = cat(T_2546[34], T_2546[33]) - node T_2635 = cat(T_2546[32], T_2546[31]) - node T_2636 = cat(T_2634, T_2635) - node T_2637 = cat(T_2633, T_2636) - node T_2638 = cat(T_2630, T_2637) - node T_2639 = cat(T_2623, T_2638) - node T_2640 = cat(T_2546[29], T_2546[28]) - node T_2641 = cat(T_2546[30], T_2640) - node T_2642 = cat(T_2546[27], T_2546[26]) - node T_2643 = cat(T_2546[25], T_2546[24]) - node T_2644 = cat(T_2642, T_2643) - node T_2645 = cat(T_2641, T_2644) - node T_2646 = cat(T_2546[23], T_2546[22]) - node T_2647 = cat(T_2546[21], T_2546[20]) - node T_2648 = cat(T_2646, T_2647) - node T_2649 = cat(T_2546[19], T_2546[18]) - node T_2650 = cat(T_2546[17], T_2546[16]) - node T_2651 = cat(T_2649, T_2650) - node T_2652 = cat(T_2648, T_2651) - node T_2653 = cat(T_2645, T_2652) - node T_2654 = cat(T_2546[15], T_2546[14]) - node T_2655 = cat(T_2546[13], T_2546[12]) - node T_2656 = cat(T_2654, T_2655) - node T_2657 = cat(T_2546[11], T_2546[10]) - node T_2658 = cat(T_2546[9], T_2546[8]) - node T_2659 = cat(T_2657, T_2658) - node T_2660 = cat(T_2656, T_2659) - node T_2661 = cat(T_2546[7], T_2546[6]) - node T_2662 = cat(T_2546[5], T_2546[4]) - node T_2663 = cat(T_2661, T_2662) - node T_2664 = cat(T_2546[3], T_2546[2]) - node T_2665 = cat(T_2546[1], T_2546[0]) - node T_2666 = cat(T_2664, T_2665) - node T_2667 = cat(T_2663, T_2666) - node T_2668 = cat(T_2660, T_2667) - node T_2669 = cat(T_2653, T_2668) - node T_2670 = cat(T_2639, T_2669) - node T_2671 = and(T_593, updatePageHit) - node T_2672 = and(T_598, updatePageHit) - node T_2673 = and(T_603, updatePageHit) - node T_2674 = and(T_608, updatePageHit) - node T_2675 = and(T_613, updatePageHit) - node T_2676 = and(T_618, updatePageHit) - node T_2677 = and(T_623, updatePageHit) - node T_2678 = and(T_628, updatePageHit) - node T_2679 = and(T_633, updatePageHit) - node T_2680 = and(T_638, updatePageHit) - node T_2681 = and(T_643, updatePageHit) - node T_2682 = and(T_648, updatePageHit) - node T_2683 = and(T_653, updatePageHit) - node T_2684 = and(T_658, updatePageHit) - node T_2685 = and(T_663, updatePageHit) - node T_2686 = and(T_668, updatePageHit) - node T_2687 = and(T_673, updatePageHit) - node T_2688 = and(T_678, updatePageHit) - node T_2689 = and(T_683, updatePageHit) - node T_2690 = and(T_688, updatePageHit) - node T_2691 = and(T_693, updatePageHit) - node T_2692 = and(T_698, updatePageHit) - node T_2693 = and(T_703, updatePageHit) - node T_2694 = and(T_708, updatePageHit) - node T_2695 = and(T_713, updatePageHit) - node T_2696 = and(T_718, updatePageHit) - node T_2697 = and(T_723, updatePageHit) - node T_2698 = and(T_728, updatePageHit) - node T_2699 = and(T_733, updatePageHit) - node T_2700 = and(T_738, updatePageHit) - node T_2701 = and(T_743, updatePageHit) - node T_2702 = and(T_748, updatePageHit) - node T_2703 = and(T_753, updatePageHit) - node T_2704 = and(T_758, updatePageHit) - node T_2705 = and(T_763, updatePageHit) - node T_2706 = and(T_768, updatePageHit) - node T_2707 = and(T_773, updatePageHit) - node T_2708 = and(T_778, updatePageHit) - node T_2709 = and(T_783, updatePageHit) - node T_2710 = and(T_788, updatePageHit) - node T_2711 = and(T_793, updatePageHit) - node T_2712 = and(T_798, updatePageHit) - node T_2713 = and(T_803, updatePageHit) - node T_2714 = and(T_808, updatePageHit) - node T_2715 = and(T_813, updatePageHit) - node T_2716 = and(T_818, updatePageHit) - node T_2717 = and(T_823, updatePageHit) - node T_2718 = and(T_828, updatePageHit) - node T_2719 = and(T_833, updatePageHit) - node T_2720 = and(T_838, updatePageHit) - node T_2721 = and(T_843, updatePageHit) - node T_2722 = and(T_848, updatePageHit) - node T_2723 = and(T_853, updatePageHit) - node T_2724 = and(T_858, updatePageHit) - node T_2725 = and(T_863, updatePageHit) - node T_2726 = and(T_868, updatePageHit) - node T_2727 = and(T_873, updatePageHit) - node T_2728 = and(T_878, updatePageHit) - node T_2729 = and(T_883, updatePageHit) - node T_2730 = and(T_888, updatePageHit) - node T_2731 = and(T_893, updatePageHit) - node T_2732 = and(T_898, updatePageHit) - node T_2734 = neq(T_2671, UInt<1>("h0")) - node T_2736 = neq(T_2672, UInt<1>("h0")) - node T_2738 = neq(T_2673, UInt<1>("h0")) - node T_2740 = neq(T_2674, UInt<1>("h0")) - node T_2742 = neq(T_2675, UInt<1>("h0")) - node T_2744 = neq(T_2676, UInt<1>("h0")) - node T_2746 = neq(T_2677, UInt<1>("h0")) - node T_2748 = neq(T_2678, UInt<1>("h0")) - node T_2750 = neq(T_2679, UInt<1>("h0")) - node T_2752 = neq(T_2680, UInt<1>("h0")) - node T_2754 = neq(T_2681, UInt<1>("h0")) - node T_2756 = neq(T_2682, UInt<1>("h0")) - node T_2758 = neq(T_2683, UInt<1>("h0")) - node T_2760 = neq(T_2684, UInt<1>("h0")) - node T_2762 = neq(T_2685, UInt<1>("h0")) - node T_2764 = neq(T_2686, UInt<1>("h0")) - node T_2766 = neq(T_2687, UInt<1>("h0")) - node T_2768 = neq(T_2688, UInt<1>("h0")) - node T_2770 = neq(T_2689, UInt<1>("h0")) - node T_2772 = neq(T_2690, UInt<1>("h0")) - node T_2774 = neq(T_2691, UInt<1>("h0")) - node T_2776 = neq(T_2692, UInt<1>("h0")) - node T_2778 = neq(T_2693, UInt<1>("h0")) - node T_2780 = neq(T_2694, UInt<1>("h0")) - node T_2782 = neq(T_2695, UInt<1>("h0")) - node T_2784 = neq(T_2696, UInt<1>("h0")) - node T_2786 = neq(T_2697, UInt<1>("h0")) - node T_2788 = neq(T_2698, UInt<1>("h0")) - node T_2790 = neq(T_2699, UInt<1>("h0")) - node T_2792 = neq(T_2700, UInt<1>("h0")) - node T_2794 = neq(T_2701, UInt<1>("h0")) - node T_2796 = neq(T_2702, UInt<1>("h0")) - node T_2798 = neq(T_2703, UInt<1>("h0")) - node T_2800 = neq(T_2704, UInt<1>("h0")) - node T_2802 = neq(T_2705, UInt<1>("h0")) - node T_2804 = neq(T_2706, UInt<1>("h0")) - node T_2806 = neq(T_2707, UInt<1>("h0")) - node T_2808 = neq(T_2708, UInt<1>("h0")) - node T_2810 = neq(T_2709, UInt<1>("h0")) - node T_2812 = neq(T_2710, UInt<1>("h0")) - node T_2814 = neq(T_2711, UInt<1>("h0")) - node T_2816 = neq(T_2712, UInt<1>("h0")) - node T_2818 = neq(T_2713, UInt<1>("h0")) - node T_2820 = neq(T_2714, UInt<1>("h0")) - node T_2822 = neq(T_2715, UInt<1>("h0")) - node T_2824 = neq(T_2716, UInt<1>("h0")) - node T_2826 = neq(T_2717, UInt<1>("h0")) - node T_2828 = neq(T_2718, UInt<1>("h0")) - node T_2830 = neq(T_2719, UInt<1>("h0")) - node T_2832 = neq(T_2720, UInt<1>("h0")) - node T_2834 = neq(T_2721, UInt<1>("h0")) - node T_2836 = neq(T_2722, UInt<1>("h0")) - node T_2838 = neq(T_2723, UInt<1>("h0")) - node T_2840 = neq(T_2724, UInt<1>("h0")) - node T_2842 = neq(T_2725, UInt<1>("h0")) - node T_2844 = neq(T_2726, UInt<1>("h0")) - node T_2846 = neq(T_2727, UInt<1>("h0")) - node T_2848 = neq(T_2728, UInt<1>("h0")) - node T_2850 = neq(T_2729, UInt<1>("h0")) - node T_2852 = neq(T_2730, UInt<1>("h0")) - node T_2854 = neq(T_2731, UInt<1>("h0")) - node T_2856 = neq(T_2732, UInt<1>("h0")) - wire T_2858 : UInt<1>[62] - T_2858[0] <= T_2734 - T_2858[1] <= T_2736 - T_2858[2] <= T_2738 - T_2858[3] <= T_2740 - T_2858[4] <= T_2742 - T_2858[5] <= T_2744 - T_2858[6] <= T_2746 - T_2858[7] <= T_2748 - T_2858[8] <= T_2750 - T_2858[9] <= T_2752 - T_2858[10] <= T_2754 - T_2858[11] <= T_2756 - T_2858[12] <= T_2758 - T_2858[13] <= T_2760 - T_2858[14] <= T_2762 - T_2858[15] <= T_2764 - T_2858[16] <= T_2766 - T_2858[17] <= T_2768 - T_2858[18] <= T_2770 - T_2858[19] <= T_2772 - T_2858[20] <= T_2774 - T_2858[21] <= T_2776 - T_2858[22] <= T_2778 - T_2858[23] <= T_2780 - T_2858[24] <= T_2782 - T_2858[25] <= T_2784 - T_2858[26] <= T_2786 - T_2858[27] <= T_2788 - T_2858[28] <= T_2790 - T_2858[29] <= T_2792 - T_2858[30] <= T_2794 - T_2858[31] <= T_2796 - T_2858[32] <= T_2798 - T_2858[33] <= T_2800 - T_2858[34] <= T_2802 - T_2858[35] <= T_2804 - T_2858[36] <= T_2806 - T_2858[37] <= T_2808 - T_2858[38] <= T_2810 - T_2858[39] <= T_2812 - T_2858[40] <= T_2814 - T_2858[41] <= T_2816 - T_2858[42] <= T_2818 - T_2858[43] <= T_2820 - T_2858[44] <= T_2822 - T_2858[45] <= T_2824 - T_2858[46] <= T_2826 - T_2858[47] <= T_2828 - T_2858[48] <= T_2830 - T_2858[49] <= T_2832 - T_2858[50] <= T_2834 - T_2858[51] <= T_2836 - T_2858[52] <= T_2838 - T_2858[53] <= T_2840 - T_2858[54] <= T_2842 - T_2858[55] <= T_2844 - T_2858[56] <= T_2846 - T_2858[57] <= T_2848 - T_2858[58] <= T_2850 - T_2858[59] <= T_2852 - T_2858[60] <= T_2854 - T_2858[61] <= T_2856 - node T_2922 = cat(T_2858[60], T_2858[59]) - node T_2923 = cat(T_2858[61], T_2922) - node T_2924 = cat(T_2858[58], T_2858[57]) - node T_2925 = cat(T_2858[56], T_2858[55]) - node T_2926 = cat(T_2924, T_2925) - node T_2927 = cat(T_2923, T_2926) - node T_2928 = cat(T_2858[54], T_2858[53]) - node T_2929 = cat(T_2858[52], T_2858[51]) - node T_2930 = cat(T_2928, T_2929) - node T_2931 = cat(T_2858[50], T_2858[49]) - node T_2932 = cat(T_2858[48], T_2858[47]) - node T_2933 = cat(T_2931, T_2932) - node T_2934 = cat(T_2930, T_2933) - node T_2935 = cat(T_2927, T_2934) - node T_2936 = cat(T_2858[46], T_2858[45]) - node T_2937 = cat(T_2858[44], T_2858[43]) - node T_2938 = cat(T_2936, T_2937) - node T_2939 = cat(T_2858[42], T_2858[41]) - node T_2940 = cat(T_2858[40], T_2858[39]) - node T_2941 = cat(T_2939, T_2940) - node T_2942 = cat(T_2938, T_2941) - node T_2943 = cat(T_2858[38], T_2858[37]) - node T_2944 = cat(T_2858[36], T_2858[35]) - node T_2945 = cat(T_2943, T_2944) - node T_2946 = cat(T_2858[34], T_2858[33]) - node T_2947 = cat(T_2858[32], T_2858[31]) - node T_2948 = cat(T_2946, T_2947) - node T_2949 = cat(T_2945, T_2948) - node T_2950 = cat(T_2942, T_2949) - node T_2951 = cat(T_2935, T_2950) - node T_2952 = cat(T_2858[29], T_2858[28]) - node T_2953 = cat(T_2858[30], T_2952) - node T_2954 = cat(T_2858[27], T_2858[26]) - node T_2955 = cat(T_2858[25], T_2858[24]) - node T_2956 = cat(T_2954, T_2955) - node T_2957 = cat(T_2953, T_2956) - node T_2958 = cat(T_2858[23], T_2858[22]) - node T_2959 = cat(T_2858[21], T_2858[20]) - node T_2960 = cat(T_2958, T_2959) - node T_2961 = cat(T_2858[19], T_2858[18]) - node T_2962 = cat(T_2858[17], T_2858[16]) - node T_2963 = cat(T_2961, T_2962) - node T_2964 = cat(T_2960, T_2963) - node T_2965 = cat(T_2957, T_2964) - node T_2966 = cat(T_2858[15], T_2858[14]) - node T_2967 = cat(T_2858[13], T_2858[12]) - node T_2968 = cat(T_2966, T_2967) - node T_2969 = cat(T_2858[11], T_2858[10]) - node T_2970 = cat(T_2858[9], T_2858[8]) - node T_2971 = cat(T_2969, T_2970) - node T_2972 = cat(T_2968, T_2971) - node T_2973 = cat(T_2858[7], T_2858[6]) - node T_2974 = cat(T_2858[5], T_2858[4]) - node T_2975 = cat(T_2973, T_2974) - node T_2976 = cat(T_2858[3], T_2858[2]) - node T_2977 = cat(T_2858[1], T_2858[0]) - node T_2978 = cat(T_2976, T_2977) - node T_2979 = cat(T_2975, T_2978) - node T_2980 = cat(T_2972, T_2979) - node T_2981 = cat(T_2965, T_2980) - node T_2982 = cat(T_2951, T_2981) - node T_2983 = and(idxValid, T_2670) - node updateHits = and(T_2983, T_2982) - reg T_2986 : UInt<16>, clk with : - reset => (reset, UInt<16>("h1")) - when r_btb_update.valid : - node T_2987 = bits(T_2986, 0, 0) - node T_2988 = bits(T_2986, 2, 2) - node T_2989 = xor(T_2987, T_2988) - node T_2990 = bits(T_2986, 3, 3) - node T_2991 = xor(T_2989, T_2990) - node T_2992 = bits(T_2986, 5, 5) - node T_2993 = xor(T_2991, T_2992) - node T_2994 = bits(T_2986, 15, 1) - node T_2995 = cat(T_2993, T_2994) - T_2986 <= T_2995 - skip - node T_2997 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h0")) - node T_2998 = and(r_btb_update.valid, T_2997) - reg nextRepl : UInt<6>, clk with : - reset => (reset, UInt<6>("h0")) - when T_2998 : - node T_3002 = eq(nextRepl, UInt<6>("h3d")) - node T_3004 = and(UInt<1>("h1"), T_3002) - node T_3007 = add(nextRepl, UInt<1>("h1")) - node T_3008 = tail(T_3007, 1) - node T_3009 = mux(T_3004, UInt<1>("h0"), T_3008) - nextRepl <= T_3009 - skip - node T_3010 = and(T_2998, T_3002) - node useUpdatePageHit = neq(updatePageHit, UInt<1>("h0")) - node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h0")) - wire idxPageRepl : UInt<6> - idxPageRepl is invalid - node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) - node T_3018 = bits(idxPageUpdateOH, 5, 4) - node T_3019 = bits(idxPageUpdateOH, 3, 0) - node T_3021 = neq(T_3018, UInt<1>("h0")) - node T_3022 = or(T_3018, T_3019) - node T_3023 = bits(T_3022, 3, 2) - node T_3024 = bits(T_3022, 1, 0) - node T_3026 = neq(T_3023, UInt<1>("h0")) - node T_3027 = or(T_3023, T_3024) - node T_3028 = bits(T_3027, 1, 1) - node T_3029 = cat(T_3026, T_3028) - node idxPageUpdate = cat(T_3021, T_3029) - node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h0")) - node T_3033 = shr(r_btb_update.bits.pc, 12) - node T_3034 = shr(io.req.bits.addr, 12) - node samePage = eq(T_3033, T_3034) - node T_3036 = not(idxPageReplEn) - node T_3037 = and(pageHit, T_3036) - node usePageHit = neq(T_3037, UInt<1>("h0")) - node T_3041 = eq(samePage, UInt<1>("h0")) - node T_3043 = eq(usePageHit, UInt<1>("h0")) - node doTgtPageRepl = and(T_3041, T_3043) - node T_3045 = bits(idxPageUpdateOH, 4, 0) - node T_3046 = shl(T_3045, 1) - node T_3047 = bits(idxPageUpdateOH, 5, 5) - node T_3048 = or(T_3046, T_3047) - node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048) - node T_3050 = mux(usePageHit, pageHit, tgtPageRepl) - node T_3051 = bits(T_3050, 5, 4) - node T_3052 = bits(T_3050, 3, 0) - node T_3054 = neq(T_3051, UInt<1>("h0")) - node T_3055 = or(T_3051, T_3052) - node T_3056 = bits(T_3055, 3, 2) - node T_3057 = bits(T_3055, 1, 0) - node T_3059 = neq(T_3056, UInt<1>("h0")) - node T_3060 = or(T_3056, T_3057) - node T_3061 = bits(T_3060, 1, 1) - node T_3062 = cat(T_3059, T_3061) - node tgtPageUpdate = cat(T_3054, T_3062) - node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h0")) - node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) - node pageReplEn = or(idxPageReplEn, tgtPageReplEn) - node T_3068 = and(r_btb_update.valid, doPageRepl) - reg T_3070 : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - when T_3068 : - node T_3072 = eq(T_3070, UInt<3>("h5")) - node T_3074 = and(UInt<1>("h1"), T_3072) - node T_3077 = add(T_3070, UInt<1>("h1")) - node T_3078 = tail(T_3077, 1) - node T_3079 = mux(T_3074, UInt<1>("h0"), T_3078) - T_3070 <= T_3079 - skip - node T_3080 = and(T_3068, T_3072) - node T_3082 = dshl(UInt<1>("h1"), T_3070) - idxPageRepl <= T_3082 - when r_btb_update.valid : - node T_3083 = eq(io.req.bits.addr, r_btb_update.bits.target) - node T_3085 = eq(reset, UInt<1>("h0")) - when T_3085 : - node T_3087 = eq(T_3083, UInt<1>("h0")) - when T_3087 : - node T_3089 = eq(reset, UInt<1>("h0")) - when T_3089 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): BTB request != I$ target") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_3090 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) - node T_3091 = or(T_593, T_903) - node T_3092 = and(pageReplEn, T_3091) - node T_3094 = neq(T_3092, UInt<1>("h0")) - node T_3095 = or(T_598, T_908) - node T_3096 = and(pageReplEn, T_3095) - node T_3098 = neq(T_3096, UInt<1>("h0")) - node T_3099 = or(T_603, T_913) - node T_3100 = and(pageReplEn, T_3099) - node T_3102 = neq(T_3100, UInt<1>("h0")) - node T_3103 = or(T_608, T_918) - node T_3104 = and(pageReplEn, T_3103) - node T_3106 = neq(T_3104, UInt<1>("h0")) - node T_3107 = or(T_613, T_923) - node T_3108 = and(pageReplEn, T_3107) - node T_3110 = neq(T_3108, UInt<1>("h0")) - node T_3111 = or(T_618, T_928) - node T_3112 = and(pageReplEn, T_3111) - node T_3114 = neq(T_3112, UInt<1>("h0")) - node T_3115 = or(T_623, T_933) - node T_3116 = and(pageReplEn, T_3115) - node T_3118 = neq(T_3116, UInt<1>("h0")) - node T_3119 = or(T_628, T_938) - node T_3120 = and(pageReplEn, T_3119) - node T_3122 = neq(T_3120, UInt<1>("h0")) - node T_3123 = or(T_633, T_943) - node T_3124 = and(pageReplEn, T_3123) - node T_3126 = neq(T_3124, UInt<1>("h0")) - node T_3127 = or(T_638, T_948) - node T_3128 = and(pageReplEn, T_3127) - node T_3130 = neq(T_3128, UInt<1>("h0")) - node T_3131 = or(T_643, T_953) - node T_3132 = and(pageReplEn, T_3131) - node T_3134 = neq(T_3132, UInt<1>("h0")) - node T_3135 = or(T_648, T_958) - node T_3136 = and(pageReplEn, T_3135) - node T_3138 = neq(T_3136, UInt<1>("h0")) - node T_3139 = or(T_653, T_963) - node T_3140 = and(pageReplEn, T_3139) - node T_3142 = neq(T_3140, UInt<1>("h0")) - node T_3143 = or(T_658, T_968) - node T_3144 = and(pageReplEn, T_3143) - node T_3146 = neq(T_3144, UInt<1>("h0")) - node T_3147 = or(T_663, T_973) - node T_3148 = and(pageReplEn, T_3147) - node T_3150 = neq(T_3148, UInt<1>("h0")) - node T_3151 = or(T_668, T_978) - node T_3152 = and(pageReplEn, T_3151) - node T_3154 = neq(T_3152, UInt<1>("h0")) - node T_3155 = or(T_673, T_983) - node T_3156 = and(pageReplEn, T_3155) - node T_3158 = neq(T_3156, UInt<1>("h0")) - node T_3159 = or(T_678, T_988) - node T_3160 = and(pageReplEn, T_3159) - node T_3162 = neq(T_3160, UInt<1>("h0")) - node T_3163 = or(T_683, T_993) - node T_3164 = and(pageReplEn, T_3163) - node T_3166 = neq(T_3164, UInt<1>("h0")) - node T_3167 = or(T_688, T_998) - node T_3168 = and(pageReplEn, T_3167) - node T_3170 = neq(T_3168, UInt<1>("h0")) - node T_3171 = or(T_693, T_1003) - node T_3172 = and(pageReplEn, T_3171) - node T_3174 = neq(T_3172, UInt<1>("h0")) - node T_3175 = or(T_698, T_1008) - node T_3176 = and(pageReplEn, T_3175) - node T_3178 = neq(T_3176, UInt<1>("h0")) - node T_3179 = or(T_703, T_1013) - node T_3180 = and(pageReplEn, T_3179) - node T_3182 = neq(T_3180, UInt<1>("h0")) - node T_3183 = or(T_708, T_1018) - node T_3184 = and(pageReplEn, T_3183) - node T_3186 = neq(T_3184, UInt<1>("h0")) - node T_3187 = or(T_713, T_1023) - node T_3188 = and(pageReplEn, T_3187) - node T_3190 = neq(T_3188, UInt<1>("h0")) - node T_3191 = or(T_718, T_1028) - node T_3192 = and(pageReplEn, T_3191) - node T_3194 = neq(T_3192, UInt<1>("h0")) - node T_3195 = or(T_723, T_1033) - node T_3196 = and(pageReplEn, T_3195) - node T_3198 = neq(T_3196, UInt<1>("h0")) - node T_3199 = or(T_728, T_1038) - node T_3200 = and(pageReplEn, T_3199) - node T_3202 = neq(T_3200, UInt<1>("h0")) - node T_3203 = or(T_733, T_1043) - node T_3204 = and(pageReplEn, T_3203) - node T_3206 = neq(T_3204, UInt<1>("h0")) - node T_3207 = or(T_738, T_1048) - node T_3208 = and(pageReplEn, T_3207) - node T_3210 = neq(T_3208, UInt<1>("h0")) - node T_3211 = or(T_743, T_1053) - node T_3212 = and(pageReplEn, T_3211) - node T_3214 = neq(T_3212, UInt<1>("h0")) - node T_3215 = or(T_748, T_1058) - node T_3216 = and(pageReplEn, T_3215) - node T_3218 = neq(T_3216, UInt<1>("h0")) - node T_3219 = or(T_753, T_1063) - node T_3220 = and(pageReplEn, T_3219) - node T_3222 = neq(T_3220, UInt<1>("h0")) - node T_3223 = or(T_758, T_1068) - node T_3224 = and(pageReplEn, T_3223) - node T_3226 = neq(T_3224, UInt<1>("h0")) - node T_3227 = or(T_763, T_1073) - node T_3228 = and(pageReplEn, T_3227) - node T_3230 = neq(T_3228, UInt<1>("h0")) - node T_3231 = or(T_768, T_1078) - node T_3232 = and(pageReplEn, T_3231) - node T_3234 = neq(T_3232, UInt<1>("h0")) - node T_3235 = or(T_773, T_1083) - node T_3236 = and(pageReplEn, T_3235) - node T_3238 = neq(T_3236, UInt<1>("h0")) - node T_3239 = or(T_778, T_1088) - node T_3240 = and(pageReplEn, T_3239) - node T_3242 = neq(T_3240, UInt<1>("h0")) - node T_3243 = or(T_783, T_1093) - node T_3244 = and(pageReplEn, T_3243) - node T_3246 = neq(T_3244, UInt<1>("h0")) - node T_3247 = or(T_788, T_1098) - node T_3248 = and(pageReplEn, T_3247) - node T_3250 = neq(T_3248, UInt<1>("h0")) - node T_3251 = or(T_793, T_1103) - node T_3252 = and(pageReplEn, T_3251) - node T_3254 = neq(T_3252, UInt<1>("h0")) - node T_3255 = or(T_798, T_1108) - node T_3256 = and(pageReplEn, T_3255) - node T_3258 = neq(T_3256, UInt<1>("h0")) - node T_3259 = or(T_803, T_1113) - node T_3260 = and(pageReplEn, T_3259) - node T_3262 = neq(T_3260, UInt<1>("h0")) - node T_3263 = or(T_808, T_1118) - node T_3264 = and(pageReplEn, T_3263) - node T_3266 = neq(T_3264, UInt<1>("h0")) - node T_3267 = or(T_813, T_1123) - node T_3268 = and(pageReplEn, T_3267) - node T_3270 = neq(T_3268, UInt<1>("h0")) - node T_3271 = or(T_818, T_1128) - node T_3272 = and(pageReplEn, T_3271) - node T_3274 = neq(T_3272, UInt<1>("h0")) - node T_3275 = or(T_823, T_1133) - node T_3276 = and(pageReplEn, T_3275) - node T_3278 = neq(T_3276, UInt<1>("h0")) - node T_3279 = or(T_828, T_1138) - node T_3280 = and(pageReplEn, T_3279) - node T_3282 = neq(T_3280, UInt<1>("h0")) - node T_3283 = or(T_833, T_1143) - node T_3284 = and(pageReplEn, T_3283) - node T_3286 = neq(T_3284, UInt<1>("h0")) - node T_3287 = or(T_838, T_1148) - node T_3288 = and(pageReplEn, T_3287) - node T_3290 = neq(T_3288, UInt<1>("h0")) - node T_3291 = or(T_843, T_1153) - node T_3292 = and(pageReplEn, T_3291) - node T_3294 = neq(T_3292, UInt<1>("h0")) - node T_3295 = or(T_848, T_1158) - node T_3296 = and(pageReplEn, T_3295) - node T_3298 = neq(T_3296, UInt<1>("h0")) - node T_3299 = or(T_853, T_1163) - node T_3300 = and(pageReplEn, T_3299) - node T_3302 = neq(T_3300, UInt<1>("h0")) - node T_3303 = or(T_858, T_1168) - node T_3304 = and(pageReplEn, T_3303) - node T_3306 = neq(T_3304, UInt<1>("h0")) - node T_3307 = or(T_863, T_1173) - node T_3308 = and(pageReplEn, T_3307) - node T_3310 = neq(T_3308, UInt<1>("h0")) - node T_3311 = or(T_868, T_1178) - node T_3312 = and(pageReplEn, T_3311) - node T_3314 = neq(T_3312, UInt<1>("h0")) - node T_3315 = or(T_873, T_1183) - node T_3316 = and(pageReplEn, T_3315) - node T_3318 = neq(T_3316, UInt<1>("h0")) - node T_3319 = or(T_878, T_1188) - node T_3320 = and(pageReplEn, T_3319) - node T_3322 = neq(T_3320, UInt<1>("h0")) - node T_3323 = or(T_883, T_1193) - node T_3324 = and(pageReplEn, T_3323) - node T_3326 = neq(T_3324, UInt<1>("h0")) - node T_3327 = or(T_888, T_1198) - node T_3328 = and(pageReplEn, T_3327) - node T_3330 = neq(T_3328, UInt<1>("h0")) - node T_3331 = or(T_893, T_1203) - node T_3332 = and(pageReplEn, T_3331) - node T_3334 = neq(T_3332, UInt<1>("h0")) - node T_3335 = or(T_898, T_1208) - node T_3336 = and(pageReplEn, T_3335) - node T_3338 = neq(T_3336, UInt<1>("h0")) - wire T_3340 : UInt<1>[62] - T_3340[0] <= T_3094 - T_3340[1] <= T_3098 - T_3340[2] <= T_3102 - T_3340[3] <= T_3106 - T_3340[4] <= T_3110 - T_3340[5] <= T_3114 - T_3340[6] <= T_3118 - T_3340[7] <= T_3122 - T_3340[8] <= T_3126 - T_3340[9] <= T_3130 - T_3340[10] <= T_3134 - T_3340[11] <= T_3138 - T_3340[12] <= T_3142 - T_3340[13] <= T_3146 - T_3340[14] <= T_3150 - T_3340[15] <= T_3154 - T_3340[16] <= T_3158 - T_3340[17] <= T_3162 - T_3340[18] <= T_3166 - T_3340[19] <= T_3170 - T_3340[20] <= T_3174 - T_3340[21] <= T_3178 - T_3340[22] <= T_3182 - T_3340[23] <= T_3186 - T_3340[24] <= T_3190 - T_3340[25] <= T_3194 - T_3340[26] <= T_3198 - T_3340[27] <= T_3202 - T_3340[28] <= T_3206 - T_3340[29] <= T_3210 - T_3340[30] <= T_3214 - T_3340[31] <= T_3218 - T_3340[32] <= T_3222 - T_3340[33] <= T_3226 - T_3340[34] <= T_3230 - T_3340[35] <= T_3234 - T_3340[36] <= T_3238 - T_3340[37] <= T_3242 - T_3340[38] <= T_3246 - T_3340[39] <= T_3250 - T_3340[40] <= T_3254 - T_3340[41] <= T_3258 - T_3340[42] <= T_3262 - T_3340[43] <= T_3266 - T_3340[44] <= T_3270 - T_3340[45] <= T_3274 - T_3340[46] <= T_3278 - T_3340[47] <= T_3282 - T_3340[48] <= T_3286 - T_3340[49] <= T_3290 - T_3340[50] <= T_3294 - T_3340[51] <= T_3298 - T_3340[52] <= T_3302 - T_3340[53] <= T_3306 - T_3340[54] <= T_3310 - T_3340[55] <= T_3314 - T_3340[56] <= T_3318 - T_3340[57] <= T_3322 - T_3340[58] <= T_3326 - T_3340[59] <= T_3330 - T_3340[60] <= T_3334 - T_3340[61] <= T_3338 - node T_3404 = cat(T_3340[60], T_3340[59]) - node T_3405 = cat(T_3340[61], T_3404) - node T_3406 = cat(T_3340[58], T_3340[57]) - node T_3407 = cat(T_3340[56], T_3340[55]) - node T_3408 = cat(T_3406, T_3407) - node T_3409 = cat(T_3405, T_3408) - node T_3410 = cat(T_3340[54], T_3340[53]) - node T_3411 = cat(T_3340[52], T_3340[51]) - node T_3412 = cat(T_3410, T_3411) - node T_3413 = cat(T_3340[50], T_3340[49]) - node T_3414 = cat(T_3340[48], T_3340[47]) - node T_3415 = cat(T_3413, T_3414) - node T_3416 = cat(T_3412, T_3415) - node T_3417 = cat(T_3409, T_3416) - node T_3418 = cat(T_3340[46], T_3340[45]) - node T_3419 = cat(T_3340[44], T_3340[43]) - node T_3420 = cat(T_3418, T_3419) - node T_3421 = cat(T_3340[42], T_3340[41]) - node T_3422 = cat(T_3340[40], T_3340[39]) - node T_3423 = cat(T_3421, T_3422) - node T_3424 = cat(T_3420, T_3423) - node T_3425 = cat(T_3340[38], T_3340[37]) - node T_3426 = cat(T_3340[36], T_3340[35]) - node T_3427 = cat(T_3425, T_3426) - node T_3428 = cat(T_3340[34], T_3340[33]) - node T_3429 = cat(T_3340[32], T_3340[31]) - node T_3430 = cat(T_3428, T_3429) - node T_3431 = cat(T_3427, T_3430) - node T_3432 = cat(T_3424, T_3431) - node T_3433 = cat(T_3417, T_3432) - node T_3434 = cat(T_3340[29], T_3340[28]) - node T_3435 = cat(T_3340[30], T_3434) - node T_3436 = cat(T_3340[27], T_3340[26]) - node T_3437 = cat(T_3340[25], T_3340[24]) - node T_3438 = cat(T_3436, T_3437) - node T_3439 = cat(T_3435, T_3438) - node T_3440 = cat(T_3340[23], T_3340[22]) - node T_3441 = cat(T_3340[21], T_3340[20]) - node T_3442 = cat(T_3440, T_3441) - node T_3443 = cat(T_3340[19], T_3340[18]) - node T_3444 = cat(T_3340[17], T_3340[16]) - node T_3445 = cat(T_3443, T_3444) - node T_3446 = cat(T_3442, T_3445) - node T_3447 = cat(T_3439, T_3446) - node T_3448 = cat(T_3340[15], T_3340[14]) - node T_3449 = cat(T_3340[13], T_3340[12]) - node T_3450 = cat(T_3448, T_3449) - node T_3451 = cat(T_3340[11], T_3340[10]) - node T_3452 = cat(T_3340[9], T_3340[8]) - node T_3453 = cat(T_3451, T_3452) - node T_3454 = cat(T_3450, T_3453) - node T_3455 = cat(T_3340[7], T_3340[6]) - node T_3456 = cat(T_3340[5], T_3340[4]) - node T_3457 = cat(T_3455, T_3456) - node T_3458 = cat(T_3340[3], T_3340[2]) - node T_3459 = cat(T_3340[1], T_3340[0]) - node T_3460 = cat(T_3458, T_3459) - node T_3461 = cat(T_3457, T_3460) - node T_3462 = cat(T_3454, T_3461) - node T_3463 = cat(T_3447, T_3462) - node T_3464 = cat(T_3433, T_3463) - node T_3466 = dshl(UInt<1>("h1"), T_3090) - node T_3467 = not(T_3464) - node T_3468 = and(idxValid, T_3467) - node T_3469 = or(T_3468, T_3466) - idxValid <= T_3469 - idxs.T_3470.addr <= T_3090 - idxs.T_3470.en <= UInt<1>("h1") - idxs.T_3470.data <= r_btb_update.bits.pc - idxs.T_3470.mask <= UInt<1>("h1") - tgts.T_3471.addr <= T_3090 - tgts.T_3471.en <= UInt<1>("h1") - tgts.T_3471.data <= io.req.bits.addr - tgts.T_3471.mask <= UInt<1>("h1") - idxPages.T_3472.addr <= T_3090 - idxPages.T_3472.en <= UInt<1>("h1") - idxPages.T_3472.data <= idxPageUpdate - idxPages.T_3472.mask <= UInt<1>("h1") - tgtPages.T_3473.addr <= T_3090 - tgtPages.T_3473.en <= UInt<1>("h1") - tgtPages.T_3473.data <= tgtPageUpdate - tgtPages.T_3473.mask <= UInt<1>("h1") - useRAS[T_3090] <= r_btb_update.bits.isReturn - isJump[T_3090] <= r_btb_update.bits.isJump - brIdx.T_3476.addr <= T_3090 - brIdx.T_3476.en <= UInt<1>("h1") - brIdx.T_3476.data <= UInt<1>("h0") - brIdx.T_3476.mask <= UInt<1>("h1") - node T_3479 = cat(UInt<2>("h1"), UInt<2>("h1")) - node T_3480 = cat(UInt<2>("h1"), T_3479) - node T_3481 = and(idxPageUpdateOH, T_3480) - node T_3483 = neq(T_3481, UInt<1>("h0")) - node T_3484 = mux(T_3483, doIdxPageRepl, doTgtPageRepl) - node T_3485 = shr(r_btb_update.bits.pc, 12) - node T_3486 = shr(io.req.bits.addr, 12) - node T_3487 = mux(T_3483, T_3485, T_3486) - node T_3488 = bits(pageReplEn, 0, 0) - node T_3489 = and(T_3484, T_3488) - when T_3489 : - pages.T_3491.addr <= UInt<1>("h0") - pages.T_3491.en <= UInt<1>("h1") - pages.T_3491.data <= T_3487 - pages.T_3491.mask <= UInt<1>("h1") - skip - node T_3492 = bits(pageReplEn, 2, 2) - node T_3493 = and(T_3484, T_3492) - when T_3493 : - pages.T_3495.addr <= UInt<2>("h2") - pages.T_3495.en <= UInt<1>("h1") - pages.T_3495.data <= T_3487 - pages.T_3495.mask <= UInt<1>("h1") - skip - node T_3496 = bits(pageReplEn, 4, 4) - node T_3497 = and(T_3484, T_3496) - when T_3497 : - pages.T_3499.addr <= UInt<3>("h4") - pages.T_3499.en <= UInt<1>("h1") - pages.T_3499.data <= T_3487 - pages.T_3499.mask <= UInt<1>("h1") - skip - node T_3500 = mux(T_3483, doTgtPageRepl, doIdxPageRepl) - node T_3501 = shr(io.req.bits.addr, 12) - node T_3502 = shr(r_btb_update.bits.pc, 12) - node T_3503 = mux(T_3483, T_3501, T_3502) - node T_3504 = bits(pageReplEn, 1, 1) - node T_3505 = and(T_3500, T_3504) - when T_3505 : - pages.T_3507.addr <= UInt<1>("h1") - pages.T_3507.en <= UInt<1>("h1") - pages.T_3507.data <= T_3503 - pages.T_3507.mask <= UInt<1>("h1") - skip - node T_3508 = bits(pageReplEn, 3, 3) - node T_3509 = and(T_3500, T_3508) - when T_3509 : - pages.T_3511.addr <= UInt<2>("h3") - pages.T_3511.en <= UInt<1>("h1") - pages.T_3511.data <= T_3503 - pages.T_3511.mask <= UInt<1>("h1") - skip - node T_3512 = bits(pageReplEn, 5, 5) - node T_3513 = and(T_3500, T_3512) - when T_3513 : - pages.T_3515.addr <= UInt<3>("h5") - pages.T_3515.en <= UInt<1>("h1") - pages.T_3515.data <= T_3503 - pages.T_3515.mask <= UInt<1>("h1") - skip - when doPageRepl : - node T_3516 = or(pageValid, pageReplEn) - pageValid <= T_3516 - skip - skip - when io.invalidate : - idxValid <= UInt<1>("h0") - pageValid <= UInt<1>("h0") - skip - node T_3520 = neq(hits, UInt<1>("h0")) - io.resp.valid <= T_3520 - io.resp.bits.taken <= io.resp.valid - node T_3521 = bits(hits, 0, 0) - node T_3522 = bits(hits, 1, 1) - node T_3523 = bits(hits, 2, 2) - node T_3524 = bits(hits, 3, 3) - node T_3525 = bits(hits, 4, 4) - node T_3526 = bits(hits, 5, 5) - node T_3527 = bits(hits, 6, 6) - node T_3528 = bits(hits, 7, 7) - node T_3529 = bits(hits, 8, 8) - node T_3530 = bits(hits, 9, 9) - node T_3531 = bits(hits, 10, 10) - node T_3532 = bits(hits, 11, 11) - node T_3533 = bits(hits, 12, 12) - node T_3534 = bits(hits, 13, 13) - node T_3535 = bits(hits, 14, 14) - node T_3536 = bits(hits, 15, 15) - node T_3537 = bits(hits, 16, 16) - node T_3538 = bits(hits, 17, 17) - node T_3539 = bits(hits, 18, 18) - node T_3540 = bits(hits, 19, 19) - node T_3541 = bits(hits, 20, 20) - node T_3542 = bits(hits, 21, 21) - node T_3543 = bits(hits, 22, 22) - node T_3544 = bits(hits, 23, 23) - node T_3545 = bits(hits, 24, 24) - node T_3546 = bits(hits, 25, 25) - node T_3547 = bits(hits, 26, 26) - node T_3548 = bits(hits, 27, 27) - node T_3549 = bits(hits, 28, 28) - node T_3550 = bits(hits, 29, 29) - node T_3551 = bits(hits, 30, 30) - node T_3552 = bits(hits, 31, 31) - node T_3553 = bits(hits, 32, 32) - node T_3554 = bits(hits, 33, 33) - node T_3555 = bits(hits, 34, 34) - node T_3556 = bits(hits, 35, 35) - node T_3557 = bits(hits, 36, 36) - node T_3558 = bits(hits, 37, 37) - node T_3559 = bits(hits, 38, 38) - node T_3560 = bits(hits, 39, 39) - node T_3561 = bits(hits, 40, 40) - node T_3562 = bits(hits, 41, 41) - node T_3563 = bits(hits, 42, 42) - node T_3564 = bits(hits, 43, 43) - node T_3565 = bits(hits, 44, 44) - node T_3566 = bits(hits, 45, 45) - node T_3567 = bits(hits, 46, 46) - node T_3568 = bits(hits, 47, 47) - node T_3569 = bits(hits, 48, 48) - node T_3570 = bits(hits, 49, 49) - node T_3571 = bits(hits, 50, 50) - node T_3572 = bits(hits, 51, 51) - node T_3573 = bits(hits, 52, 52) - node T_3574 = bits(hits, 53, 53) - node T_3575 = bits(hits, 54, 54) - node T_3576 = bits(hits, 55, 55) - node T_3577 = bits(hits, 56, 56) - node T_3578 = bits(hits, 57, 57) - node T_3579 = bits(hits, 58, 58) - node T_3580 = bits(hits, 59, 59) - node T_3581 = bits(hits, 60, 60) - node T_3582 = bits(hits, 61, 61) - node T_3584 = mux(T_3521, T_903, UInt<1>("h0")) - node T_3586 = mux(T_3522, T_908, UInt<1>("h0")) - node T_3588 = mux(T_3523, T_913, UInt<1>("h0")) - node T_3590 = mux(T_3524, T_918, UInt<1>("h0")) - node T_3592 = mux(T_3525, T_923, UInt<1>("h0")) - node T_3594 = mux(T_3526, T_928, UInt<1>("h0")) - node T_3596 = mux(T_3527, T_933, UInt<1>("h0")) - node T_3598 = mux(T_3528, T_938, UInt<1>("h0")) - node T_3600 = mux(T_3529, T_943, UInt<1>("h0")) - node T_3602 = mux(T_3530, T_948, UInt<1>("h0")) - node T_3604 = mux(T_3531, T_953, UInt<1>("h0")) - node T_3606 = mux(T_3532, T_958, UInt<1>("h0")) - node T_3608 = mux(T_3533, T_963, UInt<1>("h0")) - node T_3610 = mux(T_3534, T_968, UInt<1>("h0")) - node T_3612 = mux(T_3535, T_973, UInt<1>("h0")) - node T_3614 = mux(T_3536, T_978, UInt<1>("h0")) - node T_3616 = mux(T_3537, T_983, UInt<1>("h0")) - node T_3618 = mux(T_3538, T_988, UInt<1>("h0")) - node T_3620 = mux(T_3539, T_993, UInt<1>("h0")) - node T_3622 = mux(T_3540, T_998, UInt<1>("h0")) - node T_3624 = mux(T_3541, T_1003, UInt<1>("h0")) - node T_3626 = mux(T_3542, T_1008, UInt<1>("h0")) - node T_3628 = mux(T_3543, T_1013, UInt<1>("h0")) - node T_3630 = mux(T_3544, T_1018, UInt<1>("h0")) - node T_3632 = mux(T_3545, T_1023, UInt<1>("h0")) - node T_3634 = mux(T_3546, T_1028, UInt<1>("h0")) - node T_3636 = mux(T_3547, T_1033, UInt<1>("h0")) - node T_3638 = mux(T_3548, T_1038, UInt<1>("h0")) - node T_3640 = mux(T_3549, T_1043, UInt<1>("h0")) - node T_3642 = mux(T_3550, T_1048, UInt<1>("h0")) - node T_3644 = mux(T_3551, T_1053, UInt<1>("h0")) - node T_3646 = mux(T_3552, T_1058, UInt<1>("h0")) - node T_3648 = mux(T_3553, T_1063, UInt<1>("h0")) - node T_3650 = mux(T_3554, T_1068, UInt<1>("h0")) - node T_3652 = mux(T_3555, T_1073, UInt<1>("h0")) - node T_3654 = mux(T_3556, T_1078, UInt<1>("h0")) - node T_3656 = mux(T_3557, T_1083, UInt<1>("h0")) - node T_3658 = mux(T_3558, T_1088, UInt<1>("h0")) - node T_3660 = mux(T_3559, T_1093, UInt<1>("h0")) - node T_3662 = mux(T_3560, T_1098, UInt<1>("h0")) - node T_3664 = mux(T_3561, T_1103, UInt<1>("h0")) - node T_3666 = mux(T_3562, T_1108, UInt<1>("h0")) - node T_3668 = mux(T_3563, T_1113, UInt<1>("h0")) - node T_3670 = mux(T_3564, T_1118, UInt<1>("h0")) - node T_3672 = mux(T_3565, T_1123, UInt<1>("h0")) - node T_3674 = mux(T_3566, T_1128, UInt<1>("h0")) - node T_3676 = mux(T_3567, T_1133, UInt<1>("h0")) - node T_3678 = mux(T_3568, T_1138, UInt<1>("h0")) - node T_3680 = mux(T_3569, T_1143, UInt<1>("h0")) - node T_3682 = mux(T_3570, T_1148, UInt<1>("h0")) - node T_3684 = mux(T_3571, T_1153, UInt<1>("h0")) - node T_3686 = mux(T_3572, T_1158, UInt<1>("h0")) - node T_3688 = mux(T_3573, T_1163, UInt<1>("h0")) - node T_3690 = mux(T_3574, T_1168, UInt<1>("h0")) - node T_3692 = mux(T_3575, T_1173, UInt<1>("h0")) - node T_3694 = mux(T_3576, T_1178, UInt<1>("h0")) - node T_3696 = mux(T_3577, T_1183, UInt<1>("h0")) - node T_3698 = mux(T_3578, T_1188, UInt<1>("h0")) - node T_3700 = mux(T_3579, T_1193, UInt<1>("h0")) - node T_3702 = mux(T_3580, T_1198, UInt<1>("h0")) - node T_3704 = mux(T_3581, T_1203, UInt<1>("h0")) - node T_3706 = mux(T_3582, T_1208, UInt<1>("h0")) - node T_3708 = or(T_3584, T_3586) - node T_3709 = or(T_3708, T_3588) - node T_3710 = or(T_3709, T_3590) - node T_3711 = or(T_3710, T_3592) - node T_3712 = or(T_3711, T_3594) - node T_3713 = or(T_3712, T_3596) - node T_3714 = or(T_3713, T_3598) - node T_3715 = or(T_3714, T_3600) - node T_3716 = or(T_3715, T_3602) - node T_3717 = or(T_3716, T_3604) - node T_3718 = or(T_3717, T_3606) - node T_3719 = or(T_3718, T_3608) - node T_3720 = or(T_3719, T_3610) - node T_3721 = or(T_3720, T_3612) - node T_3722 = or(T_3721, T_3614) - node T_3723 = or(T_3722, T_3616) - node T_3724 = or(T_3723, T_3618) - node T_3725 = or(T_3724, T_3620) - node T_3726 = or(T_3725, T_3622) - node T_3727 = or(T_3726, T_3624) - node T_3728 = or(T_3727, T_3626) - node T_3729 = or(T_3728, T_3628) - node T_3730 = or(T_3729, T_3630) - node T_3731 = or(T_3730, T_3632) - node T_3732 = or(T_3731, T_3634) - node T_3733 = or(T_3732, T_3636) - node T_3734 = or(T_3733, T_3638) - node T_3735 = or(T_3734, T_3640) - node T_3736 = or(T_3735, T_3642) - node T_3737 = or(T_3736, T_3644) - node T_3738 = or(T_3737, T_3646) - node T_3739 = or(T_3738, T_3648) - node T_3740 = or(T_3739, T_3650) - node T_3741 = or(T_3740, T_3652) - node T_3742 = or(T_3741, T_3654) - node T_3743 = or(T_3742, T_3656) - node T_3744 = or(T_3743, T_3658) - node T_3745 = or(T_3744, T_3660) - node T_3746 = or(T_3745, T_3662) - node T_3747 = or(T_3746, T_3664) - node T_3748 = or(T_3747, T_3666) - node T_3749 = or(T_3748, T_3668) - node T_3750 = or(T_3749, T_3670) - node T_3751 = or(T_3750, T_3672) - node T_3752 = or(T_3751, T_3674) - node T_3753 = or(T_3752, T_3676) - node T_3754 = or(T_3753, T_3678) - node T_3755 = or(T_3754, T_3680) - node T_3756 = or(T_3755, T_3682) - node T_3757 = or(T_3756, T_3684) - node T_3758 = or(T_3757, T_3686) - node T_3759 = or(T_3758, T_3688) - node T_3760 = or(T_3759, T_3690) - node T_3761 = or(T_3760, T_3692) - node T_3762 = or(T_3761, T_3694) - node T_3763 = or(T_3762, T_3696) - node T_3764 = or(T_3763, T_3698) - node T_3765 = or(T_3764, T_3700) - node T_3766 = or(T_3765, T_3702) - node T_3767 = or(T_3766, T_3704) - node T_3768 = or(T_3767, T_3706) - wire T_3769 : UInt<6> - T_3769 is invalid - T_3769 <= T_3768 - node T_3770 = bits(T_3769, 0, 0) - node T_3771 = bits(T_3769, 1, 1) - node T_3772 = bits(T_3769, 2, 2) - node T_3773 = bits(T_3769, 3, 3) - node T_3774 = bits(T_3769, 4, 4) - node T_3775 = bits(T_3769, 5, 5) - pages.T_3777.addr <= UInt<1>("h0") - pages.T_3777.en <= UInt<1>("h1") - pages.T_3779.addr <= UInt<1>("h1") - pages.T_3779.en <= UInt<1>("h1") - pages.T_3781.addr <= UInt<2>("h2") - pages.T_3781.en <= UInt<1>("h1") - pages.T_3783.addr <= UInt<2>("h3") - pages.T_3783.en <= UInt<1>("h1") - pages.T_3785.addr <= UInt<3>("h4") - pages.T_3785.en <= UInt<1>("h1") - pages.T_3787.addr <= UInt<3>("h5") - pages.T_3787.en <= UInt<1>("h1") - node T_3789 = mux(T_3770, pages.T_3777.data, UInt<1>("h0")) - node T_3791 = mux(T_3771, pages.T_3779.data, UInt<1>("h0")) - node T_3793 = mux(T_3772, pages.T_3781.data, UInt<1>("h0")) - node T_3795 = mux(T_3773, pages.T_3783.data, UInt<1>("h0")) - node T_3797 = mux(T_3774, pages.T_3785.data, UInt<1>("h0")) - node T_3799 = mux(T_3775, pages.T_3787.data, UInt<1>("h0")) - node T_3801 = or(T_3789, T_3791) - node T_3802 = or(T_3801, T_3793) - node T_3803 = or(T_3802, T_3795) - node T_3804 = or(T_3803, T_3797) - node T_3805 = or(T_3804, T_3799) - wire T_3806 : UInt<27> - T_3806 is invalid - T_3806 <= T_3805 - node T_3807 = bits(hits, 0, 0) - node T_3808 = bits(hits, 1, 1) - node T_3809 = bits(hits, 2, 2) - node T_3810 = bits(hits, 3, 3) - node T_3811 = bits(hits, 4, 4) - node T_3812 = bits(hits, 5, 5) - node T_3813 = bits(hits, 6, 6) - node T_3814 = bits(hits, 7, 7) - node T_3815 = bits(hits, 8, 8) - node T_3816 = bits(hits, 9, 9) - node T_3817 = bits(hits, 10, 10) - node T_3818 = bits(hits, 11, 11) - node T_3819 = bits(hits, 12, 12) - node T_3820 = bits(hits, 13, 13) - node T_3821 = bits(hits, 14, 14) - node T_3822 = bits(hits, 15, 15) - node T_3823 = bits(hits, 16, 16) - node T_3824 = bits(hits, 17, 17) - node T_3825 = bits(hits, 18, 18) - node T_3826 = bits(hits, 19, 19) - node T_3827 = bits(hits, 20, 20) - node T_3828 = bits(hits, 21, 21) - node T_3829 = bits(hits, 22, 22) - node T_3830 = bits(hits, 23, 23) - node T_3831 = bits(hits, 24, 24) - node T_3832 = bits(hits, 25, 25) - node T_3833 = bits(hits, 26, 26) - node T_3834 = bits(hits, 27, 27) - node T_3835 = bits(hits, 28, 28) - node T_3836 = bits(hits, 29, 29) - node T_3837 = bits(hits, 30, 30) - node T_3838 = bits(hits, 31, 31) - node T_3839 = bits(hits, 32, 32) - node T_3840 = bits(hits, 33, 33) - node T_3841 = bits(hits, 34, 34) - node T_3842 = bits(hits, 35, 35) - node T_3843 = bits(hits, 36, 36) - node T_3844 = bits(hits, 37, 37) - node T_3845 = bits(hits, 38, 38) - node T_3846 = bits(hits, 39, 39) - node T_3847 = bits(hits, 40, 40) - node T_3848 = bits(hits, 41, 41) - node T_3849 = bits(hits, 42, 42) - node T_3850 = bits(hits, 43, 43) - node T_3851 = bits(hits, 44, 44) - node T_3852 = bits(hits, 45, 45) - node T_3853 = bits(hits, 46, 46) - node T_3854 = bits(hits, 47, 47) - node T_3855 = bits(hits, 48, 48) - node T_3856 = bits(hits, 49, 49) - node T_3857 = bits(hits, 50, 50) - node T_3858 = bits(hits, 51, 51) - node T_3859 = bits(hits, 52, 52) - node T_3860 = bits(hits, 53, 53) - node T_3861 = bits(hits, 54, 54) - node T_3862 = bits(hits, 55, 55) - node T_3863 = bits(hits, 56, 56) - node T_3864 = bits(hits, 57, 57) - node T_3865 = bits(hits, 58, 58) - node T_3866 = bits(hits, 59, 59) - node T_3867 = bits(hits, 60, 60) - node T_3868 = bits(hits, 61, 61) - tgts.T_3870.addr <= UInt<1>("h0") - tgts.T_3870.en <= UInt<1>("h1") - tgts.T_3872.addr <= UInt<1>("h1") - tgts.T_3872.en <= UInt<1>("h1") - tgts.T_3874.addr <= UInt<2>("h2") - tgts.T_3874.en <= UInt<1>("h1") - tgts.T_3876.addr <= UInt<2>("h3") - tgts.T_3876.en <= UInt<1>("h1") - tgts.T_3878.addr <= UInt<3>("h4") - tgts.T_3878.en <= UInt<1>("h1") - tgts.T_3880.addr <= UInt<3>("h5") - tgts.T_3880.en <= UInt<1>("h1") - tgts.T_3882.addr <= UInt<3>("h6") - tgts.T_3882.en <= UInt<1>("h1") - tgts.T_3884.addr <= UInt<3>("h7") - tgts.T_3884.en <= UInt<1>("h1") - tgts.T_3886.addr <= UInt<4>("h8") - tgts.T_3886.en <= UInt<1>("h1") - tgts.T_3888.addr <= UInt<4>("h9") - tgts.T_3888.en <= UInt<1>("h1") - tgts.T_3890.addr <= UInt<4>("ha") - tgts.T_3890.en <= UInt<1>("h1") - tgts.T_3892.addr <= UInt<4>("hb") - tgts.T_3892.en <= UInt<1>("h1") - tgts.T_3894.addr <= UInt<4>("hc") - tgts.T_3894.en <= UInt<1>("h1") - tgts.T_3896.addr <= UInt<4>("hd") - tgts.T_3896.en <= UInt<1>("h1") - tgts.T_3898.addr <= UInt<4>("he") - tgts.T_3898.en <= UInt<1>("h1") - tgts.T_3900.addr <= UInt<4>("hf") - tgts.T_3900.en <= UInt<1>("h1") - tgts.T_3902.addr <= UInt<5>("h10") - tgts.T_3902.en <= UInt<1>("h1") - tgts.T_3904.addr <= UInt<5>("h11") - tgts.T_3904.en <= UInt<1>("h1") - tgts.T_3906.addr <= UInt<5>("h12") - tgts.T_3906.en <= UInt<1>("h1") - tgts.T_3908.addr <= UInt<5>("h13") - tgts.T_3908.en <= UInt<1>("h1") - tgts.T_3910.addr <= UInt<5>("h14") - tgts.T_3910.en <= UInt<1>("h1") - tgts.T_3912.addr <= UInt<5>("h15") - tgts.T_3912.en <= UInt<1>("h1") - tgts.T_3914.addr <= UInt<5>("h16") - tgts.T_3914.en <= UInt<1>("h1") - tgts.T_3916.addr <= UInt<5>("h17") - tgts.T_3916.en <= UInt<1>("h1") - tgts.T_3918.addr <= UInt<5>("h18") - tgts.T_3918.en <= UInt<1>("h1") - tgts.T_3920.addr <= UInt<5>("h19") - tgts.T_3920.en <= UInt<1>("h1") - tgts.T_3922.addr <= UInt<5>("h1a") - tgts.T_3922.en <= UInt<1>("h1") - tgts.T_3924.addr <= UInt<5>("h1b") - tgts.T_3924.en <= UInt<1>("h1") - tgts.T_3926.addr <= UInt<5>("h1c") - tgts.T_3926.en <= UInt<1>("h1") - tgts.T_3928.addr <= UInt<5>("h1d") - tgts.T_3928.en <= UInt<1>("h1") - tgts.T_3930.addr <= UInt<5>("h1e") - tgts.T_3930.en <= UInt<1>("h1") - tgts.T_3932.addr <= UInt<5>("h1f") - tgts.T_3932.en <= UInt<1>("h1") - tgts.T_3934.addr <= UInt<6>("h20") - tgts.T_3934.en <= UInt<1>("h1") - tgts.T_3936.addr <= UInt<6>("h21") - tgts.T_3936.en <= UInt<1>("h1") - tgts.T_3938.addr <= UInt<6>("h22") - tgts.T_3938.en <= UInt<1>("h1") - tgts.T_3940.addr <= UInt<6>("h23") - tgts.T_3940.en <= UInt<1>("h1") - tgts.T_3942.addr <= UInt<6>("h24") - tgts.T_3942.en <= UInt<1>("h1") - tgts.T_3944.addr <= UInt<6>("h25") - tgts.T_3944.en <= UInt<1>("h1") - tgts.T_3946.addr <= UInt<6>("h26") - tgts.T_3946.en <= UInt<1>("h1") - tgts.T_3948.addr <= UInt<6>("h27") - tgts.T_3948.en <= UInt<1>("h1") - tgts.T_3950.addr <= UInt<6>("h28") - tgts.T_3950.en <= UInt<1>("h1") - tgts.T_3952.addr <= UInt<6>("h29") - tgts.T_3952.en <= UInt<1>("h1") - tgts.T_3954.addr <= UInt<6>("h2a") - tgts.T_3954.en <= UInt<1>("h1") - tgts.T_3956.addr <= UInt<6>("h2b") - tgts.T_3956.en <= UInt<1>("h1") - tgts.T_3958.addr <= UInt<6>("h2c") - tgts.T_3958.en <= UInt<1>("h1") - tgts.T_3960.addr <= UInt<6>("h2d") - tgts.T_3960.en <= UInt<1>("h1") - tgts.T_3962.addr <= UInt<6>("h2e") - tgts.T_3962.en <= UInt<1>("h1") - tgts.T_3964.addr <= UInt<6>("h2f") - tgts.T_3964.en <= UInt<1>("h1") - tgts.T_3966.addr <= UInt<6>("h30") - tgts.T_3966.en <= UInt<1>("h1") - tgts.T_3968.addr <= UInt<6>("h31") - tgts.T_3968.en <= UInt<1>("h1") - tgts.T_3970.addr <= UInt<6>("h32") - tgts.T_3970.en <= UInt<1>("h1") - tgts.T_3972.addr <= UInt<6>("h33") - tgts.T_3972.en <= UInt<1>("h1") - tgts.T_3974.addr <= UInt<6>("h34") - tgts.T_3974.en <= UInt<1>("h1") - tgts.T_3976.addr <= UInt<6>("h35") - tgts.T_3976.en <= UInt<1>("h1") - tgts.T_3978.addr <= UInt<6>("h36") - tgts.T_3978.en <= UInt<1>("h1") - tgts.T_3980.addr <= UInt<6>("h37") - tgts.T_3980.en <= UInt<1>("h1") - tgts.T_3982.addr <= UInt<6>("h38") - tgts.T_3982.en <= UInt<1>("h1") - tgts.T_3984.addr <= UInt<6>("h39") - tgts.T_3984.en <= UInt<1>("h1") - tgts.T_3986.addr <= UInt<6>("h3a") - tgts.T_3986.en <= UInt<1>("h1") - tgts.T_3988.addr <= UInt<6>("h3b") - tgts.T_3988.en <= UInt<1>("h1") - tgts.T_3990.addr <= UInt<6>("h3c") - tgts.T_3990.en <= UInt<1>("h1") - tgts.T_3992.addr <= UInt<6>("h3d") - tgts.T_3992.en <= UInt<1>("h1") - node T_3994 = mux(T_3807, tgts.T_3870.data, UInt<1>("h0")) - node T_3996 = mux(T_3808, tgts.T_3872.data, UInt<1>("h0")) - node T_3998 = mux(T_3809, tgts.T_3874.data, UInt<1>("h0")) - node T_4000 = mux(T_3810, tgts.T_3876.data, UInt<1>("h0")) - node T_4002 = mux(T_3811, tgts.T_3878.data, UInt<1>("h0")) - node T_4004 = mux(T_3812, tgts.T_3880.data, UInt<1>("h0")) - node T_4006 = mux(T_3813, tgts.T_3882.data, UInt<1>("h0")) - node T_4008 = mux(T_3814, tgts.T_3884.data, UInt<1>("h0")) - node T_4010 = mux(T_3815, tgts.T_3886.data, UInt<1>("h0")) - node T_4012 = mux(T_3816, tgts.T_3888.data, UInt<1>("h0")) - node T_4014 = mux(T_3817, tgts.T_3890.data, UInt<1>("h0")) - node T_4016 = mux(T_3818, tgts.T_3892.data, UInt<1>("h0")) - node T_4018 = mux(T_3819, tgts.T_3894.data, UInt<1>("h0")) - node T_4020 = mux(T_3820, tgts.T_3896.data, UInt<1>("h0")) - node T_4022 = mux(T_3821, tgts.T_3898.data, UInt<1>("h0")) - node T_4024 = mux(T_3822, tgts.T_3900.data, UInt<1>("h0")) - node T_4026 = mux(T_3823, tgts.T_3902.data, UInt<1>("h0")) - node T_4028 = mux(T_3824, tgts.T_3904.data, UInt<1>("h0")) - node T_4030 = mux(T_3825, tgts.T_3906.data, UInt<1>("h0")) - node T_4032 = mux(T_3826, tgts.T_3908.data, UInt<1>("h0")) - node T_4034 = mux(T_3827, tgts.T_3910.data, UInt<1>("h0")) - node T_4036 = mux(T_3828, tgts.T_3912.data, UInt<1>("h0")) - node T_4038 = mux(T_3829, tgts.T_3914.data, UInt<1>("h0")) - node T_4040 = mux(T_3830, tgts.T_3916.data, UInt<1>("h0")) - node T_4042 = mux(T_3831, tgts.T_3918.data, UInt<1>("h0")) - node T_4044 = mux(T_3832, tgts.T_3920.data, UInt<1>("h0")) - node T_4046 = mux(T_3833, tgts.T_3922.data, UInt<1>("h0")) - node T_4048 = mux(T_3834, tgts.T_3924.data, UInt<1>("h0")) - node T_4050 = mux(T_3835, tgts.T_3926.data, UInt<1>("h0")) - node T_4052 = mux(T_3836, tgts.T_3928.data, UInt<1>("h0")) - node T_4054 = mux(T_3837, tgts.T_3930.data, UInt<1>("h0")) - node T_4056 = mux(T_3838, tgts.T_3932.data, UInt<1>("h0")) - node T_4058 = mux(T_3839, tgts.T_3934.data, UInt<1>("h0")) - node T_4060 = mux(T_3840, tgts.T_3936.data, UInt<1>("h0")) - node T_4062 = mux(T_3841, tgts.T_3938.data, UInt<1>("h0")) - node T_4064 = mux(T_3842, tgts.T_3940.data, UInt<1>("h0")) - node T_4066 = mux(T_3843, tgts.T_3942.data, UInt<1>("h0")) - node T_4068 = mux(T_3844, tgts.T_3944.data, UInt<1>("h0")) - node T_4070 = mux(T_3845, tgts.T_3946.data, UInt<1>("h0")) - node T_4072 = mux(T_3846, tgts.T_3948.data, UInt<1>("h0")) - node T_4074 = mux(T_3847, tgts.T_3950.data, UInt<1>("h0")) - node T_4076 = mux(T_3848, tgts.T_3952.data, UInt<1>("h0")) - node T_4078 = mux(T_3849, tgts.T_3954.data, UInt<1>("h0")) - node T_4080 = mux(T_3850, tgts.T_3956.data, UInt<1>("h0")) - node T_4082 = mux(T_3851, tgts.T_3958.data, UInt<1>("h0")) - node T_4084 = mux(T_3852, tgts.T_3960.data, UInt<1>("h0")) - node T_4086 = mux(T_3853, tgts.T_3962.data, UInt<1>("h0")) - node T_4088 = mux(T_3854, tgts.T_3964.data, UInt<1>("h0")) - node T_4090 = mux(T_3855, tgts.T_3966.data, UInt<1>("h0")) - node T_4092 = mux(T_3856, tgts.T_3968.data, UInt<1>("h0")) - node T_4094 = mux(T_3857, tgts.T_3970.data, UInt<1>("h0")) - node T_4096 = mux(T_3858, tgts.T_3972.data, UInt<1>("h0")) - node T_4098 = mux(T_3859, tgts.T_3974.data, UInt<1>("h0")) - node T_4100 = mux(T_3860, tgts.T_3976.data, UInt<1>("h0")) - node T_4102 = mux(T_3861, tgts.T_3978.data, UInt<1>("h0")) - node T_4104 = mux(T_3862, tgts.T_3980.data, UInt<1>("h0")) - node T_4106 = mux(T_3863, tgts.T_3982.data, UInt<1>("h0")) - node T_4108 = mux(T_3864, tgts.T_3984.data, UInt<1>("h0")) - node T_4110 = mux(T_3865, tgts.T_3986.data, UInt<1>("h0")) - node T_4112 = mux(T_3866, tgts.T_3988.data, UInt<1>("h0")) - node T_4114 = mux(T_3867, tgts.T_3990.data, UInt<1>("h0")) - node T_4116 = mux(T_3868, tgts.T_3992.data, UInt<1>("h0")) - node T_4118 = or(T_3994, T_3996) - node T_4119 = or(T_4118, T_3998) - node T_4120 = or(T_4119, T_4000) - node T_4121 = or(T_4120, T_4002) - node T_4122 = or(T_4121, T_4004) - node T_4123 = or(T_4122, T_4006) - node T_4124 = or(T_4123, T_4008) - node T_4125 = or(T_4124, T_4010) - node T_4126 = or(T_4125, T_4012) - node T_4127 = or(T_4126, T_4014) - node T_4128 = or(T_4127, T_4016) - node T_4129 = or(T_4128, T_4018) - node T_4130 = or(T_4129, T_4020) - node T_4131 = or(T_4130, T_4022) - node T_4132 = or(T_4131, T_4024) - node T_4133 = or(T_4132, T_4026) - node T_4134 = or(T_4133, T_4028) - node T_4135 = or(T_4134, T_4030) - node T_4136 = or(T_4135, T_4032) - node T_4137 = or(T_4136, T_4034) - node T_4138 = or(T_4137, T_4036) - node T_4139 = or(T_4138, T_4038) - node T_4140 = or(T_4139, T_4040) - node T_4141 = or(T_4140, T_4042) - node T_4142 = or(T_4141, T_4044) - node T_4143 = or(T_4142, T_4046) - node T_4144 = or(T_4143, T_4048) - node T_4145 = or(T_4144, T_4050) - node T_4146 = or(T_4145, T_4052) - node T_4147 = or(T_4146, T_4054) - node T_4148 = or(T_4147, T_4056) - node T_4149 = or(T_4148, T_4058) - node T_4150 = or(T_4149, T_4060) - node T_4151 = or(T_4150, T_4062) - node T_4152 = or(T_4151, T_4064) - node T_4153 = or(T_4152, T_4066) - node T_4154 = or(T_4153, T_4068) - node T_4155 = or(T_4154, T_4070) - node T_4156 = or(T_4155, T_4072) - node T_4157 = or(T_4156, T_4074) - node T_4158 = or(T_4157, T_4076) - node T_4159 = or(T_4158, T_4078) - node T_4160 = or(T_4159, T_4080) - node T_4161 = or(T_4160, T_4082) - node T_4162 = or(T_4161, T_4084) - node T_4163 = or(T_4162, T_4086) - node T_4164 = or(T_4163, T_4088) - node T_4165 = or(T_4164, T_4090) - node T_4166 = or(T_4165, T_4092) - node T_4167 = or(T_4166, T_4094) - node T_4168 = or(T_4167, T_4096) - node T_4169 = or(T_4168, T_4098) - node T_4170 = or(T_4169, T_4100) - node T_4171 = or(T_4170, T_4102) - node T_4172 = or(T_4171, T_4104) - node T_4173 = or(T_4172, T_4106) - node T_4174 = or(T_4173, T_4108) - node T_4175 = or(T_4174, T_4110) - node T_4176 = or(T_4175, T_4112) - node T_4177 = or(T_4176, T_4114) - node T_4178 = or(T_4177, T_4116) - wire T_4179 : UInt<12> - T_4179 is invalid - T_4179 <= T_4178 - node T_4180 = cat(T_3806, T_4179) - io.resp.bits.target <= T_4180 - node T_4181 = bits(hits, 61, 32) - node T_4182 = bits(hits, 31, 0) - node T_4184 = neq(T_4181, UInt<1>("h0")) - node T_4185 = or(T_4181, T_4182) - node T_4186 = bits(T_4185, 31, 16) - node T_4187 = bits(T_4185, 15, 0) - node T_4189 = neq(T_4186, UInt<1>("h0")) - node T_4190 = or(T_4186, T_4187) - node T_4191 = bits(T_4190, 15, 8) - node T_4192 = bits(T_4190, 7, 0) - node T_4194 = neq(T_4191, UInt<1>("h0")) - node T_4195 = or(T_4191, T_4192) - node T_4196 = bits(T_4195, 7, 4) - node T_4197 = bits(T_4195, 3, 0) - node T_4199 = neq(T_4196, UInt<1>("h0")) - node T_4200 = or(T_4196, T_4197) - node T_4201 = bits(T_4200, 3, 2) - node T_4202 = bits(T_4200, 1, 0) - node T_4204 = neq(T_4201, UInt<1>("h0")) - node T_4205 = or(T_4201, T_4202) - node T_4206 = bits(T_4205, 1, 1) - node T_4207 = cat(T_4204, T_4206) - node T_4208 = cat(T_4199, T_4207) - node T_4209 = cat(T_4194, T_4208) - node T_4210 = cat(T_4189, T_4209) - node T_4211 = cat(T_4184, T_4210) - io.resp.bits.entry <= T_4211 - brIdx.T_4212.addr <= io.resp.bits.entry - brIdx.T_4212.en <= UInt<1>("h1") - io.resp.bits.bridx <= brIdx.T_4212.data - io.resp.bits.mask <= UInt<1>("h1") - mem T_4216 : - data-type => UInt<2> - depth => 128 - write-latency => 1 - read-latency => 0 - reader => T_4542 - writer => T_4549 - T_4216.T_4542.addr is invalid - T_4216.T_4542.clk <= clk - T_4216.T_4542.en <= UInt<1>("h0") - T_4216.T_4549.addr is invalid - T_4216.T_4549.clk <= clk - T_4216.T_4549.en <= UInt<1>("h0") - T_4216.T_4549.data is invalid - T_4216.T_4549.mask <= UInt<1>("h0") - reg T_4218 : UInt<7>, clk with : - reset => (UInt<1>("h0"), T_4218) - node T_4219 = bits(hits, 0, 0) - node T_4220 = bits(hits, 1, 1) - node T_4221 = bits(hits, 2, 2) - node T_4222 = bits(hits, 3, 3) - node T_4223 = bits(hits, 4, 4) - node T_4224 = bits(hits, 5, 5) - node T_4225 = bits(hits, 6, 6) - node T_4226 = bits(hits, 7, 7) - node T_4227 = bits(hits, 8, 8) - node T_4228 = bits(hits, 9, 9) - node T_4229 = bits(hits, 10, 10) - node T_4230 = bits(hits, 11, 11) - node T_4231 = bits(hits, 12, 12) - node T_4232 = bits(hits, 13, 13) - node T_4233 = bits(hits, 14, 14) - node T_4234 = bits(hits, 15, 15) - node T_4235 = bits(hits, 16, 16) - node T_4236 = bits(hits, 17, 17) - node T_4237 = bits(hits, 18, 18) - node T_4238 = bits(hits, 19, 19) - node T_4239 = bits(hits, 20, 20) - node T_4240 = bits(hits, 21, 21) - node T_4241 = bits(hits, 22, 22) - node T_4242 = bits(hits, 23, 23) - node T_4243 = bits(hits, 24, 24) - node T_4244 = bits(hits, 25, 25) - node T_4245 = bits(hits, 26, 26) - node T_4246 = bits(hits, 27, 27) - node T_4247 = bits(hits, 28, 28) - node T_4248 = bits(hits, 29, 29) - node T_4249 = bits(hits, 30, 30) - node T_4250 = bits(hits, 31, 31) - node T_4251 = bits(hits, 32, 32) - node T_4252 = bits(hits, 33, 33) - node T_4253 = bits(hits, 34, 34) - node T_4254 = bits(hits, 35, 35) - node T_4255 = bits(hits, 36, 36) - node T_4256 = bits(hits, 37, 37) - node T_4257 = bits(hits, 38, 38) - node T_4258 = bits(hits, 39, 39) - node T_4259 = bits(hits, 40, 40) - node T_4260 = bits(hits, 41, 41) - node T_4261 = bits(hits, 42, 42) - node T_4262 = bits(hits, 43, 43) - node T_4263 = bits(hits, 44, 44) - node T_4264 = bits(hits, 45, 45) - node T_4265 = bits(hits, 46, 46) - node T_4266 = bits(hits, 47, 47) - node T_4267 = bits(hits, 48, 48) - node T_4268 = bits(hits, 49, 49) - node T_4269 = bits(hits, 50, 50) - node T_4270 = bits(hits, 51, 51) - node T_4271 = bits(hits, 52, 52) - node T_4272 = bits(hits, 53, 53) - node T_4273 = bits(hits, 54, 54) - node T_4274 = bits(hits, 55, 55) - node T_4275 = bits(hits, 56, 56) - node T_4276 = bits(hits, 57, 57) - node T_4277 = bits(hits, 58, 58) - node T_4278 = bits(hits, 59, 59) - node T_4279 = bits(hits, 60, 60) - node T_4280 = bits(hits, 61, 61) - node T_4282 = shl(isJump[0], 0) - node T_4283 = mux(T_4219, T_4282, UInt<1>("h0")) - node T_4285 = shl(isJump[1], 0) - node T_4286 = mux(T_4220, T_4285, UInt<1>("h0")) - node T_4288 = shl(isJump[2], 0) - node T_4289 = mux(T_4221, T_4288, UInt<1>("h0")) - node T_4291 = shl(isJump[3], 0) - node T_4292 = mux(T_4222, T_4291, UInt<1>("h0")) - node T_4294 = shl(isJump[4], 0) - node T_4295 = mux(T_4223, T_4294, UInt<1>("h0")) - node T_4297 = shl(isJump[5], 0) - node T_4298 = mux(T_4224, T_4297, UInt<1>("h0")) - node T_4300 = shl(isJump[6], 0) - node T_4301 = mux(T_4225, T_4300, UInt<1>("h0")) - node T_4303 = shl(isJump[7], 0) - node T_4304 = mux(T_4226, T_4303, UInt<1>("h0")) - node T_4306 = shl(isJump[8], 0) - node T_4307 = mux(T_4227, T_4306, UInt<1>("h0")) - node T_4309 = shl(isJump[9], 0) - node T_4310 = mux(T_4228, T_4309, UInt<1>("h0")) - node T_4312 = shl(isJump[10], 0) - node T_4313 = mux(T_4229, T_4312, UInt<1>("h0")) - node T_4315 = shl(isJump[11], 0) - node T_4316 = mux(T_4230, T_4315, UInt<1>("h0")) - node T_4318 = shl(isJump[12], 0) - node T_4319 = mux(T_4231, T_4318, UInt<1>("h0")) - node T_4321 = shl(isJump[13], 0) - node T_4322 = mux(T_4232, T_4321, UInt<1>("h0")) - node T_4324 = shl(isJump[14], 0) - node T_4325 = mux(T_4233, T_4324, UInt<1>("h0")) - node T_4327 = shl(isJump[15], 0) - node T_4328 = mux(T_4234, T_4327, UInt<1>("h0")) - node T_4330 = shl(isJump[16], 0) - node T_4331 = mux(T_4235, T_4330, UInt<1>("h0")) - node T_4333 = shl(isJump[17], 0) - node T_4334 = mux(T_4236, T_4333, UInt<1>("h0")) - node T_4336 = shl(isJump[18], 0) - node T_4337 = mux(T_4237, T_4336, UInt<1>("h0")) - node T_4339 = shl(isJump[19], 0) - node T_4340 = mux(T_4238, T_4339, UInt<1>("h0")) - node T_4342 = shl(isJump[20], 0) - node T_4343 = mux(T_4239, T_4342, UInt<1>("h0")) - node T_4345 = shl(isJump[21], 0) - node T_4346 = mux(T_4240, T_4345, UInt<1>("h0")) - node T_4348 = shl(isJump[22], 0) - node T_4349 = mux(T_4241, T_4348, UInt<1>("h0")) - node T_4351 = shl(isJump[23], 0) - node T_4352 = mux(T_4242, T_4351, UInt<1>("h0")) - node T_4354 = shl(isJump[24], 0) - node T_4355 = mux(T_4243, T_4354, UInt<1>("h0")) - node T_4357 = shl(isJump[25], 0) - node T_4358 = mux(T_4244, T_4357, UInt<1>("h0")) - node T_4360 = shl(isJump[26], 0) - node T_4361 = mux(T_4245, T_4360, UInt<1>("h0")) - node T_4363 = shl(isJump[27], 0) - node T_4364 = mux(T_4246, T_4363, UInt<1>("h0")) - node T_4366 = shl(isJump[28], 0) - node T_4367 = mux(T_4247, T_4366, UInt<1>("h0")) - node T_4369 = shl(isJump[29], 0) - node T_4370 = mux(T_4248, T_4369, UInt<1>("h0")) - node T_4372 = shl(isJump[30], 0) - node T_4373 = mux(T_4249, T_4372, UInt<1>("h0")) - node T_4375 = shl(isJump[31], 0) - node T_4376 = mux(T_4250, T_4375, UInt<1>("h0")) - node T_4378 = shl(isJump[32], 0) - node T_4379 = mux(T_4251, T_4378, UInt<1>("h0")) - node T_4381 = shl(isJump[33], 0) - node T_4382 = mux(T_4252, T_4381, UInt<1>("h0")) - node T_4384 = shl(isJump[34], 0) - node T_4385 = mux(T_4253, T_4384, UInt<1>("h0")) - node T_4387 = shl(isJump[35], 0) - node T_4388 = mux(T_4254, T_4387, UInt<1>("h0")) - node T_4390 = shl(isJump[36], 0) - node T_4391 = mux(T_4255, T_4390, UInt<1>("h0")) - node T_4393 = shl(isJump[37], 0) - node T_4394 = mux(T_4256, T_4393, UInt<1>("h0")) - node T_4396 = shl(isJump[38], 0) - node T_4397 = mux(T_4257, T_4396, UInt<1>("h0")) - node T_4399 = shl(isJump[39], 0) - node T_4400 = mux(T_4258, T_4399, UInt<1>("h0")) - node T_4402 = shl(isJump[40], 0) - node T_4403 = mux(T_4259, T_4402, UInt<1>("h0")) - node T_4405 = shl(isJump[41], 0) - node T_4406 = mux(T_4260, T_4405, UInt<1>("h0")) - node T_4408 = shl(isJump[42], 0) - node T_4409 = mux(T_4261, T_4408, UInt<1>("h0")) - node T_4411 = shl(isJump[43], 0) - node T_4412 = mux(T_4262, T_4411, UInt<1>("h0")) - node T_4414 = shl(isJump[44], 0) - node T_4415 = mux(T_4263, T_4414, UInt<1>("h0")) - node T_4417 = shl(isJump[45], 0) - node T_4418 = mux(T_4264, T_4417, UInt<1>("h0")) - node T_4420 = shl(isJump[46], 0) - node T_4421 = mux(T_4265, T_4420, UInt<1>("h0")) - node T_4423 = shl(isJump[47], 0) - node T_4424 = mux(T_4266, T_4423, UInt<1>("h0")) - node T_4426 = shl(isJump[48], 0) - node T_4427 = mux(T_4267, T_4426, UInt<1>("h0")) - node T_4429 = shl(isJump[49], 0) - node T_4430 = mux(T_4268, T_4429, UInt<1>("h0")) - node T_4432 = shl(isJump[50], 0) - node T_4433 = mux(T_4269, T_4432, UInt<1>("h0")) - node T_4435 = shl(isJump[51], 0) - node T_4436 = mux(T_4270, T_4435, UInt<1>("h0")) - node T_4438 = shl(isJump[52], 0) - node T_4439 = mux(T_4271, T_4438, UInt<1>("h0")) - node T_4441 = shl(isJump[53], 0) - node T_4442 = mux(T_4272, T_4441, UInt<1>("h0")) - node T_4444 = shl(isJump[54], 0) - node T_4445 = mux(T_4273, T_4444, UInt<1>("h0")) - node T_4447 = shl(isJump[55], 0) - node T_4448 = mux(T_4274, T_4447, UInt<1>("h0")) - node T_4450 = shl(isJump[56], 0) - node T_4451 = mux(T_4275, T_4450, UInt<1>("h0")) - node T_4453 = shl(isJump[57], 0) - node T_4454 = mux(T_4276, T_4453, UInt<1>("h0")) - node T_4456 = shl(isJump[58], 0) - node T_4457 = mux(T_4277, T_4456, UInt<1>("h0")) - node T_4459 = shl(isJump[59], 0) - node T_4460 = mux(T_4278, T_4459, UInt<1>("h0")) - node T_4462 = shl(isJump[60], 0) - node T_4463 = mux(T_4279, T_4462, UInt<1>("h0")) - node T_4465 = shl(isJump[61], 0) - node T_4466 = mux(T_4280, T_4465, UInt<1>("h0")) - node T_4468 = or(T_4283, T_4286) - node T_4469 = or(T_4468, T_4289) - node T_4470 = or(T_4469, T_4292) - node T_4471 = or(T_4470, T_4295) - node T_4472 = or(T_4471, T_4298) - node T_4473 = or(T_4472, T_4301) - node T_4474 = or(T_4473, T_4304) - node T_4475 = or(T_4474, T_4307) - node T_4476 = or(T_4475, T_4310) - node T_4477 = or(T_4476, T_4313) - node T_4478 = or(T_4477, T_4316) - node T_4479 = or(T_4478, T_4319) - node T_4480 = or(T_4479, T_4322) - node T_4481 = or(T_4480, T_4325) - node T_4482 = or(T_4481, T_4328) - node T_4483 = or(T_4482, T_4331) - node T_4484 = or(T_4483, T_4334) - node T_4485 = or(T_4484, T_4337) - node T_4486 = or(T_4485, T_4340) - node T_4487 = or(T_4486, T_4343) - node T_4488 = or(T_4487, T_4346) - node T_4489 = or(T_4488, T_4349) - node T_4490 = or(T_4489, T_4352) - node T_4491 = or(T_4490, T_4355) - node T_4492 = or(T_4491, T_4358) - node T_4493 = or(T_4492, T_4361) - node T_4494 = or(T_4493, T_4364) - node T_4495 = or(T_4494, T_4367) - node T_4496 = or(T_4495, T_4370) - node T_4497 = or(T_4496, T_4373) - node T_4498 = or(T_4497, T_4376) - node T_4499 = or(T_4498, T_4379) - node T_4500 = or(T_4499, T_4382) - node T_4501 = or(T_4500, T_4385) - node T_4502 = or(T_4501, T_4388) - node T_4503 = or(T_4502, T_4391) - node T_4504 = or(T_4503, T_4394) - node T_4505 = or(T_4504, T_4397) - node T_4506 = or(T_4505, T_4400) - node T_4507 = or(T_4506, T_4403) - node T_4508 = or(T_4507, T_4406) - node T_4509 = or(T_4508, T_4409) - node T_4510 = or(T_4509, T_4412) - node T_4511 = or(T_4510, T_4415) - node T_4512 = or(T_4511, T_4418) - node T_4513 = or(T_4512, T_4421) - node T_4514 = or(T_4513, T_4424) - node T_4515 = or(T_4514, T_4427) - node T_4516 = or(T_4515, T_4430) - node T_4517 = or(T_4516, T_4433) - node T_4518 = or(T_4517, T_4436) - node T_4519 = or(T_4518, T_4439) - node T_4520 = or(T_4519, T_4442) - node T_4521 = or(T_4520, T_4445) - node T_4522 = or(T_4521, T_4448) - node T_4523 = or(T_4522, T_4451) - node T_4524 = or(T_4523, T_4454) - node T_4525 = or(T_4524, T_4457) - node T_4526 = or(T_4525, T_4460) - node T_4527 = or(T_4526, T_4463) - node T_4528 = or(T_4527, T_4466) - wire T_4529 : UInt<1> - T_4529 is invalid - T_4529 <= T_4528 - node T_4531 = eq(T_4529, UInt<1>("h0")) - node T_4532 = and(io.req.valid, io.resp.valid) - node T_4533 = and(T_4532, T_4531) - wire T_4537 : { history : UInt<7>, value : UInt<2>} - T_4537 is invalid - node T_4540 = bits(io.req.bits.addr, 8, 2) - node T_4541 = xor(T_4540, T_4218) - T_4216.T_4542.addr <= T_4541 - T_4216.T_4542.en <= UInt<1>("h1") - T_4537.value <= T_4216.T_4542.data - T_4537.history <= T_4218 - node T_4543 = bits(T_4537.value, 0, 0) - when T_4533 : - node T_4544 = bits(T_4218, 6, 1) - node T_4545 = cat(T_4543, T_4544) - T_4218 <= T_4545 - skip - node T_4546 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) - when T_4546 : - node T_4547 = bits(io.bht_update.bits.pc, 8, 2) - node T_4548 = xor(T_4547, io.bht_update.bits.prediction.bits.bht.history) - T_4216.T_4549.addr <= T_4548 - T_4216.T_4549.en <= UInt<1>("h1") - node T_4550 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) - node T_4551 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) - node T_4552 = and(T_4550, T_4551) - node T_4553 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) - node T_4554 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) - node T_4555 = or(T_4553, T_4554) - node T_4556 = and(T_4555, io.bht_update.bits.taken) - node T_4557 = or(T_4552, T_4556) - node T_4558 = cat(io.bht_update.bits.taken, T_4557) - T_4216.T_4549.data <= T_4558 - T_4216.T_4549.mask <= UInt<1>("h1") - when io.bht_update.bits.mispredict : - node T_4559 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) - node T_4560 = cat(io.bht_update.bits.taken, T_4559) - T_4218 <= T_4560 - skip - skip - node T_4561 = bits(T_4537.value, 0, 0) - node T_4563 = eq(T_4561, UInt<1>("h0")) - node T_4564 = and(T_4563, T_4531) - when T_4564 : - io.resp.bits.taken <= UInt<1>("h0") - skip - io.resp.bits.bht <- T_4537 - reg T_4567 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - reg T_4569 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_4578 : UInt[2], clk with : - reset => (UInt<1>("h0"), T_4578) - node T_4582 = bits(hits, 0, 0) - node T_4583 = bits(hits, 1, 1) - node T_4584 = bits(hits, 2, 2) - node T_4585 = bits(hits, 3, 3) - node T_4586 = bits(hits, 4, 4) - node T_4587 = bits(hits, 5, 5) - node T_4588 = bits(hits, 6, 6) - node T_4589 = bits(hits, 7, 7) - node T_4590 = bits(hits, 8, 8) - node T_4591 = bits(hits, 9, 9) - node T_4592 = bits(hits, 10, 10) - node T_4593 = bits(hits, 11, 11) - node T_4594 = bits(hits, 12, 12) - node T_4595 = bits(hits, 13, 13) - node T_4596 = bits(hits, 14, 14) - node T_4597 = bits(hits, 15, 15) - node T_4598 = bits(hits, 16, 16) - node T_4599 = bits(hits, 17, 17) - node T_4600 = bits(hits, 18, 18) - node T_4601 = bits(hits, 19, 19) - node T_4602 = bits(hits, 20, 20) - node T_4603 = bits(hits, 21, 21) - node T_4604 = bits(hits, 22, 22) - node T_4605 = bits(hits, 23, 23) - node T_4606 = bits(hits, 24, 24) - node T_4607 = bits(hits, 25, 25) - node T_4608 = bits(hits, 26, 26) - node T_4609 = bits(hits, 27, 27) - node T_4610 = bits(hits, 28, 28) - node T_4611 = bits(hits, 29, 29) - node T_4612 = bits(hits, 30, 30) - node T_4613 = bits(hits, 31, 31) - node T_4614 = bits(hits, 32, 32) - node T_4615 = bits(hits, 33, 33) - node T_4616 = bits(hits, 34, 34) - node T_4617 = bits(hits, 35, 35) - node T_4618 = bits(hits, 36, 36) - node T_4619 = bits(hits, 37, 37) - node T_4620 = bits(hits, 38, 38) - node T_4621 = bits(hits, 39, 39) - node T_4622 = bits(hits, 40, 40) - node T_4623 = bits(hits, 41, 41) - node T_4624 = bits(hits, 42, 42) - node T_4625 = bits(hits, 43, 43) - node T_4626 = bits(hits, 44, 44) - node T_4627 = bits(hits, 45, 45) - node T_4628 = bits(hits, 46, 46) - node T_4629 = bits(hits, 47, 47) - node T_4630 = bits(hits, 48, 48) - node T_4631 = bits(hits, 49, 49) - node T_4632 = bits(hits, 50, 50) - node T_4633 = bits(hits, 51, 51) - node T_4634 = bits(hits, 52, 52) - node T_4635 = bits(hits, 53, 53) - node T_4636 = bits(hits, 54, 54) - node T_4637 = bits(hits, 55, 55) - node T_4638 = bits(hits, 56, 56) - node T_4639 = bits(hits, 57, 57) - node T_4640 = bits(hits, 58, 58) - node T_4641 = bits(hits, 59, 59) - node T_4642 = bits(hits, 60, 60) - node T_4643 = bits(hits, 61, 61) - node T_4645 = shl(useRAS[0], 0) - node T_4646 = mux(T_4582, T_4645, UInt<1>("h0")) - node T_4648 = shl(useRAS[1], 0) - node T_4649 = mux(T_4583, T_4648, UInt<1>("h0")) - node T_4651 = shl(useRAS[2], 0) - node T_4652 = mux(T_4584, T_4651, UInt<1>("h0")) - node T_4654 = shl(useRAS[3], 0) - node T_4655 = mux(T_4585, T_4654, UInt<1>("h0")) - node T_4657 = shl(useRAS[4], 0) - node T_4658 = mux(T_4586, T_4657, UInt<1>("h0")) - node T_4660 = shl(useRAS[5], 0) - node T_4661 = mux(T_4587, T_4660, UInt<1>("h0")) - node T_4663 = shl(useRAS[6], 0) - node T_4664 = mux(T_4588, T_4663, UInt<1>("h0")) - node T_4666 = shl(useRAS[7], 0) - node T_4667 = mux(T_4589, T_4666, UInt<1>("h0")) - node T_4669 = shl(useRAS[8], 0) - node T_4670 = mux(T_4590, T_4669, UInt<1>("h0")) - node T_4672 = shl(useRAS[9], 0) - node T_4673 = mux(T_4591, T_4672, UInt<1>("h0")) - node T_4675 = shl(useRAS[10], 0) - node T_4676 = mux(T_4592, T_4675, UInt<1>("h0")) - node T_4678 = shl(useRAS[11], 0) - node T_4679 = mux(T_4593, T_4678, UInt<1>("h0")) - node T_4681 = shl(useRAS[12], 0) - node T_4682 = mux(T_4594, T_4681, UInt<1>("h0")) - node T_4684 = shl(useRAS[13], 0) - node T_4685 = mux(T_4595, T_4684, UInt<1>("h0")) - node T_4687 = shl(useRAS[14], 0) - node T_4688 = mux(T_4596, T_4687, UInt<1>("h0")) - node T_4690 = shl(useRAS[15], 0) - node T_4691 = mux(T_4597, T_4690, UInt<1>("h0")) - node T_4693 = shl(useRAS[16], 0) - node T_4694 = mux(T_4598, T_4693, UInt<1>("h0")) - node T_4696 = shl(useRAS[17], 0) - node T_4697 = mux(T_4599, T_4696, UInt<1>("h0")) - node T_4699 = shl(useRAS[18], 0) - node T_4700 = mux(T_4600, T_4699, UInt<1>("h0")) - node T_4702 = shl(useRAS[19], 0) - node T_4703 = mux(T_4601, T_4702, UInt<1>("h0")) - node T_4705 = shl(useRAS[20], 0) - node T_4706 = mux(T_4602, T_4705, UInt<1>("h0")) - node T_4708 = shl(useRAS[21], 0) - node T_4709 = mux(T_4603, T_4708, UInt<1>("h0")) - node T_4711 = shl(useRAS[22], 0) - node T_4712 = mux(T_4604, T_4711, UInt<1>("h0")) - node T_4714 = shl(useRAS[23], 0) - node T_4715 = mux(T_4605, T_4714, UInt<1>("h0")) - node T_4717 = shl(useRAS[24], 0) - node T_4718 = mux(T_4606, T_4717, UInt<1>("h0")) - node T_4720 = shl(useRAS[25], 0) - node T_4721 = mux(T_4607, T_4720, UInt<1>("h0")) - node T_4723 = shl(useRAS[26], 0) - node T_4724 = mux(T_4608, T_4723, UInt<1>("h0")) - node T_4726 = shl(useRAS[27], 0) - node T_4727 = mux(T_4609, T_4726, UInt<1>("h0")) - node T_4729 = shl(useRAS[28], 0) - node T_4730 = mux(T_4610, T_4729, UInt<1>("h0")) - node T_4732 = shl(useRAS[29], 0) - node T_4733 = mux(T_4611, T_4732, UInt<1>("h0")) - node T_4735 = shl(useRAS[30], 0) - node T_4736 = mux(T_4612, T_4735, UInt<1>("h0")) - node T_4738 = shl(useRAS[31], 0) - node T_4739 = mux(T_4613, T_4738, UInt<1>("h0")) - node T_4741 = shl(useRAS[32], 0) - node T_4742 = mux(T_4614, T_4741, UInt<1>("h0")) - node T_4744 = shl(useRAS[33], 0) - node T_4745 = mux(T_4615, T_4744, UInt<1>("h0")) - node T_4747 = shl(useRAS[34], 0) - node T_4748 = mux(T_4616, T_4747, UInt<1>("h0")) - node T_4750 = shl(useRAS[35], 0) - node T_4751 = mux(T_4617, T_4750, UInt<1>("h0")) - node T_4753 = shl(useRAS[36], 0) - node T_4754 = mux(T_4618, T_4753, UInt<1>("h0")) - node T_4756 = shl(useRAS[37], 0) - node T_4757 = mux(T_4619, T_4756, UInt<1>("h0")) - node T_4759 = shl(useRAS[38], 0) - node T_4760 = mux(T_4620, T_4759, UInt<1>("h0")) - node T_4762 = shl(useRAS[39], 0) - node T_4763 = mux(T_4621, T_4762, UInt<1>("h0")) - node T_4765 = shl(useRAS[40], 0) - node T_4766 = mux(T_4622, T_4765, UInt<1>("h0")) - node T_4768 = shl(useRAS[41], 0) - node T_4769 = mux(T_4623, T_4768, UInt<1>("h0")) - node T_4771 = shl(useRAS[42], 0) - node T_4772 = mux(T_4624, T_4771, UInt<1>("h0")) - node T_4774 = shl(useRAS[43], 0) - node T_4775 = mux(T_4625, T_4774, UInt<1>("h0")) - node T_4777 = shl(useRAS[44], 0) - node T_4778 = mux(T_4626, T_4777, UInt<1>("h0")) - node T_4780 = shl(useRAS[45], 0) - node T_4781 = mux(T_4627, T_4780, UInt<1>("h0")) - node T_4783 = shl(useRAS[46], 0) - node T_4784 = mux(T_4628, T_4783, UInt<1>("h0")) - node T_4786 = shl(useRAS[47], 0) - node T_4787 = mux(T_4629, T_4786, UInt<1>("h0")) - node T_4789 = shl(useRAS[48], 0) - node T_4790 = mux(T_4630, T_4789, UInt<1>("h0")) - node T_4792 = shl(useRAS[49], 0) - node T_4793 = mux(T_4631, T_4792, UInt<1>("h0")) - node T_4795 = shl(useRAS[50], 0) - node T_4796 = mux(T_4632, T_4795, UInt<1>("h0")) - node T_4798 = shl(useRAS[51], 0) - node T_4799 = mux(T_4633, T_4798, UInt<1>("h0")) - node T_4801 = shl(useRAS[52], 0) - node T_4802 = mux(T_4634, T_4801, UInt<1>("h0")) - node T_4804 = shl(useRAS[53], 0) - node T_4805 = mux(T_4635, T_4804, UInt<1>("h0")) - node T_4807 = shl(useRAS[54], 0) - node T_4808 = mux(T_4636, T_4807, UInt<1>("h0")) - node T_4810 = shl(useRAS[55], 0) - node T_4811 = mux(T_4637, T_4810, UInt<1>("h0")) - node T_4813 = shl(useRAS[56], 0) - node T_4814 = mux(T_4638, T_4813, UInt<1>("h0")) - node T_4816 = shl(useRAS[57], 0) - node T_4817 = mux(T_4639, T_4816, UInt<1>("h0")) - node T_4819 = shl(useRAS[58], 0) - node T_4820 = mux(T_4640, T_4819, UInt<1>("h0")) - node T_4822 = shl(useRAS[59], 0) - node T_4823 = mux(T_4641, T_4822, UInt<1>("h0")) - node T_4825 = shl(useRAS[60], 0) - node T_4826 = mux(T_4642, T_4825, UInt<1>("h0")) - node T_4828 = shl(useRAS[61], 0) - node T_4829 = mux(T_4643, T_4828, UInt<1>("h0")) - node T_4831 = or(T_4646, T_4649) - node T_4832 = or(T_4831, T_4652) - node T_4833 = or(T_4832, T_4655) - node T_4834 = or(T_4833, T_4658) - node T_4835 = or(T_4834, T_4661) - node T_4836 = or(T_4835, T_4664) - node T_4837 = or(T_4836, T_4667) - node T_4838 = or(T_4837, T_4670) - node T_4839 = or(T_4838, T_4673) - node T_4840 = or(T_4839, T_4676) - node T_4841 = or(T_4840, T_4679) - node T_4842 = or(T_4841, T_4682) - node T_4843 = or(T_4842, T_4685) - node T_4844 = or(T_4843, T_4688) - node T_4845 = or(T_4844, T_4691) - node T_4846 = or(T_4845, T_4694) - node T_4847 = or(T_4846, T_4697) - node T_4848 = or(T_4847, T_4700) - node T_4849 = or(T_4848, T_4703) - node T_4850 = or(T_4849, T_4706) - node T_4851 = or(T_4850, T_4709) - node T_4852 = or(T_4851, T_4712) - node T_4853 = or(T_4852, T_4715) - node T_4854 = or(T_4853, T_4718) - node T_4855 = or(T_4854, T_4721) - node T_4856 = or(T_4855, T_4724) - node T_4857 = or(T_4856, T_4727) - node T_4858 = or(T_4857, T_4730) - node T_4859 = or(T_4858, T_4733) - node T_4860 = or(T_4859, T_4736) - node T_4861 = or(T_4860, T_4739) - node T_4862 = or(T_4861, T_4742) - node T_4863 = or(T_4862, T_4745) - node T_4864 = or(T_4863, T_4748) - node T_4865 = or(T_4864, T_4751) - node T_4866 = or(T_4865, T_4754) - node T_4867 = or(T_4866, T_4757) - node T_4868 = or(T_4867, T_4760) - node T_4869 = or(T_4868, T_4763) - node T_4870 = or(T_4869, T_4766) - node T_4871 = or(T_4870, T_4769) - node T_4872 = or(T_4871, T_4772) - node T_4873 = or(T_4872, T_4775) - node T_4874 = or(T_4873, T_4778) - node T_4875 = or(T_4874, T_4781) - node T_4876 = or(T_4875, T_4784) - node T_4877 = or(T_4876, T_4787) - node T_4878 = or(T_4877, T_4790) - node T_4879 = or(T_4878, T_4793) - node T_4880 = or(T_4879, T_4796) - node T_4881 = or(T_4880, T_4799) - node T_4882 = or(T_4881, T_4802) - node T_4883 = or(T_4882, T_4805) - node T_4884 = or(T_4883, T_4808) - node T_4885 = or(T_4884, T_4811) - node T_4886 = or(T_4885, T_4814) - node T_4887 = or(T_4886, T_4817) - node T_4888 = or(T_4887, T_4820) - node T_4889 = or(T_4888, T_4823) - node T_4890 = or(T_4889, T_4826) - node T_4891 = or(T_4890, T_4829) - wire T_4892 : UInt<1> - T_4892 is invalid - T_4892 <= T_4891 - node T_4894 = eq(T_4567, UInt<1>("h0")) - node T_4896 = eq(T_4894, UInt<1>("h0")) - node T_4897 = and(T_4896, T_4892) - when T_4897 : - io.resp.bits.target <= T_4578[T_4569] - skip - when io.ras_update.valid : - when io.ras_update.bits.isCall : - node T_4900 = lt(T_4567, UInt<2>("h2")) - when T_4900 : - node T_4902 = add(T_4567, UInt<1>("h1")) - node T_4903 = tail(T_4902, 1) - T_4567 <= T_4903 - skip - node T_4906 = lt(T_4569, UInt<1>("h1")) - node T_4907 = or(UInt<1>("h1"), T_4906) - node T_4909 = add(T_4569, UInt<1>("h1")) - node T_4910 = tail(T_4909, 1) - node T_4912 = mux(T_4907, T_4910, UInt<1>("h0")) - T_4578[T_4912] <= io.ras_update.bits.returnAddr - T_4569 <= T_4912 - when T_4892 : - io.resp.bits.target <= io.ras_update.bits.returnAddr - skip - skip - node T_4914 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) - node T_4916 = eq(io.ras_update.bits.isCall, UInt<1>("h0")) - node T_4917 = and(T_4916, T_4914) - when T_4917 : - node T_4919 = eq(T_4567, UInt<1>("h0")) - node T_4921 = eq(T_4919, UInt<1>("h0")) - when T_4921 : - node T_4923 = sub(T_4567, UInt<1>("h1")) - node T_4924 = tail(T_4923, 1) - T_4567 <= T_4924 - node T_4927 = gt(T_4569, UInt<1>("h0")) - node T_4928 = or(UInt<1>("h1"), T_4927) - node T_4930 = sub(T_4569, UInt<1>("h1")) - node T_4931 = tail(T_4930, 1) - node T_4933 = mux(T_4928, T_4931, UInt<1>("h1")) - T_4569 <= T_4933 - skip - skip - skip - when io.invalidate : - T_4567 <= UInt<1>("h0") - skip - module FlowThroughSerializer : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, cnt : UInt<1>, done : UInt<1>} - io is invalid - io.out <- io.in - io.cnt <= UInt<1>("h0") - io.done <= UInt<1>("h1") - module ICache : - input clk : Clock - input reset : UInt<1> - output io : {flip req : { valid : UInt<1>, bits : { idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg invalidated : UInt<1>, clk with : - reset => (UInt<1>("h0"), invalidated) - node stall = eq(io.resp.ready, UInt<1>("h0")) - wire rdy : UInt<1> - rdy is invalid - reg refill_addr : UInt<32>, clk with : - reset => (UInt<1>("h0"), refill_addr) - wire s1_any_tag_hit : UInt<1> - s1_any_tag_hit is invalid - reg s1_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg s1_pgoff : UInt<12>, clk with : - reset => (UInt<1>("h0"), s1_pgoff) - node s1_addr = cat(io.req.bits.ppn, s1_pgoff) - node s1_tag = bits(s1_addr, 31, 12) - node T_523 = and(s1_valid, stall) - node s0_valid = or(io.req.valid, T_523) - node T_525 = and(s1_valid, stall) - node s0_pgoff = mux(T_525, s1_pgoff, io.req.bits.idx) - node T_527 = and(io.req.valid, rdy) - node T_528 = and(s1_valid, stall) - node T_530 = eq(io.req.bits.kill, UInt<1>("h0")) - node T_531 = and(T_528, T_530) - node T_532 = or(T_527, T_531) - s1_valid <= T_532 - node T_533 = and(io.req.valid, rdy) - when T_533 : - s1_pgoff <= io.req.bits.idx - skip - node T_535 = eq(io.req.bits.kill, UInt<1>("h0")) - node T_536 = and(s1_valid, T_535) - node T_537 = eq(state, UInt<1>("h0")) - node out_valid = and(T_536, T_537) - node s1_idx = bits(s1_addr, 11, 6) - node s1_offset = bits(s1_addr, 5, 0) - node s1_hit = and(out_valid, s1_any_tag_hit) - node T_543 = eq(s1_any_tag_hit, UInt<1>("h0")) - node s1_miss = and(out_valid, T_543) - node T_545 = eq(state, UInt<1>("h0")) - node T_547 = eq(s1_miss, UInt<1>("h0")) - node T_548 = and(T_545, T_547) - rdy <= T_548 - node T_549 = eq(state, UInt<1>("h0")) - node T_550 = and(s1_valid, T_549) - node T_551 = and(T_550, s1_miss) - when T_551 : - refill_addr <= s1_addr - skip - node refill_tag = bits(refill_addr, 31, 12) - inst T_553 of FlowThroughSerializer - T_553.io is invalid - T_553.clk <= clk - T_553.reset <= reset - T_553.io.in.valid <= io.mem.grant.valid - T_553.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_553.io.in.ready - node T_554 = and(T_553.io.out.ready, T_553.io.out.valid) - reg refill_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_554 : - node T_558 = eq(refill_cnt, UInt<2>("h3")) - node T_560 = and(UInt<1>("h0"), T_558) - node T_563 = add(refill_cnt, UInt<1>("h1")) - node T_564 = tail(T_563, 1) - node T_565 = mux(T_560, UInt<1>("h0"), T_564) - refill_cnt <= T_565 - skip - node refill_wrap = and(T_554, T_558) - node T_567 = eq(state, UInt<2>("h3")) - node refill_done = and(T_567, refill_wrap) - T_553.io.out.ready <= UInt<1>("h1") - reg T_571 : UInt<16>, clk with : - reset => (reset, UInt<16>("h1")) - when s1_miss : - node T_572 = bits(T_571, 0, 0) - node T_573 = bits(T_571, 2, 2) - node T_574 = xor(T_572, T_573) - node T_575 = bits(T_571, 3, 3) - node T_576 = xor(T_574, T_575) - node T_577 = bits(T_571, 5, 5) - node T_578 = xor(T_576, T_577) - node T_579 = bits(T_571, 15, 1) - node T_580 = cat(T_578, T_579) - T_571 <= T_580 - skip - node repl_way = bits(T_571, 1, 0) - mem tag_array : - data-type => UInt<20>[4] - depth => 64 - write-latency => 1 - read-latency => 1 - reader => tag_rdata - writer => T_637 - tag_array.tag_rdata.addr is invalid - tag_array.tag_rdata.clk <= clk - tag_array.tag_rdata.en <= UInt<1>("h0") - tag_array.T_637.addr is invalid - tag_array.T_637.clk <= clk - tag_array.T_637.en <= UInt<1>("h0") - tag_array.T_637.data is invalid - tag_array.T_637.mask[0] <= UInt<1>("h0") - tag_array.T_637.mask[1] <= UInt<1>("h0") - tag_array.T_637.mask[2] <= UInt<1>("h0") - tag_array.T_637.mask[3] <= UInt<1>("h0") - node T_599 = bits(s0_pgoff, 11, 6) - node T_601 = eq(refill_done, UInt<1>("h0")) - node T_602 = and(T_601, s0_valid) - wire T_604 : UInt - T_604 is invalid - when T_602 : - T_604 <= T_599 - skip - tag_array.tag_rdata.addr <= T_604 - tag_array.tag_rdata.en <= UInt<1>("h1") - when refill_done : - wire T_614 : UInt<20>[4] - T_614[0] <= refill_tag - T_614[1] <= refill_tag - T_614[2] <= refill_tag - T_614[3] <= refill_tag - node T_621 = eq(repl_way, UInt<1>("h0")) - node T_623 = eq(repl_way, UInt<1>("h1")) - node T_625 = eq(repl_way, UInt<2>("h2")) - node T_627 = eq(repl_way, UInt<2>("h3")) - wire T_629 : UInt<1>[4] - T_629[0] <= T_621 - T_629[1] <= T_623 - T_629[2] <= T_625 - T_629[3] <= T_627 - tag_array.T_637.addr <= s1_idx - tag_array.T_637.en <= UInt<1>("h1") - when T_629[0] : - tag_array.T_637.data[0] <= T_614[0] - tag_array.T_637.mask[0] <= UInt<1>("h1") - skip - when T_629[1] : - tag_array.T_637.data[1] <= T_614[1] - tag_array.T_637.mask[1] <= UInt<1>("h1") - skip - when T_629[2] : - tag_array.T_637.data[2] <= T_614[2] - tag_array.T_637.mask[2] <= UInt<1>("h1") - skip - when T_629[3] : - tag_array.T_637.data[3] <= T_614[3] - tag_array.T_637.mask[3] <= UInt<1>("h1") - skip - skip - reg vb_array : UInt<256>, clk with : - reset => (reset, UInt<256>("h0")) - node T_646 = eq(invalidated, UInt<1>("h0")) - node T_647 = and(refill_done, T_646) - when T_647 : - node T_648 = cat(repl_way, s1_idx) - node T_651 = dshl(UInt<1>("h1"), T_648) - node T_652 = or(vb_array, T_651) - node T_653 = not(vb_array) - node T_654 = or(T_653, T_651) - node T_655 = not(T_654) - node T_656 = mux(UInt<1>("h1"), T_652, T_655) - vb_array <= T_656 - skip - when io.invalidate : - vb_array <= UInt<1>("h0") - invalidated <= UInt<1>("h1") - skip - wire s1_disparity : UInt<1>[4] - s1_disparity is invalid - node T_675 = and(s1_valid, s1_disparity[0]) - when T_675 : - node T_677 = cat(UInt<1>("h0"), s1_idx) - node T_680 = dshl(UInt<1>("h1"), T_677) - node T_681 = or(vb_array, T_680) - node T_682 = not(vb_array) - node T_683 = or(T_682, T_680) - node T_684 = not(T_683) - node T_685 = mux(UInt<1>("h0"), T_681, T_684) - vb_array <= T_685 - skip - node T_686 = and(s1_valid, s1_disparity[1]) - when T_686 : - node T_688 = cat(UInt<1>("h1"), s1_idx) - node T_691 = dshl(UInt<1>("h1"), T_688) - node T_692 = or(vb_array, T_691) - node T_693 = not(vb_array) - node T_694 = or(T_693, T_691) - node T_695 = not(T_694) - node T_696 = mux(UInt<1>("h0"), T_692, T_695) - vb_array <= T_696 - skip - node T_697 = and(s1_valid, s1_disparity[2]) - when T_697 : - node T_699 = cat(UInt<2>("h2"), s1_idx) - node T_702 = dshl(UInt<1>("h1"), T_699) - node T_703 = or(vb_array, T_702) - node T_704 = not(vb_array) - node T_705 = or(T_704, T_702) - node T_706 = not(T_705) - node T_707 = mux(UInt<1>("h0"), T_703, T_706) - vb_array <= T_707 - skip - node T_708 = and(s1_valid, s1_disparity[3]) - when T_708 : - node T_710 = cat(UInt<2>("h3"), s1_idx) - node T_713 = dshl(UInt<1>("h1"), T_710) - node T_714 = or(vb_array, T_713) - node T_715 = not(vb_array) - node T_716 = or(T_715, T_713) - node T_717 = not(T_716) - node T_718 = mux(UInt<1>("h0"), T_714, T_717) - vb_array <= T_718 - skip - wire s1_tag_match : UInt<1>[4] - s1_tag_match is invalid - wire s1_tag_hit : UInt<1>[4] - s1_tag_hit is invalid - wire s1_dout : UInt<128>[4] - s1_dout is invalid - node T_768 = eq(io.invalidate, UInt<1>("h0")) - node T_770 = bits(s1_pgoff, 11, 6) - node T_771 = cat(UInt<1>("h0"), T_770) - node T_772 = dshr(vb_array, T_771) - node T_773 = bits(T_772, 0, 0) - node T_774 = bits(T_773, 0, 0) - node T_775 = and(T_768, T_774) - node T_778 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_779 = and(s1_valid, rdy) - node T_781 = eq(stall, UInt<1>("h0")) - node T_782 = and(T_779, T_781) - when T_782 : - skip - node T_783 = bits(tag_array.tag_rdata.data[0], 19, 0) - node T_784 = eq(T_783, s1_tag) - s1_tag_match[0] <= T_784 - node T_785 = and(T_775, s1_tag_match[0]) - s1_tag_hit[0] <= T_785 - node T_788 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_789 = or(T_778, T_788) - node T_790 = and(T_775, T_789) - s1_disparity[0] <= T_790 - node T_792 = eq(io.invalidate, UInt<1>("h0")) - node T_794 = bits(s1_pgoff, 11, 6) - node T_795 = cat(UInt<1>("h1"), T_794) - node T_796 = dshr(vb_array, T_795) - node T_797 = bits(T_796, 0, 0) - node T_798 = bits(T_797, 0, 0) - node T_799 = and(T_792, T_798) - node T_802 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_803 = and(s1_valid, rdy) - node T_805 = eq(stall, UInt<1>("h0")) - node T_806 = and(T_803, T_805) - when T_806 : - skip - node T_807 = bits(tag_array.tag_rdata.data[1], 19, 0) - node T_808 = eq(T_807, s1_tag) - s1_tag_match[1] <= T_808 - node T_809 = and(T_799, s1_tag_match[1]) - s1_tag_hit[1] <= T_809 - node T_812 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_813 = or(T_802, T_812) - node T_814 = and(T_799, T_813) - s1_disparity[1] <= T_814 - node T_816 = eq(io.invalidate, UInt<1>("h0")) - node T_818 = bits(s1_pgoff, 11, 6) - node T_819 = cat(UInt<2>("h2"), T_818) - node T_820 = dshr(vb_array, T_819) - node T_821 = bits(T_820, 0, 0) - node T_822 = bits(T_821, 0, 0) - node T_823 = and(T_816, T_822) - node T_826 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_827 = and(s1_valid, rdy) - node T_829 = eq(stall, UInt<1>("h0")) - node T_830 = and(T_827, T_829) - when T_830 : - skip - node T_831 = bits(tag_array.tag_rdata.data[2], 19, 0) - node T_832 = eq(T_831, s1_tag) - s1_tag_match[2] <= T_832 - node T_833 = and(T_823, s1_tag_match[2]) - s1_tag_hit[2] <= T_833 - node T_836 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_837 = or(T_826, T_836) - node T_838 = and(T_823, T_837) - s1_disparity[2] <= T_838 - node T_840 = eq(io.invalidate, UInt<1>("h0")) - node T_842 = bits(s1_pgoff, 11, 6) - node T_843 = cat(UInt<2>("h3"), T_842) - node T_844 = dshr(vb_array, T_843) - node T_845 = bits(T_844, 0, 0) - node T_846 = bits(T_845, 0, 0) - node T_847 = and(T_840, T_846) - node T_850 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_851 = and(s1_valid, rdy) - node T_853 = eq(stall, UInt<1>("h0")) - node T_854 = and(T_851, T_853) - when T_854 : - skip - node T_855 = bits(tag_array.tag_rdata.data[3], 19, 0) - node T_856 = eq(T_855, s1_tag) - s1_tag_match[3] <= T_856 - node T_857 = and(T_847, s1_tag_match[3]) - s1_tag_hit[3] <= T_857 - node T_860 = or(UInt<1>("h0"), UInt<1>("h0")) - node T_861 = or(T_850, T_860) - node T_862 = and(T_847, T_861) - s1_disparity[3] <= T_862 - node T_863 = or(s1_tag_hit[0], s1_tag_hit[1]) - node T_864 = or(T_863, s1_tag_hit[2]) - node T_865 = or(T_864, s1_tag_hit[3]) - node T_866 = or(s1_disparity[0], s1_disparity[1]) - node T_867 = or(T_866, s1_disparity[2]) - node T_868 = or(T_867, s1_disparity[3]) - node T_870 = eq(T_868, UInt<1>("h0")) - node T_871 = and(T_865, T_870) - s1_any_tag_hit <= T_871 - mem T_874 : - data-type => UInt<128> - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_886 - writer => T_879 - T_874.T_886.addr is invalid - T_874.T_886.clk <= clk - T_874.T_886.en <= UInt<1>("h0") - T_874.T_879.addr is invalid - T_874.T_879.clk <= clk - T_874.T_879.en <= UInt<1>("h0") - T_874.T_879.data is invalid - T_874.T_879.mask <= UInt<1>("h0") - node T_876 = eq(repl_way, UInt<1>("h0")) - node T_877 = and(T_553.io.out.valid, T_876) - when T_877 : - node T_878 = cat(s1_idx, refill_cnt) - T_874.T_879.addr <= T_878 - T_874.T_879.en <= UInt<1>("h1") - T_874.T_879.data <= T_553.io.out.bits.data - T_874.T_879.mask <= UInt<1>("h1") - skip - node T_880 = bits(s0_pgoff, 11, 4) - node T_882 = eq(T_877, UInt<1>("h0")) - node T_883 = and(T_882, s0_valid) - wire T_885 : UInt - T_885 is invalid - when T_883 : - T_885 <= T_880 - skip - T_874.T_886.addr <= T_885 - T_874.T_886.en <= UInt<1>("h1") - s1_dout[0] <= T_874.T_886.data - mem T_889 : - data-type => UInt<128> - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_901 - writer => T_894 - T_889.T_901.addr is invalid - T_889.T_901.clk <= clk - T_889.T_901.en <= UInt<1>("h0") - T_889.T_894.addr is invalid - T_889.T_894.clk <= clk - T_889.T_894.en <= UInt<1>("h0") - T_889.T_894.data is invalid - T_889.T_894.mask <= UInt<1>("h0") - node T_891 = eq(repl_way, UInt<1>("h1")) - node T_892 = and(T_553.io.out.valid, T_891) - when T_892 : - node T_893 = cat(s1_idx, refill_cnt) - T_889.T_894.addr <= T_893 - T_889.T_894.en <= UInt<1>("h1") - T_889.T_894.data <= T_553.io.out.bits.data - T_889.T_894.mask <= UInt<1>("h1") - skip - node T_895 = bits(s0_pgoff, 11, 4) - node T_897 = eq(T_892, UInt<1>("h0")) - node T_898 = and(T_897, s0_valid) - wire T_900 : UInt - T_900 is invalid - when T_898 : - T_900 <= T_895 - skip - T_889.T_901.addr <= T_900 - T_889.T_901.en <= UInt<1>("h1") - s1_dout[1] <= T_889.T_901.data - mem T_904 : - data-type => UInt<128> - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_916 - writer => T_909 - T_904.T_916.addr is invalid - T_904.T_916.clk <= clk - T_904.T_916.en <= UInt<1>("h0") - T_904.T_909.addr is invalid - T_904.T_909.clk <= clk - T_904.T_909.en <= UInt<1>("h0") - T_904.T_909.data is invalid - T_904.T_909.mask <= UInt<1>("h0") - node T_906 = eq(repl_way, UInt<2>("h2")) - node T_907 = and(T_553.io.out.valid, T_906) - when T_907 : - node T_908 = cat(s1_idx, refill_cnt) - T_904.T_909.addr <= T_908 - T_904.T_909.en <= UInt<1>("h1") - T_904.T_909.data <= T_553.io.out.bits.data - T_904.T_909.mask <= UInt<1>("h1") - skip - node T_910 = bits(s0_pgoff, 11, 4) - node T_912 = eq(T_907, UInt<1>("h0")) - node T_913 = and(T_912, s0_valid) - wire T_915 : UInt - T_915 is invalid - when T_913 : - T_915 <= T_910 - skip - T_904.T_916.addr <= T_915 - T_904.T_916.en <= UInt<1>("h1") - s1_dout[2] <= T_904.T_916.data - mem T_919 : - data-type => UInt<128> - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_931 - writer => T_924 - T_919.T_931.addr is invalid - T_919.T_931.clk <= clk - T_919.T_931.en <= UInt<1>("h0") - T_919.T_924.addr is invalid - T_919.T_924.clk <= clk - T_919.T_924.en <= UInt<1>("h0") - T_919.T_924.data is invalid - T_919.T_924.mask <= UInt<1>("h0") - node T_921 = eq(repl_way, UInt<2>("h3")) - node T_922 = and(T_553.io.out.valid, T_921) - when T_922 : - node T_923 = cat(s1_idx, refill_cnt) - T_919.T_924.addr <= T_923 - T_919.T_924.en <= UInt<1>("h1") - T_919.T_924.data <= T_553.io.out.bits.data - T_919.T_924.mask <= UInt<1>("h1") - skip - node T_925 = bits(s0_pgoff, 11, 4) - node T_927 = eq(T_922, UInt<1>("h0")) - node T_928 = and(T_927, s0_valid) - wire T_930 : UInt - T_930 is invalid - when T_928 : - T_930 <= T_925 - skip - T_919.T_931.addr <= T_930 - T_919.T_931.en <= UInt<1>("h1") - s1_dout[3] <= T_919.T_931.data - node T_933 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h0")) - node T_935 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h0")) - node T_937 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h0")) - node T_939 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h0")) - node T_941 = or(T_933, T_935) - node T_942 = or(T_941, T_937) - node T_943 = or(T_942, T_939) - wire T_944 : UInt<128> - T_944 is invalid - T_944 <= T_943 - io.resp.bits.datablock <= T_944 - io.resp.valid <= s1_hit - node T_945 = eq(state, UInt<1>("h1")) - io.mem.acquire.valid <= T_945 - node T_946 = shr(refill_addr, 6) - node T_957 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_958 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_959 = cat(T_957, T_958) - node T_961 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_962 = cat(UInt<3>("h7"), T_961) - node T_964 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_966 = cat(UInt<1>("h0"), UInt<1>("h1")) - node T_968 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_969 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_970 = cat(T_968, T_969) - node T_972 = cat(UInt<5>("h0"), UInt<1>("h1")) - node T_974 = cat(UInt<5>("h1"), UInt<1>("h1")) - node T_975 = eq(UInt<3>("h6"), UInt<3>("h1")) - node T_976 = mux(T_975, T_974, UInt<1>("h0")) - node T_977 = eq(UInt<3>("h5"), UInt<3>("h1")) - node T_978 = mux(T_977, T_972, T_976) - node T_979 = eq(UInt<3>("h4"), UInt<3>("h1")) - node T_980 = mux(T_979, T_970, T_978) - node T_981 = eq(UInt<3>("h3"), UInt<3>("h1")) - node T_982 = mux(T_981, T_966, T_980) - node T_983 = eq(UInt<3>("h2"), UInt<3>("h1")) - node T_984 = mux(T_983, T_964, T_982) - node T_985 = eq(UInt<3>("h1"), UInt<3>("h1")) - node T_986 = mux(T_985, T_962, T_984) - node T_987 = eq(UInt<3>("h0"), UInt<3>("h1")) - node T_988 = mux(T_987, T_959, T_986) - wire T_1020 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1020 is invalid - T_1020.is_builtin_type <= UInt<1>("h1") - T_1020.a_type <= UInt<3>("h1") - T_1020.client_xact_id <= UInt<1>("h0") - T_1020.addr_block <= T_946 - T_1020.addr_beat <= UInt<1>("h0") - T_1020.data <= UInt<1>("h0") - T_1020.union <= T_988 - io.mem.acquire.bits <- T_1020 - node T_1051 = eq(UInt<1>("h0"), state) - when T_1051 : - when s1_miss : - state <= UInt<1>("h1") - skip - invalidated <= UInt<1>("h0") - skip - node T_1053 = eq(UInt<1>("h1"), state) - when T_1053 : - when io.mem.acquire.ready : - state <= UInt<2>("h2") - skip - skip - node T_1054 = eq(UInt<2>("h2"), state) - when T_1054 : - when io.mem.grant.valid : - state <= UInt<2>("h3") - skip - skip - node T_1055 = eq(UInt<2>("h3"), state) - when T_1055 : - when refill_done : - state <= UInt<1>("h0") - skip - skip - module RocketCAM : - input clk : Clock - input reset : UInt<1> - output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>} - io is invalid - mem cam_tags : - data-type => UInt<34> - depth => 8 - write-latency => 1 - read-latency => 0 - reader => T_32 - reader => T_37 - reader => T_42 - reader => T_47 - reader => T_52 - reader => T_57 - reader => T_62 - reader => T_67 - writer => T_27 - cam_tags.T_32.addr is invalid - cam_tags.T_32.clk <= clk - cam_tags.T_37.addr is invalid - cam_tags.T_37.clk <= clk - cam_tags.T_42.addr is invalid - cam_tags.T_42.clk <= clk - cam_tags.T_47.addr is invalid - cam_tags.T_47.clk <= clk - cam_tags.T_52.addr is invalid - cam_tags.T_52.clk <= clk - cam_tags.T_57.addr is invalid - cam_tags.T_57.clk <= clk - cam_tags.T_62.addr is invalid - cam_tags.T_62.clk <= clk - cam_tags.T_67.addr is invalid - cam_tags.T_67.clk <= clk - cam_tags.T_32.en <= UInt<1>("h0") - cam_tags.T_37.en <= UInt<1>("h0") - cam_tags.T_42.en <= UInt<1>("h0") - cam_tags.T_47.en <= UInt<1>("h0") - cam_tags.T_52.en <= UInt<1>("h0") - cam_tags.T_57.en <= UInt<1>("h0") - cam_tags.T_62.en <= UInt<1>("h0") - cam_tags.T_67.en <= UInt<1>("h0") - cam_tags.T_27.addr is invalid - cam_tags.T_27.clk <= clk - cam_tags.T_27.en <= UInt<1>("h0") - cam_tags.T_27.data is invalid - cam_tags.T_27.mask <= UInt<1>("h0") - reg vb_array : UInt<8>, clk with : - reset => (reset, UInt<8>("h0")) - when io.write : - node T_21 = dshl(UInt<1>("h1"), io.write_addr) - node T_22 = or(vb_array, T_21) - node T_23 = not(vb_array) - node T_24 = or(T_23, T_21) - node T_25 = not(T_24) - node T_26 = mux(UInt<1>("h1"), T_22, T_25) - vb_array <= T_26 - cam_tags.T_27.addr <= io.write_addr - cam_tags.T_27.en <= UInt<1>("h1") - cam_tags.T_27.data <= io.write_tag - cam_tags.T_27.mask <= UInt<1>("h1") - skip - when io.clear : - node T_28 = not(io.clear_mask) - node T_29 = and(vb_array, T_28) - vb_array <= T_29 - skip - node T_30 = bits(vb_array, 0, 0) - cam_tags.T_32.addr <= UInt<1>("h0") - cam_tags.T_32.en <= UInt<1>("h1") - node T_33 = eq(cam_tags.T_32.data, io.tag) - node T_34 = and(T_30, T_33) - node T_35 = bits(vb_array, 1, 1) - cam_tags.T_37.addr <= UInt<1>("h1") - cam_tags.T_37.en <= UInt<1>("h1") - node T_38 = eq(cam_tags.T_37.data, io.tag) - node T_39 = and(T_35, T_38) - node T_40 = bits(vb_array, 2, 2) - cam_tags.T_42.addr <= UInt<2>("h2") - cam_tags.T_42.en <= UInt<1>("h1") - node T_43 = eq(cam_tags.T_42.data, io.tag) - node T_44 = and(T_40, T_43) - node T_45 = bits(vb_array, 3, 3) - cam_tags.T_47.addr <= UInt<2>("h3") - cam_tags.T_47.en <= UInt<1>("h1") - node T_48 = eq(cam_tags.T_47.data, io.tag) - node T_49 = and(T_45, T_48) - node T_50 = bits(vb_array, 4, 4) - cam_tags.T_52.addr <= UInt<3>("h4") - cam_tags.T_52.en <= UInt<1>("h1") - node T_53 = eq(cam_tags.T_52.data, io.tag) - node T_54 = and(T_50, T_53) - node T_55 = bits(vb_array, 5, 5) - cam_tags.T_57.addr <= UInt<3>("h5") - cam_tags.T_57.en <= UInt<1>("h1") - node T_58 = eq(cam_tags.T_57.data, io.tag) - node T_59 = and(T_55, T_58) - node T_60 = bits(vb_array, 6, 6) - cam_tags.T_62.addr <= UInt<3>("h6") - cam_tags.T_62.en <= UInt<1>("h1") - node T_63 = eq(cam_tags.T_62.data, io.tag) - node T_64 = and(T_60, T_63) - node T_65 = bits(vb_array, 7, 7) - cam_tags.T_67.addr <= UInt<3>("h7") - cam_tags.T_67.en <= UInt<1>("h1") - node T_68 = eq(cam_tags.T_67.data, io.tag) - node T_69 = and(T_65, T_68) - io.valid_bits <= vb_array - wire T_71 : UInt<1>[8] - T_71[0] <= T_34 - T_71[1] <= T_39 - T_71[2] <= T_44 - T_71[3] <= T_49 - T_71[4] <= T_54 - T_71[5] <= T_59 - T_71[6] <= T_64 - T_71[7] <= T_69 - node T_81 = cat(T_71[7], T_71[6]) - node T_82 = cat(T_71[5], T_71[4]) - node T_83 = cat(T_81, T_82) - node T_84 = cat(T_71[3], T_71[2]) - node T_85 = cat(T_71[1], T_71[0]) - node T_86 = cat(T_84, T_85) - node T_87 = cat(T_83, T_86) - io.hits <= T_87 - node T_89 = neq(io.hits, UInt<1>("h0")) - io.hit <= T_89 - module TLB : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : { miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg r_refill_tag : UInt, clk with : - reset => (UInt<1>("h0"), r_refill_tag) - reg r_refill_waddr : UInt, clk with : - reset => (UInt<1>("h0"), r_refill_waddr) - reg r_req : { asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk with : - reset => (UInt<1>("h0"), r_req) - inst tag_cam of RocketCAM - tag_cam.io is invalid - tag_cam.clk <= clk - tag_cam.reset <= reset - mem tag_ram : - data-type => UInt<20> - depth => 8 - write-latency => 1 - read-latency => 0 - reader => T_859 - reader => T_861 - reader => T_863 - reader => T_865 - reader => T_867 - reader => T_869 - reader => T_871 - reader => T_873 - writer => T_383 - tag_ram.T_859.addr is invalid - tag_ram.T_859.clk <= clk - tag_ram.T_861.addr is invalid - tag_ram.T_861.clk <= clk - tag_ram.T_863.addr is invalid - tag_ram.T_863.clk <= clk - tag_ram.T_865.addr is invalid - tag_ram.T_865.clk <= clk - tag_ram.T_867.addr is invalid - tag_ram.T_867.clk <= clk - tag_ram.T_869.addr is invalid - tag_ram.T_869.clk <= clk - tag_ram.T_871.addr is invalid - tag_ram.T_871.clk <= clk - tag_ram.T_873.addr is invalid - tag_ram.T_873.clk <= clk - tag_ram.T_859.en <= UInt<1>("h0") - tag_ram.T_861.en <= UInt<1>("h0") - tag_ram.T_863.en <= UInt<1>("h0") - tag_ram.T_865.en <= UInt<1>("h0") - tag_ram.T_867.en <= UInt<1>("h0") - tag_ram.T_869.en <= UInt<1>("h0") - tag_ram.T_871.en <= UInt<1>("h0") - tag_ram.T_873.en <= UInt<1>("h0") - tag_ram.T_383.addr is invalid - tag_ram.T_383.clk <= clk - tag_ram.T_383.en <= UInt<1>("h0") - tag_ram.T_383.data is invalid - tag_ram.T_383.mask <= UInt<1>("h0") - node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) - tag_cam.io.tag <= lookup_tag - node T_176 = eq(state, UInt<2>("h2")) - node T_177 = and(T_176, io.ptw.resp.valid) - tag_cam.io.write <= T_177 - tag_cam.io.write_tag <= r_refill_tag - tag_cam.io.write_addr <= r_refill_waddr - node T_178 = bits(tag_cam.io.hits, 7, 4) - node T_179 = bits(tag_cam.io.hits, 3, 0) - node T_181 = neq(T_178, UInt<1>("h0")) - node T_182 = or(T_178, T_179) - node T_183 = bits(T_182, 3, 2) - node T_184 = bits(T_182, 1, 0) - node T_186 = neq(T_183, UInt<1>("h0")) - node T_187 = or(T_183, T_184) - node T_188 = bits(T_187, 1, 1) - node T_189 = cat(T_186, T_188) - node tag_hit_addr = cat(T_181, T_189) - reg valid_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), valid_array) - reg ur_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), ur_array) - reg uw_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), uw_array) - reg ux_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), ux_array) - reg sr_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), sr_array) - reg sw_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), sw_array) - reg sx_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), sx_array) - reg dirty_array : UInt<1>[8], clk with : - reset => (UInt<1>("h0"), dirty_array) - when io.ptw.resp.valid : - tag_ram.T_383.addr <= r_refill_waddr - tag_ram.T_383.en <= UInt<1>("h1") - tag_ram.T_383.data <= io.ptw.resp.bits.pte.ppn - tag_ram.T_383.mask <= UInt<1>("h1") - node T_386 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - valid_array[r_refill_waddr] <= T_386 - node T_389 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h2")) - node T_390 = and(io.ptw.resp.bits.pte.v, T_389) - node T_392 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h8")) - node T_393 = and(T_390, T_392) - node T_395 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_396 = and(T_393, T_395) - ur_array[r_refill_waddr] <= T_396 - node T_399 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h2")) - node T_400 = and(io.ptw.resp.bits.pte.v, T_399) - node T_402 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h8")) - node T_403 = and(T_400, T_402) - node T_404 = bits(io.ptw.resp.bits.pte.typ, 0, 0) - node T_405 = and(T_403, T_404) - node T_407 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_408 = and(T_405, T_407) - uw_array[r_refill_waddr] <= T_408 - node T_411 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h2")) - node T_412 = and(io.ptw.resp.bits.pte.v, T_411) - node T_414 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h8")) - node T_415 = and(T_412, T_414) - node T_416 = bits(io.ptw.resp.bits.pte.typ, 1, 1) - node T_417 = and(T_415, T_416) - node T_419 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_420 = and(T_417, T_419) - ux_array[r_refill_waddr] <= T_420 - node T_423 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h2")) - node T_424 = and(io.ptw.resp.bits.pte.v, T_423) - node T_426 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_427 = and(T_424, T_426) - sr_array[r_refill_waddr] <= T_427 - node T_430 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h2")) - node T_431 = and(io.ptw.resp.bits.pte.v, T_430) - node T_432 = bits(io.ptw.resp.bits.pte.typ, 0, 0) - node T_433 = and(T_431, T_432) - node T_435 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_436 = and(T_433, T_435) - sw_array[r_refill_waddr] <= T_436 - node T_439 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h4")) - node T_440 = and(io.ptw.resp.bits.pte.v, T_439) - node T_441 = bits(io.ptw.resp.bits.pte.typ, 1, 1) - node T_442 = and(T_440, T_441) - node T_444 = eq(io.ptw.resp.bits.error, UInt<1>("h0")) - node T_445 = and(T_442, T_444) - sx_array[r_refill_waddr] <= T_445 - dirty_array[r_refill_waddr] <= io.ptw.resp.bits.pte.d - skip - node T_447 = not(tag_cam.io.valid_bits) - node T_449 = eq(T_447, UInt<1>("h0")) - node has_invalid_entry = eq(T_449, UInt<1>("h0")) - node T_452 = not(tag_cam.io.valid_bits) - node T_453 = bits(T_452, 0, 0) - node T_454 = bits(T_452, 1, 1) - node T_455 = bits(T_452, 2, 2) - node T_456 = bits(T_452, 3, 3) - node T_457 = bits(T_452, 4, 4) - node T_458 = bits(T_452, 5, 5) - node T_459 = bits(T_452, 6, 6) - node T_460 = bits(T_452, 7, 7) - wire T_462 : UInt<1>[8] - T_462[0] <= T_453 - T_462[1] <= T_454 - T_462[2] <= T_455 - T_462[3] <= T_456 - T_462[4] <= T_457 - T_462[5] <= T_458 - T_462[6] <= T_459 - T_462[7] <= T_460 - node T_480 = mux(T_462[6], UInt<3>("h6"), UInt<3>("h7")) - node T_481 = mux(T_462[5], UInt<3>("h5"), T_480) - node T_482 = mux(T_462[4], UInt<3>("h4"), T_481) - node T_483 = mux(T_462[3], UInt<2>("h3"), T_482) - node T_484 = mux(T_462[2], UInt<2>("h2"), T_483) - node T_485 = mux(T_462[1], UInt<1>("h1"), T_484) - node invalid_entry = mux(T_462[0], UInt<1>("h0"), T_485) - reg T_488 : UInt<8>, clk with : - reset => (UInt<1>("h0"), T_488) - node T_490 = dshr(T_488, UInt<1>("h1")) - node T_491 = bits(T_490, 0, 0) - node T_492 = cat(UInt<1>("h1"), T_491) - node T_493 = dshr(T_488, T_492) - node T_494 = bits(T_493, 0, 0) - node T_495 = cat(T_492, T_494) - node T_496 = dshr(T_488, T_495) - node T_497 = bits(T_496, 0, 0) - node T_498 = cat(T_495, T_497) - node T_499 = bits(T_498, 2, 0) - node repl_waddr = mux(has_invalid_entry, invalid_entry, T_499) - node T_502 = eq(io.req.bits.instruction, UInt<1>("h0")) - node T_503 = and(io.ptw.status.mprv, T_502) - node priv = mux(T_503, io.ptw.status.prv1, io.ptw.status.prv) - node priv_s = eq(priv, UInt<1>("h1")) - node priv_uses_vm = leq(priv, UInt<1>("h1")) - node T_510 = eq(r_req.store, UInt<1>("h0")) - node T_511 = or(r_req.instruction, r_req.store) - node T_513 = eq(T_511, UInt<1>("h0")) - node T_514 = cat(r_req.store, T_513) - node req_xwr = cat(T_510, T_514) - node T_516 = cat(sr_array[7], sr_array[6]) - node T_517 = cat(sr_array[5], sr_array[4]) - node T_518 = cat(T_516, T_517) - node T_519 = cat(sr_array[3], sr_array[2]) - node T_520 = cat(sr_array[1], sr_array[0]) - node T_521 = cat(T_519, T_520) - node T_522 = cat(T_518, T_521) - node T_523 = cat(ur_array[7], ur_array[6]) - node T_524 = cat(ur_array[5], ur_array[4]) - node T_525 = cat(T_523, T_524) - node T_526 = cat(ur_array[3], ur_array[2]) - node T_527 = cat(ur_array[1], ur_array[0]) - node T_528 = cat(T_526, T_527) - node T_529 = cat(T_525, T_528) - node r_array = mux(priv_s, T_522, T_529) - node T_531 = cat(sw_array[7], sw_array[6]) - node T_532 = cat(sw_array[5], sw_array[4]) - node T_533 = cat(T_531, T_532) - node T_534 = cat(sw_array[3], sw_array[2]) - node T_535 = cat(sw_array[1], sw_array[0]) - node T_536 = cat(T_534, T_535) - node T_537 = cat(T_533, T_536) - node T_538 = cat(uw_array[7], uw_array[6]) - node T_539 = cat(uw_array[5], uw_array[4]) - node T_540 = cat(T_538, T_539) - node T_541 = cat(uw_array[3], uw_array[2]) - node T_542 = cat(uw_array[1], uw_array[0]) - node T_543 = cat(T_541, T_542) - node T_544 = cat(T_540, T_543) - node w_array = mux(priv_s, T_537, T_544) - node T_546 = cat(sx_array[7], sx_array[6]) - node T_547 = cat(sx_array[5], sx_array[4]) - node T_548 = cat(T_546, T_547) - node T_549 = cat(sx_array[3], sx_array[2]) - node T_550 = cat(sx_array[1], sx_array[0]) - node T_551 = cat(T_549, T_550) - node T_552 = cat(T_548, T_551) - node T_553 = cat(ux_array[7], ux_array[6]) - node T_554 = cat(ux_array[5], ux_array[4]) - node T_555 = cat(T_553, T_554) - node T_556 = cat(ux_array[3], ux_array[2]) - node T_557 = cat(ux_array[1], ux_array[0]) - node T_558 = cat(T_556, T_557) - node T_559 = cat(T_555, T_558) - node x_array = mux(priv_s, T_552, T_559) - node T_561 = bits(io.ptw.status.vm, 3, 3) - node T_562 = and(T_561, priv_uses_vm) - node T_564 = eq(io.req.bits.passthrough, UInt<1>("h0")) - node vm_enabled = and(T_562, T_564) - node T_566 = bits(io.req.bits.vpn, 27, 27) - node T_567 = bits(io.req.bits.vpn, 26, 26) - node bad_va = neq(T_566, T_567) - node T_569 = cat(dirty_array[7], dirty_array[6]) - node T_570 = cat(dirty_array[5], dirty_array[4]) - node T_571 = cat(T_569, T_570) - node T_572 = cat(dirty_array[3], dirty_array[2]) - node T_573 = cat(dirty_array[1], dirty_array[0]) - node T_574 = cat(T_572, T_573) - node T_575 = cat(T_571, T_574) - node T_577 = mux(io.req.bits.store, w_array, UInt<1>("h0")) - node T_578 = not(T_577) - node T_579 = or(T_575, T_578) - node tag_hits = and(tag_cam.io.hits, T_579) - node tag_hit = neq(tag_hits, UInt<1>("h0")) - node tlb_hit = and(vm_enabled, tag_hit) - node T_585 = eq(tag_hit, UInt<1>("h0")) - node T_586 = and(vm_enabled, T_585) - node T_588 = eq(bad_va, UInt<1>("h0")) - node tlb_miss = and(T_586, T_588) - node T_590 = and(io.req.valid, tlb_hit) - when T_590 : - node T_591 = bits(tag_cam.io.hits, 7, 4) - node T_592 = bits(tag_cam.io.hits, 3, 0) - node T_594 = neq(T_591, UInt<1>("h0")) - node T_595 = or(T_591, T_592) - node T_596 = bits(T_595, 3, 2) - node T_597 = bits(T_595, 1, 0) - node T_599 = neq(T_596, UInt<1>("h0")) - node T_600 = or(T_596, T_597) - node T_601 = bits(T_600, 1, 1) - node T_602 = cat(T_599, T_601) - node T_603 = cat(T_594, T_602) - node T_605 = bits(T_603, 2, 2) - node T_607 = dshl(UInt<8>("h1"), UInt<1>("h1")) - node T_608 = bits(T_607, 7, 0) - node T_609 = not(T_608) - node T_610 = and(T_488, T_609) - node T_612 = mux(T_605, UInt<1>("h0"), T_608) - node T_613 = or(T_610, T_612) - node T_614 = cat(UInt<1>("h1"), T_605) - node T_615 = bits(T_603, 1, 1) - node T_617 = dshl(UInt<8>("h1"), T_614) - node T_618 = bits(T_617, 7, 0) - node T_619 = not(T_618) - node T_620 = and(T_613, T_619) - node T_622 = mux(T_615, UInt<1>("h0"), T_618) - node T_623 = or(T_620, T_622) - node T_624 = cat(T_614, T_615) - node T_625 = bits(T_603, 0, 0) - node T_627 = dshl(UInt<8>("h1"), T_624) - node T_628 = bits(T_627, 7, 0) - node T_629 = not(T_628) - node T_630 = and(T_623, T_629) - node T_632 = mux(T_625, UInt<1>("h0"), T_628) - node T_633 = or(T_630, T_632) - node T_634 = cat(T_624, T_625) - T_488 <= T_633 - skip - node paddr = cat(io.resp.ppn, UInt<12>("h0")) - node T_638 = geq(paddr, UInt<1>("h0")) - node T_640 = lt(paddr, UInt<31>("h40000000")) - node T_641 = and(T_638, T_640) - node T_643 = geq(paddr, UInt<31>("h40000000")) - node T_645 = lt(paddr, UInt<31>("h40008000")) - node T_646 = and(T_643, T_645) - node T_648 = geq(paddr, UInt<31>("h40008000")) - node T_650 = lt(paddr, UInt<31>("h40010000")) - node T_651 = and(T_648, T_650) - node T_653 = geq(paddr, UInt<31>("h40010000")) - node T_655 = lt(paddr, UInt<31>("h40010200")) - node T_656 = and(T_653, T_655) - node T_658 = geq(paddr, UInt<32>("h80000000")) - node T_660 = lt(paddr, UInt<33>("h100000000")) - node T_661 = and(T_658, T_660) - node T_662 = or(T_641, T_646) - node T_663 = or(T_662, T_651) - node T_664 = or(T_663, T_656) - node addr_ok = or(T_664, T_661) - node T_667 = geq(paddr, UInt<1>("h0")) - node T_669 = lt(paddr, UInt<31>("h40000000")) - node T_670 = and(T_667, T_669) - wire T_680 : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_680 is invalid - T_680.r <= UInt<1>("h1") - T_680.w <= UInt<1>("h1") - T_680.x <= UInt<1>("h1") - node T_688 = geq(paddr, UInt<31>("h40000000")) - node T_690 = lt(paddr, UInt<31>("h40008000")) - node T_691 = and(T_688, T_690) - wire T_701 : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_701 is invalid - T_701.r <= UInt<1>("h1") - T_701.w <= UInt<1>("h0") - T_701.x <= UInt<1>("h0") - node T_709 = geq(paddr, UInt<31>("h40008000")) - node T_711 = lt(paddr, UInt<31>("h40010000")) - node T_712 = and(T_709, T_711) - wire T_722 : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_722 is invalid - T_722.r <= UInt<1>("h1") - T_722.w <= UInt<1>("h1") - T_722.x <= UInt<1>("h0") - node T_730 = geq(paddr, UInt<31>("h40010000")) - node T_732 = lt(paddr, UInt<31>("h40010200")) - node T_733 = and(T_730, T_732) - wire T_743 : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_743 is invalid - T_743.r <= UInt<1>("h1") - T_743.w <= UInt<1>("h1") - T_743.x <= UInt<1>("h0") - node T_751 = geq(paddr, UInt<32>("h80000000")) - node T_753 = lt(paddr, UInt<33>("h100000000")) - node T_754 = and(T_751, T_753) - wire T_764 : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_764 is invalid - T_764.r <= UInt<1>("h1") - T_764.w <= UInt<1>("h1") - T_764.x <= UInt<1>("h0") - node T_771 = cat(T_680.w, T_680.r) - node T_772 = cat(T_680.x, T_771) - node T_774 = mux(T_670, T_772, UInt<1>("h0")) - node T_775 = cat(T_701.w, T_701.r) - node T_776 = cat(T_701.x, T_775) - node T_778 = mux(T_691, T_776, UInt<1>("h0")) - node T_779 = cat(T_722.w, T_722.r) - node T_780 = cat(T_722.x, T_779) - node T_782 = mux(T_712, T_780, UInt<1>("h0")) - node T_783 = cat(T_743.w, T_743.r) - node T_784 = cat(T_743.x, T_783) - node T_786 = mux(T_733, T_784, UInt<1>("h0")) - node T_787 = cat(T_764.w, T_764.r) - node T_788 = cat(T_764.x, T_787) - node T_790 = mux(T_754, T_788, UInt<1>("h0")) - node T_795 = or(T_774, T_778) - node T_796 = or(T_795, T_782) - node T_797 = or(T_796, T_786) - node T_798 = or(T_797, T_790) - wire addr_prot : { x : UInt<1>, w : UInt<1>, r : UInt<1>} - addr_prot is invalid - node T_807 = bits(T_798, 0, 0) - addr_prot.r <= T_807 - node T_808 = bits(T_798, 1, 1) - addr_prot.w <= T_808 - node T_809 = bits(T_798, 2, 2) - addr_prot.x <= T_809 - node T_810 = eq(state, UInt<1>("h0")) - io.req.ready <= T_810 - node T_812 = eq(addr_ok, UInt<1>("h0")) - node T_814 = eq(addr_prot.r, UInt<1>("h0")) - node T_815 = or(T_812, T_814) - node T_816 = or(T_815, bad_va) - node T_817 = and(r_array, tag_cam.io.hits) - node T_819 = neq(T_817, UInt<1>("h0")) - node T_821 = eq(T_819, UInt<1>("h0")) - node T_822 = and(tlb_hit, T_821) - node T_823 = or(T_816, T_822) - io.resp.xcpt_ld <= T_823 - node T_825 = eq(addr_ok, UInt<1>("h0")) - node T_827 = eq(addr_prot.w, UInt<1>("h0")) - node T_828 = or(T_825, T_827) - node T_829 = or(T_828, bad_va) - node T_830 = and(w_array, tag_cam.io.hits) - node T_832 = neq(T_830, UInt<1>("h0")) - node T_834 = eq(T_832, UInt<1>("h0")) - node T_835 = and(tlb_hit, T_834) - node T_836 = or(T_829, T_835) - io.resp.xcpt_st <= T_836 - node T_838 = eq(addr_ok, UInt<1>("h0")) - node T_840 = eq(addr_prot.x, UInt<1>("h0")) - node T_841 = or(T_838, T_840) - node T_842 = or(T_841, bad_va) - node T_843 = and(x_array, tag_cam.io.hits) - node T_845 = neq(T_843, UInt<1>("h0")) - node T_847 = eq(T_845, UInt<1>("h0")) - node T_848 = and(tlb_hit, T_847) - node T_849 = or(T_842, T_848) - io.resp.xcpt_if <= T_849 - io.resp.miss <= tlb_miss - node T_850 = bits(tag_cam.io.hits, 0, 0) - node T_851 = bits(tag_cam.io.hits, 1, 1) - node T_852 = bits(tag_cam.io.hits, 2, 2) - node T_853 = bits(tag_cam.io.hits, 3, 3) - node T_854 = bits(tag_cam.io.hits, 4, 4) - node T_855 = bits(tag_cam.io.hits, 5, 5) - node T_856 = bits(tag_cam.io.hits, 6, 6) - node T_857 = bits(tag_cam.io.hits, 7, 7) - tag_ram.T_859.addr <= UInt<1>("h0") - tag_ram.T_859.en <= UInt<1>("h1") - tag_ram.T_861.addr <= UInt<1>("h1") - tag_ram.T_861.en <= UInt<1>("h1") - tag_ram.T_863.addr <= UInt<2>("h2") - tag_ram.T_863.en <= UInt<1>("h1") - tag_ram.T_865.addr <= UInt<2>("h3") - tag_ram.T_865.en <= UInt<1>("h1") - tag_ram.T_867.addr <= UInt<3>("h4") - tag_ram.T_867.en <= UInt<1>("h1") - tag_ram.T_869.addr <= UInt<3>("h5") - tag_ram.T_869.en <= UInt<1>("h1") - tag_ram.T_871.addr <= UInt<3>("h6") - tag_ram.T_871.en <= UInt<1>("h1") - tag_ram.T_873.addr <= UInt<3>("h7") - tag_ram.T_873.en <= UInt<1>("h1") - node T_875 = mux(T_850, tag_ram.T_859.data, UInt<1>("h0")) - node T_877 = mux(T_851, tag_ram.T_861.data, UInt<1>("h0")) - node T_879 = mux(T_852, tag_ram.T_863.data, UInt<1>("h0")) - node T_881 = mux(T_853, tag_ram.T_865.data, UInt<1>("h0")) - node T_883 = mux(T_854, tag_ram.T_867.data, UInt<1>("h0")) - node T_885 = mux(T_855, tag_ram.T_869.data, UInt<1>("h0")) - node T_887 = mux(T_856, tag_ram.T_871.data, UInt<1>("h0")) - node T_889 = mux(T_857, tag_ram.T_873.data, UInt<1>("h0")) - node T_891 = or(T_875, T_877) - node T_892 = or(T_891, T_879) - node T_893 = or(T_892, T_881) - node T_894 = or(T_893, T_883) - node T_895 = or(T_894, T_885) - node T_896 = or(T_895, T_887) - node T_897 = or(T_896, T_889) - wire T_898 : UInt<20> - T_898 is invalid - T_898 <= T_897 - node T_899 = bits(io.req.bits.vpn, 19, 0) - node T_900 = mux(vm_enabled, T_898, T_899) - io.resp.ppn <= T_900 - io.resp.hit_idx <= tag_cam.io.hits - node T_901 = and(io.req.ready, io.req.valid) - node T_902 = or(io.ptw.invalidate, T_901) - tag_cam.io.clear <= T_902 - node T_903 = cat(valid_array[7], valid_array[6]) - node T_904 = cat(valid_array[5], valid_array[4]) - node T_905 = cat(T_903, T_904) - node T_906 = cat(valid_array[3], valid_array[2]) - node T_907 = cat(valid_array[1], valid_array[0]) - node T_908 = cat(T_906, T_907) - node T_909 = cat(T_905, T_908) - node T_910 = not(T_909) - node T_911 = not(tag_hits) - node T_912 = and(tag_cam.io.hits, T_911) - node T_913 = or(T_910, T_912) - tag_cam.io.clear_mask <= T_913 - when io.ptw.invalidate : - node T_915 = not(UInt<8>("h0")) - tag_cam.io.clear_mask <= T_915 - skip - node T_916 = eq(state, UInt<1>("h1")) - io.ptw.req.valid <= T_916 - io.ptw.req.bits.addr <= r_refill_tag - io.ptw.req.bits.prv <= io.ptw.status.prv - io.ptw.req.bits.store <= r_req.store - io.ptw.req.bits.fetch <= r_req.instruction - node T_917 = and(io.req.ready, io.req.valid) - node T_918 = and(T_917, tlb_miss) - when T_918 : - state <= UInt<1>("h1") - r_refill_tag <= lookup_tag - r_refill_waddr <= repl_waddr - r_req <- io.req.bits - skip - node T_919 = eq(state, UInt<1>("h1")) - when T_919 : - when io.ptw.invalidate : - state <= UInt<1>("h0") - skip - when io.ptw.req.ready : - state <= UInt<2>("h2") - when io.ptw.invalidate : - state <= UInt<2>("h3") - skip - skip - skip - node T_920 = eq(state, UInt<2>("h2")) - node T_921 = and(T_920, io.ptw.invalidate) - when T_921 : - state <= UInt<2>("h3") - skip - when io.ptw.resp.valid : - state <= UInt<1>("h0") - skip - module Queue_92 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, datablock : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, datablock : UInt<128>}}, count : UInt<1>} - io is invalid - mem ram : - data-type => { data : UInt<32>, datablock : UInt<128>} - depth => 1 - write-latency => 1 - read-latency => 0 - reader => T_539 - writer => T_477 - ram.T_539.addr is invalid - ram.T_539.clk <= clk - ram.T_539.en <= UInt<1>("h0") - ram.T_477.addr is invalid - ram.T_477.clk <= clk - ram.T_477.en <= UInt<1>("h0") - ram.T_477.data is invalid - ram.T_477.mask.data <= UInt<1>("h0") - ram.T_477.mask.datablock <= UInt<1>("h0") - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_463 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_463) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_469 = and(io.enq.ready, io.enq.valid) - node T_471 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_469, T_471) - node T_473 = and(io.deq.ready, io.deq.valid) - node T_475 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_473, T_475) - when do_enq : - ram.T_477.addr <= UInt<1>("h0") - ram.T_477.en <= UInt<1>("h1") - ram.T_477.data <- io.enq.bits - ram.T_477.mask.data <= UInt<1>("h1") - ram.T_477.mask.datablock <= UInt<1>("h1") - skip - when do_deq : - skip - node T_528 = neq(do_enq, do_deq) - when T_528 : - maybe_full <= do_enq - skip - node T_530 = eq(empty, UInt<1>("h0")) - node T_532 = and(UInt<1>("h0"), io.enq.valid) - node T_533 = or(T_530, T_532) - io.deq.valid <= T_533 - node T_535 = eq(full, UInt<1>("h0")) - node T_537 = and(UInt<1>("h1"), io.deq.ready) - node T_538 = or(T_535, T_537) - io.enq.ready <= T_538 - ram.T_539.addr <= UInt<1>("h0") - ram.T_539.en <= UInt<1>("h1") - node T_588 = mux(maybe_flow, io.enq.bits, ram.T_539.data) - io.deq.bits <- T_588 - node T_637 = sub(UInt<1>("h0"), UInt<1>("h0")) - node ptr_diff = tail(T_637, 1) - node T_639 = and(maybe_full, ptr_match) - node T_640 = cat(T_639, ptr_diff) - io.count <= T_640 - module Frontend : - input clk : Clock - input reset : UInt<1> - output io : {flip cpu : { req : { valid : UInt<1>, bits : { pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io is invalid - inst btb of BTB - btb.io is invalid - btb.clk <= clk - btb.reset <= reset - inst icache of ICache - icache.io is invalid - icache.clk <= clk - icache.reset <= reset - inst tlb of TLB - tlb.io is invalid - tlb.clk <= clk - tlb.reset <= reset - reg s1_pc_ : UInt, clk with : - reset => (UInt<1>("h0"), s1_pc_) - node T_1280 = not(s1_pc_) - node T_1282 = or(T_1280, UInt<2>("h3")) - node s1_pc = not(T_1282) - reg s1_same_block : UInt<1>, clk with : - reset => (UInt<1>("h0"), s1_same_block) - reg s2_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h1")) - reg s2_pc : UInt, clk with : - reset => (reset, UInt<10>("h200")) - reg s2_btb_resp_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg s2_btb_resp_bits : { taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), s2_btb_resp_bits) - reg s2_xcpt_if : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wire s2_resp_valid : UInt<1> - s2_resp_valid <= UInt<1>("h0") - wire s2_resp_data : UInt<128> - s2_resp_data is invalid - node T_1307 = bits(btb.io.resp.bits.target, 38, 38) - node btbTarget = cat(T_1307, btb.io.resp.bits.target) - node T_1310 = add(s1_pc, UInt<3>("h4")) - node ntpc_0 = tail(T_1310, 1) - node T_1312 = bits(s1_pc, 38, 38) - node T_1313 = bits(ntpc_0, 38, 38) - node T_1314 = and(T_1312, T_1313) - node T_1315 = bits(ntpc_0, 38, 2) - node T_1317 = cat(T_1315, UInt<2>("h0")) - node ntpc = cat(T_1314, T_1317) - node T_1320 = eq(s2_resp_valid, UInt<1>("h0")) - node icmiss = and(s2_valid, T_1320) - node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc) - node npc = mux(icmiss, s2_pc, predicted_npc) - node T_1325 = eq(icmiss, UInt<1>("h0")) - node T_1327 = eq(io.cpu.req.valid, UInt<1>("h0")) - node T_1328 = and(T_1325, T_1327) - node T_1330 = eq(btb.io.resp.bits.taken, UInt<1>("h0")) - node T_1331 = and(T_1328, T_1330) - node T_1333 = and(ntpc, UInt<5>("h10")) - node T_1335 = and(s1_pc, UInt<5>("h10")) - node T_1336 = eq(T_1333, T_1335) - node s0_same_block = and(T_1331, T_1336) - node T_1339 = eq(io.cpu.resp.ready, UInt<1>("h0")) - node stall = and(io.cpu.resp.valid, T_1339) - node T_1342 = eq(stall, UInt<1>("h0")) - when T_1342 : - node T_1344 = eq(tlb.io.resp.miss, UInt<1>("h0")) - node T_1345 = and(s0_same_block, T_1344) - s1_same_block <= T_1345 - s1_pc_ <= npc - node T_1347 = eq(icmiss, UInt<1>("h0")) - s2_valid <= T_1347 - node T_1349 = eq(icmiss, UInt<1>("h0")) - when T_1349 : - s2_pc <= s1_pc - s2_btb_resp_valid <= btb.io.resp.valid - when btb.io.resp.valid : - s2_btb_resp_bits <- btb.io.resp.bits - skip - s2_xcpt_if <= tlb.io.resp.xcpt_if - skip - skip - when io.cpu.req.valid : - s1_same_block <= UInt<1>("h0") - s1_pc_ <= io.cpu.req.bits.pc - s2_valid <= UInt<1>("h0") - skip - node T_1353 = eq(stall, UInt<1>("h0")) - node T_1355 = eq(icmiss, UInt<1>("h0")) - node T_1356 = and(T_1353, T_1355) - btb.io.req.valid <= T_1356 - btb.io.req.bits.addr <= s1_pc - btb.io.btb_update <- io.cpu.btb_update - btb.io.bht_update <- io.cpu.bht_update - btb.io.ras_update <- io.cpu.ras_update - node T_1357 = or(io.cpu.invalidate, io.ptw.invalidate) - btb.io.invalidate <= T_1357 - io.ptw <- tlb.io.ptw - node T_1359 = eq(stall, UInt<1>("h0")) - node T_1361 = eq(icmiss, UInt<1>("h0")) - node T_1362 = and(T_1359, T_1361) - tlb.io.req.valid <= T_1362 - node T_1363 = shr(s1_pc, 12) - tlb.io.req.bits.vpn <= T_1363 - tlb.io.req.bits.asid <= UInt<1>("h0") - tlb.io.req.bits.passthrough <= UInt<1>("h0") - tlb.io.req.bits.instruction <= UInt<1>("h1") - tlb.io.req.bits.store <= UInt<1>("h0") - io.mem <- icache.io.mem - node T_1369 = eq(stall, UInt<1>("h0")) - node T_1371 = eq(s0_same_block, UInt<1>("h0")) - node T_1372 = and(T_1369, T_1371) - icache.io.req.valid <= T_1372 - icache.io.req.bits.idx <= io.cpu.npc - icache.io.invalidate <= io.cpu.invalidate - icache.io.req.bits.ppn <= tlb.io.resp.ppn - node T_1373 = or(io.cpu.req.valid, tlb.io.resp.miss) - node T_1374 = or(T_1373, tlb.io.resp.xcpt_if) - node T_1375 = or(T_1374, icmiss) - node T_1376 = or(T_1375, io.ptw.invalidate) - icache.io.req.bits.kill <= T_1376 - node T_1377 = or(s2_xcpt_if, s2_resp_valid) - node T_1378 = and(s2_valid, T_1377) - io.cpu.resp.valid <= T_1378 - io.cpu.resp.bits.pc <= s2_pc - node T_1379 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) - io.cpu.npc <= T_1379 - inst T_1429 of Queue_92 - T_1429.io is invalid - T_1429.clk <= clk - T_1429.reset <= reset - T_1429.io.enq <- icache.io.resp - node T_1431 = eq(stall, UInt<1>("h0")) - node T_1433 = eq(s1_same_block, UInt<1>("h0")) - node T_1434 = and(T_1431, T_1433) - T_1429.io.deq.ready <= T_1434 - s2_resp_valid <= T_1429.io.deq.valid - s2_resp_data <= T_1429.io.deq.bits.datablock - node T_1435 = bits(s2_pc, 3, 2) - node T_1436 = shl(T_1435, 5) - node fetch_data = dshr(s2_resp_data, T_1436) - node T_1438 = bits(fetch_data, 31, 0) - io.cpu.resp.bits.data[0] <= T_1438 - node T_1440 = and(UInt<2>("h3"), s2_btb_resp_bits.mask) - node T_1441 = mux(s2_btb_resp_valid, T_1440, UInt<2>("h3")) - io.cpu.resp.bits.mask <= T_1441 - io.cpu.resp.bits.xcpt_if <= s2_xcpt_if - io.cpu.btb_resp.valid <= s2_btb_resp_valid - io.cpu.btb_resp.bits <- s2_btb_resp_bits - module WritebackUnit : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - io is invalid - reg active : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg r1_data_req_fired : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg r2_data_req_fired : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg data_req_cnt : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - node T_476 = not(UInt<1>("h1")) - node beat_done = eq(T_476, UInt<1>("h0")) - node T_479 = and(io.release.ready, io.release.valid) - reg beat_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_479 : - node T_483 = eq(beat_cnt, UInt<2>("h3")) - node T_485 = and(UInt<1>("h0"), T_483) - node T_488 = add(beat_cnt, UInt<1>("h1")) - node T_489 = tail(T_488, 1) - node T_490 = mux(T_485, UInt<1>("h0"), T_489) - beat_cnt <= T_490 - skip - node all_beats_done = and(T_479, T_483) - reg req : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk with : - reset => (UInt<1>("h0"), req) - io.release.valid <= UInt<1>("h0") - when active : - r1_data_req_fired <= UInt<1>("h0") - r2_data_req_fired <= r1_data_req_fired - node T_556 = and(io.data_req.ready, io.data_req.valid) - node T_557 = and(io.meta_read.ready, io.meta_read.valid) - node T_558 = and(T_556, T_557) - when T_558 : - r1_data_req_fired <= UInt<1>("h1") - node T_561 = add(data_req_cnt, UInt<1>("h1")) - node T_562 = tail(T_561, 1) - data_req_cnt <= T_562 - skip - when r2_data_req_fired : - io.release.valid <= beat_done - when beat_done : - node T_564 = eq(io.release.ready, UInt<1>("h0")) - when T_564 : - r1_data_req_fired <= UInt<1>("h0") - r2_data_req_fired <= UInt<1>("h0") - node T_568 = and(UInt<1>("h1"), r1_data_req_fired) - node T_571 = mux(T_568, UInt<2>("h2"), UInt<1>("h1")) - node T_572 = sub(data_req_cnt, T_571) - node T_573 = tail(T_572, 1) - data_req_cnt <= T_573 - skip - node T_575 = eq(T_564, UInt<1>("h0")) - when T_575 : - skip - skip - node T_577 = eq(r1_data_req_fired, UInt<1>("h0")) - when T_577 : - node T_579 = lt(data_req_cnt, UInt<3>("h4")) - node T_581 = eq(io.release.ready, UInt<1>("h0")) - node T_582 = or(T_579, T_581) - active <= T_582 - skip - skip - skip - node T_583 = and(io.req.ready, io.req.valid) - when T_583 : - active <= UInt<1>("h1") - data_req_cnt <= UInt<1>("h0") - req <- io.req.bits - skip - node T_587 = eq(active, UInt<1>("h0")) - io.req.ready <= T_587 - node req_idx = bits(req.addr_block, 5, 0) - node T_590 = lt(data_req_cnt, UInt<3>("h4")) - node fire = and(active, T_590) - io.meta_read.valid <= fire - io.meta_read.bits.idx <= req_idx - node T_592 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_592 - io.data_req.valid <= fire - io.data_req.bits.way_en <= req.way_en - node T_593 = bits(data_req_cnt, 1, 0) - node T_594 = cat(req_idx, T_593) - node T_595 = shl(T_594, 4) - io.data_req.bits.addr <= T_595 - io.release.bits <- req - io.release.bits.addr_beat <= beat_cnt - io.release.bits.data <= io.data_resp - module ProbeUnit : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : { state : UInt<2>}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg old_coh : { state : UInt<2>}, clk with : - reset => (UInt<1>("h0"), old_coh) - reg way_en : UInt, clk with : - reset => (UInt<1>("h0"), way_en) - reg req : { addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk with : - reset => (UInt<1>("h0"), req) - node tag_matches = neq(way_en, UInt<1>("h0")) - wire miss_coh : { state : UInt<2>} - miss_coh is invalid - miss_coh.state <= UInt<1>("h0") - node reply_coh = mux(tag_matches, old_coh, miss_coh) - wire T_947 : UInt<2>[1] - T_947[0] <= UInt<2>("h3") - node T_950 = eq(T_947[0], reply_coh.state) - node T_952 = or(UInt<1>("h0"), T_950) - node T_953 = mux(T_952, UInt<1>("h0"), UInt<2>("h3")) - node T_954 = mux(T_952, UInt<1>("h1"), UInt<3>("h4")) - node T_955 = mux(T_952, UInt<2>("h2"), UInt<3>("h5")) - node T_956 = eq(UInt<5>("h13"), UInt<5>("h10")) - node T_957 = mux(T_956, T_955, UInt<3>("h5")) - node T_958 = eq(UInt<5>("h11"), UInt<5>("h10")) - node T_959 = mux(T_958, T_954, T_957) - node T_960 = eq(UInt<5>("h10"), UInt<5>("h10")) - node T_961 = mux(T_960, T_953, T_959) - wire T_963 : UInt<2>[1] - T_963[0] <= UInt<2>("h3") - node T_966 = eq(T_963[0], reply_coh.state) - node T_968 = or(UInt<1>("h0"), T_966) - node T_969 = mux(T_968, UInt<1>("h0"), UInt<2>("h3")) - node T_970 = mux(T_968, UInt<1>("h1"), UInt<3>("h4")) - node T_971 = mux(T_968, UInt<2>("h2"), UInt<3>("h5")) - node T_972 = eq(UInt<5>("h13"), UInt<5>("h11")) - node T_973 = mux(T_972, T_971, UInt<3>("h5")) - node T_974 = eq(UInt<5>("h11"), UInt<5>("h11")) - node T_975 = mux(T_974, T_970, T_973) - node T_976 = eq(UInt<5>("h10"), UInt<5>("h11")) - node T_977 = mux(T_976, T_969, T_975) - wire T_979 : UInt<2>[1] - T_979[0] <= UInt<2>("h3") - node T_982 = eq(T_979[0], reply_coh.state) - node T_984 = or(UInt<1>("h0"), T_982) - node T_985 = mux(T_984, UInt<1>("h0"), UInt<2>("h3")) - node T_986 = mux(T_984, UInt<1>("h1"), UInt<3>("h4")) - node T_987 = mux(T_984, UInt<2>("h2"), UInt<3>("h5")) - node T_988 = eq(UInt<5>("h13"), UInt<5>("h13")) - node T_989 = mux(T_988, T_987, UInt<3>("h5")) - node T_990 = eq(UInt<5>("h11"), UInt<5>("h13")) - node T_991 = mux(T_990, T_986, T_989) - node T_992 = eq(UInt<5>("h10"), UInt<5>("h13")) - node T_993 = mux(T_992, T_985, T_991) - node T_994 = eq(UInt<2>("h2"), req.p_type) - node T_995 = mux(T_994, T_993, UInt<2>("h3")) - node T_996 = eq(UInt<1>("h1"), req.p_type) - node T_997 = mux(T_996, T_977, T_995) - node T_998 = eq(UInt<1>("h0"), req.p_type) - node T_999 = mux(T_998, T_961, T_997) - wire reply : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - reply is invalid - reply.r_type <= T_999 - reply.client_xact_id <= UInt<1>("h0") - reply.addr_block <= req.addr_block - reply.addr_beat <= UInt<1>("h0") - reply.data <= UInt<1>("h0") - reply.voluntary <= UInt<1>("h0") - node T_1061 = eq(state, UInt<1>("h0")) - io.req.ready <= T_1061 - node T_1062 = eq(state, UInt<3>("h5")) - io.rep.valid <= T_1062 - io.rep.bits <- reply - node T_1064 = eq(io.rep.valid, UInt<1>("h0")) - wire T_1066 : UInt<2>[3] - T_1066[0] <= UInt<1>("h0") - T_1066[1] <= UInt<1>("h1") - T_1066[2] <= UInt<2>("h2") - node T_1071 = eq(T_1066[0], io.rep.bits.r_type) - node T_1072 = eq(T_1066[1], io.rep.bits.r_type) - node T_1073 = eq(T_1066[2], io.rep.bits.r_type) - node T_1075 = or(UInt<1>("h0"), T_1071) - node T_1076 = or(T_1075, T_1072) - node T_1077 = or(T_1076, T_1073) - node T_1079 = eq(T_1077, UInt<1>("h0")) - node T_1080 = or(T_1064, T_1079) - node T_1082 = eq(reset, UInt<1>("h0")) - when T_1082 : - node T_1084 = eq(T_1080, UInt<1>("h0")) - when T_1084 : - node T_1086 = eq(reset, UInt<1>("h0")) - when T_1086 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - node T_1087 = eq(state, UInt<1>("h1")) - io.meta_read.valid <= T_1087 - io.meta_read.bits.idx <= req.addr_block - node T_1088 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_1088 - node T_1089 = eq(state, UInt<4>("h8")) - io.meta_write.valid <= T_1089 - io.meta_write.bits.way_en <= way_en - io.meta_write.bits.idx <= req.addr_block - node T_1090 = shr(req.addr_block, 6) - io.meta_write.bits.data.tag <= T_1090 - node T_1091 = eq(UInt<2>("h2"), req.p_type) - node T_1092 = mux(T_1091, old_coh.state, old_coh.state) - node T_1093 = eq(UInt<1>("h1"), req.p_type) - node T_1094 = mux(T_1093, UInt<1>("h1"), T_1092) - node T_1095 = eq(UInt<1>("h0"), req.p_type) - node T_1096 = mux(T_1095, UInt<1>("h0"), T_1094) - wire T_1122 : { state : UInt<2>} - T_1122 is invalid - T_1122.state <= T_1096 - io.meta_write.bits.data.coh <- T_1122 - node T_1147 = eq(state, UInt<3>("h6")) - io.wb_req.valid <= T_1147 - io.wb_req.bits <- reply - io.wb_req.bits.way_en <= way_en - node T_1148 = and(io.req.ready, io.req.valid) - when T_1148 : - state <= UInt<1>("h1") - req <- io.req.bits - skip - node T_1149 = and(io.meta_read.ready, io.meta_read.valid) - when T_1149 : - state <= UInt<2>("h2") - skip - node T_1150 = eq(state, UInt<2>("h2")) - when T_1150 : - state <= UInt<2>("h3") - skip - node T_1151 = eq(state, UInt<2>("h3")) - when T_1151 : - state <= UInt<3>("h4") - old_coh <- io.block_state - way_en <= io.way_en - node T_1153 = eq(io.mshr_rdy, UInt<1>("h0")) - when T_1153 : - state <= UInt<1>("h1") - skip - skip - node T_1154 = eq(state, UInt<3>("h4")) - when T_1154 : - wire T_1156 : UInt<2>[1] - T_1156[0] <= UInt<2>("h3") - node T_1159 = eq(T_1156[0], old_coh.state) - node T_1161 = or(UInt<1>("h0"), T_1159) - node T_1162 = and(tag_matches, T_1161) - node T_1163 = mux(T_1162, UInt<3>("h6"), UInt<3>("h5")) - state <= T_1163 - skip - node T_1164 = eq(state, UInt<3>("h5")) - node T_1165 = and(T_1164, io.rep.ready) - when T_1165 : - node T_1166 = mux(tag_matches, UInt<4>("h8"), UInt<1>("h0")) - state <= T_1166 - skip - node T_1167 = and(io.wb_req.ready, io.wb_req.valid) - when T_1167 : - state <= UInt<3>("h7") - skip - node T_1168 = eq(state, UInt<3>("h7")) - node T_1169 = and(T_1168, io.wb_req.ready) - when T_1169 : - state <= UInt<4>("h8") - skip - node T_1170 = and(io.meta_write.ready, io.meta_write.valid) - when T_1170 : - state <= UInt<1>("h0") - skip - module Arbiter_93 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>} - io is invalid - wire T_108 : UInt<1> - T_108 is invalid - io.out.valid <= io.in[T_108].valid - io.out.bits <- io.in[T_108].bits - io.chosen <= T_108 - io.in[T_108].ready <= UInt<1>("h0") - node T_139 = or(UInt<1>("h0"), io.in[0].valid) - node T_141 = eq(T_139, UInt<1>("h0")) - node T_143 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_144 = mux(UInt<1>("h0"), T_143, UInt<1>("h1")) - node T_145 = and(T_144, io.out.ready) - io.in[0].ready <= T_145 - node T_147 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_148 = mux(UInt<1>("h0"), T_147, T_141) - node T_149 = and(T_148, io.out.ready) - io.in[1].ready <= T_149 - node T_152 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_153 = mux(UInt<1>("h0"), UInt<1>("h1"), T_152) - T_108 <= T_153 - module Arbiter_94 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, chosen : UInt<1>} - io is invalid - wire T_1714 : UInt<1> - T_1714 is invalid - io.out.valid <= io.in[T_1714].valid - io.out.bits <- io.in[T_1714].bits - io.chosen <= T_1714 - io.in[T_1714].ready <= UInt<1>("h0") - node T_2183 = or(UInt<1>("h0"), io.in[0].valid) - node T_2185 = eq(T_2183, UInt<1>("h0")) - node T_2187 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2188 = mux(UInt<1>("h0"), T_2187, UInt<1>("h1")) - node T_2189 = and(T_2188, io.out.ready) - io.in[0].ready <= T_2189 - node T_2191 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_2192 = mux(UInt<1>("h0"), T_2191, T_2185) - node T_2193 = and(T_2192, io.out.ready) - io.in[1].ready <= T_2193 - node T_2196 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_2197 = mux(UInt<1>("h0"), UInt<1>("h1"), T_2196) - T_1714 <= T_2197 - module LockingArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<2>} - io is invalid - reg T_852 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_854 : UInt, clk with : - reset => (reset, UInt<2>("h2")) - wire T_856 : UInt<2> - T_856 is invalid - io.out.valid <= io.in[T_856].valid - io.out.bits <- io.in[T_856].bits - io.chosen <= T_856 - io.in[T_856].ready <= UInt<1>("h0") - node T_1055 = or(UInt<1>("h0"), io.in[0].valid) - node T_1057 = eq(T_1055, UInt<1>("h0")) - node T_1059 = or(UInt<1>("h0"), io.in[0].valid) - node T_1060 = or(T_1059, io.in[1].valid) - node T_1062 = eq(T_1060, UInt<1>("h0")) - node T_1064 = eq(T_854, UInt<1>("h0")) - node T_1065 = mux(T_852, T_1064, UInt<1>("h1")) - node T_1066 = and(T_1065, io.out.ready) - io.in[0].ready <= T_1066 - node T_1068 = eq(T_854, UInt<1>("h1")) - node T_1069 = mux(T_852, T_1068, T_1057) - node T_1070 = and(T_1069, io.out.ready) - io.in[1].ready <= T_1070 - node T_1072 = eq(T_854, UInt<2>("h2")) - node T_1073 = mux(T_852, T_1072, T_1062) - node T_1074 = and(T_1073, io.out.ready) - io.in[2].ready <= T_1074 - reg T_1076 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_1078 = add(T_1076, UInt<1>("h1")) - node T_1079 = tail(T_1078, 1) - node T_1080 = and(io.out.ready, io.out.valid) - when T_1080 : - node T_1082 = and(UInt<1>("h1"), io.out.bits.is_builtin_type) - wire T_1085 : UInt<3>[1] - T_1085[0] <= UInt<3>("h3") - node T_1088 = eq(T_1085[0], io.out.bits.a_type) - node T_1090 = or(UInt<1>("h0"), T_1088) - node T_1091 = and(T_1082, T_1090) - when T_1091 : - T_1076 <= T_1079 - node T_1093 = eq(T_852, UInt<1>("h0")) - when T_1093 : - T_852 <= UInt<1>("h1") - node T_1095 = and(io.in[0].ready, io.in[0].valid) - node T_1096 = and(io.in[1].ready, io.in[1].valid) - node T_1097 = and(io.in[2].ready, io.in[2].valid) - wire T_1099 : UInt<1>[3] - T_1099[0] <= T_1095 - T_1099[1] <= T_1096 - T_1099[2] <= T_1097 - node T_1107 = mux(T_1099[1], UInt<1>("h1"), UInt<2>("h2")) - node T_1108 = mux(T_1099[0], UInt<1>("h0"), T_1107) - T_854 <= T_1108 - skip - skip - node T_1110 = eq(T_1079, UInt<1>("h0")) - when T_1110 : - T_852 <= UInt<1>("h0") - skip - skip - node T_1114 = mux(io.in[1].valid, UInt<1>("h1"), UInt<2>("h2")) - node choose = mux(io.in[0].valid, UInt<1>("h0"), T_1114) - node T_1117 = mux(T_852, T_854, choose) - T_856 <= T_1117 - module Arbiter_95 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, chosen : UInt<1>} - io is invalid - wire T_724 : UInt<1> - T_724 is invalid - io.out.valid <= io.in[T_724].valid - io.out.bits <- io.in[T_724].bits - io.chosen <= T_724 - io.in[T_724].ready <= UInt<1>("h0") - node T_923 = or(UInt<1>("h0"), io.in[0].valid) - node T_925 = eq(T_923, UInt<1>("h0")) - node T_927 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_928 = mux(UInt<1>("h0"), T_927, UInt<1>("h1")) - node T_929 = and(T_928, io.out.ready) - io.in[0].ready <= T_929 - node T_931 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_932 = mux(UInt<1>("h0"), T_931, T_925) - node T_933 = and(T_932, io.out.ready) - io.in[1].ready <= T_933 - node T_936 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_937 = mux(UInt<1>("h0"), UInt<1>("h1"), T_936) - T_724 <= T_937 - module Arbiter_96 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>} - io is invalid - wire T_1230 : UInt<1> - T_1230 is invalid - io.out.valid <= io.in[T_1230].valid - io.out.bits <- io.in[T_1230].bits - io.chosen <= T_1230 - io.in[T_1230].ready <= UInt<1>("h0") - node T_1567 = or(UInt<1>("h0"), io.in[0].valid) - node T_1569 = eq(T_1567, UInt<1>("h0")) - node T_1571 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_1572 = mux(UInt<1>("h0"), T_1571, UInt<1>("h1")) - node T_1573 = and(T_1572, io.out.ready) - io.in[0].ready <= T_1573 - node T_1575 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_1576 = mux(UInt<1>("h0"), T_1575, T_1569) - node T_1577 = and(T_1576, io.out.ready) - io.in[1].ready <= T_1577 - node T_1580 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_1581 = mux(UInt<1>("h0"), UInt<1>("h1"), T_1580) - T_1230 <= T_1581 - module Arbiter_97 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} - io is invalid - wire T_64 : UInt<1> - T_64 is invalid - io.out.valid <= io.in[T_64].valid - io.out.bits <= io.in[T_64].bits - io.chosen <= T_64 - io.in[T_64].ready <= UInt<1>("h0") - node T_83 = or(UInt<1>("h0"), io.in[0].valid) - node T_85 = eq(T_83, UInt<1>("h0")) - node T_87 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_88 = mux(UInt<1>("h0"), T_87, UInt<1>("h1")) - node T_89 = and(T_88, io.out.ready) - io.in[0].ready <= T_89 - node T_91 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_92 = mux(UInt<1>("h0"), T_91, T_85) - node T_93 = and(T_92, io.out.ready) - io.in[1].ready <= T_93 - node T_96 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_97 = mux(UInt<1>("h0"), UInt<1>("h1"), T_96) - T_64 <= T_97 - module Queue_98 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>} - io is invalid - mem ram : - data-type => { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} - depth => 16 - write-latency => 1 - read-latency => 0 - reader => T_607 - writer => T_524 - ram.T_607.addr is invalid - ram.T_607.clk <= clk - ram.T_607.en <= UInt<1>("h0") - ram.T_524.addr is invalid - ram.T_524.clk <= clk - ram.T_524.en <= UInt<1>("h0") - ram.T_524.data is invalid - ram.T_524.mask.addr <= UInt<1>("h0") - ram.T_524.mask.tag <= UInt<1>("h0") - ram.T_524.mask.cmd <= UInt<1>("h0") - ram.T_524.mask.typ <= UInt<1>("h0") - ram.T_524.mask.kill <= UInt<1>("h0") - ram.T_524.mask.phys <= UInt<1>("h0") - ram.T_524.mask.sdq_id <= UInt<1>("h0") - reg T_503 : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - reg T_505 : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_503, T_505) - node T_510 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_510) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_516 = and(io.enq.ready, io.enq.valid) - node T_518 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_516, T_518) - node T_520 = and(io.deq.ready, io.deq.valid) - node T_522 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_520, T_522) - when do_enq : - ram.T_524.addr <= T_503 - ram.T_524.en <= UInt<1>("h1") - ram.T_524.data <- io.enq.bits - ram.T_524.mask.addr <= UInt<1>("h1") - ram.T_524.mask.tag <= UInt<1>("h1") - ram.T_524.mask.cmd <= UInt<1>("h1") - ram.T_524.mask.typ <= UInt<1>("h1") - ram.T_524.mask.kill <= UInt<1>("h1") - ram.T_524.mask.phys <= UInt<1>("h1") - ram.T_524.mask.sdq_id <= UInt<1>("h1") - node T_579 = eq(T_503, UInt<4>("hf")) - node T_581 = and(UInt<1>("h0"), T_579) - node T_584 = add(T_503, UInt<1>("h1")) - node T_585 = tail(T_584, 1) - node T_586 = mux(T_581, UInt<1>("h0"), T_585) - T_503 <= T_586 - skip - when do_deq : - node T_588 = eq(T_505, UInt<4>("hf")) - node T_590 = and(UInt<1>("h0"), T_588) - node T_593 = add(T_505, UInt<1>("h1")) - node T_594 = tail(T_593, 1) - node T_595 = mux(T_590, UInt<1>("h0"), T_594) - T_505 <= T_595 - skip - node T_596 = neq(do_enq, do_deq) - when T_596 : - maybe_full <= do_enq - skip - node T_598 = eq(empty, UInt<1>("h0")) - node T_600 = and(UInt<1>("h0"), io.enq.valid) - node T_601 = or(T_598, T_600) - io.deq.valid <= T_601 - node T_603 = eq(full, UInt<1>("h0")) - node T_605 = and(UInt<1>("h0"), io.deq.ready) - node T_606 = or(T_603, T_605) - io.enq.ready <= T_606 - ram.T_607.addr <= T_505 - ram.T_607.en <= UInt<1>("h1") - node T_661 = mux(maybe_flow, io.enq.bits, ram.T_607.data) - io.deq.bits <- T_661 - node T_715 = sub(T_503, T_505) - node ptr_diff = tail(T_715, 1) - node T_717 = and(maybe_full, ptr_match) - node T_718 = cat(T_717, ptr_diff) - io.count <= T_718 - module MSHR : - input clk : Clock - input reset : UInt<1> - output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { tag : UInt<20>, coh : { state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : { way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : { valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - wire T_1277 : { state : UInt<2>} - T_1277 is invalid - T_1277.state <= UInt<1>("h0") - reg new_coh_state : { state : UInt<2>}, clk with : - reset => (reset, T_1277) - reg req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { tag : UInt<20>, coh : { state : UInt<2>}}, way_en : UInt<4>}, clk with : - reset => (UInt<1>("h0"), req) - node req_idx = bits(req.addr, 11, 6) - node T_1586 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1586) - node T_1588 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1590 = or(T_1588, T_1589) - node T_1591 = bits(io.req_bits.cmd, 3, 3) - node T_1592 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1593 = or(T_1591, T_1592) - node T_1594 = or(T_1590, T_1593) - node T_1595 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1596 = or(T_1594, T_1595) - node T_1597 = eq(io.req_bits.cmd, UInt<5>("h6")) - node T_1598 = or(T_1596, T_1597) - node T_1599 = eq(req.cmd, UInt<5>("h1")) - node T_1600 = eq(req.cmd, UInt<5>("h7")) - node T_1601 = or(T_1599, T_1600) - node T_1602 = bits(req.cmd, 3, 3) - node T_1603 = eq(req.cmd, UInt<5>("h4")) - node T_1604 = or(T_1602, T_1603) - node T_1605 = or(T_1601, T_1604) - node T_1606 = eq(req.cmd, UInt<5>("h3")) - node T_1607 = or(T_1605, T_1606) - node T_1608 = eq(req.cmd, UInt<5>("h6")) - node T_1609 = or(T_1607, T_1608) - node T_1611 = eq(T_1609, UInt<1>("h0")) - node cmd_requires_second_acquire = and(T_1598, T_1611) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] <= UInt<1>("h1") - states_before_refill[1] <= UInt<2>("h2") - states_before_refill[2] <= UInt<2>("h3") - node T_1619 = eq(states_before_refill[0], state) - node T_1620 = eq(states_before_refill[1], state) - node T_1621 = eq(states_before_refill[2], state) - node T_1623 = or(UInt<1>("h0"), T_1619) - node T_1624 = or(T_1623, T_1620) - node T_1625 = or(T_1624, T_1621) - wire T_1627 : UInt<3>[2] - T_1627[0] <= UInt<3>("h4") - T_1627[1] <= UInt<3>("h5") - node T_1631 = eq(T_1627[0], state) - node T_1632 = eq(T_1627[1], state) - node T_1634 = or(UInt<1>("h0"), T_1631) - node T_1635 = or(T_1634, T_1632) - node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h0")) - node T_1638 = and(T_1635, T_1637) - node T_1639 = or(T_1625, T_1638) - node sec_rdy = and(idx_match, T_1639) - wire T_1644 : UInt<3>[1] - T_1644[0] <= UInt<3>("h5") - node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) - node T_1649 = or(UInt<1>("h0"), T_1647) - wire T_1651 : UInt<1>[2] - T_1651[0] <= UInt<1>("h0") - T_1651[1] <= UInt<1>("h1") - node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) - node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) - node T_1658 = or(UInt<1>("h0"), T_1655) - node T_1659 = or(T_1658, T_1656) - node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) - node gnt_multi_data = and(UInt<1>("h1"), T_1660) - node T_1662 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1662 : - node T_1666 = eq(refill_cnt, UInt<2>("h3")) - node T_1668 = and(UInt<1>("h0"), T_1666) - node T_1671 = add(refill_cnt, UInt<1>("h1")) - node T_1672 = tail(T_1671, 1) - node T_1673 = mux(T_1668, UInt<1>("h0"), T_1672) - refill_cnt <= T_1673 - skip - node refill_count_done = and(T_1662, T_1666) - node T_1676 = eq(gnt_multi_data, UInt<1>("h0")) - node T_1677 = or(T_1676, refill_count_done) - node refill_done = and(io.mem_grant.valid, T_1677) - inst rpq of Queue_98 - rpq.io is invalid - rpq.clk <= clk - rpq.reset <= reset - node T_1734 = and(io.req_pri_val, io.req_pri_rdy) - node T_1735 = and(io.req_sec_val, sec_rdy) - node T_1736 = or(T_1734, T_1735) - node T_1737 = eq(io.req_bits.cmd, UInt<5>("h2")) - node T_1738 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1739 = or(T_1737, T_1738) - node T_1741 = eq(T_1739, UInt<1>("h0")) - node T_1742 = and(T_1736, T_1741) - rpq.io.enq.valid <= T_1742 - rpq.io.enq.bits <- io.req_bits - node T_1743 = eq(state, UInt<4>("h8")) - node T_1744 = and(io.replay.ready, T_1743) - node T_1745 = eq(state, UInt<1>("h0")) - node T_1746 = or(T_1744, T_1745) - rpq.io.deq.ready <= T_1746 - node T_1747 = eq(req.cmd, UInt<5>("h1")) - node T_1748 = eq(req.cmd, UInt<5>("h7")) - node T_1749 = or(T_1747, T_1748) - node T_1750 = bits(req.cmd, 3, 3) - node T_1751 = eq(req.cmd, UInt<5>("h4")) - node T_1752 = or(T_1750, T_1751) - node T_1753 = or(T_1749, T_1752) - node T_1754 = mux(T_1753, UInt<2>("h3"), UInt<2>("h2")) - node T_1755 = eq(UInt<2>("h2"), io.mem_grant.bits.g_type) - node T_1756 = mux(T_1755, UInt<2>("h3"), UInt<1>("h0")) - node T_1757 = eq(UInt<1>("h1"), io.mem_grant.bits.g_type) - node T_1758 = mux(T_1757, T_1754, T_1756) - node T_1759 = eq(UInt<1>("h0"), io.mem_grant.bits.g_type) - node T_1760 = mux(T_1759, UInt<1>("h1"), T_1758) - node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h0"), T_1760) - wire coh_on_grant : { state : UInt<2>} - coh_on_grant is invalid - coh_on_grant.state <= T_1761 - node T_1812 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1813 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = bits(io.req_bits.cmd, 3, 3) - node T_1816 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1817 = or(T_1815, T_1816) - node T_1818 = or(T_1814, T_1817) - node T_1819 = mux(T_1818, UInt<2>("h3"), io.req_bits.old_meta.coh.state) - wire coh_on_hit : { state : UInt<2>} - coh_on_hit is invalid - coh_on_hit.state <= T_1819 - node T_1870 = eq(state, UInt<4>("h8")) - node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h0")) - node T_1873 = and(T_1870, T_1872) - when T_1873 : - state <= UInt<1>("h0") - skip - node T_1874 = eq(state, UInt<3>("h7")) - when T_1874 : - state <= UInt<4>("h8") - skip - node T_1875 = eq(state, UInt<3>("h6")) - node T_1876 = and(T_1875, io.meta_write.ready) - when T_1876 : - state <= UInt<3>("h7") - skip - node T_1877 = eq(state, UInt<3>("h5")) - when T_1877 : - when io.mem_grant.valid : - new_coh_state <- coh_on_grant - skip - when refill_done : - state <= UInt<3>("h6") - skip - skip - node T_1878 = and(io.mem_req.ready, io.mem_req.valid) - when T_1878 : - state <= UInt<3>("h5") - skip - node T_1879 = eq(state, UInt<2>("h3")) - node T_1880 = and(T_1879, io.meta_write.ready) - when T_1880 : - state <= UInt<3>("h4") - skip - node T_1881 = eq(state, UInt<2>("h2")) - node T_1882 = and(T_1881, io.mem_grant.valid) - when T_1882 : - state <= UInt<2>("h3") - skip - node T_1883 = and(io.wb_req.ready, io.wb_req.valid) - when T_1883 : - node T_1886 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1887 = mux(T_1886, UInt<2>("h2"), UInt<2>("h3")) - state <= T_1887 - skip - node T_1888 = and(io.req_sec_val, io.req_sec_rdy) - when T_1888 : - when cmd_requires_second_acquire : - req.cmd <= io.req_bits.cmd - skip - skip - node T_1889 = and(io.req_pri_val, io.req_pri_rdy) - when T_1889 : - req <- io.req_bits - when io.req_bits.tag_match : - node T_1890 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1891 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1892 = or(T_1890, T_1891) - node T_1893 = bits(io.req_bits.cmd, 3, 3) - node T_1894 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1895 = or(T_1893, T_1894) - node T_1896 = or(T_1892, T_1895) - node T_1897 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1898 = or(T_1896, T_1897) - node T_1899 = eq(io.req_bits.cmd, UInt<5>("h6")) - node T_1900 = or(T_1898, T_1899) - wire T_1902 : UInt<2>[2] - T_1902[0] <= UInt<2>("h2") - T_1902[1] <= UInt<2>("h3") - node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) - node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) - node T_1909 = or(UInt<1>("h0"), T_1906) - node T_1910 = or(T_1909, T_1907) - wire T_1912 : UInt<2>[3] - T_1912[0] <= UInt<1>("h1") - T_1912[1] <= UInt<2>("h2") - T_1912[2] <= UInt<2>("h3") - node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) - node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) - node T_1921 = or(UInt<1>("h0"), T_1917) - node T_1922 = or(T_1921, T_1918) - node T_1923 = or(T_1922, T_1919) - node T_1924 = mux(T_1900, T_1910, T_1923) - when T_1924 : - state <= UInt<3>("h6") - new_coh_state <- coh_on_hit - skip - node T_1926 = eq(T_1924, UInt<1>("h0")) - when T_1926 : - state <= UInt<3>("h4") - skip - skip - node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h0")) - when T_1928 : - wire T_1930 : UInt<2>[1] - T_1930[0] <= UInt<2>("h3") - node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) - node T_1935 = or(UInt<1>("h0"), T_1933) - node T_1936 = mux(T_1935, UInt<1>("h1"), UInt<2>("h3")) - state <= T_1936 - skip - skip - node T_1937 = neq(state, UInt<1>("h0")) - node T_1938 = and(T_1937, idx_match) - io.idx_match <= T_1938 - io.refill.way_en <= req.way_en - node T_1939 = cat(req_idx, refill_cnt) - node T_1940 = shl(T_1939, 4) - io.refill.addr <= T_1940 - node T_1941 = shr(req.addr, 12) - io.tag <= T_1941 - node T_1942 = eq(state, UInt<1>("h0")) - io.req_pri_rdy <= T_1942 - node T_1943 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1943 - reg meta_hazard : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_1947 = neq(meta_hazard, UInt<1>("h0")) - when T_1947 : - node T_1949 = add(meta_hazard, UInt<1>("h1")) - node T_1950 = tail(T_1949, 1) - meta_hazard <= T_1950 - skip - node T_1951 = and(io.meta_write.ready, io.meta_write.valid) - when T_1951 : - meta_hazard <= UInt<1>("h1") - skip - node T_1954 = eq(idx_match, UInt<1>("h0")) - node T_1955 = eq(states_before_refill[0], state) - node T_1956 = eq(states_before_refill[1], state) - node T_1957 = eq(states_before_refill[2], state) - node T_1959 = or(UInt<1>("h0"), T_1955) - node T_1960 = or(T_1959, T_1956) - node T_1961 = or(T_1960, T_1957) - node T_1963 = eq(T_1961, UInt<1>("h0")) - node T_1965 = eq(meta_hazard, UInt<1>("h0")) - node T_1966 = and(T_1963, T_1965) - node T_1967 = or(T_1954, T_1966) - io.probe_rdy <= T_1967 - node T_1968 = eq(state, UInt<3>("h6")) - node T_1969 = eq(state, UInt<2>("h3")) - node T_1970 = or(T_1968, T_1969) - io.meta_write.valid <= T_1970 - io.meta_write.bits.idx <= req_idx - node T_1971 = eq(state, UInt<2>("h3")) - wire T_1973 : UInt<2>[2] - T_1973[0] <= UInt<2>("h2") - T_1973[1] <= UInt<2>("h3") - node T_1977 = eq(T_1973[0], req.old_meta.coh.state) - node T_1978 = eq(T_1973[1], req.old_meta.coh.state) - node T_1980 = or(UInt<1>("h0"), T_1977) - node T_1981 = or(T_1980, T_1978) - node T_1982 = mux(T_1981, UInt<1>("h1"), req.old_meta.coh.state) - node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h3")) - node T_1984 = mux(T_1983, UInt<2>("h2"), req.old_meta.coh.state) - node T_1985 = eq(UInt<5>("h13"), UInt<5>("h10")) - node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) - node T_1987 = eq(UInt<5>("h11"), UInt<5>("h10")) - node T_1988 = mux(T_1987, T_1982, T_1986) - node T_1989 = eq(UInt<5>("h10"), UInt<5>("h10")) - node T_1990 = mux(T_1989, UInt<1>("h0"), T_1988) - wire T_2016 : { state : UInt<2>} - T_2016 is invalid - T_2016.state <= T_1990 - node T_2041 = mux(T_1971, T_2016, new_coh_state) - io.meta_write.bits.data.coh <- T_2041 - io.meta_write.bits.data.tag <= io.tag - io.meta_write.bits.way_en <= req.way_en - node T_2066 = eq(state, UInt<1>("h1")) - io.wb_req.valid <= T_2066 - node T_2068 = cat(req.old_meta.tag, req_idx) - wire T_2073 : UInt<2>[1] - T_2073[0] <= UInt<2>("h3") - node T_2076 = eq(T_2073[0], req.old_meta.coh.state) - node T_2078 = or(UInt<1>("h0"), T_2076) - node T_2079 = mux(T_2078, UInt<1>("h0"), UInt<2>("h3")) - node T_2080 = mux(T_2078, UInt<1>("h1"), UInt<3>("h4")) - node T_2081 = mux(T_2078, UInt<2>("h2"), UInt<3>("h5")) - node T_2082 = eq(UInt<5>("h13"), UInt<5>("h10")) - node T_2083 = mux(T_2082, T_2081, UInt<3>("h5")) - node T_2084 = eq(UInt<5>("h11"), UInt<5>("h10")) - node T_2085 = mux(T_2084, T_2080, T_2083) - node T_2086 = eq(UInt<5>("h10"), UInt<5>("h10")) - node T_2087 = mux(T_2086, T_2079, T_2085) - wire T_2118 : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2118 is invalid - T_2118.r_type <= T_2087 - T_2118.client_xact_id <= UInt<1>("h0") - T_2118.addr_block <= T_2068 - T_2118.addr_beat <= UInt<1>("h0") - T_2118.data <= UInt<1>("h0") - T_2118.voluntary <= UInt<1>("h1") - io.wb_req.bits <- T_2118 - io.wb_req.bits.way_en <= req.way_en - node T_2148 = eq(state, UInt<3>("h4")) - io.mem_req.valid <= T_2148 - node T_2149 = cat(io.tag, req_idx) - node T_2152 = eq(req.cmd, UInt<5>("h1")) - node T_2153 = eq(req.cmd, UInt<5>("h7")) - node T_2154 = or(T_2152, T_2153) - node T_2155 = bits(req.cmd, 3, 3) - node T_2156 = eq(req.cmd, UInt<5>("h4")) - node T_2157 = or(T_2155, T_2156) - node T_2158 = or(T_2154, T_2157) - node T_2159 = eq(req.cmd, UInt<5>("h3")) - node T_2160 = or(T_2158, T_2159) - node T_2161 = eq(req.cmd, UInt<5>("h6")) - node T_2162 = or(T_2160, T_2161) - node T_2163 = mux(T_2162, UInt<1>("h1"), UInt<1>("h0")) - node T_2165 = cat(req.cmd, UInt<1>("h1")) - wire T_2199 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2199 is invalid - T_2199.is_builtin_type <= UInt<1>("h0") - T_2199.a_type <= T_2163 - T_2199.client_xact_id <= UInt<1>("h0") - T_2199.addr_block <= T_2149 - T_2199.addr_beat <= UInt<1>("h0") - T_2199.data <= UInt<1>("h0") - T_2199.union <= T_2165 - io.mem_req.bits <- T_2199 - node T_2230 = eq(state, UInt<4>("h8")) - io.meta_read.valid <= T_2230 - io.meta_read.bits.idx <= req_idx - io.meta_read.bits.tag <= io.tag - node T_2231 = eq(state, UInt<4>("h8")) - node T_2232 = and(T_2231, rpq.io.deq.valid) - io.replay.valid <= T_2232 - io.replay.bits <- rpq.io.deq.bits - io.replay.bits.phys <= UInt<1>("h1") - node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2235 = cat(req_idx, T_2234) - node T_2236 = cat(io.tag, T_2235) - io.replay.bits.addr <= T_2236 - node T_2238 = eq(io.meta_read.ready, UInt<1>("h0")) - when T_2238 : - rpq.io.deq.ready <= UInt<1>("h0") - io.replay.bits.cmd <= UInt<5>("h5") - skip - module MSHR_99 : - input clk : Clock - input reset : UInt<1> - output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { tag : UInt<20>, coh : { state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : { way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : { valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - wire T_1277 : { state : UInt<2>} - T_1277 is invalid - T_1277.state <= UInt<1>("h0") - reg new_coh_state : { state : UInt<2>}, clk with : - reset => (reset, T_1277) - reg req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { tag : UInt<20>, coh : { state : UInt<2>}}, way_en : UInt<4>}, clk with : - reset => (UInt<1>("h0"), req) - node req_idx = bits(req.addr, 11, 6) - node T_1586 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1586) - node T_1588 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1590 = or(T_1588, T_1589) - node T_1591 = bits(io.req_bits.cmd, 3, 3) - node T_1592 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1593 = or(T_1591, T_1592) - node T_1594 = or(T_1590, T_1593) - node T_1595 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1596 = or(T_1594, T_1595) - node T_1597 = eq(io.req_bits.cmd, UInt<5>("h6")) - node T_1598 = or(T_1596, T_1597) - node T_1599 = eq(req.cmd, UInt<5>("h1")) - node T_1600 = eq(req.cmd, UInt<5>("h7")) - node T_1601 = or(T_1599, T_1600) - node T_1602 = bits(req.cmd, 3, 3) - node T_1603 = eq(req.cmd, UInt<5>("h4")) - node T_1604 = or(T_1602, T_1603) - node T_1605 = or(T_1601, T_1604) - node T_1606 = eq(req.cmd, UInt<5>("h3")) - node T_1607 = or(T_1605, T_1606) - node T_1608 = eq(req.cmd, UInt<5>("h6")) - node T_1609 = or(T_1607, T_1608) - node T_1611 = eq(T_1609, UInt<1>("h0")) - node cmd_requires_second_acquire = and(T_1598, T_1611) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] <= UInt<1>("h1") - states_before_refill[1] <= UInt<2>("h2") - states_before_refill[2] <= UInt<2>("h3") - node T_1619 = eq(states_before_refill[0], state) - node T_1620 = eq(states_before_refill[1], state) - node T_1621 = eq(states_before_refill[2], state) - node T_1623 = or(UInt<1>("h0"), T_1619) - node T_1624 = or(T_1623, T_1620) - node T_1625 = or(T_1624, T_1621) - wire T_1627 : UInt<3>[2] - T_1627[0] <= UInt<3>("h4") - T_1627[1] <= UInt<3>("h5") - node T_1631 = eq(T_1627[0], state) - node T_1632 = eq(T_1627[1], state) - node T_1634 = or(UInt<1>("h0"), T_1631) - node T_1635 = or(T_1634, T_1632) - node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h0")) - node T_1638 = and(T_1635, T_1637) - node T_1639 = or(T_1625, T_1638) - node sec_rdy = and(idx_match, T_1639) - wire T_1644 : UInt<3>[1] - T_1644[0] <= UInt<3>("h5") - node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) - node T_1649 = or(UInt<1>("h0"), T_1647) - wire T_1651 : UInt<1>[2] - T_1651[0] <= UInt<1>("h0") - T_1651[1] <= UInt<1>("h1") - node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) - node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) - node T_1658 = or(UInt<1>("h0"), T_1655) - node T_1659 = or(T_1658, T_1656) - node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) - node gnt_multi_data = and(UInt<1>("h1"), T_1660) - node T_1662 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - when T_1662 : - node T_1666 = eq(refill_cnt, UInt<2>("h3")) - node T_1668 = and(UInt<1>("h0"), T_1666) - node T_1671 = add(refill_cnt, UInt<1>("h1")) - node T_1672 = tail(T_1671, 1) - node T_1673 = mux(T_1668, UInt<1>("h0"), T_1672) - refill_cnt <= T_1673 - skip - node refill_count_done = and(T_1662, T_1666) - node T_1676 = eq(gnt_multi_data, UInt<1>("h0")) - node T_1677 = or(T_1676, refill_count_done) - node refill_done = and(io.mem_grant.valid, T_1677) - inst rpq of Queue_98 - rpq.io is invalid - rpq.clk <= clk - rpq.reset <= reset - node T_1734 = and(io.req_pri_val, io.req_pri_rdy) - node T_1735 = and(io.req_sec_val, sec_rdy) - node T_1736 = or(T_1734, T_1735) - node T_1737 = eq(io.req_bits.cmd, UInt<5>("h2")) - node T_1738 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1739 = or(T_1737, T_1738) - node T_1741 = eq(T_1739, UInt<1>("h0")) - node T_1742 = and(T_1736, T_1741) - rpq.io.enq.valid <= T_1742 - rpq.io.enq.bits <- io.req_bits - node T_1743 = eq(state, UInt<4>("h8")) - node T_1744 = and(io.replay.ready, T_1743) - node T_1745 = eq(state, UInt<1>("h0")) - node T_1746 = or(T_1744, T_1745) - rpq.io.deq.ready <= T_1746 - node T_1747 = eq(req.cmd, UInt<5>("h1")) - node T_1748 = eq(req.cmd, UInt<5>("h7")) - node T_1749 = or(T_1747, T_1748) - node T_1750 = bits(req.cmd, 3, 3) - node T_1751 = eq(req.cmd, UInt<5>("h4")) - node T_1752 = or(T_1750, T_1751) - node T_1753 = or(T_1749, T_1752) - node T_1754 = mux(T_1753, UInt<2>("h3"), UInt<2>("h2")) - node T_1755 = eq(UInt<2>("h2"), io.mem_grant.bits.g_type) - node T_1756 = mux(T_1755, UInt<2>("h3"), UInt<1>("h0")) - node T_1757 = eq(UInt<1>("h1"), io.mem_grant.bits.g_type) - node T_1758 = mux(T_1757, T_1754, T_1756) - node T_1759 = eq(UInt<1>("h0"), io.mem_grant.bits.g_type) - node T_1760 = mux(T_1759, UInt<1>("h1"), T_1758) - node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h0"), T_1760) - wire coh_on_grant : { state : UInt<2>} - coh_on_grant is invalid - coh_on_grant.state <= T_1761 - node T_1812 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1813 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = bits(io.req_bits.cmd, 3, 3) - node T_1816 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1817 = or(T_1815, T_1816) - node T_1818 = or(T_1814, T_1817) - node T_1819 = mux(T_1818, UInt<2>("h3"), io.req_bits.old_meta.coh.state) - wire coh_on_hit : { state : UInt<2>} - coh_on_hit is invalid - coh_on_hit.state <= T_1819 - node T_1870 = eq(state, UInt<4>("h8")) - node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h0")) - node T_1873 = and(T_1870, T_1872) - when T_1873 : - state <= UInt<1>("h0") - skip - node T_1874 = eq(state, UInt<3>("h7")) - when T_1874 : - state <= UInt<4>("h8") - skip - node T_1875 = eq(state, UInt<3>("h6")) - node T_1876 = and(T_1875, io.meta_write.ready) - when T_1876 : - state <= UInt<3>("h7") - skip - node T_1877 = eq(state, UInt<3>("h5")) - when T_1877 : - when io.mem_grant.valid : - new_coh_state <- coh_on_grant - skip - when refill_done : - state <= UInt<3>("h6") - skip - skip - node T_1878 = and(io.mem_req.ready, io.mem_req.valid) - when T_1878 : - state <= UInt<3>("h5") - skip - node T_1879 = eq(state, UInt<2>("h3")) - node T_1880 = and(T_1879, io.meta_write.ready) - when T_1880 : - state <= UInt<3>("h4") - skip - node T_1881 = eq(state, UInt<2>("h2")) - node T_1882 = and(T_1881, io.mem_grant.valid) - when T_1882 : - state <= UInt<2>("h3") - skip - node T_1883 = and(io.wb_req.ready, io.wb_req.valid) - when T_1883 : - node T_1886 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1887 = mux(T_1886, UInt<2>("h2"), UInt<2>("h3")) - state <= T_1887 - skip - node T_1888 = and(io.req_sec_val, io.req_sec_rdy) - when T_1888 : - when cmd_requires_second_acquire : - req.cmd <= io.req_bits.cmd - skip - skip - node T_1889 = and(io.req_pri_val, io.req_pri_rdy) - when T_1889 : - req <- io.req_bits - when io.req_bits.tag_match : - node T_1890 = eq(io.req_bits.cmd, UInt<5>("h1")) - node T_1891 = eq(io.req_bits.cmd, UInt<5>("h7")) - node T_1892 = or(T_1890, T_1891) - node T_1893 = bits(io.req_bits.cmd, 3, 3) - node T_1894 = eq(io.req_bits.cmd, UInt<5>("h4")) - node T_1895 = or(T_1893, T_1894) - node T_1896 = or(T_1892, T_1895) - node T_1897 = eq(io.req_bits.cmd, UInt<5>("h3")) - node T_1898 = or(T_1896, T_1897) - node T_1899 = eq(io.req_bits.cmd, UInt<5>("h6")) - node T_1900 = or(T_1898, T_1899) - wire T_1902 : UInt<2>[2] - T_1902[0] <= UInt<2>("h2") - T_1902[1] <= UInt<2>("h3") - node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) - node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) - node T_1909 = or(UInt<1>("h0"), T_1906) - node T_1910 = or(T_1909, T_1907) - wire T_1912 : UInt<2>[3] - T_1912[0] <= UInt<1>("h1") - T_1912[1] <= UInt<2>("h2") - T_1912[2] <= UInt<2>("h3") - node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) - node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) - node T_1921 = or(UInt<1>("h0"), T_1917) - node T_1922 = or(T_1921, T_1918) - node T_1923 = or(T_1922, T_1919) - node T_1924 = mux(T_1900, T_1910, T_1923) - when T_1924 : - state <= UInt<3>("h6") - new_coh_state <- coh_on_hit - skip - node T_1926 = eq(T_1924, UInt<1>("h0")) - when T_1926 : - state <= UInt<3>("h4") - skip - skip - node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h0")) - when T_1928 : - wire T_1930 : UInt<2>[1] - T_1930[0] <= UInt<2>("h3") - node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) - node T_1935 = or(UInt<1>("h0"), T_1933) - node T_1936 = mux(T_1935, UInt<1>("h1"), UInt<2>("h3")) - state <= T_1936 - skip - skip - node T_1937 = neq(state, UInt<1>("h0")) - node T_1938 = and(T_1937, idx_match) - io.idx_match <= T_1938 - io.refill.way_en <= req.way_en - node T_1939 = cat(req_idx, refill_cnt) - node T_1940 = shl(T_1939, 4) - io.refill.addr <= T_1940 - node T_1941 = shr(req.addr, 12) - io.tag <= T_1941 - node T_1942 = eq(state, UInt<1>("h0")) - io.req_pri_rdy <= T_1942 - node T_1943 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1943 - reg meta_hazard : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_1947 = neq(meta_hazard, UInt<1>("h0")) - when T_1947 : - node T_1949 = add(meta_hazard, UInt<1>("h1")) - node T_1950 = tail(T_1949, 1) - meta_hazard <= T_1950 - skip - node T_1951 = and(io.meta_write.ready, io.meta_write.valid) - when T_1951 : - meta_hazard <= UInt<1>("h1") - skip - node T_1954 = eq(idx_match, UInt<1>("h0")) - node T_1955 = eq(states_before_refill[0], state) - node T_1956 = eq(states_before_refill[1], state) - node T_1957 = eq(states_before_refill[2], state) - node T_1959 = or(UInt<1>("h0"), T_1955) - node T_1960 = or(T_1959, T_1956) - node T_1961 = or(T_1960, T_1957) - node T_1963 = eq(T_1961, UInt<1>("h0")) - node T_1965 = eq(meta_hazard, UInt<1>("h0")) - node T_1966 = and(T_1963, T_1965) - node T_1967 = or(T_1954, T_1966) - io.probe_rdy <= T_1967 - node T_1968 = eq(state, UInt<3>("h6")) - node T_1969 = eq(state, UInt<2>("h3")) - node T_1970 = or(T_1968, T_1969) - io.meta_write.valid <= T_1970 - io.meta_write.bits.idx <= req_idx - node T_1971 = eq(state, UInt<2>("h3")) - wire T_1973 : UInt<2>[2] - T_1973[0] <= UInt<2>("h2") - T_1973[1] <= UInt<2>("h3") - node T_1977 = eq(T_1973[0], req.old_meta.coh.state) - node T_1978 = eq(T_1973[1], req.old_meta.coh.state) - node T_1980 = or(UInt<1>("h0"), T_1977) - node T_1981 = or(T_1980, T_1978) - node T_1982 = mux(T_1981, UInt<1>("h1"), req.old_meta.coh.state) - node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h3")) - node T_1984 = mux(T_1983, UInt<2>("h2"), req.old_meta.coh.state) - node T_1985 = eq(UInt<5>("h13"), UInt<5>("h10")) - node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) - node T_1987 = eq(UInt<5>("h11"), UInt<5>("h10")) - node T_1988 = mux(T_1987, T_1982, T_1986) - node T_1989 = eq(UInt<5>("h10"), UInt<5>("h10")) - node T_1990 = mux(T_1989, UInt<1>("h0"), T_1988) - wire T_2016 : { state : UInt<2>} - T_2016 is invalid - T_2016.state <= T_1990 - node T_2041 = mux(T_1971, T_2016, new_coh_state) - io.meta_write.bits.data.coh <- T_2041 - io.meta_write.bits.data.tag <= io.tag - io.meta_write.bits.way_en <= req.way_en - node T_2066 = eq(state, UInt<1>("h1")) - io.wb_req.valid <= T_2066 - node T_2068 = cat(req.old_meta.tag, req_idx) - wire T_2073 : UInt<2>[1] - T_2073[0] <= UInt<2>("h3") - node T_2076 = eq(T_2073[0], req.old_meta.coh.state) - node T_2078 = or(UInt<1>("h0"), T_2076) - node T_2079 = mux(T_2078, UInt<1>("h0"), UInt<2>("h3")) - node T_2080 = mux(T_2078, UInt<1>("h1"), UInt<3>("h4")) - node T_2081 = mux(T_2078, UInt<2>("h2"), UInt<3>("h5")) - node T_2082 = eq(UInt<5>("h13"), UInt<5>("h10")) - node T_2083 = mux(T_2082, T_2081, UInt<3>("h5")) - node T_2084 = eq(UInt<5>("h11"), UInt<5>("h10")) - node T_2085 = mux(T_2084, T_2080, T_2083) - node T_2086 = eq(UInt<5>("h10"), UInt<5>("h10")) - node T_2087 = mux(T_2086, T_2079, T_2085) - wire T_2118 : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2118 is invalid - T_2118.r_type <= T_2087 - T_2118.client_xact_id <= UInt<1>("h1") - T_2118.addr_block <= T_2068 - T_2118.addr_beat <= UInt<1>("h0") - T_2118.data <= UInt<1>("h0") - T_2118.voluntary <= UInt<1>("h1") - io.wb_req.bits <- T_2118 - io.wb_req.bits.way_en <= req.way_en - node T_2148 = eq(state, UInt<3>("h4")) - io.mem_req.valid <= T_2148 - node T_2149 = cat(io.tag, req_idx) - node T_2152 = eq(req.cmd, UInt<5>("h1")) - node T_2153 = eq(req.cmd, UInt<5>("h7")) - node T_2154 = or(T_2152, T_2153) - node T_2155 = bits(req.cmd, 3, 3) - node T_2156 = eq(req.cmd, UInt<5>("h4")) - node T_2157 = or(T_2155, T_2156) - node T_2158 = or(T_2154, T_2157) - node T_2159 = eq(req.cmd, UInt<5>("h3")) - node T_2160 = or(T_2158, T_2159) - node T_2161 = eq(req.cmd, UInt<5>("h6")) - node T_2162 = or(T_2160, T_2161) - node T_2163 = mux(T_2162, UInt<1>("h1"), UInt<1>("h0")) - node T_2165 = cat(req.cmd, UInt<1>("h1")) - wire T_2199 : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2199 is invalid - T_2199.is_builtin_type <= UInt<1>("h0") - T_2199.a_type <= T_2163 - T_2199.client_xact_id <= UInt<1>("h1") - T_2199.addr_block <= T_2149 - T_2199.addr_beat <= UInt<1>("h0") - T_2199.data <= UInt<1>("h0") - T_2199.union <= T_2165 - io.mem_req.bits <- T_2199 - node T_2230 = eq(state, UInt<4>("h8")) - io.meta_read.valid <= T_2230 - io.meta_read.bits.idx <= req_idx - io.meta_read.bits.tag <= io.tag - node T_2231 = eq(state, UInt<4>("h8")) - node T_2232 = and(T_2231, rpq.io.deq.valid) - io.replay.valid <= T_2232 - io.replay.bits <- rpq.io.deq.bits - io.replay.bits.phys <= UInt<1>("h1") - node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2235 = cat(req_idx, T_2234) - node T_2236 = cat(io.tag, T_2235) - io.replay.bits.addr <= T_2236 - node T_2238 = eq(io.meta_read.ready, UInt<1>("h0")) - when T_2238 : - rpq.io.deq.ready <= UInt<1>("h0") - io.replay.bits.cmd <= UInt<5>("h5") - skip - module Arbiter_101 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} - io is invalid - wire T_54 : UInt<1> - T_54 is invalid - io.out.valid <= io.in[T_54].valid - io.out.bits <= io.in[T_54].bits - io.chosen <= T_54 - io.in[T_54].ready <= UInt<1>("h0") - node T_73 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_74 = mux(UInt<1>("h0"), T_73, UInt<1>("h1")) - node T_75 = and(T_74, io.out.ready) - io.in[0].ready <= T_75 - node T_77 = mux(UInt<1>("h0"), UInt<1>("h0"), UInt<1>("h0")) - T_54 <= T_77 - module Arbiter_102 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>} - io is invalid - wire T_1062 : UInt<1> - T_1062 is invalid - io.out.valid <= io.in[T_1062].valid - io.out.bits <- io.in[T_1062].bits - io.chosen <= T_1062 - io.in[T_1062].ready <= UInt<1>("h0") - node T_1417 = eq(UInt<1>("h0"), UInt<1>("h0")) - node T_1418 = mux(UInt<1>("h0"), T_1417, UInt<1>("h1")) - node T_1419 = and(T_1418, io.out.ready) - io.in[0].ready <= T_1419 - node T_1421 = mux(UInt<1>("h0"), UInt<1>("h0"), UInt<1>("h0")) - T_1062 <= T_1421 - module IOMSHR : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : { valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}} - io is invalid - reg req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), req) - node req_cmd_sc = eq(req.cmd, UInt<5>("h7")) - reg grant_word : UInt<64>, clk with : - reset => (UInt<1>("h0"), grant_word) - node T_861 = bits(req.typ, 1, 0) - node T_862 = bits(req.typ, 1, 0) - node T_863 = asSInt(req.typ) - node T_865 = geq(T_863, asSInt(UInt<1>("h0"))) - node beat_offset = bits(req.addr, 3, 3) - node T_868 = bits(req.addr, 0, 0) - node T_870 = mux(T_868, UInt<1>("h1"), UInt<1>("h0")) - node T_872 = geq(T_861, UInt<1>("h1")) - node T_875 = mux(T_872, UInt<1>("h1"), UInt<1>("h0")) - node T_876 = or(T_870, T_875) - node T_877 = bits(req.addr, 0, 0) - node T_879 = mux(T_877, UInt<1>("h0"), UInt<1>("h1")) - node T_880 = cat(T_876, T_879) - node T_881 = bits(req.addr, 1, 1) - node T_883 = mux(T_881, T_880, UInt<1>("h0")) - node T_885 = geq(T_861, UInt<2>("h2")) - node T_888 = mux(T_885, UInt<2>("h3"), UInt<1>("h0")) - node T_889 = or(T_883, T_888) - node T_890 = bits(req.addr, 1, 1) - node T_892 = mux(T_890, UInt<1>("h0"), T_880) - node T_893 = cat(T_889, T_892) - node T_894 = bits(req.addr, 2, 2) - node T_896 = mux(T_894, T_893, UInt<1>("h0")) - node T_898 = geq(T_861, UInt<2>("h3")) - node T_901 = mux(T_898, UInt<4>("hf"), UInt<1>("h0")) - node T_902 = or(T_896, T_901) - node T_903 = bits(req.addr, 2, 2) - node T_905 = mux(T_903, UInt<1>("h0"), T_893) - node T_906 = cat(T_902, T_905) - node T_908 = cat(beat_offset, UInt<3>("h0")) - node beat_mask = dshl(T_906, T_908) - node T_911 = eq(T_861, UInt<1>("h0")) - node T_912 = bits(req.data, 7, 0) - node T_913 = cat(T_912, T_912) - node T_914 = cat(T_913, T_913) - node T_915 = cat(T_914, T_914) - node T_917 = eq(T_861, UInt<1>("h1")) - node T_918 = bits(req.data, 15, 0) - node T_919 = cat(T_918, T_918) - node T_920 = cat(T_919, T_919) - node T_922 = eq(T_861, UInt<2>("h2")) - node T_923 = bits(req.data, 31, 0) - node T_924 = cat(T_923, T_923) - node T_925 = mux(T_922, T_924, req.data) - node T_926 = mux(T_917, T_920, T_925) - node T_927 = mux(T_911, T_915, T_926) - node beat_data = cat(T_927, T_927) - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - node T_935 = eq(state, UInt<1>("h0")) - io.req.ready <= T_935 - node addr_block = bits(req.addr, 31, 6) - node addr_beat = bits(req.addr, 5, 4) - node addr_byte = bits(req.addr, 3, 0) - node T_947 = cat(addr_byte, req.typ) - node T_948 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_949 = cat(T_947, T_948) - node T_951 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_952 = cat(req.typ, T_951) - node T_954 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_956 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_958 = cat(addr_byte, req.typ) - node T_959 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_960 = cat(T_958, T_959) - node T_962 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_964 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_965 = eq(UInt<3>("h6"), UInt<3>("h0")) - node T_966 = mux(T_965, T_964, UInt<1>("h0")) - node T_967 = eq(UInt<3>("h5"), UInt<3>("h0")) - node T_968 = mux(T_967, T_962, T_966) - node T_969 = eq(UInt<3>("h4"), UInt<3>("h0")) - node T_970 = mux(T_969, T_960, T_968) - node T_971 = eq(UInt<3>("h3"), UInt<3>("h0")) - node T_972 = mux(T_971, T_956, T_970) - node T_973 = eq(UInt<3>("h2"), UInt<3>("h0")) - node T_974 = mux(T_973, T_954, T_972) - node T_975 = eq(UInt<3>("h1"), UInt<3>("h0")) - node T_976 = mux(T_975, T_952, T_974) - node T_977 = eq(UInt<3>("h0"), UInt<3>("h0")) - node T_978 = mux(T_977, T_949, T_976) - wire get_acquire : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - get_acquire is invalid - get_acquire.is_builtin_type <= UInt<1>("h1") - get_acquire.a_type <= UInt<3>("h0") - get_acquire.client_xact_id <= UInt<2>("h2") - get_acquire.addr_block <= addr_block - get_acquire.addr_beat <= addr_beat - get_acquire.data <= UInt<1>("h0") - get_acquire.union <= T_978 - node T_1049 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1050 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_1051 = cat(T_1049, T_1050) - node T_1053 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_1054 = cat(UInt<3>("h7"), T_1053) - node T_1056 = cat(beat_mask, UInt<1>("h0")) - node T_1058 = cat(beat_mask, UInt<1>("h0")) - node T_1060 = cat(UInt<1>("h0"), UInt<3>("h7")) - node T_1061 = cat(UInt<1>("h0"), UInt<1>("h0")) - node T_1062 = cat(T_1060, T_1061) - node T_1064 = cat(UInt<5>("h0"), UInt<1>("h0")) - node T_1066 = cat(UInt<5>("h1"), UInt<1>("h0")) - node T_1067 = eq(UInt<3>("h6"), UInt<3>("h2")) - node T_1068 = mux(T_1067, T_1066, UInt<1>("h0")) - node T_1069 = eq(UInt<3>("h5"), UInt<3>("h2")) - node T_1070 = mux(T_1069, T_1064, T_1068) - node T_1071 = eq(UInt<3>("h4"), UInt<3>("h2")) - node T_1072 = mux(T_1071, T_1062, T_1070) - node T_1073 = eq(UInt<3>("h3"), UInt<3>("h2")) - node T_1074 = mux(T_1073, T_1058, T_1072) - node T_1075 = eq(UInt<3>("h2"), UInt<3>("h2")) - node T_1076 = mux(T_1075, T_1056, T_1074) - node T_1077 = eq(UInt<3>("h1"), UInt<3>("h2")) - node T_1078 = mux(T_1077, T_1054, T_1076) - node T_1079 = eq(UInt<3>("h0"), UInt<3>("h2")) - node T_1080 = mux(T_1079, T_1051, T_1078) - wire put_acquire : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - put_acquire is invalid - put_acquire.is_builtin_type <= UInt<1>("h1") - put_acquire.a_type <= UInt<3>("h2") - put_acquire.client_xact_id <= UInt<2>("h2") - put_acquire.addr_block <= addr_block - put_acquire.addr_beat <= addr_beat - put_acquire.data <= beat_data - put_acquire.union <= T_1080 - node T_1143 = eq(state, UInt<1>("h1")) - io.acquire.valid <= T_1143 - node T_1144 = eq(req.cmd, UInt<5>("h0")) - node T_1145 = eq(req.cmd, UInt<5>("h6")) - node T_1146 = or(T_1144, T_1145) - node T_1147 = eq(req.cmd, UInt<5>("h7")) - node T_1148 = or(T_1146, T_1147) - node T_1149 = bits(req.cmd, 3, 3) - node T_1150 = eq(req.cmd, UInt<5>("h4")) - node T_1151 = or(T_1149, T_1150) - node T_1152 = or(T_1148, T_1151) - node T_1153 = mux(T_1152, get_acquire, put_acquire) - io.acquire.bits <- T_1153 - node T_1184 = eq(state, UInt<2>("h3")) - io.resp.valid <= T_1184 - io.resp.bits <- req - node T_1185 = eq(req.cmd, UInt<5>("h0")) - node T_1186 = eq(req.cmd, UInt<5>("h6")) - node T_1187 = or(T_1185, T_1186) - node T_1188 = eq(req.cmd, UInt<5>("h7")) - node T_1189 = or(T_1187, T_1188) - node T_1190 = bits(req.cmd, 3, 3) - node T_1191 = eq(req.cmd, UInt<5>("h4")) - node T_1192 = or(T_1190, T_1191) - node T_1193 = or(T_1189, T_1192) - io.resp.bits.has_data <= T_1193 - node T_1194 = bits(req.addr, 2, 2) - node T_1195 = bits(grant_word, 63, 32) - node T_1196 = bits(grant_word, 31, 0) - node T_1197 = mux(T_1194, T_1195, T_1196) - node T_1199 = and(UInt<1>("h0"), req_cmd_sc) - node T_1201 = mux(T_1199, UInt<1>("h0"), T_1197) - node T_1203 = eq(T_862, UInt<2>("h2")) - node T_1204 = or(T_1203, T_1199) - node T_1205 = bits(T_1201, 31, 31) - node T_1206 = and(T_865, T_1205) - node T_1208 = sub(UInt<32>("h0"), T_1206) - node T_1209 = tail(T_1208, 1) - node T_1210 = bits(grant_word, 63, 32) - node T_1211 = mux(T_1204, T_1209, T_1210) - node T_1212 = cat(T_1211, T_1201) - node T_1213 = bits(req.addr, 1, 1) - node T_1214 = bits(T_1212, 31, 16) - node T_1215 = bits(T_1212, 15, 0) - node T_1216 = mux(T_1213, T_1214, T_1215) - node T_1218 = and(UInt<1>("h0"), req_cmd_sc) - node T_1220 = mux(T_1218, UInt<1>("h0"), T_1216) - node T_1222 = eq(T_862, UInt<1>("h1")) - node T_1223 = or(T_1222, T_1218) - node T_1224 = bits(T_1220, 15, 15) - node T_1225 = and(T_865, T_1224) - node T_1227 = sub(UInt<48>("h0"), T_1225) - node T_1228 = tail(T_1227, 1) - node T_1229 = bits(T_1212, 63, 16) - node T_1230 = mux(T_1223, T_1228, T_1229) - node T_1231 = cat(T_1230, T_1220) - node T_1232 = bits(req.addr, 0, 0) - node T_1233 = bits(T_1231, 15, 8) - node T_1234 = bits(T_1231, 7, 0) - node T_1235 = mux(T_1232, T_1233, T_1234) - node T_1237 = and(UInt<1>("h1"), req_cmd_sc) - node T_1239 = mux(T_1237, UInt<1>("h0"), T_1235) - node T_1241 = eq(T_862, UInt<1>("h0")) - node T_1242 = or(T_1241, T_1237) - node T_1243 = bits(T_1239, 7, 7) - node T_1244 = and(T_865, T_1243) - node T_1246 = sub(UInt<56>("h0"), T_1244) - node T_1247 = tail(T_1246, 1) - node T_1248 = bits(T_1231, 63, 8) - node T_1249 = mux(T_1242, T_1247, T_1248) - node T_1250 = cat(T_1249, T_1239) - node T_1251 = or(T_1250, req_cmd_sc) - io.resp.bits.data <= T_1251 - io.resp.bits.store_data <= req.data - io.resp.bits.nack <= UInt<1>("h0") - io.resp.bits.replay <= io.resp.valid - node T_1253 = and(io.req.ready, io.req.valid) - when T_1253 : - req <- io.req.bits - state <= UInt<1>("h1") - skip - node T_1254 = and(io.acquire.ready, io.acquire.valid) - when T_1254 : - state <= UInt<2>("h2") - skip - node T_1255 = eq(state, UInt<2>("h2")) - node T_1256 = and(T_1255, io.grant.valid) - when T_1256 : - node T_1257 = eq(req.cmd, UInt<5>("h0")) - node T_1258 = eq(req.cmd, UInt<5>("h6")) - node T_1259 = or(T_1257, T_1258) - node T_1260 = eq(req.cmd, UInt<5>("h7")) - node T_1261 = or(T_1259, T_1260) - node T_1262 = bits(req.cmd, 3, 3) - node T_1263 = eq(req.cmd, UInt<5>("h4")) - node T_1264 = or(T_1262, T_1263) - node T_1265 = or(T_1261, T_1264) - when T_1265 : - node T_1266 = bits(req.addr, 3, 3) - node T_1268 = cat(T_1266, UInt<6>("h0")) - node T_1269 = dshr(io.grant.bits.data, T_1268) - node T_1270 = bits(T_1269, 63, 0) - grant_word <= T_1270 - state <= UInt<2>("h3") - skip - node T_1272 = eq(T_1265, UInt<1>("h0")) - when T_1272 : - state <= UInt<1>("h0") - skip - skip - node T_1273 = and(io.resp.ready, io.resp.valid) - when T_1273 : - state <= UInt<1>("h0") - skip - module MSHRFile : - input clk : Clock - input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : { tag : UInt<20>, coh : { state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : { way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : { valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>} - io is invalid - node cacheable = lt(io.req.bits.addr, UInt<31>("h40000000")) - reg sdq_val : UInt<17>, clk with : - reset => (reset, UInt<17>("h0")) - node T_1807 = bits(sdq_val, 16, 0) - node T_1808 = not(T_1807) - node T_1809 = bits(T_1808, 0, 0) - node T_1810 = bits(T_1808, 1, 1) - node T_1811 = bits(T_1808, 2, 2) - node T_1812 = bits(T_1808, 3, 3) - node T_1813 = bits(T_1808, 4, 4) - node T_1814 = bits(T_1808, 5, 5) - node T_1815 = bits(T_1808, 6, 6) - node T_1816 = bits(T_1808, 7, 7) - node T_1817 = bits(T_1808, 8, 8) - node T_1818 = bits(T_1808, 9, 9) - node T_1819 = bits(T_1808, 10, 10) - node T_1820 = bits(T_1808, 11, 11) - node T_1821 = bits(T_1808, 12, 12) - node T_1822 = bits(T_1808, 13, 13) - node T_1823 = bits(T_1808, 14, 14) - node T_1824 = bits(T_1808, 15, 15) - node T_1825 = bits(T_1808, 16, 16) - wire T_1827 : UInt<1>[17] - T_1827[0] <= T_1809 - T_1827[1] <= T_1810 - T_1827[2] <= T_1811 - T_1827[3] <= T_1812 - T_1827[4] <= T_1813 - T_1827[5] <= T_1814 - T_1827[6] <= T_1815 - T_1827[7] <= T_1816 - T_1827[8] <= T_1817 - T_1827[9] <= T_1818 - T_1827[10] <= T_1819 - T_1827[11] <= T_1820 - T_1827[12] <= T_1821 - T_1827[13] <= T_1822 - T_1827[14] <= T_1823 - T_1827[15] <= T_1824 - T_1827[16] <= T_1825 - node T_1863 = mux(T_1827[15], UInt<4>("hf"), UInt<5>("h10")) - node T_1864 = mux(T_1827[14], UInt<4>("he"), T_1863) - node T_1865 = mux(T_1827[13], UInt<4>("hd"), T_1864) - node T_1866 = mux(T_1827[12], UInt<4>("hc"), T_1865) - node T_1867 = mux(T_1827[11], UInt<4>("hb"), T_1866) - node T_1868 = mux(T_1827[10], UInt<4>("ha"), T_1867) - node T_1869 = mux(T_1827[9], UInt<4>("h9"), T_1868) - node T_1870 = mux(T_1827[8], UInt<4>("h8"), T_1869) - node T_1871 = mux(T_1827[7], UInt<3>("h7"), T_1870) - node T_1872 = mux(T_1827[6], UInt<3>("h6"), T_1871) - node T_1873 = mux(T_1827[5], UInt<3>("h5"), T_1872) - node T_1874 = mux(T_1827[4], UInt<3>("h4"), T_1873) - node T_1875 = mux(T_1827[3], UInt<2>("h3"), T_1874) - node T_1876 = mux(T_1827[2], UInt<2>("h2"), T_1875) - node T_1877 = mux(T_1827[1], UInt<1>("h1"), T_1876) - node sdq_alloc_id = mux(T_1827[0], UInt<1>("h0"), T_1877) - node T_1879 = not(sdq_val) - node T_1881 = eq(T_1879, UInt<1>("h0")) - node sdq_rdy = eq(T_1881, UInt<1>("h0")) - node T_1884 = and(io.req.valid, io.req.ready) - node T_1885 = and(T_1884, cacheable) - node T_1886 = eq(io.req.bits.cmd, UInt<5>("h1")) - node T_1887 = eq(io.req.bits.cmd, UInt<5>("h7")) - node T_1888 = or(T_1886, T_1887) - node T_1889 = bits(io.req.bits.cmd, 3, 3) - node T_1890 = eq(io.req.bits.cmd, UInt<5>("h4")) - node T_1891 = or(T_1889, T_1890) - node T_1892 = or(T_1888, T_1891) - node sdq_enq = and(T_1885, T_1892) - mem sdq : - data-type => UInt<64> - depth => 17 - write-latency => 1 - read-latency => 0 - reader => T_2888 - writer => T_1896 - sdq.T_2888.addr is invalid - sdq.T_2888.clk <= clk - sdq.T_2888.en <= UInt<1>("h0") - sdq.T_1896.addr is invalid - sdq.T_1896.clk <= clk - sdq.T_1896.en <= UInt<1>("h0") - sdq.T_1896.data is invalid - sdq.T_1896.mask <= UInt<1>("h0") - when sdq_enq : - sdq.T_1896.addr <= sdq_alloc_id - sdq.T_1896.en <= UInt<1>("h1") - sdq.T_1896.data <= io.req.bits.data - sdq.T_1896.mask <= UInt<1>("h1") - skip - wire idxMatch : UInt<1>[2] - idxMatch is invalid - wire tagList : UInt<20>[2] - tagList is invalid - node T_1922 = mux(idxMatch[0], tagList[0], UInt<1>("h0")) - node T_1924 = mux(idxMatch[1], tagList[1], UInt<1>("h0")) - node T_1926 = or(T_1922, T_1924) - wire T_1927 : UInt<20> - T_1927 is invalid - T_1927 <= T_1926 - node T_1928 = shr(io.req.bits.addr, 12) - node tag_match = eq(T_1927, T_1928) - wire wbTagList : UInt[2] - wbTagList is invalid - wire refillMux : { way_en : UInt<4>, addr : UInt<12>}[2] - refillMux is invalid - inst meta_read_arb of Arbiter_93 - meta_read_arb.io is invalid - meta_read_arb.clk <= clk - meta_read_arb.reset <= reset - inst meta_write_arb of Arbiter_94 - meta_write_arb.io is invalid - meta_write_arb.clk <= clk - meta_write_arb.reset <= reset - inst mem_req_arb of LockingArbiter - mem_req_arb.io is invalid - mem_req_arb.clk <= clk - mem_req_arb.reset <= reset - inst wb_req_arb of Arbiter_95 - wb_req_arb.io is invalid - wb_req_arb.clk <= clk - wb_req_arb.reset <= reset - inst replay_arb of Arbiter_96 - replay_arb.io is invalid - replay_arb.clk <= clk - replay_arb.reset <= reset - inst alloc_arb of Arbiter_97 - alloc_arb.io is invalid - alloc_arb.clk <= clk - alloc_arb.reset <= reset - io.fence_rdy <= UInt<1>("h1") - io.probe_rdy <= UInt<1>("h1") - inst T_2714 of MSHR - T_2714.io is invalid - T_2714.clk <= clk - T_2714.reset <= reset - idxMatch[0] <= T_2714.io.idx_match - tagList[0] <= T_2714.io.tag - node T_2715 = shr(T_2714.io.wb_req.bits.addr_block, 6) - wbTagList[0] <= T_2715 - alloc_arb.io.in[0].valid <= T_2714.io.req_pri_rdy - T_2714.io.req_pri_val <= alloc_arb.io.in[0].ready - node T_2716 = and(io.req.valid, sdq_rdy) - node T_2717 = and(T_2716, tag_match) - T_2714.io.req_sec_val <= T_2717 - T_2714.io.req_bits <- io.req.bits - T_2714.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[0] <- T_2714.io.meta_read - meta_write_arb.io.in[0] <- T_2714.io.meta_write - mem_req_arb.io.in[0] <- T_2714.io.mem_req - wb_req_arb.io.in[0] <- T_2714.io.wb_req - replay_arb.io.in[0] <- T_2714.io.replay - node T_2719 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h0")) - node T_2720 = and(io.mem_grant.valid, T_2719) - T_2714.io.mem_grant.valid <= T_2720 - T_2714.io.mem_grant.bits <- io.mem_grant.bits - refillMux[0] <- T_2714.io.refill - node T_2721 = or(UInt<1>("h0"), T_2714.io.req_pri_rdy) - node T_2722 = or(UInt<1>("h0"), T_2714.io.req_sec_rdy) - node T_2723 = or(UInt<1>("h0"), T_2714.io.idx_match) - node T_2725 = eq(T_2714.io.req_pri_rdy, UInt<1>("h0")) - when T_2725 : - io.fence_rdy <= UInt<1>("h0") - skip - node T_2728 = eq(T_2714.io.probe_rdy, UInt<1>("h0")) - when T_2728 : - io.probe_rdy <= UInt<1>("h0") - skip - inst T_2730 of MSHR_99 - T_2730.io is invalid - T_2730.clk <= clk - T_2730.reset <= reset - idxMatch[1] <= T_2730.io.idx_match - tagList[1] <= T_2730.io.tag - node T_2731 = shr(T_2730.io.wb_req.bits.addr_block, 6) - wbTagList[1] <= T_2731 - alloc_arb.io.in[1].valid <= T_2730.io.req_pri_rdy - T_2730.io.req_pri_val <= alloc_arb.io.in[1].ready - node T_2732 = and(io.req.valid, sdq_rdy) - node T_2733 = and(T_2732, tag_match) - T_2730.io.req_sec_val <= T_2733 - T_2730.io.req_bits <- io.req.bits - T_2730.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[1] <- T_2730.io.meta_read - meta_write_arb.io.in[1] <- T_2730.io.meta_write - mem_req_arb.io.in[1] <- T_2730.io.mem_req - wb_req_arb.io.in[1] <- T_2730.io.wb_req - replay_arb.io.in[1] <- T_2730.io.replay - node T_2735 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h1")) - node T_2736 = and(io.mem_grant.valid, T_2735) - T_2730.io.mem_grant.valid <= T_2736 - T_2730.io.mem_grant.bits <- io.mem_grant.bits - refillMux[1] <- T_2730.io.refill - node pri_rdy = or(T_2721, T_2730.io.req_pri_rdy) - node sec_rdy = or(T_2722, T_2730.io.req_sec_rdy) - node idx_match = or(T_2723, T_2730.io.idx_match) - node T_2741 = eq(T_2730.io.req_pri_rdy, UInt<1>("h0")) - when T_2741 : - io.fence_rdy <= UInt<1>("h0") - skip - node T_2744 = eq(T_2730.io.probe_rdy, UInt<1>("h0")) - when T_2744 : - io.probe_rdy <= UInt<1>("h0") - skip - node T_2746 = and(io.req.valid, sdq_rdy) - node T_2747 = and(T_2746, cacheable) - node T_2749 = eq(idx_match, UInt<1>("h0")) - node T_2750 = and(T_2747, T_2749) - alloc_arb.io.out.ready <= T_2750 - io.meta_read <- meta_read_arb.io.out - io.meta_write <- meta_write_arb.io.out - io.mem_req <- mem_req_arb.io.out - io.wb_req <- wb_req_arb.io.out - inst mmio_alloc_arb of Arbiter_101 - mmio_alloc_arb.io is invalid - mmio_alloc_arb.clk <= clk - mmio_alloc_arb.reset <= reset - inst resp_arb of Arbiter_102 - resp_arb.io is invalid - resp_arb.clk <= clk - resp_arb.reset <= reset - inst T_2812 of IOMSHR - T_2812.io is invalid - T_2812.clk <= clk - T_2812.reset <= reset - mmio_alloc_arb.io.in[0].valid <= T_2812.io.req.ready - T_2812.io.req.valid <= mmio_alloc_arb.io.in[0].ready - T_2812.io.req.bits <- io.req.bits - node mmio_rdy = or(UInt<1>("h0"), T_2812.io.req.ready) - mem_req_arb.io.in[2] <- T_2812.io.acquire - T_2812.io.grant.bits <- io.mem_grant.bits - node T_2815 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h2")) - node T_2816 = and(io.mem_grant.valid, T_2815) - T_2812.io.grant.valid <= T_2816 - resp_arb.io.in[0] <- T_2812.io.resp - node T_2818 = eq(T_2812.io.req.ready, UInt<1>("h0")) - when T_2818 : - io.fence_rdy <= UInt<1>("h0") - skip - node T_2821 = eq(cacheable, UInt<1>("h0")) - node T_2822 = and(io.req.valid, T_2821) - mmio_alloc_arb.io.out.ready <= T_2822 - io.resp <- resp_arb.io.out - node T_2824 = eq(cacheable, UInt<1>("h0")) - node T_2825 = and(tag_match, sec_rdy) - node T_2826 = mux(idx_match, T_2825, pri_rdy) - node T_2827 = and(T_2826, sdq_rdy) - node T_2828 = mux(T_2824, mmio_rdy, T_2827) - io.req.ready <= T_2828 - io.secondary_miss <= idx_match - io.refill <- refillMux[io.mem_grant.bits.client_xact_id] - node T_2878 = and(io.replay.ready, io.replay.valid) - node T_2879 = eq(io.replay.bits.cmd, UInt<5>("h1")) - node T_2880 = eq(io.replay.bits.cmd, UInt<5>("h7")) - node T_2881 = or(T_2879, T_2880) - node T_2882 = bits(io.replay.bits.cmd, 3, 3) - node T_2883 = eq(io.replay.bits.cmd, UInt<5>("h4")) - node T_2884 = or(T_2882, T_2883) - node T_2885 = or(T_2881, T_2884) - node free_sdq = and(T_2878, T_2885) - reg T_2887 : UInt<5>, clk with : - reset => (UInt<1>("h0"), T_2887) - when free_sdq : - T_2887 <= replay_arb.io.out.bits.sdq_id - skip - sdq.T_2888.addr <= T_2887 - sdq.T_2888.en <= UInt<1>("h1") - io.replay.bits.data <= sdq.T_2888.data - io.replay <- replay_arb.io.out - node T_2889 = or(io.replay.valid, sdq_enq) - when T_2889 : - node T_2891 = dshl(UInt<1>("h1"), replay_arb.io.out.bits.sdq_id) - node T_2893 = sub(UInt<17>("h0"), free_sdq) - node T_2894 = tail(T_2893, 1) - node T_2895 = and(T_2891, T_2894) - node T_2896 = not(T_2895) - node T_2897 = and(sdq_val, T_2896) - node T_2898 = bits(sdq_val, 16, 0) - node T_2899 = not(T_2898) - node T_2900 = bits(T_2899, 0, 0) - node T_2901 = bits(T_2899, 1, 1) - node T_2902 = bits(T_2899, 2, 2) - node T_2903 = bits(T_2899, 3, 3) - node T_2904 = bits(T_2899, 4, 4) - node T_2905 = bits(T_2899, 5, 5) - node T_2906 = bits(T_2899, 6, 6) - node T_2907 = bits(T_2899, 7, 7) - node T_2908 = bits(T_2899, 8, 8) - node T_2909 = bits(T_2899, 9, 9) - node T_2910 = bits(T_2899, 10, 10) - node T_2911 = bits(T_2899, 11, 11) - node T_2912 = bits(T_2899, 12, 12) - node T_2913 = bits(T_2899, 13, 13) - node T_2914 = bits(T_2899, 14, 14) - node T_2915 = bits(T_2899, 15, 15) - node T_2916 = bits(T_2899, 16, 16) - wire T_2935 : UInt<17>[17] - T_2935[0] <= UInt<17>("h1") - T_2935[1] <= UInt<17>("h2") - T_2935[2] <= UInt<17>("h4") - T_2935[3] <= UInt<17>("h8") - T_2935[4] <= UInt<17>("h10") - T_2935[5] <= UInt<17>("h20") - T_2935[6] <= UInt<17>("h40") - T_2935[7] <= UInt<17>("h80") - T_2935[8] <= UInt<17>("h100") - T_2935[9] <= UInt<17>("h200") - T_2935[10] <= UInt<17>("h400") - T_2935[11] <= UInt<17>("h800") - T_2935[12] <= UInt<17>("h1000") - T_2935[13] <= UInt<17>("h2000") - T_2935[14] <= UInt<17>("h4000") - T_2935[15] <= UInt<17>("h8000") - T_2935[16] <= UInt<17>("h10000") - node T_2956 = mux(T_2916, T_2935[16], UInt<17>("h0")) - node T_2957 = mux(T_2915, T_2935[15], T_2956) - node T_2958 = mux(T_2914, T_2935[14], T_2957) - node T_2959 = mux(T_2913, T_2935[13], T_2958) - node T_2960 = mux(T_2912, T_2935[12], T_2959) - node T_2961 = mux(T_2911, T_2935[11], T_2960) - node T_2962 = mux(T_2910, T_2935[10], T_2961) - node T_2963 = mux(T_2909, T_2935[9], T_2962) - node T_2964 = mux(T_2908, T_2935[8], T_2963) - node T_2965 = mux(T_2907, T_2935[7], T_2964) - node T_2966 = mux(T_2906, T_2935[6], T_2965) - node T_2967 = mux(T_2905, T_2935[5], T_2966) - node T_2968 = mux(T_2904, T_2935[4], T_2967) - node T_2969 = mux(T_2903, T_2935[3], T_2968) - node T_2970 = mux(T_2902, T_2935[2], T_2969) - node T_2971 = mux(T_2901, T_2935[1], T_2970) - node T_2972 = mux(T_2900, T_2935[0], T_2971) - node T_2974 = sub(UInt<17>("h0"), sdq_enq) - node T_2975 = tail(T_2974, 1) - node T_2976 = and(T_2972, T_2975) - node T_2977 = or(T_2897, T_2976) - sdq_val <= T_2977 - skip - module MetadataArray : - input clk : Clock - input reset : UInt<1> - output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, resp : { tag : UInt<20>, coh : { state : UInt<2>}}[4]} - io is invalid - wire T_30 : { state : UInt<2>} - T_30 is invalid - T_30.state <= UInt<1>("h0") - wire rstVal : { tag : UInt<20>, coh : { state : UInt<2>}} - rstVal is invalid - rstVal.tag <= UInt<1>("h0") - rstVal.coh <- T_30 - reg rst_cnt : UInt<7>, clk with : - reset => (reset, UInt<7>("h0")) - node rst = lt(rst_cnt, UInt<7>("h40")) - node waddr = mux(rst, rst_cnt, io.write.bits.idx) - node T_1633 = mux(rst, rstVal, io.write.bits.data) - node wdata = cat(T_1633.tag, T_1633.coh.state) - node T_1708 = asSInt(io.write.bits.way_en) - node T_1709 = mux(rst, asSInt(UInt<1>("h1")), T_1708) - node T_1710 = bits(T_1709, 0, 0) - node T_1711 = bits(T_1709, 1, 1) - node T_1712 = bits(T_1709, 2, 2) - node T_1713 = bits(T_1709, 3, 3) - wire wmask : UInt<1>[4] - wmask[0] <= T_1710 - wmask[1] <= T_1711 - wmask[2] <= T_1712 - wmask[3] <= T_1713 - when rst : - node T_1722 = add(rst_cnt, UInt<1>("h1")) - node T_1723 = tail(T_1722, 1) - rst_cnt <= T_1723 - skip - mem tag_arr : - data-type => UInt<22>[4] - depth => 64 - write-latency => 1 - read-latency => 1 - reader => T_1761 - writer => T_1751 - tag_arr.T_1761.addr is invalid - tag_arr.T_1761.clk <= clk - tag_arr.T_1761.en <= UInt<1>("h0") - tag_arr.T_1751.addr is invalid - tag_arr.T_1751.clk <= clk - tag_arr.T_1751.en <= UInt<1>("h0") - tag_arr.T_1751.data is invalid - tag_arr.T_1751.mask[0] <= UInt<1>("h0") - tag_arr.T_1751.mask[1] <= UInt<1>("h0") - tag_arr.T_1751.mask[2] <= UInt<1>("h0") - tag_arr.T_1751.mask[3] <= UInt<1>("h0") - node T_1741 = or(rst, io.write.valid) - when T_1741 : - wire T_1743 : UInt<22>[4] - T_1743[0] <= wdata - T_1743[1] <= wdata - T_1743[2] <= wdata - T_1743[3] <= wdata - tag_arr.T_1751.addr <= waddr - tag_arr.T_1751.en <= UInt<1>("h1") - when wmask[0] : - tag_arr.T_1751.data[0] <= T_1743[0] - tag_arr.T_1751.mask[0] <= UInt<1>("h1") - skip - when wmask[1] : - tag_arr.T_1751.data[1] <= T_1743[1] - tag_arr.T_1751.mask[1] <= UInt<1>("h1") - skip - when wmask[2] : - tag_arr.T_1751.data[2] <= T_1743[2] - tag_arr.T_1751.mask[2] <= UInt<1>("h1") - skip - when wmask[3] : - tag_arr.T_1751.data[3] <= T_1743[3] - tag_arr.T_1751.mask[3] <= UInt<1>("h1") - skip - skip - wire T_1758 : UInt - T_1758 is invalid - when io.read.valid : - T_1758 <= io.read.bits.idx - skip - tag_arr.T_1761.addr <= T_1758 - tag_arr.T_1761.en <= UInt<1>("h1") - node T_1767 = cat(tag_arr.T_1761.data[3], tag_arr.T_1761.data[2]) - node T_1768 = cat(tag_arr.T_1761.data[1], tag_arr.T_1761.data[0]) - node tags = cat(T_1767, T_1768) - wire T_2428 : { tag : UInt<20>, coh : { state : UInt<2>}}[4] - T_2428 is invalid - node T_2794 = bits(tags, 1, 0) - T_2428[0].coh.state <= T_2794 - node T_2795 = bits(tags, 21, 2) - T_2428[0].tag <= T_2795 - node T_2796 = bits(tags, 23, 22) - T_2428[1].coh.state <= T_2796 - node T_2797 = bits(tags, 43, 24) - T_2428[1].tag <= T_2797 - node T_2798 = bits(tags, 45, 44) - T_2428[2].coh.state <= T_2798 - node T_2799 = bits(tags, 65, 46) - T_2428[2].tag <= T_2799 - node T_2800 = bits(tags, 67, 66) - T_2428[3].coh.state <= T_2800 - node T_2801 = bits(tags, 87, 68) - T_2428[3].tag <= T_2801 - io.resp <= T_2428 - node T_2803 = eq(rst, UInt<1>("h0")) - node T_2805 = eq(io.write.valid, UInt<1>("h0")) - node T_2806 = and(T_2803, T_2805) - io.read.ready <= T_2806 - node T_2808 = eq(rst, UInt<1>("h0")) - io.write.ready <= T_2808 - module Arbiter_105 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>}}, chosen : UInt<3>} - io is invalid - wire T_128 : UInt<3> - T_128 is invalid - io.out.valid <= io.in[T_128].valid - io.out.bits <- io.in[T_128].bits - io.chosen <= T_128 - io.in[T_128].ready <= UInt<1>("h0") - node T_153 = or(UInt<1>("h0"), io.in[0].valid) - node T_155 = eq(T_153, UInt<1>("h0")) - node T_157 = or(UInt<1>("h0"), io.in[0].valid) - node T_158 = or(T_157, io.in[1].valid) - node T_160 = eq(T_158, UInt<1>("h0")) - node T_162 = or(UInt<1>("h0"), io.in[0].valid) - node T_163 = or(T_162, io.in[1].valid) - node T_164 = or(T_163, io.in[2].valid) - node T_166 = eq(T_164, UInt<1>("h0")) - node T_168 = or(UInt<1>("h0"), io.in[0].valid) - node T_169 = or(T_168, io.in[1].valid) - node T_170 = or(T_169, io.in[2].valid) - node T_171 = or(T_170, io.in[3].valid) - node T_173 = eq(T_171, UInt<1>("h0")) - node T_175 = eq(UInt<3>("h4"), UInt<1>("h0")) - node T_176 = mux(UInt<1>("h0"), T_175, UInt<1>("h1")) - node T_177 = and(T_176, io.out.ready) - io.in[0].ready <= T_177 - node T_179 = eq(UInt<3>("h4"), UInt<1>("h1")) - node T_180 = mux(UInt<1>("h0"), T_179, T_155) - node T_181 = and(T_180, io.out.ready) - io.in[1].ready <= T_181 - node T_183 = eq(UInt<3>("h4"), UInt<2>("h2")) - node T_184 = mux(UInt<1>("h0"), T_183, T_160) - node T_185 = and(T_184, io.out.ready) - io.in[2].ready <= T_185 - node T_187 = eq(UInt<3>("h4"), UInt<2>("h3")) - node T_188 = mux(UInt<1>("h0"), T_187, T_166) - node T_189 = and(T_188, io.out.ready) - io.in[3].ready <= T_189 - node T_191 = eq(UInt<3>("h4"), UInt<3>("h4")) - node T_192 = mux(UInt<1>("h0"), T_191, T_173) - node T_193 = and(T_192, io.out.ready) - io.in[4].ready <= T_193 - node T_196 = mux(io.in[3].valid, UInt<2>("h3"), UInt<3>("h4")) - node T_198 = mux(io.in[2].valid, UInt<2>("h2"), T_196) - node T_200 = mux(io.in[1].valid, UInt<1>("h1"), T_198) - node T_202 = mux(io.in[0].valid, UInt<1>("h0"), T_200) - node T_203 = mux(UInt<1>("h0"), UInt<3>("h4"), T_202) - T_128 <= T_203 - module DataArray : - input clk : Clock - input reset : UInt<1> - output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]} - io is invalid - node waddr = shr(io.write.bits.addr, 4) - node raddr = shr(io.read.bits.addr, 4) - node T_572 = bits(io.write.bits.way_en, 1, 0) - node T_573 = bits(io.read.bits.way_en, 1, 0) - wire T_582 : UInt<128>[2] - T_582 is invalid - reg T_586 : UInt<12>, clk with : - reset => (UInt<1>("h0"), T_586) - when io.read.valid : - T_586 <= io.read.bits.addr - skip - mem T_599 : - data-type => UInt<64>[2] - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_632 - writer => T_621 - T_599.T_632.addr is invalid - T_599.T_632.clk <= clk - T_599.T_632.en <= UInt<1>("h0") - T_599.T_621.addr is invalid - T_599.T_621.clk <= clk - T_599.T_621.en <= UInt<1>("h0") - T_599.T_621.data is invalid - T_599.T_621.mask[0] <= UInt<1>("h0") - T_599.T_621.mask[1] <= UInt<1>("h0") - node T_601 = neq(T_572, UInt<1>("h0")) - node T_602 = and(T_601, io.write.valid) - node T_603 = bits(io.write.bits.wmask, 0, 0) - node T_604 = and(T_602, T_603) - when T_604 : - node T_605 = bits(io.write.bits.data, 63, 0) - node T_606 = bits(io.write.bits.data, 63, 0) - wire T_608 : UInt<64>[2] - T_608[0] <= T_605 - T_608[1] <= T_606 - node T_612 = bits(T_572, 0, 0) - node T_613 = bits(T_572, 1, 1) - wire T_615 : UInt<1>[2] - T_615[0] <= T_612 - T_615[1] <= T_613 - T_599.T_621.addr <= waddr - T_599.T_621.en <= UInt<1>("h1") - when T_615[0] : - T_599.T_621.data[0] <= T_608[0] - T_599.T_621.mask[0] <= UInt<1>("h1") - skip - when T_615[1] : - T_599.T_621.data[1] <= T_608[1] - T_599.T_621.mask[1] <= UInt<1>("h1") - skip - skip - node T_626 = neq(T_573, UInt<1>("h0")) - node T_627 = and(T_626, io.read.valid) - wire T_629 : UInt - T_629 is invalid - when T_627 : - T_629 <= raddr - skip - T_599.T_632.addr <= T_629 - T_599.T_632.en <= UInt<1>("h1") - node T_636 = cat(T_599.T_632.data[1], T_599.T_632.data[0]) - T_582[0] <= T_636 - mem T_649 : - data-type => UInt<64>[2] - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_682 - writer => T_671 - T_649.T_682.addr is invalid - T_649.T_682.clk <= clk - T_649.T_682.en <= UInt<1>("h0") - T_649.T_671.addr is invalid - T_649.T_671.clk <= clk - T_649.T_671.en <= UInt<1>("h0") - T_649.T_671.data is invalid - T_649.T_671.mask[0] <= UInt<1>("h0") - T_649.T_671.mask[1] <= UInt<1>("h0") - node T_651 = neq(T_572, UInt<1>("h0")) - node T_652 = and(T_651, io.write.valid) - node T_653 = bits(io.write.bits.wmask, 1, 1) - node T_654 = and(T_652, T_653) - when T_654 : - node T_655 = bits(io.write.bits.data, 127, 64) - node T_656 = bits(io.write.bits.data, 127, 64) - wire T_658 : UInt<64>[2] - T_658[0] <= T_655 - T_658[1] <= T_656 - node T_662 = bits(T_572, 0, 0) - node T_663 = bits(T_572, 1, 1) - wire T_665 : UInt<1>[2] - T_665[0] <= T_662 - T_665[1] <= T_663 - T_649.T_671.addr <= waddr - T_649.T_671.en <= UInt<1>("h1") - when T_665[0] : - T_649.T_671.data[0] <= T_658[0] - T_649.T_671.mask[0] <= UInt<1>("h1") - skip - when T_665[1] : - T_649.T_671.data[1] <= T_658[1] - T_649.T_671.mask[1] <= UInt<1>("h1") - skip - skip - node T_676 = neq(T_573, UInt<1>("h0")) - node T_677 = and(T_676, io.read.valid) - wire T_679 : UInt - T_679 is invalid - when T_677 : - T_679 <= raddr - skip - T_649.T_682.addr <= T_679 - T_649.T_682.en <= UInt<1>("h1") - node T_686 = cat(T_649.T_682.data[1], T_649.T_682.data[0]) - T_582[1] <= T_686 - node T_687 = bits(T_582[0], 63, 0) - node T_688 = bits(T_582[1], 63, 0) - wire T_690 : UInt<64>[2] - T_690[0] <= T_687 - T_690[1] <= T_688 - node T_694 = bits(T_586, 3, 3) - wire T_697 : UInt<64>[2] - T_697[0] <= T_690[T_694] - T_697[1] <= T_690[1] - node T_701 = cat(T_697[1], T_697[0]) - io.resp[0] <= T_701 - node T_702 = bits(T_582[0], 127, 64) - node T_703 = bits(T_582[1], 127, 64) - wire T_705 : UInt<64>[2] - T_705[0] <= T_702 - T_705[1] <= T_703 - node T_709 = bits(T_586, 3, 3) - wire T_712 : UInt<64>[2] - T_712[0] <= T_705[T_709] - T_712[1] <= T_705[1] - node T_716 = cat(T_712[1], T_712[0]) - io.resp[1] <= T_716 - node T_717 = bits(io.write.bits.way_en, 3, 2) - node T_718 = bits(io.read.bits.way_en, 3, 2) - wire T_727 : UInt<128>[2] - T_727 is invalid - reg T_731 : UInt<12>, clk with : - reset => (UInt<1>("h0"), T_731) - when io.read.valid : - T_731 <= io.read.bits.addr - skip - mem T_744 : - data-type => UInt<64>[2] - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_777 - writer => T_766 - T_744.T_777.addr is invalid - T_744.T_777.clk <= clk - T_744.T_777.en <= UInt<1>("h0") - T_744.T_766.addr is invalid - T_744.T_766.clk <= clk - T_744.T_766.en <= UInt<1>("h0") - T_744.T_766.data is invalid - T_744.T_766.mask[0] <= UInt<1>("h0") - T_744.T_766.mask[1] <= UInt<1>("h0") - node T_746 = neq(T_717, UInt<1>("h0")) - node T_747 = and(T_746, io.write.valid) - node T_748 = bits(io.write.bits.wmask, 0, 0) - node T_749 = and(T_747, T_748) - when T_749 : - node T_750 = bits(io.write.bits.data, 63, 0) - node T_751 = bits(io.write.bits.data, 63, 0) - wire T_753 : UInt<64>[2] - T_753[0] <= T_750 - T_753[1] <= T_751 - node T_757 = bits(T_717, 0, 0) - node T_758 = bits(T_717, 1, 1) - wire T_760 : UInt<1>[2] - T_760[0] <= T_757 - T_760[1] <= T_758 - T_744.T_766.addr <= waddr - T_744.T_766.en <= UInt<1>("h1") - when T_760[0] : - T_744.T_766.data[0] <= T_753[0] - T_744.T_766.mask[0] <= UInt<1>("h1") - skip - when T_760[1] : - T_744.T_766.data[1] <= T_753[1] - T_744.T_766.mask[1] <= UInt<1>("h1") - skip - skip - node T_771 = neq(T_718, UInt<1>("h0")) - node T_772 = and(T_771, io.read.valid) - wire T_774 : UInt - T_774 is invalid - when T_772 : - T_774 <= raddr - skip - T_744.T_777.addr <= T_774 - T_744.T_777.en <= UInt<1>("h1") - node T_781 = cat(T_744.T_777.data[1], T_744.T_777.data[0]) - T_727[0] <= T_781 - mem T_794 : - data-type => UInt<64>[2] - depth => 256 - write-latency => 1 - read-latency => 1 - reader => T_827 - writer => T_816 - T_794.T_827.addr is invalid - T_794.T_827.clk <= clk - T_794.T_827.en <= UInt<1>("h0") - T_794.T_816.addr is invalid - T_794.T_816.clk <= clk - T_794.T_816.en <= UInt<1>("h0") - T_794.T_816.data is invalid - T_794.T_816.mask[0] <= UInt<1>("h0") - T_794.T_816.mask[1] <= UInt<1>("h0") - node T_796 = neq(T_717, UInt<1>("h0")) - node T_797 = and(T_796, io.write.valid) - node T_798 = bits(io.write.bits.wmask, 1, 1) - node T_799 = and(T_797, T_798) - when T_799 : - node T_800 = bits(io.write.bits.data, 127, 64) - node T_801 = bits(io.write.bits.data, 127, 64) - wire T_803 : UInt<64>[2] - T_803[0] <= T_800 - T_803[1] <= T_801 - node T_807 = bits(T_717, 0, 0) - node T_808 = bits(T_717, 1, 1) - wire T_810 : UInt<1>[2] - T_810[0] <= T_807 - T_810[1] <= T_808 - T_794.T_816.addr <= waddr - T_794.T_816.en <= UInt<1>("h1") - when T_810[0] : - T_794.T_816.data[0] <= T_803[0] - T_794.T_816.mask[0] <= UInt<1>("h1") - skip - when T_810[1] : - T_794.T_816.data[1] <= T_803[1] - T_794.T_816.mask[1] <= UInt<1>("h1") - skip - skip - node T_821 = neq(T_718, UInt<1>("h0")) - node T_822 = and(T_821, io.read.valid) - wire T_824 : UInt - T_824 is invalid - when T_822 : - T_824 <= raddr - skip - T_794.T_827.addr <= T_824 - T_794.T_827.en <= UInt<1>("h1") - node T_831 = cat(T_794.T_827.data[1], T_794.T_827.data[0]) - T_727[1] <= T_831 - node T_832 = bits(T_727[0], 63, 0) - node T_833 = bits(T_727[1], 63, 0) - wire T_835 : UInt<64>[2] - T_835[0] <= T_832 - T_835[1] <= T_833 - node T_839 = bits(T_731, 3, 3) - wire T_842 : UInt<64>[2] - T_842[0] <= T_835[T_839] - T_842[1] <= T_835[1] - node T_846 = cat(T_842[1], T_842[0]) - io.resp[2] <= T_846 - node T_847 = bits(T_727[0], 127, 64) - node T_848 = bits(T_727[1], 127, 64) - wire T_850 : UInt<64>[2] - T_850[0] <= T_847 - T_850[1] <= T_848 - node T_854 = bits(T_731, 3, 3) - wire T_857 : UInt<64>[2] - T_857[0] <= T_850[T_854] - T_857[1] <= T_850[1] - node T_861 = cat(T_857[1], T_857[0]) - io.resp[3] <= T_861 - io.read.ready <= UInt<1>("h1") - io.write.ready <= UInt<1>("h1") - module Arbiter_107 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>} - io is invalid - wire T_1524 : UInt<2> - T_1524 is invalid - io.out.valid <= io.in[T_1524].valid - io.out.bits <- io.in[T_1524].bits - io.chosen <= T_1524 - io.in[T_1524].ready <= UInt<1>("h0") - node T_1831 = or(UInt<1>("h0"), io.in[0].valid) - node T_1833 = eq(T_1831, UInt<1>("h0")) - node T_1835 = or(UInt<1>("h0"), io.in[0].valid) - node T_1836 = or(T_1835, io.in[1].valid) - node T_1838 = eq(T_1836, UInt<1>("h0")) - node T_1840 = or(UInt<1>("h0"), io.in[0].valid) - node T_1841 = or(T_1840, io.in[1].valid) - node T_1842 = or(T_1841, io.in[2].valid) - node T_1844 = eq(T_1842, UInt<1>("h0")) - node T_1846 = eq(UInt<2>("h3"), UInt<1>("h0")) - node T_1847 = mux(UInt<1>("h0"), T_1846, UInt<1>("h1")) - node T_1848 = and(T_1847, io.out.ready) - io.in[0].ready <= T_1848 - node T_1850 = eq(UInt<2>("h3"), UInt<1>("h1")) - node T_1851 = mux(UInt<1>("h0"), T_1850, T_1833) - node T_1852 = and(T_1851, io.out.ready) - io.in[1].ready <= T_1852 - node T_1854 = eq(UInt<2>("h3"), UInt<2>("h2")) - node T_1855 = mux(UInt<1>("h0"), T_1854, T_1838) - node T_1856 = and(T_1855, io.out.ready) - io.in[2].ready <= T_1856 - node T_1858 = eq(UInt<2>("h3"), UInt<2>("h3")) - node T_1859 = mux(UInt<1>("h0"), T_1858, T_1844) - node T_1860 = and(T_1859, io.out.ready) - io.in[3].ready <= T_1860 - node T_1863 = mux(io.in[2].valid, UInt<2>("h2"), UInt<2>("h3")) - node T_1865 = mux(io.in[1].valid, UInt<1>("h1"), T_1863) - node T_1867 = mux(io.in[0].valid, UInt<1>("h0"), T_1865) - node T_1868 = mux(UInt<1>("h0"), UInt<2>("h3"), T_1867) - T_1524 <= T_1868 - module Arbiter_108 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>} - io is invalid - wire T_1164 : UInt<1> - T_1164 is invalid - io.out.valid <= io.in[T_1164].valid - io.out.bits <- io.in[T_1164].bits - io.chosen <= T_1164 - io.in[T_1164].ready <= UInt<1>("h0") - node T_1483 = or(UInt<1>("h0"), io.in[0].valid) - node T_1485 = eq(T_1483, UInt<1>("h0")) - node T_1487 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_1488 = mux(UInt<1>("h0"), T_1487, UInt<1>("h1")) - node T_1489 = and(T_1488, io.out.ready) - io.in[0].ready <= T_1489 - node T_1491 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_1492 = mux(UInt<1>("h0"), T_1491, T_1485) - node T_1493 = and(T_1492, io.out.ready) - io.in[1].ready <= T_1493 - node T_1496 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_1497 = mux(UInt<1>("h0"), UInt<1>("h1"), T_1496) - T_1164 <= T_1497 - module AMOALU : - input clk : Clock - input reset : UInt<1> - output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} - io is invalid - node T_10 = bits(io.typ, 1, 0) - node T_12 = eq(T_10, UInt<2>("h2")) - node T_13 = bits(io.rhs, 31, 0) - node T_14 = cat(T_13, T_13) - node rhs = mux(T_12, T_14, io.rhs) - node T_16 = eq(io.cmd, UInt<5>("hc")) - node T_17 = eq(io.cmd, UInt<5>("hd")) - node sgned = or(T_16, T_17) - node T_19 = eq(io.cmd, UInt<5>("hd")) - node T_20 = eq(io.cmd, UInt<5>("hf")) - node max = or(T_19, T_20) - node T_22 = eq(io.cmd, UInt<5>("hc")) - node T_23 = eq(io.cmd, UInt<5>("he")) - node min = or(T_22, T_23) - node T_25 = eq(io.typ, UInt<3>("h2")) - node T_26 = eq(io.typ, UInt<3>("h6")) - node T_27 = or(T_25, T_26) - node T_28 = eq(io.typ, UInt<3>("h0")) - node T_29 = or(T_27, T_28) - node T_30 = eq(io.typ, UInt<3>("h4")) - node word = or(T_29, T_30) - node T_33 = not(UInt<64>("h0")) - node T_34 = bits(io.addr, 2, 2) - node T_35 = shl(T_34, 31) - node mask = xor(T_33, T_35) - node T_37 = and(io.lhs, mask) - node T_38 = and(rhs, mask) - node T_39 = add(T_37, T_38) - node adder_out = tail(T_39, 1) - node T_41 = bits(io.addr, 2, 2) - node T_43 = eq(T_41, UInt<1>("h0")) - node T_44 = and(word, T_43) - node T_45 = bits(io.lhs, 31, 31) - node T_46 = bits(io.lhs, 63, 63) - node cmp_lhs = mux(T_44, T_45, T_46) - node T_48 = bits(io.addr, 2, 2) - node T_50 = eq(T_48, UInt<1>("h0")) - node T_51 = and(word, T_50) - node T_52 = bits(rhs, 31, 31) - node T_53 = bits(rhs, 63, 63) - node cmp_rhs = mux(T_51, T_52, T_53) - node T_55 = bits(io.lhs, 31, 0) - node T_56 = bits(rhs, 31, 0) - node lt_lo = lt(T_55, T_56) - node T_58 = bits(io.lhs, 63, 32) - node T_59 = bits(rhs, 63, 32) - node lt_hi = lt(T_58, T_59) - node T_61 = bits(io.lhs, 63, 32) - node T_62 = bits(rhs, 63, 32) - node eq_hi = eq(T_61, T_62) - node T_64 = bits(io.addr, 2, 2) - node T_65 = mux(T_64, lt_hi, lt_lo) - node T_66 = and(eq_hi, lt_lo) - node T_67 = or(lt_hi, T_66) - node lt = mux(word, T_65, T_67) - node T_69 = eq(cmp_lhs, cmp_rhs) - node T_70 = mux(sgned, cmp_lhs, cmp_rhs) - node less = mux(T_69, lt, T_70) - node T_72 = eq(io.cmd, UInt<5>("h8")) - node T_73 = eq(io.cmd, UInt<5>("hb")) - node T_74 = and(io.lhs, rhs) - node T_75 = eq(io.cmd, UInt<5>("ha")) - node T_76 = or(io.lhs, rhs) - node T_77 = eq(io.cmd, UInt<5>("h9")) - node T_78 = xor(io.lhs, rhs) - node T_79 = mux(less, min, max) - node T_81 = eq(T_10, UInt<1>("h0")) - node T_82 = bits(io.rhs, 7, 0) - node T_83 = cat(T_82, T_82) - node T_84 = cat(T_83, T_83) - node T_85 = cat(T_84, T_84) - node T_87 = eq(T_10, UInt<1>("h1")) - node T_88 = bits(io.rhs, 15, 0) - node T_89 = cat(T_88, T_88) - node T_90 = cat(T_89, T_89) - node T_92 = eq(T_10, UInt<2>("h2")) - node T_93 = bits(io.rhs, 31, 0) - node T_94 = cat(T_93, T_93) - node T_95 = mux(T_92, T_94, io.rhs) - node T_96 = mux(T_87, T_90, T_95) - node T_97 = mux(T_81, T_85, T_96) - node T_98 = mux(T_79, io.lhs, T_97) - node T_99 = mux(T_77, T_78, T_98) - node T_100 = mux(T_75, T_76, T_99) - node T_101 = mux(T_73, T_74, T_100) - node out = mux(T_72, adder_out, T_101) - node T_104 = bits(io.addr, 0, 0) - node T_106 = mux(T_104, UInt<1>("h1"), UInt<1>("h0")) - node T_108 = geq(T_10, UInt<1>("h1")) - node T_111 = mux(T_108, UInt<1>("h1"), UInt<1>("h0")) - node T_112 = or(T_106, T_111) - node T_113 = bits(io.addr, 0, 0) - node T_115 = mux(T_113, UInt<1>("h0"), UInt<1>("h1")) - node T_116 = cat(T_112, T_115) - node T_117 = bits(io.addr, 1, 1) - node T_119 = mux(T_117, T_116, UInt<1>("h0")) - node T_121 = geq(T_10, UInt<2>("h2")) - node T_124 = mux(T_121, UInt<2>("h3"), UInt<1>("h0")) - node T_125 = or(T_119, T_124) - node T_126 = bits(io.addr, 1, 1) - node T_128 = mux(T_126, UInt<1>("h0"), T_116) - node T_129 = cat(T_125, T_128) - node T_130 = bits(io.addr, 2, 2) - node T_132 = mux(T_130, T_129, UInt<1>("h0")) - node T_134 = geq(T_10, UInt<2>("h3")) - node T_137 = mux(T_134, UInt<4>("hf"), UInt<1>("h0")) - node T_138 = or(T_132, T_137) - node T_139 = bits(io.addr, 2, 2) - node T_141 = mux(T_139, UInt<1>("h0"), T_129) - node T_142 = cat(T_138, T_141) - node T_143 = bits(T_142, 0, 0) - node T_144 = bits(T_142, 1, 1) - node T_145 = bits(T_142, 2, 2) - node T_146 = bits(T_142, 3, 3) - node T_147 = bits(T_142, 4, 4) - node T_148 = bits(T_142, 5, 5) - node T_149 = bits(T_142, 6, 6) - node T_150 = bits(T_142, 7, 7) - wire T_152 : UInt<1>[8] - T_152[0] <= T_143 - T_152[1] <= T_144 - T_152[2] <= T_145 - T_152[3] <= T_146 - T_152[4] <= T_147 - T_152[5] <= T_148 - T_152[6] <= T_149 - T_152[7] <= T_150 - node T_163 = sub(UInt<8>("h0"), T_152[0]) - node T_164 = tail(T_163, 1) - node T_166 = sub(UInt<8>("h0"), T_152[1]) - node T_167 = tail(T_166, 1) - node T_169 = sub(UInt<8>("h0"), T_152[2]) - node T_170 = tail(T_169, 1) - node T_172 = sub(UInt<8>("h0"), T_152[3]) - node T_173 = tail(T_172, 1) - node T_175 = sub(UInt<8>("h0"), T_152[4]) - node T_176 = tail(T_175, 1) - node T_178 = sub(UInt<8>("h0"), T_152[5]) - node T_179 = tail(T_178, 1) - node T_181 = sub(UInt<8>("h0"), T_152[6]) - node T_182 = tail(T_181, 1) - node T_184 = sub(UInt<8>("h0"), T_152[7]) - node T_185 = tail(T_184, 1) - wire T_187 : UInt<8>[8] - T_187[0] <= T_164 - T_187[1] <= T_167 - T_187[2] <= T_170 - T_187[3] <= T_173 - T_187[4] <= T_176 - T_187[5] <= T_179 - T_187[6] <= T_182 - T_187[7] <= T_185 - node T_197 = cat(T_187[7], T_187[6]) - node T_198 = cat(T_187[5], T_187[4]) - node T_199 = cat(T_197, T_198) - node T_200 = cat(T_187[3], T_187[2]) - node T_201 = cat(T_187[1], T_187[0]) - node T_202 = cat(T_200, T_201) - node wmask = cat(T_199, T_202) - node T_204 = and(wmask, out) - node T_205 = not(wmask) - node T_206 = and(T_205, io.lhs) - node T_207 = or(T_204, T_206) - io.out <= T_207 - module LockingArbiter_109 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, chosen : UInt<1>} - io is invalid - reg T_700 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_702 : UInt, clk with : - reset => (reset, UInt<1>("h1")) - wire T_704 : UInt<1> - T_704 is invalid - io.out.valid <= io.in[T_704].valid - io.out.bits <- io.in[T_704].bits - io.chosen <= T_704 - io.in[T_704].ready <= UInt<1>("h0") - node T_897 = or(UInt<1>("h0"), io.in[0].valid) - node T_899 = eq(T_897, UInt<1>("h0")) - node T_901 = eq(T_702, UInt<1>("h0")) - node T_902 = mux(T_700, T_901, UInt<1>("h1")) - node T_903 = and(T_902, io.out.ready) - io.in[0].ready <= T_903 - node T_905 = eq(T_702, UInt<1>("h1")) - node T_906 = mux(T_700, T_905, T_899) - node T_907 = and(T_906, io.out.ready) - io.in[1].ready <= T_907 - reg T_909 : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - node T_911 = add(T_909, UInt<1>("h1")) - node T_912 = tail(T_911, 1) - node T_913 = and(io.out.ready, io.out.valid) - when T_913 : - wire T_916 : UInt<2>[3] - T_916[0] <= UInt<1>("h0") - T_916[1] <= UInt<1>("h1") - T_916[2] <= UInt<2>("h2") - node T_921 = eq(T_916[0], io.out.bits.r_type) - node T_922 = eq(T_916[1], io.out.bits.r_type) - node T_923 = eq(T_916[2], io.out.bits.r_type) - node T_925 = or(UInt<1>("h0"), T_921) - node T_926 = or(T_925, T_922) - node T_927 = or(T_926, T_923) - node T_928 = and(UInt<1>("h1"), T_927) - when T_928 : - T_909 <= T_912 - node T_930 = eq(T_700, UInt<1>("h0")) - when T_930 : - T_700 <= UInt<1>("h1") - node T_932 = and(io.in[0].ready, io.in[0].valid) - node T_933 = and(io.in[1].ready, io.in[1].valid) - wire T_935 : UInt<1>[2] - T_935[0] <= T_932 - T_935[1] <= T_933 - node T_941 = mux(T_935[0], UInt<1>("h0"), UInt<1>("h1")) - T_702 <= T_941 - skip - skip - node T_943 = eq(T_912, UInt<1>("h0")) - when T_943 : - T_700 <= UInt<1>("h0") - skip - skip - node choose = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_948 = mux(T_700, T_702, choose) - T_704 <= T_948 - module HellaCache : - input clk : Clock - input reset : UInt<1> - output io : {flip cpu : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io is invalid - inst wb of WritebackUnit - wb.io is invalid - wb.clk <= clk - wb.reset <= reset - inst prober of ProbeUnit - prober.io is invalid - prober.clk <= clk - prober.reset <= reset - inst mshrs of MSHRFile - mshrs.io is invalid - mshrs.clk <= clk - mshrs.reset <= reset - io.cpu.req.ready <= UInt<1>("h1") - node T_1622 = and(io.cpu.req.ready, io.cpu.req.valid) - reg s1_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - s1_valid <= T_1622 - reg s1_req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), s1_req) - node T_1680 = eq(io.cpu.req.bits.kill, UInt<1>("h0")) - node s1_valid_masked = and(s1_valid, T_1680) - reg s1_replay : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg s1_clk_en : UInt<1>, clk with : - reset => (UInt<1>("h0"), s1_clk_en) - reg s2_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - s2_valid <= s1_valid_masked - node T_1688 = and(s1_valid, io.cpu.req.bits.kill) - reg s2_killed : UInt<1>, clk with : - reset => (UInt<1>("h0"), s2_killed) - s2_killed <= T_1688 - reg s2_req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), s2_req) - reg T_1745 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_1745 <= s1_replay - node T_1746 = neq(s2_req.cmd, UInt<5>("h5")) - node s2_replay = and(T_1745, T_1746) - wire s2_recycle : UInt<1> - s2_recycle is invalid - wire s2_valid_masked : UInt<1> - s2_valid_masked is invalid - reg s3_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg s3_req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), s3_req) - reg s3_way : UInt, clk with : - reset => (UInt<1>("h0"), s3_way) - reg s1_recycled : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - when s1_clk_en : - s1_recycled <= s2_recycle - skip - node T_1812 = eq(s1_req.cmd, UInt<5>("h0")) - node T_1813 = eq(s1_req.cmd, UInt<5>("h6")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = eq(s1_req.cmd, UInt<5>("h7")) - node T_1816 = or(T_1814, T_1815) - node T_1817 = bits(s1_req.cmd, 3, 3) - node T_1818 = eq(s1_req.cmd, UInt<5>("h4")) - node T_1819 = or(T_1817, T_1818) - node s1_read = or(T_1816, T_1819) - node T_1821 = eq(s1_req.cmd, UInt<5>("h1")) - node T_1822 = eq(s1_req.cmd, UInt<5>("h7")) - node T_1823 = or(T_1821, T_1822) - node T_1824 = bits(s1_req.cmd, 3, 3) - node T_1825 = eq(s1_req.cmd, UInt<5>("h4")) - node T_1826 = or(T_1824, T_1825) - node s1_write = or(T_1823, T_1826) - node T_1828 = or(s1_read, s1_write) - node T_1829 = eq(s1_req.cmd, UInt<5>("h2")) - node T_1830 = eq(s1_req.cmd, UInt<5>("h3")) - node T_1831 = or(T_1829, T_1830) - node s1_readwrite = or(T_1828, T_1831) - inst dtlb of TLB - dtlb.io is invalid - dtlb.clk <= clk - dtlb.reset <= reset - io.ptw <- dtlb.io.ptw - node T_1834 = and(s1_valid_masked, s1_readwrite) - node T_1836 = eq(s1_req.phys, UInt<1>("h0")) - node T_1837 = and(T_1834, T_1836) - dtlb.io.req.valid <= T_1837 - dtlb.io.req.bits.passthrough <= s1_req.phys - dtlb.io.req.bits.asid <= UInt<1>("h0") - node T_1839 = shr(s1_req.addr, 12) - dtlb.io.req.bits.vpn <= T_1839 - dtlb.io.req.bits.instruction <= UInt<1>("h0") - dtlb.io.req.bits.store <= s1_write - node T_1842 = eq(dtlb.io.req.ready, UInt<1>("h0")) - node T_1844 = eq(io.cpu.req.bits.phys, UInt<1>("h0")) - node T_1845 = and(T_1842, T_1844) - when T_1845 : - io.cpu.req.ready <= UInt<1>("h0") - skip - when io.cpu.req.valid : - s1_req <- io.cpu.req.bits - skip - when wb.io.meta_read.valid : - node T_1847 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) - node T_1848 = shl(T_1847, 6) - s1_req.addr <= T_1848 - s1_req.phys <= UInt<1>("h1") - skip - when prober.io.meta_read.valid : - node T_1850 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) - node T_1851 = shl(T_1850, 6) - s1_req.addr <= T_1851 - s1_req.phys <= UInt<1>("h1") - skip - when mshrs.io.replay.valid : - s1_req <- mshrs.io.replay.bits - skip - when s2_recycle : - s1_req <- s2_req - skip - node T_1853 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.io.resp.ppn, T_1853) - when s1_clk_en : - s2_req.kill <= s1_req.kill - s2_req.typ <= s1_req.typ - s2_req.phys <= s1_req.phys - s2_req.addr <= s1_addr - when s1_write : - node T_1855 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) - s2_req.data <= T_1855 - skip - when s1_recycled : - s2_req.data <= s1_req.data - skip - s2_req.tag <= s1_req.tag - s2_req.cmd <= s1_req.cmd - skip - node T_1857 = bits(s1_req.typ, 1, 0) - node T_1859 = dshl(UInt<1>("h1"), T_1857) - node T_1861 = sub(T_1859, UInt<1>("h1")) - node T_1862 = tail(T_1861, 1) - node T_1863 = bits(T_1862, 2, 0) - node T_1864 = and(s1_req.addr, T_1863) - node misaligned = neq(T_1864, UInt<1>("h0")) - node T_1867 = and(s1_read, misaligned) - io.cpu.xcpt.ma.ld <= T_1867 - node T_1868 = and(s1_write, misaligned) - io.cpu.xcpt.ma.st <= T_1868 - node T_1869 = and(s1_read, dtlb.io.resp.xcpt_ld) - io.cpu.xcpt.pf.ld <= T_1869 - node T_1870 = and(s1_write, dtlb.io.resp.xcpt_st) - io.cpu.xcpt.pf.st <= T_1870 - node T_1871 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) - node T_1872 = or(T_1871, io.cpu.xcpt.pf.ld) - node T_1873 = or(T_1872, io.cpu.xcpt.pf.st) - reg T_1874 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_1874) - T_1874 <= T_1873 - node T_1875 = and(T_1874, io.cpu.resp.valid) - node T_1877 = eq(T_1875, UInt<1>("h0")) - node T_1879 = eq(reset, UInt<1>("h0")) - when T_1879 : - node T_1881 = eq(T_1877, UInt<1>("h0")) - when T_1881 : - node T_1883 = eq(reset, UInt<1>("h0")) - when T_1883 : - printf(clk, UInt<1>("h1"), "Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.") - skip - stop(clk, UInt<1>("h1"), 1) - skip - skip - inst meta of MetadataArray - meta.io is invalid - meta.clk <= clk - meta.reset <= reset - inst metaReadArb of Arbiter_105 - metaReadArb.io is invalid - metaReadArb.clk <= clk - metaReadArb.reset <= reset - inst metaWriteArb of Arbiter_94 - metaWriteArb.io is invalid - metaWriteArb.clk <= clk - metaWriteArb.reset <= reset - meta.io.read <- metaReadArb.io.out - meta.io.write <- metaWriteArb.io.out - inst data of DataArray - data.io is invalid - data.clk <= clk - data.reset <= reset - inst readArb of Arbiter_107 - readArb.io is invalid - readArb.clk <= clk - readArb.reset <= reset - inst writeArb of Arbiter_108 - writeArb.io is invalid - writeArb.clk <= clk - writeArb.reset <= reset - data.io.write.valid <= writeArb.io.out.valid - writeArb.io.out.ready <= data.io.write.ready - data.io.write.bits <- writeArb.io.out.bits - node T_2141 = bits(writeArb.io.out.bits.data, 63, 0) - node T_2142 = bits(writeArb.io.out.bits.data, 127, 64) - wire T_2144 : UInt<64>[2] - T_2144[0] <= T_2141 - T_2144[1] <= T_2142 - node T_2148 = cat(T_2144[1], T_2144[0]) - data.io.write.bits.data <= T_2148 - metaReadArb.io.in[4].valid <= io.cpu.req.valid - node T_2149 = shr(io.cpu.req.bits.addr, 6) - metaReadArb.io.in[4].bits.idx <= T_2149 - node T_2151 = eq(metaReadArb.io.in[4].ready, UInt<1>("h0")) - when T_2151 : - io.cpu.req.ready <= UInt<1>("h0") - skip - readArb.io.in[3].valid <= io.cpu.req.valid - readArb.io.in[3].bits.addr <= io.cpu.req.bits.addr - node T_2154 = not(UInt<4>("h0")) - readArb.io.in[3].bits.way_en <= T_2154 - node T_2156 = eq(readArb.io.in[3].ready, UInt<1>("h0")) - when T_2156 : - io.cpu.req.ready <= UInt<1>("h0") - skip - metaReadArb.io.in[0].valid <= s2_recycle - node T_2158 = shr(s2_req.addr, 6) - metaReadArb.io.in[0].bits.idx <= T_2158 - readArb.io.in[0].valid <= s2_recycle - readArb.io.in[0].bits.addr <= s2_req.addr - node T_2160 = not(UInt<4>("h0")) - readArb.io.in[0].bits.way_en <= T_2160 - node T_2161 = shr(s1_addr, 12) - node T_2162 = eq(meta.io.resp[0].tag, T_2161) - node T_2163 = shr(s1_addr, 12) - node T_2164 = eq(meta.io.resp[1].tag, T_2163) - node T_2165 = shr(s1_addr, 12) - node T_2166 = eq(meta.io.resp[2].tag, T_2165) - node T_2167 = shr(s1_addr, 12) - node T_2168 = eq(meta.io.resp[3].tag, T_2167) - wire T_2170 : UInt<1>[4] - T_2170[0] <= T_2162 - T_2170[1] <= T_2164 - T_2170[2] <= T_2166 - T_2170[3] <= T_2168 - node T_2176 = cat(T_2170[3], T_2170[2]) - node T_2177 = cat(T_2170[1], T_2170[0]) - node s1_tag_eq_way = cat(T_2176, T_2177) - node T_2179 = bits(s1_tag_eq_way, 0, 0) - node T_2180 = neq(meta.io.resp[0].coh.state, UInt<1>("h0")) - node T_2181 = and(T_2179, T_2180) - node T_2182 = bits(s1_tag_eq_way, 1, 1) - node T_2183 = neq(meta.io.resp[1].coh.state, UInt<1>("h0")) - node T_2184 = and(T_2182, T_2183) - node T_2185 = bits(s1_tag_eq_way, 2, 2) - node T_2186 = neq(meta.io.resp[2].coh.state, UInt<1>("h0")) - node T_2187 = and(T_2185, T_2186) - node T_2188 = bits(s1_tag_eq_way, 3, 3) - node T_2189 = neq(meta.io.resp[3].coh.state, UInt<1>("h0")) - node T_2190 = and(T_2188, T_2189) - wire T_2192 : UInt<1>[4] - T_2192[0] <= T_2181 - T_2192[1] <= T_2184 - T_2192[2] <= T_2187 - T_2192[3] <= T_2190 - node T_2198 = cat(T_2192[3], T_2192[2]) - node T_2199 = cat(T_2192[1], T_2192[0]) - node s1_tag_match_way = cat(T_2198, T_2199) - s1_clk_en <= metaReadArb.io.out.valid - node T_2202 = eq(s1_valid, UInt<1>("h0")) - node T_2203 = and(s1_clk_en, T_2202) - node T_2205 = eq(s1_replay, UInt<1>("h0")) - node s1_writeback = and(T_2203, T_2205) - reg s2_tag_match_way : UInt<4>, clk with : - reset => (UInt<1>("h0"), s2_tag_match_way) - when s1_clk_en : - s2_tag_match_way <= s1_tag_match_way - skip - node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h0")) - reg T_2210 : { state : UInt<2>}, clk with : - reset => (UInt<1>("h0"), T_2210) - when s1_clk_en : - T_2210 <- meta.io.resp[0].coh - skip - reg T_2235 : { state : UInt<2>}, clk with : - reset => (UInt<1>("h0"), T_2235) - when s1_clk_en : - T_2235 <- meta.io.resp[1].coh - skip - reg T_2260 : { state : UInt<2>}, clk with : - reset => (UInt<1>("h0"), T_2260) - when s1_clk_en : - T_2260 <- meta.io.resp[2].coh - skip - reg T_2285 : { state : UInt<2>}, clk with : - reset => (UInt<1>("h0"), T_2285) - when s1_clk_en : - T_2285 <- meta.io.resp[3].coh - skip - wire T_2335 : { state : UInt<2>}[4] - T_2335[0] <- T_2210 - T_2335[1] <- T_2235 - T_2335[2] <- T_2260 - T_2335[3] <- T_2285 - node T_2461 = bits(s2_tag_match_way, 0, 0) - node T_2462 = bits(s2_tag_match_way, 1, 1) - node T_2463 = bits(s2_tag_match_way, 2, 2) - node T_2464 = bits(s2_tag_match_way, 3, 3) - node T_2466 = mux(T_2461, T_2335[0].state, UInt<1>("h0")) - node T_2468 = mux(T_2462, T_2335[1].state, UInt<1>("h0")) - node T_2470 = mux(T_2463, T_2335[2].state, UInt<1>("h0")) - node T_2472 = mux(T_2464, T_2335[3].state, UInt<1>("h0")) - node T_2498 = or(T_2466, T_2468) - node T_2499 = or(T_2498, T_2470) - node T_2500 = or(T_2499, T_2472) - wire s2_hit_state : { state : UInt<2>} - s2_hit_state is invalid - node T_2551 = bits(T_2500, 1, 0) - s2_hit_state.state <= T_2551 - node T_2552 = eq(s2_req.cmd, UInt<5>("h1")) - node T_2553 = eq(s2_req.cmd, UInt<5>("h7")) - node T_2554 = or(T_2552, T_2553) - node T_2555 = bits(s2_req.cmd, 3, 3) - node T_2556 = eq(s2_req.cmd, UInt<5>("h4")) - node T_2557 = or(T_2555, T_2556) - node T_2558 = or(T_2554, T_2557) - node T_2559 = eq(s2_req.cmd, UInt<5>("h3")) - node T_2560 = or(T_2558, T_2559) - node T_2561 = eq(s2_req.cmd, UInt<5>("h6")) - node T_2562 = or(T_2560, T_2561) - wire T_2564 : UInt<2>[2] - T_2564[0] <= UInt<2>("h2") - T_2564[1] <= UInt<2>("h3") - node T_2568 = eq(T_2564[0], s2_hit_state.state) - node T_2569 = eq(T_2564[1], s2_hit_state.state) - node T_2571 = or(UInt<1>("h0"), T_2568) - node T_2572 = or(T_2571, T_2569) - wire T_2574 : UInt<2>[3] - T_2574[0] <= UInt<1>("h1") - T_2574[1] <= UInt<2>("h2") - T_2574[2] <= UInt<2>("h3") - node T_2579 = eq(T_2574[0], s2_hit_state.state) - node T_2580 = eq(T_2574[1], s2_hit_state.state) - node T_2581 = eq(T_2574[2], s2_hit_state.state) - node T_2583 = or(UInt<1>("h0"), T_2579) - node T_2584 = or(T_2583, T_2580) - node T_2585 = or(T_2584, T_2581) - node T_2586 = mux(T_2562, T_2572, T_2585) - node T_2587 = and(s2_tag_match, T_2586) - node T_2588 = eq(s2_req.cmd, UInt<5>("h1")) - node T_2589 = eq(s2_req.cmd, UInt<5>("h7")) - node T_2590 = or(T_2588, T_2589) - node T_2591 = bits(s2_req.cmd, 3, 3) - node T_2592 = eq(s2_req.cmd, UInt<5>("h4")) - node T_2593 = or(T_2591, T_2592) - node T_2594 = or(T_2590, T_2593) - node T_2595 = mux(T_2594, UInt<2>("h3"), s2_hit_state.state) - wire T_2621 : { state : UInt<2>} - T_2621 is invalid - T_2621.state <= T_2595 - node T_2646 = eq(s2_hit_state.state, T_2621.state) - node s2_hit = and(T_2587, T_2646) - reg lrsc_count : UInt, clk with : - reset => (reset, UInt<1>("h0")) - node lrsc_valid = neq(lrsc_count, UInt<1>("h0")) - reg lrsc_addr : UInt, clk with : - reset => (UInt<1>("h0"), lrsc_addr) - node s2_lr = eq(s2_req.cmd, UInt<5>("h6")) - node s2_sc = eq(s2_req.cmd, UInt<5>("h7")) - node T_2656 = shr(s2_req.addr, 6) - node T_2657 = eq(lrsc_addr, T_2656) - node s2_lrsc_addr_match = and(lrsc_valid, T_2657) - node T_2660 = eq(s2_lrsc_addr_match, UInt<1>("h0")) - node s2_sc_fail = and(s2_sc, T_2660) - when lrsc_valid : - node T_2663 = sub(lrsc_count, UInt<1>("h1")) - node T_2664 = tail(T_2663, 1) - lrsc_count <= T_2664 - skip - node T_2665 = and(s2_valid_masked, s2_hit) - node T_2666 = or(T_2665, s2_replay) - when T_2666 : - when s2_lr : - node T_2668 = eq(lrsc_valid, UInt<1>("h0")) - when T_2668 : - lrsc_count <= UInt<5>("h1f") - skip - node T_2670 = shr(s2_req.addr, 6) - lrsc_addr <= T_2670 - skip - when s2_sc : - lrsc_count <= UInt<1>("h0") - skip - skip - when io.cpu.invalidate_lr : - lrsc_count <= UInt<1>("h0") - skip - wire s2_data : UInt<128>[4] - s2_data is invalid - reg T_2697 : UInt<64>[2], clk with : - reset => (UInt<1>("h0"), T_2697) - node T_2701 = bits(s1_tag_eq_way, 0, 0) - node T_2702 = and(s1_clk_en, T_2701) - node T_2706 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2707 = or(UInt<1>("h1"), T_2706) - node T_2708 = or(T_2707, s1_writeback) - node T_2709 = and(T_2702, T_2708) - when T_2709 : - node T_2710 = shr(data.io.resp[0], 0) - T_2697[0] <= T_2710 - skip - node T_2714 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2715 = or(UInt<1>("h0"), T_2714) - node T_2716 = or(T_2715, s1_writeback) - node T_2717 = and(T_2702, T_2716) - when T_2717 : - node T_2718 = shr(data.io.resp[0], 64) - T_2697[1] <= T_2718 - skip - node T_2719 = cat(T_2697[1], T_2697[0]) - s2_data[0] <= T_2719 - reg T_2728 : UInt<64>[2], clk with : - reset => (UInt<1>("h0"), T_2728) - node T_2732 = bits(s1_tag_eq_way, 1, 1) - node T_2733 = and(s1_clk_en, T_2732) - node T_2737 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2738 = or(UInt<1>("h1"), T_2737) - node T_2739 = or(T_2738, s1_writeback) - node T_2740 = and(T_2733, T_2739) - when T_2740 : - node T_2741 = shr(data.io.resp[1], 0) - T_2728[0] <= T_2741 - skip - node T_2745 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2746 = or(UInt<1>("h0"), T_2745) - node T_2747 = or(T_2746, s1_writeback) - node T_2748 = and(T_2733, T_2747) - when T_2748 : - node T_2749 = shr(data.io.resp[1], 64) - T_2728[1] <= T_2749 - skip - node T_2750 = cat(T_2728[1], T_2728[0]) - s2_data[1] <= T_2750 - reg T_2759 : UInt<64>[2], clk with : - reset => (UInt<1>("h0"), T_2759) - node T_2763 = bits(s1_tag_eq_way, 2, 2) - node T_2764 = and(s1_clk_en, T_2763) - node T_2768 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2769 = or(UInt<1>("h1"), T_2768) - node T_2770 = or(T_2769, s1_writeback) - node T_2771 = and(T_2764, T_2770) - when T_2771 : - node T_2772 = shr(data.io.resp[2], 0) - T_2759[0] <= T_2772 - skip - node T_2776 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2777 = or(UInt<1>("h0"), T_2776) - node T_2778 = or(T_2777, s1_writeback) - node T_2779 = and(T_2764, T_2778) - when T_2779 : - node T_2780 = shr(data.io.resp[2], 64) - T_2759[1] <= T_2780 - skip - node T_2781 = cat(T_2759[1], T_2759[0]) - s2_data[2] <= T_2781 - reg T_2790 : UInt<64>[2], clk with : - reset => (UInt<1>("h0"), T_2790) - node T_2794 = bits(s1_tag_eq_way, 3, 3) - node T_2795 = and(s1_clk_en, T_2794) - node T_2799 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2800 = or(UInt<1>("h1"), T_2799) - node T_2801 = or(T_2800, s1_writeback) - node T_2802 = and(T_2795, T_2801) - when T_2802 : - node T_2803 = shr(data.io.resp[3], 0) - T_2790[0] <= T_2803 - skip - node T_2807 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_2808 = or(UInt<1>("h0"), T_2807) - node T_2809 = or(T_2808, s1_writeback) - node T_2810 = and(T_2795, T_2809) - when T_2810 : - node T_2811 = shr(data.io.resp[3], 64) - T_2790[1] <= T_2811 - skip - node T_2812 = cat(T_2790[1], T_2790[0]) - s2_data[3] <= T_2812 - node T_2813 = bits(s2_tag_match_way, 0, 0) - node T_2814 = bits(s2_tag_match_way, 1, 1) - node T_2815 = bits(s2_tag_match_way, 2, 2) - node T_2816 = bits(s2_tag_match_way, 3, 3) - node T_2818 = mux(T_2813, s2_data[0], UInt<1>("h0")) - node T_2820 = mux(T_2814, s2_data[1], UInt<1>("h0")) - node T_2822 = mux(T_2815, s2_data[2], UInt<1>("h0")) - node T_2824 = mux(T_2816, s2_data[3], UInt<1>("h0")) - node T_2826 = or(T_2818, T_2820) - node T_2827 = or(T_2826, T_2822) - node T_2828 = or(T_2827, T_2824) - wire s2_data_muxed : UInt<128> - s2_data_muxed is invalid - s2_data_muxed <= T_2828 - node T_2830 = bits(s2_data_muxed, 63, 0) - node T_2831 = bits(s2_data_muxed, 127, 64) - wire T_2833 : UInt<64>[2] - T_2833[0] <= T_2830 - T_2833[1] <= T_2831 - node s2_data_corrected = cat(T_2833[1], T_2833[0]) - wire T_2839 : UInt<64>[2] - T_2839[0] <= T_2830 - T_2839[1] <= T_2831 - node s2_data_uncorrected = cat(T_2839[1], T_2839[0]) - wire T_2848 : UInt<1>[2] - T_2848[0] <= UInt<1>("h0") - T_2848[1] <= UInt<1>("h0") - node T_2852 = cat(T_2848[1], T_2848[0]) - node T_2853 = dshr(T_2852, UInt<1>("h0")) - node s2_data_correctable = bits(T_2853, 0, 0) - node T_2855 = and(s2_valid_masked, s2_hit) - node T_2856 = or(T_2855, s2_replay) - node T_2858 = eq(s2_sc_fail, UInt<1>("h0")) - node T_2859 = and(T_2856, T_2858) - node T_2860 = eq(s2_req.cmd, UInt<5>("h1")) - node T_2861 = eq(s2_req.cmd, UInt<5>("h7")) - node T_2862 = or(T_2860, T_2861) - node T_2863 = bits(s2_req.cmd, 3, 3) - node T_2864 = eq(s2_req.cmd, UInt<5>("h4")) - node T_2865 = or(T_2863, T_2864) - node T_2866 = or(T_2862, T_2865) - node T_2867 = and(T_2859, T_2866) - s3_valid <= T_2867 - inst amoalu of AMOALU - amoalu.io is invalid - amoalu.clk <= clk - amoalu.reset <= reset - node T_2869 = or(s2_valid, s2_replay) - node T_2870 = eq(s2_req.cmd, UInt<5>("h1")) - node T_2871 = eq(s2_req.cmd, UInt<5>("h7")) - node T_2872 = or(T_2870, T_2871) - node T_2873 = bits(s2_req.cmd, 3, 3) - node T_2874 = eq(s2_req.cmd, UInt<5>("h4")) - node T_2875 = or(T_2873, T_2874) - node T_2876 = or(T_2872, T_2875) - node T_2877 = or(T_2876, s2_data_correctable) - node T_2878 = and(T_2869, T_2877) - when T_2878 : - s3_req <- s2_req - node T_2879 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) - s3_req.data <= T_2879 - s3_way <= s2_tag_match_way - skip - writeArb.io.in[0].bits.addr <= s3_req.addr - node rowIdx = bits(s3_req.addr, 3, 3) - node rowWMask = dshl(UInt<1>("h1"), rowIdx) - writeArb.io.in[0].bits.wmask <= rowWMask - node T_2883 = cat(s3_req.data, s3_req.data) - writeArb.io.in[0].bits.data <= T_2883 - writeArb.io.in[0].valid <= s3_valid - writeArb.io.in[0].bits.way_en <= s3_way - wire T_2885 : UInt<1> - T_2885 is invalid - T_2885 <= UInt<1>("h0") - reg T_2888 : UInt<16>, clk with : - reset => (reset, UInt<16>("h1")) - when T_2885 : - node T_2889 = bits(T_2888, 0, 0) - node T_2890 = bits(T_2888, 2, 2) - node T_2891 = xor(T_2889, T_2890) - node T_2892 = bits(T_2888, 3, 3) - node T_2893 = xor(T_2891, T_2892) - node T_2894 = bits(T_2888, 5, 5) - node T_2895 = xor(T_2893, T_2894) - node T_2896 = bits(T_2888, 15, 1) - node T_2897 = cat(T_2895, T_2896) - T_2888 <= T_2897 - skip - node T_2898 = bits(T_2888, 1, 0) - node s1_replaced_way_en = dshl(UInt<1>("h1"), T_2898) - node T_2901 = bits(T_2888, 1, 0) - reg T_2902 : UInt<2>, clk with : - reset => (UInt<1>("h0"), T_2902) - when s1_clk_en : - T_2902 <= T_2901 - skip - node s2_replaced_way_en = dshl(UInt<1>("h1"), T_2902) - node T_2905 = bits(s1_replaced_way_en, 0, 0) - node T_2906 = and(s1_clk_en, T_2905) - reg T_2907 : { tag : UInt<20>, coh : { state : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), T_2907) - when T_2906 : - T_2907 <- meta.io.resp[0] - skip - node T_2980 = bits(s1_replaced_way_en, 1, 1) - node T_2981 = and(s1_clk_en, T_2980) - reg T_2982 : { tag : UInt<20>, coh : { state : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), T_2982) - when T_2981 : - T_2982 <- meta.io.resp[1] - skip - node T_3055 = bits(s1_replaced_way_en, 2, 2) - node T_3056 = and(s1_clk_en, T_3055) - reg T_3057 : { tag : UInt<20>, coh : { state : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), T_3057) - when T_3056 : - T_3057 <- meta.io.resp[2] - skip - node T_3130 = bits(s1_replaced_way_en, 3, 3) - node T_3131 = and(s1_clk_en, T_3130) - reg T_3132 : { tag : UInt<20>, coh : { state : UInt<2>}}, clk with : - reset => (UInt<1>("h0"), T_3132) - when T_3131 : - T_3132 <- meta.io.resp[3] - skip - wire T_3278 : { tag : UInt<20>, coh : { state : UInt<2>}}[4] - T_3278[0] <- T_2907 - T_3278[1] <- T_2982 - T_3278[2] <- T_3057 - T_3278[3] <- T_3132 - node T_3644 = bits(s2_replaced_way_en, 0, 0) - node T_3645 = bits(s2_replaced_way_en, 1, 1) - node T_3646 = bits(s2_replaced_way_en, 2, 2) - node T_3647 = bits(s2_replaced_way_en, 3, 3) - node T_3648 = cat(T_3278[0].tag, T_3278[0].coh.state) - node T_3650 = mux(T_3644, T_3648, UInt<1>("h0")) - node T_3651 = cat(T_3278[1].tag, T_3278[1].coh.state) - node T_3653 = mux(T_3645, T_3651, UInt<1>("h0")) - node T_3654 = cat(T_3278[2].tag, T_3278[2].coh.state) - node T_3656 = mux(T_3646, T_3654, UInt<1>("h0")) - node T_3657 = cat(T_3278[3].tag, T_3278[3].coh.state) - node T_3659 = mux(T_3647, T_3657, UInt<1>("h0")) - node T_3733 = or(T_3650, T_3653) - node T_3734 = or(T_3733, T_3656) - node T_3735 = or(T_3734, T_3659) - wire s2_repl_meta : { tag : UInt<20>, coh : { state : UInt<2>}} - s2_repl_meta is invalid - node T_3882 = bits(T_3735, 1, 0) - s2_repl_meta.coh.state <= T_3882 - node T_3883 = bits(T_3735, 21, 2) - s2_repl_meta.tag <= T_3883 - node T_3885 = eq(s2_hit, UInt<1>("h0")) - node T_3886 = and(s2_valid_masked, T_3885) - node T_3887 = eq(s2_req.cmd, UInt<5>("h2")) - node T_3888 = eq(s2_req.cmd, UInt<5>("h3")) - node T_3889 = or(T_3887, T_3888) - node T_3890 = eq(s2_req.cmd, UInt<5>("h0")) - node T_3891 = eq(s2_req.cmd, UInt<5>("h6")) - node T_3892 = or(T_3890, T_3891) - node T_3893 = eq(s2_req.cmd, UInt<5>("h7")) - node T_3894 = or(T_3892, T_3893) - node T_3895 = bits(s2_req.cmd, 3, 3) - node T_3896 = eq(s2_req.cmd, UInt<5>("h4")) - node T_3897 = or(T_3895, T_3896) - node T_3898 = or(T_3894, T_3897) - node T_3899 = or(T_3889, T_3898) - node T_3900 = eq(s2_req.cmd, UInt<5>("h1")) - node T_3901 = eq(s2_req.cmd, UInt<5>("h7")) - node T_3902 = or(T_3900, T_3901) - node T_3903 = bits(s2_req.cmd, 3, 3) - node T_3904 = eq(s2_req.cmd, UInt<5>("h4")) - node T_3905 = or(T_3903, T_3904) - node T_3906 = or(T_3902, T_3905) - node T_3907 = or(T_3899, T_3906) - node T_3908 = and(T_3886, T_3907) - mshrs.io.req.valid <= T_3908 - mshrs.io.req.bits <- s2_req - mshrs.io.req.bits.tag_match <= s2_tag_match - wire T_3982 : { tag : UInt<20>, coh : { state : UInt<2>}} - T_3982 is invalid - T_3982.tag <= s2_repl_meta.tag - T_3982.coh <- s2_hit_state - node T_4055 = mux(s2_tag_match, T_3982, s2_repl_meta) - mshrs.io.req.bits.old_meta <- T_4055 - node T_4128 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) - mshrs.io.req.bits.way_en <= T_4128 - mshrs.io.req.bits.data <= s2_req.data - node T_4129 = and(mshrs.io.req.ready, mshrs.io.req.valid) - when T_4129 : - T_2885 <= UInt<1>("h1") - skip - io.mem.acquire <- mshrs.io.mem_req - readArb.io.in[1].valid <= mshrs.io.replay.valid - readArb.io.in[1].bits <- mshrs.io.replay.bits - node T_4132 = not(UInt<4>("h0")) - readArb.io.in[1].bits.way_en <= T_4132 - mshrs.io.replay.ready <= readArb.io.in[1].ready - node T_4133 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) - s1_replay <= T_4133 - metaReadArb.io.in[1] <- mshrs.io.meta_read - metaWriteArb.io.in[0] <- mshrs.io.meta_write - inst releaseArb of LockingArbiter_109 - releaseArb.io is invalid - releaseArb.clk <= clk - releaseArb.reset <= reset - io.mem.release <- releaseArb.io.out - node T_4166 = eq(lrsc_valid, UInt<1>("h0")) - node T_4167 = and(io.mem.probe.valid, T_4166) - prober.io.req.valid <= T_4167 - node T_4169 = eq(lrsc_valid, UInt<1>("h0")) - node T_4170 = and(prober.io.req.ready, T_4169) - io.mem.probe.ready <= T_4170 - prober.io.req.bits <- io.mem.probe.bits - releaseArb.io.in[1] <- prober.io.rep - prober.io.way_en <= s2_tag_match_way - prober.io.block_state <- s2_hit_state - metaReadArb.io.in[2] <- prober.io.meta_read - metaWriteArb.io.in[1] <- prober.io.meta_write - prober.io.mshr_rdy <= mshrs.io.probe_rdy - inst T_4171 of FlowThroughSerializer - T_4171.io is invalid - T_4171.clk <= clk - T_4171.reset <= reset - T_4171.io.in.valid <= io.mem.grant.valid - T_4171.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_4171.io.in.ready - node T_4172 = and(T_4171.io.out.ready, T_4171.io.out.valid) - mshrs.io.mem_grant.valid <= T_4172 - mshrs.io.mem_grant.bits <- T_4171.io.out.bits - wire T_4176 : UInt<3>[2] - T_4176[0] <= UInt<3>("h5") - T_4176[1] <= UInt<3>("h4") - node T_4180 = eq(T_4176[0], T_4171.io.out.bits.g_type) - node T_4181 = eq(T_4176[1], T_4171.io.out.bits.g_type) - node T_4183 = or(UInt<1>("h0"), T_4180) - node T_4184 = or(T_4183, T_4181) - wire T_4186 : UInt<1>[2] - T_4186[0] <= UInt<1>("h0") - T_4186[1] <= UInt<1>("h1") - node T_4190 = eq(T_4186[0], T_4171.io.out.bits.g_type) - node T_4191 = eq(T_4186[1], T_4171.io.out.bits.g_type) - node T_4193 = or(UInt<1>("h0"), T_4190) - node T_4194 = or(T_4193, T_4191) - node T_4195 = mux(T_4171.io.out.bits.is_builtin_type, T_4184, T_4194) - node T_4197 = eq(T_4195, UInt<1>("h0")) - node T_4198 = or(writeArb.io.in[1].ready, T_4197) - T_4171.io.out.ready <= T_4198 - wire T_4202 : UInt<3>[2] - T_4202[0] <= UInt<3>("h5") - T_4202[1] <= UInt<3>("h4") - node T_4206 = eq(T_4202[0], T_4171.io.out.bits.g_type) - node T_4207 = eq(T_4202[1], T_4171.io.out.bits.g_type) - node T_4209 = or(UInt<1>("h0"), T_4206) - node T_4210 = or(T_4209, T_4207) - wire T_4212 : UInt<1>[2] - T_4212[0] <= UInt<1>("h0") - T_4212[1] <= UInt<1>("h1") - node T_4216 = eq(T_4212[0], T_4171.io.out.bits.g_type) - node T_4217 = eq(T_4212[1], T_4171.io.out.bits.g_type) - node T_4219 = or(UInt<1>("h0"), T_4216) - node T_4220 = or(T_4219, T_4217) - node T_4221 = mux(T_4171.io.out.bits.is_builtin_type, T_4210, T_4220) - node T_4222 = and(T_4171.io.out.valid, T_4221) - node T_4224 = lt(T_4171.io.out.bits.client_xact_id, UInt<2>("h2")) - node T_4225 = and(T_4222, T_4224) - writeArb.io.in[1].valid <= T_4225 - writeArb.io.in[1].bits.addr <= mshrs.io.refill.addr - writeArb.io.in[1].bits.way_en <= mshrs.io.refill.way_en - node T_4227 = not(UInt<2>("h0")) - writeArb.io.in[1].bits.wmask <= T_4227 - node T_4228 = bits(T_4171.io.out.bits.data, 127, 0) - writeArb.io.in[1].bits.data <= T_4228 - data.io.read <- readArb.io.out - node T_4230 = eq(T_4171.io.out.valid, UInt<1>("h0")) - node T_4231 = or(T_4230, T_4171.io.out.ready) - readArb.io.out.ready <= T_4231 - inst wbArb of Arbiter_95 - wbArb.io is invalid - wbArb.clk <= clk - wbArb.reset <= reset - wbArb.io.in[0] <- prober.io.wb_req - wbArb.io.in[1] <- mshrs.io.wb_req - wb.io.req <- wbArb.io.out - metaReadArb.io.in[3] <- wb.io.meta_read - readArb.io.in[2] <- wb.io.data_req - wb.io.data_resp <= s2_data_corrected - releaseArb.io.in[0] <- wb.io.release - reg s4_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - s4_valid <= s3_valid - node T_4266 = and(s3_valid, metaReadArb.io.out.valid) - reg s4_req : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk with : - reset => (UInt<1>("h0"), s4_req) - when T_4266 : - s4_req <- s3_req - skip - node T_4321 = or(s2_valid_masked, s2_replay) - node T_4323 = eq(s2_sc_fail, UInt<1>("h0")) - node T_4324 = and(T_4321, T_4323) - node T_4325 = shr(s1_addr, 3) - node T_4326 = shr(s2_req.addr, 3) - node T_4327 = eq(T_4325, T_4326) - node T_4328 = and(T_4324, T_4327) - node T_4329 = eq(s2_req.cmd, UInt<5>("h1")) - node T_4330 = eq(s2_req.cmd, UInt<5>("h7")) - node T_4331 = or(T_4329, T_4330) - node T_4332 = bits(s2_req.cmd, 3, 3) - node T_4333 = eq(s2_req.cmd, UInt<5>("h4")) - node T_4334 = or(T_4332, T_4333) - node T_4335 = or(T_4331, T_4334) - node T_4336 = and(T_4328, T_4335) - node T_4337 = shr(s1_addr, 3) - node T_4338 = shr(s3_req.addr, 3) - node T_4339 = eq(T_4337, T_4338) - node T_4340 = and(s3_valid, T_4339) - node T_4341 = eq(s3_req.cmd, UInt<5>("h1")) - node T_4342 = eq(s3_req.cmd, UInt<5>("h7")) - node T_4343 = or(T_4341, T_4342) - node T_4344 = bits(s3_req.cmd, 3, 3) - node T_4345 = eq(s3_req.cmd, UInt<5>("h4")) - node T_4346 = or(T_4344, T_4345) - node T_4347 = or(T_4343, T_4346) - node T_4348 = and(T_4340, T_4347) - node T_4349 = shr(s1_addr, 3) - node T_4350 = shr(s4_req.addr, 3) - node T_4351 = eq(T_4349, T_4350) - node T_4352 = and(s4_valid, T_4351) - node T_4353 = eq(s4_req.cmd, UInt<5>("h1")) - node T_4354 = eq(s4_req.cmd, UInt<5>("h7")) - node T_4355 = or(T_4353, T_4354) - node T_4356 = bits(s4_req.cmd, 3, 3) - node T_4357 = eq(s4_req.cmd, UInt<5>("h4")) - node T_4358 = or(T_4356, T_4357) - node T_4359 = or(T_4355, T_4358) - node T_4360 = and(T_4352, T_4359) - reg s2_store_bypass_data : UInt<64>, clk with : - reset => (UInt<1>("h0"), s2_store_bypass_data) - reg s2_store_bypass : UInt<1>, clk with : - reset => (UInt<1>("h0"), s2_store_bypass) - when s1_clk_en : - s2_store_bypass <= UInt<1>("h0") - node T_4366 = or(T_4336, T_4348) - node T_4367 = or(T_4366, T_4360) - when T_4367 : - node T_4368 = mux(T_4348, s3_req.data, s4_req.data) - node T_4369 = mux(T_4336, amoalu.io.out, T_4368) - s2_store_bypass_data <= T_4369 - s2_store_bypass <= UInt<1>("h1") - skip - skip - node T_4372 = cat(UInt<1>("h0"), UInt<6>("h0")) - node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4372) - node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) - node T_4375 = bits(s2_req.typ, 1, 0) - node T_4376 = asSInt(s2_req.typ) - node T_4378 = geq(T_4376, asSInt(UInt<1>("h0"))) - amoalu.io.addr <= s2_req.addr - amoalu.io.cmd <= s2_req.cmd - amoalu.io.typ <= s2_req.typ - amoalu.io.lhs <= s2_data_word - amoalu.io.rhs <= s2_req.data - node T_4379 = and(dtlb.io.req.valid, dtlb.io.resp.miss) - node T_4380 = bits(s1_req.addr, 11, 6) - node T_4381 = eq(T_4380, prober.io.meta_write.bits.idx) - node T_4383 = eq(prober.io.req.ready, UInt<1>("h0")) - node T_4384 = and(T_4381, T_4383) - node s1_nack = or(T_4379, T_4384) - node T_4386 = or(s1_valid, s1_replay) - reg s2_nack_hit : UInt<1>, clk with : - reset => (UInt<1>("h0"), s2_nack_hit) - when T_4386 : - s2_nack_hit <= s1_nack - skip - when s2_nack_hit : - mshrs.io.req.valid <= UInt<1>("h0") - skip - node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss) - node T_4391 = eq(s2_hit, UInt<1>("h0")) - node T_4393 = eq(mshrs.io.req.ready, UInt<1>("h0")) - node s2_nack_miss = and(T_4391, T_4393) - node T_4395 = or(s2_nack_hit, s2_nack_victim) - node s2_nack = or(T_4395, s2_nack_miss) - node T_4398 = eq(s2_nack, UInt<1>("h0")) - node T_4399 = and(s2_valid, T_4398) - s2_valid_masked <= T_4399 - node T_4400 = or(s2_valid, s2_replay) - node T_4401 = and(T_4400, s2_hit) - node s2_recycle_ecc = and(T_4401, s2_data_correctable) - reg s2_recycle_next : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_4405 = or(s1_valid, s1_replay) - when T_4405 : - s2_recycle_next <= s2_recycle_ecc - skip - node T_4406 = or(s2_recycle_ecc, s2_recycle_next) - s2_recycle <= T_4406 - reg block_miss : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_4409 = or(s2_valid, block_miss) - node T_4410 = and(T_4409, s2_nack_miss) - block_miss <= T_4410 - when block_miss : - io.cpu.req.ready <= UInt<1>("h0") - skip - wire cache_resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - cache_resp is invalid - node T_4701 = and(s2_valid_masked, s2_hit) - node T_4702 = or(s2_replay, T_4701) - node T_4704 = eq(s2_data_correctable, UInt<1>("h0")) - node T_4705 = and(T_4702, T_4704) - cache_resp.valid <= T_4705 - cache_resp.bits <- s2_req - node T_4706 = eq(s2_req.cmd, UInt<5>("h0")) - node T_4707 = eq(s2_req.cmd, UInt<5>("h6")) - node T_4708 = or(T_4706, T_4707) - node T_4709 = eq(s2_req.cmd, UInt<5>("h7")) - node T_4710 = or(T_4708, T_4709) - node T_4711 = bits(s2_req.cmd, 3, 3) - node T_4712 = eq(s2_req.cmd, UInt<5>("h4")) - node T_4713 = or(T_4711, T_4712) - node T_4714 = or(T_4710, T_4713) - cache_resp.bits.has_data <= T_4714 - node T_4715 = bits(s2_req.addr, 2, 2) - node T_4716 = bits(s2_data_word, 63, 32) - node T_4717 = bits(s2_data_word, 31, 0) - node T_4718 = mux(T_4715, T_4716, T_4717) - node T_4720 = and(UInt<1>("h0"), s2_sc) - node T_4722 = mux(T_4720, UInt<1>("h0"), T_4718) - node T_4724 = eq(T_4375, UInt<2>("h2")) - node T_4725 = or(T_4724, T_4720) - node T_4726 = bits(T_4722, 31, 31) - node T_4727 = and(T_4378, T_4726) - node T_4729 = sub(UInt<32>("h0"), T_4727) - node T_4730 = tail(T_4729, 1) - node T_4731 = bits(s2_data_word, 63, 32) - node T_4732 = mux(T_4725, T_4730, T_4731) - node T_4733 = cat(T_4732, T_4722) - node T_4734 = bits(s2_req.addr, 1, 1) - node T_4735 = bits(T_4733, 31, 16) - node T_4736 = bits(T_4733, 15, 0) - node T_4737 = mux(T_4734, T_4735, T_4736) - node T_4739 = and(UInt<1>("h0"), s2_sc) - node T_4741 = mux(T_4739, UInt<1>("h0"), T_4737) - node T_4743 = eq(T_4375, UInt<1>("h1")) - node T_4744 = or(T_4743, T_4739) - node T_4745 = bits(T_4741, 15, 15) - node T_4746 = and(T_4378, T_4745) - node T_4748 = sub(UInt<48>("h0"), T_4746) - node T_4749 = tail(T_4748, 1) - node T_4750 = bits(T_4733, 63, 16) - node T_4751 = mux(T_4744, T_4749, T_4750) - node T_4752 = cat(T_4751, T_4741) - node T_4753 = bits(s2_req.addr, 0, 0) - node T_4754 = bits(T_4752, 15, 8) - node T_4755 = bits(T_4752, 7, 0) - node T_4756 = mux(T_4753, T_4754, T_4755) - node T_4758 = and(UInt<1>("h1"), s2_sc) - node T_4760 = mux(T_4758, UInt<1>("h0"), T_4756) - node T_4762 = eq(T_4375, UInt<1>("h0")) - node T_4763 = or(T_4762, T_4758) - node T_4764 = bits(T_4760, 7, 7) - node T_4765 = and(T_4378, T_4764) - node T_4767 = sub(UInt<56>("h0"), T_4765) - node T_4768 = tail(T_4767, 1) - node T_4769 = bits(T_4752, 63, 8) - node T_4770 = mux(T_4763, T_4768, T_4769) - node T_4771 = cat(T_4770, T_4760) - node T_4772 = or(T_4771, s2_sc_fail) - cache_resp.bits.data <= T_4772 - cache_resp.bits.store_data <= s2_req.data - node T_4773 = and(s2_valid, s2_nack) - cache_resp.bits.nack <= T_4773 - cache_resp.bits.replay <= s2_replay - wire uncache_resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - uncache_resp is invalid - uncache_resp.bits <- mshrs.io.resp.bits - uncache_resp.valid <= mshrs.io.resp.valid - node T_5063 = or(s2_valid, s2_killed) - node cache_pass = or(T_5063, s2_replay) - node T_5066 = eq(cache_pass, UInt<1>("h0")) - mshrs.io.resp.ready <= T_5066 - node T_5067 = mux(cache_pass, cache_resp, uncache_resp) - io.cpu.resp <- T_5067 - node T_5183 = bits(s2_req.addr, 2, 2) - node T_5184 = bits(s2_data_word, 63, 32) - node T_5185 = bits(s2_data_word, 31, 0) - node T_5186 = mux(T_5183, T_5184, T_5185) - node T_5188 = and(UInt<1>("h0"), s2_sc) - node T_5190 = mux(T_5188, UInt<1>("h0"), T_5186) - node T_5192 = eq(T_4375, UInt<2>("h2")) - node T_5193 = or(T_5192, T_5188) - node T_5194 = bits(T_5190, 31, 31) - node T_5195 = and(T_4378, T_5194) - node T_5197 = sub(UInt<32>("h0"), T_5195) - node T_5198 = tail(T_5197, 1) - node T_5199 = bits(s2_data_word, 63, 32) - node T_5200 = mux(T_5193, T_5198, T_5199) - node T_5201 = cat(T_5200, T_5190) - io.cpu.resp.bits.data_word_bypass <= T_5201 - node T_5203 = eq(s1_valid, UInt<1>("h0")) - node T_5204 = and(mshrs.io.fence_rdy, T_5203) - node T_5206 = eq(s2_valid, UInt<1>("h0")) - node T_5207 = and(T_5204, T_5206) - io.cpu.ordered <= T_5207 - node T_5208 = and(s1_replay, s1_read) - io.cpu.replay_next.valid <= T_5208 - io.cpu.replay_next.bits <= s1_req.tag - module RRArbiter_112 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} - io is invalid - wire T_152 : UInt<1> - T_152 is invalid - io.out.valid <= io.in[T_152].valid - io.out.bits <- io.in[T_152].bits - io.chosen <= T_152 - io.in[T_152].ready <= UInt<1>("h0") - reg T_195 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node T_196 = gt(UInt<1>("h0"), T_195) - node T_197 = and(io.in[0].valid, T_196) - node T_199 = gt(UInt<1>("h1"), T_195) - node T_200 = and(io.in[1].valid, T_199) - node T_203 = or(UInt<1>("h0"), T_197) - node T_205 = eq(T_203, UInt<1>("h0")) - node T_207 = or(UInt<1>("h0"), T_197) - node T_208 = or(T_207, T_200) - node T_210 = eq(T_208, UInt<1>("h0")) - node T_212 = or(UInt<1>("h0"), T_197) - node T_213 = or(T_212, T_200) - node T_214 = or(T_213, io.in[0].valid) - node T_216 = eq(T_214, UInt<1>("h0")) - node T_218 = gt(UInt<1>("h0"), T_195) - node T_219 = and(UInt<1>("h1"), T_218) - node T_220 = or(T_219, T_210) - node T_222 = gt(UInt<1>("h1"), T_195) - node T_223 = and(T_205, T_222) - node T_224 = or(T_223, T_216) - node T_226 = eq(UInt<1>("h1"), UInt<1>("h0")) - node T_227 = mux(UInt<1>("h0"), T_226, T_220) - node T_228 = and(T_227, io.out.ready) - io.in[0].ready <= T_228 - node T_230 = eq(UInt<1>("h1"), UInt<1>("h1")) - node T_231 = mux(UInt<1>("h0"), T_230, T_224) - node T_232 = and(T_231, io.out.ready) - io.in[1].ready <= T_232 - node T_235 = mux(io.in[0].valid, UInt<1>("h0"), UInt<1>("h1")) - node T_237 = gt(UInt<1>("h1"), T_195) - node T_238 = and(io.in[1].valid, T_237) - node T_240 = mux(T_238, UInt<1>("h1"), T_235) - node T_241 = mux(UInt<1>("h0"), UInt<1>("h1"), T_240) - T_152 <= T_241 - node T_242 = and(io.out.ready, io.out.valid) - when T_242 : - T_195 <= T_152 - skip - module PTW : - input clk : Clock - input reset : UInt<1> - output io : {flip requestor : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { error : UInt<1>, pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : { sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}} - io is invalid - reg state : UInt, clk with : - reset => (reset, UInt<1>("h0")) - reg count : UInt<2>, clk with : - reset => (UInt<1>("h0"), count) - reg r_req : { addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk with : - reset => (UInt<1>("h0"), r_req) - reg r_req_dest : UInt, clk with : - reset => (UInt<1>("h0"), r_req_dest) - reg r_pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk with : - reset => (UInt<1>("h0"), r_pte) - node T_1590 = shr(r_req.addr, 18) - node T_1591 = bits(T_1590, 8, 0) - node T_1592 = shr(r_req.addr, 9) - node T_1593 = bits(T_1592, 8, 0) - node T_1594 = shr(r_req.addr, 0) - node T_1595 = bits(T_1594, 8, 0) - wire T_1597 : UInt<9>[3] - T_1597[0] <= T_1591 - T_1597[1] <= T_1593 - T_1597[2] <= T_1595 - inst arb of RRArbiter_112 - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- io.requestor[0].req - arb.io.in[1] <- io.requestor[1].req - node T_1609 = eq(state, UInt<1>("h0")) - arb.io.out.ready <= T_1609 - wire pte : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte is invalid - node T_1631 = bits(io.mem.resp.bits.data, 0, 0) - pte.v <= T_1631 - node T_1632 = bits(io.mem.resp.bits.data, 4, 1) - pte.typ <= T_1632 - node T_1633 = bits(io.mem.resp.bits.data, 5, 5) - pte.r <= T_1633 - node T_1634 = bits(io.mem.resp.bits.data, 6, 6) - pte.d <= T_1634 - node T_1635 = bits(io.mem.resp.bits.data, 9, 7) - pte.reserved_for_software <= T_1635 - node T_1636 = bits(io.mem.resp.bits.data, 29, 10) - pte.ppn <= T_1636 - node T_1637 = cat(r_pte.ppn, T_1597[count]) - node pte_addr = shl(T_1637, 3) - node T_1639 = and(arb.io.out.ready, arb.io.out.valid) - when T_1639 : - r_req <- arb.io.out.bits - r_req_dest <= arb.io.chosen - node T_1640 = bits(io.dpath.ptbr, 31, 12) - r_pte.ppn <= T_1640 - skip - reg T_1642 : UInt<3>, clk with : - reset => (UInt<1>("h0"), T_1642) - reg T_1652 : UInt<1>[3], clk with : - reset => (UInt<1>("h0"), T_1652) - node T_1657 = cat(T_1652[1], T_1652[0]) - node T_1658 = cat(T_1652[2], T_1657) - mem T_1661 : - data-type => UInt<32> - depth => 3 - write-latency => 1 - read-latency => 0 - reader => T_1666 - reader => T_1669 - reader => T_1672 - writer => T_1721 - T_1661.T_1666.addr is invalid - T_1661.T_1666.clk <= clk - T_1661.T_1669.addr is invalid - T_1661.T_1669.clk <= clk - T_1661.T_1672.addr is invalid - T_1661.T_1672.clk <= clk - T_1661.T_1666.en <= UInt<1>("h0") - T_1661.T_1669.en <= UInt<1>("h0") - T_1661.T_1672.en <= UInt<1>("h0") - T_1661.T_1721.addr is invalid - T_1661.T_1721.clk <= clk - T_1661.T_1721.en <= UInt<1>("h0") - T_1661.T_1721.data is invalid - T_1661.T_1721.mask <= UInt<1>("h0") - mem T_1664 : - data-type => UInt<20> - depth => 3 - write-latency => 1 - read-latency => 0 - reader => T_1761 - reader => T_1763 - reader => T_1765 - writer => T_1722 - T_1664.T_1761.addr is invalid - T_1664.T_1761.clk <= clk - T_1664.T_1763.addr is invalid - T_1664.T_1763.clk <= clk - T_1664.T_1765.addr is invalid - T_1664.T_1765.clk <= clk - T_1664.T_1761.en <= UInt<1>("h0") - T_1664.T_1763.en <= UInt<1>("h0") - T_1664.T_1765.en <= UInt<1>("h0") - T_1664.T_1722.addr is invalid - T_1664.T_1722.clk <= clk - T_1664.T_1722.en <= UInt<1>("h0") - T_1664.T_1722.data is invalid - T_1664.T_1722.mask <= UInt<1>("h0") - T_1661.T_1666.addr <= UInt<1>("h0") - T_1661.T_1666.en <= UInt<1>("h1") - node T_1667 = eq(T_1661.T_1666.data, pte_addr) - T_1661.T_1669.addr <= UInt<1>("h1") - T_1661.T_1669.en <= UInt<1>("h1") - node T_1670 = eq(T_1661.T_1669.data, pte_addr) - T_1661.T_1672.addr <= UInt<2>("h2") - T_1661.T_1672.en <= UInt<1>("h1") - node T_1673 = eq(T_1661.T_1672.data, pte_addr) - wire T_1675 : UInt<1>[3] - T_1675[0] <= T_1667 - T_1675[1] <= T_1670 - T_1675[2] <= T_1673 - node T_1680 = cat(T_1675[1], T_1675[0]) - node T_1681 = cat(T_1675[2], T_1680) - node T_1682 = and(T_1681, T_1658) - node pte_cache_hit = neq(T_1682, UInt<1>("h0")) - node T_1686 = lt(pte.typ, UInt<2>("h2")) - node T_1687 = and(pte.v, T_1686) - node T_1688 = and(io.mem.resp.valid, T_1687) - node T_1690 = eq(pte_cache_hit, UInt<1>("h0")) - node T_1691 = and(T_1688, T_1690) - when T_1691 : - node T_1692 = not(T_1658) - node T_1694 = eq(T_1692, UInt<1>("h0")) - node T_1696 = dshr(T_1642, UInt<1>("h1")) - node T_1697 = bits(T_1696, 0, 0) - node T_1698 = cat(UInt<1>("h1"), T_1697) - node T_1699 = dshr(T_1642, T_1698) - node T_1700 = bits(T_1699, 0, 0) - node T_1701 = cat(T_1698, T_1700) - node T_1702 = bits(T_1701, 1, 0) - node T_1703 = not(T_1658) - node T_1704 = bits(T_1703, 0, 0) - node T_1705 = bits(T_1703, 1, 1) - node T_1706 = bits(T_1703, 2, 2) - wire T_1708 : UInt<1>[3] - T_1708[0] <= T_1704 - T_1708[1] <= T_1705 - T_1708[2] <= T_1706 - node T_1716 = mux(T_1708[1], UInt<1>("h1"), UInt<2>("h2")) - node T_1717 = mux(T_1708[0], UInt<1>("h0"), T_1716) - node T_1718 = mux(T_1694, T_1702, T_1717) - T_1652[T_1718] <= UInt<1>("h1") - T_1661.T_1721.addr <= T_1718 - T_1661.T_1721.en <= UInt<1>("h1") - T_1661.T_1721.data <= pte_addr - T_1661.T_1721.mask <= UInt<1>("h1") - T_1664.T_1722.addr <= T_1718 - T_1664.T_1722.en <= UInt<1>("h1") - T_1664.T_1722.data <= pte.ppn - T_1664.T_1722.mask <= UInt<1>("h1") - skip - node T_1723 = eq(state, UInt<1>("h1")) - node T_1724 = and(pte_cache_hit, T_1723) - when T_1724 : - node T_1725 = bits(T_1682, 2, 2) - node T_1726 = bits(T_1682, 1, 0) - node T_1728 = neq(T_1725, UInt<1>("h0")) - node T_1729 = or(T_1725, T_1726) - node T_1730 = bits(T_1729, 1, 1) - node T_1731 = cat(T_1728, T_1730) - node T_1733 = bits(T_1731, 1, 1) - node T_1735 = dshl(UInt<3>("h1"), UInt<1>("h1")) - node T_1736 = bits(T_1735, 2, 0) - node T_1737 = not(T_1736) - node T_1738 = and(T_1642, T_1737) - node T_1740 = mux(T_1733, UInt<1>("h0"), T_1736) - node T_1741 = or(T_1738, T_1740) - node T_1742 = cat(UInt<1>("h1"), T_1733) - node T_1743 = bits(T_1731, 0, 0) - node T_1745 = dshl(UInt<3>("h1"), T_1742) - node T_1746 = bits(T_1745, 2, 0) - node T_1747 = not(T_1746) - node T_1748 = and(T_1741, T_1747) - node T_1750 = mux(T_1743, UInt<1>("h0"), T_1746) - node T_1751 = or(T_1748, T_1750) - node T_1752 = cat(T_1742, T_1743) - T_1642 <= T_1751 - skip - node T_1753 = or(reset, io.dpath.invalidate) - when T_1753 : - T_1652[0] <= UInt<1>("h0") - T_1652[1] <= UInt<1>("h0") - T_1652[2] <= UInt<1>("h0") - skip - node T_1757 = bits(T_1682, 0, 0) - node T_1758 = bits(T_1682, 1, 1) - node T_1759 = bits(T_1682, 2, 2) - T_1664.T_1761.addr <= UInt<1>("h0") - T_1664.T_1761.en <= UInt<1>("h1") - T_1664.T_1763.addr <= UInt<1>("h1") - T_1664.T_1763.en <= UInt<1>("h1") - T_1664.T_1765.addr <= UInt<2>("h2") - T_1664.T_1765.en <= UInt<1>("h1") - node T_1767 = mux(T_1757, T_1664.T_1761.data, UInt<1>("h0")) - node T_1769 = mux(T_1758, T_1664.T_1763.data, UInt<1>("h0")) - node T_1771 = mux(T_1759, T_1664.T_1765.data, UInt<1>("h0")) - node T_1773 = or(T_1767, T_1769) - node T_1774 = or(T_1773, T_1771) - wire pte_cache_data : UInt<20> - pte_cache_data is invalid - pte_cache_data <= T_1774 - node T_1776 = bits(r_req.prv, 0, 0) - node T_1778 = geq(pte.typ, UInt<3>("h4")) - node T_1779 = and(pte.v, T_1778) - node T_1780 = bits(pte.typ, 1, 1) - node T_1781 = and(T_1779, T_1780) - node T_1783 = geq(pte.typ, UInt<2>("h2")) - node T_1784 = and(pte.v, T_1783) - node T_1785 = bits(pte.typ, 0, 0) - node T_1786 = and(T_1784, T_1785) - node T_1788 = geq(pte.typ, UInt<2>("h2")) - node T_1789 = and(pte.v, T_1788) - node T_1790 = mux(r_req.store, T_1786, T_1789) - node T_1791 = mux(r_req.fetch, T_1781, T_1790) - node T_1793 = geq(pte.typ, UInt<2>("h2")) - node T_1794 = and(pte.v, T_1793) - node T_1796 = lt(pte.typ, UInt<4>("h8")) - node T_1797 = and(T_1794, T_1796) - node T_1798 = bits(pte.typ, 1, 1) - node T_1799 = and(T_1797, T_1798) - node T_1801 = geq(pte.typ, UInt<2>("h2")) - node T_1802 = and(pte.v, T_1801) - node T_1804 = lt(pte.typ, UInt<4>("h8")) - node T_1805 = and(T_1802, T_1804) - node T_1806 = bits(pte.typ, 0, 0) - node T_1807 = and(T_1805, T_1806) - node T_1809 = geq(pte.typ, UInt<2>("h2")) - node T_1810 = and(pte.v, T_1809) - node T_1812 = lt(pte.typ, UInt<4>("h8")) - node T_1813 = and(T_1810, T_1812) - node T_1814 = mux(r_req.store, T_1807, T_1813) - node T_1815 = mux(r_req.fetch, T_1799, T_1814) - node perm_ok = mux(T_1776, T_1791, T_1815) - node T_1818 = eq(pte.r, UInt<1>("h0")) - node T_1820 = eq(pte.d, UInt<1>("h0")) - node T_1821 = and(r_req.store, T_1820) - node T_1822 = or(T_1818, T_1821) - node set_dirty_bit = and(perm_ok, T_1822) - node T_1824 = eq(state, UInt<2>("h2")) - node T_1825 = and(io.mem.resp.valid, T_1824) - node T_1827 = eq(set_dirty_bit, UInt<1>("h0")) - node T_1828 = and(T_1825, T_1827) - when T_1828 : - r_pte <- pte - skip - wire T_1844 : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - T_1844 is invalid - T_1844.v <= UInt<1>("h0") - T_1844.typ <= UInt<4>("h0") - T_1844.r <= UInt<1>("h0") - T_1844.d <= UInt<1>("h0") - T_1844.reserved_for_software <= UInt<3>("h0") - T_1844.ppn <= UInt<20>("h0") - wire pte_wdata : { ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte_wdata <- T_1844 - pte_wdata.r <= UInt<1>("h1") - pte_wdata.d <= r_req.store - node T_1865 = eq(state, UInt<1>("h1")) - node T_1866 = eq(state, UInt<2>("h3")) - node T_1867 = or(T_1865, T_1866) - io.mem.req.valid <= T_1867 - io.mem.req.bits.phys <= UInt<1>("h1") - node T_1869 = eq(state, UInt<2>("h3")) - node T_1870 = mux(T_1869, UInt<5>("ha"), UInt<5>("h0")) - io.mem.req.bits.cmd <= T_1870 - io.mem.req.bits.typ <= UInt<3>("h3") - io.mem.req.bits.addr <= pte_addr - io.mem.req.bits.kill <= UInt<1>("h0") - node T_1872 = cat(pte_wdata.reserved_for_software, pte_wdata.d) - node T_1873 = cat(pte_wdata.ppn, T_1872) - node T_1874 = cat(pte_wdata.typ, pte_wdata.v) - node T_1875 = cat(pte_wdata.r, T_1874) - node T_1876 = cat(T_1873, T_1875) - io.mem.req.bits.data <= T_1876 - node resp_err = eq(state, UInt<3>("h6")) - node T_1878 = eq(state, UInt<3>("h5")) - node resp_val = or(T_1878, resp_err) - node r_resp_ppn = shr(io.mem.req.bits.addr, 12) - node T_1881 = shr(r_resp_ppn, 18) - node T_1882 = bits(r_req.addr, 17, 0) - node T_1883 = cat(T_1881, T_1882) - node T_1884 = shr(r_resp_ppn, 9) - node T_1885 = bits(r_req.addr, 8, 0) - node T_1886 = cat(T_1884, T_1885) - wire T_1888 : UInt<28>[3] - T_1888[0] <= T_1883 - T_1888[1] <= T_1886 - T_1888[2] <= r_resp_ppn - node T_1895 = eq(r_req_dest, UInt<1>("h0")) - node T_1896 = and(resp_val, T_1895) - io.requestor[0].resp.valid <= T_1896 - io.requestor[0].resp.bits.error <= resp_err - io.requestor[0].resp.bits.pte <- r_pte - io.requestor[0].resp.bits.pte.ppn <= T_1888[count] - io.requestor[0].invalidate <= io.dpath.invalidate - io.requestor[0].status <- io.dpath.status - node T_1898 = eq(r_req_dest, UInt<1>("h1")) - node T_1899 = and(resp_val, T_1898) - io.requestor[1].resp.valid <= T_1899 - io.requestor[1].resp.bits.error <= resp_err - io.requestor[1].resp.bits.pte <- r_pte - io.requestor[1].resp.bits.pte.ppn <= T_1888[count] - io.requestor[1].invalidate <= io.dpath.invalidate - io.requestor[1].status <- io.dpath.status - node T_1900 = eq(UInt<1>("h0"), state) - when T_1900 : - when arb.io.out.valid : - state <= UInt<1>("h1") - skip - count <= UInt<1>("h0") - skip - node T_1902 = eq(UInt<1>("h1"), state) - when T_1902 : - node T_1904 = lt(count, UInt<2>("h2")) - node T_1905 = and(pte_cache_hit, T_1904) - when T_1905 : - io.mem.req.valid <= UInt<1>("h0") - state <= UInt<1>("h1") - node T_1908 = add(count, UInt<1>("h1")) - node T_1909 = tail(T_1908, 1) - count <= T_1909 - r_pte.ppn <= pte_cache_data - skip - node T_1911 = eq(T_1905, UInt<1>("h0")) - node T_1912 = and(T_1911, io.mem.req.ready) - when T_1912 : - state <= UInt<2>("h2") - skip - skip - node T_1913 = eq(UInt<2>("h2"), state) - when T_1913 : - when io.mem.resp.bits.nack : - state <= UInt<1>("h1") - skip - when io.mem.resp.valid : - state <= UInt<3>("h6") - node T_1915 = lt(pte.typ, UInt<2>("h2")) - node T_1916 = and(pte.v, T_1915) - node T_1918 = lt(count, UInt<2>("h2")) - node T_1919 = and(T_1916, T_1918) - when T_1919 : - state <= UInt<1>("h1") - node T_1921 = add(count, UInt<1>("h1")) - node T_1922 = tail(T_1921, 1) - count <= T_1922 - skip - node T_1924 = geq(pte.typ, UInt<2>("h2")) - node T_1925 = and(pte.v, T_1924) - when T_1925 : - node T_1926 = mux(set_dirty_bit, UInt<2>("h3"), UInt<3>("h5")) - state <= T_1926 - skip - skip - skip - node T_1927 = eq(UInt<2>("h3"), state) - when T_1927 : - when io.mem.req.ready : - state <= UInt<3>("h4") - skip - skip - node T_1928 = eq(UInt<3>("h4"), state) - when T_1928 : - when io.mem.resp.bits.nack : - state <= UInt<2>("h3") - skip - when io.mem.resp.valid : - state <= UInt<1>("h1") - skip - skip - node T_1929 = eq(UInt<3>("h5"), state) - when T_1929 : - state <= UInt<1>("h0") - skip - node T_1930 = eq(UInt<3>("h6"), state) - when T_1930 : - state <= UInt<1>("h0") - skip - module HellaCacheArbiter : - input clk : Clock - input reset : UInt<1> - output io : {flip requestor : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : { valid : UInt<1>, bits : UInt<9>}, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} - io is invalid - reg T_5286 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_5286) - T_5286 <= io.requestor[0].req.valid - reg T_5287 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_5287) - T_5287 <= io.requestor[1].req.valid - node T_5288 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) - io.mem.req.valid <= T_5288 - io.requestor[0].req.ready <= io.mem.req.ready - node T_5290 = eq(io.requestor[0].req.valid, UInt<1>("h0")) - node T_5291 = and(io.requestor[0].req.ready, T_5290) - io.requestor[1].req.ready <= T_5291 - io.mem.req.bits <- io.requestor[1].req.bits - node T_5293 = cat(io.requestor[1].req.bits.tag, UInt<1>("h1")) - io.mem.req.bits.tag <= T_5293 - when io.requestor[0].req.valid : - io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd - io.mem.req.bits.typ <= io.requestor[0].req.bits.typ - io.mem.req.bits.addr <= io.requestor[0].req.bits.addr - io.mem.req.bits.phys <= io.requestor[0].req.bits.phys - node T_5295 = cat(io.requestor[0].req.bits.tag, UInt<1>("h0")) - io.mem.req.bits.tag <= T_5295 - skip - when T_5286 : - io.mem.req.bits.kill <= io.requestor[0].req.bits.kill - io.mem.req.bits.data <= io.requestor[0].req.bits.data - skip - node T_5296 = bits(io.mem.resp.bits.tag, 0, 0) - node T_5298 = eq(T_5296, UInt<1>("h0")) - node T_5299 = and(io.mem.resp.valid, T_5298) - io.requestor[0].resp.valid <= T_5299 - io.requestor[0].xcpt <- io.mem.xcpt - io.requestor[0].ordered <= io.mem.ordered - io.requestor[0].resp.bits <- io.mem.resp.bits - node T_5300 = shr(io.mem.resp.bits.tag, 1) - io.requestor[0].resp.bits.tag <= T_5300 - node T_5301 = and(io.mem.resp.bits.nack, T_5298) - io.requestor[0].resp.bits.nack <= T_5301 - node T_5302 = and(io.mem.resp.bits.replay, T_5298) - io.requestor[0].resp.bits.replay <= T_5302 - node T_5303 = bits(io.mem.replay_next.bits, 0, 0) - node T_5305 = eq(T_5303, UInt<1>("h0")) - node T_5306 = and(io.mem.replay_next.valid, T_5305) - io.requestor[0].replay_next.valid <= T_5306 - node T_5307 = shr(io.mem.replay_next.bits, 1) - io.requestor[0].replay_next.bits <= T_5307 - node T_5308 = bits(io.mem.resp.bits.tag, 0, 0) - node T_5310 = eq(T_5308, UInt<1>("h1")) - node T_5311 = and(io.mem.resp.valid, T_5310) - io.requestor[1].resp.valid <= T_5311 - io.requestor[1].xcpt <- io.mem.xcpt - io.requestor[1].ordered <= io.mem.ordered - io.requestor[1].resp.bits <- io.mem.resp.bits - node T_5312 = shr(io.mem.resp.bits.tag, 1) - io.requestor[1].resp.bits.tag <= T_5312 - node T_5313 = and(io.mem.resp.bits.nack, T_5310) - io.requestor[1].resp.bits.nack <= T_5313 - node T_5314 = and(io.mem.resp.bits.replay, T_5310) - io.requestor[1].resp.bits.replay <= T_5314 - node T_5315 = bits(io.mem.replay_next.bits, 0, 0) - node T_5317 = eq(T_5315, UInt<1>("h1")) - node T_5318 = and(io.mem.replay_next.valid, T_5317) - io.requestor[1].replay_next.valid <= T_5318 - node T_5319 = shr(io.mem.replay_next.bits, 1) - io.requestor[1].replay_next.bits <= T_5319 - module FPUDecoder : - input clk : Clock - input reset : UInt<1> - output io : {flip inst : UInt<32>, sigs : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} - io is invalid - node T_42 = and(io.inst, UInt<32>("h4")) - node T_44 = eq(T_42, UInt<32>("h4")) - node T_46 = and(io.inst, UInt<32>("h8000010")) - node T_48 = eq(T_46, UInt<32>("h8000010")) - node T_50 = or(UInt<1>("h0"), T_44) - node T_51 = or(T_50, T_48) - node T_53 = and(io.inst, UInt<32>("h8")) - node T_55 = eq(T_53, UInt<32>("h8")) - node T_57 = and(io.inst, UInt<32>("h10000010")) - node T_59 = eq(T_57, UInt<32>("h10000010")) - node T_61 = or(UInt<1>("h0"), T_55) - node T_62 = or(T_61, T_59) - node T_64 = and(io.inst, UInt<32>("h40")) - node T_66 = eq(T_64, UInt<32>("h0")) - node T_68 = and(io.inst, UInt<32>("h20000000")) - node T_70 = eq(T_68, UInt<32>("h20000000")) - node T_72 = or(UInt<1>("h0"), T_66) - node T_73 = or(T_72, T_70) - node T_75 = and(io.inst, UInt<32>("h40000000")) - node T_77 = eq(T_75, UInt<32>("h40000000")) - node T_79 = or(UInt<1>("h0"), T_66) - node T_80 = or(T_79, T_77) - node T_82 = and(io.inst, UInt<32>("h10")) - node T_84 = eq(T_82, UInt<32>("h0")) - node T_86 = or(UInt<1>("h0"), T_84) - node T_87 = cat(T_62, T_51) - node T_88 = cat(T_73, T_87) - node T_89 = cat(T_80, T_88) - node T_90 = cat(T_86, T_89) - node T_92 = or(UInt<1>("h0"), T_66) - node T_94 = and(io.inst, UInt<32>("h80000020")) - node T_96 = eq(T_94, UInt<32>("h0")) - node T_98 = and(io.inst, UInt<32>("h30")) - node T_100 = eq(T_98, UInt<32>("h0")) - node T_102 = and(io.inst, UInt<32>("h10000020")) - node T_104 = eq(T_102, UInt<32>("h10000000")) - node T_106 = or(UInt<1>("h0"), T_96) - node T_107 = or(T_106, T_100) - node T_108 = or(T_107, T_104) - node T_110 = and(io.inst, UInt<32>("h80000004")) - node T_112 = eq(T_110, UInt<32>("h0")) - node T_114 = and(io.inst, UInt<32>("h10000004")) - node T_116 = eq(T_114, UInt<32>("h0")) - node T_118 = and(io.inst, UInt<32>("h50")) - node T_120 = eq(T_118, UInt<32>("h40")) - node T_122 = or(UInt<1>("h0"), T_112) - node T_123 = or(T_122, T_116) - node T_124 = or(T_123, T_120) - node T_126 = and(io.inst, UInt<32>("h40000004")) - node T_128 = eq(T_126, UInt<32>("h0")) - node T_130 = and(io.inst, UInt<32>("h20")) - node T_132 = eq(T_130, UInt<32>("h20")) - node T_134 = or(UInt<1>("h0"), T_128) - node T_135 = or(T_134, T_132) - node T_136 = or(T_135, T_120) - node T_138 = or(UInt<1>("h0"), T_120) - node T_140 = and(io.inst, UInt<32>("h50000010")) - node T_142 = eq(T_140, UInt<32>("h50000010")) - node T_144 = or(UInt<1>("h0"), T_66) - node T_145 = or(T_144, T_142) - node T_147 = and(io.inst, UInt<32>("h30000010")) - node T_149 = eq(T_147, UInt<32>("h10")) - node T_151 = or(UInt<1>("h0"), T_149) - node T_153 = and(io.inst, UInt<32>("h1040")) - node T_155 = eq(T_153, UInt<32>("h0")) - node T_157 = and(io.inst, UInt<32>("h2000040")) - node T_159 = eq(T_157, UInt<32>("h40")) - node T_161 = or(UInt<1>("h0"), T_155) - node T_162 = or(T_161, T_159) - node T_164 = and(io.inst, UInt<32>("h90000010")) - node T_166 = eq(T_164, UInt<32>("h90000010")) - node T_168 = or(UInt<1>("h0"), T_166) - node T_170 = and(io.inst, UInt<32>("h90000010")) - node T_172 = eq(T_170, UInt<32>("h80000010")) - node T_174 = or(UInt<1>("h0"), T_132) - node T_175 = or(T_174, T_172) - node T_177 = and(io.inst, UInt<32>("ha0000010")) - node T_179 = eq(T_177, UInt<32>("h20000010")) - node T_181 = and(io.inst, UInt<32>("hd0000010")) - node T_183 = eq(T_181, UInt<32>("h40000010")) - node T_185 = or(UInt<1>("h0"), T_179) - node T_186 = or(T_185, T_183) - node T_188 = and(io.inst, UInt<32>("h70000004")) - node T_190 = eq(T_188, UInt<32>("h0")) - node T_192 = and(io.inst, UInt<32>("h68000004")) - node T_194 = eq(T_192, UInt<32>("h0")) - node T_196 = or(UInt<1>("h0"), T_190) - node T_197 = or(T_196, T_194) - node T_198 = or(T_197, T_120) - node T_200 = and(io.inst, UInt<32>("h58000010")) - node T_202 = eq(T_200, UInt<32>("h18000010")) - node T_204 = or(UInt<1>("h0"), T_202) - node T_206 = and(io.inst, UInt<32>("hd0000010")) - node T_208 = eq(T_206, UInt<32>("h50000010")) - node T_210 = or(UInt<1>("h0"), T_208) - node T_212 = and(io.inst, UInt<32>("h20000004")) - node T_214 = eq(T_212, UInt<32>("h0")) - node T_216 = and(io.inst, UInt<32>("h40002000")) - node T_218 = eq(T_216, UInt<32>("h40000000")) - node T_220 = or(UInt<1>("h0"), T_214) - node T_221 = or(T_220, T_120) - node T_222 = or(T_221, T_218) - node T_224 = and(io.inst, UInt<32>("h8002000")) - node T_226 = eq(T_224, UInt<32>("h8000000")) - node T_228 = and(io.inst, UInt<32>("hc0000004")) - node T_230 = eq(T_228, UInt<32>("h80000000")) - node T_232 = or(UInt<1>("h0"), T_214) - node T_233 = or(T_232, T_120) - node T_234 = or(T_233, T_226) - node T_235 = or(T_234, T_230) - io.sigs.cmd <= T_90 - io.sigs.ldst <= T_92 - io.sigs.wen <= T_108 - io.sigs.ren1 <= T_124 - io.sigs.ren2 <= T_136 - io.sigs.ren3 <= T_138 - io.sigs.swap12 <= T_145 - io.sigs.swap23 <= T_151 - io.sigs.single <= T_162 - io.sigs.fromint <= T_168 - io.sigs.toint <= T_175 - io.sigs.fastpipe <= T_186 - io.sigs.fma <= T_198 - io.sigs.div <= T_204 - io.sigs.sqrt <= T_210 - io.sigs.round <= T_222 - io.sigs.wflags <= T_235 - module MulAddRecFN_preMul : - input clk : Clock - input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} - io is invalid - node signA = bits(io.a, 32, 32) - node expA = bits(io.a, 31, 23) - node fractA = bits(io.a, 22, 0) - node T_50 = bits(expA, 8, 6) - node isZeroA = eq(T_50, UInt<1>("h0")) - node T_54 = eq(isZeroA, UInt<1>("h0")) - node sigA = cat(T_54, fractA) - node signB = bits(io.b, 32, 32) - node expB = bits(io.b, 31, 23) - node fractB = bits(io.b, 22, 0) - node T_59 = bits(expB, 8, 6) - node isZeroB = eq(T_59, UInt<1>("h0")) - node T_63 = eq(isZeroB, UInt<1>("h0")) - node sigB = cat(T_63, fractB) - node T_65 = bits(io.c, 32, 32) - node T_66 = bits(io.op, 0, 0) - node opSignC = xor(T_65, T_66) - node expC = bits(io.c, 31, 23) - node fractC = bits(io.c, 22, 0) - node T_70 = bits(expC, 8, 6) - node isZeroC = eq(T_70, UInt<1>("h0")) - node T_74 = eq(isZeroC, UInt<1>("h0")) - node sigC = cat(T_74, fractC) - node T_76 = xor(signA, signB) - node T_77 = bits(io.op, 1, 1) - node signProd = xor(T_76, T_77) - node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bits(expB, 8, 8) - node T_82 = eq(T_80, UInt<1>("h0")) - node T_84 = sub(UInt<3>("h0"), T_82) - node T_85 = tail(T_84, 1) - node T_86 = bits(expB, 7, 0) - node T_87 = cat(T_85, T_86) - node T_88 = add(expA, T_87) - node T_89 = tail(T_88, 1) - node T_91 = add(T_89, UInt<5>("h1b")) - node sExpAlignedProd = tail(T_91, 1) - node doSubMags = xor(signProd, opSignC) - node T_94 = sub(sExpAlignedProd, expC) - node sNatCAlignDist = tail(T_94, 1) - node T_96 = bits(sNatCAlignDist, 10, 10) - node CAlignDist_floor = or(isZeroProd, T_96) - node T_98 = bits(sNatCAlignDist, 9, 0) - node T_100 = eq(T_98, UInt<1>("h0")) - node CAlignDist_0 = or(CAlignDist_floor, T_100) - node T_103 = eq(isZeroC, UInt<1>("h0")) - node T_104 = bits(sNatCAlignDist, 9, 0) - node T_106 = lt(T_104, UInt<5>("h19")) - node T_107 = or(CAlignDist_floor, T_106) - node isCDominant = and(T_103, T_107) - node T_110 = bits(sNatCAlignDist, 9, 0) - node T_112 = lt(T_110, UInt<7>("h4a")) - node T_113 = bits(sNatCAlignDist, 6, 0) - node T_115 = mux(T_112, T_113, UInt<7>("h4a")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h0"), T_115) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_119 = dshr(asSInt(UInt<129>("h100000000000000000000000000000000")), CAlignDist) - node T_120 = bits(T_119, 77, 54) - node T_121 = bits(T_120, 15, 0) - node T_124 = shl(UInt<8>("hff"), 8) - node T_125 = xor(UInt<16>("hffff"), T_124) - node T_126 = shr(T_121, 8) - node T_127 = and(T_126, T_125) - node T_128 = bits(T_121, 7, 0) - node T_129 = shl(T_128, 8) - node T_130 = not(T_125) - node T_131 = and(T_129, T_130) - node T_132 = or(T_127, T_131) - node T_133 = bits(T_125, 11, 0) - node T_134 = shl(T_133, 4) - node T_135 = xor(T_125, T_134) - node T_136 = shr(T_132, 4) - node T_137 = and(T_136, T_135) - node T_138 = bits(T_132, 11, 0) - node T_139 = shl(T_138, 4) - node T_140 = not(T_135) - node T_141 = and(T_139, T_140) - node T_142 = or(T_137, T_141) - node T_143 = bits(T_135, 13, 0) - node T_144 = shl(T_143, 2) - node T_145 = xor(T_135, T_144) - node T_146 = shr(T_142, 2) - node T_147 = and(T_146, T_145) - node T_148 = bits(T_142, 13, 0) - node T_149 = shl(T_148, 2) - node T_150 = not(T_145) - node T_151 = and(T_149, T_150) - node T_152 = or(T_147, T_151) - node T_153 = bits(T_145, 14, 0) - node T_154 = shl(T_153, 1) - node T_155 = xor(T_145, T_154) - node T_156 = shr(T_152, 1) - node T_157 = and(T_156, T_155) - node T_158 = bits(T_152, 14, 0) - node T_159 = shl(T_158, 1) - node T_160 = not(T_155) - node T_161 = and(T_159, T_160) - node T_162 = or(T_157, T_161) - node T_163 = bits(T_120, 23, 16) - node T_166 = shl(UInt<4>("hf"), 4) - node T_167 = xor(UInt<8>("hff"), T_166) - node T_168 = shr(T_163, 4) - node T_169 = and(T_168, T_167) - node T_170 = bits(T_163, 3, 0) - node T_171 = shl(T_170, 4) - node T_172 = not(T_167) - node T_173 = and(T_171, T_172) - node T_174 = or(T_169, T_173) - node T_175 = bits(T_167, 5, 0) - node T_176 = shl(T_175, 2) - node T_177 = xor(T_167, T_176) - node T_178 = shr(T_174, 2) - node T_179 = and(T_178, T_177) - node T_180 = bits(T_174, 5, 0) - node T_181 = shl(T_180, 2) - node T_182 = not(T_177) - node T_183 = and(T_181, T_182) - node T_184 = or(T_179, T_183) - node T_185 = bits(T_177, 6, 0) - node T_186 = shl(T_185, 1) - node T_187 = xor(T_177, T_186) - node T_188 = shr(T_184, 1) - node T_189 = and(T_188, T_187) - node T_190 = bits(T_184, 6, 0) - node T_191 = shl(T_190, 1) - node T_192 = not(T_187) - node T_193 = and(T_191, T_192) - node T_194 = or(T_189, T_193) - node CExtraMask = cat(T_162, T_194) - node T_196 = not(sigC) - node negSigC = mux(doSubMags, T_196, sigC) - node T_199 = sub(UInt<50>("h0"), doSubMags) - node T_200 = tail(T_199, 1) - node T_201 = cat(negSigC, T_200) - node T_202 = cat(doSubMags, T_201) - node T_203 = asSInt(T_202) - node T_204 = dshr(T_203, CAlignDist) - node T_205 = and(sigC, CExtraMask) - node T_207 = neq(T_205, UInt<1>("h0")) - node T_208 = xor(T_207, doSubMags) - node T_209 = asUInt(T_204) - node T_210 = cat(T_209, T_208) - node alignedNegSigC = bits(T_210, 74, 0) - io.mulAddA <= sigA - io.mulAddB <= sigB - node T_212 = bits(alignedNegSigC, 48, 1) - io.mulAddC <= T_212 - node T_213 = bits(expA, 8, 6) - io.toPostMul.highExpA <= T_213 - node T_214 = bits(fractA, 22, 22) - io.toPostMul.isNaN_isQuietNaNA <= T_214 - node T_215 = bits(expB, 8, 6) - io.toPostMul.highExpB <= T_215 - node T_216 = bits(fractB, 22, 22) - io.toPostMul.isNaN_isQuietNaNB <= T_216 - io.toPostMul.signProd <= signProd - io.toPostMul.isZeroProd <= isZeroProd - io.toPostMul.opSignC <= opSignC - node T_217 = bits(expC, 8, 6) - io.toPostMul.highExpC <= T_217 - node T_218 = bits(fractC, 22, 22) - io.toPostMul.isNaN_isQuietNaNC <= T_218 - io.toPostMul.isCDominant <= isCDominant - io.toPostMul.CAlignDist_0 <= CAlignDist_0 - io.toPostMul.CAlignDist <= CAlignDist - node T_219 = bits(alignedNegSigC, 0, 0) - io.toPostMul.bit0AlignedNegSigC <= T_219 - node T_220 = bits(alignedNegSigC, 74, 49) - io.toPostMul.highAlignedNegSigC <= T_220 - io.toPostMul.sExpSum <= sExpSum - io.toPostMul.roundingMode <= io.roundingMode - module MulAddRecFN_postMul : - input clk : Clock - input reset : UInt<1> - output io : {flip fromPreMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} - io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h0")) - node T_44 = bits(io.fromPreMul.highExpA, 2, 1) - node isSpecialA = eq(T_44, UInt<2>("h3")) - node T_47 = bits(io.fromPreMul.highExpA, 0, 0) - node T_49 = eq(T_47, UInt<1>("h0")) - node isInfA = and(isSpecialA, T_49) - node T_51 = bits(io.fromPreMul.highExpA, 0, 0) - node isNaNA = and(isSpecialA, T_51) - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h0")) - node isSigNaNA = and(isNaNA, T_54) - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h0")) - node T_58 = bits(io.fromPreMul.highExpB, 2, 1) - node isSpecialB = eq(T_58, UInt<2>("h3")) - node T_61 = bits(io.fromPreMul.highExpB, 0, 0) - node T_63 = eq(T_61, UInt<1>("h0")) - node isInfB = and(isSpecialB, T_63) - node T_65 = bits(io.fromPreMul.highExpB, 0, 0) - node isNaNB = and(isSpecialB, T_65) - node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h0")) - node isSigNaNB = and(isNaNB, T_68) - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h0")) - node T_72 = bits(io.fromPreMul.highExpC, 2, 1) - node isSpecialC = eq(T_72, UInt<2>("h3")) - node T_75 = bits(io.fromPreMul.highExpC, 0, 0) - node T_77 = eq(T_75, UInt<1>("h0")) - node isInfC = and(isSpecialC, T_77) - node T_79 = bits(io.fromPreMul.highExpC, 0, 0) - node isNaNC = and(isSpecialC, T_79) - node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h0")) - node isSigNaNC = and(isNaNC, T_82) - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h0")) - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h1")) - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h2")) - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h3")) - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h1"), UInt<1>("h0")) - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_96 = bits(io.mulAddResult, 48, 48) - node T_98 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h1")) - node T_99 = tail(T_98, 1) - node T_100 = mux(T_96, T_99, io.fromPreMul.highAlignedNegSigC) - node T_101 = bits(io.mulAddResult, 47, 0) - node T_102 = cat(T_101, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_100, T_102) - node T_105 = bits(sigSum, 50, 1) - node T_106 = xor(UInt<50>("h0"), T_105) - node T_107 = or(UInt<50>("h0"), T_105) - node T_108 = shl(T_107, 1) - node T_109 = xor(T_106, T_108) - node T_111 = bits(T_109, 49, 0) - node T_112 = bits(T_111, 49, 49) - node T_114 = bits(T_111, 48, 48) - node T_116 = bits(T_111, 47, 47) - node T_118 = bits(T_111, 46, 46) - node T_120 = bits(T_111, 45, 45) - node T_122 = bits(T_111, 44, 44) - node T_124 = bits(T_111, 43, 43) - node T_126 = bits(T_111, 42, 42) - node T_128 = bits(T_111, 41, 41) - node T_130 = bits(T_111, 40, 40) - node T_132 = bits(T_111, 39, 39) - node T_134 = bits(T_111, 38, 38) - node T_136 = bits(T_111, 37, 37) - node T_138 = bits(T_111, 36, 36) - node T_140 = bits(T_111, 35, 35) - node T_142 = bits(T_111, 34, 34) - node T_144 = bits(T_111, 33, 33) - node T_146 = bits(T_111, 32, 32) - node T_148 = bits(T_111, 31, 31) - node T_150 = bits(T_111, 30, 30) - node T_152 = bits(T_111, 29, 29) - node T_154 = bits(T_111, 28, 28) - node T_156 = bits(T_111, 27, 27) - node T_158 = bits(T_111, 26, 26) - node T_160 = bits(T_111, 25, 25) - node T_162 = bits(T_111, 24, 24) - node T_164 = bits(T_111, 23, 23) - node T_166 = bits(T_111, 22, 22) - node T_168 = bits(T_111, 21, 21) - node T_170 = bits(T_111, 20, 20) - node T_172 = bits(T_111, 19, 19) - node T_174 = bits(T_111, 18, 18) - node T_176 = bits(T_111, 17, 17) - node T_178 = bits(T_111, 16, 16) - node T_180 = bits(T_111, 15, 15) - node T_182 = bits(T_111, 14, 14) - node T_184 = bits(T_111, 13, 13) - node T_186 = bits(T_111, 12, 12) - node T_188 = bits(T_111, 11, 11) - node T_190 = bits(T_111, 10, 10) - node T_192 = bits(T_111, 9, 9) - node T_194 = bits(T_111, 8, 8) - node T_196 = bits(T_111, 7, 7) - node T_198 = bits(T_111, 6, 6) - node T_200 = bits(T_111, 5, 5) - node T_202 = bits(T_111, 4, 4) - node T_204 = bits(T_111, 3, 3) - node T_206 = bits(T_111, 2, 2) - node T_208 = bits(T_111, 1, 1) - node T_209 = shl(T_208, 0) - node T_210 = mux(T_206, UInt<2>("h2"), T_209) - node T_211 = mux(T_204, UInt<2>("h3"), T_210) - node T_212 = mux(T_202, UInt<3>("h4"), T_211) - node T_213 = mux(T_200, UInt<3>("h5"), T_212) - node T_214 = mux(T_198, UInt<3>("h6"), T_213) - node T_215 = mux(T_196, UInt<3>("h7"), T_214) - node T_216 = mux(T_194, UInt<4>("h8"), T_215) - node T_217 = mux(T_192, UInt<4>("h9"), T_216) - node T_218 = mux(T_190, UInt<4>("ha"), T_217) - node T_219 = mux(T_188, UInt<4>("hb"), T_218) - node T_220 = mux(T_186, UInt<4>("hc"), T_219) - node T_221 = mux(T_184, UInt<4>("hd"), T_220) - node T_222 = mux(T_182, UInt<4>("he"), T_221) - node T_223 = mux(T_180, UInt<4>("hf"), T_222) - node T_224 = mux(T_178, UInt<5>("h10"), T_223) - node T_225 = mux(T_176, UInt<5>("h11"), T_224) - node T_226 = mux(T_174, UInt<5>("h12"), T_225) - node T_227 = mux(T_172, UInt<5>("h13"), T_226) - node T_228 = mux(T_170, UInt<5>("h14"), T_227) - node T_229 = mux(T_168, UInt<5>("h15"), T_228) - node T_230 = mux(T_166, UInt<5>("h16"), T_229) - node T_231 = mux(T_164, UInt<5>("h17"), T_230) - node T_232 = mux(T_162, UInt<5>("h18"), T_231) - node T_233 = mux(T_160, UInt<5>("h19"), T_232) - node T_234 = mux(T_158, UInt<5>("h1a"), T_233) - node T_235 = mux(T_156, UInt<5>("h1b"), T_234) - node T_236 = mux(T_154, UInt<5>("h1c"), T_235) - node T_237 = mux(T_152, UInt<5>("h1d"), T_236) - node T_238 = mux(T_150, UInt<5>("h1e"), T_237) - node T_239 = mux(T_148, UInt<5>("h1f"), T_238) - node T_240 = mux(T_146, UInt<6>("h20"), T_239) - node T_241 = mux(T_144, UInt<6>("h21"), T_240) - node T_242 = mux(T_142, UInt<6>("h22"), T_241) - node T_243 = mux(T_140, UInt<6>("h23"), T_242) - node T_244 = mux(T_138, UInt<6>("h24"), T_243) - node T_245 = mux(T_136, UInt<6>("h25"), T_244) - node T_246 = mux(T_134, UInt<6>("h26"), T_245) - node T_247 = mux(T_132, UInt<6>("h27"), T_246) - node T_248 = mux(T_130, UInt<6>("h28"), T_247) - node T_249 = mux(T_128, UInt<6>("h29"), T_248) - node T_250 = mux(T_126, UInt<6>("h2a"), T_249) - node T_251 = mux(T_124, UInt<6>("h2b"), T_250) - node T_252 = mux(T_122, UInt<6>("h2c"), T_251) - node T_253 = mux(T_120, UInt<6>("h2d"), T_252) - node T_254 = mux(T_118, UInt<6>("h2e"), T_253) - node T_255 = mux(T_116, UInt<6>("h2f"), T_254) - node T_256 = mux(T_114, UInt<6>("h30"), T_255) - node T_257 = mux(T_112, UInt<6>("h31"), T_256) - node T_258 = sub(UInt<7>("h49"), T_257) - node estNormPos_dist = tail(T_258, 1) - node T_260 = bits(sigSum, 33, 18) - node T_262 = neq(T_260, UInt<1>("h0")) - node T_263 = bits(sigSum, 17, 0) - node T_265 = neq(T_263, UInt<1>("h0")) - node firstReduceSigSum = cat(T_262, T_265) - node notSigSum = not(sigSum) - node T_268 = bits(notSigSum, 33, 18) - node T_270 = neq(T_268, UInt<1>("h0")) - node T_271 = bits(notSigSum, 17, 0) - node T_273 = neq(T_271, UInt<1>("h0")) - node firstReduceNotSigSum = cat(T_270, T_273) - node T_275 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_277 = sub(io.fromPreMul.CAlignDist, UInt<1>("h1")) - node T_278 = tail(T_277, 1) - node T_279 = bits(T_278, 4, 0) - node CDom_estNormDist = mux(T_275, io.fromPreMul.CAlignDist, T_279) - node T_281 = not(doSubMags) - node T_282 = bits(CDom_estNormDist, 4, 4) - node T_283 = not(T_282) - node T_284 = and(T_281, T_283) - node T_285 = asSInt(T_284) - node T_286 = bits(sigSum, 74, 34) - node T_288 = neq(firstReduceSigSum, UInt<1>("h0")) - node T_289 = cat(T_286, T_288) - node T_290 = asSInt(T_289) - node T_291 = and(T_285, T_290) - node T_292 = asSInt(T_291) - node T_293 = not(doSubMags) - node T_294 = bits(CDom_estNormDist, 4, 4) - node T_295 = and(T_293, T_294) - node T_296 = asSInt(T_295) - node T_297 = bits(sigSum, 58, 18) - node T_298 = bits(firstReduceSigSum, 0, 0) - node T_299 = cat(T_297, T_298) - node T_300 = asSInt(T_299) - node T_301 = and(T_296, T_300) - node T_302 = asSInt(T_301) - node T_303 = or(T_292, T_302) - node T_304 = asSInt(T_303) - node T_305 = bits(CDom_estNormDist, 4, 4) - node T_306 = not(T_305) - node T_307 = and(doSubMags, T_306) - node T_308 = asSInt(T_307) - node T_309 = bits(notSigSum, 74, 34) - node T_311 = neq(firstReduceNotSigSum, UInt<1>("h0")) - node T_312 = cat(T_309, T_311) - node T_313 = asSInt(T_312) - node T_314 = and(T_308, T_313) - node T_315 = asSInt(T_314) - node T_316 = or(T_304, T_315) - node T_317 = asSInt(T_316) - node T_318 = bits(CDom_estNormDist, 4, 4) - node T_319 = and(doSubMags, T_318) - node T_320 = asSInt(T_319) - node T_321 = bits(notSigSum, 58, 18) - node T_322 = bits(firstReduceNotSigSum, 0, 0) - node T_323 = cat(T_321, T_322) - node T_324 = asSInt(T_323) - node T_325 = and(T_320, T_324) - node T_326 = asSInt(T_325) - node T_327 = or(T_317, T_326) - node T_328 = asSInt(T_327) - node CDom_firstNormAbsSigSum = asUInt(T_328) - node T_330 = bits(sigSum, 50, 18) - node T_331 = bits(firstReduceNotSigSum, 0, 0) - node T_332 = not(T_331) - node T_333 = bits(firstReduceSigSum, 0, 0) - node T_334 = mux(doSubMags, T_332, T_333) - node T_335 = cat(T_330, T_334) - node T_336 = bits(sigSum, 42, 1) - node T_337 = bits(estNormPos_dist, 5, 5) - node T_338 = bits(estNormPos_dist, 4, 4) - node T_339 = bits(sigSum, 26, 1) - node T_341 = sub(UInt<16>("h0"), doSubMags) - node T_342 = tail(T_341, 1) - node T_343 = cat(T_339, T_342) - node T_344 = mux(T_338, T_343, T_336) - node T_345 = bits(estNormPos_dist, 4, 4) - node T_346 = bits(sigSum, 10, 1) - node T_348 = sub(UInt<32>("h0"), doSubMags) - node T_349 = tail(T_348, 1) - node T_350 = cat(T_346, T_349) - node T_351 = mux(T_345, T_335, T_350) - node notCDom_pos_firstNormAbsSigSum = mux(T_337, T_344, T_351) - node T_353 = bits(notSigSum, 49, 18) - node T_354 = bits(firstReduceNotSigSum, 0, 0) - node T_355 = cat(T_353, T_354) - node T_356 = bits(notSigSum, 42, 1) - node T_357 = bits(estNormPos_dist, 5, 5) - node T_358 = bits(estNormPos_dist, 4, 4) - node T_359 = bits(notSigSum, 27, 1) - node T_361 = dshl(T_359, UInt<5>("h10")) - node T_362 = mux(T_358, T_361, T_356) - node T_363 = bits(estNormPos_dist, 4, 4) - node T_364 = bits(notSigSum, 11, 1) - node T_366 = dshl(T_364, UInt<6>("h20")) - node T_367 = mux(T_363, T_355, T_366) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_357, T_362, T_367) - node notCDom_signSigSum = bits(sigSum, 51, 51) - node T_370 = not(isZeroC) - node T_371 = and(doSubMags, T_370) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_371, notCDom_signSigSum) - node T_373 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_373) - node T_375 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_376 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_375, T_376) - node T_378 = not(io.fromPreMul.isCDominant) - node T_379 = not(notCDom_signSigSum) - node T_380 = and(T_378, T_379) - node doIncrSig = and(T_380, doSubMags) - node estNormDist_5 = bits(estNormDist, 3, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_385 = dshr(asSInt(UInt<17>("h10000")), normTo2ShiftDist) - node T_386 = bits(T_385, 15, 1) - node T_387 = bits(T_386, 7, 0) - node T_390 = shl(UInt<4>("hf"), 4) - node T_391 = xor(UInt<8>("hff"), T_390) - node T_392 = shr(T_387, 4) - node T_393 = and(T_392, T_391) - node T_394 = bits(T_387, 3, 0) - node T_395 = shl(T_394, 4) - node T_396 = not(T_391) - node T_397 = and(T_395, T_396) - node T_398 = or(T_393, T_397) - node T_399 = bits(T_391, 5, 0) - node T_400 = shl(T_399, 2) - node T_401 = xor(T_391, T_400) - node T_402 = shr(T_398, 2) - node T_403 = and(T_402, T_401) - node T_404 = bits(T_398, 5, 0) - node T_405 = shl(T_404, 2) - node T_406 = not(T_401) - node T_407 = and(T_405, T_406) - node T_408 = or(T_403, T_407) - node T_409 = bits(T_401, 6, 0) - node T_410 = shl(T_409, 1) - node T_411 = xor(T_401, T_410) - node T_412 = shr(T_408, 1) - node T_413 = and(T_412, T_411) - node T_414 = bits(T_408, 6, 0) - node T_415 = shl(T_414, 1) - node T_416 = not(T_411) - node T_417 = and(T_415, T_416) - node T_418 = or(T_413, T_417) - node T_419 = bits(T_386, 14, 8) - node T_420 = bits(T_419, 3, 0) - node T_421 = bits(T_420, 1, 0) - node T_422 = bits(T_421, 0, 0) - node T_423 = bits(T_421, 1, 1) - node T_424 = cat(T_422, T_423) - node T_425 = bits(T_420, 3, 2) - node T_426 = bits(T_425, 0, 0) - node T_427 = bits(T_425, 1, 1) - node T_428 = cat(T_426, T_427) - node T_429 = cat(T_424, T_428) - node T_430 = bits(T_419, 6, 4) - node T_431 = bits(T_430, 1, 0) - node T_432 = bits(T_431, 0, 0) - node T_433 = bits(T_431, 1, 1) - node T_434 = cat(T_432, T_433) - node T_435 = bits(T_430, 2, 2) - node T_436 = cat(T_434, T_435) - node T_437 = cat(T_429, T_436) - node T_438 = cat(T_418, T_437) - node absSigSumExtraMask = cat(T_438, UInt<1>("h1")) - node T_441 = bits(cFirstNormAbsSigSum, 42, 1) - node T_442 = dshr(T_441, normTo2ShiftDist) - node T_443 = bits(cFirstNormAbsSigSum, 15, 0) - node T_444 = not(T_443) - node T_445 = and(T_444, absSigSumExtraMask) - node T_447 = eq(T_445, UInt<1>("h0")) - node T_448 = bits(cFirstNormAbsSigSum, 15, 0) - node T_449 = and(T_448, absSigSumExtraMask) - node T_451 = neq(T_449, UInt<1>("h0")) - node T_452 = mux(doIncrSig, T_447, T_451) - node T_453 = cat(T_442, T_452) - node sigX3 = bits(T_453, 27, 0) - node T_455 = bits(sigX3, 27, 26) - node sigX3Shift1 = eq(T_455, UInt<1>("h0")) - node T_458 = sub(io.fromPreMul.sExpSum, estNormDist) - node sExpX3 = tail(T_458, 1) - node T_460 = bits(sigX3, 27, 25) - node isZeroY = eq(T_460, UInt<1>("h0")) - node T_463 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_463) - node sExpX3_13 = bits(sExpX3, 9, 0) - node T_466 = bits(sExpX3, 10, 10) - node T_468 = sub(UInt<27>("h0"), T_466) - node T_469 = tail(T_468, 1) - node T_470 = not(sExpX3_13) - node T_472 = dshr(asSInt(UInt<1025>("h10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_470) - node T_473 = bits(T_472, 131, 107) - node T_474 = bits(T_473, 15, 0) - node T_477 = shl(UInt<8>("hff"), 8) - node T_478 = xor(UInt<16>("hffff"), T_477) - node T_479 = shr(T_474, 8) - node T_480 = and(T_479, T_478) - node T_481 = bits(T_474, 7, 0) - node T_482 = shl(T_481, 8) - node T_483 = not(T_478) - node T_484 = and(T_482, T_483) - node T_485 = or(T_480, T_484) - node T_486 = bits(T_478, 11, 0) - node T_487 = shl(T_486, 4) - node T_488 = xor(T_478, T_487) - node T_489 = shr(T_485, 4) - node T_490 = and(T_489, T_488) - node T_491 = bits(T_485, 11, 0) - node T_492 = shl(T_491, 4) - node T_493 = not(T_488) - node T_494 = and(T_492, T_493) - node T_495 = or(T_490, T_494) - node T_496 = bits(T_488, 13, 0) - node T_497 = shl(T_496, 2) - node T_498 = xor(T_488, T_497) - node T_499 = shr(T_495, 2) - node T_500 = and(T_499, T_498) - node T_501 = bits(T_495, 13, 0) - node T_502 = shl(T_501, 2) - node T_503 = not(T_498) - node T_504 = and(T_502, T_503) - node T_505 = or(T_500, T_504) - node T_506 = bits(T_498, 14, 0) - node T_507 = shl(T_506, 1) - node T_508 = xor(T_498, T_507) - node T_509 = shr(T_505, 1) - node T_510 = and(T_509, T_508) - node T_511 = bits(T_505, 14, 0) - node T_512 = shl(T_511, 1) - node T_513 = not(T_508) - node T_514 = and(T_512, T_513) - node T_515 = or(T_510, T_514) - node T_516 = bits(T_473, 24, 16) - node T_517 = bits(T_516, 7, 0) - node T_520 = shl(UInt<4>("hf"), 4) - node T_521 = xor(UInt<8>("hff"), T_520) - node T_522 = shr(T_517, 4) - node T_523 = and(T_522, T_521) - node T_524 = bits(T_517, 3, 0) - node T_525 = shl(T_524, 4) - node T_526 = not(T_521) - node T_527 = and(T_525, T_526) - node T_528 = or(T_523, T_527) - node T_529 = bits(T_521, 5, 0) - node T_530 = shl(T_529, 2) - node T_531 = xor(T_521, T_530) - node T_532 = shr(T_528, 2) - node T_533 = and(T_532, T_531) - node T_534 = bits(T_528, 5, 0) - node T_535 = shl(T_534, 2) - node T_536 = not(T_531) - node T_537 = and(T_535, T_536) - node T_538 = or(T_533, T_537) - node T_539 = bits(T_531, 6, 0) - node T_540 = shl(T_539, 1) - node T_541 = xor(T_531, T_540) - node T_542 = shr(T_538, 1) - node T_543 = and(T_542, T_541) - node T_544 = bits(T_538, 6, 0) - node T_545 = shl(T_544, 1) - node T_546 = not(T_541) - node T_547 = and(T_545, T_546) - node T_548 = or(T_543, T_547) - node T_549 = bits(T_516, 8, 8) - node T_550 = cat(T_548, T_549) - node T_551 = cat(T_515, T_550) - node T_552 = bits(sigX3, 26, 26) - node T_553 = or(T_551, T_552) - node T_555 = cat(T_553, UInt<2>("h3")) - node roundMask = or(T_469, T_555) - node T_557 = shr(roundMask, 1) - node T_558 = not(T_557) - node roundPosMask = and(T_558, roundMask) - node T_560 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_560, UInt<1>("h0")) - node T_563 = shr(roundMask, 1) - node T_564 = and(sigX3, T_563) - node anyRoundExtra = neq(T_564, UInt<1>("h0")) - node T_567 = not(sigX3) - node T_568 = shr(roundMask, 1) - node T_569 = and(T_567, T_568) - node allRoundExtra = eq(T_569, UInt<1>("h0")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_575 = not(doIncrSig) - node T_576 = and(T_575, roundingMode_nearest_even) - node T_577 = and(T_576, roundPosBit) - node T_578 = and(T_577, anyRoundExtra) - node T_579 = not(doIncrSig) - node T_580 = and(T_579, roundDirectUp) - node T_581 = and(T_580, anyRound) - node T_582 = or(T_578, T_581) - node T_583 = and(doIncrSig, allRound) - node T_584 = or(T_582, T_583) - node T_585 = and(doIncrSig, roundingMode_nearest_even) - node T_586 = and(T_585, roundPosBit) - node T_587 = or(T_584, T_586) - node T_588 = and(doIncrSig, roundDirectUp) - node T_590 = and(T_588, UInt<1>("h1")) - node roundUp = or(T_587, T_590) - node T_592 = not(roundPosBit) - node T_593 = and(roundingMode_nearest_even, T_592) - node T_594 = and(T_593, allRoundExtra) - node T_595 = and(roundingMode_nearest_even, roundPosBit) - node T_596 = not(anyRoundExtra) - node T_597 = and(T_595, T_596) - node roundEven = mux(doIncrSig, T_594, T_597) - node T_599 = not(allRound) - node roundInexact = mux(doIncrSig, T_599, anyRound) - node T_601 = or(sigX3, roundMask) - node T_602 = shr(T_601, 2) - node T_604 = add(T_602, UInt<1>("h1")) - node T_605 = tail(T_604, 1) - node roundUp_sigY3 = bits(T_605, 25, 0) - node T_607 = not(roundUp) - node T_608 = not(roundEven) - node T_609 = and(T_607, T_608) - node T_610 = bits(T_609, 0, 0) - node T_611 = not(roundMask) - node T_612 = and(sigX3, T_611) - node T_613 = shr(T_612, 2) - node T_615 = mux(T_610, T_613, UInt<1>("h0")) - node T_616 = bits(roundUp, 0, 0) - node T_618 = mux(T_616, roundUp_sigY3, UInt<1>("h0")) - node T_619 = or(T_615, T_618) - node T_620 = shr(roundMask, 1) - node T_621 = not(T_620) - node T_622 = and(roundUp_sigY3, T_621) - node T_624 = mux(roundEven, T_622, UInt<1>("h0")) - node sigY3 = or(T_619, T_624) - node T_626 = bits(sigY3, 25, 25) - node T_628 = add(sExpX3, UInt<1>("h1")) - node T_629 = tail(T_628, 1) - node T_631 = mux(T_626, T_629, UInt<1>("h0")) - node T_632 = bits(sigY3, 24, 24) - node T_634 = mux(T_632, sExpX3, UInt<1>("h0")) - node T_635 = or(T_631, T_634) - node T_636 = bits(sigY3, 25, 24) - node T_638 = eq(T_636, UInt<1>("h0")) - node T_640 = sub(sExpX3, UInt<1>("h1")) - node T_641 = tail(T_640, 1) - node T_643 = mux(T_638, T_641, UInt<1>("h0")) - node sExpY = or(T_635, T_643) - node expY = bits(sExpY, 8, 0) - node T_646 = bits(sigY3, 22, 0) - node T_647 = bits(sigY3, 23, 1) - node fractY = mux(sigX3Shift1, T_646, T_647) - node T_649 = bits(sExpY, 9, 7) - node overflowY = eq(T_649, UInt<2>("h3")) - node T_652 = not(isZeroY) - node T_653 = bits(sExpY, 9, 9) - node T_654 = bits(sExpY, 8, 0) - node T_656 = lt(T_654, UInt<7>("h6b")) - node T_657 = or(T_653, T_656) - node totalUnderflowY = and(T_652, T_657) - node T_659 = bits(sExpX3, 10, 10) - node T_662 = mux(sigX3Shift1, UInt<8>("h82"), UInt<8>("h81")) - node T_663 = leq(sExpX3_13, T_662) - node T_664 = or(T_659, T_663) - node underflowY = and(roundInexact, T_664) - node T_666 = and(roundingMode_min, signY) - node T_667 = not(signY) - node T_668 = and(roundingMode_max, T_667) - node roundMagUp = or(T_666, T_668) - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_674 = not(addSpecial) - node T_675 = not(notSpecial_addZeros) - node commonCase = and(T_674, T_675) - node T_677 = and(isInfA, isZeroB) - node T_678 = and(isZeroA, isInfB) - node T_679 = or(T_677, T_678) - node T_680 = not(isNaNA) - node T_681 = not(isNaNB) - node T_682 = and(T_680, T_681) - node T_683 = or(isInfA, isInfB) - node T_684 = and(T_682, T_683) - node T_685 = and(T_684, isInfC) - node T_686 = and(T_685, doSubMags) - node notSigNaN_invalid = or(T_679, T_686) - node T_688 = or(isSigNaNA, isSigNaNB) - node T_689 = or(T_688, isSigNaNC) - node invalid = or(T_689, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_693 = and(commonCase, roundInexact) - node inexact = or(overflow, T_693) - node T_695 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_695, totalUnderflowY) - node T_697 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_697, roundMagUp) - node T_699 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_699) - node T_701 = or(isInfA, isInfB) - node T_702 = or(T_701, isInfC) - node T_703 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_702, T_703) - node T_705 = or(isNaNA, isNaNB) - node T_706 = or(T_705, isNaNC) - node isNaNOut = or(T_706, notSigNaN_invalid) - node T_709 = eq(doSubMags, UInt<1>("h0")) - node T_710 = and(T_709, io.fromPreMul.opSignC) - node T_712 = eq(isSpecialC, UInt<1>("h0")) - node T_713 = and(mulSpecial, T_712) - node T_714 = and(T_713, io.fromPreMul.signProd) - node T_715 = or(T_710, T_714) - node T_717 = eq(mulSpecial, UInt<1>("h0")) - node T_718 = and(T_717, isSpecialC) - node T_719 = and(T_718, io.fromPreMul.opSignC) - node T_720 = or(T_715, T_719) - node T_722 = eq(mulSpecial, UInt<1>("h0")) - node T_723 = and(T_722, notSpecial_addZeros) - node T_724 = and(T_723, doSubMags) - node T_725 = and(T_724, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_720, T_725) - node T_728 = eq(isNaNOut, UInt<1>("h0")) - node T_729 = and(T_728, uncommonCaseSignOut) - node T_730 = and(commonCase, signY) - node signOut = or(T_729, T_730) - node T_734 = mux(notSpecial_isZeroOut, UInt<9>("h1c0"), UInt<9>("h0")) - node T_735 = not(T_734) - node T_736 = and(expY, T_735) - node T_738 = not(UInt<9>("h6b")) - node T_740 = mux(pegMinFiniteMagOut, T_738, UInt<9>("h0")) - node T_741 = not(T_740) - node T_742 = and(T_736, T_741) - node T_745 = mux(pegMaxFiniteMagOut, UInt<9>("h80"), UInt<9>("h0")) - node T_746 = not(T_745) - node T_747 = and(T_742, T_746) - node T_750 = mux(notNaN_isInfOut, UInt<7>("h40"), UInt<9>("h0")) - node T_751 = not(T_750) - node T_752 = and(T_747, T_751) - node T_755 = mux(pegMinFiniteMagOut, UInt<7>("h6b"), UInt<9>("h0")) - node T_756 = or(T_752, T_755) - node T_759 = mux(pegMaxFiniteMagOut, UInt<9>("h17f"), UInt<9>("h0")) - node T_760 = or(T_756, T_759) - node T_763 = mux(notNaN_isInfOut, UInt<9>("h180"), UInt<9>("h0")) - node T_764 = or(T_760, T_763) - node T_767 = mux(isNaNOut, UInt<9>("h1c0"), UInt<9>("h0")) - node expOut = or(T_764, T_767) - node T_769 = and(totalUnderflowY, roundMagUp) - node T_770 = or(T_769, isNaNOut) - node T_772 = mux(T_770, UInt<1>("h0"), fractY) - node T_773 = shl(isNaNOut, 22) - node T_774 = or(T_772, T_773) - node T_776 = sub(UInt<23>("h0"), pegMaxFiniteMagOut) - node T_777 = tail(T_776, 1) - node fractOut = or(T_774, T_777) - node T_779 = cat(expOut, fractOut) - node T_780 = cat(signOut, T_779) - io.out <= T_780 - node T_782 = cat(invalid, UInt<1>("h0")) - node T_783 = cat(underflow, inexact) - node T_784 = cat(overflow, T_783) - node T_785 = cat(T_782, T_784) - io.exceptionFlags <= T_785 - module MulAddRecFN : - input clk : Clock - input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul - mulAddRecFN_preMul.io is invalid - mulAddRecFN_preMul.clk <= clk - mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul - mulAddRecFN_postMul.io is invalid - mulAddRecFN_postMul.clk <= clk - mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op - mulAddRecFN_preMul.io.a <= io.a - mulAddRecFN_preMul.io.b <= io.b - mulAddRecFN_preMul.io.c <= io.c - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_16 = cat(UInt<1>("h0"), mulAddRecFN_preMul.io.mulAddC) - node T_17 = add(T_14, T_16) - node T_18 = tail(T_17, 1) - mulAddRecFN_postMul.io.mulAddResult <= T_18 - io.out <= mulAddRecFN_postMul.io.out - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags - module FPUFMAPipe : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} - io is invalid - node one = shl(UInt<1>("h1"), 31) - node T_136 = bits(io.in.bits.in1, 32, 32) - node T_137 = bits(io.in.bits.in2, 32, 32) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 32) - reg valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), valid) - valid <= io.in.valid - reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : - reset => (UInt<1>("h0"), in) - when io.in.valid : - in <- io.in.bits - node T_187 = bits(io.in.bits.cmd, 1, 1) - node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bits(io.in.bits.cmd, 0, 0) - node T_191 = cat(T_189, T_190) - in.cmd <= T_191 - when io.in.bits.swap23 : - in.in2 <= one - skip - node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h0")) - when T_194 : - in.in3 <= zero - skip - skip - inst fma of MulAddRecFN - fma.io is invalid - fma.clk <= clk - fma.reset <= reset - fma.io.op <= in.cmd - fma.io.roundingMode <= in.rm - fma.io.a <= in.in1 - fma.io.b <= in.in2 - fma.io.c <= in.in3 - wire res : { data : UInt<65>, exc : UInt<5>} - res is invalid - node T_203 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_204 = cat(T_203, fma.io.out) - res.data <= T_204 - res.exc <= fma.io.exceptionFlags - reg T_207 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_207 <= valid - reg T_208 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_208) - when valid : - T_208 <- res - skip - wire T_219 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} - T_219 is invalid - T_219.valid <= T_207 - T_219.bits <- T_208 - io.out <- T_219 - module MulAddRecFN_preMul_115 : - input clk : Clock - input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} - io is invalid - node signA = bits(io.a, 64, 64) - node expA = bits(io.a, 63, 52) - node fractA = bits(io.a, 51, 0) - node T_50 = bits(expA, 11, 9) - node isZeroA = eq(T_50, UInt<1>("h0")) - node T_54 = eq(isZeroA, UInt<1>("h0")) - node sigA = cat(T_54, fractA) - node signB = bits(io.b, 64, 64) - node expB = bits(io.b, 63, 52) - node fractB = bits(io.b, 51, 0) - node T_59 = bits(expB, 11, 9) - node isZeroB = eq(T_59, UInt<1>("h0")) - node T_63 = eq(isZeroB, UInt<1>("h0")) - node sigB = cat(T_63, fractB) - node T_65 = bits(io.c, 64, 64) - node T_66 = bits(io.op, 0, 0) - node opSignC = xor(T_65, T_66) - node expC = bits(io.c, 63, 52) - node fractC = bits(io.c, 51, 0) - node T_70 = bits(expC, 11, 9) - node isZeroC = eq(T_70, UInt<1>("h0")) - node T_74 = eq(isZeroC, UInt<1>("h0")) - node sigC = cat(T_74, fractC) - node T_76 = xor(signA, signB) - node T_77 = bits(io.op, 1, 1) - node signProd = xor(T_76, T_77) - node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bits(expB, 11, 11) - node T_82 = eq(T_80, UInt<1>("h0")) - node T_84 = sub(UInt<3>("h0"), T_82) - node T_85 = tail(T_84, 1) - node T_86 = bits(expB, 10, 0) - node T_87 = cat(T_85, T_86) - node T_88 = add(expA, T_87) - node T_89 = tail(T_88, 1) - node T_91 = add(T_89, UInt<6>("h38")) - node sExpAlignedProd = tail(T_91, 1) - node doSubMags = xor(signProd, opSignC) - node T_94 = sub(sExpAlignedProd, expC) - node sNatCAlignDist = tail(T_94, 1) - node T_96 = bits(sNatCAlignDist, 13, 13) - node CAlignDist_floor = or(isZeroProd, T_96) - node T_98 = bits(sNatCAlignDist, 12, 0) - node T_100 = eq(T_98, UInt<1>("h0")) - node CAlignDist_0 = or(CAlignDist_floor, T_100) - node T_103 = eq(isZeroC, UInt<1>("h0")) - node T_104 = bits(sNatCAlignDist, 12, 0) - node T_106 = lt(T_104, UInt<6>("h36")) - node T_107 = or(CAlignDist_floor, T_106) - node isCDominant = and(T_103, T_107) - node T_110 = bits(sNatCAlignDist, 12, 0) - node T_112 = lt(T_110, UInt<8>("ha1")) - node T_113 = bits(sNatCAlignDist, 7, 0) - node T_115 = mux(T_112, T_113, UInt<8>("ha1")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h0"), T_115) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_119 = dshr(asSInt(UInt<257>("h10000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) - node T_120 = bits(T_119, 147, 95) - node T_121 = bits(T_120, 31, 0) - node T_124 = shl(UInt<16>("hffff"), 16) - node T_125 = xor(UInt<32>("hffffffff"), T_124) - node T_126 = shr(T_121, 16) - node T_127 = and(T_126, T_125) - node T_128 = bits(T_121, 15, 0) - node T_129 = shl(T_128, 16) - node T_130 = not(T_125) - node T_131 = and(T_129, T_130) - node T_132 = or(T_127, T_131) - node T_133 = bits(T_125, 23, 0) - node T_134 = shl(T_133, 8) - node T_135 = xor(T_125, T_134) - node T_136 = shr(T_132, 8) - node T_137 = and(T_136, T_135) - node T_138 = bits(T_132, 23, 0) - node T_139 = shl(T_138, 8) - node T_140 = not(T_135) - node T_141 = and(T_139, T_140) - node T_142 = or(T_137, T_141) - node T_143 = bits(T_135, 27, 0) - node T_144 = shl(T_143, 4) - node T_145 = xor(T_135, T_144) - node T_146 = shr(T_142, 4) - node T_147 = and(T_146, T_145) - node T_148 = bits(T_142, 27, 0) - node T_149 = shl(T_148, 4) - node T_150 = not(T_145) - node T_151 = and(T_149, T_150) - node T_152 = or(T_147, T_151) - node T_153 = bits(T_145, 29, 0) - node T_154 = shl(T_153, 2) - node T_155 = xor(T_145, T_154) - node T_156 = shr(T_152, 2) - node T_157 = and(T_156, T_155) - node T_158 = bits(T_152, 29, 0) - node T_159 = shl(T_158, 2) - node T_160 = not(T_155) - node T_161 = and(T_159, T_160) - node T_162 = or(T_157, T_161) - node T_163 = bits(T_155, 30, 0) - node T_164 = shl(T_163, 1) - node T_165 = xor(T_155, T_164) - node T_166 = shr(T_162, 1) - node T_167 = and(T_166, T_165) - node T_168 = bits(T_162, 30, 0) - node T_169 = shl(T_168, 1) - node T_170 = not(T_165) - node T_171 = and(T_169, T_170) - node T_172 = or(T_167, T_171) - node T_173 = bits(T_120, 52, 32) - node T_174 = bits(T_173, 15, 0) - node T_177 = shl(UInt<8>("hff"), 8) - node T_178 = xor(UInt<16>("hffff"), T_177) - node T_179 = shr(T_174, 8) - node T_180 = and(T_179, T_178) - node T_181 = bits(T_174, 7, 0) - node T_182 = shl(T_181, 8) - node T_183 = not(T_178) - node T_184 = and(T_182, T_183) - node T_185 = or(T_180, T_184) - node T_186 = bits(T_178, 11, 0) - node T_187 = shl(T_186, 4) - node T_188 = xor(T_178, T_187) - node T_189 = shr(T_185, 4) - node T_190 = and(T_189, T_188) - node T_191 = bits(T_185, 11, 0) - node T_192 = shl(T_191, 4) - node T_193 = not(T_188) - node T_194 = and(T_192, T_193) - node T_195 = or(T_190, T_194) - node T_196 = bits(T_188, 13, 0) - node T_197 = shl(T_196, 2) - node T_198 = xor(T_188, T_197) - node T_199 = shr(T_195, 2) - node T_200 = and(T_199, T_198) - node T_201 = bits(T_195, 13, 0) - node T_202 = shl(T_201, 2) - node T_203 = not(T_198) - node T_204 = and(T_202, T_203) - node T_205 = or(T_200, T_204) - node T_206 = bits(T_198, 14, 0) - node T_207 = shl(T_206, 1) - node T_208 = xor(T_198, T_207) - node T_209 = shr(T_205, 1) - node T_210 = and(T_209, T_208) - node T_211 = bits(T_205, 14, 0) - node T_212 = shl(T_211, 1) - node T_213 = not(T_208) - node T_214 = and(T_212, T_213) - node T_215 = or(T_210, T_214) - node T_216 = bits(T_173, 20, 16) - node T_217 = bits(T_216, 3, 0) - node T_218 = bits(T_217, 1, 0) - node T_219 = bits(T_218, 0, 0) - node T_220 = bits(T_218, 1, 1) - node T_221 = cat(T_219, T_220) - node T_222 = bits(T_217, 3, 2) - node T_223 = bits(T_222, 0, 0) - node T_224 = bits(T_222, 1, 1) - node T_225 = cat(T_223, T_224) - node T_226 = cat(T_221, T_225) - node T_227 = bits(T_216, 4, 4) - node T_228 = cat(T_226, T_227) - node T_229 = cat(T_215, T_228) - node CExtraMask = cat(T_172, T_229) - node T_231 = not(sigC) - node negSigC = mux(doSubMags, T_231, sigC) - node T_234 = sub(UInt<108>("h0"), doSubMags) - node T_235 = tail(T_234, 1) - node T_236 = cat(negSigC, T_235) - node T_237 = cat(doSubMags, T_236) - node T_238 = asSInt(T_237) - node T_239 = dshr(T_238, CAlignDist) - node T_240 = and(sigC, CExtraMask) - node T_242 = neq(T_240, UInt<1>("h0")) - node T_243 = xor(T_242, doSubMags) - node T_244 = asUInt(T_239) - node T_245 = cat(T_244, T_243) - node alignedNegSigC = bits(T_245, 161, 0) - io.mulAddA <= sigA - io.mulAddB <= sigB - node T_247 = bits(alignedNegSigC, 106, 1) - io.mulAddC <= T_247 - node T_248 = bits(expA, 11, 9) - io.toPostMul.highExpA <= T_248 - node T_249 = bits(fractA, 51, 51) - io.toPostMul.isNaN_isQuietNaNA <= T_249 - node T_250 = bits(expB, 11, 9) - io.toPostMul.highExpB <= T_250 - node T_251 = bits(fractB, 51, 51) - io.toPostMul.isNaN_isQuietNaNB <= T_251 - io.toPostMul.signProd <= signProd - io.toPostMul.isZeroProd <= isZeroProd - io.toPostMul.opSignC <= opSignC - node T_252 = bits(expC, 11, 9) - io.toPostMul.highExpC <= T_252 - node T_253 = bits(fractC, 51, 51) - io.toPostMul.isNaN_isQuietNaNC <= T_253 - io.toPostMul.isCDominant <= isCDominant - io.toPostMul.CAlignDist_0 <= CAlignDist_0 - io.toPostMul.CAlignDist <= CAlignDist - node T_254 = bits(alignedNegSigC, 0, 0) - io.toPostMul.bit0AlignedNegSigC <= T_254 - node T_255 = bits(alignedNegSigC, 161, 107) - io.toPostMul.highAlignedNegSigC <= T_255 - io.toPostMul.sExpSum <= sExpSum - io.toPostMul.roundingMode <= io.roundingMode - module MulAddRecFN_postMul_116 : - input clk : Clock - input reset : UInt<1> - output io : {flip fromPreMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} - io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h0")) - node T_44 = bits(io.fromPreMul.highExpA, 2, 1) - node isSpecialA = eq(T_44, UInt<2>("h3")) - node T_47 = bits(io.fromPreMul.highExpA, 0, 0) - node T_49 = eq(T_47, UInt<1>("h0")) - node isInfA = and(isSpecialA, T_49) - node T_51 = bits(io.fromPreMul.highExpA, 0, 0) - node isNaNA = and(isSpecialA, T_51) - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h0")) - node isSigNaNA = and(isNaNA, T_54) - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h0")) - node T_58 = bits(io.fromPreMul.highExpB, 2, 1) - node isSpecialB = eq(T_58, UInt<2>("h3")) - node T_61 = bits(io.fromPreMul.highExpB, 0, 0) - node T_63 = eq(T_61, UInt<1>("h0")) - node isInfB = and(isSpecialB, T_63) - node T_65 = bits(io.fromPreMul.highExpB, 0, 0) - node isNaNB = and(isSpecialB, T_65) - node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h0")) - node isSigNaNB = and(isNaNB, T_68) - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h0")) - node T_72 = bits(io.fromPreMul.highExpC, 2, 1) - node isSpecialC = eq(T_72, UInt<2>("h3")) - node T_75 = bits(io.fromPreMul.highExpC, 0, 0) - node T_77 = eq(T_75, UInt<1>("h0")) - node isInfC = and(isSpecialC, T_77) - node T_79 = bits(io.fromPreMul.highExpC, 0, 0) - node isNaNC = and(isSpecialC, T_79) - node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h0")) - node isSigNaNC = and(isNaNC, T_82) - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h0")) - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h1")) - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h2")) - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h3")) - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h1"), UInt<1>("h0")) - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_92 = bits(io.mulAddResult, 106, 106) - node T_94 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h1")) - node T_95 = tail(T_94, 1) - node T_96 = mux(T_92, T_95, io.fromPreMul.highAlignedNegSigC) - node T_97 = bits(io.mulAddResult, 105, 0) - node T_98 = cat(T_97, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_96, T_98) - node T_101 = bits(sigSum, 108, 1) - node T_102 = xor(UInt<108>("h0"), T_101) - node T_103 = or(UInt<108>("h0"), T_101) - node T_104 = shl(T_103, 1) - node T_105 = xor(T_102, T_104) - node T_107 = bits(T_105, 107, 0) - node T_108 = bits(T_107, 107, 107) - node T_110 = bits(T_107, 106, 106) - node T_112 = bits(T_107, 105, 105) - node T_114 = bits(T_107, 104, 104) - node T_116 = bits(T_107, 103, 103) - node T_118 = bits(T_107, 102, 102) - node T_120 = bits(T_107, 101, 101) - node T_122 = bits(T_107, 100, 100) - node T_124 = bits(T_107, 99, 99) - node T_126 = bits(T_107, 98, 98) - node T_128 = bits(T_107, 97, 97) - node T_130 = bits(T_107, 96, 96) - node T_132 = bits(T_107, 95, 95) - node T_134 = bits(T_107, 94, 94) - node T_136 = bits(T_107, 93, 93) - node T_138 = bits(T_107, 92, 92) - node T_140 = bits(T_107, 91, 91) - node T_142 = bits(T_107, 90, 90) - node T_144 = bits(T_107, 89, 89) - node T_146 = bits(T_107, 88, 88) - node T_148 = bits(T_107, 87, 87) - node T_150 = bits(T_107, 86, 86) - node T_152 = bits(T_107, 85, 85) - node T_154 = bits(T_107, 84, 84) - node T_156 = bits(T_107, 83, 83) - node T_158 = bits(T_107, 82, 82) - node T_160 = bits(T_107, 81, 81) - node T_162 = bits(T_107, 80, 80) - node T_164 = bits(T_107, 79, 79) - node T_166 = bits(T_107, 78, 78) - node T_168 = bits(T_107, 77, 77) - node T_170 = bits(T_107, 76, 76) - node T_172 = bits(T_107, 75, 75) - node T_174 = bits(T_107, 74, 74) - node T_176 = bits(T_107, 73, 73) - node T_178 = bits(T_107, 72, 72) - node T_180 = bits(T_107, 71, 71) - node T_182 = bits(T_107, 70, 70) - node T_184 = bits(T_107, 69, 69) - node T_186 = bits(T_107, 68, 68) - node T_188 = bits(T_107, 67, 67) - node T_190 = bits(T_107, 66, 66) - node T_192 = bits(T_107, 65, 65) - node T_194 = bits(T_107, 64, 64) - node T_196 = bits(T_107, 63, 63) - node T_198 = bits(T_107, 62, 62) - node T_200 = bits(T_107, 61, 61) - node T_202 = bits(T_107, 60, 60) - node T_204 = bits(T_107, 59, 59) - node T_206 = bits(T_107, 58, 58) - node T_208 = bits(T_107, 57, 57) - node T_210 = bits(T_107, 56, 56) - node T_212 = bits(T_107, 55, 55) - node T_214 = bits(T_107, 54, 54) - node T_216 = bits(T_107, 53, 53) - node T_218 = bits(T_107, 52, 52) - node T_220 = bits(T_107, 51, 51) - node T_222 = bits(T_107, 50, 50) - node T_224 = bits(T_107, 49, 49) - node T_226 = bits(T_107, 48, 48) - node T_228 = bits(T_107, 47, 47) - node T_230 = bits(T_107, 46, 46) - node T_232 = bits(T_107, 45, 45) - node T_234 = bits(T_107, 44, 44) - node T_236 = bits(T_107, 43, 43) - node T_238 = bits(T_107, 42, 42) - node T_240 = bits(T_107, 41, 41) - node T_242 = bits(T_107, 40, 40) - node T_244 = bits(T_107, 39, 39) - node T_246 = bits(T_107, 38, 38) - node T_248 = bits(T_107, 37, 37) - node T_250 = bits(T_107, 36, 36) - node T_252 = bits(T_107, 35, 35) - node T_254 = bits(T_107, 34, 34) - node T_256 = bits(T_107, 33, 33) - node T_258 = bits(T_107, 32, 32) - node T_260 = bits(T_107, 31, 31) - node T_262 = bits(T_107, 30, 30) - node T_264 = bits(T_107, 29, 29) - node T_266 = bits(T_107, 28, 28) - node T_268 = bits(T_107, 27, 27) - node T_270 = bits(T_107, 26, 26) - node T_272 = bits(T_107, 25, 25) - node T_274 = bits(T_107, 24, 24) - node T_276 = bits(T_107, 23, 23) - node T_278 = bits(T_107, 22, 22) - node T_280 = bits(T_107, 21, 21) - node T_282 = bits(T_107, 20, 20) - node T_284 = bits(T_107, 19, 19) - node T_286 = bits(T_107, 18, 18) - node T_288 = bits(T_107, 17, 17) - node T_290 = bits(T_107, 16, 16) - node T_292 = bits(T_107, 15, 15) - node T_294 = bits(T_107, 14, 14) - node T_296 = bits(T_107, 13, 13) - node T_298 = bits(T_107, 12, 12) - node T_300 = bits(T_107, 11, 11) - node T_302 = bits(T_107, 10, 10) - node T_304 = bits(T_107, 9, 9) - node T_306 = bits(T_107, 8, 8) - node T_308 = bits(T_107, 7, 7) - node T_310 = bits(T_107, 6, 6) - node T_312 = bits(T_107, 5, 5) - node T_314 = bits(T_107, 4, 4) - node T_316 = bits(T_107, 3, 3) - node T_318 = bits(T_107, 2, 2) - node T_320 = bits(T_107, 1, 1) - node T_321 = shl(T_320, 0) - node T_322 = mux(T_318, UInt<2>("h2"), T_321) - node T_323 = mux(T_316, UInt<2>("h3"), T_322) - node T_324 = mux(T_314, UInt<3>("h4"), T_323) - node T_325 = mux(T_312, UInt<3>("h5"), T_324) - node T_326 = mux(T_310, UInt<3>("h6"), T_325) - node T_327 = mux(T_308, UInt<3>("h7"), T_326) - node T_328 = mux(T_306, UInt<4>("h8"), T_327) - node T_329 = mux(T_304, UInt<4>("h9"), T_328) - node T_330 = mux(T_302, UInt<4>("ha"), T_329) - node T_331 = mux(T_300, UInt<4>("hb"), T_330) - node T_332 = mux(T_298, UInt<4>("hc"), T_331) - node T_333 = mux(T_296, UInt<4>("hd"), T_332) - node T_334 = mux(T_294, UInt<4>("he"), T_333) - node T_335 = mux(T_292, UInt<4>("hf"), T_334) - node T_336 = mux(T_290, UInt<5>("h10"), T_335) - node T_337 = mux(T_288, UInt<5>("h11"), T_336) - node T_338 = mux(T_286, UInt<5>("h12"), T_337) - node T_339 = mux(T_284, UInt<5>("h13"), T_338) - node T_340 = mux(T_282, UInt<5>("h14"), T_339) - node T_341 = mux(T_280, UInt<5>("h15"), T_340) - node T_342 = mux(T_278, UInt<5>("h16"), T_341) - node T_343 = mux(T_276, UInt<5>("h17"), T_342) - node T_344 = mux(T_274, UInt<5>("h18"), T_343) - node T_345 = mux(T_272, UInt<5>("h19"), T_344) - node T_346 = mux(T_270, UInt<5>("h1a"), T_345) - node T_347 = mux(T_268, UInt<5>("h1b"), T_346) - node T_348 = mux(T_266, UInt<5>("h1c"), T_347) - node T_349 = mux(T_264, UInt<5>("h1d"), T_348) - node T_350 = mux(T_262, UInt<5>("h1e"), T_349) - node T_351 = mux(T_260, UInt<5>("h1f"), T_350) - node T_352 = mux(T_258, UInt<6>("h20"), T_351) - node T_353 = mux(T_256, UInt<6>("h21"), T_352) - node T_354 = mux(T_254, UInt<6>("h22"), T_353) - node T_355 = mux(T_252, UInt<6>("h23"), T_354) - node T_356 = mux(T_250, UInt<6>("h24"), T_355) - node T_357 = mux(T_248, UInt<6>("h25"), T_356) - node T_358 = mux(T_246, UInt<6>("h26"), T_357) - node T_359 = mux(T_244, UInt<6>("h27"), T_358) - node T_360 = mux(T_242, UInt<6>("h28"), T_359) - node T_361 = mux(T_240, UInt<6>("h29"), T_360) - node T_362 = mux(T_238, UInt<6>("h2a"), T_361) - node T_363 = mux(T_236, UInt<6>("h2b"), T_362) - node T_364 = mux(T_234, UInt<6>("h2c"), T_363) - node T_365 = mux(T_232, UInt<6>("h2d"), T_364) - node T_366 = mux(T_230, UInt<6>("h2e"), T_365) - node T_367 = mux(T_228, UInt<6>("h2f"), T_366) - node T_368 = mux(T_226, UInt<6>("h30"), T_367) - node T_369 = mux(T_224, UInt<6>("h31"), T_368) - node T_370 = mux(T_222, UInt<6>("h32"), T_369) - node T_371 = mux(T_220, UInt<6>("h33"), T_370) - node T_372 = mux(T_218, UInt<6>("h34"), T_371) - node T_373 = mux(T_216, UInt<6>("h35"), T_372) - node T_374 = mux(T_214, UInt<6>("h36"), T_373) - node T_375 = mux(T_212, UInt<6>("h37"), T_374) - node T_376 = mux(T_210, UInt<6>("h38"), T_375) - node T_377 = mux(T_208, UInt<6>("h39"), T_376) - node T_378 = mux(T_206, UInt<6>("h3a"), T_377) - node T_379 = mux(T_204, UInt<6>("h3b"), T_378) - node T_380 = mux(T_202, UInt<6>("h3c"), T_379) - node T_381 = mux(T_200, UInt<6>("h3d"), T_380) - node T_382 = mux(T_198, UInt<6>("h3e"), T_381) - node T_383 = mux(T_196, UInt<6>("h3f"), T_382) - node T_384 = mux(T_194, UInt<7>("h40"), T_383) - node T_385 = mux(T_192, UInt<7>("h41"), T_384) - node T_386 = mux(T_190, UInt<7>("h42"), T_385) - node T_387 = mux(T_188, UInt<7>("h43"), T_386) - node T_388 = mux(T_186, UInt<7>("h44"), T_387) - node T_389 = mux(T_184, UInt<7>("h45"), T_388) - node T_390 = mux(T_182, UInt<7>("h46"), T_389) - node T_391 = mux(T_180, UInt<7>("h47"), T_390) - node T_392 = mux(T_178, UInt<7>("h48"), T_391) - node T_393 = mux(T_176, UInt<7>("h49"), T_392) - node T_394 = mux(T_174, UInt<7>("h4a"), T_393) - node T_395 = mux(T_172, UInt<7>("h4b"), T_394) - node T_396 = mux(T_170, UInt<7>("h4c"), T_395) - node T_397 = mux(T_168, UInt<7>("h4d"), T_396) - node T_398 = mux(T_166, UInt<7>("h4e"), T_397) - node T_399 = mux(T_164, UInt<7>("h4f"), T_398) - node T_400 = mux(T_162, UInt<7>("h50"), T_399) - node T_401 = mux(T_160, UInt<7>("h51"), T_400) - node T_402 = mux(T_158, UInt<7>("h52"), T_401) - node T_403 = mux(T_156, UInt<7>("h53"), T_402) - node T_404 = mux(T_154, UInt<7>("h54"), T_403) - node T_405 = mux(T_152, UInt<7>("h55"), T_404) - node T_406 = mux(T_150, UInt<7>("h56"), T_405) - node T_407 = mux(T_148, UInt<7>("h57"), T_406) - node T_408 = mux(T_146, UInt<7>("h58"), T_407) - node T_409 = mux(T_144, UInt<7>("h59"), T_408) - node T_410 = mux(T_142, UInt<7>("h5a"), T_409) - node T_411 = mux(T_140, UInt<7>("h5b"), T_410) - node T_412 = mux(T_138, UInt<7>("h5c"), T_411) - node T_413 = mux(T_136, UInt<7>("h5d"), T_412) - node T_414 = mux(T_134, UInt<7>("h5e"), T_413) - node T_415 = mux(T_132, UInt<7>("h5f"), T_414) - node T_416 = mux(T_130, UInt<7>("h60"), T_415) - node T_417 = mux(T_128, UInt<7>("h61"), T_416) - node T_418 = mux(T_126, UInt<7>("h62"), T_417) - node T_419 = mux(T_124, UInt<7>("h63"), T_418) - node T_420 = mux(T_122, UInt<7>("h64"), T_419) - node T_421 = mux(T_120, UInt<7>("h65"), T_420) - node T_422 = mux(T_118, UInt<7>("h66"), T_421) - node T_423 = mux(T_116, UInt<7>("h67"), T_422) - node T_424 = mux(T_114, UInt<7>("h68"), T_423) - node T_425 = mux(T_112, UInt<7>("h69"), T_424) - node T_426 = mux(T_110, UInt<7>("h6a"), T_425) - node T_427 = mux(T_108, UInt<7>("h6b"), T_426) - node T_428 = sub(UInt<8>("ha0"), T_427) - node estNormPos_dist = tail(T_428, 1) - node T_430 = bits(sigSum, 75, 44) - node T_432 = neq(T_430, UInt<1>("h0")) - node T_433 = bits(sigSum, 43, 0) - node T_435 = neq(T_433, UInt<1>("h0")) - node firstReduceSigSum = cat(T_432, T_435) - node notSigSum = not(sigSum) - node T_438 = bits(notSigSum, 75, 44) - node T_440 = neq(T_438, UInt<1>("h0")) - node T_441 = bits(notSigSum, 43, 0) - node T_443 = neq(T_441, UInt<1>("h0")) - node firstReduceNotSigSum = cat(T_440, T_443) - node T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h1")) - node T_448 = tail(T_447, 1) - node T_449 = bits(T_448, 5, 0) - node CDom_estNormDist = mux(T_445, io.fromPreMul.CAlignDist, T_449) - node T_451 = not(doSubMags) - node T_452 = bits(CDom_estNormDist, 5, 5) - node T_453 = not(T_452) - node T_454 = and(T_451, T_453) - node T_455 = asSInt(T_454) - node T_456 = bits(sigSum, 161, 76) - node T_458 = neq(firstReduceSigSum, UInt<1>("h0")) - node T_459 = cat(T_456, T_458) - node T_460 = asSInt(T_459) - node T_461 = and(T_455, T_460) - node T_462 = asSInt(T_461) - node T_463 = not(doSubMags) - node T_464 = bits(CDom_estNormDist, 5, 5) - node T_465 = and(T_463, T_464) - node T_466 = asSInt(T_465) - node T_467 = bits(sigSum, 129, 44) - node T_468 = bits(firstReduceSigSum, 0, 0) - node T_469 = cat(T_467, T_468) - node T_470 = asSInt(T_469) - node T_471 = and(T_466, T_470) - node T_472 = asSInt(T_471) - node T_473 = or(T_462, T_472) - node T_474 = asSInt(T_473) - node T_475 = bits(CDom_estNormDist, 5, 5) - node T_476 = not(T_475) - node T_477 = and(doSubMags, T_476) - node T_478 = asSInt(T_477) - node T_479 = bits(notSigSum, 161, 76) - node T_481 = neq(firstReduceNotSigSum, UInt<1>("h0")) - node T_482 = cat(T_479, T_481) - node T_483 = asSInt(T_482) - node T_484 = and(T_478, T_483) - node T_485 = asSInt(T_484) - node T_486 = or(T_474, T_485) - node T_487 = asSInt(T_486) - node T_488 = bits(CDom_estNormDist, 5, 5) - node T_489 = and(doSubMags, T_488) - node T_490 = asSInt(T_489) - node T_491 = bits(notSigSum, 129, 44) - node T_492 = bits(firstReduceNotSigSum, 0, 0) - node T_493 = cat(T_491, T_492) - node T_494 = asSInt(T_493) - node T_495 = and(T_490, T_494) - node T_496 = asSInt(T_495) - node T_497 = or(T_487, T_496) - node T_498 = asSInt(T_497) - node CDom_firstNormAbsSigSum = asUInt(T_498) - node T_500 = bits(sigSum, 108, 44) - node T_501 = bits(firstReduceNotSigSum, 0, 0) - node T_502 = not(T_501) - node T_503 = bits(firstReduceSigSum, 0, 0) - node T_504 = mux(doSubMags, T_502, T_503) - node T_505 = cat(T_500, T_504) - node T_506 = bits(sigSum, 97, 1) - node T_507 = bits(estNormPos_dist, 4, 4) - node T_508 = bits(sigSum, 1, 1) - node T_510 = sub(UInt<86>("h0"), doSubMags) - node T_511 = tail(T_510, 1) - node T_512 = cat(T_508, T_511) - node T_513 = mux(T_507, T_505, T_512) - node T_514 = bits(sigSum, 97, 12) - node T_515 = bits(notSigSum, 11, 1) - node T_517 = eq(T_515, UInt<1>("h0")) - node T_518 = bits(sigSum, 11, 1) - node T_520 = neq(T_518, UInt<1>("h0")) - node T_521 = mux(doSubMags, T_517, T_520) - node T_522 = cat(T_514, T_521) - node T_523 = bits(estNormPos_dist, 6, 6) - node T_524 = bits(estNormPos_dist, 5, 5) - node T_525 = bits(sigSum, 65, 1) - node T_527 = sub(UInt<22>("h0"), doSubMags) - node T_528 = tail(T_527, 1) - node T_529 = cat(T_525, T_528) - node T_530 = mux(T_524, T_529, T_522) - node T_531 = bits(estNormPos_dist, 5, 5) - node T_532 = bits(sigSum, 33, 1) - node T_534 = sub(UInt<54>("h0"), doSubMags) - node T_535 = tail(T_534, 1) - node T_536 = cat(T_532, T_535) - node T_537 = mux(T_531, T_513, T_536) - node notCDom_pos_firstNormAbsSigSum = mux(T_523, T_530, T_537) - node T_539 = bits(notSigSum, 107, 44) - node T_540 = bits(firstReduceNotSigSum, 0, 0) - node T_541 = cat(T_539, T_540) - node T_542 = bits(notSigSum, 97, 1) - node T_543 = bits(estNormPos_dist, 4, 4) - node T_544 = bits(notSigSum, 2, 1) - node T_546 = dshl(T_544, UInt<7>("h56")) - node T_547 = mux(T_543, T_541, T_546) - node T_548 = bits(notSigSum, 98, 12) - node T_549 = bits(notSigSum, 11, 1) - node T_551 = neq(T_549, UInt<1>("h0")) - node T_552 = cat(T_548, T_551) - node T_553 = bits(estNormPos_dist, 6, 6) - node T_554 = bits(estNormPos_dist, 5, 5) - node T_555 = bits(notSigSum, 66, 1) - node T_557 = dshl(T_555, UInt<5>("h16")) - node T_558 = mux(T_554, T_557, T_552) - node T_559 = bits(estNormPos_dist, 5, 5) - node T_560 = bits(notSigSum, 34, 1) - node T_562 = dshl(T_560, UInt<6>("h36")) - node T_563 = mux(T_559, T_547, T_562) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_553, T_558, T_563) - node notCDom_signSigSum = bits(sigSum, 109, 109) - node T_566 = not(isZeroC) - node T_567 = and(doSubMags, T_566) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_567, notCDom_signSigSum) - node T_569 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_569) - node T_571 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_572 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_571, T_572) - node T_574 = not(io.fromPreMul.isCDominant) - node T_575 = not(notCDom_signSigSum) - node T_576 = and(T_574, T_575) - node doIncrSig = and(T_576, doSubMags) - node estNormDist_5 = bits(estNormDist, 4, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_581 = dshr(asSInt(UInt<33>("h100000000")), normTo2ShiftDist) - node T_582 = bits(T_581, 31, 1) - node T_583 = bits(T_582, 15, 0) - node T_586 = shl(UInt<8>("hff"), 8) - node T_587 = xor(UInt<16>("hffff"), T_586) - node T_588 = shr(T_583, 8) - node T_589 = and(T_588, T_587) - node T_590 = bits(T_583, 7, 0) - node T_591 = shl(T_590, 8) - node T_592 = not(T_587) - node T_593 = and(T_591, T_592) - node T_594 = or(T_589, T_593) - node T_595 = bits(T_587, 11, 0) - node T_596 = shl(T_595, 4) - node T_597 = xor(T_587, T_596) - node T_598 = shr(T_594, 4) - node T_599 = and(T_598, T_597) - node T_600 = bits(T_594, 11, 0) - node T_601 = shl(T_600, 4) - node T_602 = not(T_597) - node T_603 = and(T_601, T_602) - node T_604 = or(T_599, T_603) - node T_605 = bits(T_597, 13, 0) - node T_606 = shl(T_605, 2) - node T_607 = xor(T_597, T_606) - node T_608 = shr(T_604, 2) - node T_609 = and(T_608, T_607) - node T_610 = bits(T_604, 13, 0) - node T_611 = shl(T_610, 2) - node T_612 = not(T_607) - node T_613 = and(T_611, T_612) - node T_614 = or(T_609, T_613) - node T_615 = bits(T_607, 14, 0) - node T_616 = shl(T_615, 1) - node T_617 = xor(T_607, T_616) - node T_618 = shr(T_614, 1) - node T_619 = and(T_618, T_617) - node T_620 = bits(T_614, 14, 0) - node T_621 = shl(T_620, 1) - node T_622 = not(T_617) - node T_623 = and(T_621, T_622) - node T_624 = or(T_619, T_623) - node T_625 = bits(T_582, 30, 16) - node T_626 = bits(T_625, 7, 0) - node T_629 = shl(UInt<4>("hf"), 4) - node T_630 = xor(UInt<8>("hff"), T_629) - node T_631 = shr(T_626, 4) - node T_632 = and(T_631, T_630) - node T_633 = bits(T_626, 3, 0) - node T_634 = shl(T_633, 4) - node T_635 = not(T_630) - node T_636 = and(T_634, T_635) - node T_637 = or(T_632, T_636) - node T_638 = bits(T_630, 5, 0) - node T_639 = shl(T_638, 2) - node T_640 = xor(T_630, T_639) - node T_641 = shr(T_637, 2) - node T_642 = and(T_641, T_640) - node T_643 = bits(T_637, 5, 0) - node T_644 = shl(T_643, 2) - node T_645 = not(T_640) - node T_646 = and(T_644, T_645) - node T_647 = or(T_642, T_646) - node T_648 = bits(T_640, 6, 0) - node T_649 = shl(T_648, 1) - node T_650 = xor(T_640, T_649) - node T_651 = shr(T_647, 1) - node T_652 = and(T_651, T_650) - node T_653 = bits(T_647, 6, 0) - node T_654 = shl(T_653, 1) - node T_655 = not(T_650) - node T_656 = and(T_654, T_655) - node T_657 = or(T_652, T_656) - node T_658 = bits(T_625, 14, 8) - node T_659 = bits(T_658, 3, 0) - node T_660 = bits(T_659, 1, 0) - node T_661 = bits(T_660, 0, 0) - node T_662 = bits(T_660, 1, 1) - node T_663 = cat(T_661, T_662) - node T_664 = bits(T_659, 3, 2) - node T_665 = bits(T_664, 0, 0) - node T_666 = bits(T_664, 1, 1) - node T_667 = cat(T_665, T_666) - node T_668 = cat(T_663, T_667) - node T_669 = bits(T_658, 6, 4) - node T_670 = bits(T_669, 1, 0) - node T_671 = bits(T_670, 0, 0) - node T_672 = bits(T_670, 1, 1) - node T_673 = cat(T_671, T_672) - node T_674 = bits(T_669, 2, 2) - node T_675 = cat(T_673, T_674) - node T_676 = cat(T_668, T_675) - node T_677 = cat(T_657, T_676) - node T_678 = cat(T_624, T_677) - node absSigSumExtraMask = cat(T_678, UInt<1>("h1")) - node T_681 = bits(cFirstNormAbsSigSum, 87, 1) - node T_682 = dshr(T_681, normTo2ShiftDist) - node T_683 = bits(cFirstNormAbsSigSum, 31, 0) - node T_684 = not(T_683) - node T_685 = and(T_684, absSigSumExtraMask) - node T_687 = eq(T_685, UInt<1>("h0")) - node T_688 = bits(cFirstNormAbsSigSum, 31, 0) - node T_689 = and(T_688, absSigSumExtraMask) - node T_691 = neq(T_689, UInt<1>("h0")) - node T_692 = mux(doIncrSig, T_687, T_691) - node T_693 = cat(T_682, T_692) - node sigX3 = bits(T_693, 56, 0) - node T_695 = bits(sigX3, 56, 55) - node sigX3Shift1 = eq(T_695, UInt<1>("h0")) - node T_698 = sub(io.fromPreMul.sExpSum, estNormDist) - node sExpX3 = tail(T_698, 1) - node T_700 = bits(sigX3, 56, 54) - node isZeroY = eq(T_700, UInt<1>("h0")) - node T_703 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_703) - node sExpX3_13 = bits(sExpX3, 12, 0) - node T_706 = bits(sExpX3, 13, 13) - node T_708 = sub(UInt<56>("h0"), T_706) - node T_709 = tail(T_708, 1) - node T_710 = not(sExpX3_13) - node T_712 = dshr(asSInt(UInt<8193>("h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_710) - node T_713 = bits(T_712, 1027, 974) - node T_714 = bits(T_713, 31, 0) - node T_717 = shl(UInt<16>("hffff"), 16) - node T_718 = xor(UInt<32>("hffffffff"), T_717) - node T_719 = shr(T_714, 16) - node T_720 = and(T_719, T_718) - node T_721 = bits(T_714, 15, 0) - node T_722 = shl(T_721, 16) - node T_723 = not(T_718) - node T_724 = and(T_722, T_723) - node T_725 = or(T_720, T_724) - node T_726 = bits(T_718, 23, 0) - node T_727 = shl(T_726, 8) - node T_728 = xor(T_718, T_727) - node T_729 = shr(T_725, 8) - node T_730 = and(T_729, T_728) - node T_731 = bits(T_725, 23, 0) - node T_732 = shl(T_731, 8) - node T_733 = not(T_728) - node T_734 = and(T_732, T_733) - node T_735 = or(T_730, T_734) - node T_736 = bits(T_728, 27, 0) - node T_737 = shl(T_736, 4) - node T_738 = xor(T_728, T_737) - node T_739 = shr(T_735, 4) - node T_740 = and(T_739, T_738) - node T_741 = bits(T_735, 27, 0) - node T_742 = shl(T_741, 4) - node T_743 = not(T_738) - node T_744 = and(T_742, T_743) - node T_745 = or(T_740, T_744) - node T_746 = bits(T_738, 29, 0) - node T_747 = shl(T_746, 2) - node T_748 = xor(T_738, T_747) - node T_749 = shr(T_745, 2) - node T_750 = and(T_749, T_748) - node T_751 = bits(T_745, 29, 0) - node T_752 = shl(T_751, 2) - node T_753 = not(T_748) - node T_754 = and(T_752, T_753) - node T_755 = or(T_750, T_754) - node T_756 = bits(T_748, 30, 0) - node T_757 = shl(T_756, 1) - node T_758 = xor(T_748, T_757) - node T_759 = shr(T_755, 1) - node T_760 = and(T_759, T_758) - node T_761 = bits(T_755, 30, 0) - node T_762 = shl(T_761, 1) - node T_763 = not(T_758) - node T_764 = and(T_762, T_763) - node T_765 = or(T_760, T_764) - node T_766 = bits(T_713, 53, 32) - node T_767 = bits(T_766, 15, 0) - node T_770 = shl(UInt<8>("hff"), 8) - node T_771 = xor(UInt<16>("hffff"), T_770) - node T_772 = shr(T_767, 8) - node T_773 = and(T_772, T_771) - node T_774 = bits(T_767, 7, 0) - node T_775 = shl(T_774, 8) - node T_776 = not(T_771) - node T_777 = and(T_775, T_776) - node T_778 = or(T_773, T_777) - node T_779 = bits(T_771, 11, 0) - node T_780 = shl(T_779, 4) - node T_781 = xor(T_771, T_780) - node T_782 = shr(T_778, 4) - node T_783 = and(T_782, T_781) - node T_784 = bits(T_778, 11, 0) - node T_785 = shl(T_784, 4) - node T_786 = not(T_781) - node T_787 = and(T_785, T_786) - node T_788 = or(T_783, T_787) - node T_789 = bits(T_781, 13, 0) - node T_790 = shl(T_789, 2) - node T_791 = xor(T_781, T_790) - node T_792 = shr(T_788, 2) - node T_793 = and(T_792, T_791) - node T_794 = bits(T_788, 13, 0) - node T_795 = shl(T_794, 2) - node T_796 = not(T_791) - node T_797 = and(T_795, T_796) - node T_798 = or(T_793, T_797) - node T_799 = bits(T_791, 14, 0) - node T_800 = shl(T_799, 1) - node T_801 = xor(T_791, T_800) - node T_802 = shr(T_798, 1) - node T_803 = and(T_802, T_801) - node T_804 = bits(T_798, 14, 0) - node T_805 = shl(T_804, 1) - node T_806 = not(T_801) - node T_807 = and(T_805, T_806) - node T_808 = or(T_803, T_807) - node T_809 = bits(T_766, 21, 16) - node T_810 = bits(T_809, 3, 0) - node T_811 = bits(T_810, 1, 0) - node T_812 = bits(T_811, 0, 0) - node T_813 = bits(T_811, 1, 1) - node T_814 = cat(T_812, T_813) - node T_815 = bits(T_810, 3, 2) - node T_816 = bits(T_815, 0, 0) - node T_817 = bits(T_815, 1, 1) - node T_818 = cat(T_816, T_817) - node T_819 = cat(T_814, T_818) - node T_820 = bits(T_809, 5, 4) - node T_821 = bits(T_820, 0, 0) - node T_822 = bits(T_820, 1, 1) - node T_823 = cat(T_821, T_822) - node T_824 = cat(T_819, T_823) - node T_825 = cat(T_808, T_824) - node T_826 = cat(T_765, T_825) - node T_827 = bits(sigX3, 55, 55) - node T_828 = or(T_826, T_827) - node T_830 = cat(T_828, UInt<2>("h3")) - node roundMask = or(T_709, T_830) - node T_832 = shr(roundMask, 1) - node T_833 = not(T_832) - node roundPosMask = and(T_833, roundMask) - node T_835 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_835, UInt<1>("h0")) - node T_838 = shr(roundMask, 1) - node T_839 = and(sigX3, T_838) - node anyRoundExtra = neq(T_839, UInt<1>("h0")) - node T_842 = not(sigX3) - node T_843 = shr(roundMask, 1) - node T_844 = and(T_842, T_843) - node allRoundExtra = eq(T_844, UInt<1>("h0")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_850 = not(doIncrSig) - node T_851 = and(T_850, roundingMode_nearest_even) - node T_852 = and(T_851, roundPosBit) - node T_853 = and(T_852, anyRoundExtra) - node T_854 = not(doIncrSig) - node T_855 = and(T_854, roundDirectUp) - node T_856 = and(T_855, anyRound) - node T_857 = or(T_853, T_856) - node T_858 = and(doIncrSig, allRound) - node T_859 = or(T_857, T_858) - node T_860 = and(doIncrSig, roundingMode_nearest_even) - node T_861 = and(T_860, roundPosBit) - node T_862 = or(T_859, T_861) - node T_863 = and(doIncrSig, roundDirectUp) - node T_865 = and(T_863, UInt<1>("h1")) - node roundUp = or(T_862, T_865) - node T_867 = not(roundPosBit) - node T_868 = and(roundingMode_nearest_even, T_867) - node T_869 = and(T_868, allRoundExtra) - node T_870 = and(roundingMode_nearest_even, roundPosBit) - node T_871 = not(anyRoundExtra) - node T_872 = and(T_870, T_871) - node roundEven = mux(doIncrSig, T_869, T_872) - node T_874 = not(allRound) - node roundInexact = mux(doIncrSig, T_874, anyRound) - node T_876 = or(sigX3, roundMask) - node T_877 = shr(T_876, 2) - node T_879 = add(T_877, UInt<1>("h1")) - node T_880 = tail(T_879, 1) - node roundUp_sigY3 = bits(T_880, 54, 0) - node T_882 = not(roundUp) - node T_883 = not(roundEven) - node T_884 = and(T_882, T_883) - node T_885 = bits(T_884, 0, 0) - node T_886 = not(roundMask) - node T_887 = and(sigX3, T_886) - node T_888 = shr(T_887, 2) - node T_890 = mux(T_885, T_888, UInt<1>("h0")) - node T_891 = bits(roundUp, 0, 0) - node T_893 = mux(T_891, roundUp_sigY3, UInt<1>("h0")) - node T_894 = or(T_890, T_893) - node T_895 = shr(roundMask, 1) - node T_896 = not(T_895) - node T_897 = and(roundUp_sigY3, T_896) - node T_899 = mux(roundEven, T_897, UInt<1>("h0")) - node sigY3 = or(T_894, T_899) - node T_901 = bits(sigY3, 54, 54) - node T_903 = add(sExpX3, UInt<1>("h1")) - node T_904 = tail(T_903, 1) - node T_906 = mux(T_901, T_904, UInt<1>("h0")) - node T_907 = bits(sigY3, 53, 53) - node T_909 = mux(T_907, sExpX3, UInt<1>("h0")) - node T_910 = or(T_906, T_909) - node T_911 = bits(sigY3, 54, 53) - node T_913 = eq(T_911, UInt<1>("h0")) - node T_915 = sub(sExpX3, UInt<1>("h1")) - node T_916 = tail(T_915, 1) - node T_918 = mux(T_913, T_916, UInt<1>("h0")) - node sExpY = or(T_910, T_918) - node expY = bits(sExpY, 11, 0) - node T_921 = bits(sigY3, 51, 0) - node T_922 = bits(sigY3, 52, 1) - node fractY = mux(sigX3Shift1, T_921, T_922) - node T_924 = bits(sExpY, 12, 10) - node overflowY = eq(T_924, UInt<2>("h3")) - node T_927 = not(isZeroY) - node T_928 = bits(sExpY, 12, 12) - node T_929 = bits(sExpY, 11, 0) - node T_931 = lt(T_929, UInt<10>("h3ce")) - node T_932 = or(T_928, T_931) - node totalUnderflowY = and(T_927, T_932) - node T_934 = bits(sExpX3, 13, 13) - node T_937 = mux(sigX3Shift1, UInt<11>("h402"), UInt<11>("h401")) - node T_938 = leq(sExpX3_13, T_937) - node T_939 = or(T_934, T_938) - node underflowY = and(roundInexact, T_939) - node T_941 = and(roundingMode_min, signY) - node T_942 = not(signY) - node T_943 = and(roundingMode_max, T_942) - node roundMagUp = or(T_941, T_943) - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_949 = not(addSpecial) - node T_950 = not(notSpecial_addZeros) - node commonCase = and(T_949, T_950) - node T_952 = and(isInfA, isZeroB) - node T_953 = and(isZeroA, isInfB) - node T_954 = or(T_952, T_953) - node T_955 = not(isNaNA) - node T_956 = not(isNaNB) - node T_957 = and(T_955, T_956) - node T_958 = or(isInfA, isInfB) - node T_959 = and(T_957, T_958) - node T_960 = and(T_959, isInfC) - node T_961 = and(T_960, doSubMags) - node notSigNaN_invalid = or(T_954, T_961) - node T_963 = or(isSigNaNA, isSigNaNB) - node T_964 = or(T_963, isSigNaNC) - node invalid = or(T_964, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_968 = and(commonCase, roundInexact) - node inexact = or(overflow, T_968) - node T_970 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_970, totalUnderflowY) - node T_972 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_972, roundMagUp) - node T_974 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_974) - node T_976 = or(isInfA, isInfB) - node T_977 = or(T_976, isInfC) - node T_978 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_977, T_978) - node T_980 = or(isNaNA, isNaNB) - node T_981 = or(T_980, isNaNC) - node isNaNOut = or(T_981, notSigNaN_invalid) - node T_984 = eq(doSubMags, UInt<1>("h0")) - node T_985 = and(T_984, io.fromPreMul.opSignC) - node T_987 = eq(isSpecialC, UInt<1>("h0")) - node T_988 = and(mulSpecial, T_987) - node T_989 = and(T_988, io.fromPreMul.signProd) - node T_990 = or(T_985, T_989) - node T_992 = eq(mulSpecial, UInt<1>("h0")) - node T_993 = and(T_992, isSpecialC) - node T_994 = and(T_993, io.fromPreMul.opSignC) - node T_995 = or(T_990, T_994) - node T_997 = eq(mulSpecial, UInt<1>("h0")) - node T_998 = and(T_997, notSpecial_addZeros) - node T_999 = and(T_998, doSubMags) - node T_1000 = and(T_999, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_995, T_1000) - node T_1003 = eq(isNaNOut, UInt<1>("h0")) - node T_1004 = and(T_1003, uncommonCaseSignOut) - node T_1005 = and(commonCase, signY) - node signOut = or(T_1004, T_1005) - node T_1009 = mux(notSpecial_isZeroOut, UInt<12>("he00"), UInt<12>("h0")) - node T_1010 = not(T_1009) - node T_1011 = and(expY, T_1010) - node T_1013 = not(UInt<12>("h3ce")) - node T_1015 = mux(pegMinFiniteMagOut, T_1013, UInt<12>("h0")) - node T_1016 = not(T_1015) - node T_1017 = and(T_1011, T_1016) - node T_1020 = mux(pegMaxFiniteMagOut, UInt<12>("h400"), UInt<12>("h0")) - node T_1021 = not(T_1020) - node T_1022 = and(T_1017, T_1021) - node T_1025 = mux(notNaN_isInfOut, UInt<10>("h200"), UInt<12>("h0")) - node T_1026 = not(T_1025) - node T_1027 = and(T_1022, T_1026) - node T_1030 = mux(pegMinFiniteMagOut, UInt<10>("h3ce"), UInt<12>("h0")) - node T_1031 = or(T_1027, T_1030) - node T_1034 = mux(pegMaxFiniteMagOut, UInt<12>("hbff"), UInt<12>("h0")) - node T_1035 = or(T_1031, T_1034) - node T_1038 = mux(notNaN_isInfOut, UInt<12>("hc00"), UInt<12>("h0")) - node T_1039 = or(T_1035, T_1038) - node T_1042 = mux(isNaNOut, UInt<12>("he00"), UInt<12>("h0")) - node expOut = or(T_1039, T_1042) - node T_1044 = and(totalUnderflowY, roundMagUp) - node T_1045 = or(T_1044, isNaNOut) - node T_1047 = mux(T_1045, UInt<1>("h0"), fractY) - node T_1048 = shl(isNaNOut, 51) - node T_1049 = or(T_1047, T_1048) - node T_1051 = sub(UInt<52>("h0"), pegMaxFiniteMagOut) - node T_1052 = tail(T_1051, 1) - node fractOut = or(T_1049, T_1052) - node T_1054 = cat(expOut, fractOut) - node T_1055 = cat(signOut, T_1054) - io.out <= T_1055 - node T_1057 = cat(invalid, UInt<1>("h0")) - node T_1058 = cat(underflow, inexact) - node T_1059 = cat(overflow, T_1058) - node T_1060 = cat(T_1057, T_1059) - io.exceptionFlags <= T_1060 - module MulAddRecFN_114 : - input clk : Clock - input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul_115 - mulAddRecFN_preMul.io is invalid - mulAddRecFN_preMul.clk <= clk - mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul_116 - mulAddRecFN_postMul.io is invalid - mulAddRecFN_postMul.clk <= clk - mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op - mulAddRecFN_preMul.io.a <= io.a - mulAddRecFN_preMul.io.b <= io.b - mulAddRecFN_preMul.io.c <= io.c - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_16 = cat(UInt<1>("h0"), mulAddRecFN_preMul.io.mulAddC) - node T_17 = add(T_14, T_16) - node T_18 = tail(T_17, 1) - mulAddRecFN_postMul.io.mulAddResult <= T_18 - io.out <= mulAddRecFN_postMul.io.out - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags - module FPUFMAPipe_113 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} - io is invalid - node one = shl(UInt<1>("h1"), 63) - node T_136 = bits(io.in.bits.in1, 64, 64) - node T_137 = bits(io.in.bits.in2, 64, 64) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 64) - reg valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), valid) - valid <= io.in.valid - reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : - reset => (UInt<1>("h0"), in) - when io.in.valid : - in <- io.in.bits - node T_187 = bits(io.in.bits.cmd, 1, 1) - node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bits(io.in.bits.cmd, 0, 0) - node T_191 = cat(T_189, T_190) - in.cmd <= T_191 - when io.in.bits.swap23 : - in.in2 <= one - skip - node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h0")) - when T_194 : - in.in3 <= zero - skip - skip - inst fma of MulAddRecFN_114 - fma.io is invalid - fma.clk <= clk - fma.reset <= reset - fma.io.op <= in.cmd - fma.io.roundingMode <= in.rm - fma.io.a <= in.in1 - fma.io.b <= in.in2 - fma.io.c <= in.in3 - wire res : { data : UInt<65>, exc : UInt<5>} - res is invalid - node T_203 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_204 = cat(T_203, fma.io.out) - res.data <= T_204 - res.exc <= fma.io.exceptionFlags - reg T_207 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_207 <= valid - reg T_208 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_208) - when valid : - T_208 <- res - skip - reg T_213 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_213 <= T_207 - reg T_214 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_214) - when T_207 : - T_214 <- T_208 - skip - wire T_225 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} - T_225 is invalid - T_225.valid <= T_213 - T_225.bits <- T_214 - io.out <- T_225 - module RecFNToRecFN : - input clk : Clock - input reset : UInt<1> - output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io is invalid - node T_8 = bits(io.in, 31, 23) - node T_9 = bits(T_8, 8, 7) - node T_11 = eq(T_9, UInt<2>("h3")) - wire T_19 : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - T_19 is invalid - node T_26 = bits(io.in, 32, 32) - T_19.sign <= T_26 - node T_27 = bits(T_8, 6, 6) - node T_28 = and(T_11, T_27) - T_19.isNaN <= T_28 - node T_29 = bits(T_8, 6, 6) - node T_31 = eq(T_29, UInt<1>("h0")) - node T_32 = and(T_11, T_31) - T_19.isInf <= T_32 - node T_33 = bits(T_8, 8, 6) - node T_35 = eq(T_33, UInt<1>("h0")) - T_19.isZero <= T_35 - node T_36 = cvt(T_8) - T_19.sExp <= T_36 - node T_38 = bits(io.in, 22, 0) - node T_40 = cat(T_38, UInt<2>("h0")) - node T_41 = cat(UInt<2>("h1"), T_40) - T_19.sig <= T_41 - node T_43 = add(T_19.sExp, asSInt(UInt<12>("h700"))) - node T_44 = tail(T_43, 1) - node T_45 = asSInt(T_44) - wire outRawFloat : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - outRawFloat is invalid - outRawFloat.sign <= T_19.sign - outRawFloat.isNaN <= T_19.isNaN - outRawFloat.isInf <= T_19.isInf - outRawFloat.isZero <= T_19.isZero - outRawFloat.sExp <= T_45 - node T_60 = shl(T_19.sig, 29) - outRawFloat.sig <= T_60 - node T_61 = bits(outRawFloat.sig, 53, 53) - node T_63 = eq(T_61, UInt<1>("h0")) - node invalidExc = and(outRawFloat.isNaN, T_63) - node T_65 = not(outRawFloat.isNaN) - node T_66 = and(outRawFloat.sign, T_65) - node T_67 = bits(outRawFloat.sExp, 11, 0) - node T_70 = mux(outRawFloat.isZero, UInt<12>("hc00"), UInt<1>("h0")) - node T_71 = not(T_70) - node T_72 = and(T_67, T_71) - node T_73 = or(outRawFloat.isZero, outRawFloat.isInf) - node T_76 = mux(T_73, UInt<12>("h200"), UInt<1>("h0")) - node T_77 = not(T_76) - node T_78 = and(T_72, T_77) - node T_81 = mux(outRawFloat.isInf, UInt<12>("hc00"), UInt<1>("h0")) - node T_82 = or(T_78, T_81) - node T_85 = mux(outRawFloat.isNaN, UInt<12>("he00"), UInt<1>("h0")) - node T_86 = or(T_82, T_85) - node T_88 = bits(outRawFloat.sig, 53, 2) - node T_89 = mux(outRawFloat.isNaN, UInt<52>("h8000000000000"), T_88) - node T_90 = cat(T_86, T_89) - node T_91 = cat(T_66, T_90) - io.out <= T_91 - node T_93 = cat(invalidExc, UInt<4>("h0")) - io.exceptionFlags <= T_93 - module CompareRecFN : - input clk : Clock - input reset : UInt<1> - output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} - io is invalid - node T_11 = bits(io.a, 63, 52) - node T_12 = bits(T_11, 11, 10) - node T_14 = eq(T_12, UInt<2>("h3")) - wire rawA : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawA is invalid - node T_29 = bits(io.a, 64, 64) - rawA.sign <= T_29 - node T_30 = bits(T_11, 9, 9) - node T_31 = and(T_14, T_30) - rawA.isNaN <= T_31 - node T_32 = bits(T_11, 9, 9) - node T_34 = eq(T_32, UInt<1>("h0")) - node T_35 = and(T_14, T_34) - rawA.isInf <= T_35 - node T_36 = bits(T_11, 11, 9) - node T_38 = eq(T_36, UInt<1>("h0")) - rawA.isZero <= T_38 - node T_39 = cvt(T_11) - rawA.sExp <= T_39 - node T_41 = bits(io.a, 51, 0) - node T_43 = cat(T_41, UInt<2>("h0")) - node T_44 = cat(UInt<2>("h1"), T_43) - rawA.sig <= T_44 - node T_45 = bits(io.b, 63, 52) - node T_46 = bits(T_45, 11, 10) - node T_48 = eq(T_46, UInt<2>("h3")) - wire rawB : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawB is invalid - node T_63 = bits(io.b, 64, 64) - rawB.sign <= T_63 - node T_64 = bits(T_45, 9, 9) - node T_65 = and(T_48, T_64) - rawB.isNaN <= T_65 - node T_66 = bits(T_45, 9, 9) - node T_68 = eq(T_66, UInt<1>("h0")) - node T_69 = and(T_48, T_68) - rawB.isInf <= T_69 - node T_70 = bits(T_45, 11, 9) - node T_72 = eq(T_70, UInt<1>("h0")) - rawB.isZero <= T_72 - node T_73 = cvt(T_45) - rawB.sExp <= T_73 - node T_75 = bits(io.b, 51, 0) - node T_77 = cat(T_75, UInt<2>("h0")) - node T_78 = cat(UInt<2>("h1"), T_77) - rawB.sig <= T_78 - node T_79 = not(rawA.isNaN) - node T_80 = not(rawB.isNaN) - node ordered = and(T_79, T_80) - node bothInfs = and(rawA.isInf, rawB.isInf) - node bothZeros = and(rawA.isZero, rawB.isZero) - node eqExps = eq(rawA.sExp, rawB.sExp) - node T_85 = lt(rawA.sExp, rawB.sExp) - node T_86 = lt(rawA.sig, rawB.sig) - node T_87 = and(eqExps, T_86) - node common_ltMags = or(T_85, T_87) - node T_89 = eq(rawA.sig, rawB.sig) - node common_eqMags = and(eqExps, T_89) - node T_91 = not(bothZeros) - node T_92 = not(rawB.sign) - node T_93 = and(rawA.sign, T_92) - node T_94 = not(bothInfs) - node T_95 = not(common_ltMags) - node T_96 = and(rawA.sign, T_95) - node T_97 = not(common_eqMags) - node T_98 = and(T_96, T_97) - node T_99 = not(rawB.sign) - node T_100 = and(T_99, common_ltMags) - node T_101 = or(T_98, T_100) - node T_102 = and(T_94, T_101) - node T_103 = or(T_93, T_102) - node ordered_lt = and(T_91, T_103) - node T_105 = eq(rawA.sign, rawB.sign) - node T_106 = or(bothInfs, common_eqMags) - node T_107 = and(T_105, T_106) - node ordered_eq = or(bothZeros, T_107) - node T_109 = bits(rawA.sig, 53, 53) - node T_111 = eq(T_109, UInt<1>("h0")) - node T_112 = and(rawA.isNaN, T_111) - node T_113 = bits(rawB.sig, 53, 53) - node T_115 = eq(T_113, UInt<1>("h0")) - node T_116 = and(rawB.isNaN, T_115) - node T_117 = or(T_112, T_116) - node T_118 = not(ordered) - node T_119 = and(io.signaling, T_118) - node invalid = or(T_117, T_119) - node T_121 = and(ordered, ordered_lt) - io.lt <= T_121 - node T_122 = and(ordered, ordered_eq) - io.eq <= T_122 - node T_123 = not(ordered_lt) - node T_124 = and(ordered, T_123) - node T_125 = not(ordered_eq) - node T_126 = and(T_124, T_125) - io.gt <= T_126 - node T_128 = cat(invalid, UInt<4>("h0")) - io.exceptionFlags <= T_128 - module RecFNToIN : - input clk : Clock - input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} - io is invalid - node sign = bits(io.in, 64, 64) - node exp = bits(io.in, 63, 52) - node fract = bits(io.in, 51, 0) - node T_12 = bits(exp, 11, 9) - node isZero = eq(T_12, UInt<1>("h0")) - node T_15 = bits(exp, 11, 10) - node T_16 = not(T_15) - node isSpecial = eq(T_16, UInt<1>("h0")) - node T_19 = bits(exp, 9, 9) - node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bits(exp, 11, 11) - node T_22 = cat(notSpecial_magGeOne, fract) - node T_23 = bits(exp, 5, 0) - node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h0")) - node shiftedSig = dshl(T_22, T_25) - node unroundedInt = bits(shiftedSig, 115, 52) - node T_28 = bits(shiftedSig, 52, 51) - node T_29 = bits(shiftedSig, 50, 0) - node T_31 = neq(T_29, UInt<1>("h0")) - node roundBits = cat(T_28, T_31) - node T_33 = bits(roundBits, 1, 0) - node T_35 = neq(T_33, UInt<1>("h0")) - node T_37 = eq(isZero, UInt<1>("h0")) - node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) - node T_39 = bits(roundBits, 2, 1) - node T_40 = not(T_39) - node T_42 = eq(T_40, UInt<1>("h0")) - node T_43 = bits(roundBits, 1, 0) - node T_44 = not(T_43) - node T_46 = eq(T_44, UInt<1>("h0")) - node T_47 = or(T_42, T_46) - node T_48 = bits(exp, 10, 0) - node T_49 = not(T_48) - node T_51 = eq(T_49, UInt<1>("h0")) - node T_52 = bits(roundBits, 1, 0) - node T_54 = neq(T_52, UInt<1>("h0")) - node T_56 = mux(T_51, T_54, UInt<1>("h0")) - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) - node T_58 = eq(io.roundingMode, UInt<2>("h0")) - node T_59 = and(T_58, roundIncr_nearestEven) - node T_60 = eq(io.roundingMode, UInt<2>("h2")) - node T_61 = and(sign, roundInexact) - node T_62 = and(T_60, T_61) - node T_63 = or(T_59, T_62) - node T_64 = eq(io.roundingMode, UInt<2>("h3")) - node T_66 = eq(sign, UInt<1>("h0")) - node T_67 = and(T_66, roundInexact) - node T_68 = and(T_64, T_67) - node roundIncr = or(T_63, T_68) - node T_70 = not(unroundedInt) - node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) - node T_72 = xor(roundIncr, sign) - node T_74 = add(onesCompUnroundedInt, UInt<1>("h1")) - node T_75 = tail(T_74, 1) - node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) - node T_77 = bits(unroundedInt, 61, 0) - node T_78 = not(T_77) - node T_80 = eq(T_78, UInt<1>("h0")) - node roundCarryBut2 = and(T_80, roundIncr) - node posExp = bits(exp, 10, 0) - node T_84 = geq(posExp, UInt<7>("h40")) - node T_86 = eq(posExp, UInt<6>("h3f")) - node T_88 = eq(sign, UInt<1>("h0")) - node T_89 = bits(unroundedInt, 62, 0) - node T_91 = neq(T_89, UInt<1>("h0")) - node T_92 = or(T_88, T_91) - node T_93 = or(T_92, roundIncr) - node T_94 = and(T_86, T_93) - node T_95 = or(T_84, T_94) - node T_97 = eq(sign, UInt<1>("h0")) - node T_99 = eq(posExp, UInt<6>("h3e")) - node T_100 = and(T_97, T_99) - node T_101 = and(T_100, roundCarryBut2) - node T_102 = or(T_95, T_101) - node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h0")) - node T_106 = geq(posExp, UInt<7>("h40")) - node T_107 = or(sign, T_106) - node T_109 = eq(posExp, UInt<6>("h3f")) - node T_110 = bits(unroundedInt, 62, 62) - node T_111 = and(T_109, T_110) - node T_112 = and(T_111, roundCarryBut2) - node T_113 = or(T_107, T_112) - node T_114 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_118 = eq(isNaN, UInt<1>("h0")) - node excSign = and(sign, T_118) - node T_120 = and(io.signedOut, excSign) - node T_123 = mux(T_120, UInt<64>("h8000000000000000"), UInt<1>("h0")) - node T_125 = eq(excSign, UInt<1>("h0")) - node T_126 = and(io.signedOut, T_125) - node T_129 = mux(T_126, UInt<63>("h7fffffffffffffff"), UInt<1>("h0")) - node T_130 = or(T_123, T_129) - node T_132 = eq(io.signedOut, UInt<1>("h0")) - node T_135 = mux(T_132, UInt<64>("hffffffffffffffff"), UInt<1>("h0")) - node excValue = or(T_130, T_135) - node T_138 = eq(isSpecial, UInt<1>("h0")) - node T_139 = and(roundInexact, T_138) - node T_141 = eq(overflow, UInt<1>("h0")) - node inexact = and(T_139, T_141) - node T_143 = or(isSpecial, overflow) - node T_144 = mux(T_143, excValue, roundedInt) - io.out <= T_144 - node T_145 = cat(overflow, inexact) - node T_146 = cat(isSpecial, T_145) - io.intExceptionFlags <= T_146 - module RecFNToIN_118 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} - io is invalid - node sign = bits(io.in, 64, 64) - node exp = bits(io.in, 63, 52) - node fract = bits(io.in, 51, 0) - node T_12 = bits(exp, 11, 9) - node isZero = eq(T_12, UInt<1>("h0")) - node T_15 = bits(exp, 11, 10) - node T_16 = not(T_15) - node isSpecial = eq(T_16, UInt<1>("h0")) - node T_19 = bits(exp, 9, 9) - node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bits(exp, 11, 11) - node T_22 = cat(notSpecial_magGeOne, fract) - node T_23 = bits(exp, 4, 0) - node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h0")) - node shiftedSig = dshl(T_22, T_25) - node unroundedInt = bits(shiftedSig, 83, 52) - node T_28 = bits(shiftedSig, 52, 51) - node T_29 = bits(shiftedSig, 50, 0) - node T_31 = neq(T_29, UInt<1>("h0")) - node roundBits = cat(T_28, T_31) - node T_33 = bits(roundBits, 1, 0) - node T_35 = neq(T_33, UInt<1>("h0")) - node T_37 = eq(isZero, UInt<1>("h0")) - node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) - node T_39 = bits(roundBits, 2, 1) - node T_40 = not(T_39) - node T_42 = eq(T_40, UInt<1>("h0")) - node T_43 = bits(roundBits, 1, 0) - node T_44 = not(T_43) - node T_46 = eq(T_44, UInt<1>("h0")) - node T_47 = or(T_42, T_46) - node T_48 = bits(exp, 10, 0) - node T_49 = not(T_48) - node T_51 = eq(T_49, UInt<1>("h0")) - node T_52 = bits(roundBits, 1, 0) - node T_54 = neq(T_52, UInt<1>("h0")) - node T_56 = mux(T_51, T_54, UInt<1>("h0")) - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) - node T_58 = eq(io.roundingMode, UInt<2>("h0")) - node T_59 = and(T_58, roundIncr_nearestEven) - node T_60 = eq(io.roundingMode, UInt<2>("h2")) - node T_61 = and(sign, roundInexact) - node T_62 = and(T_60, T_61) - node T_63 = or(T_59, T_62) - node T_64 = eq(io.roundingMode, UInt<2>("h3")) - node T_66 = eq(sign, UInt<1>("h0")) - node T_67 = and(T_66, roundInexact) - node T_68 = and(T_64, T_67) - node roundIncr = or(T_63, T_68) - node T_70 = not(unroundedInt) - node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) - node T_72 = xor(roundIncr, sign) - node T_74 = add(onesCompUnroundedInt, UInt<1>("h1")) - node T_75 = tail(T_74, 1) - node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) - node T_77 = bits(unroundedInt, 29, 0) - node T_78 = not(T_77) - node T_80 = eq(T_78, UInt<1>("h0")) - node roundCarryBut2 = and(T_80, roundIncr) - node posExp = bits(exp, 10, 0) - node T_84 = geq(posExp, UInt<6>("h20")) - node T_86 = eq(posExp, UInt<5>("h1f")) - node T_88 = eq(sign, UInt<1>("h0")) - node T_89 = bits(unroundedInt, 30, 0) - node T_91 = neq(T_89, UInt<1>("h0")) - node T_92 = or(T_88, T_91) - node T_93 = or(T_92, roundIncr) - node T_94 = and(T_86, T_93) - node T_95 = or(T_84, T_94) - node T_97 = eq(sign, UInt<1>("h0")) - node T_99 = eq(posExp, UInt<5>("h1e")) - node T_100 = and(T_97, T_99) - node T_101 = and(T_100, roundCarryBut2) - node T_102 = or(T_95, T_101) - node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h0")) - node T_106 = geq(posExp, UInt<6>("h20")) - node T_107 = or(sign, T_106) - node T_109 = eq(posExp, UInt<5>("h1f")) - node T_110 = bits(unroundedInt, 30, 30) - node T_111 = and(T_109, T_110) - node T_112 = and(T_111, roundCarryBut2) - node T_113 = or(T_107, T_112) - node T_114 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_118 = eq(isNaN, UInt<1>("h0")) - node excSign = and(sign, T_118) - node T_120 = and(io.signedOut, excSign) - node T_123 = mux(T_120, UInt<32>("h80000000"), UInt<1>("h0")) - node T_125 = eq(excSign, UInt<1>("h0")) - node T_126 = and(io.signedOut, T_125) - node T_129 = mux(T_126, UInt<31>("h7fffffff"), UInt<1>("h0")) - node T_130 = or(T_123, T_129) - node T_132 = eq(io.signedOut, UInt<1>("h0")) - node T_135 = mux(T_132, UInt<32>("hffffffff"), UInt<1>("h0")) - node excValue = or(T_130, T_135) - node T_138 = eq(isSpecial, UInt<1>("h0")) - node T_139 = and(roundInexact, T_138) - node T_141 = eq(overflow, UInt<1>("h0")) - node inexact = and(T_139, T_141) - node T_143 = or(isSpecial, overflow) - node T_144 = mux(T_143, excValue, roundedInt) - io.out <= T_144 - node T_145 = cat(overflow, inexact) - node T_146 = cat(isSpecial, T_145) - io.intExceptionFlags <= T_146 - module FPToInt : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : { valid : UInt<1>, bits : { lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} - io is invalid - reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : - reset => (UInt<1>("h0"), in) - reg valid : UInt<1>, clk with : - reset => (UInt<1>("h0"), valid) - valid <= io.in.valid - inst T_233 of RecFNToRecFN - T_233.io is invalid - T_233.clk <= clk - T_233.reset <= reset - T_233.io.in <= io.in.bits.in1 - T_233.io.roundingMode <= UInt<1>("h0") - inst T_235 of RecFNToRecFN - T_235.io is invalid - T_235.clk <= clk - T_235.reset <= reset - T_235.io.in <= io.in.bits.in2 - T_235.io.roundingMode <= UInt<1>("h0") - when io.in.valid : - in <- io.in.bits - node T_238 = eq(io.in.bits.ldst, UInt<1>("h0")) - node T_239 = and(io.in.bits.single, T_238) - node T_242 = and(io.in.bits.cmd, UInt<4>("hc")) - node T_243 = eq(UInt<4>("hc"), T_242) - node T_245 = eq(T_243, UInt<1>("h0")) - node T_246 = and(T_239, T_245) - when T_246 : - in.in1 <= T_233.io.out - in.in2 <= T_235.io.out - skip - skip - node T_247 = bits(in.in1, 32, 32) - node T_248 = bits(in.in1, 31, 23) - node T_249 = bits(in.in1, 22, 0) - node T_250 = bits(T_248, 6, 0) - node T_252 = lt(T_250, UInt<2>("h2")) - node T_253 = bits(T_248, 8, 6) - node T_255 = eq(T_253, UInt<1>("h1")) - node T_256 = bits(T_248, 8, 7) - node T_258 = eq(T_256, UInt<1>("h1")) - node T_259 = and(T_258, T_252) - node T_260 = or(T_255, T_259) - node T_261 = bits(T_248, 8, 7) - node T_263 = eq(T_261, UInt<1>("h1")) - node T_265 = eq(T_252, UInt<1>("h0")) - node T_266 = and(T_263, T_265) - node T_267 = bits(T_248, 8, 7) - node T_269 = eq(T_267, UInt<2>("h2")) - node T_270 = or(T_266, T_269) - node T_271 = bits(T_248, 8, 7) - node T_273 = eq(T_271, UInt<2>("h3")) - node T_274 = bits(T_248, 6, 6) - node T_275 = and(T_273, T_274) - node T_277 = bits(T_248, 4, 0) - node T_278 = sub(UInt<2>("h2"), T_277) - node T_279 = tail(T_278, 1) - node T_281 = cat(UInt<1>("h1"), T_249) - node T_282 = dshr(T_281, T_279) - node T_283 = bits(T_282, 22, 0) - node T_284 = bits(T_248, 7, 0) - node T_286 = sub(T_284, UInt<8>("h81")) - node T_287 = tail(T_286, 1) - node T_289 = sub(UInt<8>("h0"), T_273) - node T_290 = tail(T_289, 1) - node T_291 = mux(T_270, T_287, T_290) - node T_292 = or(T_270, T_275) - node T_294 = mux(T_260, T_283, UInt<1>("h0")) - node T_295 = mux(T_292, T_249, T_294) - node T_296 = cat(T_291, T_295) - node unrec_s = cat(T_247, T_296) - node T_298 = bits(in.in1, 64, 64) - node T_299 = bits(in.in1, 63, 52) - node T_300 = bits(in.in1, 51, 0) - node T_301 = bits(T_299, 9, 0) - node T_303 = lt(T_301, UInt<2>("h2")) - node T_304 = bits(T_299, 11, 9) - node T_306 = eq(T_304, UInt<1>("h1")) - node T_307 = bits(T_299, 11, 10) - node T_309 = eq(T_307, UInt<1>("h1")) - node T_310 = and(T_309, T_303) - node T_311 = or(T_306, T_310) - node T_312 = bits(T_299, 11, 10) - node T_314 = eq(T_312, UInt<1>("h1")) - node T_316 = eq(T_303, UInt<1>("h0")) - node T_317 = and(T_314, T_316) - node T_318 = bits(T_299, 11, 10) - node T_320 = eq(T_318, UInt<2>("h2")) - node T_321 = or(T_317, T_320) - node T_322 = bits(T_299, 11, 10) - node T_324 = eq(T_322, UInt<2>("h3")) - node T_325 = bits(T_299, 9, 9) - node T_326 = and(T_324, T_325) - node T_328 = bits(T_299, 5, 0) - node T_329 = sub(UInt<2>("h2"), T_328) - node T_330 = tail(T_329, 1) - node T_332 = cat(UInt<1>("h1"), T_300) - node T_333 = dshr(T_332, T_330) - node T_334 = bits(T_333, 51, 0) - node T_335 = bits(T_299, 10, 0) - node T_337 = sub(T_335, UInt<11>("h401")) - node T_338 = tail(T_337, 1) - node T_340 = sub(UInt<11>("h0"), T_324) - node T_341 = tail(T_340, 1) - node T_342 = mux(T_321, T_338, T_341) - node T_343 = or(T_321, T_326) - node T_345 = mux(T_311, T_334, UInt<1>("h0")) - node T_346 = mux(T_343, T_300, T_345) - node T_347 = cat(T_342, T_346) - node unrec_d = cat(T_298, T_347) - node T_349 = bits(unrec_s, 31, 31) - node T_351 = sub(UInt<32>("h0"), T_349) - node T_352 = tail(T_351, 1) - node T_353 = cat(T_352, unrec_s) - node unrec_out = mux(in.single, T_353, unrec_d) - node T_355 = bits(in.in1, 32, 32) - node T_356 = bits(in.in1, 31, 23) - node T_357 = bits(in.in1, 22, 0) - node T_358 = bits(T_356, 8, 6) - node T_359 = bits(T_358, 2, 1) - node T_361 = eq(T_359, UInt<2>("h3")) - node T_362 = bits(T_356, 6, 0) - node T_364 = lt(T_362, UInt<2>("h2")) - node T_366 = eq(T_358, UInt<1>("h1")) - node T_368 = eq(T_359, UInt<1>("h1")) - node T_369 = and(T_368, T_364) - node T_370 = or(T_366, T_369) - node T_372 = eq(T_359, UInt<1>("h1")) - node T_374 = eq(T_364, UInt<1>("h0")) - node T_375 = and(T_372, T_374) - node T_377 = eq(T_359, UInt<2>("h2")) - node T_378 = or(T_375, T_377) - node T_380 = eq(T_358, UInt<1>("h0")) - node T_381 = bits(T_356, 6, 6) - node T_383 = eq(T_381, UInt<1>("h0")) - node T_384 = and(T_361, T_383) - node T_385 = not(T_358) - node T_387 = eq(T_385, UInt<1>("h0")) - node T_388 = bits(T_357, 22, 22) - node T_390 = eq(T_388, UInt<1>("h0")) - node T_391 = and(T_387, T_390) - node T_392 = bits(T_357, 22, 22) - node T_393 = and(T_387, T_392) - node T_395 = eq(T_355, UInt<1>("h0")) - node T_396 = and(T_384, T_395) - node T_398 = eq(T_355, UInt<1>("h0")) - node T_399 = and(T_378, T_398) - node T_401 = eq(T_355, UInt<1>("h0")) - node T_402 = and(T_370, T_401) - node T_404 = eq(T_355, UInt<1>("h0")) - node T_405 = and(T_380, T_404) - node T_406 = and(T_380, T_355) - node T_407 = and(T_370, T_355) - node T_408 = and(T_378, T_355) - node T_409 = and(T_384, T_355) - node T_410 = cat(T_393, T_391) - node T_411 = cat(T_399, T_402) - node T_412 = cat(T_396, T_411) - node T_413 = cat(T_410, T_412) - node T_414 = cat(T_405, T_406) - node T_415 = cat(T_408, T_409) - node T_416 = cat(T_407, T_415) - node T_417 = cat(T_414, T_416) - node classify_s = cat(T_413, T_417) - node T_419 = bits(in.in1, 64, 64) - node T_420 = bits(in.in1, 63, 52) - node T_421 = bits(in.in1, 51, 0) - node T_422 = bits(T_420, 11, 9) - node T_423 = bits(T_422, 2, 1) - node T_425 = eq(T_423, UInt<2>("h3")) - node T_426 = bits(T_420, 9, 0) - node T_428 = lt(T_426, UInt<2>("h2")) - node T_430 = eq(T_422, UInt<1>("h1")) - node T_432 = eq(T_423, UInt<1>("h1")) - node T_433 = and(T_432, T_428) - node T_434 = or(T_430, T_433) - node T_436 = eq(T_423, UInt<1>("h1")) - node T_438 = eq(T_428, UInt<1>("h0")) - node T_439 = and(T_436, T_438) - node T_441 = eq(T_423, UInt<2>("h2")) - node T_442 = or(T_439, T_441) - node T_444 = eq(T_422, UInt<1>("h0")) - node T_445 = bits(T_420, 9, 9) - node T_447 = eq(T_445, UInt<1>("h0")) - node T_448 = and(T_425, T_447) - node T_449 = not(T_422) - node T_451 = eq(T_449, UInt<1>("h0")) - node T_452 = bits(T_421, 51, 51) - node T_454 = eq(T_452, UInt<1>("h0")) - node T_455 = and(T_451, T_454) - node T_456 = bits(T_421, 51, 51) - node T_457 = and(T_451, T_456) - node T_459 = eq(T_419, UInt<1>("h0")) - node T_460 = and(T_448, T_459) - node T_462 = eq(T_419, UInt<1>("h0")) - node T_463 = and(T_442, T_462) - node T_465 = eq(T_419, UInt<1>("h0")) - node T_466 = and(T_434, T_465) - node T_468 = eq(T_419, UInt<1>("h0")) - node T_469 = and(T_444, T_468) - node T_470 = and(T_444, T_419) - node T_471 = and(T_434, T_419) - node T_472 = and(T_442, T_419) - node T_473 = and(T_448, T_419) - node T_474 = cat(T_457, T_455) - node T_475 = cat(T_463, T_466) - node T_476 = cat(T_460, T_475) - node T_477 = cat(T_474, T_476) - node T_478 = cat(T_469, T_470) - node T_479 = cat(T_472, T_473) - node T_480 = cat(T_471, T_479) - node T_481 = cat(T_478, T_480) - node classify_d = cat(T_477, T_481) - node classify_out = mux(in.single, classify_s, classify_d) - inst dcmp of CompareRecFN - dcmp.io is invalid - dcmp.clk <= clk - dcmp.reset <= reset - dcmp.io.a <= in.in1 - dcmp.io.b <= in.in2 - dcmp.io.signaling <= UInt<1>("h1") - node T_486 = not(in.rm) - node T_487 = cat(dcmp.io.lt, dcmp.io.eq) - node T_488 = and(T_486, T_487) - node dcmp_out = neq(T_488, UInt<1>("h0")) - inst d2l of RecFNToIN - d2l.io is invalid - d2l.clk <= clk - d2l.reset <= reset - inst d2w of RecFNToIN_118 - d2w.io is invalid - d2w.clk <= clk - d2w.reset <= reset - d2l.io.in <= in.in1 - d2l.io.roundingMode <= in.rm - node T_493 = bits(in.typ, 0, 0) - node T_494 = not(T_493) - d2l.io.signedOut <= T_494 - d2w.io.in <= in.in1 - d2w.io.roundingMode <= in.rm - node T_495 = bits(in.typ, 0, 0) - node T_496 = not(T_495) - d2w.io.signedOut <= T_496 - node T_497 = bits(in.rm, 0, 0) - node T_498 = mux(T_497, classify_out, unrec_out) - io.out.bits.toint <= T_498 - io.out.bits.store <= unrec_out - io.out.bits.exc <= UInt<1>("h0") - node T_502 = and(in.cmd, UInt<4>("hc")) - node T_503 = eq(UInt<3>("h4"), T_502) - when T_503 : - io.out.bits.toint <= dcmp_out - io.out.bits.exc <= dcmp.io.exceptionFlags - skip - node T_506 = and(in.cmd, UInt<4>("hc")) - node T_507 = eq(UInt<4>("h8"), T_506) - when T_507 : - node T_508 = bits(in.typ, 1, 1) - node T_509 = asSInt(d2l.io.out) - node T_510 = asSInt(d2w.io.out) - node T_511 = mux(T_508, T_509, T_510) - node T_512 = asUInt(T_511) - io.out.bits.toint <= T_512 - node T_513 = bits(in.typ, 1, 1) - node T_514 = mux(T_513, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags) - node T_515 = bits(T_514, 2, 1) - node T_517 = neq(T_515, UInt<1>("h0")) - node T_519 = bits(T_514, 0, 0) - node T_520 = cat(UInt<3>("h0"), T_519) - node T_521 = cat(T_517, T_520) - io.out.bits.exc <= T_521 - skip - io.out.valid <= valid - io.out.bits.lt <= dcmp.io.lt - io.as_double <- in - module INToRecFN : - input clk : Clock - input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io is invalid - node T_9 = bits(io.in, 63, 63) - node sign = and(io.signedIn, T_9) - node T_12 = sub(UInt<1>("h0"), io.in) - node T_13 = tail(T_12, 1) - node absIn = mux(sign, T_13, io.in) - node T_15 = shl(absIn, 0) - node T_16 = bits(T_15, 63, 63) - node T_18 = bits(T_15, 62, 62) - node T_20 = bits(T_15, 61, 61) - node T_22 = bits(T_15, 60, 60) - node T_24 = bits(T_15, 59, 59) - node T_26 = bits(T_15, 58, 58) - node T_28 = bits(T_15, 57, 57) - node T_30 = bits(T_15, 56, 56) - node T_32 = bits(T_15, 55, 55) - node T_34 = bits(T_15, 54, 54) - node T_36 = bits(T_15, 53, 53) - node T_38 = bits(T_15, 52, 52) - node T_40 = bits(T_15, 51, 51) - node T_42 = bits(T_15, 50, 50) - node T_44 = bits(T_15, 49, 49) - node T_46 = bits(T_15, 48, 48) - node T_48 = bits(T_15, 47, 47) - node T_50 = bits(T_15, 46, 46) - node T_52 = bits(T_15, 45, 45) - node T_54 = bits(T_15, 44, 44) - node T_56 = bits(T_15, 43, 43) - node T_58 = bits(T_15, 42, 42) - node T_60 = bits(T_15, 41, 41) - node T_62 = bits(T_15, 40, 40) - node T_64 = bits(T_15, 39, 39) - node T_66 = bits(T_15, 38, 38) - node T_68 = bits(T_15, 37, 37) - node T_70 = bits(T_15, 36, 36) - node T_72 = bits(T_15, 35, 35) - node T_74 = bits(T_15, 34, 34) - node T_76 = bits(T_15, 33, 33) - node T_78 = bits(T_15, 32, 32) - node T_80 = bits(T_15, 31, 31) - node T_82 = bits(T_15, 30, 30) - node T_84 = bits(T_15, 29, 29) - node T_86 = bits(T_15, 28, 28) - node T_88 = bits(T_15, 27, 27) - node T_90 = bits(T_15, 26, 26) - node T_92 = bits(T_15, 25, 25) - node T_94 = bits(T_15, 24, 24) - node T_96 = bits(T_15, 23, 23) - node T_98 = bits(T_15, 22, 22) - node T_100 = bits(T_15, 21, 21) - node T_102 = bits(T_15, 20, 20) - node T_104 = bits(T_15, 19, 19) - node T_106 = bits(T_15, 18, 18) - node T_108 = bits(T_15, 17, 17) - node T_110 = bits(T_15, 16, 16) - node T_112 = bits(T_15, 15, 15) - node T_114 = bits(T_15, 14, 14) - node T_116 = bits(T_15, 13, 13) - node T_118 = bits(T_15, 12, 12) - node T_120 = bits(T_15, 11, 11) - node T_122 = bits(T_15, 10, 10) - node T_124 = bits(T_15, 9, 9) - node T_126 = bits(T_15, 8, 8) - node T_128 = bits(T_15, 7, 7) - node T_130 = bits(T_15, 6, 6) - node T_132 = bits(T_15, 5, 5) - node T_134 = bits(T_15, 4, 4) - node T_136 = bits(T_15, 3, 3) - node T_138 = bits(T_15, 2, 2) - node T_140 = bits(T_15, 1, 1) - node T_141 = shl(T_140, 0) - node T_142 = mux(T_138, UInt<2>("h2"), T_141) - node T_143 = mux(T_136, UInt<2>("h3"), T_142) - node T_144 = mux(T_134, UInt<3>("h4"), T_143) - node T_145 = mux(T_132, UInt<3>("h5"), T_144) - node T_146 = mux(T_130, UInt<3>("h6"), T_145) - node T_147 = mux(T_128, UInt<3>("h7"), T_146) - node T_148 = mux(T_126, UInt<4>("h8"), T_147) - node T_149 = mux(T_124, UInt<4>("h9"), T_148) - node T_150 = mux(T_122, UInt<4>("ha"), T_149) - node T_151 = mux(T_120, UInt<4>("hb"), T_150) - node T_152 = mux(T_118, UInt<4>("hc"), T_151) - node T_153 = mux(T_116, UInt<4>("hd"), T_152) - node T_154 = mux(T_114, UInt<4>("he"), T_153) - node T_155 = mux(T_112, UInt<4>("hf"), T_154) - node T_156 = mux(T_110, UInt<5>("h10"), T_155) - node T_157 = mux(T_108, UInt<5>("h11"), T_156) - node T_158 = mux(T_106, UInt<5>("h12"), T_157) - node T_159 = mux(T_104, UInt<5>("h13"), T_158) - node T_160 = mux(T_102, UInt<5>("h14"), T_159) - node T_161 = mux(T_100, UInt<5>("h15"), T_160) - node T_162 = mux(T_98, UInt<5>("h16"), T_161) - node T_163 = mux(T_96, UInt<5>("h17"), T_162) - node T_164 = mux(T_94, UInt<5>("h18"), T_163) - node T_165 = mux(T_92, UInt<5>("h19"), T_164) - node T_166 = mux(T_90, UInt<5>("h1a"), T_165) - node T_167 = mux(T_88, UInt<5>("h1b"), T_166) - node T_168 = mux(T_86, UInt<5>("h1c"), T_167) - node T_169 = mux(T_84, UInt<5>("h1d"), T_168) - node T_170 = mux(T_82, UInt<5>("h1e"), T_169) - node T_171 = mux(T_80, UInt<5>("h1f"), T_170) - node T_172 = mux(T_78, UInt<6>("h20"), T_171) - node T_173 = mux(T_76, UInt<6>("h21"), T_172) - node T_174 = mux(T_74, UInt<6>("h22"), T_173) - node T_175 = mux(T_72, UInt<6>("h23"), T_174) - node T_176 = mux(T_70, UInt<6>("h24"), T_175) - node T_177 = mux(T_68, UInt<6>("h25"), T_176) - node T_178 = mux(T_66, UInt<6>("h26"), T_177) - node T_179 = mux(T_64, UInt<6>("h27"), T_178) - node T_180 = mux(T_62, UInt<6>("h28"), T_179) - node T_181 = mux(T_60, UInt<6>("h29"), T_180) - node T_182 = mux(T_58, UInt<6>("h2a"), T_181) - node T_183 = mux(T_56, UInt<6>("h2b"), T_182) - node T_184 = mux(T_54, UInt<6>("h2c"), T_183) - node T_185 = mux(T_52, UInt<6>("h2d"), T_184) - node T_186 = mux(T_50, UInt<6>("h2e"), T_185) - node T_187 = mux(T_48, UInt<6>("h2f"), T_186) - node T_188 = mux(T_46, UInt<6>("h30"), T_187) - node T_189 = mux(T_44, UInt<6>("h31"), T_188) - node T_190 = mux(T_42, UInt<6>("h32"), T_189) - node T_191 = mux(T_40, UInt<6>("h33"), T_190) - node T_192 = mux(T_38, UInt<6>("h34"), T_191) - node T_193 = mux(T_36, UInt<6>("h35"), T_192) - node T_194 = mux(T_34, UInt<6>("h36"), T_193) - node T_195 = mux(T_32, UInt<6>("h37"), T_194) - node T_196 = mux(T_30, UInt<6>("h38"), T_195) - node T_197 = mux(T_28, UInt<6>("h39"), T_196) - node T_198 = mux(T_26, UInt<6>("h3a"), T_197) - node T_199 = mux(T_24, UInt<6>("h3b"), T_198) - node T_200 = mux(T_22, UInt<6>("h3c"), T_199) - node T_201 = mux(T_20, UInt<6>("h3d"), T_200) - node T_202 = mux(T_18, UInt<6>("h3e"), T_201) - node T_203 = mux(T_16, UInt<6>("h3f"), T_202) - node normCount = not(T_203) - node T_205 = dshl(absIn, normCount) - node normAbsIn = bits(T_205, 63, 0) - node T_208 = bits(normAbsIn, 40, 39) - node T_209 = bits(normAbsIn, 38, 0) - node T_211 = neq(T_209, UInt<1>("h0")) - node roundBits = cat(T_208, T_211) - node T_213 = bits(roundBits, 1, 0) - node roundInexact = neq(T_213, UInt<1>("h0")) - node T_216 = eq(io.roundingMode, UInt<2>("h0")) - node T_217 = bits(roundBits, 2, 1) - node T_218 = not(T_217) - node T_220 = eq(T_218, UInt<1>("h0")) - node T_221 = bits(roundBits, 1, 0) - node T_222 = not(T_221) - node T_224 = eq(T_222, UInt<1>("h0")) - node T_225 = or(T_220, T_224) - node T_227 = mux(T_216, T_225, UInt<1>("h0")) - node T_228 = eq(io.roundingMode, UInt<2>("h2")) - node T_229 = and(sign, roundInexact) - node T_231 = mux(T_228, T_229, UInt<1>("h0")) - node T_232 = or(T_227, T_231) - node T_233 = eq(io.roundingMode, UInt<2>("h3")) - node T_235 = eq(sign, UInt<1>("h0")) - node T_236 = and(T_235, roundInexact) - node T_238 = mux(T_233, T_236, UInt<1>("h0")) - node round = or(T_232, T_238) - node T_241 = bits(normAbsIn, 63, 40) - node unroundedNorm = cat(UInt<1>("h0"), T_241) - node T_245 = add(unroundedNorm, UInt<1>("h1")) - node T_246 = tail(T_245, 1) - node roundedNorm = mux(round, T_246, unroundedNorm) - node T_249 = not(normCount) - node unroundedExp = cat(UInt<1>("h0"), T_249) - node T_253 = cat(UInt<1>("h0"), unroundedExp) - node T_254 = bits(roundedNorm, 24, 24) - node T_255 = add(T_253, T_254) - node roundedExp = tail(T_255, 1) - node T_258 = bits(normAbsIn, 63, 63) - node T_260 = bits(roundedExp, 7, 0) - node T_261 = mux(UInt<1>("h0"), UInt<8>("h80"), T_260) - node expOut = cat(T_258, T_261) - node overflow = or(UInt<1>("h0"), UInt<1>("h0")) - node inexact = or(roundInexact, overflow) - node T_265 = bits(roundedNorm, 22, 0) - node T_266 = cat(expOut, T_265) - node T_267 = cat(sign, T_266) - io.out <= T_267 - node T_270 = cat(UInt<2>("h0"), overflow) - node T_271 = cat(UInt<1>("h0"), inexact) - node T_272 = cat(T_270, T_271) - io.exceptionFlags <= T_272 - module INToRecFN_119 : - input clk : Clock - input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io is invalid - node T_9 = bits(io.in, 63, 63) - node sign = and(io.signedIn, T_9) - node T_12 = sub(UInt<1>("h0"), io.in) - node T_13 = tail(T_12, 1) - node absIn = mux(sign, T_13, io.in) - node T_15 = shl(absIn, 0) - node T_16 = bits(T_15, 63, 63) - node T_18 = bits(T_15, 62, 62) - node T_20 = bits(T_15, 61, 61) - node T_22 = bits(T_15, 60, 60) - node T_24 = bits(T_15, 59, 59) - node T_26 = bits(T_15, 58, 58) - node T_28 = bits(T_15, 57, 57) - node T_30 = bits(T_15, 56, 56) - node T_32 = bits(T_15, 55, 55) - node T_34 = bits(T_15, 54, 54) - node T_36 = bits(T_15, 53, 53) - node T_38 = bits(T_15, 52, 52) - node T_40 = bits(T_15, 51, 51) - node T_42 = bits(T_15, 50, 50) - node T_44 = bits(T_15, 49, 49) - node T_46 = bits(T_15, 48, 48) - node T_48 = bits(T_15, 47, 47) - node T_50 = bits(T_15, 46, 46) - node T_52 = bits(T_15, 45, 45) - node T_54 = bits(T_15, 44, 44) - node T_56 = bits(T_15, 43, 43) - node T_58 = bits(T_15, 42, 42) - node T_60 = bits(T_15, 41, 41) - node T_62 = bits(T_15, 40, 40) - node T_64 = bits(T_15, 39, 39) - node T_66 = bits(T_15, 38, 38) - node T_68 = bits(T_15, 37, 37) - node T_70 = bits(T_15, 36, 36) - node T_72 = bits(T_15, 35, 35) - node T_74 = bits(T_15, 34, 34) - node T_76 = bits(T_15, 33, 33) - node T_78 = bits(T_15, 32, 32) - node T_80 = bits(T_15, 31, 31) - node T_82 = bits(T_15, 30, 30) - node T_84 = bits(T_15, 29, 29) - node T_86 = bits(T_15, 28, 28) - node T_88 = bits(T_15, 27, 27) - node T_90 = bits(T_15, 26, 26) - node T_92 = bits(T_15, 25, 25) - node T_94 = bits(T_15, 24, 24) - node T_96 = bits(T_15, 23, 23) - node T_98 = bits(T_15, 22, 22) - node T_100 = bits(T_15, 21, 21) - node T_102 = bits(T_15, 20, 20) - node T_104 = bits(T_15, 19, 19) - node T_106 = bits(T_15, 18, 18) - node T_108 = bits(T_15, 17, 17) - node T_110 = bits(T_15, 16, 16) - node T_112 = bits(T_15, 15, 15) - node T_114 = bits(T_15, 14, 14) - node T_116 = bits(T_15, 13, 13) - node T_118 = bits(T_15, 12, 12) - node T_120 = bits(T_15, 11, 11) - node T_122 = bits(T_15, 10, 10) - node T_124 = bits(T_15, 9, 9) - node T_126 = bits(T_15, 8, 8) - node T_128 = bits(T_15, 7, 7) - node T_130 = bits(T_15, 6, 6) - node T_132 = bits(T_15, 5, 5) - node T_134 = bits(T_15, 4, 4) - node T_136 = bits(T_15, 3, 3) - node T_138 = bits(T_15, 2, 2) - node T_140 = bits(T_15, 1, 1) - node T_141 = shl(T_140, 0) - node T_142 = mux(T_138, UInt<2>("h2"), T_141) - node T_143 = mux(T_136, UInt<2>("h3"), T_142) - node T_144 = mux(T_134, UInt<3>("h4"), T_143) - node T_145 = mux(T_132, UInt<3>("h5"), T_144) - node T_146 = mux(T_130, UInt<3>("h6"), T_145) - node T_147 = mux(T_128, UInt<3>("h7"), T_146) - node T_148 = mux(T_126, UInt<4>("h8"), T_147) - node T_149 = mux(T_124, UInt<4>("h9"), T_148) - node T_150 = mux(T_122, UInt<4>("ha"), T_149) - node T_151 = mux(T_120, UInt<4>("hb"), T_150) - node T_152 = mux(T_118, UInt<4>("hc"), T_151) - node T_153 = mux(T_116, UInt<4>("hd"), T_152) - node T_154 = mux(T_114, UInt<4>("he"), T_153) - node T_155 = mux(T_112, UInt<4>("hf"), T_154) - node T_156 = mux(T_110, UInt<5>("h10"), T_155) - node T_157 = mux(T_108, UInt<5>("h11"), T_156) - node T_158 = mux(T_106, UInt<5>("h12"), T_157) - node T_159 = mux(T_104, UInt<5>("h13"), T_158) - node T_160 = mux(T_102, UInt<5>("h14"), T_159) - node T_161 = mux(T_100, UInt<5>("h15"), T_160) - node T_162 = mux(T_98, UInt<5>("h16"), T_161) - node T_163 = mux(T_96, UInt<5>("h17"), T_162) - node T_164 = mux(T_94, UInt<5>("h18"), T_163) - node T_165 = mux(T_92, UInt<5>("h19"), T_164) - node T_166 = mux(T_90, UInt<5>("h1a"), T_165) - node T_167 = mux(T_88, UInt<5>("h1b"), T_166) - node T_168 = mux(T_86, UInt<5>("h1c"), T_167) - node T_169 = mux(T_84, UInt<5>("h1d"), T_168) - node T_170 = mux(T_82, UInt<5>("h1e"), T_169) - node T_171 = mux(T_80, UInt<5>("h1f"), T_170) - node T_172 = mux(T_78, UInt<6>("h20"), T_171) - node T_173 = mux(T_76, UInt<6>("h21"), T_172) - node T_174 = mux(T_74, UInt<6>("h22"), T_173) - node T_175 = mux(T_72, UInt<6>("h23"), T_174) - node T_176 = mux(T_70, UInt<6>("h24"), T_175) - node T_177 = mux(T_68, UInt<6>("h25"), T_176) - node T_178 = mux(T_66, UInt<6>("h26"), T_177) - node T_179 = mux(T_64, UInt<6>("h27"), T_178) - node T_180 = mux(T_62, UInt<6>("h28"), T_179) - node T_181 = mux(T_60, UInt<6>("h29"), T_180) - node T_182 = mux(T_58, UInt<6>("h2a"), T_181) - node T_183 = mux(T_56, UInt<6>("h2b"), T_182) - node T_184 = mux(T_54, UInt<6>("h2c"), T_183) - node T_185 = mux(T_52, UInt<6>("h2d"), T_184) - node T_186 = mux(T_50, UInt<6>("h2e"), T_185) - node T_187 = mux(T_48, UInt<6>("h2f"), T_186) - node T_188 = mux(T_46, UInt<6>("h30"), T_187) - node T_189 = mux(T_44, UInt<6>("h31"), T_188) - node T_190 = mux(T_42, UInt<6>("h32"), T_189) - node T_191 = mux(T_40, UInt<6>("h33"), T_190) - node T_192 = mux(T_38, UInt<6>("h34"), T_191) - node T_193 = mux(T_36, UInt<6>("h35"), T_192) - node T_194 = mux(T_34, UInt<6>("h36"), T_193) - node T_195 = mux(T_32, UInt<6>("h37"), T_194) - node T_196 = mux(T_30, UInt<6>("h38"), T_195) - node T_197 = mux(T_28, UInt<6>("h39"), T_196) - node T_198 = mux(T_26, UInt<6>("h3a"), T_197) - node T_199 = mux(T_24, UInt<6>("h3b"), T_198) - node T_200 = mux(T_22, UInt<6>("h3c"), T_199) - node T_201 = mux(T_20, UInt<6>("h3d"), T_200) - node T_202 = mux(T_18, UInt<6>("h3e"), T_201) - node T_203 = mux(T_16, UInt<6>("h3f"), T_202) - node normCount = not(T_203) - node T_205 = dshl(absIn, normCount) - node normAbsIn = bits(T_205, 63, 0) - node T_208 = bits(normAbsIn, 11, 10) - node T_209 = bits(normAbsIn, 9, 0) - node T_211 = neq(T_209, UInt<1>("h0")) - node roundBits = cat(T_208, T_211) - node T_213 = bits(roundBits, 1, 0) - node roundInexact = neq(T_213, UInt<1>("h0")) - node T_216 = eq(io.roundingMode, UInt<2>("h0")) - node T_217 = bits(roundBits, 2, 1) - node T_218 = not(T_217) - node T_220 = eq(T_218, UInt<1>("h0")) - node T_221 = bits(roundBits, 1, 0) - node T_222 = not(T_221) - node T_224 = eq(T_222, UInt<1>("h0")) - node T_225 = or(T_220, T_224) - node T_227 = mux(T_216, T_225, UInt<1>("h0")) - node T_228 = eq(io.roundingMode, UInt<2>("h2")) - node T_229 = and(sign, roundInexact) - node T_231 = mux(T_228, T_229, UInt<1>("h0")) - node T_232 = or(T_227, T_231) - node T_233 = eq(io.roundingMode, UInt<2>("h3")) - node T_235 = eq(sign, UInt<1>("h0")) - node T_236 = and(T_235, roundInexact) - node T_238 = mux(T_233, T_236, UInt<1>("h0")) - node round = or(T_232, T_238) - node T_241 = bits(normAbsIn, 63, 11) - node unroundedNorm = cat(UInt<1>("h0"), T_241) - node T_245 = add(unroundedNorm, UInt<1>("h1")) - node T_246 = tail(T_245, 1) - node roundedNorm = mux(round, T_246, unroundedNorm) - node T_249 = not(normCount) - node unroundedExp = cat(UInt<4>("h0"), T_249) - node T_253 = cat(UInt<1>("h0"), unroundedExp) - node T_254 = bits(roundedNorm, 53, 53) - node T_255 = add(T_253, T_254) - node roundedExp = tail(T_255, 1) - node T_258 = bits(normAbsIn, 63, 63) - node T_260 = bits(roundedExp, 10, 0) - node T_261 = mux(UInt<1>("h0"), UInt<11>("h400"), T_260) - node expOut = cat(T_258, T_261) - node overflow = or(UInt<1>("h0"), UInt<1>("h0")) - node inexact = or(roundInexact, overflow) - node T_265 = bits(roundedNorm, 51, 0) - node T_266 = cat(expOut, T_265) - node T_267 = cat(sign, T_266) - io.out <= T_267 - node T_270 = cat(UInt<2>("h0"), overflow) - node T_271 = cat(UInt<1>("h0"), inexact) - node T_272 = cat(T_270, T_271) - io.exceptionFlags <= T_272 - module IntToFP : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} - io is invalid - reg T_136 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_136 <= io.in.valid - reg T_137 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : - reset => (UInt<1>("h0"), T_137) - when io.in.valid : - T_137 <- io.in.bits - skip - wire in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in is invalid - in.valid <= T_136 - in.bits <- T_137 - wire mux : { data : UInt<65>, exc : UInt<5>} - mux is invalid - mux.exc <= UInt<1>("h0") - node T_263 = bits(in.bits.in1, 63, 63) - node T_264 = bits(in.bits.in1, 62, 52) - node T_265 = bits(in.bits.in1, 51, 0) - node T_267 = eq(T_264, UInt<1>("h0")) - node T_269 = eq(T_265, UInt<1>("h0")) - node T_270 = and(T_267, T_269) - node T_271 = shl(T_265, 12) - node T_272 = bits(T_271, 63, 63) - node T_274 = bits(T_271, 62, 62) - node T_276 = bits(T_271, 61, 61) - node T_278 = bits(T_271, 60, 60) - node T_280 = bits(T_271, 59, 59) - node T_282 = bits(T_271, 58, 58) - node T_284 = bits(T_271, 57, 57) - node T_286 = bits(T_271, 56, 56) - node T_288 = bits(T_271, 55, 55) - node T_290 = bits(T_271, 54, 54) - node T_292 = bits(T_271, 53, 53) - node T_294 = bits(T_271, 52, 52) - node T_296 = bits(T_271, 51, 51) - node T_298 = bits(T_271, 50, 50) - node T_300 = bits(T_271, 49, 49) - node T_302 = bits(T_271, 48, 48) - node T_304 = bits(T_271, 47, 47) - node T_306 = bits(T_271, 46, 46) - node T_308 = bits(T_271, 45, 45) - node T_310 = bits(T_271, 44, 44) - node T_312 = bits(T_271, 43, 43) - node T_314 = bits(T_271, 42, 42) - node T_316 = bits(T_271, 41, 41) - node T_318 = bits(T_271, 40, 40) - node T_320 = bits(T_271, 39, 39) - node T_322 = bits(T_271, 38, 38) - node T_324 = bits(T_271, 37, 37) - node T_326 = bits(T_271, 36, 36) - node T_328 = bits(T_271, 35, 35) - node T_330 = bits(T_271, 34, 34) - node T_332 = bits(T_271, 33, 33) - node T_334 = bits(T_271, 32, 32) - node T_336 = bits(T_271, 31, 31) - node T_338 = bits(T_271, 30, 30) - node T_340 = bits(T_271, 29, 29) - node T_342 = bits(T_271, 28, 28) - node T_344 = bits(T_271, 27, 27) - node T_346 = bits(T_271, 26, 26) - node T_348 = bits(T_271, 25, 25) - node T_350 = bits(T_271, 24, 24) - node T_352 = bits(T_271, 23, 23) - node T_354 = bits(T_271, 22, 22) - node T_356 = bits(T_271, 21, 21) - node T_358 = bits(T_271, 20, 20) - node T_360 = bits(T_271, 19, 19) - node T_362 = bits(T_271, 18, 18) - node T_364 = bits(T_271, 17, 17) - node T_366 = bits(T_271, 16, 16) - node T_368 = bits(T_271, 15, 15) - node T_370 = bits(T_271, 14, 14) - node T_372 = bits(T_271, 13, 13) - node T_374 = bits(T_271, 12, 12) - node T_376 = bits(T_271, 11, 11) - node T_378 = bits(T_271, 10, 10) - node T_380 = bits(T_271, 9, 9) - node T_382 = bits(T_271, 8, 8) - node T_384 = bits(T_271, 7, 7) - node T_386 = bits(T_271, 6, 6) - node T_388 = bits(T_271, 5, 5) - node T_390 = bits(T_271, 4, 4) - node T_392 = bits(T_271, 3, 3) - node T_394 = bits(T_271, 2, 2) - node T_396 = bits(T_271, 1, 1) - node T_397 = shl(T_396, 0) - node T_398 = mux(T_394, UInt<2>("h2"), T_397) - node T_399 = mux(T_392, UInt<2>("h3"), T_398) - node T_400 = mux(T_390, UInt<3>("h4"), T_399) - node T_401 = mux(T_388, UInt<3>("h5"), T_400) - node T_402 = mux(T_386, UInt<3>("h6"), T_401) - node T_403 = mux(T_384, UInt<3>("h7"), T_402) - node T_404 = mux(T_382, UInt<4>("h8"), T_403) - node T_405 = mux(T_380, UInt<4>("h9"), T_404) - node T_406 = mux(T_378, UInt<4>("ha"), T_405) - node T_407 = mux(T_376, UInt<4>("hb"), T_406) - node T_408 = mux(T_374, UInt<4>("hc"), T_407) - node T_409 = mux(T_372, UInt<4>("hd"), T_408) - node T_410 = mux(T_370, UInt<4>("he"), T_409) - node T_411 = mux(T_368, UInt<4>("hf"), T_410) - node T_412 = mux(T_366, UInt<5>("h10"), T_411) - node T_413 = mux(T_364, UInt<5>("h11"), T_412) - node T_414 = mux(T_362, UInt<5>("h12"), T_413) - node T_415 = mux(T_360, UInt<5>("h13"), T_414) - node T_416 = mux(T_358, UInt<5>("h14"), T_415) - node T_417 = mux(T_356, UInt<5>("h15"), T_416) - node T_418 = mux(T_354, UInt<5>("h16"), T_417) - node T_419 = mux(T_352, UInt<5>("h17"), T_418) - node T_420 = mux(T_350, UInt<5>("h18"), T_419) - node T_421 = mux(T_348, UInt<5>("h19"), T_420) - node T_422 = mux(T_346, UInt<5>("h1a"), T_421) - node T_423 = mux(T_344, UInt<5>("h1b"), T_422) - node T_424 = mux(T_342, UInt<5>("h1c"), T_423) - node T_425 = mux(T_340, UInt<5>("h1d"), T_424) - node T_426 = mux(T_338, UInt<5>("h1e"), T_425) - node T_427 = mux(T_336, UInt<5>("h1f"), T_426) - node T_428 = mux(T_334, UInt<6>("h20"), T_427) - node T_429 = mux(T_332, UInt<6>("h21"), T_428) - node T_430 = mux(T_330, UInt<6>("h22"), T_429) - node T_431 = mux(T_328, UInt<6>("h23"), T_430) - node T_432 = mux(T_326, UInt<6>("h24"), T_431) - node T_433 = mux(T_324, UInt<6>("h25"), T_432) - node T_434 = mux(T_322, UInt<6>("h26"), T_433) - node T_435 = mux(T_320, UInt<6>("h27"), T_434) - node T_436 = mux(T_318, UInt<6>("h28"), T_435) - node T_437 = mux(T_316, UInt<6>("h29"), T_436) - node T_438 = mux(T_314, UInt<6>("h2a"), T_437) - node T_439 = mux(T_312, UInt<6>("h2b"), T_438) - node T_440 = mux(T_310, UInt<6>("h2c"), T_439) - node T_441 = mux(T_308, UInt<6>("h2d"), T_440) - node T_442 = mux(T_306, UInt<6>("h2e"), T_441) - node T_443 = mux(T_304, UInt<6>("h2f"), T_442) - node T_444 = mux(T_302, UInt<6>("h30"), T_443) - node T_445 = mux(T_300, UInt<6>("h31"), T_444) - node T_446 = mux(T_298, UInt<6>("h32"), T_445) - node T_447 = mux(T_296, UInt<6>("h33"), T_446) - node T_448 = mux(T_294, UInt<6>("h34"), T_447) - node T_449 = mux(T_292, UInt<6>("h35"), T_448) - node T_450 = mux(T_290, UInt<6>("h36"), T_449) - node T_451 = mux(T_288, UInt<6>("h37"), T_450) - node T_452 = mux(T_286, UInt<6>("h38"), T_451) - node T_453 = mux(T_284, UInt<6>("h39"), T_452) - node T_454 = mux(T_282, UInt<6>("h3a"), T_453) - node T_455 = mux(T_280, UInt<6>("h3b"), T_454) - node T_456 = mux(T_278, UInt<6>("h3c"), T_455) - node T_457 = mux(T_276, UInt<6>("h3d"), T_456) - node T_458 = mux(T_274, UInt<6>("h3e"), T_457) - node T_459 = mux(T_272, UInt<6>("h3f"), T_458) - node T_460 = not(T_459) - node T_461 = dshl(T_265, T_460) - node T_462 = bits(T_461, 50, 0) - node T_464 = cat(T_462, UInt<1>("h0")) - node T_467 = sub(UInt<12>("h0"), UInt<1>("h1")) - node T_468 = tail(T_467, 1) - node T_469 = xor(T_460, T_468) - node T_470 = mux(T_267, T_469, T_264) - node T_474 = mux(T_267, UInt<2>("h2"), UInt<1>("h1")) - node T_475 = or(UInt<11>("h400"), T_474) - node T_476 = add(T_470, T_475) - node T_477 = tail(T_476, 1) - node T_478 = bits(T_477, 11, 10) - node T_480 = eq(T_478, UInt<2>("h3")) - node T_482 = eq(T_269, UInt<1>("h0")) - node T_483 = and(T_480, T_482) - node T_485 = sub(UInt<3>("h0"), T_270) - node T_486 = tail(T_485, 1) - node T_487 = shl(T_486, 9) - node T_488 = not(T_487) - node T_489 = and(T_477, T_488) - node T_490 = shl(T_483, 9) - node T_491 = or(T_489, T_490) - node T_492 = mux(T_267, T_464, T_265) - node T_493 = cat(T_491, T_492) - node T_494 = cat(T_263, T_493) - mux.data <= T_494 - when in.bits.single : - node T_496 = bits(in.bits.in1, 31, 31) - node T_497 = bits(in.bits.in1, 30, 23) - node T_498 = bits(in.bits.in1, 22, 0) - node T_500 = eq(T_497, UInt<1>("h0")) - node T_502 = eq(T_498, UInt<1>("h0")) - node T_503 = and(T_500, T_502) - node T_504 = shl(T_498, 9) - node T_505 = bits(T_504, 31, 31) - node T_507 = bits(T_504, 30, 30) - node T_509 = bits(T_504, 29, 29) - node T_511 = bits(T_504, 28, 28) - node T_513 = bits(T_504, 27, 27) - node T_515 = bits(T_504, 26, 26) - node T_517 = bits(T_504, 25, 25) - node T_519 = bits(T_504, 24, 24) - node T_521 = bits(T_504, 23, 23) - node T_523 = bits(T_504, 22, 22) - node T_525 = bits(T_504, 21, 21) - node T_527 = bits(T_504, 20, 20) - node T_529 = bits(T_504, 19, 19) - node T_531 = bits(T_504, 18, 18) - node T_533 = bits(T_504, 17, 17) - node T_535 = bits(T_504, 16, 16) - node T_537 = bits(T_504, 15, 15) - node T_539 = bits(T_504, 14, 14) - node T_541 = bits(T_504, 13, 13) - node T_543 = bits(T_504, 12, 12) - node T_545 = bits(T_504, 11, 11) - node T_547 = bits(T_504, 10, 10) - node T_549 = bits(T_504, 9, 9) - node T_551 = bits(T_504, 8, 8) - node T_553 = bits(T_504, 7, 7) - node T_555 = bits(T_504, 6, 6) - node T_557 = bits(T_504, 5, 5) - node T_559 = bits(T_504, 4, 4) - node T_561 = bits(T_504, 3, 3) - node T_563 = bits(T_504, 2, 2) - node T_565 = bits(T_504, 1, 1) - node T_566 = shl(T_565, 0) - node T_567 = mux(T_563, UInt<2>("h2"), T_566) - node T_568 = mux(T_561, UInt<2>("h3"), T_567) - node T_569 = mux(T_559, UInt<3>("h4"), T_568) - node T_570 = mux(T_557, UInt<3>("h5"), T_569) - node T_571 = mux(T_555, UInt<3>("h6"), T_570) - node T_572 = mux(T_553, UInt<3>("h7"), T_571) - node T_573 = mux(T_551, UInt<4>("h8"), T_572) - node T_574 = mux(T_549, UInt<4>("h9"), T_573) - node T_575 = mux(T_547, UInt<4>("ha"), T_574) - node T_576 = mux(T_545, UInt<4>("hb"), T_575) - node T_577 = mux(T_543, UInt<4>("hc"), T_576) - node T_578 = mux(T_541, UInt<4>("hd"), T_577) - node T_579 = mux(T_539, UInt<4>("he"), T_578) - node T_580 = mux(T_537, UInt<4>("hf"), T_579) - node T_581 = mux(T_535, UInt<5>("h10"), T_580) - node T_582 = mux(T_533, UInt<5>("h11"), T_581) - node T_583 = mux(T_531, UInt<5>("h12"), T_582) - node T_584 = mux(T_529, UInt<5>("h13"), T_583) - node T_585 = mux(T_527, UInt<5>("h14"), T_584) - node T_586 = mux(T_525, UInt<5>("h15"), T_585) - node T_587 = mux(T_523, UInt<5>("h16"), T_586) - node T_588 = mux(T_521, UInt<5>("h17"), T_587) - node T_589 = mux(T_519, UInt<5>("h18"), T_588) - node T_590 = mux(T_517, UInt<5>("h19"), T_589) - node T_591 = mux(T_515, UInt<5>("h1a"), T_590) - node T_592 = mux(T_513, UInt<5>("h1b"), T_591) - node T_593 = mux(T_511, UInt<5>("h1c"), T_592) - node T_594 = mux(T_509, UInt<5>("h1d"), T_593) - node T_595 = mux(T_507, UInt<5>("h1e"), T_594) - node T_596 = mux(T_505, UInt<5>("h1f"), T_595) - node T_597 = not(T_596) - node T_598 = dshl(T_498, T_597) - node T_599 = bits(T_598, 21, 0) - node T_601 = cat(T_599, UInt<1>("h0")) - node T_604 = sub(UInt<9>("h0"), UInt<1>("h1")) - node T_605 = tail(T_604, 1) - node T_606 = xor(T_597, T_605) - node T_607 = mux(T_500, T_606, T_497) - node T_611 = mux(T_500, UInt<2>("h2"), UInt<1>("h1")) - node T_612 = or(UInt<8>("h80"), T_611) - node T_613 = add(T_607, T_612) - node T_614 = tail(T_613, 1) - node T_615 = bits(T_614, 8, 7) - node T_617 = eq(T_615, UInt<2>("h3")) - node T_619 = eq(T_502, UInt<1>("h0")) - node T_620 = and(T_617, T_619) - node T_622 = sub(UInt<3>("h0"), T_503) - node T_623 = tail(T_622, 1) - node T_624 = shl(T_623, 6) - node T_625 = not(T_624) - node T_626 = and(T_614, T_625) - node T_627 = shl(T_620, 6) - node T_628 = or(T_626, T_627) - node T_629 = mux(T_500, T_601, T_498) - node T_630 = cat(T_628, T_629) - node T_631 = cat(T_496, T_630) - node T_632 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_633 = cat(T_632, T_631) - mux.data <= T_633 - skip - node T_634 = bits(in.bits.typ, 1, 1) - node T_635 = asSInt(in.bits.in1) - node T_636 = bits(in.bits.typ, 0, 0) - node T_637 = bits(in.bits.in1, 31, 0) - node T_638 = cvt(T_637) - node T_639 = bits(in.bits.in1, 31, 0) - node T_640 = asSInt(T_639) - node T_641 = mux(T_636, T_638, T_640) - node longValue = mux(T_634, T_635, T_641) - inst l2s of INToRecFN - l2s.io is invalid - l2s.clk <= clk - l2s.reset <= reset - node T_644 = bits(in.bits.typ, 0, 0) - node T_645 = not(T_644) - l2s.io.signedIn <= T_645 - node T_646 = asUInt(longValue) - l2s.io.in <= T_646 - l2s.io.roundingMode <= in.bits.rm - inst l2d of INToRecFN_119 - l2d.io is invalid - l2d.clk <= clk - l2d.reset <= reset - node T_648 = bits(in.bits.typ, 0, 0) - node T_649 = not(T_648) - l2d.io.signedIn <= T_649 - node T_650 = asUInt(longValue) - l2d.io.in <= T_650 - l2d.io.roundingMode <= in.bits.rm - node T_653 = and(in.bits.cmd, UInt<3>("h4")) - node T_654 = eq(UInt<1>("h0"), T_653) - when T_654 : - when in.bits.single : - node T_656 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_657 = cat(T_656, l2s.io.out) - mux.data <= T_657 - mux.exc <= l2s.io.exceptionFlags - skip - node T_659 = eq(in.bits.single, UInt<1>("h0")) - when T_659 : - mux.data <= l2d.io.out - mux.exc <= l2d.io.exceptionFlags - skip - skip - reg T_662 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_662 <= in.valid - reg T_663 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_663) - when in.valid : - T_663 <- mux - skip - reg T_668 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_668 <= T_662 - reg T_669 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_669) - when T_662 : - T_669 <- T_663 - skip - wire T_680 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} - T_680 is invalid - T_680.valid <= T_668 - T_680.bits <- T_669 - io.out <- T_680 - module RoundRawFNToRecFN : - input clk : Clock - input reset : UInt<1> - output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io is invalid - node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h0")) - node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h1")) - node roundingMode_min = eq(io.roundingMode, UInt<2>("h2")) - node roundingMode_max = eq(io.roundingMode, UInt<2>("h3")) - node T_27 = and(roundingMode_min, io.in.sign) - node T_28 = not(io.in.sign) - node T_29 = and(roundingMode_max, T_28) - node roundMagUp = or(T_27, T_29) - node doShiftSigDown1 = bits(io.in.sig, 26, 26) - node T_33 = lt(io.in.sExp, asSInt(UInt<1>("h0"))) - node T_35 = sub(UInt<25>("h0"), T_33) - node T_36 = tail(T_35, 1) - node T_37 = bits(io.in.sExp, 8, 0) - node T_38 = not(T_37) - node T_40 = dshr(asSInt(UInt<513>("h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_38) - node T_41 = bits(T_40, 130, 106) - node T_42 = bits(T_41, 15, 0) - node T_45 = shl(UInt<8>("hff"), 8) - node T_46 = xor(UInt<16>("hffff"), T_45) - node T_47 = shr(T_42, 8) - node T_48 = and(T_47, T_46) - node T_49 = bits(T_42, 7, 0) - node T_50 = shl(T_49, 8) - node T_51 = not(T_46) - node T_52 = and(T_50, T_51) - node T_53 = or(T_48, T_52) - node T_54 = bits(T_46, 11, 0) - node T_55 = shl(T_54, 4) - node T_56 = xor(T_46, T_55) - node T_57 = shr(T_53, 4) - node T_58 = and(T_57, T_56) - node T_59 = bits(T_53, 11, 0) - node T_60 = shl(T_59, 4) - node T_61 = not(T_56) - node T_62 = and(T_60, T_61) - node T_63 = or(T_58, T_62) - node T_64 = bits(T_56, 13, 0) - node T_65 = shl(T_64, 2) - node T_66 = xor(T_56, T_65) - node T_67 = shr(T_63, 2) - node T_68 = and(T_67, T_66) - node T_69 = bits(T_63, 13, 0) - node T_70 = shl(T_69, 2) - node T_71 = not(T_66) - node T_72 = and(T_70, T_71) - node T_73 = or(T_68, T_72) - node T_74 = bits(T_66, 14, 0) - node T_75 = shl(T_74, 1) - node T_76 = xor(T_66, T_75) - node T_77 = shr(T_73, 1) - node T_78 = and(T_77, T_76) - node T_79 = bits(T_73, 14, 0) - node T_80 = shl(T_79, 1) - node T_81 = not(T_76) - node T_82 = and(T_80, T_81) - node T_83 = or(T_78, T_82) - node T_84 = bits(T_41, 24, 16) - node T_85 = bits(T_84, 7, 0) - node T_88 = shl(UInt<4>("hf"), 4) - node T_89 = xor(UInt<8>("hff"), T_88) - node T_90 = shr(T_85, 4) - node T_91 = and(T_90, T_89) - node T_92 = bits(T_85, 3, 0) - node T_93 = shl(T_92, 4) - node T_94 = not(T_89) - node T_95 = and(T_93, T_94) - node T_96 = or(T_91, T_95) - node T_97 = bits(T_89, 5, 0) - node T_98 = shl(T_97, 2) - node T_99 = xor(T_89, T_98) - node T_100 = shr(T_96, 2) - node T_101 = and(T_100, T_99) - node T_102 = bits(T_96, 5, 0) - node T_103 = shl(T_102, 2) - node T_104 = not(T_99) - node T_105 = and(T_103, T_104) - node T_106 = or(T_101, T_105) - node T_107 = bits(T_99, 6, 0) - node T_108 = shl(T_107, 1) - node T_109 = xor(T_99, T_108) - node T_110 = shr(T_106, 1) - node T_111 = and(T_110, T_109) - node T_112 = bits(T_106, 6, 0) - node T_113 = shl(T_112, 1) - node T_114 = not(T_109) - node T_115 = and(T_113, T_114) - node T_116 = or(T_111, T_115) - node T_117 = bits(T_84, 8, 8) - node T_118 = cat(T_116, T_117) - node T_119 = cat(T_83, T_118) - node T_120 = or(T_36, T_119) - node T_121 = or(T_120, doShiftSigDown1) - node roundMask = cat(T_121, UInt<2>("h3")) - node T_124 = shr(roundMask, 1) - node T_125 = not(T_124) - node roundPosMask = and(T_125, roundMask) - node T_127 = and(io.in.sig, roundPosMask) - node roundPosBit = neq(T_127, UInt<1>("h0")) - node T_130 = shr(roundMask, 1) - node T_131 = and(io.in.sig, T_130) - node anyRoundExtra = neq(T_131, UInt<1>("h0")) - node common_inexact = or(roundPosBit, anyRoundExtra) - node T_135 = and(roundingMode_nearest_even, roundPosBit) - node T_136 = and(roundMagUp, common_inexact) - node T_137 = or(T_135, T_136) - node T_138 = or(io.in.sig, roundMask) - node T_139 = shr(T_138, 2) - node T_141 = add(T_139, UInt<1>("h1")) - node T_142 = tail(T_141, 1) - node T_143 = and(roundingMode_nearest_even, roundPosBit) - node T_144 = not(anyRoundExtra) - node T_145 = and(T_143, T_144) - node T_146 = shr(roundMask, 1) - node T_148 = mux(T_145, T_146, UInt<26>("h0")) - node T_149 = not(T_148) - node T_150 = and(T_142, T_149) - node T_151 = not(roundMask) - node T_152 = and(io.in.sig, T_151) - node T_153 = shr(T_152, 2) - node roundedSig = mux(T_137, T_150, T_153) - node T_155 = shr(roundedSig, 24) - node T_156 = cvt(T_155) - node T_157 = add(io.in.sExp, T_156) - node T_158 = tail(T_157, 1) - node sRoundedExp = asSInt(T_158) - node common_expOut = bits(sRoundedExp, 8, 0) - node T_161 = bits(roundedSig, 23, 1) - node T_162 = bits(roundedSig, 22, 0) - node common_fractOut = mux(doShiftSigDown1, T_161, T_162) - node T_164 = shr(sRoundedExp, 7) - node common_overflow = geq(T_164, asSInt(UInt<3>("h3"))) - node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h6b"))) - node T_171 = mux(doShiftSigDown1, asSInt(UInt<9>("h81")), asSInt(UInt<9>("h82"))) - node T_172 = lt(io.in.sExp, T_171) - node common_underflow = and(common_inexact, T_172) - node isNaNOut = or(io.invalidExc, io.in.isNaN) - node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) - node T_176 = not(isNaNOut) - node T_177 = not(notNaN_isSpecialInfOut) - node T_178 = and(T_176, T_177) - node T_179 = not(io.in.isZero) - node commonCase = and(T_178, T_179) - node overflow = and(commonCase, common_overflow) - node underflow = and(commonCase, common_underflow) - node T_183 = and(commonCase, common_inexact) - node inexact = or(overflow, T_183) - node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node T_186 = and(commonCase, common_totalUnderflow) - node pegMinNonzeroMagOut = and(T_186, roundMagUp) - node T_188 = and(commonCase, overflow) - node T_189 = not(overflow_roundMagUp) - node pegMaxFiniteMagOut = and(T_188, T_189) - node T_191 = and(overflow, overflow_roundMagUp) - node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_191) - node signOut = mux(isNaNOut, UInt<1>("h0"), io.in.sign) - node T_195 = or(io.in.isZero, common_totalUnderflow) - node T_198 = mux(T_195, UInt<9>("h1c0"), UInt<1>("h0")) - node T_199 = not(T_198) - node T_200 = and(common_expOut, T_199) - node T_202 = not(UInt<9>("h6b")) - node T_204 = mux(pegMinNonzeroMagOut, T_202, UInt<1>("h0")) - node T_205 = not(T_204) - node T_206 = and(T_200, T_205) - node T_209 = mux(pegMaxFiniteMagOut, UInt<9>("h80"), UInt<1>("h0")) - node T_210 = not(T_209) - node T_211 = and(T_206, T_210) - node T_214 = mux(notNaN_isInfOut, UInt<9>("h40"), UInt<1>("h0")) - node T_215 = not(T_214) - node T_216 = and(T_211, T_215) - node T_219 = mux(pegMinNonzeroMagOut, UInt<9>("h6b"), UInt<1>("h0")) - node T_220 = or(T_216, T_219) - node T_223 = mux(pegMaxFiniteMagOut, UInt<9>("h17f"), UInt<1>("h0")) - node T_224 = or(T_220, T_223) - node T_227 = mux(notNaN_isInfOut, UInt<9>("h180"), UInt<1>("h0")) - node T_228 = or(T_224, T_227) - node T_231 = mux(isNaNOut, UInt<9>("h1c0"), UInt<1>("h0")) - node expOut = or(T_228, T_231) - node T_233 = and(common_totalUnderflow, roundMagUp) - node T_234 = or(T_233, isNaNOut) - node T_236 = mux(T_234, UInt<1>("h0"), common_fractOut) - node T_238 = sub(UInt<23>("h0"), pegMaxFiniteMagOut) - node T_239 = tail(T_238, 1) - node T_240 = or(T_236, T_239) - node T_241 = shl(isNaNOut, 22) - node fractOut = or(T_240, T_241) - node T_243 = cat(expOut, fractOut) - node T_244 = cat(signOut, T_243) - io.out <= T_244 - node T_245 = cat(io.invalidExc, io.infiniteExc) - node T_246 = cat(underflow, inexact) - node T_247 = cat(overflow, T_246) - node T_248 = cat(T_245, T_247) - io.exceptionFlags <= T_248 - module RecFNToRecFN_121 : - input clk : Clock - input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io is invalid - node T_8 = bits(io.in, 63, 52) - node T_9 = bits(T_8, 11, 10) - node T_11 = eq(T_9, UInt<2>("h3")) - wire T_19 : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - T_19 is invalid - node T_26 = bits(io.in, 64, 64) - T_19.sign <= T_26 - node T_27 = bits(T_8, 9, 9) - node T_28 = and(T_11, T_27) - T_19.isNaN <= T_28 - node T_29 = bits(T_8, 9, 9) - node T_31 = eq(T_29, UInt<1>("h0")) - node T_32 = and(T_11, T_31) - T_19.isInf <= T_32 - node T_33 = bits(T_8, 11, 9) - node T_35 = eq(T_33, UInt<1>("h0")) - T_19.isZero <= T_35 - node T_36 = cvt(T_8) - T_19.sExp <= T_36 - node T_38 = bits(io.in, 51, 0) - node T_40 = cat(T_38, UInt<2>("h0")) - node T_41 = cat(UInt<2>("h1"), T_40) - T_19.sig <= T_41 - node T_43 = add(T_19.sExp, asSInt(UInt<12>("h900"))) - node T_44 = tail(T_43, 1) - node T_45 = asSInt(T_44) - wire outRawFloat : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - outRawFloat is invalid - outRawFloat.sign <= T_19.sign - outRawFloat.isNaN <= T_19.isNaN - outRawFloat.isInf <= T_19.isInf - outRawFloat.isZero <= T_19.isZero - node T_61 = lt(T_45, asSInt(UInt<1>("h0"))) - node T_62 = bits(T_45, 11, 9) - node T_64 = neq(T_62, UInt<1>("h0")) - node T_66 = cat(UInt<1>("h1"), UInt<1>("h1")) - node T_67 = cat(T_66, T_66) - node T_68 = cat(T_66, T_67) - node T_69 = cat(UInt<1>("h1"), T_68) - node T_71 = cat(T_69, UInt<2>("h0")) - node T_72 = bits(T_45, 8, 0) - node T_73 = mux(T_64, T_71, T_72) - node T_74 = cat(T_61, T_73) - node T_75 = asSInt(T_74) - outRawFloat.sExp <= T_75 - node T_76 = bits(T_19.sig, 55, 30) - node T_77 = bits(T_19.sig, 29, 0) - node T_79 = neq(T_77, UInt<1>("h0")) - node T_80 = cat(T_76, T_79) - outRawFloat.sig <= T_80 - node T_81 = bits(outRawFloat.sig, 24, 24) - node T_83 = eq(T_81, UInt<1>("h0")) - node invalidExc = and(outRawFloat.isNaN, T_83) - inst T_85 of RoundRawFNToRecFN - T_85.io is invalid - T_85.clk <= clk - T_85.reset <= reset - T_85.io.invalidExc <= invalidExc - T_85.io.infiniteExc <= UInt<1>("h0") - T_85.io.in <- outRawFloat - T_85.io.roundingMode <= io.roundingMode - io.out <= T_85.io.out - io.exceptionFlags <= T_85.io.exceptionFlags - module FPToFP : - input clk : Clock - input reset : UInt<1> - output io : {flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} - io is invalid - reg T_137 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_137 <= io.in.valid - reg T_138 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : - reset => (UInt<1>("h0"), T_138) - when io.in.valid : - T_138 <- io.in.bits - skip - wire in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in is invalid - in.valid <= T_137 - in.bits <- T_138 - node T_259 = and(in.bits.cmd, UInt<3>("h5")) - node isSgnj = eq(UInt<3>("h4"), T_259) - node T_261 = and(in.bits.single, isSgnj) - node T_262 = bits(in.bits.rm, 1, 1) - node T_264 = eq(T_261, UInt<1>("h0")) - node T_265 = or(T_262, T_264) - node T_266 = bits(in.bits.in1, 32, 32) - node T_267 = bits(in.bits.rm, 0, 0) - node T_268 = mux(T_265, T_266, T_267) - node T_269 = bits(in.bits.in2, 32, 32) - node T_270 = and(T_261, T_269) - node sign_s = xor(T_268, T_270) - node T_273 = eq(in.bits.single, UInt<1>("h0")) - node T_274 = and(T_273, isSgnj) - node T_275 = bits(in.bits.rm, 1, 1) - node T_277 = eq(T_274, UInt<1>("h0")) - node T_278 = or(T_275, T_277) - node T_279 = bits(in.bits.in1, 64, 64) - node T_280 = bits(in.bits.rm, 0, 0) - node T_281 = mux(T_278, T_279, T_280) - node T_282 = bits(in.bits.in2, 64, 64) - node T_283 = and(T_274, T_282) - node sign_d = xor(T_281, T_283) - node T_285 = bits(in.bits.in1, 63, 33) - node T_286 = bits(in.bits.in1, 31, 0) - node T_287 = cat(sign_d, T_285) - node T_288 = cat(sign_s, T_286) - node fsgnj = cat(T_287, T_288) - inst s2d of RecFNToRecFN - s2d.io is invalid - s2d.clk <= clk - s2d.reset <= reset - inst d2s of RecFNToRecFN_121 - d2s.io is invalid - d2s.clk <= clk - d2s.reset <= reset - s2d.io.in <= in.bits.in1 - s2d.io.roundingMode <= in.bits.rm - d2s.io.in <= in.bits.in1 - d2s.io.roundingMode <= in.bits.rm - node T_292 = bits(in.bits.in1, 31, 29) - node T_293 = not(T_292) - node T_295 = eq(T_293, UInt<1>("h0")) - node T_296 = bits(in.bits.in1, 63, 61) - node T_297 = not(T_296) - node T_299 = eq(T_297, UInt<1>("h0")) - node isnan1 = mux(in.bits.single, T_295, T_299) - node T_301 = bits(in.bits.in2, 31, 29) - node T_302 = not(T_301) - node T_304 = eq(T_302, UInt<1>("h0")) - node T_305 = bits(in.bits.in2, 63, 61) - node T_306 = not(T_305) - node T_308 = eq(T_306, UInt<1>("h0")) - node isnan2 = mux(in.bits.single, T_304, T_308) - node T_310 = bits(in.bits.in1, 22, 22) - node T_311 = bits(in.bits.in1, 51, 51) - node T_312 = mux(in.bits.single, T_310, T_311) - node T_313 = not(T_312) - node issnan1 = and(isnan1, T_313) - node T_315 = bits(in.bits.in2, 22, 22) - node T_316 = bits(in.bits.in2, 51, 51) - node T_317 = mux(in.bits.single, T_315, T_316) - node T_318 = not(T_317) - node issnan2 = and(isnan2, T_318) - node T_320 = or(issnan1, issnan2) - node minmax_exc = cat(T_320, UInt<4>("h0")) - node isMax = bits(in.bits.rm, 0, 0) - node T_324 = neq(isMax, io.lt) - node T_326 = eq(isnan1, UInt<1>("h0")) - node T_327 = and(T_324, T_326) - node isLHS = or(isnan2, T_327) - wire mux : { data : UInt<65>, exc : UInt<5>} - mux is invalid - mux.exc <= minmax_exc - mux.data <= in.bits.in2 - when isSgnj : - mux.exc <= UInt<1>("h0") - skip - node T_336 = or(isSgnj, isLHS) - when T_336 : - mux.data <= fsgnj - skip - node T_339 = and(in.bits.cmd, UInt<3>("h4")) - node T_340 = eq(UInt<1>("h0"), T_339) - when T_340 : - when in.bits.single : - node T_342 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_343 = cat(T_342, d2s.io.out) - mux.data <= T_343 - mux.exc <= d2s.io.exceptionFlags - skip - node T_345 = eq(in.bits.single, UInt<1>("h0")) - when T_345 : - mux.data <= s2d.io.out - mux.exc <= s2d.io.exceptionFlags - skip - skip - reg T_348 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - T_348 <= in.valid - reg T_349 : { data : UInt<65>, exc : UInt<5>}, clk with : - reset => (UInt<1>("h0"), T_349) - when in.valid : - T_349 <- mux - skip - wire T_360 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} - T_360 is invalid - T_360.valid <= T_348 - T_360.bits <- T_349 - io.out <- T_360 - module DivSqrtRecF64_mulAddZ31 : - input clk : Clock - input reset : UInt<1> - output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} - io is invalid - reg valid_PA : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sqrtOp_PA : UInt<1>, clk with : - reset => (UInt<1>("h0"), sqrtOp_PA) - reg sign_PA : UInt<1>, clk with : - reset => (UInt<1>("h0"), sign_PA) - reg specialCodeB_PA : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeB_PA) - reg fractB_51_PA : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractB_51_PA) - reg roundingMode_PA : UInt<2>, clk with : - reset => (UInt<1>("h0"), roundingMode_PA) - reg specialCodeA_PA : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeA_PA) - reg fractA_51_PA : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractA_51_PA) - reg exp_PA : UInt<14>, clk with : - reset => (UInt<1>("h0"), exp_PA) - reg fractB_other_PA : UInt<51>, clk with : - reset => (UInt<1>("h0"), fractB_other_PA) - reg fractA_other_PA : UInt<51>, clk with : - reset => (UInt<1>("h0"), fractA_other_PA) - reg valid_PB : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sqrtOp_PB : UInt<1>, clk with : - reset => (UInt<1>("h0"), sqrtOp_PB) - reg sign_PB : UInt<1>, clk with : - reset => (UInt<1>("h0"), sign_PB) - reg specialCodeA_PB : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeA_PB) - reg fractA_51_PB : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractA_51_PB) - reg specialCodeB_PB : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeB_PB) - reg fractB_51_PB : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractB_51_PB) - reg roundingMode_PB : UInt<2>, clk with : - reset => (UInt<1>("h0"), roundingMode_PB) - reg exp_PB : UInt<14>, clk with : - reset => (UInt<1>("h0"), exp_PB) - reg fractA_0_PB : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractA_0_PB) - reg fractB_other_PB : UInt<51>, clk with : - reset => (UInt<1>("h0"), fractB_other_PB) - reg valid_PC : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg sqrtOp_PC : UInt<1>, clk with : - reset => (UInt<1>("h0"), sqrtOp_PC) - reg sign_PC : UInt<1>, clk with : - reset => (UInt<1>("h0"), sign_PC) - reg specialCodeA_PC : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeA_PC) - reg fractA_51_PC : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractA_51_PC) - reg specialCodeB_PC : UInt<3>, clk with : - reset => (UInt<1>("h0"), specialCodeB_PC) - reg fractB_51_PC : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractB_51_PC) - reg roundingMode_PC : UInt<2>, clk with : - reset => (UInt<1>("h0"), roundingMode_PC) - reg exp_PC : UInt<14>, clk with : - reset => (UInt<1>("h0"), exp_PC) - reg fractA_0_PC : UInt<1>, clk with : - reset => (UInt<1>("h0"), fractA_0_PC) - reg fractB_other_PC : UInt<51>, clk with : - reset => (UInt<1>("h0"), fractB_other_PC) - reg cycleNum_A : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg cycleNum_B : UInt<4>, clk with : - reset => (reset, UInt<4>("h0")) - reg cycleNum_C : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg cycleNum_E : UInt<3>, clk with : - reset => (reset, UInt<3>("h0")) - reg fractR0_A : UInt<9>, clk with : - reset => (UInt<1>("h0"), fractR0_A) - reg hiSqrR0_A_sqrt : UInt<10>, clk with : - reset => (UInt<1>("h0"), hiSqrR0_A_sqrt) - reg partNegSigma0_A : UInt<21>, clk with : - reset => (UInt<1>("h0"), partNegSigma0_A) - reg nextMulAdd9A_A : UInt<9>, clk with : - reset => (UInt<1>("h0"), nextMulAdd9A_A) - reg nextMulAdd9B_A : UInt<9>, clk with : - reset => (UInt<1>("h0"), nextMulAdd9B_A) - reg ER1_B_sqrt : UInt<17>, clk with : - reset => (UInt<1>("h0"), ER1_B_sqrt) - reg ESqrR1_B_sqrt : UInt<32>, clk with : - reset => (UInt<1>("h0"), ESqrR1_B_sqrt) - reg sigX1_B : UInt<58>, clk with : - reset => (UInt<1>("h0"), sigX1_B) - reg sqrSigma1_C : UInt<33>, clk with : - reset => (UInt<1>("h0"), sqrSigma1_C) - reg sigXN_C : UInt<58>, clk with : - reset => (UInt<1>("h0"), sigXN_C) - reg u_C_sqrt : UInt<31>, clk with : - reset => (UInt<1>("h0"), u_C_sqrt) - reg E_E_div : UInt<1>, clk with : - reset => (UInt<1>("h0"), E_E_div) - reg sigT_E : UInt<53>, clk with : - reset => (UInt<1>("h0"), sigT_E) - reg extraT_E : UInt<1>, clk with : - reset => (UInt<1>("h0"), extraT_E) - reg isNegRemT_E : UInt<1>, clk with : - reset => (UInt<1>("h0"), isNegRemT_E) - reg trueEqX_E1 : UInt<1>, clk with : - reset => (UInt<1>("h0"), trueEqX_E1) - wire ready_PA : UInt<1> - ready_PA is invalid - wire ready_PB : UInt<1> - ready_PB is invalid - wire ready_PC : UInt<1> - ready_PC is invalid - wire leaving_PA : UInt<1> - leaving_PA is invalid - wire leaving_PB : UInt<1> - leaving_PB is invalid - wire leaving_PC : UInt<1> - leaving_PC is invalid - wire cyc_B10_sqrt : UInt<1> - cyc_B10_sqrt is invalid - wire cyc_B9_sqrt : UInt<1> - cyc_B9_sqrt is invalid - wire cyc_B8_sqrt : UInt<1> - cyc_B8_sqrt is invalid - wire cyc_B7_sqrt : UInt<1> - cyc_B7_sqrt is invalid - wire cyc_B6 : UInt<1> - cyc_B6 is invalid - wire cyc_B5 : UInt<1> - cyc_B5 is invalid - wire cyc_B4 : UInt<1> - cyc_B4 is invalid - wire cyc_B3 : UInt<1> - cyc_B3 is invalid - wire cyc_B2 : UInt<1> - cyc_B2 is invalid - wire cyc_B1 : UInt<1> - cyc_B1 is invalid - wire cyc_B6_div : UInt<1> - cyc_B6_div is invalid - wire cyc_B5_div : UInt<1> - cyc_B5_div is invalid - wire cyc_B4_div : UInt<1> - cyc_B4_div is invalid - wire cyc_B3_div : UInt<1> - cyc_B3_div is invalid - wire cyc_B2_div : UInt<1> - cyc_B2_div is invalid - wire cyc_B1_div : UInt<1> - cyc_B1_div is invalid - wire cyc_B6_sqrt : UInt<1> - cyc_B6_sqrt is invalid - wire cyc_B5_sqrt : UInt<1> - cyc_B5_sqrt is invalid - wire cyc_B4_sqrt : UInt<1> - cyc_B4_sqrt is invalid - wire cyc_B3_sqrt : UInt<1> - cyc_B3_sqrt is invalid - wire cyc_B2_sqrt : UInt<1> - cyc_B2_sqrt is invalid - wire cyc_B1_sqrt : UInt<1> - cyc_B1_sqrt is invalid - wire cyc_C5 : UInt<1> - cyc_C5 is invalid - wire cyc_C4 : UInt<1> - cyc_C4 is invalid - wire valid_normalCase_leaving_PB : UInt<1> - valid_normalCase_leaving_PB is invalid - wire cyc_C2 : UInt<1> - cyc_C2 is invalid - wire cyc_C1 : UInt<1> - cyc_C1 is invalid - wire cyc_E4 : UInt<1> - cyc_E4 is invalid - wire cyc_E3 : UInt<1> - cyc_E3 is invalid - wire cyc_E2 : UInt<1> - cyc_E2 is invalid - wire cyc_E1 : UInt<1> - cyc_E1 is invalid - wire zSigma1_B4 : UInt - zSigma1_B4 is invalid - wire sigXNU_B3_CX : UInt - sigXNU_B3_CX is invalid - wire zComplSigT_C1_sqrt : UInt - zComplSigT_C1_sqrt is invalid - wire zComplSigT_C1 : UInt - zComplSigT_C1 is invalid - node T_210 = not(cyc_B7_sqrt) - node T_211 = and(ready_PA, T_210) - node T_212 = not(cyc_B6_sqrt) - node T_213 = and(T_211, T_212) - node T_214 = not(cyc_B5_sqrt) - node T_215 = and(T_213, T_214) - node T_216 = not(cyc_B4_sqrt) - node T_217 = and(T_215, T_216) - node T_218 = not(cyc_B3) - node T_219 = and(T_217, T_218) - node T_220 = not(cyc_B2) - node T_221 = and(T_219, T_220) - node T_222 = not(cyc_B1_sqrt) - node T_223 = and(T_221, T_222) - node T_224 = not(cyc_C5) - node T_225 = and(T_223, T_224) - node T_226 = not(cyc_C4) - node T_227 = and(T_225, T_226) - io.inReady_div <= T_227 - node T_228 = not(cyc_B6_sqrt) - node T_229 = and(ready_PA, T_228) - node T_230 = not(cyc_B5_sqrt) - node T_231 = and(T_229, T_230) - node T_232 = not(cyc_B4_sqrt) - node T_233 = and(T_231, T_232) - node T_234 = not(cyc_B2_div) - node T_235 = and(T_233, T_234) - node T_236 = not(cyc_B1_sqrt) - node T_237 = and(T_235, T_236) - io.inReady_sqrt <= T_237 - node T_238 = and(io.inReady_div, io.inValid) - node T_239 = not(io.sqrtOp) - node cyc_S_div = and(T_238, T_239) - node T_241 = and(io.inReady_sqrt, io.inValid) - node cyc_S_sqrt = and(T_241, io.sqrtOp) - node cyc_S = or(cyc_S_div, cyc_S_sqrt) - node signA_S = bits(io.a, 64, 64) - node expA_S = bits(io.a, 63, 52) - node fractA_S = bits(io.a, 51, 0) - node specialCodeA_S = bits(expA_S, 11, 9) - node isZeroA_S = eq(specialCodeA_S, UInt<3>("h0")) - node T_250 = bits(specialCodeA_S, 2, 1) - node isSpecialA_S = eq(T_250, UInt<2>("h3")) - node signB_S = bits(io.b, 64, 64) - node expB_S = bits(io.b, 63, 52) - node fractB_S = bits(io.b, 51, 0) - node specialCodeB_S = bits(expB_S, 11, 9) - node isZeroB_S = eq(specialCodeB_S, UInt<3>("h0")) - node T_259 = bits(specialCodeB_S, 2, 1) - node isSpecialB_S = eq(T_259, UInt<2>("h3")) - node T_262 = xor(signA_S, signB_S) - node sign_S = mux(io.sqrtOp, signB_S, T_262) - node T_264 = not(isSpecialA_S) - node T_265 = not(isSpecialB_S) - node T_266 = and(T_264, T_265) - node T_267 = not(isZeroA_S) - node T_268 = and(T_266, T_267) - node T_269 = not(isZeroB_S) - node normalCase_S_div = and(T_268, T_269) - node T_271 = not(isSpecialB_S) - node T_272 = not(isZeroB_S) - node T_273 = and(T_271, T_272) - node T_274 = not(signB_S) - node normalCase_S_sqrt = and(T_273, T_274) - node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) - node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) - node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) - node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) - node T_280 = not(ready_PB) - node T_281 = or(valid_PA, T_280) - node T_282 = and(cyc_S, T_281) - node entering_PA = or(entering_PA_normalCase, T_282) - node T_284 = not(normalCase_S) - node T_285 = and(cyc_S, T_284) - node T_286 = not(valid_PA) - node T_287 = and(T_285, T_286) - node T_288 = not(valid_PB) - node T_289 = not(ready_PC) - node T_290 = and(T_288, T_289) - node T_291 = or(leaving_PB, T_290) - node entering_PB_S = and(T_287, T_291) - node T_293 = not(normalCase_S) - node T_294 = and(cyc_S, T_293) - node T_295 = not(valid_PA) - node T_296 = and(T_294, T_295) - node T_297 = not(valid_PB) - node T_298 = and(T_296, T_297) - node entering_PC_S = and(T_298, ready_PC) - node T_300 = or(entering_PA, leaving_PA) - when T_300 : - valid_PA <= entering_PA - skip - when entering_PA : - sqrtOp_PA <= io.sqrtOp - sign_PA <= sign_S - specialCodeB_PA <= specialCodeB_S - node T_301 = bits(fractB_S, 51, 51) - fractB_51_PA <= T_301 - roundingMode_PA <= io.roundingMode - skip - node T_302 = not(io.sqrtOp) - node T_303 = and(entering_PA, T_302) - when T_303 : - specialCodeA_PA <= specialCodeA_S - node T_304 = bits(fractA_S, 51, 51) - fractA_51_PA <= T_304 - skip - when entering_PA_normalCase : - node T_305 = bits(expB_S, 11, 11) - node T_307 = sub(UInt<3>("h0"), T_305) - node T_308 = tail(T_307, 1) - node T_309 = bits(expB_S, 10, 0) - node T_310 = not(T_309) - node T_311 = cat(T_308, T_310) - node T_312 = add(expA_S, T_311) - node T_313 = tail(T_312, 1) - node T_314 = mux(io.sqrtOp, expB_S, T_313) - exp_PA <= T_314 - node T_315 = bits(fractB_S, 50, 0) - fractB_other_PA <= T_315 - skip - when entering_PA_normalCase_div : - node T_316 = bits(fractA_S, 50, 0) - fractA_other_PA <= T_316 - skip - node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h0")) - node T_319 = bits(specialCodeA_PA, 2, 1) - node isSpecialA_PA = eq(T_319, UInt<2>("h3")) - node T_323 = cat(fractA_51_PA, fractA_other_PA) - node sigA_PA = cat(UInt<1>("h1"), T_323) - node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h0")) - node T_327 = bits(specialCodeB_PA, 2, 1) - node isSpecialB_PA = eq(T_327, UInt<2>("h3")) - node T_331 = cat(fractB_51_PA, fractB_other_PA) - node sigB_PA = cat(UInt<1>("h1"), T_331) - node T_333 = not(isSpecialB_PA) - node T_334 = not(isZeroB_PA) - node T_335 = and(T_333, T_334) - node T_336 = not(sign_PA) - node T_337 = and(T_335, T_336) - node T_338 = not(isSpecialA_PA) - node T_339 = not(isSpecialB_PA) - node T_340 = and(T_338, T_339) - node T_341 = not(isZeroA_PA) - node T_342 = and(T_340, T_341) - node T_343 = not(isZeroB_PA) - node T_344 = and(T_342, T_343) - node normalCase_PA = mux(sqrtOp_PA, T_337, T_344) - node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) - node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) - node T_348 = and(valid_PA, valid_leaving_PA) - leaving_PA <= T_348 - node T_349 = not(valid_PA) - node T_350 = or(T_349, valid_leaving_PA) - ready_PA <= T_350 - node T_351 = and(valid_PA, normalCase_PA) - node entering_PB_normalCase = and(T_351, valid_normalCase_leaving_PA) - node entering_PB = or(entering_PB_S, leaving_PA) - node T_354 = or(entering_PB, leaving_PB) - when T_354 : - valid_PB <= entering_PB - skip - when entering_PB : - node T_355 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) - sqrtOp_PB <= T_355 - node T_356 = mux(valid_PA, sign_PA, sign_S) - sign_PB <= T_356 - node T_357 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) - specialCodeA_PB <= T_357 - node T_358 = bits(fractA_S, 51, 51) - node T_359 = mux(valid_PA, fractA_51_PA, T_358) - fractA_51_PB <= T_359 - node T_360 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) - specialCodeB_PB <= T_360 - node T_361 = bits(fractB_S, 51, 51) - node T_362 = mux(valid_PA, fractB_51_PA, T_361) - fractB_51_PB <= T_362 - node T_363 = mux(valid_PA, roundingMode_PA, io.roundingMode) - roundingMode_PB <= T_363 - skip - when entering_PB_normalCase : - exp_PB <= exp_PA - node T_364 = bits(fractA_other_PA, 0, 0) - fractA_0_PB <= T_364 - fractB_other_PB <= fractB_other_PA - skip - node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h0")) - node T_367 = bits(specialCodeA_PB, 2, 1) - node isSpecialA_PB = eq(T_367, UInt<2>("h3")) - node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h0")) - node T_372 = bits(specialCodeB_PB, 2, 1) - node isSpecialB_PB = eq(T_372, UInt<2>("h3")) - node T_375 = not(isSpecialB_PB) - node T_376 = not(isZeroB_PB) - node T_377 = and(T_375, T_376) - node T_378 = not(sign_PB) - node T_379 = and(T_377, T_378) - node T_380 = not(isSpecialA_PB) - node T_381 = not(isSpecialB_PB) - node T_382 = and(T_380, T_381) - node T_383 = not(isZeroA_PB) - node T_384 = and(T_382, T_383) - node T_385 = not(isZeroB_PB) - node T_386 = and(T_384, T_385) - node normalCase_PB = mux(sqrtOp_PB, T_379, T_386) - node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) - node T_389 = and(valid_PB, valid_leaving_PB) - leaving_PB <= T_389 - node T_390 = not(valid_PB) - node T_391 = or(T_390, valid_leaving_PB) - ready_PB <= T_391 - node T_392 = and(valid_PB, normalCase_PB) - node entering_PC_normalCase = and(T_392, valid_normalCase_leaving_PB) - node entering_PC = or(entering_PC_S, leaving_PB) - node T_395 = or(entering_PC, leaving_PC) - when T_395 : - valid_PC <= entering_PC - skip - when entering_PC : - node T_396 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) - sqrtOp_PC <= T_396 - node T_397 = mux(valid_PB, sign_PB, sign_S) - sign_PC <= T_397 - node T_398 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) - specialCodeA_PC <= T_398 - node T_399 = bits(fractA_S, 51, 51) - node T_400 = mux(valid_PB, fractA_51_PB, T_399) - fractA_51_PC <= T_400 - node T_401 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) - specialCodeB_PC <= T_401 - node T_402 = bits(fractB_S, 51, 51) - node T_403 = mux(valid_PB, fractB_51_PB, T_402) - fractB_51_PC <= T_403 - node T_404 = mux(valid_PB, roundingMode_PB, io.roundingMode) - roundingMode_PC <= T_404 - skip - when entering_PC_normalCase : - exp_PC <= exp_PB - fractA_0_PC <= fractA_0_PB - fractB_other_PC <= fractB_other_PB - skip - node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h0")) - node T_407 = bits(specialCodeA_PC, 2, 1) - node isSpecialA_PC = eq(T_407, UInt<2>("h3")) - node T_410 = bits(specialCodeA_PC, 0, 0) - node T_411 = not(T_410) - node isInfA_PC = and(isSpecialA_PC, T_411) - node T_413 = bits(specialCodeA_PC, 0, 0) - node isNaNA_PC = and(isSpecialA_PC, T_413) - node T_415 = not(fractA_51_PC) - node isSigNaNA_PC = and(isNaNA_PC, T_415) - node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h0")) - node T_419 = bits(specialCodeB_PC, 2, 1) - node isSpecialB_PC = eq(T_419, UInt<2>("h3")) - node T_422 = bits(specialCodeB_PC, 0, 0) - node T_423 = not(T_422) - node isInfB_PC = and(isSpecialB_PC, T_423) - node T_425 = bits(specialCodeB_PC, 0, 0) - node isNaNB_PC = and(isSpecialB_PC, T_425) - node T_427 = not(fractB_51_PC) - node isSigNaNB_PC = and(isNaNB_PC, T_427) - node T_430 = cat(fractB_51_PC, fractB_other_PC) - node sigB_PC = cat(UInt<1>("h1"), T_430) - node T_432 = not(isSpecialB_PC) - node T_433 = not(isZeroB_PC) - node T_434 = and(T_432, T_433) - node T_435 = not(sign_PC) - node T_436 = and(T_434, T_435) - node T_437 = not(isSpecialA_PC) - node T_438 = not(isSpecialB_PC) - node T_439 = and(T_437, T_438) - node T_440 = not(isZeroA_PC) - node T_441 = and(T_439, T_440) - node T_442 = not(isZeroB_PC) - node T_443 = and(T_441, T_442) - node normalCase_PC = mux(sqrtOp_PC, T_436, T_443) - node T_446 = add(exp_PC, UInt<2>("h2")) - node expP2_PC = tail(T_446, 1) - node T_448 = bits(exp_PC, 0, 0) - node T_449 = bits(expP2_PC, 13, 1) - node T_451 = cat(T_449, UInt<1>("h0")) - node T_452 = bits(exp_PC, 13, 1) - node T_454 = cat(T_452, UInt<1>("h1")) - node expP1_PC = mux(T_448, T_451, T_454) - node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h0")) - node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h1")) - node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h2")) - node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h3")) - node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) - node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) - node T_462 = not(roundMagUp_PC) - node T_463 = not(roundingMode_near_even_PC) - node roundMagDown_PC = and(T_462, T_463) - node T_465 = not(normalCase_PC) - node valid_leaving_PC = or(T_465, cyc_E1) - node T_467 = and(valid_PC, valid_leaving_PC) - leaving_PC <= T_467 - node T_468 = not(valid_PC) - node T_469 = or(T_468, valid_leaving_PC) - ready_PC <= T_469 - node T_470 = not(sqrtOp_PC) - node T_471 = and(leaving_PC, T_470) - io.outValid_div <= T_471 - node T_472 = and(leaving_PC, sqrtOp_PC) - io.outValid_sqrt <= T_472 - node T_474 = neq(cycleNum_A, UInt<1>("h0")) - node T_475 = or(entering_PA_normalCase, T_474) - when T_475 : - node T_478 = mux(entering_PA_normalCase_div, UInt<2>("h3"), UInt<1>("h0")) - node T_481 = mux(entering_PA_normalCase_sqrt, UInt<3>("h6"), UInt<1>("h0")) - node T_482 = or(T_478, T_481) - node T_483 = not(entering_PA_normalCase) - node T_485 = sub(cycleNum_A, UInt<1>("h1")) - node T_486 = tail(T_485, 1) - node T_488 = mux(T_483, T_486, UInt<1>("h0")) - node T_489 = or(T_482, T_488) - cycleNum_A <= T_489 - skip - node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h6")) - node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h5")) - node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h4")) - node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) - node cyc_A3 = eq(cycleNum_A, UInt<2>("h3")) - node cyc_A2 = eq(cycleNum_A, UInt<2>("h2")) - node cyc_A1 = eq(cycleNum_A, UInt<1>("h1")) - node T_503 = not(sqrtOp_PA) - node cyc_A3_div = and(cyc_A3, T_503) - node T_505 = not(sqrtOp_PA) - node cyc_A2_div = and(cyc_A2, T_505) - node T_507 = not(sqrtOp_PA) - node cyc_A1_div = and(cyc_A1, T_507) - node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) - node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) - node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) - node T_513 = neq(cycleNum_B, UInt<1>("h0")) - node T_514 = or(cyc_A1, T_513) - when T_514 : - node T_517 = mux(sqrtOp_PA, UInt<4>("ha"), UInt<3>("h6")) - node T_519 = sub(cycleNum_B, UInt<1>("h1")) - node T_520 = tail(T_519, 1) - node T_521 = mux(cyc_A1, T_517, T_520) - cycleNum_B <= T_521 - skip - node T_523 = eq(cycleNum_B, UInt<4>("ha")) - cyc_B10_sqrt <= T_523 - node T_525 = eq(cycleNum_B, UInt<4>("h9")) - cyc_B9_sqrt <= T_525 - node T_527 = eq(cycleNum_B, UInt<4>("h8")) - cyc_B8_sqrt <= T_527 - node T_529 = eq(cycleNum_B, UInt<3>("h7")) - cyc_B7_sqrt <= T_529 - node T_531 = eq(cycleNum_B, UInt<3>("h6")) - cyc_B6 <= T_531 - node T_533 = eq(cycleNum_B, UInt<3>("h5")) - cyc_B5 <= T_533 - node T_535 = eq(cycleNum_B, UInt<3>("h4")) - cyc_B4 <= T_535 - node T_537 = eq(cycleNum_B, UInt<2>("h3")) - cyc_B3 <= T_537 - node T_539 = eq(cycleNum_B, UInt<2>("h2")) - cyc_B2 <= T_539 - node T_541 = eq(cycleNum_B, UInt<1>("h1")) - cyc_B1 <= T_541 - node T_542 = and(cyc_B6, valid_PA) - node T_543 = not(sqrtOp_PA) - node T_544 = and(T_542, T_543) - cyc_B6_div <= T_544 - node T_545 = and(cyc_B5, valid_PA) - node T_546 = not(sqrtOp_PA) - node T_547 = and(T_545, T_546) - cyc_B5_div <= T_547 - node T_548 = and(cyc_B4, valid_PA) - node T_549 = not(sqrtOp_PA) - node T_550 = and(T_548, T_549) - cyc_B4_div <= T_550 - node T_551 = not(sqrtOp_PB) - node T_552 = and(cyc_B3, T_551) - cyc_B3_div <= T_552 - node T_553 = not(sqrtOp_PB) - node T_554 = and(cyc_B2, T_553) - cyc_B2_div <= T_554 - node T_555 = not(sqrtOp_PB) - node T_556 = and(cyc_B1, T_555) - cyc_B1_div <= T_556 - node T_557 = and(cyc_B6, valid_PB) - node T_558 = and(T_557, sqrtOp_PB) - cyc_B6_sqrt <= T_558 - node T_559 = and(cyc_B5, valid_PB) - node T_560 = and(T_559, sqrtOp_PB) - cyc_B5_sqrt <= T_560 - node T_561 = and(cyc_B4, valid_PB) - node T_562 = and(T_561, sqrtOp_PB) - cyc_B4_sqrt <= T_562 - node T_563 = and(cyc_B3, sqrtOp_PB) - cyc_B3_sqrt <= T_563 - node T_564 = and(cyc_B2, sqrtOp_PB) - cyc_B2_sqrt <= T_564 - node T_565 = and(cyc_B1, sqrtOp_PB) - cyc_B1_sqrt <= T_565 - node T_567 = neq(cycleNum_C, UInt<1>("h0")) - node T_568 = or(cyc_B1, T_567) - when T_568 : - node T_571 = mux(sqrtOp_PB, UInt<3>("h6"), UInt<3>("h5")) - node T_573 = sub(cycleNum_C, UInt<1>("h1")) - node T_574 = tail(T_573, 1) - node T_575 = mux(cyc_B1, T_571, T_574) - cycleNum_C <= T_575 - skip - node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h6")) - node T_579 = eq(cycleNum_C, UInt<3>("h5")) - cyc_C5 <= T_579 - node T_581 = eq(cycleNum_C, UInt<3>("h4")) - cyc_C4 <= T_581 - node T_583 = eq(cycleNum_C, UInt<2>("h3")) - valid_normalCase_leaving_PB <= T_583 - node T_585 = eq(cycleNum_C, UInt<2>("h2")) - cyc_C2 <= T_585 - node T_587 = eq(cycleNum_C, UInt<1>("h1")) - cyc_C1 <= T_587 - node T_588 = not(sqrtOp_PB) - node cyc_C5_div = and(cyc_C5, T_588) - node T_590 = not(sqrtOp_PB) - node cyc_C4_div = and(cyc_C4, T_590) - node T_592 = not(sqrtOp_PB) - node cyc_C3_div = and(valid_normalCase_leaving_PB, T_592) - node T_594 = not(sqrtOp_PC) - node cyc_C2_div = and(cyc_C2, T_594) - node T_596 = not(sqrtOp_PC) - node cyc_C1_div = and(cyc_C1, T_596) - node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) - node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) - node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) - node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) - node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) - node T_604 = neq(cycleNum_E, UInt<1>("h0")) - node T_605 = or(cyc_C1, T_604) - when T_605 : - node T_608 = sub(cycleNum_E, UInt<1>("h1")) - node T_609 = tail(T_608, 1) - node T_610 = mux(cyc_C1, UInt<3>("h4"), T_609) - cycleNum_E <= T_610 - skip - node T_612 = eq(cycleNum_E, UInt<3>("h4")) - cyc_E4 <= T_612 - node T_614 = eq(cycleNum_E, UInt<2>("h3")) - cyc_E3 <= T_614 - node T_616 = eq(cycleNum_E, UInt<2>("h2")) - cyc_E2 <= T_616 - node T_618 = eq(cycleNum_E, UInt<1>("h1")) - cyc_E1 <= T_618 - node T_619 = not(sqrtOp_PC) - node cyc_E4_div = and(cyc_E4, T_619) - node T_621 = not(sqrtOp_PC) - node cyc_E3_div = and(cyc_E3, T_621) - node T_623 = not(sqrtOp_PC) - node cyc_E2_div = and(cyc_E2, T_623) - node T_625 = not(sqrtOp_PC) - node cyc_E1_div = and(cyc_E1, T_625) - node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) - node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) - node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) - node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) - node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h0")) - node T_633 = bits(fractB_S, 51, 49) - node T_635 = eq(T_633, UInt<1>("h0")) - node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_635) - node T_637 = bits(fractB_S, 51, 49) - node T_639 = eq(T_637, UInt<1>("h1")) - node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_639) - node T_641 = bits(fractB_S, 51, 49) - node T_643 = eq(T_641, UInt<2>("h2")) - node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_643) - node T_645 = bits(fractB_S, 51, 49) - node T_647 = eq(T_645, UInt<2>("h3")) - node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_647) - node T_649 = bits(fractB_S, 51, 49) - node T_651 = eq(T_649, UInt<3>("h4")) - node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_651) - node T_653 = bits(fractB_S, 51, 49) - node T_655 = eq(T_653, UInt<3>("h5")) - node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_655) - node T_657 = bits(fractB_S, 51, 49) - node T_659 = eq(T_657, UInt<3>("h6")) - node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_659) - node T_661 = bits(fractB_S, 51, 49) - node T_663 = eq(T_661, UInt<3>("h7")) - node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_663) - node T_667 = mux(zLinPiece_0_A4_div, UInt<9>("h1c7"), UInt<1>("h0")) - node T_670 = mux(zLinPiece_1_A4_div, UInt<9>("h16c"), UInt<1>("h0")) - node T_671 = or(T_667, T_670) - node T_674 = mux(zLinPiece_2_A4_div, UInt<9>("h12a"), UInt<1>("h0")) - node T_675 = or(T_671, T_674) - node T_678 = mux(zLinPiece_3_A4_div, UInt<9>("hf8"), UInt<1>("h0")) - node T_679 = or(T_675, T_678) - node T_682 = mux(zLinPiece_4_A4_div, UInt<9>("hd2"), UInt<1>("h0")) - node T_683 = or(T_679, T_682) - node T_686 = mux(zLinPiece_5_A4_div, UInt<9>("hb4"), UInt<1>("h0")) - node T_687 = or(T_683, T_686) - node T_690 = mux(zLinPiece_6_A4_div, UInt<9>("h9c"), UInt<1>("h0")) - node T_691 = or(T_687, T_690) - node T_694 = mux(zLinPiece_7_A4_div, UInt<9>("h89"), UInt<1>("h0")) - node zK1_A4_div = or(T_691, T_694) - node T_697 = not(UInt<12>("hfe3")) - node T_699 = mux(zLinPiece_0_A4_div, T_697, UInt<1>("h0")) - node T_701 = not(UInt<12>("hc5d")) - node T_703 = mux(zLinPiece_1_A4_div, T_701, UInt<1>("h0")) - node T_704 = or(T_699, T_703) - node T_706 = not(UInt<12>("h98a")) - node T_708 = mux(zLinPiece_2_A4_div, T_706, UInt<1>("h0")) - node T_709 = or(T_704, T_708) - node T_711 = not(UInt<12>("h739")) - node T_713 = mux(zLinPiece_3_A4_div, T_711, UInt<1>("h0")) - node T_714 = or(T_709, T_713) - node T_716 = not(UInt<12>("h54b")) - node T_718 = mux(zLinPiece_4_A4_div, T_716, UInt<1>("h0")) - node T_719 = or(T_714, T_718) - node T_721 = not(UInt<12>("h3a9")) - node T_723 = mux(zLinPiece_5_A4_div, T_721, UInt<1>("h0")) - node T_724 = or(T_719, T_723) - node T_726 = not(UInt<12>("h242")) - node T_728 = mux(zLinPiece_6_A4_div, T_726, UInt<1>("h0")) - node T_729 = or(T_724, T_728) - node T_731 = not(UInt<12>("h10b")) - node T_733 = mux(zLinPiece_7_A4_div, T_731, UInt<1>("h0")) - node zComplFractK0_A4_div = or(T_729, T_733) - node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h0")) - node T_737 = bits(expB_S, 0, 0) - node T_738 = not(T_737) - node T_739 = and(entering_PA_normalCase_sqrt, T_738) - node T_740 = bits(fractB_S, 51, 51) - node T_741 = not(T_740) - node zQuadPiece_0_A7_sqrt = and(T_739, T_741) - node T_743 = bits(expB_S, 0, 0) - node T_744 = not(T_743) - node T_745 = and(entering_PA_normalCase_sqrt, T_744) - node T_746 = bits(fractB_S, 51, 51) - node zQuadPiece_1_A7_sqrt = and(T_745, T_746) - node T_748 = bits(expB_S, 0, 0) - node T_749 = and(entering_PA_normalCase_sqrt, T_748) - node T_750 = bits(fractB_S, 51, 51) - node T_751 = not(T_750) - node zQuadPiece_2_A7_sqrt = and(T_749, T_751) - node T_753 = bits(expB_S, 0, 0) - node T_754 = and(entering_PA_normalCase_sqrt, T_753) - node T_755 = bits(fractB_S, 51, 51) - node zQuadPiece_3_A7_sqrt = and(T_754, T_755) - node T_759 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h1c8"), UInt<1>("h0")) - node T_762 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("hc1"), UInt<1>("h0")) - node T_763 = or(T_759, T_762) - node T_766 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h143"), UInt<1>("h0")) - node T_767 = or(T_763, T_766) - node T_770 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h89"), UInt<1>("h0")) - node zK2_A7_sqrt = or(T_767, T_770) - node T_773 = not(UInt<10>("h3d0")) - node T_775 = mux(zQuadPiece_0_A7_sqrt, T_773, UInt<1>("h0")) - node T_777 = not(UInt<10>("h220")) - node T_779 = mux(zQuadPiece_1_A7_sqrt, T_777, UInt<1>("h0")) - node T_780 = or(T_775, T_779) - node T_782 = not(UInt<10>("h2b2")) - node T_784 = mux(zQuadPiece_2_A7_sqrt, T_782, UInt<1>("h0")) - node T_785 = or(T_780, T_784) - node T_787 = not(UInt<10>("h181")) - node T_789 = mux(zQuadPiece_3_A7_sqrt, T_787, UInt<1>("h0")) - node zComplK1_A7_sqrt = or(T_785, T_789) - node T_791 = bits(exp_PA, 0, 0) - node T_792 = not(T_791) - node T_793 = and(cyc_A6_sqrt, T_792) - node T_794 = bits(sigB_PA, 51, 51) - node T_795 = not(T_794) - node zQuadPiece_0_A6_sqrt = and(T_793, T_795) - node T_797 = bits(exp_PA, 0, 0) - node T_798 = not(T_797) - node T_799 = and(cyc_A6_sqrt, T_798) - node T_800 = bits(sigB_PA, 51, 51) - node zQuadPiece_1_A6_sqrt = and(T_799, T_800) - node T_802 = bits(exp_PA, 0, 0) - node T_803 = and(cyc_A6_sqrt, T_802) - node T_804 = bits(sigB_PA, 51, 51) - node T_805 = not(T_804) - node zQuadPiece_2_A6_sqrt = and(T_803, T_805) - node T_807 = bits(exp_PA, 0, 0) - node T_808 = and(cyc_A6_sqrt, T_807) - node T_809 = bits(sigB_PA, 51, 51) - node zQuadPiece_3_A6_sqrt = and(T_808, T_809) - node T_812 = not(UInt<13>("h1fe5")) - node T_814 = mux(zQuadPiece_0_A6_sqrt, T_812, UInt<1>("h0")) - node T_816 = not(UInt<13>("h1435")) - node T_818 = mux(zQuadPiece_1_A6_sqrt, T_816, UInt<1>("h0")) - node T_819 = or(T_814, T_818) - node T_821 = not(UInt<13>("hd2c")) - node T_823 = mux(zQuadPiece_2_A6_sqrt, T_821, UInt<1>("h0")) - node T_824 = or(T_819, T_823) - node T_826 = not(UInt<13>("h4e8")) - node T_828 = mux(zQuadPiece_3_A6_sqrt, T_826, UInt<1>("h0")) - node zComplFractK0_A6_sqrt = or(T_824, T_828) - node T_830 = bits(zFractB_A4_div, 48, 40) - node T_831 = or(T_830, zK2_A7_sqrt) - node T_832 = not(cyc_S) - node T_834 = mux(T_832, nextMulAdd9A_A, UInt<1>("h0")) - node mulAdd9A_A = or(T_831, T_834) - node T_836 = bits(zFractB_A7_sqrt, 50, 42) - node T_837 = or(zK1_A4_div, T_836) - node T_838 = not(cyc_S) - node T_840 = mux(T_838, nextMulAdd9B_A, UInt<1>("h0")) - node mulAdd9B_A = or(T_837, T_840) - node T_842 = shl(zComplK1_A7_sqrt, 10) - node T_844 = sub(UInt<6>("h0"), cyc_A6_sqrt) - node T_845 = tail(T_844, 1) - node T_846 = cat(zComplFractK0_A6_sqrt, T_845) - node T_847 = cat(cyc_A6_sqrt, T_846) - node T_848 = or(T_842, T_847) - node T_850 = sub(UInt<8>("h0"), entering_PA_normalCase_div) - node T_851 = tail(T_850, 1) - node T_852 = cat(zComplFractK0_A4_div, T_851) - node T_853 = cat(entering_PA_normalCase_div, T_852) - node T_854 = or(T_848, T_853) - node T_856 = shl(fractR0_A, 10) - node T_857 = add(UInt<20>("h40000"), T_856) - node T_858 = tail(T_857, 1) - node T_860 = mux(cyc_A5_sqrt, T_858, UInt<1>("h0")) - node T_861 = or(T_854, T_860) - node T_862 = bits(hiSqrR0_A_sqrt, 9, 9) - node T_863 = not(T_862) - node T_864 = and(cyc_A4_sqrt, T_863) - node T_867 = mux(T_864, UInt<11>("h400"), UInt<1>("h0")) - node T_868 = or(T_861, T_867) - node T_869 = bits(hiSqrR0_A_sqrt, 9, 9) - node T_870 = and(cyc_A4_sqrt, T_869) - node T_871 = or(T_870, cyc_A3_div) - node T_872 = bits(sigB_PA, 46, 26) - node T_874 = add(T_872, UInt<11>("h400")) - node T_875 = tail(T_874, 1) - node T_877 = mux(T_871, T_875, UInt<1>("h0")) - node T_878 = or(T_868, T_877) - node T_879 = or(cyc_A3_sqrt, cyc_A2) - node T_881 = mux(T_879, partNegSigma0_A, UInt<1>("h0")) - node T_882 = or(T_878, T_881) - node T_883 = shl(fractR0_A, 16) - node T_885 = mux(cyc_A1_sqrt, T_883, UInt<1>("h0")) - node T_886 = or(T_882, T_885) - node T_887 = shl(fractR0_A, 15) - node T_889 = mux(cyc_A1_div, T_887, UInt<1>("h0")) - node mulAdd9C_A = or(T_886, T_889) - node T_891 = mul(mulAdd9A_A, mulAdd9B_A) - node T_893 = bits(mulAdd9C_A, 17, 0) - node T_894 = cat(UInt<1>("h0"), T_893) - node T_895 = add(T_891, T_894) - node loMulAdd9Out_A = tail(T_895, 1) - node T_897 = bits(loMulAdd9Out_A, 18, 18) - node T_898 = bits(mulAdd9C_A, 24, 18) - node T_900 = add(T_898, UInt<1>("h1")) - node T_901 = tail(T_900, 1) - node T_902 = bits(mulAdd9C_A, 24, 18) - node T_903 = mux(T_897, T_901, T_902) - node T_904 = bits(loMulAdd9Out_A, 17, 0) - node mulAdd9Out_A = cat(T_903, T_904) - node T_906 = bits(mulAdd9Out_A, 19, 19) - node T_907 = and(cyc_A6_sqrt, T_906) - node T_908 = not(mulAdd9Out_A) - node T_909 = shr(T_908, 10) - node T_911 = mux(T_907, T_909, UInt<1>("h0")) - node zFractR0_A6_sqrt = bits(T_911, 8, 0) - node T_913 = bits(exp_PA, 0, 0) - node T_914 = shl(mulAdd9Out_A, 1) - node sqrR0_A5_sqrt = mux(T_913, T_914, mulAdd9Out_A) - node T_916 = bits(mulAdd9Out_A, 20, 20) - node T_917 = and(entering_PA_normalCase_div, T_916) - node T_918 = not(mulAdd9Out_A) - node T_919 = shr(T_918, 11) - node T_921 = mux(T_917, T_919, UInt<1>("h0")) - node zFractR0_A4_div = bits(T_921, 8, 0) - node T_923 = bits(mulAdd9Out_A, 11, 11) - node T_924 = and(cyc_A2, T_923) - node T_925 = not(mulAdd9Out_A) - node T_926 = shr(T_925, 2) - node T_928 = mux(T_924, T_926, UInt<1>("h0")) - node zSigma0_A2 = bits(T_928, 8, 0) - node T_930 = shr(mulAdd9Out_A, 10) - node T_931 = shr(mulAdd9Out_A, 9) - node T_932 = mux(sqrtOp_PA, T_930, T_931) - node fractR1_A1 = bits(T_932, 14, 0) - node r1_A1 = cat(UInt<1>("h1"), fractR1_A1) - node T_936 = bits(exp_PA, 0, 0) - node T_937 = shl(r1_A1, 1) - node ER1_A1_sqrt = mux(T_936, T_937, r1_A1) - node T_939 = or(cyc_A6_sqrt, entering_PA_normalCase_div) - when T_939 : - node T_940 = or(zFractR0_A6_sqrt, zFractR0_A4_div) - fractR0_A <= T_940 - skip - when cyc_A5_sqrt : - node T_941 = shr(sqrR0_A5_sqrt, 10) - hiSqrR0_A_sqrt <= T_941 - skip - node T_942 = or(cyc_A4_sqrt, cyc_A3) - when T_942 : - node T_943 = shr(mulAdd9Out_A, 9) - node T_944 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_943) - node T_945 = bits(T_944, 20, 0) - partNegSigma0_A <= T_945 - skip - node T_946 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_947 = or(T_946, cyc_A5_sqrt) - node T_948 = or(T_947, cyc_A4) - node T_949 = or(T_948, cyc_A3) - node T_950 = or(T_949, cyc_A2) - when T_950 : - node T_951 = not(mulAdd9Out_A) - node T_952 = shr(T_951, 11) - node T_954 = mux(entering_PA_normalCase_sqrt, T_952, UInt<1>("h0")) - node T_955 = or(T_954, zFractR0_A6_sqrt) - node T_956 = bits(sigB_PA, 43, 35) - node T_958 = mux(cyc_A4_sqrt, T_956, UInt<1>("h0")) - node T_959 = or(T_955, T_958) - node T_960 = bits(zFractB_A4_div, 43, 35) - node T_961 = or(T_959, T_960) - node T_962 = or(cyc_A5_sqrt, cyc_A3) - node T_963 = bits(sigB_PA, 52, 44) - node T_965 = mux(T_962, T_963, UInt<1>("h0")) - node T_966 = or(T_961, T_965) - node T_967 = or(T_966, zSigma0_A2) - nextMulAdd9A_A <= T_967 - skip - node T_968 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_969 = or(T_968, cyc_A5_sqrt) - node T_970 = or(T_969, cyc_A4) - node T_971 = or(T_970, cyc_A2) - when T_971 : - node T_972 = bits(zFractB_A7_sqrt, 50, 42) - node T_973 = or(T_972, zFractR0_A6_sqrt) - node T_974 = bits(sqrR0_A5_sqrt, 9, 1) - node T_976 = mux(cyc_A5_sqrt, T_974, UInt<1>("h0")) - node T_977 = or(T_973, T_976) - node T_978 = or(T_977, zFractR0_A4_div) - node T_979 = bits(hiSqrR0_A_sqrt, 8, 0) - node T_981 = mux(cyc_A4_sqrt, T_979, UInt<1>("h0")) - node T_982 = or(T_978, T_981) - node T_984 = bits(fractR0_A, 8, 1) - node T_985 = cat(UInt<1>("h1"), T_984) - node T_987 = mux(cyc_A2, T_985, UInt<1>("h0")) - node T_988 = or(T_982, T_987) - nextMulAdd9B_A <= T_988 - skip - when cyc_A1_sqrt : - ER1_B_sqrt <= ER1_A1_sqrt - skip - node T_989 = or(cyc_A1, cyc_B7_sqrt) - node T_990 = or(T_989, cyc_B6_div) - node T_991 = or(T_990, cyc_B4) - node T_992 = or(T_991, cyc_B3) - node T_993 = or(T_992, cyc_C6_sqrt) - node T_994 = or(T_993, cyc_C4) - node T_995 = or(T_994, cyc_C1) - io.latchMulAddA_0 <= T_995 - node T_996 = shl(ER1_A1_sqrt, 36) - node T_998 = mux(cyc_A1_sqrt, T_996, UInt<1>("h0")) - node T_999 = or(cyc_B7_sqrt, cyc_A1_div) - node T_1001 = mux(T_999, sigB_PA, UInt<1>("h0")) - node T_1002 = or(T_998, T_1001) - node T_1004 = mux(cyc_B6_div, sigA_PA, UInt<1>("h0")) - node T_1005 = or(T_1002, T_1004) - node T_1006 = bits(zSigma1_B4, 45, 12) - node T_1007 = or(T_1005, T_1006) - node T_1008 = or(cyc_B3, cyc_C6_sqrt) - node T_1009 = bits(sigXNU_B3_CX, 57, 12) - node T_1011 = mux(T_1008, T_1009, UInt<1>("h0")) - node T_1012 = or(T_1007, T_1011) - node T_1013 = bits(sigXN_C, 57, 25) - node T_1014 = shl(T_1013, 13) - node T_1016 = mux(cyc_C4_div, T_1014, UInt<1>("h0")) - node T_1017 = or(T_1012, T_1016) - node T_1018 = shl(u_C_sqrt, 15) - node T_1020 = mux(cyc_C4_sqrt, T_1018, UInt<1>("h0")) - node T_1021 = or(T_1017, T_1020) - node T_1023 = mux(cyc_C1_div, sigB_PC, UInt<1>("h0")) - node T_1024 = or(T_1021, T_1023) - node T_1025 = or(T_1024, zComplSigT_C1_sqrt) - io.mulAddA_0 <= T_1025 - node T_1026 = or(cyc_A1, cyc_B7_sqrt) - node T_1027 = or(T_1026, cyc_B6_sqrt) - node T_1028 = or(T_1027, cyc_B4) - node T_1029 = or(T_1028, cyc_C6_sqrt) - node T_1030 = or(T_1029, cyc_C4) - node T_1031 = or(T_1030, cyc_C1) - io.latchMulAddB_0 <= T_1031 - node T_1032 = shl(r1_A1, 36) - node T_1034 = mux(cyc_A1, T_1032, UInt<1>("h0")) - node T_1035 = shl(ESqrR1_B_sqrt, 19) - node T_1037 = mux(cyc_B7_sqrt, T_1035, UInt<1>("h0")) - node T_1038 = or(T_1034, T_1037) - node T_1039 = shl(ER1_B_sqrt, 36) - node T_1041 = mux(cyc_B6_sqrt, T_1039, UInt<1>("h0")) - node T_1042 = or(T_1038, T_1041) - node T_1043 = or(T_1042, zSigma1_B4) - node T_1044 = bits(sqrSigma1_C, 30, 1) - node T_1046 = mux(cyc_C6_sqrt, T_1044, UInt<1>("h0")) - node T_1047 = or(T_1043, T_1046) - node T_1049 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h0")) - node T_1050 = or(T_1047, T_1049) - node T_1051 = or(T_1050, zComplSigT_C1) - io.mulAddB_0 <= T_1051 - node T_1052 = or(cyc_A4, cyc_A3_div) - node T_1053 = or(T_1052, cyc_A1_div) - node T_1054 = or(T_1053, cyc_B10_sqrt) - node T_1055 = or(T_1054, cyc_B9_sqrt) - node T_1056 = or(T_1055, cyc_B7_sqrt) - node T_1057 = or(T_1056, cyc_B6) - node T_1058 = or(T_1057, cyc_B5_sqrt) - node T_1059 = or(T_1058, cyc_B3_sqrt) - node T_1060 = or(T_1059, cyc_B2_div) - node T_1061 = or(T_1060, cyc_B1_sqrt) - node T_1062 = or(T_1061, cyc_C4) - node T_1063 = or(cyc_A3, cyc_A2_div) - node T_1064 = or(T_1063, cyc_B9_sqrt) - node T_1065 = or(T_1064, cyc_B8_sqrt) - node T_1066 = or(T_1065, cyc_B6) - node T_1067 = or(T_1066, cyc_B5) - node T_1068 = or(T_1067, cyc_B4_sqrt) - node T_1069 = or(T_1068, cyc_B2_sqrt) - node T_1070 = or(T_1069, cyc_B1_div) - node T_1071 = or(T_1070, cyc_C6_sqrt) - node T_1072 = or(T_1071, valid_normalCase_leaving_PB) - node T_1073 = or(cyc_A2, cyc_A1_div) - node T_1074 = or(T_1073, cyc_B8_sqrt) - node T_1075 = or(T_1074, cyc_B7_sqrt) - node T_1076 = or(T_1075, cyc_B5) - node T_1077 = or(T_1076, cyc_B4) - node T_1078 = or(T_1077, cyc_B3_sqrt) - node T_1079 = or(T_1078, cyc_B1_sqrt) - node T_1080 = or(T_1079, cyc_C5) - node T_1081 = or(T_1080, cyc_C2) - node T_1082 = or(io.latchMulAddA_0, cyc_B6) - node T_1083 = or(T_1082, cyc_B2_sqrt) - node T_1084 = cat(T_1062, T_1072) - node T_1085 = cat(T_1081, T_1083) - node T_1086 = cat(T_1084, T_1085) - io.usingMulAdd <= T_1086 - node T_1087 = shl(sigX1_B, 47) - node T_1089 = mux(cyc_B1, T_1087, UInt<1>("h0")) - node T_1090 = shl(sigX1_B, 46) - node T_1092 = mux(cyc_C6_sqrt, T_1090, UInt<1>("h0")) - node T_1093 = or(T_1089, T_1092) - node T_1094 = or(cyc_C4_sqrt, cyc_C2) - node T_1095 = shl(sigXN_C, 47) - node T_1097 = mux(T_1094, T_1095, UInt<1>("h0")) - node T_1098 = or(T_1093, T_1097) - node T_1099 = not(E_E_div) - node T_1100 = and(cyc_E3_div, T_1099) - node T_1101 = shl(fractA_0_PC, 53) - node T_1103 = mux(T_1100, T_1101, UInt<1>("h0")) - node T_1104 = or(T_1098, T_1103) - node T_1105 = bits(exp_PC, 0, 0) - node T_1106 = bits(sigB_PC, 0, 0) - node T_1108 = cat(T_1106, UInt<1>("h0")) - node T_1109 = bits(sigB_PC, 1, 1) - node T_1110 = bits(sigB_PC, 0, 0) - node T_1111 = xor(T_1109, T_1110) - node T_1112 = bits(sigB_PC, 0, 0) - node T_1113 = cat(T_1111, T_1112) - node T_1114 = mux(T_1105, T_1108, T_1113) - node T_1115 = not(extraT_E) - node T_1117 = cat(T_1115, UInt<1>("h0")) - node T_1118 = xor(T_1114, T_1117) - node T_1119 = shl(T_1118, 54) - node T_1121 = mux(cyc_E3_sqrt, T_1119, UInt<1>("h0")) - node T_1122 = or(T_1104, T_1121) - io.mulAddC_2 <= T_1122 - node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) - node T_1124 = bits(io.mulAddResult_3, 90, 45) - node T_1125 = not(T_1124) - node T_1127 = mux(cyc_B4, T_1125, UInt<1>("h0")) - zSigma1_B4 <= T_1127 - node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) - node T_1129 = bits(io.mulAddResult_3, 104, 47) - sigXNU_B3_CX <= T_1129 - node T_1130 = bits(io.mulAddResult_3, 104, 104) - node E_C1_div = not(T_1130) - node T_1132 = not(E_C1_div) - node T_1133 = and(cyc_C1_div, T_1132) - node T_1134 = or(T_1133, cyc_C1_sqrt) - node T_1135 = bits(io.mulAddResult_3, 104, 51) - node T_1136 = not(T_1135) - node T_1138 = mux(T_1134, T_1136, UInt<1>("h0")) - node T_1139 = and(cyc_C1_div, E_C1_div) - node T_1141 = bits(io.mulAddResult_3, 102, 50) - node T_1142 = not(T_1141) - node T_1143 = cat(UInt<1>("h0"), T_1142) - node T_1145 = mux(T_1139, T_1143, UInt<1>("h0")) - node T_1146 = or(T_1138, T_1145) - zComplSigT_C1 <= T_1146 - node T_1147 = bits(io.mulAddResult_3, 104, 51) - node T_1148 = not(T_1147) - node T_1150 = mux(cyc_C1_sqrt, T_1148, UInt<1>("h0")) - zComplSigT_C1_sqrt <= T_1150 - node sigT_C1 = not(zComplSigT_C1) - node remT_E2 = bits(io.mulAddResult_3, 55, 0) - when cyc_B8_sqrt : - ESqrR1_B_sqrt <= ESqrR1_B8_sqrt - skip - when cyc_B3 : - sigX1_B <= sigXNU_B3_CX - skip - when cyc_B1 : - sqrSigma1_C <= sqrSigma1_B1 - skip - node T_1153 = or(cyc_C6_sqrt, cyc_C5_div) - node T_1154 = or(T_1153, cyc_C3_sqrt) - when T_1154 : - sigXN_C <= sigXNU_B3_CX - skip - when cyc_C5_sqrt : - node T_1155 = bits(sigXNU_B3_CX, 56, 26) - u_C_sqrt <= T_1155 - skip - when cyc_C1 : - E_E_div <= E_C1_div - node T_1156 = bits(sigT_C1, 53, 1) - sigT_E <= T_1156 - node T_1157 = bits(sigT_C1, 0, 0) - extraT_E <= T_1157 - skip - when cyc_E2 : - node T_1158 = bits(remT_E2, 55, 55) - node T_1159 = bits(remT_E2, 53, 53) - node T_1160 = mux(sqrtOp_PC, T_1158, T_1159) - isNegRemT_E <= T_1160 - node T_1161 = bits(remT_E2, 53, 0) - node T_1163 = eq(T_1161, UInt<1>("h0")) - node T_1164 = not(sqrtOp_PC) - node T_1165 = bits(remT_E2, 55, 54) - node T_1167 = eq(T_1165, UInt<1>("h0")) - node T_1168 = or(T_1164, T_1167) - node T_1169 = and(T_1163, T_1168) - trueEqX_E1 <= T_1169 - skip - node T_1170 = not(sqrtOp_PC) - node T_1171 = and(T_1170, E_E_div) - node T_1173 = mux(T_1171, exp_PC, UInt<1>("h0")) - node T_1174 = not(sqrtOp_PC) - node T_1175 = not(E_E_div) - node T_1176 = and(T_1174, T_1175) - node T_1178 = mux(T_1176, expP1_PC, UInt<1>("h0")) - node T_1179 = or(T_1173, T_1178) - node T_1180 = shr(exp_PC, 1) - node T_1182 = add(T_1180, UInt<12>("h400")) - node T_1183 = tail(T_1182, 1) - node T_1185 = mux(sqrtOp_PC, T_1183, UInt<1>("h0")) - node sExpX_E = or(T_1179, T_1185) - node posExpX_E = bits(sExpX_E, 12, 0) - node T_1188 = not(posExpX_E) - node T_1190 = dshr(asSInt(UInt<8193>("h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1188) - node T_1191 = bits(T_1190, 1026, 974) - node T_1192 = bits(T_1191, 31, 0) - node T_1195 = shl(UInt<16>("hffff"), 16) - node T_1196 = xor(UInt<32>("hffffffff"), T_1195) - node T_1197 = shr(T_1192, 16) - node T_1198 = and(T_1197, T_1196) - node T_1199 = bits(T_1192, 15, 0) - node T_1200 = shl(T_1199, 16) - node T_1201 = not(T_1196) - node T_1202 = and(T_1200, T_1201) - node T_1203 = or(T_1198, T_1202) - node T_1204 = bits(T_1196, 23, 0) - node T_1205 = shl(T_1204, 8) - node T_1206 = xor(T_1196, T_1205) - node T_1207 = shr(T_1203, 8) - node T_1208 = and(T_1207, T_1206) - node T_1209 = bits(T_1203, 23, 0) - node T_1210 = shl(T_1209, 8) - node T_1211 = not(T_1206) - node T_1212 = and(T_1210, T_1211) - node T_1213 = or(T_1208, T_1212) - node T_1214 = bits(T_1206, 27, 0) - node T_1215 = shl(T_1214, 4) - node T_1216 = xor(T_1206, T_1215) - node T_1217 = shr(T_1213, 4) - node T_1218 = and(T_1217, T_1216) - node T_1219 = bits(T_1213, 27, 0) - node T_1220 = shl(T_1219, 4) - node T_1221 = not(T_1216) - node T_1222 = and(T_1220, T_1221) - node T_1223 = or(T_1218, T_1222) - node T_1224 = bits(T_1216, 29, 0) - node T_1225 = shl(T_1224, 2) - node T_1226 = xor(T_1216, T_1225) - node T_1227 = shr(T_1223, 2) - node T_1228 = and(T_1227, T_1226) - node T_1229 = bits(T_1223, 29, 0) - node T_1230 = shl(T_1229, 2) - node T_1231 = not(T_1226) - node T_1232 = and(T_1230, T_1231) - node T_1233 = or(T_1228, T_1232) - node T_1234 = bits(T_1226, 30, 0) - node T_1235 = shl(T_1234, 1) - node T_1236 = xor(T_1226, T_1235) - node T_1237 = shr(T_1233, 1) - node T_1238 = and(T_1237, T_1236) - node T_1239 = bits(T_1233, 30, 0) - node T_1240 = shl(T_1239, 1) - node T_1241 = not(T_1236) - node T_1242 = and(T_1240, T_1241) - node T_1243 = or(T_1238, T_1242) - node T_1244 = bits(T_1191, 52, 32) - node T_1245 = bits(T_1244, 15, 0) - node T_1248 = shl(UInt<8>("hff"), 8) - node T_1249 = xor(UInt<16>("hffff"), T_1248) - node T_1250 = shr(T_1245, 8) - node T_1251 = and(T_1250, T_1249) - node T_1252 = bits(T_1245, 7, 0) - node T_1253 = shl(T_1252, 8) - node T_1254 = not(T_1249) - node T_1255 = and(T_1253, T_1254) - node T_1256 = or(T_1251, T_1255) - node T_1257 = bits(T_1249, 11, 0) - node T_1258 = shl(T_1257, 4) - node T_1259 = xor(T_1249, T_1258) - node T_1260 = shr(T_1256, 4) - node T_1261 = and(T_1260, T_1259) - node T_1262 = bits(T_1256, 11, 0) - node T_1263 = shl(T_1262, 4) - node T_1264 = not(T_1259) - node T_1265 = and(T_1263, T_1264) - node T_1266 = or(T_1261, T_1265) - node T_1267 = bits(T_1259, 13, 0) - node T_1268 = shl(T_1267, 2) - node T_1269 = xor(T_1259, T_1268) - node T_1270 = shr(T_1266, 2) - node T_1271 = and(T_1270, T_1269) - node T_1272 = bits(T_1266, 13, 0) - node T_1273 = shl(T_1272, 2) - node T_1274 = not(T_1269) - node T_1275 = and(T_1273, T_1274) - node T_1276 = or(T_1271, T_1275) - node T_1277 = bits(T_1269, 14, 0) - node T_1278 = shl(T_1277, 1) - node T_1279 = xor(T_1269, T_1278) - node T_1280 = shr(T_1276, 1) - node T_1281 = and(T_1280, T_1279) - node T_1282 = bits(T_1276, 14, 0) - node T_1283 = shl(T_1282, 1) - node T_1284 = not(T_1279) - node T_1285 = and(T_1283, T_1284) - node T_1286 = or(T_1281, T_1285) - node T_1287 = bits(T_1244, 20, 16) - node T_1288 = bits(T_1287, 3, 0) - node T_1289 = bits(T_1288, 1, 0) - node T_1290 = bits(T_1289, 0, 0) - node T_1291 = bits(T_1289, 1, 1) - node T_1292 = cat(T_1290, T_1291) - node T_1293 = bits(T_1288, 3, 2) - node T_1294 = bits(T_1293, 0, 0) - node T_1295 = bits(T_1293, 1, 1) - node T_1296 = cat(T_1294, T_1295) - node T_1297 = cat(T_1292, T_1296) - node T_1298 = bits(T_1287, 4, 4) - node T_1299 = cat(T_1297, T_1298) - node T_1300 = cat(T_1286, T_1299) - node roundMask_E = cat(T_1243, T_1300) - node T_1303 = cat(UInt<1>("h0"), roundMask_E) - node T_1304 = not(T_1303) - node T_1306 = cat(roundMask_E, UInt<1>("h1")) - node incrPosMask_E = and(T_1304, T_1306) - node T_1308 = shr(incrPosMask_E, 1) - node T_1309 = and(sigT_E, T_1308) - node hiRoundPosBitT_E = neq(T_1309, UInt<1>("h0")) - node T_1312 = shr(roundMask_E, 1) - node T_1313 = and(sigT_E, T_1312) - node all0sHiRoundExtraT_E = eq(T_1313, UInt<1>("h0")) - node T_1316 = not(sigT_E) - node T_1317 = shr(roundMask_E, 1) - node T_1318 = and(T_1316, T_1317) - node all1sHiRoundExtraT_E = eq(T_1318, UInt<1>("h0")) - node T_1321 = bits(roundMask_E, 0, 0) - node T_1322 = not(T_1321) - node T_1323 = or(T_1322, hiRoundPosBitT_E) - node all1sHiRoundT_E = and(T_1323, all1sHiRoundExtraT_E) - node T_1326 = add(UInt<54>("h0"), sigT_E) - node T_1327 = tail(T_1326, 1) - node T_1328 = add(T_1327, roundMagUp_PC) - node sigAdjT_E = tail(T_1328, 1) - node T_1331 = not(roundMask_E) - node T_1332 = cat(UInt<1>("h1"), T_1331) - node sigY0_E = and(sigAdjT_E, T_1332) - node T_1335 = cat(UInt<1>("h0"), roundMask_E) - node T_1336 = or(sigAdjT_E, T_1335) - node T_1338 = add(T_1336, UInt<1>("h1")) - node sigY1_E = tail(T_1338, 1) - node T_1340 = not(isNegRemT_E) - node T_1341 = not(trueEqX_E1) - node T_1342 = and(T_1340, T_1341) - node trueLtX_E1 = mux(sqrtOp_PC, T_1342, isNegRemT_E) - node T_1344 = bits(roundMask_E, 0, 0) - node T_1345 = not(trueLtX_E1) - node T_1346 = and(T_1344, T_1345) - node T_1347 = and(T_1346, all1sHiRoundExtraT_E) - node T_1348 = and(T_1347, extraT_E) - node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1348) - node T_1350 = not(trueEqX_E1) - node T_1351 = not(extraT_E) - node T_1352 = or(T_1350, T_1351) - node T_1353 = not(all1sHiRoundExtraT_E) - node anyRoundExtra_E1 = or(T_1352, T_1353) - node T_1355 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) - node T_1356 = not(anyRoundExtra_E1) - node T_1357 = and(T_1355, T_1356) - node roundEvenMask_E1 = mux(T_1357, incrPosMask_E, UInt<1>("h0")) - node T_1360 = and(roundMagDown_PC, extraT_E) - node T_1361 = not(trueLtX_E1) - node T_1362 = and(T_1360, T_1361) - node T_1363 = and(T_1362, all1sHiRoundT_E) - node T_1364 = not(trueLtX_E1) - node T_1365 = and(extraT_E, T_1364) - node T_1366 = not(trueEqX_E1) - node T_1367 = and(T_1365, T_1366) - node T_1368 = not(all1sHiRoundT_E) - node T_1369 = or(T_1367, T_1368) - node T_1370 = and(roundMagUp_PC, T_1369) - node T_1371 = or(T_1363, T_1370) - node T_1372 = not(trueLtX_E1) - node T_1373 = or(extraT_E, T_1372) - node T_1374 = bits(roundMask_E, 0, 0) - node T_1375 = not(T_1374) - node T_1376 = and(T_1373, T_1375) - node T_1377 = or(hiRoundPosBitT_E, T_1376) - node T_1378 = not(trueLtX_E1) - node T_1379 = and(extraT_E, T_1378) - node T_1380 = and(T_1379, all1sHiRoundExtraT_E) - node T_1381 = or(T_1377, T_1380) - node T_1382 = and(roundingMode_near_even_PC, T_1381) - node T_1383 = or(T_1371, T_1382) - node T_1384 = mux(T_1383, sigY1_E, sigY0_E) - node T_1385 = not(roundEvenMask_E1) - node sigY_E1 = and(T_1384, T_1385) - node fractY_E1 = bits(sigY_E1, 51, 0) - node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) - node T_1389 = bits(sigY_E1, 53, 53) - node T_1390 = not(T_1389) - node T_1392 = mux(T_1390, sExpX_E, UInt<1>("h0")) - node T_1393 = bits(sigY_E1, 53, 53) - node T_1394 = not(sqrtOp_PC) - node T_1395 = and(T_1393, T_1394) - node T_1396 = and(T_1395, E_E_div) - node T_1398 = mux(T_1396, expP1_PC, UInt<1>("h0")) - node T_1399 = or(T_1392, T_1398) - node T_1400 = bits(sigY_E1, 53, 53) - node T_1401 = not(sqrtOp_PC) - node T_1402 = and(T_1400, T_1401) - node T_1403 = not(E_E_div) - node T_1404 = and(T_1402, T_1403) - node T_1406 = mux(T_1404, expP2_PC, UInt<1>("h0")) - node T_1407 = or(T_1399, T_1406) - node T_1408 = bits(sigY_E1, 53, 53) - node T_1409 = and(T_1408, sqrtOp_PC) - node T_1410 = shr(expP2_PC, 1) - node T_1412 = add(T_1410, UInt<12>("h400")) - node T_1413 = tail(T_1412, 1) - node T_1415 = mux(T_1409, T_1413, UInt<1>("h0")) - node sExpY_E1 = or(T_1407, T_1415) - node expY_E1 = bits(sExpY_E1, 11, 0) - node T_1418 = bits(sExpY_E1, 13, 13) - node T_1419 = not(T_1418) - node T_1421 = bits(sExpY_E1, 12, 10) - node T_1422 = leq(UInt<3>("h3"), T_1421) - node overflowY_E1 = and(T_1419, T_1422) - node T_1424 = bits(sExpY_E1, 13, 13) - node T_1425 = bits(sExpY_E1, 12, 0) - node T_1427 = lt(T_1425, UInt<13>("h3ce")) - node totalUnderflowY_E1 = or(T_1424, T_1427) - node T_1430 = leq(posExpX_E, UInt<13>("h401")) - node T_1431 = and(T_1430, inexactY_E1) - node underflowY_E1 = or(totalUnderflowY_E1, T_1431) - node T_1433 = not(isNaNB_PC) - node T_1434 = not(isZeroB_PC) - node T_1435 = and(T_1433, T_1434) - node T_1436 = and(T_1435, sign_PC) - node T_1437 = and(isZeroA_PC, isZeroB_PC) - node T_1438 = and(isInfA_PC, isInfB_PC) - node T_1439 = or(T_1437, T_1438) - node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1436, T_1439) - node T_1441 = not(sqrtOp_PC) - node T_1442 = and(T_1441, isSigNaNA_PC) - node T_1443 = or(T_1442, isSigNaNB_PC) - node invalid_PC = or(T_1443, notSigNaN_invalid_PC) - node T_1445 = not(sqrtOp_PC) - node T_1446 = not(isSpecialA_PC) - node T_1447 = and(T_1445, T_1446) - node T_1448 = not(isZeroA_PC) - node T_1449 = and(T_1447, T_1448) - node infinity_PC = and(T_1449, isZeroB_PC) - node overflow_E1 = and(normalCase_PC, overflowY_E1) - node underflow_E1 = and(normalCase_PC, underflowY_E1) - node T_1453 = or(overflow_E1, underflow_E1) - node T_1454 = and(normalCase_PC, inexactY_E1) - node inexact_E1 = or(T_1453, T_1454) - node T_1456 = or(isZeroA_PC, isInfB_PC) - node T_1457 = not(roundMagUp_PC) - node T_1458 = and(totalUnderflowY_E1, T_1457) - node T_1459 = or(T_1456, T_1458) - node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1459) - node T_1461 = and(normalCase_PC, totalUnderflowY_E1) - node pegMinFiniteMagOut_E1 = and(T_1461, roundMagUp_PC) - node T_1463 = not(overflowY_roundMagUp_PC) - node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1463) - node T_1465 = or(isInfA_PC, isZeroB_PC) - node T_1466 = and(overflow_E1, overflowY_roundMagUp_PC) - node T_1467 = or(T_1465, T_1466) - node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1467) - node T_1469 = not(sqrtOp_PC) - node T_1470 = and(T_1469, isNaNA_PC) - node T_1471 = or(T_1470, isNaNB_PC) - node isNaNOut_PC = or(T_1471, notSigNaN_invalid_PC) - node T_1473 = not(isNaNOut_PC) - node T_1474 = and(isZeroB_PC, sign_PC) - node T_1475 = mux(sqrtOp_PC, T_1474, sign_PC) - node signOut_PC = and(T_1473, T_1475) - node T_1478 = not(UInt<12>("h1ff")) - node T_1480 = mux(notSpecial_isZeroOut_E1, T_1478, UInt<1>("h0")) - node T_1481 = not(T_1480) - node T_1482 = and(expY_E1, T_1481) - node T_1484 = not(UInt<12>("h3ce")) - node T_1486 = mux(pegMinFiniteMagOut_E1, T_1484, UInt<1>("h0")) - node T_1487 = not(T_1486) - node T_1488 = and(T_1482, T_1487) - node T_1490 = not(UInt<12>("hbff")) - node T_1492 = mux(pegMaxFiniteMagOut_E1, T_1490, UInt<1>("h0")) - node T_1493 = not(T_1492) - node T_1494 = and(T_1488, T_1493) - node T_1496 = not(UInt<12>("hdff")) - node T_1498 = mux(notNaN_isInfOut_E1, T_1496, UInt<1>("h0")) - node T_1499 = not(T_1498) - node T_1500 = and(T_1494, T_1499) - node T_1503 = mux(pegMinFiniteMagOut_E1, UInt<12>("h3ce"), UInt<1>("h0")) - node T_1504 = or(T_1500, T_1503) - node T_1507 = mux(pegMaxFiniteMagOut_E1, UInt<12>("hbff"), UInt<1>("h0")) - node T_1508 = or(T_1504, T_1507) - node T_1511 = mux(notNaN_isInfOut_E1, UInt<12>("hc00"), UInt<1>("h0")) - node T_1512 = or(T_1508, T_1511) - node T_1515 = mux(isNaNOut_PC, UInt<12>("he00"), UInt<1>("h0")) - node expOut_E1 = or(T_1512, T_1515) - node T_1517 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) - node T_1518 = or(T_1517, isNaNOut_PC) - node T_1520 = mux(T_1518, UInt<1>("h0"), fractY_E1) - node T_1522 = sub(UInt<52>("h0"), pegMaxFiniteMagOut_E1) - node T_1523 = tail(T_1522, 1) - node T_1524 = or(T_1520, T_1523) - node T_1525 = shl(isNaNOut_PC, 51) - node fractOut_E1 = or(T_1524, T_1525) - node T_1527 = cat(expOut_E1, fractOut_E1) - node T_1528 = cat(signOut_PC, T_1527) - io.out <= T_1528 - node T_1529 = cat(invalid_PC, infinity_PC) - node T_1530 = cat(underflow_E1, inexact_E1) - node T_1531 = cat(overflow_E1, T_1530) - node T_1532 = cat(T_1529, T_1531) - io.exceptionFlags <= T_1532 - module Mul54 : - input clk : Clock - input reset : UInt<1> - output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} - io is invalid - reg val_s1 : UInt<1>, clk with : - reset => (UInt<1>("h0"), val_s1) - reg val_s2 : UInt<1>, clk with : - reset => (UInt<1>("h0"), val_s2) - reg reg_a_s1 : UInt<54>, clk with : - reset => (UInt<1>("h0"), reg_a_s1) - reg reg_b_s1 : UInt<54>, clk with : - reset => (UInt<1>("h0"), reg_b_s1) - reg reg_a_s2 : UInt<54>, clk with : - reset => (UInt<1>("h0"), reg_a_s2) - reg reg_b_s2 : UInt<54>, clk with : - reset => (UInt<1>("h0"), reg_b_s2) - reg reg_result_s3 : UInt<105>, clk with : - reset => (UInt<1>("h0"), reg_result_s3) - val_s1 <= io.val_s0 - val_s2 <= val_s1 - when io.val_s0 : - when io.latch_a_s0 : - reg_a_s1 <= io.a_s0 - skip - when io.latch_b_s0 : - reg_b_s1 <= io.b_s0 - skip - skip - when val_s1 : - reg_a_s2 <= reg_a_s1 - reg_b_s2 <= reg_b_s1 - skip - when val_s2 : - node T_25 = mul(reg_a_s2, reg_b_s2) - node T_26 = bits(T_25, 104, 0) - node T_27 = add(T_26, io.c_s2) - node T_28 = tail(T_27, 1) - reg_result_s3 <= T_28 - skip - io.result_s3 <= reg_result_s3 - module DivSqrtRecF64 : - input clk : Clock - input reset : UInt<1> - output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} - io is invalid - inst ds of DivSqrtRecF64_mulAddZ31 - ds.io is invalid - ds.clk <= clk - ds.reset <= reset - io.inReady_div <= ds.io.inReady_div - io.inReady_sqrt <= ds.io.inReady_sqrt - ds.io.inValid <= io.inValid - ds.io.sqrtOp <= io.sqrtOp - ds.io.a <= io.a - ds.io.b <= io.b - ds.io.roundingMode <= io.roundingMode - io.outValid_div <= ds.io.outValid_div - io.outValid_sqrt <= ds.io.outValid_sqrt - io.out <= ds.io.out - io.exceptionFlags <= ds.io.exceptionFlags - inst mul of Mul54 - mul.io is invalid - mul.clk <= clk - mul.reset <= reset - node T_17 = bits(ds.io.usingMulAdd, 0, 0) - mul.io.val_s0 <= T_17 - mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 - mul.io.a_s0 <= ds.io.mulAddA_0 - mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 - mul.io.b_s0 <= ds.io.mulAddB_0 - mul.io.c_s2 <= ds.io.mulAddC_2 - ds.io.mulAddResult_3 <= mul.io.result_s3 - module FPU : - input clk : Clock - input reset : UInt<1> - output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} - io is invalid - reg ex_reg_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - ex_reg_valid <= io.valid - node req_valid = or(ex_reg_valid, io.cp_req.valid) - reg ex_reg_inst : UInt<32>, clk with : - reset => (UInt<1>("h0"), ex_reg_inst) - when io.valid : - ex_reg_inst <= io.inst - skip - node T_202 = eq(ex_reg_valid, UInt<1>("h0")) - node ex_cp_valid = and(io.cp_req.valid, T_202) - node T_205 = eq(io.killx, UInt<1>("h0")) - node T_206 = and(ex_reg_valid, T_205) - node T_207 = or(T_206, ex_cp_valid) - reg mem_reg_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - mem_reg_valid <= T_207 - reg mem_reg_inst : UInt<32>, clk with : - reset => (UInt<1>("h0"), mem_reg_inst) - when ex_reg_valid : - mem_reg_inst <= ex_reg_inst - skip - reg mem_cp_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - mem_cp_valid <= ex_cp_valid - node T_213 = or(io.killm, io.nack_mem) - node T_215 = eq(mem_cp_valid, UInt<1>("h0")) - node killm = and(T_213, T_215) - node T_218 = eq(killm, UInt<1>("h0")) - node T_219 = or(T_218, mem_cp_valid) - node T_220 = and(mem_reg_valid, T_219) - reg wb_reg_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wb_reg_valid <= T_220 - reg wb_cp_valid : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - wb_cp_valid <= mem_cp_valid - inst fp_decoder of FPUDecoder - fp_decoder.io is invalid - fp_decoder.clk <= clk - fp_decoder.reset <= reset - fp_decoder.io.inst <= io.inst - wire cp_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - cp_ctrl is invalid - cp_ctrl <- io.cp_req.bits - io.cp_resp.valid <= UInt<1>("h0") - io.cp_resp.bits.data <= UInt<1>("h0") - reg T_264 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : - reset => (UInt<1>("h0"), T_264) - when io.valid : - T_264 <- fp_decoder.io.sigs - skip - node ex_ctrl = mux(ex_reg_valid, T_264, cp_ctrl) - reg mem_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : - reset => (UInt<1>("h0"), mem_ctrl) - when req_valid : - mem_ctrl <- ex_ctrl - skip - reg wb_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : - reset => (UInt<1>("h0"), wb_ctrl) - when mem_reg_valid : - wb_ctrl <- mem_ctrl - skip - reg load_wb : UInt<1>, clk with : - reset => (UInt<1>("h0"), load_wb) - load_wb <= io.dmem_resp_val - node T_337 = eq(io.dmem_resp_type, UInt<3>("h2")) - node T_338 = eq(io.dmem_resp_type, UInt<3>("h6")) - node T_339 = or(T_337, T_338) - reg load_wb_single : UInt<1>, clk with : - reset => (UInt<1>("h0"), load_wb_single) - when io.dmem_resp_val : - load_wb_single <= T_339 - skip - reg load_wb_data : UInt<64>, clk with : - reset => (UInt<1>("h0"), load_wb_data) - when io.dmem_resp_val : - load_wb_data <= io.dmem_resp_data - skip - reg load_wb_tag : UInt<5>, clk with : - reset => (UInt<1>("h0"), load_wb_tag) - when io.dmem_resp_val : - load_wb_tag <= io.dmem_resp_tag - skip - node T_343 = bits(load_wb_data, 31, 31) - node T_344 = bits(load_wb_data, 30, 23) - node T_345 = bits(load_wb_data, 22, 0) - node T_347 = eq(T_344, UInt<1>("h0")) - node T_349 = eq(T_345, UInt<1>("h0")) - node T_350 = and(T_347, T_349) - node T_351 = shl(T_345, 9) - node T_352 = bits(T_351, 31, 31) - node T_354 = bits(T_351, 30, 30) - node T_356 = bits(T_351, 29, 29) - node T_358 = bits(T_351, 28, 28) - node T_360 = bits(T_351, 27, 27) - node T_362 = bits(T_351, 26, 26) - node T_364 = bits(T_351, 25, 25) - node T_366 = bits(T_351, 24, 24) - node T_368 = bits(T_351, 23, 23) - node T_370 = bits(T_351, 22, 22) - node T_372 = bits(T_351, 21, 21) - node T_374 = bits(T_351, 20, 20) - node T_376 = bits(T_351, 19, 19) - node T_378 = bits(T_351, 18, 18) - node T_380 = bits(T_351, 17, 17) - node T_382 = bits(T_351, 16, 16) - node T_384 = bits(T_351, 15, 15) - node T_386 = bits(T_351, 14, 14) - node T_388 = bits(T_351, 13, 13) - node T_390 = bits(T_351, 12, 12) - node T_392 = bits(T_351, 11, 11) - node T_394 = bits(T_351, 10, 10) - node T_396 = bits(T_351, 9, 9) - node T_398 = bits(T_351, 8, 8) - node T_400 = bits(T_351, 7, 7) - node T_402 = bits(T_351, 6, 6) - node T_404 = bits(T_351, 5, 5) - node T_406 = bits(T_351, 4, 4) - node T_408 = bits(T_351, 3, 3) - node T_410 = bits(T_351, 2, 2) - node T_412 = bits(T_351, 1, 1) - node T_413 = shl(T_412, 0) - node T_414 = mux(T_410, UInt<2>("h2"), T_413) - node T_415 = mux(T_408, UInt<2>("h3"), T_414) - node T_416 = mux(T_406, UInt<3>("h4"), T_415) - node T_417 = mux(T_404, UInt<3>("h5"), T_416) - node T_418 = mux(T_402, UInt<3>("h6"), T_417) - node T_419 = mux(T_400, UInt<3>("h7"), T_418) - node T_420 = mux(T_398, UInt<4>("h8"), T_419) - node T_421 = mux(T_396, UInt<4>("h9"), T_420) - node T_422 = mux(T_394, UInt<4>("ha"), T_421) - node T_423 = mux(T_392, UInt<4>("hb"), T_422) - node T_424 = mux(T_390, UInt<4>("hc"), T_423) - node T_425 = mux(T_388, UInt<4>("hd"), T_424) - node T_426 = mux(T_386, UInt<4>("he"), T_425) - node T_427 = mux(T_384, UInt<4>("hf"), T_426) - node T_428 = mux(T_382, UInt<5>("h10"), T_427) - node T_429 = mux(T_380, UInt<5>("h11"), T_428) - node T_430 = mux(T_378, UInt<5>("h12"), T_429) - node T_431 = mux(T_376, UInt<5>("h13"), T_430) - node T_432 = mux(T_374, UInt<5>("h14"), T_431) - node T_433 = mux(T_372, UInt<5>("h15"), T_432) - node T_434 = mux(T_370, UInt<5>("h16"), T_433) - node T_435 = mux(T_368, UInt<5>("h17"), T_434) - node T_436 = mux(T_366, UInt<5>("h18"), T_435) - node T_437 = mux(T_364, UInt<5>("h19"), T_436) - node T_438 = mux(T_362, UInt<5>("h1a"), T_437) - node T_439 = mux(T_360, UInt<5>("h1b"), T_438) - node T_440 = mux(T_358, UInt<5>("h1c"), T_439) - node T_441 = mux(T_356, UInt<5>("h1d"), T_440) - node T_442 = mux(T_354, UInt<5>("h1e"), T_441) - node T_443 = mux(T_352, UInt<5>("h1f"), T_442) - node T_444 = not(T_443) - node T_445 = dshl(T_345, T_444) - node T_446 = bits(T_445, 21, 0) - node T_448 = cat(T_446, UInt<1>("h0")) - node T_451 = sub(UInt<9>("h0"), UInt<1>("h1")) - node T_452 = tail(T_451, 1) - node T_453 = xor(T_444, T_452) - node T_454 = mux(T_347, T_453, T_344) - node T_458 = mux(T_347, UInt<2>("h2"), UInt<1>("h1")) - node T_459 = or(UInt<8>("h80"), T_458) - node T_460 = add(T_454, T_459) - node T_461 = tail(T_460, 1) - node T_462 = bits(T_461, 8, 7) - node T_464 = eq(T_462, UInt<2>("h3")) - node T_466 = eq(T_349, UInt<1>("h0")) - node T_467 = and(T_464, T_466) - node T_469 = sub(UInt<3>("h0"), T_350) - node T_470 = tail(T_469, 1) - node T_471 = shl(T_470, 6) - node T_472 = not(T_471) - node T_473 = and(T_461, T_472) - node T_474 = shl(T_467, 6) - node T_475 = or(T_473, T_474) - node T_476 = mux(T_347, T_448, T_345) - node T_477 = cat(T_475, T_476) - node rec_s = cat(T_343, T_477) - node T_479 = bits(load_wb_data, 63, 63) - node T_480 = bits(load_wb_data, 62, 52) - node T_481 = bits(load_wb_data, 51, 0) - node T_483 = eq(T_480, UInt<1>("h0")) - node T_485 = eq(T_481, UInt<1>("h0")) - node T_486 = and(T_483, T_485) - node T_487 = shl(T_481, 12) - node T_488 = bits(T_487, 63, 63) - node T_490 = bits(T_487, 62, 62) - node T_492 = bits(T_487, 61, 61) - node T_494 = bits(T_487, 60, 60) - node T_496 = bits(T_487, 59, 59) - node T_498 = bits(T_487, 58, 58) - node T_500 = bits(T_487, 57, 57) - node T_502 = bits(T_487, 56, 56) - node T_504 = bits(T_487, 55, 55) - node T_506 = bits(T_487, 54, 54) - node T_508 = bits(T_487, 53, 53) - node T_510 = bits(T_487, 52, 52) - node T_512 = bits(T_487, 51, 51) - node T_514 = bits(T_487, 50, 50) - node T_516 = bits(T_487, 49, 49) - node T_518 = bits(T_487, 48, 48) - node T_520 = bits(T_487, 47, 47) - node T_522 = bits(T_487, 46, 46) - node T_524 = bits(T_487, 45, 45) - node T_526 = bits(T_487, 44, 44) - node T_528 = bits(T_487, 43, 43) - node T_530 = bits(T_487, 42, 42) - node T_532 = bits(T_487, 41, 41) - node T_534 = bits(T_487, 40, 40) - node T_536 = bits(T_487, 39, 39) - node T_538 = bits(T_487, 38, 38) - node T_540 = bits(T_487, 37, 37) - node T_542 = bits(T_487, 36, 36) - node T_544 = bits(T_487, 35, 35) - node T_546 = bits(T_487, 34, 34) - node T_548 = bits(T_487, 33, 33) - node T_550 = bits(T_487, 32, 32) - node T_552 = bits(T_487, 31, 31) - node T_554 = bits(T_487, 30, 30) - node T_556 = bits(T_487, 29, 29) - node T_558 = bits(T_487, 28, 28) - node T_560 = bits(T_487, 27, 27) - node T_562 = bits(T_487, 26, 26) - node T_564 = bits(T_487, 25, 25) - node T_566 = bits(T_487, 24, 24) - node T_568 = bits(T_487, 23, 23) - node T_570 = bits(T_487, 22, 22) - node T_572 = bits(T_487, 21, 21) - node T_574 = bits(T_487, 20, 20) - node T_576 = bits(T_487, 19, 19) - node T_578 = bits(T_487, 18, 18) - node T_580 = bits(T_487, 17, 17) - node T_582 = bits(T_487, 16, 16) - node T_584 = bits(T_487, 15, 15) - node T_586 = bits(T_487, 14, 14) - node T_588 = bits(T_487, 13, 13) - node T_590 = bits(T_487, 12, 12) - node T_592 = bits(T_487, 11, 11) - node T_594 = bits(T_487, 10, 10) - node T_596 = bits(T_487, 9, 9) - node T_598 = bits(T_487, 8, 8) - node T_600 = bits(T_487, 7, 7) - node T_602 = bits(T_487, 6, 6) - node T_604 = bits(T_487, 5, 5) - node T_606 = bits(T_487, 4, 4) - node T_608 = bits(T_487, 3, 3) - node T_610 = bits(T_487, 2, 2) - node T_612 = bits(T_487, 1, 1) - node T_613 = shl(T_612, 0) - node T_614 = mux(T_610, UInt<2>("h2"), T_613) - node T_615 = mux(T_608, UInt<2>("h3"), T_614) - node T_616 = mux(T_606, UInt<3>("h4"), T_615) - node T_617 = mux(T_604, UInt<3>("h5"), T_616) - node T_618 = mux(T_602, UInt<3>("h6"), T_617) - node T_619 = mux(T_600, UInt<3>("h7"), T_618) - node T_620 = mux(T_598, UInt<4>("h8"), T_619) - node T_621 = mux(T_596, UInt<4>("h9"), T_620) - node T_622 = mux(T_594, UInt<4>("ha"), T_621) - node T_623 = mux(T_592, UInt<4>("hb"), T_622) - node T_624 = mux(T_590, UInt<4>("hc"), T_623) - node T_625 = mux(T_588, UInt<4>("hd"), T_624) - node T_626 = mux(T_586, UInt<4>("he"), T_625) - node T_627 = mux(T_584, UInt<4>("hf"), T_626) - node T_628 = mux(T_582, UInt<5>("h10"), T_627) - node T_629 = mux(T_580, UInt<5>("h11"), T_628) - node T_630 = mux(T_578, UInt<5>("h12"), T_629) - node T_631 = mux(T_576, UInt<5>("h13"), T_630) - node T_632 = mux(T_574, UInt<5>("h14"), T_631) - node T_633 = mux(T_572, UInt<5>("h15"), T_632) - node T_634 = mux(T_570, UInt<5>("h16"), T_633) - node T_635 = mux(T_568, UInt<5>("h17"), T_634) - node T_636 = mux(T_566, UInt<5>("h18"), T_635) - node T_637 = mux(T_564, UInt<5>("h19"), T_636) - node T_638 = mux(T_562, UInt<5>("h1a"), T_637) - node T_639 = mux(T_560, UInt<5>("h1b"), T_638) - node T_640 = mux(T_558, UInt<5>("h1c"), T_639) - node T_641 = mux(T_556, UInt<5>("h1d"), T_640) - node T_642 = mux(T_554, UInt<5>("h1e"), T_641) - node T_643 = mux(T_552, UInt<5>("h1f"), T_642) - node T_644 = mux(T_550, UInt<6>("h20"), T_643) - node T_645 = mux(T_548, UInt<6>("h21"), T_644) - node T_646 = mux(T_546, UInt<6>("h22"), T_645) - node T_647 = mux(T_544, UInt<6>("h23"), T_646) - node T_648 = mux(T_542, UInt<6>("h24"), T_647) - node T_649 = mux(T_540, UInt<6>("h25"), T_648) - node T_650 = mux(T_538, UInt<6>("h26"), T_649) - node T_651 = mux(T_536, UInt<6>("h27"), T_650) - node T_652 = mux(T_534, UInt<6>("h28"), T_651) - node T_653 = mux(T_532, UInt<6>("h29"), T_652) - node T_654 = mux(T_530, UInt<6>("h2a"), T_653) - node T_655 = mux(T_528, UInt<6>("h2b"), T_654) - node T_656 = mux(T_526, UInt<6>("h2c"), T_655) - node T_657 = mux(T_524, UInt<6>("h2d"), T_656) - node T_658 = mux(T_522, UInt<6>("h2e"), T_657) - node T_659 = mux(T_520, UInt<6>("h2f"), T_658) - node T_660 = mux(T_518, UInt<6>("h30"), T_659) - node T_661 = mux(T_516, UInt<6>("h31"), T_660) - node T_662 = mux(T_514, UInt<6>("h32"), T_661) - node T_663 = mux(T_512, UInt<6>("h33"), T_662) - node T_664 = mux(T_510, UInt<6>("h34"), T_663) - node T_665 = mux(T_508, UInt<6>("h35"), T_664) - node T_666 = mux(T_506, UInt<6>("h36"), T_665) - node T_667 = mux(T_504, UInt<6>("h37"), T_666) - node T_668 = mux(T_502, UInt<6>("h38"), T_667) - node T_669 = mux(T_500, UInt<6>("h39"), T_668) - node T_670 = mux(T_498, UInt<6>("h3a"), T_669) - node T_671 = mux(T_496, UInt<6>("h3b"), T_670) - node T_672 = mux(T_494, UInt<6>("h3c"), T_671) - node T_673 = mux(T_492, UInt<6>("h3d"), T_672) - node T_674 = mux(T_490, UInt<6>("h3e"), T_673) - node T_675 = mux(T_488, UInt<6>("h3f"), T_674) - node T_676 = not(T_675) - node T_677 = dshl(T_481, T_676) - node T_678 = bits(T_677, 50, 0) - node T_680 = cat(T_678, UInt<1>("h0")) - node T_683 = sub(UInt<12>("h0"), UInt<1>("h1")) - node T_684 = tail(T_683, 1) - node T_685 = xor(T_676, T_684) - node T_686 = mux(T_483, T_685, T_480) - node T_690 = mux(T_483, UInt<2>("h2"), UInt<1>("h1")) - node T_691 = or(UInt<11>("h400"), T_690) - node T_692 = add(T_686, T_691) - node T_693 = tail(T_692, 1) - node T_694 = bits(T_693, 11, 10) - node T_696 = eq(T_694, UInt<2>("h3")) - node T_698 = eq(T_485, UInt<1>("h0")) - node T_699 = and(T_696, T_698) - node T_701 = sub(UInt<3>("h0"), T_486) - node T_702 = tail(T_701, 1) - node T_703 = shl(T_702, 9) - node T_704 = not(T_703) - node T_705 = and(T_693, T_704) - node T_706 = shl(T_699, 9) - node T_707 = or(T_705, T_706) - node T_708 = mux(T_483, T_680, T_481) - node T_709 = cat(T_707, T_708) - node rec_d = cat(T_479, T_709) - node T_712 = asUInt(asSInt(UInt<32>("hffffffff"))) - node T_713 = cat(T_712, rec_s) - node load_wb_data_recoded = mux(load_wb_single, T_713, rec_d) - mem regfile : - data-type => UInt<65> - depth => 32 - write-latency => 1 - read-latency => 0 - reader => ex_rs1 - reader => ex_rs2 - reader => ex_rs3 - writer => T_718 - writer => T_985 - regfile.ex_rs1.addr is invalid - regfile.ex_rs1.clk <= clk - regfile.ex_rs2.addr is invalid - regfile.ex_rs2.clk <= clk - regfile.ex_rs3.addr is invalid - regfile.ex_rs3.clk <= clk - regfile.ex_rs1.en <= UInt<1>("h0") - regfile.ex_rs2.en <= UInt<1>("h0") - regfile.ex_rs3.en <= UInt<1>("h0") - regfile.T_718.addr is invalid - regfile.T_718.clk <= clk - regfile.T_985.addr is invalid - regfile.T_985.clk <= clk - regfile.T_718.en <= UInt<1>("h0") - regfile.T_985.en <= UInt<1>("h0") - regfile.T_718.data is invalid - regfile.T_718.mask <= UInt<1>("h0") - regfile.T_985.data is invalid - regfile.T_985.mask <= UInt<1>("h0") - when load_wb : - regfile.T_718.addr <= load_wb_tag - regfile.T_718.en <= UInt<1>("h1") - regfile.T_718.data <= load_wb_data_recoded - regfile.T_718.mask <= UInt<1>("h1") - skip - reg ex_ra1 : UInt, clk with : - reset => (UInt<1>("h0"), ex_ra1) - reg ex_ra2 : UInt, clk with : - reset => (UInt<1>("h0"), ex_ra2) - reg ex_ra3 : UInt, clk with : - reset => (UInt<1>("h0"), ex_ra3) - when io.valid : - when fp_decoder.io.sigs.ren1 : - node T_726 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h0")) - when T_726 : - node T_727 = bits(io.inst, 19, 15) - ex_ra1 <= T_727 - skip - when fp_decoder.io.sigs.swap12 : - node T_728 = bits(io.inst, 19, 15) - ex_ra2 <= T_728 - skip - skip - when fp_decoder.io.sigs.ren2 : - when fp_decoder.io.sigs.swap12 : - node T_729 = bits(io.inst, 24, 20) - ex_ra1 <= T_729 - skip - when fp_decoder.io.sigs.swap23 : - node T_730 = bits(io.inst, 24, 20) - ex_ra3 <= T_730 - skip - node T_732 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h0")) - node T_734 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h0")) - node T_735 = and(T_732, T_734) - when T_735 : - node T_736 = bits(io.inst, 24, 20) - ex_ra2 <= T_736 - skip - skip - when fp_decoder.io.sigs.ren3 : - node T_737 = bits(io.inst, 31, 27) - ex_ra3 <= T_737 - skip - skip - regfile.ex_rs1.addr <= ex_ra1 - regfile.ex_rs1.en <= UInt<1>("h1") - regfile.ex_rs2.addr <= ex_ra2 - regfile.ex_rs2.en <= UInt<1>("h1") - regfile.ex_rs3.addr <= ex_ra3 - regfile.ex_rs3.en <= UInt<1>("h1") - node T_741 = bits(ex_reg_inst, 14, 12) - node T_743 = eq(T_741, UInt<3>("h7")) - node T_744 = bits(ex_reg_inst, 14, 12) - node ex_rm = mux(T_743, io.fcsr_rm, T_744) - node cp_rs2 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in3, io.cp_req.bits.in2) - node cp_rs3 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in2, io.cp_req.bits.in3) - wire req : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} - req is invalid - req <- ex_ctrl - node T_794 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm) - req.rm <= T_794 - node T_795 = mux(ex_reg_valid, regfile.ex_rs1.data, io.cp_req.bits.in1) - req.in1 <= T_795 - node T_796 = mux(ex_reg_valid, regfile.ex_rs2.data, cp_rs2) - req.in2 <= T_796 - node T_797 = mux(ex_reg_valid, regfile.ex_rs3.data, cp_rs3) - req.in3 <= T_797 - node T_798 = bits(ex_reg_inst, 21, 20) - node T_799 = mux(ex_reg_valid, T_798, io.cp_req.bits.typ) - req.typ <= T_799 - inst sfma of FPUFMAPipe - sfma.io is invalid - sfma.clk <= clk - sfma.reset <= reset - node T_801 = and(req_valid, ex_ctrl.fma) - node T_802 = and(T_801, ex_ctrl.single) - sfma.io.in.valid <= T_802 - sfma.io.in.bits <- req - inst dfma of FPUFMAPipe_113 - dfma.io is invalid - dfma.clk <= clk - dfma.reset <= reset - node T_804 = and(req_valid, ex_ctrl.fma) - node T_806 = eq(ex_ctrl.single, UInt<1>("h0")) - node T_807 = and(T_804, T_806) - dfma.io.in.valid <= T_807 - dfma.io.in.bits <- req - inst fpiu of FPToInt - fpiu.io is invalid - fpiu.clk <= clk - fpiu.reset <= reset - node T_809 = or(ex_ctrl.toint, ex_ctrl.div) - node T_810 = or(T_809, ex_ctrl.sqrt) - node T_813 = and(ex_ctrl.cmd, UInt<4>("hd")) - node T_814 = eq(UInt<3>("h5"), T_813) - node T_815 = or(T_810, T_814) - node T_816 = and(req_valid, T_815) - fpiu.io.in.valid <= T_816 - fpiu.io.in.bits <- req - io.store_data <= fpiu.io.out.bits.store - io.toint_data <= fpiu.io.out.bits.toint - node T_817 = and(fpiu.io.out.valid, mem_cp_valid) - node T_818 = and(T_817, mem_ctrl.toint) - when T_818 : - io.cp_resp.bits.data <= fpiu.io.out.bits.toint - io.cp_resp.valid <= UInt<1>("h1") - skip - inst ifpu of IntToFP - ifpu.io is invalid - ifpu.clk <= clk - ifpu.reset <= reset - node T_821 = and(req_valid, ex_ctrl.fromint) - ifpu.io.in.valid <= T_821 - ifpu.io.in.bits <- req - node T_822 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1) - ifpu.io.in.bits.in1 <= T_822 - inst fpmu of FPToFP - fpmu.io is invalid - fpmu.clk <= clk - fpmu.reset <= reset - node T_824 = and(req_valid, ex_ctrl.fastpipe) - fpmu.io.in.valid <= T_824 - fpmu.io.in.bits <- req - fpmu.io.lt <= fpiu.io.out.bits.lt - reg divSqrt_wen : UInt<1>, clk with : - reset => (UInt<1>("h0"), divSqrt_wen) - divSqrt_wen <= UInt<1>("h0") - wire divSqrt_inReady : UInt<1> - divSqrt_inReady <= UInt<1>("h0") - reg divSqrt_waddr : UInt, clk with : - reset => (UInt<1>("h0"), divSqrt_waddr) - wire divSqrt_wdata : UInt - divSqrt_wdata is invalid - wire divSqrt_flags : UInt - divSqrt_flags is invalid - reg divSqrt_in_flight : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg divSqrt_killed : UInt<1>, clk with : - reset => (UInt<1>("h0"), divSqrt_killed) - node T_841 = mux(mem_ctrl.fastpipe, UInt<1>("h1"), UInt<1>("h0")) - node T_844 = mux(mem_ctrl.fromint, UInt<2>("h2"), UInt<1>("h0")) - node T_845 = and(mem_ctrl.fma, mem_ctrl.single) - node T_848 = mux(T_845, UInt<1>("h1"), UInt<1>("h0")) - node T_850 = eq(mem_ctrl.single, UInt<1>("h0")) - node T_851 = and(mem_ctrl.fma, T_850) - node T_854 = mux(T_851, UInt<2>("h2"), UInt<1>("h0")) - node T_855 = or(T_841, T_844) - node T_856 = or(T_855, T_848) - node memLatencyMask = or(T_856, T_854) - reg wen : UInt<2>, clk with : - reset => (reset, UInt<2>("h0")) - reg winfo : UInt[2], clk with : - reset => (UInt<1>("h0"), winfo) - node T_872 = or(mem_ctrl.fma, mem_ctrl.fastpipe) - node T_873 = or(T_872, mem_ctrl.fromint) - node mem_wen = and(mem_reg_valid, T_873) - node T_877 = mux(ex_ctrl.fastpipe, UInt<2>("h2"), UInt<1>("h0")) - node T_880 = mux(ex_ctrl.fromint, UInt<3>("h4"), UInt<1>("h0")) - node T_881 = and(ex_ctrl.fma, ex_ctrl.single) - node T_884 = mux(T_881, UInt<2>("h2"), UInt<1>("h0")) - node T_886 = eq(ex_ctrl.single, UInt<1>("h0")) - node T_887 = and(ex_ctrl.fma, T_886) - node T_890 = mux(T_887, UInt<3>("h4"), UInt<1>("h0")) - node T_891 = or(T_877, T_880) - node T_892 = or(T_891, T_884) - node T_893 = or(T_892, T_890) - node T_894 = and(memLatencyMask, T_893) - node T_896 = neq(T_894, UInt<1>("h0")) - node T_897 = and(mem_wen, T_896) - node T_900 = mux(ex_ctrl.fastpipe, UInt<3>("h4"), UInt<1>("h0")) - node T_903 = mux(ex_ctrl.fromint, UInt<4>("h8"), UInt<1>("h0")) - node T_904 = and(ex_ctrl.fma, ex_ctrl.single) - node T_907 = mux(T_904, UInt<3>("h4"), UInt<1>("h0")) - node T_909 = eq(ex_ctrl.single, UInt<1>("h0")) - node T_910 = and(ex_ctrl.fma, T_909) - node T_913 = mux(T_910, UInt<4>("h8"), UInt<1>("h0")) - node T_914 = or(T_900, T_903) - node T_915 = or(T_914, T_907) - node T_916 = or(T_915, T_913) - node T_917 = and(wen, T_916) - node T_919 = neq(T_917, UInt<1>("h0")) - node T_920 = or(T_897, T_919) - reg write_port_busy : UInt<1>, clk with : - reset => (UInt<1>("h0"), write_port_busy) - when req_valid : - write_port_busy <= T_920 - skip - node T_924 = mux(mem_ctrl.fastpipe, UInt<1>("h0"), UInt<1>("h0")) - node T_927 = mux(mem_ctrl.fromint, UInt<1>("h1"), UInt<1>("h0")) - node T_928 = and(mem_ctrl.fma, mem_ctrl.single) - node T_931 = mux(T_928, UInt<2>("h2"), UInt<1>("h0")) - node T_933 = eq(mem_ctrl.single, UInt<1>("h0")) - node T_934 = and(mem_ctrl.fma, T_933) - node T_937 = mux(T_934, UInt<2>("h3"), UInt<1>("h0")) - node T_938 = or(T_924, T_927) - node T_939 = or(T_938, T_931) - node T_940 = or(T_939, T_937) - node T_941 = bits(mem_reg_inst, 11, 7) - node T_942 = cat(mem_cp_valid, T_940) - node T_943 = cat(mem_ctrl.single, T_941) - node mem_winfo = cat(T_942, T_943) - node T_945 = bits(wen, 1, 1) - when T_945 : - winfo[0] <= winfo[1] - skip - node T_946 = shr(wen, 1) - wen <= T_946 - when mem_wen : - node T_948 = eq(killm, UInt<1>("h0")) - when T_948 : - node T_949 = shr(wen, 1) - node T_950 = or(T_949, memLatencyMask) - wen <= T_950 - skip - node T_952 = eq(write_port_busy, UInt<1>("h0")) - node T_953 = bits(memLatencyMask, 0, 0) - node T_954 = and(T_952, T_953) - when T_954 : - winfo[0] <= mem_winfo - skip - node T_956 = eq(write_port_busy, UInt<1>("h0")) - node T_957 = bits(memLatencyMask, 1, 1) - node T_958 = and(T_956, T_957) - when T_958 : - winfo[1] <= mem_winfo - skip - skip - node T_959 = bits(winfo[0], 4, 0) - node waddr = mux(divSqrt_wen, divSqrt_waddr, T_959) - node wsrc = shr(winfo[0], 6) - node wcp = bits(winfo[0], 8, 8) - wire T_964 : UInt<65>[4] - T_964[0] <= fpmu.io.out.bits.data - T_964[1] <= ifpu.io.out.bits.data - T_964[2] <= sfma.io.out.bits.data - T_964[3] <= dfma.io.out.bits.data - node wdata = mux(divSqrt_wen, divSqrt_wdata, T_964[wsrc]) - wire T_973 : UInt<5>[4] - T_973[0] <= fpmu.io.out.bits.exc - T_973[1] <= ifpu.io.out.bits.exc - T_973[2] <= sfma.io.out.bits.exc - T_973[3] <= dfma.io.out.bits.exc - node T_981 = eq(wcp, UInt<1>("h0")) - node T_982 = bits(wen, 0, 0) - node T_983 = and(T_981, T_982) - node T_984 = or(T_983, divSqrt_wen) - when T_984 : - regfile.T_985.addr <= waddr - regfile.T_985.en <= UInt<1>("h1") - regfile.T_985.data <= wdata - regfile.T_985.mask <= UInt<1>("h1") - skip - node T_986 = bits(wen, 0, 0) - node T_987 = and(wcp, T_986) - when T_987 : - io.cp_resp.bits.data <= wdata - io.cp_resp.valid <= UInt<1>("h1") - skip - node T_990 = eq(ex_reg_valid, UInt<1>("h0")) - io.cp_req.ready <= T_990 - node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) - reg wb_toint_exc : UInt<5>, clk with : - reset => (UInt<1>("h0"), wb_toint_exc) - when mem_ctrl.toint : - wb_toint_exc <= fpiu.io.out.bits.exc - skip - node T_993 = or(wb_toint_valid, divSqrt_wen) - node T_994 = bits(wen, 0, 0) - node T_995 = or(T_993, T_994) - io.fcsr_flags.valid <= T_995 - node T_997 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h0")) - node T_999 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h0")) - node T_1000 = or(T_997, T_999) - node T_1001 = bits(wen, 0, 0) - node T_1003 = mux(T_1001, T_973[wsrc], UInt<1>("h0")) - node T_1004 = or(T_1000, T_1003) - io.fcsr_flags.bits <= T_1004 - node T_1005 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1006 = and(mem_reg_valid, T_1005) - node T_1008 = eq(divSqrt_inReady, UInt<1>("h0")) - node T_1010 = neq(wen, UInt<1>("h0")) - node T_1011 = or(T_1008, T_1010) - node units_busy = and(T_1006, T_1011) - node T_1013 = and(ex_reg_valid, ex_ctrl.wflags) - node T_1014 = and(mem_reg_valid, mem_ctrl.wflags) - node T_1015 = or(T_1013, T_1014) - node T_1016 = and(wb_reg_valid, wb_ctrl.toint) - node T_1017 = or(T_1015, T_1016) - node T_1019 = neq(wen, UInt<1>("h0")) - node T_1020 = or(T_1017, T_1019) - node T_1021 = or(T_1020, divSqrt_in_flight) - node T_1023 = eq(T_1021, UInt<1>("h0")) - io.fcsr_rdy <= T_1023 - node T_1024 = or(units_busy, write_port_busy) - node T_1025 = or(T_1024, divSqrt_in_flight) - io.nack_mem <= T_1025 - io.dec <- fp_decoder.io.sigs - node T_1027 = eq(wb_cp_valid, UInt<1>("h0")) - node T_1028 = and(wb_reg_valid, T_1027) - node T_1030 = or(UInt<1>("h0"), mem_ctrl.div) - node T_1031 = or(T_1030, mem_ctrl.sqrt) - reg T_1032 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_1032) - T_1032 <= T_1031 - node T_1033 = and(T_1028, T_1032) - io.sboard_set <= T_1033 - node T_1035 = eq(wb_cp_valid, UInt<1>("h0")) - node T_1036 = bits(wen, 0, 0) - node T_1038 = and(T_1036, UInt<1>("h0")) - node T_1039 = or(divSqrt_wen, T_1038) - node T_1040 = and(T_1035, T_1039) - io.sboard_clr <= T_1040 - io.sboard_clra <= waddr - node T_1041 = bits(ex_rm, 2, 2) - node T_1042 = and(T_1041, ex_ctrl.round) - io.illegal_rm <= T_1042 - divSqrt_wdata <= UInt<1>("h0") - divSqrt_flags <= UInt<1>("h0") - reg T_1046 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_1046) - reg T_1048 : UInt, clk with : - reset => (UInt<1>("h0"), T_1048) - reg T_1050 : UInt, clk with : - reset => (UInt<1>("h0"), T_1050) - reg T_1052 : UInt, clk with : - reset => (UInt<1>("h0"), T_1052) - inst T_1053 of DivSqrtRecF64 - T_1053.io is invalid - T_1053.clk <= clk - T_1053.reset <= reset - node T_1054 = mux(T_1053.io.sqrtOp, T_1053.io.inReady_sqrt, T_1053.io.inReady_div) - divSqrt_inReady <= T_1054 - node T_1055 = or(T_1053.io.outValid_div, T_1053.io.outValid_sqrt) - node T_1056 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1057 = and(mem_reg_valid, T_1056) - node T_1059 = eq(divSqrt_in_flight, UInt<1>("h0")) - node T_1060 = and(T_1057, T_1059) - T_1053.io.inValid <= T_1060 - T_1053.io.sqrtOp <= mem_ctrl.sqrt - T_1053.io.a <= fpiu.io.as_double.in1 - T_1053.io.b <= fpiu.io.as_double.in2 - T_1053.io.roundingMode <= fpiu.io.as_double.rm - node T_1061 = and(T_1053.io.inValid, divSqrt_inReady) - when T_1061 : - divSqrt_in_flight <= UInt<1>("h1") - divSqrt_killed <= killm - T_1046 <= mem_ctrl.single - node T_1063 = bits(mem_reg_inst, 11, 7) - divSqrt_waddr <= T_1063 - T_1048 <= T_1053.io.roundingMode - skip - when T_1055 : - node T_1065 = eq(divSqrt_killed, UInt<1>("h0")) - divSqrt_wen <= T_1065 - T_1052 <= T_1053.io.out - divSqrt_in_flight <= UInt<1>("h0") - T_1050 <= T_1053.io.exceptionFlags - skip - inst T_1067 of RecFNToRecFN_121 - T_1067.io is invalid - T_1067.clk <= clk - T_1067.reset <= reset - T_1067.io.in <= T_1052 - T_1067.io.roundingMode <= ex_rm - node T_1068 = mux(T_1046, T_1067.io.out, T_1052) - divSqrt_wdata <= T_1068 - node T_1070 = mux(T_1046, T_1067.io.exceptionFlags, UInt<1>("h0")) - node T_1071 = or(T_1050, T_1070) - divSqrt_flags <= T_1071 - module RocketTile : - input clk : Clock - input reset : UInt<1> - output io : { cached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], uncached : { acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, dma : { req : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<2>, status : UInt<2>}}}} - io is invalid - inst core of Rocket - core.io is invalid - core.clk <= clk - core.reset <= reset - inst icache of Frontend - icache.io is invalid - icache.clk <= clk - icache.reset <= reset - inst dcache of HellaCache - dcache.io is invalid - dcache.clk <= clk - dcache.reset <= reset - inst ptw of PTW - ptw.io is invalid - ptw.clk <= clk - ptw.reset <= reset - dcache.io.cpu.invalidate_lr <= core.io.dmem.invalidate_lr - inst dcArb of HellaCacheArbiter - dcArb.io is invalid - dcArb.clk <= clk - dcArb.reset <= reset - dcArb.io.requestor[0] <- ptw.io.mem - dcArb.io.requestor[1] <- core.io.dmem - dcache.io.cpu <- dcArb.io.mem - ptw.io.requestor[0] <- icache.io.ptw - ptw.io.requestor[1] <- dcache.io.ptw - io.host <- core.io.host - icache.io.cpu <- core.io.imem - core.io.ptw <- ptw.io.dpath - inst T_3284 of FPU - T_3284.io is invalid - T_3284.clk <= clk - T_3284.reset <= reset - core.io.fpu <- T_3284.io - io.cached[0] <- dcache.io.mem - io.uncached[0] <- icache.io.mem - T_3284.io.cp_req.valid <= UInt<1>("h0") - T_3284.io.cp_resp.ready <= UInt<1>("h0") - io.dma.req.valid <= UInt<1>("h0") - io.dma.resp.ready <= UInt<1>("h0") - module Queue_124 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : { rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>} - io is invalid - mem ram : - data-type => { rw : UInt<1>, addr : UInt<12>, data : UInt<64>} - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_107 - writer => T_74 - ram.T_107.addr is invalid - ram.T_107.clk <= clk - ram.T_107.en <= UInt<1>("h0") - ram.T_74.addr is invalid - ram.T_74.clk <= clk - ram.T_74.en <= UInt<1>("h0") - ram.T_74.data is invalid - ram.T_74.mask.rw <= UInt<1>("h0") - ram.T_74.mask.addr <= UInt<1>("h0") - ram.T_74.mask.data <= UInt<1>("h0") - reg T_53 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_55 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_53, T_55) - node T_60 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_60) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_66 = and(io.enq.ready, io.enq.valid) - node T_68 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_66, T_68) - node T_70 = and(io.deq.ready, io.deq.valid) - node T_72 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_70, T_72) - when do_enq : - ram.T_74.addr <= T_53 - ram.T_74.en <= UInt<1>("h1") - ram.T_74.data <- io.enq.bits - ram.T_74.mask.rw <= UInt<1>("h1") - ram.T_74.mask.addr <= UInt<1>("h1") - ram.T_74.mask.data <= UInt<1>("h1") - node T_79 = eq(T_53, UInt<1>("h1")) - node T_81 = and(UInt<1>("h0"), T_79) - node T_84 = add(T_53, UInt<1>("h1")) - node T_85 = tail(T_84, 1) - node T_86 = mux(T_81, UInt<1>("h0"), T_85) - T_53 <= T_86 - skip - when do_deq : - node T_88 = eq(T_55, UInt<1>("h1")) - node T_90 = and(UInt<1>("h0"), T_88) - node T_93 = add(T_55, UInt<1>("h1")) - node T_94 = tail(T_93, 1) - node T_95 = mux(T_90, UInt<1>("h0"), T_94) - T_55 <= T_95 - skip - node T_96 = neq(do_enq, do_deq) - when T_96 : - maybe_full <= do_enq - skip - node T_98 = eq(empty, UInt<1>("h0")) - node T_100 = and(UInt<1>("h0"), io.enq.valid) - node T_101 = or(T_98, T_100) - io.deq.valid <= T_101 - node T_103 = eq(full, UInt<1>("h0")) - node T_105 = and(UInt<1>("h0"), io.deq.ready) - node T_106 = or(T_103, T_105) - io.enq.ready <= T_106 - ram.T_107.addr <= T_55 - ram.T_107.en <= UInt<1>("h1") - node T_111 = mux(maybe_flow, io.enq.bits, ram.T_107.data) - io.deq.bits <- T_111 - node T_115 = sub(T_53, T_55) - node ptr_diff = tail(T_115, 1) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - io.count <= T_118 - module Queue_125 : - input clk : Clock - input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>} - io is invalid - mem ram : - data-type => UInt<64> - depth => 2 - write-latency => 1 - read-latency => 0 - reader => T_77 - writer => T_47 - ram.T_77.addr is invalid - ram.T_77.clk <= clk - ram.T_77.en <= UInt<1>("h0") - ram.T_47.addr is invalid - ram.T_47.clk <= clk - ram.T_47.en <= UInt<1>("h0") - ram.T_47.data is invalid - ram.T_47.mask <= UInt<1>("h0") - reg T_26 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg T_28 : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - reg maybe_full : UInt<1>, clk with : - reset => (reset, UInt<1>("h0")) - node ptr_match = eq(T_26, T_28) - node T_33 = eq(maybe_full, UInt<1>("h0")) - node empty = and(ptr_match, T_33) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h0"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_39 = and(io.enq.ready, io.enq.valid) - node T_41 = eq(do_flow, UInt<1>("h0")) - node do_enq = and(T_39, T_41) - node T_43 = and(io.deq.ready, io.deq.valid) - node T_45 = eq(do_flow, UInt<1>("h0")) - node do_deq = and(T_43, T_45) - when do_enq : - ram.T_47.addr <= T_26 - ram.T_47.en <= UInt<1>("h1") - ram.T_47.data <= io.enq.bits - ram.T_47.mask <= UInt<1>("h1") - node T_49 = eq(T_26, UInt<1>("h1")) - node T_51 = and(UInt<1>("h0"), T_49) - node T_54 = add(T_26, UInt<1>("h1")) - node T_55 = tail(T_54, 1) - node T_56 = mux(T_51, UInt<1>("h0"), T_55) - T_26 <= T_56 - skip - when do_deq : - node T_58 = eq(T_28, UInt<1>("h1")) - node T_60 = and(UInt<1>("h0"), T_58) - node T_63 = add(T_28, UInt<1>("h1")) - node T_64 = tail(T_63, 1) - node T_65 = mux(T_60, UInt<1>("h0"), T_64) - T_28 <= T_65 - skip - node T_66 = neq(do_enq, do_deq) - when T_66 : - maybe_full <= do_enq - skip - node T_68 = eq(empty, UInt<1>("h0")) - node T_70 = and(UInt<1>("h0"), io.enq.valid) - node T_71 = or(T_68, T_70) - io.deq.valid <= T_71 - node T_73 = eq(full, UInt<1>("h0")) - node T_75 = and(UInt<1>("h0"), io.deq.ready) - node T_76 = or(T_73, T_75) - io.enq.ready <= T_76 - ram.T_77.addr <= T_28 - ram.T_77.en <= UInt<1>("h1") - node T_78 = mux(maybe_flow, io.enq.bits, ram.T_77.data) - io.deq.bits <= T_78 - node T_79 = sub(T_26, T_28) - node ptr_diff = tail(T_79, 1) - node T_81 = and(maybe_full, ptr_match) - node T_82 = cat(T_81, ptr_diff) - io.count <= T_82 - module Top : - input clk : Clock - input reset : UInt<1> - output io : { host : { clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : { aw : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1]} - io is invalid - inst uncore of Uncore - uncore.io is invalid - uncore.clk <= clk - uncore.reset <= reset - inst T_669 of RocketTile - T_669.io is invalid - T_669.clk <= clk - T_669.reset <= uncore.io.htif[0].reset - T_669.io.host.id <= UInt<1>("h0") - reg T_671 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_671) - T_671 <= uncore.io.htif[0].reset - reg T_672 : UInt<1>, clk with : - reset => (UInt<1>("h0"), T_672) - T_672 <= T_671 - T_669.io.host.reset <= T_672 - inst T_677 of Queue_124 - T_677.io is invalid - T_677.clk <= clk - T_677.reset <= reset - T_677.io.enq.valid <= uncore.io.htif[0].csr.req.valid - T_677.io.enq.bits <- uncore.io.htif[0].csr.req.bits - uncore.io.htif[0].csr.req.ready <= T_677.io.enq.ready - T_669.io.host.csr.req <- T_677.io.deq - inst T_679 of Queue_125 - T_679.io is invalid - T_679.clk <= clk - T_679.reset <= reset - T_679.io.enq.valid <= T_669.io.host.csr.resp.valid - T_679.io.enq.bits <= T_669.io.host.csr.resp.bits - T_669.io.host.csr.resp.ready <= T_679.io.enq.ready - uncore.io.htif[0].csr.resp <- T_679.io.deq - uncore.io.htif[0].debug_stats_csr <= T_669.io.host.debug_stats_csr - uncore.io.tiles_cached[0] <- T_669.io.cached[0] - uncore.io.tiles_uncached[0] <- T_669.io.uncached[0] - io.host <- uncore.io.host - io.mem_backup_ctrl <- uncore.io.mem_backup_ctrl - inst T_692 of Queue_36 - T_692.io is invalid - T_692.clk <= clk - T_692.reset <= reset - T_692.io.enq.valid <= uncore.io.mem[0].ar.valid - T_692.io.enq.bits <- uncore.io.mem[0].ar.bits - uncore.io.mem[0].ar.ready <= T_692.io.enq.ready - io.mem[0].ar <- T_692.io.deq - inst T_705 of Queue_36 - T_705.io is invalid - T_705.clk <= clk - T_705.reset <= reset - T_705.io.enq.valid <= uncore.io.mem[0].aw.valid - T_705.io.enq.bits <- uncore.io.mem[0].aw.bits - uncore.io.mem[0].aw.ready <= T_705.io.enq.ready - io.mem[0].aw <- T_705.io.deq - inst T_711 of Queue_74 - T_711.io is invalid - T_711.clk <= clk - T_711.reset <= reset - T_711.io.enq.valid <= uncore.io.mem[0].w.valid - T_711.io.enq.bits <- uncore.io.mem[0].w.bits - uncore.io.mem[0].w.ready <= T_711.io.enq.ready - io.mem[0].w <- T_711.io.deq - inst T_718 of Queue_75 - T_718.io is invalid - T_718.clk <= clk - T_718.reset <= reset - T_718.io.enq.valid <= io.mem[0].r.valid - T_718.io.enq.bits <- io.mem[0].r.bits - io.mem[0].r.ready <= T_718.io.enq.ready - uncore.io.mem[0].r <- T_718.io.deq - inst T_723 of Queue_76 - T_723.io is invalid - T_723.clk <= clk - T_723.reset <= reset - T_723.io.enq.valid <= io.mem[0].b.valid - T_723.io.enq.bits <- io.mem[0].b.bits - io.mem[0].b.ready <= T_723.io.enq.ready - uncore.io.mem[0].b <- T_723.io.deq - io.mem[0].ar.bits.cache <= UInt<4>("h3") - io.mem[0].aw.bits.cache <= UInt<4>("h3") - inst errslave of NastiErrorSlave_40 - errslave.io is invalid - errslave.clk <= clk - errslave.reset <= reset - errslave.io <- uncore.io.mmio diff --git a/regress/rocket.0.fir b/regress/rocket.0.fir deleted file mode 100644 index 242ca041..00000000 --- a/regress/rocket.0.fir +++ /dev/null @@ -1,32895 +0,0 @@ -circuit Top : - module HTIF : - output scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>} - output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1] - output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - scr.wdata := UInt<1>("h00") - scr.waddr := UInt<1>("h00") - scr.wen := UInt<1>("h00") - mem_1.grant.ready := UInt<1>("h00") - mem_1.acquire.bits.union := UInt<1>("h00") - mem_1.acquire.bits.a_type := UInt<1>("h00") - mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") - mem_1.acquire.bits.data := UInt<1>("h00") - mem_1.acquire.bits.addr_beat := UInt<1>("h00") - mem_1.acquire.bits.client_xact_id := UInt<1>("h00") - mem_1.acquire.bits.addr_block := UInt<1>("h00") - mem_1.acquire.valid := UInt<1>("h00") - cpu[0].ipi_rep.bits := UInt<1>("h00") - cpu[0].ipi_rep.valid := UInt<1>("h00") - cpu[0].ipi_req.ready := UInt<1>("h00") - cpu[0].pcr_rep.ready := UInt<1>("h00") - cpu[0].pcr_req.bits.data := UInt<1>("h00") - cpu[0].pcr_req.bits.addr := UInt<1>("h00") - cpu[0].pcr_req.bits.rw := UInt<1>("h00") - cpu[0].pcr_req.valid := UInt<1>("h00") - cpu[0].id := UInt<1>("h00") - cpu[0].reset := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.out.bits := UInt<1>("h00") - host.out.valid := UInt<1>("h00") - host.in.ready := UInt<1>("h00") - host.clk_edge := UInt<1>("h00") - host.clk := UInt<1>("h00") - host.debug_stats_pcr := cpu[0].debug_stats_pcr - reg rx_count : UInt<15>, clock, reset - onreset rx_count := UInt<15>("h00") - reg rx_shifter : UInt<64>, clock, reset - node T_804 = bits(rx_shifter, 63, 16) - node rx_shifter_in = cat(host.in.bits, T_804) - node next_cmd = bits(rx_shifter_in, 3, 0) - reg cmd : UInt, clock, reset - reg size : UInt, clock, reset - reg pos : UInt, clock, reset - reg seqno : UInt, clock, reset - reg addr : UInt, clock, reset - node T_817 = and(host.in.valid, host.in.ready) - when T_817 : - rx_shifter := rx_shifter_in - node T_819 = addw(rx_count, UInt<1>("h01")) - rx_count := T_819 - node T_821 = eq(rx_count, UInt<2>("h03")) - when T_821 : - cmd := next_cmd - node T_822 = bits(rx_shifter_in, 15, 4) - size := T_822 - node T_823 = bits(rx_shifter_in, 15, 7) - pos := T_823 - node T_824 = bits(rx_shifter_in, 23, 16) - seqno := T_824 - node T_825 = bits(rx_shifter_in, 63, 24) - addr := T_825 - skip - skip - node rx_word_count = shr(rx_count, 2) - node T_827 = bits(rx_count, 1, 0) - node T_828 = not(T_827) - node T_830 = eq(T_828, UInt<1>("h00")) - node rx_word_done = and(host.in.valid, T_830) - cmem packet_ram : UInt<64>[8], clock - node T_835 = and(rx_word_done, host.in.ready) - when T_835 : - node T_836 = bits(rx_word_count, 2, 0) - node T_838 = subw(T_836, UInt<1>("h01")) - infer accessor T_839 = packet_ram[T_838] - T_839 := rx_shifter_in - skip - node pcr_addr = bits(addr, 11, 0) - node pcr_coreid = bits(addr, 21, 20) - infer accessor pcr_wdata = packet_ram[UInt<1>("h00")] - node T_851 = bits(size, 2, 0) - node T_853 = neq(T_851, UInt<1>("h00")) - node T_854 = bits(addr, 2, 0) - node T_856 = neq(T_854, UInt<1>("h00")) - node bad_mem_packet = or(T_853, T_856) - node T_858 = eq(cmd, UInt<1>("h00")) - node T_859 = eq(cmd, UInt<1>("h01")) - node T_860 = or(T_858, T_859) - node T_861 = eq(cmd, UInt<2>("h02")) - node T_862 = eq(cmd, UInt<2>("h03")) - node T_863 = or(T_861, T_862) - node T_865 = neq(size, UInt<1>("h01")) - node T_867 = mux(T_863, T_865, UInt<1>("h01")) - node nack = mux(T_860, bad_mem_packet, T_867) - reg tx_count : UInt<15>, clock, reset - onreset tx_count := UInt<15>("h00") - node tx_subword_count = bits(tx_count, 1, 0) - node tx_word_count = bits(tx_count, 14, 2) - node T_873 = bits(tx_word_count, 2, 0) - node packet_ram_raddr = subw(T_873, UInt<1>("h01")) - node T_876 = and(host.out.valid, host.out.ready) - when T_876 : - node T_878 = addw(tx_count, UInt<1>("h01")) - tx_count := T_878 - skip - node T_880 = eq(rx_word_count, UInt<1>("h00")) - node T_881 = neq(next_cmd, UInt<1>("h01")) - node T_882 = neq(next_cmd, UInt<2>("h03")) - node T_883 = and(T_881, T_882) - node T_884 = eq(rx_word_count, size) - node T_885 = bits(rx_word_count, 2, 0) - node T_887 = eq(T_885, UInt<1>("h00")) - node T_888 = or(T_884, T_887) - node T_889 = mux(T_880, T_883, T_888) - node rx_done = and(rx_word_done, T_889) - node T_892 = eq(nack, UInt<1>("h00")) - node T_893 = eq(cmd, UInt<1>("h00")) - node T_894 = eq(cmd, UInt<2>("h02")) - node T_895 = or(T_893, T_894) - node T_896 = eq(cmd, UInt<2>("h03")) - node T_897 = or(T_895, T_896) - node T_898 = and(T_892, T_897) - node tx_size = mux(T_898, size, UInt<1>("h00")) - node T_901 = not(tx_subword_count) - node T_903 = eq(T_901, UInt<1>("h00")) - node T_904 = and(host.out.ready, T_903) - node T_905 = eq(tx_word_count, tx_size) - node T_907 = gt(tx_word_count, UInt<1>("h00")) - node T_908 = not(packet_ram_raddr) - node T_910 = eq(T_908, UInt<1>("h00")) - node T_911 = and(T_907, T_910) - node T_912 = or(T_905, T_911) - node tx_done = and(T_904, T_912) - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - node T_924 = eq(state, UInt<3>("h04")) - node T_925 = and(T_924, mem_1.acquire.ready) - node T_926 = eq(state, UInt<3>("h05")) - node T_927 = and(T_926, mem_1.grant.valid) - node T_928 = or(T_925, T_927) - reg cnt : UInt<2>, clock, reset - onreset cnt := UInt<2>("h00") - when T_928 : - node T_932 = eq(cnt, UInt<2>("h03")) - node T_934 = and(UInt<1>("h00"), T_932) - node T_937 = addw(cnt, UInt<1>("h01")) - node T_938 = mux(T_934, UInt<1>("h00"), T_937) - cnt := T_938 - skip - node cnt_done = and(T_928, T_932) - node T_941 = eq(rx_word_count, UInt<1>("h00")) - node rx_cmd = mux(T_941, next_cmd, cmd) - node T_943 = eq(state, UInt<1>("h00")) - node T_944 = and(T_943, rx_done) - when T_944 : - node T_945 = eq(rx_cmd, UInt<1>("h00")) - node T_946 = eq(rx_cmd, UInt<1>("h01")) - node T_947 = eq(rx_cmd, UInt<2>("h02")) - node T_948 = eq(rx_cmd, UInt<2>("h03")) - node T_949 = or(T_947, T_948) - node T_950 = mux(T_949, UInt<1>("h01"), UInt<3>("h07")) - node T_951 = mux(T_946, UInt<3>("h04"), T_950) - node T_952 = mux(T_945, UInt<2>("h03"), T_951) - state := T_952 - skip - node T_953 = eq(state, UInt<3>("h04")) - when T_953 : - when cnt_done : - state := UInt<3>("h06") - skip - skip - node T_954 = eq(state, UInt<2>("h03")) - when T_954 : - when mem_1.acquire.ready : - state := UInt<3>("h05") - skip - skip - node T_955 = eq(state, UInt<3>("h06")) - node T_956 = and(T_955, mem_1.grant.valid) - when T_956 : - node T_957 = eq(cmd, UInt<1>("h00")) - node T_959 = eq(pos, UInt<1>("h01")) - node T_960 = or(T_957, T_959) - node T_961 = mux(T_960, UInt<3>("h07"), UInt<1>("h00")) - state := T_961 - node T_963 = subw(pos, UInt<1>("h01")) - pos := T_963 - node T_965 = addw(addr, UInt<4>("h08")) - addr := T_965 - skip - node T_966 = eq(state, UInt<3>("h05")) - node T_967 = and(T_966, cnt_done) - when T_967 : - node T_968 = eq(cmd, UInt<1>("h00")) - node T_970 = eq(pos, UInt<1>("h01")) - node T_971 = or(T_968, T_970) - node T_972 = mux(T_971, UInt<3>("h07"), UInt<1>("h00")) - state := T_972 - node T_974 = subw(pos, UInt<1>("h01")) - pos := T_974 - node T_976 = addw(addr, UInt<4>("h08")) - addr := T_976 - skip - node T_977 = eq(state, UInt<3>("h07")) - node T_978 = and(T_977, tx_done) - when T_978 : - node T_979 = eq(tx_word_count, tx_size) - when T_979 : - rx_count := UInt<1>("h00") - tx_count := UInt<1>("h00") - skip - node T_982 = eq(cmd, UInt<1>("h00")) - node T_984 = neq(pos, UInt<1>("h00")) - node T_985 = and(T_982, T_984) - node T_986 = mux(T_985, UInt<2>("h03"), UInt<1>("h00")) - state := T_986 - skip - node T_988 = eq(state, UInt<3>("h05")) - node T_989 = and(T_988, mem_1.grant.valid) - when T_989 : - node T_990 = cat(mem_1.grant.bits.addr_beat, UInt<1>("h00")) - infer accessor T_991 = packet_ram[T_990] - node T_992 = bits(mem_1.grant.bits.data, 63, 0) - T_991 := T_992 - skip - node T_993 = cat(cnt, UInt<1>("h00")) - infer accessor T_994 = packet_ram[T_993] - node T_996 = eq(state, UInt<3>("h05")) - node T_997 = and(T_996, mem_1.grant.valid) - when T_997 : - node T_998 = cat(mem_1.grant.bits.addr_beat, UInt<1>("h01")) - infer accessor T_999 = packet_ram[T_998] - node T_1000 = bits(mem_1.grant.bits.data, 127, 64) - T_999 := T_1000 - skip - node T_1001 = cat(cnt, UInt<1>("h01")) - infer accessor T_1002 = packet_ram[T_1001] - node mem_req_data = cat(T_1002, T_994) - node init_addr = shr(addr, 3) - node T_1005 = eq(state, UInt<2>("h03")) - node T_1006 = eq(state, UInt<3>("h04")) - node T_1007 = or(T_1005, T_1006) - mem_1.acquire.valid := T_1007 - node T_1008 = eq(cmd, UInt<1>("h01")) - node T_1045 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_1046 = cat(T_1045, UInt<1>("h01")) - wire T_1078 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_1078.union := UInt<1>("h00") - T_1078.a_type := UInt<1>("h00") - T_1078.is_builtin_type := UInt<1>("h00") - T_1078.data := UInt<1>("h00") - T_1078.addr_beat := UInt<1>("h00") - T_1078.client_xact_id := UInt<1>("h00") - T_1078.addr_block := UInt<1>("h00") - T_1078.is_builtin_type := UInt<1>("h01") - T_1078.a_type := UInt<3>("h03") - T_1078.client_xact_id := UInt<1>("h00") - T_1078.addr_block := init_addr - T_1078.addr_beat := cnt - T_1078.data := mem_req_data - T_1078.union := T_1046 - node T_1120 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1121 = cat(UInt<3>("h07"), T_1120) - wire T_1155 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_1155.union := UInt<1>("h00") - T_1155.a_type := UInt<1>("h00") - T_1155.is_builtin_type := UInt<1>("h00") - T_1155.data := UInt<1>("h00") - T_1155.addr_beat := UInt<1>("h00") - T_1155.client_xact_id := UInt<1>("h00") - T_1155.addr_block := UInt<1>("h00") - T_1155.is_builtin_type := UInt<1>("h01") - T_1155.a_type := UInt<3>("h01") - T_1155.client_xact_id := UInt<1>("h00") - T_1155.addr_block := init_addr - T_1155.addr_beat := UInt<1>("h00") - T_1155.data := UInt<1>("h00") - T_1155.union := T_1121 - wire T_1224 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_1224 <> T_1155 - when T_1008 : - T_1224 <> T_1078 - skip - mem_1.acquire.bits <> T_1224 - mem_1.grant.ready := UInt<1>("h01") - reg rtc : UInt<64>, clock, reset - onreset rtc := UInt<64>("h00") - reg T_1259 : UInt<7>, clock, reset - onreset T_1259 := UInt<7>("h00") - node rtc_tick = eq(T_1259, UInt<7>("h063")) - node T_1263 = and(UInt<1>("h01"), rtc_tick) - node T_1266 = addw(T_1259, UInt<1>("h01")) - node T_1267 = mux(T_1263, UInt<1>("h00"), T_1266) - T_1259 := T_1267 - when rtc_tick : - node T_1269 = addw(rtc, UInt<1>("h01")) - rtc := T_1269 - skip - reg pcrReadData : UInt<64>, clock, reset - reg T_1273 : UInt<1>, clock, reset - onreset T_1273 := UInt<1>("h01") - reg T_1275 : UInt<1>, clock, reset - onreset T_1275 := UInt<1>("h00") - node T_1277 = eq(pcr_coreid, UInt<1>("h00")) - node T_1278 = eq(state, UInt<1>("h01")) - node T_1279 = and(T_1278, T_1277) - node T_1281 = neq(pcr_addr, UInt<11>("h0782")) - node T_1282 = and(T_1279, T_1281) - cpu[0].pcr_req.valid := T_1282 - node T_1283 = eq(cmd, UInt<2>("h03")) - cpu[0].pcr_req.bits.rw := T_1283 - cpu[0].pcr_req.bits.addr := pcr_addr - cpu[0].pcr_req.bits.data := pcr_wdata - cpu[0].reset := T_1273 - reg T_1285 : UInt<1>, clock, reset - onreset T_1285 := UInt<1>("h00") - reg T_1287 : UInt<1>, clock, reset - onreset T_1287 := UInt<1>("h00") - when rtc_tick : - T_1285 := UInt<1>("h00") - skip - when cpu[0].pcr_rep.valid : - T_1287 := UInt<1>("h00") - skip - when T_1287 : - cpu[0].pcr_req.valid := UInt<1>("h00") - skip - node T_1291 = neq(state, UInt<1>("h01")) - node T_1292 = neq(state, UInt<2>("h02")) - node T_1293 = and(T_1291, T_1292) - node T_1295 = eq(T_1285, UInt<1>("h00")) - node T_1296 = and(T_1293, T_1295) - node T_1298 = eq(T_1287, UInt<1>("h00")) - node T_1299 = and(T_1296, T_1298) - when T_1299 : - cpu[0].pcr_req.valid := UInt<1>("h01") - cpu[0].pcr_req.bits.rw := UInt<1>("h01") - cpu[0].pcr_req.bits.addr := UInt<11>("h0782") - cpu[0].pcr_req.bits.data := rtc - T_1285 := cpu[0].pcr_req.ready - T_1287 := cpu[0].pcr_req.ready - skip - when cpu[0].ipi_rep.ready : - T_1275 := UInt<1>("h00") - skip - cpu[0].ipi_rep.valid := T_1275 - cpu[0].ipi_req.ready := UInt<1>("h01") - node T_1306 = eq(cpu[0].ipi_req.bits, UInt<1>("h00")) - node T_1307 = and(cpu[0].ipi_req.valid, T_1306) - when T_1307 : - T_1275 := UInt<1>("h01") - skip - node T_1309 = eq(state, UInt<1>("h01")) - node T_1310 = and(cpu[0].pcr_req.ready, cpu[0].pcr_req.valid) - node T_1311 = and(T_1309, T_1310) - when T_1311 : - state := UInt<2>("h02") - skip - node T_1312 = eq(state, UInt<1>("h01")) - node T_1313 = and(T_1312, T_1277) - node T_1315 = eq(pcr_addr, UInt<11>("h0782")) - node T_1316 = and(T_1313, T_1315) - when T_1316 : - node T_1317 = eq(cmd, UInt<2>("h03")) - when T_1317 : - node T_1318 = bit(pcr_wdata, 0) - T_1273 := T_1318 - skip - pcrReadData := T_1273 - state := UInt<3>("h07") - skip - cpu[0].pcr_rep.ready := UInt<1>("h01") - node T_1320 = eq(state, UInt<2>("h02")) - node T_1321 = and(T_1320, cpu[0].pcr_rep.valid) - when T_1321 : - pcrReadData := cpu[0].pcr_rep.bits - state := UInt<3>("h07") - skip - node scr_addr = bits(addr, 5, 0) - wire scr_rdata : UInt<64>[64] - scr_rdata[0] := UInt<1>("h00") - scr_rdata[1] := UInt<1>("h00") - scr_rdata[2] := UInt<1>("h00") - scr_rdata[3] := UInt<1>("h00") - scr_rdata[4] := UInt<1>("h00") - scr_rdata[5] := UInt<1>("h00") - scr_rdata[6] := UInt<1>("h00") - scr_rdata[7] := UInt<1>("h00") - scr_rdata[8] := UInt<1>("h00") - scr_rdata[9] := UInt<1>("h00") - scr_rdata[10] := UInt<1>("h00") - scr_rdata[11] := UInt<1>("h00") - scr_rdata[12] := UInt<1>("h00") - scr_rdata[13] := UInt<1>("h00") - scr_rdata[14] := UInt<1>("h00") - scr_rdata[15] := UInt<1>("h00") - scr_rdata[16] := UInt<1>("h00") - scr_rdata[17] := UInt<1>("h00") - scr_rdata[18] := UInt<1>("h00") - scr_rdata[19] := UInt<1>("h00") - scr_rdata[20] := UInt<1>("h00") - scr_rdata[21] := UInt<1>("h00") - scr_rdata[22] := UInt<1>("h00") - scr_rdata[23] := UInt<1>("h00") - scr_rdata[24] := UInt<1>("h00") - scr_rdata[25] := UInt<1>("h00") - scr_rdata[26] := UInt<1>("h00") - scr_rdata[27] := UInt<1>("h00") - scr_rdata[28] := UInt<1>("h00") - scr_rdata[29] := UInt<1>("h00") - scr_rdata[30] := UInt<1>("h00") - scr_rdata[31] := UInt<1>("h00") - scr_rdata[32] := UInt<1>("h00") - scr_rdata[33] := UInt<1>("h00") - scr_rdata[34] := UInt<1>("h00") - scr_rdata[35] := UInt<1>("h00") - scr_rdata[36] := UInt<1>("h00") - scr_rdata[37] := UInt<1>("h00") - scr_rdata[38] := UInt<1>("h00") - scr_rdata[39] := UInt<1>("h00") - scr_rdata[40] := UInt<1>("h00") - scr_rdata[41] := UInt<1>("h00") - scr_rdata[42] := UInt<1>("h00") - scr_rdata[43] := UInt<1>("h00") - scr_rdata[44] := UInt<1>("h00") - scr_rdata[45] := UInt<1>("h00") - scr_rdata[46] := UInt<1>("h00") - scr_rdata[47] := UInt<1>("h00") - scr_rdata[48] := UInt<1>("h00") - scr_rdata[49] := UInt<1>("h00") - scr_rdata[50] := UInt<1>("h00") - scr_rdata[51] := UInt<1>("h00") - scr_rdata[52] := UInt<1>("h00") - scr_rdata[53] := UInt<1>("h00") - scr_rdata[54] := UInt<1>("h00") - scr_rdata[55] := UInt<1>("h00") - scr_rdata[56] := UInt<1>("h00") - scr_rdata[57] := UInt<1>("h00") - scr_rdata[58] := UInt<1>("h00") - scr_rdata[59] := UInt<1>("h00") - scr_rdata[60] := UInt<1>("h00") - scr_rdata[61] := UInt<1>("h00") - scr_rdata[62] := UInt<1>("h00") - scr_rdata[63] := UInt<1>("h00") - scr_rdata[0] := scr.rdata[0] - scr_rdata[1] := scr.rdata[1] - scr_rdata[2] := scr.rdata[2] - scr_rdata[3] := scr.rdata[3] - scr_rdata[4] := scr.rdata[4] - scr_rdata[5] := scr.rdata[5] - scr_rdata[6] := scr.rdata[6] - scr_rdata[7] := scr.rdata[7] - scr_rdata[8] := scr.rdata[8] - scr_rdata[9] := scr.rdata[9] - scr_rdata[10] := scr.rdata[10] - scr_rdata[11] := scr.rdata[11] - scr_rdata[12] := scr.rdata[12] - scr_rdata[13] := scr.rdata[13] - scr_rdata[14] := scr.rdata[14] - scr_rdata[15] := scr.rdata[15] - scr_rdata[16] := scr.rdata[16] - scr_rdata[17] := scr.rdata[17] - scr_rdata[18] := scr.rdata[18] - scr_rdata[19] := scr.rdata[19] - scr_rdata[20] := scr.rdata[20] - scr_rdata[21] := scr.rdata[21] - scr_rdata[22] := scr.rdata[22] - scr_rdata[23] := scr.rdata[23] - scr_rdata[24] := scr.rdata[24] - scr_rdata[25] := scr.rdata[25] - scr_rdata[26] := scr.rdata[26] - scr_rdata[27] := scr.rdata[27] - scr_rdata[28] := scr.rdata[28] - scr_rdata[29] := scr.rdata[29] - scr_rdata[30] := scr.rdata[30] - scr_rdata[31] := scr.rdata[31] - scr_rdata[32] := scr.rdata[32] - scr_rdata[33] := scr.rdata[33] - scr_rdata[34] := scr.rdata[34] - scr_rdata[35] := scr.rdata[35] - scr_rdata[36] := scr.rdata[36] - scr_rdata[37] := scr.rdata[37] - scr_rdata[38] := scr.rdata[38] - scr_rdata[39] := scr.rdata[39] - scr_rdata[40] := scr.rdata[40] - scr_rdata[41] := scr.rdata[41] - scr_rdata[42] := scr.rdata[42] - scr_rdata[43] := scr.rdata[43] - scr_rdata[44] := scr.rdata[44] - scr_rdata[45] := scr.rdata[45] - scr_rdata[46] := scr.rdata[46] - scr_rdata[47] := scr.rdata[47] - scr_rdata[48] := scr.rdata[48] - scr_rdata[49] := scr.rdata[49] - scr_rdata[50] := scr.rdata[50] - scr_rdata[51] := scr.rdata[51] - scr_rdata[52] := scr.rdata[52] - scr_rdata[53] := scr.rdata[53] - scr_rdata[54] := scr.rdata[54] - scr_rdata[55] := scr.rdata[55] - scr_rdata[56] := scr.rdata[56] - scr_rdata[57] := scr.rdata[57] - scr_rdata[58] := scr.rdata[58] - scr_rdata[59] := scr.rdata[59] - scr_rdata[60] := scr.rdata[60] - scr_rdata[61] := scr.rdata[61] - scr_rdata[62] := scr.rdata[62] - scr_rdata[63] := scr.rdata[63] - scr_rdata[0] := UInt<1>("h01") - scr_rdata[1] := UInt<13>("h01000") - scr.wen := UInt<1>("h00") - scr.wdata := pcr_wdata - scr.waddr := scr_addr - node T_1526 = eq(state, UInt<1>("h01")) - node T_1527 = not(pcr_coreid) - node T_1529 = eq(T_1527, UInt<1>("h00")) - node T_1530 = and(T_1526, T_1529) - when T_1530 : - node T_1531 = eq(cmd, UInt<2>("h03")) - scr.wen := T_1531 - infer accessor T_1532 = scr_rdata[scr_addr] - pcrReadData := T_1532 - state := UInt<3>("h07") - skip - node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) - node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) - node T_1536 = cat(addr, seqno) - node T_1537 = cat(tx_size, tx_cmd_ext) - node tx_header = cat(T_1536, T_1537) - node T_1540 = eq(tx_word_count, UInt<1>("h00")) - node T_1541 = eq(cmd, UInt<2>("h02")) - node T_1542 = eq(cmd, UInt<2>("h03")) - node T_1543 = or(T_1541, T_1542) - infer accessor T_1544 = packet_ram[packet_ram_raddr] - node T_1545 = mux(T_1543, pcrReadData, T_1544) - node tx_data = mux(T_1540, tx_header, T_1545) - node T_1547 = eq(state, UInt<1>("h00")) - host.in.ready := T_1547 - node T_1548 = eq(state, UInt<3>("h07")) - host.out.valid := T_1548 - node T_1549 = bits(tx_count, 1, 0) - node T_1551 = cat(T_1549, UInt<4>("h00")) - node T_1552 = dshr(tx_data, T_1551) - host.out.bits := T_1552 - - module ClientTileLinkIOWrapper : - output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - out.release.bits.voluntary := UInt<1>("h00") - out.release.bits.r_type := UInt<1>("h00") - out.release.bits.data := UInt<1>("h00") - out.release.bits.addr_beat := UInt<1>("h00") - out.release.bits.client_xact_id := UInt<1>("h00") - out.release.bits.addr_block := UInt<1>("h00") - out.release.valid := UInt<1>("h00") - out.probe.ready := UInt<1>("h00") - out.grant.ready := UInt<1>("h00") - out.acquire.bits.union := UInt<1>("h00") - out.acquire.bits.a_type := UInt<1>("h00") - out.acquire.bits.is_builtin_type := UInt<1>("h00") - out.acquire.bits.data := UInt<1>("h00") - out.acquire.bits.addr_beat := UInt<1>("h00") - out.acquire.bits.client_xact_id := UInt<1>("h00") - out.acquire.bits.addr_block := UInt<1>("h00") - out.acquire.valid := UInt<1>("h00") - in.grant.bits.g_type := UInt<1>("h00") - in.grant.bits.is_builtin_type := UInt<1>("h00") - in.grant.bits.manager_xact_id := UInt<1>("h00") - in.grant.bits.client_xact_id := UInt<1>("h00") - in.grant.bits.data := UInt<1>("h00") - in.grant.bits.addr_beat := UInt<1>("h00") - in.grant.valid := UInt<1>("h00") - in.acquire.ready := UInt<1>("h00") - out.acquire <> in.acquire - in.grant <> out.grant - out.probe.ready := UInt<1>("h01") - out.release.valid := UInt<1>("h00") - - module FinishQueue : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.dst := UInt<1>("h00") - deq.bits.fin.manager_xact_id := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem T_463 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2], clock - reg T_465 : UInt<1>, clock, reset - onreset T_465 := UInt<1>("h00") - reg T_467 : UInt<1>, clock, reset - onreset T_467 := UInt<1>("h00") - reg T_469 : UInt<1>, clock, reset - onreset T_469 := UInt<1>("h00") - node T_470 = eq(T_465, T_467) - node T_472 = eq(T_469, UInt<1>("h00")) - node T_473 = and(T_470, T_472) - node T_474 = and(T_470, T_469) - node T_476 = and(UInt<1>("h00"), T_473) - node T_477 = and(T_476, deq.ready) - node T_478 = and(enq.ready, enq.valid) - node T_480 = eq(T_477, UInt<1>("h00")) - node T_481 = and(T_478, T_480) - node T_482 = and(deq.ready, deq.valid) - node T_484 = eq(T_477, UInt<1>("h00")) - node T_485 = and(T_482, T_484) - when T_481 : - infer accessor T_486 = T_463[T_465] - T_486 <> enq.bits - node T_537 = eq(T_465, UInt<1>("h01")) - node T_539 = and(UInt<1>("h00"), T_537) - node T_542 = addw(T_465, UInt<1>("h01")) - node T_543 = mux(T_539, UInt<1>("h00"), T_542) - T_465 := T_543 - skip - when T_485 : - node T_545 = eq(T_467, UInt<1>("h01")) - node T_547 = and(UInt<1>("h00"), T_545) - node T_550 = addw(T_467, UInt<1>("h01")) - node T_551 = mux(T_547, UInt<1>("h00"), T_550) - T_467 := T_551 - skip - node T_552 = neq(T_481, T_485) - when T_552 : - T_469 := T_481 - skip - node T_554 = eq(T_473, UInt<1>("h00")) - node T_556 = and(UInt<1>("h00"), enq.valid) - node T_557 = or(T_554, T_556) - deq.valid := T_557 - node T_559 = eq(T_474, UInt<1>("h00")) - node T_561 = and(UInt<1>("h00"), deq.ready) - node T_562 = or(T_559, T_561) - enq.ready := T_562 - infer accessor T_563 = T_463[T_467] - wire T_663 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>} - T_663 <> T_563 - when T_476 : - T_663 <> enq.bits - skip - deq.bits <> T_663 - node T_713 = subw(T_465, T_467) - node T_714 = and(T_469, T_470) - node T_715 = cat(T_714, T_713) - count := T_715 - - module FinishUnit : - output ready : UInt<1> - output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - ready := UInt<1>("h00") - finish.bits.payload.manager_xact_id := UInt<1>("h00") - finish.bits.header.dst := UInt<1>("h00") - finish.bits.header.src := UInt<1>("h00") - finish.valid := UInt<1>("h00") - refill.bits.g_type := UInt<1>("h00") - refill.bits.is_builtin_type := UInt<1>("h00") - refill.bits.manager_xact_id := UInt<1>("h00") - refill.bits.client_xact_id := UInt<1>("h00") - refill.bits.data := UInt<1>("h00") - refill.bits.addr_beat := UInt<1>("h00") - refill.valid := UInt<1>("h00") - grant.ready := UInt<1>("h00") - node T_441 = and(grant.ready, grant.valid) - wire T_446 : UInt<3>[1] - T_446[0] := UInt<3>("h05") - node T_449 = eq(T_446[0], grant.bits.payload.g_type) - node T_451 = or(UInt<1>("h00"), T_449) - wire T_453 : UInt<1>[2] - T_453[0] := UInt<1>("h00") - T_453[1] := UInt<1>("h01") - node T_457 = eq(T_453[0], grant.bits.payload.g_type) - node T_458 = eq(T_453[1], grant.bits.payload.g_type) - node T_460 = or(UInt<1>("h00"), T_457) - node T_461 = or(T_460, T_458) - node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) - node T_463 = and(UInt<1>("h01"), T_462) - node T_464 = and(T_441, T_463) - reg T_466 : UInt<2>, clock, reset - onreset T_466 := UInt<2>("h00") - when T_464 : - node T_468 = eq(T_466, UInt<2>("h03")) - node T_470 = and(UInt<1>("h00"), T_468) - node T_473 = addw(T_466, UInt<1>("h01")) - node T_474 = mux(T_470, UInt<1>("h00"), T_473) - T_466 := T_474 - skip - node T_475 = and(T_464, T_468) - node T_476 = mux(T_463, T_466, UInt<1>("h00")) - node T_477 = mux(T_463, T_475, T_441) - inst T_634 of FinishQueue - T_634.deq.ready := UInt<1>("h00") - T_634.enq.bits.dst := UInt<1>("h00") - T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") - T_634.enq.valid := UInt<1>("h00") - T_634.reset := UInt<1>("h00") - T_634.clock := clock - T_634.reset := reset - node T_533 = and(grant.ready, grant.valid) - node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_539 = and(grant.bits.payload.is_builtin_type, T_538) - node T_541 = eq(T_539, UInt<1>("h00")) - node T_542 = and(T_536, T_541) - node T_543 = and(T_533, T_542) - wire T_547 : UInt<3>[1] - T_547[0] := UInt<3>("h05") - node T_550 = eq(T_547[0], grant.bits.payload.g_type) - node T_552 = or(UInt<1>("h00"), T_550) - wire T_554 : UInt<1>[2] - T_554[0] := UInt<1>("h00") - T_554[1] := UInt<1>("h01") - node T_558 = eq(T_554[0], grant.bits.payload.g_type) - node T_559 = eq(T_554[1], grant.bits.payload.g_type) - node T_561 = or(UInt<1>("h00"), T_558) - node T_562 = or(T_561, T_559) - node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) - node T_564 = and(UInt<1>("h01"), T_563) - node T_566 = eq(T_564, UInt<1>("h00")) - node T_567 = or(T_566, T_477) - node T_568 = and(T_543, T_567) - T_634.enq.valid := T_568 - wire T_594 : {manager_xact_id : UInt<4>} - T_594.manager_xact_id := UInt<1>("h00") - T_594.manager_xact_id := grant.bits.payload.manager_xact_id - T_634.enq.bits.fin <> T_594 - T_634.enq.bits.dst := grant.bits.header.src - finish.bits.header.src := UInt<1>("h00") - finish.bits.header.dst := T_634.deq.bits.dst - finish.bits.payload <> T_634.deq.bits.fin - finish.valid := T_634.deq.valid - T_634.deq.ready := finish.ready - refill.valid := grant.valid - refill.bits <> grant.bits.payload - node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_626 = and(grant.bits.payload.is_builtin_type, T_625) - node T_628 = eq(T_626, UInt<1>("h00")) - node T_629 = and(T_623, T_628) - node T_631 = eq(T_629, UInt<1>("h00")) - node T_632 = or(T_634.enq.ready, T_631) - node T_633 = and(T_632, refill.ready) - grant.ready := T_633 - ready := T_634.enq.ready - - module ClientTileLinkNetworkPort : - output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - network.release.bits.payload.voluntary := UInt<1>("h00") - network.release.bits.payload.r_type := UInt<1>("h00") - network.release.bits.payload.data := UInt<1>("h00") - network.release.bits.payload.addr_beat := UInt<1>("h00") - network.release.bits.payload.client_xact_id := UInt<1>("h00") - network.release.bits.payload.addr_block := UInt<1>("h00") - network.release.bits.header.dst := UInt<1>("h00") - network.release.bits.header.src := UInt<1>("h00") - network.release.valid := UInt<1>("h00") - network.probe.ready := UInt<1>("h00") - network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - network.finish.bits.header.dst := UInt<1>("h00") - network.finish.bits.header.src := UInt<1>("h00") - network.finish.valid := UInt<1>("h00") - network.grant.ready := UInt<1>("h00") - network.acquire.bits.payload.union := UInt<1>("h00") - network.acquire.bits.payload.a_type := UInt<1>("h00") - network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - network.acquire.bits.payload.data := UInt<1>("h00") - network.acquire.bits.payload.addr_beat := UInt<1>("h00") - network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - network.acquire.bits.payload.addr_block := UInt<1>("h00") - network.acquire.bits.header.dst := UInt<1>("h00") - network.acquire.bits.header.src := UInt<1>("h00") - network.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.p_type := UInt<1>("h00") - client.probe.bits.addr_block := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.grant.bits.g_type := UInt<1>("h00") - client.grant.bits.is_builtin_type := UInt<1>("h00") - client.grant.bits.manager_xact_id := UInt<1>("h00") - client.grant.bits.client_xact_id := UInt<1>("h00") - client.grant.bits.data := UInt<1>("h00") - client.grant.bits.addr_beat := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - inst finisher of FinishUnit - finisher.finish.ready := UInt<1>("h00") - finisher.refill.ready := UInt<1>("h00") - finisher.grant.bits.payload.g_type := UInt<1>("h00") - finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") - finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.data := UInt<1>("h00") - finisher.grant.bits.payload.addr_beat := UInt<1>("h00") - finisher.grant.bits.header.dst := UInt<1>("h00") - finisher.grant.bits.header.src := UInt<1>("h00") - finisher.grant.valid := UInt<1>("h00") - finisher.reset := UInt<1>("h00") - finisher.clock := clock - finisher.reset := reset - finisher.grant <> network.grant - network.finish <> finisher.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - acq_with_header.bits.payload.union := UInt<1>("h00") - acq_with_header.bits.payload.a_type := UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") - acq_with_header.bits.payload.data := UInt<1>("h00") - acq_with_header.bits.payload.addr_beat := UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") - acq_with_header.bits.payload.addr_block := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.valid := UInt<1>("h00") - acq_with_header.ready := UInt<1>("h00") - acq_with_header.bits.payload <> client.acquire.bits - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.valid := client.acquire.valid - client.acquire.ready := acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - rel_with_header.bits.payload.voluntary := UInt<1>("h00") - rel_with_header.bits.payload.r_type := UInt<1>("h00") - rel_with_header.bits.payload.data := UInt<1>("h00") - rel_with_header.bits.payload.addr_beat := UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") - rel_with_header.bits.payload.addr_block := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.valid := UInt<1>("h00") - rel_with_header.ready := UInt<1>("h00") - rel_with_header.bits.payload <> client.release.bits - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.valid := client.release.valid - client.release.ready := rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type := UInt<1>("h00") - prb_without_header.bits.addr_block := UInt<1>("h00") - prb_without_header.valid := UInt<1>("h00") - prb_without_header.ready := UInt<1>("h00") - prb_without_header.valid := network.probe.valid - prb_without_header.bits <> network.probe.bits.payload - network.probe.ready := prb_without_header.ready - network.acquire.bits <> acq_with_header.bits - node T_2345 = and(acq_with_header.valid, finisher.ready) - network.acquire.valid := T_2345 - node T_2346 = and(network.acquire.ready, finisher.ready) - acq_with_header.ready := T_2346 - network.release <> rel_with_header - client.probe <> prb_without_header - client.grant <> finisher.refill - - module Queue : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.union := UInt<1>("h00") - deq.bits.payload.a_type := UInt<1>("h00") - deq.bits.payload.is_builtin_type := UInt<1>("h00") - deq.bits.payload.data := UInt<1>("h00") - deq.bits.payload.addr_beat := UInt<1>("h00") - deq.bits.payload.client_xact_id := UInt<1>("h00") - deq.bits.payload.addr_block := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2], clock - reg T_331 : UInt<1>, clock, reset - onreset T_331 := UInt<1>("h00") - reg T_333 : UInt<1>, clock, reset - onreset T_333 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_331, T_333) - node T_338 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_338) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_344 = and(enq.ready, enq.valid) - node T_346 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_344, T_346) - node T_348 = and(deq.ready, deq.valid) - node T_350 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_348, T_350) - when do_enq : - infer accessor T_352 = ram[T_331] - T_352 <> enq.bits - node T_388 = eq(T_331, UInt<1>("h01")) - node T_390 = and(UInt<1>("h00"), T_388) - node T_393 = addw(T_331, UInt<1>("h01")) - node T_394 = mux(T_390, UInt<1>("h00"), T_393) - T_331 := T_394 - skip - when do_deq : - node T_396 = eq(T_333, UInt<1>("h01")) - node T_398 = and(UInt<1>("h00"), T_396) - node T_401 = addw(T_333, UInt<1>("h01")) - node T_402 = mux(T_398, UInt<1>("h00"), T_401) - T_333 := T_402 - skip - node T_403 = neq(do_enq, do_deq) - when T_403 : - maybe_full := do_enq - skip - node T_405 = eq(empty, UInt<1>("h00")) - node T_407 = and(UInt<1>("h00"), enq.valid) - node T_408 = or(T_405, T_407) - deq.valid := T_408 - node T_410 = eq(full, UInt<1>("h00")) - node T_412 = and(UInt<1>("h00"), deq.ready) - node T_413 = or(T_410, T_412) - enq.ready := T_413 - infer accessor T_414 = ram[T_333] - wire T_484 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - T_484 <> T_414 - when maybe_flow : - T_484 <> enq.bits - skip - deq.bits <> T_484 - node ptr_diff = subw(T_331, T_333) - node T_520 = and(maybe_full, ptr_match) - node T_521 = cat(T_520, ptr_diff) - count := T_521 - - module Queue_2 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.p_type := UInt<1>("h00") - deq.bits.payload.addr_block := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2], clock - reg T_286 : UInt<1>, clock, reset - onreset T_286 := UInt<1>("h00") - reg T_288 : UInt<1>, clock, reset - onreset T_288 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_286, T_288) - node T_293 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_293) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_299 = and(enq.ready, enq.valid) - node T_301 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_299, T_301) - node T_303 = and(deq.ready, deq.valid) - node T_305 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_303, T_305) - when do_enq : - infer accessor T_307 = ram[T_286] - T_307 <> enq.bits - node T_338 = eq(T_286, UInt<1>("h01")) - node T_340 = and(UInt<1>("h00"), T_338) - node T_343 = addw(T_286, UInt<1>("h01")) - node T_344 = mux(T_340, UInt<1>("h00"), T_343) - T_286 := T_344 - skip - when do_deq : - node T_346 = eq(T_288, UInt<1>("h01")) - node T_348 = and(UInt<1>("h00"), T_346) - node T_351 = addw(T_288, UInt<1>("h01")) - node T_352 = mux(T_348, UInt<1>("h00"), T_351) - T_288 := T_352 - skip - node T_353 = neq(do_enq, do_deq) - when T_353 : - maybe_full := do_enq - skip - node T_355 = eq(empty, UInt<1>("h00")) - node T_357 = and(UInt<1>("h00"), enq.valid) - node T_358 = or(T_355, T_357) - deq.valid := T_358 - node T_360 = eq(full, UInt<1>("h00")) - node T_362 = and(UInt<1>("h00"), deq.ready) - node T_363 = or(T_360, T_362) - enq.ready := T_363 - infer accessor T_364 = ram[T_288] - wire T_424 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}} - T_424 <> T_364 - when maybe_flow : - T_424 <> enq.bits - skip - deq.bits <> T_424 - node ptr_diff = subw(T_286, T_288) - node T_455 = and(maybe_full, ptr_match) - node T_456 = cat(T_455, ptr_diff) - count := T_456 - - module Queue_3 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.voluntary := UInt<1>("h00") - deq.bits.payload.r_type := UInt<1>("h00") - deq.bits.payload.data := UInt<1>("h00") - deq.bits.payload.addr_beat := UInt<1>("h00") - deq.bits.payload.client_xact_id := UInt<1>("h00") - deq.bits.payload.addr_block := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2], clock - reg T_322 : UInt<1>, clock, reset - onreset T_322 := UInt<1>("h00") - reg T_324 : UInt<1>, clock, reset - onreset T_324 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_322, T_324) - node T_329 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_329) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_335 = and(enq.ready, enq.valid) - node T_337 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_335, T_337) - node T_339 = and(deq.ready, deq.valid) - node T_341 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_339, T_341) - when do_enq : - infer accessor T_343 = ram[T_322] - T_343 <> enq.bits - node T_378 = eq(T_322, UInt<1>("h01")) - node T_380 = and(UInt<1>("h00"), T_378) - node T_383 = addw(T_322, UInt<1>("h01")) - node T_384 = mux(T_380, UInt<1>("h00"), T_383) - T_322 := T_384 - skip - when do_deq : - node T_386 = eq(T_324, UInt<1>("h01")) - node T_388 = and(UInt<1>("h00"), T_386) - node T_391 = addw(T_324, UInt<1>("h01")) - node T_392 = mux(T_388, UInt<1>("h00"), T_391) - T_324 := T_392 - skip - node T_393 = neq(do_enq, do_deq) - when T_393 : - maybe_full := do_enq - skip - node T_395 = eq(empty, UInt<1>("h00")) - node T_397 = and(UInt<1>("h00"), enq.valid) - node T_398 = or(T_395, T_397) - deq.valid := T_398 - node T_400 = eq(full, UInt<1>("h00")) - node T_402 = and(UInt<1>("h00"), deq.ready) - node T_403 = or(T_400, T_402) - enq.ready := T_403 - infer accessor T_404 = ram[T_324] - wire T_472 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - T_472 <> T_404 - when maybe_flow : - T_472 <> enq.bits - skip - deq.bits <> T_472 - node ptr_diff = subw(T_322, T_324) - node T_507 = and(maybe_full, ptr_match) - node T_508 = cat(T_507, ptr_diff) - count := T_508 - - module Queue_4 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.g_type := UInt<1>("h00") - deq.bits.payload.is_builtin_type := UInt<1>("h00") - deq.bits.payload.manager_xact_id := UInt<1>("h00") - deq.bits.payload.client_xact_id := UInt<1>("h00") - deq.bits.payload.data := UInt<1>("h00") - deq.bits.payload.addr_beat := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2], clock - reg T_322 : UInt<1>, clock, reset - onreset T_322 := UInt<1>("h00") - reg T_324 : UInt<1>, clock, reset - onreset T_324 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_322, T_324) - node T_329 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_329) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_335 = and(enq.ready, enq.valid) - node T_337 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_335, T_337) - node T_339 = and(deq.ready, deq.valid) - node T_341 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_339, T_341) - when do_enq : - infer accessor T_343 = ram[T_322] - T_343 <> enq.bits - node T_378 = eq(T_322, UInt<1>("h01")) - node T_380 = and(UInt<1>("h00"), T_378) - node T_383 = addw(T_322, UInt<1>("h01")) - node T_384 = mux(T_380, UInt<1>("h00"), T_383) - T_322 := T_384 - skip - when do_deq : - node T_386 = eq(T_324, UInt<1>("h01")) - node T_388 = and(UInt<1>("h00"), T_386) - node T_391 = addw(T_324, UInt<1>("h01")) - node T_392 = mux(T_388, UInt<1>("h00"), T_391) - T_324 := T_392 - skip - node T_393 = neq(do_enq, do_deq) - when T_393 : - maybe_full := do_enq - skip - node T_395 = eq(empty, UInt<1>("h00")) - node T_397 = and(UInt<1>("h00"), enq.valid) - node T_398 = or(T_395, T_397) - deq.valid := T_398 - node T_400 = eq(full, UInt<1>("h00")) - node T_402 = and(UInt<1>("h00"), deq.ready) - node T_403 = or(T_400, T_402) - enq.ready := T_403 - infer accessor T_404 = ram[T_324] - wire T_472 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - T_472 <> T_404 - when maybe_flow : - T_472 <> enq.bits - skip - deq.bits <> T_472 - node ptr_diff = subw(T_322, T_324) - node T_507 = and(maybe_full, ptr_match) - node T_508 = cat(T_507, ptr_diff) - count := T_508 - - module Queue_5 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.manager_xact_id := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2], clock - reg T_277 : UInt<1>, clock, reset - onreset T_277 := UInt<1>("h00") - reg T_279 : UInt<1>, clock, reset - onreset T_279 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_277, T_279) - node T_284 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_284) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_290 = and(enq.ready, enq.valid) - node T_292 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_290, T_292) - node T_294 = and(deq.ready, deq.valid) - node T_296 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_294, T_296) - when do_enq : - infer accessor T_298 = ram[T_277] - T_298 <> enq.bits - node T_328 = eq(T_277, UInt<1>("h01")) - node T_330 = and(UInt<1>("h00"), T_328) - node T_333 = addw(T_277, UInt<1>("h01")) - node T_334 = mux(T_330, UInt<1>("h00"), T_333) - T_277 := T_334 - skip - when do_deq : - node T_336 = eq(T_279, UInt<1>("h01")) - node T_338 = and(UInt<1>("h00"), T_336) - node T_341 = addw(T_279, UInt<1>("h01")) - node T_342 = mux(T_338, UInt<1>("h00"), T_341) - T_279 := T_342 - skip - node T_343 = neq(do_enq, do_deq) - when T_343 : - maybe_full := do_enq - skip - node T_345 = eq(empty, UInt<1>("h00")) - node T_347 = and(UInt<1>("h00"), enq.valid) - node T_348 = or(T_345, T_347) - deq.valid := T_348 - node T_350 = eq(full, UInt<1>("h00")) - node T_352 = and(UInt<1>("h00"), deq.ready) - node T_353 = or(T_350, T_352) - enq.ready := T_353 - infer accessor T_354 = ram[T_279] - wire T_412 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}} - T_412 <> T_354 - when maybe_flow : - T_412 <> enq.bits - skip - deq.bits <> T_412 - node ptr_diff = subw(T_277, T_279) - node T_442 = and(maybe_full, ptr_match) - node T_443 = cat(T_442, ptr_diff) - count := T_443 - - module TileLinkEnqueuer : - output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input clock : Clock - input reset : UInt<1> - - manager.release.bits.payload.voluntary := UInt<1>("h00") - manager.release.bits.payload.r_type := UInt<1>("h00") - manager.release.bits.payload.data := UInt<1>("h00") - manager.release.bits.payload.addr_beat := UInt<1>("h00") - manager.release.bits.payload.client_xact_id := UInt<1>("h00") - manager.release.bits.payload.addr_block := UInt<1>("h00") - manager.release.bits.header.dst := UInt<1>("h00") - manager.release.bits.header.src := UInt<1>("h00") - manager.release.valid := UInt<1>("h00") - manager.probe.ready := UInt<1>("h00") - manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") - manager.finish.bits.header.dst := UInt<1>("h00") - manager.finish.bits.header.src := UInt<1>("h00") - manager.finish.valid := UInt<1>("h00") - manager.grant.ready := UInt<1>("h00") - manager.acquire.bits.payload.union := UInt<1>("h00") - manager.acquire.bits.payload.a_type := UInt<1>("h00") - manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - manager.acquire.bits.payload.data := UInt<1>("h00") - manager.acquire.bits.payload.addr_beat := UInt<1>("h00") - manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") - manager.acquire.bits.payload.addr_block := UInt<1>("h00") - manager.acquire.bits.header.dst := UInt<1>("h00") - manager.acquire.bits.header.src := UInt<1>("h00") - manager.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.payload.p_type := UInt<1>("h00") - client.probe.bits.payload.addr_block := UInt<1>("h00") - client.probe.bits.header.dst := UInt<1>("h00") - client.probe.bits.header.src := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.finish.ready := UInt<1>("h00") - client.grant.bits.payload.g_type := UInt<1>("h00") - client.grant.bits.payload.is_builtin_type := UInt<1>("h00") - client.grant.bits.payload.manager_xact_id := UInt<1>("h00") - client.grant.bits.payload.client_xact_id := UInt<1>("h00") - client.grant.bits.payload.data := UInt<1>("h00") - client.grant.bits.payload.addr_beat := UInt<1>("h00") - client.grant.bits.header.dst := UInt<1>("h00") - client.grant.bits.header.src := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - inst T_2615 of Queue - T_2615.deq.ready := UInt<1>("h00") - T_2615.enq.bits.payload.union := UInt<1>("h00") - T_2615.enq.bits.payload.a_type := UInt<1>("h00") - T_2615.enq.bits.payload.is_builtin_type := UInt<1>("h00") - T_2615.enq.bits.payload.data := UInt<1>("h00") - T_2615.enq.bits.payload.addr_beat := UInt<1>("h00") - T_2615.enq.bits.payload.client_xact_id := UInt<1>("h00") - T_2615.enq.bits.payload.addr_block := UInt<1>("h00") - T_2615.enq.bits.header.dst := UInt<1>("h00") - T_2615.enq.bits.header.src := UInt<1>("h00") - T_2615.enq.valid := UInt<1>("h00") - T_2615.reset := UInt<1>("h00") - T_2615.clock := clock - T_2615.reset := reset - T_2615.enq.valid := client.acquire.valid - T_2615.enq.bits <> client.acquire.bits - client.acquire.ready := T_2615.enq.ready - manager.acquire <> T_2615.deq - inst T_2616 of Queue_2 - T_2616.deq.ready := UInt<1>("h00") - T_2616.enq.bits.payload.p_type := UInt<1>("h00") - T_2616.enq.bits.payload.addr_block := UInt<1>("h00") - T_2616.enq.bits.header.dst := UInt<1>("h00") - T_2616.enq.bits.header.src := UInt<1>("h00") - T_2616.enq.valid := UInt<1>("h00") - T_2616.reset := UInt<1>("h00") - T_2616.clock := clock - T_2616.reset := reset - T_2616.enq.valid := manager.probe.valid - T_2616.enq.bits <> manager.probe.bits - manager.probe.ready := T_2616.enq.ready - client.probe <> T_2616.deq - inst T_2617 of Queue_3 - T_2617.deq.ready := UInt<1>("h00") - T_2617.enq.bits.payload.voluntary := UInt<1>("h00") - T_2617.enq.bits.payload.r_type := UInt<1>("h00") - T_2617.enq.bits.payload.data := UInt<1>("h00") - T_2617.enq.bits.payload.addr_beat := UInt<1>("h00") - T_2617.enq.bits.payload.client_xact_id := UInt<1>("h00") - T_2617.enq.bits.payload.addr_block := UInt<1>("h00") - T_2617.enq.bits.header.dst := UInt<1>("h00") - T_2617.enq.bits.header.src := UInt<1>("h00") - T_2617.enq.valid := UInt<1>("h00") - T_2617.reset := UInt<1>("h00") - T_2617.clock := clock - T_2617.reset := reset - T_2617.enq.valid := client.release.valid - T_2617.enq.bits <> client.release.bits - client.release.ready := T_2617.enq.ready - manager.release <> T_2617.deq - inst T_2618 of Queue_4 - T_2618.deq.ready := UInt<1>("h00") - T_2618.enq.bits.payload.g_type := UInt<1>("h00") - T_2618.enq.bits.payload.is_builtin_type := UInt<1>("h00") - T_2618.enq.bits.payload.manager_xact_id := UInt<1>("h00") - T_2618.enq.bits.payload.client_xact_id := UInt<1>("h00") - T_2618.enq.bits.payload.data := UInt<1>("h00") - T_2618.enq.bits.payload.addr_beat := UInt<1>("h00") - T_2618.enq.bits.header.dst := UInt<1>("h00") - T_2618.enq.bits.header.src := UInt<1>("h00") - T_2618.enq.valid := UInt<1>("h00") - T_2618.reset := UInt<1>("h00") - T_2618.clock := clock - T_2618.reset := reset - T_2618.enq.valid := manager.grant.valid - T_2618.enq.bits <> manager.grant.bits - manager.grant.ready := T_2618.enq.ready - client.grant <> T_2618.deq - inst T_2619 of Queue_5 - T_2619.deq.ready := UInt<1>("h00") - T_2619.enq.bits.payload.manager_xact_id := UInt<1>("h00") - T_2619.enq.bits.header.dst := UInt<1>("h00") - T_2619.enq.bits.header.src := UInt<1>("h00") - T_2619.enq.valid := UInt<1>("h00") - T_2619.reset := UInt<1>("h00") - T_2619.clock := clock - T_2619.reset := reset - T_2619.enq.valid := client.finish.valid - T_2619.enq.bits <> client.finish.bits - client.finish.ready := T_2619.enq.ready - manager.finish <> T_2619.deq - - module FinishUnit_7 : - output ready : UInt<1> - output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - ready := UInt<1>("h00") - finish.bits.payload.manager_xact_id := UInt<1>("h00") - finish.bits.header.dst := UInt<1>("h00") - finish.bits.header.src := UInt<1>("h00") - finish.valid := UInt<1>("h00") - refill.bits.g_type := UInt<1>("h00") - refill.bits.is_builtin_type := UInt<1>("h00") - refill.bits.manager_xact_id := UInt<1>("h00") - refill.bits.client_xact_id := UInt<1>("h00") - refill.bits.data := UInt<1>("h00") - refill.bits.addr_beat := UInt<1>("h00") - refill.valid := UInt<1>("h00") - grant.ready := UInt<1>("h00") - node T_441 = and(grant.ready, grant.valid) - wire T_446 : UInt<3>[1] - T_446[0] := UInt<3>("h05") - node T_449 = eq(T_446[0], grant.bits.payload.g_type) - node T_451 = or(UInt<1>("h00"), T_449) - wire T_453 : UInt<1>[2] - T_453[0] := UInt<1>("h00") - T_453[1] := UInt<1>("h01") - node T_457 = eq(T_453[0], grant.bits.payload.g_type) - node T_458 = eq(T_453[1], grant.bits.payload.g_type) - node T_460 = or(UInt<1>("h00"), T_457) - node T_461 = or(T_460, T_458) - node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) - node T_463 = and(UInt<1>("h01"), T_462) - node T_464 = and(T_441, T_463) - reg T_466 : UInt<2>, clock, reset - onreset T_466 := UInt<2>("h00") - when T_464 : - node T_468 = eq(T_466, UInt<2>("h03")) - node T_470 = and(UInt<1>("h00"), T_468) - node T_473 = addw(T_466, UInt<1>("h01")) - node T_474 = mux(T_470, UInt<1>("h00"), T_473) - T_466 := T_474 - skip - node T_475 = and(T_464, T_468) - node T_476 = mux(T_463, T_466, UInt<1>("h00")) - node T_477 = mux(T_463, T_475, T_441) - inst T_634 of FinishQueue - T_634.deq.ready := UInt<1>("h00") - T_634.enq.bits.dst := UInt<1>("h00") - T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") - T_634.enq.valid := UInt<1>("h00") - T_634.reset := UInt<1>("h00") - T_634.clock := clock - T_634.reset := reset - node T_533 = and(grant.ready, grant.valid) - node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_539 = and(grant.bits.payload.is_builtin_type, T_538) - node T_541 = eq(T_539, UInt<1>("h00")) - node T_542 = and(T_536, T_541) - node T_543 = and(T_533, T_542) - wire T_547 : UInt<3>[1] - T_547[0] := UInt<3>("h05") - node T_550 = eq(T_547[0], grant.bits.payload.g_type) - node T_552 = or(UInt<1>("h00"), T_550) - wire T_554 : UInt<1>[2] - T_554[0] := UInt<1>("h00") - T_554[1] := UInt<1>("h01") - node T_558 = eq(T_554[0], grant.bits.payload.g_type) - node T_559 = eq(T_554[1], grant.bits.payload.g_type) - node T_561 = or(UInt<1>("h00"), T_558) - node T_562 = or(T_561, T_559) - node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) - node T_564 = and(UInt<1>("h01"), T_563) - node T_566 = eq(T_564, UInt<1>("h00")) - node T_567 = or(T_566, T_477) - node T_568 = and(T_543, T_567) - T_634.enq.valid := T_568 - wire T_594 : {manager_xact_id : UInt<4>} - T_594.manager_xact_id := UInt<1>("h00") - T_594.manager_xact_id := grant.bits.payload.manager_xact_id - T_634.enq.bits.fin <> T_594 - T_634.enq.bits.dst := grant.bits.header.src - finish.bits.header.src := UInt<1>("h01") - finish.bits.header.dst := T_634.deq.bits.dst - finish.bits.payload <> T_634.deq.bits.fin - finish.valid := T_634.deq.valid - T_634.deq.ready := finish.ready - refill.valid := grant.valid - refill.bits <> grant.bits.payload - node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_626 = and(grant.bits.payload.is_builtin_type, T_625) - node T_628 = eq(T_626, UInt<1>("h00")) - node T_629 = and(T_623, T_628) - node T_631 = eq(T_629, UInt<1>("h00")) - node T_632 = or(T_634.enq.ready, T_631) - node T_633 = and(T_632, refill.ready) - grant.ready := T_633 - ready := T_634.enq.ready - - module ClientTileLinkNetworkPort_6 : - output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - network.release.bits.payload.voluntary := UInt<1>("h00") - network.release.bits.payload.r_type := UInt<1>("h00") - network.release.bits.payload.data := UInt<1>("h00") - network.release.bits.payload.addr_beat := UInt<1>("h00") - network.release.bits.payload.client_xact_id := UInt<1>("h00") - network.release.bits.payload.addr_block := UInt<1>("h00") - network.release.bits.header.dst := UInt<1>("h00") - network.release.bits.header.src := UInt<1>("h00") - network.release.valid := UInt<1>("h00") - network.probe.ready := UInt<1>("h00") - network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - network.finish.bits.header.dst := UInt<1>("h00") - network.finish.bits.header.src := UInt<1>("h00") - network.finish.valid := UInt<1>("h00") - network.grant.ready := UInt<1>("h00") - network.acquire.bits.payload.union := UInt<1>("h00") - network.acquire.bits.payload.a_type := UInt<1>("h00") - network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - network.acquire.bits.payload.data := UInt<1>("h00") - network.acquire.bits.payload.addr_beat := UInt<1>("h00") - network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - network.acquire.bits.payload.addr_block := UInt<1>("h00") - network.acquire.bits.header.dst := UInt<1>("h00") - network.acquire.bits.header.src := UInt<1>("h00") - network.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.p_type := UInt<1>("h00") - client.probe.bits.addr_block := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.grant.bits.g_type := UInt<1>("h00") - client.grant.bits.is_builtin_type := UInt<1>("h00") - client.grant.bits.manager_xact_id := UInt<1>("h00") - client.grant.bits.client_xact_id := UInt<1>("h00") - client.grant.bits.data := UInt<1>("h00") - client.grant.bits.addr_beat := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - inst finisher of FinishUnit_7 - finisher.finish.ready := UInt<1>("h00") - finisher.refill.ready := UInt<1>("h00") - finisher.grant.bits.payload.g_type := UInt<1>("h00") - finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") - finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.data := UInt<1>("h00") - finisher.grant.bits.payload.addr_beat := UInt<1>("h00") - finisher.grant.bits.header.dst := UInt<1>("h00") - finisher.grant.bits.header.src := UInt<1>("h00") - finisher.grant.valid := UInt<1>("h00") - finisher.reset := UInt<1>("h00") - finisher.clock := clock - finisher.reset := reset - finisher.grant <> network.grant - network.finish <> finisher.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - acq_with_header.bits.payload.union := UInt<1>("h00") - acq_with_header.bits.payload.a_type := UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") - acq_with_header.bits.payload.data := UInt<1>("h00") - acq_with_header.bits.payload.addr_beat := UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") - acq_with_header.bits.payload.addr_block := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.valid := UInt<1>("h00") - acq_with_header.ready := UInt<1>("h00") - acq_with_header.bits.payload <> client.acquire.bits - acq_with_header.bits.header.src := UInt<1>("h01") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.valid := client.acquire.valid - client.acquire.ready := acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - rel_with_header.bits.payload.voluntary := UInt<1>("h00") - rel_with_header.bits.payload.r_type := UInt<1>("h00") - rel_with_header.bits.payload.data := UInt<1>("h00") - rel_with_header.bits.payload.addr_beat := UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") - rel_with_header.bits.payload.addr_block := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.valid := UInt<1>("h00") - rel_with_header.ready := UInt<1>("h00") - rel_with_header.bits.payload <> client.release.bits - rel_with_header.bits.header.src := UInt<1>("h01") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.valid := client.release.valid - client.release.ready := rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type := UInt<1>("h00") - prb_without_header.bits.addr_block := UInt<1>("h00") - prb_without_header.valid := UInt<1>("h00") - prb_without_header.ready := UInt<1>("h00") - prb_without_header.valid := network.probe.valid - prb_without_header.bits <> network.probe.bits.payload - network.probe.ready := prb_without_header.ready - network.acquire.bits <> acq_with_header.bits - node T_2345 = and(acq_with_header.valid, finisher.ready) - network.acquire.valid := T_2345 - node T_2346 = and(network.acquire.ready, finisher.ready) - acq_with_header.ready := T_2346 - network.release <> rel_with_header - client.probe <> prb_without_header - client.grant <> finisher.refill - - module FinishUnit_16 : - output ready : UInt<1> - output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - ready := UInt<1>("h00") - finish.bits.payload.manager_xact_id := UInt<1>("h00") - finish.bits.header.dst := UInt<1>("h00") - finish.bits.header.src := UInt<1>("h00") - finish.valid := UInt<1>("h00") - refill.bits.g_type := UInt<1>("h00") - refill.bits.is_builtin_type := UInt<1>("h00") - refill.bits.manager_xact_id := UInt<1>("h00") - refill.bits.client_xact_id := UInt<1>("h00") - refill.bits.data := UInt<1>("h00") - refill.bits.addr_beat := UInt<1>("h00") - refill.valid := UInt<1>("h00") - grant.ready := UInt<1>("h00") - node T_441 = and(grant.ready, grant.valid) - wire T_446 : UInt<3>[1] - T_446[0] := UInt<3>("h05") - node T_449 = eq(T_446[0], grant.bits.payload.g_type) - node T_451 = or(UInt<1>("h00"), T_449) - wire T_453 : UInt<1>[2] - T_453[0] := UInt<1>("h00") - T_453[1] := UInt<1>("h01") - node T_457 = eq(T_453[0], grant.bits.payload.g_type) - node T_458 = eq(T_453[1], grant.bits.payload.g_type) - node T_460 = or(UInt<1>("h00"), T_457) - node T_461 = or(T_460, T_458) - node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) - node T_463 = and(UInt<1>("h01"), T_462) - node T_464 = and(T_441, T_463) - reg T_466 : UInt<2>, clock, reset - onreset T_466 := UInt<2>("h00") - when T_464 : - node T_468 = eq(T_466, UInt<2>("h03")) - node T_470 = and(UInt<1>("h00"), T_468) - node T_473 = addw(T_466, UInt<1>("h01")) - node T_474 = mux(T_470, UInt<1>("h00"), T_473) - T_466 := T_474 - skip - node T_475 = and(T_464, T_468) - node T_476 = mux(T_463, T_466, UInt<1>("h00")) - node T_477 = mux(T_463, T_475, T_441) - inst T_634 of FinishQueue - T_634.deq.ready := UInt<1>("h00") - T_634.enq.bits.dst := UInt<1>("h00") - T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") - T_634.enq.valid := UInt<1>("h00") - T_634.reset := UInt<1>("h00") - T_634.clock := clock - T_634.reset := reset - node T_533 = and(grant.ready, grant.valid) - node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_539 = and(grant.bits.payload.is_builtin_type, T_538) - node T_541 = eq(T_539, UInt<1>("h00")) - node T_542 = and(T_536, T_541) - node T_543 = and(T_533, T_542) - wire T_547 : UInt<3>[1] - T_547[0] := UInt<3>("h05") - node T_550 = eq(T_547[0], grant.bits.payload.g_type) - node T_552 = or(UInt<1>("h00"), T_550) - wire T_554 : UInt<1>[2] - T_554[0] := UInt<1>("h00") - T_554[1] := UInt<1>("h01") - node T_558 = eq(T_554[0], grant.bits.payload.g_type) - node T_559 = eq(T_554[1], grant.bits.payload.g_type) - node T_561 = or(UInt<1>("h00"), T_558) - node T_562 = or(T_561, T_559) - node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) - node T_564 = and(UInt<1>("h01"), T_563) - node T_566 = eq(T_564, UInt<1>("h00")) - node T_567 = or(T_566, T_477) - node T_568 = and(T_543, T_567) - T_634.enq.valid := T_568 - wire T_594 : {manager_xact_id : UInt<4>} - T_594.manager_xact_id := UInt<1>("h00") - T_594.manager_xact_id := grant.bits.payload.manager_xact_id - T_634.enq.bits.fin <> T_594 - T_634.enq.bits.dst := grant.bits.header.src - finish.bits.header.src := UInt<2>("h02") - finish.bits.header.dst := T_634.deq.bits.dst - finish.bits.payload <> T_634.deq.bits.fin - finish.valid := T_634.deq.valid - T_634.deq.ready := finish.ready - refill.valid := grant.valid - refill.bits <> grant.bits.payload - node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_626 = and(grant.bits.payload.is_builtin_type, T_625) - node T_628 = eq(T_626, UInt<1>("h00")) - node T_629 = and(T_623, T_628) - node T_631 = eq(T_629, UInt<1>("h00")) - node T_632 = or(T_634.enq.ready, T_631) - node T_633 = and(T_632, refill.ready) - grant.ready := T_633 - ready := T_634.enq.ready - - module ClientTileLinkNetworkPort_15 : - output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - network.release.bits.payload.voluntary := UInt<1>("h00") - network.release.bits.payload.r_type := UInt<1>("h00") - network.release.bits.payload.data := UInt<1>("h00") - network.release.bits.payload.addr_beat := UInt<1>("h00") - network.release.bits.payload.client_xact_id := UInt<1>("h00") - network.release.bits.payload.addr_block := UInt<1>("h00") - network.release.bits.header.dst := UInt<1>("h00") - network.release.bits.header.src := UInt<1>("h00") - network.release.valid := UInt<1>("h00") - network.probe.ready := UInt<1>("h00") - network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - network.finish.bits.header.dst := UInt<1>("h00") - network.finish.bits.header.src := UInt<1>("h00") - network.finish.valid := UInt<1>("h00") - network.grant.ready := UInt<1>("h00") - network.acquire.bits.payload.union := UInt<1>("h00") - network.acquire.bits.payload.a_type := UInt<1>("h00") - network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - network.acquire.bits.payload.data := UInt<1>("h00") - network.acquire.bits.payload.addr_beat := UInt<1>("h00") - network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - network.acquire.bits.payload.addr_block := UInt<1>("h00") - network.acquire.bits.header.dst := UInt<1>("h00") - network.acquire.bits.header.src := UInt<1>("h00") - network.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.p_type := UInt<1>("h00") - client.probe.bits.addr_block := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.grant.bits.g_type := UInt<1>("h00") - client.grant.bits.is_builtin_type := UInt<1>("h00") - client.grant.bits.manager_xact_id := UInt<1>("h00") - client.grant.bits.client_xact_id := UInt<1>("h00") - client.grant.bits.data := UInt<1>("h00") - client.grant.bits.addr_beat := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - inst finisher of FinishUnit_16 - finisher.finish.ready := UInt<1>("h00") - finisher.refill.ready := UInt<1>("h00") - finisher.grant.bits.payload.g_type := UInt<1>("h00") - finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") - finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.data := UInt<1>("h00") - finisher.grant.bits.payload.addr_beat := UInt<1>("h00") - finisher.grant.bits.header.dst := UInt<1>("h00") - finisher.grant.bits.header.src := UInt<1>("h00") - finisher.grant.valid := UInt<1>("h00") - finisher.reset := UInt<1>("h00") - finisher.clock := clock - finisher.reset := reset - finisher.grant <> network.grant - network.finish <> finisher.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - acq_with_header.bits.payload.union := UInt<1>("h00") - acq_with_header.bits.payload.a_type := UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") - acq_with_header.bits.payload.data := UInt<1>("h00") - acq_with_header.bits.payload.addr_beat := UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") - acq_with_header.bits.payload.addr_block := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.valid := UInt<1>("h00") - acq_with_header.ready := UInt<1>("h00") - acq_with_header.bits.payload <> client.acquire.bits - acq_with_header.bits.header.src := UInt<2>("h02") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.valid := client.acquire.valid - client.acquire.ready := acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - rel_with_header.bits.payload.voluntary := UInt<1>("h00") - rel_with_header.bits.payload.r_type := UInt<1>("h00") - rel_with_header.bits.payload.data := UInt<1>("h00") - rel_with_header.bits.payload.addr_beat := UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") - rel_with_header.bits.payload.addr_block := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.valid := UInt<1>("h00") - rel_with_header.ready := UInt<1>("h00") - rel_with_header.bits.payload <> client.release.bits - rel_with_header.bits.header.src := UInt<2>("h02") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.valid := client.release.valid - client.release.ready := rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type := UInt<1>("h00") - prb_without_header.bits.addr_block := UInt<1>("h00") - prb_without_header.valid := UInt<1>("h00") - prb_without_header.ready := UInt<1>("h00") - prb_without_header.valid := network.probe.valid - prb_without_header.bits <> network.probe.bits.payload - network.probe.ready := prb_without_header.ready - network.acquire.bits <> acq_with_header.bits - node T_2345 = and(acq_with_header.valid, finisher.ready) - network.acquire.valid := T_2345 - node T_2346 = and(network.acquire.ready, finisher.ready) - acq_with_header.ready := T_2346 - network.release <> rel_with_header - client.probe <> prb_without_header - client.grant <> finisher.refill - - module ManagerTileLinkNetworkPort : - input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - network.release.ready := UInt<1>("h00") - network.probe.bits.payload.p_type := UInt<1>("h00") - network.probe.bits.payload.addr_block := UInt<1>("h00") - network.probe.bits.header.dst := UInt<1>("h00") - network.probe.bits.header.src := UInt<1>("h00") - network.probe.valid := UInt<1>("h00") - network.finish.ready := UInt<1>("h00") - network.grant.bits.payload.g_type := UInt<1>("h00") - network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - network.grant.bits.payload.client_xact_id := UInt<1>("h00") - network.grant.bits.payload.data := UInt<1>("h00") - network.grant.bits.payload.addr_beat := UInt<1>("h00") - network.grant.bits.header.dst := UInt<1>("h00") - network.grant.bits.header.src := UInt<1>("h00") - network.grant.valid := UInt<1>("h00") - network.acquire.ready := UInt<1>("h00") - manager.release.bits.client_id := UInt<1>("h00") - manager.release.bits.voluntary := UInt<1>("h00") - manager.release.bits.r_type := UInt<1>("h00") - manager.release.bits.data := UInt<1>("h00") - manager.release.bits.addr_beat := UInt<1>("h00") - manager.release.bits.client_xact_id := UInt<1>("h00") - manager.release.bits.addr_block := UInt<1>("h00") - manager.release.valid := UInt<1>("h00") - manager.probe.ready := UInt<1>("h00") - manager.finish.bits.manager_xact_id := UInt<1>("h00") - manager.finish.valid := UInt<1>("h00") - manager.grant.ready := UInt<1>("h00") - manager.acquire.bits.client_id := UInt<1>("h00") - manager.acquire.bits.union := UInt<1>("h00") - manager.acquire.bits.a_type := UInt<1>("h00") - manager.acquire.bits.is_builtin_type := UInt<1>("h00") - manager.acquire.bits.data := UInt<1>("h00") - manager.acquire.bits.addr_beat := UInt<1>("h00") - manager.acquire.bits.client_xact_id := UInt<1>("h00") - manager.acquire.bits.addr_block := UInt<1>("h00") - manager.acquire.valid := UInt<1>("h00") - wire T_3060 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}} - T_3060.bits.payload.client_id := UInt<1>("h00") - T_3060.bits.payload.g_type := UInt<1>("h00") - T_3060.bits.payload.is_builtin_type := UInt<1>("h00") - T_3060.bits.payload.manager_xact_id := UInt<1>("h00") - T_3060.bits.payload.client_xact_id := UInt<1>("h00") - T_3060.bits.payload.data := UInt<1>("h00") - T_3060.bits.payload.addr_beat := UInt<1>("h00") - T_3060.bits.header.dst := UInt<1>("h00") - T_3060.bits.header.src := UInt<1>("h00") - T_3060.valid := UInt<1>("h00") - T_3060.ready := UInt<1>("h00") - T_3060.bits.payload <> manager.grant.bits - T_3060.bits.header.src := UInt<1>("h00") - T_3060.bits.header.dst := manager.grant.bits.client_id - T_3060.valid := manager.grant.valid - manager.grant.ready := T_3060.ready - network.grant <> T_3060 - wire T_3241 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} - T_3241.bits.payload.client_id := UInt<1>("h00") - T_3241.bits.payload.p_type := UInt<1>("h00") - T_3241.bits.payload.addr_block := UInt<1>("h00") - T_3241.bits.header.dst := UInt<1>("h00") - T_3241.bits.header.src := UInt<1>("h00") - T_3241.valid := UInt<1>("h00") - T_3241.ready := UInt<1>("h00") - T_3241.bits.payload <> manager.probe.bits - T_3241.bits.header.src := UInt<1>("h00") - T_3241.bits.header.dst := manager.probe.bits.client_id - T_3241.valid := manager.probe.valid - manager.probe.ready := T_3241.ready - network.probe <> T_3241 - manager.acquire.bits.client_id := network.acquire.bits.header.src - wire T_3379 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - T_3379.bits.union := UInt<1>("h00") - T_3379.bits.a_type := UInt<1>("h00") - T_3379.bits.is_builtin_type := UInt<1>("h00") - T_3379.bits.data := UInt<1>("h00") - T_3379.bits.addr_beat := UInt<1>("h00") - T_3379.bits.client_xact_id := UInt<1>("h00") - T_3379.bits.addr_block := UInt<1>("h00") - T_3379.valid := UInt<1>("h00") - T_3379.ready := UInt<1>("h00") - T_3379.valid := network.acquire.valid - T_3379.bits <> network.acquire.bits.payload - network.acquire.ready := T_3379.ready - manager.acquire <> T_3379 - manager.release.bits.client_id := network.release.bits.header.src - wire T_3516 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - T_3516.bits.voluntary := UInt<1>("h00") - T_3516.bits.r_type := UInt<1>("h00") - T_3516.bits.data := UInt<1>("h00") - T_3516.bits.addr_beat := UInt<1>("h00") - T_3516.bits.client_xact_id := UInt<1>("h00") - T_3516.bits.addr_block := UInt<1>("h00") - T_3516.valid := UInt<1>("h00") - T_3516.ready := UInt<1>("h00") - T_3516.valid := network.release.valid - T_3516.bits <> network.release.bits.payload - network.release.ready := T_3516.ready - manager.release <> T_3516 - wire T_3640 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} - T_3640.bits.manager_xact_id := UInt<1>("h00") - T_3640.valid := UInt<1>("h00") - T_3640.ready := UInt<1>("h00") - T_3640.valid := network.finish.valid - T_3640.bits <> network.finish.bits.payload - network.finish.ready := T_3640.ready - manager.finish <> T_3640 - - module Queue_25 : - output count : UInt<1> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.payload.voluntary := UInt<1>("h00") - deq.bits.payload.r_type := UInt<1>("h00") - deq.bits.payload.data := UInt<1>("h00") - deq.bits.payload.addr_beat := UInt<1>("h00") - deq.bits.payload.client_xact_id := UInt<1>("h00") - deq.bits.payload.addr_block := UInt<1>("h00") - deq.bits.header.dst := UInt<1>("h00") - deq.bits.header.src := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_327 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_327) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_333 = and(enq.ready, enq.valid) - node T_335 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_333, T_335) - node T_337 = and(deq.ready, deq.valid) - node T_339 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_337, T_339) - when do_enq : - infer accessor T_341 = ram[UInt<1>("h00")] - T_341 <> enq.bits - skip - when do_deq : - skip - node T_377 = neq(do_enq, do_deq) - when T_377 : - maybe_full := do_enq - skip - node T_379 = eq(empty, UInt<1>("h00")) - node T_381 = and(UInt<1>("h00"), enq.valid) - node T_382 = or(T_379, T_381) - deq.valid := T_382 - node T_384 = eq(full, UInt<1>("h00")) - node T_386 = and(UInt<1>("h00"), deq.ready) - node T_387 = or(T_384, T_386) - enq.ready := T_387 - infer accessor T_388 = ram[UInt<1>("h00")] - wire T_456 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - T_456 <> T_388 - when maybe_flow : - T_456 <> enq.bits - skip - deq.bits <> T_456 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_491 = and(maybe_full, ptr_match) - node T_492 = cat(T_491, ptr_diff) - count := T_492 - - module TileLinkEnqueuer_24 : - output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input clock : Clock - input reset : UInt<1> - - manager.release.bits.payload.voluntary := UInt<1>("h00") - manager.release.bits.payload.r_type := UInt<1>("h00") - manager.release.bits.payload.data := UInt<1>("h00") - manager.release.bits.payload.addr_beat := UInt<1>("h00") - manager.release.bits.payload.client_xact_id := UInt<1>("h00") - manager.release.bits.payload.addr_block := UInt<1>("h00") - manager.release.bits.header.dst := UInt<1>("h00") - manager.release.bits.header.src := UInt<1>("h00") - manager.release.valid := UInt<1>("h00") - manager.probe.ready := UInt<1>("h00") - manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") - manager.finish.bits.header.dst := UInt<1>("h00") - manager.finish.bits.header.src := UInt<1>("h00") - manager.finish.valid := UInt<1>("h00") - manager.grant.ready := UInt<1>("h00") - manager.acquire.bits.payload.union := UInt<1>("h00") - manager.acquire.bits.payload.a_type := UInt<1>("h00") - manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - manager.acquire.bits.payload.data := UInt<1>("h00") - manager.acquire.bits.payload.addr_beat := UInt<1>("h00") - manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") - manager.acquire.bits.payload.addr_block := UInt<1>("h00") - manager.acquire.bits.header.dst := UInt<1>("h00") - manager.acquire.bits.header.src := UInt<1>("h00") - manager.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.payload.p_type := UInt<1>("h00") - client.probe.bits.payload.addr_block := UInt<1>("h00") - client.probe.bits.header.dst := UInt<1>("h00") - client.probe.bits.header.src := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.finish.ready := UInt<1>("h00") - client.grant.bits.payload.g_type := UInt<1>("h00") - client.grant.bits.payload.is_builtin_type := UInt<1>("h00") - client.grant.bits.payload.manager_xact_id := UInt<1>("h00") - client.grant.bits.payload.client_xact_id := UInt<1>("h00") - client.grant.bits.payload.data := UInt<1>("h00") - client.grant.bits.payload.addr_beat := UInt<1>("h00") - client.grant.bits.header.dst := UInt<1>("h00") - client.grant.bits.header.src := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - manager.acquire <> client.acquire - client.probe <> manager.probe - inst T_2451 of Queue_25 - T_2451.deq.ready := UInt<1>("h00") - T_2451.enq.bits.payload.voluntary := UInt<1>("h00") - T_2451.enq.bits.payload.r_type := UInt<1>("h00") - T_2451.enq.bits.payload.data := UInt<1>("h00") - T_2451.enq.bits.payload.addr_beat := UInt<1>("h00") - T_2451.enq.bits.payload.client_xact_id := UInt<1>("h00") - T_2451.enq.bits.payload.addr_block := UInt<1>("h00") - T_2451.enq.bits.header.dst := UInt<1>("h00") - T_2451.enq.bits.header.src := UInt<1>("h00") - T_2451.enq.valid := UInt<1>("h00") - T_2451.reset := UInt<1>("h00") - T_2451.clock := clock - T_2451.reset := reset - T_2451.enq.valid := client.release.valid - T_2451.enq.bits <> client.release.bits - client.release.ready := T_2451.enq.ready - manager.release <> T_2451.deq - client.grant <> manager.grant - manager.finish <> client.finish - - module LockingRRArbiter : - output chosen : UInt<2> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}[3] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.payload.union := UInt<1>("h00") - out.bits.payload.a_type := UInt<1>("h00") - out.bits.payload.is_builtin_type := UInt<1>("h00") - out.bits.payload.data := UInt<1>("h00") - out.bits.payload.addr_beat := UInt<1>("h00") - out.bits.payload.client_xact_id := UInt<1>("h00") - out.bits.payload.addr_block := UInt<1>("h00") - out.bits.header.dst := UInt<1>("h00") - out.bits.header.src := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - reg T_956 : UInt<1>, clock, reset - onreset T_956 := UInt<1>("h00") - reg T_958 : UInt, clock, reset - onreset T_958 := UInt<2>("h02") - wire T_960 : UInt<2> - T_960 := UInt<1>("h00") - infer accessor T_962 = in[T_960] - out.valid := T_962.valid - infer accessor T_1035 = in[T_960] - out.bits <> T_1035.bits - chosen := T_960 - infer accessor T_1108 = in[T_960] - T_1108.ready := UInt<1>("h00") - reg last_grant : UInt<2>, clock, reset - onreset last_grant := UInt<2>("h00") - node T_1185 = gt(UInt<1>("h00"), last_grant) - node T_1186 = and(in[0].valid, T_1185) - node T_1188 = gt(UInt<1>("h01"), last_grant) - node T_1189 = and(in[1].valid, T_1188) - node T_1191 = gt(UInt<2>("h02"), last_grant) - node T_1192 = and(in[2].valid, T_1191) - node T_1195 = or(UInt<1>("h00"), T_1186) - node T_1197 = eq(T_1195, UInt<1>("h00")) - node T_1199 = or(UInt<1>("h00"), T_1186) - node T_1200 = or(T_1199, T_1189) - node T_1202 = eq(T_1200, UInt<1>("h00")) - node T_1204 = or(UInt<1>("h00"), T_1186) - node T_1205 = or(T_1204, T_1189) - node T_1206 = or(T_1205, T_1192) - node T_1208 = eq(T_1206, UInt<1>("h00")) - node T_1210 = or(UInt<1>("h00"), T_1186) - node T_1211 = or(T_1210, T_1189) - node T_1212 = or(T_1211, T_1192) - node T_1213 = or(T_1212, in[0].valid) - node T_1215 = eq(T_1213, UInt<1>("h00")) - node T_1217 = or(UInt<1>("h00"), T_1186) - node T_1218 = or(T_1217, T_1189) - node T_1219 = or(T_1218, T_1192) - node T_1220 = or(T_1219, in[0].valid) - node T_1221 = or(T_1220, in[1].valid) - node T_1223 = eq(T_1221, UInt<1>("h00")) - node T_1225 = gt(UInt<1>("h00"), last_grant) - node T_1226 = and(UInt<1>("h01"), T_1225) - node T_1227 = or(T_1226, T_1208) - node T_1229 = gt(UInt<1>("h01"), last_grant) - node T_1230 = and(T_1197, T_1229) - node T_1231 = or(T_1230, T_1215) - node T_1233 = gt(UInt<2>("h02"), last_grant) - node T_1234 = and(T_1202, T_1233) - node T_1235 = or(T_1234, T_1223) - node T_1237 = eq(T_958, UInt<1>("h00")) - node T_1238 = mux(T_956, T_1237, T_1227) - node T_1239 = and(T_1238, out.ready) - in[0].ready := T_1239 - node T_1241 = eq(T_958, UInt<1>("h01")) - node T_1242 = mux(T_956, T_1241, T_1231) - node T_1243 = and(T_1242, out.ready) - in[1].ready := T_1243 - node T_1245 = eq(T_958, UInt<2>("h02")) - node T_1246 = mux(T_956, T_1245, T_1235) - node T_1247 = and(T_1246, out.ready) - in[2].ready := T_1247 - reg T_1249 : UInt<2>, clock, reset - onreset T_1249 := UInt<2>("h00") - node T_1251 = addw(T_1249, UInt<1>("h01")) - node T_1252 = and(out.ready, out.valid) - when T_1252 : - node T_1254 = and(UInt<1>("h01"), out.bits.payload.is_builtin_type) - wire T_1257 : UInt<3>[1] - T_1257[0] := UInt<3>("h03") - node T_1260 = eq(T_1257[0], out.bits.payload.a_type) - node T_1262 = or(UInt<1>("h00"), T_1260) - node T_1263 = and(T_1254, T_1262) - when T_1263 : - T_1249 := T_1251 - node T_1265 = eq(T_956, UInt<1>("h00")) - when T_1265 : - T_956 := UInt<1>("h01") - node T_1267 = and(in[0].ready, in[0].valid) - node T_1268 = and(in[1].ready, in[1].valid) - node T_1269 = and(in[2].ready, in[2].valid) - wire T_1271 : UInt<1>[3] - T_1271[0] := T_1267 - T_1271[1] := T_1268 - T_1271[2] := T_1269 - node T_1279 = mux(T_1271[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1280 = mux(T_1271[0], UInt<1>("h00"), T_1279) - T_958 := T_1280 - skip - skip - node T_1282 = eq(T_1251, UInt<1>("h00")) - when T_1282 : - T_956 := UInt<1>("h00") - skip - skip - node T_1286 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_1288 = mux(in[0].valid, UInt<1>("h00"), T_1286) - node T_1290 = gt(UInt<2>("h02"), last_grant) - node T_1291 = and(in[2].valid, T_1290) - node T_1293 = mux(T_1291, UInt<2>("h02"), T_1288) - node T_1295 = gt(UInt<1>("h01"), last_grant) - node T_1296 = and(in[1].valid, T_1295) - node choose = mux(T_1296, UInt<1>("h01"), T_1293) - node T_1299 = mux(T_956, T_958, choose) - T_960 := T_1299 - node T_1300 = and(out.ready, out.valid) - when T_1300 : - last_grant := T_960 - skip - - module LockingRRArbiter_26 : - output chosen : UInt<2> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.payload.voluntary := UInt<1>("h00") - out.bits.payload.r_type := UInt<1>("h00") - out.bits.payload.data := UInt<1>("h00") - out.bits.payload.addr_beat := UInt<1>("h00") - out.bits.payload.client_xact_id := UInt<1>("h00") - out.bits.payload.addr_block := UInt<1>("h00") - out.bits.header.dst := UInt<1>("h00") - out.bits.header.src := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - reg T_930 : UInt<1>, clock, reset - onreset T_930 := UInt<1>("h00") - reg T_932 : UInt, clock, reset - onreset T_932 := UInt<2>("h02") - wire T_934 : UInt<2> - T_934 := UInt<1>("h00") - infer accessor T_936 = in[T_934] - out.valid := T_936.valid - infer accessor T_1007 = in[T_934] - out.bits <> T_1007.bits - chosen := T_934 - infer accessor T_1078 = in[T_934] - T_1078.ready := UInt<1>("h00") - reg last_grant : UInt<2>, clock, reset - onreset last_grant := UInt<2>("h00") - node T_1153 = gt(UInt<1>("h00"), last_grant) - node T_1154 = and(in[0].valid, T_1153) - node T_1156 = gt(UInt<1>("h01"), last_grant) - node T_1157 = and(in[1].valid, T_1156) - node T_1159 = gt(UInt<2>("h02"), last_grant) - node T_1160 = and(in[2].valid, T_1159) - node T_1163 = or(UInt<1>("h00"), T_1154) - node T_1165 = eq(T_1163, UInt<1>("h00")) - node T_1167 = or(UInt<1>("h00"), T_1154) - node T_1168 = or(T_1167, T_1157) - node T_1170 = eq(T_1168, UInt<1>("h00")) - node T_1172 = or(UInt<1>("h00"), T_1154) - node T_1173 = or(T_1172, T_1157) - node T_1174 = or(T_1173, T_1160) - node T_1176 = eq(T_1174, UInt<1>("h00")) - node T_1178 = or(UInt<1>("h00"), T_1154) - node T_1179 = or(T_1178, T_1157) - node T_1180 = or(T_1179, T_1160) - node T_1181 = or(T_1180, in[0].valid) - node T_1183 = eq(T_1181, UInt<1>("h00")) - node T_1185 = or(UInt<1>("h00"), T_1154) - node T_1186 = or(T_1185, T_1157) - node T_1187 = or(T_1186, T_1160) - node T_1188 = or(T_1187, in[0].valid) - node T_1189 = or(T_1188, in[1].valid) - node T_1191 = eq(T_1189, UInt<1>("h00")) - node T_1193 = gt(UInt<1>("h00"), last_grant) - node T_1194 = and(UInt<1>("h01"), T_1193) - node T_1195 = or(T_1194, T_1176) - node T_1197 = gt(UInt<1>("h01"), last_grant) - node T_1198 = and(T_1165, T_1197) - node T_1199 = or(T_1198, T_1183) - node T_1201 = gt(UInt<2>("h02"), last_grant) - node T_1202 = and(T_1170, T_1201) - node T_1203 = or(T_1202, T_1191) - node T_1205 = eq(T_932, UInt<1>("h00")) - node T_1206 = mux(T_930, T_1205, T_1195) - node T_1207 = and(T_1206, out.ready) - in[0].ready := T_1207 - node T_1209 = eq(T_932, UInt<1>("h01")) - node T_1210 = mux(T_930, T_1209, T_1199) - node T_1211 = and(T_1210, out.ready) - in[1].ready := T_1211 - node T_1213 = eq(T_932, UInt<2>("h02")) - node T_1214 = mux(T_930, T_1213, T_1203) - node T_1215 = and(T_1214, out.ready) - in[2].ready := T_1215 - reg T_1217 : UInt<2>, clock, reset - onreset T_1217 := UInt<2>("h00") - node T_1219 = addw(T_1217, UInt<1>("h01")) - node T_1220 = and(out.ready, out.valid) - when T_1220 : - wire T_1223 : UInt<2>[3] - T_1223[0] := UInt<1>("h00") - T_1223[1] := UInt<1>("h01") - T_1223[2] := UInt<2>("h02") - node T_1228 = eq(T_1223[0], out.bits.payload.r_type) - node T_1229 = eq(T_1223[1], out.bits.payload.r_type) - node T_1230 = eq(T_1223[2], out.bits.payload.r_type) - node T_1232 = or(UInt<1>("h00"), T_1228) - node T_1233 = or(T_1232, T_1229) - node T_1234 = or(T_1233, T_1230) - node T_1235 = and(UInt<1>("h01"), T_1234) - when T_1235 : - T_1217 := T_1219 - node T_1237 = eq(T_930, UInt<1>("h00")) - when T_1237 : - T_930 := UInt<1>("h01") - node T_1239 = and(in[0].ready, in[0].valid) - node T_1240 = and(in[1].ready, in[1].valid) - node T_1241 = and(in[2].ready, in[2].valid) - wire T_1243 : UInt<1>[3] - T_1243[0] := T_1239 - T_1243[1] := T_1240 - T_1243[2] := T_1241 - node T_1251 = mux(T_1243[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1252 = mux(T_1243[0], UInt<1>("h00"), T_1251) - T_932 := T_1252 - skip - skip - node T_1254 = eq(T_1219, UInt<1>("h00")) - when T_1254 : - T_930 := UInt<1>("h00") - skip - skip - node T_1258 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_1260 = mux(in[0].valid, UInt<1>("h00"), T_1258) - node T_1262 = gt(UInt<2>("h02"), last_grant) - node T_1263 = and(in[2].valid, T_1262) - node T_1265 = mux(T_1263, UInt<2>("h02"), T_1260) - node T_1267 = gt(UInt<1>("h01"), last_grant) - node T_1268 = and(in[1].valid, T_1267) - node choose = mux(T_1268, UInt<1>("h01"), T_1265) - node T_1271 = mux(T_930, T_932, choose) - T_934 := T_1271 - node T_1272 = and(out.ready, out.valid) - when T_1272 : - last_grant := T_934 - skip - - module RRArbiter : - output chosen : UInt<2> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.payload.manager_xact_id := UInt<1>("h00") - out.bits.header.dst := UInt<1>("h00") - out.bits.header.src := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - wire T_802 : UInt<2> - T_802 := UInt<1>("h00") - infer accessor T_804 = in[T_802] - out.valid := T_804.valid - infer accessor T_865 = in[T_802] - out.bits <> T_865.bits - chosen := T_802 - infer accessor T_926 = in[T_802] - T_926.ready := UInt<1>("h00") - reg T_990 : UInt<2>, clock, reset - onreset T_990 := UInt<2>("h00") - node T_991 = gt(UInt<1>("h00"), T_990) - node T_992 = and(in[0].valid, T_991) - node T_994 = gt(UInt<1>("h01"), T_990) - node T_995 = and(in[1].valid, T_994) - node T_997 = gt(UInt<2>("h02"), T_990) - node T_998 = and(in[2].valid, T_997) - node T_1001 = or(UInt<1>("h00"), T_992) - node T_1003 = eq(T_1001, UInt<1>("h00")) - node T_1005 = or(UInt<1>("h00"), T_992) - node T_1006 = or(T_1005, T_995) - node T_1008 = eq(T_1006, UInt<1>("h00")) - node T_1010 = or(UInt<1>("h00"), T_992) - node T_1011 = or(T_1010, T_995) - node T_1012 = or(T_1011, T_998) - node T_1014 = eq(T_1012, UInt<1>("h00")) - node T_1016 = or(UInt<1>("h00"), T_992) - node T_1017 = or(T_1016, T_995) - node T_1018 = or(T_1017, T_998) - node T_1019 = or(T_1018, in[0].valid) - node T_1021 = eq(T_1019, UInt<1>("h00")) - node T_1023 = or(UInt<1>("h00"), T_992) - node T_1024 = or(T_1023, T_995) - node T_1025 = or(T_1024, T_998) - node T_1026 = or(T_1025, in[0].valid) - node T_1027 = or(T_1026, in[1].valid) - node T_1029 = eq(T_1027, UInt<1>("h00")) - node T_1031 = gt(UInt<1>("h00"), T_990) - node T_1032 = and(UInt<1>("h01"), T_1031) - node T_1033 = or(T_1032, T_1014) - node T_1035 = gt(UInt<1>("h01"), T_990) - node T_1036 = and(T_1003, T_1035) - node T_1037 = or(T_1036, T_1021) - node T_1039 = gt(UInt<2>("h02"), T_990) - node T_1040 = and(T_1008, T_1039) - node T_1041 = or(T_1040, T_1029) - node T_1043 = eq(UInt<2>("h02"), UInt<1>("h00")) - node T_1044 = mux(UInt<1>("h00"), T_1043, T_1033) - node T_1045 = and(T_1044, out.ready) - in[0].ready := T_1045 - node T_1047 = eq(UInt<2>("h02"), UInt<1>("h01")) - node T_1048 = mux(UInt<1>("h00"), T_1047, T_1037) - node T_1049 = and(T_1048, out.ready) - in[1].ready := T_1049 - node T_1051 = eq(UInt<2>("h02"), UInt<2>("h02")) - node T_1052 = mux(UInt<1>("h00"), T_1051, T_1041) - node T_1053 = and(T_1052, out.ready) - in[2].ready := T_1053 - node T_1056 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_1058 = mux(in[0].valid, UInt<1>("h00"), T_1056) - node T_1060 = gt(UInt<2>("h02"), T_990) - node T_1061 = and(in[2].valid, T_1060) - node T_1063 = mux(T_1061, UInt<2>("h02"), T_1058) - node T_1065 = gt(UInt<1>("h01"), T_990) - node T_1066 = and(in[1].valid, T_1065) - node T_1068 = mux(T_1066, UInt<1>("h01"), T_1063) - node T_1069 = mux(UInt<1>("h00"), UInt<2>("h02"), T_1068) - T_802 := T_1069 - node T_1070 = and(out.ready, out.valid) - when T_1070 : - T_990 := T_802 - skip - - module RocketChipTileLinkArbiter : - input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}[1] - input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3] - input clock : Clock - input reset : UInt<1> - - managers[0].release.bits.client_id := UInt<1>("h00") - managers[0].release.bits.voluntary := UInt<1>("h00") - managers[0].release.bits.r_type := UInt<1>("h00") - managers[0].release.bits.data := UInt<1>("h00") - managers[0].release.bits.addr_beat := UInt<1>("h00") - managers[0].release.bits.client_xact_id := UInt<1>("h00") - managers[0].release.bits.addr_block := UInt<1>("h00") - managers[0].release.valid := UInt<1>("h00") - managers[0].probe.ready := UInt<1>("h00") - managers[0].finish.bits.manager_xact_id := UInt<1>("h00") - managers[0].finish.valid := UInt<1>("h00") - managers[0].grant.ready := UInt<1>("h00") - managers[0].acquire.bits.client_id := UInt<1>("h00") - managers[0].acquire.bits.union := UInt<1>("h00") - managers[0].acquire.bits.a_type := UInt<1>("h00") - managers[0].acquire.bits.is_builtin_type := UInt<1>("h00") - managers[0].acquire.bits.data := UInt<1>("h00") - managers[0].acquire.bits.addr_beat := UInt<1>("h00") - managers[0].acquire.bits.client_xact_id := UInt<1>("h00") - managers[0].acquire.bits.addr_block := UInt<1>("h00") - managers[0].acquire.valid := UInt<1>("h00") - clients[0].release.ready := UInt<1>("h00") - clients[0].probe.bits.p_type := UInt<1>("h00") - clients[0].probe.bits.addr_block := UInt<1>("h00") - clients[0].probe.valid := UInt<1>("h00") - clients[0].grant.bits.g_type := UInt<1>("h00") - clients[0].grant.bits.is_builtin_type := UInt<1>("h00") - clients[0].grant.bits.manager_xact_id := UInt<1>("h00") - clients[0].grant.bits.client_xact_id := UInt<1>("h00") - clients[0].grant.bits.data := UInt<1>("h00") - clients[0].grant.bits.addr_beat := UInt<1>("h00") - clients[0].grant.valid := UInt<1>("h00") - clients[0].acquire.ready := UInt<1>("h00") - clients[1].release.ready := UInt<1>("h00") - clients[1].probe.bits.p_type := UInt<1>("h00") - clients[1].probe.bits.addr_block := UInt<1>("h00") - clients[1].probe.valid := UInt<1>("h00") - clients[1].grant.bits.g_type := UInt<1>("h00") - clients[1].grant.bits.is_builtin_type := UInt<1>("h00") - clients[1].grant.bits.manager_xact_id := UInt<1>("h00") - clients[1].grant.bits.client_xact_id := UInt<1>("h00") - clients[1].grant.bits.data := UInt<1>("h00") - clients[1].grant.bits.addr_beat := UInt<1>("h00") - clients[1].grant.valid := UInt<1>("h00") - clients[1].acquire.ready := UInt<1>("h00") - clients[2].release.ready := UInt<1>("h00") - clients[2].probe.bits.p_type := UInt<1>("h00") - clients[2].probe.bits.addr_block := UInt<1>("h00") - clients[2].probe.valid := UInt<1>("h00") - clients[2].grant.bits.g_type := UInt<1>("h00") - clients[2].grant.bits.is_builtin_type := UInt<1>("h00") - clients[2].grant.bits.manager_xact_id := UInt<1>("h00") - clients[2].grant.bits.client_xact_id := UInt<1>("h00") - clients[2].grant.bits.data := UInt<1>("h00") - clients[2].grant.bits.addr_beat := UInt<1>("h00") - clients[2].grant.valid := UInt<1>("h00") - clients[2].acquire.ready := UInt<1>("h00") - inst T_11799 of ClientTileLinkNetworkPort - T_11799.network.release.ready := UInt<1>("h00") - T_11799.network.probe.bits.payload.p_type := UInt<1>("h00") - T_11799.network.probe.bits.payload.addr_block := UInt<1>("h00") - T_11799.network.probe.bits.header.dst := UInt<1>("h00") - T_11799.network.probe.bits.header.src := UInt<1>("h00") - T_11799.network.probe.valid := UInt<1>("h00") - T_11799.network.finish.ready := UInt<1>("h00") - T_11799.network.grant.bits.payload.g_type := UInt<1>("h00") - T_11799.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11799.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11799.network.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11799.network.grant.bits.payload.data := UInt<1>("h00") - T_11799.network.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11799.network.grant.bits.header.dst := UInt<1>("h00") - T_11799.network.grant.bits.header.src := UInt<1>("h00") - T_11799.network.grant.valid := UInt<1>("h00") - T_11799.network.acquire.ready := UInt<1>("h00") - T_11799.client.release.bits.voluntary := UInt<1>("h00") - T_11799.client.release.bits.r_type := UInt<1>("h00") - T_11799.client.release.bits.data := UInt<1>("h00") - T_11799.client.release.bits.addr_beat := UInt<1>("h00") - T_11799.client.release.bits.client_xact_id := UInt<1>("h00") - T_11799.client.release.bits.addr_block := UInt<1>("h00") - T_11799.client.release.valid := UInt<1>("h00") - T_11799.client.probe.ready := UInt<1>("h00") - T_11799.client.grant.ready := UInt<1>("h00") - T_11799.client.acquire.bits.union := UInt<1>("h00") - T_11799.client.acquire.bits.a_type := UInt<1>("h00") - T_11799.client.acquire.bits.is_builtin_type := UInt<1>("h00") - T_11799.client.acquire.bits.data := UInt<1>("h00") - T_11799.client.acquire.bits.addr_beat := UInt<1>("h00") - T_11799.client.acquire.bits.client_xact_id := UInt<1>("h00") - T_11799.client.acquire.bits.addr_block := UInt<1>("h00") - T_11799.client.acquire.valid := UInt<1>("h00") - T_11799.reset := UInt<1>("h00") - T_11799.clock := clock - T_11799.reset := reset - inst T_11800 of TileLinkEnqueuer - T_11800.manager.release.ready := UInt<1>("h00") - T_11800.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_11800.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_11800.manager.probe.bits.header.dst := UInt<1>("h00") - T_11800.manager.probe.bits.header.src := UInt<1>("h00") - T_11800.manager.probe.valid := UInt<1>("h00") - T_11800.manager.finish.ready := UInt<1>("h00") - T_11800.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_11800.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11800.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11800.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11800.manager.grant.bits.payload.data := UInt<1>("h00") - T_11800.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11800.manager.grant.bits.header.dst := UInt<1>("h00") - T_11800.manager.grant.bits.header.src := UInt<1>("h00") - T_11800.manager.grant.valid := UInt<1>("h00") - T_11800.manager.acquire.ready := UInt<1>("h00") - T_11800.client.release.bits.payload.voluntary := UInt<1>("h00") - T_11800.client.release.bits.payload.r_type := UInt<1>("h00") - T_11800.client.release.bits.payload.data := UInt<1>("h00") - T_11800.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_11800.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_11800.client.release.bits.payload.addr_block := UInt<1>("h00") - T_11800.client.release.bits.header.dst := UInt<1>("h00") - T_11800.client.release.bits.header.src := UInt<1>("h00") - T_11800.client.release.valid := UInt<1>("h00") - T_11800.client.probe.ready := UInt<1>("h00") - T_11800.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_11800.client.finish.bits.header.dst := UInt<1>("h00") - T_11800.client.finish.bits.header.src := UInt<1>("h00") - T_11800.client.finish.valid := UInt<1>("h00") - T_11800.client.grant.ready := UInt<1>("h00") - T_11800.client.acquire.bits.payload.union := UInt<1>("h00") - T_11800.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_11800.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_11800.client.acquire.bits.payload.data := UInt<1>("h00") - T_11800.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_11800.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_11800.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_11800.client.acquire.bits.header.dst := UInt<1>("h00") - T_11800.client.acquire.bits.header.src := UInt<1>("h00") - T_11800.client.acquire.valid := UInt<1>("h00") - T_11800.reset := UInt<1>("h00") - T_11800.clock := clock - T_11800.reset := reset - T_11799.client <> clients[0] - T_11800.client <> T_11799.network - inst T_11801 of ClientTileLinkNetworkPort_6 - T_11801.network.release.ready := UInt<1>("h00") - T_11801.network.probe.bits.payload.p_type := UInt<1>("h00") - T_11801.network.probe.bits.payload.addr_block := UInt<1>("h00") - T_11801.network.probe.bits.header.dst := UInt<1>("h00") - T_11801.network.probe.bits.header.src := UInt<1>("h00") - T_11801.network.probe.valid := UInt<1>("h00") - T_11801.network.finish.ready := UInt<1>("h00") - T_11801.network.grant.bits.payload.g_type := UInt<1>("h00") - T_11801.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11801.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11801.network.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11801.network.grant.bits.payload.data := UInt<1>("h00") - T_11801.network.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11801.network.grant.bits.header.dst := UInt<1>("h00") - T_11801.network.grant.bits.header.src := UInt<1>("h00") - T_11801.network.grant.valid := UInt<1>("h00") - T_11801.network.acquire.ready := UInt<1>("h00") - T_11801.client.release.bits.voluntary := UInt<1>("h00") - T_11801.client.release.bits.r_type := UInt<1>("h00") - T_11801.client.release.bits.data := UInt<1>("h00") - T_11801.client.release.bits.addr_beat := UInt<1>("h00") - T_11801.client.release.bits.client_xact_id := UInt<1>("h00") - T_11801.client.release.bits.addr_block := UInt<1>("h00") - T_11801.client.release.valid := UInt<1>("h00") - T_11801.client.probe.ready := UInt<1>("h00") - T_11801.client.grant.ready := UInt<1>("h00") - T_11801.client.acquire.bits.union := UInt<1>("h00") - T_11801.client.acquire.bits.a_type := UInt<1>("h00") - T_11801.client.acquire.bits.is_builtin_type := UInt<1>("h00") - T_11801.client.acquire.bits.data := UInt<1>("h00") - T_11801.client.acquire.bits.addr_beat := UInt<1>("h00") - T_11801.client.acquire.bits.client_xact_id := UInt<1>("h00") - T_11801.client.acquire.bits.addr_block := UInt<1>("h00") - T_11801.client.acquire.valid := UInt<1>("h00") - T_11801.reset := UInt<1>("h00") - T_11801.clock := clock - T_11801.reset := reset - inst T_11802 of TileLinkEnqueuer - T_11802.manager.release.ready := UInt<1>("h00") - T_11802.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_11802.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_11802.manager.probe.bits.header.dst := UInt<1>("h00") - T_11802.manager.probe.bits.header.src := UInt<1>("h00") - T_11802.manager.probe.valid := UInt<1>("h00") - T_11802.manager.finish.ready := UInt<1>("h00") - T_11802.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_11802.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11802.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11802.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11802.manager.grant.bits.payload.data := UInt<1>("h00") - T_11802.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11802.manager.grant.bits.header.dst := UInt<1>("h00") - T_11802.manager.grant.bits.header.src := UInt<1>("h00") - T_11802.manager.grant.valid := UInt<1>("h00") - T_11802.manager.acquire.ready := UInt<1>("h00") - T_11802.client.release.bits.payload.voluntary := UInt<1>("h00") - T_11802.client.release.bits.payload.r_type := UInt<1>("h00") - T_11802.client.release.bits.payload.data := UInt<1>("h00") - T_11802.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_11802.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_11802.client.release.bits.payload.addr_block := UInt<1>("h00") - T_11802.client.release.bits.header.dst := UInt<1>("h00") - T_11802.client.release.bits.header.src := UInt<1>("h00") - T_11802.client.release.valid := UInt<1>("h00") - T_11802.client.probe.ready := UInt<1>("h00") - T_11802.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_11802.client.finish.bits.header.dst := UInt<1>("h00") - T_11802.client.finish.bits.header.src := UInt<1>("h00") - T_11802.client.finish.valid := UInt<1>("h00") - T_11802.client.grant.ready := UInt<1>("h00") - T_11802.client.acquire.bits.payload.union := UInt<1>("h00") - T_11802.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_11802.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_11802.client.acquire.bits.payload.data := UInt<1>("h00") - T_11802.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_11802.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_11802.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_11802.client.acquire.bits.header.dst := UInt<1>("h00") - T_11802.client.acquire.bits.header.src := UInt<1>("h00") - T_11802.client.acquire.valid := UInt<1>("h00") - T_11802.reset := UInt<1>("h00") - T_11802.clock := clock - T_11802.reset := reset - T_11801.client <> clients[1] - T_11802.client <> T_11801.network - inst T_11803 of ClientTileLinkNetworkPort_15 - T_11803.network.release.ready := UInt<1>("h00") - T_11803.network.probe.bits.payload.p_type := UInt<1>("h00") - T_11803.network.probe.bits.payload.addr_block := UInt<1>("h00") - T_11803.network.probe.bits.header.dst := UInt<1>("h00") - T_11803.network.probe.bits.header.src := UInt<1>("h00") - T_11803.network.probe.valid := UInt<1>("h00") - T_11803.network.finish.ready := UInt<1>("h00") - T_11803.network.grant.bits.payload.g_type := UInt<1>("h00") - T_11803.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11803.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11803.network.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11803.network.grant.bits.payload.data := UInt<1>("h00") - T_11803.network.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11803.network.grant.bits.header.dst := UInt<1>("h00") - T_11803.network.grant.bits.header.src := UInt<1>("h00") - T_11803.network.grant.valid := UInt<1>("h00") - T_11803.network.acquire.ready := UInt<1>("h00") - T_11803.client.release.bits.voluntary := UInt<1>("h00") - T_11803.client.release.bits.r_type := UInt<1>("h00") - T_11803.client.release.bits.data := UInt<1>("h00") - T_11803.client.release.bits.addr_beat := UInt<1>("h00") - T_11803.client.release.bits.client_xact_id := UInt<1>("h00") - T_11803.client.release.bits.addr_block := UInt<1>("h00") - T_11803.client.release.valid := UInt<1>("h00") - T_11803.client.probe.ready := UInt<1>("h00") - T_11803.client.grant.ready := UInt<1>("h00") - T_11803.client.acquire.bits.union := UInt<1>("h00") - T_11803.client.acquire.bits.a_type := UInt<1>("h00") - T_11803.client.acquire.bits.is_builtin_type := UInt<1>("h00") - T_11803.client.acquire.bits.data := UInt<1>("h00") - T_11803.client.acquire.bits.addr_beat := UInt<1>("h00") - T_11803.client.acquire.bits.client_xact_id := UInt<1>("h00") - T_11803.client.acquire.bits.addr_block := UInt<1>("h00") - T_11803.client.acquire.valid := UInt<1>("h00") - T_11803.reset := UInt<1>("h00") - T_11803.clock := clock - T_11803.reset := reset - inst T_11804 of TileLinkEnqueuer - T_11804.manager.release.ready := UInt<1>("h00") - T_11804.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_11804.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_11804.manager.probe.bits.header.dst := UInt<1>("h00") - T_11804.manager.probe.bits.header.src := UInt<1>("h00") - T_11804.manager.probe.valid := UInt<1>("h00") - T_11804.manager.finish.ready := UInt<1>("h00") - T_11804.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_11804.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11804.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11804.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11804.manager.grant.bits.payload.data := UInt<1>("h00") - T_11804.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11804.manager.grant.bits.header.dst := UInt<1>("h00") - T_11804.manager.grant.bits.header.src := UInt<1>("h00") - T_11804.manager.grant.valid := UInt<1>("h00") - T_11804.manager.acquire.ready := UInt<1>("h00") - T_11804.client.release.bits.payload.voluntary := UInt<1>("h00") - T_11804.client.release.bits.payload.r_type := UInt<1>("h00") - T_11804.client.release.bits.payload.data := UInt<1>("h00") - T_11804.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_11804.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_11804.client.release.bits.payload.addr_block := UInt<1>("h00") - T_11804.client.release.bits.header.dst := UInt<1>("h00") - T_11804.client.release.bits.header.src := UInt<1>("h00") - T_11804.client.release.valid := UInt<1>("h00") - T_11804.client.probe.ready := UInt<1>("h00") - T_11804.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_11804.client.finish.bits.header.dst := UInt<1>("h00") - T_11804.client.finish.bits.header.src := UInt<1>("h00") - T_11804.client.finish.valid := UInt<1>("h00") - T_11804.client.grant.ready := UInt<1>("h00") - T_11804.client.acquire.bits.payload.union := UInt<1>("h00") - T_11804.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_11804.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_11804.client.acquire.bits.payload.data := UInt<1>("h00") - T_11804.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_11804.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_11804.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_11804.client.acquire.bits.header.dst := UInt<1>("h00") - T_11804.client.acquire.bits.header.src := UInt<1>("h00") - T_11804.client.acquire.valid := UInt<1>("h00") - T_11804.reset := UInt<1>("h00") - T_11804.clock := clock - T_11804.reset := reset - T_11803.client <> clients[2] - T_11804.client <> T_11803.network - inst T_11805 of ManagerTileLinkNetworkPort - T_11805.network.release.bits.payload.voluntary := UInt<1>("h00") - T_11805.network.release.bits.payload.r_type := UInt<1>("h00") - T_11805.network.release.bits.payload.data := UInt<1>("h00") - T_11805.network.release.bits.payload.addr_beat := UInt<1>("h00") - T_11805.network.release.bits.payload.client_xact_id := UInt<1>("h00") - T_11805.network.release.bits.payload.addr_block := UInt<1>("h00") - T_11805.network.release.bits.header.dst := UInt<1>("h00") - T_11805.network.release.bits.header.src := UInt<1>("h00") - T_11805.network.release.valid := UInt<1>("h00") - T_11805.network.probe.ready := UInt<1>("h00") - T_11805.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_11805.network.finish.bits.header.dst := UInt<1>("h00") - T_11805.network.finish.bits.header.src := UInt<1>("h00") - T_11805.network.finish.valid := UInt<1>("h00") - T_11805.network.grant.ready := UInt<1>("h00") - T_11805.network.acquire.bits.payload.union := UInt<1>("h00") - T_11805.network.acquire.bits.payload.a_type := UInt<1>("h00") - T_11805.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_11805.network.acquire.bits.payload.data := UInt<1>("h00") - T_11805.network.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_11805.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_11805.network.acquire.bits.payload.addr_block := UInt<1>("h00") - T_11805.network.acquire.bits.header.dst := UInt<1>("h00") - T_11805.network.acquire.bits.header.src := UInt<1>("h00") - T_11805.network.acquire.valid := UInt<1>("h00") - T_11805.manager.release.ready := UInt<1>("h00") - T_11805.manager.probe.bits.client_id := UInt<1>("h00") - T_11805.manager.probe.bits.p_type := UInt<1>("h00") - T_11805.manager.probe.bits.addr_block := UInt<1>("h00") - T_11805.manager.probe.valid := UInt<1>("h00") - T_11805.manager.finish.ready := UInt<1>("h00") - T_11805.manager.grant.bits.client_id := UInt<1>("h00") - T_11805.manager.grant.bits.g_type := UInt<1>("h00") - T_11805.manager.grant.bits.is_builtin_type := UInt<1>("h00") - T_11805.manager.grant.bits.manager_xact_id := UInt<1>("h00") - T_11805.manager.grant.bits.client_xact_id := UInt<1>("h00") - T_11805.manager.grant.bits.data := UInt<1>("h00") - T_11805.manager.grant.bits.addr_beat := UInt<1>("h00") - T_11805.manager.grant.valid := UInt<1>("h00") - T_11805.manager.acquire.ready := UInt<1>("h00") - T_11805.reset := UInt<1>("h00") - T_11805.clock := clock - T_11805.reset := reset - inst T_11806 of TileLinkEnqueuer_24 - T_11806.manager.release.ready := UInt<1>("h00") - T_11806.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_11806.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_11806.manager.probe.bits.header.dst := UInt<1>("h00") - T_11806.manager.probe.bits.header.src := UInt<1>("h00") - T_11806.manager.probe.valid := UInt<1>("h00") - T_11806.manager.finish.ready := UInt<1>("h00") - T_11806.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_11806.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_11806.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_11806.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_11806.manager.grant.bits.payload.data := UInt<1>("h00") - T_11806.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_11806.manager.grant.bits.header.dst := UInt<1>("h00") - T_11806.manager.grant.bits.header.src := UInt<1>("h00") - T_11806.manager.grant.valid := UInt<1>("h00") - T_11806.manager.acquire.ready := UInt<1>("h00") - T_11806.client.release.bits.payload.voluntary := UInt<1>("h00") - T_11806.client.release.bits.payload.r_type := UInt<1>("h00") - T_11806.client.release.bits.payload.data := UInt<1>("h00") - T_11806.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_11806.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_11806.client.release.bits.payload.addr_block := UInt<1>("h00") - T_11806.client.release.bits.header.dst := UInt<1>("h00") - T_11806.client.release.bits.header.src := UInt<1>("h00") - T_11806.client.release.valid := UInt<1>("h00") - T_11806.client.probe.ready := UInt<1>("h00") - T_11806.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_11806.client.finish.bits.header.dst := UInt<1>("h00") - T_11806.client.finish.bits.header.src := UInt<1>("h00") - T_11806.client.finish.valid := UInt<1>("h00") - T_11806.client.grant.ready := UInt<1>("h00") - T_11806.client.acquire.bits.payload.union := UInt<1>("h00") - T_11806.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_11806.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_11806.client.acquire.bits.payload.data := UInt<1>("h00") - T_11806.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_11806.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_11806.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_11806.client.acquire.bits.header.dst := UInt<1>("h00") - T_11806.client.acquire.bits.header.src := UInt<1>("h00") - T_11806.client.acquire.valid := UInt<1>("h00") - T_11806.reset := UInt<1>("h00") - T_11806.clock := clock - T_11806.reset := reset - T_11805.manager <> managers[0] - T_11805.network <> T_11806.manager - inst T_11807 of LockingRRArbiter - T_11807.out.ready := UInt<1>("h00") - T_11807.in[0].bits.payload.union := UInt<1>("h00") - T_11807.in[0].bits.payload.a_type := UInt<1>("h00") - T_11807.in[0].bits.payload.is_builtin_type := UInt<1>("h00") - T_11807.in[0].bits.payload.data := UInt<1>("h00") - T_11807.in[0].bits.payload.addr_beat := UInt<1>("h00") - T_11807.in[0].bits.payload.client_xact_id := UInt<1>("h00") - T_11807.in[0].bits.payload.addr_block := UInt<1>("h00") - T_11807.in[0].bits.header.dst := UInt<1>("h00") - T_11807.in[0].bits.header.src := UInt<1>("h00") - T_11807.in[0].valid := UInt<1>("h00") - T_11807.in[1].bits.payload.union := UInt<1>("h00") - T_11807.in[1].bits.payload.a_type := UInt<1>("h00") - T_11807.in[1].bits.payload.is_builtin_type := UInt<1>("h00") - T_11807.in[1].bits.payload.data := UInt<1>("h00") - T_11807.in[1].bits.payload.addr_beat := UInt<1>("h00") - T_11807.in[1].bits.payload.client_xact_id := UInt<1>("h00") - T_11807.in[1].bits.payload.addr_block := UInt<1>("h00") - T_11807.in[1].bits.header.dst := UInt<1>("h00") - T_11807.in[1].bits.header.src := UInt<1>("h00") - T_11807.in[1].valid := UInt<1>("h00") - T_11807.in[2].bits.payload.union := UInt<1>("h00") - T_11807.in[2].bits.payload.a_type := UInt<1>("h00") - T_11807.in[2].bits.payload.is_builtin_type := UInt<1>("h00") - T_11807.in[2].bits.payload.data := UInt<1>("h00") - T_11807.in[2].bits.payload.addr_beat := UInt<1>("h00") - T_11807.in[2].bits.payload.client_xact_id := UInt<1>("h00") - T_11807.in[2].bits.payload.addr_block := UInt<1>("h00") - T_11807.in[2].bits.header.dst := UInt<1>("h00") - T_11807.in[2].bits.header.src := UInt<1>("h00") - T_11807.in[2].valid := UInt<1>("h00") - T_11807.reset := UInt<1>("h00") - T_11807.clock := clock - T_11807.reset := reset - T_11807.in[0].valid := T_11800.manager.acquire.valid - T_11807.in[0].bits <> T_11800.manager.acquire.bits - T_11807.in[0].bits.payload.client_xact_id := T_11800.manager.acquire.bits.payload.client_xact_id - T_11800.manager.acquire.ready := T_11807.in[0].ready - T_11807.in[1].valid := T_11802.manager.acquire.valid - T_11807.in[1].bits <> T_11802.manager.acquire.bits - T_11807.in[1].bits.payload.client_xact_id := T_11802.manager.acquire.bits.payload.client_xact_id - T_11802.manager.acquire.ready := T_11807.in[1].ready - T_11807.in[2].valid := T_11804.manager.acquire.valid - T_11807.in[2].bits <> T_11804.manager.acquire.bits - T_11807.in[2].bits.payload.client_xact_id := T_11804.manager.acquire.bits.payload.client_xact_id - T_11804.manager.acquire.ready := T_11807.in[2].ready - T_11806.client.acquire <> T_11807.out - inst T_11808 of LockingRRArbiter_26 - T_11808.out.ready := UInt<1>("h00") - T_11808.in[0].bits.payload.voluntary := UInt<1>("h00") - T_11808.in[0].bits.payload.r_type := UInt<1>("h00") - T_11808.in[0].bits.payload.data := UInt<1>("h00") - T_11808.in[0].bits.payload.addr_beat := UInt<1>("h00") - T_11808.in[0].bits.payload.client_xact_id := UInt<1>("h00") - T_11808.in[0].bits.payload.addr_block := UInt<1>("h00") - T_11808.in[0].bits.header.dst := UInt<1>("h00") - T_11808.in[0].bits.header.src := UInt<1>("h00") - T_11808.in[0].valid := UInt<1>("h00") - T_11808.in[1].bits.payload.voluntary := UInt<1>("h00") - T_11808.in[1].bits.payload.r_type := UInt<1>("h00") - T_11808.in[1].bits.payload.data := UInt<1>("h00") - T_11808.in[1].bits.payload.addr_beat := UInt<1>("h00") - T_11808.in[1].bits.payload.client_xact_id := UInt<1>("h00") - T_11808.in[1].bits.payload.addr_block := UInt<1>("h00") - T_11808.in[1].bits.header.dst := UInt<1>("h00") - T_11808.in[1].bits.header.src := UInt<1>("h00") - T_11808.in[1].valid := UInt<1>("h00") - T_11808.in[2].bits.payload.voluntary := UInt<1>("h00") - T_11808.in[2].bits.payload.r_type := UInt<1>("h00") - T_11808.in[2].bits.payload.data := UInt<1>("h00") - T_11808.in[2].bits.payload.addr_beat := UInt<1>("h00") - T_11808.in[2].bits.payload.client_xact_id := UInt<1>("h00") - T_11808.in[2].bits.payload.addr_block := UInt<1>("h00") - T_11808.in[2].bits.header.dst := UInt<1>("h00") - T_11808.in[2].bits.header.src := UInt<1>("h00") - T_11808.in[2].valid := UInt<1>("h00") - T_11808.reset := UInt<1>("h00") - T_11808.clock := clock - T_11808.reset := reset - T_11808.in[0].valid := T_11800.manager.release.valid - T_11808.in[0].bits <> T_11800.manager.release.bits - T_11808.in[0].bits.payload.client_xact_id := T_11800.manager.release.bits.payload.client_xact_id - T_11800.manager.release.ready := T_11808.in[0].ready - T_11808.in[1].valid := T_11802.manager.release.valid - T_11808.in[1].bits <> T_11802.manager.release.bits - T_11808.in[1].bits.payload.client_xact_id := T_11802.manager.release.bits.payload.client_xact_id - T_11802.manager.release.ready := T_11808.in[1].ready - T_11808.in[2].valid := T_11804.manager.release.valid - T_11808.in[2].bits <> T_11804.manager.release.bits - T_11808.in[2].bits.payload.client_xact_id := T_11804.manager.release.bits.payload.client_xact_id - T_11804.manager.release.ready := T_11808.in[2].ready - T_11806.client.release <> T_11808.out - inst T_11809 of RRArbiter - T_11809.out.ready := UInt<1>("h00") - T_11809.in[0].bits.payload.manager_xact_id := UInt<1>("h00") - T_11809.in[0].bits.header.dst := UInt<1>("h00") - T_11809.in[0].bits.header.src := UInt<1>("h00") - T_11809.in[0].valid := UInt<1>("h00") - T_11809.in[1].bits.payload.manager_xact_id := UInt<1>("h00") - T_11809.in[1].bits.header.dst := UInt<1>("h00") - T_11809.in[1].bits.header.src := UInt<1>("h00") - T_11809.in[1].valid := UInt<1>("h00") - T_11809.in[2].bits.payload.manager_xact_id := UInt<1>("h00") - T_11809.in[2].bits.header.dst := UInt<1>("h00") - T_11809.in[2].bits.header.src := UInt<1>("h00") - T_11809.in[2].valid := UInt<1>("h00") - T_11809.reset := UInt<1>("h00") - T_11809.clock := clock - T_11809.reset := reset - T_11809.in[0] <> T_11800.manager.finish - T_11809.in[1] <> T_11802.manager.finish - T_11809.in[2] <> T_11804.manager.finish - T_11806.client.finish <> T_11809.out - T_11806.client.probe.ready := UInt<1>("h00") - T_11800.manager.probe.valid := UInt<1>("h00") - node T_11782 = eq(T_11806.client.probe.bits.header.dst, UInt<1>("h00")) - when T_11782 : - T_11800.manager.probe.valid := T_11806.client.probe.valid - T_11806.client.probe.ready := T_11800.manager.probe.ready - skip - T_11800.manager.probe.bits <> T_11806.client.probe.bits - T_11802.manager.probe.valid := UInt<1>("h00") - node T_11785 = eq(T_11806.client.probe.bits.header.dst, UInt<1>("h01")) - when T_11785 : - T_11802.manager.probe.valid := T_11806.client.probe.valid - T_11806.client.probe.ready := T_11802.manager.probe.ready - skip - T_11802.manager.probe.bits <> T_11806.client.probe.bits - T_11804.manager.probe.valid := UInt<1>("h00") - node T_11788 = eq(T_11806.client.probe.bits.header.dst, UInt<2>("h02")) - when T_11788 : - T_11804.manager.probe.valid := T_11806.client.probe.valid - T_11806.client.probe.ready := T_11804.manager.probe.ready - skip - T_11804.manager.probe.bits <> T_11806.client.probe.bits - T_11806.client.grant.ready := UInt<1>("h00") - T_11800.manager.grant.valid := UInt<1>("h00") - node T_11792 = eq(T_11806.client.grant.bits.header.dst, UInt<1>("h00")) - when T_11792 : - T_11800.manager.grant.valid := T_11806.client.grant.valid - T_11806.client.grant.ready := T_11800.manager.grant.ready - skip - T_11800.manager.grant.bits <> T_11806.client.grant.bits - T_11802.manager.grant.valid := UInt<1>("h00") - node T_11795 = eq(T_11806.client.grant.bits.header.dst, UInt<1>("h01")) - when T_11795 : - T_11802.manager.grant.valid := T_11806.client.grant.valid - T_11806.client.grant.ready := T_11802.manager.grant.ready - skip - T_11802.manager.grant.bits <> T_11806.client.grant.bits - T_11804.manager.grant.valid := UInt<1>("h00") - node T_11798 = eq(T_11806.client.grant.bits.header.dst, UInt<2>("h02")) - when T_11798 : - T_11804.manager.grant.valid := T_11806.client.grant.valid - T_11806.client.grant.ready := T_11804.manager.grant.ready - skip - T_11804.manager.grant.bits <> T_11806.client.grant.bits - - module BroadcastVoluntaryReleaseTracker : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - reg collect_irel_data : UInt<1>, clock, reset - onreset collect_irel_data := UInt<1>("h00") - reg irel_data_valid : UInt<4>, clock, reset - onreset irel_data_valid := UInt<4>("h00") - node T_1091 = and(inner.release.ready, inner.release.valid) - wire T_1095 : UInt<2>[3] - T_1095[0] := UInt<1>("h00") - T_1095[1] := UInt<1>("h01") - T_1095[2] := UInt<2>("h02") - node T_1100 = eq(T_1095[0], inner.release.bits.r_type) - node T_1101 = eq(T_1095[1], inner.release.bits.r_type) - node T_1102 = eq(T_1095[2], inner.release.bits.r_type) - node T_1104 = or(UInt<1>("h00"), T_1100) - node T_1105 = or(T_1104, T_1101) - node T_1106 = or(T_1105, T_1102) - node T_1107 = and(UInt<1>("h01"), T_1106) - node T_1108 = and(T_1091, T_1107) - reg T_1110 : UInt<2>, clock, reset - onreset T_1110 := UInt<2>("h00") - when T_1108 : - node T_1112 = eq(T_1110, UInt<2>("h03")) - node T_1114 = and(UInt<1>("h00"), T_1112) - node T_1117 = addw(T_1110, UInt<1>("h01")) - node T_1118 = mux(T_1114, UInt<1>("h00"), T_1117) - T_1110 := T_1118 - skip - node T_1119 = and(T_1108, T_1112) - node T_1120 = mux(T_1107, T_1110, UInt<1>("h00")) - node irel_data_done = mux(T_1107, T_1119, T_1091) - node T_1123 = and(outer.acquire.ready, outer.acquire.valid) - node T_1125 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1128 : UInt<3>[1] - T_1128[0] := UInt<3>("h03") - node T_1131 = eq(T_1128[0], outer.acquire.bits.a_type) - node T_1133 = or(UInt<1>("h00"), T_1131) - node T_1134 = and(T_1125, T_1133) - node T_1135 = and(T_1123, T_1134) - reg T_1137 : UInt<2>, clock, reset - onreset T_1137 := UInt<2>("h00") - when T_1135 : - node T_1139 = eq(T_1137, UInt<2>("h03")) - node T_1141 = and(UInt<1>("h00"), T_1139) - node T_1144 = addw(T_1137, UInt<1>("h01")) - node T_1145 = mux(T_1141, UInt<1>("h00"), T_1144) - T_1137 := T_1145 - skip - node T_1146 = and(T_1135, T_1139) - node oacq_data_cnt = mux(T_1134, T_1137, UInt<1>("h00")) - node oacq_data_done = mux(T_1134, T_1146, T_1123) - has_acquire_conflict := UInt<1>("h00") - has_release_match := inner.release.bits.voluntary - has_acquire_match := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - wire T_1194 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1194.client_id := UInt<1>("h00") - T_1194.g_type := UInt<1>("h00") - T_1194.is_builtin_type := UInt<1>("h00") - T_1194.manager_xact_id := UInt<1>("h00") - T_1194.client_xact_id := UInt<1>("h00") - T_1194.data := UInt<1>("h00") - T_1194.addr_beat := UInt<1>("h00") - T_1194.client_id := xact.client_id - T_1194.is_builtin_type := UInt<1>("h01") - T_1194.g_type := UInt<3>("h00") - T_1194.client_xact_id := xact.client_xact_id - T_1194.manager_xact_id := UInt<1>("h00") - T_1194.addr_beat := UInt<1>("h00") - T_1194.data := UInt<1>("h00") - inner.grant.bits <> T_1194 - infer accessor T_1233 = data_buffer[oacq_data_cnt] - node T_1266 = asUInt(asSInt(UInt<1>("h01"))) - node T_1267 = cat(T_1266, UInt<1>("h01")) - wire T_1296 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - T_1296.union := UInt<1>("h00") - T_1296.a_type := UInt<1>("h00") - T_1296.is_builtin_type := UInt<1>("h00") - T_1296.data := UInt<1>("h00") - T_1296.addr_beat := UInt<1>("h00") - T_1296.client_xact_id := UInt<1>("h00") - T_1296.addr_block := UInt<1>("h00") - T_1296.is_builtin_type := UInt<1>("h01") - T_1296.a_type := UInt<3>("h03") - T_1296.client_xact_id := UInt<1>("h00") - T_1296.addr_block := xact.addr_block - T_1296.addr_beat := oacq_data_cnt - T_1296.data := T_1233 - T_1296.union := T_1267 - outer.acquire.bits <> T_1296 - when collect_irel_data : - inner.release.ready := UInt<1>("h01") - when inner.release.valid : - infer accessor T_1332 = data_buffer[inner.release.bits.addr_beat] - T_1332 := inner.release.bits.data - node T_1335 = dshl(UInt<1>("h01"), inner.release.bits.addr_beat) - node T_1336 = or(irel_data_valid, T_1335) - node T_1337 = not(irel_data_valid) - node T_1338 = or(T_1337, T_1335) - node T_1339 = not(T_1338) - node T_1340 = mux(UInt<1>("h01"), T_1336, T_1339) - irel_data_valid := T_1340 - skip - when irel_data_done : - collect_irel_data := UInt<1>("h00") - skip - skip - node T_1342 = eq(UInt<1>("h00"), state) - when T_1342 : - inner.release.ready := UInt<1>("h01") - when inner.release.valid : - xact <> inner.release.bits - infer accessor T_1345 = data_buffer[UInt<1>("h00")] - T_1345 := inner.release.bits.data - wire T_1348 : UInt<2>[3] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - T_1348[2] := UInt<2>("h02") - node T_1353 = eq(T_1348[0], inner.release.bits.r_type) - node T_1354 = eq(T_1348[1], inner.release.bits.r_type) - node T_1355 = eq(T_1348[2], inner.release.bits.r_type) - node T_1357 = or(UInt<1>("h00"), T_1353) - node T_1358 = or(T_1357, T_1354) - node T_1359 = or(T_1358, T_1355) - node T_1360 = and(UInt<1>("h01"), T_1359) - collect_irel_data := T_1360 - wire T_1362 : UInt<2>[3] - T_1362[0] := UInt<1>("h00") - T_1362[1] := UInt<1>("h01") - T_1362[2] := UInt<2>("h02") - node T_1367 = eq(T_1362[0], inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - node T_1374 = dshl(T_1373, inner.release.bits.addr_beat) - irel_data_valid := T_1374 - wire T_1376 : UInt<2>[3] - T_1376[0] := UInt<1>("h00") - T_1376[1] := UInt<1>("h01") - T_1376[2] := UInt<2>("h02") - node T_1381 = eq(T_1376[0], inner.release.bits.r_type) - node T_1382 = eq(T_1376[1], inner.release.bits.r_type) - node T_1383 = eq(T_1376[2], inner.release.bits.r_type) - node T_1385 = or(UInt<1>("h00"), T_1381) - node T_1386 = or(T_1385, T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1390 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1391 = mux(T_1390, UInt<2>("h03"), UInt<1>("h00")) - node T_1392 = mux(T_1387, UInt<1>("h01"), T_1391) - state := T_1392 - skip - skip - node T_1393 = eq(UInt<1>("h01"), state) - when T_1393 : - node T_1395 = eq(collect_irel_data, UInt<1>("h00")) - node T_1396 = dshr(irel_data_valid, oacq_data_cnt) - node T_1397 = bit(T_1396, 0) - node T_1398 = or(T_1395, T_1397) - outer.acquire.valid := T_1398 - when oacq_data_done : - state := UInt<2>("h02") - skip - skip - node T_1399 = eq(UInt<2>("h02"), state) - when T_1399 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - node T_1400 = and(inner.grant.ready, inner.grant.valid) - when T_1400 : - node T_1403 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1405 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_1406 = and(inner.grant.bits.is_builtin_type, T_1405) - node T_1408 = eq(T_1406, UInt<1>("h00")) - node T_1409 = and(T_1403, T_1408) - node T_1410 = mux(T_1409, UInt<2>("h03"), UInt<1>("h00")) - state := T_1410 - skip - skip - node T_1411 = eq(UInt<2>("h03"), state) - when T_1411 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<1>("h01") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<1>("h01") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<1>("h01") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<1>("h01") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<1>("h01") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_27 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<2>("h02") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<2>("h02") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<2>("h02") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<2>("h02") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<2>("h02") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_28 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<2>("h03") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<2>("h03") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<2>("h03") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<2>("h03") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<2>("h03") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_29 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<3>("h04") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<3>("h04") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<3>("h04") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<3>("h04") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<3>("h04") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_30 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<3>("h05") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<3>("h05") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<3>("h05") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<3>("h05") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<3>("h05") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_31 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<3>("h06") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<3>("h06") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<3>("h06") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<3>("h06") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<3>("h06") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module BroadcastAcquireTracker_32 : - output has_release_match : UInt<1> - output has_acquire_match : UInt<1> - output has_acquire_conflict : UInt<1> - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - has_release_match := UInt<1>("h00") - has_acquire_match := UInt<1>("h00") - has_acquire_conflict := UInt<1>("h00") - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset - reg data_buffer : UInt<4>[4], clock, reset - wire coh : {sharers : UInt<1>} - coh.sharers := UInt<1>("h00") - coh.sharers := UInt<1>("h00") - node T_1092 = neq(state, UInt<1>("h00")) - node T_1093 = and(T_1092, xact.is_builtin_type) - wire T_1099 : UInt<3>[4] - T_1099[0] := UInt<3>("h00") - T_1099[1] := UInt<3>("h02") - T_1099[2] := UInt<3>("h04") - T_1099[3] := UInt<3>("h05") - node T_1105 = eq(T_1099[0], xact.a_type) - node T_1106 = eq(T_1099[1], xact.a_type) - node T_1107 = eq(T_1099[2], xact.a_type) - node T_1108 = eq(T_1099[3], xact.a_type) - node T_1110 = or(UInt<1>("h00"), T_1105) - node T_1111 = or(T_1110, T_1106) - node T_1112 = or(T_1111, T_1107) - node T_1113 = or(T_1112, T_1108) - node T_1114 = and(T_1093, T_1113) - node T_1116 = eq(T_1114, UInt<1>("h00")) - reg release_count : UInt<1>, clock, reset - onreset release_count := UInt<1>("h00") - reg pending_probes : UInt<1>, clock, reset - onreset pending_probes := UInt<1>("h00") - node T_1121 = bit(pending_probes, 0) - wire T_1123 : UInt<1>[1] - T_1123[0] := T_1121 - node T_1128 = asUInt(asSInt(UInt<1>("h01"))) - node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) - node T_1132 = or(T_1128, T_1131) - node T_1133 = not(T_1128) - node T_1134 = or(T_1133, T_1131) - node T_1135 = not(T_1134) - node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) - node T_1137 = not(incoherent[0]) - node mask_incoherent = and(mask_self, T_1137) - reg collect_iacq_data : UInt<1>, clock, reset - onreset collect_iacq_data := UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clock, reset - onreset iacq_data_valid := UInt<4>("h00") - node T_1143 = and(inner.acquire.ready, inner.acquire.valid) - node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_1149 : UInt<3>[1] - T_1149[0] := UInt<3>("h03") - node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) - node T_1154 = or(UInt<1>("h00"), T_1152) - node T_1155 = and(T_1146, T_1154) - node T_1156 = and(T_1143, T_1155) - reg T_1158 : UInt<2>, clock, reset - onreset T_1158 := UInt<2>("h00") - when T_1156 : - node T_1160 = eq(T_1158, UInt<2>("h03")) - node T_1162 = and(UInt<1>("h00"), T_1160) - node T_1165 = addw(T_1158, UInt<1>("h01")) - node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) - T_1158 := T_1166 - skip - node T_1167 = and(T_1156, T_1160) - node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) - node iacq_data_done = mux(T_1155, T_1167, T_1143) - node T_1170 = and(inner.release.ready, inner.release.valid) - wire T_1174 : UInt<2>[3] - T_1174[0] := UInt<1>("h00") - T_1174[1] := UInt<1>("h01") - T_1174[2] := UInt<2>("h02") - node T_1179 = eq(T_1174[0], inner.release.bits.r_type) - node T_1180 = eq(T_1174[1], inner.release.bits.r_type) - node T_1181 = eq(T_1174[2], inner.release.bits.r_type) - node T_1183 = or(UInt<1>("h00"), T_1179) - node T_1184 = or(T_1183, T_1180) - node T_1185 = or(T_1184, T_1181) - node T_1186 = and(UInt<1>("h01"), T_1185) - node T_1187 = and(T_1170, T_1186) - reg T_1189 : UInt<2>, clock, reset - onreset T_1189 := UInt<2>("h00") - when T_1187 : - node T_1191 = eq(T_1189, UInt<2>("h03")) - node T_1193 = and(UInt<1>("h00"), T_1191) - node T_1196 = addw(T_1189, UInt<1>("h01")) - node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) - T_1189 := T_1197 - skip - node T_1198 = and(T_1187, T_1191) - node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) - node irel_data_done = mux(T_1186, T_1198, T_1170) - node T_1202 = and(inner.grant.ready, inner.grant.valid) - wire T_1206 : UInt<3>[1] - T_1206[0] := UInt<3>("h05") - node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) - node T_1211 = or(UInt<1>("h00"), T_1209) - wire T_1213 : UInt<1>[2] - T_1213[0] := UInt<1>("h00") - T_1213[1] := UInt<1>("h01") - node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) - node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) - node T_1220 = or(UInt<1>("h00"), T_1217) - node T_1221 = or(T_1220, T_1218) - node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) - node T_1223 = and(UInt<1>("h01"), T_1222) - node T_1224 = and(T_1202, T_1223) - reg T_1226 : UInt<2>, clock, reset - onreset T_1226 := UInt<2>("h00") - when T_1224 : - node T_1228 = eq(T_1226, UInt<2>("h03")) - node T_1230 = and(UInt<1>("h00"), T_1228) - node T_1233 = addw(T_1226, UInt<1>("h01")) - node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) - T_1226 := T_1234 - skip - node T_1235 = and(T_1224, T_1228) - node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) - node ignt_data_done = mux(T_1223, T_1235, T_1202) - node T_1239 = and(outer.acquire.ready, outer.acquire.valid) - node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) - wire T_1244 : UInt<3>[1] - T_1244[0] := UInt<3>("h03") - node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) - node T_1249 = or(UInt<1>("h00"), T_1247) - node T_1250 = and(T_1241, T_1249) - node T_1251 = and(T_1239, T_1250) - reg T_1253 : UInt<2>, clock, reset - onreset T_1253 := UInt<2>("h00") - when T_1251 : - node T_1255 = eq(T_1253, UInt<2>("h03")) - node T_1257 = and(UInt<1>("h00"), T_1255) - node T_1260 = addw(T_1253, UInt<1>("h01")) - node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) - T_1253 := T_1261 - skip - node T_1262 = and(T_1251, T_1255) - node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) - node oacq_data_done = mux(T_1250, T_1262, T_1239) - node T_1265 = and(outer.grant.ready, outer.grant.valid) - wire T_1270 : UInt<3>[1] - T_1270[0] := UInt<3>("h05") - node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) - node T_1275 = or(UInt<1>("h00"), T_1273) - wire T_1277 : UInt<1>[1] - T_1277[0] := UInt<1>("h00") - node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) - node T_1282 = or(UInt<1>("h00"), T_1280) - node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) - node T_1284 = and(UInt<1>("h01"), T_1283) - node T_1285 = and(T_1265, T_1284) - reg T_1287 : UInt<2>, clock, reset - onreset T_1287 := UInt<2>("h00") - when T_1285 : - node T_1289 = eq(T_1287, UInt<2>("h03")) - node T_1291 = and(UInt<1>("h00"), T_1289) - node T_1294 = addw(T_1287, UInt<1>("h01")) - node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) - T_1287 := T_1295 - skip - node T_1296 = and(T_1285, T_1289) - node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) - node ognt_data_done = mux(T_1284, T_1296, T_1265) - reg pending_ognt_ack : UInt<1>, clock, reset - onreset pending_ognt_ack := UInt<1>("h00") - wire T_1305 : UInt<3>[3] - T_1305[0] := UInt<3>("h02") - T_1305[1] := UInt<3>("h03") - T_1305[2] := UInt<3>("h04") - node T_1310 = eq(T_1305[0], xact.a_type) - node T_1311 = eq(T_1305[1], xact.a_type) - node T_1312 = eq(T_1305[2], xact.a_type) - node T_1314 = or(UInt<1>("h00"), T_1310) - node T_1315 = or(T_1314, T_1311) - node T_1316 = or(T_1315, T_1312) - node pending_outer_write = and(xact.is_builtin_type, T_1316) - wire T_1322 : UInt<3>[3] - T_1322[0] := UInt<3>("h02") - T_1322[1] := UInt<3>("h03") - T_1322[2] := UInt<3>("h04") - node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) - node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) - node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) - node T_1331 = or(UInt<1>("h00"), T_1327) - node T_1332 = or(T_1331, T_1328) - node T_1333 = or(T_1332, T_1329) - node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) - wire T_1338 : UInt<3>[2] - T_1338[0] := UInt<3>("h05") - T_1338[1] := UInt<3>("h04") - node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) - node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) - node T_1345 = or(UInt<1>("h00"), T_1342) - node T_1346 = or(T_1345, T_1343) - wire T_1348 : UInt<1>[2] - T_1348[0] := UInt<1>("h00") - T_1348[1] := UInt<1>("h01") - node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) - node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) - node T_1355 = or(UInt<1>("h00"), T_1352) - node T_1356 = or(T_1355, T_1353) - node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) - node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) - node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) - node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) - node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) - node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) - node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) - node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) - node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) - node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) - node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) - node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) - node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) - node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) - node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) - node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) - wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1424.client_id := UInt<1>("h00") - T_1424.g_type := UInt<1>("h00") - T_1424.is_builtin_type := UInt<1>("h00") - T_1424.manager_xact_id := UInt<1>("h00") - T_1424.client_xact_id := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - T_1424.addr_beat := UInt<1>("h00") - T_1424.client_id := inner.acquire.bits.client_id - T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type - T_1424.g_type := T_1392 - T_1424.client_xact_id := inner.acquire.bits.client_xact_id - T_1424.manager_xact_id := UInt<3>("h07") - T_1424.addr_beat := UInt<1>("h00") - T_1424.data := UInt<1>("h00") - wire T_1465 : UInt<3>[2] - T_1465[0] := UInt<3>("h05") - T_1465[1] := UInt<3>("h04") - node T_1469 = eq(T_1465[0], T_1424.g_type) - node T_1470 = eq(T_1465[1], T_1424.g_type) - node T_1472 = or(UInt<1>("h00"), T_1469) - node T_1473 = or(T_1472, T_1470) - wire T_1475 : UInt<1>[2] - T_1475[0] := UInt<1>("h00") - T_1475[1] := UInt<1>("h01") - node T_1479 = eq(T_1475[0], T_1424.g_type) - node T_1480 = eq(T_1475[1], T_1424.g_type) - node T_1482 = or(UInt<1>("h00"), T_1479) - node T_1483 = or(T_1482, T_1480) - node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) - node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1486 = neq(state, UInt<1>("h00")) - node T_1487 = and(T_1485, T_1486) - node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1490 = and(T_1487, T_1489) - has_acquire_conflict := T_1490 - node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) - node T_1492 = and(T_1491, collect_iacq_data) - has_acquire_match := T_1492 - node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) - node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) - node T_1496 = and(T_1493, T_1495) - node T_1497 = eq(state, UInt<1>("h01")) - node T_1498 = and(T_1496, T_1497) - has_release_match := T_1498 - infer accessor T_1500 = data_buffer[oacq_data_cnt] - node T_1533 = asUInt(asSInt(UInt<1>("h01"))) - node T_1534 = cat(T_1533, UInt<1>("h01")) - wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_acq.union := UInt<1>("h00") - outer_write_acq.a_type := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h00") - outer_write_acq.data := UInt<1>("h00") - outer_write_acq.addr_beat := UInt<1>("h00") - outer_write_acq.client_xact_id := UInt<1>("h00") - outer_write_acq.addr_block := UInt<1>("h00") - outer_write_acq.is_builtin_type := UInt<1>("h01") - outer_write_acq.a_type := UInt<3>("h03") - outer_write_acq.client_xact_id := UInt<3>("h07") - outer_write_acq.addr_block := xact.addr_block - outer_write_acq.addr_beat := oacq_data_cnt - outer_write_acq.data := T_1500 - outer_write_acq.union := T_1534 - node T_1631 = asUInt(asSInt(UInt<1>("h01"))) - node T_1632 = cat(T_1631, UInt<1>("h01")) - wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_write_rel.union := UInt<1>("h00") - outer_write_rel.a_type := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h00") - outer_write_rel.data := UInt<1>("h00") - outer_write_rel.addr_beat := UInt<1>("h00") - outer_write_rel.client_xact_id := UInt<1>("h00") - outer_write_rel.addr_block := UInt<1>("h00") - outer_write_rel.is_builtin_type := UInt<1>("h01") - outer_write_rel.a_type := UInt<3>("h03") - outer_write_rel.client_xact_id := UInt<3>("h07") - outer_write_rel.addr_block := xact.addr_block - outer_write_rel.addr_beat := inner.release.bits.addr_beat - outer_write_rel.data := inner.release.bits.data - outer_write_rel.union := T_1632 - node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1701 = cat(UInt<3>("h07"), T_1700) - wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} - outer_read.union := UInt<1>("h00") - outer_read.a_type := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.addr_beat := UInt<1>("h00") - outer_read.client_xact_id := UInt<1>("h00") - outer_read.addr_block := UInt<1>("h00") - outer_read.is_builtin_type := UInt<1>("h01") - outer_read.a_type := UInt<3>("h01") - outer_read.client_xact_id := UInt<3>("h07") - outer_read.addr_block := xact.addr_block - outer_read.addr_beat := UInt<1>("h00") - outer_read.data := UInt<1>("h00") - outer_read.union := T_1701 - outer.acquire.valid := UInt<1>("h00") - outer.acquire.bits <> outer_read - outer.grant.ready := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - node T_1775 = eq(UInt<3>("h04"), xact.a_type) - node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) - node T_1777 = eq(UInt<3>("h02"), xact.a_type) - node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) - node T_1779 = eq(UInt<3>("h00"), xact.a_type) - node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) - node T_1781 = eq(UInt<3>("h03"), xact.a_type) - node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) - node T_1783 = eq(UInt<3>("h01"), xact.a_type) - node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) - node T_1785 = eq(UInt<1>("h01"), xact.a_type) - node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) - node T_1787 = eq(UInt<1>("h00"), xact.a_type) - node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) - node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) - wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := UInt<1>("h00") - T_1817.addr_block := UInt<1>("h00") - T_1817.client_id := UInt<1>("h00") - T_1817.p_type := T_1789 - T_1817.addr_block := xact.addr_block - inner.probe.bits <> T_1817 - inner.grant.valid := UInt<1>("h00") - node T_1864 = eq(UInt<3>("h05"), xact.a_type) - node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) - node T_1866 = eq(UInt<3>("h04"), xact.a_type) - node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) - node T_1868 = eq(UInt<3>("h03"), xact.a_type) - node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) - node T_1870 = eq(UInt<3>("h02"), xact.a_type) - node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) - node T_1872 = eq(UInt<3>("h01"), xact.a_type) - node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) - node T_1874 = eq(UInt<3>("h00"), xact.a_type) - node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) - node T_1876 = eq(xact.a_type, UInt<1>("h00")) - node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) - node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) - node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) - wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} - T_1914.client_id := UInt<1>("h00") - T_1914.g_type := UInt<1>("h00") - T_1914.is_builtin_type := UInt<1>("h00") - T_1914.manager_xact_id := UInt<1>("h00") - T_1914.client_xact_id := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - T_1914.addr_beat := UInt<1>("h00") - T_1914.client_id := xact.client_id - T_1914.is_builtin_type := xact.is_builtin_type - T_1914.g_type := T_1882 - T_1914.client_xact_id := xact.client_xact_id - T_1914.manager_xact_id := UInt<3>("h07") - T_1914.addr_beat := UInt<1>("h00") - T_1914.data := UInt<1>("h00") - inner.grant.bits <> T_1914 - inner.acquire.ready := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - node T_1955 = neq(state, UInt<1>("h00")) - node T_1956 = and(T_1955, collect_iacq_data) - node T_1957 = and(inner.acquire.ready, inner.acquire.valid) - node T_1958 = and(T_1956, T_1957) - node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) - node T_1960 = and(T_1958, T_1959) - node T_1962 = eq(T_1960, UInt<1>("h00")) - node T_1963 = neq(state, UInt<1>("h00")) - node T_1964 = and(T_1963, collect_iacq_data) - node T_1965 = and(inner.acquire.ready, inner.acquire.valid) - node T_1966 = and(T_1964, T_1965) - node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1968 = and(T_1966, T_1967) - node T_1970 = eq(T_1968, UInt<1>("h00")) - node T_1971 = eq(state, UInt<1>("h00")) - node T_1972 = and(inner.acquire.ready, inner.acquire.valid) - node T_1973 = and(T_1971, T_1972) - node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1978 = eq(T_1976, UInt<1>("h00")) - when collect_iacq_data : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] - T_1980 := inner.acquire.bits.data - node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) - node T_1984 = or(iacq_data_valid, T_1983) - node T_1985 = not(iacq_data_valid) - node T_1986 = or(T_1985, T_1983) - node T_1987 = not(T_1986) - node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) - iacq_data_valid := T_1988 - skip - when iacq_data_done : - collect_iacq_data := UInt<1>("h00") - skip - skip - when pending_ognt_ack : - outer.grant.ready := UInt<1>("h01") - when outer.grant.valid : - pending_ognt_ack := UInt<1>("h00") - skip - skip - node T_1992 = eq(UInt<1>("h00"), state) - when T_1992 : - inner.acquire.ready := UInt<1>("h01") - when inner.acquire.valid : - xact <> inner.acquire.bits - infer accessor T_1995 = data_buffer[UInt<1>("h00")] - T_1995 := inner.acquire.bits.data - node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) - wire T_2000 : UInt<3>[1] - T_2000[0] := UInt<3>("h03") - node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) - node T_2005 = or(UInt<1>("h00"), T_2003) - node T_2006 = and(T_1997, T_2005) - collect_iacq_data := T_2006 - wire T_2011 : UInt<3>[3] - T_2011[0] := UInt<3>("h02") - T_2011[1] := UInt<3>("h03") - T_2011[2] := UInt<3>("h04") - node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) - node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) - node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) - node T_2020 = or(UInt<1>("h00"), T_2016) - node T_2021 = or(T_2020, T_2017) - node T_2022 = or(T_2021, T_2018) - node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) - node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) - iacq_data_valid := T_2024 - node T_2026 = neq(mask_incoherent, UInt<1>("h00")) - when T_2026 : - pending_probes := mask_incoherent - node T_2027 = bit(mask_incoherent, 0) - node T_2028 = bit(mask_incoherent, 1) - node T_2029 = bit(mask_incoherent, 2) - node T_2030 = bit(mask_incoherent, 3) - node T_2032 = cat(UInt<1>("h00"), T_2028) - node T_2033 = addw(T_2027, T_2032) - node T_2036 = cat(UInt<1>("h00"), T_2030) - node T_2037 = addw(T_2029, T_2036) - node T_2038 = cat(UInt<1>("h00"), T_2037) - node T_2039 = addw(T_2033, T_2038) - release_count := T_2039 - skip - node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) - node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) - state := T_2042 - skip - skip - node T_2043 = eq(UInt<1>("h01"), state) - when T_2043 : - node T_2045 = neq(pending_probes, UInt<1>("h00")) - inner.probe.valid := T_2045 - when inner.probe.ready : - node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_2048 = not(T_2047) - node T_2049 = and(pending_probes, T_2048) - pending_probes := T_2049 - skip - wire T_2051 : UInt<2>[3] - T_2051[0] := UInt<1>("h00") - T_2051[1] := UInt<1>("h01") - T_2051[2] := UInt<2>("h02") - node T_2056 = eq(T_2051[0], inner.release.bits.r_type) - node T_2057 = eq(T_2051[1], inner.release.bits.r_type) - node T_2058 = eq(T_2051[2], inner.release.bits.r_type) - node T_2060 = or(UInt<1>("h00"), T_2056) - node T_2061 = or(T_2060, T_2057) - node T_2062 = or(T_2061, T_2058) - node T_2064 = eq(T_2062, UInt<1>("h00")) - node T_2065 = or(T_2064, outer.acquire.ready) - inner.release.ready := T_2065 - when inner.release.valid : - wire T_2067 : UInt<2>[3] - T_2067[0] := UInt<1>("h00") - T_2067[1] := UInt<1>("h01") - T_2067[2] := UInt<2>("h02") - node T_2072 = eq(T_2067[0], inner.release.bits.r_type) - node T_2073 = eq(T_2067[1], inner.release.bits.r_type) - node T_2074 = eq(T_2067[2], inner.release.bits.r_type) - node T_2076 = or(UInt<1>("h00"), T_2072) - node T_2077 = or(T_2076, T_2073) - node T_2078 = or(T_2077, T_2074) - when T_2078 : - outer.acquire.valid := UInt<1>("h01") - outer.acquire.bits <> outer_write_rel - when outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2082 = subw(release_count, UInt<1>("h01")) - release_count := T_2082 - node T_2084 = eq(release_count, UInt<1>("h01")) - when T_2084 : - node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) - state := T_2086 - skip - skip - skip - skip - else : - node T_2088 = subw(release_count, UInt<1>("h01")) - release_count := T_2088 - node T_2090 = eq(release_count, UInt<1>("h01")) - when T_2090 : - node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) - state := T_2092 - skip - skip - skip - skip - node T_2093 = eq(UInt<2>("h03"), state) - when T_2093 : - node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) - node T_2098 = or(T_2095, T_2097) - node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) - node T_2100 = bit(T_2099, 0) - node T_2101 = or(T_2098, T_2100) - outer.acquire.valid := T_2101 - outer.acquire.bits <> outer_write_acq - when oacq_data_done : - pending_ognt_ack := UInt<1>("h01") - node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state := T_2103 - skip - skip - node T_2104 = eq(UInt<2>("h02"), state) - when T_2104 : - node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) - outer.acquire.valid := T_2106 - outer.acquire.bits <> outer_read - node T_2107 = and(outer.acquire.ready, outer.acquire.valid) - when T_2107 : - state := UInt<3>("h05") - skip - skip - node T_2108 = eq(UInt<3>("h05"), state) - when T_2108 : - outer.grant.ready := inner.grant.ready - inner.grant.valid := outer.grant.valid - when ignt_data_done : - node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) - node T_2116 = eq(T_2114, UInt<1>("h00")) - node T_2117 = and(T_2111, T_2116) - node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) - state := T_2118 - skip - skip - node T_2119 = eq(UInt<3>("h04"), state) - when T_2119 : - inner.grant.valid := UInt<1>("h01") - when inner.grant.ready : - node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) - node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) - node T_2128 = eq(T_2126, UInt<1>("h00")) - node T_2129 = and(T_2123, T_2128) - node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) - state := T_2130 - skip - skip - node T_2131 = eq(UInt<3>("h06"), state) - when T_2131 : - inner.finish.ready := UInt<1>("h01") - when inner.finish.valid : - state := UInt<1>("h00") - skip - skip - - module LockingRRArbiter_33 : - output chosen : UInt<3> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}[8] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.client_id := UInt<1>("h00") - out.bits.g_type := UInt<1>("h00") - out.bits.is_builtin_type := UInt<1>("h00") - out.bits.manager_xact_id := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - in[3].ready := UInt<1>("h00") - in[4].ready := UInt<1>("h00") - in[5].ready := UInt<1>("h00") - in[6].ready := UInt<1>("h00") - in[7].ready := UInt<1>("h00") - reg T_1502 : UInt<1>, clock, reset - onreset T_1502 := UInt<1>("h00") - reg T_1504 : UInt, clock, reset - onreset T_1504 := UInt<3>("h07") - wire T_1506 : UInt<3> - T_1506 := UInt<1>("h00") - infer accessor T_1508 = in[T_1506] - out.valid := T_1508.valid - infer accessor T_1573 = in[T_1506] - out.bits <> T_1573.bits - chosen := T_1506 - infer accessor T_1638 = in[T_1506] - T_1638.ready := UInt<1>("h00") - reg last_grant : UInt<3>, clock, reset - onreset last_grant := UInt<3>("h00") - node T_1707 = gt(UInt<1>("h00"), last_grant) - node T_1708 = and(in[0].valid, T_1707) - node T_1710 = gt(UInt<1>("h01"), last_grant) - node T_1711 = and(in[1].valid, T_1710) - node T_1713 = gt(UInt<2>("h02"), last_grant) - node T_1714 = and(in[2].valid, T_1713) - node T_1716 = gt(UInt<2>("h03"), last_grant) - node T_1717 = and(in[3].valid, T_1716) - node T_1719 = gt(UInt<3>("h04"), last_grant) - node T_1720 = and(in[4].valid, T_1719) - node T_1722 = gt(UInt<3>("h05"), last_grant) - node T_1723 = and(in[5].valid, T_1722) - node T_1725 = gt(UInt<3>("h06"), last_grant) - node T_1726 = and(in[6].valid, T_1725) - node T_1728 = gt(UInt<3>("h07"), last_grant) - node T_1729 = and(in[7].valid, T_1728) - node T_1732 = or(UInt<1>("h00"), T_1708) - node T_1734 = eq(T_1732, UInt<1>("h00")) - node T_1736 = or(UInt<1>("h00"), T_1708) - node T_1737 = or(T_1736, T_1711) - node T_1739 = eq(T_1737, UInt<1>("h00")) - node T_1741 = or(UInt<1>("h00"), T_1708) - node T_1742 = or(T_1741, T_1711) - node T_1743 = or(T_1742, T_1714) - node T_1745 = eq(T_1743, UInt<1>("h00")) - node T_1747 = or(UInt<1>("h00"), T_1708) - node T_1748 = or(T_1747, T_1711) - node T_1749 = or(T_1748, T_1714) - node T_1750 = or(T_1749, T_1717) - node T_1752 = eq(T_1750, UInt<1>("h00")) - node T_1754 = or(UInt<1>("h00"), T_1708) - node T_1755 = or(T_1754, T_1711) - node T_1756 = or(T_1755, T_1714) - node T_1757 = or(T_1756, T_1717) - node T_1758 = or(T_1757, T_1720) - node T_1760 = eq(T_1758, UInt<1>("h00")) - node T_1762 = or(UInt<1>("h00"), T_1708) - node T_1763 = or(T_1762, T_1711) - node T_1764 = or(T_1763, T_1714) - node T_1765 = or(T_1764, T_1717) - node T_1766 = or(T_1765, T_1720) - node T_1767 = or(T_1766, T_1723) - node T_1769 = eq(T_1767, UInt<1>("h00")) - node T_1771 = or(UInt<1>("h00"), T_1708) - node T_1772 = or(T_1771, T_1711) - node T_1773 = or(T_1772, T_1714) - node T_1774 = or(T_1773, T_1717) - node T_1775 = or(T_1774, T_1720) - node T_1776 = or(T_1775, T_1723) - node T_1777 = or(T_1776, T_1726) - node T_1779 = eq(T_1777, UInt<1>("h00")) - node T_1781 = or(UInt<1>("h00"), T_1708) - node T_1782 = or(T_1781, T_1711) - node T_1783 = or(T_1782, T_1714) - node T_1784 = or(T_1783, T_1717) - node T_1785 = or(T_1784, T_1720) - node T_1786 = or(T_1785, T_1723) - node T_1787 = or(T_1786, T_1726) - node T_1788 = or(T_1787, T_1729) - node T_1790 = eq(T_1788, UInt<1>("h00")) - node T_1792 = or(UInt<1>("h00"), T_1708) - node T_1793 = or(T_1792, T_1711) - node T_1794 = or(T_1793, T_1714) - node T_1795 = or(T_1794, T_1717) - node T_1796 = or(T_1795, T_1720) - node T_1797 = or(T_1796, T_1723) - node T_1798 = or(T_1797, T_1726) - node T_1799 = or(T_1798, T_1729) - node T_1800 = or(T_1799, in[0].valid) - node T_1802 = eq(T_1800, UInt<1>("h00")) - node T_1804 = or(UInt<1>("h00"), T_1708) - node T_1805 = or(T_1804, T_1711) - node T_1806 = or(T_1805, T_1714) - node T_1807 = or(T_1806, T_1717) - node T_1808 = or(T_1807, T_1720) - node T_1809 = or(T_1808, T_1723) - node T_1810 = or(T_1809, T_1726) - node T_1811 = or(T_1810, T_1729) - node T_1812 = or(T_1811, in[0].valid) - node T_1813 = or(T_1812, in[1].valid) - node T_1815 = eq(T_1813, UInt<1>("h00")) - node T_1817 = or(UInt<1>("h00"), T_1708) - node T_1818 = or(T_1817, T_1711) - node T_1819 = or(T_1818, T_1714) - node T_1820 = or(T_1819, T_1717) - node T_1821 = or(T_1820, T_1720) - node T_1822 = or(T_1821, T_1723) - node T_1823 = or(T_1822, T_1726) - node T_1824 = or(T_1823, T_1729) - node T_1825 = or(T_1824, in[0].valid) - node T_1826 = or(T_1825, in[1].valid) - node T_1827 = or(T_1826, in[2].valid) - node T_1829 = eq(T_1827, UInt<1>("h00")) - node T_1831 = or(UInt<1>("h00"), T_1708) - node T_1832 = or(T_1831, T_1711) - node T_1833 = or(T_1832, T_1714) - node T_1834 = or(T_1833, T_1717) - node T_1835 = or(T_1834, T_1720) - node T_1836 = or(T_1835, T_1723) - node T_1837 = or(T_1836, T_1726) - node T_1838 = or(T_1837, T_1729) - node T_1839 = or(T_1838, in[0].valid) - node T_1840 = or(T_1839, in[1].valid) - node T_1841 = or(T_1840, in[2].valid) - node T_1842 = or(T_1841, in[3].valid) - node T_1844 = eq(T_1842, UInt<1>("h00")) - node T_1846 = or(UInt<1>("h00"), T_1708) - node T_1847 = or(T_1846, T_1711) - node T_1848 = or(T_1847, T_1714) - node T_1849 = or(T_1848, T_1717) - node T_1850 = or(T_1849, T_1720) - node T_1851 = or(T_1850, T_1723) - node T_1852 = or(T_1851, T_1726) - node T_1853 = or(T_1852, T_1729) - node T_1854 = or(T_1853, in[0].valid) - node T_1855 = or(T_1854, in[1].valid) - node T_1856 = or(T_1855, in[2].valid) - node T_1857 = or(T_1856, in[3].valid) - node T_1858 = or(T_1857, in[4].valid) - node T_1860 = eq(T_1858, UInt<1>("h00")) - node T_1862 = or(UInt<1>("h00"), T_1708) - node T_1863 = or(T_1862, T_1711) - node T_1864 = or(T_1863, T_1714) - node T_1865 = or(T_1864, T_1717) - node T_1866 = or(T_1865, T_1720) - node T_1867 = or(T_1866, T_1723) - node T_1868 = or(T_1867, T_1726) - node T_1869 = or(T_1868, T_1729) - node T_1870 = or(T_1869, in[0].valid) - node T_1871 = or(T_1870, in[1].valid) - node T_1872 = or(T_1871, in[2].valid) - node T_1873 = or(T_1872, in[3].valid) - node T_1874 = or(T_1873, in[4].valid) - node T_1875 = or(T_1874, in[5].valid) - node T_1877 = eq(T_1875, UInt<1>("h00")) - node T_1879 = or(UInt<1>("h00"), T_1708) - node T_1880 = or(T_1879, T_1711) - node T_1881 = or(T_1880, T_1714) - node T_1882 = or(T_1881, T_1717) - node T_1883 = or(T_1882, T_1720) - node T_1884 = or(T_1883, T_1723) - node T_1885 = or(T_1884, T_1726) - node T_1886 = or(T_1885, T_1729) - node T_1887 = or(T_1886, in[0].valid) - node T_1888 = or(T_1887, in[1].valid) - node T_1889 = or(T_1888, in[2].valid) - node T_1890 = or(T_1889, in[3].valid) - node T_1891 = or(T_1890, in[4].valid) - node T_1892 = or(T_1891, in[5].valid) - node T_1893 = or(T_1892, in[6].valid) - node T_1895 = eq(T_1893, UInt<1>("h00")) - node T_1897 = gt(UInt<1>("h00"), last_grant) - node T_1898 = and(UInt<1>("h01"), T_1897) - node T_1899 = or(T_1898, T_1790) - node T_1901 = gt(UInt<1>("h01"), last_grant) - node T_1902 = and(T_1734, T_1901) - node T_1903 = or(T_1902, T_1802) - node T_1905 = gt(UInt<2>("h02"), last_grant) - node T_1906 = and(T_1739, T_1905) - node T_1907 = or(T_1906, T_1815) - node T_1909 = gt(UInt<2>("h03"), last_grant) - node T_1910 = and(T_1745, T_1909) - node T_1911 = or(T_1910, T_1829) - node T_1913 = gt(UInt<3>("h04"), last_grant) - node T_1914 = and(T_1752, T_1913) - node T_1915 = or(T_1914, T_1844) - node T_1917 = gt(UInt<3>("h05"), last_grant) - node T_1918 = and(T_1760, T_1917) - node T_1919 = or(T_1918, T_1860) - node T_1921 = gt(UInt<3>("h06"), last_grant) - node T_1922 = and(T_1769, T_1921) - node T_1923 = or(T_1922, T_1877) - node T_1925 = gt(UInt<3>("h07"), last_grant) - node T_1926 = and(T_1779, T_1925) - node T_1927 = or(T_1926, T_1895) - node T_1929 = eq(T_1504, UInt<1>("h00")) - node T_1930 = mux(T_1502, T_1929, T_1899) - node T_1931 = and(T_1930, out.ready) - in[0].ready := T_1931 - node T_1933 = eq(T_1504, UInt<1>("h01")) - node T_1934 = mux(T_1502, T_1933, T_1903) - node T_1935 = and(T_1934, out.ready) - in[1].ready := T_1935 - node T_1937 = eq(T_1504, UInt<2>("h02")) - node T_1938 = mux(T_1502, T_1937, T_1907) - node T_1939 = and(T_1938, out.ready) - in[2].ready := T_1939 - node T_1941 = eq(T_1504, UInt<2>("h03")) - node T_1942 = mux(T_1502, T_1941, T_1911) - node T_1943 = and(T_1942, out.ready) - in[3].ready := T_1943 - node T_1945 = eq(T_1504, UInt<3>("h04")) - node T_1946 = mux(T_1502, T_1945, T_1915) - node T_1947 = and(T_1946, out.ready) - in[4].ready := T_1947 - node T_1949 = eq(T_1504, UInt<3>("h05")) - node T_1950 = mux(T_1502, T_1949, T_1919) - node T_1951 = and(T_1950, out.ready) - in[5].ready := T_1951 - node T_1953 = eq(T_1504, UInt<3>("h06")) - node T_1954 = mux(T_1502, T_1953, T_1923) - node T_1955 = and(T_1954, out.ready) - in[6].ready := T_1955 - node T_1957 = eq(T_1504, UInt<3>("h07")) - node T_1958 = mux(T_1502, T_1957, T_1927) - node T_1959 = and(T_1958, out.ready) - in[7].ready := T_1959 - reg T_1961 : UInt<2>, clock, reset - onreset T_1961 := UInt<2>("h00") - node T_1963 = addw(T_1961, UInt<1>("h01")) - node T_1964 = and(out.ready, out.valid) - when T_1964 : - wire T_1968 : UInt<3>[1] - T_1968[0] := UInt<3>("h05") - node T_1971 = eq(T_1968[0], out.bits.g_type) - node T_1973 = or(UInt<1>("h00"), T_1971) - wire T_1975 : UInt<1>[2] - T_1975[0] := UInt<1>("h00") - T_1975[1] := UInt<1>("h01") - node T_1979 = eq(T_1975[0], out.bits.g_type) - node T_1980 = eq(T_1975[1], out.bits.g_type) - node T_1982 = or(UInt<1>("h00"), T_1979) - node T_1983 = or(T_1982, T_1980) - node T_1984 = mux(out.bits.is_builtin_type, T_1973, T_1983) - node T_1985 = and(UInt<1>("h01"), T_1984) - when T_1985 : - T_1961 := T_1963 - node T_1987 = eq(T_1502, UInt<1>("h00")) - when T_1987 : - T_1502 := UInt<1>("h01") - node T_1989 = and(in[0].ready, in[0].valid) - node T_1990 = and(in[1].ready, in[1].valid) - node T_1991 = and(in[2].ready, in[2].valid) - node T_1992 = and(in[3].ready, in[3].valid) - node T_1993 = and(in[4].ready, in[4].valid) - node T_1994 = and(in[5].ready, in[5].valid) - node T_1995 = and(in[6].ready, in[6].valid) - node T_1996 = and(in[7].ready, in[7].valid) - wire T_1998 : UInt<1>[8] - T_1998[0] := T_1989 - T_1998[1] := T_1990 - T_1998[2] := T_1991 - T_1998[3] := T_1992 - T_1998[4] := T_1993 - T_1998[5] := T_1994 - T_1998[6] := T_1995 - T_1998[7] := T_1996 - node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07")) - node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016) - node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017) - node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018) - node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019) - node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020) - node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021) - T_1504 := T_2022 - skip - skip - node T_2024 = eq(T_1963, UInt<1>("h00")) - when T_2024 : - T_1502 := UInt<1>("h00") - skip - skip - node T_2028 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_2030 = mux(in[5].valid, UInt<3>("h05"), T_2028) - node T_2032 = mux(in[4].valid, UInt<3>("h04"), T_2030) - node T_2034 = mux(in[3].valid, UInt<2>("h03"), T_2032) - node T_2036 = mux(in[2].valid, UInt<2>("h02"), T_2034) - node T_2038 = mux(in[1].valid, UInt<1>("h01"), T_2036) - node T_2040 = mux(in[0].valid, UInt<1>("h00"), T_2038) - node T_2042 = gt(UInt<3>("h07"), last_grant) - node T_2043 = and(in[7].valid, T_2042) - node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040) - node T_2047 = gt(UInt<3>("h06"), last_grant) - node T_2048 = and(in[6].valid, T_2047) - node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045) - node T_2052 = gt(UInt<3>("h05"), last_grant) - node T_2053 = and(in[5].valid, T_2052) - node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050) - node T_2057 = gt(UInt<3>("h04"), last_grant) - node T_2058 = and(in[4].valid, T_2057) - node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055) - node T_2062 = gt(UInt<2>("h03"), last_grant) - node T_2063 = and(in[3].valid, T_2062) - node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060) - node T_2067 = gt(UInt<2>("h02"), last_grant) - node T_2068 = and(in[2].valid, T_2067) - node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065) - node T_2072 = gt(UInt<1>("h01"), last_grant) - node T_2073 = and(in[1].valid, T_2072) - node choose = mux(T_2073, UInt<1>("h01"), T_2070) - node T_2076 = mux(T_1502, T_1504, choose) - T_1506 := T_2076 - node T_2077 = and(out.ready, out.valid) - when T_2077 : - last_grant := T_1506 - skip - - module LockingRRArbiter_34 : - output chosen : UInt<3> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.client_id := UInt<1>("h00") - out.bits.p_type := UInt<1>("h00") - out.bits.addr_block := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - in[3].ready := UInt<1>("h00") - in[4].ready := UInt<1>("h00") - in[5].ready := UInt<1>("h00") - in[6].ready := UInt<1>("h00") - in[7].ready := UInt<1>("h00") - reg T_1318 : UInt<1>, clock, reset - onreset T_1318 := UInt<1>("h00") - reg T_1320 : UInt, clock, reset - onreset T_1320 := UInt<3>("h07") - wire T_1322 : UInt<3> - T_1322 := UInt<1>("h00") - infer accessor T_1324 = in[T_1322] - out.valid := T_1324.valid - infer accessor T_1381 = in[T_1322] - out.bits <> T_1381.bits - chosen := T_1322 - infer accessor T_1438 = in[T_1322] - T_1438.ready := UInt<1>("h00") - reg last_grant : UInt<3>, clock, reset - onreset last_grant := UInt<3>("h00") - node T_1499 = gt(UInt<1>("h00"), last_grant) - node T_1500 = and(in[0].valid, T_1499) - node T_1502 = gt(UInt<1>("h01"), last_grant) - node T_1503 = and(in[1].valid, T_1502) - node T_1505 = gt(UInt<2>("h02"), last_grant) - node T_1506 = and(in[2].valid, T_1505) - node T_1508 = gt(UInt<2>("h03"), last_grant) - node T_1509 = and(in[3].valid, T_1508) - node T_1511 = gt(UInt<3>("h04"), last_grant) - node T_1512 = and(in[4].valid, T_1511) - node T_1514 = gt(UInt<3>("h05"), last_grant) - node T_1515 = and(in[5].valid, T_1514) - node T_1517 = gt(UInt<3>("h06"), last_grant) - node T_1518 = and(in[6].valid, T_1517) - node T_1520 = gt(UInt<3>("h07"), last_grant) - node T_1521 = and(in[7].valid, T_1520) - node T_1524 = or(UInt<1>("h00"), T_1500) - node T_1526 = eq(T_1524, UInt<1>("h00")) - node T_1528 = or(UInt<1>("h00"), T_1500) - node T_1529 = or(T_1528, T_1503) - node T_1531 = eq(T_1529, UInt<1>("h00")) - node T_1533 = or(UInt<1>("h00"), T_1500) - node T_1534 = or(T_1533, T_1503) - node T_1535 = or(T_1534, T_1506) - node T_1537 = eq(T_1535, UInt<1>("h00")) - node T_1539 = or(UInt<1>("h00"), T_1500) - node T_1540 = or(T_1539, T_1503) - node T_1541 = or(T_1540, T_1506) - node T_1542 = or(T_1541, T_1509) - node T_1544 = eq(T_1542, UInt<1>("h00")) - node T_1546 = or(UInt<1>("h00"), T_1500) - node T_1547 = or(T_1546, T_1503) - node T_1548 = or(T_1547, T_1506) - node T_1549 = or(T_1548, T_1509) - node T_1550 = or(T_1549, T_1512) - node T_1552 = eq(T_1550, UInt<1>("h00")) - node T_1554 = or(UInt<1>("h00"), T_1500) - node T_1555 = or(T_1554, T_1503) - node T_1556 = or(T_1555, T_1506) - node T_1557 = or(T_1556, T_1509) - node T_1558 = or(T_1557, T_1512) - node T_1559 = or(T_1558, T_1515) - node T_1561 = eq(T_1559, UInt<1>("h00")) - node T_1563 = or(UInt<1>("h00"), T_1500) - node T_1564 = or(T_1563, T_1503) - node T_1565 = or(T_1564, T_1506) - node T_1566 = or(T_1565, T_1509) - node T_1567 = or(T_1566, T_1512) - node T_1568 = or(T_1567, T_1515) - node T_1569 = or(T_1568, T_1518) - node T_1571 = eq(T_1569, UInt<1>("h00")) - node T_1573 = or(UInt<1>("h00"), T_1500) - node T_1574 = or(T_1573, T_1503) - node T_1575 = or(T_1574, T_1506) - node T_1576 = or(T_1575, T_1509) - node T_1577 = or(T_1576, T_1512) - node T_1578 = or(T_1577, T_1515) - node T_1579 = or(T_1578, T_1518) - node T_1580 = or(T_1579, T_1521) - node T_1582 = eq(T_1580, UInt<1>("h00")) - node T_1584 = or(UInt<1>("h00"), T_1500) - node T_1585 = or(T_1584, T_1503) - node T_1586 = or(T_1585, T_1506) - node T_1587 = or(T_1586, T_1509) - node T_1588 = or(T_1587, T_1512) - node T_1589 = or(T_1588, T_1515) - node T_1590 = or(T_1589, T_1518) - node T_1591 = or(T_1590, T_1521) - node T_1592 = or(T_1591, in[0].valid) - node T_1594 = eq(T_1592, UInt<1>("h00")) - node T_1596 = or(UInt<1>("h00"), T_1500) - node T_1597 = or(T_1596, T_1503) - node T_1598 = or(T_1597, T_1506) - node T_1599 = or(T_1598, T_1509) - node T_1600 = or(T_1599, T_1512) - node T_1601 = or(T_1600, T_1515) - node T_1602 = or(T_1601, T_1518) - node T_1603 = or(T_1602, T_1521) - node T_1604 = or(T_1603, in[0].valid) - node T_1605 = or(T_1604, in[1].valid) - node T_1607 = eq(T_1605, UInt<1>("h00")) - node T_1609 = or(UInt<1>("h00"), T_1500) - node T_1610 = or(T_1609, T_1503) - node T_1611 = or(T_1610, T_1506) - node T_1612 = or(T_1611, T_1509) - node T_1613 = or(T_1612, T_1512) - node T_1614 = or(T_1613, T_1515) - node T_1615 = or(T_1614, T_1518) - node T_1616 = or(T_1615, T_1521) - node T_1617 = or(T_1616, in[0].valid) - node T_1618 = or(T_1617, in[1].valid) - node T_1619 = or(T_1618, in[2].valid) - node T_1621 = eq(T_1619, UInt<1>("h00")) - node T_1623 = or(UInt<1>("h00"), T_1500) - node T_1624 = or(T_1623, T_1503) - node T_1625 = or(T_1624, T_1506) - node T_1626 = or(T_1625, T_1509) - node T_1627 = or(T_1626, T_1512) - node T_1628 = or(T_1627, T_1515) - node T_1629 = or(T_1628, T_1518) - node T_1630 = or(T_1629, T_1521) - node T_1631 = or(T_1630, in[0].valid) - node T_1632 = or(T_1631, in[1].valid) - node T_1633 = or(T_1632, in[2].valid) - node T_1634 = or(T_1633, in[3].valid) - node T_1636 = eq(T_1634, UInt<1>("h00")) - node T_1638 = or(UInt<1>("h00"), T_1500) - node T_1639 = or(T_1638, T_1503) - node T_1640 = or(T_1639, T_1506) - node T_1641 = or(T_1640, T_1509) - node T_1642 = or(T_1641, T_1512) - node T_1643 = or(T_1642, T_1515) - node T_1644 = or(T_1643, T_1518) - node T_1645 = or(T_1644, T_1521) - node T_1646 = or(T_1645, in[0].valid) - node T_1647 = or(T_1646, in[1].valid) - node T_1648 = or(T_1647, in[2].valid) - node T_1649 = or(T_1648, in[3].valid) - node T_1650 = or(T_1649, in[4].valid) - node T_1652 = eq(T_1650, UInt<1>("h00")) - node T_1654 = or(UInt<1>("h00"), T_1500) - node T_1655 = or(T_1654, T_1503) - node T_1656 = or(T_1655, T_1506) - node T_1657 = or(T_1656, T_1509) - node T_1658 = or(T_1657, T_1512) - node T_1659 = or(T_1658, T_1515) - node T_1660 = or(T_1659, T_1518) - node T_1661 = or(T_1660, T_1521) - node T_1662 = or(T_1661, in[0].valid) - node T_1663 = or(T_1662, in[1].valid) - node T_1664 = or(T_1663, in[2].valid) - node T_1665 = or(T_1664, in[3].valid) - node T_1666 = or(T_1665, in[4].valid) - node T_1667 = or(T_1666, in[5].valid) - node T_1669 = eq(T_1667, UInt<1>("h00")) - node T_1671 = or(UInt<1>("h00"), T_1500) - node T_1672 = or(T_1671, T_1503) - node T_1673 = or(T_1672, T_1506) - node T_1674 = or(T_1673, T_1509) - node T_1675 = or(T_1674, T_1512) - node T_1676 = or(T_1675, T_1515) - node T_1677 = or(T_1676, T_1518) - node T_1678 = or(T_1677, T_1521) - node T_1679 = or(T_1678, in[0].valid) - node T_1680 = or(T_1679, in[1].valid) - node T_1681 = or(T_1680, in[2].valid) - node T_1682 = or(T_1681, in[3].valid) - node T_1683 = or(T_1682, in[4].valid) - node T_1684 = or(T_1683, in[5].valid) - node T_1685 = or(T_1684, in[6].valid) - node T_1687 = eq(T_1685, UInt<1>("h00")) - node T_1689 = gt(UInt<1>("h00"), last_grant) - node T_1690 = and(UInt<1>("h01"), T_1689) - node T_1691 = or(T_1690, T_1582) - node T_1693 = gt(UInt<1>("h01"), last_grant) - node T_1694 = and(T_1526, T_1693) - node T_1695 = or(T_1694, T_1594) - node T_1697 = gt(UInt<2>("h02"), last_grant) - node T_1698 = and(T_1531, T_1697) - node T_1699 = or(T_1698, T_1607) - node T_1701 = gt(UInt<2>("h03"), last_grant) - node T_1702 = and(T_1537, T_1701) - node T_1703 = or(T_1702, T_1621) - node T_1705 = gt(UInt<3>("h04"), last_grant) - node T_1706 = and(T_1544, T_1705) - node T_1707 = or(T_1706, T_1636) - node T_1709 = gt(UInt<3>("h05"), last_grant) - node T_1710 = and(T_1552, T_1709) - node T_1711 = or(T_1710, T_1652) - node T_1713 = gt(UInt<3>("h06"), last_grant) - node T_1714 = and(T_1561, T_1713) - node T_1715 = or(T_1714, T_1669) - node T_1717 = gt(UInt<3>("h07"), last_grant) - node T_1718 = and(T_1571, T_1717) - node T_1719 = or(T_1718, T_1687) - node T_1721 = eq(T_1320, UInt<1>("h00")) - node T_1722 = mux(T_1318, T_1721, T_1691) - node T_1723 = and(T_1722, out.ready) - in[0].ready := T_1723 - node T_1725 = eq(T_1320, UInt<1>("h01")) - node T_1726 = mux(T_1318, T_1725, T_1695) - node T_1727 = and(T_1726, out.ready) - in[1].ready := T_1727 - node T_1729 = eq(T_1320, UInt<2>("h02")) - node T_1730 = mux(T_1318, T_1729, T_1699) - node T_1731 = and(T_1730, out.ready) - in[2].ready := T_1731 - node T_1733 = eq(T_1320, UInt<2>("h03")) - node T_1734 = mux(T_1318, T_1733, T_1703) - node T_1735 = and(T_1734, out.ready) - in[3].ready := T_1735 - node T_1737 = eq(T_1320, UInt<3>("h04")) - node T_1738 = mux(T_1318, T_1737, T_1707) - node T_1739 = and(T_1738, out.ready) - in[4].ready := T_1739 - node T_1741 = eq(T_1320, UInt<3>("h05")) - node T_1742 = mux(T_1318, T_1741, T_1711) - node T_1743 = and(T_1742, out.ready) - in[5].ready := T_1743 - node T_1745 = eq(T_1320, UInt<3>("h06")) - node T_1746 = mux(T_1318, T_1745, T_1715) - node T_1747 = and(T_1746, out.ready) - in[6].ready := T_1747 - node T_1749 = eq(T_1320, UInt<3>("h07")) - node T_1750 = mux(T_1318, T_1749, T_1719) - node T_1751 = and(T_1750, out.ready) - in[7].ready := T_1751 - reg T_1753 : UInt<2>, clock, reset - onreset T_1753 := UInt<2>("h00") - node T_1755 = addw(T_1753, UInt<1>("h01")) - node T_1756 = and(out.ready, out.valid) - when T_1756 : - when UInt<1>("h00") : - T_1753 := T_1755 - node T_1759 = eq(T_1318, UInt<1>("h00")) - when T_1759 : - T_1318 := UInt<1>("h01") - node T_1761 = and(in[0].ready, in[0].valid) - node T_1762 = and(in[1].ready, in[1].valid) - node T_1763 = and(in[2].ready, in[2].valid) - node T_1764 = and(in[3].ready, in[3].valid) - node T_1765 = and(in[4].ready, in[4].valid) - node T_1766 = and(in[5].ready, in[5].valid) - node T_1767 = and(in[6].ready, in[6].valid) - node T_1768 = and(in[7].ready, in[7].valid) - wire T_1770 : UInt<1>[8] - T_1770[0] := T_1761 - T_1770[1] := T_1762 - T_1770[2] := T_1763 - T_1770[3] := T_1764 - T_1770[4] := T_1765 - T_1770[5] := T_1766 - T_1770[6] := T_1767 - T_1770[7] := T_1768 - node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788) - node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789) - node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790) - node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791) - node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792) - node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793) - T_1320 := T_1794 - skip - skip - node T_1796 = eq(T_1755, UInt<1>("h00")) - when T_1796 : - T_1318 := UInt<1>("h00") - skip - skip - node T_1800 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_1802 = mux(in[5].valid, UInt<3>("h05"), T_1800) - node T_1804 = mux(in[4].valid, UInt<3>("h04"), T_1802) - node T_1806 = mux(in[3].valid, UInt<2>("h03"), T_1804) - node T_1808 = mux(in[2].valid, UInt<2>("h02"), T_1806) - node T_1810 = mux(in[1].valid, UInt<1>("h01"), T_1808) - node T_1812 = mux(in[0].valid, UInt<1>("h00"), T_1810) - node T_1814 = gt(UInt<3>("h07"), last_grant) - node T_1815 = and(in[7].valid, T_1814) - node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812) - node T_1819 = gt(UInt<3>("h06"), last_grant) - node T_1820 = and(in[6].valid, T_1819) - node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817) - node T_1824 = gt(UInt<3>("h05"), last_grant) - node T_1825 = and(in[5].valid, T_1824) - node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822) - node T_1829 = gt(UInt<3>("h04"), last_grant) - node T_1830 = and(in[4].valid, T_1829) - node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827) - node T_1834 = gt(UInt<2>("h03"), last_grant) - node T_1835 = and(in[3].valid, T_1834) - node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832) - node T_1839 = gt(UInt<2>("h02"), last_grant) - node T_1840 = and(in[2].valid, T_1839) - node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837) - node T_1844 = gt(UInt<1>("h01"), last_grant) - node T_1845 = and(in[1].valid, T_1844) - node choose = mux(T_1845, UInt<1>("h01"), T_1842) - node T_1848 = mux(T_1318, T_1320, choose) - T_1322 := T_1848 - node T_1849 = and(out.ready, out.valid) - when T_1849 : - last_grant := T_1322 - skip - - module LockingRRArbiter_35 : - output chosen : UInt<3> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}[8] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.union := UInt<1>("h00") - out.bits.a_type := UInt<1>("h00") - out.bits.is_builtin_type := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.addr_block := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - in[3].ready := UInt<1>("h00") - in[4].ready := UInt<1>("h00") - in[5].ready := UInt<1>("h00") - in[6].ready := UInt<1>("h00") - in[7].ready := UInt<1>("h00") - reg T_1364 : UInt<1>, clock, reset - onreset T_1364 := UInt<1>("h00") - reg T_1366 : UInt, clock, reset - onreset T_1366 := UInt<3>("h07") - wire T_1368 : UInt<3> - T_1368 := UInt<1>("h00") - infer accessor T_1370 = in[T_1368] - out.valid := T_1370.valid - infer accessor T_1429 = in[T_1368] - out.bits <> T_1429.bits - chosen := T_1368 - infer accessor T_1488 = in[T_1368] - T_1488.ready := UInt<1>("h00") - reg last_grant : UInt<3>, clock, reset - onreset last_grant := UInt<3>("h00") - node T_1551 = gt(UInt<1>("h00"), last_grant) - node T_1552 = and(in[0].valid, T_1551) - node T_1554 = gt(UInt<1>("h01"), last_grant) - node T_1555 = and(in[1].valid, T_1554) - node T_1557 = gt(UInt<2>("h02"), last_grant) - node T_1558 = and(in[2].valid, T_1557) - node T_1560 = gt(UInt<2>("h03"), last_grant) - node T_1561 = and(in[3].valid, T_1560) - node T_1563 = gt(UInt<3>("h04"), last_grant) - node T_1564 = and(in[4].valid, T_1563) - node T_1566 = gt(UInt<3>("h05"), last_grant) - node T_1567 = and(in[5].valid, T_1566) - node T_1569 = gt(UInt<3>("h06"), last_grant) - node T_1570 = and(in[6].valid, T_1569) - node T_1572 = gt(UInt<3>("h07"), last_grant) - node T_1573 = and(in[7].valid, T_1572) - node T_1576 = or(UInt<1>("h00"), T_1552) - node T_1578 = eq(T_1576, UInt<1>("h00")) - node T_1580 = or(UInt<1>("h00"), T_1552) - node T_1581 = or(T_1580, T_1555) - node T_1583 = eq(T_1581, UInt<1>("h00")) - node T_1585 = or(UInt<1>("h00"), T_1552) - node T_1586 = or(T_1585, T_1555) - node T_1587 = or(T_1586, T_1558) - node T_1589 = eq(T_1587, UInt<1>("h00")) - node T_1591 = or(UInt<1>("h00"), T_1552) - node T_1592 = or(T_1591, T_1555) - node T_1593 = or(T_1592, T_1558) - node T_1594 = or(T_1593, T_1561) - node T_1596 = eq(T_1594, UInt<1>("h00")) - node T_1598 = or(UInt<1>("h00"), T_1552) - node T_1599 = or(T_1598, T_1555) - node T_1600 = or(T_1599, T_1558) - node T_1601 = or(T_1600, T_1561) - node T_1602 = or(T_1601, T_1564) - node T_1604 = eq(T_1602, UInt<1>("h00")) - node T_1606 = or(UInt<1>("h00"), T_1552) - node T_1607 = or(T_1606, T_1555) - node T_1608 = or(T_1607, T_1558) - node T_1609 = or(T_1608, T_1561) - node T_1610 = or(T_1609, T_1564) - node T_1611 = or(T_1610, T_1567) - node T_1613 = eq(T_1611, UInt<1>("h00")) - node T_1615 = or(UInt<1>("h00"), T_1552) - node T_1616 = or(T_1615, T_1555) - node T_1617 = or(T_1616, T_1558) - node T_1618 = or(T_1617, T_1561) - node T_1619 = or(T_1618, T_1564) - node T_1620 = or(T_1619, T_1567) - node T_1621 = or(T_1620, T_1570) - node T_1623 = eq(T_1621, UInt<1>("h00")) - node T_1625 = or(UInt<1>("h00"), T_1552) - node T_1626 = or(T_1625, T_1555) - node T_1627 = or(T_1626, T_1558) - node T_1628 = or(T_1627, T_1561) - node T_1629 = or(T_1628, T_1564) - node T_1630 = or(T_1629, T_1567) - node T_1631 = or(T_1630, T_1570) - node T_1632 = or(T_1631, T_1573) - node T_1634 = eq(T_1632, UInt<1>("h00")) - node T_1636 = or(UInt<1>("h00"), T_1552) - node T_1637 = or(T_1636, T_1555) - node T_1638 = or(T_1637, T_1558) - node T_1639 = or(T_1638, T_1561) - node T_1640 = or(T_1639, T_1564) - node T_1641 = or(T_1640, T_1567) - node T_1642 = or(T_1641, T_1570) - node T_1643 = or(T_1642, T_1573) - node T_1644 = or(T_1643, in[0].valid) - node T_1646 = eq(T_1644, UInt<1>("h00")) - node T_1648 = or(UInt<1>("h00"), T_1552) - node T_1649 = or(T_1648, T_1555) - node T_1650 = or(T_1649, T_1558) - node T_1651 = or(T_1650, T_1561) - node T_1652 = or(T_1651, T_1564) - node T_1653 = or(T_1652, T_1567) - node T_1654 = or(T_1653, T_1570) - node T_1655 = or(T_1654, T_1573) - node T_1656 = or(T_1655, in[0].valid) - node T_1657 = or(T_1656, in[1].valid) - node T_1659 = eq(T_1657, UInt<1>("h00")) - node T_1661 = or(UInt<1>("h00"), T_1552) - node T_1662 = or(T_1661, T_1555) - node T_1663 = or(T_1662, T_1558) - node T_1664 = or(T_1663, T_1561) - node T_1665 = or(T_1664, T_1564) - node T_1666 = or(T_1665, T_1567) - node T_1667 = or(T_1666, T_1570) - node T_1668 = or(T_1667, T_1573) - node T_1669 = or(T_1668, in[0].valid) - node T_1670 = or(T_1669, in[1].valid) - node T_1671 = or(T_1670, in[2].valid) - node T_1673 = eq(T_1671, UInt<1>("h00")) - node T_1675 = or(UInt<1>("h00"), T_1552) - node T_1676 = or(T_1675, T_1555) - node T_1677 = or(T_1676, T_1558) - node T_1678 = or(T_1677, T_1561) - node T_1679 = or(T_1678, T_1564) - node T_1680 = or(T_1679, T_1567) - node T_1681 = or(T_1680, T_1570) - node T_1682 = or(T_1681, T_1573) - node T_1683 = or(T_1682, in[0].valid) - node T_1684 = or(T_1683, in[1].valid) - node T_1685 = or(T_1684, in[2].valid) - node T_1686 = or(T_1685, in[3].valid) - node T_1688 = eq(T_1686, UInt<1>("h00")) - node T_1690 = or(UInt<1>("h00"), T_1552) - node T_1691 = or(T_1690, T_1555) - node T_1692 = or(T_1691, T_1558) - node T_1693 = or(T_1692, T_1561) - node T_1694 = or(T_1693, T_1564) - node T_1695 = or(T_1694, T_1567) - node T_1696 = or(T_1695, T_1570) - node T_1697 = or(T_1696, T_1573) - node T_1698 = or(T_1697, in[0].valid) - node T_1699 = or(T_1698, in[1].valid) - node T_1700 = or(T_1699, in[2].valid) - node T_1701 = or(T_1700, in[3].valid) - node T_1702 = or(T_1701, in[4].valid) - node T_1704 = eq(T_1702, UInt<1>("h00")) - node T_1706 = or(UInt<1>("h00"), T_1552) - node T_1707 = or(T_1706, T_1555) - node T_1708 = or(T_1707, T_1558) - node T_1709 = or(T_1708, T_1561) - node T_1710 = or(T_1709, T_1564) - node T_1711 = or(T_1710, T_1567) - node T_1712 = or(T_1711, T_1570) - node T_1713 = or(T_1712, T_1573) - node T_1714 = or(T_1713, in[0].valid) - node T_1715 = or(T_1714, in[1].valid) - node T_1716 = or(T_1715, in[2].valid) - node T_1717 = or(T_1716, in[3].valid) - node T_1718 = or(T_1717, in[4].valid) - node T_1719 = or(T_1718, in[5].valid) - node T_1721 = eq(T_1719, UInt<1>("h00")) - node T_1723 = or(UInt<1>("h00"), T_1552) - node T_1724 = or(T_1723, T_1555) - node T_1725 = or(T_1724, T_1558) - node T_1726 = or(T_1725, T_1561) - node T_1727 = or(T_1726, T_1564) - node T_1728 = or(T_1727, T_1567) - node T_1729 = or(T_1728, T_1570) - node T_1730 = or(T_1729, T_1573) - node T_1731 = or(T_1730, in[0].valid) - node T_1732 = or(T_1731, in[1].valid) - node T_1733 = or(T_1732, in[2].valid) - node T_1734 = or(T_1733, in[3].valid) - node T_1735 = or(T_1734, in[4].valid) - node T_1736 = or(T_1735, in[5].valid) - node T_1737 = or(T_1736, in[6].valid) - node T_1739 = eq(T_1737, UInt<1>("h00")) - node T_1741 = gt(UInt<1>("h00"), last_grant) - node T_1742 = and(UInt<1>("h01"), T_1741) - node T_1743 = or(T_1742, T_1634) - node T_1745 = gt(UInt<1>("h01"), last_grant) - node T_1746 = and(T_1578, T_1745) - node T_1747 = or(T_1746, T_1646) - node T_1749 = gt(UInt<2>("h02"), last_grant) - node T_1750 = and(T_1583, T_1749) - node T_1751 = or(T_1750, T_1659) - node T_1753 = gt(UInt<2>("h03"), last_grant) - node T_1754 = and(T_1589, T_1753) - node T_1755 = or(T_1754, T_1673) - node T_1757 = gt(UInt<3>("h04"), last_grant) - node T_1758 = and(T_1596, T_1757) - node T_1759 = or(T_1758, T_1688) - node T_1761 = gt(UInt<3>("h05"), last_grant) - node T_1762 = and(T_1604, T_1761) - node T_1763 = or(T_1762, T_1704) - node T_1765 = gt(UInt<3>("h06"), last_grant) - node T_1766 = and(T_1613, T_1765) - node T_1767 = or(T_1766, T_1721) - node T_1769 = gt(UInt<3>("h07"), last_grant) - node T_1770 = and(T_1623, T_1769) - node T_1771 = or(T_1770, T_1739) - node T_1773 = eq(T_1366, UInt<1>("h00")) - node T_1774 = mux(T_1364, T_1773, T_1743) - node T_1775 = and(T_1774, out.ready) - in[0].ready := T_1775 - node T_1777 = eq(T_1366, UInt<1>("h01")) - node T_1778 = mux(T_1364, T_1777, T_1747) - node T_1779 = and(T_1778, out.ready) - in[1].ready := T_1779 - node T_1781 = eq(T_1366, UInt<2>("h02")) - node T_1782 = mux(T_1364, T_1781, T_1751) - node T_1783 = and(T_1782, out.ready) - in[2].ready := T_1783 - node T_1785 = eq(T_1366, UInt<2>("h03")) - node T_1786 = mux(T_1364, T_1785, T_1755) - node T_1787 = and(T_1786, out.ready) - in[3].ready := T_1787 - node T_1789 = eq(T_1366, UInt<3>("h04")) - node T_1790 = mux(T_1364, T_1789, T_1759) - node T_1791 = and(T_1790, out.ready) - in[4].ready := T_1791 - node T_1793 = eq(T_1366, UInt<3>("h05")) - node T_1794 = mux(T_1364, T_1793, T_1763) - node T_1795 = and(T_1794, out.ready) - in[5].ready := T_1795 - node T_1797 = eq(T_1366, UInt<3>("h06")) - node T_1798 = mux(T_1364, T_1797, T_1767) - node T_1799 = and(T_1798, out.ready) - in[6].ready := T_1799 - node T_1801 = eq(T_1366, UInt<3>("h07")) - node T_1802 = mux(T_1364, T_1801, T_1771) - node T_1803 = and(T_1802, out.ready) - in[7].ready := T_1803 - reg T_1805 : UInt<2>, clock, reset - onreset T_1805 := UInt<2>("h00") - node T_1807 = addw(T_1805, UInt<1>("h01")) - node T_1808 = and(out.ready, out.valid) - when T_1808 : - node T_1810 = and(UInt<1>("h01"), out.bits.is_builtin_type) - wire T_1813 : UInt<3>[1] - T_1813[0] := UInt<3>("h03") - node T_1816 = eq(T_1813[0], out.bits.a_type) - node T_1818 = or(UInt<1>("h00"), T_1816) - node T_1819 = and(T_1810, T_1818) - when T_1819 : - T_1805 := T_1807 - node T_1821 = eq(T_1364, UInt<1>("h00")) - when T_1821 : - T_1364 := UInt<1>("h01") - node T_1823 = and(in[0].ready, in[0].valid) - node T_1824 = and(in[1].ready, in[1].valid) - node T_1825 = and(in[2].ready, in[2].valid) - node T_1826 = and(in[3].ready, in[3].valid) - node T_1827 = and(in[4].ready, in[4].valid) - node T_1828 = and(in[5].ready, in[5].valid) - node T_1829 = and(in[6].ready, in[6].valid) - node T_1830 = and(in[7].ready, in[7].valid) - wire T_1832 : UInt<1>[8] - T_1832[0] := T_1823 - T_1832[1] := T_1824 - T_1832[2] := T_1825 - T_1832[3] := T_1826 - T_1832[4] := T_1827 - T_1832[5] := T_1828 - T_1832[6] := T_1829 - T_1832[7] := T_1830 - node T_1850 = mux(T_1832[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1851 = mux(T_1832[5], UInt<3>("h05"), T_1850) - node T_1852 = mux(T_1832[4], UInt<3>("h04"), T_1851) - node T_1853 = mux(T_1832[3], UInt<2>("h03"), T_1852) - node T_1854 = mux(T_1832[2], UInt<2>("h02"), T_1853) - node T_1855 = mux(T_1832[1], UInt<1>("h01"), T_1854) - node T_1856 = mux(T_1832[0], UInt<1>("h00"), T_1855) - T_1366 := T_1856 - skip - skip - node T_1858 = eq(T_1807, UInt<1>("h00")) - when T_1858 : - T_1364 := UInt<1>("h00") - skip - skip - node T_1862 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_1864 = mux(in[5].valid, UInt<3>("h05"), T_1862) - node T_1866 = mux(in[4].valid, UInt<3>("h04"), T_1864) - node T_1868 = mux(in[3].valid, UInt<2>("h03"), T_1866) - node T_1870 = mux(in[2].valid, UInt<2>("h02"), T_1868) - node T_1872 = mux(in[1].valid, UInt<1>("h01"), T_1870) - node T_1874 = mux(in[0].valid, UInt<1>("h00"), T_1872) - node T_1876 = gt(UInt<3>("h07"), last_grant) - node T_1877 = and(in[7].valid, T_1876) - node T_1879 = mux(T_1877, UInt<3>("h07"), T_1874) - node T_1881 = gt(UInt<3>("h06"), last_grant) - node T_1882 = and(in[6].valid, T_1881) - node T_1884 = mux(T_1882, UInt<3>("h06"), T_1879) - node T_1886 = gt(UInt<3>("h05"), last_grant) - node T_1887 = and(in[5].valid, T_1886) - node T_1889 = mux(T_1887, UInt<3>("h05"), T_1884) - node T_1891 = gt(UInt<3>("h04"), last_grant) - node T_1892 = and(in[4].valid, T_1891) - node T_1894 = mux(T_1892, UInt<3>("h04"), T_1889) - node T_1896 = gt(UInt<2>("h03"), last_grant) - node T_1897 = and(in[3].valid, T_1896) - node T_1899 = mux(T_1897, UInt<2>("h03"), T_1894) - node T_1901 = gt(UInt<2>("h02"), last_grant) - node T_1902 = and(in[2].valid, T_1901) - node T_1904 = mux(T_1902, UInt<2>("h02"), T_1899) - node T_1906 = gt(UInt<1>("h01"), last_grant) - node T_1907 = and(in[1].valid, T_1906) - node choose = mux(T_1907, UInt<1>("h01"), T_1904) - node T_1910 = mux(T_1364, T_1366, choose) - T_1368 := T_1910 - node T_1911 = and(out.ready, out.valid) - when T_1911 : - last_grant := T_1368 - skip - - module ClientUncachedTileLinkIOArbiter : - output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[8] - input clock : Clock - input reset : UInt<1> - - out.grant.ready := UInt<1>("h00") - out.acquire.bits.union := UInt<1>("h00") - out.acquire.bits.a_type := UInt<1>("h00") - out.acquire.bits.is_builtin_type := UInt<1>("h00") - out.acquire.bits.data := UInt<1>("h00") - out.acquire.bits.addr_beat := UInt<1>("h00") - out.acquire.bits.client_xact_id := UInt<1>("h00") - out.acquire.bits.addr_block := UInt<1>("h00") - out.acquire.valid := UInt<1>("h00") - in[0].grant.bits.g_type := UInt<1>("h00") - in[0].grant.bits.is_builtin_type := UInt<1>("h00") - in[0].grant.bits.manager_xact_id := UInt<1>("h00") - in[0].grant.bits.client_xact_id := UInt<1>("h00") - in[0].grant.bits.data := UInt<1>("h00") - in[0].grant.bits.addr_beat := UInt<1>("h00") - in[0].grant.valid := UInt<1>("h00") - in[0].acquire.ready := UInt<1>("h00") - in[1].grant.bits.g_type := UInt<1>("h00") - in[1].grant.bits.is_builtin_type := UInt<1>("h00") - in[1].grant.bits.manager_xact_id := UInt<1>("h00") - in[1].grant.bits.client_xact_id := UInt<1>("h00") - in[1].grant.bits.data := UInt<1>("h00") - in[1].grant.bits.addr_beat := UInt<1>("h00") - in[1].grant.valid := UInt<1>("h00") - in[1].acquire.ready := UInt<1>("h00") - in[2].grant.bits.g_type := UInt<1>("h00") - in[2].grant.bits.is_builtin_type := UInt<1>("h00") - in[2].grant.bits.manager_xact_id := UInt<1>("h00") - in[2].grant.bits.client_xact_id := UInt<1>("h00") - in[2].grant.bits.data := UInt<1>("h00") - in[2].grant.bits.addr_beat := UInt<1>("h00") - in[2].grant.valid := UInt<1>("h00") - in[2].acquire.ready := UInt<1>("h00") - in[3].grant.bits.g_type := UInt<1>("h00") - in[3].grant.bits.is_builtin_type := UInt<1>("h00") - in[3].grant.bits.manager_xact_id := UInt<1>("h00") - in[3].grant.bits.client_xact_id := UInt<1>("h00") - in[3].grant.bits.data := UInt<1>("h00") - in[3].grant.bits.addr_beat := UInt<1>("h00") - in[3].grant.valid := UInt<1>("h00") - in[3].acquire.ready := UInt<1>("h00") - in[4].grant.bits.g_type := UInt<1>("h00") - in[4].grant.bits.is_builtin_type := UInt<1>("h00") - in[4].grant.bits.manager_xact_id := UInt<1>("h00") - in[4].grant.bits.client_xact_id := UInt<1>("h00") - in[4].grant.bits.data := UInt<1>("h00") - in[4].grant.bits.addr_beat := UInt<1>("h00") - in[4].grant.valid := UInt<1>("h00") - in[4].acquire.ready := UInt<1>("h00") - in[5].grant.bits.g_type := UInt<1>("h00") - in[5].grant.bits.is_builtin_type := UInt<1>("h00") - in[5].grant.bits.manager_xact_id := UInt<1>("h00") - in[5].grant.bits.client_xact_id := UInt<1>("h00") - in[5].grant.bits.data := UInt<1>("h00") - in[5].grant.bits.addr_beat := UInt<1>("h00") - in[5].grant.valid := UInt<1>("h00") - in[5].acquire.ready := UInt<1>("h00") - in[6].grant.bits.g_type := UInt<1>("h00") - in[6].grant.bits.is_builtin_type := UInt<1>("h00") - in[6].grant.bits.manager_xact_id := UInt<1>("h00") - in[6].grant.bits.client_xact_id := UInt<1>("h00") - in[6].grant.bits.data := UInt<1>("h00") - in[6].grant.bits.addr_beat := UInt<1>("h00") - in[6].grant.valid := UInt<1>("h00") - in[6].acquire.ready := UInt<1>("h00") - in[7].grant.bits.g_type := UInt<1>("h00") - in[7].grant.bits.is_builtin_type := UInt<1>("h00") - in[7].grant.bits.manager_xact_id := UInt<1>("h00") - in[7].grant.bits.client_xact_id := UInt<1>("h00") - in[7].grant.bits.data := UInt<1>("h00") - in[7].grant.bits.addr_beat := UInt<1>("h00") - in[7].grant.valid := UInt<1>("h00") - in[7].acquire.ready := UInt<1>("h00") - inst T_5875 of LockingRRArbiter_35 - T_5875.out.ready := UInt<1>("h00") - T_5875.in[0].bits.union := UInt<1>("h00") - T_5875.in[0].bits.a_type := UInt<1>("h00") - T_5875.in[0].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[0].bits.data := UInt<1>("h00") - T_5875.in[0].bits.addr_beat := UInt<1>("h00") - T_5875.in[0].bits.client_xact_id := UInt<1>("h00") - T_5875.in[0].bits.addr_block := UInt<1>("h00") - T_5875.in[0].valid := UInt<1>("h00") - T_5875.in[1].bits.union := UInt<1>("h00") - T_5875.in[1].bits.a_type := UInt<1>("h00") - T_5875.in[1].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[1].bits.data := UInt<1>("h00") - T_5875.in[1].bits.addr_beat := UInt<1>("h00") - T_5875.in[1].bits.client_xact_id := UInt<1>("h00") - T_5875.in[1].bits.addr_block := UInt<1>("h00") - T_5875.in[1].valid := UInt<1>("h00") - T_5875.in[2].bits.union := UInt<1>("h00") - T_5875.in[2].bits.a_type := UInt<1>("h00") - T_5875.in[2].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[2].bits.data := UInt<1>("h00") - T_5875.in[2].bits.addr_beat := UInt<1>("h00") - T_5875.in[2].bits.client_xact_id := UInt<1>("h00") - T_5875.in[2].bits.addr_block := UInt<1>("h00") - T_5875.in[2].valid := UInt<1>("h00") - T_5875.in[3].bits.union := UInt<1>("h00") - T_5875.in[3].bits.a_type := UInt<1>("h00") - T_5875.in[3].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[3].bits.data := UInt<1>("h00") - T_5875.in[3].bits.addr_beat := UInt<1>("h00") - T_5875.in[3].bits.client_xact_id := UInt<1>("h00") - T_5875.in[3].bits.addr_block := UInt<1>("h00") - T_5875.in[3].valid := UInt<1>("h00") - T_5875.in[4].bits.union := UInt<1>("h00") - T_5875.in[4].bits.a_type := UInt<1>("h00") - T_5875.in[4].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[4].bits.data := UInt<1>("h00") - T_5875.in[4].bits.addr_beat := UInt<1>("h00") - T_5875.in[4].bits.client_xact_id := UInt<1>("h00") - T_5875.in[4].bits.addr_block := UInt<1>("h00") - T_5875.in[4].valid := UInt<1>("h00") - T_5875.in[5].bits.union := UInt<1>("h00") - T_5875.in[5].bits.a_type := UInt<1>("h00") - T_5875.in[5].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[5].bits.data := UInt<1>("h00") - T_5875.in[5].bits.addr_beat := UInt<1>("h00") - T_5875.in[5].bits.client_xact_id := UInt<1>("h00") - T_5875.in[5].bits.addr_block := UInt<1>("h00") - T_5875.in[5].valid := UInt<1>("h00") - T_5875.in[6].bits.union := UInt<1>("h00") - T_5875.in[6].bits.a_type := UInt<1>("h00") - T_5875.in[6].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[6].bits.data := UInt<1>("h00") - T_5875.in[6].bits.addr_beat := UInt<1>("h00") - T_5875.in[6].bits.client_xact_id := UInt<1>("h00") - T_5875.in[6].bits.addr_block := UInt<1>("h00") - T_5875.in[6].valid := UInt<1>("h00") - T_5875.in[7].bits.union := UInt<1>("h00") - T_5875.in[7].bits.a_type := UInt<1>("h00") - T_5875.in[7].bits.is_builtin_type := UInt<1>("h00") - T_5875.in[7].bits.data := UInt<1>("h00") - T_5875.in[7].bits.addr_beat := UInt<1>("h00") - T_5875.in[7].bits.client_xact_id := UInt<1>("h00") - T_5875.in[7].bits.addr_block := UInt<1>("h00") - T_5875.in[7].valid := UInt<1>("h00") - T_5875.reset := UInt<1>("h00") - T_5875.clock := clock - T_5875.reset := reset - T_5875.in[0].valid := in[0].acquire.valid - T_5875.in[0].bits <> in[0].acquire.bits - node T_5819 = cat(in[0].acquire.bits.client_xact_id, UInt<3>("h00")) - T_5875.in[0].bits.client_xact_id := T_5819 - in[0].acquire.ready := T_5875.in[0].ready - T_5875.in[1].valid := in[1].acquire.valid - T_5875.in[1].bits <> in[1].acquire.bits - node T_5821 = cat(in[1].acquire.bits.client_xact_id, UInt<3>("h01")) - T_5875.in[1].bits.client_xact_id := T_5821 - in[1].acquire.ready := T_5875.in[1].ready - T_5875.in[2].valid := in[2].acquire.valid - T_5875.in[2].bits <> in[2].acquire.bits - node T_5823 = cat(in[2].acquire.bits.client_xact_id, UInt<3>("h02")) - T_5875.in[2].bits.client_xact_id := T_5823 - in[2].acquire.ready := T_5875.in[2].ready - T_5875.in[3].valid := in[3].acquire.valid - T_5875.in[3].bits <> in[3].acquire.bits - node T_5825 = cat(in[3].acquire.bits.client_xact_id, UInt<3>("h03")) - T_5875.in[3].bits.client_xact_id := T_5825 - in[3].acquire.ready := T_5875.in[3].ready - T_5875.in[4].valid := in[4].acquire.valid - T_5875.in[4].bits <> in[4].acquire.bits - node T_5827 = cat(in[4].acquire.bits.client_xact_id, UInt<3>("h04")) - T_5875.in[4].bits.client_xact_id := T_5827 - in[4].acquire.ready := T_5875.in[4].ready - T_5875.in[5].valid := in[5].acquire.valid - T_5875.in[5].bits <> in[5].acquire.bits - node T_5829 = cat(in[5].acquire.bits.client_xact_id, UInt<3>("h05")) - T_5875.in[5].bits.client_xact_id := T_5829 - in[5].acquire.ready := T_5875.in[5].ready - T_5875.in[6].valid := in[6].acquire.valid - T_5875.in[6].bits <> in[6].acquire.bits - node T_5831 = cat(in[6].acquire.bits.client_xact_id, UInt<3>("h06")) - T_5875.in[6].bits.client_xact_id := T_5831 - in[6].acquire.ready := T_5875.in[6].ready - T_5875.in[7].valid := in[7].acquire.valid - T_5875.in[7].bits <> in[7].acquire.bits - node T_5833 = cat(in[7].acquire.bits.client_xact_id, UInt<3>("h07")) - T_5875.in[7].bits.client_xact_id := T_5833 - in[7].acquire.ready := T_5875.in[7].ready - out.acquire <> T_5875.out - out.grant.ready := UInt<1>("h00") - in[0].grant.valid := UInt<1>("h00") - node T_5836 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5838 = eq(T_5836, UInt<1>("h00")) - when T_5838 : - in[0].grant.valid := out.grant.valid - out.grant.ready := in[0].grant.ready - skip - in[0].grant.bits <> out.grant.bits - node T_5839 = shr(out.grant.bits.client_xact_id, 3) - in[0].grant.bits.client_xact_id := T_5839 - in[1].grant.valid := UInt<1>("h00") - node T_5841 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5843 = eq(T_5841, UInt<1>("h01")) - when T_5843 : - in[1].grant.valid := out.grant.valid - out.grant.ready := in[1].grant.ready - skip - in[1].grant.bits <> out.grant.bits - node T_5844 = shr(out.grant.bits.client_xact_id, 3) - in[1].grant.bits.client_xact_id := T_5844 - in[2].grant.valid := UInt<1>("h00") - node T_5846 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5848 = eq(T_5846, UInt<2>("h02")) - when T_5848 : - in[2].grant.valid := out.grant.valid - out.grant.ready := in[2].grant.ready - skip - in[2].grant.bits <> out.grant.bits - node T_5849 = shr(out.grant.bits.client_xact_id, 3) - in[2].grant.bits.client_xact_id := T_5849 - in[3].grant.valid := UInt<1>("h00") - node T_5851 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5853 = eq(T_5851, UInt<2>("h03")) - when T_5853 : - in[3].grant.valid := out.grant.valid - out.grant.ready := in[3].grant.ready - skip - in[3].grant.bits <> out.grant.bits - node T_5854 = shr(out.grant.bits.client_xact_id, 3) - in[3].grant.bits.client_xact_id := T_5854 - in[4].grant.valid := UInt<1>("h00") - node T_5856 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5858 = eq(T_5856, UInt<3>("h04")) - when T_5858 : - in[4].grant.valid := out.grant.valid - out.grant.ready := in[4].grant.ready - skip - in[4].grant.bits <> out.grant.bits - node T_5859 = shr(out.grant.bits.client_xact_id, 3) - in[4].grant.bits.client_xact_id := T_5859 - in[5].grant.valid := UInt<1>("h00") - node T_5861 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5863 = eq(T_5861, UInt<3>("h05")) - when T_5863 : - in[5].grant.valid := out.grant.valid - out.grant.ready := in[5].grant.ready - skip - in[5].grant.bits <> out.grant.bits - node T_5864 = shr(out.grant.bits.client_xact_id, 3) - in[5].grant.bits.client_xact_id := T_5864 - in[6].grant.valid := UInt<1>("h00") - node T_5866 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5868 = eq(T_5866, UInt<3>("h06")) - when T_5868 : - in[6].grant.valid := out.grant.valid - out.grant.ready := in[6].grant.ready - skip - in[6].grant.bits <> out.grant.bits - node T_5869 = shr(out.grant.bits.client_xact_id, 3) - in[6].grant.bits.client_xact_id := T_5869 - in[7].grant.valid := UInt<1>("h00") - node T_5871 = bits(out.grant.bits.client_xact_id, 2, 0) - node T_5873 = eq(T_5871, UInt<3>("h07")) - when T_5873 : - in[7].grant.valid := out.grant.valid - out.grant.ready := in[7].grant.ready - skip - in[7].grant.bits <> out.grant.bits - node T_5874 = shr(out.grant.bits.client_xact_id, 3) - in[7].grant.bits.client_xact_id := T_5874 - - module L2BroadcastHub : - output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input incoherent : UInt<1>[1] - output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} - input clock : Clock - input reset : UInt<1> - - outer.grant.ready := UInt<1>("h00") - outer.acquire.bits.union := UInt<1>("h00") - outer.acquire.bits.a_type := UInt<1>("h00") - outer.acquire.bits.is_builtin_type := UInt<1>("h00") - outer.acquire.bits.data := UInt<1>("h00") - outer.acquire.bits.addr_beat := UInt<1>("h00") - outer.acquire.bits.client_xact_id := UInt<1>("h00") - outer.acquire.bits.addr_block := UInt<1>("h00") - outer.acquire.valid := UInt<1>("h00") - inner.release.ready := UInt<1>("h00") - inner.probe.bits.client_id := UInt<1>("h00") - inner.probe.bits.p_type := UInt<1>("h00") - inner.probe.bits.addr_block := UInt<1>("h00") - inner.probe.valid := UInt<1>("h00") - inner.finish.ready := UInt<1>("h00") - inner.grant.bits.client_id := UInt<1>("h00") - inner.grant.bits.g_type := UInt<1>("h00") - inner.grant.bits.is_builtin_type := UInt<1>("h00") - inner.grant.bits.manager_xact_id := UInt<1>("h00") - inner.grant.bits.client_xact_id := UInt<1>("h00") - inner.grant.bits.data := UInt<1>("h00") - inner.grant.bits.addr_beat := UInt<1>("h00") - inner.grant.valid := UInt<1>("h00") - inner.acquire.ready := UInt<1>("h00") - inst T_2011 of BroadcastVoluntaryReleaseTracker - T_2011.outer.grant.bits.g_type := UInt<1>("h00") - T_2011.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2011.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2011.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2011.outer.grant.bits.data := UInt<1>("h00") - T_2011.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2011.outer.grant.valid := UInt<1>("h00") - T_2011.outer.acquire.ready := UInt<1>("h00") - T_2011.incoherent[0] := UInt<1>("h00") - T_2011.inner.release.bits.client_id := UInt<1>("h00") - T_2011.inner.release.bits.voluntary := UInt<1>("h00") - T_2011.inner.release.bits.r_type := UInt<1>("h00") - T_2011.inner.release.bits.data := UInt<1>("h00") - T_2011.inner.release.bits.addr_beat := UInt<1>("h00") - T_2011.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2011.inner.release.bits.addr_block := UInt<1>("h00") - T_2011.inner.release.valid := UInt<1>("h00") - T_2011.inner.probe.ready := UInt<1>("h00") - T_2011.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2011.inner.finish.valid := UInt<1>("h00") - T_2011.inner.grant.ready := UInt<1>("h00") - T_2011.inner.acquire.bits.client_id := UInt<1>("h00") - T_2011.inner.acquire.bits.union := UInt<1>("h00") - T_2011.inner.acquire.bits.a_type := UInt<1>("h00") - T_2011.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2011.inner.acquire.bits.data := UInt<1>("h00") - T_2011.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2011.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2011.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2011.inner.acquire.valid := UInt<1>("h00") - T_2011.reset := UInt<1>("h00") - T_2011.clock := clock - T_2011.reset := reset - inst T_2012 of BroadcastAcquireTracker - T_2012.outer.grant.bits.g_type := UInt<1>("h00") - T_2012.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2012.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2012.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2012.outer.grant.bits.data := UInt<1>("h00") - T_2012.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2012.outer.grant.valid := UInt<1>("h00") - T_2012.outer.acquire.ready := UInt<1>("h00") - T_2012.incoherent[0] := UInt<1>("h00") - T_2012.inner.release.bits.client_id := UInt<1>("h00") - T_2012.inner.release.bits.voluntary := UInt<1>("h00") - T_2012.inner.release.bits.r_type := UInt<1>("h00") - T_2012.inner.release.bits.data := UInt<1>("h00") - T_2012.inner.release.bits.addr_beat := UInt<1>("h00") - T_2012.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2012.inner.release.bits.addr_block := UInt<1>("h00") - T_2012.inner.release.valid := UInt<1>("h00") - T_2012.inner.probe.ready := UInt<1>("h00") - T_2012.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2012.inner.finish.valid := UInt<1>("h00") - T_2012.inner.grant.ready := UInt<1>("h00") - T_2012.inner.acquire.bits.client_id := UInt<1>("h00") - T_2012.inner.acquire.bits.union := UInt<1>("h00") - T_2012.inner.acquire.bits.a_type := UInt<1>("h00") - T_2012.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2012.inner.acquire.bits.data := UInt<1>("h00") - T_2012.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2012.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2012.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2012.inner.acquire.valid := UInt<1>("h00") - T_2012.reset := UInt<1>("h00") - T_2012.clock := clock - T_2012.reset := reset - inst T_2013 of BroadcastAcquireTracker_27 - T_2013.outer.grant.bits.g_type := UInt<1>("h00") - T_2013.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2013.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2013.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2013.outer.grant.bits.data := UInt<1>("h00") - T_2013.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2013.outer.grant.valid := UInt<1>("h00") - T_2013.outer.acquire.ready := UInt<1>("h00") - T_2013.incoherent[0] := UInt<1>("h00") - T_2013.inner.release.bits.client_id := UInt<1>("h00") - T_2013.inner.release.bits.voluntary := UInt<1>("h00") - T_2013.inner.release.bits.r_type := UInt<1>("h00") - T_2013.inner.release.bits.data := UInt<1>("h00") - T_2013.inner.release.bits.addr_beat := UInt<1>("h00") - T_2013.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2013.inner.release.bits.addr_block := UInt<1>("h00") - T_2013.inner.release.valid := UInt<1>("h00") - T_2013.inner.probe.ready := UInt<1>("h00") - T_2013.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2013.inner.finish.valid := UInt<1>("h00") - T_2013.inner.grant.ready := UInt<1>("h00") - T_2013.inner.acquire.bits.client_id := UInt<1>("h00") - T_2013.inner.acquire.bits.union := UInt<1>("h00") - T_2013.inner.acquire.bits.a_type := UInt<1>("h00") - T_2013.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2013.inner.acquire.bits.data := UInt<1>("h00") - T_2013.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2013.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2013.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2013.inner.acquire.valid := UInt<1>("h00") - T_2013.reset := UInt<1>("h00") - T_2013.clock := clock - T_2013.reset := reset - inst T_2014 of BroadcastAcquireTracker_28 - T_2014.outer.grant.bits.g_type := UInt<1>("h00") - T_2014.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2014.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2014.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2014.outer.grant.bits.data := UInt<1>("h00") - T_2014.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2014.outer.grant.valid := UInt<1>("h00") - T_2014.outer.acquire.ready := UInt<1>("h00") - T_2014.incoherent[0] := UInt<1>("h00") - T_2014.inner.release.bits.client_id := UInt<1>("h00") - T_2014.inner.release.bits.voluntary := UInt<1>("h00") - T_2014.inner.release.bits.r_type := UInt<1>("h00") - T_2014.inner.release.bits.data := UInt<1>("h00") - T_2014.inner.release.bits.addr_beat := UInt<1>("h00") - T_2014.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2014.inner.release.bits.addr_block := UInt<1>("h00") - T_2014.inner.release.valid := UInt<1>("h00") - T_2014.inner.probe.ready := UInt<1>("h00") - T_2014.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2014.inner.finish.valid := UInt<1>("h00") - T_2014.inner.grant.ready := UInt<1>("h00") - T_2014.inner.acquire.bits.client_id := UInt<1>("h00") - T_2014.inner.acquire.bits.union := UInt<1>("h00") - T_2014.inner.acquire.bits.a_type := UInt<1>("h00") - T_2014.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2014.inner.acquire.bits.data := UInt<1>("h00") - T_2014.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2014.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2014.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2014.inner.acquire.valid := UInt<1>("h00") - T_2014.reset := UInt<1>("h00") - T_2014.clock := clock - T_2014.reset := reset - inst T_2015 of BroadcastAcquireTracker_29 - T_2015.outer.grant.bits.g_type := UInt<1>("h00") - T_2015.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2015.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2015.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2015.outer.grant.bits.data := UInt<1>("h00") - T_2015.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2015.outer.grant.valid := UInt<1>("h00") - T_2015.outer.acquire.ready := UInt<1>("h00") - T_2015.incoherent[0] := UInt<1>("h00") - T_2015.inner.release.bits.client_id := UInt<1>("h00") - T_2015.inner.release.bits.voluntary := UInt<1>("h00") - T_2015.inner.release.bits.r_type := UInt<1>("h00") - T_2015.inner.release.bits.data := UInt<1>("h00") - T_2015.inner.release.bits.addr_beat := UInt<1>("h00") - T_2015.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2015.inner.release.bits.addr_block := UInt<1>("h00") - T_2015.inner.release.valid := UInt<1>("h00") - T_2015.inner.probe.ready := UInt<1>("h00") - T_2015.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2015.inner.finish.valid := UInt<1>("h00") - T_2015.inner.grant.ready := UInt<1>("h00") - T_2015.inner.acquire.bits.client_id := UInt<1>("h00") - T_2015.inner.acquire.bits.union := UInt<1>("h00") - T_2015.inner.acquire.bits.a_type := UInt<1>("h00") - T_2015.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2015.inner.acquire.bits.data := UInt<1>("h00") - T_2015.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2015.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2015.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2015.inner.acquire.valid := UInt<1>("h00") - T_2015.reset := UInt<1>("h00") - T_2015.clock := clock - T_2015.reset := reset - inst T_2016 of BroadcastAcquireTracker_30 - T_2016.outer.grant.bits.g_type := UInt<1>("h00") - T_2016.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2016.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2016.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2016.outer.grant.bits.data := UInt<1>("h00") - T_2016.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2016.outer.grant.valid := UInt<1>("h00") - T_2016.outer.acquire.ready := UInt<1>("h00") - T_2016.incoherent[0] := UInt<1>("h00") - T_2016.inner.release.bits.client_id := UInt<1>("h00") - T_2016.inner.release.bits.voluntary := UInt<1>("h00") - T_2016.inner.release.bits.r_type := UInt<1>("h00") - T_2016.inner.release.bits.data := UInt<1>("h00") - T_2016.inner.release.bits.addr_beat := UInt<1>("h00") - T_2016.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2016.inner.release.bits.addr_block := UInt<1>("h00") - T_2016.inner.release.valid := UInt<1>("h00") - T_2016.inner.probe.ready := UInt<1>("h00") - T_2016.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2016.inner.finish.valid := UInt<1>("h00") - T_2016.inner.grant.ready := UInt<1>("h00") - T_2016.inner.acquire.bits.client_id := UInt<1>("h00") - T_2016.inner.acquire.bits.union := UInt<1>("h00") - T_2016.inner.acquire.bits.a_type := UInt<1>("h00") - T_2016.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2016.inner.acquire.bits.data := UInt<1>("h00") - T_2016.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2016.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2016.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2016.inner.acquire.valid := UInt<1>("h00") - T_2016.reset := UInt<1>("h00") - T_2016.clock := clock - T_2016.reset := reset - inst T_2017 of BroadcastAcquireTracker_31 - T_2017.outer.grant.bits.g_type := UInt<1>("h00") - T_2017.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2017.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2017.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2017.outer.grant.bits.data := UInt<1>("h00") - T_2017.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2017.outer.grant.valid := UInt<1>("h00") - T_2017.outer.acquire.ready := UInt<1>("h00") - T_2017.incoherent[0] := UInt<1>("h00") - T_2017.inner.release.bits.client_id := UInt<1>("h00") - T_2017.inner.release.bits.voluntary := UInt<1>("h00") - T_2017.inner.release.bits.r_type := UInt<1>("h00") - T_2017.inner.release.bits.data := UInt<1>("h00") - T_2017.inner.release.bits.addr_beat := UInt<1>("h00") - T_2017.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2017.inner.release.bits.addr_block := UInt<1>("h00") - T_2017.inner.release.valid := UInt<1>("h00") - T_2017.inner.probe.ready := UInt<1>("h00") - T_2017.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2017.inner.finish.valid := UInt<1>("h00") - T_2017.inner.grant.ready := UInt<1>("h00") - T_2017.inner.acquire.bits.client_id := UInt<1>("h00") - T_2017.inner.acquire.bits.union := UInt<1>("h00") - T_2017.inner.acquire.bits.a_type := UInt<1>("h00") - T_2017.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2017.inner.acquire.bits.data := UInt<1>("h00") - T_2017.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2017.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2017.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2017.inner.acquire.valid := UInt<1>("h00") - T_2017.reset := UInt<1>("h00") - T_2017.clock := clock - T_2017.reset := reset - inst T_2018 of BroadcastAcquireTracker_32 - T_2018.outer.grant.bits.g_type := UInt<1>("h00") - T_2018.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_2018.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_2018.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_2018.outer.grant.bits.data := UInt<1>("h00") - T_2018.outer.grant.bits.addr_beat := UInt<1>("h00") - T_2018.outer.grant.valid := UInt<1>("h00") - T_2018.outer.acquire.ready := UInt<1>("h00") - T_2018.incoherent[0] := UInt<1>("h00") - T_2018.inner.release.bits.client_id := UInt<1>("h00") - T_2018.inner.release.bits.voluntary := UInt<1>("h00") - T_2018.inner.release.bits.r_type := UInt<1>("h00") - T_2018.inner.release.bits.data := UInt<1>("h00") - T_2018.inner.release.bits.addr_beat := UInt<1>("h00") - T_2018.inner.release.bits.client_xact_id := UInt<1>("h00") - T_2018.inner.release.bits.addr_block := UInt<1>("h00") - T_2018.inner.release.valid := UInt<1>("h00") - T_2018.inner.probe.ready := UInt<1>("h00") - T_2018.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_2018.inner.finish.valid := UInt<1>("h00") - T_2018.inner.grant.ready := UInt<1>("h00") - T_2018.inner.acquire.bits.client_id := UInt<1>("h00") - T_2018.inner.acquire.bits.union := UInt<1>("h00") - T_2018.inner.acquire.bits.a_type := UInt<1>("h00") - T_2018.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_2018.inner.acquire.bits.data := UInt<1>("h00") - T_2018.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_2018.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_2018.inner.acquire.bits.addr_block := UInt<1>("h00") - T_2018.inner.acquire.valid := UInt<1>("h00") - T_2018.reset := UInt<1>("h00") - T_2018.clock := clock - T_2018.reset := reset - T_2011.incoherent := incoherent - T_2012.incoherent := incoherent - T_2013.incoherent := incoherent - T_2014.incoherent := incoherent - T_2015.incoherent := incoherent - T_2016.incoherent := incoherent - T_2017.incoherent := incoherent - T_2018.incoherent := incoherent - reg sdq : UInt<128>[4], clock, reset - reg sdq_val : UInt<4>, clock, reset - onreset sdq_val := UInt<4>("h00") - node T_1196 = not(sdq_val) - node T_1197 = bit(T_1196, 0) - node T_1198 = bit(T_1196, 1) - node T_1199 = bit(T_1196, 2) - node T_1200 = bit(T_1196, 3) - wire T_1202 : UInt<1>[4] - T_1202[0] := T_1197 - T_1202[1] := T_1198 - T_1202[2] := T_1199 - T_1202[3] := T_1200 - node T_1212 = mux(T_1202[2], UInt<2>("h02"), UInt<2>("h03")) - node T_1213 = mux(T_1202[1], UInt<1>("h01"), T_1212) - node sdq_alloc_id = mux(T_1202[0], UInt<1>("h00"), T_1213) - node T_1215 = not(sdq_val) - node T_1217 = eq(T_1215, UInt<1>("h00")) - node sdq_rdy = eq(T_1217, UInt<1>("h00")) - node T_1220 = and(inner.acquire.ready, inner.acquire.valid) - wire T_1225 : UInt<3>[3] - T_1225[0] := UInt<3>("h02") - T_1225[1] := UInt<3>("h03") - T_1225[2] := UInt<3>("h04") - node T_1230 = eq(T_1225[0], inner.acquire.bits.a_type) - node T_1231 = eq(T_1225[1], inner.acquire.bits.a_type) - node T_1232 = eq(T_1225[2], inner.acquire.bits.a_type) - node T_1234 = or(UInt<1>("h00"), T_1230) - node T_1235 = or(T_1234, T_1231) - node T_1236 = or(T_1235, T_1232) - node T_1237 = and(inner.acquire.bits.is_builtin_type, T_1236) - node sdq_enq = and(T_1220, T_1237) - when sdq_enq : - infer accessor T_1239 = sdq[sdq_alloc_id] - T_1239 := inner.acquire.bits.data - skip - wire T_1241 : UInt<1>[8] - T_1241[0] := T_2011.has_acquire_conflict - T_1241[1] := T_2012.has_acquire_conflict - T_1241[2] := T_2013.has_acquire_conflict - T_1241[3] := T_2014.has_acquire_conflict - T_1241[4] := T_2015.has_acquire_conflict - T_1241[5] := T_2016.has_acquire_conflict - T_1241[6] := T_2017.has_acquire_conflict - T_1241[7] := T_2018.has_acquire_conflict - node T_1251 = cat(T_1241[7], T_1241[6]) - node T_1252 = cat(T_1241[5], T_1241[4]) - node T_1253 = cat(T_1251, T_1252) - node T_1254 = cat(T_1241[3], T_1241[2]) - node T_1255 = cat(T_1241[1], T_1241[0]) - node T_1256 = cat(T_1254, T_1255) - node acquireConflicts = cat(T_1253, T_1256) - wire T_1259 : UInt<1>[8] - T_1259[0] := T_2011.has_acquire_match - T_1259[1] := T_2012.has_acquire_match - T_1259[2] := T_2013.has_acquire_match - T_1259[3] := T_2014.has_acquire_match - T_1259[4] := T_2015.has_acquire_match - T_1259[5] := T_2016.has_acquire_match - T_1259[6] := T_2017.has_acquire_match - T_1259[7] := T_2018.has_acquire_match - node T_1269 = cat(T_1259[7], T_1259[6]) - node T_1270 = cat(T_1259[5], T_1259[4]) - node T_1271 = cat(T_1269, T_1270) - node T_1272 = cat(T_1259[3], T_1259[2]) - node T_1273 = cat(T_1259[1], T_1259[0]) - node T_1274 = cat(T_1272, T_1273) - node acquireMatches = cat(T_1271, T_1274) - wire T_1277 : UInt<1>[8] - T_1277[0] := T_2011.inner.acquire.ready - T_1277[1] := T_2012.inner.acquire.ready - T_1277[2] := T_2013.inner.acquire.ready - T_1277[3] := T_2014.inner.acquire.ready - T_1277[4] := T_2015.inner.acquire.ready - T_1277[5] := T_2016.inner.acquire.ready - T_1277[6] := T_2017.inner.acquire.ready - T_1277[7] := T_2018.inner.acquire.ready - node T_1287 = cat(T_1277[7], T_1277[6]) - node T_1288 = cat(T_1277[5], T_1277[4]) - node T_1289 = cat(T_1287, T_1288) - node T_1290 = cat(T_1277[3], T_1277[2]) - node T_1291 = cat(T_1277[1], T_1277[0]) - node T_1292 = cat(T_1290, T_1291) - node acquireReadys = cat(T_1289, T_1292) - node T_1295 = neq(acquireMatches, UInt<1>("h00")) - node T_1296 = bit(acquireMatches, 0) - node T_1297 = bit(acquireMatches, 1) - node T_1298 = bit(acquireMatches, 2) - node T_1299 = bit(acquireMatches, 3) - node T_1300 = bit(acquireMatches, 4) - node T_1301 = bit(acquireMatches, 5) - node T_1302 = bit(acquireMatches, 6) - node T_1303 = bit(acquireMatches, 7) - wire T_1305 : UInt<1>[8] - T_1305[0] := T_1296 - T_1305[1] := T_1297 - T_1305[2] := T_1298 - T_1305[3] := T_1299 - T_1305[4] := T_1300 - T_1305[5] := T_1301 - T_1305[6] := T_1302 - T_1305[7] := T_1303 - node T_1323 = mux(T_1305[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1324 = mux(T_1305[5], UInt<3>("h05"), T_1323) - node T_1325 = mux(T_1305[4], UInt<3>("h04"), T_1324) - node T_1326 = mux(T_1305[3], UInt<2>("h03"), T_1325) - node T_1327 = mux(T_1305[2], UInt<2>("h02"), T_1326) - node T_1328 = mux(T_1305[1], UInt<1>("h01"), T_1327) - node T_1329 = mux(T_1305[0], UInt<1>("h00"), T_1328) - node T_1330 = bit(acquireReadys, 0) - node T_1331 = bit(acquireReadys, 1) - node T_1332 = bit(acquireReadys, 2) - node T_1333 = bit(acquireReadys, 3) - node T_1334 = bit(acquireReadys, 4) - node T_1335 = bit(acquireReadys, 5) - node T_1336 = bit(acquireReadys, 6) - node T_1337 = bit(acquireReadys, 7) - wire T_1339 : UInt<1>[8] - T_1339[0] := T_1330 - T_1339[1] := T_1331 - T_1339[2] := T_1332 - T_1339[3] := T_1333 - T_1339[4] := T_1334 - T_1339[5] := T_1335 - T_1339[6] := T_1336 - T_1339[7] := T_1337 - node T_1357 = mux(T_1339[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1358 = mux(T_1339[5], UInt<3>("h05"), T_1357) - node T_1359 = mux(T_1339[4], UInt<3>("h04"), T_1358) - node T_1360 = mux(T_1339[3], UInt<2>("h03"), T_1359) - node T_1361 = mux(T_1339[2], UInt<2>("h02"), T_1360) - node T_1362 = mux(T_1339[1], UInt<1>("h01"), T_1361) - node T_1363 = mux(T_1339[0], UInt<1>("h00"), T_1362) - node acquire_idx = mux(T_1295, T_1329, T_1363) - node T_1366 = neq(acquireConflicts, UInt<1>("h00")) - node T_1368 = eq(sdq_rdy, UInt<1>("h00")) - node block_acquires = or(T_1366, T_1368) - node T_1371 = neq(acquireReadys, UInt<1>("h00")) - node T_1373 = eq(block_acquires, UInt<1>("h00")) - node T_1374 = and(T_1371, T_1373) - inner.acquire.ready := T_1374 - T_2011.inner.acquire.bits <> inner.acquire.bits - wire T_1378 : {idx : UInt<2>, loc : UInt<2>} - T_1378.loc := UInt<1>("h00") - T_1378.idx := UInt<1>("h00") - T_1378.idx := sdq_alloc_id - T_1378.loc := UInt<1>("h00") - node T_1383 = cat(T_1378.idx, T_1378.loc) - T_2011.inner.acquire.bits.data := T_1383 - node T_1385 = eq(block_acquires, UInt<1>("h00")) - node T_1386 = and(inner.acquire.valid, T_1385) - node T_1388 = eq(acquire_idx, UInt<1>("h00")) - node T_1389 = and(T_1386, T_1388) - T_2011.inner.acquire.valid := T_1389 - T_2012.inner.acquire.bits <> inner.acquire.bits - wire T_1393 : {idx : UInt<2>, loc : UInt<2>} - T_1393.loc := UInt<1>("h00") - T_1393.idx := UInt<1>("h00") - T_1393.idx := sdq_alloc_id - T_1393.loc := UInt<1>("h00") - node T_1398 = cat(T_1393.idx, T_1393.loc) - T_2012.inner.acquire.bits.data := T_1398 - node T_1400 = eq(block_acquires, UInt<1>("h00")) - node T_1401 = and(inner.acquire.valid, T_1400) - node T_1403 = eq(acquire_idx, UInt<1>("h01")) - node T_1404 = and(T_1401, T_1403) - T_2012.inner.acquire.valid := T_1404 - T_2013.inner.acquire.bits <> inner.acquire.bits - wire T_1408 : {idx : UInt<2>, loc : UInt<2>} - T_1408.loc := UInt<1>("h00") - T_1408.idx := UInt<1>("h00") - T_1408.idx := sdq_alloc_id - T_1408.loc := UInt<1>("h00") - node T_1413 = cat(T_1408.idx, T_1408.loc) - T_2013.inner.acquire.bits.data := T_1413 - node T_1415 = eq(block_acquires, UInt<1>("h00")) - node T_1416 = and(inner.acquire.valid, T_1415) - node T_1418 = eq(acquire_idx, UInt<2>("h02")) - node T_1419 = and(T_1416, T_1418) - T_2013.inner.acquire.valid := T_1419 - T_2014.inner.acquire.bits <> inner.acquire.bits - wire T_1423 : {idx : UInt<2>, loc : UInt<2>} - T_1423.loc := UInt<1>("h00") - T_1423.idx := UInt<1>("h00") - T_1423.idx := sdq_alloc_id - T_1423.loc := UInt<1>("h00") - node T_1428 = cat(T_1423.idx, T_1423.loc) - T_2014.inner.acquire.bits.data := T_1428 - node T_1430 = eq(block_acquires, UInt<1>("h00")) - node T_1431 = and(inner.acquire.valid, T_1430) - node T_1433 = eq(acquire_idx, UInt<2>("h03")) - node T_1434 = and(T_1431, T_1433) - T_2014.inner.acquire.valid := T_1434 - T_2015.inner.acquire.bits <> inner.acquire.bits - wire T_1438 : {idx : UInt<2>, loc : UInt<2>} - T_1438.loc := UInt<1>("h00") - T_1438.idx := UInt<1>("h00") - T_1438.idx := sdq_alloc_id - T_1438.loc := UInt<1>("h00") - node T_1443 = cat(T_1438.idx, T_1438.loc) - T_2015.inner.acquire.bits.data := T_1443 - node T_1445 = eq(block_acquires, UInt<1>("h00")) - node T_1446 = and(inner.acquire.valid, T_1445) - node T_1448 = eq(acquire_idx, UInt<3>("h04")) - node T_1449 = and(T_1446, T_1448) - T_2015.inner.acquire.valid := T_1449 - T_2016.inner.acquire.bits <> inner.acquire.bits - wire T_1453 : {idx : UInt<2>, loc : UInt<2>} - T_1453.loc := UInt<1>("h00") - T_1453.idx := UInt<1>("h00") - T_1453.idx := sdq_alloc_id - T_1453.loc := UInt<1>("h00") - node T_1458 = cat(T_1453.idx, T_1453.loc) - T_2016.inner.acquire.bits.data := T_1458 - node T_1460 = eq(block_acquires, UInt<1>("h00")) - node T_1461 = and(inner.acquire.valid, T_1460) - node T_1463 = eq(acquire_idx, UInt<3>("h05")) - node T_1464 = and(T_1461, T_1463) - T_2016.inner.acquire.valid := T_1464 - T_2017.inner.acquire.bits <> inner.acquire.bits - wire T_1468 : {idx : UInt<2>, loc : UInt<2>} - T_1468.loc := UInt<1>("h00") - T_1468.idx := UInt<1>("h00") - T_1468.idx := sdq_alloc_id - T_1468.loc := UInt<1>("h00") - node T_1473 = cat(T_1468.idx, T_1468.loc) - T_2017.inner.acquire.bits.data := T_1473 - node T_1475 = eq(block_acquires, UInt<1>("h00")) - node T_1476 = and(inner.acquire.valid, T_1475) - node T_1478 = eq(acquire_idx, UInt<3>("h06")) - node T_1479 = and(T_1476, T_1478) - T_2017.inner.acquire.valid := T_1479 - T_2018.inner.acquire.bits <> inner.acquire.bits - wire T_1483 : {idx : UInt<2>, loc : UInt<2>} - T_1483.loc := UInt<1>("h00") - T_1483.idx := UInt<1>("h00") - T_1483.idx := sdq_alloc_id - T_1483.loc := UInt<1>("h00") - node T_1488 = cat(T_1483.idx, T_1483.loc) - T_2018.inner.acquire.bits.data := T_1488 - node T_1490 = eq(block_acquires, UInt<1>("h00")) - node T_1491 = and(inner.acquire.valid, T_1490) - node T_1493 = eq(acquire_idx, UInt<3>("h07")) - node T_1494 = and(T_1491, T_1493) - T_2018.inner.acquire.valid := T_1494 - node T_1495 = and(inner.release.ready, inner.release.valid) - node T_1496 = and(T_1495, inner.release.bits.voluntary) - wire T_1498 : UInt<2>[3] - T_1498[0] := UInt<1>("h00") - T_1498[1] := UInt<1>("h01") - T_1498[2] := UInt<2>("h02") - node T_1503 = eq(T_1498[0], inner.release.bits.r_type) - node T_1504 = eq(T_1498[1], inner.release.bits.r_type) - node T_1505 = eq(T_1498[2], inner.release.bits.r_type) - node T_1507 = or(UInt<1>("h00"), T_1503) - node T_1508 = or(T_1507, T_1504) - node T_1509 = or(T_1508, T_1505) - node vwbdq_enq = and(T_1496, T_1509) - reg rel_data_cnt : UInt<2>, clock, reset - onreset rel_data_cnt := UInt<2>("h00") - when vwbdq_enq : - node T_1514 = eq(rel_data_cnt, UInt<2>("h03")) - node T_1516 = and(UInt<1>("h00"), T_1514) - node T_1519 = addw(rel_data_cnt, UInt<1>("h01")) - node T_1520 = mux(T_1516, UInt<1>("h00"), T_1519) - rel_data_cnt := T_1520 - skip - node rel_data_done = and(vwbdq_enq, T_1514) - reg vwbdq : UInt<128>[4], clock, reset - when vwbdq_enq : - infer accessor T_1537 = vwbdq[rel_data_cnt] - T_1537 := inner.release.bits.data - skip - wire T_1539 : UInt<1>[8] - T_1539[0] := T_2011.inner.release.ready - T_1539[1] := T_2012.inner.release.ready - T_1539[2] := T_2013.inner.release.ready - T_1539[3] := T_2014.inner.release.ready - T_1539[4] := T_2015.inner.release.ready - T_1539[5] := T_2016.inner.release.ready - T_1539[6] := T_2017.inner.release.ready - T_1539[7] := T_2018.inner.release.ready - node T_1549 = cat(T_1539[7], T_1539[6]) - node T_1550 = cat(T_1539[5], T_1539[4]) - node T_1551 = cat(T_1549, T_1550) - node T_1552 = cat(T_1539[3], T_1539[2]) - node T_1553 = cat(T_1539[1], T_1539[0]) - node T_1554 = cat(T_1552, T_1553) - node releaseReadys = cat(T_1551, T_1554) - wire T_1557 : UInt<1>[8] - T_1557[0] := T_2011.has_release_match - T_1557[1] := T_2012.has_release_match - T_1557[2] := T_2013.has_release_match - T_1557[3] := T_2014.has_release_match - T_1557[4] := T_2015.has_release_match - T_1557[5] := T_2016.has_release_match - T_1557[6] := T_2017.has_release_match - T_1557[7] := T_2018.has_release_match - node T_1567 = cat(T_1557[7], T_1557[6]) - node T_1568 = cat(T_1557[5], T_1557[4]) - node T_1569 = cat(T_1567, T_1568) - node T_1570 = cat(T_1557[3], T_1557[2]) - node T_1571 = cat(T_1557[1], T_1557[0]) - node T_1572 = cat(T_1570, T_1571) - node releaseMatches = cat(T_1569, T_1572) - node T_1574 = bit(releaseMatches, 0) - node T_1575 = bit(releaseMatches, 1) - node T_1576 = bit(releaseMatches, 2) - node T_1577 = bit(releaseMatches, 3) - node T_1578 = bit(releaseMatches, 4) - node T_1579 = bit(releaseMatches, 5) - node T_1580 = bit(releaseMatches, 6) - node T_1581 = bit(releaseMatches, 7) - wire T_1583 : UInt<1>[8] - T_1583[0] := T_1574 - T_1583[1] := T_1575 - T_1583[2] := T_1576 - T_1583[3] := T_1577 - T_1583[4] := T_1578 - T_1583[5] := T_1579 - T_1583[6] := T_1580 - T_1583[7] := T_1581 - node T_1601 = mux(T_1583[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1602 = mux(T_1583[5], UInt<3>("h05"), T_1601) - node T_1603 = mux(T_1583[4], UInt<3>("h04"), T_1602) - node T_1604 = mux(T_1583[3], UInt<2>("h03"), T_1603) - node T_1605 = mux(T_1583[2], UInt<2>("h02"), T_1604) - node T_1606 = mux(T_1583[1], UInt<1>("h01"), T_1605) - node release_idx = mux(T_1583[0], UInt<1>("h00"), T_1606) - node T_1608 = dshr(releaseReadys, release_idx) - node T_1609 = bit(T_1608, 0) - inner.release.ready := T_1609 - node T_1611 = eq(release_idx, UInt<1>("h00")) - node T_1612 = and(inner.release.valid, T_1611) - T_2011.inner.release.valid := T_1612 - T_2011.inner.release.bits <> inner.release.bits - wire T_1616 : {idx : UInt<2>, loc : UInt<2>} - T_1616.loc := UInt<1>("h00") - T_1616.idx := UInt<1>("h00") - T_1616.idx := rel_data_cnt - T_1616.loc := UInt<1>("h01") - node T_1621 = cat(T_1616.idx, T_1616.loc) - T_2011.inner.release.bits.data := T_1621 - node T_1623 = eq(release_idx, UInt<1>("h01")) - node T_1624 = and(inner.release.valid, T_1623) - T_2012.inner.release.valid := T_1624 - T_2012.inner.release.bits <> inner.release.bits - wire T_1628 : {idx : UInt<2>, loc : UInt<2>} - T_1628.loc := UInt<1>("h00") - T_1628.idx := UInt<1>("h00") - T_1628.idx := rel_data_cnt - T_1628.loc := UInt<2>("h02") - node T_1633 = cat(T_1628.idx, T_1628.loc) - T_2012.inner.release.bits.data := T_1633 - node T_1635 = eq(release_idx, UInt<2>("h02")) - node T_1636 = and(inner.release.valid, T_1635) - T_2013.inner.release.valid := T_1636 - T_2013.inner.release.bits <> inner.release.bits - wire T_1640 : {idx : UInt<2>, loc : UInt<2>} - T_1640.loc := UInt<1>("h00") - T_1640.idx := UInt<1>("h00") - T_1640.idx := rel_data_cnt - T_1640.loc := UInt<2>("h02") - node T_1645 = cat(T_1640.idx, T_1640.loc) - T_2013.inner.release.bits.data := T_1645 - node T_1647 = eq(release_idx, UInt<2>("h03")) - node T_1648 = and(inner.release.valid, T_1647) - T_2014.inner.release.valid := T_1648 - T_2014.inner.release.bits <> inner.release.bits - wire T_1652 : {idx : UInt<2>, loc : UInt<2>} - T_1652.loc := UInt<1>("h00") - T_1652.idx := UInt<1>("h00") - T_1652.idx := rel_data_cnt - T_1652.loc := UInt<2>("h02") - node T_1657 = cat(T_1652.idx, T_1652.loc) - T_2014.inner.release.bits.data := T_1657 - node T_1659 = eq(release_idx, UInt<3>("h04")) - node T_1660 = and(inner.release.valid, T_1659) - T_2015.inner.release.valid := T_1660 - T_2015.inner.release.bits <> inner.release.bits - wire T_1664 : {idx : UInt<2>, loc : UInt<2>} - T_1664.loc := UInt<1>("h00") - T_1664.idx := UInt<1>("h00") - T_1664.idx := rel_data_cnt - T_1664.loc := UInt<2>("h02") - node T_1669 = cat(T_1664.idx, T_1664.loc) - T_2015.inner.release.bits.data := T_1669 - node T_1671 = eq(release_idx, UInt<3>("h05")) - node T_1672 = and(inner.release.valid, T_1671) - T_2016.inner.release.valid := T_1672 - T_2016.inner.release.bits <> inner.release.bits - wire T_1676 : {idx : UInt<2>, loc : UInt<2>} - T_1676.loc := UInt<1>("h00") - T_1676.idx := UInt<1>("h00") - T_1676.idx := rel_data_cnt - T_1676.loc := UInt<2>("h02") - node T_1681 = cat(T_1676.idx, T_1676.loc) - T_2016.inner.release.bits.data := T_1681 - node T_1683 = eq(release_idx, UInt<3>("h06")) - node T_1684 = and(inner.release.valid, T_1683) - T_2017.inner.release.valid := T_1684 - T_2017.inner.release.bits <> inner.release.bits - wire T_1688 : {idx : UInt<2>, loc : UInt<2>} - T_1688.loc := UInt<1>("h00") - T_1688.idx := UInt<1>("h00") - T_1688.idx := rel_data_cnt - T_1688.loc := UInt<2>("h02") - node T_1693 = cat(T_1688.idx, T_1688.loc) - T_2017.inner.release.bits.data := T_1693 - node T_1695 = eq(release_idx, UInt<3>("h07")) - node T_1696 = and(inner.release.valid, T_1695) - T_2018.inner.release.valid := T_1696 - T_2018.inner.release.bits <> inner.release.bits - wire T_1700 : {idx : UInt<2>, loc : UInt<2>} - T_1700.loc := UInt<1>("h00") - T_1700.idx := UInt<1>("h00") - T_1700.idx := rel_data_cnt - T_1700.loc := UInt<2>("h02") - node T_1705 = cat(T_1700.idx, T_1700.loc) - T_2018.inner.release.bits.data := T_1705 - node T_1707 = neq(releaseMatches, UInt<1>("h00")) - node T_1709 = eq(T_1707, UInt<1>("h00")) - node T_1710 = and(inner.release.valid, T_1709) - node T_1712 = eq(T_1710, UInt<1>("h00")) - inst T_2019 of LockingRRArbiter_33 - T_2019.out.ready := UInt<1>("h00") - T_2019.in[0].bits.client_id := UInt<1>("h00") - T_2019.in[0].bits.g_type := UInt<1>("h00") - T_2019.in[0].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[0].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[0].bits.client_xact_id := UInt<1>("h00") - T_2019.in[0].bits.data := UInt<1>("h00") - T_2019.in[0].bits.addr_beat := UInt<1>("h00") - T_2019.in[0].valid := UInt<1>("h00") - T_2019.in[1].bits.client_id := UInt<1>("h00") - T_2019.in[1].bits.g_type := UInt<1>("h00") - T_2019.in[1].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[1].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[1].bits.client_xact_id := UInt<1>("h00") - T_2019.in[1].bits.data := UInt<1>("h00") - T_2019.in[1].bits.addr_beat := UInt<1>("h00") - T_2019.in[1].valid := UInt<1>("h00") - T_2019.in[2].bits.client_id := UInt<1>("h00") - T_2019.in[2].bits.g_type := UInt<1>("h00") - T_2019.in[2].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[2].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[2].bits.client_xact_id := UInt<1>("h00") - T_2019.in[2].bits.data := UInt<1>("h00") - T_2019.in[2].bits.addr_beat := UInt<1>("h00") - T_2019.in[2].valid := UInt<1>("h00") - T_2019.in[3].bits.client_id := UInt<1>("h00") - T_2019.in[3].bits.g_type := UInt<1>("h00") - T_2019.in[3].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[3].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[3].bits.client_xact_id := UInt<1>("h00") - T_2019.in[3].bits.data := UInt<1>("h00") - T_2019.in[3].bits.addr_beat := UInt<1>("h00") - T_2019.in[3].valid := UInt<1>("h00") - T_2019.in[4].bits.client_id := UInt<1>("h00") - T_2019.in[4].bits.g_type := UInt<1>("h00") - T_2019.in[4].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[4].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[4].bits.client_xact_id := UInt<1>("h00") - T_2019.in[4].bits.data := UInt<1>("h00") - T_2019.in[4].bits.addr_beat := UInt<1>("h00") - T_2019.in[4].valid := UInt<1>("h00") - T_2019.in[5].bits.client_id := UInt<1>("h00") - T_2019.in[5].bits.g_type := UInt<1>("h00") - T_2019.in[5].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[5].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[5].bits.client_xact_id := UInt<1>("h00") - T_2019.in[5].bits.data := UInt<1>("h00") - T_2019.in[5].bits.addr_beat := UInt<1>("h00") - T_2019.in[5].valid := UInt<1>("h00") - T_2019.in[6].bits.client_id := UInt<1>("h00") - T_2019.in[6].bits.g_type := UInt<1>("h00") - T_2019.in[6].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[6].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[6].bits.client_xact_id := UInt<1>("h00") - T_2019.in[6].bits.data := UInt<1>("h00") - T_2019.in[6].bits.addr_beat := UInt<1>("h00") - T_2019.in[6].valid := UInt<1>("h00") - T_2019.in[7].bits.client_id := UInt<1>("h00") - T_2019.in[7].bits.g_type := UInt<1>("h00") - T_2019.in[7].bits.is_builtin_type := UInt<1>("h00") - T_2019.in[7].bits.manager_xact_id := UInt<1>("h00") - T_2019.in[7].bits.client_xact_id := UInt<1>("h00") - T_2019.in[7].bits.data := UInt<1>("h00") - T_2019.in[7].bits.addr_beat := UInt<1>("h00") - T_2019.in[7].valid := UInt<1>("h00") - T_2019.reset := UInt<1>("h00") - T_2019.clock := clock - T_2019.reset := reset - inner.grant <> T_2019.out - T_2019.in[0] <> T_2011.inner.grant - T_2019.in[1] <> T_2012.inner.grant - T_2019.in[2] <> T_2013.inner.grant - T_2019.in[3] <> T_2014.inner.grant - T_2019.in[4] <> T_2015.inner.grant - T_2019.in[5] <> T_2016.inner.grant - T_2019.in[6] <> T_2017.inner.grant - T_2019.in[7] <> T_2018.inner.grant - inner.grant.bits.data := outer.grant.bits.data - inner.grant.bits.addr_beat := outer.grant.bits.addr_beat - inst T_2020 of LockingRRArbiter_34 - T_2020.out.ready := UInt<1>("h00") - T_2020.in[0].bits.client_id := UInt<1>("h00") - T_2020.in[0].bits.p_type := UInt<1>("h00") - T_2020.in[0].bits.addr_block := UInt<1>("h00") - T_2020.in[0].valid := UInt<1>("h00") - T_2020.in[1].bits.client_id := UInt<1>("h00") - T_2020.in[1].bits.p_type := UInt<1>("h00") - T_2020.in[1].bits.addr_block := UInt<1>("h00") - T_2020.in[1].valid := UInt<1>("h00") - T_2020.in[2].bits.client_id := UInt<1>("h00") - T_2020.in[2].bits.p_type := UInt<1>("h00") - T_2020.in[2].bits.addr_block := UInt<1>("h00") - T_2020.in[2].valid := UInt<1>("h00") - T_2020.in[3].bits.client_id := UInt<1>("h00") - T_2020.in[3].bits.p_type := UInt<1>("h00") - T_2020.in[3].bits.addr_block := UInt<1>("h00") - T_2020.in[3].valid := UInt<1>("h00") - T_2020.in[4].bits.client_id := UInt<1>("h00") - T_2020.in[4].bits.p_type := UInt<1>("h00") - T_2020.in[4].bits.addr_block := UInt<1>("h00") - T_2020.in[4].valid := UInt<1>("h00") - T_2020.in[5].bits.client_id := UInt<1>("h00") - T_2020.in[5].bits.p_type := UInt<1>("h00") - T_2020.in[5].bits.addr_block := UInt<1>("h00") - T_2020.in[5].valid := UInt<1>("h00") - T_2020.in[6].bits.client_id := UInt<1>("h00") - T_2020.in[6].bits.p_type := UInt<1>("h00") - T_2020.in[6].bits.addr_block := UInt<1>("h00") - T_2020.in[6].valid := UInt<1>("h00") - T_2020.in[7].bits.client_id := UInt<1>("h00") - T_2020.in[7].bits.p_type := UInt<1>("h00") - T_2020.in[7].bits.addr_block := UInt<1>("h00") - T_2020.in[7].valid := UInt<1>("h00") - T_2020.reset := UInt<1>("h00") - T_2020.clock := clock - T_2020.reset := reset - inner.probe <> T_2020.out - T_2020.in[0] <> T_2011.inner.probe - T_2020.in[1] <> T_2012.inner.probe - T_2020.in[2] <> T_2013.inner.probe - T_2020.in[3] <> T_2014.inner.probe - T_2020.in[4] <> T_2015.inner.probe - T_2020.in[5] <> T_2016.inner.probe - T_2020.in[6] <> T_2017.inner.probe - T_2020.in[7] <> T_2018.inner.probe - T_2011.inner.finish.bits <> inner.finish.bits - T_2012.inner.finish.bits <> inner.finish.bits - T_2013.inner.finish.bits <> inner.finish.bits - T_2014.inner.finish.bits <> inner.finish.bits - T_2015.inner.finish.bits <> inner.finish.bits - T_2016.inner.finish.bits <> inner.finish.bits - T_2017.inner.finish.bits <> inner.finish.bits - T_2018.inner.finish.bits <> inner.finish.bits - node T_1814 = eq(inner.finish.bits.manager_xact_id, UInt<1>("h00")) - node T_1815 = and(inner.finish.valid, T_1814) - T_2011.inner.finish.valid := T_1815 - node T_1817 = eq(inner.finish.bits.manager_xact_id, UInt<1>("h01")) - node T_1818 = and(inner.finish.valid, T_1817) - T_2012.inner.finish.valid := T_1818 - node T_1820 = eq(inner.finish.bits.manager_xact_id, UInt<2>("h02")) - node T_1821 = and(inner.finish.valid, T_1820) - T_2013.inner.finish.valid := T_1821 - node T_1823 = eq(inner.finish.bits.manager_xact_id, UInt<2>("h03")) - node T_1824 = and(inner.finish.valid, T_1823) - T_2014.inner.finish.valid := T_1824 - node T_1826 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h04")) - node T_1827 = and(inner.finish.valid, T_1826) - T_2015.inner.finish.valid := T_1827 - node T_1829 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h05")) - node T_1830 = and(inner.finish.valid, T_1829) - T_2016.inner.finish.valid := T_1830 - node T_1832 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h06")) - node T_1833 = and(inner.finish.valid, T_1832) - T_2017.inner.finish.valid := T_1833 - node T_1835 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h07")) - node T_1836 = and(inner.finish.valid, T_1835) - T_2018.inner.finish.valid := T_1836 - wire T_1838 : UInt<1>[8] - T_1838[0] := T_2011.inner.finish.ready - T_1838[1] := T_2012.inner.finish.ready - T_1838[2] := T_2013.inner.finish.ready - T_1838[3] := T_2014.inner.finish.ready - T_1838[4] := T_2015.inner.finish.ready - T_1838[5] := T_2016.inner.finish.ready - T_1838[6] := T_2017.inner.finish.ready - T_1838[7] := T_2018.inner.finish.ready - infer accessor T_1848 = T_1838[inner.finish.bits.manager_xact_id] - inner.finish.ready := T_1848 - inst outer_arb of ClientUncachedTileLinkIOArbiter - outer_arb.out.grant.bits.g_type := UInt<1>("h00") - outer_arb.out.grant.bits.is_builtin_type := UInt<1>("h00") - outer_arb.out.grant.bits.manager_xact_id := UInt<1>("h00") - outer_arb.out.grant.bits.client_xact_id := UInt<1>("h00") - outer_arb.out.grant.bits.data := UInt<1>("h00") - outer_arb.out.grant.bits.addr_beat := UInt<1>("h00") - outer_arb.out.grant.valid := UInt<1>("h00") - outer_arb.out.acquire.ready := UInt<1>("h00") - outer_arb.in[0].grant.ready := UInt<1>("h00") - outer_arb.in[0].acquire.bits.union := UInt<1>("h00") - outer_arb.in[0].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[0].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[0].acquire.bits.data := UInt<1>("h00") - outer_arb.in[0].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[0].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[0].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[0].acquire.valid := UInt<1>("h00") - outer_arb.in[1].grant.ready := UInt<1>("h00") - outer_arb.in[1].acquire.bits.union := UInt<1>("h00") - outer_arb.in[1].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[1].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[1].acquire.bits.data := UInt<1>("h00") - outer_arb.in[1].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[1].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[1].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[1].acquire.valid := UInt<1>("h00") - outer_arb.in[2].grant.ready := UInt<1>("h00") - outer_arb.in[2].acquire.bits.union := UInt<1>("h00") - outer_arb.in[2].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[2].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[2].acquire.bits.data := UInt<1>("h00") - outer_arb.in[2].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[2].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[2].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[2].acquire.valid := UInt<1>("h00") - outer_arb.in[3].grant.ready := UInt<1>("h00") - outer_arb.in[3].acquire.bits.union := UInt<1>("h00") - outer_arb.in[3].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[3].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[3].acquire.bits.data := UInt<1>("h00") - outer_arb.in[3].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[3].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[3].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[3].acquire.valid := UInt<1>("h00") - outer_arb.in[4].grant.ready := UInt<1>("h00") - outer_arb.in[4].acquire.bits.union := UInt<1>("h00") - outer_arb.in[4].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[4].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[4].acquire.bits.data := UInt<1>("h00") - outer_arb.in[4].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[4].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[4].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[4].acquire.valid := UInt<1>("h00") - outer_arb.in[5].grant.ready := UInt<1>("h00") - outer_arb.in[5].acquire.bits.union := UInt<1>("h00") - outer_arb.in[5].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[5].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[5].acquire.bits.data := UInt<1>("h00") - outer_arb.in[5].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[5].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[5].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[5].acquire.valid := UInt<1>("h00") - outer_arb.in[6].grant.ready := UInt<1>("h00") - outer_arb.in[6].acquire.bits.union := UInt<1>("h00") - outer_arb.in[6].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[6].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[6].acquire.bits.data := UInt<1>("h00") - outer_arb.in[6].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[6].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[6].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[6].acquire.valid := UInt<1>("h00") - outer_arb.in[7].grant.ready := UInt<1>("h00") - outer_arb.in[7].acquire.bits.union := UInt<1>("h00") - outer_arb.in[7].acquire.bits.a_type := UInt<1>("h00") - outer_arb.in[7].acquire.bits.is_builtin_type := UInt<1>("h00") - outer_arb.in[7].acquire.bits.data := UInt<1>("h00") - outer_arb.in[7].acquire.bits.addr_beat := UInt<1>("h00") - outer_arb.in[7].acquire.bits.client_xact_id := UInt<1>("h00") - outer_arb.in[7].acquire.bits.addr_block := UInt<1>("h00") - outer_arb.in[7].acquire.valid := UInt<1>("h00") - outer_arb.reset := UInt<1>("h00") - outer_arb.clock := clock - outer_arb.reset := reset - outer_arb.in[0] <> T_2011.outer - outer_arb.in[1] <> T_2012.outer - outer_arb.in[2] <> T_2013.outer - outer_arb.in[3] <> T_2014.outer - outer_arb.in[4] <> T_2015.outer - outer_arb.in[5] <> T_2016.outer - outer_arb.in[6] <> T_2017.outer - outer_arb.in[7] <> T_2018.outer - wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} - outer_data_ptr.loc := UInt<1>("h00") - outer_data_ptr.idx := UInt<1>("h00") - node T_1941 = bits(outer_arb.out.acquire.bits.data, 1, 0) - outer_data_ptr.loc := T_1941 - node T_1942 = bits(outer_arb.out.acquire.bits.data, 3, 2) - outer_data_ptr.idx := T_1942 - node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) - node T_1944 = and(outer.acquire.ready, outer.acquire.valid) - wire T_1949 : UInt<3>[3] - T_1949[0] := UInt<3>("h02") - T_1949[1] := UInt<3>("h03") - T_1949[2] := UInt<3>("h04") - node T_1954 = eq(T_1949[0], outer.acquire.bits.a_type) - node T_1955 = eq(T_1949[1], outer.acquire.bits.a_type) - node T_1956 = eq(T_1949[2], outer.acquire.bits.a_type) - node T_1958 = or(UInt<1>("h00"), T_1954) - node T_1959 = or(T_1958, T_1955) - node T_1960 = or(T_1959, T_1956) - node T_1961 = and(outer.acquire.bits.is_builtin_type, T_1960) - node T_1962 = and(T_1944, T_1961) - node T_1963 = eq(outer_data_ptr.loc, UInt<1>("h00")) - node free_sdq = and(T_1962, T_1963) - outer <> outer_arb.out - infer accessor T_1965 = sdq[outer_data_ptr.idx] - infer accessor T_1966 = vwbdq[outer_data_ptr.idx] - node T_1967 = eq(UInt<1>("h01"), outer_data_ptr.loc) - node T_1968 = mux(T_1967, T_1966, inner.release.bits.data) - node T_1969 = eq(UInt<1>("h00"), outer_data_ptr.loc) - node T_1970 = mux(T_1969, T_1965, T_1968) - outer.acquire.bits.data := T_1970 - node T_1971 = bit(outer_arb.out.acquire.bits.union, 1) - node T_1973 = subw(UInt<16>("h00"), T_1971) - node T_1974 = bit(outer_arb.out.acquire.bits.union, 0) - node T_1975 = cat(T_1973, T_1974) - outer.acquire.bits.union := T_1975 - node T_1976 = or(outer.acquire.valid, sdq_enq) - when T_1976 : - node T_1978 = dshl(UInt<1>("h01"), outer_data_ptr.idx) - node T_1980 = subw(UInt<4>("h00"), free_sdq) - node T_1981 = and(T_1978, T_1980) - node T_1982 = not(T_1981) - node T_1983 = and(sdq_val, T_1982) - node T_1984 = bits(sdq_val, 3, 0) - node T_1985 = not(T_1984) - node T_1986 = bit(T_1985, 0) - node T_1987 = bit(T_1985, 1) - node T_1988 = bit(T_1985, 2) - node T_1989 = bit(T_1985, 3) - wire T_1995 : UInt<4>[4] - T_1995[0] := UInt<4>("h01") - T_1995[1] := UInt<4>("h02") - T_1995[2] := UInt<4>("h04") - T_1995[3] := UInt<4>("h08") - node T_2003 = mux(T_1989, T_1995[3], UInt<4>("h00")) - node T_2004 = mux(T_1988, T_1995[2], T_2003) - node T_2005 = mux(T_1987, T_1995[1], T_2004) - node T_2006 = mux(T_1986, T_1995[0], T_2005) - node T_2008 = subw(UInt<4>("h00"), sdq_enq) - node T_2009 = and(T_2006, T_2008) - node T_2010 = or(T_1983, T_2009) - sdq_val := T_2010 - skip - - module FinishQueue_39 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.dst := UInt<1>("h00") - deq.bits.fin.manager_xact_id := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem T_409 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}[2], clock - reg T_411 : UInt<1>, clock, reset - onreset T_411 := UInt<1>("h00") - reg T_413 : UInt<1>, clock, reset - onreset T_413 := UInt<1>("h00") - reg T_415 : UInt<1>, clock, reset - onreset T_415 := UInt<1>("h00") - node T_416 = eq(T_411, T_413) - node T_418 = eq(T_415, UInt<1>("h00")) - node T_419 = and(T_416, T_418) - node T_420 = and(T_416, T_415) - node T_422 = and(UInt<1>("h00"), T_419) - node T_423 = and(T_422, deq.ready) - node T_424 = and(enq.ready, enq.valid) - node T_426 = eq(T_423, UInt<1>("h00")) - node T_427 = and(T_424, T_426) - node T_428 = and(deq.ready, deq.valid) - node T_430 = eq(T_423, UInt<1>("h00")) - node T_431 = and(T_428, T_430) - when T_427 : - infer accessor T_432 = T_409[T_411] - T_432 <> enq.bits - node T_477 = eq(T_411, UInt<1>("h01")) - node T_479 = and(UInt<1>("h00"), T_477) - node T_482 = addw(T_411, UInt<1>("h01")) - node T_483 = mux(T_479, UInt<1>("h00"), T_482) - T_411 := T_483 - skip - when T_431 : - node T_485 = eq(T_413, UInt<1>("h01")) - node T_487 = and(UInt<1>("h00"), T_485) - node T_490 = addw(T_413, UInt<1>("h01")) - node T_491 = mux(T_487, UInt<1>("h00"), T_490) - T_413 := T_491 - skip - node T_492 = neq(T_427, T_431) - when T_492 : - T_415 := T_427 - skip - node T_494 = eq(T_419, UInt<1>("h00")) - node T_496 = and(UInt<1>("h00"), enq.valid) - node T_497 = or(T_494, T_496) - deq.valid := T_497 - node T_499 = eq(T_420, UInt<1>("h00")) - node T_501 = and(UInt<1>("h00"), deq.ready) - node T_502 = or(T_499, T_501) - enq.ready := T_502 - infer accessor T_503 = T_409[T_413] - wire T_591 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>} - T_591 <> T_503 - when T_422 : - T_591 <> enq.bits - skip - deq.bits <> T_591 - node T_635 = subw(T_411, T_413) - node T_636 = and(T_415, T_416) - node T_637 = cat(T_636, T_635) - count := T_637 - - module FinishUnit_38 : - output ready : UInt<1> - output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}} - output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - ready := UInt<1>("h00") - finish.bits.payload.manager_xact_id := UInt<1>("h00") - finish.bits.header.dst := UInt<1>("h00") - finish.bits.header.src := UInt<1>("h00") - finish.valid := UInt<1>("h00") - refill.bits.g_type := UInt<1>("h00") - refill.bits.is_builtin_type := UInt<1>("h00") - refill.bits.manager_xact_id := UInt<1>("h00") - refill.bits.client_xact_id := UInt<1>("h00") - refill.bits.data := UInt<1>("h00") - refill.bits.addr_beat := UInt<1>("h00") - refill.valid := UInt<1>("h00") - grant.ready := UInt<1>("h00") - node T_399 = and(grant.ready, grant.valid) - wire T_404 : UInt<3>[1] - T_404[0] := UInt<3>("h05") - node T_407 = eq(T_404[0], grant.bits.payload.g_type) - node T_409 = or(UInt<1>("h00"), T_407) - wire T_411 : UInt<1>[1] - T_411[0] := UInt<1>("h00") - node T_414 = eq(T_411[0], grant.bits.payload.g_type) - node T_416 = or(UInt<1>("h00"), T_414) - node T_417 = mux(grant.bits.payload.is_builtin_type, T_409, T_416) - node T_418 = and(UInt<1>("h01"), T_417) - node T_419 = and(T_399, T_418) - reg T_421 : UInt<2>, clock, reset - onreset T_421 := UInt<2>("h00") - when T_419 : - node T_423 = eq(T_421, UInt<2>("h03")) - node T_425 = and(UInt<1>("h00"), T_423) - node T_428 = addw(T_421, UInt<1>("h01")) - node T_429 = mux(T_425, UInt<1>("h00"), T_428) - T_421 := T_429 - skip - node T_430 = and(T_419, T_423) - node T_431 = mux(T_418, T_421, UInt<1>("h00")) - node T_432 = mux(T_418, T_430, T_399) - inst T_574 of FinishQueue_39 - T_574.deq.ready := UInt<1>("h00") - T_574.enq.bits.dst := UInt<1>("h00") - T_574.enq.bits.fin.manager_xact_id := UInt<1>("h00") - T_574.enq.valid := UInt<1>("h00") - T_574.reset := UInt<1>("h00") - T_574.clock := clock - T_574.reset := reset - node T_482 = and(grant.ready, grant.valid) - node T_485 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_487 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_488 = and(grant.bits.payload.is_builtin_type, T_487) - node T_490 = eq(T_488, UInt<1>("h00")) - node T_491 = and(T_485, T_490) - node T_492 = and(T_482, T_491) - wire T_496 : UInt<3>[1] - T_496[0] := UInt<3>("h05") - node T_499 = eq(T_496[0], grant.bits.payload.g_type) - node T_501 = or(UInt<1>("h00"), T_499) - wire T_503 : UInt<1>[1] - T_503[0] := UInt<1>("h00") - node T_506 = eq(T_503[0], grant.bits.payload.g_type) - node T_508 = or(UInt<1>("h00"), T_506) - node T_509 = mux(grant.bits.payload.is_builtin_type, T_501, T_508) - node T_510 = and(UInt<1>("h01"), T_509) - node T_512 = eq(T_510, UInt<1>("h00")) - node T_513 = or(T_512, T_432) - node T_514 = and(T_492, T_513) - T_574.enq.valid := T_514 - wire T_537 : {manager_xact_id : UInt<1>} - T_537.manager_xact_id := UInt<1>("h00") - T_537.manager_xact_id := grant.bits.payload.manager_xact_id - T_574.enq.bits.fin <> T_537 - T_574.enq.bits.dst := grant.bits.header.src - finish.bits.header.src := UInt<1>("h00") - finish.bits.header.dst := T_574.deq.bits.dst - finish.bits.payload <> T_574.deq.bits.fin - finish.valid := T_574.deq.valid - T_574.deq.ready := finish.ready - refill.valid := grant.valid - refill.bits <> grant.bits.payload - node T_563 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_565 = eq(grant.bits.payload.g_type, UInt<3>("h00")) - node T_566 = and(grant.bits.payload.is_builtin_type, T_565) - node T_568 = eq(T_566, UInt<1>("h00")) - node T_569 = and(T_563, T_568) - node T_571 = eq(T_569, UInt<1>("h00")) - node T_572 = or(T_574.enq.ready, T_571) - node T_573 = and(T_572, refill.ready) - grant.ready := T_573 - ready := T_574.enq.ready - - module ClientTileLinkNetworkPort_37 : - output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - network.release.bits.payload.voluntary := UInt<1>("h00") - network.release.bits.payload.r_type := UInt<1>("h00") - network.release.bits.payload.data := UInt<1>("h00") - network.release.bits.payload.addr_beat := UInt<1>("h00") - network.release.bits.payload.client_xact_id := UInt<1>("h00") - network.release.bits.payload.addr_block := UInt<1>("h00") - network.release.bits.header.dst := UInt<1>("h00") - network.release.bits.header.src := UInt<1>("h00") - network.release.valid := UInt<1>("h00") - network.probe.ready := UInt<1>("h00") - network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - network.finish.bits.header.dst := UInt<1>("h00") - network.finish.bits.header.src := UInt<1>("h00") - network.finish.valid := UInt<1>("h00") - network.grant.ready := UInt<1>("h00") - network.acquire.bits.payload.union := UInt<1>("h00") - network.acquire.bits.payload.a_type := UInt<1>("h00") - network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - network.acquire.bits.payload.data := UInt<1>("h00") - network.acquire.bits.payload.addr_beat := UInt<1>("h00") - network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - network.acquire.bits.payload.addr_block := UInt<1>("h00") - network.acquire.bits.header.dst := UInt<1>("h00") - network.acquire.bits.header.src := UInt<1>("h00") - network.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.p_type := UInt<1>("h00") - client.probe.bits.addr_block := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.grant.bits.g_type := UInt<1>("h00") - client.grant.bits.is_builtin_type := UInt<1>("h00") - client.grant.bits.manager_xact_id := UInt<1>("h00") - client.grant.bits.client_xact_id := UInt<1>("h00") - client.grant.bits.data := UInt<1>("h00") - client.grant.bits.addr_beat := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - inst finisher of FinishUnit_38 - finisher.finish.ready := UInt<1>("h00") - finisher.refill.ready := UInt<1>("h00") - finisher.grant.bits.payload.g_type := UInt<1>("h00") - finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") - finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") - finisher.grant.bits.payload.data := UInt<1>("h00") - finisher.grant.bits.payload.addr_beat := UInt<1>("h00") - finisher.grant.bits.header.dst := UInt<1>("h00") - finisher.grant.bits.header.src := UInt<1>("h00") - finisher.grant.valid := UInt<1>("h00") - finisher.reset := UInt<1>("h00") - finisher.clock := clock - finisher.reset := reset - finisher.grant <> network.grant - network.finish <> finisher.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} - acq_with_header.bits.payload.union := UInt<1>("h00") - acq_with_header.bits.payload.a_type := UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") - acq_with_header.bits.payload.data := UInt<1>("h00") - acq_with_header.bits.payload.addr_beat := UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") - acq_with_header.bits.payload.addr_block := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.valid := UInt<1>("h00") - acq_with_header.ready := UInt<1>("h00") - acq_with_header.bits.payload <> client.acquire.bits - acq_with_header.bits.header.src := UInt<1>("h00") - acq_with_header.bits.header.dst := UInt<1>("h00") - acq_with_header.valid := client.acquire.valid - client.acquire.ready := acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - rel_with_header.bits.payload.voluntary := UInt<1>("h00") - rel_with_header.bits.payload.r_type := UInt<1>("h00") - rel_with_header.bits.payload.data := UInt<1>("h00") - rel_with_header.bits.payload.addr_beat := UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") - rel_with_header.bits.payload.addr_block := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.valid := UInt<1>("h00") - rel_with_header.ready := UInt<1>("h00") - rel_with_header.bits.payload <> client.release.bits - rel_with_header.bits.header.src := UInt<1>("h00") - rel_with_header.bits.header.dst := UInt<1>("h00") - rel_with_header.valid := client.release.valid - client.release.ready := rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type := UInt<1>("h00") - prb_without_header.bits.addr_block := UInt<1>("h00") - prb_without_header.valid := UInt<1>("h00") - prb_without_header.ready := UInt<1>("h00") - prb_without_header.valid := network.probe.valid - prb_without_header.bits <> network.probe.bits.payload - network.probe.ready := prb_without_header.ready - network.acquire.bits <> acq_with_header.bits - node T_2123 = and(acq_with_header.valid, finisher.ready) - network.acquire.valid := T_2123 - node T_2124 = and(network.acquire.ready, finisher.ready) - acq_with_header.ready := T_2124 - network.release <> rel_with_header - client.probe <> prb_without_header - client.grant <> finisher.refill - - module TileLinkEnqueuer_40 : - output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input clock : Clock - input reset : UInt<1> - - manager.release.bits.payload.voluntary := UInt<1>("h00") - manager.release.bits.payload.r_type := UInt<1>("h00") - manager.release.bits.payload.data := UInt<1>("h00") - manager.release.bits.payload.addr_beat := UInt<1>("h00") - manager.release.bits.payload.client_xact_id := UInt<1>("h00") - manager.release.bits.payload.addr_block := UInt<1>("h00") - manager.release.bits.header.dst := UInt<1>("h00") - manager.release.bits.header.src := UInt<1>("h00") - manager.release.valid := UInt<1>("h00") - manager.probe.ready := UInt<1>("h00") - manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") - manager.finish.bits.header.dst := UInt<1>("h00") - manager.finish.bits.header.src := UInt<1>("h00") - manager.finish.valid := UInt<1>("h00") - manager.grant.ready := UInt<1>("h00") - manager.acquire.bits.payload.union := UInt<1>("h00") - manager.acquire.bits.payload.a_type := UInt<1>("h00") - manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - manager.acquire.bits.payload.data := UInt<1>("h00") - manager.acquire.bits.payload.addr_beat := UInt<1>("h00") - manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") - manager.acquire.bits.payload.addr_block := UInt<1>("h00") - manager.acquire.bits.header.dst := UInt<1>("h00") - manager.acquire.bits.header.src := UInt<1>("h00") - manager.acquire.valid := UInt<1>("h00") - client.release.ready := UInt<1>("h00") - client.probe.bits.payload.p_type := UInt<1>("h00") - client.probe.bits.payload.addr_block := UInt<1>("h00") - client.probe.bits.header.dst := UInt<1>("h00") - client.probe.bits.header.src := UInt<1>("h00") - client.probe.valid := UInt<1>("h00") - client.finish.ready := UInt<1>("h00") - client.grant.bits.payload.g_type := UInt<1>("h00") - client.grant.bits.payload.is_builtin_type := UInt<1>("h00") - client.grant.bits.payload.manager_xact_id := UInt<1>("h00") - client.grant.bits.payload.client_xact_id := UInt<1>("h00") - client.grant.bits.payload.data := UInt<1>("h00") - client.grant.bits.payload.addr_beat := UInt<1>("h00") - client.grant.bits.header.dst := UInt<1>("h00") - client.grant.bits.header.src := UInt<1>("h00") - client.grant.valid := UInt<1>("h00") - client.acquire.ready := UInt<1>("h00") - manager.acquire <> client.acquire - client.probe <> manager.probe - manager.release <> client.release - client.grant <> manager.grant - manager.finish <> client.finish - - module ManagerTileLinkNetworkPort_41 : - input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} - input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - network.release.ready := UInt<1>("h00") - network.probe.bits.payload.p_type := UInt<1>("h00") - network.probe.bits.payload.addr_block := UInt<1>("h00") - network.probe.bits.header.dst := UInt<1>("h00") - network.probe.bits.header.src := UInt<1>("h00") - network.probe.valid := UInt<1>("h00") - network.finish.ready := UInt<1>("h00") - network.grant.bits.payload.g_type := UInt<1>("h00") - network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - network.grant.bits.payload.client_xact_id := UInt<1>("h00") - network.grant.bits.payload.data := UInt<1>("h00") - network.grant.bits.payload.addr_beat := UInt<1>("h00") - network.grant.bits.header.dst := UInt<1>("h00") - network.grant.bits.header.src := UInt<1>("h00") - network.grant.valid := UInt<1>("h00") - network.acquire.ready := UInt<1>("h00") - manager.release.bits.client_id := UInt<1>("h00") - manager.release.bits.voluntary := UInt<1>("h00") - manager.release.bits.r_type := UInt<1>("h00") - manager.release.bits.data := UInt<1>("h00") - manager.release.bits.addr_beat := UInt<1>("h00") - manager.release.bits.client_xact_id := UInt<1>("h00") - manager.release.bits.addr_block := UInt<1>("h00") - manager.release.valid := UInt<1>("h00") - manager.probe.ready := UInt<1>("h00") - manager.finish.bits.manager_xact_id := UInt<1>("h00") - manager.finish.valid := UInt<1>("h00") - manager.grant.ready := UInt<1>("h00") - manager.acquire.bits.client_id := UInt<1>("h00") - manager.acquire.bits.union := UInt<1>("h00") - manager.acquire.bits.a_type := UInt<1>("h00") - manager.acquire.bits.is_builtin_type := UInt<1>("h00") - manager.acquire.bits.data := UInt<1>("h00") - manager.acquire.bits.addr_beat := UInt<1>("h00") - manager.acquire.bits.client_xact_id := UInt<1>("h00") - manager.acquire.bits.addr_block := UInt<1>("h00") - manager.acquire.valid := UInt<1>("h00") - wire T_2766 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}} - T_2766.bits.payload.client_id := UInt<1>("h00") - T_2766.bits.payload.g_type := UInt<1>("h00") - T_2766.bits.payload.is_builtin_type := UInt<1>("h00") - T_2766.bits.payload.manager_xact_id := UInt<1>("h00") - T_2766.bits.payload.client_xact_id := UInt<1>("h00") - T_2766.bits.payload.data := UInt<1>("h00") - T_2766.bits.payload.addr_beat := UInt<1>("h00") - T_2766.bits.header.dst := UInt<1>("h00") - T_2766.bits.header.src := UInt<1>("h00") - T_2766.valid := UInt<1>("h00") - T_2766.ready := UInt<1>("h00") - T_2766.bits.payload <> manager.grant.bits - T_2766.bits.header.src := UInt<1>("h00") - T_2766.bits.header.dst := manager.grant.bits.client_id - T_2766.valid := manager.grant.valid - manager.grant.ready := T_2766.ready - network.grant <> T_2766 - wire T_2932 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} - T_2932.bits.payload.client_id := UInt<1>("h00") - T_2932.bits.payload.p_type := UInt<1>("h00") - T_2932.bits.payload.addr_block := UInt<1>("h00") - T_2932.bits.header.dst := UInt<1>("h00") - T_2932.bits.header.src := UInt<1>("h00") - T_2932.valid := UInt<1>("h00") - T_2932.ready := UInt<1>("h00") - T_2932.bits.payload <> manager.probe.bits - T_2932.bits.header.src := UInt<1>("h00") - T_2932.bits.header.dst := manager.probe.bits.client_id - T_2932.valid := manager.probe.valid - manager.probe.ready := T_2932.ready - network.probe <> T_2932 - manager.acquire.bits.client_id := network.acquire.bits.header.src - wire T_3058 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - T_3058.bits.union := UInt<1>("h00") - T_3058.bits.a_type := UInt<1>("h00") - T_3058.bits.is_builtin_type := UInt<1>("h00") - T_3058.bits.data := UInt<1>("h00") - T_3058.bits.addr_beat := UInt<1>("h00") - T_3058.bits.client_xact_id := UInt<1>("h00") - T_3058.bits.addr_block := UInt<1>("h00") - T_3058.valid := UInt<1>("h00") - T_3058.ready := UInt<1>("h00") - T_3058.valid := network.acquire.valid - T_3058.bits <> network.acquire.bits.payload - network.acquire.ready := T_3058.ready - manager.acquire <> T_3058 - manager.release.bits.client_id := network.release.bits.header.src - wire T_3183 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - T_3183.bits.voluntary := UInt<1>("h00") - T_3183.bits.r_type := UInt<1>("h00") - T_3183.bits.data := UInt<1>("h00") - T_3183.bits.addr_beat := UInt<1>("h00") - T_3183.bits.client_xact_id := UInt<1>("h00") - T_3183.bits.addr_block := UInt<1>("h00") - T_3183.valid := UInt<1>("h00") - T_3183.ready := UInt<1>("h00") - T_3183.valid := network.release.valid - T_3183.bits <> network.release.bits.payload - network.release.ready := T_3183.ready - manager.release <> T_3183 - wire T_3295 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}} - T_3295.bits.manager_xact_id := UInt<1>("h00") - T_3295.valid := UInt<1>("h00") - T_3295.ready := UInt<1>("h00") - T_3295.valid := network.finish.valid - T_3295.bits <> network.finish.bits.payload - network.finish.ready := T_3295.ready - manager.finish <> T_3295 - - module RocketChipTileLinkArbiter_36 : - input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}[1] - input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] - input clock : Clock - input reset : UInt<1> - - managers[0].release.bits.client_id := UInt<1>("h00") - managers[0].release.bits.voluntary := UInt<1>("h00") - managers[0].release.bits.r_type := UInt<1>("h00") - managers[0].release.bits.data := UInt<1>("h00") - managers[0].release.bits.addr_beat := UInt<1>("h00") - managers[0].release.bits.client_xact_id := UInt<1>("h00") - managers[0].release.bits.addr_block := UInt<1>("h00") - managers[0].release.valid := UInt<1>("h00") - managers[0].probe.ready := UInt<1>("h00") - managers[0].finish.bits.manager_xact_id := UInt<1>("h00") - managers[0].finish.valid := UInt<1>("h00") - managers[0].grant.ready := UInt<1>("h00") - managers[0].acquire.bits.client_id := UInt<1>("h00") - managers[0].acquire.bits.union := UInt<1>("h00") - managers[0].acquire.bits.a_type := UInt<1>("h00") - managers[0].acquire.bits.is_builtin_type := UInt<1>("h00") - managers[0].acquire.bits.data := UInt<1>("h00") - managers[0].acquire.bits.addr_beat := UInt<1>("h00") - managers[0].acquire.bits.client_xact_id := UInt<1>("h00") - managers[0].acquire.bits.addr_block := UInt<1>("h00") - managers[0].acquire.valid := UInt<1>("h00") - clients[0].release.ready := UInt<1>("h00") - clients[0].probe.bits.p_type := UInt<1>("h00") - clients[0].probe.bits.addr_block := UInt<1>("h00") - clients[0].probe.valid := UInt<1>("h00") - clients[0].grant.bits.g_type := UInt<1>("h00") - clients[0].grant.bits.is_builtin_type := UInt<1>("h00") - clients[0].grant.bits.manager_xact_id := UInt<1>("h00") - clients[0].grant.bits.client_xact_id := UInt<1>("h00") - clients[0].grant.bits.data := UInt<1>("h00") - clients[0].grant.bits.addr_beat := UInt<1>("h00") - clients[0].grant.valid := UInt<1>("h00") - clients[0].acquire.ready := UInt<1>("h00") - inst T_8589 of ClientTileLinkNetworkPort_37 - T_8589.network.release.ready := UInt<1>("h00") - T_8589.network.probe.bits.payload.p_type := UInt<1>("h00") - T_8589.network.probe.bits.payload.addr_block := UInt<1>("h00") - T_8589.network.probe.bits.header.dst := UInt<1>("h00") - T_8589.network.probe.bits.header.src := UInt<1>("h00") - T_8589.network.probe.valid := UInt<1>("h00") - T_8589.network.finish.ready := UInt<1>("h00") - T_8589.network.grant.bits.payload.g_type := UInt<1>("h00") - T_8589.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_8589.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_8589.network.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_8589.network.grant.bits.payload.data := UInt<1>("h00") - T_8589.network.grant.bits.payload.addr_beat := UInt<1>("h00") - T_8589.network.grant.bits.header.dst := UInt<1>("h00") - T_8589.network.grant.bits.header.src := UInt<1>("h00") - T_8589.network.grant.valid := UInt<1>("h00") - T_8589.network.acquire.ready := UInt<1>("h00") - T_8589.client.release.bits.voluntary := UInt<1>("h00") - T_8589.client.release.bits.r_type := UInt<1>("h00") - T_8589.client.release.bits.data := UInt<1>("h00") - T_8589.client.release.bits.addr_beat := UInt<1>("h00") - T_8589.client.release.bits.client_xact_id := UInt<1>("h00") - T_8589.client.release.bits.addr_block := UInt<1>("h00") - T_8589.client.release.valid := UInt<1>("h00") - T_8589.client.probe.ready := UInt<1>("h00") - T_8589.client.grant.ready := UInt<1>("h00") - T_8589.client.acquire.bits.union := UInt<1>("h00") - T_8589.client.acquire.bits.a_type := UInt<1>("h00") - T_8589.client.acquire.bits.is_builtin_type := UInt<1>("h00") - T_8589.client.acquire.bits.data := UInt<1>("h00") - T_8589.client.acquire.bits.addr_beat := UInt<1>("h00") - T_8589.client.acquire.bits.client_xact_id := UInt<1>("h00") - T_8589.client.acquire.bits.addr_block := UInt<1>("h00") - T_8589.client.acquire.valid := UInt<1>("h00") - T_8589.reset := UInt<1>("h00") - T_8589.clock := clock - T_8589.reset := reset - inst T_8590 of TileLinkEnqueuer_40 - T_8590.manager.release.ready := UInt<1>("h00") - T_8590.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_8590.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_8590.manager.probe.bits.header.dst := UInt<1>("h00") - T_8590.manager.probe.bits.header.src := UInt<1>("h00") - T_8590.manager.probe.valid := UInt<1>("h00") - T_8590.manager.finish.ready := UInt<1>("h00") - T_8590.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_8590.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_8590.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_8590.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_8590.manager.grant.bits.payload.data := UInt<1>("h00") - T_8590.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_8590.manager.grant.bits.header.dst := UInt<1>("h00") - T_8590.manager.grant.bits.header.src := UInt<1>("h00") - T_8590.manager.grant.valid := UInt<1>("h00") - T_8590.manager.acquire.ready := UInt<1>("h00") - T_8590.client.release.bits.payload.voluntary := UInt<1>("h00") - T_8590.client.release.bits.payload.r_type := UInt<1>("h00") - T_8590.client.release.bits.payload.data := UInt<1>("h00") - T_8590.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_8590.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_8590.client.release.bits.payload.addr_block := UInt<1>("h00") - T_8590.client.release.bits.header.dst := UInt<1>("h00") - T_8590.client.release.bits.header.src := UInt<1>("h00") - T_8590.client.release.valid := UInt<1>("h00") - T_8590.client.probe.ready := UInt<1>("h00") - T_8590.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_8590.client.finish.bits.header.dst := UInt<1>("h00") - T_8590.client.finish.bits.header.src := UInt<1>("h00") - T_8590.client.finish.valid := UInt<1>("h00") - T_8590.client.grant.ready := UInt<1>("h00") - T_8590.client.acquire.bits.payload.union := UInt<1>("h00") - T_8590.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_8590.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_8590.client.acquire.bits.payload.data := UInt<1>("h00") - T_8590.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_8590.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_8590.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_8590.client.acquire.bits.header.dst := UInt<1>("h00") - T_8590.client.acquire.bits.header.src := UInt<1>("h00") - T_8590.client.acquire.valid := UInt<1>("h00") - T_8590.reset := UInt<1>("h00") - T_8590.clock := clock - T_8590.reset := reset - T_8589.client <> clients[0] - T_8590.client <> T_8589.network - inst T_8591 of ManagerTileLinkNetworkPort_41 - T_8591.network.release.bits.payload.voluntary := UInt<1>("h00") - T_8591.network.release.bits.payload.r_type := UInt<1>("h00") - T_8591.network.release.bits.payload.data := UInt<1>("h00") - T_8591.network.release.bits.payload.addr_beat := UInt<1>("h00") - T_8591.network.release.bits.payload.client_xact_id := UInt<1>("h00") - T_8591.network.release.bits.payload.addr_block := UInt<1>("h00") - T_8591.network.release.bits.header.dst := UInt<1>("h00") - T_8591.network.release.bits.header.src := UInt<1>("h00") - T_8591.network.release.valid := UInt<1>("h00") - T_8591.network.probe.ready := UInt<1>("h00") - T_8591.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_8591.network.finish.bits.header.dst := UInt<1>("h00") - T_8591.network.finish.bits.header.src := UInt<1>("h00") - T_8591.network.finish.valid := UInt<1>("h00") - T_8591.network.grant.ready := UInt<1>("h00") - T_8591.network.acquire.bits.payload.union := UInt<1>("h00") - T_8591.network.acquire.bits.payload.a_type := UInt<1>("h00") - T_8591.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_8591.network.acquire.bits.payload.data := UInt<1>("h00") - T_8591.network.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_8591.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_8591.network.acquire.bits.payload.addr_block := UInt<1>("h00") - T_8591.network.acquire.bits.header.dst := UInt<1>("h00") - T_8591.network.acquire.bits.header.src := UInt<1>("h00") - T_8591.network.acquire.valid := UInt<1>("h00") - T_8591.manager.release.ready := UInt<1>("h00") - T_8591.manager.probe.bits.client_id := UInt<1>("h00") - T_8591.manager.probe.bits.p_type := UInt<1>("h00") - T_8591.manager.probe.bits.addr_block := UInt<1>("h00") - T_8591.manager.probe.valid := UInt<1>("h00") - T_8591.manager.finish.ready := UInt<1>("h00") - T_8591.manager.grant.bits.client_id := UInt<1>("h00") - T_8591.manager.grant.bits.g_type := UInt<1>("h00") - T_8591.manager.grant.bits.is_builtin_type := UInt<1>("h00") - T_8591.manager.grant.bits.manager_xact_id := UInt<1>("h00") - T_8591.manager.grant.bits.client_xact_id := UInt<1>("h00") - T_8591.manager.grant.bits.data := UInt<1>("h00") - T_8591.manager.grant.bits.addr_beat := UInt<1>("h00") - T_8591.manager.grant.valid := UInt<1>("h00") - T_8591.manager.acquire.ready := UInt<1>("h00") - T_8591.reset := UInt<1>("h00") - T_8591.clock := clock - T_8591.reset := reset - inst T_8592 of TileLinkEnqueuer_40 - T_8592.manager.release.ready := UInt<1>("h00") - T_8592.manager.probe.bits.payload.p_type := UInt<1>("h00") - T_8592.manager.probe.bits.payload.addr_block := UInt<1>("h00") - T_8592.manager.probe.bits.header.dst := UInt<1>("h00") - T_8592.manager.probe.bits.header.src := UInt<1>("h00") - T_8592.manager.probe.valid := UInt<1>("h00") - T_8592.manager.finish.ready := UInt<1>("h00") - T_8592.manager.grant.bits.payload.g_type := UInt<1>("h00") - T_8592.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") - T_8592.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") - T_8592.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") - T_8592.manager.grant.bits.payload.data := UInt<1>("h00") - T_8592.manager.grant.bits.payload.addr_beat := UInt<1>("h00") - T_8592.manager.grant.bits.header.dst := UInt<1>("h00") - T_8592.manager.grant.bits.header.src := UInt<1>("h00") - T_8592.manager.grant.valid := UInt<1>("h00") - T_8592.manager.acquire.ready := UInt<1>("h00") - T_8592.client.release.bits.payload.voluntary := UInt<1>("h00") - T_8592.client.release.bits.payload.r_type := UInt<1>("h00") - T_8592.client.release.bits.payload.data := UInt<1>("h00") - T_8592.client.release.bits.payload.addr_beat := UInt<1>("h00") - T_8592.client.release.bits.payload.client_xact_id := UInt<1>("h00") - T_8592.client.release.bits.payload.addr_block := UInt<1>("h00") - T_8592.client.release.bits.header.dst := UInt<1>("h00") - T_8592.client.release.bits.header.src := UInt<1>("h00") - T_8592.client.release.valid := UInt<1>("h00") - T_8592.client.probe.ready := UInt<1>("h00") - T_8592.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") - T_8592.client.finish.bits.header.dst := UInt<1>("h00") - T_8592.client.finish.bits.header.src := UInt<1>("h00") - T_8592.client.finish.valid := UInt<1>("h00") - T_8592.client.grant.ready := UInt<1>("h00") - T_8592.client.acquire.bits.payload.union := UInt<1>("h00") - T_8592.client.acquire.bits.payload.a_type := UInt<1>("h00") - T_8592.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") - T_8592.client.acquire.bits.payload.data := UInt<1>("h00") - T_8592.client.acquire.bits.payload.addr_beat := UInt<1>("h00") - T_8592.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") - T_8592.client.acquire.bits.payload.addr_block := UInt<1>("h00") - T_8592.client.acquire.bits.header.dst := UInt<1>("h00") - T_8592.client.acquire.bits.header.src := UInt<1>("h00") - T_8592.client.acquire.valid := UInt<1>("h00") - T_8592.reset := UInt<1>("h00") - T_8592.clock := clock - T_8592.reset := reset - T_8591.manager <> managers[0] - T_8591.network <> T_8592.manager - T_8592.client <> T_8590.manager - - module Arbiter : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.client_id := UInt<1>("h00") - out.bits.g_type := UInt<1>("h00") - out.bits.is_builtin_type := UInt<1>("h00") - out.bits.manager_xact_id := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_658 : UInt<1> - T_658 := UInt<1>("h00") - infer accessor T_660 = in[T_658] - out.valid := T_660.valid - infer accessor T_719 = in[T_658] - out.bits <> T_719.bits - chosen := T_658 - infer accessor T_778 = in[T_658] - T_778.ready := UInt<1>("h00") - node T_840 = or(UInt<1>("h00"), in[0].valid) - node T_842 = eq(T_840, UInt<1>("h00")) - node T_844 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_845 = mux(UInt<1>("h00"), T_844, UInt<1>("h01")) - node T_846 = and(T_845, out.ready) - in[0].ready := T_846 - node T_848 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_849 = mux(UInt<1>("h00"), T_848, T_842) - node T_850 = and(T_849, out.ready) - in[1].ready := T_850 - node T_853 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_854 = mux(UInt<1>("h00"), UInt<1>("h01"), T_853) - T_658 := T_854 - - module MemIOTileLinkIOConverter : - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - mem_1.resp.ready := UInt<1>("h00") - mem_1.req_data.bits.data := UInt<1>("h00") - mem_1.req_data.valid := UInt<1>("h00") - mem_1.req_cmd.bits.rw := UInt<1>("h00") - mem_1.req_cmd.bits.tag := UInt<1>("h00") - mem_1.req_cmd.bits.addr := UInt<1>("h00") - mem_1.req_cmd.valid := UInt<1>("h00") - tl.release.ready := UInt<1>("h00") - tl.probe.bits.client_id := UInt<1>("h00") - tl.probe.bits.p_type := UInt<1>("h00") - tl.probe.bits.addr_block := UInt<1>("h00") - tl.probe.valid := UInt<1>("h00") - tl.finish.ready := UInt<1>("h00") - tl.grant.bits.client_id := UInt<1>("h00") - tl.grant.bits.g_type := UInt<1>("h00") - tl.grant.bits.is_builtin_type := UInt<1>("h00") - tl.grant.bits.manager_xact_id := UInt<1>("h00") - tl.grant.bits.client_xact_id := UInt<1>("h00") - tl.grant.bits.data := UInt<1>("h00") - tl.grant.bits.addr_beat := UInt<1>("h00") - tl.grant.valid := UInt<1>("h00") - tl.acquire.ready := UInt<1>("h00") - tl.acquire.ready := UInt<1>("h00") - tl.probe.valid := UInt<1>("h00") - tl.release.ready := UInt<1>("h00") - tl.finish.ready := UInt<1>("h01") - mem_1.resp.ready := UInt<1>("h00") - inst gnt_arb of Arbiter - gnt_arb.out.ready := UInt<1>("h00") - gnt_arb.in[0].bits.client_id := UInt<1>("h00") - gnt_arb.in[0].bits.g_type := UInt<1>("h00") - gnt_arb.in[0].bits.is_builtin_type := UInt<1>("h00") - gnt_arb.in[0].bits.manager_xact_id := UInt<1>("h00") - gnt_arb.in[0].bits.client_xact_id := UInt<1>("h00") - gnt_arb.in[0].bits.data := UInt<1>("h00") - gnt_arb.in[0].bits.addr_beat := UInt<1>("h00") - gnt_arb.in[0].valid := UInt<1>("h00") - gnt_arb.in[1].bits.client_id := UInt<1>("h00") - gnt_arb.in[1].bits.g_type := UInt<1>("h00") - gnt_arb.in[1].bits.is_builtin_type := UInt<1>("h00") - gnt_arb.in[1].bits.manager_xact_id := UInt<1>("h00") - gnt_arb.in[1].bits.client_xact_id := UInt<1>("h00") - gnt_arb.in[1].bits.data := UInt<1>("h00") - gnt_arb.in[1].bits.addr_beat := UInt<1>("h00") - gnt_arb.in[1].valid := UInt<1>("h00") - gnt_arb.reset := UInt<1>("h00") - gnt_arb.clock := clock - gnt_arb.reset := reset - tl.grant <> gnt_arb.out - wire T_721 : UInt<3>[3] - T_721[0] := UInt<3>("h02") - T_721[1] := UInt<3>("h03") - T_721[2] := UInt<3>("h04") - node T_726 = eq(T_721[0], tl.acquire.bits.a_type) - node T_727 = eq(T_721[1], tl.acquire.bits.a_type) - node T_728 = eq(T_721[2], tl.acquire.bits.a_type) - node T_730 = or(UInt<1>("h00"), T_726) - node T_731 = or(T_730, T_727) - node T_732 = or(T_731, T_728) - node acq_has_data = and(tl.acquire.bits.is_builtin_type, T_732) - wire T_735 : UInt<2>[3] - T_735[0] := UInt<1>("h00") - T_735[1] := UInt<1>("h01") - T_735[2] := UInt<2>("h02") - node T_740 = eq(T_735[0], tl.release.bits.r_type) - node T_741 = eq(T_735[1], tl.release.bits.r_type) - node T_742 = eq(T_735[2], tl.release.bits.r_type) - node T_744 = or(UInt<1>("h00"), T_740) - node T_745 = or(T_744, T_741) - node rel_has_data = or(T_745, T_742) - reg active_out : UInt<1>, clock, reset - onreset active_out := UInt<1>("h00") - reg cmd_sent_out : UInt<1>, clock, reset - onreset cmd_sent_out := UInt<1>("h00") - reg tag_out : UInt<7>, clock, reset - reg addr_out : UInt<26>, clock, reset - reg has_data : UInt<1>, clock, reset - onreset has_data := UInt<1>("h00") - reg data_from_rel : UInt<1>, clock, reset - onreset data_from_rel := UInt<1>("h00") - node T_759 = and(tl.acquire.ready, tl.acquire.valid) - node T_760 = and(T_759, acq_has_data) - node T_761 = and(tl.release.ready, tl.release.valid) - node T_762 = and(T_761, rel_has_data) - node T_763 = or(T_760, T_762) - reg tl_cnt_out : UInt<2>, clock, reset - onreset tl_cnt_out := UInt<2>("h00") - when T_763 : - node T_767 = eq(tl_cnt_out, UInt<2>("h03")) - node T_769 = and(UInt<1>("h00"), T_767) - node T_772 = addw(tl_cnt_out, UInt<1>("h01")) - node T_773 = mux(T_769, UInt<1>("h00"), T_772) - tl_cnt_out := T_773 - skip - node tl_wrap_out = and(T_763, T_767) - reg tl_done_out : UInt<1>, clock, reset - onreset tl_done_out := UInt<1>("h00") - reg make_grant_ack : UInt<1>, clock, reset - onreset make_grant_ack := UInt<1>("h00") - gnt_arb.in[1].valid := UInt<1>("h00") - node T_780 = bits(tag_out, 5, 5) - node T_784 = mux(data_from_rel, UInt<3>("h00"), UInt<3>("h03")) - node T_785 = shr(tag_out, 1) - wire T_817 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>} - T_817.client_id := UInt<1>("h00") - T_817.g_type := UInt<1>("h00") - T_817.is_builtin_type := UInt<1>("h00") - T_817.manager_xact_id := UInt<1>("h00") - T_817.client_xact_id := UInt<1>("h00") - T_817.data := UInt<1>("h00") - T_817.addr_beat := UInt<1>("h00") - T_817.client_id := T_780 - T_817.is_builtin_type := UInt<1>("h01") - T_817.g_type := T_784 - T_817.client_xact_id := T_785 - T_817.manager_xact_id := UInt<1>("h00") - T_817.addr_beat := UInt<1>("h00") - T_817.data := UInt<1>("h00") - gnt_arb.in[1].bits <> T_817 - mem_1.req_cmd.valid := UInt<1>("h00") - mem_1.req_data.valid := UInt<1>("h00") - mem_1.req_cmd.bits.rw := has_data - mem_1.req_cmd.bits.tag := tag_out - mem_1.req_cmd.bits.addr := addr_out - node T_854 = mux(data_from_rel, tl.release.bits.data, tl.acquire.bits.data) - mem_1.req_data.bits.data := T_854 - node T_856 = eq(active_out, UInt<1>("h00")) - when T_856 : - tl.release.ready := mem_1.req_data.ready - node T_858 = eq(tl.release.valid, UInt<1>("h00")) - node T_859 = and(mem_1.req_data.ready, T_858) - tl.acquire.ready := T_859 - node T_860 = and(tl.release.valid, rel_has_data) - node T_861 = and(tl.acquire.valid, acq_has_data) - node T_862 = or(T_860, T_861) - mem_1.req_data.valid := T_862 - node T_863 = or(tl.release.valid, tl.acquire.valid) - node T_864 = and(mem_1.req_data.ready, T_863) - when T_864 : - node T_866 = eq(mem_1.req_cmd.ready, UInt<1>("h00")) - node T_867 = or(T_866, mem_1.req_data.valid) - active_out := T_867 - mem_1.req_cmd.valid := UInt<1>("h01") - cmd_sent_out := mem_1.req_cmd.ready - tl_done_out := tl_wrap_out - when tl.release.valid : - data_from_rel := UInt<1>("h01") - node T_872 = eq(UInt<1>("h00"), UInt<1>("h00")) - make_grant_ack := T_872 - mem_1.req_data.bits.data := tl.release.bits.data - node T_873 = cat(tl.release.bits.client_xact_id, tl.release.bits.voluntary) - node T_874 = cat(tl.release.bits.client_id, T_873) - mem_1.req_cmd.bits.tag := T_874 - mem_1.req_cmd.bits.addr := tl.release.bits.addr_block - mem_1.req_cmd.bits.rw := rel_has_data - tag_out := T_874 - addr_out := tl.release.bits.addr_block - has_data := rel_has_data - skip - else : - when tl.acquire.valid : - data_from_rel := UInt<1>("h00") - make_grant_ack := acq_has_data - mem_1.req_data.bits.data := tl.acquire.bits.data - mem_1.req_cmd.bits.rw := acq_has_data - node T_876 = cat(tl.acquire.bits.client_xact_id, tl.acquire.bits.is_builtin_type) - node T_877 = cat(tl.acquire.bits.client_id, T_876) - mem_1.req_cmd.bits.tag := T_877 - mem_1.req_cmd.bits.addr := tl.acquire.bits.addr_block - mem_1.req_cmd.bits.rw := acq_has_data - tag_out := T_877 - addr_out := tl.acquire.bits.addr_block - has_data := acq_has_data - skip - skip - skip - skip - when active_out : - node T_879 = eq(cmd_sent_out, UInt<1>("h00")) - mem_1.req_cmd.valid := T_879 - node T_880 = and(mem_1.req_cmd.ready, mem_1.req_cmd.valid) - node T_881 = or(cmd_sent_out, T_880) - cmd_sent_out := T_881 - node T_883 = eq(tl_done_out, UInt<1>("h00")) - node T_884 = and(has_data, T_883) - when T_884 : - when data_from_rel : - tl.release.ready := mem_1.req_data.ready - mem_1.req_data.valid := tl.release.valid - skip - else : - tl.acquire.ready := mem_1.req_data.ready - mem_1.req_data.valid := tl.acquire.valid - skip - skip - when tl_wrap_out : - tl_done_out := UInt<1>("h01") - skip - node T_886 = and(tl_done_out, make_grant_ack) - when T_886 : - gnt_arb.in[1].valid := UInt<1>("h01") - when gnt_arb.in[1].ready : - make_grant_ack := UInt<1>("h00") - skip - skip - node T_890 = eq(has_data, UInt<1>("h00")) - node T_891 = or(T_890, tl_done_out) - node T_892 = and(cmd_sent_out, T_891) - node T_894 = eq(make_grant_ack, UInt<1>("h00")) - node T_895 = and(T_892, T_894) - when T_895 : - active_out := UInt<1>("h00") - skip - skip - reg active_in : UInt<1>, clock, reset - onreset active_in := UInt<1>("h00") - node T_899 = and(tl.grant.ready, tl.grant.valid) - wire T_903 : UInt<3>[1] - T_903[0] := UInt<3>("h05") - node T_906 = eq(T_903[0], tl.grant.bits.g_type) - node T_908 = or(UInt<1>("h00"), T_906) - wire T_910 : UInt<1>[1] - T_910[0] := UInt<1>("h00") - node T_913 = eq(T_910[0], tl.grant.bits.g_type) - node T_915 = or(UInt<1>("h00"), T_913) - node T_916 = mux(tl.grant.bits.is_builtin_type, T_908, T_915) - node T_917 = and(UInt<1>("h01"), T_916) - node T_918 = and(T_899, T_917) - reg tl_cnt_in : UInt<2>, clock, reset - onreset tl_cnt_in := UInt<2>("h00") - when T_918 : - node T_922 = eq(tl_cnt_in, UInt<2>("h03")) - node T_924 = and(UInt<1>("h00"), T_922) - node T_927 = addw(tl_cnt_in, UInt<1>("h01")) - node T_928 = mux(T_924, UInt<1>("h00"), T_927) - tl_cnt_in := T_928 - skip - node tl_wrap_in = and(T_918, T_922) - reg tag_in : UInt<7>, clock, reset - gnt_arb.in[0].valid := mem_1.resp.valid - mem_1.resp.ready := gnt_arb.in[0].ready - node T_932 = bits(mem_1.resp.bits.tag, 5, 5) - node T_933 = bit(mem_1.resp.bits.tag, 0) - node T_934 = bit(mem_1.resp.bits.tag, 0) - node T_937 = mux(T_934, UInt<3>("h05"), UInt<1>("h00")) - node T_938 = shr(mem_1.resp.bits.tag, 1) - wire T_968 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>} - T_968.client_id := UInt<1>("h00") - T_968.g_type := UInt<1>("h00") - T_968.is_builtin_type := UInt<1>("h00") - T_968.manager_xact_id := UInt<1>("h00") - T_968.client_xact_id := UInt<1>("h00") - T_968.data := UInt<1>("h00") - T_968.addr_beat := UInt<1>("h00") - T_968.client_id := T_932 - T_968.is_builtin_type := T_933 - T_968.g_type := T_937 - T_968.client_xact_id := T_938 - T_968.manager_xact_id := UInt<1>("h00") - T_968.addr_beat := tl_cnt_in - T_968.data := mem_1.resp.bits.data - gnt_arb.in[0].bits <> T_968 - - module HellaFlowQueue : - output count : UInt<6> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.data := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - wire do_flow : UInt<1> - do_flow := UInt<1>("h00") - node T_35 = and(enq.ready, enq.valid) - node T_37 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_35, T_37) - node T_39 = and(deq.ready, deq.valid) - node T_41 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_39, T_41) - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - reg enq_ptr : UInt<6>, clock, reset - onreset enq_ptr := UInt<6>("h00") - when do_enq : - node T_48 = eq(enq_ptr, UInt<6>("h023")) - node T_50 = and(UInt<1>("h01"), T_48) - node T_53 = addw(enq_ptr, UInt<1>("h01")) - node T_54 = mux(T_50, UInt<1>("h00"), T_53) - enq_ptr := T_54 - skip - node T_55 = and(do_enq, T_48) - reg deq_ptr : UInt<6>, clock, reset - onreset deq_ptr := UInt<6>("h00") - when do_deq : - node T_59 = eq(deq_ptr, UInt<6>("h023")) - node T_61 = and(UInt<1>("h01"), T_59) - node T_64 = addw(deq_ptr, UInt<1>("h01")) - node T_65 = mux(T_61, UInt<1>("h00"), T_64) - deq_ptr := T_65 - skip - node deq_done = and(do_deq, T_59) - node T_67 = neq(do_enq, do_deq) - when T_67 : - maybe_full := do_enq - skip - node ptr_match = eq(enq_ptr, deq_ptr) - node T_70 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_70) - node full = and(ptr_match, maybe_full) - node T_73 = subw(enq_ptr, deq_ptr) - node T_75 = geq(T_73, UInt<2>("h02")) - node atLeastTwo = or(full, T_75) - node T_77 = and(empty, deq.ready) - do_flow := T_77 - cmem T_82 : {data : UInt<128>}[36], clock - when do_enq : - infer accessor T_83 = T_82[enq_ptr] - T_83 <> enq.bits - skip - node T_86 = eq(deq.valid, UInt<1>("h00")) - node T_88 = eq(empty, UInt<1>("h00")) - node T_89 = and(T_86, T_88) - node T_90 = or(atLeastTwo, T_89) - node ren = and(deq.ready, T_90) - node T_94 = addw(deq_ptr, UInt<1>("h01")) - node T_95 = mux(deq_done, UInt<1>("h00"), T_94) - node raddr = mux(deq.valid, T_95, deq_ptr) - reg ram_out_valid : UInt<1>, clock, reset - ram_out_valid := ren - node T_98 = mux(empty, enq.valid, ram_out_valid) - deq.valid := T_98 - node T_100 = eq(full, UInt<1>("h00")) - enq.ready := T_100 - reg T_101 : UInt<6>, clock, reset - when ren : - T_101 := raddr - skip - infer accessor T_102 = T_82[T_101] - wire T_106 : {data : UInt<128>} - T_106 <> T_102 - when empty : - T_106 <> enq.bits - skip - deq.bits <> T_106 - - module Queue_43 : - output count : UInt<1> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.data := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {data : UInt<128>}[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_39 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_39) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_45 = and(enq.ready, enq.valid) - node T_47 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_45, T_47) - node T_49 = and(deq.ready, deq.valid) - node T_51 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_49, T_51) - when do_enq : - infer accessor T_53 = ram[UInt<1>("h00")] - T_53 <> enq.bits - skip - when do_deq : - skip - node T_57 = neq(do_enq, do_deq) - when T_57 : - maybe_full := do_enq - skip - node T_59 = eq(empty, UInt<1>("h00")) - node T_61 = and(UInt<1>("h00"), enq.valid) - node T_62 = or(T_59, T_61) - deq.valid := T_62 - node T_64 = eq(full, UInt<1>("h00")) - node T_66 = and(UInt<1>("h01"), deq.ready) - node T_67 = or(T_64, T_66) - enq.ready := T_67 - infer accessor T_68 = ram[UInt<1>("h00")] - wire T_72 : {data : UInt<128>} - T_72 <> T_68 - when maybe_flow : - T_72 <> enq.bits - skip - deq.bits <> T_72 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_75 = and(maybe_full, ptr_match) - node T_76 = cat(T_75, ptr_diff) - count := T_76 - - module HellaQueue : - output count : UInt<6> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.data := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - inst fq of HellaFlowQueue - fq.deq.ready := UInt<1>("h00") - fq.enq.bits.data := UInt<1>("h00") - fq.enq.valid := UInt<1>("h00") - fq.reset := UInt<1>("h00") - fq.clock := clock - fq.reset := reset - fq.enq <> enq - inst T_43 of Queue_43 - T_43.deq.ready := UInt<1>("h00") - T_43.enq.bits.data := UInt<1>("h00") - T_43.enq.valid := UInt<1>("h00") - T_43.reset := UInt<1>("h00") - T_43.clock := clock - T_43.reset := reset - T_43.enq.valid := fq.deq.valid - T_43.enq.bits <> fq.deq.bits - fq.deq.ready := T_43.enq.ready - deq <> T_43.deq - - module HellaFlowQueue_45 : - output count : UInt<6> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.tag := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - wire do_flow : UInt<1> - do_flow := UInt<1>("h00") - node T_35 = and(enq.ready, enq.valid) - node T_37 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_35, T_37) - node T_39 = and(deq.ready, deq.valid) - node T_41 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_39, T_41) - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - reg enq_ptr : UInt<6>, clock, reset - onreset enq_ptr := UInt<6>("h00") - when do_enq : - node T_48 = eq(enq_ptr, UInt<6>("h023")) - node T_50 = and(UInt<1>("h01"), T_48) - node T_53 = addw(enq_ptr, UInt<1>("h01")) - node T_54 = mux(T_50, UInt<1>("h00"), T_53) - enq_ptr := T_54 - skip - node T_55 = and(do_enq, T_48) - reg deq_ptr : UInt<6>, clock, reset - onreset deq_ptr := UInt<6>("h00") - when do_deq : - node T_59 = eq(deq_ptr, UInt<6>("h023")) - node T_61 = and(UInt<1>("h01"), T_59) - node T_64 = addw(deq_ptr, UInt<1>("h01")) - node T_65 = mux(T_61, UInt<1>("h00"), T_64) - deq_ptr := T_65 - skip - node deq_done = and(do_deq, T_59) - node T_67 = neq(do_enq, do_deq) - when T_67 : - maybe_full := do_enq - skip - node ptr_match = eq(enq_ptr, deq_ptr) - node T_70 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_70) - node full = and(ptr_match, maybe_full) - node T_73 = subw(enq_ptr, deq_ptr) - node T_75 = geq(T_73, UInt<2>("h02")) - node atLeastTwo = or(full, T_75) - node T_77 = and(empty, deq.ready) - do_flow := T_77 - cmem T_82 : {tag : UInt<7>}[36], clock - when do_enq : - infer accessor T_83 = T_82[enq_ptr] - T_83 <> enq.bits - skip - node T_86 = eq(deq.valid, UInt<1>("h00")) - node T_88 = eq(empty, UInt<1>("h00")) - node T_89 = and(T_86, T_88) - node T_90 = or(atLeastTwo, T_89) - node ren = and(deq.ready, T_90) - node T_94 = addw(deq_ptr, UInt<1>("h01")) - node T_95 = mux(deq_done, UInt<1>("h00"), T_94) - node raddr = mux(deq.valid, T_95, deq_ptr) - reg ram_out_valid : UInt<1>, clock, reset - ram_out_valid := ren - node T_98 = mux(empty, enq.valid, ram_out_valid) - deq.valid := T_98 - node T_100 = eq(full, UInt<1>("h00")) - enq.ready := T_100 - reg T_101 : UInt<6>, clock, reset - when ren : - T_101 := raddr - skip - infer accessor T_102 = T_82[T_101] - wire T_106 : {tag : UInt<7>} - T_106 <> T_102 - when empty : - T_106 <> enq.bits - skip - deq.bits <> T_106 - - module Queue_46 : - output count : UInt<1> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.tag := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {tag : UInt<7>}[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_39 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_39) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_45 = and(enq.ready, enq.valid) - node T_47 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_45, T_47) - node T_49 = and(deq.ready, deq.valid) - node T_51 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_49, T_51) - when do_enq : - infer accessor T_53 = ram[UInt<1>("h00")] - T_53 <> enq.bits - skip - when do_deq : - skip - node T_57 = neq(do_enq, do_deq) - when T_57 : - maybe_full := do_enq - skip - node T_59 = eq(empty, UInt<1>("h00")) - node T_61 = and(UInt<1>("h00"), enq.valid) - node T_62 = or(T_59, T_61) - deq.valid := T_62 - node T_64 = eq(full, UInt<1>("h00")) - node T_66 = and(UInt<1>("h01"), deq.ready) - node T_67 = or(T_64, T_66) - enq.ready := T_67 - infer accessor T_68 = ram[UInt<1>("h00")] - wire T_72 : {tag : UInt<7>} - T_72 <> T_68 - when maybe_flow : - T_72 <> enq.bits - skip - deq.bits <> T_72 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_75 = and(maybe_full, ptr_match) - node T_76 = cat(T_75, ptr_diff) - count := T_76 - - module HellaQueue_44 : - output count : UInt<6> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.tag := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - inst fq of HellaFlowQueue_45 - fq.deq.ready := UInt<1>("h00") - fq.enq.bits.tag := UInt<1>("h00") - fq.enq.valid := UInt<1>("h00") - fq.reset := UInt<1>("h00") - fq.clock := clock - fq.reset := reset - fq.enq <> enq - inst T_43 of Queue_46 - T_43.deq.ready := UInt<1>("h00") - T_43.enq.bits.tag := UInt<1>("h00") - T_43.enq.valid := UInt<1>("h00") - T_43.reset := UInt<1>("h00") - T_43.clock := clock - T_43.reset := reset - T_43.enq.valid := fq.deq.valid - T_43.enq.bits <> fq.deq.bits - fq.deq.ready := T_43.enq.ready - deq <> T_43.deq - - module MemPipeIOMemIOConverter : - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - input cpu : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - input clock : Clock - input reset : UInt<1> - - mem_1.req_data.bits.data := UInt<1>("h00") - mem_1.req_data.valid := UInt<1>("h00") - mem_1.req_cmd.bits.rw := UInt<1>("h00") - mem_1.req_cmd.bits.tag := UInt<1>("h00") - mem_1.req_cmd.bits.addr := UInt<1>("h00") - mem_1.req_cmd.valid := UInt<1>("h00") - cpu.resp.bits.tag := UInt<1>("h00") - cpu.resp.bits.data := UInt<1>("h00") - cpu.resp.valid := UInt<1>("h00") - cpu.req_data.ready := UInt<1>("h00") - cpu.req_cmd.ready := UInt<1>("h00") - wire inc : UInt<1> - inc := UInt<1>("h00") - wire dec : UInt<1> - dec := UInt<1>("h00") - reg count : UInt<6>, clock, reset - onreset count := UInt<6>("h024") - node watermark = geq(count, UInt<3>("h04")) - node T_151 = eq(dec, UInt<1>("h00")) - node T_152 = and(inc, T_151) - when T_152 : - node T_154 = addw(count, UInt<1>("h01")) - count := T_154 - skip - node T_156 = eq(inc, UInt<1>("h00")) - node T_157 = and(T_156, dec) - when T_157 : - node T_159 = subw(count, UInt<3>("h04")) - count := T_159 - skip - node T_160 = and(inc, dec) - when T_160 : - node T_162 = subw(count, UInt<2>("h03")) - count := T_162 - skip - node cmdq_mask = or(cpu.req_cmd.bits.rw, watermark) - node T_164 = and(cpu.req_cmd.valid, cmdq_mask) - mem_1.req_cmd.valid := T_164 - node T_165 = and(mem_1.req_cmd.ready, cmdq_mask) - cpu.req_cmd.ready := T_165 - mem_1.req_cmd.bits <> cpu.req_cmd.bits - mem_1.req_data <> cpu.req_data - inst resp_data_q of HellaQueue - resp_data_q.deq.ready := UInt<1>("h00") - resp_data_q.enq.bits.data := UInt<1>("h00") - resp_data_q.enq.valid := UInt<1>("h00") - resp_data_q.reset := UInt<1>("h00") - resp_data_q.clock := clock - resp_data_q.reset := reset - resp_data_q.enq.valid := mem_1.resp.valid - resp_data_q.enq.bits.data := mem_1.resp.bits.data - inst resp_tag_q of HellaQueue_44 - resp_tag_q.deq.ready := UInt<1>("h00") - resp_tag_q.enq.bits.tag := UInt<1>("h00") - resp_tag_q.enq.valid := UInt<1>("h00") - resp_tag_q.reset := UInt<1>("h00") - resp_tag_q.clock := clock - resp_tag_q.reset := reset - resp_tag_q.enq.valid := mem_1.resp.valid - resp_tag_q.enq.bits.tag := mem_1.resp.bits.tag - node T_174 = and(resp_data_q.deq.valid, resp_tag_q.deq.valid) - cpu.resp.valid := T_174 - cpu.resp.bits.data := resp_data_q.deq.bits.data - cpu.resp.bits.tag := resp_tag_q.deq.bits.tag - resp_data_q.deq.ready := cpu.resp.ready - resp_tag_q.deq.ready := cpu.resp.ready - node T_175 = and(resp_data_q.deq.ready, resp_data_q.deq.valid) - node T_176 = and(resp_tag_q.deq.ready, resp_tag_q.deq.valid) - node T_177 = and(T_175, T_176) - inc := T_177 - node T_178 = and(mem_1.req_cmd.ready, mem_1.req_cmd.valid) - node T_180 = eq(mem_1.req_cmd.bits.rw, UInt<1>("h00")) - node T_181 = and(T_178, T_180) - dec := T_181 - - module Queue_47 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.rw := UInt<1>("h00") - deq.bits.tag := UInt<1>("h00") - deq.bits.addr := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}[2], clock - reg T_52 : UInt<1>, clock, reset - onreset T_52 := UInt<1>("h00") - reg T_54 : UInt<1>, clock, reset - onreset T_54 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_52, T_54) - node T_59 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_59) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_65 = and(enq.ready, enq.valid) - node T_67 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_65, T_67) - node T_69 = and(deq.ready, deq.valid) - node T_71 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_69, T_71) - when do_enq : - infer accessor T_73 = ram[T_52] - T_73 <> enq.bits - node T_78 = eq(T_52, UInt<1>("h01")) - node T_80 = and(UInt<1>("h00"), T_78) - node T_83 = addw(T_52, UInt<1>("h01")) - node T_84 = mux(T_80, UInt<1>("h00"), T_83) - T_52 := T_84 - skip - when do_deq : - node T_86 = eq(T_54, UInt<1>("h01")) - node T_88 = and(UInt<1>("h00"), T_86) - node T_91 = addw(T_54, UInt<1>("h01")) - node T_92 = mux(T_88, UInt<1>("h00"), T_91) - T_54 := T_92 - skip - node T_93 = neq(do_enq, do_deq) - when T_93 : - maybe_full := do_enq - skip - node T_95 = eq(empty, UInt<1>("h00")) - node T_97 = and(UInt<1>("h00"), enq.valid) - node T_98 = or(T_95, T_97) - deq.valid := T_98 - node T_100 = eq(full, UInt<1>("h00")) - node T_102 = and(UInt<1>("h01"), deq.ready) - node T_103 = or(T_100, T_102) - enq.ready := T_103 - infer accessor T_104 = ram[T_54] - wire T_112 : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>} - T_112 <> T_104 - when maybe_flow : - T_112 <> enq.bits - skip - deq.bits <> T_112 - node ptr_diff = subw(T_52, T_54) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - count := T_118 - - module Queue_48 : - output count : UInt<3> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.data := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {data : UInt<128>}[4], clock - reg T_34 : UInt<2>, clock, reset - onreset T_34 := UInt<2>("h00") - reg T_36 : UInt<2>, clock, reset - onreset T_36 := UInt<2>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_34, T_36) - node T_41 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_41) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_47 = and(enq.ready, enq.valid) - node T_49 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_47, T_49) - node T_51 = and(deq.ready, deq.valid) - node T_53 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_51, T_53) - when do_enq : - infer accessor T_55 = ram[T_34] - T_55 <> enq.bits - node T_58 = eq(T_34, UInt<2>("h03")) - node T_60 = and(UInt<1>("h00"), T_58) - node T_63 = addw(T_34, UInt<1>("h01")) - node T_64 = mux(T_60, UInt<1>("h00"), T_63) - T_34 := T_64 - skip - when do_deq : - node T_66 = eq(T_36, UInt<2>("h03")) - node T_68 = and(UInt<1>("h00"), T_66) - node T_71 = addw(T_36, UInt<1>("h01")) - node T_72 = mux(T_68, UInt<1>("h00"), T_71) - T_36 := T_72 - skip - node T_73 = neq(do_enq, do_deq) - when T_73 : - maybe_full := do_enq - skip - node T_75 = eq(empty, UInt<1>("h00")) - node T_77 = and(UInt<1>("h00"), enq.valid) - node T_78 = or(T_75, T_77) - deq.valid := T_78 - node T_80 = eq(full, UInt<1>("h00")) - node T_82 = and(UInt<1>("h01"), deq.ready) - node T_83 = or(T_80, T_82) - enq.ready := T_83 - infer accessor T_84 = ram[T_36] - wire T_88 : {data : UInt<128>} - T_88 <> T_84 - when maybe_flow : - T_88 <> enq.bits - skip - deq.bits <> T_88 - node ptr_diff = subw(T_34, T_36) - node T_91 = and(maybe_full, ptr_match) - node T_92 = cat(T_91, ptr_diff) - count := T_92 - - module MemPipeIOTileLinkIOConverter : - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - mem_1.req_data.bits.data := UInt<1>("h00") - mem_1.req_data.valid := UInt<1>("h00") - mem_1.req_cmd.bits.rw := UInt<1>("h00") - mem_1.req_cmd.bits.tag := UInt<1>("h00") - mem_1.req_cmd.bits.addr := UInt<1>("h00") - mem_1.req_cmd.valid := UInt<1>("h00") - tl.release.ready := UInt<1>("h00") - tl.probe.bits.client_id := UInt<1>("h00") - tl.probe.bits.p_type := UInt<1>("h00") - tl.probe.bits.addr_block := UInt<1>("h00") - tl.probe.valid := UInt<1>("h00") - tl.finish.ready := UInt<1>("h00") - tl.grant.bits.client_id := UInt<1>("h00") - tl.grant.bits.g_type := UInt<1>("h00") - tl.grant.bits.is_builtin_type := UInt<1>("h00") - tl.grant.bits.manager_xact_id := UInt<1>("h00") - tl.grant.bits.client_xact_id := UInt<1>("h00") - tl.grant.bits.data := UInt<1>("h00") - tl.grant.bits.addr_beat := UInt<1>("h00") - tl.grant.valid := UInt<1>("h00") - tl.acquire.ready := UInt<1>("h00") - inst a of MemIOTileLinkIOConverter - a.mem_1.resp.bits.tag := UInt<1>("h00") - a.mem_1.resp.bits.data := UInt<1>("h00") - a.mem_1.resp.valid := UInt<1>("h00") - a.mem_1.req_data.ready := UInt<1>("h00") - a.mem_1.req_cmd.ready := UInt<1>("h00") - a.tl.release.bits.client_id := UInt<1>("h00") - a.tl.release.bits.voluntary := UInt<1>("h00") - a.tl.release.bits.r_type := UInt<1>("h00") - a.tl.release.bits.data := UInt<1>("h00") - a.tl.release.bits.addr_beat := UInt<1>("h00") - a.tl.release.bits.client_xact_id := UInt<1>("h00") - a.tl.release.bits.addr_block := UInt<1>("h00") - a.tl.release.valid := UInt<1>("h00") - a.tl.probe.ready := UInt<1>("h00") - a.tl.finish.bits.manager_xact_id := UInt<1>("h00") - a.tl.finish.valid := UInt<1>("h00") - a.tl.grant.ready := UInt<1>("h00") - a.tl.acquire.bits.client_id := UInt<1>("h00") - a.tl.acquire.bits.union := UInt<1>("h00") - a.tl.acquire.bits.a_type := UInt<1>("h00") - a.tl.acquire.bits.is_builtin_type := UInt<1>("h00") - a.tl.acquire.bits.data := UInt<1>("h00") - a.tl.acquire.bits.addr_beat := UInt<1>("h00") - a.tl.acquire.bits.client_xact_id := UInt<1>("h00") - a.tl.acquire.bits.addr_block := UInt<1>("h00") - a.tl.acquire.valid := UInt<1>("h00") - a.reset := UInt<1>("h00") - a.clock := clock - a.reset := reset - inst b of MemPipeIOMemIOConverter - b.mem_1.resp.bits.tag := UInt<1>("h00") - b.mem_1.resp.bits.data := UInt<1>("h00") - b.mem_1.resp.valid := UInt<1>("h00") - b.mem_1.req_data.ready := UInt<1>("h00") - b.mem_1.req_cmd.ready := UInt<1>("h00") - b.cpu.resp.ready := UInt<1>("h00") - b.cpu.req_data.bits.data := UInt<1>("h00") - b.cpu.req_data.valid := UInt<1>("h00") - b.cpu.req_cmd.bits.rw := UInt<1>("h00") - b.cpu.req_cmd.bits.tag := UInt<1>("h00") - b.cpu.req_cmd.bits.addr := UInt<1>("h00") - b.cpu.req_cmd.valid := UInt<1>("h00") - b.reset := UInt<1>("h00") - b.clock := clock - b.reset := reset - tl <> a.tl - inst T_702 of Queue_47 - T_702.deq.ready := UInt<1>("h00") - T_702.enq.bits.rw := UInt<1>("h00") - T_702.enq.bits.tag := UInt<1>("h00") - T_702.enq.bits.addr := UInt<1>("h00") - T_702.enq.valid := UInt<1>("h00") - T_702.reset := UInt<1>("h00") - T_702.clock := clock - T_702.reset := reset - T_702.enq.valid := a.mem_1.req_cmd.valid - T_702.enq.bits <> a.mem_1.req_cmd.bits - a.mem_1.req_cmd.ready := T_702.enq.ready - b.cpu.req_cmd <> T_702.deq - inst T_703 of Queue_48 - T_703.deq.ready := UInt<1>("h00") - T_703.enq.bits.data := UInt<1>("h00") - T_703.enq.valid := UInt<1>("h00") - T_703.reset := UInt<1>("h00") - T_703.clock := clock - T_703.reset := reset - T_703.enq.valid := a.mem_1.req_data.valid - T_703.enq.bits <> a.mem_1.req_data.bits - a.mem_1.req_data.ready := T_703.enq.ready - b.cpu.req_data <> T_703.deq - a.mem_1.resp <> b.cpu.resp - mem_1 <> b.mem_1 - - module ClientTileLinkIOWrapper_49 : - output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input clock : Clock - input reset : UInt<1> - - out.release.bits.voluntary := UInt<1>("h00") - out.release.bits.r_type := UInt<1>("h00") - out.release.bits.data := UInt<1>("h00") - out.release.bits.addr_beat := UInt<1>("h00") - out.release.bits.client_xact_id := UInt<1>("h00") - out.release.bits.addr_block := UInt<1>("h00") - out.release.valid := UInt<1>("h00") - out.probe.ready := UInt<1>("h00") - out.grant.ready := UInt<1>("h00") - out.acquire.bits.union := UInt<1>("h00") - out.acquire.bits.a_type := UInt<1>("h00") - out.acquire.bits.is_builtin_type := UInt<1>("h00") - out.acquire.bits.data := UInt<1>("h00") - out.acquire.bits.addr_beat := UInt<1>("h00") - out.acquire.bits.client_xact_id := UInt<1>("h00") - out.acquire.bits.addr_block := UInt<1>("h00") - out.acquire.valid := UInt<1>("h00") - in.grant.bits.g_type := UInt<1>("h00") - in.grant.bits.is_builtin_type := UInt<1>("h00") - in.grant.bits.manager_xact_id := UInt<1>("h00") - in.grant.bits.client_xact_id := UInt<1>("h00") - in.grant.bits.data := UInt<1>("h00") - in.grant.bits.addr_beat := UInt<1>("h00") - in.grant.valid := UInt<1>("h00") - in.acquire.ready := UInt<1>("h00") - out.acquire <> in.acquire - in.grant <> out.grant - out.probe.ready := UInt<1>("h01") - out.release.valid := UInt<1>("h00") - - module MemIOArbiter : - output outer : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - input inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] - input clock : Clock - input reset : UInt<1> - - outer.resp.ready := UInt<1>("h00") - outer.req_data.bits.data := UInt<1>("h00") - outer.req_data.valid := UInt<1>("h00") - outer.req_cmd.bits.rw := UInt<1>("h00") - outer.req_cmd.bits.tag := UInt<1>("h00") - outer.req_cmd.bits.addr := UInt<1>("h00") - outer.req_cmd.valid := UInt<1>("h00") - inner[0].resp.bits.tag := UInt<1>("h00") - inner[0].resp.bits.data := UInt<1>("h00") - inner[0].resp.valid := UInt<1>("h00") - inner[0].req_data.ready := UInt<1>("h00") - inner[0].req_cmd.ready := UInt<1>("h00") - outer <> inner[0] - - module MemSerdes : - output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} - input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - input clock : Clock - input reset : UInt<1> - - narrow.req.bits := UInt<1>("h00") - narrow.req.valid := UInt<1>("h00") - wide.resp.bits.tag := UInt<1>("h00") - wide.resp.bits.data := UInt<1>("h00") - wide.resp.valid := UInt<1>("h00") - wide.req_data.ready := UInt<1>("h00") - wide.req_cmd.ready := UInt<1>("h00") - node T_111 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_112 = cat(wide.req_cmd.bits.addr, T_111) - reg out_buf : UInt, clock, reset - reg in_buf : UInt, clock, reset - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg send_cnt : UInt<3>, clock, reset - onreset send_cnt := UInt<3>("h00") - reg data_send_cnt : UInt<2>, clock, reset - onreset data_send_cnt := UInt<2>("h00") - node T_129 = eq(send_cnt, UInt<2>("h02")) - node adone = and(narrow.req.ready, T_129) - node T_132 = eq(send_cnt, UInt<3>("h07")) - node ddone = and(narrow.req.ready, T_132) - node T_134 = and(narrow.req.valid, narrow.req.ready) - when T_134 : - node T_136 = addw(send_cnt, UInt<1>("h01")) - send_cnt := T_136 - node T_138 = dshr(out_buf, UInt<5>("h010")) - out_buf := T_138 - skip - node T_139 = and(wide.req_cmd.valid, wide.req_cmd.ready) - when T_139 : - node T_140 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_141 = cat(wide.req_cmd.bits.addr, T_140) - out_buf := T_141 - skip - node T_142 = and(wide.req_data.valid, wide.req_data.ready) - when T_142 : - out_buf := wide.req_data.bits.data - skip - node T_143 = eq(state, UInt<1>("h00")) - wide.req_cmd.ready := T_143 - node T_144 = eq(state, UInt<2>("h03")) - wide.req_data.ready := T_144 - node T_145 = eq(state, UInt<1>("h01")) - node T_146 = eq(state, UInt<2>("h02")) - node T_147 = or(T_145, T_146) - node T_148 = eq(state, UInt<3>("h04")) - node T_149 = or(T_147, T_148) - narrow.req.valid := T_149 - narrow.req.bits := out_buf - node T_150 = eq(state, UInt<1>("h00")) - node T_151 = and(T_150, wide.req_cmd.valid) - when T_151 : - node T_152 = mux(wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) - state := T_152 - skip - node T_153 = eq(state, UInt<1>("h01")) - node T_154 = and(T_153, adone) - when T_154 : - state := UInt<1>("h00") - send_cnt := UInt<1>("h00") - skip - node T_156 = eq(state, UInt<2>("h02")) - node T_157 = and(T_156, adone) - when T_157 : - state := UInt<2>("h03") - send_cnt := UInt<1>("h00") - skip - node T_159 = eq(state, UInt<2>("h03")) - node T_160 = and(T_159, wide.req_data.valid) - when T_160 : - state := UInt<3>("h04") - skip - node T_161 = eq(state, UInt<3>("h04")) - node T_162 = and(T_161, ddone) - when T_162 : - node T_164 = addw(data_send_cnt, UInt<1>("h01")) - data_send_cnt := T_164 - node T_166 = eq(data_send_cnt, UInt<2>("h03")) - node T_167 = mux(T_166, UInt<1>("h00"), UInt<2>("h03")) - state := T_167 - send_cnt := UInt<1>("h00") - skip - reg recv_cnt : UInt<4>, clock, reset - onreset recv_cnt := UInt<4>("h00") - reg data_recv_cnt : UInt<2>, clock, reset - onreset data_recv_cnt := UInt<2>("h00") - reg resp_val : UInt<1>, clock, reset - onreset resp_val := UInt<1>("h00") - resp_val := UInt<1>("h00") - when narrow.resp.valid : - node T_177 = addw(recv_cnt, UInt<1>("h01")) - recv_cnt := T_177 - node T_179 = eq(recv_cnt, UInt<4>("h08")) - when T_179 : - recv_cnt := UInt<1>("h00") - node T_182 = addw(data_recv_cnt, UInt<1>("h01")) - data_recv_cnt := T_182 - resp_val := UInt<1>("h01") - skip - node T_184 = bits(in_buf, 143, 16) - node T_185 = cat(narrow.resp.bits, T_184) - in_buf := T_185 - skip - wide.resp.valid := resp_val - wire T_189 : {data : UInt<128>, tag : UInt<7>} - T_189.tag := UInt<1>("h00") - T_189.data := UInt<1>("h00") - node T_194 = bits(in_buf, 6, 0) - T_189.tag := T_194 - node T_195 = bits(in_buf, 134, 7) - T_189.data := T_195 - wide.resp.bits <> T_189 - - module OuterMemorySystem : - input mem_backup_en : UInt<1> - output mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] - input incoherent : UInt<1>[1] - input htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1] - input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] - input clock : Clock - input reset : UInt<1> - - mem_backup.req.bits := UInt<1>("h00") - mem_backup.req.valid := UInt<1>("h00") - mem_1[0].resp.ready := UInt<1>("h00") - mem_1[0].req_data.bits.data := UInt<1>("h00") - mem_1[0].req_data.valid := UInt<1>("h00") - mem_1[0].req_cmd.bits.rw := UInt<1>("h00") - mem_1[0].req_cmd.bits.tag := UInt<1>("h00") - mem_1[0].req_cmd.bits.addr := UInt<1>("h00") - mem_1[0].req_cmd.valid := UInt<1>("h00") - htif_uncached.grant.bits.g_type := UInt<1>("h00") - htif_uncached.grant.bits.is_builtin_type := UInt<1>("h00") - htif_uncached.grant.bits.manager_xact_id := UInt<1>("h00") - htif_uncached.grant.bits.client_xact_id := UInt<1>("h00") - htif_uncached.grant.bits.data := UInt<1>("h00") - htif_uncached.grant.bits.addr_beat := UInt<1>("h00") - htif_uncached.grant.valid := UInt<1>("h00") - htif_uncached.acquire.ready := UInt<1>("h00") - tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") - tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") - tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") - tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") - tiles_uncached[0].grant.bits.data := UInt<1>("h00") - tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") - tiles_uncached[0].grant.valid := UInt<1>("h00") - tiles_uncached[0].acquire.ready := UInt<1>("h00") - tiles_cached[0].release.ready := UInt<1>("h00") - tiles_cached[0].probe.bits.p_type := UInt<1>("h00") - tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") - tiles_cached[0].probe.valid := UInt<1>("h00") - tiles_cached[0].grant.bits.g_type := UInt<1>("h00") - tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") - tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") - tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") - tiles_cached[0].grant.bits.data := UInt<1>("h00") - tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") - tiles_cached[0].grant.valid := UInt<1>("h00") - tiles_cached[0].acquire.ready := UInt<1>("h00") - inst T_7394 of ClientTileLinkIOWrapper - T_7394.out.release.ready := UInt<1>("h00") - T_7394.out.probe.bits.p_type := UInt<1>("h00") - T_7394.out.probe.bits.addr_block := UInt<1>("h00") - T_7394.out.probe.valid := UInt<1>("h00") - T_7394.out.grant.bits.g_type := UInt<1>("h00") - T_7394.out.grant.bits.is_builtin_type := UInt<1>("h00") - T_7394.out.grant.bits.manager_xact_id := UInt<1>("h00") - T_7394.out.grant.bits.client_xact_id := UInt<1>("h00") - T_7394.out.grant.bits.data := UInt<1>("h00") - T_7394.out.grant.bits.addr_beat := UInt<1>("h00") - T_7394.out.grant.valid := UInt<1>("h00") - T_7394.out.acquire.ready := UInt<1>("h00") - T_7394.in.grant.ready := UInt<1>("h00") - T_7394.in.acquire.bits.union := UInt<1>("h00") - T_7394.in.acquire.bits.a_type := UInt<1>("h00") - T_7394.in.acquire.bits.is_builtin_type := UInt<1>("h00") - T_7394.in.acquire.bits.data := UInt<1>("h00") - T_7394.in.acquire.bits.addr_beat := UInt<1>("h00") - T_7394.in.acquire.bits.client_xact_id := UInt<1>("h00") - T_7394.in.acquire.bits.addr_block := UInt<1>("h00") - T_7394.in.acquire.valid := UInt<1>("h00") - T_7394.reset := UInt<1>("h00") - T_7394.clock := clock - T_7394.reset := reset - T_7394.in <> tiles_uncached[0] - inst T_7395 of ClientTileLinkIOWrapper - T_7395.out.release.ready := UInt<1>("h00") - T_7395.out.probe.bits.p_type := UInt<1>("h00") - T_7395.out.probe.bits.addr_block := UInt<1>("h00") - T_7395.out.probe.valid := UInt<1>("h00") - T_7395.out.grant.bits.g_type := UInt<1>("h00") - T_7395.out.grant.bits.is_builtin_type := UInt<1>("h00") - T_7395.out.grant.bits.manager_xact_id := UInt<1>("h00") - T_7395.out.grant.bits.client_xact_id := UInt<1>("h00") - T_7395.out.grant.bits.data := UInt<1>("h00") - T_7395.out.grant.bits.addr_beat := UInt<1>("h00") - T_7395.out.grant.valid := UInt<1>("h00") - T_7395.out.acquire.ready := UInt<1>("h00") - T_7395.in.grant.ready := UInt<1>("h00") - T_7395.in.acquire.bits.union := UInt<1>("h00") - T_7395.in.acquire.bits.a_type := UInt<1>("h00") - T_7395.in.acquire.bits.is_builtin_type := UInt<1>("h00") - T_7395.in.acquire.bits.data := UInt<1>("h00") - T_7395.in.acquire.bits.addr_beat := UInt<1>("h00") - T_7395.in.acquire.bits.client_xact_id := UInt<1>("h00") - T_7395.in.acquire.bits.addr_block := UInt<1>("h00") - T_7395.in.acquire.valid := UInt<1>("h00") - T_7395.reset := UInt<1>("h00") - T_7395.clock := clock - T_7395.reset := reset - T_7395.in <> htif_uncached - inst l1tol2net of RocketChipTileLinkArbiter - l1tol2net.managers[0].release.ready := UInt<1>("h00") - l1tol2net.managers[0].probe.bits.client_id := UInt<1>("h00") - l1tol2net.managers[0].probe.bits.p_type := UInt<1>("h00") - l1tol2net.managers[0].probe.bits.addr_block := UInt<1>("h00") - l1tol2net.managers[0].probe.valid := UInt<1>("h00") - l1tol2net.managers[0].finish.ready := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.client_id := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.g_type := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.is_builtin_type := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.manager_xact_id := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.client_xact_id := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.data := UInt<1>("h00") - l1tol2net.managers[0].grant.bits.addr_beat := UInt<1>("h00") - l1tol2net.managers[0].grant.valid := UInt<1>("h00") - l1tol2net.managers[0].acquire.ready := UInt<1>("h00") - l1tol2net.clients[0].release.bits.voluntary := UInt<1>("h00") - l1tol2net.clients[0].release.bits.r_type := UInt<1>("h00") - l1tol2net.clients[0].release.bits.data := UInt<1>("h00") - l1tol2net.clients[0].release.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[0].release.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[0].release.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[0].release.valid := UInt<1>("h00") - l1tol2net.clients[0].probe.ready := UInt<1>("h00") - l1tol2net.clients[0].grant.ready := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.union := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.a_type := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.is_builtin_type := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.data := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[0].acquire.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[0].acquire.valid := UInt<1>("h00") - l1tol2net.clients[1].release.bits.voluntary := UInt<1>("h00") - l1tol2net.clients[1].release.bits.r_type := UInt<1>("h00") - l1tol2net.clients[1].release.bits.data := UInt<1>("h00") - l1tol2net.clients[1].release.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[1].release.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[1].release.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[1].release.valid := UInt<1>("h00") - l1tol2net.clients[1].probe.ready := UInt<1>("h00") - l1tol2net.clients[1].grant.ready := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.union := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.a_type := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.is_builtin_type := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.data := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[1].acquire.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[1].acquire.valid := UInt<1>("h00") - l1tol2net.clients[2].release.bits.voluntary := UInt<1>("h00") - l1tol2net.clients[2].release.bits.r_type := UInt<1>("h00") - l1tol2net.clients[2].release.bits.data := UInt<1>("h00") - l1tol2net.clients[2].release.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[2].release.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[2].release.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[2].release.valid := UInt<1>("h00") - l1tol2net.clients[2].probe.ready := UInt<1>("h00") - l1tol2net.clients[2].grant.ready := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.union := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.a_type := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.is_builtin_type := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.data := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.addr_beat := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.client_xact_id := UInt<1>("h00") - l1tol2net.clients[2].acquire.bits.addr_block := UInt<1>("h00") - l1tol2net.clients[2].acquire.valid := UInt<1>("h00") - l1tol2net.reset := UInt<1>("h00") - l1tol2net.clock := clock - l1tol2net.reset := reset - inst T_7397 of L2BroadcastHub - T_7397.outer.grant.bits.g_type := UInt<1>("h00") - T_7397.outer.grant.bits.is_builtin_type := UInt<1>("h00") - T_7397.outer.grant.bits.manager_xact_id := UInt<1>("h00") - T_7397.outer.grant.bits.client_xact_id := UInt<1>("h00") - T_7397.outer.grant.bits.data := UInt<1>("h00") - T_7397.outer.grant.bits.addr_beat := UInt<1>("h00") - T_7397.outer.grant.valid := UInt<1>("h00") - T_7397.outer.acquire.ready := UInt<1>("h00") - T_7397.incoherent[0] := UInt<1>("h00") - T_7397.inner.release.bits.client_id := UInt<1>("h00") - T_7397.inner.release.bits.voluntary := UInt<1>("h00") - T_7397.inner.release.bits.r_type := UInt<1>("h00") - T_7397.inner.release.bits.data := UInt<1>("h00") - T_7397.inner.release.bits.addr_beat := UInt<1>("h00") - T_7397.inner.release.bits.client_xact_id := UInt<1>("h00") - T_7397.inner.release.bits.addr_block := UInt<1>("h00") - T_7397.inner.release.valid := UInt<1>("h00") - T_7397.inner.probe.ready := UInt<1>("h00") - T_7397.inner.finish.bits.manager_xact_id := UInt<1>("h00") - T_7397.inner.finish.valid := UInt<1>("h00") - T_7397.inner.grant.ready := UInt<1>("h00") - T_7397.inner.acquire.bits.client_id := UInt<1>("h00") - T_7397.inner.acquire.bits.union := UInt<1>("h00") - T_7397.inner.acquire.bits.a_type := UInt<1>("h00") - T_7397.inner.acquire.bits.is_builtin_type := UInt<1>("h00") - T_7397.inner.acquire.bits.data := UInt<1>("h00") - T_7397.inner.acquire.bits.addr_beat := UInt<1>("h00") - T_7397.inner.acquire.bits.client_xact_id := UInt<1>("h00") - T_7397.inner.acquire.bits.addr_block := UInt<1>("h00") - T_7397.inner.acquire.valid := UInt<1>("h00") - T_7397.reset := UInt<1>("h00") - T_7397.clock := clock - T_7397.reset := reset - T_7397.incoherent := incoherent - l1tol2net.clients[0] <> tiles_cached[0] - l1tol2net.clients[1] <> T_7394.out - l1tol2net.clients[2] <> T_7395.out - l1tol2net.managers[0] <> T_7397.inner - inst T_7398 of RocketChipTileLinkArbiter_36 - T_7398.managers[0].release.ready := UInt<1>("h00") - T_7398.managers[0].probe.bits.client_id := UInt<1>("h00") - T_7398.managers[0].probe.bits.p_type := UInt<1>("h00") - T_7398.managers[0].probe.bits.addr_block := UInt<1>("h00") - T_7398.managers[0].probe.valid := UInt<1>("h00") - T_7398.managers[0].finish.ready := UInt<1>("h00") - T_7398.managers[0].grant.bits.client_id := UInt<1>("h00") - T_7398.managers[0].grant.bits.g_type := UInt<1>("h00") - T_7398.managers[0].grant.bits.is_builtin_type := UInt<1>("h00") - T_7398.managers[0].grant.bits.manager_xact_id := UInt<1>("h00") - T_7398.managers[0].grant.bits.client_xact_id := UInt<1>("h00") - T_7398.managers[0].grant.bits.data := UInt<1>("h00") - T_7398.managers[0].grant.bits.addr_beat := UInt<1>("h00") - T_7398.managers[0].grant.valid := UInt<1>("h00") - T_7398.managers[0].acquire.ready := UInt<1>("h00") - T_7398.clients[0].release.bits.voluntary := UInt<1>("h00") - T_7398.clients[0].release.bits.r_type := UInt<1>("h00") - T_7398.clients[0].release.bits.data := UInt<1>("h00") - T_7398.clients[0].release.bits.addr_beat := UInt<1>("h00") - T_7398.clients[0].release.bits.client_xact_id := UInt<1>("h00") - T_7398.clients[0].release.bits.addr_block := UInt<1>("h00") - T_7398.clients[0].release.valid := UInt<1>("h00") - T_7398.clients[0].probe.ready := UInt<1>("h00") - T_7398.clients[0].grant.ready := UInt<1>("h00") - T_7398.clients[0].acquire.bits.union := UInt<1>("h00") - T_7398.clients[0].acquire.bits.a_type := UInt<1>("h00") - T_7398.clients[0].acquire.bits.is_builtin_type := UInt<1>("h00") - T_7398.clients[0].acquire.bits.data := UInt<1>("h00") - T_7398.clients[0].acquire.bits.addr_beat := UInt<1>("h00") - T_7398.clients[0].acquire.bits.client_xact_id := UInt<1>("h00") - T_7398.clients[0].acquire.bits.addr_block := UInt<1>("h00") - T_7398.clients[0].acquire.valid := UInt<1>("h00") - T_7398.reset := UInt<1>("h00") - T_7398.clock := clock - T_7398.reset := reset - inst T_7399 of MemPipeIOTileLinkIOConverter - T_7399.mem_1.resp.bits.tag := UInt<1>("h00") - T_7399.mem_1.resp.bits.data := UInt<1>("h00") - T_7399.mem_1.resp.valid := UInt<1>("h00") - T_7399.mem_1.req_data.ready := UInt<1>("h00") - T_7399.mem_1.req_cmd.ready := UInt<1>("h00") - T_7399.tl.release.bits.client_id := UInt<1>("h00") - T_7399.tl.release.bits.voluntary := UInt<1>("h00") - T_7399.tl.release.bits.r_type := UInt<1>("h00") - T_7399.tl.release.bits.data := UInt<1>("h00") - T_7399.tl.release.bits.addr_beat := UInt<1>("h00") - T_7399.tl.release.bits.client_xact_id := UInt<1>("h00") - T_7399.tl.release.bits.addr_block := UInt<1>("h00") - T_7399.tl.release.valid := UInt<1>("h00") - T_7399.tl.probe.ready := UInt<1>("h00") - T_7399.tl.finish.bits.manager_xact_id := UInt<1>("h00") - T_7399.tl.finish.valid := UInt<1>("h00") - T_7399.tl.grant.ready := UInt<1>("h00") - T_7399.tl.acquire.bits.client_id := UInt<1>("h00") - T_7399.tl.acquire.bits.union := UInt<1>("h00") - T_7399.tl.acquire.bits.a_type := UInt<1>("h00") - T_7399.tl.acquire.bits.is_builtin_type := UInt<1>("h00") - T_7399.tl.acquire.bits.data := UInt<1>("h00") - T_7399.tl.acquire.bits.addr_beat := UInt<1>("h00") - T_7399.tl.acquire.bits.client_xact_id := UInt<1>("h00") - T_7399.tl.acquire.bits.addr_block := UInt<1>("h00") - T_7399.tl.acquire.valid := UInt<1>("h00") - T_7399.reset := UInt<1>("h00") - T_7399.clock := clock - T_7399.reset := reset - inst T_7400 of ClientTileLinkIOWrapper_49 - T_7400.out.release.ready := UInt<1>("h00") - T_7400.out.probe.bits.p_type := UInt<1>("h00") - T_7400.out.probe.bits.addr_block := UInt<1>("h00") - T_7400.out.probe.valid := UInt<1>("h00") - T_7400.out.grant.bits.g_type := UInt<1>("h00") - T_7400.out.grant.bits.is_builtin_type := UInt<1>("h00") - T_7400.out.grant.bits.manager_xact_id := UInt<1>("h00") - T_7400.out.grant.bits.client_xact_id := UInt<1>("h00") - T_7400.out.grant.bits.data := UInt<1>("h00") - T_7400.out.grant.bits.addr_beat := UInt<1>("h00") - T_7400.out.grant.valid := UInt<1>("h00") - T_7400.out.acquire.ready := UInt<1>("h00") - T_7400.in.grant.ready := UInt<1>("h00") - T_7400.in.acquire.bits.union := UInt<1>("h00") - T_7400.in.acquire.bits.a_type := UInt<1>("h00") - T_7400.in.acquire.bits.is_builtin_type := UInt<1>("h00") - T_7400.in.acquire.bits.data := UInt<1>("h00") - T_7400.in.acquire.bits.addr_beat := UInt<1>("h00") - T_7400.in.acquire.bits.client_xact_id := UInt<1>("h00") - T_7400.in.acquire.bits.addr_block := UInt<1>("h00") - T_7400.in.acquire.valid := UInt<1>("h00") - T_7400.reset := UInt<1>("h00") - T_7400.clock := clock - T_7400.reset := reset - T_7400.in <> T_7397.outer - T_7398.clients[0] <> T_7400.out - T_7398.managers[0] <> T_7399.tl - wire T_7290 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - T_7290.resp.bits.tag := UInt<1>("h00") - T_7290.resp.bits.data := UInt<1>("h00") - T_7290.resp.valid := UInt<1>("h00") - T_7290.resp.ready := UInt<1>("h00") - T_7290.req_data.bits.data := UInt<1>("h00") - T_7290.req_data.valid := UInt<1>("h00") - T_7290.req_data.ready := UInt<1>("h00") - T_7290.req_cmd.bits.rw := UInt<1>("h00") - T_7290.req_cmd.bits.tag := UInt<1>("h00") - T_7290.req_cmd.bits.addr := UInt<1>("h00") - T_7290.req_cmd.valid := UInt<1>("h00") - T_7290.req_cmd.ready := UInt<1>("h00") - T_7399.mem_1.resp.valid := T_7290.resp.valid - T_7399.mem_1.resp.bits <> T_7290.resp.bits - T_7290.resp.ready := UInt<1>("h01") - T_7290.req_cmd.valid := T_7399.mem_1.req_cmd.valid - T_7290.req_cmd.bits <> T_7399.mem_1.req_cmd.bits - T_7399.mem_1.req_cmd.ready := T_7290.req_cmd.ready - T_7290.req_data.valid := T_7399.mem_1.req_data.valid - T_7290.req_data.bits <> T_7399.mem_1.req_data.bits - T_7399.mem_1.req_data.ready := T_7290.req_data.ready - inst T_7401 of MemIOArbiter - T_7401.outer.resp.bits.tag := UInt<1>("h00") - T_7401.outer.resp.bits.data := UInt<1>("h00") - T_7401.outer.resp.valid := UInt<1>("h00") - T_7401.outer.req_data.ready := UInt<1>("h00") - T_7401.outer.req_cmd.ready := UInt<1>("h00") - T_7401.inner[0].resp.ready := UInt<1>("h00") - T_7401.inner[0].req_data.bits.data := UInt<1>("h00") - T_7401.inner[0].req_data.valid := UInt<1>("h00") - T_7401.inner[0].req_cmd.bits.rw := UInt<1>("h00") - T_7401.inner[0].req_cmd.bits.tag := UInt<1>("h00") - T_7401.inner[0].req_cmd.bits.addr := UInt<1>("h00") - T_7401.inner[0].req_cmd.valid := UInt<1>("h00") - T_7401.reset := UInt<1>("h00") - T_7401.clock := clock - T_7401.reset := reset - inst T_7402 of MemSerdes - T_7402.narrow.resp.bits := UInt<1>("h00") - T_7402.narrow.resp.valid := UInt<1>("h00") - T_7402.narrow.req.ready := UInt<1>("h00") - T_7402.wide.resp.ready := UInt<1>("h00") - T_7402.wide.req_data.bits.data := UInt<1>("h00") - T_7402.wide.req_data.valid := UInt<1>("h00") - T_7402.wide.req_cmd.bits.rw := UInt<1>("h00") - T_7402.wide.req_cmd.bits.tag := UInt<1>("h00") - T_7402.wide.req_cmd.bits.addr := UInt<1>("h00") - T_7402.wide.req_cmd.valid := UInt<1>("h00") - T_7402.reset := UInt<1>("h00") - T_7402.clock := clock - T_7402.reset := reset - T_7402.wide <> T_7401.outer - mem_backup <> T_7402.narrow - node T_7373 = mux(mem_backup_en, T_7401.inner[0].req_cmd.ready, mem_1[0].req_cmd.ready) - T_7290.req_cmd.ready := T_7373 - node T_7375 = eq(mem_backup_en, UInt<1>("h00")) - node T_7376 = and(T_7290.req_cmd.valid, T_7375) - mem_1[0].req_cmd.valid := T_7376 - mem_1[0].req_cmd.bits <> T_7290.req_cmd.bits - node T_7377 = and(T_7290.req_cmd.valid, mem_backup_en) - T_7401.inner[0].req_cmd.valid := T_7377 - T_7401.inner[0].req_cmd.bits <> T_7290.req_cmd.bits - node T_7378 = mux(mem_backup_en, T_7401.inner[0].req_data.ready, mem_1[0].req_data.ready) - T_7290.req_data.ready := T_7378 - node T_7380 = eq(mem_backup_en, UInt<1>("h00")) - node T_7381 = and(T_7290.req_data.valid, T_7380) - mem_1[0].req_data.valid := T_7381 - mem_1[0].req_data.bits <> T_7290.req_data.bits - node T_7382 = and(T_7290.req_data.valid, mem_backup_en) - T_7401.inner[0].req_data.valid := T_7382 - T_7401.inner[0].req_data.bits <> T_7290.req_data.bits - node T_7383 = mux(mem_backup_en, T_7401.inner[0].resp.valid, mem_1[0].resp.valid) - T_7290.resp.valid := T_7383 - wire T_7387 : {data : UInt<128>, tag : UInt<7>} - T_7387 <> mem_1[0].resp.bits - when mem_backup_en : - T_7387 <> T_7401.inner[0].resp.bits - skip - T_7290.resp.bits <> T_7387 - node T_7391 = eq(mem_backup_en, UInt<1>("h00")) - node T_7392 = and(T_7290.resp.ready, T_7391) - mem_1[0].resp.ready := T_7392 - node T_7393 = and(T_7290.resp.ready, mem_backup_en) - T_7401.inner[0].resp.ready := T_7393 - - module Queue_50 : - output count : UInt<1> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : UInt<17>[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_30 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_30) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_36 = and(enq.ready, enq.valid) - node T_38 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_36, T_38) - node T_40 = and(deq.ready, deq.valid) - node T_42 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_40, T_42) - when do_enq : - infer accessor T_44 = ram[UInt<1>("h00")] - T_44 := enq.bits - skip - when do_deq : - skip - node T_47 = neq(do_enq, do_deq) - when T_47 : - maybe_full := do_enq - skip - node T_49 = eq(empty, UInt<1>("h00")) - node T_51 = and(UInt<1>("h00"), enq.valid) - node T_52 = or(T_49, T_51) - deq.valid := T_52 - node T_54 = eq(full, UInt<1>("h00")) - node T_56 = and(UInt<1>("h00"), deq.ready) - node T_57 = or(T_54, T_56) - enq.ready := T_57 - infer accessor T_58 = ram[UInt<1>("h00")] - node T_59 = mux(maybe_flow, enq.bits, T_58) - deq.bits := T_59 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_61 = and(maybe_full, ptr_match) - node T_62 = cat(T_61, ptr_diff) - count := T_62 - - module SlowIO : - output divisor : UInt<32> - input set_divisor : {valid : UInt<1>, bits : UInt<32>} - output clk_slow : UInt<1> - input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input clock : Clock - input reset : UInt<1> - - divisor := UInt<1>("h00") - clk_slow := UInt<1>("h00") - in_slow.ready := UInt<1>("h00") - in_fast.bits := UInt<1>("h00") - in_fast.valid := UInt<1>("h00") - out_slow.bits := UInt<1>("h00") - out_slow.valid := UInt<1>("h00") - out_fast.ready := UInt<1>("h00") - reg divisor_1 : UInt, clock, reset - onreset divisor_1 := UInt<9>("h01ff") - reg d_shadow : UInt, clock, reset - onreset d_shadow := UInt<9>("h01ff") - reg hold : UInt, clock, reset - onreset hold := UInt<7>("h07f") - reg h_shadow : UInt, clock, reset - onreset h_shadow := UInt<7>("h07f") - when set_divisor.valid : - node T_57 = bits(set_divisor.bits, 8, 0) - d_shadow := T_57 - node T_58 = bits(set_divisor.bits, 24, 16) - h_shadow := T_58 - skip - node T_59 = shl(hold, 16) - node T_60 = or(T_59, divisor_1) - divisor := T_60 - reg count : UInt<9>, clock, reset - reg myclock : UInt<1>, clock, reset - node T_66 = addw(count, UInt<1>("h01")) - count := T_66 - node T_67 = shr(divisor_1, 1) - node rising = eq(count, T_67) - node falling = eq(count, divisor_1) - node T_70 = shr(divisor_1, 1) - node T_71 = addw(T_70, hold) - node held = eq(count, T_71) - when falling : - divisor_1 := d_shadow - hold := h_shadow - count := UInt<1>("h00") - myclock := UInt<1>("h00") - skip - when rising : - myclock := UInt<1>("h01") - skip - reg in_slow_rdy : UInt<1>, clock, reset - onreset in_slow_rdy := UInt<1>("h00") - reg out_slow_val : UInt<1>, clock, reset - onreset out_slow_val := UInt<1>("h00") - reg out_slow_bits : UInt<17>, clock, reset - inst fromhost_q of Queue_50 - fromhost_q.deq.ready := UInt<1>("h00") - fromhost_q.enq.bits := UInt<1>("h00") - fromhost_q.enq.valid := UInt<1>("h00") - fromhost_q.reset := UInt<1>("h00") - fromhost_q.clock := clock - fromhost_q.reset := reset - node T_87 = and(in_slow.valid, in_slow_rdy) - node T_88 = or(T_87, reset) - node T_89 = and(rising, T_88) - fromhost_q.enq.valid := T_89 - fromhost_q.enq.bits := in_slow.bits - in_fast <> fromhost_q.deq - inst tohost_q of Queue_50 - tohost_q.deq.ready := UInt<1>("h00") - tohost_q.enq.bits := UInt<1>("h00") - tohost_q.enq.valid := UInt<1>("h00") - tohost_q.reset := UInt<1>("h00") - tohost_q.clock := clock - tohost_q.reset := reset - tohost_q.enq <> out_fast - node T_95 = and(rising, out_slow.ready) - node T_96 = and(T_95, out_slow_val) - tohost_q.deq.ready := T_96 - when held : - in_slow_rdy := fromhost_q.enq.ready - out_slow_val := tohost_q.deq.valid - node T_97 = mux(reset, fromhost_q.deq.bits, tohost_q.deq.bits) - out_slow_bits := T_97 - skip - in_slow.ready := in_slow_rdy - out_slow.valid := out_slow_val - out_slow.bits := out_slow_bits - clk_slow := myclock - - module Uncore : - output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} - input htif : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1] - input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1] - input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] - output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - mem_backup_ctrl.out_valid := UInt<1>("h00") - htif[0].ipi_rep.bits := UInt<1>("h00") - htif[0].ipi_rep.valid := UInt<1>("h00") - htif[0].ipi_req.ready := UInt<1>("h00") - htif[0].pcr_rep.ready := UInt<1>("h00") - htif[0].pcr_req.bits.data := UInt<1>("h00") - htif[0].pcr_req.bits.addr := UInt<1>("h00") - htif[0].pcr_req.bits.rw := UInt<1>("h00") - htif[0].pcr_req.valid := UInt<1>("h00") - htif[0].id := UInt<1>("h00") - htif[0].reset := UInt<1>("h00") - tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") - tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") - tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") - tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") - tiles_uncached[0].grant.bits.data := UInt<1>("h00") - tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") - tiles_uncached[0].grant.valid := UInt<1>("h00") - tiles_uncached[0].acquire.ready := UInt<1>("h00") - tiles_cached[0].release.ready := UInt<1>("h00") - tiles_cached[0].probe.bits.p_type := UInt<1>("h00") - tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") - tiles_cached[0].probe.valid := UInt<1>("h00") - tiles_cached[0].grant.bits.g_type := UInt<1>("h00") - tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") - tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") - tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") - tiles_cached[0].grant.bits.data := UInt<1>("h00") - tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") - tiles_cached[0].grant.valid := UInt<1>("h00") - tiles_cached[0].acquire.ready := UInt<1>("h00") - mem_1[0].resp.ready := UInt<1>("h00") - mem_1[0].req_data.bits.data := UInt<1>("h00") - mem_1[0].req_data.valid := UInt<1>("h00") - mem_1[0].req_cmd.bits.rw := UInt<1>("h00") - mem_1[0].req_cmd.bits.tag := UInt<1>("h00") - mem_1[0].req_cmd.bits.addr := UInt<1>("h00") - mem_1[0].req_cmd.valid := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.out.bits := UInt<1>("h00") - host.out.valid := UInt<1>("h00") - host.in.ready := UInt<1>("h00") - host.clk_edge := UInt<1>("h00") - host.clk := UInt<1>("h00") - inst htif_2 of HTIF - htif_2.scr.rdata[0] := UInt<1>("h00") - htif_2.scr.rdata[1] := UInt<1>("h00") - htif_2.scr.rdata[2] := UInt<1>("h00") - htif_2.scr.rdata[3] := UInt<1>("h00") - htif_2.scr.rdata[4] := UInt<1>("h00") - htif_2.scr.rdata[5] := UInt<1>("h00") - htif_2.scr.rdata[6] := UInt<1>("h00") - htif_2.scr.rdata[7] := UInt<1>("h00") - htif_2.scr.rdata[8] := UInt<1>("h00") - htif_2.scr.rdata[9] := UInt<1>("h00") - htif_2.scr.rdata[10] := UInt<1>("h00") - htif_2.scr.rdata[11] := UInt<1>("h00") - htif_2.scr.rdata[12] := UInt<1>("h00") - htif_2.scr.rdata[13] := UInt<1>("h00") - htif_2.scr.rdata[14] := UInt<1>("h00") - htif_2.scr.rdata[15] := UInt<1>("h00") - htif_2.scr.rdata[16] := UInt<1>("h00") - htif_2.scr.rdata[17] := UInt<1>("h00") - htif_2.scr.rdata[18] := UInt<1>("h00") - htif_2.scr.rdata[19] := UInt<1>("h00") - htif_2.scr.rdata[20] := UInt<1>("h00") - htif_2.scr.rdata[21] := UInt<1>("h00") - htif_2.scr.rdata[22] := UInt<1>("h00") - htif_2.scr.rdata[23] := UInt<1>("h00") - htif_2.scr.rdata[24] := UInt<1>("h00") - htif_2.scr.rdata[25] := UInt<1>("h00") - htif_2.scr.rdata[26] := UInt<1>("h00") - htif_2.scr.rdata[27] := UInt<1>("h00") - htif_2.scr.rdata[28] := UInt<1>("h00") - htif_2.scr.rdata[29] := UInt<1>("h00") - htif_2.scr.rdata[30] := UInt<1>("h00") - htif_2.scr.rdata[31] := UInt<1>("h00") - htif_2.scr.rdata[32] := UInt<1>("h00") - htif_2.scr.rdata[33] := UInt<1>("h00") - htif_2.scr.rdata[34] := UInt<1>("h00") - htif_2.scr.rdata[35] := UInt<1>("h00") - htif_2.scr.rdata[36] := UInt<1>("h00") - htif_2.scr.rdata[37] := UInt<1>("h00") - htif_2.scr.rdata[38] := UInt<1>("h00") - htif_2.scr.rdata[39] := UInt<1>("h00") - htif_2.scr.rdata[40] := UInt<1>("h00") - htif_2.scr.rdata[41] := UInt<1>("h00") - htif_2.scr.rdata[42] := UInt<1>("h00") - htif_2.scr.rdata[43] := UInt<1>("h00") - htif_2.scr.rdata[44] := UInt<1>("h00") - htif_2.scr.rdata[45] := UInt<1>("h00") - htif_2.scr.rdata[46] := UInt<1>("h00") - htif_2.scr.rdata[47] := UInt<1>("h00") - htif_2.scr.rdata[48] := UInt<1>("h00") - htif_2.scr.rdata[49] := UInt<1>("h00") - htif_2.scr.rdata[50] := UInt<1>("h00") - htif_2.scr.rdata[51] := UInt<1>("h00") - htif_2.scr.rdata[52] := UInt<1>("h00") - htif_2.scr.rdata[53] := UInt<1>("h00") - htif_2.scr.rdata[54] := UInt<1>("h00") - htif_2.scr.rdata[55] := UInt<1>("h00") - htif_2.scr.rdata[56] := UInt<1>("h00") - htif_2.scr.rdata[57] := UInt<1>("h00") - htif_2.scr.rdata[58] := UInt<1>("h00") - htif_2.scr.rdata[59] := UInt<1>("h00") - htif_2.scr.rdata[60] := UInt<1>("h00") - htif_2.scr.rdata[61] := UInt<1>("h00") - htif_2.scr.rdata[62] := UInt<1>("h00") - htif_2.scr.rdata[63] := UInt<1>("h00") - htif_2.mem_1.grant.bits.g_type := UInt<1>("h00") - htif_2.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") - htif_2.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") - htif_2.mem_1.grant.bits.client_xact_id := UInt<1>("h00") - htif_2.mem_1.grant.bits.data := UInt<1>("h00") - htif_2.mem_1.grant.bits.addr_beat := UInt<1>("h00") - htif_2.mem_1.grant.valid := UInt<1>("h00") - htif_2.mem_1.acquire.ready := UInt<1>("h00") - htif_2.cpu[0].debug_stats_pcr := UInt<1>("h00") - htif_2.cpu[0].ipi_rep.ready := UInt<1>("h00") - htif_2.cpu[0].ipi_req.bits := UInt<1>("h00") - htif_2.cpu[0].ipi_req.valid := UInt<1>("h00") - htif_2.cpu[0].pcr_rep.bits := UInt<1>("h00") - htif_2.cpu[0].pcr_rep.valid := UInt<1>("h00") - htif_2.cpu[0].pcr_req.ready := UInt<1>("h00") - htif_2.host.out.ready := UInt<1>("h00") - htif_2.host.in.bits := UInt<1>("h00") - htif_2.host.in.valid := UInt<1>("h00") - htif_2.reset := UInt<1>("h00") - htif_2.clock := clock - htif_2.reset := reset - inst outmemsys of OuterMemorySystem - outmemsys.mem_backup_en := UInt<1>("h00") - outmemsys.mem_backup.resp.bits := UInt<1>("h00") - outmemsys.mem_backup.resp.valid := UInt<1>("h00") - outmemsys.mem_backup.req.ready := UInt<1>("h00") - outmemsys.mem_1[0].resp.bits.tag := UInt<1>("h00") - outmemsys.mem_1[0].resp.bits.data := UInt<1>("h00") - outmemsys.mem_1[0].resp.valid := UInt<1>("h00") - outmemsys.mem_1[0].req_data.ready := UInt<1>("h00") - outmemsys.mem_1[0].req_cmd.ready := UInt<1>("h00") - outmemsys.incoherent[0] := UInt<1>("h00") - outmemsys.htif_uncached.grant.ready := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.union := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.a_type := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.is_builtin_type := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.data := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.addr_beat := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.client_xact_id := UInt<1>("h00") - outmemsys.htif_uncached.acquire.bits.addr_block := UInt<1>("h00") - outmemsys.htif_uncached.acquire.valid := UInt<1>("h00") - outmemsys.tiles_uncached[0].grant.ready := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") - outmemsys.tiles_uncached[0].acquire.valid := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.r_type := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.data := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") - outmemsys.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") - outmemsys.tiles_cached[0].release.valid := UInt<1>("h00") - outmemsys.tiles_cached[0].probe.ready := UInt<1>("h00") - outmemsys.tiles_cached[0].grant.ready := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.union := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.data := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") - outmemsys.tiles_cached[0].acquire.valid := UInt<1>("h00") - outmemsys.reset := UInt<1>("h00") - outmemsys.clock := clock - outmemsys.reset := reset - outmemsys.incoherent[0] := htif_2.cpu[0].reset - outmemsys.htif_uncached <> htif_2.mem_1 - outmemsys.tiles_uncached <> tiles_uncached - outmemsys.tiles_cached <> tiles_cached - host.debug_stats_pcr := htif_2.host.debug_stats_pcr - htif_2.cpu <> htif - mem_1 <> outmemsys.mem_1 - outmemsys.mem_backup_en := mem_backup_ctrl.en - inst T_7095 of SlowIO - T_7095.set_divisor.bits := UInt<1>("h00") - T_7095.set_divisor.valid := UInt<1>("h00") - T_7095.in_slow.bits := UInt<1>("h00") - T_7095.in_slow.valid := UInt<1>("h00") - T_7095.in_fast.ready := UInt<1>("h00") - T_7095.out_slow.ready := UInt<1>("h00") - T_7095.out_fast.bits := UInt<1>("h00") - T_7095.out_fast.valid := UInt<1>("h00") - T_7095.reset := UInt<1>("h00") - T_7095.clock := clock - T_7095.reset := reset - node T_7060 = eq(htif_2.scr.waddr, UInt<6>("h03f")) - node T_7061 = and(htif_2.scr.wen, T_7060) - T_7095.set_divisor.valid := T_7061 - T_7095.set_divisor.bits := htif_2.scr.wdata - htif_2.scr.rdata[63] := T_7095.divisor - node T_7062 = or(htif_2.host.out.valid, outmemsys.mem_backup.req.valid) - T_7095.out_fast.valid := T_7062 - node T_7063 = mux(htif_2.host.out.valid, htif_2.host.out.bits, outmemsys.mem_backup.req.bits) - node T_7064 = cat(htif_2.host.out.valid, T_7063) - T_7095.out_fast.bits := T_7064 - htif_2.host.out.ready := T_7095.out_fast.ready - node T_7066 = eq(htif_2.host.out.valid, UInt<1>("h00")) - node T_7067 = and(T_7095.out_fast.ready, T_7066) - outmemsys.mem_backup.req.ready := T_7067 - node T_7068 = bit(T_7095.out_slow.bits, 16) - node T_7069 = and(T_7095.out_slow.valid, T_7068) - host.out.valid := T_7069 - host.out.bits := T_7095.out_slow.bits - node T_7070 = bit(T_7095.out_slow.bits, 16) - node T_7072 = eq(T_7070, UInt<1>("h00")) - node T_7073 = and(T_7095.out_slow.valid, T_7072) - mem_backup_ctrl.out_valid := T_7073 - node T_7074 = bit(T_7095.out_slow.bits, 16) - node T_7075 = mux(T_7074, host.out.ready, mem_backup_ctrl.out_ready) - T_7095.out_slow.ready := T_7075 - node T_7076 = and(mem_backup_ctrl.en, mem_backup_ctrl.in_valid) - node T_7077 = or(T_7076, host.in.valid) - T_7095.in_slow.valid := T_7077 - node T_7078 = cat(T_7076, host.in.bits) - T_7095.in_slow.bits := T_7078 - host.in.ready := T_7095.in_slow.ready - node T_7079 = bit(T_7095.in_fast.bits, 16) - node T_7080 = and(T_7095.in_fast.valid, T_7079) - outmemsys.mem_backup.resp.valid := T_7080 - outmemsys.mem_backup.resp.bits := T_7095.in_fast.bits - node T_7081 = bit(T_7095.in_fast.bits, 16) - node T_7083 = eq(T_7081, UInt<1>("h00")) - node T_7084 = and(T_7095.in_fast.valid, T_7083) - htif_2.host.in.valid := T_7084 - htif_2.host.in.bits := T_7095.in_fast.bits - node T_7085 = bit(T_7095.in_fast.bits, 16) - node T_7087 = mux(T_7085, UInt<1>("h01"), htif_2.host.in.ready) - T_7095.in_fast.ready := T_7087 - host.clk := T_7095.clk_slow - reg T_7088 : UInt<1>, clock, reset - T_7088 := host.clk - node T_7090 = eq(T_7088, UInt<1>("h00")) - node T_7091 = and(host.clk, T_7090) - reg T_7092 : UInt<1>, clock, reset - T_7092 := T_7091 - host.clk_edge := T_7092 - - module BTB : - input invalidate : UInt<1> - input ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}} - input bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}} - input btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} - output resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}} - input req : {valid : UInt<1>, bits : {addr : UInt<39>}} - input clock : Clock - input reset : UInt<1> - - resp.bits.bht.value := UInt<1>("h00") - resp.bits.bht.history := UInt<1>("h00") - resp.bits.entry := UInt<1>("h00") - resp.bits.target := UInt<1>("h00") - resp.bits.bridx := UInt<1>("h00") - resp.bits.mask := UInt<1>("h00") - resp.bits.taken := UInt<1>("h00") - resp.valid := UInt<1>("h00") - reg idxValid : UInt<62>, clock, reset - onreset idxValid := UInt<62>("h00") - cmem idxs : UInt<12>[62], clock - cmem idxPages : UInt<3>[62], clock - cmem tgts : UInt<12>[62], clock - cmem tgtPages : UInt<3>[62], clock - cmem pages : UInt<27>[6], clock - reg pageValid : UInt<6>, clock, reset - onreset pageValid := UInt<6>("h00") - infer accessor T_589 = idxPages[UInt<1>("h00")] - node T_591 = dshl(UInt<1>("h01"), T_589) - node T_592 = bits(T_591, 5, 0) - infer accessor T_594 = idxPages[UInt<1>("h01")] - node T_596 = dshl(UInt<1>("h01"), T_594) - node T_597 = bits(T_596, 5, 0) - infer accessor T_599 = idxPages[UInt<2>("h02")] - node T_601 = dshl(UInt<1>("h01"), T_599) - node T_602 = bits(T_601, 5, 0) - infer accessor T_604 = idxPages[UInt<2>("h03")] - node T_606 = dshl(UInt<1>("h01"), T_604) - node T_607 = bits(T_606, 5, 0) - infer accessor T_609 = idxPages[UInt<3>("h04")] - node T_611 = dshl(UInt<1>("h01"), T_609) - node T_612 = bits(T_611, 5, 0) - infer accessor T_614 = idxPages[UInt<3>("h05")] - node T_616 = dshl(UInt<1>("h01"), T_614) - node T_617 = bits(T_616, 5, 0) - infer accessor T_619 = idxPages[UInt<3>("h06")] - node T_621 = dshl(UInt<1>("h01"), T_619) - node T_622 = bits(T_621, 5, 0) - infer accessor T_624 = idxPages[UInt<3>("h07")] - node T_626 = dshl(UInt<1>("h01"), T_624) - node T_627 = bits(T_626, 5, 0) - infer accessor T_629 = idxPages[UInt<4>("h08")] - node T_631 = dshl(UInt<1>("h01"), T_629) - node T_632 = bits(T_631, 5, 0) - infer accessor T_634 = idxPages[UInt<4>("h09")] - node T_636 = dshl(UInt<1>("h01"), T_634) - node T_637 = bits(T_636, 5, 0) - infer accessor T_639 = idxPages[UInt<4>("h0a")] - node T_641 = dshl(UInt<1>("h01"), T_639) - node T_642 = bits(T_641, 5, 0) - infer accessor T_644 = idxPages[UInt<4>("h0b")] - node T_646 = dshl(UInt<1>("h01"), T_644) - node T_647 = bits(T_646, 5, 0) - infer accessor T_649 = idxPages[UInt<4>("h0c")] - node T_651 = dshl(UInt<1>("h01"), T_649) - node T_652 = bits(T_651, 5, 0) - infer accessor T_654 = idxPages[UInt<4>("h0d")] - node T_656 = dshl(UInt<1>("h01"), T_654) - node T_657 = bits(T_656, 5, 0) - infer accessor T_659 = idxPages[UInt<4>("h0e")] - node T_661 = dshl(UInt<1>("h01"), T_659) - node T_662 = bits(T_661, 5, 0) - infer accessor T_664 = idxPages[UInt<4>("h0f")] - node T_666 = dshl(UInt<1>("h01"), T_664) - node T_667 = bits(T_666, 5, 0) - infer accessor T_669 = idxPages[UInt<5>("h010")] - node T_671 = dshl(UInt<1>("h01"), T_669) - node T_672 = bits(T_671, 5, 0) - infer accessor T_674 = idxPages[UInt<5>("h011")] - node T_676 = dshl(UInt<1>("h01"), T_674) - node T_677 = bits(T_676, 5, 0) - infer accessor T_679 = idxPages[UInt<5>("h012")] - node T_681 = dshl(UInt<1>("h01"), T_679) - node T_682 = bits(T_681, 5, 0) - infer accessor T_684 = idxPages[UInt<5>("h013")] - node T_686 = dshl(UInt<1>("h01"), T_684) - node T_687 = bits(T_686, 5, 0) - infer accessor T_689 = idxPages[UInt<5>("h014")] - node T_691 = dshl(UInt<1>("h01"), T_689) - node T_692 = bits(T_691, 5, 0) - infer accessor T_694 = idxPages[UInt<5>("h015")] - node T_696 = dshl(UInt<1>("h01"), T_694) - node T_697 = bits(T_696, 5, 0) - infer accessor T_699 = idxPages[UInt<5>("h016")] - node T_701 = dshl(UInt<1>("h01"), T_699) - node T_702 = bits(T_701, 5, 0) - infer accessor T_704 = idxPages[UInt<5>("h017")] - node T_706 = dshl(UInt<1>("h01"), T_704) - node T_707 = bits(T_706, 5, 0) - infer accessor T_709 = idxPages[UInt<5>("h018")] - node T_711 = dshl(UInt<1>("h01"), T_709) - node T_712 = bits(T_711, 5, 0) - infer accessor T_714 = idxPages[UInt<5>("h019")] - node T_716 = dshl(UInt<1>("h01"), T_714) - node T_717 = bits(T_716, 5, 0) - infer accessor T_719 = idxPages[UInt<5>("h01a")] - node T_721 = dshl(UInt<1>("h01"), T_719) - node T_722 = bits(T_721, 5, 0) - infer accessor T_724 = idxPages[UInt<5>("h01b")] - node T_726 = dshl(UInt<1>("h01"), T_724) - node T_727 = bits(T_726, 5, 0) - infer accessor T_729 = idxPages[UInt<5>("h01c")] - node T_731 = dshl(UInt<1>("h01"), T_729) - node T_732 = bits(T_731, 5, 0) - infer accessor T_734 = idxPages[UInt<5>("h01d")] - node T_736 = dshl(UInt<1>("h01"), T_734) - node T_737 = bits(T_736, 5, 0) - infer accessor T_739 = idxPages[UInt<5>("h01e")] - node T_741 = dshl(UInt<1>("h01"), T_739) - node T_742 = bits(T_741, 5, 0) - infer accessor T_744 = idxPages[UInt<5>("h01f")] - node T_746 = dshl(UInt<1>("h01"), T_744) - node T_747 = bits(T_746, 5, 0) - infer accessor T_749 = idxPages[UInt<6>("h020")] - node T_751 = dshl(UInt<1>("h01"), T_749) - node T_752 = bits(T_751, 5, 0) - infer accessor T_754 = idxPages[UInt<6>("h021")] - node T_756 = dshl(UInt<1>("h01"), T_754) - node T_757 = bits(T_756, 5, 0) - infer accessor T_759 = idxPages[UInt<6>("h022")] - node T_761 = dshl(UInt<1>("h01"), T_759) - node T_762 = bits(T_761, 5, 0) - infer accessor T_764 = idxPages[UInt<6>("h023")] - node T_766 = dshl(UInt<1>("h01"), T_764) - node T_767 = bits(T_766, 5, 0) - infer accessor T_769 = idxPages[UInt<6>("h024")] - node T_771 = dshl(UInt<1>("h01"), T_769) - node T_772 = bits(T_771, 5, 0) - infer accessor T_774 = idxPages[UInt<6>("h025")] - node T_776 = dshl(UInt<1>("h01"), T_774) - node T_777 = bits(T_776, 5, 0) - infer accessor T_779 = idxPages[UInt<6>("h026")] - node T_781 = dshl(UInt<1>("h01"), T_779) - node T_782 = bits(T_781, 5, 0) - infer accessor T_784 = idxPages[UInt<6>("h027")] - node T_786 = dshl(UInt<1>("h01"), T_784) - node T_787 = bits(T_786, 5, 0) - infer accessor T_789 = idxPages[UInt<6>("h028")] - node T_791 = dshl(UInt<1>("h01"), T_789) - node T_792 = bits(T_791, 5, 0) - infer accessor T_794 = idxPages[UInt<6>("h029")] - node T_796 = dshl(UInt<1>("h01"), T_794) - node T_797 = bits(T_796, 5, 0) - infer accessor T_799 = idxPages[UInt<6>("h02a")] - node T_801 = dshl(UInt<1>("h01"), T_799) - node T_802 = bits(T_801, 5, 0) - infer accessor T_804 = idxPages[UInt<6>("h02b")] - node T_806 = dshl(UInt<1>("h01"), T_804) - node T_807 = bits(T_806, 5, 0) - infer accessor T_809 = idxPages[UInt<6>("h02c")] - node T_811 = dshl(UInt<1>("h01"), T_809) - node T_812 = bits(T_811, 5, 0) - infer accessor T_814 = idxPages[UInt<6>("h02d")] - node T_816 = dshl(UInt<1>("h01"), T_814) - node T_817 = bits(T_816, 5, 0) - infer accessor T_819 = idxPages[UInt<6>("h02e")] - node T_821 = dshl(UInt<1>("h01"), T_819) - node T_822 = bits(T_821, 5, 0) - infer accessor T_824 = idxPages[UInt<6>("h02f")] - node T_826 = dshl(UInt<1>("h01"), T_824) - node T_827 = bits(T_826, 5, 0) - infer accessor T_829 = idxPages[UInt<6>("h030")] - node T_831 = dshl(UInt<1>("h01"), T_829) - node T_832 = bits(T_831, 5, 0) - infer accessor T_834 = idxPages[UInt<6>("h031")] - node T_836 = dshl(UInt<1>("h01"), T_834) - node T_837 = bits(T_836, 5, 0) - infer accessor T_839 = idxPages[UInt<6>("h032")] - node T_841 = dshl(UInt<1>("h01"), T_839) - node T_842 = bits(T_841, 5, 0) - infer accessor T_844 = idxPages[UInt<6>("h033")] - node T_846 = dshl(UInt<1>("h01"), T_844) - node T_847 = bits(T_846, 5, 0) - infer accessor T_849 = idxPages[UInt<6>("h034")] - node T_851 = dshl(UInt<1>("h01"), T_849) - node T_852 = bits(T_851, 5, 0) - infer accessor T_854 = idxPages[UInt<6>("h035")] - node T_856 = dshl(UInt<1>("h01"), T_854) - node T_857 = bits(T_856, 5, 0) - infer accessor T_859 = idxPages[UInt<6>("h036")] - node T_861 = dshl(UInt<1>("h01"), T_859) - node T_862 = bits(T_861, 5, 0) - infer accessor T_864 = idxPages[UInt<6>("h037")] - node T_866 = dshl(UInt<1>("h01"), T_864) - node T_867 = bits(T_866, 5, 0) - infer accessor T_869 = idxPages[UInt<6>("h038")] - node T_871 = dshl(UInt<1>("h01"), T_869) - node T_872 = bits(T_871, 5, 0) - infer accessor T_874 = idxPages[UInt<6>("h039")] - node T_876 = dshl(UInt<1>("h01"), T_874) - node T_877 = bits(T_876, 5, 0) - infer accessor T_879 = idxPages[UInt<6>("h03a")] - node T_881 = dshl(UInt<1>("h01"), T_879) - node T_882 = bits(T_881, 5, 0) - infer accessor T_884 = idxPages[UInt<6>("h03b")] - node T_886 = dshl(UInt<1>("h01"), T_884) - node T_887 = bits(T_886, 5, 0) - infer accessor T_889 = idxPages[UInt<6>("h03c")] - node T_891 = dshl(UInt<1>("h01"), T_889) - node T_892 = bits(T_891, 5, 0) - infer accessor T_894 = idxPages[UInt<6>("h03d")] - node T_896 = dshl(UInt<1>("h01"), T_894) - node T_897 = bits(T_896, 5, 0) - infer accessor T_899 = tgtPages[UInt<1>("h00")] - node T_901 = dshl(UInt<1>("h01"), T_899) - node T_902 = bits(T_901, 5, 0) - infer accessor T_904 = tgtPages[UInt<1>("h01")] - node T_906 = dshl(UInt<1>("h01"), T_904) - node T_907 = bits(T_906, 5, 0) - infer accessor T_909 = tgtPages[UInt<2>("h02")] - node T_911 = dshl(UInt<1>("h01"), T_909) - node T_912 = bits(T_911, 5, 0) - infer accessor T_914 = tgtPages[UInt<2>("h03")] - node T_916 = dshl(UInt<1>("h01"), T_914) - node T_917 = bits(T_916, 5, 0) - infer accessor T_919 = tgtPages[UInt<3>("h04")] - node T_921 = dshl(UInt<1>("h01"), T_919) - node T_922 = bits(T_921, 5, 0) - infer accessor T_924 = tgtPages[UInt<3>("h05")] - node T_926 = dshl(UInt<1>("h01"), T_924) - node T_927 = bits(T_926, 5, 0) - infer accessor T_929 = tgtPages[UInt<3>("h06")] - node T_931 = dshl(UInt<1>("h01"), T_929) - node T_932 = bits(T_931, 5, 0) - infer accessor T_934 = tgtPages[UInt<3>("h07")] - node T_936 = dshl(UInt<1>("h01"), T_934) - node T_937 = bits(T_936, 5, 0) - infer accessor T_939 = tgtPages[UInt<4>("h08")] - node T_941 = dshl(UInt<1>("h01"), T_939) - node T_942 = bits(T_941, 5, 0) - infer accessor T_944 = tgtPages[UInt<4>("h09")] - node T_946 = dshl(UInt<1>("h01"), T_944) - node T_947 = bits(T_946, 5, 0) - infer accessor T_949 = tgtPages[UInt<4>("h0a")] - node T_951 = dshl(UInt<1>("h01"), T_949) - node T_952 = bits(T_951, 5, 0) - infer accessor T_954 = tgtPages[UInt<4>("h0b")] - node T_956 = dshl(UInt<1>("h01"), T_954) - node T_957 = bits(T_956, 5, 0) - infer accessor T_959 = tgtPages[UInt<4>("h0c")] - node T_961 = dshl(UInt<1>("h01"), T_959) - node T_962 = bits(T_961, 5, 0) - infer accessor T_964 = tgtPages[UInt<4>("h0d")] - node T_966 = dshl(UInt<1>("h01"), T_964) - node T_967 = bits(T_966, 5, 0) - infer accessor T_969 = tgtPages[UInt<4>("h0e")] - node T_971 = dshl(UInt<1>("h01"), T_969) - node T_972 = bits(T_971, 5, 0) - infer accessor T_974 = tgtPages[UInt<4>("h0f")] - node T_976 = dshl(UInt<1>("h01"), T_974) - node T_977 = bits(T_976, 5, 0) - infer accessor T_979 = tgtPages[UInt<5>("h010")] - node T_981 = dshl(UInt<1>("h01"), T_979) - node T_982 = bits(T_981, 5, 0) - infer accessor T_984 = tgtPages[UInt<5>("h011")] - node T_986 = dshl(UInt<1>("h01"), T_984) - node T_987 = bits(T_986, 5, 0) - infer accessor T_989 = tgtPages[UInt<5>("h012")] - node T_991 = dshl(UInt<1>("h01"), T_989) - node T_992 = bits(T_991, 5, 0) - infer accessor T_994 = tgtPages[UInt<5>("h013")] - node T_996 = dshl(UInt<1>("h01"), T_994) - node T_997 = bits(T_996, 5, 0) - infer accessor T_999 = tgtPages[UInt<5>("h014")] - node T_1001 = dshl(UInt<1>("h01"), T_999) - node T_1002 = bits(T_1001, 5, 0) - infer accessor T_1004 = tgtPages[UInt<5>("h015")] - node T_1006 = dshl(UInt<1>("h01"), T_1004) - node T_1007 = bits(T_1006, 5, 0) - infer accessor T_1009 = tgtPages[UInt<5>("h016")] - node T_1011 = dshl(UInt<1>("h01"), T_1009) - node T_1012 = bits(T_1011, 5, 0) - infer accessor T_1014 = tgtPages[UInt<5>("h017")] - node T_1016 = dshl(UInt<1>("h01"), T_1014) - node T_1017 = bits(T_1016, 5, 0) - infer accessor T_1019 = tgtPages[UInt<5>("h018")] - node T_1021 = dshl(UInt<1>("h01"), T_1019) - node T_1022 = bits(T_1021, 5, 0) - infer accessor T_1024 = tgtPages[UInt<5>("h019")] - node T_1026 = dshl(UInt<1>("h01"), T_1024) - node T_1027 = bits(T_1026, 5, 0) - infer accessor T_1029 = tgtPages[UInt<5>("h01a")] - node T_1031 = dshl(UInt<1>("h01"), T_1029) - node T_1032 = bits(T_1031, 5, 0) - infer accessor T_1034 = tgtPages[UInt<5>("h01b")] - node T_1036 = dshl(UInt<1>("h01"), T_1034) - node T_1037 = bits(T_1036, 5, 0) - infer accessor T_1039 = tgtPages[UInt<5>("h01c")] - node T_1041 = dshl(UInt<1>("h01"), T_1039) - node T_1042 = bits(T_1041, 5, 0) - infer accessor T_1044 = tgtPages[UInt<5>("h01d")] - node T_1046 = dshl(UInt<1>("h01"), T_1044) - node T_1047 = bits(T_1046, 5, 0) - infer accessor T_1049 = tgtPages[UInt<5>("h01e")] - node T_1051 = dshl(UInt<1>("h01"), T_1049) - node T_1052 = bits(T_1051, 5, 0) - infer accessor T_1054 = tgtPages[UInt<5>("h01f")] - node T_1056 = dshl(UInt<1>("h01"), T_1054) - node T_1057 = bits(T_1056, 5, 0) - infer accessor T_1059 = tgtPages[UInt<6>("h020")] - node T_1061 = dshl(UInt<1>("h01"), T_1059) - node T_1062 = bits(T_1061, 5, 0) - infer accessor T_1064 = tgtPages[UInt<6>("h021")] - node T_1066 = dshl(UInt<1>("h01"), T_1064) - node T_1067 = bits(T_1066, 5, 0) - infer accessor T_1069 = tgtPages[UInt<6>("h022")] - node T_1071 = dshl(UInt<1>("h01"), T_1069) - node T_1072 = bits(T_1071, 5, 0) - infer accessor T_1074 = tgtPages[UInt<6>("h023")] - node T_1076 = dshl(UInt<1>("h01"), T_1074) - node T_1077 = bits(T_1076, 5, 0) - infer accessor T_1079 = tgtPages[UInt<6>("h024")] - node T_1081 = dshl(UInt<1>("h01"), T_1079) - node T_1082 = bits(T_1081, 5, 0) - infer accessor T_1084 = tgtPages[UInt<6>("h025")] - node T_1086 = dshl(UInt<1>("h01"), T_1084) - node T_1087 = bits(T_1086, 5, 0) - infer accessor T_1089 = tgtPages[UInt<6>("h026")] - node T_1091 = dshl(UInt<1>("h01"), T_1089) - node T_1092 = bits(T_1091, 5, 0) - infer accessor T_1094 = tgtPages[UInt<6>("h027")] - node T_1096 = dshl(UInt<1>("h01"), T_1094) - node T_1097 = bits(T_1096, 5, 0) - infer accessor T_1099 = tgtPages[UInt<6>("h028")] - node T_1101 = dshl(UInt<1>("h01"), T_1099) - node T_1102 = bits(T_1101, 5, 0) - infer accessor T_1104 = tgtPages[UInt<6>("h029")] - node T_1106 = dshl(UInt<1>("h01"), T_1104) - node T_1107 = bits(T_1106, 5, 0) - infer accessor T_1109 = tgtPages[UInt<6>("h02a")] - node T_1111 = dshl(UInt<1>("h01"), T_1109) - node T_1112 = bits(T_1111, 5, 0) - infer accessor T_1114 = tgtPages[UInt<6>("h02b")] - node T_1116 = dshl(UInt<1>("h01"), T_1114) - node T_1117 = bits(T_1116, 5, 0) - infer accessor T_1119 = tgtPages[UInt<6>("h02c")] - node T_1121 = dshl(UInt<1>("h01"), T_1119) - node T_1122 = bits(T_1121, 5, 0) - infer accessor T_1124 = tgtPages[UInt<6>("h02d")] - node T_1126 = dshl(UInt<1>("h01"), T_1124) - node T_1127 = bits(T_1126, 5, 0) - infer accessor T_1129 = tgtPages[UInt<6>("h02e")] - node T_1131 = dshl(UInt<1>("h01"), T_1129) - node T_1132 = bits(T_1131, 5, 0) - infer accessor T_1134 = tgtPages[UInt<6>("h02f")] - node T_1136 = dshl(UInt<1>("h01"), T_1134) - node T_1137 = bits(T_1136, 5, 0) - infer accessor T_1139 = tgtPages[UInt<6>("h030")] - node T_1141 = dshl(UInt<1>("h01"), T_1139) - node T_1142 = bits(T_1141, 5, 0) - infer accessor T_1144 = tgtPages[UInt<6>("h031")] - node T_1146 = dshl(UInt<1>("h01"), T_1144) - node T_1147 = bits(T_1146, 5, 0) - infer accessor T_1149 = tgtPages[UInt<6>("h032")] - node T_1151 = dshl(UInt<1>("h01"), T_1149) - node T_1152 = bits(T_1151, 5, 0) - infer accessor T_1154 = tgtPages[UInt<6>("h033")] - node T_1156 = dshl(UInt<1>("h01"), T_1154) - node T_1157 = bits(T_1156, 5, 0) - infer accessor T_1159 = tgtPages[UInt<6>("h034")] - node T_1161 = dshl(UInt<1>("h01"), T_1159) - node T_1162 = bits(T_1161, 5, 0) - infer accessor T_1164 = tgtPages[UInt<6>("h035")] - node T_1166 = dshl(UInt<1>("h01"), T_1164) - node T_1167 = bits(T_1166, 5, 0) - infer accessor T_1169 = tgtPages[UInt<6>("h036")] - node T_1171 = dshl(UInt<1>("h01"), T_1169) - node T_1172 = bits(T_1171, 5, 0) - infer accessor T_1174 = tgtPages[UInt<6>("h037")] - node T_1176 = dshl(UInt<1>("h01"), T_1174) - node T_1177 = bits(T_1176, 5, 0) - infer accessor T_1179 = tgtPages[UInt<6>("h038")] - node T_1181 = dshl(UInt<1>("h01"), T_1179) - node T_1182 = bits(T_1181, 5, 0) - infer accessor T_1184 = tgtPages[UInt<6>("h039")] - node T_1186 = dshl(UInt<1>("h01"), T_1184) - node T_1187 = bits(T_1186, 5, 0) - infer accessor T_1189 = tgtPages[UInt<6>("h03a")] - node T_1191 = dshl(UInt<1>("h01"), T_1189) - node T_1192 = bits(T_1191, 5, 0) - infer accessor T_1194 = tgtPages[UInt<6>("h03b")] - node T_1196 = dshl(UInt<1>("h01"), T_1194) - node T_1197 = bits(T_1196, 5, 0) - infer accessor T_1199 = tgtPages[UInt<6>("h03c")] - node T_1201 = dshl(UInt<1>("h01"), T_1199) - node T_1202 = bits(T_1201, 5, 0) - infer accessor T_1204 = tgtPages[UInt<6>("h03d")] - node T_1206 = dshl(UInt<1>("h01"), T_1204) - node T_1207 = bits(T_1206, 5, 0) - reg useRAS : UInt<1>[62], clock, reset - reg isJump : UInt<1>[62], clock, reset - cmem brIdx : UInt<1>[62], clock - reg T_1477 : UInt<1>, clock, reset - onreset T_1477 := UInt<1>("h00") - T_1477 := btb_update.valid - reg T_1478 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clock, reset - when btb_update.valid : - T_1478 <> btb_update.bits - skip - wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} - r_btb_update.bits.br_pc := UInt<1>("h00") - r_btb_update.bits.isReturn := UInt<1>("h00") - r_btb_update.bits.isJump := UInt<1>("h00") - r_btb_update.bits.taken := UInt<1>("h00") - r_btb_update.bits.target := UInt<1>("h00") - r_btb_update.bits.pc := UInt<1>("h00") - r_btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") - r_btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") - r_btb_update.bits.prediction.bits.entry := UInt<1>("h00") - r_btb_update.bits.prediction.bits.target := UInt<1>("h00") - r_btb_update.bits.prediction.bits.bridx := UInt<1>("h00") - r_btb_update.bits.prediction.bits.mask := UInt<1>("h00") - r_btb_update.bits.prediction.bits.taken := UInt<1>("h00") - r_btb_update.bits.prediction.valid := UInt<1>("h00") - r_btb_update.valid := UInt<1>("h00") - r_btb_update.valid := T_1477 - r_btb_update.bits <> T_1478 - node T_1677 = shr(req.bits.addr, 12) - infer accessor T_1679 = pages[UInt<1>("h00")] - node T_1680 = eq(T_1679, T_1677) - infer accessor T_1682 = pages[UInt<1>("h01")] - node T_1683 = eq(T_1682, T_1677) - infer accessor T_1685 = pages[UInt<2>("h02")] - node T_1686 = eq(T_1685, T_1677) - infer accessor T_1688 = pages[UInt<2>("h03")] - node T_1689 = eq(T_1688, T_1677) - infer accessor T_1691 = pages[UInt<3>("h04")] - node T_1692 = eq(T_1691, T_1677) - infer accessor T_1694 = pages[UInt<3>("h05")] - node T_1695 = eq(T_1694, T_1677) - wire T_1697 : UInt<1>[6] - T_1697[0] := T_1680 - T_1697[1] := T_1683 - T_1697[2] := T_1686 - T_1697[3] := T_1689 - T_1697[4] := T_1692 - T_1697[5] := T_1695 - node T_1705 = cat(T_1697[4], T_1697[3]) - node T_1706 = cat(T_1697[5], T_1705) - node T_1707 = cat(T_1697[1], T_1697[0]) - node T_1708 = cat(T_1697[2], T_1707) - node T_1709 = cat(T_1706, T_1708) - node pageHit = and(T_1709, pageValid) - node T_1711 = bits(req.bits.addr, 11, 0) - infer accessor T_1713 = idxs[UInt<1>("h00")] - node T_1714 = eq(T_1713, T_1711) - infer accessor T_1716 = idxs[UInt<1>("h01")] - node T_1717 = eq(T_1716, T_1711) - infer accessor T_1719 = idxs[UInt<2>("h02")] - node T_1720 = eq(T_1719, T_1711) - infer accessor T_1722 = idxs[UInt<2>("h03")] - node T_1723 = eq(T_1722, T_1711) - infer accessor T_1725 = idxs[UInt<3>("h04")] - node T_1726 = eq(T_1725, T_1711) - infer accessor T_1728 = idxs[UInt<3>("h05")] - node T_1729 = eq(T_1728, T_1711) - infer accessor T_1731 = idxs[UInt<3>("h06")] - node T_1732 = eq(T_1731, T_1711) - infer accessor T_1734 = idxs[UInt<3>("h07")] - node T_1735 = eq(T_1734, T_1711) - infer accessor T_1737 = idxs[UInt<4>("h08")] - node T_1738 = eq(T_1737, T_1711) - infer accessor T_1740 = idxs[UInt<4>("h09")] - node T_1741 = eq(T_1740, T_1711) - infer accessor T_1743 = idxs[UInt<4>("h0a")] - node T_1744 = eq(T_1743, T_1711) - infer accessor T_1746 = idxs[UInt<4>("h0b")] - node T_1747 = eq(T_1746, T_1711) - infer accessor T_1749 = idxs[UInt<4>("h0c")] - node T_1750 = eq(T_1749, T_1711) - infer accessor T_1752 = idxs[UInt<4>("h0d")] - node T_1753 = eq(T_1752, T_1711) - infer accessor T_1755 = idxs[UInt<4>("h0e")] - node T_1756 = eq(T_1755, T_1711) - infer accessor T_1758 = idxs[UInt<4>("h0f")] - node T_1759 = eq(T_1758, T_1711) - infer accessor T_1761 = idxs[UInt<5>("h010")] - node T_1762 = eq(T_1761, T_1711) - infer accessor T_1764 = idxs[UInt<5>("h011")] - node T_1765 = eq(T_1764, T_1711) - infer accessor T_1767 = idxs[UInt<5>("h012")] - node T_1768 = eq(T_1767, T_1711) - infer accessor T_1770 = idxs[UInt<5>("h013")] - node T_1771 = eq(T_1770, T_1711) - infer accessor T_1773 = idxs[UInt<5>("h014")] - node T_1774 = eq(T_1773, T_1711) - infer accessor T_1776 = idxs[UInt<5>("h015")] - node T_1777 = eq(T_1776, T_1711) - infer accessor T_1779 = idxs[UInt<5>("h016")] - node T_1780 = eq(T_1779, T_1711) - infer accessor T_1782 = idxs[UInt<5>("h017")] - node T_1783 = eq(T_1782, T_1711) - infer accessor T_1785 = idxs[UInt<5>("h018")] - node T_1786 = eq(T_1785, T_1711) - infer accessor T_1788 = idxs[UInt<5>("h019")] - node T_1789 = eq(T_1788, T_1711) - infer accessor T_1791 = idxs[UInt<5>("h01a")] - node T_1792 = eq(T_1791, T_1711) - infer accessor T_1794 = idxs[UInt<5>("h01b")] - node T_1795 = eq(T_1794, T_1711) - infer accessor T_1797 = idxs[UInt<5>("h01c")] - node T_1798 = eq(T_1797, T_1711) - infer accessor T_1800 = idxs[UInt<5>("h01d")] - node T_1801 = eq(T_1800, T_1711) - infer accessor T_1803 = idxs[UInt<5>("h01e")] - node T_1804 = eq(T_1803, T_1711) - infer accessor T_1806 = idxs[UInt<5>("h01f")] - node T_1807 = eq(T_1806, T_1711) - infer accessor T_1809 = idxs[UInt<6>("h020")] - node T_1810 = eq(T_1809, T_1711) - infer accessor T_1812 = idxs[UInt<6>("h021")] - node T_1813 = eq(T_1812, T_1711) - infer accessor T_1815 = idxs[UInt<6>("h022")] - node T_1816 = eq(T_1815, T_1711) - infer accessor T_1818 = idxs[UInt<6>("h023")] - node T_1819 = eq(T_1818, T_1711) - infer accessor T_1821 = idxs[UInt<6>("h024")] - node T_1822 = eq(T_1821, T_1711) - infer accessor T_1824 = idxs[UInt<6>("h025")] - node T_1825 = eq(T_1824, T_1711) - infer accessor T_1827 = idxs[UInt<6>("h026")] - node T_1828 = eq(T_1827, T_1711) - infer accessor T_1830 = idxs[UInt<6>("h027")] - node T_1831 = eq(T_1830, T_1711) - infer accessor T_1833 = idxs[UInt<6>("h028")] - node T_1834 = eq(T_1833, T_1711) - infer accessor T_1836 = idxs[UInt<6>("h029")] - node T_1837 = eq(T_1836, T_1711) - infer accessor T_1839 = idxs[UInt<6>("h02a")] - node T_1840 = eq(T_1839, T_1711) - infer accessor T_1842 = idxs[UInt<6>("h02b")] - node T_1843 = eq(T_1842, T_1711) - infer accessor T_1845 = idxs[UInt<6>("h02c")] - node T_1846 = eq(T_1845, T_1711) - infer accessor T_1848 = idxs[UInt<6>("h02d")] - node T_1849 = eq(T_1848, T_1711) - infer accessor T_1851 = idxs[UInt<6>("h02e")] - node T_1852 = eq(T_1851, T_1711) - infer accessor T_1854 = idxs[UInt<6>("h02f")] - node T_1855 = eq(T_1854, T_1711) - infer accessor T_1857 = idxs[UInt<6>("h030")] - node T_1858 = eq(T_1857, T_1711) - infer accessor T_1860 = idxs[UInt<6>("h031")] - node T_1861 = eq(T_1860, T_1711) - infer accessor T_1863 = idxs[UInt<6>("h032")] - node T_1864 = eq(T_1863, T_1711) - infer accessor T_1866 = idxs[UInt<6>("h033")] - node T_1867 = eq(T_1866, T_1711) - infer accessor T_1869 = idxs[UInt<6>("h034")] - node T_1870 = eq(T_1869, T_1711) - infer accessor T_1872 = idxs[UInt<6>("h035")] - node T_1873 = eq(T_1872, T_1711) - infer accessor T_1875 = idxs[UInt<6>("h036")] - node T_1876 = eq(T_1875, T_1711) - infer accessor T_1878 = idxs[UInt<6>("h037")] - node T_1879 = eq(T_1878, T_1711) - infer accessor T_1881 = idxs[UInt<6>("h038")] - node T_1882 = eq(T_1881, T_1711) - infer accessor T_1884 = idxs[UInt<6>("h039")] - node T_1885 = eq(T_1884, T_1711) - infer accessor T_1887 = idxs[UInt<6>("h03a")] - node T_1888 = eq(T_1887, T_1711) - infer accessor T_1890 = idxs[UInt<6>("h03b")] - node T_1891 = eq(T_1890, T_1711) - infer accessor T_1893 = idxs[UInt<6>("h03c")] - node T_1894 = eq(T_1893, T_1711) - infer accessor T_1896 = idxs[UInt<6>("h03d")] - node T_1897 = eq(T_1896, T_1711) - wire T_1899 : UInt<1>[62] - T_1899[0] := T_1714 - T_1899[1] := T_1717 - T_1899[2] := T_1720 - T_1899[3] := T_1723 - T_1899[4] := T_1726 - T_1899[5] := T_1729 - T_1899[6] := T_1732 - T_1899[7] := T_1735 - T_1899[8] := T_1738 - T_1899[9] := T_1741 - T_1899[10] := T_1744 - T_1899[11] := T_1747 - T_1899[12] := T_1750 - T_1899[13] := T_1753 - T_1899[14] := T_1756 - T_1899[15] := T_1759 - T_1899[16] := T_1762 - T_1899[17] := T_1765 - T_1899[18] := T_1768 - T_1899[19] := T_1771 - T_1899[20] := T_1774 - T_1899[21] := T_1777 - T_1899[22] := T_1780 - T_1899[23] := T_1783 - T_1899[24] := T_1786 - T_1899[25] := T_1789 - T_1899[26] := T_1792 - T_1899[27] := T_1795 - T_1899[28] := T_1798 - T_1899[29] := T_1801 - T_1899[30] := T_1804 - T_1899[31] := T_1807 - T_1899[32] := T_1810 - T_1899[33] := T_1813 - T_1899[34] := T_1816 - T_1899[35] := T_1819 - T_1899[36] := T_1822 - T_1899[37] := T_1825 - T_1899[38] := T_1828 - T_1899[39] := T_1831 - T_1899[40] := T_1834 - T_1899[41] := T_1837 - T_1899[42] := T_1840 - T_1899[43] := T_1843 - T_1899[44] := T_1846 - T_1899[45] := T_1849 - T_1899[46] := T_1852 - T_1899[47] := T_1855 - T_1899[48] := T_1858 - T_1899[49] := T_1861 - T_1899[50] := T_1864 - T_1899[51] := T_1867 - T_1899[52] := T_1870 - T_1899[53] := T_1873 - T_1899[54] := T_1876 - T_1899[55] := T_1879 - T_1899[56] := T_1882 - T_1899[57] := T_1885 - T_1899[58] := T_1888 - T_1899[59] := T_1891 - T_1899[60] := T_1894 - T_1899[61] := T_1897 - node T_1963 = cat(T_1899[60], T_1899[59]) - node T_1964 = cat(T_1899[61], T_1963) - node T_1965 = cat(T_1899[58], T_1899[57]) - node T_1966 = cat(T_1899[56], T_1899[55]) - node T_1967 = cat(T_1965, T_1966) - node T_1968 = cat(T_1964, T_1967) - node T_1969 = cat(T_1899[54], T_1899[53]) - node T_1970 = cat(T_1899[52], T_1899[51]) - node T_1971 = cat(T_1969, T_1970) - node T_1972 = cat(T_1899[50], T_1899[49]) - node T_1973 = cat(T_1899[48], T_1899[47]) - node T_1974 = cat(T_1972, T_1973) - node T_1975 = cat(T_1971, T_1974) - node T_1976 = cat(T_1968, T_1975) - node T_1977 = cat(T_1899[46], T_1899[45]) - node T_1978 = cat(T_1899[44], T_1899[43]) - node T_1979 = cat(T_1977, T_1978) - node T_1980 = cat(T_1899[42], T_1899[41]) - node T_1981 = cat(T_1899[40], T_1899[39]) - node T_1982 = cat(T_1980, T_1981) - node T_1983 = cat(T_1979, T_1982) - node T_1984 = cat(T_1899[38], T_1899[37]) - node T_1985 = cat(T_1899[36], T_1899[35]) - node T_1986 = cat(T_1984, T_1985) - node T_1987 = cat(T_1899[34], T_1899[33]) - node T_1988 = cat(T_1899[32], T_1899[31]) - node T_1989 = cat(T_1987, T_1988) - node T_1990 = cat(T_1986, T_1989) - node T_1991 = cat(T_1983, T_1990) - node T_1992 = cat(T_1976, T_1991) - node T_1993 = cat(T_1899[29], T_1899[28]) - node T_1994 = cat(T_1899[30], T_1993) - node T_1995 = cat(T_1899[27], T_1899[26]) - node T_1996 = cat(T_1899[25], T_1899[24]) - node T_1997 = cat(T_1995, T_1996) - node T_1998 = cat(T_1994, T_1997) - node T_1999 = cat(T_1899[23], T_1899[22]) - node T_2000 = cat(T_1899[21], T_1899[20]) - node T_2001 = cat(T_1999, T_2000) - node T_2002 = cat(T_1899[19], T_1899[18]) - node T_2003 = cat(T_1899[17], T_1899[16]) - node T_2004 = cat(T_2002, T_2003) - node T_2005 = cat(T_2001, T_2004) - node T_2006 = cat(T_1998, T_2005) - node T_2007 = cat(T_1899[15], T_1899[14]) - node T_2008 = cat(T_1899[13], T_1899[12]) - node T_2009 = cat(T_2007, T_2008) - node T_2010 = cat(T_1899[11], T_1899[10]) - node T_2011 = cat(T_1899[9], T_1899[8]) - node T_2012 = cat(T_2010, T_2011) - node T_2013 = cat(T_2009, T_2012) - node T_2014 = cat(T_1899[7], T_1899[6]) - node T_2015 = cat(T_1899[5], T_1899[4]) - node T_2016 = cat(T_2014, T_2015) - node T_2017 = cat(T_1899[3], T_1899[2]) - node T_2018 = cat(T_1899[1], T_1899[0]) - node T_2019 = cat(T_2017, T_2018) - node T_2020 = cat(T_2016, T_2019) - node T_2021 = cat(T_2013, T_2020) - node T_2022 = cat(T_2006, T_2021) - node T_2023 = cat(T_1992, T_2022) - node T_2024 = and(T_592, pageHit) - node T_2025 = and(T_597, pageHit) - node T_2026 = and(T_602, pageHit) - node T_2027 = and(T_607, pageHit) - node T_2028 = and(T_612, pageHit) - node T_2029 = and(T_617, pageHit) - node T_2030 = and(T_622, pageHit) - node T_2031 = and(T_627, pageHit) - node T_2032 = and(T_632, pageHit) - node T_2033 = and(T_637, pageHit) - node T_2034 = and(T_642, pageHit) - node T_2035 = and(T_647, pageHit) - node T_2036 = and(T_652, pageHit) - node T_2037 = and(T_657, pageHit) - node T_2038 = and(T_662, pageHit) - node T_2039 = and(T_667, pageHit) - node T_2040 = and(T_672, pageHit) - node T_2041 = and(T_677, pageHit) - node T_2042 = and(T_682, pageHit) - node T_2043 = and(T_687, pageHit) - node T_2044 = and(T_692, pageHit) - node T_2045 = and(T_697, pageHit) - node T_2046 = and(T_702, pageHit) - node T_2047 = and(T_707, pageHit) - node T_2048 = and(T_712, pageHit) - node T_2049 = and(T_717, pageHit) - node T_2050 = and(T_722, pageHit) - node T_2051 = and(T_727, pageHit) - node T_2052 = and(T_732, pageHit) - node T_2053 = and(T_737, pageHit) - node T_2054 = and(T_742, pageHit) - node T_2055 = and(T_747, pageHit) - node T_2056 = and(T_752, pageHit) - node T_2057 = and(T_757, pageHit) - node T_2058 = and(T_762, pageHit) - node T_2059 = and(T_767, pageHit) - node T_2060 = and(T_772, pageHit) - node T_2061 = and(T_777, pageHit) - node T_2062 = and(T_782, pageHit) - node T_2063 = and(T_787, pageHit) - node T_2064 = and(T_792, pageHit) - node T_2065 = and(T_797, pageHit) - node T_2066 = and(T_802, pageHit) - node T_2067 = and(T_807, pageHit) - node T_2068 = and(T_812, pageHit) - node T_2069 = and(T_817, pageHit) - node T_2070 = and(T_822, pageHit) - node T_2071 = and(T_827, pageHit) - node T_2072 = and(T_832, pageHit) - node T_2073 = and(T_837, pageHit) - node T_2074 = and(T_842, pageHit) - node T_2075 = and(T_847, pageHit) - node T_2076 = and(T_852, pageHit) - node T_2077 = and(T_857, pageHit) - node T_2078 = and(T_862, pageHit) - node T_2079 = and(T_867, pageHit) - node T_2080 = and(T_872, pageHit) - node T_2081 = and(T_877, pageHit) - node T_2082 = and(T_882, pageHit) - node T_2083 = and(T_887, pageHit) - node T_2084 = and(T_892, pageHit) - node T_2085 = and(T_897, pageHit) - node T_2087 = neq(T_2024, UInt<1>("h00")) - node T_2089 = neq(T_2025, UInt<1>("h00")) - node T_2091 = neq(T_2026, UInt<1>("h00")) - node T_2093 = neq(T_2027, UInt<1>("h00")) - node T_2095 = neq(T_2028, UInt<1>("h00")) - node T_2097 = neq(T_2029, UInt<1>("h00")) - node T_2099 = neq(T_2030, UInt<1>("h00")) - node T_2101 = neq(T_2031, UInt<1>("h00")) - node T_2103 = neq(T_2032, UInt<1>("h00")) - node T_2105 = neq(T_2033, UInt<1>("h00")) - node T_2107 = neq(T_2034, UInt<1>("h00")) - node T_2109 = neq(T_2035, UInt<1>("h00")) - node T_2111 = neq(T_2036, UInt<1>("h00")) - node T_2113 = neq(T_2037, UInt<1>("h00")) - node T_2115 = neq(T_2038, UInt<1>("h00")) - node T_2117 = neq(T_2039, UInt<1>("h00")) - node T_2119 = neq(T_2040, UInt<1>("h00")) - node T_2121 = neq(T_2041, UInt<1>("h00")) - node T_2123 = neq(T_2042, UInt<1>("h00")) - node T_2125 = neq(T_2043, UInt<1>("h00")) - node T_2127 = neq(T_2044, UInt<1>("h00")) - node T_2129 = neq(T_2045, UInt<1>("h00")) - node T_2131 = neq(T_2046, UInt<1>("h00")) - node T_2133 = neq(T_2047, UInt<1>("h00")) - node T_2135 = neq(T_2048, UInt<1>("h00")) - node T_2137 = neq(T_2049, UInt<1>("h00")) - node T_2139 = neq(T_2050, UInt<1>("h00")) - node T_2141 = neq(T_2051, UInt<1>("h00")) - node T_2143 = neq(T_2052, UInt<1>("h00")) - node T_2145 = neq(T_2053, UInt<1>("h00")) - node T_2147 = neq(T_2054, UInt<1>("h00")) - node T_2149 = neq(T_2055, UInt<1>("h00")) - node T_2151 = neq(T_2056, UInt<1>("h00")) - node T_2153 = neq(T_2057, UInt<1>("h00")) - node T_2155 = neq(T_2058, UInt<1>("h00")) - node T_2157 = neq(T_2059, UInt<1>("h00")) - node T_2159 = neq(T_2060, UInt<1>("h00")) - node T_2161 = neq(T_2061, UInt<1>("h00")) - node T_2163 = neq(T_2062, UInt<1>("h00")) - node T_2165 = neq(T_2063, UInt<1>("h00")) - node T_2167 = neq(T_2064, UInt<1>("h00")) - node T_2169 = neq(T_2065, UInt<1>("h00")) - node T_2171 = neq(T_2066, UInt<1>("h00")) - node T_2173 = neq(T_2067, UInt<1>("h00")) - node T_2175 = neq(T_2068, UInt<1>("h00")) - node T_2177 = neq(T_2069, UInt<1>("h00")) - node T_2179 = neq(T_2070, UInt<1>("h00")) - node T_2181 = neq(T_2071, UInt<1>("h00")) - node T_2183 = neq(T_2072, UInt<1>("h00")) - node T_2185 = neq(T_2073, UInt<1>("h00")) - node T_2187 = neq(T_2074, UInt<1>("h00")) - node T_2189 = neq(T_2075, UInt<1>("h00")) - node T_2191 = neq(T_2076, UInt<1>("h00")) - node T_2193 = neq(T_2077, UInt<1>("h00")) - node T_2195 = neq(T_2078, UInt<1>("h00")) - node T_2197 = neq(T_2079, UInt<1>("h00")) - node T_2199 = neq(T_2080, UInt<1>("h00")) - node T_2201 = neq(T_2081, UInt<1>("h00")) - node T_2203 = neq(T_2082, UInt<1>("h00")) - node T_2205 = neq(T_2083, UInt<1>("h00")) - node T_2207 = neq(T_2084, UInt<1>("h00")) - node T_2209 = neq(T_2085, UInt<1>("h00")) - wire T_2211 : UInt<1>[62] - T_2211[0] := T_2087 - T_2211[1] := T_2089 - T_2211[2] := T_2091 - T_2211[3] := T_2093 - T_2211[4] := T_2095 - T_2211[5] := T_2097 - T_2211[6] := T_2099 - T_2211[7] := T_2101 - T_2211[8] := T_2103 - T_2211[9] := T_2105 - T_2211[10] := T_2107 - T_2211[11] := T_2109 - T_2211[12] := T_2111 - T_2211[13] := T_2113 - T_2211[14] := T_2115 - T_2211[15] := T_2117 - T_2211[16] := T_2119 - T_2211[17] := T_2121 - T_2211[18] := T_2123 - T_2211[19] := T_2125 - T_2211[20] := T_2127 - T_2211[21] := T_2129 - T_2211[22] := T_2131 - T_2211[23] := T_2133 - T_2211[24] := T_2135 - T_2211[25] := T_2137 - T_2211[26] := T_2139 - T_2211[27] := T_2141 - T_2211[28] := T_2143 - T_2211[29] := T_2145 - T_2211[30] := T_2147 - T_2211[31] := T_2149 - T_2211[32] := T_2151 - T_2211[33] := T_2153 - T_2211[34] := T_2155 - T_2211[35] := T_2157 - T_2211[36] := T_2159 - T_2211[37] := T_2161 - T_2211[38] := T_2163 - T_2211[39] := T_2165 - T_2211[40] := T_2167 - T_2211[41] := T_2169 - T_2211[42] := T_2171 - T_2211[43] := T_2173 - T_2211[44] := T_2175 - T_2211[45] := T_2177 - T_2211[46] := T_2179 - T_2211[47] := T_2181 - T_2211[48] := T_2183 - T_2211[49] := T_2185 - T_2211[50] := T_2187 - T_2211[51] := T_2189 - T_2211[52] := T_2191 - T_2211[53] := T_2193 - T_2211[54] := T_2195 - T_2211[55] := T_2197 - T_2211[56] := T_2199 - T_2211[57] := T_2201 - T_2211[58] := T_2203 - T_2211[59] := T_2205 - T_2211[60] := T_2207 - T_2211[61] := T_2209 - node T_2275 = cat(T_2211[60], T_2211[59]) - node T_2276 = cat(T_2211[61], T_2275) - node T_2277 = cat(T_2211[58], T_2211[57]) - node T_2278 = cat(T_2211[56], T_2211[55]) - node T_2279 = cat(T_2277, T_2278) - node T_2280 = cat(T_2276, T_2279) - node T_2281 = cat(T_2211[54], T_2211[53]) - node T_2282 = cat(T_2211[52], T_2211[51]) - node T_2283 = cat(T_2281, T_2282) - node T_2284 = cat(T_2211[50], T_2211[49]) - node T_2285 = cat(T_2211[48], T_2211[47]) - node T_2286 = cat(T_2284, T_2285) - node T_2287 = cat(T_2283, T_2286) - node T_2288 = cat(T_2280, T_2287) - node T_2289 = cat(T_2211[46], T_2211[45]) - node T_2290 = cat(T_2211[44], T_2211[43]) - node T_2291 = cat(T_2289, T_2290) - node T_2292 = cat(T_2211[42], T_2211[41]) - node T_2293 = cat(T_2211[40], T_2211[39]) - node T_2294 = cat(T_2292, T_2293) - node T_2295 = cat(T_2291, T_2294) - node T_2296 = cat(T_2211[38], T_2211[37]) - node T_2297 = cat(T_2211[36], T_2211[35]) - node T_2298 = cat(T_2296, T_2297) - node T_2299 = cat(T_2211[34], T_2211[33]) - node T_2300 = cat(T_2211[32], T_2211[31]) - node T_2301 = cat(T_2299, T_2300) - node T_2302 = cat(T_2298, T_2301) - node T_2303 = cat(T_2295, T_2302) - node T_2304 = cat(T_2288, T_2303) - node T_2305 = cat(T_2211[29], T_2211[28]) - node T_2306 = cat(T_2211[30], T_2305) - node T_2307 = cat(T_2211[27], T_2211[26]) - node T_2308 = cat(T_2211[25], T_2211[24]) - node T_2309 = cat(T_2307, T_2308) - node T_2310 = cat(T_2306, T_2309) - node T_2311 = cat(T_2211[23], T_2211[22]) - node T_2312 = cat(T_2211[21], T_2211[20]) - node T_2313 = cat(T_2311, T_2312) - node T_2314 = cat(T_2211[19], T_2211[18]) - node T_2315 = cat(T_2211[17], T_2211[16]) - node T_2316 = cat(T_2314, T_2315) - node T_2317 = cat(T_2313, T_2316) - node T_2318 = cat(T_2310, T_2317) - node T_2319 = cat(T_2211[15], T_2211[14]) - node T_2320 = cat(T_2211[13], T_2211[12]) - node T_2321 = cat(T_2319, T_2320) - node T_2322 = cat(T_2211[11], T_2211[10]) - node T_2323 = cat(T_2211[9], T_2211[8]) - node T_2324 = cat(T_2322, T_2323) - node T_2325 = cat(T_2321, T_2324) - node T_2326 = cat(T_2211[7], T_2211[6]) - node T_2327 = cat(T_2211[5], T_2211[4]) - node T_2328 = cat(T_2326, T_2327) - node T_2329 = cat(T_2211[3], T_2211[2]) - node T_2330 = cat(T_2211[1], T_2211[0]) - node T_2331 = cat(T_2329, T_2330) - node T_2332 = cat(T_2328, T_2331) - node T_2333 = cat(T_2325, T_2332) - node T_2334 = cat(T_2318, T_2333) - node T_2335 = cat(T_2304, T_2334) - node T_2336 = and(idxValid, T_2023) - node hits = and(T_2336, T_2335) - node T_2338 = shr(r_btb_update.bits.pc, 12) - infer accessor T_2340 = pages[UInt<1>("h00")] - node T_2341 = eq(T_2340, T_2338) - infer accessor T_2343 = pages[UInt<1>("h01")] - node T_2344 = eq(T_2343, T_2338) - infer accessor T_2346 = pages[UInt<2>("h02")] - node T_2347 = eq(T_2346, T_2338) - infer accessor T_2349 = pages[UInt<2>("h03")] - node T_2350 = eq(T_2349, T_2338) - infer accessor T_2352 = pages[UInt<3>("h04")] - node T_2353 = eq(T_2352, T_2338) - infer accessor T_2355 = pages[UInt<3>("h05")] - node T_2356 = eq(T_2355, T_2338) - wire T_2358 : UInt<1>[6] - T_2358[0] := T_2341 - T_2358[1] := T_2344 - T_2358[2] := T_2347 - T_2358[3] := T_2350 - T_2358[4] := T_2353 - T_2358[5] := T_2356 - node T_2366 = cat(T_2358[4], T_2358[3]) - node T_2367 = cat(T_2358[5], T_2366) - node T_2368 = cat(T_2358[1], T_2358[0]) - node T_2369 = cat(T_2358[2], T_2368) - node T_2370 = cat(T_2367, T_2369) - node updatePageHit = and(T_2370, pageValid) - node T_2372 = bits(r_btb_update.bits.pc, 11, 0) - infer accessor T_2374 = idxs[UInt<1>("h00")] - node T_2375 = eq(T_2374, T_2372) - infer accessor T_2377 = idxs[UInt<1>("h01")] - node T_2378 = eq(T_2377, T_2372) - infer accessor T_2380 = idxs[UInt<2>("h02")] - node T_2381 = eq(T_2380, T_2372) - infer accessor T_2383 = idxs[UInt<2>("h03")] - node T_2384 = eq(T_2383, T_2372) - infer accessor T_2386 = idxs[UInt<3>("h04")] - node T_2387 = eq(T_2386, T_2372) - infer accessor T_2389 = idxs[UInt<3>("h05")] - node T_2390 = eq(T_2389, T_2372) - infer accessor T_2392 = idxs[UInt<3>("h06")] - node T_2393 = eq(T_2392, T_2372) - infer accessor T_2395 = idxs[UInt<3>("h07")] - node T_2396 = eq(T_2395, T_2372) - infer accessor T_2398 = idxs[UInt<4>("h08")] - node T_2399 = eq(T_2398, T_2372) - infer accessor T_2401 = idxs[UInt<4>("h09")] - node T_2402 = eq(T_2401, T_2372) - infer accessor T_2404 = idxs[UInt<4>("h0a")] - node T_2405 = eq(T_2404, T_2372) - infer accessor T_2407 = idxs[UInt<4>("h0b")] - node T_2408 = eq(T_2407, T_2372) - infer accessor T_2410 = idxs[UInt<4>("h0c")] - node T_2411 = eq(T_2410, T_2372) - infer accessor T_2413 = idxs[UInt<4>("h0d")] - node T_2414 = eq(T_2413, T_2372) - infer accessor T_2416 = idxs[UInt<4>("h0e")] - node T_2417 = eq(T_2416, T_2372) - infer accessor T_2419 = idxs[UInt<4>("h0f")] - node T_2420 = eq(T_2419, T_2372) - infer accessor T_2422 = idxs[UInt<5>("h010")] - node T_2423 = eq(T_2422, T_2372) - infer accessor T_2425 = idxs[UInt<5>("h011")] - node T_2426 = eq(T_2425, T_2372) - infer accessor T_2428 = idxs[UInt<5>("h012")] - node T_2429 = eq(T_2428, T_2372) - infer accessor T_2431 = idxs[UInt<5>("h013")] - node T_2432 = eq(T_2431, T_2372) - infer accessor T_2434 = idxs[UInt<5>("h014")] - node T_2435 = eq(T_2434, T_2372) - infer accessor T_2437 = idxs[UInt<5>("h015")] - node T_2438 = eq(T_2437, T_2372) - infer accessor T_2440 = idxs[UInt<5>("h016")] - node T_2441 = eq(T_2440, T_2372) - infer accessor T_2443 = idxs[UInt<5>("h017")] - node T_2444 = eq(T_2443, T_2372) - infer accessor T_2446 = idxs[UInt<5>("h018")] - node T_2447 = eq(T_2446, T_2372) - infer accessor T_2449 = idxs[UInt<5>("h019")] - node T_2450 = eq(T_2449, T_2372) - infer accessor T_2452 = idxs[UInt<5>("h01a")] - node T_2453 = eq(T_2452, T_2372) - infer accessor T_2455 = idxs[UInt<5>("h01b")] - node T_2456 = eq(T_2455, T_2372) - infer accessor T_2458 = idxs[UInt<5>("h01c")] - node T_2459 = eq(T_2458, T_2372) - infer accessor T_2461 = idxs[UInt<5>("h01d")] - node T_2462 = eq(T_2461, T_2372) - infer accessor T_2464 = idxs[UInt<5>("h01e")] - node T_2465 = eq(T_2464, T_2372) - infer accessor T_2467 = idxs[UInt<5>("h01f")] - node T_2468 = eq(T_2467, T_2372) - infer accessor T_2470 = idxs[UInt<6>("h020")] - node T_2471 = eq(T_2470, T_2372) - infer accessor T_2473 = idxs[UInt<6>("h021")] - node T_2474 = eq(T_2473, T_2372) - infer accessor T_2476 = idxs[UInt<6>("h022")] - node T_2477 = eq(T_2476, T_2372) - infer accessor T_2479 = idxs[UInt<6>("h023")] - node T_2480 = eq(T_2479, T_2372) - infer accessor T_2482 = idxs[UInt<6>("h024")] - node T_2483 = eq(T_2482, T_2372) - infer accessor T_2485 = idxs[UInt<6>("h025")] - node T_2486 = eq(T_2485, T_2372) - infer accessor T_2488 = idxs[UInt<6>("h026")] - node T_2489 = eq(T_2488, T_2372) - infer accessor T_2491 = idxs[UInt<6>("h027")] - node T_2492 = eq(T_2491, T_2372) - infer accessor T_2494 = idxs[UInt<6>("h028")] - node T_2495 = eq(T_2494, T_2372) - infer accessor T_2497 = idxs[UInt<6>("h029")] - node T_2498 = eq(T_2497, T_2372) - infer accessor T_2500 = idxs[UInt<6>("h02a")] - node T_2501 = eq(T_2500, T_2372) - infer accessor T_2503 = idxs[UInt<6>("h02b")] - node T_2504 = eq(T_2503, T_2372) - infer accessor T_2506 = idxs[UInt<6>("h02c")] - node T_2507 = eq(T_2506, T_2372) - infer accessor T_2509 = idxs[UInt<6>("h02d")] - node T_2510 = eq(T_2509, T_2372) - infer accessor T_2512 = idxs[UInt<6>("h02e")] - node T_2513 = eq(T_2512, T_2372) - infer accessor T_2515 = idxs[UInt<6>("h02f")] - node T_2516 = eq(T_2515, T_2372) - infer accessor T_2518 = idxs[UInt<6>("h030")] - node T_2519 = eq(T_2518, T_2372) - infer accessor T_2521 = idxs[UInt<6>("h031")] - node T_2522 = eq(T_2521, T_2372) - infer accessor T_2524 = idxs[UInt<6>("h032")] - node T_2525 = eq(T_2524, T_2372) - infer accessor T_2527 = idxs[UInt<6>("h033")] - node T_2528 = eq(T_2527, T_2372) - infer accessor T_2530 = idxs[UInt<6>("h034")] - node T_2531 = eq(T_2530, T_2372) - infer accessor T_2533 = idxs[UInt<6>("h035")] - node T_2534 = eq(T_2533, T_2372) - infer accessor T_2536 = idxs[UInt<6>("h036")] - node T_2537 = eq(T_2536, T_2372) - infer accessor T_2539 = idxs[UInt<6>("h037")] - node T_2540 = eq(T_2539, T_2372) - infer accessor T_2542 = idxs[UInt<6>("h038")] - node T_2543 = eq(T_2542, T_2372) - infer accessor T_2545 = idxs[UInt<6>("h039")] - node T_2546 = eq(T_2545, T_2372) - infer accessor T_2548 = idxs[UInt<6>("h03a")] - node T_2549 = eq(T_2548, T_2372) - infer accessor T_2551 = idxs[UInt<6>("h03b")] - node T_2552 = eq(T_2551, T_2372) - infer accessor T_2554 = idxs[UInt<6>("h03c")] - node T_2555 = eq(T_2554, T_2372) - infer accessor T_2557 = idxs[UInt<6>("h03d")] - node T_2558 = eq(T_2557, T_2372) - wire T_2560 : UInt<1>[62] - T_2560[0] := T_2375 - T_2560[1] := T_2378 - T_2560[2] := T_2381 - T_2560[3] := T_2384 - T_2560[4] := T_2387 - T_2560[5] := T_2390 - T_2560[6] := T_2393 - T_2560[7] := T_2396 - T_2560[8] := T_2399 - T_2560[9] := T_2402 - T_2560[10] := T_2405 - T_2560[11] := T_2408 - T_2560[12] := T_2411 - T_2560[13] := T_2414 - T_2560[14] := T_2417 - T_2560[15] := T_2420 - T_2560[16] := T_2423 - T_2560[17] := T_2426 - T_2560[18] := T_2429 - T_2560[19] := T_2432 - T_2560[20] := T_2435 - T_2560[21] := T_2438 - T_2560[22] := T_2441 - T_2560[23] := T_2444 - T_2560[24] := T_2447 - T_2560[25] := T_2450 - T_2560[26] := T_2453 - T_2560[27] := T_2456 - T_2560[28] := T_2459 - T_2560[29] := T_2462 - T_2560[30] := T_2465 - T_2560[31] := T_2468 - T_2560[32] := T_2471 - T_2560[33] := T_2474 - T_2560[34] := T_2477 - T_2560[35] := T_2480 - T_2560[36] := T_2483 - T_2560[37] := T_2486 - T_2560[38] := T_2489 - T_2560[39] := T_2492 - T_2560[40] := T_2495 - T_2560[41] := T_2498 - T_2560[42] := T_2501 - T_2560[43] := T_2504 - T_2560[44] := T_2507 - T_2560[45] := T_2510 - T_2560[46] := T_2513 - T_2560[47] := T_2516 - T_2560[48] := T_2519 - T_2560[49] := T_2522 - T_2560[50] := T_2525 - T_2560[51] := T_2528 - T_2560[52] := T_2531 - T_2560[53] := T_2534 - T_2560[54] := T_2537 - T_2560[55] := T_2540 - T_2560[56] := T_2543 - T_2560[57] := T_2546 - T_2560[58] := T_2549 - T_2560[59] := T_2552 - T_2560[60] := T_2555 - T_2560[61] := T_2558 - node T_2624 = cat(T_2560[60], T_2560[59]) - node T_2625 = cat(T_2560[61], T_2624) - node T_2626 = cat(T_2560[58], T_2560[57]) - node T_2627 = cat(T_2560[56], T_2560[55]) - node T_2628 = cat(T_2626, T_2627) - node T_2629 = cat(T_2625, T_2628) - node T_2630 = cat(T_2560[54], T_2560[53]) - node T_2631 = cat(T_2560[52], T_2560[51]) - node T_2632 = cat(T_2630, T_2631) - node T_2633 = cat(T_2560[50], T_2560[49]) - node T_2634 = cat(T_2560[48], T_2560[47]) - node T_2635 = cat(T_2633, T_2634) - node T_2636 = cat(T_2632, T_2635) - node T_2637 = cat(T_2629, T_2636) - node T_2638 = cat(T_2560[46], T_2560[45]) - node T_2639 = cat(T_2560[44], T_2560[43]) - node T_2640 = cat(T_2638, T_2639) - node T_2641 = cat(T_2560[42], T_2560[41]) - node T_2642 = cat(T_2560[40], T_2560[39]) - node T_2643 = cat(T_2641, T_2642) - node T_2644 = cat(T_2640, T_2643) - node T_2645 = cat(T_2560[38], T_2560[37]) - node T_2646 = cat(T_2560[36], T_2560[35]) - node T_2647 = cat(T_2645, T_2646) - node T_2648 = cat(T_2560[34], T_2560[33]) - node T_2649 = cat(T_2560[32], T_2560[31]) - node T_2650 = cat(T_2648, T_2649) - node T_2651 = cat(T_2647, T_2650) - node T_2652 = cat(T_2644, T_2651) - node T_2653 = cat(T_2637, T_2652) - node T_2654 = cat(T_2560[29], T_2560[28]) - node T_2655 = cat(T_2560[30], T_2654) - node T_2656 = cat(T_2560[27], T_2560[26]) - node T_2657 = cat(T_2560[25], T_2560[24]) - node T_2658 = cat(T_2656, T_2657) - node T_2659 = cat(T_2655, T_2658) - node T_2660 = cat(T_2560[23], T_2560[22]) - node T_2661 = cat(T_2560[21], T_2560[20]) - node T_2662 = cat(T_2660, T_2661) - node T_2663 = cat(T_2560[19], T_2560[18]) - node T_2664 = cat(T_2560[17], T_2560[16]) - node T_2665 = cat(T_2663, T_2664) - node T_2666 = cat(T_2662, T_2665) - node T_2667 = cat(T_2659, T_2666) - node T_2668 = cat(T_2560[15], T_2560[14]) - node T_2669 = cat(T_2560[13], T_2560[12]) - node T_2670 = cat(T_2668, T_2669) - node T_2671 = cat(T_2560[11], T_2560[10]) - node T_2672 = cat(T_2560[9], T_2560[8]) - node T_2673 = cat(T_2671, T_2672) - node T_2674 = cat(T_2670, T_2673) - node T_2675 = cat(T_2560[7], T_2560[6]) - node T_2676 = cat(T_2560[5], T_2560[4]) - node T_2677 = cat(T_2675, T_2676) - node T_2678 = cat(T_2560[3], T_2560[2]) - node T_2679 = cat(T_2560[1], T_2560[0]) - node T_2680 = cat(T_2678, T_2679) - node T_2681 = cat(T_2677, T_2680) - node T_2682 = cat(T_2674, T_2681) - node T_2683 = cat(T_2667, T_2682) - node T_2684 = cat(T_2653, T_2683) - node T_2685 = and(T_592, updatePageHit) - node T_2686 = and(T_597, updatePageHit) - node T_2687 = and(T_602, updatePageHit) - node T_2688 = and(T_607, updatePageHit) - node T_2689 = and(T_612, updatePageHit) - node T_2690 = and(T_617, updatePageHit) - node T_2691 = and(T_622, updatePageHit) - node T_2692 = and(T_627, updatePageHit) - node T_2693 = and(T_632, updatePageHit) - node T_2694 = and(T_637, updatePageHit) - node T_2695 = and(T_642, updatePageHit) - node T_2696 = and(T_647, updatePageHit) - node T_2697 = and(T_652, updatePageHit) - node T_2698 = and(T_657, updatePageHit) - node T_2699 = and(T_662, updatePageHit) - node T_2700 = and(T_667, updatePageHit) - node T_2701 = and(T_672, updatePageHit) - node T_2702 = and(T_677, updatePageHit) - node T_2703 = and(T_682, updatePageHit) - node T_2704 = and(T_687, updatePageHit) - node T_2705 = and(T_692, updatePageHit) - node T_2706 = and(T_697, updatePageHit) - node T_2707 = and(T_702, updatePageHit) - node T_2708 = and(T_707, updatePageHit) - node T_2709 = and(T_712, updatePageHit) - node T_2710 = and(T_717, updatePageHit) - node T_2711 = and(T_722, updatePageHit) - node T_2712 = and(T_727, updatePageHit) - node T_2713 = and(T_732, updatePageHit) - node T_2714 = and(T_737, updatePageHit) - node T_2715 = and(T_742, updatePageHit) - node T_2716 = and(T_747, updatePageHit) - node T_2717 = and(T_752, updatePageHit) - node T_2718 = and(T_757, updatePageHit) - node T_2719 = and(T_762, updatePageHit) - node T_2720 = and(T_767, updatePageHit) - node T_2721 = and(T_772, updatePageHit) - node T_2722 = and(T_777, updatePageHit) - node T_2723 = and(T_782, updatePageHit) - node T_2724 = and(T_787, updatePageHit) - node T_2725 = and(T_792, updatePageHit) - node T_2726 = and(T_797, updatePageHit) - node T_2727 = and(T_802, updatePageHit) - node T_2728 = and(T_807, updatePageHit) - node T_2729 = and(T_812, updatePageHit) - node T_2730 = and(T_817, updatePageHit) - node T_2731 = and(T_822, updatePageHit) - node T_2732 = and(T_827, updatePageHit) - node T_2733 = and(T_832, updatePageHit) - node T_2734 = and(T_837, updatePageHit) - node T_2735 = and(T_842, updatePageHit) - node T_2736 = and(T_847, updatePageHit) - node T_2737 = and(T_852, updatePageHit) - node T_2738 = and(T_857, updatePageHit) - node T_2739 = and(T_862, updatePageHit) - node T_2740 = and(T_867, updatePageHit) - node T_2741 = and(T_872, updatePageHit) - node T_2742 = and(T_877, updatePageHit) - node T_2743 = and(T_882, updatePageHit) - node T_2744 = and(T_887, updatePageHit) - node T_2745 = and(T_892, updatePageHit) - node T_2746 = and(T_897, updatePageHit) - node T_2748 = neq(T_2685, UInt<1>("h00")) - node T_2750 = neq(T_2686, UInt<1>("h00")) - node T_2752 = neq(T_2687, UInt<1>("h00")) - node T_2754 = neq(T_2688, UInt<1>("h00")) - node T_2756 = neq(T_2689, UInt<1>("h00")) - node T_2758 = neq(T_2690, UInt<1>("h00")) - node T_2760 = neq(T_2691, UInt<1>("h00")) - node T_2762 = neq(T_2692, UInt<1>("h00")) - node T_2764 = neq(T_2693, UInt<1>("h00")) - node T_2766 = neq(T_2694, UInt<1>("h00")) - node T_2768 = neq(T_2695, UInt<1>("h00")) - node T_2770 = neq(T_2696, UInt<1>("h00")) - node T_2772 = neq(T_2697, UInt<1>("h00")) - node T_2774 = neq(T_2698, UInt<1>("h00")) - node T_2776 = neq(T_2699, UInt<1>("h00")) - node T_2778 = neq(T_2700, UInt<1>("h00")) - node T_2780 = neq(T_2701, UInt<1>("h00")) - node T_2782 = neq(T_2702, UInt<1>("h00")) - node T_2784 = neq(T_2703, UInt<1>("h00")) - node T_2786 = neq(T_2704, UInt<1>("h00")) - node T_2788 = neq(T_2705, UInt<1>("h00")) - node T_2790 = neq(T_2706, UInt<1>("h00")) - node T_2792 = neq(T_2707, UInt<1>("h00")) - node T_2794 = neq(T_2708, UInt<1>("h00")) - node T_2796 = neq(T_2709, UInt<1>("h00")) - node T_2798 = neq(T_2710, UInt<1>("h00")) - node T_2800 = neq(T_2711, UInt<1>("h00")) - node T_2802 = neq(T_2712, UInt<1>("h00")) - node T_2804 = neq(T_2713, UInt<1>("h00")) - node T_2806 = neq(T_2714, UInt<1>("h00")) - node T_2808 = neq(T_2715, UInt<1>("h00")) - node T_2810 = neq(T_2716, UInt<1>("h00")) - node T_2812 = neq(T_2717, UInt<1>("h00")) - node T_2814 = neq(T_2718, UInt<1>("h00")) - node T_2816 = neq(T_2719, UInt<1>("h00")) - node T_2818 = neq(T_2720, UInt<1>("h00")) - node T_2820 = neq(T_2721, UInt<1>("h00")) - node T_2822 = neq(T_2722, UInt<1>("h00")) - node T_2824 = neq(T_2723, UInt<1>("h00")) - node T_2826 = neq(T_2724, UInt<1>("h00")) - node T_2828 = neq(T_2725, UInt<1>("h00")) - node T_2830 = neq(T_2726, UInt<1>("h00")) - node T_2832 = neq(T_2727, UInt<1>("h00")) - node T_2834 = neq(T_2728, UInt<1>("h00")) - node T_2836 = neq(T_2729, UInt<1>("h00")) - node T_2838 = neq(T_2730, UInt<1>("h00")) - node T_2840 = neq(T_2731, UInt<1>("h00")) - node T_2842 = neq(T_2732, UInt<1>("h00")) - node T_2844 = neq(T_2733, UInt<1>("h00")) - node T_2846 = neq(T_2734, UInt<1>("h00")) - node T_2848 = neq(T_2735, UInt<1>("h00")) - node T_2850 = neq(T_2736, UInt<1>("h00")) - node T_2852 = neq(T_2737, UInt<1>("h00")) - node T_2854 = neq(T_2738, UInt<1>("h00")) - node T_2856 = neq(T_2739, UInt<1>("h00")) - node T_2858 = neq(T_2740, UInt<1>("h00")) - node T_2860 = neq(T_2741, UInt<1>("h00")) - node T_2862 = neq(T_2742, UInt<1>("h00")) - node T_2864 = neq(T_2743, UInt<1>("h00")) - node T_2866 = neq(T_2744, UInt<1>("h00")) - node T_2868 = neq(T_2745, UInt<1>("h00")) - node T_2870 = neq(T_2746, UInt<1>("h00")) - wire T_2872 : UInt<1>[62] - T_2872[0] := T_2748 - T_2872[1] := T_2750 - T_2872[2] := T_2752 - T_2872[3] := T_2754 - T_2872[4] := T_2756 - T_2872[5] := T_2758 - T_2872[6] := T_2760 - T_2872[7] := T_2762 - T_2872[8] := T_2764 - T_2872[9] := T_2766 - T_2872[10] := T_2768 - T_2872[11] := T_2770 - T_2872[12] := T_2772 - T_2872[13] := T_2774 - T_2872[14] := T_2776 - T_2872[15] := T_2778 - T_2872[16] := T_2780 - T_2872[17] := T_2782 - T_2872[18] := T_2784 - T_2872[19] := T_2786 - T_2872[20] := T_2788 - T_2872[21] := T_2790 - T_2872[22] := T_2792 - T_2872[23] := T_2794 - T_2872[24] := T_2796 - T_2872[25] := T_2798 - T_2872[26] := T_2800 - T_2872[27] := T_2802 - T_2872[28] := T_2804 - T_2872[29] := T_2806 - T_2872[30] := T_2808 - T_2872[31] := T_2810 - T_2872[32] := T_2812 - T_2872[33] := T_2814 - T_2872[34] := T_2816 - T_2872[35] := T_2818 - T_2872[36] := T_2820 - T_2872[37] := T_2822 - T_2872[38] := T_2824 - T_2872[39] := T_2826 - T_2872[40] := T_2828 - T_2872[41] := T_2830 - T_2872[42] := T_2832 - T_2872[43] := T_2834 - T_2872[44] := T_2836 - T_2872[45] := T_2838 - T_2872[46] := T_2840 - T_2872[47] := T_2842 - T_2872[48] := T_2844 - T_2872[49] := T_2846 - T_2872[50] := T_2848 - T_2872[51] := T_2850 - T_2872[52] := T_2852 - T_2872[53] := T_2854 - T_2872[54] := T_2856 - T_2872[55] := T_2858 - T_2872[56] := T_2860 - T_2872[57] := T_2862 - T_2872[58] := T_2864 - T_2872[59] := T_2866 - T_2872[60] := T_2868 - T_2872[61] := T_2870 - node T_2936 = cat(T_2872[60], T_2872[59]) - node T_2937 = cat(T_2872[61], T_2936) - node T_2938 = cat(T_2872[58], T_2872[57]) - node T_2939 = cat(T_2872[56], T_2872[55]) - node T_2940 = cat(T_2938, T_2939) - node T_2941 = cat(T_2937, T_2940) - node T_2942 = cat(T_2872[54], T_2872[53]) - node T_2943 = cat(T_2872[52], T_2872[51]) - node T_2944 = cat(T_2942, T_2943) - node T_2945 = cat(T_2872[50], T_2872[49]) - node T_2946 = cat(T_2872[48], T_2872[47]) - node T_2947 = cat(T_2945, T_2946) - node T_2948 = cat(T_2944, T_2947) - node T_2949 = cat(T_2941, T_2948) - node T_2950 = cat(T_2872[46], T_2872[45]) - node T_2951 = cat(T_2872[44], T_2872[43]) - node T_2952 = cat(T_2950, T_2951) - node T_2953 = cat(T_2872[42], T_2872[41]) - node T_2954 = cat(T_2872[40], T_2872[39]) - node T_2955 = cat(T_2953, T_2954) - node T_2956 = cat(T_2952, T_2955) - node T_2957 = cat(T_2872[38], T_2872[37]) - node T_2958 = cat(T_2872[36], T_2872[35]) - node T_2959 = cat(T_2957, T_2958) - node T_2960 = cat(T_2872[34], T_2872[33]) - node T_2961 = cat(T_2872[32], T_2872[31]) - node T_2962 = cat(T_2960, T_2961) - node T_2963 = cat(T_2959, T_2962) - node T_2964 = cat(T_2956, T_2963) - node T_2965 = cat(T_2949, T_2964) - node T_2966 = cat(T_2872[29], T_2872[28]) - node T_2967 = cat(T_2872[30], T_2966) - node T_2968 = cat(T_2872[27], T_2872[26]) - node T_2969 = cat(T_2872[25], T_2872[24]) - node T_2970 = cat(T_2968, T_2969) - node T_2971 = cat(T_2967, T_2970) - node T_2972 = cat(T_2872[23], T_2872[22]) - node T_2973 = cat(T_2872[21], T_2872[20]) - node T_2974 = cat(T_2972, T_2973) - node T_2975 = cat(T_2872[19], T_2872[18]) - node T_2976 = cat(T_2872[17], T_2872[16]) - node T_2977 = cat(T_2975, T_2976) - node T_2978 = cat(T_2974, T_2977) - node T_2979 = cat(T_2971, T_2978) - node T_2980 = cat(T_2872[15], T_2872[14]) - node T_2981 = cat(T_2872[13], T_2872[12]) - node T_2982 = cat(T_2980, T_2981) - node T_2983 = cat(T_2872[11], T_2872[10]) - node T_2984 = cat(T_2872[9], T_2872[8]) - node T_2985 = cat(T_2983, T_2984) - node T_2986 = cat(T_2982, T_2985) - node T_2987 = cat(T_2872[7], T_2872[6]) - node T_2988 = cat(T_2872[5], T_2872[4]) - node T_2989 = cat(T_2987, T_2988) - node T_2990 = cat(T_2872[3], T_2872[2]) - node T_2991 = cat(T_2872[1], T_2872[0]) - node T_2992 = cat(T_2990, T_2991) - node T_2993 = cat(T_2989, T_2992) - node T_2994 = cat(T_2986, T_2993) - node T_2995 = cat(T_2979, T_2994) - node T_2996 = cat(T_2965, T_2995) - node T_2997 = and(idxValid, T_2684) - node updateHits = and(T_2997, T_2996) - reg T_3000 : UInt<16>, clock, reset - onreset T_3000 := UInt<16>("h01") - when r_btb_update.valid : - node T_3001 = bit(T_3000, 0) - node T_3002 = bit(T_3000, 2) - node T_3003 = xor(T_3001, T_3002) - node T_3004 = bit(T_3000, 3) - node T_3005 = xor(T_3003, T_3004) - node T_3006 = bit(T_3000, 5) - node T_3007 = xor(T_3005, T_3006) - node T_3008 = bits(T_3000, 15, 1) - node T_3009 = cat(T_3007, T_3008) - T_3000 := T_3009 - skip - node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) - node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) - wire idxPageRepl : UInt<6> - idxPageRepl := UInt<1>("h00") - node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) - node T_3018 = bits(idxPageUpdateOH, 5, 4) - node T_3019 = bits(idxPageUpdateOH, 3, 0) - node T_3021 = neq(T_3018, UInt<1>("h00")) - node T_3022 = or(T_3018, T_3019) - node T_3023 = bits(T_3022, 3, 2) - node T_3024 = bits(T_3022, 1, 0) - node T_3026 = neq(T_3023, UInt<1>("h00")) - node T_3027 = or(T_3023, T_3024) - node T_3028 = bit(T_3027, 1) - node T_3029 = cat(T_3026, T_3028) - node idxPageUpdate = cat(T_3021, T_3029) - node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) - node T_3033 = shr(r_btb_update.bits.pc, 12) - node T_3034 = shr(req.bits.addr, 12) - node samePage = eq(T_3033, T_3034) - node T_3036 = not(idxPageReplEn) - node T_3037 = and(pageHit, T_3036) - node usePageHit = neq(T_3037, UInt<1>("h00")) - node T_3041 = eq(samePage, UInt<1>("h00")) - node T_3043 = eq(usePageHit, UInt<1>("h00")) - node doTgtPageRepl = and(T_3041, T_3043) - node T_3045 = bits(idxPageUpdateOH, 4, 0) - node T_3046 = shl(T_3045, 1) - node T_3047 = bit(idxPageUpdateOH, 5) - node T_3048 = or(T_3046, T_3047) - node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048) - node T_3050 = mux(usePageHit, pageHit, tgtPageRepl) - node T_3051 = bits(T_3050, 5, 4) - node T_3052 = bits(T_3050, 3, 0) - node T_3054 = neq(T_3051, UInt<1>("h00")) - node T_3055 = or(T_3051, T_3052) - node T_3056 = bits(T_3055, 3, 2) - node T_3057 = bits(T_3055, 1, 0) - node T_3059 = neq(T_3056, UInt<1>("h00")) - node T_3060 = or(T_3056, T_3057) - node T_3061 = bit(T_3060, 1) - node T_3062 = cat(T_3059, T_3061) - node tgtPageUpdate = cat(T_3054, T_3062) - node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) - node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) - node pageReplEn = or(idxPageReplEn, tgtPageReplEn) - node T_3068 = and(r_btb_update.valid, doPageRepl) - reg T_3070 : UInt<3>, clock, reset - onreset T_3070 := UInt<3>("h00") - when T_3068 : - node T_3072 = eq(T_3070, UInt<3>("h05")) - node T_3074 = and(UInt<1>("h01"), T_3072) - node T_3077 = addw(T_3070, UInt<1>("h01")) - node T_3078 = mux(T_3074, UInt<1>("h00"), T_3077) - T_3070 := T_3078 - skip - node T_3079 = and(T_3068, T_3072) - node T_3081 = dshl(UInt<1>("h01"), T_3070) - idxPageRepl := T_3081 - when r_btb_update.valid : - node T_3082 = eq(req.bits.addr, r_btb_update.bits.target) - node T_3084 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) - reg T_3086 : UInt<6>, clock, reset - onreset T_3086 := UInt<6>("h00") - when T_3084 : - node T_3088 = eq(T_3086, UInt<6>("h03d")) - node T_3090 = and(UInt<1>("h01"), T_3088) - node T_3093 = addw(T_3086, UInt<1>("h01")) - node T_3094 = mux(T_3090, UInt<1>("h00"), T_3093) - T_3086 := T_3094 - skip - node T_3095 = and(T_3084, T_3088) - node T_3096 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, T_3086) - node T_3097 = or(T_592, T_902) - node T_3098 = and(pageReplEn, T_3097) - node T_3100 = neq(T_3098, UInt<1>("h00")) - node T_3101 = or(T_597, T_907) - node T_3102 = and(pageReplEn, T_3101) - node T_3104 = neq(T_3102, UInt<1>("h00")) - node T_3105 = or(T_602, T_912) - node T_3106 = and(pageReplEn, T_3105) - node T_3108 = neq(T_3106, UInt<1>("h00")) - node T_3109 = or(T_607, T_917) - node T_3110 = and(pageReplEn, T_3109) - node T_3112 = neq(T_3110, UInt<1>("h00")) - node T_3113 = or(T_612, T_922) - node T_3114 = and(pageReplEn, T_3113) - node T_3116 = neq(T_3114, UInt<1>("h00")) - node T_3117 = or(T_617, T_927) - node T_3118 = and(pageReplEn, T_3117) - node T_3120 = neq(T_3118, UInt<1>("h00")) - node T_3121 = or(T_622, T_932) - node T_3122 = and(pageReplEn, T_3121) - node T_3124 = neq(T_3122, UInt<1>("h00")) - node T_3125 = or(T_627, T_937) - node T_3126 = and(pageReplEn, T_3125) - node T_3128 = neq(T_3126, UInt<1>("h00")) - node T_3129 = or(T_632, T_942) - node T_3130 = and(pageReplEn, T_3129) - node T_3132 = neq(T_3130, UInt<1>("h00")) - node T_3133 = or(T_637, T_947) - node T_3134 = and(pageReplEn, T_3133) - node T_3136 = neq(T_3134, UInt<1>("h00")) - node T_3137 = or(T_642, T_952) - node T_3138 = and(pageReplEn, T_3137) - node T_3140 = neq(T_3138, UInt<1>("h00")) - node T_3141 = or(T_647, T_957) - node T_3142 = and(pageReplEn, T_3141) - node T_3144 = neq(T_3142, UInt<1>("h00")) - node T_3145 = or(T_652, T_962) - node T_3146 = and(pageReplEn, T_3145) - node T_3148 = neq(T_3146, UInt<1>("h00")) - node T_3149 = or(T_657, T_967) - node T_3150 = and(pageReplEn, T_3149) - node T_3152 = neq(T_3150, UInt<1>("h00")) - node T_3153 = or(T_662, T_972) - node T_3154 = and(pageReplEn, T_3153) - node T_3156 = neq(T_3154, UInt<1>("h00")) - node T_3157 = or(T_667, T_977) - node T_3158 = and(pageReplEn, T_3157) - node T_3160 = neq(T_3158, UInt<1>("h00")) - node T_3161 = or(T_672, T_982) - node T_3162 = and(pageReplEn, T_3161) - node T_3164 = neq(T_3162, UInt<1>("h00")) - node T_3165 = or(T_677, T_987) - node T_3166 = and(pageReplEn, T_3165) - node T_3168 = neq(T_3166, UInt<1>("h00")) - node T_3169 = or(T_682, T_992) - node T_3170 = and(pageReplEn, T_3169) - node T_3172 = neq(T_3170, UInt<1>("h00")) - node T_3173 = or(T_687, T_997) - node T_3174 = and(pageReplEn, T_3173) - node T_3176 = neq(T_3174, UInt<1>("h00")) - node T_3177 = or(T_692, T_1002) - node T_3178 = and(pageReplEn, T_3177) - node T_3180 = neq(T_3178, UInt<1>("h00")) - node T_3181 = or(T_697, T_1007) - node T_3182 = and(pageReplEn, T_3181) - node T_3184 = neq(T_3182, UInt<1>("h00")) - node T_3185 = or(T_702, T_1012) - node T_3186 = and(pageReplEn, T_3185) - node T_3188 = neq(T_3186, UInt<1>("h00")) - node T_3189 = or(T_707, T_1017) - node T_3190 = and(pageReplEn, T_3189) - node T_3192 = neq(T_3190, UInt<1>("h00")) - node T_3193 = or(T_712, T_1022) - node T_3194 = and(pageReplEn, T_3193) - node T_3196 = neq(T_3194, UInt<1>("h00")) - node T_3197 = or(T_717, T_1027) - node T_3198 = and(pageReplEn, T_3197) - node T_3200 = neq(T_3198, UInt<1>("h00")) - node T_3201 = or(T_722, T_1032) - node T_3202 = and(pageReplEn, T_3201) - node T_3204 = neq(T_3202, UInt<1>("h00")) - node T_3205 = or(T_727, T_1037) - node T_3206 = and(pageReplEn, T_3205) - node T_3208 = neq(T_3206, UInt<1>("h00")) - node T_3209 = or(T_732, T_1042) - node T_3210 = and(pageReplEn, T_3209) - node T_3212 = neq(T_3210, UInt<1>("h00")) - node T_3213 = or(T_737, T_1047) - node T_3214 = and(pageReplEn, T_3213) - node T_3216 = neq(T_3214, UInt<1>("h00")) - node T_3217 = or(T_742, T_1052) - node T_3218 = and(pageReplEn, T_3217) - node T_3220 = neq(T_3218, UInt<1>("h00")) - node T_3221 = or(T_747, T_1057) - node T_3222 = and(pageReplEn, T_3221) - node T_3224 = neq(T_3222, UInt<1>("h00")) - node T_3225 = or(T_752, T_1062) - node T_3226 = and(pageReplEn, T_3225) - node T_3228 = neq(T_3226, UInt<1>("h00")) - node T_3229 = or(T_757, T_1067) - node T_3230 = and(pageReplEn, T_3229) - node T_3232 = neq(T_3230, UInt<1>("h00")) - node T_3233 = or(T_762, T_1072) - node T_3234 = and(pageReplEn, T_3233) - node T_3236 = neq(T_3234, UInt<1>("h00")) - node T_3237 = or(T_767, T_1077) - node T_3238 = and(pageReplEn, T_3237) - node T_3240 = neq(T_3238, UInt<1>("h00")) - node T_3241 = or(T_772, T_1082) - node T_3242 = and(pageReplEn, T_3241) - node T_3244 = neq(T_3242, UInt<1>("h00")) - node T_3245 = or(T_777, T_1087) - node T_3246 = and(pageReplEn, T_3245) - node T_3248 = neq(T_3246, UInt<1>("h00")) - node T_3249 = or(T_782, T_1092) - node T_3250 = and(pageReplEn, T_3249) - node T_3252 = neq(T_3250, UInt<1>("h00")) - node T_3253 = or(T_787, T_1097) - node T_3254 = and(pageReplEn, T_3253) - node T_3256 = neq(T_3254, UInt<1>("h00")) - node T_3257 = or(T_792, T_1102) - node T_3258 = and(pageReplEn, T_3257) - node T_3260 = neq(T_3258, UInt<1>("h00")) - node T_3261 = or(T_797, T_1107) - node T_3262 = and(pageReplEn, T_3261) - node T_3264 = neq(T_3262, UInt<1>("h00")) - node T_3265 = or(T_802, T_1112) - node T_3266 = and(pageReplEn, T_3265) - node T_3268 = neq(T_3266, UInt<1>("h00")) - node T_3269 = or(T_807, T_1117) - node T_3270 = and(pageReplEn, T_3269) - node T_3272 = neq(T_3270, UInt<1>("h00")) - node T_3273 = or(T_812, T_1122) - node T_3274 = and(pageReplEn, T_3273) - node T_3276 = neq(T_3274, UInt<1>("h00")) - node T_3277 = or(T_817, T_1127) - node T_3278 = and(pageReplEn, T_3277) - node T_3280 = neq(T_3278, UInt<1>("h00")) - node T_3281 = or(T_822, T_1132) - node T_3282 = and(pageReplEn, T_3281) - node T_3284 = neq(T_3282, UInt<1>("h00")) - node T_3285 = or(T_827, T_1137) - node T_3286 = and(pageReplEn, T_3285) - node T_3288 = neq(T_3286, UInt<1>("h00")) - node T_3289 = or(T_832, T_1142) - node T_3290 = and(pageReplEn, T_3289) - node T_3292 = neq(T_3290, UInt<1>("h00")) - node T_3293 = or(T_837, T_1147) - node T_3294 = and(pageReplEn, T_3293) - node T_3296 = neq(T_3294, UInt<1>("h00")) - node T_3297 = or(T_842, T_1152) - node T_3298 = and(pageReplEn, T_3297) - node T_3300 = neq(T_3298, UInt<1>("h00")) - node T_3301 = or(T_847, T_1157) - node T_3302 = and(pageReplEn, T_3301) - node T_3304 = neq(T_3302, UInt<1>("h00")) - node T_3305 = or(T_852, T_1162) - node T_3306 = and(pageReplEn, T_3305) - node T_3308 = neq(T_3306, UInt<1>("h00")) - node T_3309 = or(T_857, T_1167) - node T_3310 = and(pageReplEn, T_3309) - node T_3312 = neq(T_3310, UInt<1>("h00")) - node T_3313 = or(T_862, T_1172) - node T_3314 = and(pageReplEn, T_3313) - node T_3316 = neq(T_3314, UInt<1>("h00")) - node T_3317 = or(T_867, T_1177) - node T_3318 = and(pageReplEn, T_3317) - node T_3320 = neq(T_3318, UInt<1>("h00")) - node T_3321 = or(T_872, T_1182) - node T_3322 = and(pageReplEn, T_3321) - node T_3324 = neq(T_3322, UInt<1>("h00")) - node T_3325 = or(T_877, T_1187) - node T_3326 = and(pageReplEn, T_3325) - node T_3328 = neq(T_3326, UInt<1>("h00")) - node T_3329 = or(T_882, T_1192) - node T_3330 = and(pageReplEn, T_3329) - node T_3332 = neq(T_3330, UInt<1>("h00")) - node T_3333 = or(T_887, T_1197) - node T_3334 = and(pageReplEn, T_3333) - node T_3336 = neq(T_3334, UInt<1>("h00")) - node T_3337 = or(T_892, T_1202) - node T_3338 = and(pageReplEn, T_3337) - node T_3340 = neq(T_3338, UInt<1>("h00")) - node T_3341 = or(T_897, T_1207) - node T_3342 = and(pageReplEn, T_3341) - node T_3344 = neq(T_3342, UInt<1>("h00")) - wire T_3346 : UInt<1>[62] - T_3346[0] := T_3100 - T_3346[1] := T_3104 - T_3346[2] := T_3108 - T_3346[3] := T_3112 - T_3346[4] := T_3116 - T_3346[5] := T_3120 - T_3346[6] := T_3124 - T_3346[7] := T_3128 - T_3346[8] := T_3132 - T_3346[9] := T_3136 - T_3346[10] := T_3140 - T_3346[11] := T_3144 - T_3346[12] := T_3148 - T_3346[13] := T_3152 - T_3346[14] := T_3156 - T_3346[15] := T_3160 - T_3346[16] := T_3164 - T_3346[17] := T_3168 - T_3346[18] := T_3172 - T_3346[19] := T_3176 - T_3346[20] := T_3180 - T_3346[21] := T_3184 - T_3346[22] := T_3188 - T_3346[23] := T_3192 - T_3346[24] := T_3196 - T_3346[25] := T_3200 - T_3346[26] := T_3204 - T_3346[27] := T_3208 - T_3346[28] := T_3212 - T_3346[29] := T_3216 - T_3346[30] := T_3220 - T_3346[31] := T_3224 - T_3346[32] := T_3228 - T_3346[33] := T_3232 - T_3346[34] := T_3236 - T_3346[35] := T_3240 - T_3346[36] := T_3244 - T_3346[37] := T_3248 - T_3346[38] := T_3252 - T_3346[39] := T_3256 - T_3346[40] := T_3260 - T_3346[41] := T_3264 - T_3346[42] := T_3268 - T_3346[43] := T_3272 - T_3346[44] := T_3276 - T_3346[45] := T_3280 - T_3346[46] := T_3284 - T_3346[47] := T_3288 - T_3346[48] := T_3292 - T_3346[49] := T_3296 - T_3346[50] := T_3300 - T_3346[51] := T_3304 - T_3346[52] := T_3308 - T_3346[53] := T_3312 - T_3346[54] := T_3316 - T_3346[55] := T_3320 - T_3346[56] := T_3324 - T_3346[57] := T_3328 - T_3346[58] := T_3332 - T_3346[59] := T_3336 - T_3346[60] := T_3340 - T_3346[61] := T_3344 - node T_3410 = cat(T_3346[60], T_3346[59]) - node T_3411 = cat(T_3346[61], T_3410) - node T_3412 = cat(T_3346[58], T_3346[57]) - node T_3413 = cat(T_3346[56], T_3346[55]) - node T_3414 = cat(T_3412, T_3413) - node T_3415 = cat(T_3411, T_3414) - node T_3416 = cat(T_3346[54], T_3346[53]) - node T_3417 = cat(T_3346[52], T_3346[51]) - node T_3418 = cat(T_3416, T_3417) - node T_3419 = cat(T_3346[50], T_3346[49]) - node T_3420 = cat(T_3346[48], T_3346[47]) - node T_3421 = cat(T_3419, T_3420) - node T_3422 = cat(T_3418, T_3421) - node T_3423 = cat(T_3415, T_3422) - node T_3424 = cat(T_3346[46], T_3346[45]) - node T_3425 = cat(T_3346[44], T_3346[43]) - node T_3426 = cat(T_3424, T_3425) - node T_3427 = cat(T_3346[42], T_3346[41]) - node T_3428 = cat(T_3346[40], T_3346[39]) - node T_3429 = cat(T_3427, T_3428) - node T_3430 = cat(T_3426, T_3429) - node T_3431 = cat(T_3346[38], T_3346[37]) - node T_3432 = cat(T_3346[36], T_3346[35]) - node T_3433 = cat(T_3431, T_3432) - node T_3434 = cat(T_3346[34], T_3346[33]) - node T_3435 = cat(T_3346[32], T_3346[31]) - node T_3436 = cat(T_3434, T_3435) - node T_3437 = cat(T_3433, T_3436) - node T_3438 = cat(T_3430, T_3437) - node T_3439 = cat(T_3423, T_3438) - node T_3440 = cat(T_3346[29], T_3346[28]) - node T_3441 = cat(T_3346[30], T_3440) - node T_3442 = cat(T_3346[27], T_3346[26]) - node T_3443 = cat(T_3346[25], T_3346[24]) - node T_3444 = cat(T_3442, T_3443) - node T_3445 = cat(T_3441, T_3444) - node T_3446 = cat(T_3346[23], T_3346[22]) - node T_3447 = cat(T_3346[21], T_3346[20]) - node T_3448 = cat(T_3446, T_3447) - node T_3449 = cat(T_3346[19], T_3346[18]) - node T_3450 = cat(T_3346[17], T_3346[16]) - node T_3451 = cat(T_3449, T_3450) - node T_3452 = cat(T_3448, T_3451) - node T_3453 = cat(T_3445, T_3452) - node T_3454 = cat(T_3346[15], T_3346[14]) - node T_3455 = cat(T_3346[13], T_3346[12]) - node T_3456 = cat(T_3454, T_3455) - node T_3457 = cat(T_3346[11], T_3346[10]) - node T_3458 = cat(T_3346[9], T_3346[8]) - node T_3459 = cat(T_3457, T_3458) - node T_3460 = cat(T_3456, T_3459) - node T_3461 = cat(T_3346[7], T_3346[6]) - node T_3462 = cat(T_3346[5], T_3346[4]) - node T_3463 = cat(T_3461, T_3462) - node T_3464 = cat(T_3346[3], T_3346[2]) - node T_3465 = cat(T_3346[1], T_3346[0]) - node T_3466 = cat(T_3464, T_3465) - node T_3467 = cat(T_3463, T_3466) - node T_3468 = cat(T_3460, T_3467) - node T_3469 = cat(T_3453, T_3468) - node T_3470 = cat(T_3439, T_3469) - node T_3472 = dshl(UInt<1>("h01"), T_3096) - node T_3473 = not(T_3470) - node T_3474 = and(idxValid, T_3473) - node T_3475 = or(T_3474, T_3472) - idxValid := T_3475 - infer accessor T_3476 = idxs[T_3096] - T_3476 := r_btb_update.bits.pc - infer accessor T_3477 = tgts[T_3096] - T_3477 := req.bits.addr - infer accessor T_3478 = idxPages[T_3096] - T_3478 := idxPageUpdate - infer accessor T_3479 = tgtPages[T_3096] - T_3479 := tgtPageUpdate - infer accessor T_3480 = useRAS[T_3096] - T_3480 := r_btb_update.bits.isReturn - infer accessor T_3481 = isJump[T_3096] - T_3481 := r_btb_update.bits.isJump - infer accessor T_3482 = brIdx[T_3096] - T_3482 := UInt<1>("h00") - node T_3485 = cat(UInt<2>("h01"), UInt<2>("h01")) - node T_3486 = cat(UInt<2>("h01"), T_3485) - node T_3487 = and(idxPageUpdateOH, T_3486) - node T_3489 = neq(T_3487, UInt<1>("h00")) - node T_3490 = mux(T_3489, doIdxPageRepl, doTgtPageRepl) - node T_3491 = shr(r_btb_update.bits.pc, 12) - node T_3492 = shr(req.bits.addr, 12) - node T_3493 = mux(T_3489, T_3491, T_3492) - node T_3494 = bit(pageReplEn, 0) - node T_3495 = and(T_3490, T_3494) - when T_3495 : - infer accessor T_3497 = pages[UInt<1>("h00")] - T_3497 := T_3493 - skip - node T_3498 = bit(pageReplEn, 2) - node T_3499 = and(T_3490, T_3498) - when T_3499 : - infer accessor T_3501 = pages[UInt<2>("h02")] - T_3501 := T_3493 - skip - node T_3502 = bit(pageReplEn, 4) - node T_3503 = and(T_3490, T_3502) - when T_3503 : - infer accessor T_3505 = pages[UInt<3>("h04")] - T_3505 := T_3493 - skip - node T_3506 = mux(T_3489, doTgtPageRepl, doIdxPageRepl) - node T_3507 = shr(req.bits.addr, 12) - node T_3508 = shr(r_btb_update.bits.pc, 12) - node T_3509 = mux(T_3489, T_3507, T_3508) - node T_3510 = bit(pageReplEn, 1) - node T_3511 = and(T_3506, T_3510) - when T_3511 : - infer accessor T_3513 = pages[UInt<1>("h01")] - T_3513 := T_3509 - skip - node T_3514 = bit(pageReplEn, 3) - node T_3515 = and(T_3506, T_3514) - when T_3515 : - infer accessor T_3517 = pages[UInt<2>("h03")] - T_3517 := T_3509 - skip - node T_3518 = bit(pageReplEn, 5) - node T_3519 = and(T_3506, T_3518) - when T_3519 : - infer accessor T_3521 = pages[UInt<3>("h05")] - T_3521 := T_3509 - skip - when doPageRepl : - node T_3522 = or(pageValid, pageReplEn) - pageValid := T_3522 - skip - skip - when invalidate : - idxValid := UInt<1>("h00") - pageValid := UInt<1>("h00") - skip - node T_3526 = neq(hits, UInt<1>("h00")) - resp.valid := T_3526 - resp.bits.taken := resp.valid - node T_3527 = bit(hits, 0) - node T_3528 = bit(hits, 1) - node T_3529 = bit(hits, 2) - node T_3530 = bit(hits, 3) - node T_3531 = bit(hits, 4) - node T_3532 = bit(hits, 5) - node T_3533 = bit(hits, 6) - node T_3534 = bit(hits, 7) - node T_3535 = bit(hits, 8) - node T_3536 = bit(hits, 9) - node T_3537 = bit(hits, 10) - node T_3538 = bit(hits, 11) - node T_3539 = bit(hits, 12) - node T_3540 = bit(hits, 13) - node T_3541 = bit(hits, 14) - node T_3542 = bit(hits, 15) - node T_3543 = bit(hits, 16) - node T_3544 = bit(hits, 17) - node T_3545 = bit(hits, 18) - node T_3546 = bit(hits, 19) - node T_3547 = bit(hits, 20) - node T_3548 = bit(hits, 21) - node T_3549 = bit(hits, 22) - node T_3550 = bit(hits, 23) - node T_3551 = bit(hits, 24) - node T_3552 = bit(hits, 25) - node T_3553 = bit(hits, 26) - node T_3554 = bit(hits, 27) - node T_3555 = bit(hits, 28) - node T_3556 = bit(hits, 29) - node T_3557 = bit(hits, 30) - node T_3558 = bit(hits, 31) - node T_3559 = bit(hits, 32) - node T_3560 = bit(hits, 33) - node T_3561 = bit(hits, 34) - node T_3562 = bit(hits, 35) - node T_3563 = bit(hits, 36) - node T_3564 = bit(hits, 37) - node T_3565 = bit(hits, 38) - node T_3566 = bit(hits, 39) - node T_3567 = bit(hits, 40) - node T_3568 = bit(hits, 41) - node T_3569 = bit(hits, 42) - node T_3570 = bit(hits, 43) - node T_3571 = bit(hits, 44) - node T_3572 = bit(hits, 45) - node T_3573 = bit(hits, 46) - node T_3574 = bit(hits, 47) - node T_3575 = bit(hits, 48) - node T_3576 = bit(hits, 49) - node T_3577 = bit(hits, 50) - node T_3578 = bit(hits, 51) - node T_3579 = bit(hits, 52) - node T_3580 = bit(hits, 53) - node T_3581 = bit(hits, 54) - node T_3582 = bit(hits, 55) - node T_3583 = bit(hits, 56) - node T_3584 = bit(hits, 57) - node T_3585 = bit(hits, 58) - node T_3586 = bit(hits, 59) - node T_3587 = bit(hits, 60) - node T_3588 = bit(hits, 61) - node T_3590 = mux(T_3527, T_902, UInt<1>("h00")) - node T_3592 = mux(T_3528, T_907, UInt<1>("h00")) - node T_3594 = mux(T_3529, T_912, UInt<1>("h00")) - node T_3596 = mux(T_3530, T_917, UInt<1>("h00")) - node T_3598 = mux(T_3531, T_922, UInt<1>("h00")) - node T_3600 = mux(T_3532, T_927, UInt<1>("h00")) - node T_3602 = mux(T_3533, T_932, UInt<1>("h00")) - node T_3604 = mux(T_3534, T_937, UInt<1>("h00")) - node T_3606 = mux(T_3535, T_942, UInt<1>("h00")) - node T_3608 = mux(T_3536, T_947, UInt<1>("h00")) - node T_3610 = mux(T_3537, T_952, UInt<1>("h00")) - node T_3612 = mux(T_3538, T_957, UInt<1>("h00")) - node T_3614 = mux(T_3539, T_962, UInt<1>("h00")) - node T_3616 = mux(T_3540, T_967, UInt<1>("h00")) - node T_3618 = mux(T_3541, T_972, UInt<1>("h00")) - node T_3620 = mux(T_3542, T_977, UInt<1>("h00")) - node T_3622 = mux(T_3543, T_982, UInt<1>("h00")) - node T_3624 = mux(T_3544, T_987, UInt<1>("h00")) - node T_3626 = mux(T_3545, T_992, UInt<1>("h00")) - node T_3628 = mux(T_3546, T_997, UInt<1>("h00")) - node T_3630 = mux(T_3547, T_1002, UInt<1>("h00")) - node T_3632 = mux(T_3548, T_1007, UInt<1>("h00")) - node T_3634 = mux(T_3549, T_1012, UInt<1>("h00")) - node T_3636 = mux(T_3550, T_1017, UInt<1>("h00")) - node T_3638 = mux(T_3551, T_1022, UInt<1>("h00")) - node T_3640 = mux(T_3552, T_1027, UInt<1>("h00")) - node T_3642 = mux(T_3553, T_1032, UInt<1>("h00")) - node T_3644 = mux(T_3554, T_1037, UInt<1>("h00")) - node T_3646 = mux(T_3555, T_1042, UInt<1>("h00")) - node T_3648 = mux(T_3556, T_1047, UInt<1>("h00")) - node T_3650 = mux(T_3557, T_1052, UInt<1>("h00")) - node T_3652 = mux(T_3558, T_1057, UInt<1>("h00")) - node T_3654 = mux(T_3559, T_1062, UInt<1>("h00")) - node T_3656 = mux(T_3560, T_1067, UInt<1>("h00")) - node T_3658 = mux(T_3561, T_1072, UInt<1>("h00")) - node T_3660 = mux(T_3562, T_1077, UInt<1>("h00")) - node T_3662 = mux(T_3563, T_1082, UInt<1>("h00")) - node T_3664 = mux(T_3564, T_1087, UInt<1>("h00")) - node T_3666 = mux(T_3565, T_1092, UInt<1>("h00")) - node T_3668 = mux(T_3566, T_1097, UInt<1>("h00")) - node T_3670 = mux(T_3567, T_1102, UInt<1>("h00")) - node T_3672 = mux(T_3568, T_1107, UInt<1>("h00")) - node T_3674 = mux(T_3569, T_1112, UInt<1>("h00")) - node T_3676 = mux(T_3570, T_1117, UInt<1>("h00")) - node T_3678 = mux(T_3571, T_1122, UInt<1>("h00")) - node T_3680 = mux(T_3572, T_1127, UInt<1>("h00")) - node T_3682 = mux(T_3573, T_1132, UInt<1>("h00")) - node T_3684 = mux(T_3574, T_1137, UInt<1>("h00")) - node T_3686 = mux(T_3575, T_1142, UInt<1>("h00")) - node T_3688 = mux(T_3576, T_1147, UInt<1>("h00")) - node T_3690 = mux(T_3577, T_1152, UInt<1>("h00")) - node T_3692 = mux(T_3578, T_1157, UInt<1>("h00")) - node T_3694 = mux(T_3579, T_1162, UInt<1>("h00")) - node T_3696 = mux(T_3580, T_1167, UInt<1>("h00")) - node T_3698 = mux(T_3581, T_1172, UInt<1>("h00")) - node T_3700 = mux(T_3582, T_1177, UInt<1>("h00")) - node T_3702 = mux(T_3583, T_1182, UInt<1>("h00")) - node T_3704 = mux(T_3584, T_1187, UInt<1>("h00")) - node T_3706 = mux(T_3585, T_1192, UInt<1>("h00")) - node T_3708 = mux(T_3586, T_1197, UInt<1>("h00")) - node T_3710 = mux(T_3587, T_1202, UInt<1>("h00")) - node T_3712 = mux(T_3588, T_1207, UInt<1>("h00")) - node T_3714 = or(T_3590, T_3592) - node T_3715 = or(T_3714, T_3594) - node T_3716 = or(T_3715, T_3596) - node T_3717 = or(T_3716, T_3598) - node T_3718 = or(T_3717, T_3600) - node T_3719 = or(T_3718, T_3602) - node T_3720 = or(T_3719, T_3604) - node T_3721 = or(T_3720, T_3606) - node T_3722 = or(T_3721, T_3608) - node T_3723 = or(T_3722, T_3610) - node T_3724 = or(T_3723, T_3612) - node T_3725 = or(T_3724, T_3614) - node T_3726 = or(T_3725, T_3616) - node T_3727 = or(T_3726, T_3618) - node T_3728 = or(T_3727, T_3620) - node T_3729 = or(T_3728, T_3622) - node T_3730 = or(T_3729, T_3624) - node T_3731 = or(T_3730, T_3626) - node T_3732 = or(T_3731, T_3628) - node T_3733 = or(T_3732, T_3630) - node T_3734 = or(T_3733, T_3632) - node T_3735 = or(T_3734, T_3634) - node T_3736 = or(T_3735, T_3636) - node T_3737 = or(T_3736, T_3638) - node T_3738 = or(T_3737, T_3640) - node T_3739 = or(T_3738, T_3642) - node T_3740 = or(T_3739, T_3644) - node T_3741 = or(T_3740, T_3646) - node T_3742 = or(T_3741, T_3648) - node T_3743 = or(T_3742, T_3650) - node T_3744 = or(T_3743, T_3652) - node T_3745 = or(T_3744, T_3654) - node T_3746 = or(T_3745, T_3656) - node T_3747 = or(T_3746, T_3658) - node T_3748 = or(T_3747, T_3660) - node T_3749 = or(T_3748, T_3662) - node T_3750 = or(T_3749, T_3664) - node T_3751 = or(T_3750, T_3666) - node T_3752 = or(T_3751, T_3668) - node T_3753 = or(T_3752, T_3670) - node T_3754 = or(T_3753, T_3672) - node T_3755 = or(T_3754, T_3674) - node T_3756 = or(T_3755, T_3676) - node T_3757 = or(T_3756, T_3678) - node T_3758 = or(T_3757, T_3680) - node T_3759 = or(T_3758, T_3682) - node T_3760 = or(T_3759, T_3684) - node T_3761 = or(T_3760, T_3686) - node T_3762 = or(T_3761, T_3688) - node T_3763 = or(T_3762, T_3690) - node T_3764 = or(T_3763, T_3692) - node T_3765 = or(T_3764, T_3694) - node T_3766 = or(T_3765, T_3696) - node T_3767 = or(T_3766, T_3698) - node T_3768 = or(T_3767, T_3700) - node T_3769 = or(T_3768, T_3702) - node T_3770 = or(T_3769, T_3704) - node T_3771 = or(T_3770, T_3706) - node T_3772 = or(T_3771, T_3708) - node T_3773 = or(T_3772, T_3710) - node T_3774 = or(T_3773, T_3712) - wire T_3775 : UInt<6> - T_3775 := UInt<1>("h00") - T_3775 := T_3774 - node T_3777 = bit(T_3775, 0) - node T_3778 = bit(T_3775, 1) - node T_3779 = bit(T_3775, 2) - node T_3780 = bit(T_3775, 3) - node T_3781 = bit(T_3775, 4) - node T_3782 = bit(T_3775, 5) - infer accessor T_3784 = pages[UInt<1>("h00")] - infer accessor T_3786 = pages[UInt<1>("h01")] - infer accessor T_3788 = pages[UInt<2>("h02")] - infer accessor T_3790 = pages[UInt<2>("h03")] - infer accessor T_3792 = pages[UInt<3>("h04")] - infer accessor T_3794 = pages[UInt<3>("h05")] - node T_3796 = mux(T_3777, T_3784, UInt<1>("h00")) - node T_3798 = mux(T_3778, T_3786, UInt<1>("h00")) - node T_3800 = mux(T_3779, T_3788, UInt<1>("h00")) - node T_3802 = mux(T_3780, T_3790, UInt<1>("h00")) - node T_3804 = mux(T_3781, T_3792, UInt<1>("h00")) - node T_3806 = mux(T_3782, T_3794, UInt<1>("h00")) - node T_3808 = or(T_3796, T_3798) - node T_3809 = or(T_3808, T_3800) - node T_3810 = or(T_3809, T_3802) - node T_3811 = or(T_3810, T_3804) - node T_3812 = or(T_3811, T_3806) - wire T_3813 : UInt<27> - T_3813 := UInt<1>("h00") - T_3813 := T_3812 - node T_3815 = bit(hits, 0) - node T_3816 = bit(hits, 1) - node T_3817 = bit(hits, 2) - node T_3818 = bit(hits, 3) - node T_3819 = bit(hits, 4) - node T_3820 = bit(hits, 5) - node T_3821 = bit(hits, 6) - node T_3822 = bit(hits, 7) - node T_3823 = bit(hits, 8) - node T_3824 = bit(hits, 9) - node T_3825 = bit(hits, 10) - node T_3826 = bit(hits, 11) - node T_3827 = bit(hits, 12) - node T_3828 = bit(hits, 13) - node T_3829 = bit(hits, 14) - node T_3830 = bit(hits, 15) - node T_3831 = bit(hits, 16) - node T_3832 = bit(hits, 17) - node T_3833 = bit(hits, 18) - node T_3834 = bit(hits, 19) - node T_3835 = bit(hits, 20) - node T_3836 = bit(hits, 21) - node T_3837 = bit(hits, 22) - node T_3838 = bit(hits, 23) - node T_3839 = bit(hits, 24) - node T_3840 = bit(hits, 25) - node T_3841 = bit(hits, 26) - node T_3842 = bit(hits, 27) - node T_3843 = bit(hits, 28) - node T_3844 = bit(hits, 29) - node T_3845 = bit(hits, 30) - node T_3846 = bit(hits, 31) - node T_3847 = bit(hits, 32) - node T_3848 = bit(hits, 33) - node T_3849 = bit(hits, 34) - node T_3850 = bit(hits, 35) - node T_3851 = bit(hits, 36) - node T_3852 = bit(hits, 37) - node T_3853 = bit(hits, 38) - node T_3854 = bit(hits, 39) - node T_3855 = bit(hits, 40) - node T_3856 = bit(hits, 41) - node T_3857 = bit(hits, 42) - node T_3858 = bit(hits, 43) - node T_3859 = bit(hits, 44) - node T_3860 = bit(hits, 45) - node T_3861 = bit(hits, 46) - node T_3862 = bit(hits, 47) - node T_3863 = bit(hits, 48) - node T_3864 = bit(hits, 49) - node T_3865 = bit(hits, 50) - node T_3866 = bit(hits, 51) - node T_3867 = bit(hits, 52) - node T_3868 = bit(hits, 53) - node T_3869 = bit(hits, 54) - node T_3870 = bit(hits, 55) - node T_3871 = bit(hits, 56) - node T_3872 = bit(hits, 57) - node T_3873 = bit(hits, 58) - node T_3874 = bit(hits, 59) - node T_3875 = bit(hits, 60) - node T_3876 = bit(hits, 61) - infer accessor T_3878 = tgts[UInt<1>("h00")] - infer accessor T_3880 = tgts[UInt<1>("h01")] - infer accessor T_3882 = tgts[UInt<2>("h02")] - infer accessor T_3884 = tgts[UInt<2>("h03")] - infer accessor T_3886 = tgts[UInt<3>("h04")] - infer accessor T_3888 = tgts[UInt<3>("h05")] - infer accessor T_3890 = tgts[UInt<3>("h06")] - infer accessor T_3892 = tgts[UInt<3>("h07")] - infer accessor T_3894 = tgts[UInt<4>("h08")] - infer accessor T_3896 = tgts[UInt<4>("h09")] - infer accessor T_3898 = tgts[UInt<4>("h0a")] - infer accessor T_3900 = tgts[UInt<4>("h0b")] - infer accessor T_3902 = tgts[UInt<4>("h0c")] - infer accessor T_3904 = tgts[UInt<4>("h0d")] - infer accessor T_3906 = tgts[UInt<4>("h0e")] - infer accessor T_3908 = tgts[UInt<4>("h0f")] - infer accessor T_3910 = tgts[UInt<5>("h010")] - infer accessor T_3912 = tgts[UInt<5>("h011")] - infer accessor T_3914 = tgts[UInt<5>("h012")] - infer accessor T_3916 = tgts[UInt<5>("h013")] - infer accessor T_3918 = tgts[UInt<5>("h014")] - infer accessor T_3920 = tgts[UInt<5>("h015")] - infer accessor T_3922 = tgts[UInt<5>("h016")] - infer accessor T_3924 = tgts[UInt<5>("h017")] - infer accessor T_3926 = tgts[UInt<5>("h018")] - infer accessor T_3928 = tgts[UInt<5>("h019")] - infer accessor T_3930 = tgts[UInt<5>("h01a")] - infer accessor T_3932 = tgts[UInt<5>("h01b")] - infer accessor T_3934 = tgts[UInt<5>("h01c")] - infer accessor T_3936 = tgts[UInt<5>("h01d")] - infer accessor T_3938 = tgts[UInt<5>("h01e")] - infer accessor T_3940 = tgts[UInt<5>("h01f")] - infer accessor T_3942 = tgts[UInt<6>("h020")] - infer accessor T_3944 = tgts[UInt<6>("h021")] - infer accessor T_3946 = tgts[UInt<6>("h022")] - infer accessor T_3948 = tgts[UInt<6>("h023")] - infer accessor T_3950 = tgts[UInt<6>("h024")] - infer accessor T_3952 = tgts[UInt<6>("h025")] - infer accessor T_3954 = tgts[UInt<6>("h026")] - infer accessor T_3956 = tgts[UInt<6>("h027")] - infer accessor T_3958 = tgts[UInt<6>("h028")] - infer accessor T_3960 = tgts[UInt<6>("h029")] - infer accessor T_3962 = tgts[UInt<6>("h02a")] - infer accessor T_3964 = tgts[UInt<6>("h02b")] - infer accessor T_3966 = tgts[UInt<6>("h02c")] - infer accessor T_3968 = tgts[UInt<6>("h02d")] - infer accessor T_3970 = tgts[UInt<6>("h02e")] - infer accessor T_3972 = tgts[UInt<6>("h02f")] - infer accessor T_3974 = tgts[UInt<6>("h030")] - infer accessor T_3976 = tgts[UInt<6>("h031")] - infer accessor T_3978 = tgts[UInt<6>("h032")] - infer accessor T_3980 = tgts[UInt<6>("h033")] - infer accessor T_3982 = tgts[UInt<6>("h034")] - infer accessor T_3984 = tgts[UInt<6>("h035")] - infer accessor T_3986 = tgts[UInt<6>("h036")] - infer accessor T_3988 = tgts[UInt<6>("h037")] - infer accessor T_3990 = tgts[UInt<6>("h038")] - infer accessor T_3992 = tgts[UInt<6>("h039")] - infer accessor T_3994 = tgts[UInt<6>("h03a")] - infer accessor T_3996 = tgts[UInt<6>("h03b")] - infer accessor T_3998 = tgts[UInt<6>("h03c")] - infer accessor T_4000 = tgts[UInt<6>("h03d")] - node T_4002 = mux(T_3815, T_3878, UInt<1>("h00")) - node T_4004 = mux(T_3816, T_3880, UInt<1>("h00")) - node T_4006 = mux(T_3817, T_3882, UInt<1>("h00")) - node T_4008 = mux(T_3818, T_3884, UInt<1>("h00")) - node T_4010 = mux(T_3819, T_3886, UInt<1>("h00")) - node T_4012 = mux(T_3820, T_3888, UInt<1>("h00")) - node T_4014 = mux(T_3821, T_3890, UInt<1>("h00")) - node T_4016 = mux(T_3822, T_3892, UInt<1>("h00")) - node T_4018 = mux(T_3823, T_3894, UInt<1>("h00")) - node T_4020 = mux(T_3824, T_3896, UInt<1>("h00")) - node T_4022 = mux(T_3825, T_3898, UInt<1>("h00")) - node T_4024 = mux(T_3826, T_3900, UInt<1>("h00")) - node T_4026 = mux(T_3827, T_3902, UInt<1>("h00")) - node T_4028 = mux(T_3828, T_3904, UInt<1>("h00")) - node T_4030 = mux(T_3829, T_3906, UInt<1>("h00")) - node T_4032 = mux(T_3830, T_3908, UInt<1>("h00")) - node T_4034 = mux(T_3831, T_3910, UInt<1>("h00")) - node T_4036 = mux(T_3832, T_3912, UInt<1>("h00")) - node T_4038 = mux(T_3833, T_3914, UInt<1>("h00")) - node T_4040 = mux(T_3834, T_3916, UInt<1>("h00")) - node T_4042 = mux(T_3835, T_3918, UInt<1>("h00")) - node T_4044 = mux(T_3836, T_3920, UInt<1>("h00")) - node T_4046 = mux(T_3837, T_3922, UInt<1>("h00")) - node T_4048 = mux(T_3838, T_3924, UInt<1>("h00")) - node T_4050 = mux(T_3839, T_3926, UInt<1>("h00")) - node T_4052 = mux(T_3840, T_3928, UInt<1>("h00")) - node T_4054 = mux(T_3841, T_3930, UInt<1>("h00")) - node T_4056 = mux(T_3842, T_3932, UInt<1>("h00")) - node T_4058 = mux(T_3843, T_3934, UInt<1>("h00")) - node T_4060 = mux(T_3844, T_3936, UInt<1>("h00")) - node T_4062 = mux(T_3845, T_3938, UInt<1>("h00")) - node T_4064 = mux(T_3846, T_3940, UInt<1>("h00")) - node T_4066 = mux(T_3847, T_3942, UInt<1>("h00")) - node T_4068 = mux(T_3848, T_3944, UInt<1>("h00")) - node T_4070 = mux(T_3849, T_3946, UInt<1>("h00")) - node T_4072 = mux(T_3850, T_3948, UInt<1>("h00")) - node T_4074 = mux(T_3851, T_3950, UInt<1>("h00")) - node T_4076 = mux(T_3852, T_3952, UInt<1>("h00")) - node T_4078 = mux(T_3853, T_3954, UInt<1>("h00")) - node T_4080 = mux(T_3854, T_3956, UInt<1>("h00")) - node T_4082 = mux(T_3855, T_3958, UInt<1>("h00")) - node T_4084 = mux(T_3856, T_3960, UInt<1>("h00")) - node T_4086 = mux(T_3857, T_3962, UInt<1>("h00")) - node T_4088 = mux(T_3858, T_3964, UInt<1>("h00")) - node T_4090 = mux(T_3859, T_3966, UInt<1>("h00")) - node T_4092 = mux(T_3860, T_3968, UInt<1>("h00")) - node T_4094 = mux(T_3861, T_3970, UInt<1>("h00")) - node T_4096 = mux(T_3862, T_3972, UInt<1>("h00")) - node T_4098 = mux(T_3863, T_3974, UInt<1>("h00")) - node T_4100 = mux(T_3864, T_3976, UInt<1>("h00")) - node T_4102 = mux(T_3865, T_3978, UInt<1>("h00")) - node T_4104 = mux(T_3866, T_3980, UInt<1>("h00")) - node T_4106 = mux(T_3867, T_3982, UInt<1>("h00")) - node T_4108 = mux(T_3868, T_3984, UInt<1>("h00")) - node T_4110 = mux(T_3869, T_3986, UInt<1>("h00")) - node T_4112 = mux(T_3870, T_3988, UInt<1>("h00")) - node T_4114 = mux(T_3871, T_3990, UInt<1>("h00")) - node T_4116 = mux(T_3872, T_3992, UInt<1>("h00")) - node T_4118 = mux(T_3873, T_3994, UInt<1>("h00")) - node T_4120 = mux(T_3874, T_3996, UInt<1>("h00")) - node T_4122 = mux(T_3875, T_3998, UInt<1>("h00")) - node T_4124 = mux(T_3876, T_4000, UInt<1>("h00")) - node T_4126 = or(T_4002, T_4004) - node T_4127 = or(T_4126, T_4006) - node T_4128 = or(T_4127, T_4008) - node T_4129 = or(T_4128, T_4010) - node T_4130 = or(T_4129, T_4012) - node T_4131 = or(T_4130, T_4014) - node T_4132 = or(T_4131, T_4016) - node T_4133 = or(T_4132, T_4018) - node T_4134 = or(T_4133, T_4020) - node T_4135 = or(T_4134, T_4022) - node T_4136 = or(T_4135, T_4024) - node T_4137 = or(T_4136, T_4026) - node T_4138 = or(T_4137, T_4028) - node T_4139 = or(T_4138, T_4030) - node T_4140 = or(T_4139, T_4032) - node T_4141 = or(T_4140, T_4034) - node T_4142 = or(T_4141, T_4036) - node T_4143 = or(T_4142, T_4038) - node T_4144 = or(T_4143, T_4040) - node T_4145 = or(T_4144, T_4042) - node T_4146 = or(T_4145, T_4044) - node T_4147 = or(T_4146, T_4046) - node T_4148 = or(T_4147, T_4048) - node T_4149 = or(T_4148, T_4050) - node T_4150 = or(T_4149, T_4052) - node T_4151 = or(T_4150, T_4054) - node T_4152 = or(T_4151, T_4056) - node T_4153 = or(T_4152, T_4058) - node T_4154 = or(T_4153, T_4060) - node T_4155 = or(T_4154, T_4062) - node T_4156 = or(T_4155, T_4064) - node T_4157 = or(T_4156, T_4066) - node T_4158 = or(T_4157, T_4068) - node T_4159 = or(T_4158, T_4070) - node T_4160 = or(T_4159, T_4072) - node T_4161 = or(T_4160, T_4074) - node T_4162 = or(T_4161, T_4076) - node T_4163 = or(T_4162, T_4078) - node T_4164 = or(T_4163, T_4080) - node T_4165 = or(T_4164, T_4082) - node T_4166 = or(T_4165, T_4084) - node T_4167 = or(T_4166, T_4086) - node T_4168 = or(T_4167, T_4088) - node T_4169 = or(T_4168, T_4090) - node T_4170 = or(T_4169, T_4092) - node T_4171 = or(T_4170, T_4094) - node T_4172 = or(T_4171, T_4096) - node T_4173 = or(T_4172, T_4098) - node T_4174 = or(T_4173, T_4100) - node T_4175 = or(T_4174, T_4102) - node T_4176 = or(T_4175, T_4104) - node T_4177 = or(T_4176, T_4106) - node T_4178 = or(T_4177, T_4108) - node T_4179 = or(T_4178, T_4110) - node T_4180 = or(T_4179, T_4112) - node T_4181 = or(T_4180, T_4114) - node T_4182 = or(T_4181, T_4116) - node T_4183 = or(T_4182, T_4118) - node T_4184 = or(T_4183, T_4120) - node T_4185 = or(T_4184, T_4122) - node T_4186 = or(T_4185, T_4124) - wire T_4187 : UInt<12> - T_4187 := UInt<1>("h00") - T_4187 := T_4186 - node T_4189 = cat(T_3813, T_4187) - resp.bits.target := T_4189 - node T_4190 = bits(hits, 61, 32) - node T_4191 = bits(hits, 31, 0) - node T_4193 = neq(T_4190, UInt<1>("h00")) - node T_4194 = or(T_4190, T_4191) - node T_4195 = bits(T_4194, 31, 16) - node T_4196 = bits(T_4194, 15, 0) - node T_4198 = neq(T_4195, UInt<1>("h00")) - node T_4199 = or(T_4195, T_4196) - node T_4200 = bits(T_4199, 15, 8) - node T_4201 = bits(T_4199, 7, 0) - node T_4203 = neq(T_4200, UInt<1>("h00")) - node T_4204 = or(T_4200, T_4201) - node T_4205 = bits(T_4204, 7, 4) - node T_4206 = bits(T_4204, 3, 0) - node T_4208 = neq(T_4205, UInt<1>("h00")) - node T_4209 = or(T_4205, T_4206) - node T_4210 = bits(T_4209, 3, 2) - node T_4211 = bits(T_4209, 1, 0) - node T_4213 = neq(T_4210, UInt<1>("h00")) - node T_4214 = or(T_4210, T_4211) - node T_4215 = bit(T_4214, 1) - node T_4216 = cat(T_4213, T_4215) - node T_4217 = cat(T_4208, T_4216) - node T_4218 = cat(T_4203, T_4217) - node T_4219 = cat(T_4198, T_4218) - node T_4220 = cat(T_4193, T_4219) - resp.bits.entry := T_4220 - infer accessor T_4221 = brIdx[resp.bits.entry] - resp.bits.bridx := T_4221 - resp.bits.mask := UInt<1>("h01") - cmem T_4225 : UInt<2>[128], clock - reg T_4227 : UInt<7>, clock, reset - node T_4228 = bit(hits, 0) - node T_4229 = bit(hits, 1) - node T_4230 = bit(hits, 2) - node T_4231 = bit(hits, 3) - node T_4232 = bit(hits, 4) - node T_4233 = bit(hits, 5) - node T_4234 = bit(hits, 6) - node T_4235 = bit(hits, 7) - node T_4236 = bit(hits, 8) - node T_4237 = bit(hits, 9) - node T_4238 = bit(hits, 10) - node T_4239 = bit(hits, 11) - node T_4240 = bit(hits, 12) - node T_4241 = bit(hits, 13) - node T_4242 = bit(hits, 14) - node T_4243 = bit(hits, 15) - node T_4244 = bit(hits, 16) - node T_4245 = bit(hits, 17) - node T_4246 = bit(hits, 18) - node T_4247 = bit(hits, 19) - node T_4248 = bit(hits, 20) - node T_4249 = bit(hits, 21) - node T_4250 = bit(hits, 22) - node T_4251 = bit(hits, 23) - node T_4252 = bit(hits, 24) - node T_4253 = bit(hits, 25) - node T_4254 = bit(hits, 26) - node T_4255 = bit(hits, 27) - node T_4256 = bit(hits, 28) - node T_4257 = bit(hits, 29) - node T_4258 = bit(hits, 30) - node T_4259 = bit(hits, 31) - node T_4260 = bit(hits, 32) - node T_4261 = bit(hits, 33) - node T_4262 = bit(hits, 34) - node T_4263 = bit(hits, 35) - node T_4264 = bit(hits, 36) - node T_4265 = bit(hits, 37) - node T_4266 = bit(hits, 38) - node T_4267 = bit(hits, 39) - node T_4268 = bit(hits, 40) - node T_4269 = bit(hits, 41) - node T_4270 = bit(hits, 42) - node T_4271 = bit(hits, 43) - node T_4272 = bit(hits, 44) - node T_4273 = bit(hits, 45) - node T_4274 = bit(hits, 46) - node T_4275 = bit(hits, 47) - node T_4276 = bit(hits, 48) - node T_4277 = bit(hits, 49) - node T_4278 = bit(hits, 50) - node T_4279 = bit(hits, 51) - node T_4280 = bit(hits, 52) - node T_4281 = bit(hits, 53) - node T_4282 = bit(hits, 54) - node T_4283 = bit(hits, 55) - node T_4284 = bit(hits, 56) - node T_4285 = bit(hits, 57) - node T_4286 = bit(hits, 58) - node T_4287 = bit(hits, 59) - node T_4288 = bit(hits, 60) - node T_4289 = bit(hits, 61) - node T_4291 = shl(isJump[0], 0) - node T_4292 = mux(T_4228, T_4291, UInt<1>("h00")) - node T_4294 = shl(isJump[1], 0) - node T_4295 = mux(T_4229, T_4294, UInt<1>("h00")) - node T_4297 = shl(isJump[2], 0) - node T_4298 = mux(T_4230, T_4297, UInt<1>("h00")) - node T_4300 = shl(isJump[3], 0) - node T_4301 = mux(T_4231, T_4300, UInt<1>("h00")) - node T_4303 = shl(isJump[4], 0) - node T_4304 = mux(T_4232, T_4303, UInt<1>("h00")) - node T_4306 = shl(isJump[5], 0) - node T_4307 = mux(T_4233, T_4306, UInt<1>("h00")) - node T_4309 = shl(isJump[6], 0) - node T_4310 = mux(T_4234, T_4309, UInt<1>("h00")) - node T_4312 = shl(isJump[7], 0) - node T_4313 = mux(T_4235, T_4312, UInt<1>("h00")) - node T_4315 = shl(isJump[8], 0) - node T_4316 = mux(T_4236, T_4315, UInt<1>("h00")) - node T_4318 = shl(isJump[9], 0) - node T_4319 = mux(T_4237, T_4318, UInt<1>("h00")) - node T_4321 = shl(isJump[10], 0) - node T_4322 = mux(T_4238, T_4321, UInt<1>("h00")) - node T_4324 = shl(isJump[11], 0) - node T_4325 = mux(T_4239, T_4324, UInt<1>("h00")) - node T_4327 = shl(isJump[12], 0) - node T_4328 = mux(T_4240, T_4327, UInt<1>("h00")) - node T_4330 = shl(isJump[13], 0) - node T_4331 = mux(T_4241, T_4330, UInt<1>("h00")) - node T_4333 = shl(isJump[14], 0) - node T_4334 = mux(T_4242, T_4333, UInt<1>("h00")) - node T_4336 = shl(isJump[15], 0) - node T_4337 = mux(T_4243, T_4336, UInt<1>("h00")) - node T_4339 = shl(isJump[16], 0) - node T_4340 = mux(T_4244, T_4339, UInt<1>("h00")) - node T_4342 = shl(isJump[17], 0) - node T_4343 = mux(T_4245, T_4342, UInt<1>("h00")) - node T_4345 = shl(isJump[18], 0) - node T_4346 = mux(T_4246, T_4345, UInt<1>("h00")) - node T_4348 = shl(isJump[19], 0) - node T_4349 = mux(T_4247, T_4348, UInt<1>("h00")) - node T_4351 = shl(isJump[20], 0) - node T_4352 = mux(T_4248, T_4351, UInt<1>("h00")) - node T_4354 = shl(isJump[21], 0) - node T_4355 = mux(T_4249, T_4354, UInt<1>("h00")) - node T_4357 = shl(isJump[22], 0) - node T_4358 = mux(T_4250, T_4357, UInt<1>("h00")) - node T_4360 = shl(isJump[23], 0) - node T_4361 = mux(T_4251, T_4360, UInt<1>("h00")) - node T_4363 = shl(isJump[24], 0) - node T_4364 = mux(T_4252, T_4363, UInt<1>("h00")) - node T_4366 = shl(isJump[25], 0) - node T_4367 = mux(T_4253, T_4366, UInt<1>("h00")) - node T_4369 = shl(isJump[26], 0) - node T_4370 = mux(T_4254, T_4369, UInt<1>("h00")) - node T_4372 = shl(isJump[27], 0) - node T_4373 = mux(T_4255, T_4372, UInt<1>("h00")) - node T_4375 = shl(isJump[28], 0) - node T_4376 = mux(T_4256, T_4375, UInt<1>("h00")) - node T_4378 = shl(isJump[29], 0) - node T_4379 = mux(T_4257, T_4378, UInt<1>("h00")) - node T_4381 = shl(isJump[30], 0) - node T_4382 = mux(T_4258, T_4381, UInt<1>("h00")) - node T_4384 = shl(isJump[31], 0) - node T_4385 = mux(T_4259, T_4384, UInt<1>("h00")) - node T_4387 = shl(isJump[32], 0) - node T_4388 = mux(T_4260, T_4387, UInt<1>("h00")) - node T_4390 = shl(isJump[33], 0) - node T_4391 = mux(T_4261, T_4390, UInt<1>("h00")) - node T_4393 = shl(isJump[34], 0) - node T_4394 = mux(T_4262, T_4393, UInt<1>("h00")) - node T_4396 = shl(isJump[35], 0) - node T_4397 = mux(T_4263, T_4396, UInt<1>("h00")) - node T_4399 = shl(isJump[36], 0) - node T_4400 = mux(T_4264, T_4399, UInt<1>("h00")) - node T_4402 = shl(isJump[37], 0) - node T_4403 = mux(T_4265, T_4402, UInt<1>("h00")) - node T_4405 = shl(isJump[38], 0) - node T_4406 = mux(T_4266, T_4405, UInt<1>("h00")) - node T_4408 = shl(isJump[39], 0) - node T_4409 = mux(T_4267, T_4408, UInt<1>("h00")) - node T_4411 = shl(isJump[40], 0) - node T_4412 = mux(T_4268, T_4411, UInt<1>("h00")) - node T_4414 = shl(isJump[41], 0) - node T_4415 = mux(T_4269, T_4414, UInt<1>("h00")) - node T_4417 = shl(isJump[42], 0) - node T_4418 = mux(T_4270, T_4417, UInt<1>("h00")) - node T_4420 = shl(isJump[43], 0) - node T_4421 = mux(T_4271, T_4420, UInt<1>("h00")) - node T_4423 = shl(isJump[44], 0) - node T_4424 = mux(T_4272, T_4423, UInt<1>("h00")) - node T_4426 = shl(isJump[45], 0) - node T_4427 = mux(T_4273, T_4426, UInt<1>("h00")) - node T_4429 = shl(isJump[46], 0) - node T_4430 = mux(T_4274, T_4429, UInt<1>("h00")) - node T_4432 = shl(isJump[47], 0) - node T_4433 = mux(T_4275, T_4432, UInt<1>("h00")) - node T_4435 = shl(isJump[48], 0) - node T_4436 = mux(T_4276, T_4435, UInt<1>("h00")) - node T_4438 = shl(isJump[49], 0) - node T_4439 = mux(T_4277, T_4438, UInt<1>("h00")) - node T_4441 = shl(isJump[50], 0) - node T_4442 = mux(T_4278, T_4441, UInt<1>("h00")) - node T_4444 = shl(isJump[51], 0) - node T_4445 = mux(T_4279, T_4444, UInt<1>("h00")) - node T_4447 = shl(isJump[52], 0) - node T_4448 = mux(T_4280, T_4447, UInt<1>("h00")) - node T_4450 = shl(isJump[53], 0) - node T_4451 = mux(T_4281, T_4450, UInt<1>("h00")) - node T_4453 = shl(isJump[54], 0) - node T_4454 = mux(T_4282, T_4453, UInt<1>("h00")) - node T_4456 = shl(isJump[55], 0) - node T_4457 = mux(T_4283, T_4456, UInt<1>("h00")) - node T_4459 = shl(isJump[56], 0) - node T_4460 = mux(T_4284, T_4459, UInt<1>("h00")) - node T_4462 = shl(isJump[57], 0) - node T_4463 = mux(T_4285, T_4462, UInt<1>("h00")) - node T_4465 = shl(isJump[58], 0) - node T_4466 = mux(T_4286, T_4465, UInt<1>("h00")) - node T_4468 = shl(isJump[59], 0) - node T_4469 = mux(T_4287, T_4468, UInt<1>("h00")) - node T_4471 = shl(isJump[60], 0) - node T_4472 = mux(T_4288, T_4471, UInt<1>("h00")) - node T_4474 = shl(isJump[61], 0) - node T_4475 = mux(T_4289, T_4474, UInt<1>("h00")) - node T_4477 = or(T_4292, T_4295) - node T_4478 = or(T_4477, T_4298) - node T_4479 = or(T_4478, T_4301) - node T_4480 = or(T_4479, T_4304) - node T_4481 = or(T_4480, T_4307) - node T_4482 = or(T_4481, T_4310) - node T_4483 = or(T_4482, T_4313) - node T_4484 = or(T_4483, T_4316) - node T_4485 = or(T_4484, T_4319) - node T_4486 = or(T_4485, T_4322) - node T_4487 = or(T_4486, T_4325) - node T_4488 = or(T_4487, T_4328) - node T_4489 = or(T_4488, T_4331) - node T_4490 = or(T_4489, T_4334) - node T_4491 = or(T_4490, T_4337) - node T_4492 = or(T_4491, T_4340) - node T_4493 = or(T_4492, T_4343) - node T_4494 = or(T_4493, T_4346) - node T_4495 = or(T_4494, T_4349) - node T_4496 = or(T_4495, T_4352) - node T_4497 = or(T_4496, T_4355) - node T_4498 = or(T_4497, T_4358) - node T_4499 = or(T_4498, T_4361) - node T_4500 = or(T_4499, T_4364) - node T_4501 = or(T_4500, T_4367) - node T_4502 = or(T_4501, T_4370) - node T_4503 = or(T_4502, T_4373) - node T_4504 = or(T_4503, T_4376) - node T_4505 = or(T_4504, T_4379) - node T_4506 = or(T_4505, T_4382) - node T_4507 = or(T_4506, T_4385) - node T_4508 = or(T_4507, T_4388) - node T_4509 = or(T_4508, T_4391) - node T_4510 = or(T_4509, T_4394) - node T_4511 = or(T_4510, T_4397) - node T_4512 = or(T_4511, T_4400) - node T_4513 = or(T_4512, T_4403) - node T_4514 = or(T_4513, T_4406) - node T_4515 = or(T_4514, T_4409) - node T_4516 = or(T_4515, T_4412) - node T_4517 = or(T_4516, T_4415) - node T_4518 = or(T_4517, T_4418) - node T_4519 = or(T_4518, T_4421) - node T_4520 = or(T_4519, T_4424) - node T_4521 = or(T_4520, T_4427) - node T_4522 = or(T_4521, T_4430) - node T_4523 = or(T_4522, T_4433) - node T_4524 = or(T_4523, T_4436) - node T_4525 = or(T_4524, T_4439) - node T_4526 = or(T_4525, T_4442) - node T_4527 = or(T_4526, T_4445) - node T_4528 = or(T_4527, T_4448) - node T_4529 = or(T_4528, T_4451) - node T_4530 = or(T_4529, T_4454) - node T_4531 = or(T_4530, T_4457) - node T_4532 = or(T_4531, T_4460) - node T_4533 = or(T_4532, T_4463) - node T_4534 = or(T_4533, T_4466) - node T_4535 = or(T_4534, T_4469) - node T_4536 = or(T_4535, T_4472) - node T_4537 = or(T_4536, T_4475) - wire T_4538 : UInt<1> - T_4538 := UInt<1>("h00") - T_4538 := T_4537 - node T_4541 = eq(T_4538, UInt<1>("h00")) - node T_4542 = and(req.valid, resp.valid) - node T_4543 = and(T_4542, T_4541) - wire T_4547 : {history : UInt<7>, value : UInt<2>} - T_4547.value := UInt<1>("h00") - T_4547.history := UInt<1>("h00") - node T_4552 = bits(req.bits.addr, 8, 2) - node T_4553 = xor(T_4552, T_4227) - infer accessor T_4554 = T_4225[T_4553] - T_4547.value := T_4554 - T_4547.history := T_4227 - node T_4555 = bit(T_4547.value, 0) - when T_4543 : - node T_4556 = bits(T_4227, 6, 1) - node T_4557 = cat(T_4555, T_4556) - T_4227 := T_4557 - skip - node T_4558 = and(bht_update.valid, bht_update.bits.prediction.valid) - when T_4558 : - node T_4559 = bits(bht_update.bits.pc, 8, 2) - node T_4560 = xor(T_4559, bht_update.bits.prediction.bits.bht.history) - infer accessor T_4561 = T_4225[T_4560] - node T_4562 = bit(bht_update.bits.prediction.bits.bht.value, 1) - node T_4563 = bit(bht_update.bits.prediction.bits.bht.value, 0) - node T_4564 = and(T_4562, T_4563) - node T_4565 = bit(bht_update.bits.prediction.bits.bht.value, 1) - node T_4566 = bit(bht_update.bits.prediction.bits.bht.value, 0) - node T_4567 = or(T_4565, T_4566) - node T_4568 = and(T_4567, bht_update.bits.taken) - node T_4569 = or(T_4564, T_4568) - node T_4570 = cat(bht_update.bits.taken, T_4569) - T_4561 := T_4570 - when bht_update.bits.mispredict : - node T_4571 = bits(bht_update.bits.prediction.bits.bht.history, 6, 1) - node T_4572 = cat(bht_update.bits.taken, T_4571) - T_4227 := T_4572 - skip - skip - node T_4573 = bit(T_4547.value, 0) - node T_4575 = eq(T_4573, UInt<1>("h00")) - node T_4576 = and(T_4575, T_4541) - when T_4576 : - resp.bits.taken := UInt<1>("h00") - skip - resp.bits.bht <> T_4547 - reg T_4579 : UInt<2>, clock, reset - onreset T_4579 := UInt<2>("h00") - reg T_4581 : UInt<1>, clock, reset - onreset T_4581 := UInt<1>("h00") - reg T_4590 : UInt[2], clock, reset - node T_4594 = bit(hits, 0) - node T_4595 = bit(hits, 1) - node T_4596 = bit(hits, 2) - node T_4597 = bit(hits, 3) - node T_4598 = bit(hits, 4) - node T_4599 = bit(hits, 5) - node T_4600 = bit(hits, 6) - node T_4601 = bit(hits, 7) - node T_4602 = bit(hits, 8) - node T_4603 = bit(hits, 9) - node T_4604 = bit(hits, 10) - node T_4605 = bit(hits, 11) - node T_4606 = bit(hits, 12) - node T_4607 = bit(hits, 13) - node T_4608 = bit(hits, 14) - node T_4609 = bit(hits, 15) - node T_4610 = bit(hits, 16) - node T_4611 = bit(hits, 17) - node T_4612 = bit(hits, 18) - node T_4613 = bit(hits, 19) - node T_4614 = bit(hits, 20) - node T_4615 = bit(hits, 21) - node T_4616 = bit(hits, 22) - node T_4617 = bit(hits, 23) - node T_4618 = bit(hits, 24) - node T_4619 = bit(hits, 25) - node T_4620 = bit(hits, 26) - node T_4621 = bit(hits, 27) - node T_4622 = bit(hits, 28) - node T_4623 = bit(hits, 29) - node T_4624 = bit(hits, 30) - node T_4625 = bit(hits, 31) - node T_4626 = bit(hits, 32) - node T_4627 = bit(hits, 33) - node T_4628 = bit(hits, 34) - node T_4629 = bit(hits, 35) - node T_4630 = bit(hits, 36) - node T_4631 = bit(hits, 37) - node T_4632 = bit(hits, 38) - node T_4633 = bit(hits, 39) - node T_4634 = bit(hits, 40) - node T_4635 = bit(hits, 41) - node T_4636 = bit(hits, 42) - node T_4637 = bit(hits, 43) - node T_4638 = bit(hits, 44) - node T_4639 = bit(hits, 45) - node T_4640 = bit(hits, 46) - node T_4641 = bit(hits, 47) - node T_4642 = bit(hits, 48) - node T_4643 = bit(hits, 49) - node T_4644 = bit(hits, 50) - node T_4645 = bit(hits, 51) - node T_4646 = bit(hits, 52) - node T_4647 = bit(hits, 53) - node T_4648 = bit(hits, 54) - node T_4649 = bit(hits, 55) - node T_4650 = bit(hits, 56) - node T_4651 = bit(hits, 57) - node T_4652 = bit(hits, 58) - node T_4653 = bit(hits, 59) - node T_4654 = bit(hits, 60) - node T_4655 = bit(hits, 61) - node T_4657 = shl(useRAS[0], 0) - node T_4658 = mux(T_4594, T_4657, UInt<1>("h00")) - node T_4660 = shl(useRAS[1], 0) - node T_4661 = mux(T_4595, T_4660, UInt<1>("h00")) - node T_4663 = shl(useRAS[2], 0) - node T_4664 = mux(T_4596, T_4663, UInt<1>("h00")) - node T_4666 = shl(useRAS[3], 0) - node T_4667 = mux(T_4597, T_4666, UInt<1>("h00")) - node T_4669 = shl(useRAS[4], 0) - node T_4670 = mux(T_4598, T_4669, UInt<1>("h00")) - node T_4672 = shl(useRAS[5], 0) - node T_4673 = mux(T_4599, T_4672, UInt<1>("h00")) - node T_4675 = shl(useRAS[6], 0) - node T_4676 = mux(T_4600, T_4675, UInt<1>("h00")) - node T_4678 = shl(useRAS[7], 0) - node T_4679 = mux(T_4601, T_4678, UInt<1>("h00")) - node T_4681 = shl(useRAS[8], 0) - node T_4682 = mux(T_4602, T_4681, UInt<1>("h00")) - node T_4684 = shl(useRAS[9], 0) - node T_4685 = mux(T_4603, T_4684, UInt<1>("h00")) - node T_4687 = shl(useRAS[10], 0) - node T_4688 = mux(T_4604, T_4687, UInt<1>("h00")) - node T_4690 = shl(useRAS[11], 0) - node T_4691 = mux(T_4605, T_4690, UInt<1>("h00")) - node T_4693 = shl(useRAS[12], 0) - node T_4694 = mux(T_4606, T_4693, UInt<1>("h00")) - node T_4696 = shl(useRAS[13], 0) - node T_4697 = mux(T_4607, T_4696, UInt<1>("h00")) - node T_4699 = shl(useRAS[14], 0) - node T_4700 = mux(T_4608, T_4699, UInt<1>("h00")) - node T_4702 = shl(useRAS[15], 0) - node T_4703 = mux(T_4609, T_4702, UInt<1>("h00")) - node T_4705 = shl(useRAS[16], 0) - node T_4706 = mux(T_4610, T_4705, UInt<1>("h00")) - node T_4708 = shl(useRAS[17], 0) - node T_4709 = mux(T_4611, T_4708, UInt<1>("h00")) - node T_4711 = shl(useRAS[18], 0) - node T_4712 = mux(T_4612, T_4711, UInt<1>("h00")) - node T_4714 = shl(useRAS[19], 0) - node T_4715 = mux(T_4613, T_4714, UInt<1>("h00")) - node T_4717 = shl(useRAS[20], 0) - node T_4718 = mux(T_4614, T_4717, UInt<1>("h00")) - node T_4720 = shl(useRAS[21], 0) - node T_4721 = mux(T_4615, T_4720, UInt<1>("h00")) - node T_4723 = shl(useRAS[22], 0) - node T_4724 = mux(T_4616, T_4723, UInt<1>("h00")) - node T_4726 = shl(useRAS[23], 0) - node T_4727 = mux(T_4617, T_4726, UInt<1>("h00")) - node T_4729 = shl(useRAS[24], 0) - node T_4730 = mux(T_4618, T_4729, UInt<1>("h00")) - node T_4732 = shl(useRAS[25], 0) - node T_4733 = mux(T_4619, T_4732, UInt<1>("h00")) - node T_4735 = shl(useRAS[26], 0) - node T_4736 = mux(T_4620, T_4735, UInt<1>("h00")) - node T_4738 = shl(useRAS[27], 0) - node T_4739 = mux(T_4621, T_4738, UInt<1>("h00")) - node T_4741 = shl(useRAS[28], 0) - node T_4742 = mux(T_4622, T_4741, UInt<1>("h00")) - node T_4744 = shl(useRAS[29], 0) - node T_4745 = mux(T_4623, T_4744, UInt<1>("h00")) - node T_4747 = shl(useRAS[30], 0) - node T_4748 = mux(T_4624, T_4747, UInt<1>("h00")) - node T_4750 = shl(useRAS[31], 0) - node T_4751 = mux(T_4625, T_4750, UInt<1>("h00")) - node T_4753 = shl(useRAS[32], 0) - node T_4754 = mux(T_4626, T_4753, UInt<1>("h00")) - node T_4756 = shl(useRAS[33], 0) - node T_4757 = mux(T_4627, T_4756, UInt<1>("h00")) - node T_4759 = shl(useRAS[34], 0) - node T_4760 = mux(T_4628, T_4759, UInt<1>("h00")) - node T_4762 = shl(useRAS[35], 0) - node T_4763 = mux(T_4629, T_4762, UInt<1>("h00")) - node T_4765 = shl(useRAS[36], 0) - node T_4766 = mux(T_4630, T_4765, UInt<1>("h00")) - node T_4768 = shl(useRAS[37], 0) - node T_4769 = mux(T_4631, T_4768, UInt<1>("h00")) - node T_4771 = shl(useRAS[38], 0) - node T_4772 = mux(T_4632, T_4771, UInt<1>("h00")) - node T_4774 = shl(useRAS[39], 0) - node T_4775 = mux(T_4633, T_4774, UInt<1>("h00")) - node T_4777 = shl(useRAS[40], 0) - node T_4778 = mux(T_4634, T_4777, UInt<1>("h00")) - node T_4780 = shl(useRAS[41], 0) - node T_4781 = mux(T_4635, T_4780, UInt<1>("h00")) - node T_4783 = shl(useRAS[42], 0) - node T_4784 = mux(T_4636, T_4783, UInt<1>("h00")) - node T_4786 = shl(useRAS[43], 0) - node T_4787 = mux(T_4637, T_4786, UInt<1>("h00")) - node T_4789 = shl(useRAS[44], 0) - node T_4790 = mux(T_4638, T_4789, UInt<1>("h00")) - node T_4792 = shl(useRAS[45], 0) - node T_4793 = mux(T_4639, T_4792, UInt<1>("h00")) - node T_4795 = shl(useRAS[46], 0) - node T_4796 = mux(T_4640, T_4795, UInt<1>("h00")) - node T_4798 = shl(useRAS[47], 0) - node T_4799 = mux(T_4641, T_4798, UInt<1>("h00")) - node T_4801 = shl(useRAS[48], 0) - node T_4802 = mux(T_4642, T_4801, UInt<1>("h00")) - node T_4804 = shl(useRAS[49], 0) - node T_4805 = mux(T_4643, T_4804, UInt<1>("h00")) - node T_4807 = shl(useRAS[50], 0) - node T_4808 = mux(T_4644, T_4807, UInt<1>("h00")) - node T_4810 = shl(useRAS[51], 0) - node T_4811 = mux(T_4645, T_4810, UInt<1>("h00")) - node T_4813 = shl(useRAS[52], 0) - node T_4814 = mux(T_4646, T_4813, UInt<1>("h00")) - node T_4816 = shl(useRAS[53], 0) - node T_4817 = mux(T_4647, T_4816, UInt<1>("h00")) - node T_4819 = shl(useRAS[54], 0) - node T_4820 = mux(T_4648, T_4819, UInt<1>("h00")) - node T_4822 = shl(useRAS[55], 0) - node T_4823 = mux(T_4649, T_4822, UInt<1>("h00")) - node T_4825 = shl(useRAS[56], 0) - node T_4826 = mux(T_4650, T_4825, UInt<1>("h00")) - node T_4828 = shl(useRAS[57], 0) - node T_4829 = mux(T_4651, T_4828, UInt<1>("h00")) - node T_4831 = shl(useRAS[58], 0) - node T_4832 = mux(T_4652, T_4831, UInt<1>("h00")) - node T_4834 = shl(useRAS[59], 0) - node T_4835 = mux(T_4653, T_4834, UInt<1>("h00")) - node T_4837 = shl(useRAS[60], 0) - node T_4838 = mux(T_4654, T_4837, UInt<1>("h00")) - node T_4840 = shl(useRAS[61], 0) - node T_4841 = mux(T_4655, T_4840, UInt<1>("h00")) - node T_4843 = or(T_4658, T_4661) - node T_4844 = or(T_4843, T_4664) - node T_4845 = or(T_4844, T_4667) - node T_4846 = or(T_4845, T_4670) - node T_4847 = or(T_4846, T_4673) - node T_4848 = or(T_4847, T_4676) - node T_4849 = or(T_4848, T_4679) - node T_4850 = or(T_4849, T_4682) - node T_4851 = or(T_4850, T_4685) - node T_4852 = or(T_4851, T_4688) - node T_4853 = or(T_4852, T_4691) - node T_4854 = or(T_4853, T_4694) - node T_4855 = or(T_4854, T_4697) - node T_4856 = or(T_4855, T_4700) - node T_4857 = or(T_4856, T_4703) - node T_4858 = or(T_4857, T_4706) - node T_4859 = or(T_4858, T_4709) - node T_4860 = or(T_4859, T_4712) - node T_4861 = or(T_4860, T_4715) - node T_4862 = or(T_4861, T_4718) - node T_4863 = or(T_4862, T_4721) - node T_4864 = or(T_4863, T_4724) - node T_4865 = or(T_4864, T_4727) - node T_4866 = or(T_4865, T_4730) - node T_4867 = or(T_4866, T_4733) - node T_4868 = or(T_4867, T_4736) - node T_4869 = or(T_4868, T_4739) - node T_4870 = or(T_4869, T_4742) - node T_4871 = or(T_4870, T_4745) - node T_4872 = or(T_4871, T_4748) - node T_4873 = or(T_4872, T_4751) - node T_4874 = or(T_4873, T_4754) - node T_4875 = or(T_4874, T_4757) - node T_4876 = or(T_4875, T_4760) - node T_4877 = or(T_4876, T_4763) - node T_4878 = or(T_4877, T_4766) - node T_4879 = or(T_4878, T_4769) - node T_4880 = or(T_4879, T_4772) - node T_4881 = or(T_4880, T_4775) - node T_4882 = or(T_4881, T_4778) - node T_4883 = or(T_4882, T_4781) - node T_4884 = or(T_4883, T_4784) - node T_4885 = or(T_4884, T_4787) - node T_4886 = or(T_4885, T_4790) - node T_4887 = or(T_4886, T_4793) - node T_4888 = or(T_4887, T_4796) - node T_4889 = or(T_4888, T_4799) - node T_4890 = or(T_4889, T_4802) - node T_4891 = or(T_4890, T_4805) - node T_4892 = or(T_4891, T_4808) - node T_4893 = or(T_4892, T_4811) - node T_4894 = or(T_4893, T_4814) - node T_4895 = or(T_4894, T_4817) - node T_4896 = or(T_4895, T_4820) - node T_4897 = or(T_4896, T_4823) - node T_4898 = or(T_4897, T_4826) - node T_4899 = or(T_4898, T_4829) - node T_4900 = or(T_4899, T_4832) - node T_4901 = or(T_4900, T_4835) - node T_4902 = or(T_4901, T_4838) - node T_4903 = or(T_4902, T_4841) - wire T_4904 : UInt<1> - T_4904 := UInt<1>("h00") - T_4904 := T_4903 - node T_4907 = eq(T_4579, UInt<1>("h00")) - node T_4909 = eq(T_4907, UInt<1>("h00")) - node T_4910 = and(T_4909, T_4904) - when T_4910 : - infer accessor T_4911 = T_4590[T_4581] - resp.bits.target := T_4911 - skip - when ras_update.valid : - when ras_update.bits.isCall : - node T_4913 = lt(T_4579, UInt<2>("h02")) - when T_4913 : - node T_4915 = addw(T_4579, UInt<1>("h01")) - T_4579 := T_4915 - skip - node T_4918 = lt(T_4581, UInt<1>("h01")) - node T_4919 = or(UInt<1>("h01"), T_4918) - node T_4921 = addw(T_4581, UInt<1>("h01")) - node T_4923 = mux(T_4919, T_4921, UInt<1>("h00")) - infer accessor T_4924 = T_4590[T_4923] - T_4924 := ras_update.bits.returnAddr - T_4581 := T_4923 - when T_4904 : - resp.bits.target := ras_update.bits.returnAddr - skip - skip - else : - node T_4925 = and(ras_update.bits.isReturn, ras_update.bits.prediction.valid) - when T_4925 : - node T_4927 = eq(T_4579, UInt<1>("h00")) - node T_4929 = eq(T_4927, UInt<1>("h00")) - when T_4929 : - node T_4931 = subw(T_4579, UInt<1>("h01")) - T_4579 := T_4931 - node T_4934 = gt(T_4581, UInt<1>("h00")) - node T_4935 = or(UInt<1>("h01"), T_4934) - node T_4937 = subw(T_4581, UInt<1>("h01")) - node T_4939 = mux(T_4935, T_4937, UInt<1>("h01")) - T_4581 := T_4939 - skip - skip - skip - skip - when invalidate : - T_4579 := UInt<1>("h00") - skip - - module FlowThroughSerializer : - output done : UInt<1> - output cnt : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - input clock : Clock - input reset : UInt<1> - - done := UInt<1>("h00") - cnt := UInt<1>("h00") - out.bits.g_type := UInt<1>("h00") - out.bits.is_builtin_type := UInt<1>("h00") - out.bits.manager_xact_id := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.valid := UInt<1>("h00") - in.ready := UInt<1>("h00") - out <> in - cnt := UInt<1>("h00") - done := UInt<1>("h01") - - module ICache : - output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - input invalidate : UInt<1> - output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}} - input req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - mem_1.grant.ready := UInt<1>("h00") - mem_1.acquire.bits.union := UInt<1>("h00") - mem_1.acquire.bits.a_type := UInt<1>("h00") - mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") - mem_1.acquire.bits.data := UInt<1>("h00") - mem_1.acquire.bits.addr_beat := UInt<1>("h00") - mem_1.acquire.bits.client_xact_id := UInt<1>("h00") - mem_1.acquire.bits.addr_block := UInt<1>("h00") - mem_1.acquire.valid := UInt<1>("h00") - resp.bits.datablock := UInt<1>("h00") - resp.bits.data := UInt<1>("h00") - resp.valid := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg invalidated : UInt<1>, clock, reset - node stall = eq(resp.ready, UInt<1>("h00")) - wire rdy : UInt<1> - rdy := UInt<1>("h00") - reg s2_valid : UInt<1>, clock, reset - onreset s2_valid := UInt<1>("h00") - reg s2_addr : UInt<32>, clock, reset - wire s2_any_tag_hit : UInt<1> - s2_any_tag_hit := UInt<1>("h00") - reg s1_valid : UInt<1>, clock, reset - onreset s1_valid := UInt<1>("h00") - reg s1_pgoff : UInt<12>, clock, reset - node s1_addr = cat(req.bits.ppn, s1_pgoff) - node s1_tag = bits(s1_addr, 31, 12) - node T_343 = and(s1_valid, stall) - node s0_valid = or(req.valid, T_343) - node T_345 = and(s1_valid, stall) - node s0_pgoff = mux(T_345, s1_pgoff, req.bits.idx) - node T_347 = and(req.valid, rdy) - node T_348 = and(s1_valid, stall) - node T_350 = eq(req.bits.kill, UInt<1>("h00")) - node T_351 = and(T_348, T_350) - node T_352 = or(T_347, T_351) - s1_valid := T_352 - node T_353 = and(req.valid, rdy) - when T_353 : - s1_pgoff := req.bits.idx - skip - node T_354 = and(s1_valid, rdy) - node T_356 = eq(req.bits.kill, UInt<1>("h00")) - node T_357 = and(T_354, T_356) - node T_358 = and(resp.valid, stall) - node T_359 = or(T_357, T_358) - s2_valid := T_359 - node T_360 = and(s1_valid, rdy) - node T_362 = eq(stall, UInt<1>("h00")) - node T_363 = and(T_360, T_362) - when T_363 : - s2_addr := s1_addr - skip - node s2_tag = bits(s2_addr, 31, 12) - node s2_idx = bits(s2_addr, 11, 6) - node s2_offset = bits(s2_addr, 5, 0) - node s2_hit = and(s2_valid, s2_any_tag_hit) - node T_369 = eq(s2_any_tag_hit, UInt<1>("h00")) - node s2_miss = and(s2_valid, T_369) - node T_371 = eq(state, UInt<1>("h00")) - node T_373 = eq(s2_miss, UInt<1>("h00")) - node T_374 = and(T_371, T_373) - rdy := T_374 - inst T_942 of FlowThroughSerializer - T_942.out.ready := UInt<1>("h00") - T_942.in.bits.g_type := UInt<1>("h00") - T_942.in.bits.is_builtin_type := UInt<1>("h00") - T_942.in.bits.manager_xact_id := UInt<1>("h00") - T_942.in.bits.client_xact_id := UInt<1>("h00") - T_942.in.bits.data := UInt<1>("h00") - T_942.in.bits.addr_beat := UInt<1>("h00") - T_942.in.valid := UInt<1>("h00") - T_942.reset := UInt<1>("h00") - T_942.clock := clock - T_942.reset := reset - T_942.in.valid := mem_1.grant.valid - T_942.in.bits <> mem_1.grant.bits - mem_1.grant.ready := T_942.in.ready - node T_384 = and(T_942.out.ready, T_942.out.valid) - reg refill_cnt : UInt<2>, clock, reset - onreset refill_cnt := UInt<2>("h00") - when T_384 : - node T_388 = eq(refill_cnt, UInt<2>("h03")) - node T_390 = and(UInt<1>("h00"), T_388) - node T_393 = addw(refill_cnt, UInt<1>("h01")) - node T_394 = mux(T_390, UInt<1>("h00"), T_393) - refill_cnt := T_394 - skip - node refill_wrap = and(T_384, T_388) - node T_396 = eq(state, UInt<2>("h03")) - node refill_done = and(T_396, refill_wrap) - T_942.out.ready := UInt<1>("h01") - reg T_400 : UInt<16>, clock, reset - onreset T_400 := UInt<16>("h01") - when s2_miss : - node T_401 = bit(T_400, 0) - node T_402 = bit(T_400, 2) - node T_403 = xor(T_401, T_402) - node T_404 = bit(T_400, 3) - node T_405 = xor(T_403, T_404) - node T_406 = bit(T_400, 5) - node T_407 = xor(T_405, T_406) - node T_408 = bits(T_400, 15, 1) - node T_409 = cat(T_407, T_408) - T_400 := T_409 - skip - node repl_way = bits(T_400, 1, 0) - cmem T_413 : UInt<80>[64], clock - node T_414 = bits(s0_pgoff, 11, 6) - node T_416 = eq(refill_done, UInt<1>("h00")) - node T_417 = and(T_416, s0_valid) - reg T_418 : UInt<6>, clock, reset - when T_417 : - T_418 := T_414 - skip - infer accessor tag_rdata = T_413[T_418] - when refill_done : - node T_421 = dshl(UInt<1>("h01"), repl_way) - node T_422 = bit(T_421, 0) - node T_423 = bit(T_421, 1) - node T_424 = bit(T_421, 2) - node T_425 = bit(T_421, 3) - wire T_427 : UInt<1>[4] - T_427[0] := T_422 - T_427[1] := T_423 - T_427[2] := T_424 - T_427[3] := T_425 - node T_434 = subw(UInt<20>("h00"), T_427[0]) - node T_436 = subw(UInt<20>("h00"), T_427[1]) - node T_438 = subw(UInt<20>("h00"), T_427[2]) - node T_440 = subw(UInt<20>("h00"), T_427[3]) - wire T_442 : UInt<20>[4] - T_442[0] := T_434 - T_442[1] := T_436 - T_442[2] := T_438 - T_442[3] := T_440 - node T_448 = cat(T_442[3], T_442[2]) - node T_449 = cat(T_442[1], T_442[0]) - node T_450 = cat(T_448, T_449) - node T_451 = cat(s2_tag, s2_tag) - node T_452 = cat(T_451, T_451) - infer accessor T_453 = T_413[s2_idx] - node T_454 = not(T_450) - node T_455 = and(T_453, T_454) - node T_456 = and(T_452, T_450) - node T_457 = or(T_455, T_456) - wire T_458 : UInt<80> - T_458 := UInt<1>("h00") - T_458 := T_457 - infer accessor T_460 = T_413[s2_idx] - T_460 := T_458 - skip - reg vb_array : UInt<256>, clock, reset - onreset vb_array := UInt<256>("h00") - node T_464 = eq(invalidated, UInt<1>("h00")) - node T_465 = and(refill_done, T_464) - when T_465 : - node T_466 = cat(repl_way, s2_idx) - node T_469 = dshl(UInt<1>("h01"), T_466) - node T_470 = or(vb_array, T_469) - node T_471 = not(vb_array) - node T_472 = or(T_471, T_469) - node T_473 = not(T_472) - node T_474 = mux(UInt<1>("h01"), T_470, T_473) - vb_array := T_474 - skip - when invalidate : - vb_array := UInt<1>("h00") - invalidated := UInt<1>("h01") - skip - wire s2_disparity : UInt<1>[4] - s2_disparity[0] := UInt<1>("h00") - s2_disparity[1] := UInt<1>("h00") - s2_disparity[2] := UInt<1>("h00") - s2_disparity[3] := UInt<1>("h00") - node T_497 = and(s2_valid, s2_disparity[0]) - when T_497 : - node T_499 = cat(UInt<1>("h00"), s2_idx) - node T_502 = dshl(UInt<1>("h01"), T_499) - node T_503 = or(vb_array, T_502) - node T_504 = not(vb_array) - node T_505 = or(T_504, T_502) - node T_506 = not(T_505) - node T_507 = mux(UInt<1>("h00"), T_503, T_506) - vb_array := T_507 - skip - node T_508 = and(s2_valid, s2_disparity[1]) - when T_508 : - node T_510 = cat(UInt<1>("h01"), s2_idx) - node T_513 = dshl(UInt<1>("h01"), T_510) - node T_514 = or(vb_array, T_513) - node T_515 = not(vb_array) - node T_516 = or(T_515, T_513) - node T_517 = not(T_516) - node T_518 = mux(UInt<1>("h00"), T_514, T_517) - vb_array := T_518 - skip - node T_519 = and(s2_valid, s2_disparity[2]) - when T_519 : - node T_521 = cat(UInt<2>("h02"), s2_idx) - node T_524 = dshl(UInt<1>("h01"), T_521) - node T_525 = or(vb_array, T_524) - node T_526 = not(vb_array) - node T_527 = or(T_526, T_524) - node T_528 = not(T_527) - node T_529 = mux(UInt<1>("h00"), T_525, T_528) - vb_array := T_529 - skip - node T_530 = and(s2_valid, s2_disparity[3]) - when T_530 : - node T_532 = cat(UInt<2>("h03"), s2_idx) - node T_535 = dshl(UInt<1>("h01"), T_532) - node T_536 = or(vb_array, T_535) - node T_537 = not(vb_array) - node T_538 = or(T_537, T_535) - node T_539 = not(T_538) - node T_540 = mux(UInt<1>("h00"), T_536, T_539) - vb_array := T_540 - skip - wire s1_tag_match : UInt<1>[4] - s1_tag_match[0] := UInt<1>("h00") - s1_tag_match[1] := UInt<1>("h00") - s1_tag_match[2] := UInt<1>("h00") - s1_tag_match[3] := UInt<1>("h00") - wire s2_tag_hit : UInt<1>[4] - s2_tag_hit[0] := UInt<1>("h00") - s2_tag_hit[1] := UInt<1>("h00") - s2_tag_hit[2] := UInt<1>("h00") - s2_tag_hit[3] := UInt<1>("h00") - reg s2_dout : UInt<128>[4], clock, reset - node T_598 = eq(invalidate, UInt<1>("h00")) - node T_600 = bits(s1_pgoff, 11, 6) - node T_601 = cat(UInt<1>("h00"), T_600) - node T_602 = dshr(vb_array, T_601) - node T_603 = bit(T_602, 0) - node T_604 = bit(T_603, 0) - node T_605 = and(T_598, T_604) - reg T_607 : UInt<1>, clock, reset - reg T_609 : UInt<1>, clock, reset - reg T_611 : UInt<1>, clock, reset - node T_612 = bits(tag_rdata, 19, 0) - node T_613 = and(s1_valid, rdy) - node T_615 = eq(stall, UInt<1>("h00")) - node T_616 = and(T_613, T_615) - when T_616 : - T_607 := T_605 - node T_619 = or(UInt<1>("h00"), UInt<1>("h00")) - T_609 := T_619 - T_611 := s1_tag_match[0] - skip - node T_620 = bits(T_612, 19, 0) - node T_621 = eq(T_620, s1_tag) - s1_tag_match[0] := T_621 - node T_622 = and(T_607, T_611) - s2_tag_hit[0] := T_622 - node T_625 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_626 = or(T_609, T_625) - node T_627 = and(T_607, T_626) - s2_disparity[0] := T_627 - node T_629 = eq(invalidate, UInt<1>("h00")) - node T_631 = bits(s1_pgoff, 11, 6) - node T_632 = cat(UInt<1>("h01"), T_631) - node T_633 = dshr(vb_array, T_632) - node T_634 = bit(T_633, 0) - node T_635 = bit(T_634, 0) - node T_636 = and(T_629, T_635) - reg T_638 : UInt<1>, clock, reset - reg T_640 : UInt<1>, clock, reset - reg T_642 : UInt<1>, clock, reset - node T_643 = bits(tag_rdata, 39, 20) - node T_644 = and(s1_valid, rdy) - node T_646 = eq(stall, UInt<1>("h00")) - node T_647 = and(T_644, T_646) - when T_647 : - T_638 := T_636 - node T_650 = or(UInt<1>("h00"), UInt<1>("h00")) - T_640 := T_650 - T_642 := s1_tag_match[1] - skip - node T_651 = bits(T_643, 19, 0) - node T_652 = eq(T_651, s1_tag) - s1_tag_match[1] := T_652 - node T_653 = and(T_638, T_642) - s2_tag_hit[1] := T_653 - node T_656 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_657 = or(T_640, T_656) - node T_658 = and(T_638, T_657) - s2_disparity[1] := T_658 - node T_660 = eq(invalidate, UInt<1>("h00")) - node T_662 = bits(s1_pgoff, 11, 6) - node T_663 = cat(UInt<2>("h02"), T_662) - node T_664 = dshr(vb_array, T_663) - node T_665 = bit(T_664, 0) - node T_666 = bit(T_665, 0) - node T_667 = and(T_660, T_666) - reg T_669 : UInt<1>, clock, reset - reg T_671 : UInt<1>, clock, reset - reg T_673 : UInt<1>, clock, reset - node T_674 = bits(tag_rdata, 59, 40) - node T_675 = and(s1_valid, rdy) - node T_677 = eq(stall, UInt<1>("h00")) - node T_678 = and(T_675, T_677) - when T_678 : - T_669 := T_667 - node T_681 = or(UInt<1>("h00"), UInt<1>("h00")) - T_671 := T_681 - T_673 := s1_tag_match[2] - skip - node T_682 = bits(T_674, 19, 0) - node T_683 = eq(T_682, s1_tag) - s1_tag_match[2] := T_683 - node T_684 = and(T_669, T_673) - s2_tag_hit[2] := T_684 - node T_687 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_688 = or(T_671, T_687) - node T_689 = and(T_669, T_688) - s2_disparity[2] := T_689 - node T_691 = eq(invalidate, UInt<1>("h00")) - node T_693 = bits(s1_pgoff, 11, 6) - node T_694 = cat(UInt<2>("h03"), T_693) - node T_695 = dshr(vb_array, T_694) - node T_696 = bit(T_695, 0) - node T_697 = bit(T_696, 0) - node T_698 = and(T_691, T_697) - reg T_700 : UInt<1>, clock, reset - reg T_702 : UInt<1>, clock, reset - reg T_704 : UInt<1>, clock, reset - node T_705 = bits(tag_rdata, 79, 60) - node T_706 = and(s1_valid, rdy) - node T_708 = eq(stall, UInt<1>("h00")) - node T_709 = and(T_706, T_708) - when T_709 : - T_700 := T_698 - node T_712 = or(UInt<1>("h00"), UInt<1>("h00")) - T_702 := T_712 - T_704 := s1_tag_match[3] - skip - node T_713 = bits(T_705, 19, 0) - node T_714 = eq(T_713, s1_tag) - s1_tag_match[3] := T_714 - node T_715 = and(T_700, T_704) - s2_tag_hit[3] := T_715 - node T_718 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_719 = or(T_702, T_718) - node T_720 = and(T_700, T_719) - s2_disparity[3] := T_720 - node T_721 = or(s2_tag_hit[0], s2_tag_hit[1]) - node T_722 = or(T_721, s2_tag_hit[2]) - node T_723 = or(T_722, s2_tag_hit[3]) - node T_724 = or(s2_disparity[0], s2_disparity[1]) - node T_725 = or(T_724, s2_disparity[2]) - node T_726 = or(T_725, s2_disparity[3]) - node T_728 = eq(T_726, UInt<1>("h00")) - node T_729 = and(T_723, T_728) - s2_any_tag_hit := T_729 - cmem T_732 : UInt<128>[256], clock - node T_734 = eq(repl_way, UInt<1>("h00")) - node T_735 = and(T_942.out.valid, T_734) - when T_735 : - node T_736 = cat(s2_idx, refill_cnt) - infer accessor T_737 = T_732[T_736] - T_737 := T_942.out.bits.data - skip - node T_738 = bits(s0_pgoff, 11, 4) - node T_740 = eq(T_735, UInt<1>("h00")) - node T_741 = and(T_740, s0_valid) - reg T_742 : UInt<8>, clock, reset - when T_741 : - T_742 := T_738 - skip - infer accessor T_743 = T_732[T_742] - node T_744 = and(s1_valid, rdy) - node T_746 = eq(stall, UInt<1>("h00")) - node T_747 = and(T_744, T_746) - node T_749 = or(UInt<1>("h00"), s1_tag_match[0]) - node T_750 = and(T_747, T_749) - when T_750 : - s2_dout[0] := T_743 - skip - cmem T_753 : UInt<128>[256], clock - node T_755 = eq(repl_way, UInt<1>("h01")) - node T_756 = and(T_942.out.valid, T_755) - when T_756 : - node T_757 = cat(s2_idx, refill_cnt) - infer accessor T_758 = T_753[T_757] - T_758 := T_942.out.bits.data - skip - node T_759 = bits(s0_pgoff, 11, 4) - node T_761 = eq(T_756, UInt<1>("h00")) - node T_762 = and(T_761, s0_valid) - reg T_763 : UInt<8>, clock, reset - when T_762 : - T_763 := T_759 - skip - infer accessor T_764 = T_753[T_763] - node T_765 = and(s1_valid, rdy) - node T_767 = eq(stall, UInt<1>("h00")) - node T_768 = and(T_765, T_767) - node T_770 = or(UInt<1>("h00"), s1_tag_match[1]) - node T_771 = and(T_768, T_770) - when T_771 : - s2_dout[1] := T_764 - skip - cmem T_774 : UInt<128>[256], clock - node T_776 = eq(repl_way, UInt<2>("h02")) - node T_777 = and(T_942.out.valid, T_776) - when T_777 : - node T_778 = cat(s2_idx, refill_cnt) - infer accessor T_779 = T_774[T_778] - T_779 := T_942.out.bits.data - skip - node T_780 = bits(s0_pgoff, 11, 4) - node T_782 = eq(T_777, UInt<1>("h00")) - node T_783 = and(T_782, s0_valid) - reg T_784 : UInt<8>, clock, reset - when T_783 : - T_784 := T_780 - skip - infer accessor T_785 = T_774[T_784] - node T_786 = and(s1_valid, rdy) - node T_788 = eq(stall, UInt<1>("h00")) - node T_789 = and(T_786, T_788) - node T_791 = or(UInt<1>("h00"), s1_tag_match[2]) - node T_792 = and(T_789, T_791) - when T_792 : - s2_dout[2] := T_785 - skip - cmem T_795 : UInt<128>[256], clock - node T_797 = eq(repl_way, UInt<2>("h03")) - node T_798 = and(T_942.out.valid, T_797) - when T_798 : - node T_799 = cat(s2_idx, refill_cnt) - infer accessor T_800 = T_795[T_799] - T_800 := T_942.out.bits.data - skip - node T_801 = bits(s0_pgoff, 11, 4) - node T_803 = eq(T_798, UInt<1>("h00")) - node T_804 = and(T_803, s0_valid) - reg T_805 : UInt<8>, clock, reset - when T_804 : - T_805 := T_801 - skip - infer accessor T_806 = T_795[T_805] - node T_807 = and(s1_valid, rdy) - node T_809 = eq(stall, UInt<1>("h00")) - node T_810 = and(T_807, T_809) - node T_812 = or(UInt<1>("h00"), s1_tag_match[3]) - node T_813 = and(T_810, T_812) - when T_813 : - s2_dout[3] := T_806 - skip - node T_814 = bits(s2_offset, 3, 2) - node T_815 = shl(T_814, 5) - node T_816 = dshr(s2_dout[0], T_815) - node T_817 = bits(T_816, 31, 0) - node T_818 = bits(s2_offset, 3, 2) - node T_819 = shl(T_818, 5) - node T_820 = dshr(s2_dout[1], T_819) - node T_821 = bits(T_820, 31, 0) - node T_822 = bits(s2_offset, 3, 2) - node T_823 = shl(T_822, 5) - node T_824 = dshr(s2_dout[2], T_823) - node T_825 = bits(T_824, 31, 0) - node T_826 = bits(s2_offset, 3, 2) - node T_827 = shl(T_826, 5) - node T_828 = dshr(s2_dout[3], T_827) - node T_829 = bits(T_828, 31, 0) - node T_831 = mux(s2_tag_hit[0], T_817, UInt<1>("h00")) - node T_833 = mux(s2_tag_hit[1], T_821, UInt<1>("h00")) - node T_835 = mux(s2_tag_hit[2], T_825, UInt<1>("h00")) - node T_837 = mux(s2_tag_hit[3], T_829, UInt<1>("h00")) - node T_839 = or(T_831, T_833) - node T_840 = or(T_839, T_835) - node T_841 = or(T_840, T_837) - wire T_842 : UInt<32> - T_842 := UInt<1>("h00") - T_842 := T_841 - resp.bits.data := T_842 - node T_845 = mux(s2_tag_hit[0], s2_dout[0], UInt<1>("h00")) - node T_847 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>("h00")) - node T_849 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>("h00")) - node T_851 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>("h00")) - node T_853 = or(T_845, T_847) - node T_854 = or(T_853, T_849) - node T_855 = or(T_854, T_851) - wire T_856 : UInt<128> - T_856 := UInt<1>("h00") - T_856 := T_855 - resp.bits.datablock := T_856 - resp.valid := s2_hit - node T_858 = eq(state, UInt<1>("h01")) - mem_1.acquire.valid := T_858 - node T_859 = shr(s2_addr, 6) - node T_864 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_865 = cat(UInt<3>("h07"), T_864) - wire T_899 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_899.union := UInt<1>("h00") - T_899.a_type := UInt<1>("h00") - T_899.is_builtin_type := UInt<1>("h00") - T_899.data := UInt<1>("h00") - T_899.addr_beat := UInt<1>("h00") - T_899.client_xact_id := UInt<1>("h00") - T_899.addr_block := UInt<1>("h00") - T_899.is_builtin_type := UInt<1>("h01") - T_899.a_type := UInt<3>("h01") - T_899.client_xact_id := UInt<1>("h00") - T_899.addr_block := T_859 - T_899.addr_beat := UInt<1>("h00") - T_899.data := UInt<1>("h00") - T_899.union := T_865 - mem_1.acquire.bits <> T_899 - node T_937 = eq(UInt<1>("h00"), state) - when T_937 : - when s2_miss : - state := UInt<1>("h01") - skip - invalidated := UInt<1>("h00") - skip - node T_939 = eq(UInt<1>("h01"), state) - when T_939 : - when mem_1.acquire.ready : - state := UInt<2>("h02") - skip - skip - node T_940 = eq(UInt<2>("h02"), state) - when T_940 : - when mem_1.grant.valid : - state := UInt<2>("h03") - skip - skip - node T_941 = eq(UInt<2>("h03"), state) - when T_941 : - when refill_done : - state := UInt<1>("h00") - skip - skip - - module RocketCAM : - input write_addr : UInt<3> - input write_tag : UInt<34> - input write : UInt<1> - output valid_bits : UInt<8> - output hits : UInt<8> - output hit : UInt<1> - input tag : UInt<34> - input clear_mask : UInt<8> - input clear : UInt<1> - input clock : Clock - input reset : UInt<1> - - valid_bits := UInt<1>("h00") - hits := UInt<1>("h00") - hit := UInt<1>("h00") - cmem cam_tags : UInt<34>[8], clock - reg vb_array : UInt<8>, clock, reset - onreset vb_array := UInt<8>("h00") - when write : - node T_20 = dshl(UInt<1>("h01"), write_addr) - node T_21 = or(vb_array, T_20) - node T_22 = not(vb_array) - node T_23 = or(T_22, T_20) - node T_24 = not(T_23) - node T_25 = mux(UInt<1>("h01"), T_21, T_24) - vb_array := T_25 - infer accessor T_26 = cam_tags[write_addr] - T_26 := write_tag - skip - when clear : - node T_27 = not(clear_mask) - node T_28 = and(vb_array, T_27) - vb_array := T_28 - skip - node T_29 = bit(vb_array, 0) - infer accessor T_31 = cam_tags[UInt<1>("h00")] - node T_32 = eq(T_31, tag) - node T_33 = and(T_29, T_32) - node T_34 = bit(vb_array, 1) - infer accessor T_36 = cam_tags[UInt<1>("h01")] - node T_37 = eq(T_36, tag) - node T_38 = and(T_34, T_37) - node T_39 = bit(vb_array, 2) - infer accessor T_41 = cam_tags[UInt<2>("h02")] - node T_42 = eq(T_41, tag) - node T_43 = and(T_39, T_42) - node T_44 = bit(vb_array, 3) - infer accessor T_46 = cam_tags[UInt<2>("h03")] - node T_47 = eq(T_46, tag) - node T_48 = and(T_44, T_47) - node T_49 = bit(vb_array, 4) - infer accessor T_51 = cam_tags[UInt<3>("h04")] - node T_52 = eq(T_51, tag) - node T_53 = and(T_49, T_52) - node T_54 = bit(vb_array, 5) - infer accessor T_56 = cam_tags[UInt<3>("h05")] - node T_57 = eq(T_56, tag) - node T_58 = and(T_54, T_57) - node T_59 = bit(vb_array, 6) - infer accessor T_61 = cam_tags[UInt<3>("h06")] - node T_62 = eq(T_61, tag) - node T_63 = and(T_59, T_62) - node T_64 = bit(vb_array, 7) - infer accessor T_66 = cam_tags[UInt<3>("h07")] - node T_67 = eq(T_66, tag) - node T_68 = and(T_64, T_67) - valid_bits := vb_array - wire T_70 : UInt<1>[8] - T_70[0] := T_33 - T_70[1] := T_38 - T_70[2] := T_43 - T_70[3] := T_48 - T_70[4] := T_53 - T_70[5] := T_58 - T_70[6] := T_63 - T_70[7] := T_68 - node T_80 = cat(T_70[7], T_70[6]) - node T_81 = cat(T_70[5], T_70[4]) - node T_82 = cat(T_80, T_81) - node T_83 = cat(T_70[3], T_70[2]) - node T_84 = cat(T_70[1], T_70[0]) - node T_85 = cat(T_83, T_84) - node T_86 = cat(T_82, T_85) - hits := T_86 - node T_88 = neq(hits, UInt<1>("h00")) - hit := T_88 - - module TLB : - output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} - output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>} - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - ptw.req.bits.fetch := UInt<1>("h00") - ptw.req.bits.store := UInt<1>("h00") - ptw.req.bits.prv := UInt<1>("h00") - ptw.req.bits.addr := UInt<1>("h00") - ptw.req.valid := UInt<1>("h00") - resp.hit_idx := UInt<1>("h00") - resp.xcpt_if := UInt<1>("h00") - resp.xcpt_st := UInt<1>("h00") - resp.xcpt_ld := UInt<1>("h00") - resp.ppn := UInt<1>("h00") - resp.miss := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg r_refill_tag : UInt, clock, reset - reg r_refill_waddr : UInt, clock, reset - reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset - inst tag_cam of RocketCAM - tag_cam.write_addr := UInt<1>("h00") - tag_cam.write_tag := UInt<1>("h00") - tag_cam.write := UInt<1>("h00") - tag_cam.tag := UInt<1>("h00") - tag_cam.clear_mask := UInt<1>("h00") - tag_cam.clear := UInt<1>("h00") - tag_cam.reset := UInt<1>("h00") - tag_cam.clock := clock - tag_cam.reset := reset - cmem tag_ram : UInt<20>[8], clock - node lookup_tag = cat(req.bits.asid, req.bits.vpn) - tag_cam.tag := lookup_tag - node T_181 = eq(state, UInt<2>("h02")) - node T_182 = and(T_181, ptw.resp.valid) - tag_cam.write := T_182 - tag_cam.write_tag := r_refill_tag - tag_cam.write_addr := r_refill_waddr - node T_183 = bits(tag_cam.hits, 7, 4) - node T_184 = bits(tag_cam.hits, 3, 0) - node T_186 = neq(T_183, UInt<1>("h00")) - node T_187 = or(T_183, T_184) - node T_188 = bits(T_187, 3, 2) - node T_189 = bits(T_187, 1, 0) - node T_191 = neq(T_188, UInt<1>("h00")) - node T_192 = or(T_188, T_189) - node T_193 = bit(T_192, 1) - node T_194 = cat(T_191, T_193) - node tag_hit_addr = cat(T_186, T_194) - reg valid_array : UInt<1>[8], clock, reset - reg ur_array : UInt<1>[8], clock, reset - reg uw_array : UInt<1>[8], clock, reset - reg ux_array : UInt<1>[8], clock, reset - reg sr_array : UInt<1>[8], clock, reset - reg sw_array : UInt<1>[8], clock, reset - reg sx_array : UInt<1>[8], clock, reset - reg dirty_array : UInt<1>[8], clock, reset - when ptw.resp.valid : - infer accessor T_388 = tag_ram[r_refill_waddr] - T_388 := ptw.resp.bits.pte.ppn - infer accessor T_389 = valid_array[r_refill_waddr] - node T_391 = eq(ptw.resp.bits.error, UInt<1>("h00")) - T_389 := T_391 - infer accessor T_392 = ur_array[r_refill_waddr] - node T_394 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_395 = and(ptw.resp.bits.pte.v, T_394) - node T_397 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_398 = and(T_395, T_397) - node T_400 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_401 = and(T_398, T_400) - T_392 := T_401 - infer accessor T_402 = uw_array[r_refill_waddr] - node T_404 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_405 = and(ptw.resp.bits.pte.v, T_404) - node T_407 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_408 = and(T_405, T_407) - node T_409 = bit(ptw.resp.bits.pte.typ, 0) - node T_410 = and(T_408, T_409) - node T_412 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_413 = and(T_410, T_412) - T_402 := T_413 - infer accessor T_414 = ux_array[r_refill_waddr] - node T_416 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_417 = and(ptw.resp.bits.pte.v, T_416) - node T_419 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_420 = and(T_417, T_419) - node T_421 = bit(ptw.resp.bits.pte.typ, 1) - node T_422 = and(T_420, T_421) - node T_424 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_425 = and(T_422, T_424) - T_414 := T_425 - infer accessor T_426 = sr_array[r_refill_waddr] - node T_428 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_429 = and(ptw.resp.bits.pte.v, T_428) - node T_431 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_432 = and(T_429, T_431) - T_426 := T_432 - infer accessor T_433 = sw_array[r_refill_waddr] - node T_435 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_436 = and(ptw.resp.bits.pte.v, T_435) - node T_437 = bit(ptw.resp.bits.pte.typ, 0) - node T_438 = and(T_436, T_437) - node T_440 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_441 = and(T_438, T_440) - T_433 := T_441 - infer accessor T_442 = sx_array[r_refill_waddr] - node T_444 = geq(ptw.resp.bits.pte.typ, UInt<3>("h04")) - node T_445 = and(ptw.resp.bits.pte.v, T_444) - node T_446 = bit(ptw.resp.bits.pte.typ, 1) - node T_447 = and(T_445, T_446) - node T_449 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_450 = and(T_447, T_449) - T_442 := T_450 - infer accessor T_451 = dirty_array[r_refill_waddr] - T_451 := ptw.resp.bits.pte.d - skip - node T_452 = not(tag_cam.valid_bits) - node T_454 = eq(T_452, UInt<1>("h00")) - node has_invalid_entry = eq(T_454, UInt<1>("h00")) - node T_457 = not(tag_cam.valid_bits) - node T_458 = bit(T_457, 0) - node T_459 = bit(T_457, 1) - node T_460 = bit(T_457, 2) - node T_461 = bit(T_457, 3) - node T_462 = bit(T_457, 4) - node T_463 = bit(T_457, 5) - node T_464 = bit(T_457, 6) - node T_465 = bit(T_457, 7) - wire T_467 : UInt<1>[8] - T_467[0] := T_458 - T_467[1] := T_459 - T_467[2] := T_460 - T_467[3] := T_461 - T_467[4] := T_462 - T_467[5] := T_463 - T_467[6] := T_464 - T_467[7] := T_465 - node T_485 = mux(T_467[6], UInt<3>("h06"), UInt<3>("h07")) - node T_486 = mux(T_467[5], UInt<3>("h05"), T_485) - node T_487 = mux(T_467[4], UInt<3>("h04"), T_486) - node T_488 = mux(T_467[3], UInt<2>("h03"), T_487) - node T_489 = mux(T_467[2], UInt<2>("h02"), T_488) - node T_490 = mux(T_467[1], UInt<1>("h01"), T_489) - node invalid_entry = mux(T_467[0], UInt<1>("h00"), T_490) - reg T_493 : UInt<8>, clock, reset - node T_495 = dshr(T_493, UInt<1>("h01")) - node T_496 = bit(T_495, 0) - node T_497 = cat(UInt<1>("h01"), T_496) - node T_498 = dshr(T_493, T_497) - node T_499 = bit(T_498, 0) - node T_500 = cat(T_497, T_499) - node T_501 = dshr(T_493, T_500) - node T_502 = bit(T_501, 0) - node T_503 = cat(T_500, T_502) - node T_504 = bits(T_503, 2, 0) - node repl_waddr = mux(has_invalid_entry, invalid_entry, T_504) - node T_507 = eq(req.bits.instruction, UInt<1>("h00")) - node T_508 = and(ptw.status.mprv, T_507) - node priv = mux(T_508, ptw.status.prv1, ptw.status.prv) - node priv_s = eq(priv, UInt<1>("h01")) - node priv_uses_vm = leq(priv, UInt<1>("h01")) - node T_536 = eq(r_req.store, UInt<1>("h00")) - node T_537 = or(r_req.instruction, r_req.store) - node T_539 = eq(T_537, UInt<1>("h00")) - node T_540 = cat(r_req.store, T_539) - node req_xwr = cat(T_536, T_540) - node T_542 = cat(sr_array[7], sr_array[6]) - node T_543 = cat(sr_array[5], sr_array[4]) - node T_544 = cat(T_542, T_543) - node T_545 = cat(sr_array[3], sr_array[2]) - node T_546 = cat(sr_array[1], sr_array[0]) - node T_547 = cat(T_545, T_546) - node T_548 = cat(T_544, T_547) - node T_549 = cat(ur_array[7], ur_array[6]) - node T_550 = cat(ur_array[5], ur_array[4]) - node T_551 = cat(T_549, T_550) - node T_552 = cat(ur_array[3], ur_array[2]) - node T_553 = cat(ur_array[1], ur_array[0]) - node T_554 = cat(T_552, T_553) - node T_555 = cat(T_551, T_554) - node r_array = mux(priv_s, T_548, T_555) - node T_557 = cat(sw_array[7], sw_array[6]) - node T_558 = cat(sw_array[5], sw_array[4]) - node T_559 = cat(T_557, T_558) - node T_560 = cat(sw_array[3], sw_array[2]) - node T_561 = cat(sw_array[1], sw_array[0]) - node T_562 = cat(T_560, T_561) - node T_563 = cat(T_559, T_562) - node T_564 = cat(uw_array[7], uw_array[6]) - node T_565 = cat(uw_array[5], uw_array[4]) - node T_566 = cat(T_564, T_565) - node T_567 = cat(uw_array[3], uw_array[2]) - node T_568 = cat(uw_array[1], uw_array[0]) - node T_569 = cat(T_567, T_568) - node T_570 = cat(T_566, T_569) - node w_array = mux(priv_s, T_563, T_570) - node T_572 = cat(sx_array[7], sx_array[6]) - node T_573 = cat(sx_array[5], sx_array[4]) - node T_574 = cat(T_572, T_573) - node T_575 = cat(sx_array[3], sx_array[2]) - node T_576 = cat(sx_array[1], sx_array[0]) - node T_577 = cat(T_575, T_576) - node T_578 = cat(T_574, T_577) - node T_579 = cat(ux_array[7], ux_array[6]) - node T_580 = cat(ux_array[5], ux_array[4]) - node T_581 = cat(T_579, T_580) - node T_582 = cat(ux_array[3], ux_array[2]) - node T_583 = cat(ux_array[1], ux_array[0]) - node T_584 = cat(T_582, T_583) - node T_585 = cat(T_581, T_584) - node x_array = mux(priv_s, T_578, T_585) - node T_587 = bit(ptw.status.vm, 3) - node vm_enabled = and(T_587, priv_uses_vm) - node T_589 = bit(req.bits.vpn, 27) - node T_590 = bit(req.bits.vpn, 26) - node bad_va = neq(T_589, T_590) - node T_592 = cat(dirty_array[7], dirty_array[6]) - node T_593 = cat(dirty_array[5], dirty_array[4]) - node T_594 = cat(T_592, T_593) - node T_595 = cat(dirty_array[3], dirty_array[2]) - node T_596 = cat(dirty_array[1], dirty_array[0]) - node T_597 = cat(T_595, T_596) - node T_598 = cat(T_594, T_597) - node T_600 = mux(req.bits.store, w_array, UInt<1>("h00")) - node T_601 = not(T_600) - node T_602 = or(T_598, T_601) - node tag_hits = and(tag_cam.hits, T_602) - node tag_hit = neq(tag_hits, UInt<1>("h00")) - node tlb_hit = and(vm_enabled, tag_hit) - node T_608 = eq(tag_hit, UInt<1>("h00")) - node T_609 = and(vm_enabled, T_608) - node T_611 = eq(bad_va, UInt<1>("h00")) - node tlb_miss = and(T_609, T_611) - node T_613 = and(req.valid, tlb_hit) - when T_613 : - node T_614 = bits(tag_cam.hits, 7, 4) - node T_615 = bits(tag_cam.hits, 3, 0) - node T_617 = neq(T_614, UInt<1>("h00")) - node T_618 = or(T_614, T_615) - node T_619 = bits(T_618, 3, 2) - node T_620 = bits(T_618, 1, 0) - node T_622 = neq(T_619, UInt<1>("h00")) - node T_623 = or(T_619, T_620) - node T_624 = bit(T_623, 1) - node T_625 = cat(T_622, T_624) - node T_626 = cat(T_617, T_625) - node T_628 = bit(T_626, 2) - node T_630 = dshl(UInt<8>("h01"), UInt<1>("h01")) - node T_631 = bits(T_630, 7, 0) - node T_632 = not(T_631) - node T_633 = and(T_493, T_632) - node T_635 = mux(T_628, UInt<1>("h00"), T_631) - node T_636 = or(T_633, T_635) - node T_637 = cat(UInt<1>("h01"), T_628) - node T_638 = bit(T_626, 1) - node T_640 = dshl(UInt<8>("h01"), T_637) - node T_641 = bits(T_640, 7, 0) - node T_642 = not(T_641) - node T_643 = and(T_636, T_642) - node T_645 = mux(T_638, UInt<1>("h00"), T_641) - node T_646 = or(T_643, T_645) - node T_647 = cat(T_637, T_638) - node T_648 = bit(T_626, 0) - node T_650 = dshl(UInt<8>("h01"), T_647) - node T_651 = bits(T_650, 7, 0) - node T_652 = not(T_651) - node T_653 = and(T_646, T_652) - node T_655 = mux(T_648, UInt<1>("h00"), T_651) - node T_656 = or(T_653, T_655) - node T_657 = cat(T_647, T_648) - T_493 := T_656 - skip - node T_658 = eq(state, UInt<1>("h00")) - req.ready := T_658 - node T_659 = and(r_array, tag_cam.hits) - node T_661 = neq(T_659, UInt<1>("h00")) - node T_663 = eq(T_661, UInt<1>("h00")) - node T_664 = and(tlb_hit, T_663) - node T_665 = or(bad_va, T_664) - resp.xcpt_ld := T_665 - node T_666 = and(w_array, tag_cam.hits) - node T_668 = neq(T_666, UInt<1>("h00")) - node T_670 = eq(T_668, UInt<1>("h00")) - node T_671 = and(tlb_hit, T_670) - node T_672 = or(bad_va, T_671) - resp.xcpt_st := T_672 - node T_673 = and(x_array, tag_cam.hits) - node T_675 = neq(T_673, UInt<1>("h00")) - node T_677 = eq(T_675, UInt<1>("h00")) - node T_678 = and(tlb_hit, T_677) - node T_679 = or(bad_va, T_678) - resp.xcpt_if := T_679 - resp.miss := tlb_miss - node T_681 = eq(req.bits.passthrough, UInt<1>("h00")) - node T_682 = and(vm_enabled, T_681) - node T_683 = bit(tag_cam.hits, 0) - node T_684 = bit(tag_cam.hits, 1) - node T_685 = bit(tag_cam.hits, 2) - node T_686 = bit(tag_cam.hits, 3) - node T_687 = bit(tag_cam.hits, 4) - node T_688 = bit(tag_cam.hits, 5) - node T_689 = bit(tag_cam.hits, 6) - node T_690 = bit(tag_cam.hits, 7) - infer accessor T_692 = tag_ram[UInt<1>("h00")] - infer accessor T_694 = tag_ram[UInt<1>("h01")] - infer accessor T_696 = tag_ram[UInt<2>("h02")] - infer accessor T_698 = tag_ram[UInt<2>("h03")] - infer accessor T_700 = tag_ram[UInt<3>("h04")] - infer accessor T_702 = tag_ram[UInt<3>("h05")] - infer accessor T_704 = tag_ram[UInt<3>("h06")] - infer accessor T_706 = tag_ram[UInt<3>("h07")] - node T_708 = mux(T_683, T_692, UInt<1>("h00")) - node T_710 = mux(T_684, T_694, UInt<1>("h00")) - node T_712 = mux(T_685, T_696, UInt<1>("h00")) - node T_714 = mux(T_686, T_698, UInt<1>("h00")) - node T_716 = mux(T_687, T_700, UInt<1>("h00")) - node T_718 = mux(T_688, T_702, UInt<1>("h00")) - node T_720 = mux(T_689, T_704, UInt<1>("h00")) - node T_722 = mux(T_690, T_706, UInt<1>("h00")) - node T_724 = or(T_708, T_710) - node T_725 = or(T_724, T_712) - node T_726 = or(T_725, T_714) - node T_727 = or(T_726, T_716) - node T_728 = or(T_727, T_718) - node T_729 = or(T_728, T_720) - node T_730 = or(T_729, T_722) - wire T_731 : UInt<20> - T_731 := UInt<1>("h00") - T_731 := T_730 - node T_733 = bits(req.bits.vpn, 19, 0) - node T_734 = mux(T_682, T_731, T_733) - resp.ppn := T_734 - resp.hit_idx := tag_cam.hits - node T_735 = and(req.ready, req.valid) - node T_736 = or(ptw.invalidate, T_735) - tag_cam.clear := T_736 - node T_737 = cat(valid_array[7], valid_array[6]) - node T_738 = cat(valid_array[5], valid_array[4]) - node T_739 = cat(T_737, T_738) - node T_740 = cat(valid_array[3], valid_array[2]) - node T_741 = cat(valid_array[1], valid_array[0]) - node T_742 = cat(T_740, T_741) - node T_743 = cat(T_739, T_742) - node T_744 = not(T_743) - node T_745 = not(tag_hits) - node T_746 = and(tag_cam.hits, T_745) - node T_747 = or(T_744, T_746) - tag_cam.clear_mask := T_747 - when ptw.invalidate : - node T_749 = not(UInt<8>("h00")) - tag_cam.clear_mask := T_749 - skip - node T_750 = eq(state, UInt<1>("h01")) - ptw.req.valid := T_750 - ptw.req.bits.addr := r_refill_tag - ptw.req.bits.prv := ptw.status.prv - ptw.req.bits.store := r_req.store - ptw.req.bits.fetch := r_req.instruction - node T_751 = and(req.ready, req.valid) - node T_752 = and(T_751, tlb_miss) - when T_752 : - state := UInt<1>("h01") - r_refill_tag := lookup_tag - r_refill_waddr := repl_waddr - r_req <> req.bits - skip - node T_753 = eq(state, UInt<1>("h01")) - when T_753 : - when ptw.invalidate : - state := UInt<1>("h00") - skip - when ptw.req.ready : - state := UInt<2>("h02") - when ptw.invalidate : - state := UInt<2>("h03") - skip - skip - skip - node T_754 = eq(state, UInt<2>("h02")) - node T_755 = and(T_754, ptw.invalidate) - when T_755 : - state := UInt<2>("h03") - skip - when ptw.resp.valid : - state := UInt<1>("h00") - skip - - module Frontend : - output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} - input cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>} - input clock : Clock - input reset : UInt<1> - - mem_1.grant.ready := UInt<1>("h00") - mem_1.acquire.bits.union := UInt<1>("h00") - mem_1.acquire.bits.a_type := UInt<1>("h00") - mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") - mem_1.acquire.bits.data := UInt<1>("h00") - mem_1.acquire.bits.addr_beat := UInt<1>("h00") - mem_1.acquire.bits.client_xact_id := UInt<1>("h00") - mem_1.acquire.bits.addr_block := UInt<1>("h00") - mem_1.acquire.valid := UInt<1>("h00") - ptw.req.bits.fetch := UInt<1>("h00") - ptw.req.bits.store := UInt<1>("h00") - ptw.req.bits.prv := UInt<1>("h00") - ptw.req.bits.addr := UInt<1>("h00") - ptw.req.valid := UInt<1>("h00") - cpu.npc := UInt<1>("h00") - cpu.btb_resp.bits.bht.value := UInt<1>("h00") - cpu.btb_resp.bits.bht.history := UInt<1>("h00") - cpu.btb_resp.bits.entry := UInt<1>("h00") - cpu.btb_resp.bits.target := UInt<1>("h00") - cpu.btb_resp.bits.bridx := UInt<1>("h00") - cpu.btb_resp.bits.mask := UInt<1>("h00") - cpu.btb_resp.bits.taken := UInt<1>("h00") - cpu.btb_resp.valid := UInt<1>("h00") - cpu.resp.bits.xcpt_if := UInt<1>("h00") - cpu.resp.bits.mask := UInt<1>("h00") - cpu.resp.bits.data[0] := UInt<1>("h00") - cpu.resp.bits.pc := UInt<1>("h00") - cpu.resp.valid := UInt<1>("h00") - inst btb of BTB - btb.invalidate := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.entry := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.target := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.mask := UInt<1>("h00") - btb.ras_update.bits.prediction.bits.taken := UInt<1>("h00") - btb.ras_update.bits.prediction.valid := UInt<1>("h00") - btb.ras_update.bits.returnAddr := UInt<1>("h00") - btb.ras_update.bits.isReturn := UInt<1>("h00") - btb.ras_update.bits.isCall := UInt<1>("h00") - btb.ras_update.valid := UInt<1>("h00") - btb.bht_update.bits.mispredict := UInt<1>("h00") - btb.bht_update.bits.taken := UInt<1>("h00") - btb.bht_update.bits.pc := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.entry := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.target := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.mask := UInt<1>("h00") - btb.bht_update.bits.prediction.bits.taken := UInt<1>("h00") - btb.bht_update.bits.prediction.valid := UInt<1>("h00") - btb.bht_update.valid := UInt<1>("h00") - btb.btb_update.bits.br_pc := UInt<1>("h00") - btb.btb_update.bits.isReturn := UInt<1>("h00") - btb.btb_update.bits.isJump := UInt<1>("h00") - btb.btb_update.bits.taken := UInt<1>("h00") - btb.btb_update.bits.target := UInt<1>("h00") - btb.btb_update.bits.pc := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.entry := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.target := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.mask := UInt<1>("h00") - btb.btb_update.bits.prediction.bits.taken := UInt<1>("h00") - btb.btb_update.bits.prediction.valid := UInt<1>("h00") - btb.btb_update.valid := UInt<1>("h00") - btb.req.bits.addr := UInt<1>("h00") - btb.req.valid := UInt<1>("h00") - btb.reset := UInt<1>("h00") - btb.clock := clock - btb.reset := reset - inst icache of ICache - icache.mem_1.grant.bits.g_type := UInt<1>("h00") - icache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") - icache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") - icache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") - icache.mem_1.grant.bits.data := UInt<1>("h00") - icache.mem_1.grant.bits.addr_beat := UInt<1>("h00") - icache.mem_1.grant.valid := UInt<1>("h00") - icache.mem_1.acquire.ready := UInt<1>("h00") - icache.invalidate := UInt<1>("h00") - icache.resp.ready := UInt<1>("h00") - icache.req.bits.kill := UInt<1>("h00") - icache.req.bits.ppn := UInt<1>("h00") - icache.req.bits.idx := UInt<1>("h00") - icache.req.valid := UInt<1>("h00") - icache.reset := UInt<1>("h00") - icache.clock := clock - icache.reset := reset - inst tlb of TLB - tlb.ptw.invalidate := UInt<1>("h00") - tlb.ptw.status.ie := UInt<1>("h00") - tlb.ptw.status.prv := UInt<1>("h00") - tlb.ptw.status.ie1 := UInt<1>("h00") - tlb.ptw.status.prv1 := UInt<1>("h00") - tlb.ptw.status.ie2 := UInt<1>("h00") - tlb.ptw.status.prv2 := UInt<1>("h00") - tlb.ptw.status.ie3 := UInt<1>("h00") - tlb.ptw.status.prv3 := UInt<1>("h00") - tlb.ptw.status.fs := UInt<1>("h00") - tlb.ptw.status.xs := UInt<1>("h00") - tlb.ptw.status.mprv := UInt<1>("h00") - tlb.ptw.status.vm := UInt<1>("h00") - tlb.ptw.status.zero1 := UInt<1>("h00") - tlb.ptw.status.sd_rv32 := UInt<1>("h00") - tlb.ptw.status.zero2 := UInt<1>("h00") - tlb.ptw.status.sd := UInt<1>("h00") - tlb.ptw.resp.bits.pte.v := UInt<1>("h00") - tlb.ptw.resp.bits.pte.typ := UInt<1>("h00") - tlb.ptw.resp.bits.pte.r := UInt<1>("h00") - tlb.ptw.resp.bits.pte.d := UInt<1>("h00") - tlb.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - tlb.ptw.resp.bits.pte.ppn := UInt<1>("h00") - tlb.ptw.resp.bits.error := UInt<1>("h00") - tlb.ptw.resp.valid := UInt<1>("h00") - tlb.ptw.req.ready := UInt<1>("h00") - tlb.req.bits.store := UInt<1>("h00") - tlb.req.bits.instruction := UInt<1>("h00") - tlb.req.bits.passthrough := UInt<1>("h00") - tlb.req.bits.vpn := UInt<1>("h00") - tlb.req.bits.asid := UInt<1>("h00") - tlb.req.valid := UInt<1>("h00") - tlb.reset := UInt<1>("h00") - tlb.clock := clock - tlb.reset := reset - reg s1_pc_ : UInt, clock, reset - node T_1322 = not(s1_pc_) - node T_1324 = or(T_1322, UInt<2>("h03")) - node s1_pc = not(T_1324) - reg s1_same_block : UInt<1>, clock, reset - reg s2_valid : UInt<1>, clock, reset - onreset s2_valid := UInt<1>("h01") - reg s2_pc : UInt, clock, reset - onreset s2_pc := UInt<10>("h0200") - reg s2_btb_resp_valid : UInt<1>, clock, reset - onreset s2_btb_resp_valid := UInt<1>("h00") - reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset - reg s2_xcpt_if : UInt<1>, clock, reset - onreset s2_xcpt_if := UInt<1>("h00") - node T_1345 = bit(btb.resp.bits.target, 38) - node btbTarget = cat(T_1345, btb.resp.bits.target) - node ntpc_0 = addw(s1_pc, UInt<3>("h04")) - node T_1349 = bit(s1_pc, 38) - node T_1350 = bit(ntpc_0, 38) - node T_1351 = and(T_1349, T_1350) - node T_1352 = bits(ntpc_0, 38, 2) - node T_1354 = cat(T_1352, UInt<2>("h00")) - node ntpc = cat(T_1351, T_1354) - node T_1357 = eq(icache.resp.valid, UInt<1>("h00")) - node icmiss = and(s2_valid, T_1357) - node predicted_npc = mux(btb.resp.bits.taken, btbTarget, ntpc) - node npc = mux(icmiss, s2_pc, predicted_npc) - node T_1362 = eq(icmiss, UInt<1>("h00")) - node T_1364 = eq(cpu.req.valid, UInt<1>("h00")) - node T_1365 = and(T_1362, T_1364) - node T_1367 = eq(btb.resp.bits.taken, UInt<1>("h00")) - node T_1368 = and(T_1365, T_1367) - node T_1370 = and(ntpc, UInt<5>("h010")) - node T_1372 = and(s1_pc, UInt<5>("h010")) - node T_1373 = eq(T_1370, T_1372) - node s0_same_block = and(T_1368, T_1373) - node T_1376 = eq(cpu.resp.ready, UInt<1>("h00")) - node stall = and(cpu.resp.valid, T_1376) - node T_1379 = eq(stall, UInt<1>("h00")) - when T_1379 : - node T_1381 = eq(tlb.resp.miss, UInt<1>("h00")) - node T_1382 = and(s0_same_block, T_1381) - s1_same_block := T_1382 - s1_pc_ := npc - node T_1384 = eq(icmiss, UInt<1>("h00")) - s2_valid := T_1384 - node T_1386 = eq(icmiss, UInt<1>("h00")) - when T_1386 : - s2_pc := s1_pc - s2_btb_resp_valid := btb.resp.valid - when btb.resp.valid : - s2_btb_resp_bits <> btb.resp.bits - skip - s2_xcpt_if := tlb.resp.xcpt_if - skip - skip - when cpu.req.valid : - s1_same_block := UInt<1>("h00") - s1_pc_ := cpu.req.bits.pc - s2_valid := UInt<1>("h00") - skip - node T_1390 = eq(stall, UInt<1>("h00")) - node T_1392 = eq(icmiss, UInt<1>("h00")) - node T_1393 = and(T_1390, T_1392) - btb.req.valid := T_1393 - btb.req.bits.addr := s1_pc - btb.btb_update <> cpu.btb_update - btb.bht_update <> cpu.bht_update - btb.ras_update <> cpu.ras_update - node T_1394 = or(cpu.invalidate, ptw.invalidate) - btb.invalidate := T_1394 - ptw <> tlb.ptw - node T_1396 = eq(stall, UInt<1>("h00")) - node T_1398 = eq(icmiss, UInt<1>("h00")) - node T_1399 = and(T_1396, T_1398) - tlb.req.valid := T_1399 - node T_1400 = shr(s1_pc, 12) - tlb.req.bits.vpn := T_1400 - tlb.req.bits.asid := UInt<1>("h00") - tlb.req.bits.passthrough := UInt<1>("h00") - tlb.req.bits.instruction := UInt<1>("h01") - tlb.req.bits.store := UInt<1>("h00") - mem_1 <> icache.mem_1 - node T_1406 = eq(stall, UInt<1>("h00")) - node T_1408 = eq(s0_same_block, UInt<1>("h00")) - node T_1409 = and(T_1406, T_1408) - icache.req.valid := T_1409 - icache.req.bits.idx := cpu.npc - icache.invalidate := cpu.invalidate - icache.req.bits.ppn := tlb.resp.ppn - node T_1410 = or(cpu.req.valid, tlb.resp.miss) - node T_1411 = or(T_1410, icmiss) - node T_1412 = or(T_1411, ptw.invalidate) - icache.req.bits.kill := T_1412 - node T_1414 = eq(stall, UInt<1>("h00")) - node T_1416 = eq(s1_same_block, UInt<1>("h00")) - node T_1417 = and(T_1414, T_1416) - icache.resp.ready := T_1417 - node T_1418 = or(s2_xcpt_if, icache.resp.valid) - node T_1419 = and(s2_valid, T_1418) - cpu.resp.valid := T_1419 - cpu.resp.bits.pc := s2_pc - node T_1420 = mux(cpu.req.valid, cpu.req.bits.pc, npc) - cpu.npc := T_1420 - node T_1421 = bits(s2_pc, 3, 2) - node T_1422 = shl(T_1421, 5) - node fetch_data = dshr(icache.resp.bits.datablock, T_1422) - node T_1424 = bits(fetch_data, 31, 0) - cpu.resp.bits.data[0] := T_1424 - node T_1426 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) - node T_1427 = mux(s2_btb_resp_valid, T_1426, UInt<2>("h03")) - cpu.resp.bits.mask := T_1427 - cpu.resp.bits.xcpt_if := s2_xcpt_if - cpu.btb_resp.valid := s2_btb_resp_valid - cpu.btb_resp.bits <> s2_btb_resp_bits - - module WritebackUnit : - output release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - input data_resp : UInt<128> - output data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} - output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - input clock : Clock - input reset : UInt<1> - - release.bits.voluntary := UInt<1>("h00") - release.bits.r_type := UInt<1>("h00") - release.bits.data := UInt<1>("h00") - release.bits.addr_beat := UInt<1>("h00") - release.bits.client_xact_id := UInt<1>("h00") - release.bits.addr_block := UInt<1>("h00") - release.valid := UInt<1>("h00") - data_req.bits.addr := UInt<1>("h00") - data_req.bits.way_en := UInt<1>("h00") - data_req.valid := UInt<1>("h00") - meta_read.bits.tag := UInt<1>("h00") - meta_read.bits.idx := UInt<1>("h00") - meta_read.valid := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg active : UInt<1>, clock, reset - onreset active := UInt<1>("h00") - reg r1_data_req_fired : UInt<1>, clock, reset - onreset r1_data_req_fired := UInt<1>("h00") - reg r2_data_req_fired : UInt<1>, clock, reset - onreset r2_data_req_fired := UInt<1>("h00") - reg data_req_cnt : UInt<3>, clock, reset - onreset data_req_cnt := UInt<3>("h00") - node T_292 = not(UInt<1>("h01")) - node beat_done = eq(T_292, UInt<1>("h00")) - node T_295 = and(release.ready, release.valid) - reg beat_cnt : UInt<2>, clock, reset - onreset beat_cnt := UInt<2>("h00") - when T_295 : - node T_299 = eq(beat_cnt, UInt<2>("h03")) - node T_301 = and(UInt<1>("h00"), T_299) - node T_304 = addw(beat_cnt, UInt<1>("h01")) - node T_305 = mux(T_301, UInt<1>("h00"), T_304) - beat_cnt := T_305 - skip - node all_beats_done = and(T_295, T_299) - reg req_1 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}, clock, reset - release.valid := UInt<1>("h00") - when active : - r1_data_req_fired := UInt<1>("h00") - r2_data_req_fired := r1_data_req_fired - node T_371 = and(data_req.ready, data_req.valid) - node T_372 = and(meta_read.ready, meta_read.valid) - node T_373 = and(T_371, T_372) - when T_373 : - r1_data_req_fired := UInt<1>("h01") - node T_376 = addw(data_req_cnt, UInt<1>("h01")) - data_req_cnt := T_376 - skip - when r2_data_req_fired : - release.valid := beat_done - when beat_done : - node T_378 = eq(release.ready, UInt<1>("h00")) - when T_378 : - r1_data_req_fired := UInt<1>("h00") - r2_data_req_fired := UInt<1>("h00") - node T_382 = and(UInt<1>("h01"), r1_data_req_fired) - node T_385 = mux(T_382, UInt<2>("h02"), UInt<1>("h01")) - node T_386 = subw(data_req_cnt, T_385) - data_req_cnt := T_386 - skip - else : - skip - skip - node T_388 = eq(r1_data_req_fired, UInt<1>("h00")) - when T_388 : - node T_390 = lt(data_req_cnt, UInt<3>("h04")) - node T_392 = eq(release.ready, UInt<1>("h00")) - node T_393 = or(T_390, T_392) - active := T_393 - skip - skip - skip - node T_394 = and(req.ready, req.valid) - when T_394 : - active := UInt<1>("h01") - data_req_cnt := UInt<1>("h00") - req_1 <> req.bits - skip - node T_398 = eq(active, UInt<1>("h00")) - req.ready := T_398 - node req_idx = bits(req_1.addr_block, 5, 0) - node T_401 = lt(data_req_cnt, UInt<3>("h04")) - node fire = and(active, T_401) - meta_read.valid := fire - meta_read.bits.idx := req_idx - node T_403 = shr(req_1.addr_block, 6) - meta_read.bits.tag := T_403 - data_req.valid := fire - data_req.bits.way_en := req_1.way_en - node T_404 = bits(data_req_cnt, 1, 0) - node T_405 = cat(req_idx, T_404) - node T_406 = shl(T_405, 4) - data_req.bits.addr := T_406 - release.bits <> req_1 - release.bits.addr_beat := beat_cnt - release.bits.data := data_resp - - module ProbeUnit : - input block_state : {state : UInt<2>} - input mshr_rdy : UInt<1> - input way_en : UInt<4> - output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - output rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - wb_req.bits.way_en := UInt<1>("h00") - wb_req.bits.voluntary := UInt<1>("h00") - wb_req.bits.r_type := UInt<1>("h00") - wb_req.bits.data := UInt<1>("h00") - wb_req.bits.addr_beat := UInt<1>("h00") - wb_req.bits.client_xact_id := UInt<1>("h00") - wb_req.bits.addr_block := UInt<1>("h00") - wb_req.valid := UInt<1>("h00") - meta_write.bits.data.coh.state := UInt<1>("h00") - meta_write.bits.data.tag := UInt<1>("h00") - meta_write.bits.way_en := UInt<1>("h00") - meta_write.bits.idx := UInt<1>("h00") - meta_write.valid := UInt<1>("h00") - meta_read.bits.tag := UInt<1>("h00") - meta_read.bits.idx := UInt<1>("h00") - meta_read.valid := UInt<1>("h00") - rep.bits.voluntary := UInt<1>("h00") - rep.bits.r_type := UInt<1>("h00") - rep.bits.data := UInt<1>("h00") - rep.bits.addr_beat := UInt<1>("h00") - rep.bits.client_xact_id := UInt<1>("h00") - rep.bits.addr_block := UInt<1>("h00") - rep.valid := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg old_coh : {state : UInt<2>}, clock, reset - reg way_en_1 : UInt, clock, reset - reg req_2 : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}, clock, reset - node tag_matches = neq(way_en_1, UInt<1>("h00")) - node T_637 = eq(state, UInt<3>("h07")) - node T_638 = and(T_637, meta_write.ready) - when T_638 : - state := UInt<1>("h00") - skip - node T_639 = eq(state, UInt<3>("h06")) - node T_640 = and(T_639, wb_req.ready) - when T_640 : - state := UInt<3>("h07") - skip - node T_641 = eq(state, UInt<3>("h05")) - node T_642 = and(T_641, wb_req.ready) - when T_642 : - state := UInt<3>("h06") - skip - node T_643 = eq(state, UInt<3>("h04")) - node T_644 = and(T_643, rep.ready) - when T_644 : - state := UInt<1>("h00") - when tag_matches : - wire T_646 : UInt<2>[1] - T_646[0] := UInt<2>("h03") - node T_649 = eq(T_646[0], old_coh.state) - node T_651 = or(UInt<1>("h00"), T_649) - node T_652 = mux(T_651, UInt<3>("h05"), UInt<3>("h07")) - state := T_652 - skip - skip - node T_653 = eq(state, UInt<2>("h03")) - when T_653 : - state := UInt<3>("h04") - old_coh <> block_state - way_en_1 := way_en - node T_655 = eq(mshr_rdy, UInt<1>("h00")) - when T_655 : - state := UInt<1>("h01") - skip - skip - node T_656 = eq(state, UInt<2>("h02")) - when T_656 : - state := UInt<2>("h03") - skip - node T_657 = eq(state, UInt<1>("h01")) - node T_658 = and(T_657, meta_read.ready) - when T_658 : - state := UInt<2>("h02") - skip - node T_659 = eq(state, UInt<1>("h00")) - node T_660 = and(T_659, req.valid) - when T_660 : - state := UInt<1>("h01") - req_2 <> req.bits - skip - wire T_665 : UInt<2>[1] - T_665[0] := UInt<2>("h03") - node T_668 = eq(T_665[0], old_coh.state) - node T_670 = or(UInt<1>("h00"), T_668) - node T_671 = mux(T_670, UInt<1>("h00"), UInt<2>("h03")) - node T_672 = mux(T_670, UInt<1>("h01"), UInt<3>("h04")) - node T_673 = mux(T_670, UInt<2>("h02"), UInt<3>("h05")) - node T_674 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_675 = mux(T_674, T_673, UInt<3>("h05")) - node T_676 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_677 = mux(T_676, T_672, T_675) - node T_678 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_679 = mux(T_678, T_671, T_677) - wire T_681 : UInt<2>[1] - T_681[0] := UInt<2>("h03") - node T_684 = eq(T_681[0], old_coh.state) - node T_686 = or(UInt<1>("h00"), T_684) - node T_687 = mux(T_686, UInt<1>("h00"), UInt<2>("h03")) - node T_688 = mux(T_686, UInt<1>("h01"), UInt<3>("h04")) - node T_689 = mux(T_686, UInt<2>("h02"), UInt<3>("h05")) - node T_690 = eq(UInt<5>("h013"), UInt<5>("h011")) - node T_691 = mux(T_690, T_689, UInt<3>("h05")) - node T_692 = eq(UInt<5>("h011"), UInt<5>("h011")) - node T_693 = mux(T_692, T_688, T_691) - node T_694 = eq(UInt<5>("h010"), UInt<5>("h011")) - node T_695 = mux(T_694, T_687, T_693) - wire T_697 : UInt<2>[1] - T_697[0] := UInt<2>("h03") - node T_700 = eq(T_697[0], old_coh.state) - node T_702 = or(UInt<1>("h00"), T_700) - node T_703 = mux(T_702, UInt<1>("h00"), UInt<2>("h03")) - node T_704 = mux(T_702, UInt<1>("h01"), UInt<3>("h04")) - node T_705 = mux(T_702, UInt<2>("h02"), UInt<3>("h05")) - node T_706 = eq(UInt<5>("h013"), UInt<5>("h013")) - node T_707 = mux(T_706, T_705, UInt<3>("h05")) - node T_708 = eq(UInt<5>("h011"), UInt<5>("h013")) - node T_709 = mux(T_708, T_704, T_707) - node T_710 = eq(UInt<5>("h010"), UInt<5>("h013")) - node T_711 = mux(T_710, T_703, T_709) - node T_712 = eq(UInt<2>("h02"), req_2.p_type) - node T_713 = mux(T_712, T_711, UInt<2>("h03")) - node T_714 = eq(UInt<1>("h01"), req_2.p_type) - node T_715 = mux(T_714, T_695, T_713) - node T_716 = eq(UInt<1>("h00"), req_2.p_type) - node T_717 = mux(T_716, T_679, T_715) - wire reply : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} - reply.voluntary := UInt<1>("h00") - reply.r_type := UInt<1>("h00") - reply.data := UInt<1>("h00") - reply.addr_beat := UInt<1>("h00") - reply.client_xact_id := UInt<1>("h00") - reply.addr_block := UInt<1>("h00") - reply.r_type := T_717 - reply.client_xact_id := UInt<1>("h00") - reply.addr_block := req_2.addr_block - reply.addr_beat := UInt<1>("h00") - reply.data := UInt<1>("h00") - reply.voluntary := UInt<1>("h00") - node T_785 = eq(state, UInt<1>("h00")) - req.ready := T_785 - node T_786 = eq(state, UInt<3>("h04")) - wire T_788 : UInt<2>[1] - T_788[0] := UInt<2>("h03") - node T_791 = eq(T_788[0], old_coh.state) - node T_793 = or(UInt<1>("h00"), T_791) - node T_794 = and(tag_matches, T_793) - node T_796 = eq(T_794, UInt<1>("h00")) - node T_797 = and(T_786, T_796) - rep.valid := T_797 - rep.bits <> reply - node T_798 = eq(state, UInt<1>("h01")) - meta_read.valid := T_798 - meta_read.bits.idx := req_2.addr_block - node T_799 = shr(req_2.addr_block, 6) - meta_read.bits.tag := T_799 - node T_800 = eq(state, UInt<3>("h07")) - meta_write.valid := T_800 - meta_write.bits.way_en := way_en_1 - meta_write.bits.idx := req_2.addr_block - node T_801 = shr(req_2.addr_block, 6) - meta_write.bits.data.tag := T_801 - node T_802 = eq(UInt<2>("h02"), req_2.p_type) - node T_803 = mux(T_802, old_coh.state, old_coh.state) - node T_804 = eq(UInt<1>("h01"), req_2.p_type) - node T_805 = mux(T_804, UInt<1>("h01"), T_803) - node T_806 = eq(UInt<1>("h00"), req_2.p_type) - node T_807 = mux(T_806, UInt<1>("h00"), T_805) - wire T_833 : {state : UInt<2>} - T_833.state := UInt<1>("h00") - T_833.state := T_807 - meta_write.bits.data.coh <> T_833 - node T_859 = eq(state, UInt<3>("h05")) - wb_req.valid := T_859 - wb_req.bits <> reply - wb_req.bits.way_en := way_en_1 - - module Arbiter_52 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.tag := UInt<1>("h00") - out.bits.idx := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_108 : UInt<1> - T_108 := UInt<1>("h00") - infer accessor T_110 = in[T_108] - out.valid := T_110.valid - infer accessor T_119 = in[T_108] - out.bits <> T_119.bits - chosen := T_108 - infer accessor T_128 = in[T_108] - T_128.ready := UInt<1>("h00") - node T_140 = or(UInt<1>("h00"), in[0].valid) - node T_142 = eq(T_140, UInt<1>("h00")) - node T_144 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_145 = mux(UInt<1>("h00"), T_144, UInt<1>("h01")) - node T_146 = and(T_145, out.ready) - in[0].ready := T_146 - node T_148 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_149 = mux(UInt<1>("h00"), T_148, T_142) - node T_150 = and(T_149, out.ready) - in[1].ready := T_150 - node T_153 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_154 = mux(UInt<1>("h00"), UInt<1>("h01"), T_153) - T_108 := T_154 - - module Arbiter_53 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.data.coh.state := UInt<1>("h00") - out.bits.data.tag := UInt<1>("h00") - out.bits.way_en := UInt<1>("h00") - out.bits.idx := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_702 : UInt<1> - T_702 := UInt<1>("h00") - infer accessor T_704 = in[T_702] - out.valid := T_704.valid - infer accessor T_767 = in[T_702] - out.bits <> T_767.bits - chosen := T_702 - infer accessor T_830 = in[T_702] - T_830.ready := UInt<1>("h00") - node T_896 = or(UInt<1>("h00"), in[0].valid) - node T_898 = eq(T_896, UInt<1>("h00")) - node T_900 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_901 = mux(UInt<1>("h00"), T_900, UInt<1>("h01")) - node T_902 = and(T_901, out.ready) - in[0].ready := T_902 - node T_904 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_905 = mux(UInt<1>("h00"), T_904, T_898) - node T_906 = and(T_905, out.ready) - in[1].ready := T_906 - node T_909 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_910 = mux(UInt<1>("h00"), UInt<1>("h01"), T_909) - T_702 := T_910 - - module LockingArbiter : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.union := UInt<1>("h00") - out.bits.a_type := UInt<1>("h00") - out.bits.is_builtin_type := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.addr_block := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - reg T_722 : UInt<1>, clock, reset - onreset T_722 := UInt<1>("h00") - reg T_724 : UInt, clock, reset - onreset T_724 := UInt<1>("h01") - wire T_726 : UInt<1> - T_726 := UInt<1>("h00") - infer accessor T_728 = in[T_726] - out.valid := T_728.valid - infer accessor T_793 = in[T_726] - out.bits <> T_793.bits - chosen := T_726 - infer accessor T_858 = in[T_726] - T_858.ready := UInt<1>("h00") - node T_926 = or(UInt<1>("h00"), in[0].valid) - node T_928 = eq(T_926, UInt<1>("h00")) - node T_930 = eq(T_724, UInt<1>("h00")) - node T_931 = mux(T_722, T_930, UInt<1>("h01")) - node T_932 = and(T_931, out.ready) - in[0].ready := T_932 - node T_934 = eq(T_724, UInt<1>("h01")) - node T_935 = mux(T_722, T_934, T_928) - node T_936 = and(T_935, out.ready) - in[1].ready := T_936 - reg T_938 : UInt<2>, clock, reset - onreset T_938 := UInt<2>("h00") - node T_940 = addw(T_938, UInt<1>("h01")) - node T_941 = and(out.ready, out.valid) - when T_941 : - node T_943 = and(UInt<1>("h01"), out.bits.is_builtin_type) - wire T_946 : UInt<3>[1] - T_946[0] := UInt<3>("h03") - node T_949 = eq(T_946[0], out.bits.a_type) - node T_951 = or(UInt<1>("h00"), T_949) - node T_952 = and(T_943, T_951) - when T_952 : - T_938 := T_940 - node T_954 = eq(T_722, UInt<1>("h00")) - when T_954 : - T_722 := UInt<1>("h01") - node T_956 = and(in[0].ready, in[0].valid) - node T_957 = and(in[1].ready, in[1].valid) - wire T_959 : UInt<1>[2] - T_959[0] := T_956 - T_959[1] := T_957 - node T_965 = mux(T_959[0], UInt<1>("h00"), UInt<1>("h01")) - T_724 := T_965 - skip - skip - node T_967 = eq(T_940, UInt<1>("h00")) - when T_967 : - T_722 := UInt<1>("h00") - skip - skip - node choose = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_972 = mux(T_722, T_724, choose) - T_726 := T_972 - - module Arbiter_54 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.way_en := UInt<1>("h00") - out.bits.voluntary := UInt<1>("h00") - out.bits.r_type := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.addr_block := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_724 : UInt<1> - T_724 := UInt<1>("h00") - infer accessor T_726 = in[T_724] - out.valid := T_726.valid - infer accessor T_791 = in[T_724] - out.bits <> T_791.bits - chosen := T_724 - infer accessor T_856 = in[T_724] - T_856.ready := UInt<1>("h00") - node T_924 = or(UInt<1>("h00"), in[0].valid) - node T_926 = eq(T_924, UInt<1>("h00")) - node T_928 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_929 = mux(UInt<1>("h00"), T_928, UInt<1>("h01")) - node T_930 = and(T_929, out.ready) - in[0].ready := T_930 - node T_932 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_933 = mux(UInt<1>("h00"), T_932, T_926) - node T_934 = and(T_933, out.ready) - in[1].ready := T_934 - node T_937 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_938 = mux(UInt<1>("h00"), UInt<1>("h01"), T_937) - T_724 := T_938 - - module Arbiter_55 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.sdq_id := UInt<1>("h00") - out.bits.phys := UInt<1>("h00") - out.bits.kill := UInt<1>("h00") - out.bits.typ := UInt<1>("h00") - out.bits.cmd := UInt<1>("h00") - out.bits.tag := UInt<1>("h00") - out.bits.addr := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_218 : UInt<1> - T_218 := UInt<1>("h00") - infer accessor T_220 = in[T_218] - out.valid := T_220.valid - infer accessor T_239 = in[T_218] - out.bits <> T_239.bits - chosen := T_218 - infer accessor T_258 = in[T_218] - T_258.ready := UInt<1>("h00") - node T_280 = or(UInt<1>("h00"), in[0].valid) - node T_282 = eq(T_280, UInt<1>("h00")) - node T_284 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_285 = mux(UInt<1>("h00"), T_284, UInt<1>("h01")) - node T_286 = and(T_285, out.ready) - in[0].ready := T_286 - node T_288 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_289 = mux(UInt<1>("h00"), T_288, T_282) - node T_290 = and(T_289, out.ready) - in[1].ready := T_290 - node T_293 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_294 = mux(UInt<1>("h00"), UInt<1>("h01"), T_293) - T_218 := T_294 - - module Arbiter_56 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_64 : UInt<1> - T_64 := UInt<1>("h00") - infer accessor T_66 = in[T_64] - out.valid := T_66.valid - infer accessor T_71 = in[T_64] - out.bits := T_71.bits - chosen := T_64 - infer accessor T_76 = in[T_64] - T_76.ready := UInt<1>("h00") - node T_84 = or(UInt<1>("h00"), in[0].valid) - node T_86 = eq(T_84, UInt<1>("h00")) - node T_88 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_89 = mux(UInt<1>("h00"), T_88, UInt<1>("h01")) - node T_90 = and(T_89, out.ready) - in[0].ready := T_90 - node T_92 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_93 = mux(UInt<1>("h00"), T_92, T_86) - node T_94 = and(T_93, out.ready) - in[1].ready := T_94 - node T_97 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_98 = mux(UInt<1>("h00"), UInt<1>("h01"), T_97) - T_64 := T_98 - - module Queue_57 : - output count : UInt<5> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.sdq_id := UInt<1>("h00") - deq.bits.phys := UInt<1>("h00") - deq.bits.kill := UInt<1>("h00") - deq.bits.typ := UInt<1>("h00") - deq.bits.cmd := UInt<1>("h00") - deq.bits.tag := UInt<1>("h00") - deq.bits.addr := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16], clock - reg T_88 : UInt<4>, clock, reset - onreset T_88 := UInt<4>("h00") - reg T_90 : UInt<4>, clock, reset - onreset T_90 := UInt<4>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_88, T_90) - node T_95 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_95) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_101 = and(enq.ready, enq.valid) - node T_103 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_101, T_103) - node T_105 = and(deq.ready, deq.valid) - node T_107 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_105, T_107) - when do_enq : - infer accessor T_109 = ram[T_88] - T_109 <> enq.bits - node T_118 = eq(T_88, UInt<4>("h0f")) - node T_120 = and(UInt<1>("h00"), T_118) - node T_123 = addw(T_88, UInt<1>("h01")) - node T_124 = mux(T_120, UInt<1>("h00"), T_123) - T_88 := T_124 - skip - when do_deq : - node T_126 = eq(T_90, UInt<4>("h0f")) - node T_128 = and(UInt<1>("h00"), T_126) - node T_131 = addw(T_90, UInt<1>("h01")) - node T_132 = mux(T_128, UInt<1>("h00"), T_131) - T_90 := T_132 - skip - node T_133 = neq(do_enq, do_deq) - when T_133 : - maybe_full := do_enq - skip - node T_135 = eq(empty, UInt<1>("h00")) - node T_137 = and(UInt<1>("h00"), enq.valid) - node T_138 = or(T_135, T_137) - deq.valid := T_138 - node T_140 = eq(full, UInt<1>("h00")) - node T_142 = and(UInt<1>("h00"), deq.ready) - node T_143 = or(T_140, T_142) - enq.ready := T_143 - infer accessor T_144 = ram[T_90] - wire T_160 : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} - T_160 <> T_144 - when maybe_flow : - T_160 <> enq.bits - skip - deq.bits <> T_160 - node ptr_diff = subw(T_88, T_90) - node T_169 = and(maybe_full, ptr_match) - node T_170 = cat(T_169, ptr_diff) - count := T_170 - - module MSHR : - output probe_rdy : UInt<1> - output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} - output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - output refill : {way_en : UInt<4>, addr : UInt<12>} - output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - output tag : UInt<20> - output idx_match : UInt<1> - input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>} - output req_sec_rdy : UInt<1> - input req_sec_val : UInt<1> - output req_pri_rdy : UInt<1> - input req_pri_val : UInt<1> - input clock : Clock - input reset : UInt<1> - - probe_rdy := UInt<1>("h00") - wb_req.bits.way_en := UInt<1>("h00") - wb_req.bits.voluntary := UInt<1>("h00") - wb_req.bits.r_type := UInt<1>("h00") - wb_req.bits.data := UInt<1>("h00") - wb_req.bits.addr_beat := UInt<1>("h00") - wb_req.bits.client_xact_id := UInt<1>("h00") - wb_req.bits.addr_block := UInt<1>("h00") - wb_req.valid := UInt<1>("h00") - replay.bits.sdq_id := UInt<1>("h00") - replay.bits.phys := UInt<1>("h00") - replay.bits.kill := UInt<1>("h00") - replay.bits.typ := UInt<1>("h00") - replay.bits.cmd := UInt<1>("h00") - replay.bits.tag := UInt<1>("h00") - replay.bits.addr := UInt<1>("h00") - replay.valid := UInt<1>("h00") - meta_write.bits.data.coh.state := UInt<1>("h00") - meta_write.bits.data.tag := UInt<1>("h00") - meta_write.bits.way_en := UInt<1>("h00") - meta_write.bits.idx := UInt<1>("h00") - meta_write.valid := UInt<1>("h00") - meta_read.bits.tag := UInt<1>("h00") - meta_read.bits.idx := UInt<1>("h00") - meta_read.valid := UInt<1>("h00") - refill.addr := UInt<1>("h00") - refill.way_en := UInt<1>("h00") - mem_req.bits.union := UInt<1>("h00") - mem_req.bits.a_type := UInt<1>("h00") - mem_req.bits.is_builtin_type := UInt<1>("h00") - mem_req.bits.data := UInt<1>("h00") - mem_req.bits.addr_beat := UInt<1>("h00") - mem_req.bits.client_xact_id := UInt<1>("h00") - mem_req.bits.addr_block := UInt<1>("h00") - mem_req.valid := UInt<1>("h00") - tag := UInt<1>("h00") - idx_match := UInt<1>("h00") - req_sec_rdy := UInt<1>("h00") - req_pri_rdy := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - wire T_657 : {state : UInt<2>} - T_657.state := UInt<1>("h00") - T_657.state := UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clock, reset - onreset new_coh_state := T_657 - reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset - node req_idx = bits(req.addr, 11, 6) - node T_783 = bits(req_bits.addr, 11, 6) - node idx_match_1 = eq(req_idx, T_783) - node T_785 = eq(req_bits.cmd, UInt<5>("h01")) - node T_786 = eq(req_bits.cmd, UInt<5>("h07")) - node T_787 = or(T_785, T_786) - node T_788 = bit(req_bits.cmd, 3) - node T_789 = eq(req_bits.cmd, UInt<5>("h04")) - node T_790 = or(T_788, T_789) - node T_791 = or(T_787, T_790) - node T_792 = eq(req_bits.cmd, UInt<5>("h03")) - node T_793 = or(T_791, T_792) - node T_794 = eq(req_bits.cmd, UInt<5>("h06")) - node T_795 = or(T_793, T_794) - node T_796 = eq(req.cmd, UInt<5>("h01")) - node T_797 = eq(req.cmd, UInt<5>("h07")) - node T_798 = or(T_796, T_797) - node T_799 = bit(req.cmd, 3) - node T_800 = eq(req.cmd, UInt<5>("h04")) - node T_801 = or(T_799, T_800) - node T_802 = or(T_798, T_801) - node T_803 = eq(req.cmd, UInt<5>("h03")) - node T_804 = or(T_802, T_803) - node T_805 = eq(req.cmd, UInt<5>("h06")) - node T_806 = or(T_804, T_805) - node T_808 = eq(T_806, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_795, T_808) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] := UInt<1>("h01") - states_before_refill[1] := UInt<2>("h02") - states_before_refill[2] := UInt<2>("h03") - node T_816 = eq(states_before_refill[0], state) - node T_817 = eq(states_before_refill[1], state) - node T_818 = eq(states_before_refill[2], state) - node T_820 = or(UInt<1>("h00"), T_816) - node T_821 = or(T_820, T_817) - node T_822 = or(T_821, T_818) - wire T_824 : UInt<3>[2] - T_824[0] := UInt<3>("h04") - T_824[1] := UInt<3>("h05") - node T_828 = eq(T_824[0], state) - node T_829 = eq(T_824[1], state) - node T_831 = or(UInt<1>("h00"), T_828) - node T_832 = or(T_831, T_829) - node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_835 = and(T_832, T_834) - node T_836 = or(T_822, T_835) - node sec_rdy = and(idx_match_1, T_836) - wire T_841 : UInt<3>[1] - T_841[0] := UInt<3>("h05") - node T_844 = eq(T_841[0], mem_grant.bits.g_type) - node T_846 = or(UInt<1>("h00"), T_844) - wire T_848 : UInt<1>[2] - T_848[0] := UInt<1>("h00") - T_848[1] := UInt<1>("h01") - node T_852 = eq(T_848[0], mem_grant.bits.g_type) - node T_853 = eq(T_848[1], mem_grant.bits.g_type) - node T_855 = or(UInt<1>("h00"), T_852) - node T_856 = or(T_855, T_853) - node T_857 = mux(mem_grant.bits.is_builtin_type, T_846, T_856) - node gnt_multi_data = and(UInt<1>("h01"), T_857) - node T_859 = and(mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clock, reset - onreset refill_cnt := UInt<2>("h00") - when T_859 : - node T_863 = eq(refill_cnt, UInt<2>("h03")) - node T_865 = and(UInt<1>("h00"), T_863) - node T_868 = addw(refill_cnt, UInt<1>("h01")) - node T_869 = mux(T_865, UInt<1>("h00"), T_868) - refill_cnt := T_869 - skip - node refill_count_done = and(T_859, T_863) - node T_872 = eq(gnt_multi_data, UInt<1>("h00")) - node T_873 = or(T_872, refill_count_done) - node refill_done = and(mem_grant.valid, T_873) - inst rpq of Queue_57 - rpq.deq.ready := UInt<1>("h00") - rpq.enq.bits.sdq_id := UInt<1>("h00") - rpq.enq.bits.phys := UInt<1>("h00") - rpq.enq.bits.kill := UInt<1>("h00") - rpq.enq.bits.typ := UInt<1>("h00") - rpq.enq.bits.cmd := UInt<1>("h00") - rpq.enq.bits.tag := UInt<1>("h00") - rpq.enq.bits.addr := UInt<1>("h00") - rpq.enq.valid := UInt<1>("h00") - rpq.reset := UInt<1>("h00") - rpq.clock := clock - rpq.reset := reset - node T_893 = and(req_pri_val, req_pri_rdy) - node T_894 = and(req_sec_val, sec_rdy) - node T_895 = or(T_893, T_894) - node T_896 = eq(req_bits.cmd, UInt<5>("h02")) - node T_897 = eq(req_bits.cmd, UInt<5>("h03")) - node T_898 = or(T_896, T_897) - node T_900 = eq(T_898, UInt<1>("h00")) - node T_901 = and(T_895, T_900) - rpq.enq.valid := T_901 - rpq.enq.bits <> req_bits - node T_902 = eq(state, UInt<4>("h08")) - node T_903 = and(replay.ready, T_902) - node T_904 = eq(state, UInt<1>("h00")) - node T_905 = or(T_903, T_904) - rpq.deq.ready := T_905 - node T_906 = eq(req.cmd, UInt<5>("h01")) - node T_907 = eq(req.cmd, UInt<5>("h07")) - node T_908 = or(T_906, T_907) - node T_909 = bit(req.cmd, 3) - node T_910 = eq(req.cmd, UInt<5>("h04")) - node T_911 = or(T_909, T_910) - node T_912 = or(T_908, T_911) - node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) - node T_914 = eq(UInt<2>("h02"), mem_grant.bits.g_type) - node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) - node T_916 = eq(UInt<1>("h01"), mem_grant.bits.g_type) - node T_917 = mux(T_916, T_913, T_915) - node T_918 = eq(UInt<1>("h00"), mem_grant.bits.g_type) - node T_919 = mux(T_918, UInt<1>("h01"), T_917) - node T_920 = mux(mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) - wire coh_on_grant : {state : UInt<2>} - coh_on_grant.state := UInt<1>("h00") - coh_on_grant.state := T_920 - node T_972 = eq(req_bits.cmd, UInt<5>("h01")) - node T_973 = eq(req_bits.cmd, UInt<5>("h07")) - node T_974 = or(T_972, T_973) - node T_975 = bit(req_bits.cmd, 3) - node T_976 = eq(req_bits.cmd, UInt<5>("h04")) - node T_977 = or(T_975, T_976) - node T_978 = or(T_974, T_977) - node T_979 = mux(T_978, UInt<2>("h03"), req_bits.old_meta.coh.state) - wire coh_on_hit : {state : UInt<2>} - coh_on_hit.state := UInt<1>("h00") - coh_on_hit.state := T_979 - node T_1031 = eq(state, UInt<4>("h08")) - node T_1033 = eq(rpq.deq.valid, UInt<1>("h00")) - node T_1034 = and(T_1031, T_1033) - when T_1034 : - state := UInt<1>("h00") - skip - node T_1035 = eq(state, UInt<3>("h07")) - when T_1035 : - state := UInt<4>("h08") - skip - node T_1036 = eq(state, UInt<3>("h06")) - node T_1037 = and(T_1036, meta_write.ready) - when T_1037 : - state := UInt<3>("h07") - skip - node T_1038 = eq(state, UInt<3>("h05")) - when T_1038 : - when mem_grant.valid : - new_coh_state <> coh_on_grant - skip - when refill_done : - state := UInt<3>("h06") - skip - skip - node T_1039 = and(mem_req.ready, mem_req.valid) - when T_1039 : - state := UInt<3>("h05") - skip - node T_1040 = eq(state, UInt<2>("h03")) - node T_1041 = and(T_1040, meta_write.ready) - when T_1041 : - state := UInt<3>("h04") - skip - node T_1042 = eq(state, UInt<2>("h02")) - node T_1043 = and(T_1042, mem_grant.valid) - when T_1043 : - state := UInt<2>("h03") - skip - node T_1044 = and(wb_req.ready, wb_req.valid) - when T_1044 : - node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) - state := T_1048 - skip - node T_1049 = and(req_sec_val, req_sec_rdy) - when T_1049 : - when cmd_requires_second_acquire : - req.cmd := req_bits.cmd - skip - skip - node T_1050 = and(req_pri_val, req_pri_rdy) - when T_1050 : - req <> req_bits - when req_bits.tag_match : - node T_1051 = eq(req_bits.cmd, UInt<5>("h01")) - node T_1052 = eq(req_bits.cmd, UInt<5>("h07")) - node T_1053 = or(T_1051, T_1052) - node T_1054 = bit(req_bits.cmd, 3) - node T_1055 = eq(req_bits.cmd, UInt<5>("h04")) - node T_1056 = or(T_1054, T_1055) - node T_1057 = or(T_1053, T_1056) - node T_1058 = eq(req_bits.cmd, UInt<5>("h03")) - node T_1059 = or(T_1057, T_1058) - node T_1060 = eq(req_bits.cmd, UInt<5>("h06")) - node T_1061 = or(T_1059, T_1060) - wire T_1063 : UInt<2>[2] - T_1063[0] := UInt<2>("h02") - T_1063[1] := UInt<2>("h03") - node T_1067 = eq(T_1063[0], req_bits.old_meta.coh.state) - node T_1068 = eq(T_1063[1], req_bits.old_meta.coh.state) - node T_1070 = or(UInt<1>("h00"), T_1067) - node T_1071 = or(T_1070, T_1068) - wire T_1073 : UInt<2>[3] - T_1073[0] := UInt<1>("h01") - T_1073[1] := UInt<2>("h02") - T_1073[2] := UInt<2>("h03") - node T_1078 = eq(T_1073[0], req_bits.old_meta.coh.state) - node T_1079 = eq(T_1073[1], req_bits.old_meta.coh.state) - node T_1080 = eq(T_1073[2], req_bits.old_meta.coh.state) - node T_1082 = or(UInt<1>("h00"), T_1078) - node T_1083 = or(T_1082, T_1079) - node T_1084 = or(T_1083, T_1080) - node T_1085 = mux(T_1061, T_1071, T_1084) - when T_1085 : - state := UInt<3>("h06") - new_coh_state <> coh_on_hit - skip - else : - state := UInt<3>("h04") - skip - skip - else : - wire T_1087 : UInt<2>[1] - T_1087[0] := UInt<2>("h03") - node T_1090 = eq(T_1087[0], req_bits.old_meta.coh.state) - node T_1092 = or(UInt<1>("h00"), T_1090) - node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) - state := T_1093 - skip - skip - node T_1094 = neq(state, UInt<1>("h00")) - node T_1095 = and(T_1094, idx_match_1) - idx_match := T_1095 - refill.way_en := req.way_en - node T_1096 = cat(req_idx, refill_cnt) - node T_1097 = shl(T_1096, 4) - refill.addr := T_1097 - node T_1098 = shr(req.addr, 12) - tag := T_1098 - node T_1099 = eq(state, UInt<1>("h00")) - req_pri_rdy := T_1099 - node T_1100 = and(sec_rdy, rpq.enq.ready) - req_sec_rdy := T_1100 - reg meta_hazard : UInt<2>, clock, reset - onreset meta_hazard := UInt<2>("h00") - node T_1104 = neq(meta_hazard, UInt<1>("h00")) - when T_1104 : - node T_1106 = addw(meta_hazard, UInt<1>("h01")) - meta_hazard := T_1106 - skip - node T_1107 = and(meta_write.ready, meta_write.valid) - when T_1107 : - meta_hazard := UInt<1>("h01") - skip - node T_1110 = eq(idx_match_1, UInt<1>("h00")) - node T_1111 = eq(states_before_refill[0], state) - node T_1112 = eq(states_before_refill[1], state) - node T_1113 = eq(states_before_refill[2], state) - node T_1115 = or(UInt<1>("h00"), T_1111) - node T_1116 = or(T_1115, T_1112) - node T_1117 = or(T_1116, T_1113) - node T_1119 = eq(T_1117, UInt<1>("h00")) - node T_1121 = eq(meta_hazard, UInt<1>("h00")) - node T_1122 = and(T_1119, T_1121) - node T_1123 = or(T_1110, T_1122) - probe_rdy := T_1123 - node T_1124 = eq(state, UInt<3>("h06")) - node T_1125 = eq(state, UInt<2>("h03")) - node T_1126 = or(T_1124, T_1125) - meta_write.valid := T_1126 - meta_write.bits.idx := req_idx - node T_1127 = eq(state, UInt<2>("h03")) - wire T_1129 : UInt<2>[2] - T_1129[0] := UInt<2>("h02") - T_1129[1] := UInt<2>("h03") - node T_1133 = eq(T_1129[0], req.old_meta.coh.state) - node T_1134 = eq(T_1129[1], req.old_meta.coh.state) - node T_1136 = or(UInt<1>("h00"), T_1133) - node T_1137 = or(T_1136, T_1134) - node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) - node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) - node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) - node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1144 = mux(T_1143, T_1138, T_1142) - node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) - wire T_1172 : {state : UInt<2>} - T_1172.state := UInt<1>("h00") - T_1172.state := T_1146 - wire T_1223 : {state : UInt<2>} - T_1223 <> new_coh_state - when T_1127 : - T_1223 <> T_1172 - skip - meta_write.bits.data.coh <> T_1223 - meta_write.bits.data.tag := tag - meta_write.bits.way_en := req.way_en - node T_1248 = eq(state, UInt<1>("h01")) - wb_req.valid := T_1248 - node T_1250 = cat(req.old_meta.tag, req_idx) - wire T_1255 : UInt<2>[1] - T_1255[0] := UInt<2>("h03") - node T_1258 = eq(T_1255[0], req.old_meta.coh.state) - node T_1260 = or(UInt<1>("h00"), T_1258) - node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) - node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) - node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) - node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) - node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1267 = mux(T_1266, T_1262, T_1265) - node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1269 = mux(T_1268, T_1261, T_1267) - wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} - T_1300.voluntary := UInt<1>("h00") - T_1300.r_type := UInt<1>("h00") - T_1300.data := UInt<1>("h00") - T_1300.addr_beat := UInt<1>("h00") - T_1300.client_xact_id := UInt<1>("h00") - T_1300.addr_block := UInt<1>("h00") - T_1300.r_type := T_1269 - T_1300.client_xact_id := UInt<1>("h00") - T_1300.addr_block := T_1250 - T_1300.addr_beat := UInt<1>("h00") - T_1300.data := UInt<1>("h00") - T_1300.voluntary := UInt<1>("h01") - wb_req.bits <> T_1300 - wb_req.bits.way_en := req.way_en - node T_1336 = eq(state, UInt<3>("h04")) - mem_req.valid := T_1336 - node T_1337 = cat(tag, req_idx) - node T_1340 = eq(req.cmd, UInt<5>("h01")) - node T_1341 = eq(req.cmd, UInt<5>("h07")) - node T_1342 = or(T_1340, T_1341) - node T_1343 = bit(req.cmd, 3) - node T_1344 = eq(req.cmd, UInt<5>("h04")) - node T_1345 = or(T_1343, T_1344) - node T_1346 = or(T_1342, T_1345) - node T_1347 = eq(req.cmd, UInt<5>("h03")) - node T_1348 = or(T_1346, T_1347) - node T_1349 = eq(req.cmd, UInt<5>("h06")) - node T_1350 = or(T_1348, T_1349) - node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) - node T_1353 = cat(req.cmd, UInt<1>("h01")) - wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_1387.union := UInt<1>("h00") - T_1387.a_type := UInt<1>("h00") - T_1387.is_builtin_type := UInt<1>("h00") - T_1387.data := UInt<1>("h00") - T_1387.addr_beat := UInt<1>("h00") - T_1387.client_xact_id := UInt<1>("h00") - T_1387.addr_block := UInt<1>("h00") - T_1387.is_builtin_type := UInt<1>("h00") - T_1387.a_type := T_1351 - T_1387.client_xact_id := UInt<1>("h00") - T_1387.addr_block := T_1337 - T_1387.addr_beat := UInt<1>("h00") - T_1387.data := UInt<1>("h00") - T_1387.union := T_1353 - mem_req.bits <> T_1387 - node T_1425 = eq(state, UInt<4>("h08")) - meta_read.valid := T_1425 - meta_read.bits.idx := req_idx - meta_read.bits.tag := tag - node T_1426 = eq(state, UInt<4>("h08")) - node T_1427 = and(T_1426, rpq.deq.valid) - replay.valid := T_1427 - replay.bits <> rpq.deq.bits - replay.bits.phys := UInt<1>("h01") - node T_1429 = bits(rpq.deq.bits.addr, 5, 0) - node T_1430 = cat(req_idx, T_1429) - node T_1431 = cat(tag, T_1430) - replay.bits.addr := T_1431 - node T_1433 = eq(meta_read.ready, UInt<1>("h00")) - when T_1433 : - rpq.deq.ready := UInt<1>("h00") - replay.bits.cmd := UInt<5>("h05") - skip - - module MSHR_58 : - output probe_rdy : UInt<1> - output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} - output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - output refill : {way_en : UInt<4>, addr : UInt<12>} - output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - output tag : UInt<20> - output idx_match : UInt<1> - input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>} - output req_sec_rdy : UInt<1> - input req_sec_val : UInt<1> - output req_pri_rdy : UInt<1> - input req_pri_val : UInt<1> - input clock : Clock - input reset : UInt<1> - - probe_rdy := UInt<1>("h00") - wb_req.bits.way_en := UInt<1>("h00") - wb_req.bits.voluntary := UInt<1>("h00") - wb_req.bits.r_type := UInt<1>("h00") - wb_req.bits.data := UInt<1>("h00") - wb_req.bits.addr_beat := UInt<1>("h00") - wb_req.bits.client_xact_id := UInt<1>("h00") - wb_req.bits.addr_block := UInt<1>("h00") - wb_req.valid := UInt<1>("h00") - replay.bits.sdq_id := UInt<1>("h00") - replay.bits.phys := UInt<1>("h00") - replay.bits.kill := UInt<1>("h00") - replay.bits.typ := UInt<1>("h00") - replay.bits.cmd := UInt<1>("h00") - replay.bits.tag := UInt<1>("h00") - replay.bits.addr := UInt<1>("h00") - replay.valid := UInt<1>("h00") - meta_write.bits.data.coh.state := UInt<1>("h00") - meta_write.bits.data.tag := UInt<1>("h00") - meta_write.bits.way_en := UInt<1>("h00") - meta_write.bits.idx := UInt<1>("h00") - meta_write.valid := UInt<1>("h00") - meta_read.bits.tag := UInt<1>("h00") - meta_read.bits.idx := UInt<1>("h00") - meta_read.valid := UInt<1>("h00") - refill.addr := UInt<1>("h00") - refill.way_en := UInt<1>("h00") - mem_req.bits.union := UInt<1>("h00") - mem_req.bits.a_type := UInt<1>("h00") - mem_req.bits.is_builtin_type := UInt<1>("h00") - mem_req.bits.data := UInt<1>("h00") - mem_req.bits.addr_beat := UInt<1>("h00") - mem_req.bits.client_xact_id := UInt<1>("h00") - mem_req.bits.addr_block := UInt<1>("h00") - mem_req.valid := UInt<1>("h00") - tag := UInt<1>("h00") - idx_match := UInt<1>("h00") - req_sec_rdy := UInt<1>("h00") - req_pri_rdy := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - wire T_657 : {state : UInt<2>} - T_657.state := UInt<1>("h00") - T_657.state := UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clock, reset - onreset new_coh_state := T_657 - reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset - node req_idx = bits(req.addr, 11, 6) - node T_783 = bits(req_bits.addr, 11, 6) - node idx_match_1 = eq(req_idx, T_783) - node T_785 = eq(req_bits.cmd, UInt<5>("h01")) - node T_786 = eq(req_bits.cmd, UInt<5>("h07")) - node T_787 = or(T_785, T_786) - node T_788 = bit(req_bits.cmd, 3) - node T_789 = eq(req_bits.cmd, UInt<5>("h04")) - node T_790 = or(T_788, T_789) - node T_791 = or(T_787, T_790) - node T_792 = eq(req_bits.cmd, UInt<5>("h03")) - node T_793 = or(T_791, T_792) - node T_794 = eq(req_bits.cmd, UInt<5>("h06")) - node T_795 = or(T_793, T_794) - node T_796 = eq(req.cmd, UInt<5>("h01")) - node T_797 = eq(req.cmd, UInt<5>("h07")) - node T_798 = or(T_796, T_797) - node T_799 = bit(req.cmd, 3) - node T_800 = eq(req.cmd, UInt<5>("h04")) - node T_801 = or(T_799, T_800) - node T_802 = or(T_798, T_801) - node T_803 = eq(req.cmd, UInt<5>("h03")) - node T_804 = or(T_802, T_803) - node T_805 = eq(req.cmd, UInt<5>("h06")) - node T_806 = or(T_804, T_805) - node T_808 = eq(T_806, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_795, T_808) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] := UInt<1>("h01") - states_before_refill[1] := UInt<2>("h02") - states_before_refill[2] := UInt<2>("h03") - node T_816 = eq(states_before_refill[0], state) - node T_817 = eq(states_before_refill[1], state) - node T_818 = eq(states_before_refill[2], state) - node T_820 = or(UInt<1>("h00"), T_816) - node T_821 = or(T_820, T_817) - node T_822 = or(T_821, T_818) - wire T_824 : UInt<3>[2] - T_824[0] := UInt<3>("h04") - T_824[1] := UInt<3>("h05") - node T_828 = eq(T_824[0], state) - node T_829 = eq(T_824[1], state) - node T_831 = or(UInt<1>("h00"), T_828) - node T_832 = or(T_831, T_829) - node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_835 = and(T_832, T_834) - node T_836 = or(T_822, T_835) - node sec_rdy = and(idx_match_1, T_836) - wire T_841 : UInt<3>[1] - T_841[0] := UInt<3>("h05") - node T_844 = eq(T_841[0], mem_grant.bits.g_type) - node T_846 = or(UInt<1>("h00"), T_844) - wire T_848 : UInt<1>[2] - T_848[0] := UInt<1>("h00") - T_848[1] := UInt<1>("h01") - node T_852 = eq(T_848[0], mem_grant.bits.g_type) - node T_853 = eq(T_848[1], mem_grant.bits.g_type) - node T_855 = or(UInt<1>("h00"), T_852) - node T_856 = or(T_855, T_853) - node T_857 = mux(mem_grant.bits.is_builtin_type, T_846, T_856) - node gnt_multi_data = and(UInt<1>("h01"), T_857) - node T_859 = and(mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clock, reset - onreset refill_cnt := UInt<2>("h00") - when T_859 : - node T_863 = eq(refill_cnt, UInt<2>("h03")) - node T_865 = and(UInt<1>("h00"), T_863) - node T_868 = addw(refill_cnt, UInt<1>("h01")) - node T_869 = mux(T_865, UInt<1>("h00"), T_868) - refill_cnt := T_869 - skip - node refill_count_done = and(T_859, T_863) - node T_872 = eq(gnt_multi_data, UInt<1>("h00")) - node T_873 = or(T_872, refill_count_done) - node refill_done = and(mem_grant.valid, T_873) - inst rpq of Queue_57 - rpq.deq.ready := UInt<1>("h00") - rpq.enq.bits.sdq_id := UInt<1>("h00") - rpq.enq.bits.phys := UInt<1>("h00") - rpq.enq.bits.kill := UInt<1>("h00") - rpq.enq.bits.typ := UInt<1>("h00") - rpq.enq.bits.cmd := UInt<1>("h00") - rpq.enq.bits.tag := UInt<1>("h00") - rpq.enq.bits.addr := UInt<1>("h00") - rpq.enq.valid := UInt<1>("h00") - rpq.reset := UInt<1>("h00") - rpq.clock := clock - rpq.reset := reset - node T_893 = and(req_pri_val, req_pri_rdy) - node T_894 = and(req_sec_val, sec_rdy) - node T_895 = or(T_893, T_894) - node T_896 = eq(req_bits.cmd, UInt<5>("h02")) - node T_897 = eq(req_bits.cmd, UInt<5>("h03")) - node T_898 = or(T_896, T_897) - node T_900 = eq(T_898, UInt<1>("h00")) - node T_901 = and(T_895, T_900) - rpq.enq.valid := T_901 - rpq.enq.bits <> req_bits - node T_902 = eq(state, UInt<4>("h08")) - node T_903 = and(replay.ready, T_902) - node T_904 = eq(state, UInt<1>("h00")) - node T_905 = or(T_903, T_904) - rpq.deq.ready := T_905 - node T_906 = eq(req.cmd, UInt<5>("h01")) - node T_907 = eq(req.cmd, UInt<5>("h07")) - node T_908 = or(T_906, T_907) - node T_909 = bit(req.cmd, 3) - node T_910 = eq(req.cmd, UInt<5>("h04")) - node T_911 = or(T_909, T_910) - node T_912 = or(T_908, T_911) - node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) - node T_914 = eq(UInt<2>("h02"), mem_grant.bits.g_type) - node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) - node T_916 = eq(UInt<1>("h01"), mem_grant.bits.g_type) - node T_917 = mux(T_916, T_913, T_915) - node T_918 = eq(UInt<1>("h00"), mem_grant.bits.g_type) - node T_919 = mux(T_918, UInt<1>("h01"), T_917) - node T_920 = mux(mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) - wire coh_on_grant : {state : UInt<2>} - coh_on_grant.state := UInt<1>("h00") - coh_on_grant.state := T_920 - node T_972 = eq(req_bits.cmd, UInt<5>("h01")) - node T_973 = eq(req_bits.cmd, UInt<5>("h07")) - node T_974 = or(T_972, T_973) - node T_975 = bit(req_bits.cmd, 3) - node T_976 = eq(req_bits.cmd, UInt<5>("h04")) - node T_977 = or(T_975, T_976) - node T_978 = or(T_974, T_977) - node T_979 = mux(T_978, UInt<2>("h03"), req_bits.old_meta.coh.state) - wire coh_on_hit : {state : UInt<2>} - coh_on_hit.state := UInt<1>("h00") - coh_on_hit.state := T_979 - node T_1031 = eq(state, UInt<4>("h08")) - node T_1033 = eq(rpq.deq.valid, UInt<1>("h00")) - node T_1034 = and(T_1031, T_1033) - when T_1034 : - state := UInt<1>("h00") - skip - node T_1035 = eq(state, UInt<3>("h07")) - when T_1035 : - state := UInt<4>("h08") - skip - node T_1036 = eq(state, UInt<3>("h06")) - node T_1037 = and(T_1036, meta_write.ready) - when T_1037 : - state := UInt<3>("h07") - skip - node T_1038 = eq(state, UInt<3>("h05")) - when T_1038 : - when mem_grant.valid : - new_coh_state <> coh_on_grant - skip - when refill_done : - state := UInt<3>("h06") - skip - skip - node T_1039 = and(mem_req.ready, mem_req.valid) - when T_1039 : - state := UInt<3>("h05") - skip - node T_1040 = eq(state, UInt<2>("h03")) - node T_1041 = and(T_1040, meta_write.ready) - when T_1041 : - state := UInt<3>("h04") - skip - node T_1042 = eq(state, UInt<2>("h02")) - node T_1043 = and(T_1042, mem_grant.valid) - when T_1043 : - state := UInt<2>("h03") - skip - node T_1044 = and(wb_req.ready, wb_req.valid) - when T_1044 : - node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) - state := T_1048 - skip - node T_1049 = and(req_sec_val, req_sec_rdy) - when T_1049 : - when cmd_requires_second_acquire : - req.cmd := req_bits.cmd - skip - skip - node T_1050 = and(req_pri_val, req_pri_rdy) - when T_1050 : - req <> req_bits - when req_bits.tag_match : - node T_1051 = eq(req_bits.cmd, UInt<5>("h01")) - node T_1052 = eq(req_bits.cmd, UInt<5>("h07")) - node T_1053 = or(T_1051, T_1052) - node T_1054 = bit(req_bits.cmd, 3) - node T_1055 = eq(req_bits.cmd, UInt<5>("h04")) - node T_1056 = or(T_1054, T_1055) - node T_1057 = or(T_1053, T_1056) - node T_1058 = eq(req_bits.cmd, UInt<5>("h03")) - node T_1059 = or(T_1057, T_1058) - node T_1060 = eq(req_bits.cmd, UInt<5>("h06")) - node T_1061 = or(T_1059, T_1060) - wire T_1063 : UInt<2>[2] - T_1063[0] := UInt<2>("h02") - T_1063[1] := UInt<2>("h03") - node T_1067 = eq(T_1063[0], req_bits.old_meta.coh.state) - node T_1068 = eq(T_1063[1], req_bits.old_meta.coh.state) - node T_1070 = or(UInt<1>("h00"), T_1067) - node T_1071 = or(T_1070, T_1068) - wire T_1073 : UInt<2>[3] - T_1073[0] := UInt<1>("h01") - T_1073[1] := UInt<2>("h02") - T_1073[2] := UInt<2>("h03") - node T_1078 = eq(T_1073[0], req_bits.old_meta.coh.state) - node T_1079 = eq(T_1073[1], req_bits.old_meta.coh.state) - node T_1080 = eq(T_1073[2], req_bits.old_meta.coh.state) - node T_1082 = or(UInt<1>("h00"), T_1078) - node T_1083 = or(T_1082, T_1079) - node T_1084 = or(T_1083, T_1080) - node T_1085 = mux(T_1061, T_1071, T_1084) - when T_1085 : - state := UInt<3>("h06") - new_coh_state <> coh_on_hit - skip - else : - state := UInt<3>("h04") - skip - skip - else : - wire T_1087 : UInt<2>[1] - T_1087[0] := UInt<2>("h03") - node T_1090 = eq(T_1087[0], req_bits.old_meta.coh.state) - node T_1092 = or(UInt<1>("h00"), T_1090) - node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) - state := T_1093 - skip - skip - node T_1094 = neq(state, UInt<1>("h00")) - node T_1095 = and(T_1094, idx_match_1) - idx_match := T_1095 - refill.way_en := req.way_en - node T_1096 = cat(req_idx, refill_cnt) - node T_1097 = shl(T_1096, 4) - refill.addr := T_1097 - node T_1098 = shr(req.addr, 12) - tag := T_1098 - node T_1099 = eq(state, UInt<1>("h00")) - req_pri_rdy := T_1099 - node T_1100 = and(sec_rdy, rpq.enq.ready) - req_sec_rdy := T_1100 - reg meta_hazard : UInt<2>, clock, reset - onreset meta_hazard := UInt<2>("h00") - node T_1104 = neq(meta_hazard, UInt<1>("h00")) - when T_1104 : - node T_1106 = addw(meta_hazard, UInt<1>("h01")) - meta_hazard := T_1106 - skip - node T_1107 = and(meta_write.ready, meta_write.valid) - when T_1107 : - meta_hazard := UInt<1>("h01") - skip - node T_1110 = eq(idx_match_1, UInt<1>("h00")) - node T_1111 = eq(states_before_refill[0], state) - node T_1112 = eq(states_before_refill[1], state) - node T_1113 = eq(states_before_refill[2], state) - node T_1115 = or(UInt<1>("h00"), T_1111) - node T_1116 = or(T_1115, T_1112) - node T_1117 = or(T_1116, T_1113) - node T_1119 = eq(T_1117, UInt<1>("h00")) - node T_1121 = eq(meta_hazard, UInt<1>("h00")) - node T_1122 = and(T_1119, T_1121) - node T_1123 = or(T_1110, T_1122) - probe_rdy := T_1123 - node T_1124 = eq(state, UInt<3>("h06")) - node T_1125 = eq(state, UInt<2>("h03")) - node T_1126 = or(T_1124, T_1125) - meta_write.valid := T_1126 - meta_write.bits.idx := req_idx - node T_1127 = eq(state, UInt<2>("h03")) - wire T_1129 : UInt<2>[2] - T_1129[0] := UInt<2>("h02") - T_1129[1] := UInt<2>("h03") - node T_1133 = eq(T_1129[0], req.old_meta.coh.state) - node T_1134 = eq(T_1129[1], req.old_meta.coh.state) - node T_1136 = or(UInt<1>("h00"), T_1133) - node T_1137 = or(T_1136, T_1134) - node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) - node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) - node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) - node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1144 = mux(T_1143, T_1138, T_1142) - node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) - wire T_1172 : {state : UInt<2>} - T_1172.state := UInt<1>("h00") - T_1172.state := T_1146 - wire T_1223 : {state : UInt<2>} - T_1223 <> new_coh_state - when T_1127 : - T_1223 <> T_1172 - skip - meta_write.bits.data.coh <> T_1223 - meta_write.bits.data.tag := tag - meta_write.bits.way_en := req.way_en - node T_1248 = eq(state, UInt<1>("h01")) - wb_req.valid := T_1248 - node T_1250 = cat(req.old_meta.tag, req_idx) - wire T_1255 : UInt<2>[1] - T_1255[0] := UInt<2>("h03") - node T_1258 = eq(T_1255[0], req.old_meta.coh.state) - node T_1260 = or(UInt<1>("h00"), T_1258) - node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) - node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) - node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) - node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) - node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1267 = mux(T_1266, T_1262, T_1265) - node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1269 = mux(T_1268, T_1261, T_1267) - wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} - T_1300.voluntary := UInt<1>("h00") - T_1300.r_type := UInt<1>("h00") - T_1300.data := UInt<1>("h00") - T_1300.addr_beat := UInt<1>("h00") - T_1300.client_xact_id := UInt<1>("h00") - T_1300.addr_block := UInt<1>("h00") - T_1300.r_type := T_1269 - T_1300.client_xact_id := UInt<1>("h01") - T_1300.addr_block := T_1250 - T_1300.addr_beat := UInt<1>("h00") - T_1300.data := UInt<1>("h00") - T_1300.voluntary := UInt<1>("h01") - wb_req.bits <> T_1300 - wb_req.bits.way_en := req.way_en - node T_1336 = eq(state, UInt<3>("h04")) - mem_req.valid := T_1336 - node T_1337 = cat(tag, req_idx) - node T_1340 = eq(req.cmd, UInt<5>("h01")) - node T_1341 = eq(req.cmd, UInt<5>("h07")) - node T_1342 = or(T_1340, T_1341) - node T_1343 = bit(req.cmd, 3) - node T_1344 = eq(req.cmd, UInt<5>("h04")) - node T_1345 = or(T_1343, T_1344) - node T_1346 = or(T_1342, T_1345) - node T_1347 = eq(req.cmd, UInt<5>("h03")) - node T_1348 = or(T_1346, T_1347) - node T_1349 = eq(req.cmd, UInt<5>("h06")) - node T_1350 = or(T_1348, T_1349) - node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) - node T_1353 = cat(req.cmd, UInt<1>("h01")) - wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} - T_1387.union := UInt<1>("h00") - T_1387.a_type := UInt<1>("h00") - T_1387.is_builtin_type := UInt<1>("h00") - T_1387.data := UInt<1>("h00") - T_1387.addr_beat := UInt<1>("h00") - T_1387.client_xact_id := UInt<1>("h00") - T_1387.addr_block := UInt<1>("h00") - T_1387.is_builtin_type := UInt<1>("h00") - T_1387.a_type := T_1351 - T_1387.client_xact_id := UInt<1>("h01") - T_1387.addr_block := T_1337 - T_1387.addr_beat := UInt<1>("h00") - T_1387.data := UInt<1>("h00") - T_1387.union := T_1353 - mem_req.bits <> T_1387 - node T_1425 = eq(state, UInt<4>("h08")) - meta_read.valid := T_1425 - meta_read.bits.idx := req_idx - meta_read.bits.tag := tag - node T_1426 = eq(state, UInt<4>("h08")) - node T_1427 = and(T_1426, rpq.deq.valid) - replay.valid := T_1427 - replay.bits <> rpq.deq.bits - replay.bits.phys := UInt<1>("h01") - node T_1429 = bits(rpq.deq.bits.addr, 5, 0) - node T_1430 = cat(req_idx, T_1429) - node T_1431 = cat(tag, T_1430) - replay.bits.addr := T_1431 - node T_1433 = eq(meta_read.ready, UInt<1>("h00")) - when T_1433 : - rpq.deq.ready := UInt<1>("h00") - replay.bits.cmd := UInt<5>("h05") - skip - - module MSHRFile : - output fence_rdy : UInt<1> - output probe_rdy : UInt<1> - output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} - input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} - output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}} - output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} - output refill : {way_en : UInt<4>, addr : UInt<12>} - output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} - output secondary_miss : UInt<1> - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}} - input clock : Clock - input reset : UInt<1> - - fence_rdy := UInt<1>("h00") - probe_rdy := UInt<1>("h00") - wb_req.bits.way_en := UInt<1>("h00") - wb_req.bits.voluntary := UInt<1>("h00") - wb_req.bits.r_type := UInt<1>("h00") - wb_req.bits.data := UInt<1>("h00") - wb_req.bits.addr_beat := UInt<1>("h00") - wb_req.bits.client_xact_id := UInt<1>("h00") - wb_req.bits.addr_block := UInt<1>("h00") - wb_req.valid := UInt<1>("h00") - replay.bits.data := UInt<1>("h00") - replay.bits.phys := UInt<1>("h00") - replay.bits.kill := UInt<1>("h00") - replay.bits.typ := UInt<1>("h00") - replay.bits.cmd := UInt<1>("h00") - replay.bits.tag := UInt<1>("h00") - replay.bits.addr := UInt<1>("h00") - replay.valid := UInt<1>("h00") - meta_write.bits.data.coh.state := UInt<1>("h00") - meta_write.bits.data.tag := UInt<1>("h00") - meta_write.bits.way_en := UInt<1>("h00") - meta_write.bits.idx := UInt<1>("h00") - meta_write.valid := UInt<1>("h00") - meta_read.bits.tag := UInt<1>("h00") - meta_read.bits.idx := UInt<1>("h00") - meta_read.valid := UInt<1>("h00") - refill.addr := UInt<1>("h00") - refill.way_en := UInt<1>("h00") - mem_req.bits.union := UInt<1>("h00") - mem_req.bits.a_type := UInt<1>("h00") - mem_req.bits.is_builtin_type := UInt<1>("h00") - mem_req.bits.data := UInt<1>("h00") - mem_req.bits.addr_beat := UInt<1>("h00") - mem_req.bits.client_xact_id := UInt<1>("h00") - mem_req.bits.addr_block := UInt<1>("h00") - mem_req.valid := UInt<1>("h00") - secondary_miss := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg sdq_val : UInt<17>, clock, reset - onreset sdq_val := UInt<17>("h00") - node T_710 = bits(sdq_val, 16, 0) - node T_711 = not(T_710) - node T_712 = bit(T_711, 0) - node T_713 = bit(T_711, 1) - node T_714 = bit(T_711, 2) - node T_715 = bit(T_711, 3) - node T_716 = bit(T_711, 4) - node T_717 = bit(T_711, 5) - node T_718 = bit(T_711, 6) - node T_719 = bit(T_711, 7) - node T_720 = bit(T_711, 8) - node T_721 = bit(T_711, 9) - node T_722 = bit(T_711, 10) - node T_723 = bit(T_711, 11) - node T_724 = bit(T_711, 12) - node T_725 = bit(T_711, 13) - node T_726 = bit(T_711, 14) - node T_727 = bit(T_711, 15) - node T_728 = bit(T_711, 16) - wire T_730 : UInt<1>[17] - T_730[0] := T_712 - T_730[1] := T_713 - T_730[2] := T_714 - T_730[3] := T_715 - T_730[4] := T_716 - T_730[5] := T_717 - T_730[6] := T_718 - T_730[7] := T_719 - T_730[8] := T_720 - T_730[9] := T_721 - T_730[10] := T_722 - T_730[11] := T_723 - T_730[12] := T_724 - T_730[13] := T_725 - T_730[14] := T_726 - T_730[15] := T_727 - T_730[16] := T_728 - node T_766 = mux(T_730[15], UInt<4>("h0f"), UInt<5>("h010")) - node T_767 = mux(T_730[14], UInt<4>("h0e"), T_766) - node T_768 = mux(T_730[13], UInt<4>("h0d"), T_767) - node T_769 = mux(T_730[12], UInt<4>("h0c"), T_768) - node T_770 = mux(T_730[11], UInt<4>("h0b"), T_769) - node T_771 = mux(T_730[10], UInt<4>("h0a"), T_770) - node T_772 = mux(T_730[9], UInt<4>("h09"), T_771) - node T_773 = mux(T_730[8], UInt<4>("h08"), T_772) - node T_774 = mux(T_730[7], UInt<3>("h07"), T_773) - node T_775 = mux(T_730[6], UInt<3>("h06"), T_774) - node T_776 = mux(T_730[5], UInt<3>("h05"), T_775) - node T_777 = mux(T_730[4], UInt<3>("h04"), T_776) - node T_778 = mux(T_730[3], UInt<2>("h03"), T_777) - node T_779 = mux(T_730[2], UInt<2>("h02"), T_778) - node T_780 = mux(T_730[1], UInt<1>("h01"), T_779) - node sdq_alloc_id = mux(T_730[0], UInt<1>("h00"), T_780) - node T_782 = not(sdq_val) - node T_784 = eq(T_782, UInt<1>("h00")) - node sdq_rdy = eq(T_784, UInt<1>("h00")) - node T_787 = and(req.valid, req.ready) - node T_788 = eq(req.bits.cmd, UInt<5>("h01")) - node T_789 = eq(req.bits.cmd, UInt<5>("h07")) - node T_790 = or(T_788, T_789) - node T_791 = bit(req.bits.cmd, 3) - node T_792 = eq(req.bits.cmd, UInt<5>("h04")) - node T_793 = or(T_791, T_792) - node T_794 = or(T_790, T_793) - node sdq_enq = and(T_787, T_794) - cmem sdq : UInt<64>[17], clock - when sdq_enq : - infer accessor T_798 = sdq[sdq_alloc_id] - T_798 := req.bits.data - skip - wire idxMatch : UInt<1>[2] - idxMatch[0] := UInt<1>("h00") - idxMatch[1] := UInt<1>("h00") - wire tagList : UInt<20>[2] - tagList[0] := UInt<1>("h00") - tagList[1] := UInt<1>("h00") - node T_828 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) - node T_830 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) - node T_832 = or(T_828, T_830) - wire T_833 : UInt<20> - T_833 := UInt<1>("h00") - T_833 := T_832 - node T_835 = shr(req.bits.addr, 12) - node tag_match = eq(T_833, T_835) - wire wbTagList : UInt[2] - wbTagList[0] := UInt<1>("h00") - wbTagList[1] := UInt<1>("h00") - wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] - refillMux[0].addr := UInt<1>("h00") - refillMux[0].way_en := UInt<1>("h00") - refillMux[1].addr := UInt<1>("h00") - refillMux[1].way_en := UInt<1>("h00") - inst meta_read_arb of Arbiter_52 - meta_read_arb.out.ready := UInt<1>("h00") - meta_read_arb.in[0].bits.tag := UInt<1>("h00") - meta_read_arb.in[0].bits.idx := UInt<1>("h00") - meta_read_arb.in[0].valid := UInt<1>("h00") - meta_read_arb.in[1].bits.tag := UInt<1>("h00") - meta_read_arb.in[1].bits.idx := UInt<1>("h00") - meta_read_arb.in[1].valid := UInt<1>("h00") - meta_read_arb.reset := UInt<1>("h00") - meta_read_arb.clock := clock - meta_read_arb.reset := reset - inst meta_write_arb of Arbiter_53 - meta_write_arb.out.ready := UInt<1>("h00") - meta_write_arb.in[0].bits.data.coh.state := UInt<1>("h00") - meta_write_arb.in[0].bits.data.tag := UInt<1>("h00") - meta_write_arb.in[0].bits.way_en := UInt<1>("h00") - meta_write_arb.in[0].bits.idx := UInt<1>("h00") - meta_write_arb.in[0].valid := UInt<1>("h00") - meta_write_arb.in[1].bits.data.coh.state := UInt<1>("h00") - meta_write_arb.in[1].bits.data.tag := UInt<1>("h00") - meta_write_arb.in[1].bits.way_en := UInt<1>("h00") - meta_write_arb.in[1].bits.idx := UInt<1>("h00") - meta_write_arb.in[1].valid := UInt<1>("h00") - meta_write_arb.reset := UInt<1>("h00") - meta_write_arb.clock := clock - meta_write_arb.reset := reset - inst mem_req_arb of LockingArbiter - mem_req_arb.out.ready := UInt<1>("h00") - mem_req_arb.in[0].bits.union := UInt<1>("h00") - mem_req_arb.in[0].bits.a_type := UInt<1>("h00") - mem_req_arb.in[0].bits.is_builtin_type := UInt<1>("h00") - mem_req_arb.in[0].bits.data := UInt<1>("h00") - mem_req_arb.in[0].bits.addr_beat := UInt<1>("h00") - mem_req_arb.in[0].bits.client_xact_id := UInt<1>("h00") - mem_req_arb.in[0].bits.addr_block := UInt<1>("h00") - mem_req_arb.in[0].valid := UInt<1>("h00") - mem_req_arb.in[1].bits.union := UInt<1>("h00") - mem_req_arb.in[1].bits.a_type := UInt<1>("h00") - mem_req_arb.in[1].bits.is_builtin_type := UInt<1>("h00") - mem_req_arb.in[1].bits.data := UInt<1>("h00") - mem_req_arb.in[1].bits.addr_beat := UInt<1>("h00") - mem_req_arb.in[1].bits.client_xact_id := UInt<1>("h00") - mem_req_arb.in[1].bits.addr_block := UInt<1>("h00") - mem_req_arb.in[1].valid := UInt<1>("h00") - mem_req_arb.reset := UInt<1>("h00") - mem_req_arb.clock := clock - mem_req_arb.reset := reset - inst wb_req_arb of Arbiter_54 - wb_req_arb.out.ready := UInt<1>("h00") - wb_req_arb.in[0].bits.way_en := UInt<1>("h00") - wb_req_arb.in[0].bits.voluntary := UInt<1>("h00") - wb_req_arb.in[0].bits.r_type := UInt<1>("h00") - wb_req_arb.in[0].bits.data := UInt<1>("h00") - wb_req_arb.in[0].bits.addr_beat := UInt<1>("h00") - wb_req_arb.in[0].bits.client_xact_id := UInt<1>("h00") - wb_req_arb.in[0].bits.addr_block := UInt<1>("h00") - wb_req_arb.in[0].valid := UInt<1>("h00") - wb_req_arb.in[1].bits.way_en := UInt<1>("h00") - wb_req_arb.in[1].bits.voluntary := UInt<1>("h00") - wb_req_arb.in[1].bits.r_type := UInt<1>("h00") - wb_req_arb.in[1].bits.data := UInt<1>("h00") - wb_req_arb.in[1].bits.addr_beat := UInt<1>("h00") - wb_req_arb.in[1].bits.client_xact_id := UInt<1>("h00") - wb_req_arb.in[1].bits.addr_block := UInt<1>("h00") - wb_req_arb.in[1].valid := UInt<1>("h00") - wb_req_arb.reset := UInt<1>("h00") - wb_req_arb.clock := clock - wb_req_arb.reset := reset - inst replay_arb of Arbiter_55 - replay_arb.out.ready := UInt<1>("h00") - replay_arb.in[0].bits.sdq_id := UInt<1>("h00") - replay_arb.in[0].bits.phys := UInt<1>("h00") - replay_arb.in[0].bits.kill := UInt<1>("h00") - replay_arb.in[0].bits.typ := UInt<1>("h00") - replay_arb.in[0].bits.cmd := UInt<1>("h00") - replay_arb.in[0].bits.tag := UInt<1>("h00") - replay_arb.in[0].bits.addr := UInt<1>("h00") - replay_arb.in[0].valid := UInt<1>("h00") - replay_arb.in[1].bits.sdq_id := UInt<1>("h00") - replay_arb.in[1].bits.phys := UInt<1>("h00") - replay_arb.in[1].bits.kill := UInt<1>("h00") - replay_arb.in[1].bits.typ := UInt<1>("h00") - replay_arb.in[1].bits.cmd := UInt<1>("h00") - replay_arb.in[1].bits.tag := UInt<1>("h00") - replay_arb.in[1].bits.addr := UInt<1>("h00") - replay_arb.in[1].valid := UInt<1>("h00") - replay_arb.reset := UInt<1>("h00") - replay_arb.clock := clock - replay_arb.reset := reset - inst alloc_arb of Arbiter_56 - alloc_arb.out.ready := UInt<1>("h00") - alloc_arb.in[0].bits := UInt<1>("h00") - alloc_arb.in[0].valid := UInt<1>("h00") - alloc_arb.in[1].bits := UInt<1>("h00") - alloc_arb.in[1].valid := UInt<1>("h00") - alloc_arb.reset := UInt<1>("h00") - alloc_arb.clock := clock - alloc_arb.reset := reset - fence_rdy := UInt<1>("h01") - probe_rdy := UInt<1>("h01") - inst T_1299 of MSHR - T_1299.wb_req.ready := UInt<1>("h00") - T_1299.mem_grant.bits.g_type := UInt<1>("h00") - T_1299.mem_grant.bits.is_builtin_type := UInt<1>("h00") - T_1299.mem_grant.bits.manager_xact_id := UInt<1>("h00") - T_1299.mem_grant.bits.client_xact_id := UInt<1>("h00") - T_1299.mem_grant.bits.data := UInt<1>("h00") - T_1299.mem_grant.bits.addr_beat := UInt<1>("h00") - T_1299.mem_grant.valid := UInt<1>("h00") - T_1299.replay.ready := UInt<1>("h00") - T_1299.meta_write.ready := UInt<1>("h00") - T_1299.meta_read.ready := UInt<1>("h00") - T_1299.mem_req.ready := UInt<1>("h00") - T_1299.req_bits.way_en := UInt<1>("h00") - T_1299.req_bits.old_meta.coh.state := UInt<1>("h00") - T_1299.req_bits.old_meta.tag := UInt<1>("h00") - T_1299.req_bits.tag_match := UInt<1>("h00") - T_1299.req_bits.sdq_id := UInt<1>("h00") - T_1299.req_bits.phys := UInt<1>("h00") - T_1299.req_bits.kill := UInt<1>("h00") - T_1299.req_bits.typ := UInt<1>("h00") - T_1299.req_bits.cmd := UInt<1>("h00") - T_1299.req_bits.tag := UInt<1>("h00") - T_1299.req_bits.addr := UInt<1>("h00") - T_1299.req_sec_val := UInt<1>("h00") - T_1299.req_pri_val := UInt<1>("h00") - T_1299.reset := UInt<1>("h00") - T_1299.clock := clock - T_1299.reset := reset - idxMatch[0] := T_1299.idx_match - tagList[0] := T_1299.tag - node T_1129 = shr(T_1299.wb_req.bits.addr_block, 6) - wbTagList[0] := T_1129 - alloc_arb.in[0].valid := T_1299.req_pri_rdy - T_1299.req_pri_val := alloc_arb.in[0].ready - node T_1130 = and(req.valid, sdq_rdy) - node T_1131 = and(T_1130, tag_match) - T_1299.req_sec_val := T_1131 - T_1299.req_bits <> req.bits - T_1299.req_bits.sdq_id := sdq_alloc_id - meta_read_arb.in[0] <> T_1299.meta_read - meta_write_arb.in[0] <> T_1299.meta_write - mem_req_arb.in[0] <> T_1299.mem_req - wb_req_arb.in[0] <> T_1299.wb_req - replay_arb.in[0] <> T_1299.replay - node T_1133 = eq(mem_grant.bits.client_xact_id, UInt<1>("h00")) - node T_1134 = and(mem_grant.valid, T_1133) - T_1299.mem_grant.valid := T_1134 - T_1299.mem_grant.bits <> mem_grant.bits - refillMux[0] <> T_1299.refill - node T_1135 = or(UInt<1>("h00"), T_1299.req_pri_rdy) - node T_1136 = or(UInt<1>("h00"), T_1299.req_sec_rdy) - node T_1137 = or(UInt<1>("h00"), T_1299.idx_match) - node T_1139 = eq(T_1299.req_pri_rdy, UInt<1>("h00")) - when T_1139 : - fence_rdy := UInt<1>("h00") - skip - node T_1142 = eq(T_1299.probe_rdy, UInt<1>("h00")) - when T_1142 : - probe_rdy := UInt<1>("h00") - skip - inst T_1300 of MSHR_58 - T_1300.wb_req.ready := UInt<1>("h00") - T_1300.mem_grant.bits.g_type := UInt<1>("h00") - T_1300.mem_grant.bits.is_builtin_type := UInt<1>("h00") - T_1300.mem_grant.bits.manager_xact_id := UInt<1>("h00") - T_1300.mem_grant.bits.client_xact_id := UInt<1>("h00") - T_1300.mem_grant.bits.data := UInt<1>("h00") - T_1300.mem_grant.bits.addr_beat := UInt<1>("h00") - T_1300.mem_grant.valid := UInt<1>("h00") - T_1300.replay.ready := UInt<1>("h00") - T_1300.meta_write.ready := UInt<1>("h00") - T_1300.meta_read.ready := UInt<1>("h00") - T_1300.mem_req.ready := UInt<1>("h00") - T_1300.req_bits.way_en := UInt<1>("h00") - T_1300.req_bits.old_meta.coh.state := UInt<1>("h00") - T_1300.req_bits.old_meta.tag := UInt<1>("h00") - T_1300.req_bits.tag_match := UInt<1>("h00") - T_1300.req_bits.sdq_id := UInt<1>("h00") - T_1300.req_bits.phys := UInt<1>("h00") - T_1300.req_bits.kill := UInt<1>("h00") - T_1300.req_bits.typ := UInt<1>("h00") - T_1300.req_bits.cmd := UInt<1>("h00") - T_1300.req_bits.tag := UInt<1>("h00") - T_1300.req_bits.addr := UInt<1>("h00") - T_1300.req_sec_val := UInt<1>("h00") - T_1300.req_pri_val := UInt<1>("h00") - T_1300.reset := UInt<1>("h00") - T_1300.clock := clock - T_1300.reset := reset - idxMatch[1] := T_1300.idx_match - tagList[1] := T_1300.tag - node T_1170 = shr(T_1300.wb_req.bits.addr_block, 6) - wbTagList[1] := T_1170 - alloc_arb.in[1].valid := T_1300.req_pri_rdy - T_1300.req_pri_val := alloc_arb.in[1].ready - node T_1171 = and(req.valid, sdq_rdy) - node T_1172 = and(T_1171, tag_match) - T_1300.req_sec_val := T_1172 - T_1300.req_bits <> req.bits - T_1300.req_bits.sdq_id := sdq_alloc_id - meta_read_arb.in[1] <> T_1300.meta_read - meta_write_arb.in[1] <> T_1300.meta_write - mem_req_arb.in[1] <> T_1300.mem_req - wb_req_arb.in[1] <> T_1300.wb_req - replay_arb.in[1] <> T_1300.replay - node T_1174 = eq(mem_grant.bits.client_xact_id, UInt<1>("h01")) - node T_1175 = and(mem_grant.valid, T_1174) - T_1300.mem_grant.valid := T_1175 - T_1300.mem_grant.bits <> mem_grant.bits - refillMux[1] <> T_1300.refill - node pri_rdy = or(T_1135, T_1300.req_pri_rdy) - node sec_rdy = or(T_1136, T_1300.req_sec_rdy) - node idx_match = or(T_1137, T_1300.idx_match) - node T_1180 = eq(T_1300.req_pri_rdy, UInt<1>("h00")) - when T_1180 : - fence_rdy := UInt<1>("h00") - skip - node T_1183 = eq(T_1300.probe_rdy, UInt<1>("h00")) - when T_1183 : - probe_rdy := UInt<1>("h00") - skip - node T_1185 = and(req.valid, sdq_rdy) - node T_1187 = eq(idx_match, UInt<1>("h00")) - node T_1188 = and(T_1185, T_1187) - alloc_arb.out.ready := T_1188 - meta_read <> meta_read_arb.out - meta_write <> meta_write_arb.out - mem_req <> mem_req_arb.out - wb_req <> wb_req_arb.out - node T_1189 = and(tag_match, sec_rdy) - node T_1190 = mux(idx_match, T_1189, pri_rdy) - node T_1191 = and(T_1190, sdq_rdy) - req.ready := T_1191 - secondary_miss := idx_match - infer accessor T_1192 = refillMux[mem_grant.bits.client_xact_id] - refill <> T_1192 - node T_1195 = and(replay.ready, replay.valid) - node T_1196 = eq(replay.bits.cmd, UInt<5>("h01")) - node T_1197 = eq(replay.bits.cmd, UInt<5>("h07")) - node T_1198 = or(T_1196, T_1197) - node T_1199 = bit(replay.bits.cmd, 3) - node T_1200 = eq(replay.bits.cmd, UInt<5>("h04")) - node T_1201 = or(T_1199, T_1200) - node T_1202 = or(T_1198, T_1201) - node free_sdq = and(T_1195, T_1202) - reg T_1204 : UInt<5>, clock, reset - when free_sdq : - T_1204 := replay_arb.out.bits.sdq_id - skip - infer accessor T_1205 = sdq[T_1204] - replay.bits.data := T_1205 - replay <> replay_arb.out - node T_1206 = or(replay.valid, sdq_enq) - when T_1206 : - node T_1208 = dshl(UInt<1>("h01"), replay_arb.out.bits.sdq_id) - node T_1210 = subw(UInt<17>("h00"), free_sdq) - node T_1211 = and(T_1208, T_1210) - node T_1212 = not(T_1211) - node T_1213 = and(sdq_val, T_1212) - node T_1214 = bits(sdq_val, 16, 0) - node T_1215 = not(T_1214) - node T_1216 = bit(T_1215, 0) - node T_1217 = bit(T_1215, 1) - node T_1218 = bit(T_1215, 2) - node T_1219 = bit(T_1215, 3) - node T_1220 = bit(T_1215, 4) - node T_1221 = bit(T_1215, 5) - node T_1222 = bit(T_1215, 6) - node T_1223 = bit(T_1215, 7) - node T_1224 = bit(T_1215, 8) - node T_1225 = bit(T_1215, 9) - node T_1226 = bit(T_1215, 10) - node T_1227 = bit(T_1215, 11) - node T_1228 = bit(T_1215, 12) - node T_1229 = bit(T_1215, 13) - node T_1230 = bit(T_1215, 14) - node T_1231 = bit(T_1215, 15) - node T_1232 = bit(T_1215, 16) - wire T_1251 : UInt<17>[17] - T_1251[0] := UInt<17>("h01") - T_1251[1] := UInt<17>("h02") - T_1251[2] := UInt<17>("h04") - T_1251[3] := UInt<17>("h08") - T_1251[4] := UInt<17>("h010") - T_1251[5] := UInt<17>("h020") - T_1251[6] := UInt<17>("h040") - T_1251[7] := UInt<17>("h080") - T_1251[8] := UInt<17>("h0100") - T_1251[9] := UInt<17>("h0200") - T_1251[10] := UInt<17>("h0400") - T_1251[11] := UInt<17>("h0800") - T_1251[12] := UInt<17>("h01000") - T_1251[13] := UInt<17>("h02000") - T_1251[14] := UInt<17>("h04000") - T_1251[15] := UInt<17>("h08000") - T_1251[16] := UInt<17>("h010000") - node T_1272 = mux(T_1232, T_1251[16], UInt<17>("h00")) - node T_1273 = mux(T_1231, T_1251[15], T_1272) - node T_1274 = mux(T_1230, T_1251[14], T_1273) - node T_1275 = mux(T_1229, T_1251[13], T_1274) - node T_1276 = mux(T_1228, T_1251[12], T_1275) - node T_1277 = mux(T_1227, T_1251[11], T_1276) - node T_1278 = mux(T_1226, T_1251[10], T_1277) - node T_1279 = mux(T_1225, T_1251[9], T_1278) - node T_1280 = mux(T_1224, T_1251[8], T_1279) - node T_1281 = mux(T_1223, T_1251[7], T_1280) - node T_1282 = mux(T_1222, T_1251[6], T_1281) - node T_1283 = mux(T_1221, T_1251[5], T_1282) - node T_1284 = mux(T_1220, T_1251[4], T_1283) - node T_1285 = mux(T_1219, T_1251[3], T_1284) - node T_1286 = mux(T_1218, T_1251[2], T_1285) - node T_1287 = mux(T_1217, T_1251[1], T_1286) - node T_1288 = mux(T_1216, T_1251[0], T_1287) - node T_1290 = subw(UInt<17>("h00"), sdq_enq) - node T_1291 = and(T_1288, T_1290) - node T_1292 = or(T_1213, T_1291) - sdq_val := T_1292 - skip - - module TLB_60 : - output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} - output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>} - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}} - input clock : Clock - input reset : UInt<1> - - ptw.req.bits.fetch := UInt<1>("h00") - ptw.req.bits.store := UInt<1>("h00") - ptw.req.bits.prv := UInt<1>("h00") - ptw.req.bits.addr := UInt<1>("h00") - ptw.req.valid := UInt<1>("h00") - resp.hit_idx := UInt<1>("h00") - resp.xcpt_if := UInt<1>("h00") - resp.xcpt_st := UInt<1>("h00") - resp.xcpt_ld := UInt<1>("h00") - resp.ppn := UInt<1>("h00") - resp.miss := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg r_refill_tag : UInt, clock, reset - reg r_refill_waddr : UInt, clock, reset - reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset - inst tag_cam of RocketCAM - tag_cam.write_addr := UInt<1>("h00") - tag_cam.write_tag := UInt<1>("h00") - tag_cam.write := UInt<1>("h00") - tag_cam.tag := UInt<1>("h00") - tag_cam.clear_mask := UInt<1>("h00") - tag_cam.clear := UInt<1>("h00") - tag_cam.reset := UInt<1>("h00") - tag_cam.clock := clock - tag_cam.reset := reset - cmem tag_ram : UInt<20>[8], clock - node lookup_tag = cat(req.bits.asid, req.bits.vpn) - tag_cam.tag := lookup_tag - node T_181 = eq(state, UInt<2>("h02")) - node T_182 = and(T_181, ptw.resp.valid) - tag_cam.write := T_182 - tag_cam.write_tag := r_refill_tag - tag_cam.write_addr := r_refill_waddr - node T_183 = bits(tag_cam.hits, 7, 4) - node T_184 = bits(tag_cam.hits, 3, 0) - node T_186 = neq(T_183, UInt<1>("h00")) - node T_187 = or(T_183, T_184) - node T_188 = bits(T_187, 3, 2) - node T_189 = bits(T_187, 1, 0) - node T_191 = neq(T_188, UInt<1>("h00")) - node T_192 = or(T_188, T_189) - node T_193 = bit(T_192, 1) - node T_194 = cat(T_191, T_193) - node tag_hit_addr = cat(T_186, T_194) - reg valid_array : UInt<1>[8], clock, reset - reg ur_array : UInt<1>[8], clock, reset - reg uw_array : UInt<1>[8], clock, reset - reg ux_array : UInt<1>[8], clock, reset - reg sr_array : UInt<1>[8], clock, reset - reg sw_array : UInt<1>[8], clock, reset - reg sx_array : UInt<1>[8], clock, reset - reg dirty_array : UInt<1>[8], clock, reset - when ptw.resp.valid : - infer accessor T_388 = tag_ram[r_refill_waddr] - T_388 := ptw.resp.bits.pte.ppn - infer accessor T_389 = valid_array[r_refill_waddr] - node T_391 = eq(ptw.resp.bits.error, UInt<1>("h00")) - T_389 := T_391 - infer accessor T_392 = ur_array[r_refill_waddr] - node T_394 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_395 = and(ptw.resp.bits.pte.v, T_394) - node T_397 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_398 = and(T_395, T_397) - node T_400 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_401 = and(T_398, T_400) - T_392 := T_401 - infer accessor T_402 = uw_array[r_refill_waddr] - node T_404 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_405 = and(ptw.resp.bits.pte.v, T_404) - node T_407 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_408 = and(T_405, T_407) - node T_409 = bit(ptw.resp.bits.pte.typ, 0) - node T_410 = and(T_408, T_409) - node T_412 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_413 = and(T_410, T_412) - T_402 := T_413 - infer accessor T_414 = ux_array[r_refill_waddr] - node T_416 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_417 = and(ptw.resp.bits.pte.v, T_416) - node T_419 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_420 = and(T_417, T_419) - node T_421 = bit(ptw.resp.bits.pte.typ, 1) - node T_422 = and(T_420, T_421) - node T_424 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_425 = and(T_422, T_424) - T_414 := T_425 - infer accessor T_426 = sr_array[r_refill_waddr] - node T_428 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_429 = and(ptw.resp.bits.pte.v, T_428) - node T_431 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_432 = and(T_429, T_431) - T_426 := T_432 - infer accessor T_433 = sw_array[r_refill_waddr] - node T_435 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_436 = and(ptw.resp.bits.pte.v, T_435) - node T_437 = bit(ptw.resp.bits.pte.typ, 0) - node T_438 = and(T_436, T_437) - node T_440 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_441 = and(T_438, T_440) - T_433 := T_441 - infer accessor T_442 = sx_array[r_refill_waddr] - node T_444 = geq(ptw.resp.bits.pte.typ, UInt<3>("h04")) - node T_445 = and(ptw.resp.bits.pte.v, T_444) - node T_446 = bit(ptw.resp.bits.pte.typ, 1) - node T_447 = and(T_445, T_446) - node T_449 = eq(ptw.resp.bits.error, UInt<1>("h00")) - node T_450 = and(T_447, T_449) - T_442 := T_450 - infer accessor T_451 = dirty_array[r_refill_waddr] - T_451 := ptw.resp.bits.pte.d - skip - node T_452 = not(tag_cam.valid_bits) - node T_454 = eq(T_452, UInt<1>("h00")) - node has_invalid_entry = eq(T_454, UInt<1>("h00")) - node T_457 = not(tag_cam.valid_bits) - node T_458 = bit(T_457, 0) - node T_459 = bit(T_457, 1) - node T_460 = bit(T_457, 2) - node T_461 = bit(T_457, 3) - node T_462 = bit(T_457, 4) - node T_463 = bit(T_457, 5) - node T_464 = bit(T_457, 6) - node T_465 = bit(T_457, 7) - wire T_467 : UInt<1>[8] - T_467[0] := T_458 - T_467[1] := T_459 - T_467[2] := T_460 - T_467[3] := T_461 - T_467[4] := T_462 - T_467[5] := T_463 - T_467[6] := T_464 - T_467[7] := T_465 - node T_485 = mux(T_467[6], UInt<3>("h06"), UInt<3>("h07")) - node T_486 = mux(T_467[5], UInt<3>("h05"), T_485) - node T_487 = mux(T_467[4], UInt<3>("h04"), T_486) - node T_488 = mux(T_467[3], UInt<2>("h03"), T_487) - node T_489 = mux(T_467[2], UInt<2>("h02"), T_488) - node T_490 = mux(T_467[1], UInt<1>("h01"), T_489) - node invalid_entry = mux(T_467[0], UInt<1>("h00"), T_490) - reg T_493 : UInt<8>, clock, reset - node T_495 = dshr(T_493, UInt<1>("h01")) - node T_496 = bit(T_495, 0) - node T_497 = cat(UInt<1>("h01"), T_496) - node T_498 = dshr(T_493, T_497) - node T_499 = bit(T_498, 0) - node T_500 = cat(T_497, T_499) - node T_501 = dshr(T_493, T_500) - node T_502 = bit(T_501, 0) - node T_503 = cat(T_500, T_502) - node T_504 = bits(T_503, 2, 0) - node repl_waddr = mux(has_invalid_entry, invalid_entry, T_504) - node T_507 = eq(req.bits.instruction, UInt<1>("h00")) - node T_508 = and(ptw.status.mprv, T_507) - node priv = mux(T_508, ptw.status.prv1, ptw.status.prv) - node priv_s = eq(priv, UInt<1>("h01")) - node priv_uses_vm = leq(priv, UInt<1>("h01")) - node T_515 = eq(r_req.store, UInt<1>("h00")) - node T_516 = or(r_req.instruction, r_req.store) - node T_518 = eq(T_516, UInt<1>("h00")) - node T_519 = cat(r_req.store, T_518) - node req_xwr = cat(T_515, T_519) - node T_521 = cat(sr_array[7], sr_array[6]) - node T_522 = cat(sr_array[5], sr_array[4]) - node T_523 = cat(T_521, T_522) - node T_524 = cat(sr_array[3], sr_array[2]) - node T_525 = cat(sr_array[1], sr_array[0]) - node T_526 = cat(T_524, T_525) - node T_527 = cat(T_523, T_526) - node T_528 = cat(ur_array[7], ur_array[6]) - node T_529 = cat(ur_array[5], ur_array[4]) - node T_530 = cat(T_528, T_529) - node T_531 = cat(ur_array[3], ur_array[2]) - node T_532 = cat(ur_array[1], ur_array[0]) - node T_533 = cat(T_531, T_532) - node T_534 = cat(T_530, T_533) - node r_array = mux(priv_s, T_527, T_534) - node T_536 = cat(sw_array[7], sw_array[6]) - node T_537 = cat(sw_array[5], sw_array[4]) - node T_538 = cat(T_536, T_537) - node T_539 = cat(sw_array[3], sw_array[2]) - node T_540 = cat(sw_array[1], sw_array[0]) - node T_541 = cat(T_539, T_540) - node T_542 = cat(T_538, T_541) - node T_543 = cat(uw_array[7], uw_array[6]) - node T_544 = cat(uw_array[5], uw_array[4]) - node T_545 = cat(T_543, T_544) - node T_546 = cat(uw_array[3], uw_array[2]) - node T_547 = cat(uw_array[1], uw_array[0]) - node T_548 = cat(T_546, T_547) - node T_549 = cat(T_545, T_548) - node w_array = mux(priv_s, T_542, T_549) - node T_551 = cat(sx_array[7], sx_array[6]) - node T_552 = cat(sx_array[5], sx_array[4]) - node T_553 = cat(T_551, T_552) - node T_554 = cat(sx_array[3], sx_array[2]) - node T_555 = cat(sx_array[1], sx_array[0]) - node T_556 = cat(T_554, T_555) - node T_557 = cat(T_553, T_556) - node T_558 = cat(ux_array[7], ux_array[6]) - node T_559 = cat(ux_array[5], ux_array[4]) - node T_560 = cat(T_558, T_559) - node T_561 = cat(ux_array[3], ux_array[2]) - node T_562 = cat(ux_array[1], ux_array[0]) - node T_563 = cat(T_561, T_562) - node T_564 = cat(T_560, T_563) - node x_array = mux(priv_s, T_557, T_564) - node T_566 = bit(ptw.status.vm, 3) - node vm_enabled = and(T_566, priv_uses_vm) - node T_568 = bit(req.bits.vpn, 27) - node T_569 = bit(req.bits.vpn, 26) - node bad_va = neq(T_568, T_569) - node T_571 = cat(dirty_array[7], dirty_array[6]) - node T_572 = cat(dirty_array[5], dirty_array[4]) - node T_573 = cat(T_571, T_572) - node T_574 = cat(dirty_array[3], dirty_array[2]) - node T_575 = cat(dirty_array[1], dirty_array[0]) - node T_576 = cat(T_574, T_575) - node T_577 = cat(T_573, T_576) - node T_579 = mux(req.bits.store, w_array, UInt<1>("h00")) - node T_580 = not(T_579) - node T_581 = or(T_577, T_580) - node tag_hits = and(tag_cam.hits, T_581) - node tag_hit = neq(tag_hits, UInt<1>("h00")) - node tlb_hit = and(vm_enabled, tag_hit) - node T_587 = eq(tag_hit, UInt<1>("h00")) - node T_588 = and(vm_enabled, T_587) - node T_590 = eq(bad_va, UInt<1>("h00")) - node tlb_miss = and(T_588, T_590) - node T_592 = and(req.valid, tlb_hit) - when T_592 : - node T_593 = bits(tag_cam.hits, 7, 4) - node T_594 = bits(tag_cam.hits, 3, 0) - node T_596 = neq(T_593, UInt<1>("h00")) - node T_597 = or(T_593, T_594) - node T_598 = bits(T_597, 3, 2) - node T_599 = bits(T_597, 1, 0) - node T_601 = neq(T_598, UInt<1>("h00")) - node T_602 = or(T_598, T_599) - node T_603 = bit(T_602, 1) - node T_604 = cat(T_601, T_603) - node T_605 = cat(T_596, T_604) - node T_607 = bit(T_605, 2) - node T_609 = dshl(UInt<8>("h01"), UInt<1>("h01")) - node T_610 = bits(T_609, 7, 0) - node T_611 = not(T_610) - node T_612 = and(T_493, T_611) - node T_614 = mux(T_607, UInt<1>("h00"), T_610) - node T_615 = or(T_612, T_614) - node T_616 = cat(UInt<1>("h01"), T_607) - node T_617 = bit(T_605, 1) - node T_619 = dshl(UInt<8>("h01"), T_616) - node T_620 = bits(T_619, 7, 0) - node T_621 = not(T_620) - node T_622 = and(T_615, T_621) - node T_624 = mux(T_617, UInt<1>("h00"), T_620) - node T_625 = or(T_622, T_624) - node T_626 = cat(T_616, T_617) - node T_627 = bit(T_605, 0) - node T_629 = dshl(UInt<8>("h01"), T_626) - node T_630 = bits(T_629, 7, 0) - node T_631 = not(T_630) - node T_632 = and(T_625, T_631) - node T_634 = mux(T_627, UInt<1>("h00"), T_630) - node T_635 = or(T_632, T_634) - node T_636 = cat(T_626, T_627) - T_493 := T_635 - skip - node T_637 = eq(state, UInt<1>("h00")) - req.ready := T_637 - node T_638 = and(r_array, tag_cam.hits) - node T_640 = neq(T_638, UInt<1>("h00")) - node T_642 = eq(T_640, UInt<1>("h00")) - node T_643 = and(tlb_hit, T_642) - node T_644 = or(bad_va, T_643) - resp.xcpt_ld := T_644 - node T_645 = and(w_array, tag_cam.hits) - node T_647 = neq(T_645, UInt<1>("h00")) - node T_649 = eq(T_647, UInt<1>("h00")) - node T_650 = and(tlb_hit, T_649) - node T_651 = or(bad_va, T_650) - resp.xcpt_st := T_651 - node T_652 = and(x_array, tag_cam.hits) - node T_654 = neq(T_652, UInt<1>("h00")) - node T_656 = eq(T_654, UInt<1>("h00")) - node T_657 = and(tlb_hit, T_656) - node T_658 = or(bad_va, T_657) - resp.xcpt_if := T_658 - resp.miss := tlb_miss - node T_660 = eq(req.bits.passthrough, UInt<1>("h00")) - node T_661 = and(vm_enabled, T_660) - node T_662 = bit(tag_cam.hits, 0) - node T_663 = bit(tag_cam.hits, 1) - node T_664 = bit(tag_cam.hits, 2) - node T_665 = bit(tag_cam.hits, 3) - node T_666 = bit(tag_cam.hits, 4) - node T_667 = bit(tag_cam.hits, 5) - node T_668 = bit(tag_cam.hits, 6) - node T_669 = bit(tag_cam.hits, 7) - infer accessor T_671 = tag_ram[UInt<1>("h00")] - infer accessor T_673 = tag_ram[UInt<1>("h01")] - infer accessor T_675 = tag_ram[UInt<2>("h02")] - infer accessor T_677 = tag_ram[UInt<2>("h03")] - infer accessor T_679 = tag_ram[UInt<3>("h04")] - infer accessor T_681 = tag_ram[UInt<3>("h05")] - infer accessor T_683 = tag_ram[UInt<3>("h06")] - infer accessor T_685 = tag_ram[UInt<3>("h07")] - node T_687 = mux(T_662, T_671, UInt<1>("h00")) - node T_689 = mux(T_663, T_673, UInt<1>("h00")) - node T_691 = mux(T_664, T_675, UInt<1>("h00")) - node T_693 = mux(T_665, T_677, UInt<1>("h00")) - node T_695 = mux(T_666, T_679, UInt<1>("h00")) - node T_697 = mux(T_667, T_681, UInt<1>("h00")) - node T_699 = mux(T_668, T_683, UInt<1>("h00")) - node T_701 = mux(T_669, T_685, UInt<1>("h00")) - node T_703 = or(T_687, T_689) - node T_704 = or(T_703, T_691) - node T_705 = or(T_704, T_693) - node T_706 = or(T_705, T_695) - node T_707 = or(T_706, T_697) - node T_708 = or(T_707, T_699) - node T_709 = or(T_708, T_701) - wire T_710 : UInt<20> - T_710 := UInt<1>("h00") - T_710 := T_709 - node T_712 = bits(req.bits.vpn, 19, 0) - node T_713 = mux(T_661, T_710, T_712) - resp.ppn := T_713 - resp.hit_idx := tag_cam.hits - node T_714 = and(req.ready, req.valid) - node T_715 = or(ptw.invalidate, T_714) - tag_cam.clear := T_715 - node T_716 = cat(valid_array[7], valid_array[6]) - node T_717 = cat(valid_array[5], valid_array[4]) - node T_718 = cat(T_716, T_717) - node T_719 = cat(valid_array[3], valid_array[2]) - node T_720 = cat(valid_array[1], valid_array[0]) - node T_721 = cat(T_719, T_720) - node T_722 = cat(T_718, T_721) - node T_723 = not(T_722) - node T_724 = not(tag_hits) - node T_725 = and(tag_cam.hits, T_724) - node T_726 = or(T_723, T_725) - tag_cam.clear_mask := T_726 - when ptw.invalidate : - node T_728 = not(UInt<8>("h00")) - tag_cam.clear_mask := T_728 - skip - node T_729 = eq(state, UInt<1>("h01")) - ptw.req.valid := T_729 - ptw.req.bits.addr := r_refill_tag - ptw.req.bits.prv := ptw.status.prv - ptw.req.bits.store := r_req.store - ptw.req.bits.fetch := r_req.instruction - node T_730 = and(req.ready, req.valid) - node T_731 = and(T_730, tlb_miss) - when T_731 : - state := UInt<1>("h01") - r_refill_tag := lookup_tag - r_refill_waddr := repl_waddr - r_req <> req.bits - skip - node T_732 = eq(state, UInt<1>("h01")) - when T_732 : - when ptw.invalidate : - state := UInt<1>("h00") - skip - when ptw.req.ready : - state := UInt<2>("h02") - when ptw.invalidate : - state := UInt<2>("h03") - skip - skip - skip - node T_733 = eq(state, UInt<2>("h02")) - node T_734 = and(T_733, ptw.invalidate) - when T_734 : - state := UInt<2>("h03") - skip - when ptw.resp.valid : - state := UInt<1>("h00") - skip - - module MetadataArray : - output resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} - input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}} - input clock : Clock - input reset : UInt<1> - - write.ready := UInt<1>("h00") - read.ready := UInt<1>("h00") - wire T_53 : {state : UInt<2>} - T_53.state := UInt<1>("h00") - T_53.state := UInt<1>("h00") - wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} - rstVal.coh.state := UInt<1>("h00") - rstVal.tag := UInt<1>("h00") - rstVal.tag := UInt<1>("h00") - rstVal.coh <> T_53 - reg rst_cnt : UInt<7>, clock, reset - onreset rst_cnt := UInt<7>("h00") - node rst = lt(rst_cnt, UInt<7>("h040")) - node waddr = mux(rst, rst_cnt, write.bits.idx) - wire T_557 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_557 <> write.bits.data - when rst : - T_557 <> rstVal - skip - node wdata = cat(T_557.tag, T_557.coh.state) - node T_586 = asSInt(write.bits.way_en) - node T_587 = mux(rst, asSInt(UInt<1>("h01")), T_586) - node wmask = asUInt(T_587) - when rst : - node T_590 = addw(rst_cnt, UInt<1>("h01")) - rst_cnt := T_590 - skip - cmem T_593 : UInt<88>[64], clock - node T_594 = or(rst, write.valid) - when T_594 : - node T_595 = cat(wdata, wdata) - node T_596 = cat(T_595, T_595) - node T_597 = bit(wmask, 0) - node T_598 = bit(wmask, 1) - node T_599 = bit(wmask, 2) - node T_600 = bit(wmask, 3) - wire T_602 : UInt<1>[4] - T_602[0] := T_597 - T_602[1] := T_598 - T_602[2] := T_599 - T_602[3] := T_600 - node T_609 = subw(UInt<22>("h00"), T_602[0]) - node T_611 = subw(UInt<22>("h00"), T_602[1]) - node T_613 = subw(UInt<22>("h00"), T_602[2]) - node T_615 = subw(UInt<22>("h00"), T_602[3]) - wire T_617 : UInt<22>[4] - T_617[0] := T_609 - T_617[1] := T_611 - T_617[2] := T_613 - T_617[3] := T_615 - node T_623 = cat(T_617[3], T_617[2]) - node T_624 = cat(T_617[1], T_617[0]) - node T_625 = cat(T_623, T_624) - infer accessor T_626 = T_593[waddr] - node T_627 = not(T_625) - node T_628 = and(T_626, T_627) - node T_629 = and(T_596, T_625) - node T_630 = or(T_628, T_629) - wire T_631 : UInt<88> - T_631 := UInt<1>("h00") - T_631 := T_630 - infer accessor T_633 = T_593[waddr] - T_633 := T_631 - skip - reg T_634 : UInt<6>, clock, reset - when read.valid : - T_634 := read.bits.idx - skip - infer accessor tags = T_593[T_634] - wire T_880 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_880[0].coh.state := UInt<1>("h00") - T_880[0].tag := UInt<1>("h00") - T_880[1].coh.state := UInt<1>("h00") - T_880[1].tag := UInt<1>("h00") - T_880[2].coh.state := UInt<1>("h00") - T_880[2].tag := UInt<1>("h00") - T_880[3].coh.state := UInt<1>("h00") - T_880[3].tag := UInt<1>("h00") - node T_1024 = bits(tags, 1, 0) - T_880[0].coh.state := T_1024 - node T_1025 = bits(tags, 21, 2) - T_880[0].tag := T_1025 - node T_1026 = bits(tags, 23, 22) - T_880[1].coh.state := T_1026 - node T_1027 = bits(tags, 43, 24) - T_880[1].tag := T_1027 - node T_1028 = bits(tags, 45, 44) - T_880[2].coh.state := T_1028 - node T_1029 = bits(tags, 65, 46) - T_880[2].tag := T_1029 - node T_1030 = bits(tags, 67, 66) - T_880[3].coh.state := T_1030 - node T_1031 = bits(tags, 87, 68) - T_880[3].tag := T_1031 - resp := T_880 - node T_1033 = eq(rst, UInt<1>("h00")) - node T_1035 = eq(write.valid, UInt<1>("h00")) - node T_1036 = and(T_1033, T_1035) - read.ready := T_1036 - node T_1038 = eq(rst, UInt<1>("h00")) - write.ready := T_1038 - - module Arbiter_62 : - output chosen : UInt<3> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.idx := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - in[3].ready := UInt<1>("h00") - in[4].ready := UInt<1>("h00") - wire T_128 : UInt<3> - T_128 := UInt<1>("h00") - infer accessor T_130 = in[T_128] - out.valid := T_130.valid - infer accessor T_137 = in[T_128] - out.bits <> T_137.bits - chosen := T_128 - infer accessor T_144 = in[T_128] - T_144.ready := UInt<1>("h00") - node T_154 = or(UInt<1>("h00"), in[0].valid) - node T_156 = eq(T_154, UInt<1>("h00")) - node T_158 = or(UInt<1>("h00"), in[0].valid) - node T_159 = or(T_158, in[1].valid) - node T_161 = eq(T_159, UInt<1>("h00")) - node T_163 = or(UInt<1>("h00"), in[0].valid) - node T_164 = or(T_163, in[1].valid) - node T_165 = or(T_164, in[2].valid) - node T_167 = eq(T_165, UInt<1>("h00")) - node T_169 = or(UInt<1>("h00"), in[0].valid) - node T_170 = or(T_169, in[1].valid) - node T_171 = or(T_170, in[2].valid) - node T_172 = or(T_171, in[3].valid) - node T_174 = eq(T_172, UInt<1>("h00")) - node T_176 = eq(UInt<3>("h04"), UInt<1>("h00")) - node T_177 = mux(UInt<1>("h00"), T_176, UInt<1>("h01")) - node T_178 = and(T_177, out.ready) - in[0].ready := T_178 - node T_180 = eq(UInt<3>("h04"), UInt<1>("h01")) - node T_181 = mux(UInt<1>("h00"), T_180, T_156) - node T_182 = and(T_181, out.ready) - in[1].ready := T_182 - node T_184 = eq(UInt<3>("h04"), UInt<2>("h02")) - node T_185 = mux(UInt<1>("h00"), T_184, T_161) - node T_186 = and(T_185, out.ready) - in[2].ready := T_186 - node T_188 = eq(UInt<3>("h04"), UInt<2>("h03")) - node T_189 = mux(UInt<1>("h00"), T_188, T_167) - node T_190 = and(T_189, out.ready) - in[3].ready := T_190 - node T_192 = eq(UInt<3>("h04"), UInt<3>("h04")) - node T_193 = mux(UInt<1>("h00"), T_192, T_174) - node T_194 = and(T_193, out.ready) - in[4].ready := T_194 - node T_197 = mux(in[3].valid, UInt<2>("h03"), UInt<3>("h04")) - node T_199 = mux(in[2].valid, UInt<2>("h02"), T_197) - node T_201 = mux(in[1].valid, UInt<1>("h01"), T_199) - node T_203 = mux(in[0].valid, UInt<1>("h00"), T_201) - node T_204 = mux(UInt<1>("h00"), UInt<3>("h04"), T_203) - T_128 := T_204 - - module DataArray : - output resp : UInt<128>[4] - input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} - input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} - input clock : Clock - input reset : UInt<1> - - resp[0] := UInt<1>("h00") - resp[1] := UInt<1>("h00") - resp[2] := UInt<1>("h00") - resp[3] := UInt<1>("h00") - write.ready := UInt<1>("h00") - read.ready := UInt<1>("h00") - node waddr = shr(write.bits.addr, 4) - node raddr = shr(read.bits.addr, 4) - node T_65 = bits(write.bits.way_en, 1, 0) - node T_66 = bits(read.bits.way_en, 1, 0) - wire T_75 : UInt<128>[2] - T_75[0] := UInt<1>("h00") - T_75[1] := UInt<1>("h00") - reg T_81 : UInt<12>, clock, reset - when read.valid : - T_81 := read.bits.addr - skip - cmem T_84 : UInt<128>[256], clock - node T_86 = neq(T_65, UInt<1>("h00")) - node T_87 = and(T_86, write.valid) - node T_88 = bit(write.bits.wmask, 0) - node T_89 = and(T_87, T_88) - when T_89 : - node T_90 = bits(write.bits.data, 63, 0) - node T_91 = cat(T_90, T_90) - node T_92 = bit(T_65, 0) - node T_93 = bit(T_65, 1) - wire T_95 : UInt<1>[2] - T_95[0] := T_92 - T_95[1] := T_93 - node T_100 = subw(UInt<64>("h00"), T_95[0]) - node T_102 = subw(UInt<64>("h00"), T_95[1]) - wire T_104 : UInt<64>[2] - T_104[0] := T_100 - T_104[1] := T_102 - node T_108 = cat(T_104[1], T_104[0]) - infer accessor T_109 = T_84[waddr] - node T_110 = not(T_108) - node T_111 = and(T_109, T_110) - node T_112 = and(T_91, T_108) - node T_113 = or(T_111, T_112) - wire T_114 : UInt<128> - T_114 := UInt<1>("h00") - T_114 := T_113 - infer accessor T_116 = T_84[waddr] - T_116 := T_114 - skip - node T_118 = neq(T_66, UInt<1>("h00")) - node T_119 = and(T_118, read.valid) - reg T_120 : UInt<8>, clock, reset - when T_119 : - T_120 := raddr - skip - infer accessor T_121 = T_84[T_120] - T_75[0] := T_121 - cmem T_124 : UInt<128>[256], clock - node T_126 = neq(T_65, UInt<1>("h00")) - node T_127 = and(T_126, write.valid) - node T_128 = bit(write.bits.wmask, 1) - node T_129 = and(T_127, T_128) - when T_129 : - node T_130 = bits(write.bits.data, 127, 64) - node T_131 = cat(T_130, T_130) - node T_132 = bit(T_65, 0) - node T_133 = bit(T_65, 1) - wire T_135 : UInt<1>[2] - T_135[0] := T_132 - T_135[1] := T_133 - node T_140 = subw(UInt<64>("h00"), T_135[0]) - node T_142 = subw(UInt<64>("h00"), T_135[1]) - wire T_144 : UInt<64>[2] - T_144[0] := T_140 - T_144[1] := T_142 - node T_148 = cat(T_144[1], T_144[0]) - infer accessor T_149 = T_124[waddr] - node T_150 = not(T_148) - node T_151 = and(T_149, T_150) - node T_152 = and(T_131, T_148) - node T_153 = or(T_151, T_152) - wire T_154 : UInt<128> - T_154 := UInt<1>("h00") - T_154 := T_153 - infer accessor T_156 = T_124[waddr] - T_156 := T_154 - skip - node T_158 = neq(T_66, UInt<1>("h00")) - node T_159 = and(T_158, read.valid) - reg T_160 : UInt<8>, clock, reset - when T_159 : - T_160 := raddr - skip - infer accessor T_161 = T_124[T_160] - T_75[1] := T_161 - node T_162 = bits(T_75[0], 63, 0) - node T_163 = bits(T_75[1], 63, 0) - wire T_165 : UInt<64>[2] - T_165[0] := T_162 - T_165[1] := T_163 - node T_169 = bits(T_81, 3, 3) - infer accessor T_170 = T_165[T_169] - wire T_172 : UInt<64>[2] - T_172[0] := T_170 - T_172[1] := T_165[1] - node T_176 = cat(T_172[1], T_172[0]) - resp[0] := T_176 - node T_177 = bits(T_75[0], 127, 64) - node T_178 = bits(T_75[1], 127, 64) - wire T_180 : UInt<64>[2] - T_180[0] := T_177 - T_180[1] := T_178 - node T_184 = bits(T_81, 3, 3) - infer accessor T_185 = T_180[T_184] - wire T_187 : UInt<64>[2] - T_187[0] := T_185 - T_187[1] := T_180[1] - node T_191 = cat(T_187[1], T_187[0]) - resp[1] := T_191 - node T_192 = bits(write.bits.way_en, 3, 2) - node T_193 = bits(read.bits.way_en, 3, 2) - wire T_202 : UInt<128>[2] - T_202[0] := UInt<1>("h00") - T_202[1] := UInt<1>("h00") - reg T_208 : UInt<12>, clock, reset - when read.valid : - T_208 := read.bits.addr - skip - cmem T_211 : UInt<128>[256], clock - node T_213 = neq(T_192, UInt<1>("h00")) - node T_214 = and(T_213, write.valid) - node T_215 = bit(write.bits.wmask, 0) - node T_216 = and(T_214, T_215) - when T_216 : - node T_217 = bits(write.bits.data, 63, 0) - node T_218 = cat(T_217, T_217) - node T_219 = bit(T_192, 0) - node T_220 = bit(T_192, 1) - wire T_222 : UInt<1>[2] - T_222[0] := T_219 - T_222[1] := T_220 - node T_227 = subw(UInt<64>("h00"), T_222[0]) - node T_229 = subw(UInt<64>("h00"), T_222[1]) - wire T_231 : UInt<64>[2] - T_231[0] := T_227 - T_231[1] := T_229 - node T_235 = cat(T_231[1], T_231[0]) - infer accessor T_236 = T_211[waddr] - node T_237 = not(T_235) - node T_238 = and(T_236, T_237) - node T_239 = and(T_218, T_235) - node T_240 = or(T_238, T_239) - wire T_241 : UInt<128> - T_241 := UInt<1>("h00") - T_241 := T_240 - infer accessor T_243 = T_211[waddr] - T_243 := T_241 - skip - node T_245 = neq(T_193, UInt<1>("h00")) - node T_246 = and(T_245, read.valid) - reg T_247 : UInt<8>, clock, reset - when T_246 : - T_247 := raddr - skip - infer accessor T_248 = T_211[T_247] - T_202[0] := T_248 - cmem T_251 : UInt<128>[256], clock - node T_253 = neq(T_192, UInt<1>("h00")) - node T_254 = and(T_253, write.valid) - node T_255 = bit(write.bits.wmask, 1) - node T_256 = and(T_254, T_255) - when T_256 : - node T_257 = bits(write.bits.data, 127, 64) - node T_258 = cat(T_257, T_257) - node T_259 = bit(T_192, 0) - node T_260 = bit(T_192, 1) - wire T_262 : UInt<1>[2] - T_262[0] := T_259 - T_262[1] := T_260 - node T_267 = subw(UInt<64>("h00"), T_262[0]) - node T_269 = subw(UInt<64>("h00"), T_262[1]) - wire T_271 : UInt<64>[2] - T_271[0] := T_267 - T_271[1] := T_269 - node T_275 = cat(T_271[1], T_271[0]) - infer accessor T_276 = T_251[waddr] - node T_277 = not(T_275) - node T_278 = and(T_276, T_277) - node T_279 = and(T_258, T_275) - node T_280 = or(T_278, T_279) - wire T_281 : UInt<128> - T_281 := UInt<1>("h00") - T_281 := T_280 - infer accessor T_283 = T_251[waddr] - T_283 := T_281 - skip - node T_285 = neq(T_193, UInt<1>("h00")) - node T_286 = and(T_285, read.valid) - reg T_287 : UInt<8>, clock, reset - when T_286 : - T_287 := raddr - skip - infer accessor T_288 = T_251[T_287] - T_202[1] := T_288 - node T_289 = bits(T_202[0], 63, 0) - node T_290 = bits(T_202[1], 63, 0) - wire T_292 : UInt<64>[2] - T_292[0] := T_289 - T_292[1] := T_290 - node T_296 = bits(T_208, 3, 3) - infer accessor T_297 = T_292[T_296] - wire T_299 : UInt<64>[2] - T_299[0] := T_297 - T_299[1] := T_292[1] - node T_303 = cat(T_299[1], T_299[0]) - resp[2] := T_303 - node T_304 = bits(T_202[0], 127, 64) - node T_305 = bits(T_202[1], 127, 64) - wire T_307 : UInt<64>[2] - T_307[0] := T_304 - T_307[1] := T_305 - node T_311 = bits(T_208, 3, 3) - infer accessor T_312 = T_307[T_311] - wire T_314 : UInt<64>[2] - T_314[0] := T_312 - T_314[1] := T_307[1] - node T_318 = cat(T_314[1], T_314[0]) - resp[3] := T_318 - read.ready := UInt<1>("h01") - write.ready := UInt<1>("h01") - - module Arbiter_64 : - output chosen : UInt<2> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.addr := UInt<1>("h00") - out.bits.way_en := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - in[2].ready := UInt<1>("h00") - in[3].ready := UInt<1>("h00") - wire T_144 : UInt<2> - T_144 := UInt<1>("h00") - infer accessor T_146 = in[T_144] - out.valid := T_146.valid - infer accessor T_155 = in[T_144] - out.bits <> T_155.bits - chosen := T_144 - infer accessor T_164 = in[T_144] - T_164.ready := UInt<1>("h00") - node T_176 = or(UInt<1>("h00"), in[0].valid) - node T_178 = eq(T_176, UInt<1>("h00")) - node T_180 = or(UInt<1>("h00"), in[0].valid) - node T_181 = or(T_180, in[1].valid) - node T_183 = eq(T_181, UInt<1>("h00")) - node T_185 = or(UInt<1>("h00"), in[0].valid) - node T_186 = or(T_185, in[1].valid) - node T_187 = or(T_186, in[2].valid) - node T_189 = eq(T_187, UInt<1>("h00")) - node T_191 = eq(UInt<2>("h03"), UInt<1>("h00")) - node T_192 = mux(UInt<1>("h00"), T_191, UInt<1>("h01")) - node T_193 = and(T_192, out.ready) - in[0].ready := T_193 - node T_195 = eq(UInt<2>("h03"), UInt<1>("h01")) - node T_196 = mux(UInt<1>("h00"), T_195, T_178) - node T_197 = and(T_196, out.ready) - in[1].ready := T_197 - node T_199 = eq(UInt<2>("h03"), UInt<2>("h02")) - node T_200 = mux(UInt<1>("h00"), T_199, T_183) - node T_201 = and(T_200, out.ready) - in[2].ready := T_201 - node T_203 = eq(UInt<2>("h03"), UInt<2>("h03")) - node T_204 = mux(UInt<1>("h00"), T_203, T_189) - node T_205 = and(T_204, out.ready) - in[3].ready := T_205 - node T_208 = mux(in[2].valid, UInt<2>("h02"), UInt<2>("h03")) - node T_210 = mux(in[1].valid, UInt<1>("h01"), T_208) - node T_212 = mux(in[0].valid, UInt<1>("h00"), T_210) - node T_213 = mux(UInt<1>("h00"), UInt<2>("h03"), T_212) - T_144 := T_213 - - module Arbiter_65 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.wmask := UInt<1>("h00") - out.bits.addr := UInt<1>("h00") - out.bits.way_en := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_152 : UInt<1> - T_152 := UInt<1>("h00") - infer accessor T_154 = in[T_152] - out.valid := T_154.valid - infer accessor T_167 = in[T_152] - out.bits <> T_167.bits - chosen := T_152 - infer accessor T_180 = in[T_152] - T_180.ready := UInt<1>("h00") - node T_196 = or(UInt<1>("h00"), in[0].valid) - node T_198 = eq(T_196, UInt<1>("h00")) - node T_200 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_201 = mux(UInt<1>("h00"), T_200, UInt<1>("h01")) - node T_202 = and(T_201, out.ready) - in[0].ready := T_202 - node T_204 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_205 = mux(UInt<1>("h00"), T_204, T_198) - node T_206 = and(T_205, out.ready) - in[1].ready := T_206 - node T_209 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_210 = mux(UInt<1>("h00"), UInt<1>("h01"), T_209) - T_152 := T_210 - - module AMOALU : - output out : UInt<64> - input rhs : UInt<64> - input lhs : UInt<64> - input typ : UInt<3> - input cmd : UInt<5> - input addr : UInt<6> - input clock : Clock - input reset : UInt<1> - - out := UInt<1>("h00") - node T_11 = eq(typ, UInt<3>("h00")) - node T_12 = eq(typ, UInt<3>("h04")) - node T_13 = or(T_11, T_12) - node T_14 = eq(typ, UInt<3>("h01")) - node T_15 = eq(typ, UInt<3>("h05")) - node T_16 = or(T_14, T_15) - node T_17 = eq(typ, UInt<3>("h02")) - node T_18 = eq(typ, UInt<3>("h06")) - node T_19 = or(T_17, T_18) - node T_20 = bits(rhs, 31, 0) - node T_21 = cat(T_20, T_20) - node rhs_1 = mux(T_19, T_21, rhs) - node T_23 = eq(cmd, UInt<5>("h0c")) - node T_24 = eq(cmd, UInt<5>("h0d")) - node sgned = or(T_23, T_24) - node T_26 = eq(cmd, UInt<5>("h0d")) - node T_27 = eq(cmd, UInt<5>("h0f")) - node max = or(T_26, T_27) - node T_29 = eq(cmd, UInt<5>("h0c")) - node T_30 = eq(cmd, UInt<5>("h0e")) - node min = or(T_29, T_30) - node T_32 = eq(typ, UInt<3>("h02")) - node T_33 = eq(typ, UInt<3>("h06")) - node T_34 = or(T_32, T_33) - node T_35 = eq(typ, UInt<3>("h00")) - node T_36 = or(T_34, T_35) - node T_37 = eq(typ, UInt<3>("h04")) - node word = or(T_36, T_37) - node T_40 = not(UInt<64>("h00")) - node T_41 = bit(addr, 2) - node T_42 = shl(T_41, 31) - node mask = xor(T_40, T_42) - node T_44 = and(lhs, mask) - node T_45 = and(rhs_1, mask) - node adder_out = addw(T_44, T_45) - node T_47 = bit(addr, 2) - node T_49 = eq(T_47, UInt<1>("h00")) - node T_50 = and(word, T_49) - node T_51 = bit(lhs, 31) - node T_52 = bit(lhs, 63) - node cmp_lhs = mux(T_50, T_51, T_52) - node T_54 = bit(addr, 2) - node T_56 = eq(T_54, UInt<1>("h00")) - node T_57 = and(word, T_56) - node T_58 = bit(rhs_1, 31) - node T_59 = bit(rhs_1, 63) - node cmp_rhs = mux(T_57, T_58, T_59) - node T_61 = bits(lhs, 31, 0) - node T_62 = bits(rhs_1, 31, 0) - node lt_lo = lt(T_61, T_62) - node T_64 = bits(lhs, 63, 32) - node T_65 = bits(rhs_1, 63, 32) - node lt_hi = lt(T_64, T_65) - node T_67 = bits(lhs, 63, 32) - node T_68 = bits(rhs_1, 63, 32) - node eq_hi = eq(T_67, T_68) - node T_70 = bit(addr, 2) - node T_71 = mux(T_70, lt_hi, lt_lo) - node T_72 = and(eq_hi, lt_lo) - node T_73 = or(lt_hi, T_72) - node lt = mux(word, T_71, T_73) - node T_75 = eq(cmp_lhs, cmp_rhs) - node T_76 = mux(sgned, cmp_lhs, cmp_rhs) - node less = mux(T_75, lt, T_76) - node T_78 = eq(cmd, UInt<5>("h08")) - node T_79 = eq(cmd, UInt<5>("h0b")) - node T_80 = and(lhs, rhs_1) - node T_81 = eq(cmd, UInt<5>("h0a")) - node T_82 = or(lhs, rhs_1) - node T_83 = eq(cmd, UInt<5>("h09")) - node T_84 = xor(lhs, rhs_1) - node T_85 = mux(less, min, max) - node T_86 = bits(rhs, 7, 0) - node T_87 = cat(T_86, T_86) - node T_88 = cat(T_87, T_87) - node T_89 = cat(T_88, T_88) - node T_90 = bits(rhs, 15, 0) - node T_91 = cat(T_90, T_90) - node T_92 = cat(T_91, T_91) - node T_93 = mux(T_16, T_92, rhs_1) - node T_94 = mux(T_13, T_89, T_93) - node T_95 = mux(T_85, lhs, T_94) - node T_96 = mux(T_83, T_84, T_95) - node T_97 = mux(T_81, T_82, T_96) - node T_98 = mux(T_79, T_80, T_97) - node out_2 = mux(T_78, adder_out, T_98) - node T_101 = bits(addr, 2, 0) - node T_102 = dshl(UInt<1>("h01"), T_101) - node T_104 = bits(addr, 2, 1) - node T_106 = cat(T_104, UInt<1>("h00")) - node T_107 = dshl(UInt<2>("h03"), T_106) - node T_109 = bit(addr, 2) - node T_111 = cat(T_109, UInt<2>("h00")) - node T_112 = dshl(UInt<4>("h0f"), T_111) - node T_114 = mux(T_19, T_112, UInt<8>("h0ff")) - node T_115 = mux(T_16, T_107, T_114) - node T_116 = mux(T_13, T_102, T_115) - node T_117 = bit(T_116, 0) - node T_118 = bit(T_116, 1) - node T_119 = bit(T_116, 2) - node T_120 = bit(T_116, 3) - node T_121 = bit(T_116, 4) - node T_122 = bit(T_116, 5) - node T_123 = bit(T_116, 6) - node T_124 = bit(T_116, 7) - node T_125 = bit(T_116, 8) - node T_126 = bit(T_116, 9) - node T_127 = bit(T_116, 10) - wire T_129 : UInt<1>[11] - T_129[0] := T_117 - T_129[1] := T_118 - T_129[2] := T_119 - T_129[3] := T_120 - T_129[4] := T_121 - T_129[5] := T_122 - T_129[6] := T_123 - T_129[7] := T_124 - T_129[8] := T_125 - T_129[9] := T_126 - T_129[10] := T_127 - node T_143 = subw(UInt<8>("h00"), T_129[0]) - node T_145 = subw(UInt<8>("h00"), T_129[1]) - node T_147 = subw(UInt<8>("h00"), T_129[2]) - node T_149 = subw(UInt<8>("h00"), T_129[3]) - node T_151 = subw(UInt<8>("h00"), T_129[4]) - node T_153 = subw(UInt<8>("h00"), T_129[5]) - node T_155 = subw(UInt<8>("h00"), T_129[6]) - node T_157 = subw(UInt<8>("h00"), T_129[7]) - node T_159 = subw(UInt<8>("h00"), T_129[8]) - node T_161 = subw(UInt<8>("h00"), T_129[9]) - node T_163 = subw(UInt<8>("h00"), T_129[10]) - wire T_165 : UInt<8>[11] - T_165[0] := T_143 - T_165[1] := T_145 - T_165[2] := T_147 - T_165[3] := T_149 - T_165[4] := T_151 - T_165[5] := T_153 - T_165[6] := T_155 - T_165[7] := T_157 - T_165[8] := T_159 - T_165[9] := T_161 - T_165[10] := T_163 - node T_178 = cat(T_165[10], T_165[9]) - node T_179 = cat(T_165[7], T_165[6]) - node T_180 = cat(T_165[8], T_179) - node T_181 = cat(T_178, T_180) - node T_182 = cat(T_165[4], T_165[3]) - node T_183 = cat(T_165[5], T_182) - node T_184 = cat(T_165[1], T_165[0]) - node T_185 = cat(T_165[2], T_184) - node T_186 = cat(T_183, T_185) - node wmask = cat(T_181, T_186) - node T_188 = and(wmask, out_2) - node T_189 = not(wmask) - node T_190 = and(T_189, lhs) - node T_191 = or(T_188, T_190) - out := T_191 - - module LockingArbiter_66 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.voluntary := UInt<1>("h00") - out.bits.r_type := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.bits.addr_beat := UInt<1>("h00") - out.bits.client_xact_id := UInt<1>("h00") - out.bits.addr_block := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - reg T_700 : UInt<1>, clock, reset - onreset T_700 := UInt<1>("h00") - reg T_702 : UInt, clock, reset - onreset T_702 := UInt<1>("h01") - wire T_704 : UInt<1> - T_704 := UInt<1>("h00") - infer accessor T_706 = in[T_704] - out.valid := T_706.valid - infer accessor T_769 = in[T_704] - out.bits <> T_769.bits - chosen := T_704 - infer accessor T_832 = in[T_704] - T_832.ready := UInt<1>("h00") - node T_898 = or(UInt<1>("h00"), in[0].valid) - node T_900 = eq(T_898, UInt<1>("h00")) - node T_902 = eq(T_702, UInt<1>("h00")) - node T_903 = mux(T_700, T_902, UInt<1>("h01")) - node T_904 = and(T_903, out.ready) - in[0].ready := T_904 - node T_906 = eq(T_702, UInt<1>("h01")) - node T_907 = mux(T_700, T_906, T_900) - node T_908 = and(T_907, out.ready) - in[1].ready := T_908 - reg T_910 : UInt<2>, clock, reset - onreset T_910 := UInt<2>("h00") - node T_912 = addw(T_910, UInt<1>("h01")) - node T_913 = and(out.ready, out.valid) - when T_913 : - wire T_916 : UInt<2>[3] - T_916[0] := UInt<1>("h00") - T_916[1] := UInt<1>("h01") - T_916[2] := UInt<2>("h02") - node T_921 = eq(T_916[0], out.bits.r_type) - node T_922 = eq(T_916[1], out.bits.r_type) - node T_923 = eq(T_916[2], out.bits.r_type) - node T_925 = or(UInt<1>("h00"), T_921) - node T_926 = or(T_925, T_922) - node T_927 = or(T_926, T_923) - node T_928 = and(UInt<1>("h01"), T_927) - when T_928 : - T_910 := T_912 - node T_930 = eq(T_700, UInt<1>("h00")) - when T_930 : - T_700 := UInt<1>("h01") - node T_932 = and(in[0].ready, in[0].valid) - node T_933 = and(in[1].ready, in[1].valid) - wire T_935 : UInt<1>[2] - T_935[0] := T_932 - T_935[1] := T_933 - node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01")) - T_702 := T_941 - skip - skip - node T_943 = eq(T_912, UInt<1>("h00")) - when T_943 : - T_700 := UInt<1>("h00") - skip - skip - node choose = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_948 = mux(T_700, T_702, choose) - T_704 := T_948 - - module HellaCache : - output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} - input cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} - input clock : Clock - input reset : UInt<1> - - mem_1.release.bits.voluntary := UInt<1>("h00") - mem_1.release.bits.r_type := UInt<1>("h00") - mem_1.release.bits.data := UInt<1>("h00") - mem_1.release.bits.addr_beat := UInt<1>("h00") - mem_1.release.bits.client_xact_id := UInt<1>("h00") - mem_1.release.bits.addr_block := UInt<1>("h00") - mem_1.release.valid := UInt<1>("h00") - mem_1.probe.ready := UInt<1>("h00") - mem_1.grant.ready := UInt<1>("h00") - mem_1.acquire.bits.union := UInt<1>("h00") - mem_1.acquire.bits.a_type := UInt<1>("h00") - mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") - mem_1.acquire.bits.data := UInt<1>("h00") - mem_1.acquire.bits.addr_beat := UInt<1>("h00") - mem_1.acquire.bits.client_xact_id := UInt<1>("h00") - mem_1.acquire.bits.addr_block := UInt<1>("h00") - mem_1.acquire.valid := UInt<1>("h00") - ptw.req.bits.fetch := UInt<1>("h00") - ptw.req.bits.store := UInt<1>("h00") - ptw.req.bits.prv := UInt<1>("h00") - ptw.req.bits.addr := UInt<1>("h00") - ptw.req.valid := UInt<1>("h00") - cpu.ordered := UInt<1>("h00") - cpu.xcpt.pf.st := UInt<1>("h00") - cpu.xcpt.pf.ld := UInt<1>("h00") - cpu.xcpt.ma.st := UInt<1>("h00") - cpu.xcpt.ma.ld := UInt<1>("h00") - cpu.replay_next.bits := UInt<1>("h00") - cpu.replay_next.valid := UInt<1>("h00") - cpu.resp.bits.store_data := UInt<1>("h00") - cpu.resp.bits.data_subword := UInt<1>("h00") - cpu.resp.bits.has_data := UInt<1>("h00") - cpu.resp.bits.replay := UInt<1>("h00") - cpu.resp.bits.nack := UInt<1>("h00") - cpu.resp.bits.data := UInt<1>("h00") - cpu.resp.bits.typ := UInt<1>("h00") - cpu.resp.bits.cmd := UInt<1>("h00") - cpu.resp.bits.tag := UInt<1>("h00") - cpu.resp.bits.addr := UInt<1>("h00") - cpu.resp.valid := UInt<1>("h00") - cpu.req.ready := UInt<1>("h00") - inst wb of WritebackUnit - wb.release.ready := UInt<1>("h00") - wb.data_resp := UInt<1>("h00") - wb.data_req.ready := UInt<1>("h00") - wb.meta_read.ready := UInt<1>("h00") - wb.req.bits.way_en := UInt<1>("h00") - wb.req.bits.voluntary := UInt<1>("h00") - wb.req.bits.r_type := UInt<1>("h00") - wb.req.bits.data := UInt<1>("h00") - wb.req.bits.addr_beat := UInt<1>("h00") - wb.req.bits.client_xact_id := UInt<1>("h00") - wb.req.bits.addr_block := UInt<1>("h00") - wb.req.valid := UInt<1>("h00") - wb.reset := UInt<1>("h00") - wb.clock := clock - wb.reset := reset - inst prober of ProbeUnit - prober.block_state.state := UInt<1>("h00") - prober.mshr_rdy := UInt<1>("h00") - prober.way_en := UInt<1>("h00") - prober.wb_req.ready := UInt<1>("h00") - prober.meta_write.ready := UInt<1>("h00") - prober.meta_read.ready := UInt<1>("h00") - prober.rep.ready := UInt<1>("h00") - prober.req.bits.client_xact_id := UInt<1>("h00") - prober.req.bits.p_type := UInt<1>("h00") - prober.req.bits.addr_block := UInt<1>("h00") - prober.req.valid := UInt<1>("h00") - prober.reset := UInt<1>("h00") - prober.clock := clock - prober.reset := reset - inst mshrs of MSHRFile - mshrs.wb_req.ready := UInt<1>("h00") - mshrs.mem_grant.bits.g_type := UInt<1>("h00") - mshrs.mem_grant.bits.is_builtin_type := UInt<1>("h00") - mshrs.mem_grant.bits.manager_xact_id := UInt<1>("h00") - mshrs.mem_grant.bits.client_xact_id := UInt<1>("h00") - mshrs.mem_grant.bits.data := UInt<1>("h00") - mshrs.mem_grant.bits.addr_beat := UInt<1>("h00") - mshrs.mem_grant.valid := UInt<1>("h00") - mshrs.replay.ready := UInt<1>("h00") - mshrs.meta_write.ready := UInt<1>("h00") - mshrs.meta_read.ready := UInt<1>("h00") - mshrs.mem_req.ready := UInt<1>("h00") - mshrs.req.bits.way_en := UInt<1>("h00") - mshrs.req.bits.old_meta.coh.state := UInt<1>("h00") - mshrs.req.bits.old_meta.tag := UInt<1>("h00") - mshrs.req.bits.tag_match := UInt<1>("h00") - mshrs.req.bits.data := UInt<1>("h00") - mshrs.req.bits.phys := UInt<1>("h00") - mshrs.req.bits.kill := UInt<1>("h00") - mshrs.req.bits.typ := UInt<1>("h00") - mshrs.req.bits.cmd := UInt<1>("h00") - mshrs.req.bits.tag := UInt<1>("h00") - mshrs.req.bits.addr := UInt<1>("h00") - mshrs.req.valid := UInt<1>("h00") - mshrs.reset := UInt<1>("h00") - mshrs.clock := clock - mshrs.reset := reset - cpu.req.ready := UInt<1>("h01") - node T_887 = and(cpu.req.ready, cpu.req.valid) - reg s1_valid : UInt<1>, clock, reset - onreset s1_valid := UInt<1>("h00") - s1_valid := T_887 - reg s1_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset - node T_899 = eq(cpu.req.bits.kill, UInt<1>("h00")) - node s1_valid_masked = and(s1_valid, T_899) - reg s1_replay : UInt<1>, clock, reset - onreset s1_replay := UInt<1>("h00") - reg s1_clk_en : UInt<1>, clock, reset - reg s2_valid : UInt<1>, clock, reset - onreset s2_valid := UInt<1>("h00") - s2_valid := s1_valid_masked - reg s2_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset - reg T_916 : UInt<1>, clock, reset - onreset T_916 := UInt<1>("h00") - T_916 := s1_replay - node T_917 = neq(s2_req.cmd, UInt<5>("h05")) - node s2_replay = and(T_916, T_917) - wire s2_recycle : UInt<1> - s2_recycle := UInt<1>("h00") - wire s2_valid_masked : UInt<1> - s2_valid_masked := UInt<1>("h00") - reg s3_valid : UInt<1>, clock, reset - onreset s3_valid := UInt<1>("h00") - reg s3_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset - reg s3_way : UInt, clock, reset - reg s1_recycled : UInt<1>, clock, reset - onreset s1_recycled := UInt<1>("h00") - when s1_clk_en : - s1_recycled := s2_recycle - skip - node T_939 = eq(s1_req.cmd, UInt<5>("h00")) - node T_940 = eq(s1_req.cmd, UInt<5>("h06")) - node T_941 = or(T_939, T_940) - node T_942 = bit(s1_req.cmd, 3) - node T_943 = eq(s1_req.cmd, UInt<5>("h04")) - node T_944 = or(T_942, T_943) - node s1_read = or(T_941, T_944) - node T_946 = eq(s1_req.cmd, UInt<5>("h01")) - node T_947 = eq(s1_req.cmd, UInt<5>("h07")) - node T_948 = or(T_946, T_947) - node T_949 = bit(s1_req.cmd, 3) - node T_950 = eq(s1_req.cmd, UInt<5>("h04")) - node T_951 = or(T_949, T_950) - node s1_write = or(T_948, T_951) - node s1_sc = eq(s1_req.cmd, UInt<5>("h07")) - node T_954 = or(s1_read, s1_write) - node T_955 = eq(s1_req.cmd, UInt<5>("h02")) - node T_956 = eq(s1_req.cmd, UInt<5>("h03")) - node T_957 = or(T_955, T_956) - node s1_readwrite = or(T_954, T_957) - inst dtlb of TLB_60 - dtlb.ptw.invalidate := UInt<1>("h00") - dtlb.ptw.status.ie := UInt<1>("h00") - dtlb.ptw.status.prv := UInt<1>("h00") - dtlb.ptw.status.ie1 := UInt<1>("h00") - dtlb.ptw.status.prv1 := UInt<1>("h00") - dtlb.ptw.status.ie2 := UInt<1>("h00") - dtlb.ptw.status.prv2 := UInt<1>("h00") - dtlb.ptw.status.ie3 := UInt<1>("h00") - dtlb.ptw.status.prv3 := UInt<1>("h00") - dtlb.ptw.status.fs := UInt<1>("h00") - dtlb.ptw.status.xs := UInt<1>("h00") - dtlb.ptw.status.mprv := UInt<1>("h00") - dtlb.ptw.status.vm := UInt<1>("h00") - dtlb.ptw.status.zero1 := UInt<1>("h00") - dtlb.ptw.status.sd_rv32 := UInt<1>("h00") - dtlb.ptw.status.zero2 := UInt<1>("h00") - dtlb.ptw.status.sd := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.v := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.typ := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.r := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.d := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - dtlb.ptw.resp.bits.pte.ppn := UInt<1>("h00") - dtlb.ptw.resp.bits.error := UInt<1>("h00") - dtlb.ptw.resp.valid := UInt<1>("h00") - dtlb.ptw.req.ready := UInt<1>("h00") - dtlb.req.bits.store := UInt<1>("h00") - dtlb.req.bits.instruction := UInt<1>("h00") - dtlb.req.bits.passthrough := UInt<1>("h00") - dtlb.req.bits.vpn := UInt<1>("h00") - dtlb.req.bits.asid := UInt<1>("h00") - dtlb.req.valid := UInt<1>("h00") - dtlb.reset := UInt<1>("h00") - dtlb.clock := clock - dtlb.reset := reset - ptw <> dtlb.ptw - node T_992 = and(s1_valid_masked, s1_readwrite) - node T_994 = eq(s1_req.phys, UInt<1>("h00")) - node T_995 = and(T_992, T_994) - dtlb.req.valid := T_995 - dtlb.req.bits.passthrough := s1_req.phys - dtlb.req.bits.asid := UInt<1>("h00") - node T_997 = shr(s1_req.addr, 12) - dtlb.req.bits.vpn := T_997 - dtlb.req.bits.instruction := UInt<1>("h00") - dtlb.req.bits.store := s1_write - node T_1000 = eq(dtlb.req.ready, UInt<1>("h00")) - node T_1002 = eq(cpu.req.bits.phys, UInt<1>("h00")) - node T_1003 = and(T_1000, T_1002) - when T_1003 : - cpu.req.ready := UInt<1>("h00") - skip - when cpu.req.valid : - s1_req <> cpu.req.bits - skip - when wb.meta_read.valid : - node T_1005 = cat(wb.meta_read.bits.tag, wb.meta_read.bits.idx) - node T_1006 = shl(T_1005, 6) - s1_req.addr := T_1006 - s1_req.phys := UInt<1>("h01") - skip - when prober.meta_read.valid : - node T_1008 = cat(prober.meta_read.bits.tag, prober.meta_read.bits.idx) - node T_1009 = shl(T_1008, 6) - s1_req.addr := T_1009 - s1_req.phys := UInt<1>("h01") - skip - when mshrs.replay.valid : - s1_req <> mshrs.replay.bits - skip - when s2_recycle : - s1_req <> s2_req - skip - node T_1011 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.resp.ppn, T_1011) - when s1_clk_en : - s2_req.kill := s1_req.kill - s2_req.typ := s1_req.typ - s2_req.phys := s1_req.phys - s2_req.addr := s1_addr - when s1_write : - node T_1013 = mux(s1_replay, mshrs.replay.bits.data, cpu.req.bits.data) - s2_req.data := T_1013 - skip - when s1_recycled : - s2_req.data := s1_req.data - skip - s2_req.tag := s1_req.tag - s2_req.cmd := s1_req.cmd - skip - node T_1014 = eq(s1_req.typ, UInt<3>("h01")) - node T_1015 = eq(s1_req.typ, UInt<3>("h05")) - node T_1016 = or(T_1014, T_1015) - node T_1017 = bit(s1_req.addr, 0) - node T_1019 = neq(T_1017, UInt<1>("h00")) - node T_1020 = and(T_1016, T_1019) - node T_1021 = eq(s1_req.typ, UInt<3>("h02")) - node T_1022 = eq(s1_req.typ, UInt<3>("h06")) - node T_1023 = or(T_1021, T_1022) - node T_1024 = bits(s1_req.addr, 1, 0) - node T_1026 = neq(T_1024, UInt<1>("h00")) - node T_1027 = and(T_1023, T_1026) - node T_1028 = or(T_1020, T_1027) - node T_1029 = eq(s1_req.typ, UInt<3>("h03")) - node T_1030 = bits(s1_req.addr, 2, 0) - node T_1032 = neq(T_1030, UInt<1>("h00")) - node T_1033 = and(T_1029, T_1032) - node misaligned = or(T_1028, T_1033) - node T_1035 = and(s1_read, misaligned) - cpu.xcpt.ma.ld := T_1035 - node T_1036 = and(s1_write, misaligned) - cpu.xcpt.ma.st := T_1036 - node T_1038 = eq(s1_req.phys, UInt<1>("h00")) - node T_1039 = and(T_1038, s1_read) - node T_1040 = and(T_1039, dtlb.resp.xcpt_ld) - cpu.xcpt.pf.ld := T_1040 - node T_1042 = eq(s1_req.phys, UInt<1>("h00")) - node T_1043 = and(T_1042, s1_write) - node T_1044 = and(T_1043, dtlb.resp.xcpt_st) - cpu.xcpt.pf.st := T_1044 - node T_1045 = or(cpu.xcpt.ma.ld, cpu.xcpt.ma.st) - node T_1046 = or(T_1045, cpu.xcpt.pf.ld) - node T_1047 = or(T_1046, cpu.xcpt.pf.st) - reg T_1048 : UInt<1>, clock, reset - T_1048 := T_1047 - node T_1049 = and(T_1048, cpu.resp.valid) - node T_1051 = eq(T_1049, UInt<1>("h00")) - inst meta of MetadataArray - meta.write.bits.data.coh.state := UInt<1>("h00") - meta.write.bits.data.tag := UInt<1>("h00") - meta.write.bits.way_en := UInt<1>("h00") - meta.write.bits.idx := UInt<1>("h00") - meta.write.valid := UInt<1>("h00") - meta.read.bits.idx := UInt<1>("h00") - meta.read.valid := UInt<1>("h00") - meta.reset := UInt<1>("h00") - meta.clock := clock - meta.reset := reset - inst metaReadArb of Arbiter_62 - metaReadArb.out.ready := UInt<1>("h00") - metaReadArb.in[0].bits.idx := UInt<1>("h00") - metaReadArb.in[0].valid := UInt<1>("h00") - metaReadArb.in[1].bits.idx := UInt<1>("h00") - metaReadArb.in[1].valid := UInt<1>("h00") - metaReadArb.in[2].bits.idx := UInt<1>("h00") - metaReadArb.in[2].valid := UInt<1>("h00") - metaReadArb.in[3].bits.idx := UInt<1>("h00") - metaReadArb.in[3].valid := UInt<1>("h00") - metaReadArb.in[4].bits.idx := UInt<1>("h00") - metaReadArb.in[4].valid := UInt<1>("h00") - metaReadArb.reset := UInt<1>("h00") - metaReadArb.clock := clock - metaReadArb.reset := reset - inst metaWriteArb of Arbiter_53 - metaWriteArb.out.ready := UInt<1>("h00") - metaWriteArb.in[0].bits.data.coh.state := UInt<1>("h00") - metaWriteArb.in[0].bits.data.tag := UInt<1>("h00") - metaWriteArb.in[0].bits.way_en := UInt<1>("h00") - metaWriteArb.in[0].bits.idx := UInt<1>("h00") - metaWriteArb.in[0].valid := UInt<1>("h00") - metaWriteArb.in[1].bits.data.coh.state := UInt<1>("h00") - metaWriteArb.in[1].bits.data.tag := UInt<1>("h00") - metaWriteArb.in[1].bits.way_en := UInt<1>("h00") - metaWriteArb.in[1].bits.idx := UInt<1>("h00") - metaWriteArb.in[1].valid := UInt<1>("h00") - metaWriteArb.reset := UInt<1>("h00") - metaWriteArb.clock := clock - metaWriteArb.reset := reset - meta.read <> metaReadArb.out - meta.write <> metaWriteArb.out - inst data of DataArray - data.write.bits.data := UInt<1>("h00") - data.write.bits.wmask := UInt<1>("h00") - data.write.bits.addr := UInt<1>("h00") - data.write.bits.way_en := UInt<1>("h00") - data.write.valid := UInt<1>("h00") - data.read.bits.addr := UInt<1>("h00") - data.read.bits.way_en := UInt<1>("h00") - data.read.valid := UInt<1>("h00") - data.reset := UInt<1>("h00") - data.clock := clock - data.reset := reset - inst readArb of Arbiter_64 - readArb.out.ready := UInt<1>("h00") - readArb.in[0].bits.addr := UInt<1>("h00") - readArb.in[0].bits.way_en := UInt<1>("h00") - readArb.in[0].valid := UInt<1>("h00") - readArb.in[1].bits.addr := UInt<1>("h00") - readArb.in[1].bits.way_en := UInt<1>("h00") - readArb.in[1].valid := UInt<1>("h00") - readArb.in[2].bits.addr := UInt<1>("h00") - readArb.in[2].bits.way_en := UInt<1>("h00") - readArb.in[2].valid := UInt<1>("h00") - readArb.in[3].bits.addr := UInt<1>("h00") - readArb.in[3].bits.way_en := UInt<1>("h00") - readArb.in[3].valid := UInt<1>("h00") - readArb.reset := UInt<1>("h00") - readArb.clock := clock - readArb.reset := reset - inst writeArb of Arbiter_65 - writeArb.out.ready := UInt<1>("h00") - writeArb.in[0].bits.data := UInt<1>("h00") - writeArb.in[0].bits.wmask := UInt<1>("h00") - writeArb.in[0].bits.addr := UInt<1>("h00") - writeArb.in[0].bits.way_en := UInt<1>("h00") - writeArb.in[0].valid := UInt<1>("h00") - writeArb.in[1].bits.data := UInt<1>("h00") - writeArb.in[1].bits.wmask := UInt<1>("h00") - writeArb.in[1].bits.addr := UInt<1>("h00") - writeArb.in[1].bits.way_en := UInt<1>("h00") - writeArb.in[1].valid := UInt<1>("h00") - writeArb.reset := UInt<1>("h00") - writeArb.clock := clock - writeArb.reset := reset - data.write.valid := writeArb.out.valid - writeArb.out.ready := data.write.ready - data.write.bits <> writeArb.out.bits - node T_1186 = bits(writeArb.out.bits.data, 63, 0) - node T_1187 = bits(writeArb.out.bits.data, 127, 64) - wire T_1189 : UInt<64>[2] - T_1189[0] := T_1186 - T_1189[1] := T_1187 - node T_1193 = cat(T_1189[1], T_1189[0]) - data.write.bits.data := T_1193 - metaReadArb.in[4].valid := cpu.req.valid - node T_1194 = shr(cpu.req.bits.addr, 6) - metaReadArb.in[4].bits.idx := T_1194 - node T_1196 = eq(metaReadArb.in[4].ready, UInt<1>("h00")) - when T_1196 : - cpu.req.ready := UInt<1>("h00") - skip - readArb.in[3].valid := cpu.req.valid - readArb.in[3].bits.addr := cpu.req.bits.addr - node T_1199 = not(UInt<4>("h00")) - readArb.in[3].bits.way_en := T_1199 - node T_1201 = eq(readArb.in[3].ready, UInt<1>("h00")) - when T_1201 : - cpu.req.ready := UInt<1>("h00") - skip - metaReadArb.in[0].valid := s2_recycle - node T_1203 = shr(s2_req.addr, 6) - metaReadArb.in[0].bits.idx := T_1203 - readArb.in[0].valid := s2_recycle - readArb.in[0].bits.addr := s2_req.addr - node T_1205 = not(UInt<4>("h00")) - readArb.in[0].bits.way_en := T_1205 - node T_1206 = shr(s1_addr, 12) - node T_1207 = eq(meta.resp[0].tag, T_1206) - node T_1208 = shr(s1_addr, 12) - node T_1209 = eq(meta.resp[1].tag, T_1208) - node T_1210 = shr(s1_addr, 12) - node T_1211 = eq(meta.resp[2].tag, T_1210) - node T_1212 = shr(s1_addr, 12) - node T_1213 = eq(meta.resp[3].tag, T_1212) - wire T_1215 : UInt<1>[4] - T_1215[0] := T_1207 - T_1215[1] := T_1209 - T_1215[2] := T_1211 - T_1215[3] := T_1213 - node T_1221 = cat(T_1215[3], T_1215[2]) - node T_1222 = cat(T_1215[1], T_1215[0]) - node s1_tag_eq_way = cat(T_1221, T_1222) - node T_1224 = bit(s1_tag_eq_way, 0) - node T_1225 = neq(meta.resp[0].coh.state, UInt<1>("h00")) - node T_1226 = and(T_1224, T_1225) - node T_1227 = bit(s1_tag_eq_way, 1) - node T_1228 = neq(meta.resp[1].coh.state, UInt<1>("h00")) - node T_1229 = and(T_1227, T_1228) - node T_1230 = bit(s1_tag_eq_way, 2) - node T_1231 = neq(meta.resp[2].coh.state, UInt<1>("h00")) - node T_1232 = and(T_1230, T_1231) - node T_1233 = bit(s1_tag_eq_way, 3) - node T_1234 = neq(meta.resp[3].coh.state, UInt<1>("h00")) - node T_1235 = and(T_1233, T_1234) - wire T_1237 : UInt<1>[4] - T_1237[0] := T_1226 - T_1237[1] := T_1229 - T_1237[2] := T_1232 - T_1237[3] := T_1235 - node T_1243 = cat(T_1237[3], T_1237[2]) - node T_1244 = cat(T_1237[1], T_1237[0]) - node s1_tag_match_way = cat(T_1243, T_1244) - s1_clk_en := metaReadArb.out.valid - node T_1247 = eq(s1_valid, UInt<1>("h00")) - node T_1248 = and(s1_clk_en, T_1247) - node T_1250 = eq(s1_replay, UInt<1>("h00")) - node s1_writeback = and(T_1248, T_1250) - reg s2_tag_match_way : UInt<4>, clock, reset - when s1_clk_en : - s2_tag_match_way := s1_tag_match_way - skip - node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) - reg T_1255 : {state : UInt<2>}, clock, reset - when s1_clk_en : - T_1255 <> meta.resp[0].coh - skip - reg T_1280 : {state : UInt<2>}, clock, reset - when s1_clk_en : - T_1280 <> meta.resp[1].coh - skip - reg T_1305 : {state : UInt<2>}, clock, reset - when s1_clk_en : - T_1305 <> meta.resp[2].coh - skip - reg T_1330 : {state : UInt<2>}, clock, reset - when s1_clk_en : - T_1330 <> meta.resp[3].coh - skip - wire T_1380 : {state : UInt<2>}[4] - T_1380[0] <> T_1255 - T_1380[1] <> T_1280 - T_1380[2] <> T_1305 - T_1380[3] <> T_1330 - node T_1506 = bit(s2_tag_match_way, 0) - node T_1507 = bit(s2_tag_match_way, 1) - node T_1508 = bit(s2_tag_match_way, 2) - node T_1509 = bit(s2_tag_match_way, 3) - node T_1511 = mux(T_1506, T_1380[0].state, UInt<1>("h00")) - node T_1513 = mux(T_1507, T_1380[1].state, UInt<1>("h00")) - node T_1515 = mux(T_1508, T_1380[2].state, UInt<1>("h00")) - node T_1517 = mux(T_1509, T_1380[3].state, UInt<1>("h00")) - node T_1543 = or(T_1511, T_1513) - node T_1544 = or(T_1543, T_1515) - node T_1545 = or(T_1544, T_1517) - wire s2_hit_state : {state : UInt<2>} - s2_hit_state.state := UInt<1>("h00") - node T_1597 = bits(T_1545, 1, 0) - s2_hit_state.state := T_1597 - node T_1598 = eq(s2_req.cmd, UInt<5>("h01")) - node T_1599 = eq(s2_req.cmd, UInt<5>("h07")) - node T_1600 = or(T_1598, T_1599) - node T_1601 = bit(s2_req.cmd, 3) - node T_1602 = eq(s2_req.cmd, UInt<5>("h04")) - node T_1603 = or(T_1601, T_1602) - node T_1604 = or(T_1600, T_1603) - node T_1605 = eq(s2_req.cmd, UInt<5>("h03")) - node T_1606 = or(T_1604, T_1605) - node T_1607 = eq(s2_req.cmd, UInt<5>("h06")) - node T_1608 = or(T_1606, T_1607) - wire T_1610 : UInt<2>[2] - T_1610[0] := UInt<2>("h02") - T_1610[1] := UInt<2>("h03") - node T_1614 = eq(T_1610[0], s2_hit_state.state) - node T_1615 = eq(T_1610[1], s2_hit_state.state) - node T_1617 = or(UInt<1>("h00"), T_1614) - node T_1618 = or(T_1617, T_1615) - wire T_1620 : UInt<2>[3] - T_1620[0] := UInt<1>("h01") - T_1620[1] := UInt<2>("h02") - T_1620[2] := UInt<2>("h03") - node T_1625 = eq(T_1620[0], s2_hit_state.state) - node T_1626 = eq(T_1620[1], s2_hit_state.state) - node T_1627 = eq(T_1620[2], s2_hit_state.state) - node T_1629 = or(UInt<1>("h00"), T_1625) - node T_1630 = or(T_1629, T_1626) - node T_1631 = or(T_1630, T_1627) - node T_1632 = mux(T_1608, T_1618, T_1631) - node T_1633 = and(s2_tag_match, T_1632) - node T_1634 = eq(s2_req.cmd, UInt<5>("h01")) - node T_1635 = eq(s2_req.cmd, UInt<5>("h07")) - node T_1636 = or(T_1634, T_1635) - node T_1637 = bit(s2_req.cmd, 3) - node T_1638 = eq(s2_req.cmd, UInt<5>("h04")) - node T_1639 = or(T_1637, T_1638) - node T_1640 = or(T_1636, T_1639) - node T_1641 = mux(T_1640, UInt<2>("h03"), s2_hit_state.state) - wire T_1667 : {state : UInt<2>} - T_1667.state := UInt<1>("h00") - T_1667.state := T_1641 - node T_1693 = eq(s2_hit_state.state, T_1667.state) - node s2_hit = and(T_1633, T_1693) - reg lrsc_count : UInt, clock, reset - onreset lrsc_count := UInt<1>("h00") - node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) - reg lrsc_addr : UInt, clock, reset - node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) - node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) - node T_1703 = shr(s2_req.addr, 6) - node T_1704 = eq(lrsc_addr, T_1703) - node s2_lrsc_addr_match = and(lrsc_valid, T_1704) - node T_1707 = eq(s2_lrsc_addr_match, UInt<1>("h00")) - node s2_sc_fail = and(s2_sc, T_1707) - when lrsc_valid : - node T_1710 = subw(lrsc_count, UInt<1>("h01")) - lrsc_count := T_1710 - skip - node T_1711 = and(s2_valid_masked, s2_hit) - node T_1712 = or(T_1711, s2_replay) - when T_1712 : - when s2_lr : - node T_1714 = eq(lrsc_valid, UInt<1>("h00")) - when T_1714 : - lrsc_count := UInt<5>("h01f") - skip - node T_1716 = shr(s2_req.addr, 6) - lrsc_addr := T_1716 - skip - when s2_sc : - lrsc_count := UInt<1>("h00") - skip - skip - when cpu.invalidate_lr : - lrsc_count := UInt<1>("h00") - skip - wire s2_data : UInt<128>[4] - s2_data[0] := UInt<1>("h00") - s2_data[1] := UInt<1>("h00") - s2_data[2] := UInt<1>("h00") - s2_data[3] := UInt<1>("h00") - reg T_1747 : UInt<64>[2], clock, reset - node T_1751 = bit(s1_tag_eq_way, 0) - node T_1752 = and(s1_clk_en, T_1751) - node T_1756 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1757 = or(UInt<1>("h01"), T_1756) - node T_1758 = or(T_1757, s1_writeback) - node T_1759 = and(T_1752, T_1758) - when T_1759 : - node T_1760 = shr(data.resp[0], 0) - T_1747[0] := T_1760 - skip - node T_1764 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1765 = or(UInt<1>("h00"), T_1764) - node T_1766 = or(T_1765, s1_writeback) - node T_1767 = and(T_1752, T_1766) - when T_1767 : - node T_1768 = shr(data.resp[0], 64) - T_1747[1] := T_1768 - skip - node T_1769 = cat(T_1747[1], T_1747[0]) - s2_data[0] := T_1769 - reg T_1778 : UInt<64>[2], clock, reset - node T_1782 = bit(s1_tag_eq_way, 1) - node T_1783 = and(s1_clk_en, T_1782) - node T_1787 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1788 = or(UInt<1>("h01"), T_1787) - node T_1789 = or(T_1788, s1_writeback) - node T_1790 = and(T_1783, T_1789) - when T_1790 : - node T_1791 = shr(data.resp[1], 0) - T_1778[0] := T_1791 - skip - node T_1795 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1796 = or(UInt<1>("h00"), T_1795) - node T_1797 = or(T_1796, s1_writeback) - node T_1798 = and(T_1783, T_1797) - when T_1798 : - node T_1799 = shr(data.resp[1], 64) - T_1778[1] := T_1799 - skip - node T_1800 = cat(T_1778[1], T_1778[0]) - s2_data[1] := T_1800 - reg T_1809 : UInt<64>[2], clock, reset - node T_1813 = bit(s1_tag_eq_way, 2) - node T_1814 = and(s1_clk_en, T_1813) - node T_1818 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1819 = or(UInt<1>("h01"), T_1818) - node T_1820 = or(T_1819, s1_writeback) - node T_1821 = and(T_1814, T_1820) - when T_1821 : - node T_1822 = shr(data.resp[2], 0) - T_1809[0] := T_1822 - skip - node T_1826 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1827 = or(UInt<1>("h00"), T_1826) - node T_1828 = or(T_1827, s1_writeback) - node T_1829 = and(T_1814, T_1828) - when T_1829 : - node T_1830 = shr(data.resp[2], 64) - T_1809[1] := T_1830 - skip - node T_1831 = cat(T_1809[1], T_1809[0]) - s2_data[2] := T_1831 - reg T_1840 : UInt<64>[2], clock, reset - node T_1844 = bit(s1_tag_eq_way, 3) - node T_1845 = and(s1_clk_en, T_1844) - node T_1849 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1850 = or(UInt<1>("h01"), T_1849) - node T_1851 = or(T_1850, s1_writeback) - node T_1852 = and(T_1845, T_1851) - when T_1852 : - node T_1853 = shr(data.resp[3], 0) - T_1840[0] := T_1853 - skip - node T_1857 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1858 = or(UInt<1>("h00"), T_1857) - node T_1859 = or(T_1858, s1_writeback) - node T_1860 = and(T_1845, T_1859) - when T_1860 : - node T_1861 = shr(data.resp[3], 64) - T_1840[1] := T_1861 - skip - node T_1862 = cat(T_1840[1], T_1840[0]) - s2_data[3] := T_1862 - node T_1863 = bit(s2_tag_match_way, 0) - node T_1864 = bit(s2_tag_match_way, 1) - node T_1865 = bit(s2_tag_match_way, 2) - node T_1866 = bit(s2_tag_match_way, 3) - node T_1868 = mux(T_1863, s2_data[0], UInt<1>("h00")) - node T_1870 = mux(T_1864, s2_data[1], UInt<1>("h00")) - node T_1872 = mux(T_1865, s2_data[2], UInt<1>("h00")) - node T_1874 = mux(T_1866, s2_data[3], UInt<1>("h00")) - node T_1876 = or(T_1868, T_1870) - node T_1877 = or(T_1876, T_1872) - node T_1878 = or(T_1877, T_1874) - wire s2_data_muxed : UInt<128> - s2_data_muxed := UInt<1>("h00") - s2_data_muxed := T_1878 - node T_1881 = bits(s2_data_muxed, 63, 0) - node T_1882 = bits(s2_data_muxed, 127, 64) - wire T_1884 : UInt<64>[2] - T_1884[0] := T_1881 - T_1884[1] := T_1882 - node s2_data_corrected = cat(T_1884[1], T_1884[0]) - wire T_1890 : UInt<64>[2] - T_1890[0] := T_1881 - T_1890[1] := T_1882 - node s2_data_uncorrected = cat(T_1890[1], T_1890[0]) - wire T_1899 : UInt<1>[2] - T_1899[0] := UInt<1>("h00") - T_1899[1] := UInt<1>("h00") - node T_1903 = cat(T_1899[1], T_1899[0]) - node T_1904 = dshr(T_1903, UInt<1>("h00")) - node s2_data_correctable = bit(T_1904, 0) - node T_1906 = and(s2_valid_masked, s2_hit) - node T_1907 = or(T_1906, s2_replay) - node T_1909 = eq(s2_sc_fail, UInt<1>("h00")) - node T_1910 = and(T_1907, T_1909) - node T_1911 = eq(s2_req.cmd, UInt<5>("h01")) - node T_1912 = eq(s2_req.cmd, UInt<5>("h07")) - node T_1913 = or(T_1911, T_1912) - node T_1914 = bit(s2_req.cmd, 3) - node T_1915 = eq(s2_req.cmd, UInt<5>("h04")) - node T_1916 = or(T_1914, T_1915) - node T_1917 = or(T_1913, T_1916) - node T_1918 = and(T_1910, T_1917) - s3_valid := T_1918 - inst amoalu of AMOALU - amoalu.rhs := UInt<1>("h00") - amoalu.lhs := UInt<1>("h00") - amoalu.typ := UInt<1>("h00") - amoalu.cmd := UInt<1>("h00") - amoalu.addr := UInt<1>("h00") - amoalu.reset := UInt<1>("h00") - amoalu.clock := clock - amoalu.reset := reset - node T_1925 = or(s2_valid, s2_replay) - node T_1926 = eq(s2_req.cmd, UInt<5>("h01")) - node T_1927 = eq(s2_req.cmd, UInt<5>("h07")) - node T_1928 = or(T_1926, T_1927) - node T_1929 = bit(s2_req.cmd, 3) - node T_1930 = eq(s2_req.cmd, UInt<5>("h04")) - node T_1931 = or(T_1929, T_1930) - node T_1932 = or(T_1928, T_1931) - node T_1933 = or(T_1932, s2_data_correctable) - node T_1934 = and(T_1925, T_1933) - when T_1934 : - s3_req <> s2_req - node T_1935 = mux(s2_data_correctable, s2_data_corrected, amoalu.out) - s3_req.data := T_1935 - s3_way := s2_tag_match_way - skip - writeArb.in[0].bits.addr := s3_req.addr - node rowIdx = bits(s3_req.addr, 3, 3) - node rowWMask = dshl(UInt<1>("h01"), rowIdx) - writeArb.in[0].bits.wmask := rowWMask - node T_1939 = cat(s3_req.data, s3_req.data) - writeArb.in[0].bits.data := T_1939 - writeArb.in[0].valid := s3_valid - writeArb.in[0].bits.way_en := s3_way - wire T_1941 : UInt<1> - T_1941 := UInt<1>("h00") - T_1941 := UInt<1>("h00") - reg T_1945 : UInt<16>, clock, reset - onreset T_1945 := UInt<16>("h01") - when T_1941 : - node T_1946 = bit(T_1945, 0) - node T_1947 = bit(T_1945, 2) - node T_1948 = xor(T_1946, T_1947) - node T_1949 = bit(T_1945, 3) - node T_1950 = xor(T_1948, T_1949) - node T_1951 = bit(T_1945, 5) - node T_1952 = xor(T_1950, T_1951) - node T_1953 = bits(T_1945, 15, 1) - node T_1954 = cat(T_1952, T_1953) - T_1945 := T_1954 - skip - node T_1955 = bits(T_1945, 1, 0) - node s1_replaced_way_en = dshl(UInt<1>("h01"), T_1955) - node T_1958 = bits(T_1945, 1, 0) - reg T_1959 : UInt<2>, clock, reset - when s1_clk_en : - T_1959 := T_1958 - skip - node s2_replaced_way_en = dshl(UInt<1>("h01"), T_1959) - node T_1962 = bit(s1_replaced_way_en, 0) - node T_1963 = and(s1_clk_en, T_1962) - reg T_1964 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset - when T_1963 : - T_1964 <> meta.resp[0] - skip - node T_1991 = bit(s1_replaced_way_en, 1) - node T_1992 = and(s1_clk_en, T_1991) - reg T_1993 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset - when T_1992 : - T_1993 <> meta.resp[1] - skip - node T_2020 = bit(s1_replaced_way_en, 2) - node T_2021 = and(s1_clk_en, T_2020) - reg T_2022 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset - when T_2021 : - T_2022 <> meta.resp[2] - skip - node T_2049 = bit(s1_replaced_way_en, 3) - node T_2050 = and(s1_clk_en, T_2049) - reg T_2051 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset - when T_2050 : - T_2051 <> meta.resp[3] - skip - wire T_2105 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_2105[0] <> T_1964 - T_2105[1] <> T_1993 - T_2105[2] <> T_2022 - T_2105[3] <> T_2051 - node T_2241 = bit(s2_replaced_way_en, 0) - node T_2242 = bit(s2_replaced_way_en, 1) - node T_2243 = bit(s2_replaced_way_en, 2) - node T_2244 = bit(s2_replaced_way_en, 3) - node T_2245 = cat(T_2105[0].tag, T_2105[0].coh.state) - node T_2247 = mux(T_2241, T_2245, UInt<1>("h00")) - node T_2248 = cat(T_2105[1].tag, T_2105[1].coh.state) - node T_2250 = mux(T_2242, T_2248, UInt<1>("h00")) - node T_2251 = cat(T_2105[2].tag, T_2105[2].coh.state) - node T_2253 = mux(T_2243, T_2251, UInt<1>("h00")) - node T_2254 = cat(T_2105[3].tag, T_2105[3].coh.state) - node T_2256 = mux(T_2244, T_2254, UInt<1>("h00")) - node T_2284 = or(T_2247, T_2250) - node T_2285 = or(T_2284, T_2253) - node T_2286 = or(T_2285, T_2256) - wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} - s2_repl_meta.coh.state := UInt<1>("h00") - s2_repl_meta.tag := UInt<1>("h00") - node T_2343 = bits(T_2286, 1, 0) - s2_repl_meta.coh.state := T_2343 - node T_2344 = bits(T_2286, 21, 2) - s2_repl_meta.tag := T_2344 - node T_2346 = eq(s2_hit, UInt<1>("h00")) - node T_2347 = and(s2_valid_masked, T_2346) - node T_2348 = eq(s2_req.cmd, UInt<5>("h02")) - node T_2349 = eq(s2_req.cmd, UInt<5>("h03")) - node T_2350 = or(T_2348, T_2349) - node T_2351 = eq(s2_req.cmd, UInt<5>("h00")) - node T_2352 = eq(s2_req.cmd, UInt<5>("h06")) - node T_2353 = or(T_2351, T_2352) - node T_2354 = bit(s2_req.cmd, 3) - node T_2355 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2356 = or(T_2354, T_2355) - node T_2357 = or(T_2353, T_2356) - node T_2358 = or(T_2350, T_2357) - node T_2359 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2360 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2361 = or(T_2359, T_2360) - node T_2362 = bit(s2_req.cmd, 3) - node T_2363 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2364 = or(T_2362, T_2363) - node T_2365 = or(T_2361, T_2364) - node T_2366 = or(T_2358, T_2365) - node T_2367 = and(T_2347, T_2366) - mshrs.req.valid := T_2367 - mshrs.req.bits <> s2_req - mshrs.req.bits.tag_match := s2_tag_match - wire T_2395 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_2395.coh.state := UInt<1>("h00") - T_2395.tag := UInt<1>("h00") - T_2395.tag := s2_repl_meta.tag - T_2395.coh <> s2_hit_state - wire T_2451 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_2451 <> s2_repl_meta - when s2_tag_match : - T_2451 <> T_2395 - skip - mshrs.req.bits.old_meta <> T_2451 - node T_2478 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) - mshrs.req.bits.way_en := T_2478 - mshrs.req.bits.data := s2_req.data - node T_2479 = and(mshrs.req.ready, mshrs.req.valid) - when T_2479 : - T_1941 := UInt<1>("h01") - skip - mem_1.acquire <> mshrs.mem_req - readArb.in[1].valid := mshrs.replay.valid - readArb.in[1].bits <> mshrs.replay.bits - node T_2482 = not(UInt<4>("h00")) - readArb.in[1].bits.way_en := T_2482 - mshrs.replay.ready := readArb.in[1].ready - node T_2483 = and(mshrs.replay.valid, readArb.in[1].ready) - s1_replay := T_2483 - metaReadArb.in[1] <> mshrs.meta_read - metaWriteArb.in[0] <> mshrs.meta_write - inst releaseArb of LockingArbiter_66 - releaseArb.out.ready := UInt<1>("h00") - releaseArb.in[0].bits.voluntary := UInt<1>("h00") - releaseArb.in[0].bits.r_type := UInt<1>("h00") - releaseArb.in[0].bits.data := UInt<1>("h00") - releaseArb.in[0].bits.addr_beat := UInt<1>("h00") - releaseArb.in[0].bits.client_xact_id := UInt<1>("h00") - releaseArb.in[0].bits.addr_block := UInt<1>("h00") - releaseArb.in[0].valid := UInt<1>("h00") - releaseArb.in[1].bits.voluntary := UInt<1>("h00") - releaseArb.in[1].bits.r_type := UInt<1>("h00") - releaseArb.in[1].bits.data := UInt<1>("h00") - releaseArb.in[1].bits.addr_beat := UInt<1>("h00") - releaseArb.in[1].bits.client_xact_id := UInt<1>("h00") - releaseArb.in[1].bits.addr_block := UInt<1>("h00") - releaseArb.in[1].valid := UInt<1>("h00") - releaseArb.reset := UInt<1>("h00") - releaseArb.clock := clock - releaseArb.reset := reset - mem_1.release <> releaseArb.out - node T_2531 = eq(lrsc_valid, UInt<1>("h00")) - node T_2532 = and(mem_1.probe.valid, T_2531) - prober.req.valid := T_2532 - node T_2534 = eq(lrsc_valid, UInt<1>("h00")) - node T_2535 = and(prober.req.ready, T_2534) - mem_1.probe.ready := T_2535 - prober.req.bits <> mem_1.probe.bits - releaseArb.in[1] <> prober.rep - prober.way_en := s2_tag_match_way - prober.block_state <> s2_hit_state - metaReadArb.in[2] <> prober.meta_read - metaWriteArb.in[1] <> prober.meta_write - prober.mshr_rdy := mshrs.probe_rdy - inst T_2836 of FlowThroughSerializer - T_2836.out.ready := UInt<1>("h00") - T_2836.in.bits.g_type := UInt<1>("h00") - T_2836.in.bits.is_builtin_type := UInt<1>("h00") - T_2836.in.bits.manager_xact_id := UInt<1>("h00") - T_2836.in.bits.client_xact_id := UInt<1>("h00") - T_2836.in.bits.data := UInt<1>("h00") - T_2836.in.bits.addr_beat := UInt<1>("h00") - T_2836.in.valid := UInt<1>("h00") - T_2836.reset := UInt<1>("h00") - T_2836.clock := clock - T_2836.reset := reset - T_2836.in.valid := mem_1.grant.valid - T_2836.in.bits <> mem_1.grant.bits - mem_1.grant.ready := T_2836.in.ready - node T_2545 = and(T_2836.out.ready, T_2836.out.valid) - mshrs.mem_grant.valid := T_2545 - mshrs.mem_grant.bits <> T_2836.out.bits - wire T_2549 : UInt<3>[2] - T_2549[0] := UInt<3>("h05") - T_2549[1] := UInt<3>("h04") - node T_2553 = eq(T_2549[0], T_2836.out.bits.g_type) - node T_2554 = eq(T_2549[1], T_2836.out.bits.g_type) - node T_2556 = or(UInt<1>("h00"), T_2553) - node T_2557 = or(T_2556, T_2554) - wire T_2559 : UInt<1>[2] - T_2559[0] := UInt<1>("h00") - T_2559[1] := UInt<1>("h01") - node T_2563 = eq(T_2559[0], T_2836.out.bits.g_type) - node T_2564 = eq(T_2559[1], T_2836.out.bits.g_type) - node T_2566 = or(UInt<1>("h00"), T_2563) - node T_2567 = or(T_2566, T_2564) - node T_2568 = mux(T_2836.out.bits.is_builtin_type, T_2557, T_2567) - node T_2570 = eq(T_2568, UInt<1>("h00")) - node T_2571 = or(writeArb.in[1].ready, T_2570) - T_2836.out.ready := T_2571 - wire T_2575 : UInt<3>[2] - T_2575[0] := UInt<3>("h05") - T_2575[1] := UInt<3>("h04") - node T_2579 = eq(T_2575[0], T_2836.out.bits.g_type) - node T_2580 = eq(T_2575[1], T_2836.out.bits.g_type) - node T_2582 = or(UInt<1>("h00"), T_2579) - node T_2583 = or(T_2582, T_2580) - wire T_2585 : UInt<1>[2] - T_2585[0] := UInt<1>("h00") - T_2585[1] := UInt<1>("h01") - node T_2589 = eq(T_2585[0], T_2836.out.bits.g_type) - node T_2590 = eq(T_2585[1], T_2836.out.bits.g_type) - node T_2592 = or(UInt<1>("h00"), T_2589) - node T_2593 = or(T_2592, T_2590) - node T_2594 = mux(T_2836.out.bits.is_builtin_type, T_2583, T_2593) - node T_2595 = and(T_2836.out.valid, T_2594) - writeArb.in[1].valid := T_2595 - writeArb.in[1].bits.addr := mshrs.refill.addr - writeArb.in[1].bits.way_en := mshrs.refill.way_en - node T_2597 = not(UInt<4>("h00")) - writeArb.in[1].bits.wmask := T_2597 - node T_2598 = bits(T_2836.out.bits.data, 127, 0) - writeArb.in[1].bits.data := T_2598 - data.read <> readArb.out - node T_2600 = eq(T_2836.out.valid, UInt<1>("h00")) - node T_2601 = or(T_2600, T_2836.out.ready) - readArb.out.ready := T_2601 - inst wbArb of Arbiter_54 - wbArb.out.ready := UInt<1>("h00") - wbArb.in[0].bits.way_en := UInt<1>("h00") - wbArb.in[0].bits.voluntary := UInt<1>("h00") - wbArb.in[0].bits.r_type := UInt<1>("h00") - wbArb.in[0].bits.data := UInt<1>("h00") - wbArb.in[0].bits.addr_beat := UInt<1>("h00") - wbArb.in[0].bits.client_xact_id := UInt<1>("h00") - wbArb.in[0].bits.addr_block := UInt<1>("h00") - wbArb.in[0].valid := UInt<1>("h00") - wbArb.in[1].bits.way_en := UInt<1>("h00") - wbArb.in[1].bits.voluntary := UInt<1>("h00") - wbArb.in[1].bits.r_type := UInt<1>("h00") - wbArb.in[1].bits.data := UInt<1>("h00") - wbArb.in[1].bits.addr_beat := UInt<1>("h00") - wbArb.in[1].bits.client_xact_id := UInt<1>("h00") - wbArb.in[1].bits.addr_block := UInt<1>("h00") - wbArb.in[1].valid := UInt<1>("h00") - wbArb.reset := UInt<1>("h00") - wbArb.clock := clock - wbArb.reset := reset - wbArb.in[0] <> prober.wb_req - wbArb.in[1] <> mshrs.wb_req - wb.req <> wbArb.out - metaReadArb.in[3] <> wb.meta_read - readArb.in[2] <> wb.data_req - wb.data_resp := s2_data_corrected - releaseArb.in[0] <> wb.release - reg s4_valid : UInt<1>, clock, reset - onreset s4_valid := UInt<1>("h00") - s4_valid := s3_valid - node T_2653 = and(s3_valid, metaReadArb.out.valid) - reg s4_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset - when T_2653 : - s4_req <> s3_req - skip - node T_2662 = or(s2_valid_masked, s2_replay) - node T_2664 = eq(s2_sc_fail, UInt<1>("h00")) - node T_2665 = and(T_2662, T_2664) - node T_2666 = shr(s1_addr, 3) - node T_2667 = shr(s2_req.addr, 3) - node T_2668 = eq(T_2666, T_2667) - node T_2669 = and(T_2665, T_2668) - node T_2670 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2671 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2672 = or(T_2670, T_2671) - node T_2673 = bit(s2_req.cmd, 3) - node T_2674 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2675 = or(T_2673, T_2674) - node T_2676 = or(T_2672, T_2675) - node T_2677 = and(T_2669, T_2676) - node T_2678 = shr(s1_addr, 3) - node T_2679 = shr(s3_req.addr, 3) - node T_2680 = eq(T_2678, T_2679) - node T_2681 = and(s3_valid, T_2680) - node T_2682 = eq(s3_req.cmd, UInt<5>("h01")) - node T_2683 = eq(s3_req.cmd, UInt<5>("h07")) - node T_2684 = or(T_2682, T_2683) - node T_2685 = bit(s3_req.cmd, 3) - node T_2686 = eq(s3_req.cmd, UInt<5>("h04")) - node T_2687 = or(T_2685, T_2686) - node T_2688 = or(T_2684, T_2687) - node T_2689 = and(T_2681, T_2688) - node T_2690 = shr(s1_addr, 3) - node T_2691 = shr(s4_req.addr, 3) - node T_2692 = eq(T_2690, T_2691) - node T_2693 = and(s4_valid, T_2692) - node T_2694 = eq(s4_req.cmd, UInt<5>("h01")) - node T_2695 = eq(s4_req.cmd, UInt<5>("h07")) - node T_2696 = or(T_2694, T_2695) - node T_2697 = bit(s4_req.cmd, 3) - node T_2698 = eq(s4_req.cmd, UInt<5>("h04")) - node T_2699 = or(T_2697, T_2698) - node T_2700 = or(T_2696, T_2699) - node T_2701 = and(T_2693, T_2700) - reg s2_store_bypass_data : UInt<64>, clock, reset - reg s2_store_bypass : UInt<1>, clock, reset - when s1_clk_en : - s2_store_bypass := UInt<1>("h00") - node T_2707 = or(T_2677, T_2689) - node T_2708 = or(T_2707, T_2701) - when T_2708 : - node T_2709 = mux(T_2689, s3_req.data, s4_req.data) - node T_2710 = mux(T_2677, amoalu.out, T_2709) - s2_store_bypass_data := T_2710 - s2_store_bypass := UInt<1>("h01") - skip - skip - node T_2713 = cat(UInt<1>("h00"), UInt<6>("h00")) - node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_2713) - node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) - node T_2716 = eq(s2_req.typ, UInt<3>("h00")) - node T_2717 = eq(s2_req.typ, UInt<3>("h04")) - node T_2718 = or(T_2716, T_2717) - node T_2719 = eq(s2_req.typ, UInt<3>("h01")) - node T_2720 = eq(s2_req.typ, UInt<3>("h05")) - node T_2721 = or(T_2719, T_2720) - node T_2722 = eq(s2_req.typ, UInt<3>("h02")) - node T_2723 = eq(s2_req.typ, UInt<3>("h06")) - node T_2724 = or(T_2722, T_2723) - node T_2725 = eq(s2_req.typ, UInt<3>("h00")) - node T_2726 = eq(s2_req.typ, UInt<3>("h01")) - node T_2727 = or(T_2725, T_2726) - node T_2728 = eq(s2_req.typ, UInt<3>("h02")) - node T_2729 = or(T_2727, T_2728) - node T_2730 = eq(s2_req.typ, UInt<3>("h03")) - node T_2731 = or(T_2729, T_2730) - node T_2732 = bit(s2_req.addr, 2) - node T_2733 = bits(s2_data_word, 63, 32) - node T_2734 = bits(s2_data_word, 31, 0) - node T_2735 = mux(T_2732, T_2733, T_2734) - node T_2736 = bit(T_2735, 31) - node T_2737 = and(T_2731, T_2736) - node T_2739 = subw(UInt<32>("h00"), T_2737) - node T_2740 = bits(s2_data_word, 63, 32) - node T_2741 = mux(T_2724, T_2739, T_2740) - node T_2742 = cat(T_2741, T_2735) - node T_2743 = bit(s2_req.addr, 1) - node T_2744 = bits(T_2742, 31, 16) - node T_2745 = bits(T_2742, 15, 0) - node T_2746 = mux(T_2743, T_2744, T_2745) - node T_2747 = bit(T_2746, 15) - node T_2748 = and(T_2731, T_2747) - node T_2750 = subw(UInt<48>("h00"), T_2748) - node T_2751 = bits(T_2742, 63, 16) - node T_2752 = mux(T_2721, T_2750, T_2751) - node T_2753 = cat(T_2752, T_2746) - node T_2755 = bit(s2_req.addr, 0) - node T_2756 = bits(T_2753, 15, 8) - node T_2757 = bits(T_2753, 7, 0) - node T_2758 = mux(T_2755, T_2756, T_2757) - node T_2759 = mux(s2_sc, UInt<1>("h00"), T_2758) - node T_2760 = or(s2_sc, T_2718) - node T_2761 = bit(T_2759, 7) - node T_2762 = and(T_2731, T_2761) - node T_2764 = subw(UInt<56>("h00"), T_2762) - node T_2765 = bits(T_2753, 63, 8) - node T_2766 = mux(T_2760, T_2764, T_2765) - node T_2767 = cat(T_2766, T_2759) - amoalu.addr := s2_req.addr - amoalu.cmd := s2_req.cmd - amoalu.typ := s2_req.typ - amoalu.lhs := s2_data_word - amoalu.rhs := s2_req.data - node T_2768 = and(dtlb.req.valid, dtlb.resp.miss) - node T_2769 = bits(s1_req.addr, 11, 6) - node T_2770 = eq(T_2769, prober.meta_write.bits.idx) - node T_2772 = eq(prober.req.ready, UInt<1>("h00")) - node T_2773 = and(T_2770, T_2772) - node s1_nack = or(T_2768, T_2773) - node T_2775 = or(s1_valid, s1_replay) - reg s2_nack_hit : UInt<1>, clock, reset - when T_2775 : - s2_nack_hit := s1_nack - skip - when s2_nack_hit : - mshrs.req.valid := UInt<1>("h00") - skip - node s2_nack_victim = and(s2_hit, mshrs.secondary_miss) - node T_2780 = eq(s2_hit, UInt<1>("h00")) - node T_2782 = eq(mshrs.req.ready, UInt<1>("h00")) - node s2_nack_miss = and(T_2780, T_2782) - node T_2784 = or(s2_nack_hit, s2_nack_victim) - node s2_nack = or(T_2784, s2_nack_miss) - node T_2787 = eq(s2_nack, UInt<1>("h00")) - node T_2788 = and(s2_valid, T_2787) - s2_valid_masked := T_2788 - node T_2789 = or(s2_valid, s2_replay) - node T_2790 = and(T_2789, s2_hit) - node s2_recycle_ecc = and(T_2790, s2_data_correctable) - reg s2_recycle_next : UInt<1>, clock, reset - onreset s2_recycle_next := UInt<1>("h00") - node T_2794 = or(s1_valid, s1_replay) - when T_2794 : - s2_recycle_next := s2_recycle_ecc - skip - node T_2795 = or(s2_recycle_ecc, s2_recycle_next) - s2_recycle := T_2795 - reg block_miss : UInt<1>, clock, reset - onreset block_miss := UInt<1>("h00") - node T_2798 = or(s2_valid, block_miss) - node T_2799 = and(T_2798, s2_nack_miss) - block_miss := T_2799 - when block_miss : - cpu.req.ready := UInt<1>("h00") - skip - node T_2801 = and(s2_valid_masked, s2_hit) - node T_2802 = or(s2_replay, T_2801) - node T_2804 = eq(s2_data_correctable, UInt<1>("h00")) - node T_2805 = and(T_2802, T_2804) - cpu.resp.valid := T_2805 - node T_2806 = and(s2_valid, s2_nack) - cpu.resp.bits.nack := T_2806 - cpu.resp.bits <> s2_req - node T_2807 = eq(s2_req.cmd, UInt<5>("h00")) - node T_2808 = eq(s2_req.cmd, UInt<5>("h06")) - node T_2809 = or(T_2807, T_2808) - node T_2810 = bit(s2_req.cmd, 3) - node T_2811 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2812 = or(T_2810, T_2811) - node T_2813 = or(T_2809, T_2812) - node T_2814 = or(T_2813, s2_sc) - cpu.resp.bits.has_data := T_2814 - cpu.resp.bits.replay := s2_replay - cpu.resp.bits.data := T_2742 - node T_2815 = or(T_2767, s2_sc_fail) - cpu.resp.bits.data_subword := T_2815 - cpu.resp.bits.store_data := s2_req.data - node T_2817 = eq(s1_valid, UInt<1>("h00")) - node T_2818 = and(mshrs.fence_rdy, T_2817) - node T_2820 = eq(s2_valid, UInt<1>("h00")) - node T_2821 = and(T_2818, T_2820) - cpu.ordered := T_2821 - node T_2822 = or(s1_read, s1_sc) - node T_2823 = and(s1_replay, T_2822) - cpu.replay_next.valid := T_2823 - cpu.replay_next.bits := s1_req.tag - - module RRArbiter_69 : - output chosen : UInt<1> - output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}} - input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2] - input clock : Clock - input reset : UInt<1> - - chosen := UInt<1>("h00") - out.bits.fetch := UInt<1>("h00") - out.bits.store := UInt<1>("h00") - out.bits.prv := UInt<1>("h00") - out.bits.addr := UInt<1>("h00") - out.valid := UInt<1>("h00") - in[0].ready := UInt<1>("h00") - in[1].ready := UInt<1>("h00") - wire T_152 : UInt<1> - T_152 := UInt<1>("h00") - infer accessor T_154 = in[T_152] - out.valid := T_154.valid - infer accessor T_167 = in[T_152] - out.bits <> T_167.bits - chosen := T_152 - infer accessor T_180 = in[T_152] - T_180.ready := UInt<1>("h00") - reg T_196 : UInt<1>, clock, reset - onreset T_196 := UInt<1>("h00") - node T_197 = gt(UInt<1>("h00"), T_196) - node T_198 = and(in[0].valid, T_197) - node T_200 = gt(UInt<1>("h01"), T_196) - node T_201 = and(in[1].valid, T_200) - node T_204 = or(UInt<1>("h00"), T_198) - node T_206 = eq(T_204, UInt<1>("h00")) - node T_208 = or(UInt<1>("h00"), T_198) - node T_209 = or(T_208, T_201) - node T_211 = eq(T_209, UInt<1>("h00")) - node T_213 = or(UInt<1>("h00"), T_198) - node T_214 = or(T_213, T_201) - node T_215 = or(T_214, in[0].valid) - node T_217 = eq(T_215, UInt<1>("h00")) - node T_219 = gt(UInt<1>("h00"), T_196) - node T_220 = and(UInt<1>("h01"), T_219) - node T_221 = or(T_220, T_211) - node T_223 = gt(UInt<1>("h01"), T_196) - node T_224 = and(T_206, T_223) - node T_225 = or(T_224, T_217) - node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_228 = mux(UInt<1>("h00"), T_227, T_221) - node T_229 = and(T_228, out.ready) - in[0].ready := T_229 - node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_232 = mux(UInt<1>("h00"), T_231, T_225) - node T_233 = and(T_232, out.ready) - in[1].ready := T_233 - node T_236 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_238 = gt(UInt<1>("h01"), T_196) - node T_239 = and(in[1].valid, T_238) - node T_241 = mux(T_239, UInt<1>("h01"), T_236) - node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) - T_152 := T_242 - node T_243 = and(out.ready, out.valid) - when T_243 : - T_196 := T_152 - skip - - module PTW : - output dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}} - output mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} - input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2] - input clock : Clock - input reset : UInt<1> - - mem_1.invalidate_lr := UInt<1>("h00") - mem_1.req.bits.data := UInt<1>("h00") - mem_1.req.bits.phys := UInt<1>("h00") - mem_1.req.bits.kill := UInt<1>("h00") - mem_1.req.bits.typ := UInt<1>("h00") - mem_1.req.bits.cmd := UInt<1>("h00") - mem_1.req.bits.tag := UInt<1>("h00") - mem_1.req.bits.addr := UInt<1>("h00") - mem_1.req.valid := UInt<1>("h00") - requestor[0].invalidate := UInt<1>("h00") - requestor[0].status.ie := UInt<1>("h00") - requestor[0].status.prv := UInt<1>("h00") - requestor[0].status.ie1 := UInt<1>("h00") - requestor[0].status.prv1 := UInt<1>("h00") - requestor[0].status.ie2 := UInt<1>("h00") - requestor[0].status.prv2 := UInt<1>("h00") - requestor[0].status.ie3 := UInt<1>("h00") - requestor[0].status.prv3 := UInt<1>("h00") - requestor[0].status.fs := UInt<1>("h00") - requestor[0].status.xs := UInt<1>("h00") - requestor[0].status.mprv := UInt<1>("h00") - requestor[0].status.vm := UInt<1>("h00") - requestor[0].status.zero1 := UInt<1>("h00") - requestor[0].status.sd_rv32 := UInt<1>("h00") - requestor[0].status.zero2 := UInt<1>("h00") - requestor[0].status.sd := UInt<1>("h00") - requestor[0].resp.bits.pte.v := UInt<1>("h00") - requestor[0].resp.bits.pte.typ := UInt<1>("h00") - requestor[0].resp.bits.pte.r := UInt<1>("h00") - requestor[0].resp.bits.pte.d := UInt<1>("h00") - requestor[0].resp.bits.pte.reserved_for_software := UInt<1>("h00") - requestor[0].resp.bits.pte.ppn := UInt<1>("h00") - requestor[0].resp.bits.error := UInt<1>("h00") - requestor[0].resp.valid := UInt<1>("h00") - requestor[0].req.ready := UInt<1>("h00") - requestor[1].invalidate := UInt<1>("h00") - requestor[1].status.ie := UInt<1>("h00") - requestor[1].status.prv := UInt<1>("h00") - requestor[1].status.ie1 := UInt<1>("h00") - requestor[1].status.prv1 := UInt<1>("h00") - requestor[1].status.ie2 := UInt<1>("h00") - requestor[1].status.prv2 := UInt<1>("h00") - requestor[1].status.ie3 := UInt<1>("h00") - requestor[1].status.prv3 := UInt<1>("h00") - requestor[1].status.fs := UInt<1>("h00") - requestor[1].status.xs := UInt<1>("h00") - requestor[1].status.mprv := UInt<1>("h00") - requestor[1].status.vm := UInt<1>("h00") - requestor[1].status.zero1 := UInt<1>("h00") - requestor[1].status.sd_rv32 := UInt<1>("h00") - requestor[1].status.zero2 := UInt<1>("h00") - requestor[1].status.sd := UInt<1>("h00") - requestor[1].resp.bits.pte.v := UInt<1>("h00") - requestor[1].resp.bits.pte.typ := UInt<1>("h00") - requestor[1].resp.bits.pte.r := UInt<1>("h00") - requestor[1].resp.bits.pte.d := UInt<1>("h00") - requestor[1].resp.bits.pte.reserved_for_software := UInt<1>("h00") - requestor[1].resp.bits.pte.ppn := UInt<1>("h00") - requestor[1].resp.bits.error := UInt<1>("h00") - requestor[1].resp.valid := UInt<1>("h00") - requestor[1].req.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg count : UInt<2>, clock, reset - reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clock, reset - reg r_req_dest : UInt, clock, reset - reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clock, reset - node T_1222 = shr(r_req.addr, 18) - node T_1223 = bits(T_1222, 8, 0) - node T_1224 = shr(r_req.addr, 9) - node T_1225 = bits(T_1224, 8, 0) - node T_1226 = shr(r_req.addr, 0) - node T_1227 = bits(T_1226, 8, 0) - wire T_1229 : UInt<9>[3] - T_1229[0] := T_1223 - T_1229[1] := T_1225 - T_1229[2] := T_1227 - infer accessor vpn_idx = T_1229[count] - inst arb of RRArbiter_69 - arb.out.ready := UInt<1>("h00") - arb.in[0].bits.fetch := UInt<1>("h00") - arb.in[0].bits.store := UInt<1>("h00") - arb.in[0].bits.prv := UInt<1>("h00") - arb.in[0].bits.addr := UInt<1>("h00") - arb.in[0].valid := UInt<1>("h00") - arb.in[1].bits.fetch := UInt<1>("h00") - arb.in[1].bits.store := UInt<1>("h00") - arb.in[1].bits.prv := UInt<1>("h00") - arb.in[1].bits.addr := UInt<1>("h00") - arb.in[1].valid := UInt<1>("h00") - arb.reset := UInt<1>("h00") - arb.clock := clock - arb.reset := reset - arb.in[0] <> requestor[0].req - arb.in[1] <> requestor[1].req - node T_1252 = eq(state, UInt<1>("h00")) - arb.out.ready := T_1252 - wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte.v := UInt<1>("h00") - pte.typ := UInt<1>("h00") - pte.r := UInt<1>("h00") - pte.d := UInt<1>("h00") - pte.reserved_for_software := UInt<1>("h00") - pte.ppn := UInt<1>("h00") - node T_1280 = bits(mem_1.resp.bits.data, 0, 0) - pte.v := T_1280 - node T_1281 = bits(mem_1.resp.bits.data, 4, 1) - pte.typ := T_1281 - node T_1282 = bits(mem_1.resp.bits.data, 5, 5) - pte.r := T_1282 - node T_1283 = bits(mem_1.resp.bits.data, 6, 6) - pte.d := T_1283 - node T_1284 = bits(mem_1.resp.bits.data, 9, 7) - pte.reserved_for_software := T_1284 - node T_1285 = bits(mem_1.resp.bits.data, 29, 10) - pte.ppn := T_1285 - node T_1286 = cat(r_pte.ppn, vpn_idx) - node pte_addr = shl(T_1286, 3) - node T_1288 = and(arb.out.ready, arb.out.valid) - when T_1288 : - r_req <> arb.out.bits - r_req_dest := arb.chosen - node T_1289 = bits(dpath.ptbr, 31, 12) - r_pte.ppn := T_1289 - skip - reg T_1291 : UInt<3>, clock, reset - reg T_1301 : UInt<1>[3], clock, reset - node T_1306 = cat(T_1301[1], T_1301[0]) - node T_1307 = cat(T_1301[2], T_1306) - cmem T_1310 : UInt<32>[3], clock - cmem T_1313 : UInt<20>[3], clock - infer accessor T_1315 = T_1310[UInt<1>("h00")] - node T_1316 = eq(T_1315, pte_addr) - infer accessor T_1318 = T_1310[UInt<1>("h01")] - node T_1319 = eq(T_1318, pte_addr) - infer accessor T_1321 = T_1310[UInt<2>("h02")] - node T_1322 = eq(T_1321, pte_addr) - wire T_1324 : UInt<1>[3] - T_1324[0] := T_1316 - T_1324[1] := T_1319 - T_1324[2] := T_1322 - node T_1329 = cat(T_1324[1], T_1324[0]) - node T_1330 = cat(T_1324[2], T_1329) - node T_1331 = and(T_1330, T_1307) - node pte_cache_hit = neq(T_1331, UInt<1>("h00")) - node T_1335 = lt(pte.typ, UInt<2>("h02")) - node T_1336 = and(pte.v, T_1335) - node T_1337 = and(mem_1.resp.valid, T_1336) - node T_1339 = eq(pte_cache_hit, UInt<1>("h00")) - node T_1340 = and(T_1337, T_1339) - when T_1340 : - node T_1341 = not(T_1307) - node T_1343 = eq(T_1341, UInt<1>("h00")) - node T_1345 = dshr(T_1291, UInt<1>("h01")) - node T_1346 = bit(T_1345, 0) - node T_1347 = cat(UInt<1>("h01"), T_1346) - node T_1348 = dshr(T_1291, T_1347) - node T_1349 = bit(T_1348, 0) - node T_1350 = cat(T_1347, T_1349) - node T_1351 = bits(T_1350, 1, 0) - node T_1352 = not(T_1307) - node T_1353 = bit(T_1352, 0) - node T_1354 = bit(T_1352, 1) - node T_1355 = bit(T_1352, 2) - wire T_1357 : UInt<1>[3] - T_1357[0] := T_1353 - T_1357[1] := T_1354 - T_1357[2] := T_1355 - node T_1365 = mux(T_1357[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1366 = mux(T_1357[0], UInt<1>("h00"), T_1365) - node T_1367 = mux(T_1343, T_1351, T_1366) - infer accessor T_1368 = T_1301[T_1367] - T_1368 := UInt<1>("h01") - infer accessor T_1370 = T_1310[T_1367] - T_1370 := pte_addr - infer accessor T_1371 = T_1313[T_1367] - T_1371 := pte.ppn - skip - node T_1372 = eq(state, UInt<1>("h01")) - node T_1373 = and(pte_cache_hit, T_1372) - when T_1373 : - node T_1374 = bits(T_1331, 2, 2) - node T_1375 = bits(T_1331, 1, 0) - node T_1377 = neq(T_1374, UInt<1>("h00")) - node T_1378 = or(T_1374, T_1375) - node T_1379 = bit(T_1378, 1) - node T_1380 = cat(T_1377, T_1379) - node T_1382 = bit(T_1380, 1) - node T_1384 = dshl(UInt<3>("h01"), UInt<1>("h01")) - node T_1385 = bits(T_1384, 2, 0) - node T_1386 = not(T_1385) - node T_1387 = and(T_1291, T_1386) - node T_1389 = mux(T_1382, UInt<1>("h00"), T_1385) - node T_1390 = or(T_1387, T_1389) - node T_1391 = cat(UInt<1>("h01"), T_1382) - node T_1392 = bit(T_1380, 0) - node T_1394 = dshl(UInt<3>("h01"), T_1391) - node T_1395 = bits(T_1394, 2, 0) - node T_1396 = not(T_1395) - node T_1397 = and(T_1390, T_1396) - node T_1399 = mux(T_1392, UInt<1>("h00"), T_1395) - node T_1400 = or(T_1397, T_1399) - node T_1401 = cat(T_1391, T_1392) - T_1291 := T_1400 - skip - node T_1402 = or(reset, dpath.invalidate) - when T_1402 : - T_1301[0] := UInt<1>("h00") - T_1301[1] := UInt<1>("h00") - T_1301[2] := UInt<1>("h00") - skip - node T_1406 = bit(T_1331, 0) - node T_1407 = bit(T_1331, 1) - node T_1408 = bit(T_1331, 2) - infer accessor T_1410 = T_1313[UInt<1>("h00")] - infer accessor T_1412 = T_1313[UInt<1>("h01")] - infer accessor T_1414 = T_1313[UInt<2>("h02")] - node T_1416 = mux(T_1406, T_1410, UInt<1>("h00")) - node T_1418 = mux(T_1407, T_1412, UInt<1>("h00")) - node T_1420 = mux(T_1408, T_1414, UInt<1>("h00")) - node T_1422 = or(T_1416, T_1418) - node T_1423 = or(T_1422, T_1420) - wire pte_cache_data : UInt<20> - pte_cache_data := UInt<1>("h00") - pte_cache_data := T_1423 - node T_1426 = bit(r_req.prv, 0) - node T_1428 = geq(pte.typ, UInt<3>("h04")) - node T_1429 = and(pte.v, T_1428) - node T_1430 = bit(pte.typ, 1) - node T_1431 = and(T_1429, T_1430) - node T_1433 = geq(pte.typ, UInt<2>("h02")) - node T_1434 = and(pte.v, T_1433) - node T_1435 = bit(pte.typ, 0) - node T_1436 = and(T_1434, T_1435) - node T_1438 = geq(pte.typ, UInt<2>("h02")) - node T_1439 = and(pte.v, T_1438) - node T_1440 = mux(r_req.store, T_1436, T_1439) - node T_1441 = mux(r_req.fetch, T_1431, T_1440) - node T_1443 = geq(pte.typ, UInt<2>("h02")) - node T_1444 = and(pte.v, T_1443) - node T_1446 = lt(pte.typ, UInt<4>("h08")) - node T_1447 = and(T_1444, T_1446) - node T_1448 = bit(pte.typ, 1) - node T_1449 = and(T_1447, T_1448) - node T_1451 = geq(pte.typ, UInt<2>("h02")) - node T_1452 = and(pte.v, T_1451) - node T_1454 = lt(pte.typ, UInt<4>("h08")) - node T_1455 = and(T_1452, T_1454) - node T_1456 = bit(pte.typ, 0) - node T_1457 = and(T_1455, T_1456) - node T_1459 = geq(pte.typ, UInt<2>("h02")) - node T_1460 = and(pte.v, T_1459) - node T_1462 = lt(pte.typ, UInt<4>("h08")) - node T_1463 = and(T_1460, T_1462) - node T_1464 = mux(r_req.store, T_1457, T_1463) - node T_1465 = mux(r_req.fetch, T_1449, T_1464) - node perm_ok = mux(T_1426, T_1441, T_1465) - node T_1468 = eq(pte.r, UInt<1>("h00")) - node T_1470 = eq(pte.d, UInt<1>("h00")) - node T_1471 = and(r_req.store, T_1470) - node T_1472 = or(T_1468, T_1471) - node set_dirty_bit = and(perm_ok, T_1472) - node T_1474 = eq(state, UInt<2>("h02")) - node T_1475 = and(mem_1.resp.valid, T_1474) - node T_1477 = eq(set_dirty_bit, UInt<1>("h00")) - node T_1478 = and(T_1475, T_1477) - when T_1478 : - r_pte <> pte - skip - wire T_1494 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - T_1494.v := UInt<1>("h00") - T_1494.typ := UInt<1>("h00") - T_1494.r := UInt<1>("h00") - T_1494.d := UInt<1>("h00") - T_1494.reserved_for_software := UInt<1>("h00") - T_1494.ppn := UInt<1>("h00") - T_1494.v := UInt<1>("h00") - T_1494.typ := UInt<4>("h00") - T_1494.r := UInt<1>("h00") - T_1494.d := UInt<1>("h00") - T_1494.reserved_for_software := UInt<3>("h00") - T_1494.ppn := UInt<20>("h00") - wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte_wdata <> T_1494 - pte_wdata.r := UInt<1>("h01") - pte_wdata.d := r_req.store - node T_1521 = eq(state, UInt<1>("h01")) - node T_1522 = eq(state, UInt<2>("h03")) - node T_1523 = or(T_1521, T_1522) - mem_1.req.valid := T_1523 - mem_1.req.bits.phys := UInt<1>("h01") - node T_1525 = eq(state, UInt<2>("h03")) - node T_1526 = mux(T_1525, UInt<5>("h0a"), UInt<5>("h00")) - mem_1.req.bits.cmd := T_1526 - mem_1.req.bits.typ := UInt<3>("h03") - mem_1.req.bits.addr := pte_addr - mem_1.req.bits.kill := UInt<1>("h00") - node T_1528 = cat(pte_wdata.reserved_for_software, pte_wdata.d) - node T_1529 = cat(pte_wdata.ppn, T_1528) - node T_1530 = cat(pte_wdata.typ, pte_wdata.v) - node T_1531 = cat(pte_wdata.r, T_1530) - node T_1532 = cat(T_1529, T_1531) - mem_1.req.bits.data := T_1532 - node resp_err = eq(state, UInt<3>("h06")) - node T_1534 = eq(state, UInt<3>("h05")) - node resp_val = or(T_1534, resp_err) - node r_resp_ppn = shr(mem_1.req.bits.addr, 12) - node T_1537 = shr(r_resp_ppn, 18) - node T_1538 = bits(r_req.addr, 17, 0) - node T_1539 = cat(T_1537, T_1538) - node T_1540 = shr(r_resp_ppn, 9) - node T_1541 = bits(r_req.addr, 8, 0) - node T_1542 = cat(T_1540, T_1541) - wire T_1544 : UInt<28>[3] - T_1544[0] := T_1539 - T_1544[1] := T_1542 - T_1544[2] := r_resp_ppn - infer accessor resp_ppn = T_1544[count] - node T_1551 = eq(r_req_dest, UInt<1>("h00")) - node T_1552 = and(resp_val, T_1551) - requestor[0].resp.valid := T_1552 - requestor[0].resp.bits.error := resp_err - requestor[0].resp.bits.pte <> r_pte - requestor[0].resp.bits.pte.ppn := resp_ppn - requestor[0].invalidate := dpath.invalidate - requestor[0].status <> dpath.status - node T_1554 = eq(r_req_dest, UInt<1>("h01")) - node T_1555 = and(resp_val, T_1554) - requestor[1].resp.valid := T_1555 - requestor[1].resp.bits.error := resp_err - requestor[1].resp.bits.pte <> r_pte - requestor[1].resp.bits.pte.ppn := resp_ppn - requestor[1].invalidate := dpath.invalidate - requestor[1].status <> dpath.status - node T_1556 = eq(UInt<1>("h00"), state) - when T_1556 : - when arb.out.valid : - state := UInt<1>("h01") - skip - count := UInt<1>("h00") - skip - node T_1558 = eq(UInt<1>("h01"), state) - when T_1558 : - node T_1560 = lt(count, UInt<2>("h02")) - node T_1561 = and(pte_cache_hit, T_1560) - when T_1561 : - mem_1.req.valid := UInt<1>("h00") - state := UInt<1>("h01") - node T_1564 = addw(count, UInt<1>("h01")) - count := T_1564 - r_pte.ppn := pte_cache_data - skip - else : - when mem_1.req.ready : - state := UInt<2>("h02") - skip - skip - skip - node T_1565 = eq(UInt<2>("h02"), state) - when T_1565 : - when mem_1.resp.bits.nack : - state := UInt<1>("h01") - skip - when mem_1.resp.valid : - state := UInt<3>("h06") - node T_1567 = lt(pte.typ, UInt<2>("h02")) - node T_1568 = and(pte.v, T_1567) - node T_1570 = lt(count, UInt<2>("h02")) - node T_1571 = and(T_1568, T_1570) - when T_1571 : - state := UInt<1>("h01") - node T_1573 = addw(count, UInt<1>("h01")) - count := T_1573 - skip - node T_1575 = geq(pte.typ, UInt<2>("h02")) - node T_1576 = and(pte.v, T_1575) - when T_1576 : - node T_1577 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) - state := T_1577 - skip - skip - skip - node T_1578 = eq(UInt<2>("h03"), state) - when T_1578 : - when mem_1.req.ready : - state := UInt<3>("h04") - skip - skip - node T_1579 = eq(UInt<3>("h04"), state) - when T_1579 : - when mem_1.resp.bits.nack : - state := UInt<2>("h03") - skip - when mem_1.resp.valid : - state := UInt<1>("h01") - skip - skip - node T_1580 = eq(UInt<3>("h05"), state) - when T_1580 : - state := UInt<1>("h00") - skip - node T_1581 = eq(UInt<3>("h06"), state) - when T_1581 : - state := UInt<1>("h00") - skip - - module CSRFile : - output interrupt_cause : UInt<64> - output interrupt : UInt<1> - input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst_1 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>} - input fcsr_flags : {valid : UInt<1>, bits : UInt<5>} - output fcsr_rm : UInt<3> - output time : UInt<64> - output fatc : UInt<1> - input pc : UInt<40> - input cause : UInt<64> - input custom_mrw_csrs : UInt<64>[0] - input uarch_counters : UInt<1>[16] - input retire : UInt<1> - input exception : UInt<1> - output evec : UInt<40> - output ptbr : UInt<32> - output status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} - output eret : UInt<1> - output csr_xcpt : UInt<1> - output csr_stall : UInt<1> - output csr_replay : UInt<1> - output rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>} - output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - interrupt_cause := UInt<1>("h00") - interrupt := UInt<1>("h00") - rocc.exception := UInt<1>("h00") - rocc.pptw.invalidate := UInt<1>("h00") - rocc.pptw.status.ie := UInt<1>("h00") - rocc.pptw.status.prv := UInt<1>("h00") - rocc.pptw.status.ie1 := UInt<1>("h00") - rocc.pptw.status.prv1 := UInt<1>("h00") - rocc.pptw.status.ie2 := UInt<1>("h00") - rocc.pptw.status.prv2 := UInt<1>("h00") - rocc.pptw.status.ie3 := UInt<1>("h00") - rocc.pptw.status.prv3 := UInt<1>("h00") - rocc.pptw.status.fs := UInt<1>("h00") - rocc.pptw.status.xs := UInt<1>("h00") - rocc.pptw.status.mprv := UInt<1>("h00") - rocc.pptw.status.vm := UInt<1>("h00") - rocc.pptw.status.zero1 := UInt<1>("h00") - rocc.pptw.status.sd_rv32 := UInt<1>("h00") - rocc.pptw.status.zero2 := UInt<1>("h00") - rocc.pptw.status.sd := UInt<1>("h00") - rocc.pptw.resp.bits.pte.v := UInt<1>("h00") - rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.pptw.resp.bits.pte.r := UInt<1>("h00") - rocc.pptw.resp.bits.pte.d := UInt<1>("h00") - rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.pptw.resp.bits.error := UInt<1>("h00") - rocc.pptw.resp.valid := UInt<1>("h00") - rocc.pptw.req.ready := UInt<1>("h00") - rocc.dptw.invalidate := UInt<1>("h00") - rocc.dptw.status.ie := UInt<1>("h00") - rocc.dptw.status.prv := UInt<1>("h00") - rocc.dptw.status.ie1 := UInt<1>("h00") - rocc.dptw.status.prv1 := UInt<1>("h00") - rocc.dptw.status.ie2 := UInt<1>("h00") - rocc.dptw.status.prv2 := UInt<1>("h00") - rocc.dptw.status.ie3 := UInt<1>("h00") - rocc.dptw.status.prv3 := UInt<1>("h00") - rocc.dptw.status.fs := UInt<1>("h00") - rocc.dptw.status.xs := UInt<1>("h00") - rocc.dptw.status.mprv := UInt<1>("h00") - rocc.dptw.status.vm := UInt<1>("h00") - rocc.dptw.status.zero1 := UInt<1>("h00") - rocc.dptw.status.sd_rv32 := UInt<1>("h00") - rocc.dptw.status.zero2 := UInt<1>("h00") - rocc.dptw.status.sd := UInt<1>("h00") - rocc.dptw.resp.bits.pte.v := UInt<1>("h00") - rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.dptw.resp.bits.pte.r := UInt<1>("h00") - rocc.dptw.resp.bits.pte.d := UInt<1>("h00") - rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.dptw.resp.bits.error := UInt<1>("h00") - rocc.dptw.resp.valid := UInt<1>("h00") - rocc.dptw.req.ready := UInt<1>("h00") - rocc.iptw.invalidate := UInt<1>("h00") - rocc.iptw.status.ie := UInt<1>("h00") - rocc.iptw.status.prv := UInt<1>("h00") - rocc.iptw.status.ie1 := UInt<1>("h00") - rocc.iptw.status.prv1 := UInt<1>("h00") - rocc.iptw.status.ie2 := UInt<1>("h00") - rocc.iptw.status.prv2 := UInt<1>("h00") - rocc.iptw.status.ie3 := UInt<1>("h00") - rocc.iptw.status.prv3 := UInt<1>("h00") - rocc.iptw.status.fs := UInt<1>("h00") - rocc.iptw.status.xs := UInt<1>("h00") - rocc.iptw.status.mprv := UInt<1>("h00") - rocc.iptw.status.vm := UInt<1>("h00") - rocc.iptw.status.zero1 := UInt<1>("h00") - rocc.iptw.status.sd_rv32 := UInt<1>("h00") - rocc.iptw.status.zero2 := UInt<1>("h00") - rocc.iptw.status.sd := UInt<1>("h00") - rocc.iptw.resp.bits.pte.v := UInt<1>("h00") - rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.iptw.resp.bits.pte.r := UInt<1>("h00") - rocc.iptw.resp.bits.pte.d := UInt<1>("h00") - rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.iptw.resp.bits.error := UInt<1>("h00") - rocc.iptw.resp.valid := UInt<1>("h00") - rocc.iptw.req.ready := UInt<1>("h00") - rocc.dmem.grant.bits.g_type := UInt<1>("h00") - rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") - rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") - rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") - rocc.dmem.grant.bits.data := UInt<1>("h00") - rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") - rocc.dmem.grant.valid := UInt<1>("h00") - rocc.dmem.acquire.ready := UInt<1>("h00") - rocc.imem.grant.bits.g_type := UInt<1>("h00") - rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") - rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") - rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") - rocc.imem.grant.bits.data := UInt<1>("h00") - rocc.imem.grant.bits.addr_beat := UInt<1>("h00") - rocc.imem.grant.valid := UInt<1>("h00") - rocc.imem.acquire.ready := UInt<1>("h00") - rocc.s := UInt<1>("h00") - rocc.mem_1.ordered := UInt<1>("h00") - rocc.mem_1.xcpt.pf.st := UInt<1>("h00") - rocc.mem_1.xcpt.pf.ld := UInt<1>("h00") - rocc.mem_1.xcpt.ma.st := UInt<1>("h00") - rocc.mem_1.xcpt.ma.ld := UInt<1>("h00") - rocc.mem_1.replay_next.bits := UInt<1>("h00") - rocc.mem_1.replay_next.valid := UInt<1>("h00") - rocc.mem_1.resp.bits.store_data := UInt<1>("h00") - rocc.mem_1.resp.bits.data_subword := UInt<1>("h00") - rocc.mem_1.resp.bits.has_data := UInt<1>("h00") - rocc.mem_1.resp.bits.replay := UInt<1>("h00") - rocc.mem_1.resp.bits.nack := UInt<1>("h00") - rocc.mem_1.resp.bits.data := UInt<1>("h00") - rocc.mem_1.resp.bits.typ := UInt<1>("h00") - rocc.mem_1.resp.bits.cmd := UInt<1>("h00") - rocc.mem_1.resp.bits.tag := UInt<1>("h00") - rocc.mem_1.resp.bits.addr := UInt<1>("h00") - rocc.mem_1.resp.valid := UInt<1>("h00") - rocc.mem_1.req.ready := UInt<1>("h00") - rocc.resp.ready := UInt<1>("h00") - rocc.cmd.bits.rs2 := UInt<1>("h00") - rocc.cmd.bits.rs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.opcode := UInt<1>("h00") - rocc.cmd.bits.inst_1.rd := UInt<1>("h00") - rocc.cmd.bits.inst_1.xs2 := UInt<1>("h00") - rocc.cmd.bits.inst_1.xs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.xd := UInt<1>("h00") - rocc.cmd.bits.inst_1.rs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.rs2 := UInt<1>("h00") - rocc.cmd.bits.inst_1.funct := UInt<1>("h00") - rocc.cmd.valid := UInt<1>("h00") - fcsr_rm := UInt<1>("h00") - time := UInt<1>("h00") - fatc := UInt<1>("h00") - evec := UInt<1>("h00") - ptbr := UInt<1>("h00") - status.ie := UInt<1>("h00") - status.prv := UInt<1>("h00") - status.ie1 := UInt<1>("h00") - status.prv1 := UInt<1>("h00") - status.ie2 := UInt<1>("h00") - status.prv2 := UInt<1>("h00") - status.ie3 := UInt<1>("h00") - status.prv3 := UInt<1>("h00") - status.fs := UInt<1>("h00") - status.xs := UInt<1>("h00") - status.mprv := UInt<1>("h00") - status.vm := UInt<1>("h00") - status.zero1 := UInt<1>("h00") - status.sd_rv32 := UInt<1>("h00") - status.zero2 := UInt<1>("h00") - status.sd := UInt<1>("h00") - eret := UInt<1>("h00") - csr_xcpt := UInt<1>("h00") - csr_stall := UInt<1>("h00") - csr_replay := UInt<1>("h00") - rw.rdata := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.ipi_rep.ready := UInt<1>("h00") - host.ipi_req.bits := UInt<1>("h00") - host.ipi_req.valid := UInt<1>("h00") - host.pcr_rep.bits := UInt<1>("h00") - host.pcr_rep.valid := UInt<1>("h00") - host.pcr_req.ready := UInt<1>("h00") - reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clock, reset - wire T_2310 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_2310.usip := UInt<1>("h00") - T_2310.ssip := UInt<1>("h00") - T_2310.hsip := UInt<1>("h00") - T_2310.msip := UInt<1>("h00") - T_2310.utip := UInt<1>("h00") - T_2310.stip := UInt<1>("h00") - T_2310.htip := UInt<1>("h00") - T_2310.mtip := UInt<1>("h00") - T_2310.usip := UInt<1>("h00") - T_2310.ssip := UInt<1>("h00") - T_2310.hsip := UInt<1>("h00") - T_2310.msip := UInt<1>("h00") - T_2310.utip := UInt<1>("h00") - T_2310.stip := UInt<1>("h00") - T_2310.htip := UInt<1>("h00") - T_2310.mtip := UInt<1>("h00") - reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset - onreset reg_mie := T_2310 - wire T_2363 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_2363.usip := UInt<1>("h00") - T_2363.ssip := UInt<1>("h00") - T_2363.hsip := UInt<1>("h00") - T_2363.msip := UInt<1>("h00") - T_2363.utip := UInt<1>("h00") - T_2363.stip := UInt<1>("h00") - T_2363.htip := UInt<1>("h00") - T_2363.mtip := UInt<1>("h00") - T_2363.usip := UInt<1>("h00") - T_2363.ssip := UInt<1>("h00") - T_2363.hsip := UInt<1>("h00") - T_2363.msip := UInt<1>("h00") - T_2363.utip := UInt<1>("h00") - T_2363.stip := UInt<1>("h00") - T_2363.htip := UInt<1>("h00") - T_2363.mtip := UInt<1>("h00") - reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset - onreset reg_mip := T_2363 - reg reg_mepc : UInt<40>, clock, reset - reg reg_mcause : UInt<64>, clock, reset - reg reg_mbadaddr : UInt<40>, clock, reset - reg reg_mscratch : UInt<64>, clock, reset - reg reg_sepc : UInt<40>, clock, reset - reg reg_scause : UInt<64>, clock, reset - reg reg_sbadaddr : UInt<40>, clock, reset - reg reg_sscratch : UInt<64>, clock, reset - reg reg_stvec : UInt<39>, clock, reset - reg reg_mtimecmp : UInt<64>, clock, reset - reg reg_sptbr : UInt<32>, clock, reset - reg reg_wfi : UInt<1>, clock, reset - onreset reg_wfi := UInt<1>("h00") - reg reg_tohost : UInt<64>, clock, reset - onreset reg_tohost := UInt<64>("h00") - reg reg_fromhost : UInt<64>, clock, reset - onreset reg_fromhost := UInt<64>("h00") - reg reg_stats : UInt<1>, clock, reset - onreset reg_stats := UInt<1>("h00") - reg reg_time : UInt<64>, clock, reset - reg T_2431 : UInt<6>, clock, reset - onreset T_2431 := UInt<6>("h00") - node T_2433 = neq(UInt<1>("h01"), UInt<1>("h00")) - node T_2435 = addw(T_2431, UInt<7>("h01")) - when T_2433 : - node T_2436 = bits(T_2435, 5, 0) - T_2431 := T_2436 - skip - reg T_2438 : UInt<58>, clock, reset - onreset T_2438 := UInt<58>("h00") - node T_2439 = bit(T_2435, 6) - node T_2440 = and(T_2433, T_2439) - when T_2440 : - node T_2442 = addw(T_2438, UInt<1>("h01")) - T_2438 := T_2442 - skip - node T_2443 = cat(T_2438, T_2431) - reg T_2445 : UInt<6>, clock, reset - onreset T_2445 := UInt<6>("h00") - node T_2447 = neq(retire, UInt<1>("h00")) - node T_2449 = addw(T_2445, UInt<7>("h01")) - when T_2447 : - node T_2450 = bits(T_2449, 5, 0) - T_2445 := T_2450 - skip - reg T_2452 : UInt<58>, clock, reset - onreset T_2452 := UInt<58>("h00") - node T_2453 = bit(T_2449, 6) - node T_2454 = and(T_2447, T_2453) - when T_2454 : - node T_2456 = addw(T_2452, UInt<1>("h01")) - T_2452 := T_2456 - skip - node T_2457 = cat(T_2452, T_2445) - reg T_2459 : UInt<6>, clock, reset - onreset T_2459 := UInt<6>("h00") - node T_2461 = neq(uarch_counters[0], UInt<1>("h00")) - node T_2463 = addw(T_2459, UInt<7>("h01")) - when T_2461 : - node T_2464 = bits(T_2463, 5, 0) - T_2459 := T_2464 - skip - reg T_2466 : UInt<58>, clock, reset - onreset T_2466 := UInt<58>("h00") - node T_2467 = bit(T_2463, 6) - node T_2468 = and(T_2461, T_2467) - when T_2468 : - node T_2470 = addw(T_2466, UInt<1>("h01")) - T_2466 := T_2470 - skip - node T_2471 = cat(T_2466, T_2459) - reg T_2473 : UInt<6>, clock, reset - onreset T_2473 := UInt<6>("h00") - node T_2475 = neq(uarch_counters[1], UInt<1>("h00")) - node T_2477 = addw(T_2473, UInt<7>("h01")) - when T_2475 : - node T_2478 = bits(T_2477, 5, 0) - T_2473 := T_2478 - skip - reg T_2480 : UInt<58>, clock, reset - onreset T_2480 := UInt<58>("h00") - node T_2481 = bit(T_2477, 6) - node T_2482 = and(T_2475, T_2481) - when T_2482 : - node T_2484 = addw(T_2480, UInt<1>("h01")) - T_2480 := T_2484 - skip - node T_2485 = cat(T_2480, T_2473) - reg T_2487 : UInt<6>, clock, reset - onreset T_2487 := UInt<6>("h00") - node T_2489 = neq(uarch_counters[2], UInt<1>("h00")) - node T_2491 = addw(T_2487, UInt<7>("h01")) - when T_2489 : - node T_2492 = bits(T_2491, 5, 0) - T_2487 := T_2492 - skip - reg T_2494 : UInt<58>, clock, reset - onreset T_2494 := UInt<58>("h00") - node T_2495 = bit(T_2491, 6) - node T_2496 = and(T_2489, T_2495) - when T_2496 : - node T_2498 = addw(T_2494, UInt<1>("h01")) - T_2494 := T_2498 - skip - node T_2499 = cat(T_2494, T_2487) - reg T_2501 : UInt<6>, clock, reset - onreset T_2501 := UInt<6>("h00") - node T_2503 = neq(uarch_counters[3], UInt<1>("h00")) - node T_2505 = addw(T_2501, UInt<7>("h01")) - when T_2503 : - node T_2506 = bits(T_2505, 5, 0) - T_2501 := T_2506 - skip - reg T_2508 : UInt<58>, clock, reset - onreset T_2508 := UInt<58>("h00") - node T_2509 = bit(T_2505, 6) - node T_2510 = and(T_2503, T_2509) - when T_2510 : - node T_2512 = addw(T_2508, UInt<1>("h01")) - T_2508 := T_2512 - skip - node T_2513 = cat(T_2508, T_2501) - reg T_2515 : UInt<6>, clock, reset - onreset T_2515 := UInt<6>("h00") - node T_2517 = neq(uarch_counters[4], UInt<1>("h00")) - node T_2519 = addw(T_2515, UInt<7>("h01")) - when T_2517 : - node T_2520 = bits(T_2519, 5, 0) - T_2515 := T_2520 - skip - reg T_2522 : UInt<58>, clock, reset - onreset T_2522 := UInt<58>("h00") - node T_2523 = bit(T_2519, 6) - node T_2524 = and(T_2517, T_2523) - when T_2524 : - node T_2526 = addw(T_2522, UInt<1>("h01")) - T_2522 := T_2526 - skip - node T_2527 = cat(T_2522, T_2515) - reg T_2529 : UInt<6>, clock, reset - onreset T_2529 := UInt<6>("h00") - node T_2531 = neq(uarch_counters[5], UInt<1>("h00")) - node T_2533 = addw(T_2529, UInt<7>("h01")) - when T_2531 : - node T_2534 = bits(T_2533, 5, 0) - T_2529 := T_2534 - skip - reg T_2536 : UInt<58>, clock, reset - onreset T_2536 := UInt<58>("h00") - node T_2537 = bit(T_2533, 6) - node T_2538 = and(T_2531, T_2537) - when T_2538 : - node T_2540 = addw(T_2536, UInt<1>("h01")) - T_2536 := T_2540 - skip - node T_2541 = cat(T_2536, T_2529) - reg T_2543 : UInt<6>, clock, reset - onreset T_2543 := UInt<6>("h00") - node T_2545 = neq(uarch_counters[6], UInt<1>("h00")) - node T_2547 = addw(T_2543, UInt<7>("h01")) - when T_2545 : - node T_2548 = bits(T_2547, 5, 0) - T_2543 := T_2548 - skip - reg T_2550 : UInt<58>, clock, reset - onreset T_2550 := UInt<58>("h00") - node T_2551 = bit(T_2547, 6) - node T_2552 = and(T_2545, T_2551) - when T_2552 : - node T_2554 = addw(T_2550, UInt<1>("h01")) - T_2550 := T_2554 - skip - node T_2555 = cat(T_2550, T_2543) - reg T_2557 : UInt<6>, clock, reset - onreset T_2557 := UInt<6>("h00") - node T_2559 = neq(uarch_counters[7], UInt<1>("h00")) - node T_2561 = addw(T_2557, UInt<7>("h01")) - when T_2559 : - node T_2562 = bits(T_2561, 5, 0) - T_2557 := T_2562 - skip - reg T_2564 : UInt<58>, clock, reset - onreset T_2564 := UInt<58>("h00") - node T_2565 = bit(T_2561, 6) - node T_2566 = and(T_2559, T_2565) - when T_2566 : - node T_2568 = addw(T_2564, UInt<1>("h01")) - T_2564 := T_2568 - skip - node T_2569 = cat(T_2564, T_2557) - reg T_2571 : UInt<6>, clock, reset - onreset T_2571 := UInt<6>("h00") - node T_2573 = neq(uarch_counters[8], UInt<1>("h00")) - node T_2575 = addw(T_2571, UInt<7>("h01")) - when T_2573 : - node T_2576 = bits(T_2575, 5, 0) - T_2571 := T_2576 - skip - reg T_2578 : UInt<58>, clock, reset - onreset T_2578 := UInt<58>("h00") - node T_2579 = bit(T_2575, 6) - node T_2580 = and(T_2573, T_2579) - when T_2580 : - node T_2582 = addw(T_2578, UInt<1>("h01")) - T_2578 := T_2582 - skip - node T_2583 = cat(T_2578, T_2571) - reg T_2585 : UInt<6>, clock, reset - onreset T_2585 := UInt<6>("h00") - node T_2587 = neq(uarch_counters[9], UInt<1>("h00")) - node T_2589 = addw(T_2585, UInt<7>("h01")) - when T_2587 : - node T_2590 = bits(T_2589, 5, 0) - T_2585 := T_2590 - skip - reg T_2592 : UInt<58>, clock, reset - onreset T_2592 := UInt<58>("h00") - node T_2593 = bit(T_2589, 6) - node T_2594 = and(T_2587, T_2593) - when T_2594 : - node T_2596 = addw(T_2592, UInt<1>("h01")) - T_2592 := T_2596 - skip - node T_2597 = cat(T_2592, T_2585) - reg T_2599 : UInt<6>, clock, reset - onreset T_2599 := UInt<6>("h00") - node T_2601 = neq(uarch_counters[10], UInt<1>("h00")) - node T_2603 = addw(T_2599, UInt<7>("h01")) - when T_2601 : - node T_2604 = bits(T_2603, 5, 0) - T_2599 := T_2604 - skip - reg T_2606 : UInt<58>, clock, reset - onreset T_2606 := UInt<58>("h00") - node T_2607 = bit(T_2603, 6) - node T_2608 = and(T_2601, T_2607) - when T_2608 : - node T_2610 = addw(T_2606, UInt<1>("h01")) - T_2606 := T_2610 - skip - node T_2611 = cat(T_2606, T_2599) - reg T_2613 : UInt<6>, clock, reset - onreset T_2613 := UInt<6>("h00") - node T_2615 = neq(uarch_counters[11], UInt<1>("h00")) - node T_2617 = addw(T_2613, UInt<7>("h01")) - when T_2615 : - node T_2618 = bits(T_2617, 5, 0) - T_2613 := T_2618 - skip - reg T_2620 : UInt<58>, clock, reset - onreset T_2620 := UInt<58>("h00") - node T_2621 = bit(T_2617, 6) - node T_2622 = and(T_2615, T_2621) - when T_2622 : - node T_2624 = addw(T_2620, UInt<1>("h01")) - T_2620 := T_2624 - skip - node T_2625 = cat(T_2620, T_2613) - reg T_2627 : UInt<6>, clock, reset - onreset T_2627 := UInt<6>("h00") - node T_2629 = neq(uarch_counters[12], UInt<1>("h00")) - node T_2631 = addw(T_2627, UInt<7>("h01")) - when T_2629 : - node T_2632 = bits(T_2631, 5, 0) - T_2627 := T_2632 - skip - reg T_2634 : UInt<58>, clock, reset - onreset T_2634 := UInt<58>("h00") - node T_2635 = bit(T_2631, 6) - node T_2636 = and(T_2629, T_2635) - when T_2636 : - node T_2638 = addw(T_2634, UInt<1>("h01")) - T_2634 := T_2638 - skip - node T_2639 = cat(T_2634, T_2627) - reg T_2641 : UInt<6>, clock, reset - onreset T_2641 := UInt<6>("h00") - node T_2643 = neq(uarch_counters[13], UInt<1>("h00")) - node T_2645 = addw(T_2641, UInt<7>("h01")) - when T_2643 : - node T_2646 = bits(T_2645, 5, 0) - T_2641 := T_2646 - skip - reg T_2648 : UInt<58>, clock, reset - onreset T_2648 := UInt<58>("h00") - node T_2649 = bit(T_2645, 6) - node T_2650 = and(T_2643, T_2649) - when T_2650 : - node T_2652 = addw(T_2648, UInt<1>("h01")) - T_2648 := T_2652 - skip - node T_2653 = cat(T_2648, T_2641) - reg T_2655 : UInt<6>, clock, reset - onreset T_2655 := UInt<6>("h00") - node T_2657 = neq(uarch_counters[14], UInt<1>("h00")) - node T_2659 = addw(T_2655, UInt<7>("h01")) - when T_2657 : - node T_2660 = bits(T_2659, 5, 0) - T_2655 := T_2660 - skip - reg T_2662 : UInt<58>, clock, reset - onreset T_2662 := UInt<58>("h00") - node T_2663 = bit(T_2659, 6) - node T_2664 = and(T_2657, T_2663) - when T_2664 : - node T_2666 = addw(T_2662, UInt<1>("h01")) - T_2662 := T_2666 - skip - node T_2667 = cat(T_2662, T_2655) - reg T_2669 : UInt<6>, clock, reset - onreset T_2669 := UInt<6>("h00") - node T_2671 = neq(uarch_counters[15], UInt<1>("h00")) - node T_2673 = addw(T_2669, UInt<7>("h01")) - when T_2671 : - node T_2674 = bits(T_2673, 5, 0) - T_2669 := T_2674 - skip - reg T_2676 : UInt<58>, clock, reset - onreset T_2676 := UInt<58>("h00") - node T_2677 = bit(T_2673, 6) - node T_2678 = and(T_2671, T_2677) - when T_2678 : - node T_2680 = addw(T_2676, UInt<1>("h01")) - T_2676 := T_2680 - skip - node T_2681 = cat(T_2676, T_2669) - reg reg_fflags : UInt<5>, clock, reset - reg reg_frm : UInt<3>, clock, reset - node irq_rocc = and(UInt<1>("h00"), rocc.interrupt) - interrupt_cause := UInt<1>("h00") - node T_2689 = bit(interrupt_cause, 63) - interrupt := T_2689 - wire some_interrupt_pending : UInt<1> - some_interrupt_pending := UInt<1>("h00") - node T_2693 = and(reg_mie.ssip, reg_mip.ssip) - node T_2694 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_2695 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_2696 = and(T_2695, reg_mstatus.ie) - node T_2697 = or(T_2694, T_2696) - node T_2698 = and(T_2693, T_2697) - when T_2698 : - interrupt_cause := UInt<64>("h08000000000000000") - skip - node T_2700 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_2701 = and(T_2693, T_2700) - when T_2701 : - some_interrupt_pending := UInt<1>("h01") - skip - node T_2704 = and(reg_mie.msip, reg_mip.msip) - node T_2705 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_2706 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_2707 = and(T_2706, reg_mstatus.ie) - node T_2708 = or(T_2705, T_2707) - node T_2709 = and(T_2704, T_2708) - when T_2709 : - interrupt_cause := UInt<64>("h08000000000000000") - skip - node T_2711 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_2712 = and(T_2704, T_2711) - when T_2712 : - some_interrupt_pending := UInt<1>("h01") - skip - node T_2715 = and(reg_mie.stip, reg_mip.stip) - node T_2716 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_2717 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_2718 = and(T_2717, reg_mstatus.ie) - node T_2719 = or(T_2716, T_2718) - node T_2720 = and(T_2715, T_2719) - when T_2720 : - interrupt_cause := UInt<64>("h08000000000000001") - skip - node T_2722 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_2723 = and(T_2715, T_2722) - when T_2723 : - some_interrupt_pending := UInt<1>("h01") - skip - node T_2726 = and(reg_mie.mtip, reg_mip.mtip) - node T_2727 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_2728 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_2729 = and(T_2728, reg_mstatus.ie) - node T_2730 = or(T_2727, T_2729) - node T_2731 = and(T_2726, T_2730) - when T_2731 : - interrupt_cause := UInt<64>("h08000000000000001") - skip - node T_2733 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_2734 = and(T_2726, T_2733) - when T_2734 : - some_interrupt_pending := UInt<1>("h01") - skip - node T_2738 = neq(reg_fromhost, UInt<1>("h00")) - node T_2739 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_2740 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_2741 = and(T_2740, reg_mstatus.ie) - node T_2742 = or(T_2739, T_2741) - node T_2743 = and(T_2738, T_2742) - when T_2743 : - interrupt_cause := UInt<64>("h08000000000000002") - skip - node T_2745 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_2746 = and(T_2738, T_2745) - when T_2746 : - some_interrupt_pending := UInt<1>("h01") - skip - node T_2749 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_2750 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_2751 = and(T_2750, reg_mstatus.ie) - node T_2752 = or(T_2749, T_2751) - node T_2753 = and(irq_rocc, T_2752) - when T_2753 : - interrupt_cause := UInt<64>("h08000000000000003") - skip - node T_2755 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_2756 = and(irq_rocc, T_2755) - when T_2756 : - some_interrupt_pending := UInt<1>("h01") - skip - node system_insn = eq(rw.cmd, UInt<3>("h04")) - node T_2759 = neq(rw.cmd, UInt<3>("h00")) - node T_2761 = eq(system_insn, UInt<1>("h00")) - node cpu_ren = and(T_2759, T_2761) - reg host_pcr_req_valid : UInt<1>, clock, reset - node T_2766 = eq(cpu_ren, UInt<1>("h00")) - node host_pcr_req_fire = and(host_pcr_req_valid, T_2766) - reg host_pcr_rep_valid : UInt<1>, clock, reset - reg host_pcr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clock, reset - node T_2775 = eq(host_pcr_req_valid, UInt<1>("h00")) - node T_2777 = eq(host_pcr_rep_valid, UInt<1>("h00")) - node T_2778 = and(T_2775, T_2777) - host.pcr_req.ready := T_2778 - host.pcr_rep.valid := host_pcr_rep_valid - host.pcr_rep.bits := host_pcr_bits.data - node T_2779 = and(host.pcr_req.ready, host.pcr_req.valid) - when T_2779 : - host_pcr_req_valid := UInt<1>("h01") - host_pcr_bits <> host.pcr_req.bits - skip - when host_pcr_req_fire : - host_pcr_req_valid := UInt<1>("h00") - host_pcr_rep_valid := UInt<1>("h01") - host_pcr_bits.data := rw.rdata - skip - node T_2783 = and(host.pcr_rep.ready, host.pcr_rep.valid) - when T_2783 : - host_pcr_rep_valid := UInt<1>("h00") - skip - host.debug_stats_pcr := reg_stats - node T_2785 = cat(status.sd, status.zero2) - node T_2786 = cat(status.sd_rv32, status.zero1) - node T_2787 = cat(T_2785, T_2786) - node T_2788 = cat(status.vm, status.mprv) - node T_2789 = cat(status.xs, status.fs) - node T_2790 = cat(T_2788, T_2789) - node T_2791 = cat(T_2787, T_2790) - node T_2792 = cat(status.prv3, status.ie3) - node T_2793 = cat(status.prv2, status.ie2) - node T_2794 = cat(T_2792, T_2793) - node T_2795 = cat(status.prv1, status.ie1) - node T_2796 = cat(status.prv, status.ie) - node T_2797 = cat(T_2795, T_2796) - node T_2798 = cat(T_2794, T_2797) - node read_mstatus = cat(T_2791, T_2798) - node T_2800 = cat(reg_frm, reg_fflags) - node T_2806 = cat(reg_mip.mtip, reg_mip.htip) - node T_2807 = cat(reg_mip.stip, reg_mip.utip) - node T_2808 = cat(T_2806, T_2807) - node T_2809 = cat(reg_mip.msip, reg_mip.hsip) - node T_2810 = cat(reg_mip.ssip, reg_mip.usip) - node T_2811 = cat(T_2809, T_2810) - node T_2812 = cat(T_2808, T_2811) - node T_2813 = cat(reg_mie.mtip, reg_mie.htip) - node T_2814 = cat(reg_mie.stip, reg_mie.utip) - node T_2815 = cat(T_2813, T_2814) - node T_2816 = cat(reg_mie.msip, reg_mie.hsip) - node T_2817 = cat(reg_mie.ssip, reg_mie.usip) - node T_2818 = cat(T_2816, T_2817) - node T_2819 = cat(T_2815, T_2818) - node T_2820 = bit(reg_mepc, 39) - node T_2822 = subw(UInt<24>("h00"), T_2820) - node T_2823 = cat(T_2822, reg_mepc) - node T_2824 = bit(reg_mbadaddr, 39) - node T_2826 = subw(UInt<24>("h00"), T_2824) - node T_2827 = cat(T_2826, reg_mbadaddr) - wire T_2854 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_2854.ie := UInt<1>("h00") - T_2854.zero1 := UInt<1>("h00") - T_2854.pie := UInt<1>("h00") - T_2854.ps := UInt<1>("h00") - T_2854.zero2 := UInt<1>("h00") - T_2854.fs := UInt<1>("h00") - T_2854.xs := UInt<1>("h00") - T_2854.mprv := UInt<1>("h00") - T_2854.zero3 := UInt<1>("h00") - T_2854.sd_rv32 := UInt<1>("h00") - T_2854.zero4 := UInt<1>("h00") - T_2854.sd := UInt<1>("h00") - node T_2879 = bits(read_mstatus, 0, 0) - T_2854.ie := T_2879 - node T_2880 = bits(read_mstatus, 2, 1) - T_2854.zero1 := T_2880 - node T_2881 = bits(read_mstatus, 3, 3) - T_2854.pie := T_2881 - node T_2882 = bits(read_mstatus, 4, 4) - T_2854.ps := T_2882 - node T_2883 = bits(read_mstatus, 11, 5) - T_2854.zero2 := T_2883 - node T_2884 = bits(read_mstatus, 13, 12) - T_2854.fs := T_2884 - node T_2885 = bits(read_mstatus, 15, 14) - T_2854.xs := T_2885 - node T_2886 = bits(read_mstatus, 16, 16) - T_2854.mprv := T_2886 - node T_2887 = bits(read_mstatus, 30, 17) - T_2854.zero3 := T_2887 - node T_2888 = bits(read_mstatus, 31, 31) - T_2854.sd_rv32 := T_2888 - node T_2889 = bits(read_mstatus, 62, 32) - T_2854.zero4 := T_2889 - node T_2890 = bits(read_mstatus, 63, 63) - T_2854.sd := T_2890 - wire T_2891 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_2891 <> T_2854 - T_2891.zero1 := UInt<1>("h00") - T_2891.zero2 := UInt<1>("h00") - T_2891.zero3 := UInt<1>("h00") - T_2891.zero4 := UInt<1>("h00") - wire T_2927 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_2927.usip := UInt<1>("h00") - T_2927.ssip := UInt<1>("h00") - T_2927.hsip := UInt<1>("h00") - T_2927.msip := UInt<1>("h00") - T_2927.utip := UInt<1>("h00") - T_2927.stip := UInt<1>("h00") - T_2927.htip := UInt<1>("h00") - T_2927.mtip := UInt<1>("h00") - T_2927.usip := UInt<1>("h00") - T_2927.ssip := UInt<1>("h00") - T_2927.hsip := UInt<1>("h00") - T_2927.msip := UInt<1>("h00") - T_2927.utip := UInt<1>("h00") - T_2927.stip := UInt<1>("h00") - T_2927.htip := UInt<1>("h00") - T_2927.mtip := UInt<1>("h00") - wire T_2952 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_2952 <> T_2927 - T_2952.ssip := reg_mip.ssip - T_2952.stip := reg_mip.stip - wire T_2980 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_2980.usip := UInt<1>("h00") - T_2980.ssip := UInt<1>("h00") - T_2980.hsip := UInt<1>("h00") - T_2980.msip := UInt<1>("h00") - T_2980.utip := UInt<1>("h00") - T_2980.stip := UInt<1>("h00") - T_2980.htip := UInt<1>("h00") - T_2980.mtip := UInt<1>("h00") - T_2980.usip := UInt<1>("h00") - T_2980.ssip := UInt<1>("h00") - T_2980.hsip := UInt<1>("h00") - T_2980.msip := UInt<1>("h00") - T_2980.utip := UInt<1>("h00") - T_2980.stip := UInt<1>("h00") - T_2980.htip := UInt<1>("h00") - T_2980.mtip := UInt<1>("h00") - wire T_3005 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_3005 <> T_2980 - T_3005.ssip := reg_mie.ssip - T_3005.stip := reg_mie.stip - node T_3014 = cat(T_2891.zero4, T_2891.sd_rv32) - node T_3015 = cat(T_2891.sd, T_3014) - node T_3016 = cat(T_2891.mprv, T_2891.xs) - node T_3017 = cat(T_2891.zero3, T_3016) - node T_3018 = cat(T_3015, T_3017) - node T_3019 = cat(T_2891.zero2, T_2891.ps) - node T_3020 = cat(T_2891.fs, T_3019) - node T_3021 = cat(T_2891.zero1, T_2891.ie) - node T_3022 = cat(T_2891.pie, T_3021) - node T_3023 = cat(T_3020, T_3022) - node T_3024 = cat(T_3018, T_3023) - node T_3025 = cat(T_2952.mtip, T_2952.htip) - node T_3026 = cat(T_2952.stip, T_2952.utip) - node T_3027 = cat(T_3025, T_3026) - node T_3028 = cat(T_2952.msip, T_2952.hsip) - node T_3029 = cat(T_2952.ssip, T_2952.usip) - node T_3030 = cat(T_3028, T_3029) - node T_3031 = cat(T_3027, T_3030) - node T_3032 = cat(T_3005.mtip, T_3005.htip) - node T_3033 = cat(T_3005.stip, T_3005.utip) - node T_3034 = cat(T_3032, T_3033) - node T_3035 = cat(T_3005.msip, T_3005.hsip) - node T_3036 = cat(T_3005.ssip, T_3005.usip) - node T_3037 = cat(T_3035, T_3036) - node T_3038 = cat(T_3034, T_3037) - node T_3039 = bit(reg_sbadaddr, 39) - node T_3041 = subw(UInt<24>("h00"), T_3039) - node T_3042 = cat(T_3041, reg_sbadaddr) - node T_3044 = bit(reg_sepc, 39) - node T_3046 = subw(UInt<24>("h00"), T_3044) - node T_3047 = cat(T_3046, reg_sepc) - node T_3048 = bit(reg_stvec, 38) - node T_3050 = subw(UInt<25>("h00"), T_3048) - node T_3051 = cat(T_3050, reg_stvec) - node addr = mux(cpu_ren, rw.addr, host_pcr_bits.addr) - node T_3054 = eq(addr, UInt<1>("h01")) - node T_3056 = eq(addr, UInt<2>("h02")) - node T_3058 = eq(addr, UInt<2>("h03")) - node T_3060 = eq(addr, UInt<12>("h0c00")) - node T_3062 = eq(addr, UInt<12>("h0900")) - node T_3064 = eq(addr, UInt<12>("h0c02")) - node T_3066 = eq(addr, UInt<12>("h0902")) - node T_3068 = eq(addr, UInt<12>("h0c01")) - node T_3070 = eq(addr, UInt<12>("h0901")) - node T_3072 = eq(addr, UInt<12>("h0d01")) - node T_3074 = eq(addr, UInt<12>("h0a01")) - node T_3076 = eq(addr, UInt<11>("h0701")) - node T_3078 = eq(addr, UInt<12>("h0f00")) - node T_3080 = eq(addr, UInt<12>("h0f01")) - node T_3082 = eq(addr, UInt<10>("h0300")) - node T_3084 = eq(addr, UInt<10>("h0302")) - node T_3086 = eq(addr, UInt<11>("h0782")) - node T_3088 = eq(addr, UInt<10>("h0301")) - node T_3090 = eq(addr, UInt<10>("h0344")) - node T_3092 = eq(addr, UInt<10>("h0304")) - node T_3094 = eq(addr, UInt<10>("h0340")) - node T_3096 = eq(addr, UInt<10>("h0341")) - node T_3098 = eq(addr, UInt<10>("h0343")) - node T_3100 = eq(addr, UInt<10>("h0342")) - node T_3102 = eq(addr, UInt<10>("h0321")) - node T_3104 = eq(addr, UInt<12>("h0f10")) - node T_3106 = eq(addr, UInt<11>("h0783")) - node T_3108 = eq(addr, UInt<8>("h0c0")) - node T_3110 = eq(addr, UInt<11>("h0780")) - node T_3112 = eq(addr, UInt<11>("h0781")) - node T_3114 = eq(addr, UInt<9>("h0100")) - node T_3116 = eq(addr, UInt<9>("h0144")) - node T_3118 = eq(addr, UInt<9>("h0104")) - node T_3120 = eq(addr, UInt<9>("h0140")) - node T_3122 = eq(addr, UInt<12>("h0d42")) - node T_3124 = eq(addr, UInt<12>("h0d43")) - node T_3126 = eq(addr, UInt<9>("h0180")) - node T_3128 = eq(addr, UInt<9>("h0181")) - node T_3130 = eq(addr, UInt<9>("h0141")) - node T_3132 = eq(addr, UInt<9>("h0101")) - node T_3134 = eq(addr, UInt<12>("h0cc0")) - node T_3136 = eq(addr, UInt<12>("h0cc1")) - node T_3138 = eq(addr, UInt<12>("h0cc2")) - node T_3140 = eq(addr, UInt<12>("h0cc3")) - node T_3142 = eq(addr, UInt<12>("h0cc4")) - node T_3144 = eq(addr, UInt<12>("h0cc5")) - node T_3146 = eq(addr, UInt<12>("h0cc6")) - node T_3148 = eq(addr, UInt<12>("h0cc7")) - node T_3150 = eq(addr, UInt<12>("h0cc8")) - node T_3152 = eq(addr, UInt<12>("h0cc9")) - node T_3154 = eq(addr, UInt<12>("h0cca")) - node T_3156 = eq(addr, UInt<12>("h0ccb")) - node T_3158 = eq(addr, UInt<12>("h0ccc")) - node T_3160 = eq(addr, UInt<12>("h0ccd")) - node T_3162 = eq(addr, UInt<12>("h0cce")) - node T_3164 = eq(addr, UInt<12>("h0ccf")) - node T_3165 = or(T_3054, T_3056) - node T_3166 = or(T_3165, T_3058) - node T_3167 = or(T_3166, T_3060) - node T_3168 = or(T_3167, T_3062) - node T_3169 = or(T_3168, T_3064) - node T_3170 = or(T_3169, T_3066) - node T_3171 = or(T_3170, T_3068) - node T_3172 = or(T_3171, T_3070) - node T_3173 = or(T_3172, T_3072) - node T_3174 = or(T_3173, T_3074) - node T_3175 = or(T_3174, T_3076) - node T_3176 = or(T_3175, T_3078) - node T_3177 = or(T_3176, T_3080) - node T_3178 = or(T_3177, T_3082) - node T_3179 = or(T_3178, T_3084) - node T_3180 = or(T_3179, T_3086) - node T_3181 = or(T_3180, T_3088) - node T_3182 = or(T_3181, T_3090) - node T_3183 = or(T_3182, T_3092) - node T_3184 = or(T_3183, T_3094) - node T_3185 = or(T_3184, T_3096) - node T_3186 = or(T_3185, T_3098) - node T_3187 = or(T_3186, T_3100) - node T_3188 = or(T_3187, T_3102) - node T_3189 = or(T_3188, T_3104) - node T_3190 = or(T_3189, T_3106) - node T_3191 = or(T_3190, T_3108) - node T_3192 = or(T_3191, T_3110) - node T_3193 = or(T_3192, T_3112) - node T_3194 = or(T_3193, T_3114) - node T_3195 = or(T_3194, T_3116) - node T_3196 = or(T_3195, T_3118) - node T_3197 = or(T_3196, T_3120) - node T_3198 = or(T_3197, T_3122) - node T_3199 = or(T_3198, T_3124) - node T_3200 = or(T_3199, T_3126) - node T_3201 = or(T_3200, T_3128) - node T_3202 = or(T_3201, T_3130) - node T_3203 = or(T_3202, T_3132) - node T_3204 = or(T_3203, T_3134) - node T_3205 = or(T_3204, T_3136) - node T_3206 = or(T_3205, T_3138) - node T_3207 = or(T_3206, T_3140) - node T_3208 = or(T_3207, T_3142) - node T_3209 = or(T_3208, T_3144) - node T_3210 = or(T_3209, T_3146) - node T_3211 = or(T_3210, T_3148) - node T_3212 = or(T_3211, T_3150) - node T_3213 = or(T_3212, T_3152) - node T_3214 = or(T_3213, T_3154) - node T_3215 = or(T_3214, T_3156) - node T_3216 = or(T_3215, T_3158) - node T_3217 = or(T_3216, T_3160) - node T_3218 = or(T_3217, T_3162) - node addr_valid = or(T_3218, T_3164) - node T_3220 = or(T_3054, T_3056) - node fp_csr = or(T_3220, T_3058) - node csr_addr_priv = bits(rw.addr, 9, 8) - node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) - node T_3224 = bits(rw.addr, 11, 10) - node T_3225 = not(T_3224) - node read_only = eq(T_3225, UInt<1>("h00")) - node T_3228 = neq(rw.cmd, UInt<3>("h05")) - node T_3229 = and(cpu_ren, T_3228) - node cpu_wen = and(T_3229, priv_sufficient) - node T_3232 = eq(read_only, UInt<1>("h00")) - node T_3233 = and(cpu_wen, T_3232) - node T_3234 = and(host_pcr_req_fire, host_pcr_bits.rw) - node wen = or(T_3233, T_3234) - node T_3236 = eq(rw.cmd, UInt<3>("h01")) - node T_3237 = eq(rw.cmd, UInt<3>("h03")) - node T_3238 = not(rw.wdata) - node T_3239 = and(rw.rdata, T_3238) - node T_3240 = eq(rw.cmd, UInt<3>("h02")) - node T_3241 = or(rw.rdata, rw.wdata) - node T_3242 = mux(T_3240, T_3241, host_pcr_bits.data) - node T_3243 = mux(T_3237, T_3239, T_3242) - node wdata = mux(T_3236, rw.wdata, T_3243) - node T_3245 = bit(rw.addr, 8) - node T_3247 = eq(T_3245, UInt<1>("h00")) - node T_3248 = bit(rw.addr, 0) - node T_3250 = eq(T_3248, UInt<1>("h00")) - node T_3251 = and(T_3247, T_3250) - node insn_call = and(T_3251, system_insn) - node T_3253 = bit(rw.addr, 8) - node T_3255 = eq(T_3253, UInt<1>("h00")) - node T_3256 = bit(rw.addr, 0) - node T_3257 = and(T_3255, T_3256) - node insn_break = and(T_3257, system_insn) - node T_3259 = bit(rw.addr, 8) - node T_3260 = bit(rw.addr, 1) - node T_3262 = eq(T_3260, UInt<1>("h00")) - node T_3263 = and(T_3259, T_3262) - node T_3264 = bit(rw.addr, 0) - node T_3266 = eq(T_3264, UInt<1>("h00")) - node T_3267 = and(T_3263, T_3266) - node T_3268 = and(T_3267, system_insn) - node insn_ret = and(T_3268, priv_sufficient) - node T_3270 = bit(rw.addr, 8) - node T_3271 = bit(rw.addr, 1) - node T_3273 = eq(T_3271, UInt<1>("h00")) - node T_3274 = and(T_3270, T_3273) - node T_3275 = bit(rw.addr, 0) - node T_3276 = and(T_3274, T_3275) - node T_3277 = and(T_3276, system_insn) - node insn_sfence_vm = and(T_3277, priv_sufficient) - node T_3279 = bit(rw.addr, 2) - node maybe_insn_redirect_trap = and(T_3279, system_insn) - node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) - node T_3282 = bit(rw.addr, 8) - node T_3283 = bit(rw.addr, 1) - node T_3284 = and(T_3282, T_3283) - node T_3285 = bit(rw.addr, 0) - node T_3287 = eq(T_3285, UInt<1>("h00")) - node T_3288 = and(T_3284, T_3287) - node T_3289 = and(T_3288, system_insn) - node insn_wfi = and(T_3289, priv_sufficient) - node T_3291 = and(cpu_wen, read_only) - node T_3293 = eq(priv_sufficient, UInt<1>("h00")) - node T_3295 = eq(addr_valid, UInt<1>("h00")) - node T_3296 = or(T_3293, T_3295) - node T_3298 = neq(status.fs, UInt<1>("h00")) - node T_3300 = eq(T_3298, UInt<1>("h00")) - node T_3301 = and(fp_csr, T_3300) - node T_3302 = or(T_3296, T_3301) - node T_3303 = and(cpu_ren, T_3302) - node T_3304 = or(T_3291, T_3303) - node T_3306 = eq(priv_sufficient, UInt<1>("h00")) - node T_3307 = and(system_insn, T_3306) - node T_3308 = or(T_3304, T_3307) - node T_3309 = or(T_3308, insn_call) - node csr_xcpt_2 = or(T_3309, insn_break) - when insn_wfi : - reg_wfi := UInt<1>("h01") - skip - when some_interrupt_pending : - reg_wfi := UInt<1>("h00") - skip - fatc := insn_sfence_vm - node T_3313 = or(exception, csr_xcpt_2) - node T_3314 = shl(reg_mstatus.prv, 6) - node T_3316 = addw(T_3314, UInt<9>("h0100")) - node T_3317 = bit(reg_stvec, 38) - node T_3318 = cat(T_3317, reg_stvec) - node T_3319 = bit(reg_mstatus.prv, 1) - node T_3320 = mux(T_3319, reg_mepc, reg_sepc) - node T_3321 = mux(maybe_insn_redirect_trap, T_3318, T_3320) - node T_3322 = mux(T_3313, T_3316, T_3321) - evec := T_3322 - ptbr := reg_sptbr - csr_xcpt := csr_xcpt_2 - node T_3323 = or(insn_ret, insn_redirect_trap) - eret := T_3323 - status <> reg_mstatus - node T_3325 = neq(reg_mstatus.fs, UInt<1>("h00")) - node T_3327 = subw(UInt<2>("h00"), T_3325) - status.fs := T_3327 - node T_3329 = neq(reg_mstatus.xs, UInt<1>("h00")) - node T_3331 = subw(UInt<2>("h00"), T_3329) - status.xs := T_3331 - node T_3332 = not(status.fs) - node T_3334 = eq(T_3332, UInt<1>("h00")) - node T_3335 = not(status.xs) - node T_3337 = eq(T_3335, UInt<1>("h00")) - node T_3338 = or(T_3334, T_3337) - status.sd := T_3338 - node T_3339 = or(exception, csr_xcpt_2) - when T_3339 : - reg_mstatus.ie := UInt<1>("h00") - reg_mstatus.prv := UInt<2>("h03") - reg_mstatus.mprv := UInt<1>("h00") - reg_mstatus.prv1 := reg_mstatus.prv - reg_mstatus.ie1 := reg_mstatus.ie - reg_mstatus.prv2 := reg_mstatus.prv1 - reg_mstatus.ie2 := reg_mstatus.ie1 - node T_3343 = not(pc) - node T_3345 = or(T_3343, UInt<2>("h03")) - node T_3346 = not(T_3345) - reg_mepc := T_3346 - reg_mcause := cause - when csr_xcpt_2 : - reg_mcause := UInt<2>("h02") - when insn_break : - reg_mcause := UInt<2>("h03") - skip - when insn_call : - node T_3350 = addw(reg_mstatus.prv, UInt<4>("h08")) - reg_mcause := T_3350 - skip - skip - reg_mbadaddr := pc - node T_3352 = eq(cause, UInt<3>("h05")) - node T_3354 = eq(cause, UInt<3>("h04")) - node T_3355 = or(T_3352, T_3354) - node T_3357 = eq(cause, UInt<3>("h07")) - node T_3358 = or(T_3355, T_3357) - node T_3360 = eq(cause, UInt<3>("h06")) - node T_3361 = or(T_3358, T_3360) - when T_3361 : - node T_3362 = bits(rw.wdata, 63, 39) - node T_3363 = bits(rw.wdata, 38, 0) - node T_3364 = asSInt(T_3363) - node T_3366 = lt(T_3364, asSInt(UInt<1>("h00"))) - node T_3367 = not(T_3362) - node T_3369 = eq(T_3367, UInt<1>("h00")) - node T_3371 = neq(T_3362, UInt<1>("h00")) - node T_3372 = mux(T_3366, T_3369, T_3371) - node T_3373 = cat(T_3372, T_3363) - reg_mbadaddr := T_3373 - skip - skip - when insn_ret : - reg_mstatus.ie := reg_mstatus.ie1 - reg_mstatus.prv := reg_mstatus.prv1 - reg_mstatus.prv1 := reg_mstatus.prv2 - reg_mstatus.ie1 := reg_mstatus.ie2 - reg_mstatus.prv2 := UInt<1>("h00") - reg_mstatus.ie2 := UInt<1>("h01") - skip - when insn_redirect_trap : - reg_mstatus.prv := UInt<1>("h01") - reg_sbadaddr := reg_mbadaddr - reg_scause := reg_mcause - reg_sepc := reg_mepc - skip - node T_3378 = cat(UInt<1>("h00"), insn_redirect_trap) - node T_3379 = addw(insn_ret, T_3378) - node T_3383 = cat(UInt<1>("h00"), csr_replay) - node T_3384 = addw(csr_xcpt_2, T_3383) - node T_3385 = cat(UInt<1>("h00"), T_3384) - node T_3386 = addw(exception, T_3385) - node T_3387 = cat(UInt<1>("h00"), T_3386) - node T_3388 = addw(T_3379, T_3387) - node T_3390 = leq(T_3388, UInt<1>("h01")) - node T_3391 = geq(reg_time, reg_mtimecmp) - when T_3391 : - reg_mip.mtip := UInt<1>("h01") - skip - time := T_2443 - node T_3393 = and(cpu_wen, T_3106) - host.ipi_req.valid := T_3393 - host.ipi_req.bits := rw.wdata - node T_3395 = eq(host.ipi_req.ready, UInt<1>("h00")) - node T_3396 = and(host.ipi_req.valid, T_3395) - csr_replay := T_3396 - csr_stall := reg_wfi - node T_3398 = eq(host_pcr_bits.rw, UInt<1>("h00")) - node T_3399 = and(host_pcr_req_fire, T_3398) - node T_3400 = and(T_3399, T_3110) - when T_3400 : - reg_tohost := UInt<1>("h00") - skip - node T_3403 = mux(T_3054, reg_fflags, UInt<1>("h00")) - node T_3405 = mux(T_3056, reg_frm, UInt<1>("h00")) - node T_3407 = mux(T_3058, T_2800, UInt<1>("h00")) - node T_3409 = mux(T_3060, T_2443, UInt<1>("h00")) - node T_3411 = mux(T_3062, T_2443, UInt<1>("h00")) - node T_3413 = mux(T_3064, T_2457, UInt<1>("h00")) - node T_3415 = mux(T_3066, T_2457, UInt<1>("h00")) - node T_3417 = mux(T_3068, reg_time, UInt<1>("h00")) - node T_3419 = mux(T_3070, reg_time, UInt<1>("h00")) - node T_3421 = mux(T_3072, reg_time, UInt<1>("h00")) - node T_3423 = mux(T_3074, reg_time, UInt<1>("h00")) - node T_3425 = mux(T_3076, reg_time, UInt<1>("h00")) - node T_3427 = mux(T_3078, UInt<64>("h08000000000041129"), UInt<1>("h00")) - node T_3429 = mux(T_3080, UInt<1>("h01"), UInt<1>("h00")) - node T_3431 = mux(T_3082, read_mstatus, UInt<1>("h00")) - node T_3433 = mux(T_3084, UInt<1>("h00"), UInt<1>("h00")) - node T_3435 = mux(T_3086, UInt<1>("h00"), UInt<1>("h00")) - node T_3437 = mux(T_3088, UInt<9>("h0100"), UInt<1>("h00")) - node T_3439 = mux(T_3090, T_2812, UInt<1>("h00")) - node T_3441 = mux(T_3092, T_2819, UInt<1>("h00")) - node T_3443 = mux(T_3094, reg_mscratch, UInt<1>("h00")) - node T_3445 = mux(T_3096, T_2823, UInt<1>("h00")) - node T_3447 = mux(T_3098, T_2827, UInt<1>("h00")) - node T_3449 = mux(T_3100, reg_mcause, UInt<1>("h00")) - node T_3451 = mux(T_3102, reg_mtimecmp, UInt<1>("h00")) - node T_3453 = mux(T_3104, host.id, UInt<1>("h00")) - node T_3455 = mux(T_3106, host.id, UInt<1>("h00")) - node T_3457 = shl(reg_stats, 0) - node T_3458 = mux(T_3108, T_3457, UInt<1>("h00")) - node T_3460 = mux(T_3110, reg_tohost, UInt<1>("h00")) - node T_3462 = mux(T_3112, reg_fromhost, UInt<1>("h00")) - node T_3464 = mux(T_3114, T_3024, UInt<1>("h00")) - node T_3466 = mux(T_3116, T_3031, UInt<1>("h00")) - node T_3468 = mux(T_3118, T_3038, UInt<1>("h00")) - node T_3470 = mux(T_3120, reg_sscratch, UInt<1>("h00")) - node T_3472 = mux(T_3122, reg_scause, UInt<1>("h00")) - node T_3474 = mux(T_3124, T_3042, UInt<1>("h00")) - node T_3476 = mux(T_3126, reg_sptbr, UInt<1>("h00")) - node T_3478 = mux(T_3128, UInt<1>("h00"), UInt<1>("h00")) - node T_3480 = mux(T_3130, T_3047, UInt<1>("h00")) - node T_3482 = mux(T_3132, T_3051, UInt<1>("h00")) - node T_3484 = mux(T_3134, T_2471, UInt<1>("h00")) - node T_3486 = mux(T_3136, T_2485, UInt<1>("h00")) - node T_3488 = mux(T_3138, T_2499, UInt<1>("h00")) - node T_3490 = mux(T_3140, T_2513, UInt<1>("h00")) - node T_3492 = mux(T_3142, T_2527, UInt<1>("h00")) - node T_3494 = mux(T_3144, T_2541, UInt<1>("h00")) - node T_3496 = mux(T_3146, T_2555, UInt<1>("h00")) - node T_3498 = mux(T_3148, T_2569, UInt<1>("h00")) - node T_3500 = mux(T_3150, T_2583, UInt<1>("h00")) - node T_3502 = mux(T_3152, T_2597, UInt<1>("h00")) - node T_3504 = mux(T_3154, T_2611, UInt<1>("h00")) - node T_3506 = mux(T_3156, T_2625, UInt<1>("h00")) - node T_3508 = mux(T_3158, T_2639, UInt<1>("h00")) - node T_3510 = mux(T_3160, T_2653, UInt<1>("h00")) - node T_3512 = mux(T_3162, T_2667, UInt<1>("h00")) - node T_3514 = mux(T_3164, T_2681, UInt<1>("h00")) - node T_3516 = or(T_3403, T_3405) - node T_3517 = or(T_3516, T_3407) - node T_3518 = or(T_3517, T_3409) - node T_3519 = or(T_3518, T_3411) - node T_3520 = or(T_3519, T_3413) - node T_3521 = or(T_3520, T_3415) - node T_3522 = or(T_3521, T_3417) - node T_3523 = or(T_3522, T_3419) - node T_3524 = or(T_3523, T_3421) - node T_3525 = or(T_3524, T_3423) - node T_3526 = or(T_3525, T_3425) - node T_3527 = or(T_3526, T_3427) - node T_3528 = or(T_3527, T_3429) - node T_3529 = or(T_3528, T_3431) - node T_3530 = or(T_3529, T_3433) - node T_3531 = or(T_3530, T_3435) - node T_3532 = or(T_3531, T_3437) - node T_3533 = or(T_3532, T_3439) - node T_3534 = or(T_3533, T_3441) - node T_3535 = or(T_3534, T_3443) - node T_3536 = or(T_3535, T_3445) - node T_3537 = or(T_3536, T_3447) - node T_3538 = or(T_3537, T_3449) - node T_3539 = or(T_3538, T_3451) - node T_3540 = or(T_3539, T_3453) - node T_3541 = or(T_3540, T_3455) - node T_3542 = or(T_3541, T_3458) - node T_3543 = or(T_3542, T_3460) - node T_3544 = or(T_3543, T_3462) - node T_3545 = or(T_3544, T_3464) - node T_3546 = or(T_3545, T_3466) - node T_3547 = or(T_3546, T_3468) - node T_3548 = or(T_3547, T_3470) - node T_3549 = or(T_3548, T_3472) - node T_3550 = or(T_3549, T_3474) - node T_3551 = or(T_3550, T_3476) - node T_3552 = or(T_3551, T_3478) - node T_3553 = or(T_3552, T_3480) - node T_3554 = or(T_3553, T_3482) - node T_3555 = or(T_3554, T_3484) - node T_3556 = or(T_3555, T_3486) - node T_3557 = or(T_3556, T_3488) - node T_3558 = or(T_3557, T_3490) - node T_3559 = or(T_3558, T_3492) - node T_3560 = or(T_3559, T_3494) - node T_3561 = or(T_3560, T_3496) - node T_3562 = or(T_3561, T_3498) - node T_3563 = or(T_3562, T_3500) - node T_3564 = or(T_3563, T_3502) - node T_3565 = or(T_3564, T_3504) - node T_3566 = or(T_3565, T_3506) - node T_3567 = or(T_3566, T_3508) - node T_3568 = or(T_3567, T_3510) - node T_3569 = or(T_3568, T_3512) - node T_3570 = or(T_3569, T_3514) - wire T_3571 : UInt<64> - T_3571 := UInt<1>("h00") - T_3571 := T_3570 - rw.rdata := T_3571 - fcsr_rm := reg_frm - when fcsr_flags.valid : - node T_3573 = or(reg_fflags, fcsr_flags.bits) - reg_fflags := T_3573 - skip - when wen : - when T_3082 : - wire T_3608 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} - T_3608.ie := UInt<1>("h00") - T_3608.prv := UInt<1>("h00") - T_3608.ie1 := UInt<1>("h00") - T_3608.prv1 := UInt<1>("h00") - T_3608.ie2 := UInt<1>("h00") - T_3608.prv2 := UInt<1>("h00") - T_3608.ie3 := UInt<1>("h00") - T_3608.prv3 := UInt<1>("h00") - T_3608.fs := UInt<1>("h00") - T_3608.xs := UInt<1>("h00") - T_3608.mprv := UInt<1>("h00") - T_3608.vm := UInt<1>("h00") - T_3608.zero1 := UInt<1>("h00") - T_3608.sd_rv32 := UInt<1>("h00") - T_3608.zero2 := UInt<1>("h00") - T_3608.sd := UInt<1>("h00") - node T_3641 = bits(wdata, 0, 0) - T_3608.ie := T_3641 - node T_3642 = bits(wdata, 2, 1) - T_3608.prv := T_3642 - node T_3643 = bits(wdata, 3, 3) - T_3608.ie1 := T_3643 - node T_3644 = bits(wdata, 5, 4) - T_3608.prv1 := T_3644 - node T_3645 = bits(wdata, 6, 6) - T_3608.ie2 := T_3645 - node T_3646 = bits(wdata, 8, 7) - T_3608.prv2 := T_3646 - node T_3647 = bits(wdata, 9, 9) - T_3608.ie3 := T_3647 - node T_3648 = bits(wdata, 11, 10) - T_3608.prv3 := T_3648 - node T_3649 = bits(wdata, 13, 12) - T_3608.fs := T_3649 - node T_3650 = bits(wdata, 15, 14) - T_3608.xs := T_3650 - node T_3651 = bits(wdata, 16, 16) - T_3608.mprv := T_3651 - node T_3652 = bits(wdata, 21, 17) - T_3608.vm := T_3652 - node T_3653 = bits(wdata, 30, 22) - T_3608.zero1 := T_3653 - node T_3654 = bits(wdata, 31, 31) - T_3608.sd_rv32 := T_3654 - node T_3655 = bits(wdata, 62, 32) - T_3608.zero2 := T_3655 - node T_3656 = bits(wdata, 63, 63) - T_3608.sd := T_3656 - reg_mstatus.ie := T_3608.ie - reg_mstatus.ie1 := T_3608.ie1 - wire T_3661 : UInt<2>[3] - T_3661[0] := UInt<2>("h03") - T_3661[1] := UInt<1>("h00") - T_3661[2] := UInt<1>("h01") - reg_mstatus.mprv := T_3608.mprv - node T_3666 = eq(T_3661[0], T_3608.prv) - node T_3667 = eq(T_3661[1], T_3608.prv) - node T_3668 = eq(T_3661[2], T_3608.prv) - node T_3670 = or(UInt<1>("h00"), T_3666) - node T_3671 = or(T_3670, T_3667) - node T_3672 = or(T_3671, T_3668) - when T_3672 : - reg_mstatus.prv := T_3608.prv - skip - node T_3673 = eq(T_3661[0], T_3608.prv1) - node T_3674 = eq(T_3661[1], T_3608.prv1) - node T_3675 = eq(T_3661[2], T_3608.prv1) - node T_3677 = or(UInt<1>("h00"), T_3673) - node T_3678 = or(T_3677, T_3674) - node T_3679 = or(T_3678, T_3675) - when T_3679 : - reg_mstatus.prv1 := T_3608.prv1 - skip - node T_3680 = eq(T_3661[0], T_3608.prv2) - node T_3681 = eq(T_3661[1], T_3608.prv2) - node T_3682 = eq(T_3661[2], T_3608.prv2) - node T_3684 = or(UInt<1>("h00"), T_3680) - node T_3685 = or(T_3684, T_3681) - node T_3686 = or(T_3685, T_3682) - when T_3686 : - reg_mstatus.prv2 := T_3608.prv2 - skip - reg_mstatus.ie2 := T_3608.ie2 - node T_3688 = eq(T_3608.vm, UInt<1>("h00")) - when T_3688 : - reg_mstatus.vm := UInt<1>("h00") - skip - node T_3691 = eq(T_3608.vm, UInt<4>("h09")) - when T_3691 : - reg_mstatus.vm := UInt<4>("h09") - skip - reg_mstatus.fs := T_3608.fs - skip - when T_3090 : - wire T_3711 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_3711.usip := UInt<1>("h00") - T_3711.ssip := UInt<1>("h00") - T_3711.hsip := UInt<1>("h00") - T_3711.msip := UInt<1>("h00") - T_3711.utip := UInt<1>("h00") - T_3711.stip := UInt<1>("h00") - T_3711.htip := UInt<1>("h00") - T_3711.mtip := UInt<1>("h00") - node T_3728 = bits(wdata, 0, 0) - T_3711.usip := T_3728 - node T_3729 = bits(wdata, 1, 1) - T_3711.ssip := T_3729 - node T_3730 = bits(wdata, 2, 2) - T_3711.hsip := T_3730 - node T_3731 = bits(wdata, 3, 3) - T_3711.msip := T_3731 - node T_3732 = bits(wdata, 4, 4) - T_3711.utip := T_3732 - node T_3733 = bits(wdata, 5, 5) - T_3711.stip := T_3733 - node T_3734 = bits(wdata, 6, 6) - T_3711.htip := T_3734 - node T_3735 = bits(wdata, 7, 7) - T_3711.mtip := T_3735 - reg_mip.ssip := T_3711.ssip - reg_mip.stip := T_3711.stip - reg_mip.msip := T_3711.msip - skip - when T_3092 : - wire T_3754 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_3754.usip := UInt<1>("h00") - T_3754.ssip := UInt<1>("h00") - T_3754.hsip := UInt<1>("h00") - T_3754.msip := UInt<1>("h00") - T_3754.utip := UInt<1>("h00") - T_3754.stip := UInt<1>("h00") - T_3754.htip := UInt<1>("h00") - T_3754.mtip := UInt<1>("h00") - node T_3771 = bits(wdata, 0, 0) - T_3754.usip := T_3771 - node T_3772 = bits(wdata, 1, 1) - T_3754.ssip := T_3772 - node T_3773 = bits(wdata, 2, 2) - T_3754.hsip := T_3773 - node T_3774 = bits(wdata, 3, 3) - T_3754.msip := T_3774 - node T_3775 = bits(wdata, 4, 4) - T_3754.utip := T_3775 - node T_3776 = bits(wdata, 5, 5) - T_3754.stip := T_3776 - node T_3777 = bits(wdata, 6, 6) - T_3754.htip := T_3777 - node T_3778 = bits(wdata, 7, 7) - T_3754.mtip := T_3778 - reg_mie.ssip := T_3754.ssip - reg_mie.stip := T_3754.stip - reg_mie.msip := T_3754.msip - reg_mie.mtip := T_3754.mtip - skip - when T_3054 : - reg_fflags := wdata - skip - when T_3056 : - reg_frm := wdata - skip - when T_3058 : - reg_fflags := wdata - node T_3779 = shr(wdata, 5) - reg_frm := T_3779 - skip - when T_3096 : - node T_3780 = not(wdata) - node T_3782 = or(T_3780, UInt<2>("h03")) - node T_3783 = not(T_3782) - reg_mepc := T_3783 - skip - when T_3094 : - reg_mscratch := wdata - skip - when T_3100 : - node T_3785 = and(wdata, UInt<64>("h0800000000000001f")) - reg_mcause := T_3785 - skip - when T_3098 : - node T_3786 = bits(wdata, 39, 0) - reg_mbadaddr := T_3786 - skip - when T_3066 : - node T_3787 = bits(wdata, 5, 0) - T_2445 := T_3787 - node T_3788 = bits(wdata, 63, 6) - T_2452 := T_3788 - skip - when T_3102 : - reg_mtimecmp := wdata - reg_mip.mtip := UInt<1>("h00") - skip - when T_3086 : - reg_time := wdata - skip - when T_3112 : - node T_3791 = eq(reg_fromhost, UInt<1>("h00")) - node T_3793 = eq(host_pcr_req_fire, UInt<1>("h00")) - node T_3794 = or(T_3791, T_3793) - when T_3794 : - reg_fromhost := wdata - skip - skip - when T_3110 : - node T_3796 = eq(reg_tohost, UInt<1>("h00")) - node T_3797 = or(T_3796, host_pcr_req_fire) - when T_3797 : - reg_tohost := wdata - skip - skip - when T_3108 : - node T_3798 = bit(wdata, 0) - reg_stats := T_3798 - skip - when T_3114 : - wire T_3825 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_3825.ie := UInt<1>("h00") - T_3825.zero1 := UInt<1>("h00") - T_3825.pie := UInt<1>("h00") - T_3825.ps := UInt<1>("h00") - T_3825.zero2 := UInt<1>("h00") - T_3825.fs := UInt<1>("h00") - T_3825.xs := UInt<1>("h00") - T_3825.mprv := UInt<1>("h00") - T_3825.zero3 := UInt<1>("h00") - T_3825.sd_rv32 := UInt<1>("h00") - T_3825.zero4 := UInt<1>("h00") - T_3825.sd := UInt<1>("h00") - node T_3850 = bits(wdata, 0, 0) - T_3825.ie := T_3850 - node T_3851 = bits(wdata, 2, 1) - T_3825.zero1 := T_3851 - node T_3852 = bits(wdata, 3, 3) - T_3825.pie := T_3852 - node T_3853 = bits(wdata, 4, 4) - T_3825.ps := T_3853 - node T_3854 = bits(wdata, 11, 5) - T_3825.zero2 := T_3854 - node T_3855 = bits(wdata, 13, 12) - T_3825.fs := T_3855 - node T_3856 = bits(wdata, 15, 14) - T_3825.xs := T_3856 - node T_3857 = bits(wdata, 16, 16) - T_3825.mprv := T_3857 - node T_3858 = bits(wdata, 30, 17) - T_3825.zero3 := T_3858 - node T_3859 = bits(wdata, 31, 31) - T_3825.sd_rv32 := T_3859 - node T_3860 = bits(wdata, 62, 32) - T_3825.zero4 := T_3860 - node T_3861 = bits(wdata, 63, 63) - T_3825.sd := T_3861 - reg_mstatus.ie := T_3825.ie - reg_mstatus.ie1 := T_3825.pie - node T_3864 = mux(T_3825.ps, UInt<1>("h01"), UInt<1>("h00")) - reg_mstatus.prv1 := T_3864 - reg_mstatus.mprv := T_3825.mprv - reg_mstatus.fs := T_3825.fs - skip - when T_3116 : - wire T_3883 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_3883.usip := UInt<1>("h00") - T_3883.ssip := UInt<1>("h00") - T_3883.hsip := UInt<1>("h00") - T_3883.msip := UInt<1>("h00") - T_3883.utip := UInt<1>("h00") - T_3883.stip := UInt<1>("h00") - T_3883.htip := UInt<1>("h00") - T_3883.mtip := UInt<1>("h00") - node T_3900 = bits(wdata, 0, 0) - T_3883.usip := T_3900 - node T_3901 = bits(wdata, 1, 1) - T_3883.ssip := T_3901 - node T_3902 = bits(wdata, 2, 2) - T_3883.hsip := T_3902 - node T_3903 = bits(wdata, 3, 3) - T_3883.msip := T_3903 - node T_3904 = bits(wdata, 4, 4) - T_3883.utip := T_3904 - node T_3905 = bits(wdata, 5, 5) - T_3883.stip := T_3905 - node T_3906 = bits(wdata, 6, 6) - T_3883.htip := T_3906 - node T_3907 = bits(wdata, 7, 7) - T_3883.mtip := T_3907 - reg_mip.ssip := T_3883.ssip - skip - when T_3118 : - wire T_3926 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_3926.usip := UInt<1>("h00") - T_3926.ssip := UInt<1>("h00") - T_3926.hsip := UInt<1>("h00") - T_3926.msip := UInt<1>("h00") - T_3926.utip := UInt<1>("h00") - T_3926.stip := UInt<1>("h00") - T_3926.htip := UInt<1>("h00") - T_3926.mtip := UInt<1>("h00") - node T_3943 = bits(wdata, 0, 0) - T_3926.usip := T_3943 - node T_3944 = bits(wdata, 1, 1) - T_3926.ssip := T_3944 - node T_3945 = bits(wdata, 2, 2) - T_3926.hsip := T_3945 - node T_3946 = bits(wdata, 3, 3) - T_3926.msip := T_3946 - node T_3947 = bits(wdata, 4, 4) - T_3926.utip := T_3947 - node T_3948 = bits(wdata, 5, 5) - T_3926.stip := T_3948 - node T_3949 = bits(wdata, 6, 6) - T_3926.htip := T_3949 - node T_3950 = bits(wdata, 7, 7) - T_3926.mtip := T_3950 - reg_mie.ssip := T_3926.ssip - reg_mie.stip := T_3926.stip - skip - when T_3120 : - reg_sscratch := wdata - skip - when T_3126 : - node T_3951 = bits(wdata, 31, 12) - node T_3953 = cat(T_3951, UInt<12>("h00")) - reg_sptbr := T_3953 - skip - when T_3130 : - node T_3954 = not(wdata) - node T_3956 = or(T_3954, UInt<2>("h03")) - node T_3957 = not(T_3956) - reg_sepc := T_3957 - skip - when T_3132 : - node T_3958 = not(wdata) - node T_3960 = or(T_3958, UInt<2>("h03")) - node T_3961 = not(T_3960) - reg_stvec := T_3961 - skip - skip - host.ipi_rep.ready := UInt<1>("h01") - when host.ipi_rep.valid : - reg_mip.msip := UInt<1>("h01") - skip - when reset : - reg_mstatus.zero1 := UInt<1>("h00") - reg_mstatus.zero2 := UInt<1>("h00") - reg_mstatus.ie := UInt<1>("h00") - reg_mstatus.prv := UInt<2>("h03") - reg_mstatus.ie1 := UInt<1>("h00") - reg_mstatus.prv1 := UInt<2>("h03") - reg_mstatus.ie2 := UInt<1>("h00") - reg_mstatus.prv2 := UInt<1>("h00") - reg_mstatus.ie3 := UInt<1>("h00") - reg_mstatus.prv3 := UInt<1>("h00") - reg_mstatus.mprv := UInt<1>("h00") - reg_mstatus.vm := UInt<1>("h00") - reg_mstatus.fs := UInt<1>("h00") - reg_mstatus.xs := UInt<1>("h00") - reg_mstatus.sd_rv32 := UInt<1>("h00") - reg_mstatus.sd := UInt<1>("h00") - skip - - module ALU : - output adder_out : UInt<64> - output out : UInt<64> - input in1 : UInt<64> - input in2 : UInt<64> - input fn : UInt<4> - input dw : UInt<1> - input clock : Clock - input reset : UInt<1> - - adder_out := UInt<1>("h00") - out := UInt<1>("h00") - node T_10 = bit(fn, 3) - node T_12 = subw(UInt<1>("h00"), in2) - node T_13 = mux(T_10, T_12, in2) - node sum = addw(in1, T_13) - node T_15 = bit(fn, 0) - node T_16 = bit(fn, 2) - node T_18 = eq(T_16, UInt<1>("h00")) - node T_20 = eq(sum, UInt<1>("h00")) - node T_21 = bit(in1, 63) - node T_22 = bit(in2, 63) - node T_23 = eq(T_21, T_22) - node T_24 = bit(sum, 63) - node T_25 = bit(fn, 1) - node T_26 = bit(in2, 63) - node T_27 = bit(in1, 63) - node T_28 = mux(T_25, T_26, T_27) - node T_29 = mux(T_23, T_24, T_28) - node T_30 = mux(T_18, T_20, T_29) - node cmp = xor(T_15, T_30) - node T_32 = bit(in2, 5) - node T_35 = and(dw, UInt<1>("h01")) - node T_36 = eq(UInt<1>("h01"), T_35) - node T_37 = and(T_32, T_36) - node T_38 = bits(in2, 4, 0) - node shamt = cat(T_37, T_38) - node T_40 = bit(fn, 3) - node T_41 = bit(in1, 31) - node T_43 = subw(UInt<32>("h00"), T_41) - node shin_hi_32 = mux(T_40, T_43, UInt<32>("h00")) - node T_48 = and(dw, UInt<1>("h01")) - node T_49 = eq(UInt<1>("h01"), T_48) - node T_50 = bits(in1, 63, 32) - node shin_hi = mux(T_49, T_50, shin_hi_32) - node T_52 = bits(in1, 31, 0) - node shin_r = cat(shin_hi, T_52) - node T_54 = eq(fn, UInt<3>("h05")) - node T_55 = eq(fn, UInt<4>("h0b")) - node T_56 = or(T_54, T_55) - node T_59 = shl(UInt<32>("h0ffffffff"), 32) - node T_60 = xor(UInt<64>("h0ffffffffffffffff"), T_59) - node T_61 = shr(shin_r, 32) - node T_62 = and(T_61, T_60) - node T_63 = bits(shin_r, 31, 0) - node T_64 = shl(T_63, 32) - node T_65 = not(T_60) - node T_66 = and(T_64, T_65) - node T_67 = or(T_62, T_66) - node T_68 = bits(T_60, 47, 0) - node T_69 = shl(T_68, 16) - node T_70 = xor(T_60, T_69) - node T_71 = shr(T_67, 16) - node T_72 = and(T_71, T_70) - node T_73 = bits(T_67, 47, 0) - node T_74 = shl(T_73, 16) - node T_75 = not(T_70) - node T_76 = and(T_74, T_75) - node T_77 = or(T_72, T_76) - node T_78 = bits(T_70, 55, 0) - node T_79 = shl(T_78, 8) - node T_80 = xor(T_70, T_79) - node T_81 = shr(T_77, 8) - node T_82 = and(T_81, T_80) - node T_83 = bits(T_77, 55, 0) - node T_84 = shl(T_83, 8) - node T_85 = not(T_80) - node T_86 = and(T_84, T_85) - node T_87 = or(T_82, T_86) - node T_88 = bits(T_80, 59, 0) - node T_89 = shl(T_88, 4) - node T_90 = xor(T_80, T_89) - node T_91 = shr(T_87, 4) - node T_92 = and(T_91, T_90) - node T_93 = bits(T_87, 59, 0) - node T_94 = shl(T_93, 4) - node T_95 = not(T_90) - node T_96 = and(T_94, T_95) - node T_97 = or(T_92, T_96) - node T_98 = bits(T_90, 61, 0) - node T_99 = shl(T_98, 2) - node T_100 = xor(T_90, T_99) - node T_101 = shr(T_97, 2) - node T_102 = and(T_101, T_100) - node T_103 = bits(T_97, 61, 0) - node T_104 = shl(T_103, 2) - node T_105 = not(T_100) - node T_106 = and(T_104, T_105) - node T_107 = or(T_102, T_106) - node T_108 = bits(T_100, 62, 0) - node T_109 = shl(T_108, 1) - node T_110 = xor(T_100, T_109) - node T_111 = shr(T_107, 1) - node T_112 = and(T_111, T_110) - node T_113 = bits(T_107, 62, 0) - node T_114 = shl(T_113, 1) - node T_115 = not(T_110) - node T_116 = and(T_114, T_115) - node T_117 = or(T_112, T_116) - node shin = mux(T_56, shin_r, T_117) - node T_119 = bit(fn, 3) - node T_120 = bit(shin, 63) - node T_121 = and(T_119, T_120) - node T_122 = cat(T_121, shin) - node T_123 = asSInt(T_122) - node T_124 = dshr(T_123, shamt) - node shout_r = bits(T_124, 63, 0) - node T_128 = shl(UInt<32>("h0ffffffff"), 32) - node T_129 = xor(UInt<64>("h0ffffffffffffffff"), T_128) - node T_130 = shr(shout_r, 32) - node T_131 = and(T_130, T_129) - node T_132 = bits(shout_r, 31, 0) - node T_133 = shl(T_132, 32) - node T_134 = not(T_129) - node T_135 = and(T_133, T_134) - node T_136 = or(T_131, T_135) - node T_137 = bits(T_129, 47, 0) - node T_138 = shl(T_137, 16) - node T_139 = xor(T_129, T_138) - node T_140 = shr(T_136, 16) - node T_141 = and(T_140, T_139) - node T_142 = bits(T_136, 47, 0) - node T_143 = shl(T_142, 16) - node T_144 = not(T_139) - node T_145 = and(T_143, T_144) - node T_146 = or(T_141, T_145) - node T_147 = bits(T_139, 55, 0) - node T_148 = shl(T_147, 8) - node T_149 = xor(T_139, T_148) - node T_150 = shr(T_146, 8) - node T_151 = and(T_150, T_149) - node T_152 = bits(T_146, 55, 0) - node T_153 = shl(T_152, 8) - node T_154 = not(T_149) - node T_155 = and(T_153, T_154) - node T_156 = or(T_151, T_155) - node T_157 = bits(T_149, 59, 0) - node T_158 = shl(T_157, 4) - node T_159 = xor(T_149, T_158) - node T_160 = shr(T_156, 4) - node T_161 = and(T_160, T_159) - node T_162 = bits(T_156, 59, 0) - node T_163 = shl(T_162, 4) - node T_164 = not(T_159) - node T_165 = and(T_163, T_164) - node T_166 = or(T_161, T_165) - node T_167 = bits(T_159, 61, 0) - node T_168 = shl(T_167, 2) - node T_169 = xor(T_159, T_168) - node T_170 = shr(T_166, 2) - node T_171 = and(T_170, T_169) - node T_172 = bits(T_166, 61, 0) - node T_173 = shl(T_172, 2) - node T_174 = not(T_169) - node T_175 = and(T_173, T_174) - node T_176 = or(T_171, T_175) - node T_177 = bits(T_169, 62, 0) - node T_178 = shl(T_177, 1) - node T_179 = xor(T_169, T_178) - node T_180 = shr(T_176, 1) - node T_181 = and(T_180, T_179) - node T_182 = bits(T_176, 62, 0) - node T_183 = shl(T_182, 1) - node T_184 = not(T_179) - node T_185 = and(T_183, T_184) - node shout_l = or(T_181, T_185) - node T_187 = eq(fn, UInt<1>("h00")) - node T_188 = eq(fn, UInt<4>("h0a")) - node T_189 = or(T_187, T_188) - node T_190 = eq(fn, UInt<3>("h05")) - node T_191 = eq(fn, UInt<4>("h0b")) - node T_192 = or(T_190, T_191) - node T_193 = eq(fn, UInt<1>("h01")) - node T_194 = eq(fn, UInt<3>("h07")) - node T_195 = and(in1, in2) - node T_196 = eq(fn, UInt<3>("h06")) - node T_197 = or(in1, in2) - node T_198 = eq(fn, UInt<3>("h04")) - node T_199 = xor(in1, in2) - node T_200 = shl(cmp, 0) - node T_201 = mux(T_198, T_199, T_200) - node T_202 = mux(T_196, T_197, T_201) - node T_203 = mux(T_194, T_195, T_202) - node T_204 = mux(T_193, shout_l, T_203) - node T_205 = mux(T_192, shout_r, T_204) - node out64 = mux(T_189, sum, T_205) - node T_209 = and(dw, UInt<1>("h01")) - node T_210 = eq(UInt<1>("h01"), T_209) - node T_211 = bits(out64, 63, 32) - node T_212 = bit(out64, 31) - node T_214 = subw(UInt<32>("h00"), T_212) - node out_hi = mux(T_210, T_211, T_214) - node T_216 = bits(out64, 31, 0) - node T_217 = cat(out_hi, T_216) - out := T_217 - adder_out := sum - - module MulDiv : - output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}} - input kill : UInt<1> - input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}} - input clock : Clock - input reset : UInt<1> - - resp.bits.tag := UInt<1>("h00") - resp.bits.data := UInt<1>("h00") - resp.valid := UInt<1>("h00") - req.ready := UInt<1>("h00") - reg state : UInt, clock, reset - onreset state := UInt<1>("h00") - reg req_1 : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock, reset - reg count : UInt<7>, clock, reset - reg neg_out : UInt<1>, clock, reset - reg isMul : UInt<1>, clock, reset - reg isHi : UInt<1>, clock, reset - reg divisor : UInt<65>, clock, reset - reg remainder : UInt<130>, clock, reset - node T_81 = and(req.bits.fn, UInt<4>("h04")) - node T_83 = eq(T_81, UInt<4>("h00")) - node T_85 = and(req.bits.fn, UInt<4>("h08")) - node T_87 = eq(T_85, UInt<4>("h08")) - node T_89 = or(UInt<1>("h00"), T_83) - node T_90 = or(T_89, T_87) - node T_92 = and(req.bits.fn, UInt<4>("h05")) - node T_94 = eq(T_92, UInt<4>("h01")) - node T_96 = and(req.bits.fn, UInt<4>("h02")) - node T_98 = eq(T_96, UInt<4>("h02")) - node T_100 = or(UInt<1>("h00"), T_94) - node T_101 = or(T_100, T_98) - node T_102 = or(T_101, T_87) - node T_104 = and(req.bits.fn, UInt<4>("h09")) - node T_106 = eq(T_104, UInt<4>("h00")) - node T_108 = and(req.bits.fn, UInt<4>("h03")) - node T_110 = eq(T_108, UInt<4>("h00")) - node T_112 = or(UInt<1>("h00"), T_106) - node T_113 = or(T_112, T_83) - node T_114 = or(T_113, T_110) - node T_116 = or(UInt<1>("h00"), T_106) - node T_117 = or(T_116, T_83) - node cmdMul = bit(T_90, 0) - node cmdHi = bit(T_102, 0) - node lhsSigned = bit(T_114, 0) - node rhsSigned = bit(T_117, 0) - node T_124 = and(req.bits.dw, UInt<1>("h01")) - node T_125 = eq(UInt<1>("h01"), T_124) - node T_126 = bit(req.bits.in1, 63) - node T_127 = bit(req.bits.in1, 31) - node T_128 = mux(T_125, T_126, T_127) - node lhs_sign = and(lhsSigned, T_128) - node T_132 = and(req.bits.dw, UInt<1>("h01")) - node T_133 = eq(UInt<1>("h01"), T_132) - node T_134 = bits(req.bits.in1, 63, 32) - node T_136 = subw(UInt<32>("h00"), lhs_sign) - node T_137 = mux(T_133, T_134, T_136) - node T_138 = bits(req.bits.in1, 31, 0) - node lhs_in = cat(T_137, T_138) - node T_142 = and(req.bits.dw, UInt<1>("h01")) - node T_143 = eq(UInt<1>("h01"), T_142) - node T_144 = bit(req.bits.in2, 63) - node T_145 = bit(req.bits.in2, 31) - node T_146 = mux(T_143, T_144, T_145) - node rhs_sign = and(rhsSigned, T_146) - node T_150 = and(req.bits.dw, UInt<1>("h01")) - node T_151 = eq(UInt<1>("h01"), T_150) - node T_152 = bits(req.bits.in2, 63, 32) - node T_154 = subw(UInt<32>("h00"), rhs_sign) - node T_155 = mux(T_151, T_152, T_154) - node T_156 = bits(req.bits.in2, 31, 0) - node rhs_in = cat(T_155, T_156) - node T_158 = bits(remainder, 128, 64) - node T_159 = bits(divisor, 64, 0) - node subtractor = subw(T_158, T_159) - node less = bit(subtractor, 64) - node T_162 = bits(remainder, 63, 0) - node negated_remainder = subw(UInt<1>("h00"), T_162) - node T_165 = eq(state, UInt<1>("h01")) - when T_165 : - node T_166 = bit(remainder, 63) - node T_167 = or(T_166, isMul) - when T_167 : - remainder := negated_remainder - skip - node T_168 = bit(divisor, 63) - node T_169 = or(T_168, isMul) - when T_169 : - divisor := subtractor - skip - state := UInt<2>("h02") - skip - node T_170 = eq(state, UInt<3>("h04")) - when T_170 : - remainder := negated_remainder - state := UInt<3>("h05") - skip - node T_171 = eq(state, UInt<2>("h03")) - when T_171 : - node T_172 = bits(remainder, 128, 65) - remainder := T_172 - node T_173 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - state := T_173 - skip - node T_174 = eq(state, UInt<2>("h02")) - node T_175 = and(T_174, isMul) - when T_175 : - node T_176 = bits(remainder, 129, 65) - node T_177 = bits(remainder, 63, 0) - node T_178 = cat(T_176, T_177) - node T_179 = bits(T_178, 63, 0) - node T_180 = bits(T_178, 128, 64) - node T_181 = asSInt(T_180) - node T_182 = asSInt(divisor) - node T_183 = bits(T_179, 7, 0) - node T_184 = mul(T_182, T_183) - node T_185 = addw(T_184, T_181) - node T_186 = bits(T_179, 63, 8) - node T_187 = asUInt(T_185) - node T_188 = cat(T_187, T_186) - node T_191 = mul(count, UInt<4>("h08")) - node T_192 = bits(T_191, 5, 0) - node T_193 = dshr(asSInt(UInt<65>("h010000000000000000")), T_192) - node T_194 = bits(T_193, 63, 0) - node T_197 = neq(count, UInt<3>("h07")) - node T_198 = and(UInt<1>("h01"), T_197) - node T_200 = neq(count, UInt<1>("h00")) - node T_201 = and(T_198, T_200) - node T_203 = eq(isHi, UInt<1>("h00")) - node T_204 = and(T_201, T_203) - node T_205 = not(T_194) - node T_206 = and(T_179, T_205) - node T_208 = eq(T_206, UInt<1>("h00")) - node T_209 = and(T_204, T_208) - node T_212 = mul(count, UInt<4>("h08")) - node T_213 = subw(UInt<7>("h040"), T_212) - node T_214 = bits(T_213, 5, 0) - node T_215 = dshr(T_178, T_214) - node T_216 = bits(T_188, 128, 64) - node T_217 = mux(T_209, T_215, T_188) - node T_218 = bits(T_217, 63, 0) - node T_219 = cat(T_216, T_218) - node T_220 = shr(T_219, 64) - node T_222 = bits(T_219, 63, 0) - node T_223 = cat(UInt<1>("h00"), T_222) - node T_224 = cat(T_220, T_223) - remainder := T_224 - node T_226 = addw(count, UInt<1>("h01")) - count := T_226 - node T_228 = eq(count, UInt<3>("h07")) - node T_229 = or(T_209, T_228) - when T_229 : - node T_230 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) - state := T_230 - skip - skip - node T_231 = eq(state, UInt<2>("h02")) - node T_233 = eq(isMul, UInt<1>("h00")) - node T_234 = and(T_231, T_233) - when T_234 : - node T_236 = eq(count, UInt<7>("h040")) - when T_236 : - node T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - node T_238 = mux(isHi, UInt<2>("h03"), T_237) - state := T_238 - skip - node T_240 = addw(count, UInt<1>("h01")) - count := T_240 - node T_241 = bits(remainder, 127, 64) - node T_242 = bits(subtractor, 63, 0) - node T_243 = mux(less, T_241, T_242) - node T_244 = bits(remainder, 63, 0) - node T_246 = eq(less, UInt<1>("h00")) - node T_247 = cat(T_244, T_246) - node T_248 = cat(T_243, T_247) - remainder := T_248 - node T_249 = bits(divisor, 63, 0) - node T_250 = bit(T_249, 63) - node T_252 = bit(T_249, 62) - node T_254 = bit(T_249, 61) - node T_256 = bit(T_249, 60) - node T_258 = bit(T_249, 59) - node T_260 = bit(T_249, 58) - node T_262 = bit(T_249, 57) - node T_264 = bit(T_249, 56) - node T_266 = bit(T_249, 55) - node T_268 = bit(T_249, 54) - node T_270 = bit(T_249, 53) - node T_272 = bit(T_249, 52) - node T_274 = bit(T_249, 51) - node T_276 = bit(T_249, 50) - node T_278 = bit(T_249, 49) - node T_280 = bit(T_249, 48) - node T_282 = bit(T_249, 47) - node T_284 = bit(T_249, 46) - node T_286 = bit(T_249, 45) - node T_288 = bit(T_249, 44) - node T_290 = bit(T_249, 43) - node T_292 = bit(T_249, 42) - node T_294 = bit(T_249, 41) - node T_296 = bit(T_249, 40) - node T_298 = bit(T_249, 39) - node T_300 = bit(T_249, 38) - node T_302 = bit(T_249, 37) - node T_304 = bit(T_249, 36) - node T_306 = bit(T_249, 35) - node T_308 = bit(T_249, 34) - node T_310 = bit(T_249, 33) - node T_312 = bit(T_249, 32) - node T_314 = bit(T_249, 31) - node T_316 = bit(T_249, 30) - node T_318 = bit(T_249, 29) - node T_320 = bit(T_249, 28) - node T_322 = bit(T_249, 27) - node T_324 = bit(T_249, 26) - node T_326 = bit(T_249, 25) - node T_328 = bit(T_249, 24) - node T_330 = bit(T_249, 23) - node T_332 = bit(T_249, 22) - node T_334 = bit(T_249, 21) - node T_336 = bit(T_249, 20) - node T_338 = bit(T_249, 19) - node T_340 = bit(T_249, 18) - node T_342 = bit(T_249, 17) - node T_344 = bit(T_249, 16) - node T_346 = bit(T_249, 15) - node T_348 = bit(T_249, 14) - node T_350 = bit(T_249, 13) - node T_352 = bit(T_249, 12) - node T_354 = bit(T_249, 11) - node T_356 = bit(T_249, 10) - node T_358 = bit(T_249, 9) - node T_360 = bit(T_249, 8) - node T_362 = bit(T_249, 7) - node T_364 = bit(T_249, 6) - node T_366 = bit(T_249, 5) - node T_368 = bit(T_249, 4) - node T_370 = bit(T_249, 3) - node T_372 = bit(T_249, 2) - node T_374 = bit(T_249, 1) - node T_375 = shl(T_374, 0) - node T_376 = mux(T_372, UInt<2>("h02"), T_375) - node T_377 = mux(T_370, UInt<2>("h03"), T_376) - node T_378 = mux(T_368, UInt<3>("h04"), T_377) - node T_379 = mux(T_366, UInt<3>("h05"), T_378) - node T_380 = mux(T_364, UInt<3>("h06"), T_379) - node T_381 = mux(T_362, UInt<3>("h07"), T_380) - node T_382 = mux(T_360, UInt<4>("h08"), T_381) - node T_383 = mux(T_358, UInt<4>("h09"), T_382) - node T_384 = mux(T_356, UInt<4>("h0a"), T_383) - node T_385 = mux(T_354, UInt<4>("h0b"), T_384) - node T_386 = mux(T_352, UInt<4>("h0c"), T_385) - node T_387 = mux(T_350, UInt<4>("h0d"), T_386) - node T_388 = mux(T_348, UInt<4>("h0e"), T_387) - node T_389 = mux(T_346, UInt<4>("h0f"), T_388) - node T_390 = mux(T_344, UInt<5>("h010"), T_389) - node T_391 = mux(T_342, UInt<5>("h011"), T_390) - node T_392 = mux(T_340, UInt<5>("h012"), T_391) - node T_393 = mux(T_338, UInt<5>("h013"), T_392) - node T_394 = mux(T_336, UInt<5>("h014"), T_393) - node T_395 = mux(T_334, UInt<5>("h015"), T_394) - node T_396 = mux(T_332, UInt<5>("h016"), T_395) - node T_397 = mux(T_330, UInt<5>("h017"), T_396) - node T_398 = mux(T_328, UInt<5>("h018"), T_397) - node T_399 = mux(T_326, UInt<5>("h019"), T_398) - node T_400 = mux(T_324, UInt<5>("h01a"), T_399) - node T_401 = mux(T_322, UInt<5>("h01b"), T_400) - node T_402 = mux(T_320, UInt<5>("h01c"), T_401) - node T_403 = mux(T_318, UInt<5>("h01d"), T_402) - node T_404 = mux(T_316, UInt<5>("h01e"), T_403) - node T_405 = mux(T_314, UInt<5>("h01f"), T_404) - node T_406 = mux(T_312, UInt<6>("h020"), T_405) - node T_407 = mux(T_310, UInt<6>("h021"), T_406) - node T_408 = mux(T_308, UInt<6>("h022"), T_407) - node T_409 = mux(T_306, UInt<6>("h023"), T_408) - node T_410 = mux(T_304, UInt<6>("h024"), T_409) - node T_411 = mux(T_302, UInt<6>("h025"), T_410) - node T_412 = mux(T_300, UInt<6>("h026"), T_411) - node T_413 = mux(T_298, UInt<6>("h027"), T_412) - node T_414 = mux(T_296, UInt<6>("h028"), T_413) - node T_415 = mux(T_294, UInt<6>("h029"), T_414) - node T_416 = mux(T_292, UInt<6>("h02a"), T_415) - node T_417 = mux(T_290, UInt<6>("h02b"), T_416) - node T_418 = mux(T_288, UInt<6>("h02c"), T_417) - node T_419 = mux(T_286, UInt<6>("h02d"), T_418) - node T_420 = mux(T_284, UInt<6>("h02e"), T_419) - node T_421 = mux(T_282, UInt<6>("h02f"), T_420) - node T_422 = mux(T_280, UInt<6>("h030"), T_421) - node T_423 = mux(T_278, UInt<6>("h031"), T_422) - node T_424 = mux(T_276, UInt<6>("h032"), T_423) - node T_425 = mux(T_274, UInt<6>("h033"), T_424) - node T_426 = mux(T_272, UInt<6>("h034"), T_425) - node T_427 = mux(T_270, UInt<6>("h035"), T_426) - node T_428 = mux(T_268, UInt<6>("h036"), T_427) - node T_429 = mux(T_266, UInt<6>("h037"), T_428) - node T_430 = mux(T_264, UInt<6>("h038"), T_429) - node T_431 = mux(T_262, UInt<6>("h039"), T_430) - node T_432 = mux(T_260, UInt<6>("h03a"), T_431) - node T_433 = mux(T_258, UInt<6>("h03b"), T_432) - node T_434 = mux(T_256, UInt<6>("h03c"), T_433) - node T_435 = mux(T_254, UInt<6>("h03d"), T_434) - node T_436 = mux(T_252, UInt<6>("h03e"), T_435) - node T_437 = mux(T_250, UInt<6>("h03f"), T_436) - node T_438 = bits(remainder, 63, 0) - node T_439 = bit(T_438, 63) - node T_441 = bit(T_438, 62) - node T_443 = bit(T_438, 61) - node T_445 = bit(T_438, 60) - node T_447 = bit(T_438, 59) - node T_449 = bit(T_438, 58) - node T_451 = bit(T_438, 57) - node T_453 = bit(T_438, 56) - node T_455 = bit(T_438, 55) - node T_457 = bit(T_438, 54) - node T_459 = bit(T_438, 53) - node T_461 = bit(T_438, 52) - node T_463 = bit(T_438, 51) - node T_465 = bit(T_438, 50) - node T_467 = bit(T_438, 49) - node T_469 = bit(T_438, 48) - node T_471 = bit(T_438, 47) - node T_473 = bit(T_438, 46) - node T_475 = bit(T_438, 45) - node T_477 = bit(T_438, 44) - node T_479 = bit(T_438, 43) - node T_481 = bit(T_438, 42) - node T_483 = bit(T_438, 41) - node T_485 = bit(T_438, 40) - node T_487 = bit(T_438, 39) - node T_489 = bit(T_438, 38) - node T_491 = bit(T_438, 37) - node T_493 = bit(T_438, 36) - node T_495 = bit(T_438, 35) - node T_497 = bit(T_438, 34) - node T_499 = bit(T_438, 33) - node T_501 = bit(T_438, 32) - node T_503 = bit(T_438, 31) - node T_505 = bit(T_438, 30) - node T_507 = bit(T_438, 29) - node T_509 = bit(T_438, 28) - node T_511 = bit(T_438, 27) - node T_513 = bit(T_438, 26) - node T_515 = bit(T_438, 25) - node T_517 = bit(T_438, 24) - node T_519 = bit(T_438, 23) - node T_521 = bit(T_438, 22) - node T_523 = bit(T_438, 21) - node T_525 = bit(T_438, 20) - node T_527 = bit(T_438, 19) - node T_529 = bit(T_438, 18) - node T_531 = bit(T_438, 17) - node T_533 = bit(T_438, 16) - node T_535 = bit(T_438, 15) - node T_537 = bit(T_438, 14) - node T_539 = bit(T_438, 13) - node T_541 = bit(T_438, 12) - node T_543 = bit(T_438, 11) - node T_545 = bit(T_438, 10) - node T_547 = bit(T_438, 9) - node T_549 = bit(T_438, 8) - node T_551 = bit(T_438, 7) - node T_553 = bit(T_438, 6) - node T_555 = bit(T_438, 5) - node T_557 = bit(T_438, 4) - node T_559 = bit(T_438, 3) - node T_561 = bit(T_438, 2) - node T_563 = bit(T_438, 1) - node T_564 = shl(T_563, 0) - node T_565 = mux(T_561, UInt<2>("h02"), T_564) - node T_566 = mux(T_559, UInt<2>("h03"), T_565) - node T_567 = mux(T_557, UInt<3>("h04"), T_566) - node T_568 = mux(T_555, UInt<3>("h05"), T_567) - node T_569 = mux(T_553, UInt<3>("h06"), T_568) - node T_570 = mux(T_551, UInt<3>("h07"), T_569) - node T_571 = mux(T_549, UInt<4>("h08"), T_570) - node T_572 = mux(T_547, UInt<4>("h09"), T_571) - node T_573 = mux(T_545, UInt<4>("h0a"), T_572) - node T_574 = mux(T_543, UInt<4>("h0b"), T_573) - node T_575 = mux(T_541, UInt<4>("h0c"), T_574) - node T_576 = mux(T_539, UInt<4>("h0d"), T_575) - node T_577 = mux(T_537, UInt<4>("h0e"), T_576) - node T_578 = mux(T_535, UInt<4>("h0f"), T_577) - node T_579 = mux(T_533, UInt<5>("h010"), T_578) - node T_580 = mux(T_531, UInt<5>("h011"), T_579) - node T_581 = mux(T_529, UInt<5>("h012"), T_580) - node T_582 = mux(T_527, UInt<5>("h013"), T_581) - node T_583 = mux(T_525, UInt<5>("h014"), T_582) - node T_584 = mux(T_523, UInt<5>("h015"), T_583) - node T_585 = mux(T_521, UInt<5>("h016"), T_584) - node T_586 = mux(T_519, UInt<5>("h017"), T_585) - node T_587 = mux(T_517, UInt<5>("h018"), T_586) - node T_588 = mux(T_515, UInt<5>("h019"), T_587) - node T_589 = mux(T_513, UInt<5>("h01a"), T_588) - node T_590 = mux(T_511, UInt<5>("h01b"), T_589) - node T_591 = mux(T_509, UInt<5>("h01c"), T_590) - node T_592 = mux(T_507, UInt<5>("h01d"), T_591) - node T_593 = mux(T_505, UInt<5>("h01e"), T_592) - node T_594 = mux(T_503, UInt<5>("h01f"), T_593) - node T_595 = mux(T_501, UInt<6>("h020"), T_594) - node T_596 = mux(T_499, UInt<6>("h021"), T_595) - node T_597 = mux(T_497, UInt<6>("h022"), T_596) - node T_598 = mux(T_495, UInt<6>("h023"), T_597) - node T_599 = mux(T_493, UInt<6>("h024"), T_598) - node T_600 = mux(T_491, UInt<6>("h025"), T_599) - node T_601 = mux(T_489, UInt<6>("h026"), T_600) - node T_602 = mux(T_487, UInt<6>("h027"), T_601) - node T_603 = mux(T_485, UInt<6>("h028"), T_602) - node T_604 = mux(T_483, UInt<6>("h029"), T_603) - node T_605 = mux(T_481, UInt<6>("h02a"), T_604) - node T_606 = mux(T_479, UInt<6>("h02b"), T_605) - node T_607 = mux(T_477, UInt<6>("h02c"), T_606) - node T_608 = mux(T_475, UInt<6>("h02d"), T_607) - node T_609 = mux(T_473, UInt<6>("h02e"), T_608) - node T_610 = mux(T_471, UInt<6>("h02f"), T_609) - node T_611 = mux(T_469, UInt<6>("h030"), T_610) - node T_612 = mux(T_467, UInt<6>("h031"), T_611) - node T_613 = mux(T_465, UInt<6>("h032"), T_612) - node T_614 = mux(T_463, UInt<6>("h033"), T_613) - node T_615 = mux(T_461, UInt<6>("h034"), T_614) - node T_616 = mux(T_459, UInt<6>("h035"), T_615) - node T_617 = mux(T_457, UInt<6>("h036"), T_616) - node T_618 = mux(T_455, UInt<6>("h037"), T_617) - node T_619 = mux(T_453, UInt<6>("h038"), T_618) - node T_620 = mux(T_451, UInt<6>("h039"), T_619) - node T_621 = mux(T_449, UInt<6>("h03a"), T_620) - node T_622 = mux(T_447, UInt<6>("h03b"), T_621) - node T_623 = mux(T_445, UInt<6>("h03c"), T_622) - node T_624 = mux(T_443, UInt<6>("h03d"), T_623) - node T_625 = mux(T_441, UInt<6>("h03e"), T_624) - node T_626 = mux(T_439, UInt<6>("h03f"), T_625) - node T_628 = addw(UInt<6>("h03f"), T_437) - node T_629 = subw(T_628, T_626) - node T_630 = gt(T_437, T_626) - node T_632 = eq(count, UInt<1>("h00")) - node T_633 = and(T_632, less) - node T_635 = gt(T_629, UInt<1>("h00")) - node T_636 = or(T_635, T_630) - node T_637 = and(T_633, T_636) - node T_639 = and(UInt<1>("h01"), T_637) - when T_639 : - node T_641 = bits(T_629, 5, 0) - node T_642 = mux(T_630, UInt<6>("h03f"), T_641) - node T_643 = bits(remainder, 63, 0) - node T_644 = dshl(T_643, T_642) - remainder := T_644 - count := T_642 - skip - node T_646 = eq(count, UInt<1>("h00")) - node T_648 = eq(less, UInt<1>("h00")) - node T_649 = and(T_646, T_648) - node T_651 = eq(isHi, UInt<1>("h00")) - node T_652 = and(T_649, T_651) - when T_652 : - neg_out := UInt<1>("h00") - skip - skip - node T_654 = and(resp.ready, resp.valid) - node T_655 = or(T_654, kill) - when T_655 : - state := UInt<1>("h00") - skip - node T_656 = and(req.ready, req.valid) - when T_656 : - node T_658 = eq(cmdMul, UInt<1>("h00")) - node T_659 = and(rhs_sign, T_658) - node T_660 = or(lhs_sign, T_659) - node T_661 = mux(T_660, UInt<1>("h01"), UInt<2>("h02")) - state := T_661 - isMul := cmdMul - isHi := cmdHi - count := UInt<1>("h00") - node T_664 = eq(cmdMul, UInt<1>("h00")) - node T_665 = neq(lhs_sign, rhs_sign) - node T_666 = mux(cmdHi, lhs_sign, T_665) - node T_667 = and(T_664, T_666) - neg_out := T_667 - node T_668 = cat(rhs_sign, rhs_in) - divisor := T_668 - remainder := lhs_in - req_1 <> req.bits - skip - resp.bits <> req_1 - node T_671 = and(req_1.dw, UInt<1>("h01")) - node T_672 = eq(UInt<1>("h00"), T_671) - node T_673 = bit(remainder, 31) - node T_675 = subw(UInt<32>("h00"), T_673) - node T_676 = bits(remainder, 31, 0) - node T_677 = cat(T_675, T_676) - node T_678 = bits(remainder, 63, 0) - node T_679 = mux(T_672, T_677, T_678) - resp.bits.data := T_679 - node T_680 = eq(state, UInt<3>("h05")) - resp.valid := T_680 - node T_681 = eq(state, UInt<1>("h00")) - req.ready := T_681 - - module Rocket : - input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst_1 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>} - input fpu : {flip inst_1 : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>} - input ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}} - output dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} - output imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>} - output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - rocc.exception := UInt<1>("h00") - rocc.pptw.invalidate := UInt<1>("h00") - rocc.pptw.status.ie := UInt<1>("h00") - rocc.pptw.status.prv := UInt<1>("h00") - rocc.pptw.status.ie1 := UInt<1>("h00") - rocc.pptw.status.prv1 := UInt<1>("h00") - rocc.pptw.status.ie2 := UInt<1>("h00") - rocc.pptw.status.prv2 := UInt<1>("h00") - rocc.pptw.status.ie3 := UInt<1>("h00") - rocc.pptw.status.prv3 := UInt<1>("h00") - rocc.pptw.status.fs := UInt<1>("h00") - rocc.pptw.status.xs := UInt<1>("h00") - rocc.pptw.status.mprv := UInt<1>("h00") - rocc.pptw.status.vm := UInt<1>("h00") - rocc.pptw.status.zero1 := UInt<1>("h00") - rocc.pptw.status.sd_rv32 := UInt<1>("h00") - rocc.pptw.status.zero2 := UInt<1>("h00") - rocc.pptw.status.sd := UInt<1>("h00") - rocc.pptw.resp.bits.pte.v := UInt<1>("h00") - rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.pptw.resp.bits.pte.r := UInt<1>("h00") - rocc.pptw.resp.bits.pte.d := UInt<1>("h00") - rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.pptw.resp.bits.error := UInt<1>("h00") - rocc.pptw.resp.valid := UInt<1>("h00") - rocc.pptw.req.ready := UInt<1>("h00") - rocc.dptw.invalidate := UInt<1>("h00") - rocc.dptw.status.ie := UInt<1>("h00") - rocc.dptw.status.prv := UInt<1>("h00") - rocc.dptw.status.ie1 := UInt<1>("h00") - rocc.dptw.status.prv1 := UInt<1>("h00") - rocc.dptw.status.ie2 := UInt<1>("h00") - rocc.dptw.status.prv2 := UInt<1>("h00") - rocc.dptw.status.ie3 := UInt<1>("h00") - rocc.dptw.status.prv3 := UInt<1>("h00") - rocc.dptw.status.fs := UInt<1>("h00") - rocc.dptw.status.xs := UInt<1>("h00") - rocc.dptw.status.mprv := UInt<1>("h00") - rocc.dptw.status.vm := UInt<1>("h00") - rocc.dptw.status.zero1 := UInt<1>("h00") - rocc.dptw.status.sd_rv32 := UInt<1>("h00") - rocc.dptw.status.zero2 := UInt<1>("h00") - rocc.dptw.status.sd := UInt<1>("h00") - rocc.dptw.resp.bits.pte.v := UInt<1>("h00") - rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.dptw.resp.bits.pte.r := UInt<1>("h00") - rocc.dptw.resp.bits.pte.d := UInt<1>("h00") - rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.dptw.resp.bits.error := UInt<1>("h00") - rocc.dptw.resp.valid := UInt<1>("h00") - rocc.dptw.req.ready := UInt<1>("h00") - rocc.iptw.invalidate := UInt<1>("h00") - rocc.iptw.status.ie := UInt<1>("h00") - rocc.iptw.status.prv := UInt<1>("h00") - rocc.iptw.status.ie1 := UInt<1>("h00") - rocc.iptw.status.prv1 := UInt<1>("h00") - rocc.iptw.status.ie2 := UInt<1>("h00") - rocc.iptw.status.prv2 := UInt<1>("h00") - rocc.iptw.status.ie3 := UInt<1>("h00") - rocc.iptw.status.prv3 := UInt<1>("h00") - rocc.iptw.status.fs := UInt<1>("h00") - rocc.iptw.status.xs := UInt<1>("h00") - rocc.iptw.status.mprv := UInt<1>("h00") - rocc.iptw.status.vm := UInt<1>("h00") - rocc.iptw.status.zero1 := UInt<1>("h00") - rocc.iptw.status.sd_rv32 := UInt<1>("h00") - rocc.iptw.status.zero2 := UInt<1>("h00") - rocc.iptw.status.sd := UInt<1>("h00") - rocc.iptw.resp.bits.pte.v := UInt<1>("h00") - rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") - rocc.iptw.resp.bits.pte.r := UInt<1>("h00") - rocc.iptw.resp.bits.pte.d := UInt<1>("h00") - rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") - rocc.iptw.resp.bits.error := UInt<1>("h00") - rocc.iptw.resp.valid := UInt<1>("h00") - rocc.iptw.req.ready := UInt<1>("h00") - rocc.dmem.grant.bits.g_type := UInt<1>("h00") - rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") - rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") - rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") - rocc.dmem.grant.bits.data := UInt<1>("h00") - rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") - rocc.dmem.grant.valid := UInt<1>("h00") - rocc.dmem.acquire.ready := UInt<1>("h00") - rocc.imem.grant.bits.g_type := UInt<1>("h00") - rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") - rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") - rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") - rocc.imem.grant.bits.data := UInt<1>("h00") - rocc.imem.grant.bits.addr_beat := UInt<1>("h00") - rocc.imem.grant.valid := UInt<1>("h00") - rocc.imem.acquire.ready := UInt<1>("h00") - rocc.s := UInt<1>("h00") - rocc.mem_1.ordered := UInt<1>("h00") - rocc.mem_1.xcpt.pf.st := UInt<1>("h00") - rocc.mem_1.xcpt.pf.ld := UInt<1>("h00") - rocc.mem_1.xcpt.ma.st := UInt<1>("h00") - rocc.mem_1.xcpt.ma.ld := UInt<1>("h00") - rocc.mem_1.replay_next.bits := UInt<1>("h00") - rocc.mem_1.replay_next.valid := UInt<1>("h00") - rocc.mem_1.resp.bits.store_data := UInt<1>("h00") - rocc.mem_1.resp.bits.data_subword := UInt<1>("h00") - rocc.mem_1.resp.bits.has_data := UInt<1>("h00") - rocc.mem_1.resp.bits.replay := UInt<1>("h00") - rocc.mem_1.resp.bits.nack := UInt<1>("h00") - rocc.mem_1.resp.bits.data := UInt<1>("h00") - rocc.mem_1.resp.bits.typ := UInt<1>("h00") - rocc.mem_1.resp.bits.cmd := UInt<1>("h00") - rocc.mem_1.resp.bits.tag := UInt<1>("h00") - rocc.mem_1.resp.bits.addr := UInt<1>("h00") - rocc.mem_1.resp.valid := UInt<1>("h00") - rocc.mem_1.req.ready := UInt<1>("h00") - rocc.resp.ready := UInt<1>("h00") - rocc.cmd.bits.rs2 := UInt<1>("h00") - rocc.cmd.bits.rs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.opcode := UInt<1>("h00") - rocc.cmd.bits.inst_1.rd := UInt<1>("h00") - rocc.cmd.bits.inst_1.xs2 := UInt<1>("h00") - rocc.cmd.bits.inst_1.xs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.xd := UInt<1>("h00") - rocc.cmd.bits.inst_1.rs1 := UInt<1>("h00") - rocc.cmd.bits.inst_1.rs2 := UInt<1>("h00") - rocc.cmd.bits.inst_1.funct := UInt<1>("h00") - rocc.cmd.valid := UInt<1>("h00") - fpu.killm := UInt<1>("h00") - fpu.killx := UInt<1>("h00") - fpu.valid := UInt<1>("h00") - fpu.dmem_resp_data := UInt<1>("h00") - fpu.dmem_resp_tag := UInt<1>("h00") - fpu.dmem_resp_type := UInt<1>("h00") - fpu.dmem_resp_val := UInt<1>("h00") - fpu.fcsr_rm := UInt<1>("h00") - fpu.fromint_data := UInt<1>("h00") - fpu.inst_1 := UInt<1>("h00") - ptw.status.ie := UInt<1>("h00") - ptw.status.prv := UInt<1>("h00") - ptw.status.ie1 := UInt<1>("h00") - ptw.status.prv1 := UInt<1>("h00") - ptw.status.ie2 := UInt<1>("h00") - ptw.status.prv2 := UInt<1>("h00") - ptw.status.ie3 := UInt<1>("h00") - ptw.status.prv3 := UInt<1>("h00") - ptw.status.fs := UInt<1>("h00") - ptw.status.xs := UInt<1>("h00") - ptw.status.mprv := UInt<1>("h00") - ptw.status.vm := UInt<1>("h00") - ptw.status.zero1 := UInt<1>("h00") - ptw.status.sd_rv32 := UInt<1>("h00") - ptw.status.zero2 := UInt<1>("h00") - ptw.status.sd := UInt<1>("h00") - ptw.invalidate := UInt<1>("h00") - ptw.ptbr := UInt<1>("h00") - dmem.invalidate_lr := UInt<1>("h00") - dmem.req.bits.data := UInt<1>("h00") - dmem.req.bits.phys := UInt<1>("h00") - dmem.req.bits.kill := UInt<1>("h00") - dmem.req.bits.typ := UInt<1>("h00") - dmem.req.bits.cmd := UInt<1>("h00") - dmem.req.bits.tag := UInt<1>("h00") - dmem.req.bits.addr := UInt<1>("h00") - dmem.req.valid := UInt<1>("h00") - imem.invalidate := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.entry := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.target := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.mask := UInt<1>("h00") - imem.ras_update.bits.prediction.bits.taken := UInt<1>("h00") - imem.ras_update.bits.prediction.valid := UInt<1>("h00") - imem.ras_update.bits.returnAddr := UInt<1>("h00") - imem.ras_update.bits.isReturn := UInt<1>("h00") - imem.ras_update.bits.isCall := UInt<1>("h00") - imem.ras_update.valid := UInt<1>("h00") - imem.bht_update.bits.mispredict := UInt<1>("h00") - imem.bht_update.bits.taken := UInt<1>("h00") - imem.bht_update.bits.pc := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.entry := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.target := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.mask := UInt<1>("h00") - imem.bht_update.bits.prediction.bits.taken := UInt<1>("h00") - imem.bht_update.bits.prediction.valid := UInt<1>("h00") - imem.bht_update.valid := UInt<1>("h00") - imem.btb_update.bits.br_pc := UInt<1>("h00") - imem.btb_update.bits.isReturn := UInt<1>("h00") - imem.btb_update.bits.isJump := UInt<1>("h00") - imem.btb_update.bits.taken := UInt<1>("h00") - imem.btb_update.bits.target := UInt<1>("h00") - imem.btb_update.bits.pc := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.entry := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.target := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.mask := UInt<1>("h00") - imem.btb_update.bits.prediction.bits.taken := UInt<1>("h00") - imem.btb_update.bits.prediction.valid := UInt<1>("h00") - imem.btb_update.valid := UInt<1>("h00") - imem.resp.ready := UInt<1>("h00") - imem.req.bits.pc := UInt<1>("h00") - imem.req.valid := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.ipi_rep.ready := UInt<1>("h00") - host.ipi_req.bits := UInt<1>("h00") - host.ipi_req.valid := UInt<1>("h00") - host.pcr_rep.bits := UInt<1>("h00") - host.pcr_rep.valid := UInt<1>("h00") - host.pcr_req.ready := UInt<1>("h00") - reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset - reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset - reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset - reg ex_reg_xcpt_interrupt : UInt<1>, clock, reset - reg ex_reg_valid : UInt<1>, clock, reset - reg ex_reg_btb_hit : UInt<1>, clock, reset - reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset - reg ex_reg_xcpt : UInt<1>, clock, reset - reg ex_reg_flush_pipe : UInt<1>, clock, reset - reg ex_reg_load_use : UInt<1>, clock, reset - reg ex_reg_cause : UInt, clock, reset - reg ex_reg_pc : UInt, clock, reset - reg ex_reg_inst : UInt, clock, reset - reg mem_reg_xcpt_interrupt : UInt<1>, clock, reset - reg mem_reg_valid : UInt<1>, clock, reset - reg mem_reg_btb_hit : UInt<1>, clock, reset - reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset - reg mem_reg_xcpt : UInt<1>, clock, reset - reg mem_reg_replay : UInt<1>, clock, reset - reg mem_reg_flush_pipe : UInt<1>, clock, reset - reg mem_reg_cause : UInt, clock, reset - reg mem_reg_slow_bypass : UInt<1>, clock, reset - reg mem_reg_pc : UInt, clock, reset - reg mem_reg_inst : UInt, clock, reset - reg mem_reg_wdata : UInt, clock, reset - reg mem_reg_rs2 : UInt, clock, reset - wire take_pc_mem : UInt<1> - take_pc_mem := UInt<1>("h00") - reg wb_reg_valid : UInt<1>, clock, reset - reg wb_reg_xcpt : UInt<1>, clock, reset - reg wb_reg_replay : UInt<1>, clock, reset - reg wb_reg_cause : UInt, clock, reset - reg wb_reg_rocc_pending : UInt<1>, clock, reset - onreset wb_reg_rocc_pending := UInt<1>("h00") - reg wb_reg_pc : UInt, clock, reset - reg wb_reg_inst : UInt, clock, reset - reg wb_reg_wdata : UInt, clock, reset - reg wb_reg_rs2 : UInt, clock, reset - wire take_pc_wb : UInt<1> - take_pc_wb := UInt<1>("h00") - node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) - wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} - id_ctrl.amo := UInt<1>("h00") - id_ctrl.fence := UInt<1>("h00") - id_ctrl.fence_i := UInt<1>("h00") - id_ctrl.csr := UInt<1>("h00") - id_ctrl.wxd := UInt<1>("h00") - id_ctrl.div := UInt<1>("h00") - id_ctrl.wfd := UInt<1>("h00") - id_ctrl.rfs3 := UInt<1>("h00") - id_ctrl.rfs2 := UInt<1>("h00") - id_ctrl.rfs1 := UInt<1>("h00") - id_ctrl.mem_type := UInt<1>("h00") - id_ctrl.mem_cmd := UInt<1>("h00") - id_ctrl.mem_1 := UInt<1>("h00") - id_ctrl.alu_fn := UInt<1>("h00") - id_ctrl.alu_dw := UInt<1>("h00") - id_ctrl.sel_imm := UInt<1>("h00") - id_ctrl.sel_alu1 := UInt<1>("h00") - id_ctrl.sel_alu2 := UInt<1>("h00") - id_ctrl.rxs1 := UInt<1>("h00") - id_ctrl.rxs2 := UInt<1>("h00") - id_ctrl.jalr := UInt<1>("h00") - id_ctrl.jal := UInt<1>("h00") - id_ctrl.branch := UInt<1>("h00") - id_ctrl.rocc := UInt<1>("h00") - id_ctrl.fp := UInt<1>("h00") - id_ctrl.legal := UInt<1>("h00") - node T_3272 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_3274 = eq(T_3272, UInt<32>("h03")) - node T_3276 = and(imem.resp.bits.data[0], UInt<32>("h0106f")) - node T_3278 = eq(T_3276, UInt<32>("h03")) - node T_3280 = and(imem.resp.bits.data[0], UInt<32>("h0607f")) - node T_3282 = eq(T_3280, UInt<32>("h0f")) - node T_3284 = and(imem.resp.bits.data[0], UInt<32>("h07077")) - node T_3286 = eq(T_3284, UInt<32>("h013")) - node T_3288 = and(imem.resp.bits.data[0], UInt<32>("h05f")) - node T_3290 = eq(T_3288, UInt<32>("h017")) - node T_3292 = and(imem.resp.bits.data[0], UInt<32>("h0fc00007f")) - node T_3294 = eq(T_3292, UInt<32>("h033")) - node T_3296 = and(imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_3298 = eq(T_3296, UInt<32>("h033")) - node T_3300 = and(imem.resp.bits.data[0], UInt<32>("h04000073")) - node T_3302 = eq(T_3300, UInt<32>("h043")) - node T_3304 = and(imem.resp.bits.data[0], UInt<32>("h0e400007f")) - node T_3306 = eq(T_3304, UInt<32>("h053")) - node T_3308 = and(imem.resp.bits.data[0], UInt<32>("h0707b")) - node T_3310 = eq(T_3308, UInt<32>("h063")) - node T_3312 = and(imem.resp.bits.data[0], UInt<32>("h07f")) - node T_3314 = eq(T_3312, UInt<32>("h06f")) - node T_3316 = and(imem.resp.bits.data[0], UInt<32>("h0ffefffff")) - node T_3318 = eq(T_3316, UInt<32>("h073")) - node T_3320 = and(imem.resp.bits.data[0], UInt<32>("h0fc00305f")) - node T_3322 = eq(T_3320, UInt<32>("h01013")) - node T_3324 = and(imem.resp.bits.data[0], UInt<32>("h0fe00305f")) - node T_3326 = eq(T_3324, UInt<32>("h0101b")) - node T_3328 = and(imem.resp.bits.data[0], UInt<32>("h0605b")) - node T_3330 = eq(T_3328, UInt<32>("h02003")) - node T_3332 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_3334 = eq(T_3332, UInt<32>("h02013")) - node T_3336 = and(imem.resp.bits.data[0], UInt<32>("h01800607f")) - node T_3338 = eq(T_3336, UInt<32>("h0202f")) - node T_3340 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_3342 = eq(T_3340, UInt<32>("h02073")) - node T_3344 = and(imem.resp.bits.data[0], UInt<32>("h0bc00707f")) - node T_3346 = eq(T_3344, UInt<32>("h05013")) - node T_3348 = and(imem.resp.bits.data[0], UInt<32>("h0be00705f")) - node T_3350 = eq(T_3348, UInt<32>("h0501b")) - node T_3352 = and(imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_3354 = eq(T_3352, UInt<32>("h05033")) - node T_3356 = and(imem.resp.bits.data[0], UInt<32>("h0fe004077")) - node T_3358 = eq(T_3356, UInt<32>("h02004033")) - node T_3360 = and(imem.resp.bits.data[0], UInt<32>("h0e800607f")) - node T_3362 = eq(T_3360, UInt<32>("h0800202f")) - node T_3364 = and(imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) - node T_3366 = eq(T_3364, UInt<32>("h010000073")) - node T_3368 = and(imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) - node T_3370 = eq(T_3368, UInt<32>("h01000202f")) - node T_3372 = and(imem.resp.bits.data[0], UInt<32>("h0fff07fff")) - node T_3374 = eq(T_3372, UInt<32>("h010100073")) - node T_3376 = and(imem.resp.bits.data[0], UInt<32>("h0f400607f")) - node T_3378 = eq(T_3376, UInt<32>("h020000053")) - node T_3380 = and(imem.resp.bits.data[0], UInt<32>("h07c00607f")) - node T_3382 = eq(T_3380, UInt<32>("h020000053")) - node T_3384 = and(imem.resp.bits.data[0], UInt<32>("h07c00507f")) - node T_3386 = eq(T_3384, UInt<32>("h020000053")) - node T_3388 = eq(imem.resp.bits.data[0], UInt<32>("h030500073")) - node T_3390 = and(imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_3392 = eq(T_3390, UInt<32>("h040100053")) - node T_3394 = and(imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_3396 = eq(T_3394, UInt<32>("h042000053")) - node T_3398 = and(imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) - node T_3400 = eq(T_3398, UInt<32>("h058000053")) - node T_3402 = and(imem.resp.bits.data[0], UInt<32>("h0edc0007f")) - node T_3404 = eq(T_3402, UInt<32>("h0c0000053")) - node T_3406 = and(imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) - node T_3408 = eq(T_3406, UInt<32>("h0e0000053")) - node T_3410 = and(imem.resp.bits.data[0], UInt<32>("h0edf0707f")) - node T_3412 = eq(T_3410, UInt<32>("h0e0000053")) - node T_3414 = and(imem.resp.bits.data[0], UInt<32>("h0603f")) - node T_3416 = eq(T_3414, UInt<32>("h023")) - node T_3418 = and(imem.resp.bits.data[0], UInt<32>("h0306f")) - node T_3420 = eq(T_3418, UInt<32>("h01063")) - node T_3422 = and(imem.resp.bits.data[0], UInt<32>("h0407f")) - node T_3424 = eq(T_3422, UInt<32>("h04063")) - node T_3426 = and(imem.resp.bits.data[0], UInt<32>("h0fc007077")) - node T_3428 = eq(T_3426, UInt<32>("h033")) - node T_3430 = or(UInt<1>("h00"), T_3274) - node T_3431 = or(T_3430, T_3278) - node T_3432 = or(T_3431, T_3282) - node T_3433 = or(T_3432, T_3286) - node T_3434 = or(T_3433, T_3290) - node T_3435 = or(T_3434, T_3294) - node T_3436 = or(T_3435, T_3298) - node T_3437 = or(T_3436, T_3302) - node T_3438 = or(T_3437, T_3306) - node T_3439 = or(T_3438, T_3310) - node T_3440 = or(T_3439, T_3314) - node T_3441 = or(T_3440, T_3318) - node T_3442 = or(T_3441, T_3322) - node T_3443 = or(T_3442, T_3326) - node T_3444 = or(T_3443, T_3330) - node T_3445 = or(T_3444, T_3334) - node T_3446 = or(T_3445, T_3338) - node T_3447 = or(T_3446, T_3342) - node T_3448 = or(T_3447, T_3346) - node T_3449 = or(T_3448, T_3350) - node T_3450 = or(T_3449, T_3354) - node T_3451 = or(T_3450, T_3358) - node T_3452 = or(T_3451, T_3362) - node T_3453 = or(T_3452, T_3366) - node T_3454 = or(T_3453, T_3370) - node T_3455 = or(T_3454, T_3374) - node T_3456 = or(T_3455, T_3378) - node T_3457 = or(T_3456, T_3382) - node T_3458 = or(T_3457, T_3386) - node T_3459 = or(T_3458, T_3388) - node T_3460 = or(T_3459, T_3392) - node T_3461 = or(T_3460, T_3396) - node T_3462 = or(T_3461, T_3400) - node T_3463 = or(T_3462, T_3404) - node T_3464 = or(T_3463, T_3408) - node T_3465 = or(T_3464, T_3412) - node T_3466 = or(T_3465, T_3416) - node T_3467 = or(T_3466, T_3420) - node T_3468 = or(T_3467, T_3424) - node T_3469 = or(T_3468, T_3428) - node T_3471 = and(imem.resp.bits.data[0], UInt<32>("h05c")) - node T_3473 = eq(T_3471, UInt<32>("h04")) - node T_3475 = and(imem.resp.bits.data[0], UInt<32>("h060")) - node T_3477 = eq(T_3475, UInt<32>("h040")) - node T_3479 = or(UInt<1>("h00"), T_3473) - node T_3480 = or(T_3479, T_3477) - node T_3483 = and(imem.resp.bits.data[0], UInt<32>("h074")) - node T_3485 = eq(T_3483, UInt<32>("h060")) - node T_3487 = or(UInt<1>("h00"), T_3485) - node T_3489 = and(imem.resp.bits.data[0], UInt<32>("h068")) - node T_3491 = eq(T_3489, UInt<32>("h068")) - node T_3493 = or(UInt<1>("h00"), T_3491) - node T_3495 = and(imem.resp.bits.data[0], UInt<32>("h0203c")) - node T_3497 = eq(T_3495, UInt<32>("h024")) - node T_3499 = or(UInt<1>("h00"), T_3497) - node T_3501 = and(imem.resp.bits.data[0], UInt<32>("h064")) - node T_3503 = eq(T_3501, UInt<32>("h020")) - node T_3505 = and(imem.resp.bits.data[0], UInt<32>("h034")) - node T_3507 = eq(T_3505, UInt<32>("h020")) - node T_3509 = and(imem.resp.bits.data[0], UInt<32>("h02048")) - node T_3511 = eq(T_3509, UInt<32>("h02008")) - node T_3513 = or(UInt<1>("h00"), T_3503) - node T_3514 = or(T_3513, T_3507) - node T_3515 = or(T_3514, T_3511) - node T_3517 = and(imem.resp.bits.data[0], UInt<32>("h044")) - node T_3519 = eq(T_3517, UInt<32>("h00")) - node T_3521 = and(imem.resp.bits.data[0], UInt<32>("h04024")) - node T_3523 = eq(T_3521, UInt<32>("h020")) - node T_3525 = and(imem.resp.bits.data[0], UInt<32>("h038")) - node T_3527 = eq(T_3525, UInt<32>("h020")) - node T_3529 = and(imem.resp.bits.data[0], UInt<32>("h02050")) - node T_3531 = eq(T_3529, UInt<32>("h02000")) - node T_3533 = and(imem.resp.bits.data[0], UInt<32>("h090000034")) - node T_3535 = eq(T_3533, UInt<32>("h090000010")) - node T_3537 = or(UInt<1>("h00"), T_3519) - node T_3538 = or(T_3537, T_3523) - node T_3539 = or(T_3538, T_3527) - node T_3540 = or(T_3539, T_3531) - node T_3541 = or(T_3540, T_3535) - node T_3543 = and(imem.resp.bits.data[0], UInt<32>("h058")) - node T_3545 = eq(T_3543, UInt<32>("h00")) - node T_3547 = and(imem.resp.bits.data[0], UInt<32>("h020")) - node T_3549 = eq(T_3547, UInt<32>("h00")) - node T_3551 = and(imem.resp.bits.data[0], UInt<32>("h0c")) - node T_3553 = eq(T_3551, UInt<32>("h04")) - node T_3555 = and(imem.resp.bits.data[0], UInt<32>("h048")) - node T_3557 = eq(T_3555, UInt<32>("h048")) - node T_3559 = and(imem.resp.bits.data[0], UInt<32>("h04050")) - node T_3561 = eq(T_3559, UInt<32>("h04050")) - node T_3563 = or(UInt<1>("h00"), T_3545) - node T_3564 = or(T_3563, T_3549) - node T_3565 = or(T_3564, T_3553) - node T_3566 = or(T_3565, T_3557) - node T_3567 = or(T_3566, T_3561) - node T_3569 = and(imem.resp.bits.data[0], UInt<32>("h048")) - node T_3571 = eq(T_3569, UInt<32>("h00")) - node T_3573 = and(imem.resp.bits.data[0], UInt<32>("h018")) - node T_3575 = eq(T_3573, UInt<32>("h00")) - node T_3577 = and(imem.resp.bits.data[0], UInt<32>("h04008")) - node T_3579 = eq(T_3577, UInt<32>("h04000")) - node T_3581 = or(UInt<1>("h00"), T_3571) - node T_3582 = or(T_3581, T_3519) - node T_3583 = or(T_3582, T_3575) - node T_3584 = or(T_3583, T_3579) - node T_3585 = cat(T_3584, T_3567) - node T_3587 = and(imem.resp.bits.data[0], UInt<32>("h04004")) - node T_3589 = eq(T_3587, UInt<32>("h00")) - node T_3591 = and(imem.resp.bits.data[0], UInt<32>("h050")) - node T_3593 = eq(T_3591, UInt<32>("h00")) - node T_3595 = and(imem.resp.bits.data[0], UInt<32>("h024")) - node T_3597 = eq(T_3595, UInt<32>("h00")) - node T_3599 = or(UInt<1>("h00"), T_3589) - node T_3600 = or(T_3599, T_3593) - node T_3601 = or(T_3600, T_3519) - node T_3602 = or(T_3601, T_3597) - node T_3603 = or(T_3602, T_3575) - node T_3605 = and(imem.resp.bits.data[0], UInt<32>("h034")) - node T_3607 = eq(T_3605, UInt<32>("h014")) - node T_3609 = or(UInt<1>("h00"), T_3607) - node T_3610 = or(T_3609, T_3557) - node T_3611 = cat(T_3610, T_3603) - node T_3613 = and(imem.resp.bits.data[0], UInt<32>("h018")) - node T_3615 = eq(T_3613, UInt<32>("h08")) - node T_3617 = and(imem.resp.bits.data[0], UInt<32>("h044")) - node T_3619 = eq(T_3617, UInt<32>("h040")) - node T_3621 = or(UInt<1>("h00"), T_3615) - node T_3622 = or(T_3621, T_3619) - node T_3624 = and(imem.resp.bits.data[0], UInt<32>("h014")) - node T_3626 = eq(T_3624, UInt<32>("h014")) - node T_3628 = or(UInt<1>("h00"), T_3615) - node T_3629 = or(T_3628, T_3626) - node T_3631 = and(imem.resp.bits.data[0], UInt<32>("h030")) - node T_3633 = eq(T_3631, UInt<32>("h00")) - node T_3635 = and(imem.resp.bits.data[0], UInt<32>("h0201c")) - node T_3637 = eq(T_3635, UInt<32>("h04")) - node T_3639 = and(imem.resp.bits.data[0], UInt<32>("h014")) - node T_3641 = eq(T_3639, UInt<32>("h010")) - node T_3643 = or(UInt<1>("h00"), T_3633) - node T_3644 = or(T_3643, T_3637) - node T_3645 = or(T_3644, T_3641) - node T_3646 = cat(T_3629, T_3622) - node T_3647 = cat(T_3645, T_3646) - node T_3649 = and(imem.resp.bits.data[0], UInt<32>("h010")) - node T_3651 = eq(T_3649, UInt<32>("h00")) - node T_3653 = and(imem.resp.bits.data[0], UInt<32>("h08")) - node T_3655 = eq(T_3653, UInt<32>("h00")) - node T_3657 = or(UInt<1>("h00"), T_3651) - node T_3658 = or(T_3657, T_3655) - node T_3660 = and(imem.resp.bits.data[0], UInt<32>("h03054")) - node T_3662 = eq(T_3660, UInt<32>("h01010")) - node T_3664 = and(imem.resp.bits.data[0], UInt<32>("h01058")) - node T_3666 = eq(T_3664, UInt<32>("h01040")) - node T_3668 = and(imem.resp.bits.data[0], UInt<32>("h07044")) - node T_3670 = eq(T_3668, UInt<32>("h07000")) - node T_3672 = or(UInt<1>("h00"), T_3662) - node T_3673 = or(T_3672, T_3666) - node T_3674 = or(T_3673, T_3670) - node T_3676 = and(imem.resp.bits.data[0], UInt<32>("h02058")) - node T_3678 = eq(T_3676, UInt<32>("h02040")) - node T_3680 = and(imem.resp.bits.data[0], UInt<32>("h03054")) - node T_3682 = eq(T_3680, UInt<32>("h03010")) - node T_3684 = and(imem.resp.bits.data[0], UInt<32>("h06054")) - node T_3686 = eq(T_3684, UInt<32>("h06010")) - node T_3688 = and(imem.resp.bits.data[0], UInt<32>("h040003034")) - node T_3690 = eq(T_3688, UInt<32>("h040000030")) - node T_3692 = and(imem.resp.bits.data[0], UInt<32>("h040001054")) - node T_3694 = eq(T_3692, UInt<32>("h040001010")) - node T_3696 = or(UInt<1>("h00"), T_3678) - node T_3697 = or(T_3696, T_3682) - node T_3698 = or(T_3697, T_3686) - node T_3699 = or(T_3698, T_3690) - node T_3700 = or(T_3699, T_3694) - node T_3702 = and(imem.resp.bits.data[0], UInt<32>("h02054")) - node T_3704 = eq(T_3702, UInt<32>("h02010")) - node T_3706 = and(imem.resp.bits.data[0], UInt<32>("h040004054")) - node T_3708 = eq(T_3706, UInt<32>("h04010")) - node T_3710 = and(imem.resp.bits.data[0], UInt<32>("h05054")) - node T_3712 = eq(T_3710, UInt<32>("h04010")) - node T_3714 = and(imem.resp.bits.data[0], UInt<32>("h04058")) - node T_3716 = eq(T_3714, UInt<32>("h04040")) - node T_3718 = or(UInt<1>("h00"), T_3704) - node T_3719 = or(T_3718, T_3708) - node T_3720 = or(T_3719, T_3712) - node T_3721 = or(T_3720, T_3716) - node T_3723 = and(imem.resp.bits.data[0], UInt<32>("h054")) - node T_3725 = eq(T_3723, UInt<32>("h040")) - node T_3727 = and(imem.resp.bits.data[0], UInt<32>("h06054")) - node T_3729 = eq(T_3727, UInt<32>("h02010")) - node T_3731 = and(imem.resp.bits.data[0], UInt<32>("h040003054")) - node T_3733 = eq(T_3731, UInt<32>("h040001010")) - node T_3735 = or(UInt<1>("h00"), T_3725) - node T_3736 = or(T_3735, T_3729) - node T_3737 = or(T_3736, T_3690) - node T_3738 = or(T_3737, T_3733) - node T_3739 = cat(T_3700, T_3674) - node T_3740 = cat(T_3721, T_3739) - node T_3741 = cat(T_3738, T_3740) - node T_3743 = and(imem.resp.bits.data[0], UInt<32>("h0405f")) - node T_3745 = eq(T_3743, UInt<32>("h03")) - node T_3747 = and(imem.resp.bits.data[0], UInt<32>("h0107f")) - node T_3749 = eq(T_3747, UInt<32>("h03")) - node T_3751 = or(UInt<1>("h00"), T_3745) - node T_3752 = or(T_3751, T_3274) - node T_3753 = or(T_3752, T_3749) - node T_3754 = or(T_3753, T_3330) - node T_3755 = or(T_3754, T_3338) - node T_3756 = or(T_3755, T_3362) - node T_3757 = or(T_3756, T_3370) - node T_3759 = and(imem.resp.bits.data[0], UInt<32>("h028")) - node T_3761 = eq(T_3759, UInt<32>("h020")) - node T_3763 = and(imem.resp.bits.data[0], UInt<32>("h018000020")) - node T_3765 = eq(T_3763, UInt<32>("h018000020")) - node T_3767 = and(imem.resp.bits.data[0], UInt<32>("h020000020")) - node T_3769 = eq(T_3767, UInt<32>("h020000020")) - node T_3771 = or(UInt<1>("h00"), T_3761) - node T_3772 = or(T_3771, T_3765) - node T_3773 = or(T_3772, T_3769) - node T_3775 = and(imem.resp.bits.data[0], UInt<32>("h010000008")) - node T_3777 = eq(T_3775, UInt<32>("h010000008")) - node T_3779 = and(imem.resp.bits.data[0], UInt<32>("h040000008")) - node T_3781 = eq(T_3779, UInt<32>("h040000008")) - node T_3783 = or(UInt<1>("h00"), T_3777) - node T_3784 = or(T_3783, T_3781) - node T_3786 = and(imem.resp.bits.data[0], UInt<32>("h08000008")) - node T_3788 = eq(T_3786, UInt<32>("h08000008")) - node T_3790 = and(imem.resp.bits.data[0], UInt<32>("h080000008")) - node T_3792 = eq(T_3790, UInt<32>("h080000008")) - node T_3794 = or(UInt<1>("h00"), T_3788) - node T_3795 = or(T_3794, T_3777) - node T_3796 = or(T_3795, T_3792) - node T_3798 = and(imem.resp.bits.data[0], UInt<32>("h018000008")) - node T_3800 = eq(T_3798, UInt<32>("h08")) - node T_3802 = or(UInt<1>("h00"), T_3800) - node T_3804 = cat(T_3784, T_3773) - node T_3805 = cat(T_3796, T_3804) - node T_3806 = cat(T_3802, T_3805) - node T_3807 = cat(UInt<1>("h00"), T_3806) - node T_3809 = and(imem.resp.bits.data[0], UInt<32>("h01000")) - node T_3811 = eq(T_3809, UInt<32>("h01000")) - node T_3813 = or(UInt<1>("h00"), T_3811) - node T_3815 = and(imem.resp.bits.data[0], UInt<32>("h02000")) - node T_3817 = eq(T_3815, UInt<32>("h02000")) - node T_3819 = or(UInt<1>("h00"), T_3817) - node T_3821 = and(imem.resp.bits.data[0], UInt<32>("h04000")) - node T_3823 = eq(T_3821, UInt<32>("h04000")) - node T_3825 = or(UInt<1>("h00"), T_3823) - node T_3826 = cat(T_3819, T_3813) - node T_3827 = cat(T_3825, T_3826) - node T_3829 = and(imem.resp.bits.data[0], UInt<32>("h080000060")) - node T_3831 = eq(T_3829, UInt<32>("h040")) - node T_3833 = and(imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_3835 = eq(T_3833, UInt<32>("h040")) - node T_3837 = and(imem.resp.bits.data[0], UInt<32>("h070")) - node T_3839 = eq(T_3837, UInt<32>("h040")) - node T_3841 = or(UInt<1>("h00"), T_3831) - node T_3842 = or(T_3841, T_3835) - node T_3843 = or(T_3842, T_3839) - node T_3845 = and(imem.resp.bits.data[0], UInt<32>("h07c")) - node T_3847 = eq(T_3845, UInt<32>("h024")) - node T_3849 = and(imem.resp.bits.data[0], UInt<32>("h040000060")) - node T_3851 = eq(T_3849, UInt<32>("h040")) - node T_3853 = and(imem.resp.bits.data[0], UInt<32>("h090000060")) - node T_3855 = eq(T_3853, UInt<32>("h010000040")) - node T_3857 = or(UInt<1>("h00"), T_3847) - node T_3858 = or(T_3857, T_3851) - node T_3859 = or(T_3858, T_3839) - node T_3860 = or(T_3859, T_3855) - node T_3862 = or(UInt<1>("h00"), T_3839) - node T_3864 = and(imem.resp.bits.data[0], UInt<32>("h03c")) - node T_3866 = eq(T_3864, UInt<32>("h04")) - node T_3868 = and(imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_3870 = eq(T_3868, UInt<32>("h010000040")) - node T_3872 = or(UInt<1>("h00"), T_3866) - node T_3873 = or(T_3872, T_3831) - node T_3874 = or(T_3873, T_3839) - node T_3875 = or(T_3874, T_3870) - node T_3877 = and(imem.resp.bits.data[0], UInt<32>("h02000074")) - node T_3879 = eq(T_3877, UInt<32>("h02000030")) - node T_3881 = or(UInt<1>("h00"), T_3879) - node T_3883 = and(imem.resp.bits.data[0], UInt<32>("h064")) - node T_3885 = eq(T_3883, UInt<32>("h00")) - node T_3887 = and(imem.resp.bits.data[0], UInt<32>("h050")) - node T_3889 = eq(T_3887, UInt<32>("h010")) - node T_3891 = and(imem.resp.bits.data[0], UInt<32>("h02024")) - node T_3893 = eq(T_3891, UInt<32>("h024")) - node T_3895 = and(imem.resp.bits.data[0], UInt<32>("h028")) - node T_3897 = eq(T_3895, UInt<32>("h028")) - node T_3899 = and(imem.resp.bits.data[0], UInt<32>("h01030")) - node T_3901 = eq(T_3899, UInt<32>("h01030")) - node T_3903 = and(imem.resp.bits.data[0], UInt<32>("h02030")) - node T_3905 = eq(T_3903, UInt<32>("h02030")) - node T_3907 = and(imem.resp.bits.data[0], UInt<32>("h090000010")) - node T_3909 = eq(T_3907, UInt<32>("h080000010")) - node T_3911 = or(UInt<1>("h00"), T_3885) - node T_3912 = or(T_3911, T_3889) - node T_3913 = or(T_3912, T_3893) - node T_3914 = or(T_3913, T_3897) - node T_3915 = or(T_3914, T_3901) - node T_3916 = or(T_3915, T_3905) - node T_3917 = or(T_3916, T_3909) - node T_3919 = and(imem.resp.bits.data[0], UInt<32>("h01070")) - node T_3921 = eq(T_3919, UInt<32>("h01070")) - node T_3923 = or(UInt<1>("h00"), T_3921) - node T_3925 = and(imem.resp.bits.data[0], UInt<32>("h02070")) - node T_3927 = eq(T_3925, UInt<32>("h02070")) - node T_3929 = or(UInt<1>("h00"), T_3927) - node T_3931 = and(imem.resp.bits.data[0], UInt<32>("h03070")) - node T_3933 = eq(T_3931, UInt<32>("h070")) - node T_3935 = or(UInt<1>("h00"), T_3933) - node T_3936 = cat(T_3929, T_3923) - node T_3937 = cat(T_3935, T_3936) - node T_3939 = and(imem.resp.bits.data[0], UInt<32>("h03058")) - node T_3941 = eq(T_3939, UInt<32>("h01008")) - node T_3943 = or(UInt<1>("h00"), T_3941) - node T_3945 = and(imem.resp.bits.data[0], UInt<32>("h03058")) - node T_3947 = eq(T_3945, UInt<32>("h08")) - node T_3949 = or(UInt<1>("h00"), T_3947) - node T_3951 = and(imem.resp.bits.data[0], UInt<32>("h06048")) - node T_3953 = eq(T_3951, UInt<32>("h02008")) - node T_3955 = or(UInt<1>("h00"), T_3953) - id_ctrl.legal := T_3469 - id_ctrl.fp := T_3480 - id_ctrl.rocc := UInt<1>("h00") - id_ctrl.branch := T_3487 - id_ctrl.jal := T_3493 - id_ctrl.jalr := T_3499 - id_ctrl.rxs2 := T_3515 - id_ctrl.rxs1 := T_3541 - id_ctrl.sel_alu2 := T_3585 - id_ctrl.sel_alu1 := T_3611 - id_ctrl.sel_imm := T_3647 - id_ctrl.alu_dw := T_3658 - id_ctrl.alu_fn := T_3741 - id_ctrl.mem_1 := T_3757 - id_ctrl.mem_cmd := T_3807 - id_ctrl.mem_type := T_3827 - id_ctrl.rfs1 := T_3843 - id_ctrl.rfs2 := T_3860 - id_ctrl.rfs3 := T_3862 - id_ctrl.wfd := T_3875 - id_ctrl.div := T_3881 - id_ctrl.wxd := T_3917 - id_ctrl.csr := T_3937 - id_ctrl.fence_i := T_3943 - id_ctrl.fence := T_3949 - id_ctrl.amo := T_3955 - node id_raddr3 = bits(imem.resp.bits.data[0], 31, 27) - node id_raddr2 = bits(imem.resp.bits.data[0], 24, 20) - node id_raddr1 = bits(imem.resp.bits.data[0], 19, 15) - node id_waddr = bits(imem.resp.bits.data[0], 11, 7) - wire id_load_use : UInt<1> - id_load_use := UInt<1>("h00") - reg id_reg_fence : UInt<1>, clock, reset - onreset id_reg_fence := UInt<1>("h00") - cmem T_3967 : UInt<64>[31], clock - wire T_3969 : UInt - T_3969 := UInt<1>("h00") - node T_3971 = not(id_raddr1) - infer accessor T_3972 = T_3967[T_3971] - T_3969 := T_3972 - wire T_3974 : UInt - T_3974 := UInt<1>("h00") - node T_3976 = not(id_raddr2) - infer accessor T_3977 = T_3967[T_3976] - T_3974 := T_3977 - wire ctrl_killd : UInt<1> - ctrl_killd := UInt<1>("h00") - inst csr of CSRFile - csr.rocc.pptw.req.bits.fetch := UInt<1>("h00") - csr.rocc.pptw.req.bits.store := UInt<1>("h00") - csr.rocc.pptw.req.bits.prv := UInt<1>("h00") - csr.rocc.pptw.req.bits.addr := UInt<1>("h00") - csr.rocc.pptw.req.valid := UInt<1>("h00") - csr.rocc.dptw.req.bits.fetch := UInt<1>("h00") - csr.rocc.dptw.req.bits.store := UInt<1>("h00") - csr.rocc.dptw.req.bits.prv := UInt<1>("h00") - csr.rocc.dptw.req.bits.addr := UInt<1>("h00") - csr.rocc.dptw.req.valid := UInt<1>("h00") - csr.rocc.iptw.req.bits.fetch := UInt<1>("h00") - csr.rocc.iptw.req.bits.store := UInt<1>("h00") - csr.rocc.iptw.req.bits.prv := UInt<1>("h00") - csr.rocc.iptw.req.bits.addr := UInt<1>("h00") - csr.rocc.iptw.req.valid := UInt<1>("h00") - csr.rocc.dmem.grant.ready := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.union := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.data := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") - csr.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") - csr.rocc.dmem.acquire.valid := UInt<1>("h00") - csr.rocc.imem.grant.ready := UInt<1>("h00") - csr.rocc.imem.acquire.bits.union := UInt<1>("h00") - csr.rocc.imem.acquire.bits.a_type := UInt<1>("h00") - csr.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") - csr.rocc.imem.acquire.bits.data := UInt<1>("h00") - csr.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") - csr.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") - csr.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") - csr.rocc.imem.acquire.valid := UInt<1>("h00") - csr.rocc.interrupt := UInt<1>("h00") - csr.rocc.busy := UInt<1>("h00") - csr.rocc.mem_1.invalidate_lr := UInt<1>("h00") - csr.rocc.mem_1.req.bits.data := UInt<1>("h00") - csr.rocc.mem_1.req.bits.phys := UInt<1>("h00") - csr.rocc.mem_1.req.bits.kill := UInt<1>("h00") - csr.rocc.mem_1.req.bits.typ := UInt<1>("h00") - csr.rocc.mem_1.req.bits.cmd := UInt<1>("h00") - csr.rocc.mem_1.req.bits.tag := UInt<1>("h00") - csr.rocc.mem_1.req.bits.addr := UInt<1>("h00") - csr.rocc.mem_1.req.valid := UInt<1>("h00") - csr.rocc.resp.bits.data := UInt<1>("h00") - csr.rocc.resp.bits.rd := UInt<1>("h00") - csr.rocc.resp.valid := UInt<1>("h00") - csr.rocc.cmd.ready := UInt<1>("h00") - csr.fcsr_flags.bits := UInt<1>("h00") - csr.fcsr_flags.valid := UInt<1>("h00") - csr.pc := UInt<1>("h00") - csr.cause := UInt<1>("h00") - csr.uarch_counters[0] := UInt<1>("h00") - csr.uarch_counters[1] := UInt<1>("h00") - csr.uarch_counters[2] := UInt<1>("h00") - csr.uarch_counters[3] := UInt<1>("h00") - csr.uarch_counters[4] := UInt<1>("h00") - csr.uarch_counters[5] := UInt<1>("h00") - csr.uarch_counters[6] := UInt<1>("h00") - csr.uarch_counters[7] := UInt<1>("h00") - csr.uarch_counters[8] := UInt<1>("h00") - csr.uarch_counters[9] := UInt<1>("h00") - csr.uarch_counters[10] := UInt<1>("h00") - csr.uarch_counters[11] := UInt<1>("h00") - csr.uarch_counters[12] := UInt<1>("h00") - csr.uarch_counters[13] := UInt<1>("h00") - csr.uarch_counters[14] := UInt<1>("h00") - csr.uarch_counters[15] := UInt<1>("h00") - csr.retire := UInt<1>("h00") - csr.exception := UInt<1>("h00") - csr.rw.wdata := UInt<1>("h00") - csr.rw.cmd := UInt<1>("h00") - csr.rw.addr := UInt<1>("h00") - csr.host.ipi_rep.bits := UInt<1>("h00") - csr.host.ipi_rep.valid := UInt<1>("h00") - csr.host.ipi_req.ready := UInt<1>("h00") - csr.host.pcr_rep.ready := UInt<1>("h00") - csr.host.pcr_req.bits.data := UInt<1>("h00") - csr.host.pcr_req.bits.addr := UInt<1>("h00") - csr.host.pcr_req.bits.rw := UInt<1>("h00") - csr.host.pcr_req.valid := UInt<1>("h00") - csr.host.id := UInt<1>("h00") - csr.host.reset := UInt<1>("h00") - csr.reset := UInt<1>("h00") - csr.clock := clock - csr.reset := reset - node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) - node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) - node T_4067 = eq(id_ctrl.csr, UInt<3>("h02")) - node T_4068 = eq(id_ctrl.csr, UInt<3>("h03")) - node T_4069 = or(T_4067, T_4068) - node T_4071 = eq(id_raddr1, UInt<1>("h00")) - node id_csr_ren = and(T_4069, T_4071) - node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) - node id_csr_addr = bits(imem.resp.bits.data[0], 31, 20) - node T_4076 = eq(id_csr_ren, UInt<1>("h00")) - node T_4077 = and(id_csr_en, T_4076) - node T_4135 = and(id_csr_addr, UInt<12>("h08c4")) - node T_4137 = eq(T_4135, UInt<12>("h040")) - node T_4139 = or(UInt<1>("h00"), T_4137) - node T_4140 = bit(T_4139, 0) - node T_4142 = eq(T_4140, UInt<1>("h00")) - node T_4143 = and(T_4077, T_4142) - node id_csr_flush = or(id_system_insn, T_4143) - node T_4146 = eq(id_ctrl.legal, UInt<1>("h00")) - node T_4148 = neq(csr.status.fs, UInt<1>("h00")) - node T_4150 = eq(T_4148, UInt<1>("h00")) - node T_4151 = and(id_ctrl.fp, T_4150) - node T_4152 = or(T_4146, T_4151) - node T_4154 = neq(csr.status.xs, UInt<1>("h00")) - node T_4156 = eq(T_4154, UInt<1>("h00")) - node T_4157 = and(id_ctrl.rocc, T_4156) - node id_illegal_insn = or(T_4152, T_4157) - node id_amo_aq = bit(imem.resp.bits.data[0], 26) - node id_amo_rl = bit(imem.resp.bits.data[0], 25) - node T_4161 = and(id_ctrl.amo, id_amo_rl) - node id_fence_next = or(id_ctrl.fence, T_4161) - node T_4164 = eq(dmem.ordered, UInt<1>("h00")) - node id_mem_busy = or(T_4164, dmem.req.valid) - node T_4167 = and(ex_reg_valid, ex_ctrl.rocc) - node T_4168 = or(rocc.busy, T_4167) - node T_4169 = and(mem_reg_valid, mem_ctrl.rocc) - node T_4170 = or(T_4168, T_4169) - node T_4171 = and(wb_reg_valid, wb_ctrl.rocc) - node T_4172 = or(T_4170, T_4171) - node id_rocc_busy = and(UInt<1>("h00"), T_4172) - node T_4174 = and(id_reg_fence, id_mem_busy) - node T_4175 = or(id_fence_next, T_4174) - id_reg_fence := T_4175 - node T_4176 = and(id_rocc_busy, id_ctrl.fence) - node T_4177 = and(id_ctrl.amo, id_amo_aq) - node T_4178 = or(T_4177, id_ctrl.fence_i) - node T_4179 = or(id_ctrl.mem_1, id_ctrl.rocc) - node T_4180 = and(id_reg_fence, T_4179) - node T_4181 = or(T_4178, T_4180) - node T_4182 = or(T_4181, id_csr_en) - node T_4183 = and(id_mem_busy, T_4182) - node id_do_fence = or(T_4176, T_4183) - node T_4187 = or(csr.interrupt, imem.resp.bits.xcpt_if) - node id_xcpt = or(T_4187, id_illegal_insn) - node T_4189 = mux(imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) - node id_cause = mux(csr.interrupt, csr.interrupt_cause, T_4189) - node ex_waddr = bits(ex_reg_inst, 11, 7) - node mem_waddr = bits(mem_reg_inst, 11, 7) - node wb_waddr = bits(wb_reg_inst, 11, 7) - node T_4197 = and(ex_reg_valid, ex_ctrl.wxd) - node T_4198 = and(mem_reg_valid, mem_ctrl.wxd) - node T_4200 = eq(mem_ctrl.mem_1, UInt<1>("h00")) - node T_4201 = and(T_4198, T_4200) - node T_4202 = and(mem_reg_valid, mem_ctrl.wxd) - node T_4203 = eq(UInt<1>("h00"), id_raddr1) - node T_4204 = and(UInt<1>("h01"), T_4203) - node T_4205 = eq(ex_waddr, id_raddr1) - node T_4206 = and(T_4197, T_4205) - node T_4207 = eq(mem_waddr, id_raddr1) - node T_4208 = and(T_4201, T_4207) - node T_4209 = eq(mem_waddr, id_raddr1) - node T_4210 = and(T_4202, T_4209) - node T_4211 = eq(UInt<1>("h00"), id_raddr2) - node T_4212 = and(UInt<1>("h01"), T_4211) - node T_4213 = eq(ex_waddr, id_raddr2) - node T_4214 = and(T_4197, T_4213) - node T_4215 = eq(mem_waddr, id_raddr2) - node T_4216 = and(T_4201, T_4215) - node T_4217 = eq(mem_waddr, id_raddr2) - node T_4218 = and(T_4202, T_4217) - wire bypass_mux : UInt[4] - bypass_mux[0] := UInt<1>("h00") - bypass_mux[1] := mem_reg_wdata - bypass_mux[2] := wb_reg_wdata - bypass_mux[3] := dmem.resp.bits.data - reg ex_reg_rs_bypass : UInt<1>[2], clock, reset - reg ex_reg_rs_lsb : UInt[2], clock, reset - reg ex_reg_rs_msb : UInt[2], clock, reset - infer accessor T_4262 = bypass_mux[ex_reg_rs_lsb[0]] - node T_4263 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) - node T_4264 = mux(ex_reg_rs_bypass[0], T_4262, T_4263) - infer accessor T_4265 = bypass_mux[ex_reg_rs_lsb[1]] - node T_4266 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) - node T_4267 = mux(ex_reg_rs_bypass[1], T_4265, T_4266) - node T_4268 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_4270 = bit(ex_reg_inst, 31) - node T_4271 = asSInt(T_4270) - node T_4272 = mux(T_4268, asSInt(UInt<1>("h00")), T_4271) - node T_4273 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_4274 = bits(ex_reg_inst, 30, 20) - node T_4275 = asSInt(T_4274) - node T_4276 = mux(T_4273, T_4275, T_4272) - node T_4277 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_4278 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_4279 = and(T_4277, T_4278) - node T_4280 = bits(ex_reg_inst, 19, 12) - node T_4281 = asSInt(T_4280) - node T_4282 = mux(T_4279, T_4272, T_4281) - node T_4283 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_4284 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_4285 = or(T_4283, T_4284) - node T_4287 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_4288 = bit(ex_reg_inst, 20) - node T_4289 = asSInt(T_4288) - node T_4290 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_4291 = bit(ex_reg_inst, 7) - node T_4292 = asSInt(T_4291) - node T_4293 = mux(T_4290, T_4292, T_4272) - node T_4294 = mux(T_4287, T_4289, T_4293) - node T_4295 = mux(T_4285, asSInt(UInt<1>("h00")), T_4294) - node T_4296 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_4297 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_4298 = or(T_4296, T_4297) - node T_4300 = bits(ex_reg_inst, 30, 25) - node T_4301 = mux(T_4298, UInt<1>("h00"), T_4300) - node T_4302 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_4304 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_4305 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_4306 = or(T_4304, T_4305) - node T_4307 = bits(ex_reg_inst, 11, 8) - node T_4308 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_4309 = bits(ex_reg_inst, 19, 16) - node T_4310 = bits(ex_reg_inst, 24, 21) - node T_4311 = mux(T_4308, T_4309, T_4310) - node T_4312 = mux(T_4306, T_4307, T_4311) - node T_4313 = mux(T_4302, UInt<1>("h00"), T_4312) - node T_4314 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_4315 = bit(ex_reg_inst, 7) - node T_4316 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) - node T_4317 = bit(ex_reg_inst, 20) - node T_4318 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_4319 = bit(ex_reg_inst, 15) - node T_4321 = shl(T_4319, 0) - node T_4322 = mux(T_4318, T_4321, UInt<1>("h00")) - node T_4323 = shl(T_4317, 0) - node T_4324 = mux(T_4316, T_4323, T_4322) - node T_4325 = shl(T_4315, 0) - node T_4326 = mux(T_4314, T_4325, T_4324) - node T_4327 = asUInt(T_4272) - node T_4328 = asUInt(T_4276) - node T_4329 = asUInt(T_4282) - node T_4330 = cat(T_4328, T_4329) - node T_4331 = cat(T_4327, T_4330) - node T_4332 = asUInt(T_4295) - node T_4333 = cat(T_4332, T_4301) - node T_4334 = cat(T_4313, T_4326) - node T_4335 = cat(T_4333, T_4334) - node T_4336 = cat(T_4331, T_4335) - node ex_imm = asSInt(T_4336) - node T_4339 = asSInt(T_4264) - node T_4340 = asSInt(ex_reg_pc) - node T_4341 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) - node T_4342 = mux(T_4341, T_4340, asSInt(UInt<1>("h00"))) - node T_4343 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) - node ex_op1 = mux(T_4343, T_4339, T_4342) - node T_4346 = asSInt(T_4267) - node T_4348 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) - node T_4349 = mux(T_4348, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) - node T_4350 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) - node T_4351 = mux(T_4350, ex_imm, T_4349) - node T_4352 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) - node ex_op2 = mux(T_4352, T_4346, T_4351) - inst alu of ALU - alu.in1 := UInt<1>("h00") - alu.in2 := UInt<1>("h00") - alu.fn := UInt<1>("h00") - alu.dw := UInt<1>("h00") - alu.reset := UInt<1>("h00") - alu.clock := clock - alu.reset := reset - alu.dw := ex_ctrl.alu_dw - alu.fn := ex_ctrl.alu_fn - node T_4359 = asUInt(ex_op2) - alu.in2 := T_4359 - node T_4360 = asUInt(ex_op1) - alu.in1 := T_4360 - inst div of MulDiv - div.resp.ready := UInt<1>("h00") - div.kill := UInt<1>("h00") - div.req.bits.tag := UInt<1>("h00") - div.req.bits.in2 := UInt<1>("h00") - div.req.bits.in1 := UInt<1>("h00") - div.req.bits.dw := UInt<1>("h00") - div.req.bits.fn := UInt<1>("h00") - div.req.valid := UInt<1>("h00") - div.reset := UInt<1>("h00") - div.clock := clock - div.reset := reset - node T_4370 = and(ex_reg_valid, ex_ctrl.div) - div.req.valid := T_4370 - div.req.bits.dw := ex_ctrl.alu_dw - div.req.bits.fn := ex_ctrl.alu_fn - div.req.bits.in1 := T_4264 - div.req.bits.in2 := T_4267 - div.req.bits.tag := ex_waddr - node T_4372 = eq(ctrl_killd, UInt<1>("h00")) - ex_reg_valid := T_4372 - node T_4374 = eq(ctrl_killd, UInt<1>("h00")) - node T_4375 = and(T_4374, id_xcpt) - ex_reg_xcpt := T_4375 - node T_4377 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_4378 = and(csr.interrupt, T_4377) - node T_4379 = and(T_4378, imem.resp.valid) - ex_reg_xcpt_interrupt := T_4379 - when id_xcpt : - ex_reg_cause := id_cause - skip - node T_4381 = eq(ctrl_killd, UInt<1>("h00")) - when T_4381 : - ex_ctrl <> id_ctrl - ex_ctrl.csr := id_csr - ex_reg_btb_hit := imem.btb_resp.valid - when imem.btb_resp.valid : - ex_reg_btb_resp <> imem.btb_resp.bits - skip - node T_4382 = or(id_ctrl.fence_i, id_csr_flush) - ex_reg_flush_pipe := T_4382 - ex_reg_load_use := id_load_use - node T_4383 = or(T_4204, T_4206) - node T_4384 = or(T_4383, T_4208) - node T_4385 = or(T_4384, T_4210) - node T_4390 = mux(T_4208, UInt<2>("h02"), UInt<2>("h03")) - node T_4391 = mux(T_4206, UInt<1>("h01"), T_4390) - node T_4392 = mux(T_4204, UInt<1>("h00"), T_4391) - ex_reg_rs_bypass[0] := T_4385 - ex_reg_rs_lsb[0] := T_4392 - node T_4394 = eq(T_4385, UInt<1>("h00")) - node T_4395 = and(id_ctrl.rxs1, T_4394) - when T_4395 : - node T_4396 = bits(T_3969, 1, 0) - ex_reg_rs_lsb[0] := T_4396 - node T_4397 = shr(T_3969, 2) - ex_reg_rs_msb[0] := T_4397 - skip - node T_4398 = or(T_4212, T_4214) - node T_4399 = or(T_4398, T_4216) - node T_4400 = or(T_4399, T_4218) - node T_4405 = mux(T_4216, UInt<2>("h02"), UInt<2>("h03")) - node T_4406 = mux(T_4214, UInt<1>("h01"), T_4405) - node T_4407 = mux(T_4212, UInt<1>("h00"), T_4406) - ex_reg_rs_bypass[1] := T_4400 - ex_reg_rs_lsb[1] := T_4407 - node T_4409 = eq(T_4400, UInt<1>("h00")) - node T_4410 = and(id_ctrl.rxs2, T_4409) - when T_4410 : - node T_4411 = bits(T_3974, 1, 0) - ex_reg_rs_lsb[1] := T_4411 - node T_4412 = shr(T_3974, 2) - ex_reg_rs_msb[1] := T_4412 - skip - skip - node T_4414 = eq(ctrl_killd, UInt<1>("h00")) - node T_4415 = or(T_4414, csr.interrupt) - when T_4415 : - ex_reg_inst := imem.resp.bits.data[0] - ex_reg_pc := imem.resp.bits.pc - skip - node T_4417 = eq(dmem.resp.valid, UInt<1>("h00")) - node wb_dcache_miss = and(wb_ctrl.mem_1, T_4417) - node T_4420 = eq(dmem.req.ready, UInt<1>("h00")) - node T_4421 = and(ex_ctrl.mem_1, T_4420) - node T_4423 = eq(div.req.ready, UInt<1>("h00")) - node T_4424 = and(ex_ctrl.div, T_4423) - node replay_ex_structural = or(T_4421, T_4424) - node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) - node T_4427 = or(replay_ex_structural, replay_ex_load_use) - node replay_ex = and(ex_reg_valid, T_4427) - node T_4429 = or(take_pc_mem_wb, replay_ex) - node T_4431 = eq(ex_reg_valid, UInt<1>("h00")) - node ctrl_killx = or(T_4429, T_4431) - node T_4433 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) - wire T_4435 : UInt<3>[4] - T_4435[0] := UInt<3>("h00") - T_4435[1] := UInt<3>("h04") - T_4435[2] := UInt<3>("h01") - T_4435[3] := UInt<3>("h05") - node T_4441 = eq(T_4435[0], ex_ctrl.mem_type) - node T_4442 = eq(T_4435[1], ex_ctrl.mem_type) - node T_4443 = eq(T_4435[2], ex_ctrl.mem_type) - node T_4444 = eq(T_4435[3], ex_ctrl.mem_type) - node T_4446 = or(UInt<1>("h00"), T_4441) - node T_4447 = or(T_4446, T_4442) - node T_4448 = or(T_4447, T_4443) - node T_4449 = or(T_4448, T_4444) - node ex_slow_bypass = or(T_4433, T_4449) - node T_4451 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) - node T_4452 = and(ex_ctrl.fp, fpu.illegal_rm) - node ex_xcpt = or(T_4451, T_4452) - node ex_cause = mux(T_4451, ex_reg_cause, UInt<2>("h02")) - node mem_br_taken = bit(mem_reg_wdata, 0) - node T_4457 = asSInt(mem_reg_pc) - node T_4458 = and(mem_ctrl.branch, mem_br_taken) - node T_4459 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_4461 = bit(mem_reg_inst, 31) - node T_4462 = asSInt(T_4461) - node T_4463 = mux(T_4459, asSInt(UInt<1>("h00")), T_4462) - node T_4464 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_4465 = bits(mem_reg_inst, 30, 20) - node T_4466 = asSInt(T_4465) - node T_4467 = mux(T_4464, T_4466, T_4463) - node T_4468 = neq(UInt<3>("h01"), UInt<3>("h02")) - node T_4469 = neq(UInt<3>("h01"), UInt<3>("h03")) - node T_4470 = and(T_4468, T_4469) - node T_4471 = bits(mem_reg_inst, 19, 12) - node T_4472 = asSInt(T_4471) - node T_4473 = mux(T_4470, T_4463, T_4472) - node T_4474 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_4475 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_4476 = or(T_4474, T_4475) - node T_4478 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_4479 = bit(mem_reg_inst, 20) - node T_4480 = asSInt(T_4479) - node T_4481 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_4482 = bit(mem_reg_inst, 7) - node T_4483 = asSInt(T_4482) - node T_4484 = mux(T_4481, T_4483, T_4463) - node T_4485 = mux(T_4478, T_4480, T_4484) - node T_4486 = mux(T_4476, asSInt(UInt<1>("h00")), T_4485) - node T_4487 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_4488 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_4489 = or(T_4487, T_4488) - node T_4491 = bits(mem_reg_inst, 30, 25) - node T_4492 = mux(T_4489, UInt<1>("h00"), T_4491) - node T_4493 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_4495 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_4496 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_4497 = or(T_4495, T_4496) - node T_4498 = bits(mem_reg_inst, 11, 8) - node T_4499 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_4500 = bits(mem_reg_inst, 19, 16) - node T_4501 = bits(mem_reg_inst, 24, 21) - node T_4502 = mux(T_4499, T_4500, T_4501) - node T_4503 = mux(T_4497, T_4498, T_4502) - node T_4504 = mux(T_4493, UInt<1>("h00"), T_4503) - node T_4505 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_4506 = bit(mem_reg_inst, 7) - node T_4507 = eq(UInt<3>("h01"), UInt<3>("h04")) - node T_4508 = bit(mem_reg_inst, 20) - node T_4509 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_4510 = bit(mem_reg_inst, 15) - node T_4512 = shl(T_4510, 0) - node T_4513 = mux(T_4509, T_4512, UInt<1>("h00")) - node T_4514 = shl(T_4508, 0) - node T_4515 = mux(T_4507, T_4514, T_4513) - node T_4516 = shl(T_4506, 0) - node T_4517 = mux(T_4505, T_4516, T_4515) - node T_4518 = asUInt(T_4463) - node T_4519 = asUInt(T_4467) - node T_4520 = asUInt(T_4473) - node T_4521 = cat(T_4519, T_4520) - node T_4522 = cat(T_4518, T_4521) - node T_4523 = asUInt(T_4486) - node T_4524 = cat(T_4523, T_4492) - node T_4525 = cat(T_4504, T_4517) - node T_4526 = cat(T_4524, T_4525) - node T_4527 = cat(T_4522, T_4526) - node T_4528 = asSInt(T_4527) - node T_4529 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_4531 = bit(mem_reg_inst, 31) - node T_4532 = asSInt(T_4531) - node T_4533 = mux(T_4529, asSInt(UInt<1>("h00")), T_4532) - node T_4534 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_4535 = bits(mem_reg_inst, 30, 20) - node T_4536 = asSInt(T_4535) - node T_4537 = mux(T_4534, T_4536, T_4533) - node T_4538 = neq(UInt<3>("h03"), UInt<3>("h02")) - node T_4539 = neq(UInt<3>("h03"), UInt<3>("h03")) - node T_4540 = and(T_4538, T_4539) - node T_4541 = bits(mem_reg_inst, 19, 12) - node T_4542 = asSInt(T_4541) - node T_4543 = mux(T_4540, T_4533, T_4542) - node T_4544 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_4545 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_4546 = or(T_4544, T_4545) - node T_4548 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_4549 = bit(mem_reg_inst, 20) - node T_4550 = asSInt(T_4549) - node T_4551 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_4552 = bit(mem_reg_inst, 7) - node T_4553 = asSInt(T_4552) - node T_4554 = mux(T_4551, T_4553, T_4533) - node T_4555 = mux(T_4548, T_4550, T_4554) - node T_4556 = mux(T_4546, asSInt(UInt<1>("h00")), T_4555) - node T_4557 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_4558 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_4559 = or(T_4557, T_4558) - node T_4561 = bits(mem_reg_inst, 30, 25) - node T_4562 = mux(T_4559, UInt<1>("h00"), T_4561) - node T_4563 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_4565 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_4566 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_4567 = or(T_4565, T_4566) - node T_4568 = bits(mem_reg_inst, 11, 8) - node T_4569 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_4570 = bits(mem_reg_inst, 19, 16) - node T_4571 = bits(mem_reg_inst, 24, 21) - node T_4572 = mux(T_4569, T_4570, T_4571) - node T_4573 = mux(T_4567, T_4568, T_4572) - node T_4574 = mux(T_4563, UInt<1>("h00"), T_4573) - node T_4575 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_4576 = bit(mem_reg_inst, 7) - node T_4577 = eq(UInt<3>("h03"), UInt<3>("h04")) - node T_4578 = bit(mem_reg_inst, 20) - node T_4579 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_4580 = bit(mem_reg_inst, 15) - node T_4582 = shl(T_4580, 0) - node T_4583 = mux(T_4579, T_4582, UInt<1>("h00")) - node T_4584 = shl(T_4578, 0) - node T_4585 = mux(T_4577, T_4584, T_4583) - node T_4586 = shl(T_4576, 0) - node T_4587 = mux(T_4575, T_4586, T_4585) - node T_4588 = asUInt(T_4533) - node T_4589 = asUInt(T_4537) - node T_4590 = asUInt(T_4543) - node T_4591 = cat(T_4589, T_4590) - node T_4592 = cat(T_4588, T_4591) - node T_4593 = asUInt(T_4556) - node T_4594 = cat(T_4593, T_4562) - node T_4595 = cat(T_4574, T_4587) - node T_4596 = cat(T_4594, T_4595) - node T_4597 = cat(T_4592, T_4596) - node T_4598 = asSInt(T_4597) - node T_4600 = mux(mem_ctrl.jal, T_4598, asSInt(UInt<4>("h04"))) - node T_4601 = mux(T_4458, T_4528, T_4600) - node mem_br_target = addw(T_4457, T_4601) - node T_4603 = asSInt(mem_reg_wdata) - node T_4604 = mux(mem_ctrl.jalr, mem_br_target, T_4603) - node mem_int_wdata = asUInt(T_4604) - node T_4606 = shr(mem_reg_wdata, 38) - node T_4607 = bits(mem_reg_wdata, 39, 38) - node T_4609 = eq(T_4606, UInt<1>("h00")) - node T_4611 = eq(T_4606, UInt<1>("h01")) - node T_4612 = or(T_4609, T_4611) - node T_4614 = neq(T_4607, UInt<1>("h00")) - node T_4615 = asSInt(T_4606) - node T_4617 = eq(T_4615, asSInt(UInt<1>("h01"))) - node T_4618 = asSInt(T_4606) - node T_4620 = eq(T_4618, asSInt(UInt<2>("h02"))) - node T_4621 = or(T_4617, T_4620) - node T_4622 = asSInt(T_4607) - node T_4624 = eq(T_4622, asSInt(UInt<1>("h01"))) - node T_4625 = bit(T_4607, 0) - node T_4626 = mux(T_4621, T_4624, T_4625) - node T_4627 = mux(T_4612, T_4614, T_4626) - node T_4628 = bits(mem_reg_wdata, 38, 0) - node T_4629 = cat(T_4627, T_4628) - node T_4630 = asSInt(T_4629) - node T_4631 = mux(mem_ctrl.jalr, T_4630, mem_br_target) - node T_4633 = and(T_4631, asSInt(UInt<2>("h02"))) - node mem_npc = asUInt(T_4633) - node T_4635 = neq(mem_npc, ex_reg_pc) - node T_4637 = eq(ex_reg_valid, UInt<1>("h00")) - node mem_wrong_npc = or(T_4635, T_4637) - node mem_npc_misaligned = bit(mem_npc, 1) - node T_4640 = and(mem_wrong_npc, mem_reg_valid) - node T_4641 = or(mem_ctrl.branch, mem_ctrl.jalr) - node T_4642 = or(T_4641, mem_ctrl.jal) - node mem_misprediction = and(T_4640, T_4642) - node T_4644 = or(mem_misprediction, mem_reg_flush_pipe) - node want_take_pc_mem = and(mem_reg_valid, T_4644) - node T_4647 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_4648 = and(want_take_pc_mem, T_4647) - take_pc_mem := T_4648 - node T_4650 = eq(ctrl_killx, UInt<1>("h00")) - mem_reg_valid := T_4650 - node T_4652 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_4653 = and(T_4652, replay_ex) - mem_reg_replay := T_4653 - node T_4655 = eq(ctrl_killx, UInt<1>("h00")) - node T_4656 = and(T_4655, ex_xcpt) - mem_reg_xcpt := T_4656 - node T_4658 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_4659 = and(T_4658, ex_reg_xcpt_interrupt) - mem_reg_xcpt_interrupt := T_4659 - when ex_xcpt : - mem_reg_cause := ex_cause - skip - node T_4660 = or(ex_reg_valid, ex_reg_xcpt_interrupt) - when T_4660 : - mem_ctrl <> ex_ctrl - mem_reg_btb_hit := ex_reg_btb_hit - when ex_reg_btb_hit : - mem_reg_btb_resp <> ex_reg_btb_resp - skip - mem_reg_flush_pipe := ex_reg_flush_pipe - mem_reg_slow_bypass := ex_slow_bypass - mem_reg_inst := ex_reg_inst - mem_reg_pc := ex_reg_pc - mem_reg_wdata := alu.out - node T_4661 = or(ex_ctrl.mem_1, ex_ctrl.rocc) - node T_4662 = and(ex_ctrl.rxs2, T_4661) - when T_4662 : - mem_reg_rs2 := T_4267 - skip - skip - node T_4663 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) - node T_4664 = and(want_take_pc_mem, mem_npc_misaligned) - node T_4666 = and(mem_reg_valid, mem_ctrl.mem_1) - node T_4667 = and(T_4666, dmem.xcpt.ma.st) - node T_4669 = and(mem_reg_valid, mem_ctrl.mem_1) - node T_4670 = and(T_4669, dmem.xcpt.ma.ld) - node T_4672 = and(mem_reg_valid, mem_ctrl.mem_1) - node T_4673 = and(T_4672, dmem.xcpt.pf.st) - node T_4675 = and(mem_reg_valid, mem_ctrl.mem_1) - node T_4676 = and(T_4675, dmem.xcpt.pf.ld) - node T_4678 = or(T_4663, T_4664) - node T_4679 = or(T_4678, T_4667) - node T_4680 = or(T_4679, T_4670) - node T_4681 = or(T_4680, T_4673) - node mem_xcpt = or(T_4681, T_4676) - node T_4683 = mux(T_4673, UInt<3>("h07"), UInt<3>("h05")) - node T_4684 = mux(T_4670, UInt<3>("h04"), T_4683) - node T_4685 = mux(T_4667, UInt<3>("h06"), T_4684) - node T_4686 = mux(T_4664, UInt<1>("h00"), T_4685) - node mem_cause = mux(T_4663, mem_reg_cause, T_4686) - node T_4688 = and(mem_reg_valid, mem_ctrl.wxd) - node dcache_kill_mem = and(T_4688, dmem.replay_next.valid) - node T_4690 = and(mem_reg_valid, mem_ctrl.fp) - node fpu_kill_mem = and(T_4690, fpu.nack_mem) - node T_4692 = or(dcache_kill_mem, mem_reg_replay) - node replay_mem = or(T_4692, fpu_kill_mem) - node T_4694 = or(dcache_kill_mem, take_pc_wb) - node T_4695 = or(T_4694, mem_reg_xcpt) - node T_4697 = eq(mem_reg_valid, UInt<1>("h00")) - node killm_common = or(T_4695, T_4697) - node T_4699 = and(div.req.ready, div.req.valid) - reg T_4700 : UInt<1>, clock, reset - T_4700 := T_4699 - node T_4701 = and(killm_common, T_4700) - div.kill := T_4701 - node T_4702 = or(killm_common, mem_xcpt) - node ctrl_killm = or(T_4702, fpu_kill_mem) - node T_4705 = eq(ctrl_killm, UInt<1>("h00")) - wb_reg_valid := T_4705 - node T_4707 = eq(take_pc_wb, UInt<1>("h00")) - node T_4708 = and(replay_mem, T_4707) - wb_reg_replay := T_4708 - node T_4710 = eq(take_pc_wb, UInt<1>("h00")) - node T_4711 = and(mem_xcpt, T_4710) - wb_reg_xcpt := T_4711 - when mem_xcpt : - wb_reg_cause := mem_cause - skip - node T_4712 = or(mem_reg_valid, mem_reg_replay) - node T_4713 = or(T_4712, mem_reg_xcpt_interrupt) - when T_4713 : - wb_ctrl <> mem_ctrl - node T_4714 = and(mem_ctrl.fp, mem_ctrl.wxd) - node T_4715 = mux(T_4714, fpu.toint_data, mem_int_wdata) - wb_reg_wdata := T_4715 - when mem_ctrl.rocc : - wb_reg_rs2 := mem_reg_rs2 - skip - wb_reg_inst := mem_reg_inst - wb_reg_pc := mem_reg_pc - skip - node T_4716 = or(wb_ctrl.div, wb_dcache_miss) - node wb_set_sboard = or(T_4716, wb_ctrl.rocc) - node T_4718 = or(dmem.resp.bits.nack, wb_reg_replay) - node replay_wb_common = or(T_4718, csr.csr_replay) - node T_4720 = and(wb_reg_valid, wb_ctrl.rocc) - node T_4722 = eq(replay_wb_common, UInt<1>("h00")) - node wb_rocc_val = and(T_4720, T_4722) - node T_4724 = and(wb_reg_valid, wb_ctrl.rocc) - node T_4726 = eq(rocc.cmd.ready, UInt<1>("h00")) - node T_4727 = and(T_4724, T_4726) - node replay_wb = or(replay_wb_common, T_4727) - node wb_xcpt = or(wb_reg_xcpt, csr.csr_xcpt) - node T_4730 = or(replay_wb, wb_xcpt) - node T_4731 = or(T_4730, csr.eret) - take_pc_wb := T_4731 - when wb_rocc_val : - node T_4733 = eq(rocc.cmd.ready, UInt<1>("h00")) - wb_reg_rocc_pending := T_4733 - skip - when wb_reg_xcpt : - wb_reg_rocc_pending := UInt<1>("h00") - skip - node T_4735 = bit(dmem.resp.bits.tag, 0) - node T_4736 = bit(T_4735, 0) - node dmem_resp_xpu = eq(T_4736, UInt<1>("h00")) - node T_4739 = bit(dmem.resp.bits.tag, 0) - node dmem_resp_fpu = bit(T_4739, 0) - node dmem_resp_waddr = bits(dmem.resp.bits.tag, 5, 1) - node dmem_resp_valid = and(dmem.resp.valid, dmem.resp.bits.has_data) - node dmem_resp_replay = and(dmem.resp.bits.replay, dmem.resp.bits.has_data) - node T_4744 = and(wb_reg_valid, wb_ctrl.wxd) - node T_4746 = eq(T_4744, UInt<1>("h00")) - div.resp.ready := T_4746 - wire ll_wdata : UInt - ll_wdata := div.resp.bits.data - wire ll_waddr : UInt - ll_waddr := div.resp.bits.tag - node T_4749 = and(div.resp.ready, div.resp.valid) - wire ll_wen : UInt<1> - ll_wen := T_4749 - node T_4751 = and(dmem_resp_replay, dmem_resp_xpu) - when T_4751 : - div.resp.ready := UInt<1>("h00") - ll_waddr := dmem_resp_waddr - ll_wen := UInt<1>("h01") - skip - node T_4755 = eq(replay_wb, UInt<1>("h00")) - node T_4756 = and(wb_reg_valid, T_4755) - node T_4758 = eq(csr.csr_xcpt, UInt<1>("h00")) - node wb_valid = and(T_4756, T_4758) - node wb_wen = and(wb_valid, wb_ctrl.wxd) - node rf_wen = or(wb_wen, ll_wen) - node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) - node T_4763 = and(dmem_resp_valid, dmem_resp_xpu) - node T_4764 = neq(wb_ctrl.csr, UInt<3>("h00")) - node T_4765 = mux(T_4764, csr.rw.rdata, wb_reg_wdata) - node T_4766 = mux(ll_wen, ll_wdata, T_4765) - node rf_wdata = mux(T_4763, dmem.resp.bits.data_subword, T_4766) - when rf_wen : - node T_4769 = neq(rf_waddr, UInt<1>("h00")) - when T_4769 : - node T_4770 = not(rf_waddr) - infer accessor T_4771 = T_3967[T_4770] - T_4771 := rf_wdata - node T_4772 = eq(rf_waddr, id_raddr1) - when T_4772 : - T_3969 := rf_wdata - skip - node T_4773 = eq(rf_waddr, id_raddr2) - when T_4773 : - T_3974 := rf_wdata - skip - skip - skip - csr.exception := wb_reg_xcpt - csr.cause := wb_reg_cause - csr.retire := wb_valid - host <> csr.host - fpu.fcsr_rm := csr.fcsr_rm - csr.fcsr_flags <> fpu.fcsr_flags - csr.rocc <> rocc - csr.pc := wb_reg_pc - csr.uarch_counters[0] := UInt<1>("h00") - csr.uarch_counters[1] := UInt<1>("h00") - csr.uarch_counters[2] := UInt<1>("h00") - csr.uarch_counters[3] := UInt<1>("h00") - csr.uarch_counters[4] := UInt<1>("h00") - csr.uarch_counters[5] := UInt<1>("h00") - csr.uarch_counters[6] := UInt<1>("h00") - csr.uarch_counters[7] := UInt<1>("h00") - csr.uarch_counters[8] := UInt<1>("h00") - csr.uarch_counters[9] := UInt<1>("h00") - csr.uarch_counters[10] := UInt<1>("h00") - csr.uarch_counters[11] := UInt<1>("h00") - csr.uarch_counters[12] := UInt<1>("h00") - csr.uarch_counters[13] := UInt<1>("h00") - csr.uarch_counters[14] := UInt<1>("h00") - csr.uarch_counters[15] := UInt<1>("h00") - ptw.ptbr := csr.ptbr - ptw.invalidate := csr.fatc - ptw.status <> csr.status - node T_4790 = bits(wb_reg_inst, 31, 20) - csr.rw.addr := T_4790 - node T_4791 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) - csr.rw.cmd := T_4791 - csr.rw.wdata := wb_reg_wdata - node T_4793 = neq(id_raddr1, UInt<1>("h00")) - node T_4794 = and(id_ctrl.rxs1, T_4793) - node T_4796 = neq(id_raddr2, UInt<1>("h00")) - node T_4797 = and(id_ctrl.rxs2, T_4796) - node T_4799 = neq(id_waddr, UInt<1>("h00")) - node T_4800 = and(id_ctrl.wxd, T_4799) - reg T_4802 : UInt<32>, clock, reset - onreset T_4802 := UInt<32>("h00") - node T_4805 = dshl(UInt<1>("h01"), ll_waddr) - node T_4807 = mux(ll_wen, T_4805, UInt<1>("h00")) - node T_4808 = not(T_4807) - node T_4809 = and(T_4802, T_4808) - node T_4810 = or(UInt<1>("h00"), ll_wen) - when T_4810 : - T_4802 := T_4809 - skip - node T_4811 = dshr(T_4809, id_raddr1) - node T_4812 = bit(T_4811, 0) - node T_4813 = and(T_4794, T_4812) - node T_4814 = dshr(T_4809, id_raddr2) - node T_4815 = bit(T_4814, 0) - node T_4816 = and(T_4797, T_4815) - node T_4817 = dshr(T_4809, id_waddr) - node T_4818 = bit(T_4817, 0) - node T_4819 = and(T_4800, T_4818) - node T_4820 = or(T_4813, T_4816) - node id_sboard_hazard = or(T_4820, T_4819) - node T_4822 = and(wb_set_sboard, wb_wen) - node T_4824 = dshl(UInt<1>("h01"), wb_waddr) - node T_4826 = mux(T_4822, T_4824, UInt<1>("h00")) - node T_4827 = or(T_4809, T_4826) - node T_4828 = or(T_4810, T_4822) - when T_4828 : - T_4802 := T_4827 - skip - node T_4829 = neq(ex_ctrl.csr, UInt<3>("h00")) - node T_4830 = or(T_4829, ex_ctrl.jalr) - node T_4831 = or(T_4830, ex_ctrl.mem_1) - node T_4832 = or(T_4831, ex_ctrl.div) - node T_4833 = or(T_4832, ex_ctrl.fp) - node ex_cannot_bypass = or(T_4833, ex_ctrl.rocc) - node T_4835 = eq(id_raddr1, ex_waddr) - node T_4836 = and(T_4794, T_4835) - node T_4837 = eq(id_raddr2, ex_waddr) - node T_4838 = and(T_4797, T_4837) - node T_4839 = eq(id_waddr, ex_waddr) - node T_4840 = and(T_4800, T_4839) - node T_4841 = or(T_4836, T_4838) - node T_4842 = or(T_4841, T_4840) - node data_hazard_ex = and(ex_ctrl.wxd, T_4842) - node T_4844 = eq(id_raddr1, ex_waddr) - node T_4845 = and(fpu.dec.ren1, T_4844) - node T_4846 = eq(id_raddr2, ex_waddr) - node T_4847 = and(fpu.dec.ren2, T_4846) - node T_4848 = eq(id_raddr3, ex_waddr) - node T_4849 = and(fpu.dec.ren3, T_4848) - node T_4850 = eq(id_waddr, ex_waddr) - node T_4851 = and(fpu.dec.wen, T_4850) - node T_4852 = or(T_4845, T_4847) - node T_4853 = or(T_4852, T_4849) - node T_4854 = or(T_4853, T_4851) - node fp_data_hazard_ex = and(ex_ctrl.wfd, T_4854) - node T_4856 = and(data_hazard_ex, ex_cannot_bypass) - node T_4857 = or(T_4856, fp_data_hazard_ex) - node id_ex_hazard = and(ex_reg_valid, T_4857) - node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) - node T_4861 = neq(mem_ctrl.csr, UInt<3>("h00")) - node T_4862 = and(mem_ctrl.mem_1, mem_mem_cmd_bh) - node T_4863 = or(T_4861, T_4862) - node T_4864 = or(T_4863, mem_ctrl.div) - node T_4865 = or(T_4864, mem_ctrl.fp) - node mem_cannot_bypass = or(T_4865, mem_ctrl.rocc) - node T_4867 = eq(id_raddr1, mem_waddr) - node T_4868 = and(T_4794, T_4867) - node T_4869 = eq(id_raddr2, mem_waddr) - node T_4870 = and(T_4797, T_4869) - node T_4871 = eq(id_waddr, mem_waddr) - node T_4872 = and(T_4800, T_4871) - node T_4873 = or(T_4868, T_4870) - node T_4874 = or(T_4873, T_4872) - node data_hazard_mem = and(mem_ctrl.wxd, T_4874) - node T_4876 = eq(id_raddr1, mem_waddr) - node T_4877 = and(fpu.dec.ren1, T_4876) - node T_4878 = eq(id_raddr2, mem_waddr) - node T_4879 = and(fpu.dec.ren2, T_4878) - node T_4880 = eq(id_raddr3, mem_waddr) - node T_4881 = and(fpu.dec.ren3, T_4880) - node T_4882 = eq(id_waddr, mem_waddr) - node T_4883 = and(fpu.dec.wen, T_4882) - node T_4884 = or(T_4877, T_4879) - node T_4885 = or(T_4884, T_4881) - node T_4886 = or(T_4885, T_4883) - node fp_data_hazard_mem = and(mem_ctrl.wfd, T_4886) - node T_4888 = and(data_hazard_mem, mem_cannot_bypass) - node T_4889 = or(T_4888, fp_data_hazard_mem) - node id_mem_hazard = and(mem_reg_valid, T_4889) - node T_4891 = and(mem_reg_valid, data_hazard_mem) - node T_4892 = and(T_4891, mem_ctrl.mem_1) - id_load_use := T_4892 - node T_4893 = eq(id_raddr1, wb_waddr) - node T_4894 = and(T_4794, T_4893) - node T_4895 = eq(id_raddr2, wb_waddr) - node T_4896 = and(T_4797, T_4895) - node T_4897 = eq(id_waddr, wb_waddr) - node T_4898 = and(T_4800, T_4897) - node T_4899 = or(T_4894, T_4896) - node T_4900 = or(T_4899, T_4898) - node data_hazard_wb = and(wb_ctrl.wxd, T_4900) - node T_4902 = eq(id_raddr1, wb_waddr) - node T_4903 = and(fpu.dec.ren1, T_4902) - node T_4904 = eq(id_raddr2, wb_waddr) - node T_4905 = and(fpu.dec.ren2, T_4904) - node T_4906 = eq(id_raddr3, wb_waddr) - node T_4907 = and(fpu.dec.ren3, T_4906) - node T_4908 = eq(id_waddr, wb_waddr) - node T_4909 = and(fpu.dec.wen, T_4908) - node T_4910 = or(T_4903, T_4905) - node T_4911 = or(T_4910, T_4907) - node T_4912 = or(T_4911, T_4909) - node fp_data_hazard_wb = and(wb_ctrl.wfd, T_4912) - node T_4914 = and(data_hazard_wb, wb_set_sboard) - node T_4915 = or(T_4914, fp_data_hazard_wb) - node id_wb_hazard = and(wb_reg_valid, T_4915) - reg T_4918 : UInt<32>, clock, reset - onreset T_4918 := UInt<32>("h00") - node T_4920 = and(wb_dcache_miss, wb_ctrl.wfd) - node T_4921 = or(T_4920, fpu.sboard_set) - node T_4922 = and(T_4921, wb_valid) - node T_4924 = dshl(UInt<1>("h01"), wb_waddr) - node T_4926 = mux(T_4922, T_4924, UInt<1>("h00")) - node T_4927 = or(T_4918, T_4926) - node T_4928 = or(UInt<1>("h00"), T_4922) - when T_4928 : - T_4918 := T_4927 - skip - node T_4929 = and(dmem_resp_replay, dmem_resp_fpu) - node T_4931 = dshl(UInt<1>("h01"), dmem_resp_waddr) - node T_4933 = mux(T_4929, T_4931, UInt<1>("h00")) - node T_4934 = not(T_4933) - node T_4935 = and(T_4927, T_4934) - node T_4936 = or(T_4928, T_4929) - when T_4936 : - T_4918 := T_4935 - skip - node T_4938 = dshl(UInt<1>("h01"), fpu.sboard_clra) - node T_4940 = mux(fpu.sboard_clr, T_4938, UInt<1>("h00")) - node T_4941 = not(T_4940) - node T_4942 = and(T_4935, T_4941) - node T_4943 = or(T_4936, fpu.sboard_clr) - when T_4943 : - T_4918 := T_4942 - skip - node T_4945 = eq(fpu.fcsr_rdy, UInt<1>("h00")) - node T_4946 = and(id_csr_en, T_4945) - node T_4947 = dshr(T_4918, id_raddr1) - node T_4948 = bit(T_4947, 0) - node T_4949 = and(fpu.dec.ren1, T_4948) - node T_4950 = dshr(T_4918, id_raddr2) - node T_4951 = bit(T_4950, 0) - node T_4952 = and(fpu.dec.ren2, T_4951) - node T_4953 = dshr(T_4918, id_raddr3) - node T_4954 = bit(T_4953, 0) - node T_4955 = and(fpu.dec.ren3, T_4954) - node T_4956 = dshr(T_4918, id_waddr) - node T_4957 = bit(T_4956, 0) - node T_4958 = and(fpu.dec.wen, T_4957) - node T_4959 = or(T_4949, T_4952) - node T_4960 = or(T_4959, T_4955) - node T_4961 = or(T_4960, T_4958) - node id_stall_fpu = or(T_4946, T_4961) - node T_4963 = or(id_ex_hazard, id_mem_hazard) - node T_4964 = or(T_4963, id_wb_hazard) - node T_4965 = or(T_4964, id_sboard_hazard) - node T_4966 = and(id_ctrl.fp, id_stall_fpu) - node T_4967 = or(T_4965, T_4966) - node T_4969 = eq(dmem.req.ready, UInt<1>("h00")) - node T_4970 = and(id_ctrl.mem_1, T_4969) - node T_4971 = or(T_4967, T_4970) - node T_4973 = and(UInt<1>("h00"), wb_reg_rocc_pending) - node T_4974 = and(T_4973, id_ctrl.rocc) - node T_4976 = eq(rocc.cmd.ready, UInt<1>("h00")) - node T_4977 = and(T_4974, T_4976) - node T_4978 = or(T_4971, T_4977) - node T_4979 = or(T_4978, id_do_fence) - node ctrl_stalld = or(T_4979, csr.csr_stall) - node T_4982 = eq(imem.resp.valid, UInt<1>("h00")) - node T_4983 = or(T_4982, take_pc_mem_wb) - node T_4984 = or(T_4983, ctrl_stalld) - node T_4985 = or(T_4984, csr.interrupt) - ctrl_killd := T_4985 - imem.req.valid := take_pc_mem_wb - node T_4986 = or(wb_xcpt, csr.eret) - node T_4987 = mux(replay_wb, wb_reg_pc, mem_npc) - node T_4988 = mux(T_4986, csr.evec, T_4987) - imem.req.bits.pc := T_4988 - node T_4989 = and(wb_reg_valid, wb_ctrl.fence_i) - imem.invalidate := T_4989 - node T_4991 = eq(ctrl_stalld, UInt<1>("h00")) - node T_4992 = or(T_4991, csr.interrupt) - imem.resp.ready := T_4992 - node T_4994 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_4995 = and(mem_reg_valid, T_4994) - node T_4996 = and(T_4995, mem_wrong_npc) - node T_4997 = and(mem_ctrl.branch, mem_br_taken) - node T_4998 = or(T_4997, mem_ctrl.jalr) - node T_4999 = or(T_4998, mem_ctrl.jal) - node T_5000 = and(T_4996, T_4999) - node T_5002 = eq(take_pc_wb, UInt<1>("h00")) - node T_5003 = and(T_5000, T_5002) - imem.btb_update.valid := T_5003 - node T_5004 = or(mem_ctrl.jal, mem_ctrl.jalr) - imem.btb_update.bits.isJump := T_5004 - node T_5005 = bits(mem_reg_inst, 19, 15) - node T_5008 = and(T_5005, UInt<5>("h019")) - node T_5009 = eq(UInt<1>("h01"), T_5008) - node T_5010 = and(mem_ctrl.jalr, T_5009) - imem.btb_update.bits.isReturn := T_5010 - imem.btb_update.bits.pc := mem_reg_pc - imem.btb_update.bits.target := imem.req.bits.pc - imem.btb_update.bits.br_pc := mem_reg_pc - imem.btb_update.bits.prediction.valid := mem_reg_btb_hit - imem.btb_update.bits.prediction.bits <> mem_reg_btb_resp - node T_5011 = and(mem_reg_valid, mem_ctrl.branch) - node T_5013 = eq(take_pc_wb, UInt<1>("h00")) - node T_5014 = and(T_5011, T_5013) - imem.bht_update.valid := T_5014 - imem.bht_update.bits.pc := mem_reg_pc - imem.bht_update.bits.taken := mem_br_taken - imem.bht_update.bits.mispredict := mem_wrong_npc - imem.bht_update.bits.prediction <> imem.btb_update.bits.prediction - node T_5015 = and(mem_reg_valid, imem.btb_update.bits.isJump) - node T_5017 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_5018 = and(T_5015, T_5017) - node T_5020 = eq(take_pc_wb, UInt<1>("h00")) - node T_5021 = and(T_5018, T_5020) - imem.ras_update.valid := T_5021 - imem.ras_update.bits.returnAddr := mem_int_wdata - node T_5022 = bit(mem_waddr, 0) - node T_5023 = and(mem_ctrl.wxd, T_5022) - imem.ras_update.bits.isCall := T_5023 - imem.ras_update.bits.isReturn := imem.btb_update.bits.isReturn - imem.ras_update.bits.prediction <> imem.btb_update.bits.prediction - node T_5025 = eq(ctrl_killd, UInt<1>("h00")) - node T_5026 = and(T_5025, id_ctrl.fp) - fpu.valid := T_5026 - fpu.killx := ctrl_killx - fpu.killm := killm_common - fpu.inst_1 := imem.resp.bits.data[0] - fpu.fromint_data := T_4264 - node T_5027 = and(dmem_resp_valid, dmem_resp_fpu) - fpu.dmem_resp_val := T_5027 - fpu.dmem_resp_data := dmem.resp.bits.data - fpu.dmem_resp_type := dmem.resp.bits.typ - fpu.dmem_resp_tag := dmem_resp_waddr - node T_5028 = and(ex_reg_valid, ex_ctrl.mem_1) - dmem.req.valid := T_5028 - node T_5029 = or(killm_common, mem_xcpt) - dmem.req.bits.kill := T_5029 - dmem.req.bits.cmd := ex_ctrl.mem_cmd - dmem.req.bits.typ := ex_ctrl.mem_type - dmem.req.bits.phys := UInt<1>("h00") - node T_5031 = shr(T_4264, 38) - node T_5032 = bits(alu.adder_out, 39, 38) - node T_5034 = eq(T_5031, UInt<1>("h00")) - node T_5036 = eq(T_5031, UInt<1>("h01")) - node T_5037 = or(T_5034, T_5036) - node T_5039 = neq(T_5032, UInt<1>("h00")) - node T_5040 = asSInt(T_5031) - node T_5042 = eq(T_5040, asSInt(UInt<1>("h01"))) - node T_5043 = asSInt(T_5031) - node T_5045 = eq(T_5043, asSInt(UInt<2>("h02"))) - node T_5046 = or(T_5042, T_5045) - node T_5047 = asSInt(T_5032) - node T_5049 = eq(T_5047, asSInt(UInt<1>("h01"))) - node T_5050 = bit(T_5032, 0) - node T_5051 = mux(T_5046, T_5049, T_5050) - node T_5052 = mux(T_5037, T_5039, T_5051) - node T_5053 = bits(alu.adder_out, 38, 0) - node T_5054 = cat(T_5052, T_5053) - dmem.req.bits.addr := T_5054 - node T_5055 = cat(ex_waddr, ex_ctrl.fp) - dmem.req.bits.tag := T_5055 - node T_5056 = mux(mem_ctrl.fp, fpu.store_data, mem_reg_rs2) - dmem.req.bits.data := T_5056 - dmem.invalidate_lr := wb_xcpt - rocc.cmd.valid := wb_rocc_val - node T_5058 = neq(csr.status.xs, UInt<1>("h00")) - node T_5059 = and(wb_xcpt, T_5058) - rocc.exception := T_5059 - node T_5061 = neq(csr.status.prv, UInt<1>("h00")) - rocc.s := T_5061 - wire T_5080 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} - T_5080.opcode := UInt<1>("h00") - T_5080.rd := UInt<1>("h00") - T_5080.xs2 := UInt<1>("h00") - T_5080.xs1 := UInt<1>("h00") - T_5080.xd := UInt<1>("h00") - T_5080.rs1 := UInt<1>("h00") - T_5080.rs2 := UInt<1>("h00") - T_5080.funct := UInt<1>("h00") - node T_5097 = bits(wb_reg_inst, 6, 0) - T_5080.opcode := T_5097 - node T_5098 = bits(wb_reg_inst, 11, 7) - T_5080.rd := T_5098 - node T_5099 = bits(wb_reg_inst, 12, 12) - T_5080.xs2 := T_5099 - node T_5100 = bits(wb_reg_inst, 13, 13) - T_5080.xs1 := T_5100 - node T_5101 = bits(wb_reg_inst, 14, 14) - T_5080.xd := T_5101 - node T_5102 = bits(wb_reg_inst, 19, 15) - T_5080.rs1 := T_5102 - node T_5103 = bits(wb_reg_inst, 24, 20) - T_5080.rs2 := T_5103 - node T_5104 = bits(wb_reg_inst, 31, 25) - T_5080.funct := T_5104 - rocc.cmd.bits.inst_1 <> T_5080 - rocc.cmd.bits.rs1 := wb_reg_wdata - rocc.cmd.bits.rs2 := wb_reg_rs2 - node T_5105 = bits(csr.time, 32, 0) - node T_5107 = mux(rf_wen, rf_waddr, UInt<1>("h00")) - node T_5108 = bits(wb_reg_inst, 19, 15) - reg T_5109 : UInt, clock, reset - T_5109 := T_4264 - reg T_5110 : UInt, clock, reset - T_5110 := T_5109 - node T_5111 = bits(wb_reg_inst, 24, 20) - reg T_5112 : UInt, clock, reset - T_5112 := T_4267 - reg T_5113 : UInt, clock, reset - T_5113 := T_5112 - - module HellaCacheArbiter : - output mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} - input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2] - input clock : Clock - input reset : UInt<1> - - mem_1.invalidate_lr := UInt<1>("h00") - mem_1.req.bits.data := UInt<1>("h00") - mem_1.req.bits.phys := UInt<1>("h00") - mem_1.req.bits.kill := UInt<1>("h00") - mem_1.req.bits.typ := UInt<1>("h00") - mem_1.req.bits.cmd := UInt<1>("h00") - mem_1.req.bits.tag := UInt<1>("h00") - mem_1.req.bits.addr := UInt<1>("h00") - mem_1.req.valid := UInt<1>("h00") - requestor[0].ordered := UInt<1>("h00") - requestor[0].xcpt.pf.st := UInt<1>("h00") - requestor[0].xcpt.pf.ld := UInt<1>("h00") - requestor[0].xcpt.ma.st := UInt<1>("h00") - requestor[0].xcpt.ma.ld := UInt<1>("h00") - requestor[0].replay_next.bits := UInt<1>("h00") - requestor[0].replay_next.valid := UInt<1>("h00") - requestor[0].resp.bits.store_data := UInt<1>("h00") - requestor[0].resp.bits.data_subword := UInt<1>("h00") - requestor[0].resp.bits.has_data := UInt<1>("h00") - requestor[0].resp.bits.replay := UInt<1>("h00") - requestor[0].resp.bits.nack := UInt<1>("h00") - requestor[0].resp.bits.data := UInt<1>("h00") - requestor[0].resp.bits.typ := UInt<1>("h00") - requestor[0].resp.bits.cmd := UInt<1>("h00") - requestor[0].resp.bits.tag := UInt<1>("h00") - requestor[0].resp.bits.addr := UInt<1>("h00") - requestor[0].resp.valid := UInt<1>("h00") - requestor[0].req.ready := UInt<1>("h00") - requestor[1].ordered := UInt<1>("h00") - requestor[1].xcpt.pf.st := UInt<1>("h00") - requestor[1].xcpt.pf.ld := UInt<1>("h00") - requestor[1].xcpt.ma.st := UInt<1>("h00") - requestor[1].xcpt.ma.ld := UInt<1>("h00") - requestor[1].replay_next.bits := UInt<1>("h00") - requestor[1].replay_next.valid := UInt<1>("h00") - requestor[1].resp.bits.store_data := UInt<1>("h00") - requestor[1].resp.bits.data_subword := UInt<1>("h00") - requestor[1].resp.bits.has_data := UInt<1>("h00") - requestor[1].resp.bits.replay := UInt<1>("h00") - requestor[1].resp.bits.nack := UInt<1>("h00") - requestor[1].resp.bits.data := UInt<1>("h00") - requestor[1].resp.bits.typ := UInt<1>("h00") - requestor[1].resp.bits.cmd := UInt<1>("h00") - requestor[1].resp.bits.tag := UInt<1>("h00") - requestor[1].resp.bits.addr := UInt<1>("h00") - requestor[1].resp.valid := UInt<1>("h00") - requestor[1].req.ready := UInt<1>("h00") - reg T_1238 : UInt<1>, clock, reset - T_1238 := requestor[0].req.valid - reg T_1239 : UInt<1>, clock, reset - T_1239 := requestor[1].req.valid - node T_1240 = or(requestor[0].req.valid, requestor[1].req.valid) - mem_1.req.valid := T_1240 - requestor[0].req.ready := mem_1.req.ready - node T_1242 = eq(requestor[0].req.valid, UInt<1>("h00")) - node T_1243 = and(requestor[0].req.ready, T_1242) - requestor[1].req.ready := T_1243 - mem_1.req.bits <> requestor[1].req.bits - node T_1245 = cat(requestor[1].req.bits.tag, UInt<1>("h01")) - mem_1.req.bits.tag := T_1245 - when requestor[0].req.valid : - mem_1.req.bits.cmd := requestor[0].req.bits.cmd - mem_1.req.bits.typ := requestor[0].req.bits.typ - mem_1.req.bits.addr := requestor[0].req.bits.addr - mem_1.req.bits.phys := requestor[0].req.bits.phys - node T_1247 = cat(requestor[0].req.bits.tag, UInt<1>("h00")) - mem_1.req.bits.tag := T_1247 - skip - when T_1238 : - mem_1.req.bits.kill := requestor[0].req.bits.kill - mem_1.req.bits.data := requestor[0].req.bits.data - skip - node T_1248 = bits(mem_1.resp.bits.tag, 0, 0) - node T_1250 = eq(T_1248, UInt<1>("h00")) - node T_1251 = and(mem_1.resp.valid, T_1250) - requestor[0].resp.valid := T_1251 - requestor[0].xcpt <> mem_1.xcpt - requestor[0].ordered := mem_1.ordered - requestor[0].resp.bits <> mem_1.resp.bits - node T_1252 = shr(mem_1.resp.bits.tag, 1) - requestor[0].resp.bits.tag := T_1252 - node T_1253 = and(mem_1.resp.bits.nack, T_1250) - requestor[0].resp.bits.nack := T_1253 - node T_1254 = and(mem_1.resp.bits.replay, T_1250) - requestor[0].resp.bits.replay := T_1254 - node T_1255 = bits(mem_1.replay_next.bits, 0, 0) - node T_1257 = eq(T_1255, UInt<1>("h00")) - node T_1258 = and(mem_1.replay_next.valid, T_1257) - requestor[0].replay_next.valid := T_1258 - node T_1259 = shr(mem_1.replay_next.bits, 1) - requestor[0].replay_next.bits := T_1259 - node T_1260 = bits(mem_1.resp.bits.tag, 0, 0) - node T_1262 = eq(T_1260, UInt<1>("h01")) - node T_1263 = and(mem_1.resp.valid, T_1262) - requestor[1].resp.valid := T_1263 - requestor[1].xcpt <> mem_1.xcpt - requestor[1].ordered := mem_1.ordered - requestor[1].resp.bits <> mem_1.resp.bits - node T_1264 = shr(mem_1.resp.bits.tag, 1) - requestor[1].resp.bits.tag := T_1264 - node T_1265 = and(mem_1.resp.bits.nack, T_1262) - requestor[1].resp.bits.nack := T_1265 - node T_1266 = and(mem_1.resp.bits.replay, T_1262) - requestor[1].resp.bits.replay := T_1266 - node T_1267 = bits(mem_1.replay_next.bits, 0, 0) - node T_1269 = eq(T_1267, UInt<1>("h01")) - node T_1270 = and(mem_1.replay_next.valid, T_1269) - requestor[1].replay_next.valid := T_1270 - node T_1271 = shr(mem_1.replay_next.bits, 1) - requestor[1].replay_next.bits := T_1271 - - module FPUDecoder : - output sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - input inst_1 : UInt<32> - input clock : Clock - input reset : UInt<1> - - sigs.wflags := UInt<1>("h00") - sigs.round := UInt<1>("h00") - sigs.sqrt := UInt<1>("h00") - sigs.div := UInt<1>("h00") - sigs.fma := UInt<1>("h00") - sigs.fastpipe := UInt<1>("h00") - sigs.toint := UInt<1>("h00") - sigs.fromint := UInt<1>("h00") - sigs.single := UInt<1>("h00") - sigs.swap23 := UInt<1>("h00") - sigs.swap12 := UInt<1>("h00") - sigs.ren3 := UInt<1>("h00") - sigs.ren2 := UInt<1>("h00") - sigs.ren1 := UInt<1>("h00") - sigs.wen := UInt<1>("h00") - sigs.ldst := UInt<1>("h00") - sigs.cmd := UInt<1>("h00") - node T_42 = and(inst_1, UInt<32>("h04")) - node T_44 = eq(T_42, UInt<32>("h04")) - node T_46 = and(inst_1, UInt<32>("h08000010")) - node T_48 = eq(T_46, UInt<32>("h08000010")) - node T_50 = or(UInt<1>("h00"), T_44) - node T_51 = or(T_50, T_48) - node T_53 = and(inst_1, UInt<32>("h08")) - node T_55 = eq(T_53, UInt<32>("h08")) - node T_57 = and(inst_1, UInt<32>("h010000010")) - node T_59 = eq(T_57, UInt<32>("h010000010")) - node T_61 = or(UInt<1>("h00"), T_55) - node T_62 = or(T_61, T_59) - node T_64 = and(inst_1, UInt<32>("h040")) - node T_66 = eq(T_64, UInt<32>("h00")) - node T_68 = and(inst_1, UInt<32>("h020000000")) - node T_70 = eq(T_68, UInt<32>("h020000000")) - node T_72 = or(UInt<1>("h00"), T_66) - node T_73 = or(T_72, T_70) - node T_75 = and(inst_1, UInt<32>("h040000000")) - node T_77 = eq(T_75, UInt<32>("h040000000")) - node T_79 = or(UInt<1>("h00"), T_66) - node T_80 = or(T_79, T_77) - node T_82 = and(inst_1, UInt<32>("h010")) - node T_84 = eq(T_82, UInt<32>("h00")) - node T_86 = or(UInt<1>("h00"), T_84) - node T_87 = cat(T_62, T_51) - node T_88 = cat(T_73, T_87) - node T_89 = cat(T_80, T_88) - node T_90 = cat(T_86, T_89) - node T_92 = or(UInt<1>("h00"), T_66) - node T_94 = and(inst_1, UInt<32>("h080000020")) - node T_96 = eq(T_94, UInt<32>("h00")) - node T_98 = and(inst_1, UInt<32>("h030")) - node T_100 = eq(T_98, UInt<32>("h00")) - node T_102 = and(inst_1, UInt<32>("h010000020")) - node T_104 = eq(T_102, UInt<32>("h010000000")) - node T_106 = or(UInt<1>("h00"), T_96) - node T_107 = or(T_106, T_100) - node T_108 = or(T_107, T_104) - node T_110 = and(inst_1, UInt<32>("h080000004")) - node T_112 = eq(T_110, UInt<32>("h00")) - node T_114 = and(inst_1, UInt<32>("h010000004")) - node T_116 = eq(T_114, UInt<32>("h00")) - node T_118 = and(inst_1, UInt<32>("h050")) - node T_120 = eq(T_118, UInt<32>("h040")) - node T_122 = or(UInt<1>("h00"), T_112) - node T_123 = or(T_122, T_116) - node T_124 = or(T_123, T_120) - node T_126 = and(inst_1, UInt<32>("h040000004")) - node T_128 = eq(T_126, UInt<32>("h00")) - node T_130 = and(inst_1, UInt<32>("h020")) - node T_132 = eq(T_130, UInt<32>("h020")) - node T_134 = or(UInt<1>("h00"), T_128) - node T_135 = or(T_134, T_132) - node T_136 = or(T_135, T_120) - node T_138 = or(UInt<1>("h00"), T_120) - node T_140 = and(inst_1, UInt<32>("h050000010")) - node T_142 = eq(T_140, UInt<32>("h050000010")) - node T_144 = or(UInt<1>("h00"), T_66) - node T_145 = or(T_144, T_142) - node T_147 = and(inst_1, UInt<32>("h030000010")) - node T_149 = eq(T_147, UInt<32>("h010")) - node T_151 = or(UInt<1>("h00"), T_149) - node T_153 = and(inst_1, UInt<32>("h01040")) - node T_155 = eq(T_153, UInt<32>("h00")) - node T_157 = and(inst_1, UInt<32>("h02000040")) - node T_159 = eq(T_157, UInt<32>("h040")) - node T_161 = or(UInt<1>("h00"), T_155) - node T_162 = or(T_161, T_159) - node T_164 = and(inst_1, UInt<32>("h090000010")) - node T_166 = eq(T_164, UInt<32>("h090000010")) - node T_168 = or(UInt<1>("h00"), T_166) - node T_170 = and(inst_1, UInt<32>("h090000010")) - node T_172 = eq(T_170, UInt<32>("h080000010")) - node T_174 = or(UInt<1>("h00"), T_132) - node T_175 = or(T_174, T_172) - node T_177 = and(inst_1, UInt<32>("h0a0000010")) - node T_179 = eq(T_177, UInt<32>("h020000010")) - node T_181 = and(inst_1, UInt<32>("h0d0000010")) - node T_183 = eq(T_181, UInt<32>("h040000010")) - node T_185 = or(UInt<1>("h00"), T_179) - node T_186 = or(T_185, T_183) - node T_188 = and(inst_1, UInt<32>("h070000004")) - node T_190 = eq(T_188, UInt<32>("h00")) - node T_192 = and(inst_1, UInt<32>("h068000004")) - node T_194 = eq(T_192, UInt<32>("h00")) - node T_196 = or(UInt<1>("h00"), T_190) - node T_197 = or(T_196, T_194) - node T_198 = or(T_197, T_120) - node T_200 = and(inst_1, UInt<32>("h058000010")) - node T_202 = eq(T_200, UInt<32>("h018000010")) - node T_204 = or(UInt<1>("h00"), T_202) - node T_206 = and(inst_1, UInt<32>("h0d0000010")) - node T_208 = eq(T_206, UInt<32>("h050000010")) - node T_210 = or(UInt<1>("h00"), T_208) - node T_212 = and(inst_1, UInt<32>("h020000004")) - node T_214 = eq(T_212, UInt<32>("h00")) - node T_216 = and(inst_1, UInt<32>("h040002000")) - node T_218 = eq(T_216, UInt<32>("h040000000")) - node T_220 = or(UInt<1>("h00"), T_214) - node T_221 = or(T_220, T_120) - node T_222 = or(T_221, T_218) - node T_224 = and(inst_1, UInt<32>("h08002000")) - node T_226 = eq(T_224, UInt<32>("h08000000")) - node T_228 = and(inst_1, UInt<32>("h0c0000004")) - node T_230 = eq(T_228, UInt<32>("h080000000")) - node T_232 = or(UInt<1>("h00"), T_214) - node T_233 = or(T_232, T_120) - node T_234 = or(T_233, T_226) - node T_235 = or(T_234, T_230) - sigs.cmd := T_90 - sigs.ldst := T_92 - sigs.wen := T_108 - sigs.ren1 := T_124 - sigs.ren2 := T_136 - sigs.ren3 := T_138 - sigs.swap12 := T_145 - sigs.swap23 := T_151 - sigs.single := T_162 - sigs.fromint := T_168 - sigs.toint := T_175 - sigs.fastpipe := T_186 - sigs.fma := T_198 - sigs.div := T_204 - sigs.sqrt := T_210 - sigs.round := T_222 - sigs.wflags := T_235 - - module mulAddSubRecodedFloatN : - output exceptionFlags : UInt<5> - output out : UInt<33> - input roundingMode : UInt<2> - input c : UInt<33> - input b : UInt<33> - input a : UInt<33> - input op : UInt<2> - input clock : Clock - input reset : UInt<1> - - exceptionFlags := UInt<1>("h00") - out := UInt<1>("h00") - node signA = bit(a, 32) - node expA = bits(a, 31, 23) - node fractA = bits(a, 22, 0) - node T_14 = bits(expA, 8, 6) - node isZeroA = eq(T_14, UInt<1>("h00")) - node T_17 = bits(expA, 8, 7) - node isSpecialA = eq(T_17, UInt<2>("h03")) - node T_20 = bit(expA, 6) - node T_22 = eq(T_20, UInt<1>("h00")) - node isInfA = and(isSpecialA, T_22) - node T_24 = bit(expA, 6) - node isNaNA = and(isSpecialA, T_24) - node T_26 = bit(fractA, 22) - node T_28 = eq(T_26, UInt<1>("h00")) - node isSigNaNA = and(isNaNA, T_28) - node T_31 = eq(isZeroA, UInt<1>("h00")) - node sigA = cat(T_31, fractA) - node signB = bit(b, 32) - node expB = bits(b, 31, 23) - node fractB = bits(b, 22, 0) - node T_36 = bits(expB, 8, 6) - node isZeroB = eq(T_36, UInt<1>("h00")) - node T_39 = bits(expB, 8, 7) - node isSpecialB = eq(T_39, UInt<2>("h03")) - node T_42 = bit(expB, 6) - node T_44 = eq(T_42, UInt<1>("h00")) - node isInfB = and(isSpecialB, T_44) - node T_46 = bit(expB, 6) - node isNaNB = and(isSpecialB, T_46) - node T_48 = bit(fractB, 22) - node T_50 = eq(T_48, UInt<1>("h00")) - node isSigNaNB = and(isNaNB, T_50) - node T_53 = eq(isZeroB, UInt<1>("h00")) - node sigB = cat(T_53, fractB) - node T_55 = bit(c, 32) - node T_56 = bit(op, 0) - node opSignC = xor(T_55, T_56) - node expC = bits(c, 31, 23) - node fractC = bits(c, 22, 0) - node T_60 = bits(expC, 8, 6) - node isZeroC = eq(T_60, UInt<1>("h00")) - node T_63 = bits(expC, 8, 7) - node isSpecialC = eq(T_63, UInt<2>("h03")) - node T_66 = bit(expC, 6) - node T_68 = eq(T_66, UInt<1>("h00")) - node isInfC = and(isSpecialC, T_68) - node T_70 = bit(expC, 6) - node isNaNC = and(isSpecialC, T_70) - node T_72 = bit(fractC, 22) - node T_74 = eq(T_72, UInt<1>("h00")) - node isSigNaNC = and(isNaNC, T_74) - node T_77 = eq(isZeroC, UInt<1>("h00")) - node sigC = cat(T_77, fractC) - node roundingMode_nearest_even = eq(roundingMode, UInt<2>("h00")) - node roundingMode_minMag = eq(roundingMode, UInt<2>("h01")) - node roundingMode_min = eq(roundingMode, UInt<2>("h02")) - node roundingMode_max = eq(roundingMode, UInt<2>("h03")) - node T_91 = xor(signA, signB) - node T_92 = bit(op, 1) - node signProd = xor(T_91, T_92) - node isZeroProd = or(isZeroA, isZeroB) - node T_95 = bit(expB, 8) - node T_97 = eq(T_95, UInt<1>("h00")) - node T_99 = subw(UInt<3>("h00"), T_97) - node T_100 = bits(expB, 7, 0) - node T_101 = cat(T_99, T_100) - node T_102 = addw(T_101, expA) - node sExpAlignedProd = addw(T_102, UInt<5>("h01b")) - node doSubMags = xor(signProd, opSignC) - node sNatCAlignDist = subw(sExpAlignedProd, expC) - node T_107 = bit(sNatCAlignDist, 10) - node CAlignDist_floor = or(isZeroProd, T_107) - node T_109 = bits(sNatCAlignDist, 9, 0) - node T_111 = eq(T_109, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_111) - node T_114 = eq(isZeroC, UInt<1>("h00")) - node T_115 = bits(sNatCAlignDist, 9, 0) - node T_117 = lt(T_115, UInt<5>("h019")) - node T_118 = or(CAlignDist_floor, T_117) - node isCDominant = and(T_114, T_118) - node T_121 = bits(sNatCAlignDist, 9, 0) - node T_123 = lt(T_121, UInt<7>("h04a")) - node T_125 = mux(T_123, sNatCAlignDist, UInt<7>("h04a")) - node T_126 = mux(CAlignDist_floor, UInt<1>("h00"), T_125) - node CAlignDist = bits(T_126, 6, 0) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_130 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) - node T_131 = bits(T_130, 77, 54) - node T_132 = bits(T_131, 15, 0) - node T_135 = shl(UInt<8>("h0ff"), 8) - node T_136 = xor(UInt<16>("h0ffff"), T_135) - node T_137 = shr(T_132, 8) - node T_138 = and(T_137, T_136) - node T_139 = bits(T_132, 7, 0) - node T_140 = shl(T_139, 8) - node T_141 = not(T_136) - node T_142 = and(T_140, T_141) - node T_143 = or(T_138, T_142) - node T_144 = bits(T_136, 11, 0) - node T_145 = shl(T_144, 4) - node T_146 = xor(T_136, T_145) - node T_147 = shr(T_143, 4) - node T_148 = and(T_147, T_146) - node T_149 = bits(T_143, 11, 0) - node T_150 = shl(T_149, 4) - node T_151 = not(T_146) - node T_152 = and(T_150, T_151) - node T_153 = or(T_148, T_152) - node T_154 = bits(T_146, 13, 0) - node T_155 = shl(T_154, 2) - node T_156 = xor(T_146, T_155) - node T_157 = shr(T_153, 2) - node T_158 = and(T_157, T_156) - node T_159 = bits(T_153, 13, 0) - node T_160 = shl(T_159, 2) - node T_161 = not(T_156) - node T_162 = and(T_160, T_161) - node T_163 = or(T_158, T_162) - node T_164 = bits(T_156, 14, 0) - node T_165 = shl(T_164, 1) - node T_166 = xor(T_156, T_165) - node T_167 = shr(T_163, 1) - node T_168 = and(T_167, T_166) - node T_169 = bits(T_163, 14, 0) - node T_170 = shl(T_169, 1) - node T_171 = not(T_166) - node T_172 = and(T_170, T_171) - node T_173 = or(T_168, T_172) - node T_174 = bits(T_131, 23, 16) - node T_177 = shl(UInt<4>("h0f"), 4) - node T_178 = xor(UInt<8>("h0ff"), T_177) - node T_179 = shr(T_174, 4) - node T_180 = and(T_179, T_178) - node T_181 = bits(T_174, 3, 0) - node T_182 = shl(T_181, 4) - node T_183 = not(T_178) - node T_184 = and(T_182, T_183) - node T_185 = or(T_180, T_184) - node T_186 = bits(T_178, 5, 0) - node T_187 = shl(T_186, 2) - node T_188 = xor(T_178, T_187) - node T_189 = shr(T_185, 2) - node T_190 = and(T_189, T_188) - node T_191 = bits(T_185, 5, 0) - node T_192 = shl(T_191, 2) - node T_193 = not(T_188) - node T_194 = and(T_192, T_193) - node T_195 = or(T_190, T_194) - node T_196 = bits(T_188, 6, 0) - node T_197 = shl(T_196, 1) - node T_198 = xor(T_188, T_197) - node T_199 = shr(T_195, 1) - node T_200 = and(T_199, T_198) - node T_201 = bits(T_195, 6, 0) - node T_202 = shl(T_201, 1) - node T_203 = not(T_198) - node T_204 = and(T_202, T_203) - node T_205 = or(T_200, T_204) - node CExtraMask = cat(T_173, T_205) - node T_207 = not(sigC) - node negSigC = mux(doSubMags, T_207, sigC) - node T_210 = subw(UInt<50>("h00"), doSubMags) - node T_211 = cat(negSigC, T_210) - node T_212 = cat(doSubMags, T_211) - node T_213 = asSInt(T_212) - node T_214 = dshr(T_213, CAlignDist) - node T_215 = and(sigC, CExtraMask) - node T_217 = neq(T_215, UInt<1>("h00")) - node T_218 = xor(T_217, doSubMags) - node T_219 = asUInt(T_214) - node T_220 = cat(T_219, T_218) - node alignedNegSigC = bits(T_220, 74, 0) - node T_222 = mul(sigA, sigB) - node T_223 = shl(T_222, 1) - node sigSum = addw(T_223, alignedNegSigC) - node T_226 = bits(sigSum, 50, 1) - node T_227 = xor(UInt<50>("h00"), T_226) - node T_228 = or(UInt<50>("h00"), T_226) - node T_229 = shl(T_228, 1) - node T_230 = xor(T_227, T_229) - node T_231 = bit(T_230, 49) - node T_233 = bit(T_230, 48) - node T_235 = bit(T_230, 47) - node T_237 = bit(T_230, 46) - node T_239 = bit(T_230, 45) - node T_241 = bit(T_230, 44) - node T_243 = bit(T_230, 43) - node T_245 = bit(T_230, 42) - node T_247 = bit(T_230, 41) - node T_249 = bit(T_230, 40) - node T_251 = bit(T_230, 39) - node T_253 = bit(T_230, 38) - node T_255 = bit(T_230, 37) - node T_257 = bit(T_230, 36) - node T_259 = bit(T_230, 35) - node T_261 = bit(T_230, 34) - node T_263 = bit(T_230, 33) - node T_265 = bit(T_230, 32) - node T_267 = bit(T_230, 31) - node T_269 = bit(T_230, 30) - node T_271 = bit(T_230, 29) - node T_273 = bit(T_230, 28) - node T_275 = bit(T_230, 27) - node T_277 = bit(T_230, 26) - node T_279 = bit(T_230, 25) - node T_281 = bit(T_230, 24) - node T_283 = bit(T_230, 23) - node T_285 = bit(T_230, 22) - node T_287 = bit(T_230, 21) - node T_289 = bit(T_230, 20) - node T_291 = bit(T_230, 19) - node T_293 = bit(T_230, 18) - node T_295 = bit(T_230, 17) - node T_297 = bit(T_230, 16) - node T_299 = bit(T_230, 15) - node T_301 = bit(T_230, 14) - node T_303 = bit(T_230, 13) - node T_305 = bit(T_230, 12) - node T_307 = bit(T_230, 11) - node T_309 = bit(T_230, 10) - node T_311 = bit(T_230, 9) - node T_313 = bit(T_230, 8) - node T_315 = bit(T_230, 7) - node T_317 = bit(T_230, 6) - node T_319 = bit(T_230, 5) - node T_321 = bit(T_230, 4) - node T_323 = bit(T_230, 3) - node T_325 = bit(T_230, 2) - node T_327 = bit(T_230, 1) - node T_329 = bit(T_230, 0) - node T_331 = mux(T_327, UInt<7>("h048"), UInt<7>("h049")) - node T_332 = mux(T_325, UInt<7>("h047"), T_331) - node T_333 = mux(T_323, UInt<7>("h046"), T_332) - node T_334 = mux(T_321, UInt<7>("h045"), T_333) - node T_335 = mux(T_319, UInt<7>("h044"), T_334) - node T_336 = mux(T_317, UInt<7>("h043"), T_335) - node T_337 = mux(T_315, UInt<7>("h042"), T_336) - node T_338 = mux(T_313, UInt<7>("h041"), T_337) - node T_339 = mux(T_311, UInt<7>("h040"), T_338) - node T_340 = mux(T_309, UInt<7>("h03f"), T_339) - node T_341 = mux(T_307, UInt<7>("h03e"), T_340) - node T_342 = mux(T_305, UInt<7>("h03d"), T_341) - node T_343 = mux(T_303, UInt<7>("h03c"), T_342) - node T_344 = mux(T_301, UInt<7>("h03b"), T_343) - node T_345 = mux(T_299, UInt<7>("h03a"), T_344) - node T_346 = mux(T_297, UInt<7>("h039"), T_345) - node T_347 = mux(T_295, UInt<7>("h038"), T_346) - node T_348 = mux(T_293, UInt<7>("h037"), T_347) - node T_349 = mux(T_291, UInt<7>("h036"), T_348) - node T_350 = mux(T_289, UInt<7>("h035"), T_349) - node T_351 = mux(T_287, UInt<7>("h034"), T_350) - node T_352 = mux(T_285, UInt<7>("h033"), T_351) - node T_353 = mux(T_283, UInt<7>("h032"), T_352) - node T_354 = mux(T_281, UInt<7>("h031"), T_353) - node T_355 = mux(T_279, UInt<7>("h030"), T_354) - node T_356 = mux(T_277, UInt<7>("h02f"), T_355) - node T_357 = mux(T_275, UInt<7>("h02e"), T_356) - node T_358 = mux(T_273, UInt<7>("h02d"), T_357) - node T_359 = mux(T_271, UInt<7>("h02c"), T_358) - node T_360 = mux(T_269, UInt<7>("h02b"), T_359) - node T_361 = mux(T_267, UInt<7>("h02a"), T_360) - node T_362 = mux(T_265, UInt<7>("h029"), T_361) - node T_363 = mux(T_263, UInt<7>("h028"), T_362) - node T_364 = mux(T_261, UInt<7>("h027"), T_363) - node T_365 = mux(T_259, UInt<7>("h026"), T_364) - node T_366 = mux(T_257, UInt<7>("h025"), T_365) - node T_367 = mux(T_255, UInt<7>("h024"), T_366) - node T_368 = mux(T_253, UInt<7>("h023"), T_367) - node T_369 = mux(T_251, UInt<7>("h022"), T_368) - node T_370 = mux(T_249, UInt<7>("h021"), T_369) - node T_371 = mux(T_247, UInt<7>("h020"), T_370) - node T_372 = mux(T_245, UInt<7>("h01f"), T_371) - node T_373 = mux(T_243, UInt<7>("h01e"), T_372) - node T_374 = mux(T_241, UInt<7>("h01d"), T_373) - node T_375 = mux(T_239, UInt<7>("h01c"), T_374) - node T_376 = mux(T_237, UInt<7>("h01b"), T_375) - node T_377 = mux(T_235, UInt<7>("h01a"), T_376) - node T_378 = mux(T_233, UInt<7>("h019"), T_377) - node estNormPos_dist = mux(T_231, UInt<7>("h018"), T_378) - node T_380 = bits(sigSum, 33, 18) - node T_382 = neq(T_380, UInt<1>("h00")) - node T_383 = bits(sigSum, 17, 0) - node T_385 = neq(T_383, UInt<1>("h00")) - node firstReduceSigSum = cat(T_382, T_385) - node notSigSum = not(sigSum) - node T_388 = bits(notSigSum, 33, 18) - node T_390 = neq(T_388, UInt<1>("h00")) - node T_391 = bits(notSigSum, 17, 0) - node T_393 = neq(T_391, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_390, T_393) - node T_395 = or(CAlignDist_0, doSubMags) - node T_397 = subw(CAlignDist, UInt<1>("h01")) - node T_398 = bits(T_397, 4, 0) - node CDom_estNormDist = mux(T_395, CAlignDist, T_398) - node T_400 = not(doSubMags) - node T_401 = bit(CDom_estNormDist, 4) - node T_402 = not(T_401) - node T_403 = and(T_400, T_402) - node T_404 = asSInt(T_403) - node T_405 = bits(sigSum, 74, 34) - node T_407 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_408 = cat(T_405, T_407) - node T_409 = asSInt(T_408) - node T_410 = and(T_404, T_409) - node T_411 = not(doSubMags) - node T_412 = bit(CDom_estNormDist, 4) - node T_413 = and(T_411, T_412) - node T_414 = asSInt(T_413) - node T_415 = bits(sigSum, 58, 18) - node T_416 = bit(firstReduceSigSum, 0) - node T_417 = cat(T_415, T_416) - node T_418 = asSInt(T_417) - node T_419 = and(T_414, T_418) - node T_420 = or(T_410, T_419) - node T_421 = bit(CDom_estNormDist, 4) - node T_422 = not(T_421) - node T_423 = and(doSubMags, T_422) - node T_424 = asSInt(T_423) - node T_425 = bits(notSigSum, 74, 34) - node T_427 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_428 = cat(T_425, T_427) - node T_429 = asSInt(T_428) - node T_430 = and(T_424, T_429) - node T_431 = or(T_420, T_430) - node T_432 = bit(CDom_estNormDist, 4) - node T_433 = and(doSubMags, T_432) - node T_434 = asSInt(T_433) - node T_435 = bits(notSigSum, 58, 18) - node T_436 = bit(firstReduceNotSigSum, 0) - node T_437 = cat(T_435, T_436) - node T_438 = asSInt(T_437) - node T_439 = and(T_434, T_438) - node T_440 = or(T_431, T_439) - node CDom_firstNormAbsSigSum = asUInt(T_440) - node T_442 = bits(sigSum, 50, 18) - node T_443 = bit(firstReduceNotSigSum, 0) - node T_444 = not(T_443) - node T_445 = bit(firstReduceSigSum, 0) - node T_446 = mux(doSubMags, T_444, T_445) - node T_447 = cat(T_442, T_446) - node T_448 = bits(sigSum, 42, 1) - node T_449 = bit(estNormPos_dist, 5) - node T_450 = bit(estNormPos_dist, 4) - node T_451 = bits(sigSum, 26, 1) - node T_453 = subw(UInt<16>("h00"), doSubMags) - node T_454 = cat(T_451, T_453) - node T_455 = mux(T_450, T_454, T_448) - node T_456 = bit(estNormPos_dist, 4) - node T_457 = bits(sigSum, 10, 1) - node T_459 = subw(UInt<32>("h00"), doSubMags) - node T_460 = cat(T_457, T_459) - node T_461 = mux(T_456, T_447, T_460) - node notCDom_pos_firstNormAbsSigSum = mux(T_449, T_455, T_461) - node T_463 = bits(notSigSum, 49, 18) - node T_464 = bit(firstReduceNotSigSum, 0) - node T_465 = cat(T_463, T_464) - node T_466 = bits(notSigSum, 42, 1) - node T_467 = bit(estNormPos_dist, 5) - node T_468 = bit(estNormPos_dist, 4) - node T_469 = bits(notSigSum, 27, 1) - node T_470 = shl(T_469, 16) - node T_471 = mux(T_468, T_470, T_466) - node T_472 = bit(estNormPos_dist, 4) - node T_473 = bits(notSigSum, 11, 1) - node T_474 = shl(T_473, 32) - node T_475 = mux(T_472, T_465, T_474) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_467, T_471, T_475) - node notCDom_signSigSum = bit(sigSum, 51) - node T_478 = not(isZeroC) - node T_479 = and(doSubMags, T_478) - node doNegSignSum = mux(isCDominant, T_479, notCDom_signSigSum) - node T_481 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(isCDominant, CDom_estNormDist, T_481) - node T_483 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_484 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_483, T_484) - node T_486 = not(isCDominant) - node T_487 = not(notCDom_signSigSum) - node T_488 = and(T_486, T_487) - node doIncrSig = and(T_488, doSubMags) - node estNormDist_5 = bits(estNormDist, 3, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_493 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) - node T_494 = bits(T_493, 15, 1) - node T_495 = bits(T_494, 7, 0) - node T_498 = shl(UInt<4>("h0f"), 4) - node T_499 = xor(UInt<8>("h0ff"), T_498) - node T_500 = shr(T_495, 4) - node T_501 = and(T_500, T_499) - node T_502 = bits(T_495, 3, 0) - node T_503 = shl(T_502, 4) - node T_504 = not(T_499) - node T_505 = and(T_503, T_504) - node T_506 = or(T_501, T_505) - node T_507 = bits(T_499, 5, 0) - node T_508 = shl(T_507, 2) - node T_509 = xor(T_499, T_508) - node T_510 = shr(T_506, 2) - node T_511 = and(T_510, T_509) - node T_512 = bits(T_506, 5, 0) - node T_513 = shl(T_512, 2) - node T_514 = not(T_509) - node T_515 = and(T_513, T_514) - node T_516 = or(T_511, T_515) - node T_517 = bits(T_509, 6, 0) - node T_518 = shl(T_517, 1) - node T_519 = xor(T_509, T_518) - node T_520 = shr(T_516, 1) - node T_521 = and(T_520, T_519) - node T_522 = bits(T_516, 6, 0) - node T_523 = shl(T_522, 1) - node T_524 = not(T_519) - node T_525 = and(T_523, T_524) - node T_526 = or(T_521, T_525) - node T_527 = bits(T_494, 14, 8) - node T_528 = bits(T_527, 3, 0) - node T_529 = bits(T_528, 1, 0) - node T_530 = bits(T_529, 0, 0) - node T_531 = bits(T_529, 1, 1) - node T_532 = cat(T_530, T_531) - node T_533 = bits(T_528, 3, 2) - node T_534 = bits(T_533, 0, 0) - node T_535 = bits(T_533, 1, 1) - node T_536 = cat(T_534, T_535) - node T_537 = cat(T_532, T_536) - node T_538 = bits(T_527, 6, 4) - node T_539 = bits(T_538, 1, 0) - node T_540 = bits(T_539, 0, 0) - node T_541 = bits(T_539, 1, 1) - node T_542 = cat(T_540, T_541) - node T_543 = bits(T_538, 2, 2) - node T_544 = cat(T_542, T_543) - node T_545 = cat(T_537, T_544) - node T_546 = cat(T_526, T_545) - node absSigSumExtraMask = cat(T_546, UInt<1>("h01")) - node T_549 = bits(cFirstNormAbsSigSum, 42, 1) - node T_550 = dshr(T_549, normTo2ShiftDist) - node T_551 = bits(cFirstNormAbsSigSum, 15, 0) - node T_552 = not(T_551) - node T_553 = and(T_552, absSigSumExtraMask) - node T_555 = eq(T_553, UInt<1>("h00")) - node T_556 = bits(cFirstNormAbsSigSum, 15, 0) - node T_557 = and(T_556, absSigSumExtraMask) - node T_559 = neq(T_557, UInt<1>("h00")) - node T_560 = mux(doIncrSig, T_555, T_559) - node T_561 = cat(T_550, T_560) - node sigX3 = bits(T_561, 27, 0) - node T_563 = bits(sigX3, 27, 26) - node sigX3Shift1 = eq(T_563, UInt<1>("h00")) - node sExpX3 = subw(sExpSum, estNormDist) - node T_567 = bits(sigX3, 27, 25) - node isZeroY = eq(T_567, UInt<1>("h00")) - node T_570 = not(isZeroY) - node T_571 = xor(signProd, doNegSignSum) - node signY = and(T_570, T_571) - node sExpX3_13 = bits(sExpX3, 9, 0) - node T_574 = bit(sExpX3, 10) - node T_576 = subw(UInt<27>("h00"), T_574) - node T_577 = not(sExpX3_13) - node T_579 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_577) - node T_580 = bits(T_579, 131, 107) - node T_581 = bits(T_580, 15, 0) - node T_584 = shl(UInt<8>("h0ff"), 8) - node T_585 = xor(UInt<16>("h0ffff"), T_584) - node T_586 = shr(T_581, 8) - node T_587 = and(T_586, T_585) - node T_588 = bits(T_581, 7, 0) - node T_589 = shl(T_588, 8) - node T_590 = not(T_585) - node T_591 = and(T_589, T_590) - node T_592 = or(T_587, T_591) - node T_593 = bits(T_585, 11, 0) - node T_594 = shl(T_593, 4) - node T_595 = xor(T_585, T_594) - node T_596 = shr(T_592, 4) - node T_597 = and(T_596, T_595) - node T_598 = bits(T_592, 11, 0) - node T_599 = shl(T_598, 4) - node T_600 = not(T_595) - node T_601 = and(T_599, T_600) - node T_602 = or(T_597, T_601) - node T_603 = bits(T_595, 13, 0) - node T_604 = shl(T_603, 2) - node T_605 = xor(T_595, T_604) - node T_606 = shr(T_602, 2) - node T_607 = and(T_606, T_605) - node T_608 = bits(T_602, 13, 0) - node T_609 = shl(T_608, 2) - node T_610 = not(T_605) - node T_611 = and(T_609, T_610) - node T_612 = or(T_607, T_611) - node T_613 = bits(T_605, 14, 0) - node T_614 = shl(T_613, 1) - node T_615 = xor(T_605, T_614) - node T_616 = shr(T_612, 1) - node T_617 = and(T_616, T_615) - node T_618 = bits(T_612, 14, 0) - node T_619 = shl(T_618, 1) - node T_620 = not(T_615) - node T_621 = and(T_619, T_620) - node T_622 = or(T_617, T_621) - node T_623 = bits(T_580, 24, 16) - node T_624 = bits(T_623, 7, 0) - node T_627 = shl(UInt<4>("h0f"), 4) - node T_628 = xor(UInt<8>("h0ff"), T_627) - node T_629 = shr(T_624, 4) - node T_630 = and(T_629, T_628) - node T_631 = bits(T_624, 3, 0) - node T_632 = shl(T_631, 4) - node T_633 = not(T_628) - node T_634 = and(T_632, T_633) - node T_635 = or(T_630, T_634) - node T_636 = bits(T_628, 5, 0) - node T_637 = shl(T_636, 2) - node T_638 = xor(T_628, T_637) - node T_639 = shr(T_635, 2) - node T_640 = and(T_639, T_638) - node T_641 = bits(T_635, 5, 0) - node T_642 = shl(T_641, 2) - node T_643 = not(T_638) - node T_644 = and(T_642, T_643) - node T_645 = or(T_640, T_644) - node T_646 = bits(T_638, 6, 0) - node T_647 = shl(T_646, 1) - node T_648 = xor(T_638, T_647) - node T_649 = shr(T_645, 1) - node T_650 = and(T_649, T_648) - node T_651 = bits(T_645, 6, 0) - node T_652 = shl(T_651, 1) - node T_653 = not(T_648) - node T_654 = and(T_652, T_653) - node T_655 = or(T_650, T_654) - node T_656 = bits(T_623, 8, 8) - node T_657 = cat(T_655, T_656) - node T_658 = cat(T_622, T_657) - node T_659 = bit(sigX3, 26) - node T_660 = or(T_658, T_659) - node T_662 = cat(T_660, UInt<2>("h03")) - node roundMask = or(T_576, T_662) - node T_664 = shr(roundMask, 1) - node T_665 = not(T_664) - node roundPosMask = and(T_665, roundMask) - node T_667 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_667, UInt<1>("h00")) - node T_670 = shr(roundMask, 1) - node T_671 = and(sigX3, T_670) - node anyRoundExtra = neq(T_671, UInt<1>("h00")) - node T_674 = not(sigX3) - node T_675 = shr(roundMask, 1) - node T_676 = and(T_674, T_675) - node allRoundExtra = eq(T_676, UInt<1>("h00")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_682 = not(doIncrSig) - node T_683 = and(T_682, roundingMode_nearest_even) - node T_684 = and(T_683, roundPosBit) - node T_685 = and(T_684, anyRoundExtra) - node T_686 = not(doIncrSig) - node T_687 = and(T_686, roundDirectUp) - node T_688 = and(T_687, anyRound) - node T_689 = or(T_685, T_688) - node T_690 = and(doIncrSig, allRound) - node T_691 = or(T_689, T_690) - node T_692 = and(doIncrSig, roundingMode_nearest_even) - node T_693 = and(T_692, roundPosBit) - node T_694 = or(T_691, T_693) - node T_695 = and(doIncrSig, roundDirectUp) - node roundUp = or(T_694, T_695) - node T_697 = not(roundPosBit) - node T_698 = and(roundingMode_nearest_even, T_697) - node T_699 = and(T_698, allRoundExtra) - node T_700 = and(roundingMode_nearest_even, roundPosBit) - node T_701 = not(anyRoundExtra) - node T_702 = and(T_700, T_701) - node roundEven = mux(doIncrSig, T_699, T_702) - node T_704 = not(allRound) - node roundInexact = mux(doIncrSig, T_704, anyRound) - node T_706 = or(sigX3, roundMask) - node T_707 = shr(T_706, 2) - node T_709 = addw(T_707, UInt<1>("h01")) - node roundUp_sigY3 = bits(T_709, 25, 0) - node T_711 = not(roundUp) - node T_712 = not(roundEven) - node T_713 = and(T_711, T_712) - node T_714 = not(roundMask) - node T_715 = and(sigX3, T_714) - node T_716 = shr(T_715, 2) - node T_718 = mux(T_713, T_716, UInt<1>("h00")) - node T_720 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) - node T_721 = or(T_718, T_720) - node T_722 = shr(roundMask, 1) - node T_723 = not(T_722) - node T_724 = and(roundUp_sigY3, T_723) - node T_726 = mux(roundEven, T_724, UInt<1>("h00")) - node sigY3 = or(T_721, T_726) - node T_728 = bit(sigY3, 25) - node T_730 = addw(sExpX3, UInt<1>("h01")) - node T_732 = mux(T_728, T_730, UInt<1>("h00")) - node T_733 = bit(sigY3, 24) - node T_735 = mux(T_733, sExpX3, UInt<1>("h00")) - node T_736 = or(T_732, T_735) - node T_737 = bits(sigY3, 25, 24) - node T_739 = eq(T_737, UInt<1>("h00")) - node T_741 = subw(sExpX3, UInt<1>("h01")) - node T_743 = mux(T_739, T_741, UInt<1>("h00")) - node sExpY = or(T_736, T_743) - node expY = bits(sExpY, 8, 0) - node T_746 = bits(sigY3, 22, 0) - node T_747 = bits(sigY3, 23, 1) - node fractY = mux(sigX3Shift1, T_746, T_747) - node T_749 = bits(sExpY, 9, 7) - node overflowY = eq(T_749, UInt<2>("h03")) - node T_752 = bit(sExpY, 9) - node T_753 = bits(sExpY, 8, 0) - node T_755 = lt(T_753, UInt<7>("h06b")) - node totalUnderflowY = or(T_752, T_755) - node T_757 = bit(sExpX3, 10) - node T_760 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) - node T_761 = leq(sExpX3_13, T_760) - node T_762 = or(T_757, T_761) - node underflowY = and(roundInexact, T_762) - node T_764 = and(roundingMode_min, signY) - node T_765 = or(roundingMode_nearest_even, T_764) - node T_766 = not(signY) - node T_767 = and(roundingMode_max, T_766) - node overflowY_roundMagUp = or(T_765, T_767) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(isZeroProd, isZeroC) - node T_772 = not(addSpecial) - node T_773 = not(notSpecial_addZeros) - node commonCase = and(T_772, T_773) - node T_775 = and(isInfA, isZeroB) - node T_776 = and(isZeroA, isInfB) - node T_777 = or(T_775, T_776) - node T_778 = not(isNaNA) - node T_779 = not(isNaNB) - node T_780 = and(T_778, T_779) - node T_781 = or(isInfA, isInfB) - node T_782 = and(T_780, T_781) - node T_783 = and(T_782, isInfC) - node T_784 = and(T_783, doSubMags) - node notSigNaN_invalid = or(T_777, T_784) - node T_786 = or(isSigNaNA, isSigNaNB) - node T_787 = or(T_786, isSigNaNC) - node invalid = or(T_787, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_791 = and(commonCase, roundInexact) - node inexact = or(overflow, T_791) - node T_793 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_793, totalUnderflowY) - node T_795 = not(overflowY_roundMagUp) - node isSatOut = and(overflow, T_795) - node T_797 = or(isInfA, isInfB) - node T_798 = or(T_797, isInfC) - node T_799 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_798, T_799) - node T_801 = or(isNaNA, isNaNB) - node T_802 = or(T_801, isNaNC) - node isNaNOut = or(T_802, notSigNaN_invalid) - node T_805 = eq(doSubMags, UInt<1>("h00")) - node T_806 = and(T_805, opSignC) - node T_808 = and(isNaNOut, UInt<1>("h01")) - node T_809 = or(T_806, T_808) - node T_811 = eq(isSpecialC, UInt<1>("h00")) - node T_812 = and(mulSpecial, T_811) - node T_813 = and(T_812, signProd) - node T_814 = or(T_809, T_813) - node T_816 = eq(mulSpecial, UInt<1>("h00")) - node T_817 = and(T_816, isSpecialC) - node T_818 = and(T_817, opSignC) - node T_819 = or(T_814, T_818) - node T_821 = eq(mulSpecial, UInt<1>("h00")) - node T_822 = and(T_821, notSpecial_addZeros) - node T_823 = and(T_822, doSubMags) - node T_825 = and(T_823, UInt<1>("h00")) - node T_826 = or(T_819, T_825) - node T_827 = and(commonCase, signY) - node signOut = or(T_826, T_827) - node T_831 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) - node T_832 = not(T_831) - node T_833 = and(expY, T_832) - node T_836 = mux(isSatOut, UInt<8>("h080"), UInt<9>("h00")) - node T_837 = not(T_836) - node T_838 = and(T_833, T_837) - node T_841 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) - node T_842 = not(T_841) - node T_843 = and(T_838, T_842) - node T_846 = mux(isSatOut, UInt<9>("h017f"), UInt<9>("h00")) - node T_847 = or(T_843, T_846) - node T_850 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) - node T_851 = or(T_847, T_850) - node T_854 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) - node expOut = or(T_851, T_854) - node T_856 = or(isNaNOut, isSatOut) - node T_858 = subw(UInt<23>("h00"), T_856) - node fractOut = or(fractY, T_858) - node T_860 = cat(expOut, fractOut) - node T_861 = cat(signOut, T_860) - out := T_861 - node T_863 = cat(invalid, UInt<1>("h00")) - node T_864 = cat(underflow, inexact) - node T_865 = cat(overflow, T_864) - node T_866 = cat(T_863, T_865) - exceptionFlags := T_866 - - module FPUFMAPipe : - output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - input clock : Clock - input reset : UInt<1> - - out.bits.exc := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.valid := UInt<1>("h00") - node one = shl(UInt<1>("h01"), 31) - node T_136 = bit(in.bits.in1, 32) - node T_137 = bit(in.bits.in2, 32) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 32) - reg valid : UInt<1>, clock, reset - valid := in.valid - reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset - when in.valid : - in_1 <> in.bits - node T_187 = bit(in.bits.cmd, 1) - node T_188 = or(in.bits.ren3, in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bit(in.bits.cmd, 0) - node T_191 = cat(T_189, T_190) - in_1.cmd := T_191 - when in.bits.swap23 : - in_1.in2 := one - skip - node T_192 = or(in.bits.ren3, in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h00")) - when T_194 : - in_1.in3 := zero - skip - skip - inst fma of mulAddSubRecodedFloatN - fma.roundingMode := UInt<1>("h00") - fma.c := UInt<1>("h00") - fma.b := UInt<1>("h00") - fma.a := UInt<1>("h00") - fma.op := UInt<1>("h00") - fma.reset := UInt<1>("h00") - fma.clock := clock - fma.reset := reset - fma.op := in_1.cmd - fma.roundingMode := in_1.rm - fma.a := in_1.in1 - fma.b := in_1.in2 - fma.c := in_1.in3 - wire res : {data : UInt<65>, exc : UInt<5>} - res.exc := UInt<1>("h00") - res.data := UInt<1>("h00") - res.data := fma.out - res.exc := fma.exceptionFlags - reg T_211 : UInt<1>, clock, reset - onreset T_211 := UInt<1>("h00") - T_211 := valid - reg T_212 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when valid : - T_212 <> res - skip - wire T_223 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_223.bits.exc := UInt<1>("h00") - T_223.bits.data := UInt<1>("h00") - T_223.valid := UInt<1>("h00") - T_223.valid := T_211 - T_223.bits <> T_212 - out <> T_223 - - module mulAddSubRecodedFloatN_71 : - output exceptionFlags : UInt<5> - output out : UInt<65> - input roundingMode : UInt<2> - input c : UInt<65> - input b : UInt<65> - input a : UInt<65> - input op : UInt<2> - input clock : Clock - input reset : UInt<1> - - exceptionFlags := UInt<1>("h00") - out := UInt<1>("h00") - node signA = bit(a, 64) - node expA = bits(a, 63, 52) - node fractA = bits(a, 51, 0) - node T_14 = bits(expA, 11, 9) - node isZeroA = eq(T_14, UInt<1>("h00")) - node T_17 = bits(expA, 11, 10) - node isSpecialA = eq(T_17, UInt<2>("h03")) - node T_20 = bit(expA, 9) - node T_22 = eq(T_20, UInt<1>("h00")) - node isInfA = and(isSpecialA, T_22) - node T_24 = bit(expA, 9) - node isNaNA = and(isSpecialA, T_24) - node T_26 = bit(fractA, 51) - node T_28 = eq(T_26, UInt<1>("h00")) - node isSigNaNA = and(isNaNA, T_28) - node T_31 = eq(isZeroA, UInt<1>("h00")) - node sigA = cat(T_31, fractA) - node signB = bit(b, 64) - node expB = bits(b, 63, 52) - node fractB = bits(b, 51, 0) - node T_36 = bits(expB, 11, 9) - node isZeroB = eq(T_36, UInt<1>("h00")) - node T_39 = bits(expB, 11, 10) - node isSpecialB = eq(T_39, UInt<2>("h03")) - node T_42 = bit(expB, 9) - node T_44 = eq(T_42, UInt<1>("h00")) - node isInfB = and(isSpecialB, T_44) - node T_46 = bit(expB, 9) - node isNaNB = and(isSpecialB, T_46) - node T_48 = bit(fractB, 51) - node T_50 = eq(T_48, UInt<1>("h00")) - node isSigNaNB = and(isNaNB, T_50) - node T_53 = eq(isZeroB, UInt<1>("h00")) - node sigB = cat(T_53, fractB) - node T_55 = bit(c, 64) - node T_56 = bit(op, 0) - node opSignC = xor(T_55, T_56) - node expC = bits(c, 63, 52) - node fractC = bits(c, 51, 0) - node T_60 = bits(expC, 11, 9) - node isZeroC = eq(T_60, UInt<1>("h00")) - node T_63 = bits(expC, 11, 10) - node isSpecialC = eq(T_63, UInt<2>("h03")) - node T_66 = bit(expC, 9) - node T_68 = eq(T_66, UInt<1>("h00")) - node isInfC = and(isSpecialC, T_68) - node T_70 = bit(expC, 9) - node isNaNC = and(isSpecialC, T_70) - node T_72 = bit(fractC, 51) - node T_74 = eq(T_72, UInt<1>("h00")) - node isSigNaNC = and(isNaNC, T_74) - node T_77 = eq(isZeroC, UInt<1>("h00")) - node sigC = cat(T_77, fractC) - node roundingMode_nearest_even = eq(roundingMode, UInt<2>("h00")) - node roundingMode_minMag = eq(roundingMode, UInt<2>("h01")) - node roundingMode_min = eq(roundingMode, UInt<2>("h02")) - node roundingMode_max = eq(roundingMode, UInt<2>("h03")) - node T_83 = xor(signA, signB) - node T_84 = bit(op, 1) - node signProd = xor(T_83, T_84) - node isZeroProd = or(isZeroA, isZeroB) - node T_87 = bit(expB, 11) - node T_89 = eq(T_87, UInt<1>("h00")) - node T_91 = subw(UInt<3>("h00"), T_89) - node T_92 = bits(expB, 10, 0) - node T_93 = cat(T_91, T_92) - node T_94 = addw(T_93, expA) - node sExpAlignedProd = addw(T_94, UInt<6>("h038")) - node doSubMags = xor(signProd, opSignC) - node sNatCAlignDist = subw(sExpAlignedProd, expC) - node T_99 = bit(sNatCAlignDist, 13) - node CAlignDist_floor = or(isZeroProd, T_99) - node T_101 = bits(sNatCAlignDist, 12, 0) - node T_103 = eq(T_101, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_103) - node T_106 = eq(isZeroC, UInt<1>("h00")) - node T_107 = bits(sNatCAlignDist, 12, 0) - node T_109 = lt(T_107, UInt<6>("h036")) - node T_110 = or(CAlignDist_floor, T_109) - node isCDominant = and(T_106, T_110) - node T_113 = bits(sNatCAlignDist, 12, 0) - node T_115 = lt(T_113, UInt<8>("h0a1")) - node T_117 = mux(T_115, sNatCAlignDist, UInt<8>("h0a1")) - node T_118 = mux(CAlignDist_floor, UInt<1>("h00"), T_117) - node CAlignDist = bits(T_118, 7, 0) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_122 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) - node T_123 = bits(T_122, 147, 95) - node T_124 = bits(T_123, 31, 0) - node T_127 = shl(UInt<16>("h0ffff"), 16) - node T_128 = xor(UInt<32>("h0ffffffff"), T_127) - node T_129 = shr(T_124, 16) - node T_130 = and(T_129, T_128) - node T_131 = bits(T_124, 15, 0) - node T_132 = shl(T_131, 16) - node T_133 = not(T_128) - node T_134 = and(T_132, T_133) - node T_135 = or(T_130, T_134) - node T_136 = bits(T_128, 23, 0) - node T_137 = shl(T_136, 8) - node T_138 = xor(T_128, T_137) - node T_139 = shr(T_135, 8) - node T_140 = and(T_139, T_138) - node T_141 = bits(T_135, 23, 0) - node T_142 = shl(T_141, 8) - node T_143 = not(T_138) - node T_144 = and(T_142, T_143) - node T_145 = or(T_140, T_144) - node T_146 = bits(T_138, 27, 0) - node T_147 = shl(T_146, 4) - node T_148 = xor(T_138, T_147) - node T_149 = shr(T_145, 4) - node T_150 = and(T_149, T_148) - node T_151 = bits(T_145, 27, 0) - node T_152 = shl(T_151, 4) - node T_153 = not(T_148) - node T_154 = and(T_152, T_153) - node T_155 = or(T_150, T_154) - node T_156 = bits(T_148, 29, 0) - node T_157 = shl(T_156, 2) - node T_158 = xor(T_148, T_157) - node T_159 = shr(T_155, 2) - node T_160 = and(T_159, T_158) - node T_161 = bits(T_155, 29, 0) - node T_162 = shl(T_161, 2) - node T_163 = not(T_158) - node T_164 = and(T_162, T_163) - node T_165 = or(T_160, T_164) - node T_166 = bits(T_158, 30, 0) - node T_167 = shl(T_166, 1) - node T_168 = xor(T_158, T_167) - node T_169 = shr(T_165, 1) - node T_170 = and(T_169, T_168) - node T_171 = bits(T_165, 30, 0) - node T_172 = shl(T_171, 1) - node T_173 = not(T_168) - node T_174 = and(T_172, T_173) - node T_175 = or(T_170, T_174) - node T_176 = bits(T_123, 52, 32) - node T_177 = bits(T_176, 15, 0) - node T_180 = shl(UInt<8>("h0ff"), 8) - node T_181 = xor(UInt<16>("h0ffff"), T_180) - node T_182 = shr(T_177, 8) - node T_183 = and(T_182, T_181) - node T_184 = bits(T_177, 7, 0) - node T_185 = shl(T_184, 8) - node T_186 = not(T_181) - node T_187 = and(T_185, T_186) - node T_188 = or(T_183, T_187) - node T_189 = bits(T_181, 11, 0) - node T_190 = shl(T_189, 4) - node T_191 = xor(T_181, T_190) - node T_192 = shr(T_188, 4) - node T_193 = and(T_192, T_191) - node T_194 = bits(T_188, 11, 0) - node T_195 = shl(T_194, 4) - node T_196 = not(T_191) - node T_197 = and(T_195, T_196) - node T_198 = or(T_193, T_197) - node T_199 = bits(T_191, 13, 0) - node T_200 = shl(T_199, 2) - node T_201 = xor(T_191, T_200) - node T_202 = shr(T_198, 2) - node T_203 = and(T_202, T_201) - node T_204 = bits(T_198, 13, 0) - node T_205 = shl(T_204, 2) - node T_206 = not(T_201) - node T_207 = and(T_205, T_206) - node T_208 = or(T_203, T_207) - node T_209 = bits(T_201, 14, 0) - node T_210 = shl(T_209, 1) - node T_211 = xor(T_201, T_210) - node T_212 = shr(T_208, 1) - node T_213 = and(T_212, T_211) - node T_214 = bits(T_208, 14, 0) - node T_215 = shl(T_214, 1) - node T_216 = not(T_211) - node T_217 = and(T_215, T_216) - node T_218 = or(T_213, T_217) - node T_219 = bits(T_176, 20, 16) - node T_220 = bits(T_219, 3, 0) - node T_221 = bits(T_220, 1, 0) - node T_222 = bits(T_221, 0, 0) - node T_223 = bits(T_221, 1, 1) - node T_224 = cat(T_222, T_223) - node T_225 = bits(T_220, 3, 2) - node T_226 = bits(T_225, 0, 0) - node T_227 = bits(T_225, 1, 1) - node T_228 = cat(T_226, T_227) - node T_229 = cat(T_224, T_228) - node T_230 = bits(T_219, 4, 4) - node T_231 = cat(T_229, T_230) - node T_232 = cat(T_218, T_231) - node CExtraMask = cat(T_175, T_232) - node T_234 = not(sigC) - node negSigC = mux(doSubMags, T_234, sigC) - node T_237 = subw(UInt<108>("h00"), doSubMags) - node T_238 = cat(negSigC, T_237) - node T_239 = cat(doSubMags, T_238) - node T_240 = asSInt(T_239) - node T_241 = dshr(T_240, CAlignDist) - node T_242 = and(sigC, CExtraMask) - node T_244 = neq(T_242, UInt<1>("h00")) - node T_245 = xor(T_244, doSubMags) - node T_246 = asUInt(T_241) - node T_247 = cat(T_246, T_245) - node alignedNegSigC = bits(T_247, 161, 0) - node T_249 = mul(sigA, sigB) - node T_250 = shl(T_249, 1) - node sigSum = addw(T_250, alignedNegSigC) - node T_253 = bits(sigSum, 108, 1) - node T_254 = xor(UInt<108>("h00"), T_253) - node T_255 = or(UInt<108>("h00"), T_253) - node T_256 = shl(T_255, 1) - node T_257 = xor(T_254, T_256) - node T_258 = bit(T_257, 107) - node T_260 = bit(T_257, 106) - node T_262 = bit(T_257, 105) - node T_264 = bit(T_257, 104) - node T_266 = bit(T_257, 103) - node T_268 = bit(T_257, 102) - node T_270 = bit(T_257, 101) - node T_272 = bit(T_257, 100) - node T_274 = bit(T_257, 99) - node T_276 = bit(T_257, 98) - node T_278 = bit(T_257, 97) - node T_280 = bit(T_257, 96) - node T_282 = bit(T_257, 95) - node T_284 = bit(T_257, 94) - node T_286 = bit(T_257, 93) - node T_288 = bit(T_257, 92) - node T_290 = bit(T_257, 91) - node T_292 = bit(T_257, 90) - node T_294 = bit(T_257, 89) - node T_296 = bit(T_257, 88) - node T_298 = bit(T_257, 87) - node T_300 = bit(T_257, 86) - node T_302 = bit(T_257, 85) - node T_304 = bit(T_257, 84) - node T_306 = bit(T_257, 83) - node T_308 = bit(T_257, 82) - node T_310 = bit(T_257, 81) - node T_312 = bit(T_257, 80) - node T_314 = bit(T_257, 79) - node T_316 = bit(T_257, 78) - node T_318 = bit(T_257, 77) - node T_320 = bit(T_257, 76) - node T_322 = bit(T_257, 75) - node T_324 = bit(T_257, 74) - node T_326 = bit(T_257, 73) - node T_328 = bit(T_257, 72) - node T_330 = bit(T_257, 71) - node T_332 = bit(T_257, 70) - node T_334 = bit(T_257, 69) - node T_336 = bit(T_257, 68) - node T_338 = bit(T_257, 67) - node T_340 = bit(T_257, 66) - node T_342 = bit(T_257, 65) - node T_344 = bit(T_257, 64) - node T_346 = bit(T_257, 63) - node T_348 = bit(T_257, 62) - node T_350 = bit(T_257, 61) - node T_352 = bit(T_257, 60) - node T_354 = bit(T_257, 59) - node T_356 = bit(T_257, 58) - node T_358 = bit(T_257, 57) - node T_360 = bit(T_257, 56) - node T_362 = bit(T_257, 55) - node T_364 = bit(T_257, 54) - node T_366 = bit(T_257, 53) - node T_368 = bit(T_257, 52) - node T_370 = bit(T_257, 51) - node T_372 = bit(T_257, 50) - node T_374 = bit(T_257, 49) - node T_376 = bit(T_257, 48) - node T_378 = bit(T_257, 47) - node T_380 = bit(T_257, 46) - node T_382 = bit(T_257, 45) - node T_384 = bit(T_257, 44) - node T_386 = bit(T_257, 43) - node T_388 = bit(T_257, 42) - node T_390 = bit(T_257, 41) - node T_392 = bit(T_257, 40) - node T_394 = bit(T_257, 39) - node T_396 = bit(T_257, 38) - node T_398 = bit(T_257, 37) - node T_400 = bit(T_257, 36) - node T_402 = bit(T_257, 35) - node T_404 = bit(T_257, 34) - node T_406 = bit(T_257, 33) - node T_408 = bit(T_257, 32) - node T_410 = bit(T_257, 31) - node T_412 = bit(T_257, 30) - node T_414 = bit(T_257, 29) - node T_416 = bit(T_257, 28) - node T_418 = bit(T_257, 27) - node T_420 = bit(T_257, 26) - node T_422 = bit(T_257, 25) - node T_424 = bit(T_257, 24) - node T_426 = bit(T_257, 23) - node T_428 = bit(T_257, 22) - node T_430 = bit(T_257, 21) - node T_432 = bit(T_257, 20) - node T_434 = bit(T_257, 19) - node T_436 = bit(T_257, 18) - node T_438 = bit(T_257, 17) - node T_440 = bit(T_257, 16) - node T_442 = bit(T_257, 15) - node T_444 = bit(T_257, 14) - node T_446 = bit(T_257, 13) - node T_448 = bit(T_257, 12) - node T_450 = bit(T_257, 11) - node T_452 = bit(T_257, 10) - node T_454 = bit(T_257, 9) - node T_456 = bit(T_257, 8) - node T_458 = bit(T_257, 7) - node T_460 = bit(T_257, 6) - node T_462 = bit(T_257, 5) - node T_464 = bit(T_257, 4) - node T_466 = bit(T_257, 3) - node T_468 = bit(T_257, 2) - node T_470 = bit(T_257, 1) - node T_472 = bit(T_257, 0) - node T_474 = mux(T_470, UInt<8>("h09f"), UInt<8>("h0a0")) - node T_475 = mux(T_468, UInt<8>("h09e"), T_474) - node T_476 = mux(T_466, UInt<8>("h09d"), T_475) - node T_477 = mux(T_464, UInt<8>("h09c"), T_476) - node T_478 = mux(T_462, UInt<8>("h09b"), T_477) - node T_479 = mux(T_460, UInt<8>("h09a"), T_478) - node T_480 = mux(T_458, UInt<8>("h099"), T_479) - node T_481 = mux(T_456, UInt<8>("h098"), T_480) - node T_482 = mux(T_454, UInt<8>("h097"), T_481) - node T_483 = mux(T_452, UInt<8>("h096"), T_482) - node T_484 = mux(T_450, UInt<8>("h095"), T_483) - node T_485 = mux(T_448, UInt<8>("h094"), T_484) - node T_486 = mux(T_446, UInt<8>("h093"), T_485) - node T_487 = mux(T_444, UInt<8>("h092"), T_486) - node T_488 = mux(T_442, UInt<8>("h091"), T_487) - node T_489 = mux(T_440, UInt<8>("h090"), T_488) - node T_490 = mux(T_438, UInt<8>("h08f"), T_489) - node T_491 = mux(T_436, UInt<8>("h08e"), T_490) - node T_492 = mux(T_434, UInt<8>("h08d"), T_491) - node T_493 = mux(T_432, UInt<8>("h08c"), T_492) - node T_494 = mux(T_430, UInt<8>("h08b"), T_493) - node T_495 = mux(T_428, UInt<8>("h08a"), T_494) - node T_496 = mux(T_426, UInt<8>("h089"), T_495) - node T_497 = mux(T_424, UInt<8>("h088"), T_496) - node T_498 = mux(T_422, UInt<8>("h087"), T_497) - node T_499 = mux(T_420, UInt<8>("h086"), T_498) - node T_500 = mux(T_418, UInt<8>("h085"), T_499) - node T_501 = mux(T_416, UInt<8>("h084"), T_500) - node T_502 = mux(T_414, UInt<8>("h083"), T_501) - node T_503 = mux(T_412, UInt<8>("h082"), T_502) - node T_504 = mux(T_410, UInt<8>("h081"), T_503) - node T_505 = mux(T_408, UInt<8>("h080"), T_504) - node T_506 = mux(T_406, UInt<8>("h07f"), T_505) - node T_507 = mux(T_404, UInt<8>("h07e"), T_506) - node T_508 = mux(T_402, UInt<8>("h07d"), T_507) - node T_509 = mux(T_400, UInt<8>("h07c"), T_508) - node T_510 = mux(T_398, UInt<8>("h07b"), T_509) - node T_511 = mux(T_396, UInt<8>("h07a"), T_510) - node T_512 = mux(T_394, UInt<8>("h079"), T_511) - node T_513 = mux(T_392, UInt<8>("h078"), T_512) - node T_514 = mux(T_390, UInt<8>("h077"), T_513) - node T_515 = mux(T_388, UInt<8>("h076"), T_514) - node T_516 = mux(T_386, UInt<8>("h075"), T_515) - node T_517 = mux(T_384, UInt<8>("h074"), T_516) - node T_518 = mux(T_382, UInt<8>("h073"), T_517) - node T_519 = mux(T_380, UInt<8>("h072"), T_518) - node T_520 = mux(T_378, UInt<8>("h071"), T_519) - node T_521 = mux(T_376, UInt<8>("h070"), T_520) - node T_522 = mux(T_374, UInt<8>("h06f"), T_521) - node T_523 = mux(T_372, UInt<8>("h06e"), T_522) - node T_524 = mux(T_370, UInt<8>("h06d"), T_523) - node T_525 = mux(T_368, UInt<8>("h06c"), T_524) - node T_526 = mux(T_366, UInt<8>("h06b"), T_525) - node T_527 = mux(T_364, UInt<8>("h06a"), T_526) - node T_528 = mux(T_362, UInt<8>("h069"), T_527) - node T_529 = mux(T_360, UInt<8>("h068"), T_528) - node T_530 = mux(T_358, UInt<8>("h067"), T_529) - node T_531 = mux(T_356, UInt<8>("h066"), T_530) - node T_532 = mux(T_354, UInt<8>("h065"), T_531) - node T_533 = mux(T_352, UInt<8>("h064"), T_532) - node T_534 = mux(T_350, UInt<8>("h063"), T_533) - node T_535 = mux(T_348, UInt<8>("h062"), T_534) - node T_536 = mux(T_346, UInt<8>("h061"), T_535) - node T_537 = mux(T_344, UInt<8>("h060"), T_536) - node T_538 = mux(T_342, UInt<8>("h05f"), T_537) - node T_539 = mux(T_340, UInt<8>("h05e"), T_538) - node T_540 = mux(T_338, UInt<8>("h05d"), T_539) - node T_541 = mux(T_336, UInt<8>("h05c"), T_540) - node T_542 = mux(T_334, UInt<8>("h05b"), T_541) - node T_543 = mux(T_332, UInt<8>("h05a"), T_542) - node T_544 = mux(T_330, UInt<8>("h059"), T_543) - node T_545 = mux(T_328, UInt<8>("h058"), T_544) - node T_546 = mux(T_326, UInt<8>("h057"), T_545) - node T_547 = mux(T_324, UInt<8>("h056"), T_546) - node T_548 = mux(T_322, UInt<8>("h055"), T_547) - node T_549 = mux(T_320, UInt<8>("h054"), T_548) - node T_550 = mux(T_318, UInt<8>("h053"), T_549) - node T_551 = mux(T_316, UInt<8>("h052"), T_550) - node T_552 = mux(T_314, UInt<8>("h051"), T_551) - node T_553 = mux(T_312, UInt<8>("h050"), T_552) - node T_554 = mux(T_310, UInt<8>("h04f"), T_553) - node T_555 = mux(T_308, UInt<8>("h04e"), T_554) - node T_556 = mux(T_306, UInt<8>("h04d"), T_555) - node T_557 = mux(T_304, UInt<8>("h04c"), T_556) - node T_558 = mux(T_302, UInt<8>("h04b"), T_557) - node T_559 = mux(T_300, UInt<8>("h04a"), T_558) - node T_560 = mux(T_298, UInt<8>("h049"), T_559) - node T_561 = mux(T_296, UInt<8>("h048"), T_560) - node T_562 = mux(T_294, UInt<8>("h047"), T_561) - node T_563 = mux(T_292, UInt<8>("h046"), T_562) - node T_564 = mux(T_290, UInt<8>("h045"), T_563) - node T_565 = mux(T_288, UInt<8>("h044"), T_564) - node T_566 = mux(T_286, UInt<8>("h043"), T_565) - node T_567 = mux(T_284, UInt<8>("h042"), T_566) - node T_568 = mux(T_282, UInt<8>("h041"), T_567) - node T_569 = mux(T_280, UInt<8>("h040"), T_568) - node T_570 = mux(T_278, UInt<8>("h03f"), T_569) - node T_571 = mux(T_276, UInt<8>("h03e"), T_570) - node T_572 = mux(T_274, UInt<8>("h03d"), T_571) - node T_573 = mux(T_272, UInt<8>("h03c"), T_572) - node T_574 = mux(T_270, UInt<8>("h03b"), T_573) - node T_575 = mux(T_268, UInt<8>("h03a"), T_574) - node T_576 = mux(T_266, UInt<8>("h039"), T_575) - node T_577 = mux(T_264, UInt<8>("h038"), T_576) - node T_578 = mux(T_262, UInt<8>("h037"), T_577) - node T_579 = mux(T_260, UInt<8>("h036"), T_578) - node estNormPos_dist = mux(T_258, UInt<8>("h035"), T_579) - node T_581 = bits(sigSum, 75, 44) - node T_583 = neq(T_581, UInt<1>("h00")) - node T_584 = bits(sigSum, 43, 0) - node T_586 = neq(T_584, UInt<1>("h00")) - node firstReduceSigSum = cat(T_583, T_586) - node notSigSum = not(sigSum) - node T_589 = bits(notSigSum, 75, 44) - node T_591 = neq(T_589, UInt<1>("h00")) - node T_592 = bits(notSigSum, 43, 0) - node T_594 = neq(T_592, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_591, T_594) - node T_596 = or(CAlignDist_0, doSubMags) - node T_598 = subw(CAlignDist, UInt<1>("h01")) - node T_599 = bits(T_598, 5, 0) - node CDom_estNormDist = mux(T_596, CAlignDist, T_599) - node T_601 = not(doSubMags) - node T_602 = bit(CDom_estNormDist, 5) - node T_603 = not(T_602) - node T_604 = and(T_601, T_603) - node T_605 = asSInt(T_604) - node T_606 = bits(sigSum, 161, 76) - node T_608 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_609 = cat(T_606, T_608) - node T_610 = asSInt(T_609) - node T_611 = and(T_605, T_610) - node T_612 = not(doSubMags) - node T_613 = bit(CDom_estNormDist, 5) - node T_614 = and(T_612, T_613) - node T_615 = asSInt(T_614) - node T_616 = bits(sigSum, 129, 44) - node T_617 = bit(firstReduceSigSum, 0) - node T_618 = cat(T_616, T_617) - node T_619 = asSInt(T_618) - node T_620 = and(T_615, T_619) - node T_621 = or(T_611, T_620) - node T_622 = bit(CDom_estNormDist, 5) - node T_623 = not(T_622) - node T_624 = and(doSubMags, T_623) - node T_625 = asSInt(T_624) - node T_626 = bits(notSigSum, 161, 76) - node T_628 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_629 = cat(T_626, T_628) - node T_630 = asSInt(T_629) - node T_631 = and(T_625, T_630) - node T_632 = or(T_621, T_631) - node T_633 = bit(CDom_estNormDist, 5) - node T_634 = and(doSubMags, T_633) - node T_635 = asSInt(T_634) - node T_636 = bits(notSigSum, 129, 44) - node T_637 = bit(firstReduceNotSigSum, 0) - node T_638 = cat(T_636, T_637) - node T_639 = asSInt(T_638) - node T_640 = and(T_635, T_639) - node T_641 = or(T_632, T_640) - node CDom_firstNormAbsSigSum = asUInt(T_641) - node T_643 = bits(sigSum, 108, 44) - node T_644 = bit(firstReduceNotSigSum, 0) - node T_645 = not(T_644) - node T_646 = bit(firstReduceSigSum, 0) - node T_647 = mux(doSubMags, T_645, T_646) - node T_648 = cat(T_643, T_647) - node T_649 = bits(sigSum, 97, 1) - node T_650 = bit(estNormPos_dist, 4) - node T_651 = bits(sigSum, 1, 1) - node T_653 = subw(UInt<86>("h00"), doSubMags) - node T_654 = cat(T_651, T_653) - node T_655 = mux(T_650, T_648, T_654) - node T_656 = bits(sigSum, 97, 12) - node T_657 = bits(notSigSum, 11, 1) - node T_659 = eq(T_657, UInt<1>("h00")) - node T_660 = bits(sigSum, 11, 1) - node T_662 = neq(T_660, UInt<1>("h00")) - node T_663 = mux(doSubMags, T_659, T_662) - node T_664 = cat(T_656, T_663) - node T_665 = bit(estNormPos_dist, 6) - node T_666 = bit(estNormPos_dist, 5) - node T_667 = bits(sigSum, 65, 1) - node T_669 = subw(UInt<22>("h00"), doSubMags) - node T_670 = cat(T_667, T_669) - node T_671 = mux(T_666, T_670, T_664) - node T_672 = bit(estNormPos_dist, 5) - node T_673 = bits(sigSum, 33, 1) - node T_675 = subw(UInt<54>("h00"), doSubMags) - node T_676 = cat(T_673, T_675) - node T_677 = mux(T_672, T_655, T_676) - node notCDom_pos_firstNormAbsSigSum = mux(T_665, T_671, T_677) - node T_679 = bits(notSigSum, 107, 44) - node T_680 = bit(firstReduceNotSigSum, 0) - node T_681 = cat(T_679, T_680) - node T_682 = bits(notSigSum, 97, 1) - node T_683 = bit(estNormPos_dist, 4) - node T_684 = bits(notSigSum, 2, 1) - node T_685 = shl(T_684, 86) - node T_686 = mux(T_683, T_681, T_685) - node T_687 = bits(notSigSum, 98, 12) - node T_688 = bits(notSigSum, 11, 1) - node T_690 = neq(T_688, UInt<1>("h00")) - node T_691 = cat(T_687, T_690) - node T_692 = bit(estNormPos_dist, 6) - node T_693 = bit(estNormPos_dist, 5) - node T_694 = bits(notSigSum, 66, 1) - node T_695 = shl(T_694, 22) - node T_696 = mux(T_693, T_695, T_691) - node T_697 = bit(estNormPos_dist, 5) - node T_698 = bits(notSigSum, 34, 1) - node T_699 = shl(T_698, 54) - node T_700 = mux(T_697, T_686, T_699) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_692, T_696, T_700) - node notCDom_signSigSum = bit(sigSum, 109) - node T_703 = not(isZeroC) - node T_704 = and(doSubMags, T_703) - node doNegSignSum = mux(isCDominant, T_704, notCDom_signSigSum) - node T_706 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(isCDominant, CDom_estNormDist, T_706) - node T_708 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_709 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_708, T_709) - node T_711 = not(isCDominant) - node T_712 = not(notCDom_signSigSum) - node T_713 = and(T_711, T_712) - node doIncrSig = and(T_713, doSubMags) - node estNormDist_5 = bits(estNormDist, 4, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_718 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) - node T_719 = bits(T_718, 31, 1) - node T_720 = bits(T_719, 15, 0) - node T_723 = shl(UInt<8>("h0ff"), 8) - node T_724 = xor(UInt<16>("h0ffff"), T_723) - node T_725 = shr(T_720, 8) - node T_726 = and(T_725, T_724) - node T_727 = bits(T_720, 7, 0) - node T_728 = shl(T_727, 8) - node T_729 = not(T_724) - node T_730 = and(T_728, T_729) - node T_731 = or(T_726, T_730) - node T_732 = bits(T_724, 11, 0) - node T_733 = shl(T_732, 4) - node T_734 = xor(T_724, T_733) - node T_735 = shr(T_731, 4) - node T_736 = and(T_735, T_734) - node T_737 = bits(T_731, 11, 0) - node T_738 = shl(T_737, 4) - node T_739 = not(T_734) - node T_740 = and(T_738, T_739) - node T_741 = or(T_736, T_740) - node T_742 = bits(T_734, 13, 0) - node T_743 = shl(T_742, 2) - node T_744 = xor(T_734, T_743) - node T_745 = shr(T_741, 2) - node T_746 = and(T_745, T_744) - node T_747 = bits(T_741, 13, 0) - node T_748 = shl(T_747, 2) - node T_749 = not(T_744) - node T_750 = and(T_748, T_749) - node T_751 = or(T_746, T_750) - node T_752 = bits(T_744, 14, 0) - node T_753 = shl(T_752, 1) - node T_754 = xor(T_744, T_753) - node T_755 = shr(T_751, 1) - node T_756 = and(T_755, T_754) - node T_757 = bits(T_751, 14, 0) - node T_758 = shl(T_757, 1) - node T_759 = not(T_754) - node T_760 = and(T_758, T_759) - node T_761 = or(T_756, T_760) - node T_762 = bits(T_719, 30, 16) - node T_763 = bits(T_762, 7, 0) - node T_766 = shl(UInt<4>("h0f"), 4) - node T_767 = xor(UInt<8>("h0ff"), T_766) - node T_768 = shr(T_763, 4) - node T_769 = and(T_768, T_767) - node T_770 = bits(T_763, 3, 0) - node T_771 = shl(T_770, 4) - node T_772 = not(T_767) - node T_773 = and(T_771, T_772) - node T_774 = or(T_769, T_773) - node T_775 = bits(T_767, 5, 0) - node T_776 = shl(T_775, 2) - node T_777 = xor(T_767, T_776) - node T_778 = shr(T_774, 2) - node T_779 = and(T_778, T_777) - node T_780 = bits(T_774, 5, 0) - node T_781 = shl(T_780, 2) - node T_782 = not(T_777) - node T_783 = and(T_781, T_782) - node T_784 = or(T_779, T_783) - node T_785 = bits(T_777, 6, 0) - node T_786 = shl(T_785, 1) - node T_787 = xor(T_777, T_786) - node T_788 = shr(T_784, 1) - node T_789 = and(T_788, T_787) - node T_790 = bits(T_784, 6, 0) - node T_791 = shl(T_790, 1) - node T_792 = not(T_787) - node T_793 = and(T_791, T_792) - node T_794 = or(T_789, T_793) - node T_795 = bits(T_762, 14, 8) - node T_796 = bits(T_795, 3, 0) - node T_797 = bits(T_796, 1, 0) - node T_798 = bits(T_797, 0, 0) - node T_799 = bits(T_797, 1, 1) - node T_800 = cat(T_798, T_799) - node T_801 = bits(T_796, 3, 2) - node T_802 = bits(T_801, 0, 0) - node T_803 = bits(T_801, 1, 1) - node T_804 = cat(T_802, T_803) - node T_805 = cat(T_800, T_804) - node T_806 = bits(T_795, 6, 4) - node T_807 = bits(T_806, 1, 0) - node T_808 = bits(T_807, 0, 0) - node T_809 = bits(T_807, 1, 1) - node T_810 = cat(T_808, T_809) - node T_811 = bits(T_806, 2, 2) - node T_812 = cat(T_810, T_811) - node T_813 = cat(T_805, T_812) - node T_814 = cat(T_794, T_813) - node T_815 = cat(T_761, T_814) - node absSigSumExtraMask = cat(T_815, UInt<1>("h01")) - node T_818 = bits(cFirstNormAbsSigSum, 87, 1) - node T_819 = dshr(T_818, normTo2ShiftDist) - node T_820 = bits(cFirstNormAbsSigSum, 31, 0) - node T_821 = not(T_820) - node T_822 = and(T_821, absSigSumExtraMask) - node T_824 = eq(T_822, UInt<1>("h00")) - node T_825 = bits(cFirstNormAbsSigSum, 31, 0) - node T_826 = and(T_825, absSigSumExtraMask) - node T_828 = neq(T_826, UInt<1>("h00")) - node T_829 = mux(doIncrSig, T_824, T_828) - node T_830 = cat(T_819, T_829) - node sigX3 = bits(T_830, 56, 0) - node T_832 = bits(sigX3, 56, 55) - node sigX3Shift1 = eq(T_832, UInt<1>("h00")) - node sExpX3 = subw(sExpSum, estNormDist) - node T_836 = bits(sigX3, 56, 54) - node isZeroY = eq(T_836, UInt<1>("h00")) - node T_839 = not(isZeroY) - node T_840 = xor(signProd, doNegSignSum) - node signY = and(T_839, T_840) - node sExpX3_13 = bits(sExpX3, 12, 0) - node T_843 = bit(sExpX3, 13) - node T_845 = subw(UInt<56>("h00"), T_843) - node T_846 = not(sExpX3_13) - node T_848 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_846) - node T_849 = bits(T_848, 1027, 974) - node T_850 = bits(T_849, 31, 0) - node T_853 = shl(UInt<16>("h0ffff"), 16) - node T_854 = xor(UInt<32>("h0ffffffff"), T_853) - node T_855 = shr(T_850, 16) - node T_856 = and(T_855, T_854) - node T_857 = bits(T_850, 15, 0) - node T_858 = shl(T_857, 16) - node T_859 = not(T_854) - node T_860 = and(T_858, T_859) - node T_861 = or(T_856, T_860) - node T_862 = bits(T_854, 23, 0) - node T_863 = shl(T_862, 8) - node T_864 = xor(T_854, T_863) - node T_865 = shr(T_861, 8) - node T_866 = and(T_865, T_864) - node T_867 = bits(T_861, 23, 0) - node T_868 = shl(T_867, 8) - node T_869 = not(T_864) - node T_870 = and(T_868, T_869) - node T_871 = or(T_866, T_870) - node T_872 = bits(T_864, 27, 0) - node T_873 = shl(T_872, 4) - node T_874 = xor(T_864, T_873) - node T_875 = shr(T_871, 4) - node T_876 = and(T_875, T_874) - node T_877 = bits(T_871, 27, 0) - node T_878 = shl(T_877, 4) - node T_879 = not(T_874) - node T_880 = and(T_878, T_879) - node T_881 = or(T_876, T_880) - node T_882 = bits(T_874, 29, 0) - node T_883 = shl(T_882, 2) - node T_884 = xor(T_874, T_883) - node T_885 = shr(T_881, 2) - node T_886 = and(T_885, T_884) - node T_887 = bits(T_881, 29, 0) - node T_888 = shl(T_887, 2) - node T_889 = not(T_884) - node T_890 = and(T_888, T_889) - node T_891 = or(T_886, T_890) - node T_892 = bits(T_884, 30, 0) - node T_893 = shl(T_892, 1) - node T_894 = xor(T_884, T_893) - node T_895 = shr(T_891, 1) - node T_896 = and(T_895, T_894) - node T_897 = bits(T_891, 30, 0) - node T_898 = shl(T_897, 1) - node T_899 = not(T_894) - node T_900 = and(T_898, T_899) - node T_901 = or(T_896, T_900) - node T_902 = bits(T_849, 53, 32) - node T_903 = bits(T_902, 15, 0) - node T_906 = shl(UInt<8>("h0ff"), 8) - node T_907 = xor(UInt<16>("h0ffff"), T_906) - node T_908 = shr(T_903, 8) - node T_909 = and(T_908, T_907) - node T_910 = bits(T_903, 7, 0) - node T_911 = shl(T_910, 8) - node T_912 = not(T_907) - node T_913 = and(T_911, T_912) - node T_914 = or(T_909, T_913) - node T_915 = bits(T_907, 11, 0) - node T_916 = shl(T_915, 4) - node T_917 = xor(T_907, T_916) - node T_918 = shr(T_914, 4) - node T_919 = and(T_918, T_917) - node T_920 = bits(T_914, 11, 0) - node T_921 = shl(T_920, 4) - node T_922 = not(T_917) - node T_923 = and(T_921, T_922) - node T_924 = or(T_919, T_923) - node T_925 = bits(T_917, 13, 0) - node T_926 = shl(T_925, 2) - node T_927 = xor(T_917, T_926) - node T_928 = shr(T_924, 2) - node T_929 = and(T_928, T_927) - node T_930 = bits(T_924, 13, 0) - node T_931 = shl(T_930, 2) - node T_932 = not(T_927) - node T_933 = and(T_931, T_932) - node T_934 = or(T_929, T_933) - node T_935 = bits(T_927, 14, 0) - node T_936 = shl(T_935, 1) - node T_937 = xor(T_927, T_936) - node T_938 = shr(T_934, 1) - node T_939 = and(T_938, T_937) - node T_940 = bits(T_934, 14, 0) - node T_941 = shl(T_940, 1) - node T_942 = not(T_937) - node T_943 = and(T_941, T_942) - node T_944 = or(T_939, T_943) - node T_945 = bits(T_902, 21, 16) - node T_946 = bits(T_945, 3, 0) - node T_947 = bits(T_946, 1, 0) - node T_948 = bits(T_947, 0, 0) - node T_949 = bits(T_947, 1, 1) - node T_950 = cat(T_948, T_949) - node T_951 = bits(T_946, 3, 2) - node T_952 = bits(T_951, 0, 0) - node T_953 = bits(T_951, 1, 1) - node T_954 = cat(T_952, T_953) - node T_955 = cat(T_950, T_954) - node T_956 = bits(T_945, 5, 4) - node T_957 = bits(T_956, 0, 0) - node T_958 = bits(T_956, 1, 1) - node T_959 = cat(T_957, T_958) - node T_960 = cat(T_955, T_959) - node T_961 = cat(T_944, T_960) - node T_962 = cat(T_901, T_961) - node T_963 = bit(sigX3, 55) - node T_964 = or(T_962, T_963) - node T_966 = cat(T_964, UInt<2>("h03")) - node roundMask = or(T_845, T_966) - node T_968 = shr(roundMask, 1) - node T_969 = not(T_968) - node roundPosMask = and(T_969, roundMask) - node T_971 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_971, UInt<1>("h00")) - node T_974 = shr(roundMask, 1) - node T_975 = and(sigX3, T_974) - node anyRoundExtra = neq(T_975, UInt<1>("h00")) - node T_978 = not(sigX3) - node T_979 = shr(roundMask, 1) - node T_980 = and(T_978, T_979) - node allRoundExtra = eq(T_980, UInt<1>("h00")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_986 = not(doIncrSig) - node T_987 = and(T_986, roundingMode_nearest_even) - node T_988 = and(T_987, roundPosBit) - node T_989 = and(T_988, anyRoundExtra) - node T_990 = not(doIncrSig) - node T_991 = and(T_990, roundDirectUp) - node T_992 = and(T_991, anyRound) - node T_993 = or(T_989, T_992) - node T_994 = and(doIncrSig, allRound) - node T_995 = or(T_993, T_994) - node T_996 = and(doIncrSig, roundingMode_nearest_even) - node T_997 = and(T_996, roundPosBit) - node T_998 = or(T_995, T_997) - node T_999 = and(doIncrSig, roundDirectUp) - node roundUp = or(T_998, T_999) - node T_1001 = not(roundPosBit) - node T_1002 = and(roundingMode_nearest_even, T_1001) - node T_1003 = and(T_1002, allRoundExtra) - node T_1004 = and(roundingMode_nearest_even, roundPosBit) - node T_1005 = not(anyRoundExtra) - node T_1006 = and(T_1004, T_1005) - node roundEven = mux(doIncrSig, T_1003, T_1006) - node T_1008 = not(allRound) - node roundInexact = mux(doIncrSig, T_1008, anyRound) - node T_1010 = or(sigX3, roundMask) - node T_1011 = shr(T_1010, 2) - node T_1013 = addw(T_1011, UInt<1>("h01")) - node roundUp_sigY3 = bits(T_1013, 54, 0) - node T_1015 = not(roundUp) - node T_1016 = not(roundEven) - node T_1017 = and(T_1015, T_1016) - node T_1018 = not(roundMask) - node T_1019 = and(sigX3, T_1018) - node T_1020 = shr(T_1019, 2) - node T_1022 = mux(T_1017, T_1020, UInt<1>("h00")) - node T_1024 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) - node T_1025 = or(T_1022, T_1024) - node T_1026 = shr(roundMask, 1) - node T_1027 = not(T_1026) - node T_1028 = and(roundUp_sigY3, T_1027) - node T_1030 = mux(roundEven, T_1028, UInt<1>("h00")) - node sigY3 = or(T_1025, T_1030) - node T_1032 = bit(sigY3, 54) - node T_1034 = addw(sExpX3, UInt<1>("h01")) - node T_1036 = mux(T_1032, T_1034, UInt<1>("h00")) - node T_1037 = bit(sigY3, 53) - node T_1039 = mux(T_1037, sExpX3, UInt<1>("h00")) - node T_1040 = or(T_1036, T_1039) - node T_1041 = bits(sigY3, 54, 53) - node T_1043 = eq(T_1041, UInt<1>("h00")) - node T_1045 = subw(sExpX3, UInt<1>("h01")) - node T_1047 = mux(T_1043, T_1045, UInt<1>("h00")) - node sExpY = or(T_1040, T_1047) - node expY = bits(sExpY, 11, 0) - node T_1050 = bits(sigY3, 51, 0) - node T_1051 = bits(sigY3, 52, 1) - node fractY = mux(sigX3Shift1, T_1050, T_1051) - node T_1053 = bits(sExpY, 12, 10) - node overflowY = eq(T_1053, UInt<2>("h03")) - node T_1056 = bit(sExpY, 12) - node T_1057 = bits(sExpY, 11, 0) - node T_1059 = lt(T_1057, UInt<10>("h03ce")) - node totalUnderflowY = or(T_1056, T_1059) - node T_1061 = bit(sExpX3, 13) - node T_1064 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) - node T_1065 = leq(sExpX3_13, T_1064) - node T_1066 = or(T_1061, T_1065) - node underflowY = and(roundInexact, T_1066) - node T_1068 = and(roundingMode_min, signY) - node T_1069 = or(roundingMode_nearest_even, T_1068) - node T_1070 = not(signY) - node T_1071 = and(roundingMode_max, T_1070) - node overflowY_roundMagUp = or(T_1069, T_1071) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(isZeroProd, isZeroC) - node T_1076 = not(addSpecial) - node T_1077 = not(notSpecial_addZeros) - node commonCase = and(T_1076, T_1077) - node T_1079 = and(isInfA, isZeroB) - node T_1080 = and(isZeroA, isInfB) - node T_1081 = or(T_1079, T_1080) - node T_1082 = not(isNaNA) - node T_1083 = not(isNaNB) - node T_1084 = and(T_1082, T_1083) - node T_1085 = or(isInfA, isInfB) - node T_1086 = and(T_1084, T_1085) - node T_1087 = and(T_1086, isInfC) - node T_1088 = and(T_1087, doSubMags) - node notSigNaN_invalid = or(T_1081, T_1088) - node T_1090 = or(isSigNaNA, isSigNaNB) - node T_1091 = or(T_1090, isSigNaNC) - node invalid = or(T_1091, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_1095 = and(commonCase, roundInexact) - node inexact = or(overflow, T_1095) - node T_1097 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_1097, totalUnderflowY) - node T_1099 = not(overflowY_roundMagUp) - node isSatOut = and(overflow, T_1099) - node T_1101 = or(isInfA, isInfB) - node T_1102 = or(T_1101, isInfC) - node T_1103 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_1102, T_1103) - node T_1105 = or(isNaNA, isNaNB) - node T_1106 = or(T_1105, isNaNC) - node isNaNOut = or(T_1106, notSigNaN_invalid) - node T_1109 = eq(doSubMags, UInt<1>("h00")) - node T_1110 = and(T_1109, opSignC) - node T_1112 = and(isNaNOut, UInt<1>("h01")) - node T_1113 = or(T_1110, T_1112) - node T_1115 = eq(isSpecialC, UInt<1>("h00")) - node T_1116 = and(mulSpecial, T_1115) - node T_1117 = and(T_1116, signProd) - node T_1118 = or(T_1113, T_1117) - node T_1120 = eq(mulSpecial, UInt<1>("h00")) - node T_1121 = and(T_1120, isSpecialC) - node T_1122 = and(T_1121, opSignC) - node T_1123 = or(T_1118, T_1122) - node T_1125 = eq(mulSpecial, UInt<1>("h00")) - node T_1126 = and(T_1125, notSpecial_addZeros) - node T_1127 = and(T_1126, doSubMags) - node T_1129 = and(T_1127, UInt<1>("h00")) - node T_1130 = or(T_1123, T_1129) - node T_1131 = and(commonCase, signY) - node signOut = or(T_1130, T_1131) - node T_1135 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) - node T_1136 = not(T_1135) - node T_1137 = and(expY, T_1136) - node T_1140 = mux(isSatOut, UInt<11>("h0400"), UInt<12>("h00")) - node T_1141 = not(T_1140) - node T_1142 = and(T_1137, T_1141) - node T_1145 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) - node T_1146 = not(T_1145) - node T_1147 = and(T_1142, T_1146) - node T_1150 = mux(isSatOut, UInt<12>("h0bff"), UInt<12>("h00")) - node T_1151 = or(T_1147, T_1150) - node T_1154 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) - node T_1155 = or(T_1151, T_1154) - node T_1158 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) - node expOut = or(T_1155, T_1158) - node T_1160 = or(isNaNOut, isSatOut) - node T_1162 = subw(UInt<52>("h00"), T_1160) - node fractOut = or(fractY, T_1162) - node T_1164 = cat(expOut, fractOut) - node T_1165 = cat(signOut, T_1164) - out := T_1165 - node T_1167 = cat(invalid, UInt<1>("h00")) - node T_1168 = cat(underflow, inexact) - node T_1169 = cat(overflow, T_1168) - node T_1170 = cat(T_1167, T_1169) - exceptionFlags := T_1170 - - module FPUFMAPipe_70 : - output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - input clock : Clock - input reset : UInt<1> - - out.bits.exc := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.valid := UInt<1>("h00") - node one = shl(UInt<1>("h01"), 63) - node T_136 = bit(in.bits.in1, 64) - node T_137 = bit(in.bits.in2, 64) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 64) - reg valid : UInt<1>, clock, reset - valid := in.valid - reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset - when in.valid : - in_1 <> in.bits - node T_187 = bit(in.bits.cmd, 1) - node T_188 = or(in.bits.ren3, in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bit(in.bits.cmd, 0) - node T_191 = cat(T_189, T_190) - in_1.cmd := T_191 - when in.bits.swap23 : - in_1.in2 := one - skip - node T_192 = or(in.bits.ren3, in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h00")) - when T_194 : - in_1.in3 := zero - skip - skip - inst fma of mulAddSubRecodedFloatN_71 - fma.roundingMode := UInt<1>("h00") - fma.c := UInt<1>("h00") - fma.b := UInt<1>("h00") - fma.a := UInt<1>("h00") - fma.op := UInt<1>("h00") - fma.reset := UInt<1>("h00") - fma.clock := clock - fma.reset := reset - fma.op := in_1.cmd - fma.roundingMode := in_1.rm - fma.a := in_1.in1 - fma.b := in_1.in2 - fma.c := in_1.in3 - wire res : {data : UInt<65>, exc : UInt<5>} - res.exc := UInt<1>("h00") - res.data := UInt<1>("h00") - res.data := fma.out - res.exc := fma.exceptionFlags - reg T_211 : UInt<1>, clock, reset - onreset T_211 := UInt<1>("h00") - T_211 := valid - reg T_212 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when valid : - T_212 <> res - skip - reg T_217 : UInt<1>, clock, reset - onreset T_217 := UInt<1>("h00") - T_217 := T_211 - reg T_218 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when T_211 : - T_218 <> T_212 - skip - wire T_229 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_229.bits.exc := UInt<1>("h00") - T_229.bits.data := UInt<1>("h00") - T_229.valid := UInt<1>("h00") - T_229.valid := T_217 - T_229.bits <> T_218 - out <> T_229 - - module recodedFloatNCompare : - output a_lt_b_invalid : UInt<1> - output a_eq_b_invalid : UInt<1> - output a_lt_b : UInt<1> - output a_eq_b : UInt<1> - input b : UInt<65> - input a : UInt<65> - input clock : Clock - input reset : UInt<1> - - a_lt_b_invalid := UInt<1>("h00") - a_eq_b_invalid := UInt<1>("h00") - a_lt_b := UInt<1>("h00") - a_eq_b := UInt<1>("h00") - node signA = bit(a, 64) - node expA = bits(a, 63, 52) - node sigA = bits(a, 51, 0) - node codeA = bits(expA, 11, 9) - node T_15 = neq(codeA, UInt<1>("h00")) - node isZeroA = eq(T_15, UInt<1>("h00")) - node T_18 = not(codeA) - node isNaNA = eq(T_18, UInt<1>("h00")) - node T_21 = bit(sigA, 51) - node T_23 = eq(T_21, UInt<1>("h00")) - node isSignalingNaNA = and(isNaNA, T_23) - node signB = bit(b, 64) - node expB = bits(b, 63, 52) - node sigB = bits(b, 51, 0) - node codeB = bits(expB, 11, 9) - node T_30 = neq(codeB, UInt<1>("h00")) - node isZeroB = eq(T_30, UInt<1>("h00")) - node T_33 = not(codeB) - node isNaNB = eq(T_33, UInt<1>("h00")) - node T_36 = bit(sigB, 51) - node T_38 = eq(T_36, UInt<1>("h00")) - node isSignalingNaNB = and(isNaNB, T_38) - node signEqual = eq(signA, signB) - node expEqual = eq(expA, expB) - node T_42 = eq(sigA, sigB) - node magEqual = and(expEqual, T_42) - node T_44 = lt(expA, expB) - node T_45 = lt(sigA, sigB) - node T_46 = and(expEqual, T_45) - node magLess = or(T_44, T_46) - node T_48 = or(isSignalingNaNA, isSignalingNaNB) - a_eq_b_invalid := T_48 - node T_49 = or(isNaNA, isNaNB) - a_lt_b_invalid := T_49 - node T_51 = eq(isNaNA, UInt<1>("h00")) - node T_52 = and(T_51, magEqual) - node T_53 = or(isZeroA, signEqual) - node T_54 = and(T_52, T_53) - a_eq_b := T_54 - node T_56 = eq(a_lt_b_invalid, UInt<1>("h00")) - node T_58 = eq(magLess, UInt<1>("h00")) - node T_59 = and(signA, T_58) - node T_61 = eq(magEqual, UInt<1>("h00")) - node T_62 = and(T_59, T_61) - node T_63 = and(isZeroA, isZeroB) - node T_65 = eq(T_63, UInt<1>("h00")) - node T_66 = mux(signA, T_65, magLess) - node T_67 = mux(signB, T_62, T_66) - node T_68 = and(T_56, T_67) - a_lt_b := T_68 - - module FPToInt : - output out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}} - output as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} - input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - input clock : Clock - input reset : UInt<1> - - out.bits.exc := UInt<1>("h00") - out.bits.toint := UInt<1>("h00") - out.bits.store := UInt<1>("h00") - out.bits.lt := UInt<1>("h00") - out.valid := UInt<1>("h00") - as_double.in3 := UInt<1>("h00") - as_double.in2 := UInt<1>("h00") - as_double.in1 := UInt<1>("h00") - as_double.typ := UInt<1>("h00") - as_double.rm := UInt<1>("h00") - as_double.wflags := UInt<1>("h00") - as_double.round := UInt<1>("h00") - as_double.sqrt := UInt<1>("h00") - as_double.div := UInt<1>("h00") - as_double.fma := UInt<1>("h00") - as_double.fastpipe := UInt<1>("h00") - as_double.toint := UInt<1>("h00") - as_double.fromint := UInt<1>("h00") - as_double.single := UInt<1>("h00") - as_double.swap23 := UInt<1>("h00") - as_double.swap12 := UInt<1>("h00") - as_double.ren3 := UInt<1>("h00") - as_double.ren2 := UInt<1>("h00") - as_double.ren1 := UInt<1>("h00") - as_double.wen := UInt<1>("h00") - as_double.ldst := UInt<1>("h00") - as_double.cmd := UInt<1>("h00") - reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset - reg valid : UInt<1>, clock, reset - valid := in.valid - when in.valid : - in_1 <> in.bits - node T_234 = eq(in.bits.ldst, UInt<1>("h00")) - node T_235 = and(in.bits.single, T_234) - node T_238 = and(in.bits.cmd, UInt<4>("h0c")) - node T_239 = eq(UInt<4>("h0c"), T_238) - node T_241 = eq(T_239, UInt<1>("h00")) - node T_242 = and(T_235, T_241) - when T_242 : - node T_244 = bit(in.bits.in1, 32) - node T_245 = bits(in.bits.in1, 22, 0) - node T_246 = bits(in.bits.in1, 31, 23) - node T_247 = bits(in.bits.in1, 31, 29) - node T_248 = bits(in.bits.in1, 30, 23) - node T_249 = not(T_247) - node T_251 = eq(T_249, UInt<1>("h00")) - node T_252 = bit(T_245, 22) - node T_254 = eq(T_252, UInt<1>("h00")) - node T_255 = and(T_251, T_254) - node T_257 = lt(T_247, UInt<1>("h01")) - node T_259 = lt(T_247, UInt<3>("h04")) - node T_261 = cat(UInt<3>("h07"), T_248) - node T_263 = lt(T_247, UInt<3>("h06")) - node T_265 = cat(UInt<4>("h08"), T_248) - node T_267 = lt(T_247, UInt<3>("h07")) - node T_270 = mux(T_267, UInt<12>("h0c00"), UInt<12>("h0e00")) - node T_271 = mux(T_263, T_265, T_270) - node T_272 = mux(T_259, T_261, T_271) - node T_273 = mux(T_257, T_248, T_272) - node T_275 = subw(UInt<52>("h00"), T_251) - node T_276 = shl(T_245, 29) - node T_277 = or(T_275, T_276) - node T_278 = cat(T_273, T_277) - node T_279 = cat(T_244, T_278) - node T_280 = shl(T_255, 4) - in_1.in1 := T_279 - node T_282 = bit(in.bits.in2, 32) - node T_283 = bits(in.bits.in2, 22, 0) - node T_284 = bits(in.bits.in2, 31, 23) - node T_285 = bits(in.bits.in2, 31, 29) - node T_286 = bits(in.bits.in2, 30, 23) - node T_287 = not(T_285) - node T_289 = eq(T_287, UInt<1>("h00")) - node T_290 = bit(T_283, 22) - node T_292 = eq(T_290, UInt<1>("h00")) - node T_293 = and(T_289, T_292) - node T_295 = lt(T_285, UInt<1>("h01")) - node T_297 = lt(T_285, UInt<3>("h04")) - node T_299 = cat(UInt<3>("h07"), T_286) - node T_301 = lt(T_285, UInt<3>("h06")) - node T_303 = cat(UInt<4>("h08"), T_286) - node T_305 = lt(T_285, UInt<3>("h07")) - node T_308 = mux(T_305, UInt<12>("h0c00"), UInt<12>("h0e00")) - node T_309 = mux(T_301, T_303, T_308) - node T_310 = mux(T_297, T_299, T_309) - node T_311 = mux(T_295, T_286, T_310) - node T_313 = subw(UInt<52>("h00"), T_289) - node T_314 = shl(T_283, 29) - node T_315 = or(T_313, T_314) - node T_316 = cat(T_311, T_315) - node T_317 = cat(T_282, T_316) - node T_318 = shl(T_293, 4) - in_1.in2 := T_317 - skip - skip - node T_319 = bit(in_1.in1, 32) - node T_320 = bits(in_1.in1, 31, 23) - node T_321 = bits(in_1.in1, 22, 0) - node T_322 = bits(T_320, 6, 0) - node T_324 = lt(T_322, UInt<2>("h02")) - node T_325 = bits(T_320, 8, 6) - node T_327 = eq(T_325, UInt<1>("h01")) - node T_328 = bits(T_320, 8, 7) - node T_330 = eq(T_328, UInt<1>("h01")) - node T_331 = and(T_330, T_324) - node T_332 = or(T_327, T_331) - node T_333 = bits(T_320, 8, 7) - node T_335 = eq(T_333, UInt<1>("h01")) - node T_337 = eq(T_324, UInt<1>("h00")) - node T_338 = and(T_335, T_337) - node T_339 = bits(T_320, 8, 7) - node T_341 = eq(T_339, UInt<2>("h02")) - node T_342 = or(T_338, T_341) - node T_343 = bits(T_320, 8, 7) - node T_345 = eq(T_343, UInt<2>("h03")) - node T_346 = bit(T_320, 6) - node T_347 = and(T_345, T_346) - node T_349 = bits(T_320, 4, 0) - node T_350 = subw(UInt<2>("h02"), T_349) - node T_352 = cat(UInt<1>("h01"), T_321) - node T_353 = dshr(T_352, T_350) - node T_354 = bits(T_353, 22, 0) - node T_355 = bits(T_320, 7, 0) - node T_357 = subw(T_355, UInt<8>("h081")) - node T_359 = subw(UInt<8>("h00"), T_345) - node T_360 = mux(T_342, T_357, T_359) - node T_361 = or(T_342, T_347) - node T_363 = mux(T_332, T_354, UInt<1>("h00")) - node T_364 = mux(T_361, T_321, T_363) - node T_365 = cat(T_360, T_364) - node unrec_s = cat(T_319, T_365) - node T_367 = bit(in_1.in1, 64) - node T_368 = bits(in_1.in1, 63, 52) - node T_369 = bits(in_1.in1, 51, 0) - node T_370 = bits(T_368, 9, 0) - node T_372 = lt(T_370, UInt<2>("h02")) - node T_373 = bits(T_368, 11, 9) - node T_375 = eq(T_373, UInt<1>("h01")) - node T_376 = bits(T_368, 11, 10) - node T_378 = eq(T_376, UInt<1>("h01")) - node T_379 = and(T_378, T_372) - node T_380 = or(T_375, T_379) - node T_381 = bits(T_368, 11, 10) - node T_383 = eq(T_381, UInt<1>("h01")) - node T_385 = eq(T_372, UInt<1>("h00")) - node T_386 = and(T_383, T_385) - node T_387 = bits(T_368, 11, 10) - node T_389 = eq(T_387, UInt<2>("h02")) - node T_390 = or(T_386, T_389) - node T_391 = bits(T_368, 11, 10) - node T_393 = eq(T_391, UInt<2>("h03")) - node T_394 = bit(T_368, 9) - node T_395 = and(T_393, T_394) - node T_397 = bits(T_368, 5, 0) - node T_398 = subw(UInt<2>("h02"), T_397) - node T_400 = cat(UInt<1>("h01"), T_369) - node T_401 = dshr(T_400, T_398) - node T_402 = bits(T_401, 51, 0) - node T_403 = bits(T_368, 10, 0) - node T_405 = subw(T_403, UInt<11>("h0401")) - node T_407 = subw(UInt<11>("h00"), T_393) - node T_408 = mux(T_390, T_405, T_407) - node T_409 = or(T_390, T_395) - node T_411 = mux(T_380, T_402, UInt<1>("h00")) - node T_412 = mux(T_409, T_369, T_411) - node T_413 = cat(T_408, T_412) - node unrec_d = cat(T_367, T_413) - node T_415 = bit(unrec_s, 31) - node T_417 = subw(UInt<32>("h00"), T_415) - node T_418 = cat(T_417, unrec_s) - node unrec_out = mux(in_1.single, T_418, unrec_d) - node T_420 = bit(in_1.in1, 32) - node T_421 = bits(in_1.in1, 31, 23) - node T_422 = bits(in_1.in1, 22, 0) - node T_423 = bits(T_421, 8, 6) - node T_424 = bits(T_423, 2, 1) - node T_426 = eq(T_424, UInt<2>("h03")) - node T_427 = bits(T_421, 6, 0) - node T_429 = lt(T_427, UInt<2>("h02")) - node T_431 = eq(T_423, UInt<1>("h01")) - node T_433 = eq(T_424, UInt<1>("h01")) - node T_434 = and(T_433, T_429) - node T_435 = or(T_431, T_434) - node T_437 = eq(T_424, UInt<1>("h01")) - node T_439 = eq(T_429, UInt<1>("h00")) - node T_440 = and(T_437, T_439) - node T_442 = eq(T_424, UInt<2>("h02")) - node T_443 = or(T_440, T_442) - node T_445 = eq(T_423, UInt<1>("h00")) - node T_446 = bit(T_421, 6) - node T_448 = eq(T_446, UInt<1>("h00")) - node T_449 = and(T_426, T_448) - node T_450 = not(T_423) - node T_452 = eq(T_450, UInt<1>("h00")) - node T_453 = bit(T_422, 22) - node T_455 = eq(T_453, UInt<1>("h00")) - node T_456 = and(T_452, T_455) - node T_457 = bit(T_422, 22) - node T_458 = and(T_452, T_457) - node T_460 = eq(T_420, UInt<1>("h00")) - node T_461 = and(T_449, T_460) - node T_463 = eq(T_420, UInt<1>("h00")) - node T_464 = and(T_443, T_463) - node T_466 = eq(T_420, UInt<1>("h00")) - node T_467 = and(T_435, T_466) - node T_469 = eq(T_420, UInt<1>("h00")) - node T_470 = and(T_445, T_469) - node T_471 = and(T_445, T_420) - node T_472 = and(T_435, T_420) - node T_473 = and(T_443, T_420) - node T_474 = and(T_449, T_420) - node T_475 = cat(T_458, T_456) - node T_476 = cat(T_464, T_467) - node T_477 = cat(T_461, T_476) - node T_478 = cat(T_475, T_477) - node T_479 = cat(T_470, T_471) - node T_480 = cat(T_473, T_474) - node T_481 = cat(T_472, T_480) - node T_482 = cat(T_479, T_481) - node classify_s = cat(T_478, T_482) - node T_484 = bit(in_1.in1, 64) - node T_485 = bits(in_1.in1, 63, 52) - node T_486 = bits(in_1.in1, 51, 0) - node T_487 = bits(T_485, 11, 9) - node T_488 = bits(T_487, 2, 1) - node T_490 = eq(T_488, UInt<2>("h03")) - node T_491 = bits(T_485, 9, 0) - node T_493 = lt(T_491, UInt<2>("h02")) - node T_495 = eq(T_487, UInt<1>("h01")) - node T_497 = eq(T_488, UInt<1>("h01")) - node T_498 = and(T_497, T_493) - node T_499 = or(T_495, T_498) - node T_501 = eq(T_488, UInt<1>("h01")) - node T_503 = eq(T_493, UInt<1>("h00")) - node T_504 = and(T_501, T_503) - node T_506 = eq(T_488, UInt<2>("h02")) - node T_507 = or(T_504, T_506) - node T_509 = eq(T_487, UInt<1>("h00")) - node T_510 = bit(T_485, 9) - node T_512 = eq(T_510, UInt<1>("h00")) - node T_513 = and(T_490, T_512) - node T_514 = not(T_487) - node T_516 = eq(T_514, UInt<1>("h00")) - node T_517 = bit(T_486, 51) - node T_519 = eq(T_517, UInt<1>("h00")) - node T_520 = and(T_516, T_519) - node T_521 = bit(T_486, 51) - node T_522 = and(T_516, T_521) - node T_524 = eq(T_484, UInt<1>("h00")) - node T_525 = and(T_513, T_524) - node T_527 = eq(T_484, UInt<1>("h00")) - node T_528 = and(T_507, T_527) - node T_530 = eq(T_484, UInt<1>("h00")) - node T_531 = and(T_499, T_530) - node T_533 = eq(T_484, UInt<1>("h00")) - node T_534 = and(T_509, T_533) - node T_535 = and(T_509, T_484) - node T_536 = and(T_499, T_484) - node T_537 = and(T_507, T_484) - node T_538 = and(T_513, T_484) - node T_539 = cat(T_522, T_520) - node T_540 = cat(T_528, T_531) - node T_541 = cat(T_525, T_540) - node T_542 = cat(T_539, T_541) - node T_543 = cat(T_534, T_535) - node T_544 = cat(T_537, T_538) - node T_545 = cat(T_536, T_544) - node T_546 = cat(T_543, T_545) - node classify_d = cat(T_542, T_546) - node classify_out = mux(in_1.single, classify_s, classify_d) - inst dcmp of recodedFloatNCompare - dcmp.b := UInt<1>("h00") - dcmp.a := UInt<1>("h00") - dcmp.reset := UInt<1>("h00") - dcmp.clock := clock - dcmp.reset := reset - dcmp.a := in_1.in1 - dcmp.b := in_1.in2 - node T_552 = not(in_1.rm) - node T_553 = cat(dcmp.a_lt_b, dcmp.a_eq_b) - node T_554 = and(T_552, T_553) - node dcmp_out = neq(T_554, UInt<1>("h00")) - node T_557 = not(in_1.rm) - node T_558 = cat(dcmp.a_lt_b_invalid, dcmp.a_eq_b_invalid) - node T_559 = and(T_557, T_558) - node T_561 = neq(T_559, UInt<1>("h00")) - node dcmp_exc = shl(T_561, 4) - node T_564 = xor(in_1.typ, UInt<1>("h01")) - node T_565 = bit(in_1.in1, 64) - node T_566 = bits(in_1.in1, 63, 52) - node T_567 = bits(in_1.in1, 51, 0) - node T_568 = bits(T_566, 10, 0) - node T_569 = not(T_568) - node T_571 = eq(T_569, UInt<1>("h00")) - node T_573 = eq(T_571, UInt<1>("h00")) - node T_574 = bit(T_566, 11) - node T_576 = eq(T_574, UInt<1>("h00")) - node T_577 = bits(T_566, 11, 9) - node T_579 = eq(T_577, UInt<1>("h00")) - node T_580 = bits(T_566, 11, 10) - node T_581 = not(T_580) - node T_583 = eq(T_581, UInt<1>("h00")) - node T_585 = bits(T_566, 5, 0) - node T_586 = mux(T_576, UInt<1>("h00"), T_585) - node T_588 = eq(T_576, UInt<1>("h00")) - node T_589 = cat(T_588, T_567) - node T_590 = dshl(T_589, T_586) - node T_591 = bits(T_590, 115, 52) - node T_592 = bits(T_590, 52, 51) - node T_593 = bits(T_590, 50, 0) - node T_595 = neq(T_593, UInt<1>("h00")) - node T_596 = cat(T_592, T_595) - node T_597 = bits(T_596, 1, 0) - node T_599 = neq(T_597, UInt<1>("h00")) - node T_601 = eq(T_573, UInt<1>("h00")) - node T_602 = and(T_601, T_599) - node T_603 = bits(T_596, 2, 1) - node T_604 = not(T_603) - node T_606 = eq(T_604, UInt<1>("h00")) - node T_607 = bits(T_596, 1, 0) - node T_608 = not(T_607) - node T_610 = eq(T_608, UInt<1>("h00")) - node T_611 = or(T_606, T_610) - node T_612 = mux(T_576, T_602, T_611) - node T_614 = eq(T_579, UInt<1>("h00")) - node T_615 = mux(T_576, T_614, T_599) - node T_616 = eq(in_1.rm, UInt<2>("h00")) - node T_617 = eq(in_1.rm, UInt<2>("h02")) - node T_618 = and(T_565, T_615) - node T_619 = eq(in_1.rm, UInt<2>("h03")) - node T_621 = eq(T_565, UInt<1>("h00")) - node T_622 = and(T_621, T_615) - node T_624 = mux(T_619, T_622, UInt<1>("h00")) - node T_625 = mux(T_617, T_618, T_624) - node T_626 = mux(T_616, T_612, T_625) - node T_627 = not(T_591) - node T_628 = mux(T_565, T_627, T_591) - node T_629 = xor(T_626, T_565) - node T_631 = addw(T_628, UInt<1>("h01")) - node T_632 = mux(T_629, T_631, T_628) - node T_633 = asSInt(T_632) - node T_634 = not(T_591) - node T_636 = eq(T_634, UInt<1>("h00")) - node T_637 = and(T_626, T_636) - node T_639 = eq(T_565, UInt<1>("h00")) - node T_640 = and(T_639, T_637) - node T_642 = eq(T_565, UInt<1>("h00")) - node T_643 = or(T_642, T_626) - node T_645 = neq(T_591, UInt<1>("h00")) - node T_646 = or(T_643, T_645) - node T_647 = bits(T_566, 10, 0) - node T_648 = eq(T_564, UInt<2>("h00")) - node T_649 = and(T_565, T_626) - node T_651 = eq(T_647, UInt<5>("h01f")) - node T_653 = geq(T_647, UInt<6>("h020")) - node T_654 = mux(T_651, T_637, T_653) - node T_655 = or(T_565, T_654) - node T_656 = mux(T_576, T_649, T_655) - node T_657 = eq(T_564, UInt<2>("h01")) - node T_660 = eq(T_647, UInt<5>("h01e")) - node T_662 = eq(T_647, UInt<5>("h01f")) - node T_664 = geq(T_647, UInt<6>("h020")) - node T_665 = mux(T_662, T_646, T_664) - node T_666 = mux(T_660, T_640, T_665) - node T_667 = mux(T_576, UInt<1>("h00"), T_666) - node T_668 = eq(T_564, UInt<2>("h02")) - node T_669 = and(T_565, T_626) - node T_671 = eq(T_647, UInt<6>("h03f")) - node T_673 = geq(T_647, UInt<7>("h040")) - node T_674 = mux(T_671, T_637, T_673) - node T_675 = or(T_565, T_674) - node T_676 = mux(T_576, T_669, T_675) - node T_679 = eq(T_647, UInt<6>("h03e")) - node T_681 = eq(T_647, UInt<6>("h03f")) - node T_683 = geq(T_647, UInt<7>("h040")) - node T_684 = mux(T_681, T_646, T_683) - node T_685 = mux(T_679, T_640, T_684) - node T_686 = mux(T_576, UInt<1>("h00"), T_685) - node T_687 = mux(T_668, T_676, T_686) - node T_688 = mux(T_657, T_667, T_687) - node T_689 = mux(T_648, T_656, T_688) - node T_690 = or(T_583, T_689) - node T_691 = eq(T_564, UInt<2>("h03")) - node T_692 = and(T_691, T_565) - node T_694 = eq(T_564, UInt<2>("h01")) - node T_695 = and(T_694, T_565) - node T_697 = eq(T_564, UInt<2>("h03")) - node T_699 = eq(T_565, UInt<1>("h00")) - node T_700 = and(T_697, T_699) - node T_702 = eq(T_564, UInt<2>("h01")) - node T_704 = eq(T_565, UInt<1>("h00")) - node T_705 = and(T_702, T_704) - node T_708 = mux(T_705, asSInt(UInt<32>("h07fffffff")), asSInt(UInt<1>("h01"))) - node T_709 = mux(T_700, asSInt(UInt<64>("h07fffffffffffffff")), T_708) - node T_710 = mux(T_695, asSInt(UInt<32>("h080000000")), T_709) - node T_711 = mux(T_692, asSInt(UInt<64>("h08000000000000000")), T_710) - node T_713 = eq(T_690, UInt<1>("h00")) - node T_714 = and(T_599, T_713) - node T_715 = mux(T_690, T_711, T_633) - node T_717 = cat(UInt<3>("h00"), T_714) - node T_718 = cat(T_690, T_717) - node T_719 = bit(in_1.rm, 0) - node T_720 = mux(T_719, classify_out, unrec_out) - out.bits.toint := T_720 - out.bits.store := unrec_out - out.bits.exc := UInt<1>("h00") - node T_724 = and(in_1.cmd, UInt<4>("h0c")) - node T_725 = eq(UInt<3>("h04"), T_724) - when T_725 : - out.bits.toint := dcmp_out - out.bits.exc := dcmp_exc - skip - node T_728 = and(in_1.cmd, UInt<4>("h0c")) - node T_729 = eq(UInt<4>("h08"), T_728) - when T_729 : - node T_730 = bit(in_1.typ, 1) - node T_731 = bits(T_715, 31, 0) - node T_732 = asSInt(T_731) - node T_733 = mux(T_730, T_715, T_732) - node T_734 = asUInt(T_733) - out.bits.toint := T_734 - out.bits.exc := T_718 - skip - out.valid := valid - out.bits.lt := dcmp.a_lt_b - as_double <> in_1 - - module IntToFP : - output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - input clock : Clock - input reset : UInt<1> - - out.bits.exc := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.valid := UInt<1>("h00") - reg T_136 : UInt<1>, clock, reset - onreset T_136 := UInt<1>("h00") - T_136 := in.valid - reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset - when in.valid : - T_137 <> in.bits - skip - wire in_1 : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in_1.bits.in3 := UInt<1>("h00") - in_1.bits.in2 := UInt<1>("h00") - in_1.bits.in1 := UInt<1>("h00") - in_1.bits.typ := UInt<1>("h00") - in_1.bits.rm := UInt<1>("h00") - in_1.bits.wflags := UInt<1>("h00") - in_1.bits.round := UInt<1>("h00") - in_1.bits.sqrt := UInt<1>("h00") - in_1.bits.div := UInt<1>("h00") - in_1.bits.fma := UInt<1>("h00") - in_1.bits.fastpipe := UInt<1>("h00") - in_1.bits.toint := UInt<1>("h00") - in_1.bits.fromint := UInt<1>("h00") - in_1.bits.single := UInt<1>("h00") - in_1.bits.swap23 := UInt<1>("h00") - in_1.bits.swap12 := UInt<1>("h00") - in_1.bits.ren3 := UInt<1>("h00") - in_1.bits.ren2 := UInt<1>("h00") - in_1.bits.ren1 := UInt<1>("h00") - in_1.bits.wen := UInt<1>("h00") - in_1.bits.ldst := UInt<1>("h00") - in_1.bits.cmd := UInt<1>("h00") - in_1.valid := UInt<1>("h00") - in_1.valid := T_136 - in_1.bits <> T_137 - wire mux : {data : UInt<65>, exc : UInt<5>} - mux.exc := UInt<1>("h00") - mux.data := UInt<1>("h00") - mux.exc := UInt<1>("h00") - node T_288 = bit(in_1.bits.in1, 63) - node T_289 = bits(in_1.bits.in1, 62, 52) - node T_290 = bits(in_1.bits.in1, 51, 0) - node T_292 = eq(T_289, UInt<1>("h00")) - node T_294 = eq(T_290, UInt<1>("h00")) - node T_295 = and(T_292, T_294) - node T_297 = eq(T_294, UInt<1>("h00")) - node T_298 = and(T_292, T_297) - node T_299 = shl(T_290, 12) - node T_300 = bit(T_299, 63) - node T_302 = bit(T_299, 62) - node T_304 = bit(T_299, 61) - node T_306 = bit(T_299, 60) - node T_308 = bit(T_299, 59) - node T_310 = bit(T_299, 58) - node T_312 = bit(T_299, 57) - node T_314 = bit(T_299, 56) - node T_316 = bit(T_299, 55) - node T_318 = bit(T_299, 54) - node T_320 = bit(T_299, 53) - node T_322 = bit(T_299, 52) - node T_324 = bit(T_299, 51) - node T_326 = bit(T_299, 50) - node T_328 = bit(T_299, 49) - node T_330 = bit(T_299, 48) - node T_332 = bit(T_299, 47) - node T_334 = bit(T_299, 46) - node T_336 = bit(T_299, 45) - node T_338 = bit(T_299, 44) - node T_340 = bit(T_299, 43) - node T_342 = bit(T_299, 42) - node T_344 = bit(T_299, 41) - node T_346 = bit(T_299, 40) - node T_348 = bit(T_299, 39) - node T_350 = bit(T_299, 38) - node T_352 = bit(T_299, 37) - node T_354 = bit(T_299, 36) - node T_356 = bit(T_299, 35) - node T_358 = bit(T_299, 34) - node T_360 = bit(T_299, 33) - node T_362 = bit(T_299, 32) - node T_364 = bit(T_299, 31) - node T_366 = bit(T_299, 30) - node T_368 = bit(T_299, 29) - node T_370 = bit(T_299, 28) - node T_372 = bit(T_299, 27) - node T_374 = bit(T_299, 26) - node T_376 = bit(T_299, 25) - node T_378 = bit(T_299, 24) - node T_380 = bit(T_299, 23) - node T_382 = bit(T_299, 22) - node T_384 = bit(T_299, 21) - node T_386 = bit(T_299, 20) - node T_388 = bit(T_299, 19) - node T_390 = bit(T_299, 18) - node T_392 = bit(T_299, 17) - node T_394 = bit(T_299, 16) - node T_396 = bit(T_299, 15) - node T_398 = bit(T_299, 14) - node T_400 = bit(T_299, 13) - node T_402 = bit(T_299, 12) - node T_404 = bit(T_299, 11) - node T_406 = bit(T_299, 10) - node T_408 = bit(T_299, 9) - node T_410 = bit(T_299, 8) - node T_412 = bit(T_299, 7) - node T_414 = bit(T_299, 6) - node T_416 = bit(T_299, 5) - node T_418 = bit(T_299, 4) - node T_420 = bit(T_299, 3) - node T_422 = bit(T_299, 2) - node T_424 = bit(T_299, 1) - node T_425 = shl(T_424, 0) - node T_426 = mux(T_422, UInt<2>("h02"), T_425) - node T_427 = mux(T_420, UInt<2>("h03"), T_426) - node T_428 = mux(T_418, UInt<3>("h04"), T_427) - node T_429 = mux(T_416, UInt<3>("h05"), T_428) - node T_430 = mux(T_414, UInt<3>("h06"), T_429) - node T_431 = mux(T_412, UInt<3>("h07"), T_430) - node T_432 = mux(T_410, UInt<4>("h08"), T_431) - node T_433 = mux(T_408, UInt<4>("h09"), T_432) - node T_434 = mux(T_406, UInt<4>("h0a"), T_433) - node T_435 = mux(T_404, UInt<4>("h0b"), T_434) - node T_436 = mux(T_402, UInt<4>("h0c"), T_435) - node T_437 = mux(T_400, UInt<4>("h0d"), T_436) - node T_438 = mux(T_398, UInt<4>("h0e"), T_437) - node T_439 = mux(T_396, UInt<4>("h0f"), T_438) - node T_440 = mux(T_394, UInt<5>("h010"), T_439) - node T_441 = mux(T_392, UInt<5>("h011"), T_440) - node T_442 = mux(T_390, UInt<5>("h012"), T_441) - node T_443 = mux(T_388, UInt<5>("h013"), T_442) - node T_444 = mux(T_386, UInt<5>("h014"), T_443) - node T_445 = mux(T_384, UInt<5>("h015"), T_444) - node T_446 = mux(T_382, UInt<5>("h016"), T_445) - node T_447 = mux(T_380, UInt<5>("h017"), T_446) - node T_448 = mux(T_378, UInt<5>("h018"), T_447) - node T_449 = mux(T_376, UInt<5>("h019"), T_448) - node T_450 = mux(T_374, UInt<5>("h01a"), T_449) - node T_451 = mux(T_372, UInt<5>("h01b"), T_450) - node T_452 = mux(T_370, UInt<5>("h01c"), T_451) - node T_453 = mux(T_368, UInt<5>("h01d"), T_452) - node T_454 = mux(T_366, UInt<5>("h01e"), T_453) - node T_455 = mux(T_364, UInt<5>("h01f"), T_454) - node T_456 = mux(T_362, UInt<6>("h020"), T_455) - node T_457 = mux(T_360, UInt<6>("h021"), T_456) - node T_458 = mux(T_358, UInt<6>("h022"), T_457) - node T_459 = mux(T_356, UInt<6>("h023"), T_458) - node T_460 = mux(T_354, UInt<6>("h024"), T_459) - node T_461 = mux(T_352, UInt<6>("h025"), T_460) - node T_462 = mux(T_350, UInt<6>("h026"), T_461) - node T_463 = mux(T_348, UInt<6>("h027"), T_462) - node T_464 = mux(T_346, UInt<6>("h028"), T_463) - node T_465 = mux(T_344, UInt<6>("h029"), T_464) - node T_466 = mux(T_342, UInt<6>("h02a"), T_465) - node T_467 = mux(T_340, UInt<6>("h02b"), T_466) - node T_468 = mux(T_338, UInt<6>("h02c"), T_467) - node T_469 = mux(T_336, UInt<6>("h02d"), T_468) - node T_470 = mux(T_334, UInt<6>("h02e"), T_469) - node T_471 = mux(T_332, UInt<6>("h02f"), T_470) - node T_472 = mux(T_330, UInt<6>("h030"), T_471) - node T_473 = mux(T_328, UInt<6>("h031"), T_472) - node T_474 = mux(T_326, UInt<6>("h032"), T_473) - node T_475 = mux(T_324, UInt<6>("h033"), T_474) - node T_476 = mux(T_322, UInt<6>("h034"), T_475) - node T_477 = mux(T_320, UInt<6>("h035"), T_476) - node T_478 = mux(T_318, UInt<6>("h036"), T_477) - node T_479 = mux(T_316, UInt<6>("h037"), T_478) - node T_480 = mux(T_314, UInt<6>("h038"), T_479) - node T_481 = mux(T_312, UInt<6>("h039"), T_480) - node T_482 = mux(T_310, UInt<6>("h03a"), T_481) - node T_483 = mux(T_308, UInt<6>("h03b"), T_482) - node T_484 = mux(T_306, UInt<6>("h03c"), T_483) - node T_485 = mux(T_304, UInt<6>("h03d"), T_484) - node T_486 = mux(T_302, UInt<6>("h03e"), T_485) - node T_487 = mux(T_300, UInt<6>("h03f"), T_486) - node T_488 = not(T_487) - node T_489 = dshl(T_299, T_488) - node T_492 = subw(UInt<6>("h00"), UInt<1>("h01")) - node T_493 = not(T_488) - node T_494 = cat(T_492, T_493) - node T_495 = bits(T_489, 62, 11) - node T_497 = mux(T_294, UInt<1>("h00"), T_494) - node T_498 = mux(T_292, T_497, T_289) - node T_503 = mux(T_298, UInt<2>("h02"), UInt<1>("h01")) - node T_504 = or(UInt<11>("h0400"), T_503) - node T_505 = mux(T_295, UInt<1>("h00"), T_504) - node T_506 = addw(T_498, T_505) - node T_507 = bits(T_506, 11, 10) - node T_508 = not(T_507) - node T_510 = eq(T_508, UInt<1>("h00")) - node T_512 = eq(T_294, UInt<1>("h00")) - node T_513 = and(T_510, T_512) - node T_514 = shl(T_513, 9) - node T_515 = or(T_506, T_514) - node T_516 = mux(T_292, T_495, T_290) - node T_517 = cat(T_515, T_516) - node T_518 = cat(T_288, T_517) - mux.data := T_518 - when in_1.bits.single : - node T_520 = bit(in_1.bits.in1, 31) - node T_521 = bits(in_1.bits.in1, 30, 23) - node T_522 = bits(in_1.bits.in1, 22, 0) - node T_524 = eq(T_521, UInt<1>("h00")) - node T_526 = eq(T_522, UInt<1>("h00")) - node T_527 = and(T_524, T_526) - node T_529 = eq(T_526, UInt<1>("h00")) - node T_530 = and(T_524, T_529) - node T_531 = shl(T_522, 9) - node T_532 = bit(T_531, 31) - node T_534 = bit(T_531, 30) - node T_536 = bit(T_531, 29) - node T_538 = bit(T_531, 28) - node T_540 = bit(T_531, 27) - node T_542 = bit(T_531, 26) - node T_544 = bit(T_531, 25) - node T_546 = bit(T_531, 24) - node T_548 = bit(T_531, 23) - node T_550 = bit(T_531, 22) - node T_552 = bit(T_531, 21) - node T_554 = bit(T_531, 20) - node T_556 = bit(T_531, 19) - node T_558 = bit(T_531, 18) - node T_560 = bit(T_531, 17) - node T_562 = bit(T_531, 16) - node T_564 = bit(T_531, 15) - node T_566 = bit(T_531, 14) - node T_568 = bit(T_531, 13) - node T_570 = bit(T_531, 12) - node T_572 = bit(T_531, 11) - node T_574 = bit(T_531, 10) - node T_576 = bit(T_531, 9) - node T_578 = bit(T_531, 8) - node T_580 = bit(T_531, 7) - node T_582 = bit(T_531, 6) - node T_584 = bit(T_531, 5) - node T_586 = bit(T_531, 4) - node T_588 = bit(T_531, 3) - node T_590 = bit(T_531, 2) - node T_592 = bit(T_531, 1) - node T_593 = shl(T_592, 0) - node T_594 = mux(T_590, UInt<2>("h02"), T_593) - node T_595 = mux(T_588, UInt<2>("h03"), T_594) - node T_596 = mux(T_586, UInt<3>("h04"), T_595) - node T_597 = mux(T_584, UInt<3>("h05"), T_596) - node T_598 = mux(T_582, UInt<3>("h06"), T_597) - node T_599 = mux(T_580, UInt<3>("h07"), T_598) - node T_600 = mux(T_578, UInt<4>("h08"), T_599) - node T_601 = mux(T_576, UInt<4>("h09"), T_600) - node T_602 = mux(T_574, UInt<4>("h0a"), T_601) - node T_603 = mux(T_572, UInt<4>("h0b"), T_602) - node T_604 = mux(T_570, UInt<4>("h0c"), T_603) - node T_605 = mux(T_568, UInt<4>("h0d"), T_604) - node T_606 = mux(T_566, UInt<4>("h0e"), T_605) - node T_607 = mux(T_564, UInt<4>("h0f"), T_606) - node T_608 = mux(T_562, UInt<5>("h010"), T_607) - node T_609 = mux(T_560, UInt<5>("h011"), T_608) - node T_610 = mux(T_558, UInt<5>("h012"), T_609) - node T_611 = mux(T_556, UInt<5>("h013"), T_610) - node T_612 = mux(T_554, UInt<5>("h014"), T_611) - node T_613 = mux(T_552, UInt<5>("h015"), T_612) - node T_614 = mux(T_550, UInt<5>("h016"), T_613) - node T_615 = mux(T_548, UInt<5>("h017"), T_614) - node T_616 = mux(T_546, UInt<5>("h018"), T_615) - node T_617 = mux(T_544, UInt<5>("h019"), T_616) - node T_618 = mux(T_542, UInt<5>("h01a"), T_617) - node T_619 = mux(T_540, UInt<5>("h01b"), T_618) - node T_620 = mux(T_538, UInt<5>("h01c"), T_619) - node T_621 = mux(T_536, UInt<5>("h01d"), T_620) - node T_622 = mux(T_534, UInt<5>("h01e"), T_621) - node T_623 = mux(T_532, UInt<5>("h01f"), T_622) - node T_624 = not(T_623) - node T_625 = dshl(T_531, T_624) - node T_628 = subw(UInt<4>("h00"), UInt<1>("h01")) - node T_629 = not(T_624) - node T_630 = cat(T_628, T_629) - node T_631 = bits(T_625, 30, 8) - node T_633 = mux(T_526, UInt<1>("h00"), T_630) - node T_634 = mux(T_524, T_633, T_521) - node T_639 = mux(T_530, UInt<2>("h02"), UInt<1>("h01")) - node T_640 = or(UInt<8>("h080"), T_639) - node T_641 = mux(T_527, UInt<1>("h00"), T_640) - node T_642 = addw(T_634, T_641) - node T_643 = bits(T_642, 8, 7) - node T_644 = not(T_643) - node T_646 = eq(T_644, UInt<1>("h00")) - node T_648 = eq(T_526, UInt<1>("h00")) - node T_649 = and(T_646, T_648) - node T_650 = shl(T_649, 6) - node T_651 = or(T_642, T_650) - node T_652 = mux(T_524, T_631, T_522) - node T_653 = cat(T_651, T_652) - node T_654 = cat(T_520, T_653) - node T_655 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_656 = cat(T_655, T_654) - mux.data := T_656 - skip - node T_659 = and(in_1.bits.cmd, UInt<3>("h04")) - node T_660 = eq(UInt<1>("h00"), T_659) - when T_660 : - when in_1.bits.single : - node T_661 = bits(in_1.bits.in1, 63, 0) - node T_663 = xor(in_1.bits.typ, UInt<1>("h01")) - node T_664 = eq(T_663, UInt<2>("h01")) - node T_665 = bit(T_661, 31) - node T_666 = eq(T_663, UInt<2>("h03")) - node T_667 = bit(T_661, 63) - node T_669 = mux(T_666, T_667, UInt<1>("h00")) - node T_670 = mux(T_664, T_665, T_669) - node T_672 = subw(UInt<1>("h00"), T_661) - node T_673 = mux(T_670, T_672, T_661) - node T_674 = eq(T_663, UInt<2>("h03")) - node T_675 = eq(T_663, UInt<2>("h02")) - node T_676 = or(T_674, T_675) - node T_677 = bits(T_673, 31, 0) - node T_678 = mux(T_676, T_673, T_677) - node T_679 = bit(T_678, 63) - node T_681 = bit(T_678, 62) - node T_683 = bit(T_678, 61) - node T_685 = bit(T_678, 60) - node T_687 = bit(T_678, 59) - node T_689 = bit(T_678, 58) - node T_691 = bit(T_678, 57) - node T_693 = bit(T_678, 56) - node T_695 = bit(T_678, 55) - node T_697 = bit(T_678, 54) - node T_699 = bit(T_678, 53) - node T_701 = bit(T_678, 52) - node T_703 = bit(T_678, 51) - node T_705 = bit(T_678, 50) - node T_707 = bit(T_678, 49) - node T_709 = bit(T_678, 48) - node T_711 = bit(T_678, 47) - node T_713 = bit(T_678, 46) - node T_715 = bit(T_678, 45) - node T_717 = bit(T_678, 44) - node T_719 = bit(T_678, 43) - node T_721 = bit(T_678, 42) - node T_723 = bit(T_678, 41) - node T_725 = bit(T_678, 40) - node T_727 = bit(T_678, 39) - node T_729 = bit(T_678, 38) - node T_731 = bit(T_678, 37) - node T_733 = bit(T_678, 36) - node T_735 = bit(T_678, 35) - node T_737 = bit(T_678, 34) - node T_739 = bit(T_678, 33) - node T_741 = bit(T_678, 32) - node T_743 = bit(T_678, 31) - node T_745 = bit(T_678, 30) - node T_747 = bit(T_678, 29) - node T_749 = bit(T_678, 28) - node T_751 = bit(T_678, 27) - node T_753 = bit(T_678, 26) - node T_755 = bit(T_678, 25) - node T_757 = bit(T_678, 24) - node T_759 = bit(T_678, 23) - node T_761 = bit(T_678, 22) - node T_763 = bit(T_678, 21) - node T_765 = bit(T_678, 20) - node T_767 = bit(T_678, 19) - node T_769 = bit(T_678, 18) - node T_771 = bit(T_678, 17) - node T_773 = bit(T_678, 16) - node T_775 = bit(T_678, 15) - node T_777 = bit(T_678, 14) - node T_779 = bit(T_678, 13) - node T_781 = bit(T_678, 12) - node T_783 = bit(T_678, 11) - node T_785 = bit(T_678, 10) - node T_787 = bit(T_678, 9) - node T_789 = bit(T_678, 8) - node T_791 = bit(T_678, 7) - node T_793 = bit(T_678, 6) - node T_795 = bit(T_678, 5) - node T_797 = bit(T_678, 4) - node T_799 = bit(T_678, 3) - node T_801 = bit(T_678, 2) - node T_803 = bit(T_678, 1) - node T_804 = shl(T_803, 0) - node T_805 = mux(T_801, UInt<2>("h02"), T_804) - node T_806 = mux(T_799, UInt<2>("h03"), T_805) - node T_807 = mux(T_797, UInt<3>("h04"), T_806) - node T_808 = mux(T_795, UInt<3>("h05"), T_807) - node T_809 = mux(T_793, UInt<3>("h06"), T_808) - node T_810 = mux(T_791, UInt<3>("h07"), T_809) - node T_811 = mux(T_789, UInt<4>("h08"), T_810) - node T_812 = mux(T_787, UInt<4>("h09"), T_811) - node T_813 = mux(T_785, UInt<4>("h0a"), T_812) - node T_814 = mux(T_783, UInt<4>("h0b"), T_813) - node T_815 = mux(T_781, UInt<4>("h0c"), T_814) - node T_816 = mux(T_779, UInt<4>("h0d"), T_815) - node T_817 = mux(T_777, UInt<4>("h0e"), T_816) - node T_818 = mux(T_775, UInt<4>("h0f"), T_817) - node T_819 = mux(T_773, UInt<5>("h010"), T_818) - node T_820 = mux(T_771, UInt<5>("h011"), T_819) - node T_821 = mux(T_769, UInt<5>("h012"), T_820) - node T_822 = mux(T_767, UInt<5>("h013"), T_821) - node T_823 = mux(T_765, UInt<5>("h014"), T_822) - node T_824 = mux(T_763, UInt<5>("h015"), T_823) - node T_825 = mux(T_761, UInt<5>("h016"), T_824) - node T_826 = mux(T_759, UInt<5>("h017"), T_825) - node T_827 = mux(T_757, UInt<5>("h018"), T_826) - node T_828 = mux(T_755, UInt<5>("h019"), T_827) - node T_829 = mux(T_753, UInt<5>("h01a"), T_828) - node T_830 = mux(T_751, UInt<5>("h01b"), T_829) - node T_831 = mux(T_749, UInt<5>("h01c"), T_830) - node T_832 = mux(T_747, UInt<5>("h01d"), T_831) - node T_833 = mux(T_745, UInt<5>("h01e"), T_832) - node T_834 = mux(T_743, UInt<5>("h01f"), T_833) - node T_835 = mux(T_741, UInt<6>("h020"), T_834) - node T_836 = mux(T_739, UInt<6>("h021"), T_835) - node T_837 = mux(T_737, UInt<6>("h022"), T_836) - node T_838 = mux(T_735, UInt<6>("h023"), T_837) - node T_839 = mux(T_733, UInt<6>("h024"), T_838) - node T_840 = mux(T_731, UInt<6>("h025"), T_839) - node T_841 = mux(T_729, UInt<6>("h026"), T_840) - node T_842 = mux(T_727, UInt<6>("h027"), T_841) - node T_843 = mux(T_725, UInt<6>("h028"), T_842) - node T_844 = mux(T_723, UInt<6>("h029"), T_843) - node T_845 = mux(T_721, UInt<6>("h02a"), T_844) - node T_846 = mux(T_719, UInt<6>("h02b"), T_845) - node T_847 = mux(T_717, UInt<6>("h02c"), T_846) - node T_848 = mux(T_715, UInt<6>("h02d"), T_847) - node T_849 = mux(T_713, UInt<6>("h02e"), T_848) - node T_850 = mux(T_711, UInt<6>("h02f"), T_849) - node T_851 = mux(T_709, UInt<6>("h030"), T_850) - node T_852 = mux(T_707, UInt<6>("h031"), T_851) - node T_853 = mux(T_705, UInt<6>("h032"), T_852) - node T_854 = mux(T_703, UInt<6>("h033"), T_853) - node T_855 = mux(T_701, UInt<6>("h034"), T_854) - node T_856 = mux(T_699, UInt<6>("h035"), T_855) - node T_857 = mux(T_697, UInt<6>("h036"), T_856) - node T_858 = mux(T_695, UInt<6>("h037"), T_857) - node T_859 = mux(T_693, UInt<6>("h038"), T_858) - node T_860 = mux(T_691, UInt<6>("h039"), T_859) - node T_861 = mux(T_689, UInt<6>("h03a"), T_860) - node T_862 = mux(T_687, UInt<6>("h03b"), T_861) - node T_863 = mux(T_685, UInt<6>("h03c"), T_862) - node T_864 = mux(T_683, UInt<6>("h03d"), T_863) - node T_865 = mux(T_681, UInt<6>("h03e"), T_864) - node T_866 = mux(T_679, UInt<6>("h03f"), T_865) - node T_867 = not(T_866) - node T_868 = dshl(T_678, T_867) - node T_870 = bits(T_868, 40, 39) - node T_871 = bits(T_868, 38, 0) - node T_873 = neq(T_871, UInt<1>("h00")) - node T_874 = cat(T_870, T_873) - node T_875 = bits(T_874, 1, 0) - node T_877 = neq(T_875, UInt<1>("h00")) - node T_878 = eq(in_1.bits.rm, UInt<2>("h00")) - node T_879 = bits(T_874, 2, 1) - node T_880 = not(T_879) - node T_882 = eq(T_880, UInt<1>("h00")) - node T_883 = bits(T_874, 1, 0) - node T_884 = not(T_883) - node T_886 = eq(T_884, UInt<1>("h00")) - node T_887 = or(T_882, T_886) - node T_888 = eq(in_1.bits.rm, UInt<2>("h02")) - node T_889 = and(T_670, T_877) - node T_890 = eq(in_1.bits.rm, UInt<2>("h03")) - node T_892 = eq(T_670, UInt<1>("h00")) - node T_893 = and(T_892, T_877) - node T_895 = mux(T_890, T_893, UInt<1>("h00")) - node T_896 = mux(T_888, T_889, T_895) - node T_897 = mux(T_878, T_887, T_896) - node T_898 = bits(T_868, 63, 40) - node T_900 = cat(UInt<1>("h00"), T_898) - node T_902 = addw(T_900, UInt<1>("h01")) - node T_903 = mux(T_897, T_902, T_900) - node T_906 = not(T_867) - node T_908 = cat(UInt<1>("h00"), T_906) - node T_910 = cat(UInt<1>("h00"), T_908) - node T_911 = bit(T_903, 24) - node T_912 = addw(T_910, T_911) - node T_913 = bit(T_868, 63) - node T_915 = bits(T_912, 7, 0) - node T_916 = mux(UInt<1>("h00"), UInt<8>("h080"), T_915) - node T_917 = cat(T_913, T_916) - node T_918 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_919 = or(T_877, T_918) - node T_920 = bits(T_903, 22, 0) - node T_921 = cat(T_917, T_920) - node T_922 = cat(T_670, T_921) - node T_925 = cat(UInt<2>("h00"), T_918) - node T_926 = cat(UInt<1>("h00"), T_919) - node T_927 = cat(T_925, T_926) - node T_929 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_930 = cat(T_929, T_922) - mux.data := T_930 - mux.exc := T_927 - skip - else : - node T_931 = bits(in_1.bits.in1, 63, 0) - node T_933 = xor(in_1.bits.typ, UInt<1>("h01")) - node T_934 = eq(T_933, UInt<2>("h01")) - node T_935 = bit(T_931, 31) - node T_936 = eq(T_933, UInt<2>("h03")) - node T_937 = bit(T_931, 63) - node T_939 = mux(T_936, T_937, UInt<1>("h00")) - node T_940 = mux(T_934, T_935, T_939) - node T_942 = subw(UInt<1>("h00"), T_931) - node T_943 = mux(T_940, T_942, T_931) - node T_944 = eq(T_933, UInt<2>("h03")) - node T_945 = eq(T_933, UInt<2>("h02")) - node T_946 = or(T_944, T_945) - node T_947 = bits(T_943, 31, 0) - node T_948 = mux(T_946, T_943, T_947) - node T_949 = bit(T_948, 63) - node T_951 = bit(T_948, 62) - node T_953 = bit(T_948, 61) - node T_955 = bit(T_948, 60) - node T_957 = bit(T_948, 59) - node T_959 = bit(T_948, 58) - node T_961 = bit(T_948, 57) - node T_963 = bit(T_948, 56) - node T_965 = bit(T_948, 55) - node T_967 = bit(T_948, 54) - node T_969 = bit(T_948, 53) - node T_971 = bit(T_948, 52) - node T_973 = bit(T_948, 51) - node T_975 = bit(T_948, 50) - node T_977 = bit(T_948, 49) - node T_979 = bit(T_948, 48) - node T_981 = bit(T_948, 47) - node T_983 = bit(T_948, 46) - node T_985 = bit(T_948, 45) - node T_987 = bit(T_948, 44) - node T_989 = bit(T_948, 43) - node T_991 = bit(T_948, 42) - node T_993 = bit(T_948, 41) - node T_995 = bit(T_948, 40) - node T_997 = bit(T_948, 39) - node T_999 = bit(T_948, 38) - node T_1001 = bit(T_948, 37) - node T_1003 = bit(T_948, 36) - node T_1005 = bit(T_948, 35) - node T_1007 = bit(T_948, 34) - node T_1009 = bit(T_948, 33) - node T_1011 = bit(T_948, 32) - node T_1013 = bit(T_948, 31) - node T_1015 = bit(T_948, 30) - node T_1017 = bit(T_948, 29) - node T_1019 = bit(T_948, 28) - node T_1021 = bit(T_948, 27) - node T_1023 = bit(T_948, 26) - node T_1025 = bit(T_948, 25) - node T_1027 = bit(T_948, 24) - node T_1029 = bit(T_948, 23) - node T_1031 = bit(T_948, 22) - node T_1033 = bit(T_948, 21) - node T_1035 = bit(T_948, 20) - node T_1037 = bit(T_948, 19) - node T_1039 = bit(T_948, 18) - node T_1041 = bit(T_948, 17) - node T_1043 = bit(T_948, 16) - node T_1045 = bit(T_948, 15) - node T_1047 = bit(T_948, 14) - node T_1049 = bit(T_948, 13) - node T_1051 = bit(T_948, 12) - node T_1053 = bit(T_948, 11) - node T_1055 = bit(T_948, 10) - node T_1057 = bit(T_948, 9) - node T_1059 = bit(T_948, 8) - node T_1061 = bit(T_948, 7) - node T_1063 = bit(T_948, 6) - node T_1065 = bit(T_948, 5) - node T_1067 = bit(T_948, 4) - node T_1069 = bit(T_948, 3) - node T_1071 = bit(T_948, 2) - node T_1073 = bit(T_948, 1) - node T_1074 = shl(T_1073, 0) - node T_1075 = mux(T_1071, UInt<2>("h02"), T_1074) - node T_1076 = mux(T_1069, UInt<2>("h03"), T_1075) - node T_1077 = mux(T_1067, UInt<3>("h04"), T_1076) - node T_1078 = mux(T_1065, UInt<3>("h05"), T_1077) - node T_1079 = mux(T_1063, UInt<3>("h06"), T_1078) - node T_1080 = mux(T_1061, UInt<3>("h07"), T_1079) - node T_1081 = mux(T_1059, UInt<4>("h08"), T_1080) - node T_1082 = mux(T_1057, UInt<4>("h09"), T_1081) - node T_1083 = mux(T_1055, UInt<4>("h0a"), T_1082) - node T_1084 = mux(T_1053, UInt<4>("h0b"), T_1083) - node T_1085 = mux(T_1051, UInt<4>("h0c"), T_1084) - node T_1086 = mux(T_1049, UInt<4>("h0d"), T_1085) - node T_1087 = mux(T_1047, UInt<4>("h0e"), T_1086) - node T_1088 = mux(T_1045, UInt<4>("h0f"), T_1087) - node T_1089 = mux(T_1043, UInt<5>("h010"), T_1088) - node T_1090 = mux(T_1041, UInt<5>("h011"), T_1089) - node T_1091 = mux(T_1039, UInt<5>("h012"), T_1090) - node T_1092 = mux(T_1037, UInt<5>("h013"), T_1091) - node T_1093 = mux(T_1035, UInt<5>("h014"), T_1092) - node T_1094 = mux(T_1033, UInt<5>("h015"), T_1093) - node T_1095 = mux(T_1031, UInt<5>("h016"), T_1094) - node T_1096 = mux(T_1029, UInt<5>("h017"), T_1095) - node T_1097 = mux(T_1027, UInt<5>("h018"), T_1096) - node T_1098 = mux(T_1025, UInt<5>("h019"), T_1097) - node T_1099 = mux(T_1023, UInt<5>("h01a"), T_1098) - node T_1100 = mux(T_1021, UInt<5>("h01b"), T_1099) - node T_1101 = mux(T_1019, UInt<5>("h01c"), T_1100) - node T_1102 = mux(T_1017, UInt<5>("h01d"), T_1101) - node T_1103 = mux(T_1015, UInt<5>("h01e"), T_1102) - node T_1104 = mux(T_1013, UInt<5>("h01f"), T_1103) - node T_1105 = mux(T_1011, UInt<6>("h020"), T_1104) - node T_1106 = mux(T_1009, UInt<6>("h021"), T_1105) - node T_1107 = mux(T_1007, UInt<6>("h022"), T_1106) - node T_1108 = mux(T_1005, UInt<6>("h023"), T_1107) - node T_1109 = mux(T_1003, UInt<6>("h024"), T_1108) - node T_1110 = mux(T_1001, UInt<6>("h025"), T_1109) - node T_1111 = mux(T_999, UInt<6>("h026"), T_1110) - node T_1112 = mux(T_997, UInt<6>("h027"), T_1111) - node T_1113 = mux(T_995, UInt<6>("h028"), T_1112) - node T_1114 = mux(T_993, UInt<6>("h029"), T_1113) - node T_1115 = mux(T_991, UInt<6>("h02a"), T_1114) - node T_1116 = mux(T_989, UInt<6>("h02b"), T_1115) - node T_1117 = mux(T_987, UInt<6>("h02c"), T_1116) - node T_1118 = mux(T_985, UInt<6>("h02d"), T_1117) - node T_1119 = mux(T_983, UInt<6>("h02e"), T_1118) - node T_1120 = mux(T_981, UInt<6>("h02f"), T_1119) - node T_1121 = mux(T_979, UInt<6>("h030"), T_1120) - node T_1122 = mux(T_977, UInt<6>("h031"), T_1121) - node T_1123 = mux(T_975, UInt<6>("h032"), T_1122) - node T_1124 = mux(T_973, UInt<6>("h033"), T_1123) - node T_1125 = mux(T_971, UInt<6>("h034"), T_1124) - node T_1126 = mux(T_969, UInt<6>("h035"), T_1125) - node T_1127 = mux(T_967, UInt<6>("h036"), T_1126) - node T_1128 = mux(T_965, UInt<6>("h037"), T_1127) - node T_1129 = mux(T_963, UInt<6>("h038"), T_1128) - node T_1130 = mux(T_961, UInt<6>("h039"), T_1129) - node T_1131 = mux(T_959, UInt<6>("h03a"), T_1130) - node T_1132 = mux(T_957, UInt<6>("h03b"), T_1131) - node T_1133 = mux(T_955, UInt<6>("h03c"), T_1132) - node T_1134 = mux(T_953, UInt<6>("h03d"), T_1133) - node T_1135 = mux(T_951, UInt<6>("h03e"), T_1134) - node T_1136 = mux(T_949, UInt<6>("h03f"), T_1135) - node T_1137 = not(T_1136) - node T_1138 = dshl(T_948, T_1137) - node T_1140 = bits(T_1138, 11, 10) - node T_1141 = bits(T_1138, 9, 0) - node T_1143 = neq(T_1141, UInt<1>("h00")) - node T_1144 = cat(T_1140, T_1143) - node T_1145 = bits(T_1144, 1, 0) - node T_1147 = neq(T_1145, UInt<1>("h00")) - node T_1148 = eq(in_1.bits.rm, UInt<2>("h00")) - node T_1149 = bits(T_1144, 2, 1) - node T_1150 = not(T_1149) - node T_1152 = eq(T_1150, UInt<1>("h00")) - node T_1153 = bits(T_1144, 1, 0) - node T_1154 = not(T_1153) - node T_1156 = eq(T_1154, UInt<1>("h00")) - node T_1157 = or(T_1152, T_1156) - node T_1158 = eq(in_1.bits.rm, UInt<2>("h02")) - node T_1159 = and(T_940, T_1147) - node T_1160 = eq(in_1.bits.rm, UInt<2>("h03")) - node T_1162 = eq(T_940, UInt<1>("h00")) - node T_1163 = and(T_1162, T_1147) - node T_1165 = mux(T_1160, T_1163, UInt<1>("h00")) - node T_1166 = mux(T_1158, T_1159, T_1165) - node T_1167 = mux(T_1148, T_1157, T_1166) - node T_1168 = bits(T_1138, 63, 11) - node T_1170 = cat(UInt<1>("h00"), T_1168) - node T_1172 = addw(T_1170, UInt<1>("h01")) - node T_1173 = mux(T_1167, T_1172, T_1170) - node T_1176 = not(T_1137) - node T_1178 = cat(UInt<4>("h00"), T_1176) - node T_1180 = cat(UInt<1>("h00"), T_1178) - node T_1181 = bit(T_1173, 53) - node T_1182 = addw(T_1180, T_1181) - node T_1183 = bit(T_1138, 63) - node T_1185 = bits(T_1182, 10, 0) - node T_1186 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_1185) - node T_1187 = cat(T_1183, T_1186) - node T_1188 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = or(T_1147, T_1188) - node T_1190 = bits(T_1173, 51, 0) - node T_1191 = cat(T_1187, T_1190) - node T_1192 = cat(T_940, T_1191) - node T_1195 = cat(UInt<2>("h00"), T_1188) - node T_1196 = cat(UInt<1>("h00"), T_1189) - node T_1197 = cat(T_1195, T_1196) - mux.data := T_1192 - mux.exc := T_1197 - skip - skip - reg T_1200 : UInt<1>, clock, reset - onreset T_1200 := UInt<1>("h00") - T_1200 := in_1.valid - reg T_1201 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when in_1.valid : - T_1201 <> mux - skip - reg T_1206 : UInt<1>, clock, reset - onreset T_1206 := UInt<1>("h00") - T_1206 := T_1200 - reg T_1207 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when T_1200 : - T_1207 <> T_1201 - skip - wire T_1218 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_1218.bits.exc := UInt<1>("h00") - T_1218.bits.data := UInt<1>("h00") - T_1218.valid := UInt<1>("h00") - T_1218.valid := T_1206 - T_1218.bits <> T_1207 - out <> T_1218 - - module FPToFP : - input lt : UInt<1> - output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - input clock : Clock - input reset : UInt<1> - - out.bits.exc := UInt<1>("h00") - out.bits.data := UInt<1>("h00") - out.valid := UInt<1>("h00") - reg T_137 : UInt<1>, clock, reset - onreset T_137 := UInt<1>("h00") - T_137 := in.valid - reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset - when in.valid : - T_138 <> in.bits - skip - wire in_1 : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in_1.bits.in3 := UInt<1>("h00") - in_1.bits.in2 := UInt<1>("h00") - in_1.bits.in1 := UInt<1>("h00") - in_1.bits.typ := UInt<1>("h00") - in_1.bits.rm := UInt<1>("h00") - in_1.bits.wflags := UInt<1>("h00") - in_1.bits.round := UInt<1>("h00") - in_1.bits.sqrt := UInt<1>("h00") - in_1.bits.div := UInt<1>("h00") - in_1.bits.fma := UInt<1>("h00") - in_1.bits.fastpipe := UInt<1>("h00") - in_1.bits.toint := UInt<1>("h00") - in_1.bits.fromint := UInt<1>("h00") - in_1.bits.single := UInt<1>("h00") - in_1.bits.swap23 := UInt<1>("h00") - in_1.bits.swap12 := UInt<1>("h00") - in_1.bits.ren3 := UInt<1>("h00") - in_1.bits.ren2 := UInt<1>("h00") - in_1.bits.ren1 := UInt<1>("h00") - in_1.bits.wen := UInt<1>("h00") - in_1.bits.ldst := UInt<1>("h00") - in_1.bits.cmd := UInt<1>("h00") - in_1.valid := UInt<1>("h00") - in_1.valid := T_137 - in_1.bits <> T_138 - node T_282 = and(in_1.bits.cmd, UInt<3>("h05")) - node isSgnj = eq(UInt<3>("h04"), T_282) - node T_284 = and(in_1.bits.single, isSgnj) - node T_285 = bit(in_1.bits.rm, 1) - node T_287 = eq(T_284, UInt<1>("h00")) - node T_288 = or(T_285, T_287) - node T_289 = bit(in_1.bits.in1, 32) - node T_290 = bit(in_1.bits.rm, 0) - node T_291 = mux(T_288, T_289, T_290) - node T_292 = bit(in_1.bits.in2, 32) - node T_293 = and(T_284, T_292) - node sign_s = xor(T_291, T_293) - node T_296 = eq(in_1.bits.single, UInt<1>("h00")) - node T_297 = and(T_296, isSgnj) - node T_298 = bit(in_1.bits.rm, 1) - node T_300 = eq(T_297, UInt<1>("h00")) - node T_301 = or(T_298, T_300) - node T_302 = bit(in_1.bits.in1, 64) - node T_303 = bit(in_1.bits.rm, 0) - node T_304 = mux(T_301, T_302, T_303) - node T_305 = bit(in_1.bits.in2, 64) - node T_306 = and(T_297, T_305) - node sign_d = xor(T_304, T_306) - node T_308 = bits(in_1.bits.in1, 63, 33) - node T_309 = bits(in_1.bits.in1, 31, 0) - node T_310 = cat(sign_d, T_308) - node T_311 = cat(sign_s, T_309) - node fsgnj = cat(T_310, T_311) - node T_313 = bit(in_1.bits.in1, 32) - node T_314 = bits(in_1.bits.in1, 22, 0) - node T_315 = bits(in_1.bits.in1, 31, 23) - node T_316 = bits(in_1.bits.in1, 31, 29) - node T_317 = bits(in_1.bits.in1, 30, 23) - node T_318 = not(T_316) - node T_320 = eq(T_318, UInt<1>("h00")) - node T_321 = bit(T_314, 22) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_324 = and(T_320, T_323) - node T_326 = lt(T_316, UInt<1>("h01")) - node T_328 = lt(T_316, UInt<3>("h04")) - node T_330 = cat(UInt<3>("h07"), T_317) - node T_332 = lt(T_316, UInt<3>("h06")) - node T_334 = cat(UInt<4>("h08"), T_317) - node T_336 = lt(T_316, UInt<3>("h07")) - node T_339 = mux(T_336, UInt<12>("h0c00"), UInt<12>("h0e00")) - node T_340 = mux(T_332, T_334, T_339) - node T_341 = mux(T_328, T_330, T_340) - node T_342 = mux(T_326, T_317, T_341) - node T_344 = subw(UInt<52>("h00"), T_320) - node T_345 = shl(T_314, 29) - node T_346 = or(T_344, T_345) - node T_347 = cat(T_342, T_346) - node T_348 = cat(T_313, T_347) - node T_349 = shl(T_324, 4) - node T_350 = bit(in_1.bits.in1, 64) - node T_351 = bits(in_1.bits.in1, 51, 0) - node T_352 = bits(in_1.bits.in1, 63, 52) - node T_353 = bits(in_1.bits.in1, 63, 61) - node T_354 = bits(in_1.bits.in1, 62, 52) - node T_355 = not(T_353) - node T_357 = eq(T_355, UInt<1>("h00")) - node T_358 = bit(T_351, 51) - node T_360 = eq(T_358, UInt<1>("h00")) - node T_361 = and(T_357, T_360) - node T_366 = neq(T_353, UInt<1>("h00")) - node T_368 = eq(T_366, UInt<1>("h00")) - node T_369 = bits(T_353, 2, 1) - node T_370 = not(T_369) - node T_372 = eq(T_370, UInt<1>("h00")) - node T_373 = or(T_368, T_372) - node T_374 = geq(T_352, UInt<11>("h076a")) - node T_375 = leq(T_352, UInt<11>("h0781")) - node T_376 = and(T_374, T_375) - node T_377 = lt(T_352, UInt<11>("h076a")) - node T_379 = eq(T_373, UInt<1>("h00")) - node T_380 = and(T_377, T_379) - node T_381 = gt(T_352, UInt<12>("h087f")) - node T_383 = eq(T_373, UInt<1>("h00")) - node T_384 = and(T_381, T_383) - node T_386 = addw(UInt<11>("h0781"), UInt<1>("h01")) - node T_387 = subw(T_386, T_352) - node T_389 = mux(T_376, T_387, UInt<1>("h00")) - node T_390 = bits(T_389, 4, 0) - node T_392 = bits(T_351, 51, 28) - node T_394 = cat(T_392, UInt<24>("h00")) - node T_395 = cat(UInt<1>("h01"), T_394) - node T_396 = dshr(T_395, T_390) - node T_397 = bits(T_396, 23, 0) - node T_399 = neq(T_397, UInt<1>("h00")) - node T_400 = bits(T_351, 27, 0) - node T_402 = neq(T_400, UInt<1>("h00")) - node T_403 = or(T_399, T_402) - node T_404 = bits(T_396, 25, 24) - node T_405 = cat(T_404, T_403) - node T_406 = bits(T_405, 1, 0) - node T_408 = neq(T_406, UInt<1>("h00")) - node T_410 = eq(T_373, UInt<1>("h00")) - node T_411 = and(T_408, T_410) - node T_412 = eq(in_1.bits.rm, UInt<2>("h00")) - node T_413 = bits(T_405, 1, 0) - node T_414 = not(T_413) - node T_416 = eq(T_414, UInt<1>("h00")) - node T_417 = bits(T_405, 2, 1) - node T_418 = not(T_417) - node T_420 = eq(T_418, UInt<1>("h00")) - node T_421 = or(T_416, T_420) - node T_422 = eq(in_1.bits.rm, UInt<2>("h02")) - node T_423 = and(T_350, T_411) - node T_424 = eq(in_1.bits.rm, UInt<2>("h03")) - node T_426 = eq(T_350, UInt<1>("h00")) - node T_427 = and(T_426, T_411) - node T_429 = mux(T_424, T_427, UInt<1>("h00")) - node T_430 = mux(T_422, T_423, T_429) - node T_431 = mux(T_412, T_421, T_430) - node T_433 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_434 = cat(T_433, T_433) - node T_435 = cat(T_434, T_434) - node T_436 = cat(T_435, T_435) - node T_437 = cat(T_435, T_436) - node T_438 = cat(UInt<1>("h01"), T_437) - node T_439 = dshl(T_438, T_390) - node T_440 = bits(T_439, 24, 0) - node T_442 = bits(T_351, 51, 29) - node T_443 = cat(UInt<2>("h01"), T_442) - node T_444 = not(T_440) - node T_445 = or(T_443, T_444) - node T_447 = addw(T_445, UInt<1>("h01")) - node T_448 = mux(T_431, T_447, T_445) - node T_449 = bits(T_352, 8, 0) - node T_451 = addw(T_449, UInt<9>("h0100")) - node T_452 = bit(T_448, 24) - node T_454 = addw(T_451, UInt<1>("h01")) - node T_455 = mux(T_452, T_454, T_451) - node T_456 = eq(in_1.bits.rm, UInt<2>("h02")) - node T_457 = and(T_456, T_350) - node T_458 = eq(in_1.bits.rm, UInt<2>("h03")) - node T_460 = eq(T_350, UInt<1>("h00")) - node T_461 = and(T_458, T_460) - node T_462 = or(T_457, T_461) - node T_463 = eq(in_1.bits.rm, UInt<2>("h00")) - node T_464 = or(T_462, T_463) - node T_466 = eq(T_464, UInt<1>("h00")) - node T_468 = subw(UInt<23>("h00"), T_466) - node T_471 = mux(T_464, UInt<9>("h0180"), UInt<9>("h017f")) - node T_475 = mux(T_462, UInt<7>("h06b"), UInt<1>("h00")) - node T_476 = shl(T_353, 6) - node T_477 = mux(T_380, T_475, T_455) - node T_478 = mux(T_384, T_471, T_477) - node T_479 = mux(T_373, T_476, T_478) - node T_481 = subw(UInt<23>("h00"), T_357) - node T_482 = bits(T_448, 22, 0) - node T_483 = mux(T_380, UInt<1>("h00"), T_482) - node T_484 = mux(T_384, T_468, T_483) - node T_485 = mux(T_373, T_481, T_484) - node T_486 = cat(T_479, T_485) - node T_487 = cat(T_350, T_486) - node T_488 = and(T_376, T_411) - node T_489 = or(T_380, T_488) - node T_490 = eq(T_352, UInt<12>("h087f")) - node T_491 = bit(T_448, 24) - node T_492 = and(T_490, T_491) - node T_493 = or(T_384, T_492) - node T_495 = or(T_411, T_384) - node T_496 = or(T_495, T_380) - node T_497 = cat(T_361, UInt<1>("h00")) - node T_498 = cat(T_489, T_496) - node T_499 = cat(T_493, T_498) - node T_500 = cat(T_497, T_499) - node T_501 = bits(in_1.bits.in1, 31, 29) - node T_502 = not(T_501) - node T_504 = eq(T_502, UInt<1>("h00")) - node T_505 = bits(in_1.bits.in1, 63, 61) - node T_506 = not(T_505) - node T_508 = eq(T_506, UInt<1>("h00")) - node isnan1 = mux(in_1.bits.single, T_504, T_508) - node T_510 = bits(in_1.bits.in2, 31, 29) - node T_511 = not(T_510) - node T_513 = eq(T_511, UInt<1>("h00")) - node T_514 = bits(in_1.bits.in2, 63, 61) - node T_515 = not(T_514) - node T_517 = eq(T_515, UInt<1>("h00")) - node isnan2 = mux(in_1.bits.single, T_513, T_517) - node T_519 = bit(in_1.bits.in1, 22) - node T_520 = bit(in_1.bits.in1, 51) - node T_521 = mux(in_1.bits.single, T_519, T_520) - node T_522 = not(T_521) - node issnan1 = and(isnan1, T_522) - node T_524 = bit(in_1.bits.in2, 22) - node T_525 = bit(in_1.bits.in2, 51) - node T_526 = mux(in_1.bits.single, T_524, T_525) - node T_527 = not(T_526) - node issnan2 = and(isnan2, T_527) - node T_529 = or(issnan1, issnan2) - node minmax_exc = cat(T_529, UInt<4>("h00")) - node isMax = bit(in_1.bits.rm, 0) - node T_533 = neq(isMax, lt) - node T_535 = eq(isnan1, UInt<1>("h00")) - node T_536 = and(T_533, T_535) - node isLHS = or(isnan2, T_536) - wire mux : {data : UInt<65>, exc : UInt<5>} - mux.exc := UInt<1>("h00") - mux.data := UInt<1>("h00") - mux.exc := minmax_exc - mux.data := in_1.bits.in2 - when isSgnj : - mux.exc := UInt<1>("h00") - skip - node T_547 = or(isSgnj, isLHS) - when T_547 : - mux.data := fsgnj - skip - node T_550 = and(in_1.bits.cmd, UInt<3>("h04")) - node T_551 = eq(UInt<1>("h00"), T_550) - when T_551 : - when in_1.bits.single : - node T_553 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_554 = cat(T_553, T_487) - mux.data := T_554 - mux.exc := T_500 - skip - else : - mux.data := T_348 - mux.exc := T_349 - skip - skip - reg T_557 : UInt<1>, clock, reset - onreset T_557 := UInt<1>("h00") - T_557 := in_1.valid - reg T_558 : {data : UInt<65>, exc : UInt<5>}, clock, reset - when in_1.valid : - T_558 <> mux - skip - wire T_569 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_569.bits.exc := UInt<1>("h00") - T_569.bits.data := UInt<1>("h00") - T_569.valid := UInt<1>("h00") - T_569.valid := T_557 - T_569.bits <> T_558 - out <> T_569 - - module divSqrtRecodedFloat64_mulAddZ31 : - input mulAddResult_3 : UInt<105> - output mulAddC_2 : UInt<105> - output mulAddB_0 : UInt<54> - output latchMulAddB_0 : UInt<1> - output mulAddA_0 : UInt<54> - output latchMulAddA_0 : UInt<1> - output usingMulAdd : UInt<4> - output exceptionFlags : UInt<5> - output out : UInt<65> - output outValid_sqrt : UInt<1> - output outValid_div : UInt<1> - input roundingMode : UInt<2> - input b : UInt<65> - input a : UInt<65> - input sqrtOp : UInt<1> - input inValid : UInt<1> - output inReady_sqrt : UInt<1> - output inReady_div : UInt<1> - input clock : Clock - input reset : UInt<1> - - mulAddC_2 := UInt<1>("h00") - mulAddB_0 := UInt<1>("h00") - latchMulAddB_0 := UInt<1>("h00") - mulAddA_0 := UInt<1>("h00") - latchMulAddA_0 := UInt<1>("h00") - usingMulAdd := UInt<1>("h00") - exceptionFlags := UInt<1>("h00") - out := UInt<1>("h00") - outValid_sqrt := UInt<1>("h00") - outValid_div := UInt<1>("h00") - inReady_sqrt := UInt<1>("h00") - inReady_div := UInt<1>("h00") - reg valid_PA : UInt<1>, clock, reset - onreset valid_PA := UInt<1>("h00") - reg sqrtOp_PA : UInt<1>, clock, reset - reg sign_PA : UInt<1>, clock, reset - reg specialCodeB_PA : UInt<3>, clock, reset - reg fractB_51_PA : UInt<1>, clock, reset - reg roundingMode_PA : UInt<2>, clock, reset - reg specialCodeA_PA : UInt<3>, clock, reset - reg fractA_51_PA : UInt<1>, clock, reset - reg exp_PA : UInt<14>, clock, reset - reg fractB_other_PA : UInt<51>, clock, reset - reg fractA_other_PA : UInt<51>, clock, reset - reg valid_PB : UInt<1>, clock, reset - onreset valid_PB := UInt<1>("h00") - reg sqrtOp_PB : UInt<1>, clock, reset - reg sign_PB : UInt<1>, clock, reset - reg specialCodeA_PB : UInt<3>, clock, reset - reg fractA_51_PB : UInt<1>, clock, reset - reg specialCodeB_PB : UInt<3>, clock, reset - reg fractB_51_PB : UInt<1>, clock, reset - reg roundingMode_PB : UInt<2>, clock, reset - reg exp_PB : UInt<14>, clock, reset - reg fractA_0_PB : UInt<1>, clock, reset - reg fractB_other_PB : UInt<51>, clock, reset - reg valid_PC : UInt<1>, clock, reset - onreset valid_PC := UInt<1>("h00") - reg sqrtOp_PC : UInt<1>, clock, reset - reg sign_PC : UInt<1>, clock, reset - reg specialCodeA_PC : UInt<3>, clock, reset - reg fractA_51_PC : UInt<1>, clock, reset - reg specialCodeB_PC : UInt<3>, clock, reset - reg fractB_51_PC : UInt<1>, clock, reset - reg roundingMode_PC : UInt<2>, clock, reset - reg exp_PC : UInt<14>, clock, reset - reg fractA_0_PC : UInt<1>, clock, reset - reg fractB_other_PC : UInt<51>, clock, reset - reg cycleNum_A : UInt<3>, clock, reset - onreset cycleNum_A := UInt<3>("h00") - reg cycleNum_B : UInt<4>, clock, reset - onreset cycleNum_B := UInt<4>("h00") - reg cycleNum_C : UInt<3>, clock, reset - onreset cycleNum_C := UInt<3>("h00") - reg cycleNum_E : UInt<3>, clock, reset - onreset cycleNum_E := UInt<3>("h00") - reg fractR0_A : UInt<9>, clock, reset - reg hiSqrR0_A_sqrt : UInt<10>, clock, reset - reg partNegSigma0_A : UInt<21>, clock, reset - reg nextMulAdd9A_A : UInt<9>, clock, reset - reg nextMulAdd9B_A : UInt<9>, clock, reset - reg ER1_B_sqrt : UInt<17>, clock, reset - reg ESqrR1_B_sqrt : UInt<32>, clock, reset - reg sigX1_B : UInt<58>, clock, reset - reg sqrSigma1_C : UInt<33>, clock, reset - reg sigXN_C : UInt<58>, clock, reset - reg u_C_sqrt : UInt<31>, clock, reset - reg E_E_div : UInt<1>, clock, reset - reg sigT_E : UInt<53>, clock, reset - reg extraT_E : UInt<1>, clock, reset - reg isNegRemT_E : UInt<1>, clock, reset - reg trueEqX_E1 : UInt<1>, clock, reset - wire ready_PA : UInt<1> - ready_PA := UInt<1>("h00") - wire ready_PB : UInt<1> - ready_PB := UInt<1>("h00") - wire ready_PC : UInt<1> - ready_PC := UInt<1>("h00") - wire leaving_PA : UInt<1> - leaving_PA := UInt<1>("h00") - wire leaving_PB : UInt<1> - leaving_PB := UInt<1>("h00") - wire leaving_PC : UInt<1> - leaving_PC := UInt<1>("h00") - wire cyc_B10_sqrt : UInt<1> - cyc_B10_sqrt := UInt<1>("h00") - wire cyc_B9_sqrt : UInt<1> - cyc_B9_sqrt := UInt<1>("h00") - wire cyc_B8_sqrt : UInt<1> - cyc_B8_sqrt := UInt<1>("h00") - wire cyc_B7_sqrt : UInt<1> - cyc_B7_sqrt := UInt<1>("h00") - wire cyc_B6 : UInt<1> - cyc_B6 := UInt<1>("h00") - wire cyc_B5 : UInt<1> - cyc_B5 := UInt<1>("h00") - wire cyc_B4 : UInt<1> - cyc_B4 := UInt<1>("h00") - wire cyc_B3 : UInt<1> - cyc_B3 := UInt<1>("h00") - wire cyc_B2 : UInt<1> - cyc_B2 := UInt<1>("h00") - wire cyc_B1 : UInt<1> - cyc_B1 := UInt<1>("h00") - wire cyc_B6_div : UInt<1> - cyc_B6_div := UInt<1>("h00") - wire cyc_B5_div : UInt<1> - cyc_B5_div := UInt<1>("h00") - wire cyc_B4_div : UInt<1> - cyc_B4_div := UInt<1>("h00") - wire cyc_B3_div : UInt<1> - cyc_B3_div := UInt<1>("h00") - wire cyc_B2_div : UInt<1> - cyc_B2_div := UInt<1>("h00") - wire cyc_B1_div : UInt<1> - cyc_B1_div := UInt<1>("h00") - wire cyc_B6_sqrt : UInt<1> - cyc_B6_sqrt := UInt<1>("h00") - wire cyc_B5_sqrt : UInt<1> - cyc_B5_sqrt := UInt<1>("h00") - wire cyc_B4_sqrt : UInt<1> - cyc_B4_sqrt := UInt<1>("h00") - wire cyc_B3_sqrt : UInt<1> - cyc_B3_sqrt := UInt<1>("h00") - wire cyc_B2_sqrt : UInt<1> - cyc_B2_sqrt := UInt<1>("h00") - wire cyc_B1_sqrt : UInt<1> - cyc_B1_sqrt := UInt<1>("h00") - wire cyc_C5 : UInt<1> - cyc_C5 := UInt<1>("h00") - wire cyc_C4 : UInt<1> - cyc_C4 := UInt<1>("h00") - wire valid_normalCase_leaving_PB : UInt<1> - valid_normalCase_leaving_PB := UInt<1>("h00") - wire cyc_C2 : UInt<1> - cyc_C2 := UInt<1>("h00") - wire cyc_C1 : UInt<1> - cyc_C1 := UInt<1>("h00") - wire cyc_E4 : UInt<1> - cyc_E4 := UInt<1>("h00") - wire cyc_E3 : UInt<1> - cyc_E3 := UInt<1>("h00") - wire cyc_E2 : UInt<1> - cyc_E2 := UInt<1>("h00") - wire cyc_E1 : UInt<1> - cyc_E1 := UInt<1>("h00") - wire zSigma1_B4 : UInt - zSigma1_B4 := UInt<1>("h00") - wire sigXNU_B3_CX : UInt - sigXNU_B3_CX := UInt<1>("h00") - wire zComplSigT_C1_sqrt : UInt - zComplSigT_C1_sqrt := UInt<1>("h00") - wire zComplSigT_C1 : UInt - zComplSigT_C1 := UInt<1>("h00") - node T_250 = not(cyc_B6_sqrt) - node T_251 = and(ready_PA, T_250) - node T_252 = not(cyc_B5_sqrt) - node T_253 = and(T_251, T_252) - node T_254 = not(cyc_B4_sqrt) - node T_255 = and(T_253, T_254) - node T_256 = not(cyc_B3) - node T_257 = and(T_255, T_256) - node T_258 = not(cyc_B2) - node T_259 = and(T_257, T_258) - node T_260 = not(cyc_B1_sqrt) - node T_261 = and(T_259, T_260) - node T_262 = not(cyc_C5) - node T_263 = and(T_261, T_262) - node T_264 = not(cyc_C4) - node T_265 = and(T_263, T_264) - inReady_div := T_265 - node T_266 = not(cyc_B6_sqrt) - node T_267 = and(ready_PA, T_266) - node T_268 = not(cyc_B5_sqrt) - node T_269 = and(T_267, T_268) - node T_270 = not(cyc_B4_sqrt) - node T_271 = and(T_269, T_270) - node T_272 = not(cyc_B2_div) - node T_273 = and(T_271, T_272) - node T_274 = not(cyc_B1_sqrt) - node T_275 = and(T_273, T_274) - inReady_sqrt := T_275 - node T_276 = and(inReady_div, inValid) - node T_277 = not(sqrtOp) - node cyc_S_div = and(T_276, T_277) - node T_279 = and(inReady_sqrt, inValid) - node cyc_S_sqrt = and(T_279, sqrtOp) - node cyc_S = or(cyc_S_div, cyc_S_sqrt) - node signA_S = bit(a, 64) - node expA_S = bits(a, 63, 52) - node fractA_S = bits(a, 51, 0) - node specialCodeA_S = bits(expA_S, 11, 9) - node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) - node T_288 = bits(specialCodeA_S, 2, 1) - node isSpecialA_S = eq(T_288, UInt<2>("h03")) - node signB_S = bit(b, 64) - node expB_S = bits(b, 63, 52) - node fractB_S = bits(b, 51, 0) - node specialCodeB_S = bits(expB_S, 11, 9) - node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) - node T_297 = bits(specialCodeB_S, 2, 1) - node isSpecialB_S = eq(T_297, UInt<2>("h03")) - node T_300 = xor(signA_S, signB_S) - node sign_S = mux(sqrtOp, signB_S, T_300) - node T_302 = not(isSpecialA_S) - node T_303 = not(isSpecialB_S) - node T_304 = and(T_302, T_303) - node T_305 = not(isZeroA_S) - node T_306 = and(T_304, T_305) - node T_307 = not(isZeroB_S) - node normalCase_S_div = and(T_306, T_307) - node T_309 = not(isSpecialB_S) - node T_310 = not(isZeroB_S) - node T_311 = and(T_309, T_310) - node T_312 = not(signB_S) - node normalCase_S_sqrt = and(T_311, T_312) - node normalCase_S = mux(sqrtOp, normalCase_S_sqrt, normalCase_S_div) - node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) - node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) - node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) - node T_318 = not(ready_PB) - node T_319 = or(valid_PA, T_318) - node T_320 = and(cyc_S, T_319) - node entering_PA = or(entering_PA_normalCase, T_320) - node T_322 = not(normalCase_S) - node T_323 = and(cyc_S, T_322) - node T_324 = not(valid_PA) - node T_325 = and(T_323, T_324) - node T_326 = not(valid_PB) - node T_327 = not(ready_PC) - node T_328 = and(T_326, T_327) - node T_329 = or(leaving_PB, T_328) - node entering_PB_S = and(T_325, T_329) - node T_331 = not(normalCase_S) - node T_332 = and(cyc_S, T_331) - node T_333 = not(valid_PA) - node T_334 = and(T_332, T_333) - node T_335 = not(valid_PB) - node T_336 = and(T_334, T_335) - node entering_PC_S = and(T_336, ready_PC) - node T_338 = or(entering_PA, leaving_PA) - when T_338 : - valid_PA := entering_PA - skip - when entering_PA : - sqrtOp_PA := sqrtOp - sign_PA := sign_S - specialCodeB_PA := specialCodeB_S - node T_339 = bit(fractB_S, 51) - fractB_51_PA := T_339 - roundingMode_PA := roundingMode - skip - node T_340 = not(sqrtOp) - node T_341 = and(entering_PA, T_340) - when T_341 : - specialCodeA_PA := specialCodeA_S - node T_342 = bit(fractA_S, 51) - fractA_51_PA := T_342 - skip - when entering_PA_normalCase : - node T_343 = bit(expB_S, 11) - node T_345 = subw(UInt<3>("h00"), T_343) - node T_346 = bits(expB_S, 10, 0) - node T_347 = not(T_346) - node T_348 = cat(T_345, T_347) - node T_349 = addw(expA_S, T_348) - node T_350 = mux(sqrtOp, expB_S, T_349) - exp_PA := T_350 - node T_351 = bits(fractB_S, 50, 0) - fractB_other_PA := T_351 - skip - when entering_PA_normalCase_div : - node T_352 = bits(fractA_S, 50, 0) - fractA_other_PA := T_352 - skip - node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) - node T_355 = bits(specialCodeA_PA, 2, 1) - node isSpecialA_PA = eq(T_355, UInt<2>("h03")) - node T_359 = cat(fractA_51_PA, fractA_other_PA) - node sigA_PA = cat(UInt<1>("h01"), T_359) - node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) - node T_363 = bits(specialCodeB_PA, 2, 1) - node isSpecialB_PA = eq(T_363, UInt<2>("h03")) - node T_367 = cat(fractB_51_PA, fractB_other_PA) - node sigB_PA = cat(UInt<1>("h01"), T_367) - node T_369 = not(isSpecialB_PA) - node T_370 = not(isZeroB_PA) - node T_371 = and(T_369, T_370) - node T_372 = not(sign_PA) - node T_373 = and(T_371, T_372) - node T_374 = not(isSpecialA_PA) - node T_375 = not(isSpecialB_PA) - node T_376 = and(T_374, T_375) - node T_377 = not(isZeroA_PA) - node T_378 = and(T_376, T_377) - node T_379 = not(isZeroB_PA) - node T_380 = and(T_378, T_379) - node normalCase_PA = mux(sqrtOp_PA, T_373, T_380) - node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) - node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) - node T_384 = and(valid_PA, valid_leaving_PA) - leaving_PA := T_384 - node T_385 = not(valid_PA) - node T_386 = or(T_385, valid_leaving_PA) - ready_PA := T_386 - node T_387 = and(valid_PA, normalCase_PA) - node entering_PB_normalCase = and(T_387, valid_normalCase_leaving_PA) - node entering_PB = or(entering_PB_S, leaving_PA) - node T_390 = or(entering_PB, leaving_PB) - when T_390 : - valid_PB := entering_PB - skip - when entering_PB : - node T_391 = mux(valid_PA, sqrtOp_PA, sqrtOp) - sqrtOp_PB := T_391 - node T_392 = mux(valid_PA, sign_PA, sign_S) - sign_PB := T_392 - node T_393 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) - specialCodeA_PB := T_393 - node T_394 = bit(fractA_S, 51) - node T_395 = mux(valid_PA, fractA_51_PA, T_394) - fractA_51_PB := T_395 - node T_396 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) - specialCodeB_PB := T_396 - node T_397 = bit(fractB_S, 51) - node T_398 = mux(valid_PA, fractB_51_PA, T_397) - fractB_51_PB := T_398 - node T_399 = mux(valid_PA, roundingMode_PA, roundingMode) - roundingMode_PB := T_399 - skip - when entering_PB_normalCase : - exp_PB := exp_PA - node T_400 = bit(fractA_other_PA, 0) - fractA_0_PB := T_400 - fractB_other_PB := fractB_other_PA - skip - node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) - node T_403 = bits(specialCodeA_PB, 2, 1) - node isSpecialA_PB = eq(T_403, UInt<2>("h03")) - node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) - node T_408 = bits(specialCodeB_PB, 2, 1) - node isSpecialB_PB = eq(T_408, UInt<2>("h03")) - node T_411 = not(isSpecialB_PB) - node T_412 = not(isZeroB_PB) - node T_413 = and(T_411, T_412) - node T_414 = not(sign_PB) - node T_415 = and(T_413, T_414) - node T_416 = not(isSpecialA_PB) - node T_417 = not(isSpecialB_PB) - node T_418 = and(T_416, T_417) - node T_419 = not(isZeroA_PB) - node T_420 = and(T_418, T_419) - node T_421 = not(isZeroB_PB) - node T_422 = and(T_420, T_421) - node normalCase_PB = mux(sqrtOp_PB, T_415, T_422) - node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) - node T_425 = and(valid_PB, valid_leaving_PB) - leaving_PB := T_425 - node T_426 = not(valid_PB) - node T_427 = or(T_426, valid_leaving_PB) - ready_PB := T_427 - node T_428 = and(valid_PB, normalCase_PB) - node entering_PC_normalCase = and(T_428, valid_normalCase_leaving_PB) - node entering_PC = or(entering_PC_S, leaving_PB) - node T_431 = or(entering_PC, leaving_PC) - when T_431 : - valid_PC := entering_PC - skip - when entering_PC : - node T_432 = mux(valid_PB, sqrtOp_PB, sqrtOp) - sqrtOp_PC := T_432 - node T_433 = mux(valid_PB, sign_PB, sign_S) - sign_PC := T_433 - node T_434 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) - specialCodeA_PC := T_434 - node T_435 = bit(fractA_S, 51) - node T_436 = mux(valid_PB, fractA_51_PB, T_435) - fractA_51_PC := T_436 - node T_437 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) - specialCodeB_PC := T_437 - node T_438 = bit(fractB_S, 51) - node T_439 = mux(valid_PB, fractB_51_PB, T_438) - fractB_51_PC := T_439 - node T_440 = mux(valid_PB, roundingMode_PB, roundingMode) - roundingMode_PC := T_440 - skip - when entering_PC_normalCase : - exp_PC := exp_PB - fractA_0_PC := fractA_0_PB - fractB_other_PC := fractB_other_PB - skip - node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) - node T_443 = bits(specialCodeA_PC, 2, 1) - node isSpecialA_PC = eq(T_443, UInt<2>("h03")) - node T_446 = bit(specialCodeA_PC, 0) - node T_447 = not(T_446) - node isInfA_PC = and(isSpecialA_PC, T_447) - node T_449 = bit(specialCodeA_PC, 0) - node isNaNA_PC = and(isSpecialA_PC, T_449) - node T_451 = not(fractA_51_PC) - node isSigNaNA_PC = and(isNaNA_PC, T_451) - node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) - node T_455 = bits(specialCodeB_PC, 2, 1) - node isSpecialB_PC = eq(T_455, UInt<2>("h03")) - node T_458 = bit(specialCodeB_PC, 0) - node T_459 = not(T_458) - node isInfB_PC = and(isSpecialB_PC, T_459) - node T_461 = bit(specialCodeB_PC, 0) - node isNaNB_PC = and(isSpecialB_PC, T_461) - node T_463 = not(fractB_51_PC) - node isSigNaNB_PC = and(isNaNB_PC, T_463) - node T_466 = cat(fractB_51_PC, fractB_other_PC) - node sigB_PC = cat(UInt<1>("h01"), T_466) - node T_468 = not(isSpecialB_PC) - node T_469 = not(isZeroB_PC) - node T_470 = and(T_468, T_469) - node T_471 = not(sign_PC) - node T_472 = and(T_470, T_471) - node T_473 = not(isSpecialA_PC) - node T_474 = not(isSpecialB_PC) - node T_475 = and(T_473, T_474) - node T_476 = not(isZeroA_PC) - node T_477 = and(T_475, T_476) - node T_478 = not(isZeroB_PC) - node T_479 = and(T_477, T_478) - node normalCase_PC = mux(sqrtOp_PC, T_472, T_479) - node expP2_PC = addw(exp_PC, UInt<2>("h02")) - node T_483 = bit(exp_PC, 0) - node T_484 = bits(expP2_PC, 13, 1) - node T_486 = cat(T_484, UInt<1>("h00")) - node T_487 = bits(exp_PC, 13, 1) - node T_489 = cat(T_487, UInt<1>("h01")) - node expP1_PC = mux(T_483, T_486, T_489) - node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) - node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) - node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) - node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) - node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) - node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) - node T_497 = not(roundMagUp_PC) - node T_498 = not(roundingMode_near_even_PC) - node roundMagDown_PC = and(T_497, T_498) - node T_500 = not(normalCase_PC) - node valid_leaving_PC = or(T_500, cyc_E1) - node T_502 = and(valid_PC, valid_leaving_PC) - leaving_PC := T_502 - node T_503 = not(valid_PC) - node T_504 = or(T_503, valid_leaving_PC) - ready_PC := T_504 - node T_505 = not(sqrtOp_PC) - node T_506 = and(leaving_PC, T_505) - outValid_div := T_506 - node T_507 = and(leaving_PC, sqrtOp_PC) - outValid_sqrt := T_507 - node T_509 = neq(cycleNum_A, UInt<1>("h00")) - node T_510 = or(entering_PA_normalCase, T_509) - when T_510 : - node T_513 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) - node T_516 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) - node T_517 = or(T_513, T_516) - node T_518 = not(entering_PA_normalCase) - node T_520 = subw(cycleNum_A, UInt<1>("h01")) - node T_522 = mux(T_518, T_520, UInt<1>("h00")) - node T_523 = or(T_517, T_522) - cycleNum_A := T_523 - skip - node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) - node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) - node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) - node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) - node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) - node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) - node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) - node T_537 = not(sqrtOp_PA) - node cyc_A3_div = and(cyc_A3, T_537) - node T_539 = not(sqrtOp_PA) - node cyc_A2_div = and(cyc_A2, T_539) - node T_541 = not(sqrtOp_PA) - node cyc_A1_div = and(cyc_A1, T_541) - node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) - node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) - node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) - node T_547 = neq(cycleNum_B, UInt<1>("h00")) - node T_548 = or(cyc_A1, T_547) - when T_548 : - node T_551 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) - node T_553 = subw(cycleNum_B, UInt<1>("h01")) - node T_554 = mux(cyc_A1, T_551, T_553) - cycleNum_B := T_554 - skip - node T_556 = eq(cycleNum_B, UInt<4>("h0a")) - cyc_B10_sqrt := T_556 - node T_558 = eq(cycleNum_B, UInt<4>("h09")) - cyc_B9_sqrt := T_558 - node T_560 = eq(cycleNum_B, UInt<4>("h08")) - cyc_B8_sqrt := T_560 - node T_562 = eq(cycleNum_B, UInt<3>("h07")) - cyc_B7_sqrt := T_562 - node T_564 = eq(cycleNum_B, UInt<3>("h06")) - cyc_B6 := T_564 - node T_566 = eq(cycleNum_B, UInt<3>("h05")) - cyc_B5 := T_566 - node T_568 = eq(cycleNum_B, UInt<3>("h04")) - cyc_B4 := T_568 - node T_570 = eq(cycleNum_B, UInt<2>("h03")) - cyc_B3 := T_570 - node T_572 = eq(cycleNum_B, UInt<2>("h02")) - cyc_B2 := T_572 - node T_574 = eq(cycleNum_B, UInt<1>("h01")) - cyc_B1 := T_574 - node T_575 = and(cyc_B6, valid_PA) - node T_576 = not(sqrtOp_PA) - node T_577 = and(T_575, T_576) - cyc_B6_div := T_577 - node T_578 = and(cyc_B5, valid_PA) - node T_579 = not(sqrtOp_PA) - node T_580 = and(T_578, T_579) - cyc_B5_div := T_580 - node T_581 = and(cyc_B4, valid_PA) - node T_582 = not(sqrtOp_PA) - node T_583 = and(T_581, T_582) - cyc_B4_div := T_583 - node T_584 = not(sqrtOp_PB) - node T_585 = and(cyc_B3, T_584) - cyc_B3_div := T_585 - node T_586 = not(sqrtOp_PB) - node T_587 = and(cyc_B2, T_586) - cyc_B2_div := T_587 - node T_588 = not(sqrtOp_PB) - node T_589 = and(cyc_B1, T_588) - cyc_B1_div := T_589 - node T_590 = and(cyc_B6, valid_PB) - node T_591 = and(T_590, sqrtOp_PB) - cyc_B6_sqrt := T_591 - node T_592 = and(cyc_B5, valid_PB) - node T_593 = and(T_592, sqrtOp_PB) - cyc_B5_sqrt := T_593 - node T_594 = and(cyc_B4, valid_PB) - node T_595 = and(T_594, sqrtOp_PB) - cyc_B4_sqrt := T_595 - node T_596 = and(cyc_B3, sqrtOp_PB) - cyc_B3_sqrt := T_596 - node T_597 = and(cyc_B2, sqrtOp_PB) - cyc_B2_sqrt := T_597 - node T_598 = and(cyc_B1, sqrtOp_PB) - cyc_B1_sqrt := T_598 - node T_600 = neq(cycleNum_C, UInt<1>("h00")) - node T_601 = or(cyc_B1, T_600) - when T_601 : - node T_604 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) - node T_606 = subw(cycleNum_C, UInt<1>("h01")) - node T_607 = mux(cyc_B1, T_604, T_606) - cycleNum_C := T_607 - skip - node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) - node T_611 = eq(cycleNum_C, UInt<3>("h05")) - cyc_C5 := T_611 - node T_613 = eq(cycleNum_C, UInt<3>("h04")) - cyc_C4 := T_613 - node T_615 = eq(cycleNum_C, UInt<2>("h03")) - valid_normalCase_leaving_PB := T_615 - node T_617 = eq(cycleNum_C, UInt<2>("h02")) - cyc_C2 := T_617 - node T_619 = eq(cycleNum_C, UInt<1>("h01")) - cyc_C1 := T_619 - node T_620 = not(sqrtOp_PB) - node cyc_C5_div = and(cyc_C5, T_620) - node T_622 = not(sqrtOp_PB) - node cyc_C4_div = and(cyc_C4, T_622) - node T_624 = not(sqrtOp_PB) - node cyc_C3_div = and(valid_normalCase_leaving_PB, T_624) - node T_626 = not(sqrtOp_PC) - node cyc_C2_div = and(cyc_C2, T_626) - node T_628 = not(sqrtOp_PC) - node cyc_C1_div = and(cyc_C1, T_628) - node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) - node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) - node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) - node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) - node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) - node T_636 = neq(cycleNum_E, UInt<1>("h00")) - node T_637 = or(cyc_C1, T_636) - when T_637 : - node T_640 = subw(cycleNum_E, UInt<1>("h01")) - node T_641 = mux(cyc_C1, UInt<3>("h04"), T_640) - cycleNum_E := T_641 - skip - node T_643 = eq(cycleNum_E, UInt<3>("h04")) - cyc_E4 := T_643 - node T_645 = eq(cycleNum_E, UInt<2>("h03")) - cyc_E3 := T_645 - node T_647 = eq(cycleNum_E, UInt<2>("h02")) - cyc_E2 := T_647 - node T_649 = eq(cycleNum_E, UInt<1>("h01")) - cyc_E1 := T_649 - node T_650 = not(sqrtOp_PC) - node cyc_E4_div = and(cyc_E4, T_650) - node T_652 = not(sqrtOp_PC) - node cyc_E3_div = and(cyc_E3, T_652) - node T_654 = not(sqrtOp_PC) - node cyc_E2_div = and(cyc_E2, T_654) - node T_656 = not(sqrtOp_PC) - node cyc_E1_div = and(cyc_E1, T_656) - node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) - node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) - node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) - node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) - node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) - node T_664 = bits(fractB_S, 51, 49) - node T_666 = eq(T_664, UInt<1>("h00")) - node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_666) - node T_668 = bits(fractB_S, 51, 49) - node T_670 = eq(T_668, UInt<1>("h01")) - node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_670) - node T_672 = bits(fractB_S, 51, 49) - node T_674 = eq(T_672, UInt<2>("h02")) - node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_674) - node T_676 = bits(fractB_S, 51, 49) - node T_678 = eq(T_676, UInt<2>("h03")) - node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_678) - node T_680 = bits(fractB_S, 51, 49) - node T_682 = eq(T_680, UInt<3>("h04")) - node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_682) - node T_684 = bits(fractB_S, 51, 49) - node T_686 = eq(T_684, UInt<3>("h05")) - node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_686) - node T_688 = bits(fractB_S, 51, 49) - node T_690 = eq(T_688, UInt<3>("h06")) - node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_690) - node T_692 = bits(fractB_S, 51, 49) - node T_694 = eq(T_692, UInt<3>("h07")) - node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_694) - node T_698 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) - node T_701 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) - node T_702 = or(T_698, T_701) - node T_705 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) - node T_706 = or(T_702, T_705) - node T_709 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) - node T_710 = or(T_706, T_709) - node T_713 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) - node T_714 = or(T_710, T_713) - node T_717 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) - node T_718 = or(T_714, T_717) - node T_721 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) - node T_722 = or(T_718, T_721) - node T_725 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) - node zK1_A4_div = or(T_722, T_725) - node T_728 = not(UInt<12>("h0fe3")) - node T_730 = mux(zLinPiece_0_A4_div, T_728, UInt<1>("h00")) - node T_732 = not(UInt<12>("h0c5d")) - node T_734 = mux(zLinPiece_1_A4_div, T_732, UInt<1>("h00")) - node T_735 = or(T_730, T_734) - node T_737 = not(UInt<12>("h098a")) - node T_739 = mux(zLinPiece_2_A4_div, T_737, UInt<1>("h00")) - node T_740 = or(T_735, T_739) - node T_742 = not(UInt<12>("h0739")) - node T_744 = mux(zLinPiece_3_A4_div, T_742, UInt<1>("h00")) - node T_745 = or(T_740, T_744) - node T_747 = not(UInt<12>("h054b")) - node T_749 = mux(zLinPiece_4_A4_div, T_747, UInt<1>("h00")) - node T_750 = or(T_745, T_749) - node T_752 = not(UInt<12>("h03a9")) - node T_754 = mux(zLinPiece_5_A4_div, T_752, UInt<1>("h00")) - node T_755 = or(T_750, T_754) - node T_757 = not(UInt<12>("h0242")) - node T_759 = mux(zLinPiece_6_A4_div, T_757, UInt<1>("h00")) - node T_760 = or(T_755, T_759) - node T_762 = not(UInt<12>("h010b")) - node T_764 = mux(zLinPiece_7_A4_div, T_762, UInt<1>("h00")) - node zComplFractK0_A4_div = or(T_760, T_764) - node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) - node T_768 = bit(expB_S, 0) - node T_769 = not(T_768) - node T_770 = and(entering_PA_normalCase_sqrt, T_769) - node T_771 = bit(fractB_S, 51) - node T_772 = not(T_771) - node zQuadPiece_0_A7_sqrt = and(T_770, T_772) - node T_774 = bit(expB_S, 0) - node T_775 = not(T_774) - node T_776 = and(entering_PA_normalCase_sqrt, T_775) - node T_777 = bit(fractB_S, 51) - node zQuadPiece_1_A7_sqrt = and(T_776, T_777) - node T_779 = bit(expB_S, 0) - node T_780 = and(entering_PA_normalCase_sqrt, T_779) - node T_781 = bit(fractB_S, 51) - node T_782 = not(T_781) - node zQuadPiece_2_A7_sqrt = and(T_780, T_782) - node T_784 = bit(expB_S, 0) - node T_785 = and(entering_PA_normalCase_sqrt, T_784) - node T_786 = bit(fractB_S, 51) - node zQuadPiece_3_A7_sqrt = and(T_785, T_786) - node T_790 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) - node T_793 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) - node T_794 = or(T_790, T_793) - node T_797 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) - node T_798 = or(T_794, T_797) - node T_801 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) - node zK2_A7_sqrt = or(T_798, T_801) - node T_804 = not(UInt<10>("h03d0")) - node T_806 = mux(zQuadPiece_0_A7_sqrt, T_804, UInt<1>("h00")) - node T_808 = not(UInt<10>("h0220")) - node T_810 = mux(zQuadPiece_1_A7_sqrt, T_808, UInt<1>("h00")) - node T_811 = or(T_806, T_810) - node T_813 = not(UInt<10>("h02b2")) - node T_815 = mux(zQuadPiece_2_A7_sqrt, T_813, UInt<1>("h00")) - node T_816 = or(T_811, T_815) - node T_818 = not(UInt<10>("h0181")) - node T_820 = mux(zQuadPiece_3_A7_sqrt, T_818, UInt<1>("h00")) - node zComplK1_A7_sqrt = or(T_816, T_820) - node T_822 = bit(exp_PA, 0) - node T_823 = not(T_822) - node T_824 = and(cyc_A6_sqrt, T_823) - node T_825 = bit(sigB_PA, 51) - node T_826 = not(T_825) - node zQuadPiece_0_A6_sqrt = and(T_824, T_826) - node T_828 = bit(exp_PA, 0) - node T_829 = not(T_828) - node T_830 = and(cyc_A6_sqrt, T_829) - node T_831 = bit(sigB_PA, 51) - node zQuadPiece_1_A6_sqrt = and(T_830, T_831) - node T_833 = bit(exp_PA, 0) - node T_834 = and(cyc_A6_sqrt, T_833) - node T_835 = bit(sigB_PA, 51) - node T_836 = not(T_835) - node zQuadPiece_2_A6_sqrt = and(T_834, T_836) - node T_838 = bit(exp_PA, 0) - node T_839 = and(cyc_A6_sqrt, T_838) - node T_840 = bit(sigB_PA, 51) - node zQuadPiece_3_A6_sqrt = and(T_839, T_840) - node T_843 = not(UInt<13>("h01fe5")) - node T_845 = mux(zQuadPiece_0_A6_sqrt, T_843, UInt<1>("h00")) - node T_847 = not(UInt<13>("h01435")) - node T_849 = mux(zQuadPiece_1_A6_sqrt, T_847, UInt<1>("h00")) - node T_850 = or(T_845, T_849) - node T_852 = not(UInt<13>("h0d2c")) - node T_854 = mux(zQuadPiece_2_A6_sqrt, T_852, UInt<1>("h00")) - node T_855 = or(T_850, T_854) - node T_857 = not(UInt<13>("h04e8")) - node T_859 = mux(zQuadPiece_3_A6_sqrt, T_857, UInt<1>("h00")) - node zComplFractK0_A6_sqrt = or(T_855, T_859) - node T_861 = bits(zFractB_A4_div, 48, 40) - node T_862 = or(T_861, zK2_A7_sqrt) - node T_863 = not(cyc_S) - node T_865 = mux(T_863, nextMulAdd9A_A, UInt<1>("h00")) - node mulAdd9A_A = or(T_862, T_865) - node T_867 = bits(zFractB_A7_sqrt, 50, 42) - node T_868 = or(zK1_A4_div, T_867) - node T_869 = not(cyc_S) - node T_871 = mux(T_869, nextMulAdd9B_A, UInt<1>("h00")) - node mulAdd9B_A = or(T_868, T_871) - node T_873 = shl(zComplK1_A7_sqrt, 10) - node T_875 = subw(UInt<6>("h00"), cyc_A6_sqrt) - node T_876 = cat(zComplFractK0_A6_sqrt, T_875) - node T_877 = cat(cyc_A6_sqrt, T_876) - node T_878 = or(T_873, T_877) - node T_880 = subw(UInt<8>("h00"), entering_PA_normalCase_div) - node T_881 = cat(zComplFractK0_A4_div, T_880) - node T_882 = cat(entering_PA_normalCase_div, T_881) - node T_883 = or(T_878, T_882) - node T_885 = shl(fractR0_A, 10) - node T_886 = addw(UInt<20>("h040000"), T_885) - node T_888 = mux(cyc_A5_sqrt, T_886, UInt<1>("h00")) - node T_889 = or(T_883, T_888) - node T_890 = bit(hiSqrR0_A_sqrt, 9) - node T_891 = not(T_890) - node T_892 = and(cyc_A4_sqrt, T_891) - node T_895 = mux(T_892, UInt<11>("h0400"), UInt<1>("h00")) - node T_896 = or(T_889, T_895) - node T_897 = bit(hiSqrR0_A_sqrt, 9) - node T_898 = and(cyc_A4_sqrt, T_897) - node T_899 = or(T_898, cyc_A3_div) - node T_900 = bits(sigB_PA, 46, 26) - node T_902 = addw(T_900, UInt<11>("h0400")) - node T_904 = mux(T_899, T_902, UInt<1>("h00")) - node T_905 = or(T_896, T_904) - node T_906 = or(cyc_A3_sqrt, cyc_A2) - node T_908 = mux(T_906, partNegSigma0_A, UInt<1>("h00")) - node T_909 = or(T_905, T_908) - node T_910 = shl(fractR0_A, 16) - node T_912 = mux(cyc_A1_sqrt, T_910, UInt<1>("h00")) - node T_913 = or(T_909, T_912) - node T_914 = shl(fractR0_A, 15) - node T_916 = mux(cyc_A1_div, T_914, UInt<1>("h00")) - node mulAdd9C_A = or(T_913, T_916) - node T_918 = mul(mulAdd9A_A, mulAdd9B_A) - node T_920 = bits(mulAdd9C_A, 17, 0) - node T_921 = cat(UInt<1>("h00"), T_920) - node loMulAdd9Out_A = addw(T_918, T_921) - node T_923 = bit(loMulAdd9Out_A, 18) - node T_924 = bits(mulAdd9C_A, 24, 18) - node T_926 = addw(T_924, UInt<1>("h01")) - node T_927 = bits(mulAdd9C_A, 24, 18) - node T_928 = mux(T_923, T_926, T_927) - node T_929 = bits(loMulAdd9Out_A, 17, 0) - node mulAdd9Out_A = cat(T_928, T_929) - node T_931 = bit(mulAdd9Out_A, 19) - node T_932 = and(cyc_A6_sqrt, T_931) - node T_933 = not(mulAdd9Out_A) - node T_934 = shr(T_933, 10) - node T_936 = mux(T_932, T_934, UInt<1>("h00")) - node zFractR0_A6_sqrt = bits(T_936, 8, 0) - node T_938 = bit(exp_PA, 0) - node T_939 = shl(mulAdd9Out_A, 1) - node sqrR0_A5_sqrt = mux(T_938, T_939, mulAdd9Out_A) - node T_941 = bit(mulAdd9Out_A, 20) - node T_942 = and(entering_PA_normalCase_div, T_941) - node T_943 = not(mulAdd9Out_A) - node T_944 = shr(T_943, 11) - node T_946 = mux(T_942, T_944, UInt<1>("h00")) - node zFractR0_A4_div = bits(T_946, 8, 0) - node T_948 = bit(mulAdd9Out_A, 11) - node T_949 = and(cyc_A2, T_948) - node T_950 = not(mulAdd9Out_A) - node T_951 = shr(T_950, 2) - node T_953 = mux(T_949, T_951, UInt<1>("h00")) - node zSigma0_A2 = bits(T_953, 8, 0) - node T_955 = shr(mulAdd9Out_A, 10) - node T_956 = shr(mulAdd9Out_A, 9) - node T_957 = mux(sqrtOp_PA, T_955, T_956) - node fractR1_A1 = bits(T_957, 14, 0) - node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) - node T_961 = bit(exp_PA, 0) - node T_962 = shl(r1_A1, 1) - node ER1_A1_sqrt = mux(T_961, T_962, r1_A1) - node T_964 = or(cyc_A6_sqrt, entering_PA_normalCase_div) - when T_964 : - node T_965 = or(zFractR0_A6_sqrt, zFractR0_A4_div) - fractR0_A := T_965 - skip - when cyc_A5_sqrt : - node T_966 = shr(sqrR0_A5_sqrt, 10) - hiSqrR0_A_sqrt := T_966 - skip - node T_967 = or(cyc_A4_sqrt, cyc_A3) - when T_967 : - node T_968 = shr(mulAdd9Out_A, 9) - node T_969 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_968) - node T_970 = bits(T_969, 20, 0) - partNegSigma0_A := T_970 - skip - node T_971 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_972 = or(T_971, cyc_A5_sqrt) - node T_973 = or(T_972, cyc_A4) - node T_974 = or(T_973, cyc_A3) - node T_975 = or(T_974, cyc_A2) - when T_975 : - node T_976 = not(mulAdd9Out_A) - node T_977 = shr(T_976, 11) - node T_979 = mux(entering_PA_normalCase_sqrt, T_977, UInt<1>("h00")) - node T_980 = or(T_979, zFractR0_A6_sqrt) - node T_981 = bits(sigB_PA, 43, 35) - node T_983 = mux(cyc_A4_sqrt, T_981, UInt<1>("h00")) - node T_984 = or(T_980, T_983) - node T_985 = bits(zFractB_A4_div, 43, 35) - node T_986 = or(T_984, T_985) - node T_987 = or(cyc_A5_sqrt, cyc_A3) - node T_988 = bits(sigB_PA, 52, 44) - node T_990 = mux(T_987, T_988, UInt<1>("h00")) - node T_991 = or(T_986, T_990) - node T_992 = or(T_991, zSigma0_A2) - nextMulAdd9A_A := T_992 - skip - node T_993 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_994 = or(T_993, cyc_A5_sqrt) - node T_995 = or(T_994, cyc_A4) - node T_996 = or(T_995, cyc_A2) - when T_996 : - node T_997 = bits(zFractB_A7_sqrt, 50, 42) - node T_998 = or(T_997, zFractR0_A6_sqrt) - node T_999 = bits(sqrR0_A5_sqrt, 9, 1) - node T_1001 = mux(cyc_A5_sqrt, T_999, UInt<1>("h00")) - node T_1002 = or(T_998, T_1001) - node T_1003 = or(T_1002, zFractR0_A4_div) - node T_1004 = bits(hiSqrR0_A_sqrt, 8, 0) - node T_1006 = mux(cyc_A4_sqrt, T_1004, UInt<1>("h00")) - node T_1007 = or(T_1003, T_1006) - node T_1009 = bits(fractR0_A, 8, 1) - node T_1010 = cat(UInt<1>("h01"), T_1009) - node T_1012 = mux(cyc_A2, T_1010, UInt<1>("h00")) - node T_1013 = or(T_1007, T_1012) - nextMulAdd9B_A := T_1013 - skip - when cyc_A1_sqrt : - ER1_B_sqrt := ER1_A1_sqrt - skip - node T_1014 = or(cyc_A1, cyc_B7_sqrt) - node T_1015 = or(T_1014, cyc_B6_div) - node T_1016 = or(T_1015, cyc_B4) - node T_1017 = or(T_1016, cyc_B3) - node T_1018 = or(T_1017, cyc_C6_sqrt) - node T_1019 = or(T_1018, cyc_C4) - node T_1020 = or(T_1019, cyc_C1) - latchMulAddA_0 := T_1020 - node T_1021 = shl(ER1_A1_sqrt, 36) - node T_1023 = mux(cyc_A1_sqrt, T_1021, UInt<1>("h00")) - node T_1024 = or(cyc_B7_sqrt, cyc_A1_div) - node T_1026 = mux(T_1024, sigB_PA, UInt<1>("h00")) - node T_1027 = or(T_1023, T_1026) - node T_1029 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) - node T_1030 = or(T_1027, T_1029) - node T_1031 = bits(zSigma1_B4, 45, 12) - node T_1032 = or(T_1030, T_1031) - node T_1033 = or(cyc_B3, cyc_C6_sqrt) - node T_1034 = bits(sigXNU_B3_CX, 57, 12) - node T_1036 = mux(T_1033, T_1034, UInt<1>("h00")) - node T_1037 = or(T_1032, T_1036) - node T_1038 = bits(sigXN_C, 57, 25) - node T_1039 = shl(T_1038, 13) - node T_1041 = mux(cyc_C4_div, T_1039, UInt<1>("h00")) - node T_1042 = or(T_1037, T_1041) - node T_1043 = shl(u_C_sqrt, 15) - node T_1045 = mux(cyc_C4_sqrt, T_1043, UInt<1>("h00")) - node T_1046 = or(T_1042, T_1045) - node T_1048 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) - node T_1049 = or(T_1046, T_1048) - node T_1050 = or(T_1049, zComplSigT_C1_sqrt) - mulAddA_0 := T_1050 - node T_1051 = or(cyc_A1, cyc_B7_sqrt) - node T_1052 = or(T_1051, cyc_B6_sqrt) - node T_1053 = or(T_1052, cyc_B4) - node T_1054 = or(T_1053, cyc_C6_sqrt) - node T_1055 = or(T_1054, cyc_C4) - node T_1056 = or(T_1055, cyc_C1) - latchMulAddB_0 := T_1056 - node T_1057 = shl(r1_A1, 36) - node T_1059 = mux(cyc_A1, T_1057, UInt<1>("h00")) - node T_1060 = shl(ESqrR1_B_sqrt, 19) - node T_1062 = mux(cyc_B7_sqrt, T_1060, UInt<1>("h00")) - node T_1063 = or(T_1059, T_1062) - node T_1064 = shl(ER1_B_sqrt, 36) - node T_1066 = mux(cyc_B6_sqrt, T_1064, UInt<1>("h00")) - node T_1067 = or(T_1063, T_1066) - node T_1068 = or(T_1067, zSigma1_B4) - node T_1069 = bits(sqrSigma1_C, 30, 1) - node T_1071 = mux(cyc_C6_sqrt, T_1069, UInt<1>("h00")) - node T_1072 = or(T_1068, T_1071) - node T_1074 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) - node T_1075 = or(T_1072, T_1074) - node T_1076 = or(T_1075, zComplSigT_C1) - mulAddB_0 := T_1076 - node T_1077 = or(cyc_A4, cyc_A3_div) - node T_1078 = or(T_1077, cyc_A1_div) - node T_1079 = or(T_1078, cyc_B10_sqrt) - node T_1080 = or(T_1079, cyc_B9_sqrt) - node T_1081 = or(T_1080, cyc_B7_sqrt) - node T_1082 = or(T_1081, cyc_B6) - node T_1083 = or(T_1082, cyc_B5_sqrt) - node T_1084 = or(T_1083, cyc_B3_sqrt) - node T_1085 = or(T_1084, cyc_B2_div) - node T_1086 = or(T_1085, cyc_B1_sqrt) - node T_1087 = or(T_1086, cyc_C4) - node T_1088 = or(cyc_A3, cyc_A2_div) - node T_1089 = or(T_1088, cyc_B9_sqrt) - node T_1090 = or(T_1089, cyc_B8_sqrt) - node T_1091 = or(T_1090, cyc_B6) - node T_1092 = or(T_1091, cyc_B5) - node T_1093 = or(T_1092, cyc_B4_sqrt) - node T_1094 = or(T_1093, cyc_B2_sqrt) - node T_1095 = or(T_1094, cyc_B1_div) - node T_1096 = or(T_1095, cyc_C6_sqrt) - node T_1097 = or(T_1096, valid_normalCase_leaving_PB) - node T_1098 = or(cyc_A2, cyc_A1_div) - node T_1099 = or(T_1098, cyc_B8_sqrt) - node T_1100 = or(T_1099, cyc_B7_sqrt) - node T_1101 = or(T_1100, cyc_B5) - node T_1102 = or(T_1101, cyc_B4) - node T_1103 = or(T_1102, cyc_B3_sqrt) - node T_1104 = or(T_1103, cyc_B1_sqrt) - node T_1105 = or(T_1104, cyc_C5) - node T_1106 = or(T_1105, cyc_C2) - node T_1107 = or(latchMulAddA_0, cyc_B6) - node T_1108 = or(T_1107, cyc_B2_sqrt) - node T_1109 = cat(T_1087, T_1097) - node T_1110 = cat(T_1106, T_1108) - node T_1111 = cat(T_1109, T_1110) - usingMulAdd := T_1111 - node T_1112 = shl(sigX1_B, 47) - node T_1114 = mux(cyc_B1, T_1112, UInt<1>("h00")) - node T_1115 = shl(sigX1_B, 46) - node T_1117 = mux(cyc_C6_sqrt, T_1115, UInt<1>("h00")) - node T_1118 = or(T_1114, T_1117) - node T_1119 = or(cyc_C4_sqrt, cyc_C2) - node T_1120 = shl(sigXN_C, 47) - node T_1122 = mux(T_1119, T_1120, UInt<1>("h00")) - node T_1123 = or(T_1118, T_1122) - node T_1124 = not(E_E_div) - node T_1125 = and(cyc_E3_div, T_1124) - node T_1126 = shl(fractA_0_PC, 53) - node T_1128 = mux(T_1125, T_1126, UInt<1>("h00")) - node T_1129 = or(T_1123, T_1128) - node T_1130 = bit(exp_PC, 0) - node T_1131 = bit(sigB_PC, 0) - node T_1133 = cat(T_1131, UInt<1>("h00")) - node T_1134 = bit(sigB_PC, 1) - node T_1135 = bit(sigB_PC, 0) - node T_1136 = xor(T_1134, T_1135) - node T_1137 = bit(sigB_PC, 0) - node T_1138 = cat(T_1136, T_1137) - node T_1139 = mux(T_1130, T_1133, T_1138) - node T_1140 = not(extraT_E) - node T_1142 = cat(T_1140, UInt<1>("h00")) - node T_1143 = xor(T_1139, T_1142) - node T_1144 = shl(T_1143, 54) - node T_1146 = mux(cyc_E3_sqrt, T_1144, UInt<1>("h00")) - node T_1147 = or(T_1129, T_1146) - mulAddC_2 := T_1147 - node ESqrR1_B8_sqrt = bits(mulAddResult_3, 103, 72) - node T_1149 = bits(mulAddResult_3, 90, 45) - node T_1150 = not(T_1149) - node T_1152 = mux(cyc_B4, T_1150, UInt<1>("h00")) - zSigma1_B4 := T_1152 - node sqrSigma1_B1 = bits(mulAddResult_3, 79, 47) - node T_1154 = bits(mulAddResult_3, 104, 47) - sigXNU_B3_CX := T_1154 - node T_1155 = bit(mulAddResult_3, 104) - node E_C1_div = not(T_1155) - node T_1157 = not(E_C1_div) - node T_1158 = and(cyc_C1_div, T_1157) - node T_1159 = or(T_1158, cyc_C1_sqrt) - node T_1160 = bits(mulAddResult_3, 104, 51) - node T_1161 = not(T_1160) - node T_1163 = mux(T_1159, T_1161, UInt<1>("h00")) - node T_1164 = and(cyc_C1_div, E_C1_div) - node T_1166 = bits(mulAddResult_3, 102, 50) - node T_1167 = not(T_1166) - node T_1168 = cat(UInt<1>("h00"), T_1167) - node T_1170 = mux(T_1164, T_1168, UInt<1>("h00")) - node T_1171 = or(T_1163, T_1170) - zComplSigT_C1 := T_1171 - node T_1172 = bits(mulAddResult_3, 104, 51) - node T_1173 = not(T_1172) - node T_1175 = mux(cyc_C1_sqrt, T_1173, UInt<1>("h00")) - zComplSigT_C1_sqrt := T_1175 - node sigT_C1 = not(zComplSigT_C1) - node remT_E2 = bits(mulAddResult_3, 55, 0) - when cyc_B8_sqrt : - ESqrR1_B_sqrt := ESqrR1_B8_sqrt - skip - when cyc_B3 : - sigX1_B := sigXNU_B3_CX - skip - when cyc_B1 : - sqrSigma1_C := sqrSigma1_B1 - skip - node T_1178 = or(cyc_C6_sqrt, cyc_C5_div) - node T_1179 = or(T_1178, cyc_C3_sqrt) - when T_1179 : - sigXN_C := sigXNU_B3_CX - skip - when cyc_C5_sqrt : - node T_1180 = bits(sigXNU_B3_CX, 56, 26) - u_C_sqrt := T_1180 - skip - when cyc_C1 : - E_E_div := E_C1_div - node T_1181 = bits(sigT_C1, 53, 1) - sigT_E := T_1181 - node T_1182 = bit(sigT_C1, 0) - extraT_E := T_1182 - skip - when cyc_E2 : - node T_1183 = bit(remT_E2, 55) - node T_1184 = bit(remT_E2, 53) - node T_1185 = mux(sqrtOp_PC, T_1183, T_1184) - isNegRemT_E := T_1185 - node T_1186 = bits(remT_E2, 53, 0) - node T_1188 = eq(T_1186, UInt<1>("h00")) - node T_1189 = not(sqrtOp_PC) - node T_1190 = bits(remT_E2, 55, 54) - node T_1192 = eq(T_1190, UInt<1>("h00")) - node T_1193 = or(T_1189, T_1192) - node T_1194 = and(T_1188, T_1193) - trueEqX_E1 := T_1194 - skip - node T_1195 = not(sqrtOp_PC) - node T_1196 = and(T_1195, E_E_div) - node T_1198 = mux(T_1196, exp_PC, UInt<1>("h00")) - node T_1199 = not(sqrtOp_PC) - node T_1200 = not(E_E_div) - node T_1201 = and(T_1199, T_1200) - node T_1203 = mux(T_1201, expP1_PC, UInt<1>("h00")) - node T_1204 = or(T_1198, T_1203) - node T_1205 = shr(exp_PC, 1) - node T_1207 = addw(T_1205, UInt<12>("h0400")) - node T_1209 = mux(sqrtOp_PC, T_1207, UInt<1>("h00")) - node sExpX_E = or(T_1204, T_1209) - node posExpX_E = bits(sExpX_E, 12, 0) - node T_1212 = bits(posExpX_E, 12, 6) - node posExpX_0001111_E = eq(T_1212, UInt<7>("h0f")) - node T_1215 = bit(posExpX_E, 5) - node T_1216 = not(T_1215) - node posExpX_00011110_E = and(posExpX_0001111_E, T_1216) - node T_1218 = bit(posExpX_E, 4) - node T_1219 = not(T_1218) - node posExpX_000111100_E = and(posExpX_00011110_E, T_1219) - node T_1221 = bits(sExpX_E, 2, 0) - node exp3X_lt_001_E = lt(T_1221, UInt<3>("h01")) - node T_1224 = bits(sExpX_E, 2, 0) - node exp3X_lt_010_E = lt(T_1224, UInt<3>("h02")) - node T_1227 = bits(sExpX_E, 2, 0) - node exp3X_lt_011_E = lt(T_1227, UInt<3>("h03")) - node T_1230 = bits(sExpX_E, 2, 0) - node exp3X_lt_100_E = lt(T_1230, UInt<3>("h04")) - node T_1233 = bits(sExpX_E, 2, 0) - node exp3X_lt_101_E = lt(T_1233, UInt<3>("h05")) - node T_1236 = bits(sExpX_E, 2, 0) - node exp3X_lt_110_E = lt(T_1236, UInt<3>("h06")) - node T_1239 = bits(sExpX_E, 2, 0) - node exp3X_lt_111_E = lt(T_1239, UInt<3>("h07")) - node T_1242 = bits(sExpX_E, 4, 3) - node exp5X_lt_01000_E = eq(T_1242, UInt<2>("h00")) - node T_1245 = bits(sExpX_E, 4, 3) - node exp5X_01_E = eq(T_1245, UInt<2>("h01")) - node T_1248 = bits(sExpX_E, 4, 3) - node exp5X_10_E = eq(T_1248, UInt<2>("h02")) - node exp5X_lt_00001_E = and(exp5X_lt_01000_E, exp3X_lt_001_E) - node exp5X_lt_00010_E = and(exp5X_lt_01000_E, exp3X_lt_010_E) - node exp5X_lt_00011_E = and(exp5X_lt_01000_E, exp3X_lt_011_E) - node exp5X_lt_00100_E = and(exp5X_lt_01000_E, exp3X_lt_100_E) - node exp5X_lt_00101_E = and(exp5X_lt_01000_E, exp3X_lt_101_E) - node exp5X_lt_00110_E = and(exp5X_lt_01000_E, exp3X_lt_110_E) - node exp5X_lt_00111_E = and(exp5X_lt_01000_E, exp3X_lt_111_E) - node T_1258 = and(exp5X_01_E, exp3X_lt_001_E) - node exp5X_lt_01001_E = or(exp5X_lt_01000_E, T_1258) - node T_1260 = and(exp5X_01_E, exp3X_lt_010_E) - node exp5X_lt_01010_E = or(exp5X_lt_01000_E, T_1260) - node T_1262 = and(exp5X_01_E, exp3X_lt_011_E) - node exp5X_lt_01011_E = or(exp5X_lt_01000_E, T_1262) - node T_1264 = and(exp5X_01_E, exp3X_lt_100_E) - node exp5X_lt_01100_E = or(exp5X_lt_01000_E, T_1264) - node T_1266 = and(exp5X_01_E, exp3X_lt_101_E) - node exp5X_lt_01101_E = or(exp5X_lt_01000_E, T_1266) - node T_1268 = and(exp5X_01_E, exp3X_lt_110_E) - node exp5X_lt_01110_E = or(exp5X_lt_01000_E, T_1268) - node T_1270 = and(exp5X_01_E, exp3X_lt_111_E) - node exp5X_lt_01111_E = or(exp5X_lt_01000_E, T_1270) - node T_1272 = bit(sExpX_E, 4) - node exp5X_lt_10000_E = not(T_1272) - node T_1274 = bit(sExpX_E, 4) - node T_1275 = not(T_1274) - node T_1276 = and(exp5X_10_E, exp3X_lt_001_E) - node exp5X_lt_10001_E = or(T_1275, T_1276) - node T_1278 = bit(sExpX_E, 4) - node T_1279 = not(T_1278) - node T_1280 = and(exp5X_10_E, exp3X_lt_010_E) - node exp5X_lt_10010_E = or(T_1279, T_1280) - node T_1282 = bit(sExpX_E, 4) - node T_1283 = not(T_1282) - node T_1284 = and(exp5X_10_E, exp3X_lt_011_E) - node exp5X_lt_10011_E = or(T_1283, T_1284) - node T_1286 = bit(sExpX_E, 4) - node T_1287 = not(T_1286) - node T_1288 = and(exp5X_10_E, exp3X_lt_100_E) - node exp5X_lt_10100_E = or(T_1287, T_1288) - node T_1290 = bit(sExpX_E, 4) - node T_1291 = not(T_1290) - node T_1292 = and(exp5X_10_E, exp3X_lt_101_E) - node exp5X_lt_10101_E = or(T_1291, T_1292) - node T_1294 = bit(sExpX_E, 4) - node T_1295 = not(T_1294) - node T_1296 = and(exp5X_10_E, exp3X_lt_110_E) - node exp5X_lt_10110_E = or(T_1295, T_1296) - node T_1298 = bit(sExpX_E, 4) - node T_1299 = not(T_1298) - node T_1300 = and(exp5X_10_E, exp3X_lt_111_E) - node exp5X_lt_10111_E = or(T_1299, T_1300) - node T_1302 = bits(sExpX_E, 4, 3) - node exp5X_lt_11000_E = neq(T_1302, UInt<2>("h03")) - node exp5X_lt_11001_E = or(exp5X_lt_11000_E, exp3X_lt_001_E) - node exp5X_lt_11010_E = or(exp5X_lt_11000_E, exp3X_lt_010_E) - node exp5X_lt_11011_E = or(exp5X_lt_11000_E, exp3X_lt_011_E) - node exp5X_lt_11100_E = or(exp5X_lt_11000_E, exp3X_lt_100_E) - node exp5X_lt_11101_E = or(exp5X_lt_11000_E, exp3X_lt_101_E) - node exp5X_lt_11110_E = or(exp5X_lt_11000_E, exp3X_lt_110_E) - node exp5X_lt_11111_E = or(exp5X_lt_11000_E, exp3X_lt_111_E) - node T_1312 = bits(sExpX_E, 3, 0) - node T_1314 = lt(T_1312, UInt<4>("h0e")) - node T_1315 = and(posExpX_000111100_E, T_1314) - node T_1316 = bits(sExpX_E, 3, 0) - node T_1318 = lt(T_1316, UInt<4>("h0f")) - node T_1319 = and(posExpX_000111100_E, T_1318) - node T_1320 = and(posExpX_00011110_E, exp5X_lt_10001_E) - node T_1321 = and(posExpX_00011110_E, exp5X_lt_10010_E) - node T_1322 = and(posExpX_00011110_E, exp5X_lt_10011_E) - node T_1323 = and(posExpX_00011110_E, exp5X_lt_10100_E) - node T_1324 = and(posExpX_00011110_E, exp5X_lt_10101_E) - node T_1325 = and(posExpX_00011110_E, exp5X_lt_10110_E) - node T_1326 = and(posExpX_00011110_E, exp5X_lt_10111_E) - node T_1327 = and(posExpX_00011110_E, exp5X_lt_11000_E) - node T_1328 = and(posExpX_00011110_E, exp5X_lt_11001_E) - node T_1329 = and(posExpX_00011110_E, exp5X_lt_11010_E) - node T_1330 = and(posExpX_00011110_E, exp5X_lt_11011_E) - node T_1331 = and(posExpX_00011110_E, exp5X_lt_11100_E) - node T_1332 = and(posExpX_00011110_E, exp5X_lt_11101_E) - node T_1333 = and(posExpX_00011110_E, exp5X_lt_11110_E) - node T_1334 = and(posExpX_00011110_E, exp5X_lt_11111_E) - node T_1335 = bit(sExpX_E, 5) - node T_1336 = not(T_1335) - node T_1337 = or(T_1336, exp5X_lt_00001_E) - node T_1338 = and(posExpX_0001111_E, T_1337) - node T_1339 = bit(sExpX_E, 5) - node T_1340 = not(T_1339) - node T_1341 = or(T_1340, exp5X_lt_00010_E) - node T_1342 = and(posExpX_0001111_E, T_1341) - node T_1343 = bit(sExpX_E, 5) - node T_1344 = not(T_1343) - node T_1345 = or(T_1344, exp5X_lt_00011_E) - node T_1346 = and(posExpX_0001111_E, T_1345) - node T_1347 = bit(sExpX_E, 5) - node T_1348 = not(T_1347) - node T_1349 = or(T_1348, exp5X_lt_00100_E) - node T_1350 = and(posExpX_0001111_E, T_1349) - node T_1351 = bit(sExpX_E, 5) - node T_1352 = not(T_1351) - node T_1353 = or(T_1352, exp5X_lt_00101_E) - node T_1354 = and(posExpX_0001111_E, T_1353) - node T_1355 = bit(sExpX_E, 5) - node T_1356 = not(T_1355) - node T_1357 = or(T_1356, exp5X_lt_00110_E) - node T_1358 = and(posExpX_0001111_E, T_1357) - node T_1359 = bit(sExpX_E, 5) - node T_1360 = not(T_1359) - node T_1361 = or(T_1360, exp5X_lt_00111_E) - node T_1362 = and(posExpX_0001111_E, T_1361) - node T_1363 = bit(sExpX_E, 5) - node T_1364 = not(T_1363) - node T_1365 = or(T_1364, exp5X_lt_01000_E) - node T_1366 = and(posExpX_0001111_E, T_1365) - node T_1367 = bit(sExpX_E, 5) - node T_1368 = not(T_1367) - node T_1369 = or(T_1368, exp5X_lt_01001_E) - node T_1370 = and(posExpX_0001111_E, T_1369) - node T_1371 = bit(sExpX_E, 5) - node T_1372 = not(T_1371) - node T_1373 = or(T_1372, exp5X_lt_01010_E) - node T_1374 = and(posExpX_0001111_E, T_1373) - node T_1375 = bit(sExpX_E, 5) - node T_1376 = not(T_1375) - node T_1377 = or(T_1376, exp5X_lt_01011_E) - node T_1378 = and(posExpX_0001111_E, T_1377) - node T_1379 = bit(sExpX_E, 5) - node T_1380 = not(T_1379) - node T_1381 = or(T_1380, exp5X_lt_01100_E) - node T_1382 = and(posExpX_0001111_E, T_1381) - node T_1383 = bit(sExpX_E, 5) - node T_1384 = not(T_1383) - node T_1385 = or(T_1384, exp5X_lt_01101_E) - node T_1386 = and(posExpX_0001111_E, T_1385) - node T_1387 = bit(sExpX_E, 5) - node T_1388 = not(T_1387) - node T_1389 = or(T_1388, exp5X_lt_01110_E) - node T_1390 = and(posExpX_0001111_E, T_1389) - node T_1391 = bit(sExpX_E, 5) - node T_1392 = not(T_1391) - node T_1393 = or(T_1392, exp5X_lt_01111_E) - node T_1394 = and(posExpX_0001111_E, T_1393) - node T_1395 = bit(sExpX_E, 5) - node T_1396 = not(T_1395) - node T_1397 = or(T_1396, exp5X_lt_10000_E) - node T_1398 = and(posExpX_0001111_E, T_1397) - node T_1399 = bit(sExpX_E, 5) - node T_1400 = not(T_1399) - node T_1401 = or(T_1400, exp5X_lt_10001_E) - node T_1402 = and(posExpX_0001111_E, T_1401) - node T_1403 = bit(sExpX_E, 5) - node T_1404 = not(T_1403) - node T_1405 = or(T_1404, exp5X_lt_10010_E) - node T_1406 = and(posExpX_0001111_E, T_1405) - node T_1407 = bit(sExpX_E, 5) - node T_1408 = not(T_1407) - node T_1409 = or(T_1408, exp5X_lt_10011_E) - node T_1410 = and(posExpX_0001111_E, T_1409) - node T_1411 = bit(sExpX_E, 5) - node T_1412 = not(T_1411) - node T_1413 = or(T_1412, exp5X_lt_10100_E) - node T_1414 = and(posExpX_0001111_E, T_1413) - node T_1415 = bit(sExpX_E, 5) - node T_1416 = not(T_1415) - node T_1417 = or(T_1416, exp5X_lt_10101_E) - node T_1418 = and(posExpX_0001111_E, T_1417) - node T_1419 = bit(sExpX_E, 5) - node T_1420 = not(T_1419) - node T_1421 = or(T_1420, exp5X_lt_10110_E) - node T_1422 = and(posExpX_0001111_E, T_1421) - node T_1423 = bit(sExpX_E, 5) - node T_1424 = not(T_1423) - node T_1425 = or(T_1424, exp5X_lt_10111_E) - node T_1426 = and(posExpX_0001111_E, T_1425) - node T_1427 = bit(sExpX_E, 5) - node T_1428 = not(T_1427) - node T_1429 = or(T_1428, exp5X_lt_11000_E) - node T_1430 = and(posExpX_0001111_E, T_1429) - node T_1431 = bit(sExpX_E, 5) - node T_1432 = not(T_1431) - node T_1433 = or(T_1432, exp5X_lt_11001_E) - node T_1434 = and(posExpX_0001111_E, T_1433) - node T_1435 = bit(sExpX_E, 5) - node T_1436 = not(T_1435) - node T_1437 = or(T_1436, exp5X_lt_11010_E) - node T_1438 = and(posExpX_0001111_E, T_1437) - node T_1439 = bit(sExpX_E, 5) - node T_1440 = not(T_1439) - node T_1441 = or(T_1440, exp5X_lt_11011_E) - node T_1442 = and(posExpX_0001111_E, T_1441) - node T_1443 = bit(sExpX_E, 5) - node T_1444 = not(T_1443) - node T_1445 = or(T_1444, exp5X_lt_11100_E) - node T_1446 = and(posExpX_0001111_E, T_1445) - node T_1447 = bit(sExpX_E, 5) - node T_1448 = not(T_1447) - node T_1449 = or(T_1448, exp5X_lt_11101_E) - node T_1450 = and(posExpX_0001111_E, T_1449) - node T_1451 = bit(sExpX_E, 5) - node T_1452 = not(T_1451) - node T_1453 = or(T_1452, exp5X_lt_11110_E) - node T_1454 = and(posExpX_0001111_E, T_1453) - node T_1455 = bit(sExpX_E, 5) - node T_1456 = not(T_1455) - node T_1457 = or(T_1456, exp5X_lt_11111_E) - node T_1458 = and(posExpX_0001111_E, T_1457) - node T_1460 = lt(posExpX_E, UInt<13>("h0401")) - node T_1462 = lt(posExpX_E, UInt<13>("h0402")) - node T_1463 = cat(T_1319, posExpX_000111100_E) - node T_1464 = cat(T_1315, T_1463) - node T_1465 = cat(T_1321, T_1322) - node T_1466 = cat(T_1320, T_1465) - node T_1467 = cat(T_1464, T_1466) - node T_1468 = cat(T_1324, T_1325) - node T_1469 = cat(T_1323, T_1468) - node T_1470 = cat(T_1326, T_1327) - node T_1471 = cat(T_1328, T_1329) - node T_1472 = cat(T_1470, T_1471) - node T_1473 = cat(T_1469, T_1472) - node T_1474 = cat(T_1467, T_1473) - node T_1475 = cat(T_1331, T_1332) - node T_1476 = cat(T_1330, T_1475) - node T_1477 = cat(T_1334, posExpX_00011110_E) - node T_1478 = cat(T_1333, T_1477) - node T_1479 = cat(T_1476, T_1478) - node T_1480 = cat(T_1342, T_1346) - node T_1481 = cat(T_1338, T_1480) - node T_1482 = cat(T_1350, T_1354) - node T_1483 = cat(T_1358, T_1362) - node T_1484 = cat(T_1482, T_1483) - node T_1485 = cat(T_1481, T_1484) - node T_1486 = cat(T_1479, T_1485) - node T_1487 = cat(T_1474, T_1486) - node T_1488 = cat(T_1370, T_1374) - node T_1489 = cat(T_1366, T_1488) - node T_1490 = cat(T_1382, T_1386) - node T_1491 = cat(T_1378, T_1490) - node T_1492 = cat(T_1489, T_1491) - node T_1493 = cat(T_1394, T_1398) - node T_1494 = cat(T_1390, T_1493) - node T_1495 = cat(T_1402, T_1406) - node T_1496 = cat(T_1410, T_1414) - node T_1497 = cat(T_1495, T_1496) - node T_1498 = cat(T_1494, T_1497) - node T_1499 = cat(T_1492, T_1498) - node T_1500 = cat(T_1422, T_1426) - node T_1501 = cat(T_1418, T_1500) - node T_1502 = cat(T_1430, T_1434) - node T_1503 = cat(T_1438, T_1442) - node T_1504 = cat(T_1502, T_1503) - node T_1505 = cat(T_1501, T_1504) - node T_1506 = cat(T_1450, T_1454) - node T_1507 = cat(T_1446, T_1506) - node T_1508 = cat(T_1458, posExpX_0001111_E) - node T_1509 = cat(T_1460, T_1462) - node T_1510 = cat(T_1508, T_1509) - node T_1511 = cat(T_1507, T_1510) - node T_1512 = cat(T_1505, T_1511) - node T_1513 = cat(T_1499, T_1512) - node roundMask_E = cat(T_1487, T_1513) - node T_1516 = cat(UInt<1>("h00"), roundMask_E) - node T_1517 = not(T_1516) - node T_1519 = cat(roundMask_E, UInt<1>("h01")) - node incrPosMask_E = and(T_1517, T_1519) - node T_1521 = shr(incrPosMask_E, 1) - node T_1522 = and(sigT_E, T_1521) - node hiRoundPosBitT_E = neq(T_1522, UInt<1>("h00")) - node T_1525 = shr(roundMask_E, 1) - node T_1526 = and(sigT_E, T_1525) - node all0sHiRoundExtraT_E = eq(T_1526, UInt<1>("h00")) - node T_1529 = not(sigT_E) - node T_1530 = shr(roundMask_E, 1) - node T_1531 = and(T_1529, T_1530) - node all1sHiRoundExtraT_E = eq(T_1531, UInt<1>("h00")) - node T_1534 = bit(roundMask_E, 0) - node T_1535 = not(T_1534) - node T_1536 = or(T_1535, hiRoundPosBitT_E) - node all1sHiRoundT_E = and(T_1536, all1sHiRoundExtraT_E) - node T_1539 = addw(UInt<54>("h00"), sigT_E) - node sigAdjT_E = addw(T_1539, roundMagUp_PC) - node T_1542 = not(roundMask_E) - node T_1543 = cat(UInt<1>("h01"), T_1542) - node sigY0_E = and(sigAdjT_E, T_1543) - node T_1546 = cat(UInt<1>("h00"), roundMask_E) - node T_1547 = or(sigAdjT_E, T_1546) - node sigY1_E = addw(T_1547, UInt<1>("h01")) - node T_1550 = not(isNegRemT_E) - node T_1551 = not(trueEqX_E1) - node T_1552 = and(T_1550, T_1551) - node trueLtX_E1 = mux(sqrtOp_PC, T_1552, isNegRemT_E) - node T_1554 = bit(roundMask_E, 0) - node T_1555 = not(trueLtX_E1) - node T_1556 = and(T_1554, T_1555) - node T_1557 = and(T_1556, all1sHiRoundExtraT_E) - node T_1558 = and(T_1557, extraT_E) - node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1558) - node T_1560 = not(trueEqX_E1) - node T_1561 = not(extraT_E) - node T_1562 = or(T_1560, T_1561) - node T_1563 = not(all1sHiRoundExtraT_E) - node anyRoundExtra_E1 = or(T_1562, T_1563) - node T_1565 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) - node T_1566 = not(anyRoundExtra_E1) - node T_1567 = and(T_1565, T_1566) - node roundEvenMask_E1 = mux(T_1567, incrPosMask_E, UInt<1>("h00")) - node T_1570 = and(roundMagDown_PC, extraT_E) - node T_1571 = not(trueLtX_E1) - node T_1572 = and(T_1570, T_1571) - node T_1573 = and(T_1572, all1sHiRoundT_E) - node T_1574 = not(trueLtX_E1) - node T_1575 = and(extraT_E, T_1574) - node T_1576 = not(trueEqX_E1) - node T_1577 = and(T_1575, T_1576) - node T_1578 = not(all1sHiRoundT_E) - node T_1579 = or(T_1577, T_1578) - node T_1580 = and(roundMagUp_PC, T_1579) - node T_1581 = or(T_1573, T_1580) - node T_1582 = not(trueLtX_E1) - node T_1583 = or(extraT_E, T_1582) - node T_1584 = bit(roundMask_E, 0) - node T_1585 = not(T_1584) - node T_1586 = and(T_1583, T_1585) - node T_1587 = or(hiRoundPosBitT_E, T_1586) - node T_1588 = not(trueLtX_E1) - node T_1589 = and(extraT_E, T_1588) - node T_1590 = and(T_1589, all1sHiRoundExtraT_E) - node T_1591 = or(T_1587, T_1590) - node T_1592 = and(roundingMode_near_even_PC, T_1591) - node T_1593 = or(T_1581, T_1592) - node T_1594 = mux(T_1593, sigY1_E, sigY0_E) - node T_1595 = not(roundEvenMask_E1) - node sigY_E1 = and(T_1594, T_1595) - node fractY_E1 = bits(sigY_E1, 51, 0) - node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) - node T_1599 = bit(sigY_E1, 53) - node T_1600 = not(T_1599) - node T_1602 = mux(T_1600, sExpX_E, UInt<1>("h00")) - node T_1603 = bit(sigY_E1, 53) - node T_1604 = not(sqrtOp_PC) - node T_1605 = and(T_1603, T_1604) - node T_1606 = and(T_1605, E_E_div) - node T_1608 = mux(T_1606, expP1_PC, UInt<1>("h00")) - node T_1609 = or(T_1602, T_1608) - node T_1610 = bit(sigY_E1, 53) - node T_1611 = not(sqrtOp_PC) - node T_1612 = and(T_1610, T_1611) - node T_1613 = not(E_E_div) - node T_1614 = and(T_1612, T_1613) - node T_1616 = mux(T_1614, expP2_PC, UInt<1>("h00")) - node T_1617 = or(T_1609, T_1616) - node T_1618 = bit(sigY_E1, 53) - node T_1619 = and(T_1618, sqrtOp_PC) - node T_1620 = shr(expP2_PC, 1) - node T_1622 = addw(T_1620, UInt<12>("h0400")) - node T_1624 = mux(T_1619, T_1622, UInt<1>("h00")) - node sExpY_E1 = or(T_1617, T_1624) - node expY_E1 = bits(sExpY_E1, 11, 0) - node T_1627 = bit(sExpY_E1, 13) - node T_1628 = not(T_1627) - node T_1630 = bits(sExpY_E1, 12, 10) - node T_1631 = leq(UInt<3>("h03"), T_1630) - node overflowY_E1 = and(T_1628, T_1631) - node T_1633 = bit(sExpY_E1, 13) - node T_1634 = bits(sExpY_E1, 12, 0) - node T_1636 = lt(T_1634, UInt<13>("h03ce")) - node totalUnderflowY_E1 = or(T_1633, T_1636) - node T_1639 = leq(posExpX_E, UInt<13>("h0401")) - node T_1640 = and(T_1639, inexactY_E1) - node underflowY_E1 = or(totalUnderflowY_E1, T_1640) - node T_1642 = not(isNaNB_PC) - node T_1643 = not(isZeroB_PC) - node T_1644 = and(T_1642, T_1643) - node T_1645 = and(T_1644, sign_PC) - node T_1646 = and(isZeroA_PC, isZeroB_PC) - node T_1647 = and(isInfA_PC, isInfB_PC) - node T_1648 = or(T_1646, T_1647) - node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1645, T_1648) - node T_1650 = not(sqrtOp_PC) - node T_1651 = and(T_1650, isSigNaNA_PC) - node T_1652 = or(T_1651, isSigNaNB_PC) - node invalid_PC = or(T_1652, notSigNaN_invalid_PC) - node T_1654 = not(sqrtOp_PC) - node T_1655 = not(isSpecialA_PC) - node T_1656 = and(T_1654, T_1655) - node T_1657 = not(isZeroA_PC) - node T_1658 = and(T_1656, T_1657) - node infinity_PC = and(T_1658, isZeroB_PC) - node overflow_E1 = and(normalCase_PC, overflowY_E1) - node underflow_E1 = and(normalCase_PC, underflowY_E1) - node T_1662 = or(overflow_E1, underflow_E1) - node T_1663 = and(normalCase_PC, inexactY_E1) - node inexact_E1 = or(T_1662, T_1663) - node T_1665 = or(isZeroA_PC, isInfB_PC) - node T_1666 = not(roundMagUp_PC) - node T_1667 = and(totalUnderflowY_E1, T_1666) - node T_1668 = or(T_1665, T_1667) - node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1668) - node T_1670 = and(normalCase_PC, totalUnderflowY_E1) - node pegMinFiniteMagOut_E1 = and(T_1670, roundMagUp_PC) - node T_1672 = not(overflowY_roundMagUp_PC) - node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1672) - node T_1674 = or(isInfA_PC, isZeroB_PC) - node T_1675 = and(overflow_E1, overflowY_roundMagUp_PC) - node T_1676 = or(T_1674, T_1675) - node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1676) - node T_1678 = not(sqrtOp_PC) - node T_1679 = and(T_1678, isNaNA_PC) - node T_1680 = or(T_1679, isNaNB_PC) - node isNaNOut_PC = or(T_1680, notSigNaN_invalid_PC) - node T_1682 = and(isZeroB_PC, sign_PC) - node T_1683 = mux(sqrtOp_PC, T_1682, sign_PC) - node signOut_PC = or(isNaNOut_PC, T_1683) - node T_1686 = not(UInt<12>("h01ff")) - node T_1688 = mux(notSpecial_isZeroOut_E1, T_1686, UInt<1>("h00")) - node T_1689 = not(T_1688) - node T_1690 = and(expY_E1, T_1689) - node T_1692 = not(UInt<12>("h03ce")) - node T_1694 = mux(pegMinFiniteMagOut_E1, T_1692, UInt<1>("h00")) - node T_1695 = not(T_1694) - node T_1696 = and(T_1690, T_1695) - node T_1698 = not(UInt<12>("h0bff")) - node T_1700 = mux(pegMaxFiniteMagOut_E1, T_1698, UInt<1>("h00")) - node T_1701 = not(T_1700) - node T_1702 = and(T_1696, T_1701) - node T_1704 = not(UInt<12>("h0dff")) - node T_1706 = mux(notNaN_isInfOut_E1, T_1704, UInt<1>("h00")) - node T_1707 = not(T_1706) - node T_1708 = and(T_1702, T_1707) - node T_1711 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) - node T_1712 = or(T_1708, T_1711) - node T_1715 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) - node T_1716 = or(T_1712, T_1715) - node T_1719 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) - node T_1720 = or(T_1716, T_1719) - node T_1723 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) - node expOut_E1 = or(T_1720, T_1723) - node T_1725 = and(totalUnderflowY_E1, roundMagUp_PC) - node T_1727 = mux(T_1725, UInt<1>("h00"), fractY_E1) - node T_1728 = or(isNaNOut_PC, pegMaxFiniteMagOut_E1) - node T_1731 = mux(T_1728, UInt<52>("h0fffffffffffff"), UInt<1>("h00")) - node fractOut_E1 = or(T_1727, T_1731) - node T_1733 = cat(expOut_E1, fractOut_E1) - node T_1734 = cat(signOut_PC, T_1733) - out := T_1734 - node T_1735 = cat(invalid_PC, infinity_PC) - node T_1736 = cat(underflow_E1, inexact_E1) - node T_1737 = cat(overflow_E1, T_1736) - node T_1738 = cat(T_1735, T_1737) - exceptionFlags := T_1738 - - module mul54 : - output result_s3 : UInt<105> - input c_s2 : UInt<105> - input b_s0 : UInt<54> - input latch_b_s0 : UInt<1> - input a_s0 : UInt<54> - input latch_a_s0 : UInt<1> - input val_s0 : UInt<1> - input clock : Clock - input reset : UInt<1> - - result_s3 := UInt<1>("h00") - reg val_s1 : UInt<1>, clock, reset - reg val_s2 : UInt<1>, clock, reset - reg reg_a_s1 : UInt<54>, clock, reset - reg reg_b_s1 : UInt<54>, clock, reset - reg reg_a_s2 : UInt<54>, clock, reset - reg reg_b_s2 : UInt<54>, clock, reset - reg reg_result_s3 : UInt<105>, clock, reset - val_s1 := val_s0 - val_s2 := val_s1 - when val_s0 : - when latch_a_s0 : - reg_a_s1 := a_s0 - skip - when latch_b_s0 : - reg_b_s1 := b_s0 - skip - skip - when val_s1 : - reg_a_s2 := reg_a_s1 - reg_b_s2 := reg_b_s1 - skip - when val_s2 : - node T_24 = mul(reg_a_s2, reg_b_s2) - node T_25 = addw(T_24, c_s2) - reg_result_s3 := T_25 - skip - result_s3 := reg_result_s3 - - module divSqrtRecodedFloat64 : - output exceptionFlags : UInt<5> - output out : UInt<65> - output outValid_sqrt : UInt<1> - output outValid_div : UInt<1> - input roundingMode : UInt<2> - input b : UInt<65> - input a : UInt<65> - input sqrtOp : UInt<1> - input inValid : UInt<1> - output inReady_sqrt : UInt<1> - output inReady_div : UInt<1> - input clock : Clock - input reset : UInt<1> - - exceptionFlags := UInt<1>("h00") - out := UInt<1>("h00") - outValid_sqrt := UInt<1>("h00") - outValid_div := UInt<1>("h00") - inReady_sqrt := UInt<1>("h00") - inReady_div := UInt<1>("h00") - inst ds of divSqrtRecodedFloat64_mulAddZ31 - ds.mulAddResult_3 := UInt<1>("h00") - ds.roundingMode := UInt<1>("h00") - ds.b := UInt<1>("h00") - ds.a := UInt<1>("h00") - ds.sqrtOp := UInt<1>("h00") - ds.inValid := UInt<1>("h00") - ds.reset := UInt<1>("h00") - ds.clock := clock - ds.reset := reset - inReady_div := ds.inReady_div - inReady_sqrt := ds.inReady_sqrt - ds.inValid := inValid - ds.sqrtOp := sqrtOp - ds.a := a - ds.b := b - ds.roundingMode := roundingMode - outValid_div := ds.outValid_div - outValid_sqrt := ds.outValid_sqrt - out := ds.out - exceptionFlags := ds.exceptionFlags - inst mul of mul54 - mul.c_s2 := UInt<1>("h00") - mul.b_s0 := UInt<1>("h00") - mul.latch_b_s0 := UInt<1>("h00") - mul.a_s0 := UInt<1>("h00") - mul.latch_a_s0 := UInt<1>("h00") - mul.val_s0 := UInt<1>("h00") - mul.reset := UInt<1>("h00") - mul.clock := clock - mul.reset := reset - node T_28 = bit(ds.usingMulAdd, 0) - mul.val_s0 := T_28 - mul.latch_a_s0 := ds.latchMulAddA_0 - mul.a_s0 := ds.mulAddA_0 - mul.latch_b_s0 := ds.latchMulAddB_0 - mul.b_s0 := ds.mulAddB_0 - mul.c_s2 := ds.mulAddC_2 - ds.mulAddResult_3 := mul.result_s3 - - module FPU : - output sboard_clra : UInt<5> - output sboard_clr : UInt<1> - output sboard_set : UInt<1> - output dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - input killm : UInt<1> - input killx : UInt<1> - output illegal_rm : UInt<1> - output nack_mem : UInt<1> - output fcsr_rdy : UInt<1> - input valid : UInt<1> - input dmem_resp_data : UInt<64> - input dmem_resp_tag : UInt<5> - input dmem_resp_type : UInt<3> - input dmem_resp_val : UInt<1> - output toint_data : UInt<64> - output store_data : UInt<64> - output fcsr_flags : {valid : UInt<1>, bits : UInt<5>} - input fcsr_rm : UInt<3> - input fromint_data : UInt<64> - input inst_1 : UInt<32> - input clock : Clock - input reset : UInt<1> - - sboard_clra := UInt<1>("h00") - sboard_clr := UInt<1>("h00") - sboard_set := UInt<1>("h00") - dec.wflags := UInt<1>("h00") - dec.round := UInt<1>("h00") - dec.sqrt := UInt<1>("h00") - dec.div := UInt<1>("h00") - dec.fma := UInt<1>("h00") - dec.fastpipe := UInt<1>("h00") - dec.toint := UInt<1>("h00") - dec.fromint := UInt<1>("h00") - dec.single := UInt<1>("h00") - dec.swap23 := UInt<1>("h00") - dec.swap12 := UInt<1>("h00") - dec.ren3 := UInt<1>("h00") - dec.ren2 := UInt<1>("h00") - dec.ren1 := UInt<1>("h00") - dec.wen := UInt<1>("h00") - dec.ldst := UInt<1>("h00") - dec.cmd := UInt<1>("h00") - illegal_rm := UInt<1>("h00") - nack_mem := UInt<1>("h00") - fcsr_rdy := UInt<1>("h00") - toint_data := UInt<1>("h00") - store_data := UInt<1>("h00") - fcsr_flags.bits := UInt<1>("h00") - fcsr_flags.valid := UInt<1>("h00") - reg ex_reg_valid : UInt<1>, clock, reset - onreset ex_reg_valid := UInt<1>("h00") - ex_reg_valid := valid - reg ex_reg_inst : UInt<32>, clock, reset - when valid : - ex_reg_inst := inst_1 - skip - node T_69 = eq(killx, UInt<1>("h00")) - node T_70 = and(ex_reg_valid, T_69) - reg mem_reg_valid : UInt<1>, clock, reset - onreset mem_reg_valid := UInt<1>("h00") - mem_reg_valid := T_70 - reg mem_reg_inst : UInt<32>, clock, reset - when ex_reg_valid : - mem_reg_inst := ex_reg_inst - skip - node killm_2 = or(killm, nack_mem) - node T_76 = eq(killm_2, UInt<1>("h00")) - node T_77 = and(mem_reg_valid, T_76) - reg wb_reg_valid : UInt<1>, clock, reset - onreset wb_reg_valid := UInt<1>("h00") - wb_reg_valid := T_77 - inst fp_decoder of FPUDecoder - fp_decoder.inst_1 := UInt<1>("h00") - fp_decoder.reset := UInt<1>("h00") - fp_decoder.clock := clock - fp_decoder.reset := reset - fp_decoder.inst_1 := inst_1 - reg ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset - when valid : - ex_ctrl <> fp_decoder.sigs - skip - reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset - when ex_reg_valid : - mem_ctrl <> ex_ctrl - skip - reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset - when mem_reg_valid : - wb_ctrl <> mem_ctrl - skip - reg load_wb : UInt<1>, clock, reset - load_wb := dmem_resp_val - node T_137 = eq(dmem_resp_type, UInt<3>("h02")) - node T_138 = eq(dmem_resp_type, UInt<3>("h06")) - node T_139 = or(T_137, T_138) - reg load_wb_single : UInt<1>, clock, reset - when dmem_resp_val : - load_wb_single := T_139 - skip - reg load_wb_data : UInt<64>, clock, reset - when dmem_resp_val : - load_wb_data := dmem_resp_data - skip - reg load_wb_tag : UInt<5>, clock, reset - when dmem_resp_val : - load_wb_tag := dmem_resp_tag - skip - node T_143 = bit(load_wb_data, 31) - node T_144 = bits(load_wb_data, 30, 23) - node T_145 = bits(load_wb_data, 22, 0) - node T_147 = eq(T_144, UInt<1>("h00")) - node T_149 = eq(T_145, UInt<1>("h00")) - node T_150 = and(T_147, T_149) - node T_152 = eq(T_149, UInt<1>("h00")) - node T_153 = and(T_147, T_152) - node T_154 = shl(T_145, 9) - node T_155 = bit(T_154, 31) - node T_157 = bit(T_154, 30) - node T_159 = bit(T_154, 29) - node T_161 = bit(T_154, 28) - node T_163 = bit(T_154, 27) - node T_165 = bit(T_154, 26) - node T_167 = bit(T_154, 25) - node T_169 = bit(T_154, 24) - node T_171 = bit(T_154, 23) - node T_173 = bit(T_154, 22) - node T_175 = bit(T_154, 21) - node T_177 = bit(T_154, 20) - node T_179 = bit(T_154, 19) - node T_181 = bit(T_154, 18) - node T_183 = bit(T_154, 17) - node T_185 = bit(T_154, 16) - node T_187 = bit(T_154, 15) - node T_189 = bit(T_154, 14) - node T_191 = bit(T_154, 13) - node T_193 = bit(T_154, 12) - node T_195 = bit(T_154, 11) - node T_197 = bit(T_154, 10) - node T_199 = bit(T_154, 9) - node T_201 = bit(T_154, 8) - node T_203 = bit(T_154, 7) - node T_205 = bit(T_154, 6) - node T_207 = bit(T_154, 5) - node T_209 = bit(T_154, 4) - node T_211 = bit(T_154, 3) - node T_213 = bit(T_154, 2) - node T_215 = bit(T_154, 1) - node T_216 = shl(T_215, 0) - node T_217 = mux(T_213, UInt<2>("h02"), T_216) - node T_218 = mux(T_211, UInt<2>("h03"), T_217) - node T_219 = mux(T_209, UInt<3>("h04"), T_218) - node T_220 = mux(T_207, UInt<3>("h05"), T_219) - node T_221 = mux(T_205, UInt<3>("h06"), T_220) - node T_222 = mux(T_203, UInt<3>("h07"), T_221) - node T_223 = mux(T_201, UInt<4>("h08"), T_222) - node T_224 = mux(T_199, UInt<4>("h09"), T_223) - node T_225 = mux(T_197, UInt<4>("h0a"), T_224) - node T_226 = mux(T_195, UInt<4>("h0b"), T_225) - node T_227 = mux(T_193, UInt<4>("h0c"), T_226) - node T_228 = mux(T_191, UInt<4>("h0d"), T_227) - node T_229 = mux(T_189, UInt<4>("h0e"), T_228) - node T_230 = mux(T_187, UInt<4>("h0f"), T_229) - node T_231 = mux(T_185, UInt<5>("h010"), T_230) - node T_232 = mux(T_183, UInt<5>("h011"), T_231) - node T_233 = mux(T_181, UInt<5>("h012"), T_232) - node T_234 = mux(T_179, UInt<5>("h013"), T_233) - node T_235 = mux(T_177, UInt<5>("h014"), T_234) - node T_236 = mux(T_175, UInt<5>("h015"), T_235) - node T_237 = mux(T_173, UInt<5>("h016"), T_236) - node T_238 = mux(T_171, UInt<5>("h017"), T_237) - node T_239 = mux(T_169, UInt<5>("h018"), T_238) - node T_240 = mux(T_167, UInt<5>("h019"), T_239) - node T_241 = mux(T_165, UInt<5>("h01a"), T_240) - node T_242 = mux(T_163, UInt<5>("h01b"), T_241) - node T_243 = mux(T_161, UInt<5>("h01c"), T_242) - node T_244 = mux(T_159, UInt<5>("h01d"), T_243) - node T_245 = mux(T_157, UInt<5>("h01e"), T_244) - node T_246 = mux(T_155, UInt<5>("h01f"), T_245) - node T_247 = not(T_246) - node T_248 = dshl(T_154, T_247) - node T_251 = subw(UInt<4>("h00"), UInt<1>("h01")) - node T_252 = not(T_247) - node T_253 = cat(T_251, T_252) - node T_254 = bits(T_248, 30, 8) - node T_256 = mux(T_149, UInt<1>("h00"), T_253) - node T_257 = mux(T_147, T_256, T_144) - node T_262 = mux(T_153, UInt<2>("h02"), UInt<1>("h01")) - node T_263 = or(UInt<8>("h080"), T_262) - node T_264 = mux(T_150, UInt<1>("h00"), T_263) - node T_265 = addw(T_257, T_264) - node T_266 = bits(T_265, 8, 7) - node T_267 = not(T_266) - node T_269 = eq(T_267, UInt<1>("h00")) - node T_271 = eq(T_149, UInt<1>("h00")) - node T_272 = and(T_269, T_271) - node T_273 = shl(T_272, 6) - node T_274 = or(T_265, T_273) - node T_275 = mux(T_147, T_254, T_145) - node T_276 = cat(T_274, T_275) - node rec_s = cat(T_143, T_276) - node T_278 = bit(load_wb_data, 63) - node T_279 = bits(load_wb_data, 62, 52) - node T_280 = bits(load_wb_data, 51, 0) - node T_282 = eq(T_279, UInt<1>("h00")) - node T_284 = eq(T_280, UInt<1>("h00")) - node T_285 = and(T_282, T_284) - node T_287 = eq(T_284, UInt<1>("h00")) - node T_288 = and(T_282, T_287) - node T_289 = shl(T_280, 12) - node T_290 = bit(T_289, 63) - node T_292 = bit(T_289, 62) - node T_294 = bit(T_289, 61) - node T_296 = bit(T_289, 60) - node T_298 = bit(T_289, 59) - node T_300 = bit(T_289, 58) - node T_302 = bit(T_289, 57) - node T_304 = bit(T_289, 56) - node T_306 = bit(T_289, 55) - node T_308 = bit(T_289, 54) - node T_310 = bit(T_289, 53) - node T_312 = bit(T_289, 52) - node T_314 = bit(T_289, 51) - node T_316 = bit(T_289, 50) - node T_318 = bit(T_289, 49) - node T_320 = bit(T_289, 48) - node T_322 = bit(T_289, 47) - node T_324 = bit(T_289, 46) - node T_326 = bit(T_289, 45) - node T_328 = bit(T_289, 44) - node T_330 = bit(T_289, 43) - node T_332 = bit(T_289, 42) - node T_334 = bit(T_289, 41) - node T_336 = bit(T_289, 40) - node T_338 = bit(T_289, 39) - node T_340 = bit(T_289, 38) - node T_342 = bit(T_289, 37) - node T_344 = bit(T_289, 36) - node T_346 = bit(T_289, 35) - node T_348 = bit(T_289, 34) - node T_350 = bit(T_289, 33) - node T_352 = bit(T_289, 32) - node T_354 = bit(T_289, 31) - node T_356 = bit(T_289, 30) - node T_358 = bit(T_289, 29) - node T_360 = bit(T_289, 28) - node T_362 = bit(T_289, 27) - node T_364 = bit(T_289, 26) - node T_366 = bit(T_289, 25) - node T_368 = bit(T_289, 24) - node T_370 = bit(T_289, 23) - node T_372 = bit(T_289, 22) - node T_374 = bit(T_289, 21) - node T_376 = bit(T_289, 20) - node T_378 = bit(T_289, 19) - node T_380 = bit(T_289, 18) - node T_382 = bit(T_289, 17) - node T_384 = bit(T_289, 16) - node T_386 = bit(T_289, 15) - node T_388 = bit(T_289, 14) - node T_390 = bit(T_289, 13) - node T_392 = bit(T_289, 12) - node T_394 = bit(T_289, 11) - node T_396 = bit(T_289, 10) - node T_398 = bit(T_289, 9) - node T_400 = bit(T_289, 8) - node T_402 = bit(T_289, 7) - node T_404 = bit(T_289, 6) - node T_406 = bit(T_289, 5) - node T_408 = bit(T_289, 4) - node T_410 = bit(T_289, 3) - node T_412 = bit(T_289, 2) - node T_414 = bit(T_289, 1) - node T_415 = shl(T_414, 0) - node T_416 = mux(T_412, UInt<2>("h02"), T_415) - node T_417 = mux(T_410, UInt<2>("h03"), T_416) - node T_418 = mux(T_408, UInt<3>("h04"), T_417) - node T_419 = mux(T_406, UInt<3>("h05"), T_418) - node T_420 = mux(T_404, UInt<3>("h06"), T_419) - node T_421 = mux(T_402, UInt<3>("h07"), T_420) - node T_422 = mux(T_400, UInt<4>("h08"), T_421) - node T_423 = mux(T_398, UInt<4>("h09"), T_422) - node T_424 = mux(T_396, UInt<4>("h0a"), T_423) - node T_425 = mux(T_394, UInt<4>("h0b"), T_424) - node T_426 = mux(T_392, UInt<4>("h0c"), T_425) - node T_427 = mux(T_390, UInt<4>("h0d"), T_426) - node T_428 = mux(T_388, UInt<4>("h0e"), T_427) - node T_429 = mux(T_386, UInt<4>("h0f"), T_428) - node T_430 = mux(T_384, UInt<5>("h010"), T_429) - node T_431 = mux(T_382, UInt<5>("h011"), T_430) - node T_432 = mux(T_380, UInt<5>("h012"), T_431) - node T_433 = mux(T_378, UInt<5>("h013"), T_432) - node T_434 = mux(T_376, UInt<5>("h014"), T_433) - node T_435 = mux(T_374, UInt<5>("h015"), T_434) - node T_436 = mux(T_372, UInt<5>("h016"), T_435) - node T_437 = mux(T_370, UInt<5>("h017"), T_436) - node T_438 = mux(T_368, UInt<5>("h018"), T_437) - node T_439 = mux(T_366, UInt<5>("h019"), T_438) - node T_440 = mux(T_364, UInt<5>("h01a"), T_439) - node T_441 = mux(T_362, UInt<5>("h01b"), T_440) - node T_442 = mux(T_360, UInt<5>("h01c"), T_441) - node T_443 = mux(T_358, UInt<5>("h01d"), T_442) - node T_444 = mux(T_356, UInt<5>("h01e"), T_443) - node T_445 = mux(T_354, UInt<5>("h01f"), T_444) - node T_446 = mux(T_352, UInt<6>("h020"), T_445) - node T_447 = mux(T_350, UInt<6>("h021"), T_446) - node T_448 = mux(T_348, UInt<6>("h022"), T_447) - node T_449 = mux(T_346, UInt<6>("h023"), T_448) - node T_450 = mux(T_344, UInt<6>("h024"), T_449) - node T_451 = mux(T_342, UInt<6>("h025"), T_450) - node T_452 = mux(T_340, UInt<6>("h026"), T_451) - node T_453 = mux(T_338, UInt<6>("h027"), T_452) - node T_454 = mux(T_336, UInt<6>("h028"), T_453) - node T_455 = mux(T_334, UInt<6>("h029"), T_454) - node T_456 = mux(T_332, UInt<6>("h02a"), T_455) - node T_457 = mux(T_330, UInt<6>("h02b"), T_456) - node T_458 = mux(T_328, UInt<6>("h02c"), T_457) - node T_459 = mux(T_326, UInt<6>("h02d"), T_458) - node T_460 = mux(T_324, UInt<6>("h02e"), T_459) - node T_461 = mux(T_322, UInt<6>("h02f"), T_460) - node T_462 = mux(T_320, UInt<6>("h030"), T_461) - node T_463 = mux(T_318, UInt<6>("h031"), T_462) - node T_464 = mux(T_316, UInt<6>("h032"), T_463) - node T_465 = mux(T_314, UInt<6>("h033"), T_464) - node T_466 = mux(T_312, UInt<6>("h034"), T_465) - node T_467 = mux(T_310, UInt<6>("h035"), T_466) - node T_468 = mux(T_308, UInt<6>("h036"), T_467) - node T_469 = mux(T_306, UInt<6>("h037"), T_468) - node T_470 = mux(T_304, UInt<6>("h038"), T_469) - node T_471 = mux(T_302, UInt<6>("h039"), T_470) - node T_472 = mux(T_300, UInt<6>("h03a"), T_471) - node T_473 = mux(T_298, UInt<6>("h03b"), T_472) - node T_474 = mux(T_296, UInt<6>("h03c"), T_473) - node T_475 = mux(T_294, UInt<6>("h03d"), T_474) - node T_476 = mux(T_292, UInt<6>("h03e"), T_475) - node T_477 = mux(T_290, UInt<6>("h03f"), T_476) - node T_478 = not(T_477) - node T_479 = dshl(T_289, T_478) - node T_482 = subw(UInt<6>("h00"), UInt<1>("h01")) - node T_483 = not(T_478) - node T_484 = cat(T_482, T_483) - node T_485 = bits(T_479, 62, 11) - node T_487 = mux(T_284, UInt<1>("h00"), T_484) - node T_488 = mux(T_282, T_487, T_279) - node T_493 = mux(T_288, UInt<2>("h02"), UInt<1>("h01")) - node T_494 = or(UInt<11>("h0400"), T_493) - node T_495 = mux(T_285, UInt<1>("h00"), T_494) - node T_496 = addw(T_488, T_495) - node T_497 = bits(T_496, 11, 10) - node T_498 = not(T_497) - node T_500 = eq(T_498, UInt<1>("h00")) - node T_502 = eq(T_284, UInt<1>("h00")) - node T_503 = and(T_500, T_502) - node T_504 = shl(T_503, 9) - node T_505 = or(T_496, T_504) - node T_506 = mux(T_282, T_485, T_280) - node T_507 = cat(T_505, T_506) - node rec_d = cat(T_278, T_507) - node T_510 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_511 = cat(T_510, rec_s) - node load_wb_data_recoded = mux(load_wb_single, T_511, rec_d) - cmem regfile : UInt<65>[32], clock - when load_wb : - infer accessor T_516 = regfile[load_wb_tag] - T_516 := load_wb_data_recoded - skip - reg ex_ra1 : UInt, clock, reset - reg ex_ra2 : UInt, clock, reset - reg ex_ra3 : UInt, clock, reset - when valid : - when fp_decoder.sigs.ren1 : - node T_524 = eq(fp_decoder.sigs.swap12, UInt<1>("h00")) - when T_524 : - node T_525 = bits(inst_1, 19, 15) - ex_ra1 := T_525 - skip - when fp_decoder.sigs.swap12 : - node T_526 = bits(inst_1, 19, 15) - ex_ra2 := T_526 - skip - skip - when fp_decoder.sigs.ren2 : - when fp_decoder.sigs.swap12 : - node T_527 = bits(inst_1, 24, 20) - ex_ra1 := T_527 - skip - when fp_decoder.sigs.swap23 : - node T_528 = bits(inst_1, 24, 20) - ex_ra3 := T_528 - skip - node T_530 = eq(fp_decoder.sigs.swap12, UInt<1>("h00")) - node T_532 = eq(fp_decoder.sigs.swap23, UInt<1>("h00")) - node T_533 = and(T_530, T_532) - when T_533 : - node T_534 = bits(inst_1, 24, 20) - ex_ra2 := T_534 - skip - skip - when fp_decoder.sigs.ren3 : - node T_535 = bits(inst_1, 31, 27) - ex_ra3 := T_535 - skip - skip - infer accessor ex_rs1 = regfile[ex_ra1] - infer accessor ex_rs2 = regfile[ex_ra2] - infer accessor ex_rs3 = regfile[ex_ra3] - node T_539 = bits(ex_reg_inst, 14, 12) - node T_541 = eq(T_539, UInt<3>("h07")) - node T_542 = bits(ex_reg_inst, 14, 12) - node ex_rm = mux(T_541, fcsr_rm, T_542) - wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} - req.in3 := UInt<1>("h00") - req.in2 := UInt<1>("h00") - req.in1 := UInt<1>("h00") - req.typ := UInt<1>("h00") - req.rm := UInt<1>("h00") - req.wflags := UInt<1>("h00") - req.round := UInt<1>("h00") - req.sqrt := UInt<1>("h00") - req.div := UInt<1>("h00") - req.fma := UInt<1>("h00") - req.fastpipe := UInt<1>("h00") - req.toint := UInt<1>("h00") - req.fromint := UInt<1>("h00") - req.single := UInt<1>("h00") - req.swap23 := UInt<1>("h00") - req.swap12 := UInt<1>("h00") - req.ren3 := UInt<1>("h00") - req.ren2 := UInt<1>("h00") - req.ren1 := UInt<1>("h00") - req.wen := UInt<1>("h00") - req.ldst := UInt<1>("h00") - req.cmd := UInt<1>("h00") - req <> ex_ctrl - req.rm := ex_rm - req.in1 := ex_rs1 - req.in2 := ex_rs2 - req.in3 := ex_rs3 - node T_612 = bits(ex_reg_inst, 21, 20) - req.typ := T_612 - inst sfma of FPUFMAPipe - sfma.in.bits.in3 := UInt<1>("h00") - sfma.in.bits.in2 := UInt<1>("h00") - sfma.in.bits.in1 := UInt<1>("h00") - sfma.in.bits.typ := UInt<1>("h00") - sfma.in.bits.rm := UInt<1>("h00") - sfma.in.bits.wflags := UInt<1>("h00") - sfma.in.bits.round := UInt<1>("h00") - sfma.in.bits.sqrt := UInt<1>("h00") - sfma.in.bits.div := UInt<1>("h00") - sfma.in.bits.fma := UInt<1>("h00") - sfma.in.bits.fastpipe := UInt<1>("h00") - sfma.in.bits.toint := UInt<1>("h00") - sfma.in.bits.fromint := UInt<1>("h00") - sfma.in.bits.single := UInt<1>("h00") - sfma.in.bits.swap23 := UInt<1>("h00") - sfma.in.bits.swap12 := UInt<1>("h00") - sfma.in.bits.ren3 := UInt<1>("h00") - sfma.in.bits.ren2 := UInt<1>("h00") - sfma.in.bits.ren1 := UInt<1>("h00") - sfma.in.bits.wen := UInt<1>("h00") - sfma.in.bits.ldst := UInt<1>("h00") - sfma.in.bits.cmd := UInt<1>("h00") - sfma.in.valid := UInt<1>("h00") - sfma.reset := UInt<1>("h00") - sfma.clock := clock - sfma.reset := reset - node T_637 = and(ex_reg_valid, ex_ctrl.fma) - node T_638 = and(T_637, ex_ctrl.single) - sfma.in.valid := T_638 - sfma.in.bits <> req - inst dfma of FPUFMAPipe_70 - dfma.in.bits.in3 := UInt<1>("h00") - dfma.in.bits.in2 := UInt<1>("h00") - dfma.in.bits.in1 := UInt<1>("h00") - dfma.in.bits.typ := UInt<1>("h00") - dfma.in.bits.rm := UInt<1>("h00") - dfma.in.bits.wflags := UInt<1>("h00") - dfma.in.bits.round := UInt<1>("h00") - dfma.in.bits.sqrt := UInt<1>("h00") - dfma.in.bits.div := UInt<1>("h00") - dfma.in.bits.fma := UInt<1>("h00") - dfma.in.bits.fastpipe := UInt<1>("h00") - dfma.in.bits.toint := UInt<1>("h00") - dfma.in.bits.fromint := UInt<1>("h00") - dfma.in.bits.single := UInt<1>("h00") - dfma.in.bits.swap23 := UInt<1>("h00") - dfma.in.bits.swap12 := UInt<1>("h00") - dfma.in.bits.ren3 := UInt<1>("h00") - dfma.in.bits.ren2 := UInt<1>("h00") - dfma.in.bits.ren1 := UInt<1>("h00") - dfma.in.bits.wen := UInt<1>("h00") - dfma.in.bits.ldst := UInt<1>("h00") - dfma.in.bits.cmd := UInt<1>("h00") - dfma.in.valid := UInt<1>("h00") - dfma.reset := UInt<1>("h00") - dfma.clock := clock - dfma.reset := reset - node T_663 = and(ex_reg_valid, ex_ctrl.fma) - node T_665 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_666 = and(T_663, T_665) - dfma.in.valid := T_666 - dfma.in.bits <> req - inst fpiu of FPToInt - fpiu.in.bits.in3 := UInt<1>("h00") - fpiu.in.bits.in2 := UInt<1>("h00") - fpiu.in.bits.in1 := UInt<1>("h00") - fpiu.in.bits.typ := UInt<1>("h00") - fpiu.in.bits.rm := UInt<1>("h00") - fpiu.in.bits.wflags := UInt<1>("h00") - fpiu.in.bits.round := UInt<1>("h00") - fpiu.in.bits.sqrt := UInt<1>("h00") - fpiu.in.bits.div := UInt<1>("h00") - fpiu.in.bits.fma := UInt<1>("h00") - fpiu.in.bits.fastpipe := UInt<1>("h00") - fpiu.in.bits.toint := UInt<1>("h00") - fpiu.in.bits.fromint := UInt<1>("h00") - fpiu.in.bits.single := UInt<1>("h00") - fpiu.in.bits.swap23 := UInt<1>("h00") - fpiu.in.bits.swap12 := UInt<1>("h00") - fpiu.in.bits.ren3 := UInt<1>("h00") - fpiu.in.bits.ren2 := UInt<1>("h00") - fpiu.in.bits.ren1 := UInt<1>("h00") - fpiu.in.bits.wen := UInt<1>("h00") - fpiu.in.bits.ldst := UInt<1>("h00") - fpiu.in.bits.cmd := UInt<1>("h00") - fpiu.in.valid := UInt<1>("h00") - fpiu.reset := UInt<1>("h00") - fpiu.clock := clock - fpiu.reset := reset - node T_691 = or(ex_ctrl.toint, ex_ctrl.div) - node T_692 = or(T_691, ex_ctrl.sqrt) - node T_695 = and(ex_ctrl.cmd, UInt<4>("h0d")) - node T_696 = eq(UInt<3>("h05"), T_695) - node T_697 = or(T_692, T_696) - node T_698 = and(ex_reg_valid, T_697) - fpiu.in.valid := T_698 - fpiu.in.bits <> req - store_data := fpiu.out.bits.store - toint_data := fpiu.out.bits.toint - inst ifpu of IntToFP - ifpu.in.bits.in3 := UInt<1>("h00") - ifpu.in.bits.in2 := UInt<1>("h00") - ifpu.in.bits.in1 := UInt<1>("h00") - ifpu.in.bits.typ := UInt<1>("h00") - ifpu.in.bits.rm := UInt<1>("h00") - ifpu.in.bits.wflags := UInt<1>("h00") - ifpu.in.bits.round := UInt<1>("h00") - ifpu.in.bits.sqrt := UInt<1>("h00") - ifpu.in.bits.div := UInt<1>("h00") - ifpu.in.bits.fma := UInt<1>("h00") - ifpu.in.bits.fastpipe := UInt<1>("h00") - ifpu.in.bits.toint := UInt<1>("h00") - ifpu.in.bits.fromint := UInt<1>("h00") - ifpu.in.bits.single := UInt<1>("h00") - ifpu.in.bits.swap23 := UInt<1>("h00") - ifpu.in.bits.swap12 := UInt<1>("h00") - ifpu.in.bits.ren3 := UInt<1>("h00") - ifpu.in.bits.ren2 := UInt<1>("h00") - ifpu.in.bits.ren1 := UInt<1>("h00") - ifpu.in.bits.wen := UInt<1>("h00") - ifpu.in.bits.ldst := UInt<1>("h00") - ifpu.in.bits.cmd := UInt<1>("h00") - ifpu.in.valid := UInt<1>("h00") - ifpu.reset := UInt<1>("h00") - ifpu.clock := clock - ifpu.reset := reset - node T_723 = and(ex_reg_valid, ex_ctrl.fromint) - ifpu.in.valid := T_723 - ifpu.in.bits <> req - ifpu.in.bits.in1 := fromint_data - inst fpmu of FPToFP - fpmu.lt := UInt<1>("h00") - fpmu.in.bits.in3 := UInt<1>("h00") - fpmu.in.bits.in2 := UInt<1>("h00") - fpmu.in.bits.in1 := UInt<1>("h00") - fpmu.in.bits.typ := UInt<1>("h00") - fpmu.in.bits.rm := UInt<1>("h00") - fpmu.in.bits.wflags := UInt<1>("h00") - fpmu.in.bits.round := UInt<1>("h00") - fpmu.in.bits.sqrt := UInt<1>("h00") - fpmu.in.bits.div := UInt<1>("h00") - fpmu.in.bits.fma := UInt<1>("h00") - fpmu.in.bits.fastpipe := UInt<1>("h00") - fpmu.in.bits.toint := UInt<1>("h00") - fpmu.in.bits.fromint := UInt<1>("h00") - fpmu.in.bits.single := UInt<1>("h00") - fpmu.in.bits.swap23 := UInt<1>("h00") - fpmu.in.bits.swap12 := UInt<1>("h00") - fpmu.in.bits.ren3 := UInt<1>("h00") - fpmu.in.bits.ren2 := UInt<1>("h00") - fpmu.in.bits.ren1 := UInt<1>("h00") - fpmu.in.bits.wen := UInt<1>("h00") - fpmu.in.bits.ldst := UInt<1>("h00") - fpmu.in.bits.cmd := UInt<1>("h00") - fpmu.in.valid := UInt<1>("h00") - fpmu.reset := UInt<1>("h00") - fpmu.clock := clock - fpmu.reset := reset - node T_749 = and(ex_reg_valid, ex_ctrl.fastpipe) - fpmu.in.valid := T_749 - fpmu.in.bits <> req - fpmu.lt := fpiu.out.bits.lt - reg divSqrt_wen : UInt<1>, clock, reset - divSqrt_wen := UInt<1>("h00") - wire divSqrt_inReady : UInt<1> - divSqrt_inReady := UInt<1>("h00") - reg divSqrt_waddr : UInt, clock, reset - wire divSqrt_wdata : UInt - divSqrt_wdata := UInt<1>("h00") - wire divSqrt_flags : UInt - divSqrt_flags := UInt<1>("h00") - reg divSqrt_in_flight : UInt<1>, clock, reset - onreset divSqrt_in_flight := UInt<1>("h00") - node T_765 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_766 = cat(T_765, sfma.out.bits.data) - node T_769 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) - node T_772 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) - node T_773 = and(mem_ctrl.fma, mem_ctrl.single) - node T_776 = mux(T_773, UInt<1>("h01"), UInt<1>("h00")) - node T_778 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_779 = and(mem_ctrl.fma, T_778) - node T_782 = mux(T_779, UInt<2>("h02"), UInt<1>("h00")) - node T_783 = or(T_769, T_772) - node T_784 = or(T_783, T_776) - node memLatencyMask = or(T_784, T_782) - reg wen : UInt<2>, clock, reset - onreset wen := UInt<2>("h00") - reg winfo : UInt[2], clock, reset - node T_800 = or(mem_ctrl.fma, mem_ctrl.fastpipe) - node T_801 = or(T_800, mem_ctrl.fromint) - node mem_wen = and(mem_reg_valid, T_801) - node T_805 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) - node T_808 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) - node T_809 = and(ex_ctrl.fma, ex_ctrl.single) - node T_812 = mux(T_809, UInt<2>("h02"), UInt<1>("h00")) - node T_814 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_815 = and(ex_ctrl.fma, T_814) - node T_818 = mux(T_815, UInt<3>("h04"), UInt<1>("h00")) - node T_819 = or(T_805, T_808) - node T_820 = or(T_819, T_812) - node T_821 = or(T_820, T_818) - node T_822 = and(memLatencyMask, T_821) - node T_824 = neq(T_822, UInt<1>("h00")) - node T_825 = and(mem_wen, T_824) - node T_828 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) - node T_831 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) - node T_832 = and(ex_ctrl.fma, ex_ctrl.single) - node T_835 = mux(T_832, UInt<3>("h04"), UInt<1>("h00")) - node T_837 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_838 = and(ex_ctrl.fma, T_837) - node T_841 = mux(T_838, UInt<4>("h08"), UInt<1>("h00")) - node T_842 = or(T_828, T_831) - node T_843 = or(T_842, T_835) - node T_844 = or(T_843, T_841) - node T_845 = and(wen, T_844) - node T_847 = neq(T_845, UInt<1>("h00")) - node T_848 = or(T_825, T_847) - reg write_port_busy : UInt<1>, clock, reset - when ex_reg_valid : - write_port_busy := T_848 - skip - node T_852 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) - node T_855 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) - node T_856 = and(mem_ctrl.fma, mem_ctrl.single) - node T_859 = mux(T_856, UInt<2>("h02"), UInt<1>("h00")) - node T_861 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_862 = and(mem_ctrl.fma, T_861) - node T_865 = mux(T_862, UInt<2>("h03"), UInt<1>("h00")) - node T_866 = or(T_852, T_855) - node T_867 = or(T_866, T_859) - node T_868 = or(T_867, T_865) - node T_869 = bits(mem_reg_inst, 11, 7) - node mem_winfo = cat(T_868, T_869) - node T_871 = bit(wen, 1) - when T_871 : - winfo[0] := winfo[1] - skip - node T_872 = shr(wen, 1) - wen := T_872 - when mem_wen : - node T_874 = eq(killm_2, UInt<1>("h00")) - when T_874 : - node T_875 = shr(wen, 1) - node T_876 = or(T_875, memLatencyMask) - wen := T_876 - skip - node T_878 = eq(write_port_busy, UInt<1>("h00")) - node T_879 = bit(memLatencyMask, 0) - node T_880 = and(T_878, T_879) - when T_880 : - winfo[0] := mem_winfo - skip - node T_882 = eq(write_port_busy, UInt<1>("h00")) - node T_883 = bit(memLatencyMask, 1) - node T_884 = and(T_882, T_883) - when T_884 : - winfo[1] := mem_winfo - skip - skip - node T_885 = bits(winfo[0], 4, 0) - node waddr = mux(divSqrt_wen, divSqrt_waddr, T_885) - node wsrc = shr(winfo[0], 5) - wire T_889 : UInt<97>[4] - T_889[0] := fpmu.out.bits.data - T_889[1] := ifpu.out.bits.data - T_889[2] := T_766 - T_889[3] := dfma.out.bits.data - infer accessor T_895 = T_889[wsrc] - node wdata = mux(divSqrt_wen, divSqrt_wdata, T_895) - wire T_898 : UInt<5>[4] - T_898[0] := fpmu.out.bits.exc - T_898[1] := ifpu.out.bits.exc - T_898[2] := sfma.out.bits.exc - T_898[3] := dfma.out.bits.exc - infer accessor wexc = T_898[wsrc] - node T_905 = bit(wen, 0) - node T_906 = or(T_905, divSqrt_wen) - when T_906 : - infer accessor T_907 = regfile[waddr] - T_907 := wdata - skip - node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) - reg wb_toint_exc : UInt<5>, clock, reset - when mem_ctrl.toint : - wb_toint_exc := fpiu.out.bits.exc - skip - node T_910 = or(wb_toint_valid, divSqrt_wen) - node T_911 = bit(wen, 0) - node T_912 = or(T_910, T_911) - fcsr_flags.valid := T_912 - node T_914 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) - node T_916 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) - node T_917 = or(T_914, T_916) - node T_918 = bit(wen, 0) - node T_920 = mux(T_918, wexc, UInt<1>("h00")) - node T_921 = or(T_917, T_920) - fcsr_flags.bits := T_921 - node T_922 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_923 = and(mem_reg_valid, T_922) - node T_925 = eq(divSqrt_inReady, UInt<1>("h00")) - node T_927 = neq(wen, UInt<1>("h00")) - node T_928 = or(T_925, T_927) - node units_busy = and(T_923, T_928) - node T_930 = and(ex_reg_valid, ex_ctrl.wflags) - node T_931 = and(mem_reg_valid, mem_ctrl.wflags) - node T_932 = or(T_930, T_931) - node T_933 = and(wb_reg_valid, wb_ctrl.toint) - node T_934 = or(T_932, T_933) - node T_936 = neq(wen, UInt<1>("h00")) - node T_937 = or(T_934, T_936) - node T_938 = or(T_937, divSqrt_in_flight) - node T_940 = eq(T_938, UInt<1>("h00")) - fcsr_rdy := T_940 - node T_941 = or(units_busy, write_port_busy) - node T_942 = or(T_941, divSqrt_in_flight) - nack_mem := T_942 - dec <> fp_decoder.sigs - node T_944 = or(UInt<1>("h00"), mem_ctrl.div) - node T_945 = or(T_944, mem_ctrl.sqrt) - reg T_946 : UInt<1>, clock, reset - T_946 := T_945 - node T_947 = and(wb_reg_valid, T_946) - sboard_set := T_947 - node T_948 = bit(wen, 0) - node T_950 = and(T_948, UInt<1>("h00")) - node T_951 = or(divSqrt_wen, T_950) - sboard_clr := T_951 - sboard_clra := waddr - node T_952 = bit(ex_rm, 2) - node T_953 = and(T_952, ex_ctrl.round) - illegal_rm := T_953 - divSqrt_wdata := UInt<1>("h00") - divSqrt_flags := UInt<1>("h00") - reg T_957 : UInt<1>, clock, reset - reg T_959 : UInt, clock, reset - reg T_961 : UInt, clock, reset - reg T_963 : UInt, clock, reset - inst T_1151 of divSqrtRecodedFloat64 - T_1151.roundingMode := UInt<1>("h00") - T_1151.b := UInt<1>("h00") - T_1151.a := UInt<1>("h00") - T_1151.sqrtOp := UInt<1>("h00") - T_1151.inValid := UInt<1>("h00") - T_1151.reset := UInt<1>("h00") - T_1151.clock := clock - T_1151.reset := reset - node T_970 = mux(T_1151.sqrtOp, T_1151.inReady_sqrt, T_1151.inReady_div) - divSqrt_inReady := T_970 - node T_971 = or(T_1151.outValid_div, T_1151.outValid_sqrt) - node T_973 = neq(wen, UInt<1>("h00")) - node T_975 = eq(T_973, UInt<1>("h00")) - node T_976 = and(mem_reg_valid, T_975) - node T_978 = eq(divSqrt_in_flight, UInt<1>("h00")) - node T_979 = and(T_976, T_978) - node T_981 = eq(killm, UInt<1>("h00")) - node T_982 = and(T_979, T_981) - node T_983 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_984 = and(T_982, T_983) - T_1151.inValid := T_984 - T_1151.sqrtOp := mem_ctrl.sqrt - T_1151.a := fpiu.as_double.in1 - T_1151.b := fpiu.as_double.in2 - T_1151.roundingMode := fpiu.as_double.rm - node T_985 = and(T_1151.inValid, divSqrt_inReady) - when T_985 : - divSqrt_in_flight := UInt<1>("h01") - T_957 := mem_ctrl.single - node T_987 = bits(mem_reg_inst, 11, 7) - divSqrt_waddr := T_987 - T_959 := T_1151.roundingMode - skip - when T_971 : - divSqrt_wen := UInt<1>("h01") - T_963 := T_1151.out - divSqrt_in_flight := UInt<1>("h00") - T_961 := T_1151.exceptionFlags - skip - node T_990 = bit(T_963, 64) - node T_991 = bits(T_963, 51, 0) - node T_992 = bits(T_963, 63, 52) - node T_993 = bits(T_963, 63, 61) - node T_994 = bits(T_963, 62, 52) - node T_995 = not(T_993) - node T_997 = eq(T_995, UInt<1>("h00")) - node T_998 = bit(T_991, 51) - node T_1000 = eq(T_998, UInt<1>("h00")) - node T_1001 = and(T_997, T_1000) - node T_1006 = neq(T_993, UInt<1>("h00")) - node T_1008 = eq(T_1006, UInt<1>("h00")) - node T_1009 = bits(T_993, 2, 1) - node T_1010 = not(T_1009) - node T_1012 = eq(T_1010, UInt<1>("h00")) - node T_1013 = or(T_1008, T_1012) - node T_1014 = geq(T_992, UInt<11>("h076a")) - node T_1015 = leq(T_992, UInt<11>("h0781")) - node T_1016 = and(T_1014, T_1015) - node T_1017 = lt(T_992, UInt<11>("h076a")) - node T_1019 = eq(T_1013, UInt<1>("h00")) - node T_1020 = and(T_1017, T_1019) - node T_1021 = gt(T_992, UInt<12>("h087f")) - node T_1023 = eq(T_1013, UInt<1>("h00")) - node T_1024 = and(T_1021, T_1023) - node T_1026 = addw(UInt<11>("h0781"), UInt<1>("h01")) - node T_1027 = subw(T_1026, T_992) - node T_1029 = mux(T_1016, T_1027, UInt<1>("h00")) - node T_1030 = bits(T_1029, 4, 0) - node T_1032 = bits(T_991, 51, 28) - node T_1034 = cat(T_1032, UInt<24>("h00")) - node T_1035 = cat(UInt<1>("h01"), T_1034) - node T_1036 = dshr(T_1035, T_1030) - node T_1037 = bits(T_1036, 23, 0) - node T_1039 = neq(T_1037, UInt<1>("h00")) - node T_1040 = bits(T_991, 27, 0) - node T_1042 = neq(T_1040, UInt<1>("h00")) - node T_1043 = or(T_1039, T_1042) - node T_1044 = bits(T_1036, 25, 24) - node T_1045 = cat(T_1044, T_1043) - node T_1046 = bits(T_1045, 1, 0) - node T_1048 = neq(T_1046, UInt<1>("h00")) - node T_1050 = eq(T_1013, UInt<1>("h00")) - node T_1051 = and(T_1048, T_1050) - node T_1052 = eq(ex_rm, UInt<2>("h00")) - node T_1053 = bits(T_1045, 1, 0) - node T_1054 = not(T_1053) - node T_1056 = eq(T_1054, UInt<1>("h00")) - node T_1057 = bits(T_1045, 2, 1) - node T_1058 = not(T_1057) - node T_1060 = eq(T_1058, UInt<1>("h00")) - node T_1061 = or(T_1056, T_1060) - node T_1062 = eq(ex_rm, UInt<2>("h02")) - node T_1063 = and(T_990, T_1051) - node T_1064 = eq(ex_rm, UInt<2>("h03")) - node T_1066 = eq(T_990, UInt<1>("h00")) - node T_1067 = and(T_1066, T_1051) - node T_1069 = mux(T_1064, T_1067, UInt<1>("h00")) - node T_1070 = mux(T_1062, T_1063, T_1069) - node T_1071 = mux(T_1052, T_1061, T_1070) - node T_1073 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_1074 = cat(T_1073, T_1073) - node T_1075 = cat(T_1074, T_1074) - node T_1076 = cat(T_1075, T_1075) - node T_1077 = cat(T_1075, T_1076) - node T_1078 = cat(UInt<1>("h01"), T_1077) - node T_1079 = dshl(T_1078, T_1030) - node T_1080 = bits(T_1079, 24, 0) - node T_1082 = bits(T_991, 51, 29) - node T_1083 = cat(UInt<2>("h01"), T_1082) - node T_1084 = not(T_1080) - node T_1085 = or(T_1083, T_1084) - node T_1087 = addw(T_1085, UInt<1>("h01")) - node T_1088 = mux(T_1071, T_1087, T_1085) - node T_1089 = bits(T_992, 8, 0) - node T_1091 = addw(T_1089, UInt<9>("h0100")) - node T_1092 = bit(T_1088, 24) - node T_1094 = addw(T_1091, UInt<1>("h01")) - node T_1095 = mux(T_1092, T_1094, T_1091) - node T_1096 = eq(ex_rm, UInt<2>("h02")) - node T_1097 = and(T_1096, T_990) - node T_1098 = eq(ex_rm, UInt<2>("h03")) - node T_1100 = eq(T_990, UInt<1>("h00")) - node T_1101 = and(T_1098, T_1100) - node T_1102 = or(T_1097, T_1101) - node T_1103 = eq(ex_rm, UInt<2>("h00")) - node T_1104 = or(T_1102, T_1103) - node T_1106 = eq(T_1104, UInt<1>("h00")) - node T_1108 = subw(UInt<23>("h00"), T_1106) - node T_1111 = mux(T_1104, UInt<9>("h0180"), UInt<9>("h017f")) - node T_1115 = mux(T_1102, UInt<7>("h06b"), UInt<1>("h00")) - node T_1116 = shl(T_993, 6) - node T_1117 = mux(T_1020, T_1115, T_1095) - node T_1118 = mux(T_1024, T_1111, T_1117) - node T_1119 = mux(T_1013, T_1116, T_1118) - node T_1121 = subw(UInt<23>("h00"), T_997) - node T_1122 = bits(T_1088, 22, 0) - node T_1123 = mux(T_1020, UInt<1>("h00"), T_1122) - node T_1124 = mux(T_1024, T_1108, T_1123) - node T_1125 = mux(T_1013, T_1121, T_1124) - node T_1126 = cat(T_1119, T_1125) - node T_1127 = cat(T_990, T_1126) - node T_1128 = and(T_1016, T_1051) - node T_1129 = or(T_1020, T_1128) - node T_1130 = eq(T_992, UInt<12>("h087f")) - node T_1131 = bit(T_1088, 24) - node T_1132 = and(T_1130, T_1131) - node T_1133 = or(T_1024, T_1132) - node T_1135 = or(T_1051, T_1024) - node T_1136 = or(T_1135, T_1020) - node T_1137 = cat(T_1001, UInt<1>("h00")) - node T_1138 = cat(T_1129, T_1136) - node T_1139 = cat(T_1133, T_1138) - node T_1140 = cat(T_1137, T_1139) - node T_1141 = mux(T_957, T_1127, T_963) - divSqrt_wdata := T_1141 - node T_1143 = mux(T_957, T_1140, UInt<1>("h00")) - node T_1144 = or(T_961, T_1143) - divSqrt_flags := T_1144 - - module RocketTile : - output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} - output uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - output cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - input clock : Clock - input reset : UInt<1> - - host.debug_stats_pcr := UInt<1>("h00") - host.ipi_rep.ready := UInt<1>("h00") - host.ipi_req.bits := UInt<1>("h00") - host.ipi_req.valid := UInt<1>("h00") - host.pcr_rep.bits := UInt<1>("h00") - host.pcr_rep.valid := UInt<1>("h00") - host.pcr_req.ready := UInt<1>("h00") - uncached.grant.ready := UInt<1>("h00") - uncached.acquire.bits.union := UInt<1>("h00") - uncached.acquire.bits.a_type := UInt<1>("h00") - uncached.acquire.bits.is_builtin_type := UInt<1>("h00") - uncached.acquire.bits.data := UInt<1>("h00") - uncached.acquire.bits.addr_beat := UInt<1>("h00") - uncached.acquire.bits.client_xact_id := UInt<1>("h00") - uncached.acquire.bits.addr_block := UInt<1>("h00") - uncached.acquire.valid := UInt<1>("h00") - cached.release.bits.voluntary := UInt<1>("h00") - cached.release.bits.r_type := UInt<1>("h00") - cached.release.bits.data := UInt<1>("h00") - cached.release.bits.addr_beat := UInt<1>("h00") - cached.release.bits.client_xact_id := UInt<1>("h00") - cached.release.bits.addr_block := UInt<1>("h00") - cached.release.valid := UInt<1>("h00") - cached.probe.ready := UInt<1>("h00") - cached.grant.ready := UInt<1>("h00") - cached.acquire.bits.union := UInt<1>("h00") - cached.acquire.bits.a_type := UInt<1>("h00") - cached.acquire.bits.is_builtin_type := UInt<1>("h00") - cached.acquire.bits.data := UInt<1>("h00") - cached.acquire.bits.addr_beat := UInt<1>("h00") - cached.acquire.bits.client_xact_id := UInt<1>("h00") - cached.acquire.bits.addr_block := UInt<1>("h00") - cached.acquire.valid := UInt<1>("h00") - inst icache of Frontend - icache.mem_1.grant.bits.g_type := UInt<1>("h00") - icache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") - icache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") - icache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") - icache.mem_1.grant.bits.data := UInt<1>("h00") - icache.mem_1.grant.bits.addr_beat := UInt<1>("h00") - icache.mem_1.grant.valid := UInt<1>("h00") - icache.mem_1.acquire.ready := UInt<1>("h00") - icache.ptw.invalidate := UInt<1>("h00") - icache.ptw.status.ie := UInt<1>("h00") - icache.ptw.status.prv := UInt<1>("h00") - icache.ptw.status.ie1 := UInt<1>("h00") - icache.ptw.status.prv1 := UInt<1>("h00") - icache.ptw.status.ie2 := UInt<1>("h00") - icache.ptw.status.prv2 := UInt<1>("h00") - icache.ptw.status.ie3 := UInt<1>("h00") - icache.ptw.status.prv3 := UInt<1>("h00") - icache.ptw.status.fs := UInt<1>("h00") - icache.ptw.status.xs := UInt<1>("h00") - icache.ptw.status.mprv := UInt<1>("h00") - icache.ptw.status.vm := UInt<1>("h00") - icache.ptw.status.zero1 := UInt<1>("h00") - icache.ptw.status.sd_rv32 := UInt<1>("h00") - icache.ptw.status.zero2 := UInt<1>("h00") - icache.ptw.status.sd := UInt<1>("h00") - icache.ptw.resp.bits.pte.v := UInt<1>("h00") - icache.ptw.resp.bits.pte.typ := UInt<1>("h00") - icache.ptw.resp.bits.pte.r := UInt<1>("h00") - icache.ptw.resp.bits.pte.d := UInt<1>("h00") - icache.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - icache.ptw.resp.bits.pte.ppn := UInt<1>("h00") - icache.ptw.resp.bits.error := UInt<1>("h00") - icache.ptw.resp.valid := UInt<1>("h00") - icache.ptw.req.ready := UInt<1>("h00") - icache.cpu.invalidate := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.entry := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.target := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.mask := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.bits.taken := UInt<1>("h00") - icache.cpu.ras_update.bits.prediction.valid := UInt<1>("h00") - icache.cpu.ras_update.bits.returnAddr := UInt<1>("h00") - icache.cpu.ras_update.bits.isReturn := UInt<1>("h00") - icache.cpu.ras_update.bits.isCall := UInt<1>("h00") - icache.cpu.ras_update.valid := UInt<1>("h00") - icache.cpu.bht_update.bits.mispredict := UInt<1>("h00") - icache.cpu.bht_update.bits.taken := UInt<1>("h00") - icache.cpu.bht_update.bits.pc := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.entry := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.target := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.mask := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.bits.taken := UInt<1>("h00") - icache.cpu.bht_update.bits.prediction.valid := UInt<1>("h00") - icache.cpu.bht_update.valid := UInt<1>("h00") - icache.cpu.btb_update.bits.br_pc := UInt<1>("h00") - icache.cpu.btb_update.bits.isReturn := UInt<1>("h00") - icache.cpu.btb_update.bits.isJump := UInt<1>("h00") - icache.cpu.btb_update.bits.taken := UInt<1>("h00") - icache.cpu.btb_update.bits.target := UInt<1>("h00") - icache.cpu.btb_update.bits.pc := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.entry := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.target := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.mask := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.bits.taken := UInt<1>("h00") - icache.cpu.btb_update.bits.prediction.valid := UInt<1>("h00") - icache.cpu.btb_update.valid := UInt<1>("h00") - icache.cpu.resp.ready := UInt<1>("h00") - icache.cpu.req.bits.pc := UInt<1>("h00") - icache.cpu.req.valid := UInt<1>("h00") - icache.reset := UInt<1>("h00") - icache.clock := clock - icache.reset := reset - inst dcache of HellaCache - dcache.mem_1.release.ready := UInt<1>("h00") - dcache.mem_1.probe.bits.p_type := UInt<1>("h00") - dcache.mem_1.probe.bits.addr_block := UInt<1>("h00") - dcache.mem_1.probe.valid := UInt<1>("h00") - dcache.mem_1.grant.bits.g_type := UInt<1>("h00") - dcache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") - dcache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") - dcache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") - dcache.mem_1.grant.bits.data := UInt<1>("h00") - dcache.mem_1.grant.bits.addr_beat := UInt<1>("h00") - dcache.mem_1.grant.valid := UInt<1>("h00") - dcache.mem_1.acquire.ready := UInt<1>("h00") - dcache.ptw.invalidate := UInt<1>("h00") - dcache.ptw.status.ie := UInt<1>("h00") - dcache.ptw.status.prv := UInt<1>("h00") - dcache.ptw.status.ie1 := UInt<1>("h00") - dcache.ptw.status.prv1 := UInt<1>("h00") - dcache.ptw.status.ie2 := UInt<1>("h00") - dcache.ptw.status.prv2 := UInt<1>("h00") - dcache.ptw.status.ie3 := UInt<1>("h00") - dcache.ptw.status.prv3 := UInt<1>("h00") - dcache.ptw.status.fs := UInt<1>("h00") - dcache.ptw.status.xs := UInt<1>("h00") - dcache.ptw.status.mprv := UInt<1>("h00") - dcache.ptw.status.vm := UInt<1>("h00") - dcache.ptw.status.zero1 := UInt<1>("h00") - dcache.ptw.status.sd_rv32 := UInt<1>("h00") - dcache.ptw.status.zero2 := UInt<1>("h00") - dcache.ptw.status.sd := UInt<1>("h00") - dcache.ptw.resp.bits.pte.v := UInt<1>("h00") - dcache.ptw.resp.bits.pte.typ := UInt<1>("h00") - dcache.ptw.resp.bits.pte.r := UInt<1>("h00") - dcache.ptw.resp.bits.pte.d := UInt<1>("h00") - dcache.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") - dcache.ptw.resp.bits.pte.ppn := UInt<1>("h00") - dcache.ptw.resp.bits.error := UInt<1>("h00") - dcache.ptw.resp.valid := UInt<1>("h00") - dcache.ptw.req.ready := UInt<1>("h00") - dcache.cpu.invalidate_lr := UInt<1>("h00") - dcache.cpu.req.bits.data := UInt<1>("h00") - dcache.cpu.req.bits.phys := UInt<1>("h00") - dcache.cpu.req.bits.kill := UInt<1>("h00") - dcache.cpu.req.bits.typ := UInt<1>("h00") - dcache.cpu.req.bits.cmd := UInt<1>("h00") - dcache.cpu.req.bits.tag := UInt<1>("h00") - dcache.cpu.req.bits.addr := UInt<1>("h00") - dcache.cpu.req.valid := UInt<1>("h00") - dcache.reset := UInt<1>("h00") - dcache.clock := clock - dcache.reset := reset - inst ptw of PTW - ptw.dpath.status.ie := UInt<1>("h00") - ptw.dpath.status.prv := UInt<1>("h00") - ptw.dpath.status.ie1 := UInt<1>("h00") - ptw.dpath.status.prv1 := UInt<1>("h00") - ptw.dpath.status.ie2 := UInt<1>("h00") - ptw.dpath.status.prv2 := UInt<1>("h00") - ptw.dpath.status.ie3 := UInt<1>("h00") - ptw.dpath.status.prv3 := UInt<1>("h00") - ptw.dpath.status.fs := UInt<1>("h00") - ptw.dpath.status.xs := UInt<1>("h00") - ptw.dpath.status.mprv := UInt<1>("h00") - ptw.dpath.status.vm := UInt<1>("h00") - ptw.dpath.status.zero1 := UInt<1>("h00") - ptw.dpath.status.sd_rv32 := UInt<1>("h00") - ptw.dpath.status.zero2 := UInt<1>("h00") - ptw.dpath.status.sd := UInt<1>("h00") - ptw.dpath.invalidate := UInt<1>("h00") - ptw.dpath.ptbr := UInt<1>("h00") - ptw.mem_1.ordered := UInt<1>("h00") - ptw.mem_1.xcpt.pf.st := UInt<1>("h00") - ptw.mem_1.xcpt.pf.ld := UInt<1>("h00") - ptw.mem_1.xcpt.ma.st := UInt<1>("h00") - ptw.mem_1.xcpt.ma.ld := UInt<1>("h00") - ptw.mem_1.replay_next.bits := UInt<1>("h00") - ptw.mem_1.replay_next.valid := UInt<1>("h00") - ptw.mem_1.resp.bits.store_data := UInt<1>("h00") - ptw.mem_1.resp.bits.data_subword := UInt<1>("h00") - ptw.mem_1.resp.bits.has_data := UInt<1>("h00") - ptw.mem_1.resp.bits.replay := UInt<1>("h00") - ptw.mem_1.resp.bits.nack := UInt<1>("h00") - ptw.mem_1.resp.bits.data := UInt<1>("h00") - ptw.mem_1.resp.bits.typ := UInt<1>("h00") - ptw.mem_1.resp.bits.cmd := UInt<1>("h00") - ptw.mem_1.resp.bits.tag := UInt<1>("h00") - ptw.mem_1.resp.bits.addr := UInt<1>("h00") - ptw.mem_1.resp.valid := UInt<1>("h00") - ptw.mem_1.req.ready := UInt<1>("h00") - ptw.requestor[0].req.bits.fetch := UInt<1>("h00") - ptw.requestor[0].req.bits.store := UInt<1>("h00") - ptw.requestor[0].req.bits.prv := UInt<1>("h00") - ptw.requestor[0].req.bits.addr := UInt<1>("h00") - ptw.requestor[0].req.valid := UInt<1>("h00") - ptw.requestor[1].req.bits.fetch := UInt<1>("h00") - ptw.requestor[1].req.bits.store := UInt<1>("h00") - ptw.requestor[1].req.bits.prv := UInt<1>("h00") - ptw.requestor[1].req.bits.addr := UInt<1>("h00") - ptw.requestor[1].req.valid := UInt<1>("h00") - ptw.reset := UInt<1>("h00") - ptw.clock := clock - ptw.reset := reset - inst core of Rocket - core.rocc.pptw.req.bits.fetch := UInt<1>("h00") - core.rocc.pptw.req.bits.store := UInt<1>("h00") - core.rocc.pptw.req.bits.prv := UInt<1>("h00") - core.rocc.pptw.req.bits.addr := UInt<1>("h00") - core.rocc.pptw.req.valid := UInt<1>("h00") - core.rocc.dptw.req.bits.fetch := UInt<1>("h00") - core.rocc.dptw.req.bits.store := UInt<1>("h00") - core.rocc.dptw.req.bits.prv := UInt<1>("h00") - core.rocc.dptw.req.bits.addr := UInt<1>("h00") - core.rocc.dptw.req.valid := UInt<1>("h00") - core.rocc.iptw.req.bits.fetch := UInt<1>("h00") - core.rocc.iptw.req.bits.store := UInt<1>("h00") - core.rocc.iptw.req.bits.prv := UInt<1>("h00") - core.rocc.iptw.req.bits.addr := UInt<1>("h00") - core.rocc.iptw.req.valid := UInt<1>("h00") - core.rocc.dmem.grant.ready := UInt<1>("h00") - core.rocc.dmem.acquire.bits.union := UInt<1>("h00") - core.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") - core.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") - core.rocc.dmem.acquire.bits.data := UInt<1>("h00") - core.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") - core.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") - core.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") - core.rocc.dmem.acquire.valid := UInt<1>("h00") - core.rocc.imem.grant.ready := UInt<1>("h00") - core.rocc.imem.acquire.bits.union := UInt<1>("h00") - core.rocc.imem.acquire.bits.a_type := UInt<1>("h00") - core.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") - core.rocc.imem.acquire.bits.data := UInt<1>("h00") - core.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") - core.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") - core.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") - core.rocc.imem.acquire.valid := UInt<1>("h00") - core.rocc.interrupt := UInt<1>("h00") - core.rocc.busy := UInt<1>("h00") - core.rocc.mem_1.invalidate_lr := UInt<1>("h00") - core.rocc.mem_1.req.bits.data := UInt<1>("h00") - core.rocc.mem_1.req.bits.phys := UInt<1>("h00") - core.rocc.mem_1.req.bits.kill := UInt<1>("h00") - core.rocc.mem_1.req.bits.typ := UInt<1>("h00") - core.rocc.mem_1.req.bits.cmd := UInt<1>("h00") - core.rocc.mem_1.req.bits.tag := UInt<1>("h00") - core.rocc.mem_1.req.bits.addr := UInt<1>("h00") - core.rocc.mem_1.req.valid := UInt<1>("h00") - core.rocc.resp.bits.data := UInt<1>("h00") - core.rocc.resp.bits.rd := UInt<1>("h00") - core.rocc.resp.valid := UInt<1>("h00") - core.rocc.cmd.ready := UInt<1>("h00") - core.fpu.sboard_clra := UInt<1>("h00") - core.fpu.sboard_clr := UInt<1>("h00") - core.fpu.sboard_set := UInt<1>("h00") - core.fpu.dec.wflags := UInt<1>("h00") - core.fpu.dec.round := UInt<1>("h00") - core.fpu.dec.sqrt := UInt<1>("h00") - core.fpu.dec.div := UInt<1>("h00") - core.fpu.dec.fma := UInt<1>("h00") - core.fpu.dec.fastpipe := UInt<1>("h00") - core.fpu.dec.toint := UInt<1>("h00") - core.fpu.dec.fromint := UInt<1>("h00") - core.fpu.dec.single := UInt<1>("h00") - core.fpu.dec.swap23 := UInt<1>("h00") - core.fpu.dec.swap12 := UInt<1>("h00") - core.fpu.dec.ren3 := UInt<1>("h00") - core.fpu.dec.ren2 := UInt<1>("h00") - core.fpu.dec.ren1 := UInt<1>("h00") - core.fpu.dec.wen := UInt<1>("h00") - core.fpu.dec.ldst := UInt<1>("h00") - core.fpu.dec.cmd := UInt<1>("h00") - core.fpu.illegal_rm := UInt<1>("h00") - core.fpu.nack_mem := UInt<1>("h00") - core.fpu.fcsr_rdy := UInt<1>("h00") - core.fpu.toint_data := UInt<1>("h00") - core.fpu.store_data := UInt<1>("h00") - core.fpu.fcsr_flags.bits := UInt<1>("h00") - core.fpu.fcsr_flags.valid := UInt<1>("h00") - core.dmem.ordered := UInt<1>("h00") - core.dmem.xcpt.pf.st := UInt<1>("h00") - core.dmem.xcpt.pf.ld := UInt<1>("h00") - core.dmem.xcpt.ma.st := UInt<1>("h00") - core.dmem.xcpt.ma.ld := UInt<1>("h00") - core.dmem.replay_next.bits := UInt<1>("h00") - core.dmem.replay_next.valid := UInt<1>("h00") - core.dmem.resp.bits.store_data := UInt<1>("h00") - core.dmem.resp.bits.data_subword := UInt<1>("h00") - core.dmem.resp.bits.has_data := UInt<1>("h00") - core.dmem.resp.bits.replay := UInt<1>("h00") - core.dmem.resp.bits.nack := UInt<1>("h00") - core.dmem.resp.bits.data := UInt<1>("h00") - core.dmem.resp.bits.typ := UInt<1>("h00") - core.dmem.resp.bits.cmd := UInt<1>("h00") - core.dmem.resp.bits.tag := UInt<1>("h00") - core.dmem.resp.bits.addr := UInt<1>("h00") - core.dmem.resp.valid := UInt<1>("h00") - core.dmem.req.ready := UInt<1>("h00") - core.imem.npc := UInt<1>("h00") - core.imem.btb_resp.bits.bht.value := UInt<1>("h00") - core.imem.btb_resp.bits.bht.history := UInt<1>("h00") - core.imem.btb_resp.bits.entry := UInt<1>("h00") - core.imem.btb_resp.bits.target := UInt<1>("h00") - core.imem.btb_resp.bits.bridx := UInt<1>("h00") - core.imem.btb_resp.bits.mask := UInt<1>("h00") - core.imem.btb_resp.bits.taken := UInt<1>("h00") - core.imem.btb_resp.valid := UInt<1>("h00") - core.imem.resp.bits.xcpt_if := UInt<1>("h00") - core.imem.resp.bits.mask := UInt<1>("h00") - core.imem.resp.bits.data[0] := UInt<1>("h00") - core.imem.resp.bits.pc := UInt<1>("h00") - core.imem.resp.valid := UInt<1>("h00") - core.host.ipi_rep.bits := UInt<1>("h00") - core.host.ipi_rep.valid := UInt<1>("h00") - core.host.ipi_req.ready := UInt<1>("h00") - core.host.pcr_rep.ready := UInt<1>("h00") - core.host.pcr_req.bits.data := UInt<1>("h00") - core.host.pcr_req.bits.addr := UInt<1>("h00") - core.host.pcr_req.bits.rw := UInt<1>("h00") - core.host.pcr_req.valid := UInt<1>("h00") - core.host.id := UInt<1>("h00") - core.host.reset := UInt<1>("h00") - core.reset := UInt<1>("h00") - core.clock := clock - core.reset := reset - dcache.cpu.invalidate_lr := core.dmem.invalidate_lr - inst dcArb of HellaCacheArbiter - dcArb.mem_1.ordered := UInt<1>("h00") - dcArb.mem_1.xcpt.pf.st := UInt<1>("h00") - dcArb.mem_1.xcpt.pf.ld := UInt<1>("h00") - dcArb.mem_1.xcpt.ma.st := UInt<1>("h00") - dcArb.mem_1.xcpt.ma.ld := UInt<1>("h00") - dcArb.mem_1.replay_next.bits := UInt<1>("h00") - dcArb.mem_1.replay_next.valid := UInt<1>("h00") - dcArb.mem_1.resp.bits.store_data := UInt<1>("h00") - dcArb.mem_1.resp.bits.data_subword := UInt<1>("h00") - dcArb.mem_1.resp.bits.has_data := UInt<1>("h00") - dcArb.mem_1.resp.bits.replay := UInt<1>("h00") - dcArb.mem_1.resp.bits.nack := UInt<1>("h00") - dcArb.mem_1.resp.bits.data := UInt<1>("h00") - dcArb.mem_1.resp.bits.typ := UInt<1>("h00") - dcArb.mem_1.resp.bits.cmd := UInt<1>("h00") - dcArb.mem_1.resp.bits.tag := UInt<1>("h00") - dcArb.mem_1.resp.bits.addr := UInt<1>("h00") - dcArb.mem_1.resp.valid := UInt<1>("h00") - dcArb.mem_1.req.ready := UInt<1>("h00") - dcArb.requestor[0].invalidate_lr := UInt<1>("h00") - dcArb.requestor[0].req.bits.data := UInt<1>("h00") - dcArb.requestor[0].req.bits.phys := UInt<1>("h00") - dcArb.requestor[0].req.bits.kill := UInt<1>("h00") - dcArb.requestor[0].req.bits.typ := UInt<1>("h00") - dcArb.requestor[0].req.bits.cmd := UInt<1>("h00") - dcArb.requestor[0].req.bits.tag := UInt<1>("h00") - dcArb.requestor[0].req.bits.addr := UInt<1>("h00") - dcArb.requestor[0].req.valid := UInt<1>("h00") - dcArb.requestor[1].invalidate_lr := UInt<1>("h00") - dcArb.requestor[1].req.bits.data := UInt<1>("h00") - dcArb.requestor[1].req.bits.phys := UInt<1>("h00") - dcArb.requestor[1].req.bits.kill := UInt<1>("h00") - dcArb.requestor[1].req.bits.typ := UInt<1>("h00") - dcArb.requestor[1].req.bits.cmd := UInt<1>("h00") - dcArb.requestor[1].req.bits.tag := UInt<1>("h00") - dcArb.requestor[1].req.bits.addr := UInt<1>("h00") - dcArb.requestor[1].req.valid := UInt<1>("h00") - dcArb.reset := UInt<1>("h00") - dcArb.clock := clock - dcArb.reset := reset - dcArb.requestor[0] <> ptw.mem_1 - dcArb.requestor[1] <> core.dmem - dcache.cpu <> dcArb.mem_1 - ptw.requestor[0] <> icache.ptw - ptw.requestor[1] <> dcache.ptw - host <> core.host - icache.cpu <> core.imem - core.ptw <> ptw.dpath - inst T_1184 of FPU - T_1184.killm := UInt<1>("h00") - T_1184.killx := UInt<1>("h00") - T_1184.valid := UInt<1>("h00") - T_1184.dmem_resp_data := UInt<1>("h00") - T_1184.dmem_resp_tag := UInt<1>("h00") - T_1184.dmem_resp_type := UInt<1>("h00") - T_1184.dmem_resp_val := UInt<1>("h00") - T_1184.fcsr_rm := UInt<1>("h00") - T_1184.fromint_data := UInt<1>("h00") - T_1184.inst_1 := UInt<1>("h00") - T_1184.reset := UInt<1>("h00") - T_1184.clock := clock - T_1184.reset := reset - core.fpu <> T_1184 - cached <> dcache.mem_1 - uncached <> icache.mem_1 - - module Queue_72 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits.data := UInt<1>("h00") - deq.bits.addr := UInt<1>("h00") - deq.bits.rw := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2], clock - reg T_52 : UInt<1>, clock, reset - onreset T_52 := UInt<1>("h00") - reg T_54 : UInt<1>, clock, reset - onreset T_54 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_52, T_54) - node T_59 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_59) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_65 = and(enq.ready, enq.valid) - node T_67 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_65, T_67) - node T_69 = and(deq.ready, deq.valid) - node T_71 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_69, T_71) - when do_enq : - infer accessor T_73 = ram[T_52] - T_73 <> enq.bits - node T_78 = eq(T_52, UInt<1>("h01")) - node T_80 = and(UInt<1>("h00"), T_78) - node T_83 = addw(T_52, UInt<1>("h01")) - node T_84 = mux(T_80, UInt<1>("h00"), T_83) - T_52 := T_84 - skip - when do_deq : - node T_86 = eq(T_54, UInt<1>("h01")) - node T_88 = and(UInt<1>("h00"), T_86) - node T_91 = addw(T_54, UInt<1>("h01")) - node T_92 = mux(T_88, UInt<1>("h00"), T_91) - T_54 := T_92 - skip - node T_93 = neq(do_enq, do_deq) - when T_93 : - maybe_full := do_enq - skip - node T_95 = eq(empty, UInt<1>("h00")) - node T_97 = and(UInt<1>("h00"), enq.valid) - node T_98 = or(T_95, T_97) - deq.valid := T_98 - node T_100 = eq(full, UInt<1>("h00")) - node T_102 = and(UInt<1>("h00"), deq.ready) - node T_103 = or(T_100, T_102) - enq.ready := T_103 - infer accessor T_104 = ram[T_54] - wire T_112 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>} - T_112 <> T_104 - when maybe_flow : - T_112 <> enq.bits - skip - deq.bits <> T_112 - node ptr_diff = subw(T_52, T_54) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - count := T_118 - - module Queue_73 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : UInt<64>[2], clock - reg T_25 : UInt<1>, clock, reset - onreset T_25 := UInt<1>("h00") - reg T_27 : UInt<1>, clock, reset - onreset T_27 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_25, T_27) - node T_32 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_32) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_38 = and(enq.ready, enq.valid) - node T_40 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_38, T_40) - node T_42 = and(deq.ready, deq.valid) - node T_44 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_42, T_44) - when do_enq : - infer accessor T_46 = ram[T_25] - T_46 := enq.bits - node T_48 = eq(T_25, UInt<1>("h01")) - node T_50 = and(UInt<1>("h00"), T_48) - node T_53 = addw(T_25, UInt<1>("h01")) - node T_54 = mux(T_50, UInt<1>("h00"), T_53) - T_25 := T_54 - skip - when do_deq : - node T_56 = eq(T_27, UInt<1>("h01")) - node T_58 = and(UInt<1>("h00"), T_56) - node T_61 = addw(T_27, UInt<1>("h01")) - node T_62 = mux(T_58, UInt<1>("h00"), T_61) - T_27 := T_62 - skip - node T_63 = neq(do_enq, do_deq) - when T_63 : - maybe_full := do_enq - skip - node T_65 = eq(empty, UInt<1>("h00")) - node T_67 = and(UInt<1>("h00"), enq.valid) - node T_68 = or(T_65, T_67) - deq.valid := T_68 - node T_70 = eq(full, UInt<1>("h00")) - node T_72 = and(UInt<1>("h00"), deq.ready) - node T_73 = or(T_70, T_72) - enq.ready := T_73 - infer accessor T_74 = ram[T_27] - node T_75 = mux(maybe_flow, enq.bits, T_74) - deq.bits := T_75 - node ptr_diff = subw(T_25, T_27) - node T_77 = and(maybe_full, ptr_match) - node T_78 = cat(T_77, ptr_diff) - count := T_78 - - module Queue_74 : - output count : UInt<2> - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} - input clock : Clock - input reset : UInt<1> - - count := UInt<1>("h00") - deq.bits := UInt<1>("h00") - deq.valid := UInt<1>("h00") - enq.ready := UInt<1>("h00") - cmem ram : UInt<1>[2], clock - reg T_25 : UInt<1>, clock, reset - onreset T_25 := UInt<1>("h00") - reg T_27 : UInt<1>, clock, reset - onreset T_27 := UInt<1>("h00") - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") - node ptr_match = eq(T_25, T_27) - node T_32 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_32) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_38 = and(enq.ready, enq.valid) - node T_40 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_38, T_40) - node T_42 = and(deq.ready, deq.valid) - node T_44 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_42, T_44) - when do_enq : - infer accessor T_46 = ram[T_25] - T_46 := enq.bits - node T_48 = eq(T_25, UInt<1>("h01")) - node T_50 = and(UInt<1>("h00"), T_48) - node T_53 = addw(T_25, UInt<1>("h01")) - node T_54 = mux(T_50, UInt<1>("h00"), T_53) - T_25 := T_54 - skip - when do_deq : - node T_56 = eq(T_27, UInt<1>("h01")) - node T_58 = and(UInt<1>("h00"), T_56) - node T_61 = addw(T_27, UInt<1>("h01")) - node T_62 = mux(T_58, UInt<1>("h00"), T_61) - T_27 := T_62 - skip - node T_63 = neq(do_enq, do_deq) - when T_63 : - maybe_full := do_enq - skip - node T_65 = eq(empty, UInt<1>("h00")) - node T_67 = and(UInt<1>("h00"), enq.valid) - node T_68 = or(T_65, T_67) - deq.valid := T_68 - node T_70 = eq(full, UInt<1>("h00")) - node T_72 = and(UInt<1>("h00"), deq.ready) - node T_73 = or(T_70, T_72) - enq.ready := T_73 - infer accessor T_74 = ram[T_27] - node T_75 = mux(maybe_flow, enq.bits, T_74) - deq.bits := T_75 - node ptr_diff = subw(T_25, T_27) - node T_77 = and(maybe_full, ptr_match) - node T_78 = cat(T_77, ptr_diff) - count := T_78 - - module MultiChannelTop : - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] - output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} - output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - mem_1[0].resp.ready := UInt<1>("h00") - mem_1[0].req_data.bits.data := UInt<1>("h00") - mem_1[0].req_data.valid := UInt<1>("h00") - mem_1[0].req_cmd.bits.rw := UInt<1>("h00") - mem_1[0].req_cmd.bits.tag := UInt<1>("h00") - mem_1[0].req_cmd.bits.addr := UInt<1>("h00") - mem_1[0].req_cmd.valid := UInt<1>("h00") - mem_backup_ctrl.out_valid := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.out.bits := UInt<1>("h00") - host.out.valid := UInt<1>("h00") - host.in.ready := UInt<1>("h00") - host.clk_edge := UInt<1>("h00") - host.clk := UInt<1>("h00") - inst uncore of Uncore - uncore.mem_backup_ctrl.out_ready := UInt<1>("h00") - uncore.mem_backup_ctrl.in_valid := UInt<1>("h00") - uncore.mem_backup_ctrl.en := UInt<1>("h00") - uncore.htif[0].debug_stats_pcr := UInt<1>("h00") - uncore.htif[0].ipi_rep.ready := UInt<1>("h00") - uncore.htif[0].ipi_req.bits := UInt<1>("h00") - uncore.htif[0].ipi_req.valid := UInt<1>("h00") - uncore.htif[0].pcr_rep.bits := UInt<1>("h00") - uncore.htif[0].pcr_rep.valid := UInt<1>("h00") - uncore.htif[0].pcr_req.ready := UInt<1>("h00") - uncore.tiles_uncached[0].grant.ready := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") - uncore.tiles_uncached[0].acquire.valid := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.r_type := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.data := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") - uncore.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") - uncore.tiles_cached[0].release.valid := UInt<1>("h00") - uncore.tiles_cached[0].probe.ready := UInt<1>("h00") - uncore.tiles_cached[0].grant.ready := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.union := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.data := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") - uncore.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") - uncore.tiles_cached[0].acquire.valid := UInt<1>("h00") - uncore.mem_1[0].resp.bits.tag := UInt<1>("h00") - uncore.mem_1[0].resp.bits.data := UInt<1>("h00") - uncore.mem_1[0].resp.valid := UInt<1>("h00") - uncore.mem_1[0].req_data.ready := UInt<1>("h00") - uncore.mem_1[0].req_cmd.ready := UInt<1>("h00") - uncore.host.out.ready := UInt<1>("h00") - uncore.host.in.bits := UInt<1>("h00") - uncore.host.in.valid := UInt<1>("h00") - uncore.reset := UInt<1>("h00") - uncore.clock := clock - uncore.reset := reset - inst T_321 of RocketTile - T_321.host.ipi_rep.bits := UInt<1>("h00") - T_321.host.ipi_rep.valid := UInt<1>("h00") - T_321.host.ipi_req.ready := UInt<1>("h00") - T_321.host.pcr_rep.ready := UInt<1>("h00") - T_321.host.pcr_req.bits.data := UInt<1>("h00") - T_321.host.pcr_req.bits.addr := UInt<1>("h00") - T_321.host.pcr_req.bits.rw := UInt<1>("h00") - T_321.host.pcr_req.valid := UInt<1>("h00") - T_321.host.id := UInt<1>("h00") - T_321.host.reset := UInt<1>("h00") - T_321.uncached.grant.bits.g_type := UInt<1>("h00") - T_321.uncached.grant.bits.is_builtin_type := UInt<1>("h00") - T_321.uncached.grant.bits.manager_xact_id := UInt<1>("h00") - T_321.uncached.grant.bits.client_xact_id := UInt<1>("h00") - T_321.uncached.grant.bits.data := UInt<1>("h00") - T_321.uncached.grant.bits.addr_beat := UInt<1>("h00") - T_321.uncached.grant.valid := UInt<1>("h00") - T_321.uncached.acquire.ready := UInt<1>("h00") - T_321.cached.release.ready := UInt<1>("h00") - T_321.cached.probe.bits.p_type := UInt<1>("h00") - T_321.cached.probe.bits.addr_block := UInt<1>("h00") - T_321.cached.probe.valid := UInt<1>("h00") - T_321.cached.grant.bits.g_type := UInt<1>("h00") - T_321.cached.grant.bits.is_builtin_type := UInt<1>("h00") - T_321.cached.grant.bits.manager_xact_id := UInt<1>("h00") - T_321.cached.grant.bits.client_xact_id := UInt<1>("h00") - T_321.cached.grant.bits.data := UInt<1>("h00") - T_321.cached.grant.bits.addr_beat := UInt<1>("h00") - T_321.cached.grant.valid := UInt<1>("h00") - T_321.cached.acquire.ready := UInt<1>("h00") - T_321.reset := UInt<1>("h00") - T_321.clock := clock - T_321.reset := uncore.htif[0].reset - T_321.host.id := UInt<1>("h00") - reg T_293 : UInt<1>, clock, reset - T_293 := uncore.htif[0].reset - reg T_294 : UInt<1>, clock, reset - T_294 := T_293 - T_321.host.reset := T_294 - inst T_322 of Queue_72 - T_322.deq.ready := UInt<1>("h00") - T_322.enq.bits.data := UInt<1>("h00") - T_322.enq.bits.addr := UInt<1>("h00") - T_322.enq.bits.rw := UInt<1>("h00") - T_322.enq.valid := UInt<1>("h00") - T_322.reset := UInt<1>("h00") - T_322.clock := clock - T_322.reset := reset - T_322.enq.valid := uncore.htif[0].pcr_req.valid - T_322.enq.bits <> uncore.htif[0].pcr_req.bits - uncore.htif[0].pcr_req.ready := T_322.enq.ready - T_321.host.pcr_req <> T_322.deq - inst T_323 of Queue_73 - T_323.deq.ready := UInt<1>("h00") - T_323.enq.bits := UInt<1>("h00") - T_323.enq.valid := UInt<1>("h00") - T_323.reset := UInt<1>("h00") - T_323.clock := clock - T_323.reset := reset - T_323.enq.valid := T_321.host.pcr_rep.valid - T_323.enq.bits := T_321.host.pcr_rep.bits - T_321.host.pcr_rep.ready := T_323.enq.ready - uncore.htif[0].pcr_rep <> T_323.deq - inst T_324 of Queue_74 - T_324.deq.ready := UInt<1>("h00") - T_324.enq.bits := UInt<1>("h00") - T_324.enq.valid := UInt<1>("h00") - T_324.reset := UInt<1>("h00") - T_324.clock := clock - T_324.reset := reset - T_324.enq.valid := T_321.host.ipi_req.valid - T_324.enq.bits := T_321.host.ipi_req.bits - T_321.host.ipi_req.ready := T_324.enq.ready - uncore.htif[0].ipi_req <> T_324.deq - inst T_325 of Queue_74 - T_325.deq.ready := UInt<1>("h00") - T_325.enq.bits := UInt<1>("h00") - T_325.enq.valid := UInt<1>("h00") - T_325.reset := UInt<1>("h00") - T_325.clock := clock - T_325.reset := reset - T_325.enq.valid := uncore.htif[0].ipi_rep.valid - T_325.enq.bits := uncore.htif[0].ipi_rep.bits - uncore.htif[0].ipi_rep.ready := T_325.enq.ready - T_321.host.ipi_rep <> T_325.deq - uncore.htif[0].debug_stats_pcr := T_321.host.debug_stats_pcr - uncore.tiles_cached[0] <> T_321.cached - uncore.tiles_uncached[0] <> T_321.uncached - host <> uncore.host - mem_1 <> uncore.mem_1 - mem_backup_ctrl <> uncore.mem_backup_ctrl - - module Top : - output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} - output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} - input clock : Clock - input reset : UInt<1> - - mem_1.resp.ready := UInt<1>("h00") - mem_1.req_data.bits.data := UInt<1>("h00") - mem_1.req_data.valid := UInt<1>("h00") - mem_1.req_cmd.bits.rw := UInt<1>("h00") - mem_1.req_cmd.bits.tag := UInt<1>("h00") - mem_1.req_cmd.bits.addr := UInt<1>("h00") - mem_1.req_cmd.valid := UInt<1>("h00") - mem_backup_ctrl.out_valid := UInt<1>("h00") - host.debug_stats_pcr := UInt<1>("h00") - host.out.bits := UInt<1>("h00") - host.out.valid := UInt<1>("h00") - host.in.ready := UInt<1>("h00") - host.clk_edge := UInt<1>("h00") - host.clk := UInt<1>("h00") - inst T_102 of MultiChannelTop - T_102.mem_1[0].resp.bits.tag := UInt<1>("h00") - T_102.mem_1[0].resp.bits.data := UInt<1>("h00") - T_102.mem_1[0].resp.valid := UInt<1>("h00") - T_102.mem_1[0].req_data.ready := UInt<1>("h00") - T_102.mem_1[0].req_cmd.ready := UInt<1>("h00") - T_102.mem_backup_ctrl.out_ready := UInt<1>("h00") - T_102.mem_backup_ctrl.in_valid := UInt<1>("h00") - T_102.mem_backup_ctrl.en := UInt<1>("h00") - T_102.host.out.ready := UInt<1>("h00") - T_102.host.in.bits := UInt<1>("h00") - T_102.host.in.valid := UInt<1>("h00") - T_102.reset := UInt<1>("h00") - T_102.clock := clock - T_102.reset := reset - inst T_103 of MemIOArbiter - T_103.outer.resp.bits.tag := UInt<1>("h00") - T_103.outer.resp.bits.data := UInt<1>("h00") - T_103.outer.resp.valid := UInt<1>("h00") - T_103.outer.req_data.ready := UInt<1>("h00") - T_103.outer.req_cmd.ready := UInt<1>("h00") - T_103.inner[0].resp.ready := UInt<1>("h00") - T_103.inner[0].req_data.bits.data := UInt<1>("h00") - T_103.inner[0].req_data.valid := UInt<1>("h00") - T_103.inner[0].req_cmd.bits.rw := UInt<1>("h00") - T_103.inner[0].req_cmd.bits.tag := UInt<1>("h00") - T_103.inner[0].req_cmd.bits.addr := UInt<1>("h00") - T_103.inner[0].req_cmd.valid := UInt<1>("h00") - T_103.reset := UInt<1>("h00") - T_103.clock := clock - T_103.reset := reset - T_103.inner <> T_102.mem_1 - mem_1 <> T_103.outer - mem_backup_ctrl <> T_102.mem_backup_ctrl - host <> T_102.host - diff --git a/regress/rocket.fir b/regress/rocket.fir index adc4bb4d..9fd52968 100644 --- a/regress/rocket.fir +++ b/regress/rocket.fir @@ -1,32400 +1,147661 @@ -circuit Top : - module Htif : - input clk : Clock +;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.7, sbtVersion: 0.13.12, builtAtString: 2017-03-15 22:45:25.683, builtAtMillis: 1489617925683 +circuit TestHarness : + module TLXbar_socBus : + input clock : Clock input reset : UInt<1> - output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - io.host.debug_stats_csr <= io.cpu[0].debug_stats_csr - reg rx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00"))) - reg rx_shifter : UInt<64>, clk - node T_1212 = bits(rx_shifter, 63, 16) - node rx_shifter_in = cat(io.host.in.bits, T_1212) - node next_cmd = bits(rx_shifter_in, 3, 0) - reg cmd : UInt, clk - reg size : UInt, clk - reg pos : UInt, clk - reg seqno : UInt, clk - reg addr : UInt, clk - node T_1225 = and(io.host.in.valid, io.host.in.ready) - when T_1225 : - rx_shifter <= rx_shifter_in - node T_1227 = add(rx_count, UInt<1>("h01")) - node T_1228 = tail(T_1227, 1) - rx_count <= T_1228 - node T_1230 = eq(rx_count, UInt<2>("h03")) - when T_1230 : - cmd <= next_cmd - node T_1231 = bits(rx_shifter_in, 15, 4) - size <= T_1231 - node T_1232 = bits(rx_shifter_in, 15, 7) - pos <= T_1232 - node T_1233 = bits(rx_shifter_in, 23, 16) - seqno <= T_1233 - node T_1234 = bits(rx_shifter_in, 63, 24) - addr <= T_1234 - skip - skip - node rx_word_count = shr(rx_count, 2) - node T_1236 = bits(rx_count, 1, 0) - node T_1237 = not(T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node rx_word_done = and(io.host.in.valid, T_1239) - cmem packet_ram : UInt<64>[8] - node T_1244 = and(rx_word_done, io.host.in.ready) - when T_1244 : - node T_1245 = bits(rx_word_count, 2, 0) - node T_1247 = sub(T_1245, UInt<1>("h01")) - node T_1248 = tail(T_1247, 1) - infer mport T_1249 = packet_ram[T_1248], clk - T_1249 <= rx_shifter_in - skip - node csr_addr = bits(addr, 11, 0) - node csr_coreid = bits(addr, 21, 20) - infer mport csr_wdata = packet_ram[UInt<1>("h00")], clk - node T_1261 = bits(size, 2, 0) - node T_1263 = neq(T_1261, UInt<1>("h00")) - node T_1264 = bits(addr, 2, 0) - node T_1266 = neq(T_1264, UInt<1>("h00")) - node bad_mem_packet = or(T_1263, T_1266) - node T_1268 = eq(cmd, UInt<1>("h00")) - node T_1269 = eq(cmd, UInt<1>("h01")) - node T_1270 = or(T_1268, T_1269) - node T_1271 = eq(cmd, UInt<2>("h02")) - node T_1272 = eq(cmd, UInt<2>("h03")) - node T_1273 = or(T_1271, T_1272) - node T_1275 = neq(size, UInt<1>("h01")) - node T_1277 = mux(T_1273, T_1275, UInt<1>("h01")) - node nack = mux(T_1270, bad_mem_packet, T_1277) - reg tx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00"))) - node tx_subword_count = bits(tx_count, 1, 0) - node tx_word_count = bits(tx_count, 14, 2) - node T_1283 = bits(tx_word_count, 2, 0) - node T_1285 = sub(T_1283, UInt<1>("h01")) - node packet_ram_raddr = tail(T_1285, 1) - node T_1287 = and(io.host.out.valid, io.host.out.ready) - when T_1287 : - node T_1289 = add(tx_count, UInt<1>("h01")) - node T_1290 = tail(T_1289, 1) - tx_count <= T_1290 - skip - node T_1292 = eq(rx_word_count, UInt<1>("h00")) - node T_1293 = neq(next_cmd, UInt<1>("h01")) - node T_1294 = neq(next_cmd, UInt<2>("h03")) - node T_1295 = and(T_1293, T_1294) - node T_1296 = eq(rx_word_count, size) - node T_1297 = bits(rx_word_count, 2, 0) - node T_1299 = eq(T_1297, UInt<1>("h00")) - node T_1300 = or(T_1296, T_1299) - node T_1301 = mux(T_1292, T_1295, T_1300) - node rx_done = and(rx_word_done, T_1301) - node T_1304 = eq(nack, UInt<1>("h00")) - node T_1305 = eq(cmd, UInt<1>("h00")) - node T_1306 = eq(cmd, UInt<2>("h02")) - node T_1307 = or(T_1305, T_1306) - node T_1308 = eq(cmd, UInt<2>("h03")) - node T_1309 = or(T_1307, T_1308) - node T_1310 = and(T_1304, T_1309) - node tx_size = mux(T_1310, size, UInt<1>("h00")) - node T_1313 = not(tx_subword_count) - node T_1315 = eq(T_1313, UInt<1>("h00")) - node T_1316 = and(io.host.out.ready, T_1315) - node T_1317 = eq(tx_word_count, tx_size) - node T_1319 = gt(tx_word_count, UInt<1>("h00")) - node T_1320 = not(packet_ram_raddr) - node T_1322 = eq(T_1320, UInt<1>("h00")) - node T_1323 = and(T_1319, T_1322) - node T_1324 = or(T_1317, T_1323) - node tx_done = and(T_1316, T_1324) - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1336 = eq(state, UInt<3>("h04")) - node T_1337 = and(T_1336, io.mem.acquire.ready) - node T_1338 = eq(state, UInt<3>("h05")) - node T_1339 = and(T_1338, io.mem.grant.valid) - node T_1340 = or(T_1337, T_1339) - reg cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1340 : - node T_1344 = eq(cnt, UInt<2>("h03")) - node T_1346 = and(UInt<1>("h00"), T_1344) - node T_1349 = add(cnt, UInt<1>("h01")) - node T_1350 = tail(T_1349, 1) - node T_1351 = mux(T_1346, UInt<1>("h00"), T_1350) - cnt <= T_1351 - skip - node cnt_done = and(T_1340, T_1344) - node T_1354 = eq(rx_word_count, UInt<1>("h00")) - node rx_cmd = mux(T_1354, next_cmd, cmd) - node T_1356 = eq(state, UInt<1>("h00")) - node T_1357 = and(T_1356, rx_done) - when T_1357 : - node T_1358 = eq(rx_cmd, UInt<1>("h00")) - node T_1359 = eq(rx_cmd, UInt<1>("h01")) - node T_1360 = eq(rx_cmd, UInt<2>("h02")) - node T_1361 = eq(rx_cmd, UInt<2>("h03")) - node T_1362 = or(T_1360, T_1361) - node T_1363 = mux(T_1362, UInt<1>("h01"), UInt<3>("h07")) - node T_1364 = mux(T_1359, UInt<3>("h04"), T_1363) - node T_1365 = mux(T_1358, UInt<2>("h03"), T_1364) - state <= T_1365 - skip - node T_1366 = eq(state, UInt<3>("h04")) - when T_1366 : - when cnt_done : - state <= UInt<3>("h06") - skip - skip - node T_1367 = eq(state, UInt<2>("h03")) - when T_1367 : - when io.mem.acquire.ready : - state <= UInt<3>("h05") - skip - skip - node T_1368 = eq(state, UInt<3>("h06")) - node T_1369 = and(T_1368, io.mem.grant.valid) - when T_1369 : - node T_1370 = eq(cmd, UInt<1>("h00")) - node T_1372 = eq(pos, UInt<1>("h01")) - node T_1373 = or(T_1370, T_1372) - node T_1374 = mux(T_1373, UInt<3>("h07"), UInt<1>("h00")) - state <= T_1374 - node T_1376 = sub(pos, UInt<1>("h01")) - node T_1377 = tail(T_1376, 1) - pos <= T_1377 - node T_1379 = add(addr, UInt<4>("h08")) - node T_1380 = tail(T_1379, 1) - addr <= T_1380 - skip - node T_1381 = eq(state, UInt<3>("h05")) - node T_1382 = and(T_1381, cnt_done) - when T_1382 : - node T_1383 = eq(cmd, UInt<1>("h00")) - node T_1385 = eq(pos, UInt<1>("h01")) - node T_1386 = or(T_1383, T_1385) - node T_1387 = mux(T_1386, UInt<3>("h07"), UInt<1>("h00")) - state <= T_1387 - node T_1389 = sub(pos, UInt<1>("h01")) - node T_1390 = tail(T_1389, 1) - pos <= T_1390 - node T_1392 = add(addr, UInt<4>("h08")) - node T_1393 = tail(T_1392, 1) - addr <= T_1393 - skip - node T_1394 = eq(state, UInt<3>("h07")) - node T_1395 = and(T_1394, tx_done) - when T_1395 : - node T_1396 = eq(tx_word_count, tx_size) - when T_1396 : - rx_count <= UInt<1>("h00") - tx_count <= UInt<1>("h00") - skip - node T_1399 = eq(cmd, UInt<1>("h00")) - node T_1401 = neq(pos, UInt<1>("h00")) - node T_1402 = and(T_1399, T_1401) - node T_1403 = mux(T_1402, UInt<2>("h03"), UInt<1>("h00")) - state <= T_1403 - skip - node T_1405 = eq(state, UInt<3>("h05")) - node T_1406 = and(T_1405, io.mem.grant.valid) - when T_1406 : - node T_1407 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00")) - infer mport T_1408 = packet_ram[T_1407], clk - node T_1409 = bits(io.mem.grant.bits.data, 63, 0) - T_1408 <= T_1409 - skip - node T_1410 = cat(cnt, UInt<1>("h00")) - infer mport T_1411 = packet_ram[T_1410], clk - node T_1413 = eq(state, UInt<3>("h05")) - node T_1414 = and(T_1413, io.mem.grant.valid) - when T_1414 : - node T_1415 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01")) - infer mport T_1416 = packet_ram[T_1415], clk - node T_1417 = bits(io.mem.grant.bits.data, 127, 64) - T_1416 <= T_1417 - skip - node T_1418 = cat(cnt, UInt<1>("h01")) - infer mport T_1419 = packet_ram[T_1418], clk - node mem_req_data = cat(T_1419, T_1411) - node init_addr = shr(addr, 3) - node T_1422 = eq(state, UInt<2>("h03")) - node T_1423 = eq(state, UInt<3>("h04")) - node T_1424 = or(T_1422, T_1423) - io.mem.acquire.valid <= T_1424 - node T_1425 = eq(cmd, UInt<1>("h01")) - node T_1453 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_1459 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1460 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1461 = cat(T_1459, T_1460) - node T_1463 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1464 = cat(UInt<3>("h07"), T_1463) - node T_1466 = cat(T_1453, UInt<1>("h01")) - node T_1468 = cat(T_1453, UInt<1>("h01")) - node T_1470 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1471 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1472 = cat(T_1470, T_1471) - node T_1474 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1476 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1477 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1478 = mux(T_1477, T_1476, UInt<1>("h00")) - node T_1479 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1480 = mux(T_1479, T_1474, T_1478) - node T_1481 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1482 = mux(T_1481, T_1472, T_1480) - node T_1483 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1484 = mux(T_1483, T_1468, T_1482) - node T_1485 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1486 = mux(T_1485, T_1466, T_1484) - node T_1487 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1488 = mux(T_1487, T_1464, T_1486) - node T_1489 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1490 = mux(T_1489, T_1461, T_1488) - wire T_1522 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1522 is invalid - T_1522.is_builtin_type <= UInt<1>("h01") - T_1522.a_type <= UInt<3>("h03") - T_1522.client_xact_id <= UInt<1>("h00") - T_1522.addr_block <= init_addr - T_1522.addr_beat <= cnt - T_1522.data <= mem_req_data - T_1522.union <= T_1490 - node T_1563 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1564 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1565 = cat(T_1563, T_1564) - node T_1567 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1568 = cat(UInt<3>("h07"), T_1567) - node T_1570 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1572 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1574 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1575 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1576 = cat(T_1574, T_1575) - node T_1578 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1580 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1581 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1582 = mux(T_1581, T_1580, UInt<1>("h00")) - node T_1583 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1584 = mux(T_1583, T_1578, T_1582) - node T_1585 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1586 = mux(T_1585, T_1576, T_1584) - node T_1587 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1588 = mux(T_1587, T_1572, T_1586) - node T_1589 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1590 = mux(T_1589, T_1570, T_1588) - node T_1591 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1592 = mux(T_1591, T_1568, T_1590) - node T_1593 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1594 = mux(T_1593, T_1565, T_1592) - wire T_1626 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1626 is invalid - T_1626.is_builtin_type <= UInt<1>("h01") - T_1626.a_type <= UInt<3>("h01") - T_1626.client_xact_id <= UInt<1>("h00") - T_1626.addr_block <= init_addr - T_1626.addr_beat <= UInt<1>("h00") - T_1626.data <= UInt<1>("h00") - T_1626.union <= T_1594 - node T_1657 = mux(T_1425, T_1522, T_1626) - io.mem.acquire.bits <- T_1657 - io.mem.grant.ready <= UInt<1>("h01") - reg csrReadData : UInt<64>, clk - reg T_1692 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - node T_1694 = eq(csr_coreid, UInt<1>("h00")) - node T_1695 = eq(state, UInt<1>("h01")) - node T_1696 = and(T_1695, T_1694) - node T_1698 = neq(csr_addr, UInt<11>("h0782")) - node T_1699 = and(T_1696, T_1698) - io.cpu[0].csr.req.valid <= T_1699 - node T_1700 = eq(cmd, UInt<2>("h03")) - io.cpu[0].csr.req.bits.rw <= T_1700 - io.cpu[0].csr.req.bits.addr <= csr_addr - io.cpu[0].csr.req.bits.data <= csr_wdata - io.cpu[0].reset <= T_1692 - node T_1701 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid) - when T_1701 : - state <= UInt<2>("h02") - skip - node T_1702 = eq(state, UInt<1>("h01")) - node T_1703 = and(T_1702, T_1694) - node T_1705 = eq(csr_addr, UInt<11>("h0782")) - node T_1706 = and(T_1703, T_1705) - when T_1706 : - node T_1707 = eq(cmd, UInt<2>("h03")) - when T_1707 : - node T_1708 = bits(csr_wdata, 0, 0) - T_1692 <= T_1708 - skip - csrReadData <= T_1692 - state <= UInt<3>("h07") - skip - io.cpu[0].csr.resp.ready <= UInt<1>("h01") - node T_1710 = eq(state, UInt<2>("h02")) - node T_1711 = and(T_1710, io.cpu[0].csr.resp.valid) - when T_1711 : - csrReadData <= io.cpu[0].csr.resp.bits - state <= UInt<3>("h07") - skip - node T_1712 = eq(state, UInt<1>("h01")) - node T_1713 = not(csr_coreid) - node T_1715 = eq(T_1713, UInt<1>("h00")) - node T_1716 = and(T_1712, T_1715) - io.scr.req.valid <= T_1716 - node T_1717 = bits(addr, 5, 0) - io.scr.req.bits.addr <= T_1717 - io.scr.req.bits.data <= csr_wdata - node T_1718 = eq(cmd, UInt<2>("h03")) - io.scr.req.bits.rw <= T_1718 - io.scr.resp.ready <= UInt<1>("h01") - node T_1720 = and(io.scr.req.ready, io.scr.req.valid) - when T_1720 : - state <= UInt<2>("h02") - skip - node T_1721 = eq(state, UInt<2>("h02")) - node T_1722 = and(T_1721, io.scr.resp.valid) - when T_1722 : - csrReadData <= io.scr.resp.bits - state <= UInt<3>("h07") - skip - node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) - node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) - node T_1726 = cat(addr, seqno) - node T_1727 = cat(tx_size, tx_cmd_ext) - node tx_header = cat(T_1726, T_1727) - node T_1730 = eq(tx_word_count, UInt<1>("h00")) - node T_1731 = eq(cmd, UInt<2>("h02")) - node T_1732 = eq(cmd, UInt<2>("h03")) - node T_1733 = or(T_1731, T_1732) - infer mport T_1734 = packet_ram[packet_ram_raddr], clk - node T_1735 = mux(T_1733, csrReadData, T_1734) - node tx_data = mux(T_1730, tx_header, T_1735) - node T_1737 = eq(state, UInt<1>("h00")) - io.host.in.ready <= T_1737 - node T_1738 = eq(state, UInt<3>("h07")) - io.host.out.valid <= T_1738 - node T_1739 = bits(tx_count, 1, 0) - node T_1741 = cat(T_1739, UInt<4>("h00")) - node T_1742 = dshr(tx_data, T_1741) - io.host.out.bits <= T_1742 - - module ClientTileLinkIOWrapper : - input clk : Clock + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + wire in : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1] @[Xbar.scala 103:18] + in is invalid @[Xbar.scala 103:18] + in[0] <- io.in.0 @[Xbar.scala 106:13] + node _T_1928 = or(io.in.0.a.bits.source, UInt<1>("h00")) @[Xbar.scala 108:53] + in[0].a.bits.source <= _T_1928 @[Xbar.scala 108:27] + node _T_1930 = or(io.in.0.c.bits.source, UInt<1>("h00")) @[Xbar.scala 109:53] + in[0].c.bits.source <= _T_1930 @[Xbar.scala 109:27] + node _T_1931 = bits(in[0].b.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.b.bits.source <= _T_1931 @[Xbar.scala 111:30] + node _T_1932 = bits(in[0].d.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.d.bits.source <= _T_1932 @[Xbar.scala 112:30] + wire out : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[2] @[Xbar.scala 116:19] + out is invalid @[Xbar.scala 116:19] + io.out.0 <- out[0] @[Xbar.scala 119:17] + node _T_3681 = or(io.out.0.d.bits.sink, UInt<1>("h01")) @[Xbar.scala 121:51] + out[0].d.bits.sink <= _T_3681 @[Xbar.scala 121:26] + io.out.0.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + io.out.1 <- out[1] @[Xbar.scala 119:17] + node _T_3684 = or(io.out.1.d.bits.sink, UInt<1>("h00")) @[Xbar.scala 121:51] + out[1].d.bits.sink <= _T_3684 @[Xbar.scala 121:26] + io.out.1.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + node _T_3687 = xor(in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3688 = cvt(_T_3687) @[Parameters.scala 117:49] + node _T_3690 = and(_T_3688, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_3691 = asSInt(_T_3690) @[Parameters.scala 117:52] + node _T_3693 = eq(_T_3691, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3695 = xor(in[0].a.bits.address, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_3696 = cvt(_T_3695) @[Parameters.scala 117:49] + node _T_3698 = and(_T_3696, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_3699 = asSInt(_T_3698) @[Parameters.scala 117:52] + node _T_3701 = eq(_T_3699, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3704 : UInt<1>[2] @[Xbar.scala 129:49] + _T_3704 is invalid @[Xbar.scala 129:49] + _T_3704[0] <= _T_3693 @[Xbar.scala 129:49] + _T_3704[1] <= _T_3701 @[Xbar.scala 129:49] + wire requestAIO : UInt<1>[2][1] @[Xbar.scala 129:25] + requestAIO is invalid @[Xbar.scala 129:25] + requestAIO[0] <- _T_3704 @[Xbar.scala 129:25] + node _T_3763 = xor(in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3764 = cvt(_T_3763) @[Parameters.scala 117:49] + node _T_3766 = and(_T_3764, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_3767 = asSInt(_T_3766) @[Parameters.scala 117:52] + node _T_3769 = eq(_T_3767, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3771 = xor(in[0].c.bits.address, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_3772 = cvt(_T_3771) @[Parameters.scala 117:49] + node _T_3774 = and(_T_3772, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_3775 = asSInt(_T_3774) @[Parameters.scala 117:52] + node _T_3777 = eq(_T_3775, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3780 : UInt<1>[2] @[Xbar.scala 130:49] + _T_3780 is invalid @[Xbar.scala 130:49] + _T_3780[0] <= _T_3769 @[Xbar.scala 130:49] + _T_3780[1] <= _T_3777 @[Xbar.scala 130:49] + wire requestCIO : UInt<1>[2][1] @[Xbar.scala 130:25] + requestCIO is invalid @[Xbar.scala 130:25] + requestCIO[0] <- _T_3780 @[Xbar.scala 130:25] + node _T_3839 = xor(UInt<1>("h00"), out[0].b.bits.source) @[Parameters.scala 37:23] + node _T_3840 = not(_T_3839) @[Parameters.scala 37:9] + node _T_3842 = or(_T_3840, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3843 = not(_T_3842) @[Parameters.scala 37:7] + node _T_3845 = eq(_T_3843, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3848 : UInt<1>[1] @[Xbar.scala 131:44] + _T_3848 is invalid @[Xbar.scala 131:44] + _T_3848[0] <= _T_3845 @[Xbar.scala 131:44] + node _T_3853 = xor(UInt<1>("h00"), out[1].b.bits.source) @[Parameters.scala 37:23] + node _T_3854 = not(_T_3853) @[Parameters.scala 37:9] + node _T_3856 = or(_T_3854, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3857 = not(_T_3856) @[Parameters.scala 37:7] + node _T_3859 = eq(_T_3857, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3862 : UInt<1>[1] @[Xbar.scala 131:44] + _T_3862 is invalid @[Xbar.scala 131:44] + _T_3862[0] <= _T_3859 @[Xbar.scala 131:44] + wire requestBOI : UInt<1>[1][2] @[Xbar.scala 131:25] + requestBOI is invalid @[Xbar.scala 131:25] + requestBOI[0] <- _T_3848 @[Xbar.scala 131:25] + requestBOI[1] <- _T_3862 @[Xbar.scala 131:25] + node _T_3924 = xor(UInt<1>("h00"), out[0].d.bits.source) @[Parameters.scala 37:23] + node _T_3925 = not(_T_3924) @[Parameters.scala 37:9] + node _T_3927 = or(_T_3925, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3928 = not(_T_3927) @[Parameters.scala 37:7] + node _T_3930 = eq(_T_3928, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3933 : UInt<1>[1] @[Xbar.scala 132:44] + _T_3933 is invalid @[Xbar.scala 132:44] + _T_3933[0] <= _T_3930 @[Xbar.scala 132:44] + node _T_3938 = xor(UInt<1>("h00"), out[1].d.bits.source) @[Parameters.scala 37:23] + node _T_3939 = not(_T_3938) @[Parameters.scala 37:9] + node _T_3941 = or(_T_3939, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3942 = not(_T_3941) @[Parameters.scala 37:7] + node _T_3944 = eq(_T_3942, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3947 : UInt<1>[1] @[Xbar.scala 132:44] + _T_3947 is invalid @[Xbar.scala 132:44] + _T_3947[0] <= _T_3944 @[Xbar.scala 132:44] + wire requestDOI : UInt<1>[1][2] @[Xbar.scala 132:25] + requestDOI is invalid @[Xbar.scala 132:25] + requestDOI[0] <- _T_3933 @[Xbar.scala 132:25] + requestDOI[1] <- _T_3947 @[Xbar.scala 132:25] + node _T_4009 = eq(UInt<1>("h01"), in[0].e.bits.sink) @[Parameters.scala 35:39] + node _T_4011 = eq(UInt<1>("h00"), in[0].e.bits.sink) @[Parameters.scala 35:39] + wire _T_4014 : UInt<1>[2] @[Xbar.scala 133:44] + _T_4014 is invalid @[Xbar.scala 133:44] + _T_4014[0] <= _T_4009 @[Xbar.scala 133:44] + _T_4014[1] <= _T_4011 @[Xbar.scala 133:44] + wire requestEIO : UInt<1>[2][1] @[Xbar.scala 133:25] + requestEIO is invalid @[Xbar.scala 133:25] + requestEIO[0] <- _T_4014 @[Xbar.scala 133:25] + node _T_4073 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4074 = dshl(_T_4073, in[0].a.bits.size) @[package.scala 19:71] + node _T_4075 = bits(_T_4074, 7, 0) @[package.scala 19:76] + node _T_4076 = not(_T_4075) @[package.scala 19:40] + node _T_4077 = shr(_T_4076, 3) @[Edges.scala 198:59] + node _T_4078 = bits(in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4080 = eq(_T_4078, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4082 = mux(_T_4080, _T_4077, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsAI : UInt<5>[1] @[Xbar.scala 135:22] + beatsAI is invalid @[Xbar.scala 135:22] + beatsAI[0] <= _T_4082 @[Xbar.scala 135:22] + node _T_4089 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4090 = dshl(_T_4089, out[0].b.bits.size) @[package.scala 19:71] + node _T_4091 = bits(_T_4090, 5, 0) @[package.scala 19:76] + node _T_4092 = not(_T_4091) @[package.scala 19:40] + node _T_4093 = shr(_T_4092, 3) @[Edges.scala 198:59] + node _T_4094 = bits(out[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4096 = eq(_T_4094, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4099 = mux(UInt<1>("h00"), _T_4093, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4101 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4102 = dshl(_T_4101, out[1].b.bits.size) @[package.scala 19:71] + node _T_4103 = bits(_T_4102, 7, 0) @[package.scala 19:76] + node _T_4104 = not(_T_4103) @[package.scala 19:40] + node _T_4105 = shr(_T_4104, 3) @[Edges.scala 198:59] + node _T_4106 = bits(out[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4108 = eq(_T_4106, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4111 = mux(UInt<1>("h00"), _T_4105, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsBO : UInt<5>[2] @[Xbar.scala 136:22] + beatsBO is invalid @[Xbar.scala 136:22] + beatsBO[0] <= _T_4099 @[Xbar.scala 136:22] + beatsBO[1] <= _T_4111 @[Xbar.scala 136:22] + node _T_4119 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4120 = dshl(_T_4119, in[0].c.bits.size) @[package.scala 19:71] + node _T_4121 = bits(_T_4120, 7, 0) @[package.scala 19:76] + node _T_4122 = not(_T_4121) @[package.scala 19:40] + node _T_4123 = shr(_T_4122, 3) @[Edges.scala 198:59] + node _T_4124 = bits(in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4126 = mux(_T_4124, _T_4123, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsCI : UInt<5>[1] @[Xbar.scala 137:22] + beatsCI is invalid @[Xbar.scala 137:22] + beatsCI[0] <= _T_4126 @[Xbar.scala 137:22] + node _T_4133 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4134 = dshl(_T_4133, out[0].d.bits.size) @[package.scala 19:71] + node _T_4135 = bits(_T_4134, 5, 0) @[package.scala 19:76] + node _T_4136 = not(_T_4135) @[package.scala 19:40] + node _T_4137 = shr(_T_4136, 3) @[Edges.scala 198:59] + node _T_4138 = bits(out[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4141 = mux(UInt<1>("h01"), _T_4137, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4143 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4144 = dshl(_T_4143, out[1].d.bits.size) @[package.scala 19:71] + node _T_4145 = bits(_T_4144, 7, 0) @[package.scala 19:76] + node _T_4146 = not(_T_4145) @[package.scala 19:40] + node _T_4147 = shr(_T_4146, 3) @[Edges.scala 198:59] + node _T_4148 = bits(out[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4150 = mux(_T_4148, _T_4147, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsDO : UInt<5>[2] @[Xbar.scala 138:22] + beatsDO is invalid @[Xbar.scala 138:22] + beatsDO[0] <= _T_4141 @[Xbar.scala 138:22] + beatsDO[1] <= _T_4150 @[Xbar.scala 138:22] + wire beatsEI : UInt<1>[1] @[Xbar.scala 139:22] + beatsEI is invalid @[Xbar.scala 139:22] + beatsEI[0] <= UInt<1>("h00") @[Xbar.scala 139:22] + wire _T_4225 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}[2] @[Xbar.scala 147:26] + _T_4225 is invalid @[Xbar.scala 147:26] + _T_4225[0].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_4350 = and(in[0].a.valid, requestAIO[0][0]) @[Xbar.scala 150:42] + _T_4225[0].valid <= _T_4350 @[Xbar.scala 150:27] + _T_4225[1].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_4351 = and(in[0].a.valid, requestAIO[0][1]) @[Xbar.scala 150:42] + _T_4225[1].valid <= _T_4351 @[Xbar.scala 150:27] + node _T_4353 = mux(requestAIO[0][0], _T_4225[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4355 = mux(requestAIO[0][1], _T_4225[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4357 = or(_T_4353, _T_4355) @[Mux.scala 19:72] + wire _T_4359 : UInt<1> @[Mux.scala 19:72] + _T_4359 is invalid @[Mux.scala 19:72] + _T_4359 <= _T_4357 @[Mux.scala 19:72] + in[0].a.ready <= _T_4359 @[Xbar.scala 152:19] + wire _T_4402 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_4402 is invalid @[Xbar.scala 147:26] + _T_4402[0].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_4486 = and(out[0].b.valid, requestBOI[0][0]) @[Xbar.scala 150:42] + _T_4402[0].valid <= _T_4486 @[Xbar.scala 150:27] + out[0].b.ready <= _T_4402[0].ready @[Xbar.scala 152:19] + wire _T_4529 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_4529 is invalid @[Xbar.scala 147:26] + _T_4529[0].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_4613 = and(out[1].b.valid, requestBOI[1][0]) @[Xbar.scala 150:42] + _T_4529[0].valid <= _T_4613 @[Xbar.scala 150:27] + out[1].b.ready <= _T_4529[0].ready @[Xbar.scala 152:19] + wire _T_4676 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}[2] @[Xbar.scala 147:26] + _T_4676 is invalid @[Xbar.scala 147:26] + _T_4676[0].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_4801 = and(in[0].c.valid, requestCIO[0][0]) @[Xbar.scala 150:42] + _T_4676[0].valid <= _T_4801 @[Xbar.scala 150:27] + _T_4676[1].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_4802 = and(in[0].c.valid, requestCIO[0][1]) @[Xbar.scala 150:42] + _T_4676[1].valid <= _T_4802 @[Xbar.scala 150:27] + node _T_4804 = mux(requestCIO[0][0], _T_4676[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4806 = mux(requestCIO[0][1], _T_4676[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4808 = or(_T_4804, _T_4806) @[Mux.scala 19:72] + wire _T_4810 : UInt<1> @[Mux.scala 19:72] + _T_4810 is invalid @[Mux.scala 19:72] + _T_4810 <= _T_4808 @[Mux.scala 19:72] + in[0].c.ready <= _T_4810 @[Xbar.scala 152:19] + wire _T_4857 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_4857 is invalid @[Xbar.scala 147:26] + _T_4857[0].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_4949 = and(out[0].d.valid, requestDOI[0][0]) @[Xbar.scala 150:42] + _T_4857[0].valid <= _T_4949 @[Xbar.scala 150:27] + out[0].d.ready <= _T_4857[0].ready @[Xbar.scala 152:19] + wire _T_4996 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_4996 is invalid @[Xbar.scala 147:26] + _T_4996[0].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_5088 = and(out[1].d.valid, requestDOI[1][0]) @[Xbar.scala 150:42] + _T_4996[0].valid <= _T_5088 @[Xbar.scala 150:27] + out[1].d.ready <= _T_4996[0].ready @[Xbar.scala 152:19] + wire _T_5115 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}[2] @[Xbar.scala 147:26] + _T_5115 is invalid @[Xbar.scala 147:26] + _T_5115[0].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_5168 = and(in[0].e.valid, requestEIO[0][0]) @[Xbar.scala 150:42] + _T_5115[0].valid <= _T_5168 @[Xbar.scala 150:27] + _T_5115[1].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_5169 = and(in[0].e.valid, requestEIO[0][1]) @[Xbar.scala 150:42] + _T_5115[1].valid <= _T_5169 @[Xbar.scala 150:27] + node _T_5171 = mux(requestEIO[0][0], _T_5115[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5173 = mux(requestEIO[0][1], _T_5115[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5175 = or(_T_5171, _T_5173) @[Mux.scala 19:72] + wire _T_5177 : UInt<1> @[Mux.scala 19:72] + _T_5177 is invalid @[Mux.scala 19:72] + _T_5177 <= _T_5175 @[Mux.scala 19:72] + in[0].e.ready <= _T_5177 @[Xbar.scala 152:19] + reg _T_5179 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5181 = eq(_T_5179, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5182 = and(_T_5181, out[0].a.ready) @[Arbiter.scala 35:24] + node _T_5185 = eq(_T_4225[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5186 = and(UInt<1>("h01"), _T_5185) @[Arbiter.scala 14:35] + wire _T_5189 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_5189 is invalid @[Arbiter.scala 40:23] + _T_5189[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_5193 = and(_T_5189[0], _T_4225[0].valid) @[Arbiter.scala 42:65] + wire _T_5196 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_5196 is invalid @[Arbiter.scala 42:23] + _T_5196[0] <= _T_5193 @[Arbiter.scala 42:23] + node _T_5201 = or(UInt<1>("h00"), _T_5196[0]) @[Arbiter.scala 47:52] + node _T_5203 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5205 = eq(_T_5196[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5206 = or(_T_5203, _T_5205) @[Arbiter.scala 48:59] + node _T_5207 = or(_T_5206, reset) @[Arbiter.scala 48:13] + node _T_5209 = eq(_T_5207, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5209 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5211 = eq(_T_4225[0].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5212 = or(_T_5211, _T_5196[0]) @[Arbiter.scala 50:36] + node _T_5213 = or(_T_5212, reset) @[Arbiter.scala 50:14] + node _T_5215 = eq(_T_5213, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5215 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5217 = mux(_T_5196[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5218 = and(out[0].a.ready, out[0].a.valid) @[Decoupled.scala 30:37] + node _T_5219 = sub(_T_5179, _T_5218) @[Arbiter.scala 55:52] + node _T_5220 = asUInt(_T_5219) @[Arbiter.scala 55:52] + node _T_5221 = tail(_T_5220, 1) @[Arbiter.scala 55:52] + node _T_5222 = mux(_T_5182, _T_5217, _T_5221) @[Arbiter.scala 55:23] + _T_5179 <= _T_5222 @[Arbiter.scala 55:17] + wire _T_5226 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_5226 is invalid @[Arbiter.scala 58:49] + _T_5226[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5230 : UInt<1>[1], clock with : (reset => (reset, _T_5226)) @[Reg.scala 26:44] + node _T_5236 = mux(_T_5181, _T_5196, _T_5230) @[Arbiter.scala 59:25] + _T_5230 <- _T_5236 @[Arbiter.scala 60:13] + _T_4225[0].ready <= out[0].a.ready @[Arbiter.scala 68:28] + node _T_5242 = mux(_T_5181, _T_4225[0].valid, _T_4225[0].valid) @[Arbiter.scala 71:24] + out[0].a.valid <= _T_5242 @[Arbiter.scala 71:18] + out[0].a.bits <- _T_4225[0].bits @[Arbiter.scala 72:17] + out[0].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[0].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_5246 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5248 = eq(_T_5246, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5249 = and(_T_5248, out[1].a.ready) @[Arbiter.scala 35:24] + node _T_5252 = eq(_T_4225[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5253 = and(UInt<1>("h01"), _T_5252) @[Arbiter.scala 14:35] + wire _T_5256 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_5256 is invalid @[Arbiter.scala 40:23] + _T_5256[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_5260 = and(_T_5256[0], _T_4225[1].valid) @[Arbiter.scala 42:65] + wire _T_5263 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_5263 is invalid @[Arbiter.scala 42:23] + _T_5263[0] <= _T_5260 @[Arbiter.scala 42:23] + node _T_5268 = or(UInt<1>("h00"), _T_5263[0]) @[Arbiter.scala 47:52] + node _T_5270 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5272 = eq(_T_5263[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5273 = or(_T_5270, _T_5272) @[Arbiter.scala 48:59] + node _T_5274 = or(_T_5273, reset) @[Arbiter.scala 48:13] + node _T_5276 = eq(_T_5274, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5276 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5278 = eq(_T_4225[1].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5279 = or(_T_5278, _T_5263[0]) @[Arbiter.scala 50:36] + node _T_5280 = or(_T_5279, reset) @[Arbiter.scala 50:14] + node _T_5282 = eq(_T_5280, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5282 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5284 = mux(_T_5263[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5285 = and(out[1].a.ready, out[1].a.valid) @[Decoupled.scala 30:37] + node _T_5286 = sub(_T_5246, _T_5285) @[Arbiter.scala 55:52] + node _T_5287 = asUInt(_T_5286) @[Arbiter.scala 55:52] + node _T_5288 = tail(_T_5287, 1) @[Arbiter.scala 55:52] + node _T_5289 = mux(_T_5249, _T_5284, _T_5288) @[Arbiter.scala 55:23] + _T_5246 <= _T_5289 @[Arbiter.scala 55:17] + wire _T_5293 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_5293 is invalid @[Arbiter.scala 58:49] + _T_5293[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5297 : UInt<1>[1], clock with : (reset => (reset, _T_5293)) @[Reg.scala 26:44] + node _T_5303 = mux(_T_5248, _T_5263, _T_5297) @[Arbiter.scala 59:25] + _T_5297 <- _T_5303 @[Arbiter.scala 60:13] + _T_4225[1].ready <= out[1].a.ready @[Arbiter.scala 68:28] + node _T_5309 = mux(_T_5248, _T_4225[1].valid, _T_4225[1].valid) @[Arbiter.scala 71:24] + out[1].a.valid <= _T_5309 @[Arbiter.scala 71:18] + out[1].a.bits <- _T_4225[1].bits @[Arbiter.scala 72:17] + out[1].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[1].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + in[0].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_5314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5316 = eq(_T_5314, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5317 = and(_T_5316, in[0].d.ready) @[Arbiter.scala 35:24] + node _T_5320 = eq(_T_4857[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5321 = and(UInt<1>("h01"), _T_5320) @[Arbiter.scala 14:35] + node _T_5323 = eq(_T_4996[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5324 = and(_T_5321, _T_5323) @[Arbiter.scala 14:35] + wire _T_5327 : UInt<1>[2] @[Arbiter.scala 40:23] + _T_5327 is invalid @[Arbiter.scala 40:23] + _T_5327[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_5327[1] <= _T_5321 @[Arbiter.scala 40:23] + node _T_5332 = and(_T_5327[0], _T_4857[0].valid) @[Arbiter.scala 42:65] + node _T_5333 = and(_T_5327[1], _T_4996[0].valid) @[Arbiter.scala 42:65] + wire _T_5336 : UInt<1>[2] @[Arbiter.scala 42:23] + _T_5336 is invalid @[Arbiter.scala 42:23] + _T_5336[0] <= _T_5332 @[Arbiter.scala 42:23] + _T_5336[1] <= _T_5333 @[Arbiter.scala 42:23] + node _T_5342 = or(UInt<1>("h00"), _T_5336[0]) @[Arbiter.scala 47:52] + node _T_5343 = or(_T_5342, _T_5336[1]) @[Arbiter.scala 47:52] + node _T_5345 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5347 = eq(_T_5336[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5348 = or(_T_5345, _T_5347) @[Arbiter.scala 48:59] + node _T_5350 = eq(_T_5342, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5352 = eq(_T_5336[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5353 = or(_T_5350, _T_5352) @[Arbiter.scala 48:59] + node _T_5354 = and(_T_5348, _T_5353) @[Arbiter.scala 48:77] + node _T_5355 = or(_T_5354, reset) @[Arbiter.scala 48:13] + node _T_5357 = eq(_T_5355, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5357 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5358 = or(_T_4857[0].valid, _T_4996[0].valid) @[Arbiter.scala 50:31] + node _T_5360 = eq(_T_5358, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5361 = or(_T_5336[0], _T_5336[1]) @[Arbiter.scala 50:54] + node _T_5362 = or(_T_5360, _T_5361) @[Arbiter.scala 50:36] + node _T_5363 = or(_T_5362, reset) @[Arbiter.scala 50:14] + node _T_5365 = eq(_T_5363, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5365 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5367 = mux(_T_5336[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5369 = mux(_T_5336[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5370 = or(_T_5367, _T_5369) @[Arbiter.scala 54:44] + node _T_5371 = and(in[0].d.ready, in[0].d.valid) @[Decoupled.scala 30:37] + node _T_5372 = sub(_T_5314, _T_5371) @[Arbiter.scala 55:52] + node _T_5373 = asUInt(_T_5372) @[Arbiter.scala 55:52] + node _T_5374 = tail(_T_5373, 1) @[Arbiter.scala 55:52] + node _T_5375 = mux(_T_5317, _T_5370, _T_5374) @[Arbiter.scala 55:23] + _T_5314 <= _T_5375 @[Arbiter.scala 55:17] + wire _T_5380 : UInt<1>[2] @[Arbiter.scala 58:49] + _T_5380 is invalid @[Arbiter.scala 58:49] + _T_5380[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_5380[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5385 : UInt<1>[2], clock with : (reset => (reset, _T_5380)) @[Reg.scala 26:44] + node _T_5393 = mux(_T_5316, _T_5336, _T_5385) @[Arbiter.scala 59:25] + _T_5385 <- _T_5393 @[Arbiter.scala 60:13] + node _T_5401 = mux(_T_5316, _T_5327, _T_5385) @[Arbiter.scala 63:26] + node _T_5409 = and(in[0].d.ready, _T_5401[0]) @[Arbiter.scala 65:33] + _T_4857[0].ready <= _T_5409 @[Arbiter.scala 65:19] + node _T_5410 = and(in[0].d.ready, _T_5401[1]) @[Arbiter.scala 65:33] + _T_4996[0].ready <= _T_5410 @[Arbiter.scala 65:19] + node _T_5411 = or(_T_4857[0].valid, _T_4996[0].valid) @[Arbiter.scala 71:46] + node _T_5413 = mux(_T_5385[0], _T_4857[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5415 = mux(_T_5385[1], _T_4996[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5417 = or(_T_5413, _T_5415) @[Mux.scala 19:72] + wire _T_5419 : UInt<1> @[Mux.scala 19:72] + _T_5419 is invalid @[Mux.scala 19:72] + _T_5419 <= _T_5417 @[Mux.scala 19:72] + node _T_5420 = mux(_T_5316, _T_5411, _T_5419) @[Arbiter.scala 71:24] + in[0].d.valid <= _T_5420 @[Arbiter.scala 71:18] + node _T_5421 = cat(_T_4857[0].bits.data, _T_4857[0].bits.error) @[Mux.scala 19:72] + node _T_5422 = cat(_T_4857[0].bits.sink, _T_4857[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_5423 = cat(_T_5422, _T_5421) @[Mux.scala 19:72] + node _T_5424 = cat(_T_4857[0].bits.size, _T_4857[0].bits.source) @[Mux.scala 19:72] + node _T_5425 = cat(_T_4857[0].bits.opcode, _T_4857[0].bits.param) @[Mux.scala 19:72] + node _T_5426 = cat(_T_5425, _T_5424) @[Mux.scala 19:72] + node _T_5427 = cat(_T_5426, _T_5423) @[Mux.scala 19:72] + node _T_5429 = mux(_T_5393[0], _T_5427, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5430 = cat(_T_4996[0].bits.data, _T_4996[0].bits.error) @[Mux.scala 19:72] + node _T_5431 = cat(_T_4996[0].bits.sink, _T_4996[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_5432 = cat(_T_5431, _T_5430) @[Mux.scala 19:72] + node _T_5433 = cat(_T_4996[0].bits.size, _T_4996[0].bits.source) @[Mux.scala 19:72] + node _T_5434 = cat(_T_4996[0].bits.opcode, _T_4996[0].bits.param) @[Mux.scala 19:72] + node _T_5435 = cat(_T_5434, _T_5433) @[Mux.scala 19:72] + node _T_5436 = cat(_T_5435, _T_5432) @[Mux.scala 19:72] + node _T_5438 = mux(_T_5393[1], _T_5436, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5448 = or(_T_5429, _T_5438) @[Mux.scala 19:72] + wire _T_5458 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_5458 is invalid @[Mux.scala 19:72] + wire _T_5468 : UInt<81> + _T_5468 is invalid + _T_5468 <= _T_5448 + node _T_5469 = bits(_T_5468, 0, 0) @[Mux.scala 19:72] + _T_5458.error <= _T_5469 @[Mux.scala 19:72] + node _T_5470 = bits(_T_5468, 64, 1) @[Mux.scala 19:72] + _T_5458.data <= _T_5470 @[Mux.scala 19:72] + node _T_5471 = bits(_T_5468, 67, 65) @[Mux.scala 19:72] + _T_5458.addr_lo <= _T_5471 @[Mux.scala 19:72] + node _T_5472 = bits(_T_5468, 68, 68) @[Mux.scala 19:72] + _T_5458.sink <= _T_5472 @[Mux.scala 19:72] + node _T_5473 = bits(_T_5468, 71, 69) @[Mux.scala 19:72] + _T_5458.source <= _T_5473 @[Mux.scala 19:72] + node _T_5474 = bits(_T_5468, 75, 72) @[Mux.scala 19:72] + _T_5458.size <= _T_5474 @[Mux.scala 19:72] + node _T_5475 = bits(_T_5468, 77, 76) @[Mux.scala 19:72] + _T_5458.param <= _T_5475 @[Mux.scala 19:72] + node _T_5476 = bits(_T_5468, 80, 78) @[Mux.scala 19:72] + _T_5458.opcode <= _T_5476 @[Mux.scala 19:72] + in[0].d.bits <- _T_5458 @[Arbiter.scala 72:17] + + module TLXbar_peripheryBus : + input clock : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} io is invalid - io.out.acquire <- io.in.acquire - io.in.grant <- io.out.grant - io.out.probe.ready <= UInt<1>("h01") - io.out.release.valid <= UInt<1>("h00") + io is invalid + wire in : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1] @[Xbar.scala 103:18] + in is invalid @[Xbar.scala 103:18] + in[0] <- io.in.0 @[Xbar.scala 106:13] + node _T_1753 = or(io.in.0.a.bits.source, UInt<1>("h00")) @[Xbar.scala 108:53] + in[0].a.bits.source <= _T_1753 @[Xbar.scala 108:27] + node _T_1755 = or(io.in.0.c.bits.source, UInt<1>("h00")) @[Xbar.scala 109:53] + in[0].c.bits.source <= _T_1755 @[Xbar.scala 109:27] + node _T_1756 = bits(in[0].b.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.b.bits.source <= _T_1756 @[Xbar.scala 111:30] + node _T_1757 = bits(in[0].d.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.d.bits.source <= _T_1757 @[Xbar.scala 112:30] + wire out : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1] @[Xbar.scala 116:19] + out is invalid @[Xbar.scala 116:19] + io.out.0 <- out[0] @[Xbar.scala 119:17] + node _T_2983 = or(io.out.0.d.bits.sink, UInt<1>("h00")) @[Xbar.scala 121:51] + out[0].d.bits.sink <= _T_2983 @[Xbar.scala 121:26] + io.out.0.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + node _T_2986 = xor(in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2987 = cvt(_T_2986) @[Parameters.scala 117:49] + node _T_2989 = and(_T_2987, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_2990 = asSInt(_T_2989) @[Parameters.scala 117:52] + node _T_2992 = eq(_T_2990, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_2995 : UInt<1>[1] @[Xbar.scala 129:49] + _T_2995 is invalid @[Xbar.scala 129:49] + _T_2995[0] <= _T_2992 @[Xbar.scala 129:49] + wire requestAIO : UInt<1>[1][1] @[Xbar.scala 129:25] + requestAIO is invalid @[Xbar.scala 129:25] + requestAIO[0] <- _T_2995 @[Xbar.scala 129:25] + node _T_3039 = xor(in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3040 = cvt(_T_3039) @[Parameters.scala 117:49] + node _T_3042 = and(_T_3040, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_3043 = asSInt(_T_3042) @[Parameters.scala 117:52] + node _T_3045 = eq(_T_3043, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3048 : UInt<1>[1] @[Xbar.scala 130:49] + _T_3048 is invalid @[Xbar.scala 130:49] + _T_3048[0] <= _T_3045 @[Xbar.scala 130:49] + wire requestCIO : UInt<1>[1][1] @[Xbar.scala 130:25] + requestCIO is invalid @[Xbar.scala 130:25] + requestCIO[0] <- _T_3048 @[Xbar.scala 130:25] + node _T_3092 = xor(UInt<1>("h00"), out[0].b.bits.source) @[Parameters.scala 37:23] + node _T_3093 = not(_T_3092) @[Parameters.scala 37:9] + node _T_3095 = or(_T_3093, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3096 = not(_T_3095) @[Parameters.scala 37:7] + node _T_3098 = eq(_T_3096, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3101 : UInt<1>[1] @[Xbar.scala 131:44] + _T_3101 is invalid @[Xbar.scala 131:44] + _T_3101[0] <= _T_3098 @[Xbar.scala 131:44] + wire requestBOI : UInt<1>[1][1] @[Xbar.scala 131:25] + requestBOI is invalid @[Xbar.scala 131:25] + requestBOI[0] <- _T_3101 @[Xbar.scala 131:25] + node _T_3145 = xor(UInt<1>("h00"), out[0].d.bits.source) @[Parameters.scala 37:23] + node _T_3146 = not(_T_3145) @[Parameters.scala 37:9] + node _T_3148 = or(_T_3146, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_3149 = not(_T_3148) @[Parameters.scala 37:7] + node _T_3151 = eq(_T_3149, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3154 : UInt<1>[1] @[Xbar.scala 132:44] + _T_3154 is invalid @[Xbar.scala 132:44] + _T_3154[0] <= _T_3151 @[Xbar.scala 132:44] + wire requestDOI : UInt<1>[1][1] @[Xbar.scala 132:25] + requestDOI is invalid @[Xbar.scala 132:25] + requestDOI[0] <- _T_3154 @[Xbar.scala 132:25] + node _T_3198 = eq(UInt<1>("h00"), in[0].e.bits.sink) @[Parameters.scala 35:39] + wire _T_3201 : UInt<1>[1] @[Xbar.scala 133:44] + _T_3201 is invalid @[Xbar.scala 133:44] + _T_3201[0] <= _T_3198 @[Xbar.scala 133:44] + wire requestEIO : UInt<1>[1][1] @[Xbar.scala 133:25] + requestEIO is invalid @[Xbar.scala 133:25] + requestEIO[0] <- _T_3201 @[Xbar.scala 133:25] + node _T_3245 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_3246 = dshl(_T_3245, in[0].a.bits.size) @[package.scala 19:71] + node _T_3247 = bits(_T_3246, 5, 0) @[package.scala 19:76] + node _T_3248 = not(_T_3247) @[package.scala 19:40] + node _T_3249 = shr(_T_3248, 2) @[Edges.scala 198:59] + node _T_3250 = bits(in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_3252 = eq(_T_3250, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_3255 = mux(UInt<1>("h00"), _T_3249, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsAI : UInt<4>[1] @[Xbar.scala 135:22] + beatsAI is invalid @[Xbar.scala 135:22] + beatsAI[0] <= _T_3255 @[Xbar.scala 135:22] + node _T_3262 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_3263 = dshl(_T_3262, out[0].b.bits.size) @[package.scala 19:71] + node _T_3264 = bits(_T_3263, 5, 0) @[package.scala 19:76] + node _T_3265 = not(_T_3264) @[package.scala 19:40] + node _T_3266 = shr(_T_3265, 2) @[Edges.scala 198:59] + node _T_3267 = bits(out[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_3269 = eq(_T_3267, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_3272 = mux(UInt<1>("h00"), _T_3266, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsBO : UInt<4>[1] @[Xbar.scala 136:22] + beatsBO is invalid @[Xbar.scala 136:22] + beatsBO[0] <= _T_3272 @[Xbar.scala 136:22] + node _T_3279 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_3280 = dshl(_T_3279, in[0].c.bits.size) @[package.scala 19:71] + node _T_3281 = bits(_T_3280, 5, 0) @[package.scala 19:76] + node _T_3282 = not(_T_3281) @[package.scala 19:40] + node _T_3283 = shr(_T_3282, 2) @[Edges.scala 198:59] + node _T_3284 = bits(in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_3286 = mux(_T_3284, _T_3283, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsCI : UInt<4>[1] @[Xbar.scala 137:22] + beatsCI is invalid @[Xbar.scala 137:22] + beatsCI[0] <= _T_3286 @[Xbar.scala 137:22] + node _T_3293 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_3294 = dshl(_T_3293, out[0].d.bits.size) @[package.scala 19:71] + node _T_3295 = bits(_T_3294, 5, 0) @[package.scala 19:76] + node _T_3296 = not(_T_3295) @[package.scala 19:40] + node _T_3297 = shr(_T_3296, 2) @[Edges.scala 198:59] + node _T_3298 = bits(out[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_3301 = mux(UInt<1>("h01"), _T_3297, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsDO : UInt<4>[1] @[Xbar.scala 138:22] + beatsDO is invalid @[Xbar.scala 138:22] + beatsDO[0] <= _T_3301 @[Xbar.scala 138:22] + wire beatsEI : UInt<1>[1] @[Xbar.scala 139:22] + beatsEI is invalid @[Xbar.scala 139:22] + beatsEI[0] <= UInt<1>("h00") @[Xbar.scala 139:22] + wire _T_3355 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}[1] @[Xbar.scala 147:26] + _T_3355 is invalid @[Xbar.scala 147:26] + _T_3355[0].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_3439 = and(in[0].a.valid, requestAIO[0][0]) @[Xbar.scala 150:42] + _T_3355[0].valid <= _T_3439 @[Xbar.scala 150:27] + in[0].a.ready <= _T_3355[0].ready @[Xbar.scala 152:19] + wire _T_3482 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}[1] @[Xbar.scala 147:26] + _T_3482 is invalid @[Xbar.scala 147:26] + _T_3482[0].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_3566 = and(out[0].b.valid, requestBOI[0][0]) @[Xbar.scala 150:42] + _T_3482[0].valid <= _T_3566 @[Xbar.scala 150:27] + out[0].b.ready <= _T_3482[0].ready @[Xbar.scala 152:19] + wire _T_3609 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_3609 is invalid @[Xbar.scala 147:26] + _T_3609[0].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_3693 = and(in[0].c.valid, requestCIO[0][0]) @[Xbar.scala 150:42] + _T_3609[0].valid <= _T_3693 @[Xbar.scala 150:27] + in[0].c.ready <= _T_3609[0].ready @[Xbar.scala 152:19] + wire _T_3740 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_3740 is invalid @[Xbar.scala 147:26] + _T_3740[0].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_3832 = and(out[0].d.valid, requestDOI[0][0]) @[Xbar.scala 150:42] + _T_3740[0].valid <= _T_3832 @[Xbar.scala 150:27] + out[0].d.ready <= _T_3740[0].ready @[Xbar.scala 152:19] + wire _T_3851 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_3851 is invalid @[Xbar.scala 147:26] + _T_3851[0].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_3887 = and(in[0].e.valid, requestEIO[0][0]) @[Xbar.scala 150:42] + _T_3851[0].valid <= _T_3887 @[Xbar.scala 150:27] + in[0].e.ready <= _T_3851[0].ready @[Xbar.scala 152:19] + reg _T_3889 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_3891 = eq(_T_3889, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_3892 = and(_T_3891, out[0].a.ready) @[Arbiter.scala 35:24] + node _T_3895 = eq(_T_3355[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_3896 = and(UInt<1>("h01"), _T_3895) @[Arbiter.scala 14:35] + wire _T_3899 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_3899 is invalid @[Arbiter.scala 40:23] + _T_3899[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_3903 = and(_T_3899[0], _T_3355[0].valid) @[Arbiter.scala 42:65] + wire _T_3906 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_3906 is invalid @[Arbiter.scala 42:23] + _T_3906[0] <= _T_3903 @[Arbiter.scala 42:23] + node _T_3911 = or(UInt<1>("h00"), _T_3906[0]) @[Arbiter.scala 47:52] + node _T_3913 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_3915 = eq(_T_3906[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_3916 = or(_T_3913, _T_3915) @[Arbiter.scala 48:59] + node _T_3917 = or(_T_3916, reset) @[Arbiter.scala 48:13] + node _T_3919 = eq(_T_3917, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_3919 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_3921 = eq(_T_3355[0].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_3922 = or(_T_3921, _T_3906[0]) @[Arbiter.scala 50:36] + node _T_3923 = or(_T_3922, reset) @[Arbiter.scala 50:14] + node _T_3925 = eq(_T_3923, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_3925 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_3927 = mux(_T_3906[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_3928 = and(out[0].a.ready, out[0].a.valid) @[Decoupled.scala 30:37] + node _T_3929 = sub(_T_3889, _T_3928) @[Arbiter.scala 55:52] + node _T_3930 = asUInt(_T_3929) @[Arbiter.scala 55:52] + node _T_3931 = tail(_T_3930, 1) @[Arbiter.scala 55:52] + node _T_3932 = mux(_T_3892, _T_3927, _T_3931) @[Arbiter.scala 55:23] + _T_3889 <= _T_3932 @[Arbiter.scala 55:17] + wire _T_3936 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_3936 is invalid @[Arbiter.scala 58:49] + _T_3936[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_3940 : UInt<1>[1], clock with : (reset => (reset, _T_3936)) @[Reg.scala 26:44] + node _T_3946 = mux(_T_3891, _T_3906, _T_3940) @[Arbiter.scala 59:25] + _T_3940 <- _T_3946 @[Arbiter.scala 60:13] + _T_3355[0].ready <= out[0].a.ready @[Arbiter.scala 68:28] + node _T_3952 = mux(_T_3891, _T_3355[0].valid, _T_3355[0].valid) @[Arbiter.scala 71:24] + out[0].a.valid <= _T_3952 @[Arbiter.scala 71:18] + out[0].a.bits <- _T_3355[0].bits @[Arbiter.scala 72:17] + out[0].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[0].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + in[0].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_3957 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_3959 = eq(_T_3957, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_3960 = and(_T_3959, in[0].d.ready) @[Arbiter.scala 35:24] + node _T_3963 = eq(_T_3740[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_3964 = and(UInt<1>("h01"), _T_3963) @[Arbiter.scala 14:35] + wire _T_3967 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_3967 is invalid @[Arbiter.scala 40:23] + _T_3967[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_3971 = and(_T_3967[0], _T_3740[0].valid) @[Arbiter.scala 42:65] + wire _T_3974 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_3974 is invalid @[Arbiter.scala 42:23] + _T_3974[0] <= _T_3971 @[Arbiter.scala 42:23] + node _T_3979 = or(UInt<1>("h00"), _T_3974[0]) @[Arbiter.scala 47:52] + node _T_3981 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_3983 = eq(_T_3974[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_3984 = or(_T_3981, _T_3983) @[Arbiter.scala 48:59] + node _T_3985 = or(_T_3984, reset) @[Arbiter.scala 48:13] + node _T_3987 = eq(_T_3985, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_3987 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_3989 = eq(_T_3740[0].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_3990 = or(_T_3989, _T_3974[0]) @[Arbiter.scala 50:36] + node _T_3991 = or(_T_3990, reset) @[Arbiter.scala 50:14] + node _T_3993 = eq(_T_3991, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_3993 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_3995 = mux(_T_3974[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_3996 = and(in[0].d.ready, in[0].d.valid) @[Decoupled.scala 30:37] + node _T_3997 = sub(_T_3957, _T_3996) @[Arbiter.scala 55:52] + node _T_3998 = asUInt(_T_3997) @[Arbiter.scala 55:52] + node _T_3999 = tail(_T_3998, 1) @[Arbiter.scala 55:52] + node _T_4000 = mux(_T_3960, _T_3995, _T_3999) @[Arbiter.scala 55:23] + _T_3957 <= _T_4000 @[Arbiter.scala 55:17] + wire _T_4004 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_4004 is invalid @[Arbiter.scala 58:49] + _T_4004[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_4008 : UInt<1>[1], clock with : (reset => (reset, _T_4004)) @[Reg.scala 26:44] + node _T_4014 = mux(_T_3959, _T_3974, _T_4008) @[Arbiter.scala 59:25] + _T_4008 <- _T_4014 @[Arbiter.scala 60:13] + _T_3740[0].ready <= in[0].d.ready @[Arbiter.scala 68:28] + node _T_4020 = mux(_T_3959, _T_3740[0].valid, _T_3740[0].valid) @[Arbiter.scala 71:24] + in[0].d.valid <= _T_4020 @[Arbiter.scala 71:18] + in[0].d.bits <- _T_3740[0].bits @[Arbiter.scala 72:17] - module FinishQueue : - input clk : Clock + module IntXbar_intBus : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>} - - io is invalid - cmem T_877 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2] - reg T_879 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_881 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_883 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_884 = eq(T_879, T_881) - node T_886 = eq(T_883, UInt<1>("h00")) - node T_887 = and(T_884, T_886) - node T_888 = and(T_884, T_883) - node T_890 = and(UInt<1>("h00"), T_887) - node T_891 = and(T_890, io.deq.ready) - node T_892 = and(io.enq.ready, io.enq.valid) - node T_894 = eq(T_891, UInt<1>("h00")) - node T_895 = and(T_892, T_894) - node T_896 = and(io.deq.ready, io.deq.valid) - node T_898 = eq(T_891, UInt<1>("h00")) - node T_899 = and(T_896, T_898) - when T_895 : - infer mport T_900 = T_877[T_879], clk - T_900 <- io.enq.bits - node T_997 = eq(T_879, UInt<1>("h01")) - node T_999 = and(UInt<1>("h00"), T_997) - node T_1002 = add(T_879, UInt<1>("h01")) - node T_1003 = tail(T_1002, 1) - node T_1004 = mux(T_999, UInt<1>("h00"), T_1003) - T_879 <= T_1004 - skip - when T_899 : - node T_1006 = eq(T_881, UInt<1>("h01")) - node T_1008 = and(UInt<1>("h00"), T_1006) - node T_1011 = add(T_881, UInt<1>("h01")) - node T_1012 = tail(T_1011, 1) - node T_1013 = mux(T_1008, UInt<1>("h00"), T_1012) - T_881 <= T_1013 - skip - node T_1014 = neq(T_895, T_899) - when T_1014 : - T_883 <= T_895 - skip - node T_1016 = eq(T_887, UInt<1>("h00")) - node T_1018 = and(UInt<1>("h00"), io.enq.valid) - node T_1019 = or(T_1016, T_1018) - io.deq.valid <= T_1019 - node T_1021 = eq(T_888, UInt<1>("h00")) - node T_1023 = and(UInt<1>("h00"), io.deq.ready) - node T_1024 = or(T_1021, T_1023) - io.enq.ready <= T_1024 - infer mport T_1025 = T_877[T_881], clk - node T_1121 = mux(T_890, io.enq.bits, T_1025) - io.deq.bits <- T_1121 - node T_1217 = sub(T_879, T_881) - node T_1218 = tail(T_1217, 1) - node T_1219 = and(T_883, T_884) - node T_1220 = cat(T_1219, T_1218) - io.count <= T_1220 - - module FinishUnit : - input clk : Clock + output io : {flip in : {0 : UInt<1>[2]}, out : {0 : UInt<1>[2]}} + + io is invalid + io is invalid + io.out.0[0] <= io.in.0[0] @[IntNodes.scala 126:24] + io.out.0[1] <= io.in.0[1] @[IntNodes.scala 126:24] + + module Queue : + input clock : Clock input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h05") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h00"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h00") - T_1190[1] <= UInt<1>("h01") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h00"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h01"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h03")) - node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h01")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h00")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h05") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h00"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h00") - T_1334[1] <= UInt<1>("h01") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h00"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h01"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h00")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : {manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<1>("h00") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h00")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h00")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h00")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h00")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - - module ClientTileLinkNetworkPort : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_1 : + input clock : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - - io is invalid - inst finisher of FinishUnit - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<1>("h00") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<1>("h00") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, count : UInt<2>} - module Queue : - input clk : Clock + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_85 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_87 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_88 = and(_T_85, _T_87) @[Decoupled.scala 188:33] + node _T_89 = and(_T_85, maybe_full) @[Decoupled.scala 189:32] + node _T_90 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_90 + node _T_91 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_91 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_92 = ram[value], clock + _T_92 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_103 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_104 = tail(_T_103, 1) @[Counter.scala 26:22] + value <= _T_104 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_107 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_108 = tail(_T_107, 1) @[Counter.scala 26:22] + value_1 <= _T_108 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_109 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_109 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_111 = eq(_T_88, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_111 @[Decoupled.scala 204:16] + node _T_113 = eq(_T_89, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_113 @[Decoupled.scala 205:16] + infer mport _T_114 = ram[value_1], clock + io.deq.bits <- _T_114 @[Decoupled.scala 206:15] + node _T_123 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_124 = asUInt(_T_123) @[Decoupled.scala 221:40] + node _T_125 = tail(_T_124, 1) @[Decoupled.scala 221:40] + node _T_126 = and(maybe_full, _T_85) @[Decoupled.scala 223:32] + node _T_127 = cat(_T_126, _T_125) @[Cat.scala 30:58] + io.count <= _T_127 @[Decoupled.scala 223:14] + + module TLBuffer_l2FrontendBus : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, count : UInt<2>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2] - reg T_1160 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1162 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1160, T_1162) - node T_1167 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1167) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1173 = and(io.enq.ready, io.enq.valid) - node T_1175 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1173, T_1175) - node T_1177 = and(io.deq.ready, io.deq.valid) - node T_1179 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1177, T_1179) - when do_enq : - infer mport T_1181 = ram[T_1160], clk - T_1181 <- io.enq.bits - node T_1309 = eq(T_1160, UInt<1>("h01")) - node T_1311 = and(UInt<1>("h00"), T_1309) - node T_1314 = add(T_1160, UInt<1>("h01")) - node T_1315 = tail(T_1314, 1) - node T_1316 = mux(T_1311, UInt<1>("h00"), T_1315) - T_1160 <= T_1316 - skip - when do_deq : - node T_1318 = eq(T_1162, UInt<1>("h01")) - node T_1320 = and(UInt<1>("h00"), T_1318) - node T_1323 = add(T_1162, UInt<1>("h01")) - node T_1324 = tail(T_1323, 1) - node T_1325 = mux(T_1320, UInt<1>("h00"), T_1324) - T_1162 <= T_1325 - skip - node T_1326 = neq(do_enq, do_deq) - when T_1326 : - maybe_full <= do_enq - skip - node T_1328 = eq(empty, UInt<1>("h00")) - node T_1330 = and(UInt<1>("h00"), io.enq.valid) - node T_1331 = or(T_1328, T_1330) - io.deq.valid <= T_1331 - node T_1333 = eq(full, UInt<1>("h00")) - node T_1335 = and(UInt<1>("h00"), io.deq.ready) - node T_1336 = or(T_1333, T_1335) - io.enq.ready <= T_1336 - infer mport T_1337 = ram[T_1162], clk - node T_1464 = mux(maybe_flow, io.enq.bits, T_1337) - io.deq.bits <- T_1464 - node T_1591 = sub(T_1160, T_1162) - node ptr_diff = tail(T_1591, 1) - node T_1593 = and(maybe_full, ptr_match) - node T_1594 = cat(T_1593, ptr_diff) - io.count <= T_1594 + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + inst Queue of Queue @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.a.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.a.bits @[Decoupled.scala 255:19] + io.in.0.a.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.a <- Queue.io.deq @[Buffer.scala 58:13] + inst Queue_1 of Queue_1 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.out.0.d.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.out.0.d.bits @[Decoupled.scala 255:19] + io.out.0.d.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.d <- Queue_1.io.deq @[Buffer.scala 59:13] + io.in.0.b.valid <= UInt<1>("h00") @[Buffer.scala 66:20] + io.in.0.c.ready <= UInt<1>("h01") @[Buffer.scala 67:20] + io.in.0.e.ready <= UInt<1>("h01") @[Buffer.scala 68:20] + io.out.0.b.ready <= UInt<1>("h01") @[Buffer.scala 69:21] + io.out.0.c.valid <= UInt<1>("h00") @[Buffer.scala 70:21] + io.out.0.e.valid <= UInt<1>("h00") @[Buffer.scala 71:21] + + module TLXbar_mem_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + wire in : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1] @[Xbar.scala 103:18] + in is invalid @[Xbar.scala 103:18] + in[0] <- io.in.0 @[Xbar.scala 106:13] + node _T_1928 = or(io.in.0.a.bits.source, UInt<1>("h00")) @[Xbar.scala 108:53] + in[0].a.bits.source <= _T_1928 @[Xbar.scala 108:27] + node _T_1930 = or(io.in.0.c.bits.source, UInt<1>("h00")) @[Xbar.scala 109:53] + in[0].c.bits.source <= _T_1930 @[Xbar.scala 109:27] + node _T_1931 = bits(in[0].b.bits.source, 4, 0) @[Xbar.scala 100:67] + io.in.0.b.bits.source <= _T_1931 @[Xbar.scala 111:30] + node _T_1932 = bits(in[0].d.bits.source, 4, 0) @[Xbar.scala 100:67] + io.in.0.d.bits.source <= _T_1932 @[Xbar.scala 112:30] + wire out : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[2] @[Xbar.scala 116:19] + out is invalid @[Xbar.scala 116:19] + io.out.0 <- out[0] @[Xbar.scala 119:17] + node _T_3681 = or(io.out.0.d.bits.sink, UInt<1>("h01")) @[Xbar.scala 121:51] + out[0].d.bits.sink <= _T_3681 @[Xbar.scala 121:26] + io.out.0.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + io.out.1 <- out[1] @[Xbar.scala 119:17] + node _T_3684 = or(io.out.1.d.bits.sink, UInt<1>("h00")) @[Xbar.scala 121:51] + out[1].d.bits.sink <= _T_3684 @[Xbar.scala 121:26] + io.out.1.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + node _T_3687 = xor(in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3688 = cvt(_T_3687) @[Parameters.scala 117:49] + node _T_3690 = and(_T_3688, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_3691 = asSInt(_T_3690) @[Parameters.scala 117:52] + node _T_3693 = eq(_T_3691, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3695 = xor(in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3696 = cvt(_T_3695) @[Parameters.scala 117:49] + node _T_3698 = and(_T_3696, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_3699 = asSInt(_T_3698) @[Parameters.scala 117:52] + node _T_3701 = eq(_T_3699, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3704 : UInt<1>[2] @[Xbar.scala 129:49] + _T_3704 is invalid @[Xbar.scala 129:49] + _T_3704[0] <= _T_3693 @[Xbar.scala 129:49] + _T_3704[1] <= _T_3701 @[Xbar.scala 129:49] + wire requestAIO : UInt<1>[2][1] @[Xbar.scala 129:25] + requestAIO is invalid @[Xbar.scala 129:25] + requestAIO[0] <- _T_3704 @[Xbar.scala 129:25] + node _T_3763 = xor(in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3764 = cvt(_T_3763) @[Parameters.scala 117:49] + node _T_3766 = and(_T_3764, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_3767 = asSInt(_T_3766) @[Parameters.scala 117:52] + node _T_3769 = eq(_T_3767, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3771 = xor(in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3772 = cvt(_T_3771) @[Parameters.scala 117:49] + node _T_3774 = and(_T_3772, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_3775 = asSInt(_T_3774) @[Parameters.scala 117:52] + node _T_3777 = eq(_T_3775, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3780 : UInt<1>[2] @[Xbar.scala 130:49] + _T_3780 is invalid @[Xbar.scala 130:49] + _T_3780[0] <= _T_3769 @[Xbar.scala 130:49] + _T_3780[1] <= _T_3777 @[Xbar.scala 130:49] + wire requestCIO : UInt<1>[2][1] @[Xbar.scala 130:25] + requestCIO is invalid @[Xbar.scala 130:25] + requestCIO[0] <- _T_3780 @[Xbar.scala 130:25] + node _T_3839 = xor(UInt<1>("h00"), out[0].b.bits.source) @[Parameters.scala 37:23] + node _T_3840 = not(_T_3839) @[Parameters.scala 37:9] + node _T_3842 = or(_T_3840, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_3843 = not(_T_3842) @[Parameters.scala 37:7] + node _T_3845 = eq(_T_3843, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3848 : UInt<1>[1] @[Xbar.scala 131:44] + _T_3848 is invalid @[Xbar.scala 131:44] + _T_3848[0] <= _T_3845 @[Xbar.scala 131:44] + node _T_3853 = xor(UInt<1>("h00"), out[1].b.bits.source) @[Parameters.scala 37:23] + node _T_3854 = not(_T_3853) @[Parameters.scala 37:9] + node _T_3856 = or(_T_3854, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_3857 = not(_T_3856) @[Parameters.scala 37:7] + node _T_3859 = eq(_T_3857, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3862 : UInt<1>[1] @[Xbar.scala 131:44] + _T_3862 is invalid @[Xbar.scala 131:44] + _T_3862[0] <= _T_3859 @[Xbar.scala 131:44] + wire requestBOI : UInt<1>[1][2] @[Xbar.scala 131:25] + requestBOI is invalid @[Xbar.scala 131:25] + requestBOI[0] <- _T_3848 @[Xbar.scala 131:25] + requestBOI[1] <- _T_3862 @[Xbar.scala 131:25] + node _T_3924 = xor(UInt<1>("h00"), out[0].d.bits.source) @[Parameters.scala 37:23] + node _T_3925 = not(_T_3924) @[Parameters.scala 37:9] + node _T_3927 = or(_T_3925, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_3928 = not(_T_3927) @[Parameters.scala 37:7] + node _T_3930 = eq(_T_3928, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3933 : UInt<1>[1] @[Xbar.scala 132:44] + _T_3933 is invalid @[Xbar.scala 132:44] + _T_3933[0] <= _T_3930 @[Xbar.scala 132:44] + node _T_3938 = xor(UInt<1>("h00"), out[1].d.bits.source) @[Parameters.scala 37:23] + node _T_3939 = not(_T_3938) @[Parameters.scala 37:9] + node _T_3941 = or(_T_3939, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_3942 = not(_T_3941) @[Parameters.scala 37:7] + node _T_3944 = eq(_T_3942, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_3947 : UInt<1>[1] @[Xbar.scala 132:44] + _T_3947 is invalid @[Xbar.scala 132:44] + _T_3947[0] <= _T_3944 @[Xbar.scala 132:44] + wire requestDOI : UInt<1>[1][2] @[Xbar.scala 132:25] + requestDOI is invalid @[Xbar.scala 132:25] + requestDOI[0] <- _T_3933 @[Xbar.scala 132:25] + requestDOI[1] <- _T_3947 @[Xbar.scala 132:25] + node _T_4009 = eq(UInt<1>("h01"), in[0].e.bits.sink) @[Parameters.scala 35:39] + node _T_4011 = eq(UInt<1>("h00"), in[0].e.bits.sink) @[Parameters.scala 35:39] + wire _T_4014 : UInt<1>[2] @[Xbar.scala 133:44] + _T_4014 is invalid @[Xbar.scala 133:44] + _T_4014[0] <= _T_4009 @[Xbar.scala 133:44] + _T_4014[1] <= _T_4011 @[Xbar.scala 133:44] + wire requestEIO : UInt<1>[2][1] @[Xbar.scala 133:25] + requestEIO is invalid @[Xbar.scala 133:25] + requestEIO[0] <- _T_4014 @[Xbar.scala 133:25] + node _T_4073 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4074 = dshl(_T_4073, in[0].a.bits.size) @[package.scala 19:71] + node _T_4075 = bits(_T_4074, 7, 0) @[package.scala 19:76] + node _T_4076 = not(_T_4075) @[package.scala 19:40] + node _T_4077 = shr(_T_4076, 3) @[Edges.scala 198:59] + node _T_4078 = bits(in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4080 = eq(_T_4078, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4082 = mux(_T_4080, _T_4077, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsAI : UInt<5>[1] @[Xbar.scala 135:22] + beatsAI is invalid @[Xbar.scala 135:22] + beatsAI[0] <= _T_4082 @[Xbar.scala 135:22] + node _T_4089 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4090 = dshl(_T_4089, out[0].b.bits.size) @[package.scala 19:71] + node _T_4091 = bits(_T_4090, 7, 0) @[package.scala 19:76] + node _T_4092 = not(_T_4091) @[package.scala 19:40] + node _T_4093 = shr(_T_4092, 3) @[Edges.scala 198:59] + node _T_4094 = bits(out[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4096 = eq(_T_4094, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4099 = mux(UInt<1>("h00"), _T_4093, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4101 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4102 = dshl(_T_4101, out[1].b.bits.size) @[package.scala 19:71] + node _T_4103 = bits(_T_4102, 5, 0) @[package.scala 19:76] + node _T_4104 = not(_T_4103) @[package.scala 19:40] + node _T_4105 = shr(_T_4104, 3) @[Edges.scala 198:59] + node _T_4106 = bits(out[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4108 = eq(_T_4106, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4111 = mux(UInt<1>("h00"), _T_4105, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsBO : UInt<5>[2] @[Xbar.scala 136:22] + beatsBO is invalid @[Xbar.scala 136:22] + beatsBO[0] <= _T_4099 @[Xbar.scala 136:22] + beatsBO[1] <= _T_4111 @[Xbar.scala 136:22] + node _T_4119 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4120 = dshl(_T_4119, in[0].c.bits.size) @[package.scala 19:71] + node _T_4121 = bits(_T_4120, 7, 0) @[package.scala 19:76] + node _T_4122 = not(_T_4121) @[package.scala 19:40] + node _T_4123 = shr(_T_4122, 3) @[Edges.scala 198:59] + node _T_4124 = bits(in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4127 = mux(UInt<1>("h00"), _T_4123, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsCI : UInt<5>[1] @[Xbar.scala 137:22] + beatsCI is invalid @[Xbar.scala 137:22] + beatsCI[0] <= _T_4127 @[Xbar.scala 137:22] + node _T_4134 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4135 = dshl(_T_4134, out[0].d.bits.size) @[package.scala 19:71] + node _T_4136 = bits(_T_4135, 7, 0) @[package.scala 19:76] + node _T_4137 = not(_T_4136) @[package.scala 19:40] + node _T_4138 = shr(_T_4137, 3) @[Edges.scala 198:59] + node _T_4139 = bits(out[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4141 = mux(_T_4139, _T_4138, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4143 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4144 = dshl(_T_4143, out[1].d.bits.size) @[package.scala 19:71] + node _T_4145 = bits(_T_4144, 5, 0) @[package.scala 19:76] + node _T_4146 = not(_T_4145) @[package.scala 19:40] + node _T_4147 = shr(_T_4146, 3) @[Edges.scala 198:59] + node _T_4148 = bits(out[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4150 = mux(_T_4148, _T_4147, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsDO : UInt<5>[2] @[Xbar.scala 138:22] + beatsDO is invalid @[Xbar.scala 138:22] + beatsDO[0] <= _T_4141 @[Xbar.scala 138:22] + beatsDO[1] <= _T_4150 @[Xbar.scala 138:22] + wire beatsEI : UInt<1>[1] @[Xbar.scala 139:22] + beatsEI is invalid @[Xbar.scala 139:22] + beatsEI[0] <= UInt<1>("h00") @[Xbar.scala 139:22] + wire _T_4225 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[2] @[Xbar.scala 147:26] + _T_4225 is invalid @[Xbar.scala 147:26] + _T_4225[0].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_4350 = and(in[0].a.valid, requestAIO[0][0]) @[Xbar.scala 150:42] + _T_4225[0].valid <= _T_4350 @[Xbar.scala 150:27] + _T_4225[1].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_4351 = and(in[0].a.valid, requestAIO[0][1]) @[Xbar.scala 150:42] + _T_4225[1].valid <= _T_4351 @[Xbar.scala 150:27] + node _T_4353 = mux(requestAIO[0][0], _T_4225[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4355 = mux(requestAIO[0][1], _T_4225[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4357 = or(_T_4353, _T_4355) @[Mux.scala 19:72] + wire _T_4359 : UInt<1> @[Mux.scala 19:72] + _T_4359 is invalid @[Mux.scala 19:72] + _T_4359 <= _T_4357 @[Mux.scala 19:72] + in[0].a.ready <= _T_4359 @[Xbar.scala 152:19] + wire _T_4402 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_4402 is invalid @[Xbar.scala 147:26] + _T_4402[0].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_4486 = and(out[0].b.valid, requestBOI[0][0]) @[Xbar.scala 150:42] + _T_4402[0].valid <= _T_4486 @[Xbar.scala 150:27] + out[0].b.ready <= _T_4402[0].ready @[Xbar.scala 152:19] + wire _T_4529 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_4529 is invalid @[Xbar.scala 147:26] + _T_4529[0].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_4613 = and(out[1].b.valid, requestBOI[1][0]) @[Xbar.scala 150:42] + _T_4529[0].valid <= _T_4613 @[Xbar.scala 150:27] + out[1].b.ready <= _T_4529[0].ready @[Xbar.scala 152:19] + wire _T_4676 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}[2] @[Xbar.scala 147:26] + _T_4676 is invalid @[Xbar.scala 147:26] + _T_4676[0].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_4801 = and(in[0].c.valid, requestCIO[0][0]) @[Xbar.scala 150:42] + _T_4676[0].valid <= _T_4801 @[Xbar.scala 150:27] + _T_4676[1].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_4802 = and(in[0].c.valid, requestCIO[0][1]) @[Xbar.scala 150:42] + _T_4676[1].valid <= _T_4802 @[Xbar.scala 150:27] + node _T_4804 = mux(requestCIO[0][0], _T_4676[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4806 = mux(requestCIO[0][1], _T_4676[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_4808 = or(_T_4804, _T_4806) @[Mux.scala 19:72] + wire _T_4810 : UInt<1> @[Mux.scala 19:72] + _T_4810 is invalid @[Mux.scala 19:72] + _T_4810 <= _T_4808 @[Mux.scala 19:72] + in[0].c.ready <= _T_4810 @[Xbar.scala 152:19] + wire _T_4857 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_4857 is invalid @[Xbar.scala 147:26] + _T_4857[0].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_4949 = and(out[0].d.valid, requestDOI[0][0]) @[Xbar.scala 150:42] + _T_4857[0].valid <= _T_4949 @[Xbar.scala 150:27] + out[0].d.ready <= _T_4857[0].ready @[Xbar.scala 152:19] + wire _T_4996 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_4996 is invalid @[Xbar.scala 147:26] + _T_4996[0].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_5088 = and(out[1].d.valid, requestDOI[1][0]) @[Xbar.scala 150:42] + _T_4996[0].valid <= _T_5088 @[Xbar.scala 150:27] + out[1].d.ready <= _T_4996[0].ready @[Xbar.scala 152:19] + wire _T_5115 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}[2] @[Xbar.scala 147:26] + _T_5115 is invalid @[Xbar.scala 147:26] + _T_5115[0].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_5168 = and(in[0].e.valid, requestEIO[0][0]) @[Xbar.scala 150:42] + _T_5115[0].valid <= _T_5168 @[Xbar.scala 150:27] + _T_5115[1].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_5169 = and(in[0].e.valid, requestEIO[0][1]) @[Xbar.scala 150:42] + _T_5115[1].valid <= _T_5169 @[Xbar.scala 150:27] + node _T_5171 = mux(requestEIO[0][0], _T_5115[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5173 = mux(requestEIO[0][1], _T_5115[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5175 = or(_T_5171, _T_5173) @[Mux.scala 19:72] + wire _T_5177 : UInt<1> @[Mux.scala 19:72] + _T_5177 is invalid @[Mux.scala 19:72] + _T_5177 <= _T_5175 @[Mux.scala 19:72] + in[0].e.ready <= _T_5177 @[Xbar.scala 152:19] + reg _T_5179 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5181 = eq(_T_5179, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5182 = and(_T_5181, out[0].a.ready) @[Arbiter.scala 35:24] + node _T_5185 = eq(_T_4225[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5186 = and(UInt<1>("h01"), _T_5185) @[Arbiter.scala 14:35] + wire _T_5189 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_5189 is invalid @[Arbiter.scala 40:23] + _T_5189[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_5193 = and(_T_5189[0], _T_4225[0].valid) @[Arbiter.scala 42:65] + wire _T_5196 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_5196 is invalid @[Arbiter.scala 42:23] + _T_5196[0] <= _T_5193 @[Arbiter.scala 42:23] + node _T_5201 = or(UInt<1>("h00"), _T_5196[0]) @[Arbiter.scala 47:52] + node _T_5203 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5205 = eq(_T_5196[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5206 = or(_T_5203, _T_5205) @[Arbiter.scala 48:59] + node _T_5207 = or(_T_5206, reset) @[Arbiter.scala 48:13] + node _T_5209 = eq(_T_5207, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5209 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5211 = eq(_T_4225[0].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5212 = or(_T_5211, _T_5196[0]) @[Arbiter.scala 50:36] + node _T_5213 = or(_T_5212, reset) @[Arbiter.scala 50:14] + node _T_5215 = eq(_T_5213, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5215 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5217 = mux(_T_5196[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5218 = and(out[0].a.ready, out[0].a.valid) @[Decoupled.scala 30:37] + node _T_5219 = sub(_T_5179, _T_5218) @[Arbiter.scala 55:52] + node _T_5220 = asUInt(_T_5219) @[Arbiter.scala 55:52] + node _T_5221 = tail(_T_5220, 1) @[Arbiter.scala 55:52] + node _T_5222 = mux(_T_5182, _T_5217, _T_5221) @[Arbiter.scala 55:23] + _T_5179 <= _T_5222 @[Arbiter.scala 55:17] + wire _T_5226 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_5226 is invalid @[Arbiter.scala 58:49] + _T_5226[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5230 : UInt<1>[1], clock with : (reset => (reset, _T_5226)) @[Reg.scala 26:44] + node _T_5236 = mux(_T_5181, _T_5196, _T_5230) @[Arbiter.scala 59:25] + _T_5230 <- _T_5236 @[Arbiter.scala 60:13] + _T_4225[0].ready <= out[0].a.ready @[Arbiter.scala 68:28] + node _T_5242 = mux(_T_5181, _T_4225[0].valid, _T_4225[0].valid) @[Arbiter.scala 71:24] + out[0].a.valid <= _T_5242 @[Arbiter.scala 71:18] + out[0].a.bits <- _T_4225[0].bits @[Arbiter.scala 72:17] + out[0].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[0].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_5246 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5248 = eq(_T_5246, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5249 = and(_T_5248, out[1].a.ready) @[Arbiter.scala 35:24] + node _T_5252 = eq(_T_4225[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5253 = and(UInt<1>("h01"), _T_5252) @[Arbiter.scala 14:35] + wire _T_5256 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_5256 is invalid @[Arbiter.scala 40:23] + _T_5256[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_5260 = and(_T_5256[0], _T_4225[1].valid) @[Arbiter.scala 42:65] + wire _T_5263 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_5263 is invalid @[Arbiter.scala 42:23] + _T_5263[0] <= _T_5260 @[Arbiter.scala 42:23] + node _T_5268 = or(UInt<1>("h00"), _T_5263[0]) @[Arbiter.scala 47:52] + node _T_5270 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5272 = eq(_T_5263[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5273 = or(_T_5270, _T_5272) @[Arbiter.scala 48:59] + node _T_5274 = or(_T_5273, reset) @[Arbiter.scala 48:13] + node _T_5276 = eq(_T_5274, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5276 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5278 = eq(_T_4225[1].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5279 = or(_T_5278, _T_5263[0]) @[Arbiter.scala 50:36] + node _T_5280 = or(_T_5279, reset) @[Arbiter.scala 50:14] + node _T_5282 = eq(_T_5280, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5282 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5284 = mux(_T_5263[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5285 = and(out[1].a.ready, out[1].a.valid) @[Decoupled.scala 30:37] + node _T_5286 = sub(_T_5246, _T_5285) @[Arbiter.scala 55:52] + node _T_5287 = asUInt(_T_5286) @[Arbiter.scala 55:52] + node _T_5288 = tail(_T_5287, 1) @[Arbiter.scala 55:52] + node _T_5289 = mux(_T_5249, _T_5284, _T_5288) @[Arbiter.scala 55:23] + _T_5246 <= _T_5289 @[Arbiter.scala 55:17] + wire _T_5293 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_5293 is invalid @[Arbiter.scala 58:49] + _T_5293[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5297 : UInt<1>[1], clock with : (reset => (reset, _T_5293)) @[Reg.scala 26:44] + node _T_5303 = mux(_T_5248, _T_5263, _T_5297) @[Arbiter.scala 59:25] + _T_5297 <- _T_5303 @[Arbiter.scala 60:13] + _T_4225[1].ready <= out[1].a.ready @[Arbiter.scala 68:28] + node _T_5309 = mux(_T_5248, _T_4225[1].valid, _T_4225[1].valid) @[Arbiter.scala 71:24] + out[1].a.valid <= _T_5309 @[Arbiter.scala 71:18] + out[1].a.bits <- _T_4225[1].bits @[Arbiter.scala 72:17] + out[1].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[1].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + in[0].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_5314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_5316 = eq(_T_5314, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_5317 = and(_T_5316, in[0].d.ready) @[Arbiter.scala 35:24] + node _T_5320 = eq(_T_4857[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5321 = and(UInt<1>("h01"), _T_5320) @[Arbiter.scala 14:35] + node _T_5323 = eq(_T_4996[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_5324 = and(_T_5321, _T_5323) @[Arbiter.scala 14:35] + wire _T_5327 : UInt<1>[2] @[Arbiter.scala 40:23] + _T_5327 is invalid @[Arbiter.scala 40:23] + _T_5327[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_5327[1] <= _T_5321 @[Arbiter.scala 40:23] + node _T_5332 = and(_T_5327[0], _T_4857[0].valid) @[Arbiter.scala 42:65] + node _T_5333 = and(_T_5327[1], _T_4996[0].valid) @[Arbiter.scala 42:65] + wire _T_5336 : UInt<1>[2] @[Arbiter.scala 42:23] + _T_5336 is invalid @[Arbiter.scala 42:23] + _T_5336[0] <= _T_5332 @[Arbiter.scala 42:23] + _T_5336[1] <= _T_5333 @[Arbiter.scala 42:23] + node _T_5342 = or(UInt<1>("h00"), _T_5336[0]) @[Arbiter.scala 47:52] + node _T_5343 = or(_T_5342, _T_5336[1]) @[Arbiter.scala 47:52] + node _T_5345 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5347 = eq(_T_5336[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5348 = or(_T_5345, _T_5347) @[Arbiter.scala 48:59] + node _T_5350 = eq(_T_5342, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_5352 = eq(_T_5336[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_5353 = or(_T_5350, _T_5352) @[Arbiter.scala 48:59] + node _T_5354 = and(_T_5348, _T_5353) @[Arbiter.scala 48:77] + node _T_5355 = or(_T_5354, reset) @[Arbiter.scala 48:13] + node _T_5357 = eq(_T_5355, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_5357 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_5358 = or(_T_4857[0].valid, _T_4996[0].valid) @[Arbiter.scala 50:31] + node _T_5360 = eq(_T_5358, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_5361 = or(_T_5336[0], _T_5336[1]) @[Arbiter.scala 50:54] + node _T_5362 = or(_T_5360, _T_5361) @[Arbiter.scala 50:36] + node _T_5363 = or(_T_5362, reset) @[Arbiter.scala 50:14] + node _T_5365 = eq(_T_5363, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_5365 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_5367 = mux(_T_5336[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5369 = mux(_T_5336[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_5370 = or(_T_5367, _T_5369) @[Arbiter.scala 54:44] + node _T_5371 = and(in[0].d.ready, in[0].d.valid) @[Decoupled.scala 30:37] + node _T_5372 = sub(_T_5314, _T_5371) @[Arbiter.scala 55:52] + node _T_5373 = asUInt(_T_5372) @[Arbiter.scala 55:52] + node _T_5374 = tail(_T_5373, 1) @[Arbiter.scala 55:52] + node _T_5375 = mux(_T_5317, _T_5370, _T_5374) @[Arbiter.scala 55:23] + _T_5314 <= _T_5375 @[Arbiter.scala 55:17] + wire _T_5380 : UInt<1>[2] @[Arbiter.scala 58:49] + _T_5380 is invalid @[Arbiter.scala 58:49] + _T_5380[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_5380[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_5385 : UInt<1>[2], clock with : (reset => (reset, _T_5380)) @[Reg.scala 26:44] + node _T_5393 = mux(_T_5316, _T_5336, _T_5385) @[Arbiter.scala 59:25] + _T_5385 <- _T_5393 @[Arbiter.scala 60:13] + node _T_5401 = mux(_T_5316, _T_5327, _T_5385) @[Arbiter.scala 63:26] + node _T_5409 = and(in[0].d.ready, _T_5401[0]) @[Arbiter.scala 65:33] + _T_4857[0].ready <= _T_5409 @[Arbiter.scala 65:19] + node _T_5410 = and(in[0].d.ready, _T_5401[1]) @[Arbiter.scala 65:33] + _T_4996[0].ready <= _T_5410 @[Arbiter.scala 65:19] + node _T_5411 = or(_T_4857[0].valid, _T_4996[0].valid) @[Arbiter.scala 71:46] + node _T_5413 = mux(_T_5385[0], _T_4857[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5415 = mux(_T_5385[1], _T_4996[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5417 = or(_T_5413, _T_5415) @[Mux.scala 19:72] + wire _T_5419 : UInt<1> @[Mux.scala 19:72] + _T_5419 is invalid @[Mux.scala 19:72] + _T_5419 <= _T_5417 @[Mux.scala 19:72] + node _T_5420 = mux(_T_5316, _T_5411, _T_5419) @[Arbiter.scala 71:24] + in[0].d.valid <= _T_5420 @[Arbiter.scala 71:18] + node _T_5421 = cat(_T_4857[0].bits.data, _T_4857[0].bits.error) @[Mux.scala 19:72] + node _T_5422 = cat(_T_4857[0].bits.sink, _T_4857[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_5423 = cat(_T_5422, _T_5421) @[Mux.scala 19:72] + node _T_5424 = cat(_T_4857[0].bits.size, _T_4857[0].bits.source) @[Mux.scala 19:72] + node _T_5425 = cat(_T_4857[0].bits.opcode, _T_4857[0].bits.param) @[Mux.scala 19:72] + node _T_5426 = cat(_T_5425, _T_5424) @[Mux.scala 19:72] + node _T_5427 = cat(_T_5426, _T_5423) @[Mux.scala 19:72] + node _T_5429 = mux(_T_5393[0], _T_5427, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5430 = cat(_T_4996[0].bits.data, _T_4996[0].bits.error) @[Mux.scala 19:72] + node _T_5431 = cat(_T_4996[0].bits.sink, _T_4996[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_5432 = cat(_T_5431, _T_5430) @[Mux.scala 19:72] + node _T_5433 = cat(_T_4996[0].bits.size, _T_4996[0].bits.source) @[Mux.scala 19:72] + node _T_5434 = cat(_T_4996[0].bits.opcode, _T_4996[0].bits.param) @[Mux.scala 19:72] + node _T_5435 = cat(_T_5434, _T_5433) @[Mux.scala 19:72] + node _T_5436 = cat(_T_5435, _T_5432) @[Mux.scala 19:72] + node _T_5438 = mux(_T_5393[1], _T_5436, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5448 = or(_T_5429, _T_5438) @[Mux.scala 19:72] + wire _T_5458 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_5458 is invalid @[Mux.scala 19:72] + wire _T_5468 : UInt<83> + _T_5468 is invalid + _T_5468 <= _T_5448 + node _T_5469 = bits(_T_5468, 0, 0) @[Mux.scala 19:72] + _T_5458.error <= _T_5469 @[Mux.scala 19:72] + node _T_5470 = bits(_T_5468, 64, 1) @[Mux.scala 19:72] + _T_5458.data <= _T_5470 @[Mux.scala 19:72] + node _T_5471 = bits(_T_5468, 67, 65) @[Mux.scala 19:72] + _T_5458.addr_lo <= _T_5471 @[Mux.scala 19:72] + node _T_5472 = bits(_T_5468, 68, 68) @[Mux.scala 19:72] + _T_5458.sink <= _T_5472 @[Mux.scala 19:72] + node _T_5473 = bits(_T_5468, 73, 69) @[Mux.scala 19:72] + _T_5458.source <= _T_5473 @[Mux.scala 19:72] + node _T_5474 = bits(_T_5468, 77, 74) @[Mux.scala 19:72] + _T_5458.size <= _T_5474 @[Mux.scala 19:72] + node _T_5475 = bits(_T_5468, 79, 78) @[Mux.scala 19:72] + _T_5458.param <= _T_5475 @[Mux.scala 19:72] + node _T_5476 = bits(_T_5468, 82, 80) @[Mux.scala 19:72] + _T_5458.opcode <= _T_5476 @[Mux.scala 19:72] + in[0].d.bits <- _T_5458 @[Arbiter.scala 72:17] + + module TLAtomicAutomata_bootrom : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + io.out.0.a.valid <= io.in.0.a.valid @[AtomicAutomata.scala 234:21] + io.in.0.a.ready <= io.out.0.a.ready @[AtomicAutomata.scala 235:20] + io.out.0.a.bits <- io.in.0.a.bits @[AtomicAutomata.scala 236:20] + io.in.0.d.valid <= io.out.0.d.valid @[AtomicAutomata.scala 238:20] + io.out.0.d.ready <= io.in.0.d.ready @[AtomicAutomata.scala 239:21] + io.in.0.d.bits <- io.out.0.d.bits @[AtomicAutomata.scala 240:19] + io.in.0.b.valid <= UInt<1>("h00") @[AtomicAutomata.scala 256:20] + io.in.0.c.ready <= UInt<1>("h01") @[AtomicAutomata.scala 257:20] + io.in.0.e.ready <= UInt<1>("h01") @[AtomicAutomata.scala 258:20] + io.out.0.b.ready <= UInt<1>("h01") @[AtomicAutomata.scala 259:21] + io.out.0.c.valid <= UInt<1>("h00") @[AtomicAutomata.scala 260:21] + io.out.0.e.valid <= UInt<1>("h00") @[AtomicAutomata.scala 261:21] + + module TLMonitor : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[BaseTop.scala 47:58] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[BaseTop.scala 47:58] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_608 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at BaseTop.scala:47:58)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + when _T_708 : @[BaseTop.scala 47:58] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[BaseTop.scala 47:58] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_725 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_726 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_728 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_731 = or(_T_730, reset) @[BaseTop.scala 47:58] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_733 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_734 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_736 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[BaseTop.scala 47:58] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_741 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at BaseTop.scala:47:58)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_742 = not(io.in[0].a.bits.mask) @[BaseTop.scala 47:58] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_745 = or(_T_744, reset) @[BaseTop.scala 47:58] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_747 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 47:58] + when _T_749 : @[BaseTop.scala 47:58] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[BaseTop.scala 47:58] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_770 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_771 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_773 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_774 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_776 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_779 = or(_T_778, reset) @[BaseTop.scala 47:58] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_781 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 47:58] + node _T_783 = or(_T_782, reset) @[BaseTop.scala 47:58] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_785 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_787 : @[BaseTop.scala 47:58] + node _T_790 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_792 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = and(_T_790, _T_798) @[Parameters.scala 132:56] + node _T_801 = or(UInt<1>("h00"), _T_799) @[Parameters.scala 134:30] + node _T_802 = or(_T_801, reset) @[BaseTop.scala 47:58] + node _T_804 = eq(_T_802, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_804 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_805 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_807 = eq(_T_805, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_807 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_808 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_810 = eq(_T_808, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_810 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_812 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_813 = or(_T_812, reset) @[BaseTop.scala 47:58] + node _T_815 = eq(_T_813, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_815 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_816 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 47:58] + node _T_817 = or(_T_816, reset) @[BaseTop.scala 47:58] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_819 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_821 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 47:58] + when _T_821 : @[BaseTop.scala 47:58] + node _T_824 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_826 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = and(_T_824, _T_832) @[Parameters.scala 132:56] + node _T_835 = or(UInt<1>("h00"), _T_833) @[Parameters.scala 134:30] + node _T_836 = or(_T_835, reset) @[BaseTop.scala 47:58] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_838 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_839 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_841 = eq(_T_839, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_841 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_842 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_844 = eq(_T_842, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_844 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_846 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_847 = or(_T_846, reset) @[BaseTop.scala 47:58] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_849 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_850 = not(_T_706) @[BaseTop.scala 47:58] + node _T_851 = and(io.in[0].a.bits.mask, _T_850) @[BaseTop.scala 47:58] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_854 = or(_T_853, reset) @[BaseTop.scala 47:58] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_856 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_858 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 47:58] + when _T_858 : @[BaseTop.scala 47:58] + node _T_861 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_863 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_864 = cvt(_T_863) @[Parameters.scala 117:49] + node _T_866 = and(_T_864, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_867 = asSInt(_T_866) @[Parameters.scala 117:52] + node _T_869 = eq(_T_867, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = and(_T_861, _T_869) @[Parameters.scala 132:56] + node _T_872 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 134:30] + node _T_873 = or(_T_872, reset) @[BaseTop.scala 47:58] + node _T_875 = eq(_T_873, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_875 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_876 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_878 = eq(_T_876, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_878 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_879 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_881 = eq(_T_879, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_881 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_883 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_884 = or(_T_883, reset) @[BaseTop.scala 47:58] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_886 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:47:58)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_887 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 47:58] + node _T_888 = or(_T_887, reset) @[BaseTop.scala 47:58] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_890 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_892 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 47:58] + when _T_892 : @[BaseTop.scala 47:58] + node _T_895 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_897 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = and(_T_895, _T_903) @[Parameters.scala 132:56] + node _T_906 = or(UInt<1>("h00"), _T_904) @[Parameters.scala 134:30] + node _T_907 = or(_T_906, reset) @[BaseTop.scala 47:58] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_909 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_910 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_912 = eq(_T_910, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_912 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_913 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_915 = eq(_T_913, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_915 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_917 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_918 = or(_T_917, reset) @[BaseTop.scala 47:58] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_920 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BaseTop.scala:47:58)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_921 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 47:58] + node _T_922 = or(_T_921, reset) @[BaseTop.scala 47:58] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_924 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 47:58] + when _T_926 : @[BaseTop.scala 47:58] + node _T_929 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_931 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = and(_T_929, _T_937) @[Parameters.scala 132:56] + node _T_940 = or(UInt<1>("h00"), _T_938) @[Parameters.scala 134:30] + node _T_941 = or(_T_940, reset) @[BaseTop.scala 47:58] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_943 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_944 = or(_T_630, reset) @[BaseTop.scala 47:58] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_946 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_947 = or(_T_638, reset) @[BaseTop.scala 47:58] + node _T_949 = eq(_T_947, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_949 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_950 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 47:58] + node _T_951 = or(_T_950, reset) @[BaseTop.scala 47:58] + node _T_953 = eq(_T_951, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_953 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + when io.in[0].b.valid : @[BaseTop.scala 47:58] + node _T_955 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_956 = or(_T_955, reset) @[BaseTop.scala 47:58] + node _T_958 = eq(_T_956, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_958 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at BaseTop.scala:47:58)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_960 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_961 = cvt(_T_960) @[Parameters.scala 117:49] + node _T_963 = and(_T_961, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_964 = asSInt(_T_963) @[Parameters.scala 117:52] + node _T_966 = eq(_T_964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_969 : UInt<1>[1] @[Parameters.scala 110:36] + _T_969 is invalid @[Parameters.scala 110:36] + _T_969[0] <= _T_966 @[Parameters.scala 110:36] + node _T_974 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_975 = dshl(_T_974, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_976 = bits(_T_975, 5, 0) @[package.scala 19:76] + node _T_977 = not(_T_976) @[package.scala 19:40] + node _T_978 = and(io.in[0].b.bits.address, _T_977) @[Edges.scala 17:16] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_982 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_983 = dshl(UInt<1>("h01"), _T_982) @[OneHot.scala 49:12] + node _T_984 = bits(_T_983, 2, 0) @[OneHot.scala 49:37] + node _T_986 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_988 = bits(_T_984, 2, 2) @[package.scala 44:26] + node _T_989 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_991 = eq(_T_989, UInt<1>("h00")) @[package.scala 46:20] + node _T_992 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_993 = and(_T_988, _T_992) @[package.scala 50:38] + node _T_994 = or(_T_986, _T_993) @[package.scala 50:29] + node _T_995 = and(UInt<1>("h01"), _T_989) @[package.scala 49:27] + node _T_996 = and(_T_988, _T_995) @[package.scala 50:38] + node _T_997 = or(_T_986, _T_996) @[package.scala 50:29] + node _T_998 = bits(_T_984, 1, 1) @[package.scala 44:26] + node _T_999 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1001 = eq(_T_999, UInt<1>("h00")) @[package.scala 46:20] + node _T_1002 = and(_T_992, _T_1001) @[package.scala 49:27] + node _T_1003 = and(_T_998, _T_1002) @[package.scala 50:38] + node _T_1004 = or(_T_994, _T_1003) @[package.scala 50:29] + node _T_1005 = and(_T_992, _T_999) @[package.scala 49:27] + node _T_1006 = and(_T_998, _T_1005) @[package.scala 50:38] + node _T_1007 = or(_T_994, _T_1006) @[package.scala 50:29] + node _T_1008 = and(_T_995, _T_1001) @[package.scala 49:27] + node _T_1009 = and(_T_998, _T_1008) @[package.scala 50:38] + node _T_1010 = or(_T_997, _T_1009) @[package.scala 50:29] + node _T_1011 = and(_T_995, _T_999) @[package.scala 49:27] + node _T_1012 = and(_T_998, _T_1011) @[package.scala 50:38] + node _T_1013 = or(_T_997, _T_1012) @[package.scala 50:29] + node _T_1014 = bits(_T_984, 0, 0) @[package.scala 44:26] + node _T_1015 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1017 = eq(_T_1015, UInt<1>("h00")) @[package.scala 46:20] + node _T_1018 = and(_T_1002, _T_1017) @[package.scala 49:27] + node _T_1019 = and(_T_1014, _T_1018) @[package.scala 50:38] + node _T_1020 = or(_T_1004, _T_1019) @[package.scala 50:29] + node _T_1021 = and(_T_1002, _T_1015) @[package.scala 49:27] + node _T_1022 = and(_T_1014, _T_1021) @[package.scala 50:38] + node _T_1023 = or(_T_1004, _T_1022) @[package.scala 50:29] + node _T_1024 = and(_T_1005, _T_1017) @[package.scala 49:27] + node _T_1025 = and(_T_1014, _T_1024) @[package.scala 50:38] + node _T_1026 = or(_T_1007, _T_1025) @[package.scala 50:29] + node _T_1027 = and(_T_1005, _T_1015) @[package.scala 49:27] + node _T_1028 = and(_T_1014, _T_1027) @[package.scala 50:38] + node _T_1029 = or(_T_1007, _T_1028) @[package.scala 50:29] + node _T_1030 = and(_T_1008, _T_1017) @[package.scala 49:27] + node _T_1031 = and(_T_1014, _T_1030) @[package.scala 50:38] + node _T_1032 = or(_T_1010, _T_1031) @[package.scala 50:29] + node _T_1033 = and(_T_1008, _T_1015) @[package.scala 49:27] + node _T_1034 = and(_T_1014, _T_1033) @[package.scala 50:38] + node _T_1035 = or(_T_1010, _T_1034) @[package.scala 50:29] + node _T_1036 = and(_T_1011, _T_1017) @[package.scala 49:27] + node _T_1037 = and(_T_1014, _T_1036) @[package.scala 50:38] + node _T_1038 = or(_T_1013, _T_1037) @[package.scala 50:29] + node _T_1039 = and(_T_1011, _T_1015) @[package.scala 49:27] + node _T_1040 = and(_T_1014, _T_1039) @[package.scala 50:38] + node _T_1041 = or(_T_1013, _T_1040) @[package.scala 50:29] + node _T_1042 = cat(_T_1023, _T_1020) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1029, _T_1026) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1035, _T_1032) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1041, _T_1038) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1050 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + when _T_1050 : @[BaseTop.scala 47:58] + node _T_1052 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1053 = not(_T_1052) @[Parameters.scala 37:9] + node _T_1055 = or(_T_1053, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1056 = not(_T_1055) @[Parameters.scala 37:7] + node _T_1058 = eq(_T_1056, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1060 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1062 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1065 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1065 is invalid @[Parameters.scala 228:27] + _T_1065[0] <= _T_1058 @[Parameters.scala 228:27] + _T_1065[1] <= _T_1060 @[Parameters.scala 228:27] + _T_1065[2] <= _T_1062 @[Parameters.scala 228:27] + node _T_1073 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1075 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1076 = and(_T_1073, _T_1075) @[Parameters.scala 63:37] + node _T_1079 = mux(_T_1065[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1081 = mux(_T_1065[1], _T_1076, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1083 = mux(_T_1065[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1085 = or(_T_1079, _T_1081) @[Mux.scala 19:72] + node _T_1086 = or(_T_1085, _T_1083) @[Mux.scala 19:72] + wire _T_1088 : UInt<1> @[Mux.scala 19:72] + _T_1088 is invalid @[Mux.scala 19:72] + _T_1088 <= _T_1086 @[Mux.scala 19:72] + node _T_1089 = or(_T_1088, reset) @[BaseTop.scala 47:58] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1091 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1092 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1094 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1096 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1097 = or(_T_1096, reset) @[BaseTop.scala 47:58] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1099 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1100 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1102 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1104 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1105 = or(_T_1104, reset) @[BaseTop.scala 47:58] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1107 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BaseTop.scala:47:58)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1108 = not(io.in[0].b.bits.mask) @[BaseTop.scala 47:58] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1111 = or(_T_1110, reset) @[BaseTop.scala 47:58] + node _T_1113 = eq(_T_1111, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1113 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1115 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 47:58] + when _T_1115 : @[BaseTop.scala 47:58] + node _T_1117 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1119 = eq(_T_1117, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1119 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1120 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1122 = eq(_T_1120, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1122 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1123 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1125 = eq(_T_1123, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1125 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1127 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1128 = or(_T_1127, reset) @[BaseTop.scala 47:58] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1130 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1131 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 47:58] + node _T_1132 = or(_T_1131, reset) @[BaseTop.scala 47:58] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1134 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1136 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1136 : @[BaseTop.scala 47:58] + node _T_1138 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1140 = eq(_T_1138, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1140 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1141 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1143 = eq(_T_1141, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1143 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1144 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1146 = eq(_T_1144, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1146 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1148 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1149 = or(_T_1148, reset) @[BaseTop.scala 47:58] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1151 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1152 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 47:58] + node _T_1153 = or(_T_1152, reset) @[BaseTop.scala 47:58] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1155 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1157 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 47:58] + when _T_1157 : @[BaseTop.scala 47:58] + node _T_1159 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1161 = eq(_T_1159, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1161 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1162 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1164 = eq(_T_1162, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1164 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1165 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1167 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1169 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1170 = or(_T_1169, reset) @[BaseTop.scala 47:58] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1172 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1173 = not(_T_1048) @[BaseTop.scala 47:58] + node _T_1174 = and(io.in[0].b.bits.mask, _T_1173) @[BaseTop.scala 47:58] + node _T_1176 = eq(_T_1174, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1177 = or(_T_1176, reset) @[BaseTop.scala 47:58] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1179 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1181 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 47:58] + when _T_1181 : @[BaseTop.scala 47:58] + node _T_1183 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1185 = eq(_T_1183, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1185 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1186 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1188 = eq(_T_1186, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1188 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1189 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1191 = eq(_T_1189, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1191 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1193 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1194 = or(_T_1193, reset) @[BaseTop.scala 47:58] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1196 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:47:58)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1197 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 47:58] + node _T_1198 = or(_T_1197, reset) @[BaseTop.scala 47:58] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1200 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1202 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 47:58] + when _T_1202 : @[BaseTop.scala 47:58] + node _T_1204 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1206 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1207 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1209 = eq(_T_1207, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1209 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1210 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1212 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1214 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1215 = or(_T_1214, reset) @[BaseTop.scala 47:58] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1217 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at BaseTop.scala:47:58)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1218 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 47:58] + node _T_1219 = or(_T_1218, reset) @[BaseTop.scala 47:58] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1221 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1223 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 47:58] + when _T_1223 : @[BaseTop.scala 47:58] + node _T_1225 = or(UInt<1>("h00"), reset) @[BaseTop.scala 47:58] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1227 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at BaseTop.scala:47:58)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1228 = or(_T_969[0], reset) @[BaseTop.scala 47:58] + node _T_1230 = eq(_T_1228, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1230 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1231 = or(_T_980, reset) @[BaseTop.scala 47:58] + node _T_1233 = eq(_T_1231, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1233 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1234 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 47:58] + node _T_1235 = or(_T_1234, reset) @[BaseTop.scala 47:58] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1237 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at BaseTop.scala:47:58)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + when io.in[0].c.valid : @[BaseTop.scala 47:58] + node _T_1239 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1240 = or(_T_1239, reset) @[BaseTop.scala 47:58] + node _T_1242 = eq(_T_1240, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1242 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at BaseTop.scala:47:58)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1244 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1245 = not(_T_1244) @[Parameters.scala 37:9] + node _T_1247 = or(_T_1245, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1248 = not(_T_1247) @[Parameters.scala 37:7] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1252 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1254 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1257 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1257 is invalid @[Parameters.scala 228:27] + _T_1257[0] <= _T_1250 @[Parameters.scala 228:27] + _T_1257[1] <= _T_1252 @[Parameters.scala 228:27] + _T_1257[2] <= _T_1254 @[Parameters.scala 228:27] + node _T_1263 = or(_T_1257[0], _T_1257[1]) @[Parameters.scala 229:46] + node _T_1264 = or(_T_1263, _T_1257[2]) @[Parameters.scala 229:46] + node _T_1266 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1267 = dshl(_T_1266, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1268 = bits(_T_1267, 5, 0) @[package.scala 19:76] + node _T_1269 = not(_T_1268) @[package.scala 19:40] + node _T_1270 = and(io.in[0].c.bits.address, _T_1269) @[Edges.scala 17:16] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1274 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1275 = cvt(_T_1274) @[Parameters.scala 117:49] + node _T_1277 = and(_T_1275, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1278 = asSInt(_T_1277) @[Parameters.scala 117:52] + node _T_1280 = eq(_T_1278, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1283 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1283 is invalid @[Parameters.scala 110:36] + _T_1283[0] <= _T_1280 @[Parameters.scala 110:36] + node _T_1288 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 47:58] + when _T_1288 : @[BaseTop.scala 47:58] + node _T_1289 = or(_T_1283[0], reset) @[BaseTop.scala 47:58] + node _T_1291 = eq(_T_1289, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1291 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1292 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1294 = eq(_T_1292, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1294 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1296 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1297 = or(_T_1296, reset) @[BaseTop.scala 47:58] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1299 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1300 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1302 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1304 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1305 = or(_T_1304, reset) @[BaseTop.scala 47:58] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1307 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BaseTop.scala:47:58)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1309 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1310 = or(_T_1309, reset) @[BaseTop.scala 47:58] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1312 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1314 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 47:58] + when _T_1314 : @[BaseTop.scala 47:58] + node _T_1315 = or(_T_1283[0], reset) @[BaseTop.scala 47:58] + node _T_1317 = eq(_T_1315, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1317 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1318 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1320 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1322 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1323 = or(_T_1322, reset) @[BaseTop.scala 47:58] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1325 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1326 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1328 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1330 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1331 = or(_T_1330, reset) @[BaseTop.scala 47:58] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1333 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BaseTop.scala:47:58)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1335 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1336 = or(_T_1335, reset) @[BaseTop.scala 47:58] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1338 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1340 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + when _T_1340 : @[BaseTop.scala 47:58] + node _T_1343 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1345 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1346 = cvt(_T_1345) @[Parameters.scala 117:49] + node _T_1348 = and(_T_1346, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1349 = asSInt(_T_1348) @[Parameters.scala 117:52] + node _T_1351 = eq(_T_1349, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1352 = and(_T_1343, _T_1351) @[Parameters.scala 132:56] + node _T_1354 = or(UInt<1>("h00"), _T_1352) @[Parameters.scala 134:30] + node _T_1355 = or(_T_1354, reset) @[BaseTop.scala 47:58] + node _T_1357 = eq(_T_1355, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1357 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1358 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1360 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1362 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1363 = or(_T_1362, reset) @[BaseTop.scala 47:58] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1365 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1366 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1368 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1370 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1371 = or(_T_1370, reset) @[BaseTop.scala 47:58] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1373 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at BaseTop.scala:47:58)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1375 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1376 = or(_T_1375, reset) @[BaseTop.scala 47:58] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1378 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1380 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[BaseTop.scala 47:58] + when _T_1380 : @[BaseTop.scala 47:58] + node _T_1383 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1385 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1386 = cvt(_T_1385) @[Parameters.scala 117:49] + node _T_1388 = and(_T_1386, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1389 = asSInt(_T_1388) @[Parameters.scala 117:52] + node _T_1391 = eq(_T_1389, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1392 = and(_T_1383, _T_1391) @[Parameters.scala 132:56] + node _T_1394 = or(UInt<1>("h00"), _T_1392) @[Parameters.scala 134:30] + node _T_1395 = or(_T_1394, reset) @[BaseTop.scala 47:58] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1397 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BaseTop.scala:47:58)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1398 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1400 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1402 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1403 = or(_T_1402, reset) @[BaseTop.scala 47:58] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1405 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1406 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1408 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1410 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1411 = or(_T_1410, reset) @[BaseTop.scala 47:58] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1413 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at BaseTop.scala:47:58)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1415 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1416 = or(_T_1415, reset) @[BaseTop.scala 47:58] + node _T_1418 = eq(_T_1416, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1418 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1420 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1420 : @[BaseTop.scala 47:58] + node _T_1421 = or(_T_1283[0], reset) @[BaseTop.scala 47:58] + node _T_1423 = eq(_T_1421, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1423 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1424 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1426 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1427 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1429 = eq(_T_1427, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1429 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1431 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1432 = or(_T_1431, reset) @[BaseTop.scala 47:58] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1434 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1436 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 47:58] + when _T_1436 : @[BaseTop.scala 47:58] + node _T_1437 = or(_T_1283[0], reset) @[BaseTop.scala 47:58] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1439 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1440 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1442 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1443 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1445 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1447 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1448 = or(_T_1447, reset) @[BaseTop.scala 47:58] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1450 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1452 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 47:58] + when _T_1452 : @[BaseTop.scala 47:58] + node _T_1453 = or(_T_1283[0], reset) @[BaseTop.scala 47:58] + node _T_1455 = eq(_T_1453, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1455 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BaseTop.scala:47:58)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1456 = or(_T_1264, reset) @[BaseTop.scala 47:58] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1458 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1459 = or(_T_1272, reset) @[BaseTop.scala 47:58] + node _T_1461 = eq(_T_1459, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1461 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1463 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1464 = or(_T_1463, reset) @[BaseTop.scala 47:58] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1466 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1468 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1469 = or(_T_1468, reset) @[BaseTop.scala 47:58] + node _T_1471 = eq(_T_1469, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1471 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + when io.in[0].d.valid : @[BaseTop.scala 47:58] + node _T_1473 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1474 = or(_T_1473, reset) @[BaseTop.scala 47:58] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1476 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at BaseTop.scala:47:58)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1478 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1479 = not(_T_1478) @[Parameters.scala 37:9] + node _T_1481 = or(_T_1479, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1482 = not(_T_1481) @[Parameters.scala 37:7] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1486 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1488 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1491 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1491 is invalid @[Parameters.scala 228:27] + _T_1491[0] <= _T_1484 @[Parameters.scala 228:27] + _T_1491[1] <= _T_1486 @[Parameters.scala 228:27] + _T_1491[2] <= _T_1488 @[Parameters.scala 228:27] + node _T_1497 = or(_T_1491[0], _T_1491[1]) @[Parameters.scala 229:46] + node _T_1498 = or(_T_1497, _T_1491[2]) @[Parameters.scala 229:46] + node _T_1500 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1501 = dshl(_T_1500, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1502 = bits(_T_1501, 5, 0) @[package.scala 19:76] + node _T_1503 = not(_T_1502) @[package.scala 19:40] + node _T_1504 = and(io.in[0].d.bits.addr_lo, _T_1503) @[Edges.scala 17:16] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1508 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[BaseTop.scala 47:58] + node _T_1510 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + when _T_1510 : @[BaseTop.scala 47:58] + node _T_1511 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1513 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1514 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1516 = eq(_T_1514, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1516 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1517 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1519 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1521 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1522 = or(_T_1521, reset) @[BaseTop.scala 47:58] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1524 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1526 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1527 = or(_T_1526, reset) @[BaseTop.scala 47:58] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1529 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1531 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1532 = or(_T_1531, reset) @[BaseTop.scala 47:58] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1534 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1536 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 47:58] + when _T_1536 : @[BaseTop.scala 47:58] + node _T_1537 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1539 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1540 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1542 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1543 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1545 = eq(_T_1543, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1545 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1547 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1548 = or(_T_1547, reset) @[BaseTop.scala 47:58] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1550 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1552 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1553 = or(_T_1552, reset) @[BaseTop.scala 47:58] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1555 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BaseTop.scala:47:58)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1557 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 47:58] + when _T_1557 : @[BaseTop.scala 47:58] + node _T_1558 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1560 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1561 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1563 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1564 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1566 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1568 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 47:58] + node _T_1569 = or(_T_1568, reset) @[BaseTop.scala 47:58] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1571 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BaseTop.scala:47:58)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1573 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1574 = or(_T_1573, reset) @[BaseTop.scala 47:58] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1576 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BaseTop.scala:47:58)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1578 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1578 : @[BaseTop.scala 47:58] + node _T_1579 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1581 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1582 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1584 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1585 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1587 = eq(_T_1585, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1587 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1589 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1590 = or(_T_1589, reset) @[BaseTop.scala 47:58] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1592 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1594 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 47:58] + when _T_1594 : @[BaseTop.scala 47:58] + node _T_1595 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1597 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1598 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1600 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1601 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1603 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1605 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1606 = or(_T_1605, reset) @[BaseTop.scala 47:58] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1608 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1610 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 47:58] + when _T_1610 : @[BaseTop.scala 47:58] + node _T_1611 = or(_T_1498, reset) @[BaseTop.scala 47:58] + node _T_1613 = eq(_T_1611, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1613 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1614 = or(_T_1506, reset) @[BaseTop.scala 47:58] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1616 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at BaseTop.scala:47:58)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1617 = or(_T_1508, reset) @[BaseTop.scala 47:58] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1619 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1621 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1622 = or(_T_1621, reset) @[BaseTop.scala 47:58] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1624 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at BaseTop.scala:47:58)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1626 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1627 = or(_T_1626, reset) @[BaseTop.scala 47:58] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1629 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at BaseTop.scala:47:58)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + when io.in[0].e.valid : @[BaseTop.scala 47:58] + node _T_1631 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[BaseTop.scala 47:58] + node _T_1632 = or(_T_1631, reset) @[BaseTop.scala 47:58] + node _T_1634 = eq(_T_1632, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1634 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1635 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1637 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1638 = dshl(_T_1637, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1639 = bits(_T_1638, 5, 0) @[package.scala 19:76] + node _T_1640 = not(_T_1639) @[package.scala 19:40] + node _T_1641 = shr(_T_1640, 3) @[Edges.scala 198:59] + node _T_1642 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1647 = mux(UInt<1>("h00"), _T_1641, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1649 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1651 = sub(_T_1649, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1652 = asUInt(_T_1651) @[Edges.scala 208:28] + node _T_1653 = tail(_T_1652, 1) @[Edges.scala 208:28] + node _T_1655 = eq(_T_1649, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1657 = eq(_T_1649, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1659 = eq(_T_1647, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1660 = or(_T_1657, _T_1659) @[Edges.scala 210:37] + node _T_1661 = and(_T_1660, _T_1635) @[Edges.scala 211:22] + node _T_1662 = not(_T_1653) @[Edges.scala 212:27] + node _T_1663 = and(_T_1647, _T_1662) @[Edges.scala 212:25] + when _T_1635 : @[Edges.scala 213:17] + node _T_1664 = mux(_T_1655, _T_1647, _T_1653) @[Edges.scala 214:21] + _T_1649 <= _T_1664 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1666 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1668 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1670 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1672 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1674 : UInt, clock @[BaseTop.scala 47:58] + node _T_1676 = eq(_T_1655, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1677 = and(io.in[0].a.valid, _T_1676) @[BaseTop.scala 47:58] + when _T_1677 : @[BaseTop.scala 47:58] + node _T_1678 = eq(io.in[0].a.bits.opcode, _T_1666) @[BaseTop.scala 47:58] + node _T_1679 = or(_T_1678, reset) @[BaseTop.scala 47:58] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1681 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1682 = eq(io.in[0].a.bits.param, _T_1668) @[BaseTop.scala 47:58] + node _T_1683 = or(_T_1682, reset) @[BaseTop.scala 47:58] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1685 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1686 = eq(io.in[0].a.bits.size, _T_1670) @[BaseTop.scala 47:58] + node _T_1687 = or(_T_1686, reset) @[BaseTop.scala 47:58] + node _T_1689 = eq(_T_1687, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1689 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1690 = eq(io.in[0].a.bits.source, _T_1672) @[BaseTop.scala 47:58] + node _T_1691 = or(_T_1690, reset) @[BaseTop.scala 47:58] + node _T_1693 = eq(_T_1691, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1693 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1694 = eq(io.in[0].a.bits.address, _T_1674) @[BaseTop.scala 47:58] + node _T_1695 = or(_T_1694, reset) @[BaseTop.scala 47:58] + node _T_1697 = eq(_T_1695, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1697 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1698 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1699 = and(_T_1698, _T_1655) @[BaseTop.scala 47:58] + when _T_1699 : @[BaseTop.scala 47:58] + _T_1666 <= io.in[0].a.bits.opcode @[BaseTop.scala 47:58] + _T_1668 <= io.in[0].a.bits.param @[BaseTop.scala 47:58] + _T_1670 <= io.in[0].a.bits.size @[BaseTop.scala 47:58] + _T_1672 <= io.in[0].a.bits.source @[BaseTop.scala 47:58] + _T_1674 <= io.in[0].a.bits.address @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1700 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1702 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1703 = dshl(_T_1702, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1704 = bits(_T_1703, 5, 0) @[package.scala 19:76] + node _T_1705 = not(_T_1704) @[package.scala 19:40] + node _T_1706 = shr(_T_1705, 3) @[Edges.scala 198:59] + node _T_1707 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1709 = eq(_T_1707, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1712 = mux(UInt<1>("h00"), _T_1706, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1714 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1716 = sub(_T_1714, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1717 = asUInt(_T_1716) @[Edges.scala 208:28] + node _T_1718 = tail(_T_1717, 1) @[Edges.scala 208:28] + node _T_1720 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1722 = eq(_T_1714, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1724 = eq(_T_1712, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1725 = or(_T_1722, _T_1724) @[Edges.scala 210:37] + node _T_1726 = and(_T_1725, _T_1700) @[Edges.scala 211:22] + node _T_1727 = not(_T_1718) @[Edges.scala 212:27] + node _T_1728 = and(_T_1712, _T_1727) @[Edges.scala 212:25] + when _T_1700 : @[Edges.scala 213:17] + node _T_1729 = mux(_T_1720, _T_1712, _T_1718) @[Edges.scala 214:21] + _T_1714 <= _T_1729 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1731 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1733 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1735 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1737 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1739 : UInt, clock @[BaseTop.scala 47:58] + node _T_1741 = eq(_T_1720, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1742 = and(io.in[0].b.valid, _T_1741) @[BaseTop.scala 47:58] + when _T_1742 : @[BaseTop.scala 47:58] + node _T_1743 = eq(io.in[0].b.bits.opcode, _T_1731) @[BaseTop.scala 47:58] + node _T_1744 = or(_T_1743, reset) @[BaseTop.scala 47:58] + node _T_1746 = eq(_T_1744, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1746 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1747 = eq(io.in[0].b.bits.param, _T_1733) @[BaseTop.scala 47:58] + node _T_1748 = or(_T_1747, reset) @[BaseTop.scala 47:58] + node _T_1750 = eq(_T_1748, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1750 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1751 = eq(io.in[0].b.bits.size, _T_1735) @[BaseTop.scala 47:58] + node _T_1752 = or(_T_1751, reset) @[BaseTop.scala 47:58] + node _T_1754 = eq(_T_1752, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1754 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1755 = eq(io.in[0].b.bits.source, _T_1737) @[BaseTop.scala 47:58] + node _T_1756 = or(_T_1755, reset) @[BaseTop.scala 47:58] + node _T_1758 = eq(_T_1756, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1758 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1759 = eq(io.in[0].b.bits.address, _T_1739) @[BaseTop.scala 47:58] + node _T_1760 = or(_T_1759, reset) @[BaseTop.scala 47:58] + node _T_1762 = eq(_T_1760, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1762 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1763 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1764 = and(_T_1763, _T_1720) @[BaseTop.scala 47:58] + when _T_1764 : @[BaseTop.scala 47:58] + _T_1731 <= io.in[0].b.bits.opcode @[BaseTop.scala 47:58] + _T_1733 <= io.in[0].b.bits.param @[BaseTop.scala 47:58] + _T_1735 <= io.in[0].b.bits.size @[BaseTop.scala 47:58] + _T_1737 <= io.in[0].b.bits.source @[BaseTop.scala 47:58] + _T_1739 <= io.in[0].b.bits.address @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1765 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1767 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1768 = dshl(_T_1767, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1769 = bits(_T_1768, 5, 0) @[package.scala 19:76] + node _T_1770 = not(_T_1769) @[package.scala 19:40] + node _T_1771 = shr(_T_1770, 3) @[Edges.scala 198:59] + node _T_1772 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1774 = mux(_T_1772, _T_1771, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1776 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1778 = sub(_T_1776, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1779 = asUInt(_T_1778) @[Edges.scala 208:28] + node _T_1780 = tail(_T_1779, 1) @[Edges.scala 208:28] + node _T_1782 = eq(_T_1776, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1784 = eq(_T_1776, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1786 = eq(_T_1774, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1787 = or(_T_1784, _T_1786) @[Edges.scala 210:37] + node _T_1788 = and(_T_1787, _T_1765) @[Edges.scala 211:22] + node _T_1789 = not(_T_1780) @[Edges.scala 212:27] + node _T_1790 = and(_T_1774, _T_1789) @[Edges.scala 212:25] + when _T_1765 : @[Edges.scala 213:17] + node _T_1791 = mux(_T_1782, _T_1774, _T_1780) @[Edges.scala 214:21] + _T_1776 <= _T_1791 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1793 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1795 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1797 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1799 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1801 : UInt, clock @[BaseTop.scala 47:58] + node _T_1803 = eq(_T_1782, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1804 = and(io.in[0].c.valid, _T_1803) @[BaseTop.scala 47:58] + when _T_1804 : @[BaseTop.scala 47:58] + node _T_1805 = eq(io.in[0].c.bits.opcode, _T_1793) @[BaseTop.scala 47:58] + node _T_1806 = or(_T_1805, reset) @[BaseTop.scala 47:58] + node _T_1808 = eq(_T_1806, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1808 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1809 = eq(io.in[0].c.bits.param, _T_1795) @[BaseTop.scala 47:58] + node _T_1810 = or(_T_1809, reset) @[BaseTop.scala 47:58] + node _T_1812 = eq(_T_1810, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1812 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1813 = eq(io.in[0].c.bits.size, _T_1797) @[BaseTop.scala 47:58] + node _T_1814 = or(_T_1813, reset) @[BaseTop.scala 47:58] + node _T_1816 = eq(_T_1814, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1816 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1817 = eq(io.in[0].c.bits.source, _T_1799) @[BaseTop.scala 47:58] + node _T_1818 = or(_T_1817, reset) @[BaseTop.scala 47:58] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1820 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1821 = eq(io.in[0].c.bits.address, _T_1801) @[BaseTop.scala 47:58] + node _T_1822 = or(_T_1821, reset) @[BaseTop.scala 47:58] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1824 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1825 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1826 = and(_T_1825, _T_1782) @[BaseTop.scala 47:58] + when _T_1826 : @[BaseTop.scala 47:58] + _T_1793 <= io.in[0].c.bits.opcode @[BaseTop.scala 47:58] + _T_1795 <= io.in[0].c.bits.param @[BaseTop.scala 47:58] + _T_1797 <= io.in[0].c.bits.size @[BaseTop.scala 47:58] + _T_1799 <= io.in[0].c.bits.source @[BaseTop.scala 47:58] + _T_1801 <= io.in[0].c.bits.address @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1827 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1829 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1830 = dshl(_T_1829, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1831 = bits(_T_1830, 5, 0) @[package.scala 19:76] + node _T_1832 = not(_T_1831) @[package.scala 19:40] + node _T_1833 = shr(_T_1832, 3) @[Edges.scala 198:59] + node _T_1834 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1837 = mux(UInt<1>("h01"), _T_1833, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1839 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1841 = sub(_T_1839, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1842 = asUInt(_T_1841) @[Edges.scala 208:28] + node _T_1843 = tail(_T_1842, 1) @[Edges.scala 208:28] + node _T_1845 = eq(_T_1839, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1847 = eq(_T_1839, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1849 = eq(_T_1837, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1850 = or(_T_1847, _T_1849) @[Edges.scala 210:37] + node _T_1851 = and(_T_1850, _T_1827) @[Edges.scala 211:22] + node _T_1852 = not(_T_1843) @[Edges.scala 212:27] + node _T_1853 = and(_T_1837, _T_1852) @[Edges.scala 212:25] + when _T_1827 : @[Edges.scala 213:17] + node _T_1854 = mux(_T_1845, _T_1837, _T_1843) @[Edges.scala 214:21] + _T_1839 <= _T_1854 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1856 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1858 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1860 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1862 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1864 : UInt, clock @[BaseTop.scala 47:58] + reg _T_1866 : UInt, clock @[BaseTop.scala 47:58] + node _T_1868 = eq(_T_1845, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1869 = and(io.in[0].d.valid, _T_1868) @[BaseTop.scala 47:58] + when _T_1869 : @[BaseTop.scala 47:58] + node _T_1870 = eq(io.in[0].d.bits.opcode, _T_1856) @[BaseTop.scala 47:58] + node _T_1871 = or(_T_1870, reset) @[BaseTop.scala 47:58] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1873 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1874 = eq(io.in[0].d.bits.param, _T_1858) @[BaseTop.scala 47:58] + node _T_1875 = or(_T_1874, reset) @[BaseTop.scala 47:58] + node _T_1877 = eq(_T_1875, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1877 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1878 = eq(io.in[0].d.bits.size, _T_1860) @[BaseTop.scala 47:58] + node _T_1879 = or(_T_1878, reset) @[BaseTop.scala 47:58] + node _T_1881 = eq(_T_1879, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1881 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1882 = eq(io.in[0].d.bits.source, _T_1862) @[BaseTop.scala 47:58] + node _T_1883 = or(_T_1882, reset) @[BaseTop.scala 47:58] + node _T_1885 = eq(_T_1883, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1885 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1886 = eq(io.in[0].d.bits.sink, _T_1864) @[BaseTop.scala 47:58] + node _T_1887 = or(_T_1886, reset) @[BaseTop.scala 47:58] + node _T_1889 = eq(_T_1887, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1889 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1890 = eq(io.in[0].d.bits.addr_lo, _T_1866) @[BaseTop.scala 47:58] + node _T_1891 = or(_T_1890, reset) @[BaseTop.scala 47:58] + node _T_1893 = eq(_T_1891, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1893 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at BaseTop.scala:47:58)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1894 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1895 = and(_T_1894, _T_1845) @[BaseTop.scala 47:58] + when _T_1895 : @[BaseTop.scala 47:58] + _T_1856 <= io.in[0].d.bits.opcode @[BaseTop.scala 47:58] + _T_1858 <= io.in[0].d.bits.param @[BaseTop.scala 47:58] + _T_1860 <= io.in[0].d.bits.size @[BaseTop.scala 47:58] + _T_1862 <= io.in[0].d.bits.source @[BaseTop.scala 47:58] + _T_1864 <= io.in[0].d.bits.sink @[BaseTop.scala 47:58] + _T_1866 <= io.in[0].d.bits.addr_lo @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + reg _T_1897 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1898 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1900 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1901 = dshl(_T_1900, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1902 = bits(_T_1901, 5, 0) @[package.scala 19:76] + node _T_1903 = not(_T_1902) @[package.scala 19:40] + node _T_1904 = shr(_T_1903, 3) @[Edges.scala 198:59] + node _T_1905 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1907 = eq(_T_1905, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1910 = mux(UInt<1>("h00"), _T_1904, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1912 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1914 = sub(_T_1912, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1915 = asUInt(_T_1914) @[Edges.scala 208:28] + node _T_1916 = tail(_T_1915, 1) @[Edges.scala 208:28] + node _T_1918 = eq(_T_1912, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1920 = eq(_T_1912, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1922 = eq(_T_1910, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1923 = or(_T_1920, _T_1922) @[Edges.scala 210:37] + node _T_1924 = and(_T_1923, _T_1898) @[Edges.scala 211:22] + node _T_1925 = not(_T_1916) @[Edges.scala 212:27] + node _T_1926 = and(_T_1910, _T_1925) @[Edges.scala 212:25] + when _T_1898 : @[Edges.scala 213:17] + node _T_1927 = mux(_T_1918, _T_1910, _T_1916) @[Edges.scala 214:21] + _T_1912 <= _T_1927 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1928 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1930 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1931 = dshl(_T_1930, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1932 = bits(_T_1931, 5, 0) @[package.scala 19:76] + node _T_1933 = not(_T_1932) @[package.scala 19:40] + node _T_1934 = shr(_T_1933, 3) @[Edges.scala 198:59] + node _T_1935 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1938 = mux(UInt<1>("h01"), _T_1934, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1940 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1942 = sub(_T_1940, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1943 = asUInt(_T_1942) @[Edges.scala 208:28] + node _T_1944 = tail(_T_1943, 1) @[Edges.scala 208:28] + node _T_1946 = eq(_T_1940, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1948 = eq(_T_1940, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1950 = eq(_T_1938, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1951 = or(_T_1948, _T_1950) @[Edges.scala 210:37] + node _T_1952 = and(_T_1951, _T_1928) @[Edges.scala 211:22] + node _T_1953 = not(_T_1944) @[Edges.scala 212:27] + node _T_1954 = and(_T_1938, _T_1953) @[Edges.scala 212:25] + when _T_1928 : @[Edges.scala 213:17] + node _T_1955 = mux(_T_1946, _T_1938, _T_1944) @[Edges.scala 214:21] + _T_1940 <= _T_1955 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1957 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + node _T_1958 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[BaseTop.scala 47:58] + node _T_1959 = or(_T_1957, _T_1958) @[BaseTop.scala 47:58] + node _T_1961 = eq(io.in[0].a.valid, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1962 = or(_T_1959, _T_1961) @[BaseTop.scala 47:58] + node _T_1964 = eq(io.in[0].d.valid, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1965 = or(_T_1962, _T_1964) @[BaseTop.scala 47:58] + node _T_1966 = or(_T_1965, reset) @[BaseTop.scala 47:58] + node _T_1968 = eq(_T_1966, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1968 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BaseTop.scala:47:58)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + wire _T_1970 : UInt<6> + _T_1970 is invalid + _T_1970 <= UInt<6>("h00") + node _T_1971 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1971 : @[BaseTop.scala 47:58] + when _T_1923 : @[BaseTop.scala 47:58] + node _T_1973 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1970 <= _T_1973 @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1974 = dshr(_T_1897, io.in[0].a.bits.source) @[BaseTop.scala 47:58] + node _T_1975 = bits(_T_1974, 0, 0) @[BaseTop.scala 47:58] + node _T_1977 = eq(_T_1975, UInt<1>("h00")) @[BaseTop.scala 47:58] + node _T_1978 = or(_T_1977, reset) @[BaseTop.scala 47:58] + node _T_1980 = eq(_T_1978, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1980 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at BaseTop.scala:47:58)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + wire _T_1982 : UInt<6> + _T_1982 is invalid + _T_1982 <= UInt<6>("h00") + node _T_1983 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1985 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 47:58] + node _T_1986 = and(_T_1983, _T_1985) @[BaseTop.scala 47:58] + when _T_1986 : @[BaseTop.scala 47:58] + when _T_1951 : @[BaseTop.scala 47:58] + node _T_1988 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1982 <= _T_1988 @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1989 = or(_T_1970, _T_1897) @[BaseTop.scala 47:58] + node _T_1990 = dshr(_T_1989, io.in[0].d.bits.source) @[BaseTop.scala 47:58] + node _T_1991 = bits(_T_1990, 0, 0) @[BaseTop.scala 47:58] + node _T_1992 = or(_T_1991, reset) @[BaseTop.scala 47:58] + node _T_1994 = eq(_T_1992, UInt<1>("h00")) @[BaseTop.scala 47:58] + when _T_1994 : @[BaseTop.scala 47:58] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BaseTop.scala:47:58)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[BaseTop.scala 47:58] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + skip @[BaseTop.scala 47:58] + node _T_1995 = or(_T_1897, _T_1970) @[BaseTop.scala 47:58] + node _T_1996 = not(_T_1982) @[BaseTop.scala 47:58] + node _T_1997 = and(_T_1995, _T_1996) @[BaseTop.scala 47:58] + _T_1897 <= _T_1997 @[BaseTop.scala 47:58] + + module Repeater : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLWidthWidget_bootrom : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + wire _T_531 : UInt<1> @[WidthWidget.scala 134:26] + _T_531 is invalid @[WidthWidget.scala 134:26] + inst Repeater of Repeater @[Repeater.scala 34:26] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.repeat <= _T_531 @[Repeater.scala 35:24] + Repeater.io.enq <- io.in.0.a @[Repeater.scala 36:21] + node _T_532 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_534 = eq(_T_532, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_536 = bits(Repeater.io.deq.bits.data, 31, 0) @[WidthWidget.scala 93:55] + node _T_537 = bits(Repeater.io.deq.bits.data, 63, 32) @[WidthWidget.scala 93:55] + wire _T_540 : UInt<32>[2] @[WidthWidget.scala 93:44] + _T_540 is invalid @[WidthWidget.scala 93:44] + _T_540[0] <= _T_536 @[WidthWidget.scala 93:44] + _T_540[1] <= _T_537 @[WidthWidget.scala 93:44] + node _T_545 = bits(Repeater.io.deq.bits.mask, 3, 0) @[WidthWidget.scala 94:55] + node _T_546 = bits(Repeater.io.deq.bits.mask, 7, 4) @[WidthWidget.scala 94:55] + wire _T_549 : UInt<4>[2] @[WidthWidget.scala 94:44] + _T_549 is invalid @[WidthWidget.scala 94:44] + _T_549[0] <= _T_545 @[WidthWidget.scala 94:44] + _T_549[1] <= _T_546 @[WidthWidget.scala 94:44] + node _T_556 = asUInt(asSInt(UInt<2>("h03"))) @[WidthWidget.scala 95:76] + reg _T_557 : UInt<2>, clock with : (reset => (reset, _T_556)) @[WidthWidget.scala 95:23] + node _T_559 = neq(_T_549[0], UInt<1>("h00")) @[WidthWidget.scala 96:36] + node _T_561 = neq(_T_549[1], UInt<1>("h00")) @[WidthWidget.scala 96:36] + node _T_563 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_564 = dshl(_T_563, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_565 = bits(_T_564, 2, 0) @[package.scala 19:76] + node _T_566 = not(_T_565) @[package.scala 19:40] + node _T_567 = shr(_T_566, 2) @[WidthWidget.scala 99:56] + node _T_569 = bits(_T_567, 0, 0) @[WidthWidget.scala 100:82] + node _T_571 = eq(_T_569, UInt<1>("h00")) @[WidthWidget.scala 100:74] + node _T_572 = bits(_T_557, 1, 1) @[WidthWidget.scala 102:25] + node _T_573 = cat(_T_571, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_574 = shl(_T_557, 1) @[WidthWidget.scala 103:69] + node _T_575 = mux(_T_572, _T_573, _T_574) @[WidthWidget.scala 103:27] + node _T_576 = bits(_T_575, 1, 1) @[WidthWidget.scala 104:28] + node _T_578 = eq(UInt<1>("h00"), UInt<1>("h00")) @[WidthWidget.scala 104:41] + node _T_579 = or(_T_576, _T_578) @[WidthWidget.scala 104:38] + node _T_580 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_580 : @[WidthWidget.scala 105:25] + _T_557 <= _T_575 @[WidthWidget.scala 106:16] + node _T_582 = eq(UInt<1>("h00"), UInt<1>("h00")) @[WidthWidget.scala 107:15] + when _T_582 : @[WidthWidget.scala 107:25] + node _T_584 = asUInt(asSInt(UInt<2>("h03"))) @[WidthWidget.scala 107:61] + _T_557 <= _T_584 @[WidthWidget.scala 107:34] + skip @[WidthWidget.scala 107:25] + skip @[WidthWidget.scala 105:25] + node _T_585 = cat(_T_561, _T_559) @[Cat.scala 30:58] + node _T_586 = and(_T_585, _T_575) @[WidthWidget.scala 110:39] + node _T_588 = bits(_T_586, 0, 0) @[Mux.scala 21:36] + node _T_589 = bits(_T_586, 1, 1) @[Mux.scala 21:36] + node _T_591 = mux(_T_588, _T_549[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_593 = mux(_T_589, _T_549[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_595 = or(_T_591, _T_593) @[Mux.scala 19:72] + wire _T_597 : UInt<4> @[Mux.scala 19:72] + _T_597 is invalid @[Mux.scala 19:72] + _T_597 <= _T_595 @[Mux.scala 19:72] + io.out.0.a <- Repeater.io.deq @[WidthWidget.scala 114:11] + io.out.0.a.bits.data <= UInt<1>("h00") @[WidthWidget.scala 115:30] + io.out.0.a.bits.mask <= _T_597 @[WidthWidget.scala 118:37] + node _T_599 = eq(_T_579, UInt<1>("h00")) @[WidthWidget.scala 125:7] + _T_531 <= _T_599 @[WidthWidget.scala 135:16] + reg _T_601 : UInt<32>, clock @[WidthWidget.scala 29:22] + reg _T_603 : UInt<4>, clock @[WidthWidget.scala 30:22] + node _T_604 = cat(io.out.0.d.bits.data, _T_601) @[Cat.scala 30:58] + node _T_606 = bits(io.out.0.d.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_607 = dshl(UInt<1>("h01"), _T_606) @[OneHot.scala 49:12] + node _T_608 = bits(_T_607, 1, 0) @[OneHot.scala 49:37] + node _T_610 = geq(io.out.0.d.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_612 = bits(_T_608, 1, 1) @[package.scala 44:26] + node _T_613 = bits(io.out.0.d.bits.addr_lo, 1, 1) @[package.scala 45:26] + node _T_615 = eq(_T_613, UInt<1>("h00")) @[package.scala 46:20] + node _T_616 = and(UInt<1>("h01"), _T_615) @[package.scala 49:27] + node _T_617 = and(_T_612, _T_616) @[package.scala 50:38] + node _T_618 = or(_T_610, _T_617) @[package.scala 50:29] + node _T_619 = and(UInt<1>("h01"), _T_613) @[package.scala 49:27] + node _T_620 = and(_T_612, _T_619) @[package.scala 50:38] + node _T_621 = or(_T_610, _T_620) @[package.scala 50:29] + node _T_622 = bits(_T_608, 0, 0) @[package.scala 44:26] + node _T_623 = bits(io.out.0.d.bits.addr_lo, 0, 0) @[package.scala 45:26] + node _T_625 = eq(_T_623, UInt<1>("h00")) @[package.scala 46:20] + node _T_626 = and(_T_616, _T_625) @[package.scala 49:27] + node _T_627 = and(_T_622, _T_626) @[package.scala 50:38] + node _T_628 = or(_T_618, _T_627) @[package.scala 50:29] + node _T_629 = and(_T_616, _T_623) @[package.scala 49:27] + node _T_630 = and(_T_622, _T_629) @[package.scala 50:38] + node _T_631 = or(_T_618, _T_630) @[package.scala 50:29] + node _T_632 = and(_T_619, _T_625) @[package.scala 49:27] + node _T_633 = and(_T_622, _T_632) @[package.scala 50:38] + node _T_634 = or(_T_621, _T_633) @[package.scala 50:29] + node _T_635 = and(_T_619, _T_623) @[package.scala 49:27] + node _T_636 = and(_T_622, _T_635) @[package.scala 50:38] + node _T_637 = or(_T_621, _T_636) @[package.scala 50:29] + node _T_638 = cat(_T_631, _T_628) @[Cat.scala 30:58] + node _T_639 = cat(_T_637, _T_634) @[Cat.scala 30:58] + node _T_640 = cat(_T_639, _T_638) @[Cat.scala 30:58] + node _T_641 = cat(_T_640, _T_603) @[Cat.scala 30:58] + node _T_642 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + reg _T_645 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_647 = eq(_T_645, UInt<1>("h00")) @[WidthWidget.scala 38:25] + node _T_649 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_650 = dshl(_T_649, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_651 = bits(_T_650, 2, 0) @[package.scala 19:76] + node _T_652 = not(_T_651) @[package.scala 19:40] + node _T_653 = shr(_T_652, 2) @[WidthWidget.scala 39:55] + node _T_654 = eq(_T_645, _T_653) @[WidthWidget.scala 40:24] + node _T_656 = eq(UInt<1>("h01"), UInt<1>("h00")) @[WidthWidget.scala 40:37] + node _T_657 = or(_T_654, _T_656) @[WidthWidget.scala 40:34] + node _T_658 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_658 : @[WidthWidget.scala 42:24] + node _T_659 = shr(_T_604, 32) @[WidthWidget.scala 43:23] + _T_601 <= _T_659 @[WidthWidget.scala 43:15] + node _T_660 = shr(_T_641, 4) @[WidthWidget.scala 44:23] + _T_603 <= _T_660 @[WidthWidget.scala 44:15] + node _T_662 = add(_T_645, UInt<1>("h01")) @[WidthWidget.scala 45:24] + node _T_663 = tail(_T_662, 1) @[WidthWidget.scala 45:24] + _T_645 <= _T_663 @[WidthWidget.scala 45:15] + when _T_657 : @[WidthWidget.scala 46:21] + _T_645 <= UInt<1>("h00") @[WidthWidget.scala 46:29] + skip @[WidthWidget.scala 46:21] + skip @[WidthWidget.scala 42:24] + node _T_665 = bits(_T_604, 63, 32) @[WidthWidget.scala 52:45] + node _T_666 = cat(_T_665, _T_665) @[Cat.scala 30:58] + node _T_667 = bits(_T_641, 7, 4) @[WidthWidget.scala 53:45] + node _T_668 = cat(_T_667, _T_667) @[Cat.scala 30:58] + node _T_669 = bits(_T_604, 63, 0) @[WidthWidget.scala 52:45] + node _T_670 = bits(_T_641, 7, 0) @[WidthWidget.scala 53:45] + wire _T_673 : UInt<64>[7] @[WidthWidget.scala 55:66] + _T_673 is invalid @[WidthWidget.scala 55:66] + _T_673[0] <= _T_666 @[WidthWidget.scala 55:66] + _T_673[1] <= _T_666 @[WidthWidget.scala 55:66] + _T_673[2] <= _T_666 @[WidthWidget.scala 55:66] + _T_673[3] <= _T_669 @[WidthWidget.scala 55:66] + _T_673[4] <= _T_669 @[WidthWidget.scala 55:66] + _T_673[5] <= _T_669 @[WidthWidget.scala 55:66] + _T_673[6] <= _T_669 @[WidthWidget.scala 55:66] + wire _T_685 : UInt<8>[7] @[WidthWidget.scala 58:66] + _T_685 is invalid @[WidthWidget.scala 58:66] + _T_685[0] <= _T_668 @[WidthWidget.scala 58:66] + _T_685[1] <= _T_668 @[WidthWidget.scala 58:66] + _T_685[2] <= _T_668 @[WidthWidget.scala 58:66] + _T_685[3] <= _T_670 @[WidthWidget.scala 58:66] + _T_685[4] <= _T_670 @[WidthWidget.scala 58:66] + _T_685[5] <= _T_670 @[WidthWidget.scala 58:66] + _T_685[6] <= _T_670 @[WidthWidget.scala 58:66] + node _T_697 = eq(_T_657, UInt<1>("h00")) @[WidthWidget.scala 66:32] + node _T_698 = or(io.in.0.d.ready, _T_697) @[WidthWidget.scala 66:29] + io.out.0.d.ready <= _T_698 @[WidthWidget.scala 66:16] + node _T_699 = and(io.out.0.d.valid, _T_657) @[WidthWidget.scala 67:29] + io.in.0.d.valid <= _T_699 @[WidthWidget.scala 67:17] + io.in.0.d.bits <- io.out.0.d.bits @[WidthWidget.scala 68:16] + io.in.0.d.bits.data <= _T_673[io.out.0.d.bits.size] @[WidthWidget.scala 69:30] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[BaseTop.scala 46:42] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[BaseTop.scala 46:42] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_608 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at BaseTop.scala:46:42)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + when _T_708 : @[BaseTop.scala 46:42] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[BaseTop.scala 46:42] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_725 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_726 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_728 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_731 = or(_T_730, reset) @[BaseTop.scala 46:42] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_733 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_734 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_736 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[BaseTop.scala 46:42] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_741 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at BaseTop.scala:46:42)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_742 = not(io.in[0].a.bits.mask) @[BaseTop.scala 46:42] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_745 = or(_T_744, reset) @[BaseTop.scala 46:42] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_747 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 46:42] + when _T_749 : @[BaseTop.scala 46:42] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[BaseTop.scala 46:42] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_770 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_771 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_773 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_774 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_776 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_779 = or(_T_778, reset) @[BaseTop.scala 46:42] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_781 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 46:42] + node _T_783 = or(_T_782, reset) @[BaseTop.scala 46:42] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_785 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_787 : @[BaseTop.scala 46:42] + node _T_790 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_792 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = and(_T_790, _T_798) @[Parameters.scala 132:56] + node _T_801 = or(UInt<1>("h00"), _T_799) @[Parameters.scala 134:30] + node _T_802 = or(_T_801, reset) @[BaseTop.scala 46:42] + node _T_804 = eq(_T_802, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_804 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_805 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_807 = eq(_T_805, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_807 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_808 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_810 = eq(_T_808, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_810 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_812 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_813 = or(_T_812, reset) @[BaseTop.scala 46:42] + node _T_815 = eq(_T_813, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_815 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_816 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 46:42] + node _T_817 = or(_T_816, reset) @[BaseTop.scala 46:42] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_819 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_821 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 46:42] + when _T_821 : @[BaseTop.scala 46:42] + node _T_824 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_826 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = and(_T_824, _T_832) @[Parameters.scala 132:56] + node _T_835 = or(UInt<1>("h00"), _T_833) @[Parameters.scala 134:30] + node _T_836 = or(_T_835, reset) @[BaseTop.scala 46:42] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_838 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_839 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_841 = eq(_T_839, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_841 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_842 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_844 = eq(_T_842, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_844 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_846 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_847 = or(_T_846, reset) @[BaseTop.scala 46:42] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_849 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_850 = not(_T_706) @[BaseTop.scala 46:42] + node _T_851 = and(io.in[0].a.bits.mask, _T_850) @[BaseTop.scala 46:42] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_854 = or(_T_853, reset) @[BaseTop.scala 46:42] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_856 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_858 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 46:42] + when _T_858 : @[BaseTop.scala 46:42] + node _T_861 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_863 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_864 = cvt(_T_863) @[Parameters.scala 117:49] + node _T_866 = and(_T_864, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_867 = asSInt(_T_866) @[Parameters.scala 117:52] + node _T_869 = eq(_T_867, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = and(_T_861, _T_869) @[Parameters.scala 132:56] + node _T_872 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 134:30] + node _T_873 = or(_T_872, reset) @[BaseTop.scala 46:42] + node _T_875 = eq(_T_873, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_875 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_876 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_878 = eq(_T_876, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_878 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_879 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_881 = eq(_T_879, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_881 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_883 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_884 = or(_T_883, reset) @[BaseTop.scala 46:42] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_886 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:46:42)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_887 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 46:42] + node _T_888 = or(_T_887, reset) @[BaseTop.scala 46:42] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_890 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_892 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 46:42] + when _T_892 : @[BaseTop.scala 46:42] + node _T_895 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_897 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = and(_T_895, _T_903) @[Parameters.scala 132:56] + node _T_906 = or(UInt<1>("h00"), _T_904) @[Parameters.scala 134:30] + node _T_907 = or(_T_906, reset) @[BaseTop.scala 46:42] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_909 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_910 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_912 = eq(_T_910, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_912 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_913 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_915 = eq(_T_913, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_915 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_917 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_918 = or(_T_917, reset) @[BaseTop.scala 46:42] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_920 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BaseTop.scala:46:42)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_921 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 46:42] + node _T_922 = or(_T_921, reset) @[BaseTop.scala 46:42] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_924 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 46:42] + when _T_926 : @[BaseTop.scala 46:42] + node _T_929 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_931 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = and(_T_929, _T_937) @[Parameters.scala 132:56] + node _T_940 = or(UInt<1>("h00"), _T_938) @[Parameters.scala 134:30] + node _T_941 = or(_T_940, reset) @[BaseTop.scala 46:42] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_943 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_944 = or(_T_630, reset) @[BaseTop.scala 46:42] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_946 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_947 = or(_T_638, reset) @[BaseTop.scala 46:42] + node _T_949 = eq(_T_947, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_949 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_950 = eq(io.in[0].a.bits.mask, _T_706) @[BaseTop.scala 46:42] + node _T_951 = or(_T_950, reset) @[BaseTop.scala 46:42] + node _T_953 = eq(_T_951, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_953 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + when io.in[0].b.valid : @[BaseTop.scala 46:42] + node _T_955 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_956 = or(_T_955, reset) @[BaseTop.scala 46:42] + node _T_958 = eq(_T_956, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_958 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at BaseTop.scala:46:42)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_960 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_961 = cvt(_T_960) @[Parameters.scala 117:49] + node _T_963 = and(_T_961, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_964 = asSInt(_T_963) @[Parameters.scala 117:52] + node _T_966 = eq(_T_964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_969 : UInt<1>[1] @[Parameters.scala 110:36] + _T_969 is invalid @[Parameters.scala 110:36] + _T_969[0] <= _T_966 @[Parameters.scala 110:36] + node _T_974 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_975 = dshl(_T_974, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_976 = bits(_T_975, 5, 0) @[package.scala 19:76] + node _T_977 = not(_T_976) @[package.scala 19:40] + node _T_978 = and(io.in[0].b.bits.address, _T_977) @[Edges.scala 17:16] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_982 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_983 = dshl(UInt<1>("h01"), _T_982) @[OneHot.scala 49:12] + node _T_984 = bits(_T_983, 2, 0) @[OneHot.scala 49:37] + node _T_986 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_988 = bits(_T_984, 2, 2) @[package.scala 44:26] + node _T_989 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_991 = eq(_T_989, UInt<1>("h00")) @[package.scala 46:20] + node _T_992 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_993 = and(_T_988, _T_992) @[package.scala 50:38] + node _T_994 = or(_T_986, _T_993) @[package.scala 50:29] + node _T_995 = and(UInt<1>("h01"), _T_989) @[package.scala 49:27] + node _T_996 = and(_T_988, _T_995) @[package.scala 50:38] + node _T_997 = or(_T_986, _T_996) @[package.scala 50:29] + node _T_998 = bits(_T_984, 1, 1) @[package.scala 44:26] + node _T_999 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1001 = eq(_T_999, UInt<1>("h00")) @[package.scala 46:20] + node _T_1002 = and(_T_992, _T_1001) @[package.scala 49:27] + node _T_1003 = and(_T_998, _T_1002) @[package.scala 50:38] + node _T_1004 = or(_T_994, _T_1003) @[package.scala 50:29] + node _T_1005 = and(_T_992, _T_999) @[package.scala 49:27] + node _T_1006 = and(_T_998, _T_1005) @[package.scala 50:38] + node _T_1007 = or(_T_994, _T_1006) @[package.scala 50:29] + node _T_1008 = and(_T_995, _T_1001) @[package.scala 49:27] + node _T_1009 = and(_T_998, _T_1008) @[package.scala 50:38] + node _T_1010 = or(_T_997, _T_1009) @[package.scala 50:29] + node _T_1011 = and(_T_995, _T_999) @[package.scala 49:27] + node _T_1012 = and(_T_998, _T_1011) @[package.scala 50:38] + node _T_1013 = or(_T_997, _T_1012) @[package.scala 50:29] + node _T_1014 = bits(_T_984, 0, 0) @[package.scala 44:26] + node _T_1015 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1017 = eq(_T_1015, UInt<1>("h00")) @[package.scala 46:20] + node _T_1018 = and(_T_1002, _T_1017) @[package.scala 49:27] + node _T_1019 = and(_T_1014, _T_1018) @[package.scala 50:38] + node _T_1020 = or(_T_1004, _T_1019) @[package.scala 50:29] + node _T_1021 = and(_T_1002, _T_1015) @[package.scala 49:27] + node _T_1022 = and(_T_1014, _T_1021) @[package.scala 50:38] + node _T_1023 = or(_T_1004, _T_1022) @[package.scala 50:29] + node _T_1024 = and(_T_1005, _T_1017) @[package.scala 49:27] + node _T_1025 = and(_T_1014, _T_1024) @[package.scala 50:38] + node _T_1026 = or(_T_1007, _T_1025) @[package.scala 50:29] + node _T_1027 = and(_T_1005, _T_1015) @[package.scala 49:27] + node _T_1028 = and(_T_1014, _T_1027) @[package.scala 50:38] + node _T_1029 = or(_T_1007, _T_1028) @[package.scala 50:29] + node _T_1030 = and(_T_1008, _T_1017) @[package.scala 49:27] + node _T_1031 = and(_T_1014, _T_1030) @[package.scala 50:38] + node _T_1032 = or(_T_1010, _T_1031) @[package.scala 50:29] + node _T_1033 = and(_T_1008, _T_1015) @[package.scala 49:27] + node _T_1034 = and(_T_1014, _T_1033) @[package.scala 50:38] + node _T_1035 = or(_T_1010, _T_1034) @[package.scala 50:29] + node _T_1036 = and(_T_1011, _T_1017) @[package.scala 49:27] + node _T_1037 = and(_T_1014, _T_1036) @[package.scala 50:38] + node _T_1038 = or(_T_1013, _T_1037) @[package.scala 50:29] + node _T_1039 = and(_T_1011, _T_1015) @[package.scala 49:27] + node _T_1040 = and(_T_1014, _T_1039) @[package.scala 50:38] + node _T_1041 = or(_T_1013, _T_1040) @[package.scala 50:29] + node _T_1042 = cat(_T_1023, _T_1020) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1029, _T_1026) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1035, _T_1032) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1041, _T_1038) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1050 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + when _T_1050 : @[BaseTop.scala 46:42] + node _T_1052 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1053 = not(_T_1052) @[Parameters.scala 37:9] + node _T_1055 = or(_T_1053, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1056 = not(_T_1055) @[Parameters.scala 37:7] + node _T_1058 = eq(_T_1056, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1060 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1062 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1065 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1065 is invalid @[Parameters.scala 228:27] + _T_1065[0] <= _T_1058 @[Parameters.scala 228:27] + _T_1065[1] <= _T_1060 @[Parameters.scala 228:27] + _T_1065[2] <= _T_1062 @[Parameters.scala 228:27] + node _T_1073 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1075 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1076 = and(_T_1073, _T_1075) @[Parameters.scala 63:37] + node _T_1079 = mux(_T_1065[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1081 = mux(_T_1065[1], _T_1076, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1083 = mux(_T_1065[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1085 = or(_T_1079, _T_1081) @[Mux.scala 19:72] + node _T_1086 = or(_T_1085, _T_1083) @[Mux.scala 19:72] + wire _T_1088 : UInt<1> @[Mux.scala 19:72] + _T_1088 is invalid @[Mux.scala 19:72] + _T_1088 <= _T_1086 @[Mux.scala 19:72] + node _T_1089 = or(_T_1088, reset) @[BaseTop.scala 46:42] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1091 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1092 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1094 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1096 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1097 = or(_T_1096, reset) @[BaseTop.scala 46:42] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1099 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1100 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1102 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1104 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1105 = or(_T_1104, reset) @[BaseTop.scala 46:42] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1107 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BaseTop.scala:46:42)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1108 = not(io.in[0].b.bits.mask) @[BaseTop.scala 46:42] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1111 = or(_T_1110, reset) @[BaseTop.scala 46:42] + node _T_1113 = eq(_T_1111, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1113 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1115 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 46:42] + when _T_1115 : @[BaseTop.scala 46:42] + node _T_1117 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1119 = eq(_T_1117, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1119 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1120 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1122 = eq(_T_1120, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1122 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1123 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1125 = eq(_T_1123, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1125 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1127 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1128 = or(_T_1127, reset) @[BaseTop.scala 46:42] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1130 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1131 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 46:42] + node _T_1132 = or(_T_1131, reset) @[BaseTop.scala 46:42] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1134 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1136 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1136 : @[BaseTop.scala 46:42] + node _T_1138 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1140 = eq(_T_1138, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1140 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1141 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1143 = eq(_T_1141, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1143 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1144 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1146 = eq(_T_1144, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1146 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1148 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1149 = or(_T_1148, reset) @[BaseTop.scala 46:42] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1151 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1152 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 46:42] + node _T_1153 = or(_T_1152, reset) @[BaseTop.scala 46:42] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1155 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1157 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 46:42] + when _T_1157 : @[BaseTop.scala 46:42] + node _T_1159 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1161 = eq(_T_1159, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1161 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1162 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1164 = eq(_T_1162, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1164 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1165 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1167 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1169 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1170 = or(_T_1169, reset) @[BaseTop.scala 46:42] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1172 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1173 = not(_T_1048) @[BaseTop.scala 46:42] + node _T_1174 = and(io.in[0].b.bits.mask, _T_1173) @[BaseTop.scala 46:42] + node _T_1176 = eq(_T_1174, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1177 = or(_T_1176, reset) @[BaseTop.scala 46:42] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1179 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1181 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 46:42] + when _T_1181 : @[BaseTop.scala 46:42] + node _T_1183 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1185 = eq(_T_1183, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1185 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1186 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1188 = eq(_T_1186, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1188 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1189 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1191 = eq(_T_1189, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1191 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1193 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1194 = or(_T_1193, reset) @[BaseTop.scala 46:42] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1196 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:46:42)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1197 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 46:42] + node _T_1198 = or(_T_1197, reset) @[BaseTop.scala 46:42] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1200 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1202 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 46:42] + when _T_1202 : @[BaseTop.scala 46:42] + node _T_1204 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1206 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1207 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1209 = eq(_T_1207, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1209 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1210 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1212 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1214 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1215 = or(_T_1214, reset) @[BaseTop.scala 46:42] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1217 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at BaseTop.scala:46:42)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1218 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 46:42] + node _T_1219 = or(_T_1218, reset) @[BaseTop.scala 46:42] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1221 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1223 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 46:42] + when _T_1223 : @[BaseTop.scala 46:42] + node _T_1225 = or(UInt<1>("h00"), reset) @[BaseTop.scala 46:42] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1227 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at BaseTop.scala:46:42)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1228 = or(_T_969[0], reset) @[BaseTop.scala 46:42] + node _T_1230 = eq(_T_1228, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1230 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1231 = or(_T_980, reset) @[BaseTop.scala 46:42] + node _T_1233 = eq(_T_1231, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1233 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1234 = eq(io.in[0].b.bits.mask, _T_1048) @[BaseTop.scala 46:42] + node _T_1235 = or(_T_1234, reset) @[BaseTop.scala 46:42] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1237 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at BaseTop.scala:46:42)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + when io.in[0].c.valid : @[BaseTop.scala 46:42] + node _T_1239 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1240 = or(_T_1239, reset) @[BaseTop.scala 46:42] + node _T_1242 = eq(_T_1240, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1242 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at BaseTop.scala:46:42)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1244 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1245 = not(_T_1244) @[Parameters.scala 37:9] + node _T_1247 = or(_T_1245, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1248 = not(_T_1247) @[Parameters.scala 37:7] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1252 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1254 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1257 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1257 is invalid @[Parameters.scala 228:27] + _T_1257[0] <= _T_1250 @[Parameters.scala 228:27] + _T_1257[1] <= _T_1252 @[Parameters.scala 228:27] + _T_1257[2] <= _T_1254 @[Parameters.scala 228:27] + node _T_1263 = or(_T_1257[0], _T_1257[1]) @[Parameters.scala 229:46] + node _T_1264 = or(_T_1263, _T_1257[2]) @[Parameters.scala 229:46] + node _T_1266 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1267 = dshl(_T_1266, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1268 = bits(_T_1267, 5, 0) @[package.scala 19:76] + node _T_1269 = not(_T_1268) @[package.scala 19:40] + node _T_1270 = and(io.in[0].c.bits.address, _T_1269) @[Edges.scala 17:16] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1274 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1275 = cvt(_T_1274) @[Parameters.scala 117:49] + node _T_1277 = and(_T_1275, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1278 = asSInt(_T_1277) @[Parameters.scala 117:52] + node _T_1280 = eq(_T_1278, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1283 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1283 is invalid @[Parameters.scala 110:36] + _T_1283[0] <= _T_1280 @[Parameters.scala 110:36] + node _T_1288 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 46:42] + when _T_1288 : @[BaseTop.scala 46:42] + node _T_1289 = or(_T_1283[0], reset) @[BaseTop.scala 46:42] + node _T_1291 = eq(_T_1289, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1291 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1292 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1294 = eq(_T_1292, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1294 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1296 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1297 = or(_T_1296, reset) @[BaseTop.scala 46:42] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1299 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1300 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1302 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1304 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1305 = or(_T_1304, reset) @[BaseTop.scala 46:42] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1307 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BaseTop.scala:46:42)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1309 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1310 = or(_T_1309, reset) @[BaseTop.scala 46:42] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1312 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1314 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 46:42] + when _T_1314 : @[BaseTop.scala 46:42] + node _T_1315 = or(_T_1283[0], reset) @[BaseTop.scala 46:42] + node _T_1317 = eq(_T_1315, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1317 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1318 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1320 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1322 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1323 = or(_T_1322, reset) @[BaseTop.scala 46:42] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1325 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1326 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1328 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1330 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1331 = or(_T_1330, reset) @[BaseTop.scala 46:42] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1333 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BaseTop.scala:46:42)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1335 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1336 = or(_T_1335, reset) @[BaseTop.scala 46:42] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1338 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1340 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + when _T_1340 : @[BaseTop.scala 46:42] + node _T_1343 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1345 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1346 = cvt(_T_1345) @[Parameters.scala 117:49] + node _T_1348 = and(_T_1346, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1349 = asSInt(_T_1348) @[Parameters.scala 117:52] + node _T_1351 = eq(_T_1349, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1352 = and(_T_1343, _T_1351) @[Parameters.scala 132:56] + node _T_1354 = or(UInt<1>("h00"), _T_1352) @[Parameters.scala 134:30] + node _T_1355 = or(_T_1354, reset) @[BaseTop.scala 46:42] + node _T_1357 = eq(_T_1355, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1357 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1358 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1360 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1362 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1363 = or(_T_1362, reset) @[BaseTop.scala 46:42] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1365 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1366 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1368 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1370 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1371 = or(_T_1370, reset) @[BaseTop.scala 46:42] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1373 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at BaseTop.scala:46:42)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1375 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1376 = or(_T_1375, reset) @[BaseTop.scala 46:42] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1378 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1380 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[BaseTop.scala 46:42] + when _T_1380 : @[BaseTop.scala 46:42] + node _T_1383 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1385 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1386 = cvt(_T_1385) @[Parameters.scala 117:49] + node _T_1388 = and(_T_1386, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1389 = asSInt(_T_1388) @[Parameters.scala 117:52] + node _T_1391 = eq(_T_1389, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1392 = and(_T_1383, _T_1391) @[Parameters.scala 132:56] + node _T_1394 = or(UInt<1>("h00"), _T_1392) @[Parameters.scala 134:30] + node _T_1395 = or(_T_1394, reset) @[BaseTop.scala 46:42] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1397 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BaseTop.scala:46:42)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1398 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1400 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1402 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1403 = or(_T_1402, reset) @[BaseTop.scala 46:42] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1405 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1406 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1408 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1410 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1411 = or(_T_1410, reset) @[BaseTop.scala 46:42] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1413 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at BaseTop.scala:46:42)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1415 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1416 = or(_T_1415, reset) @[BaseTop.scala 46:42] + node _T_1418 = eq(_T_1416, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1418 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1420 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1420 : @[BaseTop.scala 46:42] + node _T_1421 = or(_T_1283[0], reset) @[BaseTop.scala 46:42] + node _T_1423 = eq(_T_1421, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1423 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1424 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1426 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1427 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1429 = eq(_T_1427, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1429 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1431 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1432 = or(_T_1431, reset) @[BaseTop.scala 46:42] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1434 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1436 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 46:42] + when _T_1436 : @[BaseTop.scala 46:42] + node _T_1437 = or(_T_1283[0], reset) @[BaseTop.scala 46:42] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1439 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1440 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1442 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1443 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1445 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1447 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1448 = or(_T_1447, reset) @[BaseTop.scala 46:42] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1450 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1452 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 46:42] + when _T_1452 : @[BaseTop.scala 46:42] + node _T_1453 = or(_T_1283[0], reset) @[BaseTop.scala 46:42] + node _T_1455 = eq(_T_1453, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1455 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BaseTop.scala:46:42)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1456 = or(_T_1264, reset) @[BaseTop.scala 46:42] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1458 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1459 = or(_T_1272, reset) @[BaseTop.scala 46:42] + node _T_1461 = eq(_T_1459, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1461 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1463 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1464 = or(_T_1463, reset) @[BaseTop.scala 46:42] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1466 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1468 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1469 = or(_T_1468, reset) @[BaseTop.scala 46:42] + node _T_1471 = eq(_T_1469, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1471 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + when io.in[0].d.valid : @[BaseTop.scala 46:42] + node _T_1473 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1474 = or(_T_1473, reset) @[BaseTop.scala 46:42] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1476 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at BaseTop.scala:46:42)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1478 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1479 = not(_T_1478) @[Parameters.scala 37:9] + node _T_1481 = or(_T_1479, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1482 = not(_T_1481) @[Parameters.scala 37:7] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1486 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1488 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1491 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1491 is invalid @[Parameters.scala 228:27] + _T_1491[0] <= _T_1484 @[Parameters.scala 228:27] + _T_1491[1] <= _T_1486 @[Parameters.scala 228:27] + _T_1491[2] <= _T_1488 @[Parameters.scala 228:27] + node _T_1497 = or(_T_1491[0], _T_1491[1]) @[Parameters.scala 229:46] + node _T_1498 = or(_T_1497, _T_1491[2]) @[Parameters.scala 229:46] + node _T_1500 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1501 = dshl(_T_1500, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1502 = bits(_T_1501, 5, 0) @[package.scala 19:76] + node _T_1503 = not(_T_1502) @[package.scala 19:40] + node _T_1504 = and(io.in[0].d.bits.addr_lo, _T_1503) @[Edges.scala 17:16] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1508 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[BaseTop.scala 46:42] + node _T_1510 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + when _T_1510 : @[BaseTop.scala 46:42] + node _T_1511 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1513 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1514 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1516 = eq(_T_1514, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1516 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1517 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1519 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1521 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1522 = or(_T_1521, reset) @[BaseTop.scala 46:42] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1524 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1526 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1527 = or(_T_1526, reset) @[BaseTop.scala 46:42] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1529 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1531 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1532 = or(_T_1531, reset) @[BaseTop.scala 46:42] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1534 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1536 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 46:42] + when _T_1536 : @[BaseTop.scala 46:42] + node _T_1537 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1539 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1540 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1542 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1543 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1545 = eq(_T_1543, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1545 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1547 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1548 = or(_T_1547, reset) @[BaseTop.scala 46:42] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1550 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1552 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1553 = or(_T_1552, reset) @[BaseTop.scala 46:42] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1555 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BaseTop.scala:46:42)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1557 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 46:42] + when _T_1557 : @[BaseTop.scala 46:42] + node _T_1558 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1560 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1561 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1563 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1564 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1566 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1568 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseTop.scala 46:42] + node _T_1569 = or(_T_1568, reset) @[BaseTop.scala 46:42] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1571 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BaseTop.scala:46:42)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1573 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1574 = or(_T_1573, reset) @[BaseTop.scala 46:42] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1576 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BaseTop.scala:46:42)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1578 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1578 : @[BaseTop.scala 46:42] + node _T_1579 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1581 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1582 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1584 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1585 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1587 = eq(_T_1585, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1587 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1589 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1590 = or(_T_1589, reset) @[BaseTop.scala 46:42] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1592 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1594 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 46:42] + when _T_1594 : @[BaseTop.scala 46:42] + node _T_1595 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1597 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1598 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1600 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1601 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1603 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1605 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1606 = or(_T_1605, reset) @[BaseTop.scala 46:42] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1608 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1610 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 46:42] + when _T_1610 : @[BaseTop.scala 46:42] + node _T_1611 = or(_T_1498, reset) @[BaseTop.scala 46:42] + node _T_1613 = eq(_T_1611, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1613 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1614 = or(_T_1506, reset) @[BaseTop.scala 46:42] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1616 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at BaseTop.scala:46:42)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1617 = or(_T_1508, reset) @[BaseTop.scala 46:42] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1619 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1621 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1622 = or(_T_1621, reset) @[BaseTop.scala 46:42] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1624 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at BaseTop.scala:46:42)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1626 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1627 = or(_T_1626, reset) @[BaseTop.scala 46:42] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1629 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at BaseTop.scala:46:42)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + when io.in[0].e.valid : @[BaseTop.scala 46:42] + node _T_1631 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[BaseTop.scala 46:42] + node _T_1632 = or(_T_1631, reset) @[BaseTop.scala 46:42] + node _T_1634 = eq(_T_1632, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1634 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1635 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1637 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1638 = dshl(_T_1637, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1639 = bits(_T_1638, 5, 0) @[package.scala 19:76] + node _T_1640 = not(_T_1639) @[package.scala 19:40] + node _T_1641 = shr(_T_1640, 3) @[Edges.scala 198:59] + node _T_1642 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1647 = mux(UInt<1>("h00"), _T_1641, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1649 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1651 = sub(_T_1649, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1652 = asUInt(_T_1651) @[Edges.scala 208:28] + node _T_1653 = tail(_T_1652, 1) @[Edges.scala 208:28] + node _T_1655 = eq(_T_1649, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1657 = eq(_T_1649, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1659 = eq(_T_1647, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1660 = or(_T_1657, _T_1659) @[Edges.scala 210:37] + node _T_1661 = and(_T_1660, _T_1635) @[Edges.scala 211:22] + node _T_1662 = not(_T_1653) @[Edges.scala 212:27] + node _T_1663 = and(_T_1647, _T_1662) @[Edges.scala 212:25] + when _T_1635 : @[Edges.scala 213:17] + node _T_1664 = mux(_T_1655, _T_1647, _T_1653) @[Edges.scala 214:21] + _T_1649 <= _T_1664 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1666 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1668 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1670 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1672 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1674 : UInt, clock @[BaseTop.scala 46:42] + node _T_1676 = eq(_T_1655, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1677 = and(io.in[0].a.valid, _T_1676) @[BaseTop.scala 46:42] + when _T_1677 : @[BaseTop.scala 46:42] + node _T_1678 = eq(io.in[0].a.bits.opcode, _T_1666) @[BaseTop.scala 46:42] + node _T_1679 = or(_T_1678, reset) @[BaseTop.scala 46:42] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1681 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1682 = eq(io.in[0].a.bits.param, _T_1668) @[BaseTop.scala 46:42] + node _T_1683 = or(_T_1682, reset) @[BaseTop.scala 46:42] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1685 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1686 = eq(io.in[0].a.bits.size, _T_1670) @[BaseTop.scala 46:42] + node _T_1687 = or(_T_1686, reset) @[BaseTop.scala 46:42] + node _T_1689 = eq(_T_1687, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1689 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1690 = eq(io.in[0].a.bits.source, _T_1672) @[BaseTop.scala 46:42] + node _T_1691 = or(_T_1690, reset) @[BaseTop.scala 46:42] + node _T_1693 = eq(_T_1691, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1693 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1694 = eq(io.in[0].a.bits.address, _T_1674) @[BaseTop.scala 46:42] + node _T_1695 = or(_T_1694, reset) @[BaseTop.scala 46:42] + node _T_1697 = eq(_T_1695, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1697 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1698 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1699 = and(_T_1698, _T_1655) @[BaseTop.scala 46:42] + when _T_1699 : @[BaseTop.scala 46:42] + _T_1666 <= io.in[0].a.bits.opcode @[BaseTop.scala 46:42] + _T_1668 <= io.in[0].a.bits.param @[BaseTop.scala 46:42] + _T_1670 <= io.in[0].a.bits.size @[BaseTop.scala 46:42] + _T_1672 <= io.in[0].a.bits.source @[BaseTop.scala 46:42] + _T_1674 <= io.in[0].a.bits.address @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1700 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1702 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1703 = dshl(_T_1702, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1704 = bits(_T_1703, 5, 0) @[package.scala 19:76] + node _T_1705 = not(_T_1704) @[package.scala 19:40] + node _T_1706 = shr(_T_1705, 3) @[Edges.scala 198:59] + node _T_1707 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1709 = eq(_T_1707, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1712 = mux(UInt<1>("h00"), _T_1706, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1714 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1716 = sub(_T_1714, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1717 = asUInt(_T_1716) @[Edges.scala 208:28] + node _T_1718 = tail(_T_1717, 1) @[Edges.scala 208:28] + node _T_1720 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1722 = eq(_T_1714, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1724 = eq(_T_1712, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1725 = or(_T_1722, _T_1724) @[Edges.scala 210:37] + node _T_1726 = and(_T_1725, _T_1700) @[Edges.scala 211:22] + node _T_1727 = not(_T_1718) @[Edges.scala 212:27] + node _T_1728 = and(_T_1712, _T_1727) @[Edges.scala 212:25] + when _T_1700 : @[Edges.scala 213:17] + node _T_1729 = mux(_T_1720, _T_1712, _T_1718) @[Edges.scala 214:21] + _T_1714 <= _T_1729 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1731 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1733 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1735 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1737 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1739 : UInt, clock @[BaseTop.scala 46:42] + node _T_1741 = eq(_T_1720, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1742 = and(io.in[0].b.valid, _T_1741) @[BaseTop.scala 46:42] + when _T_1742 : @[BaseTop.scala 46:42] + node _T_1743 = eq(io.in[0].b.bits.opcode, _T_1731) @[BaseTop.scala 46:42] + node _T_1744 = or(_T_1743, reset) @[BaseTop.scala 46:42] + node _T_1746 = eq(_T_1744, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1746 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1747 = eq(io.in[0].b.bits.param, _T_1733) @[BaseTop.scala 46:42] + node _T_1748 = or(_T_1747, reset) @[BaseTop.scala 46:42] + node _T_1750 = eq(_T_1748, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1750 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1751 = eq(io.in[0].b.bits.size, _T_1735) @[BaseTop.scala 46:42] + node _T_1752 = or(_T_1751, reset) @[BaseTop.scala 46:42] + node _T_1754 = eq(_T_1752, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1754 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1755 = eq(io.in[0].b.bits.source, _T_1737) @[BaseTop.scala 46:42] + node _T_1756 = or(_T_1755, reset) @[BaseTop.scala 46:42] + node _T_1758 = eq(_T_1756, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1758 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1759 = eq(io.in[0].b.bits.address, _T_1739) @[BaseTop.scala 46:42] + node _T_1760 = or(_T_1759, reset) @[BaseTop.scala 46:42] + node _T_1762 = eq(_T_1760, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1762 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1763 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1764 = and(_T_1763, _T_1720) @[BaseTop.scala 46:42] + when _T_1764 : @[BaseTop.scala 46:42] + _T_1731 <= io.in[0].b.bits.opcode @[BaseTop.scala 46:42] + _T_1733 <= io.in[0].b.bits.param @[BaseTop.scala 46:42] + _T_1735 <= io.in[0].b.bits.size @[BaseTop.scala 46:42] + _T_1737 <= io.in[0].b.bits.source @[BaseTop.scala 46:42] + _T_1739 <= io.in[0].b.bits.address @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1765 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1767 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1768 = dshl(_T_1767, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1769 = bits(_T_1768, 5, 0) @[package.scala 19:76] + node _T_1770 = not(_T_1769) @[package.scala 19:40] + node _T_1771 = shr(_T_1770, 3) @[Edges.scala 198:59] + node _T_1772 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1774 = mux(_T_1772, _T_1771, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1776 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1778 = sub(_T_1776, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1779 = asUInt(_T_1778) @[Edges.scala 208:28] + node _T_1780 = tail(_T_1779, 1) @[Edges.scala 208:28] + node _T_1782 = eq(_T_1776, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1784 = eq(_T_1776, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1786 = eq(_T_1774, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1787 = or(_T_1784, _T_1786) @[Edges.scala 210:37] + node _T_1788 = and(_T_1787, _T_1765) @[Edges.scala 211:22] + node _T_1789 = not(_T_1780) @[Edges.scala 212:27] + node _T_1790 = and(_T_1774, _T_1789) @[Edges.scala 212:25] + when _T_1765 : @[Edges.scala 213:17] + node _T_1791 = mux(_T_1782, _T_1774, _T_1780) @[Edges.scala 214:21] + _T_1776 <= _T_1791 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1793 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1795 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1797 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1799 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1801 : UInt, clock @[BaseTop.scala 46:42] + node _T_1803 = eq(_T_1782, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1804 = and(io.in[0].c.valid, _T_1803) @[BaseTop.scala 46:42] + when _T_1804 : @[BaseTop.scala 46:42] + node _T_1805 = eq(io.in[0].c.bits.opcode, _T_1793) @[BaseTop.scala 46:42] + node _T_1806 = or(_T_1805, reset) @[BaseTop.scala 46:42] + node _T_1808 = eq(_T_1806, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1808 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1809 = eq(io.in[0].c.bits.param, _T_1795) @[BaseTop.scala 46:42] + node _T_1810 = or(_T_1809, reset) @[BaseTop.scala 46:42] + node _T_1812 = eq(_T_1810, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1812 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1813 = eq(io.in[0].c.bits.size, _T_1797) @[BaseTop.scala 46:42] + node _T_1814 = or(_T_1813, reset) @[BaseTop.scala 46:42] + node _T_1816 = eq(_T_1814, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1816 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1817 = eq(io.in[0].c.bits.source, _T_1799) @[BaseTop.scala 46:42] + node _T_1818 = or(_T_1817, reset) @[BaseTop.scala 46:42] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1820 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1821 = eq(io.in[0].c.bits.address, _T_1801) @[BaseTop.scala 46:42] + node _T_1822 = or(_T_1821, reset) @[BaseTop.scala 46:42] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1824 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1825 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1826 = and(_T_1825, _T_1782) @[BaseTop.scala 46:42] + when _T_1826 : @[BaseTop.scala 46:42] + _T_1793 <= io.in[0].c.bits.opcode @[BaseTop.scala 46:42] + _T_1795 <= io.in[0].c.bits.param @[BaseTop.scala 46:42] + _T_1797 <= io.in[0].c.bits.size @[BaseTop.scala 46:42] + _T_1799 <= io.in[0].c.bits.source @[BaseTop.scala 46:42] + _T_1801 <= io.in[0].c.bits.address @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1827 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1829 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1830 = dshl(_T_1829, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1831 = bits(_T_1830, 5, 0) @[package.scala 19:76] + node _T_1832 = not(_T_1831) @[package.scala 19:40] + node _T_1833 = shr(_T_1832, 3) @[Edges.scala 198:59] + node _T_1834 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1837 = mux(UInt<1>("h01"), _T_1833, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1839 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1841 = sub(_T_1839, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1842 = asUInt(_T_1841) @[Edges.scala 208:28] + node _T_1843 = tail(_T_1842, 1) @[Edges.scala 208:28] + node _T_1845 = eq(_T_1839, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1847 = eq(_T_1839, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1849 = eq(_T_1837, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1850 = or(_T_1847, _T_1849) @[Edges.scala 210:37] + node _T_1851 = and(_T_1850, _T_1827) @[Edges.scala 211:22] + node _T_1852 = not(_T_1843) @[Edges.scala 212:27] + node _T_1853 = and(_T_1837, _T_1852) @[Edges.scala 212:25] + when _T_1827 : @[Edges.scala 213:17] + node _T_1854 = mux(_T_1845, _T_1837, _T_1843) @[Edges.scala 214:21] + _T_1839 <= _T_1854 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1856 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1858 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1860 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1862 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1864 : UInt, clock @[BaseTop.scala 46:42] + reg _T_1866 : UInt, clock @[BaseTop.scala 46:42] + node _T_1868 = eq(_T_1845, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1869 = and(io.in[0].d.valid, _T_1868) @[BaseTop.scala 46:42] + when _T_1869 : @[BaseTop.scala 46:42] + node _T_1870 = eq(io.in[0].d.bits.opcode, _T_1856) @[BaseTop.scala 46:42] + node _T_1871 = or(_T_1870, reset) @[BaseTop.scala 46:42] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1873 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1874 = eq(io.in[0].d.bits.param, _T_1858) @[BaseTop.scala 46:42] + node _T_1875 = or(_T_1874, reset) @[BaseTop.scala 46:42] + node _T_1877 = eq(_T_1875, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1877 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1878 = eq(io.in[0].d.bits.size, _T_1860) @[BaseTop.scala 46:42] + node _T_1879 = or(_T_1878, reset) @[BaseTop.scala 46:42] + node _T_1881 = eq(_T_1879, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1881 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1882 = eq(io.in[0].d.bits.source, _T_1862) @[BaseTop.scala 46:42] + node _T_1883 = or(_T_1882, reset) @[BaseTop.scala 46:42] + node _T_1885 = eq(_T_1883, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1885 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1886 = eq(io.in[0].d.bits.sink, _T_1864) @[BaseTop.scala 46:42] + node _T_1887 = or(_T_1886, reset) @[BaseTop.scala 46:42] + node _T_1889 = eq(_T_1887, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1889 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1890 = eq(io.in[0].d.bits.addr_lo, _T_1866) @[BaseTop.scala 46:42] + node _T_1891 = or(_T_1890, reset) @[BaseTop.scala 46:42] + node _T_1893 = eq(_T_1891, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1893 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at BaseTop.scala:46:42)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1894 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1895 = and(_T_1894, _T_1845) @[BaseTop.scala 46:42] + when _T_1895 : @[BaseTop.scala 46:42] + _T_1856 <= io.in[0].d.bits.opcode @[BaseTop.scala 46:42] + _T_1858 <= io.in[0].d.bits.param @[BaseTop.scala 46:42] + _T_1860 <= io.in[0].d.bits.size @[BaseTop.scala 46:42] + _T_1862 <= io.in[0].d.bits.source @[BaseTop.scala 46:42] + _T_1864 <= io.in[0].d.bits.sink @[BaseTop.scala 46:42] + _T_1866 <= io.in[0].d.bits.addr_lo @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + reg _T_1897 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1898 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1900 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1901 = dshl(_T_1900, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1902 = bits(_T_1901, 5, 0) @[package.scala 19:76] + node _T_1903 = not(_T_1902) @[package.scala 19:40] + node _T_1904 = shr(_T_1903, 3) @[Edges.scala 198:59] + node _T_1905 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1907 = eq(_T_1905, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1910 = mux(UInt<1>("h00"), _T_1904, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1912 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1914 = sub(_T_1912, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1915 = asUInt(_T_1914) @[Edges.scala 208:28] + node _T_1916 = tail(_T_1915, 1) @[Edges.scala 208:28] + node _T_1918 = eq(_T_1912, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1920 = eq(_T_1912, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1922 = eq(_T_1910, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1923 = or(_T_1920, _T_1922) @[Edges.scala 210:37] + node _T_1924 = and(_T_1923, _T_1898) @[Edges.scala 211:22] + node _T_1925 = not(_T_1916) @[Edges.scala 212:27] + node _T_1926 = and(_T_1910, _T_1925) @[Edges.scala 212:25] + when _T_1898 : @[Edges.scala 213:17] + node _T_1927 = mux(_T_1918, _T_1910, _T_1916) @[Edges.scala 214:21] + _T_1912 <= _T_1927 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1928 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1930 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1931 = dshl(_T_1930, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1932 = bits(_T_1931, 5, 0) @[package.scala 19:76] + node _T_1933 = not(_T_1932) @[package.scala 19:40] + node _T_1934 = shr(_T_1933, 3) @[Edges.scala 198:59] + node _T_1935 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1938 = mux(UInt<1>("h01"), _T_1934, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1940 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1942 = sub(_T_1940, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1943 = asUInt(_T_1942) @[Edges.scala 208:28] + node _T_1944 = tail(_T_1943, 1) @[Edges.scala 208:28] + node _T_1946 = eq(_T_1940, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1948 = eq(_T_1940, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1950 = eq(_T_1938, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1951 = or(_T_1948, _T_1950) @[Edges.scala 210:37] + node _T_1952 = and(_T_1951, _T_1928) @[Edges.scala 211:22] + node _T_1953 = not(_T_1944) @[Edges.scala 212:27] + node _T_1954 = and(_T_1938, _T_1953) @[Edges.scala 212:25] + when _T_1928 : @[Edges.scala 213:17] + node _T_1955 = mux(_T_1946, _T_1938, _T_1944) @[Edges.scala 214:21] + _T_1940 <= _T_1955 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1957 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + node _T_1958 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[BaseTop.scala 46:42] + node _T_1959 = or(_T_1957, _T_1958) @[BaseTop.scala 46:42] + node _T_1961 = eq(io.in[0].a.valid, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1962 = or(_T_1959, _T_1961) @[BaseTop.scala 46:42] + node _T_1964 = eq(io.in[0].d.valid, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1965 = or(_T_1962, _T_1964) @[BaseTop.scala 46:42] + node _T_1966 = or(_T_1965, reset) @[BaseTop.scala 46:42] + node _T_1968 = eq(_T_1966, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1968 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BaseTop.scala:46:42)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + wire _T_1970 : UInt<6> + _T_1970 is invalid + _T_1970 <= UInt<6>("h00") + node _T_1971 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1971 : @[BaseTop.scala 46:42] + when _T_1923 : @[BaseTop.scala 46:42] + node _T_1973 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1970 <= _T_1973 @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1974 = dshr(_T_1897, io.in[0].a.bits.source) @[BaseTop.scala 46:42] + node _T_1975 = bits(_T_1974, 0, 0) @[BaseTop.scala 46:42] + node _T_1977 = eq(_T_1975, UInt<1>("h00")) @[BaseTop.scala 46:42] + node _T_1978 = or(_T_1977, reset) @[BaseTop.scala 46:42] + node _T_1980 = eq(_T_1978, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1980 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at BaseTop.scala:46:42)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + wire _T_1982 : UInt<6> + _T_1982 is invalid + _T_1982 <= UInt<6>("h00") + node _T_1983 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1985 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 46:42] + node _T_1986 = and(_T_1983, _T_1985) @[BaseTop.scala 46:42] + when _T_1986 : @[BaseTop.scala 46:42] + when _T_1951 : @[BaseTop.scala 46:42] + node _T_1988 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1982 <= _T_1988 @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1989 = or(_T_1970, _T_1897) @[BaseTop.scala 46:42] + node _T_1990 = dshr(_T_1989, io.in[0].d.bits.source) @[BaseTop.scala 46:42] + node _T_1991 = bits(_T_1990, 0, 0) @[BaseTop.scala 46:42] + node _T_1992 = or(_T_1991, reset) @[BaseTop.scala 46:42] + node _T_1994 = eq(_T_1992, UInt<1>("h00")) @[BaseTop.scala 46:42] + when _T_1994 : @[BaseTop.scala 46:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BaseTop.scala:46:42)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[BaseTop.scala 46:42] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + skip @[BaseTop.scala 46:42] + node _T_1995 = or(_T_1897, _T_1970) @[BaseTop.scala 46:42] + node _T_1996 = not(_T_1982) @[BaseTop.scala 46:42] + node _T_1997 = and(_T_1995, _T_1996) @[BaseTop.scala 46:42] + _T_1897 <= _T_1997 @[BaseTop.scala 46:42] module Queue_2 : - input clk : Clock + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2] - reg T_1115 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1117 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1115, T_1117) - node T_1122 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1122) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1128 = and(io.enq.ready, io.enq.valid) - node T_1130 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1128, T_1130) - node T_1132 = and(io.deq.ready, io.deq.valid) - node T_1134 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1132, T_1134) - when do_enq : - infer mport T_1136 = ram[T_1115], clk - T_1136 <- io.enq.bits - node T_1259 = eq(T_1115, UInt<1>("h01")) - node T_1261 = and(UInt<1>("h00"), T_1259) - node T_1264 = add(T_1115, UInt<1>("h01")) - node T_1265 = tail(T_1264, 1) - node T_1266 = mux(T_1261, UInt<1>("h00"), T_1265) - T_1115 <= T_1266 - skip - when do_deq : - node T_1268 = eq(T_1117, UInt<1>("h01")) - node T_1270 = and(UInt<1>("h00"), T_1268) - node T_1273 = add(T_1117, UInt<1>("h01")) - node T_1274 = tail(T_1273, 1) - node T_1275 = mux(T_1270, UInt<1>("h00"), T_1274) - T_1117 <= T_1275 - skip - node T_1276 = neq(do_enq, do_deq) - when T_1276 : - maybe_full <= do_enq - skip - node T_1278 = eq(empty, UInt<1>("h00")) - node T_1280 = and(UInt<1>("h00"), io.enq.valid) - node T_1281 = or(T_1278, T_1280) - io.deq.valid <= T_1281 - node T_1283 = eq(full, UInt<1>("h00")) - node T_1285 = and(UInt<1>("h00"), io.deq.ready) - node T_1286 = or(T_1283, T_1285) - io.enq.ready <= T_1286 - infer mport T_1287 = ram[T_1117], clk - node T_1409 = mux(maybe_flow, io.enq.bits, T_1287) - io.deq.bits <- T_1409 - node T_1531 = sub(T_1115, T_1117) - node ptr_diff = tail(T_1531, 1) - node T_1533 = and(maybe_full, ptr_match) - node T_1534 = cat(T_1533, ptr_diff) - io.count <= T_1534 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] module Queue_3 : - input clk : Clock + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<2>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2] - reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1151, T_1153) - node T_1158 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1158) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1164 = and(io.enq.ready, io.enq.valid) - node T_1166 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1164, T_1166) - node T_1168 = and(io.deq.ready, io.deq.valid) - node T_1170 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1168, T_1170) - when do_enq : - infer mport T_1172 = ram[T_1151], clk - T_1172 <- io.enq.bits - node T_1299 = eq(T_1151, UInt<1>("h01")) - node T_1301 = and(UInt<1>("h00"), T_1299) - node T_1304 = add(T_1151, UInt<1>("h01")) - node T_1305 = tail(T_1304, 1) - node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305) - T_1151 <= T_1306 - skip - when do_deq : - node T_1308 = eq(T_1153, UInt<1>("h01")) - node T_1310 = and(UInt<1>("h00"), T_1308) - node T_1313 = add(T_1153, UInt<1>("h01")) - node T_1314 = tail(T_1313, 1) - node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314) - T_1153 <= T_1315 - skip - node T_1316 = neq(do_enq, do_deq) - when T_1316 : - maybe_full <= do_enq - skip - node T_1318 = eq(empty, UInt<1>("h00")) - node T_1320 = and(UInt<1>("h00"), io.enq.valid) - node T_1321 = or(T_1318, T_1320) - io.deq.valid <= T_1321 - node T_1323 = eq(full, UInt<1>("h00")) - node T_1325 = and(UInt<1>("h00"), io.deq.ready) - node T_1326 = or(T_1323, T_1325) - io.enq.ready <= T_1326 - infer mport T_1327 = ram[T_1153], clk - node T_1453 = mux(maybe_flow, io.enq.bits, T_1327) - io.deq.bits <- T_1453 - node T_1579 = sub(T_1151, T_1153) - node ptr_diff = tail(T_1579, 1) - node T_1581 = and(maybe_full, ptr_match) - node T_1582 = cat(T_1581, ptr_diff) - io.count <= T_1582 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, count : UInt<2>} - module Queue_4 : - input clk : Clock + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_85 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_87 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_88 = and(_T_85, _T_87) @[Decoupled.scala 188:33] + node _T_89 = and(_T_85, maybe_full) @[Decoupled.scala 189:32] + node _T_90 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_90 + node _T_91 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_91 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_92 = ram[value], clock + _T_92 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_103 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_104 = tail(_T_103, 1) @[Counter.scala 26:22] + value <= _T_104 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_107 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_108 = tail(_T_107, 1) @[Counter.scala 26:22] + value_1 <= _T_108 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_109 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_109 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_111 = eq(_T_88, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_111 @[Decoupled.scala 204:16] + node _T_113 = eq(_T_89, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_113 @[Decoupled.scala 205:16] + infer mport _T_114 = ram[value_1], clock + io.deq.bits <- _T_114 @[Decoupled.scala 206:15] + node _T_123 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_124 = asUInt(_T_123) @[Decoupled.scala 221:40] + node _T_125 = tail(_T_124, 1) @[Decoupled.scala 221:40] + node _T_126 = and(maybe_full, _T_85) @[Decoupled.scala 223:32] + node _T_127 = cat(_T_126, _T_125) @[Cat.scala 30:58] + io.count <= _T_127 @[Decoupled.scala 223:14] + + module TLBuffer_bootrom : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, count : UInt<2>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}[2] - reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1151, T_1153) - node T_1158 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1158) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1164 = and(io.enq.ready, io.enq.valid) - node T_1166 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1164, T_1166) - node T_1168 = and(io.deq.ready, io.deq.valid) - node T_1170 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1168, T_1170) - when do_enq : - infer mport T_1172 = ram[T_1151], clk - T_1172 <- io.enq.bits - node T_1299 = eq(T_1151, UInt<1>("h01")) - node T_1301 = and(UInt<1>("h00"), T_1299) - node T_1304 = add(T_1151, UInt<1>("h01")) - node T_1305 = tail(T_1304, 1) - node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305) - T_1151 <= T_1306 - skip - when do_deq : - node T_1308 = eq(T_1153, UInt<1>("h01")) - node T_1310 = and(UInt<1>("h00"), T_1308) - node T_1313 = add(T_1153, UInt<1>("h01")) - node T_1314 = tail(T_1313, 1) - node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314) - T_1153 <= T_1315 - skip - node T_1316 = neq(do_enq, do_deq) - when T_1316 : - maybe_full <= do_enq - skip - node T_1318 = eq(empty, UInt<1>("h00")) - node T_1320 = and(UInt<1>("h00"), io.enq.valid) - node T_1321 = or(T_1318, T_1320) - io.deq.valid <= T_1321 - node T_1323 = eq(full, UInt<1>("h00")) - node T_1325 = and(UInt<1>("h00"), io.deq.ready) - node T_1326 = or(T_1323, T_1325) - io.enq.ready <= T_1326 - infer mport T_1327 = ram[T_1153], clk - node T_1453 = mux(maybe_flow, io.enq.bits, T_1327) - io.deq.bits <- T_1453 - node T_1579 = sub(T_1151, T_1153) - node ptr_diff = tail(T_1579, 1) - node T_1581 = and(maybe_full, ptr_match) - node T_1582 = cat(T_1581, ptr_diff) - io.count <= T_1582 + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} - module Queue_5 : - input clk : Clock + io is invalid + io is invalid + inst Queue of Queue_2 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.a.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.a.bits @[Decoupled.scala 255:19] + io.in.0.a.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.a <- Queue.io.deq @[Buffer.scala 58:13] + inst Queue_1 of Queue_3 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.out.0.d.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.out.0.d.bits @[Decoupled.scala 255:19] + io.out.0.d.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.d <- Queue_1.io.deq @[Buffer.scala 59:13] + io.in.0.b.valid <= UInt<1>("h00") @[Buffer.scala 66:20] + io.in.0.c.ready <= UInt<1>("h01") @[Buffer.scala 67:20] + io.in.0.e.ready <= UInt<1>("h01") @[Buffer.scala 68:20] + io.out.0.b.ready <= UInt<1>("h01") @[Buffer.scala 69:21] + io.out.0.c.valid <= UInt<1>("h00") @[Buffer.scala 70:21] + io.out.0.e.valid <= UInt<1>("h00") @[Buffer.scala 71:21] + + module TLMonitor_2 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, count : UInt<2>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2] - reg T_1106 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1108 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1106, T_1108) - node T_1113 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1113) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1119 = and(io.enq.ready, io.enq.valid) - node T_1121 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1119, T_1121) - node T_1123 = and(io.deq.ready, io.deq.valid) - node T_1125 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1123, T_1125) - when do_enq : - infer mport T_1127 = ram[T_1106], clk - T_1127 <- io.enq.bits - node T_1249 = eq(T_1106, UInt<1>("h01")) - node T_1251 = and(UInt<1>("h00"), T_1249) - node T_1254 = add(T_1106, UInt<1>("h01")) - node T_1255 = tail(T_1254, 1) - node T_1256 = mux(T_1251, UInt<1>("h00"), T_1255) - T_1106 <= T_1256 - skip - when do_deq : - node T_1258 = eq(T_1108, UInt<1>("h01")) - node T_1260 = and(UInt<1>("h00"), T_1258) - node T_1263 = add(T_1108, UInt<1>("h01")) - node T_1264 = tail(T_1263, 1) - node T_1265 = mux(T_1260, UInt<1>("h00"), T_1264) - T_1108 <= T_1265 - skip - node T_1266 = neq(do_enq, do_deq) - when T_1266 : - maybe_full <= do_enq - skip - node T_1268 = eq(empty, UInt<1>("h00")) - node T_1270 = and(UInt<1>("h00"), io.enq.valid) - node T_1271 = or(T_1268, T_1270) - io.deq.valid <= T_1271 - node T_1273 = eq(full, UInt<1>("h00")) - node T_1275 = and(UInt<1>("h00"), io.deq.ready) - node T_1276 = or(T_1273, T_1275) - io.enq.ready <= T_1276 - infer mport T_1277 = ram[T_1108], clk - node T_1398 = mux(maybe_flow, io.enq.bits, T_1277) - io.deq.bits <- T_1398 - node T_1519 = sub(T_1106, T_1108) - node ptr_diff = tail(T_1519, 1) - node T_1521 = and(maybe_full, ptr_match) - node T_1522 = cat(T_1521, ptr_diff) - io.count <= T_1522 - - module TileLinkEnqueuer : - input clk : Clock + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[BaseTop.scala 45:15] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[BaseTop.scala 45:15] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_608 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at BaseTop.scala:45:15)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 1, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = cat(_T_665, _T_662) @[Cat.scala 30:58] + node _T_673 = cat(_T_671, _T_668) @[Cat.scala 30:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 30:58] + node _T_676 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + when _T_676 : @[BaseTop.scala 45:15] + node _T_679 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_681 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_682 = cvt(_T_681) @[Parameters.scala 117:49] + node _T_684 = and(_T_682, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_685 = asSInt(_T_684) @[Parameters.scala 117:52] + node _T_687 = eq(_T_685, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = and(_T_679, _T_687) @[Parameters.scala 132:56] + node _T_690 = or(UInt<1>("h00"), _T_688) @[Parameters.scala 134:30] + node _T_691 = or(_T_690, reset) @[BaseTop.scala 45:15] + node _T_693 = eq(_T_691, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_693 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_694 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_696 = eq(_T_694, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_696 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_698 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_699 = or(_T_698, reset) @[BaseTop.scala 45:15] + node _T_701 = eq(_T_699, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_701 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_702 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_704 = eq(_T_702, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_704 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_706 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_707 = or(_T_706, reset) @[BaseTop.scala 45:15] + node _T_709 = eq(_T_707, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_709 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at BaseTop.scala:45:15)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_710 = not(io.in[0].a.bits.mask) @[BaseTop.scala 45:15] + node _T_712 = eq(_T_710, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_713 = or(_T_712, reset) @[BaseTop.scala 45:15] + node _T_715 = eq(_T_713, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_715 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_717 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 45:15] + when _T_717 : @[BaseTop.scala 45:15] + node _T_720 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_722 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_723 = and(_T_720, _T_722) @[Parameters.scala 63:37] + node _T_724 = or(UInt<1>("h00"), _T_723) @[Parameters.scala 132:31] + node _T_726 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_727 = cvt(_T_726) @[Parameters.scala 117:49] + node _T_729 = and(_T_727, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_730 = asSInt(_T_729) @[Parameters.scala 117:52] + node _T_732 = eq(_T_730, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_733 = and(_T_724, _T_732) @[Parameters.scala 132:56] + node _T_735 = or(UInt<1>("h00"), _T_733) @[Parameters.scala 134:30] + node _T_736 = or(_T_735, reset) @[BaseTop.scala 45:15] + node _T_738 = eq(_T_736, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_738 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_739 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_741 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_742 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_744 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_746 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_747 = or(_T_746, reset) @[BaseTop.scala 45:15] + node _T_749 = eq(_T_747, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_749 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_750 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 45:15] + node _T_751 = or(_T_750, reset) @[BaseTop.scala 45:15] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_753 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_755 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_755 : @[BaseTop.scala 45:15] + node _T_758 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_760 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_761 = cvt(_T_760) @[Parameters.scala 117:49] + node _T_763 = and(_T_761, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_764 = asSInt(_T_763) @[Parameters.scala 117:52] + node _T_766 = eq(_T_764, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_767 = and(_T_758, _T_766) @[Parameters.scala 132:56] + node _T_769 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 134:30] + node _T_770 = or(_T_769, reset) @[BaseTop.scala 45:15] + node _T_772 = eq(_T_770, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_772 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_773 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_775 = eq(_T_773, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_775 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_776 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_778 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_780 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_781 = or(_T_780, reset) @[BaseTop.scala 45:15] + node _T_783 = eq(_T_781, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_783 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_784 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 45:15] + node _T_785 = or(_T_784, reset) @[BaseTop.scala 45:15] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_787 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_789 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 45:15] + when _T_789 : @[BaseTop.scala 45:15] + node _T_792 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_794 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_795 = cvt(_T_794) @[Parameters.scala 117:49] + node _T_797 = and(_T_795, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_798 = asSInt(_T_797) @[Parameters.scala 117:52] + node _T_800 = eq(_T_798, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_801 = and(_T_792, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[BaseTop.scala 45:15] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_806 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_807 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_809 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_810 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_812 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_815 = or(_T_814, reset) @[BaseTop.scala 45:15] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_817 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_818 = not(_T_674) @[BaseTop.scala 45:15] + node _T_819 = and(io.in[0].a.bits.mask, _T_818) @[BaseTop.scala 45:15] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_822 = or(_T_821, reset) @[BaseTop.scala 45:15] + node _T_824 = eq(_T_822, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_824 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_826 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 45:15] + when _T_826 : @[BaseTop.scala 45:15] + node _T_829 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_831 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_832 = cvt(_T_831) @[Parameters.scala 117:49] + node _T_834 = and(_T_832, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_835 = asSInt(_T_834) @[Parameters.scala 117:52] + node _T_837 = eq(_T_835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_838 = and(_T_829, _T_837) @[Parameters.scala 132:56] + node _T_840 = or(UInt<1>("h00"), _T_838) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[BaseTop.scala 45:15] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_843 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_844 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_846 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_847 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_849 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_851 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_852 = or(_T_851, reset) @[BaseTop.scala 45:15] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_854 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:45:15)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_855 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 45:15] + node _T_856 = or(_T_855, reset) @[BaseTop.scala 45:15] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_858 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 45:15] + when _T_860 : @[BaseTop.scala 45:15] + node _T_863 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_865 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_872 = and(_T_863, _T_871) @[Parameters.scala 132:56] + node _T_874 = or(UInt<1>("h00"), _T_872) @[Parameters.scala 134:30] + node _T_875 = or(_T_874, reset) @[BaseTop.scala 45:15] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_877 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_878 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_880 = eq(_T_878, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_880 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_881 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_883 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_885 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_886 = or(_T_885, reset) @[BaseTop.scala 45:15] + node _T_888 = eq(_T_886, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_888 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BaseTop.scala:45:15)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_889 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 45:15] + node _T_890 = or(_T_889, reset) @[BaseTop.scala 45:15] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_892 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_894 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 45:15] + when _T_894 : @[BaseTop.scala 45:15] + node _T_897 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_899 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_900 = cvt(_T_899) @[Parameters.scala 117:49] + node _T_902 = and(_T_900, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_903 = asSInt(_T_902) @[Parameters.scala 117:52] + node _T_905 = eq(_T_903, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_906 = and(_T_897, _T_905) @[Parameters.scala 132:56] + node _T_908 = or(UInt<1>("h00"), _T_906) @[Parameters.scala 134:30] + node _T_909 = or(_T_908, reset) @[BaseTop.scala 45:15] + node _T_911 = eq(_T_909, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_911 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_912 = or(_T_630, reset) @[BaseTop.scala 45:15] + node _T_914 = eq(_T_912, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_914 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_915 = or(_T_638, reset) @[BaseTop.scala 45:15] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_917 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_918 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 45:15] + node _T_919 = or(_T_918, reset) @[BaseTop.scala 45:15] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_921 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + when io.in[0].b.valid : @[BaseTop.scala 45:15] + node _T_923 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_924 = or(_T_923, reset) @[BaseTop.scala 45:15] + node _T_926 = eq(_T_924, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_926 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at BaseTop.scala:45:15)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_928 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_929 = cvt(_T_928) @[Parameters.scala 117:49] + node _T_931 = and(_T_929, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_932 = asSInt(_T_931) @[Parameters.scala 117:52] + node _T_934 = eq(_T_932, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_937 : UInt<1>[1] @[Parameters.scala 110:36] + _T_937 is invalid @[Parameters.scala 110:36] + _T_937[0] <= _T_934 @[Parameters.scala 110:36] + node _T_942 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_943 = dshl(_T_942, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_944 = bits(_T_943, 5, 0) @[package.scala 19:76] + node _T_945 = not(_T_944) @[package.scala 19:40] + node _T_946 = and(io.in[0].b.bits.address, _T_945) @[Edges.scala 17:16] + node _T_948 = eq(_T_946, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_950 = bits(io.in[0].b.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_951 = dshl(UInt<1>("h01"), _T_950) @[OneHot.scala 49:12] + node _T_952 = bits(_T_951, 1, 0) @[OneHot.scala 49:37] + node _T_954 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_956 = bits(_T_952, 1, 1) @[package.scala 44:26] + node _T_957 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[package.scala 46:20] + node _T_960 = and(UInt<1>("h01"), _T_959) @[package.scala 49:27] + node _T_961 = and(_T_956, _T_960) @[package.scala 50:38] + node _T_962 = or(_T_954, _T_961) @[package.scala 50:29] + node _T_963 = and(UInt<1>("h01"), _T_957) @[package.scala 49:27] + node _T_964 = and(_T_956, _T_963) @[package.scala 50:38] + node _T_965 = or(_T_954, _T_964) @[package.scala 50:29] + node _T_966 = bits(_T_952, 0, 0) @[package.scala 44:26] + node _T_967 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[package.scala 46:20] + node _T_970 = and(_T_960, _T_969) @[package.scala 49:27] + node _T_971 = and(_T_966, _T_970) @[package.scala 50:38] + node _T_972 = or(_T_962, _T_971) @[package.scala 50:29] + node _T_973 = and(_T_960, _T_967) @[package.scala 49:27] + node _T_974 = and(_T_966, _T_973) @[package.scala 50:38] + node _T_975 = or(_T_962, _T_974) @[package.scala 50:29] + node _T_976 = and(_T_963, _T_969) @[package.scala 49:27] + node _T_977 = and(_T_966, _T_976) @[package.scala 50:38] + node _T_978 = or(_T_965, _T_977) @[package.scala 50:29] + node _T_979 = and(_T_963, _T_967) @[package.scala 49:27] + node _T_980 = and(_T_966, _T_979) @[package.scala 50:38] + node _T_981 = or(_T_965, _T_980) @[package.scala 50:29] + node _T_982 = cat(_T_975, _T_972) @[Cat.scala 30:58] + node _T_983 = cat(_T_981, _T_978) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, _T_982) @[Cat.scala 30:58] + node _T_986 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + when _T_986 : @[BaseTop.scala 45:15] + node _T_988 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_989 = not(_T_988) @[Parameters.scala 37:9] + node _T_991 = or(_T_989, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_992 = not(_T_991) @[Parameters.scala 37:7] + node _T_994 = eq(_T_992, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_996 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_998 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1001 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1001 is invalid @[Parameters.scala 228:27] + _T_1001[0] <= _T_994 @[Parameters.scala 228:27] + _T_1001[1] <= _T_996 @[Parameters.scala 228:27] + _T_1001[2] <= _T_998 @[Parameters.scala 228:27] + node _T_1009 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1011 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1012 = and(_T_1009, _T_1011) @[Parameters.scala 63:37] + node _T_1015 = mux(_T_1001[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1017 = mux(_T_1001[1], _T_1012, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1019 = mux(_T_1001[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1021 = or(_T_1015, _T_1017) @[Mux.scala 19:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 19:72] + wire _T_1024 : UInt<1> @[Mux.scala 19:72] + _T_1024 is invalid @[Mux.scala 19:72] + _T_1024 <= _T_1022 @[Mux.scala 19:72] + node _T_1025 = or(_T_1024, reset) @[BaseTop.scala 45:15] + node _T_1027 = eq(_T_1025, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1027 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1028 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1030 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1032 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1033 = or(_T_1032, reset) @[BaseTop.scala 45:15] + node _T_1035 = eq(_T_1033, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1035 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1036 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1038 = eq(_T_1036, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1038 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1040 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1041 = or(_T_1040, reset) @[BaseTop.scala 45:15] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1043 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BaseTop.scala:45:15)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1044 = not(io.in[0].b.bits.mask) @[BaseTop.scala 45:15] + node _T_1046 = eq(_T_1044, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1047 = or(_T_1046, reset) @[BaseTop.scala 45:15] + node _T_1049 = eq(_T_1047, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1049 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1051 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 45:15] + when _T_1051 : @[BaseTop.scala 45:15] + node _T_1053 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1055 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1056 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1058 = eq(_T_1056, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1058 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1059 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1061 = eq(_T_1059, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1061 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1063 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1064 = or(_T_1063, reset) @[BaseTop.scala 45:15] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1066 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1067 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 45:15] + node _T_1068 = or(_T_1067, reset) @[BaseTop.scala 45:15] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1070 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1072 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1072 : @[BaseTop.scala 45:15] + node _T_1074 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1076 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1077 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1079 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1080 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1082 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1084 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1085 = or(_T_1084, reset) @[BaseTop.scala 45:15] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1087 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1088 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 45:15] + node _T_1089 = or(_T_1088, reset) @[BaseTop.scala 45:15] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1091 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1093 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 45:15] + when _T_1093 : @[BaseTop.scala 45:15] + node _T_1095 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1097 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1098 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1100 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1101 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1103 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1105 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1106 = or(_T_1105, reset) @[BaseTop.scala 45:15] + node _T_1108 = eq(_T_1106, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1108 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1109 = not(_T_984) @[BaseTop.scala 45:15] + node _T_1110 = and(io.in[0].b.bits.mask, _T_1109) @[BaseTop.scala 45:15] + node _T_1112 = eq(_T_1110, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1113 = or(_T_1112, reset) @[BaseTop.scala 45:15] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1115 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1117 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 45:15] + when _T_1117 : @[BaseTop.scala 45:15] + node _T_1119 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1121 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1122 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1124 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1125 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1127 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1129 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1130 = or(_T_1129, reset) @[BaseTop.scala 45:15] + node _T_1132 = eq(_T_1130, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1132 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:45:15)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1133 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 45:15] + node _T_1134 = or(_T_1133, reset) @[BaseTop.scala 45:15] + node _T_1136 = eq(_T_1134, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1136 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1138 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 45:15] + when _T_1138 : @[BaseTop.scala 45:15] + node _T_1140 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1142 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1143 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1145 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1146 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1148 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1150 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1151 = or(_T_1150, reset) @[BaseTop.scala 45:15] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1153 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at BaseTop.scala:45:15)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1154 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 45:15] + node _T_1155 = or(_T_1154, reset) @[BaseTop.scala 45:15] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1157 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1159 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 45:15] + when _T_1159 : @[BaseTop.scala 45:15] + node _T_1161 = or(UInt<1>("h00"), reset) @[BaseTop.scala 45:15] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1163 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at BaseTop.scala:45:15)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1164 = or(_T_937[0], reset) @[BaseTop.scala 45:15] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1166 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1167 = or(_T_948, reset) @[BaseTop.scala 45:15] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1169 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1170 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 45:15] + node _T_1171 = or(_T_1170, reset) @[BaseTop.scala 45:15] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1173 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at BaseTop.scala:45:15)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + when io.in[0].c.valid : @[BaseTop.scala 45:15] + node _T_1175 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1176 = or(_T_1175, reset) @[BaseTop.scala 45:15] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1178 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at BaseTop.scala:45:15)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1180 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1181 = not(_T_1180) @[Parameters.scala 37:9] + node _T_1183 = or(_T_1181, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1184 = not(_T_1183) @[Parameters.scala 37:7] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1188 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1190 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1193 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1193 is invalid @[Parameters.scala 228:27] + _T_1193[0] <= _T_1186 @[Parameters.scala 228:27] + _T_1193[1] <= _T_1188 @[Parameters.scala 228:27] + _T_1193[2] <= _T_1190 @[Parameters.scala 228:27] + node _T_1199 = or(_T_1193[0], _T_1193[1]) @[Parameters.scala 229:46] + node _T_1200 = or(_T_1199, _T_1193[2]) @[Parameters.scala 229:46] + node _T_1202 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1203 = dshl(_T_1202, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1204 = bits(_T_1203, 5, 0) @[package.scala 19:76] + node _T_1205 = not(_T_1204) @[package.scala 19:40] + node _T_1206 = and(io.in[0].c.bits.address, _T_1205) @[Edges.scala 17:16] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1210 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1211 = cvt(_T_1210) @[Parameters.scala 117:49] + node _T_1213 = and(_T_1211, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1214 = asSInt(_T_1213) @[Parameters.scala 117:52] + node _T_1216 = eq(_T_1214, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1219 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1219 is invalid @[Parameters.scala 110:36] + _T_1219[0] <= _T_1216 @[Parameters.scala 110:36] + node _T_1224 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 45:15] + when _T_1224 : @[BaseTop.scala 45:15] + node _T_1225 = or(_T_1219[0], reset) @[BaseTop.scala 45:15] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1227 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1228 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1230 = eq(_T_1228, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1230 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1232 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1233 = or(_T_1232, reset) @[BaseTop.scala 45:15] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1235 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1236 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1238 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1240 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1241 = or(_T_1240, reset) @[BaseTop.scala 45:15] + node _T_1243 = eq(_T_1241, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1243 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BaseTop.scala:45:15)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1245 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1246 = or(_T_1245, reset) @[BaseTop.scala 45:15] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1248 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1250 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 45:15] + when _T_1250 : @[BaseTop.scala 45:15] + node _T_1251 = or(_T_1219[0], reset) @[BaseTop.scala 45:15] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1253 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1254 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1256 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1258 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1259 = or(_T_1258, reset) @[BaseTop.scala 45:15] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1261 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1262 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1264 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1266 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1267 = or(_T_1266, reset) @[BaseTop.scala 45:15] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1269 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BaseTop.scala:45:15)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1271 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1272 = or(_T_1271, reset) @[BaseTop.scala 45:15] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1274 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1276 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + when _T_1276 : @[BaseTop.scala 45:15] + node _T_1279 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1281 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1282 = cvt(_T_1281) @[Parameters.scala 117:49] + node _T_1284 = and(_T_1282, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1285 = asSInt(_T_1284) @[Parameters.scala 117:52] + node _T_1287 = eq(_T_1285, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1288 = and(_T_1279, _T_1287) @[Parameters.scala 132:56] + node _T_1290 = or(UInt<1>("h00"), _T_1288) @[Parameters.scala 134:30] + node _T_1291 = or(_T_1290, reset) @[BaseTop.scala 45:15] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1293 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1294 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1296 = eq(_T_1294, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1296 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1298 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1299 = or(_T_1298, reset) @[BaseTop.scala 45:15] + node _T_1301 = eq(_T_1299, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1301 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1302 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1304 = eq(_T_1302, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1304 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1306 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1307 = or(_T_1306, reset) @[BaseTop.scala 45:15] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1309 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at BaseTop.scala:45:15)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1311 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1312 = or(_T_1311, reset) @[BaseTop.scala 45:15] + node _T_1314 = eq(_T_1312, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1314 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1316 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[BaseTop.scala 45:15] + when _T_1316 : @[BaseTop.scala 45:15] + node _T_1319 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1321 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1322 = cvt(_T_1321) @[Parameters.scala 117:49] + node _T_1324 = and(_T_1322, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1325 = asSInt(_T_1324) @[Parameters.scala 117:52] + node _T_1327 = eq(_T_1325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1328 = and(_T_1319, _T_1327) @[Parameters.scala 132:56] + node _T_1330 = or(UInt<1>("h00"), _T_1328) @[Parameters.scala 134:30] + node _T_1331 = or(_T_1330, reset) @[BaseTop.scala 45:15] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1333 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BaseTop.scala:45:15)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1334 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1336 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1338 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1339 = or(_T_1338, reset) @[BaseTop.scala 45:15] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1341 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1342 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1344 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1346 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1347 = or(_T_1346, reset) @[BaseTop.scala 45:15] + node _T_1349 = eq(_T_1347, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1349 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at BaseTop.scala:45:15)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1351 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1352 = or(_T_1351, reset) @[BaseTop.scala 45:15] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1354 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1356 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1356 : @[BaseTop.scala 45:15] + node _T_1357 = or(_T_1219[0], reset) @[BaseTop.scala 45:15] + node _T_1359 = eq(_T_1357, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1359 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1360 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1362 = eq(_T_1360, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1362 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1363 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1365 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1367 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1368 = or(_T_1367, reset) @[BaseTop.scala 45:15] + node _T_1370 = eq(_T_1368, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1370 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1372 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 45:15] + when _T_1372 : @[BaseTop.scala 45:15] + node _T_1373 = or(_T_1219[0], reset) @[BaseTop.scala 45:15] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1375 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1376 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1378 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1379 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1381 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1383 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1384 = or(_T_1383, reset) @[BaseTop.scala 45:15] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1386 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 45:15] + when _T_1388 : @[BaseTop.scala 45:15] + node _T_1389 = or(_T_1219[0], reset) @[BaseTop.scala 45:15] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1391 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BaseTop.scala:45:15)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1392 = or(_T_1200, reset) @[BaseTop.scala 45:15] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1394 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1395 = or(_T_1208, reset) @[BaseTop.scala 45:15] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1397 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1399 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1400 = or(_T_1399, reset) @[BaseTop.scala 45:15] + node _T_1402 = eq(_T_1400, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1402 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1404 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1405 = or(_T_1404, reset) @[BaseTop.scala 45:15] + node _T_1407 = eq(_T_1405, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1407 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + when io.in[0].d.valid : @[BaseTop.scala 45:15] + node _T_1409 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1410 = or(_T_1409, reset) @[BaseTop.scala 45:15] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1412 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at BaseTop.scala:45:15)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1414 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1415 = not(_T_1414) @[Parameters.scala 37:9] + node _T_1417 = or(_T_1415, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1418 = not(_T_1417) @[Parameters.scala 37:7] + node _T_1420 = eq(_T_1418, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1422 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1424 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1427 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1427 is invalid @[Parameters.scala 228:27] + _T_1427[0] <= _T_1420 @[Parameters.scala 228:27] + _T_1427[1] <= _T_1422 @[Parameters.scala 228:27] + _T_1427[2] <= _T_1424 @[Parameters.scala 228:27] + node _T_1433 = or(_T_1427[0], _T_1427[1]) @[Parameters.scala 229:46] + node _T_1434 = or(_T_1433, _T_1427[2]) @[Parameters.scala 229:46] + node _T_1436 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1437 = dshl(_T_1436, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1438 = bits(_T_1437, 5, 0) @[package.scala 19:76] + node _T_1439 = not(_T_1438) @[package.scala 19:40] + node _T_1440 = and(io.in[0].d.bits.addr_lo, _T_1439) @[Edges.scala 17:16] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1444 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[BaseTop.scala 45:15] + node _T_1446 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + when _T_1446 : @[BaseTop.scala 45:15] + node _T_1447 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1449 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1450 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1452 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1453 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1455 = eq(_T_1453, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1455 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1457 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1458 = or(_T_1457, reset) @[BaseTop.scala 45:15] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1460 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1462 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1463 = or(_T_1462, reset) @[BaseTop.scala 45:15] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1465 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1467 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1468 = or(_T_1467, reset) @[BaseTop.scala 45:15] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1470 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1472 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 45:15] + when _T_1472 : @[BaseTop.scala 45:15] + node _T_1473 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1475 = eq(_T_1473, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1475 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1476 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1478 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1479 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1481 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1483 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1484 = or(_T_1483, reset) @[BaseTop.scala 45:15] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1486 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1488 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1489 = or(_T_1488, reset) @[BaseTop.scala 45:15] + node _T_1491 = eq(_T_1489, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1491 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BaseTop.scala:45:15)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1493 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 45:15] + when _T_1493 : @[BaseTop.scala 45:15] + node _T_1494 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1496 = eq(_T_1494, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1496 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1497 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1499 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1500 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1502 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1504 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 45:15] + node _T_1505 = or(_T_1504, reset) @[BaseTop.scala 45:15] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1507 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BaseTop.scala:45:15)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1509 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1510 = or(_T_1509, reset) @[BaseTop.scala 45:15] + node _T_1512 = eq(_T_1510, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1512 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BaseTop.scala:45:15)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1514 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1514 : @[BaseTop.scala 45:15] + node _T_1515 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1517 = eq(_T_1515, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1517 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1518 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1520 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1521 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1523 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1525 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1526 = or(_T_1525, reset) @[BaseTop.scala 45:15] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1528 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1530 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 45:15] + when _T_1530 : @[BaseTop.scala 45:15] + node _T_1531 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1533 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1534 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1536 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1537 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1539 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1541 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1542 = or(_T_1541, reset) @[BaseTop.scala 45:15] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1544 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1546 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 45:15] + when _T_1546 : @[BaseTop.scala 45:15] + node _T_1547 = or(_T_1434, reset) @[BaseTop.scala 45:15] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1549 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1550 = or(_T_1442, reset) @[BaseTop.scala 45:15] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1552 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at BaseTop.scala:45:15)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1553 = or(_T_1444, reset) @[BaseTop.scala 45:15] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1555 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1557 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1558 = or(_T_1557, reset) @[BaseTop.scala 45:15] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1560 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at BaseTop.scala:45:15)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1562 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1563 = or(_T_1562, reset) @[BaseTop.scala 45:15] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1565 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at BaseTop.scala:45:15)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + when io.in[0].e.valid : @[BaseTop.scala 45:15] + node _T_1567 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[BaseTop.scala 45:15] + node _T_1568 = or(_T_1567, reset) @[BaseTop.scala 45:15] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1570 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1571 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1573 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1574 = dshl(_T_1573, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1575 = bits(_T_1574, 5, 0) @[package.scala 19:76] + node _T_1576 = not(_T_1575) @[package.scala 19:40] + node _T_1577 = shr(_T_1576, 2) @[Edges.scala 198:59] + node _T_1578 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1583 = mux(UInt<1>("h00"), _T_1577, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1585 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1587 = sub(_T_1585, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1588 = asUInt(_T_1587) @[Edges.scala 208:28] + node _T_1589 = tail(_T_1588, 1) @[Edges.scala 208:28] + node _T_1591 = eq(_T_1585, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1593 = eq(_T_1585, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1595 = eq(_T_1583, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1596 = or(_T_1593, _T_1595) @[Edges.scala 210:37] + node _T_1597 = and(_T_1596, _T_1571) @[Edges.scala 211:22] + node _T_1598 = not(_T_1589) @[Edges.scala 212:27] + node _T_1599 = and(_T_1583, _T_1598) @[Edges.scala 212:25] + when _T_1571 : @[Edges.scala 213:17] + node _T_1600 = mux(_T_1591, _T_1583, _T_1589) @[Edges.scala 214:21] + _T_1585 <= _T_1600 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1602 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1604 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1606 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1608 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1610 : UInt, clock @[BaseTop.scala 45:15] + node _T_1612 = eq(_T_1591, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1613 = and(io.in[0].a.valid, _T_1612) @[BaseTop.scala 45:15] + when _T_1613 : @[BaseTop.scala 45:15] + node _T_1614 = eq(io.in[0].a.bits.opcode, _T_1602) @[BaseTop.scala 45:15] + node _T_1615 = or(_T_1614, reset) @[BaseTop.scala 45:15] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1617 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1618 = eq(io.in[0].a.bits.param, _T_1604) @[BaseTop.scala 45:15] + node _T_1619 = or(_T_1618, reset) @[BaseTop.scala 45:15] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1621 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1622 = eq(io.in[0].a.bits.size, _T_1606) @[BaseTop.scala 45:15] + node _T_1623 = or(_T_1622, reset) @[BaseTop.scala 45:15] + node _T_1625 = eq(_T_1623, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1625 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1626 = eq(io.in[0].a.bits.source, _T_1608) @[BaseTop.scala 45:15] + node _T_1627 = or(_T_1626, reset) @[BaseTop.scala 45:15] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1629 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1630 = eq(io.in[0].a.bits.address, _T_1610) @[BaseTop.scala 45:15] + node _T_1631 = or(_T_1630, reset) @[BaseTop.scala 45:15] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1633 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1634 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1635 = and(_T_1634, _T_1591) @[BaseTop.scala 45:15] + when _T_1635 : @[BaseTop.scala 45:15] + _T_1602 <= io.in[0].a.bits.opcode @[BaseTop.scala 45:15] + _T_1604 <= io.in[0].a.bits.param @[BaseTop.scala 45:15] + _T_1606 <= io.in[0].a.bits.size @[BaseTop.scala 45:15] + _T_1608 <= io.in[0].a.bits.source @[BaseTop.scala 45:15] + _T_1610 <= io.in[0].a.bits.address @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1636 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1638 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1639 = dshl(_T_1638, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1640 = bits(_T_1639, 5, 0) @[package.scala 19:76] + node _T_1641 = not(_T_1640) @[package.scala 19:40] + node _T_1642 = shr(_T_1641, 2) @[Edges.scala 198:59] + node _T_1643 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1645 = eq(_T_1643, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1648 = mux(UInt<1>("h00"), _T_1642, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1650 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1652 = sub(_T_1650, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1653 = asUInt(_T_1652) @[Edges.scala 208:28] + node _T_1654 = tail(_T_1653, 1) @[Edges.scala 208:28] + node _T_1656 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1658 = eq(_T_1650, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1660 = eq(_T_1648, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1661 = or(_T_1658, _T_1660) @[Edges.scala 210:37] + node _T_1662 = and(_T_1661, _T_1636) @[Edges.scala 211:22] + node _T_1663 = not(_T_1654) @[Edges.scala 212:27] + node _T_1664 = and(_T_1648, _T_1663) @[Edges.scala 212:25] + when _T_1636 : @[Edges.scala 213:17] + node _T_1665 = mux(_T_1656, _T_1648, _T_1654) @[Edges.scala 214:21] + _T_1650 <= _T_1665 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1667 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1669 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1671 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1673 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1675 : UInt, clock @[BaseTop.scala 45:15] + node _T_1677 = eq(_T_1656, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1678 = and(io.in[0].b.valid, _T_1677) @[BaseTop.scala 45:15] + when _T_1678 : @[BaseTop.scala 45:15] + node _T_1679 = eq(io.in[0].b.bits.opcode, _T_1667) @[BaseTop.scala 45:15] + node _T_1680 = or(_T_1679, reset) @[BaseTop.scala 45:15] + node _T_1682 = eq(_T_1680, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1682 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1683 = eq(io.in[0].b.bits.param, _T_1669) @[BaseTop.scala 45:15] + node _T_1684 = or(_T_1683, reset) @[BaseTop.scala 45:15] + node _T_1686 = eq(_T_1684, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1686 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1687 = eq(io.in[0].b.bits.size, _T_1671) @[BaseTop.scala 45:15] + node _T_1688 = or(_T_1687, reset) @[BaseTop.scala 45:15] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1690 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1691 = eq(io.in[0].b.bits.source, _T_1673) @[BaseTop.scala 45:15] + node _T_1692 = or(_T_1691, reset) @[BaseTop.scala 45:15] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1694 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1695 = eq(io.in[0].b.bits.address, _T_1675) @[BaseTop.scala 45:15] + node _T_1696 = or(_T_1695, reset) @[BaseTop.scala 45:15] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1698 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1699 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1700 = and(_T_1699, _T_1656) @[BaseTop.scala 45:15] + when _T_1700 : @[BaseTop.scala 45:15] + _T_1667 <= io.in[0].b.bits.opcode @[BaseTop.scala 45:15] + _T_1669 <= io.in[0].b.bits.param @[BaseTop.scala 45:15] + _T_1671 <= io.in[0].b.bits.size @[BaseTop.scala 45:15] + _T_1673 <= io.in[0].b.bits.source @[BaseTop.scala 45:15] + _T_1675 <= io.in[0].b.bits.address @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1701 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1703 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1704 = dshl(_T_1703, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1705 = bits(_T_1704, 5, 0) @[package.scala 19:76] + node _T_1706 = not(_T_1705) @[package.scala 19:40] + node _T_1707 = shr(_T_1706, 2) @[Edges.scala 198:59] + node _T_1708 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1710 = mux(_T_1708, _T_1707, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1712 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1714 = sub(_T_1712, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1715 = asUInt(_T_1714) @[Edges.scala 208:28] + node _T_1716 = tail(_T_1715, 1) @[Edges.scala 208:28] + node _T_1718 = eq(_T_1712, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1720 = eq(_T_1712, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1722 = eq(_T_1710, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1723 = or(_T_1720, _T_1722) @[Edges.scala 210:37] + node _T_1724 = and(_T_1723, _T_1701) @[Edges.scala 211:22] + node _T_1725 = not(_T_1716) @[Edges.scala 212:27] + node _T_1726 = and(_T_1710, _T_1725) @[Edges.scala 212:25] + when _T_1701 : @[Edges.scala 213:17] + node _T_1727 = mux(_T_1718, _T_1710, _T_1716) @[Edges.scala 214:21] + _T_1712 <= _T_1727 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1729 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1731 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1733 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1735 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1737 : UInt, clock @[BaseTop.scala 45:15] + node _T_1739 = eq(_T_1718, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1740 = and(io.in[0].c.valid, _T_1739) @[BaseTop.scala 45:15] + when _T_1740 : @[BaseTop.scala 45:15] + node _T_1741 = eq(io.in[0].c.bits.opcode, _T_1729) @[BaseTop.scala 45:15] + node _T_1742 = or(_T_1741, reset) @[BaseTop.scala 45:15] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1744 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1745 = eq(io.in[0].c.bits.param, _T_1731) @[BaseTop.scala 45:15] + node _T_1746 = or(_T_1745, reset) @[BaseTop.scala 45:15] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1748 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1749 = eq(io.in[0].c.bits.size, _T_1733) @[BaseTop.scala 45:15] + node _T_1750 = or(_T_1749, reset) @[BaseTop.scala 45:15] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1752 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1753 = eq(io.in[0].c.bits.source, _T_1735) @[BaseTop.scala 45:15] + node _T_1754 = or(_T_1753, reset) @[BaseTop.scala 45:15] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1756 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1757 = eq(io.in[0].c.bits.address, _T_1737) @[BaseTop.scala 45:15] + node _T_1758 = or(_T_1757, reset) @[BaseTop.scala 45:15] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1760 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1761 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1762 = and(_T_1761, _T_1718) @[BaseTop.scala 45:15] + when _T_1762 : @[BaseTop.scala 45:15] + _T_1729 <= io.in[0].c.bits.opcode @[BaseTop.scala 45:15] + _T_1731 <= io.in[0].c.bits.param @[BaseTop.scala 45:15] + _T_1733 <= io.in[0].c.bits.size @[BaseTop.scala 45:15] + _T_1735 <= io.in[0].c.bits.source @[BaseTop.scala 45:15] + _T_1737 <= io.in[0].c.bits.address @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1763 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1765 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1766 = dshl(_T_1765, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1767 = bits(_T_1766, 5, 0) @[package.scala 19:76] + node _T_1768 = not(_T_1767) @[package.scala 19:40] + node _T_1769 = shr(_T_1768, 2) @[Edges.scala 198:59] + node _T_1770 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1773 = mux(UInt<1>("h01"), _T_1769, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1775 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1777 = sub(_T_1775, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1778 = asUInt(_T_1777) @[Edges.scala 208:28] + node _T_1779 = tail(_T_1778, 1) @[Edges.scala 208:28] + node _T_1781 = eq(_T_1775, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1783 = eq(_T_1775, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1785 = eq(_T_1773, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1786 = or(_T_1783, _T_1785) @[Edges.scala 210:37] + node _T_1787 = and(_T_1786, _T_1763) @[Edges.scala 211:22] + node _T_1788 = not(_T_1779) @[Edges.scala 212:27] + node _T_1789 = and(_T_1773, _T_1788) @[Edges.scala 212:25] + when _T_1763 : @[Edges.scala 213:17] + node _T_1790 = mux(_T_1781, _T_1773, _T_1779) @[Edges.scala 214:21] + _T_1775 <= _T_1790 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1792 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1794 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1796 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1798 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1800 : UInt, clock @[BaseTop.scala 45:15] + reg _T_1802 : UInt, clock @[BaseTop.scala 45:15] + node _T_1804 = eq(_T_1781, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1805 = and(io.in[0].d.valid, _T_1804) @[BaseTop.scala 45:15] + when _T_1805 : @[BaseTop.scala 45:15] + node _T_1806 = eq(io.in[0].d.bits.opcode, _T_1792) @[BaseTop.scala 45:15] + node _T_1807 = or(_T_1806, reset) @[BaseTop.scala 45:15] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1809 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1810 = eq(io.in[0].d.bits.param, _T_1794) @[BaseTop.scala 45:15] + node _T_1811 = or(_T_1810, reset) @[BaseTop.scala 45:15] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1813 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1814 = eq(io.in[0].d.bits.size, _T_1796) @[BaseTop.scala 45:15] + node _T_1815 = or(_T_1814, reset) @[BaseTop.scala 45:15] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1817 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1818 = eq(io.in[0].d.bits.source, _T_1798) @[BaseTop.scala 45:15] + node _T_1819 = or(_T_1818, reset) @[BaseTop.scala 45:15] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1821 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1822 = eq(io.in[0].d.bits.sink, _T_1800) @[BaseTop.scala 45:15] + node _T_1823 = or(_T_1822, reset) @[BaseTop.scala 45:15] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1825 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1826 = eq(io.in[0].d.bits.addr_lo, _T_1802) @[BaseTop.scala 45:15] + node _T_1827 = or(_T_1826, reset) @[BaseTop.scala 45:15] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1829 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at BaseTop.scala:45:15)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1830 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1831 = and(_T_1830, _T_1781) @[BaseTop.scala 45:15] + when _T_1831 : @[BaseTop.scala 45:15] + _T_1792 <= io.in[0].d.bits.opcode @[BaseTop.scala 45:15] + _T_1794 <= io.in[0].d.bits.param @[BaseTop.scala 45:15] + _T_1796 <= io.in[0].d.bits.size @[BaseTop.scala 45:15] + _T_1798 <= io.in[0].d.bits.source @[BaseTop.scala 45:15] + _T_1800 <= io.in[0].d.bits.sink @[BaseTop.scala 45:15] + _T_1802 <= io.in[0].d.bits.addr_lo @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + reg _T_1833 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1834 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 2) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1843 = eq(_T_1841, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1846 = mux(UInt<1>("h00"), _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1834) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1864 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1866 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1867 = dshl(_T_1866, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1868 = bits(_T_1867, 5, 0) @[package.scala 19:76] + node _T_1869 = not(_T_1868) @[package.scala 19:40] + node _T_1870 = shr(_T_1869, 2) @[Edges.scala 198:59] + node _T_1871 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1874 = mux(UInt<1>("h01"), _T_1870, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1876 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1878 = sub(_T_1876, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1879 = asUInt(_T_1878) @[Edges.scala 208:28] + node _T_1880 = tail(_T_1879, 1) @[Edges.scala 208:28] + node _T_1882 = eq(_T_1876, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1884 = eq(_T_1876, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1886 = eq(_T_1874, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1887 = or(_T_1884, _T_1886) @[Edges.scala 210:37] + node _T_1888 = and(_T_1887, _T_1864) @[Edges.scala 211:22] + node _T_1889 = not(_T_1880) @[Edges.scala 212:27] + node _T_1890 = and(_T_1874, _T_1889) @[Edges.scala 212:25] + when _T_1864 : @[Edges.scala 213:17] + node _T_1891 = mux(_T_1882, _T_1874, _T_1880) @[Edges.scala 214:21] + _T_1876 <= _T_1891 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1893 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + node _T_1894 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[BaseTop.scala 45:15] + node _T_1895 = or(_T_1893, _T_1894) @[BaseTop.scala 45:15] + node _T_1897 = eq(io.in[0].a.valid, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1898 = or(_T_1895, _T_1897) @[BaseTop.scala 45:15] + node _T_1900 = eq(io.in[0].d.valid, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1901 = or(_T_1898, _T_1900) @[BaseTop.scala 45:15] + node _T_1902 = or(_T_1901, reset) @[BaseTop.scala 45:15] + node _T_1904 = eq(_T_1902, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1904 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BaseTop.scala:45:15)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + wire _T_1906 : UInt<6> + _T_1906 is invalid + _T_1906 <= UInt<6>("h00") + node _T_1907 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1907 : @[BaseTop.scala 45:15] + when _T_1859 : @[BaseTop.scala 45:15] + node _T_1909 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1906 <= _T_1909 @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1910 = dshr(_T_1833, io.in[0].a.bits.source) @[BaseTop.scala 45:15] + node _T_1911 = bits(_T_1910, 0, 0) @[BaseTop.scala 45:15] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[BaseTop.scala 45:15] + node _T_1914 = or(_T_1913, reset) @[BaseTop.scala 45:15] + node _T_1916 = eq(_T_1914, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1916 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at BaseTop.scala:45:15)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + wire _T_1918 : UInt<6> + _T_1918 is invalid + _T_1918 <= UInt<6>("h00") + node _T_1919 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1921 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 45:15] + node _T_1922 = and(_T_1919, _T_1921) @[BaseTop.scala 45:15] + when _T_1922 : @[BaseTop.scala 45:15] + when _T_1887 : @[BaseTop.scala 45:15] + node _T_1924 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1918 <= _T_1924 @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1925 = or(_T_1906, _T_1833) @[BaseTop.scala 45:15] + node _T_1926 = dshr(_T_1925, io.in[0].d.bits.source) @[BaseTop.scala 45:15] + node _T_1927 = bits(_T_1926, 0, 0) @[BaseTop.scala 45:15] + node _T_1928 = or(_T_1927, reset) @[BaseTop.scala 45:15] + node _T_1930 = eq(_T_1928, UInt<1>("h00")) @[BaseTop.scala 45:15] + when _T_1930 : @[BaseTop.scala 45:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BaseTop.scala:45:15)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[BaseTop.scala 45:15] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + skip @[BaseTop.scala 45:15] + node _T_1931 = or(_T_1833, _T_1906) @[BaseTop.scala 45:15] + node _T_1932 = not(_T_1918) @[BaseTop.scala 45:15] + node _T_1933 = and(_T_1931, _T_1932) @[BaseTop.scala 45:15] + _T_1833 <= _T_1933 @[BaseTop.scala 45:15] + + module TLMonitor_3 : + input clock : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - - io is invalid - inst T_7778 of Queue - T_7778.io is invalid - T_7778.clk <= clk - T_7778.reset <= reset - T_7778.io.enq.valid <= io.client.acquire.valid - T_7778.io.enq.bits <- io.client.acquire.bits - io.client.acquire.ready <= T_7778.io.enq.ready - io.manager.acquire <- T_7778.io.deq - inst T_7901 of Queue_2 - T_7901.io is invalid - T_7901.clk <= clk - T_7901.reset <= reset - T_7901.io.enq.valid <= io.manager.probe.valid - T_7901.io.enq.bits <- io.manager.probe.bits - io.manager.probe.ready <= T_7901.io.enq.ready - io.client.probe <- T_7901.io.deq - inst T_8028 of Queue_3 - T_8028.io is invalid - T_8028.clk <= clk - T_8028.reset <= reset - T_8028.io.enq.valid <= io.client.release.valid - T_8028.io.enq.bits <- io.client.release.bits - io.client.release.ready <= T_8028.io.enq.ready - io.manager.release <- T_8028.io.deq - inst T_8155 of Queue_4 - T_8155.io is invalid - T_8155.clk <= clk - T_8155.reset <= reset - T_8155.io.enq.valid <= io.manager.grant.valid - T_8155.io.enq.bits <- io.manager.grant.bits - io.manager.grant.ready <= T_8155.io.enq.ready - io.client.grant <- T_8155.io.deq - inst T_8277 of Queue_5 - T_8277.io is invalid - T_8277.clk <= clk - T_8277.reset <= reset - T_8277.io.enq.valid <= io.client.finish.valid - T_8277.io.enq.bits <- io.client.finish.bits - io.client.finish.ready <= T_8277.io.enq.ready - io.manager.finish <- T_8277.io.deq - - module FinishUnit_7 : - input clk : Clock + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[BaseTop.scala 44:21] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[BaseTop.scala 44:21] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_608 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at BaseTop.scala:44:21)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 1, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = cat(_T_665, _T_662) @[Cat.scala 30:58] + node _T_673 = cat(_T_671, _T_668) @[Cat.scala 30:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 30:58] + node _T_676 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 44:21] + when _T_676 : @[BaseTop.scala 44:21] + node _T_679 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_681 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_682 = cvt(_T_681) @[Parameters.scala 117:49] + node _T_684 = and(_T_682, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_685 = asSInt(_T_684) @[Parameters.scala 117:52] + node _T_687 = eq(_T_685, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = and(_T_679, _T_687) @[Parameters.scala 132:56] + node _T_690 = or(UInt<1>("h00"), _T_688) @[Parameters.scala 134:30] + node _T_691 = or(_T_690, reset) @[BaseTop.scala 44:21] + node _T_693 = eq(_T_691, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_693 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_694 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_696 = eq(_T_694, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_696 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_698 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_699 = or(_T_698, reset) @[BaseTop.scala 44:21] + node _T_701 = eq(_T_699, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_701 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_702 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_704 = eq(_T_702, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_704 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_706 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_707 = or(_T_706, reset) @[BaseTop.scala 44:21] + node _T_709 = eq(_T_707, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_709 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at BaseTop.scala:44:21)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_710 = not(io.in[0].a.bits.mask) @[BaseTop.scala 44:21] + node _T_712 = eq(_T_710, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_713 = or(_T_712, reset) @[BaseTop.scala 44:21] + node _T_715 = eq(_T_713, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_715 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_717 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 44:21] + when _T_717 : @[BaseTop.scala 44:21] + node _T_720 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_722 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_723 = and(_T_720, _T_722) @[Parameters.scala 63:37] + node _T_724 = or(UInt<1>("h00"), _T_723) @[Parameters.scala 132:31] + node _T_726 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_727 = cvt(_T_726) @[Parameters.scala 117:49] + node _T_729 = and(_T_727, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_730 = asSInt(_T_729) @[Parameters.scala 117:52] + node _T_732 = eq(_T_730, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_733 = and(_T_724, _T_732) @[Parameters.scala 132:56] + node _T_735 = or(UInt<1>("h00"), _T_733) @[Parameters.scala 134:30] + node _T_736 = or(_T_735, reset) @[BaseTop.scala 44:21] + node _T_738 = eq(_T_736, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_738 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_739 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_741 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_742 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_744 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_746 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_747 = or(_T_746, reset) @[BaseTop.scala 44:21] + node _T_749 = eq(_T_747, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_749 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_750 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 44:21] + node _T_751 = or(_T_750, reset) @[BaseTop.scala 44:21] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_753 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_755 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_755 : @[BaseTop.scala 44:21] + node _T_758 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_760 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_761 = cvt(_T_760) @[Parameters.scala 117:49] + node _T_763 = and(_T_761, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_764 = asSInt(_T_763) @[Parameters.scala 117:52] + node _T_766 = eq(_T_764, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_767 = and(_T_758, _T_766) @[Parameters.scala 132:56] + node _T_769 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 134:30] + node _T_770 = or(_T_769, reset) @[BaseTop.scala 44:21] + node _T_772 = eq(_T_770, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_772 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_773 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_775 = eq(_T_773, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_775 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_776 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_778 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_780 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_781 = or(_T_780, reset) @[BaseTop.scala 44:21] + node _T_783 = eq(_T_781, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_783 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_784 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 44:21] + node _T_785 = or(_T_784, reset) @[BaseTop.scala 44:21] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_787 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_789 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 44:21] + when _T_789 : @[BaseTop.scala 44:21] + node _T_792 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_794 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_795 = cvt(_T_794) @[Parameters.scala 117:49] + node _T_797 = and(_T_795, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_798 = asSInt(_T_797) @[Parameters.scala 117:52] + node _T_800 = eq(_T_798, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_801 = and(_T_792, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[BaseTop.scala 44:21] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_806 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_807 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_809 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_810 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_812 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_815 = or(_T_814, reset) @[BaseTop.scala 44:21] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_817 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_818 = not(_T_674) @[BaseTop.scala 44:21] + node _T_819 = and(io.in[0].a.bits.mask, _T_818) @[BaseTop.scala 44:21] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_822 = or(_T_821, reset) @[BaseTop.scala 44:21] + node _T_824 = eq(_T_822, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_824 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_826 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 44:21] + when _T_826 : @[BaseTop.scala 44:21] + node _T_829 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_831 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_832 = cvt(_T_831) @[Parameters.scala 117:49] + node _T_834 = and(_T_832, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_835 = asSInt(_T_834) @[Parameters.scala 117:52] + node _T_837 = eq(_T_835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_838 = and(_T_829, _T_837) @[Parameters.scala 132:56] + node _T_840 = or(UInt<1>("h00"), _T_838) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[BaseTop.scala 44:21] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_843 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_844 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_846 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_847 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_849 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_851 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_852 = or(_T_851, reset) @[BaseTop.scala 44:21] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_854 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:44:21)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_855 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 44:21] + node _T_856 = or(_T_855, reset) @[BaseTop.scala 44:21] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_858 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 44:21] + when _T_860 : @[BaseTop.scala 44:21] + node _T_863 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_865 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_872 = and(_T_863, _T_871) @[Parameters.scala 132:56] + node _T_874 = or(UInt<1>("h00"), _T_872) @[Parameters.scala 134:30] + node _T_875 = or(_T_874, reset) @[BaseTop.scala 44:21] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_877 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_878 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_880 = eq(_T_878, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_880 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_881 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_883 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_885 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_886 = or(_T_885, reset) @[BaseTop.scala 44:21] + node _T_888 = eq(_T_886, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_888 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BaseTop.scala:44:21)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_889 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 44:21] + node _T_890 = or(_T_889, reset) @[BaseTop.scala 44:21] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_892 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_894 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 44:21] + when _T_894 : @[BaseTop.scala 44:21] + node _T_897 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_899 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_900 = cvt(_T_899) @[Parameters.scala 117:49] + node _T_902 = and(_T_900, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_903 = asSInt(_T_902) @[Parameters.scala 117:52] + node _T_905 = eq(_T_903, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_906 = and(_T_897, _T_905) @[Parameters.scala 132:56] + node _T_908 = or(UInt<1>("h00"), _T_906) @[Parameters.scala 134:30] + node _T_909 = or(_T_908, reset) @[BaseTop.scala 44:21] + node _T_911 = eq(_T_909, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_911 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_912 = or(_T_630, reset) @[BaseTop.scala 44:21] + node _T_914 = eq(_T_912, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_914 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_915 = or(_T_638, reset) @[BaseTop.scala 44:21] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_917 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_918 = eq(io.in[0].a.bits.mask, _T_674) @[BaseTop.scala 44:21] + node _T_919 = or(_T_918, reset) @[BaseTop.scala 44:21] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_921 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + when io.in[0].b.valid : @[BaseTop.scala 44:21] + node _T_923 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_924 = or(_T_923, reset) @[BaseTop.scala 44:21] + node _T_926 = eq(_T_924, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_926 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at BaseTop.scala:44:21)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_928 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_929 = cvt(_T_928) @[Parameters.scala 117:49] + node _T_931 = and(_T_929, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_932 = asSInt(_T_931) @[Parameters.scala 117:52] + node _T_934 = eq(_T_932, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_937 : UInt<1>[1] @[Parameters.scala 110:36] + _T_937 is invalid @[Parameters.scala 110:36] + _T_937[0] <= _T_934 @[Parameters.scala 110:36] + node _T_942 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_943 = dshl(_T_942, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_944 = bits(_T_943, 5, 0) @[package.scala 19:76] + node _T_945 = not(_T_944) @[package.scala 19:40] + node _T_946 = and(io.in[0].b.bits.address, _T_945) @[Edges.scala 17:16] + node _T_948 = eq(_T_946, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_950 = bits(io.in[0].b.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_951 = dshl(UInt<1>("h01"), _T_950) @[OneHot.scala 49:12] + node _T_952 = bits(_T_951, 1, 0) @[OneHot.scala 49:37] + node _T_954 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_956 = bits(_T_952, 1, 1) @[package.scala 44:26] + node _T_957 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[package.scala 46:20] + node _T_960 = and(UInt<1>("h01"), _T_959) @[package.scala 49:27] + node _T_961 = and(_T_956, _T_960) @[package.scala 50:38] + node _T_962 = or(_T_954, _T_961) @[package.scala 50:29] + node _T_963 = and(UInt<1>("h01"), _T_957) @[package.scala 49:27] + node _T_964 = and(_T_956, _T_963) @[package.scala 50:38] + node _T_965 = or(_T_954, _T_964) @[package.scala 50:29] + node _T_966 = bits(_T_952, 0, 0) @[package.scala 44:26] + node _T_967 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[package.scala 46:20] + node _T_970 = and(_T_960, _T_969) @[package.scala 49:27] + node _T_971 = and(_T_966, _T_970) @[package.scala 50:38] + node _T_972 = or(_T_962, _T_971) @[package.scala 50:29] + node _T_973 = and(_T_960, _T_967) @[package.scala 49:27] + node _T_974 = and(_T_966, _T_973) @[package.scala 50:38] + node _T_975 = or(_T_962, _T_974) @[package.scala 50:29] + node _T_976 = and(_T_963, _T_969) @[package.scala 49:27] + node _T_977 = and(_T_966, _T_976) @[package.scala 50:38] + node _T_978 = or(_T_965, _T_977) @[package.scala 50:29] + node _T_979 = and(_T_963, _T_967) @[package.scala 49:27] + node _T_980 = and(_T_966, _T_979) @[package.scala 50:38] + node _T_981 = or(_T_965, _T_980) @[package.scala 50:29] + node _T_982 = cat(_T_975, _T_972) @[Cat.scala 30:58] + node _T_983 = cat(_T_981, _T_978) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, _T_982) @[Cat.scala 30:58] + node _T_986 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 44:21] + when _T_986 : @[BaseTop.scala 44:21] + node _T_988 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_989 = not(_T_988) @[Parameters.scala 37:9] + node _T_991 = or(_T_989, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_992 = not(_T_991) @[Parameters.scala 37:7] + node _T_994 = eq(_T_992, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_996 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_998 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1001 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1001 is invalid @[Parameters.scala 228:27] + _T_1001[0] <= _T_994 @[Parameters.scala 228:27] + _T_1001[1] <= _T_996 @[Parameters.scala 228:27] + _T_1001[2] <= _T_998 @[Parameters.scala 228:27] + node _T_1009 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1011 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1012 = and(_T_1009, _T_1011) @[Parameters.scala 63:37] + node _T_1015 = mux(_T_1001[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1017 = mux(_T_1001[1], _T_1012, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1019 = mux(_T_1001[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1021 = or(_T_1015, _T_1017) @[Mux.scala 19:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 19:72] + wire _T_1024 : UInt<1> @[Mux.scala 19:72] + _T_1024 is invalid @[Mux.scala 19:72] + _T_1024 <= _T_1022 @[Mux.scala 19:72] + node _T_1025 = or(_T_1024, reset) @[BaseTop.scala 44:21] + node _T_1027 = eq(_T_1025, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1027 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1028 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1030 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1032 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1033 = or(_T_1032, reset) @[BaseTop.scala 44:21] + node _T_1035 = eq(_T_1033, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1035 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1036 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1038 = eq(_T_1036, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1038 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1040 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1041 = or(_T_1040, reset) @[BaseTop.scala 44:21] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1043 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BaseTop.scala:44:21)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1044 = not(io.in[0].b.bits.mask) @[BaseTop.scala 44:21] + node _T_1046 = eq(_T_1044, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1047 = or(_T_1046, reset) @[BaseTop.scala 44:21] + node _T_1049 = eq(_T_1047, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1049 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1051 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 44:21] + when _T_1051 : @[BaseTop.scala 44:21] + node _T_1053 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1055 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1056 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1058 = eq(_T_1056, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1058 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1059 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1061 = eq(_T_1059, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1061 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1063 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1064 = or(_T_1063, reset) @[BaseTop.scala 44:21] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1066 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1067 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 44:21] + node _T_1068 = or(_T_1067, reset) @[BaseTop.scala 44:21] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1070 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1072 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1072 : @[BaseTop.scala 44:21] + node _T_1074 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1076 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1077 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1079 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1080 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1082 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1084 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1085 = or(_T_1084, reset) @[BaseTop.scala 44:21] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1087 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1088 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 44:21] + node _T_1089 = or(_T_1088, reset) @[BaseTop.scala 44:21] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1091 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1093 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 44:21] + when _T_1093 : @[BaseTop.scala 44:21] + node _T_1095 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1097 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1098 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1100 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1101 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1103 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1105 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1106 = or(_T_1105, reset) @[BaseTop.scala 44:21] + node _T_1108 = eq(_T_1106, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1108 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1109 = not(_T_984) @[BaseTop.scala 44:21] + node _T_1110 = and(io.in[0].b.bits.mask, _T_1109) @[BaseTop.scala 44:21] + node _T_1112 = eq(_T_1110, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1113 = or(_T_1112, reset) @[BaseTop.scala 44:21] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1115 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1117 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 44:21] + when _T_1117 : @[BaseTop.scala 44:21] + node _T_1119 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1121 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1122 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1124 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1125 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1127 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1129 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1130 = or(_T_1129, reset) @[BaseTop.scala 44:21] + node _T_1132 = eq(_T_1130, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1132 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at BaseTop.scala:44:21)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1133 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 44:21] + node _T_1134 = or(_T_1133, reset) @[BaseTop.scala 44:21] + node _T_1136 = eq(_T_1134, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1136 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1138 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[BaseTop.scala 44:21] + when _T_1138 : @[BaseTop.scala 44:21] + node _T_1140 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1142 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1143 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1145 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1146 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1148 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1150 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1151 = or(_T_1150, reset) @[BaseTop.scala 44:21] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1153 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at BaseTop.scala:44:21)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1154 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 44:21] + node _T_1155 = or(_T_1154, reset) @[BaseTop.scala 44:21] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1157 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1159 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 44:21] + when _T_1159 : @[BaseTop.scala 44:21] + node _T_1161 = or(UInt<1>("h00"), reset) @[BaseTop.scala 44:21] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1163 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at BaseTop.scala:44:21)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1164 = or(_T_937[0], reset) @[BaseTop.scala 44:21] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1166 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1167 = or(_T_948, reset) @[BaseTop.scala 44:21] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1169 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1170 = eq(io.in[0].b.bits.mask, _T_984) @[BaseTop.scala 44:21] + node _T_1171 = or(_T_1170, reset) @[BaseTop.scala 44:21] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1173 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at BaseTop.scala:44:21)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + when io.in[0].c.valid : @[BaseTop.scala 44:21] + node _T_1175 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1176 = or(_T_1175, reset) @[BaseTop.scala 44:21] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1178 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at BaseTop.scala:44:21)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1180 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1181 = not(_T_1180) @[Parameters.scala 37:9] + node _T_1183 = or(_T_1181, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1184 = not(_T_1183) @[Parameters.scala 37:7] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1188 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1190 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1193 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1193 is invalid @[Parameters.scala 228:27] + _T_1193[0] <= _T_1186 @[Parameters.scala 228:27] + _T_1193[1] <= _T_1188 @[Parameters.scala 228:27] + _T_1193[2] <= _T_1190 @[Parameters.scala 228:27] + node _T_1199 = or(_T_1193[0], _T_1193[1]) @[Parameters.scala 229:46] + node _T_1200 = or(_T_1199, _T_1193[2]) @[Parameters.scala 229:46] + node _T_1202 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1203 = dshl(_T_1202, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1204 = bits(_T_1203, 5, 0) @[package.scala 19:76] + node _T_1205 = not(_T_1204) @[package.scala 19:40] + node _T_1206 = and(io.in[0].c.bits.address, _T_1205) @[Edges.scala 17:16] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1210 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1211 = cvt(_T_1210) @[Parameters.scala 117:49] + node _T_1213 = and(_T_1211, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1214 = asSInt(_T_1213) @[Parameters.scala 117:52] + node _T_1216 = eq(_T_1214, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1219 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1219 is invalid @[Parameters.scala 110:36] + _T_1219[0] <= _T_1216 @[Parameters.scala 110:36] + node _T_1224 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 44:21] + when _T_1224 : @[BaseTop.scala 44:21] + node _T_1225 = or(_T_1219[0], reset) @[BaseTop.scala 44:21] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1227 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1228 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1230 = eq(_T_1228, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1230 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1232 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1233 = or(_T_1232, reset) @[BaseTop.scala 44:21] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1235 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1236 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1238 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1240 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1241 = or(_T_1240, reset) @[BaseTop.scala 44:21] + node _T_1243 = eq(_T_1241, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1243 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BaseTop.scala:44:21)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1245 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1246 = or(_T_1245, reset) @[BaseTop.scala 44:21] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1248 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1250 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 44:21] + when _T_1250 : @[BaseTop.scala 44:21] + node _T_1251 = or(_T_1219[0], reset) @[BaseTop.scala 44:21] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1253 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1254 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1256 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1258 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1259 = or(_T_1258, reset) @[BaseTop.scala 44:21] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1261 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1262 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1264 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1266 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1267 = or(_T_1266, reset) @[BaseTop.scala 44:21] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1269 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BaseTop.scala:44:21)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1271 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1272 = or(_T_1271, reset) @[BaseTop.scala 44:21] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1274 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1276 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 44:21] + when _T_1276 : @[BaseTop.scala 44:21] + node _T_1279 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1281 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1282 = cvt(_T_1281) @[Parameters.scala 117:49] + node _T_1284 = and(_T_1282, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1285 = asSInt(_T_1284) @[Parameters.scala 117:52] + node _T_1287 = eq(_T_1285, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1288 = and(_T_1279, _T_1287) @[Parameters.scala 132:56] + node _T_1290 = or(UInt<1>("h00"), _T_1288) @[Parameters.scala 134:30] + node _T_1291 = or(_T_1290, reset) @[BaseTop.scala 44:21] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1293 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1294 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1296 = eq(_T_1294, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1296 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1298 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1299 = or(_T_1298, reset) @[BaseTop.scala 44:21] + node _T_1301 = eq(_T_1299, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1301 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1302 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1304 = eq(_T_1302, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1304 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1306 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1307 = or(_T_1306, reset) @[BaseTop.scala 44:21] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1309 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at BaseTop.scala:44:21)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1311 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1312 = or(_T_1311, reset) @[BaseTop.scala 44:21] + node _T_1314 = eq(_T_1312, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1314 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1316 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[BaseTop.scala 44:21] + when _T_1316 : @[BaseTop.scala 44:21] + node _T_1319 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1321 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1322 = cvt(_T_1321) @[Parameters.scala 117:49] + node _T_1324 = and(_T_1322, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1325 = asSInt(_T_1324) @[Parameters.scala 117:52] + node _T_1327 = eq(_T_1325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1328 = and(_T_1319, _T_1327) @[Parameters.scala 132:56] + node _T_1330 = or(UInt<1>("h00"), _T_1328) @[Parameters.scala 134:30] + node _T_1331 = or(_T_1330, reset) @[BaseTop.scala 44:21] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1333 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BaseTop.scala:44:21)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1334 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1336 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1338 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1339 = or(_T_1338, reset) @[BaseTop.scala 44:21] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1341 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1342 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1344 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1346 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1347 = or(_T_1346, reset) @[BaseTop.scala 44:21] + node _T_1349 = eq(_T_1347, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1349 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at BaseTop.scala:44:21)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1351 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1352 = or(_T_1351, reset) @[BaseTop.scala 44:21] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1354 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1356 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1356 : @[BaseTop.scala 44:21] + node _T_1357 = or(_T_1219[0], reset) @[BaseTop.scala 44:21] + node _T_1359 = eq(_T_1357, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1359 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1360 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1362 = eq(_T_1360, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1362 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1363 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1365 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1367 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1368 = or(_T_1367, reset) @[BaseTop.scala 44:21] + node _T_1370 = eq(_T_1368, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1370 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1372 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 44:21] + when _T_1372 : @[BaseTop.scala 44:21] + node _T_1373 = or(_T_1219[0], reset) @[BaseTop.scala 44:21] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1375 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1376 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1378 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1379 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1381 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1383 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1384 = or(_T_1383, reset) @[BaseTop.scala 44:21] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1386 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 44:21] + when _T_1388 : @[BaseTop.scala 44:21] + node _T_1389 = or(_T_1219[0], reset) @[BaseTop.scala 44:21] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1391 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BaseTop.scala:44:21)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1392 = or(_T_1200, reset) @[BaseTop.scala 44:21] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1394 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1395 = or(_T_1208, reset) @[BaseTop.scala 44:21] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1397 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1399 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1400 = or(_T_1399, reset) @[BaseTop.scala 44:21] + node _T_1402 = eq(_T_1400, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1402 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1404 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1405 = or(_T_1404, reset) @[BaseTop.scala 44:21] + node _T_1407 = eq(_T_1405, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1407 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + when io.in[0].d.valid : @[BaseTop.scala 44:21] + node _T_1409 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1410 = or(_T_1409, reset) @[BaseTop.scala 44:21] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1412 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at BaseTop.scala:44:21)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1414 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1415 = not(_T_1414) @[Parameters.scala 37:9] + node _T_1417 = or(_T_1415, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1418 = not(_T_1417) @[Parameters.scala 37:7] + node _T_1420 = eq(_T_1418, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1422 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1424 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1427 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1427 is invalid @[Parameters.scala 228:27] + _T_1427[0] <= _T_1420 @[Parameters.scala 228:27] + _T_1427[1] <= _T_1422 @[Parameters.scala 228:27] + _T_1427[2] <= _T_1424 @[Parameters.scala 228:27] + node _T_1433 = or(_T_1427[0], _T_1427[1]) @[Parameters.scala 229:46] + node _T_1434 = or(_T_1433, _T_1427[2]) @[Parameters.scala 229:46] + node _T_1436 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1437 = dshl(_T_1436, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1438 = bits(_T_1437, 5, 0) @[package.scala 19:76] + node _T_1439 = not(_T_1438) @[package.scala 19:40] + node _T_1440 = and(io.in[0].d.bits.addr_lo, _T_1439) @[Edges.scala 17:16] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1444 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[BaseTop.scala 44:21] + node _T_1446 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 44:21] + when _T_1446 : @[BaseTop.scala 44:21] + node _T_1447 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1449 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1450 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1452 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1453 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1455 = eq(_T_1453, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1455 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1457 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1458 = or(_T_1457, reset) @[BaseTop.scala 44:21] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1460 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1462 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1463 = or(_T_1462, reset) @[BaseTop.scala 44:21] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1465 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1467 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1468 = or(_T_1467, reset) @[BaseTop.scala 44:21] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1470 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1472 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[BaseTop.scala 44:21] + when _T_1472 : @[BaseTop.scala 44:21] + node _T_1473 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1475 = eq(_T_1473, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1475 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1476 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1478 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1479 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1481 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1483 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1484 = or(_T_1483, reset) @[BaseTop.scala 44:21] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1486 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1488 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1489 = or(_T_1488, reset) @[BaseTop.scala 44:21] + node _T_1491 = eq(_T_1489, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1491 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BaseTop.scala:44:21)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1493 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[BaseTop.scala 44:21] + when _T_1493 : @[BaseTop.scala 44:21] + node _T_1494 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1496 = eq(_T_1494, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1496 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1497 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1499 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1500 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1502 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1504 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[BaseTop.scala 44:21] + node _T_1505 = or(_T_1504, reset) @[BaseTop.scala 44:21] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1507 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BaseTop.scala:44:21)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1509 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1510 = or(_T_1509, reset) @[BaseTop.scala 44:21] + node _T_1512 = eq(_T_1510, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1512 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BaseTop.scala:44:21)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1514 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1514 : @[BaseTop.scala 44:21] + node _T_1515 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1517 = eq(_T_1515, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1517 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1518 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1520 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1521 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1523 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1525 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1526 = or(_T_1525, reset) @[BaseTop.scala 44:21] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1528 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1530 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[BaseTop.scala 44:21] + when _T_1530 : @[BaseTop.scala 44:21] + node _T_1531 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1533 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1534 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1536 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1537 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1539 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1541 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1542 = or(_T_1541, reset) @[BaseTop.scala 44:21] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1544 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1546 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[BaseTop.scala 44:21] + when _T_1546 : @[BaseTop.scala 44:21] + node _T_1547 = or(_T_1434, reset) @[BaseTop.scala 44:21] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1549 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1550 = or(_T_1442, reset) @[BaseTop.scala 44:21] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1552 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at BaseTop.scala:44:21)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1553 = or(_T_1444, reset) @[BaseTop.scala 44:21] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1555 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1557 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1558 = or(_T_1557, reset) @[BaseTop.scala 44:21] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1560 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at BaseTop.scala:44:21)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1562 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1563 = or(_T_1562, reset) @[BaseTop.scala 44:21] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1565 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at BaseTop.scala:44:21)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + when io.in[0].e.valid : @[BaseTop.scala 44:21] + node _T_1567 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[BaseTop.scala 44:21] + node _T_1568 = or(_T_1567, reset) @[BaseTop.scala 44:21] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1570 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1571 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1573 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1574 = dshl(_T_1573, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1575 = bits(_T_1574, 5, 0) @[package.scala 19:76] + node _T_1576 = not(_T_1575) @[package.scala 19:40] + node _T_1577 = shr(_T_1576, 2) @[Edges.scala 198:59] + node _T_1578 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1583 = mux(UInt<1>("h00"), _T_1577, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1585 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1587 = sub(_T_1585, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1588 = asUInt(_T_1587) @[Edges.scala 208:28] + node _T_1589 = tail(_T_1588, 1) @[Edges.scala 208:28] + node _T_1591 = eq(_T_1585, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1593 = eq(_T_1585, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1595 = eq(_T_1583, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1596 = or(_T_1593, _T_1595) @[Edges.scala 210:37] + node _T_1597 = and(_T_1596, _T_1571) @[Edges.scala 211:22] + node _T_1598 = not(_T_1589) @[Edges.scala 212:27] + node _T_1599 = and(_T_1583, _T_1598) @[Edges.scala 212:25] + when _T_1571 : @[Edges.scala 213:17] + node _T_1600 = mux(_T_1591, _T_1583, _T_1589) @[Edges.scala 214:21] + _T_1585 <= _T_1600 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1602 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1604 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1606 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1608 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1610 : UInt, clock @[BaseTop.scala 44:21] + node _T_1612 = eq(_T_1591, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1613 = and(io.in[0].a.valid, _T_1612) @[BaseTop.scala 44:21] + when _T_1613 : @[BaseTop.scala 44:21] + node _T_1614 = eq(io.in[0].a.bits.opcode, _T_1602) @[BaseTop.scala 44:21] + node _T_1615 = or(_T_1614, reset) @[BaseTop.scala 44:21] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1617 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1618 = eq(io.in[0].a.bits.param, _T_1604) @[BaseTop.scala 44:21] + node _T_1619 = or(_T_1618, reset) @[BaseTop.scala 44:21] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1621 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1622 = eq(io.in[0].a.bits.size, _T_1606) @[BaseTop.scala 44:21] + node _T_1623 = or(_T_1622, reset) @[BaseTop.scala 44:21] + node _T_1625 = eq(_T_1623, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1625 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1626 = eq(io.in[0].a.bits.source, _T_1608) @[BaseTop.scala 44:21] + node _T_1627 = or(_T_1626, reset) @[BaseTop.scala 44:21] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1629 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1630 = eq(io.in[0].a.bits.address, _T_1610) @[BaseTop.scala 44:21] + node _T_1631 = or(_T_1630, reset) @[BaseTop.scala 44:21] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1633 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1634 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1635 = and(_T_1634, _T_1591) @[BaseTop.scala 44:21] + when _T_1635 : @[BaseTop.scala 44:21] + _T_1602 <= io.in[0].a.bits.opcode @[BaseTop.scala 44:21] + _T_1604 <= io.in[0].a.bits.param @[BaseTop.scala 44:21] + _T_1606 <= io.in[0].a.bits.size @[BaseTop.scala 44:21] + _T_1608 <= io.in[0].a.bits.source @[BaseTop.scala 44:21] + _T_1610 <= io.in[0].a.bits.address @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1636 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1638 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1639 = dshl(_T_1638, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1640 = bits(_T_1639, 5, 0) @[package.scala 19:76] + node _T_1641 = not(_T_1640) @[package.scala 19:40] + node _T_1642 = shr(_T_1641, 2) @[Edges.scala 198:59] + node _T_1643 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1645 = eq(_T_1643, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1648 = mux(UInt<1>("h00"), _T_1642, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1650 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1652 = sub(_T_1650, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1653 = asUInt(_T_1652) @[Edges.scala 208:28] + node _T_1654 = tail(_T_1653, 1) @[Edges.scala 208:28] + node _T_1656 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1658 = eq(_T_1650, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1660 = eq(_T_1648, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1661 = or(_T_1658, _T_1660) @[Edges.scala 210:37] + node _T_1662 = and(_T_1661, _T_1636) @[Edges.scala 211:22] + node _T_1663 = not(_T_1654) @[Edges.scala 212:27] + node _T_1664 = and(_T_1648, _T_1663) @[Edges.scala 212:25] + when _T_1636 : @[Edges.scala 213:17] + node _T_1665 = mux(_T_1656, _T_1648, _T_1654) @[Edges.scala 214:21] + _T_1650 <= _T_1665 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1667 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1669 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1671 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1673 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1675 : UInt, clock @[BaseTop.scala 44:21] + node _T_1677 = eq(_T_1656, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1678 = and(io.in[0].b.valid, _T_1677) @[BaseTop.scala 44:21] + when _T_1678 : @[BaseTop.scala 44:21] + node _T_1679 = eq(io.in[0].b.bits.opcode, _T_1667) @[BaseTop.scala 44:21] + node _T_1680 = or(_T_1679, reset) @[BaseTop.scala 44:21] + node _T_1682 = eq(_T_1680, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1682 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1683 = eq(io.in[0].b.bits.param, _T_1669) @[BaseTop.scala 44:21] + node _T_1684 = or(_T_1683, reset) @[BaseTop.scala 44:21] + node _T_1686 = eq(_T_1684, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1686 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1687 = eq(io.in[0].b.bits.size, _T_1671) @[BaseTop.scala 44:21] + node _T_1688 = or(_T_1687, reset) @[BaseTop.scala 44:21] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1690 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1691 = eq(io.in[0].b.bits.source, _T_1673) @[BaseTop.scala 44:21] + node _T_1692 = or(_T_1691, reset) @[BaseTop.scala 44:21] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1694 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1695 = eq(io.in[0].b.bits.address, _T_1675) @[BaseTop.scala 44:21] + node _T_1696 = or(_T_1695, reset) @[BaseTop.scala 44:21] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1698 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1699 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1700 = and(_T_1699, _T_1656) @[BaseTop.scala 44:21] + when _T_1700 : @[BaseTop.scala 44:21] + _T_1667 <= io.in[0].b.bits.opcode @[BaseTop.scala 44:21] + _T_1669 <= io.in[0].b.bits.param @[BaseTop.scala 44:21] + _T_1671 <= io.in[0].b.bits.size @[BaseTop.scala 44:21] + _T_1673 <= io.in[0].b.bits.source @[BaseTop.scala 44:21] + _T_1675 <= io.in[0].b.bits.address @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1701 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1703 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1704 = dshl(_T_1703, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1705 = bits(_T_1704, 5, 0) @[package.scala 19:76] + node _T_1706 = not(_T_1705) @[package.scala 19:40] + node _T_1707 = shr(_T_1706, 2) @[Edges.scala 198:59] + node _T_1708 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1710 = mux(_T_1708, _T_1707, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1712 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1714 = sub(_T_1712, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1715 = asUInt(_T_1714) @[Edges.scala 208:28] + node _T_1716 = tail(_T_1715, 1) @[Edges.scala 208:28] + node _T_1718 = eq(_T_1712, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1720 = eq(_T_1712, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1722 = eq(_T_1710, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1723 = or(_T_1720, _T_1722) @[Edges.scala 210:37] + node _T_1724 = and(_T_1723, _T_1701) @[Edges.scala 211:22] + node _T_1725 = not(_T_1716) @[Edges.scala 212:27] + node _T_1726 = and(_T_1710, _T_1725) @[Edges.scala 212:25] + when _T_1701 : @[Edges.scala 213:17] + node _T_1727 = mux(_T_1718, _T_1710, _T_1716) @[Edges.scala 214:21] + _T_1712 <= _T_1727 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1729 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1731 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1733 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1735 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1737 : UInt, clock @[BaseTop.scala 44:21] + node _T_1739 = eq(_T_1718, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1740 = and(io.in[0].c.valid, _T_1739) @[BaseTop.scala 44:21] + when _T_1740 : @[BaseTop.scala 44:21] + node _T_1741 = eq(io.in[0].c.bits.opcode, _T_1729) @[BaseTop.scala 44:21] + node _T_1742 = or(_T_1741, reset) @[BaseTop.scala 44:21] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1744 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1745 = eq(io.in[0].c.bits.param, _T_1731) @[BaseTop.scala 44:21] + node _T_1746 = or(_T_1745, reset) @[BaseTop.scala 44:21] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1748 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1749 = eq(io.in[0].c.bits.size, _T_1733) @[BaseTop.scala 44:21] + node _T_1750 = or(_T_1749, reset) @[BaseTop.scala 44:21] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1752 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1753 = eq(io.in[0].c.bits.source, _T_1735) @[BaseTop.scala 44:21] + node _T_1754 = or(_T_1753, reset) @[BaseTop.scala 44:21] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1756 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1757 = eq(io.in[0].c.bits.address, _T_1737) @[BaseTop.scala 44:21] + node _T_1758 = or(_T_1757, reset) @[BaseTop.scala 44:21] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1760 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1761 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1762 = and(_T_1761, _T_1718) @[BaseTop.scala 44:21] + when _T_1762 : @[BaseTop.scala 44:21] + _T_1729 <= io.in[0].c.bits.opcode @[BaseTop.scala 44:21] + _T_1731 <= io.in[0].c.bits.param @[BaseTop.scala 44:21] + _T_1733 <= io.in[0].c.bits.size @[BaseTop.scala 44:21] + _T_1735 <= io.in[0].c.bits.source @[BaseTop.scala 44:21] + _T_1737 <= io.in[0].c.bits.address @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1763 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1765 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1766 = dshl(_T_1765, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1767 = bits(_T_1766, 5, 0) @[package.scala 19:76] + node _T_1768 = not(_T_1767) @[package.scala 19:40] + node _T_1769 = shr(_T_1768, 2) @[Edges.scala 198:59] + node _T_1770 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1773 = mux(UInt<1>("h01"), _T_1769, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1775 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1777 = sub(_T_1775, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1778 = asUInt(_T_1777) @[Edges.scala 208:28] + node _T_1779 = tail(_T_1778, 1) @[Edges.scala 208:28] + node _T_1781 = eq(_T_1775, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1783 = eq(_T_1775, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1785 = eq(_T_1773, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1786 = or(_T_1783, _T_1785) @[Edges.scala 210:37] + node _T_1787 = and(_T_1786, _T_1763) @[Edges.scala 211:22] + node _T_1788 = not(_T_1779) @[Edges.scala 212:27] + node _T_1789 = and(_T_1773, _T_1788) @[Edges.scala 212:25] + when _T_1763 : @[Edges.scala 213:17] + node _T_1790 = mux(_T_1781, _T_1773, _T_1779) @[Edges.scala 214:21] + _T_1775 <= _T_1790 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1792 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1794 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1796 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1798 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1800 : UInt, clock @[BaseTop.scala 44:21] + reg _T_1802 : UInt, clock @[BaseTop.scala 44:21] + node _T_1804 = eq(_T_1781, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1805 = and(io.in[0].d.valid, _T_1804) @[BaseTop.scala 44:21] + when _T_1805 : @[BaseTop.scala 44:21] + node _T_1806 = eq(io.in[0].d.bits.opcode, _T_1792) @[BaseTop.scala 44:21] + node _T_1807 = or(_T_1806, reset) @[BaseTop.scala 44:21] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1809 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1810 = eq(io.in[0].d.bits.param, _T_1794) @[BaseTop.scala 44:21] + node _T_1811 = or(_T_1810, reset) @[BaseTop.scala 44:21] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1813 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1814 = eq(io.in[0].d.bits.size, _T_1796) @[BaseTop.scala 44:21] + node _T_1815 = or(_T_1814, reset) @[BaseTop.scala 44:21] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1817 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1818 = eq(io.in[0].d.bits.source, _T_1798) @[BaseTop.scala 44:21] + node _T_1819 = or(_T_1818, reset) @[BaseTop.scala 44:21] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1821 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1822 = eq(io.in[0].d.bits.sink, _T_1800) @[BaseTop.scala 44:21] + node _T_1823 = or(_T_1822, reset) @[BaseTop.scala 44:21] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1825 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1826 = eq(io.in[0].d.bits.addr_lo, _T_1802) @[BaseTop.scala 44:21] + node _T_1827 = or(_T_1826, reset) @[BaseTop.scala 44:21] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1829 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at BaseTop.scala:44:21)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1830 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1831 = and(_T_1830, _T_1781) @[BaseTop.scala 44:21] + when _T_1831 : @[BaseTop.scala 44:21] + _T_1792 <= io.in[0].d.bits.opcode @[BaseTop.scala 44:21] + _T_1794 <= io.in[0].d.bits.param @[BaseTop.scala 44:21] + _T_1796 <= io.in[0].d.bits.size @[BaseTop.scala 44:21] + _T_1798 <= io.in[0].d.bits.source @[BaseTop.scala 44:21] + _T_1800 <= io.in[0].d.bits.sink @[BaseTop.scala 44:21] + _T_1802 <= io.in[0].d.bits.addr_lo @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + reg _T_1833 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1834 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 2) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1843 = eq(_T_1841, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1846 = mux(UInt<1>("h00"), _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1834) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1864 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1866 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1867 = dshl(_T_1866, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1868 = bits(_T_1867, 5, 0) @[package.scala 19:76] + node _T_1869 = not(_T_1868) @[package.scala 19:40] + node _T_1870 = shr(_T_1869, 2) @[Edges.scala 198:59] + node _T_1871 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1874 = mux(UInt<1>("h01"), _T_1870, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1876 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1878 = sub(_T_1876, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1879 = asUInt(_T_1878) @[Edges.scala 208:28] + node _T_1880 = tail(_T_1879, 1) @[Edges.scala 208:28] + node _T_1882 = eq(_T_1876, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1884 = eq(_T_1876, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1886 = eq(_T_1874, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1887 = or(_T_1884, _T_1886) @[Edges.scala 210:37] + node _T_1888 = and(_T_1887, _T_1864) @[Edges.scala 211:22] + node _T_1889 = not(_T_1880) @[Edges.scala 212:27] + node _T_1890 = and(_T_1874, _T_1889) @[Edges.scala 212:25] + when _T_1864 : @[Edges.scala 213:17] + node _T_1891 = mux(_T_1882, _T_1874, _T_1880) @[Edges.scala 214:21] + _T_1876 <= _T_1891 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1893 : UInt<6> + _T_1893 is invalid + _T_1893 <= UInt<6>("h00") + node _T_1894 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1894 : @[BaseTop.scala 44:21] + when _T_1859 : @[BaseTop.scala 44:21] + node _T_1896 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1893 <= _T_1896 @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1897 = dshr(_T_1833, io.in[0].a.bits.source) @[BaseTop.scala 44:21] + node _T_1898 = bits(_T_1897, 0, 0) @[BaseTop.scala 44:21] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[BaseTop.scala 44:21] + node _T_1901 = or(_T_1900, reset) @[BaseTop.scala 44:21] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1903 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at BaseTop.scala:44:21)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + wire _T_1905 : UInt<6> + _T_1905 is invalid + _T_1905 <= UInt<6>("h00") + node _T_1906 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1908 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseTop.scala 44:21] + node _T_1909 = and(_T_1906, _T_1908) @[BaseTop.scala 44:21] + when _T_1909 : @[BaseTop.scala 44:21] + when _T_1887 : @[BaseTop.scala 44:21] + node _T_1911 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1905 <= _T_1911 @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1912 = or(_T_1893, _T_1833) @[BaseTop.scala 44:21] + node _T_1913 = dshr(_T_1912, io.in[0].d.bits.source) @[BaseTop.scala 44:21] + node _T_1914 = bits(_T_1913, 0, 0) @[BaseTop.scala 44:21] + node _T_1915 = or(_T_1914, reset) @[BaseTop.scala 44:21] + node _T_1917 = eq(_T_1915, UInt<1>("h00")) @[BaseTop.scala 44:21] + when _T_1917 : @[BaseTop.scala 44:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BaseTop.scala:44:21)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[BaseTop.scala 44:21] + stop(clock, UInt<1>(1), 1) @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + skip @[BaseTop.scala 44:21] + node _T_1918 = or(_T_1833, _T_1893) @[BaseTop.scala 44:21] + node _T_1919 = not(_T_1905) @[BaseTop.scala 44:21] + node _T_1920 = and(_T_1918, _T_1919) @[BaseTop.scala 44:21] + _T_1833 <= _T_1920 @[BaseTop.scala 44:21] + + module IntXing : + input clock : Clock input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h05") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h00"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h00") - T_1190[1] <= UInt<1>("h01") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h00"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h01"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h03")) - node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h01")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h00")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h05") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h00"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h00") - T_1334[1] <= UInt<1>("h01") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h00"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h01"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h00")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : {manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<1>("h01") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h00")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h00")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h00")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h00")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - - module ClientTileLinkNetworkPort_6 : - input clk : Clock + output io : {flip in : {0 : UInt<1>[2]}, out : {0 : UInt<1>[2]}} + + io is invalid + io is invalid + reg _T_16 : UInt<1>[2], clock @[Reg.scala 14:44] + _T_16 <- io.in.0 @[Reg.scala 14:44] + reg _T_24 : UInt<1>[2], clock @[Reg.scala 14:44] + _T_24 <- _T_16 @[Reg.scala 14:44] + reg _T_35 : UInt<1>[2], clock @[Reg.scala 14:44] + _T_35 <- _T_24 @[Reg.scala 14:44] + reg _T_49 : UInt<1>[2], clock @[Reg.scala 14:44] + _T_49 <- _T_35 @[Reg.scala 14:44] + io.out.0 <- _T_49 @[IntNodes.scala 141:11] + + module Queue_4 : + input clock : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - - io is invalid - inst finisher of FinishUnit_7 - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<1>("h01") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<1>("h01") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill - - module FinishUnit_16 : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<6>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[32] @[Decoupled.scala 182:24] + reg value : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<5>("h01f")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<5>("h01f")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_46 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_72 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_73 = asUInt(_T_72) @[Decoupled.scala 221:40] + node _T_74 = tail(_T_73, 1) @[Decoupled.scala 221:40] + node _T_75 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 30:58] + io.count <= _T_76 @[Decoupled.scala 223:14] + + module PositionalMultiQueue : + input clock : Clock input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - - io is invalid - node T_1178 = and(io.grant.ready, io.grant.valid) - wire T_1183 : UInt<3>[1] - T_1183[0] <= UInt<3>("h05") - node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) - node T_1188 = or(UInt<1>("h00"), T_1186) - wire T_1190 : UInt<1>[2] - T_1190[0] <= UInt<1>("h00") - T_1190[1] <= UInt<1>("h01") - node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) - node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) - node T_1197 = or(UInt<1>("h00"), T_1194) - node T_1198 = or(T_1197, T_1195) - node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) - node T_1200 = and(UInt<1>("h01"), T_1199) - node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1201 : - node T_1205 = eq(T_1203, UInt<2>("h03")) - node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = add(T_1203, UInt<1>("h01")) - node T_1211 = tail(T_1210, 1) - node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) - T_1203 <= T_1212 - skip - node T_1213 = and(T_1201, T_1205) - node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1215 = mux(T_1200, T_1213, T_1178) - inst T_1312 of FinishQueue - T_1312.io is invalid - T_1312.clk <= clk - T_1312.reset <= reset - node T_1313 = and(io.grant.ready, io.grant.valid) - node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) - node T_1321 = eq(T_1319, UInt<1>("h00")) - node T_1322 = and(T_1316, T_1321) - node T_1323 = and(T_1313, T_1322) - wire T_1327 : UInt<3>[1] - T_1327[0] <= UInt<3>("h05") - node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) - node T_1332 = or(UInt<1>("h00"), T_1330) - wire T_1334 : UInt<1>[2] - T_1334[0] <= UInt<1>("h00") - T_1334[1] <= UInt<1>("h01") - node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) - node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) - node T_1341 = or(UInt<1>("h00"), T_1338) - node T_1342 = or(T_1341, T_1339) - node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) - node T_1344 = and(UInt<1>("h01"), T_1343) - node T_1346 = eq(T_1344, UInt<1>("h00")) - node T_1347 = or(T_1346, T_1215) - node T_1348 = and(T_1323, T_1347) - T_1312.io.enq.valid <= T_1348 - wire T_1374 : {manager_xact_id : UInt<4>} - T_1374 is invalid - T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1312.io.enq.bits.fin <- T_1374 - T_1312.io.enq.bits.dst <= io.grant.bits.header.src - io.finish.bits.header.src <= UInt<2>("h02") - io.finish.bits.header.dst <= T_1312.io.deq.bits.dst - io.finish.bits.payload <- T_1312.io.deq.bits.fin - io.finish.valid <= T_1312.io.deq.valid - T_1312.io.deq.ready <= io.finish.ready - node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) - node T_1407 = eq(T_1405, UInt<1>("h00")) - node T_1408 = and(T_1402, T_1407) - node T_1410 = eq(T_1408, UInt<1>("h00")) - node T_1411 = or(T_1312.io.enq.ready, T_1410) - node T_1412 = and(T_1411, io.grant.valid) - io.refill.valid <= T_1412 - io.refill.bits <- io.grant.bits.payload - node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) - node T_1420 = eq(T_1418, UInt<1>("h00")) - node T_1421 = and(T_1415, T_1420) - node T_1423 = eq(T_1421, UInt<1>("h00")) - node T_1424 = or(T_1312.io.enq.ready, T_1423) - node T_1425 = and(T_1424, io.refill.ready) - io.grant.ready <= T_1425 - io.ready <= T_1312.io.enq.ready - - module ClientTileLinkNetworkPort_15 : - input clk : Clock + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_1 : + input clock : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - - io is invalid - inst finisher of FinishUnit_16 - finisher.io is invalid - finisher.clk <= clk - finisher.reset <= reset - finisher.io.grant <- io.network.grant - io.network.finish <- finisher.io.finish - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header is invalid - acq_with_header.bits.payload <- io.client.acquire.bits - acq_with_header.bits.header.src <= UInt<2>("h02") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.valid <= io.client.acquire.valid - io.client.acquire.ready <= acq_with_header.ready - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header is invalid - rel_with_header.bits.payload <- io.client.release.bits - rel_with_header.bits.header.src <= UInt<2>("h02") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.valid <= io.client.release.valid - io.client.release.ready <= rel_with_header.ready - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header is invalid - prb_without_header.valid <= io.network.probe.valid - prb_without_header.bits <- io.network.probe.bits.payload - io.network.probe.ready <= prb_without_header.ready - io.network.acquire.bits <- acq_with_header.bits - node T_4978 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_4978 - node T_4979 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_4979 - io.network.release <- rel_with_header - io.client.probe <- prb_without_header - io.client.grant <- finisher.io.refill - - module ManagerTileLinkNetworkPort : - input clk : Clock + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_2 : + input clock : Clock input reset : UInt<1> - output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - - io is invalid - wire T_6833 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}} - T_6833 is invalid - T_6833.bits.payload <- io.manager.grant.bits - T_6833.bits.header.src <= UInt<1>("h00") - T_6833.bits.header.dst <= io.manager.grant.bits.client_id - T_6833.valid <= io.manager.grant.valid - io.manager.grant.ready <= T_6833.ready - io.network.grant <- T_6833 - wire T_7463 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} - T_7463 is invalid - T_7463.bits.payload <- io.manager.probe.bits - T_7463.bits.header.src <= UInt<1>("h00") - T_7463.bits.header.dst <= io.manager.probe.bits.client_id - T_7463.valid <= io.manager.probe.valid - io.manager.probe.ready <= T_7463.ready - io.network.probe <- T_7463 - io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src - wire T_7778 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} - T_7778 is invalid - T_7778.valid <= io.network.acquire.valid - T_7778.bits <- io.network.acquire.bits.payload - io.network.acquire.ready <= T_7778.ready - io.manager.acquire <- T_7778 - io.manager.release.bits.client_id <= io.network.release.bits.header.src - wire T_7906 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - T_7906 is invalid - T_7906.valid <= io.network.release.valid - T_7906.bits <- io.network.release.bits.payload - io.network.release.ready <= T_7906.ready - io.manager.release <- T_7906 - wire T_8022 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} - T_8022 is invalid - T_8022.valid <= io.network.finish.valid - T_8022.bits <- io.network.finish.bits.payload - io.network.finish.ready <= T_8022.ready - io.manager.finish <- T_8022 + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module Queue_25 : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_3 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<1>} - - io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[1] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1156 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_1156) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_1162 = and(io.enq.ready, io.enq.valid) - node T_1164 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_1162, T_1164) - node T_1166 = and(io.deq.ready, io.deq.valid) - node T_1168 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_1166, T_1168) - when do_enq : - infer mport T_1170 = ram[UInt<1>("h00")], clk - T_1170 <- io.enq.bits - skip - when do_deq : - skip - node T_1298 = neq(do_enq, do_deq) - when T_1298 : - maybe_full <= do_enq - skip - node T_1300 = eq(empty, UInt<1>("h00")) - node T_1302 = and(UInt<1>("h00"), io.enq.valid) - node T_1303 = or(T_1300, T_1302) - io.deq.valid <= T_1303 - node T_1305 = eq(full, UInt<1>("h00")) - node T_1307 = and(UInt<1>("h00"), io.deq.ready) - node T_1308 = or(T_1305, T_1307) - io.enq.ready <= T_1308 - infer mport T_1309 = ram[UInt<1>("h00")], clk - node T_1435 = mux(maybe_flow, io.enq.bits, T_1309) - io.deq.bits <- T_1435 - node T_1561 = sub(UInt<1>("h00"), UInt<1>("h00")) - node ptr_diff = tail(T_1561, 1) - node T_1563 = and(maybe_full, ptr_match) - node T_1564 = cat(T_1563, ptr_diff) - io.count <= T_1564 - - module TileLinkEnqueuer_24 : - input clk : Clock + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_4 : + input clock : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} io is invalid - io.manager.acquire <- io.client.acquire - io.client.probe <- io.manager.probe - inst T_7777 of Queue_25 - T_7777.io is invalid - T_7777.clk <= clk - T_7777.reset <= reset - T_7777.io.enq.valid <= io.client.release.valid - T_7777.io.enq.bits <- io.client.release.bits - io.client.release.ready <= T_7777.io.enq.ready - io.manager.release <- T_7777.io.deq - io.client.grant <- io.manager.grant - io.manager.finish <- io.client.finish + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] - module LockingRRArbiter : - input clk : Clock + module PositionalMultiQueue_5 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, chosen : UInt<2>} - - io is invalid - reg T_3348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_3350 : UInt, clk with : (reset => (reset, UInt<2>("h02"))) - wire T_3352 : UInt<2> - T_3352 is invalid - io.out.valid <= io.in[T_3352].valid - io.out.bits <- io.in[T_3352].bits - io.chosen <= T_3352 - io.in[T_3352].ready <= UInt<1>("h00") - reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_4128 = gt(UInt<1>("h00"), last_grant) - node T_4129 = and(io.in[0].valid, T_4128) - node T_4131 = gt(UInt<1>("h01"), last_grant) - node T_4132 = and(io.in[1].valid, T_4131) - node T_4134 = gt(UInt<2>("h02"), last_grant) - node T_4135 = and(io.in[2].valid, T_4134) - node T_4138 = or(UInt<1>("h00"), T_4129) - node T_4140 = eq(T_4138, UInt<1>("h00")) - node T_4142 = or(UInt<1>("h00"), T_4129) - node T_4143 = or(T_4142, T_4132) - node T_4145 = eq(T_4143, UInt<1>("h00")) - node T_4147 = or(UInt<1>("h00"), T_4129) - node T_4148 = or(T_4147, T_4132) - node T_4149 = or(T_4148, T_4135) - node T_4151 = eq(T_4149, UInt<1>("h00")) - node T_4153 = or(UInt<1>("h00"), T_4129) - node T_4154 = or(T_4153, T_4132) - node T_4155 = or(T_4154, T_4135) - node T_4156 = or(T_4155, io.in[0].valid) - node T_4158 = eq(T_4156, UInt<1>("h00")) - node T_4160 = or(UInt<1>("h00"), T_4129) - node T_4161 = or(T_4160, T_4132) - node T_4162 = or(T_4161, T_4135) - node T_4163 = or(T_4162, io.in[0].valid) - node T_4164 = or(T_4163, io.in[1].valid) - node T_4166 = eq(T_4164, UInt<1>("h00")) - node T_4168 = gt(UInt<1>("h00"), last_grant) - node T_4169 = and(UInt<1>("h01"), T_4168) - node T_4170 = or(T_4169, T_4151) - node T_4172 = gt(UInt<1>("h01"), last_grant) - node T_4173 = and(T_4140, T_4172) - node T_4174 = or(T_4173, T_4158) - node T_4176 = gt(UInt<2>("h02"), last_grant) - node T_4177 = and(T_4145, T_4176) - node T_4178 = or(T_4177, T_4166) - node T_4180 = eq(T_3350, UInt<1>("h00")) - node T_4181 = mux(T_3348, T_4180, T_4170) - node T_4182 = and(T_4181, io.out.ready) - io.in[0].ready <= T_4182 - node T_4184 = eq(T_3350, UInt<1>("h01")) - node T_4185 = mux(T_3348, T_4184, T_4174) - node T_4186 = and(T_4185, io.out.ready) - io.in[1].ready <= T_4186 - node T_4188 = eq(T_3350, UInt<2>("h02")) - node T_4189 = mux(T_3348, T_4188, T_4178) - node T_4190 = and(T_4189, io.out.ready) - io.in[2].ready <= T_4190 - reg T_4192 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_4194 = add(T_4192, UInt<1>("h01")) - node T_4195 = tail(T_4194, 1) - node T_4196 = and(io.out.ready, io.out.valid) - when T_4196 : - node T_4198 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type) - wire T_4201 : UInt<3>[1] - T_4201[0] <= UInt<3>("h03") - node T_4204 = eq(T_4201[0], io.out.bits.payload.a_type) - node T_4206 = or(UInt<1>("h00"), T_4204) - node T_4207 = and(T_4198, T_4206) - when T_4207 : - T_4192 <= T_4195 - node T_4209 = eq(T_3348, UInt<1>("h00")) - when T_4209 : - T_3348 <= UInt<1>("h01") - node T_4211 = and(io.in[0].ready, io.in[0].valid) - node T_4212 = and(io.in[1].ready, io.in[1].valid) - node T_4213 = and(io.in[2].ready, io.in[2].valid) - wire T_4215 : UInt<1>[3] - T_4215[0] <= T_4211 - T_4215[1] <= T_4212 - T_4215[2] <= T_4213 - node T_4223 = mux(T_4215[1], UInt<1>("h01"), UInt<2>("h02")) - node T_4224 = mux(T_4215[0], UInt<1>("h00"), T_4223) - T_3350 <= T_4224 - skip - skip - node T_4226 = eq(T_4195, UInt<1>("h00")) - when T_4226 : - T_3348 <= UInt<1>("h00") - skip - skip - node T_4230 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_4232 = mux(io.in[0].valid, UInt<1>("h00"), T_4230) - node T_4234 = gt(UInt<2>("h02"), last_grant) - node T_4235 = and(io.in[2].valid, T_4234) - node T_4237 = mux(T_4235, UInt<2>("h02"), T_4232) - node T_4239 = gt(UInt<1>("h01"), last_grant) - node T_4240 = and(io.in[1].valid, T_4239) - node choose = mux(T_4240, UInt<1>("h01"), T_4237) - node T_4243 = mux(T_3348, T_3350, choose) - T_3352 <= T_4243 - node T_4244 = and(io.out.ready, io.out.valid) - when T_4244 : - last_grant <= T_3352 - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module LockingRRArbiter_26 : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_6 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, chosen : UInt<2>} - - io is invalid - reg T_3322 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_3324 : UInt, clk with : (reset => (reset, UInt<2>("h02"))) - wire T_3326 : UInt<2> - T_3326 is invalid - io.out.valid <= io.in[T_3326].valid - io.out.bits <- io.in[T_3326].bits - io.chosen <= T_3326 - io.in[T_3326].ready <= UInt<1>("h00") - reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_4096 = gt(UInt<1>("h00"), last_grant) - node T_4097 = and(io.in[0].valid, T_4096) - node T_4099 = gt(UInt<1>("h01"), last_grant) - node T_4100 = and(io.in[1].valid, T_4099) - node T_4102 = gt(UInt<2>("h02"), last_grant) - node T_4103 = and(io.in[2].valid, T_4102) - node T_4106 = or(UInt<1>("h00"), T_4097) - node T_4108 = eq(T_4106, UInt<1>("h00")) - node T_4110 = or(UInt<1>("h00"), T_4097) - node T_4111 = or(T_4110, T_4100) - node T_4113 = eq(T_4111, UInt<1>("h00")) - node T_4115 = or(UInt<1>("h00"), T_4097) - node T_4116 = or(T_4115, T_4100) - node T_4117 = or(T_4116, T_4103) - node T_4119 = eq(T_4117, UInt<1>("h00")) - node T_4121 = or(UInt<1>("h00"), T_4097) - node T_4122 = or(T_4121, T_4100) - node T_4123 = or(T_4122, T_4103) - node T_4124 = or(T_4123, io.in[0].valid) - node T_4126 = eq(T_4124, UInt<1>("h00")) - node T_4128 = or(UInt<1>("h00"), T_4097) - node T_4129 = or(T_4128, T_4100) - node T_4130 = or(T_4129, T_4103) - node T_4131 = or(T_4130, io.in[0].valid) - node T_4132 = or(T_4131, io.in[1].valid) - node T_4134 = eq(T_4132, UInt<1>("h00")) - node T_4136 = gt(UInt<1>("h00"), last_grant) - node T_4137 = and(UInt<1>("h01"), T_4136) - node T_4138 = or(T_4137, T_4119) - node T_4140 = gt(UInt<1>("h01"), last_grant) - node T_4141 = and(T_4108, T_4140) - node T_4142 = or(T_4141, T_4126) - node T_4144 = gt(UInt<2>("h02"), last_grant) - node T_4145 = and(T_4113, T_4144) - node T_4146 = or(T_4145, T_4134) - node T_4148 = eq(T_3324, UInt<1>("h00")) - node T_4149 = mux(T_3322, T_4148, T_4138) - node T_4150 = and(T_4149, io.out.ready) - io.in[0].ready <= T_4150 - node T_4152 = eq(T_3324, UInt<1>("h01")) - node T_4153 = mux(T_3322, T_4152, T_4142) - node T_4154 = and(T_4153, io.out.ready) - io.in[1].ready <= T_4154 - node T_4156 = eq(T_3324, UInt<2>("h02")) - node T_4157 = mux(T_3322, T_4156, T_4146) - node T_4158 = and(T_4157, io.out.ready) - io.in[2].ready <= T_4158 - reg T_4160 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_4162 = add(T_4160, UInt<1>("h01")) - node T_4163 = tail(T_4162, 1) - node T_4164 = and(io.out.ready, io.out.valid) - when T_4164 : - wire T_4167 : UInt<2>[3] - T_4167[0] <= UInt<1>("h00") - T_4167[1] <= UInt<1>("h01") - T_4167[2] <= UInt<2>("h02") - node T_4172 = eq(T_4167[0], io.out.bits.payload.r_type) - node T_4173 = eq(T_4167[1], io.out.bits.payload.r_type) - node T_4174 = eq(T_4167[2], io.out.bits.payload.r_type) - node T_4176 = or(UInt<1>("h00"), T_4172) - node T_4177 = or(T_4176, T_4173) - node T_4178 = or(T_4177, T_4174) - node T_4179 = and(UInt<1>("h01"), T_4178) - when T_4179 : - T_4160 <= T_4163 - node T_4181 = eq(T_3322, UInt<1>("h00")) - when T_4181 : - T_3322 <= UInt<1>("h01") - node T_4183 = and(io.in[0].ready, io.in[0].valid) - node T_4184 = and(io.in[1].ready, io.in[1].valid) - node T_4185 = and(io.in[2].ready, io.in[2].valid) - wire T_4187 : UInt<1>[3] - T_4187[0] <= T_4183 - T_4187[1] <= T_4184 - T_4187[2] <= T_4185 - node T_4195 = mux(T_4187[1], UInt<1>("h01"), UInt<2>("h02")) - node T_4196 = mux(T_4187[0], UInt<1>("h00"), T_4195) - T_3324 <= T_4196 - skip - skip - node T_4198 = eq(T_4163, UInt<1>("h00")) - when T_4198 : - T_3322 <= UInt<1>("h00") - skip - skip - node T_4202 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_4204 = mux(io.in[0].valid, UInt<1>("h00"), T_4202) - node T_4206 = gt(UInt<2>("h02"), last_grant) - node T_4207 = and(io.in[2].valid, T_4206) - node T_4209 = mux(T_4207, UInt<2>("h02"), T_4204) - node T_4211 = gt(UInt<1>("h01"), last_grant) - node T_4212 = and(io.in[1].valid, T_4211) - node choose = mux(T_4212, UInt<1>("h01"), T_4209) - node T_4215 = mux(T_3322, T_3324, choose) - T_3326 <= T_4215 - node T_4216 = and(io.out.ready, io.out.valid) - when T_4216 : - last_grant <= T_3326 - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module RRArbiter : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_7 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>} - - io is invalid - wire T_3194 : UInt<2> - T_3194 is invalid - io.out.valid <= io.in[T_3194].valid - io.out.bits <- io.in[T_3194].bits - io.chosen <= T_3194 - io.in[T_3194].ready <= UInt<1>("h00") - reg T_3933 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_3934 = gt(UInt<1>("h00"), T_3933) - node T_3935 = and(io.in[0].valid, T_3934) - node T_3937 = gt(UInt<1>("h01"), T_3933) - node T_3938 = and(io.in[1].valid, T_3937) - node T_3940 = gt(UInt<2>("h02"), T_3933) - node T_3941 = and(io.in[2].valid, T_3940) - node T_3944 = or(UInt<1>("h00"), T_3935) - node T_3946 = eq(T_3944, UInt<1>("h00")) - node T_3948 = or(UInt<1>("h00"), T_3935) - node T_3949 = or(T_3948, T_3938) - node T_3951 = eq(T_3949, UInt<1>("h00")) - node T_3953 = or(UInt<1>("h00"), T_3935) - node T_3954 = or(T_3953, T_3938) - node T_3955 = or(T_3954, T_3941) - node T_3957 = eq(T_3955, UInt<1>("h00")) - node T_3959 = or(UInt<1>("h00"), T_3935) - node T_3960 = or(T_3959, T_3938) - node T_3961 = or(T_3960, T_3941) - node T_3962 = or(T_3961, io.in[0].valid) - node T_3964 = eq(T_3962, UInt<1>("h00")) - node T_3966 = or(UInt<1>("h00"), T_3935) - node T_3967 = or(T_3966, T_3938) - node T_3968 = or(T_3967, T_3941) - node T_3969 = or(T_3968, io.in[0].valid) - node T_3970 = or(T_3969, io.in[1].valid) - node T_3972 = eq(T_3970, UInt<1>("h00")) - node T_3974 = gt(UInt<1>("h00"), T_3933) - node T_3975 = and(UInt<1>("h01"), T_3974) - node T_3976 = or(T_3975, T_3957) - node T_3978 = gt(UInt<1>("h01"), T_3933) - node T_3979 = and(T_3946, T_3978) - node T_3980 = or(T_3979, T_3964) - node T_3982 = gt(UInt<2>("h02"), T_3933) - node T_3983 = and(T_3951, T_3982) - node T_3984 = or(T_3983, T_3972) - node T_3986 = eq(UInt<2>("h02"), UInt<1>("h00")) - node T_3987 = mux(UInt<1>("h00"), T_3986, T_3976) - node T_3988 = and(T_3987, io.out.ready) - io.in[0].ready <= T_3988 - node T_3990 = eq(UInt<2>("h02"), UInt<1>("h01")) - node T_3991 = mux(UInt<1>("h00"), T_3990, T_3980) - node T_3992 = and(T_3991, io.out.ready) - io.in[1].ready <= T_3992 - node T_3994 = eq(UInt<2>("h02"), UInt<2>("h02")) - node T_3995 = mux(UInt<1>("h00"), T_3994, T_3984) - node T_3996 = and(T_3995, io.out.ready) - io.in[2].ready <= T_3996 - node T_3999 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_4001 = mux(io.in[0].valid, UInt<1>("h00"), T_3999) - node T_4003 = gt(UInt<2>("h02"), T_3933) - node T_4004 = and(io.in[2].valid, T_4003) - node T_4006 = mux(T_4004, UInt<2>("h02"), T_4001) - node T_4008 = gt(UInt<1>("h01"), T_3933) - node T_4009 = and(io.in[1].valid, T_4008) - node T_4011 = mux(T_4009, UInt<1>("h01"), T_4006) - node T_4012 = mux(UInt<1>("h00"), UInt<2>("h02"), T_4011) - T_3194 <= T_4012 - node T_4013 = and(io.out.ready, io.out.valid) - when T_4013 : - T_3933 <= T_3194 - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module RocketChipTileLinkArbiter : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_8 : + input clock : Clock input reset : UInt<1> - output io : {flip clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}[1]} - - io is invalid - inst T_11386 of ClientTileLinkNetworkPort - T_11386.io is invalid - T_11386.clk <= clk - T_11386.reset <= reset - inst T_11387 of TileLinkEnqueuer - T_11387.io is invalid - T_11387.clk <= clk - T_11387.reset <= reset - T_11386.io.client <- io.clients[0] - T_11387.io.client <- T_11386.io.network - inst T_11388 of ClientTileLinkNetworkPort_6 - T_11388.io is invalid - T_11388.clk <= clk - T_11388.reset <= reset - inst T_11389 of TileLinkEnqueuer - T_11389.io is invalid - T_11389.clk <= clk - T_11389.reset <= reset - T_11388.io.client <- io.clients[1] - T_11389.io.client <- T_11388.io.network - inst T_11390 of ClientTileLinkNetworkPort_15 - T_11390.io is invalid - T_11390.clk <= clk - T_11390.reset <= reset - inst T_11391 of TileLinkEnqueuer - T_11391.io is invalid - T_11391.clk <= clk - T_11391.reset <= reset - T_11390.io.client <- io.clients[2] - T_11391.io.client <- T_11390.io.network - inst T_11392 of ManagerTileLinkNetworkPort - T_11392.io is invalid - T_11392.clk <= clk - T_11392.reset <= reset - inst T_11393 of TileLinkEnqueuer_24 - T_11393.io is invalid - T_11393.clk <= clk - T_11393.reset <= reset - T_11392.io.manager <- io.managers[0] - T_11392.io.network <- T_11393.io.manager - inst T_11394 of LockingRRArbiter - T_11394.io is invalid - T_11394.clk <= clk - T_11394.reset <= reset - T_11394.io.in[0].valid <= T_11387.io.manager.acquire.valid - T_11394.io.in[0].bits <- T_11387.io.manager.acquire.bits - T_11394.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.acquire.bits.payload.client_xact_id - T_11387.io.manager.acquire.ready <= T_11394.io.in[0].ready - T_11394.io.in[1].valid <= T_11389.io.manager.acquire.valid - T_11394.io.in[1].bits <- T_11389.io.manager.acquire.bits - T_11394.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.acquire.bits.payload.client_xact_id - T_11389.io.manager.acquire.ready <= T_11394.io.in[1].ready - T_11394.io.in[2].valid <= T_11391.io.manager.acquire.valid - T_11394.io.in[2].bits <- T_11391.io.manager.acquire.bits - T_11394.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.acquire.bits.payload.client_xact_id - T_11391.io.manager.acquire.ready <= T_11394.io.in[2].ready - T_11393.io.client.acquire <- T_11394.io.out - inst T_11395 of LockingRRArbiter_26 - T_11395.io is invalid - T_11395.clk <= clk - T_11395.reset <= reset - T_11395.io.in[0].valid <= T_11387.io.manager.release.valid - T_11395.io.in[0].bits <- T_11387.io.manager.release.bits - T_11395.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.release.bits.payload.client_xact_id - T_11387.io.manager.release.ready <= T_11395.io.in[0].ready - T_11395.io.in[1].valid <= T_11389.io.manager.release.valid - T_11395.io.in[1].bits <- T_11389.io.manager.release.bits - T_11395.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.release.bits.payload.client_xact_id - T_11389.io.manager.release.ready <= T_11395.io.in[1].ready - T_11395.io.in[2].valid <= T_11391.io.manager.release.valid - T_11395.io.in[2].bits <- T_11391.io.manager.release.bits - T_11395.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.release.bits.payload.client_xact_id - T_11391.io.manager.release.ready <= T_11395.io.in[2].ready - T_11393.io.client.release <- T_11395.io.out - inst T_11396 of RRArbiter - T_11396.io is invalid - T_11396.clk <= clk - T_11396.reset <= reset - T_11396.io.in[0] <- T_11387.io.manager.finish - T_11396.io.in[1] <- T_11389.io.manager.finish - T_11396.io.in[2] <- T_11391.io.manager.finish - T_11393.io.client.finish <- T_11396.io.out - T_11393.io.client.probe.ready <= UInt<1>("h00") - T_11387.io.manager.probe.valid <= UInt<1>("h00") - node T_11400 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h00")) - when T_11400 : - T_11387.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11387.io.manager.probe.ready - skip - T_11387.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11389.io.manager.probe.valid <= UInt<1>("h00") - node T_11403 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h01")) - when T_11403 : - T_11389.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11389.io.manager.probe.ready - skip - T_11389.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11391.io.manager.probe.valid <= UInt<1>("h00") - node T_11406 = eq(T_11393.io.client.probe.bits.header.dst, UInt<2>("h02")) - when T_11406 : - T_11391.io.manager.probe.valid <= T_11393.io.client.probe.valid - T_11393.io.client.probe.ready <= T_11391.io.manager.probe.ready - skip - T_11391.io.manager.probe.bits <- T_11393.io.client.probe.bits - T_11393.io.client.grant.ready <= UInt<1>("h00") - T_11387.io.manager.grant.valid <= UInt<1>("h00") - node T_11410 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h00")) - when T_11410 : - T_11387.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11387.io.manager.grant.ready - skip - T_11387.io.manager.grant.bits <- T_11393.io.client.grant.bits - T_11389.io.manager.grant.valid <= UInt<1>("h00") - node T_11413 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h01")) - when T_11413 : - T_11389.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11389.io.manager.grant.ready - skip - T_11389.io.manager.grant.bits <- T_11393.io.client.grant.bits - T_11391.io.manager.grant.valid <= UInt<1>("h00") - node T_11416 = eq(T_11393.io.client.grant.bits.header.dst, UInt<2>("h02")) - when T_11416 : - T_11391.io.manager.grant.valid <= T_11393.io.client.grant.valid - T_11393.io.client.grant.ready <= T_11391.io.manager.grant.ready - skip - T_11391.io.manager.grant.bits <- T_11393.io.client.grant.bits + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module BroadcastVoluntaryReleaseTracker : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_9 : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - reg collect_irel_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg irel_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_302 = and(io.inner.release.ready, io.inner.release.valid) - wire T_306 : UInt<2>[3] - T_306[0] <= UInt<1>("h00") - T_306[1] <= UInt<1>("h01") - T_306[2] <= UInt<2>("h02") - node T_311 = eq(T_306[0], io.inner.release.bits.r_type) - node T_312 = eq(T_306[1], io.inner.release.bits.r_type) - node T_313 = eq(T_306[2], io.inner.release.bits.r_type) - node T_315 = or(UInt<1>("h00"), T_311) - node T_316 = or(T_315, T_312) - node T_317 = or(T_316, T_313) - node T_318 = and(UInt<1>("h01"), T_317) - node T_319 = and(T_302, T_318) - reg T_321 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_319 : - node T_323 = eq(T_321, UInt<2>("h03")) - node T_325 = and(UInt<1>("h00"), T_323) - node T_328 = add(T_321, UInt<1>("h01")) - node T_329 = tail(T_328, 1) - node T_330 = mux(T_325, UInt<1>("h00"), T_329) - T_321 <= T_330 - skip - node T_331 = and(T_319, T_323) - node T_332 = mux(T_318, T_321, UInt<1>("h00")) - node irel_data_done = mux(T_318, T_331, T_302) - node T_335 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_337 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_340 : UInt<3>[1] - T_340[0] <= UInt<3>("h03") - node T_343 = eq(T_340[0], io.outer.acquire.bits.a_type) - node T_345 = or(UInt<1>("h00"), T_343) - node T_346 = and(T_337, T_345) - node T_347 = and(T_335, T_346) - reg T_349 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_347 : - node T_351 = eq(T_349, UInt<2>("h03")) - node T_353 = and(UInt<1>("h00"), T_351) - node T_356 = add(T_349, UInt<1>("h01")) - node T_357 = tail(T_356, 1) - node T_358 = mux(T_353, UInt<1>("h00"), T_357) - T_349 <= T_358 - skip - node T_359 = and(T_347, T_351) - node oacq_data_cnt = mux(T_346, T_349, UInt<1>("h00")) - node oacq_data_done = mux(T_346, T_359, T_335) - io.has_acquire_conflict <= UInt<1>("h00") - io.has_release_match <= io.inner.release.bits.voluntary - io.has_acquire_match <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - wire T_384 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_384 is invalid - T_384.client_id <= xact.client_id - T_384.is_builtin_type <= UInt<1>("h01") - T_384.g_type <= UInt<3>("h00") - T_384.client_xact_id <= xact.client_xact_id - T_384.manager_xact_id <= UInt<1>("h00") - T_384.addr_beat <= UInt<1>("h00") - T_384.data <= UInt<1>("h00") - io.inner.grant.bits <- T_384 - node T_397 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_403 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_404 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_405 = cat(T_403, T_404) - node T_407 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_408 = cat(UInt<3>("h07"), T_407) - node T_410 = cat(T_397, UInt<1>("h01")) - node T_412 = cat(T_397, UInt<1>("h01")) - node T_414 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_415 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_416 = cat(T_414, T_415) - node T_418 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_420 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_421 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_422 = mux(T_421, T_420, UInt<1>("h00")) - node T_423 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_424 = mux(T_423, T_418, T_422) - node T_425 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_426 = mux(T_425, T_416, T_424) - node T_427 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_428 = mux(T_427, T_412, T_426) - node T_429 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_430 = mux(T_429, T_410, T_428) - node T_431 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_432 = mux(T_431, T_408, T_430) - node T_433 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_434 = mux(T_433, T_405, T_432) - wire T_443 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_443 is invalid - T_443.is_builtin_type <= UInt<1>("h01") - T_443.a_type <= UInt<3>("h03") - T_443.client_xact_id <= UInt<1>("h00") - T_443.addr_block <= xact.addr_block - T_443.addr_beat <= oacq_data_cnt - T_443.data <= xact.data_buffer[oacq_data_cnt] - T_443.union <= T_434 - io.outer.acquire.bits <- T_443 - when collect_irel_data : - io.inner.release.ready <= UInt<1>("h01") - when io.inner.release.valid : - xact.data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data - node T_455 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) - node T_456 = or(irel_data_valid, T_455) - node T_457 = not(irel_data_valid) - node T_458 = or(T_457, T_455) - node T_459 = not(T_458) - node T_460 = mux(UInt<1>("h01"), T_456, T_459) - irel_data_valid <= T_460 - skip - when irel_data_done : - collect_irel_data <= UInt<1>("h00") - skip - skip - node T_462 = eq(UInt<1>("h00"), state) - when T_462 : - io.inner.release.ready <= UInt<1>("h01") - when io.inner.release.valid : - xact <- io.inner.release.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.release.bits.data - wire T_468 : UInt<2>[3] - T_468[0] <= UInt<1>("h00") - T_468[1] <= UInt<1>("h01") - T_468[2] <= UInt<2>("h02") - node T_473 = eq(T_468[0], io.inner.release.bits.r_type) - node T_474 = eq(T_468[1], io.inner.release.bits.r_type) - node T_475 = eq(T_468[2], io.inner.release.bits.r_type) - node T_477 = or(UInt<1>("h00"), T_473) - node T_478 = or(T_477, T_474) - node T_479 = or(T_478, T_475) - node T_480 = and(UInt<1>("h01"), T_479) - collect_irel_data <= T_480 - wire T_482 : UInt<2>[3] - T_482[0] <= UInt<1>("h00") - T_482[1] <= UInt<1>("h01") - T_482[2] <= UInt<2>("h02") - node T_487 = eq(T_482[0], io.inner.release.bits.r_type) - node T_488 = eq(T_482[1], io.inner.release.bits.r_type) - node T_489 = eq(T_482[2], io.inner.release.bits.r_type) - node T_491 = or(UInt<1>("h00"), T_487) - node T_492 = or(T_491, T_488) - node T_493 = or(T_492, T_489) - node T_494 = dshl(T_493, io.inner.release.bits.addr_beat) - irel_data_valid <= T_494 - wire T_496 : UInt<2>[3] - T_496[0] <= UInt<1>("h00") - T_496[1] <= UInt<1>("h01") - T_496[2] <= UInt<2>("h02") - node T_501 = eq(T_496[0], io.inner.release.bits.r_type) - node T_502 = eq(T_496[1], io.inner.release.bits.r_type) - node T_503 = eq(T_496[2], io.inner.release.bits.r_type) - node T_505 = or(UInt<1>("h00"), T_501) - node T_506 = or(T_505, T_502) - node T_507 = or(T_506, T_503) - node T_510 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_511 = mux(T_510, UInt<2>("h03"), UInt<1>("h00")) - node T_512 = mux(T_507, UInt<1>("h01"), T_511) - state <= T_512 - skip - skip - node T_513 = eq(UInt<1>("h01"), state) - when T_513 : - node T_515 = eq(collect_irel_data, UInt<1>("h00")) - node T_516 = dshr(irel_data_valid, oacq_data_cnt) - node T_517 = bits(T_516, 0, 0) - node T_518 = or(T_515, T_517) - io.outer.acquire.valid <= T_518 - when oacq_data_done : - state <= UInt<2>("h02") - skip - skip - node T_519 = eq(UInt<2>("h02"), state) - when T_519 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - node T_520 = and(io.inner.grant.ready, io.inner.grant.valid) - when T_520 : - node T_523 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_525 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_526 = and(io.inner.grant.bits.is_builtin_type, T_525) - node T_528 = eq(T_526, UInt<1>("h00")) - node T_529 = and(T_523, T_528) - node T_530 = mux(T_529, UInt<2>("h03"), UInt<1>("h00")) - state <= T_530 - skip - skip - node T_531 = eq(UInt<2>("h03"), state) - when T_531 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") - skip - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module BroadcastAcquireTracker : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_10 : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<1>("h01") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<1>("h01") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<1>("h01") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<1>("h01") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h01") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<1>("h01") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<1>("h01") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") - skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") - skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") - skip - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} - module BroadcastAcquireTracker_27 : - input clk : Clock + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_11 : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<2>("h02") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<2>("h02") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<2>("h02") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<2>("h02") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<2>("h02") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<2>("h02") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<2>("h02") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") - skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") - skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") - skip - skip + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_12 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_13 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_14 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_15 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[2] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<7>[2] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_108 = data[io.enq.bits.pos], clock + _T_108 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_109 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_110 = bits(_T_109, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_113 = or(_T_112, reset) @[PositionalMultiQueue.scala 46:12] + node _T_115 = eq(_T_113, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_115 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_119 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_119 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_121 = next[tail[io.enq.bits.way]], clock + _T_121 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<7>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_187 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_188 = dshl(UInt<1>("h01"), _T_187) @[OneHot.scala 49:12] + node waySelect = bits(_T_188, 1, 0) @[OneHot.scala 49:37] + node _T_190 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_191 = and(io.enq.valid, _T_190) @[PositionalMultiQueue.scala 60:29] + node _T_192 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_191 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_194 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_194 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_195 = data[head[0]], clock + deq[0].bits.data <= _T_195 @[PositionalMultiQueue.scala 77:24] + node _T_196 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_196 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_197 = next[head[0]], clock + node _T_198 = mux(_T_192, io.enq.bits.pos, _T_197) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_198 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_200 = dshl(_T_199, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_201 = or(UInt<1>("h00"), _T_200) @[PositionalMultiQueue.scala 83:25] + node _T_202 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_203 = neq(_T_191, _T_202) @[PositionalMultiQueue.scala 85:15] + when _T_203 : @[PositionalMultiQueue.scala 85:34] + node _T_204 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_205 = and(_T_204, _T_192) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_205 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_206 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_207 = and(io.enq.valid, _T_206) @[PositionalMultiQueue.scala 60:29] + node _T_208 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_207 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_210 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_210 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_211 = data[head[1]], clock + deq[1].bits.data <= _T_211 @[PositionalMultiQueue.scala 77:24] + node _T_212 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_212 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_213 = next[head[1]], clock + node _T_214 = mux(_T_208, io.enq.bits.pos, _T_213) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_214 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_215 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_216 = dshl(_T_215, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_201, _T_216) @[PositionalMultiQueue.scala 83:25] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_218 = neq(_T_207, _T_217) @[PositionalMultiQueue.scala 85:15] + when _T_218 : @[PositionalMultiQueue.scala 85:34] + node _T_219 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_220 = and(_T_219, _T_208) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_220 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_221 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_222 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_223 = and(_T_221, _T_222) @[PositionalMultiQueue.scala 90:31] + guard <= _T_223 @[PositionalMultiQueue.scala 90:9] + + module Queue_5 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_48 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_50 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_51 = and(_T_48, _T_50) @[Decoupled.scala 188:33] + node _T_52 = and(_T_48, maybe_full) @[Decoupled.scala 189:32] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_53 + node _T_54 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_54 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_56 = ram[UInt<1>("h00")], clock + _T_56 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_62 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_62 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_64 = eq(_T_51, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_64 @[Decoupled.scala 204:16] + node _T_66 = eq(_T_52, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_66 @[Decoupled.scala 205:16] + infer mport _T_68 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_68 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_51 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_75 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_76 = asUInt(_T_75) @[Decoupled.scala 221:40] + node _T_77 = tail(_T_76, 1) @[Decoupled.scala 221:40] + node _T_78 = and(maybe_full, _T_48) @[Decoupled.scala 223:32] + node _T_79 = cat(_T_78, _T_77) @[Cat.scala 30:58] + io.count <= _T_79 @[Decoupled.scala 223:14] + + module Queue_6 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_97 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_99 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_100 = and(_T_97, _T_99) @[Decoupled.scala 188:33] + node _T_101 = and(_T_97, maybe_full) @[Decoupled.scala 189:32] + node _T_102 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_102 + node _T_103 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_103 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_105 = ram[UInt<1>("h00")], clock + _T_105 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_118 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_118 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_120 = eq(_T_100, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_120 @[Decoupled.scala 204:16] + node _T_122 = eq(_T_101, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_122 @[Decoupled.scala 205:16] + infer mport _T_124 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_124 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_100 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_138 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_139 = asUInt(_T_138) @[Decoupled.scala 221:40] + node _T_140 = tail(_T_139, 1) @[Decoupled.scala 221:40] + node _T_141 = and(maybe_full, _T_97) @[Decoupled.scala 223:32] + node _T_142 = cat(_T_141, _T_140) @[Cat.scala 30:58] + io.count <= _T_142 @[Decoupled.scala 223:14] + + module TLToAXI4_rocketchipPeripheryMasterAXI4Memconverter : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_4 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + wire _T_517 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}} @[Decoupled.scala 272:19] + _T_517 is invalid @[Decoupled.scala 272:19] + _T_517.bits <- Queue.io.deq.bits @[Decoupled.scala 273:14] + _T_517.valid <= Queue.io.deq.valid @[Decoupled.scala 274:15] + Queue.io.deq.ready <= _T_517.ready @[Decoupled.scala 275:15] + node _T_528 = bits(io.in.0.a.bits.address, 2, 0) @[Edges.scala 172:47] + node _T_529 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_531 = eq(_T_529, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_532 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_534 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_535 = dshl(_T_534, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_536 = bits(_T_535, 7, 0) @[package.scala 19:76] + node _T_537 = not(_T_536) @[package.scala 19:40] + node _T_538 = shr(_T_537, 3) @[Edges.scala 198:59] + node _T_539 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_541 = eq(_T_539, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_543 = mux(_T_541, _T_538, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_545 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_547 = sub(_T_545, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_548 = asUInt(_T_547) @[Edges.scala 208:28] + node _T_549 = tail(_T_548, 1) @[Edges.scala 208:28] + node _T_551 = eq(_T_545, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_553 = eq(_T_545, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_555 = eq(_T_543, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_556 = or(_T_553, _T_555) @[Edges.scala 210:37] + node _T_557 = and(_T_556, _T_532) @[Edges.scala 211:22] + node _T_558 = not(_T_549) @[Edges.scala 212:27] + node _T_559 = and(_T_543, _T_558) @[Edges.scala 212:25] + when _T_532 : @[Edges.scala 213:17] + node _T_560 = mux(_T_551, _T_543, _T_549) @[Edges.scala 214:21] + _T_545 <= _T_560 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_562 = lt(io.in.0.a.bits.source, UInt<6>("h020")) @[ToAXI4.scala 82:25] + node _T_563 = or(_T_562, reset) @[ToAXI4.scala 82:14] + node _T_565 = eq(_T_563, UInt<1>("h00")) @[ToAXI4.scala 82:14] + when _T_565 : @[ToAXI4.scala 82:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:82 assert (a_source < UInt(BigInt(1) << sourceBits))\n") @[ToAXI4.scala 82:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 82:14] + skip @[ToAXI4.scala 82:14] + node _T_567 = lt(io.in.0.a.bits.size, UInt<5>("h010")) @[ToAXI4.scala 83:25] + node _T_568 = or(_T_567, reset) @[ToAXI4.scala 83:14] + node _T_570 = eq(_T_568, UInt<1>("h00")) @[ToAXI4.scala 83:14] + when _T_570 : @[ToAXI4.scala 83:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:83 assert (a_size < UInt(BigInt(1) << sizeBits))\n") @[ToAXI4.scala 83:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 83:14] + skip @[ToAXI4.scala 83:14] + node _T_572 = lt(_T_528, UInt<4>("h08")) @[ToAXI4.scala 84:25] + node _T_573 = or(_T_572, reset) @[ToAXI4.scala 84:14] + node _T_575 = eq(_T_573, UInt<1>("h00")) @[ToAXI4.scala 84:14] + when _T_575 : @[ToAXI4.scala 84:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:84 assert (a_addr_lo < UInt(BigInt(1) << addrBits))\n") @[ToAXI4.scala 84:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 84:14] + skip @[ToAXI4.scala 84:14] + node _T_576 = shl(io.in.0.a.bits.source, 0) @[ToAXI4.scala 93:31] + node _T_577 = shl(io.in.0.a.bits.size, 5) @[ToAXI4.scala 93:55] + node _T_578 = or(_T_576, _T_577) @[ToAXI4.scala 93:45] + node _T_579 = shl(_T_528, 9) @[ToAXI4.scala 93:80] + node _T_580 = or(_T_578, _T_579) @[ToAXI4.scala 93:67] + wire _T_582 : UInt<12> @[ToAXI4.scala 96:25] + _T_582 is invalid @[ToAXI4.scala 96:25] + node _T_583 = bits(_T_582, 4, 0) @[ToAXI4.scala 97:50] + node _T_584 = bits(_T_582, 8, 5) @[ToAXI4.scala 98:50] + node _T_585 = bits(_T_582, 11, 9) @[ToAXI4.scala 99:50] + wire _T_587 : UInt<12> @[ToAXI4.scala 101:25] + _T_587 is invalid @[ToAXI4.scala 101:25] + node _T_588 = bits(_T_587, 4, 0) @[ToAXI4.scala 102:50] + node _T_589 = bits(_T_587, 8, 5) @[ToAXI4.scala 103:50] + node _T_590 = bits(_T_587, 11, 9) @[ToAXI4.scala 104:50] + inst PositionalMultiQueue of PositionalMultiQueue @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue.io is invalid + PositionalMultiQueue.clock <= clock + PositionalMultiQueue.reset <= reset + inst PositionalMultiQueue_1 of PositionalMultiQueue_1 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_1.io is invalid + PositionalMultiQueue_1.clock <= clock + PositionalMultiQueue_1.reset <= reset + inst PositionalMultiQueue_2 of PositionalMultiQueue_2 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_2.io is invalid + PositionalMultiQueue_2.clock <= clock + PositionalMultiQueue_2.reset <= reset + inst PositionalMultiQueue_3 of PositionalMultiQueue_3 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_3.io is invalid + PositionalMultiQueue_3.clock <= clock + PositionalMultiQueue_3.reset <= reset + inst PositionalMultiQueue_4 of PositionalMultiQueue_4 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_4.io is invalid + PositionalMultiQueue_4.clock <= clock + PositionalMultiQueue_4.reset <= reset + inst PositionalMultiQueue_5 of PositionalMultiQueue_5 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_5.io is invalid + PositionalMultiQueue_5.clock <= clock + PositionalMultiQueue_5.reset <= reset + inst PositionalMultiQueue_6 of PositionalMultiQueue_6 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_6.io is invalid + PositionalMultiQueue_6.clock <= clock + PositionalMultiQueue_6.reset <= reset + inst PositionalMultiQueue_7 of PositionalMultiQueue_7 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_7.io is invalid + PositionalMultiQueue_7.clock <= clock + PositionalMultiQueue_7.reset <= reset + inst PositionalMultiQueue_8 of PositionalMultiQueue_8 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_8.io is invalid + PositionalMultiQueue_8.clock <= clock + PositionalMultiQueue_8.reset <= reset + inst PositionalMultiQueue_9 of PositionalMultiQueue_9 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_9.io is invalid + PositionalMultiQueue_9.clock <= clock + PositionalMultiQueue_9.reset <= reset + inst PositionalMultiQueue_10 of PositionalMultiQueue_10 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_10.io is invalid + PositionalMultiQueue_10.clock <= clock + PositionalMultiQueue_10.reset <= reset + inst PositionalMultiQueue_11 of PositionalMultiQueue_11 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_11.io is invalid + PositionalMultiQueue_11.clock <= clock + PositionalMultiQueue_11.reset <= reset + inst PositionalMultiQueue_12 of PositionalMultiQueue_12 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_12.io is invalid + PositionalMultiQueue_12.clock <= clock + PositionalMultiQueue_12.reset <= reset + inst PositionalMultiQueue_13 of PositionalMultiQueue_13 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_13.io is invalid + PositionalMultiQueue_13.clock <= clock + PositionalMultiQueue_13.reset <= reset + inst PositionalMultiQueue_14 of PositionalMultiQueue_14 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_14.io is invalid + PositionalMultiQueue_14.clock <= clock + PositionalMultiQueue_14.reset <= reset + inst PositionalMultiQueue_15 of PositionalMultiQueue_15 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_15.io is invalid + PositionalMultiQueue_15.clock <= clock + PositionalMultiQueue_15.reset <= reset + node _T_607 = bits(io.in.0.a.bits.source, 4, 4) @[ToAXI4.scala 129:69] + node _T_608 = bits(io.in.0.a.bits.source, 3, 0) @[ToAXI4.scala 130:72] + node _T_609 = bits(io.out.0.r.bits.id, 3, 0) @[ToAXI4.scala 131:68] + node _T_610 = bits(_T_517.bits.id, 3, 0) @[ToAXI4.scala 132:68] + node _T_612 = bits(_T_608, 3, 0) @[OneHot.scala 49:17] + node _T_613 = dshl(UInt<1>("h01"), _T_612) @[OneHot.scala 49:12] + node _T_614 = bits(_T_613, 15, 0) @[OneHot.scala 49:37] + node _T_616 = bits(_T_609, 3, 0) @[OneHot.scala 49:17] + node _T_617 = dshl(UInt<1>("h01"), _T_616) @[OneHot.scala 49:12] + node _T_618 = bits(_T_617, 15, 0) @[OneHot.scala 49:37] + node _T_620 = bits(_T_610, 3, 0) @[OneHot.scala 49:17] + node _T_621 = dshl(UInt<1>("h01"), _T_620) @[OneHot.scala 49:12] + node _T_622 = bits(_T_621, 15, 0) @[OneHot.scala 49:37] + node _T_623 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_624 = and(_T_623, _T_556) @[ToAXI4.scala 139:41] + node _T_625 = bits(_T_614, 0, 0) @[ToAXI4.scala 139:66] + node _T_626 = and(_T_624, _T_625) @[ToAXI4.scala 139:51] + PositionalMultiQueue.io.enq.valid <= _T_626 @[ToAXI4.scala 139:26] + PositionalMultiQueue.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_627 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue.io.enq.bits.data <= _T_627 @[ToAXI4.scala 141:30] + node _T_630 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue.io.enq.bits.way <= _T_630 @[ToAXI4.scala 142:30] + node _T_631 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_632 = bits(_T_622, 0, 0) @[ToAXI4.scala 144:60] + node _T_633 = and(_T_631, _T_632) @[ToAXI4.scala 144:45] + PositionalMultiQueue.io.deq[0].ready <= _T_633 @[ToAXI4.scala 144:29] + node _T_634 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_635 = bits(_T_618, 0, 0) @[ToAXI4.scala 145:60] + node _T_636 = and(_T_634, _T_635) @[ToAXI4.scala 145:45] + node _T_637 = and(_T_636, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue.io.deq[1].ready <= _T_637 @[ToAXI4.scala 145:29] + node _T_639 = eq(PositionalMultiQueue.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_640 = or(PositionalMultiQueue.io.deq[0].valid, _T_639) @[ToAXI4.scala 147:37] + node _T_641 = or(_T_640, reset) @[ToAXI4.scala 147:18] + node _T_643 = eq(_T_641, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_643 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_645 = eq(PositionalMultiQueue.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_646 = or(PositionalMultiQueue.io.deq[1].valid, _T_645) @[ToAXI4.scala 148:37] + node _T_647 = or(_T_646, reset) @[ToAXI4.scala 148:18] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_649 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_650 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_651 = and(_T_650, _T_556) @[ToAXI4.scala 139:41] + node _T_652 = bits(_T_614, 1, 1) @[ToAXI4.scala 139:66] + node _T_653 = and(_T_651, _T_652) @[ToAXI4.scala 139:51] + PositionalMultiQueue_1.io.enq.valid <= _T_653 @[ToAXI4.scala 139:26] + PositionalMultiQueue_1.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_654 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_1.io.enq.bits.data <= _T_654 @[ToAXI4.scala 141:30] + node _T_657 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_1.io.enq.bits.way <= _T_657 @[ToAXI4.scala 142:30] + node _T_658 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_659 = bits(_T_622, 1, 1) @[ToAXI4.scala 144:60] + node _T_660 = and(_T_658, _T_659) @[ToAXI4.scala 144:45] + PositionalMultiQueue_1.io.deq[0].ready <= _T_660 @[ToAXI4.scala 144:29] + node _T_661 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_662 = bits(_T_618, 1, 1) @[ToAXI4.scala 145:60] + node _T_663 = and(_T_661, _T_662) @[ToAXI4.scala 145:45] + node _T_664 = and(_T_663, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_1.io.deq[1].ready <= _T_664 @[ToAXI4.scala 145:29] + node _T_666 = eq(PositionalMultiQueue_1.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_667 = or(PositionalMultiQueue_1.io.deq[0].valid, _T_666) @[ToAXI4.scala 147:37] + node _T_668 = or(_T_667, reset) @[ToAXI4.scala 147:18] + node _T_670 = eq(_T_668, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_670 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_672 = eq(PositionalMultiQueue_1.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_673 = or(PositionalMultiQueue_1.io.deq[1].valid, _T_672) @[ToAXI4.scala 148:37] + node _T_674 = or(_T_673, reset) @[ToAXI4.scala 148:18] + node _T_676 = eq(_T_674, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_676 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_677 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_678 = and(_T_677, _T_556) @[ToAXI4.scala 139:41] + node _T_679 = bits(_T_614, 2, 2) @[ToAXI4.scala 139:66] + node _T_680 = and(_T_678, _T_679) @[ToAXI4.scala 139:51] + PositionalMultiQueue_2.io.enq.valid <= _T_680 @[ToAXI4.scala 139:26] + PositionalMultiQueue_2.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_681 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_2.io.enq.bits.data <= _T_681 @[ToAXI4.scala 141:30] + node _T_684 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_2.io.enq.bits.way <= _T_684 @[ToAXI4.scala 142:30] + node _T_685 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_686 = bits(_T_622, 2, 2) @[ToAXI4.scala 144:60] + node _T_687 = and(_T_685, _T_686) @[ToAXI4.scala 144:45] + PositionalMultiQueue_2.io.deq[0].ready <= _T_687 @[ToAXI4.scala 144:29] + node _T_688 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_689 = bits(_T_618, 2, 2) @[ToAXI4.scala 145:60] + node _T_690 = and(_T_688, _T_689) @[ToAXI4.scala 145:45] + node _T_691 = and(_T_690, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_2.io.deq[1].ready <= _T_691 @[ToAXI4.scala 145:29] + node _T_693 = eq(PositionalMultiQueue_2.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_694 = or(PositionalMultiQueue_2.io.deq[0].valid, _T_693) @[ToAXI4.scala 147:37] + node _T_695 = or(_T_694, reset) @[ToAXI4.scala 147:18] + node _T_697 = eq(_T_695, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_697 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_699 = eq(PositionalMultiQueue_2.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_700 = or(PositionalMultiQueue_2.io.deq[1].valid, _T_699) @[ToAXI4.scala 148:37] + node _T_701 = or(_T_700, reset) @[ToAXI4.scala 148:18] + node _T_703 = eq(_T_701, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_703 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_704 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_705 = and(_T_704, _T_556) @[ToAXI4.scala 139:41] + node _T_706 = bits(_T_614, 3, 3) @[ToAXI4.scala 139:66] + node _T_707 = and(_T_705, _T_706) @[ToAXI4.scala 139:51] + PositionalMultiQueue_3.io.enq.valid <= _T_707 @[ToAXI4.scala 139:26] + PositionalMultiQueue_3.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_708 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_3.io.enq.bits.data <= _T_708 @[ToAXI4.scala 141:30] + node _T_711 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_3.io.enq.bits.way <= _T_711 @[ToAXI4.scala 142:30] + node _T_712 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_713 = bits(_T_622, 3, 3) @[ToAXI4.scala 144:60] + node _T_714 = and(_T_712, _T_713) @[ToAXI4.scala 144:45] + PositionalMultiQueue_3.io.deq[0].ready <= _T_714 @[ToAXI4.scala 144:29] + node _T_715 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_716 = bits(_T_618, 3, 3) @[ToAXI4.scala 145:60] + node _T_717 = and(_T_715, _T_716) @[ToAXI4.scala 145:45] + node _T_718 = and(_T_717, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_3.io.deq[1].ready <= _T_718 @[ToAXI4.scala 145:29] + node _T_720 = eq(PositionalMultiQueue_3.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_721 = or(PositionalMultiQueue_3.io.deq[0].valid, _T_720) @[ToAXI4.scala 147:37] + node _T_722 = or(_T_721, reset) @[ToAXI4.scala 147:18] + node _T_724 = eq(_T_722, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_724 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_726 = eq(PositionalMultiQueue_3.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_727 = or(PositionalMultiQueue_3.io.deq[1].valid, _T_726) @[ToAXI4.scala 148:37] + node _T_728 = or(_T_727, reset) @[ToAXI4.scala 148:18] + node _T_730 = eq(_T_728, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_730 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_731 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_732 = and(_T_731, _T_556) @[ToAXI4.scala 139:41] + node _T_733 = bits(_T_614, 4, 4) @[ToAXI4.scala 139:66] + node _T_734 = and(_T_732, _T_733) @[ToAXI4.scala 139:51] + PositionalMultiQueue_4.io.enq.valid <= _T_734 @[ToAXI4.scala 139:26] + PositionalMultiQueue_4.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_735 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_4.io.enq.bits.data <= _T_735 @[ToAXI4.scala 141:30] + node _T_738 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_4.io.enq.bits.way <= _T_738 @[ToAXI4.scala 142:30] + node _T_739 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_740 = bits(_T_622, 4, 4) @[ToAXI4.scala 144:60] + node _T_741 = and(_T_739, _T_740) @[ToAXI4.scala 144:45] + PositionalMultiQueue_4.io.deq[0].ready <= _T_741 @[ToAXI4.scala 144:29] + node _T_742 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_743 = bits(_T_618, 4, 4) @[ToAXI4.scala 145:60] + node _T_744 = and(_T_742, _T_743) @[ToAXI4.scala 145:45] + node _T_745 = and(_T_744, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_4.io.deq[1].ready <= _T_745 @[ToAXI4.scala 145:29] + node _T_747 = eq(PositionalMultiQueue_4.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_748 = or(PositionalMultiQueue_4.io.deq[0].valid, _T_747) @[ToAXI4.scala 147:37] + node _T_749 = or(_T_748, reset) @[ToAXI4.scala 147:18] + node _T_751 = eq(_T_749, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_751 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_753 = eq(PositionalMultiQueue_4.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_754 = or(PositionalMultiQueue_4.io.deq[1].valid, _T_753) @[ToAXI4.scala 148:37] + node _T_755 = or(_T_754, reset) @[ToAXI4.scala 148:18] + node _T_757 = eq(_T_755, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_757 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_758 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_759 = and(_T_758, _T_556) @[ToAXI4.scala 139:41] + node _T_760 = bits(_T_614, 5, 5) @[ToAXI4.scala 139:66] + node _T_761 = and(_T_759, _T_760) @[ToAXI4.scala 139:51] + PositionalMultiQueue_5.io.enq.valid <= _T_761 @[ToAXI4.scala 139:26] + PositionalMultiQueue_5.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_762 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_5.io.enq.bits.data <= _T_762 @[ToAXI4.scala 141:30] + node _T_765 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_5.io.enq.bits.way <= _T_765 @[ToAXI4.scala 142:30] + node _T_766 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_767 = bits(_T_622, 5, 5) @[ToAXI4.scala 144:60] + node _T_768 = and(_T_766, _T_767) @[ToAXI4.scala 144:45] + PositionalMultiQueue_5.io.deq[0].ready <= _T_768 @[ToAXI4.scala 144:29] + node _T_769 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_770 = bits(_T_618, 5, 5) @[ToAXI4.scala 145:60] + node _T_771 = and(_T_769, _T_770) @[ToAXI4.scala 145:45] + node _T_772 = and(_T_771, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_5.io.deq[1].ready <= _T_772 @[ToAXI4.scala 145:29] + node _T_774 = eq(PositionalMultiQueue_5.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_775 = or(PositionalMultiQueue_5.io.deq[0].valid, _T_774) @[ToAXI4.scala 147:37] + node _T_776 = or(_T_775, reset) @[ToAXI4.scala 147:18] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_778 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_780 = eq(PositionalMultiQueue_5.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_781 = or(PositionalMultiQueue_5.io.deq[1].valid, _T_780) @[ToAXI4.scala 148:37] + node _T_782 = or(_T_781, reset) @[ToAXI4.scala 148:18] + node _T_784 = eq(_T_782, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_784 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_785 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_786 = and(_T_785, _T_556) @[ToAXI4.scala 139:41] + node _T_787 = bits(_T_614, 6, 6) @[ToAXI4.scala 139:66] + node _T_788 = and(_T_786, _T_787) @[ToAXI4.scala 139:51] + PositionalMultiQueue_6.io.enq.valid <= _T_788 @[ToAXI4.scala 139:26] + PositionalMultiQueue_6.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_789 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_6.io.enq.bits.data <= _T_789 @[ToAXI4.scala 141:30] + node _T_792 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_6.io.enq.bits.way <= _T_792 @[ToAXI4.scala 142:30] + node _T_793 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_794 = bits(_T_622, 6, 6) @[ToAXI4.scala 144:60] + node _T_795 = and(_T_793, _T_794) @[ToAXI4.scala 144:45] + PositionalMultiQueue_6.io.deq[0].ready <= _T_795 @[ToAXI4.scala 144:29] + node _T_796 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_797 = bits(_T_618, 6, 6) @[ToAXI4.scala 145:60] + node _T_798 = and(_T_796, _T_797) @[ToAXI4.scala 145:45] + node _T_799 = and(_T_798, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_6.io.deq[1].ready <= _T_799 @[ToAXI4.scala 145:29] + node _T_801 = eq(PositionalMultiQueue_6.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_802 = or(PositionalMultiQueue_6.io.deq[0].valid, _T_801) @[ToAXI4.scala 147:37] + node _T_803 = or(_T_802, reset) @[ToAXI4.scala 147:18] + node _T_805 = eq(_T_803, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_805 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_807 = eq(PositionalMultiQueue_6.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_808 = or(PositionalMultiQueue_6.io.deq[1].valid, _T_807) @[ToAXI4.scala 148:37] + node _T_809 = or(_T_808, reset) @[ToAXI4.scala 148:18] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_811 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_812 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_813 = and(_T_812, _T_556) @[ToAXI4.scala 139:41] + node _T_814 = bits(_T_614, 7, 7) @[ToAXI4.scala 139:66] + node _T_815 = and(_T_813, _T_814) @[ToAXI4.scala 139:51] + PositionalMultiQueue_7.io.enq.valid <= _T_815 @[ToAXI4.scala 139:26] + PositionalMultiQueue_7.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_816 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_7.io.enq.bits.data <= _T_816 @[ToAXI4.scala 141:30] + node _T_819 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_7.io.enq.bits.way <= _T_819 @[ToAXI4.scala 142:30] + node _T_820 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_821 = bits(_T_622, 7, 7) @[ToAXI4.scala 144:60] + node _T_822 = and(_T_820, _T_821) @[ToAXI4.scala 144:45] + PositionalMultiQueue_7.io.deq[0].ready <= _T_822 @[ToAXI4.scala 144:29] + node _T_823 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_824 = bits(_T_618, 7, 7) @[ToAXI4.scala 145:60] + node _T_825 = and(_T_823, _T_824) @[ToAXI4.scala 145:45] + node _T_826 = and(_T_825, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_7.io.deq[1].ready <= _T_826 @[ToAXI4.scala 145:29] + node _T_828 = eq(PositionalMultiQueue_7.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_829 = or(PositionalMultiQueue_7.io.deq[0].valid, _T_828) @[ToAXI4.scala 147:37] + node _T_830 = or(_T_829, reset) @[ToAXI4.scala 147:18] + node _T_832 = eq(_T_830, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_832 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_834 = eq(PositionalMultiQueue_7.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_835 = or(PositionalMultiQueue_7.io.deq[1].valid, _T_834) @[ToAXI4.scala 148:37] + node _T_836 = or(_T_835, reset) @[ToAXI4.scala 148:18] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_838 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_839 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_840 = and(_T_839, _T_556) @[ToAXI4.scala 139:41] + node _T_841 = bits(_T_614, 8, 8) @[ToAXI4.scala 139:66] + node _T_842 = and(_T_840, _T_841) @[ToAXI4.scala 139:51] + PositionalMultiQueue_8.io.enq.valid <= _T_842 @[ToAXI4.scala 139:26] + PositionalMultiQueue_8.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_843 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_8.io.enq.bits.data <= _T_843 @[ToAXI4.scala 141:30] + node _T_846 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_8.io.enq.bits.way <= _T_846 @[ToAXI4.scala 142:30] + node _T_847 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_848 = bits(_T_622, 8, 8) @[ToAXI4.scala 144:60] + node _T_849 = and(_T_847, _T_848) @[ToAXI4.scala 144:45] + PositionalMultiQueue_8.io.deq[0].ready <= _T_849 @[ToAXI4.scala 144:29] + node _T_850 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_851 = bits(_T_618, 8, 8) @[ToAXI4.scala 145:60] + node _T_852 = and(_T_850, _T_851) @[ToAXI4.scala 145:45] + node _T_853 = and(_T_852, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_8.io.deq[1].ready <= _T_853 @[ToAXI4.scala 145:29] + node _T_855 = eq(PositionalMultiQueue_8.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_856 = or(PositionalMultiQueue_8.io.deq[0].valid, _T_855) @[ToAXI4.scala 147:37] + node _T_857 = or(_T_856, reset) @[ToAXI4.scala 147:18] + node _T_859 = eq(_T_857, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_859 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_861 = eq(PositionalMultiQueue_8.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_862 = or(PositionalMultiQueue_8.io.deq[1].valid, _T_861) @[ToAXI4.scala 148:37] + node _T_863 = or(_T_862, reset) @[ToAXI4.scala 148:18] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_865 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_866 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_867 = and(_T_866, _T_556) @[ToAXI4.scala 139:41] + node _T_868 = bits(_T_614, 9, 9) @[ToAXI4.scala 139:66] + node _T_869 = and(_T_867, _T_868) @[ToAXI4.scala 139:51] + PositionalMultiQueue_9.io.enq.valid <= _T_869 @[ToAXI4.scala 139:26] + PositionalMultiQueue_9.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_870 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_9.io.enq.bits.data <= _T_870 @[ToAXI4.scala 141:30] + node _T_873 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_9.io.enq.bits.way <= _T_873 @[ToAXI4.scala 142:30] + node _T_874 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_875 = bits(_T_622, 9, 9) @[ToAXI4.scala 144:60] + node _T_876 = and(_T_874, _T_875) @[ToAXI4.scala 144:45] + PositionalMultiQueue_9.io.deq[0].ready <= _T_876 @[ToAXI4.scala 144:29] + node _T_877 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_878 = bits(_T_618, 9, 9) @[ToAXI4.scala 145:60] + node _T_879 = and(_T_877, _T_878) @[ToAXI4.scala 145:45] + node _T_880 = and(_T_879, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_9.io.deq[1].ready <= _T_880 @[ToAXI4.scala 145:29] + node _T_882 = eq(PositionalMultiQueue_9.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_883 = or(PositionalMultiQueue_9.io.deq[0].valid, _T_882) @[ToAXI4.scala 147:37] + node _T_884 = or(_T_883, reset) @[ToAXI4.scala 147:18] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_886 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_888 = eq(PositionalMultiQueue_9.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_889 = or(PositionalMultiQueue_9.io.deq[1].valid, _T_888) @[ToAXI4.scala 148:37] + node _T_890 = or(_T_889, reset) @[ToAXI4.scala 148:18] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_892 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_893 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_894 = and(_T_893, _T_556) @[ToAXI4.scala 139:41] + node _T_895 = bits(_T_614, 10, 10) @[ToAXI4.scala 139:66] + node _T_896 = and(_T_894, _T_895) @[ToAXI4.scala 139:51] + PositionalMultiQueue_10.io.enq.valid <= _T_896 @[ToAXI4.scala 139:26] + PositionalMultiQueue_10.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_897 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_10.io.enq.bits.data <= _T_897 @[ToAXI4.scala 141:30] + node _T_900 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_10.io.enq.bits.way <= _T_900 @[ToAXI4.scala 142:30] + node _T_901 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_902 = bits(_T_622, 10, 10) @[ToAXI4.scala 144:60] + node _T_903 = and(_T_901, _T_902) @[ToAXI4.scala 144:45] + PositionalMultiQueue_10.io.deq[0].ready <= _T_903 @[ToAXI4.scala 144:29] + node _T_904 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_905 = bits(_T_618, 10, 10) @[ToAXI4.scala 145:60] + node _T_906 = and(_T_904, _T_905) @[ToAXI4.scala 145:45] + node _T_907 = and(_T_906, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_10.io.deq[1].ready <= _T_907 @[ToAXI4.scala 145:29] + node _T_909 = eq(PositionalMultiQueue_10.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_910 = or(PositionalMultiQueue_10.io.deq[0].valid, _T_909) @[ToAXI4.scala 147:37] + node _T_911 = or(_T_910, reset) @[ToAXI4.scala 147:18] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_913 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_915 = eq(PositionalMultiQueue_10.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_916 = or(PositionalMultiQueue_10.io.deq[1].valid, _T_915) @[ToAXI4.scala 148:37] + node _T_917 = or(_T_916, reset) @[ToAXI4.scala 148:18] + node _T_919 = eq(_T_917, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_919 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_920 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_921 = and(_T_920, _T_556) @[ToAXI4.scala 139:41] + node _T_922 = bits(_T_614, 11, 11) @[ToAXI4.scala 139:66] + node _T_923 = and(_T_921, _T_922) @[ToAXI4.scala 139:51] + PositionalMultiQueue_11.io.enq.valid <= _T_923 @[ToAXI4.scala 139:26] + PositionalMultiQueue_11.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_924 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_11.io.enq.bits.data <= _T_924 @[ToAXI4.scala 141:30] + node _T_927 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_11.io.enq.bits.way <= _T_927 @[ToAXI4.scala 142:30] + node _T_928 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_929 = bits(_T_622, 11, 11) @[ToAXI4.scala 144:60] + node _T_930 = and(_T_928, _T_929) @[ToAXI4.scala 144:45] + PositionalMultiQueue_11.io.deq[0].ready <= _T_930 @[ToAXI4.scala 144:29] + node _T_931 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_932 = bits(_T_618, 11, 11) @[ToAXI4.scala 145:60] + node _T_933 = and(_T_931, _T_932) @[ToAXI4.scala 145:45] + node _T_934 = and(_T_933, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_11.io.deq[1].ready <= _T_934 @[ToAXI4.scala 145:29] + node _T_936 = eq(PositionalMultiQueue_11.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_937 = or(PositionalMultiQueue_11.io.deq[0].valid, _T_936) @[ToAXI4.scala 147:37] + node _T_938 = or(_T_937, reset) @[ToAXI4.scala 147:18] + node _T_940 = eq(_T_938, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_940 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_942 = eq(PositionalMultiQueue_11.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_943 = or(PositionalMultiQueue_11.io.deq[1].valid, _T_942) @[ToAXI4.scala 148:37] + node _T_944 = or(_T_943, reset) @[ToAXI4.scala 148:18] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_946 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_947 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_948 = and(_T_947, _T_556) @[ToAXI4.scala 139:41] + node _T_949 = bits(_T_614, 12, 12) @[ToAXI4.scala 139:66] + node _T_950 = and(_T_948, _T_949) @[ToAXI4.scala 139:51] + PositionalMultiQueue_12.io.enq.valid <= _T_950 @[ToAXI4.scala 139:26] + PositionalMultiQueue_12.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_951 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_12.io.enq.bits.data <= _T_951 @[ToAXI4.scala 141:30] + node _T_954 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_12.io.enq.bits.way <= _T_954 @[ToAXI4.scala 142:30] + node _T_955 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_956 = bits(_T_622, 12, 12) @[ToAXI4.scala 144:60] + node _T_957 = and(_T_955, _T_956) @[ToAXI4.scala 144:45] + PositionalMultiQueue_12.io.deq[0].ready <= _T_957 @[ToAXI4.scala 144:29] + node _T_958 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_959 = bits(_T_618, 12, 12) @[ToAXI4.scala 145:60] + node _T_960 = and(_T_958, _T_959) @[ToAXI4.scala 145:45] + node _T_961 = and(_T_960, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_12.io.deq[1].ready <= _T_961 @[ToAXI4.scala 145:29] + node _T_963 = eq(PositionalMultiQueue_12.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_964 = or(PositionalMultiQueue_12.io.deq[0].valid, _T_963) @[ToAXI4.scala 147:37] + node _T_965 = or(_T_964, reset) @[ToAXI4.scala 147:18] + node _T_967 = eq(_T_965, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_967 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_969 = eq(PositionalMultiQueue_12.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_970 = or(PositionalMultiQueue_12.io.deq[1].valid, _T_969) @[ToAXI4.scala 148:37] + node _T_971 = or(_T_970, reset) @[ToAXI4.scala 148:18] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_973 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_974 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_975 = and(_T_974, _T_556) @[ToAXI4.scala 139:41] + node _T_976 = bits(_T_614, 13, 13) @[ToAXI4.scala 139:66] + node _T_977 = and(_T_975, _T_976) @[ToAXI4.scala 139:51] + PositionalMultiQueue_13.io.enq.valid <= _T_977 @[ToAXI4.scala 139:26] + PositionalMultiQueue_13.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_978 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_13.io.enq.bits.data <= _T_978 @[ToAXI4.scala 141:30] + node _T_981 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_13.io.enq.bits.way <= _T_981 @[ToAXI4.scala 142:30] + node _T_982 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_983 = bits(_T_622, 13, 13) @[ToAXI4.scala 144:60] + node _T_984 = and(_T_982, _T_983) @[ToAXI4.scala 144:45] + PositionalMultiQueue_13.io.deq[0].ready <= _T_984 @[ToAXI4.scala 144:29] + node _T_985 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_986 = bits(_T_618, 13, 13) @[ToAXI4.scala 145:60] + node _T_987 = and(_T_985, _T_986) @[ToAXI4.scala 145:45] + node _T_988 = and(_T_987, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_13.io.deq[1].ready <= _T_988 @[ToAXI4.scala 145:29] + node _T_990 = eq(PositionalMultiQueue_13.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_991 = or(PositionalMultiQueue_13.io.deq[0].valid, _T_990) @[ToAXI4.scala 147:37] + node _T_992 = or(_T_991, reset) @[ToAXI4.scala 147:18] + node _T_994 = eq(_T_992, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_994 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_996 = eq(PositionalMultiQueue_13.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_997 = or(PositionalMultiQueue_13.io.deq[1].valid, _T_996) @[ToAXI4.scala 148:37] + node _T_998 = or(_T_997, reset) @[ToAXI4.scala 148:18] + node _T_1000 = eq(_T_998, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_1000 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_1001 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_1002 = and(_T_1001, _T_556) @[ToAXI4.scala 139:41] + node _T_1003 = bits(_T_614, 14, 14) @[ToAXI4.scala 139:66] + node _T_1004 = and(_T_1002, _T_1003) @[ToAXI4.scala 139:51] + PositionalMultiQueue_14.io.enq.valid <= _T_1004 @[ToAXI4.scala 139:26] + PositionalMultiQueue_14.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_1005 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_14.io.enq.bits.data <= _T_1005 @[ToAXI4.scala 141:30] + node _T_1008 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_14.io.enq.bits.way <= _T_1008 @[ToAXI4.scala 142:30] + node _T_1009 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_1010 = bits(_T_622, 14, 14) @[ToAXI4.scala 144:60] + node _T_1011 = and(_T_1009, _T_1010) @[ToAXI4.scala 144:45] + PositionalMultiQueue_14.io.deq[0].ready <= _T_1011 @[ToAXI4.scala 144:29] + node _T_1012 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_1013 = bits(_T_618, 14, 14) @[ToAXI4.scala 145:60] + node _T_1014 = and(_T_1012, _T_1013) @[ToAXI4.scala 145:45] + node _T_1015 = and(_T_1014, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_14.io.deq[1].ready <= _T_1015 @[ToAXI4.scala 145:29] + node _T_1017 = eq(PositionalMultiQueue_14.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_1018 = or(PositionalMultiQueue_14.io.deq[0].valid, _T_1017) @[ToAXI4.scala 147:37] + node _T_1019 = or(_T_1018, reset) @[ToAXI4.scala 147:18] + node _T_1021 = eq(_T_1019, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_1021 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_1023 = eq(PositionalMultiQueue_14.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_1024 = or(PositionalMultiQueue_14.io.deq[1].valid, _T_1023) @[ToAXI4.scala 148:37] + node _T_1025 = or(_T_1024, reset) @[ToAXI4.scala 148:18] + node _T_1027 = eq(_T_1025, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_1027 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_1028 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_1029 = and(_T_1028, _T_556) @[ToAXI4.scala 139:41] + node _T_1030 = bits(_T_614, 15, 15) @[ToAXI4.scala 139:66] + node _T_1031 = and(_T_1029, _T_1030) @[ToAXI4.scala 139:51] + PositionalMultiQueue_15.io.enq.valid <= _T_1031 @[ToAXI4.scala 139:26] + PositionalMultiQueue_15.io.enq.bits.pos <= _T_607 @[ToAXI4.scala 140:30] + node _T_1032 = shr(_T_580, 5) @[ToAXI4.scala 141:41] + PositionalMultiQueue_15.io.enq.bits.data <= _T_1032 @[ToAXI4.scala 141:30] + node _T_1035 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_15.io.enq.bits.way <= _T_1035 @[ToAXI4.scala 142:30] + node _T_1036 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_1037 = bits(_T_622, 15, 15) @[ToAXI4.scala 144:60] + node _T_1038 = and(_T_1036, _T_1037) @[ToAXI4.scala 144:45] + PositionalMultiQueue_15.io.deq[0].ready <= _T_1038 @[ToAXI4.scala 144:29] + node _T_1039 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_1040 = bits(_T_618, 15, 15) @[ToAXI4.scala 145:60] + node _T_1041 = and(_T_1039, _T_1040) @[ToAXI4.scala 145:45] + node _T_1042 = and(_T_1041, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_15.io.deq[1].ready <= _T_1042 @[ToAXI4.scala 145:29] + node _T_1044 = eq(PositionalMultiQueue_15.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_1045 = or(PositionalMultiQueue_15.io.deq[0].valid, _T_1044) @[ToAXI4.scala 147:37] + node _T_1046 = or(_T_1045, reset) @[ToAXI4.scala 147:18] + node _T_1048 = eq(_T_1046, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_1048 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_1050 = eq(PositionalMultiQueue_15.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_1051 = or(PositionalMultiQueue_15.io.deq[1].valid, _T_1050) @[ToAXI4.scala 148:37] + node _T_1052 = or(_T_1051, reset) @[ToAXI4.scala 148:18] + node _T_1054 = eq(_T_1052, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_1054 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + wire _T_1057 : UInt<7>[16] @[ToAXI4.scala 151:29] + _T_1057 is invalid @[ToAXI4.scala 151:29] + _T_1057[0] <= PositionalMultiQueue.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[1] <= PositionalMultiQueue_1.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[2] <= PositionalMultiQueue_2.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[3] <= PositionalMultiQueue_3.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[4] <= PositionalMultiQueue_4.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[5] <= PositionalMultiQueue_5.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[6] <= PositionalMultiQueue_6.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[7] <= PositionalMultiQueue_7.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[8] <= PositionalMultiQueue_8.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[9] <= PositionalMultiQueue_9.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[10] <= PositionalMultiQueue_10.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[11] <= PositionalMultiQueue_11.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[12] <= PositionalMultiQueue_12.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[13] <= PositionalMultiQueue_13.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[14] <= PositionalMultiQueue_14.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_1057[15] <= PositionalMultiQueue_15.io.deq[0].bits.data @[ToAXI4.scala 151:29] + wire _T_1079 : UInt<1>[16] @[ToAXI4.scala 152:29] + _T_1079 is invalid @[ToAXI4.scala 152:29] + _T_1079[0] <= PositionalMultiQueue.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[1] <= PositionalMultiQueue_1.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[2] <= PositionalMultiQueue_2.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[3] <= PositionalMultiQueue_3.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[4] <= PositionalMultiQueue_4.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[5] <= PositionalMultiQueue_5.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[6] <= PositionalMultiQueue_6.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[7] <= PositionalMultiQueue_7.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[8] <= PositionalMultiQueue_8.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[9] <= PositionalMultiQueue_9.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[10] <= PositionalMultiQueue_10.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[11] <= PositionalMultiQueue_11.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[12] <= PositionalMultiQueue_12.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[13] <= PositionalMultiQueue_13.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[14] <= PositionalMultiQueue_14.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_1079[15] <= PositionalMultiQueue_15.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + wire _T_1101 : UInt<7>[16] @[ToAXI4.scala 153:29] + _T_1101 is invalid @[ToAXI4.scala 153:29] + _T_1101[0] <= PositionalMultiQueue.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[1] <= PositionalMultiQueue_1.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[2] <= PositionalMultiQueue_2.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[3] <= PositionalMultiQueue_3.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[4] <= PositionalMultiQueue_4.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[5] <= PositionalMultiQueue_5.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[6] <= PositionalMultiQueue_6.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[7] <= PositionalMultiQueue_7.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[8] <= PositionalMultiQueue_8.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[9] <= PositionalMultiQueue_9.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[10] <= PositionalMultiQueue_10.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[11] <= PositionalMultiQueue_11.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[12] <= PositionalMultiQueue_12.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[13] <= PositionalMultiQueue_13.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[14] <= PositionalMultiQueue_14.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_1101[15] <= PositionalMultiQueue_15.io.deq[1].bits.data @[ToAXI4.scala 153:29] + wire _T_1123 : UInt<1>[16] @[ToAXI4.scala 154:29] + _T_1123 is invalid @[ToAXI4.scala 154:29] + _T_1123[0] <= PositionalMultiQueue.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[1] <= PositionalMultiQueue_1.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[2] <= PositionalMultiQueue_2.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[3] <= PositionalMultiQueue_3.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[4] <= PositionalMultiQueue_4.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[5] <= PositionalMultiQueue_5.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[6] <= PositionalMultiQueue_6.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[7] <= PositionalMultiQueue_7.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[8] <= PositionalMultiQueue_8.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[9] <= PositionalMultiQueue_9.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[10] <= PositionalMultiQueue_10.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[11] <= PositionalMultiQueue_11.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[12] <= PositionalMultiQueue_12.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[13] <= PositionalMultiQueue_13.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[14] <= PositionalMultiQueue_14.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_1123[15] <= PositionalMultiQueue_15.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + node _T_1143 = cat(_T_1057[_T_610], _T_1079[_T_610]) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_517.bits.id) @[Cat.scala 30:58] + _T_587 <= _T_1144 @[ToAXI4.scala 157:17] + node _T_1145 = cat(_T_1101[_T_609], _T_1123[_T_609]) @[Cat.scala 30:58] + node _T_1146 = cat(_T_1145, io.out.0.r.bits.id) @[Cat.scala 30:58] + _T_582 <= _T_1146 @[ToAXI4.scala 158:17] + wire _T_1185 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}} @[ToAXI4.scala 163:25] + _T_1185 is invalid @[ToAXI4.scala 163:25] + wire _T_1212 : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}} @[ToAXI4.scala 164:23] + _T_1212 is invalid @[ToAXI4.scala 164:23] + inst Queue_1 of Queue_5 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= _T_1212.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- _T_1212.bits @[Decoupled.scala 255:19] + _T_1212.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + wire _T_1242 : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}} @[Decoupled.scala 272:19] + _T_1242 is invalid @[Decoupled.scala 272:19] + _T_1242.bits <- Queue_1.io.deq.bits @[Decoupled.scala 273:14] + _T_1242.valid <= Queue_1.io.deq.valid @[Decoupled.scala 274:15] + Queue_1.io.deq.ready <= _T_1242.ready @[Decoupled.scala 275:15] + io.out.0.w <- _T_1242 @[ToAXI4.scala 165:13] + inst Queue_2 of Queue_6 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_1185.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_1185.bits @[Decoupled.scala 255:19] + _T_1185.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + wire _T_1293 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}} @[Decoupled.scala 272:19] + _T_1293 is invalid @[Decoupled.scala 272:19] + _T_1293.bits <- Queue_2.io.deq.bits @[Decoupled.scala 273:14] + _T_1293.valid <= Queue_2.io.deq.valid @[Decoupled.scala 274:15] + Queue_2.io.deq.ready <= _T_1293.ready @[Decoupled.scala 275:15] + io.out.0.ar.bits <- _T_1293.bits @[ToAXI4.scala 169:19] + io.out.0.aw.bits <- _T_1293.bits @[ToAXI4.scala 170:19] + node _T_1321 = eq(_T_1293.bits.wen, UInt<1>("h00")) @[ToAXI4.scala 171:42] + node _T_1322 = and(_T_1293.valid, _T_1321) @[ToAXI4.scala 171:39] + io.out.0.ar.valid <= _T_1322 @[ToAXI4.scala 171:20] + node _T_1323 = and(_T_1293.valid, _T_1293.bits.wen) @[ToAXI4.scala 172:39] + io.out.0.aw.valid <= _T_1323 @[ToAXI4.scala 172:20] + node _T_1324 = mux(_T_1293.bits.wen, io.out.0.aw.ready, io.out.0.ar.ready) @[ToAXI4.scala 173:29] + _T_1293.ready <= _T_1324 @[ToAXI4.scala 173:23] + reg _T_1327 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1328 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + when _T_1328 : @[ToAXI4.scala 178:26] + node _T_1330 = eq(_T_556, UInt<1>("h00")) @[ToAXI4.scala 178:38] + _T_1327 <= _T_1330 @[ToAXI4.scala 178:35] + skip @[ToAXI4.scala 178:26] + _T_1185.bits.wen <= _T_531 @[ToAXI4.scala 181:17] + _T_1185.bits.id <= _T_580 @[ToAXI4.scala 182:17] + _T_1185.bits.addr <= io.in.0.a.bits.address @[ToAXI4.scala 183:17] + node _T_1332 = asUInt(asSInt(UInt<11>("h07ff"))) @[package.scala 19:64] + node _T_1333 = dshl(_T_1332, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_1334 = bits(_T_1333, 10, 0) @[package.scala 19:76] + node _T_1335 = not(_T_1334) @[package.scala 19:40] + node _T_1336 = shr(_T_1335, 3) @[ToAXI4.scala 184:84] + _T_1185.bits.len <= _T_1336 @[ToAXI4.scala 184:17] + node _T_1337 = geq(io.in.0.a.bits.size, UInt<2>("h03")) @[ToAXI4.scala 185:31] + node _T_1338 = mux(_T_1337, UInt<2>("h03"), io.in.0.a.bits.size) @[ToAXI4.scala 185:23] + _T_1185.bits.size <= _T_1338 @[ToAXI4.scala 185:17] + _T_1185.bits.burst <= UInt<2>("h01") @[ToAXI4.scala 186:17] + _T_1185.bits.lock <= UInt<1>("h00") @[ToAXI4.scala 187:17] + _T_1185.bits.cache <= UInt<1>("h00") @[ToAXI4.scala 188:17] + _T_1185.bits.prot <= UInt<3>("h01") @[ToAXI4.scala 189:17] + _T_1185.bits.qos <= UInt<1>("h00") @[ToAXI4.scala 190:17] + node _T_1344 = or(_T_1327, _T_1185.ready) @[ToAXI4.scala 192:42] + node _T_1345 = and(_T_1344, _T_1212.ready) @[ToAXI4.scala 192:60] + node _T_1346 = mux(_T_531, _T_1345, _T_1185.ready) @[ToAXI4.scala 192:24] + io.in.0.a.ready <= _T_1346 @[ToAXI4.scala 192:18] + node _T_1348 = eq(_T_1327, UInt<1>("h00")) @[ToAXI4.scala 193:51] + node _T_1349 = and(_T_1348, _T_1212.ready) @[ToAXI4.scala 193:59] + node _T_1351 = mux(_T_531, _T_1349, UInt<1>("h01")) @[ToAXI4.scala 193:41] + node _T_1352 = and(io.in.0.a.valid, _T_1351) @[ToAXI4.scala 193:35] + _T_1185.valid <= _T_1352 @[ToAXI4.scala 193:21] + node _T_1353 = and(io.in.0.a.valid, _T_531) @[ToAXI4.scala 195:33] + node _T_1354 = or(_T_1327, _T_1185.ready) @[ToAXI4.scala 195:55] + node _T_1355 = and(_T_1353, _T_1354) @[ToAXI4.scala 195:44] + _T_1212.valid <= _T_1355 @[ToAXI4.scala 195:19] + _T_1212.bits.data <= io.in.0.a.bits.data @[ToAXI4.scala 196:23] + _T_1212.bits.strb <= io.in.0.a.bits.mask @[ToAXI4.scala 197:23] + _T_1212.bits.last <= _T_556 @[ToAXI4.scala 198:23] + reg _T_1357 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1358 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + when _T_1358 : @[ToAXI4.scala 202:27] + node _T_1360 = eq(io.out.0.r.bits.last, UInt<1>("h00")) @[ToAXI4.scala 202:42] + _T_1357 <= _T_1360 @[ToAXI4.scala 202:39] + skip @[ToAXI4.scala 202:27] + node _T_1361 = or(io.out.0.r.valid, _T_1357) @[ToAXI4.scala 204:32] + io.out.0.r.ready <= io.in.0.d.ready @[ToAXI4.scala 206:19] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[ToAXI4.scala 207:36] + node _T_1364 = and(io.in.0.d.ready, _T_1363) @[ToAXI4.scala 207:33] + _T_517.ready <= _T_1364 @[ToAXI4.scala 207:19] + node _T_1365 = mux(_T_1361, io.out.0.r.valid, _T_517.valid) @[ToAXI4.scala 208:24] + io.in.0.d.valid <= _T_1365 @[ToAXI4.scala 208:18] + node _T_1367 = neq(io.out.0.r.bits.resp, UInt<2>("h00")) @[ToAXI4.scala 210:37] + node _T_1369 = neq(_T_517.bits.resp, UInt<2>("h00")) @[ToAXI4.scala 211:37] + wire _T_1381 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 633:17] + _T_1381 is invalid @[Edges.scala 633:17] + _T_1381.opcode <= UInt<1>("h01") @[Edges.scala 634:15] + _T_1381.param <= UInt<1>("h00") @[Edges.scala 635:15] + _T_1381.size <= _T_584 @[Edges.scala 636:15] + _T_1381.source <= _T_583 @[Edges.scala 637:15] + _T_1381.sink <= UInt<1>("h00") @[Edges.scala 638:15] + node _T_1392 = bits(_T_585, 2, 0) @[Edges.scala 172:47] + _T_1381.addr_lo <= _T_1392 @[Edges.scala 639:15] + _T_1381.data <= UInt<1>("h00") @[Edges.scala 640:15] + _T_1381.error <= _T_1367 @[Edges.scala 641:15] + wire _T_1403 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_1403 is invalid @[Edges.scala 617:17] + _T_1403.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_1403.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_1403.size <= _T_589 @[Edges.scala 620:15] + _T_1403.source <= _T_588 @[Edges.scala 621:15] + _T_1403.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_1414 = bits(_T_590, 2, 0) @[Edges.scala 172:47] + _T_1403.addr_lo <= _T_1414 @[Edges.scala 623:15] + _T_1403.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_1403.error <= _T_1369 @[Edges.scala 625:15] + node _T_1416 = mux(_T_1361, _T_1381, _T_1403) @[ToAXI4.scala 216:23] + io.in.0.d.bits <- _T_1416 @[ToAXI4.scala 216:17] + io.in.0.d.bits.data <= io.out.0.r.bits.data @[ToAXI4.scala 217:22] + io.in.0.b.valid <= UInt<1>("h00") @[ToAXI4.scala 220:18] + io.in.0.c.ready <= UInt<1>("h01") @[ToAXI4.scala 221:18] + io.in.0.e.ready <= UInt<1>("h01") @[ToAXI4.scala 222:18] + + module Queue_7 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_8 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_50 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_52 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_53 = and(_T_50, _T_52) @[Decoupled.scala 188:33] + node _T_54 = and(_T_50, maybe_full) @[Decoupled.scala 189:32] + node _T_55 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_55 + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_56 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_57 = ram[value], clock + _T_57 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_63 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_64 = tail(_T_63, 1) @[Counter.scala 26:22] + value <= _T_64 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_67 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_68 = tail(_T_67, 1) @[Counter.scala 26:22] + value_1 <= _T_68 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_69 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_69 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_71 = eq(_T_53, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_71 @[Decoupled.scala 204:16] + node _T_73 = eq(_T_54, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_73 @[Decoupled.scala 205:16] + infer mport _T_74 = ram[value_1], clock + io.deq.bits <- _T_74 @[Decoupled.scala 206:15] + node _T_78 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_79 = asUInt(_T_78) @[Decoupled.scala 221:40] + node _T_80 = tail(_T_79, 1) @[Decoupled.scala 221:40] + node _T_81 = and(maybe_full, _T_50) @[Decoupled.scala 223:32] + node _T_82 = cat(_T_81, _T_80) @[Cat.scala 30:58] + io.count <= _T_82 @[Decoupled.scala 223:14] + + module Queue_9 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module Queue_10 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_11 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_57 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_59 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_60 = and(_T_57, _T_59) @[Decoupled.scala 188:33] + node _T_61 = and(_T_57, maybe_full) @[Decoupled.scala 189:32] + node _T_62 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_62 + node _T_63 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_63 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_64 = ram[value], clock + _T_64 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_71 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_72 = tail(_T_71, 1) @[Counter.scala 26:22] + value <= _T_72 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_75 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_76 = tail(_T_75, 1) @[Counter.scala 26:22] + value_1 <= _T_76 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_77 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_77 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_79 = eq(_T_60, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_79 @[Decoupled.scala 204:16] + node _T_81 = eq(_T_61, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_81 @[Decoupled.scala 205:16] + infer mport _T_82 = ram[value_1], clock + io.deq.bits <- _T_82 @[Decoupled.scala 206:15] + node _T_87 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_88 = asUInt(_T_87) @[Decoupled.scala 221:40] + node _T_89 = tail(_T_88, 1) @[Decoupled.scala 221:40] + node _T_90 = and(maybe_full, _T_57) @[Decoupled.scala 223:32] + node _T_91 = cat(_T_90, _T_89) @[Cat.scala 30:58] + io.count <= _T_91 @[Decoupled.scala 223:14] + + module AXI4Buffer_rocketchipPeripheryMasterAXI4Membuffer : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_7 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.aw <- Queue.io.deq @[Buffer.scala 31:26] + inst Queue_1 of Queue_8 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.w.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.w.bits @[Decoupled.scala 255:19] + io.in.0.w.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.w <- Queue_1.io.deq @[Buffer.scala 32:26] + inst Queue_2 of Queue_9 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.b <- Queue_2.io.deq @[Buffer.scala 33:26] + inst Queue_3 of Queue_10 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_3.io.deq @[Buffer.scala 34:26] + inst Queue_4 of Queue_11 @[Decoupled.scala 253:19] + Queue_4.io is invalid + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= io.out.0.r.valid @[Decoupled.scala 254:20] + Queue_4.io.enq.bits <- io.out.0.r.bits @[Decoupled.scala 255:19] + io.out.0.r.ready <= Queue_4.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.r <- Queue_4.io.deq @[Buffer.scala 35:26] + + module TLMonitor_4 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 117:20] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 117:20] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_608 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:117:20)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + when _T_700 : @[Periphery.scala 117:20] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_712 = and(_T_703, _T_711) @[Parameters.scala 132:56] + node _T_714 = or(UInt<1>("h00"), _T_712) @[Parameters.scala 134:30] + node _T_715 = or(_T_714, reset) @[Periphery.scala 117:20] + node _T_717 = eq(_T_715, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_717 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_718 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_720 = eq(_T_718, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_720 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_722 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_723 = or(_T_722, reset) @[Periphery.scala 117:20] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_725 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_726 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_728 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_730 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_731 = or(_T_730, reset) @[Periphery.scala 117:20] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_733 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:117:20)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_734 = not(io.in[0].a.bits.mask) @[Periphery.scala 117:20] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_737 = or(_T_736, reset) @[Periphery.scala 117:20] + node _T_739 = eq(_T_737, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_739 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_741 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 117:20] + when _T_741 : @[Periphery.scala 117:20] + node _T_744 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_746 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_747 = and(_T_744, _T_746) @[Parameters.scala 63:37] + node _T_748 = or(UInt<1>("h00"), _T_747) @[Parameters.scala 132:31] + node _T_750 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_751 = cvt(_T_750) @[Parameters.scala 117:49] + node _T_753 = and(_T_751, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_754 = asSInt(_T_753) @[Parameters.scala 117:52] + node _T_756 = eq(_T_754, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_757 = and(_T_748, _T_756) @[Parameters.scala 132:56] + node _T_759 = or(UInt<1>("h00"), _T_757) @[Parameters.scala 134:30] + node _T_760 = or(_T_759, reset) @[Periphery.scala 117:20] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_762 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_763 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_765 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_766 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_768 = eq(_T_766, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_768 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_770 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_771 = or(_T_770, reset) @[Periphery.scala 117:20] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_773 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_774 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 117:20] + node _T_775 = or(_T_774, reset) @[Periphery.scala 117:20] + node _T_777 = eq(_T_775, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_777 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_779 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_779 : @[Periphery.scala 117:20] + node _T_782 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_784 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_785 = and(_T_782, _T_784) @[Parameters.scala 63:37] + node _T_786 = or(UInt<1>("h00"), _T_785) @[Parameters.scala 132:31] + node _T_788 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_789 = cvt(_T_788) @[Parameters.scala 117:49] + node _T_791 = and(_T_789, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_792 = asSInt(_T_791) @[Parameters.scala 117:52] + node _T_794 = eq(_T_792, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_795 = and(_T_786, _T_794) @[Parameters.scala 132:56] + node _T_797 = or(UInt<1>("h00"), _T_795) @[Parameters.scala 134:30] + node _T_798 = or(_T_797, reset) @[Periphery.scala 117:20] + node _T_800 = eq(_T_798, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_800 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_801 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_803 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_804 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_806 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_808 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_809 = or(_T_808, reset) @[Periphery.scala 117:20] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_811 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_812 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 117:20] + node _T_813 = or(_T_812, reset) @[Periphery.scala 117:20] + node _T_815 = eq(_T_813, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_815 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_817 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 117:20] + when _T_817 : @[Periphery.scala 117:20] + node _T_820 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_822 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_823 = and(_T_820, _T_822) @[Parameters.scala 63:37] + node _T_824 = or(UInt<1>("h00"), _T_823) @[Parameters.scala 132:31] + node _T_826 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = and(_T_824, _T_832) @[Parameters.scala 132:56] + node _T_835 = or(UInt<1>("h00"), _T_833) @[Parameters.scala 134:30] + node _T_836 = or(_T_835, reset) @[Periphery.scala 117:20] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_838 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_839 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_841 = eq(_T_839, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_841 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_842 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_844 = eq(_T_842, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_844 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_846 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_847 = or(_T_846, reset) @[Periphery.scala 117:20] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_849 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_850 = not(_T_698) @[Periphery.scala 117:20] + node _T_851 = and(io.in[0].a.bits.mask, _T_850) @[Periphery.scala 117:20] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_854 = or(_T_853, reset) @[Periphery.scala 117:20] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_856 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_858 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 117:20] + when _T_858 : @[Periphery.scala 117:20] + node _T_861 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_863 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_864 = cvt(_T_863) @[Parameters.scala 117:49] + node _T_866 = and(_T_864, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_867 = asSInt(_T_866) @[Parameters.scala 117:52] + node _T_869 = eq(_T_867, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = and(_T_861, _T_869) @[Parameters.scala 132:56] + node _T_872 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 134:30] + node _T_873 = or(_T_872, reset) @[Periphery.scala 117:20] + node _T_875 = eq(_T_873, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_875 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_876 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_878 = eq(_T_876, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_878 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_879 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_881 = eq(_T_879, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_881 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_883 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_884 = or(_T_883, reset) @[Periphery.scala 117:20] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_886 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:117:20)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_887 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 117:20] + node _T_888 = or(_T_887, reset) @[Periphery.scala 117:20] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_890 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_892 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 117:20] + when _T_892 : @[Periphery.scala 117:20] + node _T_895 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_897 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = and(_T_895, _T_903) @[Parameters.scala 132:56] + node _T_906 = or(UInt<1>("h00"), _T_904) @[Parameters.scala 134:30] + node _T_907 = or(_T_906, reset) @[Periphery.scala 117:20] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_909 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_910 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_912 = eq(_T_910, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_912 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_913 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_915 = eq(_T_913, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_915 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_917 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_918 = or(_T_917, reset) @[Periphery.scala 117:20] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_920 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:117:20)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_921 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 117:20] + node _T_922 = or(_T_921, reset) @[Periphery.scala 117:20] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_924 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 117:20] + when _T_926 : @[Periphery.scala 117:20] + node _T_929 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_931 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = and(_T_929, _T_937) @[Parameters.scala 132:56] + node _T_940 = or(UInt<1>("h00"), _T_938) @[Parameters.scala 134:30] + node _T_941 = or(_T_940, reset) @[Periphery.scala 117:20] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_943 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_944 = or(_T_619[0], reset) @[Periphery.scala 117:20] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_946 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_947 = or(_T_630, reset) @[Periphery.scala 117:20] + node _T_949 = eq(_T_947, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_949 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_950 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 117:20] + node _T_951 = or(_T_950, reset) @[Periphery.scala 117:20] + node _T_953 = eq(_T_951, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_953 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + when io.in[0].b.valid : @[Periphery.scala 117:20] + node _T_955 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_956 = or(_T_955, reset) @[Periphery.scala 117:20] + node _T_958 = eq(_T_956, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_958 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:117:20)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_960 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_961 = cvt(_T_960) @[Parameters.scala 117:49] + node _T_963 = and(_T_961, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_964 = asSInt(_T_963) @[Parameters.scala 117:52] + node _T_966 = eq(_T_964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_969 : UInt<1>[1] @[Parameters.scala 110:36] + _T_969 is invalid @[Parameters.scala 110:36] + _T_969[0] <= _T_966 @[Parameters.scala 110:36] + node _T_974 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_975 = dshl(_T_974, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_976 = bits(_T_975, 7, 0) @[package.scala 19:76] + node _T_977 = not(_T_976) @[package.scala 19:40] + node _T_978 = and(io.in[0].b.bits.address, _T_977) @[Edges.scala 17:16] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_982 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_983 = dshl(UInt<1>("h01"), _T_982) @[OneHot.scala 49:12] + node _T_984 = bits(_T_983, 2, 0) @[OneHot.scala 49:37] + node _T_986 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_988 = bits(_T_984, 2, 2) @[package.scala 44:26] + node _T_989 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_991 = eq(_T_989, UInt<1>("h00")) @[package.scala 46:20] + node _T_992 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_993 = and(_T_988, _T_992) @[package.scala 50:38] + node _T_994 = or(_T_986, _T_993) @[package.scala 50:29] + node _T_995 = and(UInt<1>("h01"), _T_989) @[package.scala 49:27] + node _T_996 = and(_T_988, _T_995) @[package.scala 50:38] + node _T_997 = or(_T_986, _T_996) @[package.scala 50:29] + node _T_998 = bits(_T_984, 1, 1) @[package.scala 44:26] + node _T_999 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1001 = eq(_T_999, UInt<1>("h00")) @[package.scala 46:20] + node _T_1002 = and(_T_992, _T_1001) @[package.scala 49:27] + node _T_1003 = and(_T_998, _T_1002) @[package.scala 50:38] + node _T_1004 = or(_T_994, _T_1003) @[package.scala 50:29] + node _T_1005 = and(_T_992, _T_999) @[package.scala 49:27] + node _T_1006 = and(_T_998, _T_1005) @[package.scala 50:38] + node _T_1007 = or(_T_994, _T_1006) @[package.scala 50:29] + node _T_1008 = and(_T_995, _T_1001) @[package.scala 49:27] + node _T_1009 = and(_T_998, _T_1008) @[package.scala 50:38] + node _T_1010 = or(_T_997, _T_1009) @[package.scala 50:29] + node _T_1011 = and(_T_995, _T_999) @[package.scala 49:27] + node _T_1012 = and(_T_998, _T_1011) @[package.scala 50:38] + node _T_1013 = or(_T_997, _T_1012) @[package.scala 50:29] + node _T_1014 = bits(_T_984, 0, 0) @[package.scala 44:26] + node _T_1015 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1017 = eq(_T_1015, UInt<1>("h00")) @[package.scala 46:20] + node _T_1018 = and(_T_1002, _T_1017) @[package.scala 49:27] + node _T_1019 = and(_T_1014, _T_1018) @[package.scala 50:38] + node _T_1020 = or(_T_1004, _T_1019) @[package.scala 50:29] + node _T_1021 = and(_T_1002, _T_1015) @[package.scala 49:27] + node _T_1022 = and(_T_1014, _T_1021) @[package.scala 50:38] + node _T_1023 = or(_T_1004, _T_1022) @[package.scala 50:29] + node _T_1024 = and(_T_1005, _T_1017) @[package.scala 49:27] + node _T_1025 = and(_T_1014, _T_1024) @[package.scala 50:38] + node _T_1026 = or(_T_1007, _T_1025) @[package.scala 50:29] + node _T_1027 = and(_T_1005, _T_1015) @[package.scala 49:27] + node _T_1028 = and(_T_1014, _T_1027) @[package.scala 50:38] + node _T_1029 = or(_T_1007, _T_1028) @[package.scala 50:29] + node _T_1030 = and(_T_1008, _T_1017) @[package.scala 49:27] + node _T_1031 = and(_T_1014, _T_1030) @[package.scala 50:38] + node _T_1032 = or(_T_1010, _T_1031) @[package.scala 50:29] + node _T_1033 = and(_T_1008, _T_1015) @[package.scala 49:27] + node _T_1034 = and(_T_1014, _T_1033) @[package.scala 50:38] + node _T_1035 = or(_T_1010, _T_1034) @[package.scala 50:29] + node _T_1036 = and(_T_1011, _T_1017) @[package.scala 49:27] + node _T_1037 = and(_T_1014, _T_1036) @[package.scala 50:38] + node _T_1038 = or(_T_1013, _T_1037) @[package.scala 50:29] + node _T_1039 = and(_T_1011, _T_1015) @[package.scala 49:27] + node _T_1040 = and(_T_1014, _T_1039) @[package.scala 50:38] + node _T_1041 = or(_T_1013, _T_1040) @[package.scala 50:29] + node _T_1042 = cat(_T_1023, _T_1020) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1029, _T_1026) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1035, _T_1032) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1041, _T_1038) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1050 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + when _T_1050 : @[Periphery.scala 117:20] + node _T_1052 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1054 = eq(_T_1052, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1054 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1055 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1057 = eq(_T_1055, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1057 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1059 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1060 = or(_T_1059, reset) @[Periphery.scala 117:20] + node _T_1062 = eq(_T_1060, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1062 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1063 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1065 = eq(_T_1063, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1065 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1067 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1068 = or(_T_1067, reset) @[Periphery.scala 117:20] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1070 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:117:20)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1071 = not(io.in[0].b.bits.mask) @[Periphery.scala 117:20] + node _T_1073 = eq(_T_1071, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 117:20] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1076 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1078 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 117:20] + when _T_1078 : @[Periphery.scala 117:20] + node _T_1080 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1082 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1083 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1085 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1086 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1088 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1090 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1091 = or(_T_1090, reset) @[Periphery.scala 117:20] + node _T_1093 = eq(_T_1091, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1093 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1094 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 117:20] + node _T_1095 = or(_T_1094, reset) @[Periphery.scala 117:20] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1097 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1099 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1099 : @[Periphery.scala 117:20] + node _T_1101 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1103 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1104 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1106 = eq(_T_1104, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1106 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1107 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1109 = eq(_T_1107, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1109 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1111 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1112 = or(_T_1111, reset) @[Periphery.scala 117:20] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1114 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1115 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 117:20] + node _T_1116 = or(_T_1115, reset) @[Periphery.scala 117:20] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1118 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1120 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 117:20] + when _T_1120 : @[Periphery.scala 117:20] + node _T_1122 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1124 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1125 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1127 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1128 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1130 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1132 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1133 = or(_T_1132, reset) @[Periphery.scala 117:20] + node _T_1135 = eq(_T_1133, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1135 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1136 = not(_T_1048) @[Periphery.scala 117:20] + node _T_1137 = and(io.in[0].b.bits.mask, _T_1136) @[Periphery.scala 117:20] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1140 = or(_T_1139, reset) @[Periphery.scala 117:20] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1142 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 117:20] + when _T_1144 : @[Periphery.scala 117:20] + node _T_1146 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1148 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1149 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1151 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1152 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1154 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1156 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1157 = or(_T_1156, reset) @[Periphery.scala 117:20] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1159 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:117:20)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 117:20] + node _T_1161 = or(_T_1160, reset) @[Periphery.scala 117:20] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1163 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 117:20] + when _T_1165 : @[Periphery.scala 117:20] + node _T_1167 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1169 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1170 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1172 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1173 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1175 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1177 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1178 = or(_T_1177, reset) @[Periphery.scala 117:20] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1180 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:117:20)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1181 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 117:20] + node _T_1182 = or(_T_1181, reset) @[Periphery.scala 117:20] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1184 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1186 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 117:20] + when _T_1186 : @[Periphery.scala 117:20] + node _T_1188 = or(UInt<1>("h00"), reset) @[Periphery.scala 117:20] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1190 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:117:20)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1191 = or(_T_969[0], reset) @[Periphery.scala 117:20] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1193 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1194 = or(_T_980, reset) @[Periphery.scala 117:20] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1196 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1197 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 117:20] + node _T_1198 = or(_T_1197, reset) @[Periphery.scala 117:20] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1200 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:117:20)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + when io.in[0].c.valid : @[Periphery.scala 117:20] + node _T_1202 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1203 = or(_T_1202, reset) @[Periphery.scala 117:20] + node _T_1205 = eq(_T_1203, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1205 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:117:20)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1207 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1208 = not(_T_1207) @[Parameters.scala 37:9] + node _T_1210 = or(_T_1208, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1211 = not(_T_1210) @[Parameters.scala 37:7] + node _T_1213 = eq(_T_1211, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1216 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1216 is invalid @[Parameters.scala 228:27] + _T_1216[0] <= _T_1213 @[Parameters.scala 228:27] + node _T_1221 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1222 = dshl(_T_1221, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1223 = bits(_T_1222, 7, 0) @[package.scala 19:76] + node _T_1224 = not(_T_1223) @[package.scala 19:40] + node _T_1225 = and(io.in[0].c.bits.address, _T_1224) @[Edges.scala 17:16] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1229 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1230 = cvt(_T_1229) @[Parameters.scala 117:49] + node _T_1232 = and(_T_1230, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1233 = asSInt(_T_1232) @[Parameters.scala 117:52] + node _T_1235 = eq(_T_1233, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1238 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1238 is invalid @[Parameters.scala 110:36] + _T_1238[0] <= _T_1235 @[Parameters.scala 110:36] + node _T_1243 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 117:20] + when _T_1243 : @[Periphery.scala 117:20] + node _T_1244 = or(_T_1238[0], reset) @[Periphery.scala 117:20] + node _T_1246 = eq(_T_1244, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1246 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1247 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1249 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1251 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1252 = or(_T_1251, reset) @[Periphery.scala 117:20] + node _T_1254 = eq(_T_1252, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1254 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1255 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1257 = eq(_T_1255, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1257 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1259 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1260 = or(_T_1259, reset) @[Periphery.scala 117:20] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1262 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:117:20)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1264 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1265 = or(_T_1264, reset) @[Periphery.scala 117:20] + node _T_1267 = eq(_T_1265, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1267 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1269 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 117:20] + when _T_1269 : @[Periphery.scala 117:20] + node _T_1270 = or(_T_1238[0], reset) @[Periphery.scala 117:20] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1272 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1273 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1275 = eq(_T_1273, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1275 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1277 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1278 = or(_T_1277, reset) @[Periphery.scala 117:20] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1280 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1281 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1283 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1285 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1286 = or(_T_1285, reset) @[Periphery.scala 117:20] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1288 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:117:20)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1290 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1291 = or(_T_1290, reset) @[Periphery.scala 117:20] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1293 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1295 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + when _T_1295 : @[Periphery.scala 117:20] + node _T_1298 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1300 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1301 = cvt(_T_1300) @[Parameters.scala 117:49] + node _T_1303 = and(_T_1301, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1304 = asSInt(_T_1303) @[Parameters.scala 117:52] + node _T_1306 = eq(_T_1304, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1307 = and(_T_1298, _T_1306) @[Parameters.scala 132:56] + node _T_1309 = or(UInt<1>("h00"), _T_1307) @[Parameters.scala 134:30] + node _T_1310 = or(_T_1309, reset) @[Periphery.scala 117:20] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1312 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1313 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1315 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1317 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1318 = or(_T_1317, reset) @[Periphery.scala 117:20] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1320 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1321 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1323 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1325 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1326 = or(_T_1325, reset) @[Periphery.scala 117:20] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1328 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:117:20)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1330 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 117:20] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1333 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1335 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 117:20] + when _T_1335 : @[Periphery.scala 117:20] + node _T_1338 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1340 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1341 = cvt(_T_1340) @[Parameters.scala 117:49] + node _T_1343 = and(_T_1341, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1344 = asSInt(_T_1343) @[Parameters.scala 117:52] + node _T_1346 = eq(_T_1344, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1347 = and(_T_1338, _T_1346) @[Parameters.scala 132:56] + node _T_1349 = or(UInt<1>("h00"), _T_1347) @[Parameters.scala 134:30] + node _T_1350 = or(_T_1349, reset) @[Periphery.scala 117:20] + node _T_1352 = eq(_T_1350, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1352 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:117:20)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1353 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1355 = eq(_T_1353, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1355 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1357 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 117:20] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1360 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1361 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1363 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1365 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1366 = or(_T_1365, reset) @[Periphery.scala 117:20] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1368 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:117:20)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1370 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1371 = or(_T_1370, reset) @[Periphery.scala 117:20] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1373 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1375 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1375 : @[Periphery.scala 117:20] + node _T_1376 = or(_T_1238[0], reset) @[Periphery.scala 117:20] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1378 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1379 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1381 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1382 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1384 = eq(_T_1382, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1384 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1386 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1387 = or(_T_1386, reset) @[Periphery.scala 117:20] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1389 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1391 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 117:20] + when _T_1391 : @[Periphery.scala 117:20] + node _T_1392 = or(_T_1238[0], reset) @[Periphery.scala 117:20] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1394 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1395 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1397 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1398 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1400 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1402 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1403 = or(_T_1402, reset) @[Periphery.scala 117:20] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1405 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1407 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 117:20] + when _T_1407 : @[Periphery.scala 117:20] + node _T_1408 = or(_T_1238[0], reset) @[Periphery.scala 117:20] + node _T_1410 = eq(_T_1408, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1410 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:117:20)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1411 = or(_T_1216[0], reset) @[Periphery.scala 117:20] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1413 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1414 = or(_T_1227, reset) @[Periphery.scala 117:20] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1416 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1418 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1419 = or(_T_1418, reset) @[Periphery.scala 117:20] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1421 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1424 = or(_T_1423, reset) @[Periphery.scala 117:20] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1426 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + when io.in[0].d.valid : @[Periphery.scala 117:20] + node _T_1428 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1429 = or(_T_1428, reset) @[Periphery.scala 117:20] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1431 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:117:20)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1433 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1434 = not(_T_1433) @[Parameters.scala 37:9] + node _T_1436 = or(_T_1434, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1437 = not(_T_1436) @[Parameters.scala 37:7] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1442 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1442 is invalid @[Parameters.scala 228:27] + _T_1442[0] <= _T_1439 @[Parameters.scala 228:27] + node _T_1447 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1448 = dshl(_T_1447, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1449 = bits(_T_1448, 7, 0) @[package.scala 19:76] + node _T_1450 = not(_T_1449) @[package.scala 19:40] + node _T_1451 = and(io.in[0].d.bits.addr_lo, _T_1450) @[Edges.scala 17:16] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1455 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 117:20] + node _T_1457 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + when _T_1457 : @[Periphery.scala 117:20] + node _T_1458 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1460 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1461 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1463 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1464 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1466 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1468 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1469 = or(_T_1468, reset) @[Periphery.scala 117:20] + node _T_1471 = eq(_T_1469, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1471 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1473 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1474 = or(_T_1473, reset) @[Periphery.scala 117:20] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1476 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1478 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1479 = or(_T_1478, reset) @[Periphery.scala 117:20] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1481 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1483 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 117:20] + when _T_1483 : @[Periphery.scala 117:20] + node _T_1484 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1486 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1487 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1489 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1490 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1492 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1494 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1495 = or(_T_1494, reset) @[Periphery.scala 117:20] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1497 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1499 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1500 = or(_T_1499, reset) @[Periphery.scala 117:20] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1502 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:117:20)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1504 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 117:20] + when _T_1504 : @[Periphery.scala 117:20] + node _T_1505 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1507 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1508 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1510 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1511 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1513 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1515 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 117:20] + node _T_1516 = or(_T_1515, reset) @[Periphery.scala 117:20] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1518 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:117:20)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1520 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1521 = or(_T_1520, reset) @[Periphery.scala 117:20] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1523 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:117:20)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1525 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1525 : @[Periphery.scala 117:20] + node _T_1526 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1528 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1529 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1531 = eq(_T_1529, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1531 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1532 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1534 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1536 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1537 = or(_T_1536, reset) @[Periphery.scala 117:20] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1539 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1541 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 117:20] + when _T_1541 : @[Periphery.scala 117:20] + node _T_1542 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1544 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1545 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1547 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1548 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1550 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1552 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1553 = or(_T_1552, reset) @[Periphery.scala 117:20] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1555 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1557 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 117:20] + when _T_1557 : @[Periphery.scala 117:20] + node _T_1558 = or(_T_1442[0], reset) @[Periphery.scala 117:20] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1560 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1561 = or(_T_1453, reset) @[Periphery.scala 117:20] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1563 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:117:20)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1564 = or(_T_1455, reset) @[Periphery.scala 117:20] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1566 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1568 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1569 = or(_T_1568, reset) @[Periphery.scala 117:20] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1571 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:117:20)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1573 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1574 = or(_T_1573, reset) @[Periphery.scala 117:20] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1576 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:117:20)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + when io.in[0].e.valid : @[Periphery.scala 117:20] + node _T_1578 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 117:20] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 117:20] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1581 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:117:20)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1582 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1584 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1585 = dshl(_T_1584, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1586 = bits(_T_1585, 7, 0) @[package.scala 19:76] + node _T_1587 = not(_T_1586) @[package.scala 19:40] + node _T_1588 = shr(_T_1587, 3) @[Edges.scala 198:59] + node _T_1589 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1593 = mux(_T_1591, _T_1588, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1595 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1597 = sub(_T_1595, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1598 = asUInt(_T_1597) @[Edges.scala 208:28] + node _T_1599 = tail(_T_1598, 1) @[Edges.scala 208:28] + node _T_1601 = eq(_T_1595, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1603 = eq(_T_1595, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1605 = eq(_T_1593, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1606 = or(_T_1603, _T_1605) @[Edges.scala 210:37] + node _T_1607 = and(_T_1606, _T_1582) @[Edges.scala 211:22] + node _T_1608 = not(_T_1599) @[Edges.scala 212:27] + node _T_1609 = and(_T_1593, _T_1608) @[Edges.scala 212:25] + when _T_1582 : @[Edges.scala 213:17] + node _T_1610 = mux(_T_1601, _T_1593, _T_1599) @[Edges.scala 214:21] + _T_1595 <= _T_1610 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1612 : UInt, clock @[Periphery.scala 117:20] + reg _T_1614 : UInt, clock @[Periphery.scala 117:20] + reg _T_1616 : UInt, clock @[Periphery.scala 117:20] + reg _T_1618 : UInt, clock @[Periphery.scala 117:20] + reg _T_1620 : UInt, clock @[Periphery.scala 117:20] + node _T_1622 = eq(_T_1601, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1623 = and(io.in[0].a.valid, _T_1622) @[Periphery.scala 117:20] + when _T_1623 : @[Periphery.scala 117:20] + node _T_1624 = eq(io.in[0].a.bits.opcode, _T_1612) @[Periphery.scala 117:20] + node _T_1625 = or(_T_1624, reset) @[Periphery.scala 117:20] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1627 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1628 = eq(io.in[0].a.bits.param, _T_1614) @[Periphery.scala 117:20] + node _T_1629 = or(_T_1628, reset) @[Periphery.scala 117:20] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1631 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1632 = eq(io.in[0].a.bits.size, _T_1616) @[Periphery.scala 117:20] + node _T_1633 = or(_T_1632, reset) @[Periphery.scala 117:20] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1635 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1636 = eq(io.in[0].a.bits.source, _T_1618) @[Periphery.scala 117:20] + node _T_1637 = or(_T_1636, reset) @[Periphery.scala 117:20] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1639 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1640 = eq(io.in[0].a.bits.address, _T_1620) @[Periphery.scala 117:20] + node _T_1641 = or(_T_1640, reset) @[Periphery.scala 117:20] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1643 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1644 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = and(_T_1644, _T_1601) @[Periphery.scala 117:20] + when _T_1645 : @[Periphery.scala 117:20] + _T_1612 <= io.in[0].a.bits.opcode @[Periphery.scala 117:20] + _T_1614 <= io.in[0].a.bits.param @[Periphery.scala 117:20] + _T_1616 <= io.in[0].a.bits.size @[Periphery.scala 117:20] + _T_1618 <= io.in[0].a.bits.source @[Periphery.scala 117:20] + _T_1620 <= io.in[0].a.bits.address @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1646 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1648 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1649 = dshl(_T_1648, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1650 = bits(_T_1649, 7, 0) @[package.scala 19:76] + node _T_1651 = not(_T_1650) @[package.scala 19:40] + node _T_1652 = shr(_T_1651, 3) @[Edges.scala 198:59] + node _T_1653 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1658 = mux(UInt<1>("h00"), _T_1652, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1660 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1662 = sub(_T_1660, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1663 = asUInt(_T_1662) @[Edges.scala 208:28] + node _T_1664 = tail(_T_1663, 1) @[Edges.scala 208:28] + node _T_1666 = eq(_T_1660, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1668 = eq(_T_1660, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1670 = eq(_T_1658, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1671 = or(_T_1668, _T_1670) @[Edges.scala 210:37] + node _T_1672 = and(_T_1671, _T_1646) @[Edges.scala 211:22] + node _T_1673 = not(_T_1664) @[Edges.scala 212:27] + node _T_1674 = and(_T_1658, _T_1673) @[Edges.scala 212:25] + when _T_1646 : @[Edges.scala 213:17] + node _T_1675 = mux(_T_1666, _T_1658, _T_1664) @[Edges.scala 214:21] + _T_1660 <= _T_1675 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1677 : UInt, clock @[Periphery.scala 117:20] + reg _T_1679 : UInt, clock @[Periphery.scala 117:20] + reg _T_1681 : UInt, clock @[Periphery.scala 117:20] + reg _T_1683 : UInt, clock @[Periphery.scala 117:20] + reg _T_1685 : UInt, clock @[Periphery.scala 117:20] + node _T_1687 = eq(_T_1666, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1688 = and(io.in[0].b.valid, _T_1687) @[Periphery.scala 117:20] + when _T_1688 : @[Periphery.scala 117:20] + node _T_1689 = eq(io.in[0].b.bits.opcode, _T_1677) @[Periphery.scala 117:20] + node _T_1690 = or(_T_1689, reset) @[Periphery.scala 117:20] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1692 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1693 = eq(io.in[0].b.bits.param, _T_1679) @[Periphery.scala 117:20] + node _T_1694 = or(_T_1693, reset) @[Periphery.scala 117:20] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1696 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1697 = eq(io.in[0].b.bits.size, _T_1681) @[Periphery.scala 117:20] + node _T_1698 = or(_T_1697, reset) @[Periphery.scala 117:20] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1700 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1701 = eq(io.in[0].b.bits.source, _T_1683) @[Periphery.scala 117:20] + node _T_1702 = or(_T_1701, reset) @[Periphery.scala 117:20] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1704 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1705 = eq(io.in[0].b.bits.address, _T_1685) @[Periphery.scala 117:20] + node _T_1706 = or(_T_1705, reset) @[Periphery.scala 117:20] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1708 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1709 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1710 = and(_T_1709, _T_1666) @[Periphery.scala 117:20] + when _T_1710 : @[Periphery.scala 117:20] + _T_1677 <= io.in[0].b.bits.opcode @[Periphery.scala 117:20] + _T_1679 <= io.in[0].b.bits.param @[Periphery.scala 117:20] + _T_1681 <= io.in[0].b.bits.size @[Periphery.scala 117:20] + _T_1683 <= io.in[0].b.bits.source @[Periphery.scala 117:20] + _T_1685 <= io.in[0].b.bits.address @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1711 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1713 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1714 = dshl(_T_1713, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1715 = bits(_T_1714, 7, 0) @[package.scala 19:76] + node _T_1716 = not(_T_1715) @[package.scala 19:40] + node _T_1717 = shr(_T_1716, 3) @[Edges.scala 198:59] + node _T_1718 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1721 = mux(UInt<1>("h00"), _T_1717, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1723 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1725 = sub(_T_1723, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1726 = asUInt(_T_1725) @[Edges.scala 208:28] + node _T_1727 = tail(_T_1726, 1) @[Edges.scala 208:28] + node _T_1729 = eq(_T_1723, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1731 = eq(_T_1723, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1733 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1734 = or(_T_1731, _T_1733) @[Edges.scala 210:37] + node _T_1735 = and(_T_1734, _T_1711) @[Edges.scala 211:22] + node _T_1736 = not(_T_1727) @[Edges.scala 212:27] + node _T_1737 = and(_T_1721, _T_1736) @[Edges.scala 212:25] + when _T_1711 : @[Edges.scala 213:17] + node _T_1738 = mux(_T_1729, _T_1721, _T_1727) @[Edges.scala 214:21] + _T_1723 <= _T_1738 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1740 : UInt, clock @[Periphery.scala 117:20] + reg _T_1742 : UInt, clock @[Periphery.scala 117:20] + reg _T_1744 : UInt, clock @[Periphery.scala 117:20] + reg _T_1746 : UInt, clock @[Periphery.scala 117:20] + reg _T_1748 : UInt, clock @[Periphery.scala 117:20] + node _T_1750 = eq(_T_1729, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1751 = and(io.in[0].c.valid, _T_1750) @[Periphery.scala 117:20] + when _T_1751 : @[Periphery.scala 117:20] + node _T_1752 = eq(io.in[0].c.bits.opcode, _T_1740) @[Periphery.scala 117:20] + node _T_1753 = or(_T_1752, reset) @[Periphery.scala 117:20] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1755 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1756 = eq(io.in[0].c.bits.param, _T_1742) @[Periphery.scala 117:20] + node _T_1757 = or(_T_1756, reset) @[Periphery.scala 117:20] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1759 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1760 = eq(io.in[0].c.bits.size, _T_1744) @[Periphery.scala 117:20] + node _T_1761 = or(_T_1760, reset) @[Periphery.scala 117:20] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1763 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1764 = eq(io.in[0].c.bits.source, _T_1746) @[Periphery.scala 117:20] + node _T_1765 = or(_T_1764, reset) @[Periphery.scala 117:20] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1767 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1768 = eq(io.in[0].c.bits.address, _T_1748) @[Periphery.scala 117:20] + node _T_1769 = or(_T_1768, reset) @[Periphery.scala 117:20] + node _T_1771 = eq(_T_1769, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1771 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1773 = and(_T_1772, _T_1729) @[Periphery.scala 117:20] + when _T_1773 : @[Periphery.scala 117:20] + _T_1740 <= io.in[0].c.bits.opcode @[Periphery.scala 117:20] + _T_1742 <= io.in[0].c.bits.param @[Periphery.scala 117:20] + _T_1744 <= io.in[0].c.bits.size @[Periphery.scala 117:20] + _T_1746 <= io.in[0].c.bits.source @[Periphery.scala 117:20] + _T_1748 <= io.in[0].c.bits.address @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1774 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1776 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1777 = dshl(_T_1776, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1778 = bits(_T_1777, 7, 0) @[package.scala 19:76] + node _T_1779 = not(_T_1778) @[package.scala 19:40] + node _T_1780 = shr(_T_1779, 3) @[Edges.scala 198:59] + node _T_1781 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1783 = mux(_T_1781, _T_1780, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1774) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1774 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[Periphery.scala 117:20] + reg _T_1804 : UInt, clock @[Periphery.scala 117:20] + reg _T_1806 : UInt, clock @[Periphery.scala 117:20] + reg _T_1808 : UInt, clock @[Periphery.scala 117:20] + reg _T_1810 : UInt, clock @[Periphery.scala 117:20] + reg _T_1812 : UInt, clock @[Periphery.scala 117:20] + node _T_1814 = eq(_T_1791, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1815 = and(io.in[0].d.valid, _T_1814) @[Periphery.scala 117:20] + when _T_1815 : @[Periphery.scala 117:20] + node _T_1816 = eq(io.in[0].d.bits.opcode, _T_1802) @[Periphery.scala 117:20] + node _T_1817 = or(_T_1816, reset) @[Periphery.scala 117:20] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1819 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1820 = eq(io.in[0].d.bits.param, _T_1804) @[Periphery.scala 117:20] + node _T_1821 = or(_T_1820, reset) @[Periphery.scala 117:20] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1823 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1824 = eq(io.in[0].d.bits.size, _T_1806) @[Periphery.scala 117:20] + node _T_1825 = or(_T_1824, reset) @[Periphery.scala 117:20] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1827 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1828 = eq(io.in[0].d.bits.source, _T_1808) @[Periphery.scala 117:20] + node _T_1829 = or(_T_1828, reset) @[Periphery.scala 117:20] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1831 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1832 = eq(io.in[0].d.bits.sink, _T_1810) @[Periphery.scala 117:20] + node _T_1833 = or(_T_1832, reset) @[Periphery.scala 117:20] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1835 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1836 = eq(io.in[0].d.bits.addr_lo, _T_1812) @[Periphery.scala 117:20] + node _T_1837 = or(_T_1836, reset) @[Periphery.scala 117:20] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1839 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:117:20)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1840 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1841 = and(_T_1840, _T_1791) @[Periphery.scala 117:20] + when _T_1841 : @[Periphery.scala 117:20] + _T_1802 <= io.in[0].d.bits.opcode @[Periphery.scala 117:20] + _T_1804 <= io.in[0].d.bits.param @[Periphery.scala 117:20] + _T_1806 <= io.in[0].d.bits.size @[Periphery.scala 117:20] + _T_1808 <= io.in[0].d.bits.source @[Periphery.scala 117:20] + _T_1810 <= io.in[0].d.bits.sink @[Periphery.scala 117:20] + _T_1812 <= io.in[0].d.bits.addr_lo @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + reg _T_1843 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_1844 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1846 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1847 = dshl(_T_1846, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1848 = bits(_T_1847, 7, 0) @[package.scala 19:76] + node _T_1849 = not(_T_1848) @[package.scala 19:40] + node _T_1850 = shr(_T_1849, 3) @[Edges.scala 198:59] + node _T_1851 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1853 = eq(_T_1851, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1855 = mux(_T_1853, _T_1850, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1857 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1859 = sub(_T_1857, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1860 = asUInt(_T_1859) @[Edges.scala 208:28] + node _T_1861 = tail(_T_1860, 1) @[Edges.scala 208:28] + node _T_1863 = eq(_T_1857, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1865 = eq(_T_1857, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1867 = eq(_T_1855, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1868 = or(_T_1865, _T_1867) @[Edges.scala 210:37] + node _T_1869 = and(_T_1868, _T_1844) @[Edges.scala 211:22] + node _T_1870 = not(_T_1861) @[Edges.scala 212:27] + node _T_1871 = and(_T_1855, _T_1870) @[Edges.scala 212:25] + when _T_1844 : @[Edges.scala 213:17] + node _T_1872 = mux(_T_1863, _T_1855, _T_1861) @[Edges.scala 214:21] + _T_1857 <= _T_1872 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1873 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1875 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1876 = dshl(_T_1875, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1877 = bits(_T_1876, 7, 0) @[package.scala 19:76] + node _T_1878 = not(_T_1877) @[package.scala 19:40] + node _T_1879 = shr(_T_1878, 3) @[Edges.scala 198:59] + node _T_1880 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1882 = mux(_T_1880, _T_1879, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1884 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1886 = sub(_T_1884, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1887 = asUInt(_T_1886) @[Edges.scala 208:28] + node _T_1888 = tail(_T_1887, 1) @[Edges.scala 208:28] + node _T_1890 = eq(_T_1884, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1892 = eq(_T_1884, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1894 = eq(_T_1882, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1895 = or(_T_1892, _T_1894) @[Edges.scala 210:37] + node _T_1896 = and(_T_1895, _T_1873) @[Edges.scala 211:22] + node _T_1897 = not(_T_1888) @[Edges.scala 212:27] + node _T_1898 = and(_T_1882, _T_1897) @[Edges.scala 212:25] + when _T_1873 : @[Edges.scala 213:17] + node _T_1899 = mux(_T_1890, _T_1882, _T_1888) @[Edges.scala 214:21] + _T_1884 <= _T_1899 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1901 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + node _T_1902 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 117:20] + node _T_1903 = or(_T_1901, _T_1902) @[Periphery.scala 117:20] + node _T_1905 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1906 = or(_T_1903, _T_1905) @[Periphery.scala 117:20] + node _T_1908 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1909 = or(_T_1906, _T_1908) @[Periphery.scala 117:20] + node _T_1910 = or(_T_1909, reset) @[Periphery.scala 117:20] + node _T_1912 = eq(_T_1910, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1912 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:117:20)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + wire _T_1914 : UInt<32> + _T_1914 is invalid + _T_1914 <= UInt<32>("h00") + node _T_1915 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1915 : @[Periphery.scala 117:20] + when _T_1868 : @[Periphery.scala 117:20] + node _T_1917 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1914 <= _T_1917 @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1918 = dshr(_T_1843, io.in[0].a.bits.source) @[Periphery.scala 117:20] + node _T_1919 = bits(_T_1918, 0, 0) @[Periphery.scala 117:20] + node _T_1921 = eq(_T_1919, UInt<1>("h00")) @[Periphery.scala 117:20] + node _T_1922 = or(_T_1921, reset) @[Periphery.scala 117:20] + node _T_1924 = eq(_T_1922, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1924 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:117:20)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + wire _T_1926 : UInt<32> + _T_1926 is invalid + _T_1926 <= UInt<32>("h00") + node _T_1927 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1929 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 117:20] + node _T_1930 = and(_T_1927, _T_1929) @[Periphery.scala 117:20] + when _T_1930 : @[Periphery.scala 117:20] + when _T_1895 : @[Periphery.scala 117:20] + node _T_1932 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1926 <= _T_1932 @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1933 = or(_T_1914, _T_1843) @[Periphery.scala 117:20] + node _T_1934 = dshr(_T_1933, io.in[0].d.bits.source) @[Periphery.scala 117:20] + node _T_1935 = bits(_T_1934, 0, 0) @[Periphery.scala 117:20] + node _T_1936 = or(_T_1935, reset) @[Periphery.scala 117:20] + node _T_1938 = eq(_T_1936, UInt<1>("h00")) @[Periphery.scala 117:20] + when _T_1938 : @[Periphery.scala 117:20] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:117:20)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 117:20] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + skip @[Periphery.scala 117:20] + node _T_1939 = or(_T_1843, _T_1914) @[Periphery.scala 117:20] + node _T_1940 = not(_T_1926) @[Periphery.scala 117:20] + node _T_1941 = and(_T_1939, _T_1940) @[Periphery.scala 117:20] + _T_1843 <= _T_1941 @[Periphery.scala 117:20] + + module TLWidthWidget : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + io.out.0.a <- io.in.0.a @[WidthWidget.scala 131:13] + io.in.0.d <- io.out.0.d @[WidthWidget.scala 131:13] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_5 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 189:42] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 189:42] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_608 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:189:42)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 7, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + when _T_708 : @[Periphery.scala 189:42] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[Periphery.scala 189:42] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_725 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_726 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_728 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_731 = or(_T_730, reset) @[Periphery.scala 189:42] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_733 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_734 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_736 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[Periphery.scala 189:42] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_741 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:189:42)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_742 = not(io.in[0].a.bits.mask) @[Periphery.scala 189:42] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_745 = or(_T_744, reset) @[Periphery.scala 189:42] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_747 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 189:42] + when _T_749 : @[Periphery.scala 189:42] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[Periphery.scala 189:42] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_770 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_771 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_773 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_774 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_776 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_779 = or(_T_778, reset) @[Periphery.scala 189:42] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_781 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 189:42] + node _T_783 = or(_T_782, reset) @[Periphery.scala 189:42] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_785 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_787 : @[Periphery.scala 189:42] + node _T_790 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_792 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_793 = and(_T_790, _T_792) @[Parameters.scala 63:37] + node _T_794 = or(UInt<1>("h00"), _T_793) @[Parameters.scala 132:31] + node _T_796 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_797 = cvt(_T_796) @[Parameters.scala 117:49] + node _T_799 = and(_T_797, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_800 = asSInt(_T_799) @[Parameters.scala 117:52] + node _T_802 = eq(_T_800, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = and(_T_794, _T_802) @[Parameters.scala 132:56] + node _T_805 = or(UInt<1>("h00"), _T_803) @[Parameters.scala 134:30] + node _T_806 = or(_T_805, reset) @[Periphery.scala 189:42] + node _T_808 = eq(_T_806, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_808 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_809 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_811 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_812 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_814 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_816 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_817 = or(_T_816, reset) @[Periphery.scala 189:42] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_819 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_820 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 189:42] + node _T_821 = or(_T_820, reset) @[Periphery.scala 189:42] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_823 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_825 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 189:42] + when _T_825 : @[Periphery.scala 189:42] + node _T_828 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_830 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_831 = and(_T_828, _T_830) @[Parameters.scala 63:37] + node _T_832 = or(UInt<1>("h00"), _T_831) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_841) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, reset) @[Periphery.scala 189:42] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_846 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_847 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_849 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_850 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_852 = eq(_T_850, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_852 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_854 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_855 = or(_T_854, reset) @[Periphery.scala 189:42] + node _T_857 = eq(_T_855, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_857 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_858 = not(_T_706) @[Periphery.scala 189:42] + node _T_859 = and(io.in[0].a.bits.mask, _T_858) @[Periphery.scala 189:42] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_862 = or(_T_861, reset) @[Periphery.scala 189:42] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_864 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_866 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 189:42] + when _T_866 : @[Periphery.scala 189:42] + node _T_869 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_871 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_872 = cvt(_T_871) @[Parameters.scala 117:49] + node _T_874 = and(_T_872, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_875 = asSInt(_T_874) @[Parameters.scala 117:52] + node _T_877 = eq(_T_875, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = and(_T_869, _T_877) @[Parameters.scala 132:56] + node _T_880 = or(UInt<1>("h00"), _T_878) @[Parameters.scala 134:30] + node _T_881 = or(_T_880, reset) @[Periphery.scala 189:42] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_883 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_884 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_886 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_887 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_889 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_891 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_892 = or(_T_891, reset) @[Periphery.scala 189:42] + node _T_894 = eq(_T_892, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_894 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:189:42)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_895 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 189:42] + node _T_896 = or(_T_895, reset) @[Periphery.scala 189:42] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_898 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_900 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 189:42] + when _T_900 : @[Periphery.scala 189:42] + node _T_903 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_905 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_906 = cvt(_T_905) @[Parameters.scala 117:49] + node _T_908 = and(_T_906, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_909 = asSInt(_T_908) @[Parameters.scala 117:52] + node _T_911 = eq(_T_909, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = and(_T_903, _T_911) @[Parameters.scala 132:56] + node _T_914 = or(UInt<1>("h00"), _T_912) @[Parameters.scala 134:30] + node _T_915 = or(_T_914, reset) @[Periphery.scala 189:42] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_917 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_918 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_920 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_921 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_923 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_925 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_926 = or(_T_925, reset) @[Periphery.scala 189:42] + node _T_928 = eq(_T_926, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_928 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:189:42)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_929 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 189:42] + node _T_930 = or(_T_929, reset) @[Periphery.scala 189:42] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_932 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 189:42] + when _T_934 : @[Periphery.scala 189:42] + node _T_937 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_939 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_940 = cvt(_T_939) @[Parameters.scala 117:49] + node _T_942 = and(_T_940, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_943 = asSInt(_T_942) @[Parameters.scala 117:52] + node _T_945 = eq(_T_943, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_946 = and(_T_937, _T_945) @[Parameters.scala 132:56] + node _T_948 = or(UInt<1>("h00"), _T_946) @[Parameters.scala 134:30] + node _T_949 = or(_T_948, reset) @[Periphery.scala 189:42] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_951 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_952 = or(_T_630, reset) @[Periphery.scala 189:42] + node _T_954 = eq(_T_952, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_954 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_955 = or(_T_638, reset) @[Periphery.scala 189:42] + node _T_957 = eq(_T_955, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_957 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_958 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 189:42] + node _T_959 = or(_T_958, reset) @[Periphery.scala 189:42] + node _T_961 = eq(_T_959, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_961 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + when io.in[0].b.valid : @[Periphery.scala 189:42] + node _T_963 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_964 = or(_T_963, reset) @[Periphery.scala 189:42] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_966 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:189:42)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_968 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_977 : UInt<1>[1] @[Parameters.scala 110:36] + _T_977 is invalid @[Parameters.scala 110:36] + _T_977[0] <= _T_974 @[Parameters.scala 110:36] + node _T_982 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_983 = dshl(_T_982, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_984 = bits(_T_983, 7, 0) @[package.scala 19:76] + node _T_985 = not(_T_984) @[package.scala 19:40] + node _T_986 = and(io.in[0].b.bits.address, _T_985) @[Edges.scala 17:16] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_990 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_991 = dshl(UInt<1>("h01"), _T_990) @[OneHot.scala 49:12] + node _T_992 = bits(_T_991, 2, 0) @[OneHot.scala 49:37] + node _T_994 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_996 = bits(_T_992, 2, 2) @[package.scala 44:26] + node _T_997 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_999 = eq(_T_997, UInt<1>("h00")) @[package.scala 46:20] + node _T_1000 = and(UInt<1>("h01"), _T_999) @[package.scala 49:27] + node _T_1001 = and(_T_996, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_994, _T_1001) @[package.scala 50:29] + node _T_1003 = and(UInt<1>("h01"), _T_997) @[package.scala 49:27] + node _T_1004 = and(_T_996, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_994, _T_1004) @[package.scala 50:29] + node _T_1006 = bits(_T_992, 1, 1) @[package.scala 44:26] + node _T_1007 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1009 = eq(_T_1007, UInt<1>("h00")) @[package.scala 46:20] + node _T_1010 = and(_T_1000, _T_1009) @[package.scala 49:27] + node _T_1011 = and(_T_1006, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_1002, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_1000, _T_1007) @[package.scala 49:27] + node _T_1014 = and(_T_1006, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_1002, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_1003, _T_1009) @[package.scala 49:27] + node _T_1017 = and(_T_1006, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_1005, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1003, _T_1007) @[package.scala 49:27] + node _T_1020 = and(_T_1006, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1005, _T_1020) @[package.scala 50:29] + node _T_1022 = bits(_T_992, 0, 0) @[package.scala 44:26] + node _T_1023 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[package.scala 46:20] + node _T_1026 = and(_T_1010, _T_1025) @[package.scala 49:27] + node _T_1027 = and(_T_1022, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1012, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1010, _T_1023) @[package.scala 49:27] + node _T_1030 = and(_T_1022, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1012, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1013, _T_1025) @[package.scala 49:27] + node _T_1033 = and(_T_1022, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1015, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1013, _T_1023) @[package.scala 49:27] + node _T_1036 = and(_T_1022, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1015, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1016, _T_1025) @[package.scala 49:27] + node _T_1039 = and(_T_1022, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1018, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1016, _T_1023) @[package.scala 49:27] + node _T_1042 = and(_T_1022, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1018, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1019, _T_1025) @[package.scala 49:27] + node _T_1045 = and(_T_1022, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1021, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1019, _T_1023) @[package.scala 49:27] + node _T_1048 = and(_T_1022, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1021, _T_1048) @[package.scala 50:29] + node _T_1050 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1050) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1054 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1058 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + when _T_1058 : @[Periphery.scala 189:42] + node _T_1060 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1061 = not(_T_1060) @[Parameters.scala 37:9] + node _T_1063 = or(_T_1061, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1064 = not(_T_1063) @[Parameters.scala 37:7] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1068 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1070 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1073 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1073 is invalid @[Parameters.scala 228:27] + _T_1073[0] <= _T_1066 @[Parameters.scala 228:27] + _T_1073[1] <= _T_1068 @[Parameters.scala 228:27] + _T_1073[2] <= _T_1070 @[Parameters.scala 228:27] + node _T_1081 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1083 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1084 = and(_T_1081, _T_1083) @[Parameters.scala 63:37] + node _T_1087 = mux(_T_1073[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1089 = mux(_T_1073[1], _T_1084, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1073[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1093 = or(_T_1087, _T_1089) @[Mux.scala 19:72] + node _T_1094 = or(_T_1093, _T_1091) @[Mux.scala 19:72] + wire _T_1096 : UInt<1> @[Mux.scala 19:72] + _T_1096 is invalid @[Mux.scala 19:72] + _T_1096 <= _T_1094 @[Mux.scala 19:72] + node _T_1097 = or(_T_1096, reset) @[Periphery.scala 189:42] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1099 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1100 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1102 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1104 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1105 = or(_T_1104, reset) @[Periphery.scala 189:42] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1107 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1108 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1110 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1112 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1113 = or(_T_1112, reset) @[Periphery.scala 189:42] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1115 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:189:42)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1116 = not(io.in[0].b.bits.mask) @[Periphery.scala 189:42] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1119 = or(_T_1118, reset) @[Periphery.scala 189:42] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1121 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1123 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 189:42] + when _T_1123 : @[Periphery.scala 189:42] + node _T_1125 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1127 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1128 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1130 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1131 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1133 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1135 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1136 = or(_T_1135, reset) @[Periphery.scala 189:42] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1138 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1139 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 189:42] + node _T_1140 = or(_T_1139, reset) @[Periphery.scala 189:42] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1142 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1144 : @[Periphery.scala 189:42] + node _T_1146 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1148 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1149 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1151 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1152 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1154 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1156 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1157 = or(_T_1156, reset) @[Periphery.scala 189:42] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1159 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 189:42] + node _T_1161 = or(_T_1160, reset) @[Periphery.scala 189:42] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1163 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 189:42] + when _T_1165 : @[Periphery.scala 189:42] + node _T_1167 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1169 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1170 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1172 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1173 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1175 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1177 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1178 = or(_T_1177, reset) @[Periphery.scala 189:42] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1180 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1181 = not(_T_1056) @[Periphery.scala 189:42] + node _T_1182 = and(io.in[0].b.bits.mask, _T_1181) @[Periphery.scala 189:42] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1185 = or(_T_1184, reset) @[Periphery.scala 189:42] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1187 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 189:42] + when _T_1189 : @[Periphery.scala 189:42] + node _T_1191 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1193 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1194 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1196 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1197 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1199 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1202 = or(_T_1201, reset) @[Periphery.scala 189:42] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1204 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:189:42)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1205 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 189:42] + node _T_1206 = or(_T_1205, reset) @[Periphery.scala 189:42] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1208 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1210 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 189:42] + when _T_1210 : @[Periphery.scala 189:42] + node _T_1212 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1214 = eq(_T_1212, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1214 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1215 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1217 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1218 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1220 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1222 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1223 = or(_T_1222, reset) @[Periphery.scala 189:42] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1225 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:189:42)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1226 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 189:42] + node _T_1227 = or(_T_1226, reset) @[Periphery.scala 189:42] + node _T_1229 = eq(_T_1227, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1229 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1231 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 189:42] + when _T_1231 : @[Periphery.scala 189:42] + node _T_1233 = or(UInt<1>("h00"), reset) @[Periphery.scala 189:42] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1235 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:189:42)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1236 = or(_T_977[0], reset) @[Periphery.scala 189:42] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1238 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1239 = or(_T_988, reset) @[Periphery.scala 189:42] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1241 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1242 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 189:42] + node _T_1243 = or(_T_1242, reset) @[Periphery.scala 189:42] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1245 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:189:42)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + when io.in[0].c.valid : @[Periphery.scala 189:42] + node _T_1247 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1248 = or(_T_1247, reset) @[Periphery.scala 189:42] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1250 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:189:42)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1252 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1253 = not(_T_1252) @[Parameters.scala 37:9] + node _T_1255 = or(_T_1253, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1256 = not(_T_1255) @[Parameters.scala 37:7] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1260 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1262 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1265 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1265 is invalid @[Parameters.scala 228:27] + _T_1265[0] <= _T_1258 @[Parameters.scala 228:27] + _T_1265[1] <= _T_1260 @[Parameters.scala 228:27] + _T_1265[2] <= _T_1262 @[Parameters.scala 228:27] + node _T_1271 = or(_T_1265[0], _T_1265[1]) @[Parameters.scala 229:46] + node _T_1272 = or(_T_1271, _T_1265[2]) @[Parameters.scala 229:46] + node _T_1274 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1275 = dshl(_T_1274, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1276 = bits(_T_1275, 7, 0) @[package.scala 19:76] + node _T_1277 = not(_T_1276) @[package.scala 19:40] + node _T_1278 = and(io.in[0].c.bits.address, _T_1277) @[Edges.scala 17:16] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1282 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1283 = cvt(_T_1282) @[Parameters.scala 117:49] + node _T_1285 = and(_T_1283, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1286 = asSInt(_T_1285) @[Parameters.scala 117:52] + node _T_1288 = eq(_T_1286, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1291 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1291 is invalid @[Parameters.scala 110:36] + _T_1291[0] <= _T_1288 @[Parameters.scala 110:36] + node _T_1296 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 189:42] + when _T_1296 : @[Periphery.scala 189:42] + node _T_1297 = or(_T_1291[0], reset) @[Periphery.scala 189:42] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1299 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1300 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1302 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1304 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1305 = or(_T_1304, reset) @[Periphery.scala 189:42] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1307 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1308 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1310 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1312 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1313 = or(_T_1312, reset) @[Periphery.scala 189:42] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1315 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:189:42)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1317 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1318 = or(_T_1317, reset) @[Periphery.scala 189:42] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1320 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1322 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 189:42] + when _T_1322 : @[Periphery.scala 189:42] + node _T_1323 = or(_T_1291[0], reset) @[Periphery.scala 189:42] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1325 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1326 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1328 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1330 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 189:42] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1333 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1334 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1336 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1338 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1339 = or(_T_1338, reset) @[Periphery.scala 189:42] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1341 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:189:42)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1343 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1344 = or(_T_1343, reset) @[Periphery.scala 189:42] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1346 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1348 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + when _T_1348 : @[Periphery.scala 189:42] + node _T_1351 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1353 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1354 = cvt(_T_1353) @[Parameters.scala 117:49] + node _T_1356 = and(_T_1354, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1357 = asSInt(_T_1356) @[Parameters.scala 117:52] + node _T_1359 = eq(_T_1357, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1360 = and(_T_1351, _T_1359) @[Parameters.scala 132:56] + node _T_1362 = or(UInt<1>("h00"), _T_1360) @[Parameters.scala 134:30] + node _T_1363 = or(_T_1362, reset) @[Periphery.scala 189:42] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1365 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1366 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1368 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1370 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1371 = or(_T_1370, reset) @[Periphery.scala 189:42] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1373 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1374 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1376 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1378 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1379 = or(_T_1378, reset) @[Periphery.scala 189:42] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1381 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:189:42)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1383 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1384 = or(_T_1383, reset) @[Periphery.scala 189:42] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1386 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 189:42] + when _T_1388 : @[Periphery.scala 189:42] + node _T_1391 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1393 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + node _T_1403 = or(_T_1402, reset) @[Periphery.scala 189:42] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1405 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:189:42)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1406 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1408 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1410 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1411 = or(_T_1410, reset) @[Periphery.scala 189:42] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1413 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1414 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1416 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1418 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1419 = or(_T_1418, reset) @[Periphery.scala 189:42] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1421 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:189:42)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1424 = or(_T_1423, reset) @[Periphery.scala 189:42] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1426 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1428 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1428 : @[Periphery.scala 189:42] + node _T_1429 = or(_T_1291[0], reset) @[Periphery.scala 189:42] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1431 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1432 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1434 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1435 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1437 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1439 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1440 = or(_T_1439, reset) @[Periphery.scala 189:42] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1442 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1444 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 189:42] + when _T_1444 : @[Periphery.scala 189:42] + node _T_1445 = or(_T_1291[0], reset) @[Periphery.scala 189:42] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1447 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1448 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1450 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1451 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1453 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1455 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1456 = or(_T_1455, reset) @[Periphery.scala 189:42] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1458 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1460 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 189:42] + when _T_1460 : @[Periphery.scala 189:42] + node _T_1461 = or(_T_1291[0], reset) @[Periphery.scala 189:42] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1463 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:189:42)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1464 = or(_T_1272, reset) @[Periphery.scala 189:42] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1466 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1467 = or(_T_1280, reset) @[Periphery.scala 189:42] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1469 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1471 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1472 = or(_T_1471, reset) @[Periphery.scala 189:42] + node _T_1474 = eq(_T_1472, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1474 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1476 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1477 = or(_T_1476, reset) @[Periphery.scala 189:42] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1479 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + when io.in[0].d.valid : @[Periphery.scala 189:42] + node _T_1481 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1482 = or(_T_1481, reset) @[Periphery.scala 189:42] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1484 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:189:42)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1486 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1487 = not(_T_1486) @[Parameters.scala 37:9] + node _T_1489 = or(_T_1487, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1490 = not(_T_1489) @[Parameters.scala 37:7] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1494 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1496 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1499 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1499 is invalid @[Parameters.scala 228:27] + _T_1499[0] <= _T_1492 @[Parameters.scala 228:27] + _T_1499[1] <= _T_1494 @[Parameters.scala 228:27] + _T_1499[2] <= _T_1496 @[Parameters.scala 228:27] + node _T_1505 = or(_T_1499[0], _T_1499[1]) @[Parameters.scala 229:46] + node _T_1506 = or(_T_1505, _T_1499[2]) @[Parameters.scala 229:46] + node _T_1508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1509 = dshl(_T_1508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1510 = bits(_T_1509, 7, 0) @[package.scala 19:76] + node _T_1511 = not(_T_1510) @[package.scala 19:40] + node _T_1512 = and(io.in[0].d.bits.addr_lo, _T_1511) @[Edges.scala 17:16] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1516 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 189:42] + node _T_1518 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + when _T_1518 : @[Periphery.scala 189:42] + node _T_1519 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1521 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1522 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1524 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1525 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1527 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1529 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1530 = or(_T_1529, reset) @[Periphery.scala 189:42] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1532 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1534 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1535 = or(_T_1534, reset) @[Periphery.scala 189:42] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1537 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1539 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1540 = or(_T_1539, reset) @[Periphery.scala 189:42] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1542 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1544 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 189:42] + when _T_1544 : @[Periphery.scala 189:42] + node _T_1545 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1547 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1548 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1550 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1551 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1553 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1555 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1556 = or(_T_1555, reset) @[Periphery.scala 189:42] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1558 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1560 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1561 = or(_T_1560, reset) @[Periphery.scala 189:42] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1563 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:189:42)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1565 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 189:42] + when _T_1565 : @[Periphery.scala 189:42] + node _T_1566 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1568 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1569 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1571 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1572 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1574 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1576 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 189:42] + node _T_1577 = or(_T_1576, reset) @[Periphery.scala 189:42] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1579 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:189:42)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1581 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1582 = or(_T_1581, reset) @[Periphery.scala 189:42] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1584 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:189:42)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1586 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1586 : @[Periphery.scala 189:42] + node _T_1587 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1589 = eq(_T_1587, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1589 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1590 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1592 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1593 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1595 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1597 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1598 = or(_T_1597, reset) @[Periphery.scala 189:42] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1600 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1602 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 189:42] + when _T_1602 : @[Periphery.scala 189:42] + node _T_1603 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1605 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1606 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1608 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1609 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1611 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1613 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1614 = or(_T_1613, reset) @[Periphery.scala 189:42] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1616 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1618 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 189:42] + when _T_1618 : @[Periphery.scala 189:42] + node _T_1619 = or(_T_1506, reset) @[Periphery.scala 189:42] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1621 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1622 = or(_T_1514, reset) @[Periphery.scala 189:42] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1624 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:189:42)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1625 = or(_T_1516, reset) @[Periphery.scala 189:42] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1627 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1629 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1630 = or(_T_1629, reset) @[Periphery.scala 189:42] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1632 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:189:42)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1634 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1635 = or(_T_1634, reset) @[Periphery.scala 189:42] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1637 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:189:42)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + when io.in[0].e.valid : @[Periphery.scala 189:42] + node _T_1639 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 189:42] + node _T_1640 = or(_T_1639, reset) @[Periphery.scala 189:42] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1642 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:189:42)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1643 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1646 = dshl(_T_1645, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1647 = bits(_T_1646, 7, 0) @[package.scala 19:76] + node _T_1648 = not(_T_1647) @[package.scala 19:40] + node _T_1649 = shr(_T_1648, 3) @[Edges.scala 198:59] + node _T_1650 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1654 = mux(_T_1652, _T_1649, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1656 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1658 = sub(_T_1656, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1659 = asUInt(_T_1658) @[Edges.scala 208:28] + node _T_1660 = tail(_T_1659, 1) @[Edges.scala 208:28] + node _T_1662 = eq(_T_1656, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1664 = eq(_T_1656, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1666 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1667 = or(_T_1664, _T_1666) @[Edges.scala 210:37] + node _T_1668 = and(_T_1667, _T_1643) @[Edges.scala 211:22] + node _T_1669 = not(_T_1660) @[Edges.scala 212:27] + node _T_1670 = and(_T_1654, _T_1669) @[Edges.scala 212:25] + when _T_1643 : @[Edges.scala 213:17] + node _T_1671 = mux(_T_1662, _T_1654, _T_1660) @[Edges.scala 214:21] + _T_1656 <= _T_1671 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1673 : UInt, clock @[Periphery.scala 189:42] + reg _T_1675 : UInt, clock @[Periphery.scala 189:42] + reg _T_1677 : UInt, clock @[Periphery.scala 189:42] + reg _T_1679 : UInt, clock @[Periphery.scala 189:42] + reg _T_1681 : UInt, clock @[Periphery.scala 189:42] + node _T_1683 = eq(_T_1662, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1684 = and(io.in[0].a.valid, _T_1683) @[Periphery.scala 189:42] + when _T_1684 : @[Periphery.scala 189:42] + node _T_1685 = eq(io.in[0].a.bits.opcode, _T_1673) @[Periphery.scala 189:42] + node _T_1686 = or(_T_1685, reset) @[Periphery.scala 189:42] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1688 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1689 = eq(io.in[0].a.bits.param, _T_1675) @[Periphery.scala 189:42] + node _T_1690 = or(_T_1689, reset) @[Periphery.scala 189:42] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1692 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1693 = eq(io.in[0].a.bits.size, _T_1677) @[Periphery.scala 189:42] + node _T_1694 = or(_T_1693, reset) @[Periphery.scala 189:42] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1696 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1697 = eq(io.in[0].a.bits.source, _T_1679) @[Periphery.scala 189:42] + node _T_1698 = or(_T_1697, reset) @[Periphery.scala 189:42] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1700 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1701 = eq(io.in[0].a.bits.address, _T_1681) @[Periphery.scala 189:42] + node _T_1702 = or(_T_1701, reset) @[Periphery.scala 189:42] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1704 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1705 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1706 = and(_T_1705, _T_1662) @[Periphery.scala 189:42] + when _T_1706 : @[Periphery.scala 189:42] + _T_1673 <= io.in[0].a.bits.opcode @[Periphery.scala 189:42] + _T_1675 <= io.in[0].a.bits.param @[Periphery.scala 189:42] + _T_1677 <= io.in[0].a.bits.size @[Periphery.scala 189:42] + _T_1679 <= io.in[0].a.bits.source @[Periphery.scala 189:42] + _T_1681 <= io.in[0].a.bits.address @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1707 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 7, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1719 = mux(UInt<1>("h00"), _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1721 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1723 = sub(_T_1721, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1724 = asUInt(_T_1723) @[Edges.scala 208:28] + node _T_1725 = tail(_T_1724, 1) @[Edges.scala 208:28] + node _T_1727 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1729 = eq(_T_1721, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1731 = eq(_T_1719, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1732 = or(_T_1729, _T_1731) @[Edges.scala 210:37] + node _T_1733 = and(_T_1732, _T_1707) @[Edges.scala 211:22] + node _T_1734 = not(_T_1725) @[Edges.scala 212:27] + node _T_1735 = and(_T_1719, _T_1734) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1736 = mux(_T_1727, _T_1719, _T_1725) @[Edges.scala 214:21] + _T_1721 <= _T_1736 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1738 : UInt, clock @[Periphery.scala 189:42] + reg _T_1740 : UInt, clock @[Periphery.scala 189:42] + reg _T_1742 : UInt, clock @[Periphery.scala 189:42] + reg _T_1744 : UInt, clock @[Periphery.scala 189:42] + reg _T_1746 : UInt, clock @[Periphery.scala 189:42] + node _T_1748 = eq(_T_1727, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1749 = and(io.in[0].b.valid, _T_1748) @[Periphery.scala 189:42] + when _T_1749 : @[Periphery.scala 189:42] + node _T_1750 = eq(io.in[0].b.bits.opcode, _T_1738) @[Periphery.scala 189:42] + node _T_1751 = or(_T_1750, reset) @[Periphery.scala 189:42] + node _T_1753 = eq(_T_1751, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1753 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1754 = eq(io.in[0].b.bits.param, _T_1740) @[Periphery.scala 189:42] + node _T_1755 = or(_T_1754, reset) @[Periphery.scala 189:42] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1757 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1758 = eq(io.in[0].b.bits.size, _T_1742) @[Periphery.scala 189:42] + node _T_1759 = or(_T_1758, reset) @[Periphery.scala 189:42] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1761 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1762 = eq(io.in[0].b.bits.source, _T_1744) @[Periphery.scala 189:42] + node _T_1763 = or(_T_1762, reset) @[Periphery.scala 189:42] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1765 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1766 = eq(io.in[0].b.bits.address, _T_1746) @[Periphery.scala 189:42] + node _T_1767 = or(_T_1766, reset) @[Periphery.scala 189:42] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1769 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1770 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1771 = and(_T_1770, _T_1727) @[Periphery.scala 189:42] + when _T_1771 : @[Periphery.scala 189:42] + _T_1738 <= io.in[0].b.bits.opcode @[Periphery.scala 189:42] + _T_1740 <= io.in[0].b.bits.param @[Periphery.scala 189:42] + _T_1742 <= io.in[0].b.bits.size @[Periphery.scala 189:42] + _T_1744 <= io.in[0].b.bits.source @[Periphery.scala 189:42] + _T_1746 <= io.in[0].b.bits.address @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1774 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1775 = dshl(_T_1774, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1776 = bits(_T_1775, 7, 0) @[package.scala 19:76] + node _T_1777 = not(_T_1776) @[package.scala 19:40] + node _T_1778 = shr(_T_1777, 3) @[Edges.scala 198:59] + node _T_1779 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1781 = mux(_T_1779, _T_1778, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1783 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1785 = sub(_T_1783, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1786 = asUInt(_T_1785) @[Edges.scala 208:28] + node _T_1787 = tail(_T_1786, 1) @[Edges.scala 208:28] + node _T_1789 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1791 = eq(_T_1783, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1793 = eq(_T_1781, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1794 = or(_T_1791, _T_1793) @[Edges.scala 210:37] + node _T_1795 = and(_T_1794, _T_1772) @[Edges.scala 211:22] + node _T_1796 = not(_T_1787) @[Edges.scala 212:27] + node _T_1797 = and(_T_1781, _T_1796) @[Edges.scala 212:25] + when _T_1772 : @[Edges.scala 213:17] + node _T_1798 = mux(_T_1789, _T_1781, _T_1787) @[Edges.scala 214:21] + _T_1783 <= _T_1798 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1800 : UInt, clock @[Periphery.scala 189:42] + reg _T_1802 : UInt, clock @[Periphery.scala 189:42] + reg _T_1804 : UInt, clock @[Periphery.scala 189:42] + reg _T_1806 : UInt, clock @[Periphery.scala 189:42] + reg _T_1808 : UInt, clock @[Periphery.scala 189:42] + node _T_1810 = eq(_T_1789, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1811 = and(io.in[0].c.valid, _T_1810) @[Periphery.scala 189:42] + when _T_1811 : @[Periphery.scala 189:42] + node _T_1812 = eq(io.in[0].c.bits.opcode, _T_1800) @[Periphery.scala 189:42] + node _T_1813 = or(_T_1812, reset) @[Periphery.scala 189:42] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1815 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1816 = eq(io.in[0].c.bits.param, _T_1802) @[Periphery.scala 189:42] + node _T_1817 = or(_T_1816, reset) @[Periphery.scala 189:42] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1819 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1820 = eq(io.in[0].c.bits.size, _T_1804) @[Periphery.scala 189:42] + node _T_1821 = or(_T_1820, reset) @[Periphery.scala 189:42] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1823 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1824 = eq(io.in[0].c.bits.source, _T_1806) @[Periphery.scala 189:42] + node _T_1825 = or(_T_1824, reset) @[Periphery.scala 189:42] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1827 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1828 = eq(io.in[0].c.bits.address, _T_1808) @[Periphery.scala 189:42] + node _T_1829 = or(_T_1828, reset) @[Periphery.scala 189:42] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1831 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1832 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1833 = and(_T_1832, _T_1789) @[Periphery.scala 189:42] + when _T_1833 : @[Periphery.scala 189:42] + _T_1800 <= io.in[0].c.bits.opcode @[Periphery.scala 189:42] + _T_1802 <= io.in[0].c.bits.param @[Periphery.scala 189:42] + _T_1804 <= io.in[0].c.bits.size @[Periphery.scala 189:42] + _T_1806 <= io.in[0].c.bits.source @[Periphery.scala 189:42] + _T_1808 <= io.in[0].c.bits.address @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1834 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 7, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 3) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1843 = mux(_T_1841, _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1845 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1847 = sub(_T_1845, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1848 = asUInt(_T_1847) @[Edges.scala 208:28] + node _T_1849 = tail(_T_1848, 1) @[Edges.scala 208:28] + node _T_1851 = eq(_T_1845, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1853 = eq(_T_1845, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1855 = eq(_T_1843, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1856 = or(_T_1853, _T_1855) @[Edges.scala 210:37] + node _T_1857 = and(_T_1856, _T_1834) @[Edges.scala 211:22] + node _T_1858 = not(_T_1849) @[Edges.scala 212:27] + node _T_1859 = and(_T_1843, _T_1858) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1860 = mux(_T_1851, _T_1843, _T_1849) @[Edges.scala 214:21] + _T_1845 <= _T_1860 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1862 : UInt, clock @[Periphery.scala 189:42] + reg _T_1864 : UInt, clock @[Periphery.scala 189:42] + reg _T_1866 : UInt, clock @[Periphery.scala 189:42] + reg _T_1868 : UInt, clock @[Periphery.scala 189:42] + reg _T_1870 : UInt, clock @[Periphery.scala 189:42] + reg _T_1872 : UInt, clock @[Periphery.scala 189:42] + node _T_1874 = eq(_T_1851, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1875 = and(io.in[0].d.valid, _T_1874) @[Periphery.scala 189:42] + when _T_1875 : @[Periphery.scala 189:42] + node _T_1876 = eq(io.in[0].d.bits.opcode, _T_1862) @[Periphery.scala 189:42] + node _T_1877 = or(_T_1876, reset) @[Periphery.scala 189:42] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1879 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1880 = eq(io.in[0].d.bits.param, _T_1864) @[Periphery.scala 189:42] + node _T_1881 = or(_T_1880, reset) @[Periphery.scala 189:42] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1883 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1884 = eq(io.in[0].d.bits.size, _T_1866) @[Periphery.scala 189:42] + node _T_1885 = or(_T_1884, reset) @[Periphery.scala 189:42] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1887 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1888 = eq(io.in[0].d.bits.source, _T_1868) @[Periphery.scala 189:42] + node _T_1889 = or(_T_1888, reset) @[Periphery.scala 189:42] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1891 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1892 = eq(io.in[0].d.bits.sink, _T_1870) @[Periphery.scala 189:42] + node _T_1893 = or(_T_1892, reset) @[Periphery.scala 189:42] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1895 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1896 = eq(io.in[0].d.bits.addr_lo, _T_1872) @[Periphery.scala 189:42] + node _T_1897 = or(_T_1896, reset) @[Periphery.scala 189:42] + node _T_1899 = eq(_T_1897, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1899 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:189:42)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1900 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = and(_T_1900, _T_1851) @[Periphery.scala 189:42] + when _T_1901 : @[Periphery.scala 189:42] + _T_1862 <= io.in[0].d.bits.opcode @[Periphery.scala 189:42] + _T_1864 <= io.in[0].d.bits.param @[Periphery.scala 189:42] + _T_1866 <= io.in[0].d.bits.size @[Periphery.scala 189:42] + _T_1868 <= io.in[0].d.bits.source @[Periphery.scala 189:42] + _T_1870 <= io.in[0].d.bits.sink @[Periphery.scala 189:42] + _T_1872 <= io.in[0].d.bits.addr_lo @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + reg _T_1903 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1904 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1906 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1907 = dshl(_T_1906, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1908 = bits(_T_1907, 7, 0) @[package.scala 19:76] + node _T_1909 = not(_T_1908) @[package.scala 19:40] + node _T_1910 = shr(_T_1909, 3) @[Edges.scala 198:59] + node _T_1911 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1915 = mux(_T_1913, _T_1910, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1917 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1919 = sub(_T_1917, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1920 = asUInt(_T_1919) @[Edges.scala 208:28] + node _T_1921 = tail(_T_1920, 1) @[Edges.scala 208:28] + node _T_1923 = eq(_T_1917, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1925 = eq(_T_1917, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1927 = eq(_T_1915, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1928 = or(_T_1925, _T_1927) @[Edges.scala 210:37] + node _T_1929 = and(_T_1928, _T_1904) @[Edges.scala 211:22] + node _T_1930 = not(_T_1921) @[Edges.scala 212:27] + node _T_1931 = and(_T_1915, _T_1930) @[Edges.scala 212:25] + when _T_1904 : @[Edges.scala 213:17] + node _T_1932 = mux(_T_1923, _T_1915, _T_1921) @[Edges.scala 214:21] + _T_1917 <= _T_1932 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1933 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1935 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1936 = dshl(_T_1935, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1937 = bits(_T_1936, 7, 0) @[package.scala 19:76] + node _T_1938 = not(_T_1937) @[package.scala 19:40] + node _T_1939 = shr(_T_1938, 3) @[Edges.scala 198:59] + node _T_1940 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1942 = mux(_T_1940, _T_1939, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1944 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1946 = sub(_T_1944, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1947 = asUInt(_T_1946) @[Edges.scala 208:28] + node _T_1948 = tail(_T_1947, 1) @[Edges.scala 208:28] + node _T_1950 = eq(_T_1944, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1952 = eq(_T_1944, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1954 = eq(_T_1942, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1955 = or(_T_1952, _T_1954) @[Edges.scala 210:37] + node _T_1956 = and(_T_1955, _T_1933) @[Edges.scala 211:22] + node _T_1957 = not(_T_1948) @[Edges.scala 212:27] + node _T_1958 = and(_T_1942, _T_1957) @[Edges.scala 212:25] + when _T_1933 : @[Edges.scala 213:17] + node _T_1959 = mux(_T_1950, _T_1942, _T_1948) @[Edges.scala 214:21] + _T_1944 <= _T_1959 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1961 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + node _T_1962 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 189:42] + node _T_1963 = or(_T_1961, _T_1962) @[Periphery.scala 189:42] + node _T_1965 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1966 = or(_T_1963, _T_1965) @[Periphery.scala 189:42] + node _T_1968 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1969 = or(_T_1966, _T_1968) @[Periphery.scala 189:42] + node _T_1970 = or(_T_1969, reset) @[Periphery.scala 189:42] + node _T_1972 = eq(_T_1970, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1972 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:189:42)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + wire _T_1974 : UInt<6> + _T_1974 is invalid + _T_1974 <= UInt<6>("h00") + node _T_1975 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1975 : @[Periphery.scala 189:42] + when _T_1928 : @[Periphery.scala 189:42] + node _T_1977 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1974 <= _T_1977 @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1978 = dshr(_T_1903, io.in[0].a.bits.source) @[Periphery.scala 189:42] + node _T_1979 = bits(_T_1978, 0, 0) @[Periphery.scala 189:42] + node _T_1981 = eq(_T_1979, UInt<1>("h00")) @[Periphery.scala 189:42] + node _T_1982 = or(_T_1981, reset) @[Periphery.scala 189:42] + node _T_1984 = eq(_T_1982, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1984 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:189:42)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + wire _T_1986 : UInt<6> + _T_1986 is invalid + _T_1986 <= UInt<6>("h00") + node _T_1987 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1989 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 189:42] + node _T_1990 = and(_T_1987, _T_1989) @[Periphery.scala 189:42] + when _T_1990 : @[Periphery.scala 189:42] + when _T_1955 : @[Periphery.scala 189:42] + node _T_1992 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1986 <= _T_1992 @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1993 = or(_T_1974, _T_1903) @[Periphery.scala 189:42] + node _T_1994 = dshr(_T_1993, io.in[0].d.bits.source) @[Periphery.scala 189:42] + node _T_1995 = bits(_T_1994, 0, 0) @[Periphery.scala 189:42] + node _T_1996 = or(_T_1995, reset) @[Periphery.scala 189:42] + node _T_1998 = eq(_T_1996, UInt<1>("h00")) @[Periphery.scala 189:42] + when _T_1998 : @[Periphery.scala 189:42] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:189:42)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 189:42] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + skip @[Periphery.scala 189:42] + node _T_1999 = or(_T_1903, _T_1974) @[Periphery.scala 189:42] + node _T_2000 = not(_T_1986) @[Periphery.scala 189:42] + node _T_2001 = and(_T_1999, _T_2000) @[Periphery.scala 189:42] + _T_1903 <= _T_2001 @[Periphery.scala 189:42] + + module Queue_12 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<3>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[6] @[Decoupled.scala 182:24] + reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<3>("h05")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + when wrap : @[Counter.scala 28:21] + value <= UInt<1>("h00") @[Counter.scala 28:29] + skip @[Counter.scala 28:21] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<3>("h05")) @[Counter.scala 25:24] + node _T_60 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_61 = tail(_T_60, 1) @[Counter.scala 26:22] + value_1 <= _T_61 @[Counter.scala 26:13] + when wrap_1 : @[Counter.scala 28:21] + value_1 <= UInt<1>("h00") @[Counter.scala 28:29] + skip @[Counter.scala 28:21] + skip @[Decoupled.scala 197:17] + node _T_63 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_63 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_65 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_65 @[Decoupled.scala 204:16] + node _T_67 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_67 @[Decoupled.scala 205:16] + infer mport _T_68 = ram[value_1], clock + io.deq.bits <- _T_68 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_46 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_74 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_75 = asUInt(_T_74) @[Decoupled.scala 221:40] + node _T_76 = tail(_T_75, 1) @[Decoupled.scala 221:40] + node _T_79 = mux(maybe_full, UInt<3>("h06"), UInt<1>("h00")) @[Decoupled.scala 226:24] + node _T_80 = gt(value_1, value) @[Decoupled.scala 228:39] + node _T_82 = add(UInt<3>("h06"), _T_76) @[Decoupled.scala 229:38] + node _T_83 = tail(_T_82, 1) @[Decoupled.scala 229:38] + node _T_84 = mux(_T_80, _T_83, _T_76) @[Decoupled.scala 228:24] + node _T_85 = mux(_T_43, _T_79, _T_84) @[Decoupled.scala 225:20] + io.count <= _T_85 @[Decoupled.scala 225:14] + + module PositionalMultiQueue_16 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_17 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_18 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_19 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_20 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module PositionalMultiQueue_21 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>, way : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2]} + + io is invalid + io is invalid + wire _T_78 : UInt<1>[2] @[PositionalMultiQueue.scala 35:45] + _T_78 is invalid @[PositionalMultiQueue.scala 35:45] + _T_78[0] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + _T_78[1] <= UInt<1>("h01") @[PositionalMultiQueue.scala 35:45] + reg empty : UInt<1>[2], clock with : (reset => (reset, _T_78)) @[Reg.scala 26:44] + reg head : UInt<1>[2], clock @[PositionalMultiQueue.scala 36:18] + reg tail : UInt<1>[2], clock @[PositionalMultiQueue.scala 37:18] + cmem next : UInt<1>[1] @[PositionalMultiQueue.scala 38:18] + cmem data : UInt<6>[1] @[PositionalMultiQueue.scala 39:18] + reg guard : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when io.enq.valid : @[PositionalMultiQueue.scala 43:24] + infer mport _T_109 = data[UInt<1>("h00")], clock + _T_109 <= io.enq.bits.data @[PositionalMultiQueue.scala 44:27] + node _T_110 = dshr(guard, io.enq.bits.pos) @[PositionalMultiQueue.scala 46:19] + node _T_111 = bits(_T_110, 0, 0) @[PositionalMultiQueue.scala 46:19] + node _T_113 = eq(_T_111, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:13] + node _T_114 = or(_T_113, reset) @[PositionalMultiQueue.scala 46:12] + node _T_116 = eq(_T_114, UInt<1>("h00")) @[PositionalMultiQueue.scala 46:12] + when _T_116 : @[PositionalMultiQueue.scala 46:12] + printf(clock, UInt<1>(1), "Assertion failed\n at PositionalMultiQueue.scala:46 assert (!guard(io.enq.bits.pos))\n") @[PositionalMultiQueue.scala 46:12] + stop(clock, UInt<1>(1), 1) @[PositionalMultiQueue.scala 46:12] + skip @[PositionalMultiQueue.scala 46:12] + node _T_120 = eq(empty[io.enq.bits.way], UInt<1>("h00")) @[PositionalMultiQueue.scala 48:11] + when _T_120 : @[PositionalMultiQueue.scala 48:36] + infer mport _T_123 = next[UInt<1>("h00")], clock + _T_123 <= io.enq.bits.pos @[PositionalMultiQueue.scala 49:35] + skip @[PositionalMultiQueue.scala 48:36] + skip @[PositionalMultiQueue.scala 43:24] + node setGuard = dshl(io.enq.valid, io.enq.bits.pos) @[PositionalMultiQueue.scala 52:32] + wire deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<6>, pos : UInt<1>}}[2] @[PositionalMultiQueue.scala 54:17] + deq is invalid @[PositionalMultiQueue.scala 54:17] + io.deq <- deq @[PositionalMultiQueue.scala 55:10] + node _T_189 = bits(io.enq.bits.way, 0, 0) @[OneHot.scala 49:17] + node _T_190 = dshl(UInt<1>("h01"), _T_189) @[OneHot.scala 49:12] + node waySelect = bits(_T_190, 1, 0) @[OneHot.scala 49:37] + node _T_192 = bits(waySelect, 0, 0) @[PositionalMultiQueue.scala 60:41] + node _T_193 = and(io.enq.valid, _T_192) @[PositionalMultiQueue.scala 60:29] + node _T_194 = eq(head[0], tail[0]) @[PositionalMultiQueue.scala 61:24] + when _T_193 : @[PositionalMultiQueue.scala 63:16] + tail[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[0] : @[PositionalMultiQueue.scala 65:23] + head[0] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_196 = eq(empty[0], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[0].valid <= _T_196 @[PositionalMultiQueue.scala 75:20] + deq[0].bits.pos <= head[0] @[PositionalMultiQueue.scala 76:23] + infer mport _T_198 = data[UInt<1>("h00")], clock + deq[0].bits.data <= _T_198 @[PositionalMultiQueue.scala 77:24] + node _T_199 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + when _T_199 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_201 = next[UInt<1>("h00")], clock + node _T_202 = mux(_T_194, io.enq.bits.pos, _T_201) @[PositionalMultiQueue.scala 81:21] + head[0] <= _T_202 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_203 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_204 = dshl(_T_203, deq[0].bits.pos) @[PositionalMultiQueue.scala 83:42] + node _T_205 = or(UInt<1>("h00"), _T_204) @[PositionalMultiQueue.scala 83:25] + node _T_206 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_207 = neq(_T_193, _T_206) @[PositionalMultiQueue.scala 85:15] + when _T_207 : @[PositionalMultiQueue.scala 85:34] + node _T_208 = and(deq[0].ready, deq[0].valid) @[Decoupled.scala 30:37] + node _T_209 = and(_T_208, _T_194) @[PositionalMultiQueue.scala 86:33] + empty[0] <= _T_209 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_210 = bits(waySelect, 1, 1) @[PositionalMultiQueue.scala 60:41] + node _T_211 = and(io.enq.valid, _T_210) @[PositionalMultiQueue.scala 60:29] + node _T_212 = eq(head[1], tail[1]) @[PositionalMultiQueue.scala 61:24] + when _T_211 : @[PositionalMultiQueue.scala 63:16] + tail[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 64:15] + when empty[1] : @[PositionalMultiQueue.scala 65:23] + head[1] <= io.enq.bits.pos @[PositionalMultiQueue.scala 66:17] + skip @[PositionalMultiQueue.scala 65:23] + skip @[PositionalMultiQueue.scala 63:16] + node _T_214 = eq(empty[1], UInt<1>("h00")) @[PositionalMultiQueue.scala 75:23] + deq[1].valid <= _T_214 @[PositionalMultiQueue.scala 75:20] + deq[1].bits.pos <= head[1] @[PositionalMultiQueue.scala 76:23] + infer mport _T_216 = data[UInt<1>("h00")], clock + deq[1].bits.data <= _T_216 @[PositionalMultiQueue.scala 77:24] + node _T_217 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + when _T_217 : @[PositionalMultiQueue.scala 80:26] + infer mport _T_219 = next[UInt<1>("h00")], clock + node _T_220 = mux(_T_212, io.enq.bits.pos, _T_219) @[PositionalMultiQueue.scala 81:21] + head[1] <= _T_220 @[PositionalMultiQueue.scala 81:15] + skip @[PositionalMultiQueue.scala 80:26] + node _T_221 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_222 = dshl(_T_221, deq[1].bits.pos) @[PositionalMultiQueue.scala 83:42] + node clrGuard = or(_T_205, _T_222) @[PositionalMultiQueue.scala 83:25] + node _T_223 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_224 = neq(_T_211, _T_223) @[PositionalMultiQueue.scala 85:15] + when _T_224 : @[PositionalMultiQueue.scala 85:34] + node _T_225 = and(deq[1].ready, deq[1].valid) @[Decoupled.scala 30:37] + node _T_226 = and(_T_225, _T_212) @[PositionalMultiQueue.scala 86:33] + empty[1] <= _T_226 @[PositionalMultiQueue.scala 86:16] + skip @[PositionalMultiQueue.scala 85:34] + node _T_227 = or(guard, setGuard) @[PositionalMultiQueue.scala 90:19] + node _T_228 = not(clrGuard) @[PositionalMultiQueue.scala 90:33] + node _T_229 = and(_T_227, _T_228) @[PositionalMultiQueue.scala 90:31] + guard <= _T_229 @[PositionalMultiQueue.scala 90:9] + + module Queue_13 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_48 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_50 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_51 = and(_T_48, _T_50) @[Decoupled.scala 188:33] + node _T_52 = and(_T_48, maybe_full) @[Decoupled.scala 189:32] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_53 + node _T_54 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_54 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_56 = ram[UInt<1>("h00")], clock + _T_56 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_62 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_62 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_64 = eq(_T_51, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_64 @[Decoupled.scala 204:16] + node _T_66 = eq(_T_52, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_66 @[Decoupled.scala 205:16] + infer mport _T_68 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_68 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_51 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_75 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_76 = asUInt(_T_75) @[Decoupled.scala 221:40] + node _T_77 = tail(_T_76, 1) @[Decoupled.scala 221:40] + node _T_78 = and(maybe_full, _T_48) @[Decoupled.scala 223:32] + node _T_79 = cat(_T_78, _T_77) @[Cat.scala 30:58] + io.count <= _T_79 @[Decoupled.scala 223:14] + + module Queue_14 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_97 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_99 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_100 = and(_T_97, _T_99) @[Decoupled.scala 188:33] + node _T_101 = and(_T_97, maybe_full) @[Decoupled.scala 189:32] + node _T_102 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_102 + node _T_103 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_103 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_105 = ram[UInt<1>("h00")], clock + _T_105 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_118 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_118 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_120 = eq(_T_100, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_120 @[Decoupled.scala 204:16] + node _T_122 = eq(_T_101, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_122 @[Decoupled.scala 205:16] + infer mport _T_124 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_124 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_100 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_138 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_139 = asUInt(_T_138) @[Decoupled.scala 221:40] + node _T_140 = tail(_T_139, 1) @[Decoupled.scala 221:40] + node _T_141 = and(maybe_full, _T_97) @[Decoupled.scala 223:32] + node _T_142 = cat(_T_141, _T_140) @[Cat.scala 30:58] + io.count <= _T_142 @[Decoupled.scala 223:14] + + module TLToAXI4 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_12 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + wire _T_517 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}} @[Decoupled.scala 272:19] + _T_517 is invalid @[Decoupled.scala 272:19] + _T_517.bits <- Queue.io.deq.bits @[Decoupled.scala 273:14] + _T_517.valid <= Queue.io.deq.valid @[Decoupled.scala 274:15] + Queue.io.deq.ready <= _T_517.ready @[Decoupled.scala 275:15] + node _T_528 = bits(io.in.0.a.bits.address, 2, 0) @[Edges.scala 172:47] + node _T_529 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_531 = eq(_T_529, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_532 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_534 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_535 = dshl(_T_534, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_536 = bits(_T_535, 7, 0) @[package.scala 19:76] + node _T_537 = not(_T_536) @[package.scala 19:40] + node _T_538 = shr(_T_537, 3) @[Edges.scala 198:59] + node _T_539 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_541 = eq(_T_539, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_543 = mux(_T_541, _T_538, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_545 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_547 = sub(_T_545, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_548 = asUInt(_T_547) @[Edges.scala 208:28] + node _T_549 = tail(_T_548, 1) @[Edges.scala 208:28] + node _T_551 = eq(_T_545, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_553 = eq(_T_545, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_555 = eq(_T_543, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_556 = or(_T_553, _T_555) @[Edges.scala 210:37] + node _T_557 = and(_T_556, _T_532) @[Edges.scala 211:22] + node _T_558 = not(_T_549) @[Edges.scala 212:27] + node _T_559 = and(_T_543, _T_558) @[Edges.scala 212:25] + when _T_532 : @[Edges.scala 213:17] + node _T_560 = mux(_T_551, _T_543, _T_549) @[Edges.scala 214:21] + _T_545 <= _T_560 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_562 = lt(io.in.0.a.bits.source, UInt<4>("h08")) @[ToAXI4.scala 82:25] + node _T_563 = or(_T_562, reset) @[ToAXI4.scala 82:14] + node _T_565 = eq(_T_563, UInt<1>("h00")) @[ToAXI4.scala 82:14] + when _T_565 : @[ToAXI4.scala 82:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:82 assert (a_source < UInt(BigInt(1) << sourceBits))\n") @[ToAXI4.scala 82:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 82:14] + skip @[ToAXI4.scala 82:14] + node _T_567 = lt(io.in.0.a.bits.size, UInt<5>("h010")) @[ToAXI4.scala 83:25] + node _T_568 = or(_T_567, reset) @[ToAXI4.scala 83:14] + node _T_570 = eq(_T_568, UInt<1>("h00")) @[ToAXI4.scala 83:14] + when _T_570 : @[ToAXI4.scala 83:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:83 assert (a_size < UInt(BigInt(1) << sizeBits))\n") @[ToAXI4.scala 83:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 83:14] + skip @[ToAXI4.scala 83:14] + node _T_572 = lt(_T_528, UInt<4>("h08")) @[ToAXI4.scala 84:25] + node _T_573 = or(_T_572, reset) @[ToAXI4.scala 84:14] + node _T_575 = eq(_T_573, UInt<1>("h00")) @[ToAXI4.scala 84:14] + when _T_575 : @[ToAXI4.scala 84:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:84 assert (a_addr_lo < UInt(BigInt(1) << addrBits))\n") @[ToAXI4.scala 84:14] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 84:14] + skip @[ToAXI4.scala 84:14] + node _T_576 = shl(io.in.0.a.bits.source, 0) @[ToAXI4.scala 93:31] + node _T_577 = shl(io.in.0.a.bits.size, 3) @[ToAXI4.scala 93:55] + node _T_578 = or(_T_576, _T_577) @[ToAXI4.scala 93:45] + node _T_579 = shl(_T_528, 7) @[ToAXI4.scala 93:80] + node _T_580 = or(_T_578, _T_579) @[ToAXI4.scala 93:67] + wire _T_582 : UInt<10> @[ToAXI4.scala 96:25] + _T_582 is invalid @[ToAXI4.scala 96:25] + node _T_583 = bits(_T_582, 2, 0) @[ToAXI4.scala 97:50] + node _T_584 = bits(_T_582, 6, 3) @[ToAXI4.scala 98:50] + node _T_585 = bits(_T_582, 9, 7) @[ToAXI4.scala 99:50] + wire _T_587 : UInt<10> @[ToAXI4.scala 101:25] + _T_587 is invalid @[ToAXI4.scala 101:25] + node _T_588 = bits(_T_587, 2, 0) @[ToAXI4.scala 102:50] + node _T_589 = bits(_T_587, 6, 3) @[ToAXI4.scala 103:50] + node _T_590 = bits(_T_587, 9, 7) @[ToAXI4.scala 104:50] + inst PositionalMultiQueue of PositionalMultiQueue_16 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue.io is invalid + PositionalMultiQueue.clock <= clock + PositionalMultiQueue.reset <= reset + inst PositionalMultiQueue_1 of PositionalMultiQueue_17 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_1.io is invalid + PositionalMultiQueue_1.clock <= clock + PositionalMultiQueue_1.reset <= reset + inst PositionalMultiQueue_2 of PositionalMultiQueue_18 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_2.io is invalid + PositionalMultiQueue_2.clock <= clock + PositionalMultiQueue_2.reset <= reset + inst PositionalMultiQueue_3 of PositionalMultiQueue_19 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_3.io is invalid + PositionalMultiQueue_3.clock <= clock + PositionalMultiQueue_3.reset <= reset + inst PositionalMultiQueue_4 of PositionalMultiQueue_20 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_4.io is invalid + PositionalMultiQueue_4.clock <= clock + PositionalMultiQueue_4.reset <= reset + inst PositionalMultiQueue_5 of PositionalMultiQueue_21 @[PositionalMultiQueue.scala 96:11] + PositionalMultiQueue_5.io is invalid + PositionalMultiQueue_5.clock <= clock + PositionalMultiQueue_5.reset <= reset + node _T_598 = bits(io.in.0.a.bits.source, 2, 0) @[ToAXI4.scala 130:72] + node _T_599 = bits(io.out.0.r.bits.id, 2, 0) @[ToAXI4.scala 131:68] + node _T_600 = bits(_T_517.bits.id, 2, 0) @[ToAXI4.scala 132:68] + node _T_602 = bits(_T_598, 2, 0) @[OneHot.scala 49:17] + node _T_603 = dshl(UInt<1>("h01"), _T_602) @[OneHot.scala 49:12] + node _T_604 = bits(_T_603, 5, 0) @[OneHot.scala 49:37] + node _T_606 = bits(_T_599, 2, 0) @[OneHot.scala 49:17] + node _T_607 = dshl(UInt<1>("h01"), _T_606) @[OneHot.scala 49:12] + node _T_608 = bits(_T_607, 5, 0) @[OneHot.scala 49:37] + node _T_610 = bits(_T_600, 2, 0) @[OneHot.scala 49:17] + node _T_611 = dshl(UInt<1>("h01"), _T_610) @[OneHot.scala 49:12] + node _T_612 = bits(_T_611, 5, 0) @[OneHot.scala 49:37] + node _T_613 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_614 = and(_T_613, _T_556) @[ToAXI4.scala 139:41] + node _T_615 = bits(_T_604, 0, 0) @[ToAXI4.scala 139:66] + node _T_616 = and(_T_614, _T_615) @[ToAXI4.scala 139:51] + PositionalMultiQueue.io.enq.valid <= _T_616 @[ToAXI4.scala 139:26] + PositionalMultiQueue.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_617 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue.io.enq.bits.data <= _T_617 @[ToAXI4.scala 141:30] + node _T_620 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue.io.enq.bits.way <= _T_620 @[ToAXI4.scala 142:30] + node _T_621 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_622 = bits(_T_612, 0, 0) @[ToAXI4.scala 144:60] + node _T_623 = and(_T_621, _T_622) @[ToAXI4.scala 144:45] + PositionalMultiQueue.io.deq[0].ready <= _T_623 @[ToAXI4.scala 144:29] + node _T_624 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_625 = bits(_T_608, 0, 0) @[ToAXI4.scala 145:60] + node _T_626 = and(_T_624, _T_625) @[ToAXI4.scala 145:45] + node _T_627 = and(_T_626, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue.io.deq[1].ready <= _T_627 @[ToAXI4.scala 145:29] + node _T_629 = eq(PositionalMultiQueue.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_630 = or(PositionalMultiQueue.io.deq[0].valid, _T_629) @[ToAXI4.scala 147:37] + node _T_631 = or(_T_630, reset) @[ToAXI4.scala 147:18] + node _T_633 = eq(_T_631, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_633 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_635 = eq(PositionalMultiQueue.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_636 = or(PositionalMultiQueue.io.deq[1].valid, _T_635) @[ToAXI4.scala 148:37] + node _T_637 = or(_T_636, reset) @[ToAXI4.scala 148:18] + node _T_639 = eq(_T_637, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_639 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_640 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_641 = and(_T_640, _T_556) @[ToAXI4.scala 139:41] + node _T_642 = bits(_T_604, 1, 1) @[ToAXI4.scala 139:66] + node _T_643 = and(_T_641, _T_642) @[ToAXI4.scala 139:51] + PositionalMultiQueue_1.io.enq.valid <= _T_643 @[ToAXI4.scala 139:26] + PositionalMultiQueue_1.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_644 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue_1.io.enq.bits.data <= _T_644 @[ToAXI4.scala 141:30] + node _T_647 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_1.io.enq.bits.way <= _T_647 @[ToAXI4.scala 142:30] + node _T_648 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_649 = bits(_T_612, 1, 1) @[ToAXI4.scala 144:60] + node _T_650 = and(_T_648, _T_649) @[ToAXI4.scala 144:45] + PositionalMultiQueue_1.io.deq[0].ready <= _T_650 @[ToAXI4.scala 144:29] + node _T_651 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_652 = bits(_T_608, 1, 1) @[ToAXI4.scala 145:60] + node _T_653 = and(_T_651, _T_652) @[ToAXI4.scala 145:45] + node _T_654 = and(_T_653, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_1.io.deq[1].ready <= _T_654 @[ToAXI4.scala 145:29] + node _T_656 = eq(PositionalMultiQueue_1.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_657 = or(PositionalMultiQueue_1.io.deq[0].valid, _T_656) @[ToAXI4.scala 147:37] + node _T_658 = or(_T_657, reset) @[ToAXI4.scala 147:18] + node _T_660 = eq(_T_658, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_660 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_662 = eq(PositionalMultiQueue_1.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_663 = or(PositionalMultiQueue_1.io.deq[1].valid, _T_662) @[ToAXI4.scala 148:37] + node _T_664 = or(_T_663, reset) @[ToAXI4.scala 148:18] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_666 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_667 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_668 = and(_T_667, _T_556) @[ToAXI4.scala 139:41] + node _T_669 = bits(_T_604, 2, 2) @[ToAXI4.scala 139:66] + node _T_670 = and(_T_668, _T_669) @[ToAXI4.scala 139:51] + PositionalMultiQueue_2.io.enq.valid <= _T_670 @[ToAXI4.scala 139:26] + PositionalMultiQueue_2.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_671 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue_2.io.enq.bits.data <= _T_671 @[ToAXI4.scala 141:30] + node _T_674 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_2.io.enq.bits.way <= _T_674 @[ToAXI4.scala 142:30] + node _T_675 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_676 = bits(_T_612, 2, 2) @[ToAXI4.scala 144:60] + node _T_677 = and(_T_675, _T_676) @[ToAXI4.scala 144:45] + PositionalMultiQueue_2.io.deq[0].ready <= _T_677 @[ToAXI4.scala 144:29] + node _T_678 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_679 = bits(_T_608, 2, 2) @[ToAXI4.scala 145:60] + node _T_680 = and(_T_678, _T_679) @[ToAXI4.scala 145:45] + node _T_681 = and(_T_680, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_2.io.deq[1].ready <= _T_681 @[ToAXI4.scala 145:29] + node _T_683 = eq(PositionalMultiQueue_2.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_684 = or(PositionalMultiQueue_2.io.deq[0].valid, _T_683) @[ToAXI4.scala 147:37] + node _T_685 = or(_T_684, reset) @[ToAXI4.scala 147:18] + node _T_687 = eq(_T_685, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_687 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_689 = eq(PositionalMultiQueue_2.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_690 = or(PositionalMultiQueue_2.io.deq[1].valid, _T_689) @[ToAXI4.scala 148:37] + node _T_691 = or(_T_690, reset) @[ToAXI4.scala 148:18] + node _T_693 = eq(_T_691, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_693 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_694 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_695 = and(_T_694, _T_556) @[ToAXI4.scala 139:41] + node _T_696 = bits(_T_604, 3, 3) @[ToAXI4.scala 139:66] + node _T_697 = and(_T_695, _T_696) @[ToAXI4.scala 139:51] + PositionalMultiQueue_3.io.enq.valid <= _T_697 @[ToAXI4.scala 139:26] + PositionalMultiQueue_3.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_698 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue_3.io.enq.bits.data <= _T_698 @[ToAXI4.scala 141:30] + node _T_701 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_3.io.enq.bits.way <= _T_701 @[ToAXI4.scala 142:30] + node _T_702 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_703 = bits(_T_612, 3, 3) @[ToAXI4.scala 144:60] + node _T_704 = and(_T_702, _T_703) @[ToAXI4.scala 144:45] + PositionalMultiQueue_3.io.deq[0].ready <= _T_704 @[ToAXI4.scala 144:29] + node _T_705 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_706 = bits(_T_608, 3, 3) @[ToAXI4.scala 145:60] + node _T_707 = and(_T_705, _T_706) @[ToAXI4.scala 145:45] + node _T_708 = and(_T_707, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_3.io.deq[1].ready <= _T_708 @[ToAXI4.scala 145:29] + node _T_710 = eq(PositionalMultiQueue_3.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_711 = or(PositionalMultiQueue_3.io.deq[0].valid, _T_710) @[ToAXI4.scala 147:37] + node _T_712 = or(_T_711, reset) @[ToAXI4.scala 147:18] + node _T_714 = eq(_T_712, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_714 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_716 = eq(PositionalMultiQueue_3.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_717 = or(PositionalMultiQueue_3.io.deq[1].valid, _T_716) @[ToAXI4.scala 148:37] + node _T_718 = or(_T_717, reset) @[ToAXI4.scala 148:18] + node _T_720 = eq(_T_718, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_720 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_721 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_722 = and(_T_721, _T_556) @[ToAXI4.scala 139:41] + node _T_723 = bits(_T_604, 4, 4) @[ToAXI4.scala 139:66] + node _T_724 = and(_T_722, _T_723) @[ToAXI4.scala 139:51] + PositionalMultiQueue_4.io.enq.valid <= _T_724 @[ToAXI4.scala 139:26] + PositionalMultiQueue_4.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_725 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue_4.io.enq.bits.data <= _T_725 @[ToAXI4.scala 141:30] + node _T_728 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_4.io.enq.bits.way <= _T_728 @[ToAXI4.scala 142:30] + node _T_729 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_730 = bits(_T_612, 4, 4) @[ToAXI4.scala 144:60] + node _T_731 = and(_T_729, _T_730) @[ToAXI4.scala 144:45] + PositionalMultiQueue_4.io.deq[0].ready <= _T_731 @[ToAXI4.scala 144:29] + node _T_732 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_733 = bits(_T_608, 4, 4) @[ToAXI4.scala 145:60] + node _T_734 = and(_T_732, _T_733) @[ToAXI4.scala 145:45] + node _T_735 = and(_T_734, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_4.io.deq[1].ready <= _T_735 @[ToAXI4.scala 145:29] + node _T_737 = eq(PositionalMultiQueue_4.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_738 = or(PositionalMultiQueue_4.io.deq[0].valid, _T_737) @[ToAXI4.scala 147:37] + node _T_739 = or(_T_738, reset) @[ToAXI4.scala 147:18] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_741 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_743 = eq(PositionalMultiQueue_4.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_744 = or(PositionalMultiQueue_4.io.deq[1].valid, _T_743) @[ToAXI4.scala 148:37] + node _T_745 = or(_T_744, reset) @[ToAXI4.scala 148:18] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_747 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + node _T_748 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_749 = and(_T_748, _T_556) @[ToAXI4.scala 139:41] + node _T_750 = bits(_T_604, 5, 5) @[ToAXI4.scala 139:66] + node _T_751 = and(_T_749, _T_750) @[ToAXI4.scala 139:51] + PositionalMultiQueue_5.io.enq.valid <= _T_751 @[ToAXI4.scala 139:26] + PositionalMultiQueue_5.io.enq.bits.pos <= UInt<1>("h00") @[ToAXI4.scala 140:30] + node _T_752 = shr(_T_580, 4) @[ToAXI4.scala 141:41] + PositionalMultiQueue_5.io.enq.bits.data <= _T_752 @[ToAXI4.scala 141:30] + node _T_755 = mux(_T_531, UInt<1>("h00"), UInt<1>("h01")) @[ToAXI4.scala 142:36] + PositionalMultiQueue_5.io.enq.bits.way <= _T_755 @[ToAXI4.scala 142:30] + node _T_756 = and(_T_517.ready, _T_517.valid) @[Decoupled.scala 30:37] + node _T_757 = bits(_T_612, 5, 5) @[ToAXI4.scala 144:60] + node _T_758 = and(_T_756, _T_757) @[ToAXI4.scala 144:45] + PositionalMultiQueue_5.io.deq[0].ready <= _T_758 @[ToAXI4.scala 144:29] + node _T_759 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + node _T_760 = bits(_T_608, 5, 5) @[ToAXI4.scala 145:60] + node _T_761 = and(_T_759, _T_760) @[ToAXI4.scala 145:45] + node _T_762 = and(_T_761, io.out.0.r.bits.last) @[ToAXI4.scala 145:64] + PositionalMultiQueue_5.io.deq[1].ready <= _T_762 @[ToAXI4.scala 145:29] + node _T_764 = eq(PositionalMultiQueue_5.io.deq[0].ready, UInt<1>("h00")) @[ToAXI4.scala 147:40] + node _T_765 = or(PositionalMultiQueue_5.io.deq[0].valid, _T_764) @[ToAXI4.scala 147:37] + node _T_766 = or(_T_765, reset) @[ToAXI4.scala 147:18] + node _T_768 = eq(_T_766, UInt<1>("h00")) @[ToAXI4.scala 147:18] + when _T_768 : @[ToAXI4.scala 147:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:147 assert (q.io.deq(0).valid || !q.io.deq(0).ready)\n") @[ToAXI4.scala 147:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 147:18] + skip @[ToAXI4.scala 147:18] + node _T_770 = eq(PositionalMultiQueue_5.io.deq[1].ready, UInt<1>("h00")) @[ToAXI4.scala 148:40] + node _T_771 = or(PositionalMultiQueue_5.io.deq[1].valid, _T_770) @[ToAXI4.scala 148:37] + node _T_772 = or(_T_771, reset) @[ToAXI4.scala 148:18] + node _T_774 = eq(_T_772, UInt<1>("h00")) @[ToAXI4.scala 148:18] + when _T_774 : @[ToAXI4.scala 148:18] + printf(clock, UInt<1>(1), "Assertion failed\n at ToAXI4.scala:148 assert (q.io.deq(1).valid || !q.io.deq(1).ready)\n") @[ToAXI4.scala 148:18] + stop(clock, UInt<1>(1), 1) @[ToAXI4.scala 148:18] + skip @[ToAXI4.scala 148:18] + wire _T_777 : UInt<6>[6] @[ToAXI4.scala 151:29] + _T_777 is invalid @[ToAXI4.scala 151:29] + _T_777[0] <= PositionalMultiQueue.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_777[1] <= PositionalMultiQueue_1.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_777[2] <= PositionalMultiQueue_2.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_777[3] <= PositionalMultiQueue_3.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_777[4] <= PositionalMultiQueue_4.io.deq[0].bits.data @[ToAXI4.scala 151:29] + _T_777[5] <= PositionalMultiQueue_5.io.deq[0].bits.data @[ToAXI4.scala 151:29] + wire _T_789 : UInt<1>[6] @[ToAXI4.scala 152:29] + _T_789 is invalid @[ToAXI4.scala 152:29] + _T_789[0] <= PositionalMultiQueue.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_789[1] <= PositionalMultiQueue_1.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_789[2] <= PositionalMultiQueue_2.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_789[3] <= PositionalMultiQueue_3.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_789[4] <= PositionalMultiQueue_4.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + _T_789[5] <= PositionalMultiQueue_5.io.deq[0].bits.pos @[ToAXI4.scala 152:29] + wire _T_801 : UInt<6>[6] @[ToAXI4.scala 153:29] + _T_801 is invalid @[ToAXI4.scala 153:29] + _T_801[0] <= PositionalMultiQueue.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_801[1] <= PositionalMultiQueue_1.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_801[2] <= PositionalMultiQueue_2.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_801[3] <= PositionalMultiQueue_3.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_801[4] <= PositionalMultiQueue_4.io.deq[1].bits.data @[ToAXI4.scala 153:29] + _T_801[5] <= PositionalMultiQueue_5.io.deq[1].bits.data @[ToAXI4.scala 153:29] + wire _T_813 : UInt<1>[6] @[ToAXI4.scala 154:29] + _T_813 is invalid @[ToAXI4.scala 154:29] + _T_813[0] <= PositionalMultiQueue.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_813[1] <= PositionalMultiQueue_1.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_813[2] <= PositionalMultiQueue_2.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_813[3] <= PositionalMultiQueue_3.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_813[4] <= PositionalMultiQueue_4.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + _T_813[5] <= PositionalMultiQueue_5.io.deq[1].bits.pos @[ToAXI4.scala 154:29] + node _T_823 = cat(_T_777[_T_600], _T_517.bits.id) @[Cat.scala 30:58] + _T_587 <= _T_823 @[ToAXI4.scala 157:17] + node _T_824 = cat(_T_801[_T_599], io.out.0.r.bits.id) @[Cat.scala 30:58] + _T_582 <= _T_824 @[ToAXI4.scala 158:17] + wire _T_863 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}} @[ToAXI4.scala 163:25] + _T_863 is invalid @[ToAXI4.scala 163:25] + wire _T_890 : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}} @[ToAXI4.scala 164:23] + _T_890 is invalid @[ToAXI4.scala 164:23] + inst Queue_1 of Queue_13 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= _T_890.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- _T_890.bits @[Decoupled.scala 255:19] + _T_890.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + wire _T_920 : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}} @[Decoupled.scala 272:19] + _T_920 is invalid @[Decoupled.scala 272:19] + _T_920.bits <- Queue_1.io.deq.bits @[Decoupled.scala 273:14] + _T_920.valid <= Queue_1.io.deq.valid @[Decoupled.scala 274:15] + Queue_1.io.deq.ready <= _T_920.ready @[Decoupled.scala 275:15] + io.out.0.w <- _T_920 @[ToAXI4.scala 165:13] + inst Queue_2 of Queue_14 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_863.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_863.bits @[Decoupled.scala 255:19] + _T_863.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + wire _T_971 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, wen : UInt<1>}} @[Decoupled.scala 272:19] + _T_971 is invalid @[Decoupled.scala 272:19] + _T_971.bits <- Queue_2.io.deq.bits @[Decoupled.scala 273:14] + _T_971.valid <= Queue_2.io.deq.valid @[Decoupled.scala 274:15] + Queue_2.io.deq.ready <= _T_971.ready @[Decoupled.scala 275:15] + io.out.0.ar.bits <- _T_971.bits @[ToAXI4.scala 169:19] + io.out.0.aw.bits <- _T_971.bits @[ToAXI4.scala 170:19] + node _T_999 = eq(_T_971.bits.wen, UInt<1>("h00")) @[ToAXI4.scala 171:42] + node _T_1000 = and(_T_971.valid, _T_999) @[ToAXI4.scala 171:39] + io.out.0.ar.valid <= _T_1000 @[ToAXI4.scala 171:20] + node _T_1001 = and(_T_971.valid, _T_971.bits.wen) @[ToAXI4.scala 172:39] + io.out.0.aw.valid <= _T_1001 @[ToAXI4.scala 172:20] + node _T_1002 = mux(_T_971.bits.wen, io.out.0.aw.ready, io.out.0.ar.ready) @[ToAXI4.scala 173:29] + _T_971.ready <= _T_1002 @[ToAXI4.scala 173:23] + reg _T_1005 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1006 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + when _T_1006 : @[ToAXI4.scala 178:26] + node _T_1008 = eq(_T_556, UInt<1>("h00")) @[ToAXI4.scala 178:38] + _T_1005 <= _T_1008 @[ToAXI4.scala 178:35] + skip @[ToAXI4.scala 178:26] + _T_863.bits.wen <= _T_531 @[ToAXI4.scala 181:17] + _T_863.bits.id <= _T_580 @[ToAXI4.scala 182:17] + _T_863.bits.addr <= io.in.0.a.bits.address @[ToAXI4.scala 183:17] + node _T_1010 = asUInt(asSInt(UInt<11>("h07ff"))) @[package.scala 19:64] + node _T_1011 = dshl(_T_1010, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_1012 = bits(_T_1011, 10, 0) @[package.scala 19:76] + node _T_1013 = not(_T_1012) @[package.scala 19:40] + node _T_1014 = shr(_T_1013, 3) @[ToAXI4.scala 184:84] + _T_863.bits.len <= _T_1014 @[ToAXI4.scala 184:17] + node _T_1015 = geq(io.in.0.a.bits.size, UInt<2>("h03")) @[ToAXI4.scala 185:31] + node _T_1016 = mux(_T_1015, UInt<2>("h03"), io.in.0.a.bits.size) @[ToAXI4.scala 185:23] + _T_863.bits.size <= _T_1016 @[ToAXI4.scala 185:17] + _T_863.bits.burst <= UInt<2>("h01") @[ToAXI4.scala 186:17] + _T_863.bits.lock <= UInt<1>("h00") @[ToAXI4.scala 187:17] + _T_863.bits.cache <= UInt<1>("h00") @[ToAXI4.scala 188:17] + _T_863.bits.prot <= UInt<3>("h01") @[ToAXI4.scala 189:17] + _T_863.bits.qos <= UInt<1>("h00") @[ToAXI4.scala 190:17] + node _T_1022 = or(_T_1005, _T_863.ready) @[ToAXI4.scala 192:42] + node _T_1023 = and(_T_1022, _T_890.ready) @[ToAXI4.scala 192:60] + node _T_1024 = mux(_T_531, _T_1023, _T_863.ready) @[ToAXI4.scala 192:24] + io.in.0.a.ready <= _T_1024 @[ToAXI4.scala 192:18] + node _T_1026 = eq(_T_1005, UInt<1>("h00")) @[ToAXI4.scala 193:51] + node _T_1027 = and(_T_1026, _T_890.ready) @[ToAXI4.scala 193:59] + node _T_1029 = mux(_T_531, _T_1027, UInt<1>("h01")) @[ToAXI4.scala 193:41] + node _T_1030 = and(io.in.0.a.valid, _T_1029) @[ToAXI4.scala 193:35] + _T_863.valid <= _T_1030 @[ToAXI4.scala 193:21] + node _T_1031 = and(io.in.0.a.valid, _T_531) @[ToAXI4.scala 195:33] + node _T_1032 = or(_T_1005, _T_863.ready) @[ToAXI4.scala 195:55] + node _T_1033 = and(_T_1031, _T_1032) @[ToAXI4.scala 195:44] + _T_890.valid <= _T_1033 @[ToAXI4.scala 195:19] + _T_890.bits.data <= io.in.0.a.bits.data @[ToAXI4.scala 196:23] + _T_890.bits.strb <= io.in.0.a.bits.mask @[ToAXI4.scala 197:23] + _T_890.bits.last <= _T_556 @[ToAXI4.scala 198:23] + reg _T_1035 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1036 = and(io.out.0.r.ready, io.out.0.r.valid) @[Decoupled.scala 30:37] + when _T_1036 : @[ToAXI4.scala 202:27] + node _T_1038 = eq(io.out.0.r.bits.last, UInt<1>("h00")) @[ToAXI4.scala 202:42] + _T_1035 <= _T_1038 @[ToAXI4.scala 202:39] + skip @[ToAXI4.scala 202:27] + node _T_1039 = or(io.out.0.r.valid, _T_1035) @[ToAXI4.scala 204:32] + io.out.0.r.ready <= io.in.0.d.ready @[ToAXI4.scala 206:19] + node _T_1041 = eq(_T_1039, UInt<1>("h00")) @[ToAXI4.scala 207:36] + node _T_1042 = and(io.in.0.d.ready, _T_1041) @[ToAXI4.scala 207:33] + _T_517.ready <= _T_1042 @[ToAXI4.scala 207:19] + node _T_1043 = mux(_T_1039, io.out.0.r.valid, _T_517.valid) @[ToAXI4.scala 208:24] + io.in.0.d.valid <= _T_1043 @[ToAXI4.scala 208:18] + node _T_1045 = neq(io.out.0.r.bits.resp, UInt<2>("h00")) @[ToAXI4.scala 210:37] + node _T_1047 = neq(_T_517.bits.resp, UInt<2>("h00")) @[ToAXI4.scala 211:37] + wire _T_1059 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 633:17] + _T_1059 is invalid @[Edges.scala 633:17] + _T_1059.opcode <= UInt<1>("h01") @[Edges.scala 634:15] + _T_1059.param <= UInt<1>("h00") @[Edges.scala 635:15] + _T_1059.size <= _T_584 @[Edges.scala 636:15] + _T_1059.source <= _T_583 @[Edges.scala 637:15] + _T_1059.sink <= UInt<1>("h00") @[Edges.scala 638:15] + node _T_1070 = bits(_T_585, 2, 0) @[Edges.scala 172:47] + _T_1059.addr_lo <= _T_1070 @[Edges.scala 639:15] + _T_1059.data <= UInt<1>("h00") @[Edges.scala 640:15] + _T_1059.error <= _T_1045 @[Edges.scala 641:15] + wire _T_1081 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_1081 is invalid @[Edges.scala 617:17] + _T_1081.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_1081.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_1081.size <= _T_589 @[Edges.scala 620:15] + _T_1081.source <= _T_588 @[Edges.scala 621:15] + _T_1081.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_1092 = bits(_T_590, 2, 0) @[Edges.scala 172:47] + _T_1081.addr_lo <= _T_1092 @[Edges.scala 623:15] + _T_1081.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_1081.error <= _T_1047 @[Edges.scala 625:15] + node _T_1094 = mux(_T_1039, _T_1059, _T_1081) @[ToAXI4.scala 216:23] + io.in.0.d.bits <- _T_1094 @[ToAXI4.scala 216:17] + io.in.0.d.bits.data <= io.out.0.r.bits.data @[ToAXI4.scala 217:22] + io.in.0.b.valid <= UInt<1>("h00") @[ToAXI4.scala 220:18] + io.in.0.c.ready <= UInt<1>("h01") @[ToAXI4.scala 221:18] + io.in.0.e.ready <= UInt<1>("h01") @[ToAXI4.scala 222:18] + + module TLMonitor_6 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 188:37] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 188:37] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_608 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:188:37)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 7, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + when _T_708 : @[Periphery.scala 188:37] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[Periphery.scala 188:37] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_725 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_726 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_728 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_731 = or(_T_730, reset) @[Periphery.scala 188:37] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_733 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_734 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_736 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[Periphery.scala 188:37] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_741 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:188:37)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_742 = not(io.in[0].a.bits.mask) @[Periphery.scala 188:37] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_745 = or(_T_744, reset) @[Periphery.scala 188:37] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_747 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 188:37] + when _T_749 : @[Periphery.scala 188:37] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[Periphery.scala 188:37] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_770 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_771 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_773 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_774 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_776 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_779 = or(_T_778, reset) @[Periphery.scala 188:37] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_781 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 188:37] + node _T_783 = or(_T_782, reset) @[Periphery.scala 188:37] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_785 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_787 : @[Periphery.scala 188:37] + node _T_790 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_792 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_793 = and(_T_790, _T_792) @[Parameters.scala 63:37] + node _T_794 = or(UInt<1>("h00"), _T_793) @[Parameters.scala 132:31] + node _T_796 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_797 = cvt(_T_796) @[Parameters.scala 117:49] + node _T_799 = and(_T_797, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_800 = asSInt(_T_799) @[Parameters.scala 117:52] + node _T_802 = eq(_T_800, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = and(_T_794, _T_802) @[Parameters.scala 132:56] + node _T_805 = or(UInt<1>("h00"), _T_803) @[Parameters.scala 134:30] + node _T_806 = or(_T_805, reset) @[Periphery.scala 188:37] + node _T_808 = eq(_T_806, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_808 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_809 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_811 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_812 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_814 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_816 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_817 = or(_T_816, reset) @[Periphery.scala 188:37] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_819 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_820 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 188:37] + node _T_821 = or(_T_820, reset) @[Periphery.scala 188:37] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_823 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_825 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 188:37] + when _T_825 : @[Periphery.scala 188:37] + node _T_828 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_830 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_831 = and(_T_828, _T_830) @[Parameters.scala 63:37] + node _T_832 = or(UInt<1>("h00"), _T_831) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_841) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, reset) @[Periphery.scala 188:37] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_846 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_847 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_849 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_850 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_852 = eq(_T_850, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_852 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_854 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_855 = or(_T_854, reset) @[Periphery.scala 188:37] + node _T_857 = eq(_T_855, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_857 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_858 = not(_T_706) @[Periphery.scala 188:37] + node _T_859 = and(io.in[0].a.bits.mask, _T_858) @[Periphery.scala 188:37] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_862 = or(_T_861, reset) @[Periphery.scala 188:37] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_864 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_866 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 188:37] + when _T_866 : @[Periphery.scala 188:37] + node _T_869 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_871 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_872 = cvt(_T_871) @[Parameters.scala 117:49] + node _T_874 = and(_T_872, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_875 = asSInt(_T_874) @[Parameters.scala 117:52] + node _T_877 = eq(_T_875, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = and(_T_869, _T_877) @[Parameters.scala 132:56] + node _T_880 = or(UInt<1>("h00"), _T_878) @[Parameters.scala 134:30] + node _T_881 = or(_T_880, reset) @[Periphery.scala 188:37] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_883 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_884 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_886 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_887 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_889 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_891 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_892 = or(_T_891, reset) @[Periphery.scala 188:37] + node _T_894 = eq(_T_892, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_894 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:188:37)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_895 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 188:37] + node _T_896 = or(_T_895, reset) @[Periphery.scala 188:37] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_898 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_900 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 188:37] + when _T_900 : @[Periphery.scala 188:37] + node _T_903 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_905 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_906 = cvt(_T_905) @[Parameters.scala 117:49] + node _T_908 = and(_T_906, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_909 = asSInt(_T_908) @[Parameters.scala 117:52] + node _T_911 = eq(_T_909, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = and(_T_903, _T_911) @[Parameters.scala 132:56] + node _T_914 = or(UInt<1>("h00"), _T_912) @[Parameters.scala 134:30] + node _T_915 = or(_T_914, reset) @[Periphery.scala 188:37] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_917 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_918 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_920 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_921 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_923 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_925 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_926 = or(_T_925, reset) @[Periphery.scala 188:37] + node _T_928 = eq(_T_926, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_928 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:188:37)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_929 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 188:37] + node _T_930 = or(_T_929, reset) @[Periphery.scala 188:37] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_932 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 188:37] + when _T_934 : @[Periphery.scala 188:37] + node _T_937 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_939 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_940 = cvt(_T_939) @[Parameters.scala 117:49] + node _T_942 = and(_T_940, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_943 = asSInt(_T_942) @[Parameters.scala 117:52] + node _T_945 = eq(_T_943, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_946 = and(_T_937, _T_945) @[Parameters.scala 132:56] + node _T_948 = or(UInt<1>("h00"), _T_946) @[Parameters.scala 134:30] + node _T_949 = or(_T_948, reset) @[Periphery.scala 188:37] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_951 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_952 = or(_T_630, reset) @[Periphery.scala 188:37] + node _T_954 = eq(_T_952, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_954 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_955 = or(_T_638, reset) @[Periphery.scala 188:37] + node _T_957 = eq(_T_955, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_957 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_958 = eq(io.in[0].a.bits.mask, _T_706) @[Periphery.scala 188:37] + node _T_959 = or(_T_958, reset) @[Periphery.scala 188:37] + node _T_961 = eq(_T_959, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_961 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + when io.in[0].b.valid : @[Periphery.scala 188:37] + node _T_963 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_964 = or(_T_963, reset) @[Periphery.scala 188:37] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_966 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:188:37)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_968 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_977 : UInt<1>[1] @[Parameters.scala 110:36] + _T_977 is invalid @[Parameters.scala 110:36] + _T_977[0] <= _T_974 @[Parameters.scala 110:36] + node _T_982 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_983 = dshl(_T_982, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_984 = bits(_T_983, 7, 0) @[package.scala 19:76] + node _T_985 = not(_T_984) @[package.scala 19:40] + node _T_986 = and(io.in[0].b.bits.address, _T_985) @[Edges.scala 17:16] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_990 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_991 = dshl(UInt<1>("h01"), _T_990) @[OneHot.scala 49:12] + node _T_992 = bits(_T_991, 2, 0) @[OneHot.scala 49:37] + node _T_994 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_996 = bits(_T_992, 2, 2) @[package.scala 44:26] + node _T_997 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_999 = eq(_T_997, UInt<1>("h00")) @[package.scala 46:20] + node _T_1000 = and(UInt<1>("h01"), _T_999) @[package.scala 49:27] + node _T_1001 = and(_T_996, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_994, _T_1001) @[package.scala 50:29] + node _T_1003 = and(UInt<1>("h01"), _T_997) @[package.scala 49:27] + node _T_1004 = and(_T_996, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_994, _T_1004) @[package.scala 50:29] + node _T_1006 = bits(_T_992, 1, 1) @[package.scala 44:26] + node _T_1007 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1009 = eq(_T_1007, UInt<1>("h00")) @[package.scala 46:20] + node _T_1010 = and(_T_1000, _T_1009) @[package.scala 49:27] + node _T_1011 = and(_T_1006, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_1002, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_1000, _T_1007) @[package.scala 49:27] + node _T_1014 = and(_T_1006, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_1002, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_1003, _T_1009) @[package.scala 49:27] + node _T_1017 = and(_T_1006, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_1005, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1003, _T_1007) @[package.scala 49:27] + node _T_1020 = and(_T_1006, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1005, _T_1020) @[package.scala 50:29] + node _T_1022 = bits(_T_992, 0, 0) @[package.scala 44:26] + node _T_1023 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[package.scala 46:20] + node _T_1026 = and(_T_1010, _T_1025) @[package.scala 49:27] + node _T_1027 = and(_T_1022, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1012, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1010, _T_1023) @[package.scala 49:27] + node _T_1030 = and(_T_1022, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1012, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1013, _T_1025) @[package.scala 49:27] + node _T_1033 = and(_T_1022, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1015, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1013, _T_1023) @[package.scala 49:27] + node _T_1036 = and(_T_1022, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1015, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1016, _T_1025) @[package.scala 49:27] + node _T_1039 = and(_T_1022, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1018, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1016, _T_1023) @[package.scala 49:27] + node _T_1042 = and(_T_1022, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1018, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1019, _T_1025) @[package.scala 49:27] + node _T_1045 = and(_T_1022, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1021, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1019, _T_1023) @[package.scala 49:27] + node _T_1048 = and(_T_1022, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1021, _T_1048) @[package.scala 50:29] + node _T_1050 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1050) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1054 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1058 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + when _T_1058 : @[Periphery.scala 188:37] + node _T_1060 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1061 = not(_T_1060) @[Parameters.scala 37:9] + node _T_1063 = or(_T_1061, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1064 = not(_T_1063) @[Parameters.scala 37:7] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1068 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1070 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1073 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1073 is invalid @[Parameters.scala 228:27] + _T_1073[0] <= _T_1066 @[Parameters.scala 228:27] + _T_1073[1] <= _T_1068 @[Parameters.scala 228:27] + _T_1073[2] <= _T_1070 @[Parameters.scala 228:27] + node _T_1081 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1083 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1084 = and(_T_1081, _T_1083) @[Parameters.scala 63:37] + node _T_1087 = mux(_T_1073[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1089 = mux(_T_1073[1], _T_1084, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1073[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1093 = or(_T_1087, _T_1089) @[Mux.scala 19:72] + node _T_1094 = or(_T_1093, _T_1091) @[Mux.scala 19:72] + wire _T_1096 : UInt<1> @[Mux.scala 19:72] + _T_1096 is invalid @[Mux.scala 19:72] + _T_1096 <= _T_1094 @[Mux.scala 19:72] + node _T_1097 = or(_T_1096, reset) @[Periphery.scala 188:37] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1099 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1100 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1102 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1104 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1105 = or(_T_1104, reset) @[Periphery.scala 188:37] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1107 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1108 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1110 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1112 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1113 = or(_T_1112, reset) @[Periphery.scala 188:37] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1115 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:188:37)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1116 = not(io.in[0].b.bits.mask) @[Periphery.scala 188:37] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1119 = or(_T_1118, reset) @[Periphery.scala 188:37] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1121 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1123 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 188:37] + when _T_1123 : @[Periphery.scala 188:37] + node _T_1125 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1127 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1128 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1130 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1131 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1133 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1135 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1136 = or(_T_1135, reset) @[Periphery.scala 188:37] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1138 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1139 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 188:37] + node _T_1140 = or(_T_1139, reset) @[Periphery.scala 188:37] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1142 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1144 : @[Periphery.scala 188:37] + node _T_1146 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1148 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1149 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1151 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1152 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1154 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1156 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1157 = or(_T_1156, reset) @[Periphery.scala 188:37] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1159 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 188:37] + node _T_1161 = or(_T_1160, reset) @[Periphery.scala 188:37] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1163 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 188:37] + when _T_1165 : @[Periphery.scala 188:37] + node _T_1167 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1169 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1170 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1172 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1173 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1175 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1177 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1178 = or(_T_1177, reset) @[Periphery.scala 188:37] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1180 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1181 = not(_T_1056) @[Periphery.scala 188:37] + node _T_1182 = and(io.in[0].b.bits.mask, _T_1181) @[Periphery.scala 188:37] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1185 = or(_T_1184, reset) @[Periphery.scala 188:37] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1187 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 188:37] + when _T_1189 : @[Periphery.scala 188:37] + node _T_1191 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1193 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1194 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1196 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1197 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1199 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1202 = or(_T_1201, reset) @[Periphery.scala 188:37] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1204 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:188:37)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1205 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 188:37] + node _T_1206 = or(_T_1205, reset) @[Periphery.scala 188:37] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1208 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1210 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 188:37] + when _T_1210 : @[Periphery.scala 188:37] + node _T_1212 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1214 = eq(_T_1212, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1214 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1215 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1217 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1218 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1220 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1222 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1223 = or(_T_1222, reset) @[Periphery.scala 188:37] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1225 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:188:37)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1226 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 188:37] + node _T_1227 = or(_T_1226, reset) @[Periphery.scala 188:37] + node _T_1229 = eq(_T_1227, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1229 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1231 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 188:37] + when _T_1231 : @[Periphery.scala 188:37] + node _T_1233 = or(UInt<1>("h00"), reset) @[Periphery.scala 188:37] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1235 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:188:37)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1236 = or(_T_977[0], reset) @[Periphery.scala 188:37] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1238 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1239 = or(_T_988, reset) @[Periphery.scala 188:37] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1241 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1242 = eq(io.in[0].b.bits.mask, _T_1056) @[Periphery.scala 188:37] + node _T_1243 = or(_T_1242, reset) @[Periphery.scala 188:37] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1245 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:188:37)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + when io.in[0].c.valid : @[Periphery.scala 188:37] + node _T_1247 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1248 = or(_T_1247, reset) @[Periphery.scala 188:37] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1250 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:188:37)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1252 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1253 = not(_T_1252) @[Parameters.scala 37:9] + node _T_1255 = or(_T_1253, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1256 = not(_T_1255) @[Parameters.scala 37:7] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1260 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1262 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1265 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1265 is invalid @[Parameters.scala 228:27] + _T_1265[0] <= _T_1258 @[Parameters.scala 228:27] + _T_1265[1] <= _T_1260 @[Parameters.scala 228:27] + _T_1265[2] <= _T_1262 @[Parameters.scala 228:27] + node _T_1271 = or(_T_1265[0], _T_1265[1]) @[Parameters.scala 229:46] + node _T_1272 = or(_T_1271, _T_1265[2]) @[Parameters.scala 229:46] + node _T_1274 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1275 = dshl(_T_1274, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1276 = bits(_T_1275, 7, 0) @[package.scala 19:76] + node _T_1277 = not(_T_1276) @[package.scala 19:40] + node _T_1278 = and(io.in[0].c.bits.address, _T_1277) @[Edges.scala 17:16] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1282 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1283 = cvt(_T_1282) @[Parameters.scala 117:49] + node _T_1285 = and(_T_1283, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1286 = asSInt(_T_1285) @[Parameters.scala 117:52] + node _T_1288 = eq(_T_1286, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1291 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1291 is invalid @[Parameters.scala 110:36] + _T_1291[0] <= _T_1288 @[Parameters.scala 110:36] + node _T_1296 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 188:37] + when _T_1296 : @[Periphery.scala 188:37] + node _T_1297 = or(_T_1291[0], reset) @[Periphery.scala 188:37] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1299 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1300 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1302 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1304 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1305 = or(_T_1304, reset) @[Periphery.scala 188:37] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1307 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1308 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1310 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1312 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1313 = or(_T_1312, reset) @[Periphery.scala 188:37] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1315 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:188:37)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1317 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1318 = or(_T_1317, reset) @[Periphery.scala 188:37] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1320 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1322 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 188:37] + when _T_1322 : @[Periphery.scala 188:37] + node _T_1323 = or(_T_1291[0], reset) @[Periphery.scala 188:37] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1325 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1326 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1328 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1330 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 188:37] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1333 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1334 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1336 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1338 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1339 = or(_T_1338, reset) @[Periphery.scala 188:37] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1341 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:188:37)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1343 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1344 = or(_T_1343, reset) @[Periphery.scala 188:37] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1346 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1348 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + when _T_1348 : @[Periphery.scala 188:37] + node _T_1351 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1353 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1354 = cvt(_T_1353) @[Parameters.scala 117:49] + node _T_1356 = and(_T_1354, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1357 = asSInt(_T_1356) @[Parameters.scala 117:52] + node _T_1359 = eq(_T_1357, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1360 = and(_T_1351, _T_1359) @[Parameters.scala 132:56] + node _T_1362 = or(UInt<1>("h00"), _T_1360) @[Parameters.scala 134:30] + node _T_1363 = or(_T_1362, reset) @[Periphery.scala 188:37] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1365 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1366 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1368 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1370 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1371 = or(_T_1370, reset) @[Periphery.scala 188:37] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1373 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1374 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1376 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1378 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1379 = or(_T_1378, reset) @[Periphery.scala 188:37] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1381 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:188:37)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1383 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1384 = or(_T_1383, reset) @[Periphery.scala 188:37] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1386 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 188:37] + when _T_1388 : @[Periphery.scala 188:37] + node _T_1391 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1393 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + node _T_1403 = or(_T_1402, reset) @[Periphery.scala 188:37] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1405 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:188:37)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1406 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1408 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1410 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1411 = or(_T_1410, reset) @[Periphery.scala 188:37] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1413 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1414 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1416 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1418 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1419 = or(_T_1418, reset) @[Periphery.scala 188:37] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1421 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:188:37)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1424 = or(_T_1423, reset) @[Periphery.scala 188:37] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1426 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1428 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1428 : @[Periphery.scala 188:37] + node _T_1429 = or(_T_1291[0], reset) @[Periphery.scala 188:37] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1431 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1432 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1434 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1435 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1437 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1439 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1440 = or(_T_1439, reset) @[Periphery.scala 188:37] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1442 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1444 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 188:37] + when _T_1444 : @[Periphery.scala 188:37] + node _T_1445 = or(_T_1291[0], reset) @[Periphery.scala 188:37] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1447 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1448 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1450 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1451 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1453 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1455 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1456 = or(_T_1455, reset) @[Periphery.scala 188:37] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1458 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1460 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 188:37] + when _T_1460 : @[Periphery.scala 188:37] + node _T_1461 = or(_T_1291[0], reset) @[Periphery.scala 188:37] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1463 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:188:37)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1464 = or(_T_1272, reset) @[Periphery.scala 188:37] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1466 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1467 = or(_T_1280, reset) @[Periphery.scala 188:37] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1469 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1471 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1472 = or(_T_1471, reset) @[Periphery.scala 188:37] + node _T_1474 = eq(_T_1472, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1474 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1476 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1477 = or(_T_1476, reset) @[Periphery.scala 188:37] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1479 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + when io.in[0].d.valid : @[Periphery.scala 188:37] + node _T_1481 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1482 = or(_T_1481, reset) @[Periphery.scala 188:37] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1484 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:188:37)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1486 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1487 = not(_T_1486) @[Parameters.scala 37:9] + node _T_1489 = or(_T_1487, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1490 = not(_T_1489) @[Parameters.scala 37:7] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1494 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1496 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1499 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1499 is invalid @[Parameters.scala 228:27] + _T_1499[0] <= _T_1492 @[Parameters.scala 228:27] + _T_1499[1] <= _T_1494 @[Parameters.scala 228:27] + _T_1499[2] <= _T_1496 @[Parameters.scala 228:27] + node _T_1505 = or(_T_1499[0], _T_1499[1]) @[Parameters.scala 229:46] + node _T_1506 = or(_T_1505, _T_1499[2]) @[Parameters.scala 229:46] + node _T_1508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1509 = dshl(_T_1508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1510 = bits(_T_1509, 7, 0) @[package.scala 19:76] + node _T_1511 = not(_T_1510) @[package.scala 19:40] + node _T_1512 = and(io.in[0].d.bits.addr_lo, _T_1511) @[Edges.scala 17:16] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1516 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 188:37] + node _T_1518 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + when _T_1518 : @[Periphery.scala 188:37] + node _T_1519 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1521 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1522 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1524 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1525 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1527 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1529 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1530 = or(_T_1529, reset) @[Periphery.scala 188:37] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1532 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1534 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1535 = or(_T_1534, reset) @[Periphery.scala 188:37] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1537 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1539 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1540 = or(_T_1539, reset) @[Periphery.scala 188:37] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1542 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1544 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 188:37] + when _T_1544 : @[Periphery.scala 188:37] + node _T_1545 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1547 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1548 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1550 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1551 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1553 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1555 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1556 = or(_T_1555, reset) @[Periphery.scala 188:37] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1558 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1560 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1561 = or(_T_1560, reset) @[Periphery.scala 188:37] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1563 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:188:37)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1565 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 188:37] + when _T_1565 : @[Periphery.scala 188:37] + node _T_1566 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1568 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1569 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1571 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1572 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1574 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1576 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 188:37] + node _T_1577 = or(_T_1576, reset) @[Periphery.scala 188:37] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1579 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:188:37)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1581 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1582 = or(_T_1581, reset) @[Periphery.scala 188:37] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1584 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:188:37)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1586 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1586 : @[Periphery.scala 188:37] + node _T_1587 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1589 = eq(_T_1587, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1589 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1590 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1592 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1593 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1595 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1597 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1598 = or(_T_1597, reset) @[Periphery.scala 188:37] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1600 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1602 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 188:37] + when _T_1602 : @[Periphery.scala 188:37] + node _T_1603 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1605 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1606 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1608 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1609 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1611 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1613 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1614 = or(_T_1613, reset) @[Periphery.scala 188:37] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1616 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1618 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 188:37] + when _T_1618 : @[Periphery.scala 188:37] + node _T_1619 = or(_T_1506, reset) @[Periphery.scala 188:37] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1621 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1622 = or(_T_1514, reset) @[Periphery.scala 188:37] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1624 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:188:37)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1625 = or(_T_1516, reset) @[Periphery.scala 188:37] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1627 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1629 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1630 = or(_T_1629, reset) @[Periphery.scala 188:37] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1632 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:188:37)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1634 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1635 = or(_T_1634, reset) @[Periphery.scala 188:37] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1637 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:188:37)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + when io.in[0].e.valid : @[Periphery.scala 188:37] + node _T_1639 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 188:37] + node _T_1640 = or(_T_1639, reset) @[Periphery.scala 188:37] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1642 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:188:37)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1643 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1646 = dshl(_T_1645, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1647 = bits(_T_1646, 7, 0) @[package.scala 19:76] + node _T_1648 = not(_T_1647) @[package.scala 19:40] + node _T_1649 = shr(_T_1648, 3) @[Edges.scala 198:59] + node _T_1650 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1654 = mux(_T_1652, _T_1649, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1656 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1658 = sub(_T_1656, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1659 = asUInt(_T_1658) @[Edges.scala 208:28] + node _T_1660 = tail(_T_1659, 1) @[Edges.scala 208:28] + node _T_1662 = eq(_T_1656, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1664 = eq(_T_1656, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1666 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1667 = or(_T_1664, _T_1666) @[Edges.scala 210:37] + node _T_1668 = and(_T_1667, _T_1643) @[Edges.scala 211:22] + node _T_1669 = not(_T_1660) @[Edges.scala 212:27] + node _T_1670 = and(_T_1654, _T_1669) @[Edges.scala 212:25] + when _T_1643 : @[Edges.scala 213:17] + node _T_1671 = mux(_T_1662, _T_1654, _T_1660) @[Edges.scala 214:21] + _T_1656 <= _T_1671 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1673 : UInt, clock @[Periphery.scala 188:37] + reg _T_1675 : UInt, clock @[Periphery.scala 188:37] + reg _T_1677 : UInt, clock @[Periphery.scala 188:37] + reg _T_1679 : UInt, clock @[Periphery.scala 188:37] + reg _T_1681 : UInt, clock @[Periphery.scala 188:37] + node _T_1683 = eq(_T_1662, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1684 = and(io.in[0].a.valid, _T_1683) @[Periphery.scala 188:37] + when _T_1684 : @[Periphery.scala 188:37] + node _T_1685 = eq(io.in[0].a.bits.opcode, _T_1673) @[Periphery.scala 188:37] + node _T_1686 = or(_T_1685, reset) @[Periphery.scala 188:37] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1688 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1689 = eq(io.in[0].a.bits.param, _T_1675) @[Periphery.scala 188:37] + node _T_1690 = or(_T_1689, reset) @[Periphery.scala 188:37] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1692 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1693 = eq(io.in[0].a.bits.size, _T_1677) @[Periphery.scala 188:37] + node _T_1694 = or(_T_1693, reset) @[Periphery.scala 188:37] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1696 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1697 = eq(io.in[0].a.bits.source, _T_1679) @[Periphery.scala 188:37] + node _T_1698 = or(_T_1697, reset) @[Periphery.scala 188:37] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1700 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1701 = eq(io.in[0].a.bits.address, _T_1681) @[Periphery.scala 188:37] + node _T_1702 = or(_T_1701, reset) @[Periphery.scala 188:37] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1704 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1705 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1706 = and(_T_1705, _T_1662) @[Periphery.scala 188:37] + when _T_1706 : @[Periphery.scala 188:37] + _T_1673 <= io.in[0].a.bits.opcode @[Periphery.scala 188:37] + _T_1675 <= io.in[0].a.bits.param @[Periphery.scala 188:37] + _T_1677 <= io.in[0].a.bits.size @[Periphery.scala 188:37] + _T_1679 <= io.in[0].a.bits.source @[Periphery.scala 188:37] + _T_1681 <= io.in[0].a.bits.address @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1707 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 7, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1719 = mux(UInt<1>("h00"), _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1721 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1723 = sub(_T_1721, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1724 = asUInt(_T_1723) @[Edges.scala 208:28] + node _T_1725 = tail(_T_1724, 1) @[Edges.scala 208:28] + node _T_1727 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1729 = eq(_T_1721, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1731 = eq(_T_1719, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1732 = or(_T_1729, _T_1731) @[Edges.scala 210:37] + node _T_1733 = and(_T_1732, _T_1707) @[Edges.scala 211:22] + node _T_1734 = not(_T_1725) @[Edges.scala 212:27] + node _T_1735 = and(_T_1719, _T_1734) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1736 = mux(_T_1727, _T_1719, _T_1725) @[Edges.scala 214:21] + _T_1721 <= _T_1736 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1738 : UInt, clock @[Periphery.scala 188:37] + reg _T_1740 : UInt, clock @[Periphery.scala 188:37] + reg _T_1742 : UInt, clock @[Periphery.scala 188:37] + reg _T_1744 : UInt, clock @[Periphery.scala 188:37] + reg _T_1746 : UInt, clock @[Periphery.scala 188:37] + node _T_1748 = eq(_T_1727, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1749 = and(io.in[0].b.valid, _T_1748) @[Periphery.scala 188:37] + when _T_1749 : @[Periphery.scala 188:37] + node _T_1750 = eq(io.in[0].b.bits.opcode, _T_1738) @[Periphery.scala 188:37] + node _T_1751 = or(_T_1750, reset) @[Periphery.scala 188:37] + node _T_1753 = eq(_T_1751, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1753 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1754 = eq(io.in[0].b.bits.param, _T_1740) @[Periphery.scala 188:37] + node _T_1755 = or(_T_1754, reset) @[Periphery.scala 188:37] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1757 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1758 = eq(io.in[0].b.bits.size, _T_1742) @[Periphery.scala 188:37] + node _T_1759 = or(_T_1758, reset) @[Periphery.scala 188:37] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1761 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1762 = eq(io.in[0].b.bits.source, _T_1744) @[Periphery.scala 188:37] + node _T_1763 = or(_T_1762, reset) @[Periphery.scala 188:37] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1765 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1766 = eq(io.in[0].b.bits.address, _T_1746) @[Periphery.scala 188:37] + node _T_1767 = or(_T_1766, reset) @[Periphery.scala 188:37] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1769 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1770 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1771 = and(_T_1770, _T_1727) @[Periphery.scala 188:37] + when _T_1771 : @[Periphery.scala 188:37] + _T_1738 <= io.in[0].b.bits.opcode @[Periphery.scala 188:37] + _T_1740 <= io.in[0].b.bits.param @[Periphery.scala 188:37] + _T_1742 <= io.in[0].b.bits.size @[Periphery.scala 188:37] + _T_1744 <= io.in[0].b.bits.source @[Periphery.scala 188:37] + _T_1746 <= io.in[0].b.bits.address @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1774 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1775 = dshl(_T_1774, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1776 = bits(_T_1775, 7, 0) @[package.scala 19:76] + node _T_1777 = not(_T_1776) @[package.scala 19:40] + node _T_1778 = shr(_T_1777, 3) @[Edges.scala 198:59] + node _T_1779 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1781 = mux(_T_1779, _T_1778, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1783 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1785 = sub(_T_1783, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1786 = asUInt(_T_1785) @[Edges.scala 208:28] + node _T_1787 = tail(_T_1786, 1) @[Edges.scala 208:28] + node _T_1789 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1791 = eq(_T_1783, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1793 = eq(_T_1781, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1794 = or(_T_1791, _T_1793) @[Edges.scala 210:37] + node _T_1795 = and(_T_1794, _T_1772) @[Edges.scala 211:22] + node _T_1796 = not(_T_1787) @[Edges.scala 212:27] + node _T_1797 = and(_T_1781, _T_1796) @[Edges.scala 212:25] + when _T_1772 : @[Edges.scala 213:17] + node _T_1798 = mux(_T_1789, _T_1781, _T_1787) @[Edges.scala 214:21] + _T_1783 <= _T_1798 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1800 : UInt, clock @[Periphery.scala 188:37] + reg _T_1802 : UInt, clock @[Periphery.scala 188:37] + reg _T_1804 : UInt, clock @[Periphery.scala 188:37] + reg _T_1806 : UInt, clock @[Periphery.scala 188:37] + reg _T_1808 : UInt, clock @[Periphery.scala 188:37] + node _T_1810 = eq(_T_1789, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1811 = and(io.in[0].c.valid, _T_1810) @[Periphery.scala 188:37] + when _T_1811 : @[Periphery.scala 188:37] + node _T_1812 = eq(io.in[0].c.bits.opcode, _T_1800) @[Periphery.scala 188:37] + node _T_1813 = or(_T_1812, reset) @[Periphery.scala 188:37] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1815 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1816 = eq(io.in[0].c.bits.param, _T_1802) @[Periphery.scala 188:37] + node _T_1817 = or(_T_1816, reset) @[Periphery.scala 188:37] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1819 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1820 = eq(io.in[0].c.bits.size, _T_1804) @[Periphery.scala 188:37] + node _T_1821 = or(_T_1820, reset) @[Periphery.scala 188:37] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1823 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1824 = eq(io.in[0].c.bits.source, _T_1806) @[Periphery.scala 188:37] + node _T_1825 = or(_T_1824, reset) @[Periphery.scala 188:37] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1827 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1828 = eq(io.in[0].c.bits.address, _T_1808) @[Periphery.scala 188:37] + node _T_1829 = or(_T_1828, reset) @[Periphery.scala 188:37] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1831 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1832 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1833 = and(_T_1832, _T_1789) @[Periphery.scala 188:37] + when _T_1833 : @[Periphery.scala 188:37] + _T_1800 <= io.in[0].c.bits.opcode @[Periphery.scala 188:37] + _T_1802 <= io.in[0].c.bits.param @[Periphery.scala 188:37] + _T_1804 <= io.in[0].c.bits.size @[Periphery.scala 188:37] + _T_1806 <= io.in[0].c.bits.source @[Periphery.scala 188:37] + _T_1808 <= io.in[0].c.bits.address @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1834 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 7, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 3) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1843 = mux(_T_1841, _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1845 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1847 = sub(_T_1845, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1848 = asUInt(_T_1847) @[Edges.scala 208:28] + node _T_1849 = tail(_T_1848, 1) @[Edges.scala 208:28] + node _T_1851 = eq(_T_1845, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1853 = eq(_T_1845, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1855 = eq(_T_1843, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1856 = or(_T_1853, _T_1855) @[Edges.scala 210:37] + node _T_1857 = and(_T_1856, _T_1834) @[Edges.scala 211:22] + node _T_1858 = not(_T_1849) @[Edges.scala 212:27] + node _T_1859 = and(_T_1843, _T_1858) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1860 = mux(_T_1851, _T_1843, _T_1849) @[Edges.scala 214:21] + _T_1845 <= _T_1860 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1862 : UInt, clock @[Periphery.scala 188:37] + reg _T_1864 : UInt, clock @[Periphery.scala 188:37] + reg _T_1866 : UInt, clock @[Periphery.scala 188:37] + reg _T_1868 : UInt, clock @[Periphery.scala 188:37] + reg _T_1870 : UInt, clock @[Periphery.scala 188:37] + reg _T_1872 : UInt, clock @[Periphery.scala 188:37] + node _T_1874 = eq(_T_1851, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1875 = and(io.in[0].d.valid, _T_1874) @[Periphery.scala 188:37] + when _T_1875 : @[Periphery.scala 188:37] + node _T_1876 = eq(io.in[0].d.bits.opcode, _T_1862) @[Periphery.scala 188:37] + node _T_1877 = or(_T_1876, reset) @[Periphery.scala 188:37] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1879 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1880 = eq(io.in[0].d.bits.param, _T_1864) @[Periphery.scala 188:37] + node _T_1881 = or(_T_1880, reset) @[Periphery.scala 188:37] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1883 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1884 = eq(io.in[0].d.bits.size, _T_1866) @[Periphery.scala 188:37] + node _T_1885 = or(_T_1884, reset) @[Periphery.scala 188:37] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1887 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1888 = eq(io.in[0].d.bits.source, _T_1868) @[Periphery.scala 188:37] + node _T_1889 = or(_T_1888, reset) @[Periphery.scala 188:37] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1891 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1892 = eq(io.in[0].d.bits.sink, _T_1870) @[Periphery.scala 188:37] + node _T_1893 = or(_T_1892, reset) @[Periphery.scala 188:37] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1895 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1896 = eq(io.in[0].d.bits.addr_lo, _T_1872) @[Periphery.scala 188:37] + node _T_1897 = or(_T_1896, reset) @[Periphery.scala 188:37] + node _T_1899 = eq(_T_1897, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1899 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:188:37)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1900 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = and(_T_1900, _T_1851) @[Periphery.scala 188:37] + when _T_1901 : @[Periphery.scala 188:37] + _T_1862 <= io.in[0].d.bits.opcode @[Periphery.scala 188:37] + _T_1864 <= io.in[0].d.bits.param @[Periphery.scala 188:37] + _T_1866 <= io.in[0].d.bits.size @[Periphery.scala 188:37] + _T_1868 <= io.in[0].d.bits.source @[Periphery.scala 188:37] + _T_1870 <= io.in[0].d.bits.sink @[Periphery.scala 188:37] + _T_1872 <= io.in[0].d.bits.addr_lo @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + reg _T_1903 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1904 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1906 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1907 = dshl(_T_1906, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1908 = bits(_T_1907, 7, 0) @[package.scala 19:76] + node _T_1909 = not(_T_1908) @[package.scala 19:40] + node _T_1910 = shr(_T_1909, 3) @[Edges.scala 198:59] + node _T_1911 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1915 = mux(_T_1913, _T_1910, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1917 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1919 = sub(_T_1917, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1920 = asUInt(_T_1919) @[Edges.scala 208:28] + node _T_1921 = tail(_T_1920, 1) @[Edges.scala 208:28] + node _T_1923 = eq(_T_1917, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1925 = eq(_T_1917, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1927 = eq(_T_1915, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1928 = or(_T_1925, _T_1927) @[Edges.scala 210:37] + node _T_1929 = and(_T_1928, _T_1904) @[Edges.scala 211:22] + node _T_1930 = not(_T_1921) @[Edges.scala 212:27] + node _T_1931 = and(_T_1915, _T_1930) @[Edges.scala 212:25] + when _T_1904 : @[Edges.scala 213:17] + node _T_1932 = mux(_T_1923, _T_1915, _T_1921) @[Edges.scala 214:21] + _T_1917 <= _T_1932 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1933 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1935 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1936 = dshl(_T_1935, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1937 = bits(_T_1936, 7, 0) @[package.scala 19:76] + node _T_1938 = not(_T_1937) @[package.scala 19:40] + node _T_1939 = shr(_T_1938, 3) @[Edges.scala 198:59] + node _T_1940 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1942 = mux(_T_1940, _T_1939, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1944 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1946 = sub(_T_1944, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1947 = asUInt(_T_1946) @[Edges.scala 208:28] + node _T_1948 = tail(_T_1947, 1) @[Edges.scala 208:28] + node _T_1950 = eq(_T_1944, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1952 = eq(_T_1944, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1954 = eq(_T_1942, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1955 = or(_T_1952, _T_1954) @[Edges.scala 210:37] + node _T_1956 = and(_T_1955, _T_1933) @[Edges.scala 211:22] + node _T_1957 = not(_T_1948) @[Edges.scala 212:27] + node _T_1958 = and(_T_1942, _T_1957) @[Edges.scala 212:25] + when _T_1933 : @[Edges.scala 213:17] + node _T_1959 = mux(_T_1950, _T_1942, _T_1948) @[Edges.scala 214:21] + _T_1944 <= _T_1959 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1961 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + node _T_1962 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 188:37] + node _T_1963 = or(_T_1961, _T_1962) @[Periphery.scala 188:37] + node _T_1965 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1966 = or(_T_1963, _T_1965) @[Periphery.scala 188:37] + node _T_1968 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1969 = or(_T_1966, _T_1968) @[Periphery.scala 188:37] + node _T_1970 = or(_T_1969, reset) @[Periphery.scala 188:37] + node _T_1972 = eq(_T_1970, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1972 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:188:37)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + wire _T_1974 : UInt<6> + _T_1974 is invalid + _T_1974 <= UInt<6>("h00") + node _T_1975 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1975 : @[Periphery.scala 188:37] + when _T_1928 : @[Periphery.scala 188:37] + node _T_1977 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1974 <= _T_1977 @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1978 = dshr(_T_1903, io.in[0].a.bits.source) @[Periphery.scala 188:37] + node _T_1979 = bits(_T_1978, 0, 0) @[Periphery.scala 188:37] + node _T_1981 = eq(_T_1979, UInt<1>("h00")) @[Periphery.scala 188:37] + node _T_1982 = or(_T_1981, reset) @[Periphery.scala 188:37] + node _T_1984 = eq(_T_1982, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1984 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:188:37)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + wire _T_1986 : UInt<6> + _T_1986 is invalid + _T_1986 <= UInt<6>("h00") + node _T_1987 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1989 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 188:37] + node _T_1990 = and(_T_1987, _T_1989) @[Periphery.scala 188:37] + when _T_1990 : @[Periphery.scala 188:37] + when _T_1955 : @[Periphery.scala 188:37] + node _T_1992 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1986 <= _T_1992 @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1993 = or(_T_1974, _T_1903) @[Periphery.scala 188:37] + node _T_1994 = dshr(_T_1993, io.in[0].d.bits.source) @[Periphery.scala 188:37] + node _T_1995 = bits(_T_1994, 0, 0) @[Periphery.scala 188:37] + node _T_1996 = or(_T_1995, reset) @[Periphery.scala 188:37] + node _T_1998 = eq(_T_1996, UInt<1>("h00")) @[Periphery.scala 188:37] + when _T_1998 : @[Periphery.scala 188:37] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:188:37)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 188:37] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + skip @[Periphery.scala 188:37] + node _T_1999 = or(_T_1903, _T_1974) @[Periphery.scala 188:37] + node _T_2000 = not(_T_1986) @[Periphery.scala 188:37] + node _T_2001 = and(_T_1999, _T_2000) @[Periphery.scala 188:37] + _T_1903 <= _T_2001 @[Periphery.scala 188:37] + + module Queue_15 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_16 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_50 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_52 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_53 = and(_T_50, _T_52) @[Decoupled.scala 188:33] + node _T_54 = and(_T_50, maybe_full) @[Decoupled.scala 189:32] + node _T_55 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_55 + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_56 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_57 = ram[value], clock + _T_57 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_63 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_64 = tail(_T_63, 1) @[Counter.scala 26:22] + value <= _T_64 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_67 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_68 = tail(_T_67, 1) @[Counter.scala 26:22] + value_1 <= _T_68 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_69 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_69 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_71 = eq(_T_53, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_71 @[Decoupled.scala 204:16] + node _T_73 = eq(_T_54, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_73 @[Decoupled.scala 205:16] + infer mport _T_74 = ram[value_1], clock + io.deq.bits <- _T_74 @[Decoupled.scala 206:15] + node _T_78 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_79 = asUInt(_T_78) @[Decoupled.scala 221:40] + node _T_80 = tail(_T_79, 1) @[Decoupled.scala 221:40] + node _T_81 = and(maybe_full, _T_50) @[Decoupled.scala 223:32] + node _T_82 = cat(_T_81, _T_80) @[Cat.scala 30:58] + io.count <= _T_82 @[Decoupled.scala 223:14] + + module Queue_17 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module Queue_18 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_19 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_57 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_59 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_60 = and(_T_57, _T_59) @[Decoupled.scala 188:33] + node _T_61 = and(_T_57, maybe_full) @[Decoupled.scala 189:32] + node _T_62 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_62 + node _T_63 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_63 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_64 = ram[value], clock + _T_64 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_71 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_72 = tail(_T_71, 1) @[Counter.scala 26:22] + value <= _T_72 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_75 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_76 = tail(_T_75, 1) @[Counter.scala 26:22] + value_1 <= _T_76 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_77 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_77 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_79 = eq(_T_60, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_79 @[Decoupled.scala 204:16] + node _T_81 = eq(_T_61, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_81 @[Decoupled.scala 205:16] + infer mport _T_82 = ram[value_1], clock + io.deq.bits <- _T_82 @[Decoupled.scala 206:15] + node _T_87 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_88 = asUInt(_T_87) @[Decoupled.scala 221:40] + node _T_89 = tail(_T_88, 1) @[Decoupled.scala 221:40] + node _T_90 = and(maybe_full, _T_57) @[Decoupled.scala 223:32] + node _T_91 = cat(_T_90, _T_89) @[Cat.scala 30:58] + io.count <= _T_91 @[Decoupled.scala 223:14] + + module AXI4Buffer : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_15 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.aw <- Queue.io.deq @[Buffer.scala 31:26] + inst Queue_1 of Queue_16 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.w.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.w.bits @[Decoupled.scala 255:19] + io.in.0.w.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.w <- Queue_1.io.deq @[Buffer.scala 32:26] + inst Queue_2 of Queue_17 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.b <- Queue_2.io.deq @[Buffer.scala 33:26] + inst Queue_3 of Queue_18 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_3.io.deq @[Buffer.scala 34:26] + inst Queue_4 of Queue_19 @[Decoupled.scala 253:19] + Queue_4.io is invalid + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= io.out.0.r.valid @[Decoupled.scala 254:20] + Queue_4.io.enq.bits <- io.out.0.r.bits @[Decoupled.scala 255:19] + io.out.0.r.ready <= Queue_4.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.r <- Queue_4.io.deq @[Buffer.scala 35:26] + + module Queue_20 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] + + module Queue_21 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] + + module Queue_22 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] + + module Queue_23 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, resp : UInt<2>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_43 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_44 = and(_T_41, _T_43) @[Decoupled.scala 188:33] + node _T_45 = and(_T_41, maybe_full) @[Decoupled.scala 189:32] + node _T_46 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_46 + node _T_47 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_47 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_49 = ram[UInt<1>("h00")], clock + _T_49 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_54 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_54 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_56 = eq(_T_44, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_56 @[Decoupled.scala 204:16] + node _T_58 = eq(_T_45, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_58 @[Decoupled.scala 205:16] + infer mport _T_60 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_60 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_44 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_66 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_67 = asUInt(_T_66) @[Decoupled.scala 221:40] + node _T_68 = tail(_T_67, 1) @[Decoupled.scala 221:40] + node _T_69 = and(maybe_full, _T_41) @[Decoupled.scala 223:32] + node _T_70 = cat(_T_69, _T_68) @[Cat.scala 30:58] + io.count <= _T_70 @[Decoupled.scala 223:14] + + module AXI4FragmenterAXI4FragmenterSideband : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<6>} + + io is invalid + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<5>("h01f")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] + + module AXI4FragmenterAXI4FragmenterSideband_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<6>} + + io is invalid + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<5>("h01f")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] + + module AXI4Fragmenter : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_20 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + wire _T_484 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_484 is invalid @[Decoupled.scala 272:19] + _T_484.bits <- Queue.io.deq.bits @[Decoupled.scala 273:14] + _T_484.valid <= Queue.io.deq.valid @[Decoupled.scala 274:15] + Queue.io.deq.ready <= _T_484.ready @[Decoupled.scala 275:15] + wire _T_509 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_509 is invalid @[Fragmenter.scala 66:23] + reg _T_535 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_537 : UInt<32>, clock @[Fragmenter.scala 69:25] + reg _T_539 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_540 = mux(_T_535, _T_539, _T_484.bits.len) @[Fragmenter.scala 72:23] + node _T_541 = mux(_T_535, _T_537, _T_484.bits.addr) @[Fragmenter.scala 73:23] + node _T_542 = bits(_T_541, 2, 0) @[Fragmenter.scala 75:53] + node _T_543 = shr(_T_541, 3) @[Fragmenter.scala 76:23] + node _T_544 = bits(_T_543, 7, 0) @[Fragmenter.scala 77:27] + node _T_546 = xor(_T_541, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_547 = cvt(_T_546) @[Parameters.scala 117:49] + node _T_549 = and(_T_547, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_550 = asSInt(_T_549) @[Parameters.scala 117:52] + node _T_552 = eq(_T_550, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_554 = xor(_T_541, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_555 = cvt(_T_554) @[Parameters.scala 117:49] + node _T_557 = and(_T_555, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_558 = asSInt(_T_557) @[Parameters.scala 117:52] + node _T_560 = eq(_T_558, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_562 = xor(_T_541, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_563 = cvt(_T_562) @[Parameters.scala 117:49] + node _T_565 = and(_T_563, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_566 = asSInt(_T_565) @[Parameters.scala 117:52] + node _T_568 = eq(_T_566, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_570 = xor(_T_541, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_571 = cvt(_T_570) @[Parameters.scala 117:49] + node _T_573 = and(_T_571, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_574 = asSInt(_T_573) @[Parameters.scala 117:52] + node _T_576 = eq(_T_574, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_578 = xor(_T_541, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_579 = cvt(_T_578) @[Parameters.scala 117:49] + node _T_581 = and(_T_579, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_582 = asSInt(_T_581) @[Parameters.scala 117:52] + node _T_584 = eq(_T_582, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_586 = xor(_T_541, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_587 = cvt(_T_586) @[Parameters.scala 117:49] + node _T_589 = and(_T_587, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_590 = asSInt(_T_589) @[Parameters.scala 117:52] + node _T_592 = eq(_T_590, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_594 = xor(_T_541, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_595 = cvt(_T_594) @[Parameters.scala 117:49] + node _T_597 = and(_T_595, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_598 = asSInt(_T_597) @[Parameters.scala 117:52] + node _T_600 = eq(_T_598, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_603 : UInt<1>[7] @[Parameters.scala 50:36] + _T_603 is invalid @[Parameters.scala 50:36] + _T_603[0] <= _T_552 @[Parameters.scala 50:36] + _T_603[1] <= _T_560 @[Parameters.scala 50:36] + _T_603[2] <= _T_568 @[Parameters.scala 50:36] + _T_603[3] <= _T_576 @[Parameters.scala 50:36] + _T_603[4] <= _T_584 @[Parameters.scala 50:36] + _T_603[5] <= _T_592 @[Parameters.scala 50:36] + _T_603[6] <= _T_600 @[Parameters.scala 50:36] + node _T_621 = mux(_T_603[0], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_623 = mux(_T_603[1], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_625 = mux(_T_603[2], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_627 = mux(_T_603[3], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_629 = mux(_T_603[4], UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_631 = mux(_T_603[5], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_633 = mux(_T_603[6], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_635 = or(_T_621, _T_623) @[Mux.scala 19:72] + node _T_636 = or(_T_635, _T_625) @[Mux.scala 19:72] + node _T_637 = or(_T_636, _T_627) @[Mux.scala 19:72] + node _T_638 = or(_T_637, _T_629) @[Mux.scala 19:72] + node _T_639 = or(_T_638, _T_631) @[Mux.scala 19:72] + node _T_640 = or(_T_639, _T_633) @[Mux.scala 19:72] + wire _T_642 : UInt<5> @[Mux.scala 19:72] + _T_642 is invalid @[Mux.scala 19:72] + _T_642 <= _T_640 @[Mux.scala 19:72] + node _T_644 = shr(_T_540, 1) @[package.scala 32:45] + node _T_645 = or(_T_540, _T_644) @[package.scala 32:40] + node _T_646 = shr(_T_645, 2) @[package.scala 32:45] + node _T_647 = or(_T_645, _T_646) @[package.scala 32:40] + node _T_648 = shr(_T_647, 4) @[package.scala 32:45] + node _T_649 = or(_T_647, _T_648) @[package.scala 32:40] + node _T_650 = shr(_T_649, 1) @[Fragmenter.scala 89:37] + node _T_651 = not(_T_540) @[Fragmenter.scala 90:32] + node _T_652 = shl(_T_651, 1) @[package.scala 25:45] + node _T_653 = bits(_T_652, 7, 0) @[package.scala 25:50] + node _T_654 = or(_T_651, _T_653) @[package.scala 25:40] + node _T_655 = shl(_T_654, 2) @[package.scala 25:45] + node _T_656 = bits(_T_655, 7, 0) @[package.scala 25:50] + node _T_657 = or(_T_654, _T_656) @[package.scala 25:40] + node _T_658 = shl(_T_657, 4) @[package.scala 25:45] + node _T_659 = bits(_T_658, 7, 0) @[package.scala 25:50] + node _T_660 = or(_T_657, _T_659) @[package.scala 25:40] + node _T_661 = not(_T_660) @[Fragmenter.scala 90:24] + node _T_662 = or(_T_650, _T_661) @[Fragmenter.scala 91:32] + node _T_663 = shl(_T_544, 1) @[package.scala 25:45] + node _T_664 = bits(_T_663, 7, 0) @[package.scala 25:50] + node _T_665 = or(_T_544, _T_664) @[package.scala 25:40] + node _T_666 = shl(_T_665, 2) @[package.scala 25:45] + node _T_667 = bits(_T_666, 7, 0) @[package.scala 25:50] + node _T_668 = or(_T_665, _T_667) @[package.scala 25:40] + node _T_669 = shl(_T_668, 4) @[package.scala 25:45] + node _T_670 = bits(_T_669, 7, 0) @[package.scala 25:50] + node _T_671 = or(_T_668, _T_670) @[package.scala 25:40] + node _T_672 = not(_T_671) @[Fragmenter.scala 92:24] + node _T_673 = and(_T_662, _T_672) @[Fragmenter.scala 94:37] + node _T_674 = and(_T_673, _T_642) @[Fragmenter.scala 94:46] + node _T_676 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_678 = neq(_T_484.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_679 = or(_T_676, _T_678) @[Fragmenter.scala 99:25] + node _T_681 = mux(_T_679, UInt<1>("h00"), _T_674) @[Fragmenter.scala 102:25] + node _T_682 = shl(_T_681, 1) @[package.scala 17:29] + node _T_684 = or(_T_682, UInt<1>("h01")) @[package.scala 17:34] + node _T_686 = cat(UInt<1>("h00"), _T_681) @[Cat.scala 30:58] + node _T_687 = not(_T_686) @[package.scala 17:47] + node _T_688 = and(_T_684, _T_687) @[package.scala 17:45] + node _T_689 = dshl(_T_688, _T_484.bits.size) @[Fragmenter.scala 105:38] + node _T_690 = add(_T_541, _T_689) @[Fragmenter.scala 105:29] + node _T_691 = tail(_T_690, 1) @[Fragmenter.scala 105:29] + node _T_693 = cat(_T_484.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_694 = dshl(_T_693, _T_484.bits.size) @[Bundles.scala 28:21] + node _T_695 = shr(_T_694, 8) @[Bundles.scala 28:30] + wire _T_696 : UInt + _T_696 is invalid + _T_696 <= _T_691 + node _T_698 = eq(_T_484.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_698 : @[Fragmenter.scala 108:59] + node _T_699 = and(_T_691, _T_695) @[Fragmenter.scala 109:33] + node _T_700 = not(_T_484.bits.addr) @[Fragmenter.scala 109:49] + node _T_701 = or(_T_700, _T_695) @[Fragmenter.scala 109:62] + node _T_702 = not(_T_701) @[Fragmenter.scala 109:47] + node _T_703 = or(_T_699, _T_702) @[Fragmenter.scala 109:45] + _T_696 <= _T_703 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_705 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_705 : @[Fragmenter.scala 111:60] + _T_696 <= _T_484.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_706 = eq(_T_681, _T_540) @[Fragmenter.scala 115:27] + node _T_707 = and(_T_509.ready, _T_706) @[Fragmenter.scala 116:30] + _T_484.ready <= _T_707 @[Fragmenter.scala 116:17] + _T_509.valid <= _T_484.valid @[Fragmenter.scala 117:19] + _T_509.bits <- _T_484.bits @[Fragmenter.scala 119:18] + _T_509.bits.len <= _T_681 @[Fragmenter.scala 120:22] + node _T_708 = not(_T_541) @[Fragmenter.scala 127:28] + node _T_710 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_711 = dshl(_T_710, _T_484.bits.size) @[package.scala 19:71] + node _T_712 = bits(_T_711, 2, 0) @[package.scala 19:76] + node _T_713 = not(_T_712) @[package.scala 19:40] + node _T_714 = or(_T_708, _T_713) @[Fragmenter.scala 127:34] + node _T_715 = not(_T_714) @[Fragmenter.scala 127:26] + _T_509.bits.addr <= _T_715 @[Fragmenter.scala 127:23] + node _T_716 = and(_T_509.ready, _T_509.valid) @[Decoupled.scala 30:37] + when _T_716 : @[Fragmenter.scala 129:27] + node _T_718 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_535 <= _T_718 @[Fragmenter.scala 130:16] + _T_537 <= _T_696 @[Fragmenter.scala 131:18] + node _T_719 = sub(_T_540, _T_688) @[Fragmenter.scala 132:25] + node _T_720 = asUInt(_T_719) @[Fragmenter.scala 132:25] + node _T_721 = tail(_T_720, 1) @[Fragmenter.scala 132:25] + _T_539 <= _T_721 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + inst Queue_1 of Queue_21 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + wire _T_757 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_757 is invalid @[Decoupled.scala 272:19] + _T_757.bits <- Queue_1.io.deq.bits @[Decoupled.scala 273:14] + _T_757.valid <= Queue_1.io.deq.valid @[Decoupled.scala 274:15] + Queue_1.io.deq.ready <= _T_757.ready @[Decoupled.scala 275:15] + wire _T_782 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_782 is invalid @[Fragmenter.scala 66:23] + reg _T_808 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_810 : UInt<32>, clock @[Fragmenter.scala 69:25] + reg _T_812 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_813 = mux(_T_808, _T_812, _T_757.bits.len) @[Fragmenter.scala 72:23] + node _T_814 = mux(_T_808, _T_810, _T_757.bits.addr) @[Fragmenter.scala 73:23] + node _T_815 = bits(_T_814, 2, 0) @[Fragmenter.scala 75:53] + node _T_816 = shr(_T_814, 3) @[Fragmenter.scala 76:23] + node _T_817 = bits(_T_816, 7, 0) @[Fragmenter.scala 77:27] + node _T_819 = xor(_T_814, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_820 = cvt(_T_819) @[Parameters.scala 117:49] + node _T_822 = and(_T_820, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_823 = asSInt(_T_822) @[Parameters.scala 117:52] + node _T_825 = eq(_T_823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_827 = xor(_T_814, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_828 = cvt(_T_827) @[Parameters.scala 117:49] + node _T_830 = and(_T_828, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_831 = asSInt(_T_830) @[Parameters.scala 117:52] + node _T_833 = eq(_T_831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_835 = xor(_T_814, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_843 = xor(_T_814, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_844 = cvt(_T_843) @[Parameters.scala 117:49] + node _T_846 = and(_T_844, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_847 = asSInt(_T_846) @[Parameters.scala 117:52] + node _T_849 = eq(_T_847, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_851 = xor(_T_814, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_852 = cvt(_T_851) @[Parameters.scala 117:49] + node _T_854 = and(_T_852, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_855 = asSInt(_T_854) @[Parameters.scala 117:52] + node _T_857 = eq(_T_855, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_859 = xor(_T_814, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_860 = cvt(_T_859) @[Parameters.scala 117:49] + node _T_862 = and(_T_860, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_863 = asSInt(_T_862) @[Parameters.scala 117:52] + node _T_865 = eq(_T_863, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_867 = xor(_T_814, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_868 = cvt(_T_867) @[Parameters.scala 117:49] + node _T_870 = and(_T_868, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_871 = asSInt(_T_870) @[Parameters.scala 117:52] + node _T_873 = eq(_T_871, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_876 : UInt<1>[7] @[Parameters.scala 50:36] + _T_876 is invalid @[Parameters.scala 50:36] + _T_876[0] <= _T_825 @[Parameters.scala 50:36] + _T_876[1] <= _T_833 @[Parameters.scala 50:36] + _T_876[2] <= _T_841 @[Parameters.scala 50:36] + _T_876[3] <= _T_849 @[Parameters.scala 50:36] + _T_876[4] <= _T_857 @[Parameters.scala 50:36] + _T_876[5] <= _T_865 @[Parameters.scala 50:36] + _T_876[6] <= _T_873 @[Parameters.scala 50:36] + node _T_894 = mux(_T_876[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_896 = mux(_T_876[1], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_898 = mux(_T_876[2], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_900 = mux(_T_876[3], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_902 = mux(_T_876[4], UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_904 = mux(_T_876[5], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_906 = mux(_T_876[6], UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_908 = or(_T_894, _T_896) @[Mux.scala 19:72] + node _T_909 = or(_T_908, _T_898) @[Mux.scala 19:72] + node _T_910 = or(_T_909, _T_900) @[Mux.scala 19:72] + node _T_911 = or(_T_910, _T_902) @[Mux.scala 19:72] + node _T_912 = or(_T_911, _T_904) @[Mux.scala 19:72] + node _T_913 = or(_T_912, _T_906) @[Mux.scala 19:72] + wire _T_915 : UInt<5> @[Mux.scala 19:72] + _T_915 is invalid @[Mux.scala 19:72] + _T_915 <= _T_913 @[Mux.scala 19:72] + node _T_917 = shr(_T_813, 1) @[package.scala 32:45] + node _T_918 = or(_T_813, _T_917) @[package.scala 32:40] + node _T_919 = shr(_T_918, 2) @[package.scala 32:45] + node _T_920 = or(_T_918, _T_919) @[package.scala 32:40] + node _T_921 = shr(_T_920, 4) @[package.scala 32:45] + node _T_922 = or(_T_920, _T_921) @[package.scala 32:40] + node _T_923 = shr(_T_922, 1) @[Fragmenter.scala 89:37] + node _T_924 = not(_T_813) @[Fragmenter.scala 90:32] + node _T_925 = shl(_T_924, 1) @[package.scala 25:45] + node _T_926 = bits(_T_925, 7, 0) @[package.scala 25:50] + node _T_927 = or(_T_924, _T_926) @[package.scala 25:40] + node _T_928 = shl(_T_927, 2) @[package.scala 25:45] + node _T_929 = bits(_T_928, 7, 0) @[package.scala 25:50] + node _T_930 = or(_T_927, _T_929) @[package.scala 25:40] + node _T_931 = shl(_T_930, 4) @[package.scala 25:45] + node _T_932 = bits(_T_931, 7, 0) @[package.scala 25:50] + node _T_933 = or(_T_930, _T_932) @[package.scala 25:40] + node _T_934 = not(_T_933) @[Fragmenter.scala 90:24] + node _T_935 = or(_T_923, _T_934) @[Fragmenter.scala 91:32] + node _T_936 = shl(_T_817, 1) @[package.scala 25:45] + node _T_937 = bits(_T_936, 7, 0) @[package.scala 25:50] + node _T_938 = or(_T_817, _T_937) @[package.scala 25:40] + node _T_939 = shl(_T_938, 2) @[package.scala 25:45] + node _T_940 = bits(_T_939, 7, 0) @[package.scala 25:50] + node _T_941 = or(_T_938, _T_940) @[package.scala 25:40] + node _T_942 = shl(_T_941, 4) @[package.scala 25:45] + node _T_943 = bits(_T_942, 7, 0) @[package.scala 25:50] + node _T_944 = or(_T_941, _T_943) @[package.scala 25:40] + node _T_945 = not(_T_944) @[Fragmenter.scala 92:24] + node _T_946 = and(_T_935, _T_945) @[Fragmenter.scala 94:37] + node _T_947 = and(_T_946, _T_915) @[Fragmenter.scala 94:46] + node _T_949 = eq(_T_757.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_951 = neq(_T_757.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_952 = or(_T_949, _T_951) @[Fragmenter.scala 99:25] + node _T_954 = mux(_T_952, UInt<1>("h00"), _T_947) @[Fragmenter.scala 102:25] + node _T_955 = shl(_T_954, 1) @[package.scala 17:29] + node _T_957 = or(_T_955, UInt<1>("h01")) @[package.scala 17:34] + node _T_959 = cat(UInt<1>("h00"), _T_954) @[Cat.scala 30:58] + node _T_960 = not(_T_959) @[package.scala 17:47] + node _T_961 = and(_T_957, _T_960) @[package.scala 17:45] + node _T_962 = dshl(_T_961, _T_757.bits.size) @[Fragmenter.scala 105:38] + node _T_963 = add(_T_814, _T_962) @[Fragmenter.scala 105:29] + node _T_964 = tail(_T_963, 1) @[Fragmenter.scala 105:29] + node _T_966 = cat(_T_757.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_967 = dshl(_T_966, _T_757.bits.size) @[Bundles.scala 28:21] + node _T_968 = shr(_T_967, 8) @[Bundles.scala 28:30] + wire _T_969 : UInt + _T_969 is invalid + _T_969 <= _T_964 + node _T_971 = eq(_T_757.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_971 : @[Fragmenter.scala 108:59] + node _T_972 = and(_T_964, _T_968) @[Fragmenter.scala 109:33] + node _T_973 = not(_T_757.bits.addr) @[Fragmenter.scala 109:49] + node _T_974 = or(_T_973, _T_968) @[Fragmenter.scala 109:62] + node _T_975 = not(_T_974) @[Fragmenter.scala 109:47] + node _T_976 = or(_T_972, _T_975) @[Fragmenter.scala 109:45] + _T_969 <= _T_976 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_978 = eq(_T_757.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_978 : @[Fragmenter.scala 111:60] + _T_969 <= _T_757.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_979 = eq(_T_954, _T_813) @[Fragmenter.scala 115:27] + node _T_980 = and(_T_782.ready, _T_979) @[Fragmenter.scala 116:30] + _T_757.ready <= _T_980 @[Fragmenter.scala 116:17] + _T_782.valid <= _T_757.valid @[Fragmenter.scala 117:19] + _T_782.bits <- _T_757.bits @[Fragmenter.scala 119:18] + _T_782.bits.len <= _T_954 @[Fragmenter.scala 120:22] + node _T_981 = not(_T_814) @[Fragmenter.scala 127:28] + node _T_983 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_984 = dshl(_T_983, _T_757.bits.size) @[package.scala 19:71] + node _T_985 = bits(_T_984, 2, 0) @[package.scala 19:76] + node _T_986 = not(_T_985) @[package.scala 19:40] + node _T_987 = or(_T_981, _T_986) @[Fragmenter.scala 127:34] + node _T_988 = not(_T_987) @[Fragmenter.scala 127:26] + _T_782.bits.addr <= _T_988 @[Fragmenter.scala 127:23] + node _T_989 = and(_T_782.ready, _T_782.valid) @[Decoupled.scala 30:37] + when _T_989 : @[Fragmenter.scala 129:27] + node _T_991 = eq(_T_979, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_808 <= _T_991 @[Fragmenter.scala 130:16] + _T_810 <= _T_969 @[Fragmenter.scala 131:18] + node _T_992 = sub(_T_813, _T_961) @[Fragmenter.scala 132:25] + node _T_993 = asUInt(_T_992) @[Fragmenter.scala 132:25] + node _T_994 = tail(_T_993, 1) @[Fragmenter.scala 132:25] + _T_812 <= _T_994 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + wire _T_995 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 148:24] + _T_995 is invalid @[Fragmenter.scala 148:24] + wire _T_1020 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[Fragmenter.scala 151:23] + _T_1020 is invalid @[Fragmenter.scala 151:23] + wire _T_1035 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}} @[Fragmenter.scala 152:23] + _T_1035 is invalid @[Fragmenter.scala 152:23] + inst Queue_2 of Queue_22 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_995.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_995.bits @[Decoupled.scala 255:19] + _T_995.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_2.io.deq @[Fragmenter.scala 158:16] + _T_1020 <- io.out.0.r @[Fragmenter.scala 159:15] + inst Queue_3 of Queue_23 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + _T_1035 <- Queue_3.io.deq @[Fragmenter.scala 165:13] + inst AXI4FragmenterAXI4FragmenterSideband of AXI4FragmenterAXI4FragmenterSideband @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband.io is invalid + AXI4FragmenterAXI4FragmenterSideband.clock <= clock + AXI4FragmenterAXI4FragmenterSideband.reset <= reset + inst AXI4FragmenterAXI4FragmenterSideband_1 of AXI4FragmenterAXI4FragmenterSideband_1 @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband_1.io is invalid + AXI4FragmenterAXI4FragmenterSideband_1.clock <= clock + AXI4FragmenterAXI4FragmenterSideband_1.reset <= reset + node _T_1059 = and(_T_509.valid, AXI4FragmenterAXI4FragmenterSideband.io.enq.ready) @[Fragmenter.scala 177:35] + _T_995.valid <= _T_1059 @[Fragmenter.scala 177:20] + node _T_1060 = and(AXI4FragmenterAXI4FragmenterSideband.io.enq.ready, _T_995.ready) @[Fragmenter.scala 178:46] + _T_509.ready <= _T_1060 @[Fragmenter.scala 178:19] + node _T_1061 = and(_T_509.valid, _T_995.ready) @[Fragmenter.scala 179:46] + AXI4FragmenterAXI4FragmenterSideband.io.enq.valid <= _T_1061 @[Fragmenter.scala 179:31] + _T_995.bits <- _T_509.bits @[Fragmenter.scala 180:19] + AXI4FragmenterAXI4FragmenterSideband.io.enq.bits <= _T_706 @[Fragmenter.scala 181:30] + reg _T_1063 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + wire _T_1065 : UInt<1> @[Fragmenter.scala 185:30] + _T_1065 is invalid @[Fragmenter.scala 185:30] + wire _T_1067 : UInt<1> @[Fragmenter.scala 186:30] + _T_1067 is invalid @[Fragmenter.scala 186:30] + node _T_1068 = and(_T_1067, _T_1065) @[Fragmenter.scala 187:26] + when _T_1068 : @[Fragmenter.scala 187:43] + _T_1063 <= UInt<1>("h01") @[Fragmenter.scala 187:60] + skip @[Fragmenter.scala 187:43] + node _T_1070 = and(io.out.0.aw.ready, io.out.0.aw.valid) @[Decoupled.scala 30:37] + when _T_1070 : @[Fragmenter.scala 188:28] + _T_1063 <= UInt<1>("h00") @[Fragmenter.scala 188:45] + skip @[Fragmenter.scala 188:28] + node _T_1072 = and(_T_782.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready) @[Fragmenter.scala 191:35] + node _T_1073 = or(_T_1065, _T_1063) @[Fragmenter.scala 191:79] + node _T_1074 = and(_T_1072, _T_1073) @[Fragmenter.scala 191:62] + io.out.0.aw.valid <= _T_1074 @[Fragmenter.scala 191:20] + node _T_1075 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready, io.out.0.aw.ready) @[Fragmenter.scala 192:46] + node _T_1076 = or(_T_1065, _T_1063) @[Fragmenter.scala 192:79] + node _T_1077 = and(_T_1075, _T_1076) @[Fragmenter.scala 192:62] + _T_782.ready <= _T_1077 @[Fragmenter.scala 192:19] + node _T_1078 = and(_T_782.valid, io.out.0.aw.ready) @[Fragmenter.scala 193:46] + node _T_1079 = or(_T_1065, _T_1063) @[Fragmenter.scala 193:79] + node _T_1080 = and(_T_1078, _T_1079) @[Fragmenter.scala 193:62] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.valid <= _T_1080 @[Fragmenter.scala 193:31] + node _T_1082 = eq(_T_1063, UInt<1>("h00")) @[Fragmenter.scala 194:38] + node _T_1083 = and(_T_782.valid, _T_1082) @[Fragmenter.scala 194:35] + _T_1067 <= _T_1083 @[Fragmenter.scala 194:20] + io.out.0.aw.bits <- _T_782.bits @[Fragmenter.scala 195:19] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.bits <= _T_979 @[Fragmenter.scala 196:30] + reg _T_1085 : UInt<9>, clock with : (reset => (reset, UInt<9>("h00"))) @[Reg.scala 26:44] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[Fragmenter.scala 200:30] + node _T_1089 = mux(_T_1067, _T_961, UInt<1>("h00")) @[Fragmenter.scala 201:35] + node _T_1090 = mux(_T_1087, _T_1089, _T_1085) @[Fragmenter.scala 201:23] + node _T_1092 = eq(_T_1090, UInt<1>("h01")) @[Fragmenter.scala 202:27] + node _T_1093 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_1094 = sub(_T_1090, _T_1093) @[Fragmenter.scala 203:27] + node _T_1095 = asUInt(_T_1094) @[Fragmenter.scala 203:27] + node _T_1096 = tail(_T_1095, 1) @[Fragmenter.scala 203:27] + _T_1085 <= _T_1096 @[Fragmenter.scala 203:17] + node _T_1097 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[Fragmenter.scala 204:15] + node _T_1101 = neq(_T_1090, UInt<1>("h00")) @[Fragmenter.scala 204:39] + node _T_1102 = or(_T_1099, _T_1101) @[Fragmenter.scala 204:29] + node _T_1103 = or(_T_1102, reset) @[Fragmenter.scala 204:14] + node _T_1105 = eq(_T_1103, UInt<1>("h00")) @[Fragmenter.scala 204:14] + when _T_1105 : @[Fragmenter.scala 204:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:204 assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible\n") @[Fragmenter.scala 204:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 204:14] + skip @[Fragmenter.scala 204:14] + _T_1065 <= _T_1087 @[Fragmenter.scala 207:20] + node _T_1107 = eq(_T_1065, UInt<1>("h00")) @[Fragmenter.scala 208:37] + node _T_1108 = or(_T_1107, _T_1067) @[Fragmenter.scala 208:51] + node _T_1109 = and(io.in.0.w.valid, _T_1108) @[Fragmenter.scala 208:33] + io.out.0.w.valid <= _T_1109 @[Fragmenter.scala 208:19] + node _T_1111 = eq(_T_1065, UInt<1>("h00")) @[Fragmenter.scala 209:37] + node _T_1112 = or(_T_1111, _T_1067) @[Fragmenter.scala 209:51] + node _T_1113 = and(io.out.0.w.ready, _T_1112) @[Fragmenter.scala 209:33] + io.in.0.w.ready <= _T_1113 @[Fragmenter.scala 209:18] + io.out.0.w.bits <- io.in.0.w.bits @[Fragmenter.scala 210:18] + io.out.0.w.bits.last <= _T_1092 @[Fragmenter.scala 211:23] + node _T_1115 = eq(io.out.0.w.valid, UInt<1>("h00")) @[Fragmenter.scala 213:15] + node _T_1117 = eq(io.in.0.w.bits.last, UInt<1>("h00")) @[Fragmenter.scala 213:31] + node _T_1118 = or(_T_1115, _T_1117) @[Fragmenter.scala 213:28] + node _T_1119 = or(_T_1118, _T_1092) @[Fragmenter.scala 213:47] + node _T_1120 = or(_T_1119, reset) @[Fragmenter.scala 213:14] + node _T_1122 = eq(_T_1120, UInt<1>("h00")) @[Fragmenter.scala 213:14] + when _T_1122 : @[Fragmenter.scala 213:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:213 assert (!out_w.valid || !in_w.bits.last || w_last)\n") @[Fragmenter.scala 213:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 213:14] + skip @[Fragmenter.scala 213:14] + node _T_1124 = eq(_T_1020.bits.last, UInt<1>("h00")) @[Fragmenter.scala 217:37] + node _T_1125 = or(_T_1124, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 217:45] + node _T_1126 = and(_T_1020.valid, _T_1125) @[Fragmenter.scala 217:33] + io.in.0.r.valid <= _T_1126 @[Fragmenter.scala 217:18] + node _T_1128 = eq(_T_1020.bits.last, UInt<1>("h00")) @[Fragmenter.scala 218:37] + node _T_1129 = or(_T_1128, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 218:45] + node _T_1130 = and(io.in.0.r.ready, _T_1129) @[Fragmenter.scala 218:33] + _T_1020.ready <= _T_1130 @[Fragmenter.scala 218:19] + node _T_1131 = and(_T_1020.bits.last, _T_1020.valid) @[Fragmenter.scala 219:41] + node _T_1132 = and(_T_1131, io.in.0.r.ready) @[Fragmenter.scala 219:56] + AXI4FragmenterAXI4FragmenterSideband.io.deq.ready <= _T_1132 @[Fragmenter.scala 219:31] + io.in.0.r.bits <- _T_1020.bits @[Fragmenter.scala 220:17] + node _T_1133 = and(_T_1020.bits.last, AXI4FragmenterAXI4FragmenterSideband.io.deq.bits) @[Fragmenter.scala 221:32] + io.in.0.r.bits.last <= _T_1133 @[Fragmenter.scala 221:22] + node _T_1134 = and(_T_1035.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid) @[Fragmenter.scala 225:33] + node _T_1135 = and(_T_1134, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits) @[Fragmenter.scala 225:60] + io.in.0.b.valid <= _T_1135 @[Fragmenter.scala 225:18] + node _T_1137 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 226:50] + node _T_1138 = or(_T_1137, io.in.0.b.ready) @[Fragmenter.scala 226:58] + node _T_1139 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid, _T_1138) @[Fragmenter.scala 226:46] + _T_1035.ready <= _T_1139 @[Fragmenter.scala 226:19] + node _T_1141 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 227:50] + node _T_1142 = or(_T_1141, io.in.0.b.ready) @[Fragmenter.scala 227:58] + node _T_1143 = and(_T_1035.valid, _T_1142) @[Fragmenter.scala 227:46] + AXI4FragmenterAXI4FragmenterSideband_1.io.deq.ready <= _T_1143 @[Fragmenter.scala 227:31] + io.in.0.b.bits <- _T_1035.bits @[Fragmenter.scala 228:17] + reg _T_1145 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node _T_1146 = or(_T_1035.bits.resp, _T_1145) @[Fragmenter.scala 232:34] + node _T_1147 = and(_T_1035.ready, _T_1035.valid) @[Decoupled.scala 30:37] + when _T_1147 : @[Fragmenter.scala 233:27] + node _T_1149 = mux(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00"), _T_1146) @[Fragmenter.scala 233:42] + _T_1145 <= _T_1149 @[Fragmenter.scala 233:36] + skip @[Fragmenter.scala 233:27] + io.in.0.b.bits.resp <= _T_1146 @[Fragmenter.scala 234:22] + + module Queue_24 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module Queue_25 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : UInt<8>[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_29 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_31 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_32 = and(_T_29, _T_31) @[Decoupled.scala 188:33] + node _T_33 = and(_T_29, maybe_full) @[Decoupled.scala 189:32] + node _T_34 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_34 + node _T_35 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_35 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_36 = ram[value], clock + _T_36 <= io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_39 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_40 = tail(_T_39, 1) @[Counter.scala 26:22] + value <= _T_40 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_43 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_44 = tail(_T_43, 1) @[Counter.scala 26:22] + value_1 <= _T_44 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_45 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_45 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_47 = eq(_T_32, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_47 @[Decoupled.scala 204:16] + node _T_49 = eq(_T_33, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_49 @[Decoupled.scala 205:16] + infer mport _T_50 = ram[value_1], clock + io.deq.bits <= _T_50 @[Decoupled.scala 206:15] + node _T_51 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_52 = asUInt(_T_51) @[Decoupled.scala 221:40] + node _T_53 = tail(_T_52, 1) @[Decoupled.scala 221:40] + node _T_54 = and(maybe_full, _T_29) @[Decoupled.scala 223:32] + node _T_55 = cat(_T_54, _T_53) @[Cat.scala 30:58] + io.count <= _T_55 @[Decoupled.scala 223:14] + + module Queue_26 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_55 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_57 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_58 = and(_T_55, _T_57) @[Decoupled.scala 188:33] + node _T_59 = and(_T_55, maybe_full) @[Decoupled.scala 189:32] + node _T_60 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_60 + node _T_61 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_61 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_63 = ram[UInt<1>("h00")], clock + _T_63 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_70 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_70 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_72 = eq(_T_58, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_72 @[Decoupled.scala 204:16] + node _T_74 = eq(_T_59, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_74 @[Decoupled.scala 205:16] + infer mport _T_76 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_76 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_58 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_84 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_85 = asUInt(_T_84) @[Decoupled.scala 221:40] + node _T_86 = tail(_T_85, 1) @[Decoupled.scala 221:40] + node _T_87 = and(maybe_full, _T_55) @[Decoupled.scala 223:32] + node _T_88 = cat(_T_87, _T_86) @[Cat.scala 30:58] + io.count <= _T_88 @[Decoupled.scala 223:14] + + module Queue_27 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<8>, resp : UInt<2>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_43 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_44 = and(_T_41, _T_43) @[Decoupled.scala 188:33] + node _T_45 = and(_T_41, maybe_full) @[Decoupled.scala 189:32] + node _T_46 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_46 + node _T_47 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_47 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_49 = ram[UInt<1>("h00")], clock + _T_49 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_54 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_54 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_56 = eq(_T_44, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_56 @[Decoupled.scala 204:16] + node _T_58 = eq(_T_45, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_58 @[Decoupled.scala 205:16] + infer mport _T_60 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_60 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_44 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_66 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_67 = asUInt(_T_66) @[Decoupled.scala 221:40] + node _T_68 = tail(_T_67, 1) @[Decoupled.scala 221:40] + node _T_69 = and(maybe_full, _T_41) @[Decoupled.scala 223:32] + node _T_70 = cat(_T_69, _T_68) @[Cat.scala 30:58] + io.count <= _T_70 @[Decoupled.scala 223:14] + + module AXI4ToTL : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + wire _T_476 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[ToTL.scala 51:23] + _T_476 is invalid @[ToTL.scala 51:23] + reg _T_498 : UInt<256>, clock with : (reset => (reset, UInt<256>("h00"))) @[Reg.scala 26:44] + node _T_499 = dshr(_T_498, io.in.0.ar.bits.id) @[ToTL.scala 53:31] + node _T_500 = bits(_T_499, 0, 0) @[ToTL.scala 53:31] + node _T_502 = cat(io.in.0.ar.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_503 = dshl(_T_502, io.in.0.ar.bits.size) @[Bundles.scala 28:21] + node _T_504 = shr(_T_503, 8) @[Bundles.scala 28:30] + node _T_505 = shl(_T_504, 1) @[package.scala 17:29] + node _T_507 = or(_T_505, UInt<1>("h01")) @[package.scala 17:34] + node _T_509 = cat(UInt<1>("h00"), _T_504) @[Cat.scala 30:58] + node _T_510 = not(_T_509) @[package.scala 17:47] + node _T_511 = and(_T_507, _T_510) @[package.scala 17:45] + node _T_512 = bits(_T_511, 15, 8) @[OneHot.scala 26:18] + node _T_513 = bits(_T_511, 7, 0) @[OneHot.scala 27:18] + node _T_515 = neq(_T_512, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_516 = or(_T_512, _T_513) @[OneHot.scala 28:28] + node _T_517 = bits(_T_516, 7, 4) @[OneHot.scala 26:18] + node _T_518 = bits(_T_516, 3, 0) @[OneHot.scala 27:18] + node _T_520 = neq(_T_517, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_521 = or(_T_517, _T_518) @[OneHot.scala 28:28] + node _T_522 = bits(_T_521, 3, 2) @[OneHot.scala 26:18] + node _T_523 = bits(_T_521, 1, 0) @[OneHot.scala 27:18] + node _T_525 = neq(_T_522, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_526 = or(_T_522, _T_523) @[OneHot.scala 28:28] + node _T_527 = bits(_T_526, 1, 1) @[CircuitMath.scala 30:8] + node _T_528 = cat(_T_525, _T_527) @[Cat.scala 30:58] + node _T_529 = cat(_T_520, _T_528) @[Cat.scala 30:58] + node _T_530 = cat(_T_515, _T_529) @[Cat.scala 30:58] + node _T_533 = leq(UInt<1>("h00"), _T_530) @[Parameters.scala 63:32] + node _T_535 = leq(_T_530, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_536 = and(_T_533, _T_535) @[Parameters.scala 63:37] + node _T_537 = or(UInt<1>("h00"), _T_536) @[Parameters.scala 132:31] + node _T_539 = xor(io.in.0.ar.bits.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_540 = cvt(_T_539) @[Parameters.scala 117:49] + node _T_542 = and(_T_540, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_543 = asSInt(_T_542) @[Parameters.scala 117:52] + node _T_545 = eq(_T_543, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_547 = xor(io.in.0.ar.bits.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_548 = cvt(_T_547) @[Parameters.scala 117:49] + node _T_550 = and(_T_548, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_551 = asSInt(_T_550) @[Parameters.scala 117:52] + node _T_553 = eq(_T_551, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_555 = xor(io.in.0.ar.bits.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_556 = cvt(_T_555) @[Parameters.scala 117:49] + node _T_558 = and(_T_556, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_559 = asSInt(_T_558) @[Parameters.scala 117:52] + node _T_561 = eq(_T_559, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_563 = xor(io.in.0.ar.bits.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_564 = cvt(_T_563) @[Parameters.scala 117:49] + node _T_566 = and(_T_564, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_567 = asSInt(_T_566) @[Parameters.scala 117:52] + node _T_569 = eq(_T_567, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_571 = xor(io.in.0.ar.bits.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_572 = cvt(_T_571) @[Parameters.scala 117:49] + node _T_574 = and(_T_572, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_575 = asSInt(_T_574) @[Parameters.scala 117:52] + node _T_577 = eq(_T_575, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_578 = or(_T_545, _T_553) @[Parameters.scala 133:42] + node _T_579 = or(_T_578, _T_561) @[Parameters.scala 133:42] + node _T_580 = or(_T_579, _T_569) @[Parameters.scala 133:42] + node _T_581 = or(_T_580, _T_577) @[Parameters.scala 133:42] + node _T_582 = and(_T_537, _T_581) @[Parameters.scala 132:56] + node _T_585 = leq(UInt<1>("h00"), _T_530) @[Parameters.scala 63:32] + node _T_587 = leq(_T_530, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_588 = and(_T_585, _T_587) @[Parameters.scala 63:37] + node _T_589 = or(UInt<1>("h00"), _T_588) @[Parameters.scala 132:31] + node _T_591 = xor(io.in.0.ar.bits.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_592 = cvt(_T_591) @[Parameters.scala 117:49] + node _T_594 = and(_T_592, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_595 = asSInt(_T_594) @[Parameters.scala 117:52] + node _T_597 = eq(_T_595, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_598 = and(_T_589, _T_597) @[Parameters.scala 132:56] + node _T_600 = or(UInt<1>("h00"), _T_582) @[Parameters.scala 134:30] + node _T_601 = or(_T_600, _T_598) @[Parameters.scala 134:30] + wire _T_616 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, last : UInt<1>}} @[ToTL.scala 58:26] + _T_616 is invalid @[ToTL.scala 58:26] + inst Queue of Queue_24 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= _T_616.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- _T_616.bits @[Decoupled.scala 255:19] + _T_616.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + reg _T_631 : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[Reg.scala 26:44] + node _T_632 = eq(_T_631, io.in.0.ar.bits.len) @[ToTL.scala 61:28] + node _T_634 = eq(io.in.0.ar.valid, UInt<1>("h00")) @[ToTL.scala 63:15] + node _T_636 = asUInt(asSInt(UInt<15>("h07fff"))) @[package.scala 19:64] + node _T_637 = dshl(_T_636, _T_530) @[package.scala 19:71] + node _T_638 = bits(_T_637, 14, 0) @[package.scala 19:76] + node _T_639 = not(_T_638) @[package.scala 19:40] + node _T_640 = eq(_T_504, _T_639) @[ToTL.scala 63:39] + node _T_641 = or(_T_634, _T_640) @[ToTL.scala 63:28] + node _T_642 = or(_T_641, reset) @[ToTL.scala 63:14] + node _T_644 = eq(_T_642, UInt<1>("h00")) @[ToTL.scala 63:14] + when _T_644 : @[ToTL.scala 63:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToTL.scala:63 assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned\n") @[ToTL.scala 63:14] + stop(clock, UInt<1>(1), 1) @[ToTL.scala 63:14] + skip @[ToTL.scala 63:14] + node _T_645 = and(_T_616.ready, _T_632) @[ToTL.scala 64:60] + node _T_646 = mux(_T_601, _T_476.ready, _T_645) @[ToTL.scala 64:25] + node _T_648 = eq(_T_500, UInt<1>("h00")) @[ToTL.scala 64:74] + node _T_649 = and(_T_646, _T_648) @[ToTL.scala 64:71] + io.in.0.ar.ready <= _T_649 @[ToTL.scala 64:19] + node _T_651 = eq(_T_500, UInt<1>("h00")) @[ToTL.scala 65:37] + node _T_652 = and(io.in.0.ar.valid, _T_651) @[ToTL.scala 65:34] + node _T_653 = and(_T_652, _T_601) @[ToTL.scala 65:46] + _T_476.valid <= _T_653 @[ToTL.scala 65:19] + node _T_654 = shl(io.in.0.ar.bits.id, 1) @[ToTL.scala 66:47] + node _T_656 = or(_T_654, UInt<1>("h01")) @[ToTL.scala 66:52] + node _T_659 = leq(UInt<1>("h00"), _T_530) @[Parameters.scala 63:32] + node _T_661 = leq(_T_530, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_662 = and(_T_659, _T_661) @[Parameters.scala 63:37] + node _T_663 = or(UInt<1>("h00"), _T_662) @[Parameters.scala 132:31] + node _T_665 = xor(io.in.0.ar.bits.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_666 = cvt(_T_665) @[Parameters.scala 117:49] + node _T_668 = and(_T_666, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_669 = asSInt(_T_668) @[Parameters.scala 117:52] + node _T_671 = eq(_T_669, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_672 = and(_T_663, _T_671) @[Parameters.scala 132:56] + node _T_675 = leq(UInt<1>("h00"), _T_530) @[Parameters.scala 63:32] + node _T_677 = leq(_T_530, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_678 = and(_T_675, _T_677) @[Parameters.scala 63:37] + node _T_679 = or(UInt<1>("h00"), _T_678) @[Parameters.scala 132:31] + node _T_681 = xor(io.in.0.ar.bits.addr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_682 = cvt(_T_681) @[Parameters.scala 117:49] + node _T_684 = and(_T_682, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_685 = asSInt(_T_684) @[Parameters.scala 117:52] + node _T_687 = eq(_T_685, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = and(_T_679, _T_687) @[Parameters.scala 132:56] + node _T_690 = or(UInt<1>("h00"), _T_672) @[Parameters.scala 134:30] + node _T_691 = or(_T_690, _T_688) @[Parameters.scala 134:30] + wire _T_700 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 342:17] + _T_700 is invalid @[Edges.scala 342:17] + _T_700.opcode <= UInt<3>("h04") @[Edges.scala 343:15] + _T_700.param <= UInt<1>("h00") @[Edges.scala 344:15] + _T_700.size <= _T_530 @[Edges.scala 345:15] + _T_700.source <= _T_656 @[Edges.scala 346:15] + _T_700.address <= io.in.0.ar.bits.addr @[Edges.scala 347:15] + node _T_711 = bits(_T_530, 1, 0) @[OneHot.scala 49:17] + node _T_712 = dshl(UInt<1>("h01"), _T_711) @[OneHot.scala 49:12] + node _T_713 = bits(_T_712, 2, 0) @[OneHot.scala 49:37] + node _T_715 = geq(_T_530, UInt<2>("h03")) @[package.scala 41:21] + node _T_717 = bits(_T_713, 2, 2) @[package.scala 44:26] + node _T_718 = bits(io.in.0.ar.bits.addr, 2, 2) @[package.scala 45:26] + node _T_720 = eq(_T_718, UInt<1>("h00")) @[package.scala 46:20] + node _T_721 = and(UInt<1>("h01"), _T_720) @[package.scala 49:27] + node _T_722 = and(_T_717, _T_721) @[package.scala 50:38] + node _T_723 = or(_T_715, _T_722) @[package.scala 50:29] + node _T_724 = and(UInt<1>("h01"), _T_718) @[package.scala 49:27] + node _T_725 = and(_T_717, _T_724) @[package.scala 50:38] + node _T_726 = or(_T_715, _T_725) @[package.scala 50:29] + node _T_727 = bits(_T_713, 1, 1) @[package.scala 44:26] + node _T_728 = bits(io.in.0.ar.bits.addr, 1, 1) @[package.scala 45:26] + node _T_730 = eq(_T_728, UInt<1>("h00")) @[package.scala 46:20] + node _T_731 = and(_T_721, _T_730) @[package.scala 49:27] + node _T_732 = and(_T_727, _T_731) @[package.scala 50:38] + node _T_733 = or(_T_723, _T_732) @[package.scala 50:29] + node _T_734 = and(_T_721, _T_728) @[package.scala 49:27] + node _T_735 = and(_T_727, _T_734) @[package.scala 50:38] + node _T_736 = or(_T_723, _T_735) @[package.scala 50:29] + node _T_737 = and(_T_724, _T_730) @[package.scala 49:27] + node _T_738 = and(_T_727, _T_737) @[package.scala 50:38] + node _T_739 = or(_T_726, _T_738) @[package.scala 50:29] + node _T_740 = and(_T_724, _T_728) @[package.scala 49:27] + node _T_741 = and(_T_727, _T_740) @[package.scala 50:38] + node _T_742 = or(_T_726, _T_741) @[package.scala 50:29] + node _T_743 = bits(_T_713, 0, 0) @[package.scala 44:26] + node _T_744 = bits(io.in.0.ar.bits.addr, 0, 0) @[package.scala 45:26] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[package.scala 46:20] + node _T_747 = and(_T_731, _T_746) @[package.scala 49:27] + node _T_748 = and(_T_743, _T_747) @[package.scala 50:38] + node _T_749 = or(_T_733, _T_748) @[package.scala 50:29] + node _T_750 = and(_T_731, _T_744) @[package.scala 49:27] + node _T_751 = and(_T_743, _T_750) @[package.scala 50:38] + node _T_752 = or(_T_733, _T_751) @[package.scala 50:29] + node _T_753 = and(_T_734, _T_746) @[package.scala 49:27] + node _T_754 = and(_T_743, _T_753) @[package.scala 50:38] + node _T_755 = or(_T_736, _T_754) @[package.scala 50:29] + node _T_756 = and(_T_734, _T_744) @[package.scala 49:27] + node _T_757 = and(_T_743, _T_756) @[package.scala 50:38] + node _T_758 = or(_T_736, _T_757) @[package.scala 50:29] + node _T_759 = and(_T_737, _T_746) @[package.scala 49:27] + node _T_760 = and(_T_743, _T_759) @[package.scala 50:38] + node _T_761 = or(_T_739, _T_760) @[package.scala 50:29] + node _T_762 = and(_T_737, _T_744) @[package.scala 49:27] + node _T_763 = and(_T_743, _T_762) @[package.scala 50:38] + node _T_764 = or(_T_739, _T_763) @[package.scala 50:29] + node _T_765 = and(_T_740, _T_746) @[package.scala 49:27] + node _T_766 = and(_T_743, _T_765) @[package.scala 50:38] + node _T_767 = or(_T_742, _T_766) @[package.scala 50:29] + node _T_768 = and(_T_740, _T_744) @[package.scala 49:27] + node _T_769 = and(_T_743, _T_768) @[package.scala 50:38] + node _T_770 = or(_T_742, _T_769) @[package.scala 50:29] + node _T_771 = cat(_T_752, _T_749) @[Cat.scala 30:58] + node _T_772 = cat(_T_758, _T_755) @[Cat.scala 30:58] + node _T_773 = cat(_T_772, _T_771) @[Cat.scala 30:58] + node _T_774 = cat(_T_764, _T_761) @[Cat.scala 30:58] + node _T_775 = cat(_T_770, _T_767) @[Cat.scala 30:58] + node _T_776 = cat(_T_775, _T_774) @[Cat.scala 30:58] + node _T_777 = cat(_T_776, _T_773) @[Cat.scala 30:58] + _T_700.mask <= _T_777 @[Edges.scala 348:15] + _T_700.data <= UInt<1>("h00") @[Edges.scala 349:15] + _T_476.bits <- _T_700 @[ToTL.scala 66:18] + node _T_780 = eq(_T_500, UInt<1>("h00")) @[ToTL.scala 67:40] + node _T_781 = and(io.in.0.ar.valid, _T_780) @[ToTL.scala 67:37] + node _T_783 = eq(_T_601, UInt<1>("h00")) @[ToTL.scala 67:52] + node _T_784 = and(_T_781, _T_783) @[ToTL.scala 67:49] + _T_616.valid <= _T_784 @[ToTL.scala 67:22] + _T_616.bits.last <= _T_632 @[ToTL.scala 68:26] + _T_616.bits.id <= io.in.0.ar.bits.id @[ToTL.scala 69:24] + node _T_785 = and(_T_616.ready, _T_616.valid) @[Decoupled.scala 30:37] + when _T_785 : @[ToTL.scala 71:30] + node _T_788 = add(_T_631, UInt<1>("h01")) @[ToTL.scala 71:72] + node _T_789 = tail(_T_788, 1) @[ToTL.scala 71:72] + node _T_790 = mux(_T_632, UInt<1>("h00"), _T_789) @[ToTL.scala 71:46] + _T_631 <= _T_790 @[ToTL.scala 71:40] + skip @[ToTL.scala 71:30] + wire _T_791 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[ToTL.scala 73:23] + _T_791 is invalid @[ToTL.scala 73:23] + reg _T_813 : UInt<256>, clock with : (reset => (reset, UInt<256>("h00"))) @[Reg.scala 26:44] + node _T_814 = dshr(_T_813, io.in.0.aw.bits.id) @[ToTL.scala 75:31] + node _T_815 = bits(_T_814, 0, 0) @[ToTL.scala 75:31] + node _T_817 = cat(io.in.0.aw.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_818 = dshl(_T_817, io.in.0.aw.bits.size) @[Bundles.scala 28:21] + node _T_819 = shr(_T_818, 8) @[Bundles.scala 28:30] + node _T_820 = shl(_T_819, 1) @[package.scala 17:29] + node _T_822 = or(_T_820, UInt<1>("h01")) @[package.scala 17:34] + node _T_824 = cat(UInt<1>("h00"), _T_819) @[Cat.scala 30:58] + node _T_825 = not(_T_824) @[package.scala 17:47] + node _T_826 = and(_T_822, _T_825) @[package.scala 17:45] + node _T_827 = bits(_T_826, 15, 8) @[OneHot.scala 26:18] + node _T_828 = bits(_T_826, 7, 0) @[OneHot.scala 27:18] + node _T_830 = neq(_T_827, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_831 = or(_T_827, _T_828) @[OneHot.scala 28:28] + node _T_832 = bits(_T_831, 7, 4) @[OneHot.scala 26:18] + node _T_833 = bits(_T_831, 3, 0) @[OneHot.scala 27:18] + node _T_835 = neq(_T_832, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_836 = or(_T_832, _T_833) @[OneHot.scala 28:28] + node _T_837 = bits(_T_836, 3, 2) @[OneHot.scala 26:18] + node _T_838 = bits(_T_836, 1, 0) @[OneHot.scala 27:18] + node _T_840 = neq(_T_837, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_841 = or(_T_837, _T_838) @[OneHot.scala 28:28] + node _T_842 = bits(_T_841, 1, 1) @[CircuitMath.scala 30:8] + node _T_843 = cat(_T_840, _T_842) @[Cat.scala 30:58] + node _T_844 = cat(_T_835, _T_843) @[Cat.scala 30:58] + node _T_845 = cat(_T_830, _T_844) @[Cat.scala 30:58] + node _T_848 = leq(UInt<1>("h00"), _T_845) @[Parameters.scala 63:32] + node _T_850 = leq(_T_845, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_851 = and(_T_848, _T_850) @[Parameters.scala 63:37] + node _T_852 = or(UInt<1>("h00"), _T_851) @[Parameters.scala 132:31] + node _T_854 = xor(io.in.0.aw.bits.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_855 = cvt(_T_854) @[Parameters.scala 117:49] + node _T_857 = and(_T_855, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_858 = asSInt(_T_857) @[Parameters.scala 117:52] + node _T_860 = eq(_T_858, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_862 = xor(io.in.0.aw.bits.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_863 = cvt(_T_862) @[Parameters.scala 117:49] + node _T_865 = and(_T_863, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_866 = asSInt(_T_865) @[Parameters.scala 117:52] + node _T_868 = eq(_T_866, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = xor(io.in.0.aw.bits.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_871 = cvt(_T_870) @[Parameters.scala 117:49] + node _T_873 = and(_T_871, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_874 = asSInt(_T_873) @[Parameters.scala 117:52] + node _T_876 = eq(_T_874, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = xor(io.in.0.aw.bits.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_879 = cvt(_T_878) @[Parameters.scala 117:49] + node _T_881 = and(_T_879, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_882 = asSInt(_T_881) @[Parameters.scala 117:52] + node _T_884 = eq(_T_882, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_886 = xor(io.in.0.aw.bits.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_887 = cvt(_T_886) @[Parameters.scala 117:49] + node _T_889 = and(_T_887, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_890 = asSInt(_T_889) @[Parameters.scala 117:52] + node _T_892 = eq(_T_890, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_893 = or(_T_860, _T_868) @[Parameters.scala 133:42] + node _T_894 = or(_T_893, _T_876) @[Parameters.scala 133:42] + node _T_895 = or(_T_894, _T_884) @[Parameters.scala 133:42] + node _T_896 = or(_T_895, _T_892) @[Parameters.scala 133:42] + node _T_897 = and(_T_852, _T_896) @[Parameters.scala 132:56] + node _T_900 = leq(UInt<1>("h00"), _T_845) @[Parameters.scala 63:32] + node _T_902 = leq(_T_845, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_903 = and(_T_900, _T_902) @[Parameters.scala 63:37] + node _T_904 = or(UInt<1>("h00"), _T_903) @[Parameters.scala 132:31] + node _T_906 = xor(io.in.0.aw.bits.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_907 = cvt(_T_906) @[Parameters.scala 117:49] + node _T_909 = and(_T_907, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_910 = asSInt(_T_909) @[Parameters.scala 117:52] + node _T_912 = eq(_T_910, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_913 = and(_T_904, _T_912) @[Parameters.scala 132:56] + node _T_916 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_918 = xor(io.in.0.aw.bits.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_919 = cvt(_T_918) @[Parameters.scala 117:49] + node _T_921 = and(_T_919, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_922 = asSInt(_T_921) @[Parameters.scala 117:52] + node _T_924 = eq(_T_922, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_925 = and(_T_916, _T_924) @[Parameters.scala 132:56] + node _T_927 = or(UInt<1>("h00"), _T_897) @[Parameters.scala 134:30] + node _T_928 = or(_T_927, _T_913) @[Parameters.scala 134:30] + node _T_929 = or(_T_928, _T_925) @[Parameters.scala 134:30] + wire _T_937 : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>} @[ToTL.scala 80:26] + _T_937 is invalid @[ToTL.scala 80:26] + inst Queue_1 of Queue_25 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= _T_937.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <= _T_937.bits @[Decoupled.scala 255:19] + _T_937.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + node _T_946 = eq(io.in.0.aw.valid, UInt<1>("h00")) @[ToTL.scala 83:15] + node _T_948 = asUInt(asSInt(UInt<15>("h07fff"))) @[package.scala 19:64] + node _T_949 = dshl(_T_948, _T_845) @[package.scala 19:71] + node _T_950 = bits(_T_949, 14, 0) @[package.scala 19:76] + node _T_951 = not(_T_950) @[package.scala 19:40] + node _T_952 = eq(_T_819, _T_951) @[ToTL.scala 83:39] + node _T_953 = or(_T_946, _T_952) @[ToTL.scala 83:28] + node _T_954 = or(_T_953, reset) @[ToTL.scala 83:14] + node _T_956 = eq(_T_954, UInt<1>("h00")) @[ToTL.scala 83:14] + when _T_956 : @[ToTL.scala 83:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToTL.scala:83 assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned\n") @[ToTL.scala 83:14] + stop(clock, UInt<1>(1), 1) @[ToTL.scala 83:14] + skip @[ToTL.scala 83:14] + node _T_958 = eq(io.in.0.aw.valid, UInt<1>("h00")) @[ToTL.scala 84:15] + node _T_960 = eq(io.in.0.aw.bits.len, UInt<1>("h00")) @[ToTL.scala 84:46] + node _T_961 = or(_T_958, _T_960) @[ToTL.scala 84:28] + node _T_963 = eq(io.in.0.aw.bits.size, UInt<2>("h03")) @[ToTL.scala 84:77] + node _T_964 = or(_T_961, _T_963) @[ToTL.scala 84:58] + node _T_965 = or(_T_964, reset) @[ToTL.scala 84:14] + node _T_967 = eq(_T_965, UInt<1>("h00")) @[ToTL.scala 84:14] + when _T_967 : @[ToTL.scala 84:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToTL.scala:84 assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned\n") @[ToTL.scala 84:14] + stop(clock, UInt<1>(1), 1) @[ToTL.scala 84:14] + skip @[ToTL.scala 84:14] + node _T_968 = mux(_T_929, _T_791.ready, _T_937.ready) @[ToTL.scala 85:25] + node _T_969 = and(_T_968, io.in.0.w.valid) @[ToTL.scala 85:61] + node _T_970 = and(_T_969, io.in.0.w.bits.last) @[ToTL.scala 85:75] + node _T_972 = eq(_T_815, UInt<1>("h00")) @[ToTL.scala 85:96] + node _T_973 = and(_T_970, _T_972) @[ToTL.scala 85:93] + io.in.0.aw.ready <= _T_973 @[ToTL.scala 85:19] + node _T_975 = eq(io.in.0.w.bits.last, UInt<1>("h00")) @[ToTL.scala 86:63] + node _T_976 = or(_T_937.ready, _T_975) @[ToTL.scala 86:60] + node _T_977 = mux(_T_929, _T_791.ready, _T_976) @[ToTL.scala 86:25] + node _T_978 = and(_T_977, io.in.0.aw.valid) @[ToTL.scala 86:80] + node _T_980 = eq(_T_815, UInt<1>("h00")) @[ToTL.scala 86:98] + node _T_981 = and(_T_978, _T_980) @[ToTL.scala 86:95] + io.in.0.w.ready <= _T_981 @[ToTL.scala 86:19] + node _T_982 = and(io.in.0.aw.valid, io.in.0.w.valid) @[ToTL.scala 87:34] + node _T_984 = eq(_T_815, UInt<1>("h00")) @[ToTL.scala 87:51] + node _T_985 = and(_T_982, _T_984) @[ToTL.scala 87:48] + node _T_986 = and(_T_985, _T_929) @[ToTL.scala 87:60] + _T_791.valid <= _T_986 @[ToTL.scala 87:19] + node _T_987 = shl(io.in.0.aw.bits.id, 1) @[ToTL.scala 88:47] + node _T_990 = leq(UInt<1>("h00"), _T_845) @[Parameters.scala 63:32] + node _T_992 = leq(_T_845, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_993 = and(_T_990, _T_992) @[Parameters.scala 63:37] + node _T_994 = or(UInt<1>("h00"), _T_993) @[Parameters.scala 132:31] + node _T_996 = xor(io.in.0.aw.bits.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_997 = cvt(_T_996) @[Parameters.scala 117:49] + node _T_999 = and(_T_997, asSInt(UInt<33>("h0fa000000"))) @[Parameters.scala 117:52] + node _T_1000 = asSInt(_T_999) @[Parameters.scala 117:52] + node _T_1002 = eq(_T_1000, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1004 = xor(io.in.0.aw.bits.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1005 = cvt(_T_1004) @[Parameters.scala 117:49] + node _T_1007 = and(_T_1005, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_1008 = asSInt(_T_1007) @[Parameters.scala 117:52] + node _T_1010 = eq(_T_1008, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1012 = xor(io.in.0.aw.bits.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1013 = cvt(_T_1012) @[Parameters.scala 117:49] + node _T_1015 = and(_T_1013, asSInt(UInt<33>("h0fbff0000"))) @[Parameters.scala 117:52] + node _T_1016 = asSInt(_T_1015) @[Parameters.scala 117:52] + node _T_1018 = eq(_T_1016, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1020 = xor(io.in.0.aw.bits.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1021 = cvt(_T_1020) @[Parameters.scala 117:49] + node _T_1023 = and(_T_1021, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_1024 = asSInt(_T_1023) @[Parameters.scala 117:52] + node _T_1026 = eq(_T_1024, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1028 = xor(io.in.0.aw.bits.addr, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_1029 = cvt(_T_1028) @[Parameters.scala 117:49] + node _T_1031 = and(_T_1029, asSInt(UInt<33>("h0f8000000"))) @[Parameters.scala 117:52] + node _T_1032 = asSInt(_T_1031) @[Parameters.scala 117:52] + node _T_1034 = eq(_T_1032, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1035 = or(_T_1002, _T_1010) @[Parameters.scala 133:42] + node _T_1036 = or(_T_1035, _T_1018) @[Parameters.scala 133:42] + node _T_1037 = or(_T_1036, _T_1026) @[Parameters.scala 133:42] + node _T_1038 = or(_T_1037, _T_1034) @[Parameters.scala 133:42] + node _T_1039 = and(_T_994, _T_1038) @[Parameters.scala 132:56] + node _T_1042 = leq(UInt<1>("h00"), _T_845) @[Parameters.scala 63:32] + node _T_1044 = leq(_T_845, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1045 = and(_T_1042, _T_1044) @[Parameters.scala 63:37] + node _T_1046 = or(UInt<1>("h00"), _T_1045) @[Parameters.scala 132:31] + node _T_1048 = xor(io.in.0.aw.bits.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1049 = cvt(_T_1048) @[Parameters.scala 117:49] + node _T_1051 = and(_T_1049, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_1052 = asSInt(_T_1051) @[Parameters.scala 117:52] + node _T_1054 = eq(_T_1052, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = and(_T_1046, _T_1054) @[Parameters.scala 132:56] + node _T_1058 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1060 = xor(io.in.0.aw.bits.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1061 = cvt(_T_1060) @[Parameters.scala 117:49] + node _T_1063 = and(_T_1061, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_1064 = asSInt(_T_1063) @[Parameters.scala 117:52] + node _T_1066 = eq(_T_1064, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1067 = and(_T_1058, _T_1066) @[Parameters.scala 132:56] + node _T_1069 = or(UInt<1>("h00"), _T_1039) @[Parameters.scala 134:30] + node _T_1070 = or(_T_1069, _T_1055) @[Parameters.scala 134:30] + node _T_1071 = or(_T_1070, _T_1067) @[Parameters.scala 134:30] + wire _T_1080 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 370:17] + _T_1080 is invalid @[Edges.scala 370:17] + _T_1080.opcode <= UInt<1>("h01") @[Edges.scala 371:15] + _T_1080.param <= UInt<1>("h00") @[Edges.scala 372:15] + _T_1080.size <= _T_845 @[Edges.scala 373:15] + _T_1080.source <= _T_987 @[Edges.scala 374:15] + _T_1080.address <= io.in.0.aw.bits.addr @[Edges.scala 375:15] + _T_1080.mask <= io.in.0.w.bits.strb @[Edges.scala 376:15] + _T_1080.data <= io.in.0.w.bits.data @[Edges.scala 377:15] + _T_791.bits <- _T_1080 @[ToTL.scala 88:18] + node _T_1090 = and(io.in.0.aw.valid, io.in.0.w.valid) @[ToTL.scala 89:37] + node _T_1092 = eq(_T_815, UInt<1>("h00")) @[ToTL.scala 89:54] + node _T_1093 = and(_T_1090, _T_1092) @[ToTL.scala 89:51] + node _T_1095 = eq(_T_929, UInt<1>("h00")) @[ToTL.scala 89:66] + node _T_1096 = and(_T_1093, _T_1095) @[ToTL.scala 89:63] + node _T_1097 = and(_T_1096, io.in.0.w.bits.last) @[ToTL.scala 89:72] + _T_937.valid <= _T_1097 @[ToTL.scala 89:22] + _T_937.bits <= io.in.0.aw.bits.id @[ToTL.scala 90:21] + reg _T_1100 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_1103 = and(_T_1102, io.out.0.a.ready) @[Arbiter.scala 35:24] + node _T_1106 = eq(_T_476.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1107 = and(UInt<1>("h01"), _T_1106) @[Arbiter.scala 14:35] + node _T_1109 = eq(_T_791.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1110 = and(_T_1107, _T_1109) @[Arbiter.scala 14:35] + wire _T_1113 : UInt<1>[2] @[Arbiter.scala 40:23] + _T_1113 is invalid @[Arbiter.scala 40:23] + _T_1113[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_1113[1] <= _T_1107 @[Arbiter.scala 40:23] + node _T_1118 = and(_T_1113[0], _T_476.valid) @[Arbiter.scala 42:65] + node _T_1119 = and(_T_1113[1], _T_791.valid) @[Arbiter.scala 42:65] + wire _T_1122 : UInt<1>[2] @[Arbiter.scala 42:23] + _T_1122 is invalid @[Arbiter.scala 42:23] + _T_1122[0] <= _T_1118 @[Arbiter.scala 42:23] + _T_1122[1] <= _T_1119 @[Arbiter.scala 42:23] + node _T_1128 = or(UInt<1>("h00"), _T_1122[0]) @[Arbiter.scala 47:52] + node _T_1129 = or(_T_1128, _T_1122[1]) @[Arbiter.scala 47:52] + node _T_1131 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1133 = eq(_T_1122[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1134 = or(_T_1131, _T_1133) @[Arbiter.scala 48:59] + node _T_1136 = eq(_T_1128, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1138 = eq(_T_1122[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1139 = or(_T_1136, _T_1138) @[Arbiter.scala 48:59] + node _T_1140 = and(_T_1134, _T_1139) @[Arbiter.scala 48:77] + node _T_1141 = or(_T_1140, reset) @[Arbiter.scala 48:13] + node _T_1143 = eq(_T_1141, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_1143 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_1144 = or(_T_476.valid, _T_791.valid) @[Arbiter.scala 50:31] + node _T_1146 = eq(_T_1144, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_1147 = or(_T_1122[0], _T_1122[1]) @[Arbiter.scala 50:54] + node _T_1148 = or(_T_1146, _T_1147) @[Arbiter.scala 50:36] + node _T_1149 = or(_T_1148, reset) @[Arbiter.scala 50:14] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_1151 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_1153 = mux(_T_1122[0], UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1155 = mux(_T_1122[1], io.in.0.aw.bits.len, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1156 = or(_T_1153, _T_1155) @[Arbiter.scala 54:44] + node _T_1157 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + node _T_1158 = sub(_T_1100, _T_1157) @[Arbiter.scala 55:52] + node _T_1159 = asUInt(_T_1158) @[Arbiter.scala 55:52] + node _T_1160 = tail(_T_1159, 1) @[Arbiter.scala 55:52] + node _T_1161 = mux(_T_1103, _T_1156, _T_1160) @[Arbiter.scala 55:23] + _T_1100 <= _T_1161 @[Arbiter.scala 55:17] + wire _T_1166 : UInt<1>[2] @[Arbiter.scala 58:49] + _T_1166 is invalid @[Arbiter.scala 58:49] + _T_1166[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1166[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_1171 : UInt<1>[2], clock with : (reset => (reset, _T_1166)) @[Reg.scala 26:44] + node _T_1179 = mux(_T_1102, _T_1122, _T_1171) @[Arbiter.scala 59:25] + _T_1171 <- _T_1179 @[Arbiter.scala 60:13] + node _T_1187 = mux(_T_1102, _T_1113, _T_1171) @[Arbiter.scala 63:26] + node _T_1195 = and(io.out.0.a.ready, _T_1187[0]) @[Arbiter.scala 65:33] + _T_476.ready <= _T_1195 @[Arbiter.scala 65:19] + node _T_1196 = and(io.out.0.a.ready, _T_1187[1]) @[Arbiter.scala 65:33] + _T_791.ready <= _T_1196 @[Arbiter.scala 65:19] + node _T_1197 = or(_T_476.valid, _T_791.valid) @[Arbiter.scala 71:46] + node _T_1199 = mux(_T_1171[0], _T_476.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1201 = mux(_T_1171[1], _T_791.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1203 = or(_T_1199, _T_1201) @[Mux.scala 19:72] + wire _T_1205 : UInt<1> @[Mux.scala 19:72] + _T_1205 is invalid @[Mux.scala 19:72] + _T_1205 <= _T_1203 @[Mux.scala 19:72] + node _T_1206 = mux(_T_1102, _T_1197, _T_1205) @[Arbiter.scala 71:24] + io.out.0.a.valid <= _T_1206 @[Arbiter.scala 71:18] + node _T_1207 = cat(_T_476.bits.address, _T_476.bits.mask) @[Mux.scala 19:72] + node _T_1208 = cat(_T_1207, _T_476.bits.data) @[Mux.scala 19:72] + node _T_1209 = cat(_T_476.bits.size, _T_476.bits.source) @[Mux.scala 19:72] + node _T_1210 = cat(_T_476.bits.opcode, _T_476.bits.param) @[Mux.scala 19:72] + node _T_1211 = cat(_T_1210, _T_1209) @[Mux.scala 19:72] + node _T_1212 = cat(_T_1211, _T_1208) @[Mux.scala 19:72] + node _T_1214 = mux(_T_1179[0], _T_1212, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1215 = cat(_T_791.bits.address, _T_791.bits.mask) @[Mux.scala 19:72] + node _T_1216 = cat(_T_1215, _T_791.bits.data) @[Mux.scala 19:72] + node _T_1217 = cat(_T_791.bits.size, _T_791.bits.source) @[Mux.scala 19:72] + node _T_1218 = cat(_T_791.bits.opcode, _T_791.bits.param) @[Mux.scala 19:72] + node _T_1219 = cat(_T_1218, _T_1217) @[Mux.scala 19:72] + node _T_1220 = cat(_T_1219, _T_1216) @[Mux.scala 19:72] + node _T_1222 = mux(_T_1179[1], _T_1220, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1231 = or(_T_1214, _T_1222) @[Mux.scala 19:72] + wire _T_1240 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_1240 is invalid @[Mux.scala 19:72] + wire _T_1249 : UInt<123> + _T_1249 is invalid + _T_1249 <= _T_1231 + node _T_1250 = bits(_T_1249, 63, 0) @[Mux.scala 19:72] + _T_1240.data <= _T_1250 @[Mux.scala 19:72] + node _T_1251 = bits(_T_1249, 71, 64) @[Mux.scala 19:72] + _T_1240.mask <= _T_1251 @[Mux.scala 19:72] + node _T_1252 = bits(_T_1249, 103, 72) @[Mux.scala 19:72] + _T_1240.address <= _T_1252 @[Mux.scala 19:72] + node _T_1253 = bits(_T_1249, 112, 104) @[Mux.scala 19:72] + _T_1240.source <= _T_1253 @[Mux.scala 19:72] + node _T_1254 = bits(_T_1249, 116, 113) @[Mux.scala 19:72] + _T_1240.size <= _T_1254 @[Mux.scala 19:72] + node _T_1255 = bits(_T_1249, 119, 117) @[Mux.scala 19:72] + _T_1240.param <= _T_1255 @[Mux.scala 19:72] + node _T_1256 = bits(_T_1249, 122, 120) @[Mux.scala 19:72] + _T_1240.opcode <= _T_1256 @[Mux.scala 19:72] + io.out.0.a.bits <- _T_1240 @[Arbiter.scala 72:17] + wire _T_1257 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}} @[ToTL.scala 94:23] + _T_1257 is invalid @[ToTL.scala 94:23] + wire _T_1268 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}} @[ToTL.scala 95:23] + _T_1268 is invalid @[ToTL.scala 95:23] + wire _T_1279 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}} @[ToTL.scala 96:23] + _T_1279 is invalid @[ToTL.scala 96:23] + wire _T_1290 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[ToTL.scala 97:23] + _T_1290 is invalid @[ToTL.scala 97:23] + wire _T_1305 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[ToTL.scala 98:23] + _T_1305 is invalid @[ToTL.scala 98:23] + wire _T_1320 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[ToTL.scala 99:23] + _T_1320 is invalid @[ToTL.scala 99:23] + node _T_1337 = mux(io.out.0.d.bits.error, UInt<2>("h02"), UInt<2>("h00")) @[ToTL.scala 101:23] + node _T_1338 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1339 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + node _T_1341 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1342 = dshl(_T_1341, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_1343 = bits(_T_1342, 7, 0) @[package.scala 19:76] + node _T_1344 = not(_T_1343) @[package.scala 19:40] + node _T_1345 = shr(_T_1344, 3) @[Edges.scala 198:59] + node _T_1346 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1348 = mux(_T_1346, _T_1345, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1350 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1352 = sub(_T_1350, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1353 = asUInt(_T_1352) @[Edges.scala 208:28] + node _T_1354 = tail(_T_1353, 1) @[Edges.scala 208:28] + node _T_1356 = eq(_T_1350, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1358 = eq(_T_1350, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1360 = eq(_T_1348, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1361 = or(_T_1358, _T_1360) @[Edges.scala 210:37] + node _T_1362 = and(_T_1361, _T_1339) @[Edges.scala 211:22] + node _T_1363 = not(_T_1354) @[Edges.scala 212:27] + node _T_1364 = and(_T_1348, _T_1363) @[Edges.scala 212:25] + when _T_1339 : @[Edges.scala 213:17] + node _T_1365 = mux(_T_1356, _T_1348, _T_1354) @[Edges.scala 214:21] + _T_1350 <= _T_1365 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1366 = mux(_T_1338, _T_1290.ready, _T_1257.ready) @[ToTL.scala 105:25] + io.out.0.d.ready <= _T_1366 @[ToTL.scala 105:19] + node _T_1367 = and(io.out.0.d.valid, _T_1338) @[ToTL.scala 106:33] + _T_1290.valid <= _T_1367 @[ToTL.scala 106:18] + node _T_1369 = eq(_T_1338, UInt<1>("h00")) @[ToTL.scala 107:36] + node _T_1370 = and(io.out.0.d.valid, _T_1369) @[ToTL.scala 107:33] + _T_1257.valid <= _T_1370 @[ToTL.scala 107:18] + node _T_1371 = shr(io.out.0.d.bits.source, 1) @[ToTL.scala 109:43] + _T_1290.bits.id <= _T_1371 @[ToTL.scala 109:22] + _T_1290.bits.data <= io.out.0.d.bits.data @[ToTL.scala 110:22] + _T_1290.bits.resp <= _T_1337 @[ToTL.scala 111:22] + _T_1290.bits.last <= _T_1361 @[ToTL.scala 112:22] + Queue.io.deq.ready <= _T_1305.ready @[ToTL.scala 114:23] + _T_1305.valid <= Queue.io.deq.valid @[ToTL.scala 115:19] + _T_1305.bits.id <= Queue.io.deq.bits.id @[ToTL.scala 116:23] + _T_1305.bits.data <= io.out.0.d.bits.data @[ToTL.scala 117:23] + _T_1305.bits.resp <= UInt<2>("h03") @[ToTL.scala 118:23] + _T_1305.bits.last <= Queue.io.deq.bits.last @[ToTL.scala 119:23] + reg _T_1374 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_1376 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1377 = and(_T_1290.ready, _T_1290.valid) @[Decoupled.scala 30:37] + when _T_1377 : @[ToTL.scala 124:27] + node _T_1379 = eq(_T_1290.bits.last, UInt<1>("h00")) @[ToTL.scala 124:45] + _T_1374 <= _T_1379 @[ToTL.scala 124:42] + skip @[ToTL.scala 124:27] + node _T_1380 = and(_T_1305.ready, _T_1305.valid) @[Decoupled.scala 30:37] + when _T_1380 : @[ToTL.scala 125:27] + node _T_1382 = eq(_T_1305.bits.last, UInt<1>("h00")) @[ToTL.scala 125:45] + _T_1376 <= _T_1382 @[ToTL.scala 125:42] + skip @[ToTL.scala 125:27] + node _T_1384 = eq(_T_1374, UInt<1>("h00")) @[ToTL.scala 126:15] + node _T_1386 = eq(_T_1376, UInt<1>("h00")) @[ToTL.scala 126:31] + node _T_1387 = or(_T_1384, _T_1386) @[ToTL.scala 126:28] + node _T_1388 = or(_T_1387, reset) @[ToTL.scala 126:14] + node _T_1390 = eq(_T_1388, UInt<1>("h00")) @[ToTL.scala 126:14] + when _T_1390 : @[ToTL.scala 126:14] + printf(clock, UInt<1>(1), "Assertion failed\n at ToTL.scala:126 assert (!mux_lock_ok || !mux_lock_err)\n") @[ToTL.scala 126:14] + stop(clock, UInt<1>(1), 1) @[ToTL.scala 126:14] + skip @[ToTL.scala 126:14] + node _T_1392 = eq(_T_1376, UInt<1>("h00")) @[ToTL.scala 129:23] + node _T_1393 = and(_T_1392, _T_1290.valid) @[ToTL.scala 129:37] + node _T_1395 = eq(_T_1374, UInt<1>("h00")) @[ToTL.scala 129:56] + node _T_1396 = and(_T_1395, _T_1305.valid) @[ToTL.scala 129:69] + node _T_1397 = or(_T_1393, _T_1396) @[ToTL.scala 129:52] + _T_1320.valid <= _T_1397 @[ToTL.scala 129:19] + node _T_1399 = eq(_T_1374, UInt<1>("h00")) @[ToTL.scala 130:26] + node _T_1400 = and(_T_1399, _T_1305.valid) @[ToTL.scala 130:39] + node _T_1401 = mux(_T_1400, _T_1305.bits, _T_1290.bits) @[ToTL.scala 130:25] + _T_1320.bits <- _T_1401 @[ToTL.scala 130:19] + node _T_1407 = eq(_T_1305.valid, UInt<1>("h00")) @[ToTL.scala 131:53] + node _T_1408 = or(_T_1374, _T_1407) @[ToTL.scala 131:50] + node _T_1409 = and(_T_1320.ready, _T_1408) @[ToTL.scala 131:34] + _T_1290.ready <= _T_1409 @[ToTL.scala 131:19] + node _T_1411 = eq(_T_1374, UInt<1>("h00")) @[ToTL.scala 132:37] + node _T_1412 = and(_T_1320.ready, _T_1411) @[ToTL.scala 132:34] + _T_1305.ready <= _T_1412 @[ToTL.scala 132:19] + inst Queue_2 of Queue_26 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_1320.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_1320.bits @[Decoupled.scala 255:19] + _T_1320.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + wire _T_1433 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[Decoupled.scala 272:19] + _T_1433 is invalid @[Decoupled.scala 272:19] + _T_1433.bits <- Queue_2.io.deq.bits @[Decoupled.scala 273:14] + _T_1433.valid <= Queue_2.io.deq.valid @[Decoupled.scala 274:15] + Queue_2.io.deq.ready <= _T_1433.ready @[Decoupled.scala 275:15] + io.in.0.r <- _T_1433 @[ToTL.scala 135:12] + node _T_1448 = shr(io.out.0.d.bits.source, 1) @[ToTL.scala 137:43] + _T_1257.bits.id <= _T_1448 @[ToTL.scala 137:22] + _T_1257.bits.resp <= _T_1337 @[ToTL.scala 138:22] + Queue_1.io.deq.ready <= _T_1268.ready @[ToTL.scala 140:23] + _T_1268.valid <= Queue_1.io.deq.valid @[ToTL.scala 141:19] + _T_1268.bits.id <= Queue_1.io.deq.bits @[ToTL.scala 142:23] + _T_1268.bits.resp <= UInt<2>("h03") @[ToTL.scala 143:23] + node _T_1450 = or(_T_1257.valid, _T_1268.valid) @[ToTL.scala 146:33] + _T_1279.valid <= _T_1450 @[ToTL.scala 146:19] + node _T_1451 = mux(_T_1268.valid, _T_1268.bits, _T_1257.bits) @[ToTL.scala 147:25] + _T_1279.bits <- _T_1451 @[ToTL.scala 147:19] + node _T_1455 = eq(_T_1268.valid, UInt<1>("h00")) @[ToTL.scala 148:37] + node _T_1456 = and(_T_1279.ready, _T_1455) @[ToTL.scala 148:34] + _T_1257.ready <= _T_1456 @[ToTL.scala 148:19] + _T_1268.ready <= _T_1279.ready @[ToTL.scala 149:19] + inst Queue_3 of Queue_27 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= _T_1279.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- _T_1279.bits @[Decoupled.scala 255:19] + _T_1279.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + wire _T_1471 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}} @[Decoupled.scala 272:19] + _T_1471 is invalid @[Decoupled.scala 272:19] + _T_1471.bits <- Queue_3.io.deq.bits @[Decoupled.scala 273:14] + _T_1471.valid <= Queue_3.io.deq.valid @[Decoupled.scala 274:15] + Queue_3.io.deq.ready <= _T_1471.ready @[Decoupled.scala 275:15] + io.in.0.b <- _T_1471 @[ToTL.scala 152:12] + node _T_1482 = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + node _T_1483 = dshl(_T_1482, io.in.0.ar.bits.id) @[ToTL.scala 155:39] + node _T_1484 = and(io.in.0.r.ready, io.in.0.r.valid) @[Decoupled.scala 30:37] + node _T_1485 = and(_T_1484, io.in.0.r.bits.last) @[ToTL.scala 156:32] + node _T_1486 = dshl(_T_1485, io.in.0.r.bits.id) @[ToTL.scala 156:58] + node _T_1487 = or(_T_498, _T_1483) @[ToTL.scala 157:33] + node _T_1488 = not(_T_1486) @[ToTL.scala 157:44] + node _T_1489 = and(_T_1487, _T_1488) @[ToTL.scala 157:42] + _T_498 <= _T_1489 @[ToTL.scala 157:18] + node _T_1490 = and(io.in.0.aw.ready, io.in.0.aw.valid) @[Decoupled.scala 30:37] + node _T_1491 = dshl(_T_1490, io.in.0.aw.bits.id) @[ToTL.scala 158:39] + node _T_1492 = and(io.in.0.b.ready, io.in.0.b.valid) @[Decoupled.scala 30:37] + node _T_1493 = dshl(_T_1492, io.in.0.b.bits.id) @[ToTL.scala 159:38] + node _T_1494 = or(_T_813, _T_1491) @[ToTL.scala 160:33] + node _T_1495 = not(_T_1493) @[ToTL.scala 160:44] + node _T_1496 = and(_T_1494, _T_1495) @[ToTL.scala 160:42] + _T_813 <= _T_1496 @[ToTL.scala 160:18] + io.out.0.b.ready <= UInt<1>("h01") @[ToTL.scala 163:19] + io.out.0.c.valid <= UInt<1>("h00") @[ToTL.scala 164:19] + io.out.0.e.valid <= UInt<1>("h00") @[ToTL.scala 165:19] + + module TLWidthWidget_l1tol2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + io.out.0.a <- io.in.0.a @[WidthWidget.scala 131:13] + io.in.0.d <- io.out.0.d @[WidthWidget.scala 131:13] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_7 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 219:36] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 219:36] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_608 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:219:36)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + when _T_700 : @[Periphery.scala 219:36] + node _T_703 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_705 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_706 = and(_T_703, _T_705) @[Parameters.scala 63:37] + node _T_707 = or(UInt<1>("h00"), _T_706) @[Parameters.scala 132:31] + node _T_709 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_710 = cvt(_T_709) @[Parameters.scala 117:49] + node _T_712 = and(_T_710, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_713 = asSInt(_T_712) @[Parameters.scala 117:52] + node _T_715 = eq(_T_713, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_717 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_718 = cvt(_T_717) @[Parameters.scala 117:49] + node _T_720 = and(_T_718, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_721 = asSInt(_T_720) @[Parameters.scala 117:52] + node _T_723 = eq(_T_721, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_724 = or(_T_715, _T_723) @[Parameters.scala 133:42] + node _T_725 = and(_T_707, _T_724) @[Parameters.scala 132:56] + node _T_728 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_730 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_731 = cvt(_T_730) @[Parameters.scala 117:49] + node _T_733 = and(_T_731, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_734 = asSInt(_T_733) @[Parameters.scala 117:52] + node _T_736 = eq(_T_734, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_738 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_739 = cvt(_T_738) @[Parameters.scala 117:49] + node _T_741 = and(_T_739, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_742 = asSInt(_T_741) @[Parameters.scala 117:52] + node _T_744 = eq(_T_742, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_746 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_747 = cvt(_T_746) @[Parameters.scala 117:49] + node _T_749 = and(_T_747, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_750 = asSInt(_T_749) @[Parameters.scala 117:52] + node _T_752 = eq(_T_750, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_754 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_755 = cvt(_T_754) @[Parameters.scala 117:49] + node _T_757 = and(_T_755, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_758 = asSInt(_T_757) @[Parameters.scala 117:52] + node _T_760 = eq(_T_758, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_761 = or(_T_736, _T_744) @[Parameters.scala 133:42] + node _T_762 = or(_T_761, _T_752) @[Parameters.scala 133:42] + node _T_763 = or(_T_762, _T_760) @[Parameters.scala 133:42] + node _T_764 = and(_T_728, _T_763) @[Parameters.scala 132:56] + node _T_766 = or(UInt<1>("h00"), _T_725) @[Parameters.scala 134:30] + node _T_767 = or(_T_766, _T_764) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[Periphery.scala 219:36] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_770 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_771 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_773 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_775 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_776 = or(_T_775, reset) @[Periphery.scala 219:36] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_778 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_779 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_781 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_783 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_784 = or(_T_783, reset) @[Periphery.scala 219:36] + node _T_786 = eq(_T_784, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_786 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:219:36)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_787 = not(io.in[0].a.bits.mask) @[Periphery.scala 219:36] + node _T_789 = eq(_T_787, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_790 = or(_T_789, reset) @[Periphery.scala 219:36] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_792 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_794 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 219:36] + when _T_794 : @[Periphery.scala 219:36] + node _T_797 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_799 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_800 = and(_T_797, _T_799) @[Parameters.scala 63:37] + node _T_801 = or(UInt<1>("h00"), _T_800) @[Parameters.scala 132:31] + node _T_803 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_812 = cvt(_T_811) @[Parameters.scala 117:49] + node _T_814 = and(_T_812, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_815 = asSInt(_T_814) @[Parameters.scala 117:52] + node _T_817 = eq(_T_815, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_819 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_820 = cvt(_T_819) @[Parameters.scala 117:49] + node _T_822 = and(_T_820, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_823 = asSInt(_T_822) @[Parameters.scala 117:52] + node _T_825 = eq(_T_823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_827 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_828 = cvt(_T_827) @[Parameters.scala 117:49] + node _T_830 = and(_T_828, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_831 = asSInt(_T_830) @[Parameters.scala 117:52] + node _T_833 = eq(_T_831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_835 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = or(_T_809, _T_817) @[Parameters.scala 133:42] + node _T_843 = or(_T_842, _T_825) @[Parameters.scala 133:42] + node _T_844 = or(_T_843, _T_833) @[Parameters.scala 133:42] + node _T_845 = or(_T_844, _T_841) @[Parameters.scala 133:42] + node _T_846 = and(_T_801, _T_845) @[Parameters.scala 132:56] + node _T_849 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_851 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_852 = and(_T_849, _T_851) @[Parameters.scala 63:37] + node _T_853 = or(UInt<1>("h00"), _T_852) @[Parameters.scala 132:31] + node _T_855 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_862 = and(_T_853, _T_861) @[Parameters.scala 132:56] + node _T_864 = or(UInt<1>("h00"), _T_846) @[Parameters.scala 134:30] + node _T_865 = or(_T_864, _T_862) @[Parameters.scala 134:30] + node _T_866 = or(_T_865, reset) @[Periphery.scala 219:36] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_868 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_869 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_871 = eq(_T_869, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_871 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_872 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_874 = eq(_T_872, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_874 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_876 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_877 = or(_T_876, reset) @[Periphery.scala 219:36] + node _T_879 = eq(_T_877, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_879 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_880 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 219:36] + node _T_881 = or(_T_880, reset) @[Periphery.scala 219:36] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_883 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_885 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_885 : @[Periphery.scala 219:36] + node _T_888 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_890 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_891 = and(_T_888, _T_890) @[Parameters.scala 63:37] + node _T_892 = or(UInt<1>("h00"), _T_891) @[Parameters.scala 132:31] + node _T_894 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_895 = cvt(_T_894) @[Parameters.scala 117:49] + node _T_897 = and(_T_895, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_898 = asSInt(_T_897) @[Parameters.scala 117:52] + node _T_900 = eq(_T_898, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_902 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_903 = cvt(_T_902) @[Parameters.scala 117:49] + node _T_905 = and(_T_903, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_906 = asSInt(_T_905) @[Parameters.scala 117:52] + node _T_908 = eq(_T_906, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_910 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_911 = cvt(_T_910) @[Parameters.scala 117:49] + node _T_913 = and(_T_911, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_914 = asSInt(_T_913) @[Parameters.scala 117:52] + node _T_916 = eq(_T_914, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_918 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_919 = cvt(_T_918) @[Parameters.scala 117:49] + node _T_921 = and(_T_919, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_922 = asSInt(_T_921) @[Parameters.scala 117:52] + node _T_924 = eq(_T_922, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_926 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_927 = cvt(_T_926) @[Parameters.scala 117:49] + node _T_929 = and(_T_927, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_930 = asSInt(_T_929) @[Parameters.scala 117:52] + node _T_932 = eq(_T_930, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_933 = or(_T_900, _T_908) @[Parameters.scala 133:42] + node _T_934 = or(_T_933, _T_916) @[Parameters.scala 133:42] + node _T_935 = or(_T_934, _T_924) @[Parameters.scala 133:42] + node _T_936 = or(_T_935, _T_932) @[Parameters.scala 133:42] + node _T_937 = and(_T_892, _T_936) @[Parameters.scala 132:56] + node _T_940 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_942 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_943 = and(_T_940, _T_942) @[Parameters.scala 63:37] + node _T_944 = or(UInt<1>("h00"), _T_943) @[Parameters.scala 132:31] + node _T_946 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_947 = cvt(_T_946) @[Parameters.scala 117:49] + node _T_949 = and(_T_947, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_950 = asSInt(_T_949) @[Parameters.scala 117:52] + node _T_952 = eq(_T_950, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_953 = and(_T_944, _T_952) @[Parameters.scala 132:56] + node _T_956 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_958 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_959 = cvt(_T_958) @[Parameters.scala 117:49] + node _T_961 = and(_T_959, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_962 = asSInt(_T_961) @[Parameters.scala 117:52] + node _T_964 = eq(_T_962, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_965 = and(_T_956, _T_964) @[Parameters.scala 132:56] + node _T_967 = or(UInt<1>("h00"), _T_937) @[Parameters.scala 134:30] + node _T_968 = or(_T_967, _T_953) @[Parameters.scala 134:30] + node _T_969 = or(_T_968, _T_965) @[Parameters.scala 134:30] + node _T_970 = or(_T_969, reset) @[Periphery.scala 219:36] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_972 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_973 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_975 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_976 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_978 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_980 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_981 = or(_T_980, reset) @[Periphery.scala 219:36] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_983 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_984 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 219:36] + node _T_985 = or(_T_984, reset) @[Periphery.scala 219:36] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_987 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_989 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 219:36] + when _T_989 : @[Periphery.scala 219:36] + node _T_992 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_994 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_995 = and(_T_992, _T_994) @[Parameters.scala 63:37] + node _T_996 = or(UInt<1>("h00"), _T_995) @[Parameters.scala 132:31] + node _T_998 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_999 = cvt(_T_998) @[Parameters.scala 117:49] + node _T_1001 = and(_T_999, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1002 = asSInt(_T_1001) @[Parameters.scala 117:52] + node _T_1004 = eq(_T_1002, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1006 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1007 = cvt(_T_1006) @[Parameters.scala 117:49] + node _T_1009 = and(_T_1007, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1010 = asSInt(_T_1009) @[Parameters.scala 117:52] + node _T_1012 = eq(_T_1010, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1014 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1015 = cvt(_T_1014) @[Parameters.scala 117:49] + node _T_1017 = and(_T_1015, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1018 = asSInt(_T_1017) @[Parameters.scala 117:52] + node _T_1020 = eq(_T_1018, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1022 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1023 = cvt(_T_1022) @[Parameters.scala 117:49] + node _T_1025 = and(_T_1023, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1026 = asSInt(_T_1025) @[Parameters.scala 117:52] + node _T_1028 = eq(_T_1026, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1030 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1031 = cvt(_T_1030) @[Parameters.scala 117:49] + node _T_1033 = and(_T_1031, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1034 = asSInt(_T_1033) @[Parameters.scala 117:52] + node _T_1036 = eq(_T_1034, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1037 = or(_T_1004, _T_1012) @[Parameters.scala 133:42] + node _T_1038 = or(_T_1037, _T_1020) @[Parameters.scala 133:42] + node _T_1039 = or(_T_1038, _T_1028) @[Parameters.scala 133:42] + node _T_1040 = or(_T_1039, _T_1036) @[Parameters.scala 133:42] + node _T_1041 = and(_T_996, _T_1040) @[Parameters.scala 132:56] + node _T_1044 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1046 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1047 = and(_T_1044, _T_1046) @[Parameters.scala 63:37] + node _T_1048 = or(UInt<1>("h00"), _T_1047) @[Parameters.scala 132:31] + node _T_1050 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1051 = cvt(_T_1050) @[Parameters.scala 117:49] + node _T_1053 = and(_T_1051, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1054 = asSInt(_T_1053) @[Parameters.scala 117:52] + node _T_1056 = eq(_T_1054, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1057 = and(_T_1048, _T_1056) @[Parameters.scala 132:56] + node _T_1060 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1062 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1063 = cvt(_T_1062) @[Parameters.scala 117:49] + node _T_1065 = and(_T_1063, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1066 = asSInt(_T_1065) @[Parameters.scala 117:52] + node _T_1068 = eq(_T_1066, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = and(_T_1060, _T_1068) @[Parameters.scala 132:56] + node _T_1071 = or(UInt<1>("h00"), _T_1041) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, _T_1057) @[Parameters.scala 134:30] + node _T_1073 = or(_T_1072, _T_1069) @[Parameters.scala 134:30] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 219:36] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1076 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1077 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1079 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1080 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1082 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1084 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1085 = or(_T_1084, reset) @[Periphery.scala 219:36] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1087 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1088 = not(_T_698) @[Periphery.scala 219:36] + node _T_1089 = and(io.in[0].a.bits.mask, _T_1088) @[Periphery.scala 219:36] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1092 = or(_T_1091, reset) @[Periphery.scala 219:36] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1094 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1096 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 219:36] + when _T_1096 : @[Periphery.scala 219:36] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1113 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1114 = cvt(_T_1113) @[Parameters.scala 117:49] + node _T_1116 = and(_T_1114, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1117 = asSInt(_T_1116) @[Parameters.scala 117:52] + node _T_1119 = eq(_T_1117, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1121 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1122 = cvt(_T_1121) @[Parameters.scala 117:49] + node _T_1124 = and(_T_1122, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1125 = asSInt(_T_1124) @[Parameters.scala 117:52] + node _T_1127 = eq(_T_1125, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1128 = or(_T_1111, _T_1119) @[Parameters.scala 133:42] + node _T_1129 = or(_T_1128, _T_1127) @[Parameters.scala 133:42] + node _T_1130 = and(_T_1103, _T_1129) @[Parameters.scala 132:56] + node _T_1133 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1135 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1136 = cvt(_T_1135) @[Parameters.scala 117:49] + node _T_1138 = and(_T_1136, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1139 = asSInt(_T_1138) @[Parameters.scala 117:52] + node _T_1141 = eq(_T_1139, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1143 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1144 = cvt(_T_1143) @[Parameters.scala 117:49] + node _T_1146 = and(_T_1144, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1147 = asSInt(_T_1146) @[Parameters.scala 117:52] + node _T_1149 = eq(_T_1147, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1151 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1152 = cvt(_T_1151) @[Parameters.scala 117:49] + node _T_1154 = and(_T_1152, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1155 = asSInt(_T_1154) @[Parameters.scala 117:52] + node _T_1157 = eq(_T_1155, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1159 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1160 = cvt(_T_1159) @[Parameters.scala 117:49] + node _T_1162 = and(_T_1160, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1163 = asSInt(_T_1162) @[Parameters.scala 117:52] + node _T_1165 = eq(_T_1163, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1166 = or(_T_1141, _T_1149) @[Parameters.scala 133:42] + node _T_1167 = or(_T_1166, _T_1157) @[Parameters.scala 133:42] + node _T_1168 = or(_T_1167, _T_1165) @[Parameters.scala 133:42] + node _T_1169 = and(_T_1133, _T_1168) @[Parameters.scala 132:56] + node _T_1171 = or(UInt<1>("h00"), _T_1130) @[Parameters.scala 134:30] + node _T_1172 = or(_T_1171, _T_1169) @[Parameters.scala 134:30] + node _T_1173 = or(_T_1172, reset) @[Periphery.scala 219:36] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1175 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1176 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1178 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1179 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_1181 = eq(_T_1179, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1181 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1183 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1184 = or(_T_1183, reset) @[Periphery.scala 219:36] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1186 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:219:36)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1187 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 219:36] + node _T_1188 = or(_T_1187, reset) @[Periphery.scala 219:36] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1190 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1192 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 219:36] + when _T_1192 : @[Periphery.scala 219:36] + node _T_1195 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1197 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1198 = and(_T_1195, _T_1197) @[Parameters.scala 63:37] + node _T_1199 = or(UInt<1>("h00"), _T_1198) @[Parameters.scala 132:31] + node _T_1201 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1202 = cvt(_T_1201) @[Parameters.scala 117:49] + node _T_1204 = and(_T_1202, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1205 = asSInt(_T_1204) @[Parameters.scala 117:52] + node _T_1207 = eq(_T_1205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1209 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1210 = cvt(_T_1209) @[Parameters.scala 117:49] + node _T_1212 = and(_T_1210, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1213 = asSInt(_T_1212) @[Parameters.scala 117:52] + node _T_1215 = eq(_T_1213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1217 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1218 = cvt(_T_1217) @[Parameters.scala 117:49] + node _T_1220 = and(_T_1218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1221 = asSInt(_T_1220) @[Parameters.scala 117:52] + node _T_1223 = eq(_T_1221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1224 = or(_T_1207, _T_1215) @[Parameters.scala 133:42] + node _T_1225 = or(_T_1224, _T_1223) @[Parameters.scala 133:42] + node _T_1226 = and(_T_1199, _T_1225) @[Parameters.scala 132:56] + node _T_1229 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1231 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1239 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1240 = cvt(_T_1239) @[Parameters.scala 117:49] + node _T_1242 = and(_T_1240, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1243 = asSInt(_T_1242) @[Parameters.scala 117:52] + node _T_1245 = eq(_T_1243, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1247 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1248 = cvt(_T_1247) @[Parameters.scala 117:49] + node _T_1250 = and(_T_1248, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1251 = asSInt(_T_1250) @[Parameters.scala 117:52] + node _T_1253 = eq(_T_1251, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1255 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1256 = cvt(_T_1255) @[Parameters.scala 117:49] + node _T_1258 = and(_T_1256, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1259 = asSInt(_T_1258) @[Parameters.scala 117:52] + node _T_1261 = eq(_T_1259, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1262 = or(_T_1237, _T_1245) @[Parameters.scala 133:42] + node _T_1263 = or(_T_1262, _T_1253) @[Parameters.scala 133:42] + node _T_1264 = or(_T_1263, _T_1261) @[Parameters.scala 133:42] + node _T_1265 = and(_T_1229, _T_1264) @[Parameters.scala 132:56] + node _T_1267 = or(UInt<1>("h00"), _T_1226) @[Parameters.scala 134:30] + node _T_1268 = or(_T_1267, _T_1265) @[Parameters.scala 134:30] + node _T_1269 = or(_T_1268, reset) @[Periphery.scala 219:36] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1271 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1272 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1274 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1275 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1277 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1279 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1280 = or(_T_1279, reset) @[Periphery.scala 219:36] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1282 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:219:36)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1283 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 219:36] + node _T_1284 = or(_T_1283, reset) @[Periphery.scala 219:36] + node _T_1286 = eq(_T_1284, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1286 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1288 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 219:36] + when _T_1288 : @[Periphery.scala 219:36] + node _T_1291 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1293 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1294 = cvt(_T_1293) @[Parameters.scala 117:49] + node _T_1296 = and(_T_1294, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1297 = asSInt(_T_1296) @[Parameters.scala 117:52] + node _T_1299 = eq(_T_1297, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1301 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1302 = cvt(_T_1301) @[Parameters.scala 117:49] + node _T_1304 = and(_T_1302, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1305 = asSInt(_T_1304) @[Parameters.scala 117:52] + node _T_1307 = eq(_T_1305, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1309 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1310 = cvt(_T_1309) @[Parameters.scala 117:49] + node _T_1312 = and(_T_1310, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1313 = asSInt(_T_1312) @[Parameters.scala 117:52] + node _T_1315 = eq(_T_1313, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1317 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1318 = cvt(_T_1317) @[Parameters.scala 117:49] + node _T_1320 = and(_T_1318, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1321 = asSInt(_T_1320) @[Parameters.scala 117:52] + node _T_1323 = eq(_T_1321, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1325 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1326 = cvt(_T_1325) @[Parameters.scala 117:49] + node _T_1328 = and(_T_1326, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1329 = asSInt(_T_1328) @[Parameters.scala 117:52] + node _T_1331 = eq(_T_1329, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1333 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1334 = cvt(_T_1333) @[Parameters.scala 117:49] + node _T_1336 = and(_T_1334, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1337 = asSInt(_T_1336) @[Parameters.scala 117:52] + node _T_1339 = eq(_T_1337, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1340 = or(_T_1299, _T_1307) @[Parameters.scala 133:42] + node _T_1341 = or(_T_1340, _T_1315) @[Parameters.scala 133:42] + node _T_1342 = or(_T_1341, _T_1323) @[Parameters.scala 133:42] + node _T_1343 = or(_T_1342, _T_1331) @[Parameters.scala 133:42] + node _T_1344 = or(_T_1343, _T_1339) @[Parameters.scala 133:42] + node _T_1345 = and(_T_1291, _T_1344) @[Parameters.scala 132:56] + node _T_1347 = or(UInt<1>("h00"), _T_1345) @[Parameters.scala 134:30] + node _T_1348 = or(_T_1347, reset) @[Periphery.scala 219:36] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1350 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1351 = or(_T_619[0], reset) @[Periphery.scala 219:36] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1353 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1354 = or(_T_630, reset) @[Periphery.scala 219:36] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1356 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1357 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 219:36] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 219:36] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1360 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + when io.in[0].b.valid : @[Periphery.scala 219:36] + node _T_1362 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1363 = or(_T_1362, reset) @[Periphery.scala 219:36] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1365 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:219:36)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1367 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1375 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1376 = cvt(_T_1375) @[Parameters.scala 117:49] + node _T_1378 = and(_T_1376, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1379 = asSInt(_T_1378) @[Parameters.scala 117:52] + node _T_1381 = eq(_T_1379, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1383 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1384 = cvt(_T_1383) @[Parameters.scala 117:49] + node _T_1386 = and(_T_1384, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1387 = asSInt(_T_1386) @[Parameters.scala 117:52] + node _T_1389 = eq(_T_1387, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1391 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1392 = cvt(_T_1391) @[Parameters.scala 117:49] + node _T_1394 = and(_T_1392, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1395 = asSInt(_T_1394) @[Parameters.scala 117:52] + node _T_1397 = eq(_T_1395, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1399 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1400 = cvt(_T_1399) @[Parameters.scala 117:49] + node _T_1402 = and(_T_1400, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1403 = asSInt(_T_1402) @[Parameters.scala 117:52] + node _T_1405 = eq(_T_1403, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1407 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1424 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1424 is invalid @[Parameters.scala 110:36] + _T_1424[0] <= _T_1373 @[Parameters.scala 110:36] + _T_1424[1] <= _T_1381 @[Parameters.scala 110:36] + _T_1424[2] <= _T_1389 @[Parameters.scala 110:36] + _T_1424[3] <= _T_1397 @[Parameters.scala 110:36] + _T_1424[4] <= _T_1405 @[Parameters.scala 110:36] + _T_1424[5] <= _T_1413 @[Parameters.scala 110:36] + _T_1424[6] <= _T_1421 @[Parameters.scala 110:36] + node _T_1434 = or(_T_1424[0], _T_1424[1]) @[Parameters.scala 119:64] + node _T_1435 = or(_T_1434, _T_1424[2]) @[Parameters.scala 119:64] + node _T_1436 = or(_T_1435, _T_1424[3]) @[Parameters.scala 119:64] + node _T_1437 = or(_T_1436, _T_1424[4]) @[Parameters.scala 119:64] + node _T_1438 = or(_T_1437, _T_1424[5]) @[Parameters.scala 119:64] + node _T_1439 = or(_T_1438, _T_1424[6]) @[Parameters.scala 119:64] + node _T_1441 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1442 = dshl(_T_1441, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1443 = bits(_T_1442, 7, 0) @[package.scala 19:76] + node _T_1444 = not(_T_1443) @[package.scala 19:40] + node _T_1445 = and(io.in[0].b.bits.address, _T_1444) @[Edges.scala 17:16] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1449 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1450 = dshl(UInt<1>("h01"), _T_1449) @[OneHot.scala 49:12] + node _T_1451 = bits(_T_1450, 2, 0) @[OneHot.scala 49:37] + node _T_1453 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1455 = bits(_T_1451, 2, 2) @[package.scala 44:26] + node _T_1456 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[package.scala 46:20] + node _T_1459 = and(UInt<1>("h01"), _T_1458) @[package.scala 49:27] + node _T_1460 = and(_T_1455, _T_1459) @[package.scala 50:38] + node _T_1461 = or(_T_1453, _T_1460) @[package.scala 50:29] + node _T_1462 = and(UInt<1>("h01"), _T_1456) @[package.scala 49:27] + node _T_1463 = and(_T_1455, _T_1462) @[package.scala 50:38] + node _T_1464 = or(_T_1453, _T_1463) @[package.scala 50:29] + node _T_1465 = bits(_T_1451, 1, 1) @[package.scala 44:26] + node _T_1466 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[package.scala 46:20] + node _T_1469 = and(_T_1459, _T_1468) @[package.scala 49:27] + node _T_1470 = and(_T_1465, _T_1469) @[package.scala 50:38] + node _T_1471 = or(_T_1461, _T_1470) @[package.scala 50:29] + node _T_1472 = and(_T_1459, _T_1466) @[package.scala 49:27] + node _T_1473 = and(_T_1465, _T_1472) @[package.scala 50:38] + node _T_1474 = or(_T_1461, _T_1473) @[package.scala 50:29] + node _T_1475 = and(_T_1462, _T_1468) @[package.scala 49:27] + node _T_1476 = and(_T_1465, _T_1475) @[package.scala 50:38] + node _T_1477 = or(_T_1464, _T_1476) @[package.scala 50:29] + node _T_1478 = and(_T_1462, _T_1466) @[package.scala 49:27] + node _T_1479 = and(_T_1465, _T_1478) @[package.scala 50:38] + node _T_1480 = or(_T_1464, _T_1479) @[package.scala 50:29] + node _T_1481 = bits(_T_1451, 0, 0) @[package.scala 44:26] + node _T_1482 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[package.scala 46:20] + node _T_1485 = and(_T_1469, _T_1484) @[package.scala 49:27] + node _T_1486 = and(_T_1481, _T_1485) @[package.scala 50:38] + node _T_1487 = or(_T_1471, _T_1486) @[package.scala 50:29] + node _T_1488 = and(_T_1469, _T_1482) @[package.scala 49:27] + node _T_1489 = and(_T_1481, _T_1488) @[package.scala 50:38] + node _T_1490 = or(_T_1471, _T_1489) @[package.scala 50:29] + node _T_1491 = and(_T_1472, _T_1484) @[package.scala 49:27] + node _T_1492 = and(_T_1481, _T_1491) @[package.scala 50:38] + node _T_1493 = or(_T_1474, _T_1492) @[package.scala 50:29] + node _T_1494 = and(_T_1472, _T_1482) @[package.scala 49:27] + node _T_1495 = and(_T_1481, _T_1494) @[package.scala 50:38] + node _T_1496 = or(_T_1474, _T_1495) @[package.scala 50:29] + node _T_1497 = and(_T_1475, _T_1484) @[package.scala 49:27] + node _T_1498 = and(_T_1481, _T_1497) @[package.scala 50:38] + node _T_1499 = or(_T_1477, _T_1498) @[package.scala 50:29] + node _T_1500 = and(_T_1475, _T_1482) @[package.scala 49:27] + node _T_1501 = and(_T_1481, _T_1500) @[package.scala 50:38] + node _T_1502 = or(_T_1477, _T_1501) @[package.scala 50:29] + node _T_1503 = and(_T_1478, _T_1484) @[package.scala 49:27] + node _T_1504 = and(_T_1481, _T_1503) @[package.scala 50:38] + node _T_1505 = or(_T_1480, _T_1504) @[package.scala 50:29] + node _T_1506 = and(_T_1478, _T_1482) @[package.scala 49:27] + node _T_1507 = and(_T_1481, _T_1506) @[package.scala 50:38] + node _T_1508 = or(_T_1480, _T_1507) @[package.scala 50:29] + node _T_1509 = cat(_T_1490, _T_1487) @[Cat.scala 30:58] + node _T_1510 = cat(_T_1496, _T_1493) @[Cat.scala 30:58] + node _T_1511 = cat(_T_1510, _T_1509) @[Cat.scala 30:58] + node _T_1512 = cat(_T_1502, _T_1499) @[Cat.scala 30:58] + node _T_1513 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1514 = cat(_T_1513, _T_1512) @[Cat.scala 30:58] + node _T_1515 = cat(_T_1514, _T_1511) @[Cat.scala 30:58] + node _T_1517 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + when _T_1517 : @[Periphery.scala 219:36] + node _T_1519 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1521 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1522 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1524 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1526 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_1527 = or(_T_1526, reset) @[Periphery.scala 219:36] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1529 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1530 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1532 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1534 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1535 = or(_T_1534, reset) @[Periphery.scala 219:36] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1537 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:219:36)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1538 = not(io.in[0].b.bits.mask) @[Periphery.scala 219:36] + node _T_1540 = eq(_T_1538, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1541 = or(_T_1540, reset) @[Periphery.scala 219:36] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1543 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1545 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 219:36] + when _T_1545 : @[Periphery.scala 219:36] + node _T_1547 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1549 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1550 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1552 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1553 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1555 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1557 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1558 = or(_T_1557, reset) @[Periphery.scala 219:36] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1560 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1561 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 219:36] + node _T_1562 = or(_T_1561, reset) @[Periphery.scala 219:36] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1564 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1566 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1566 : @[Periphery.scala 219:36] + node _T_1568 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1570 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1571 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1573 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1574 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1576 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1578 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 219:36] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1581 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1582 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 219:36] + node _T_1583 = or(_T_1582, reset) @[Periphery.scala 219:36] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1585 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1587 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 219:36] + when _T_1587 : @[Periphery.scala 219:36] + node _T_1589 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1591 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1592 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1594 = eq(_T_1592, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1594 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1595 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1597 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1599 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1600 = or(_T_1599, reset) @[Periphery.scala 219:36] + node _T_1602 = eq(_T_1600, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1602 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1603 = not(_T_1515) @[Periphery.scala 219:36] + node _T_1604 = and(io.in[0].b.bits.mask, _T_1603) @[Periphery.scala 219:36] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1607 = or(_T_1606, reset) @[Periphery.scala 219:36] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1609 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1611 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 219:36] + when _T_1611 : @[Periphery.scala 219:36] + node _T_1613 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1615 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1616 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1618 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1619 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1621 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1623 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1624 = or(_T_1623, reset) @[Periphery.scala 219:36] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1626 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:219:36)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1627 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 219:36] + node _T_1628 = or(_T_1627, reset) @[Periphery.scala 219:36] + node _T_1630 = eq(_T_1628, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1630 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1632 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 219:36] + when _T_1632 : @[Periphery.scala 219:36] + node _T_1634 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1636 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1637 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1639 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1640 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1642 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1644 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1645 = or(_T_1644, reset) @[Periphery.scala 219:36] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1647 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:219:36)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1648 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 219:36] + node _T_1649 = or(_T_1648, reset) @[Periphery.scala 219:36] + node _T_1651 = eq(_T_1649, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1651 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1653 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 219:36] + when _T_1653 : @[Periphery.scala 219:36] + node _T_1655 = or(UInt<1>("h00"), reset) @[Periphery.scala 219:36] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1657 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:219:36)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1658 = or(_T_1439, reset) @[Periphery.scala 219:36] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1660 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1661 = or(_T_1447, reset) @[Periphery.scala 219:36] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1663 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1664 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 219:36] + node _T_1665 = or(_T_1664, reset) @[Periphery.scala 219:36] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1667 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:219:36)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + when io.in[0].c.valid : @[Periphery.scala 219:36] + node _T_1669 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1670 = or(_T_1669, reset) @[Periphery.scala 219:36] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1672 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:219:36)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1674 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1675 = not(_T_1674) @[Parameters.scala 37:9] + node _T_1677 = or(_T_1675, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_1678 = not(_T_1677) @[Parameters.scala 37:7] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1683 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1683 is invalid @[Parameters.scala 228:27] + _T_1683[0] <= _T_1680 @[Parameters.scala 228:27] + node _T_1688 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1689 = dshl(_T_1688, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1690 = bits(_T_1689, 7, 0) @[package.scala 19:76] + node _T_1691 = not(_T_1690) @[package.scala 19:40] + node _T_1692 = and(io.in[0].c.bits.address, _T_1691) @[Edges.scala 17:16] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1696 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1697 = cvt(_T_1696) @[Parameters.scala 117:49] + node _T_1699 = and(_T_1697, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1700 = asSInt(_T_1699) @[Parameters.scala 117:52] + node _T_1702 = eq(_T_1700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1704 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1705 = cvt(_T_1704) @[Parameters.scala 117:49] + node _T_1707 = and(_T_1705, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1708 = asSInt(_T_1707) @[Parameters.scala 117:52] + node _T_1710 = eq(_T_1708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1712 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1713 = cvt(_T_1712) @[Parameters.scala 117:49] + node _T_1715 = and(_T_1713, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1716 = asSInt(_T_1715) @[Parameters.scala 117:52] + node _T_1718 = eq(_T_1716, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1720 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1721 = cvt(_T_1720) @[Parameters.scala 117:49] + node _T_1723 = and(_T_1721, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1724 = asSInt(_T_1723) @[Parameters.scala 117:52] + node _T_1726 = eq(_T_1724, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1728 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1729 = cvt(_T_1728) @[Parameters.scala 117:49] + node _T_1731 = and(_T_1729, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1732 = asSInt(_T_1731) @[Parameters.scala 117:52] + node _T_1734 = eq(_T_1732, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1736 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1737 = cvt(_T_1736) @[Parameters.scala 117:49] + node _T_1739 = and(_T_1737, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1740 = asSInt(_T_1739) @[Parameters.scala 117:52] + node _T_1742 = eq(_T_1740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1744 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1745 = cvt(_T_1744) @[Parameters.scala 117:49] + node _T_1747 = and(_T_1745, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1748 = asSInt(_T_1747) @[Parameters.scala 117:52] + node _T_1750 = eq(_T_1748, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1753 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1753 is invalid @[Parameters.scala 110:36] + _T_1753[0] <= _T_1702 @[Parameters.scala 110:36] + _T_1753[1] <= _T_1710 @[Parameters.scala 110:36] + _T_1753[2] <= _T_1718 @[Parameters.scala 110:36] + _T_1753[3] <= _T_1726 @[Parameters.scala 110:36] + _T_1753[4] <= _T_1734 @[Parameters.scala 110:36] + _T_1753[5] <= _T_1742 @[Parameters.scala 110:36] + _T_1753[6] <= _T_1750 @[Parameters.scala 110:36] + node _T_1763 = or(_T_1753[0], _T_1753[1]) @[Parameters.scala 119:64] + node _T_1764 = or(_T_1763, _T_1753[2]) @[Parameters.scala 119:64] + node _T_1765 = or(_T_1764, _T_1753[3]) @[Parameters.scala 119:64] + node _T_1766 = or(_T_1765, _T_1753[4]) @[Parameters.scala 119:64] + node _T_1767 = or(_T_1766, _T_1753[5]) @[Parameters.scala 119:64] + node _T_1768 = or(_T_1767, _T_1753[6]) @[Parameters.scala 119:64] + node _T_1770 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 219:36] + when _T_1770 : @[Periphery.scala 219:36] + node _T_1771 = or(_T_1768, reset) @[Periphery.scala 219:36] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1773 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1774 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1776 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1778 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_1779 = or(_T_1778, reset) @[Periphery.scala 219:36] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1781 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1782 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1784 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1786 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1787 = or(_T_1786, reset) @[Periphery.scala 219:36] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1789 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:219:36)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1791 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1792 = or(_T_1791, reset) @[Periphery.scala 219:36] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1794 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1796 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 219:36] + when _T_1796 : @[Periphery.scala 219:36] + node _T_1797 = or(_T_1768, reset) @[Periphery.scala 219:36] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1799 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1800 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1802 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1804 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_1805 = or(_T_1804, reset) @[Periphery.scala 219:36] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1807 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1808 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1810 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1812 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1813 = or(_T_1812, reset) @[Periphery.scala 219:36] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1815 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:219:36)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1817 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1818 = or(_T_1817, reset) @[Periphery.scala 219:36] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1820 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1822 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + when _T_1822 : @[Periphery.scala 219:36] + node _T_1825 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1827 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1828 = and(_T_1825, _T_1827) @[Parameters.scala 63:37] + node _T_1829 = or(UInt<1>("h00"), _T_1828) @[Parameters.scala 132:31] + node _T_1831 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1832 = cvt(_T_1831) @[Parameters.scala 117:49] + node _T_1834 = and(_T_1832, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1835 = asSInt(_T_1834) @[Parameters.scala 117:52] + node _T_1837 = eq(_T_1835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1839 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1840 = cvt(_T_1839) @[Parameters.scala 117:49] + node _T_1842 = and(_T_1840, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1843 = asSInt(_T_1842) @[Parameters.scala 117:52] + node _T_1845 = eq(_T_1843, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1846 = or(_T_1837, _T_1845) @[Parameters.scala 133:42] + node _T_1847 = and(_T_1829, _T_1846) @[Parameters.scala 132:56] + node _T_1850 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1852 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1853 = cvt(_T_1852) @[Parameters.scala 117:49] + node _T_1855 = and(_T_1853, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1856 = asSInt(_T_1855) @[Parameters.scala 117:52] + node _T_1858 = eq(_T_1856, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1860 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1861 = cvt(_T_1860) @[Parameters.scala 117:49] + node _T_1863 = and(_T_1861, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1864 = asSInt(_T_1863) @[Parameters.scala 117:52] + node _T_1866 = eq(_T_1864, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1868 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1869 = cvt(_T_1868) @[Parameters.scala 117:49] + node _T_1871 = and(_T_1869, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1872 = asSInt(_T_1871) @[Parameters.scala 117:52] + node _T_1874 = eq(_T_1872, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1876 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1877 = cvt(_T_1876) @[Parameters.scala 117:49] + node _T_1879 = and(_T_1877, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1880 = asSInt(_T_1879) @[Parameters.scala 117:52] + node _T_1882 = eq(_T_1880, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1883 = or(_T_1858, _T_1866) @[Parameters.scala 133:42] + node _T_1884 = or(_T_1883, _T_1874) @[Parameters.scala 133:42] + node _T_1885 = or(_T_1884, _T_1882) @[Parameters.scala 133:42] + node _T_1886 = and(_T_1850, _T_1885) @[Parameters.scala 132:56] + node _T_1888 = or(UInt<1>("h00"), _T_1847) @[Parameters.scala 134:30] + node _T_1889 = or(_T_1888, _T_1886) @[Parameters.scala 134:30] + node _T_1890 = or(_T_1889, reset) @[Periphery.scala 219:36] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1892 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1893 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1895 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1897 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_1898 = or(_T_1897, reset) @[Periphery.scala 219:36] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1900 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1901 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1903 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1905 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1906 = or(_T_1905, reset) @[Periphery.scala 219:36] + node _T_1908 = eq(_T_1906, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1908 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:219:36)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1910 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_1911 = or(_T_1910, reset) @[Periphery.scala 219:36] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1913 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1915 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 219:36] + when _T_1915 : @[Periphery.scala 219:36] + node _T_1918 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1920 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1921 = and(_T_1918, _T_1920) @[Parameters.scala 63:37] + node _T_1922 = or(UInt<1>("h00"), _T_1921) @[Parameters.scala 132:31] + node _T_1924 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1925 = cvt(_T_1924) @[Parameters.scala 117:49] + node _T_1927 = and(_T_1925, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1928 = asSInt(_T_1927) @[Parameters.scala 117:52] + node _T_1930 = eq(_T_1928, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1932 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1933 = cvt(_T_1932) @[Parameters.scala 117:49] + node _T_1935 = and(_T_1933, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1936 = asSInt(_T_1935) @[Parameters.scala 117:52] + node _T_1938 = eq(_T_1936, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1939 = or(_T_1930, _T_1938) @[Parameters.scala 133:42] + node _T_1940 = and(_T_1922, _T_1939) @[Parameters.scala 132:56] + node _T_1943 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1945 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1946 = cvt(_T_1945) @[Parameters.scala 117:49] + node _T_1948 = and(_T_1946, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1949 = asSInt(_T_1948) @[Parameters.scala 117:52] + node _T_1951 = eq(_T_1949, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1953 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1954 = cvt(_T_1953) @[Parameters.scala 117:49] + node _T_1956 = and(_T_1954, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1957 = asSInt(_T_1956) @[Parameters.scala 117:52] + node _T_1959 = eq(_T_1957, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1961 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1962 = cvt(_T_1961) @[Parameters.scala 117:49] + node _T_1964 = and(_T_1962, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1965 = asSInt(_T_1964) @[Parameters.scala 117:52] + node _T_1967 = eq(_T_1965, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1969 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1970 = cvt(_T_1969) @[Parameters.scala 117:49] + node _T_1972 = and(_T_1970, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1973 = asSInt(_T_1972) @[Parameters.scala 117:52] + node _T_1975 = eq(_T_1973, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = or(_T_1951, _T_1959) @[Parameters.scala 133:42] + node _T_1977 = or(_T_1976, _T_1967) @[Parameters.scala 133:42] + node _T_1978 = or(_T_1977, _T_1975) @[Parameters.scala 133:42] + node _T_1979 = and(_T_1943, _T_1978) @[Parameters.scala 132:56] + node _T_1981 = or(UInt<1>("h00"), _T_1940) @[Parameters.scala 134:30] + node _T_1982 = or(_T_1981, _T_1979) @[Parameters.scala 134:30] + node _T_1983 = or(_T_1982, reset) @[Periphery.scala 219:36] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1985 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:219:36)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1986 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1988 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1990 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_1991 = or(_T_1990, reset) @[Periphery.scala 219:36] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1993 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1994 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_1996 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_1998 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1999 = or(_T_1998, reset) @[Periphery.scala 219:36] + node _T_2001 = eq(_T_1999, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2001 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:219:36)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2003 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2004 = or(_T_2003, reset) @[Periphery.scala 219:36] + node _T_2006 = eq(_T_2004, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2006 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2008 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2008 : @[Periphery.scala 219:36] + node _T_2009 = or(_T_1768, reset) @[Periphery.scala 219:36] + node _T_2011 = eq(_T_2009, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2011 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2012 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_2014 = eq(_T_2012, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2014 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2015 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2017 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2019 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2020 = or(_T_2019, reset) @[Periphery.scala 219:36] + node _T_2022 = eq(_T_2020, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2022 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2024 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 219:36] + when _T_2024 : @[Periphery.scala 219:36] + node _T_2025 = or(_T_1768, reset) @[Periphery.scala 219:36] + node _T_2027 = eq(_T_2025, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2027 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2028 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2030 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2031 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2033 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2035 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2036 = or(_T_2035, reset) @[Periphery.scala 219:36] + node _T_2038 = eq(_T_2036, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2038 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2040 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 219:36] + when _T_2040 : @[Periphery.scala 219:36] + node _T_2041 = or(_T_1768, reset) @[Periphery.scala 219:36] + node _T_2043 = eq(_T_2041, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2043 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:219:36)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2044 = or(_T_1683[0], reset) @[Periphery.scala 219:36] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2046 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2047 = or(_T_1694, reset) @[Periphery.scala 219:36] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2049 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2051 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2052 = or(_T_2051, reset) @[Periphery.scala 219:36] + node _T_2054 = eq(_T_2052, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2054 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2056 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2057 = or(_T_2056, reset) @[Periphery.scala 219:36] + node _T_2059 = eq(_T_2057, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2059 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + when io.in[0].d.valid : @[Periphery.scala 219:36] + node _T_2061 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2062 = or(_T_2061, reset) @[Periphery.scala 219:36] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2064 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:219:36)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2066 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_2067 = not(_T_2066) @[Parameters.scala 37:9] + node _T_2069 = or(_T_2067, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_2070 = not(_T_2069) @[Parameters.scala 37:7] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2075 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2075 is invalid @[Parameters.scala 228:27] + _T_2075[0] <= _T_2072 @[Parameters.scala 228:27] + node _T_2080 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2081 = dshl(_T_2080, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2082 = bits(_T_2081, 7, 0) @[package.scala 19:76] + node _T_2083 = not(_T_2082) @[package.scala 19:40] + node _T_2084 = and(io.in[0].d.bits.addr_lo, _T_2083) @[Edges.scala 17:16] + node _T_2086 = eq(_T_2084, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2088 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[Periphery.scala 219:36] + node _T_2090 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + when _T_2090 : @[Periphery.scala 219:36] + node _T_2091 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2093 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2094 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2096 = eq(_T_2094, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2096 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2097 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2099 = eq(_T_2097, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2099 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2101 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_2102 = or(_T_2101, reset) @[Periphery.scala 219:36] + node _T_2104 = eq(_T_2102, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2104 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2106 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2107 = or(_T_2106, reset) @[Periphery.scala 219:36] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2109 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2111 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2112 = or(_T_2111, reset) @[Periphery.scala 219:36] + node _T_2114 = eq(_T_2112, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2114 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2116 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 219:36] + when _T_2116 : @[Periphery.scala 219:36] + node _T_2117 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2119 = eq(_T_2117, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2119 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2120 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2122 = eq(_T_2120, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2122 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2123 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2125 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2127 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_2128 = or(_T_2127, reset) @[Periphery.scala 219:36] + node _T_2130 = eq(_T_2128, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2130 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2132 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2133 = or(_T_2132, reset) @[Periphery.scala 219:36] + node _T_2135 = eq(_T_2133, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2135 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:219:36)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2137 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 219:36] + when _T_2137 : @[Periphery.scala 219:36] + node _T_2138 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2140 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2141 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2143 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2144 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2146 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2148 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 219:36] + node _T_2149 = or(_T_2148, reset) @[Periphery.scala 219:36] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2151 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:219:36)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2153 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2154 = or(_T_2153, reset) @[Periphery.scala 219:36] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2156 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:219:36)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2158 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2158 : @[Periphery.scala 219:36] + node _T_2159 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2161 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2162 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2164 = eq(_T_2162, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2164 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2165 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2167 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2169 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2170 = or(_T_2169, reset) @[Periphery.scala 219:36] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2172 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2174 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 219:36] + when _T_2174 : @[Periphery.scala 219:36] + node _T_2175 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2177 = eq(_T_2175, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2177 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2178 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2180 = eq(_T_2178, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2180 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2181 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2183 = eq(_T_2181, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2183 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2185 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2186 = or(_T_2185, reset) @[Periphery.scala 219:36] + node _T_2188 = eq(_T_2186, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2188 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2190 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 219:36] + when _T_2190 : @[Periphery.scala 219:36] + node _T_2191 = or(_T_2075[0], reset) @[Periphery.scala 219:36] + node _T_2193 = eq(_T_2191, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2193 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2194 = or(_T_2086, reset) @[Periphery.scala 219:36] + node _T_2196 = eq(_T_2194, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2196 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:219:36)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2197 = or(_T_2088, reset) @[Periphery.scala 219:36] + node _T_2199 = eq(_T_2197, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2199 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2201 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2202 = or(_T_2201, reset) @[Periphery.scala 219:36] + node _T_2204 = eq(_T_2202, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2204 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:219:36)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2206 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2207 = or(_T_2206, reset) @[Periphery.scala 219:36] + node _T_2209 = eq(_T_2207, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2209 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:219:36)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + when io.in[0].e.valid : @[Periphery.scala 219:36] + node _T_2211 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[Periphery.scala 219:36] + node _T_2212 = or(_T_2211, reset) @[Periphery.scala 219:36] + node _T_2214 = eq(_T_2212, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2214 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:219:36)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2215 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2217 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2218 = dshl(_T_2217, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2219 = bits(_T_2218, 7, 0) @[package.scala 19:76] + node _T_2220 = not(_T_2219) @[package.scala 19:40] + node _T_2221 = shr(_T_2220, 3) @[Edges.scala 198:59] + node _T_2222 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2224 = eq(_T_2222, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2226 = mux(_T_2224, _T_2221, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2228 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2230 = sub(_T_2228, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2231 = asUInt(_T_2230) @[Edges.scala 208:28] + node _T_2232 = tail(_T_2231, 1) @[Edges.scala 208:28] + node _T_2234 = eq(_T_2228, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2236 = eq(_T_2228, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2238 = eq(_T_2226, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2239 = or(_T_2236, _T_2238) @[Edges.scala 210:37] + node _T_2240 = and(_T_2239, _T_2215) @[Edges.scala 211:22] + node _T_2241 = not(_T_2232) @[Edges.scala 212:27] + node _T_2242 = and(_T_2226, _T_2241) @[Edges.scala 212:25] + when _T_2215 : @[Edges.scala 213:17] + node _T_2243 = mux(_T_2234, _T_2226, _T_2232) @[Edges.scala 214:21] + _T_2228 <= _T_2243 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2245 : UInt, clock @[Periphery.scala 219:36] + reg _T_2247 : UInt, clock @[Periphery.scala 219:36] + reg _T_2249 : UInt, clock @[Periphery.scala 219:36] + reg _T_2251 : UInt, clock @[Periphery.scala 219:36] + reg _T_2253 : UInt, clock @[Periphery.scala 219:36] + node _T_2255 = eq(_T_2234, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2256 = and(io.in[0].a.valid, _T_2255) @[Periphery.scala 219:36] + when _T_2256 : @[Periphery.scala 219:36] + node _T_2257 = eq(io.in[0].a.bits.opcode, _T_2245) @[Periphery.scala 219:36] + node _T_2258 = or(_T_2257, reset) @[Periphery.scala 219:36] + node _T_2260 = eq(_T_2258, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2260 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2261 = eq(io.in[0].a.bits.param, _T_2247) @[Periphery.scala 219:36] + node _T_2262 = or(_T_2261, reset) @[Periphery.scala 219:36] + node _T_2264 = eq(_T_2262, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2264 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2265 = eq(io.in[0].a.bits.size, _T_2249) @[Periphery.scala 219:36] + node _T_2266 = or(_T_2265, reset) @[Periphery.scala 219:36] + node _T_2268 = eq(_T_2266, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2268 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2269 = eq(io.in[0].a.bits.source, _T_2251) @[Periphery.scala 219:36] + node _T_2270 = or(_T_2269, reset) @[Periphery.scala 219:36] + node _T_2272 = eq(_T_2270, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2272 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2273 = eq(io.in[0].a.bits.address, _T_2253) @[Periphery.scala 219:36] + node _T_2274 = or(_T_2273, reset) @[Periphery.scala 219:36] + node _T_2276 = eq(_T_2274, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2276 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2277 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2278 = and(_T_2277, _T_2234) @[Periphery.scala 219:36] + when _T_2278 : @[Periphery.scala 219:36] + _T_2245 <= io.in[0].a.bits.opcode @[Periphery.scala 219:36] + _T_2247 <= io.in[0].a.bits.param @[Periphery.scala 219:36] + _T_2249 <= io.in[0].a.bits.size @[Periphery.scala 219:36] + _T_2251 <= io.in[0].a.bits.source @[Periphery.scala 219:36] + _T_2253 <= io.in[0].a.bits.address @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2279 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2281 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2282 = dshl(_T_2281, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2283 = bits(_T_2282, 7, 0) @[package.scala 19:76] + node _T_2284 = not(_T_2283) @[package.scala 19:40] + node _T_2285 = shr(_T_2284, 3) @[Edges.scala 198:59] + node _T_2286 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2288 = eq(_T_2286, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2291 = mux(UInt<1>("h00"), _T_2285, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2293 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2295 = sub(_T_2293, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2296 = asUInt(_T_2295) @[Edges.scala 208:28] + node _T_2297 = tail(_T_2296, 1) @[Edges.scala 208:28] + node _T_2299 = eq(_T_2293, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2301 = eq(_T_2293, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2303 = eq(_T_2291, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2304 = or(_T_2301, _T_2303) @[Edges.scala 210:37] + node _T_2305 = and(_T_2304, _T_2279) @[Edges.scala 211:22] + node _T_2306 = not(_T_2297) @[Edges.scala 212:27] + node _T_2307 = and(_T_2291, _T_2306) @[Edges.scala 212:25] + when _T_2279 : @[Edges.scala 213:17] + node _T_2308 = mux(_T_2299, _T_2291, _T_2297) @[Edges.scala 214:21] + _T_2293 <= _T_2308 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2310 : UInt, clock @[Periphery.scala 219:36] + reg _T_2312 : UInt, clock @[Periphery.scala 219:36] + reg _T_2314 : UInt, clock @[Periphery.scala 219:36] + reg _T_2316 : UInt, clock @[Periphery.scala 219:36] + reg _T_2318 : UInt, clock @[Periphery.scala 219:36] + node _T_2320 = eq(_T_2299, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2321 = and(io.in[0].b.valid, _T_2320) @[Periphery.scala 219:36] + when _T_2321 : @[Periphery.scala 219:36] + node _T_2322 = eq(io.in[0].b.bits.opcode, _T_2310) @[Periphery.scala 219:36] + node _T_2323 = or(_T_2322, reset) @[Periphery.scala 219:36] + node _T_2325 = eq(_T_2323, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2325 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2326 = eq(io.in[0].b.bits.param, _T_2312) @[Periphery.scala 219:36] + node _T_2327 = or(_T_2326, reset) @[Periphery.scala 219:36] + node _T_2329 = eq(_T_2327, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2329 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2330 = eq(io.in[0].b.bits.size, _T_2314) @[Periphery.scala 219:36] + node _T_2331 = or(_T_2330, reset) @[Periphery.scala 219:36] + node _T_2333 = eq(_T_2331, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2333 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2334 = eq(io.in[0].b.bits.source, _T_2316) @[Periphery.scala 219:36] + node _T_2335 = or(_T_2334, reset) @[Periphery.scala 219:36] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2337 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2338 = eq(io.in[0].b.bits.address, _T_2318) @[Periphery.scala 219:36] + node _T_2339 = or(_T_2338, reset) @[Periphery.scala 219:36] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2341 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2342 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2343 = and(_T_2342, _T_2299) @[Periphery.scala 219:36] + when _T_2343 : @[Periphery.scala 219:36] + _T_2310 <= io.in[0].b.bits.opcode @[Periphery.scala 219:36] + _T_2312 <= io.in[0].b.bits.param @[Periphery.scala 219:36] + _T_2314 <= io.in[0].b.bits.size @[Periphery.scala 219:36] + _T_2316 <= io.in[0].b.bits.source @[Periphery.scala 219:36] + _T_2318 <= io.in[0].b.bits.address @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2344 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2346 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2347 = dshl(_T_2346, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2348 = bits(_T_2347, 7, 0) @[package.scala 19:76] + node _T_2349 = not(_T_2348) @[package.scala 19:40] + node _T_2350 = shr(_T_2349, 3) @[Edges.scala 198:59] + node _T_2351 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2354 = mux(UInt<1>("h00"), _T_2350, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2356 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2358 = sub(_T_2356, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2359 = asUInt(_T_2358) @[Edges.scala 208:28] + node _T_2360 = tail(_T_2359, 1) @[Edges.scala 208:28] + node _T_2362 = eq(_T_2356, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2364 = eq(_T_2356, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2366 = eq(_T_2354, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2367 = or(_T_2364, _T_2366) @[Edges.scala 210:37] + node _T_2368 = and(_T_2367, _T_2344) @[Edges.scala 211:22] + node _T_2369 = not(_T_2360) @[Edges.scala 212:27] + node _T_2370 = and(_T_2354, _T_2369) @[Edges.scala 212:25] + when _T_2344 : @[Edges.scala 213:17] + node _T_2371 = mux(_T_2362, _T_2354, _T_2360) @[Edges.scala 214:21] + _T_2356 <= _T_2371 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2373 : UInt, clock @[Periphery.scala 219:36] + reg _T_2375 : UInt, clock @[Periphery.scala 219:36] + reg _T_2377 : UInt, clock @[Periphery.scala 219:36] + reg _T_2379 : UInt, clock @[Periphery.scala 219:36] + reg _T_2381 : UInt, clock @[Periphery.scala 219:36] + node _T_2383 = eq(_T_2362, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2384 = and(io.in[0].c.valid, _T_2383) @[Periphery.scala 219:36] + when _T_2384 : @[Periphery.scala 219:36] + node _T_2385 = eq(io.in[0].c.bits.opcode, _T_2373) @[Periphery.scala 219:36] + node _T_2386 = or(_T_2385, reset) @[Periphery.scala 219:36] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2388 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2389 = eq(io.in[0].c.bits.param, _T_2375) @[Periphery.scala 219:36] + node _T_2390 = or(_T_2389, reset) @[Periphery.scala 219:36] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2392 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2393 = eq(io.in[0].c.bits.size, _T_2377) @[Periphery.scala 219:36] + node _T_2394 = or(_T_2393, reset) @[Periphery.scala 219:36] + node _T_2396 = eq(_T_2394, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2396 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2397 = eq(io.in[0].c.bits.source, _T_2379) @[Periphery.scala 219:36] + node _T_2398 = or(_T_2397, reset) @[Periphery.scala 219:36] + node _T_2400 = eq(_T_2398, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2400 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2401 = eq(io.in[0].c.bits.address, _T_2381) @[Periphery.scala 219:36] + node _T_2402 = or(_T_2401, reset) @[Periphery.scala 219:36] + node _T_2404 = eq(_T_2402, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2404 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2405 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2406 = and(_T_2405, _T_2362) @[Periphery.scala 219:36] + when _T_2406 : @[Periphery.scala 219:36] + _T_2373 <= io.in[0].c.bits.opcode @[Periphery.scala 219:36] + _T_2375 <= io.in[0].c.bits.param @[Periphery.scala 219:36] + _T_2377 <= io.in[0].c.bits.size @[Periphery.scala 219:36] + _T_2379 <= io.in[0].c.bits.source @[Periphery.scala 219:36] + _T_2381 <= io.in[0].c.bits.address @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2407 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2409 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2410 = dshl(_T_2409, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2411 = bits(_T_2410, 7, 0) @[package.scala 19:76] + node _T_2412 = not(_T_2411) @[package.scala 19:40] + node _T_2413 = shr(_T_2412, 3) @[Edges.scala 198:59] + node _T_2414 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2416 = mux(_T_2414, _T_2413, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2418 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2420 = sub(_T_2418, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2421 = asUInt(_T_2420) @[Edges.scala 208:28] + node _T_2422 = tail(_T_2421, 1) @[Edges.scala 208:28] + node _T_2424 = eq(_T_2418, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2426 = eq(_T_2418, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2428 = eq(_T_2416, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2429 = or(_T_2426, _T_2428) @[Edges.scala 210:37] + node _T_2430 = and(_T_2429, _T_2407) @[Edges.scala 211:22] + node _T_2431 = not(_T_2422) @[Edges.scala 212:27] + node _T_2432 = and(_T_2416, _T_2431) @[Edges.scala 212:25] + when _T_2407 : @[Edges.scala 213:17] + node _T_2433 = mux(_T_2424, _T_2416, _T_2422) @[Edges.scala 214:21] + _T_2418 <= _T_2433 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2435 : UInt, clock @[Periphery.scala 219:36] + reg _T_2437 : UInt, clock @[Periphery.scala 219:36] + reg _T_2439 : UInt, clock @[Periphery.scala 219:36] + reg _T_2441 : UInt, clock @[Periphery.scala 219:36] + reg _T_2443 : UInt, clock @[Periphery.scala 219:36] + reg _T_2445 : UInt, clock @[Periphery.scala 219:36] + node _T_2447 = eq(_T_2424, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2448 = and(io.in[0].d.valid, _T_2447) @[Periphery.scala 219:36] + when _T_2448 : @[Periphery.scala 219:36] + node _T_2449 = eq(io.in[0].d.bits.opcode, _T_2435) @[Periphery.scala 219:36] + node _T_2450 = or(_T_2449, reset) @[Periphery.scala 219:36] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2452 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2453 = eq(io.in[0].d.bits.param, _T_2437) @[Periphery.scala 219:36] + node _T_2454 = or(_T_2453, reset) @[Periphery.scala 219:36] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2456 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2457 = eq(io.in[0].d.bits.size, _T_2439) @[Periphery.scala 219:36] + node _T_2458 = or(_T_2457, reset) @[Periphery.scala 219:36] + node _T_2460 = eq(_T_2458, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2460 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2461 = eq(io.in[0].d.bits.source, _T_2441) @[Periphery.scala 219:36] + node _T_2462 = or(_T_2461, reset) @[Periphery.scala 219:36] + node _T_2464 = eq(_T_2462, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2464 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2465 = eq(io.in[0].d.bits.sink, _T_2443) @[Periphery.scala 219:36] + node _T_2466 = or(_T_2465, reset) @[Periphery.scala 219:36] + node _T_2468 = eq(_T_2466, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2468 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2469 = eq(io.in[0].d.bits.addr_lo, _T_2445) @[Periphery.scala 219:36] + node _T_2470 = or(_T_2469, reset) @[Periphery.scala 219:36] + node _T_2472 = eq(_T_2470, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2472 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:219:36)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2473 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2474 = and(_T_2473, _T_2424) @[Periphery.scala 219:36] + when _T_2474 : @[Periphery.scala 219:36] + _T_2435 <= io.in[0].d.bits.opcode @[Periphery.scala 219:36] + _T_2437 <= io.in[0].d.bits.param @[Periphery.scala 219:36] + _T_2439 <= io.in[0].d.bits.size @[Periphery.scala 219:36] + _T_2441 <= io.in[0].d.bits.source @[Periphery.scala 219:36] + _T_2443 <= io.in[0].d.bits.sink @[Periphery.scala 219:36] + _T_2445 <= io.in[0].d.bits.addr_lo @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + reg _T_2476 : UInt<512>, clock with : (reset => (reset, UInt<512>("h00"))) @[Reg.scala 26:44] + node _T_2477 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2479 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2480 = dshl(_T_2479, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2481 = bits(_T_2480, 7, 0) @[package.scala 19:76] + node _T_2482 = not(_T_2481) @[package.scala 19:40] + node _T_2483 = shr(_T_2482, 3) @[Edges.scala 198:59] + node _T_2484 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2486 = eq(_T_2484, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2488 = mux(_T_2486, _T_2483, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2490 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2492 = sub(_T_2490, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2493 = asUInt(_T_2492) @[Edges.scala 208:28] + node _T_2494 = tail(_T_2493, 1) @[Edges.scala 208:28] + node _T_2496 = eq(_T_2490, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2498 = eq(_T_2490, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2500 = eq(_T_2488, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2501 = or(_T_2498, _T_2500) @[Edges.scala 210:37] + node _T_2502 = and(_T_2501, _T_2477) @[Edges.scala 211:22] + node _T_2503 = not(_T_2494) @[Edges.scala 212:27] + node _T_2504 = and(_T_2488, _T_2503) @[Edges.scala 212:25] + when _T_2477 : @[Edges.scala 213:17] + node _T_2505 = mux(_T_2496, _T_2488, _T_2494) @[Edges.scala 214:21] + _T_2490 <= _T_2505 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2506 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2509 = dshl(_T_2508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2510 = bits(_T_2509, 7, 0) @[package.scala 19:76] + node _T_2511 = not(_T_2510) @[package.scala 19:40] + node _T_2512 = shr(_T_2511, 3) @[Edges.scala 198:59] + node _T_2513 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2515 = mux(_T_2513, _T_2512, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2517 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2519 = sub(_T_2517, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2520 = asUInt(_T_2519) @[Edges.scala 208:28] + node _T_2521 = tail(_T_2520, 1) @[Edges.scala 208:28] + node _T_2523 = eq(_T_2517, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2525 = eq(_T_2517, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2527 = eq(_T_2515, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2528 = or(_T_2525, _T_2527) @[Edges.scala 210:37] + node _T_2529 = and(_T_2528, _T_2506) @[Edges.scala 211:22] + node _T_2530 = not(_T_2521) @[Edges.scala 212:27] + node _T_2531 = and(_T_2515, _T_2530) @[Edges.scala 212:25] + when _T_2506 : @[Edges.scala 213:17] + node _T_2532 = mux(_T_2523, _T_2515, _T_2521) @[Edges.scala 214:21] + _T_2517 <= _T_2532 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2534 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + node _T_2535 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 219:36] + node _T_2536 = or(_T_2534, _T_2535) @[Periphery.scala 219:36] + node _T_2538 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2539 = or(_T_2536, _T_2538) @[Periphery.scala 219:36] + node _T_2541 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2542 = or(_T_2539, _T_2541) @[Periphery.scala 219:36] + node _T_2543 = or(_T_2542, reset) @[Periphery.scala 219:36] + node _T_2545 = eq(_T_2543, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2545 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:219:36)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + wire _T_2547 : UInt<512> + _T_2547 is invalid + _T_2547 <= UInt<512>("h00") + node _T_2548 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2548 : @[Periphery.scala 219:36] + when _T_2501 : @[Periphery.scala 219:36] + node _T_2550 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2547 <= _T_2550 @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2551 = dshr(_T_2476, io.in[0].a.bits.source) @[Periphery.scala 219:36] + node _T_2552 = bits(_T_2551, 0, 0) @[Periphery.scala 219:36] + node _T_2554 = eq(_T_2552, UInt<1>("h00")) @[Periphery.scala 219:36] + node _T_2555 = or(_T_2554, reset) @[Periphery.scala 219:36] + node _T_2557 = eq(_T_2555, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2557 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:219:36)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + wire _T_2559 : UInt<512> + _T_2559 is invalid + _T_2559 <= UInt<512>("h00") + node _T_2560 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2562 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 219:36] + node _T_2563 = and(_T_2560, _T_2562) @[Periphery.scala 219:36] + when _T_2563 : @[Periphery.scala 219:36] + when _T_2528 : @[Periphery.scala 219:36] + node _T_2565 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2559 <= _T_2565 @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2566 = or(_T_2547, _T_2476) @[Periphery.scala 219:36] + node _T_2567 = dshr(_T_2566, io.in[0].d.bits.source) @[Periphery.scala 219:36] + node _T_2568 = bits(_T_2567, 0, 0) @[Periphery.scala 219:36] + node _T_2569 = or(_T_2568, reset) @[Periphery.scala 219:36] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[Periphery.scala 219:36] + when _T_2571 : @[Periphery.scala 219:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:219:36)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 219:36] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + skip @[Periphery.scala 219:36] + node _T_2572 = or(_T_2476, _T_2547) @[Periphery.scala 219:36] + node _T_2573 = not(_T_2559) @[Periphery.scala 219:36] + node _T_2574 = and(_T_2572, _T_2573) @[Periphery.scala 219:36] + _T_2476 <= _T_2574 @[Periphery.scala 219:36] + + module TLSourceShrinker_l1tol2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + io.out.0.b.ready <= UInt<1>("h01") @[SourceShrinker.scala 33:19] + io.out.0.c.valid <= UInt<1>("h00") @[SourceShrinker.scala 34:19] + io.out.0.e.valid <= UInt<1>("h00") @[SourceShrinker.scala 35:19] + io.in.0.b.valid <= UInt<1>("h00") @[SourceShrinker.scala 36:18] + io.in.0.c.ready <= UInt<1>("h01") @[SourceShrinker.scala 37:18] + io.in.0.e.ready <= UInt<1>("h01") @[SourceShrinker.scala 38:18] + cmem _T_537 : UInt<9>[4] @[SourceShrinker.scala 45:30] + reg _T_539 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_540 = not(_T_539) @[SourceShrinker.scala 47:35] + node _T_541 = shl(_T_540, 1) @[package.scala 25:45] + node _T_542 = bits(_T_541, 3, 0) @[package.scala 25:50] + node _T_543 = or(_T_540, _T_542) @[package.scala 25:40] + node _T_544 = shl(_T_543, 2) @[package.scala 25:45] + node _T_545 = bits(_T_544, 3, 0) @[package.scala 25:50] + node _T_546 = or(_T_543, _T_545) @[package.scala 25:40] + node _T_547 = shl(_T_546, 1) @[SourceShrinker.scala 47:47] + node _T_548 = not(_T_547) @[SourceShrinker.scala 47:26] + node _T_549 = not(_T_539) @[SourceShrinker.scala 47:55] + node _T_550 = and(_T_548, _T_549) @[SourceShrinker.scala 47:53] + node _T_551 = bits(_T_550, 4, 4) @[OneHot.scala 26:18] + node _T_552 = bits(_T_550, 3, 0) @[OneHot.scala 27:18] + node _T_554 = neq(_T_551, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_555 = or(_T_551, _T_552) @[OneHot.scala 28:28] + node _T_556 = bits(_T_555, 3, 2) @[OneHot.scala 26:18] + node _T_557 = bits(_T_555, 1, 0) @[OneHot.scala 27:18] + node _T_559 = neq(_T_556, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_560 = or(_T_556, _T_557) @[OneHot.scala 28:28] + node _T_561 = bits(_T_560, 1, 1) @[CircuitMath.scala 30:8] + node _T_562 = cat(_T_559, _T_561) @[Cat.scala 30:58] + node _T_563 = cat(_T_554, _T_562) @[Cat.scala 30:58] + node _T_564 = not(_T_539) @[SourceShrinker.scala 49:34] + node _T_566 = eq(_T_564, UInt<1>("h00")) @[SourceShrinker.scala 49:34] + node _T_567 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_569 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_570 = dshl(_T_569, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_571 = bits(_T_570, 7, 0) @[package.scala 19:76] + node _T_572 = not(_T_571) @[package.scala 19:40] + node _T_573 = shr(_T_572, 3) @[Edges.scala 198:59] + node _T_574 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_576 = eq(_T_574, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_578 = mux(_T_576, _T_573, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_580 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_582 = sub(_T_580, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_583 = asUInt(_T_582) @[Edges.scala 208:28] + node _T_584 = tail(_T_583, 1) @[Edges.scala 208:28] + node _T_586 = eq(_T_580, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_588 = eq(_T_580, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_590 = eq(_T_578, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_591 = or(_T_588, _T_590) @[Edges.scala 210:37] + node _T_592 = and(_T_591, _T_567) @[Edges.scala 211:22] + node _T_593 = not(_T_584) @[Edges.scala 212:27] + node _T_594 = and(_T_578, _T_593) @[Edges.scala 212:25] + when _T_567 : @[Edges.scala 213:17] + node _T_595 = mux(_T_586, _T_578, _T_584) @[Edges.scala 214:21] + _T_580 <= _T_595 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_596 = and(io.in.0.d.ready, io.in.0.d.valid) @[Decoupled.scala 30:37] + node _T_598 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_599 = dshl(_T_598, io.in.0.d.bits.size) @[package.scala 19:71] + node _T_600 = bits(_T_599, 7, 0) @[package.scala 19:76] + node _T_601 = not(_T_600) @[package.scala 19:40] + node _T_602 = shr(_T_601, 3) @[Edges.scala 198:59] + node _T_603 = bits(io.in.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_605 = mux(_T_603, _T_602, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_607 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_609 = sub(_T_607, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_610 = asUInt(_T_609) @[Edges.scala 208:28] + node _T_611 = tail(_T_610, 1) @[Edges.scala 208:28] + node _T_613 = eq(_T_607, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_615 = eq(_T_607, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_617 = eq(_T_605, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_618 = or(_T_615, _T_617) @[Edges.scala 210:37] + node _T_619 = and(_T_618, _T_596) @[Edges.scala 211:22] + node _T_620 = not(_T_611) @[Edges.scala 212:27] + node _T_621 = and(_T_605, _T_620) @[Edges.scala 212:25] + when _T_596 : @[Edges.scala 213:17] + node _T_622 = mux(_T_613, _T_605, _T_611) @[Edges.scala 214:21] + _T_607 <= _T_622 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_623 = and(_T_586, _T_566) @[SourceShrinker.scala 54:29] + node _T_625 = eq(_T_623, UInt<1>("h00")) @[SourceShrinker.scala 55:38] + node _T_626 = and(io.out.0.a.ready, _T_625) @[SourceShrinker.scala 55:35] + io.in.0.a.ready <= _T_626 @[SourceShrinker.scala 55:20] + node _T_628 = eq(_T_623, UInt<1>("h00")) @[SourceShrinker.scala 56:38] + node _T_629 = and(io.in.0.a.valid, _T_628) @[SourceShrinker.scala 56:35] + io.out.0.a.valid <= _T_629 @[SourceShrinker.scala 56:21] + io.out.0.a.bits <- io.in.0.a.bits @[SourceShrinker.scala 57:20] + reg _T_631 : UInt<3>, clock @[Reg.scala 34:16] + when _T_586 : @[Reg.scala 35:19] + _T_631 <= _T_563 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_632 = mux(_T_586, _T_563, _T_631) @[Package.scala 27:42] + io.out.0.a.bits.source <= _T_632 @[SourceShrinker.scala 58:27] + io.in.0.d <- io.out.0.d @[SourceShrinker.scala 60:14] + infer mport _T_633 = _T_537[io.out.0.d.bits.source], clock + io.in.0.d.bits.source <= _T_633 @[SourceShrinker.scala 61:26] + node _T_634 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_635 = and(_T_586, _T_634) @[SourceShrinker.scala 63:23] + when _T_635 : @[SourceShrinker.scala 63:39] + node _T_636 = bits(_T_563, 1, 0) + infer mport _T_637 = _T_537[_T_636], clock + _T_637 <= io.in.0.a.bits.source @[SourceShrinker.scala 64:33] + skip @[SourceShrinker.scala 63:39] + node _T_638 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_639 = and(_T_586, _T_638) @[SourceShrinker.scala 67:29] + node _T_640 = and(io.in.0.d.ready, io.in.0.d.valid) @[Decoupled.scala 30:37] + node _T_641 = and(_T_618, _T_640) @[SourceShrinker.scala 68:27] + node _T_643 = mux(_T_639, _T_550, UInt<1>("h00")) @[SourceShrinker.scala 69:27] + node _T_645 = dshl(UInt<1>("h01"), io.out.0.d.bits.source) @[OneHot.scala 47:11] + node _T_647 = mux(_T_641, _T_645, UInt<1>("h00")) @[SourceShrinker.scala 70:26] + node _T_648 = or(_T_539, _T_643) @[SourceShrinker.scala 71:33] + node _T_649 = not(_T_647) @[SourceShrinker.scala 71:47] + node _T_650 = and(_T_648, _T_649) @[SourceShrinker.scala 71:45] + _T_539 <= _T_650 @[SourceShrinker.scala 71:19] + + module TLMonitor_8 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 218:45] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 218:45] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_608 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:218:45)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + when _T_700 : @[Periphery.scala 218:45] + node _T_703 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_705 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_706 = and(_T_703, _T_705) @[Parameters.scala 63:37] + node _T_707 = or(UInt<1>("h00"), _T_706) @[Parameters.scala 132:31] + node _T_709 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_710 = cvt(_T_709) @[Parameters.scala 117:49] + node _T_712 = and(_T_710, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_713 = asSInt(_T_712) @[Parameters.scala 117:52] + node _T_715 = eq(_T_713, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_717 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_718 = cvt(_T_717) @[Parameters.scala 117:49] + node _T_720 = and(_T_718, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_721 = asSInt(_T_720) @[Parameters.scala 117:52] + node _T_723 = eq(_T_721, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_724 = or(_T_715, _T_723) @[Parameters.scala 133:42] + node _T_725 = and(_T_707, _T_724) @[Parameters.scala 132:56] + node _T_728 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_730 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_731 = cvt(_T_730) @[Parameters.scala 117:49] + node _T_733 = and(_T_731, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_734 = asSInt(_T_733) @[Parameters.scala 117:52] + node _T_736 = eq(_T_734, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_738 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_739 = cvt(_T_738) @[Parameters.scala 117:49] + node _T_741 = and(_T_739, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_742 = asSInt(_T_741) @[Parameters.scala 117:52] + node _T_744 = eq(_T_742, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_746 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_747 = cvt(_T_746) @[Parameters.scala 117:49] + node _T_749 = and(_T_747, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_750 = asSInt(_T_749) @[Parameters.scala 117:52] + node _T_752 = eq(_T_750, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_754 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_755 = cvt(_T_754) @[Parameters.scala 117:49] + node _T_757 = and(_T_755, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_758 = asSInt(_T_757) @[Parameters.scala 117:52] + node _T_760 = eq(_T_758, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_761 = or(_T_736, _T_744) @[Parameters.scala 133:42] + node _T_762 = or(_T_761, _T_752) @[Parameters.scala 133:42] + node _T_763 = or(_T_762, _T_760) @[Parameters.scala 133:42] + node _T_764 = and(_T_728, _T_763) @[Parameters.scala 132:56] + node _T_766 = or(UInt<1>("h00"), _T_725) @[Parameters.scala 134:30] + node _T_767 = or(_T_766, _T_764) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[Periphery.scala 218:45] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_770 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_771 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_773 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_775 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_776 = or(_T_775, reset) @[Periphery.scala 218:45] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_778 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_779 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_781 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_783 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_784 = or(_T_783, reset) @[Periphery.scala 218:45] + node _T_786 = eq(_T_784, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_786 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:218:45)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_787 = not(io.in[0].a.bits.mask) @[Periphery.scala 218:45] + node _T_789 = eq(_T_787, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_790 = or(_T_789, reset) @[Periphery.scala 218:45] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_792 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_794 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 218:45] + when _T_794 : @[Periphery.scala 218:45] + node _T_797 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_799 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_800 = and(_T_797, _T_799) @[Parameters.scala 63:37] + node _T_801 = or(UInt<1>("h00"), _T_800) @[Parameters.scala 132:31] + node _T_803 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_812 = cvt(_T_811) @[Parameters.scala 117:49] + node _T_814 = and(_T_812, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_815 = asSInt(_T_814) @[Parameters.scala 117:52] + node _T_817 = eq(_T_815, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_819 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_820 = cvt(_T_819) @[Parameters.scala 117:49] + node _T_822 = and(_T_820, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_823 = asSInt(_T_822) @[Parameters.scala 117:52] + node _T_825 = eq(_T_823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_827 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_828 = cvt(_T_827) @[Parameters.scala 117:49] + node _T_830 = and(_T_828, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_831 = asSInt(_T_830) @[Parameters.scala 117:52] + node _T_833 = eq(_T_831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_835 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = or(_T_809, _T_817) @[Parameters.scala 133:42] + node _T_843 = or(_T_842, _T_825) @[Parameters.scala 133:42] + node _T_844 = or(_T_843, _T_833) @[Parameters.scala 133:42] + node _T_845 = or(_T_844, _T_841) @[Parameters.scala 133:42] + node _T_846 = and(_T_801, _T_845) @[Parameters.scala 132:56] + node _T_849 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_851 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_852 = and(_T_849, _T_851) @[Parameters.scala 63:37] + node _T_853 = or(UInt<1>("h00"), _T_852) @[Parameters.scala 132:31] + node _T_855 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_862 = and(_T_853, _T_861) @[Parameters.scala 132:56] + node _T_864 = or(UInt<1>("h00"), _T_846) @[Parameters.scala 134:30] + node _T_865 = or(_T_864, _T_862) @[Parameters.scala 134:30] + node _T_866 = or(_T_865, reset) @[Periphery.scala 218:45] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_868 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_869 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_871 = eq(_T_869, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_871 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_872 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_874 = eq(_T_872, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_874 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_876 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_877 = or(_T_876, reset) @[Periphery.scala 218:45] + node _T_879 = eq(_T_877, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_879 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_880 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 218:45] + node _T_881 = or(_T_880, reset) @[Periphery.scala 218:45] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_883 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_885 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_885 : @[Periphery.scala 218:45] + node _T_888 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_890 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_891 = and(_T_888, _T_890) @[Parameters.scala 63:37] + node _T_892 = or(UInt<1>("h00"), _T_891) @[Parameters.scala 132:31] + node _T_894 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_895 = cvt(_T_894) @[Parameters.scala 117:49] + node _T_897 = and(_T_895, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_898 = asSInt(_T_897) @[Parameters.scala 117:52] + node _T_900 = eq(_T_898, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_902 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_903 = cvt(_T_902) @[Parameters.scala 117:49] + node _T_905 = and(_T_903, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_906 = asSInt(_T_905) @[Parameters.scala 117:52] + node _T_908 = eq(_T_906, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_910 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_911 = cvt(_T_910) @[Parameters.scala 117:49] + node _T_913 = and(_T_911, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_914 = asSInt(_T_913) @[Parameters.scala 117:52] + node _T_916 = eq(_T_914, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_918 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_919 = cvt(_T_918) @[Parameters.scala 117:49] + node _T_921 = and(_T_919, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_922 = asSInt(_T_921) @[Parameters.scala 117:52] + node _T_924 = eq(_T_922, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_926 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_927 = cvt(_T_926) @[Parameters.scala 117:49] + node _T_929 = and(_T_927, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_930 = asSInt(_T_929) @[Parameters.scala 117:52] + node _T_932 = eq(_T_930, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_933 = or(_T_900, _T_908) @[Parameters.scala 133:42] + node _T_934 = or(_T_933, _T_916) @[Parameters.scala 133:42] + node _T_935 = or(_T_934, _T_924) @[Parameters.scala 133:42] + node _T_936 = or(_T_935, _T_932) @[Parameters.scala 133:42] + node _T_937 = and(_T_892, _T_936) @[Parameters.scala 132:56] + node _T_940 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_942 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_943 = and(_T_940, _T_942) @[Parameters.scala 63:37] + node _T_944 = or(UInt<1>("h00"), _T_943) @[Parameters.scala 132:31] + node _T_946 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_947 = cvt(_T_946) @[Parameters.scala 117:49] + node _T_949 = and(_T_947, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_950 = asSInt(_T_949) @[Parameters.scala 117:52] + node _T_952 = eq(_T_950, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_953 = and(_T_944, _T_952) @[Parameters.scala 132:56] + node _T_956 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_958 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_959 = cvt(_T_958) @[Parameters.scala 117:49] + node _T_961 = and(_T_959, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_962 = asSInt(_T_961) @[Parameters.scala 117:52] + node _T_964 = eq(_T_962, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_965 = and(_T_956, _T_964) @[Parameters.scala 132:56] + node _T_967 = or(UInt<1>("h00"), _T_937) @[Parameters.scala 134:30] + node _T_968 = or(_T_967, _T_953) @[Parameters.scala 134:30] + node _T_969 = or(_T_968, _T_965) @[Parameters.scala 134:30] + node _T_970 = or(_T_969, reset) @[Periphery.scala 218:45] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_972 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_973 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_975 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_976 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_978 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_980 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_981 = or(_T_980, reset) @[Periphery.scala 218:45] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_983 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_984 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 218:45] + node _T_985 = or(_T_984, reset) @[Periphery.scala 218:45] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_987 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_989 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 218:45] + when _T_989 : @[Periphery.scala 218:45] + node _T_992 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_994 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_995 = and(_T_992, _T_994) @[Parameters.scala 63:37] + node _T_996 = or(UInt<1>("h00"), _T_995) @[Parameters.scala 132:31] + node _T_998 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_999 = cvt(_T_998) @[Parameters.scala 117:49] + node _T_1001 = and(_T_999, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1002 = asSInt(_T_1001) @[Parameters.scala 117:52] + node _T_1004 = eq(_T_1002, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1006 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1007 = cvt(_T_1006) @[Parameters.scala 117:49] + node _T_1009 = and(_T_1007, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1010 = asSInt(_T_1009) @[Parameters.scala 117:52] + node _T_1012 = eq(_T_1010, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1014 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1015 = cvt(_T_1014) @[Parameters.scala 117:49] + node _T_1017 = and(_T_1015, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1018 = asSInt(_T_1017) @[Parameters.scala 117:52] + node _T_1020 = eq(_T_1018, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1022 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1023 = cvt(_T_1022) @[Parameters.scala 117:49] + node _T_1025 = and(_T_1023, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1026 = asSInt(_T_1025) @[Parameters.scala 117:52] + node _T_1028 = eq(_T_1026, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1030 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1031 = cvt(_T_1030) @[Parameters.scala 117:49] + node _T_1033 = and(_T_1031, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1034 = asSInt(_T_1033) @[Parameters.scala 117:52] + node _T_1036 = eq(_T_1034, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1037 = or(_T_1004, _T_1012) @[Parameters.scala 133:42] + node _T_1038 = or(_T_1037, _T_1020) @[Parameters.scala 133:42] + node _T_1039 = or(_T_1038, _T_1028) @[Parameters.scala 133:42] + node _T_1040 = or(_T_1039, _T_1036) @[Parameters.scala 133:42] + node _T_1041 = and(_T_996, _T_1040) @[Parameters.scala 132:56] + node _T_1044 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1046 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1047 = and(_T_1044, _T_1046) @[Parameters.scala 63:37] + node _T_1048 = or(UInt<1>("h00"), _T_1047) @[Parameters.scala 132:31] + node _T_1050 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1051 = cvt(_T_1050) @[Parameters.scala 117:49] + node _T_1053 = and(_T_1051, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1054 = asSInt(_T_1053) @[Parameters.scala 117:52] + node _T_1056 = eq(_T_1054, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1057 = and(_T_1048, _T_1056) @[Parameters.scala 132:56] + node _T_1060 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1062 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1063 = cvt(_T_1062) @[Parameters.scala 117:49] + node _T_1065 = and(_T_1063, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1066 = asSInt(_T_1065) @[Parameters.scala 117:52] + node _T_1068 = eq(_T_1066, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = and(_T_1060, _T_1068) @[Parameters.scala 132:56] + node _T_1071 = or(UInt<1>("h00"), _T_1041) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, _T_1057) @[Parameters.scala 134:30] + node _T_1073 = or(_T_1072, _T_1069) @[Parameters.scala 134:30] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 218:45] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1076 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1077 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1079 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1080 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1082 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1084 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1085 = or(_T_1084, reset) @[Periphery.scala 218:45] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1087 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1088 = not(_T_698) @[Periphery.scala 218:45] + node _T_1089 = and(io.in[0].a.bits.mask, _T_1088) @[Periphery.scala 218:45] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1092 = or(_T_1091, reset) @[Periphery.scala 218:45] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1094 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1096 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 218:45] + when _T_1096 : @[Periphery.scala 218:45] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1113 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1114 = cvt(_T_1113) @[Parameters.scala 117:49] + node _T_1116 = and(_T_1114, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1117 = asSInt(_T_1116) @[Parameters.scala 117:52] + node _T_1119 = eq(_T_1117, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1121 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1122 = cvt(_T_1121) @[Parameters.scala 117:49] + node _T_1124 = and(_T_1122, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1125 = asSInt(_T_1124) @[Parameters.scala 117:52] + node _T_1127 = eq(_T_1125, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1128 = or(_T_1111, _T_1119) @[Parameters.scala 133:42] + node _T_1129 = or(_T_1128, _T_1127) @[Parameters.scala 133:42] + node _T_1130 = and(_T_1103, _T_1129) @[Parameters.scala 132:56] + node _T_1133 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1135 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1136 = cvt(_T_1135) @[Parameters.scala 117:49] + node _T_1138 = and(_T_1136, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1139 = asSInt(_T_1138) @[Parameters.scala 117:52] + node _T_1141 = eq(_T_1139, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1143 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1144 = cvt(_T_1143) @[Parameters.scala 117:49] + node _T_1146 = and(_T_1144, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1147 = asSInt(_T_1146) @[Parameters.scala 117:52] + node _T_1149 = eq(_T_1147, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1151 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1152 = cvt(_T_1151) @[Parameters.scala 117:49] + node _T_1154 = and(_T_1152, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1155 = asSInt(_T_1154) @[Parameters.scala 117:52] + node _T_1157 = eq(_T_1155, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1159 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1160 = cvt(_T_1159) @[Parameters.scala 117:49] + node _T_1162 = and(_T_1160, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1163 = asSInt(_T_1162) @[Parameters.scala 117:52] + node _T_1165 = eq(_T_1163, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1166 = or(_T_1141, _T_1149) @[Parameters.scala 133:42] + node _T_1167 = or(_T_1166, _T_1157) @[Parameters.scala 133:42] + node _T_1168 = or(_T_1167, _T_1165) @[Parameters.scala 133:42] + node _T_1169 = and(_T_1133, _T_1168) @[Parameters.scala 132:56] + node _T_1171 = or(UInt<1>("h00"), _T_1130) @[Parameters.scala 134:30] + node _T_1172 = or(_T_1171, _T_1169) @[Parameters.scala 134:30] + node _T_1173 = or(_T_1172, reset) @[Periphery.scala 218:45] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1175 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1176 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1178 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1179 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_1181 = eq(_T_1179, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1181 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1183 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1184 = or(_T_1183, reset) @[Periphery.scala 218:45] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1186 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:218:45)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1187 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 218:45] + node _T_1188 = or(_T_1187, reset) @[Periphery.scala 218:45] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1190 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1192 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 218:45] + when _T_1192 : @[Periphery.scala 218:45] + node _T_1195 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1197 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1198 = and(_T_1195, _T_1197) @[Parameters.scala 63:37] + node _T_1199 = or(UInt<1>("h00"), _T_1198) @[Parameters.scala 132:31] + node _T_1201 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1202 = cvt(_T_1201) @[Parameters.scala 117:49] + node _T_1204 = and(_T_1202, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1205 = asSInt(_T_1204) @[Parameters.scala 117:52] + node _T_1207 = eq(_T_1205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1209 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1210 = cvt(_T_1209) @[Parameters.scala 117:49] + node _T_1212 = and(_T_1210, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1213 = asSInt(_T_1212) @[Parameters.scala 117:52] + node _T_1215 = eq(_T_1213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1217 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1218 = cvt(_T_1217) @[Parameters.scala 117:49] + node _T_1220 = and(_T_1218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1221 = asSInt(_T_1220) @[Parameters.scala 117:52] + node _T_1223 = eq(_T_1221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1224 = or(_T_1207, _T_1215) @[Parameters.scala 133:42] + node _T_1225 = or(_T_1224, _T_1223) @[Parameters.scala 133:42] + node _T_1226 = and(_T_1199, _T_1225) @[Parameters.scala 132:56] + node _T_1229 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1231 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1239 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1240 = cvt(_T_1239) @[Parameters.scala 117:49] + node _T_1242 = and(_T_1240, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1243 = asSInt(_T_1242) @[Parameters.scala 117:52] + node _T_1245 = eq(_T_1243, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1247 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1248 = cvt(_T_1247) @[Parameters.scala 117:49] + node _T_1250 = and(_T_1248, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1251 = asSInt(_T_1250) @[Parameters.scala 117:52] + node _T_1253 = eq(_T_1251, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1255 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1256 = cvt(_T_1255) @[Parameters.scala 117:49] + node _T_1258 = and(_T_1256, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1259 = asSInt(_T_1258) @[Parameters.scala 117:52] + node _T_1261 = eq(_T_1259, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1262 = or(_T_1237, _T_1245) @[Parameters.scala 133:42] + node _T_1263 = or(_T_1262, _T_1253) @[Parameters.scala 133:42] + node _T_1264 = or(_T_1263, _T_1261) @[Parameters.scala 133:42] + node _T_1265 = and(_T_1229, _T_1264) @[Parameters.scala 132:56] + node _T_1267 = or(UInt<1>("h00"), _T_1226) @[Parameters.scala 134:30] + node _T_1268 = or(_T_1267, _T_1265) @[Parameters.scala 134:30] + node _T_1269 = or(_T_1268, reset) @[Periphery.scala 218:45] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1271 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1272 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1274 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1275 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1277 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1279 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1280 = or(_T_1279, reset) @[Periphery.scala 218:45] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1282 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:218:45)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1283 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 218:45] + node _T_1284 = or(_T_1283, reset) @[Periphery.scala 218:45] + node _T_1286 = eq(_T_1284, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1286 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1288 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 218:45] + when _T_1288 : @[Periphery.scala 218:45] + node _T_1291 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1293 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1294 = cvt(_T_1293) @[Parameters.scala 117:49] + node _T_1296 = and(_T_1294, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1297 = asSInt(_T_1296) @[Parameters.scala 117:52] + node _T_1299 = eq(_T_1297, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1301 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1302 = cvt(_T_1301) @[Parameters.scala 117:49] + node _T_1304 = and(_T_1302, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1305 = asSInt(_T_1304) @[Parameters.scala 117:52] + node _T_1307 = eq(_T_1305, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1309 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1310 = cvt(_T_1309) @[Parameters.scala 117:49] + node _T_1312 = and(_T_1310, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1313 = asSInt(_T_1312) @[Parameters.scala 117:52] + node _T_1315 = eq(_T_1313, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1317 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1318 = cvt(_T_1317) @[Parameters.scala 117:49] + node _T_1320 = and(_T_1318, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1321 = asSInt(_T_1320) @[Parameters.scala 117:52] + node _T_1323 = eq(_T_1321, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1325 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1326 = cvt(_T_1325) @[Parameters.scala 117:49] + node _T_1328 = and(_T_1326, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1329 = asSInt(_T_1328) @[Parameters.scala 117:52] + node _T_1331 = eq(_T_1329, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1333 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1334 = cvt(_T_1333) @[Parameters.scala 117:49] + node _T_1336 = and(_T_1334, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1337 = asSInt(_T_1336) @[Parameters.scala 117:52] + node _T_1339 = eq(_T_1337, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1340 = or(_T_1299, _T_1307) @[Parameters.scala 133:42] + node _T_1341 = or(_T_1340, _T_1315) @[Parameters.scala 133:42] + node _T_1342 = or(_T_1341, _T_1323) @[Parameters.scala 133:42] + node _T_1343 = or(_T_1342, _T_1331) @[Parameters.scala 133:42] + node _T_1344 = or(_T_1343, _T_1339) @[Parameters.scala 133:42] + node _T_1345 = and(_T_1291, _T_1344) @[Parameters.scala 132:56] + node _T_1347 = or(UInt<1>("h00"), _T_1345) @[Parameters.scala 134:30] + node _T_1348 = or(_T_1347, reset) @[Periphery.scala 218:45] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1350 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1351 = or(_T_619[0], reset) @[Periphery.scala 218:45] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1353 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1354 = or(_T_630, reset) @[Periphery.scala 218:45] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1356 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1357 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 218:45] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 218:45] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1360 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + when io.in[0].b.valid : @[Periphery.scala 218:45] + node _T_1362 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1363 = or(_T_1362, reset) @[Periphery.scala 218:45] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1365 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:218:45)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1367 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1375 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1376 = cvt(_T_1375) @[Parameters.scala 117:49] + node _T_1378 = and(_T_1376, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1379 = asSInt(_T_1378) @[Parameters.scala 117:52] + node _T_1381 = eq(_T_1379, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1383 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1384 = cvt(_T_1383) @[Parameters.scala 117:49] + node _T_1386 = and(_T_1384, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1387 = asSInt(_T_1386) @[Parameters.scala 117:52] + node _T_1389 = eq(_T_1387, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1391 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1392 = cvt(_T_1391) @[Parameters.scala 117:49] + node _T_1394 = and(_T_1392, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1395 = asSInt(_T_1394) @[Parameters.scala 117:52] + node _T_1397 = eq(_T_1395, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1399 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1400 = cvt(_T_1399) @[Parameters.scala 117:49] + node _T_1402 = and(_T_1400, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1403 = asSInt(_T_1402) @[Parameters.scala 117:52] + node _T_1405 = eq(_T_1403, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1407 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1424 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1424 is invalid @[Parameters.scala 110:36] + _T_1424[0] <= _T_1373 @[Parameters.scala 110:36] + _T_1424[1] <= _T_1381 @[Parameters.scala 110:36] + _T_1424[2] <= _T_1389 @[Parameters.scala 110:36] + _T_1424[3] <= _T_1397 @[Parameters.scala 110:36] + _T_1424[4] <= _T_1405 @[Parameters.scala 110:36] + _T_1424[5] <= _T_1413 @[Parameters.scala 110:36] + _T_1424[6] <= _T_1421 @[Parameters.scala 110:36] + node _T_1434 = or(_T_1424[0], _T_1424[1]) @[Parameters.scala 119:64] + node _T_1435 = or(_T_1434, _T_1424[2]) @[Parameters.scala 119:64] + node _T_1436 = or(_T_1435, _T_1424[3]) @[Parameters.scala 119:64] + node _T_1437 = or(_T_1436, _T_1424[4]) @[Parameters.scala 119:64] + node _T_1438 = or(_T_1437, _T_1424[5]) @[Parameters.scala 119:64] + node _T_1439 = or(_T_1438, _T_1424[6]) @[Parameters.scala 119:64] + node _T_1441 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1442 = dshl(_T_1441, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1443 = bits(_T_1442, 7, 0) @[package.scala 19:76] + node _T_1444 = not(_T_1443) @[package.scala 19:40] + node _T_1445 = and(io.in[0].b.bits.address, _T_1444) @[Edges.scala 17:16] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1449 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1450 = dshl(UInt<1>("h01"), _T_1449) @[OneHot.scala 49:12] + node _T_1451 = bits(_T_1450, 2, 0) @[OneHot.scala 49:37] + node _T_1453 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1455 = bits(_T_1451, 2, 2) @[package.scala 44:26] + node _T_1456 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[package.scala 46:20] + node _T_1459 = and(UInt<1>("h01"), _T_1458) @[package.scala 49:27] + node _T_1460 = and(_T_1455, _T_1459) @[package.scala 50:38] + node _T_1461 = or(_T_1453, _T_1460) @[package.scala 50:29] + node _T_1462 = and(UInt<1>("h01"), _T_1456) @[package.scala 49:27] + node _T_1463 = and(_T_1455, _T_1462) @[package.scala 50:38] + node _T_1464 = or(_T_1453, _T_1463) @[package.scala 50:29] + node _T_1465 = bits(_T_1451, 1, 1) @[package.scala 44:26] + node _T_1466 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[package.scala 46:20] + node _T_1469 = and(_T_1459, _T_1468) @[package.scala 49:27] + node _T_1470 = and(_T_1465, _T_1469) @[package.scala 50:38] + node _T_1471 = or(_T_1461, _T_1470) @[package.scala 50:29] + node _T_1472 = and(_T_1459, _T_1466) @[package.scala 49:27] + node _T_1473 = and(_T_1465, _T_1472) @[package.scala 50:38] + node _T_1474 = or(_T_1461, _T_1473) @[package.scala 50:29] + node _T_1475 = and(_T_1462, _T_1468) @[package.scala 49:27] + node _T_1476 = and(_T_1465, _T_1475) @[package.scala 50:38] + node _T_1477 = or(_T_1464, _T_1476) @[package.scala 50:29] + node _T_1478 = and(_T_1462, _T_1466) @[package.scala 49:27] + node _T_1479 = and(_T_1465, _T_1478) @[package.scala 50:38] + node _T_1480 = or(_T_1464, _T_1479) @[package.scala 50:29] + node _T_1481 = bits(_T_1451, 0, 0) @[package.scala 44:26] + node _T_1482 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[package.scala 46:20] + node _T_1485 = and(_T_1469, _T_1484) @[package.scala 49:27] + node _T_1486 = and(_T_1481, _T_1485) @[package.scala 50:38] + node _T_1487 = or(_T_1471, _T_1486) @[package.scala 50:29] + node _T_1488 = and(_T_1469, _T_1482) @[package.scala 49:27] + node _T_1489 = and(_T_1481, _T_1488) @[package.scala 50:38] + node _T_1490 = or(_T_1471, _T_1489) @[package.scala 50:29] + node _T_1491 = and(_T_1472, _T_1484) @[package.scala 49:27] + node _T_1492 = and(_T_1481, _T_1491) @[package.scala 50:38] + node _T_1493 = or(_T_1474, _T_1492) @[package.scala 50:29] + node _T_1494 = and(_T_1472, _T_1482) @[package.scala 49:27] + node _T_1495 = and(_T_1481, _T_1494) @[package.scala 50:38] + node _T_1496 = or(_T_1474, _T_1495) @[package.scala 50:29] + node _T_1497 = and(_T_1475, _T_1484) @[package.scala 49:27] + node _T_1498 = and(_T_1481, _T_1497) @[package.scala 50:38] + node _T_1499 = or(_T_1477, _T_1498) @[package.scala 50:29] + node _T_1500 = and(_T_1475, _T_1482) @[package.scala 49:27] + node _T_1501 = and(_T_1481, _T_1500) @[package.scala 50:38] + node _T_1502 = or(_T_1477, _T_1501) @[package.scala 50:29] + node _T_1503 = and(_T_1478, _T_1484) @[package.scala 49:27] + node _T_1504 = and(_T_1481, _T_1503) @[package.scala 50:38] + node _T_1505 = or(_T_1480, _T_1504) @[package.scala 50:29] + node _T_1506 = and(_T_1478, _T_1482) @[package.scala 49:27] + node _T_1507 = and(_T_1481, _T_1506) @[package.scala 50:38] + node _T_1508 = or(_T_1480, _T_1507) @[package.scala 50:29] + node _T_1509 = cat(_T_1490, _T_1487) @[Cat.scala 30:58] + node _T_1510 = cat(_T_1496, _T_1493) @[Cat.scala 30:58] + node _T_1511 = cat(_T_1510, _T_1509) @[Cat.scala 30:58] + node _T_1512 = cat(_T_1502, _T_1499) @[Cat.scala 30:58] + node _T_1513 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1514 = cat(_T_1513, _T_1512) @[Cat.scala 30:58] + node _T_1515 = cat(_T_1514, _T_1511) @[Cat.scala 30:58] + node _T_1517 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + when _T_1517 : @[Periphery.scala 218:45] + node _T_1519 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1521 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1522 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1524 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1526 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_1527 = or(_T_1526, reset) @[Periphery.scala 218:45] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1529 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1530 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1532 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1534 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1535 = or(_T_1534, reset) @[Periphery.scala 218:45] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1537 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:218:45)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1538 = not(io.in[0].b.bits.mask) @[Periphery.scala 218:45] + node _T_1540 = eq(_T_1538, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1541 = or(_T_1540, reset) @[Periphery.scala 218:45] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1543 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1545 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 218:45] + when _T_1545 : @[Periphery.scala 218:45] + node _T_1547 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1549 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1550 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1552 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1553 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1555 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1557 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1558 = or(_T_1557, reset) @[Periphery.scala 218:45] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1560 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1561 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 218:45] + node _T_1562 = or(_T_1561, reset) @[Periphery.scala 218:45] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1564 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1566 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1566 : @[Periphery.scala 218:45] + node _T_1568 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1570 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1571 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1573 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1574 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1576 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1578 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 218:45] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1581 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1582 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 218:45] + node _T_1583 = or(_T_1582, reset) @[Periphery.scala 218:45] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1585 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1587 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 218:45] + when _T_1587 : @[Periphery.scala 218:45] + node _T_1589 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1591 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1592 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1594 = eq(_T_1592, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1594 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1595 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1597 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1599 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1600 = or(_T_1599, reset) @[Periphery.scala 218:45] + node _T_1602 = eq(_T_1600, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1602 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1603 = not(_T_1515) @[Periphery.scala 218:45] + node _T_1604 = and(io.in[0].b.bits.mask, _T_1603) @[Periphery.scala 218:45] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1607 = or(_T_1606, reset) @[Periphery.scala 218:45] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1609 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1611 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 218:45] + when _T_1611 : @[Periphery.scala 218:45] + node _T_1613 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1615 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1616 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1618 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1619 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1621 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1623 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1624 = or(_T_1623, reset) @[Periphery.scala 218:45] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1626 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:218:45)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1627 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 218:45] + node _T_1628 = or(_T_1627, reset) @[Periphery.scala 218:45] + node _T_1630 = eq(_T_1628, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1630 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1632 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 218:45] + when _T_1632 : @[Periphery.scala 218:45] + node _T_1634 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1636 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1637 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1639 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1640 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1642 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1644 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1645 = or(_T_1644, reset) @[Periphery.scala 218:45] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1647 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:218:45)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1648 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 218:45] + node _T_1649 = or(_T_1648, reset) @[Periphery.scala 218:45] + node _T_1651 = eq(_T_1649, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1651 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1653 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 218:45] + when _T_1653 : @[Periphery.scala 218:45] + node _T_1655 = or(UInt<1>("h00"), reset) @[Periphery.scala 218:45] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1657 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:218:45)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1658 = or(_T_1439, reset) @[Periphery.scala 218:45] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1660 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1661 = or(_T_1447, reset) @[Periphery.scala 218:45] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1663 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1664 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 218:45] + node _T_1665 = or(_T_1664, reset) @[Periphery.scala 218:45] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1667 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:218:45)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + when io.in[0].c.valid : @[Periphery.scala 218:45] + node _T_1669 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1670 = or(_T_1669, reset) @[Periphery.scala 218:45] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1672 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:218:45)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1674 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1675 = not(_T_1674) @[Parameters.scala 37:9] + node _T_1677 = or(_T_1675, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_1678 = not(_T_1677) @[Parameters.scala 37:7] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1683 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1683 is invalid @[Parameters.scala 228:27] + _T_1683[0] <= _T_1680 @[Parameters.scala 228:27] + node _T_1688 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1689 = dshl(_T_1688, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1690 = bits(_T_1689, 7, 0) @[package.scala 19:76] + node _T_1691 = not(_T_1690) @[package.scala 19:40] + node _T_1692 = and(io.in[0].c.bits.address, _T_1691) @[Edges.scala 17:16] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1696 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1697 = cvt(_T_1696) @[Parameters.scala 117:49] + node _T_1699 = and(_T_1697, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1700 = asSInt(_T_1699) @[Parameters.scala 117:52] + node _T_1702 = eq(_T_1700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1704 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1705 = cvt(_T_1704) @[Parameters.scala 117:49] + node _T_1707 = and(_T_1705, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1708 = asSInt(_T_1707) @[Parameters.scala 117:52] + node _T_1710 = eq(_T_1708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1712 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1713 = cvt(_T_1712) @[Parameters.scala 117:49] + node _T_1715 = and(_T_1713, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1716 = asSInt(_T_1715) @[Parameters.scala 117:52] + node _T_1718 = eq(_T_1716, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1720 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1721 = cvt(_T_1720) @[Parameters.scala 117:49] + node _T_1723 = and(_T_1721, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1724 = asSInt(_T_1723) @[Parameters.scala 117:52] + node _T_1726 = eq(_T_1724, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1728 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1729 = cvt(_T_1728) @[Parameters.scala 117:49] + node _T_1731 = and(_T_1729, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1732 = asSInt(_T_1731) @[Parameters.scala 117:52] + node _T_1734 = eq(_T_1732, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1736 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1737 = cvt(_T_1736) @[Parameters.scala 117:49] + node _T_1739 = and(_T_1737, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1740 = asSInt(_T_1739) @[Parameters.scala 117:52] + node _T_1742 = eq(_T_1740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1744 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1745 = cvt(_T_1744) @[Parameters.scala 117:49] + node _T_1747 = and(_T_1745, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1748 = asSInt(_T_1747) @[Parameters.scala 117:52] + node _T_1750 = eq(_T_1748, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1753 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1753 is invalid @[Parameters.scala 110:36] + _T_1753[0] <= _T_1702 @[Parameters.scala 110:36] + _T_1753[1] <= _T_1710 @[Parameters.scala 110:36] + _T_1753[2] <= _T_1718 @[Parameters.scala 110:36] + _T_1753[3] <= _T_1726 @[Parameters.scala 110:36] + _T_1753[4] <= _T_1734 @[Parameters.scala 110:36] + _T_1753[5] <= _T_1742 @[Parameters.scala 110:36] + _T_1753[6] <= _T_1750 @[Parameters.scala 110:36] + node _T_1763 = or(_T_1753[0], _T_1753[1]) @[Parameters.scala 119:64] + node _T_1764 = or(_T_1763, _T_1753[2]) @[Parameters.scala 119:64] + node _T_1765 = or(_T_1764, _T_1753[3]) @[Parameters.scala 119:64] + node _T_1766 = or(_T_1765, _T_1753[4]) @[Parameters.scala 119:64] + node _T_1767 = or(_T_1766, _T_1753[5]) @[Parameters.scala 119:64] + node _T_1768 = or(_T_1767, _T_1753[6]) @[Parameters.scala 119:64] + node _T_1770 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 218:45] + when _T_1770 : @[Periphery.scala 218:45] + node _T_1771 = or(_T_1768, reset) @[Periphery.scala 218:45] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1773 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1774 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1776 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1778 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_1779 = or(_T_1778, reset) @[Periphery.scala 218:45] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1781 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1782 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1784 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1786 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1787 = or(_T_1786, reset) @[Periphery.scala 218:45] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1789 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:218:45)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1791 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1792 = or(_T_1791, reset) @[Periphery.scala 218:45] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1794 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1796 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 218:45] + when _T_1796 : @[Periphery.scala 218:45] + node _T_1797 = or(_T_1768, reset) @[Periphery.scala 218:45] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1799 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1800 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1802 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1804 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_1805 = or(_T_1804, reset) @[Periphery.scala 218:45] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1807 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1808 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1810 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1812 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1813 = or(_T_1812, reset) @[Periphery.scala 218:45] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1815 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:218:45)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1817 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1818 = or(_T_1817, reset) @[Periphery.scala 218:45] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1820 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1822 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + when _T_1822 : @[Periphery.scala 218:45] + node _T_1825 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1827 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1828 = and(_T_1825, _T_1827) @[Parameters.scala 63:37] + node _T_1829 = or(UInt<1>("h00"), _T_1828) @[Parameters.scala 132:31] + node _T_1831 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1832 = cvt(_T_1831) @[Parameters.scala 117:49] + node _T_1834 = and(_T_1832, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1835 = asSInt(_T_1834) @[Parameters.scala 117:52] + node _T_1837 = eq(_T_1835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1839 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1840 = cvt(_T_1839) @[Parameters.scala 117:49] + node _T_1842 = and(_T_1840, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1843 = asSInt(_T_1842) @[Parameters.scala 117:52] + node _T_1845 = eq(_T_1843, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1846 = or(_T_1837, _T_1845) @[Parameters.scala 133:42] + node _T_1847 = and(_T_1829, _T_1846) @[Parameters.scala 132:56] + node _T_1850 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1852 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1853 = cvt(_T_1852) @[Parameters.scala 117:49] + node _T_1855 = and(_T_1853, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1856 = asSInt(_T_1855) @[Parameters.scala 117:52] + node _T_1858 = eq(_T_1856, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1860 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1861 = cvt(_T_1860) @[Parameters.scala 117:49] + node _T_1863 = and(_T_1861, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1864 = asSInt(_T_1863) @[Parameters.scala 117:52] + node _T_1866 = eq(_T_1864, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1868 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1869 = cvt(_T_1868) @[Parameters.scala 117:49] + node _T_1871 = and(_T_1869, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1872 = asSInt(_T_1871) @[Parameters.scala 117:52] + node _T_1874 = eq(_T_1872, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1876 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1877 = cvt(_T_1876) @[Parameters.scala 117:49] + node _T_1879 = and(_T_1877, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1880 = asSInt(_T_1879) @[Parameters.scala 117:52] + node _T_1882 = eq(_T_1880, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1883 = or(_T_1858, _T_1866) @[Parameters.scala 133:42] + node _T_1884 = or(_T_1883, _T_1874) @[Parameters.scala 133:42] + node _T_1885 = or(_T_1884, _T_1882) @[Parameters.scala 133:42] + node _T_1886 = and(_T_1850, _T_1885) @[Parameters.scala 132:56] + node _T_1888 = or(UInt<1>("h00"), _T_1847) @[Parameters.scala 134:30] + node _T_1889 = or(_T_1888, _T_1886) @[Parameters.scala 134:30] + node _T_1890 = or(_T_1889, reset) @[Periphery.scala 218:45] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1892 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1893 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1895 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1897 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_1898 = or(_T_1897, reset) @[Periphery.scala 218:45] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1900 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1901 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1903 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1905 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1906 = or(_T_1905, reset) @[Periphery.scala 218:45] + node _T_1908 = eq(_T_1906, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1908 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:218:45)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1910 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_1911 = or(_T_1910, reset) @[Periphery.scala 218:45] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1913 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1915 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 218:45] + when _T_1915 : @[Periphery.scala 218:45] + node _T_1918 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1920 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1921 = and(_T_1918, _T_1920) @[Parameters.scala 63:37] + node _T_1922 = or(UInt<1>("h00"), _T_1921) @[Parameters.scala 132:31] + node _T_1924 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1925 = cvt(_T_1924) @[Parameters.scala 117:49] + node _T_1927 = and(_T_1925, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1928 = asSInt(_T_1927) @[Parameters.scala 117:52] + node _T_1930 = eq(_T_1928, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1932 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1933 = cvt(_T_1932) @[Parameters.scala 117:49] + node _T_1935 = and(_T_1933, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1936 = asSInt(_T_1935) @[Parameters.scala 117:52] + node _T_1938 = eq(_T_1936, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1939 = or(_T_1930, _T_1938) @[Parameters.scala 133:42] + node _T_1940 = and(_T_1922, _T_1939) @[Parameters.scala 132:56] + node _T_1943 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1945 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1946 = cvt(_T_1945) @[Parameters.scala 117:49] + node _T_1948 = and(_T_1946, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1949 = asSInt(_T_1948) @[Parameters.scala 117:52] + node _T_1951 = eq(_T_1949, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1953 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1954 = cvt(_T_1953) @[Parameters.scala 117:49] + node _T_1956 = and(_T_1954, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1957 = asSInt(_T_1956) @[Parameters.scala 117:52] + node _T_1959 = eq(_T_1957, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1961 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1962 = cvt(_T_1961) @[Parameters.scala 117:49] + node _T_1964 = and(_T_1962, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1965 = asSInt(_T_1964) @[Parameters.scala 117:52] + node _T_1967 = eq(_T_1965, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1969 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1970 = cvt(_T_1969) @[Parameters.scala 117:49] + node _T_1972 = and(_T_1970, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1973 = asSInt(_T_1972) @[Parameters.scala 117:52] + node _T_1975 = eq(_T_1973, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = or(_T_1951, _T_1959) @[Parameters.scala 133:42] + node _T_1977 = or(_T_1976, _T_1967) @[Parameters.scala 133:42] + node _T_1978 = or(_T_1977, _T_1975) @[Parameters.scala 133:42] + node _T_1979 = and(_T_1943, _T_1978) @[Parameters.scala 132:56] + node _T_1981 = or(UInt<1>("h00"), _T_1940) @[Parameters.scala 134:30] + node _T_1982 = or(_T_1981, _T_1979) @[Parameters.scala 134:30] + node _T_1983 = or(_T_1982, reset) @[Periphery.scala 218:45] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1985 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:218:45)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1986 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1988 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1990 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_1991 = or(_T_1990, reset) @[Periphery.scala 218:45] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1993 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1994 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_1996 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_1998 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1999 = or(_T_1998, reset) @[Periphery.scala 218:45] + node _T_2001 = eq(_T_1999, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2001 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:218:45)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2003 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2004 = or(_T_2003, reset) @[Periphery.scala 218:45] + node _T_2006 = eq(_T_2004, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2006 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2008 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2008 : @[Periphery.scala 218:45] + node _T_2009 = or(_T_1768, reset) @[Periphery.scala 218:45] + node _T_2011 = eq(_T_2009, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2011 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2012 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_2014 = eq(_T_2012, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2014 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2015 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2017 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2019 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2020 = or(_T_2019, reset) @[Periphery.scala 218:45] + node _T_2022 = eq(_T_2020, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2022 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2024 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 218:45] + when _T_2024 : @[Periphery.scala 218:45] + node _T_2025 = or(_T_1768, reset) @[Periphery.scala 218:45] + node _T_2027 = eq(_T_2025, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2027 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2028 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2030 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2031 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2033 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2035 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2036 = or(_T_2035, reset) @[Periphery.scala 218:45] + node _T_2038 = eq(_T_2036, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2038 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2040 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 218:45] + when _T_2040 : @[Periphery.scala 218:45] + node _T_2041 = or(_T_1768, reset) @[Periphery.scala 218:45] + node _T_2043 = eq(_T_2041, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2043 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:218:45)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2044 = or(_T_1683[0], reset) @[Periphery.scala 218:45] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2046 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2047 = or(_T_1694, reset) @[Periphery.scala 218:45] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2049 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2051 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2052 = or(_T_2051, reset) @[Periphery.scala 218:45] + node _T_2054 = eq(_T_2052, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2054 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2056 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2057 = or(_T_2056, reset) @[Periphery.scala 218:45] + node _T_2059 = eq(_T_2057, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2059 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + when io.in[0].d.valid : @[Periphery.scala 218:45] + node _T_2061 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2062 = or(_T_2061, reset) @[Periphery.scala 218:45] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2064 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:218:45)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2066 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_2067 = not(_T_2066) @[Parameters.scala 37:9] + node _T_2069 = or(_T_2067, UInt<9>("h01ff")) @[Parameters.scala 37:28] + node _T_2070 = not(_T_2069) @[Parameters.scala 37:7] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2075 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2075 is invalid @[Parameters.scala 228:27] + _T_2075[0] <= _T_2072 @[Parameters.scala 228:27] + node _T_2080 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2081 = dshl(_T_2080, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2082 = bits(_T_2081, 7, 0) @[package.scala 19:76] + node _T_2083 = not(_T_2082) @[package.scala 19:40] + node _T_2084 = and(io.in[0].d.bits.addr_lo, _T_2083) @[Edges.scala 17:16] + node _T_2086 = eq(_T_2084, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2088 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[Periphery.scala 218:45] + node _T_2090 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + when _T_2090 : @[Periphery.scala 218:45] + node _T_2091 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2093 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2094 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2096 = eq(_T_2094, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2096 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2097 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2099 = eq(_T_2097, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2099 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2101 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_2102 = or(_T_2101, reset) @[Periphery.scala 218:45] + node _T_2104 = eq(_T_2102, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2104 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2106 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2107 = or(_T_2106, reset) @[Periphery.scala 218:45] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2109 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2111 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2112 = or(_T_2111, reset) @[Periphery.scala 218:45] + node _T_2114 = eq(_T_2112, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2114 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2116 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 218:45] + when _T_2116 : @[Periphery.scala 218:45] + node _T_2117 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2119 = eq(_T_2117, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2119 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2120 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2122 = eq(_T_2120, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2122 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2123 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2125 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2127 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_2128 = or(_T_2127, reset) @[Periphery.scala 218:45] + node _T_2130 = eq(_T_2128, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2130 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2132 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2133 = or(_T_2132, reset) @[Periphery.scala 218:45] + node _T_2135 = eq(_T_2133, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2135 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:218:45)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2137 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 218:45] + when _T_2137 : @[Periphery.scala 218:45] + node _T_2138 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2140 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2141 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2143 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2144 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2146 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2148 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 218:45] + node _T_2149 = or(_T_2148, reset) @[Periphery.scala 218:45] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2151 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:218:45)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2153 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2154 = or(_T_2153, reset) @[Periphery.scala 218:45] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2156 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:218:45)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2158 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2158 : @[Periphery.scala 218:45] + node _T_2159 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2161 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2162 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2164 = eq(_T_2162, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2164 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2165 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2167 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2169 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2170 = or(_T_2169, reset) @[Periphery.scala 218:45] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2172 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2174 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 218:45] + when _T_2174 : @[Periphery.scala 218:45] + node _T_2175 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2177 = eq(_T_2175, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2177 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2178 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2180 = eq(_T_2178, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2180 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2181 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2183 = eq(_T_2181, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2183 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2185 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2186 = or(_T_2185, reset) @[Periphery.scala 218:45] + node _T_2188 = eq(_T_2186, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2188 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2190 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 218:45] + when _T_2190 : @[Periphery.scala 218:45] + node _T_2191 = or(_T_2075[0], reset) @[Periphery.scala 218:45] + node _T_2193 = eq(_T_2191, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2193 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2194 = or(_T_2086, reset) @[Periphery.scala 218:45] + node _T_2196 = eq(_T_2194, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2196 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:218:45)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2197 = or(_T_2088, reset) @[Periphery.scala 218:45] + node _T_2199 = eq(_T_2197, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2199 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2201 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2202 = or(_T_2201, reset) @[Periphery.scala 218:45] + node _T_2204 = eq(_T_2202, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2204 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:218:45)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2206 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2207 = or(_T_2206, reset) @[Periphery.scala 218:45] + node _T_2209 = eq(_T_2207, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2209 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:218:45)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + when io.in[0].e.valid : @[Periphery.scala 218:45] + node _T_2211 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[Periphery.scala 218:45] + node _T_2212 = or(_T_2211, reset) @[Periphery.scala 218:45] + node _T_2214 = eq(_T_2212, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2214 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:218:45)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2215 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2217 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2218 = dshl(_T_2217, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2219 = bits(_T_2218, 7, 0) @[package.scala 19:76] + node _T_2220 = not(_T_2219) @[package.scala 19:40] + node _T_2221 = shr(_T_2220, 3) @[Edges.scala 198:59] + node _T_2222 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2224 = eq(_T_2222, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2226 = mux(_T_2224, _T_2221, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2228 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2230 = sub(_T_2228, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2231 = asUInt(_T_2230) @[Edges.scala 208:28] + node _T_2232 = tail(_T_2231, 1) @[Edges.scala 208:28] + node _T_2234 = eq(_T_2228, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2236 = eq(_T_2228, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2238 = eq(_T_2226, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2239 = or(_T_2236, _T_2238) @[Edges.scala 210:37] + node _T_2240 = and(_T_2239, _T_2215) @[Edges.scala 211:22] + node _T_2241 = not(_T_2232) @[Edges.scala 212:27] + node _T_2242 = and(_T_2226, _T_2241) @[Edges.scala 212:25] + when _T_2215 : @[Edges.scala 213:17] + node _T_2243 = mux(_T_2234, _T_2226, _T_2232) @[Edges.scala 214:21] + _T_2228 <= _T_2243 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2245 : UInt, clock @[Periphery.scala 218:45] + reg _T_2247 : UInt, clock @[Periphery.scala 218:45] + reg _T_2249 : UInt, clock @[Periphery.scala 218:45] + reg _T_2251 : UInt, clock @[Periphery.scala 218:45] + reg _T_2253 : UInt, clock @[Periphery.scala 218:45] + node _T_2255 = eq(_T_2234, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2256 = and(io.in[0].a.valid, _T_2255) @[Periphery.scala 218:45] + when _T_2256 : @[Periphery.scala 218:45] + node _T_2257 = eq(io.in[0].a.bits.opcode, _T_2245) @[Periphery.scala 218:45] + node _T_2258 = or(_T_2257, reset) @[Periphery.scala 218:45] + node _T_2260 = eq(_T_2258, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2260 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2261 = eq(io.in[0].a.bits.param, _T_2247) @[Periphery.scala 218:45] + node _T_2262 = or(_T_2261, reset) @[Periphery.scala 218:45] + node _T_2264 = eq(_T_2262, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2264 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2265 = eq(io.in[0].a.bits.size, _T_2249) @[Periphery.scala 218:45] + node _T_2266 = or(_T_2265, reset) @[Periphery.scala 218:45] + node _T_2268 = eq(_T_2266, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2268 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2269 = eq(io.in[0].a.bits.source, _T_2251) @[Periphery.scala 218:45] + node _T_2270 = or(_T_2269, reset) @[Periphery.scala 218:45] + node _T_2272 = eq(_T_2270, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2272 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2273 = eq(io.in[0].a.bits.address, _T_2253) @[Periphery.scala 218:45] + node _T_2274 = or(_T_2273, reset) @[Periphery.scala 218:45] + node _T_2276 = eq(_T_2274, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2276 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2277 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2278 = and(_T_2277, _T_2234) @[Periphery.scala 218:45] + when _T_2278 : @[Periphery.scala 218:45] + _T_2245 <= io.in[0].a.bits.opcode @[Periphery.scala 218:45] + _T_2247 <= io.in[0].a.bits.param @[Periphery.scala 218:45] + _T_2249 <= io.in[0].a.bits.size @[Periphery.scala 218:45] + _T_2251 <= io.in[0].a.bits.source @[Periphery.scala 218:45] + _T_2253 <= io.in[0].a.bits.address @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2279 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2281 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2282 = dshl(_T_2281, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2283 = bits(_T_2282, 7, 0) @[package.scala 19:76] + node _T_2284 = not(_T_2283) @[package.scala 19:40] + node _T_2285 = shr(_T_2284, 3) @[Edges.scala 198:59] + node _T_2286 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2288 = eq(_T_2286, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2291 = mux(UInt<1>("h00"), _T_2285, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2293 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2295 = sub(_T_2293, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2296 = asUInt(_T_2295) @[Edges.scala 208:28] + node _T_2297 = tail(_T_2296, 1) @[Edges.scala 208:28] + node _T_2299 = eq(_T_2293, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2301 = eq(_T_2293, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2303 = eq(_T_2291, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2304 = or(_T_2301, _T_2303) @[Edges.scala 210:37] + node _T_2305 = and(_T_2304, _T_2279) @[Edges.scala 211:22] + node _T_2306 = not(_T_2297) @[Edges.scala 212:27] + node _T_2307 = and(_T_2291, _T_2306) @[Edges.scala 212:25] + when _T_2279 : @[Edges.scala 213:17] + node _T_2308 = mux(_T_2299, _T_2291, _T_2297) @[Edges.scala 214:21] + _T_2293 <= _T_2308 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2310 : UInt, clock @[Periphery.scala 218:45] + reg _T_2312 : UInt, clock @[Periphery.scala 218:45] + reg _T_2314 : UInt, clock @[Periphery.scala 218:45] + reg _T_2316 : UInt, clock @[Periphery.scala 218:45] + reg _T_2318 : UInt, clock @[Periphery.scala 218:45] + node _T_2320 = eq(_T_2299, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2321 = and(io.in[0].b.valid, _T_2320) @[Periphery.scala 218:45] + when _T_2321 : @[Periphery.scala 218:45] + node _T_2322 = eq(io.in[0].b.bits.opcode, _T_2310) @[Periphery.scala 218:45] + node _T_2323 = or(_T_2322, reset) @[Periphery.scala 218:45] + node _T_2325 = eq(_T_2323, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2325 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2326 = eq(io.in[0].b.bits.param, _T_2312) @[Periphery.scala 218:45] + node _T_2327 = or(_T_2326, reset) @[Periphery.scala 218:45] + node _T_2329 = eq(_T_2327, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2329 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2330 = eq(io.in[0].b.bits.size, _T_2314) @[Periphery.scala 218:45] + node _T_2331 = or(_T_2330, reset) @[Periphery.scala 218:45] + node _T_2333 = eq(_T_2331, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2333 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2334 = eq(io.in[0].b.bits.source, _T_2316) @[Periphery.scala 218:45] + node _T_2335 = or(_T_2334, reset) @[Periphery.scala 218:45] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2337 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2338 = eq(io.in[0].b.bits.address, _T_2318) @[Periphery.scala 218:45] + node _T_2339 = or(_T_2338, reset) @[Periphery.scala 218:45] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2341 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2342 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2343 = and(_T_2342, _T_2299) @[Periphery.scala 218:45] + when _T_2343 : @[Periphery.scala 218:45] + _T_2310 <= io.in[0].b.bits.opcode @[Periphery.scala 218:45] + _T_2312 <= io.in[0].b.bits.param @[Periphery.scala 218:45] + _T_2314 <= io.in[0].b.bits.size @[Periphery.scala 218:45] + _T_2316 <= io.in[0].b.bits.source @[Periphery.scala 218:45] + _T_2318 <= io.in[0].b.bits.address @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2344 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2346 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2347 = dshl(_T_2346, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2348 = bits(_T_2347, 7, 0) @[package.scala 19:76] + node _T_2349 = not(_T_2348) @[package.scala 19:40] + node _T_2350 = shr(_T_2349, 3) @[Edges.scala 198:59] + node _T_2351 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2354 = mux(UInt<1>("h00"), _T_2350, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2356 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2358 = sub(_T_2356, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2359 = asUInt(_T_2358) @[Edges.scala 208:28] + node _T_2360 = tail(_T_2359, 1) @[Edges.scala 208:28] + node _T_2362 = eq(_T_2356, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2364 = eq(_T_2356, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2366 = eq(_T_2354, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2367 = or(_T_2364, _T_2366) @[Edges.scala 210:37] + node _T_2368 = and(_T_2367, _T_2344) @[Edges.scala 211:22] + node _T_2369 = not(_T_2360) @[Edges.scala 212:27] + node _T_2370 = and(_T_2354, _T_2369) @[Edges.scala 212:25] + when _T_2344 : @[Edges.scala 213:17] + node _T_2371 = mux(_T_2362, _T_2354, _T_2360) @[Edges.scala 214:21] + _T_2356 <= _T_2371 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2373 : UInt, clock @[Periphery.scala 218:45] + reg _T_2375 : UInt, clock @[Periphery.scala 218:45] + reg _T_2377 : UInt, clock @[Periphery.scala 218:45] + reg _T_2379 : UInt, clock @[Periphery.scala 218:45] + reg _T_2381 : UInt, clock @[Periphery.scala 218:45] + node _T_2383 = eq(_T_2362, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2384 = and(io.in[0].c.valid, _T_2383) @[Periphery.scala 218:45] + when _T_2384 : @[Periphery.scala 218:45] + node _T_2385 = eq(io.in[0].c.bits.opcode, _T_2373) @[Periphery.scala 218:45] + node _T_2386 = or(_T_2385, reset) @[Periphery.scala 218:45] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2388 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2389 = eq(io.in[0].c.bits.param, _T_2375) @[Periphery.scala 218:45] + node _T_2390 = or(_T_2389, reset) @[Periphery.scala 218:45] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2392 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2393 = eq(io.in[0].c.bits.size, _T_2377) @[Periphery.scala 218:45] + node _T_2394 = or(_T_2393, reset) @[Periphery.scala 218:45] + node _T_2396 = eq(_T_2394, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2396 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2397 = eq(io.in[0].c.bits.source, _T_2379) @[Periphery.scala 218:45] + node _T_2398 = or(_T_2397, reset) @[Periphery.scala 218:45] + node _T_2400 = eq(_T_2398, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2400 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2401 = eq(io.in[0].c.bits.address, _T_2381) @[Periphery.scala 218:45] + node _T_2402 = or(_T_2401, reset) @[Periphery.scala 218:45] + node _T_2404 = eq(_T_2402, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2404 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2405 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2406 = and(_T_2405, _T_2362) @[Periphery.scala 218:45] + when _T_2406 : @[Periphery.scala 218:45] + _T_2373 <= io.in[0].c.bits.opcode @[Periphery.scala 218:45] + _T_2375 <= io.in[0].c.bits.param @[Periphery.scala 218:45] + _T_2377 <= io.in[0].c.bits.size @[Periphery.scala 218:45] + _T_2379 <= io.in[0].c.bits.source @[Periphery.scala 218:45] + _T_2381 <= io.in[0].c.bits.address @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2407 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2409 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2410 = dshl(_T_2409, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2411 = bits(_T_2410, 7, 0) @[package.scala 19:76] + node _T_2412 = not(_T_2411) @[package.scala 19:40] + node _T_2413 = shr(_T_2412, 3) @[Edges.scala 198:59] + node _T_2414 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2416 = mux(_T_2414, _T_2413, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2418 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2420 = sub(_T_2418, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2421 = asUInt(_T_2420) @[Edges.scala 208:28] + node _T_2422 = tail(_T_2421, 1) @[Edges.scala 208:28] + node _T_2424 = eq(_T_2418, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2426 = eq(_T_2418, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2428 = eq(_T_2416, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2429 = or(_T_2426, _T_2428) @[Edges.scala 210:37] + node _T_2430 = and(_T_2429, _T_2407) @[Edges.scala 211:22] + node _T_2431 = not(_T_2422) @[Edges.scala 212:27] + node _T_2432 = and(_T_2416, _T_2431) @[Edges.scala 212:25] + when _T_2407 : @[Edges.scala 213:17] + node _T_2433 = mux(_T_2424, _T_2416, _T_2422) @[Edges.scala 214:21] + _T_2418 <= _T_2433 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2435 : UInt, clock @[Periphery.scala 218:45] + reg _T_2437 : UInt, clock @[Periphery.scala 218:45] + reg _T_2439 : UInt, clock @[Periphery.scala 218:45] + reg _T_2441 : UInt, clock @[Periphery.scala 218:45] + reg _T_2443 : UInt, clock @[Periphery.scala 218:45] + reg _T_2445 : UInt, clock @[Periphery.scala 218:45] + node _T_2447 = eq(_T_2424, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2448 = and(io.in[0].d.valid, _T_2447) @[Periphery.scala 218:45] + when _T_2448 : @[Periphery.scala 218:45] + node _T_2449 = eq(io.in[0].d.bits.opcode, _T_2435) @[Periphery.scala 218:45] + node _T_2450 = or(_T_2449, reset) @[Periphery.scala 218:45] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2452 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2453 = eq(io.in[0].d.bits.param, _T_2437) @[Periphery.scala 218:45] + node _T_2454 = or(_T_2453, reset) @[Periphery.scala 218:45] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2456 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2457 = eq(io.in[0].d.bits.size, _T_2439) @[Periphery.scala 218:45] + node _T_2458 = or(_T_2457, reset) @[Periphery.scala 218:45] + node _T_2460 = eq(_T_2458, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2460 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2461 = eq(io.in[0].d.bits.source, _T_2441) @[Periphery.scala 218:45] + node _T_2462 = or(_T_2461, reset) @[Periphery.scala 218:45] + node _T_2464 = eq(_T_2462, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2464 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2465 = eq(io.in[0].d.bits.sink, _T_2443) @[Periphery.scala 218:45] + node _T_2466 = or(_T_2465, reset) @[Periphery.scala 218:45] + node _T_2468 = eq(_T_2466, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2468 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2469 = eq(io.in[0].d.bits.addr_lo, _T_2445) @[Periphery.scala 218:45] + node _T_2470 = or(_T_2469, reset) @[Periphery.scala 218:45] + node _T_2472 = eq(_T_2470, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2472 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:218:45)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2473 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2474 = and(_T_2473, _T_2424) @[Periphery.scala 218:45] + when _T_2474 : @[Periphery.scala 218:45] + _T_2435 <= io.in[0].d.bits.opcode @[Periphery.scala 218:45] + _T_2437 <= io.in[0].d.bits.param @[Periphery.scala 218:45] + _T_2439 <= io.in[0].d.bits.size @[Periphery.scala 218:45] + _T_2441 <= io.in[0].d.bits.source @[Periphery.scala 218:45] + _T_2443 <= io.in[0].d.bits.sink @[Periphery.scala 218:45] + _T_2445 <= io.in[0].d.bits.addr_lo @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + reg _T_2476 : UInt<512>, clock with : (reset => (reset, UInt<512>("h00"))) @[Reg.scala 26:44] + node _T_2477 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2479 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2480 = dshl(_T_2479, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2481 = bits(_T_2480, 7, 0) @[package.scala 19:76] + node _T_2482 = not(_T_2481) @[package.scala 19:40] + node _T_2483 = shr(_T_2482, 3) @[Edges.scala 198:59] + node _T_2484 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2486 = eq(_T_2484, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2488 = mux(_T_2486, _T_2483, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2490 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2492 = sub(_T_2490, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2493 = asUInt(_T_2492) @[Edges.scala 208:28] + node _T_2494 = tail(_T_2493, 1) @[Edges.scala 208:28] + node _T_2496 = eq(_T_2490, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2498 = eq(_T_2490, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2500 = eq(_T_2488, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2501 = or(_T_2498, _T_2500) @[Edges.scala 210:37] + node _T_2502 = and(_T_2501, _T_2477) @[Edges.scala 211:22] + node _T_2503 = not(_T_2494) @[Edges.scala 212:27] + node _T_2504 = and(_T_2488, _T_2503) @[Edges.scala 212:25] + when _T_2477 : @[Edges.scala 213:17] + node _T_2505 = mux(_T_2496, _T_2488, _T_2494) @[Edges.scala 214:21] + _T_2490 <= _T_2505 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2506 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2509 = dshl(_T_2508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2510 = bits(_T_2509, 7, 0) @[package.scala 19:76] + node _T_2511 = not(_T_2510) @[package.scala 19:40] + node _T_2512 = shr(_T_2511, 3) @[Edges.scala 198:59] + node _T_2513 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2515 = mux(_T_2513, _T_2512, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2517 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2519 = sub(_T_2517, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2520 = asUInt(_T_2519) @[Edges.scala 208:28] + node _T_2521 = tail(_T_2520, 1) @[Edges.scala 208:28] + node _T_2523 = eq(_T_2517, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2525 = eq(_T_2517, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2527 = eq(_T_2515, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2528 = or(_T_2525, _T_2527) @[Edges.scala 210:37] + node _T_2529 = and(_T_2528, _T_2506) @[Edges.scala 211:22] + node _T_2530 = not(_T_2521) @[Edges.scala 212:27] + node _T_2531 = and(_T_2515, _T_2530) @[Edges.scala 212:25] + when _T_2506 : @[Edges.scala 213:17] + node _T_2532 = mux(_T_2523, _T_2515, _T_2521) @[Edges.scala 214:21] + _T_2517 <= _T_2532 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2534 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + node _T_2535 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 218:45] + node _T_2536 = or(_T_2534, _T_2535) @[Periphery.scala 218:45] + node _T_2538 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2539 = or(_T_2536, _T_2538) @[Periphery.scala 218:45] + node _T_2541 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2542 = or(_T_2539, _T_2541) @[Periphery.scala 218:45] + node _T_2543 = or(_T_2542, reset) @[Periphery.scala 218:45] + node _T_2545 = eq(_T_2543, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2545 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:218:45)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + wire _T_2547 : UInt<512> + _T_2547 is invalid + _T_2547 <= UInt<512>("h00") + node _T_2548 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2548 : @[Periphery.scala 218:45] + when _T_2501 : @[Periphery.scala 218:45] + node _T_2550 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2547 <= _T_2550 @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2551 = dshr(_T_2476, io.in[0].a.bits.source) @[Periphery.scala 218:45] + node _T_2552 = bits(_T_2551, 0, 0) @[Periphery.scala 218:45] + node _T_2554 = eq(_T_2552, UInt<1>("h00")) @[Periphery.scala 218:45] + node _T_2555 = or(_T_2554, reset) @[Periphery.scala 218:45] + node _T_2557 = eq(_T_2555, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2557 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:218:45)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + wire _T_2559 : UInt<512> + _T_2559 is invalid + _T_2559 <= UInt<512>("h00") + node _T_2560 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2562 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 218:45] + node _T_2563 = and(_T_2560, _T_2562) @[Periphery.scala 218:45] + when _T_2563 : @[Periphery.scala 218:45] + when _T_2528 : @[Periphery.scala 218:45] + node _T_2565 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2559 <= _T_2565 @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2566 = or(_T_2547, _T_2476) @[Periphery.scala 218:45] + node _T_2567 = dshr(_T_2566, io.in[0].d.bits.source) @[Periphery.scala 218:45] + node _T_2568 = bits(_T_2567, 0, 0) @[Periphery.scala 218:45] + node _T_2569 = or(_T_2568, reset) @[Periphery.scala 218:45] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[Periphery.scala 218:45] + when _T_2571 : @[Periphery.scala 218:45] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:218:45)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 218:45] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + skip @[Periphery.scala 218:45] + node _T_2572 = or(_T_2476, _T_2547) @[Periphery.scala 218:45] + node _T_2573 = not(_T_2559) @[Periphery.scala 218:45] + node _T_2574 = and(_T_2572, _T_2573) @[Periphery.scala 218:45] + _T_2476 <= _T_2574 @[Periphery.scala 218:45] + + module TLMonitor_9 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 217:22] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 217:22] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_608 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:217:22)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + when _T_700 : @[Periphery.scala 217:22] + node _T_703 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_705 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_706 = and(_T_703, _T_705) @[Parameters.scala 63:37] + node _T_707 = or(UInt<1>("h00"), _T_706) @[Parameters.scala 132:31] + node _T_709 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_710 = cvt(_T_709) @[Parameters.scala 117:49] + node _T_712 = and(_T_710, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_713 = asSInt(_T_712) @[Parameters.scala 117:52] + node _T_715 = eq(_T_713, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_717 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_718 = cvt(_T_717) @[Parameters.scala 117:49] + node _T_720 = and(_T_718, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_721 = asSInt(_T_720) @[Parameters.scala 117:52] + node _T_723 = eq(_T_721, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_724 = or(_T_715, _T_723) @[Parameters.scala 133:42] + node _T_725 = and(_T_707, _T_724) @[Parameters.scala 132:56] + node _T_728 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_730 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_731 = cvt(_T_730) @[Parameters.scala 117:49] + node _T_733 = and(_T_731, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_734 = asSInt(_T_733) @[Parameters.scala 117:52] + node _T_736 = eq(_T_734, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_738 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_739 = cvt(_T_738) @[Parameters.scala 117:49] + node _T_741 = and(_T_739, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_742 = asSInt(_T_741) @[Parameters.scala 117:52] + node _T_744 = eq(_T_742, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_746 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_747 = cvt(_T_746) @[Parameters.scala 117:49] + node _T_749 = and(_T_747, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_750 = asSInt(_T_749) @[Parameters.scala 117:52] + node _T_752 = eq(_T_750, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_754 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_755 = cvt(_T_754) @[Parameters.scala 117:49] + node _T_757 = and(_T_755, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_758 = asSInt(_T_757) @[Parameters.scala 117:52] + node _T_760 = eq(_T_758, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_761 = or(_T_736, _T_744) @[Parameters.scala 133:42] + node _T_762 = or(_T_761, _T_752) @[Parameters.scala 133:42] + node _T_763 = or(_T_762, _T_760) @[Parameters.scala 133:42] + node _T_764 = and(_T_728, _T_763) @[Parameters.scala 132:56] + node _T_766 = or(UInt<1>("h00"), _T_725) @[Parameters.scala 134:30] + node _T_767 = or(_T_766, _T_764) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[Periphery.scala 217:22] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_770 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_771 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_773 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_775 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_776 = or(_T_775, reset) @[Periphery.scala 217:22] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_778 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_779 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_781 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_783 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_784 = or(_T_783, reset) @[Periphery.scala 217:22] + node _T_786 = eq(_T_784, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_786 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:217:22)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_787 = not(io.in[0].a.bits.mask) @[Periphery.scala 217:22] + node _T_789 = eq(_T_787, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_790 = or(_T_789, reset) @[Periphery.scala 217:22] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_792 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_794 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 217:22] + when _T_794 : @[Periphery.scala 217:22] + node _T_797 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_799 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_800 = and(_T_797, _T_799) @[Parameters.scala 63:37] + node _T_801 = or(UInt<1>("h00"), _T_800) @[Parameters.scala 132:31] + node _T_803 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_812 = cvt(_T_811) @[Parameters.scala 117:49] + node _T_814 = and(_T_812, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_815 = asSInt(_T_814) @[Parameters.scala 117:52] + node _T_817 = eq(_T_815, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_819 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_820 = cvt(_T_819) @[Parameters.scala 117:49] + node _T_822 = and(_T_820, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_823 = asSInt(_T_822) @[Parameters.scala 117:52] + node _T_825 = eq(_T_823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_827 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_828 = cvt(_T_827) @[Parameters.scala 117:49] + node _T_830 = and(_T_828, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_831 = asSInt(_T_830) @[Parameters.scala 117:52] + node _T_833 = eq(_T_831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_835 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = or(_T_809, _T_817) @[Parameters.scala 133:42] + node _T_843 = or(_T_842, _T_825) @[Parameters.scala 133:42] + node _T_844 = or(_T_843, _T_833) @[Parameters.scala 133:42] + node _T_845 = or(_T_844, _T_841) @[Parameters.scala 133:42] + node _T_846 = and(_T_801, _T_845) @[Parameters.scala 132:56] + node _T_849 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_851 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_852 = and(_T_849, _T_851) @[Parameters.scala 63:37] + node _T_853 = or(UInt<1>("h00"), _T_852) @[Parameters.scala 132:31] + node _T_855 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_862 = and(_T_853, _T_861) @[Parameters.scala 132:56] + node _T_864 = or(UInt<1>("h00"), _T_846) @[Parameters.scala 134:30] + node _T_865 = or(_T_864, _T_862) @[Parameters.scala 134:30] + node _T_866 = or(_T_865, reset) @[Periphery.scala 217:22] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_868 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_869 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_871 = eq(_T_869, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_871 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_872 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_874 = eq(_T_872, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_874 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_876 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_877 = or(_T_876, reset) @[Periphery.scala 217:22] + node _T_879 = eq(_T_877, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_879 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_880 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 217:22] + node _T_881 = or(_T_880, reset) @[Periphery.scala 217:22] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_883 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_885 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_885 : @[Periphery.scala 217:22] + node _T_888 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_890 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_891 = and(_T_888, _T_890) @[Parameters.scala 63:37] + node _T_892 = or(UInt<1>("h00"), _T_891) @[Parameters.scala 132:31] + node _T_894 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_895 = cvt(_T_894) @[Parameters.scala 117:49] + node _T_897 = and(_T_895, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_898 = asSInt(_T_897) @[Parameters.scala 117:52] + node _T_900 = eq(_T_898, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_902 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_903 = cvt(_T_902) @[Parameters.scala 117:49] + node _T_905 = and(_T_903, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_906 = asSInt(_T_905) @[Parameters.scala 117:52] + node _T_908 = eq(_T_906, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_910 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_911 = cvt(_T_910) @[Parameters.scala 117:49] + node _T_913 = and(_T_911, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_914 = asSInt(_T_913) @[Parameters.scala 117:52] + node _T_916 = eq(_T_914, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_918 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_919 = cvt(_T_918) @[Parameters.scala 117:49] + node _T_921 = and(_T_919, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_922 = asSInt(_T_921) @[Parameters.scala 117:52] + node _T_924 = eq(_T_922, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_926 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_927 = cvt(_T_926) @[Parameters.scala 117:49] + node _T_929 = and(_T_927, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_930 = asSInt(_T_929) @[Parameters.scala 117:52] + node _T_932 = eq(_T_930, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_933 = or(_T_900, _T_908) @[Parameters.scala 133:42] + node _T_934 = or(_T_933, _T_916) @[Parameters.scala 133:42] + node _T_935 = or(_T_934, _T_924) @[Parameters.scala 133:42] + node _T_936 = or(_T_935, _T_932) @[Parameters.scala 133:42] + node _T_937 = and(_T_892, _T_936) @[Parameters.scala 132:56] + node _T_940 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_942 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_943 = and(_T_940, _T_942) @[Parameters.scala 63:37] + node _T_944 = or(UInt<1>("h00"), _T_943) @[Parameters.scala 132:31] + node _T_946 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_947 = cvt(_T_946) @[Parameters.scala 117:49] + node _T_949 = and(_T_947, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_950 = asSInt(_T_949) @[Parameters.scala 117:52] + node _T_952 = eq(_T_950, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_953 = and(_T_944, _T_952) @[Parameters.scala 132:56] + node _T_956 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_958 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_959 = cvt(_T_958) @[Parameters.scala 117:49] + node _T_961 = and(_T_959, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_962 = asSInt(_T_961) @[Parameters.scala 117:52] + node _T_964 = eq(_T_962, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_965 = and(_T_956, _T_964) @[Parameters.scala 132:56] + node _T_967 = or(UInt<1>("h00"), _T_937) @[Parameters.scala 134:30] + node _T_968 = or(_T_967, _T_953) @[Parameters.scala 134:30] + node _T_969 = or(_T_968, _T_965) @[Parameters.scala 134:30] + node _T_970 = or(_T_969, reset) @[Periphery.scala 217:22] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_972 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_973 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_975 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_976 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_978 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_980 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_981 = or(_T_980, reset) @[Periphery.scala 217:22] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_983 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_984 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 217:22] + node _T_985 = or(_T_984, reset) @[Periphery.scala 217:22] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_987 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_989 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 217:22] + when _T_989 : @[Periphery.scala 217:22] + node _T_992 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_994 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_995 = and(_T_992, _T_994) @[Parameters.scala 63:37] + node _T_996 = or(UInt<1>("h00"), _T_995) @[Parameters.scala 132:31] + node _T_998 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_999 = cvt(_T_998) @[Parameters.scala 117:49] + node _T_1001 = and(_T_999, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1002 = asSInt(_T_1001) @[Parameters.scala 117:52] + node _T_1004 = eq(_T_1002, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1006 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1007 = cvt(_T_1006) @[Parameters.scala 117:49] + node _T_1009 = and(_T_1007, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1010 = asSInt(_T_1009) @[Parameters.scala 117:52] + node _T_1012 = eq(_T_1010, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1014 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1015 = cvt(_T_1014) @[Parameters.scala 117:49] + node _T_1017 = and(_T_1015, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1018 = asSInt(_T_1017) @[Parameters.scala 117:52] + node _T_1020 = eq(_T_1018, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1022 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1023 = cvt(_T_1022) @[Parameters.scala 117:49] + node _T_1025 = and(_T_1023, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1026 = asSInt(_T_1025) @[Parameters.scala 117:52] + node _T_1028 = eq(_T_1026, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1030 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1031 = cvt(_T_1030) @[Parameters.scala 117:49] + node _T_1033 = and(_T_1031, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1034 = asSInt(_T_1033) @[Parameters.scala 117:52] + node _T_1036 = eq(_T_1034, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1037 = or(_T_1004, _T_1012) @[Parameters.scala 133:42] + node _T_1038 = or(_T_1037, _T_1020) @[Parameters.scala 133:42] + node _T_1039 = or(_T_1038, _T_1028) @[Parameters.scala 133:42] + node _T_1040 = or(_T_1039, _T_1036) @[Parameters.scala 133:42] + node _T_1041 = and(_T_996, _T_1040) @[Parameters.scala 132:56] + node _T_1044 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1046 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1047 = and(_T_1044, _T_1046) @[Parameters.scala 63:37] + node _T_1048 = or(UInt<1>("h00"), _T_1047) @[Parameters.scala 132:31] + node _T_1050 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1051 = cvt(_T_1050) @[Parameters.scala 117:49] + node _T_1053 = and(_T_1051, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1054 = asSInt(_T_1053) @[Parameters.scala 117:52] + node _T_1056 = eq(_T_1054, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1057 = and(_T_1048, _T_1056) @[Parameters.scala 132:56] + node _T_1060 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1062 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1063 = cvt(_T_1062) @[Parameters.scala 117:49] + node _T_1065 = and(_T_1063, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1066 = asSInt(_T_1065) @[Parameters.scala 117:52] + node _T_1068 = eq(_T_1066, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = and(_T_1060, _T_1068) @[Parameters.scala 132:56] + node _T_1071 = or(UInt<1>("h00"), _T_1041) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, _T_1057) @[Parameters.scala 134:30] + node _T_1073 = or(_T_1072, _T_1069) @[Parameters.scala 134:30] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 217:22] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1076 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1077 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1079 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1080 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1082 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1084 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1085 = or(_T_1084, reset) @[Periphery.scala 217:22] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1087 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1088 = not(_T_698) @[Periphery.scala 217:22] + node _T_1089 = and(io.in[0].a.bits.mask, _T_1088) @[Periphery.scala 217:22] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1092 = or(_T_1091, reset) @[Periphery.scala 217:22] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1094 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1096 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 217:22] + when _T_1096 : @[Periphery.scala 217:22] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1113 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1114 = cvt(_T_1113) @[Parameters.scala 117:49] + node _T_1116 = and(_T_1114, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1117 = asSInt(_T_1116) @[Parameters.scala 117:52] + node _T_1119 = eq(_T_1117, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1121 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1122 = cvt(_T_1121) @[Parameters.scala 117:49] + node _T_1124 = and(_T_1122, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1125 = asSInt(_T_1124) @[Parameters.scala 117:52] + node _T_1127 = eq(_T_1125, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1128 = or(_T_1111, _T_1119) @[Parameters.scala 133:42] + node _T_1129 = or(_T_1128, _T_1127) @[Parameters.scala 133:42] + node _T_1130 = and(_T_1103, _T_1129) @[Parameters.scala 132:56] + node _T_1133 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1135 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1136 = cvt(_T_1135) @[Parameters.scala 117:49] + node _T_1138 = and(_T_1136, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1139 = asSInt(_T_1138) @[Parameters.scala 117:52] + node _T_1141 = eq(_T_1139, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1143 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1144 = cvt(_T_1143) @[Parameters.scala 117:49] + node _T_1146 = and(_T_1144, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1147 = asSInt(_T_1146) @[Parameters.scala 117:52] + node _T_1149 = eq(_T_1147, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1151 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1152 = cvt(_T_1151) @[Parameters.scala 117:49] + node _T_1154 = and(_T_1152, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1155 = asSInt(_T_1154) @[Parameters.scala 117:52] + node _T_1157 = eq(_T_1155, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1159 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1160 = cvt(_T_1159) @[Parameters.scala 117:49] + node _T_1162 = and(_T_1160, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1163 = asSInt(_T_1162) @[Parameters.scala 117:52] + node _T_1165 = eq(_T_1163, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1166 = or(_T_1141, _T_1149) @[Parameters.scala 133:42] + node _T_1167 = or(_T_1166, _T_1157) @[Parameters.scala 133:42] + node _T_1168 = or(_T_1167, _T_1165) @[Parameters.scala 133:42] + node _T_1169 = and(_T_1133, _T_1168) @[Parameters.scala 132:56] + node _T_1171 = or(UInt<1>("h00"), _T_1130) @[Parameters.scala 134:30] + node _T_1172 = or(_T_1171, _T_1169) @[Parameters.scala 134:30] + node _T_1173 = or(_T_1172, reset) @[Periphery.scala 217:22] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1175 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1176 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1178 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1179 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_1181 = eq(_T_1179, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1181 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1183 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1184 = or(_T_1183, reset) @[Periphery.scala 217:22] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1186 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:217:22)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1187 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 217:22] + node _T_1188 = or(_T_1187, reset) @[Periphery.scala 217:22] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1190 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1192 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 217:22] + when _T_1192 : @[Periphery.scala 217:22] + node _T_1195 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1197 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1198 = and(_T_1195, _T_1197) @[Parameters.scala 63:37] + node _T_1199 = or(UInt<1>("h00"), _T_1198) @[Parameters.scala 132:31] + node _T_1201 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1202 = cvt(_T_1201) @[Parameters.scala 117:49] + node _T_1204 = and(_T_1202, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1205 = asSInt(_T_1204) @[Parameters.scala 117:52] + node _T_1207 = eq(_T_1205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1209 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1210 = cvt(_T_1209) @[Parameters.scala 117:49] + node _T_1212 = and(_T_1210, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1213 = asSInt(_T_1212) @[Parameters.scala 117:52] + node _T_1215 = eq(_T_1213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1217 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1218 = cvt(_T_1217) @[Parameters.scala 117:49] + node _T_1220 = and(_T_1218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1221 = asSInt(_T_1220) @[Parameters.scala 117:52] + node _T_1223 = eq(_T_1221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1224 = or(_T_1207, _T_1215) @[Parameters.scala 133:42] + node _T_1225 = or(_T_1224, _T_1223) @[Parameters.scala 133:42] + node _T_1226 = and(_T_1199, _T_1225) @[Parameters.scala 132:56] + node _T_1229 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1231 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1239 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1240 = cvt(_T_1239) @[Parameters.scala 117:49] + node _T_1242 = and(_T_1240, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1243 = asSInt(_T_1242) @[Parameters.scala 117:52] + node _T_1245 = eq(_T_1243, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1247 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1248 = cvt(_T_1247) @[Parameters.scala 117:49] + node _T_1250 = and(_T_1248, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1251 = asSInt(_T_1250) @[Parameters.scala 117:52] + node _T_1253 = eq(_T_1251, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1255 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1256 = cvt(_T_1255) @[Parameters.scala 117:49] + node _T_1258 = and(_T_1256, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1259 = asSInt(_T_1258) @[Parameters.scala 117:52] + node _T_1261 = eq(_T_1259, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1262 = or(_T_1237, _T_1245) @[Parameters.scala 133:42] + node _T_1263 = or(_T_1262, _T_1253) @[Parameters.scala 133:42] + node _T_1264 = or(_T_1263, _T_1261) @[Parameters.scala 133:42] + node _T_1265 = and(_T_1229, _T_1264) @[Parameters.scala 132:56] + node _T_1267 = or(UInt<1>("h00"), _T_1226) @[Parameters.scala 134:30] + node _T_1268 = or(_T_1267, _T_1265) @[Parameters.scala 134:30] + node _T_1269 = or(_T_1268, reset) @[Periphery.scala 217:22] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1271 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1272 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1274 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1275 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1277 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1279 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1280 = or(_T_1279, reset) @[Periphery.scala 217:22] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1282 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:217:22)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1283 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 217:22] + node _T_1284 = or(_T_1283, reset) @[Periphery.scala 217:22] + node _T_1286 = eq(_T_1284, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1286 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1288 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 217:22] + when _T_1288 : @[Periphery.scala 217:22] + node _T_1291 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1293 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1294 = cvt(_T_1293) @[Parameters.scala 117:49] + node _T_1296 = and(_T_1294, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1297 = asSInt(_T_1296) @[Parameters.scala 117:52] + node _T_1299 = eq(_T_1297, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1301 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1302 = cvt(_T_1301) @[Parameters.scala 117:49] + node _T_1304 = and(_T_1302, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1305 = asSInt(_T_1304) @[Parameters.scala 117:52] + node _T_1307 = eq(_T_1305, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1309 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1310 = cvt(_T_1309) @[Parameters.scala 117:49] + node _T_1312 = and(_T_1310, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1313 = asSInt(_T_1312) @[Parameters.scala 117:52] + node _T_1315 = eq(_T_1313, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1317 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1318 = cvt(_T_1317) @[Parameters.scala 117:49] + node _T_1320 = and(_T_1318, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1321 = asSInt(_T_1320) @[Parameters.scala 117:52] + node _T_1323 = eq(_T_1321, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1325 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1326 = cvt(_T_1325) @[Parameters.scala 117:49] + node _T_1328 = and(_T_1326, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1329 = asSInt(_T_1328) @[Parameters.scala 117:52] + node _T_1331 = eq(_T_1329, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1333 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1334 = cvt(_T_1333) @[Parameters.scala 117:49] + node _T_1336 = and(_T_1334, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1337 = asSInt(_T_1336) @[Parameters.scala 117:52] + node _T_1339 = eq(_T_1337, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1340 = or(_T_1299, _T_1307) @[Parameters.scala 133:42] + node _T_1341 = or(_T_1340, _T_1315) @[Parameters.scala 133:42] + node _T_1342 = or(_T_1341, _T_1323) @[Parameters.scala 133:42] + node _T_1343 = or(_T_1342, _T_1331) @[Parameters.scala 133:42] + node _T_1344 = or(_T_1343, _T_1339) @[Parameters.scala 133:42] + node _T_1345 = and(_T_1291, _T_1344) @[Parameters.scala 132:56] + node _T_1347 = or(UInt<1>("h00"), _T_1345) @[Parameters.scala 134:30] + node _T_1348 = or(_T_1347, reset) @[Periphery.scala 217:22] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1350 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1351 = or(_T_619[0], reset) @[Periphery.scala 217:22] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1353 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1354 = or(_T_630, reset) @[Periphery.scala 217:22] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1356 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1357 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 217:22] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 217:22] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1360 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + when io.in[0].b.valid : @[Periphery.scala 217:22] + node _T_1362 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1363 = or(_T_1362, reset) @[Periphery.scala 217:22] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1365 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:217:22)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1367 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1375 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1376 = cvt(_T_1375) @[Parameters.scala 117:49] + node _T_1378 = and(_T_1376, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1379 = asSInt(_T_1378) @[Parameters.scala 117:52] + node _T_1381 = eq(_T_1379, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1383 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1384 = cvt(_T_1383) @[Parameters.scala 117:49] + node _T_1386 = and(_T_1384, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1387 = asSInt(_T_1386) @[Parameters.scala 117:52] + node _T_1389 = eq(_T_1387, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1391 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1392 = cvt(_T_1391) @[Parameters.scala 117:49] + node _T_1394 = and(_T_1392, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1395 = asSInt(_T_1394) @[Parameters.scala 117:52] + node _T_1397 = eq(_T_1395, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1399 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1400 = cvt(_T_1399) @[Parameters.scala 117:49] + node _T_1402 = and(_T_1400, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1403 = asSInt(_T_1402) @[Parameters.scala 117:52] + node _T_1405 = eq(_T_1403, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1407 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1424 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1424 is invalid @[Parameters.scala 110:36] + _T_1424[0] <= _T_1373 @[Parameters.scala 110:36] + _T_1424[1] <= _T_1381 @[Parameters.scala 110:36] + _T_1424[2] <= _T_1389 @[Parameters.scala 110:36] + _T_1424[3] <= _T_1397 @[Parameters.scala 110:36] + _T_1424[4] <= _T_1405 @[Parameters.scala 110:36] + _T_1424[5] <= _T_1413 @[Parameters.scala 110:36] + _T_1424[6] <= _T_1421 @[Parameters.scala 110:36] + node _T_1434 = or(_T_1424[0], _T_1424[1]) @[Parameters.scala 119:64] + node _T_1435 = or(_T_1434, _T_1424[2]) @[Parameters.scala 119:64] + node _T_1436 = or(_T_1435, _T_1424[3]) @[Parameters.scala 119:64] + node _T_1437 = or(_T_1436, _T_1424[4]) @[Parameters.scala 119:64] + node _T_1438 = or(_T_1437, _T_1424[5]) @[Parameters.scala 119:64] + node _T_1439 = or(_T_1438, _T_1424[6]) @[Parameters.scala 119:64] + node _T_1441 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1442 = dshl(_T_1441, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1443 = bits(_T_1442, 7, 0) @[package.scala 19:76] + node _T_1444 = not(_T_1443) @[package.scala 19:40] + node _T_1445 = and(io.in[0].b.bits.address, _T_1444) @[Edges.scala 17:16] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1449 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1450 = dshl(UInt<1>("h01"), _T_1449) @[OneHot.scala 49:12] + node _T_1451 = bits(_T_1450, 2, 0) @[OneHot.scala 49:37] + node _T_1453 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1455 = bits(_T_1451, 2, 2) @[package.scala 44:26] + node _T_1456 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[package.scala 46:20] + node _T_1459 = and(UInt<1>("h01"), _T_1458) @[package.scala 49:27] + node _T_1460 = and(_T_1455, _T_1459) @[package.scala 50:38] + node _T_1461 = or(_T_1453, _T_1460) @[package.scala 50:29] + node _T_1462 = and(UInt<1>("h01"), _T_1456) @[package.scala 49:27] + node _T_1463 = and(_T_1455, _T_1462) @[package.scala 50:38] + node _T_1464 = or(_T_1453, _T_1463) @[package.scala 50:29] + node _T_1465 = bits(_T_1451, 1, 1) @[package.scala 44:26] + node _T_1466 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[package.scala 46:20] + node _T_1469 = and(_T_1459, _T_1468) @[package.scala 49:27] + node _T_1470 = and(_T_1465, _T_1469) @[package.scala 50:38] + node _T_1471 = or(_T_1461, _T_1470) @[package.scala 50:29] + node _T_1472 = and(_T_1459, _T_1466) @[package.scala 49:27] + node _T_1473 = and(_T_1465, _T_1472) @[package.scala 50:38] + node _T_1474 = or(_T_1461, _T_1473) @[package.scala 50:29] + node _T_1475 = and(_T_1462, _T_1468) @[package.scala 49:27] + node _T_1476 = and(_T_1465, _T_1475) @[package.scala 50:38] + node _T_1477 = or(_T_1464, _T_1476) @[package.scala 50:29] + node _T_1478 = and(_T_1462, _T_1466) @[package.scala 49:27] + node _T_1479 = and(_T_1465, _T_1478) @[package.scala 50:38] + node _T_1480 = or(_T_1464, _T_1479) @[package.scala 50:29] + node _T_1481 = bits(_T_1451, 0, 0) @[package.scala 44:26] + node _T_1482 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[package.scala 46:20] + node _T_1485 = and(_T_1469, _T_1484) @[package.scala 49:27] + node _T_1486 = and(_T_1481, _T_1485) @[package.scala 50:38] + node _T_1487 = or(_T_1471, _T_1486) @[package.scala 50:29] + node _T_1488 = and(_T_1469, _T_1482) @[package.scala 49:27] + node _T_1489 = and(_T_1481, _T_1488) @[package.scala 50:38] + node _T_1490 = or(_T_1471, _T_1489) @[package.scala 50:29] + node _T_1491 = and(_T_1472, _T_1484) @[package.scala 49:27] + node _T_1492 = and(_T_1481, _T_1491) @[package.scala 50:38] + node _T_1493 = or(_T_1474, _T_1492) @[package.scala 50:29] + node _T_1494 = and(_T_1472, _T_1482) @[package.scala 49:27] + node _T_1495 = and(_T_1481, _T_1494) @[package.scala 50:38] + node _T_1496 = or(_T_1474, _T_1495) @[package.scala 50:29] + node _T_1497 = and(_T_1475, _T_1484) @[package.scala 49:27] + node _T_1498 = and(_T_1481, _T_1497) @[package.scala 50:38] + node _T_1499 = or(_T_1477, _T_1498) @[package.scala 50:29] + node _T_1500 = and(_T_1475, _T_1482) @[package.scala 49:27] + node _T_1501 = and(_T_1481, _T_1500) @[package.scala 50:38] + node _T_1502 = or(_T_1477, _T_1501) @[package.scala 50:29] + node _T_1503 = and(_T_1478, _T_1484) @[package.scala 49:27] + node _T_1504 = and(_T_1481, _T_1503) @[package.scala 50:38] + node _T_1505 = or(_T_1480, _T_1504) @[package.scala 50:29] + node _T_1506 = and(_T_1478, _T_1482) @[package.scala 49:27] + node _T_1507 = and(_T_1481, _T_1506) @[package.scala 50:38] + node _T_1508 = or(_T_1480, _T_1507) @[package.scala 50:29] + node _T_1509 = cat(_T_1490, _T_1487) @[Cat.scala 30:58] + node _T_1510 = cat(_T_1496, _T_1493) @[Cat.scala 30:58] + node _T_1511 = cat(_T_1510, _T_1509) @[Cat.scala 30:58] + node _T_1512 = cat(_T_1502, _T_1499) @[Cat.scala 30:58] + node _T_1513 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1514 = cat(_T_1513, _T_1512) @[Cat.scala 30:58] + node _T_1515 = cat(_T_1514, _T_1511) @[Cat.scala 30:58] + node _T_1517 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + when _T_1517 : @[Periphery.scala 217:22] + node _T_1519 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1521 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1522 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1524 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1526 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_1527 = or(_T_1526, reset) @[Periphery.scala 217:22] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1529 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1530 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1532 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1534 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1535 = or(_T_1534, reset) @[Periphery.scala 217:22] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1537 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:217:22)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1538 = not(io.in[0].b.bits.mask) @[Periphery.scala 217:22] + node _T_1540 = eq(_T_1538, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1541 = or(_T_1540, reset) @[Periphery.scala 217:22] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1543 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1545 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 217:22] + when _T_1545 : @[Periphery.scala 217:22] + node _T_1547 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1549 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1550 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1552 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1553 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1555 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1557 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1558 = or(_T_1557, reset) @[Periphery.scala 217:22] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1560 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1561 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 217:22] + node _T_1562 = or(_T_1561, reset) @[Periphery.scala 217:22] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1564 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1566 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1566 : @[Periphery.scala 217:22] + node _T_1568 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1570 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1571 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1573 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1574 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1576 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1578 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 217:22] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1581 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1582 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 217:22] + node _T_1583 = or(_T_1582, reset) @[Periphery.scala 217:22] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1585 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1587 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 217:22] + when _T_1587 : @[Periphery.scala 217:22] + node _T_1589 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1591 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1592 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1594 = eq(_T_1592, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1594 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1595 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1597 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1599 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1600 = or(_T_1599, reset) @[Periphery.scala 217:22] + node _T_1602 = eq(_T_1600, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1602 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1603 = not(_T_1515) @[Periphery.scala 217:22] + node _T_1604 = and(io.in[0].b.bits.mask, _T_1603) @[Periphery.scala 217:22] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1607 = or(_T_1606, reset) @[Periphery.scala 217:22] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1609 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1611 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 217:22] + when _T_1611 : @[Periphery.scala 217:22] + node _T_1613 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1615 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1616 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1618 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1619 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1621 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1623 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1624 = or(_T_1623, reset) @[Periphery.scala 217:22] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1626 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:217:22)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1627 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 217:22] + node _T_1628 = or(_T_1627, reset) @[Periphery.scala 217:22] + node _T_1630 = eq(_T_1628, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1630 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1632 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 217:22] + when _T_1632 : @[Periphery.scala 217:22] + node _T_1634 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1636 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1637 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1639 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1640 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1642 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1644 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1645 = or(_T_1644, reset) @[Periphery.scala 217:22] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1647 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:217:22)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1648 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 217:22] + node _T_1649 = or(_T_1648, reset) @[Periphery.scala 217:22] + node _T_1651 = eq(_T_1649, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1651 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1653 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 217:22] + when _T_1653 : @[Periphery.scala 217:22] + node _T_1655 = or(UInt<1>("h00"), reset) @[Periphery.scala 217:22] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1657 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:217:22)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1658 = or(_T_1439, reset) @[Periphery.scala 217:22] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1660 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1661 = or(_T_1447, reset) @[Periphery.scala 217:22] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1663 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1664 = eq(io.in[0].b.bits.mask, _T_1515) @[Periphery.scala 217:22] + node _T_1665 = or(_T_1664, reset) @[Periphery.scala 217:22] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1667 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:217:22)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + when io.in[0].c.valid : @[Periphery.scala 217:22] + node _T_1669 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1670 = or(_T_1669, reset) @[Periphery.scala 217:22] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1672 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:217:22)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1674 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1675 = not(_T_1674) @[Parameters.scala 37:9] + node _T_1677 = or(_T_1675, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1678 = not(_T_1677) @[Parameters.scala 37:7] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1683 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1683 is invalid @[Parameters.scala 228:27] + _T_1683[0] <= _T_1680 @[Parameters.scala 228:27] + node _T_1688 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1689 = dshl(_T_1688, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1690 = bits(_T_1689, 7, 0) @[package.scala 19:76] + node _T_1691 = not(_T_1690) @[package.scala 19:40] + node _T_1692 = and(io.in[0].c.bits.address, _T_1691) @[Edges.scala 17:16] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1696 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1697 = cvt(_T_1696) @[Parameters.scala 117:49] + node _T_1699 = and(_T_1697, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1700 = asSInt(_T_1699) @[Parameters.scala 117:52] + node _T_1702 = eq(_T_1700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1704 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1705 = cvt(_T_1704) @[Parameters.scala 117:49] + node _T_1707 = and(_T_1705, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1708 = asSInt(_T_1707) @[Parameters.scala 117:52] + node _T_1710 = eq(_T_1708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1712 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1713 = cvt(_T_1712) @[Parameters.scala 117:49] + node _T_1715 = and(_T_1713, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1716 = asSInt(_T_1715) @[Parameters.scala 117:52] + node _T_1718 = eq(_T_1716, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1720 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1721 = cvt(_T_1720) @[Parameters.scala 117:49] + node _T_1723 = and(_T_1721, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1724 = asSInt(_T_1723) @[Parameters.scala 117:52] + node _T_1726 = eq(_T_1724, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1728 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1729 = cvt(_T_1728) @[Parameters.scala 117:49] + node _T_1731 = and(_T_1729, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1732 = asSInt(_T_1731) @[Parameters.scala 117:52] + node _T_1734 = eq(_T_1732, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1736 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1737 = cvt(_T_1736) @[Parameters.scala 117:49] + node _T_1739 = and(_T_1737, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1740 = asSInt(_T_1739) @[Parameters.scala 117:52] + node _T_1742 = eq(_T_1740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1744 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1745 = cvt(_T_1744) @[Parameters.scala 117:49] + node _T_1747 = and(_T_1745, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1748 = asSInt(_T_1747) @[Parameters.scala 117:52] + node _T_1750 = eq(_T_1748, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1753 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1753 is invalid @[Parameters.scala 110:36] + _T_1753[0] <= _T_1702 @[Parameters.scala 110:36] + _T_1753[1] <= _T_1710 @[Parameters.scala 110:36] + _T_1753[2] <= _T_1718 @[Parameters.scala 110:36] + _T_1753[3] <= _T_1726 @[Parameters.scala 110:36] + _T_1753[4] <= _T_1734 @[Parameters.scala 110:36] + _T_1753[5] <= _T_1742 @[Parameters.scala 110:36] + _T_1753[6] <= _T_1750 @[Parameters.scala 110:36] + node _T_1763 = or(_T_1753[0], _T_1753[1]) @[Parameters.scala 119:64] + node _T_1764 = or(_T_1763, _T_1753[2]) @[Parameters.scala 119:64] + node _T_1765 = or(_T_1764, _T_1753[3]) @[Parameters.scala 119:64] + node _T_1766 = or(_T_1765, _T_1753[4]) @[Parameters.scala 119:64] + node _T_1767 = or(_T_1766, _T_1753[5]) @[Parameters.scala 119:64] + node _T_1768 = or(_T_1767, _T_1753[6]) @[Parameters.scala 119:64] + node _T_1770 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 217:22] + when _T_1770 : @[Periphery.scala 217:22] + node _T_1771 = or(_T_1768, reset) @[Periphery.scala 217:22] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1773 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1774 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1776 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1778 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_1779 = or(_T_1778, reset) @[Periphery.scala 217:22] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1781 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1782 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1784 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1786 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1787 = or(_T_1786, reset) @[Periphery.scala 217:22] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1789 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:217:22)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1791 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1792 = or(_T_1791, reset) @[Periphery.scala 217:22] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1794 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1796 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 217:22] + when _T_1796 : @[Periphery.scala 217:22] + node _T_1797 = or(_T_1768, reset) @[Periphery.scala 217:22] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1799 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1800 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1802 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1804 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_1805 = or(_T_1804, reset) @[Periphery.scala 217:22] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1807 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1808 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1810 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1812 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1813 = or(_T_1812, reset) @[Periphery.scala 217:22] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1815 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:217:22)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1817 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1818 = or(_T_1817, reset) @[Periphery.scala 217:22] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1820 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1822 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + when _T_1822 : @[Periphery.scala 217:22] + node _T_1825 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1827 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1828 = and(_T_1825, _T_1827) @[Parameters.scala 63:37] + node _T_1829 = or(UInt<1>("h00"), _T_1828) @[Parameters.scala 132:31] + node _T_1831 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1832 = cvt(_T_1831) @[Parameters.scala 117:49] + node _T_1834 = and(_T_1832, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1835 = asSInt(_T_1834) @[Parameters.scala 117:52] + node _T_1837 = eq(_T_1835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1839 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1840 = cvt(_T_1839) @[Parameters.scala 117:49] + node _T_1842 = and(_T_1840, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1843 = asSInt(_T_1842) @[Parameters.scala 117:52] + node _T_1845 = eq(_T_1843, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1846 = or(_T_1837, _T_1845) @[Parameters.scala 133:42] + node _T_1847 = and(_T_1829, _T_1846) @[Parameters.scala 132:56] + node _T_1850 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1852 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1853 = cvt(_T_1852) @[Parameters.scala 117:49] + node _T_1855 = and(_T_1853, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1856 = asSInt(_T_1855) @[Parameters.scala 117:52] + node _T_1858 = eq(_T_1856, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1860 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1861 = cvt(_T_1860) @[Parameters.scala 117:49] + node _T_1863 = and(_T_1861, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1864 = asSInt(_T_1863) @[Parameters.scala 117:52] + node _T_1866 = eq(_T_1864, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1868 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1869 = cvt(_T_1868) @[Parameters.scala 117:49] + node _T_1871 = and(_T_1869, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1872 = asSInt(_T_1871) @[Parameters.scala 117:52] + node _T_1874 = eq(_T_1872, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1876 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1877 = cvt(_T_1876) @[Parameters.scala 117:49] + node _T_1879 = and(_T_1877, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1880 = asSInt(_T_1879) @[Parameters.scala 117:52] + node _T_1882 = eq(_T_1880, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1883 = or(_T_1858, _T_1866) @[Parameters.scala 133:42] + node _T_1884 = or(_T_1883, _T_1874) @[Parameters.scala 133:42] + node _T_1885 = or(_T_1884, _T_1882) @[Parameters.scala 133:42] + node _T_1886 = and(_T_1850, _T_1885) @[Parameters.scala 132:56] + node _T_1888 = or(UInt<1>("h00"), _T_1847) @[Parameters.scala 134:30] + node _T_1889 = or(_T_1888, _T_1886) @[Parameters.scala 134:30] + node _T_1890 = or(_T_1889, reset) @[Periphery.scala 217:22] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1892 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1893 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1895 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1897 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_1898 = or(_T_1897, reset) @[Periphery.scala 217:22] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1900 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1901 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1903 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1905 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1906 = or(_T_1905, reset) @[Periphery.scala 217:22] + node _T_1908 = eq(_T_1906, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1908 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:217:22)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1910 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_1911 = or(_T_1910, reset) @[Periphery.scala 217:22] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1913 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1915 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 217:22] + when _T_1915 : @[Periphery.scala 217:22] + node _T_1918 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1920 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1921 = and(_T_1918, _T_1920) @[Parameters.scala 63:37] + node _T_1922 = or(UInt<1>("h00"), _T_1921) @[Parameters.scala 132:31] + node _T_1924 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1925 = cvt(_T_1924) @[Parameters.scala 117:49] + node _T_1927 = and(_T_1925, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1928 = asSInt(_T_1927) @[Parameters.scala 117:52] + node _T_1930 = eq(_T_1928, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1932 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1933 = cvt(_T_1932) @[Parameters.scala 117:49] + node _T_1935 = and(_T_1933, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1936 = asSInt(_T_1935) @[Parameters.scala 117:52] + node _T_1938 = eq(_T_1936, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1939 = or(_T_1930, _T_1938) @[Parameters.scala 133:42] + node _T_1940 = and(_T_1922, _T_1939) @[Parameters.scala 132:56] + node _T_1943 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1945 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1946 = cvt(_T_1945) @[Parameters.scala 117:49] + node _T_1948 = and(_T_1946, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1949 = asSInt(_T_1948) @[Parameters.scala 117:52] + node _T_1951 = eq(_T_1949, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1953 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1954 = cvt(_T_1953) @[Parameters.scala 117:49] + node _T_1956 = and(_T_1954, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1957 = asSInt(_T_1956) @[Parameters.scala 117:52] + node _T_1959 = eq(_T_1957, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1961 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1962 = cvt(_T_1961) @[Parameters.scala 117:49] + node _T_1964 = and(_T_1962, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1965 = asSInt(_T_1964) @[Parameters.scala 117:52] + node _T_1967 = eq(_T_1965, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1969 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1970 = cvt(_T_1969) @[Parameters.scala 117:49] + node _T_1972 = and(_T_1970, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1973 = asSInt(_T_1972) @[Parameters.scala 117:52] + node _T_1975 = eq(_T_1973, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = or(_T_1951, _T_1959) @[Parameters.scala 133:42] + node _T_1977 = or(_T_1976, _T_1967) @[Parameters.scala 133:42] + node _T_1978 = or(_T_1977, _T_1975) @[Parameters.scala 133:42] + node _T_1979 = and(_T_1943, _T_1978) @[Parameters.scala 132:56] + node _T_1981 = or(UInt<1>("h00"), _T_1940) @[Parameters.scala 134:30] + node _T_1982 = or(_T_1981, _T_1979) @[Parameters.scala 134:30] + node _T_1983 = or(_T_1982, reset) @[Periphery.scala 217:22] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1985 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:217:22)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1986 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1988 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1990 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_1991 = or(_T_1990, reset) @[Periphery.scala 217:22] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1993 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1994 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_1996 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_1998 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1999 = or(_T_1998, reset) @[Periphery.scala 217:22] + node _T_2001 = eq(_T_1999, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2001 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:217:22)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2003 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2004 = or(_T_2003, reset) @[Periphery.scala 217:22] + node _T_2006 = eq(_T_2004, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2006 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2008 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2008 : @[Periphery.scala 217:22] + node _T_2009 = or(_T_1768, reset) @[Periphery.scala 217:22] + node _T_2011 = eq(_T_2009, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2011 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2012 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_2014 = eq(_T_2012, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2014 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2015 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2017 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2019 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2020 = or(_T_2019, reset) @[Periphery.scala 217:22] + node _T_2022 = eq(_T_2020, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2022 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2024 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 217:22] + when _T_2024 : @[Periphery.scala 217:22] + node _T_2025 = or(_T_1768, reset) @[Periphery.scala 217:22] + node _T_2027 = eq(_T_2025, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2027 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2028 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2030 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2031 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2033 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2035 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2036 = or(_T_2035, reset) @[Periphery.scala 217:22] + node _T_2038 = eq(_T_2036, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2038 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2040 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 217:22] + when _T_2040 : @[Periphery.scala 217:22] + node _T_2041 = or(_T_1768, reset) @[Periphery.scala 217:22] + node _T_2043 = eq(_T_2041, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2043 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:217:22)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2044 = or(_T_1683[0], reset) @[Periphery.scala 217:22] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2046 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2047 = or(_T_1694, reset) @[Periphery.scala 217:22] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2049 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2051 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2052 = or(_T_2051, reset) @[Periphery.scala 217:22] + node _T_2054 = eq(_T_2052, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2054 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2056 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2057 = or(_T_2056, reset) @[Periphery.scala 217:22] + node _T_2059 = eq(_T_2057, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2059 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + when io.in[0].d.valid : @[Periphery.scala 217:22] + node _T_2061 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2062 = or(_T_2061, reset) @[Periphery.scala 217:22] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2064 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:217:22)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2066 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_2067 = not(_T_2066) @[Parameters.scala 37:9] + node _T_2069 = or(_T_2067, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_2070 = not(_T_2069) @[Parameters.scala 37:7] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2075 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2075 is invalid @[Parameters.scala 228:27] + _T_2075[0] <= _T_2072 @[Parameters.scala 228:27] + node _T_2080 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2081 = dshl(_T_2080, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2082 = bits(_T_2081, 7, 0) @[package.scala 19:76] + node _T_2083 = not(_T_2082) @[package.scala 19:40] + node _T_2084 = and(io.in[0].d.bits.addr_lo, _T_2083) @[Edges.scala 17:16] + node _T_2086 = eq(_T_2084, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2088 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[Periphery.scala 217:22] + node _T_2090 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + when _T_2090 : @[Periphery.scala 217:22] + node _T_2091 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2093 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2094 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2096 = eq(_T_2094, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2096 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2097 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2099 = eq(_T_2097, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2099 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2101 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_2102 = or(_T_2101, reset) @[Periphery.scala 217:22] + node _T_2104 = eq(_T_2102, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2104 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2106 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2107 = or(_T_2106, reset) @[Periphery.scala 217:22] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2109 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2111 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2112 = or(_T_2111, reset) @[Periphery.scala 217:22] + node _T_2114 = eq(_T_2112, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2114 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2116 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 217:22] + when _T_2116 : @[Periphery.scala 217:22] + node _T_2117 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2119 = eq(_T_2117, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2119 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2120 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2122 = eq(_T_2120, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2122 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2123 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2125 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2127 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_2128 = or(_T_2127, reset) @[Periphery.scala 217:22] + node _T_2130 = eq(_T_2128, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2130 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2132 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2133 = or(_T_2132, reset) @[Periphery.scala 217:22] + node _T_2135 = eq(_T_2133, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2135 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:217:22)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2137 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 217:22] + when _T_2137 : @[Periphery.scala 217:22] + node _T_2138 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2140 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2141 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2143 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2144 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2146 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2148 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 217:22] + node _T_2149 = or(_T_2148, reset) @[Periphery.scala 217:22] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2151 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:217:22)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2153 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2154 = or(_T_2153, reset) @[Periphery.scala 217:22] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2156 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:217:22)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2158 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2158 : @[Periphery.scala 217:22] + node _T_2159 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2161 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2162 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2164 = eq(_T_2162, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2164 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2165 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2167 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2169 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2170 = or(_T_2169, reset) @[Periphery.scala 217:22] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2172 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2174 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 217:22] + when _T_2174 : @[Periphery.scala 217:22] + node _T_2175 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2177 = eq(_T_2175, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2177 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2178 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2180 = eq(_T_2178, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2180 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2181 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2183 = eq(_T_2181, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2183 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2185 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2186 = or(_T_2185, reset) @[Periphery.scala 217:22] + node _T_2188 = eq(_T_2186, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2188 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2190 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 217:22] + when _T_2190 : @[Periphery.scala 217:22] + node _T_2191 = or(_T_2075[0], reset) @[Periphery.scala 217:22] + node _T_2193 = eq(_T_2191, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2193 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2194 = or(_T_2086, reset) @[Periphery.scala 217:22] + node _T_2196 = eq(_T_2194, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2196 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:217:22)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2197 = or(_T_2088, reset) @[Periphery.scala 217:22] + node _T_2199 = eq(_T_2197, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2199 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2201 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2202 = or(_T_2201, reset) @[Periphery.scala 217:22] + node _T_2204 = eq(_T_2202, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2204 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:217:22)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2206 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2207 = or(_T_2206, reset) @[Periphery.scala 217:22] + node _T_2209 = eq(_T_2207, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2209 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:217:22)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + when io.in[0].e.valid : @[Periphery.scala 217:22] + node _T_2211 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[Periphery.scala 217:22] + node _T_2212 = or(_T_2211, reset) @[Periphery.scala 217:22] + node _T_2214 = eq(_T_2212, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2214 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:217:22)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2215 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2217 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2218 = dshl(_T_2217, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2219 = bits(_T_2218, 7, 0) @[package.scala 19:76] + node _T_2220 = not(_T_2219) @[package.scala 19:40] + node _T_2221 = shr(_T_2220, 3) @[Edges.scala 198:59] + node _T_2222 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2224 = eq(_T_2222, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2226 = mux(_T_2224, _T_2221, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2228 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2230 = sub(_T_2228, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2231 = asUInt(_T_2230) @[Edges.scala 208:28] + node _T_2232 = tail(_T_2231, 1) @[Edges.scala 208:28] + node _T_2234 = eq(_T_2228, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2236 = eq(_T_2228, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2238 = eq(_T_2226, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2239 = or(_T_2236, _T_2238) @[Edges.scala 210:37] + node _T_2240 = and(_T_2239, _T_2215) @[Edges.scala 211:22] + node _T_2241 = not(_T_2232) @[Edges.scala 212:27] + node _T_2242 = and(_T_2226, _T_2241) @[Edges.scala 212:25] + when _T_2215 : @[Edges.scala 213:17] + node _T_2243 = mux(_T_2234, _T_2226, _T_2232) @[Edges.scala 214:21] + _T_2228 <= _T_2243 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2245 : UInt, clock @[Periphery.scala 217:22] + reg _T_2247 : UInt, clock @[Periphery.scala 217:22] + reg _T_2249 : UInt, clock @[Periphery.scala 217:22] + reg _T_2251 : UInt, clock @[Periphery.scala 217:22] + reg _T_2253 : UInt, clock @[Periphery.scala 217:22] + node _T_2255 = eq(_T_2234, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2256 = and(io.in[0].a.valid, _T_2255) @[Periphery.scala 217:22] + when _T_2256 : @[Periphery.scala 217:22] + node _T_2257 = eq(io.in[0].a.bits.opcode, _T_2245) @[Periphery.scala 217:22] + node _T_2258 = or(_T_2257, reset) @[Periphery.scala 217:22] + node _T_2260 = eq(_T_2258, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2260 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2261 = eq(io.in[0].a.bits.param, _T_2247) @[Periphery.scala 217:22] + node _T_2262 = or(_T_2261, reset) @[Periphery.scala 217:22] + node _T_2264 = eq(_T_2262, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2264 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2265 = eq(io.in[0].a.bits.size, _T_2249) @[Periphery.scala 217:22] + node _T_2266 = or(_T_2265, reset) @[Periphery.scala 217:22] + node _T_2268 = eq(_T_2266, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2268 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2269 = eq(io.in[0].a.bits.source, _T_2251) @[Periphery.scala 217:22] + node _T_2270 = or(_T_2269, reset) @[Periphery.scala 217:22] + node _T_2272 = eq(_T_2270, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2272 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2273 = eq(io.in[0].a.bits.address, _T_2253) @[Periphery.scala 217:22] + node _T_2274 = or(_T_2273, reset) @[Periphery.scala 217:22] + node _T_2276 = eq(_T_2274, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2276 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2277 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2278 = and(_T_2277, _T_2234) @[Periphery.scala 217:22] + when _T_2278 : @[Periphery.scala 217:22] + _T_2245 <= io.in[0].a.bits.opcode @[Periphery.scala 217:22] + _T_2247 <= io.in[0].a.bits.param @[Periphery.scala 217:22] + _T_2249 <= io.in[0].a.bits.size @[Periphery.scala 217:22] + _T_2251 <= io.in[0].a.bits.source @[Periphery.scala 217:22] + _T_2253 <= io.in[0].a.bits.address @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2279 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2281 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2282 = dshl(_T_2281, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2283 = bits(_T_2282, 7, 0) @[package.scala 19:76] + node _T_2284 = not(_T_2283) @[package.scala 19:40] + node _T_2285 = shr(_T_2284, 3) @[Edges.scala 198:59] + node _T_2286 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2288 = eq(_T_2286, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2291 = mux(UInt<1>("h00"), _T_2285, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2293 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2295 = sub(_T_2293, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2296 = asUInt(_T_2295) @[Edges.scala 208:28] + node _T_2297 = tail(_T_2296, 1) @[Edges.scala 208:28] + node _T_2299 = eq(_T_2293, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2301 = eq(_T_2293, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2303 = eq(_T_2291, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2304 = or(_T_2301, _T_2303) @[Edges.scala 210:37] + node _T_2305 = and(_T_2304, _T_2279) @[Edges.scala 211:22] + node _T_2306 = not(_T_2297) @[Edges.scala 212:27] + node _T_2307 = and(_T_2291, _T_2306) @[Edges.scala 212:25] + when _T_2279 : @[Edges.scala 213:17] + node _T_2308 = mux(_T_2299, _T_2291, _T_2297) @[Edges.scala 214:21] + _T_2293 <= _T_2308 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2310 : UInt, clock @[Periphery.scala 217:22] + reg _T_2312 : UInt, clock @[Periphery.scala 217:22] + reg _T_2314 : UInt, clock @[Periphery.scala 217:22] + reg _T_2316 : UInt, clock @[Periphery.scala 217:22] + reg _T_2318 : UInt, clock @[Periphery.scala 217:22] + node _T_2320 = eq(_T_2299, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2321 = and(io.in[0].b.valid, _T_2320) @[Periphery.scala 217:22] + when _T_2321 : @[Periphery.scala 217:22] + node _T_2322 = eq(io.in[0].b.bits.opcode, _T_2310) @[Periphery.scala 217:22] + node _T_2323 = or(_T_2322, reset) @[Periphery.scala 217:22] + node _T_2325 = eq(_T_2323, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2325 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2326 = eq(io.in[0].b.bits.param, _T_2312) @[Periphery.scala 217:22] + node _T_2327 = or(_T_2326, reset) @[Periphery.scala 217:22] + node _T_2329 = eq(_T_2327, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2329 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2330 = eq(io.in[0].b.bits.size, _T_2314) @[Periphery.scala 217:22] + node _T_2331 = or(_T_2330, reset) @[Periphery.scala 217:22] + node _T_2333 = eq(_T_2331, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2333 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2334 = eq(io.in[0].b.bits.source, _T_2316) @[Periphery.scala 217:22] + node _T_2335 = or(_T_2334, reset) @[Periphery.scala 217:22] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2337 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2338 = eq(io.in[0].b.bits.address, _T_2318) @[Periphery.scala 217:22] + node _T_2339 = or(_T_2338, reset) @[Periphery.scala 217:22] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2341 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2342 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2343 = and(_T_2342, _T_2299) @[Periphery.scala 217:22] + when _T_2343 : @[Periphery.scala 217:22] + _T_2310 <= io.in[0].b.bits.opcode @[Periphery.scala 217:22] + _T_2312 <= io.in[0].b.bits.param @[Periphery.scala 217:22] + _T_2314 <= io.in[0].b.bits.size @[Periphery.scala 217:22] + _T_2316 <= io.in[0].b.bits.source @[Periphery.scala 217:22] + _T_2318 <= io.in[0].b.bits.address @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2344 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2346 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2347 = dshl(_T_2346, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2348 = bits(_T_2347, 7, 0) @[package.scala 19:76] + node _T_2349 = not(_T_2348) @[package.scala 19:40] + node _T_2350 = shr(_T_2349, 3) @[Edges.scala 198:59] + node _T_2351 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2354 = mux(UInt<1>("h00"), _T_2350, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2356 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2358 = sub(_T_2356, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2359 = asUInt(_T_2358) @[Edges.scala 208:28] + node _T_2360 = tail(_T_2359, 1) @[Edges.scala 208:28] + node _T_2362 = eq(_T_2356, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2364 = eq(_T_2356, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2366 = eq(_T_2354, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2367 = or(_T_2364, _T_2366) @[Edges.scala 210:37] + node _T_2368 = and(_T_2367, _T_2344) @[Edges.scala 211:22] + node _T_2369 = not(_T_2360) @[Edges.scala 212:27] + node _T_2370 = and(_T_2354, _T_2369) @[Edges.scala 212:25] + when _T_2344 : @[Edges.scala 213:17] + node _T_2371 = mux(_T_2362, _T_2354, _T_2360) @[Edges.scala 214:21] + _T_2356 <= _T_2371 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2373 : UInt, clock @[Periphery.scala 217:22] + reg _T_2375 : UInt, clock @[Periphery.scala 217:22] + reg _T_2377 : UInt, clock @[Periphery.scala 217:22] + reg _T_2379 : UInt, clock @[Periphery.scala 217:22] + reg _T_2381 : UInt, clock @[Periphery.scala 217:22] + node _T_2383 = eq(_T_2362, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2384 = and(io.in[0].c.valid, _T_2383) @[Periphery.scala 217:22] + when _T_2384 : @[Periphery.scala 217:22] + node _T_2385 = eq(io.in[0].c.bits.opcode, _T_2373) @[Periphery.scala 217:22] + node _T_2386 = or(_T_2385, reset) @[Periphery.scala 217:22] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2388 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2389 = eq(io.in[0].c.bits.param, _T_2375) @[Periphery.scala 217:22] + node _T_2390 = or(_T_2389, reset) @[Periphery.scala 217:22] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2392 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2393 = eq(io.in[0].c.bits.size, _T_2377) @[Periphery.scala 217:22] + node _T_2394 = or(_T_2393, reset) @[Periphery.scala 217:22] + node _T_2396 = eq(_T_2394, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2396 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2397 = eq(io.in[0].c.bits.source, _T_2379) @[Periphery.scala 217:22] + node _T_2398 = or(_T_2397, reset) @[Periphery.scala 217:22] + node _T_2400 = eq(_T_2398, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2400 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2401 = eq(io.in[0].c.bits.address, _T_2381) @[Periphery.scala 217:22] + node _T_2402 = or(_T_2401, reset) @[Periphery.scala 217:22] + node _T_2404 = eq(_T_2402, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2404 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2405 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2406 = and(_T_2405, _T_2362) @[Periphery.scala 217:22] + when _T_2406 : @[Periphery.scala 217:22] + _T_2373 <= io.in[0].c.bits.opcode @[Periphery.scala 217:22] + _T_2375 <= io.in[0].c.bits.param @[Periphery.scala 217:22] + _T_2377 <= io.in[0].c.bits.size @[Periphery.scala 217:22] + _T_2379 <= io.in[0].c.bits.source @[Periphery.scala 217:22] + _T_2381 <= io.in[0].c.bits.address @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2407 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2409 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2410 = dshl(_T_2409, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2411 = bits(_T_2410, 7, 0) @[package.scala 19:76] + node _T_2412 = not(_T_2411) @[package.scala 19:40] + node _T_2413 = shr(_T_2412, 3) @[Edges.scala 198:59] + node _T_2414 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2416 = mux(_T_2414, _T_2413, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2418 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2420 = sub(_T_2418, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2421 = asUInt(_T_2420) @[Edges.scala 208:28] + node _T_2422 = tail(_T_2421, 1) @[Edges.scala 208:28] + node _T_2424 = eq(_T_2418, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2426 = eq(_T_2418, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2428 = eq(_T_2416, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2429 = or(_T_2426, _T_2428) @[Edges.scala 210:37] + node _T_2430 = and(_T_2429, _T_2407) @[Edges.scala 211:22] + node _T_2431 = not(_T_2422) @[Edges.scala 212:27] + node _T_2432 = and(_T_2416, _T_2431) @[Edges.scala 212:25] + when _T_2407 : @[Edges.scala 213:17] + node _T_2433 = mux(_T_2424, _T_2416, _T_2422) @[Edges.scala 214:21] + _T_2418 <= _T_2433 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2435 : UInt, clock @[Periphery.scala 217:22] + reg _T_2437 : UInt, clock @[Periphery.scala 217:22] + reg _T_2439 : UInt, clock @[Periphery.scala 217:22] + reg _T_2441 : UInt, clock @[Periphery.scala 217:22] + reg _T_2443 : UInt, clock @[Periphery.scala 217:22] + reg _T_2445 : UInt, clock @[Periphery.scala 217:22] + node _T_2447 = eq(_T_2424, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2448 = and(io.in[0].d.valid, _T_2447) @[Periphery.scala 217:22] + when _T_2448 : @[Periphery.scala 217:22] + node _T_2449 = eq(io.in[0].d.bits.opcode, _T_2435) @[Periphery.scala 217:22] + node _T_2450 = or(_T_2449, reset) @[Periphery.scala 217:22] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2452 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2453 = eq(io.in[0].d.bits.param, _T_2437) @[Periphery.scala 217:22] + node _T_2454 = or(_T_2453, reset) @[Periphery.scala 217:22] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2456 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2457 = eq(io.in[0].d.bits.size, _T_2439) @[Periphery.scala 217:22] + node _T_2458 = or(_T_2457, reset) @[Periphery.scala 217:22] + node _T_2460 = eq(_T_2458, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2460 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2461 = eq(io.in[0].d.bits.source, _T_2441) @[Periphery.scala 217:22] + node _T_2462 = or(_T_2461, reset) @[Periphery.scala 217:22] + node _T_2464 = eq(_T_2462, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2464 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2465 = eq(io.in[0].d.bits.sink, _T_2443) @[Periphery.scala 217:22] + node _T_2466 = or(_T_2465, reset) @[Periphery.scala 217:22] + node _T_2468 = eq(_T_2466, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2468 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2469 = eq(io.in[0].d.bits.addr_lo, _T_2445) @[Periphery.scala 217:22] + node _T_2470 = or(_T_2469, reset) @[Periphery.scala 217:22] + node _T_2472 = eq(_T_2470, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2472 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:217:22)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2473 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2474 = and(_T_2473, _T_2424) @[Periphery.scala 217:22] + when _T_2474 : @[Periphery.scala 217:22] + _T_2435 <= io.in[0].d.bits.opcode @[Periphery.scala 217:22] + _T_2437 <= io.in[0].d.bits.param @[Periphery.scala 217:22] + _T_2439 <= io.in[0].d.bits.size @[Periphery.scala 217:22] + _T_2441 <= io.in[0].d.bits.source @[Periphery.scala 217:22] + _T_2443 <= io.in[0].d.bits.sink @[Periphery.scala 217:22] + _T_2445 <= io.in[0].d.bits.addr_lo @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + reg _T_2476 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_2477 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2479 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2480 = dshl(_T_2479, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2481 = bits(_T_2480, 7, 0) @[package.scala 19:76] + node _T_2482 = not(_T_2481) @[package.scala 19:40] + node _T_2483 = shr(_T_2482, 3) @[Edges.scala 198:59] + node _T_2484 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2486 = eq(_T_2484, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2488 = mux(_T_2486, _T_2483, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2490 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2492 = sub(_T_2490, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2493 = asUInt(_T_2492) @[Edges.scala 208:28] + node _T_2494 = tail(_T_2493, 1) @[Edges.scala 208:28] + node _T_2496 = eq(_T_2490, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2498 = eq(_T_2490, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2500 = eq(_T_2488, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2501 = or(_T_2498, _T_2500) @[Edges.scala 210:37] + node _T_2502 = and(_T_2501, _T_2477) @[Edges.scala 211:22] + node _T_2503 = not(_T_2494) @[Edges.scala 212:27] + node _T_2504 = and(_T_2488, _T_2503) @[Edges.scala 212:25] + when _T_2477 : @[Edges.scala 213:17] + node _T_2505 = mux(_T_2496, _T_2488, _T_2494) @[Edges.scala 214:21] + _T_2490 <= _T_2505 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2506 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2509 = dshl(_T_2508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2510 = bits(_T_2509, 7, 0) @[package.scala 19:76] + node _T_2511 = not(_T_2510) @[package.scala 19:40] + node _T_2512 = shr(_T_2511, 3) @[Edges.scala 198:59] + node _T_2513 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2515 = mux(_T_2513, _T_2512, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2517 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2519 = sub(_T_2517, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2520 = asUInt(_T_2519) @[Edges.scala 208:28] + node _T_2521 = tail(_T_2520, 1) @[Edges.scala 208:28] + node _T_2523 = eq(_T_2517, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2525 = eq(_T_2517, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2527 = eq(_T_2515, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2528 = or(_T_2525, _T_2527) @[Edges.scala 210:37] + node _T_2529 = and(_T_2528, _T_2506) @[Edges.scala 211:22] + node _T_2530 = not(_T_2521) @[Edges.scala 212:27] + node _T_2531 = and(_T_2515, _T_2530) @[Edges.scala 212:25] + when _T_2506 : @[Edges.scala 213:17] + node _T_2532 = mux(_T_2523, _T_2515, _T_2521) @[Edges.scala 214:21] + _T_2517 <= _T_2532 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2534 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + node _T_2535 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 217:22] + node _T_2536 = or(_T_2534, _T_2535) @[Periphery.scala 217:22] + node _T_2538 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2539 = or(_T_2536, _T_2538) @[Periphery.scala 217:22] + node _T_2541 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2542 = or(_T_2539, _T_2541) @[Periphery.scala 217:22] + node _T_2543 = or(_T_2542, reset) @[Periphery.scala 217:22] + node _T_2545 = eq(_T_2543, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2545 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Periphery.scala:217:22)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + wire _T_2547 : UInt<4> + _T_2547 is invalid + _T_2547 <= UInt<4>("h00") + node _T_2548 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2548 : @[Periphery.scala 217:22] + when _T_2501 : @[Periphery.scala 217:22] + node _T_2550 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2547 <= _T_2550 @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2551 = dshr(_T_2476, io.in[0].a.bits.source) @[Periphery.scala 217:22] + node _T_2552 = bits(_T_2551, 0, 0) @[Periphery.scala 217:22] + node _T_2554 = eq(_T_2552, UInt<1>("h00")) @[Periphery.scala 217:22] + node _T_2555 = or(_T_2554, reset) @[Periphery.scala 217:22] + node _T_2557 = eq(_T_2555, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2557 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:217:22)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + wire _T_2559 : UInt<4> + _T_2559 is invalid + _T_2559 <= UInt<4>("h00") + node _T_2560 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2562 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 217:22] + node _T_2563 = and(_T_2560, _T_2562) @[Periphery.scala 217:22] + when _T_2563 : @[Periphery.scala 217:22] + when _T_2528 : @[Periphery.scala 217:22] + node _T_2565 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2559 <= _T_2565 @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2566 = or(_T_2547, _T_2476) @[Periphery.scala 217:22] + node _T_2567 = dshr(_T_2566, io.in[0].d.bits.source) @[Periphery.scala 217:22] + node _T_2568 = bits(_T_2567, 0, 0) @[Periphery.scala 217:22] + node _T_2569 = or(_T_2568, reset) @[Periphery.scala 217:22] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[Periphery.scala 217:22] + when _T_2571 : @[Periphery.scala 217:22] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:217:22)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 217:22] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + skip @[Periphery.scala 217:22] + node _T_2572 = or(_T_2476, _T_2547) @[Periphery.scala 217:22] + node _T_2573 = not(_T_2559) @[Periphery.scala 217:22] + node _T_2574 = and(_T_2572, _T_2573) @[Periphery.scala 217:22] + _T_2476 <= _T_2574 @[Periphery.scala 217:22] + + module TLROM_bootrom : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + wire rom : UInt<32>[1024] @[Rom.scala 40:18] + rom is invalid @[Rom.scala 40:18] + rom[0] <= UInt<32>("h06f") @[Rom.scala 40:18] + rom[1] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[2] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[3] <= UInt<32>("h01020") @[Rom.scala 40:18] + rom[4] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[5] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[6] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[7] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[8] <= UInt<32>("h07374642f") @[Rom.scala 40:18] + rom[9] <= UInt<32>("h02f31762d") @[Rom.scala 40:18] + rom[10] <= UInt<32>("h02f0a0a3b") @[Rom.scala 40:18] + rom[11] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[12] <= UInt<32>("h064646123") @[Rom.scala 40:18] + rom[13] <= UInt<32>("h073736572") @[Rom.scala 40:18] + rom[14] <= UInt<32>("h06c65632d") @[Rom.scala 40:18] + rom[15] <= UInt<32>("h03d20736c") @[Rom.scala 40:18] + rom[16] <= UInt<32>("h03e313c20") @[Rom.scala 40:18] + rom[17] <= UInt<32>("h023090a3b") @[Rom.scala 40:18] + rom[18] <= UInt<32>("h0657a6973") @[Rom.scala 40:18] + rom[19] <= UInt<32>("h06c65632d") @[Rom.scala 40:18] + rom[20] <= UInt<32>("h03d20736c") @[Rom.scala 40:18] + rom[21] <= UInt<32>("h03e313c20") @[Rom.scala 40:18] + rom[22] <= UInt<32>("h063090a3b") @[Rom.scala 40:18] + rom[23] <= UInt<32>("h061706d6f") @[Rom.scala 40:18] + rom[24] <= UInt<32>("h06c626974") @[Rom.scala 40:18] + rom[25] <= UInt<32>("h0203d2065") @[Rom.scala 40:18] + rom[26] <= UInt<32>("h062637522") @[Rom.scala 40:18] + rom[27] <= UInt<32>("h02c726162") @[Rom.scala 40:18] + rom[28] <= UInt<32>("h06b636f72") @[Rom.scala 40:18] + rom[29] <= UInt<32>("h068637465") @[Rom.scala 40:18] + rom[30] <= UInt<32>("h0752d7069") @[Rom.scala 40:18] + rom[31] <= UInt<32>("h06f6e6b6e") @[Rom.scala 40:18] + rom[32] <= UInt<32>("h0642d6e77") @[Rom.scala 40:18] + rom[33] <= UInt<32>("h03b227665") @[Rom.scala 40:18] + rom[34] <= UInt<32>("h06f6d090a") @[Rom.scala 40:18] + rom[35] <= UInt<32>("h0206c6564") @[Rom.scala 40:18] + rom[36] <= UInt<32>("h07522203d") @[Rom.scala 40:18] + rom[37] <= UInt<32>("h061626263") @[Rom.scala 40:18] + rom[38] <= UInt<32>("h06f722c72") @[Rom.scala 40:18] + rom[39] <= UInt<32>("h074656b63") @[Rom.scala 40:18] + rom[40] <= UInt<32>("h070696863") @[Rom.scala 40:18] + rom[41] <= UInt<32>("h06b6e752d") @[Rom.scala 40:18] + rom[42] <= UInt<32>("h06e776f6e") @[Rom.scala 40:18] + rom[43] <= UInt<32>("h090a3b22") @[Rom.scala 40:18] + rom[44] <= UInt<32>("h0203a374c") @[Rom.scala 40:18] + rom[45] <= UInt<32>("h073757063") @[Rom.scala 40:18] + rom[46] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[47] <= UInt<32>("h064612309") @[Rom.scala 40:18] + rom[48] <= UInt<32>("h073657264") @[Rom.scala 40:18] + rom[49] <= UInt<32>("h065632d73") @[Rom.scala 40:18] + rom[50] <= UInt<32>("h020736c6c") @[Rom.scala 40:18] + rom[51] <= UInt<32>("h0313c203d") @[Rom.scala 40:18] + rom[52] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[53] <= UInt<32>("h069732309") @[Rom.scala 40:18] + rom[54] <= UInt<32>("h0632d657a") @[Rom.scala 40:18] + rom[55] <= UInt<32>("h0736c6c65") @[Rom.scala 40:18] + rom[56] <= UInt<32>("h03c203d20") @[Rom.scala 40:18] + rom[57] <= UInt<32>("h0a3b3e30") @[Rom.scala 40:18] + rom[58] <= UInt<32>("h069740909") @[Rom.scala 40:18] + rom[59] <= UInt<32>("h06162656d") @[Rom.scala 40:18] + rom[60] <= UInt<32>("h0662d6573") @[Rom.scala 40:18] + rom[61] <= UInt<32>("h075716572") @[Rom.scala 40:18] + rom[62] <= UInt<32>("h079636e65") @[Rom.scala 40:18] + rom[63] <= UInt<32>("h03c203d20") @[Rom.scala 40:18] + rom[64] <= UInt<32>("h0a3b3e30") @[Rom.scala 40:18] + rom[65] <= UInt<32>("h0314c0909") @[Rom.scala 40:18] + rom[66] <= UInt<32>("h063203a31") @[Rom.scala 40:18] + rom[67] <= UInt<32>("h030407570") @[Rom.scala 40:18] + rom[68] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[69] <= UInt<32>("h069230909") @[Rom.scala 40:18] + rom[70] <= UInt<32>("h07265746e") @[Rom.scala 40:18] + rom[71] <= UInt<32>("h074707572") @[Rom.scala 40:18] + rom[72] <= UInt<32>("h06c65632d") @[Rom.scala 40:18] + rom[73] <= UInt<32>("h03d20736c") @[Rom.scala 40:18] + rom[74] <= UInt<32>("h03e313c20") @[Rom.scala 40:18] + rom[75] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[76] <= UInt<32>("h06f6c6309") @[Rom.scala 40:18] + rom[77] <= UInt<32>("h0662d6b63") @[Rom.scala 40:18] + rom[78] <= UInt<32>("h075716572") @[Rom.scala 40:18] + rom[79] <= UInt<32>("h079636e65") @[Rom.scala 40:18] + rom[80] <= UInt<32>("h03c203d20") @[Rom.scala 40:18] + rom[81] <= UInt<32>("h0a3b3e30") @[Rom.scala 40:18] + rom[82] <= UInt<32>("h063090909") @[Rom.scala 40:18] + rom[83] <= UInt<32>("h061706d6f") @[Rom.scala 40:18] + rom[84] <= UInt<32>("h06c626974") @[Rom.scala 40:18] + rom[85] <= UInt<32>("h0203d2065") @[Rom.scala 40:18] + rom[86] <= UInt<32>("h073697222") @[Rom.scala 40:18] + rom[87] <= UInt<32>("h03b227663") @[Rom.scala 40:18] + rom[88] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[89] <= UInt<32>("h061632d64") @[Rom.scala 40:18] + rom[90] <= UInt<32>("h02d656863") @[Rom.scala 40:18] + rom[91] <= UInt<32>("h0636f6c62") @[Rom.scala 40:18] + rom[92] <= UInt<32>("h069732d6b") @[Rom.scala 40:18] + rom[93] <= UInt<32>("h03d20657a") @[Rom.scala 40:18] + rom[94] <= UInt<32>("h034363c20") @[Rom.scala 40:18] + rom[95] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[96] <= UInt<32>("h02d640909") @[Rom.scala 40:18] + rom[97] <= UInt<32>("h068636163") @[Rom.scala 40:18] + rom[98] <= UInt<32>("h065732d65") @[Rom.scala 40:18] + rom[99] <= UInt<32>("h03d207374") @[Rom.scala 40:18] + rom[100] <= UInt<32>("h034363c20") @[Rom.scala 40:18] + rom[101] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[102] <= UInt<32>("h02d640909") @[Rom.scala 40:18] + rom[103] <= UInt<32>("h068636163") @[Rom.scala 40:18] + rom[104] <= UInt<32>("h069732d65") @[Rom.scala 40:18] + rom[105] <= UInt<32>("h03d20657a") @[Rom.scala 40:18] + rom[106] <= UInt<32>("h036313c20") @[Rom.scala 40:18] + rom[107] <= UInt<32>("h03e343833") @[Rom.scala 40:18] + rom[108] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[109] <= UInt<32>("h0742d6409") @[Rom.scala 40:18] + rom[110] <= UInt<32>("h0732d626c") @[Rom.scala 40:18] + rom[111] <= UInt<32>("h020737465") @[Rom.scala 40:18] + rom[112] <= UInt<32>("h0313c203d") @[Rom.scala 40:18] + rom[113] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[114] <= UInt<32>("h02d640909") @[Rom.scala 40:18] + rom[115] <= UInt<32>("h02d626c74") @[Rom.scala 40:18] + rom[116] <= UInt<32>("h0657a6973") @[Rom.scala 40:18] + rom[117] <= UInt<32>("h03c203d20") @[Rom.scala 40:18] + rom[118] <= UInt<32>("h0a3b3e38") @[Rom.scala 40:18] + rom[119] <= UInt<32>("h064090909") @[Rom.scala 40:18] + rom[120] <= UInt<32>("h063697665") @[Rom.scala 40:18] + rom[121] <= UInt<32>("h079745f65") @[Rom.scala 40:18] + rom[122] <= UInt<32>("h03d206570") @[Rom.scala 40:18] + rom[123] <= UInt<32>("h070632220") @[Rom.scala 40:18] + rom[124] <= UInt<32>("h0a3b2275") @[Rom.scala 40:18] + rom[125] <= UInt<32>("h069090909") @[Rom.scala 40:18] + rom[126] <= UInt<32>("h06361632d") @[Rom.scala 40:18] + rom[127] <= UInt<32>("h0622d6568") @[Rom.scala 40:18] + rom[128] <= UInt<32>("h06b636f6c") @[Rom.scala 40:18] + rom[129] <= UInt<32>("h07a69732d") @[Rom.scala 40:18] + rom[130] <= UInt<32>("h0203d2065") @[Rom.scala 40:18] + rom[131] <= UInt<32>("h03e34363c") @[Rom.scala 40:18] + rom[132] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[133] <= UInt<32>("h0632d6909") @[Rom.scala 40:18] + rom[134] <= UInt<32>("h065686361") @[Rom.scala 40:18] + rom[135] <= UInt<32>("h07465732d") @[Rom.scala 40:18] + rom[136] <= UInt<32>("h0203d2073") @[Rom.scala 40:18] + rom[137] <= UInt<32>("h03e34363c") @[Rom.scala 40:18] + rom[138] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[139] <= UInt<32>("h0632d6909") @[Rom.scala 40:18] + rom[140] <= UInt<32>("h065686361") @[Rom.scala 40:18] + rom[141] <= UInt<32>("h07a69732d") @[Rom.scala 40:18] + rom[142] <= UInt<32>("h0203d2065") @[Rom.scala 40:18] + rom[143] <= UInt<32>("h03336313c") @[Rom.scala 40:18] + rom[144] <= UInt<32>("h03b3e3438") @[Rom.scala 40:18] + rom[145] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[146] <= UInt<32>("h06c742d69") @[Rom.scala 40:18] + rom[147] <= UInt<32>("h065732d62") @[Rom.scala 40:18] + rom[148] <= UInt<32>("h03d207374") @[Rom.scala 40:18] + rom[149] <= UInt<32>("h03e313c20") @[Rom.scala 40:18] + rom[150] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[151] <= UInt<32>("h0742d6909") @[Rom.scala 40:18] + rom[152] <= UInt<32>("h0732d626c") @[Rom.scala 40:18] + rom[153] <= UInt<32>("h020657a69") @[Rom.scala 40:18] + rom[154] <= UInt<32>("h0383c203d") @[Rom.scala 40:18] + rom[155] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[156] <= UInt<32>("h06e690909") @[Rom.scala 40:18] + rom[157] <= UInt<32>("h072726574") @[Rom.scala 40:18] + rom[158] <= UInt<32>("h02d747075") @[Rom.scala 40:18] + rom[159] <= UInt<32>("h0746e6f63") @[Rom.scala 40:18] + rom[160] <= UInt<32>("h06c6c6f72") @[Rom.scala 40:18] + rom[161] <= UInt<32>("h0a3b7265") @[Rom.scala 40:18] + rom[162] <= UInt<32>("h06d090909") @[Rom.scala 40:18] + rom[163] <= UInt<32>("h0742d756d") @[Rom.scala 40:18] + rom[164] <= UInt<32>("h020657079") @[Rom.scala 40:18] + rom[165] <= UInt<32>("h07222203d") @[Rom.scala 40:18] + rom[166] <= UInt<32>("h076637369") @[Rom.scala 40:18] + rom[167] <= UInt<32>("h03376732c") @[Rom.scala 40:18] + rom[168] <= UInt<32>("h0a3b2239") @[Rom.scala 40:18] + rom[169] <= UInt<32>("h06e090909") @[Rom.scala 40:18] + rom[170] <= UInt<32>("h02d747865") @[Rom.scala 40:18] + rom[171] <= UInt<32>("h06576656c") @[Rom.scala 40:18] + rom[172] <= UInt<32>("h061632d6c") @[Rom.scala 40:18] + rom[173] <= UInt<32>("h020656863") @[Rom.scala 40:18] + rom[174] <= UInt<32>("h0263c203d") @[Rom.scala 40:18] + rom[175] <= UInt<32>("h02620344c") @[Rom.scala 40:18] + rom[176] <= UInt<32>("h03b3e314c") @[Rom.scala 40:18] + rom[177] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[178] <= UInt<32>("h020676572") @[Rom.scala 40:18] + rom[179] <= UInt<32>("h0303c203d") @[Rom.scala 40:18] + rom[180] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[181] <= UInt<32>("h069720909") @[Rom.scala 40:18] + rom[182] <= UInt<32>("h02c766373") @[Rom.scala 40:18] + rom[183] <= UInt<32>("h020617369") @[Rom.scala 40:18] + rom[184] <= UInt<32>("h07222203d") @[Rom.scala 40:18] + rom[185] <= UInt<32>("h069343676") @[Rom.scala 40:18] + rom[186] <= UInt<32>("h06466616d") @[Rom.scala 40:18] + rom[187] <= UInt<32>("h03b227363") @[Rom.scala 40:18] + rom[188] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[189] <= UInt<32>("h074617473") @[Rom.scala 40:18] + rom[190] <= UInt<32>("h03d207375") @[Rom.scala 40:18] + rom[191] <= UInt<32>("h06b6f2220") @[Rom.scala 40:18] + rom[192] <= UInt<32>("h03b227961") @[Rom.scala 40:18] + rom[193] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[194] <= UInt<32>("h02d626c74") @[Rom.scala 40:18] + rom[195] <= UInt<32>("h0696c7073") @[Rom.scala 40:18] + rom[196] <= UInt<32>("h090a3b74") @[Rom.scala 40:18] + rom[197] <= UInt<32>("h0a3b7d09") @[Rom.scala 40:18] + rom[198] <= UInt<32>("h0a3b7d09") @[Rom.scala 40:18] + rom[199] <= UInt<32>("h03a314c09") @[Rom.scala 40:18] + rom[200] <= UInt<32>("h06d656d20") @[Rom.scala 40:18] + rom[201] <= UInt<32>("h04079726f") @[Rom.scala 40:18] + rom[202] <= UInt<32>("h030303038") @[Rom.scala 40:18] + rom[203] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[204] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[205] <= UInt<32>("h076656409") @[Rom.scala 40:18] + rom[206] <= UInt<32>("h05f656369") @[Rom.scala 40:18] + rom[207] <= UInt<32>("h065707974") @[Rom.scala 40:18] + rom[208] <= UInt<32>("h022203d20") @[Rom.scala 40:18] + rom[209] <= UInt<32>("h06f6d656d") @[Rom.scala 40:18] + rom[210] <= UInt<32>("h03b227972") @[Rom.scala 40:18] + rom[211] <= UInt<32>("h07209090a") @[Rom.scala 40:18] + rom[212] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[213] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[214] <= UInt<32>("h030303038") @[Rom.scala 40:18] + rom[215] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[216] <= UInt<32>("h031783020") @[Rom.scala 40:18] + rom[217] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[218] <= UInt<32>("h03e303030") @[Rom.scala 40:18] + rom[219] <= UInt<32>("h07d090a3b") @[Rom.scala 40:18] + rom[220] <= UInt<32>("h04c090a3b") @[Rom.scala 40:18] + rom[221] <= UInt<32>("h073203a36") @[Rom.scala 40:18] + rom[222] <= UInt<32>("h07b20636f") @[Rom.scala 40:18] + rom[223] <= UInt<32>("h02309090a") @[Rom.scala 40:18] + rom[224] <= UInt<32>("h072646461") @[Rom.scala 40:18] + rom[225] <= UInt<32>("h02d737365") @[Rom.scala 40:18] + rom[226] <= UInt<32>("h06c6c6563") @[Rom.scala 40:18] + rom[227] <= UInt<32>("h0203d2073") @[Rom.scala 40:18] + rom[228] <= UInt<32>("h03b3e313c") @[Rom.scala 40:18] + rom[229] <= UInt<32>("h02309090a") @[Rom.scala 40:18] + rom[230] <= UInt<32>("h0657a6973") @[Rom.scala 40:18] + rom[231] <= UInt<32>("h06c65632d") @[Rom.scala 40:18] + rom[232] <= UInt<32>("h03d20736c") @[Rom.scala 40:18] + rom[233] <= UInt<32>("h03e313c20") @[Rom.scala 40:18] + rom[234] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[235] <= UInt<32>("h0706d6f63") @[Rom.scala 40:18] + rom[236] <= UInt<32>("h062697461") @[Rom.scala 40:18] + rom[237] <= UInt<32>("h03d20656c") @[Rom.scala 40:18] + rom[238] <= UInt<32>("h063752220") @[Rom.scala 40:18] + rom[239] <= UInt<32>("h072616262") @[Rom.scala 40:18] + rom[240] <= UInt<32>("h0636f722c") @[Rom.scala 40:18] + rom[241] <= UInt<32>("h06374656b") @[Rom.scala 40:18] + rom[242] <= UInt<32>("h02d706968") @[Rom.scala 40:18] + rom[243] <= UInt<32>("h06e6b6e75") @[Rom.scala 40:18] + rom[244] <= UInt<32>("h02d6e776f") @[Rom.scala 40:18] + rom[245] <= UInt<32>("h022636f73") @[Rom.scala 40:18] + rom[246] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[247] <= UInt<32>("h0676e6172") @[Rom.scala 40:18] + rom[248] <= UInt<32>("h0a3b7365") @[Rom.scala 40:18] + rom[249] <= UInt<32>("h0314c0909") @[Rom.scala 40:18] + rom[250] <= UInt<32>("h063203a30") @[Rom.scala 40:18] + rom[251] <= UInt<32>("h0746e696c") @[Rom.scala 40:18] + rom[252] <= UInt<32>("h030303240") @[Rom.scala 40:18] + rom[253] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[254] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[255] <= UInt<32>("h06f630909") @[Rom.scala 40:18] + rom[256] <= UInt<32>("h07461706d") @[Rom.scala 40:18] + rom[257] <= UInt<32>("h0656c6269") @[Rom.scala 40:18] + rom[258] <= UInt<32>("h022203d20") @[Rom.scala 40:18] + rom[259] <= UInt<32>("h063736972") @[Rom.scala 40:18] + rom[260] <= UInt<32>("h06c632c76") @[Rom.scala 40:18] + rom[261] <= UInt<32>("h030746e69") @[Rom.scala 40:18] + rom[262] <= UInt<32>("h090a3b22") @[Rom.scala 40:18] + rom[263] <= UInt<32>("h06e690909") @[Rom.scala 40:18] + rom[264] <= UInt<32>("h072726574") @[Rom.scala 40:18] + rom[265] <= UInt<32>("h073747075") @[Rom.scala 40:18] + rom[266] <= UInt<32>("h07478652d") @[Rom.scala 40:18] + rom[267] <= UInt<32>("h065646e65") @[Rom.scala 40:18] + rom[268] <= UInt<32>("h0203d2064") @[Rom.scala 40:18] + rom[269] <= UInt<32>("h0314c263c") @[Rom.scala 40:18] + rom[270] <= UInt<32>("h020332031") @[Rom.scala 40:18] + rom[271] <= UInt<32>("h031314c26") @[Rom.scala 40:18] + rom[272] <= UInt<32>("h03b3e3720") @[Rom.scala 40:18] + rom[273] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[274] <= UInt<32>("h020676572") @[Rom.scala 40:18] + rom[275] <= UInt<32>("h0303c203d") @[Rom.scala 40:18] + rom[276] <= UInt<32>("h030303278") @[Rom.scala 40:18] + rom[277] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[278] <= UInt<32>("h031783020") @[Rom.scala 40:18] + rom[279] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[280] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[281] <= UInt<32>("h0a3b7d09") @[Rom.scala 40:18] + rom[282] <= UInt<32>("h0384c0909") @[Rom.scala 40:18] + rom[283] <= UInt<32>("h06564203a") @[Rom.scala 40:18] + rom[284] <= UInt<32>("h040677562") @[Rom.scala 40:18] + rom[285] <= UInt<32>("h0a7b2030") @[Rom.scala 40:18] + rom[286] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[287] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[288] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[289] <= UInt<32>("h078302030") @[Rom.scala 40:18] + rom[290] <= UInt<32>("h030303031") @[Rom.scala 40:18] + rom[291] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[292] <= UInt<32>("h0a3b7d09") @[Rom.scala 40:18] + rom[293] <= UInt<32>("h0394c0909") @[Rom.scala 40:18] + rom[294] <= UInt<32>("h06e69203a") @[Rom.scala 40:18] + rom[295] <= UInt<32>("h072726574") @[Rom.scala 40:18] + rom[296] <= UInt<32>("h02d747075") @[Rom.scala 40:18] + rom[297] <= UInt<32>("h0746e6f63") @[Rom.scala 40:18] + rom[298] <= UInt<32>("h06c6c6f72") @[Rom.scala 40:18] + rom[299] <= UInt<32>("h063407265") @[Rom.scala 40:18] + rom[300] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[301] <= UInt<32>("h07b203030") @[Rom.scala 40:18] + rom[302] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[303] <= UInt<32>("h064646123") @[Rom.scala 40:18] + rom[304] <= UInt<32>("h073736572") @[Rom.scala 40:18] + rom[305] <= UInt<32>("h06c65632d") @[Rom.scala 40:18] + rom[306] <= UInt<32>("h03d20736c") @[Rom.scala 40:18] + rom[307] <= UInt<32>("h03e303c20") @[Rom.scala 40:18] + rom[308] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[309] <= UInt<32>("h06e692309") @[Rom.scala 40:18] + rom[310] <= UInt<32>("h072726574") @[Rom.scala 40:18] + rom[311] <= UInt<32>("h02d747075") @[Rom.scala 40:18] + rom[312] <= UInt<32>("h06c6c6563") @[Rom.scala 40:18] + rom[313] <= UInt<32>("h0203d2073") @[Rom.scala 40:18] + rom[314] <= UInt<32>("h03b3e313c") @[Rom.scala 40:18] + rom[315] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[316] <= UInt<32>("h0706d6f63") @[Rom.scala 40:18] + rom[317] <= UInt<32>("h062697461") @[Rom.scala 40:18] + rom[318] <= UInt<32>("h03d20656c") @[Rom.scala 40:18] + rom[319] <= UInt<32>("h069722220") @[Rom.scala 40:18] + rom[320] <= UInt<32>("h02c766373") @[Rom.scala 40:18] + rom[321] <= UInt<32>("h063696c70") @[Rom.scala 40:18] + rom[322] <= UInt<32>("h0a3b2230") @[Rom.scala 40:18] + rom[323] <= UInt<32>("h069090909") @[Rom.scala 40:18] + rom[324] <= UInt<32>("h07265746e") @[Rom.scala 40:18] + rom[325] <= UInt<32>("h074707572") @[Rom.scala 40:18] + rom[326] <= UInt<32>("h06e6f632d") @[Rom.scala 40:18] + rom[327] <= UInt<32>("h06c6f7274") @[Rom.scala 40:18] + rom[328] <= UInt<32>("h03b72656c") @[Rom.scala 40:18] + rom[329] <= UInt<32>("h0909090a") @[Rom.scala 40:18] + rom[330] <= UInt<32>("h065746e69") @[Rom.scala 40:18] + rom[331] <= UInt<32>("h070757272") @[Rom.scala 40:18] + rom[332] <= UInt<32>("h0652d7374") @[Rom.scala 40:18] + rom[333] <= UInt<32>("h06e657478") @[Rom.scala 40:18] + rom[334] <= UInt<32>("h020646564") @[Rom.scala 40:18] + rom[335] <= UInt<32>("h0263c203d") @[Rom.scala 40:18] + rom[336] <= UInt<32>("h02031314c") @[Rom.scala 40:18] + rom[337] <= UInt<32>("h026203131") @[Rom.scala 40:18] + rom[338] <= UInt<32>("h02031314c") @[Rom.scala 40:18] + rom[339] <= UInt<32>("h0a3b3e39") @[Rom.scala 40:18] + rom[340] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[341] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[342] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[343] <= UInt<32>("h030303063") @[Rom.scala 40:18] + rom[344] <= UInt<32>("h020303030") @[Rom.scala 40:18] + rom[345] <= UInt<32>("h030347830") @[Rom.scala 40:18] + rom[346] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[347] <= UInt<32>("h0a3b3e30") @[Rom.scala 40:18] + rom[348] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[349] <= UInt<32>("h076637369") @[Rom.scala 40:18] + rom[350] <= UInt<32>("h065646e2c") @[Rom.scala 40:18] + rom[351] <= UInt<32>("h0203d2076") @[Rom.scala 40:18] + rom[352] <= UInt<32>("h03b3e323c") @[Rom.scala 40:18] + rom[353] <= UInt<32>("h07d09090a") @[Rom.scala 40:18] + rom[354] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[355] <= UInt<32>("h0203a324c") @[Rom.scala 40:18] + rom[356] <= UInt<32>("h06f696d6d") @[Rom.scala 40:18] + rom[357] <= UInt<32>("h030303640") @[Rom.scala 40:18] + rom[358] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[359] <= UInt<32>("h0a7b2030") @[Rom.scala 40:18] + rom[360] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[361] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[362] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[363] <= UInt<32>("h030303036") @[Rom.scala 40:18] + rom[364] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[365] <= UInt<32>("h032783020") @[Rom.scala 40:18] + rom[366] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[367] <= UInt<32>("h03e303030") @[Rom.scala 40:18] + rom[368] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[369] <= UInt<32>("h090a3b7d") @[Rom.scala 40:18] + rom[370] <= UInt<32>("h03a304c09") @[Rom.scala 40:18] + rom[371] <= UInt<32>("h066666f20") @[Rom.scala 40:18] + rom[372] <= UInt<32>("h070696863") @[Rom.scala 40:18] + rom[373] <= UInt<32>("h0746e692d") @[Rom.scala 40:18] + rom[374] <= UInt<32>("h075727265") @[Rom.scala 40:18] + rom[375] <= UInt<32>("h020737470") @[Rom.scala 40:18] + rom[376] <= UInt<32>("h09090a7b") @[Rom.scala 40:18] + rom[377] <= UInt<32>("h0746e6909") @[Rom.scala 40:18] + rom[378] <= UInt<32>("h075727265") @[Rom.scala 40:18] + rom[379] <= UInt<32>("h0702d7470") @[Rom.scala 40:18] + rom[380] <= UInt<32>("h06e657261") @[Rom.scala 40:18] + rom[381] <= UInt<32>("h0203d2074") @[Rom.scala 40:18] + rom[382] <= UInt<32>("h0394c263c") @[Rom.scala 40:18] + rom[383] <= UInt<32>("h090a3b3e") @[Rom.scala 40:18] + rom[384] <= UInt<32>("h06e690909") @[Rom.scala 40:18] + rom[385] <= UInt<32>("h072726574") @[Rom.scala 40:18] + rom[386] <= UInt<32>("h073747075") @[Rom.scala 40:18] + rom[387] <= UInt<32>("h03c203d20") @[Rom.scala 40:18] + rom[388] <= UInt<32>("h03e322031") @[Rom.scala 40:18] + rom[389] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[390] <= UInt<32>("h090a3b7d") @[Rom.scala 40:18] + rom[391] <= UInt<32>("h03a334c09") @[Rom.scala 40:18] + rom[392] <= UInt<32>("h06d6f7220") @[Rom.scala 40:18] + rom[393] <= UInt<32>("h030303140") @[Rom.scala 40:18] + rom[394] <= UInt<32>("h0a7b2030") @[Rom.scala 40:18] + rom[395] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[396] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[397] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[398] <= UInt<32>("h030303031") @[Rom.scala 40:18] + rom[399] <= UInt<32>("h031783020") @[Rom.scala 40:18] + rom[400] <= UInt<32>("h03e303030") @[Rom.scala 40:18] + rom[401] <= UInt<32>("h09090a3b") @[Rom.scala 40:18] + rom[402] <= UInt<32>("h090a3b7d") @[Rom.scala 40:18] + rom[403] <= UInt<32>("h03a344c09") @[Rom.scala 40:18] + rom[404] <= UInt<32>("h06d6f7220") @[Rom.scala 40:18] + rom[405] <= UInt<32>("h030306140") @[Rom.scala 40:18] + rom[406] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[407] <= UInt<32>("h090a7b20") @[Rom.scala 40:18] + rom[408] <= UInt<32>("h06f630909") @[Rom.scala 40:18] + rom[409] <= UInt<32>("h07461706d") @[Rom.scala 40:18] + rom[410] <= UInt<32>("h0656c6269") @[Rom.scala 40:18] + rom[411] <= UInt<32>("h022203d20") @[Rom.scala 40:18] + rom[412] <= UInt<32>("h062626375") @[Rom.scala 40:18] + rom[413] <= UInt<32>("h0632c7261") @[Rom.scala 40:18] + rom[414] <= UInt<32>("h065686361") @[Rom.scala 40:18] + rom[415] <= UInt<32>("h0656c6261") @[Rom.scala 40:18] + rom[416] <= UInt<32>("h072657a2d") @[Rom.scala 40:18] + rom[417] <= UInt<32>("h0a3b226f") @[Rom.scala 40:18] + rom[418] <= UInt<32>("h072090909") @[Rom.scala 40:18] + rom[419] <= UInt<32>("h03d206765") @[Rom.scala 40:18] + rom[420] <= UInt<32>("h078303c20") @[Rom.scala 40:18] + rom[421] <= UInt<32>("h030303061") @[Rom.scala 40:18] + rom[422] <= UInt<32>("h020303030") @[Rom.scala 40:18] + rom[423] <= UInt<32>("h030327830") @[Rom.scala 40:18] + rom[424] <= UInt<32>("h030303030") @[Rom.scala 40:18] + rom[425] <= UInt<32>("h0a3b3e30") @[Rom.scala 40:18] + rom[426] <= UInt<32>("h03b7d0909") @[Rom.scala 40:18] + rom[427] <= UInt<32>("h03b7d090a") @[Rom.scala 40:18] + rom[428] <= UInt<32>("h0a3b7d0a") @[Rom.scala 40:18] + rom[429] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[430] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[431] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[432] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[433] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[434] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[435] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[436] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[437] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[438] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[439] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[440] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[441] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[442] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[443] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[444] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[445] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[446] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[447] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[448] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[449] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[450] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[451] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[452] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[453] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[454] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[455] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[456] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[457] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[458] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[459] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[460] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[461] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[462] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[463] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[464] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[465] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[466] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[467] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[468] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[469] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[470] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[471] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[472] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[473] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[474] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[475] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[476] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[477] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[478] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[479] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[480] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[481] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[482] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[483] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[484] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[485] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[486] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[487] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[488] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[489] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[490] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[491] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[492] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[493] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[494] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[495] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[496] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[497] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[498] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[499] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[500] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[501] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[502] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[503] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[504] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[505] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[506] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[507] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[508] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[509] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[510] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[511] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[512] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[513] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[514] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[515] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[516] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[517] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[518] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[519] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[520] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[521] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[522] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[523] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[524] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[525] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[526] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[527] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[528] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[529] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[530] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[531] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[532] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[533] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[534] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[535] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[536] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[537] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[538] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[539] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[540] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[541] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[542] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[543] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[544] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[545] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[546] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[547] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[548] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[549] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[550] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[551] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[552] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[553] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[554] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[555] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[556] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[557] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[558] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[559] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[560] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[561] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[562] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[563] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[564] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[565] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[566] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[567] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[568] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[569] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[570] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[571] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[572] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[573] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[574] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[575] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[576] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[577] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[578] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[579] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[580] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[581] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[582] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[583] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[584] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[585] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[586] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[587] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[588] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[589] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[590] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[591] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[592] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[593] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[594] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[595] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[596] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[597] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[598] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[599] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[600] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[601] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[602] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[603] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[604] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[605] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[606] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[607] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[608] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[609] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[610] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[611] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[612] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[613] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[614] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[615] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[616] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[617] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[618] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[619] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[620] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[621] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[622] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[623] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[624] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[625] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[626] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[627] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[628] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[629] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[630] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[631] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[632] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[633] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[634] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[635] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[636] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[637] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[638] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[639] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[640] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[641] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[642] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[643] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[644] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[645] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[646] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[647] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[648] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[649] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[650] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[651] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[652] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[653] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[654] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[655] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[656] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[657] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[658] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[659] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[660] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[661] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[662] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[663] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[664] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[665] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[666] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[667] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[668] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[669] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[670] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[671] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[672] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[673] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[674] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[675] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[676] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[677] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[678] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[679] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[680] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[681] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[682] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[683] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[684] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[685] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[686] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[687] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[688] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[689] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[690] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[691] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[692] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[693] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[694] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[695] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[696] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[697] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[698] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[699] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[700] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[701] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[702] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[703] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[704] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[705] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[706] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[707] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[708] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[709] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[710] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[711] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[712] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[713] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[714] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[715] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[716] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[717] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[718] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[719] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[720] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[721] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[722] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[723] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[724] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[725] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[726] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[727] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[728] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[729] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[730] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[731] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[732] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[733] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[734] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[735] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[736] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[737] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[738] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[739] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[740] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[741] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[742] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[743] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[744] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[745] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[746] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[747] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[748] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[749] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[750] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[751] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[752] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[753] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[754] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[755] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[756] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[757] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[758] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[759] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[760] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[761] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[762] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[763] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[764] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[765] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[766] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[767] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[768] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[769] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[770] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[771] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[772] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[773] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[774] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[775] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[776] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[777] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[778] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[779] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[780] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[781] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[782] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[783] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[784] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[785] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[786] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[787] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[788] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[789] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[790] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[791] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[792] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[793] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[794] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[795] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[796] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[797] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[798] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[799] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[800] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[801] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[802] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[803] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[804] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[805] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[806] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[807] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[808] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[809] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[810] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[811] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[812] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[813] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[814] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[815] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[816] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[817] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[818] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[819] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[820] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[821] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[822] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[823] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[824] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[825] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[826] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[827] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[828] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[829] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[830] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[831] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[832] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[833] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[834] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[835] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[836] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[837] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[838] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[839] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[840] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[841] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[842] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[843] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[844] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[845] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[846] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[847] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[848] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[849] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[850] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[851] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[852] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[853] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[854] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[855] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[856] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[857] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[858] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[859] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[860] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[861] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[862] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[863] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[864] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[865] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[866] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[867] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[868] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[869] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[870] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[871] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[872] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[873] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[874] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[875] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[876] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[877] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[878] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[879] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[880] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[881] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[882] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[883] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[884] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[885] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[886] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[887] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[888] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[889] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[890] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[891] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[892] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[893] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[894] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[895] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[896] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[897] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[898] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[899] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[900] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[901] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[902] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[903] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[904] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[905] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[906] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[907] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[908] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[909] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[910] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[911] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[912] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[913] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[914] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[915] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[916] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[917] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[918] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[919] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[920] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[921] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[922] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[923] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[924] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[925] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[926] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[927] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[928] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[929] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[930] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[931] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[932] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[933] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[934] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[935] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[936] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[937] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[938] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[939] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[940] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[941] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[942] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[943] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[944] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[945] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[946] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[947] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[948] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[949] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[950] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[951] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[952] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[953] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[954] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[955] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[956] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[957] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[958] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[959] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[960] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[961] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[962] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[963] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[964] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[965] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[966] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[967] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[968] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[969] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[970] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[971] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[972] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[973] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[974] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[975] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[976] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[977] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[978] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[979] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[980] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[981] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[982] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[983] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[984] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[985] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[986] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[987] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[988] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[989] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[990] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[991] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[992] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[993] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[994] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[995] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[996] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[997] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[998] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[999] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1000] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1001] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1002] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1003] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1004] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1005] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1006] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1007] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1008] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1009] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1010] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1011] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1012] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1013] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1014] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1015] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1016] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1017] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1018] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1019] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1020] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1021] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1022] <= UInt<32>("h00") @[Rom.scala 40:18] + rom[1023] <= UInt<32>("h00") @[Rom.scala 40:18] + io.in.0.d.valid <= io.in.0.a.valid @[Rom.scala 42:16] + io.in.0.a.ready <= io.in.0.d.ready @[Rom.scala 43:16] + node index = bits(io.in.0.a.bits.address, 11, 2) @[Rom.scala 45:34] + wire _T_2417 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>} @[Edges.scala 633:17] + _T_2417 is invalid @[Edges.scala 633:17] + _T_2417.opcode <= UInt<1>("h01") @[Edges.scala 634:15] + _T_2417.param <= UInt<1>("h00") @[Edges.scala 635:15] + _T_2417.size <= io.in.0.a.bits.size @[Edges.scala 636:15] + _T_2417.source <= io.in.0.a.bits.source @[Edges.scala 637:15] + _T_2417.sink <= UInt<1>("h00") @[Edges.scala 638:15] + node _T_2428 = bits(io.in.0.a.bits.address, 1, 0) @[Edges.scala 172:47] + _T_2417.addr_lo <= _T_2428 @[Edges.scala 639:15] + _T_2417.data <= rom[index] @[Edges.scala 640:15] + _T_2417.error <= UInt<1>("h00") @[Edges.scala 641:15] + io.in.0.d.bits <- _T_2417 @[Rom.scala 46:15] + io.in.0.b.valid <= UInt<1>("h00") @[Rom.scala 49:16] + io.in.0.c.ready <= UInt<1>("h01") @[Rom.scala 50:16] + io.in.0.e.ready <= UInt<1>("h01") @[Rom.scala 51:16] + + module Repeater_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLFragmenter_bootrom : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg _T_531 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + reg _T_533 : UInt, clock @[Fragmenter.scala 136:22] + node _T_534 = bits(io.out.0.d.bits.source, 3, 0) @[Fragmenter.scala 137:39] + node _T_536 = eq(_T_531, UInt<1>("h00")) @[Fragmenter.scala 138:27] + node _T_538 = bits(io.out.0.d.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_539 = dshl(UInt<1>("h01"), _T_538) @[OneHot.scala 49:12] + node _T_540 = bits(_T_539, 2, 0) @[OneHot.scala 49:37] + node _T_542 = asUInt(asSInt(UInt<2>("h03"))) @[package.scala 19:64] + node _T_543 = dshl(_T_542, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_544 = bits(_T_543, 1, 0) @[package.scala 19:76] + node _T_545 = not(_T_544) @[package.scala 19:40] + node _T_546 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_548 = shl(_T_534, 0) @[Fragmenter.scala 144:38] + node _T_549 = shr(_T_545, 2) @[Fragmenter.scala 145:34] + node _T_551 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Fragmenter.scala 146:15] + node _T_552 = and(_T_548, _T_549) @[Fragmenter.scala 146:48] + node _T_554 = eq(_T_552, UInt<1>("h00")) @[Fragmenter.scala 146:63] + node _T_555 = or(_T_551, _T_554) @[Fragmenter.scala 146:28] + node _T_556 = or(_T_555, reset) @[Fragmenter.scala 146:14] + node _T_558 = eq(_T_556, UInt<1>("h00")) @[Fragmenter.scala 146:14] + when _T_558 : @[Fragmenter.scala 146:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:146 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n") @[Fragmenter.scala 146:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 146:14] + skip @[Fragmenter.scala 146:14] + node _T_560 = mux(UInt<1>("h01"), _T_549, UInt<1>("h00")) @[Fragmenter.scala 147:48] + node _T_561 = or(_T_548, _T_560) @[Fragmenter.scala 147:43] + node _T_563 = shr(_T_540, 2) @[Fragmenter.scala 148:58] + node _T_564 = mux(UInt<1>("h01"), UInt<1>("h01"), _T_563) @[Fragmenter.scala 148:30] + node _T_565 = shl(_T_534, 2) @[Fragmenter.scala 150:45] + node _T_566 = or(_T_565, _T_545) @[Fragmenter.scala 150:67] + node _T_567 = shl(_T_566, 1) @[package.scala 17:29] + node _T_569 = or(_T_567, UInt<1>("h01")) @[package.scala 17:34] + node _T_571 = cat(UInt<1>("h00"), _T_566) @[Cat.scala 30:58] + node _T_572 = not(_T_571) @[package.scala 17:47] + node _T_573 = and(_T_569, _T_572) @[package.scala 17:45] + node _T_574 = bits(_T_573, 6, 4) @[OneHot.scala 26:18] + node _T_575 = bits(_T_573, 3, 0) @[OneHot.scala 27:18] + node _T_577 = neq(_T_574, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_578 = or(_T_574, _T_575) @[OneHot.scala 28:28] + node _T_579 = bits(_T_578, 3, 2) @[OneHot.scala 26:18] + node _T_580 = bits(_T_578, 1, 0) @[OneHot.scala 27:18] + node _T_582 = neq(_T_579, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_583 = or(_T_579, _T_580) @[OneHot.scala 28:28] + node _T_584 = bits(_T_583, 1, 1) @[CircuitMath.scala 30:8] + node _T_585 = cat(_T_582, _T_584) @[Cat.scala 30:58] + node _T_586 = cat(_T_577, _T_585) @[Cat.scala 30:58] + node _T_587 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_587 : @[Fragmenter.scala 152:27] + node _T_588 = sub(_T_531, _T_564) @[Fragmenter.scala 153:53] + node _T_589 = asUInt(_T_588) @[Fragmenter.scala 153:53] + node _T_590 = tail(_T_589, 1) @[Fragmenter.scala 153:53] + node _T_591 = mux(_T_536, _T_561, _T_590) @[Fragmenter.scala 153:22] + _T_531 <= _T_591 @[Fragmenter.scala 153:16] + when _T_536 : @[Fragmenter.scala 154:23] + _T_533 <= _T_586 @[Fragmenter.scala 154:31] + skip @[Fragmenter.scala 154:23] + skip @[Fragmenter.scala 152:27] + node _T_593 = eq(UInt<1>("h01"), UInt<1>("h00")) @[Fragmenter.scala 158:18] + node _T_595 = neq(_T_534, UInt<1>("h00")) @[Fragmenter.scala 158:41] + node _T_596 = and(_T_593, _T_595) @[Fragmenter.scala 158:28] + node _T_597 = or(io.in.0.d.ready, _T_596) @[Fragmenter.scala 159:33] + io.out.0.d.ready <= _T_597 @[Fragmenter.scala 159:19] + node _T_599 = eq(_T_596, UInt<1>("h00")) @[Fragmenter.scala 160:37] + node _T_600 = and(io.out.0.d.valid, _T_599) @[Fragmenter.scala 160:34] + io.in.0.d.valid <= _T_600 @[Fragmenter.scala 160:19] + io.in.0.d.bits <- io.out.0.d.bits @[Fragmenter.scala 161:19] + node _T_601 = not(_T_545) @[Fragmenter.scala 162:49] + node _T_602 = and(io.out.0.d.bits.addr_lo, _T_601) @[Fragmenter.scala 162:47] + io.in.0.d.bits.addr_lo <= _T_602 @[Fragmenter.scala 162:25] + node _T_603 = shr(io.out.0.d.bits.source, 4) @[Fragmenter.scala 163:45] + io.in.0.d.bits.source <= _T_603 @[Fragmenter.scala 163:24] + node _T_604 = mux(_T_536, _T_586, _T_533) @[Fragmenter.scala 164:30] + io.in.0.d.bits.size <= _T_604 @[Fragmenter.scala 164:24] + reg _T_606 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_607 = or(_T_606, io.out.0.d.bits.error) @[Fragmenter.scala 168:29] + node _T_608 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_608 : @[Fragmenter.scala 169:27] + node _T_610 = mux(_T_596, _T_607, UInt<1>("h00")) @[Fragmenter.scala 169:43] + _T_606 <= _T_610 @[Fragmenter.scala 169:37] + skip @[Fragmenter.scala 169:27] + io.in.0.d.bits.error <= _T_607 @[Fragmenter.scala 170:23] + inst Repeater of Repeater_1 @[Fragmenter.scala 190:28] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.enq <- io.in.0.a @[Fragmenter.scala 191:23] + node _T_614 = xor(Repeater.io.deq.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_615 = cvt(_T_614) @[Parameters.scala 117:49] + node _T_617 = and(_T_615, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_618 = asSInt(_T_617) @[Parameters.scala 117:52] + node _T_620 = eq(_T_618, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_623 : UInt<1>[1] @[Parameters.scala 112:36] + _T_623 is invalid @[Parameters.scala 112:36] + _T_623[0] <= _T_620 @[Parameters.scala 112:36] + node _T_633 = eq(UInt<3>("h05"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_634 = mux(_T_633, UInt<2>("h02"), UInt<2>("h02")) @[Mux.scala 46:16] + node _T_635 = eq(UInt<3>("h04"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_636 = mux(_T_635, UInt<2>("h02"), _T_634) @[Mux.scala 46:16] + node _T_637 = eq(UInt<2>("h03"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_638 = mux(_T_637, UInt<2>("h02"), _T_636) @[Mux.scala 46:16] + node _T_639 = eq(UInt<2>("h02"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_640 = mux(_T_639, UInt<2>("h02"), _T_638) @[Mux.scala 46:16] + node _T_641 = eq(UInt<1>("h01"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_642 = mux(_T_641, UInt<2>("h02"), _T_640) @[Mux.scala 46:16] + node _T_643 = eq(UInt<1>("h00"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_644 = mux(_T_643, UInt<2>("h02"), _T_642) @[Mux.scala 46:16] + node _T_645 = gt(Repeater.io.deq.bits.size, _T_644) @[Fragmenter.scala 213:29] + node _T_646 = mux(_T_645, _T_644, Repeater.io.deq.bits.size) @[Fragmenter.scala 213:22] + node _T_648 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_649 = dshl(_T_648, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_650 = bits(_T_649, 5, 0) @[package.scala 19:76] + node _T_651 = not(_T_650) @[package.scala 19:40] + node _T_653 = asUInt(asSInt(UInt<2>("h03"))) @[package.scala 19:64] + node _T_654 = dshl(_T_653, _T_646) @[package.scala 19:71] + node _T_655 = bits(_T_654, 1, 0) @[package.scala 19:76] + node _T_656 = not(_T_655) @[package.scala 19:40] + node _T_657 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_662 = mux(UInt<1>("h00"), UInt<1>("h00"), _T_656) @[Fragmenter.scala 217:22] + reg _T_664 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[Fragmenter.scala 220:27] + node _T_667 = shr(_T_651, 2) @[Fragmenter.scala 221:46] + node _T_669 = sub(_T_664, UInt<1>("h01")) @[Fragmenter.scala 221:77] + node _T_670 = asUInt(_T_669) @[Fragmenter.scala 221:77] + node _T_671 = tail(_T_670, 1) @[Fragmenter.scala 221:77] + node _T_672 = mux(_T_666, _T_667, _T_671) @[Fragmenter.scala 221:28] + node _T_673 = not(_T_672) @[Fragmenter.scala 222:26] + node _T_674 = shr(_T_662, 2) @[Fragmenter.scala 222:48] + node _T_675 = or(_T_673, _T_674) @[Fragmenter.scala 222:39] + node _T_676 = not(_T_675) @[Fragmenter.scala 222:24] + node _T_677 = shr(_T_672, 0) @[Fragmenter.scala 223:38] + node _T_678 = not(_T_677) @[Fragmenter.scala 223:24] + node _T_679 = shr(_T_656, 2) @[Fragmenter.scala 223:82] + node _T_680 = or(_T_678, _T_679) @[Fragmenter.scala 223:70] + node _T_681 = not(_T_680) @[Fragmenter.scala 223:22] + node _T_682 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Fragmenter.scala 225:27] + _T_664 <= _T_676 @[Fragmenter.scala 225:36] + skip @[Fragmenter.scala 225:27] + node _T_684 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Fragmenter.scala 227:29] + node _T_686 = neq(_T_681, UInt<1>("h00")) @[Fragmenter.scala 227:51] + node _T_687 = and(_T_684, _T_686) @[Fragmenter.scala 227:39] + Repeater.io.repeat <= _T_687 @[Fragmenter.scala 227:26] + io.out.0.a <- Repeater.io.deq @[Fragmenter.scala 228:13] + node _T_688 = not(_T_681) @[Fragmenter.scala 229:50] + node _T_689 = shl(_T_688, 2) @[Fragmenter.scala 229:60] + node _T_690 = and(_T_689, _T_651) @[Fragmenter.scala 229:81] + node _T_691 = or(Repeater.io.deq.bits.address, _T_690) @[Fragmenter.scala 229:47] + io.out.0.a.bits.address <= _T_691 @[Fragmenter.scala 229:26] + node _T_692 = cat(Repeater.io.deq.bits.source, _T_681) @[Cat.scala 30:58] + io.out.0.a.bits.source <= _T_692 @[Fragmenter.scala 230:25] + io.out.0.a.bits.size <= _T_646 @[Fragmenter.scala 231:23] + node _T_694 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 234:15] + node _T_696 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Fragmenter.scala 234:36] + node _T_697 = or(_T_694, _T_696) @[Fragmenter.scala 234:33] + node _T_698 = or(_T_697, reset) @[Fragmenter.scala 234:14] + node _T_700 = eq(_T_698, UInt<1>("h00")) @[Fragmenter.scala 234:14] + when _T_700 : @[Fragmenter.scala 234:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:234 assert (!repeater.io.full || !aHasData)\n") @[Fragmenter.scala 234:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 234:14] + skip @[Fragmenter.scala 234:14] + io.out.0.a.bits.data <= io.in.0.a.bits.data @[Fragmenter.scala 235:23] + node _T_703 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 237:15] + node _T_704 = eq(Repeater.io.deq.bits.mask, UInt<4>("h0f")) @[Fragmenter.scala 237:51] + node _T_705 = or(_T_703, _T_704) @[Fragmenter.scala 237:33] + node _T_706 = or(_T_705, reset) @[Fragmenter.scala 237:14] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 237:14] + when _T_708 : @[Fragmenter.scala 237:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") @[Fragmenter.scala 237:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 237:14] + skip @[Fragmenter.scala 237:14] + node _T_709 = mux(Repeater.io.full, UInt<4>("h0f"), io.in.0.a.bits.mask) @[Fragmenter.scala 238:29] + io.out.0.a.bits.mask <= _T_709 @[Fragmenter.scala 238:23] + io.in.0.b.valid <= UInt<1>("h00") @[Fragmenter.scala 241:18] + io.in.0.c.ready <= UInt<1>("h01") @[Fragmenter.scala 242:18] + io.in.0.e.ready <= UInt<1>("h01") @[Fragmenter.scala 243:18] + io.out.0.b.ready <= UInt<1>("h01") @[Fragmenter.scala 244:19] + io.out.0.c.valid <= UInt<1>("h00") @[Fragmenter.scala 245:19] + io.out.0.e.valid <= UInt<1>("h00") @[Fragmenter.scala 246:19] + + module TLMonitor_10 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 312:78] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 312:78] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_608 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:312:78)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 1, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = cat(_T_665, _T_662) @[Cat.scala 30:58] + node _T_673 = cat(_T_671, _T_668) @[Cat.scala 30:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 30:58] + node _T_676 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:78] + when _T_676 : @[Periphery.scala 312:78] + node _T_679 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_681 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_682 = cvt(_T_681) @[Parameters.scala 117:49] + node _T_684 = and(_T_682, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_685 = asSInt(_T_684) @[Parameters.scala 117:52] + node _T_687 = eq(_T_685, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = and(_T_679, _T_687) @[Parameters.scala 132:56] + node _T_690 = or(UInt<1>("h00"), _T_688) @[Parameters.scala 134:30] + node _T_691 = or(_T_690, reset) @[Periphery.scala 312:78] + node _T_693 = eq(_T_691, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_693 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_694 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_696 = eq(_T_694, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_696 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_698 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_699 = or(_T_698, reset) @[Periphery.scala 312:78] + node _T_701 = eq(_T_699, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_701 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_702 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_704 = eq(_T_702, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_704 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_706 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_707 = or(_T_706, reset) @[Periphery.scala 312:78] + node _T_709 = eq(_T_707, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_709 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:312:78)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_710 = not(io.in[0].a.bits.mask) @[Periphery.scala 312:78] + node _T_712 = eq(_T_710, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_713 = or(_T_712, reset) @[Periphery.scala 312:78] + node _T_715 = eq(_T_713, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_715 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_717 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:78] + when _T_717 : @[Periphery.scala 312:78] + node _T_720 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_722 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_723 = and(_T_720, _T_722) @[Parameters.scala 63:37] + node _T_724 = or(UInt<1>("h00"), _T_723) @[Parameters.scala 132:31] + node _T_726 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_727 = cvt(_T_726) @[Parameters.scala 117:49] + node _T_729 = and(_T_727, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_730 = asSInt(_T_729) @[Parameters.scala 117:52] + node _T_732 = eq(_T_730, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_733 = and(_T_724, _T_732) @[Parameters.scala 132:56] + node _T_735 = or(UInt<1>("h00"), _T_733) @[Parameters.scala 134:30] + node _T_736 = or(_T_735, reset) @[Periphery.scala 312:78] + node _T_738 = eq(_T_736, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_738 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_739 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_741 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_742 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_744 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_746 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_747 = or(_T_746, reset) @[Periphery.scala 312:78] + node _T_749 = eq(_T_747, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_749 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_750 = eq(io.in[0].a.bits.mask, _T_674) @[Periphery.scala 312:78] + node _T_751 = or(_T_750, reset) @[Periphery.scala 312:78] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_753 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_755 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_755 : @[Periphery.scala 312:78] + node _T_758 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_760 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_761 = cvt(_T_760) @[Parameters.scala 117:49] + node _T_763 = and(_T_761, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_764 = asSInt(_T_763) @[Parameters.scala 117:52] + node _T_766 = eq(_T_764, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_767 = and(_T_758, _T_766) @[Parameters.scala 132:56] + node _T_769 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 134:30] + node _T_770 = or(_T_769, reset) @[Periphery.scala 312:78] + node _T_772 = eq(_T_770, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_772 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_773 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_775 = eq(_T_773, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_775 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_776 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_778 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_780 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_781 = or(_T_780, reset) @[Periphery.scala 312:78] + node _T_783 = eq(_T_781, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_783 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_784 = eq(io.in[0].a.bits.mask, _T_674) @[Periphery.scala 312:78] + node _T_785 = or(_T_784, reset) @[Periphery.scala 312:78] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_787 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_789 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:78] + when _T_789 : @[Periphery.scala 312:78] + node _T_792 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_794 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_795 = cvt(_T_794) @[Parameters.scala 117:49] + node _T_797 = and(_T_795, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_798 = asSInt(_T_797) @[Parameters.scala 117:52] + node _T_800 = eq(_T_798, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_801 = and(_T_792, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[Periphery.scala 312:78] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_806 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_807 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_809 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_810 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_812 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_815 = or(_T_814, reset) @[Periphery.scala 312:78] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_817 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_818 = not(_T_674) @[Periphery.scala 312:78] + node _T_819 = and(io.in[0].a.bits.mask, _T_818) @[Periphery.scala 312:78] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_822 = or(_T_821, reset) @[Periphery.scala 312:78] + node _T_824 = eq(_T_822, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_824 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_826 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:78] + when _T_826 : @[Periphery.scala 312:78] + node _T_829 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_831 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_832 = cvt(_T_831) @[Parameters.scala 117:49] + node _T_834 = and(_T_832, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_835 = asSInt(_T_834) @[Parameters.scala 117:52] + node _T_837 = eq(_T_835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_838 = and(_T_829, _T_837) @[Parameters.scala 132:56] + node _T_840 = or(UInt<1>("h00"), _T_838) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[Periphery.scala 312:78] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_843 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_844 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_846 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_847 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_849 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_851 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_852 = or(_T_851, reset) @[Periphery.scala 312:78] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_854 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:312:78)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_855 = eq(io.in[0].a.bits.mask, _T_674) @[Periphery.scala 312:78] + node _T_856 = or(_T_855, reset) @[Periphery.scala 312:78] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_858 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 312:78] + when _T_860 : @[Periphery.scala 312:78] + node _T_863 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_865 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_872 = and(_T_863, _T_871) @[Parameters.scala 132:56] + node _T_874 = or(UInt<1>("h00"), _T_872) @[Parameters.scala 134:30] + node _T_875 = or(_T_874, reset) @[Periphery.scala 312:78] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_877 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_878 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_880 = eq(_T_878, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_880 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_881 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_883 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_885 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_886 = or(_T_885, reset) @[Periphery.scala 312:78] + node _T_888 = eq(_T_886, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_888 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:312:78)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_889 = eq(io.in[0].a.bits.mask, _T_674) @[Periphery.scala 312:78] + node _T_890 = or(_T_889, reset) @[Periphery.scala 312:78] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_892 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_894 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:78] + when _T_894 : @[Periphery.scala 312:78] + node _T_897 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_899 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_900 = cvt(_T_899) @[Parameters.scala 117:49] + node _T_902 = and(_T_900, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_903 = asSInt(_T_902) @[Parameters.scala 117:52] + node _T_905 = eq(_T_903, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_906 = and(_T_897, _T_905) @[Parameters.scala 132:56] + node _T_908 = or(UInt<1>("h00"), _T_906) @[Parameters.scala 134:30] + node _T_909 = or(_T_908, reset) @[Periphery.scala 312:78] + node _T_911 = eq(_T_909, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_911 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_912 = or(_T_630, reset) @[Periphery.scala 312:78] + node _T_914 = eq(_T_912, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_914 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_915 = or(_T_638, reset) @[Periphery.scala 312:78] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_917 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_918 = eq(io.in[0].a.bits.mask, _T_674) @[Periphery.scala 312:78] + node _T_919 = or(_T_918, reset) @[Periphery.scala 312:78] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_921 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + when io.in[0].b.valid : @[Periphery.scala 312:78] + node _T_923 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_924 = or(_T_923, reset) @[Periphery.scala 312:78] + node _T_926 = eq(_T_924, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_926 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:312:78)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_928 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_929 = cvt(_T_928) @[Parameters.scala 117:49] + node _T_931 = and(_T_929, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_932 = asSInt(_T_931) @[Parameters.scala 117:52] + node _T_934 = eq(_T_932, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_937 : UInt<1>[1] @[Parameters.scala 110:36] + _T_937 is invalid @[Parameters.scala 110:36] + _T_937[0] <= _T_934 @[Parameters.scala 110:36] + node _T_942 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_943 = dshl(_T_942, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_944 = bits(_T_943, 5, 0) @[package.scala 19:76] + node _T_945 = not(_T_944) @[package.scala 19:40] + node _T_946 = and(io.in[0].b.bits.address, _T_945) @[Edges.scala 17:16] + node _T_948 = eq(_T_946, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_950 = bits(io.in[0].b.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_951 = dshl(UInt<1>("h01"), _T_950) @[OneHot.scala 49:12] + node _T_952 = bits(_T_951, 1, 0) @[OneHot.scala 49:37] + node _T_954 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_956 = bits(_T_952, 1, 1) @[package.scala 44:26] + node _T_957 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[package.scala 46:20] + node _T_960 = and(UInt<1>("h01"), _T_959) @[package.scala 49:27] + node _T_961 = and(_T_956, _T_960) @[package.scala 50:38] + node _T_962 = or(_T_954, _T_961) @[package.scala 50:29] + node _T_963 = and(UInt<1>("h01"), _T_957) @[package.scala 49:27] + node _T_964 = and(_T_956, _T_963) @[package.scala 50:38] + node _T_965 = or(_T_954, _T_964) @[package.scala 50:29] + node _T_966 = bits(_T_952, 0, 0) @[package.scala 44:26] + node _T_967 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[package.scala 46:20] + node _T_970 = and(_T_960, _T_969) @[package.scala 49:27] + node _T_971 = and(_T_966, _T_970) @[package.scala 50:38] + node _T_972 = or(_T_962, _T_971) @[package.scala 50:29] + node _T_973 = and(_T_960, _T_967) @[package.scala 49:27] + node _T_974 = and(_T_966, _T_973) @[package.scala 50:38] + node _T_975 = or(_T_962, _T_974) @[package.scala 50:29] + node _T_976 = and(_T_963, _T_969) @[package.scala 49:27] + node _T_977 = and(_T_966, _T_976) @[package.scala 50:38] + node _T_978 = or(_T_965, _T_977) @[package.scala 50:29] + node _T_979 = and(_T_963, _T_967) @[package.scala 49:27] + node _T_980 = and(_T_966, _T_979) @[package.scala 50:38] + node _T_981 = or(_T_965, _T_980) @[package.scala 50:29] + node _T_982 = cat(_T_975, _T_972) @[Cat.scala 30:58] + node _T_983 = cat(_T_981, _T_978) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, _T_982) @[Cat.scala 30:58] + node _T_986 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:78] + when _T_986 : @[Periphery.scala 312:78] + node _T_988 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_989 = not(_T_988) @[Parameters.scala 37:9] + node _T_991 = or(_T_989, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_992 = not(_T_991) @[Parameters.scala 37:7] + node _T_994 = eq(_T_992, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_996 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_998 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1001 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1001 is invalid @[Parameters.scala 228:27] + _T_1001[0] <= _T_994 @[Parameters.scala 228:27] + _T_1001[1] <= _T_996 @[Parameters.scala 228:27] + _T_1001[2] <= _T_998 @[Parameters.scala 228:27] + node _T_1009 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1011 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1012 = and(_T_1009, _T_1011) @[Parameters.scala 63:37] + node _T_1015 = mux(_T_1001[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1017 = mux(_T_1001[1], _T_1012, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1019 = mux(_T_1001[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1021 = or(_T_1015, _T_1017) @[Mux.scala 19:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 19:72] + wire _T_1024 : UInt<1> @[Mux.scala 19:72] + _T_1024 is invalid @[Mux.scala 19:72] + _T_1024 <= _T_1022 @[Mux.scala 19:72] + node _T_1025 = or(_T_1024, reset) @[Periphery.scala 312:78] + node _T_1027 = eq(_T_1025, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1027 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1028 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1030 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1032 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1033 = or(_T_1032, reset) @[Periphery.scala 312:78] + node _T_1035 = eq(_T_1033, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1035 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1036 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1038 = eq(_T_1036, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1038 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1040 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1041 = or(_T_1040, reset) @[Periphery.scala 312:78] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1043 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:312:78)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1044 = not(io.in[0].b.bits.mask) @[Periphery.scala 312:78] + node _T_1046 = eq(_T_1044, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1047 = or(_T_1046, reset) @[Periphery.scala 312:78] + node _T_1049 = eq(_T_1047, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1049 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1051 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:78] + when _T_1051 : @[Periphery.scala 312:78] + node _T_1053 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1055 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1056 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1058 = eq(_T_1056, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1058 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1059 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1061 = eq(_T_1059, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1061 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1063 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1064 = or(_T_1063, reset) @[Periphery.scala 312:78] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1066 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1067 = eq(io.in[0].b.bits.mask, _T_984) @[Periphery.scala 312:78] + node _T_1068 = or(_T_1067, reset) @[Periphery.scala 312:78] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1070 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1072 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1072 : @[Periphery.scala 312:78] + node _T_1074 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1076 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1077 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1079 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1080 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1082 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1084 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1085 = or(_T_1084, reset) @[Periphery.scala 312:78] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1087 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1088 = eq(io.in[0].b.bits.mask, _T_984) @[Periphery.scala 312:78] + node _T_1089 = or(_T_1088, reset) @[Periphery.scala 312:78] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1091 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1093 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:78] + when _T_1093 : @[Periphery.scala 312:78] + node _T_1095 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1097 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1098 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1100 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1101 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1103 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1105 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1106 = or(_T_1105, reset) @[Periphery.scala 312:78] + node _T_1108 = eq(_T_1106, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1108 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1109 = not(_T_984) @[Periphery.scala 312:78] + node _T_1110 = and(io.in[0].b.bits.mask, _T_1109) @[Periphery.scala 312:78] + node _T_1112 = eq(_T_1110, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1113 = or(_T_1112, reset) @[Periphery.scala 312:78] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1115 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1117 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:78] + when _T_1117 : @[Periphery.scala 312:78] + node _T_1119 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1121 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1122 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1124 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1125 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1127 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1129 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1130 = or(_T_1129, reset) @[Periphery.scala 312:78] + node _T_1132 = eq(_T_1130, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1132 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:312:78)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1133 = eq(io.in[0].b.bits.mask, _T_984) @[Periphery.scala 312:78] + node _T_1134 = or(_T_1133, reset) @[Periphery.scala 312:78] + node _T_1136 = eq(_T_1134, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1136 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1138 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 312:78] + when _T_1138 : @[Periphery.scala 312:78] + node _T_1140 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1142 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1143 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1145 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1146 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1148 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1150 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1151 = or(_T_1150, reset) @[Periphery.scala 312:78] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1153 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:312:78)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1154 = eq(io.in[0].b.bits.mask, _T_984) @[Periphery.scala 312:78] + node _T_1155 = or(_T_1154, reset) @[Periphery.scala 312:78] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1157 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1159 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:78] + when _T_1159 : @[Periphery.scala 312:78] + node _T_1161 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:78] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1163 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:312:78)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1164 = or(_T_937[0], reset) @[Periphery.scala 312:78] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1166 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1167 = or(_T_948, reset) @[Periphery.scala 312:78] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1169 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1170 = eq(io.in[0].b.bits.mask, _T_984) @[Periphery.scala 312:78] + node _T_1171 = or(_T_1170, reset) @[Periphery.scala 312:78] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1173 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:312:78)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + when io.in[0].c.valid : @[Periphery.scala 312:78] + node _T_1175 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1176 = or(_T_1175, reset) @[Periphery.scala 312:78] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1178 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:312:78)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1180 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1181 = not(_T_1180) @[Parameters.scala 37:9] + node _T_1183 = or(_T_1181, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1184 = not(_T_1183) @[Parameters.scala 37:7] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1188 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1190 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1193 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1193 is invalid @[Parameters.scala 228:27] + _T_1193[0] <= _T_1186 @[Parameters.scala 228:27] + _T_1193[1] <= _T_1188 @[Parameters.scala 228:27] + _T_1193[2] <= _T_1190 @[Parameters.scala 228:27] + node _T_1199 = or(_T_1193[0], _T_1193[1]) @[Parameters.scala 229:46] + node _T_1200 = or(_T_1199, _T_1193[2]) @[Parameters.scala 229:46] + node _T_1202 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1203 = dshl(_T_1202, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1204 = bits(_T_1203, 5, 0) @[package.scala 19:76] + node _T_1205 = not(_T_1204) @[package.scala 19:40] + node _T_1206 = and(io.in[0].c.bits.address, _T_1205) @[Edges.scala 17:16] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1210 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1211 = cvt(_T_1210) @[Parameters.scala 117:49] + node _T_1213 = and(_T_1211, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1214 = asSInt(_T_1213) @[Parameters.scala 117:52] + node _T_1216 = eq(_T_1214, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1219 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1219 is invalid @[Parameters.scala 110:36] + _T_1219[0] <= _T_1216 @[Parameters.scala 110:36] + node _T_1224 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:78] + when _T_1224 : @[Periphery.scala 312:78] + node _T_1225 = or(_T_1219[0], reset) @[Periphery.scala 312:78] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1227 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1228 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1230 = eq(_T_1228, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1230 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1232 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1233 = or(_T_1232, reset) @[Periphery.scala 312:78] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1235 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1236 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1238 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1240 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1241 = or(_T_1240, reset) @[Periphery.scala 312:78] + node _T_1243 = eq(_T_1241, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1243 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:312:78)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1245 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1246 = or(_T_1245, reset) @[Periphery.scala 312:78] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1248 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1250 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:78] + when _T_1250 : @[Periphery.scala 312:78] + node _T_1251 = or(_T_1219[0], reset) @[Periphery.scala 312:78] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1253 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1254 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1256 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1258 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1259 = or(_T_1258, reset) @[Periphery.scala 312:78] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1261 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1262 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1264 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1266 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1267 = or(_T_1266, reset) @[Periphery.scala 312:78] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1269 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:312:78)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1271 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1272 = or(_T_1271, reset) @[Periphery.scala 312:78] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1274 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1276 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:78] + when _T_1276 : @[Periphery.scala 312:78] + node _T_1279 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1281 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1282 = cvt(_T_1281) @[Parameters.scala 117:49] + node _T_1284 = and(_T_1282, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1285 = asSInt(_T_1284) @[Parameters.scala 117:52] + node _T_1287 = eq(_T_1285, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1288 = and(_T_1279, _T_1287) @[Parameters.scala 132:56] + node _T_1290 = or(UInt<1>("h00"), _T_1288) @[Parameters.scala 134:30] + node _T_1291 = or(_T_1290, reset) @[Periphery.scala 312:78] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1293 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1294 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1296 = eq(_T_1294, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1296 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1298 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1299 = or(_T_1298, reset) @[Periphery.scala 312:78] + node _T_1301 = eq(_T_1299, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1301 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1302 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1304 = eq(_T_1302, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1304 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1306 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1307 = or(_T_1306, reset) @[Periphery.scala 312:78] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1309 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:312:78)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1311 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1312 = or(_T_1311, reset) @[Periphery.scala 312:78] + node _T_1314 = eq(_T_1312, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1314 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1316 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 312:78] + when _T_1316 : @[Periphery.scala 312:78] + node _T_1319 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1321 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1322 = cvt(_T_1321) @[Parameters.scala 117:49] + node _T_1324 = and(_T_1322, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1325 = asSInt(_T_1324) @[Parameters.scala 117:52] + node _T_1327 = eq(_T_1325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1328 = and(_T_1319, _T_1327) @[Parameters.scala 132:56] + node _T_1330 = or(UInt<1>("h00"), _T_1328) @[Parameters.scala 134:30] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 312:78] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1333 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:312:78)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1334 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1336 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1338 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1339 = or(_T_1338, reset) @[Periphery.scala 312:78] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1341 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1342 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1344 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1346 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1347 = or(_T_1346, reset) @[Periphery.scala 312:78] + node _T_1349 = eq(_T_1347, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1349 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:312:78)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1351 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1352 = or(_T_1351, reset) @[Periphery.scala 312:78] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1354 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1356 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1356 : @[Periphery.scala 312:78] + node _T_1357 = or(_T_1219[0], reset) @[Periphery.scala 312:78] + node _T_1359 = eq(_T_1357, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1359 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1360 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1362 = eq(_T_1360, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1362 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1363 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1365 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1367 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1368 = or(_T_1367, reset) @[Periphery.scala 312:78] + node _T_1370 = eq(_T_1368, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1370 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1372 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:78] + when _T_1372 : @[Periphery.scala 312:78] + node _T_1373 = or(_T_1219[0], reset) @[Periphery.scala 312:78] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1375 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1376 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1378 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1379 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1381 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1383 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1384 = or(_T_1383, reset) @[Periphery.scala 312:78] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1386 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:78] + when _T_1388 : @[Periphery.scala 312:78] + node _T_1389 = or(_T_1219[0], reset) @[Periphery.scala 312:78] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1391 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:312:78)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1392 = or(_T_1200, reset) @[Periphery.scala 312:78] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1394 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1395 = or(_T_1208, reset) @[Periphery.scala 312:78] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1397 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1399 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1400 = or(_T_1399, reset) @[Periphery.scala 312:78] + node _T_1402 = eq(_T_1400, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1402 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1404 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1405 = or(_T_1404, reset) @[Periphery.scala 312:78] + node _T_1407 = eq(_T_1405, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1407 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + when io.in[0].d.valid : @[Periphery.scala 312:78] + node _T_1409 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1410 = or(_T_1409, reset) @[Periphery.scala 312:78] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1412 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:312:78)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1414 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1415 = not(_T_1414) @[Parameters.scala 37:9] + node _T_1417 = or(_T_1415, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1418 = not(_T_1417) @[Parameters.scala 37:7] + node _T_1420 = eq(_T_1418, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1422 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1424 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1427 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1427 is invalid @[Parameters.scala 228:27] + _T_1427[0] <= _T_1420 @[Parameters.scala 228:27] + _T_1427[1] <= _T_1422 @[Parameters.scala 228:27] + _T_1427[2] <= _T_1424 @[Parameters.scala 228:27] + node _T_1433 = or(_T_1427[0], _T_1427[1]) @[Parameters.scala 229:46] + node _T_1434 = or(_T_1433, _T_1427[2]) @[Parameters.scala 229:46] + node _T_1436 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1437 = dshl(_T_1436, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1438 = bits(_T_1437, 5, 0) @[package.scala 19:76] + node _T_1439 = not(_T_1438) @[package.scala 19:40] + node _T_1440 = and(io.in[0].d.bits.addr_lo, _T_1439) @[Edges.scala 17:16] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1444 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 312:78] + node _T_1446 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:78] + when _T_1446 : @[Periphery.scala 312:78] + node _T_1447 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1449 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1450 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1452 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1453 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1455 = eq(_T_1453, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1455 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1457 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1458 = or(_T_1457, reset) @[Periphery.scala 312:78] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1460 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1462 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1463 = or(_T_1462, reset) @[Periphery.scala 312:78] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1465 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1467 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1468 = or(_T_1467, reset) @[Periphery.scala 312:78] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1470 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1472 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:78] + when _T_1472 : @[Periphery.scala 312:78] + node _T_1473 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1475 = eq(_T_1473, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1475 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1476 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1478 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1479 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1481 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1483 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1484 = or(_T_1483, reset) @[Periphery.scala 312:78] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1486 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1488 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1489 = or(_T_1488, reset) @[Periphery.scala 312:78] + node _T_1491 = eq(_T_1489, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1491 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:312:78)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1493 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:78] + when _T_1493 : @[Periphery.scala 312:78] + node _T_1494 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1496 = eq(_T_1494, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1496 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1497 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1499 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1500 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1502 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1504 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:78] + node _T_1505 = or(_T_1504, reset) @[Periphery.scala 312:78] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1507 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:312:78)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1509 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1510 = or(_T_1509, reset) @[Periphery.scala 312:78] + node _T_1512 = eq(_T_1510, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1512 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:312:78)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1514 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1514 : @[Periphery.scala 312:78] + node _T_1515 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1517 = eq(_T_1515, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1517 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1518 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1520 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1521 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1523 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1525 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1526 = or(_T_1525, reset) @[Periphery.scala 312:78] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1528 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1530 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:78] + when _T_1530 : @[Periphery.scala 312:78] + node _T_1531 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1533 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1534 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1536 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1537 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1539 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1541 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1542 = or(_T_1541, reset) @[Periphery.scala 312:78] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1544 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1546 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:78] + when _T_1546 : @[Periphery.scala 312:78] + node _T_1547 = or(_T_1434, reset) @[Periphery.scala 312:78] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1549 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1550 = or(_T_1442, reset) @[Periphery.scala 312:78] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1552 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:312:78)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1553 = or(_T_1444, reset) @[Periphery.scala 312:78] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1555 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1557 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1558 = or(_T_1557, reset) @[Periphery.scala 312:78] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1560 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:312:78)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1562 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1563 = or(_T_1562, reset) @[Periphery.scala 312:78] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1565 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:312:78)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + when io.in[0].e.valid : @[Periphery.scala 312:78] + node _T_1567 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 312:78] + node _T_1568 = or(_T_1567, reset) @[Periphery.scala 312:78] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1570 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:312:78)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1571 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1573 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1574 = dshl(_T_1573, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1575 = bits(_T_1574, 5, 0) @[package.scala 19:76] + node _T_1576 = not(_T_1575) @[package.scala 19:40] + node _T_1577 = shr(_T_1576, 2) @[Edges.scala 198:59] + node _T_1578 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1583 = mux(UInt<1>("h00"), _T_1577, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1585 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1587 = sub(_T_1585, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1588 = asUInt(_T_1587) @[Edges.scala 208:28] + node _T_1589 = tail(_T_1588, 1) @[Edges.scala 208:28] + node _T_1591 = eq(_T_1585, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1593 = eq(_T_1585, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1595 = eq(_T_1583, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1596 = or(_T_1593, _T_1595) @[Edges.scala 210:37] + node _T_1597 = and(_T_1596, _T_1571) @[Edges.scala 211:22] + node _T_1598 = not(_T_1589) @[Edges.scala 212:27] + node _T_1599 = and(_T_1583, _T_1598) @[Edges.scala 212:25] + when _T_1571 : @[Edges.scala 213:17] + node _T_1600 = mux(_T_1591, _T_1583, _T_1589) @[Edges.scala 214:21] + _T_1585 <= _T_1600 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1602 : UInt, clock @[Periphery.scala 312:78] + reg _T_1604 : UInt, clock @[Periphery.scala 312:78] + reg _T_1606 : UInt, clock @[Periphery.scala 312:78] + reg _T_1608 : UInt, clock @[Periphery.scala 312:78] + reg _T_1610 : UInt, clock @[Periphery.scala 312:78] + node _T_1612 = eq(_T_1591, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1613 = and(io.in[0].a.valid, _T_1612) @[Periphery.scala 312:78] + when _T_1613 : @[Periphery.scala 312:78] + node _T_1614 = eq(io.in[0].a.bits.opcode, _T_1602) @[Periphery.scala 312:78] + node _T_1615 = or(_T_1614, reset) @[Periphery.scala 312:78] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1617 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1618 = eq(io.in[0].a.bits.param, _T_1604) @[Periphery.scala 312:78] + node _T_1619 = or(_T_1618, reset) @[Periphery.scala 312:78] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1621 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1622 = eq(io.in[0].a.bits.size, _T_1606) @[Periphery.scala 312:78] + node _T_1623 = or(_T_1622, reset) @[Periphery.scala 312:78] + node _T_1625 = eq(_T_1623, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1625 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1626 = eq(io.in[0].a.bits.source, _T_1608) @[Periphery.scala 312:78] + node _T_1627 = or(_T_1626, reset) @[Periphery.scala 312:78] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1629 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1630 = eq(io.in[0].a.bits.address, _T_1610) @[Periphery.scala 312:78] + node _T_1631 = or(_T_1630, reset) @[Periphery.scala 312:78] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1633 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1634 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1635 = and(_T_1634, _T_1591) @[Periphery.scala 312:78] + when _T_1635 : @[Periphery.scala 312:78] + _T_1602 <= io.in[0].a.bits.opcode @[Periphery.scala 312:78] + _T_1604 <= io.in[0].a.bits.param @[Periphery.scala 312:78] + _T_1606 <= io.in[0].a.bits.size @[Periphery.scala 312:78] + _T_1608 <= io.in[0].a.bits.source @[Periphery.scala 312:78] + _T_1610 <= io.in[0].a.bits.address @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1636 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1638 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1639 = dshl(_T_1638, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1640 = bits(_T_1639, 5, 0) @[package.scala 19:76] + node _T_1641 = not(_T_1640) @[package.scala 19:40] + node _T_1642 = shr(_T_1641, 2) @[Edges.scala 198:59] + node _T_1643 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1645 = eq(_T_1643, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1648 = mux(UInt<1>("h00"), _T_1642, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1650 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1652 = sub(_T_1650, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1653 = asUInt(_T_1652) @[Edges.scala 208:28] + node _T_1654 = tail(_T_1653, 1) @[Edges.scala 208:28] + node _T_1656 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1658 = eq(_T_1650, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1660 = eq(_T_1648, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1661 = or(_T_1658, _T_1660) @[Edges.scala 210:37] + node _T_1662 = and(_T_1661, _T_1636) @[Edges.scala 211:22] + node _T_1663 = not(_T_1654) @[Edges.scala 212:27] + node _T_1664 = and(_T_1648, _T_1663) @[Edges.scala 212:25] + when _T_1636 : @[Edges.scala 213:17] + node _T_1665 = mux(_T_1656, _T_1648, _T_1654) @[Edges.scala 214:21] + _T_1650 <= _T_1665 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1667 : UInt, clock @[Periphery.scala 312:78] + reg _T_1669 : UInt, clock @[Periphery.scala 312:78] + reg _T_1671 : UInt, clock @[Periphery.scala 312:78] + reg _T_1673 : UInt, clock @[Periphery.scala 312:78] + reg _T_1675 : UInt, clock @[Periphery.scala 312:78] + node _T_1677 = eq(_T_1656, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1678 = and(io.in[0].b.valid, _T_1677) @[Periphery.scala 312:78] + when _T_1678 : @[Periphery.scala 312:78] + node _T_1679 = eq(io.in[0].b.bits.opcode, _T_1667) @[Periphery.scala 312:78] + node _T_1680 = or(_T_1679, reset) @[Periphery.scala 312:78] + node _T_1682 = eq(_T_1680, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1682 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1683 = eq(io.in[0].b.bits.param, _T_1669) @[Periphery.scala 312:78] + node _T_1684 = or(_T_1683, reset) @[Periphery.scala 312:78] + node _T_1686 = eq(_T_1684, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1686 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1687 = eq(io.in[0].b.bits.size, _T_1671) @[Periphery.scala 312:78] + node _T_1688 = or(_T_1687, reset) @[Periphery.scala 312:78] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1690 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1691 = eq(io.in[0].b.bits.source, _T_1673) @[Periphery.scala 312:78] + node _T_1692 = or(_T_1691, reset) @[Periphery.scala 312:78] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1694 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1695 = eq(io.in[0].b.bits.address, _T_1675) @[Periphery.scala 312:78] + node _T_1696 = or(_T_1695, reset) @[Periphery.scala 312:78] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1698 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1699 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1700 = and(_T_1699, _T_1656) @[Periphery.scala 312:78] + when _T_1700 : @[Periphery.scala 312:78] + _T_1667 <= io.in[0].b.bits.opcode @[Periphery.scala 312:78] + _T_1669 <= io.in[0].b.bits.param @[Periphery.scala 312:78] + _T_1671 <= io.in[0].b.bits.size @[Periphery.scala 312:78] + _T_1673 <= io.in[0].b.bits.source @[Periphery.scala 312:78] + _T_1675 <= io.in[0].b.bits.address @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1701 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1703 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1704 = dshl(_T_1703, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1705 = bits(_T_1704, 5, 0) @[package.scala 19:76] + node _T_1706 = not(_T_1705) @[package.scala 19:40] + node _T_1707 = shr(_T_1706, 2) @[Edges.scala 198:59] + node _T_1708 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1710 = mux(_T_1708, _T_1707, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1712 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1714 = sub(_T_1712, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1715 = asUInt(_T_1714) @[Edges.scala 208:28] + node _T_1716 = tail(_T_1715, 1) @[Edges.scala 208:28] + node _T_1718 = eq(_T_1712, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1720 = eq(_T_1712, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1722 = eq(_T_1710, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1723 = or(_T_1720, _T_1722) @[Edges.scala 210:37] + node _T_1724 = and(_T_1723, _T_1701) @[Edges.scala 211:22] + node _T_1725 = not(_T_1716) @[Edges.scala 212:27] + node _T_1726 = and(_T_1710, _T_1725) @[Edges.scala 212:25] + when _T_1701 : @[Edges.scala 213:17] + node _T_1727 = mux(_T_1718, _T_1710, _T_1716) @[Edges.scala 214:21] + _T_1712 <= _T_1727 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1729 : UInt, clock @[Periphery.scala 312:78] + reg _T_1731 : UInt, clock @[Periphery.scala 312:78] + reg _T_1733 : UInt, clock @[Periphery.scala 312:78] + reg _T_1735 : UInt, clock @[Periphery.scala 312:78] + reg _T_1737 : UInt, clock @[Periphery.scala 312:78] + node _T_1739 = eq(_T_1718, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1740 = and(io.in[0].c.valid, _T_1739) @[Periphery.scala 312:78] + when _T_1740 : @[Periphery.scala 312:78] + node _T_1741 = eq(io.in[0].c.bits.opcode, _T_1729) @[Periphery.scala 312:78] + node _T_1742 = or(_T_1741, reset) @[Periphery.scala 312:78] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1744 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1745 = eq(io.in[0].c.bits.param, _T_1731) @[Periphery.scala 312:78] + node _T_1746 = or(_T_1745, reset) @[Periphery.scala 312:78] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1748 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1749 = eq(io.in[0].c.bits.size, _T_1733) @[Periphery.scala 312:78] + node _T_1750 = or(_T_1749, reset) @[Periphery.scala 312:78] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1752 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1753 = eq(io.in[0].c.bits.source, _T_1735) @[Periphery.scala 312:78] + node _T_1754 = or(_T_1753, reset) @[Periphery.scala 312:78] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1756 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1757 = eq(io.in[0].c.bits.address, _T_1737) @[Periphery.scala 312:78] + node _T_1758 = or(_T_1757, reset) @[Periphery.scala 312:78] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1760 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1761 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1762 = and(_T_1761, _T_1718) @[Periphery.scala 312:78] + when _T_1762 : @[Periphery.scala 312:78] + _T_1729 <= io.in[0].c.bits.opcode @[Periphery.scala 312:78] + _T_1731 <= io.in[0].c.bits.param @[Periphery.scala 312:78] + _T_1733 <= io.in[0].c.bits.size @[Periphery.scala 312:78] + _T_1735 <= io.in[0].c.bits.source @[Periphery.scala 312:78] + _T_1737 <= io.in[0].c.bits.address @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1763 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1765 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1766 = dshl(_T_1765, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1767 = bits(_T_1766, 5, 0) @[package.scala 19:76] + node _T_1768 = not(_T_1767) @[package.scala 19:40] + node _T_1769 = shr(_T_1768, 2) @[Edges.scala 198:59] + node _T_1770 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1773 = mux(UInt<1>("h01"), _T_1769, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1775 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1777 = sub(_T_1775, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1778 = asUInt(_T_1777) @[Edges.scala 208:28] + node _T_1779 = tail(_T_1778, 1) @[Edges.scala 208:28] + node _T_1781 = eq(_T_1775, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1783 = eq(_T_1775, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1785 = eq(_T_1773, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1786 = or(_T_1783, _T_1785) @[Edges.scala 210:37] + node _T_1787 = and(_T_1786, _T_1763) @[Edges.scala 211:22] + node _T_1788 = not(_T_1779) @[Edges.scala 212:27] + node _T_1789 = and(_T_1773, _T_1788) @[Edges.scala 212:25] + when _T_1763 : @[Edges.scala 213:17] + node _T_1790 = mux(_T_1781, _T_1773, _T_1779) @[Edges.scala 214:21] + _T_1775 <= _T_1790 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1792 : UInt, clock @[Periphery.scala 312:78] + reg _T_1794 : UInt, clock @[Periphery.scala 312:78] + reg _T_1796 : UInt, clock @[Periphery.scala 312:78] + reg _T_1798 : UInt, clock @[Periphery.scala 312:78] + reg _T_1800 : UInt, clock @[Periphery.scala 312:78] + reg _T_1802 : UInt, clock @[Periphery.scala 312:78] + node _T_1804 = eq(_T_1781, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1805 = and(io.in[0].d.valid, _T_1804) @[Periphery.scala 312:78] + when _T_1805 : @[Periphery.scala 312:78] + node _T_1806 = eq(io.in[0].d.bits.opcode, _T_1792) @[Periphery.scala 312:78] + node _T_1807 = or(_T_1806, reset) @[Periphery.scala 312:78] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1809 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1810 = eq(io.in[0].d.bits.param, _T_1794) @[Periphery.scala 312:78] + node _T_1811 = or(_T_1810, reset) @[Periphery.scala 312:78] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1813 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1814 = eq(io.in[0].d.bits.size, _T_1796) @[Periphery.scala 312:78] + node _T_1815 = or(_T_1814, reset) @[Periphery.scala 312:78] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1817 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1818 = eq(io.in[0].d.bits.source, _T_1798) @[Periphery.scala 312:78] + node _T_1819 = or(_T_1818, reset) @[Periphery.scala 312:78] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1821 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1822 = eq(io.in[0].d.bits.sink, _T_1800) @[Periphery.scala 312:78] + node _T_1823 = or(_T_1822, reset) @[Periphery.scala 312:78] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1825 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1826 = eq(io.in[0].d.bits.addr_lo, _T_1802) @[Periphery.scala 312:78] + node _T_1827 = or(_T_1826, reset) @[Periphery.scala 312:78] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1829 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:312:78)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1830 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1831 = and(_T_1830, _T_1781) @[Periphery.scala 312:78] + when _T_1831 : @[Periphery.scala 312:78] + _T_1792 <= io.in[0].d.bits.opcode @[Periphery.scala 312:78] + _T_1794 <= io.in[0].d.bits.param @[Periphery.scala 312:78] + _T_1796 <= io.in[0].d.bits.size @[Periphery.scala 312:78] + _T_1798 <= io.in[0].d.bits.source @[Periphery.scala 312:78] + _T_1800 <= io.in[0].d.bits.sink @[Periphery.scala 312:78] + _T_1802 <= io.in[0].d.bits.addr_lo @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + reg _T_1833 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1834 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 2) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1843 = eq(_T_1841, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1846 = mux(UInt<1>("h00"), _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1834) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1864 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1866 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1867 = dshl(_T_1866, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1868 = bits(_T_1867, 5, 0) @[package.scala 19:76] + node _T_1869 = not(_T_1868) @[package.scala 19:40] + node _T_1870 = shr(_T_1869, 2) @[Edges.scala 198:59] + node _T_1871 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1874 = mux(UInt<1>("h01"), _T_1870, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1876 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1878 = sub(_T_1876, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1879 = asUInt(_T_1878) @[Edges.scala 208:28] + node _T_1880 = tail(_T_1879, 1) @[Edges.scala 208:28] + node _T_1882 = eq(_T_1876, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1884 = eq(_T_1876, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1886 = eq(_T_1874, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1887 = or(_T_1884, _T_1886) @[Edges.scala 210:37] + node _T_1888 = and(_T_1887, _T_1864) @[Edges.scala 211:22] + node _T_1889 = not(_T_1880) @[Edges.scala 212:27] + node _T_1890 = and(_T_1874, _T_1889) @[Edges.scala 212:25] + when _T_1864 : @[Edges.scala 213:17] + node _T_1891 = mux(_T_1882, _T_1874, _T_1880) @[Edges.scala 214:21] + _T_1876 <= _T_1891 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1893 : UInt<6> + _T_1893 is invalid + _T_1893 <= UInt<6>("h00") + node _T_1894 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1894 : @[Periphery.scala 312:78] + when _T_1859 : @[Periphery.scala 312:78] + node _T_1896 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1893 <= _T_1896 @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1897 = dshr(_T_1833, io.in[0].a.bits.source) @[Periphery.scala 312:78] + node _T_1898 = bits(_T_1897, 0, 0) @[Periphery.scala 312:78] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[Periphery.scala 312:78] + node _T_1901 = or(_T_1900, reset) @[Periphery.scala 312:78] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1903 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:312:78)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + wire _T_1905 : UInt<6> + _T_1905 is invalid + _T_1905 <= UInt<6>("h00") + node _T_1906 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1908 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:78] + node _T_1909 = and(_T_1906, _T_1908) @[Periphery.scala 312:78] + when _T_1909 : @[Periphery.scala 312:78] + when _T_1887 : @[Periphery.scala 312:78] + node _T_1911 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1905 <= _T_1911 @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1912 = or(_T_1893, _T_1833) @[Periphery.scala 312:78] + node _T_1913 = dshr(_T_1912, io.in[0].d.bits.source) @[Periphery.scala 312:78] + node _T_1914 = bits(_T_1913, 0, 0) @[Periphery.scala 312:78] + node _T_1915 = or(_T_1914, reset) @[Periphery.scala 312:78] + node _T_1917 = eq(_T_1915, UInt<1>("h00")) @[Periphery.scala 312:78] + when _T_1917 : @[Periphery.scala 312:78] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:312:78)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 312:78] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + skip @[Periphery.scala 312:78] + node _T_1918 = or(_T_1833, _T_1893) @[Periphery.scala 312:78] + node _T_1919 = not(_T_1905) @[Periphery.scala 312:78] + node _T_1920 = and(_T_1918, _T_1919) @[Periphery.scala 312:78] + _T_1833 <= _T_1920 @[Periphery.scala 312:78] + + module TLMonitor_11 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 312:16] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 312:16] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_608 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:312:16)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<6>("h03f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = xor(UInt<7>("h050"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_619 = not(_T_618) @[Parameters.scala 37:9] + node _T_621 = or(_T_619, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_622 = not(_T_621) @[Parameters.scala 37:7] + node _T_624 = eq(_T_622, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_626 = xor(UInt<7>("h040"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_627 = not(_T_626) @[Parameters.scala 37:9] + node _T_629 = or(_T_627, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_630 = not(_T_629) @[Parameters.scala 37:7] + node _T_632 = eq(_T_630, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_635 : UInt<1>[3] @[Parameters.scala 228:27] + _T_635 is invalid @[Parameters.scala 228:27] + _T_635[0] <= _T_616 @[Parameters.scala 228:27] + _T_635[1] <= _T_624 @[Parameters.scala 228:27] + _T_635[2] <= _T_632 @[Parameters.scala 228:27] + node _T_641 = or(_T_635[0], _T_635[1]) @[Parameters.scala 229:46] + node _T_642 = or(_T_641, _T_635[2]) @[Parameters.scala 229:46] + node _T_644 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_645 = dshl(_T_644, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_646 = bits(_T_645, 5, 0) @[package.scala 19:76] + node _T_647 = not(_T_646) @[package.scala 19:40] + node _T_648 = and(io.in[0].a.bits.address, _T_647) @[Edges.scala 17:16] + node _T_650 = eq(_T_648, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_652 = bits(io.in[0].a.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_653 = dshl(UInt<1>("h01"), _T_652) @[OneHot.scala 49:12] + node _T_654 = bits(_T_653, 1, 0) @[OneHot.scala 49:37] + node _T_656 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_658 = bits(_T_654, 1, 1) @[package.scala 44:26] + node _T_659 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_661 = eq(_T_659, UInt<1>("h00")) @[package.scala 46:20] + node _T_662 = and(UInt<1>("h01"), _T_661) @[package.scala 49:27] + node _T_663 = and(_T_658, _T_662) @[package.scala 50:38] + node _T_664 = or(_T_656, _T_663) @[package.scala 50:29] + node _T_665 = and(UInt<1>("h01"), _T_659) @[package.scala 49:27] + node _T_666 = and(_T_658, _T_665) @[package.scala 50:38] + node _T_667 = or(_T_656, _T_666) @[package.scala 50:29] + node _T_668 = bits(_T_654, 0, 0) @[package.scala 44:26] + node _T_669 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_671 = eq(_T_669, UInt<1>("h00")) @[package.scala 46:20] + node _T_672 = and(_T_662, _T_671) @[package.scala 49:27] + node _T_673 = and(_T_668, _T_672) @[package.scala 50:38] + node _T_674 = or(_T_664, _T_673) @[package.scala 50:29] + node _T_675 = and(_T_662, _T_669) @[package.scala 49:27] + node _T_676 = and(_T_668, _T_675) @[package.scala 50:38] + node _T_677 = or(_T_664, _T_676) @[package.scala 50:29] + node _T_678 = and(_T_665, _T_671) @[package.scala 49:27] + node _T_679 = and(_T_668, _T_678) @[package.scala 50:38] + node _T_680 = or(_T_667, _T_679) @[package.scala 50:29] + node _T_681 = and(_T_665, _T_669) @[package.scala 49:27] + node _T_682 = and(_T_668, _T_681) @[package.scala 50:38] + node _T_683 = or(_T_667, _T_682) @[package.scala 50:29] + node _T_684 = cat(_T_677, _T_674) @[Cat.scala 30:58] + node _T_685 = cat(_T_683, _T_680) @[Cat.scala 30:58] + node _T_686 = cat(_T_685, _T_684) @[Cat.scala 30:58] + node _T_688 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:16] + when _T_688 : @[Periphery.scala 312:16] + node _T_691 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_693 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_694 = cvt(_T_693) @[Parameters.scala 117:49] + node _T_696 = and(_T_694, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_697 = asSInt(_T_696) @[Parameters.scala 117:52] + node _T_699 = eq(_T_697, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_700 = and(_T_691, _T_699) @[Parameters.scala 132:56] + node _T_702 = or(UInt<1>("h00"), _T_700) @[Parameters.scala 134:30] + node _T_703 = or(_T_702, reset) @[Periphery.scala 312:16] + node _T_705 = eq(_T_703, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_705 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_706 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_708 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_710 = geq(io.in[0].a.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_711 = or(_T_710, reset) @[Periphery.scala 312:16] + node _T_713 = eq(_T_711, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_713 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_714 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_716 = eq(_T_714, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_716 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_718 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_719 = or(_T_718, reset) @[Periphery.scala 312:16] + node _T_721 = eq(_T_719, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_721 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:312:16)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_722 = not(io.in[0].a.bits.mask) @[Periphery.scala 312:16] + node _T_724 = eq(_T_722, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_725 = or(_T_724, reset) @[Periphery.scala 312:16] + node _T_727 = eq(_T_725, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_727 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_729 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:16] + when _T_729 : @[Periphery.scala 312:16] + node _T_732 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_734 = leq(io.in[0].a.bits.size, UInt<2>("h02")) @[Parameters.scala 63:42] + node _T_735 = and(_T_732, _T_734) @[Parameters.scala 63:37] + node _T_736 = or(UInt<1>("h00"), _T_735) @[Parameters.scala 132:31] + node _T_738 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_739 = cvt(_T_738) @[Parameters.scala 117:49] + node _T_741 = and(_T_739, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_742 = asSInt(_T_741) @[Parameters.scala 117:52] + node _T_744 = eq(_T_742, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_745 = and(_T_736, _T_744) @[Parameters.scala 132:56] + node _T_747 = or(UInt<1>("h00"), _T_745) @[Parameters.scala 134:30] + node _T_748 = or(_T_747, reset) @[Periphery.scala 312:16] + node _T_750 = eq(_T_748, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_750 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_751 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_753 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_754 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_756 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_758 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_759 = or(_T_758, reset) @[Periphery.scala 312:16] + node _T_761 = eq(_T_759, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_761 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_762 = eq(io.in[0].a.bits.mask, _T_686) @[Periphery.scala 312:16] + node _T_763 = or(_T_762, reset) @[Periphery.scala 312:16] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_765 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_767 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_767 : @[Periphery.scala 312:16] + node _T_770 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_772 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_773 = cvt(_T_772) @[Parameters.scala 117:49] + node _T_775 = and(_T_773, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_776 = asSInt(_T_775) @[Parameters.scala 117:52] + node _T_778 = eq(_T_776, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_779 = and(_T_770, _T_778) @[Parameters.scala 132:56] + node _T_781 = or(UInt<1>("h00"), _T_779) @[Parameters.scala 134:30] + node _T_782 = or(_T_781, reset) @[Periphery.scala 312:16] + node _T_784 = eq(_T_782, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_784 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_785 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_787 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_788 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_790 = eq(_T_788, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_790 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_792 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_793 = or(_T_792, reset) @[Periphery.scala 312:16] + node _T_795 = eq(_T_793, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_795 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_796 = eq(io.in[0].a.bits.mask, _T_686) @[Periphery.scala 312:16] + node _T_797 = or(_T_796, reset) @[Periphery.scala 312:16] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_799 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_801 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:16] + when _T_801 : @[Periphery.scala 312:16] + node _T_804 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_806 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_807 = cvt(_T_806) @[Parameters.scala 117:49] + node _T_809 = and(_T_807, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_810 = asSInt(_T_809) @[Parameters.scala 117:52] + node _T_812 = eq(_T_810, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_813 = and(_T_804, _T_812) @[Parameters.scala 132:56] + node _T_815 = or(UInt<1>("h00"), _T_813) @[Parameters.scala 134:30] + node _T_816 = or(_T_815, reset) @[Periphery.scala 312:16] + node _T_818 = eq(_T_816, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_818 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_819 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_821 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_822 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_824 = eq(_T_822, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_824 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_826 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_827 = or(_T_826, reset) @[Periphery.scala 312:16] + node _T_829 = eq(_T_827, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_829 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_830 = not(_T_686) @[Periphery.scala 312:16] + node _T_831 = and(io.in[0].a.bits.mask, _T_830) @[Periphery.scala 312:16] + node _T_833 = eq(_T_831, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_834 = or(_T_833, reset) @[Periphery.scala 312:16] + node _T_836 = eq(_T_834, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_836 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_838 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:16] + when _T_838 : @[Periphery.scala 312:16] + node _T_841 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_843 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_844 = cvt(_T_843) @[Parameters.scala 117:49] + node _T_846 = and(_T_844, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_847 = asSInt(_T_846) @[Parameters.scala 117:52] + node _T_849 = eq(_T_847, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_850 = and(_T_841, _T_849) @[Parameters.scala 132:56] + node _T_852 = or(UInt<1>("h00"), _T_850) @[Parameters.scala 134:30] + node _T_853 = or(_T_852, reset) @[Periphery.scala 312:16] + node _T_855 = eq(_T_853, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_855 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_856 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_858 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_859 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_861 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_863 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_864 = or(_T_863, reset) @[Periphery.scala 312:16] + node _T_866 = eq(_T_864, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_866 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:312:16)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_867 = eq(io.in[0].a.bits.mask, _T_686) @[Periphery.scala 312:16] + node _T_868 = or(_T_867, reset) @[Periphery.scala 312:16] + node _T_870 = eq(_T_868, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_870 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_872 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 312:16] + when _T_872 : @[Periphery.scala 312:16] + node _T_875 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_877 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_878 = cvt(_T_877) @[Parameters.scala 117:49] + node _T_880 = and(_T_878, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_881 = asSInt(_T_880) @[Parameters.scala 117:52] + node _T_883 = eq(_T_881, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_884 = and(_T_875, _T_883) @[Parameters.scala 132:56] + node _T_886 = or(UInt<1>("h00"), _T_884) @[Parameters.scala 134:30] + node _T_887 = or(_T_886, reset) @[Periphery.scala 312:16] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_889 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_890 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_892 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_893 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_895 = eq(_T_893, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_895 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_897 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_898 = or(_T_897, reset) @[Periphery.scala 312:16] + node _T_900 = eq(_T_898, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_900 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:312:16)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_901 = eq(io.in[0].a.bits.mask, _T_686) @[Periphery.scala 312:16] + node _T_902 = or(_T_901, reset) @[Periphery.scala 312:16] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_904 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_906 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:16] + when _T_906 : @[Periphery.scala 312:16] + node _T_909 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_911 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_912 = cvt(_T_911) @[Parameters.scala 117:49] + node _T_914 = and(_T_912, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_915 = asSInt(_T_914) @[Parameters.scala 117:52] + node _T_917 = eq(_T_915, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_918 = and(_T_909, _T_917) @[Parameters.scala 132:56] + node _T_920 = or(UInt<1>("h00"), _T_918) @[Parameters.scala 134:30] + node _T_921 = or(_T_920, reset) @[Periphery.scala 312:16] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_923 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_924 = or(_T_642, reset) @[Periphery.scala 312:16] + node _T_926 = eq(_T_924, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_926 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_927 = or(_T_650, reset) @[Periphery.scala 312:16] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_929 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_930 = eq(io.in[0].a.bits.mask, _T_686) @[Periphery.scala 312:16] + node _T_931 = or(_T_930, reset) @[Periphery.scala 312:16] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_933 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + when io.in[0].b.valid : @[Periphery.scala 312:16] + node _T_935 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_936 = or(_T_935, reset) @[Periphery.scala 312:16] + node _T_938 = eq(_T_936, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_938 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:312:16)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_940 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_941 = cvt(_T_940) @[Parameters.scala 117:49] + node _T_943 = and(_T_941, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_944 = asSInt(_T_943) @[Parameters.scala 117:52] + node _T_946 = eq(_T_944, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_949 : UInt<1>[1] @[Parameters.scala 110:36] + _T_949 is invalid @[Parameters.scala 110:36] + _T_949[0] <= _T_946 @[Parameters.scala 110:36] + node _T_954 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_955 = dshl(_T_954, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_956 = bits(_T_955, 5, 0) @[package.scala 19:76] + node _T_957 = not(_T_956) @[package.scala 19:40] + node _T_958 = and(io.in[0].b.bits.address, _T_957) @[Edges.scala 17:16] + node _T_960 = eq(_T_958, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_962 = bits(io.in[0].b.bits.size, 0, 0) @[OneHot.scala 49:17] + node _T_963 = dshl(UInt<1>("h01"), _T_962) @[OneHot.scala 49:12] + node _T_964 = bits(_T_963, 1, 0) @[OneHot.scala 49:37] + node _T_966 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[package.scala 41:21] + node _T_968 = bits(_T_964, 1, 1) @[package.scala 44:26] + node _T_969 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_971 = eq(_T_969, UInt<1>("h00")) @[package.scala 46:20] + node _T_972 = and(UInt<1>("h01"), _T_971) @[package.scala 49:27] + node _T_973 = and(_T_968, _T_972) @[package.scala 50:38] + node _T_974 = or(_T_966, _T_973) @[package.scala 50:29] + node _T_975 = and(UInt<1>("h01"), _T_969) @[package.scala 49:27] + node _T_976 = and(_T_968, _T_975) @[package.scala 50:38] + node _T_977 = or(_T_966, _T_976) @[package.scala 50:29] + node _T_978 = bits(_T_964, 0, 0) @[package.scala 44:26] + node _T_979 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_981 = eq(_T_979, UInt<1>("h00")) @[package.scala 46:20] + node _T_982 = and(_T_972, _T_981) @[package.scala 49:27] + node _T_983 = and(_T_978, _T_982) @[package.scala 50:38] + node _T_984 = or(_T_974, _T_983) @[package.scala 50:29] + node _T_985 = and(_T_972, _T_979) @[package.scala 49:27] + node _T_986 = and(_T_978, _T_985) @[package.scala 50:38] + node _T_987 = or(_T_974, _T_986) @[package.scala 50:29] + node _T_988 = and(_T_975, _T_981) @[package.scala 49:27] + node _T_989 = and(_T_978, _T_988) @[package.scala 50:38] + node _T_990 = or(_T_977, _T_989) @[package.scala 50:29] + node _T_991 = and(_T_975, _T_979) @[package.scala 49:27] + node _T_992 = and(_T_978, _T_991) @[package.scala 50:38] + node _T_993 = or(_T_977, _T_992) @[package.scala 50:29] + node _T_994 = cat(_T_987, _T_984) @[Cat.scala 30:58] + node _T_995 = cat(_T_993, _T_990) @[Cat.scala 30:58] + node _T_996 = cat(_T_995, _T_994) @[Cat.scala 30:58] + node _T_998 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:16] + when _T_998 : @[Periphery.scala 312:16] + node _T_1000 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1001 = not(_T_1000) @[Parameters.scala 37:9] + node _T_1003 = or(_T_1001, UInt<6>("h03f")) @[Parameters.scala 37:28] + node _T_1004 = not(_T_1003) @[Parameters.scala 37:7] + node _T_1006 = eq(_T_1004, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1008 = xor(UInt<7>("h050"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1009 = not(_T_1008) @[Parameters.scala 37:9] + node _T_1011 = or(_T_1009, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1012 = not(_T_1011) @[Parameters.scala 37:7] + node _T_1014 = eq(_T_1012, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1016 = xor(UInt<7>("h040"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1017 = not(_T_1016) @[Parameters.scala 37:9] + node _T_1019 = or(_T_1017, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1020 = not(_T_1019) @[Parameters.scala 37:7] + node _T_1022 = eq(_T_1020, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1025 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1025 is invalid @[Parameters.scala 228:27] + _T_1025[0] <= _T_1006 @[Parameters.scala 228:27] + _T_1025[1] <= _T_1014 @[Parameters.scala 228:27] + _T_1025[2] <= _T_1022 @[Parameters.scala 228:27] + node _T_1033 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1035 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1036 = and(_T_1033, _T_1035) @[Parameters.scala 63:37] + node _T_1039 = mux(_T_1025[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1041 = mux(_T_1025[1], _T_1036, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1043 = mux(_T_1025[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1045 = or(_T_1039, _T_1041) @[Mux.scala 19:72] + node _T_1046 = or(_T_1045, _T_1043) @[Mux.scala 19:72] + wire _T_1048 : UInt<1> @[Mux.scala 19:72] + _T_1048 is invalid @[Mux.scala 19:72] + _T_1048 <= _T_1046 @[Mux.scala 19:72] + node _T_1049 = or(_T_1048, reset) @[Periphery.scala 312:16] + node _T_1051 = eq(_T_1049, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1051 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1052 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1054 = eq(_T_1052, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1054 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1056 = geq(io.in[0].b.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1057 = or(_T_1056, reset) @[Periphery.scala 312:16] + node _T_1059 = eq(_T_1057, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1059 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1060 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1062 = eq(_T_1060, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1062 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1064 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1065 = or(_T_1064, reset) @[Periphery.scala 312:16] + node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1067 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:312:16)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1068 = not(io.in[0].b.bits.mask) @[Periphery.scala 312:16] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1071 = or(_T_1070, reset) @[Periphery.scala 312:16] + node _T_1073 = eq(_T_1071, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1073 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1075 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:16] + when _T_1075 : @[Periphery.scala 312:16] + node _T_1077 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1079 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1080 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1082 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1083 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1085 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1087 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1088 = or(_T_1087, reset) @[Periphery.scala 312:16] + node _T_1090 = eq(_T_1088, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1090 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1091 = eq(io.in[0].b.bits.mask, _T_996) @[Periphery.scala 312:16] + node _T_1092 = or(_T_1091, reset) @[Periphery.scala 312:16] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1094 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1096 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1096 : @[Periphery.scala 312:16] + node _T_1098 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1100 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1101 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1103 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1104 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1106 = eq(_T_1104, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1106 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1108 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1109 = or(_T_1108, reset) @[Periphery.scala 312:16] + node _T_1111 = eq(_T_1109, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1111 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1112 = eq(io.in[0].b.bits.mask, _T_996) @[Periphery.scala 312:16] + node _T_1113 = or(_T_1112, reset) @[Periphery.scala 312:16] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1115 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1117 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:16] + when _T_1117 : @[Periphery.scala 312:16] + node _T_1119 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1121 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1122 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1124 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1125 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1127 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1129 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1130 = or(_T_1129, reset) @[Periphery.scala 312:16] + node _T_1132 = eq(_T_1130, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1132 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1133 = not(_T_996) @[Periphery.scala 312:16] + node _T_1134 = and(io.in[0].b.bits.mask, _T_1133) @[Periphery.scala 312:16] + node _T_1136 = eq(_T_1134, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1137 = or(_T_1136, reset) @[Periphery.scala 312:16] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1139 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1141 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:16] + when _T_1141 : @[Periphery.scala 312:16] + node _T_1143 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1145 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1146 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1148 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1149 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1151 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1153 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1154 = or(_T_1153, reset) @[Periphery.scala 312:16] + node _T_1156 = eq(_T_1154, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1156 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:312:16)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1157 = eq(io.in[0].b.bits.mask, _T_996) @[Periphery.scala 312:16] + node _T_1158 = or(_T_1157, reset) @[Periphery.scala 312:16] + node _T_1160 = eq(_T_1158, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1160 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1162 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 312:16] + when _T_1162 : @[Periphery.scala 312:16] + node _T_1164 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1166 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1167 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1169 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1170 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1172 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1174 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1175 = or(_T_1174, reset) @[Periphery.scala 312:16] + node _T_1177 = eq(_T_1175, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1177 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:312:16)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1178 = eq(io.in[0].b.bits.mask, _T_996) @[Periphery.scala 312:16] + node _T_1179 = or(_T_1178, reset) @[Periphery.scala 312:16] + node _T_1181 = eq(_T_1179, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1181 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1183 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:16] + when _T_1183 : @[Periphery.scala 312:16] + node _T_1185 = or(UInt<1>("h00"), reset) @[Periphery.scala 312:16] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1187 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:312:16)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1188 = or(_T_949[0], reset) @[Periphery.scala 312:16] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1190 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1191 = or(_T_960, reset) @[Periphery.scala 312:16] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1193 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1194 = eq(io.in[0].b.bits.mask, _T_996) @[Periphery.scala 312:16] + node _T_1195 = or(_T_1194, reset) @[Periphery.scala 312:16] + node _T_1197 = eq(_T_1195, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1197 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:312:16)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + when io.in[0].c.valid : @[Periphery.scala 312:16] + node _T_1199 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1200 = or(_T_1199, reset) @[Periphery.scala 312:16] + node _T_1202 = eq(_T_1200, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1202 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:312:16)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1204 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1205 = not(_T_1204) @[Parameters.scala 37:9] + node _T_1207 = or(_T_1205, UInt<6>("h03f")) @[Parameters.scala 37:28] + node _T_1208 = not(_T_1207) @[Parameters.scala 37:7] + node _T_1210 = eq(_T_1208, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1212 = xor(UInt<7>("h050"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1213 = not(_T_1212) @[Parameters.scala 37:9] + node _T_1215 = or(_T_1213, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1216 = not(_T_1215) @[Parameters.scala 37:7] + node _T_1218 = eq(_T_1216, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1220 = xor(UInt<7>("h040"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1221 = not(_T_1220) @[Parameters.scala 37:9] + node _T_1223 = or(_T_1221, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1224 = not(_T_1223) @[Parameters.scala 37:7] + node _T_1226 = eq(_T_1224, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1229 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1229 is invalid @[Parameters.scala 228:27] + _T_1229[0] <= _T_1210 @[Parameters.scala 228:27] + _T_1229[1] <= _T_1218 @[Parameters.scala 228:27] + _T_1229[2] <= _T_1226 @[Parameters.scala 228:27] + node _T_1235 = or(_T_1229[0], _T_1229[1]) @[Parameters.scala 229:46] + node _T_1236 = or(_T_1235, _T_1229[2]) @[Parameters.scala 229:46] + node _T_1238 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1239 = dshl(_T_1238, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1240 = bits(_T_1239, 5, 0) @[package.scala 19:76] + node _T_1241 = not(_T_1240) @[package.scala 19:40] + node _T_1242 = and(io.in[0].c.bits.address, _T_1241) @[Edges.scala 17:16] + node _T_1244 = eq(_T_1242, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1246 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1247 = cvt(_T_1246) @[Parameters.scala 117:49] + node _T_1249 = and(_T_1247, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1250 = asSInt(_T_1249) @[Parameters.scala 117:52] + node _T_1252 = eq(_T_1250, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1255 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1255 is invalid @[Parameters.scala 110:36] + _T_1255[0] <= _T_1252 @[Parameters.scala 110:36] + node _T_1260 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:16] + when _T_1260 : @[Periphery.scala 312:16] + node _T_1261 = or(_T_1255[0], reset) @[Periphery.scala 312:16] + node _T_1263 = eq(_T_1261, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1263 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1264 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1266 = eq(_T_1264, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1266 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1268 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1269 = or(_T_1268, reset) @[Periphery.scala 312:16] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1271 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1272 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1274 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1276 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1277 = or(_T_1276, reset) @[Periphery.scala 312:16] + node _T_1279 = eq(_T_1277, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1279 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:312:16)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1281 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1282 = or(_T_1281, reset) @[Periphery.scala 312:16] + node _T_1284 = eq(_T_1282, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1284 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1286 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:16] + when _T_1286 : @[Periphery.scala 312:16] + node _T_1287 = or(_T_1255[0], reset) @[Periphery.scala 312:16] + node _T_1289 = eq(_T_1287, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1289 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1290 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1292 = eq(_T_1290, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1292 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1294 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1295 = or(_T_1294, reset) @[Periphery.scala 312:16] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1297 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1298 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1300 = eq(_T_1298, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1300 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1302 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1303 = or(_T_1302, reset) @[Periphery.scala 312:16] + node _T_1305 = eq(_T_1303, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1305 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:312:16)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1307 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1308 = or(_T_1307, reset) @[Periphery.scala 312:16] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1310 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1312 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:16] + when _T_1312 : @[Periphery.scala 312:16] + node _T_1315 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1317 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1318 = cvt(_T_1317) @[Parameters.scala 117:49] + node _T_1320 = and(_T_1318, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1321 = asSInt(_T_1320) @[Parameters.scala 117:52] + node _T_1323 = eq(_T_1321, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1324 = and(_T_1315, _T_1323) @[Parameters.scala 132:56] + node _T_1326 = or(UInt<1>("h00"), _T_1324) @[Parameters.scala 134:30] + node _T_1327 = or(_T_1326, reset) @[Periphery.scala 312:16] + node _T_1329 = eq(_T_1327, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1329 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1330 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1332 = eq(_T_1330, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1332 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1334 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1335 = or(_T_1334, reset) @[Periphery.scala 312:16] + node _T_1337 = eq(_T_1335, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1337 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1338 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1340 = eq(_T_1338, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1340 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1342 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1343 = or(_T_1342, reset) @[Periphery.scala 312:16] + node _T_1345 = eq(_T_1343, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1345 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:312:16)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1347 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1348 = or(_T_1347, reset) @[Periphery.scala 312:16] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1350 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1352 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 312:16] + when _T_1352 : @[Periphery.scala 312:16] + node _T_1355 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1357 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1358 = cvt(_T_1357) @[Parameters.scala 117:49] + node _T_1360 = and(_T_1358, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1361 = asSInt(_T_1360) @[Parameters.scala 117:52] + node _T_1363 = eq(_T_1361, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1364 = and(_T_1355, _T_1363) @[Parameters.scala 132:56] + node _T_1366 = or(UInt<1>("h00"), _T_1364) @[Parameters.scala 134:30] + node _T_1367 = or(_T_1366, reset) @[Periphery.scala 312:16] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1369 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:312:16)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1370 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1372 = eq(_T_1370, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1372 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1374 = geq(io.in[0].c.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1375 = or(_T_1374, reset) @[Periphery.scala 312:16] + node _T_1377 = eq(_T_1375, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1377 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1378 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1380 = eq(_T_1378, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1380 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1382 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1383 = or(_T_1382, reset) @[Periphery.scala 312:16] + node _T_1385 = eq(_T_1383, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1385 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:312:16)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1387 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1388 = or(_T_1387, reset) @[Periphery.scala 312:16] + node _T_1390 = eq(_T_1388, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1390 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1392 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1392 : @[Periphery.scala 312:16] + node _T_1393 = or(_T_1255[0], reset) @[Periphery.scala 312:16] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1395 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1396 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1398 = eq(_T_1396, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1398 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1399 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1401 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1403 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1404 = or(_T_1403, reset) @[Periphery.scala 312:16] + node _T_1406 = eq(_T_1404, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1406 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1408 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:16] + when _T_1408 : @[Periphery.scala 312:16] + node _T_1409 = or(_T_1255[0], reset) @[Periphery.scala 312:16] + node _T_1411 = eq(_T_1409, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1411 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1412 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1414 = eq(_T_1412, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1414 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1415 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1417 = eq(_T_1415, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1417 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1419 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1420 = or(_T_1419, reset) @[Periphery.scala 312:16] + node _T_1422 = eq(_T_1420, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1422 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1424 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:16] + when _T_1424 : @[Periphery.scala 312:16] + node _T_1425 = or(_T_1255[0], reset) @[Periphery.scala 312:16] + node _T_1427 = eq(_T_1425, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1427 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:312:16)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1428 = or(_T_1236, reset) @[Periphery.scala 312:16] + node _T_1430 = eq(_T_1428, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1430 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1431 = or(_T_1244, reset) @[Periphery.scala 312:16] + node _T_1433 = eq(_T_1431, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1433 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1435 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1436 = or(_T_1435, reset) @[Periphery.scala 312:16] + node _T_1438 = eq(_T_1436, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1438 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1440 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1441 = or(_T_1440, reset) @[Periphery.scala 312:16] + node _T_1443 = eq(_T_1441, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1443 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + when io.in[0].d.valid : @[Periphery.scala 312:16] + node _T_1445 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1446 = or(_T_1445, reset) @[Periphery.scala 312:16] + node _T_1448 = eq(_T_1446, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1448 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:312:16)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1450 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1451 = not(_T_1450) @[Parameters.scala 37:9] + node _T_1453 = or(_T_1451, UInt<6>("h03f")) @[Parameters.scala 37:28] + node _T_1454 = not(_T_1453) @[Parameters.scala 37:7] + node _T_1456 = eq(_T_1454, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1458 = xor(UInt<7>("h050"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1459 = not(_T_1458) @[Parameters.scala 37:9] + node _T_1461 = or(_T_1459, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1462 = not(_T_1461) @[Parameters.scala 37:7] + node _T_1464 = eq(_T_1462, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1466 = xor(UInt<7>("h040"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1467 = not(_T_1466) @[Parameters.scala 37:9] + node _T_1469 = or(_T_1467, UInt<4>("h0f")) @[Parameters.scala 37:28] + node _T_1470 = not(_T_1469) @[Parameters.scala 37:7] + node _T_1472 = eq(_T_1470, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1475 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1475 is invalid @[Parameters.scala 228:27] + _T_1475[0] <= _T_1456 @[Parameters.scala 228:27] + _T_1475[1] <= _T_1464 @[Parameters.scala 228:27] + _T_1475[2] <= _T_1472 @[Parameters.scala 228:27] + node _T_1481 = or(_T_1475[0], _T_1475[1]) @[Parameters.scala 229:46] + node _T_1482 = or(_T_1481, _T_1475[2]) @[Parameters.scala 229:46] + node _T_1484 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1485 = dshl(_T_1484, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1486 = bits(_T_1485, 5, 0) @[package.scala 19:76] + node _T_1487 = not(_T_1486) @[package.scala 19:40] + node _T_1488 = and(io.in[0].d.bits.addr_lo, _T_1487) @[Edges.scala 17:16] + node _T_1490 = eq(_T_1488, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1492 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 312:16] + node _T_1494 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:16] + when _T_1494 : @[Periphery.scala 312:16] + node _T_1495 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1497 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1498 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1500 = eq(_T_1498, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1500 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1501 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1503 = eq(_T_1501, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1503 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1505 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1506 = or(_T_1505, reset) @[Periphery.scala 312:16] + node _T_1508 = eq(_T_1506, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1508 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1510 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1511 = or(_T_1510, reset) @[Periphery.scala 312:16] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1513 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1515 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1516 = or(_T_1515, reset) @[Periphery.scala 312:16] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1518 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1520 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 312:16] + when _T_1520 : @[Periphery.scala 312:16] + node _T_1521 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1523 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1524 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1526 = eq(_T_1524, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1526 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1527 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1529 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1531 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1532 = or(_T_1531, reset) @[Periphery.scala 312:16] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1534 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1536 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1537 = or(_T_1536, reset) @[Periphery.scala 312:16] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1539 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:312:16)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1541 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 312:16] + when _T_1541 : @[Periphery.scala 312:16] + node _T_1542 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1544 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1545 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1547 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1548 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1550 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1552 = geq(io.in[0].d.bits.size, UInt<2>("h02")) @[Periphery.scala 312:16] + node _T_1553 = or(_T_1552, reset) @[Periphery.scala 312:16] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1555 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:312:16)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1557 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1558 = or(_T_1557, reset) @[Periphery.scala 312:16] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1560 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:312:16)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1562 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1562 : @[Periphery.scala 312:16] + node _T_1563 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1565 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1566 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1568 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1569 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1571 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1573 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1574 = or(_T_1573, reset) @[Periphery.scala 312:16] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1576 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1578 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 312:16] + when _T_1578 : @[Periphery.scala 312:16] + node _T_1579 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1581 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1582 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1584 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1585 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1587 = eq(_T_1585, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1587 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1589 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1590 = or(_T_1589, reset) @[Periphery.scala 312:16] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1592 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1594 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 312:16] + when _T_1594 : @[Periphery.scala 312:16] + node _T_1595 = or(_T_1482, reset) @[Periphery.scala 312:16] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1597 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1598 = or(_T_1490, reset) @[Periphery.scala 312:16] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1600 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:312:16)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1601 = or(_T_1492, reset) @[Periphery.scala 312:16] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1603 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1605 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1606 = or(_T_1605, reset) @[Periphery.scala 312:16] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1608 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:312:16)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1610 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1611 = or(_T_1610, reset) @[Periphery.scala 312:16] + node _T_1613 = eq(_T_1611, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1613 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:312:16)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + when io.in[0].e.valid : @[Periphery.scala 312:16] + node _T_1615 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 312:16] + node _T_1616 = or(_T_1615, reset) @[Periphery.scala 312:16] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1618 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:312:16)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1619 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1621 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1622 = dshl(_T_1621, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1623 = bits(_T_1622, 5, 0) @[package.scala 19:76] + node _T_1624 = not(_T_1623) @[package.scala 19:40] + node _T_1625 = shr(_T_1624, 2) @[Edges.scala 198:59] + node _T_1626 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1628 = eq(_T_1626, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1631 = mux(UInt<1>("h00"), _T_1625, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1633 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1635 = sub(_T_1633, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1636 = asUInt(_T_1635) @[Edges.scala 208:28] + node _T_1637 = tail(_T_1636, 1) @[Edges.scala 208:28] + node _T_1639 = eq(_T_1633, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1641 = eq(_T_1633, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1643 = eq(_T_1631, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1644 = or(_T_1641, _T_1643) @[Edges.scala 210:37] + node _T_1645 = and(_T_1644, _T_1619) @[Edges.scala 211:22] + node _T_1646 = not(_T_1637) @[Edges.scala 212:27] + node _T_1647 = and(_T_1631, _T_1646) @[Edges.scala 212:25] + when _T_1619 : @[Edges.scala 213:17] + node _T_1648 = mux(_T_1639, _T_1631, _T_1637) @[Edges.scala 214:21] + _T_1633 <= _T_1648 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1650 : UInt, clock @[Periphery.scala 312:16] + reg _T_1652 : UInt, clock @[Periphery.scala 312:16] + reg _T_1654 : UInt, clock @[Periphery.scala 312:16] + reg _T_1656 : UInt, clock @[Periphery.scala 312:16] + reg _T_1658 : UInt, clock @[Periphery.scala 312:16] + node _T_1660 = eq(_T_1639, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1661 = and(io.in[0].a.valid, _T_1660) @[Periphery.scala 312:16] + when _T_1661 : @[Periphery.scala 312:16] + node _T_1662 = eq(io.in[0].a.bits.opcode, _T_1650) @[Periphery.scala 312:16] + node _T_1663 = or(_T_1662, reset) @[Periphery.scala 312:16] + node _T_1665 = eq(_T_1663, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1665 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1666 = eq(io.in[0].a.bits.param, _T_1652) @[Periphery.scala 312:16] + node _T_1667 = or(_T_1666, reset) @[Periphery.scala 312:16] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1669 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1670 = eq(io.in[0].a.bits.size, _T_1654) @[Periphery.scala 312:16] + node _T_1671 = or(_T_1670, reset) @[Periphery.scala 312:16] + node _T_1673 = eq(_T_1671, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1673 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1674 = eq(io.in[0].a.bits.source, _T_1656) @[Periphery.scala 312:16] + node _T_1675 = or(_T_1674, reset) @[Periphery.scala 312:16] + node _T_1677 = eq(_T_1675, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1677 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1678 = eq(io.in[0].a.bits.address, _T_1658) @[Periphery.scala 312:16] + node _T_1679 = or(_T_1678, reset) @[Periphery.scala 312:16] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1681 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1682 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1683 = and(_T_1682, _T_1639) @[Periphery.scala 312:16] + when _T_1683 : @[Periphery.scala 312:16] + _T_1650 <= io.in[0].a.bits.opcode @[Periphery.scala 312:16] + _T_1652 <= io.in[0].a.bits.param @[Periphery.scala 312:16] + _T_1654 <= io.in[0].a.bits.size @[Periphery.scala 312:16] + _T_1656 <= io.in[0].a.bits.source @[Periphery.scala 312:16] + _T_1658 <= io.in[0].a.bits.address @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1684 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1686 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1687 = dshl(_T_1686, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1688 = bits(_T_1687, 5, 0) @[package.scala 19:76] + node _T_1689 = not(_T_1688) @[package.scala 19:40] + node _T_1690 = shr(_T_1689, 2) @[Edges.scala 198:59] + node _T_1691 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1693 = eq(_T_1691, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1696 = mux(UInt<1>("h00"), _T_1690, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1698 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1700 = sub(_T_1698, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1701 = asUInt(_T_1700) @[Edges.scala 208:28] + node _T_1702 = tail(_T_1701, 1) @[Edges.scala 208:28] + node _T_1704 = eq(_T_1698, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1706 = eq(_T_1698, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1708 = eq(_T_1696, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1709 = or(_T_1706, _T_1708) @[Edges.scala 210:37] + node _T_1710 = and(_T_1709, _T_1684) @[Edges.scala 211:22] + node _T_1711 = not(_T_1702) @[Edges.scala 212:27] + node _T_1712 = and(_T_1696, _T_1711) @[Edges.scala 212:25] + when _T_1684 : @[Edges.scala 213:17] + node _T_1713 = mux(_T_1704, _T_1696, _T_1702) @[Edges.scala 214:21] + _T_1698 <= _T_1713 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1715 : UInt, clock @[Periphery.scala 312:16] + reg _T_1717 : UInt, clock @[Periphery.scala 312:16] + reg _T_1719 : UInt, clock @[Periphery.scala 312:16] + reg _T_1721 : UInt, clock @[Periphery.scala 312:16] + reg _T_1723 : UInt, clock @[Periphery.scala 312:16] + node _T_1725 = eq(_T_1704, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1726 = and(io.in[0].b.valid, _T_1725) @[Periphery.scala 312:16] + when _T_1726 : @[Periphery.scala 312:16] + node _T_1727 = eq(io.in[0].b.bits.opcode, _T_1715) @[Periphery.scala 312:16] + node _T_1728 = or(_T_1727, reset) @[Periphery.scala 312:16] + node _T_1730 = eq(_T_1728, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1730 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1731 = eq(io.in[0].b.bits.param, _T_1717) @[Periphery.scala 312:16] + node _T_1732 = or(_T_1731, reset) @[Periphery.scala 312:16] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1734 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1735 = eq(io.in[0].b.bits.size, _T_1719) @[Periphery.scala 312:16] + node _T_1736 = or(_T_1735, reset) @[Periphery.scala 312:16] + node _T_1738 = eq(_T_1736, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1738 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1739 = eq(io.in[0].b.bits.source, _T_1721) @[Periphery.scala 312:16] + node _T_1740 = or(_T_1739, reset) @[Periphery.scala 312:16] + node _T_1742 = eq(_T_1740, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1742 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1743 = eq(io.in[0].b.bits.address, _T_1723) @[Periphery.scala 312:16] + node _T_1744 = or(_T_1743, reset) @[Periphery.scala 312:16] + node _T_1746 = eq(_T_1744, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1746 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1747 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1748 = and(_T_1747, _T_1704) @[Periphery.scala 312:16] + when _T_1748 : @[Periphery.scala 312:16] + _T_1715 <= io.in[0].b.bits.opcode @[Periphery.scala 312:16] + _T_1717 <= io.in[0].b.bits.param @[Periphery.scala 312:16] + _T_1719 <= io.in[0].b.bits.size @[Periphery.scala 312:16] + _T_1721 <= io.in[0].b.bits.source @[Periphery.scala 312:16] + _T_1723 <= io.in[0].b.bits.address @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1749 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1751 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1752 = dshl(_T_1751, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1753 = bits(_T_1752, 5, 0) @[package.scala 19:76] + node _T_1754 = not(_T_1753) @[package.scala 19:40] + node _T_1755 = shr(_T_1754, 2) @[Edges.scala 198:59] + node _T_1756 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1758 = mux(_T_1756, _T_1755, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1760 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1762 = sub(_T_1760, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1763 = asUInt(_T_1762) @[Edges.scala 208:28] + node _T_1764 = tail(_T_1763, 1) @[Edges.scala 208:28] + node _T_1766 = eq(_T_1760, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1768 = eq(_T_1760, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1770 = eq(_T_1758, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1771 = or(_T_1768, _T_1770) @[Edges.scala 210:37] + node _T_1772 = and(_T_1771, _T_1749) @[Edges.scala 211:22] + node _T_1773 = not(_T_1764) @[Edges.scala 212:27] + node _T_1774 = and(_T_1758, _T_1773) @[Edges.scala 212:25] + when _T_1749 : @[Edges.scala 213:17] + node _T_1775 = mux(_T_1766, _T_1758, _T_1764) @[Edges.scala 214:21] + _T_1760 <= _T_1775 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1777 : UInt, clock @[Periphery.scala 312:16] + reg _T_1779 : UInt, clock @[Periphery.scala 312:16] + reg _T_1781 : UInt, clock @[Periphery.scala 312:16] + reg _T_1783 : UInt, clock @[Periphery.scala 312:16] + reg _T_1785 : UInt, clock @[Periphery.scala 312:16] + node _T_1787 = eq(_T_1766, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1788 = and(io.in[0].c.valid, _T_1787) @[Periphery.scala 312:16] + when _T_1788 : @[Periphery.scala 312:16] + node _T_1789 = eq(io.in[0].c.bits.opcode, _T_1777) @[Periphery.scala 312:16] + node _T_1790 = or(_T_1789, reset) @[Periphery.scala 312:16] + node _T_1792 = eq(_T_1790, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1792 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1793 = eq(io.in[0].c.bits.param, _T_1779) @[Periphery.scala 312:16] + node _T_1794 = or(_T_1793, reset) @[Periphery.scala 312:16] + node _T_1796 = eq(_T_1794, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1796 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1797 = eq(io.in[0].c.bits.size, _T_1781) @[Periphery.scala 312:16] + node _T_1798 = or(_T_1797, reset) @[Periphery.scala 312:16] + node _T_1800 = eq(_T_1798, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1800 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1801 = eq(io.in[0].c.bits.source, _T_1783) @[Periphery.scala 312:16] + node _T_1802 = or(_T_1801, reset) @[Periphery.scala 312:16] + node _T_1804 = eq(_T_1802, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1804 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1805 = eq(io.in[0].c.bits.address, _T_1785) @[Periphery.scala 312:16] + node _T_1806 = or(_T_1805, reset) @[Periphery.scala 312:16] + node _T_1808 = eq(_T_1806, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1808 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1809 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1810 = and(_T_1809, _T_1766) @[Periphery.scala 312:16] + when _T_1810 : @[Periphery.scala 312:16] + _T_1777 <= io.in[0].c.bits.opcode @[Periphery.scala 312:16] + _T_1779 <= io.in[0].c.bits.param @[Periphery.scala 312:16] + _T_1781 <= io.in[0].c.bits.size @[Periphery.scala 312:16] + _T_1783 <= io.in[0].c.bits.source @[Periphery.scala 312:16] + _T_1785 <= io.in[0].c.bits.address @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1811 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1813 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1814 = dshl(_T_1813, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1815 = bits(_T_1814, 5, 0) @[package.scala 19:76] + node _T_1816 = not(_T_1815) @[package.scala 19:40] + node _T_1817 = shr(_T_1816, 2) @[Edges.scala 198:59] + node _T_1818 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1821 = mux(UInt<1>("h01"), _T_1817, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1823 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1825 = sub(_T_1823, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1826 = asUInt(_T_1825) @[Edges.scala 208:28] + node _T_1827 = tail(_T_1826, 1) @[Edges.scala 208:28] + node _T_1829 = eq(_T_1823, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1831 = eq(_T_1823, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1833 = eq(_T_1821, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1834 = or(_T_1831, _T_1833) @[Edges.scala 210:37] + node _T_1835 = and(_T_1834, _T_1811) @[Edges.scala 211:22] + node _T_1836 = not(_T_1827) @[Edges.scala 212:27] + node _T_1837 = and(_T_1821, _T_1836) @[Edges.scala 212:25] + when _T_1811 : @[Edges.scala 213:17] + node _T_1838 = mux(_T_1829, _T_1821, _T_1827) @[Edges.scala 214:21] + _T_1823 <= _T_1838 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1840 : UInt, clock @[Periphery.scala 312:16] + reg _T_1842 : UInt, clock @[Periphery.scala 312:16] + reg _T_1844 : UInt, clock @[Periphery.scala 312:16] + reg _T_1846 : UInt, clock @[Periphery.scala 312:16] + reg _T_1848 : UInt, clock @[Periphery.scala 312:16] + reg _T_1850 : UInt, clock @[Periphery.scala 312:16] + node _T_1852 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1853 = and(io.in[0].d.valid, _T_1852) @[Periphery.scala 312:16] + when _T_1853 : @[Periphery.scala 312:16] + node _T_1854 = eq(io.in[0].d.bits.opcode, _T_1840) @[Periphery.scala 312:16] + node _T_1855 = or(_T_1854, reset) @[Periphery.scala 312:16] + node _T_1857 = eq(_T_1855, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1857 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1858 = eq(io.in[0].d.bits.param, _T_1842) @[Periphery.scala 312:16] + node _T_1859 = or(_T_1858, reset) @[Periphery.scala 312:16] + node _T_1861 = eq(_T_1859, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1861 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1862 = eq(io.in[0].d.bits.size, _T_1844) @[Periphery.scala 312:16] + node _T_1863 = or(_T_1862, reset) @[Periphery.scala 312:16] + node _T_1865 = eq(_T_1863, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1865 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1866 = eq(io.in[0].d.bits.source, _T_1846) @[Periphery.scala 312:16] + node _T_1867 = or(_T_1866, reset) @[Periphery.scala 312:16] + node _T_1869 = eq(_T_1867, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1869 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1870 = eq(io.in[0].d.bits.sink, _T_1848) @[Periphery.scala 312:16] + node _T_1871 = or(_T_1870, reset) @[Periphery.scala 312:16] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1873 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1874 = eq(io.in[0].d.bits.addr_lo, _T_1850) @[Periphery.scala 312:16] + node _T_1875 = or(_T_1874, reset) @[Periphery.scala 312:16] + node _T_1877 = eq(_T_1875, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1877 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:312:16)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1878 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1879 = and(_T_1878, _T_1829) @[Periphery.scala 312:16] + when _T_1879 : @[Periphery.scala 312:16] + _T_1840 <= io.in[0].d.bits.opcode @[Periphery.scala 312:16] + _T_1842 <= io.in[0].d.bits.param @[Periphery.scala 312:16] + _T_1844 <= io.in[0].d.bits.size @[Periphery.scala 312:16] + _T_1846 <= io.in[0].d.bits.source @[Periphery.scala 312:16] + _T_1848 <= io.in[0].d.bits.sink @[Periphery.scala 312:16] + _T_1850 <= io.in[0].d.bits.addr_lo @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + reg _T_1881 : UInt<96>, clock with : (reset => (reset, UInt<96>("h00"))) @[Reg.scala 26:44] + node _T_1882 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1884 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1885 = dshl(_T_1884, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1886 = bits(_T_1885, 5, 0) @[package.scala 19:76] + node _T_1887 = not(_T_1886) @[package.scala 19:40] + node _T_1888 = shr(_T_1887, 2) @[Edges.scala 198:59] + node _T_1889 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1894 = mux(UInt<1>("h00"), _T_1888, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1896 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1898 = sub(_T_1896, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1899 = asUInt(_T_1898) @[Edges.scala 208:28] + node _T_1900 = tail(_T_1899, 1) @[Edges.scala 208:28] + node _T_1902 = eq(_T_1896, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1904 = eq(_T_1896, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1906 = eq(_T_1894, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1907 = or(_T_1904, _T_1906) @[Edges.scala 210:37] + node _T_1908 = and(_T_1907, _T_1882) @[Edges.scala 211:22] + node _T_1909 = not(_T_1900) @[Edges.scala 212:27] + node _T_1910 = and(_T_1894, _T_1909) @[Edges.scala 212:25] + when _T_1882 : @[Edges.scala 213:17] + node _T_1911 = mux(_T_1902, _T_1894, _T_1900) @[Edges.scala 214:21] + _T_1896 <= _T_1911 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1912 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1914 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1915 = dshl(_T_1914, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1916 = bits(_T_1915, 5, 0) @[package.scala 19:76] + node _T_1917 = not(_T_1916) @[package.scala 19:40] + node _T_1918 = shr(_T_1917, 2) @[Edges.scala 198:59] + node _T_1919 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1922 = mux(UInt<1>("h01"), _T_1918, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1924 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_1926 = sub(_T_1924, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1927 = asUInt(_T_1926) @[Edges.scala 208:28] + node _T_1928 = tail(_T_1927, 1) @[Edges.scala 208:28] + node _T_1930 = eq(_T_1924, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1932 = eq(_T_1924, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1934 = eq(_T_1922, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1935 = or(_T_1932, _T_1934) @[Edges.scala 210:37] + node _T_1936 = and(_T_1935, _T_1912) @[Edges.scala 211:22] + node _T_1937 = not(_T_1928) @[Edges.scala 212:27] + node _T_1938 = and(_T_1922, _T_1937) @[Edges.scala 212:25] + when _T_1912 : @[Edges.scala 213:17] + node _T_1939 = mux(_T_1930, _T_1922, _T_1928) @[Edges.scala 214:21] + _T_1924 <= _T_1939 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1941 : UInt<96> + _T_1941 is invalid + _T_1941 <= UInt<96>("h00") + node _T_1942 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1942 : @[Periphery.scala 312:16] + when _T_1907 : @[Periphery.scala 312:16] + node _T_1944 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1941 <= _T_1944 @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1945 = dshr(_T_1881, io.in[0].a.bits.source) @[Periphery.scala 312:16] + node _T_1946 = bits(_T_1945, 0, 0) @[Periphery.scala 312:16] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[Periphery.scala 312:16] + node _T_1949 = or(_T_1948, reset) @[Periphery.scala 312:16] + node _T_1951 = eq(_T_1949, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1951 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:312:16)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + wire _T_1953 : UInt<96> + _T_1953 is invalid + _T_1953 <= UInt<96>("h00") + node _T_1954 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1956 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 312:16] + node _T_1957 = and(_T_1954, _T_1956) @[Periphery.scala 312:16] + when _T_1957 : @[Periphery.scala 312:16] + when _T_1935 : @[Periphery.scala 312:16] + node _T_1959 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1953 <= _T_1959 @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1960 = or(_T_1941, _T_1881) @[Periphery.scala 312:16] + node _T_1961 = dshr(_T_1960, io.in[0].d.bits.source) @[Periphery.scala 312:16] + node _T_1962 = bits(_T_1961, 0, 0) @[Periphery.scala 312:16] + node _T_1963 = or(_T_1962, reset) @[Periphery.scala 312:16] + node _T_1965 = eq(_T_1963, UInt<1>("h00")) @[Periphery.scala 312:16] + when _T_1965 : @[Periphery.scala 312:16] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:312:16)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 312:16] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + skip @[Periphery.scala 312:16] + node _T_1966 = or(_T_1881, _T_1941) @[Periphery.scala 312:16] + node _T_1967 = not(_T_1953) @[Periphery.scala 312:16] + node _T_1968 = and(_T_1966, _T_1967) @[Periphery.scala 312:16] + _T_1881 <= _T_1968 @[Periphery.scala 312:16] + + module Queue_28 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module TLZero_zeros_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + inst a of Queue_28 @[Decoupled.scala 253:19] + a.io is invalid + a.clock <= clock + a.reset <= reset + a.io.enq.valid <= io.in.0.a.valid @[Decoupled.scala 254:20] + a.io.enq.bits <- io.in.0.a.bits @[Decoupled.scala 255:19] + io.in.0.a.ready <= a.io.enq.ready @[Decoupled.scala 256:15] + node _T_361 = bits(a.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node hasData = eq(_T_361, UInt<1>("h00")) @[Edges.scala 76:28] + a.io.deq.ready <= io.in.0.d.ready @[Zero.scala 37:13] + io.in.0.d.valid <= a.io.deq.valid @[Zero.scala 38:16] + wire _T_374 : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_374 is invalid @[Edges.scala 617:17] + _T_374.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_374.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_374.size <= a.io.deq.bits.size @[Edges.scala 620:15] + _T_374.source <= a.io.deq.bits.source @[Edges.scala 621:15] + _T_374.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_385 = bits(a.io.deq.bits.address, 2, 0) @[Edges.scala 172:47] + _T_374.addr_lo <= _T_385 @[Edges.scala 623:15] + _T_374.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_374.error <= UInt<1>("h00") @[Edges.scala 625:15] + io.in.0.d.bits <- _T_374 @[Zero.scala 39:15] + node _T_389 = mux(hasData, UInt<1>("h00"), UInt<1>("h01")) @[Zero.scala 40:28] + io.in.0.d.bits.opcode <= _T_389 @[Zero.scala 40:22] + io.in.0.b.valid <= UInt<1>("h00") @[Zero.scala 43:16] + io.in.0.c.ready <= UInt<1>("h01") @[Zero.scala 44:16] + io.in.0.e.ready <= UInt<1>("h01") @[Zero.scala 45:16] + + module Repeater_2 : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLFragmenter_zeros_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg _T_531 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + reg _T_533 : UInt, clock @[Fragmenter.scala 136:22] + node _T_534 = bits(io.out.0.d.bits.source, 2, 0) @[Fragmenter.scala 137:39] + node _T_536 = eq(_T_531, UInt<1>("h00")) @[Fragmenter.scala 138:27] + node _T_538 = bits(io.out.0.d.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_539 = dshl(UInt<1>("h01"), _T_538) @[OneHot.scala 49:12] + node _T_540 = bits(_T_539, 3, 0) @[OneHot.scala 49:37] + node _T_542 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_543 = dshl(_T_542, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_544 = bits(_T_543, 2, 0) @[package.scala 19:76] + node _T_545 = not(_T_544) @[package.scala 19:40] + node _T_546 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_547 = shl(_T_534, 0) @[Fragmenter.scala 144:38] + node _T_548 = shr(_T_545, 3) @[Fragmenter.scala 145:34] + node _T_550 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Fragmenter.scala 146:15] + node _T_551 = and(_T_547, _T_548) @[Fragmenter.scala 146:48] + node _T_553 = eq(_T_551, UInt<1>("h00")) @[Fragmenter.scala 146:63] + node _T_554 = or(_T_550, _T_553) @[Fragmenter.scala 146:28] + node _T_555 = or(_T_554, reset) @[Fragmenter.scala 146:14] + node _T_557 = eq(_T_555, UInt<1>("h00")) @[Fragmenter.scala 146:14] + when _T_557 : @[Fragmenter.scala 146:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:146 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n") @[Fragmenter.scala 146:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 146:14] + skip @[Fragmenter.scala 146:14] + node _T_559 = mux(_T_546, _T_548, UInt<1>("h00")) @[Fragmenter.scala 147:48] + node _T_560 = or(_T_547, _T_559) @[Fragmenter.scala 147:43] + node _T_562 = shr(_T_540, 3) @[Fragmenter.scala 148:58] + node _T_563 = mux(_T_546, UInt<1>("h01"), _T_562) @[Fragmenter.scala 148:30] + node _T_564 = shl(_T_534, 3) @[Fragmenter.scala 150:45] + node _T_565 = or(_T_564, _T_545) @[Fragmenter.scala 150:67] + node _T_566 = shl(_T_565, 1) @[package.scala 17:29] + node _T_568 = or(_T_566, UInt<1>("h01")) @[package.scala 17:34] + node _T_570 = cat(UInt<1>("h00"), _T_565) @[Cat.scala 30:58] + node _T_571 = not(_T_570) @[package.scala 17:47] + node _T_572 = and(_T_568, _T_571) @[package.scala 17:45] + node _T_573 = bits(_T_572, 6, 4) @[OneHot.scala 26:18] + node _T_574 = bits(_T_572, 3, 0) @[OneHot.scala 27:18] + node _T_576 = neq(_T_573, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_577 = or(_T_573, _T_574) @[OneHot.scala 28:28] + node _T_578 = bits(_T_577, 3, 2) @[OneHot.scala 26:18] + node _T_579 = bits(_T_577, 1, 0) @[OneHot.scala 27:18] + node _T_581 = neq(_T_578, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_582 = or(_T_578, _T_579) @[OneHot.scala 28:28] + node _T_583 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_584 = cat(_T_581, _T_583) @[Cat.scala 30:58] + node _T_585 = cat(_T_576, _T_584) @[Cat.scala 30:58] + node _T_586 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_586 : @[Fragmenter.scala 152:27] + node _T_587 = sub(_T_531, _T_563) @[Fragmenter.scala 153:53] + node _T_588 = asUInt(_T_587) @[Fragmenter.scala 153:53] + node _T_589 = tail(_T_588, 1) @[Fragmenter.scala 153:53] + node _T_590 = mux(_T_536, _T_560, _T_589) @[Fragmenter.scala 153:22] + _T_531 <= _T_590 @[Fragmenter.scala 153:16] + when _T_536 : @[Fragmenter.scala 154:23] + _T_533 <= _T_585 @[Fragmenter.scala 154:31] + skip @[Fragmenter.scala 154:23] + skip @[Fragmenter.scala 152:27] + node _T_592 = eq(_T_546, UInt<1>("h00")) @[Fragmenter.scala 158:18] + node _T_594 = neq(_T_534, UInt<1>("h00")) @[Fragmenter.scala 158:41] + node _T_595 = and(_T_592, _T_594) @[Fragmenter.scala 158:28] + node _T_596 = or(io.in.0.d.ready, _T_595) @[Fragmenter.scala 159:33] + io.out.0.d.ready <= _T_596 @[Fragmenter.scala 159:19] + node _T_598 = eq(_T_595, UInt<1>("h00")) @[Fragmenter.scala 160:37] + node _T_599 = and(io.out.0.d.valid, _T_598) @[Fragmenter.scala 160:34] + io.in.0.d.valid <= _T_599 @[Fragmenter.scala 160:19] + io.in.0.d.bits <- io.out.0.d.bits @[Fragmenter.scala 161:19] + node _T_600 = not(_T_545) @[Fragmenter.scala 162:49] + node _T_601 = and(io.out.0.d.bits.addr_lo, _T_600) @[Fragmenter.scala 162:47] + io.in.0.d.bits.addr_lo <= _T_601 @[Fragmenter.scala 162:25] + node _T_602 = shr(io.out.0.d.bits.source, 3) @[Fragmenter.scala 163:45] + io.in.0.d.bits.source <= _T_602 @[Fragmenter.scala 163:24] + node _T_603 = mux(_T_536, _T_585, _T_533) @[Fragmenter.scala 164:30] + io.in.0.d.bits.size <= _T_603 @[Fragmenter.scala 164:24] + reg _T_605 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_606 = or(_T_605, io.out.0.d.bits.error) @[Fragmenter.scala 168:29] + node _T_607 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_607 : @[Fragmenter.scala 169:27] + node _T_609 = mux(_T_595, _T_606, UInt<1>("h00")) @[Fragmenter.scala 169:43] + _T_605 <= _T_609 @[Fragmenter.scala 169:37] + skip @[Fragmenter.scala 169:27] + io.in.0.d.bits.error <= _T_606 @[Fragmenter.scala 170:23] + inst Repeater of Repeater_2 @[Fragmenter.scala 190:28] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.enq <- io.in.0.a @[Fragmenter.scala 191:23] + node _T_615 = xor(Repeater.io.deq.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_616 = cvt(_T_615) @[Parameters.scala 117:49] + node _T_618 = and(_T_616, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_619 = asSInt(_T_618) @[Parameters.scala 117:52] + node _T_621 = eq(_T_619, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_624 : UInt<1>[1] @[Parameters.scala 112:36] + _T_624 is invalid @[Parameters.scala 112:36] + _T_624[0] <= _T_621 @[Parameters.scala 112:36] + node _T_634 = eq(UInt<3>("h05"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_635 = mux(_T_634, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 46:16] + node _T_636 = eq(UInt<3>("h04"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_637 = mux(_T_636, UInt<2>("h03"), _T_635) @[Mux.scala 46:16] + node _T_638 = eq(UInt<2>("h03"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_639 = mux(_T_638, UInt<2>("h03"), _T_637) @[Mux.scala 46:16] + node _T_640 = eq(UInt<2>("h02"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_641 = mux(_T_640, UInt<2>("h03"), _T_639) @[Mux.scala 46:16] + node _T_642 = eq(UInt<1>("h01"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_643 = mux(_T_642, UInt<2>("h03"), _T_641) @[Mux.scala 46:16] + node _T_644 = eq(UInt<1>("h00"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_645 = mux(_T_644, UInt<2>("h03"), _T_643) @[Mux.scala 46:16] + node _T_646 = gt(Repeater.io.deq.bits.size, _T_645) @[Fragmenter.scala 213:29] + node _T_647 = mux(_T_646, _T_645, Repeater.io.deq.bits.size) @[Fragmenter.scala 213:22] + node _T_649 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_650 = dshl(_T_649, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_651 = bits(_T_650, 5, 0) @[package.scala 19:76] + node _T_652 = not(_T_651) @[package.scala 19:40] + node _T_654 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_655 = dshl(_T_654, _T_647) @[package.scala 19:71] + node _T_656 = bits(_T_655, 2, 0) @[package.scala 19:76] + node _T_657 = not(_T_656) @[package.scala 19:40] + node _T_658 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_660 = eq(_T_658, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_662 = mux(_T_660, UInt<1>("h00"), _T_657) @[Fragmenter.scala 217:22] + reg _T_664 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[Fragmenter.scala 220:27] + node _T_667 = shr(_T_652, 3) @[Fragmenter.scala 221:46] + node _T_669 = sub(_T_664, UInt<1>("h01")) @[Fragmenter.scala 221:77] + node _T_670 = asUInt(_T_669) @[Fragmenter.scala 221:77] + node _T_671 = tail(_T_670, 1) @[Fragmenter.scala 221:77] + node _T_672 = mux(_T_666, _T_667, _T_671) @[Fragmenter.scala 221:28] + node _T_673 = not(_T_672) @[Fragmenter.scala 222:26] + node _T_674 = shr(_T_662, 3) @[Fragmenter.scala 222:48] + node _T_675 = or(_T_673, _T_674) @[Fragmenter.scala 222:39] + node _T_676 = not(_T_675) @[Fragmenter.scala 222:24] + node _T_677 = shr(_T_672, 0) @[Fragmenter.scala 223:38] + node _T_678 = not(_T_677) @[Fragmenter.scala 223:24] + node _T_679 = shr(_T_657, 3) @[Fragmenter.scala 223:82] + node _T_680 = or(_T_678, _T_679) @[Fragmenter.scala 223:70] + node _T_681 = not(_T_680) @[Fragmenter.scala 223:22] + node _T_682 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Fragmenter.scala 225:27] + _T_664 <= _T_676 @[Fragmenter.scala 225:36] + skip @[Fragmenter.scala 225:27] + node _T_684 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 227:29] + node _T_686 = neq(_T_681, UInt<1>("h00")) @[Fragmenter.scala 227:51] + node _T_687 = and(_T_684, _T_686) @[Fragmenter.scala 227:39] + Repeater.io.repeat <= _T_687 @[Fragmenter.scala 227:26] + io.out.0.a <- Repeater.io.deq @[Fragmenter.scala 228:13] + node _T_688 = not(_T_681) @[Fragmenter.scala 229:50] + node _T_689 = shl(_T_688, 3) @[Fragmenter.scala 229:60] + node _T_690 = and(_T_689, _T_652) @[Fragmenter.scala 229:81] + node _T_691 = or(Repeater.io.deq.bits.address, _T_690) @[Fragmenter.scala 229:47] + io.out.0.a.bits.address <= _T_691 @[Fragmenter.scala 229:26] + node _T_692 = cat(Repeater.io.deq.bits.source, _T_681) @[Cat.scala 30:58] + io.out.0.a.bits.source <= _T_692 @[Fragmenter.scala 230:25] + io.out.0.a.bits.size <= _T_647 @[Fragmenter.scala 231:23] + node _T_694 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 234:15] + node _T_696 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 234:36] + node _T_697 = or(_T_694, _T_696) @[Fragmenter.scala 234:33] + node _T_698 = or(_T_697, reset) @[Fragmenter.scala 234:14] + node _T_700 = eq(_T_698, UInt<1>("h00")) @[Fragmenter.scala 234:14] + when _T_700 : @[Fragmenter.scala 234:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:234 assert (!repeater.io.full || !aHasData)\n") @[Fragmenter.scala 234:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 234:14] + skip @[Fragmenter.scala 234:14] + io.out.0.a.bits.data <= io.in.0.a.bits.data @[Fragmenter.scala 235:23] + node _T_703 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 237:15] + node _T_704 = eq(Repeater.io.deq.bits.mask, UInt<8>("h0ff")) @[Fragmenter.scala 237:51] + node _T_705 = or(_T_703, _T_704) @[Fragmenter.scala 237:33] + node _T_706 = or(_T_705, reset) @[Fragmenter.scala 237:14] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 237:14] + when _T_708 : @[Fragmenter.scala 237:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") @[Fragmenter.scala 237:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 237:14] + skip @[Fragmenter.scala 237:14] + node _T_709 = mux(Repeater.io.full, UInt<8>("h0ff"), io.in.0.a.bits.mask) @[Fragmenter.scala 238:29] + io.out.0.a.bits.mask <= _T_709 @[Fragmenter.scala 238:23] + io.in.0.b.valid <= UInt<1>("h00") @[Fragmenter.scala 241:18] + io.in.0.c.ready <= UInt<1>("h01") @[Fragmenter.scala 242:18] + io.in.0.e.ready <= UInt<1>("h01") @[Fragmenter.scala 243:18] + io.out.0.b.ready <= UInt<1>("h01") @[Fragmenter.scala 244:19] + io.out.0.c.valid <= UInt<1>("h00") @[Fragmenter.scala 245:19] + io.out.0.e.valid <= UInt<1>("h00") @[Fragmenter.scala 246:19] + + module TLMonitor_12 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 149:59] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 149:59] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_608 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:149:59)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 5, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + when _T_700 : @[Periphery.scala 149:59] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_712 = and(_T_703, _T_711) @[Parameters.scala 132:56] + node _T_714 = or(UInt<1>("h00"), _T_712) @[Parameters.scala 134:30] + node _T_715 = or(_T_714, reset) @[Periphery.scala 149:59] + node _T_717 = eq(_T_715, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_717 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_718 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_720 = eq(_T_718, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_720 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_722 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_723 = or(_T_722, reset) @[Periphery.scala 149:59] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_725 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_726 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_728 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_730 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_731 = or(_T_730, reset) @[Periphery.scala 149:59] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_733 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:149:59)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_734 = not(io.in[0].a.bits.mask) @[Periphery.scala 149:59] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_737 = or(_T_736, reset) @[Periphery.scala 149:59] + node _T_739 = eq(_T_737, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_739 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_741 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:59] + when _T_741 : @[Periphery.scala 149:59] + node _T_744 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_746 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_747 = and(_T_744, _T_746) @[Parameters.scala 63:37] + node _T_748 = or(UInt<1>("h00"), _T_747) @[Parameters.scala 132:31] + node _T_750 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_751 = cvt(_T_750) @[Parameters.scala 117:49] + node _T_753 = and(_T_751, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_754 = asSInt(_T_753) @[Parameters.scala 117:52] + node _T_756 = eq(_T_754, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_757 = and(_T_748, _T_756) @[Parameters.scala 132:56] + node _T_759 = or(UInt<1>("h00"), _T_757) @[Parameters.scala 134:30] + node _T_760 = or(_T_759, reset) @[Periphery.scala 149:59] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_762 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_763 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_765 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_766 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_768 = eq(_T_766, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_768 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_770 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_771 = or(_T_770, reset) @[Periphery.scala 149:59] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_773 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_774 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:59] + node _T_775 = or(_T_774, reset) @[Periphery.scala 149:59] + node _T_777 = eq(_T_775, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_777 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_779 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_779 : @[Periphery.scala 149:59] + node _T_782 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_784 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_785 = and(_T_782, _T_784) @[Parameters.scala 63:37] + node _T_786 = or(UInt<1>("h00"), _T_785) @[Parameters.scala 132:31] + node _T_788 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_789 = cvt(_T_788) @[Parameters.scala 117:49] + node _T_791 = and(_T_789, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_792 = asSInt(_T_791) @[Parameters.scala 117:52] + node _T_794 = eq(_T_792, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_795 = and(_T_786, _T_794) @[Parameters.scala 132:56] + node _T_797 = or(UInt<1>("h00"), _T_795) @[Parameters.scala 134:30] + node _T_798 = or(_T_797, reset) @[Periphery.scala 149:59] + node _T_800 = eq(_T_798, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_800 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_801 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_803 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_804 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_806 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_808 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_809 = or(_T_808, reset) @[Periphery.scala 149:59] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_811 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_812 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:59] + node _T_813 = or(_T_812, reset) @[Periphery.scala 149:59] + node _T_815 = eq(_T_813, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_815 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_817 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:59] + when _T_817 : @[Periphery.scala 149:59] + node _T_820 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_822 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_823 = and(_T_820, _T_822) @[Parameters.scala 63:37] + node _T_824 = or(UInt<1>("h00"), _T_823) @[Parameters.scala 132:31] + node _T_826 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = and(_T_824, _T_832) @[Parameters.scala 132:56] + node _T_835 = or(UInt<1>("h00"), _T_833) @[Parameters.scala 134:30] + node _T_836 = or(_T_835, reset) @[Periphery.scala 149:59] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_838 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_839 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_841 = eq(_T_839, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_841 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_842 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_844 = eq(_T_842, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_844 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_846 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_847 = or(_T_846, reset) @[Periphery.scala 149:59] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_849 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_850 = not(_T_698) @[Periphery.scala 149:59] + node _T_851 = and(io.in[0].a.bits.mask, _T_850) @[Periphery.scala 149:59] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_854 = or(_T_853, reset) @[Periphery.scala 149:59] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_856 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_858 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:59] + when _T_858 : @[Periphery.scala 149:59] + node _T_861 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_863 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_864 = cvt(_T_863) @[Parameters.scala 117:49] + node _T_866 = and(_T_864, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_867 = asSInt(_T_866) @[Parameters.scala 117:52] + node _T_869 = eq(_T_867, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = and(_T_861, _T_869) @[Parameters.scala 132:56] + node _T_872 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 134:30] + node _T_873 = or(_T_872, reset) @[Periphery.scala 149:59] + node _T_875 = eq(_T_873, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_875 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_876 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_878 = eq(_T_876, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_878 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_879 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_881 = eq(_T_879, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_881 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_883 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_884 = or(_T_883, reset) @[Periphery.scala 149:59] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_886 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:149:59)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_887 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:59] + node _T_888 = or(_T_887, reset) @[Periphery.scala 149:59] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_890 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_892 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 149:59] + when _T_892 : @[Periphery.scala 149:59] + node _T_895 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_897 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = and(_T_895, _T_903) @[Parameters.scala 132:56] + node _T_906 = or(UInt<1>("h00"), _T_904) @[Parameters.scala 134:30] + node _T_907 = or(_T_906, reset) @[Periphery.scala 149:59] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_909 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_910 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_912 = eq(_T_910, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_912 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_913 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_915 = eq(_T_913, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_915 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_917 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_918 = or(_T_917, reset) @[Periphery.scala 149:59] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_920 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:149:59)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_921 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:59] + node _T_922 = or(_T_921, reset) @[Periphery.scala 149:59] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_924 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:59] + when _T_926 : @[Periphery.scala 149:59] + node _T_929 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_931 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = and(_T_929, _T_937) @[Parameters.scala 132:56] + node _T_940 = or(UInt<1>("h00"), _T_938) @[Parameters.scala 134:30] + node _T_941 = or(_T_940, reset) @[Periphery.scala 149:59] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_943 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_944 = or(_T_619[0], reset) @[Periphery.scala 149:59] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_946 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_947 = or(_T_630, reset) @[Periphery.scala 149:59] + node _T_949 = eq(_T_947, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_949 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_950 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:59] + node _T_951 = or(_T_950, reset) @[Periphery.scala 149:59] + node _T_953 = eq(_T_951, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_953 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + when io.in[0].b.valid : @[Periphery.scala 149:59] + node _T_955 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_956 = or(_T_955, reset) @[Periphery.scala 149:59] + node _T_958 = eq(_T_956, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_958 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:149:59)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_960 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_961 = cvt(_T_960) @[Parameters.scala 117:49] + node _T_963 = and(_T_961, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_964 = asSInt(_T_963) @[Parameters.scala 117:52] + node _T_966 = eq(_T_964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_969 : UInt<1>[1] @[Parameters.scala 110:36] + _T_969 is invalid @[Parameters.scala 110:36] + _T_969[0] <= _T_966 @[Parameters.scala 110:36] + node _T_974 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_975 = dshl(_T_974, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_976 = bits(_T_975, 5, 0) @[package.scala 19:76] + node _T_977 = not(_T_976) @[package.scala 19:40] + node _T_978 = and(io.in[0].b.bits.address, _T_977) @[Edges.scala 17:16] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_982 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_983 = dshl(UInt<1>("h01"), _T_982) @[OneHot.scala 49:12] + node _T_984 = bits(_T_983, 2, 0) @[OneHot.scala 49:37] + node _T_986 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_988 = bits(_T_984, 2, 2) @[package.scala 44:26] + node _T_989 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_991 = eq(_T_989, UInt<1>("h00")) @[package.scala 46:20] + node _T_992 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_993 = and(_T_988, _T_992) @[package.scala 50:38] + node _T_994 = or(_T_986, _T_993) @[package.scala 50:29] + node _T_995 = and(UInt<1>("h01"), _T_989) @[package.scala 49:27] + node _T_996 = and(_T_988, _T_995) @[package.scala 50:38] + node _T_997 = or(_T_986, _T_996) @[package.scala 50:29] + node _T_998 = bits(_T_984, 1, 1) @[package.scala 44:26] + node _T_999 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1001 = eq(_T_999, UInt<1>("h00")) @[package.scala 46:20] + node _T_1002 = and(_T_992, _T_1001) @[package.scala 49:27] + node _T_1003 = and(_T_998, _T_1002) @[package.scala 50:38] + node _T_1004 = or(_T_994, _T_1003) @[package.scala 50:29] + node _T_1005 = and(_T_992, _T_999) @[package.scala 49:27] + node _T_1006 = and(_T_998, _T_1005) @[package.scala 50:38] + node _T_1007 = or(_T_994, _T_1006) @[package.scala 50:29] + node _T_1008 = and(_T_995, _T_1001) @[package.scala 49:27] + node _T_1009 = and(_T_998, _T_1008) @[package.scala 50:38] + node _T_1010 = or(_T_997, _T_1009) @[package.scala 50:29] + node _T_1011 = and(_T_995, _T_999) @[package.scala 49:27] + node _T_1012 = and(_T_998, _T_1011) @[package.scala 50:38] + node _T_1013 = or(_T_997, _T_1012) @[package.scala 50:29] + node _T_1014 = bits(_T_984, 0, 0) @[package.scala 44:26] + node _T_1015 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1017 = eq(_T_1015, UInt<1>("h00")) @[package.scala 46:20] + node _T_1018 = and(_T_1002, _T_1017) @[package.scala 49:27] + node _T_1019 = and(_T_1014, _T_1018) @[package.scala 50:38] + node _T_1020 = or(_T_1004, _T_1019) @[package.scala 50:29] + node _T_1021 = and(_T_1002, _T_1015) @[package.scala 49:27] + node _T_1022 = and(_T_1014, _T_1021) @[package.scala 50:38] + node _T_1023 = or(_T_1004, _T_1022) @[package.scala 50:29] + node _T_1024 = and(_T_1005, _T_1017) @[package.scala 49:27] + node _T_1025 = and(_T_1014, _T_1024) @[package.scala 50:38] + node _T_1026 = or(_T_1007, _T_1025) @[package.scala 50:29] + node _T_1027 = and(_T_1005, _T_1015) @[package.scala 49:27] + node _T_1028 = and(_T_1014, _T_1027) @[package.scala 50:38] + node _T_1029 = or(_T_1007, _T_1028) @[package.scala 50:29] + node _T_1030 = and(_T_1008, _T_1017) @[package.scala 49:27] + node _T_1031 = and(_T_1014, _T_1030) @[package.scala 50:38] + node _T_1032 = or(_T_1010, _T_1031) @[package.scala 50:29] + node _T_1033 = and(_T_1008, _T_1015) @[package.scala 49:27] + node _T_1034 = and(_T_1014, _T_1033) @[package.scala 50:38] + node _T_1035 = or(_T_1010, _T_1034) @[package.scala 50:29] + node _T_1036 = and(_T_1011, _T_1017) @[package.scala 49:27] + node _T_1037 = and(_T_1014, _T_1036) @[package.scala 50:38] + node _T_1038 = or(_T_1013, _T_1037) @[package.scala 50:29] + node _T_1039 = and(_T_1011, _T_1015) @[package.scala 49:27] + node _T_1040 = and(_T_1014, _T_1039) @[package.scala 50:38] + node _T_1041 = or(_T_1013, _T_1040) @[package.scala 50:29] + node _T_1042 = cat(_T_1023, _T_1020) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1029, _T_1026) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1035, _T_1032) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1041, _T_1038) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1050 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + when _T_1050 : @[Periphery.scala 149:59] + node _T_1052 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1054 = eq(_T_1052, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1054 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1055 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1057 = eq(_T_1055, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1057 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1059 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1060 = or(_T_1059, reset) @[Periphery.scala 149:59] + node _T_1062 = eq(_T_1060, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1062 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1063 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1065 = eq(_T_1063, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1065 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1067 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1068 = or(_T_1067, reset) @[Periphery.scala 149:59] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1070 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:149:59)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1071 = not(io.in[0].b.bits.mask) @[Periphery.scala 149:59] + node _T_1073 = eq(_T_1071, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 149:59] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1076 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1078 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:59] + when _T_1078 : @[Periphery.scala 149:59] + node _T_1080 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1082 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1083 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1085 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1086 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1088 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1090 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1091 = or(_T_1090, reset) @[Periphery.scala 149:59] + node _T_1093 = eq(_T_1091, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1093 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1094 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:59] + node _T_1095 = or(_T_1094, reset) @[Periphery.scala 149:59] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1097 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1099 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1099 : @[Periphery.scala 149:59] + node _T_1101 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1103 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1104 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1106 = eq(_T_1104, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1106 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1107 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1109 = eq(_T_1107, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1109 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1111 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1112 = or(_T_1111, reset) @[Periphery.scala 149:59] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1114 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1115 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:59] + node _T_1116 = or(_T_1115, reset) @[Periphery.scala 149:59] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1118 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1120 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:59] + when _T_1120 : @[Periphery.scala 149:59] + node _T_1122 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1124 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1125 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1127 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1128 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1130 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1132 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1133 = or(_T_1132, reset) @[Periphery.scala 149:59] + node _T_1135 = eq(_T_1133, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1135 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1136 = not(_T_1048) @[Periphery.scala 149:59] + node _T_1137 = and(io.in[0].b.bits.mask, _T_1136) @[Periphery.scala 149:59] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1140 = or(_T_1139, reset) @[Periphery.scala 149:59] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1142 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:59] + when _T_1144 : @[Periphery.scala 149:59] + node _T_1146 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1148 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1149 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1151 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1152 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1154 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1156 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1157 = or(_T_1156, reset) @[Periphery.scala 149:59] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1159 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:149:59)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:59] + node _T_1161 = or(_T_1160, reset) @[Periphery.scala 149:59] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1163 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 149:59] + when _T_1165 : @[Periphery.scala 149:59] + node _T_1167 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1169 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1170 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1172 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1173 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1175 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1177 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1178 = or(_T_1177, reset) @[Periphery.scala 149:59] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1180 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:149:59)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1181 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:59] + node _T_1182 = or(_T_1181, reset) @[Periphery.scala 149:59] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1184 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1186 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:59] + when _T_1186 : @[Periphery.scala 149:59] + node _T_1188 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:59] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1190 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:149:59)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1191 = or(_T_969[0], reset) @[Periphery.scala 149:59] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1193 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1194 = or(_T_980, reset) @[Periphery.scala 149:59] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1196 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1197 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:59] + node _T_1198 = or(_T_1197, reset) @[Periphery.scala 149:59] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1200 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:149:59)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + when io.in[0].c.valid : @[Periphery.scala 149:59] + node _T_1202 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1203 = or(_T_1202, reset) @[Periphery.scala 149:59] + node _T_1205 = eq(_T_1203, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1205 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:149:59)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1207 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1208 = not(_T_1207) @[Parameters.scala 37:9] + node _T_1210 = or(_T_1208, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1211 = not(_T_1210) @[Parameters.scala 37:7] + node _T_1213 = eq(_T_1211, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1216 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1216 is invalid @[Parameters.scala 228:27] + _T_1216[0] <= _T_1213 @[Parameters.scala 228:27] + node _T_1221 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1222 = dshl(_T_1221, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1223 = bits(_T_1222, 5, 0) @[package.scala 19:76] + node _T_1224 = not(_T_1223) @[package.scala 19:40] + node _T_1225 = and(io.in[0].c.bits.address, _T_1224) @[Edges.scala 17:16] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1229 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1230 = cvt(_T_1229) @[Parameters.scala 117:49] + node _T_1232 = and(_T_1230, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1233 = asSInt(_T_1232) @[Parameters.scala 117:52] + node _T_1235 = eq(_T_1233, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1238 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1238 is invalid @[Parameters.scala 110:36] + _T_1238[0] <= _T_1235 @[Parameters.scala 110:36] + node _T_1243 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:59] + when _T_1243 : @[Periphery.scala 149:59] + node _T_1244 = or(_T_1238[0], reset) @[Periphery.scala 149:59] + node _T_1246 = eq(_T_1244, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1246 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1247 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1249 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1251 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1252 = or(_T_1251, reset) @[Periphery.scala 149:59] + node _T_1254 = eq(_T_1252, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1254 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1255 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1257 = eq(_T_1255, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1257 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1259 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1260 = or(_T_1259, reset) @[Periphery.scala 149:59] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1262 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:149:59)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1264 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1265 = or(_T_1264, reset) @[Periphery.scala 149:59] + node _T_1267 = eq(_T_1265, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1267 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1269 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:59] + when _T_1269 : @[Periphery.scala 149:59] + node _T_1270 = or(_T_1238[0], reset) @[Periphery.scala 149:59] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1272 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1273 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1275 = eq(_T_1273, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1275 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1277 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1278 = or(_T_1277, reset) @[Periphery.scala 149:59] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1280 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1281 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1283 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1285 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1286 = or(_T_1285, reset) @[Periphery.scala 149:59] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1288 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:149:59)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1290 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1291 = or(_T_1290, reset) @[Periphery.scala 149:59] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1293 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1295 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + when _T_1295 : @[Periphery.scala 149:59] + node _T_1298 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1300 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1301 = cvt(_T_1300) @[Parameters.scala 117:49] + node _T_1303 = and(_T_1301, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1304 = asSInt(_T_1303) @[Parameters.scala 117:52] + node _T_1306 = eq(_T_1304, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1307 = and(_T_1298, _T_1306) @[Parameters.scala 132:56] + node _T_1309 = or(UInt<1>("h00"), _T_1307) @[Parameters.scala 134:30] + node _T_1310 = or(_T_1309, reset) @[Periphery.scala 149:59] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1312 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1313 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1315 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1317 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1318 = or(_T_1317, reset) @[Periphery.scala 149:59] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1320 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1321 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1323 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1325 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1326 = or(_T_1325, reset) @[Periphery.scala 149:59] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1328 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:149:59)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1330 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 149:59] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1333 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1335 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 149:59] + when _T_1335 : @[Periphery.scala 149:59] + node _T_1338 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1340 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1341 = cvt(_T_1340) @[Parameters.scala 117:49] + node _T_1343 = and(_T_1341, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1344 = asSInt(_T_1343) @[Parameters.scala 117:52] + node _T_1346 = eq(_T_1344, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1347 = and(_T_1338, _T_1346) @[Parameters.scala 132:56] + node _T_1349 = or(UInt<1>("h00"), _T_1347) @[Parameters.scala 134:30] + node _T_1350 = or(_T_1349, reset) @[Periphery.scala 149:59] + node _T_1352 = eq(_T_1350, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1352 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:149:59)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1353 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1355 = eq(_T_1353, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1355 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1357 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 149:59] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1360 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1361 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1363 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1365 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1366 = or(_T_1365, reset) @[Periphery.scala 149:59] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1368 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:149:59)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1370 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1371 = or(_T_1370, reset) @[Periphery.scala 149:59] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1373 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1375 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1375 : @[Periphery.scala 149:59] + node _T_1376 = or(_T_1238[0], reset) @[Periphery.scala 149:59] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1378 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1379 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1381 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1382 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1384 = eq(_T_1382, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1384 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1386 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1387 = or(_T_1386, reset) @[Periphery.scala 149:59] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1389 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1391 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:59] + when _T_1391 : @[Periphery.scala 149:59] + node _T_1392 = or(_T_1238[0], reset) @[Periphery.scala 149:59] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1394 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1395 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1397 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1398 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1400 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1402 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1403 = or(_T_1402, reset) @[Periphery.scala 149:59] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1405 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1407 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:59] + when _T_1407 : @[Periphery.scala 149:59] + node _T_1408 = or(_T_1238[0], reset) @[Periphery.scala 149:59] + node _T_1410 = eq(_T_1408, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1410 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:149:59)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1411 = or(_T_1216[0], reset) @[Periphery.scala 149:59] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1413 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1414 = or(_T_1227, reset) @[Periphery.scala 149:59] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1416 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1418 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1419 = or(_T_1418, reset) @[Periphery.scala 149:59] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1421 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1424 = or(_T_1423, reset) @[Periphery.scala 149:59] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1426 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + when io.in[0].d.valid : @[Periphery.scala 149:59] + node _T_1428 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1429 = or(_T_1428, reset) @[Periphery.scala 149:59] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1431 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:149:59)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1433 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1434 = not(_T_1433) @[Parameters.scala 37:9] + node _T_1436 = or(_T_1434, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1437 = not(_T_1436) @[Parameters.scala 37:7] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1442 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1442 is invalid @[Parameters.scala 228:27] + _T_1442[0] <= _T_1439 @[Parameters.scala 228:27] + node _T_1447 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1448 = dshl(_T_1447, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1449 = bits(_T_1448, 5, 0) @[package.scala 19:76] + node _T_1450 = not(_T_1449) @[package.scala 19:40] + node _T_1451 = and(io.in[0].d.bits.addr_lo, _T_1450) @[Edges.scala 17:16] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1455 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 149:59] + node _T_1457 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + when _T_1457 : @[Periphery.scala 149:59] + node _T_1458 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1460 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1461 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1463 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1464 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1466 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1468 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1469 = or(_T_1468, reset) @[Periphery.scala 149:59] + node _T_1471 = eq(_T_1469, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1471 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1473 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1474 = or(_T_1473, reset) @[Periphery.scala 149:59] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1476 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1478 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1479 = or(_T_1478, reset) @[Periphery.scala 149:59] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1481 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1483 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:59] + when _T_1483 : @[Periphery.scala 149:59] + node _T_1484 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1486 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1487 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1489 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1490 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1492 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1494 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1495 = or(_T_1494, reset) @[Periphery.scala 149:59] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1497 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1499 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1500 = or(_T_1499, reset) @[Periphery.scala 149:59] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1502 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:149:59)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1504 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:59] + when _T_1504 : @[Periphery.scala 149:59] + node _T_1505 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1507 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1508 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1510 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1511 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1513 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1515 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:59] + node _T_1516 = or(_T_1515, reset) @[Periphery.scala 149:59] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1518 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:149:59)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1520 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1521 = or(_T_1520, reset) @[Periphery.scala 149:59] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1523 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:149:59)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1525 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1525 : @[Periphery.scala 149:59] + node _T_1526 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1528 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1529 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1531 = eq(_T_1529, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1531 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1532 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1534 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1536 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1537 = or(_T_1536, reset) @[Periphery.scala 149:59] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1539 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1541 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:59] + when _T_1541 : @[Periphery.scala 149:59] + node _T_1542 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1544 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1545 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1547 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1548 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1550 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1552 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1553 = or(_T_1552, reset) @[Periphery.scala 149:59] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1555 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1557 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:59] + when _T_1557 : @[Periphery.scala 149:59] + node _T_1558 = or(_T_1442[0], reset) @[Periphery.scala 149:59] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1560 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1561 = or(_T_1453, reset) @[Periphery.scala 149:59] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1563 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:149:59)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1564 = or(_T_1455, reset) @[Periphery.scala 149:59] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1566 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1568 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1569 = or(_T_1568, reset) @[Periphery.scala 149:59] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1571 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:149:59)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1573 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1574 = or(_T_1573, reset) @[Periphery.scala 149:59] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1576 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:149:59)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + when io.in[0].e.valid : @[Periphery.scala 149:59] + node _T_1578 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 149:59] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 149:59] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1581 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:149:59)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1582 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1584 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1585 = dshl(_T_1584, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1586 = bits(_T_1585, 5, 0) @[package.scala 19:76] + node _T_1587 = not(_T_1586) @[package.scala 19:40] + node _T_1588 = shr(_T_1587, 3) @[Edges.scala 198:59] + node _T_1589 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1593 = mux(_T_1591, _T_1588, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1595 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1597 = sub(_T_1595, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1598 = asUInt(_T_1597) @[Edges.scala 208:28] + node _T_1599 = tail(_T_1598, 1) @[Edges.scala 208:28] + node _T_1601 = eq(_T_1595, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1603 = eq(_T_1595, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1605 = eq(_T_1593, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1606 = or(_T_1603, _T_1605) @[Edges.scala 210:37] + node _T_1607 = and(_T_1606, _T_1582) @[Edges.scala 211:22] + node _T_1608 = not(_T_1599) @[Edges.scala 212:27] + node _T_1609 = and(_T_1593, _T_1608) @[Edges.scala 212:25] + when _T_1582 : @[Edges.scala 213:17] + node _T_1610 = mux(_T_1601, _T_1593, _T_1599) @[Edges.scala 214:21] + _T_1595 <= _T_1610 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1612 : UInt, clock @[Periphery.scala 149:59] + reg _T_1614 : UInt, clock @[Periphery.scala 149:59] + reg _T_1616 : UInt, clock @[Periphery.scala 149:59] + reg _T_1618 : UInt, clock @[Periphery.scala 149:59] + reg _T_1620 : UInt, clock @[Periphery.scala 149:59] + node _T_1622 = eq(_T_1601, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1623 = and(io.in[0].a.valid, _T_1622) @[Periphery.scala 149:59] + when _T_1623 : @[Periphery.scala 149:59] + node _T_1624 = eq(io.in[0].a.bits.opcode, _T_1612) @[Periphery.scala 149:59] + node _T_1625 = or(_T_1624, reset) @[Periphery.scala 149:59] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1627 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1628 = eq(io.in[0].a.bits.param, _T_1614) @[Periphery.scala 149:59] + node _T_1629 = or(_T_1628, reset) @[Periphery.scala 149:59] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1631 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1632 = eq(io.in[0].a.bits.size, _T_1616) @[Periphery.scala 149:59] + node _T_1633 = or(_T_1632, reset) @[Periphery.scala 149:59] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1635 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1636 = eq(io.in[0].a.bits.source, _T_1618) @[Periphery.scala 149:59] + node _T_1637 = or(_T_1636, reset) @[Periphery.scala 149:59] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1639 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1640 = eq(io.in[0].a.bits.address, _T_1620) @[Periphery.scala 149:59] + node _T_1641 = or(_T_1640, reset) @[Periphery.scala 149:59] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1643 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1644 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = and(_T_1644, _T_1601) @[Periphery.scala 149:59] + when _T_1645 : @[Periphery.scala 149:59] + _T_1612 <= io.in[0].a.bits.opcode @[Periphery.scala 149:59] + _T_1614 <= io.in[0].a.bits.param @[Periphery.scala 149:59] + _T_1616 <= io.in[0].a.bits.size @[Periphery.scala 149:59] + _T_1618 <= io.in[0].a.bits.source @[Periphery.scala 149:59] + _T_1620 <= io.in[0].a.bits.address @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1646 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1648 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1649 = dshl(_T_1648, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1650 = bits(_T_1649, 5, 0) @[package.scala 19:76] + node _T_1651 = not(_T_1650) @[package.scala 19:40] + node _T_1652 = shr(_T_1651, 3) @[Edges.scala 198:59] + node _T_1653 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1658 = mux(UInt<1>("h00"), _T_1652, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1660 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1662 = sub(_T_1660, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1663 = asUInt(_T_1662) @[Edges.scala 208:28] + node _T_1664 = tail(_T_1663, 1) @[Edges.scala 208:28] + node _T_1666 = eq(_T_1660, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1668 = eq(_T_1660, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1670 = eq(_T_1658, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1671 = or(_T_1668, _T_1670) @[Edges.scala 210:37] + node _T_1672 = and(_T_1671, _T_1646) @[Edges.scala 211:22] + node _T_1673 = not(_T_1664) @[Edges.scala 212:27] + node _T_1674 = and(_T_1658, _T_1673) @[Edges.scala 212:25] + when _T_1646 : @[Edges.scala 213:17] + node _T_1675 = mux(_T_1666, _T_1658, _T_1664) @[Edges.scala 214:21] + _T_1660 <= _T_1675 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1677 : UInt, clock @[Periphery.scala 149:59] + reg _T_1679 : UInt, clock @[Periphery.scala 149:59] + reg _T_1681 : UInt, clock @[Periphery.scala 149:59] + reg _T_1683 : UInt, clock @[Periphery.scala 149:59] + reg _T_1685 : UInt, clock @[Periphery.scala 149:59] + node _T_1687 = eq(_T_1666, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1688 = and(io.in[0].b.valid, _T_1687) @[Periphery.scala 149:59] + when _T_1688 : @[Periphery.scala 149:59] + node _T_1689 = eq(io.in[0].b.bits.opcode, _T_1677) @[Periphery.scala 149:59] + node _T_1690 = or(_T_1689, reset) @[Periphery.scala 149:59] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1692 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1693 = eq(io.in[0].b.bits.param, _T_1679) @[Periphery.scala 149:59] + node _T_1694 = or(_T_1693, reset) @[Periphery.scala 149:59] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1696 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1697 = eq(io.in[0].b.bits.size, _T_1681) @[Periphery.scala 149:59] + node _T_1698 = or(_T_1697, reset) @[Periphery.scala 149:59] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1700 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1701 = eq(io.in[0].b.bits.source, _T_1683) @[Periphery.scala 149:59] + node _T_1702 = or(_T_1701, reset) @[Periphery.scala 149:59] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1704 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1705 = eq(io.in[0].b.bits.address, _T_1685) @[Periphery.scala 149:59] + node _T_1706 = or(_T_1705, reset) @[Periphery.scala 149:59] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1708 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1709 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1710 = and(_T_1709, _T_1666) @[Periphery.scala 149:59] + when _T_1710 : @[Periphery.scala 149:59] + _T_1677 <= io.in[0].b.bits.opcode @[Periphery.scala 149:59] + _T_1679 <= io.in[0].b.bits.param @[Periphery.scala 149:59] + _T_1681 <= io.in[0].b.bits.size @[Periphery.scala 149:59] + _T_1683 <= io.in[0].b.bits.source @[Periphery.scala 149:59] + _T_1685 <= io.in[0].b.bits.address @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1711 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1713 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1714 = dshl(_T_1713, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1715 = bits(_T_1714, 5, 0) @[package.scala 19:76] + node _T_1716 = not(_T_1715) @[package.scala 19:40] + node _T_1717 = shr(_T_1716, 3) @[Edges.scala 198:59] + node _T_1718 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1721 = mux(UInt<1>("h00"), _T_1717, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1723 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1725 = sub(_T_1723, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1726 = asUInt(_T_1725) @[Edges.scala 208:28] + node _T_1727 = tail(_T_1726, 1) @[Edges.scala 208:28] + node _T_1729 = eq(_T_1723, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1731 = eq(_T_1723, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1733 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1734 = or(_T_1731, _T_1733) @[Edges.scala 210:37] + node _T_1735 = and(_T_1734, _T_1711) @[Edges.scala 211:22] + node _T_1736 = not(_T_1727) @[Edges.scala 212:27] + node _T_1737 = and(_T_1721, _T_1736) @[Edges.scala 212:25] + when _T_1711 : @[Edges.scala 213:17] + node _T_1738 = mux(_T_1729, _T_1721, _T_1727) @[Edges.scala 214:21] + _T_1723 <= _T_1738 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1740 : UInt, clock @[Periphery.scala 149:59] + reg _T_1742 : UInt, clock @[Periphery.scala 149:59] + reg _T_1744 : UInt, clock @[Periphery.scala 149:59] + reg _T_1746 : UInt, clock @[Periphery.scala 149:59] + reg _T_1748 : UInt, clock @[Periphery.scala 149:59] + node _T_1750 = eq(_T_1729, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1751 = and(io.in[0].c.valid, _T_1750) @[Periphery.scala 149:59] + when _T_1751 : @[Periphery.scala 149:59] + node _T_1752 = eq(io.in[0].c.bits.opcode, _T_1740) @[Periphery.scala 149:59] + node _T_1753 = or(_T_1752, reset) @[Periphery.scala 149:59] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1755 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1756 = eq(io.in[0].c.bits.param, _T_1742) @[Periphery.scala 149:59] + node _T_1757 = or(_T_1756, reset) @[Periphery.scala 149:59] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1759 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1760 = eq(io.in[0].c.bits.size, _T_1744) @[Periphery.scala 149:59] + node _T_1761 = or(_T_1760, reset) @[Periphery.scala 149:59] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1763 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1764 = eq(io.in[0].c.bits.source, _T_1746) @[Periphery.scala 149:59] + node _T_1765 = or(_T_1764, reset) @[Periphery.scala 149:59] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1767 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1768 = eq(io.in[0].c.bits.address, _T_1748) @[Periphery.scala 149:59] + node _T_1769 = or(_T_1768, reset) @[Periphery.scala 149:59] + node _T_1771 = eq(_T_1769, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1771 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1773 = and(_T_1772, _T_1729) @[Periphery.scala 149:59] + when _T_1773 : @[Periphery.scala 149:59] + _T_1740 <= io.in[0].c.bits.opcode @[Periphery.scala 149:59] + _T_1742 <= io.in[0].c.bits.param @[Periphery.scala 149:59] + _T_1744 <= io.in[0].c.bits.size @[Periphery.scala 149:59] + _T_1746 <= io.in[0].c.bits.source @[Periphery.scala 149:59] + _T_1748 <= io.in[0].c.bits.address @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1774 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1776 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1777 = dshl(_T_1776, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1778 = bits(_T_1777, 5, 0) @[package.scala 19:76] + node _T_1779 = not(_T_1778) @[package.scala 19:40] + node _T_1780 = shr(_T_1779, 3) @[Edges.scala 198:59] + node _T_1781 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1783 = mux(_T_1781, _T_1780, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1774) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1774 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[Periphery.scala 149:59] + reg _T_1804 : UInt, clock @[Periphery.scala 149:59] + reg _T_1806 : UInt, clock @[Periphery.scala 149:59] + reg _T_1808 : UInt, clock @[Periphery.scala 149:59] + reg _T_1810 : UInt, clock @[Periphery.scala 149:59] + reg _T_1812 : UInt, clock @[Periphery.scala 149:59] + node _T_1814 = eq(_T_1791, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1815 = and(io.in[0].d.valid, _T_1814) @[Periphery.scala 149:59] + when _T_1815 : @[Periphery.scala 149:59] + node _T_1816 = eq(io.in[0].d.bits.opcode, _T_1802) @[Periphery.scala 149:59] + node _T_1817 = or(_T_1816, reset) @[Periphery.scala 149:59] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1819 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1820 = eq(io.in[0].d.bits.param, _T_1804) @[Periphery.scala 149:59] + node _T_1821 = or(_T_1820, reset) @[Periphery.scala 149:59] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1823 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1824 = eq(io.in[0].d.bits.size, _T_1806) @[Periphery.scala 149:59] + node _T_1825 = or(_T_1824, reset) @[Periphery.scala 149:59] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1827 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1828 = eq(io.in[0].d.bits.source, _T_1808) @[Periphery.scala 149:59] + node _T_1829 = or(_T_1828, reset) @[Periphery.scala 149:59] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1831 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1832 = eq(io.in[0].d.bits.sink, _T_1810) @[Periphery.scala 149:59] + node _T_1833 = or(_T_1832, reset) @[Periphery.scala 149:59] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1835 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1836 = eq(io.in[0].d.bits.addr_lo, _T_1812) @[Periphery.scala 149:59] + node _T_1837 = or(_T_1836, reset) @[Periphery.scala 149:59] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1839 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:149:59)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1840 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1841 = and(_T_1840, _T_1791) @[Periphery.scala 149:59] + when _T_1841 : @[Periphery.scala 149:59] + _T_1802 <= io.in[0].d.bits.opcode @[Periphery.scala 149:59] + _T_1804 <= io.in[0].d.bits.param @[Periphery.scala 149:59] + _T_1806 <= io.in[0].d.bits.size @[Periphery.scala 149:59] + _T_1808 <= io.in[0].d.bits.source @[Periphery.scala 149:59] + _T_1810 <= io.in[0].d.bits.sink @[Periphery.scala 149:59] + _T_1812 <= io.in[0].d.bits.addr_lo @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + reg _T_1843 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_1844 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1846 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1847 = dshl(_T_1846, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1848 = bits(_T_1847, 5, 0) @[package.scala 19:76] + node _T_1849 = not(_T_1848) @[package.scala 19:40] + node _T_1850 = shr(_T_1849, 3) @[Edges.scala 198:59] + node _T_1851 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1853 = eq(_T_1851, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1855 = mux(_T_1853, _T_1850, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1857 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1859 = sub(_T_1857, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1860 = asUInt(_T_1859) @[Edges.scala 208:28] + node _T_1861 = tail(_T_1860, 1) @[Edges.scala 208:28] + node _T_1863 = eq(_T_1857, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1865 = eq(_T_1857, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1867 = eq(_T_1855, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1868 = or(_T_1865, _T_1867) @[Edges.scala 210:37] + node _T_1869 = and(_T_1868, _T_1844) @[Edges.scala 211:22] + node _T_1870 = not(_T_1861) @[Edges.scala 212:27] + node _T_1871 = and(_T_1855, _T_1870) @[Edges.scala 212:25] + when _T_1844 : @[Edges.scala 213:17] + node _T_1872 = mux(_T_1863, _T_1855, _T_1861) @[Edges.scala 214:21] + _T_1857 <= _T_1872 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1873 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1875 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1876 = dshl(_T_1875, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1877 = bits(_T_1876, 5, 0) @[package.scala 19:76] + node _T_1878 = not(_T_1877) @[package.scala 19:40] + node _T_1879 = shr(_T_1878, 3) @[Edges.scala 198:59] + node _T_1880 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1882 = mux(_T_1880, _T_1879, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1884 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1886 = sub(_T_1884, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1887 = asUInt(_T_1886) @[Edges.scala 208:28] + node _T_1888 = tail(_T_1887, 1) @[Edges.scala 208:28] + node _T_1890 = eq(_T_1884, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1892 = eq(_T_1884, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1894 = eq(_T_1882, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1895 = or(_T_1892, _T_1894) @[Edges.scala 210:37] + node _T_1896 = and(_T_1895, _T_1873) @[Edges.scala 211:22] + node _T_1897 = not(_T_1888) @[Edges.scala 212:27] + node _T_1898 = and(_T_1882, _T_1897) @[Edges.scala 212:25] + when _T_1873 : @[Edges.scala 213:17] + node _T_1899 = mux(_T_1890, _T_1882, _T_1888) @[Edges.scala 214:21] + _T_1884 <= _T_1899 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1901 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + node _T_1902 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 149:59] + node _T_1903 = or(_T_1901, _T_1902) @[Periphery.scala 149:59] + node _T_1905 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1906 = or(_T_1903, _T_1905) @[Periphery.scala 149:59] + node _T_1908 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1909 = or(_T_1906, _T_1908) @[Periphery.scala 149:59] + node _T_1910 = or(_T_1909, reset) @[Periphery.scala 149:59] + node _T_1912 = eq(_T_1910, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1912 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Periphery.scala:149:59)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + wire _T_1914 : UInt<32> + _T_1914 is invalid + _T_1914 <= UInt<32>("h00") + node _T_1915 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1915 : @[Periphery.scala 149:59] + when _T_1868 : @[Periphery.scala 149:59] + node _T_1917 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1914 <= _T_1917 @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1918 = dshr(_T_1843, io.in[0].a.bits.source) @[Periphery.scala 149:59] + node _T_1919 = bits(_T_1918, 0, 0) @[Periphery.scala 149:59] + node _T_1921 = eq(_T_1919, UInt<1>("h00")) @[Periphery.scala 149:59] + node _T_1922 = or(_T_1921, reset) @[Periphery.scala 149:59] + node _T_1924 = eq(_T_1922, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1924 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:149:59)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + wire _T_1926 : UInt<32> + _T_1926 is invalid + _T_1926 <= UInt<32>("h00") + node _T_1927 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1929 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:59] + node _T_1930 = and(_T_1927, _T_1929) @[Periphery.scala 149:59] + when _T_1930 : @[Periphery.scala 149:59] + when _T_1895 : @[Periphery.scala 149:59] + node _T_1932 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1926 <= _T_1932 @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1933 = or(_T_1914, _T_1843) @[Periphery.scala 149:59] + node _T_1934 = dshr(_T_1933, io.in[0].d.bits.source) @[Periphery.scala 149:59] + node _T_1935 = bits(_T_1934, 0, 0) @[Periphery.scala 149:59] + node _T_1936 = or(_T_1935, reset) @[Periphery.scala 149:59] + node _T_1938 = eq(_T_1936, UInt<1>("h00")) @[Periphery.scala 149:59] + when _T_1938 : @[Periphery.scala 149:59] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:149:59)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 149:59] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + skip @[Periphery.scala 149:59] + node _T_1939 = or(_T_1843, _T_1914) @[Periphery.scala 149:59] + node _T_1940 = not(_T_1926) @[Periphery.scala 149:59] + node _T_1941 = and(_T_1939, _T_1940) @[Periphery.scala 149:59] + _T_1843 <= _T_1941 @[Periphery.scala 149:59] + + module TLMonitor_13 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Periphery.scala 149:15] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Periphery.scala 149:15] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_608 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:149:15)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<8>("h0ff")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 2, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + when _T_700 : @[Periphery.scala 149:15] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_712 = and(_T_703, _T_711) @[Parameters.scala 132:56] + node _T_714 = or(UInt<1>("h00"), _T_712) @[Parameters.scala 134:30] + node _T_715 = or(_T_714, reset) @[Periphery.scala 149:15] + node _T_717 = eq(_T_715, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_717 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_718 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_720 = eq(_T_718, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_720 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_722 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_723 = or(_T_722, reset) @[Periphery.scala 149:15] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_725 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_726 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_728 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_730 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_731 = or(_T_730, reset) @[Periphery.scala 149:15] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_733 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Periphery.scala:149:15)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_734 = not(io.in[0].a.bits.mask) @[Periphery.scala 149:15] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_737 = or(_T_736, reset) @[Periphery.scala 149:15] + node _T_739 = eq(_T_737, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_739 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_741 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:15] + when _T_741 : @[Periphery.scala 149:15] + node _T_744 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_746 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_747 = and(_T_744, _T_746) @[Parameters.scala 63:37] + node _T_748 = or(UInt<1>("h00"), _T_747) @[Parameters.scala 132:31] + node _T_750 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_751 = cvt(_T_750) @[Parameters.scala 117:49] + node _T_753 = and(_T_751, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_754 = asSInt(_T_753) @[Parameters.scala 117:52] + node _T_756 = eq(_T_754, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_757 = and(_T_748, _T_756) @[Parameters.scala 132:56] + node _T_759 = or(UInt<1>("h00"), _T_757) @[Parameters.scala 134:30] + node _T_760 = or(_T_759, reset) @[Periphery.scala 149:15] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_762 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_763 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_765 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_766 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_768 = eq(_T_766, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_768 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_770 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_771 = or(_T_770, reset) @[Periphery.scala 149:15] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_773 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_774 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:15] + node _T_775 = or(_T_774, reset) @[Periphery.scala 149:15] + node _T_777 = eq(_T_775, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_777 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_779 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_779 : @[Periphery.scala 149:15] + node _T_782 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_784 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_785 = and(_T_782, _T_784) @[Parameters.scala 63:37] + node _T_786 = or(UInt<1>("h00"), _T_785) @[Parameters.scala 132:31] + node _T_788 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_789 = cvt(_T_788) @[Parameters.scala 117:49] + node _T_791 = and(_T_789, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_792 = asSInt(_T_791) @[Parameters.scala 117:52] + node _T_794 = eq(_T_792, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_795 = and(_T_786, _T_794) @[Parameters.scala 132:56] + node _T_797 = or(UInt<1>("h00"), _T_795) @[Parameters.scala 134:30] + node _T_798 = or(_T_797, reset) @[Periphery.scala 149:15] + node _T_800 = eq(_T_798, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_800 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_801 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_803 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_804 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_806 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_808 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_809 = or(_T_808, reset) @[Periphery.scala 149:15] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_811 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_812 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:15] + node _T_813 = or(_T_812, reset) @[Periphery.scala 149:15] + node _T_815 = eq(_T_813, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_815 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_817 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:15] + when _T_817 : @[Periphery.scala 149:15] + node _T_820 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_822 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_823 = and(_T_820, _T_822) @[Parameters.scala 63:37] + node _T_824 = or(UInt<1>("h00"), _T_823) @[Parameters.scala 132:31] + node _T_826 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = and(_T_824, _T_832) @[Parameters.scala 132:56] + node _T_835 = or(UInt<1>("h00"), _T_833) @[Parameters.scala 134:30] + node _T_836 = or(_T_835, reset) @[Periphery.scala 149:15] + node _T_838 = eq(_T_836, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_838 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_839 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_841 = eq(_T_839, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_841 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_842 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_844 = eq(_T_842, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_844 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_846 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_847 = or(_T_846, reset) @[Periphery.scala 149:15] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_849 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_850 = not(_T_698) @[Periphery.scala 149:15] + node _T_851 = and(io.in[0].a.bits.mask, _T_850) @[Periphery.scala 149:15] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_854 = or(_T_853, reset) @[Periphery.scala 149:15] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_856 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_858 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:15] + when _T_858 : @[Periphery.scala 149:15] + node _T_861 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_863 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_864 = cvt(_T_863) @[Parameters.scala 117:49] + node _T_866 = and(_T_864, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_867 = asSInt(_T_866) @[Parameters.scala 117:52] + node _T_869 = eq(_T_867, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_870 = and(_T_861, _T_869) @[Parameters.scala 132:56] + node _T_872 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 134:30] + node _T_873 = or(_T_872, reset) @[Periphery.scala 149:15] + node _T_875 = eq(_T_873, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_875 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_876 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_878 = eq(_T_876, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_878 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_879 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_881 = eq(_T_879, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_881 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_883 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_884 = or(_T_883, reset) @[Periphery.scala 149:15] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_886 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:149:15)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_887 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:15] + node _T_888 = or(_T_887, reset) @[Periphery.scala 149:15] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_890 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_892 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Periphery.scala 149:15] + when _T_892 : @[Periphery.scala 149:15] + node _T_895 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_897 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = and(_T_895, _T_903) @[Parameters.scala 132:56] + node _T_906 = or(UInt<1>("h00"), _T_904) @[Parameters.scala 134:30] + node _T_907 = or(_T_906, reset) @[Periphery.scala 149:15] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_909 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_910 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_912 = eq(_T_910, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_912 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_913 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_915 = eq(_T_913, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_915 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_917 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_918 = or(_T_917, reset) @[Periphery.scala 149:15] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_920 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:149:15)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_921 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:15] + node _T_922 = or(_T_921, reset) @[Periphery.scala 149:15] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_924 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:15] + when _T_926 : @[Periphery.scala 149:15] + node _T_929 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_931 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = and(_T_929, _T_937) @[Parameters.scala 132:56] + node _T_940 = or(UInt<1>("h00"), _T_938) @[Parameters.scala 134:30] + node _T_941 = or(_T_940, reset) @[Periphery.scala 149:15] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_943 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_944 = or(_T_619[0], reset) @[Periphery.scala 149:15] + node _T_946 = eq(_T_944, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_946 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_947 = or(_T_630, reset) @[Periphery.scala 149:15] + node _T_949 = eq(_T_947, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_949 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_950 = eq(io.in[0].a.bits.mask, _T_698) @[Periphery.scala 149:15] + node _T_951 = or(_T_950, reset) @[Periphery.scala 149:15] + node _T_953 = eq(_T_951, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_953 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + when io.in[0].b.valid : @[Periphery.scala 149:15] + node _T_955 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_956 = or(_T_955, reset) @[Periphery.scala 149:15] + node _T_958 = eq(_T_956, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_958 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Periphery.scala:149:15)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_960 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_961 = cvt(_T_960) @[Parameters.scala 117:49] + node _T_963 = and(_T_961, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_964 = asSInt(_T_963) @[Parameters.scala 117:52] + node _T_966 = eq(_T_964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_969 : UInt<1>[1] @[Parameters.scala 110:36] + _T_969 is invalid @[Parameters.scala 110:36] + _T_969[0] <= _T_966 @[Parameters.scala 110:36] + node _T_974 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_975 = dshl(_T_974, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_976 = bits(_T_975, 2, 0) @[package.scala 19:76] + node _T_977 = not(_T_976) @[package.scala 19:40] + node _T_978 = and(io.in[0].b.bits.address, _T_977) @[Edges.scala 17:16] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_982 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_983 = dshl(UInt<1>("h01"), _T_982) @[OneHot.scala 49:12] + node _T_984 = bits(_T_983, 2, 0) @[OneHot.scala 49:37] + node _T_986 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_988 = bits(_T_984, 2, 2) @[package.scala 44:26] + node _T_989 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_991 = eq(_T_989, UInt<1>("h00")) @[package.scala 46:20] + node _T_992 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_993 = and(_T_988, _T_992) @[package.scala 50:38] + node _T_994 = or(_T_986, _T_993) @[package.scala 50:29] + node _T_995 = and(UInt<1>("h01"), _T_989) @[package.scala 49:27] + node _T_996 = and(_T_988, _T_995) @[package.scala 50:38] + node _T_997 = or(_T_986, _T_996) @[package.scala 50:29] + node _T_998 = bits(_T_984, 1, 1) @[package.scala 44:26] + node _T_999 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1001 = eq(_T_999, UInt<1>("h00")) @[package.scala 46:20] + node _T_1002 = and(_T_992, _T_1001) @[package.scala 49:27] + node _T_1003 = and(_T_998, _T_1002) @[package.scala 50:38] + node _T_1004 = or(_T_994, _T_1003) @[package.scala 50:29] + node _T_1005 = and(_T_992, _T_999) @[package.scala 49:27] + node _T_1006 = and(_T_998, _T_1005) @[package.scala 50:38] + node _T_1007 = or(_T_994, _T_1006) @[package.scala 50:29] + node _T_1008 = and(_T_995, _T_1001) @[package.scala 49:27] + node _T_1009 = and(_T_998, _T_1008) @[package.scala 50:38] + node _T_1010 = or(_T_997, _T_1009) @[package.scala 50:29] + node _T_1011 = and(_T_995, _T_999) @[package.scala 49:27] + node _T_1012 = and(_T_998, _T_1011) @[package.scala 50:38] + node _T_1013 = or(_T_997, _T_1012) @[package.scala 50:29] + node _T_1014 = bits(_T_984, 0, 0) @[package.scala 44:26] + node _T_1015 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1017 = eq(_T_1015, UInt<1>("h00")) @[package.scala 46:20] + node _T_1018 = and(_T_1002, _T_1017) @[package.scala 49:27] + node _T_1019 = and(_T_1014, _T_1018) @[package.scala 50:38] + node _T_1020 = or(_T_1004, _T_1019) @[package.scala 50:29] + node _T_1021 = and(_T_1002, _T_1015) @[package.scala 49:27] + node _T_1022 = and(_T_1014, _T_1021) @[package.scala 50:38] + node _T_1023 = or(_T_1004, _T_1022) @[package.scala 50:29] + node _T_1024 = and(_T_1005, _T_1017) @[package.scala 49:27] + node _T_1025 = and(_T_1014, _T_1024) @[package.scala 50:38] + node _T_1026 = or(_T_1007, _T_1025) @[package.scala 50:29] + node _T_1027 = and(_T_1005, _T_1015) @[package.scala 49:27] + node _T_1028 = and(_T_1014, _T_1027) @[package.scala 50:38] + node _T_1029 = or(_T_1007, _T_1028) @[package.scala 50:29] + node _T_1030 = and(_T_1008, _T_1017) @[package.scala 49:27] + node _T_1031 = and(_T_1014, _T_1030) @[package.scala 50:38] + node _T_1032 = or(_T_1010, _T_1031) @[package.scala 50:29] + node _T_1033 = and(_T_1008, _T_1015) @[package.scala 49:27] + node _T_1034 = and(_T_1014, _T_1033) @[package.scala 50:38] + node _T_1035 = or(_T_1010, _T_1034) @[package.scala 50:29] + node _T_1036 = and(_T_1011, _T_1017) @[package.scala 49:27] + node _T_1037 = and(_T_1014, _T_1036) @[package.scala 50:38] + node _T_1038 = or(_T_1013, _T_1037) @[package.scala 50:29] + node _T_1039 = and(_T_1011, _T_1015) @[package.scala 49:27] + node _T_1040 = and(_T_1014, _T_1039) @[package.scala 50:38] + node _T_1041 = or(_T_1013, _T_1040) @[package.scala 50:29] + node _T_1042 = cat(_T_1023, _T_1020) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1029, _T_1026) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1035, _T_1032) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1041, _T_1038) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1050 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + when _T_1050 : @[Periphery.scala 149:15] + node _T_1052 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1054 = eq(_T_1052, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1054 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1055 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1057 = eq(_T_1055, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1057 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1059 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1060 = or(_T_1059, reset) @[Periphery.scala 149:15] + node _T_1062 = eq(_T_1060, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1062 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1063 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1065 = eq(_T_1063, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1065 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1067 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1068 = or(_T_1067, reset) @[Periphery.scala 149:15] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1070 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Periphery.scala:149:15)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1071 = not(io.in[0].b.bits.mask) @[Periphery.scala 149:15] + node _T_1073 = eq(_T_1071, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1074 = or(_T_1073, reset) @[Periphery.scala 149:15] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1076 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1078 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:15] + when _T_1078 : @[Periphery.scala 149:15] + node _T_1080 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1082 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1083 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1085 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1086 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1088 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1090 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1091 = or(_T_1090, reset) @[Periphery.scala 149:15] + node _T_1093 = eq(_T_1091, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1093 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1094 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:15] + node _T_1095 = or(_T_1094, reset) @[Periphery.scala 149:15] + node _T_1097 = eq(_T_1095, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1097 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1099 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1099 : @[Periphery.scala 149:15] + node _T_1101 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1103 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1104 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1106 = eq(_T_1104, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1106 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1107 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1109 = eq(_T_1107, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1109 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1111 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1112 = or(_T_1111, reset) @[Periphery.scala 149:15] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1114 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1115 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:15] + node _T_1116 = or(_T_1115, reset) @[Periphery.scala 149:15] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1118 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1120 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:15] + when _T_1120 : @[Periphery.scala 149:15] + node _T_1122 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1124 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1125 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1127 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1128 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1130 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1132 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1133 = or(_T_1132, reset) @[Periphery.scala 149:15] + node _T_1135 = eq(_T_1133, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1135 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1136 = not(_T_1048) @[Periphery.scala 149:15] + node _T_1137 = and(io.in[0].b.bits.mask, _T_1136) @[Periphery.scala 149:15] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1140 = or(_T_1139, reset) @[Periphery.scala 149:15] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1142 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:15] + when _T_1144 : @[Periphery.scala 149:15] + node _T_1146 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1148 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1149 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1151 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1152 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1154 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1156 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1157 = or(_T_1156, reset) @[Periphery.scala 149:15] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1159 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:149:15)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:15] + node _T_1161 = or(_T_1160, reset) @[Periphery.scala 149:15] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1163 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Periphery.scala 149:15] + when _T_1165 : @[Periphery.scala 149:15] + node _T_1167 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1169 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1170 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1172 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1173 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1175 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1177 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1178 = or(_T_1177, reset) @[Periphery.scala 149:15] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1180 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Periphery.scala:149:15)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1181 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:15] + node _T_1182 = or(_T_1181, reset) @[Periphery.scala 149:15] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1184 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1186 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:15] + when _T_1186 : @[Periphery.scala 149:15] + node _T_1188 = or(UInt<1>("h00"), reset) @[Periphery.scala 149:15] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1190 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Periphery.scala:149:15)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1191 = or(_T_969[0], reset) @[Periphery.scala 149:15] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1193 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1194 = or(_T_980, reset) @[Periphery.scala 149:15] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1196 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1197 = eq(io.in[0].b.bits.mask, _T_1048) @[Periphery.scala 149:15] + node _T_1198 = or(_T_1197, reset) @[Periphery.scala 149:15] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1200 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Periphery.scala:149:15)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + when io.in[0].c.valid : @[Periphery.scala 149:15] + node _T_1202 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1203 = or(_T_1202, reset) @[Periphery.scala 149:15] + node _T_1205 = eq(_T_1203, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1205 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Periphery.scala:149:15)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1207 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1208 = not(_T_1207) @[Parameters.scala 37:9] + node _T_1210 = or(_T_1208, UInt<8>("h0ff")) @[Parameters.scala 37:28] + node _T_1211 = not(_T_1210) @[Parameters.scala 37:7] + node _T_1213 = eq(_T_1211, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1216 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1216 is invalid @[Parameters.scala 228:27] + _T_1216[0] <= _T_1213 @[Parameters.scala 228:27] + node _T_1221 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1222 = dshl(_T_1221, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1223 = bits(_T_1222, 2, 0) @[package.scala 19:76] + node _T_1224 = not(_T_1223) @[package.scala 19:40] + node _T_1225 = and(io.in[0].c.bits.address, _T_1224) @[Edges.scala 17:16] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1229 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1230 = cvt(_T_1229) @[Parameters.scala 117:49] + node _T_1232 = and(_T_1230, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1233 = asSInt(_T_1232) @[Parameters.scala 117:52] + node _T_1235 = eq(_T_1233, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1238 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1238 is invalid @[Parameters.scala 110:36] + _T_1238[0] <= _T_1235 @[Parameters.scala 110:36] + node _T_1243 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:15] + when _T_1243 : @[Periphery.scala 149:15] + node _T_1244 = or(_T_1238[0], reset) @[Periphery.scala 149:15] + node _T_1246 = eq(_T_1244, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1246 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1247 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1249 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1251 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1252 = or(_T_1251, reset) @[Periphery.scala 149:15] + node _T_1254 = eq(_T_1252, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1254 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1255 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1257 = eq(_T_1255, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1257 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1259 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1260 = or(_T_1259, reset) @[Periphery.scala 149:15] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1262 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Periphery.scala:149:15)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1264 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1265 = or(_T_1264, reset) @[Periphery.scala 149:15] + node _T_1267 = eq(_T_1265, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1267 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1269 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:15] + when _T_1269 : @[Periphery.scala 149:15] + node _T_1270 = or(_T_1238[0], reset) @[Periphery.scala 149:15] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1272 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1273 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1275 = eq(_T_1273, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1275 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1277 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1278 = or(_T_1277, reset) @[Periphery.scala 149:15] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1280 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1281 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1283 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1285 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1286 = or(_T_1285, reset) @[Periphery.scala 149:15] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1288 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Periphery.scala:149:15)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1290 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1291 = or(_T_1290, reset) @[Periphery.scala 149:15] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1293 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1295 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + when _T_1295 : @[Periphery.scala 149:15] + node _T_1298 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1300 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1301 = cvt(_T_1300) @[Parameters.scala 117:49] + node _T_1303 = and(_T_1301, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1304 = asSInt(_T_1303) @[Parameters.scala 117:52] + node _T_1306 = eq(_T_1304, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1307 = and(_T_1298, _T_1306) @[Parameters.scala 132:56] + node _T_1309 = or(UInt<1>("h00"), _T_1307) @[Parameters.scala 134:30] + node _T_1310 = or(_T_1309, reset) @[Periphery.scala 149:15] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1312 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1313 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1315 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1317 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1318 = or(_T_1317, reset) @[Periphery.scala 149:15] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1320 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1321 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1323 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1325 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1326 = or(_T_1325, reset) @[Periphery.scala 149:15] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1328 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Periphery.scala:149:15)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1330 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1331 = or(_T_1330, reset) @[Periphery.scala 149:15] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1333 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1335 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Periphery.scala 149:15] + when _T_1335 : @[Periphery.scala 149:15] + node _T_1338 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1340 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1341 = cvt(_T_1340) @[Parameters.scala 117:49] + node _T_1343 = and(_T_1341, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1344 = asSInt(_T_1343) @[Parameters.scala 117:52] + node _T_1346 = eq(_T_1344, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1347 = and(_T_1338, _T_1346) @[Parameters.scala 132:56] + node _T_1349 = or(UInt<1>("h00"), _T_1347) @[Parameters.scala 134:30] + node _T_1350 = or(_T_1349, reset) @[Periphery.scala 149:15] + node _T_1352 = eq(_T_1350, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1352 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Periphery.scala:149:15)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1353 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1355 = eq(_T_1353, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1355 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1357 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1358 = or(_T_1357, reset) @[Periphery.scala 149:15] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1360 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1361 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1363 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1365 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1366 = or(_T_1365, reset) @[Periphery.scala 149:15] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1368 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Periphery.scala:149:15)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1370 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1371 = or(_T_1370, reset) @[Periphery.scala 149:15] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1373 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1375 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1375 : @[Periphery.scala 149:15] + node _T_1376 = or(_T_1238[0], reset) @[Periphery.scala 149:15] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1378 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1379 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1381 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1382 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1384 = eq(_T_1382, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1384 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1386 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1387 = or(_T_1386, reset) @[Periphery.scala 149:15] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1389 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1391 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:15] + when _T_1391 : @[Periphery.scala 149:15] + node _T_1392 = or(_T_1238[0], reset) @[Periphery.scala 149:15] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1394 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1395 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1397 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1398 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1400 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1402 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1403 = or(_T_1402, reset) @[Periphery.scala 149:15] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1405 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1407 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:15] + when _T_1407 : @[Periphery.scala 149:15] + node _T_1408 = or(_T_1238[0], reset) @[Periphery.scala 149:15] + node _T_1410 = eq(_T_1408, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1410 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Periphery.scala:149:15)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1411 = or(_T_1216[0], reset) @[Periphery.scala 149:15] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1413 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1414 = or(_T_1227, reset) @[Periphery.scala 149:15] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1416 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1418 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1419 = or(_T_1418, reset) @[Periphery.scala 149:15] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1421 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1424 = or(_T_1423, reset) @[Periphery.scala 149:15] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1426 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + when io.in[0].d.valid : @[Periphery.scala 149:15] + node _T_1428 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1429 = or(_T_1428, reset) @[Periphery.scala 149:15] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1431 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:149:15)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1433 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1434 = not(_T_1433) @[Parameters.scala 37:9] + node _T_1436 = or(_T_1434, UInt<8>("h0ff")) @[Parameters.scala 37:28] + node _T_1437 = not(_T_1436) @[Parameters.scala 37:7] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1442 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1442 is invalid @[Parameters.scala 228:27] + _T_1442[0] <= _T_1439 @[Parameters.scala 228:27] + node _T_1447 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1448 = dshl(_T_1447, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1449 = bits(_T_1448, 2, 0) @[package.scala 19:76] + node _T_1450 = not(_T_1449) @[package.scala 19:40] + node _T_1451 = and(io.in[0].d.bits.addr_lo, _T_1450) @[Edges.scala 17:16] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1455 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[Periphery.scala 149:15] + node _T_1457 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + when _T_1457 : @[Periphery.scala 149:15] + node _T_1458 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1460 = eq(_T_1458, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1460 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1461 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1463 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1464 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1466 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1468 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1469 = or(_T_1468, reset) @[Periphery.scala 149:15] + node _T_1471 = eq(_T_1469, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1471 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1473 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1474 = or(_T_1473, reset) @[Periphery.scala 149:15] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1476 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1478 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1479 = or(_T_1478, reset) @[Periphery.scala 149:15] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1481 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1483 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Periphery.scala 149:15] + when _T_1483 : @[Periphery.scala 149:15] + node _T_1484 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1486 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1487 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1489 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1490 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1492 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1494 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1495 = or(_T_1494, reset) @[Periphery.scala 149:15] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1497 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1499 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1500 = or(_T_1499, reset) @[Periphery.scala 149:15] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1502 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:149:15)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1504 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Periphery.scala 149:15] + when _T_1504 : @[Periphery.scala 149:15] + node _T_1505 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1507 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1508 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1510 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1511 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1513 = eq(_T_1511, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1513 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1515 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Periphery.scala 149:15] + node _T_1516 = or(_T_1515, reset) @[Periphery.scala 149:15] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1518 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:149:15)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1520 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1521 = or(_T_1520, reset) @[Periphery.scala 149:15] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1523 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:149:15)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1525 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1525 : @[Periphery.scala 149:15] + node _T_1526 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1528 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1529 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1531 = eq(_T_1529, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1531 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1532 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1534 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1536 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1537 = or(_T_1536, reset) @[Periphery.scala 149:15] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1539 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1541 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Periphery.scala 149:15] + when _T_1541 : @[Periphery.scala 149:15] + node _T_1542 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1544 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1545 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1547 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1548 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1550 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1552 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1553 = or(_T_1552, reset) @[Periphery.scala 149:15] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1555 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1557 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Periphery.scala 149:15] + when _T_1557 : @[Periphery.scala 149:15] + node _T_1558 = or(_T_1442[0], reset) @[Periphery.scala 149:15] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1560 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1561 = or(_T_1453, reset) @[Periphery.scala 149:15] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1563 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Periphery.scala:149:15)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1564 = or(_T_1455, reset) @[Periphery.scala 149:15] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1566 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1568 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1569 = or(_T_1568, reset) @[Periphery.scala 149:15] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1571 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:149:15)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1573 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1574 = or(_T_1573, reset) @[Periphery.scala 149:15] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1576 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Periphery.scala:149:15)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + when io.in[0].e.valid : @[Periphery.scala 149:15] + node _T_1578 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[Periphery.scala 149:15] + node _T_1579 = or(_T_1578, reset) @[Periphery.scala 149:15] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1581 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Periphery.scala:149:15)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1582 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1584 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1585 = dshl(_T_1584, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1586 = bits(_T_1585, 2, 0) @[package.scala 19:76] + node _T_1587 = not(_T_1586) @[package.scala 19:40] + node _T_1588 = shr(_T_1587, 3) @[Edges.scala 198:59] + node _T_1589 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1593 = mux(_T_1591, _T_1588, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1595 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1597 = sub(_T_1595, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1598 = asUInt(_T_1597) @[Edges.scala 208:28] + node _T_1599 = tail(_T_1598, 1) @[Edges.scala 208:28] + node _T_1601 = eq(_T_1595, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1603 = eq(_T_1595, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1605 = eq(_T_1593, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1606 = or(_T_1603, _T_1605) @[Edges.scala 210:37] + node _T_1607 = and(_T_1606, _T_1582) @[Edges.scala 211:22] + node _T_1608 = not(_T_1599) @[Edges.scala 212:27] + node _T_1609 = and(_T_1593, _T_1608) @[Edges.scala 212:25] + when _T_1582 : @[Edges.scala 213:17] + node _T_1610 = mux(_T_1601, _T_1593, _T_1599) @[Edges.scala 214:21] + _T_1595 <= _T_1610 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1612 : UInt, clock @[Periphery.scala 149:15] + reg _T_1614 : UInt, clock @[Periphery.scala 149:15] + reg _T_1616 : UInt, clock @[Periphery.scala 149:15] + reg _T_1618 : UInt, clock @[Periphery.scala 149:15] + reg _T_1620 : UInt, clock @[Periphery.scala 149:15] + node _T_1622 = eq(_T_1601, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1623 = and(io.in[0].a.valid, _T_1622) @[Periphery.scala 149:15] + when _T_1623 : @[Periphery.scala 149:15] + node _T_1624 = eq(io.in[0].a.bits.opcode, _T_1612) @[Periphery.scala 149:15] + node _T_1625 = or(_T_1624, reset) @[Periphery.scala 149:15] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1627 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1628 = eq(io.in[0].a.bits.param, _T_1614) @[Periphery.scala 149:15] + node _T_1629 = or(_T_1628, reset) @[Periphery.scala 149:15] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1631 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1632 = eq(io.in[0].a.bits.size, _T_1616) @[Periphery.scala 149:15] + node _T_1633 = or(_T_1632, reset) @[Periphery.scala 149:15] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1635 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1636 = eq(io.in[0].a.bits.source, _T_1618) @[Periphery.scala 149:15] + node _T_1637 = or(_T_1636, reset) @[Periphery.scala 149:15] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1639 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1640 = eq(io.in[0].a.bits.address, _T_1620) @[Periphery.scala 149:15] + node _T_1641 = or(_T_1640, reset) @[Periphery.scala 149:15] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1643 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1644 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = and(_T_1644, _T_1601) @[Periphery.scala 149:15] + when _T_1645 : @[Periphery.scala 149:15] + _T_1612 <= io.in[0].a.bits.opcode @[Periphery.scala 149:15] + _T_1614 <= io.in[0].a.bits.param @[Periphery.scala 149:15] + _T_1616 <= io.in[0].a.bits.size @[Periphery.scala 149:15] + _T_1618 <= io.in[0].a.bits.source @[Periphery.scala 149:15] + _T_1620 <= io.in[0].a.bits.address @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1646 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1648 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1649 = dshl(_T_1648, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1650 = bits(_T_1649, 2, 0) @[package.scala 19:76] + node _T_1651 = not(_T_1650) @[package.scala 19:40] + node _T_1652 = shr(_T_1651, 3) @[Edges.scala 198:59] + node _T_1653 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1658 = mux(UInt<1>("h00"), _T_1652, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1660 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1662 = sub(_T_1660, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1663 = asUInt(_T_1662) @[Edges.scala 208:28] + node _T_1664 = tail(_T_1663, 1) @[Edges.scala 208:28] + node _T_1666 = eq(_T_1660, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1668 = eq(_T_1660, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1670 = eq(_T_1658, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1671 = or(_T_1668, _T_1670) @[Edges.scala 210:37] + node _T_1672 = and(_T_1671, _T_1646) @[Edges.scala 211:22] + node _T_1673 = not(_T_1664) @[Edges.scala 212:27] + node _T_1674 = and(_T_1658, _T_1673) @[Edges.scala 212:25] + when _T_1646 : @[Edges.scala 213:17] + node _T_1675 = mux(_T_1666, _T_1658, _T_1664) @[Edges.scala 214:21] + _T_1660 <= _T_1675 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1677 : UInt, clock @[Periphery.scala 149:15] + reg _T_1679 : UInt, clock @[Periphery.scala 149:15] + reg _T_1681 : UInt, clock @[Periphery.scala 149:15] + reg _T_1683 : UInt, clock @[Periphery.scala 149:15] + reg _T_1685 : UInt, clock @[Periphery.scala 149:15] + node _T_1687 = eq(_T_1666, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1688 = and(io.in[0].b.valid, _T_1687) @[Periphery.scala 149:15] + when _T_1688 : @[Periphery.scala 149:15] + node _T_1689 = eq(io.in[0].b.bits.opcode, _T_1677) @[Periphery.scala 149:15] + node _T_1690 = or(_T_1689, reset) @[Periphery.scala 149:15] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1692 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1693 = eq(io.in[0].b.bits.param, _T_1679) @[Periphery.scala 149:15] + node _T_1694 = or(_T_1693, reset) @[Periphery.scala 149:15] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1696 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1697 = eq(io.in[0].b.bits.size, _T_1681) @[Periphery.scala 149:15] + node _T_1698 = or(_T_1697, reset) @[Periphery.scala 149:15] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1700 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1701 = eq(io.in[0].b.bits.source, _T_1683) @[Periphery.scala 149:15] + node _T_1702 = or(_T_1701, reset) @[Periphery.scala 149:15] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1704 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1705 = eq(io.in[0].b.bits.address, _T_1685) @[Periphery.scala 149:15] + node _T_1706 = or(_T_1705, reset) @[Periphery.scala 149:15] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1708 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1709 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1710 = and(_T_1709, _T_1666) @[Periphery.scala 149:15] + when _T_1710 : @[Periphery.scala 149:15] + _T_1677 <= io.in[0].b.bits.opcode @[Periphery.scala 149:15] + _T_1679 <= io.in[0].b.bits.param @[Periphery.scala 149:15] + _T_1681 <= io.in[0].b.bits.size @[Periphery.scala 149:15] + _T_1683 <= io.in[0].b.bits.source @[Periphery.scala 149:15] + _T_1685 <= io.in[0].b.bits.address @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1711 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1713 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1714 = dshl(_T_1713, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1715 = bits(_T_1714, 2, 0) @[package.scala 19:76] + node _T_1716 = not(_T_1715) @[package.scala 19:40] + node _T_1717 = shr(_T_1716, 3) @[Edges.scala 198:59] + node _T_1718 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1721 = mux(UInt<1>("h00"), _T_1717, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1723 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1725 = sub(_T_1723, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1726 = asUInt(_T_1725) @[Edges.scala 208:28] + node _T_1727 = tail(_T_1726, 1) @[Edges.scala 208:28] + node _T_1729 = eq(_T_1723, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1731 = eq(_T_1723, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1733 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1734 = or(_T_1731, _T_1733) @[Edges.scala 210:37] + node _T_1735 = and(_T_1734, _T_1711) @[Edges.scala 211:22] + node _T_1736 = not(_T_1727) @[Edges.scala 212:27] + node _T_1737 = and(_T_1721, _T_1736) @[Edges.scala 212:25] + when _T_1711 : @[Edges.scala 213:17] + node _T_1738 = mux(_T_1729, _T_1721, _T_1727) @[Edges.scala 214:21] + _T_1723 <= _T_1738 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1740 : UInt, clock @[Periphery.scala 149:15] + reg _T_1742 : UInt, clock @[Periphery.scala 149:15] + reg _T_1744 : UInt, clock @[Periphery.scala 149:15] + reg _T_1746 : UInt, clock @[Periphery.scala 149:15] + reg _T_1748 : UInt, clock @[Periphery.scala 149:15] + node _T_1750 = eq(_T_1729, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1751 = and(io.in[0].c.valid, _T_1750) @[Periphery.scala 149:15] + when _T_1751 : @[Periphery.scala 149:15] + node _T_1752 = eq(io.in[0].c.bits.opcode, _T_1740) @[Periphery.scala 149:15] + node _T_1753 = or(_T_1752, reset) @[Periphery.scala 149:15] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1755 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1756 = eq(io.in[0].c.bits.param, _T_1742) @[Periphery.scala 149:15] + node _T_1757 = or(_T_1756, reset) @[Periphery.scala 149:15] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1759 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1760 = eq(io.in[0].c.bits.size, _T_1744) @[Periphery.scala 149:15] + node _T_1761 = or(_T_1760, reset) @[Periphery.scala 149:15] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1763 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1764 = eq(io.in[0].c.bits.source, _T_1746) @[Periphery.scala 149:15] + node _T_1765 = or(_T_1764, reset) @[Periphery.scala 149:15] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1767 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1768 = eq(io.in[0].c.bits.address, _T_1748) @[Periphery.scala 149:15] + node _T_1769 = or(_T_1768, reset) @[Periphery.scala 149:15] + node _T_1771 = eq(_T_1769, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1771 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1773 = and(_T_1772, _T_1729) @[Periphery.scala 149:15] + when _T_1773 : @[Periphery.scala 149:15] + _T_1740 <= io.in[0].c.bits.opcode @[Periphery.scala 149:15] + _T_1742 <= io.in[0].c.bits.param @[Periphery.scala 149:15] + _T_1744 <= io.in[0].c.bits.size @[Periphery.scala 149:15] + _T_1746 <= io.in[0].c.bits.source @[Periphery.scala 149:15] + _T_1748 <= io.in[0].c.bits.address @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1774 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1776 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1777 = dshl(_T_1776, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1778 = bits(_T_1777, 2, 0) @[package.scala 19:76] + node _T_1779 = not(_T_1778) @[package.scala 19:40] + node _T_1780 = shr(_T_1779, 3) @[Edges.scala 198:59] + node _T_1781 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1783 = mux(_T_1781, _T_1780, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1774) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1774 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[Periphery.scala 149:15] + reg _T_1804 : UInt, clock @[Periphery.scala 149:15] + reg _T_1806 : UInt, clock @[Periphery.scala 149:15] + reg _T_1808 : UInt, clock @[Periphery.scala 149:15] + reg _T_1810 : UInt, clock @[Periphery.scala 149:15] + reg _T_1812 : UInt, clock @[Periphery.scala 149:15] + node _T_1814 = eq(_T_1791, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1815 = and(io.in[0].d.valid, _T_1814) @[Periphery.scala 149:15] + when _T_1815 : @[Periphery.scala 149:15] + node _T_1816 = eq(io.in[0].d.bits.opcode, _T_1802) @[Periphery.scala 149:15] + node _T_1817 = or(_T_1816, reset) @[Periphery.scala 149:15] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1819 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1820 = eq(io.in[0].d.bits.param, _T_1804) @[Periphery.scala 149:15] + node _T_1821 = or(_T_1820, reset) @[Periphery.scala 149:15] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1823 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1824 = eq(io.in[0].d.bits.size, _T_1806) @[Periphery.scala 149:15] + node _T_1825 = or(_T_1824, reset) @[Periphery.scala 149:15] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1827 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1828 = eq(io.in[0].d.bits.source, _T_1808) @[Periphery.scala 149:15] + node _T_1829 = or(_T_1828, reset) @[Periphery.scala 149:15] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1831 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1832 = eq(io.in[0].d.bits.sink, _T_1810) @[Periphery.scala 149:15] + node _T_1833 = or(_T_1832, reset) @[Periphery.scala 149:15] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1835 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1836 = eq(io.in[0].d.bits.addr_lo, _T_1812) @[Periphery.scala 149:15] + node _T_1837 = or(_T_1836, reset) @[Periphery.scala 149:15] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1839 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Periphery.scala:149:15)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1840 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1841 = and(_T_1840, _T_1791) @[Periphery.scala 149:15] + when _T_1841 : @[Periphery.scala 149:15] + _T_1802 <= io.in[0].d.bits.opcode @[Periphery.scala 149:15] + _T_1804 <= io.in[0].d.bits.param @[Periphery.scala 149:15] + _T_1806 <= io.in[0].d.bits.size @[Periphery.scala 149:15] + _T_1808 <= io.in[0].d.bits.source @[Periphery.scala 149:15] + _T_1810 <= io.in[0].d.bits.sink @[Periphery.scala 149:15] + _T_1812 <= io.in[0].d.bits.addr_lo @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + reg _T_1843 : UInt<256>, clock with : (reset => (reset, UInt<256>("h00"))) @[Reg.scala 26:44] + node _T_1844 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1846 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1847 = dshl(_T_1846, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1848 = bits(_T_1847, 2, 0) @[package.scala 19:76] + node _T_1849 = not(_T_1848) @[package.scala 19:40] + node _T_1850 = shr(_T_1849, 3) @[Edges.scala 198:59] + node _T_1851 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1853 = eq(_T_1851, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1855 = mux(_T_1853, _T_1850, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1857 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1859 = sub(_T_1857, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1860 = asUInt(_T_1859) @[Edges.scala 208:28] + node _T_1861 = tail(_T_1860, 1) @[Edges.scala 208:28] + node _T_1863 = eq(_T_1857, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1865 = eq(_T_1857, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1867 = eq(_T_1855, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1868 = or(_T_1865, _T_1867) @[Edges.scala 210:37] + node _T_1869 = and(_T_1868, _T_1844) @[Edges.scala 211:22] + node _T_1870 = not(_T_1861) @[Edges.scala 212:27] + node _T_1871 = and(_T_1855, _T_1870) @[Edges.scala 212:25] + when _T_1844 : @[Edges.scala 213:17] + node _T_1872 = mux(_T_1863, _T_1855, _T_1861) @[Edges.scala 214:21] + _T_1857 <= _T_1872 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1873 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1875 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_1876 = dshl(_T_1875, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1877 = bits(_T_1876, 2, 0) @[package.scala 19:76] + node _T_1878 = not(_T_1877) @[package.scala 19:40] + node _T_1879 = shr(_T_1878, 3) @[Edges.scala 198:59] + node _T_1880 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1882 = mux(_T_1880, _T_1879, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1884 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1886 = sub(_T_1884, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1887 = asUInt(_T_1886) @[Edges.scala 208:28] + node _T_1888 = tail(_T_1887, 1) @[Edges.scala 208:28] + node _T_1890 = eq(_T_1884, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1892 = eq(_T_1884, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1894 = eq(_T_1882, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1895 = or(_T_1892, _T_1894) @[Edges.scala 210:37] + node _T_1896 = and(_T_1895, _T_1873) @[Edges.scala 211:22] + node _T_1897 = not(_T_1888) @[Edges.scala 212:27] + node _T_1898 = and(_T_1882, _T_1897) @[Edges.scala 212:25] + when _T_1873 : @[Edges.scala 213:17] + node _T_1899 = mux(_T_1890, _T_1882, _T_1888) @[Edges.scala 214:21] + _T_1884 <= _T_1899 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1901 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + node _T_1902 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Periphery.scala 149:15] + node _T_1903 = or(_T_1901, _T_1902) @[Periphery.scala 149:15] + node _T_1905 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1906 = or(_T_1903, _T_1905) @[Periphery.scala 149:15] + node _T_1908 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1909 = or(_T_1906, _T_1908) @[Periphery.scala 149:15] + node _T_1910 = or(_T_1909, reset) @[Periphery.scala 149:15] + node _T_1912 = eq(_T_1910, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1912 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Periphery.scala:149:15)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + wire _T_1914 : UInt<256> + _T_1914 is invalid + _T_1914 <= UInt<256>("h00") + node _T_1915 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1915 : @[Periphery.scala 149:15] + when _T_1868 : @[Periphery.scala 149:15] + node _T_1917 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1914 <= _T_1917 @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1918 = dshr(_T_1843, io.in[0].a.bits.source) @[Periphery.scala 149:15] + node _T_1919 = bits(_T_1918, 0, 0) @[Periphery.scala 149:15] + node _T_1921 = eq(_T_1919, UInt<1>("h00")) @[Periphery.scala 149:15] + node _T_1922 = or(_T_1921, reset) @[Periphery.scala 149:15] + node _T_1924 = eq(_T_1922, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1924 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:149:15)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + wire _T_1926 : UInt<256> + _T_1926 is invalid + _T_1926 <= UInt<256>("h00") + node _T_1927 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1929 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Periphery.scala 149:15] + node _T_1930 = and(_T_1927, _T_1929) @[Periphery.scala 149:15] + when _T_1930 : @[Periphery.scala 149:15] + when _T_1895 : @[Periphery.scala 149:15] + node _T_1932 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1926 <= _T_1932 @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1933 = or(_T_1914, _T_1843) @[Periphery.scala 149:15] + node _T_1934 = dshr(_T_1933, io.in[0].d.bits.source) @[Periphery.scala 149:15] + node _T_1935 = bits(_T_1934, 0, 0) @[Periphery.scala 149:15] + node _T_1936 = or(_T_1935, reset) @[Periphery.scala 149:15] + node _T_1938 = eq(_T_1936, UInt<1>("h00")) @[Periphery.scala 149:15] + when _T_1938 : @[Periphery.scala 149:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:149:15)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Periphery.scala 149:15] + stop(clock, UInt<1>(1), 1) @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + skip @[Periphery.scala 149:15] + node _T_1939 = or(_T_1843, _T_1914) @[Periphery.scala 149:15] + node _T_1940 = not(_T_1926) @[Periphery.scala 149:15] + node _T_1941 = and(_T_1939, _T_1940) @[Periphery.scala 149:15] + _T_1843 <= _T_1941 @[Periphery.scala 149:15] + + module TLXbar_l1tol2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {2 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}, 1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, out : {2 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}, 1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}} + + io is invalid + io is invalid + wire in : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[3] @[Xbar.scala 103:18] + in is invalid @[Xbar.scala 103:18] + in[0] <- io.in.0 @[Xbar.scala 106:13] + node _T_3845 = or(io.in.0.a.bits.source, UInt<1>("h00")) @[Xbar.scala 108:53] + in[0].a.bits.source <= _T_3845 @[Xbar.scala 108:27] + node _T_3847 = or(io.in.0.c.bits.source, UInt<1>("h00")) @[Xbar.scala 109:53] + in[0].c.bits.source <= _T_3847 @[Xbar.scala 109:27] + node _T_3848 = bits(in[0].b.bits.source, 1, 0) @[Xbar.scala 100:67] + io.in.0.b.bits.source <= _T_3848 @[Xbar.scala 111:30] + node _T_3849 = bits(in[0].d.bits.source, 1, 0) @[Xbar.scala 100:67] + io.in.0.d.bits.source <= _T_3849 @[Xbar.scala 112:30] + in[1] <- io.in.1 @[Xbar.scala 106:13] + node _T_3851 = or(io.in.1.a.bits.source, UInt<3>("h05")) @[Xbar.scala 108:53] + in[1].a.bits.source <= _T_3851 @[Xbar.scala 108:27] + node _T_3853 = or(io.in.1.c.bits.source, UInt<3>("h05")) @[Xbar.scala 109:53] + in[1].c.bits.source <= _T_3853 @[Xbar.scala 109:27] + io.in.1.b.bits.source <= UInt<1>("h00") @[Xbar.scala 111:30] + io.in.1.d.bits.source <= UInt<1>("h00") @[Xbar.scala 112:30] + in[2] <- io.in.2 @[Xbar.scala 106:13] + node _T_3857 = or(io.in.2.a.bits.source, UInt<3>("h04")) @[Xbar.scala 108:53] + in[2].a.bits.source <= _T_3857 @[Xbar.scala 108:27] + node _T_3859 = or(io.in.2.c.bits.source, UInt<3>("h04")) @[Xbar.scala 109:53] + in[2].c.bits.source <= _T_3859 @[Xbar.scala 109:27] + io.in.2.b.bits.source <= UInt<1>("h00") @[Xbar.scala 111:30] + io.in.2.d.bits.source <= UInt<1>("h00") @[Xbar.scala 112:30] + wire out : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[3] @[Xbar.scala 116:19] + out is invalid @[Xbar.scala 116:19] + io.out.0 <- out[0] @[Xbar.scala 119:17] + node _T_6133 = or(io.out.0.d.bits.sink, UInt<3>("h04")) @[Xbar.scala 121:51] + out[0].d.bits.sink <= _T_6133 @[Xbar.scala 121:26] + node _T_6134 = bits(out[0].e.bits.sink, 1, 0) @[Xbar.scala 100:67] + io.out.0.e.bits.sink <= _T_6134 @[Xbar.scala 123:29] + io.out.1 <- out[1] @[Xbar.scala 119:17] + node _T_6136 = or(io.out.1.d.bits.sink, UInt<4>("h08")) @[Xbar.scala 121:51] + out[1].d.bits.sink <= _T_6136 @[Xbar.scala 121:26] + node _T_6137 = bits(out[1].e.bits.sink, 0, 0) @[Xbar.scala 100:67] + io.out.1.e.bits.sink <= _T_6137 @[Xbar.scala 123:29] + io.out.2 <- out[2] @[Xbar.scala 119:17] + node _T_6139 = or(io.out.2.d.bits.sink, UInt<1>("h00")) @[Xbar.scala 121:51] + out[2].d.bits.sink <= _T_6139 @[Xbar.scala 121:26] + node _T_6140 = bits(out[2].e.bits.sink, 1, 0) @[Xbar.scala 100:67] + io.out.2.e.bits.sink <= _T_6140 @[Xbar.scala 123:29] + node _T_6142 = xor(in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6143 = cvt(_T_6142) @[Parameters.scala 117:49] + node _T_6145 = and(_T_6143, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6146 = asSInt(_T_6145) @[Parameters.scala 117:52] + node _T_6148 = eq(_T_6146, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6150 = xor(in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6151 = cvt(_T_6150) @[Parameters.scala 117:49] + node _T_6153 = and(_T_6151, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6154 = asSInt(_T_6153) @[Parameters.scala 117:52] + node _T_6156 = eq(_T_6154, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6158 = xor(in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6159 = cvt(_T_6158) @[Parameters.scala 117:49] + node _T_6161 = and(_T_6159, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6162 = asSInt(_T_6161) @[Parameters.scala 117:52] + node _T_6164 = eq(_T_6162, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6165 = or(_T_6148, _T_6156) @[Xbar.scala 83:97] + node _T_6166 = or(_T_6165, _T_6164) @[Xbar.scala 83:97] + node _T_6168 = xor(in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6169 = cvt(_T_6168) @[Parameters.scala 117:49] + node _T_6171 = and(_T_6169, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6172 = asSInt(_T_6171) @[Parameters.scala 117:52] + node _T_6174 = eq(_T_6172, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6176 = xor(in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6177 = cvt(_T_6176) @[Parameters.scala 117:49] + node _T_6179 = and(_T_6177, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6180 = asSInt(_T_6179) @[Parameters.scala 117:52] + node _T_6182 = eq(_T_6180, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6183 = or(_T_6174, _T_6182) @[Xbar.scala 83:97] + node _T_6185 = xor(in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6186 = cvt(_T_6185) @[Parameters.scala 117:49] + node _T_6188 = and(_T_6186, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6189 = asSInt(_T_6188) @[Parameters.scala 117:52] + node _T_6191 = eq(_T_6189, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6193 = xor(in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6194 = cvt(_T_6193) @[Parameters.scala 117:49] + node _T_6196 = and(_T_6194, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6197 = asSInt(_T_6196) @[Parameters.scala 117:52] + node _T_6199 = eq(_T_6197, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6200 = or(_T_6191, _T_6199) @[Xbar.scala 83:97] + wire _T_6203 : UInt<1>[3] @[Xbar.scala 129:49] + _T_6203 is invalid @[Xbar.scala 129:49] + _T_6203[0] <= _T_6166 @[Xbar.scala 129:49] + _T_6203[1] <= _T_6183 @[Xbar.scala 129:49] + _T_6203[2] <= _T_6200 @[Xbar.scala 129:49] + node _T_6210 = xor(in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6211 = cvt(_T_6210) @[Parameters.scala 117:49] + node _T_6213 = and(_T_6211, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6214 = asSInt(_T_6213) @[Parameters.scala 117:52] + node _T_6216 = eq(_T_6214, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6218 = xor(in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6219 = cvt(_T_6218) @[Parameters.scala 117:49] + node _T_6221 = and(_T_6219, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6222 = asSInt(_T_6221) @[Parameters.scala 117:52] + node _T_6224 = eq(_T_6222, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6226 = xor(in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6227 = cvt(_T_6226) @[Parameters.scala 117:49] + node _T_6229 = and(_T_6227, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6230 = asSInt(_T_6229) @[Parameters.scala 117:52] + node _T_6232 = eq(_T_6230, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6233 = or(_T_6216, _T_6224) @[Xbar.scala 83:97] + node _T_6234 = or(_T_6233, _T_6232) @[Xbar.scala 83:97] + node _T_6236 = xor(in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6237 = cvt(_T_6236) @[Parameters.scala 117:49] + node _T_6239 = and(_T_6237, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6240 = asSInt(_T_6239) @[Parameters.scala 117:52] + node _T_6242 = eq(_T_6240, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6244 = xor(in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6245 = cvt(_T_6244) @[Parameters.scala 117:49] + node _T_6247 = and(_T_6245, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6248 = asSInt(_T_6247) @[Parameters.scala 117:52] + node _T_6250 = eq(_T_6248, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6251 = or(_T_6242, _T_6250) @[Xbar.scala 83:97] + node _T_6253 = xor(in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6254 = cvt(_T_6253) @[Parameters.scala 117:49] + node _T_6256 = and(_T_6254, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6257 = asSInt(_T_6256) @[Parameters.scala 117:52] + node _T_6259 = eq(_T_6257, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6261 = xor(in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6262 = cvt(_T_6261) @[Parameters.scala 117:49] + node _T_6264 = and(_T_6262, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6265 = asSInt(_T_6264) @[Parameters.scala 117:52] + node _T_6267 = eq(_T_6265, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6268 = or(_T_6259, _T_6267) @[Xbar.scala 83:97] + wire _T_6271 : UInt<1>[3] @[Xbar.scala 129:49] + _T_6271 is invalid @[Xbar.scala 129:49] + _T_6271[0] <= _T_6234 @[Xbar.scala 129:49] + _T_6271[1] <= _T_6251 @[Xbar.scala 129:49] + _T_6271[2] <= _T_6268 @[Xbar.scala 129:49] + node _T_6278 = xor(in[2].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6279 = cvt(_T_6278) @[Parameters.scala 117:49] + node _T_6281 = and(_T_6279, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6282 = asSInt(_T_6281) @[Parameters.scala 117:52] + node _T_6284 = eq(_T_6282, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6286 = xor(in[2].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6287 = cvt(_T_6286) @[Parameters.scala 117:49] + node _T_6289 = and(_T_6287, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6290 = asSInt(_T_6289) @[Parameters.scala 117:52] + node _T_6292 = eq(_T_6290, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6294 = xor(in[2].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6295 = cvt(_T_6294) @[Parameters.scala 117:49] + node _T_6297 = and(_T_6295, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6298 = asSInt(_T_6297) @[Parameters.scala 117:52] + node _T_6300 = eq(_T_6298, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6301 = or(_T_6284, _T_6292) @[Xbar.scala 83:97] + node _T_6302 = or(_T_6301, _T_6300) @[Xbar.scala 83:97] + node _T_6304 = xor(in[2].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6305 = cvt(_T_6304) @[Parameters.scala 117:49] + node _T_6307 = and(_T_6305, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6308 = asSInt(_T_6307) @[Parameters.scala 117:52] + node _T_6310 = eq(_T_6308, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6312 = xor(in[2].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6313 = cvt(_T_6312) @[Parameters.scala 117:49] + node _T_6315 = and(_T_6313, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6316 = asSInt(_T_6315) @[Parameters.scala 117:52] + node _T_6318 = eq(_T_6316, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6319 = or(_T_6310, _T_6318) @[Xbar.scala 83:97] + node _T_6321 = xor(in[2].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6322 = cvt(_T_6321) @[Parameters.scala 117:49] + node _T_6324 = and(_T_6322, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6325 = asSInt(_T_6324) @[Parameters.scala 117:52] + node _T_6327 = eq(_T_6325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6329 = xor(in[2].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6330 = cvt(_T_6329) @[Parameters.scala 117:49] + node _T_6332 = and(_T_6330, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6333 = asSInt(_T_6332) @[Parameters.scala 117:52] + node _T_6335 = eq(_T_6333, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6336 = or(_T_6327, _T_6335) @[Xbar.scala 83:97] + wire _T_6339 : UInt<1>[3] @[Xbar.scala 129:49] + _T_6339 is invalid @[Xbar.scala 129:49] + _T_6339[0] <= _T_6302 @[Xbar.scala 129:49] + _T_6339[1] <= _T_6319 @[Xbar.scala 129:49] + _T_6339[2] <= _T_6336 @[Xbar.scala 129:49] + wire requestAIO : UInt<1>[3][3] @[Xbar.scala 129:25] + requestAIO is invalid @[Xbar.scala 129:25] + requestAIO[0] <- _T_6203 @[Xbar.scala 129:25] + requestAIO[1] <- _T_6271 @[Xbar.scala 129:25] + requestAIO[2] <- _T_6339 @[Xbar.scala 129:25] + node _T_6477 = xor(in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6478 = cvt(_T_6477) @[Parameters.scala 117:49] + node _T_6480 = and(_T_6478, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6481 = asSInt(_T_6480) @[Parameters.scala 117:52] + node _T_6483 = eq(_T_6481, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6485 = xor(in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6486 = cvt(_T_6485) @[Parameters.scala 117:49] + node _T_6488 = and(_T_6486, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6489 = asSInt(_T_6488) @[Parameters.scala 117:52] + node _T_6491 = eq(_T_6489, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6493 = xor(in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6494 = cvt(_T_6493) @[Parameters.scala 117:49] + node _T_6496 = and(_T_6494, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6497 = asSInt(_T_6496) @[Parameters.scala 117:52] + node _T_6499 = eq(_T_6497, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6500 = or(_T_6483, _T_6491) @[Xbar.scala 83:97] + node _T_6501 = or(_T_6500, _T_6499) @[Xbar.scala 83:97] + node _T_6503 = xor(in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6504 = cvt(_T_6503) @[Parameters.scala 117:49] + node _T_6506 = and(_T_6504, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6507 = asSInt(_T_6506) @[Parameters.scala 117:52] + node _T_6509 = eq(_T_6507, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6511 = xor(in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6512 = cvt(_T_6511) @[Parameters.scala 117:49] + node _T_6514 = and(_T_6512, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6515 = asSInt(_T_6514) @[Parameters.scala 117:52] + node _T_6517 = eq(_T_6515, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6518 = or(_T_6509, _T_6517) @[Xbar.scala 83:97] + node _T_6520 = xor(in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6521 = cvt(_T_6520) @[Parameters.scala 117:49] + node _T_6523 = and(_T_6521, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6524 = asSInt(_T_6523) @[Parameters.scala 117:52] + node _T_6526 = eq(_T_6524, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6528 = xor(in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6529 = cvt(_T_6528) @[Parameters.scala 117:49] + node _T_6531 = and(_T_6529, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6532 = asSInt(_T_6531) @[Parameters.scala 117:52] + node _T_6534 = eq(_T_6532, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6535 = or(_T_6526, _T_6534) @[Xbar.scala 83:97] + wire _T_6538 : UInt<1>[3] @[Xbar.scala 130:49] + _T_6538 is invalid @[Xbar.scala 130:49] + _T_6538[0] <= _T_6501 @[Xbar.scala 130:49] + _T_6538[1] <= _T_6518 @[Xbar.scala 130:49] + _T_6538[2] <= _T_6535 @[Xbar.scala 130:49] + node _T_6545 = xor(in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6546 = cvt(_T_6545) @[Parameters.scala 117:49] + node _T_6548 = and(_T_6546, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6549 = asSInt(_T_6548) @[Parameters.scala 117:52] + node _T_6551 = eq(_T_6549, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6553 = xor(in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6554 = cvt(_T_6553) @[Parameters.scala 117:49] + node _T_6556 = and(_T_6554, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6557 = asSInt(_T_6556) @[Parameters.scala 117:52] + node _T_6559 = eq(_T_6557, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6561 = xor(in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6562 = cvt(_T_6561) @[Parameters.scala 117:49] + node _T_6564 = and(_T_6562, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6565 = asSInt(_T_6564) @[Parameters.scala 117:52] + node _T_6567 = eq(_T_6565, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6568 = or(_T_6551, _T_6559) @[Xbar.scala 83:97] + node _T_6569 = or(_T_6568, _T_6567) @[Xbar.scala 83:97] + node _T_6571 = xor(in[1].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6572 = cvt(_T_6571) @[Parameters.scala 117:49] + node _T_6574 = and(_T_6572, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6575 = asSInt(_T_6574) @[Parameters.scala 117:52] + node _T_6577 = eq(_T_6575, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6579 = xor(in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6580 = cvt(_T_6579) @[Parameters.scala 117:49] + node _T_6582 = and(_T_6580, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6583 = asSInt(_T_6582) @[Parameters.scala 117:52] + node _T_6585 = eq(_T_6583, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6586 = or(_T_6577, _T_6585) @[Xbar.scala 83:97] + node _T_6588 = xor(in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6589 = cvt(_T_6588) @[Parameters.scala 117:49] + node _T_6591 = and(_T_6589, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6592 = asSInt(_T_6591) @[Parameters.scala 117:52] + node _T_6594 = eq(_T_6592, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6596 = xor(in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6597 = cvt(_T_6596) @[Parameters.scala 117:49] + node _T_6599 = and(_T_6597, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6600 = asSInt(_T_6599) @[Parameters.scala 117:52] + node _T_6602 = eq(_T_6600, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6603 = or(_T_6594, _T_6602) @[Xbar.scala 83:97] + wire _T_6606 : UInt<1>[3] @[Xbar.scala 130:49] + _T_6606 is invalid @[Xbar.scala 130:49] + _T_6606[0] <= _T_6569 @[Xbar.scala 130:49] + _T_6606[1] <= _T_6586 @[Xbar.scala 130:49] + _T_6606[2] <= _T_6603 @[Xbar.scala 130:49] + node _T_6613 = xor(in[2].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_6614 = cvt(_T_6613) @[Parameters.scala 117:49] + node _T_6616 = and(_T_6614, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_6617 = asSInt(_T_6616) @[Parameters.scala 117:52] + node _T_6619 = eq(_T_6617, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6621 = xor(in[2].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_6622 = cvt(_T_6621) @[Parameters.scala 117:49] + node _T_6624 = and(_T_6622, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_6625 = asSInt(_T_6624) @[Parameters.scala 117:52] + node _T_6627 = eq(_T_6625, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6629 = xor(in[2].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_6630 = cvt(_T_6629) @[Parameters.scala 117:49] + node _T_6632 = and(_T_6630, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6633 = asSInt(_T_6632) @[Parameters.scala 117:52] + node _T_6635 = eq(_T_6633, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6636 = or(_T_6619, _T_6627) @[Xbar.scala 83:97] + node _T_6637 = or(_T_6636, _T_6635) @[Xbar.scala 83:97] + node _T_6639 = xor(in[2].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_6640 = cvt(_T_6639) @[Parameters.scala 117:49] + node _T_6642 = and(_T_6640, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_6643 = asSInt(_T_6642) @[Parameters.scala 117:52] + node _T_6645 = eq(_T_6643, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6647 = xor(in[2].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_6648 = cvt(_T_6647) @[Parameters.scala 117:49] + node _T_6650 = and(_T_6648, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_6651 = asSInt(_T_6650) @[Parameters.scala 117:52] + node _T_6653 = eq(_T_6651, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6654 = or(_T_6645, _T_6653) @[Xbar.scala 83:97] + node _T_6656 = xor(in[2].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_6657 = cvt(_T_6656) @[Parameters.scala 117:49] + node _T_6659 = and(_T_6657, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_6660 = asSInt(_T_6659) @[Parameters.scala 117:52] + node _T_6662 = eq(_T_6660, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6664 = xor(in[2].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_6665 = cvt(_T_6664) @[Parameters.scala 117:49] + node _T_6667 = and(_T_6665, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_6668 = asSInt(_T_6667) @[Parameters.scala 117:52] + node _T_6670 = eq(_T_6668, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_6671 = or(_T_6662, _T_6670) @[Xbar.scala 83:97] + wire _T_6674 : UInt<1>[3] @[Xbar.scala 130:49] + _T_6674 is invalid @[Xbar.scala 130:49] + _T_6674[0] <= _T_6637 @[Xbar.scala 130:49] + _T_6674[1] <= _T_6654 @[Xbar.scala 130:49] + _T_6674[2] <= _T_6671 @[Xbar.scala 130:49] + wire requestCIO : UInt<1>[3][3] @[Xbar.scala 130:25] + requestCIO is invalid @[Xbar.scala 130:25] + requestCIO[0] <- _T_6538 @[Xbar.scala 130:25] + requestCIO[1] <- _T_6606 @[Xbar.scala 130:25] + requestCIO[2] <- _T_6674 @[Xbar.scala 130:25] + node _T_6812 = xor(UInt<1>("h00"), out[0].b.bits.source) @[Parameters.scala 37:23] + node _T_6813 = not(_T_6812) @[Parameters.scala 37:9] + node _T_6815 = or(_T_6813, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_6816 = not(_T_6815) @[Parameters.scala 37:7] + node _T_6818 = eq(_T_6816, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_6820 = eq(UInt<3>("h05"), out[0].b.bits.source) @[Parameters.scala 35:39] + node _T_6822 = eq(UInt<3>("h04"), out[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_6825 : UInt<1>[3] @[Xbar.scala 131:44] + _T_6825 is invalid @[Xbar.scala 131:44] + _T_6825[0] <= _T_6818 @[Xbar.scala 131:44] + _T_6825[1] <= _T_6820 @[Xbar.scala 131:44] + _T_6825[2] <= _T_6822 @[Xbar.scala 131:44] + node _T_6832 = xor(UInt<1>("h00"), out[1].b.bits.source) @[Parameters.scala 37:23] + node _T_6833 = not(_T_6832) @[Parameters.scala 37:9] + node _T_6835 = or(_T_6833, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_6836 = not(_T_6835) @[Parameters.scala 37:7] + node _T_6838 = eq(_T_6836, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_6840 = eq(UInt<3>("h05"), out[1].b.bits.source) @[Parameters.scala 35:39] + node _T_6842 = eq(UInt<3>("h04"), out[1].b.bits.source) @[Parameters.scala 35:39] + wire _T_6845 : UInt<1>[3] @[Xbar.scala 131:44] + _T_6845 is invalid @[Xbar.scala 131:44] + _T_6845[0] <= _T_6838 @[Xbar.scala 131:44] + _T_6845[1] <= _T_6840 @[Xbar.scala 131:44] + _T_6845[2] <= _T_6842 @[Xbar.scala 131:44] + node _T_6852 = xor(UInt<1>("h00"), out[2].b.bits.source) @[Parameters.scala 37:23] + node _T_6853 = not(_T_6852) @[Parameters.scala 37:9] + node _T_6855 = or(_T_6853, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_6856 = not(_T_6855) @[Parameters.scala 37:7] + node _T_6858 = eq(_T_6856, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_6860 = eq(UInt<3>("h05"), out[2].b.bits.source) @[Parameters.scala 35:39] + node _T_6862 = eq(UInt<3>("h04"), out[2].b.bits.source) @[Parameters.scala 35:39] + wire _T_6865 : UInt<1>[3] @[Xbar.scala 131:44] + _T_6865 is invalid @[Xbar.scala 131:44] + _T_6865[0] <= _T_6858 @[Xbar.scala 131:44] + _T_6865[1] <= _T_6860 @[Xbar.scala 131:44] + _T_6865[2] <= _T_6862 @[Xbar.scala 131:44] + wire requestBOI : UInt<1>[3][3] @[Xbar.scala 131:25] + requestBOI is invalid @[Xbar.scala 131:25] + requestBOI[0] <- _T_6825 @[Xbar.scala 131:25] + requestBOI[1] <- _T_6845 @[Xbar.scala 131:25] + requestBOI[2] <- _T_6865 @[Xbar.scala 131:25] + node _T_7003 = xor(UInt<1>("h00"), out[0].d.bits.source) @[Parameters.scala 37:23] + node _T_7004 = not(_T_7003) @[Parameters.scala 37:9] + node _T_7006 = or(_T_7004, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7007 = not(_T_7006) @[Parameters.scala 37:7] + node _T_7009 = eq(_T_7007, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7011 = eq(UInt<3>("h05"), out[0].d.bits.source) @[Parameters.scala 35:39] + node _T_7013 = eq(UInt<3>("h04"), out[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_7016 : UInt<1>[3] @[Xbar.scala 132:44] + _T_7016 is invalid @[Xbar.scala 132:44] + _T_7016[0] <= _T_7009 @[Xbar.scala 132:44] + _T_7016[1] <= _T_7011 @[Xbar.scala 132:44] + _T_7016[2] <= _T_7013 @[Xbar.scala 132:44] + node _T_7023 = xor(UInt<1>("h00"), out[1].d.bits.source) @[Parameters.scala 37:23] + node _T_7024 = not(_T_7023) @[Parameters.scala 37:9] + node _T_7026 = or(_T_7024, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7027 = not(_T_7026) @[Parameters.scala 37:7] + node _T_7029 = eq(_T_7027, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7031 = eq(UInt<3>("h05"), out[1].d.bits.source) @[Parameters.scala 35:39] + node _T_7033 = eq(UInt<3>("h04"), out[1].d.bits.source) @[Parameters.scala 35:39] + wire _T_7036 : UInt<1>[3] @[Xbar.scala 132:44] + _T_7036 is invalid @[Xbar.scala 132:44] + _T_7036[0] <= _T_7029 @[Xbar.scala 132:44] + _T_7036[1] <= _T_7031 @[Xbar.scala 132:44] + _T_7036[2] <= _T_7033 @[Xbar.scala 132:44] + node _T_7043 = xor(UInt<1>("h00"), out[2].d.bits.source) @[Parameters.scala 37:23] + node _T_7044 = not(_T_7043) @[Parameters.scala 37:9] + node _T_7046 = or(_T_7044, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7047 = not(_T_7046) @[Parameters.scala 37:7] + node _T_7049 = eq(_T_7047, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7051 = eq(UInt<3>("h05"), out[2].d.bits.source) @[Parameters.scala 35:39] + node _T_7053 = eq(UInt<3>("h04"), out[2].d.bits.source) @[Parameters.scala 35:39] + wire _T_7056 : UInt<1>[3] @[Xbar.scala 132:44] + _T_7056 is invalid @[Xbar.scala 132:44] + _T_7056[0] <= _T_7049 @[Xbar.scala 132:44] + _T_7056[1] <= _T_7051 @[Xbar.scala 132:44] + _T_7056[2] <= _T_7053 @[Xbar.scala 132:44] + wire requestDOI : UInt<1>[3][3] @[Xbar.scala 132:25] + requestDOI is invalid @[Xbar.scala 132:25] + requestDOI[0] <- _T_7016 @[Xbar.scala 132:25] + requestDOI[1] <- _T_7036 @[Xbar.scala 132:25] + requestDOI[2] <- _T_7056 @[Xbar.scala 132:25] + node _T_7194 = xor(UInt<3>("h04"), in[0].e.bits.sink) @[Parameters.scala 37:23] + node _T_7195 = not(_T_7194) @[Parameters.scala 37:9] + node _T_7197 = or(_T_7195, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7198 = not(_T_7197) @[Parameters.scala 37:7] + node _T_7200 = eq(_T_7198, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7202 = xor(UInt<4>("h08"), in[0].e.bits.sink) @[Parameters.scala 37:23] + node _T_7203 = not(_T_7202) @[Parameters.scala 37:9] + node _T_7205 = or(_T_7203, UInt<1>("h01")) @[Parameters.scala 37:28] + node _T_7206 = not(_T_7205) @[Parameters.scala 37:7] + node _T_7208 = eq(_T_7206, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7210 = xor(UInt<1>("h00"), in[0].e.bits.sink) @[Parameters.scala 37:23] + node _T_7211 = not(_T_7210) @[Parameters.scala 37:9] + node _T_7213 = or(_T_7211, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7214 = not(_T_7213) @[Parameters.scala 37:7] + node _T_7216 = eq(_T_7214, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_7219 : UInt<1>[3] @[Xbar.scala 133:44] + _T_7219 is invalid @[Xbar.scala 133:44] + _T_7219[0] <= _T_7200 @[Xbar.scala 133:44] + _T_7219[1] <= _T_7208 @[Xbar.scala 133:44] + _T_7219[2] <= _T_7216 @[Xbar.scala 133:44] + node _T_7226 = xor(UInt<3>("h04"), in[1].e.bits.sink) @[Parameters.scala 37:23] + node _T_7227 = not(_T_7226) @[Parameters.scala 37:9] + node _T_7229 = or(_T_7227, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7230 = not(_T_7229) @[Parameters.scala 37:7] + node _T_7232 = eq(_T_7230, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7234 = xor(UInt<4>("h08"), in[1].e.bits.sink) @[Parameters.scala 37:23] + node _T_7235 = not(_T_7234) @[Parameters.scala 37:9] + node _T_7237 = or(_T_7235, UInt<1>("h01")) @[Parameters.scala 37:28] + node _T_7238 = not(_T_7237) @[Parameters.scala 37:7] + node _T_7240 = eq(_T_7238, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7242 = xor(UInt<1>("h00"), in[1].e.bits.sink) @[Parameters.scala 37:23] + node _T_7243 = not(_T_7242) @[Parameters.scala 37:9] + node _T_7245 = or(_T_7243, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7246 = not(_T_7245) @[Parameters.scala 37:7] + node _T_7248 = eq(_T_7246, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_7251 : UInt<1>[3] @[Xbar.scala 133:44] + _T_7251 is invalid @[Xbar.scala 133:44] + _T_7251[0] <= _T_7232 @[Xbar.scala 133:44] + _T_7251[1] <= _T_7240 @[Xbar.scala 133:44] + _T_7251[2] <= _T_7248 @[Xbar.scala 133:44] + node _T_7258 = xor(UInt<3>("h04"), in[2].e.bits.sink) @[Parameters.scala 37:23] + node _T_7259 = not(_T_7258) @[Parameters.scala 37:9] + node _T_7261 = or(_T_7259, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7262 = not(_T_7261) @[Parameters.scala 37:7] + node _T_7264 = eq(_T_7262, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7266 = xor(UInt<4>("h08"), in[2].e.bits.sink) @[Parameters.scala 37:23] + node _T_7267 = not(_T_7266) @[Parameters.scala 37:9] + node _T_7269 = or(_T_7267, UInt<1>("h01")) @[Parameters.scala 37:28] + node _T_7270 = not(_T_7269) @[Parameters.scala 37:7] + node _T_7272 = eq(_T_7270, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_7274 = xor(UInt<1>("h00"), in[2].e.bits.sink) @[Parameters.scala 37:23] + node _T_7275 = not(_T_7274) @[Parameters.scala 37:9] + node _T_7277 = or(_T_7275, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_7278 = not(_T_7277) @[Parameters.scala 37:7] + node _T_7280 = eq(_T_7278, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_7283 : UInt<1>[3] @[Xbar.scala 133:44] + _T_7283 is invalid @[Xbar.scala 133:44] + _T_7283[0] <= _T_7264 @[Xbar.scala 133:44] + _T_7283[1] <= _T_7272 @[Xbar.scala 133:44] + _T_7283[2] <= _T_7280 @[Xbar.scala 133:44] + wire requestEIO : UInt<1>[3][3] @[Xbar.scala 133:25] + requestEIO is invalid @[Xbar.scala 133:25] + requestEIO[0] <- _T_7219 @[Xbar.scala 133:25] + requestEIO[1] <- _T_7251 @[Xbar.scala 133:25] + requestEIO[2] <- _T_7283 @[Xbar.scala 133:25] + node _T_7421 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7422 = dshl(_T_7421, in[0].a.bits.size) @[package.scala 19:71] + node _T_7423 = bits(_T_7422, 7, 0) @[package.scala 19:76] + node _T_7424 = not(_T_7423) @[package.scala 19:40] + node _T_7425 = shr(_T_7424, 3) @[Edges.scala 198:59] + node _T_7426 = bits(in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_7428 = eq(_T_7426, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_7430 = mux(_T_7428, _T_7425, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7432 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7433 = dshl(_T_7432, in[1].a.bits.size) @[package.scala 19:71] + node _T_7434 = bits(_T_7433, 7, 0) @[package.scala 19:76] + node _T_7435 = not(_T_7434) @[package.scala 19:40] + node _T_7436 = shr(_T_7435, 3) @[Edges.scala 198:59] + node _T_7437 = bits(in[1].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_7439 = eq(_T_7437, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_7441 = mux(_T_7439, _T_7436, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7443 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7444 = dshl(_T_7443, in[2].a.bits.size) @[package.scala 19:71] + node _T_7445 = bits(_T_7444, 7, 0) @[package.scala 19:76] + node _T_7446 = not(_T_7445) @[package.scala 19:40] + node _T_7447 = shr(_T_7446, 3) @[Edges.scala 198:59] + node _T_7448 = bits(in[2].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_7450 = eq(_T_7448, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_7452 = mux(_T_7450, _T_7447, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsAI : UInt<5>[3] @[Xbar.scala 135:22] + beatsAI is invalid @[Xbar.scala 135:22] + beatsAI[0] <= _T_7430 @[Xbar.scala 135:22] + beatsAI[1] <= _T_7441 @[Xbar.scala 135:22] + beatsAI[2] <= _T_7452 @[Xbar.scala 135:22] + node _T_7461 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_7462 = dshl(_T_7461, out[0].b.bits.size) @[package.scala 19:71] + node _T_7463 = bits(_T_7462, 5, 0) @[package.scala 19:76] + node _T_7464 = not(_T_7463) @[package.scala 19:40] + node _T_7465 = shr(_T_7464, 3) @[Edges.scala 198:59] + node _T_7466 = bits(out[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_7468 = eq(_T_7466, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_7471 = mux(UInt<1>("h00"), _T_7465, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7473 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7474 = dshl(_T_7473, out[1].b.bits.size) @[package.scala 19:71] + node _T_7475 = bits(_T_7474, 7, 0) @[package.scala 19:76] + node _T_7476 = not(_T_7475) @[package.scala 19:40] + node _T_7477 = shr(_T_7476, 3) @[Edges.scala 198:59] + node _T_7478 = bits(out[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_7480 = eq(_T_7478, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_7483 = mux(UInt<1>("h00"), _T_7477, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7485 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_7486 = dshl(_T_7485, out[2].b.bits.size) @[package.scala 19:71] + node _T_7487 = bits(_T_7486, 5, 0) @[package.scala 19:76] + node _T_7488 = not(_T_7487) @[package.scala 19:40] + node _T_7489 = shr(_T_7488, 3) @[Edges.scala 198:59] + node _T_7490 = bits(out[2].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_7492 = eq(_T_7490, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_7495 = mux(UInt<1>("h00"), _T_7489, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsBO : UInt<5>[3] @[Xbar.scala 136:22] + beatsBO is invalid @[Xbar.scala 136:22] + beatsBO[0] <= _T_7471 @[Xbar.scala 136:22] + beatsBO[1] <= _T_7483 @[Xbar.scala 136:22] + beatsBO[2] <= _T_7495 @[Xbar.scala 136:22] + node _T_7504 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7505 = dshl(_T_7504, in[0].c.bits.size) @[package.scala 19:71] + node _T_7506 = bits(_T_7505, 7, 0) @[package.scala 19:76] + node _T_7507 = not(_T_7506) @[package.scala 19:40] + node _T_7508 = shr(_T_7507, 3) @[Edges.scala 198:59] + node _T_7509 = bits(in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_7512 = mux(UInt<1>("h00"), _T_7508, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7514 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7515 = dshl(_T_7514, in[1].c.bits.size) @[package.scala 19:71] + node _T_7516 = bits(_T_7515, 7, 0) @[package.scala 19:76] + node _T_7517 = not(_T_7516) @[package.scala 19:40] + node _T_7518 = shr(_T_7517, 3) @[Edges.scala 198:59] + node _T_7519 = bits(in[1].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_7521 = mux(_T_7519, _T_7518, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7523 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7524 = dshl(_T_7523, in[2].c.bits.size) @[package.scala 19:71] + node _T_7525 = bits(_T_7524, 7, 0) @[package.scala 19:76] + node _T_7526 = not(_T_7525) @[package.scala 19:40] + node _T_7527 = shr(_T_7526, 3) @[Edges.scala 198:59] + node _T_7528 = bits(in[2].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_7531 = mux(UInt<1>("h00"), _T_7527, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsCI : UInt<5>[3] @[Xbar.scala 137:22] + beatsCI is invalid @[Xbar.scala 137:22] + beatsCI[0] <= _T_7512 @[Xbar.scala 137:22] + beatsCI[1] <= _T_7521 @[Xbar.scala 137:22] + beatsCI[2] <= _T_7531 @[Xbar.scala 137:22] + node _T_7540 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_7541 = dshl(_T_7540, out[0].d.bits.size) @[package.scala 19:71] + node _T_7542 = bits(_T_7541, 5, 0) @[package.scala 19:76] + node _T_7543 = not(_T_7542) @[package.scala 19:40] + node _T_7544 = shr(_T_7543, 3) @[Edges.scala 198:59] + node _T_7545 = bits(out[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_7547 = mux(_T_7545, _T_7544, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7549 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_7550 = dshl(_T_7549, out[1].d.bits.size) @[package.scala 19:71] + node _T_7551 = bits(_T_7550, 7, 0) @[package.scala 19:76] + node _T_7552 = not(_T_7551) @[package.scala 19:40] + node _T_7553 = shr(_T_7552, 3) @[Edges.scala 198:59] + node _T_7554 = bits(out[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_7556 = mux(_T_7554, _T_7553, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_7558 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_7559 = dshl(_T_7558, out[2].d.bits.size) @[package.scala 19:71] + node _T_7560 = bits(_T_7559, 5, 0) @[package.scala 19:76] + node _T_7561 = not(_T_7560) @[package.scala 19:40] + node _T_7562 = shr(_T_7561, 3) @[Edges.scala 198:59] + node _T_7563 = bits(out[2].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_7565 = mux(_T_7563, _T_7562, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsDO : UInt<5>[3] @[Xbar.scala 138:22] + beatsDO is invalid @[Xbar.scala 138:22] + beatsDO[0] <= _T_7547 @[Xbar.scala 138:22] + beatsDO[1] <= _T_7556 @[Xbar.scala 138:22] + beatsDO[2] <= _T_7565 @[Xbar.scala 138:22] + wire beatsEI : UInt<1>[3] @[Xbar.scala 139:22] + beatsEI is invalid @[Xbar.scala 139:22] + beatsEI[0] <= UInt<1>("h00") @[Xbar.scala 139:22] + beatsEI[1] <= UInt<1>("h00") @[Xbar.scala 139:22] + beatsEI[2] <= UInt<1>("h00") @[Xbar.scala 139:22] + wire _T_7665 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_7665 is invalid @[Xbar.scala 147:26] + _T_7665[0].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_7831 = and(in[0].a.valid, requestAIO[0][0]) @[Xbar.scala 150:42] + _T_7665[0].valid <= _T_7831 @[Xbar.scala 150:27] + _T_7665[1].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_7832 = and(in[0].a.valid, requestAIO[0][1]) @[Xbar.scala 150:42] + _T_7665[1].valid <= _T_7832 @[Xbar.scala 150:27] + _T_7665[2].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_7833 = and(in[0].a.valid, requestAIO[0][2]) @[Xbar.scala 150:42] + _T_7665[2].valid <= _T_7833 @[Xbar.scala 150:27] + node _T_7835 = mux(requestAIO[0][0], _T_7665[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_7837 = mux(requestAIO[0][1], _T_7665[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_7839 = mux(requestAIO[0][2], _T_7665[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_7841 = or(_T_7835, _T_7837) @[Mux.scala 19:72] + node _T_7842 = or(_T_7841, _T_7839) @[Mux.scala 19:72] + wire _T_7844 : UInt<1> @[Mux.scala 19:72] + _T_7844 is invalid @[Mux.scala 19:72] + _T_7844 <= _T_7842 @[Mux.scala 19:72] + in[0].a.ready <= _T_7844 @[Xbar.scala 152:19] + wire _T_7927 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_7927 is invalid @[Xbar.scala 147:26] + _T_7927[0].bits <- in[1].a.bits @[Xbar.scala 149:26] + node _T_8093 = and(in[1].a.valid, requestAIO[1][0]) @[Xbar.scala 150:42] + _T_7927[0].valid <= _T_8093 @[Xbar.scala 150:27] + _T_7927[1].bits <- in[1].a.bits @[Xbar.scala 149:26] + node _T_8094 = and(in[1].a.valid, requestAIO[1][1]) @[Xbar.scala 150:42] + _T_7927[1].valid <= _T_8094 @[Xbar.scala 150:27] + _T_7927[2].bits <- in[1].a.bits @[Xbar.scala 149:26] + node _T_8095 = and(in[1].a.valid, requestAIO[1][2]) @[Xbar.scala 150:42] + _T_7927[2].valid <= _T_8095 @[Xbar.scala 150:27] + node _T_8097 = mux(requestAIO[1][0], _T_7927[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8099 = mux(requestAIO[1][1], _T_7927[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8101 = mux(requestAIO[1][2], _T_7927[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8103 = or(_T_8097, _T_8099) @[Mux.scala 19:72] + node _T_8104 = or(_T_8103, _T_8101) @[Mux.scala 19:72] + wire _T_8106 : UInt<1> @[Mux.scala 19:72] + _T_8106 is invalid @[Mux.scala 19:72] + _T_8106 <= _T_8104 @[Mux.scala 19:72] + in[1].a.ready <= _T_8106 @[Xbar.scala 152:19] + wire _T_8189 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_8189 is invalid @[Xbar.scala 147:26] + _T_8189[0].bits <- in[2].a.bits @[Xbar.scala 149:26] + node _T_8355 = and(in[2].a.valid, requestAIO[2][0]) @[Xbar.scala 150:42] + _T_8189[0].valid <= _T_8355 @[Xbar.scala 150:27] + _T_8189[1].bits <- in[2].a.bits @[Xbar.scala 149:26] + node _T_8356 = and(in[2].a.valid, requestAIO[2][1]) @[Xbar.scala 150:42] + _T_8189[1].valid <= _T_8356 @[Xbar.scala 150:27] + _T_8189[2].bits <- in[2].a.bits @[Xbar.scala 149:26] + node _T_8357 = and(in[2].a.valid, requestAIO[2][2]) @[Xbar.scala 150:42] + _T_8189[2].valid <= _T_8357 @[Xbar.scala 150:27] + node _T_8359 = mux(requestAIO[2][0], _T_8189[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8361 = mux(requestAIO[2][1], _T_8189[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8363 = mux(requestAIO[2][2], _T_8189[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8365 = or(_T_8359, _T_8361) @[Mux.scala 19:72] + node _T_8366 = or(_T_8365, _T_8363) @[Mux.scala 19:72] + wire _T_8368 : UInt<1> @[Mux.scala 19:72] + _T_8368 is invalid @[Mux.scala 19:72] + _T_8368 <= _T_8366 @[Mux.scala 19:72] + in[2].a.ready <= _T_8368 @[Xbar.scala 152:19] + wire _T_8451 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_8451 is invalid @[Xbar.scala 147:26] + _T_8451[0].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_8617 = and(out[0].b.valid, requestBOI[0][0]) @[Xbar.scala 150:42] + _T_8451[0].valid <= _T_8617 @[Xbar.scala 150:27] + _T_8451[1].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_8618 = and(out[0].b.valid, requestBOI[0][1]) @[Xbar.scala 150:42] + _T_8451[1].valid <= _T_8618 @[Xbar.scala 150:27] + _T_8451[2].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_8619 = and(out[0].b.valid, requestBOI[0][2]) @[Xbar.scala 150:42] + _T_8451[2].valid <= _T_8619 @[Xbar.scala 150:27] + node _T_8621 = mux(requestBOI[0][0], _T_8451[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8623 = mux(requestBOI[0][1], _T_8451[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8625 = mux(requestBOI[0][2], _T_8451[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8627 = or(_T_8621, _T_8623) @[Mux.scala 19:72] + node _T_8628 = or(_T_8627, _T_8625) @[Mux.scala 19:72] + wire _T_8630 : UInt<1> @[Mux.scala 19:72] + _T_8630 is invalid @[Mux.scala 19:72] + _T_8630 <= _T_8628 @[Mux.scala 19:72] + out[0].b.ready <= _T_8630 @[Xbar.scala 152:19] + wire _T_8713 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_8713 is invalid @[Xbar.scala 147:26] + _T_8713[0].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_8879 = and(out[1].b.valid, requestBOI[1][0]) @[Xbar.scala 150:42] + _T_8713[0].valid <= _T_8879 @[Xbar.scala 150:27] + _T_8713[1].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_8880 = and(out[1].b.valid, requestBOI[1][1]) @[Xbar.scala 150:42] + _T_8713[1].valid <= _T_8880 @[Xbar.scala 150:27] + _T_8713[2].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_8881 = and(out[1].b.valid, requestBOI[1][2]) @[Xbar.scala 150:42] + _T_8713[2].valid <= _T_8881 @[Xbar.scala 150:27] + node _T_8883 = mux(requestBOI[1][0], _T_8713[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8885 = mux(requestBOI[1][1], _T_8713[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8887 = mux(requestBOI[1][2], _T_8713[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_8889 = or(_T_8883, _T_8885) @[Mux.scala 19:72] + node _T_8890 = or(_T_8889, _T_8887) @[Mux.scala 19:72] + wire _T_8892 : UInt<1> @[Mux.scala 19:72] + _T_8892 is invalid @[Mux.scala 19:72] + _T_8892 <= _T_8890 @[Mux.scala 19:72] + out[1].b.ready <= _T_8892 @[Xbar.scala 152:19] + wire _T_8975 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_8975 is invalid @[Xbar.scala 147:26] + _T_8975[0].bits <- out[2].b.bits @[Xbar.scala 149:26] + node _T_9141 = and(out[2].b.valid, requestBOI[2][0]) @[Xbar.scala 150:42] + _T_8975[0].valid <= _T_9141 @[Xbar.scala 150:27] + _T_8975[1].bits <- out[2].b.bits @[Xbar.scala 149:26] + node _T_9142 = and(out[2].b.valid, requestBOI[2][1]) @[Xbar.scala 150:42] + _T_8975[1].valid <= _T_9142 @[Xbar.scala 150:27] + _T_8975[2].bits <- out[2].b.bits @[Xbar.scala 149:26] + node _T_9143 = and(out[2].b.valid, requestBOI[2][2]) @[Xbar.scala 150:42] + _T_8975[2].valid <= _T_9143 @[Xbar.scala 150:27] + node _T_9145 = mux(requestBOI[2][0], _T_8975[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9147 = mux(requestBOI[2][1], _T_8975[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9149 = mux(requestBOI[2][2], _T_8975[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9151 = or(_T_9145, _T_9147) @[Mux.scala 19:72] + node _T_9152 = or(_T_9151, _T_9149) @[Mux.scala 19:72] + wire _T_9154 : UInt<1> @[Mux.scala 19:72] + _T_9154 is invalid @[Mux.scala 19:72] + _T_9154 <= _T_9152 @[Mux.scala 19:72] + out[2].b.ready <= _T_9154 @[Xbar.scala 152:19] + wire _T_9237 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_9237 is invalid @[Xbar.scala 147:26] + _T_9237[0].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_9403 = and(in[0].c.valid, requestCIO[0][0]) @[Xbar.scala 150:42] + _T_9237[0].valid <= _T_9403 @[Xbar.scala 150:27] + _T_9237[1].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_9404 = and(in[0].c.valid, requestCIO[0][1]) @[Xbar.scala 150:42] + _T_9237[1].valid <= _T_9404 @[Xbar.scala 150:27] + _T_9237[2].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_9405 = and(in[0].c.valid, requestCIO[0][2]) @[Xbar.scala 150:42] + _T_9237[2].valid <= _T_9405 @[Xbar.scala 150:27] + node _T_9407 = mux(requestCIO[0][0], _T_9237[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9409 = mux(requestCIO[0][1], _T_9237[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9411 = mux(requestCIO[0][2], _T_9237[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9413 = or(_T_9407, _T_9409) @[Mux.scala 19:72] + node _T_9414 = or(_T_9413, _T_9411) @[Mux.scala 19:72] + wire _T_9416 : UInt<1> @[Mux.scala 19:72] + _T_9416 is invalid @[Mux.scala 19:72] + _T_9416 <= _T_9414 @[Mux.scala 19:72] + in[0].c.ready <= _T_9416 @[Xbar.scala 152:19] + wire _T_9499 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_9499 is invalid @[Xbar.scala 147:26] + _T_9499[0].bits <- in[1].c.bits @[Xbar.scala 149:26] + node _T_9665 = and(in[1].c.valid, requestCIO[1][0]) @[Xbar.scala 150:42] + _T_9499[0].valid <= _T_9665 @[Xbar.scala 150:27] + _T_9499[1].bits <- in[1].c.bits @[Xbar.scala 149:26] + node _T_9666 = and(in[1].c.valid, requestCIO[1][1]) @[Xbar.scala 150:42] + _T_9499[1].valid <= _T_9666 @[Xbar.scala 150:27] + _T_9499[2].bits <- in[1].c.bits @[Xbar.scala 149:26] + node _T_9667 = and(in[1].c.valid, requestCIO[1][2]) @[Xbar.scala 150:42] + _T_9499[2].valid <= _T_9667 @[Xbar.scala 150:27] + node _T_9669 = mux(requestCIO[1][0], _T_9499[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9671 = mux(requestCIO[1][1], _T_9499[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9673 = mux(requestCIO[1][2], _T_9499[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9675 = or(_T_9669, _T_9671) @[Mux.scala 19:72] + node _T_9676 = or(_T_9675, _T_9673) @[Mux.scala 19:72] + wire _T_9678 : UInt<1> @[Mux.scala 19:72] + _T_9678 is invalid @[Mux.scala 19:72] + _T_9678 <= _T_9676 @[Mux.scala 19:72] + in[1].c.ready <= _T_9678 @[Xbar.scala 152:19] + wire _T_9761 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_9761 is invalid @[Xbar.scala 147:26] + _T_9761[0].bits <- in[2].c.bits @[Xbar.scala 149:26] + node _T_9927 = and(in[2].c.valid, requestCIO[2][0]) @[Xbar.scala 150:42] + _T_9761[0].valid <= _T_9927 @[Xbar.scala 150:27] + _T_9761[1].bits <- in[2].c.bits @[Xbar.scala 149:26] + node _T_9928 = and(in[2].c.valid, requestCIO[2][1]) @[Xbar.scala 150:42] + _T_9761[1].valid <= _T_9928 @[Xbar.scala 150:27] + _T_9761[2].bits <- in[2].c.bits @[Xbar.scala 149:26] + node _T_9929 = and(in[2].c.valid, requestCIO[2][2]) @[Xbar.scala 150:42] + _T_9761[2].valid <= _T_9929 @[Xbar.scala 150:27] + node _T_9931 = mux(requestCIO[2][0], _T_9761[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9933 = mux(requestCIO[2][1], _T_9761[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9935 = mux(requestCIO[2][2], _T_9761[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_9937 = or(_T_9931, _T_9933) @[Mux.scala 19:72] + node _T_9938 = or(_T_9937, _T_9935) @[Mux.scala 19:72] + wire _T_9940 : UInt<1> @[Mux.scala 19:72] + _T_9940 is invalid @[Mux.scala 19:72] + _T_9940 <= _T_9938 @[Mux.scala 19:72] + in[2].c.ready <= _T_9940 @[Xbar.scala 152:19] + wire _T_10031 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_10031 is invalid @[Xbar.scala 147:26] + _T_10031[0].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_10213 = and(out[0].d.valid, requestDOI[0][0]) @[Xbar.scala 150:42] + _T_10031[0].valid <= _T_10213 @[Xbar.scala 150:27] + _T_10031[1].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_10214 = and(out[0].d.valid, requestDOI[0][1]) @[Xbar.scala 150:42] + _T_10031[1].valid <= _T_10214 @[Xbar.scala 150:27] + _T_10031[2].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_10215 = and(out[0].d.valid, requestDOI[0][2]) @[Xbar.scala 150:42] + _T_10031[2].valid <= _T_10215 @[Xbar.scala 150:27] + node _T_10217 = mux(requestDOI[0][0], _T_10031[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10219 = mux(requestDOI[0][1], _T_10031[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10221 = mux(requestDOI[0][2], _T_10031[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10223 = or(_T_10217, _T_10219) @[Mux.scala 19:72] + node _T_10224 = or(_T_10223, _T_10221) @[Mux.scala 19:72] + wire _T_10226 : UInt<1> @[Mux.scala 19:72] + _T_10226 is invalid @[Mux.scala 19:72] + _T_10226 <= _T_10224 @[Mux.scala 19:72] + out[0].d.ready <= _T_10226 @[Xbar.scala 152:19] + wire _T_10317 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_10317 is invalid @[Xbar.scala 147:26] + _T_10317[0].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_10499 = and(out[1].d.valid, requestDOI[1][0]) @[Xbar.scala 150:42] + _T_10317[0].valid <= _T_10499 @[Xbar.scala 150:27] + _T_10317[1].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_10500 = and(out[1].d.valid, requestDOI[1][1]) @[Xbar.scala 150:42] + _T_10317[1].valid <= _T_10500 @[Xbar.scala 150:27] + _T_10317[2].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_10501 = and(out[1].d.valid, requestDOI[1][2]) @[Xbar.scala 150:42] + _T_10317[2].valid <= _T_10501 @[Xbar.scala 150:27] + node _T_10503 = mux(requestDOI[1][0], _T_10317[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10505 = mux(requestDOI[1][1], _T_10317[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10507 = mux(requestDOI[1][2], _T_10317[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10509 = or(_T_10503, _T_10505) @[Mux.scala 19:72] + node _T_10510 = or(_T_10509, _T_10507) @[Mux.scala 19:72] + wire _T_10512 : UInt<1> @[Mux.scala 19:72] + _T_10512 is invalid @[Mux.scala 19:72] + _T_10512 <= _T_10510 @[Mux.scala 19:72] + out[1].d.ready <= _T_10512 @[Xbar.scala 152:19] + wire _T_10603 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_10603 is invalid @[Xbar.scala 147:26] + _T_10603[0].bits <- out[2].d.bits @[Xbar.scala 149:26] + node _T_10785 = and(out[2].d.valid, requestDOI[2][0]) @[Xbar.scala 150:42] + _T_10603[0].valid <= _T_10785 @[Xbar.scala 150:27] + _T_10603[1].bits <- out[2].d.bits @[Xbar.scala 149:26] + node _T_10786 = and(out[2].d.valid, requestDOI[2][1]) @[Xbar.scala 150:42] + _T_10603[1].valid <= _T_10786 @[Xbar.scala 150:27] + _T_10603[2].bits <- out[2].d.bits @[Xbar.scala 149:26] + node _T_10787 = and(out[2].d.valid, requestDOI[2][2]) @[Xbar.scala 150:42] + _T_10603[2].valid <= _T_10787 @[Xbar.scala 150:27] + node _T_10789 = mux(requestDOI[2][0], _T_10603[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10791 = mux(requestDOI[2][1], _T_10603[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10793 = mux(requestDOI[2][2], _T_10603[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10795 = or(_T_10789, _T_10791) @[Mux.scala 19:72] + node _T_10796 = or(_T_10795, _T_10793) @[Mux.scala 19:72] + wire _T_10798 : UInt<1> @[Mux.scala 19:72] + _T_10798 is invalid @[Mux.scala 19:72] + _T_10798 <= _T_10796 @[Mux.scala 19:72] + out[2].d.ready <= _T_10798 @[Xbar.scala 152:19] + wire _T_10833 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}[3] @[Xbar.scala 147:26] + _T_10833 is invalid @[Xbar.scala 147:26] + _T_10833[0].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_10903 = and(in[0].e.valid, requestEIO[0][0]) @[Xbar.scala 150:42] + _T_10833[0].valid <= _T_10903 @[Xbar.scala 150:27] + _T_10833[1].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_10904 = and(in[0].e.valid, requestEIO[0][1]) @[Xbar.scala 150:42] + _T_10833[1].valid <= _T_10904 @[Xbar.scala 150:27] + _T_10833[2].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_10905 = and(in[0].e.valid, requestEIO[0][2]) @[Xbar.scala 150:42] + _T_10833[2].valid <= _T_10905 @[Xbar.scala 150:27] + node _T_10907 = mux(requestEIO[0][0], _T_10833[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10909 = mux(requestEIO[0][1], _T_10833[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10911 = mux(requestEIO[0][2], _T_10833[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_10913 = or(_T_10907, _T_10909) @[Mux.scala 19:72] + node _T_10914 = or(_T_10913, _T_10911) @[Mux.scala 19:72] + wire _T_10916 : UInt<1> @[Mux.scala 19:72] + _T_10916 is invalid @[Mux.scala 19:72] + _T_10916 <= _T_10914 @[Mux.scala 19:72] + in[0].e.ready <= _T_10916 @[Xbar.scala 152:19] + wire _T_10951 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}[3] @[Xbar.scala 147:26] + _T_10951 is invalid @[Xbar.scala 147:26] + _T_10951[0].bits <- in[1].e.bits @[Xbar.scala 149:26] + node _T_11021 = and(in[1].e.valid, requestEIO[1][0]) @[Xbar.scala 150:42] + _T_10951[0].valid <= _T_11021 @[Xbar.scala 150:27] + _T_10951[1].bits <- in[1].e.bits @[Xbar.scala 149:26] + node _T_11022 = and(in[1].e.valid, requestEIO[1][1]) @[Xbar.scala 150:42] + _T_10951[1].valid <= _T_11022 @[Xbar.scala 150:27] + _T_10951[2].bits <- in[1].e.bits @[Xbar.scala 149:26] + node _T_11023 = and(in[1].e.valid, requestEIO[1][2]) @[Xbar.scala 150:42] + _T_10951[2].valid <= _T_11023 @[Xbar.scala 150:27] + node _T_11025 = mux(requestEIO[1][0], _T_10951[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11027 = mux(requestEIO[1][1], _T_10951[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11029 = mux(requestEIO[1][2], _T_10951[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11031 = or(_T_11025, _T_11027) @[Mux.scala 19:72] + node _T_11032 = or(_T_11031, _T_11029) @[Mux.scala 19:72] + wire _T_11034 : UInt<1> @[Mux.scala 19:72] + _T_11034 is invalid @[Mux.scala 19:72] + _T_11034 <= _T_11032 @[Mux.scala 19:72] + in[1].e.ready <= _T_11034 @[Xbar.scala 152:19] + wire _T_11069 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}[3] @[Xbar.scala 147:26] + _T_11069 is invalid @[Xbar.scala 147:26] + _T_11069[0].bits <- in[2].e.bits @[Xbar.scala 149:26] + node _T_11139 = and(in[2].e.valid, requestEIO[2][0]) @[Xbar.scala 150:42] + _T_11069[0].valid <= _T_11139 @[Xbar.scala 150:27] + _T_11069[1].bits <- in[2].e.bits @[Xbar.scala 149:26] + node _T_11140 = and(in[2].e.valid, requestEIO[2][1]) @[Xbar.scala 150:42] + _T_11069[1].valid <= _T_11140 @[Xbar.scala 150:27] + _T_11069[2].bits <- in[2].e.bits @[Xbar.scala 149:26] + node _T_11141 = and(in[2].e.valid, requestEIO[2][2]) @[Xbar.scala 150:42] + _T_11069[2].valid <= _T_11141 @[Xbar.scala 150:27] + node _T_11143 = mux(requestEIO[2][0], _T_11069[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11145 = mux(requestEIO[2][1], _T_11069[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11147 = mux(requestEIO[2][2], _T_11069[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11149 = or(_T_11143, _T_11145) @[Mux.scala 19:72] + node _T_11150 = or(_T_11149, _T_11147) @[Mux.scala 19:72] + wire _T_11152 : UInt<1> @[Mux.scala 19:72] + _T_11152 is invalid @[Mux.scala 19:72] + _T_11152 <= _T_11150 @[Mux.scala 19:72] + in[2].e.ready <= _T_11152 @[Xbar.scala 152:19] + reg _T_11154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11156 = eq(_T_11154, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11157 = and(_T_11156, out[0].a.ready) @[Arbiter.scala 35:24] + node _T_11160 = eq(_T_7665[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11161 = and(UInt<1>("h01"), _T_11160) @[Arbiter.scala 14:35] + node _T_11163 = eq(_T_7927[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11164 = and(_T_11161, _T_11163) @[Arbiter.scala 14:35] + node _T_11166 = eq(_T_8189[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11167 = and(_T_11164, _T_11166) @[Arbiter.scala 14:35] + wire _T_11170 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_11170 is invalid @[Arbiter.scala 40:23] + _T_11170[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_11170[1] <= _T_11161 @[Arbiter.scala 40:23] + _T_11170[2] <= _T_11164 @[Arbiter.scala 40:23] + node _T_11176 = and(_T_11170[0], _T_7665[0].valid) @[Arbiter.scala 42:65] + node _T_11177 = and(_T_11170[1], _T_7927[0].valid) @[Arbiter.scala 42:65] + node _T_11178 = and(_T_11170[2], _T_8189[0].valid) @[Arbiter.scala 42:65] + wire _T_11181 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_11181 is invalid @[Arbiter.scala 42:23] + _T_11181[0] <= _T_11176 @[Arbiter.scala 42:23] + _T_11181[1] <= _T_11177 @[Arbiter.scala 42:23] + _T_11181[2] <= _T_11178 @[Arbiter.scala 42:23] + node _T_11188 = or(UInt<1>("h00"), _T_11181[0]) @[Arbiter.scala 47:52] + node _T_11189 = or(_T_11188, _T_11181[1]) @[Arbiter.scala 47:52] + node _T_11190 = or(_T_11189, _T_11181[2]) @[Arbiter.scala 47:52] + node _T_11192 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11194 = eq(_T_11181[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11195 = or(_T_11192, _T_11194) @[Arbiter.scala 48:59] + node _T_11197 = eq(_T_11188, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11199 = eq(_T_11181[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11200 = or(_T_11197, _T_11199) @[Arbiter.scala 48:59] + node _T_11202 = eq(_T_11189, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11204 = eq(_T_11181[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11205 = or(_T_11202, _T_11204) @[Arbiter.scala 48:59] + node _T_11206 = and(_T_11195, _T_11200) @[Arbiter.scala 48:77] + node _T_11207 = and(_T_11206, _T_11205) @[Arbiter.scala 48:77] + node _T_11208 = or(_T_11207, reset) @[Arbiter.scala 48:13] + node _T_11210 = eq(_T_11208, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11210 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11211 = or(_T_7665[0].valid, _T_7927[0].valid) @[Arbiter.scala 50:31] + node _T_11212 = or(_T_11211, _T_8189[0].valid) @[Arbiter.scala 50:31] + node _T_11214 = eq(_T_11212, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11215 = or(_T_11181[0], _T_11181[1]) @[Arbiter.scala 50:54] + node _T_11216 = or(_T_11215, _T_11181[2]) @[Arbiter.scala 50:54] + node _T_11217 = or(_T_11214, _T_11216) @[Arbiter.scala 50:36] + node _T_11218 = or(_T_11217, reset) @[Arbiter.scala 50:14] + node _T_11220 = eq(_T_11218, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11220 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11222 = mux(_T_11181[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11224 = mux(_T_11181[1], beatsAI[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11226 = mux(_T_11181[2], beatsAI[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11227 = or(_T_11222, _T_11224) @[Arbiter.scala 54:44] + node _T_11228 = or(_T_11227, _T_11226) @[Arbiter.scala 54:44] + node _T_11229 = and(out[0].a.ready, out[0].a.valid) @[Decoupled.scala 30:37] + node _T_11230 = sub(_T_11154, _T_11229) @[Arbiter.scala 55:52] + node _T_11231 = asUInt(_T_11230) @[Arbiter.scala 55:52] + node _T_11232 = tail(_T_11231, 1) @[Arbiter.scala 55:52] + node _T_11233 = mux(_T_11157, _T_11228, _T_11232) @[Arbiter.scala 55:23] + _T_11154 <= _T_11233 @[Arbiter.scala 55:17] + wire _T_11239 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_11239 is invalid @[Arbiter.scala 58:49] + _T_11239[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11239[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11239[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11245 : UInt<1>[3], clock with : (reset => (reset, _T_11239)) @[Reg.scala 26:44] + node _T_11255 = mux(_T_11156, _T_11181, _T_11245) @[Arbiter.scala 59:25] + _T_11245 <- _T_11255 @[Arbiter.scala 60:13] + node _T_11265 = mux(_T_11156, _T_11170, _T_11245) @[Arbiter.scala 63:26] + node _T_11275 = and(out[0].a.ready, _T_11265[0]) @[Arbiter.scala 65:33] + _T_7665[0].ready <= _T_11275 @[Arbiter.scala 65:19] + node _T_11276 = and(out[0].a.ready, _T_11265[1]) @[Arbiter.scala 65:33] + _T_7927[0].ready <= _T_11276 @[Arbiter.scala 65:19] + node _T_11277 = and(out[0].a.ready, _T_11265[2]) @[Arbiter.scala 65:33] + _T_8189[0].ready <= _T_11277 @[Arbiter.scala 65:19] + node _T_11278 = or(_T_7665[0].valid, _T_7927[0].valid) @[Arbiter.scala 71:46] + node _T_11279 = or(_T_11278, _T_8189[0].valid) @[Arbiter.scala 71:46] + node _T_11281 = mux(_T_11245[0], _T_7665[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11283 = mux(_T_11245[1], _T_7927[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11285 = mux(_T_11245[2], _T_8189[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11287 = or(_T_11281, _T_11283) @[Mux.scala 19:72] + node _T_11288 = or(_T_11287, _T_11285) @[Mux.scala 19:72] + wire _T_11290 : UInt<1> @[Mux.scala 19:72] + _T_11290 is invalid @[Mux.scala 19:72] + _T_11290 <= _T_11288 @[Mux.scala 19:72] + node _T_11291 = mux(_T_11156, _T_11279, _T_11290) @[Arbiter.scala 71:24] + out[0].a.valid <= _T_11291 @[Arbiter.scala 71:18] + node _T_11292 = cat(_T_7665[0].bits.address, _T_7665[0].bits.mask) @[Mux.scala 19:72] + node _T_11293 = cat(_T_11292, _T_7665[0].bits.data) @[Mux.scala 19:72] + node _T_11294 = cat(_T_7665[0].bits.size, _T_7665[0].bits.source) @[Mux.scala 19:72] + node _T_11295 = cat(_T_7665[0].bits.opcode, _T_7665[0].bits.param) @[Mux.scala 19:72] + node _T_11296 = cat(_T_11295, _T_11294) @[Mux.scala 19:72] + node _T_11297 = cat(_T_11296, _T_11293) @[Mux.scala 19:72] + node _T_11299 = mux(_T_11255[0], _T_11297, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11300 = cat(_T_7927[0].bits.address, _T_7927[0].bits.mask) @[Mux.scala 19:72] + node _T_11301 = cat(_T_11300, _T_7927[0].bits.data) @[Mux.scala 19:72] + node _T_11302 = cat(_T_7927[0].bits.size, _T_7927[0].bits.source) @[Mux.scala 19:72] + node _T_11303 = cat(_T_7927[0].bits.opcode, _T_7927[0].bits.param) @[Mux.scala 19:72] + node _T_11304 = cat(_T_11303, _T_11302) @[Mux.scala 19:72] + node _T_11305 = cat(_T_11304, _T_11301) @[Mux.scala 19:72] + node _T_11307 = mux(_T_11255[1], _T_11305, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11308 = cat(_T_8189[0].bits.address, _T_8189[0].bits.mask) @[Mux.scala 19:72] + node _T_11309 = cat(_T_11308, _T_8189[0].bits.data) @[Mux.scala 19:72] + node _T_11310 = cat(_T_8189[0].bits.size, _T_8189[0].bits.source) @[Mux.scala 19:72] + node _T_11311 = cat(_T_8189[0].bits.opcode, _T_8189[0].bits.param) @[Mux.scala 19:72] + node _T_11312 = cat(_T_11311, _T_11310) @[Mux.scala 19:72] + node _T_11313 = cat(_T_11312, _T_11309) @[Mux.scala 19:72] + node _T_11315 = mux(_T_11255[2], _T_11313, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11324 = or(_T_11299, _T_11307) @[Mux.scala 19:72] + node _T_11325 = or(_T_11324, _T_11315) @[Mux.scala 19:72] + wire _T_11334 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_11334 is invalid @[Mux.scala 19:72] + wire _T_11343 : UInt<117> + _T_11343 is invalid + _T_11343 <= _T_11325 + node _T_11344 = bits(_T_11343, 63, 0) @[Mux.scala 19:72] + _T_11334.data <= _T_11344 @[Mux.scala 19:72] + node _T_11345 = bits(_T_11343, 71, 64) @[Mux.scala 19:72] + _T_11334.mask <= _T_11345 @[Mux.scala 19:72] + node _T_11346 = bits(_T_11343, 103, 72) @[Mux.scala 19:72] + _T_11334.address <= _T_11346 @[Mux.scala 19:72] + node _T_11347 = bits(_T_11343, 106, 104) @[Mux.scala 19:72] + _T_11334.source <= _T_11347 @[Mux.scala 19:72] + node _T_11348 = bits(_T_11343, 110, 107) @[Mux.scala 19:72] + _T_11334.size <= _T_11348 @[Mux.scala 19:72] + node _T_11349 = bits(_T_11343, 113, 111) @[Mux.scala 19:72] + _T_11334.param <= _T_11349 @[Mux.scala 19:72] + node _T_11350 = bits(_T_11343, 116, 114) @[Mux.scala 19:72] + _T_11334.opcode <= _T_11350 @[Mux.scala 19:72] + out[0].a.bits <- _T_11334 @[Arbiter.scala 72:17] + out[0].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[0].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_11354 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11356 = eq(_T_11354, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11357 = and(_T_11356, out[1].a.ready) @[Arbiter.scala 35:24] + node _T_11360 = eq(_T_7665[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11361 = and(UInt<1>("h01"), _T_11360) @[Arbiter.scala 14:35] + node _T_11363 = eq(_T_7927[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11364 = and(_T_11361, _T_11363) @[Arbiter.scala 14:35] + node _T_11366 = eq(_T_8189[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11367 = and(_T_11364, _T_11366) @[Arbiter.scala 14:35] + wire _T_11370 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_11370 is invalid @[Arbiter.scala 40:23] + _T_11370[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_11370[1] <= _T_11361 @[Arbiter.scala 40:23] + _T_11370[2] <= _T_11364 @[Arbiter.scala 40:23] + node _T_11376 = and(_T_11370[0], _T_7665[1].valid) @[Arbiter.scala 42:65] + node _T_11377 = and(_T_11370[1], _T_7927[1].valid) @[Arbiter.scala 42:65] + node _T_11378 = and(_T_11370[2], _T_8189[1].valid) @[Arbiter.scala 42:65] + wire _T_11381 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_11381 is invalid @[Arbiter.scala 42:23] + _T_11381[0] <= _T_11376 @[Arbiter.scala 42:23] + _T_11381[1] <= _T_11377 @[Arbiter.scala 42:23] + _T_11381[2] <= _T_11378 @[Arbiter.scala 42:23] + node _T_11388 = or(UInt<1>("h00"), _T_11381[0]) @[Arbiter.scala 47:52] + node _T_11389 = or(_T_11388, _T_11381[1]) @[Arbiter.scala 47:52] + node _T_11390 = or(_T_11389, _T_11381[2]) @[Arbiter.scala 47:52] + node _T_11392 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11394 = eq(_T_11381[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11395 = or(_T_11392, _T_11394) @[Arbiter.scala 48:59] + node _T_11397 = eq(_T_11388, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11399 = eq(_T_11381[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11400 = or(_T_11397, _T_11399) @[Arbiter.scala 48:59] + node _T_11402 = eq(_T_11389, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11404 = eq(_T_11381[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11405 = or(_T_11402, _T_11404) @[Arbiter.scala 48:59] + node _T_11406 = and(_T_11395, _T_11400) @[Arbiter.scala 48:77] + node _T_11407 = and(_T_11406, _T_11405) @[Arbiter.scala 48:77] + node _T_11408 = or(_T_11407, reset) @[Arbiter.scala 48:13] + node _T_11410 = eq(_T_11408, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11410 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11411 = or(_T_7665[1].valid, _T_7927[1].valid) @[Arbiter.scala 50:31] + node _T_11412 = or(_T_11411, _T_8189[1].valid) @[Arbiter.scala 50:31] + node _T_11414 = eq(_T_11412, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11415 = or(_T_11381[0], _T_11381[1]) @[Arbiter.scala 50:54] + node _T_11416 = or(_T_11415, _T_11381[2]) @[Arbiter.scala 50:54] + node _T_11417 = or(_T_11414, _T_11416) @[Arbiter.scala 50:36] + node _T_11418 = or(_T_11417, reset) @[Arbiter.scala 50:14] + node _T_11420 = eq(_T_11418, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11420 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11422 = mux(_T_11381[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11424 = mux(_T_11381[1], beatsAI[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11426 = mux(_T_11381[2], beatsAI[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11427 = or(_T_11422, _T_11424) @[Arbiter.scala 54:44] + node _T_11428 = or(_T_11427, _T_11426) @[Arbiter.scala 54:44] + node _T_11429 = and(out[1].a.ready, out[1].a.valid) @[Decoupled.scala 30:37] + node _T_11430 = sub(_T_11354, _T_11429) @[Arbiter.scala 55:52] + node _T_11431 = asUInt(_T_11430) @[Arbiter.scala 55:52] + node _T_11432 = tail(_T_11431, 1) @[Arbiter.scala 55:52] + node _T_11433 = mux(_T_11357, _T_11428, _T_11432) @[Arbiter.scala 55:23] + _T_11354 <= _T_11433 @[Arbiter.scala 55:17] + wire _T_11439 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_11439 is invalid @[Arbiter.scala 58:49] + _T_11439[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11439[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11439[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11445 : UInt<1>[3], clock with : (reset => (reset, _T_11439)) @[Reg.scala 26:44] + node _T_11455 = mux(_T_11356, _T_11381, _T_11445) @[Arbiter.scala 59:25] + _T_11445 <- _T_11455 @[Arbiter.scala 60:13] + node _T_11465 = mux(_T_11356, _T_11370, _T_11445) @[Arbiter.scala 63:26] + node _T_11475 = and(out[1].a.ready, _T_11465[0]) @[Arbiter.scala 65:33] + _T_7665[1].ready <= _T_11475 @[Arbiter.scala 65:19] + node _T_11476 = and(out[1].a.ready, _T_11465[1]) @[Arbiter.scala 65:33] + _T_7927[1].ready <= _T_11476 @[Arbiter.scala 65:19] + node _T_11477 = and(out[1].a.ready, _T_11465[2]) @[Arbiter.scala 65:33] + _T_8189[1].ready <= _T_11477 @[Arbiter.scala 65:19] + node _T_11478 = or(_T_7665[1].valid, _T_7927[1].valid) @[Arbiter.scala 71:46] + node _T_11479 = or(_T_11478, _T_8189[1].valid) @[Arbiter.scala 71:46] + node _T_11481 = mux(_T_11445[0], _T_7665[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11483 = mux(_T_11445[1], _T_7927[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11485 = mux(_T_11445[2], _T_8189[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11487 = or(_T_11481, _T_11483) @[Mux.scala 19:72] + node _T_11488 = or(_T_11487, _T_11485) @[Mux.scala 19:72] + wire _T_11490 : UInt<1> @[Mux.scala 19:72] + _T_11490 is invalid @[Mux.scala 19:72] + _T_11490 <= _T_11488 @[Mux.scala 19:72] + node _T_11491 = mux(_T_11356, _T_11479, _T_11490) @[Arbiter.scala 71:24] + out[1].a.valid <= _T_11491 @[Arbiter.scala 71:18] + node _T_11492 = cat(_T_7665[1].bits.address, _T_7665[1].bits.mask) @[Mux.scala 19:72] + node _T_11493 = cat(_T_11492, _T_7665[1].bits.data) @[Mux.scala 19:72] + node _T_11494 = cat(_T_7665[1].bits.size, _T_7665[1].bits.source) @[Mux.scala 19:72] + node _T_11495 = cat(_T_7665[1].bits.opcode, _T_7665[1].bits.param) @[Mux.scala 19:72] + node _T_11496 = cat(_T_11495, _T_11494) @[Mux.scala 19:72] + node _T_11497 = cat(_T_11496, _T_11493) @[Mux.scala 19:72] + node _T_11499 = mux(_T_11455[0], _T_11497, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11500 = cat(_T_7927[1].bits.address, _T_7927[1].bits.mask) @[Mux.scala 19:72] + node _T_11501 = cat(_T_11500, _T_7927[1].bits.data) @[Mux.scala 19:72] + node _T_11502 = cat(_T_7927[1].bits.size, _T_7927[1].bits.source) @[Mux.scala 19:72] + node _T_11503 = cat(_T_7927[1].bits.opcode, _T_7927[1].bits.param) @[Mux.scala 19:72] + node _T_11504 = cat(_T_11503, _T_11502) @[Mux.scala 19:72] + node _T_11505 = cat(_T_11504, _T_11501) @[Mux.scala 19:72] + node _T_11507 = mux(_T_11455[1], _T_11505, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11508 = cat(_T_8189[1].bits.address, _T_8189[1].bits.mask) @[Mux.scala 19:72] + node _T_11509 = cat(_T_11508, _T_8189[1].bits.data) @[Mux.scala 19:72] + node _T_11510 = cat(_T_8189[1].bits.size, _T_8189[1].bits.source) @[Mux.scala 19:72] + node _T_11511 = cat(_T_8189[1].bits.opcode, _T_8189[1].bits.param) @[Mux.scala 19:72] + node _T_11512 = cat(_T_11511, _T_11510) @[Mux.scala 19:72] + node _T_11513 = cat(_T_11512, _T_11509) @[Mux.scala 19:72] + node _T_11515 = mux(_T_11455[2], _T_11513, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11524 = or(_T_11499, _T_11507) @[Mux.scala 19:72] + node _T_11525 = or(_T_11524, _T_11515) @[Mux.scala 19:72] + wire _T_11534 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_11534 is invalid @[Mux.scala 19:72] + wire _T_11543 : UInt<117> + _T_11543 is invalid + _T_11543 <= _T_11525 + node _T_11544 = bits(_T_11543, 63, 0) @[Mux.scala 19:72] + _T_11534.data <= _T_11544 @[Mux.scala 19:72] + node _T_11545 = bits(_T_11543, 71, 64) @[Mux.scala 19:72] + _T_11534.mask <= _T_11545 @[Mux.scala 19:72] + node _T_11546 = bits(_T_11543, 103, 72) @[Mux.scala 19:72] + _T_11534.address <= _T_11546 @[Mux.scala 19:72] + node _T_11547 = bits(_T_11543, 106, 104) @[Mux.scala 19:72] + _T_11534.source <= _T_11547 @[Mux.scala 19:72] + node _T_11548 = bits(_T_11543, 110, 107) @[Mux.scala 19:72] + _T_11534.size <= _T_11548 @[Mux.scala 19:72] + node _T_11549 = bits(_T_11543, 113, 111) @[Mux.scala 19:72] + _T_11534.param <= _T_11549 @[Mux.scala 19:72] + node _T_11550 = bits(_T_11543, 116, 114) @[Mux.scala 19:72] + _T_11534.opcode <= _T_11550 @[Mux.scala 19:72] + out[1].a.bits <- _T_11534 @[Arbiter.scala 72:17] + out[1].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[1].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_11554 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11556 = eq(_T_11554, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11557 = and(_T_11556, out[2].a.ready) @[Arbiter.scala 35:24] + node _T_11560 = eq(_T_7665[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11561 = and(UInt<1>("h01"), _T_11560) @[Arbiter.scala 14:35] + node _T_11563 = eq(_T_7927[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11564 = and(_T_11561, _T_11563) @[Arbiter.scala 14:35] + node _T_11566 = eq(_T_8189[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11567 = and(_T_11564, _T_11566) @[Arbiter.scala 14:35] + wire _T_11570 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_11570 is invalid @[Arbiter.scala 40:23] + _T_11570[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_11570[1] <= _T_11561 @[Arbiter.scala 40:23] + _T_11570[2] <= _T_11564 @[Arbiter.scala 40:23] + node _T_11576 = and(_T_11570[0], _T_7665[2].valid) @[Arbiter.scala 42:65] + node _T_11577 = and(_T_11570[1], _T_7927[2].valid) @[Arbiter.scala 42:65] + node _T_11578 = and(_T_11570[2], _T_8189[2].valid) @[Arbiter.scala 42:65] + wire _T_11581 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_11581 is invalid @[Arbiter.scala 42:23] + _T_11581[0] <= _T_11576 @[Arbiter.scala 42:23] + _T_11581[1] <= _T_11577 @[Arbiter.scala 42:23] + _T_11581[2] <= _T_11578 @[Arbiter.scala 42:23] + node _T_11588 = or(UInt<1>("h00"), _T_11581[0]) @[Arbiter.scala 47:52] + node _T_11589 = or(_T_11588, _T_11581[1]) @[Arbiter.scala 47:52] + node _T_11590 = or(_T_11589, _T_11581[2]) @[Arbiter.scala 47:52] + node _T_11592 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11594 = eq(_T_11581[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11595 = or(_T_11592, _T_11594) @[Arbiter.scala 48:59] + node _T_11597 = eq(_T_11588, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11599 = eq(_T_11581[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11600 = or(_T_11597, _T_11599) @[Arbiter.scala 48:59] + node _T_11602 = eq(_T_11589, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11604 = eq(_T_11581[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11605 = or(_T_11602, _T_11604) @[Arbiter.scala 48:59] + node _T_11606 = and(_T_11595, _T_11600) @[Arbiter.scala 48:77] + node _T_11607 = and(_T_11606, _T_11605) @[Arbiter.scala 48:77] + node _T_11608 = or(_T_11607, reset) @[Arbiter.scala 48:13] + node _T_11610 = eq(_T_11608, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11610 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11611 = or(_T_7665[2].valid, _T_7927[2].valid) @[Arbiter.scala 50:31] + node _T_11612 = or(_T_11611, _T_8189[2].valid) @[Arbiter.scala 50:31] + node _T_11614 = eq(_T_11612, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11615 = or(_T_11581[0], _T_11581[1]) @[Arbiter.scala 50:54] + node _T_11616 = or(_T_11615, _T_11581[2]) @[Arbiter.scala 50:54] + node _T_11617 = or(_T_11614, _T_11616) @[Arbiter.scala 50:36] + node _T_11618 = or(_T_11617, reset) @[Arbiter.scala 50:14] + node _T_11620 = eq(_T_11618, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11620 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11622 = mux(_T_11581[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11624 = mux(_T_11581[1], beatsAI[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11626 = mux(_T_11581[2], beatsAI[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11627 = or(_T_11622, _T_11624) @[Arbiter.scala 54:44] + node _T_11628 = or(_T_11627, _T_11626) @[Arbiter.scala 54:44] + node _T_11629 = and(out[2].a.ready, out[2].a.valid) @[Decoupled.scala 30:37] + node _T_11630 = sub(_T_11554, _T_11629) @[Arbiter.scala 55:52] + node _T_11631 = asUInt(_T_11630) @[Arbiter.scala 55:52] + node _T_11632 = tail(_T_11631, 1) @[Arbiter.scala 55:52] + node _T_11633 = mux(_T_11557, _T_11628, _T_11632) @[Arbiter.scala 55:23] + _T_11554 <= _T_11633 @[Arbiter.scala 55:17] + wire _T_11639 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_11639 is invalid @[Arbiter.scala 58:49] + _T_11639[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11639[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11639[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11645 : UInt<1>[3], clock with : (reset => (reset, _T_11639)) @[Reg.scala 26:44] + node _T_11655 = mux(_T_11556, _T_11581, _T_11645) @[Arbiter.scala 59:25] + _T_11645 <- _T_11655 @[Arbiter.scala 60:13] + node _T_11665 = mux(_T_11556, _T_11570, _T_11645) @[Arbiter.scala 63:26] + node _T_11675 = and(out[2].a.ready, _T_11665[0]) @[Arbiter.scala 65:33] + _T_7665[2].ready <= _T_11675 @[Arbiter.scala 65:19] + node _T_11676 = and(out[2].a.ready, _T_11665[1]) @[Arbiter.scala 65:33] + _T_7927[2].ready <= _T_11676 @[Arbiter.scala 65:19] + node _T_11677 = and(out[2].a.ready, _T_11665[2]) @[Arbiter.scala 65:33] + _T_8189[2].ready <= _T_11677 @[Arbiter.scala 65:19] + node _T_11678 = or(_T_7665[2].valid, _T_7927[2].valid) @[Arbiter.scala 71:46] + node _T_11679 = or(_T_11678, _T_8189[2].valid) @[Arbiter.scala 71:46] + node _T_11681 = mux(_T_11645[0], _T_7665[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11683 = mux(_T_11645[1], _T_7927[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11685 = mux(_T_11645[2], _T_8189[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11687 = or(_T_11681, _T_11683) @[Mux.scala 19:72] + node _T_11688 = or(_T_11687, _T_11685) @[Mux.scala 19:72] + wire _T_11690 : UInt<1> @[Mux.scala 19:72] + _T_11690 is invalid @[Mux.scala 19:72] + _T_11690 <= _T_11688 @[Mux.scala 19:72] + node _T_11691 = mux(_T_11556, _T_11679, _T_11690) @[Arbiter.scala 71:24] + out[2].a.valid <= _T_11691 @[Arbiter.scala 71:18] + node _T_11692 = cat(_T_7665[2].bits.address, _T_7665[2].bits.mask) @[Mux.scala 19:72] + node _T_11693 = cat(_T_11692, _T_7665[2].bits.data) @[Mux.scala 19:72] + node _T_11694 = cat(_T_7665[2].bits.size, _T_7665[2].bits.source) @[Mux.scala 19:72] + node _T_11695 = cat(_T_7665[2].bits.opcode, _T_7665[2].bits.param) @[Mux.scala 19:72] + node _T_11696 = cat(_T_11695, _T_11694) @[Mux.scala 19:72] + node _T_11697 = cat(_T_11696, _T_11693) @[Mux.scala 19:72] + node _T_11699 = mux(_T_11655[0], _T_11697, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11700 = cat(_T_7927[2].bits.address, _T_7927[2].bits.mask) @[Mux.scala 19:72] + node _T_11701 = cat(_T_11700, _T_7927[2].bits.data) @[Mux.scala 19:72] + node _T_11702 = cat(_T_7927[2].bits.size, _T_7927[2].bits.source) @[Mux.scala 19:72] + node _T_11703 = cat(_T_7927[2].bits.opcode, _T_7927[2].bits.param) @[Mux.scala 19:72] + node _T_11704 = cat(_T_11703, _T_11702) @[Mux.scala 19:72] + node _T_11705 = cat(_T_11704, _T_11701) @[Mux.scala 19:72] + node _T_11707 = mux(_T_11655[1], _T_11705, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11708 = cat(_T_8189[2].bits.address, _T_8189[2].bits.mask) @[Mux.scala 19:72] + node _T_11709 = cat(_T_11708, _T_8189[2].bits.data) @[Mux.scala 19:72] + node _T_11710 = cat(_T_8189[2].bits.size, _T_8189[2].bits.source) @[Mux.scala 19:72] + node _T_11711 = cat(_T_8189[2].bits.opcode, _T_8189[2].bits.param) @[Mux.scala 19:72] + node _T_11712 = cat(_T_11711, _T_11710) @[Mux.scala 19:72] + node _T_11713 = cat(_T_11712, _T_11709) @[Mux.scala 19:72] + node _T_11715 = mux(_T_11655[2], _T_11713, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_11724 = or(_T_11699, _T_11707) @[Mux.scala 19:72] + node _T_11725 = or(_T_11724, _T_11715) @[Mux.scala 19:72] + wire _T_11734 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_11734 is invalid @[Mux.scala 19:72] + wire _T_11743 : UInt<117> + _T_11743 is invalid + _T_11743 <= _T_11725 + node _T_11744 = bits(_T_11743, 63, 0) @[Mux.scala 19:72] + _T_11734.data <= _T_11744 @[Mux.scala 19:72] + node _T_11745 = bits(_T_11743, 71, 64) @[Mux.scala 19:72] + _T_11734.mask <= _T_11745 @[Mux.scala 19:72] + node _T_11746 = bits(_T_11743, 103, 72) @[Mux.scala 19:72] + _T_11734.address <= _T_11746 @[Mux.scala 19:72] + node _T_11747 = bits(_T_11743, 106, 104) @[Mux.scala 19:72] + _T_11734.source <= _T_11747 @[Mux.scala 19:72] + node _T_11748 = bits(_T_11743, 110, 107) @[Mux.scala 19:72] + _T_11734.size <= _T_11748 @[Mux.scala 19:72] + node _T_11749 = bits(_T_11743, 113, 111) @[Mux.scala 19:72] + _T_11734.param <= _T_11749 @[Mux.scala 19:72] + node _T_11750 = bits(_T_11743, 116, 114) @[Mux.scala 19:72] + _T_11734.opcode <= _T_11750 @[Mux.scala 19:72] + out[2].a.bits <- _T_11734 @[Arbiter.scala 72:17] + reg _T_11752 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11754 = eq(_T_11752, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11755 = and(_T_11754, out[2].c.ready) @[Arbiter.scala 35:24] + node _T_11758 = eq(_T_9499[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11759 = and(UInt<1>("h01"), _T_11758) @[Arbiter.scala 14:35] + wire _T_11762 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_11762 is invalid @[Arbiter.scala 40:23] + _T_11762[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_11766 = and(_T_11762[0], _T_9499[2].valid) @[Arbiter.scala 42:65] + wire _T_11769 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_11769 is invalid @[Arbiter.scala 42:23] + _T_11769[0] <= _T_11766 @[Arbiter.scala 42:23] + node _T_11774 = or(UInt<1>("h00"), _T_11769[0]) @[Arbiter.scala 47:52] + node _T_11776 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11778 = eq(_T_11769[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11779 = or(_T_11776, _T_11778) @[Arbiter.scala 48:59] + node _T_11780 = or(_T_11779, reset) @[Arbiter.scala 48:13] + node _T_11782 = eq(_T_11780, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11782 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11784 = eq(_T_9499[2].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11785 = or(_T_11784, _T_11769[0]) @[Arbiter.scala 50:36] + node _T_11786 = or(_T_11785, reset) @[Arbiter.scala 50:14] + node _T_11788 = eq(_T_11786, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11788 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11790 = mux(_T_11769[0], beatsCI[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11791 = and(out[2].c.ready, out[2].c.valid) @[Decoupled.scala 30:37] + node _T_11792 = sub(_T_11752, _T_11791) @[Arbiter.scala 55:52] + node _T_11793 = asUInt(_T_11792) @[Arbiter.scala 55:52] + node _T_11794 = tail(_T_11793, 1) @[Arbiter.scala 55:52] + node _T_11795 = mux(_T_11755, _T_11790, _T_11794) @[Arbiter.scala 55:23] + _T_11752 <= _T_11795 @[Arbiter.scala 55:17] + wire _T_11799 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_11799 is invalid @[Arbiter.scala 58:49] + _T_11799[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11803 : UInt<1>[1], clock with : (reset => (reset, _T_11799)) @[Reg.scala 26:44] + node _T_11809 = mux(_T_11754, _T_11769, _T_11803) @[Arbiter.scala 59:25] + _T_11803 <- _T_11809 @[Arbiter.scala 60:13] + _T_9499[2].ready <= out[2].c.ready @[Arbiter.scala 68:28] + node _T_11815 = mux(_T_11754, _T_9499[2].valid, _T_9499[2].valid) @[Arbiter.scala 71:24] + out[2].c.valid <= _T_11815 @[Arbiter.scala 71:18] + out[2].c.bits <- _T_9499[2].bits @[Arbiter.scala 72:17] + reg _T_11817 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11819 = eq(_T_11817, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11820 = and(_T_11819, out[2].e.ready) @[Arbiter.scala 35:24] + node _T_11823 = eq(_T_10951[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11824 = and(UInt<1>("h01"), _T_11823) @[Arbiter.scala 14:35] + wire _T_11827 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_11827 is invalid @[Arbiter.scala 40:23] + _T_11827[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_11831 = and(_T_11827[0], _T_10951[2].valid) @[Arbiter.scala 42:65] + wire _T_11834 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_11834 is invalid @[Arbiter.scala 42:23] + _T_11834[0] <= _T_11831 @[Arbiter.scala 42:23] + node _T_11839 = or(UInt<1>("h00"), _T_11834[0]) @[Arbiter.scala 47:52] + node _T_11841 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11843 = eq(_T_11834[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11844 = or(_T_11841, _T_11843) @[Arbiter.scala 48:59] + node _T_11845 = or(_T_11844, reset) @[Arbiter.scala 48:13] + node _T_11847 = eq(_T_11845, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11847 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11849 = eq(_T_10951[2].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11850 = or(_T_11849, _T_11834[0]) @[Arbiter.scala 50:36] + node _T_11851 = or(_T_11850, reset) @[Arbiter.scala 50:14] + node _T_11853 = eq(_T_11851, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11853 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11855 = mux(_T_11834[0], beatsEI[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11856 = and(out[2].e.ready, out[2].e.valid) @[Decoupled.scala 30:37] + node _T_11857 = sub(_T_11817, _T_11856) @[Arbiter.scala 55:52] + node _T_11858 = asUInt(_T_11857) @[Arbiter.scala 55:52] + node _T_11859 = tail(_T_11858, 1) @[Arbiter.scala 55:52] + node _T_11860 = mux(_T_11820, _T_11855, _T_11859) @[Arbiter.scala 55:23] + _T_11817 <= _T_11860 @[Arbiter.scala 55:17] + wire _T_11864 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_11864 is invalid @[Arbiter.scala 58:49] + _T_11864[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11868 : UInt<1>[1], clock with : (reset => (reset, _T_11864)) @[Reg.scala 26:44] + node _T_11874 = mux(_T_11819, _T_11834, _T_11868) @[Arbiter.scala 59:25] + _T_11868 <- _T_11874 @[Arbiter.scala 60:13] + _T_10951[2].ready <= out[2].e.ready @[Arbiter.scala 68:28] + node _T_11880 = mux(_T_11819, _T_10951[2].valid, _T_10951[2].valid) @[Arbiter.scala 71:24] + out[2].e.valid <= _T_11880 @[Arbiter.scala 71:18] + out[2].e.bits <- _T_10951[2].bits @[Arbiter.scala 72:17] + in[0].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_11883 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_11885 = eq(_T_11883, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_11886 = and(_T_11885, in[0].d.ready) @[Arbiter.scala 35:24] + node _T_11889 = eq(_T_10031[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11890 = and(UInt<1>("h01"), _T_11889) @[Arbiter.scala 14:35] + node _T_11892 = eq(_T_10317[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11893 = and(_T_11890, _T_11892) @[Arbiter.scala 14:35] + node _T_11895 = eq(_T_10603[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_11896 = and(_T_11893, _T_11895) @[Arbiter.scala 14:35] + wire _T_11899 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_11899 is invalid @[Arbiter.scala 40:23] + _T_11899[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_11899[1] <= _T_11890 @[Arbiter.scala 40:23] + _T_11899[2] <= _T_11893 @[Arbiter.scala 40:23] + node _T_11905 = and(_T_11899[0], _T_10031[0].valid) @[Arbiter.scala 42:65] + node _T_11906 = and(_T_11899[1], _T_10317[0].valid) @[Arbiter.scala 42:65] + node _T_11907 = and(_T_11899[2], _T_10603[0].valid) @[Arbiter.scala 42:65] + wire _T_11910 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_11910 is invalid @[Arbiter.scala 42:23] + _T_11910[0] <= _T_11905 @[Arbiter.scala 42:23] + _T_11910[1] <= _T_11906 @[Arbiter.scala 42:23] + _T_11910[2] <= _T_11907 @[Arbiter.scala 42:23] + node _T_11917 = or(UInt<1>("h00"), _T_11910[0]) @[Arbiter.scala 47:52] + node _T_11918 = or(_T_11917, _T_11910[1]) @[Arbiter.scala 47:52] + node _T_11919 = or(_T_11918, _T_11910[2]) @[Arbiter.scala 47:52] + node _T_11921 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11923 = eq(_T_11910[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11924 = or(_T_11921, _T_11923) @[Arbiter.scala 48:59] + node _T_11926 = eq(_T_11917, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11928 = eq(_T_11910[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11929 = or(_T_11926, _T_11928) @[Arbiter.scala 48:59] + node _T_11931 = eq(_T_11918, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_11933 = eq(_T_11910[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_11934 = or(_T_11931, _T_11933) @[Arbiter.scala 48:59] + node _T_11935 = and(_T_11924, _T_11929) @[Arbiter.scala 48:77] + node _T_11936 = and(_T_11935, _T_11934) @[Arbiter.scala 48:77] + node _T_11937 = or(_T_11936, reset) @[Arbiter.scala 48:13] + node _T_11939 = eq(_T_11937, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_11939 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_11940 = or(_T_10031[0].valid, _T_10317[0].valid) @[Arbiter.scala 50:31] + node _T_11941 = or(_T_11940, _T_10603[0].valid) @[Arbiter.scala 50:31] + node _T_11943 = eq(_T_11941, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_11944 = or(_T_11910[0], _T_11910[1]) @[Arbiter.scala 50:54] + node _T_11945 = or(_T_11944, _T_11910[2]) @[Arbiter.scala 50:54] + node _T_11946 = or(_T_11943, _T_11945) @[Arbiter.scala 50:36] + node _T_11947 = or(_T_11946, reset) @[Arbiter.scala 50:14] + node _T_11949 = eq(_T_11947, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_11949 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_11951 = mux(_T_11910[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11953 = mux(_T_11910[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11955 = mux(_T_11910[2], beatsDO[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_11956 = or(_T_11951, _T_11953) @[Arbiter.scala 54:44] + node _T_11957 = or(_T_11956, _T_11955) @[Arbiter.scala 54:44] + node _T_11958 = and(in[0].d.ready, in[0].d.valid) @[Decoupled.scala 30:37] + node _T_11959 = sub(_T_11883, _T_11958) @[Arbiter.scala 55:52] + node _T_11960 = asUInt(_T_11959) @[Arbiter.scala 55:52] + node _T_11961 = tail(_T_11960, 1) @[Arbiter.scala 55:52] + node _T_11962 = mux(_T_11886, _T_11957, _T_11961) @[Arbiter.scala 55:23] + _T_11883 <= _T_11962 @[Arbiter.scala 55:17] + wire _T_11968 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_11968 is invalid @[Arbiter.scala 58:49] + _T_11968[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11968[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_11968[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_11974 : UInt<1>[3], clock with : (reset => (reset, _T_11968)) @[Reg.scala 26:44] + node _T_11984 = mux(_T_11885, _T_11910, _T_11974) @[Arbiter.scala 59:25] + _T_11974 <- _T_11984 @[Arbiter.scala 60:13] + node _T_11994 = mux(_T_11885, _T_11899, _T_11974) @[Arbiter.scala 63:26] + node _T_12004 = and(in[0].d.ready, _T_11994[0]) @[Arbiter.scala 65:33] + _T_10031[0].ready <= _T_12004 @[Arbiter.scala 65:19] + node _T_12005 = and(in[0].d.ready, _T_11994[1]) @[Arbiter.scala 65:33] + _T_10317[0].ready <= _T_12005 @[Arbiter.scala 65:19] + node _T_12006 = and(in[0].d.ready, _T_11994[2]) @[Arbiter.scala 65:33] + _T_10603[0].ready <= _T_12006 @[Arbiter.scala 65:19] + node _T_12007 = or(_T_10031[0].valid, _T_10317[0].valid) @[Arbiter.scala 71:46] + node _T_12008 = or(_T_12007, _T_10603[0].valid) @[Arbiter.scala 71:46] + node _T_12010 = mux(_T_11974[0], _T_10031[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12012 = mux(_T_11974[1], _T_10317[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12014 = mux(_T_11974[2], _T_10603[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12016 = or(_T_12010, _T_12012) @[Mux.scala 19:72] + node _T_12017 = or(_T_12016, _T_12014) @[Mux.scala 19:72] + wire _T_12019 : UInt<1> @[Mux.scala 19:72] + _T_12019 is invalid @[Mux.scala 19:72] + _T_12019 <= _T_12017 @[Mux.scala 19:72] + node _T_12020 = mux(_T_11885, _T_12008, _T_12019) @[Arbiter.scala 71:24] + in[0].d.valid <= _T_12020 @[Arbiter.scala 71:18] + node _T_12021 = cat(_T_10031[0].bits.data, _T_10031[0].bits.error) @[Mux.scala 19:72] + node _T_12022 = cat(_T_10031[0].bits.sink, _T_10031[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_12023 = cat(_T_12022, _T_12021) @[Mux.scala 19:72] + node _T_12024 = cat(_T_10031[0].bits.size, _T_10031[0].bits.source) @[Mux.scala 19:72] + node _T_12025 = cat(_T_10031[0].bits.opcode, _T_10031[0].bits.param) @[Mux.scala 19:72] + node _T_12026 = cat(_T_12025, _T_12024) @[Mux.scala 19:72] + node _T_12027 = cat(_T_12026, _T_12023) @[Mux.scala 19:72] + node _T_12029 = mux(_T_11984[0], _T_12027, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12030 = cat(_T_10317[0].bits.data, _T_10317[0].bits.error) @[Mux.scala 19:72] + node _T_12031 = cat(_T_10317[0].bits.sink, _T_10317[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_12032 = cat(_T_12031, _T_12030) @[Mux.scala 19:72] + node _T_12033 = cat(_T_10317[0].bits.size, _T_10317[0].bits.source) @[Mux.scala 19:72] + node _T_12034 = cat(_T_10317[0].bits.opcode, _T_10317[0].bits.param) @[Mux.scala 19:72] + node _T_12035 = cat(_T_12034, _T_12033) @[Mux.scala 19:72] + node _T_12036 = cat(_T_12035, _T_12032) @[Mux.scala 19:72] + node _T_12038 = mux(_T_11984[1], _T_12036, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12039 = cat(_T_10603[0].bits.data, _T_10603[0].bits.error) @[Mux.scala 19:72] + node _T_12040 = cat(_T_10603[0].bits.sink, _T_10603[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_12041 = cat(_T_12040, _T_12039) @[Mux.scala 19:72] + node _T_12042 = cat(_T_10603[0].bits.size, _T_10603[0].bits.source) @[Mux.scala 19:72] + node _T_12043 = cat(_T_10603[0].bits.opcode, _T_10603[0].bits.param) @[Mux.scala 19:72] + node _T_12044 = cat(_T_12043, _T_12042) @[Mux.scala 19:72] + node _T_12045 = cat(_T_12044, _T_12041) @[Mux.scala 19:72] + node _T_12047 = mux(_T_11984[2], _T_12045, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12057 = or(_T_12029, _T_12038) @[Mux.scala 19:72] + node _T_12058 = or(_T_12057, _T_12047) @[Mux.scala 19:72] + wire _T_12068 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_12068 is invalid @[Mux.scala 19:72] + wire _T_12078 : UInt<84> + _T_12078 is invalid + _T_12078 <= _T_12058 + node _T_12079 = bits(_T_12078, 0, 0) @[Mux.scala 19:72] + _T_12068.error <= _T_12079 @[Mux.scala 19:72] + node _T_12080 = bits(_T_12078, 64, 1) @[Mux.scala 19:72] + _T_12068.data <= _T_12080 @[Mux.scala 19:72] + node _T_12081 = bits(_T_12078, 67, 65) @[Mux.scala 19:72] + _T_12068.addr_lo <= _T_12081 @[Mux.scala 19:72] + node _T_12082 = bits(_T_12078, 71, 68) @[Mux.scala 19:72] + _T_12068.sink <= _T_12082 @[Mux.scala 19:72] + node _T_12083 = bits(_T_12078, 74, 72) @[Mux.scala 19:72] + _T_12068.source <= _T_12083 @[Mux.scala 19:72] + node _T_12084 = bits(_T_12078, 78, 75) @[Mux.scala 19:72] + _T_12068.size <= _T_12084 @[Mux.scala 19:72] + node _T_12085 = bits(_T_12078, 80, 79) @[Mux.scala 19:72] + _T_12068.param <= _T_12085 @[Mux.scala 19:72] + node _T_12086 = bits(_T_12078, 83, 81) @[Mux.scala 19:72] + _T_12068.opcode <= _T_12086 @[Mux.scala 19:72] + in[0].d.bits <- _T_12068 @[Arbiter.scala 72:17] + reg _T_12088 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_12090 = eq(_T_12088, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_12091 = and(_T_12090, in[1].b.ready) @[Arbiter.scala 35:24] + node _T_12094 = eq(_T_8975[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12095 = and(UInt<1>("h01"), _T_12094) @[Arbiter.scala 14:35] + wire _T_12098 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_12098 is invalid @[Arbiter.scala 40:23] + _T_12098[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_12102 = and(_T_12098[0], _T_8975[1].valid) @[Arbiter.scala 42:65] + wire _T_12105 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_12105 is invalid @[Arbiter.scala 42:23] + _T_12105[0] <= _T_12102 @[Arbiter.scala 42:23] + node _T_12110 = or(UInt<1>("h00"), _T_12105[0]) @[Arbiter.scala 47:52] + node _T_12112 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12114 = eq(_T_12105[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12115 = or(_T_12112, _T_12114) @[Arbiter.scala 48:59] + node _T_12116 = or(_T_12115, reset) @[Arbiter.scala 48:13] + node _T_12118 = eq(_T_12116, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_12118 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_12120 = eq(_T_8975[1].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_12121 = or(_T_12120, _T_12105[0]) @[Arbiter.scala 50:36] + node _T_12122 = or(_T_12121, reset) @[Arbiter.scala 50:14] + node _T_12124 = eq(_T_12122, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_12124 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_12126 = mux(_T_12105[0], beatsBO[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12127 = and(in[1].b.ready, in[1].b.valid) @[Decoupled.scala 30:37] + node _T_12128 = sub(_T_12088, _T_12127) @[Arbiter.scala 55:52] + node _T_12129 = asUInt(_T_12128) @[Arbiter.scala 55:52] + node _T_12130 = tail(_T_12129, 1) @[Arbiter.scala 55:52] + node _T_12131 = mux(_T_12091, _T_12126, _T_12130) @[Arbiter.scala 55:23] + _T_12088 <= _T_12131 @[Arbiter.scala 55:17] + wire _T_12135 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_12135 is invalid @[Arbiter.scala 58:49] + _T_12135[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_12139 : UInt<1>[1], clock with : (reset => (reset, _T_12135)) @[Reg.scala 26:44] + node _T_12145 = mux(_T_12090, _T_12105, _T_12139) @[Arbiter.scala 59:25] + _T_12139 <- _T_12145 @[Arbiter.scala 60:13] + _T_8975[1].ready <= in[1].b.ready @[Arbiter.scala 68:28] + node _T_12151 = mux(_T_12090, _T_8975[1].valid, _T_8975[1].valid) @[Arbiter.scala 71:24] + in[1].b.valid <= _T_12151 @[Arbiter.scala 71:18] + in[1].b.bits <- _T_8975[1].bits @[Arbiter.scala 72:17] + reg _T_12153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_12155 = eq(_T_12153, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_12156 = and(_T_12155, in[1].d.ready) @[Arbiter.scala 35:24] + node _T_12159 = eq(_T_10031[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12160 = and(UInt<1>("h01"), _T_12159) @[Arbiter.scala 14:35] + node _T_12162 = eq(_T_10317[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12163 = and(_T_12160, _T_12162) @[Arbiter.scala 14:35] + node _T_12165 = eq(_T_10603[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12166 = and(_T_12163, _T_12165) @[Arbiter.scala 14:35] + wire _T_12169 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_12169 is invalid @[Arbiter.scala 40:23] + _T_12169[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_12169[1] <= _T_12160 @[Arbiter.scala 40:23] + _T_12169[2] <= _T_12163 @[Arbiter.scala 40:23] + node _T_12175 = and(_T_12169[0], _T_10031[1].valid) @[Arbiter.scala 42:65] + node _T_12176 = and(_T_12169[1], _T_10317[1].valid) @[Arbiter.scala 42:65] + node _T_12177 = and(_T_12169[2], _T_10603[1].valid) @[Arbiter.scala 42:65] + wire _T_12180 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_12180 is invalid @[Arbiter.scala 42:23] + _T_12180[0] <= _T_12175 @[Arbiter.scala 42:23] + _T_12180[1] <= _T_12176 @[Arbiter.scala 42:23] + _T_12180[2] <= _T_12177 @[Arbiter.scala 42:23] + node _T_12187 = or(UInt<1>("h00"), _T_12180[0]) @[Arbiter.scala 47:52] + node _T_12188 = or(_T_12187, _T_12180[1]) @[Arbiter.scala 47:52] + node _T_12189 = or(_T_12188, _T_12180[2]) @[Arbiter.scala 47:52] + node _T_12191 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12193 = eq(_T_12180[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12194 = or(_T_12191, _T_12193) @[Arbiter.scala 48:59] + node _T_12196 = eq(_T_12187, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12198 = eq(_T_12180[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12199 = or(_T_12196, _T_12198) @[Arbiter.scala 48:59] + node _T_12201 = eq(_T_12188, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12203 = eq(_T_12180[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12204 = or(_T_12201, _T_12203) @[Arbiter.scala 48:59] + node _T_12205 = and(_T_12194, _T_12199) @[Arbiter.scala 48:77] + node _T_12206 = and(_T_12205, _T_12204) @[Arbiter.scala 48:77] + node _T_12207 = or(_T_12206, reset) @[Arbiter.scala 48:13] + node _T_12209 = eq(_T_12207, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_12209 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_12210 = or(_T_10031[1].valid, _T_10317[1].valid) @[Arbiter.scala 50:31] + node _T_12211 = or(_T_12210, _T_10603[1].valid) @[Arbiter.scala 50:31] + node _T_12213 = eq(_T_12211, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_12214 = or(_T_12180[0], _T_12180[1]) @[Arbiter.scala 50:54] + node _T_12215 = or(_T_12214, _T_12180[2]) @[Arbiter.scala 50:54] + node _T_12216 = or(_T_12213, _T_12215) @[Arbiter.scala 50:36] + node _T_12217 = or(_T_12216, reset) @[Arbiter.scala 50:14] + node _T_12219 = eq(_T_12217, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_12219 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_12221 = mux(_T_12180[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12223 = mux(_T_12180[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12225 = mux(_T_12180[2], beatsDO[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12226 = or(_T_12221, _T_12223) @[Arbiter.scala 54:44] + node _T_12227 = or(_T_12226, _T_12225) @[Arbiter.scala 54:44] + node _T_12228 = and(in[1].d.ready, in[1].d.valid) @[Decoupled.scala 30:37] + node _T_12229 = sub(_T_12153, _T_12228) @[Arbiter.scala 55:52] + node _T_12230 = asUInt(_T_12229) @[Arbiter.scala 55:52] + node _T_12231 = tail(_T_12230, 1) @[Arbiter.scala 55:52] + node _T_12232 = mux(_T_12156, _T_12227, _T_12231) @[Arbiter.scala 55:23] + _T_12153 <= _T_12232 @[Arbiter.scala 55:17] + wire _T_12238 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_12238 is invalid @[Arbiter.scala 58:49] + _T_12238[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_12238[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_12238[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_12244 : UInt<1>[3], clock with : (reset => (reset, _T_12238)) @[Reg.scala 26:44] + node _T_12254 = mux(_T_12155, _T_12180, _T_12244) @[Arbiter.scala 59:25] + _T_12244 <- _T_12254 @[Arbiter.scala 60:13] + node _T_12264 = mux(_T_12155, _T_12169, _T_12244) @[Arbiter.scala 63:26] + node _T_12274 = and(in[1].d.ready, _T_12264[0]) @[Arbiter.scala 65:33] + _T_10031[1].ready <= _T_12274 @[Arbiter.scala 65:19] + node _T_12275 = and(in[1].d.ready, _T_12264[1]) @[Arbiter.scala 65:33] + _T_10317[1].ready <= _T_12275 @[Arbiter.scala 65:19] + node _T_12276 = and(in[1].d.ready, _T_12264[2]) @[Arbiter.scala 65:33] + _T_10603[1].ready <= _T_12276 @[Arbiter.scala 65:19] + node _T_12277 = or(_T_10031[1].valid, _T_10317[1].valid) @[Arbiter.scala 71:46] + node _T_12278 = or(_T_12277, _T_10603[1].valid) @[Arbiter.scala 71:46] + node _T_12280 = mux(_T_12244[0], _T_10031[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12282 = mux(_T_12244[1], _T_10317[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12284 = mux(_T_12244[2], _T_10603[1].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12286 = or(_T_12280, _T_12282) @[Mux.scala 19:72] + node _T_12287 = or(_T_12286, _T_12284) @[Mux.scala 19:72] + wire _T_12289 : UInt<1> @[Mux.scala 19:72] + _T_12289 is invalid @[Mux.scala 19:72] + _T_12289 <= _T_12287 @[Mux.scala 19:72] + node _T_12290 = mux(_T_12155, _T_12278, _T_12289) @[Arbiter.scala 71:24] + in[1].d.valid <= _T_12290 @[Arbiter.scala 71:18] + node _T_12291 = cat(_T_10031[1].bits.data, _T_10031[1].bits.error) @[Mux.scala 19:72] + node _T_12292 = cat(_T_10031[1].bits.sink, _T_10031[1].bits.addr_lo) @[Mux.scala 19:72] + node _T_12293 = cat(_T_12292, _T_12291) @[Mux.scala 19:72] + node _T_12294 = cat(_T_10031[1].bits.size, _T_10031[1].bits.source) @[Mux.scala 19:72] + node _T_12295 = cat(_T_10031[1].bits.opcode, _T_10031[1].bits.param) @[Mux.scala 19:72] + node _T_12296 = cat(_T_12295, _T_12294) @[Mux.scala 19:72] + node _T_12297 = cat(_T_12296, _T_12293) @[Mux.scala 19:72] + node _T_12299 = mux(_T_12254[0], _T_12297, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12300 = cat(_T_10317[1].bits.data, _T_10317[1].bits.error) @[Mux.scala 19:72] + node _T_12301 = cat(_T_10317[1].bits.sink, _T_10317[1].bits.addr_lo) @[Mux.scala 19:72] + node _T_12302 = cat(_T_12301, _T_12300) @[Mux.scala 19:72] + node _T_12303 = cat(_T_10317[1].bits.size, _T_10317[1].bits.source) @[Mux.scala 19:72] + node _T_12304 = cat(_T_10317[1].bits.opcode, _T_10317[1].bits.param) @[Mux.scala 19:72] + node _T_12305 = cat(_T_12304, _T_12303) @[Mux.scala 19:72] + node _T_12306 = cat(_T_12305, _T_12302) @[Mux.scala 19:72] + node _T_12308 = mux(_T_12254[1], _T_12306, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12309 = cat(_T_10603[1].bits.data, _T_10603[1].bits.error) @[Mux.scala 19:72] + node _T_12310 = cat(_T_10603[1].bits.sink, _T_10603[1].bits.addr_lo) @[Mux.scala 19:72] + node _T_12311 = cat(_T_12310, _T_12309) @[Mux.scala 19:72] + node _T_12312 = cat(_T_10603[1].bits.size, _T_10603[1].bits.source) @[Mux.scala 19:72] + node _T_12313 = cat(_T_10603[1].bits.opcode, _T_10603[1].bits.param) @[Mux.scala 19:72] + node _T_12314 = cat(_T_12313, _T_12312) @[Mux.scala 19:72] + node _T_12315 = cat(_T_12314, _T_12311) @[Mux.scala 19:72] + node _T_12317 = mux(_T_12254[2], _T_12315, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12327 = or(_T_12299, _T_12308) @[Mux.scala 19:72] + node _T_12328 = or(_T_12327, _T_12317) @[Mux.scala 19:72] + wire _T_12338 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_12338 is invalid @[Mux.scala 19:72] + wire _T_12348 : UInt<84> + _T_12348 is invalid + _T_12348 <= _T_12328 + node _T_12349 = bits(_T_12348, 0, 0) @[Mux.scala 19:72] + _T_12338.error <= _T_12349 @[Mux.scala 19:72] + node _T_12350 = bits(_T_12348, 64, 1) @[Mux.scala 19:72] + _T_12338.data <= _T_12350 @[Mux.scala 19:72] + node _T_12351 = bits(_T_12348, 67, 65) @[Mux.scala 19:72] + _T_12338.addr_lo <= _T_12351 @[Mux.scala 19:72] + node _T_12352 = bits(_T_12348, 71, 68) @[Mux.scala 19:72] + _T_12338.sink <= _T_12352 @[Mux.scala 19:72] + node _T_12353 = bits(_T_12348, 74, 72) @[Mux.scala 19:72] + _T_12338.source <= _T_12353 @[Mux.scala 19:72] + node _T_12354 = bits(_T_12348, 78, 75) @[Mux.scala 19:72] + _T_12338.size <= _T_12354 @[Mux.scala 19:72] + node _T_12355 = bits(_T_12348, 80, 79) @[Mux.scala 19:72] + _T_12338.param <= _T_12355 @[Mux.scala 19:72] + node _T_12356 = bits(_T_12348, 83, 81) @[Mux.scala 19:72] + _T_12338.opcode <= _T_12356 @[Mux.scala 19:72] + in[1].d.bits <- _T_12338 @[Arbiter.scala 72:17] + in[2].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_12359 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_12361 = eq(_T_12359, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_12362 = and(_T_12361, in[2].d.ready) @[Arbiter.scala 35:24] + node _T_12365 = eq(_T_10031[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12366 = and(UInt<1>("h01"), _T_12365) @[Arbiter.scala 14:35] + node _T_12368 = eq(_T_10317[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12369 = and(_T_12366, _T_12368) @[Arbiter.scala 14:35] + node _T_12371 = eq(_T_10603[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_12372 = and(_T_12369, _T_12371) @[Arbiter.scala 14:35] + wire _T_12375 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_12375 is invalid @[Arbiter.scala 40:23] + _T_12375[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_12375[1] <= _T_12366 @[Arbiter.scala 40:23] + _T_12375[2] <= _T_12369 @[Arbiter.scala 40:23] + node _T_12381 = and(_T_12375[0], _T_10031[2].valid) @[Arbiter.scala 42:65] + node _T_12382 = and(_T_12375[1], _T_10317[2].valid) @[Arbiter.scala 42:65] + node _T_12383 = and(_T_12375[2], _T_10603[2].valid) @[Arbiter.scala 42:65] + wire _T_12386 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_12386 is invalid @[Arbiter.scala 42:23] + _T_12386[0] <= _T_12381 @[Arbiter.scala 42:23] + _T_12386[1] <= _T_12382 @[Arbiter.scala 42:23] + _T_12386[2] <= _T_12383 @[Arbiter.scala 42:23] + node _T_12393 = or(UInt<1>("h00"), _T_12386[0]) @[Arbiter.scala 47:52] + node _T_12394 = or(_T_12393, _T_12386[1]) @[Arbiter.scala 47:52] + node _T_12395 = or(_T_12394, _T_12386[2]) @[Arbiter.scala 47:52] + node _T_12397 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12399 = eq(_T_12386[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12400 = or(_T_12397, _T_12399) @[Arbiter.scala 48:59] + node _T_12402 = eq(_T_12393, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12404 = eq(_T_12386[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12405 = or(_T_12402, _T_12404) @[Arbiter.scala 48:59] + node _T_12407 = eq(_T_12394, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_12409 = eq(_T_12386[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_12410 = or(_T_12407, _T_12409) @[Arbiter.scala 48:59] + node _T_12411 = and(_T_12400, _T_12405) @[Arbiter.scala 48:77] + node _T_12412 = and(_T_12411, _T_12410) @[Arbiter.scala 48:77] + node _T_12413 = or(_T_12412, reset) @[Arbiter.scala 48:13] + node _T_12415 = eq(_T_12413, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_12415 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_12416 = or(_T_10031[2].valid, _T_10317[2].valid) @[Arbiter.scala 50:31] + node _T_12417 = or(_T_12416, _T_10603[2].valid) @[Arbiter.scala 50:31] + node _T_12419 = eq(_T_12417, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_12420 = or(_T_12386[0], _T_12386[1]) @[Arbiter.scala 50:54] + node _T_12421 = or(_T_12420, _T_12386[2]) @[Arbiter.scala 50:54] + node _T_12422 = or(_T_12419, _T_12421) @[Arbiter.scala 50:36] + node _T_12423 = or(_T_12422, reset) @[Arbiter.scala 50:14] + node _T_12425 = eq(_T_12423, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_12425 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_12427 = mux(_T_12386[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12429 = mux(_T_12386[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12431 = mux(_T_12386[2], beatsDO[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_12432 = or(_T_12427, _T_12429) @[Arbiter.scala 54:44] + node _T_12433 = or(_T_12432, _T_12431) @[Arbiter.scala 54:44] + node _T_12434 = and(in[2].d.ready, in[2].d.valid) @[Decoupled.scala 30:37] + node _T_12435 = sub(_T_12359, _T_12434) @[Arbiter.scala 55:52] + node _T_12436 = asUInt(_T_12435) @[Arbiter.scala 55:52] + node _T_12437 = tail(_T_12436, 1) @[Arbiter.scala 55:52] + node _T_12438 = mux(_T_12362, _T_12433, _T_12437) @[Arbiter.scala 55:23] + _T_12359 <= _T_12438 @[Arbiter.scala 55:17] + wire _T_12444 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_12444 is invalid @[Arbiter.scala 58:49] + _T_12444[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_12444[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_12444[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_12450 : UInt<1>[3], clock with : (reset => (reset, _T_12444)) @[Reg.scala 26:44] + node _T_12460 = mux(_T_12361, _T_12386, _T_12450) @[Arbiter.scala 59:25] + _T_12450 <- _T_12460 @[Arbiter.scala 60:13] + node _T_12470 = mux(_T_12361, _T_12375, _T_12450) @[Arbiter.scala 63:26] + node _T_12480 = and(in[2].d.ready, _T_12470[0]) @[Arbiter.scala 65:33] + _T_10031[2].ready <= _T_12480 @[Arbiter.scala 65:19] + node _T_12481 = and(in[2].d.ready, _T_12470[1]) @[Arbiter.scala 65:33] + _T_10317[2].ready <= _T_12481 @[Arbiter.scala 65:19] + node _T_12482 = and(in[2].d.ready, _T_12470[2]) @[Arbiter.scala 65:33] + _T_10603[2].ready <= _T_12482 @[Arbiter.scala 65:19] + node _T_12483 = or(_T_10031[2].valid, _T_10317[2].valid) @[Arbiter.scala 71:46] + node _T_12484 = or(_T_12483, _T_10603[2].valid) @[Arbiter.scala 71:46] + node _T_12486 = mux(_T_12450[0], _T_10031[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12488 = mux(_T_12450[1], _T_10317[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12490 = mux(_T_12450[2], _T_10603[2].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12492 = or(_T_12486, _T_12488) @[Mux.scala 19:72] + node _T_12493 = or(_T_12492, _T_12490) @[Mux.scala 19:72] + wire _T_12495 : UInt<1> @[Mux.scala 19:72] + _T_12495 is invalid @[Mux.scala 19:72] + _T_12495 <= _T_12493 @[Mux.scala 19:72] + node _T_12496 = mux(_T_12361, _T_12484, _T_12495) @[Arbiter.scala 71:24] + in[2].d.valid <= _T_12496 @[Arbiter.scala 71:18] + node _T_12497 = cat(_T_10031[2].bits.data, _T_10031[2].bits.error) @[Mux.scala 19:72] + node _T_12498 = cat(_T_10031[2].bits.sink, _T_10031[2].bits.addr_lo) @[Mux.scala 19:72] + node _T_12499 = cat(_T_12498, _T_12497) @[Mux.scala 19:72] + node _T_12500 = cat(_T_10031[2].bits.size, _T_10031[2].bits.source) @[Mux.scala 19:72] + node _T_12501 = cat(_T_10031[2].bits.opcode, _T_10031[2].bits.param) @[Mux.scala 19:72] + node _T_12502 = cat(_T_12501, _T_12500) @[Mux.scala 19:72] + node _T_12503 = cat(_T_12502, _T_12499) @[Mux.scala 19:72] + node _T_12505 = mux(_T_12460[0], _T_12503, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12506 = cat(_T_10317[2].bits.data, _T_10317[2].bits.error) @[Mux.scala 19:72] + node _T_12507 = cat(_T_10317[2].bits.sink, _T_10317[2].bits.addr_lo) @[Mux.scala 19:72] + node _T_12508 = cat(_T_12507, _T_12506) @[Mux.scala 19:72] + node _T_12509 = cat(_T_10317[2].bits.size, _T_10317[2].bits.source) @[Mux.scala 19:72] + node _T_12510 = cat(_T_10317[2].bits.opcode, _T_10317[2].bits.param) @[Mux.scala 19:72] + node _T_12511 = cat(_T_12510, _T_12509) @[Mux.scala 19:72] + node _T_12512 = cat(_T_12511, _T_12508) @[Mux.scala 19:72] + node _T_12514 = mux(_T_12460[1], _T_12512, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12515 = cat(_T_10603[2].bits.data, _T_10603[2].bits.error) @[Mux.scala 19:72] + node _T_12516 = cat(_T_10603[2].bits.sink, _T_10603[2].bits.addr_lo) @[Mux.scala 19:72] + node _T_12517 = cat(_T_12516, _T_12515) @[Mux.scala 19:72] + node _T_12518 = cat(_T_10603[2].bits.size, _T_10603[2].bits.source) @[Mux.scala 19:72] + node _T_12519 = cat(_T_10603[2].bits.opcode, _T_10603[2].bits.param) @[Mux.scala 19:72] + node _T_12520 = cat(_T_12519, _T_12518) @[Mux.scala 19:72] + node _T_12521 = cat(_T_12520, _T_12517) @[Mux.scala 19:72] + node _T_12523 = mux(_T_12460[2], _T_12521, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_12533 = or(_T_12505, _T_12514) @[Mux.scala 19:72] + node _T_12534 = or(_T_12533, _T_12523) @[Mux.scala 19:72] + wire _T_12544 : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_12544 is invalid @[Mux.scala 19:72] + wire _T_12554 : UInt<84> + _T_12554 is invalid + _T_12554 <= _T_12534 + node _T_12555 = bits(_T_12554, 0, 0) @[Mux.scala 19:72] + _T_12544.error <= _T_12555 @[Mux.scala 19:72] + node _T_12556 = bits(_T_12554, 64, 1) @[Mux.scala 19:72] + _T_12544.data <= _T_12556 @[Mux.scala 19:72] + node _T_12557 = bits(_T_12554, 67, 65) @[Mux.scala 19:72] + _T_12544.addr_lo <= _T_12557 @[Mux.scala 19:72] + node _T_12558 = bits(_T_12554, 71, 68) @[Mux.scala 19:72] + _T_12544.sink <= _T_12558 @[Mux.scala 19:72] + node _T_12559 = bits(_T_12554, 74, 72) @[Mux.scala 19:72] + _T_12544.source <= _T_12559 @[Mux.scala 19:72] + node _T_12560 = bits(_T_12554, 78, 75) @[Mux.scala 19:72] + _T_12544.size <= _T_12560 @[Mux.scala 19:72] + node _T_12561 = bits(_T_12554, 80, 79) @[Mux.scala 19:72] + _T_12544.param <= _T_12561 @[Mux.scala 19:72] + node _T_12562 = bits(_T_12554, 83, 81) @[Mux.scala 19:72] + _T_12544.opcode <= _T_12562 @[Mux.scala 19:72] + in[2].d.bits <- _T_12544 @[Arbiter.scala 72:17] + + module TLXbar_cbus : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}, out : {2 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}, 1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + wire in : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1] @[Xbar.scala 103:18] + in is invalid @[Xbar.scala 103:18] + in[0] <- io.in.0 @[Xbar.scala 106:13] + node _T_2103 = or(io.in.0.a.bits.source, UInt<1>("h00")) @[Xbar.scala 108:53] + in[0].a.bits.source <= _T_2103 @[Xbar.scala 108:27] + node _T_2105 = or(io.in.0.c.bits.source, UInt<1>("h00")) @[Xbar.scala 109:53] + in[0].c.bits.source <= _T_2105 @[Xbar.scala 109:27] + node _T_2106 = bits(in[0].b.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.b.bits.source <= _T_2106 @[Xbar.scala 111:30] + node _T_2107 = bits(in[0].d.bits.source, 2, 0) @[Xbar.scala 100:67] + io.in.0.d.bits.source <= _T_2107 @[Xbar.scala 112:30] + wire out : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[3] @[Xbar.scala 116:19] + out is invalid @[Xbar.scala 116:19] + io.out.0 <- out[0] @[Xbar.scala 119:17] + node _T_4379 = or(io.out.0.d.bits.sink, UInt<2>("h02")) @[Xbar.scala 121:51] + out[0].d.bits.sink <= _T_4379 @[Xbar.scala 121:26] + io.out.0.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + io.out.1 <- out[1] @[Xbar.scala 119:17] + node _T_4382 = or(io.out.1.d.bits.sink, UInt<1>("h01")) @[Xbar.scala 121:51] + out[1].d.bits.sink <= _T_4382 @[Xbar.scala 121:26] + io.out.1.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + io.out.2 <- out[2] @[Xbar.scala 119:17] + node _T_4385 = or(io.out.2.d.bits.sink, UInt<1>("h00")) @[Xbar.scala 121:51] + out[2].d.bits.sink <= _T_4385 @[Xbar.scala 121:26] + io.out.2.e.bits.sink <= UInt<1>("h00") @[Xbar.scala 123:29] + node _T_4388 = xor(in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4389 = cvt(_T_4388) @[Parameters.scala 117:49] + node _T_4391 = and(_T_4389, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_4392 = asSInt(_T_4391) @[Parameters.scala 117:52] + node _T_4394 = eq(_T_4392, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4396 = xor(in[0].a.bits.address, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_4397 = cvt(_T_4396) @[Parameters.scala 117:49] + node _T_4399 = and(_T_4397, asSInt(UInt<28>("h04000000"))) @[Parameters.scala 117:52] + node _T_4400 = asSInt(_T_4399) @[Parameters.scala 117:52] + node _T_4402 = eq(_T_4400, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4404 = xor(in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4405 = cvt(_T_4404) @[Parameters.scala 117:49] + node _T_4407 = and(_T_4405, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_4408 = asSInt(_T_4407) @[Parameters.scala 117:52] + node _T_4410 = eq(_T_4408, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_4413 : UInt<1>[3] @[Xbar.scala 129:49] + _T_4413 is invalid @[Xbar.scala 129:49] + _T_4413[0] <= _T_4394 @[Xbar.scala 129:49] + _T_4413[1] <= _T_4402 @[Xbar.scala 129:49] + _T_4413[2] <= _T_4410 @[Xbar.scala 129:49] + wire requestAIO : UInt<1>[3][1] @[Xbar.scala 129:25] + requestAIO is invalid @[Xbar.scala 129:25] + requestAIO[0] <- _T_4413 @[Xbar.scala 129:25] + node _T_4487 = xor(in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4488 = cvt(_T_4487) @[Parameters.scala 117:49] + node _T_4490 = and(_T_4488, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_4491 = asSInt(_T_4490) @[Parameters.scala 117:52] + node _T_4493 = eq(_T_4491, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4495 = xor(in[0].c.bits.address, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_4496 = cvt(_T_4495) @[Parameters.scala 117:49] + node _T_4498 = and(_T_4496, asSInt(UInt<28>("h04000000"))) @[Parameters.scala 117:52] + node _T_4499 = asSInt(_T_4498) @[Parameters.scala 117:52] + node _T_4501 = eq(_T_4499, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4503 = xor(in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4504 = cvt(_T_4503) @[Parameters.scala 117:49] + node _T_4506 = and(_T_4504, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_4507 = asSInt(_T_4506) @[Parameters.scala 117:52] + node _T_4509 = eq(_T_4507, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_4512 : UInt<1>[3] @[Xbar.scala 130:49] + _T_4512 is invalid @[Xbar.scala 130:49] + _T_4512[0] <= _T_4493 @[Xbar.scala 130:49] + _T_4512[1] <= _T_4501 @[Xbar.scala 130:49] + _T_4512[2] <= _T_4509 @[Xbar.scala 130:49] + wire requestCIO : UInt<1>[3][1] @[Xbar.scala 130:25] + requestCIO is invalid @[Xbar.scala 130:25] + requestCIO[0] <- _T_4512 @[Xbar.scala 130:25] + node _T_4586 = xor(UInt<1>("h00"), out[0].b.bits.source) @[Parameters.scala 37:23] + node _T_4587 = not(_T_4586) @[Parameters.scala 37:9] + node _T_4589 = or(_T_4587, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4590 = not(_T_4589) @[Parameters.scala 37:7] + node _T_4592 = eq(_T_4590, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4595 : UInt<1>[1] @[Xbar.scala 131:44] + _T_4595 is invalid @[Xbar.scala 131:44] + _T_4595[0] <= _T_4592 @[Xbar.scala 131:44] + node _T_4600 = xor(UInt<1>("h00"), out[1].b.bits.source) @[Parameters.scala 37:23] + node _T_4601 = not(_T_4600) @[Parameters.scala 37:9] + node _T_4603 = or(_T_4601, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4604 = not(_T_4603) @[Parameters.scala 37:7] + node _T_4606 = eq(_T_4604, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4609 : UInt<1>[1] @[Xbar.scala 131:44] + _T_4609 is invalid @[Xbar.scala 131:44] + _T_4609[0] <= _T_4606 @[Xbar.scala 131:44] + node _T_4614 = xor(UInt<1>("h00"), out[2].b.bits.source) @[Parameters.scala 37:23] + node _T_4615 = not(_T_4614) @[Parameters.scala 37:9] + node _T_4617 = or(_T_4615, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4618 = not(_T_4617) @[Parameters.scala 37:7] + node _T_4620 = eq(_T_4618, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4623 : UInt<1>[1] @[Xbar.scala 131:44] + _T_4623 is invalid @[Xbar.scala 131:44] + _T_4623[0] <= _T_4620 @[Xbar.scala 131:44] + wire requestBOI : UInt<1>[1][3] @[Xbar.scala 131:25] + requestBOI is invalid @[Xbar.scala 131:25] + requestBOI[0] <- _T_4595 @[Xbar.scala 131:25] + requestBOI[1] <- _T_4609 @[Xbar.scala 131:25] + requestBOI[2] <- _T_4623 @[Xbar.scala 131:25] + node _T_4703 = xor(UInt<1>("h00"), out[0].d.bits.source) @[Parameters.scala 37:23] + node _T_4704 = not(_T_4703) @[Parameters.scala 37:9] + node _T_4706 = or(_T_4704, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4707 = not(_T_4706) @[Parameters.scala 37:7] + node _T_4709 = eq(_T_4707, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4712 : UInt<1>[1] @[Xbar.scala 132:44] + _T_4712 is invalid @[Xbar.scala 132:44] + _T_4712[0] <= _T_4709 @[Xbar.scala 132:44] + node _T_4717 = xor(UInt<1>("h00"), out[1].d.bits.source) @[Parameters.scala 37:23] + node _T_4718 = not(_T_4717) @[Parameters.scala 37:9] + node _T_4720 = or(_T_4718, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4721 = not(_T_4720) @[Parameters.scala 37:7] + node _T_4723 = eq(_T_4721, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4726 : UInt<1>[1] @[Xbar.scala 132:44] + _T_4726 is invalid @[Xbar.scala 132:44] + _T_4726[0] <= _T_4723 @[Xbar.scala 132:44] + node _T_4731 = xor(UInt<1>("h00"), out[2].d.bits.source) @[Parameters.scala 37:23] + node _T_4732 = not(_T_4731) @[Parameters.scala 37:9] + node _T_4734 = or(_T_4732, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_4735 = not(_T_4734) @[Parameters.scala 37:7] + node _T_4737 = eq(_T_4735, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_4740 : UInt<1>[1] @[Xbar.scala 132:44] + _T_4740 is invalid @[Xbar.scala 132:44] + _T_4740[0] <= _T_4737 @[Xbar.scala 132:44] + wire requestDOI : UInt<1>[1][3] @[Xbar.scala 132:25] + requestDOI is invalid @[Xbar.scala 132:25] + requestDOI[0] <- _T_4712 @[Xbar.scala 132:25] + requestDOI[1] <- _T_4726 @[Xbar.scala 132:25] + requestDOI[2] <- _T_4740 @[Xbar.scala 132:25] + node _T_4820 = eq(UInt<2>("h02"), in[0].e.bits.sink) @[Parameters.scala 35:39] + node _T_4822 = eq(UInt<1>("h01"), in[0].e.bits.sink) @[Parameters.scala 35:39] + node _T_4824 = eq(UInt<1>("h00"), in[0].e.bits.sink) @[Parameters.scala 35:39] + wire _T_4827 : UInt<1>[3] @[Xbar.scala 133:44] + _T_4827 is invalid @[Xbar.scala 133:44] + _T_4827[0] <= _T_4820 @[Xbar.scala 133:44] + _T_4827[1] <= _T_4822 @[Xbar.scala 133:44] + _T_4827[2] <= _T_4824 @[Xbar.scala 133:44] + wire requestEIO : UInt<1>[3][1] @[Xbar.scala 133:25] + requestEIO is invalid @[Xbar.scala 133:25] + requestEIO[0] <- _T_4827 @[Xbar.scala 133:25] + node _T_4901 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4902 = dshl(_T_4901, in[0].a.bits.size) @[package.scala 19:71] + node _T_4903 = bits(_T_4902, 5, 0) @[package.scala 19:76] + node _T_4904 = not(_T_4903) @[package.scala 19:40] + node _T_4905 = shr(_T_4904, 3) @[Edges.scala 198:59] + node _T_4906 = bits(in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4908 = eq(_T_4906, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4910 = mux(_T_4908, _T_4905, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsAI : UInt<3>[1] @[Xbar.scala 135:22] + beatsAI is invalid @[Xbar.scala 135:22] + beatsAI[0] <= _T_4910 @[Xbar.scala 135:22] + node _T_4917 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4918 = dshl(_T_4917, out[0].b.bits.size) @[package.scala 19:71] + node _T_4919 = bits(_T_4918, 5, 0) @[package.scala 19:76] + node _T_4920 = not(_T_4919) @[package.scala 19:40] + node _T_4921 = shr(_T_4920, 3) @[Edges.scala 198:59] + node _T_4922 = bits(out[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4924 = eq(_T_4922, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4927 = mux(UInt<1>("h00"), _T_4921, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4929 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4930 = dshl(_T_4929, out[1].b.bits.size) @[package.scala 19:71] + node _T_4931 = bits(_T_4930, 5, 0) @[package.scala 19:76] + node _T_4932 = not(_T_4931) @[package.scala 19:40] + node _T_4933 = shr(_T_4932, 3) @[Edges.scala 198:59] + node _T_4934 = bits(out[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4936 = eq(_T_4934, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4939 = mux(UInt<1>("h00"), _T_4933, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4941 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4942 = dshl(_T_4941, out[2].b.bits.size) @[package.scala 19:71] + node _T_4943 = bits(_T_4942, 5, 0) @[package.scala 19:76] + node _T_4944 = not(_T_4943) @[package.scala 19:40] + node _T_4945 = shr(_T_4944, 3) @[Edges.scala 198:59] + node _T_4946 = bits(out[2].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4948 = eq(_T_4946, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4951 = mux(UInt<1>("h00"), _T_4945, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsBO : UInt<3>[3] @[Xbar.scala 136:22] + beatsBO is invalid @[Xbar.scala 136:22] + beatsBO[0] <= _T_4927 @[Xbar.scala 136:22] + beatsBO[1] <= _T_4939 @[Xbar.scala 136:22] + beatsBO[2] <= _T_4951 @[Xbar.scala 136:22] + node _T_4960 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4961 = dshl(_T_4960, in[0].c.bits.size) @[package.scala 19:71] + node _T_4962 = bits(_T_4961, 5, 0) @[package.scala 19:76] + node _T_4963 = not(_T_4962) @[package.scala 19:40] + node _T_4964 = shr(_T_4963, 3) @[Edges.scala 198:59] + node _T_4965 = bits(in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4967 = mux(_T_4965, _T_4964, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsCI : UInt<3>[1] @[Xbar.scala 137:22] + beatsCI is invalid @[Xbar.scala 137:22] + beatsCI[0] <= _T_4967 @[Xbar.scala 137:22] + node _T_4974 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4975 = dshl(_T_4974, out[0].d.bits.size) @[package.scala 19:71] + node _T_4976 = bits(_T_4975, 5, 0) @[package.scala 19:76] + node _T_4977 = not(_T_4976) @[package.scala 19:40] + node _T_4978 = shr(_T_4977, 3) @[Edges.scala 198:59] + node _T_4979 = bits(out[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4981 = mux(_T_4979, _T_4978, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4983 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4984 = dshl(_T_4983, out[1].d.bits.size) @[package.scala 19:71] + node _T_4985 = bits(_T_4984, 5, 0) @[package.scala 19:76] + node _T_4986 = not(_T_4985) @[package.scala 19:40] + node _T_4987 = shr(_T_4986, 3) @[Edges.scala 198:59] + node _T_4988 = bits(out[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4990 = mux(_T_4988, _T_4987, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_4992 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_4993 = dshl(_T_4992, out[2].d.bits.size) @[package.scala 19:71] + node _T_4994 = bits(_T_4993, 5, 0) @[package.scala 19:76] + node _T_4995 = not(_T_4994) @[package.scala 19:40] + node _T_4996 = shr(_T_4995, 3) @[Edges.scala 198:59] + node _T_4997 = bits(out[2].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4999 = mux(_T_4997, _T_4996, UInt<1>("h00")) @[Edges.scala 199:14] + wire beatsDO : UInt<3>[3] @[Xbar.scala 138:22] + beatsDO is invalid @[Xbar.scala 138:22] + beatsDO[0] <= _T_4981 @[Xbar.scala 138:22] + beatsDO[1] <= _T_4990 @[Xbar.scala 138:22] + beatsDO[2] <= _T_4999 @[Xbar.scala 138:22] + wire beatsEI : UInt<1>[1] @[Xbar.scala 139:22] + beatsEI is invalid @[Xbar.scala 139:22] + beatsEI[0] <= UInt<1>("h00") @[Xbar.scala 139:22] + wire _T_5095 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}[3] @[Xbar.scala 147:26] + _T_5095 is invalid @[Xbar.scala 147:26] + _T_5095[0].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_5261 = and(in[0].a.valid, requestAIO[0][0]) @[Xbar.scala 150:42] + _T_5095[0].valid <= _T_5261 @[Xbar.scala 150:27] + _T_5095[1].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_5262 = and(in[0].a.valid, requestAIO[0][1]) @[Xbar.scala 150:42] + _T_5095[1].valid <= _T_5262 @[Xbar.scala 150:27] + _T_5095[2].bits <- in[0].a.bits @[Xbar.scala 149:26] + node _T_5263 = and(in[0].a.valid, requestAIO[0][2]) @[Xbar.scala 150:42] + _T_5095[2].valid <= _T_5263 @[Xbar.scala 150:27] + node _T_5265 = mux(requestAIO[0][0], _T_5095[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5267 = mux(requestAIO[0][1], _T_5095[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5269 = mux(requestAIO[0][2], _T_5095[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5271 = or(_T_5265, _T_5267) @[Mux.scala 19:72] + node _T_5272 = or(_T_5271, _T_5269) @[Mux.scala 19:72] + wire _T_5274 : UInt<1> @[Mux.scala 19:72] + _T_5274 is invalid @[Mux.scala 19:72] + _T_5274 <= _T_5272 @[Mux.scala 19:72] + in[0].a.ready <= _T_5274 @[Xbar.scala 152:19] + wire _T_5317 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_5317 is invalid @[Xbar.scala 147:26] + _T_5317[0].bits <- out[0].b.bits @[Xbar.scala 149:26] + node _T_5401 = and(out[0].b.valid, requestBOI[0][0]) @[Xbar.scala 150:42] + _T_5317[0].valid <= _T_5401 @[Xbar.scala 150:27] + out[0].b.ready <= _T_5317[0].ready @[Xbar.scala 152:19] + wire _T_5444 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_5444 is invalid @[Xbar.scala 147:26] + _T_5444[0].bits <- out[1].b.bits @[Xbar.scala 149:26] + node _T_5528 = and(out[1].b.valid, requestBOI[1][0]) @[Xbar.scala 150:42] + _T_5444[0].valid <= _T_5528 @[Xbar.scala 150:27] + out[1].b.ready <= _T_5444[0].ready @[Xbar.scala 152:19] + wire _T_5571 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}[1] @[Xbar.scala 147:26] + _T_5571 is invalid @[Xbar.scala 147:26] + _T_5571[0].bits <- out[2].b.bits @[Xbar.scala 149:26] + node _T_5655 = and(out[2].b.valid, requestBOI[2][0]) @[Xbar.scala 150:42] + _T_5571[0].valid <= _T_5655 @[Xbar.scala 150:27] + out[2].b.ready <= _T_5571[0].ready @[Xbar.scala 152:19] + wire _T_5738 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}[3] @[Xbar.scala 147:26] + _T_5738 is invalid @[Xbar.scala 147:26] + _T_5738[0].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_5904 = and(in[0].c.valid, requestCIO[0][0]) @[Xbar.scala 150:42] + _T_5738[0].valid <= _T_5904 @[Xbar.scala 150:27] + _T_5738[1].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_5905 = and(in[0].c.valid, requestCIO[0][1]) @[Xbar.scala 150:42] + _T_5738[1].valid <= _T_5905 @[Xbar.scala 150:27] + _T_5738[2].bits <- in[0].c.bits @[Xbar.scala 149:26] + node _T_5906 = and(in[0].c.valid, requestCIO[0][2]) @[Xbar.scala 150:42] + _T_5738[2].valid <= _T_5906 @[Xbar.scala 150:27] + node _T_5908 = mux(requestCIO[0][0], _T_5738[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5910 = mux(requestCIO[0][1], _T_5738[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5912 = mux(requestCIO[0][2], _T_5738[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_5914 = or(_T_5908, _T_5910) @[Mux.scala 19:72] + node _T_5915 = or(_T_5914, _T_5912) @[Mux.scala 19:72] + wire _T_5917 : UInt<1> @[Mux.scala 19:72] + _T_5917 is invalid @[Mux.scala 19:72] + _T_5917 <= _T_5915 @[Mux.scala 19:72] + in[0].c.ready <= _T_5917 @[Xbar.scala 152:19] + wire _T_5964 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_5964 is invalid @[Xbar.scala 147:26] + _T_5964[0].bits <- out[0].d.bits @[Xbar.scala 149:26] + node _T_6056 = and(out[0].d.valid, requestDOI[0][0]) @[Xbar.scala 150:42] + _T_5964[0].valid <= _T_6056 @[Xbar.scala 150:27] + out[0].d.ready <= _T_5964[0].ready @[Xbar.scala 152:19] + wire _T_6103 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_6103 is invalid @[Xbar.scala 147:26] + _T_6103[0].bits <- out[1].d.bits @[Xbar.scala 149:26] + node _T_6195 = and(out[1].d.valid, requestDOI[1][0]) @[Xbar.scala 150:42] + _T_6103[0].valid <= _T_6195 @[Xbar.scala 150:27] + out[1].d.ready <= _T_6103[0].ready @[Xbar.scala 152:19] + wire _T_6242 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}[1] @[Xbar.scala 147:26] + _T_6242 is invalid @[Xbar.scala 147:26] + _T_6242[0].bits <- out[2].d.bits @[Xbar.scala 149:26] + node _T_6334 = and(out[2].d.valid, requestDOI[2][0]) @[Xbar.scala 150:42] + _T_6242[0].valid <= _T_6334 @[Xbar.scala 150:27] + out[2].d.ready <= _T_6242[0].ready @[Xbar.scala 152:19] + wire _T_6369 : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}[3] @[Xbar.scala 147:26] + _T_6369 is invalid @[Xbar.scala 147:26] + _T_6369[0].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_6439 = and(in[0].e.valid, requestEIO[0][0]) @[Xbar.scala 150:42] + _T_6369[0].valid <= _T_6439 @[Xbar.scala 150:27] + _T_6369[1].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_6440 = and(in[0].e.valid, requestEIO[0][1]) @[Xbar.scala 150:42] + _T_6369[1].valid <= _T_6440 @[Xbar.scala 150:27] + _T_6369[2].bits <- in[0].e.bits @[Xbar.scala 149:26] + node _T_6441 = and(in[0].e.valid, requestEIO[0][2]) @[Xbar.scala 150:42] + _T_6369[2].valid <= _T_6441 @[Xbar.scala 150:27] + node _T_6443 = mux(requestEIO[0][0], _T_6369[0].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6445 = mux(requestEIO[0][1], _T_6369[1].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6447 = mux(requestEIO[0][2], _T_6369[2].ready, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6449 = or(_T_6443, _T_6445) @[Mux.scala 19:72] + node _T_6450 = or(_T_6449, _T_6447) @[Mux.scala 19:72] + wire _T_6452 : UInt<1> @[Mux.scala 19:72] + _T_6452 is invalid @[Mux.scala 19:72] + _T_6452 <= _T_6450 @[Mux.scala 19:72] + in[0].e.ready <= _T_6452 @[Xbar.scala 152:19] + reg _T_6454 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_6456 = eq(_T_6454, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_6457 = and(_T_6456, out[0].a.ready) @[Arbiter.scala 35:24] + node _T_6460 = eq(_T_5095[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6461 = and(UInt<1>("h01"), _T_6460) @[Arbiter.scala 14:35] + wire _T_6464 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_6464 is invalid @[Arbiter.scala 40:23] + _T_6464[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_6468 = and(_T_6464[0], _T_5095[0].valid) @[Arbiter.scala 42:65] + wire _T_6471 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_6471 is invalid @[Arbiter.scala 42:23] + _T_6471[0] <= _T_6468 @[Arbiter.scala 42:23] + node _T_6476 = or(UInt<1>("h00"), _T_6471[0]) @[Arbiter.scala 47:52] + node _T_6478 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6480 = eq(_T_6471[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6481 = or(_T_6478, _T_6480) @[Arbiter.scala 48:59] + node _T_6482 = or(_T_6481, reset) @[Arbiter.scala 48:13] + node _T_6484 = eq(_T_6482, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_6484 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_6486 = eq(_T_5095[0].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_6487 = or(_T_6486, _T_6471[0]) @[Arbiter.scala 50:36] + node _T_6488 = or(_T_6487, reset) @[Arbiter.scala 50:14] + node _T_6490 = eq(_T_6488, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_6490 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_6492 = mux(_T_6471[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6493 = and(out[0].a.ready, out[0].a.valid) @[Decoupled.scala 30:37] + node _T_6494 = sub(_T_6454, _T_6493) @[Arbiter.scala 55:52] + node _T_6495 = asUInt(_T_6494) @[Arbiter.scala 55:52] + node _T_6496 = tail(_T_6495, 1) @[Arbiter.scala 55:52] + node _T_6497 = mux(_T_6457, _T_6492, _T_6496) @[Arbiter.scala 55:23] + _T_6454 <= _T_6497 @[Arbiter.scala 55:17] + wire _T_6501 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_6501 is invalid @[Arbiter.scala 58:49] + _T_6501[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_6505 : UInt<1>[1], clock with : (reset => (reset, _T_6501)) @[Reg.scala 26:44] + node _T_6511 = mux(_T_6456, _T_6471, _T_6505) @[Arbiter.scala 59:25] + _T_6505 <- _T_6511 @[Arbiter.scala 60:13] + _T_5095[0].ready <= out[0].a.ready @[Arbiter.scala 68:28] + node _T_6517 = mux(_T_6456, _T_5095[0].valid, _T_5095[0].valid) @[Arbiter.scala 71:24] + out[0].a.valid <= _T_6517 @[Arbiter.scala 71:18] + out[0].a.bits <- _T_5095[0].bits @[Arbiter.scala 72:17] + out[0].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[0].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_6521 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_6523 = eq(_T_6521, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_6524 = and(_T_6523, out[1].a.ready) @[Arbiter.scala 35:24] + node _T_6527 = eq(_T_5095[1].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6528 = and(UInt<1>("h01"), _T_6527) @[Arbiter.scala 14:35] + wire _T_6531 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_6531 is invalid @[Arbiter.scala 40:23] + _T_6531[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_6535 = and(_T_6531[0], _T_5095[1].valid) @[Arbiter.scala 42:65] + wire _T_6538 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_6538 is invalid @[Arbiter.scala 42:23] + _T_6538[0] <= _T_6535 @[Arbiter.scala 42:23] + node _T_6543 = or(UInt<1>("h00"), _T_6538[0]) @[Arbiter.scala 47:52] + node _T_6545 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6547 = eq(_T_6538[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6548 = or(_T_6545, _T_6547) @[Arbiter.scala 48:59] + node _T_6549 = or(_T_6548, reset) @[Arbiter.scala 48:13] + node _T_6551 = eq(_T_6549, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_6551 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_6553 = eq(_T_5095[1].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_6554 = or(_T_6553, _T_6538[0]) @[Arbiter.scala 50:36] + node _T_6555 = or(_T_6554, reset) @[Arbiter.scala 50:14] + node _T_6557 = eq(_T_6555, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_6557 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_6559 = mux(_T_6538[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6560 = and(out[1].a.ready, out[1].a.valid) @[Decoupled.scala 30:37] + node _T_6561 = sub(_T_6521, _T_6560) @[Arbiter.scala 55:52] + node _T_6562 = asUInt(_T_6561) @[Arbiter.scala 55:52] + node _T_6563 = tail(_T_6562, 1) @[Arbiter.scala 55:52] + node _T_6564 = mux(_T_6524, _T_6559, _T_6563) @[Arbiter.scala 55:23] + _T_6521 <= _T_6564 @[Arbiter.scala 55:17] + wire _T_6568 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_6568 is invalid @[Arbiter.scala 58:49] + _T_6568[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_6572 : UInt<1>[1], clock with : (reset => (reset, _T_6568)) @[Reg.scala 26:44] + node _T_6578 = mux(_T_6523, _T_6538, _T_6572) @[Arbiter.scala 59:25] + _T_6572 <- _T_6578 @[Arbiter.scala 60:13] + _T_5095[1].ready <= out[1].a.ready @[Arbiter.scala 68:28] + node _T_6584 = mux(_T_6523, _T_5095[1].valid, _T_5095[1].valid) @[Arbiter.scala 71:24] + out[1].a.valid <= _T_6584 @[Arbiter.scala 71:18] + out[1].a.bits <- _T_5095[1].bits @[Arbiter.scala 72:17] + out[1].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[1].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_6588 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_6590 = eq(_T_6588, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_6591 = and(_T_6590, out[2].a.ready) @[Arbiter.scala 35:24] + node _T_6594 = eq(_T_5095[2].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6595 = and(UInt<1>("h01"), _T_6594) @[Arbiter.scala 14:35] + wire _T_6598 : UInt<1>[1] @[Arbiter.scala 40:23] + _T_6598 is invalid @[Arbiter.scala 40:23] + _T_6598[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + node _T_6602 = and(_T_6598[0], _T_5095[2].valid) @[Arbiter.scala 42:65] + wire _T_6605 : UInt<1>[1] @[Arbiter.scala 42:23] + _T_6605 is invalid @[Arbiter.scala 42:23] + _T_6605[0] <= _T_6602 @[Arbiter.scala 42:23] + node _T_6610 = or(UInt<1>("h00"), _T_6605[0]) @[Arbiter.scala 47:52] + node _T_6612 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6614 = eq(_T_6605[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6615 = or(_T_6612, _T_6614) @[Arbiter.scala 48:59] + node _T_6616 = or(_T_6615, reset) @[Arbiter.scala 48:13] + node _T_6618 = eq(_T_6616, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_6618 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_6620 = eq(_T_5095[2].valid, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_6621 = or(_T_6620, _T_6605[0]) @[Arbiter.scala 50:36] + node _T_6622 = or(_T_6621, reset) @[Arbiter.scala 50:14] + node _T_6624 = eq(_T_6622, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_6624 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_6626 = mux(_T_6605[0], beatsAI[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6627 = and(out[2].a.ready, out[2].a.valid) @[Decoupled.scala 30:37] + node _T_6628 = sub(_T_6588, _T_6627) @[Arbiter.scala 55:52] + node _T_6629 = asUInt(_T_6628) @[Arbiter.scala 55:52] + node _T_6630 = tail(_T_6629, 1) @[Arbiter.scala 55:52] + node _T_6631 = mux(_T_6591, _T_6626, _T_6630) @[Arbiter.scala 55:23] + _T_6588 <= _T_6631 @[Arbiter.scala 55:17] + wire _T_6635 : UInt<1>[1] @[Arbiter.scala 58:49] + _T_6635 is invalid @[Arbiter.scala 58:49] + _T_6635[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_6639 : UInt<1>[1], clock with : (reset => (reset, _T_6635)) @[Reg.scala 26:44] + node _T_6645 = mux(_T_6590, _T_6605, _T_6639) @[Arbiter.scala 59:25] + _T_6639 <- _T_6645 @[Arbiter.scala 60:13] + _T_5095[2].ready <= out[2].a.ready @[Arbiter.scala 68:28] + node _T_6651 = mux(_T_6590, _T_5095[2].valid, _T_5095[2].valid) @[Arbiter.scala 71:24] + out[2].a.valid <= _T_6651 @[Arbiter.scala 71:18] + out[2].a.bits <- _T_5095[2].bits @[Arbiter.scala 72:17] + out[2].c.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + out[2].e.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + in[0].b.valid <= UInt<1>("h00") @[Arbiter.scala 26:18] + reg _T_6656 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_6658 = eq(_T_6656, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_6659 = and(_T_6658, in[0].d.ready) @[Arbiter.scala 35:24] + node _T_6662 = eq(_T_5964[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6663 = and(UInt<1>("h01"), _T_6662) @[Arbiter.scala 14:35] + node _T_6665 = eq(_T_6103[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6666 = and(_T_6663, _T_6665) @[Arbiter.scala 14:35] + node _T_6668 = eq(_T_6242[0].valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_6669 = and(_T_6666, _T_6668) @[Arbiter.scala 14:35] + wire _T_6672 : UInt<1>[3] @[Arbiter.scala 40:23] + _T_6672 is invalid @[Arbiter.scala 40:23] + _T_6672[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_6672[1] <= _T_6663 @[Arbiter.scala 40:23] + _T_6672[2] <= _T_6666 @[Arbiter.scala 40:23] + node _T_6678 = and(_T_6672[0], _T_5964[0].valid) @[Arbiter.scala 42:65] + node _T_6679 = and(_T_6672[1], _T_6103[0].valid) @[Arbiter.scala 42:65] + node _T_6680 = and(_T_6672[2], _T_6242[0].valid) @[Arbiter.scala 42:65] + wire _T_6683 : UInt<1>[3] @[Arbiter.scala 42:23] + _T_6683 is invalid @[Arbiter.scala 42:23] + _T_6683[0] <= _T_6678 @[Arbiter.scala 42:23] + _T_6683[1] <= _T_6679 @[Arbiter.scala 42:23] + _T_6683[2] <= _T_6680 @[Arbiter.scala 42:23] + node _T_6690 = or(UInt<1>("h00"), _T_6683[0]) @[Arbiter.scala 47:52] + node _T_6691 = or(_T_6690, _T_6683[1]) @[Arbiter.scala 47:52] + node _T_6692 = or(_T_6691, _T_6683[2]) @[Arbiter.scala 47:52] + node _T_6694 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6696 = eq(_T_6683[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6697 = or(_T_6694, _T_6696) @[Arbiter.scala 48:59] + node _T_6699 = eq(_T_6690, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6701 = eq(_T_6683[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6702 = or(_T_6699, _T_6701) @[Arbiter.scala 48:59] + node _T_6704 = eq(_T_6691, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_6706 = eq(_T_6683[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_6707 = or(_T_6704, _T_6706) @[Arbiter.scala 48:59] + node _T_6708 = and(_T_6697, _T_6702) @[Arbiter.scala 48:77] + node _T_6709 = and(_T_6708, _T_6707) @[Arbiter.scala 48:77] + node _T_6710 = or(_T_6709, reset) @[Arbiter.scala 48:13] + node _T_6712 = eq(_T_6710, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_6712 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_6713 = or(_T_5964[0].valid, _T_6103[0].valid) @[Arbiter.scala 50:31] + node _T_6714 = or(_T_6713, _T_6242[0].valid) @[Arbiter.scala 50:31] + node _T_6716 = eq(_T_6714, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_6717 = or(_T_6683[0], _T_6683[1]) @[Arbiter.scala 50:54] + node _T_6718 = or(_T_6717, _T_6683[2]) @[Arbiter.scala 50:54] + node _T_6719 = or(_T_6716, _T_6718) @[Arbiter.scala 50:36] + node _T_6720 = or(_T_6719, reset) @[Arbiter.scala 50:14] + node _T_6722 = eq(_T_6720, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_6722 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_6724 = mux(_T_6683[0], beatsDO[0], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6726 = mux(_T_6683[1], beatsDO[1], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6728 = mux(_T_6683[2], beatsDO[2], UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_6729 = or(_T_6724, _T_6726) @[Arbiter.scala 54:44] + node _T_6730 = or(_T_6729, _T_6728) @[Arbiter.scala 54:44] + node _T_6731 = and(in[0].d.ready, in[0].d.valid) @[Decoupled.scala 30:37] + node _T_6732 = sub(_T_6656, _T_6731) @[Arbiter.scala 55:52] + node _T_6733 = asUInt(_T_6732) @[Arbiter.scala 55:52] + node _T_6734 = tail(_T_6733, 1) @[Arbiter.scala 55:52] + node _T_6735 = mux(_T_6659, _T_6730, _T_6734) @[Arbiter.scala 55:23] + _T_6656 <= _T_6735 @[Arbiter.scala 55:17] + wire _T_6741 : UInt<1>[3] @[Arbiter.scala 58:49] + _T_6741 is invalid @[Arbiter.scala 58:49] + _T_6741[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_6741[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_6741[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_6747 : UInt<1>[3], clock with : (reset => (reset, _T_6741)) @[Reg.scala 26:44] + node _T_6757 = mux(_T_6658, _T_6683, _T_6747) @[Arbiter.scala 59:25] + _T_6747 <- _T_6757 @[Arbiter.scala 60:13] + node _T_6767 = mux(_T_6658, _T_6672, _T_6747) @[Arbiter.scala 63:26] + node _T_6777 = and(in[0].d.ready, _T_6767[0]) @[Arbiter.scala 65:33] + _T_5964[0].ready <= _T_6777 @[Arbiter.scala 65:19] + node _T_6778 = and(in[0].d.ready, _T_6767[1]) @[Arbiter.scala 65:33] + _T_6103[0].ready <= _T_6778 @[Arbiter.scala 65:19] + node _T_6779 = and(in[0].d.ready, _T_6767[2]) @[Arbiter.scala 65:33] + _T_6242[0].ready <= _T_6779 @[Arbiter.scala 65:19] + node _T_6780 = or(_T_5964[0].valid, _T_6103[0].valid) @[Arbiter.scala 71:46] + node _T_6781 = or(_T_6780, _T_6242[0].valid) @[Arbiter.scala 71:46] + node _T_6783 = mux(_T_6747[0], _T_5964[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6785 = mux(_T_6747[1], _T_6103[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6787 = mux(_T_6747[2], _T_6242[0].valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6789 = or(_T_6783, _T_6785) @[Mux.scala 19:72] + node _T_6790 = or(_T_6789, _T_6787) @[Mux.scala 19:72] + wire _T_6792 : UInt<1> @[Mux.scala 19:72] + _T_6792 is invalid @[Mux.scala 19:72] + _T_6792 <= _T_6790 @[Mux.scala 19:72] + node _T_6793 = mux(_T_6658, _T_6781, _T_6792) @[Arbiter.scala 71:24] + in[0].d.valid <= _T_6793 @[Arbiter.scala 71:18] + node _T_6794 = cat(_T_5964[0].bits.data, _T_5964[0].bits.error) @[Mux.scala 19:72] + node _T_6795 = cat(_T_5964[0].bits.sink, _T_5964[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_6796 = cat(_T_6795, _T_6794) @[Mux.scala 19:72] + node _T_6797 = cat(_T_5964[0].bits.size, _T_5964[0].bits.source) @[Mux.scala 19:72] + node _T_6798 = cat(_T_5964[0].bits.opcode, _T_5964[0].bits.param) @[Mux.scala 19:72] + node _T_6799 = cat(_T_6798, _T_6797) @[Mux.scala 19:72] + node _T_6800 = cat(_T_6799, _T_6796) @[Mux.scala 19:72] + node _T_6802 = mux(_T_6757[0], _T_6800, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6803 = cat(_T_6103[0].bits.data, _T_6103[0].bits.error) @[Mux.scala 19:72] + node _T_6804 = cat(_T_6103[0].bits.sink, _T_6103[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_6805 = cat(_T_6804, _T_6803) @[Mux.scala 19:72] + node _T_6806 = cat(_T_6103[0].bits.size, _T_6103[0].bits.source) @[Mux.scala 19:72] + node _T_6807 = cat(_T_6103[0].bits.opcode, _T_6103[0].bits.param) @[Mux.scala 19:72] + node _T_6808 = cat(_T_6807, _T_6806) @[Mux.scala 19:72] + node _T_6809 = cat(_T_6808, _T_6805) @[Mux.scala 19:72] + node _T_6811 = mux(_T_6757[1], _T_6809, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6812 = cat(_T_6242[0].bits.data, _T_6242[0].bits.error) @[Mux.scala 19:72] + node _T_6813 = cat(_T_6242[0].bits.sink, _T_6242[0].bits.addr_lo) @[Mux.scala 19:72] + node _T_6814 = cat(_T_6813, _T_6812) @[Mux.scala 19:72] + node _T_6815 = cat(_T_6242[0].bits.size, _T_6242[0].bits.source) @[Mux.scala 19:72] + node _T_6816 = cat(_T_6242[0].bits.opcode, _T_6242[0].bits.param) @[Mux.scala 19:72] + node _T_6817 = cat(_T_6816, _T_6815) @[Mux.scala 19:72] + node _T_6818 = cat(_T_6817, _T_6814) @[Mux.scala 19:72] + node _T_6820 = mux(_T_6757[2], _T_6818, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_6830 = or(_T_6802, _T_6811) @[Mux.scala 19:72] + node _T_6831 = or(_T_6830, _T_6820) @[Mux.scala 19:72] + wire _T_6841 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_6841 is invalid @[Mux.scala 19:72] + wire _T_6851 : UInt<81> + _T_6851 is invalid + _T_6851 <= _T_6831 + node _T_6852 = bits(_T_6851, 0, 0) @[Mux.scala 19:72] + _T_6841.error <= _T_6852 @[Mux.scala 19:72] + node _T_6853 = bits(_T_6851, 64, 1) @[Mux.scala 19:72] + _T_6841.data <= _T_6853 @[Mux.scala 19:72] + node _T_6854 = bits(_T_6851, 67, 65) @[Mux.scala 19:72] + _T_6841.addr_lo <= _T_6854 @[Mux.scala 19:72] + node _T_6855 = bits(_T_6851, 69, 68) @[Mux.scala 19:72] + _T_6841.sink <= _T_6855 @[Mux.scala 19:72] + node _T_6856 = bits(_T_6851, 72, 70) @[Mux.scala 19:72] + _T_6841.source <= _T_6856 @[Mux.scala 19:72] + node _T_6857 = bits(_T_6851, 75, 73) @[Mux.scala 19:72] + _T_6841.size <= _T_6857 @[Mux.scala 19:72] + node _T_6858 = bits(_T_6851, 77, 76) @[Mux.scala 19:72] + _T_6841.param <= _T_6858 @[Mux.scala 19:72] + node _T_6859 = bits(_T_6851, 80, 78) @[Mux.scala 19:72] + _T_6841.opcode <= _T_6859 @[Mux.scala 19:72] + in[0].d.bits <- _T_6841 @[Arbiter.scala 72:17] + + module IntXbar_intBar : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : UInt<1>[2]}, out : {0 : UInt<1>[2]}} + + io is invalid + io is invalid + io.out.0[0] <= io.in.0[0] @[IntNodes.scala 126:24] + io.out.0[1] <= io.in.0[1] @[IntNodes.scala 126:24] + + module TLMonitor_14 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 33:15] + node _T_957 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_958 = or(_T_957, reset) @[CoreplexNetwork.scala 33:15] + node _T_960 = eq(_T_958, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_960 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_962 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_963 = not(_T_962) @[Parameters.scala 37:9] + node _T_965 = or(_T_963, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_966 = not(_T_965) @[Parameters.scala 37:7] + node _T_968 = eq(_T_966, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_971 : UInt<1>[1] @[Parameters.scala 228:27] + _T_971 is invalid @[Parameters.scala 228:27] + _T_971[0] <= _T_968 @[Parameters.scala 228:27] + node _T_976 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_977 = dshl(_T_976, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_978 = bits(_T_977, 7, 0) @[package.scala 19:76] + node _T_979 = not(_T_978) @[package.scala 19:40] + node _T_980 = and(io.in[0].a.bits.address, _T_979) @[Edges.scala 17:16] + node _T_982 = eq(_T_980, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_984 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_985 = dshl(UInt<1>("h01"), _T_984) @[OneHot.scala 49:12] + node _T_986 = bits(_T_985, 2, 0) @[OneHot.scala 49:37] + node _T_988 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_990 = bits(_T_986, 2, 2) @[package.scala 44:26] + node _T_991 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[package.scala 46:20] + node _T_994 = and(UInt<1>("h01"), _T_993) @[package.scala 49:27] + node _T_995 = and(_T_990, _T_994) @[package.scala 50:38] + node _T_996 = or(_T_988, _T_995) @[package.scala 50:29] + node _T_997 = and(UInt<1>("h01"), _T_991) @[package.scala 49:27] + node _T_998 = and(_T_990, _T_997) @[package.scala 50:38] + node _T_999 = or(_T_988, _T_998) @[package.scala 50:29] + node _T_1000 = bits(_T_986, 1, 1) @[package.scala 44:26] + node _T_1001 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_1003 = eq(_T_1001, UInt<1>("h00")) @[package.scala 46:20] + node _T_1004 = and(_T_994, _T_1003) @[package.scala 49:27] + node _T_1005 = and(_T_1000, _T_1004) @[package.scala 50:38] + node _T_1006 = or(_T_996, _T_1005) @[package.scala 50:29] + node _T_1007 = and(_T_994, _T_1001) @[package.scala 49:27] + node _T_1008 = and(_T_1000, _T_1007) @[package.scala 50:38] + node _T_1009 = or(_T_996, _T_1008) @[package.scala 50:29] + node _T_1010 = and(_T_997, _T_1003) @[package.scala 49:27] + node _T_1011 = and(_T_1000, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_999, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_997, _T_1001) @[package.scala 49:27] + node _T_1014 = and(_T_1000, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_999, _T_1014) @[package.scala 50:29] + node _T_1016 = bits(_T_986, 0, 0) @[package.scala 44:26] + node _T_1017 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[package.scala 46:20] + node _T_1020 = and(_T_1004, _T_1019) @[package.scala 49:27] + node _T_1021 = and(_T_1016, _T_1020) @[package.scala 50:38] + node _T_1022 = or(_T_1006, _T_1021) @[package.scala 50:29] + node _T_1023 = and(_T_1004, _T_1017) @[package.scala 49:27] + node _T_1024 = and(_T_1016, _T_1023) @[package.scala 50:38] + node _T_1025 = or(_T_1006, _T_1024) @[package.scala 50:29] + node _T_1026 = and(_T_1007, _T_1019) @[package.scala 49:27] + node _T_1027 = and(_T_1016, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1009, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1007, _T_1017) @[package.scala 49:27] + node _T_1030 = and(_T_1016, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1009, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1010, _T_1019) @[package.scala 49:27] + node _T_1033 = and(_T_1016, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1012, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1010, _T_1017) @[package.scala 49:27] + node _T_1036 = and(_T_1016, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1012, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1013, _T_1019) @[package.scala 49:27] + node _T_1039 = and(_T_1016, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1015, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1013, _T_1017) @[package.scala 49:27] + node _T_1042 = and(_T_1016, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1015, _T_1042) @[package.scala 50:29] + node _T_1044 = cat(_T_1025, _T_1022) @[Cat.scala 30:58] + node _T_1045 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1046 = cat(_T_1045, _T_1044) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1049 = cat(_T_1048, _T_1047) @[Cat.scala 30:58] + node _T_1050 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1052 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + when _T_1052 : @[CoreplexNetwork.scala 33:15] + node _T_1055 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1057 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1058 = and(_T_1055, _T_1057) @[Parameters.scala 63:37] + node _T_1059 = or(UInt<1>("h00"), _T_1058) @[Parameters.scala 132:31] + node _T_1061 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1062 = cvt(_T_1061) @[Parameters.scala 117:49] + node _T_1064 = and(_T_1062, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1065 = asSInt(_T_1064) @[Parameters.scala 117:52] + node _T_1067 = eq(_T_1065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1070 = cvt(_T_1069) @[Parameters.scala 117:49] + node _T_1072 = and(_T_1070, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1073 = asSInt(_T_1072) @[Parameters.scala 117:52] + node _T_1075 = eq(_T_1073, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1076 = or(_T_1067, _T_1075) @[Parameters.scala 133:42] + node _T_1077 = and(_T_1059, _T_1076) @[Parameters.scala 132:56] + node _T_1080 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1082 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1083 = cvt(_T_1082) @[Parameters.scala 117:49] + node _T_1085 = and(_T_1083, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1086 = asSInt(_T_1085) @[Parameters.scala 117:52] + node _T_1088 = eq(_T_1086, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1090 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1091 = cvt(_T_1090) @[Parameters.scala 117:49] + node _T_1093 = and(_T_1091, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1094 = asSInt(_T_1093) @[Parameters.scala 117:52] + node _T_1096 = eq(_T_1094, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1098 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1099 = cvt(_T_1098) @[Parameters.scala 117:49] + node _T_1101 = and(_T_1099, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1102 = asSInt(_T_1101) @[Parameters.scala 117:52] + node _T_1104 = eq(_T_1102, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1106 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1107 = cvt(_T_1106) @[Parameters.scala 117:49] + node _T_1109 = and(_T_1107, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1110 = asSInt(_T_1109) @[Parameters.scala 117:52] + node _T_1112 = eq(_T_1110, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1113 = or(_T_1088, _T_1096) @[Parameters.scala 133:42] + node _T_1114 = or(_T_1113, _T_1104) @[Parameters.scala 133:42] + node _T_1115 = or(_T_1114, _T_1112) @[Parameters.scala 133:42] + node _T_1116 = and(_T_1080, _T_1115) @[Parameters.scala 132:56] + node _T_1118 = or(UInt<1>("h00"), _T_1077) @[Parameters.scala 134:30] + node _T_1119 = or(_T_1118, _T_1116) @[Parameters.scala 134:30] + node _T_1120 = or(_T_1119, reset) @[CoreplexNetwork.scala 33:15] + node _T_1122 = eq(_T_1120, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1122 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1123 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1125 = eq(_T_1123, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1125 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1127 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_1128 = or(_T_1127, reset) @[CoreplexNetwork.scala 33:15] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1130 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1131 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1133 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1135 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_1136 = or(_T_1135, reset) @[CoreplexNetwork.scala 33:15] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1138 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1139 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 33:15] + node _T_1141 = eq(_T_1139, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1142 = or(_T_1141, reset) @[CoreplexNetwork.scala 33:15] + node _T_1144 = eq(_T_1142, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1144 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1146 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 33:15] + when _T_1146 : @[CoreplexNetwork.scala 33:15] + node _T_1149 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1151 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1152 = and(_T_1149, _T_1151) @[Parameters.scala 63:37] + node _T_1153 = or(UInt<1>("h00"), _T_1152) @[Parameters.scala 132:31] + node _T_1155 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1156 = cvt(_T_1155) @[Parameters.scala 117:49] + node _T_1158 = and(_T_1156, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1159 = asSInt(_T_1158) @[Parameters.scala 117:52] + node _T_1161 = eq(_T_1159, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1163 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1164 = cvt(_T_1163) @[Parameters.scala 117:49] + node _T_1166 = and(_T_1164, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1167 = asSInt(_T_1166) @[Parameters.scala 117:52] + node _T_1169 = eq(_T_1167, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1171 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1172 = cvt(_T_1171) @[Parameters.scala 117:49] + node _T_1174 = and(_T_1172, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1175 = asSInt(_T_1174) @[Parameters.scala 117:52] + node _T_1177 = eq(_T_1175, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1179 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1180 = cvt(_T_1179) @[Parameters.scala 117:49] + node _T_1182 = and(_T_1180, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1183 = asSInt(_T_1182) @[Parameters.scala 117:52] + node _T_1185 = eq(_T_1183, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1187 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1188 = cvt(_T_1187) @[Parameters.scala 117:49] + node _T_1190 = and(_T_1188, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1191 = asSInt(_T_1190) @[Parameters.scala 117:52] + node _T_1193 = eq(_T_1191, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1194 = or(_T_1161, _T_1169) @[Parameters.scala 133:42] + node _T_1195 = or(_T_1194, _T_1177) @[Parameters.scala 133:42] + node _T_1196 = or(_T_1195, _T_1185) @[Parameters.scala 133:42] + node _T_1197 = or(_T_1196, _T_1193) @[Parameters.scala 133:42] + node _T_1198 = and(_T_1153, _T_1197) @[Parameters.scala 132:56] + node _T_1201 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1203 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1204 = and(_T_1201, _T_1203) @[Parameters.scala 63:37] + node _T_1205 = or(UInt<1>("h00"), _T_1204) @[Parameters.scala 132:31] + node _T_1207 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1208 = cvt(_T_1207) @[Parameters.scala 117:49] + node _T_1210 = and(_T_1208, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1211 = asSInt(_T_1210) @[Parameters.scala 117:52] + node _T_1213 = eq(_T_1211, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1214 = and(_T_1205, _T_1213) @[Parameters.scala 132:56] + node _T_1216 = or(UInt<1>("h00"), _T_1198) @[Parameters.scala 134:30] + node _T_1217 = or(_T_1216, _T_1214) @[Parameters.scala 134:30] + node _T_1218 = or(_T_1217, reset) @[CoreplexNetwork.scala 33:15] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1220 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1221 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1223 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1224 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1226 = eq(_T_1224, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1226 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1228 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1229 = or(_T_1228, reset) @[CoreplexNetwork.scala 33:15] + node _T_1231 = eq(_T_1229, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1231 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1232 = eq(io.in[0].a.bits.mask, _T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1233 = or(_T_1232, reset) @[CoreplexNetwork.scala 33:15] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1235 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1237 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1237 : @[CoreplexNetwork.scala 33:15] + node _T_1240 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1242 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1243 = and(_T_1240, _T_1242) @[Parameters.scala 63:37] + node _T_1244 = or(UInt<1>("h00"), _T_1243) @[Parameters.scala 132:31] + node _T_1246 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1247 = cvt(_T_1246) @[Parameters.scala 117:49] + node _T_1249 = and(_T_1247, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1250 = asSInt(_T_1249) @[Parameters.scala 117:52] + node _T_1252 = eq(_T_1250, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1254 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1255 = cvt(_T_1254) @[Parameters.scala 117:49] + node _T_1257 = and(_T_1255, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1258 = asSInt(_T_1257) @[Parameters.scala 117:52] + node _T_1260 = eq(_T_1258, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1262 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1263 = cvt(_T_1262) @[Parameters.scala 117:49] + node _T_1265 = and(_T_1263, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1266 = asSInt(_T_1265) @[Parameters.scala 117:52] + node _T_1268 = eq(_T_1266, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1270 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1271 = cvt(_T_1270) @[Parameters.scala 117:49] + node _T_1273 = and(_T_1271, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1274 = asSInt(_T_1273) @[Parameters.scala 117:52] + node _T_1276 = eq(_T_1274, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1278 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1279 = cvt(_T_1278) @[Parameters.scala 117:49] + node _T_1281 = and(_T_1279, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1282 = asSInt(_T_1281) @[Parameters.scala 117:52] + node _T_1284 = eq(_T_1282, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1285 = or(_T_1252, _T_1260) @[Parameters.scala 133:42] + node _T_1286 = or(_T_1285, _T_1268) @[Parameters.scala 133:42] + node _T_1287 = or(_T_1286, _T_1276) @[Parameters.scala 133:42] + node _T_1288 = or(_T_1287, _T_1284) @[Parameters.scala 133:42] + node _T_1289 = and(_T_1244, _T_1288) @[Parameters.scala 132:56] + node _T_1292 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1294 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1295 = and(_T_1292, _T_1294) @[Parameters.scala 63:37] + node _T_1296 = or(UInt<1>("h00"), _T_1295) @[Parameters.scala 132:31] + node _T_1298 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1299 = cvt(_T_1298) @[Parameters.scala 117:49] + node _T_1301 = and(_T_1299, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1302 = asSInt(_T_1301) @[Parameters.scala 117:52] + node _T_1304 = eq(_T_1302, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1305 = and(_T_1296, _T_1304) @[Parameters.scala 132:56] + node _T_1308 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1310 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1311 = cvt(_T_1310) @[Parameters.scala 117:49] + node _T_1313 = and(_T_1311, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1314 = asSInt(_T_1313) @[Parameters.scala 117:52] + node _T_1316 = eq(_T_1314, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1317 = and(_T_1308, _T_1316) @[Parameters.scala 132:56] + node _T_1319 = or(UInt<1>("h00"), _T_1289) @[Parameters.scala 134:30] + node _T_1320 = or(_T_1319, _T_1305) @[Parameters.scala 134:30] + node _T_1321 = or(_T_1320, _T_1317) @[Parameters.scala 134:30] + node _T_1322 = or(_T_1321, reset) @[CoreplexNetwork.scala 33:15] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1324 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1325 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1327 = eq(_T_1325, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1327 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1328 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1330 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1332 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1333 = or(_T_1332, reset) @[CoreplexNetwork.scala 33:15] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1335 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1336 = eq(io.in[0].a.bits.mask, _T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1337 = or(_T_1336, reset) @[CoreplexNetwork.scala 33:15] + node _T_1339 = eq(_T_1337, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1339 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1341 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 33:15] + when _T_1341 : @[CoreplexNetwork.scala 33:15] + node _T_1344 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1346 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1347 = and(_T_1344, _T_1346) @[Parameters.scala 63:37] + node _T_1348 = or(UInt<1>("h00"), _T_1347) @[Parameters.scala 132:31] + node _T_1350 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1351 = cvt(_T_1350) @[Parameters.scala 117:49] + node _T_1353 = and(_T_1351, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1354 = asSInt(_T_1353) @[Parameters.scala 117:52] + node _T_1356 = eq(_T_1354, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1358 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1359 = cvt(_T_1358) @[Parameters.scala 117:49] + node _T_1361 = and(_T_1359, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1362 = asSInt(_T_1361) @[Parameters.scala 117:52] + node _T_1364 = eq(_T_1362, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1366 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1367 = cvt(_T_1366) @[Parameters.scala 117:49] + node _T_1369 = and(_T_1367, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1370 = asSInt(_T_1369) @[Parameters.scala 117:52] + node _T_1372 = eq(_T_1370, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1374 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1375 = cvt(_T_1374) @[Parameters.scala 117:49] + node _T_1377 = and(_T_1375, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1378 = asSInt(_T_1377) @[Parameters.scala 117:52] + node _T_1380 = eq(_T_1378, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1382 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1383 = cvt(_T_1382) @[Parameters.scala 117:49] + node _T_1385 = and(_T_1383, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1386 = asSInt(_T_1385) @[Parameters.scala 117:52] + node _T_1388 = eq(_T_1386, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1389 = or(_T_1356, _T_1364) @[Parameters.scala 133:42] + node _T_1390 = or(_T_1389, _T_1372) @[Parameters.scala 133:42] + node _T_1391 = or(_T_1390, _T_1380) @[Parameters.scala 133:42] + node _T_1392 = or(_T_1391, _T_1388) @[Parameters.scala 133:42] + node _T_1393 = and(_T_1348, _T_1392) @[Parameters.scala 132:56] + node _T_1396 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1398 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1399 = and(_T_1396, _T_1398) @[Parameters.scala 63:37] + node _T_1400 = or(UInt<1>("h00"), _T_1399) @[Parameters.scala 132:31] + node _T_1402 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1403 = cvt(_T_1402) @[Parameters.scala 117:49] + node _T_1405 = and(_T_1403, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1406 = asSInt(_T_1405) @[Parameters.scala 117:52] + node _T_1408 = eq(_T_1406, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1409 = and(_T_1400, _T_1408) @[Parameters.scala 132:56] + node _T_1412 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1414 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1415 = cvt(_T_1414) @[Parameters.scala 117:49] + node _T_1417 = and(_T_1415, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1418 = asSInt(_T_1417) @[Parameters.scala 117:52] + node _T_1420 = eq(_T_1418, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1421 = and(_T_1412, _T_1420) @[Parameters.scala 132:56] + node _T_1423 = or(UInt<1>("h00"), _T_1393) @[Parameters.scala 134:30] + node _T_1424 = or(_T_1423, _T_1409) @[Parameters.scala 134:30] + node _T_1425 = or(_T_1424, _T_1421) @[Parameters.scala 134:30] + node _T_1426 = or(_T_1425, reset) @[CoreplexNetwork.scala 33:15] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1428 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1429 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1431 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1432 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1434 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1436 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1437 = or(_T_1436, reset) @[CoreplexNetwork.scala 33:15] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1439 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1440 = not(_T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1441 = and(io.in[0].a.bits.mask, _T_1440) @[CoreplexNetwork.scala 33:15] + node _T_1443 = eq(_T_1441, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1444 = or(_T_1443, reset) @[CoreplexNetwork.scala 33:15] + node _T_1446 = eq(_T_1444, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1446 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1448 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 33:15] + when _T_1448 : @[CoreplexNetwork.scala 33:15] + node _T_1451 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1453 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1454 = and(_T_1451, _T_1453) @[Parameters.scala 63:37] + node _T_1455 = or(UInt<1>("h00"), _T_1454) @[Parameters.scala 132:31] + node _T_1457 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1458 = cvt(_T_1457) @[Parameters.scala 117:49] + node _T_1460 = and(_T_1458, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1461 = asSInt(_T_1460) @[Parameters.scala 117:52] + node _T_1463 = eq(_T_1461, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1465 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1466 = cvt(_T_1465) @[Parameters.scala 117:49] + node _T_1468 = and(_T_1466, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1469 = asSInt(_T_1468) @[Parameters.scala 117:52] + node _T_1471 = eq(_T_1469, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1473 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1474 = cvt(_T_1473) @[Parameters.scala 117:49] + node _T_1476 = and(_T_1474, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1477 = asSInt(_T_1476) @[Parameters.scala 117:52] + node _T_1479 = eq(_T_1477, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1480 = or(_T_1463, _T_1471) @[Parameters.scala 133:42] + node _T_1481 = or(_T_1480, _T_1479) @[Parameters.scala 133:42] + node _T_1482 = and(_T_1455, _T_1481) @[Parameters.scala 132:56] + node _T_1485 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1487 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1488 = cvt(_T_1487) @[Parameters.scala 117:49] + node _T_1490 = and(_T_1488, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1491 = asSInt(_T_1490) @[Parameters.scala 117:52] + node _T_1493 = eq(_T_1491, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1495 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1496 = cvt(_T_1495) @[Parameters.scala 117:49] + node _T_1498 = and(_T_1496, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1499 = asSInt(_T_1498) @[Parameters.scala 117:52] + node _T_1501 = eq(_T_1499, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1503 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1504 = cvt(_T_1503) @[Parameters.scala 117:49] + node _T_1506 = and(_T_1504, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1507 = asSInt(_T_1506) @[Parameters.scala 117:52] + node _T_1509 = eq(_T_1507, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1511 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1512 = cvt(_T_1511) @[Parameters.scala 117:49] + node _T_1514 = and(_T_1512, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1515 = asSInt(_T_1514) @[Parameters.scala 117:52] + node _T_1517 = eq(_T_1515, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1518 = or(_T_1493, _T_1501) @[Parameters.scala 133:42] + node _T_1519 = or(_T_1518, _T_1509) @[Parameters.scala 133:42] + node _T_1520 = or(_T_1519, _T_1517) @[Parameters.scala 133:42] + node _T_1521 = and(_T_1485, _T_1520) @[Parameters.scala 132:56] + node _T_1523 = or(UInt<1>("h00"), _T_1482) @[Parameters.scala 134:30] + node _T_1524 = or(_T_1523, _T_1521) @[Parameters.scala 134:30] + node _T_1525 = or(_T_1524, reset) @[CoreplexNetwork.scala 33:15] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1527 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1528 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1530 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1531 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1533 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1535 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1536 = or(_T_1535, reset) @[CoreplexNetwork.scala 33:15] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1538 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1539 = eq(io.in[0].a.bits.mask, _T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1540 = or(_T_1539, reset) @[CoreplexNetwork.scala 33:15] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1542 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1544 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + when _T_1544 : @[CoreplexNetwork.scala 33:15] + node _T_1547 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1549 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1550 = and(_T_1547, _T_1549) @[Parameters.scala 63:37] + node _T_1551 = or(UInt<1>("h00"), _T_1550) @[Parameters.scala 132:31] + node _T_1553 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1554 = cvt(_T_1553) @[Parameters.scala 117:49] + node _T_1556 = and(_T_1554, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1557 = asSInt(_T_1556) @[Parameters.scala 117:52] + node _T_1559 = eq(_T_1557, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1561 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1562 = cvt(_T_1561) @[Parameters.scala 117:49] + node _T_1564 = and(_T_1562, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1565 = asSInt(_T_1564) @[Parameters.scala 117:52] + node _T_1567 = eq(_T_1565, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1569 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1570 = cvt(_T_1569) @[Parameters.scala 117:49] + node _T_1572 = and(_T_1570, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1573 = asSInt(_T_1572) @[Parameters.scala 117:52] + node _T_1575 = eq(_T_1573, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1576 = or(_T_1559, _T_1567) @[Parameters.scala 133:42] + node _T_1577 = or(_T_1576, _T_1575) @[Parameters.scala 133:42] + node _T_1578 = and(_T_1551, _T_1577) @[Parameters.scala 132:56] + node _T_1581 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1583 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1584 = cvt(_T_1583) @[Parameters.scala 117:49] + node _T_1586 = and(_T_1584, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1587 = asSInt(_T_1586) @[Parameters.scala 117:52] + node _T_1589 = eq(_T_1587, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1591 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1592 = cvt(_T_1591) @[Parameters.scala 117:49] + node _T_1594 = and(_T_1592, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1595 = asSInt(_T_1594) @[Parameters.scala 117:52] + node _T_1597 = eq(_T_1595, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1599 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1600 = cvt(_T_1599) @[Parameters.scala 117:49] + node _T_1602 = and(_T_1600, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1603 = asSInt(_T_1602) @[Parameters.scala 117:52] + node _T_1605 = eq(_T_1603, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1607 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1608 = cvt(_T_1607) @[Parameters.scala 117:49] + node _T_1610 = and(_T_1608, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1611 = asSInt(_T_1610) @[Parameters.scala 117:52] + node _T_1613 = eq(_T_1611, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1614 = or(_T_1589, _T_1597) @[Parameters.scala 133:42] + node _T_1615 = or(_T_1614, _T_1605) @[Parameters.scala 133:42] + node _T_1616 = or(_T_1615, _T_1613) @[Parameters.scala 133:42] + node _T_1617 = and(_T_1581, _T_1616) @[Parameters.scala 132:56] + node _T_1619 = or(UInt<1>("h00"), _T_1578) @[Parameters.scala 134:30] + node _T_1620 = or(_T_1619, _T_1617) @[Parameters.scala 134:30] + node _T_1621 = or(_T_1620, reset) @[CoreplexNetwork.scala 33:15] + node _T_1623 = eq(_T_1621, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1623 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1624 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1626 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1627 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1629 = eq(_T_1627, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1629 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1631 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1632 = or(_T_1631, reset) @[CoreplexNetwork.scala 33:15] + node _T_1634 = eq(_T_1632, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1634 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1635 = eq(io.in[0].a.bits.mask, _T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1636 = or(_T_1635, reset) @[CoreplexNetwork.scala 33:15] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1638 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1640 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 33:15] + when _T_1640 : @[CoreplexNetwork.scala 33:15] + node _T_1643 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1645 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1646 = cvt(_T_1645) @[Parameters.scala 117:49] + node _T_1648 = and(_T_1646, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1649 = asSInt(_T_1648) @[Parameters.scala 117:52] + node _T_1651 = eq(_T_1649, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1653 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1654 = cvt(_T_1653) @[Parameters.scala 117:49] + node _T_1656 = and(_T_1654, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1657 = asSInt(_T_1656) @[Parameters.scala 117:52] + node _T_1659 = eq(_T_1657, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1661 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1662 = cvt(_T_1661) @[Parameters.scala 117:49] + node _T_1664 = and(_T_1662, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1665 = asSInt(_T_1664) @[Parameters.scala 117:52] + node _T_1667 = eq(_T_1665, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1669 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1670 = cvt(_T_1669) @[Parameters.scala 117:49] + node _T_1672 = and(_T_1670, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1673 = asSInt(_T_1672) @[Parameters.scala 117:52] + node _T_1675 = eq(_T_1673, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1677 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1678 = cvt(_T_1677) @[Parameters.scala 117:49] + node _T_1680 = and(_T_1678, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1681 = asSInt(_T_1680) @[Parameters.scala 117:52] + node _T_1683 = eq(_T_1681, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1685 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1686 = cvt(_T_1685) @[Parameters.scala 117:49] + node _T_1688 = and(_T_1686, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1689 = asSInt(_T_1688) @[Parameters.scala 117:52] + node _T_1691 = eq(_T_1689, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1692 = or(_T_1651, _T_1659) @[Parameters.scala 133:42] + node _T_1693 = or(_T_1692, _T_1667) @[Parameters.scala 133:42] + node _T_1694 = or(_T_1693, _T_1675) @[Parameters.scala 133:42] + node _T_1695 = or(_T_1694, _T_1683) @[Parameters.scala 133:42] + node _T_1696 = or(_T_1695, _T_1691) @[Parameters.scala 133:42] + node _T_1697 = and(_T_1643, _T_1696) @[Parameters.scala 132:56] + node _T_1699 = or(UInt<1>("h00"), _T_1697) @[Parameters.scala 134:30] + node _T_1700 = or(_T_1699, reset) @[CoreplexNetwork.scala 33:15] + node _T_1702 = eq(_T_1700, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1702 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1703 = or(_T_971[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_1705 = eq(_T_1703, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1705 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1706 = or(_T_982, reset) @[CoreplexNetwork.scala 33:15] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1708 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1709 = eq(io.in[0].a.bits.mask, _T_1050) @[CoreplexNetwork.scala 33:15] + node _T_1710 = or(_T_1709, reset) @[CoreplexNetwork.scala 33:15] + node _T_1712 = eq(_T_1710, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1712 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + when io.in[0].b.valid : @[CoreplexNetwork.scala 33:15] + node _T_1714 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1715 = or(_T_1714, reset) @[CoreplexNetwork.scala 33:15] + node _T_1717 = eq(_T_1715, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1717 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1719 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1720 = cvt(_T_1719) @[Parameters.scala 117:49] + node _T_1722 = and(_T_1720, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1723 = asSInt(_T_1722) @[Parameters.scala 117:52] + node _T_1725 = eq(_T_1723, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1727 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1728 = cvt(_T_1727) @[Parameters.scala 117:49] + node _T_1730 = and(_T_1728, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1731 = asSInt(_T_1730) @[Parameters.scala 117:52] + node _T_1733 = eq(_T_1731, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1735 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1736 = cvt(_T_1735) @[Parameters.scala 117:49] + node _T_1738 = and(_T_1736, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1739 = asSInt(_T_1738) @[Parameters.scala 117:52] + node _T_1741 = eq(_T_1739, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1743 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1744 = cvt(_T_1743) @[Parameters.scala 117:49] + node _T_1746 = and(_T_1744, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1747 = asSInt(_T_1746) @[Parameters.scala 117:52] + node _T_1749 = eq(_T_1747, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1751 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1752 = cvt(_T_1751) @[Parameters.scala 117:49] + node _T_1754 = and(_T_1752, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1755 = asSInt(_T_1754) @[Parameters.scala 117:52] + node _T_1757 = eq(_T_1755, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1759 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1760 = cvt(_T_1759) @[Parameters.scala 117:49] + node _T_1762 = and(_T_1760, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1763 = asSInt(_T_1762) @[Parameters.scala 117:52] + node _T_1765 = eq(_T_1763, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1767 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1768 = cvt(_T_1767) @[Parameters.scala 117:49] + node _T_1770 = and(_T_1768, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1771 = asSInt(_T_1770) @[Parameters.scala 117:52] + node _T_1773 = eq(_T_1771, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1776 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1776 is invalid @[Parameters.scala 110:36] + _T_1776[0] <= _T_1725 @[Parameters.scala 110:36] + _T_1776[1] <= _T_1733 @[Parameters.scala 110:36] + _T_1776[2] <= _T_1741 @[Parameters.scala 110:36] + _T_1776[3] <= _T_1749 @[Parameters.scala 110:36] + _T_1776[4] <= _T_1757 @[Parameters.scala 110:36] + _T_1776[5] <= _T_1765 @[Parameters.scala 110:36] + _T_1776[6] <= _T_1773 @[Parameters.scala 110:36] + node _T_1786 = or(_T_1776[0], _T_1776[1]) @[Parameters.scala 119:64] + node _T_1787 = or(_T_1786, _T_1776[2]) @[Parameters.scala 119:64] + node _T_1788 = or(_T_1787, _T_1776[3]) @[Parameters.scala 119:64] + node _T_1789 = or(_T_1788, _T_1776[4]) @[Parameters.scala 119:64] + node _T_1790 = or(_T_1789, _T_1776[5]) @[Parameters.scala 119:64] + node _T_1791 = or(_T_1790, _T_1776[6]) @[Parameters.scala 119:64] + node _T_1793 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1794 = dshl(_T_1793, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1795 = bits(_T_1794, 7, 0) @[package.scala 19:76] + node _T_1796 = not(_T_1795) @[package.scala 19:40] + node _T_1797 = and(io.in[0].b.bits.address, _T_1796) @[Edges.scala 17:16] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1801 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1802 = dshl(UInt<1>("h01"), _T_1801) @[OneHot.scala 49:12] + node _T_1803 = bits(_T_1802, 2, 0) @[OneHot.scala 49:37] + node _T_1805 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1807 = bits(_T_1803, 2, 2) @[package.scala 44:26] + node _T_1808 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[package.scala 46:20] + node _T_1811 = and(UInt<1>("h01"), _T_1810) @[package.scala 49:27] + node _T_1812 = and(_T_1807, _T_1811) @[package.scala 50:38] + node _T_1813 = or(_T_1805, _T_1812) @[package.scala 50:29] + node _T_1814 = and(UInt<1>("h01"), _T_1808) @[package.scala 49:27] + node _T_1815 = and(_T_1807, _T_1814) @[package.scala 50:38] + node _T_1816 = or(_T_1805, _T_1815) @[package.scala 50:29] + node _T_1817 = bits(_T_1803, 1, 1) @[package.scala 44:26] + node _T_1818 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[package.scala 46:20] + node _T_1821 = and(_T_1811, _T_1820) @[package.scala 49:27] + node _T_1822 = and(_T_1817, _T_1821) @[package.scala 50:38] + node _T_1823 = or(_T_1813, _T_1822) @[package.scala 50:29] + node _T_1824 = and(_T_1811, _T_1818) @[package.scala 49:27] + node _T_1825 = and(_T_1817, _T_1824) @[package.scala 50:38] + node _T_1826 = or(_T_1813, _T_1825) @[package.scala 50:29] + node _T_1827 = and(_T_1814, _T_1820) @[package.scala 49:27] + node _T_1828 = and(_T_1817, _T_1827) @[package.scala 50:38] + node _T_1829 = or(_T_1816, _T_1828) @[package.scala 50:29] + node _T_1830 = and(_T_1814, _T_1818) @[package.scala 49:27] + node _T_1831 = and(_T_1817, _T_1830) @[package.scala 50:38] + node _T_1832 = or(_T_1816, _T_1831) @[package.scala 50:29] + node _T_1833 = bits(_T_1803, 0, 0) @[package.scala 44:26] + node _T_1834 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1836 = eq(_T_1834, UInt<1>("h00")) @[package.scala 46:20] + node _T_1837 = and(_T_1821, _T_1836) @[package.scala 49:27] + node _T_1838 = and(_T_1833, _T_1837) @[package.scala 50:38] + node _T_1839 = or(_T_1823, _T_1838) @[package.scala 50:29] + node _T_1840 = and(_T_1821, _T_1834) @[package.scala 49:27] + node _T_1841 = and(_T_1833, _T_1840) @[package.scala 50:38] + node _T_1842 = or(_T_1823, _T_1841) @[package.scala 50:29] + node _T_1843 = and(_T_1824, _T_1836) @[package.scala 49:27] + node _T_1844 = and(_T_1833, _T_1843) @[package.scala 50:38] + node _T_1845 = or(_T_1826, _T_1844) @[package.scala 50:29] + node _T_1846 = and(_T_1824, _T_1834) @[package.scala 49:27] + node _T_1847 = and(_T_1833, _T_1846) @[package.scala 50:38] + node _T_1848 = or(_T_1826, _T_1847) @[package.scala 50:29] + node _T_1849 = and(_T_1827, _T_1836) @[package.scala 49:27] + node _T_1850 = and(_T_1833, _T_1849) @[package.scala 50:38] + node _T_1851 = or(_T_1829, _T_1850) @[package.scala 50:29] + node _T_1852 = and(_T_1827, _T_1834) @[package.scala 49:27] + node _T_1853 = and(_T_1833, _T_1852) @[package.scala 50:38] + node _T_1854 = or(_T_1829, _T_1853) @[package.scala 50:29] + node _T_1855 = and(_T_1830, _T_1836) @[package.scala 49:27] + node _T_1856 = and(_T_1833, _T_1855) @[package.scala 50:38] + node _T_1857 = or(_T_1832, _T_1856) @[package.scala 50:29] + node _T_1858 = and(_T_1830, _T_1834) @[package.scala 49:27] + node _T_1859 = and(_T_1833, _T_1858) @[package.scala 50:38] + node _T_1860 = or(_T_1832, _T_1859) @[package.scala 50:29] + node _T_1861 = cat(_T_1842, _T_1839) @[Cat.scala 30:58] + node _T_1862 = cat(_T_1848, _T_1845) @[Cat.scala 30:58] + node _T_1863 = cat(_T_1862, _T_1861) @[Cat.scala 30:58] + node _T_1864 = cat(_T_1854, _T_1851) @[Cat.scala 30:58] + node _T_1865 = cat(_T_1860, _T_1857) @[Cat.scala 30:58] + node _T_1866 = cat(_T_1865, _T_1864) @[Cat.scala 30:58] + node _T_1867 = cat(_T_1866, _T_1863) @[Cat.scala 30:58] + node _T_1869 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + when _T_1869 : @[CoreplexNetwork.scala 33:15] + node _T_1871 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1873 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1874 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1876 = eq(_T_1874, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1876 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1878 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_1879 = or(_T_1878, reset) @[CoreplexNetwork.scala 33:15] + node _T_1881 = eq(_T_1879, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1881 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1882 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1884 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1886 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1887 = or(_T_1886, reset) @[CoreplexNetwork.scala 33:15] + node _T_1889 = eq(_T_1887, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1889 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1890 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 33:15] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1893 = or(_T_1892, reset) @[CoreplexNetwork.scala 33:15] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1895 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1897 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 33:15] + when _T_1897 : @[CoreplexNetwork.scala 33:15] + node _T_1899 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1901 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1902 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1904 = eq(_T_1902, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1904 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1905 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1907 = eq(_T_1905, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1907 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1909 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1910 = or(_T_1909, reset) @[CoreplexNetwork.scala 33:15] + node _T_1912 = eq(_T_1910, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1912 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1913 = eq(io.in[0].b.bits.mask, _T_1867) @[CoreplexNetwork.scala 33:15] + node _T_1914 = or(_T_1913, reset) @[CoreplexNetwork.scala 33:15] + node _T_1916 = eq(_T_1914, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1916 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1918 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1918 : @[CoreplexNetwork.scala 33:15] + node _T_1920 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1922 = eq(_T_1920, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1922 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1923 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1925 = eq(_T_1923, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1925 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1926 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1928 = eq(_T_1926, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1928 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1930 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1931 = or(_T_1930, reset) @[CoreplexNetwork.scala 33:15] + node _T_1933 = eq(_T_1931, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1933 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1934 = eq(io.in[0].b.bits.mask, _T_1867) @[CoreplexNetwork.scala 33:15] + node _T_1935 = or(_T_1934, reset) @[CoreplexNetwork.scala 33:15] + node _T_1937 = eq(_T_1935, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1937 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1939 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 33:15] + when _T_1939 : @[CoreplexNetwork.scala 33:15] + node _T_1941 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1943 = eq(_T_1941, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1943 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1944 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1946 = eq(_T_1944, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1946 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1947 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1949 = eq(_T_1947, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1949 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1951 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1952 = or(_T_1951, reset) @[CoreplexNetwork.scala 33:15] + node _T_1954 = eq(_T_1952, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1954 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1955 = not(_T_1867) @[CoreplexNetwork.scala 33:15] + node _T_1956 = and(io.in[0].b.bits.mask, _T_1955) @[CoreplexNetwork.scala 33:15] + node _T_1958 = eq(_T_1956, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_1959 = or(_T_1958, reset) @[CoreplexNetwork.scala 33:15] + node _T_1961 = eq(_T_1959, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1961 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1963 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 33:15] + when _T_1963 : @[CoreplexNetwork.scala 33:15] + node _T_1965 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1967 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1968 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1970 = eq(_T_1968, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1970 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1971 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1973 = eq(_T_1971, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1973 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1975 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1976 = or(_T_1975, reset) @[CoreplexNetwork.scala 33:15] + node _T_1978 = eq(_T_1976, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1978 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1979 = eq(io.in[0].b.bits.mask, _T_1867) @[CoreplexNetwork.scala 33:15] + node _T_1980 = or(_T_1979, reset) @[CoreplexNetwork.scala 33:15] + node _T_1982 = eq(_T_1980, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1982 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1984 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + when _T_1984 : @[CoreplexNetwork.scala 33:15] + node _T_1986 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1988 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1989 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_1991 = eq(_T_1989, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1991 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1992 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_1994 = eq(_T_1992, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1994 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_1996 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1997 = or(_T_1996, reset) @[CoreplexNetwork.scala 33:15] + node _T_1999 = eq(_T_1997, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_1999 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2000 = eq(io.in[0].b.bits.mask, _T_1867) @[CoreplexNetwork.scala 33:15] + node _T_2001 = or(_T_2000, reset) @[CoreplexNetwork.scala 33:15] + node _T_2003 = eq(_T_2001, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2003 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2005 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 33:15] + when _T_2005 : @[CoreplexNetwork.scala 33:15] + node _T_2007 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 33:15] + node _T_2009 = eq(_T_2007, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2009 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2010 = or(_T_1791, reset) @[CoreplexNetwork.scala 33:15] + node _T_2012 = eq(_T_2010, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2012 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2013 = or(_T_1799, reset) @[CoreplexNetwork.scala 33:15] + node _T_2015 = eq(_T_2013, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2015 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2016 = eq(io.in[0].b.bits.mask, _T_1867) @[CoreplexNetwork.scala 33:15] + node _T_2017 = or(_T_2016, reset) @[CoreplexNetwork.scala 33:15] + node _T_2019 = eq(_T_2017, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2019 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + when io.in[0].c.valid : @[CoreplexNetwork.scala 33:15] + node _T_2021 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_2022 = or(_T_2021, reset) @[CoreplexNetwork.scala 33:15] + node _T_2024 = eq(_T_2022, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2024 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2026 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_2027 = not(_T_2026) @[Parameters.scala 37:9] + node _T_2029 = or(_T_2027, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_2030 = not(_T_2029) @[Parameters.scala 37:7] + node _T_2032 = eq(_T_2030, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2035 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2035 is invalid @[Parameters.scala 228:27] + _T_2035[0] <= _T_2032 @[Parameters.scala 228:27] + node _T_2040 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2041 = dshl(_T_2040, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2042 = bits(_T_2041, 7, 0) @[package.scala 19:76] + node _T_2043 = not(_T_2042) @[package.scala 19:40] + node _T_2044 = and(io.in[0].c.bits.address, _T_2043) @[Edges.scala 17:16] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2048 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2049 = cvt(_T_2048) @[Parameters.scala 117:49] + node _T_2051 = and(_T_2049, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_2052 = asSInt(_T_2051) @[Parameters.scala 117:52] + node _T_2054 = eq(_T_2052, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2056 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2057 = cvt(_T_2056) @[Parameters.scala 117:49] + node _T_2059 = and(_T_2057, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2060 = asSInt(_T_2059) @[Parameters.scala 117:52] + node _T_2062 = eq(_T_2060, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2064 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2065 = cvt(_T_2064) @[Parameters.scala 117:49] + node _T_2067 = and(_T_2065, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_2068 = asSInt(_T_2067) @[Parameters.scala 117:52] + node _T_2070 = eq(_T_2068, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2072 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2073 = cvt(_T_2072) @[Parameters.scala 117:49] + node _T_2075 = and(_T_2073, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2076 = asSInt(_T_2075) @[Parameters.scala 117:52] + node _T_2078 = eq(_T_2076, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2080 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2081 = cvt(_T_2080) @[Parameters.scala 117:49] + node _T_2083 = and(_T_2081, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2084 = asSInt(_T_2083) @[Parameters.scala 117:52] + node _T_2086 = eq(_T_2084, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2088 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2089 = cvt(_T_2088) @[Parameters.scala 117:49] + node _T_2091 = and(_T_2089, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2092 = asSInt(_T_2091) @[Parameters.scala 117:52] + node _T_2094 = eq(_T_2092, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2096 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2097 = cvt(_T_2096) @[Parameters.scala 117:49] + node _T_2099 = and(_T_2097, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2100 = asSInt(_T_2099) @[Parameters.scala 117:52] + node _T_2102 = eq(_T_2100, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_2105 : UInt<1>[7] @[Parameters.scala 110:36] + _T_2105 is invalid @[Parameters.scala 110:36] + _T_2105[0] <= _T_2054 @[Parameters.scala 110:36] + _T_2105[1] <= _T_2062 @[Parameters.scala 110:36] + _T_2105[2] <= _T_2070 @[Parameters.scala 110:36] + _T_2105[3] <= _T_2078 @[Parameters.scala 110:36] + _T_2105[4] <= _T_2086 @[Parameters.scala 110:36] + _T_2105[5] <= _T_2094 @[Parameters.scala 110:36] + _T_2105[6] <= _T_2102 @[Parameters.scala 110:36] + node _T_2115 = or(_T_2105[0], _T_2105[1]) @[Parameters.scala 119:64] + node _T_2116 = or(_T_2115, _T_2105[2]) @[Parameters.scala 119:64] + node _T_2117 = or(_T_2116, _T_2105[3]) @[Parameters.scala 119:64] + node _T_2118 = or(_T_2117, _T_2105[4]) @[Parameters.scala 119:64] + node _T_2119 = or(_T_2118, _T_2105[5]) @[Parameters.scala 119:64] + node _T_2120 = or(_T_2119, _T_2105[6]) @[Parameters.scala 119:64] + node _T_2122 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 33:15] + when _T_2122 : @[CoreplexNetwork.scala 33:15] + node _T_2123 = or(_T_2120, reset) @[CoreplexNetwork.scala 33:15] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2125 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2126 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2128 = eq(_T_2126, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2128 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2130 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2131 = or(_T_2130, reset) @[CoreplexNetwork.scala 33:15] + node _T_2133 = eq(_T_2131, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2133 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2134 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2136 = eq(_T_2134, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2136 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2138 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2139 = or(_T_2138, reset) @[CoreplexNetwork.scala 33:15] + node _T_2141 = eq(_T_2139, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2141 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2143 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2144 = or(_T_2143, reset) @[CoreplexNetwork.scala 33:15] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2146 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2148 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 33:15] + when _T_2148 : @[CoreplexNetwork.scala 33:15] + node _T_2149 = or(_T_2120, reset) @[CoreplexNetwork.scala 33:15] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2151 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2152 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2154 = eq(_T_2152, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2154 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2156 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2157 = or(_T_2156, reset) @[CoreplexNetwork.scala 33:15] + node _T_2159 = eq(_T_2157, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2159 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2160 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2162 = eq(_T_2160, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2162 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2164 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2165 = or(_T_2164, reset) @[CoreplexNetwork.scala 33:15] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2167 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2169 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2170 = or(_T_2169, reset) @[CoreplexNetwork.scala 33:15] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2172 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2174 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + when _T_2174 : @[CoreplexNetwork.scala 33:15] + node _T_2177 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2179 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2180 = and(_T_2177, _T_2179) @[Parameters.scala 63:37] + node _T_2181 = or(UInt<1>("h00"), _T_2180) @[Parameters.scala 132:31] + node _T_2183 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2184 = cvt(_T_2183) @[Parameters.scala 117:49] + node _T_2186 = and(_T_2184, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2187 = asSInt(_T_2186) @[Parameters.scala 117:52] + node _T_2189 = eq(_T_2187, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2191 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2192 = cvt(_T_2191) @[Parameters.scala 117:49] + node _T_2194 = and(_T_2192, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2195 = asSInt(_T_2194) @[Parameters.scala 117:52] + node _T_2197 = eq(_T_2195, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2198 = or(_T_2189, _T_2197) @[Parameters.scala 133:42] + node _T_2199 = and(_T_2181, _T_2198) @[Parameters.scala 132:56] + node _T_2202 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2204 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2205 = cvt(_T_2204) @[Parameters.scala 117:49] + node _T_2207 = and(_T_2205, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2208 = asSInt(_T_2207) @[Parameters.scala 117:52] + node _T_2210 = eq(_T_2208, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2212 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2213 = cvt(_T_2212) @[Parameters.scala 117:49] + node _T_2215 = and(_T_2213, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2216 = asSInt(_T_2215) @[Parameters.scala 117:52] + node _T_2218 = eq(_T_2216, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2220 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2221 = cvt(_T_2220) @[Parameters.scala 117:49] + node _T_2223 = and(_T_2221, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2224 = asSInt(_T_2223) @[Parameters.scala 117:52] + node _T_2226 = eq(_T_2224, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2228 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2229 = cvt(_T_2228) @[Parameters.scala 117:49] + node _T_2231 = and(_T_2229, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2232 = asSInt(_T_2231) @[Parameters.scala 117:52] + node _T_2234 = eq(_T_2232, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2235 = or(_T_2210, _T_2218) @[Parameters.scala 133:42] + node _T_2236 = or(_T_2235, _T_2226) @[Parameters.scala 133:42] + node _T_2237 = or(_T_2236, _T_2234) @[Parameters.scala 133:42] + node _T_2238 = and(_T_2202, _T_2237) @[Parameters.scala 132:56] + node _T_2240 = or(UInt<1>("h00"), _T_2199) @[Parameters.scala 134:30] + node _T_2241 = or(_T_2240, _T_2238) @[Parameters.scala 134:30] + node _T_2242 = or(_T_2241, reset) @[CoreplexNetwork.scala 33:15] + node _T_2244 = eq(_T_2242, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2244 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2245 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2247 = eq(_T_2245, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2247 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2249 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2250 = or(_T_2249, reset) @[CoreplexNetwork.scala 33:15] + node _T_2252 = eq(_T_2250, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2252 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2253 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2255 = eq(_T_2253, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2255 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2257 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2258 = or(_T_2257, reset) @[CoreplexNetwork.scala 33:15] + node _T_2260 = eq(_T_2258, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2260 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2262 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2263 = or(_T_2262, reset) @[CoreplexNetwork.scala 33:15] + node _T_2265 = eq(_T_2263, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2265 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2267 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 33:15] + when _T_2267 : @[CoreplexNetwork.scala 33:15] + node _T_2270 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2272 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2273 = and(_T_2270, _T_2272) @[Parameters.scala 63:37] + node _T_2274 = or(UInt<1>("h00"), _T_2273) @[Parameters.scala 132:31] + node _T_2276 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2277 = cvt(_T_2276) @[Parameters.scala 117:49] + node _T_2279 = and(_T_2277, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2280 = asSInt(_T_2279) @[Parameters.scala 117:52] + node _T_2282 = eq(_T_2280, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2284 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2285 = cvt(_T_2284) @[Parameters.scala 117:49] + node _T_2287 = and(_T_2285, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2288 = asSInt(_T_2287) @[Parameters.scala 117:52] + node _T_2290 = eq(_T_2288, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2291 = or(_T_2282, _T_2290) @[Parameters.scala 133:42] + node _T_2292 = and(_T_2274, _T_2291) @[Parameters.scala 132:56] + node _T_2295 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2297 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2298 = cvt(_T_2297) @[Parameters.scala 117:49] + node _T_2300 = and(_T_2298, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2301 = asSInt(_T_2300) @[Parameters.scala 117:52] + node _T_2303 = eq(_T_2301, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2305 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2306 = cvt(_T_2305) @[Parameters.scala 117:49] + node _T_2308 = and(_T_2306, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2309 = asSInt(_T_2308) @[Parameters.scala 117:52] + node _T_2311 = eq(_T_2309, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2313 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2314 = cvt(_T_2313) @[Parameters.scala 117:49] + node _T_2316 = and(_T_2314, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2317 = asSInt(_T_2316) @[Parameters.scala 117:52] + node _T_2319 = eq(_T_2317, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2321 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2322 = cvt(_T_2321) @[Parameters.scala 117:49] + node _T_2324 = and(_T_2322, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2325 = asSInt(_T_2324) @[Parameters.scala 117:52] + node _T_2327 = eq(_T_2325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2328 = or(_T_2303, _T_2311) @[Parameters.scala 133:42] + node _T_2329 = or(_T_2328, _T_2319) @[Parameters.scala 133:42] + node _T_2330 = or(_T_2329, _T_2327) @[Parameters.scala 133:42] + node _T_2331 = and(_T_2295, _T_2330) @[Parameters.scala 132:56] + node _T_2333 = or(UInt<1>("h00"), _T_2292) @[Parameters.scala 134:30] + node _T_2334 = or(_T_2333, _T_2331) @[Parameters.scala 134:30] + node _T_2335 = or(_T_2334, reset) @[CoreplexNetwork.scala 33:15] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2337 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2338 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2340 = eq(_T_2338, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2340 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2342 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2343 = or(_T_2342, reset) @[CoreplexNetwork.scala 33:15] + node _T_2345 = eq(_T_2343, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2345 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2346 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2348 = eq(_T_2346, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2348 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2350 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2351 = or(_T_2350, reset) @[CoreplexNetwork.scala 33:15] + node _T_2353 = eq(_T_2351, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2353 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2355 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2356 = or(_T_2355, reset) @[CoreplexNetwork.scala 33:15] + node _T_2358 = eq(_T_2356, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2358 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2360 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2360 : @[CoreplexNetwork.scala 33:15] + node _T_2361 = or(_T_2120, reset) @[CoreplexNetwork.scala 33:15] + node _T_2363 = eq(_T_2361, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2363 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2364 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2366 = eq(_T_2364, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2366 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2367 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2369 = eq(_T_2367, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2369 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2371 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2372 = or(_T_2371, reset) @[CoreplexNetwork.scala 33:15] + node _T_2374 = eq(_T_2372, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2374 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2376 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 33:15] + when _T_2376 : @[CoreplexNetwork.scala 33:15] + node _T_2377 = or(_T_2120, reset) @[CoreplexNetwork.scala 33:15] + node _T_2379 = eq(_T_2377, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2379 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2380 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2382 = eq(_T_2380, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2382 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2383 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2385 = eq(_T_2383, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2385 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2387 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2388 = or(_T_2387, reset) @[CoreplexNetwork.scala 33:15] + node _T_2390 = eq(_T_2388, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2390 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2392 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 33:15] + when _T_2392 : @[CoreplexNetwork.scala 33:15] + node _T_2393 = or(_T_2120, reset) @[CoreplexNetwork.scala 33:15] + node _T_2395 = eq(_T_2393, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2395 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2396 = or(_T_2035[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2398 = eq(_T_2396, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2398 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2399 = or(_T_2046, reset) @[CoreplexNetwork.scala 33:15] + node _T_2401 = eq(_T_2399, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2401 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2403 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2404 = or(_T_2403, reset) @[CoreplexNetwork.scala 33:15] + node _T_2406 = eq(_T_2404, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2406 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2408 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2409 = or(_T_2408, reset) @[CoreplexNetwork.scala 33:15] + node _T_2411 = eq(_T_2409, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2411 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + when io.in[0].d.valid : @[CoreplexNetwork.scala 33:15] + node _T_2413 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2414 = or(_T_2413, reset) @[CoreplexNetwork.scala 33:15] + node _T_2416 = eq(_T_2414, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2416 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2418 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_2419 = not(_T_2418) @[Parameters.scala 37:9] + node _T_2421 = or(_T_2419, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_2422 = not(_T_2421) @[Parameters.scala 37:7] + node _T_2424 = eq(_T_2422, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2427 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2427 is invalid @[Parameters.scala 228:27] + _T_2427[0] <= _T_2424 @[Parameters.scala 228:27] + node _T_2432 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2433 = dshl(_T_2432, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2434 = bits(_T_2433, 7, 0) @[package.scala 19:76] + node _T_2435 = not(_T_2434) @[package.scala 19:40] + node _T_2436 = and(io.in[0].d.bits.addr_lo, _T_2435) @[Edges.scala 17:16] + node _T_2438 = eq(_T_2436, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2440 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[CoreplexNetwork.scala 33:15] + node _T_2442 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + when _T_2442 : @[CoreplexNetwork.scala 33:15] + node _T_2443 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2445 = eq(_T_2443, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2445 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2446 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2448 = eq(_T_2446, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2448 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2449 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2451 = eq(_T_2449, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2451 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2453 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2454 = or(_T_2453, reset) @[CoreplexNetwork.scala 33:15] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2456 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2458 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2459 = or(_T_2458, reset) @[CoreplexNetwork.scala 33:15] + node _T_2461 = eq(_T_2459, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2461 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2463 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2464 = or(_T_2463, reset) @[CoreplexNetwork.scala 33:15] + node _T_2466 = eq(_T_2464, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2466 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2468 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 33:15] + when _T_2468 : @[CoreplexNetwork.scala 33:15] + node _T_2469 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2471 = eq(_T_2469, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2471 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2472 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2474 = eq(_T_2472, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2474 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2475 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2477 = eq(_T_2475, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2477 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2479 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2480 = or(_T_2479, reset) @[CoreplexNetwork.scala 33:15] + node _T_2482 = eq(_T_2480, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2482 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2484 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2485 = or(_T_2484, reset) @[CoreplexNetwork.scala 33:15] + node _T_2487 = eq(_T_2485, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2487 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2489 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 33:15] + when _T_2489 : @[CoreplexNetwork.scala 33:15] + node _T_2490 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2492 = eq(_T_2490, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2492 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2493 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2495 = eq(_T_2493, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2495 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2496 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2498 = eq(_T_2496, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2498 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2500 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 33:15] + node _T_2501 = or(_T_2500, reset) @[CoreplexNetwork.scala 33:15] + node _T_2503 = eq(_T_2501, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2503 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2505 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2506 = or(_T_2505, reset) @[CoreplexNetwork.scala 33:15] + node _T_2508 = eq(_T_2506, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2508 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2510 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2510 : @[CoreplexNetwork.scala 33:15] + node _T_2511 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2513 = eq(_T_2511, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2513 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2514 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2516 = eq(_T_2514, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2516 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2517 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2519 = eq(_T_2517, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2519 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2521 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2522 = or(_T_2521, reset) @[CoreplexNetwork.scala 33:15] + node _T_2524 = eq(_T_2522, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2524 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2526 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 33:15] + when _T_2526 : @[CoreplexNetwork.scala 33:15] + node _T_2527 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2529 = eq(_T_2527, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2529 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2530 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2532 = eq(_T_2530, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2532 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2533 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2535 = eq(_T_2533, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2535 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2537 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2538 = or(_T_2537, reset) @[CoreplexNetwork.scala 33:15] + node _T_2540 = eq(_T_2538, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2540 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2542 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 33:15] + when _T_2542 : @[CoreplexNetwork.scala 33:15] + node _T_2543 = or(_T_2427[0], reset) @[CoreplexNetwork.scala 33:15] + node _T_2545 = eq(_T_2543, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2545 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2546 = or(_T_2438, reset) @[CoreplexNetwork.scala 33:15] + node _T_2548 = eq(_T_2546, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2548 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2549 = or(_T_2440, reset) @[CoreplexNetwork.scala 33:15] + node _T_2551 = eq(_T_2549, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2551 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2553 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2554 = or(_T_2553, reset) @[CoreplexNetwork.scala 33:15] + node _T_2556 = eq(_T_2554, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2556 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2558 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2559 = or(_T_2558, reset) @[CoreplexNetwork.scala 33:15] + node _T_2561 = eq(_T_2559, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2561 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + when io.in[0].e.valid : @[CoreplexNetwork.scala 33:15] + node _T_2563 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[CoreplexNetwork.scala 33:15] + node _T_2564 = or(_T_2563, reset) @[CoreplexNetwork.scala 33:15] + node _T_2566 = eq(_T_2564, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2566 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2567 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2569 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2570 = dshl(_T_2569, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2571 = bits(_T_2570, 7, 0) @[package.scala 19:76] + node _T_2572 = not(_T_2571) @[package.scala 19:40] + node _T_2573 = shr(_T_2572, 3) @[Edges.scala 198:59] + node _T_2574 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2576 = eq(_T_2574, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2578 = mux(_T_2576, _T_2573, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2580 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2582 = sub(_T_2580, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2583 = asUInt(_T_2582) @[Edges.scala 208:28] + node _T_2584 = tail(_T_2583, 1) @[Edges.scala 208:28] + node _T_2586 = eq(_T_2580, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2588 = eq(_T_2580, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2590 = eq(_T_2578, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2591 = or(_T_2588, _T_2590) @[Edges.scala 210:37] + node _T_2592 = and(_T_2591, _T_2567) @[Edges.scala 211:22] + node _T_2593 = not(_T_2584) @[Edges.scala 212:27] + node _T_2594 = and(_T_2578, _T_2593) @[Edges.scala 212:25] + when _T_2567 : @[Edges.scala 213:17] + node _T_2595 = mux(_T_2586, _T_2578, _T_2584) @[Edges.scala 214:21] + _T_2580 <= _T_2595 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2597 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2599 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2601 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2603 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2605 : UInt, clock @[CoreplexNetwork.scala 33:15] + node _T_2607 = eq(_T_2586, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2608 = and(io.in[0].a.valid, _T_2607) @[CoreplexNetwork.scala 33:15] + when _T_2608 : @[CoreplexNetwork.scala 33:15] + node _T_2609 = eq(io.in[0].a.bits.opcode, _T_2597) @[CoreplexNetwork.scala 33:15] + node _T_2610 = or(_T_2609, reset) @[CoreplexNetwork.scala 33:15] + node _T_2612 = eq(_T_2610, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2612 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2613 = eq(io.in[0].a.bits.param, _T_2599) @[CoreplexNetwork.scala 33:15] + node _T_2614 = or(_T_2613, reset) @[CoreplexNetwork.scala 33:15] + node _T_2616 = eq(_T_2614, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2616 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2617 = eq(io.in[0].a.bits.size, _T_2601) @[CoreplexNetwork.scala 33:15] + node _T_2618 = or(_T_2617, reset) @[CoreplexNetwork.scala 33:15] + node _T_2620 = eq(_T_2618, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2620 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2621 = eq(io.in[0].a.bits.source, _T_2603) @[CoreplexNetwork.scala 33:15] + node _T_2622 = or(_T_2621, reset) @[CoreplexNetwork.scala 33:15] + node _T_2624 = eq(_T_2622, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2624 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2625 = eq(io.in[0].a.bits.address, _T_2605) @[CoreplexNetwork.scala 33:15] + node _T_2626 = or(_T_2625, reset) @[CoreplexNetwork.scala 33:15] + node _T_2628 = eq(_T_2626, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2628 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2629 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2630 = and(_T_2629, _T_2586) @[CoreplexNetwork.scala 33:15] + when _T_2630 : @[CoreplexNetwork.scala 33:15] + _T_2597 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 33:15] + _T_2599 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 33:15] + _T_2601 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 33:15] + _T_2603 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 33:15] + _T_2605 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2631 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2633 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2634 = dshl(_T_2633, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2635 = bits(_T_2634, 7, 0) @[package.scala 19:76] + node _T_2636 = not(_T_2635) @[package.scala 19:40] + node _T_2637 = shr(_T_2636, 3) @[Edges.scala 198:59] + node _T_2638 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2640 = eq(_T_2638, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2643 = mux(UInt<1>("h00"), _T_2637, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2645 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2647 = sub(_T_2645, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2648 = asUInt(_T_2647) @[Edges.scala 208:28] + node _T_2649 = tail(_T_2648, 1) @[Edges.scala 208:28] + node _T_2651 = eq(_T_2645, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2653 = eq(_T_2645, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2655 = eq(_T_2643, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2656 = or(_T_2653, _T_2655) @[Edges.scala 210:37] + node _T_2657 = and(_T_2656, _T_2631) @[Edges.scala 211:22] + node _T_2658 = not(_T_2649) @[Edges.scala 212:27] + node _T_2659 = and(_T_2643, _T_2658) @[Edges.scala 212:25] + when _T_2631 : @[Edges.scala 213:17] + node _T_2660 = mux(_T_2651, _T_2643, _T_2649) @[Edges.scala 214:21] + _T_2645 <= _T_2660 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2662 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2664 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2666 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2668 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2670 : UInt, clock @[CoreplexNetwork.scala 33:15] + node _T_2672 = eq(_T_2651, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2673 = and(io.in[0].b.valid, _T_2672) @[CoreplexNetwork.scala 33:15] + when _T_2673 : @[CoreplexNetwork.scala 33:15] + node _T_2674 = eq(io.in[0].b.bits.opcode, _T_2662) @[CoreplexNetwork.scala 33:15] + node _T_2675 = or(_T_2674, reset) @[CoreplexNetwork.scala 33:15] + node _T_2677 = eq(_T_2675, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2677 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2678 = eq(io.in[0].b.bits.param, _T_2664) @[CoreplexNetwork.scala 33:15] + node _T_2679 = or(_T_2678, reset) @[CoreplexNetwork.scala 33:15] + node _T_2681 = eq(_T_2679, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2681 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2682 = eq(io.in[0].b.bits.size, _T_2666) @[CoreplexNetwork.scala 33:15] + node _T_2683 = or(_T_2682, reset) @[CoreplexNetwork.scala 33:15] + node _T_2685 = eq(_T_2683, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2685 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2686 = eq(io.in[0].b.bits.source, _T_2668) @[CoreplexNetwork.scala 33:15] + node _T_2687 = or(_T_2686, reset) @[CoreplexNetwork.scala 33:15] + node _T_2689 = eq(_T_2687, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2689 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2690 = eq(io.in[0].b.bits.address, _T_2670) @[CoreplexNetwork.scala 33:15] + node _T_2691 = or(_T_2690, reset) @[CoreplexNetwork.scala 33:15] + node _T_2693 = eq(_T_2691, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2693 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2694 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2695 = and(_T_2694, _T_2651) @[CoreplexNetwork.scala 33:15] + when _T_2695 : @[CoreplexNetwork.scala 33:15] + _T_2662 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 33:15] + _T_2664 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 33:15] + _T_2666 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 33:15] + _T_2668 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 33:15] + _T_2670 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2696 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2698 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2699 = dshl(_T_2698, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2700 = bits(_T_2699, 7, 0) @[package.scala 19:76] + node _T_2701 = not(_T_2700) @[package.scala 19:40] + node _T_2702 = shr(_T_2701, 3) @[Edges.scala 198:59] + node _T_2703 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2706 = mux(UInt<1>("h00"), _T_2702, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2708 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2710 = sub(_T_2708, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2711 = asUInt(_T_2710) @[Edges.scala 208:28] + node _T_2712 = tail(_T_2711, 1) @[Edges.scala 208:28] + node _T_2714 = eq(_T_2708, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2716 = eq(_T_2708, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2718 = eq(_T_2706, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2719 = or(_T_2716, _T_2718) @[Edges.scala 210:37] + node _T_2720 = and(_T_2719, _T_2696) @[Edges.scala 211:22] + node _T_2721 = not(_T_2712) @[Edges.scala 212:27] + node _T_2722 = and(_T_2706, _T_2721) @[Edges.scala 212:25] + when _T_2696 : @[Edges.scala 213:17] + node _T_2723 = mux(_T_2714, _T_2706, _T_2712) @[Edges.scala 214:21] + _T_2708 <= _T_2723 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2725 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2727 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2729 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2731 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2733 : UInt, clock @[CoreplexNetwork.scala 33:15] + node _T_2735 = eq(_T_2714, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2736 = and(io.in[0].c.valid, _T_2735) @[CoreplexNetwork.scala 33:15] + when _T_2736 : @[CoreplexNetwork.scala 33:15] + node _T_2737 = eq(io.in[0].c.bits.opcode, _T_2725) @[CoreplexNetwork.scala 33:15] + node _T_2738 = or(_T_2737, reset) @[CoreplexNetwork.scala 33:15] + node _T_2740 = eq(_T_2738, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2740 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2741 = eq(io.in[0].c.bits.param, _T_2727) @[CoreplexNetwork.scala 33:15] + node _T_2742 = or(_T_2741, reset) @[CoreplexNetwork.scala 33:15] + node _T_2744 = eq(_T_2742, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2744 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2745 = eq(io.in[0].c.bits.size, _T_2729) @[CoreplexNetwork.scala 33:15] + node _T_2746 = or(_T_2745, reset) @[CoreplexNetwork.scala 33:15] + node _T_2748 = eq(_T_2746, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2748 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2749 = eq(io.in[0].c.bits.source, _T_2731) @[CoreplexNetwork.scala 33:15] + node _T_2750 = or(_T_2749, reset) @[CoreplexNetwork.scala 33:15] + node _T_2752 = eq(_T_2750, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2752 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2753 = eq(io.in[0].c.bits.address, _T_2733) @[CoreplexNetwork.scala 33:15] + node _T_2754 = or(_T_2753, reset) @[CoreplexNetwork.scala 33:15] + node _T_2756 = eq(_T_2754, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2756 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2757 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2758 = and(_T_2757, _T_2714) @[CoreplexNetwork.scala 33:15] + when _T_2758 : @[CoreplexNetwork.scala 33:15] + _T_2725 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 33:15] + _T_2727 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 33:15] + _T_2729 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 33:15] + _T_2731 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 33:15] + _T_2733 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2759 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2761 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2762 = dshl(_T_2761, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2763 = bits(_T_2762, 7, 0) @[package.scala 19:76] + node _T_2764 = not(_T_2763) @[package.scala 19:40] + node _T_2765 = shr(_T_2764, 3) @[Edges.scala 198:59] + node _T_2766 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2768 = mux(_T_2766, _T_2765, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2770 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2772 = sub(_T_2770, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2773 = asUInt(_T_2772) @[Edges.scala 208:28] + node _T_2774 = tail(_T_2773, 1) @[Edges.scala 208:28] + node _T_2776 = eq(_T_2770, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2778 = eq(_T_2770, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2780 = eq(_T_2768, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2781 = or(_T_2778, _T_2780) @[Edges.scala 210:37] + node _T_2782 = and(_T_2781, _T_2759) @[Edges.scala 211:22] + node _T_2783 = not(_T_2774) @[Edges.scala 212:27] + node _T_2784 = and(_T_2768, _T_2783) @[Edges.scala 212:25] + when _T_2759 : @[Edges.scala 213:17] + node _T_2785 = mux(_T_2776, _T_2768, _T_2774) @[Edges.scala 214:21] + _T_2770 <= _T_2785 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2787 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2789 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2791 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2793 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2795 : UInt, clock @[CoreplexNetwork.scala 33:15] + reg _T_2797 : UInt, clock @[CoreplexNetwork.scala 33:15] + node _T_2799 = eq(_T_2776, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2800 = and(io.in[0].d.valid, _T_2799) @[CoreplexNetwork.scala 33:15] + when _T_2800 : @[CoreplexNetwork.scala 33:15] + node _T_2801 = eq(io.in[0].d.bits.opcode, _T_2787) @[CoreplexNetwork.scala 33:15] + node _T_2802 = or(_T_2801, reset) @[CoreplexNetwork.scala 33:15] + node _T_2804 = eq(_T_2802, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2804 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2805 = eq(io.in[0].d.bits.param, _T_2789) @[CoreplexNetwork.scala 33:15] + node _T_2806 = or(_T_2805, reset) @[CoreplexNetwork.scala 33:15] + node _T_2808 = eq(_T_2806, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2808 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2809 = eq(io.in[0].d.bits.size, _T_2791) @[CoreplexNetwork.scala 33:15] + node _T_2810 = or(_T_2809, reset) @[CoreplexNetwork.scala 33:15] + node _T_2812 = eq(_T_2810, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2812 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2813 = eq(io.in[0].d.bits.source, _T_2793) @[CoreplexNetwork.scala 33:15] + node _T_2814 = or(_T_2813, reset) @[CoreplexNetwork.scala 33:15] + node _T_2816 = eq(_T_2814, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2816 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2817 = eq(io.in[0].d.bits.sink, _T_2795) @[CoreplexNetwork.scala 33:15] + node _T_2818 = or(_T_2817, reset) @[CoreplexNetwork.scala 33:15] + node _T_2820 = eq(_T_2818, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2820 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2821 = eq(io.in[0].d.bits.addr_lo, _T_2797) @[CoreplexNetwork.scala 33:15] + node _T_2822 = or(_T_2821, reset) @[CoreplexNetwork.scala 33:15] + node _T_2824 = eq(_T_2822, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2824 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2825 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2826 = and(_T_2825, _T_2776) @[CoreplexNetwork.scala 33:15] + when _T_2826 : @[CoreplexNetwork.scala 33:15] + _T_2787 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 33:15] + _T_2789 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 33:15] + _T_2791 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 33:15] + _T_2793 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 33:15] + _T_2795 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 33:15] + _T_2797 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + reg _T_2828 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_2829 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2831 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2832 = dshl(_T_2831, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2833 = bits(_T_2832, 7, 0) @[package.scala 19:76] + node _T_2834 = not(_T_2833) @[package.scala 19:40] + node _T_2835 = shr(_T_2834, 3) @[Edges.scala 198:59] + node _T_2836 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2838 = eq(_T_2836, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2840 = mux(_T_2838, _T_2835, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2842 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2844 = sub(_T_2842, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2845 = asUInt(_T_2844) @[Edges.scala 208:28] + node _T_2846 = tail(_T_2845, 1) @[Edges.scala 208:28] + node _T_2848 = eq(_T_2842, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2850 = eq(_T_2842, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2852 = eq(_T_2840, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2853 = or(_T_2850, _T_2852) @[Edges.scala 210:37] + node _T_2854 = and(_T_2853, _T_2829) @[Edges.scala 211:22] + node _T_2855 = not(_T_2846) @[Edges.scala 212:27] + node _T_2856 = and(_T_2840, _T_2855) @[Edges.scala 212:25] + when _T_2829 : @[Edges.scala 213:17] + node _T_2857 = mux(_T_2848, _T_2840, _T_2846) @[Edges.scala 214:21] + _T_2842 <= _T_2857 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2858 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2860 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2861 = dshl(_T_2860, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2862 = bits(_T_2861, 7, 0) @[package.scala 19:76] + node _T_2863 = not(_T_2862) @[package.scala 19:40] + node _T_2864 = shr(_T_2863, 3) @[Edges.scala 198:59] + node _T_2865 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2867 = mux(_T_2865, _T_2864, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2869 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2871 = sub(_T_2869, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2872 = asUInt(_T_2871) @[Edges.scala 208:28] + node _T_2873 = tail(_T_2872, 1) @[Edges.scala 208:28] + node _T_2875 = eq(_T_2869, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2877 = eq(_T_2869, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2879 = eq(_T_2867, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2880 = or(_T_2877, _T_2879) @[Edges.scala 210:37] + node _T_2881 = and(_T_2880, _T_2858) @[Edges.scala 211:22] + node _T_2882 = not(_T_2873) @[Edges.scala 212:27] + node _T_2883 = and(_T_2867, _T_2882) @[Edges.scala 212:25] + when _T_2858 : @[Edges.scala 213:17] + node _T_2884 = mux(_T_2875, _T_2867, _T_2873) @[Edges.scala 214:21] + _T_2869 <= _T_2884 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2886 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + node _T_2887 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 33:15] + node _T_2888 = or(_T_2886, _T_2887) @[CoreplexNetwork.scala 33:15] + node _T_2890 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2891 = or(_T_2888, _T_2890) @[CoreplexNetwork.scala 33:15] + node _T_2893 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2894 = or(_T_2891, _T_2893) @[CoreplexNetwork.scala 33:15] + node _T_2895 = or(_T_2894, reset) @[CoreplexNetwork.scala 33:15] + node _T_2897 = eq(_T_2895, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2897 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + wire _T_2899 : UInt<4> + _T_2899 is invalid + _T_2899 <= UInt<4>("h00") + node _T_2900 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2900 : @[CoreplexNetwork.scala 33:15] + when _T_2853 : @[CoreplexNetwork.scala 33:15] + node _T_2902 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2899 <= _T_2902 @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2903 = dshr(_T_2828, io.in[0].a.bits.source) @[CoreplexNetwork.scala 33:15] + node _T_2904 = bits(_T_2903, 0, 0) @[CoreplexNetwork.scala 33:15] + node _T_2906 = eq(_T_2904, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + node _T_2907 = or(_T_2906, reset) @[CoreplexNetwork.scala 33:15] + node _T_2909 = eq(_T_2907, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2909 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + wire _T_2911 : UInt<4> + _T_2911 is invalid + _T_2911 <= UInt<4>("h00") + node _T_2912 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2914 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 33:15] + node _T_2915 = and(_T_2912, _T_2914) @[CoreplexNetwork.scala 33:15] + when _T_2915 : @[CoreplexNetwork.scala 33:15] + when _T_2880 : @[CoreplexNetwork.scala 33:15] + node _T_2917 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2911 <= _T_2917 @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2918 = or(_T_2899, _T_2828) @[CoreplexNetwork.scala 33:15] + node _T_2919 = dshr(_T_2918, io.in[0].d.bits.source) @[CoreplexNetwork.scala 33:15] + node _T_2920 = bits(_T_2919, 0, 0) @[CoreplexNetwork.scala 33:15] + node _T_2921 = or(_T_2920, reset) @[CoreplexNetwork.scala 33:15] + node _T_2923 = eq(_T_2921, UInt<1>("h00")) @[CoreplexNetwork.scala 33:15] + when _T_2923 : @[CoreplexNetwork.scala 33:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:33:15)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 33:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + skip @[CoreplexNetwork.scala 33:15] + node _T_2924 = or(_T_2828, _T_2899) @[CoreplexNetwork.scala 33:15] + node _T_2925 = not(_T_2911) @[CoreplexNetwork.scala 33:15] + node _T_2926 = and(_T_2924, _T_2925) @[CoreplexNetwork.scala 33:15] + _T_2828 <= _T_2926 @[CoreplexNetwork.scala 33:15] + + module TLWidthWidget_cbus : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}} + + io is invalid + io is invalid + io.out.0.a <- io.in.0.a @[WidthWidget.scala 131:13] + io.in.0.d <- io.out.0.d @[WidthWidget.scala 131:13] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_15 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 38:36] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 38:36] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_608 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + when _T_708 : @[CoreplexNetwork.scala 38:36] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_729 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_730 = cvt(_T_729) @[Parameters.scala 117:49] + node _T_732 = and(_T_730, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_733 = asSInt(_T_732) @[Parameters.scala 117:52] + node _T_735 = eq(_T_733, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_736 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_737 = or(_T_736, _T_735) @[Parameters.scala 133:42] + node _T_738 = and(_T_711, _T_737) @[Parameters.scala 132:56] + node _T_740 = or(UInt<1>("h00"), _T_738) @[Parameters.scala 134:30] + node _T_741 = or(_T_740, reset) @[CoreplexNetwork.scala 38:36] + node _T_743 = eq(_T_741, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_743 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_744 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_746 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_748 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_749 = or(_T_748, reset) @[CoreplexNetwork.scala 38:36] + node _T_751 = eq(_T_749, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_751 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_752 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_754 = eq(_T_752, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_754 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_756 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_757 = or(_T_756, reset) @[CoreplexNetwork.scala 38:36] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_759 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_760 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 38:36] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_763 = or(_T_762, reset) @[CoreplexNetwork.scala 38:36] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_765 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_767 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 38:36] + when _T_767 : @[CoreplexNetwork.scala 38:36] + node _T_770 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_772 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_773 = and(_T_770, _T_772) @[Parameters.scala 63:37] + node _T_774 = or(UInt<1>("h00"), _T_773) @[Parameters.scala 132:31] + node _T_776 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_777 = cvt(_T_776) @[Parameters.scala 117:49] + node _T_779 = and(_T_777, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_780 = asSInt(_T_779) @[Parameters.scala 117:52] + node _T_782 = eq(_T_780, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_784 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_785 = cvt(_T_784) @[Parameters.scala 117:49] + node _T_787 = and(_T_785, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_788 = asSInt(_T_787) @[Parameters.scala 117:52] + node _T_790 = eq(_T_788, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_792 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = or(_T_782, _T_790) @[Parameters.scala 133:42] + node _T_800 = or(_T_799, _T_798) @[Parameters.scala 133:42] + node _T_801 = and(_T_774, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[CoreplexNetwork.scala 38:36] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_806 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_807 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_809 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_810 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_812 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_815 = or(_T_814, reset) @[CoreplexNetwork.scala 38:36] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_817 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_818 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 38:36] + node _T_819 = or(_T_818, reset) @[CoreplexNetwork.scala 38:36] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_821 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_823 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_823 : @[CoreplexNetwork.scala 38:36] + node _T_826 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_828 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_829 = and(_T_826, _T_828) @[Parameters.scala 63:37] + node _T_830 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 132:31] + node _T_832 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_833 = cvt(_T_832) @[Parameters.scala 117:49] + node _T_835 = and(_T_833, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_836 = asSInt(_T_835) @[Parameters.scala 117:52] + node _T_838 = eq(_T_836, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_840 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_841 = cvt(_T_840) @[Parameters.scala 117:49] + node _T_843 = and(_T_841, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_844 = asSInt(_T_843) @[Parameters.scala 117:52] + node _T_846 = eq(_T_844, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_848 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_849 = cvt(_T_848) @[Parameters.scala 117:49] + node _T_851 = and(_T_849, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_852 = asSInt(_T_851) @[Parameters.scala 117:52] + node _T_854 = eq(_T_852, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_855 = or(_T_838, _T_846) @[Parameters.scala 133:42] + node _T_856 = or(_T_855, _T_854) @[Parameters.scala 133:42] + node _T_857 = and(_T_830, _T_856) @[Parameters.scala 132:56] + node _T_859 = or(UInt<1>("h00"), _T_857) @[Parameters.scala 134:30] + node _T_860 = or(_T_859, reset) @[CoreplexNetwork.scala 38:36] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_862 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_863 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_865 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_866 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_868 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_870 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_871 = or(_T_870, reset) @[CoreplexNetwork.scala 38:36] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_873 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_874 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 38:36] + node _T_875 = or(_T_874, reset) @[CoreplexNetwork.scala 38:36] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_877 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_879 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 38:36] + when _T_879 : @[CoreplexNetwork.scala 38:36] + node _T_882 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_884 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_885 = and(_T_882, _T_884) @[Parameters.scala 63:37] + node _T_886 = or(UInt<1>("h00"), _T_885) @[Parameters.scala 132:31] + node _T_888 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_889 = cvt(_T_888) @[Parameters.scala 117:49] + node _T_891 = and(_T_889, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_892 = asSInt(_T_891) @[Parameters.scala 117:52] + node _T_894 = eq(_T_892, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_897 = cvt(_T_896) @[Parameters.scala 117:49] + node _T_899 = and(_T_897, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_900 = asSInt(_T_899) @[Parameters.scala 117:52] + node _T_902 = eq(_T_900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_905 = cvt(_T_904) @[Parameters.scala 117:49] + node _T_907 = and(_T_905, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_908 = asSInt(_T_907) @[Parameters.scala 117:52] + node _T_910 = eq(_T_908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_911 = or(_T_894, _T_902) @[Parameters.scala 133:42] + node _T_912 = or(_T_911, _T_910) @[Parameters.scala 133:42] + node _T_913 = and(_T_886, _T_912) @[Parameters.scala 132:56] + node _T_915 = or(UInt<1>("h00"), _T_913) @[Parameters.scala 134:30] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 38:36] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_918 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_919 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_921 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_922 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_924 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_926 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_927 = or(_T_926, reset) @[CoreplexNetwork.scala 38:36] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_929 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_930 = not(_T_706) @[CoreplexNetwork.scala 38:36] + node _T_931 = and(io.in[0].a.bits.mask, _T_930) @[CoreplexNetwork.scala 38:36] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_934 = or(_T_933, reset) @[CoreplexNetwork.scala 38:36] + node _T_936 = eq(_T_934, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_936 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_938 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 38:36] + when _T_938 : @[CoreplexNetwork.scala 38:36] + node _T_941 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_943 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_944 = and(_T_941, _T_943) @[Parameters.scala 63:37] + node _T_945 = or(UInt<1>("h00"), _T_944) @[Parameters.scala 132:31] + node _T_947 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_948 = cvt(_T_947) @[Parameters.scala 117:49] + node _T_950 = and(_T_948, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_951 = asSInt(_T_950) @[Parameters.scala 117:52] + node _T_953 = eq(_T_951, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_955 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_956 = cvt(_T_955) @[Parameters.scala 117:49] + node _T_958 = and(_T_956, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_959 = asSInt(_T_958) @[Parameters.scala 117:52] + node _T_961 = eq(_T_959, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_963 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_964 = cvt(_T_963) @[Parameters.scala 117:49] + node _T_966 = and(_T_964, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_967 = asSInt(_T_966) @[Parameters.scala 117:52] + node _T_969 = eq(_T_967, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_970 = or(_T_953, _T_961) @[Parameters.scala 133:42] + node _T_971 = or(_T_970, _T_969) @[Parameters.scala 133:42] + node _T_972 = and(_T_945, _T_971) @[Parameters.scala 132:56] + node _T_974 = or(UInt<1>("h00"), _T_972) @[Parameters.scala 134:30] + node _T_975 = or(_T_974, reset) @[CoreplexNetwork.scala 38:36] + node _T_977 = eq(_T_975, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_977 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_978 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_980 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_981 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_983 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_985 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_986 = or(_T_985, reset) @[CoreplexNetwork.scala 38:36] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_988 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_989 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 38:36] + node _T_990 = or(_T_989, reset) @[CoreplexNetwork.scala 38:36] + node _T_992 = eq(_T_990, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_992 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_994 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + when _T_994 : @[CoreplexNetwork.scala 38:36] + node _T_997 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_999 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1000 = and(_T_997, _T_999) @[Parameters.scala 63:37] + node _T_1001 = or(UInt<1>("h00"), _T_1000) @[Parameters.scala 132:31] + node _T_1003 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1012 = cvt(_T_1011) @[Parameters.scala 117:49] + node _T_1014 = and(_T_1012, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1015 = asSInt(_T_1014) @[Parameters.scala 117:52] + node _T_1017 = eq(_T_1015, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1019 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1020 = cvt(_T_1019) @[Parameters.scala 117:49] + node _T_1022 = and(_T_1020, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1023 = asSInt(_T_1022) @[Parameters.scala 117:52] + node _T_1025 = eq(_T_1023, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1026 = or(_T_1009, _T_1017) @[Parameters.scala 133:42] + node _T_1027 = or(_T_1026, _T_1025) @[Parameters.scala 133:42] + node _T_1028 = and(_T_1001, _T_1027) @[Parameters.scala 132:56] + node _T_1030 = or(UInt<1>("h00"), _T_1028) @[Parameters.scala 134:30] + node _T_1031 = or(_T_1030, reset) @[CoreplexNetwork.scala 38:36] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1033 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1034 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1036 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1037 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_1039 = eq(_T_1037, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1039 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1041 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1042 = or(_T_1041, reset) @[CoreplexNetwork.scala 38:36] + node _T_1044 = eq(_T_1042, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1044 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1045 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 38:36] + node _T_1046 = or(_T_1045, reset) @[CoreplexNetwork.scala 38:36] + node _T_1048 = eq(_T_1046, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1048 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1050 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 38:36] + when _T_1050 : @[CoreplexNetwork.scala 38:36] + node _T_1053 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1055 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1063 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1064 = cvt(_T_1063) @[Parameters.scala 117:49] + node _T_1066 = and(_T_1064, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1067 = asSInt(_T_1066) @[Parameters.scala 117:52] + node _T_1069 = eq(_T_1067, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1071 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1072 = cvt(_T_1071) @[Parameters.scala 117:49] + node _T_1074 = and(_T_1072, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1075 = asSInt(_T_1074) @[Parameters.scala 117:52] + node _T_1077 = eq(_T_1075, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1078 = or(_T_1061, _T_1069) @[Parameters.scala 133:42] + node _T_1079 = or(_T_1078, _T_1077) @[Parameters.scala 133:42] + node _T_1080 = and(_T_1053, _T_1079) @[Parameters.scala 132:56] + node _T_1082 = or(UInt<1>("h00"), _T_1080) @[Parameters.scala 134:30] + node _T_1083 = or(_T_1082, reset) @[CoreplexNetwork.scala 38:36] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1085 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1086 = or(_T_630, reset) @[CoreplexNetwork.scala 38:36] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1088 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1089 = or(_T_638, reset) @[CoreplexNetwork.scala 38:36] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1091 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1092 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 38:36] + node _T_1093 = or(_T_1092, reset) @[CoreplexNetwork.scala 38:36] + node _T_1095 = eq(_T_1093, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1095 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + when io.in[0].b.valid : @[CoreplexNetwork.scala 38:36] + node _T_1097 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1098 = or(_T_1097, reset) @[CoreplexNetwork.scala 38:36] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1100 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1102 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1103 = cvt(_T_1102) @[Parameters.scala 117:49] + node _T_1105 = and(_T_1103, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1106 = asSInt(_T_1105) @[Parameters.scala 117:52] + node _T_1108 = eq(_T_1106, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1110 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1111 = cvt(_T_1110) @[Parameters.scala 117:49] + node _T_1113 = and(_T_1111, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1114 = asSInt(_T_1113) @[Parameters.scala 117:52] + node _T_1116 = eq(_T_1114, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1118 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1119 = cvt(_T_1118) @[Parameters.scala 117:49] + node _T_1121 = and(_T_1119, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1122 = asSInt(_T_1121) @[Parameters.scala 117:52] + node _T_1124 = eq(_T_1122, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1127 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1127 is invalid @[Parameters.scala 110:36] + _T_1127[0] <= _T_1108 @[Parameters.scala 110:36] + _T_1127[1] <= _T_1116 @[Parameters.scala 110:36] + _T_1127[2] <= _T_1124 @[Parameters.scala 110:36] + node _T_1133 = or(_T_1127[0], _T_1127[1]) @[Parameters.scala 119:64] + node _T_1134 = or(_T_1133, _T_1127[2]) @[Parameters.scala 119:64] + node _T_1136 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1137 = dshl(_T_1136, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1138 = bits(_T_1137, 5, 0) @[package.scala 19:76] + node _T_1139 = not(_T_1138) @[package.scala 19:40] + node _T_1140 = and(io.in[0].b.bits.address, _T_1139) @[Edges.scala 17:16] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1144 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1145 = dshl(UInt<1>("h01"), _T_1144) @[OneHot.scala 49:12] + node _T_1146 = bits(_T_1145, 2, 0) @[OneHot.scala 49:37] + node _T_1148 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1150 = bits(_T_1146, 2, 2) @[package.scala 44:26] + node _T_1151 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[package.scala 46:20] + node _T_1154 = and(UInt<1>("h01"), _T_1153) @[package.scala 49:27] + node _T_1155 = and(_T_1150, _T_1154) @[package.scala 50:38] + node _T_1156 = or(_T_1148, _T_1155) @[package.scala 50:29] + node _T_1157 = and(UInt<1>("h01"), _T_1151) @[package.scala 49:27] + node _T_1158 = and(_T_1150, _T_1157) @[package.scala 50:38] + node _T_1159 = or(_T_1148, _T_1158) @[package.scala 50:29] + node _T_1160 = bits(_T_1146, 1, 1) @[package.scala 44:26] + node _T_1161 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[package.scala 46:20] + node _T_1164 = and(_T_1154, _T_1163) @[package.scala 49:27] + node _T_1165 = and(_T_1160, _T_1164) @[package.scala 50:38] + node _T_1166 = or(_T_1156, _T_1165) @[package.scala 50:29] + node _T_1167 = and(_T_1154, _T_1161) @[package.scala 49:27] + node _T_1168 = and(_T_1160, _T_1167) @[package.scala 50:38] + node _T_1169 = or(_T_1156, _T_1168) @[package.scala 50:29] + node _T_1170 = and(_T_1157, _T_1163) @[package.scala 49:27] + node _T_1171 = and(_T_1160, _T_1170) @[package.scala 50:38] + node _T_1172 = or(_T_1159, _T_1171) @[package.scala 50:29] + node _T_1173 = and(_T_1157, _T_1161) @[package.scala 49:27] + node _T_1174 = and(_T_1160, _T_1173) @[package.scala 50:38] + node _T_1175 = or(_T_1159, _T_1174) @[package.scala 50:29] + node _T_1176 = bits(_T_1146, 0, 0) @[package.scala 44:26] + node _T_1177 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[package.scala 46:20] + node _T_1180 = and(_T_1164, _T_1179) @[package.scala 49:27] + node _T_1181 = and(_T_1176, _T_1180) @[package.scala 50:38] + node _T_1182 = or(_T_1166, _T_1181) @[package.scala 50:29] + node _T_1183 = and(_T_1164, _T_1177) @[package.scala 49:27] + node _T_1184 = and(_T_1176, _T_1183) @[package.scala 50:38] + node _T_1185 = or(_T_1166, _T_1184) @[package.scala 50:29] + node _T_1186 = and(_T_1167, _T_1179) @[package.scala 49:27] + node _T_1187 = and(_T_1176, _T_1186) @[package.scala 50:38] + node _T_1188 = or(_T_1169, _T_1187) @[package.scala 50:29] + node _T_1189 = and(_T_1167, _T_1177) @[package.scala 49:27] + node _T_1190 = and(_T_1176, _T_1189) @[package.scala 50:38] + node _T_1191 = or(_T_1169, _T_1190) @[package.scala 50:29] + node _T_1192 = and(_T_1170, _T_1179) @[package.scala 49:27] + node _T_1193 = and(_T_1176, _T_1192) @[package.scala 50:38] + node _T_1194 = or(_T_1172, _T_1193) @[package.scala 50:29] + node _T_1195 = and(_T_1170, _T_1177) @[package.scala 49:27] + node _T_1196 = and(_T_1176, _T_1195) @[package.scala 50:38] + node _T_1197 = or(_T_1172, _T_1196) @[package.scala 50:29] + node _T_1198 = and(_T_1173, _T_1179) @[package.scala 49:27] + node _T_1199 = and(_T_1176, _T_1198) @[package.scala 50:38] + node _T_1200 = or(_T_1175, _T_1199) @[package.scala 50:29] + node _T_1201 = and(_T_1173, _T_1177) @[package.scala 49:27] + node _T_1202 = and(_T_1176, _T_1201) @[package.scala 50:38] + node _T_1203 = or(_T_1175, _T_1202) @[package.scala 50:29] + node _T_1204 = cat(_T_1185, _T_1182) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1191, _T_1188) @[Cat.scala 30:58] + node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 30:58] + node _T_1207 = cat(_T_1197, _T_1194) @[Cat.scala 30:58] + node _T_1208 = cat(_T_1203, _T_1200) @[Cat.scala 30:58] + node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 30:58] + node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 30:58] + node _T_1212 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + when _T_1212 : @[CoreplexNetwork.scala 38:36] + node _T_1214 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1215 = not(_T_1214) @[Parameters.scala 37:9] + node _T_1217 = or(_T_1215, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1218 = not(_T_1217) @[Parameters.scala 37:7] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1222 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1224 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1227 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1227 is invalid @[Parameters.scala 228:27] + _T_1227[0] <= _T_1220 @[Parameters.scala 228:27] + _T_1227[1] <= _T_1222 @[Parameters.scala 228:27] + _T_1227[2] <= _T_1224 @[Parameters.scala 228:27] + node _T_1235 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1237 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1238 = and(_T_1235, _T_1237) @[Parameters.scala 63:37] + node _T_1241 = mux(_T_1227[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1243 = mux(_T_1227[1], _T_1238, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1245 = mux(_T_1227[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1247 = or(_T_1241, _T_1243) @[Mux.scala 19:72] + node _T_1248 = or(_T_1247, _T_1245) @[Mux.scala 19:72] + wire _T_1250 : UInt<1> @[Mux.scala 19:72] + _T_1250 is invalid @[Mux.scala 19:72] + _T_1250 <= _T_1248 @[Mux.scala 19:72] + node _T_1251 = or(_T_1250, reset) @[CoreplexNetwork.scala 38:36] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1253 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1254 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1256 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1258 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1259 = or(_T_1258, reset) @[CoreplexNetwork.scala 38:36] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1261 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1262 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1264 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1266 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1267 = or(_T_1266, reset) @[CoreplexNetwork.scala 38:36] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1269 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1270 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 38:36] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1273 = or(_T_1272, reset) @[CoreplexNetwork.scala 38:36] + node _T_1275 = eq(_T_1273, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1275 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1277 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 38:36] + when _T_1277 : @[CoreplexNetwork.scala 38:36] + node _T_1279 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1281 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1282 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1284 = eq(_T_1282, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1284 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1285 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1287 = eq(_T_1285, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1287 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1289 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1290 = or(_T_1289, reset) @[CoreplexNetwork.scala 38:36] + node _T_1292 = eq(_T_1290, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1292 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1293 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1294 = or(_T_1293, reset) @[CoreplexNetwork.scala 38:36] + node _T_1296 = eq(_T_1294, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1296 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1298 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1298 : @[CoreplexNetwork.scala 38:36] + node _T_1300 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1302 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1303 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1305 = eq(_T_1303, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1305 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1306 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1308 = eq(_T_1306, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1308 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1310 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1311 = or(_T_1310, reset) @[CoreplexNetwork.scala 38:36] + node _T_1313 = eq(_T_1311, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1313 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1314 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1315 = or(_T_1314, reset) @[CoreplexNetwork.scala 38:36] + node _T_1317 = eq(_T_1315, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1317 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1319 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 38:36] + when _T_1319 : @[CoreplexNetwork.scala 38:36] + node _T_1321 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1323 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1324 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1326 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1327 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1329 = eq(_T_1327, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1329 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1331 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1332 = or(_T_1331, reset) @[CoreplexNetwork.scala 38:36] + node _T_1334 = eq(_T_1332, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1334 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1335 = not(_T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1336 = and(io.in[0].b.bits.mask, _T_1335) @[CoreplexNetwork.scala 38:36] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1339 = or(_T_1338, reset) @[CoreplexNetwork.scala 38:36] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1341 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1343 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 38:36] + when _T_1343 : @[CoreplexNetwork.scala 38:36] + node _T_1345 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1347 = eq(_T_1345, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1347 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1348 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1350 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1351 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1353 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1355 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1356 = or(_T_1355, reset) @[CoreplexNetwork.scala 38:36] + node _T_1358 = eq(_T_1356, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1358 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1359 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1360 = or(_T_1359, reset) @[CoreplexNetwork.scala 38:36] + node _T_1362 = eq(_T_1360, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1362 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1364 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + when _T_1364 : @[CoreplexNetwork.scala 38:36] + node _T_1366 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1368 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1369 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1371 = eq(_T_1369, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1371 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1372 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1374 = eq(_T_1372, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1374 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1376 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1377 = or(_T_1376, reset) @[CoreplexNetwork.scala 38:36] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1379 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1380 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1381 = or(_T_1380, reset) @[CoreplexNetwork.scala 38:36] + node _T_1383 = eq(_T_1381, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1383 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1385 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 38:36] + when _T_1385 : @[CoreplexNetwork.scala 38:36] + node _T_1387 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 38:36] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1389 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1390 = or(_T_1134, reset) @[CoreplexNetwork.scala 38:36] + node _T_1392 = eq(_T_1390, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1392 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1393 = or(_T_1142, reset) @[CoreplexNetwork.scala 38:36] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1395 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1396 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 38:36] + node _T_1397 = or(_T_1396, reset) @[CoreplexNetwork.scala 38:36] + node _T_1399 = eq(_T_1397, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1399 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + when io.in[0].c.valid : @[CoreplexNetwork.scala 38:36] + node _T_1401 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1402 = or(_T_1401, reset) @[CoreplexNetwork.scala 38:36] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1404 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1406 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1407 = not(_T_1406) @[Parameters.scala 37:9] + node _T_1409 = or(_T_1407, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1410 = not(_T_1409) @[Parameters.scala 37:7] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1414 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1416 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1419 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1419 is invalid @[Parameters.scala 228:27] + _T_1419[0] <= _T_1412 @[Parameters.scala 228:27] + _T_1419[1] <= _T_1414 @[Parameters.scala 228:27] + _T_1419[2] <= _T_1416 @[Parameters.scala 228:27] + node _T_1425 = or(_T_1419[0], _T_1419[1]) @[Parameters.scala 229:46] + node _T_1426 = or(_T_1425, _T_1419[2]) @[Parameters.scala 229:46] + node _T_1428 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1429 = dshl(_T_1428, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1430 = bits(_T_1429, 5, 0) @[package.scala 19:76] + node _T_1431 = not(_T_1430) @[package.scala 19:40] + node _T_1432 = and(io.in[0].c.bits.address, _T_1431) @[Edges.scala 17:16] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1436 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1437 = cvt(_T_1436) @[Parameters.scala 117:49] + node _T_1439 = and(_T_1437, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1440 = asSInt(_T_1439) @[Parameters.scala 117:52] + node _T_1442 = eq(_T_1440, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1444 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1445 = cvt(_T_1444) @[Parameters.scala 117:49] + node _T_1447 = and(_T_1445, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1448 = asSInt(_T_1447) @[Parameters.scala 117:52] + node _T_1450 = eq(_T_1448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1452 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1453 = cvt(_T_1452) @[Parameters.scala 117:49] + node _T_1455 = and(_T_1453, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1456 = asSInt(_T_1455) @[Parameters.scala 117:52] + node _T_1458 = eq(_T_1456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1461 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1461 is invalid @[Parameters.scala 110:36] + _T_1461[0] <= _T_1442 @[Parameters.scala 110:36] + _T_1461[1] <= _T_1450 @[Parameters.scala 110:36] + _T_1461[2] <= _T_1458 @[Parameters.scala 110:36] + node _T_1467 = or(_T_1461[0], _T_1461[1]) @[Parameters.scala 119:64] + node _T_1468 = or(_T_1467, _T_1461[2]) @[Parameters.scala 119:64] + node _T_1470 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 38:36] + when _T_1470 : @[CoreplexNetwork.scala 38:36] + node _T_1471 = or(_T_1468, reset) @[CoreplexNetwork.scala 38:36] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1473 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1474 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1476 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1478 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 38:36] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1481 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1482 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1484 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1486 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1487 = or(_T_1486, reset) @[CoreplexNetwork.scala 38:36] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1489 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1491 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1492 = or(_T_1491, reset) @[CoreplexNetwork.scala 38:36] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1494 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 38:36] + when _T_1496 : @[CoreplexNetwork.scala 38:36] + node _T_1497 = or(_T_1468, reset) @[CoreplexNetwork.scala 38:36] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1499 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1500 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1502 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1504 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1505 = or(_T_1504, reset) @[CoreplexNetwork.scala 38:36] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1507 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1508 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1510 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1512 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1513 = or(_T_1512, reset) @[CoreplexNetwork.scala 38:36] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1515 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1517 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1518 = or(_T_1517, reset) @[CoreplexNetwork.scala 38:36] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1520 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1522 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + when _T_1522 : @[CoreplexNetwork.scala 38:36] + node _T_1525 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1527 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1528 = cvt(_T_1527) @[Parameters.scala 117:49] + node _T_1530 = and(_T_1528, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1531 = asSInt(_T_1530) @[Parameters.scala 117:52] + node _T_1533 = eq(_T_1531, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1535 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1536 = cvt(_T_1535) @[Parameters.scala 117:49] + node _T_1538 = and(_T_1536, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1539 = asSInt(_T_1538) @[Parameters.scala 117:52] + node _T_1541 = eq(_T_1539, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1543 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1544 = cvt(_T_1543) @[Parameters.scala 117:49] + node _T_1546 = and(_T_1544, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1547 = asSInt(_T_1546) @[Parameters.scala 117:52] + node _T_1549 = eq(_T_1547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1550 = or(_T_1533, _T_1541) @[Parameters.scala 133:42] + node _T_1551 = or(_T_1550, _T_1549) @[Parameters.scala 133:42] + node _T_1552 = and(_T_1525, _T_1551) @[Parameters.scala 132:56] + node _T_1554 = or(UInt<1>("h00"), _T_1552) @[Parameters.scala 134:30] + node _T_1555 = or(_T_1554, reset) @[CoreplexNetwork.scala 38:36] + node _T_1557 = eq(_T_1555, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1557 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1558 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1560 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1562 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1563 = or(_T_1562, reset) @[CoreplexNetwork.scala 38:36] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1565 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1566 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1568 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1570 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1571 = or(_T_1570, reset) @[CoreplexNetwork.scala 38:36] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1573 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1575 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1576 = or(_T_1575, reset) @[CoreplexNetwork.scala 38:36] + node _T_1578 = eq(_T_1576, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1578 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1580 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 38:36] + when _T_1580 : @[CoreplexNetwork.scala 38:36] + node _T_1583 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1585 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1586 = cvt(_T_1585) @[Parameters.scala 117:49] + node _T_1588 = and(_T_1586, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1589 = asSInt(_T_1588) @[Parameters.scala 117:52] + node _T_1591 = eq(_T_1589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1593 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1594 = cvt(_T_1593) @[Parameters.scala 117:49] + node _T_1596 = and(_T_1594, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1597 = asSInt(_T_1596) @[Parameters.scala 117:52] + node _T_1599 = eq(_T_1597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1601 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1602 = cvt(_T_1601) @[Parameters.scala 117:49] + node _T_1604 = and(_T_1602, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1605 = asSInt(_T_1604) @[Parameters.scala 117:52] + node _T_1607 = eq(_T_1605, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1608 = or(_T_1591, _T_1599) @[Parameters.scala 133:42] + node _T_1609 = or(_T_1608, _T_1607) @[Parameters.scala 133:42] + node _T_1610 = and(_T_1583, _T_1609) @[Parameters.scala 132:56] + node _T_1612 = or(UInt<1>("h00"), _T_1610) @[Parameters.scala 134:30] + node _T_1613 = or(_T_1612, reset) @[CoreplexNetwork.scala 38:36] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1615 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1616 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1618 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1620 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1621 = or(_T_1620, reset) @[CoreplexNetwork.scala 38:36] + node _T_1623 = eq(_T_1621, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1623 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1624 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1626 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1628 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1629 = or(_T_1628, reset) @[CoreplexNetwork.scala 38:36] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1631 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1633 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1634 = or(_T_1633, reset) @[CoreplexNetwork.scala 38:36] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1636 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1638 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1638 : @[CoreplexNetwork.scala 38:36] + node _T_1639 = or(_T_1468, reset) @[CoreplexNetwork.scala 38:36] + node _T_1641 = eq(_T_1639, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1641 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1642 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1644 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1645 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1647 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1649 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1650 = or(_T_1649, reset) @[CoreplexNetwork.scala 38:36] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1652 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1654 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 38:36] + when _T_1654 : @[CoreplexNetwork.scala 38:36] + node _T_1655 = or(_T_1468, reset) @[CoreplexNetwork.scala 38:36] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1657 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1658 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1660 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1661 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1663 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1665 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1666 = or(_T_1665, reset) @[CoreplexNetwork.scala 38:36] + node _T_1668 = eq(_T_1666, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1668 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1670 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 38:36] + when _T_1670 : @[CoreplexNetwork.scala 38:36] + node _T_1671 = or(_T_1468, reset) @[CoreplexNetwork.scala 38:36] + node _T_1673 = eq(_T_1671, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1673 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1674 = or(_T_1426, reset) @[CoreplexNetwork.scala 38:36] + node _T_1676 = eq(_T_1674, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1676 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1677 = or(_T_1434, reset) @[CoreplexNetwork.scala 38:36] + node _T_1679 = eq(_T_1677, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1679 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1681 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1682 = or(_T_1681, reset) @[CoreplexNetwork.scala 38:36] + node _T_1684 = eq(_T_1682, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1684 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1686 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1687 = or(_T_1686, reset) @[CoreplexNetwork.scala 38:36] + node _T_1689 = eq(_T_1687, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1689 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + when io.in[0].d.valid : @[CoreplexNetwork.scala 38:36] + node _T_1691 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1692 = or(_T_1691, reset) @[CoreplexNetwork.scala 38:36] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1694 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1696 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1697 = not(_T_1696) @[Parameters.scala 37:9] + node _T_1699 = or(_T_1697, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1700 = not(_T_1699) @[Parameters.scala 37:7] + node _T_1702 = eq(_T_1700, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1704 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1706 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1709 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1709 is invalid @[Parameters.scala 228:27] + _T_1709[0] <= _T_1702 @[Parameters.scala 228:27] + _T_1709[1] <= _T_1704 @[Parameters.scala 228:27] + _T_1709[2] <= _T_1706 @[Parameters.scala 228:27] + node _T_1715 = or(_T_1709[0], _T_1709[1]) @[Parameters.scala 229:46] + node _T_1716 = or(_T_1715, _T_1709[2]) @[Parameters.scala 229:46] + node _T_1718 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1719 = dshl(_T_1718, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1720 = bits(_T_1719, 5, 0) @[package.scala 19:76] + node _T_1721 = not(_T_1720) @[package.scala 19:40] + node _T_1722 = and(io.in[0].d.bits.addr_lo, _T_1721) @[Edges.scala 17:16] + node _T_1724 = eq(_T_1722, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1726 = lt(io.in[0].d.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1728 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + when _T_1728 : @[CoreplexNetwork.scala 38:36] + node _T_1729 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1731 = eq(_T_1729, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1731 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1732 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1734 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1735 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1737 = eq(_T_1735, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1737 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1739 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1740 = or(_T_1739, reset) @[CoreplexNetwork.scala 38:36] + node _T_1742 = eq(_T_1740, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1742 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1744 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1745 = or(_T_1744, reset) @[CoreplexNetwork.scala 38:36] + node _T_1747 = eq(_T_1745, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1747 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1749 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1750 = or(_T_1749, reset) @[CoreplexNetwork.scala 38:36] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1752 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1754 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 38:36] + when _T_1754 : @[CoreplexNetwork.scala 38:36] + node _T_1755 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1757 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1758 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1760 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1761 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1763 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1765 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1766 = or(_T_1765, reset) @[CoreplexNetwork.scala 38:36] + node _T_1768 = eq(_T_1766, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1768 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1770 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1771 = or(_T_1770, reset) @[CoreplexNetwork.scala 38:36] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1773 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1775 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 38:36] + when _T_1775 : @[CoreplexNetwork.scala 38:36] + node _T_1776 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1778 = eq(_T_1776, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1778 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1779 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1781 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1782 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1784 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1786 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1787 = or(_T_1786, reset) @[CoreplexNetwork.scala 38:36] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1789 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1791 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1792 = or(_T_1791, reset) @[CoreplexNetwork.scala 38:36] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1794 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1796 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1796 : @[CoreplexNetwork.scala 38:36] + node _T_1797 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1799 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1800 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1802 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1803 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1805 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1807 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1808 = or(_T_1807, reset) @[CoreplexNetwork.scala 38:36] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1810 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1812 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 38:36] + when _T_1812 : @[CoreplexNetwork.scala 38:36] + node _T_1813 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1815 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1816 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1818 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1819 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1821 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1823 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1824 = or(_T_1823, reset) @[CoreplexNetwork.scala 38:36] + node _T_1826 = eq(_T_1824, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1826 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1828 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 38:36] + when _T_1828 : @[CoreplexNetwork.scala 38:36] + node _T_1829 = or(_T_1716, reset) @[CoreplexNetwork.scala 38:36] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1831 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1832 = or(_T_1724, reset) @[CoreplexNetwork.scala 38:36] + node _T_1834 = eq(_T_1832, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1834 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1835 = or(_T_1726, reset) @[CoreplexNetwork.scala 38:36] + node _T_1837 = eq(_T_1835, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1837 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1839 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1840 = or(_T_1839, reset) @[CoreplexNetwork.scala 38:36] + node _T_1842 = eq(_T_1840, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1842 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1844 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1845 = or(_T_1844, reset) @[CoreplexNetwork.scala 38:36] + node _T_1847 = eq(_T_1845, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1847 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + when io.in[0].e.valid : @[CoreplexNetwork.scala 38:36] + node _T_1849 = lt(io.in[0].e.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 38:36] + node _T_1850 = or(_T_1849, reset) @[CoreplexNetwork.scala 38:36] + node _T_1852 = eq(_T_1850, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1852 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1853 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1855 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1856 = dshl(_T_1855, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1857 = bits(_T_1856, 5, 0) @[package.scala 19:76] + node _T_1858 = not(_T_1857) @[package.scala 19:40] + node _T_1859 = shr(_T_1858, 3) @[Edges.scala 198:59] + node _T_1860 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1862 = eq(_T_1860, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1864 = mux(_T_1862, _T_1859, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1866 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1868 = sub(_T_1866, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1869 = asUInt(_T_1868) @[Edges.scala 208:28] + node _T_1870 = tail(_T_1869, 1) @[Edges.scala 208:28] + node _T_1872 = eq(_T_1866, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1874 = eq(_T_1866, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1876 = eq(_T_1864, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1877 = or(_T_1874, _T_1876) @[Edges.scala 210:37] + node _T_1878 = and(_T_1877, _T_1853) @[Edges.scala 211:22] + node _T_1879 = not(_T_1870) @[Edges.scala 212:27] + node _T_1880 = and(_T_1864, _T_1879) @[Edges.scala 212:25] + when _T_1853 : @[Edges.scala 213:17] + node _T_1881 = mux(_T_1872, _T_1864, _T_1870) @[Edges.scala 214:21] + _T_1866 <= _T_1881 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1883 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1885 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1887 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1889 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1891 : UInt, clock @[CoreplexNetwork.scala 38:36] + node _T_1893 = eq(_T_1872, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1894 = and(io.in[0].a.valid, _T_1893) @[CoreplexNetwork.scala 38:36] + when _T_1894 : @[CoreplexNetwork.scala 38:36] + node _T_1895 = eq(io.in[0].a.bits.opcode, _T_1883) @[CoreplexNetwork.scala 38:36] + node _T_1896 = or(_T_1895, reset) @[CoreplexNetwork.scala 38:36] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1898 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1899 = eq(io.in[0].a.bits.param, _T_1885) @[CoreplexNetwork.scala 38:36] + node _T_1900 = or(_T_1899, reset) @[CoreplexNetwork.scala 38:36] + node _T_1902 = eq(_T_1900, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1902 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1903 = eq(io.in[0].a.bits.size, _T_1887) @[CoreplexNetwork.scala 38:36] + node _T_1904 = or(_T_1903, reset) @[CoreplexNetwork.scala 38:36] + node _T_1906 = eq(_T_1904, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1906 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1907 = eq(io.in[0].a.bits.source, _T_1889) @[CoreplexNetwork.scala 38:36] + node _T_1908 = or(_T_1907, reset) @[CoreplexNetwork.scala 38:36] + node _T_1910 = eq(_T_1908, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1910 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1911 = eq(io.in[0].a.bits.address, _T_1891) @[CoreplexNetwork.scala 38:36] + node _T_1912 = or(_T_1911, reset) @[CoreplexNetwork.scala 38:36] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1914 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1915 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1916 = and(_T_1915, _T_1872) @[CoreplexNetwork.scala 38:36] + when _T_1916 : @[CoreplexNetwork.scala 38:36] + _T_1883 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 38:36] + _T_1885 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 38:36] + _T_1887 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 38:36] + _T_1889 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 38:36] + _T_1891 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1917 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1919 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1920 = dshl(_T_1919, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1921 = bits(_T_1920, 5, 0) @[package.scala 19:76] + node _T_1922 = not(_T_1921) @[package.scala 19:40] + node _T_1923 = shr(_T_1922, 3) @[Edges.scala 198:59] + node _T_1924 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1926 = eq(_T_1924, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1929 = mux(UInt<1>("h00"), _T_1923, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1931 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1933 = sub(_T_1931, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1934 = asUInt(_T_1933) @[Edges.scala 208:28] + node _T_1935 = tail(_T_1934, 1) @[Edges.scala 208:28] + node _T_1937 = eq(_T_1931, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1939 = eq(_T_1931, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1941 = eq(_T_1929, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1942 = or(_T_1939, _T_1941) @[Edges.scala 210:37] + node _T_1943 = and(_T_1942, _T_1917) @[Edges.scala 211:22] + node _T_1944 = not(_T_1935) @[Edges.scala 212:27] + node _T_1945 = and(_T_1929, _T_1944) @[Edges.scala 212:25] + when _T_1917 : @[Edges.scala 213:17] + node _T_1946 = mux(_T_1937, _T_1929, _T_1935) @[Edges.scala 214:21] + _T_1931 <= _T_1946 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1948 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1950 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1952 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1954 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_1956 : UInt, clock @[CoreplexNetwork.scala 38:36] + node _T_1958 = eq(_T_1937, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_1959 = and(io.in[0].b.valid, _T_1958) @[CoreplexNetwork.scala 38:36] + when _T_1959 : @[CoreplexNetwork.scala 38:36] + node _T_1960 = eq(io.in[0].b.bits.opcode, _T_1948) @[CoreplexNetwork.scala 38:36] + node _T_1961 = or(_T_1960, reset) @[CoreplexNetwork.scala 38:36] + node _T_1963 = eq(_T_1961, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1963 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1964 = eq(io.in[0].b.bits.param, _T_1950) @[CoreplexNetwork.scala 38:36] + node _T_1965 = or(_T_1964, reset) @[CoreplexNetwork.scala 38:36] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1967 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1968 = eq(io.in[0].b.bits.size, _T_1952) @[CoreplexNetwork.scala 38:36] + node _T_1969 = or(_T_1968, reset) @[CoreplexNetwork.scala 38:36] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1971 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1972 = eq(io.in[0].b.bits.source, _T_1954) @[CoreplexNetwork.scala 38:36] + node _T_1973 = or(_T_1972, reset) @[CoreplexNetwork.scala 38:36] + node _T_1975 = eq(_T_1973, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1975 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1976 = eq(io.in[0].b.bits.address, _T_1956) @[CoreplexNetwork.scala 38:36] + node _T_1977 = or(_T_1976, reset) @[CoreplexNetwork.scala 38:36] + node _T_1979 = eq(_T_1977, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_1979 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1980 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1981 = and(_T_1980, _T_1937) @[CoreplexNetwork.scala 38:36] + when _T_1981 : @[CoreplexNetwork.scala 38:36] + _T_1948 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 38:36] + _T_1950 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 38:36] + _T_1952 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 38:36] + _T_1954 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 38:36] + _T_1956 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_1982 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1984 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1985 = dshl(_T_1984, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1986 = bits(_T_1985, 5, 0) @[package.scala 19:76] + node _T_1987 = not(_T_1986) @[package.scala 19:40] + node _T_1988 = shr(_T_1987, 3) @[Edges.scala 198:59] + node _T_1989 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1991 = mux(_T_1989, _T_1988, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1993 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1995 = sub(_T_1993, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1996 = asUInt(_T_1995) @[Edges.scala 208:28] + node _T_1997 = tail(_T_1996, 1) @[Edges.scala 208:28] + node _T_1999 = eq(_T_1993, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2001 = eq(_T_1993, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2003 = eq(_T_1991, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2004 = or(_T_2001, _T_2003) @[Edges.scala 210:37] + node _T_2005 = and(_T_2004, _T_1982) @[Edges.scala 211:22] + node _T_2006 = not(_T_1997) @[Edges.scala 212:27] + node _T_2007 = and(_T_1991, _T_2006) @[Edges.scala 212:25] + when _T_1982 : @[Edges.scala 213:17] + node _T_2008 = mux(_T_1999, _T_1991, _T_1997) @[Edges.scala 214:21] + _T_1993 <= _T_2008 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2010 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2012 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2014 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2016 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2018 : UInt, clock @[CoreplexNetwork.scala 38:36] + node _T_2020 = eq(_T_1999, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_2021 = and(io.in[0].c.valid, _T_2020) @[CoreplexNetwork.scala 38:36] + when _T_2021 : @[CoreplexNetwork.scala 38:36] + node _T_2022 = eq(io.in[0].c.bits.opcode, _T_2010) @[CoreplexNetwork.scala 38:36] + node _T_2023 = or(_T_2022, reset) @[CoreplexNetwork.scala 38:36] + node _T_2025 = eq(_T_2023, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2025 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2026 = eq(io.in[0].c.bits.param, _T_2012) @[CoreplexNetwork.scala 38:36] + node _T_2027 = or(_T_2026, reset) @[CoreplexNetwork.scala 38:36] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2029 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2030 = eq(io.in[0].c.bits.size, _T_2014) @[CoreplexNetwork.scala 38:36] + node _T_2031 = or(_T_2030, reset) @[CoreplexNetwork.scala 38:36] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2033 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2034 = eq(io.in[0].c.bits.source, _T_2016) @[CoreplexNetwork.scala 38:36] + node _T_2035 = or(_T_2034, reset) @[CoreplexNetwork.scala 38:36] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2037 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2038 = eq(io.in[0].c.bits.address, _T_2018) @[CoreplexNetwork.scala 38:36] + node _T_2039 = or(_T_2038, reset) @[CoreplexNetwork.scala 38:36] + node _T_2041 = eq(_T_2039, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2041 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2042 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2043 = and(_T_2042, _T_1999) @[CoreplexNetwork.scala 38:36] + when _T_2043 : @[CoreplexNetwork.scala 38:36] + _T_2010 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 38:36] + _T_2012 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 38:36] + _T_2014 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 38:36] + _T_2016 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 38:36] + _T_2018 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2044 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2046 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2047 = dshl(_T_2046, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2048 = bits(_T_2047, 5, 0) @[package.scala 19:76] + node _T_2049 = not(_T_2048) @[package.scala 19:40] + node _T_2050 = shr(_T_2049, 3) @[Edges.scala 198:59] + node _T_2051 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2053 = mux(_T_2051, _T_2050, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2055 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2057 = sub(_T_2055, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2058 = asUInt(_T_2057) @[Edges.scala 208:28] + node _T_2059 = tail(_T_2058, 1) @[Edges.scala 208:28] + node _T_2061 = eq(_T_2055, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2063 = eq(_T_2055, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2065 = eq(_T_2053, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2066 = or(_T_2063, _T_2065) @[Edges.scala 210:37] + node _T_2067 = and(_T_2066, _T_2044) @[Edges.scala 211:22] + node _T_2068 = not(_T_2059) @[Edges.scala 212:27] + node _T_2069 = and(_T_2053, _T_2068) @[Edges.scala 212:25] + when _T_2044 : @[Edges.scala 213:17] + node _T_2070 = mux(_T_2061, _T_2053, _T_2059) @[Edges.scala 214:21] + _T_2055 <= _T_2070 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2072 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2074 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2076 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2078 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2080 : UInt, clock @[CoreplexNetwork.scala 38:36] + reg _T_2082 : UInt, clock @[CoreplexNetwork.scala 38:36] + node _T_2084 = eq(_T_2061, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_2085 = and(io.in[0].d.valid, _T_2084) @[CoreplexNetwork.scala 38:36] + when _T_2085 : @[CoreplexNetwork.scala 38:36] + node _T_2086 = eq(io.in[0].d.bits.opcode, _T_2072) @[CoreplexNetwork.scala 38:36] + node _T_2087 = or(_T_2086, reset) @[CoreplexNetwork.scala 38:36] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2089 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2090 = eq(io.in[0].d.bits.param, _T_2074) @[CoreplexNetwork.scala 38:36] + node _T_2091 = or(_T_2090, reset) @[CoreplexNetwork.scala 38:36] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2093 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2094 = eq(io.in[0].d.bits.size, _T_2076) @[CoreplexNetwork.scala 38:36] + node _T_2095 = or(_T_2094, reset) @[CoreplexNetwork.scala 38:36] + node _T_2097 = eq(_T_2095, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2097 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2098 = eq(io.in[0].d.bits.source, _T_2078) @[CoreplexNetwork.scala 38:36] + node _T_2099 = or(_T_2098, reset) @[CoreplexNetwork.scala 38:36] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2101 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2102 = eq(io.in[0].d.bits.sink, _T_2080) @[CoreplexNetwork.scala 38:36] + node _T_2103 = or(_T_2102, reset) @[CoreplexNetwork.scala 38:36] + node _T_2105 = eq(_T_2103, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2105 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2106 = eq(io.in[0].d.bits.addr_lo, _T_2082) @[CoreplexNetwork.scala 38:36] + node _T_2107 = or(_T_2106, reset) @[CoreplexNetwork.scala 38:36] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2109 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2110 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2111 = and(_T_2110, _T_2061) @[CoreplexNetwork.scala 38:36] + when _T_2111 : @[CoreplexNetwork.scala 38:36] + _T_2072 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 38:36] + _T_2074 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 38:36] + _T_2076 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 38:36] + _T_2078 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 38:36] + _T_2080 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 38:36] + _T_2082 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + reg _T_2113 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2114 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2116 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2117 = dshl(_T_2116, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2118 = bits(_T_2117, 5, 0) @[package.scala 19:76] + node _T_2119 = not(_T_2118) @[package.scala 19:40] + node _T_2120 = shr(_T_2119, 3) @[Edges.scala 198:59] + node _T_2121 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2123 = eq(_T_2121, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2125 = mux(_T_2123, _T_2120, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2127 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2129 = sub(_T_2127, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2130 = asUInt(_T_2129) @[Edges.scala 208:28] + node _T_2131 = tail(_T_2130, 1) @[Edges.scala 208:28] + node _T_2133 = eq(_T_2127, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2135 = eq(_T_2127, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2137 = eq(_T_2125, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2138 = or(_T_2135, _T_2137) @[Edges.scala 210:37] + node _T_2139 = and(_T_2138, _T_2114) @[Edges.scala 211:22] + node _T_2140 = not(_T_2131) @[Edges.scala 212:27] + node _T_2141 = and(_T_2125, _T_2140) @[Edges.scala 212:25] + when _T_2114 : @[Edges.scala 213:17] + node _T_2142 = mux(_T_2133, _T_2125, _T_2131) @[Edges.scala 214:21] + _T_2127 <= _T_2142 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2143 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2145 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2146 = dshl(_T_2145, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2147 = bits(_T_2146, 5, 0) @[package.scala 19:76] + node _T_2148 = not(_T_2147) @[package.scala 19:40] + node _T_2149 = shr(_T_2148, 3) @[Edges.scala 198:59] + node _T_2150 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2152 = mux(_T_2150, _T_2149, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2154 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2156 = sub(_T_2154, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2157 = asUInt(_T_2156) @[Edges.scala 208:28] + node _T_2158 = tail(_T_2157, 1) @[Edges.scala 208:28] + node _T_2160 = eq(_T_2154, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2162 = eq(_T_2154, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2164 = eq(_T_2152, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2165 = or(_T_2162, _T_2164) @[Edges.scala 210:37] + node _T_2166 = and(_T_2165, _T_2143) @[Edges.scala 211:22] + node _T_2167 = not(_T_2158) @[Edges.scala 212:27] + node _T_2168 = and(_T_2152, _T_2167) @[Edges.scala 212:25] + when _T_2143 : @[Edges.scala 213:17] + node _T_2169 = mux(_T_2160, _T_2152, _T_2158) @[Edges.scala 214:21] + _T_2154 <= _T_2169 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2171 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + node _T_2172 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 38:36] + node _T_2173 = or(_T_2171, _T_2172) @[CoreplexNetwork.scala 38:36] + node _T_2175 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_2176 = or(_T_2173, _T_2175) @[CoreplexNetwork.scala 38:36] + node _T_2178 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_2179 = or(_T_2176, _T_2178) @[CoreplexNetwork.scala 38:36] + node _T_2180 = or(_T_2179, reset) @[CoreplexNetwork.scala 38:36] + node _T_2182 = eq(_T_2180, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2182 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + wire _T_2184 : UInt<6> + _T_2184 is invalid + _T_2184 <= UInt<6>("h00") + node _T_2185 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2185 : @[CoreplexNetwork.scala 38:36] + when _T_2138 : @[CoreplexNetwork.scala 38:36] + node _T_2187 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2184 <= _T_2187 @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2188 = dshr(_T_2113, io.in[0].a.bits.source) @[CoreplexNetwork.scala 38:36] + node _T_2189 = bits(_T_2188, 0, 0) @[CoreplexNetwork.scala 38:36] + node _T_2191 = eq(_T_2189, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + node _T_2192 = or(_T_2191, reset) @[CoreplexNetwork.scala 38:36] + node _T_2194 = eq(_T_2192, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2194 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + wire _T_2196 : UInt<6> + _T_2196 is invalid + _T_2196 <= UInt<6>("h00") + node _T_2197 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2199 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 38:36] + node _T_2200 = and(_T_2197, _T_2199) @[CoreplexNetwork.scala 38:36] + when _T_2200 : @[CoreplexNetwork.scala 38:36] + when _T_2165 : @[CoreplexNetwork.scala 38:36] + node _T_2202 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2196 <= _T_2202 @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2203 = or(_T_2184, _T_2113) @[CoreplexNetwork.scala 38:36] + node _T_2204 = dshr(_T_2203, io.in[0].d.bits.source) @[CoreplexNetwork.scala 38:36] + node _T_2205 = bits(_T_2204, 0, 0) @[CoreplexNetwork.scala 38:36] + node _T_2206 = or(_T_2205, reset) @[CoreplexNetwork.scala 38:36] + node _T_2208 = eq(_T_2206, UInt<1>("h00")) @[CoreplexNetwork.scala 38:36] + when _T_2208 : @[CoreplexNetwork.scala 38:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:38:36)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 38:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + skip @[CoreplexNetwork.scala 38:36] + node _T_2209 = or(_T_2113, _T_2184) @[CoreplexNetwork.scala 38:36] + node _T_2210 = not(_T_2196) @[CoreplexNetwork.scala 38:36] + node _T_2211 = and(_T_2209, _T_2210) @[CoreplexNetwork.scala 38:36] + _T_2113 <= _T_2211 @[CoreplexNetwork.scala 38:36] + + module TLAtomicAutomata_cbus : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}} + + io is invalid + io is invalid + wire _T_539 : {state : UInt<2>} @[AtomicAutomata.scala 76:27] + _T_539 is invalid @[AtomicAutomata.scala 76:27] + _T_539.state <= UInt<1>("h00") @[AtomicAutomata.scala 77:23] + wire _T_545 : {state : UInt<2>}[1] @[AtomicAutomata.scala 78:46] + _T_545 is invalid @[AtomicAutomata.scala 78:46] + _T_545[0] <- _T_539 @[AtomicAutomata.scala 78:46] + reg _T_553 : {state : UInt<2>}[1], clock with : (reset => (reset, _T_545)) @[Reg.scala 26:44] + reg _T_598 : {bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}, fifoId : UInt<2>, lut : UInt<4>}[1], clock @[AtomicAutomata.scala 79:24] + reg _T_648 : {data : UInt<64>}[1], clock @[AtomicAutomata.scala 80:24] + node _T_656 = eq(_T_553[0].state, UInt<1>("h00")) @[AtomicAutomata.scala 82:44] + node _T_657 = eq(_T_553[0].state, UInt<2>("h02")) @[AtomicAutomata.scala 83:44] + node _T_658 = eq(_T_553[0].state, UInt<2>("h03")) @[AtomicAutomata.scala 84:49] + node _T_659 = eq(_T_553[0].state, UInt<2>("h02")) @[AtomicAutomata.scala 84:68] + node _T_660 = or(_T_658, _T_659) @[AtomicAutomata.scala 84:57] + node _T_661 = neq(_T_553[0].state, UInt<1>("h00")) @[AtomicAutomata.scala 85:49] + node _T_663 = xor(io.in.0.a.bits.address, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_664 = cvt(_T_663) @[Parameters.scala 117:49] + node _T_666 = and(_T_664, asSInt(UInt<28>("h04000000"))) @[Parameters.scala 117:52] + node _T_667 = asSInt(_T_666) @[Parameters.scala 117:52] + node _T_669 = eq(_T_667, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_671 = xor(io.in.0.a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_672 = cvt(_T_671) @[Parameters.scala 117:49] + node _T_674 = and(_T_672, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_675 = asSInt(_T_674) @[Parameters.scala 117:52] + node _T_677 = eq(_T_675, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_679 = xor(io.in.0.a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_680 = cvt(_T_679) @[Parameters.scala 117:49] + node _T_682 = and(_T_680, asSInt(UInt<28>("h06000000"))) @[Parameters.scala 117:52] + node _T_683 = asSInt(_T_682) @[Parameters.scala 117:52] + node _T_685 = eq(_T_683, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_688 : UInt<1>[3] @[Parameters.scala 112:36] + _T_688 is invalid @[Parameters.scala 112:36] + _T_688[0] <= _T_669 @[Parameters.scala 112:36] + _T_688[1] <= _T_677 @[Parameters.scala 112:36] + _T_688[2] <= _T_685 @[Parameters.scala 112:36] + node _T_697 = eq(io.in.0.a.bits.opcode, UInt<2>("h03")) @[AtomicAutomata.scala 92:47] + node _T_699 = eq(io.in.0.a.bits.opcode, UInt<2>("h02")) @[AtomicAutomata.scala 93:47] + node _T_701 = mux(_T_699, UInt<1>("h00"), UInt<1>("h01")) @[AtomicAutomata.scala 94:63] + node _T_702 = mux(_T_697, UInt<1>("h00"), _T_701) @[AtomicAutomata.scala 94:32] + node _T_704 = or(UInt<1>("h00"), _T_657) @[AtomicAutomata.scala 98:60] + node _T_706 = eq(UInt<1>("h00"), UInt<1>("h00")) @[AtomicAutomata.scala 99:83] + node _T_707 = and(_T_657, _T_706) @[AtomicAutomata.scala 99:80] + node _T_709 = mux(_T_688[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_711 = mux(_T_688[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_713 = mux(_T_688[2], UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_715 = or(_T_709, _T_711) @[Mux.scala 19:72] + node _T_716 = or(_T_715, _T_713) @[Mux.scala 19:72] + wire _T_718 : UInt<2> @[Mux.scala 19:72] + _T_718 is invalid @[Mux.scala 19:72] + _T_718 <= _T_716 @[Mux.scala 19:72] + node _T_719 = eq(_T_598[0].fifoId, _T_718) @[AtomicAutomata.scala 107:60] + node _T_720 = and(_T_660, _T_719) @[AtomicAutomata.scala 107:96] + node _T_722 = or(UInt<1>("h00"), _T_656) @[AtomicAutomata.scala 111:62] + node _T_724 = eq(UInt<1>("h00"), UInt<1>("h00")) @[AtomicAutomata.scala 112:85] + node _T_725 = and(_T_656, _T_724) @[AtomicAutomata.scala 112:82] + node _T_726 = bits(_T_598[0].bits.data, 0, 0) @[AtomicAutomata.scala 115:63] + node _T_727 = bits(_T_648[0].data, 0, 0) @[AtomicAutomata.scala 115:73] + node _T_728 = cat(_T_726, _T_727) @[Cat.scala 30:58] + node _T_729 = bits(_T_598[0].bits.data, 1, 1) @[AtomicAutomata.scala 115:63] + node _T_730 = bits(_T_648[0].data, 1, 1) @[AtomicAutomata.scala 115:73] + node _T_731 = cat(_T_729, _T_730) @[Cat.scala 30:58] + node _T_732 = bits(_T_598[0].bits.data, 2, 2) @[AtomicAutomata.scala 115:63] + node _T_733 = bits(_T_648[0].data, 2, 2) @[AtomicAutomata.scala 115:73] + node _T_734 = cat(_T_732, _T_733) @[Cat.scala 30:58] + node _T_735 = bits(_T_598[0].bits.data, 3, 3) @[AtomicAutomata.scala 115:63] + node _T_736 = bits(_T_648[0].data, 3, 3) @[AtomicAutomata.scala 115:73] + node _T_737 = cat(_T_735, _T_736) @[Cat.scala 30:58] + node _T_738 = bits(_T_598[0].bits.data, 4, 4) @[AtomicAutomata.scala 115:63] + node _T_739 = bits(_T_648[0].data, 4, 4) @[AtomicAutomata.scala 115:73] + node _T_740 = cat(_T_738, _T_739) @[Cat.scala 30:58] + node _T_741 = bits(_T_598[0].bits.data, 5, 5) @[AtomicAutomata.scala 115:63] + node _T_742 = bits(_T_648[0].data, 5, 5) @[AtomicAutomata.scala 115:73] + node _T_743 = cat(_T_741, _T_742) @[Cat.scala 30:58] + node _T_744 = bits(_T_598[0].bits.data, 6, 6) @[AtomicAutomata.scala 115:63] + node _T_745 = bits(_T_648[0].data, 6, 6) @[AtomicAutomata.scala 115:73] + node _T_746 = cat(_T_744, _T_745) @[Cat.scala 30:58] + node _T_747 = bits(_T_598[0].bits.data, 7, 7) @[AtomicAutomata.scala 115:63] + node _T_748 = bits(_T_648[0].data, 7, 7) @[AtomicAutomata.scala 115:73] + node _T_749 = cat(_T_747, _T_748) @[Cat.scala 30:58] + node _T_750 = bits(_T_598[0].bits.data, 8, 8) @[AtomicAutomata.scala 115:63] + node _T_751 = bits(_T_648[0].data, 8, 8) @[AtomicAutomata.scala 115:73] + node _T_752 = cat(_T_750, _T_751) @[Cat.scala 30:58] + node _T_753 = bits(_T_598[0].bits.data, 9, 9) @[AtomicAutomata.scala 115:63] + node _T_754 = bits(_T_648[0].data, 9, 9) @[AtomicAutomata.scala 115:73] + node _T_755 = cat(_T_753, _T_754) @[Cat.scala 30:58] + node _T_756 = bits(_T_598[0].bits.data, 10, 10) @[AtomicAutomata.scala 115:63] + node _T_757 = bits(_T_648[0].data, 10, 10) @[AtomicAutomata.scala 115:73] + node _T_758 = cat(_T_756, _T_757) @[Cat.scala 30:58] + node _T_759 = bits(_T_598[0].bits.data, 11, 11) @[AtomicAutomata.scala 115:63] + node _T_760 = bits(_T_648[0].data, 11, 11) @[AtomicAutomata.scala 115:73] + node _T_761 = cat(_T_759, _T_760) @[Cat.scala 30:58] + node _T_762 = bits(_T_598[0].bits.data, 12, 12) @[AtomicAutomata.scala 115:63] + node _T_763 = bits(_T_648[0].data, 12, 12) @[AtomicAutomata.scala 115:73] + node _T_764 = cat(_T_762, _T_763) @[Cat.scala 30:58] + node _T_765 = bits(_T_598[0].bits.data, 13, 13) @[AtomicAutomata.scala 115:63] + node _T_766 = bits(_T_648[0].data, 13, 13) @[AtomicAutomata.scala 115:73] + node _T_767 = cat(_T_765, _T_766) @[Cat.scala 30:58] + node _T_768 = bits(_T_598[0].bits.data, 14, 14) @[AtomicAutomata.scala 115:63] + node _T_769 = bits(_T_648[0].data, 14, 14) @[AtomicAutomata.scala 115:73] + node _T_770 = cat(_T_768, _T_769) @[Cat.scala 30:58] + node _T_771 = bits(_T_598[0].bits.data, 15, 15) @[AtomicAutomata.scala 115:63] + node _T_772 = bits(_T_648[0].data, 15, 15) @[AtomicAutomata.scala 115:73] + node _T_773 = cat(_T_771, _T_772) @[Cat.scala 30:58] + node _T_774 = bits(_T_598[0].bits.data, 16, 16) @[AtomicAutomata.scala 115:63] + node _T_775 = bits(_T_648[0].data, 16, 16) @[AtomicAutomata.scala 115:73] + node _T_776 = cat(_T_774, _T_775) @[Cat.scala 30:58] + node _T_777 = bits(_T_598[0].bits.data, 17, 17) @[AtomicAutomata.scala 115:63] + node _T_778 = bits(_T_648[0].data, 17, 17) @[AtomicAutomata.scala 115:73] + node _T_779 = cat(_T_777, _T_778) @[Cat.scala 30:58] + node _T_780 = bits(_T_598[0].bits.data, 18, 18) @[AtomicAutomata.scala 115:63] + node _T_781 = bits(_T_648[0].data, 18, 18) @[AtomicAutomata.scala 115:73] + node _T_782 = cat(_T_780, _T_781) @[Cat.scala 30:58] + node _T_783 = bits(_T_598[0].bits.data, 19, 19) @[AtomicAutomata.scala 115:63] + node _T_784 = bits(_T_648[0].data, 19, 19) @[AtomicAutomata.scala 115:73] + node _T_785 = cat(_T_783, _T_784) @[Cat.scala 30:58] + node _T_786 = bits(_T_598[0].bits.data, 20, 20) @[AtomicAutomata.scala 115:63] + node _T_787 = bits(_T_648[0].data, 20, 20) @[AtomicAutomata.scala 115:73] + node _T_788 = cat(_T_786, _T_787) @[Cat.scala 30:58] + node _T_789 = bits(_T_598[0].bits.data, 21, 21) @[AtomicAutomata.scala 115:63] + node _T_790 = bits(_T_648[0].data, 21, 21) @[AtomicAutomata.scala 115:73] + node _T_791 = cat(_T_789, _T_790) @[Cat.scala 30:58] + node _T_792 = bits(_T_598[0].bits.data, 22, 22) @[AtomicAutomata.scala 115:63] + node _T_793 = bits(_T_648[0].data, 22, 22) @[AtomicAutomata.scala 115:73] + node _T_794 = cat(_T_792, _T_793) @[Cat.scala 30:58] + node _T_795 = bits(_T_598[0].bits.data, 23, 23) @[AtomicAutomata.scala 115:63] + node _T_796 = bits(_T_648[0].data, 23, 23) @[AtomicAutomata.scala 115:73] + node _T_797 = cat(_T_795, _T_796) @[Cat.scala 30:58] + node _T_798 = bits(_T_598[0].bits.data, 24, 24) @[AtomicAutomata.scala 115:63] + node _T_799 = bits(_T_648[0].data, 24, 24) @[AtomicAutomata.scala 115:73] + node _T_800 = cat(_T_798, _T_799) @[Cat.scala 30:58] + node _T_801 = bits(_T_598[0].bits.data, 25, 25) @[AtomicAutomata.scala 115:63] + node _T_802 = bits(_T_648[0].data, 25, 25) @[AtomicAutomata.scala 115:73] + node _T_803 = cat(_T_801, _T_802) @[Cat.scala 30:58] + node _T_804 = bits(_T_598[0].bits.data, 26, 26) @[AtomicAutomata.scala 115:63] + node _T_805 = bits(_T_648[0].data, 26, 26) @[AtomicAutomata.scala 115:73] + node _T_806 = cat(_T_804, _T_805) @[Cat.scala 30:58] + node _T_807 = bits(_T_598[0].bits.data, 27, 27) @[AtomicAutomata.scala 115:63] + node _T_808 = bits(_T_648[0].data, 27, 27) @[AtomicAutomata.scala 115:73] + node _T_809 = cat(_T_807, _T_808) @[Cat.scala 30:58] + node _T_810 = bits(_T_598[0].bits.data, 28, 28) @[AtomicAutomata.scala 115:63] + node _T_811 = bits(_T_648[0].data, 28, 28) @[AtomicAutomata.scala 115:73] + node _T_812 = cat(_T_810, _T_811) @[Cat.scala 30:58] + node _T_813 = bits(_T_598[0].bits.data, 29, 29) @[AtomicAutomata.scala 115:63] + node _T_814 = bits(_T_648[0].data, 29, 29) @[AtomicAutomata.scala 115:73] + node _T_815 = cat(_T_813, _T_814) @[Cat.scala 30:58] + node _T_816 = bits(_T_598[0].bits.data, 30, 30) @[AtomicAutomata.scala 115:63] + node _T_817 = bits(_T_648[0].data, 30, 30) @[AtomicAutomata.scala 115:73] + node _T_818 = cat(_T_816, _T_817) @[Cat.scala 30:58] + node _T_819 = bits(_T_598[0].bits.data, 31, 31) @[AtomicAutomata.scala 115:63] + node _T_820 = bits(_T_648[0].data, 31, 31) @[AtomicAutomata.scala 115:73] + node _T_821 = cat(_T_819, _T_820) @[Cat.scala 30:58] + node _T_822 = bits(_T_598[0].bits.data, 32, 32) @[AtomicAutomata.scala 115:63] + node _T_823 = bits(_T_648[0].data, 32, 32) @[AtomicAutomata.scala 115:73] + node _T_824 = cat(_T_822, _T_823) @[Cat.scala 30:58] + node _T_825 = bits(_T_598[0].bits.data, 33, 33) @[AtomicAutomata.scala 115:63] + node _T_826 = bits(_T_648[0].data, 33, 33) @[AtomicAutomata.scala 115:73] + node _T_827 = cat(_T_825, _T_826) @[Cat.scala 30:58] + node _T_828 = bits(_T_598[0].bits.data, 34, 34) @[AtomicAutomata.scala 115:63] + node _T_829 = bits(_T_648[0].data, 34, 34) @[AtomicAutomata.scala 115:73] + node _T_830 = cat(_T_828, _T_829) @[Cat.scala 30:58] + node _T_831 = bits(_T_598[0].bits.data, 35, 35) @[AtomicAutomata.scala 115:63] + node _T_832 = bits(_T_648[0].data, 35, 35) @[AtomicAutomata.scala 115:73] + node _T_833 = cat(_T_831, _T_832) @[Cat.scala 30:58] + node _T_834 = bits(_T_598[0].bits.data, 36, 36) @[AtomicAutomata.scala 115:63] + node _T_835 = bits(_T_648[0].data, 36, 36) @[AtomicAutomata.scala 115:73] + node _T_836 = cat(_T_834, _T_835) @[Cat.scala 30:58] + node _T_837 = bits(_T_598[0].bits.data, 37, 37) @[AtomicAutomata.scala 115:63] + node _T_838 = bits(_T_648[0].data, 37, 37) @[AtomicAutomata.scala 115:73] + node _T_839 = cat(_T_837, _T_838) @[Cat.scala 30:58] + node _T_840 = bits(_T_598[0].bits.data, 38, 38) @[AtomicAutomata.scala 115:63] + node _T_841 = bits(_T_648[0].data, 38, 38) @[AtomicAutomata.scala 115:73] + node _T_842 = cat(_T_840, _T_841) @[Cat.scala 30:58] + node _T_843 = bits(_T_598[0].bits.data, 39, 39) @[AtomicAutomata.scala 115:63] + node _T_844 = bits(_T_648[0].data, 39, 39) @[AtomicAutomata.scala 115:73] + node _T_845 = cat(_T_843, _T_844) @[Cat.scala 30:58] + node _T_846 = bits(_T_598[0].bits.data, 40, 40) @[AtomicAutomata.scala 115:63] + node _T_847 = bits(_T_648[0].data, 40, 40) @[AtomicAutomata.scala 115:73] + node _T_848 = cat(_T_846, _T_847) @[Cat.scala 30:58] + node _T_849 = bits(_T_598[0].bits.data, 41, 41) @[AtomicAutomata.scala 115:63] + node _T_850 = bits(_T_648[0].data, 41, 41) @[AtomicAutomata.scala 115:73] + node _T_851 = cat(_T_849, _T_850) @[Cat.scala 30:58] + node _T_852 = bits(_T_598[0].bits.data, 42, 42) @[AtomicAutomata.scala 115:63] + node _T_853 = bits(_T_648[0].data, 42, 42) @[AtomicAutomata.scala 115:73] + node _T_854 = cat(_T_852, _T_853) @[Cat.scala 30:58] + node _T_855 = bits(_T_598[0].bits.data, 43, 43) @[AtomicAutomata.scala 115:63] + node _T_856 = bits(_T_648[0].data, 43, 43) @[AtomicAutomata.scala 115:73] + node _T_857 = cat(_T_855, _T_856) @[Cat.scala 30:58] + node _T_858 = bits(_T_598[0].bits.data, 44, 44) @[AtomicAutomata.scala 115:63] + node _T_859 = bits(_T_648[0].data, 44, 44) @[AtomicAutomata.scala 115:73] + node _T_860 = cat(_T_858, _T_859) @[Cat.scala 30:58] + node _T_861 = bits(_T_598[0].bits.data, 45, 45) @[AtomicAutomata.scala 115:63] + node _T_862 = bits(_T_648[0].data, 45, 45) @[AtomicAutomata.scala 115:73] + node _T_863 = cat(_T_861, _T_862) @[Cat.scala 30:58] + node _T_864 = bits(_T_598[0].bits.data, 46, 46) @[AtomicAutomata.scala 115:63] + node _T_865 = bits(_T_648[0].data, 46, 46) @[AtomicAutomata.scala 115:73] + node _T_866 = cat(_T_864, _T_865) @[Cat.scala 30:58] + node _T_867 = bits(_T_598[0].bits.data, 47, 47) @[AtomicAutomata.scala 115:63] + node _T_868 = bits(_T_648[0].data, 47, 47) @[AtomicAutomata.scala 115:73] + node _T_869 = cat(_T_867, _T_868) @[Cat.scala 30:58] + node _T_870 = bits(_T_598[0].bits.data, 48, 48) @[AtomicAutomata.scala 115:63] + node _T_871 = bits(_T_648[0].data, 48, 48) @[AtomicAutomata.scala 115:73] + node _T_872 = cat(_T_870, _T_871) @[Cat.scala 30:58] + node _T_873 = bits(_T_598[0].bits.data, 49, 49) @[AtomicAutomata.scala 115:63] + node _T_874 = bits(_T_648[0].data, 49, 49) @[AtomicAutomata.scala 115:73] + node _T_875 = cat(_T_873, _T_874) @[Cat.scala 30:58] + node _T_876 = bits(_T_598[0].bits.data, 50, 50) @[AtomicAutomata.scala 115:63] + node _T_877 = bits(_T_648[0].data, 50, 50) @[AtomicAutomata.scala 115:73] + node _T_878 = cat(_T_876, _T_877) @[Cat.scala 30:58] + node _T_879 = bits(_T_598[0].bits.data, 51, 51) @[AtomicAutomata.scala 115:63] + node _T_880 = bits(_T_648[0].data, 51, 51) @[AtomicAutomata.scala 115:73] + node _T_881 = cat(_T_879, _T_880) @[Cat.scala 30:58] + node _T_882 = bits(_T_598[0].bits.data, 52, 52) @[AtomicAutomata.scala 115:63] + node _T_883 = bits(_T_648[0].data, 52, 52) @[AtomicAutomata.scala 115:73] + node _T_884 = cat(_T_882, _T_883) @[Cat.scala 30:58] + node _T_885 = bits(_T_598[0].bits.data, 53, 53) @[AtomicAutomata.scala 115:63] + node _T_886 = bits(_T_648[0].data, 53, 53) @[AtomicAutomata.scala 115:73] + node _T_887 = cat(_T_885, _T_886) @[Cat.scala 30:58] + node _T_888 = bits(_T_598[0].bits.data, 54, 54) @[AtomicAutomata.scala 115:63] + node _T_889 = bits(_T_648[0].data, 54, 54) @[AtomicAutomata.scala 115:73] + node _T_890 = cat(_T_888, _T_889) @[Cat.scala 30:58] + node _T_891 = bits(_T_598[0].bits.data, 55, 55) @[AtomicAutomata.scala 115:63] + node _T_892 = bits(_T_648[0].data, 55, 55) @[AtomicAutomata.scala 115:73] + node _T_893 = cat(_T_891, _T_892) @[Cat.scala 30:58] + node _T_894 = bits(_T_598[0].bits.data, 56, 56) @[AtomicAutomata.scala 115:63] + node _T_895 = bits(_T_648[0].data, 56, 56) @[AtomicAutomata.scala 115:73] + node _T_896 = cat(_T_894, _T_895) @[Cat.scala 30:58] + node _T_897 = bits(_T_598[0].bits.data, 57, 57) @[AtomicAutomata.scala 115:63] + node _T_898 = bits(_T_648[0].data, 57, 57) @[AtomicAutomata.scala 115:73] + node _T_899 = cat(_T_897, _T_898) @[Cat.scala 30:58] + node _T_900 = bits(_T_598[0].bits.data, 58, 58) @[AtomicAutomata.scala 115:63] + node _T_901 = bits(_T_648[0].data, 58, 58) @[AtomicAutomata.scala 115:73] + node _T_902 = cat(_T_900, _T_901) @[Cat.scala 30:58] + node _T_903 = bits(_T_598[0].bits.data, 59, 59) @[AtomicAutomata.scala 115:63] + node _T_904 = bits(_T_648[0].data, 59, 59) @[AtomicAutomata.scala 115:73] + node _T_905 = cat(_T_903, _T_904) @[Cat.scala 30:58] + node _T_906 = bits(_T_598[0].bits.data, 60, 60) @[AtomicAutomata.scala 115:63] + node _T_907 = bits(_T_648[0].data, 60, 60) @[AtomicAutomata.scala 115:73] + node _T_908 = cat(_T_906, _T_907) @[Cat.scala 30:58] + node _T_909 = bits(_T_598[0].bits.data, 61, 61) @[AtomicAutomata.scala 115:63] + node _T_910 = bits(_T_648[0].data, 61, 61) @[AtomicAutomata.scala 115:73] + node _T_911 = cat(_T_909, _T_910) @[Cat.scala 30:58] + node _T_912 = bits(_T_598[0].bits.data, 62, 62) @[AtomicAutomata.scala 115:63] + node _T_913 = bits(_T_648[0].data, 62, 62) @[AtomicAutomata.scala 115:73] + node _T_914 = cat(_T_912, _T_913) @[Cat.scala 30:58] + node _T_915 = bits(_T_598[0].bits.data, 63, 63) @[AtomicAutomata.scala 115:63] + node _T_916 = bits(_T_648[0].data, 63, 63) @[AtomicAutomata.scala 115:73] + node _T_917 = cat(_T_915, _T_916) @[Cat.scala 30:58] + node _T_918 = dshr(_T_598[0].lut, _T_728) @[AtomicAutomata.scala 116:57] + node _T_919 = bits(_T_918, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_920 = dshr(_T_598[0].lut, _T_731) @[AtomicAutomata.scala 116:57] + node _T_921 = bits(_T_920, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_922 = dshr(_T_598[0].lut, _T_734) @[AtomicAutomata.scala 116:57] + node _T_923 = bits(_T_922, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_924 = dshr(_T_598[0].lut, _T_737) @[AtomicAutomata.scala 116:57] + node _T_925 = bits(_T_924, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_926 = dshr(_T_598[0].lut, _T_740) @[AtomicAutomata.scala 116:57] + node _T_927 = bits(_T_926, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_928 = dshr(_T_598[0].lut, _T_743) @[AtomicAutomata.scala 116:57] + node _T_929 = bits(_T_928, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_930 = dshr(_T_598[0].lut, _T_746) @[AtomicAutomata.scala 116:57] + node _T_931 = bits(_T_930, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_932 = dshr(_T_598[0].lut, _T_749) @[AtomicAutomata.scala 116:57] + node _T_933 = bits(_T_932, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_934 = dshr(_T_598[0].lut, _T_752) @[AtomicAutomata.scala 116:57] + node _T_935 = bits(_T_934, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_936 = dshr(_T_598[0].lut, _T_755) @[AtomicAutomata.scala 116:57] + node _T_937 = bits(_T_936, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_938 = dshr(_T_598[0].lut, _T_758) @[AtomicAutomata.scala 116:57] + node _T_939 = bits(_T_938, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_940 = dshr(_T_598[0].lut, _T_761) @[AtomicAutomata.scala 116:57] + node _T_941 = bits(_T_940, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_942 = dshr(_T_598[0].lut, _T_764) @[AtomicAutomata.scala 116:57] + node _T_943 = bits(_T_942, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_944 = dshr(_T_598[0].lut, _T_767) @[AtomicAutomata.scala 116:57] + node _T_945 = bits(_T_944, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_946 = dshr(_T_598[0].lut, _T_770) @[AtomicAutomata.scala 116:57] + node _T_947 = bits(_T_946, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_948 = dshr(_T_598[0].lut, _T_773) @[AtomicAutomata.scala 116:57] + node _T_949 = bits(_T_948, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_950 = dshr(_T_598[0].lut, _T_776) @[AtomicAutomata.scala 116:57] + node _T_951 = bits(_T_950, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_952 = dshr(_T_598[0].lut, _T_779) @[AtomicAutomata.scala 116:57] + node _T_953 = bits(_T_952, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_954 = dshr(_T_598[0].lut, _T_782) @[AtomicAutomata.scala 116:57] + node _T_955 = bits(_T_954, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_956 = dshr(_T_598[0].lut, _T_785) @[AtomicAutomata.scala 116:57] + node _T_957 = bits(_T_956, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_958 = dshr(_T_598[0].lut, _T_788) @[AtomicAutomata.scala 116:57] + node _T_959 = bits(_T_958, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_960 = dshr(_T_598[0].lut, _T_791) @[AtomicAutomata.scala 116:57] + node _T_961 = bits(_T_960, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_962 = dshr(_T_598[0].lut, _T_794) @[AtomicAutomata.scala 116:57] + node _T_963 = bits(_T_962, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_964 = dshr(_T_598[0].lut, _T_797) @[AtomicAutomata.scala 116:57] + node _T_965 = bits(_T_964, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_966 = dshr(_T_598[0].lut, _T_800) @[AtomicAutomata.scala 116:57] + node _T_967 = bits(_T_966, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_968 = dshr(_T_598[0].lut, _T_803) @[AtomicAutomata.scala 116:57] + node _T_969 = bits(_T_968, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_970 = dshr(_T_598[0].lut, _T_806) @[AtomicAutomata.scala 116:57] + node _T_971 = bits(_T_970, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_972 = dshr(_T_598[0].lut, _T_809) @[AtomicAutomata.scala 116:57] + node _T_973 = bits(_T_972, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_974 = dshr(_T_598[0].lut, _T_812) @[AtomicAutomata.scala 116:57] + node _T_975 = bits(_T_974, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_976 = dshr(_T_598[0].lut, _T_815) @[AtomicAutomata.scala 116:57] + node _T_977 = bits(_T_976, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_978 = dshr(_T_598[0].lut, _T_818) @[AtomicAutomata.scala 116:57] + node _T_979 = bits(_T_978, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_980 = dshr(_T_598[0].lut, _T_821) @[AtomicAutomata.scala 116:57] + node _T_981 = bits(_T_980, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_982 = dshr(_T_598[0].lut, _T_824) @[AtomicAutomata.scala 116:57] + node _T_983 = bits(_T_982, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_984 = dshr(_T_598[0].lut, _T_827) @[AtomicAutomata.scala 116:57] + node _T_985 = bits(_T_984, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_986 = dshr(_T_598[0].lut, _T_830) @[AtomicAutomata.scala 116:57] + node _T_987 = bits(_T_986, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_988 = dshr(_T_598[0].lut, _T_833) @[AtomicAutomata.scala 116:57] + node _T_989 = bits(_T_988, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_990 = dshr(_T_598[0].lut, _T_836) @[AtomicAutomata.scala 116:57] + node _T_991 = bits(_T_990, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_992 = dshr(_T_598[0].lut, _T_839) @[AtomicAutomata.scala 116:57] + node _T_993 = bits(_T_992, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_994 = dshr(_T_598[0].lut, _T_842) @[AtomicAutomata.scala 116:57] + node _T_995 = bits(_T_994, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_996 = dshr(_T_598[0].lut, _T_845) @[AtomicAutomata.scala 116:57] + node _T_997 = bits(_T_996, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_998 = dshr(_T_598[0].lut, _T_848) @[AtomicAutomata.scala 116:57] + node _T_999 = bits(_T_998, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1000 = dshr(_T_598[0].lut, _T_851) @[AtomicAutomata.scala 116:57] + node _T_1001 = bits(_T_1000, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1002 = dshr(_T_598[0].lut, _T_854) @[AtomicAutomata.scala 116:57] + node _T_1003 = bits(_T_1002, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1004 = dshr(_T_598[0].lut, _T_857) @[AtomicAutomata.scala 116:57] + node _T_1005 = bits(_T_1004, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1006 = dshr(_T_598[0].lut, _T_860) @[AtomicAutomata.scala 116:57] + node _T_1007 = bits(_T_1006, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1008 = dshr(_T_598[0].lut, _T_863) @[AtomicAutomata.scala 116:57] + node _T_1009 = bits(_T_1008, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1010 = dshr(_T_598[0].lut, _T_866) @[AtomicAutomata.scala 116:57] + node _T_1011 = bits(_T_1010, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1012 = dshr(_T_598[0].lut, _T_869) @[AtomicAutomata.scala 116:57] + node _T_1013 = bits(_T_1012, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1014 = dshr(_T_598[0].lut, _T_872) @[AtomicAutomata.scala 116:57] + node _T_1015 = bits(_T_1014, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1016 = dshr(_T_598[0].lut, _T_875) @[AtomicAutomata.scala 116:57] + node _T_1017 = bits(_T_1016, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1018 = dshr(_T_598[0].lut, _T_878) @[AtomicAutomata.scala 116:57] + node _T_1019 = bits(_T_1018, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1020 = dshr(_T_598[0].lut, _T_881) @[AtomicAutomata.scala 116:57] + node _T_1021 = bits(_T_1020, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1022 = dshr(_T_598[0].lut, _T_884) @[AtomicAutomata.scala 116:57] + node _T_1023 = bits(_T_1022, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1024 = dshr(_T_598[0].lut, _T_887) @[AtomicAutomata.scala 116:57] + node _T_1025 = bits(_T_1024, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1026 = dshr(_T_598[0].lut, _T_890) @[AtomicAutomata.scala 116:57] + node _T_1027 = bits(_T_1026, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1028 = dshr(_T_598[0].lut, _T_893) @[AtomicAutomata.scala 116:57] + node _T_1029 = bits(_T_1028, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1030 = dshr(_T_598[0].lut, _T_896) @[AtomicAutomata.scala 116:57] + node _T_1031 = bits(_T_1030, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1032 = dshr(_T_598[0].lut, _T_899) @[AtomicAutomata.scala 116:57] + node _T_1033 = bits(_T_1032, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1034 = dshr(_T_598[0].lut, _T_902) @[AtomicAutomata.scala 116:57] + node _T_1035 = bits(_T_1034, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1036 = dshr(_T_598[0].lut, _T_905) @[AtomicAutomata.scala 116:57] + node _T_1037 = bits(_T_1036, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1038 = dshr(_T_598[0].lut, _T_908) @[AtomicAutomata.scala 116:57] + node _T_1039 = bits(_T_1038, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1040 = dshr(_T_598[0].lut, _T_911) @[AtomicAutomata.scala 116:57] + node _T_1041 = bits(_T_1040, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1042 = dshr(_T_598[0].lut, _T_914) @[AtomicAutomata.scala 116:57] + node _T_1043 = bits(_T_1042, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1044 = dshr(_T_598[0].lut, _T_917) @[AtomicAutomata.scala 116:57] + node _T_1045 = bits(_T_1044, 0, 0) @[AtomicAutomata.scala 116:57] + node _T_1046 = cat(_T_921, _T_919) @[Cat.scala 30:58] + node _T_1047 = cat(_T_925, _T_923) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1046) @[Cat.scala 30:58] + node _T_1049 = cat(_T_929, _T_927) @[Cat.scala 30:58] + node _T_1050 = cat(_T_933, _T_931) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1050, _T_1049) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1048) @[Cat.scala 30:58] + node _T_1053 = cat(_T_937, _T_935) @[Cat.scala 30:58] + node _T_1054 = cat(_T_941, _T_939) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_945, _T_943) @[Cat.scala 30:58] + node _T_1057 = cat(_T_949, _T_947) @[Cat.scala 30:58] + node _T_1058 = cat(_T_1057, _T_1056) @[Cat.scala 30:58] + node _T_1059 = cat(_T_1058, _T_1055) @[Cat.scala 30:58] + node _T_1060 = cat(_T_1059, _T_1052) @[Cat.scala 30:58] + node _T_1061 = cat(_T_953, _T_951) @[Cat.scala 30:58] + node _T_1062 = cat(_T_957, _T_955) @[Cat.scala 30:58] + node _T_1063 = cat(_T_1062, _T_1061) @[Cat.scala 30:58] + node _T_1064 = cat(_T_961, _T_959) @[Cat.scala 30:58] + node _T_1065 = cat(_T_965, _T_963) @[Cat.scala 30:58] + node _T_1066 = cat(_T_1065, _T_1064) @[Cat.scala 30:58] + node _T_1067 = cat(_T_1066, _T_1063) @[Cat.scala 30:58] + node _T_1068 = cat(_T_969, _T_967) @[Cat.scala 30:58] + node _T_1069 = cat(_T_973, _T_971) @[Cat.scala 30:58] + node _T_1070 = cat(_T_1069, _T_1068) @[Cat.scala 30:58] + node _T_1071 = cat(_T_977, _T_975) @[Cat.scala 30:58] + node _T_1072 = cat(_T_981, _T_979) @[Cat.scala 30:58] + node _T_1073 = cat(_T_1072, _T_1071) @[Cat.scala 30:58] + node _T_1074 = cat(_T_1073, _T_1070) @[Cat.scala 30:58] + node _T_1075 = cat(_T_1074, _T_1067) @[Cat.scala 30:58] + node _T_1076 = cat(_T_1075, _T_1060) @[Cat.scala 30:58] + node _T_1077 = cat(_T_985, _T_983) @[Cat.scala 30:58] + node _T_1078 = cat(_T_989, _T_987) @[Cat.scala 30:58] + node _T_1079 = cat(_T_1078, _T_1077) @[Cat.scala 30:58] + node _T_1080 = cat(_T_993, _T_991) @[Cat.scala 30:58] + node _T_1081 = cat(_T_997, _T_995) @[Cat.scala 30:58] + node _T_1082 = cat(_T_1081, _T_1080) @[Cat.scala 30:58] + node _T_1083 = cat(_T_1082, _T_1079) @[Cat.scala 30:58] + node _T_1084 = cat(_T_1001, _T_999) @[Cat.scala 30:58] + node _T_1085 = cat(_T_1005, _T_1003) @[Cat.scala 30:58] + node _T_1086 = cat(_T_1085, _T_1084) @[Cat.scala 30:58] + node _T_1087 = cat(_T_1009, _T_1007) @[Cat.scala 30:58] + node _T_1088 = cat(_T_1013, _T_1011) @[Cat.scala 30:58] + node _T_1089 = cat(_T_1088, _T_1087) @[Cat.scala 30:58] + node _T_1090 = cat(_T_1089, _T_1086) @[Cat.scala 30:58] + node _T_1091 = cat(_T_1090, _T_1083) @[Cat.scala 30:58] + node _T_1092 = cat(_T_1017, _T_1015) @[Cat.scala 30:58] + node _T_1093 = cat(_T_1021, _T_1019) @[Cat.scala 30:58] + node _T_1094 = cat(_T_1093, _T_1092) @[Cat.scala 30:58] + node _T_1095 = cat(_T_1025, _T_1023) @[Cat.scala 30:58] + node _T_1096 = cat(_T_1029, _T_1027) @[Cat.scala 30:58] + node _T_1097 = cat(_T_1096, _T_1095) @[Cat.scala 30:58] + node _T_1098 = cat(_T_1097, _T_1094) @[Cat.scala 30:58] + node _T_1099 = cat(_T_1033, _T_1031) @[Cat.scala 30:58] + node _T_1100 = cat(_T_1037, _T_1035) @[Cat.scala 30:58] + node _T_1101 = cat(_T_1100, _T_1099) @[Cat.scala 30:58] + node _T_1102 = cat(_T_1041, _T_1039) @[Cat.scala 30:58] + node _T_1103 = cat(_T_1045, _T_1043) @[Cat.scala 30:58] + node _T_1104 = cat(_T_1103, _T_1102) @[Cat.scala 30:58] + node _T_1105 = cat(_T_1104, _T_1101) @[Cat.scala 30:58] + node _T_1106 = cat(_T_1105, _T_1098) @[Cat.scala 30:58] + node _T_1107 = cat(_T_1106, _T_1091) @[Cat.scala 30:58] + node _T_1108 = cat(_T_1107, _T_1076) @[Cat.scala 30:58] + node _T_1109 = bits(_T_598[0].bits.param, 1, 1) @[AtomicAutomata.scala 119:42] + node _T_1110 = bits(_T_598[0].bits.param, 0, 0) @[AtomicAutomata.scala 120:42] + node _T_1111 = bits(_T_598[0].bits.param, 2, 2) @[AtomicAutomata.scala 121:39] + node _T_1112 = not(_T_598[0].bits.mask) @[AtomicAutomata.scala 123:25] + node _T_1113 = shr(_T_598[0].bits.mask, 1) @[AtomicAutomata.scala 123:39] + node _T_1114 = or(_T_1112, _T_1113) @[AtomicAutomata.scala 123:31] + node _T_1115 = not(_T_1114) @[AtomicAutomata.scala 123:23] + node _T_1116 = bits(_T_598[0].bits.data, 7, 7) @[AtomicAutomata.scala 124:64] + node _T_1117 = bits(_T_598[0].bits.data, 15, 15) @[AtomicAutomata.scala 124:64] + node _T_1118 = bits(_T_598[0].bits.data, 23, 23) @[AtomicAutomata.scala 124:64] + node _T_1119 = bits(_T_598[0].bits.data, 31, 31) @[AtomicAutomata.scala 124:64] + node _T_1120 = bits(_T_598[0].bits.data, 39, 39) @[AtomicAutomata.scala 124:64] + node _T_1121 = bits(_T_598[0].bits.data, 47, 47) @[AtomicAutomata.scala 124:64] + node _T_1122 = bits(_T_598[0].bits.data, 55, 55) @[AtomicAutomata.scala 124:64] + node _T_1123 = bits(_T_598[0].bits.data, 63, 63) @[AtomicAutomata.scala 124:64] + node _T_1124 = cat(_T_1117, _T_1116) @[Cat.scala 30:58] + node _T_1125 = cat(_T_1119, _T_1118) @[Cat.scala 30:58] + node _T_1126 = cat(_T_1125, _T_1124) @[Cat.scala 30:58] + node _T_1127 = cat(_T_1121, _T_1120) @[Cat.scala 30:58] + node _T_1128 = cat(_T_1123, _T_1122) @[Cat.scala 30:58] + node _T_1129 = cat(_T_1128, _T_1127) @[Cat.scala 30:58] + node _T_1130 = cat(_T_1129, _T_1126) @[Cat.scala 30:58] + node _T_1131 = bits(_T_648[0].data, 7, 7) @[AtomicAutomata.scala 125:64] + node _T_1132 = bits(_T_648[0].data, 15, 15) @[AtomicAutomata.scala 125:64] + node _T_1133 = bits(_T_648[0].data, 23, 23) @[AtomicAutomata.scala 125:64] + node _T_1134 = bits(_T_648[0].data, 31, 31) @[AtomicAutomata.scala 125:64] + node _T_1135 = bits(_T_648[0].data, 39, 39) @[AtomicAutomata.scala 125:64] + node _T_1136 = bits(_T_648[0].data, 47, 47) @[AtomicAutomata.scala 125:64] + node _T_1137 = bits(_T_648[0].data, 55, 55) @[AtomicAutomata.scala 125:64] + node _T_1138 = bits(_T_648[0].data, 63, 63) @[AtomicAutomata.scala 125:64] + node _T_1139 = cat(_T_1132, _T_1131) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1134, _T_1133) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1136, _T_1135) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1137) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1146 = and(_T_1130, _T_1115) @[AtomicAutomata.scala 127:38] + node _T_1147 = shl(_T_1146, 1) @[AtomicAutomata.scala 127:49] + node _T_1148 = bits(_T_1147, 7, 0) @[AtomicAutomata.scala 127:54] + node _T_1149 = and(_T_1145, _T_1115) @[AtomicAutomata.scala 128:38] + node _T_1150 = shl(_T_1149, 1) @[AtomicAutomata.scala 128:49] + node _T_1151 = bits(_T_1150, 7, 0) @[AtomicAutomata.scala 128:54] + node _T_1152 = shl(_T_1148, 1) @[package.scala 25:45] + node _T_1153 = bits(_T_1152, 7, 0) @[package.scala 25:50] + node _T_1154 = or(_T_1148, _T_1153) @[package.scala 25:40] + node _T_1155 = shl(_T_1154, 2) @[package.scala 25:45] + node _T_1156 = bits(_T_1155, 7, 0) @[package.scala 25:50] + node _T_1157 = or(_T_1154, _T_1156) @[package.scala 25:40] + node _T_1158 = shl(_T_1157, 4) @[package.scala 25:45] + node _T_1159 = bits(_T_1158, 7, 0) @[package.scala 25:50] + node _T_1160 = or(_T_1157, _T_1159) @[package.scala 25:40] + node _T_1161 = bits(_T_1160, 0, 0) @[Bitwise.scala 27:51] + node _T_1162 = bits(_T_1160, 1, 1) @[Bitwise.scala 27:51] + node _T_1163 = bits(_T_1160, 2, 2) @[Bitwise.scala 27:51] + node _T_1164 = bits(_T_1160, 3, 3) @[Bitwise.scala 27:51] + node _T_1165 = bits(_T_1160, 4, 4) @[Bitwise.scala 27:51] + node _T_1166 = bits(_T_1160, 5, 5) @[Bitwise.scala 27:51] + node _T_1167 = bits(_T_1160, 6, 6) @[Bitwise.scala 27:51] + node _T_1168 = bits(_T_1160, 7, 7) @[Bitwise.scala 27:51] + node _T_1169 = bits(_T_1161, 0, 0) @[Bitwise.scala 71:15] + node _T_1172 = mux(_T_1169, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1173 = bits(_T_1162, 0, 0) @[Bitwise.scala 71:15] + node _T_1176 = mux(_T_1173, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1177 = bits(_T_1163, 0, 0) @[Bitwise.scala 71:15] + node _T_1180 = mux(_T_1177, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1181 = bits(_T_1164, 0, 0) @[Bitwise.scala 71:15] + node _T_1184 = mux(_T_1181, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1185 = bits(_T_1165, 0, 0) @[Bitwise.scala 71:15] + node _T_1188 = mux(_T_1185, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1189 = bits(_T_1166, 0, 0) @[Bitwise.scala 71:15] + node _T_1192 = mux(_T_1189, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1193 = bits(_T_1167, 0, 0) @[Bitwise.scala 71:15] + node _T_1196 = mux(_T_1193, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1197 = bits(_T_1168, 0, 0) @[Bitwise.scala 71:15] + node _T_1200 = mux(_T_1197, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1201 = cat(_T_1176, _T_1172) @[Cat.scala 30:58] + node _T_1202 = cat(_T_1184, _T_1180) @[Cat.scala 30:58] + node _T_1203 = cat(_T_1202, _T_1201) @[Cat.scala 30:58] + node _T_1204 = cat(_T_1192, _T_1188) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1200, _T_1196) @[Cat.scala 30:58] + node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 30:58] + node _T_1207 = cat(_T_1206, _T_1203) @[Cat.scala 30:58] + node _T_1208 = shl(_T_1151, 1) @[package.scala 25:45] + node _T_1209 = bits(_T_1208, 7, 0) @[package.scala 25:50] + node _T_1210 = or(_T_1151, _T_1209) @[package.scala 25:40] + node _T_1211 = shl(_T_1210, 2) @[package.scala 25:45] + node _T_1212 = bits(_T_1211, 7, 0) @[package.scala 25:50] + node _T_1213 = or(_T_1210, _T_1212) @[package.scala 25:40] + node _T_1214 = shl(_T_1213, 4) @[package.scala 25:45] + node _T_1215 = bits(_T_1214, 7, 0) @[package.scala 25:50] + node _T_1216 = or(_T_1213, _T_1215) @[package.scala 25:40] + node _T_1217 = bits(_T_1216, 0, 0) @[Bitwise.scala 27:51] + node _T_1218 = bits(_T_1216, 1, 1) @[Bitwise.scala 27:51] + node _T_1219 = bits(_T_1216, 2, 2) @[Bitwise.scala 27:51] + node _T_1220 = bits(_T_1216, 3, 3) @[Bitwise.scala 27:51] + node _T_1221 = bits(_T_1216, 4, 4) @[Bitwise.scala 27:51] + node _T_1222 = bits(_T_1216, 5, 5) @[Bitwise.scala 27:51] + node _T_1223 = bits(_T_1216, 6, 6) @[Bitwise.scala 27:51] + node _T_1224 = bits(_T_1216, 7, 7) @[Bitwise.scala 27:51] + node _T_1225 = bits(_T_1217, 0, 0) @[Bitwise.scala 71:15] + node _T_1228 = mux(_T_1225, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1229 = bits(_T_1218, 0, 0) @[Bitwise.scala 71:15] + node _T_1232 = mux(_T_1229, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1233 = bits(_T_1219, 0, 0) @[Bitwise.scala 71:15] + node _T_1236 = mux(_T_1233, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1237 = bits(_T_1220, 0, 0) @[Bitwise.scala 71:15] + node _T_1240 = mux(_T_1237, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1241 = bits(_T_1221, 0, 0) @[Bitwise.scala 71:15] + node _T_1244 = mux(_T_1241, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1245 = bits(_T_1222, 0, 0) @[Bitwise.scala 71:15] + node _T_1248 = mux(_T_1245, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1249 = bits(_T_1223, 0, 0) @[Bitwise.scala 71:15] + node _T_1252 = mux(_T_1249, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1253 = bits(_T_1224, 0, 0) @[Bitwise.scala 71:15] + node _T_1256 = mux(_T_1253, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1257 = cat(_T_1232, _T_1228) @[Cat.scala 30:58] + node _T_1258 = cat(_T_1240, _T_1236) @[Cat.scala 30:58] + node _T_1259 = cat(_T_1258, _T_1257) @[Cat.scala 30:58] + node _T_1260 = cat(_T_1248, _T_1244) @[Cat.scala 30:58] + node _T_1261 = cat(_T_1256, _T_1252) @[Cat.scala 30:58] + node _T_1262 = cat(_T_1261, _T_1260) @[Cat.scala 30:58] + node _T_1263 = cat(_T_1262, _T_1259) @[Cat.scala 30:58] + node _T_1264 = bits(_T_598[0].bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_1265 = bits(_T_598[0].bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_1266 = bits(_T_598[0].bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_1267 = bits(_T_598[0].bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_1268 = bits(_T_598[0].bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_1269 = bits(_T_598[0].bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_1270 = bits(_T_598[0].bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_1271 = bits(_T_598[0].bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_1272 = bits(_T_1264, 0, 0) @[Bitwise.scala 71:15] + node _T_1275 = mux(_T_1272, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1276 = bits(_T_1265, 0, 0) @[Bitwise.scala 71:15] + node _T_1279 = mux(_T_1276, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1280 = bits(_T_1266, 0, 0) @[Bitwise.scala 71:15] + node _T_1283 = mux(_T_1280, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1284 = bits(_T_1267, 0, 0) @[Bitwise.scala 71:15] + node _T_1287 = mux(_T_1284, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1288 = bits(_T_1268, 0, 0) @[Bitwise.scala 71:15] + node _T_1291 = mux(_T_1288, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1292 = bits(_T_1269, 0, 0) @[Bitwise.scala 71:15] + node _T_1295 = mux(_T_1292, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1296 = bits(_T_1270, 0, 0) @[Bitwise.scala 71:15] + node _T_1299 = mux(_T_1296, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1300 = bits(_T_1271, 0, 0) @[Bitwise.scala 71:15] + node _T_1303 = mux(_T_1300, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_1304 = cat(_T_1279, _T_1275) @[Cat.scala 30:58] + node _T_1305 = cat(_T_1287, _T_1283) @[Cat.scala 30:58] + node _T_1306 = cat(_T_1305, _T_1304) @[Cat.scala 30:58] + node _T_1307 = cat(_T_1295, _T_1291) @[Cat.scala 30:58] + node _T_1308 = cat(_T_1303, _T_1299) @[Cat.scala 30:58] + node _T_1309 = cat(_T_1308, _T_1307) @[Cat.scala 30:58] + node _T_1310 = cat(_T_1309, _T_1306) @[Cat.scala 30:58] + node _T_1311 = and(_T_598[0].bits.data, _T_1310) @[AtomicAutomata.scala 133:28] + node _T_1312 = or(_T_1311, _T_1207) @[AtomicAutomata.scala 133:41] + node _T_1313 = and(_T_648[0].data, _T_1310) @[AtomicAutomata.scala 134:28] + node _T_1314 = or(_T_1313, _T_1263) @[AtomicAutomata.scala 134:41] + node _T_1315 = not(_T_1314) @[AtomicAutomata.scala 135:43] + node _T_1316 = mux(_T_1111, _T_1314, _T_1315) @[AtomicAutomata.scala 135:26] + node _T_1317 = add(_T_1312, _T_1316) @[AtomicAutomata.scala 136:33] + node _T_1318 = tail(_T_1317, 1) @[AtomicAutomata.scala 136:33] + node _T_1319 = bits(_T_1312, 63, 63) @[AtomicAutomata.scala 138:49] + node _T_1320 = eq(_T_1109, _T_1319) @[AtomicAutomata.scala 138:38] + node _T_1321 = bits(_T_1312, 63, 63) @[AtomicAutomata.scala 139:35] + node _T_1322 = bits(_T_1314, 63, 63) @[AtomicAutomata.scala 139:50] + node _T_1323 = eq(_T_1321, _T_1322) @[AtomicAutomata.scala 139:39] + node _T_1324 = bits(_T_1318, 63, 63) @[AtomicAutomata.scala 139:65] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[AtomicAutomata.scala 139:55] + node _T_1327 = mux(_T_1323, _T_1326, _T_1320) @[AtomicAutomata.scala 139:27] + node _T_1328 = eq(_T_1110, _T_1327) @[AtomicAutomata.scala 140:31] + node _T_1329 = mux(_T_1328, _T_598[0].bits.data, _T_648[0].data) @[AtomicAutomata.scala 141:50] + node _T_1330 = mux(_T_1111, _T_1318, _T_1329) @[AtomicAutomata.scala 141:28] + node _T_1331 = bits(_T_598[0].bits.opcode, 0, 0) @[AtomicAutomata.scala 147:34] + node _T_1332 = mux(_T_1331, _T_1108, _T_1330) @[AtomicAutomata.scala 147:14] + wire _T_1333 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[AtomicAutomata.scala 150:28] + _T_1333 is invalid @[AtomicAutomata.scala 150:28] + node _T_1355 = eq(_T_720, UInt<1>("h00")) @[AtomicAutomata.scala 151:23] + node _T_1356 = or(_T_702, _T_656) @[AtomicAutomata.scala 151:53] + node _T_1357 = and(_T_1355, _T_1356) @[AtomicAutomata.scala 151:35] + node _T_1358 = and(_T_1333.ready, _T_1357) @[AtomicAutomata.scala 152:38] + io.in.0.a.ready <= _T_1358 @[AtomicAutomata.scala 152:20] + node _T_1359 = and(io.in.0.a.valid, _T_1357) @[AtomicAutomata.scala 153:38] + _T_1333.valid <= _T_1359 @[AtomicAutomata.scala 153:24] + _T_1333.bits <- io.in.0.a.bits @[AtomicAutomata.scala 154:24] + node _T_1361 = eq(_T_702, UInt<1>("h00")) @[AtomicAutomata.scala 155:15] + when _T_1361 : @[AtomicAutomata.scala 155:31] + _T_1333.bits.opcode <= UInt<3>("h04") @[AtomicAutomata.scala 156:32] + _T_1333.bits.param <= UInt<1>("h00") @[AtomicAutomata.scala 157:32] + skip @[AtomicAutomata.scala 155:31] + wire _T_1364 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[AtomicAutomata.scala 161:28] + _T_1364 is invalid @[AtomicAutomata.scala 161:28] + _T_1364.valid <= _T_657 @[AtomicAutomata.scala 162:24] + node _T_1387 = leq(UInt<1>("h00"), _T_598[0].bits.size) @[Parameters.scala 63:32] + node _T_1389 = leq(_T_598[0].bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1390 = and(_T_1387, _T_1389) @[Parameters.scala 63:37] + node _T_1391 = or(UInt<1>("h00"), _T_1390) @[Parameters.scala 132:31] + node _T_1393 = xor(_T_598[0].bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + wire _T_1411 : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 356:17] + _T_1411 is invalid @[Edges.scala 356:17] + _T_1411.opcode <= UInt<1>("h00") @[Edges.scala 357:15] + _T_1411.param <= UInt<1>("h00") @[Edges.scala 358:15] + _T_1411.size <= _T_598[0].bits.size @[Edges.scala 359:15] + _T_1411.source <= _T_598[0].bits.source @[Edges.scala 360:15] + _T_1411.address <= _T_598[0].bits.address @[Edges.scala 361:15] + node _T_1422 = bits(_T_598[0].bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1423 = dshl(UInt<1>("h01"), _T_1422) @[OneHot.scala 49:12] + node _T_1424 = bits(_T_1423, 2, 0) @[OneHot.scala 49:37] + node _T_1426 = geq(_T_598[0].bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1428 = bits(_T_1424, 2, 2) @[package.scala 44:26] + node _T_1429 = bits(_T_598[0].bits.address, 2, 2) @[package.scala 45:26] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[package.scala 46:20] + node _T_1432 = and(UInt<1>("h01"), _T_1431) @[package.scala 49:27] + node _T_1433 = and(_T_1428, _T_1432) @[package.scala 50:38] + node _T_1434 = or(_T_1426, _T_1433) @[package.scala 50:29] + node _T_1435 = and(UInt<1>("h01"), _T_1429) @[package.scala 49:27] + node _T_1436 = and(_T_1428, _T_1435) @[package.scala 50:38] + node _T_1437 = or(_T_1426, _T_1436) @[package.scala 50:29] + node _T_1438 = bits(_T_1424, 1, 1) @[package.scala 44:26] + node _T_1439 = bits(_T_598[0].bits.address, 1, 1) @[package.scala 45:26] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[package.scala 46:20] + node _T_1442 = and(_T_1432, _T_1441) @[package.scala 49:27] + node _T_1443 = and(_T_1438, _T_1442) @[package.scala 50:38] + node _T_1444 = or(_T_1434, _T_1443) @[package.scala 50:29] + node _T_1445 = and(_T_1432, _T_1439) @[package.scala 49:27] + node _T_1446 = and(_T_1438, _T_1445) @[package.scala 50:38] + node _T_1447 = or(_T_1434, _T_1446) @[package.scala 50:29] + node _T_1448 = and(_T_1435, _T_1441) @[package.scala 49:27] + node _T_1449 = and(_T_1438, _T_1448) @[package.scala 50:38] + node _T_1450 = or(_T_1437, _T_1449) @[package.scala 50:29] + node _T_1451 = and(_T_1435, _T_1439) @[package.scala 49:27] + node _T_1452 = and(_T_1438, _T_1451) @[package.scala 50:38] + node _T_1453 = or(_T_1437, _T_1452) @[package.scala 50:29] + node _T_1454 = bits(_T_1424, 0, 0) @[package.scala 44:26] + node _T_1455 = bits(_T_598[0].bits.address, 0, 0) @[package.scala 45:26] + node _T_1457 = eq(_T_1455, UInt<1>("h00")) @[package.scala 46:20] + node _T_1458 = and(_T_1442, _T_1457) @[package.scala 49:27] + node _T_1459 = and(_T_1454, _T_1458) @[package.scala 50:38] + node _T_1460 = or(_T_1444, _T_1459) @[package.scala 50:29] + node _T_1461 = and(_T_1442, _T_1455) @[package.scala 49:27] + node _T_1462 = and(_T_1454, _T_1461) @[package.scala 50:38] + node _T_1463 = or(_T_1444, _T_1462) @[package.scala 50:29] + node _T_1464 = and(_T_1445, _T_1457) @[package.scala 49:27] + node _T_1465 = and(_T_1454, _T_1464) @[package.scala 50:38] + node _T_1466 = or(_T_1447, _T_1465) @[package.scala 50:29] + node _T_1467 = and(_T_1445, _T_1455) @[package.scala 49:27] + node _T_1468 = and(_T_1454, _T_1467) @[package.scala 50:38] + node _T_1469 = or(_T_1447, _T_1468) @[package.scala 50:29] + node _T_1470 = and(_T_1448, _T_1457) @[package.scala 49:27] + node _T_1471 = and(_T_1454, _T_1470) @[package.scala 50:38] + node _T_1472 = or(_T_1450, _T_1471) @[package.scala 50:29] + node _T_1473 = and(_T_1448, _T_1455) @[package.scala 49:27] + node _T_1474 = and(_T_1454, _T_1473) @[package.scala 50:38] + node _T_1475 = or(_T_1450, _T_1474) @[package.scala 50:29] + node _T_1476 = and(_T_1451, _T_1457) @[package.scala 49:27] + node _T_1477 = and(_T_1454, _T_1476) @[package.scala 50:38] + node _T_1478 = or(_T_1453, _T_1477) @[package.scala 50:29] + node _T_1479 = and(_T_1451, _T_1455) @[package.scala 49:27] + node _T_1480 = and(_T_1454, _T_1479) @[package.scala 50:38] + node _T_1481 = or(_T_1453, _T_1480) @[package.scala 50:29] + node _T_1482 = cat(_T_1463, _T_1460) @[Cat.scala 30:58] + node _T_1483 = cat(_T_1469, _T_1466) @[Cat.scala 30:58] + node _T_1484 = cat(_T_1483, _T_1482) @[Cat.scala 30:58] + node _T_1485 = cat(_T_1475, _T_1472) @[Cat.scala 30:58] + node _T_1486 = cat(_T_1481, _T_1478) @[Cat.scala 30:58] + node _T_1487 = cat(_T_1486, _T_1485) @[Cat.scala 30:58] + node _T_1488 = cat(_T_1487, _T_1484) @[Cat.scala 30:58] + _T_1411.mask <= _T_1488 @[Edges.scala 362:15] + _T_1411.data <= _T_1332 @[Edges.scala 363:15] + _T_1364.bits <- _T_1411 @[AtomicAutomata.scala 163:23] + node _T_1491 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1492 = dshl(_T_1491, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_1493 = bits(_T_1492, 5, 0) @[package.scala 19:76] + node _T_1494 = not(_T_1493) @[package.scala 19:40] + node _T_1495 = shr(_T_1494, 3) @[Edges.scala 198:59] + node _T_1496 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1498 = eq(_T_1496, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1500 = mux(_T_1498, _T_1495, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1502 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1504 = eq(_T_1502, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_1505 = and(_T_1504, io.out.0.a.ready) @[Arbiter.scala 35:24] + node _T_1508 = eq(_T_1364.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1509 = and(UInt<1>("h01"), _T_1508) @[Arbiter.scala 14:35] + node _T_1511 = eq(_T_1333.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1512 = and(_T_1509, _T_1511) @[Arbiter.scala 14:35] + wire _T_1515 : UInt<1>[2] @[Arbiter.scala 40:23] + _T_1515 is invalid @[Arbiter.scala 40:23] + _T_1515[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_1515[1] <= _T_1509 @[Arbiter.scala 40:23] + node _T_1520 = and(_T_1515[0], _T_1364.valid) @[Arbiter.scala 42:65] + node _T_1521 = and(_T_1515[1], _T_1333.valid) @[Arbiter.scala 42:65] + wire _T_1524 : UInt<1>[2] @[Arbiter.scala 42:23] + _T_1524 is invalid @[Arbiter.scala 42:23] + _T_1524[0] <= _T_1520 @[Arbiter.scala 42:23] + _T_1524[1] <= _T_1521 @[Arbiter.scala 42:23] + node _T_1530 = or(UInt<1>("h00"), _T_1524[0]) @[Arbiter.scala 47:52] + node _T_1531 = or(_T_1530, _T_1524[1]) @[Arbiter.scala 47:52] + node _T_1533 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1535 = eq(_T_1524[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1536 = or(_T_1533, _T_1535) @[Arbiter.scala 48:59] + node _T_1538 = eq(_T_1530, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1540 = eq(_T_1524[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1541 = or(_T_1538, _T_1540) @[Arbiter.scala 48:59] + node _T_1542 = and(_T_1536, _T_1541) @[Arbiter.scala 48:77] + node _T_1543 = or(_T_1542, reset) @[Arbiter.scala 48:13] + node _T_1545 = eq(_T_1543, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_1545 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_1546 = or(_T_1364.valid, _T_1333.valid) @[Arbiter.scala 50:31] + node _T_1548 = eq(_T_1546, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_1549 = or(_T_1524[0], _T_1524[1]) @[Arbiter.scala 50:54] + node _T_1550 = or(_T_1548, _T_1549) @[Arbiter.scala 50:36] + node _T_1551 = or(_T_1550, reset) @[Arbiter.scala 50:14] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_1553 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_1555 = mux(_T_1524[0], UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1557 = mux(_T_1524[1], _T_1500, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1558 = or(_T_1555, _T_1557) @[Arbiter.scala 54:44] + node _T_1559 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + node _T_1560 = sub(_T_1502, _T_1559) @[Arbiter.scala 55:52] + node _T_1561 = asUInt(_T_1560) @[Arbiter.scala 55:52] + node _T_1562 = tail(_T_1561, 1) @[Arbiter.scala 55:52] + node _T_1563 = mux(_T_1505, _T_1558, _T_1562) @[Arbiter.scala 55:23] + _T_1502 <= _T_1563 @[Arbiter.scala 55:17] + wire _T_1568 : UInt<1>[2] @[Arbiter.scala 58:49] + _T_1568 is invalid @[Arbiter.scala 58:49] + _T_1568[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1568[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_1573 : UInt<1>[2], clock with : (reset => (reset, _T_1568)) @[Reg.scala 26:44] + node _T_1581 = mux(_T_1504, _T_1524, _T_1573) @[Arbiter.scala 59:25] + _T_1573 <- _T_1581 @[Arbiter.scala 60:13] + node _T_1589 = mux(_T_1504, _T_1515, _T_1573) @[Arbiter.scala 63:26] + node _T_1597 = and(io.out.0.a.ready, _T_1589[0]) @[Arbiter.scala 65:33] + _T_1364.ready <= _T_1597 @[Arbiter.scala 65:19] + node _T_1598 = and(io.out.0.a.ready, _T_1589[1]) @[Arbiter.scala 65:33] + _T_1333.ready <= _T_1598 @[Arbiter.scala 65:19] + node _T_1599 = or(_T_1364.valid, _T_1333.valid) @[Arbiter.scala 71:46] + node _T_1601 = mux(_T_1573[0], _T_1364.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1603 = mux(_T_1573[1], _T_1333.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1605 = or(_T_1601, _T_1603) @[Mux.scala 19:72] + wire _T_1607 : UInt<1> @[Mux.scala 19:72] + _T_1607 is invalid @[Mux.scala 19:72] + _T_1607 <= _T_1605 @[Mux.scala 19:72] + node _T_1608 = mux(_T_1504, _T_1599, _T_1607) @[Arbiter.scala 71:24] + io.out.0.a.valid <= _T_1608 @[Arbiter.scala 71:18] + node _T_1609 = cat(_T_1364.bits.address, _T_1364.bits.mask) @[Mux.scala 19:72] + node _T_1610 = cat(_T_1609, _T_1364.bits.data) @[Mux.scala 19:72] + node _T_1611 = cat(_T_1364.bits.size, _T_1364.bits.source) @[Mux.scala 19:72] + node _T_1612 = cat(_T_1364.bits.opcode, _T_1364.bits.param) @[Mux.scala 19:72] + node _T_1613 = cat(_T_1612, _T_1611) @[Mux.scala 19:72] + node _T_1614 = cat(_T_1613, _T_1610) @[Mux.scala 19:72] + node _T_1616 = mux(_T_1581[0], _T_1614, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1617 = cat(_T_1333.bits.address, _T_1333.bits.mask) @[Mux.scala 19:72] + node _T_1618 = cat(_T_1617, _T_1333.bits.data) @[Mux.scala 19:72] + node _T_1619 = cat(_T_1333.bits.size, _T_1333.bits.source) @[Mux.scala 19:72] + node _T_1620 = cat(_T_1333.bits.opcode, _T_1333.bits.param) @[Mux.scala 19:72] + node _T_1621 = cat(_T_1620, _T_1619) @[Mux.scala 19:72] + node _T_1622 = cat(_T_1621, _T_1618) @[Mux.scala 19:72] + node _T_1624 = mux(_T_1581[1], _T_1622, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1633 = or(_T_1616, _T_1624) @[Mux.scala 19:72] + wire _T_1642 : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_1642 is invalid @[Mux.scala 19:72] + wire _T_1651 : UInt<112> + _T_1651 is invalid + _T_1651 <= _T_1633 + node _T_1652 = bits(_T_1651, 63, 0) @[Mux.scala 19:72] + _T_1642.data <= _T_1652 @[Mux.scala 19:72] + node _T_1653 = bits(_T_1651, 71, 64) @[Mux.scala 19:72] + _T_1642.mask <= _T_1653 @[Mux.scala 19:72] + node _T_1654 = bits(_T_1651, 99, 72) @[Mux.scala 19:72] + _T_1642.address <= _T_1654 @[Mux.scala 19:72] + node _T_1655 = bits(_T_1651, 102, 100) @[Mux.scala 19:72] + _T_1642.source <= _T_1655 @[Mux.scala 19:72] + node _T_1656 = bits(_T_1651, 105, 103) @[Mux.scala 19:72] + _T_1642.size <= _T_1656 @[Mux.scala 19:72] + node _T_1657 = bits(_T_1651, 108, 106) @[Mux.scala 19:72] + _T_1642.param <= _T_1657 @[Mux.scala 19:72] + node _T_1658 = bits(_T_1651, 111, 109) @[Mux.scala 19:72] + _T_1642.opcode <= _T_1658 @[Mux.scala 19:72] + io.out.0.a.bits <- _T_1642 @[Arbiter.scala 72:17] + node _T_1659 = and(_T_1333.ready, _T_1333.valid) @[Decoupled.scala 30:37] + node _T_1661 = eq(_T_702, UInt<1>("h00")) @[AtomicAutomata.scala 169:34] + node _T_1662 = and(_T_1659, _T_1661) @[AtomicAutomata.scala 169:31] + when _T_1662 : @[AtomicAutomata.scala 169:50] + when _T_725 : @[AtomicAutomata.scala 171:23] + _T_598[0].fifoId <= _T_718 @[AtomicAutomata.scala 172:24] + _T_598[0].bits <- io.in.0.a.bits @[AtomicAutomata.scala 173:24] + node _T_1663 = bits(io.in.0.a.bits.param, 1, 0) @[AtomicAutomata.scala 174:52] + node _T_1673 = eq(UInt<3>("h03"), _T_1663) @[Mux.scala 46:19] + node _T_1674 = mux(_T_1673, UInt<4>("h0c"), UInt<4>("h00")) @[Mux.scala 46:16] + node _T_1675 = eq(UInt<3>("h00"), _T_1663) @[Mux.scala 46:19] + node _T_1676 = mux(_T_1675, UInt<3>("h06"), _T_1674) @[Mux.scala 46:16] + node _T_1677 = eq(UInt<3>("h01"), _T_1663) @[Mux.scala 46:19] + node _T_1678 = mux(_T_1677, UInt<4>("h0e"), _T_1676) @[Mux.scala 46:16] + node _T_1679 = eq(UInt<3>("h02"), _T_1663) @[Mux.scala 46:19] + node _T_1680 = mux(_T_1679, UInt<4>("h08"), _T_1678) @[Mux.scala 46:16] + _T_598[0].lut <= _T_1680 @[AtomicAutomata.scala 174:24] + skip @[AtomicAutomata.scala 171:23] + when _T_725 : @[AtomicAutomata.scala 182:23] + _T_553[0].state <= UInt<2>("h03") @[AtomicAutomata.scala 183:23] + skip @[AtomicAutomata.scala 182:23] + skip @[AtomicAutomata.scala 169:50] + node _T_1681 = and(_T_1364.ready, _T_1364.valid) @[Decoupled.scala 30:37] + when _T_1681 : @[AtomicAutomata.scala 189:32] + when _T_707 : @[AtomicAutomata.scala 191:23] + _T_553[0].state <= UInt<1>("h01") @[AtomicAutomata.scala 192:23] + skip @[AtomicAutomata.scala 191:23] + skip @[AtomicAutomata.scala 189:32] + node _T_1682 = eq(_T_598[0].bits.source, io.in.0.d.bits.source) @[AtomicAutomata.scala 198:53] + node _T_1683 = and(_T_1682, _T_661) @[AtomicAutomata.scala 199:83] + node _T_1685 = mux(UInt<1>("h00"), _T_725, _T_1683) @[AtomicAutomata.scala 203:85] + node _T_1686 = or(UInt<1>("h00"), _T_1683) @[AtomicAutomata.scala 204:46] + node _T_1688 = eq(io.out.0.d.bits.opcode, UInt<1>("h01")) @[AtomicAutomata.scala 205:40] + node _T_1690 = eq(io.out.0.d.bits.opcode, UInt<1>("h00")) @[AtomicAutomata.scala 206:40] + node _T_1691 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_1691 : @[AtomicAutomata.scala 208:29] + node _T_1692 = and(_T_1685, _T_1688) @[AtomicAutomata.scala 210:22] + when _T_1692 : @[AtomicAutomata.scala 210:33] + _T_648[0].data <= io.out.0.d.bits.data @[AtomicAutomata.scala 211:22] + skip @[AtomicAutomata.scala 210:33] + when _T_1685 : @[AtomicAutomata.scala 215:23] + node _T_1693 = mux(_T_1688, UInt<2>("h02"), UInt<1>("h00")) @[AtomicAutomata.scala 217:29] + _T_553[0].state <= _T_1693 @[AtomicAutomata.scala 217:23] + skip @[AtomicAutomata.scala 215:23] + skip @[AtomicAutomata.scala 208:29] + node _T_1694 = and(_T_1688, _T_1686) @[AtomicAutomata.scala 222:29] + node _T_1695 = and(_T_1690, _T_1683) @[AtomicAutomata.scala 223:31] + node _T_1697 = eq(_T_1694, UInt<1>("h00")) @[AtomicAutomata.scala 225:38] + node _T_1698 = and(io.out.0.d.valid, _T_1697) @[AtomicAutomata.scala 225:35] + io.in.0.d.valid <= _T_1698 @[AtomicAutomata.scala 225:20] + node _T_1699 = or(io.in.0.d.ready, _T_1694) @[AtomicAutomata.scala 226:35] + io.out.0.d.ready <= _T_1699 @[AtomicAutomata.scala 226:21] + io.in.0.d.bits <- io.out.0.d.bits @[AtomicAutomata.scala 228:19] + when _T_1695 : @[AtomicAutomata.scala 229:26] + io.in.0.d.bits.opcode <= UInt<1>("h01") @[AtomicAutomata.scala 230:28] + io.in.0.d.bits.data <= _T_648[0].data @[AtomicAutomata.scala 231:26] + skip @[AtomicAutomata.scala 229:26] + io.in.0.b.valid <= UInt<1>("h00") @[AtomicAutomata.scala 256:20] + io.in.0.c.ready <= UInt<1>("h01") @[AtomicAutomata.scala 257:20] + io.in.0.e.ready <= UInt<1>("h01") @[AtomicAutomata.scala 258:20] + io.out.0.b.ready <= UInt<1>("h01") @[AtomicAutomata.scala 259:21] + io.out.0.c.valid <= UInt<1>("h00") @[AtomicAutomata.scala 260:21] + io.out.0.e.valid <= UInt<1>("h00") @[AtomicAutomata.scala 261:21] + + module TLMonitor_16 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 37:40] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 37:40] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_608 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + when _T_708 : @[CoreplexNetwork.scala 37:40] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_729 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_730 = cvt(_T_729) @[Parameters.scala 117:49] + node _T_732 = and(_T_730, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_733 = asSInt(_T_732) @[Parameters.scala 117:52] + node _T_735 = eq(_T_733, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_736 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_737 = or(_T_736, _T_735) @[Parameters.scala 133:42] + node _T_738 = and(_T_711, _T_737) @[Parameters.scala 132:56] + node _T_740 = or(UInt<1>("h00"), _T_738) @[Parameters.scala 134:30] + node _T_741 = or(_T_740, reset) @[CoreplexNetwork.scala 37:40] + node _T_743 = eq(_T_741, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_743 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_744 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_746 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_748 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_749 = or(_T_748, reset) @[CoreplexNetwork.scala 37:40] + node _T_751 = eq(_T_749, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_751 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_752 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_754 = eq(_T_752, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_754 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_756 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_757 = or(_T_756, reset) @[CoreplexNetwork.scala 37:40] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_759 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_760 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 37:40] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_763 = or(_T_762, reset) @[CoreplexNetwork.scala 37:40] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_765 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_767 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 37:40] + when _T_767 : @[CoreplexNetwork.scala 37:40] + node _T_770 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_772 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_773 = and(_T_770, _T_772) @[Parameters.scala 63:37] + node _T_774 = or(UInt<1>("h00"), _T_773) @[Parameters.scala 132:31] + node _T_776 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_777 = cvt(_T_776) @[Parameters.scala 117:49] + node _T_779 = and(_T_777, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_780 = asSInt(_T_779) @[Parameters.scala 117:52] + node _T_782 = eq(_T_780, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_784 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_785 = cvt(_T_784) @[Parameters.scala 117:49] + node _T_787 = and(_T_785, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_788 = asSInt(_T_787) @[Parameters.scala 117:52] + node _T_790 = eq(_T_788, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_792 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = or(_T_782, _T_790) @[Parameters.scala 133:42] + node _T_800 = or(_T_799, _T_798) @[Parameters.scala 133:42] + node _T_801 = and(_T_774, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[CoreplexNetwork.scala 37:40] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_806 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_807 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_809 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_810 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_812 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_815 = or(_T_814, reset) @[CoreplexNetwork.scala 37:40] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_817 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_818 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 37:40] + node _T_819 = or(_T_818, reset) @[CoreplexNetwork.scala 37:40] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_821 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_823 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_823 : @[CoreplexNetwork.scala 37:40] + node _T_826 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_828 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_829 = and(_T_826, _T_828) @[Parameters.scala 63:37] + node _T_830 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 132:31] + node _T_832 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_833 = cvt(_T_832) @[Parameters.scala 117:49] + node _T_835 = and(_T_833, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_836 = asSInt(_T_835) @[Parameters.scala 117:52] + node _T_838 = eq(_T_836, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_840 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_841 = cvt(_T_840) @[Parameters.scala 117:49] + node _T_843 = and(_T_841, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_844 = asSInt(_T_843) @[Parameters.scala 117:52] + node _T_846 = eq(_T_844, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_848 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_849 = cvt(_T_848) @[Parameters.scala 117:49] + node _T_851 = and(_T_849, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_852 = asSInt(_T_851) @[Parameters.scala 117:52] + node _T_854 = eq(_T_852, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_855 = or(_T_838, _T_846) @[Parameters.scala 133:42] + node _T_856 = or(_T_855, _T_854) @[Parameters.scala 133:42] + node _T_857 = and(_T_830, _T_856) @[Parameters.scala 132:56] + node _T_859 = or(UInt<1>("h00"), _T_857) @[Parameters.scala 134:30] + node _T_860 = or(_T_859, reset) @[CoreplexNetwork.scala 37:40] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_862 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_863 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_865 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_866 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_868 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_870 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_871 = or(_T_870, reset) @[CoreplexNetwork.scala 37:40] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_873 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_874 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 37:40] + node _T_875 = or(_T_874, reset) @[CoreplexNetwork.scala 37:40] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_877 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_879 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 37:40] + when _T_879 : @[CoreplexNetwork.scala 37:40] + node _T_882 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_884 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_885 = and(_T_882, _T_884) @[Parameters.scala 63:37] + node _T_886 = or(UInt<1>("h00"), _T_885) @[Parameters.scala 132:31] + node _T_888 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_889 = cvt(_T_888) @[Parameters.scala 117:49] + node _T_891 = and(_T_889, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_892 = asSInt(_T_891) @[Parameters.scala 117:52] + node _T_894 = eq(_T_892, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_897 = cvt(_T_896) @[Parameters.scala 117:49] + node _T_899 = and(_T_897, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_900 = asSInt(_T_899) @[Parameters.scala 117:52] + node _T_902 = eq(_T_900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_905 = cvt(_T_904) @[Parameters.scala 117:49] + node _T_907 = and(_T_905, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_908 = asSInt(_T_907) @[Parameters.scala 117:52] + node _T_910 = eq(_T_908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_911 = or(_T_894, _T_902) @[Parameters.scala 133:42] + node _T_912 = or(_T_911, _T_910) @[Parameters.scala 133:42] + node _T_913 = and(_T_886, _T_912) @[Parameters.scala 132:56] + node _T_915 = or(UInt<1>("h00"), _T_913) @[Parameters.scala 134:30] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 37:40] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_918 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_919 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_921 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_922 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_924 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_926 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_927 = or(_T_926, reset) @[CoreplexNetwork.scala 37:40] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_929 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_930 = not(_T_706) @[CoreplexNetwork.scala 37:40] + node _T_931 = and(io.in[0].a.bits.mask, _T_930) @[CoreplexNetwork.scala 37:40] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_934 = or(_T_933, reset) @[CoreplexNetwork.scala 37:40] + node _T_936 = eq(_T_934, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_936 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_938 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 37:40] + when _T_938 : @[CoreplexNetwork.scala 37:40] + node _T_941 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_943 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_944 = and(_T_941, _T_943) @[Parameters.scala 63:37] + node _T_945 = or(UInt<1>("h00"), _T_944) @[Parameters.scala 132:31] + node _T_947 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_948 = cvt(_T_947) @[Parameters.scala 117:49] + node _T_950 = and(_T_948, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_951 = asSInt(_T_950) @[Parameters.scala 117:52] + node _T_953 = eq(_T_951, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_955 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_956 = cvt(_T_955) @[Parameters.scala 117:49] + node _T_958 = and(_T_956, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_959 = asSInt(_T_958) @[Parameters.scala 117:52] + node _T_961 = eq(_T_959, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_963 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_964 = cvt(_T_963) @[Parameters.scala 117:49] + node _T_966 = and(_T_964, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_967 = asSInt(_T_966) @[Parameters.scala 117:52] + node _T_969 = eq(_T_967, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_970 = or(_T_953, _T_961) @[Parameters.scala 133:42] + node _T_971 = or(_T_970, _T_969) @[Parameters.scala 133:42] + node _T_972 = and(_T_945, _T_971) @[Parameters.scala 132:56] + node _T_974 = or(UInt<1>("h00"), _T_972) @[Parameters.scala 134:30] + node _T_975 = or(_T_974, reset) @[CoreplexNetwork.scala 37:40] + node _T_977 = eq(_T_975, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_977 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_978 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_980 = eq(_T_978, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_980 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_981 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_983 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_985 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_986 = or(_T_985, reset) @[CoreplexNetwork.scala 37:40] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_988 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_989 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 37:40] + node _T_990 = or(_T_989, reset) @[CoreplexNetwork.scala 37:40] + node _T_992 = eq(_T_990, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_992 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_994 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + when _T_994 : @[CoreplexNetwork.scala 37:40] + node _T_997 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_999 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1000 = and(_T_997, _T_999) @[Parameters.scala 63:37] + node _T_1001 = or(UInt<1>("h00"), _T_1000) @[Parameters.scala 132:31] + node _T_1003 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1012 = cvt(_T_1011) @[Parameters.scala 117:49] + node _T_1014 = and(_T_1012, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1015 = asSInt(_T_1014) @[Parameters.scala 117:52] + node _T_1017 = eq(_T_1015, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1019 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1020 = cvt(_T_1019) @[Parameters.scala 117:49] + node _T_1022 = and(_T_1020, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1023 = asSInt(_T_1022) @[Parameters.scala 117:52] + node _T_1025 = eq(_T_1023, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1026 = or(_T_1009, _T_1017) @[Parameters.scala 133:42] + node _T_1027 = or(_T_1026, _T_1025) @[Parameters.scala 133:42] + node _T_1028 = and(_T_1001, _T_1027) @[Parameters.scala 132:56] + node _T_1030 = or(UInt<1>("h00"), _T_1028) @[Parameters.scala 134:30] + node _T_1031 = or(_T_1030, reset) @[CoreplexNetwork.scala 37:40] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1033 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1034 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1036 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1037 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_1039 = eq(_T_1037, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1039 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1041 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1042 = or(_T_1041, reset) @[CoreplexNetwork.scala 37:40] + node _T_1044 = eq(_T_1042, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1044 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1045 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 37:40] + node _T_1046 = or(_T_1045, reset) @[CoreplexNetwork.scala 37:40] + node _T_1048 = eq(_T_1046, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1048 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1050 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 37:40] + when _T_1050 : @[CoreplexNetwork.scala 37:40] + node _T_1053 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1055 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1063 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1064 = cvt(_T_1063) @[Parameters.scala 117:49] + node _T_1066 = and(_T_1064, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1067 = asSInt(_T_1066) @[Parameters.scala 117:52] + node _T_1069 = eq(_T_1067, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1071 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1072 = cvt(_T_1071) @[Parameters.scala 117:49] + node _T_1074 = and(_T_1072, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1075 = asSInt(_T_1074) @[Parameters.scala 117:52] + node _T_1077 = eq(_T_1075, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1078 = or(_T_1061, _T_1069) @[Parameters.scala 133:42] + node _T_1079 = or(_T_1078, _T_1077) @[Parameters.scala 133:42] + node _T_1080 = and(_T_1053, _T_1079) @[Parameters.scala 132:56] + node _T_1082 = or(UInt<1>("h00"), _T_1080) @[Parameters.scala 134:30] + node _T_1083 = or(_T_1082, reset) @[CoreplexNetwork.scala 37:40] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1085 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1086 = or(_T_630, reset) @[CoreplexNetwork.scala 37:40] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1088 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1089 = or(_T_638, reset) @[CoreplexNetwork.scala 37:40] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1091 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1092 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 37:40] + node _T_1093 = or(_T_1092, reset) @[CoreplexNetwork.scala 37:40] + node _T_1095 = eq(_T_1093, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1095 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + when io.in[0].b.valid : @[CoreplexNetwork.scala 37:40] + node _T_1097 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1098 = or(_T_1097, reset) @[CoreplexNetwork.scala 37:40] + node _T_1100 = eq(_T_1098, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1100 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1102 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1103 = cvt(_T_1102) @[Parameters.scala 117:49] + node _T_1105 = and(_T_1103, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1106 = asSInt(_T_1105) @[Parameters.scala 117:52] + node _T_1108 = eq(_T_1106, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1110 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1111 = cvt(_T_1110) @[Parameters.scala 117:49] + node _T_1113 = and(_T_1111, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1114 = asSInt(_T_1113) @[Parameters.scala 117:52] + node _T_1116 = eq(_T_1114, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1118 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1119 = cvt(_T_1118) @[Parameters.scala 117:49] + node _T_1121 = and(_T_1119, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1122 = asSInt(_T_1121) @[Parameters.scala 117:52] + node _T_1124 = eq(_T_1122, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1127 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1127 is invalid @[Parameters.scala 110:36] + _T_1127[0] <= _T_1108 @[Parameters.scala 110:36] + _T_1127[1] <= _T_1116 @[Parameters.scala 110:36] + _T_1127[2] <= _T_1124 @[Parameters.scala 110:36] + node _T_1133 = or(_T_1127[0], _T_1127[1]) @[Parameters.scala 119:64] + node _T_1134 = or(_T_1133, _T_1127[2]) @[Parameters.scala 119:64] + node _T_1136 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1137 = dshl(_T_1136, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1138 = bits(_T_1137, 5, 0) @[package.scala 19:76] + node _T_1139 = not(_T_1138) @[package.scala 19:40] + node _T_1140 = and(io.in[0].b.bits.address, _T_1139) @[Edges.scala 17:16] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1144 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1145 = dshl(UInt<1>("h01"), _T_1144) @[OneHot.scala 49:12] + node _T_1146 = bits(_T_1145, 2, 0) @[OneHot.scala 49:37] + node _T_1148 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1150 = bits(_T_1146, 2, 2) @[package.scala 44:26] + node _T_1151 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[package.scala 46:20] + node _T_1154 = and(UInt<1>("h01"), _T_1153) @[package.scala 49:27] + node _T_1155 = and(_T_1150, _T_1154) @[package.scala 50:38] + node _T_1156 = or(_T_1148, _T_1155) @[package.scala 50:29] + node _T_1157 = and(UInt<1>("h01"), _T_1151) @[package.scala 49:27] + node _T_1158 = and(_T_1150, _T_1157) @[package.scala 50:38] + node _T_1159 = or(_T_1148, _T_1158) @[package.scala 50:29] + node _T_1160 = bits(_T_1146, 1, 1) @[package.scala 44:26] + node _T_1161 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[package.scala 46:20] + node _T_1164 = and(_T_1154, _T_1163) @[package.scala 49:27] + node _T_1165 = and(_T_1160, _T_1164) @[package.scala 50:38] + node _T_1166 = or(_T_1156, _T_1165) @[package.scala 50:29] + node _T_1167 = and(_T_1154, _T_1161) @[package.scala 49:27] + node _T_1168 = and(_T_1160, _T_1167) @[package.scala 50:38] + node _T_1169 = or(_T_1156, _T_1168) @[package.scala 50:29] + node _T_1170 = and(_T_1157, _T_1163) @[package.scala 49:27] + node _T_1171 = and(_T_1160, _T_1170) @[package.scala 50:38] + node _T_1172 = or(_T_1159, _T_1171) @[package.scala 50:29] + node _T_1173 = and(_T_1157, _T_1161) @[package.scala 49:27] + node _T_1174 = and(_T_1160, _T_1173) @[package.scala 50:38] + node _T_1175 = or(_T_1159, _T_1174) @[package.scala 50:29] + node _T_1176 = bits(_T_1146, 0, 0) @[package.scala 44:26] + node _T_1177 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[package.scala 46:20] + node _T_1180 = and(_T_1164, _T_1179) @[package.scala 49:27] + node _T_1181 = and(_T_1176, _T_1180) @[package.scala 50:38] + node _T_1182 = or(_T_1166, _T_1181) @[package.scala 50:29] + node _T_1183 = and(_T_1164, _T_1177) @[package.scala 49:27] + node _T_1184 = and(_T_1176, _T_1183) @[package.scala 50:38] + node _T_1185 = or(_T_1166, _T_1184) @[package.scala 50:29] + node _T_1186 = and(_T_1167, _T_1179) @[package.scala 49:27] + node _T_1187 = and(_T_1176, _T_1186) @[package.scala 50:38] + node _T_1188 = or(_T_1169, _T_1187) @[package.scala 50:29] + node _T_1189 = and(_T_1167, _T_1177) @[package.scala 49:27] + node _T_1190 = and(_T_1176, _T_1189) @[package.scala 50:38] + node _T_1191 = or(_T_1169, _T_1190) @[package.scala 50:29] + node _T_1192 = and(_T_1170, _T_1179) @[package.scala 49:27] + node _T_1193 = and(_T_1176, _T_1192) @[package.scala 50:38] + node _T_1194 = or(_T_1172, _T_1193) @[package.scala 50:29] + node _T_1195 = and(_T_1170, _T_1177) @[package.scala 49:27] + node _T_1196 = and(_T_1176, _T_1195) @[package.scala 50:38] + node _T_1197 = or(_T_1172, _T_1196) @[package.scala 50:29] + node _T_1198 = and(_T_1173, _T_1179) @[package.scala 49:27] + node _T_1199 = and(_T_1176, _T_1198) @[package.scala 50:38] + node _T_1200 = or(_T_1175, _T_1199) @[package.scala 50:29] + node _T_1201 = and(_T_1173, _T_1177) @[package.scala 49:27] + node _T_1202 = and(_T_1176, _T_1201) @[package.scala 50:38] + node _T_1203 = or(_T_1175, _T_1202) @[package.scala 50:29] + node _T_1204 = cat(_T_1185, _T_1182) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1191, _T_1188) @[Cat.scala 30:58] + node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 30:58] + node _T_1207 = cat(_T_1197, _T_1194) @[Cat.scala 30:58] + node _T_1208 = cat(_T_1203, _T_1200) @[Cat.scala 30:58] + node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 30:58] + node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 30:58] + node _T_1212 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + when _T_1212 : @[CoreplexNetwork.scala 37:40] + node _T_1214 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1215 = not(_T_1214) @[Parameters.scala 37:9] + node _T_1217 = or(_T_1215, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1218 = not(_T_1217) @[Parameters.scala 37:7] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1222 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1224 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1227 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1227 is invalid @[Parameters.scala 228:27] + _T_1227[0] <= _T_1220 @[Parameters.scala 228:27] + _T_1227[1] <= _T_1222 @[Parameters.scala 228:27] + _T_1227[2] <= _T_1224 @[Parameters.scala 228:27] + node _T_1235 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1237 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1238 = and(_T_1235, _T_1237) @[Parameters.scala 63:37] + node _T_1241 = mux(_T_1227[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1243 = mux(_T_1227[1], _T_1238, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1245 = mux(_T_1227[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1247 = or(_T_1241, _T_1243) @[Mux.scala 19:72] + node _T_1248 = or(_T_1247, _T_1245) @[Mux.scala 19:72] + wire _T_1250 : UInt<1> @[Mux.scala 19:72] + _T_1250 is invalid @[Mux.scala 19:72] + _T_1250 <= _T_1248 @[Mux.scala 19:72] + node _T_1251 = or(_T_1250, reset) @[CoreplexNetwork.scala 37:40] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1253 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1254 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1256 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1258 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1259 = or(_T_1258, reset) @[CoreplexNetwork.scala 37:40] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1261 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1262 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1264 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1266 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1267 = or(_T_1266, reset) @[CoreplexNetwork.scala 37:40] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1269 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1270 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 37:40] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1273 = or(_T_1272, reset) @[CoreplexNetwork.scala 37:40] + node _T_1275 = eq(_T_1273, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1275 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1277 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 37:40] + when _T_1277 : @[CoreplexNetwork.scala 37:40] + node _T_1279 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1281 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1282 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1284 = eq(_T_1282, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1284 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1285 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1287 = eq(_T_1285, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1287 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1289 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1290 = or(_T_1289, reset) @[CoreplexNetwork.scala 37:40] + node _T_1292 = eq(_T_1290, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1292 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1293 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1294 = or(_T_1293, reset) @[CoreplexNetwork.scala 37:40] + node _T_1296 = eq(_T_1294, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1296 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1298 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1298 : @[CoreplexNetwork.scala 37:40] + node _T_1300 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1302 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1303 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1305 = eq(_T_1303, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1305 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1306 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1308 = eq(_T_1306, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1308 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1310 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1311 = or(_T_1310, reset) @[CoreplexNetwork.scala 37:40] + node _T_1313 = eq(_T_1311, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1313 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1314 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1315 = or(_T_1314, reset) @[CoreplexNetwork.scala 37:40] + node _T_1317 = eq(_T_1315, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1317 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1319 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 37:40] + when _T_1319 : @[CoreplexNetwork.scala 37:40] + node _T_1321 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1323 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1324 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1326 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1327 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1329 = eq(_T_1327, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1329 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1331 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1332 = or(_T_1331, reset) @[CoreplexNetwork.scala 37:40] + node _T_1334 = eq(_T_1332, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1334 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1335 = not(_T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1336 = and(io.in[0].b.bits.mask, _T_1335) @[CoreplexNetwork.scala 37:40] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1339 = or(_T_1338, reset) @[CoreplexNetwork.scala 37:40] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1341 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1343 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 37:40] + when _T_1343 : @[CoreplexNetwork.scala 37:40] + node _T_1345 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1347 = eq(_T_1345, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1347 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1348 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1350 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1351 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1353 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1355 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1356 = or(_T_1355, reset) @[CoreplexNetwork.scala 37:40] + node _T_1358 = eq(_T_1356, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1358 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1359 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1360 = or(_T_1359, reset) @[CoreplexNetwork.scala 37:40] + node _T_1362 = eq(_T_1360, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1362 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1364 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + when _T_1364 : @[CoreplexNetwork.scala 37:40] + node _T_1366 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1368 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1369 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1371 = eq(_T_1369, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1371 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1372 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1374 = eq(_T_1372, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1374 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1376 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1377 = or(_T_1376, reset) @[CoreplexNetwork.scala 37:40] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1379 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1380 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1381 = or(_T_1380, reset) @[CoreplexNetwork.scala 37:40] + node _T_1383 = eq(_T_1381, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1383 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1385 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 37:40] + when _T_1385 : @[CoreplexNetwork.scala 37:40] + node _T_1387 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 37:40] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1389 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1390 = or(_T_1134, reset) @[CoreplexNetwork.scala 37:40] + node _T_1392 = eq(_T_1390, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1392 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1393 = or(_T_1142, reset) @[CoreplexNetwork.scala 37:40] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1395 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1396 = eq(io.in[0].b.bits.mask, _T_1210) @[CoreplexNetwork.scala 37:40] + node _T_1397 = or(_T_1396, reset) @[CoreplexNetwork.scala 37:40] + node _T_1399 = eq(_T_1397, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1399 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + when io.in[0].c.valid : @[CoreplexNetwork.scala 37:40] + node _T_1401 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1402 = or(_T_1401, reset) @[CoreplexNetwork.scala 37:40] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1404 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1406 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1407 = not(_T_1406) @[Parameters.scala 37:9] + node _T_1409 = or(_T_1407, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1410 = not(_T_1409) @[Parameters.scala 37:7] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1414 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1416 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1419 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1419 is invalid @[Parameters.scala 228:27] + _T_1419[0] <= _T_1412 @[Parameters.scala 228:27] + _T_1419[1] <= _T_1414 @[Parameters.scala 228:27] + _T_1419[2] <= _T_1416 @[Parameters.scala 228:27] + node _T_1425 = or(_T_1419[0], _T_1419[1]) @[Parameters.scala 229:46] + node _T_1426 = or(_T_1425, _T_1419[2]) @[Parameters.scala 229:46] + node _T_1428 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1429 = dshl(_T_1428, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1430 = bits(_T_1429, 5, 0) @[package.scala 19:76] + node _T_1431 = not(_T_1430) @[package.scala 19:40] + node _T_1432 = and(io.in[0].c.bits.address, _T_1431) @[Edges.scala 17:16] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1436 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1437 = cvt(_T_1436) @[Parameters.scala 117:49] + node _T_1439 = and(_T_1437, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1440 = asSInt(_T_1439) @[Parameters.scala 117:52] + node _T_1442 = eq(_T_1440, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1444 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1445 = cvt(_T_1444) @[Parameters.scala 117:49] + node _T_1447 = and(_T_1445, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1448 = asSInt(_T_1447) @[Parameters.scala 117:52] + node _T_1450 = eq(_T_1448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1452 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1453 = cvt(_T_1452) @[Parameters.scala 117:49] + node _T_1455 = and(_T_1453, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1456 = asSInt(_T_1455) @[Parameters.scala 117:52] + node _T_1458 = eq(_T_1456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1461 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1461 is invalid @[Parameters.scala 110:36] + _T_1461[0] <= _T_1442 @[Parameters.scala 110:36] + _T_1461[1] <= _T_1450 @[Parameters.scala 110:36] + _T_1461[2] <= _T_1458 @[Parameters.scala 110:36] + node _T_1467 = or(_T_1461[0], _T_1461[1]) @[Parameters.scala 119:64] + node _T_1468 = or(_T_1467, _T_1461[2]) @[Parameters.scala 119:64] + node _T_1470 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 37:40] + when _T_1470 : @[CoreplexNetwork.scala 37:40] + node _T_1471 = or(_T_1468, reset) @[CoreplexNetwork.scala 37:40] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1473 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1474 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1476 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1478 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 37:40] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1481 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1482 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1484 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1486 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1487 = or(_T_1486, reset) @[CoreplexNetwork.scala 37:40] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1489 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1491 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1492 = or(_T_1491, reset) @[CoreplexNetwork.scala 37:40] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1494 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 37:40] + when _T_1496 : @[CoreplexNetwork.scala 37:40] + node _T_1497 = or(_T_1468, reset) @[CoreplexNetwork.scala 37:40] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1499 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1500 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1502 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1504 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1505 = or(_T_1504, reset) @[CoreplexNetwork.scala 37:40] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1507 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1508 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1510 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1512 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1513 = or(_T_1512, reset) @[CoreplexNetwork.scala 37:40] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1515 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1517 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1518 = or(_T_1517, reset) @[CoreplexNetwork.scala 37:40] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1520 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1522 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + when _T_1522 : @[CoreplexNetwork.scala 37:40] + node _T_1525 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1527 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1528 = cvt(_T_1527) @[Parameters.scala 117:49] + node _T_1530 = and(_T_1528, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1531 = asSInt(_T_1530) @[Parameters.scala 117:52] + node _T_1533 = eq(_T_1531, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1535 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1536 = cvt(_T_1535) @[Parameters.scala 117:49] + node _T_1538 = and(_T_1536, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1539 = asSInt(_T_1538) @[Parameters.scala 117:52] + node _T_1541 = eq(_T_1539, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1543 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1544 = cvt(_T_1543) @[Parameters.scala 117:49] + node _T_1546 = and(_T_1544, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1547 = asSInt(_T_1546) @[Parameters.scala 117:52] + node _T_1549 = eq(_T_1547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1550 = or(_T_1533, _T_1541) @[Parameters.scala 133:42] + node _T_1551 = or(_T_1550, _T_1549) @[Parameters.scala 133:42] + node _T_1552 = and(_T_1525, _T_1551) @[Parameters.scala 132:56] + node _T_1554 = or(UInt<1>("h00"), _T_1552) @[Parameters.scala 134:30] + node _T_1555 = or(_T_1554, reset) @[CoreplexNetwork.scala 37:40] + node _T_1557 = eq(_T_1555, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1557 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1558 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1560 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1562 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1563 = or(_T_1562, reset) @[CoreplexNetwork.scala 37:40] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1565 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1566 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1568 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1570 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1571 = or(_T_1570, reset) @[CoreplexNetwork.scala 37:40] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1573 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1575 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1576 = or(_T_1575, reset) @[CoreplexNetwork.scala 37:40] + node _T_1578 = eq(_T_1576, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1578 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1580 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 37:40] + when _T_1580 : @[CoreplexNetwork.scala 37:40] + node _T_1583 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1585 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1586 = cvt(_T_1585) @[Parameters.scala 117:49] + node _T_1588 = and(_T_1586, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1589 = asSInt(_T_1588) @[Parameters.scala 117:52] + node _T_1591 = eq(_T_1589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1593 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1594 = cvt(_T_1593) @[Parameters.scala 117:49] + node _T_1596 = and(_T_1594, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1597 = asSInt(_T_1596) @[Parameters.scala 117:52] + node _T_1599 = eq(_T_1597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1601 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1602 = cvt(_T_1601) @[Parameters.scala 117:49] + node _T_1604 = and(_T_1602, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1605 = asSInt(_T_1604) @[Parameters.scala 117:52] + node _T_1607 = eq(_T_1605, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1608 = or(_T_1591, _T_1599) @[Parameters.scala 133:42] + node _T_1609 = or(_T_1608, _T_1607) @[Parameters.scala 133:42] + node _T_1610 = and(_T_1583, _T_1609) @[Parameters.scala 132:56] + node _T_1612 = or(UInt<1>("h00"), _T_1610) @[Parameters.scala 134:30] + node _T_1613 = or(_T_1612, reset) @[CoreplexNetwork.scala 37:40] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1615 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1616 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1618 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1620 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1621 = or(_T_1620, reset) @[CoreplexNetwork.scala 37:40] + node _T_1623 = eq(_T_1621, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1623 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1624 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1626 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1628 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1629 = or(_T_1628, reset) @[CoreplexNetwork.scala 37:40] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1631 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1633 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1634 = or(_T_1633, reset) @[CoreplexNetwork.scala 37:40] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1636 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1638 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1638 : @[CoreplexNetwork.scala 37:40] + node _T_1639 = or(_T_1468, reset) @[CoreplexNetwork.scala 37:40] + node _T_1641 = eq(_T_1639, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1641 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1642 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1644 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1645 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1647 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1649 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1650 = or(_T_1649, reset) @[CoreplexNetwork.scala 37:40] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1652 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1654 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 37:40] + when _T_1654 : @[CoreplexNetwork.scala 37:40] + node _T_1655 = or(_T_1468, reset) @[CoreplexNetwork.scala 37:40] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1657 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1658 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1660 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1661 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1663 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1665 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1666 = or(_T_1665, reset) @[CoreplexNetwork.scala 37:40] + node _T_1668 = eq(_T_1666, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1668 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1670 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 37:40] + when _T_1670 : @[CoreplexNetwork.scala 37:40] + node _T_1671 = or(_T_1468, reset) @[CoreplexNetwork.scala 37:40] + node _T_1673 = eq(_T_1671, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1673 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1674 = or(_T_1426, reset) @[CoreplexNetwork.scala 37:40] + node _T_1676 = eq(_T_1674, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1676 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1677 = or(_T_1434, reset) @[CoreplexNetwork.scala 37:40] + node _T_1679 = eq(_T_1677, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1679 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1681 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1682 = or(_T_1681, reset) @[CoreplexNetwork.scala 37:40] + node _T_1684 = eq(_T_1682, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1684 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1686 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1687 = or(_T_1686, reset) @[CoreplexNetwork.scala 37:40] + node _T_1689 = eq(_T_1687, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1689 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + when io.in[0].d.valid : @[CoreplexNetwork.scala 37:40] + node _T_1691 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1692 = or(_T_1691, reset) @[CoreplexNetwork.scala 37:40] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1694 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1696 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1697 = not(_T_1696) @[Parameters.scala 37:9] + node _T_1699 = or(_T_1697, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1700 = not(_T_1699) @[Parameters.scala 37:7] + node _T_1702 = eq(_T_1700, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1704 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1706 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1709 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1709 is invalid @[Parameters.scala 228:27] + _T_1709[0] <= _T_1702 @[Parameters.scala 228:27] + _T_1709[1] <= _T_1704 @[Parameters.scala 228:27] + _T_1709[2] <= _T_1706 @[Parameters.scala 228:27] + node _T_1715 = or(_T_1709[0], _T_1709[1]) @[Parameters.scala 229:46] + node _T_1716 = or(_T_1715, _T_1709[2]) @[Parameters.scala 229:46] + node _T_1718 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1719 = dshl(_T_1718, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1720 = bits(_T_1719, 5, 0) @[package.scala 19:76] + node _T_1721 = not(_T_1720) @[package.scala 19:40] + node _T_1722 = and(io.in[0].d.bits.addr_lo, _T_1721) @[Edges.scala 17:16] + node _T_1724 = eq(_T_1722, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1726 = lt(io.in[0].d.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1728 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + when _T_1728 : @[CoreplexNetwork.scala 37:40] + node _T_1729 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1731 = eq(_T_1729, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1731 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1732 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1734 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1735 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1737 = eq(_T_1735, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1737 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1739 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1740 = or(_T_1739, reset) @[CoreplexNetwork.scala 37:40] + node _T_1742 = eq(_T_1740, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1742 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1744 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1745 = or(_T_1744, reset) @[CoreplexNetwork.scala 37:40] + node _T_1747 = eq(_T_1745, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1747 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1749 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1750 = or(_T_1749, reset) @[CoreplexNetwork.scala 37:40] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1752 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1754 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 37:40] + when _T_1754 : @[CoreplexNetwork.scala 37:40] + node _T_1755 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1757 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1758 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1760 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1761 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1763 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1765 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1766 = or(_T_1765, reset) @[CoreplexNetwork.scala 37:40] + node _T_1768 = eq(_T_1766, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1768 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1770 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1771 = or(_T_1770, reset) @[CoreplexNetwork.scala 37:40] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1773 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1775 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 37:40] + when _T_1775 : @[CoreplexNetwork.scala 37:40] + node _T_1776 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1778 = eq(_T_1776, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1778 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1779 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1781 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1782 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1784 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1786 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1787 = or(_T_1786, reset) @[CoreplexNetwork.scala 37:40] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1789 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1791 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1792 = or(_T_1791, reset) @[CoreplexNetwork.scala 37:40] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1794 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1796 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1796 : @[CoreplexNetwork.scala 37:40] + node _T_1797 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1799 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1800 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1802 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1803 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1805 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1807 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1808 = or(_T_1807, reset) @[CoreplexNetwork.scala 37:40] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1810 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1812 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 37:40] + when _T_1812 : @[CoreplexNetwork.scala 37:40] + node _T_1813 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1815 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1816 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1818 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1819 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1821 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1823 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1824 = or(_T_1823, reset) @[CoreplexNetwork.scala 37:40] + node _T_1826 = eq(_T_1824, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1826 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1828 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 37:40] + when _T_1828 : @[CoreplexNetwork.scala 37:40] + node _T_1829 = or(_T_1716, reset) @[CoreplexNetwork.scala 37:40] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1831 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1832 = or(_T_1724, reset) @[CoreplexNetwork.scala 37:40] + node _T_1834 = eq(_T_1832, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1834 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1835 = or(_T_1726, reset) @[CoreplexNetwork.scala 37:40] + node _T_1837 = eq(_T_1835, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1837 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1839 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1840 = or(_T_1839, reset) @[CoreplexNetwork.scala 37:40] + node _T_1842 = eq(_T_1840, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1842 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1844 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1845 = or(_T_1844, reset) @[CoreplexNetwork.scala 37:40] + node _T_1847 = eq(_T_1845, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1847 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + when io.in[0].e.valid : @[CoreplexNetwork.scala 37:40] + node _T_1849 = lt(io.in[0].e.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 37:40] + node _T_1850 = or(_T_1849, reset) @[CoreplexNetwork.scala 37:40] + node _T_1852 = eq(_T_1850, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1852 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1853 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1855 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1856 = dshl(_T_1855, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1857 = bits(_T_1856, 5, 0) @[package.scala 19:76] + node _T_1858 = not(_T_1857) @[package.scala 19:40] + node _T_1859 = shr(_T_1858, 3) @[Edges.scala 198:59] + node _T_1860 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1862 = eq(_T_1860, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1864 = mux(_T_1862, _T_1859, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1866 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1868 = sub(_T_1866, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1869 = asUInt(_T_1868) @[Edges.scala 208:28] + node _T_1870 = tail(_T_1869, 1) @[Edges.scala 208:28] + node _T_1872 = eq(_T_1866, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1874 = eq(_T_1866, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1876 = eq(_T_1864, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1877 = or(_T_1874, _T_1876) @[Edges.scala 210:37] + node _T_1878 = and(_T_1877, _T_1853) @[Edges.scala 211:22] + node _T_1879 = not(_T_1870) @[Edges.scala 212:27] + node _T_1880 = and(_T_1864, _T_1879) @[Edges.scala 212:25] + when _T_1853 : @[Edges.scala 213:17] + node _T_1881 = mux(_T_1872, _T_1864, _T_1870) @[Edges.scala 214:21] + _T_1866 <= _T_1881 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1883 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1885 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1887 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1889 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1891 : UInt, clock @[CoreplexNetwork.scala 37:40] + node _T_1893 = eq(_T_1872, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1894 = and(io.in[0].a.valid, _T_1893) @[CoreplexNetwork.scala 37:40] + when _T_1894 : @[CoreplexNetwork.scala 37:40] + node _T_1895 = eq(io.in[0].a.bits.opcode, _T_1883) @[CoreplexNetwork.scala 37:40] + node _T_1896 = or(_T_1895, reset) @[CoreplexNetwork.scala 37:40] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1898 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1899 = eq(io.in[0].a.bits.param, _T_1885) @[CoreplexNetwork.scala 37:40] + node _T_1900 = or(_T_1899, reset) @[CoreplexNetwork.scala 37:40] + node _T_1902 = eq(_T_1900, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1902 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1903 = eq(io.in[0].a.bits.size, _T_1887) @[CoreplexNetwork.scala 37:40] + node _T_1904 = or(_T_1903, reset) @[CoreplexNetwork.scala 37:40] + node _T_1906 = eq(_T_1904, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1906 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1907 = eq(io.in[0].a.bits.source, _T_1889) @[CoreplexNetwork.scala 37:40] + node _T_1908 = or(_T_1907, reset) @[CoreplexNetwork.scala 37:40] + node _T_1910 = eq(_T_1908, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1910 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1911 = eq(io.in[0].a.bits.address, _T_1891) @[CoreplexNetwork.scala 37:40] + node _T_1912 = or(_T_1911, reset) @[CoreplexNetwork.scala 37:40] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1914 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1915 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1916 = and(_T_1915, _T_1872) @[CoreplexNetwork.scala 37:40] + when _T_1916 : @[CoreplexNetwork.scala 37:40] + _T_1883 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 37:40] + _T_1885 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 37:40] + _T_1887 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 37:40] + _T_1889 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 37:40] + _T_1891 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1917 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1919 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1920 = dshl(_T_1919, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1921 = bits(_T_1920, 5, 0) @[package.scala 19:76] + node _T_1922 = not(_T_1921) @[package.scala 19:40] + node _T_1923 = shr(_T_1922, 3) @[Edges.scala 198:59] + node _T_1924 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1926 = eq(_T_1924, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1929 = mux(UInt<1>("h00"), _T_1923, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1931 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1933 = sub(_T_1931, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1934 = asUInt(_T_1933) @[Edges.scala 208:28] + node _T_1935 = tail(_T_1934, 1) @[Edges.scala 208:28] + node _T_1937 = eq(_T_1931, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1939 = eq(_T_1931, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1941 = eq(_T_1929, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1942 = or(_T_1939, _T_1941) @[Edges.scala 210:37] + node _T_1943 = and(_T_1942, _T_1917) @[Edges.scala 211:22] + node _T_1944 = not(_T_1935) @[Edges.scala 212:27] + node _T_1945 = and(_T_1929, _T_1944) @[Edges.scala 212:25] + when _T_1917 : @[Edges.scala 213:17] + node _T_1946 = mux(_T_1937, _T_1929, _T_1935) @[Edges.scala 214:21] + _T_1931 <= _T_1946 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1948 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1950 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1952 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1954 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_1956 : UInt, clock @[CoreplexNetwork.scala 37:40] + node _T_1958 = eq(_T_1937, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_1959 = and(io.in[0].b.valid, _T_1958) @[CoreplexNetwork.scala 37:40] + when _T_1959 : @[CoreplexNetwork.scala 37:40] + node _T_1960 = eq(io.in[0].b.bits.opcode, _T_1948) @[CoreplexNetwork.scala 37:40] + node _T_1961 = or(_T_1960, reset) @[CoreplexNetwork.scala 37:40] + node _T_1963 = eq(_T_1961, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1963 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1964 = eq(io.in[0].b.bits.param, _T_1950) @[CoreplexNetwork.scala 37:40] + node _T_1965 = or(_T_1964, reset) @[CoreplexNetwork.scala 37:40] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1967 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1968 = eq(io.in[0].b.bits.size, _T_1952) @[CoreplexNetwork.scala 37:40] + node _T_1969 = or(_T_1968, reset) @[CoreplexNetwork.scala 37:40] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1971 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1972 = eq(io.in[0].b.bits.source, _T_1954) @[CoreplexNetwork.scala 37:40] + node _T_1973 = or(_T_1972, reset) @[CoreplexNetwork.scala 37:40] + node _T_1975 = eq(_T_1973, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1975 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1976 = eq(io.in[0].b.bits.address, _T_1956) @[CoreplexNetwork.scala 37:40] + node _T_1977 = or(_T_1976, reset) @[CoreplexNetwork.scala 37:40] + node _T_1979 = eq(_T_1977, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_1979 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1980 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1981 = and(_T_1980, _T_1937) @[CoreplexNetwork.scala 37:40] + when _T_1981 : @[CoreplexNetwork.scala 37:40] + _T_1948 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 37:40] + _T_1950 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 37:40] + _T_1952 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 37:40] + _T_1954 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 37:40] + _T_1956 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_1982 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1984 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1985 = dshl(_T_1984, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1986 = bits(_T_1985, 5, 0) @[package.scala 19:76] + node _T_1987 = not(_T_1986) @[package.scala 19:40] + node _T_1988 = shr(_T_1987, 3) @[Edges.scala 198:59] + node _T_1989 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1991 = mux(_T_1989, _T_1988, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1993 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1995 = sub(_T_1993, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1996 = asUInt(_T_1995) @[Edges.scala 208:28] + node _T_1997 = tail(_T_1996, 1) @[Edges.scala 208:28] + node _T_1999 = eq(_T_1993, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2001 = eq(_T_1993, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2003 = eq(_T_1991, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2004 = or(_T_2001, _T_2003) @[Edges.scala 210:37] + node _T_2005 = and(_T_2004, _T_1982) @[Edges.scala 211:22] + node _T_2006 = not(_T_1997) @[Edges.scala 212:27] + node _T_2007 = and(_T_1991, _T_2006) @[Edges.scala 212:25] + when _T_1982 : @[Edges.scala 213:17] + node _T_2008 = mux(_T_1999, _T_1991, _T_1997) @[Edges.scala 214:21] + _T_1993 <= _T_2008 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2010 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2012 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2014 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2016 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2018 : UInt, clock @[CoreplexNetwork.scala 37:40] + node _T_2020 = eq(_T_1999, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_2021 = and(io.in[0].c.valid, _T_2020) @[CoreplexNetwork.scala 37:40] + when _T_2021 : @[CoreplexNetwork.scala 37:40] + node _T_2022 = eq(io.in[0].c.bits.opcode, _T_2010) @[CoreplexNetwork.scala 37:40] + node _T_2023 = or(_T_2022, reset) @[CoreplexNetwork.scala 37:40] + node _T_2025 = eq(_T_2023, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2025 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2026 = eq(io.in[0].c.bits.param, _T_2012) @[CoreplexNetwork.scala 37:40] + node _T_2027 = or(_T_2026, reset) @[CoreplexNetwork.scala 37:40] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2029 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2030 = eq(io.in[0].c.bits.size, _T_2014) @[CoreplexNetwork.scala 37:40] + node _T_2031 = or(_T_2030, reset) @[CoreplexNetwork.scala 37:40] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2033 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2034 = eq(io.in[0].c.bits.source, _T_2016) @[CoreplexNetwork.scala 37:40] + node _T_2035 = or(_T_2034, reset) @[CoreplexNetwork.scala 37:40] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2037 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2038 = eq(io.in[0].c.bits.address, _T_2018) @[CoreplexNetwork.scala 37:40] + node _T_2039 = or(_T_2038, reset) @[CoreplexNetwork.scala 37:40] + node _T_2041 = eq(_T_2039, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2041 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2042 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2043 = and(_T_2042, _T_1999) @[CoreplexNetwork.scala 37:40] + when _T_2043 : @[CoreplexNetwork.scala 37:40] + _T_2010 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 37:40] + _T_2012 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 37:40] + _T_2014 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 37:40] + _T_2016 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 37:40] + _T_2018 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2044 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2046 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2047 = dshl(_T_2046, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2048 = bits(_T_2047, 5, 0) @[package.scala 19:76] + node _T_2049 = not(_T_2048) @[package.scala 19:40] + node _T_2050 = shr(_T_2049, 3) @[Edges.scala 198:59] + node _T_2051 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2053 = mux(_T_2051, _T_2050, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2055 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2057 = sub(_T_2055, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2058 = asUInt(_T_2057) @[Edges.scala 208:28] + node _T_2059 = tail(_T_2058, 1) @[Edges.scala 208:28] + node _T_2061 = eq(_T_2055, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2063 = eq(_T_2055, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2065 = eq(_T_2053, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2066 = or(_T_2063, _T_2065) @[Edges.scala 210:37] + node _T_2067 = and(_T_2066, _T_2044) @[Edges.scala 211:22] + node _T_2068 = not(_T_2059) @[Edges.scala 212:27] + node _T_2069 = and(_T_2053, _T_2068) @[Edges.scala 212:25] + when _T_2044 : @[Edges.scala 213:17] + node _T_2070 = mux(_T_2061, _T_2053, _T_2059) @[Edges.scala 214:21] + _T_2055 <= _T_2070 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2072 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2074 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2076 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2078 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2080 : UInt, clock @[CoreplexNetwork.scala 37:40] + reg _T_2082 : UInt, clock @[CoreplexNetwork.scala 37:40] + node _T_2084 = eq(_T_2061, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_2085 = and(io.in[0].d.valid, _T_2084) @[CoreplexNetwork.scala 37:40] + when _T_2085 : @[CoreplexNetwork.scala 37:40] + node _T_2086 = eq(io.in[0].d.bits.opcode, _T_2072) @[CoreplexNetwork.scala 37:40] + node _T_2087 = or(_T_2086, reset) @[CoreplexNetwork.scala 37:40] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2089 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2090 = eq(io.in[0].d.bits.param, _T_2074) @[CoreplexNetwork.scala 37:40] + node _T_2091 = or(_T_2090, reset) @[CoreplexNetwork.scala 37:40] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2093 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2094 = eq(io.in[0].d.bits.size, _T_2076) @[CoreplexNetwork.scala 37:40] + node _T_2095 = or(_T_2094, reset) @[CoreplexNetwork.scala 37:40] + node _T_2097 = eq(_T_2095, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2097 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2098 = eq(io.in[0].d.bits.source, _T_2078) @[CoreplexNetwork.scala 37:40] + node _T_2099 = or(_T_2098, reset) @[CoreplexNetwork.scala 37:40] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2101 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2102 = eq(io.in[0].d.bits.sink, _T_2080) @[CoreplexNetwork.scala 37:40] + node _T_2103 = or(_T_2102, reset) @[CoreplexNetwork.scala 37:40] + node _T_2105 = eq(_T_2103, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2105 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2106 = eq(io.in[0].d.bits.addr_lo, _T_2082) @[CoreplexNetwork.scala 37:40] + node _T_2107 = or(_T_2106, reset) @[CoreplexNetwork.scala 37:40] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2109 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2110 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2111 = and(_T_2110, _T_2061) @[CoreplexNetwork.scala 37:40] + when _T_2111 : @[CoreplexNetwork.scala 37:40] + _T_2072 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 37:40] + _T_2074 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 37:40] + _T_2076 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 37:40] + _T_2078 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 37:40] + _T_2080 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 37:40] + _T_2082 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + reg _T_2113 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2114 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2116 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2117 = dshl(_T_2116, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2118 = bits(_T_2117, 5, 0) @[package.scala 19:76] + node _T_2119 = not(_T_2118) @[package.scala 19:40] + node _T_2120 = shr(_T_2119, 3) @[Edges.scala 198:59] + node _T_2121 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2123 = eq(_T_2121, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2125 = mux(_T_2123, _T_2120, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2127 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2129 = sub(_T_2127, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2130 = asUInt(_T_2129) @[Edges.scala 208:28] + node _T_2131 = tail(_T_2130, 1) @[Edges.scala 208:28] + node _T_2133 = eq(_T_2127, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2135 = eq(_T_2127, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2137 = eq(_T_2125, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2138 = or(_T_2135, _T_2137) @[Edges.scala 210:37] + node _T_2139 = and(_T_2138, _T_2114) @[Edges.scala 211:22] + node _T_2140 = not(_T_2131) @[Edges.scala 212:27] + node _T_2141 = and(_T_2125, _T_2140) @[Edges.scala 212:25] + when _T_2114 : @[Edges.scala 213:17] + node _T_2142 = mux(_T_2133, _T_2125, _T_2131) @[Edges.scala 214:21] + _T_2127 <= _T_2142 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2143 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2145 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2146 = dshl(_T_2145, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2147 = bits(_T_2146, 5, 0) @[package.scala 19:76] + node _T_2148 = not(_T_2147) @[package.scala 19:40] + node _T_2149 = shr(_T_2148, 3) @[Edges.scala 198:59] + node _T_2150 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2152 = mux(_T_2150, _T_2149, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2154 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2156 = sub(_T_2154, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2157 = asUInt(_T_2156) @[Edges.scala 208:28] + node _T_2158 = tail(_T_2157, 1) @[Edges.scala 208:28] + node _T_2160 = eq(_T_2154, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2162 = eq(_T_2154, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2164 = eq(_T_2152, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2165 = or(_T_2162, _T_2164) @[Edges.scala 210:37] + node _T_2166 = and(_T_2165, _T_2143) @[Edges.scala 211:22] + node _T_2167 = not(_T_2158) @[Edges.scala 212:27] + node _T_2168 = and(_T_2152, _T_2167) @[Edges.scala 212:25] + when _T_2143 : @[Edges.scala 213:17] + node _T_2169 = mux(_T_2160, _T_2152, _T_2158) @[Edges.scala 214:21] + _T_2154 <= _T_2169 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2171 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + node _T_2172 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 37:40] + node _T_2173 = or(_T_2171, _T_2172) @[CoreplexNetwork.scala 37:40] + node _T_2175 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_2176 = or(_T_2173, _T_2175) @[CoreplexNetwork.scala 37:40] + node _T_2178 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_2179 = or(_T_2176, _T_2178) @[CoreplexNetwork.scala 37:40] + node _T_2180 = or(_T_2179, reset) @[CoreplexNetwork.scala 37:40] + node _T_2182 = eq(_T_2180, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2182 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + wire _T_2184 : UInt<6> + _T_2184 is invalid + _T_2184 <= UInt<6>("h00") + node _T_2185 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2185 : @[CoreplexNetwork.scala 37:40] + when _T_2138 : @[CoreplexNetwork.scala 37:40] + node _T_2187 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2184 <= _T_2187 @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2188 = dshr(_T_2113, io.in[0].a.bits.source) @[CoreplexNetwork.scala 37:40] + node _T_2189 = bits(_T_2188, 0, 0) @[CoreplexNetwork.scala 37:40] + node _T_2191 = eq(_T_2189, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + node _T_2192 = or(_T_2191, reset) @[CoreplexNetwork.scala 37:40] + node _T_2194 = eq(_T_2192, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2194 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + wire _T_2196 : UInt<6> + _T_2196 is invalid + _T_2196 <= UInt<6>("h00") + node _T_2197 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2199 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 37:40] + node _T_2200 = and(_T_2197, _T_2199) @[CoreplexNetwork.scala 37:40] + when _T_2200 : @[CoreplexNetwork.scala 37:40] + when _T_2165 : @[CoreplexNetwork.scala 37:40] + node _T_2202 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2196 <= _T_2202 @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2203 = or(_T_2184, _T_2113) @[CoreplexNetwork.scala 37:40] + node _T_2204 = dshr(_T_2203, io.in[0].d.bits.source) @[CoreplexNetwork.scala 37:40] + node _T_2205 = bits(_T_2204, 0, 0) @[CoreplexNetwork.scala 37:40] + node _T_2206 = or(_T_2205, reset) @[CoreplexNetwork.scala 37:40] + node _T_2208 = eq(_T_2206, UInt<1>("h00")) @[CoreplexNetwork.scala 37:40] + when _T_2208 : @[CoreplexNetwork.scala 37:40] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:37:40)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 37:40] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + skip @[CoreplexNetwork.scala 37:40] + node _T_2209 = or(_T_2113, _T_2184) @[CoreplexNetwork.scala 37:40] + node _T_2210 = not(_T_2196) @[CoreplexNetwork.scala 37:40] + node _T_2211 = and(_T_2209, _T_2210) @[CoreplexNetwork.scala 37:40] + _T_2113 <= _T_2211 @[CoreplexNetwork.scala 37:40] + + module Queue_29 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_30 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_85 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_87 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_88 = and(_T_85, _T_87) @[Decoupled.scala 188:33] + node _T_89 = and(_T_85, maybe_full) @[Decoupled.scala 189:32] + node _T_90 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_90 + node _T_91 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_91 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_92 = ram[value], clock + _T_92 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_103 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_104 = tail(_T_103, 1) @[Counter.scala 26:22] + value <= _T_104 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_107 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_108 = tail(_T_107, 1) @[Counter.scala 26:22] + value_1 <= _T_108 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_109 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_109 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_111 = eq(_T_88, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_111 @[Decoupled.scala 204:16] + node _T_113 = eq(_T_89, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_113 @[Decoupled.scala 205:16] + infer mport _T_114 = ram[value_1], clock + io.deq.bits <- _T_114 @[Decoupled.scala 206:15] + node _T_123 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_124 = asUInt(_T_123) @[Decoupled.scala 221:40] + node _T_125 = tail(_T_124, 1) @[Decoupled.scala 221:40] + node _T_126 = and(maybe_full, _T_85) @[Decoupled.scala 223:32] + node _T_127 = cat(_T_126, _T_125) @[Cat.scala 30:58] + io.count <= _T_127 @[Decoupled.scala 223:14] + + module TLBuffer_cbus : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_29 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.a.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.a.bits @[Decoupled.scala 255:19] + io.in.0.a.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.a <- Queue.io.deq @[Buffer.scala 58:13] + inst Queue_1 of Queue_30 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.out.0.d.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.out.0.d.bits @[Decoupled.scala 255:19] + io.out.0.d.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.d <- Queue_1.io.deq @[Buffer.scala 59:13] + io.in.0.b.valid <= UInt<1>("h00") @[Buffer.scala 66:20] + io.in.0.c.ready <= UInt<1>("h01") @[Buffer.scala 67:20] + io.in.0.e.ready <= UInt<1>("h01") @[Buffer.scala 68:20] + io.out.0.b.ready <= UInt<1>("h01") @[Buffer.scala 69:21] + io.out.0.c.valid <= UInt<1>("h00") @[Buffer.scala 70:21] + io.out.0.e.valid <= UInt<1>("h00") @[Buffer.scala 71:21] + + module TLMonitor_17 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 36:15] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 36:15] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_608 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + when _T_708 : @[CoreplexNetwork.scala 36:15] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_729 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_730 = cvt(_T_729) @[Parameters.scala 117:49] + node _T_732 = and(_T_730, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_733 = asSInt(_T_732) @[Parameters.scala 117:52] + node _T_735 = eq(_T_733, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_736 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_737 = or(_T_736, _T_735) @[Parameters.scala 133:42] + node _T_738 = and(_T_711, _T_737) @[Parameters.scala 132:56] + node _T_740 = or(UInt<1>("h00"), _T_738) @[Parameters.scala 134:30] + node _T_741 = or(_T_740, reset) @[CoreplexNetwork.scala 36:15] + node _T_743 = eq(_T_741, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_743 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_744 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_746 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_748 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_749 = or(_T_748, reset) @[CoreplexNetwork.scala 36:15] + node _T_751 = eq(_T_749, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_751 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_752 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_754 = eq(_T_752, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_754 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_756 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_757 = or(_T_756, reset) @[CoreplexNetwork.scala 36:15] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_759 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_760 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 36:15] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_763 = or(_T_762, reset) @[CoreplexNetwork.scala 36:15] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_765 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_767 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 36:15] + when _T_767 : @[CoreplexNetwork.scala 36:15] + node _T_770 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_772 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_773 = and(_T_770, _T_772) @[Parameters.scala 63:37] + node _T_774 = or(UInt<1>("h00"), _T_773) @[Parameters.scala 132:31] + node _T_776 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_777 = cvt(_T_776) @[Parameters.scala 117:49] + node _T_779 = and(_T_777, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_780 = asSInt(_T_779) @[Parameters.scala 117:52] + node _T_782 = eq(_T_780, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_784 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_785 = cvt(_T_784) @[Parameters.scala 117:49] + node _T_787 = and(_T_785, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_788 = asSInt(_T_787) @[Parameters.scala 117:52] + node _T_790 = eq(_T_788, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_792 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = or(_T_782, _T_790) @[Parameters.scala 133:42] + node _T_800 = or(_T_799, _T_798) @[Parameters.scala 133:42] + node _T_801 = and(_T_774, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[CoreplexNetwork.scala 36:15] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_806 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_807 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_809 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_810 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_812 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_815 = or(_T_814, reset) @[CoreplexNetwork.scala 36:15] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_817 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_818 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 36:15] + node _T_819 = or(_T_818, reset) @[CoreplexNetwork.scala 36:15] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_821 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_823 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_823 : @[CoreplexNetwork.scala 36:15] + node _T_826 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_828 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_829 = and(_T_826, _T_828) @[Parameters.scala 63:37] + node _T_830 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 132:31] + node _T_832 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_833 = cvt(_T_832) @[Parameters.scala 117:49] + node _T_835 = and(_T_833, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_836 = asSInt(_T_835) @[Parameters.scala 117:52] + node _T_838 = eq(_T_836, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_840 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_841 = cvt(_T_840) @[Parameters.scala 117:49] + node _T_843 = and(_T_841, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_844 = asSInt(_T_843) @[Parameters.scala 117:52] + node _T_846 = eq(_T_844, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_848 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_849 = cvt(_T_848) @[Parameters.scala 117:49] + node _T_851 = and(_T_849, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_852 = asSInt(_T_851) @[Parameters.scala 117:52] + node _T_854 = eq(_T_852, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_855 = or(_T_838, _T_846) @[Parameters.scala 133:42] + node _T_856 = or(_T_855, _T_854) @[Parameters.scala 133:42] + node _T_857 = and(_T_830, _T_856) @[Parameters.scala 132:56] + node _T_859 = or(UInt<1>("h00"), _T_857) @[Parameters.scala 134:30] + node _T_860 = or(_T_859, reset) @[CoreplexNetwork.scala 36:15] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_862 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_863 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_865 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_866 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_868 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_870 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_871 = or(_T_870, reset) @[CoreplexNetwork.scala 36:15] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_873 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_874 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 36:15] + node _T_875 = or(_T_874, reset) @[CoreplexNetwork.scala 36:15] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_877 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_879 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 36:15] + when _T_879 : @[CoreplexNetwork.scala 36:15] + node _T_882 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_884 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_885 = and(_T_882, _T_884) @[Parameters.scala 63:37] + node _T_886 = or(UInt<1>("h00"), _T_885) @[Parameters.scala 132:31] + node _T_888 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_889 = cvt(_T_888) @[Parameters.scala 117:49] + node _T_891 = and(_T_889, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_892 = asSInt(_T_891) @[Parameters.scala 117:52] + node _T_894 = eq(_T_892, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_897 = cvt(_T_896) @[Parameters.scala 117:49] + node _T_899 = and(_T_897, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_900 = asSInt(_T_899) @[Parameters.scala 117:52] + node _T_902 = eq(_T_900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_905 = cvt(_T_904) @[Parameters.scala 117:49] + node _T_907 = and(_T_905, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_908 = asSInt(_T_907) @[Parameters.scala 117:52] + node _T_910 = eq(_T_908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_911 = or(_T_894, _T_902) @[Parameters.scala 133:42] + node _T_912 = or(_T_911, _T_910) @[Parameters.scala 133:42] + node _T_913 = and(_T_886, _T_912) @[Parameters.scala 132:56] + node _T_915 = or(UInt<1>("h00"), _T_913) @[Parameters.scala 134:30] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 36:15] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_918 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_919 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_921 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_922 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_924 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_926 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_927 = or(_T_926, reset) @[CoreplexNetwork.scala 36:15] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_929 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_930 = not(_T_706) @[CoreplexNetwork.scala 36:15] + node _T_931 = and(io.in[0].a.bits.mask, _T_930) @[CoreplexNetwork.scala 36:15] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_934 = or(_T_933, reset) @[CoreplexNetwork.scala 36:15] + node _T_936 = eq(_T_934, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_936 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_938 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 36:15] + when _T_938 : @[CoreplexNetwork.scala 36:15] + node _T_941 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_943 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_944 = cvt(_T_943) @[Parameters.scala 117:49] + node _T_946 = and(_T_944, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_947 = asSInt(_T_946) @[Parameters.scala 117:52] + node _T_949 = eq(_T_947, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_951 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_959 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_960 = cvt(_T_959) @[Parameters.scala 117:49] + node _T_962 = and(_T_960, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_963 = asSInt(_T_962) @[Parameters.scala 117:52] + node _T_965 = eq(_T_963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_966 = or(_T_949, _T_957) @[Parameters.scala 133:42] + node _T_967 = or(_T_966, _T_965) @[Parameters.scala 133:42] + node _T_968 = and(_T_941, _T_967) @[Parameters.scala 132:56] + node _T_970 = or(UInt<1>("h00"), _T_968) @[Parameters.scala 134:30] + node _T_971 = or(_T_970, reset) @[CoreplexNetwork.scala 36:15] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_973 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_974 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_976 = eq(_T_974, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_976 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_977 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_979 = eq(_T_977, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_979 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_981 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_982 = or(_T_981, reset) @[CoreplexNetwork.scala 36:15] + node _T_984 = eq(_T_982, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_984 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_985 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 36:15] + node _T_986 = or(_T_985, reset) @[CoreplexNetwork.scala 36:15] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_988 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_990 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + when _T_990 : @[CoreplexNetwork.scala 36:15] + node _T_993 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_995 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_996 = cvt(_T_995) @[Parameters.scala 117:49] + node _T_998 = and(_T_996, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_999 = asSInt(_T_998) @[Parameters.scala 117:52] + node _T_1001 = eq(_T_999, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1003 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1012 = cvt(_T_1011) @[Parameters.scala 117:49] + node _T_1014 = and(_T_1012, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1015 = asSInt(_T_1014) @[Parameters.scala 117:52] + node _T_1017 = eq(_T_1015, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1018 = or(_T_1001, _T_1009) @[Parameters.scala 133:42] + node _T_1019 = or(_T_1018, _T_1017) @[Parameters.scala 133:42] + node _T_1020 = and(_T_993, _T_1019) @[Parameters.scala 132:56] + node _T_1022 = or(UInt<1>("h00"), _T_1020) @[Parameters.scala 134:30] + node _T_1023 = or(_T_1022, reset) @[CoreplexNetwork.scala 36:15] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1025 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1026 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_1028 = eq(_T_1026, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1028 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1029 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1031 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1033 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1034 = or(_T_1033, reset) @[CoreplexNetwork.scala 36:15] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1036 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 36:15] + node _T_1038 = or(_T_1037, reset) @[CoreplexNetwork.scala 36:15] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1040 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1042 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 36:15] + when _T_1042 : @[CoreplexNetwork.scala 36:15] + node _T_1045 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1047 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1063 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1064 = cvt(_T_1063) @[Parameters.scala 117:49] + node _T_1066 = and(_T_1064, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1067 = asSInt(_T_1066) @[Parameters.scala 117:52] + node _T_1069 = eq(_T_1067, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1070 = or(_T_1053, _T_1061) @[Parameters.scala 133:42] + node _T_1071 = or(_T_1070, _T_1069) @[Parameters.scala 133:42] + node _T_1072 = and(_T_1045, _T_1071) @[Parameters.scala 132:56] + node _T_1074 = or(UInt<1>("h00"), _T_1072) @[Parameters.scala 134:30] + node _T_1075 = or(_T_1074, reset) @[CoreplexNetwork.scala 36:15] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1077 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1078 = or(_T_630, reset) @[CoreplexNetwork.scala 36:15] + node _T_1080 = eq(_T_1078, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1080 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1081 = or(_T_638, reset) @[CoreplexNetwork.scala 36:15] + node _T_1083 = eq(_T_1081, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1083 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1084 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 36:15] + node _T_1085 = or(_T_1084, reset) @[CoreplexNetwork.scala 36:15] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1087 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + when io.in[0].b.valid : @[CoreplexNetwork.scala 36:15] + node _T_1089 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1090 = or(_T_1089, reset) @[CoreplexNetwork.scala 36:15] + node _T_1092 = eq(_T_1090, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1092 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1094 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1095 = cvt(_T_1094) @[Parameters.scala 117:49] + node _T_1097 = and(_T_1095, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1098 = asSInt(_T_1097) @[Parameters.scala 117:52] + node _T_1100 = eq(_T_1098, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1102 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1103 = cvt(_T_1102) @[Parameters.scala 117:49] + node _T_1105 = and(_T_1103, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1106 = asSInt(_T_1105) @[Parameters.scala 117:52] + node _T_1108 = eq(_T_1106, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1110 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1111 = cvt(_T_1110) @[Parameters.scala 117:49] + node _T_1113 = and(_T_1111, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1114 = asSInt(_T_1113) @[Parameters.scala 117:52] + node _T_1116 = eq(_T_1114, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1119 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1119 is invalid @[Parameters.scala 110:36] + _T_1119[0] <= _T_1100 @[Parameters.scala 110:36] + _T_1119[1] <= _T_1108 @[Parameters.scala 110:36] + _T_1119[2] <= _T_1116 @[Parameters.scala 110:36] + node _T_1125 = or(_T_1119[0], _T_1119[1]) @[Parameters.scala 119:64] + node _T_1126 = or(_T_1125, _T_1119[2]) @[Parameters.scala 119:64] + node _T_1128 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1129 = dshl(_T_1128, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1130 = bits(_T_1129, 5, 0) @[package.scala 19:76] + node _T_1131 = not(_T_1130) @[package.scala 19:40] + node _T_1132 = and(io.in[0].b.bits.address, _T_1131) @[Edges.scala 17:16] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1136 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1137 = dshl(UInt<1>("h01"), _T_1136) @[OneHot.scala 49:12] + node _T_1138 = bits(_T_1137, 2, 0) @[OneHot.scala 49:37] + node _T_1140 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1142 = bits(_T_1138, 2, 2) @[package.scala 44:26] + node _T_1143 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[package.scala 46:20] + node _T_1146 = and(UInt<1>("h01"), _T_1145) @[package.scala 49:27] + node _T_1147 = and(_T_1142, _T_1146) @[package.scala 50:38] + node _T_1148 = or(_T_1140, _T_1147) @[package.scala 50:29] + node _T_1149 = and(UInt<1>("h01"), _T_1143) @[package.scala 49:27] + node _T_1150 = and(_T_1142, _T_1149) @[package.scala 50:38] + node _T_1151 = or(_T_1140, _T_1150) @[package.scala 50:29] + node _T_1152 = bits(_T_1138, 1, 1) @[package.scala 44:26] + node _T_1153 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[package.scala 46:20] + node _T_1156 = and(_T_1146, _T_1155) @[package.scala 49:27] + node _T_1157 = and(_T_1152, _T_1156) @[package.scala 50:38] + node _T_1158 = or(_T_1148, _T_1157) @[package.scala 50:29] + node _T_1159 = and(_T_1146, _T_1153) @[package.scala 49:27] + node _T_1160 = and(_T_1152, _T_1159) @[package.scala 50:38] + node _T_1161 = or(_T_1148, _T_1160) @[package.scala 50:29] + node _T_1162 = and(_T_1149, _T_1155) @[package.scala 49:27] + node _T_1163 = and(_T_1152, _T_1162) @[package.scala 50:38] + node _T_1164 = or(_T_1151, _T_1163) @[package.scala 50:29] + node _T_1165 = and(_T_1149, _T_1153) @[package.scala 49:27] + node _T_1166 = and(_T_1152, _T_1165) @[package.scala 50:38] + node _T_1167 = or(_T_1151, _T_1166) @[package.scala 50:29] + node _T_1168 = bits(_T_1138, 0, 0) @[package.scala 44:26] + node _T_1169 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1171 = eq(_T_1169, UInt<1>("h00")) @[package.scala 46:20] + node _T_1172 = and(_T_1156, _T_1171) @[package.scala 49:27] + node _T_1173 = and(_T_1168, _T_1172) @[package.scala 50:38] + node _T_1174 = or(_T_1158, _T_1173) @[package.scala 50:29] + node _T_1175 = and(_T_1156, _T_1169) @[package.scala 49:27] + node _T_1176 = and(_T_1168, _T_1175) @[package.scala 50:38] + node _T_1177 = or(_T_1158, _T_1176) @[package.scala 50:29] + node _T_1178 = and(_T_1159, _T_1171) @[package.scala 49:27] + node _T_1179 = and(_T_1168, _T_1178) @[package.scala 50:38] + node _T_1180 = or(_T_1161, _T_1179) @[package.scala 50:29] + node _T_1181 = and(_T_1159, _T_1169) @[package.scala 49:27] + node _T_1182 = and(_T_1168, _T_1181) @[package.scala 50:38] + node _T_1183 = or(_T_1161, _T_1182) @[package.scala 50:29] + node _T_1184 = and(_T_1162, _T_1171) @[package.scala 49:27] + node _T_1185 = and(_T_1168, _T_1184) @[package.scala 50:38] + node _T_1186 = or(_T_1164, _T_1185) @[package.scala 50:29] + node _T_1187 = and(_T_1162, _T_1169) @[package.scala 49:27] + node _T_1188 = and(_T_1168, _T_1187) @[package.scala 50:38] + node _T_1189 = or(_T_1164, _T_1188) @[package.scala 50:29] + node _T_1190 = and(_T_1165, _T_1171) @[package.scala 49:27] + node _T_1191 = and(_T_1168, _T_1190) @[package.scala 50:38] + node _T_1192 = or(_T_1167, _T_1191) @[package.scala 50:29] + node _T_1193 = and(_T_1165, _T_1169) @[package.scala 49:27] + node _T_1194 = and(_T_1168, _T_1193) @[package.scala 50:38] + node _T_1195 = or(_T_1167, _T_1194) @[package.scala 50:29] + node _T_1196 = cat(_T_1177, _T_1174) @[Cat.scala 30:58] + node _T_1197 = cat(_T_1183, _T_1180) @[Cat.scala 30:58] + node _T_1198 = cat(_T_1197, _T_1196) @[Cat.scala 30:58] + node _T_1199 = cat(_T_1189, _T_1186) @[Cat.scala 30:58] + node _T_1200 = cat(_T_1195, _T_1192) @[Cat.scala 30:58] + node _T_1201 = cat(_T_1200, _T_1199) @[Cat.scala 30:58] + node _T_1202 = cat(_T_1201, _T_1198) @[Cat.scala 30:58] + node _T_1204 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + when _T_1204 : @[CoreplexNetwork.scala 36:15] + node _T_1206 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1207 = not(_T_1206) @[Parameters.scala 37:9] + node _T_1209 = or(_T_1207, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1210 = not(_T_1209) @[Parameters.scala 37:7] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1214 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1216 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1219 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1219 is invalid @[Parameters.scala 228:27] + _T_1219[0] <= _T_1212 @[Parameters.scala 228:27] + _T_1219[1] <= _T_1214 @[Parameters.scala 228:27] + _T_1219[2] <= _T_1216 @[Parameters.scala 228:27] + node _T_1227 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1229 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1230 = and(_T_1227, _T_1229) @[Parameters.scala 63:37] + node _T_1233 = mux(_T_1219[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1235 = mux(_T_1219[1], _T_1230, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1237 = mux(_T_1219[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1239 = or(_T_1233, _T_1235) @[Mux.scala 19:72] + node _T_1240 = or(_T_1239, _T_1237) @[Mux.scala 19:72] + wire _T_1242 : UInt<1> @[Mux.scala 19:72] + _T_1242 is invalid @[Mux.scala 19:72] + _T_1242 <= _T_1240 @[Mux.scala 19:72] + node _T_1243 = or(_T_1242, reset) @[CoreplexNetwork.scala 36:15] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1245 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1246 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1248 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1250 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1251 = or(_T_1250, reset) @[CoreplexNetwork.scala 36:15] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1253 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1254 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1256 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1258 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1259 = or(_T_1258, reset) @[CoreplexNetwork.scala 36:15] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1261 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1262 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 36:15] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1265 = or(_T_1264, reset) @[CoreplexNetwork.scala 36:15] + node _T_1267 = eq(_T_1265, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1267 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1269 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 36:15] + when _T_1269 : @[CoreplexNetwork.scala 36:15] + node _T_1271 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1273 = eq(_T_1271, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1273 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1274 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1276 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1277 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1279 = eq(_T_1277, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1279 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1281 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1282 = or(_T_1281, reset) @[CoreplexNetwork.scala 36:15] + node _T_1284 = eq(_T_1282, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1284 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1285 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1286 = or(_T_1285, reset) @[CoreplexNetwork.scala 36:15] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1288 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1290 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1290 : @[CoreplexNetwork.scala 36:15] + node _T_1292 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1294 = eq(_T_1292, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1294 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1295 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1297 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1298 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1300 = eq(_T_1298, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1300 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1302 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1303 = or(_T_1302, reset) @[CoreplexNetwork.scala 36:15] + node _T_1305 = eq(_T_1303, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1305 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1306 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1307 = or(_T_1306, reset) @[CoreplexNetwork.scala 36:15] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1309 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1311 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 36:15] + when _T_1311 : @[CoreplexNetwork.scala 36:15] + node _T_1313 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1315 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1316 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1318 = eq(_T_1316, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1318 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1319 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1321 = eq(_T_1319, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1321 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1323 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1324 = or(_T_1323, reset) @[CoreplexNetwork.scala 36:15] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1326 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1327 = not(_T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1328 = and(io.in[0].b.bits.mask, _T_1327) @[CoreplexNetwork.scala 36:15] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1331 = or(_T_1330, reset) @[CoreplexNetwork.scala 36:15] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1333 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1335 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 36:15] + when _T_1335 : @[CoreplexNetwork.scala 36:15] + node _T_1337 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1339 = eq(_T_1337, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1339 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1340 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1342 = eq(_T_1340, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1342 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1343 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1345 = eq(_T_1343, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1345 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1347 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1348 = or(_T_1347, reset) @[CoreplexNetwork.scala 36:15] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1350 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1351 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1352 = or(_T_1351, reset) @[CoreplexNetwork.scala 36:15] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1354 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1356 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + when _T_1356 : @[CoreplexNetwork.scala 36:15] + node _T_1358 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1360 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1361 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1363 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1364 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1366 = eq(_T_1364, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1366 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1368 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1369 = or(_T_1368, reset) @[CoreplexNetwork.scala 36:15] + node _T_1371 = eq(_T_1369, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1371 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1372 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1373 = or(_T_1372, reset) @[CoreplexNetwork.scala 36:15] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1375 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1377 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 36:15] + when _T_1377 : @[CoreplexNetwork.scala 36:15] + node _T_1379 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 36:15] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1381 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1382 = or(_T_1126, reset) @[CoreplexNetwork.scala 36:15] + node _T_1384 = eq(_T_1382, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1384 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1385 = or(_T_1134, reset) @[CoreplexNetwork.scala 36:15] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1387 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1388 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 36:15] + node _T_1389 = or(_T_1388, reset) @[CoreplexNetwork.scala 36:15] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1391 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + when io.in[0].c.valid : @[CoreplexNetwork.scala 36:15] + node _T_1393 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1394 = or(_T_1393, reset) @[CoreplexNetwork.scala 36:15] + node _T_1396 = eq(_T_1394, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1396 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1398 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1399 = not(_T_1398) @[Parameters.scala 37:9] + node _T_1401 = or(_T_1399, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1402 = not(_T_1401) @[Parameters.scala 37:7] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1406 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1408 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1411 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1411 is invalid @[Parameters.scala 228:27] + _T_1411[0] <= _T_1404 @[Parameters.scala 228:27] + _T_1411[1] <= _T_1406 @[Parameters.scala 228:27] + _T_1411[2] <= _T_1408 @[Parameters.scala 228:27] + node _T_1417 = or(_T_1411[0], _T_1411[1]) @[Parameters.scala 229:46] + node _T_1418 = or(_T_1417, _T_1411[2]) @[Parameters.scala 229:46] + node _T_1420 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1421 = dshl(_T_1420, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1422 = bits(_T_1421, 5, 0) @[package.scala 19:76] + node _T_1423 = not(_T_1422) @[package.scala 19:40] + node _T_1424 = and(io.in[0].c.bits.address, _T_1423) @[Edges.scala 17:16] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1428 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1429 = cvt(_T_1428) @[Parameters.scala 117:49] + node _T_1431 = and(_T_1429, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1432 = asSInt(_T_1431) @[Parameters.scala 117:52] + node _T_1434 = eq(_T_1432, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1436 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1437 = cvt(_T_1436) @[Parameters.scala 117:49] + node _T_1439 = and(_T_1437, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1440 = asSInt(_T_1439) @[Parameters.scala 117:52] + node _T_1442 = eq(_T_1440, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1444 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1445 = cvt(_T_1444) @[Parameters.scala 117:49] + node _T_1447 = and(_T_1445, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1448 = asSInt(_T_1447) @[Parameters.scala 117:52] + node _T_1450 = eq(_T_1448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1453 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1453 is invalid @[Parameters.scala 110:36] + _T_1453[0] <= _T_1434 @[Parameters.scala 110:36] + _T_1453[1] <= _T_1442 @[Parameters.scala 110:36] + _T_1453[2] <= _T_1450 @[Parameters.scala 110:36] + node _T_1459 = or(_T_1453[0], _T_1453[1]) @[Parameters.scala 119:64] + node _T_1460 = or(_T_1459, _T_1453[2]) @[Parameters.scala 119:64] + node _T_1462 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 36:15] + when _T_1462 : @[CoreplexNetwork.scala 36:15] + node _T_1463 = or(_T_1460, reset) @[CoreplexNetwork.scala 36:15] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1465 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1466 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1468 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1470 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 36:15] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1473 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1474 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1476 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1478 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 36:15] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1481 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1483 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1484 = or(_T_1483, reset) @[CoreplexNetwork.scala 36:15] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1486 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1488 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 36:15] + when _T_1488 : @[CoreplexNetwork.scala 36:15] + node _T_1489 = or(_T_1460, reset) @[CoreplexNetwork.scala 36:15] + node _T_1491 = eq(_T_1489, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1491 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1492 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1494 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1496 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1497 = or(_T_1496, reset) @[CoreplexNetwork.scala 36:15] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1499 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1500 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1502 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1504 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1505 = or(_T_1504, reset) @[CoreplexNetwork.scala 36:15] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1507 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1509 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1510 = or(_T_1509, reset) @[CoreplexNetwork.scala 36:15] + node _T_1512 = eq(_T_1510, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1512 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1514 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + when _T_1514 : @[CoreplexNetwork.scala 36:15] + node _T_1517 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1519 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1520 = cvt(_T_1519) @[Parameters.scala 117:49] + node _T_1522 = and(_T_1520, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1523 = asSInt(_T_1522) @[Parameters.scala 117:52] + node _T_1525 = eq(_T_1523, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1527 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1528 = cvt(_T_1527) @[Parameters.scala 117:49] + node _T_1530 = and(_T_1528, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1531 = asSInt(_T_1530) @[Parameters.scala 117:52] + node _T_1533 = eq(_T_1531, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1535 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1536 = cvt(_T_1535) @[Parameters.scala 117:49] + node _T_1538 = and(_T_1536, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1539 = asSInt(_T_1538) @[Parameters.scala 117:52] + node _T_1541 = eq(_T_1539, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1542 = or(_T_1525, _T_1533) @[Parameters.scala 133:42] + node _T_1543 = or(_T_1542, _T_1541) @[Parameters.scala 133:42] + node _T_1544 = and(_T_1517, _T_1543) @[Parameters.scala 132:56] + node _T_1546 = or(UInt<1>("h00"), _T_1544) @[Parameters.scala 134:30] + node _T_1547 = or(_T_1546, reset) @[CoreplexNetwork.scala 36:15] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1549 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1550 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1552 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1554 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1555 = or(_T_1554, reset) @[CoreplexNetwork.scala 36:15] + node _T_1557 = eq(_T_1555, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1557 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1558 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1560 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1562 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1563 = or(_T_1562, reset) @[CoreplexNetwork.scala 36:15] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1565 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1567 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1568 = or(_T_1567, reset) @[CoreplexNetwork.scala 36:15] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1570 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1572 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 36:15] + when _T_1572 : @[CoreplexNetwork.scala 36:15] + node _T_1575 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1577 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1578 = cvt(_T_1577) @[Parameters.scala 117:49] + node _T_1580 = and(_T_1578, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1581 = asSInt(_T_1580) @[Parameters.scala 117:52] + node _T_1583 = eq(_T_1581, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1585 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1586 = cvt(_T_1585) @[Parameters.scala 117:49] + node _T_1588 = and(_T_1586, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1589 = asSInt(_T_1588) @[Parameters.scala 117:52] + node _T_1591 = eq(_T_1589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1593 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1594 = cvt(_T_1593) @[Parameters.scala 117:49] + node _T_1596 = and(_T_1594, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1597 = asSInt(_T_1596) @[Parameters.scala 117:52] + node _T_1599 = eq(_T_1597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1600 = or(_T_1583, _T_1591) @[Parameters.scala 133:42] + node _T_1601 = or(_T_1600, _T_1599) @[Parameters.scala 133:42] + node _T_1602 = and(_T_1575, _T_1601) @[Parameters.scala 132:56] + node _T_1604 = or(UInt<1>("h00"), _T_1602) @[Parameters.scala 134:30] + node _T_1605 = or(_T_1604, reset) @[CoreplexNetwork.scala 36:15] + node _T_1607 = eq(_T_1605, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1607 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1608 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1610 = eq(_T_1608, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1610 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1612 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1613 = or(_T_1612, reset) @[CoreplexNetwork.scala 36:15] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1615 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1616 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1618 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1620 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1621 = or(_T_1620, reset) @[CoreplexNetwork.scala 36:15] + node _T_1623 = eq(_T_1621, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1623 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1625 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1626 = or(_T_1625, reset) @[CoreplexNetwork.scala 36:15] + node _T_1628 = eq(_T_1626, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1628 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1630 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1630 : @[CoreplexNetwork.scala 36:15] + node _T_1631 = or(_T_1460, reset) @[CoreplexNetwork.scala 36:15] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1633 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1634 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1636 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1637 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1639 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1641 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1642 = or(_T_1641, reset) @[CoreplexNetwork.scala 36:15] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1644 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1646 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 36:15] + when _T_1646 : @[CoreplexNetwork.scala 36:15] + node _T_1647 = or(_T_1460, reset) @[CoreplexNetwork.scala 36:15] + node _T_1649 = eq(_T_1647, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1649 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1650 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1652 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1653 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1655 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1657 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1658 = or(_T_1657, reset) @[CoreplexNetwork.scala 36:15] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1660 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1662 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 36:15] + when _T_1662 : @[CoreplexNetwork.scala 36:15] + node _T_1663 = or(_T_1460, reset) @[CoreplexNetwork.scala 36:15] + node _T_1665 = eq(_T_1663, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1665 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1666 = or(_T_1418, reset) @[CoreplexNetwork.scala 36:15] + node _T_1668 = eq(_T_1666, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1668 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1669 = or(_T_1426, reset) @[CoreplexNetwork.scala 36:15] + node _T_1671 = eq(_T_1669, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1671 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1673 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1674 = or(_T_1673, reset) @[CoreplexNetwork.scala 36:15] + node _T_1676 = eq(_T_1674, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1676 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1678 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1679 = or(_T_1678, reset) @[CoreplexNetwork.scala 36:15] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1681 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + when io.in[0].d.valid : @[CoreplexNetwork.scala 36:15] + node _T_1683 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1684 = or(_T_1683, reset) @[CoreplexNetwork.scala 36:15] + node _T_1686 = eq(_T_1684, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1686 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1688 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1689 = not(_T_1688) @[Parameters.scala 37:9] + node _T_1691 = or(_T_1689, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1692 = not(_T_1691) @[Parameters.scala 37:7] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1696 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1698 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1701 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1701 is invalid @[Parameters.scala 228:27] + _T_1701[0] <= _T_1694 @[Parameters.scala 228:27] + _T_1701[1] <= _T_1696 @[Parameters.scala 228:27] + _T_1701[2] <= _T_1698 @[Parameters.scala 228:27] + node _T_1707 = or(_T_1701[0], _T_1701[1]) @[Parameters.scala 229:46] + node _T_1708 = or(_T_1707, _T_1701[2]) @[Parameters.scala 229:46] + node _T_1710 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1711 = dshl(_T_1710, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1712 = bits(_T_1711, 5, 0) @[package.scala 19:76] + node _T_1713 = not(_T_1712) @[package.scala 19:40] + node _T_1714 = and(io.in[0].d.bits.addr_lo, _T_1713) @[Edges.scala 17:16] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1718 = lt(io.in[0].d.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1720 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + when _T_1720 : @[CoreplexNetwork.scala 36:15] + node _T_1721 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1723 = eq(_T_1721, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1723 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1724 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1726 = eq(_T_1724, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1726 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1727 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1729 = eq(_T_1727, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1729 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1731 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1732 = or(_T_1731, reset) @[CoreplexNetwork.scala 36:15] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1734 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1736 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1737 = or(_T_1736, reset) @[CoreplexNetwork.scala 36:15] + node _T_1739 = eq(_T_1737, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1739 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1741 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1742 = or(_T_1741, reset) @[CoreplexNetwork.scala 36:15] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1744 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1746 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 36:15] + when _T_1746 : @[CoreplexNetwork.scala 36:15] + node _T_1747 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1749 = eq(_T_1747, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1749 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1750 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1752 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1753 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1755 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1757 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1758 = or(_T_1757, reset) @[CoreplexNetwork.scala 36:15] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1760 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1762 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1763 = or(_T_1762, reset) @[CoreplexNetwork.scala 36:15] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1765 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1767 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 36:15] + when _T_1767 : @[CoreplexNetwork.scala 36:15] + node _T_1768 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1770 = eq(_T_1768, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1770 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1771 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1773 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1774 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1776 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1778 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1779 = or(_T_1778, reset) @[CoreplexNetwork.scala 36:15] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1781 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1783 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1784 = or(_T_1783, reset) @[CoreplexNetwork.scala 36:15] + node _T_1786 = eq(_T_1784, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1786 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1788 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1788 : @[CoreplexNetwork.scala 36:15] + node _T_1789 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1791 = eq(_T_1789, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1791 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1792 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1794 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1795 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1797 = eq(_T_1795, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1797 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1799 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1800 = or(_T_1799, reset) @[CoreplexNetwork.scala 36:15] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1802 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1804 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 36:15] + when _T_1804 : @[CoreplexNetwork.scala 36:15] + node _T_1805 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1807 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1808 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1810 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1811 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1813 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1815 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1816 = or(_T_1815, reset) @[CoreplexNetwork.scala 36:15] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1818 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1820 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 36:15] + when _T_1820 : @[CoreplexNetwork.scala 36:15] + node _T_1821 = or(_T_1708, reset) @[CoreplexNetwork.scala 36:15] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1823 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1824 = or(_T_1716, reset) @[CoreplexNetwork.scala 36:15] + node _T_1826 = eq(_T_1824, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1826 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1827 = or(_T_1718, reset) @[CoreplexNetwork.scala 36:15] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1829 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1831 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1832 = or(_T_1831, reset) @[CoreplexNetwork.scala 36:15] + node _T_1834 = eq(_T_1832, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1834 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1836 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1837 = or(_T_1836, reset) @[CoreplexNetwork.scala 36:15] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1839 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + when io.in[0].e.valid : @[CoreplexNetwork.scala 36:15] + node _T_1841 = lt(io.in[0].e.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 36:15] + node _T_1842 = or(_T_1841, reset) @[CoreplexNetwork.scala 36:15] + node _T_1844 = eq(_T_1842, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1844 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1845 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1847 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1848 = dshl(_T_1847, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1849 = bits(_T_1848, 5, 0) @[package.scala 19:76] + node _T_1850 = not(_T_1849) @[package.scala 19:40] + node _T_1851 = shr(_T_1850, 3) @[Edges.scala 198:59] + node _T_1852 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1854 = eq(_T_1852, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1856 = mux(_T_1854, _T_1851, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1858 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1860 = sub(_T_1858, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1861 = asUInt(_T_1860) @[Edges.scala 208:28] + node _T_1862 = tail(_T_1861, 1) @[Edges.scala 208:28] + node _T_1864 = eq(_T_1858, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1866 = eq(_T_1858, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1868 = eq(_T_1856, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1869 = or(_T_1866, _T_1868) @[Edges.scala 210:37] + node _T_1870 = and(_T_1869, _T_1845) @[Edges.scala 211:22] + node _T_1871 = not(_T_1862) @[Edges.scala 212:27] + node _T_1872 = and(_T_1856, _T_1871) @[Edges.scala 212:25] + when _T_1845 : @[Edges.scala 213:17] + node _T_1873 = mux(_T_1864, _T_1856, _T_1862) @[Edges.scala 214:21] + _T_1858 <= _T_1873 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1875 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1877 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1879 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1881 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1883 : UInt, clock @[CoreplexNetwork.scala 36:15] + node _T_1885 = eq(_T_1864, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1886 = and(io.in[0].a.valid, _T_1885) @[CoreplexNetwork.scala 36:15] + when _T_1886 : @[CoreplexNetwork.scala 36:15] + node _T_1887 = eq(io.in[0].a.bits.opcode, _T_1875) @[CoreplexNetwork.scala 36:15] + node _T_1888 = or(_T_1887, reset) @[CoreplexNetwork.scala 36:15] + node _T_1890 = eq(_T_1888, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1890 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1891 = eq(io.in[0].a.bits.param, _T_1877) @[CoreplexNetwork.scala 36:15] + node _T_1892 = or(_T_1891, reset) @[CoreplexNetwork.scala 36:15] + node _T_1894 = eq(_T_1892, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1894 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1895 = eq(io.in[0].a.bits.size, _T_1879) @[CoreplexNetwork.scala 36:15] + node _T_1896 = or(_T_1895, reset) @[CoreplexNetwork.scala 36:15] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1898 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1899 = eq(io.in[0].a.bits.source, _T_1881) @[CoreplexNetwork.scala 36:15] + node _T_1900 = or(_T_1899, reset) @[CoreplexNetwork.scala 36:15] + node _T_1902 = eq(_T_1900, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1902 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1903 = eq(io.in[0].a.bits.address, _T_1883) @[CoreplexNetwork.scala 36:15] + node _T_1904 = or(_T_1903, reset) @[CoreplexNetwork.scala 36:15] + node _T_1906 = eq(_T_1904, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1906 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1907 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1908 = and(_T_1907, _T_1864) @[CoreplexNetwork.scala 36:15] + when _T_1908 : @[CoreplexNetwork.scala 36:15] + _T_1875 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 36:15] + _T_1877 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 36:15] + _T_1879 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 36:15] + _T_1881 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 36:15] + _T_1883 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1909 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1911 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1912 = dshl(_T_1911, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1913 = bits(_T_1912, 5, 0) @[package.scala 19:76] + node _T_1914 = not(_T_1913) @[package.scala 19:40] + node _T_1915 = shr(_T_1914, 3) @[Edges.scala 198:59] + node _T_1916 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1918 = eq(_T_1916, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1921 = mux(UInt<1>("h00"), _T_1915, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1923 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1925 = sub(_T_1923, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1926 = asUInt(_T_1925) @[Edges.scala 208:28] + node _T_1927 = tail(_T_1926, 1) @[Edges.scala 208:28] + node _T_1929 = eq(_T_1923, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1931 = eq(_T_1923, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1933 = eq(_T_1921, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1934 = or(_T_1931, _T_1933) @[Edges.scala 210:37] + node _T_1935 = and(_T_1934, _T_1909) @[Edges.scala 211:22] + node _T_1936 = not(_T_1927) @[Edges.scala 212:27] + node _T_1937 = and(_T_1921, _T_1936) @[Edges.scala 212:25] + when _T_1909 : @[Edges.scala 213:17] + node _T_1938 = mux(_T_1929, _T_1921, _T_1927) @[Edges.scala 214:21] + _T_1923 <= _T_1938 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1940 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1942 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1944 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1946 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_1948 : UInt, clock @[CoreplexNetwork.scala 36:15] + node _T_1950 = eq(_T_1929, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_1951 = and(io.in[0].b.valid, _T_1950) @[CoreplexNetwork.scala 36:15] + when _T_1951 : @[CoreplexNetwork.scala 36:15] + node _T_1952 = eq(io.in[0].b.bits.opcode, _T_1940) @[CoreplexNetwork.scala 36:15] + node _T_1953 = or(_T_1952, reset) @[CoreplexNetwork.scala 36:15] + node _T_1955 = eq(_T_1953, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1955 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1956 = eq(io.in[0].b.bits.param, _T_1942) @[CoreplexNetwork.scala 36:15] + node _T_1957 = or(_T_1956, reset) @[CoreplexNetwork.scala 36:15] + node _T_1959 = eq(_T_1957, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1959 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1960 = eq(io.in[0].b.bits.size, _T_1944) @[CoreplexNetwork.scala 36:15] + node _T_1961 = or(_T_1960, reset) @[CoreplexNetwork.scala 36:15] + node _T_1963 = eq(_T_1961, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1963 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1964 = eq(io.in[0].b.bits.source, _T_1946) @[CoreplexNetwork.scala 36:15] + node _T_1965 = or(_T_1964, reset) @[CoreplexNetwork.scala 36:15] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1967 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1968 = eq(io.in[0].b.bits.address, _T_1948) @[CoreplexNetwork.scala 36:15] + node _T_1969 = or(_T_1968, reset) @[CoreplexNetwork.scala 36:15] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_1971 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1972 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1973 = and(_T_1972, _T_1929) @[CoreplexNetwork.scala 36:15] + when _T_1973 : @[CoreplexNetwork.scala 36:15] + _T_1940 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 36:15] + _T_1942 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 36:15] + _T_1944 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 36:15] + _T_1946 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 36:15] + _T_1948 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_1974 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1976 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1977 = dshl(_T_1976, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1978 = bits(_T_1977, 5, 0) @[package.scala 19:76] + node _T_1979 = not(_T_1978) @[package.scala 19:40] + node _T_1980 = shr(_T_1979, 3) @[Edges.scala 198:59] + node _T_1981 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1983 = mux(_T_1981, _T_1980, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1985 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1987 = sub(_T_1985, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1988 = asUInt(_T_1987) @[Edges.scala 208:28] + node _T_1989 = tail(_T_1988, 1) @[Edges.scala 208:28] + node _T_1991 = eq(_T_1985, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1993 = eq(_T_1985, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1995 = eq(_T_1983, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1996 = or(_T_1993, _T_1995) @[Edges.scala 210:37] + node _T_1997 = and(_T_1996, _T_1974) @[Edges.scala 211:22] + node _T_1998 = not(_T_1989) @[Edges.scala 212:27] + node _T_1999 = and(_T_1983, _T_1998) @[Edges.scala 212:25] + when _T_1974 : @[Edges.scala 213:17] + node _T_2000 = mux(_T_1991, _T_1983, _T_1989) @[Edges.scala 214:21] + _T_1985 <= _T_2000 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2002 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2004 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2006 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2008 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2010 : UInt, clock @[CoreplexNetwork.scala 36:15] + node _T_2012 = eq(_T_1991, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_2013 = and(io.in[0].c.valid, _T_2012) @[CoreplexNetwork.scala 36:15] + when _T_2013 : @[CoreplexNetwork.scala 36:15] + node _T_2014 = eq(io.in[0].c.bits.opcode, _T_2002) @[CoreplexNetwork.scala 36:15] + node _T_2015 = or(_T_2014, reset) @[CoreplexNetwork.scala 36:15] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2017 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2018 = eq(io.in[0].c.bits.param, _T_2004) @[CoreplexNetwork.scala 36:15] + node _T_2019 = or(_T_2018, reset) @[CoreplexNetwork.scala 36:15] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2021 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2022 = eq(io.in[0].c.bits.size, _T_2006) @[CoreplexNetwork.scala 36:15] + node _T_2023 = or(_T_2022, reset) @[CoreplexNetwork.scala 36:15] + node _T_2025 = eq(_T_2023, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2025 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2026 = eq(io.in[0].c.bits.source, _T_2008) @[CoreplexNetwork.scala 36:15] + node _T_2027 = or(_T_2026, reset) @[CoreplexNetwork.scala 36:15] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2029 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2030 = eq(io.in[0].c.bits.address, _T_2010) @[CoreplexNetwork.scala 36:15] + node _T_2031 = or(_T_2030, reset) @[CoreplexNetwork.scala 36:15] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2033 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2034 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2035 = and(_T_2034, _T_1991) @[CoreplexNetwork.scala 36:15] + when _T_2035 : @[CoreplexNetwork.scala 36:15] + _T_2002 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 36:15] + _T_2004 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 36:15] + _T_2006 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 36:15] + _T_2008 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 36:15] + _T_2010 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2036 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2038 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2039 = dshl(_T_2038, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2040 = bits(_T_2039, 5, 0) @[package.scala 19:76] + node _T_2041 = not(_T_2040) @[package.scala 19:40] + node _T_2042 = shr(_T_2041, 3) @[Edges.scala 198:59] + node _T_2043 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2045 = mux(_T_2043, _T_2042, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2047 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2049 = sub(_T_2047, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2050 = asUInt(_T_2049) @[Edges.scala 208:28] + node _T_2051 = tail(_T_2050, 1) @[Edges.scala 208:28] + node _T_2053 = eq(_T_2047, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2055 = eq(_T_2047, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2057 = eq(_T_2045, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2058 = or(_T_2055, _T_2057) @[Edges.scala 210:37] + node _T_2059 = and(_T_2058, _T_2036) @[Edges.scala 211:22] + node _T_2060 = not(_T_2051) @[Edges.scala 212:27] + node _T_2061 = and(_T_2045, _T_2060) @[Edges.scala 212:25] + when _T_2036 : @[Edges.scala 213:17] + node _T_2062 = mux(_T_2053, _T_2045, _T_2051) @[Edges.scala 214:21] + _T_2047 <= _T_2062 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2064 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2066 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2068 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2070 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2072 : UInt, clock @[CoreplexNetwork.scala 36:15] + reg _T_2074 : UInt, clock @[CoreplexNetwork.scala 36:15] + node _T_2076 = eq(_T_2053, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_2077 = and(io.in[0].d.valid, _T_2076) @[CoreplexNetwork.scala 36:15] + when _T_2077 : @[CoreplexNetwork.scala 36:15] + node _T_2078 = eq(io.in[0].d.bits.opcode, _T_2064) @[CoreplexNetwork.scala 36:15] + node _T_2079 = or(_T_2078, reset) @[CoreplexNetwork.scala 36:15] + node _T_2081 = eq(_T_2079, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2081 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2082 = eq(io.in[0].d.bits.param, _T_2066) @[CoreplexNetwork.scala 36:15] + node _T_2083 = or(_T_2082, reset) @[CoreplexNetwork.scala 36:15] + node _T_2085 = eq(_T_2083, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2085 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2086 = eq(io.in[0].d.bits.size, _T_2068) @[CoreplexNetwork.scala 36:15] + node _T_2087 = or(_T_2086, reset) @[CoreplexNetwork.scala 36:15] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2089 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2090 = eq(io.in[0].d.bits.source, _T_2070) @[CoreplexNetwork.scala 36:15] + node _T_2091 = or(_T_2090, reset) @[CoreplexNetwork.scala 36:15] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2093 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2094 = eq(io.in[0].d.bits.sink, _T_2072) @[CoreplexNetwork.scala 36:15] + node _T_2095 = or(_T_2094, reset) @[CoreplexNetwork.scala 36:15] + node _T_2097 = eq(_T_2095, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2097 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2098 = eq(io.in[0].d.bits.addr_lo, _T_2074) @[CoreplexNetwork.scala 36:15] + node _T_2099 = or(_T_2098, reset) @[CoreplexNetwork.scala 36:15] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2101 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2102 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2103 = and(_T_2102, _T_2053) @[CoreplexNetwork.scala 36:15] + when _T_2103 : @[CoreplexNetwork.scala 36:15] + _T_2064 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 36:15] + _T_2066 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 36:15] + _T_2068 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 36:15] + _T_2070 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 36:15] + _T_2072 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 36:15] + _T_2074 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + reg _T_2105 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2106 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2108 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2109 = dshl(_T_2108, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2110 = bits(_T_2109, 5, 0) @[package.scala 19:76] + node _T_2111 = not(_T_2110) @[package.scala 19:40] + node _T_2112 = shr(_T_2111, 3) @[Edges.scala 198:59] + node _T_2113 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2115 = eq(_T_2113, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2117 = mux(_T_2115, _T_2112, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2119 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2121 = sub(_T_2119, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2122 = asUInt(_T_2121) @[Edges.scala 208:28] + node _T_2123 = tail(_T_2122, 1) @[Edges.scala 208:28] + node _T_2125 = eq(_T_2119, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2127 = eq(_T_2119, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2129 = eq(_T_2117, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2130 = or(_T_2127, _T_2129) @[Edges.scala 210:37] + node _T_2131 = and(_T_2130, _T_2106) @[Edges.scala 211:22] + node _T_2132 = not(_T_2123) @[Edges.scala 212:27] + node _T_2133 = and(_T_2117, _T_2132) @[Edges.scala 212:25] + when _T_2106 : @[Edges.scala 213:17] + node _T_2134 = mux(_T_2125, _T_2117, _T_2123) @[Edges.scala 214:21] + _T_2119 <= _T_2134 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2135 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2137 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2138 = dshl(_T_2137, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2139 = bits(_T_2138, 5, 0) @[package.scala 19:76] + node _T_2140 = not(_T_2139) @[package.scala 19:40] + node _T_2141 = shr(_T_2140, 3) @[Edges.scala 198:59] + node _T_2142 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2144 = mux(_T_2142, _T_2141, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2146 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2148 = sub(_T_2146, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2149 = asUInt(_T_2148) @[Edges.scala 208:28] + node _T_2150 = tail(_T_2149, 1) @[Edges.scala 208:28] + node _T_2152 = eq(_T_2146, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2154 = eq(_T_2146, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2156 = eq(_T_2144, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2157 = or(_T_2154, _T_2156) @[Edges.scala 210:37] + node _T_2158 = and(_T_2157, _T_2135) @[Edges.scala 211:22] + node _T_2159 = not(_T_2150) @[Edges.scala 212:27] + node _T_2160 = and(_T_2144, _T_2159) @[Edges.scala 212:25] + when _T_2135 : @[Edges.scala 213:17] + node _T_2161 = mux(_T_2152, _T_2144, _T_2150) @[Edges.scala 214:21] + _T_2146 <= _T_2161 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2163 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + node _T_2164 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 36:15] + node _T_2165 = or(_T_2163, _T_2164) @[CoreplexNetwork.scala 36:15] + node _T_2167 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_2168 = or(_T_2165, _T_2167) @[CoreplexNetwork.scala 36:15] + node _T_2170 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_2171 = or(_T_2168, _T_2170) @[CoreplexNetwork.scala 36:15] + node _T_2172 = or(_T_2171, reset) @[CoreplexNetwork.scala 36:15] + node _T_2174 = eq(_T_2172, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2174 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + wire _T_2176 : UInt<6> + _T_2176 is invalid + _T_2176 <= UInt<6>("h00") + node _T_2177 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2177 : @[CoreplexNetwork.scala 36:15] + when _T_2130 : @[CoreplexNetwork.scala 36:15] + node _T_2179 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2176 <= _T_2179 @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2180 = dshr(_T_2105, io.in[0].a.bits.source) @[CoreplexNetwork.scala 36:15] + node _T_2181 = bits(_T_2180, 0, 0) @[CoreplexNetwork.scala 36:15] + node _T_2183 = eq(_T_2181, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + node _T_2184 = or(_T_2183, reset) @[CoreplexNetwork.scala 36:15] + node _T_2186 = eq(_T_2184, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2186 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + wire _T_2188 : UInt<6> + _T_2188 is invalid + _T_2188 <= UInt<6>("h00") + node _T_2189 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2191 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 36:15] + node _T_2192 = and(_T_2189, _T_2191) @[CoreplexNetwork.scala 36:15] + when _T_2192 : @[CoreplexNetwork.scala 36:15] + when _T_2157 : @[CoreplexNetwork.scala 36:15] + node _T_2194 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2188 <= _T_2194 @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2195 = or(_T_2176, _T_2105) @[CoreplexNetwork.scala 36:15] + node _T_2196 = dshr(_T_2195, io.in[0].d.bits.source) @[CoreplexNetwork.scala 36:15] + node _T_2197 = bits(_T_2196, 0, 0) @[CoreplexNetwork.scala 36:15] + node _T_2198 = or(_T_2197, reset) @[CoreplexNetwork.scala 36:15] + node _T_2200 = eq(_T_2198, UInt<1>("h00")) @[CoreplexNetwork.scala 36:15] + when _T_2200 : @[CoreplexNetwork.scala 36:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:36:15)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 36:15] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + skip @[CoreplexNetwork.scala 36:15] + node _T_2201 = or(_T_2105, _T_2176) @[CoreplexNetwork.scala 36:15] + node _T_2202 = not(_T_2188) @[CoreplexNetwork.scala 36:15] + node _T_2203 = and(_T_2201, _T_2202) @[CoreplexNetwork.scala 36:15] + _T_2105 <= _T_2203 @[CoreplexNetwork.scala 36:15] + + module TLMonitor_18 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 35:13] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 35:13] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_608 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 35:13] + when _T_708 : @[CoreplexNetwork.scala 35:13] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_729 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_730 = cvt(_T_729) @[Parameters.scala 117:49] + node _T_732 = and(_T_730, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_733 = asSInt(_T_732) @[Parameters.scala 117:52] + node _T_735 = eq(_T_733, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_736 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_737 = or(_T_736, _T_735) @[Parameters.scala 133:42] + node _T_738 = and(_T_711, _T_737) @[Parameters.scala 132:56] + node _T_740 = or(UInt<1>("h00"), _T_738) @[Parameters.scala 134:30] + node _T_741 = or(_T_740, reset) @[CoreplexNetwork.scala 35:13] + node _T_743 = eq(_T_741, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_743 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_744 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_746 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_748 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_749 = or(_T_748, reset) @[CoreplexNetwork.scala 35:13] + node _T_751 = eq(_T_749, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_751 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_752 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_754 = eq(_T_752, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_754 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_756 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_757 = or(_T_756, reset) @[CoreplexNetwork.scala 35:13] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_759 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_760 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 35:13] + node _T_762 = eq(_T_760, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_763 = or(_T_762, reset) @[CoreplexNetwork.scala 35:13] + node _T_765 = eq(_T_763, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_765 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_767 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 35:13] + when _T_767 : @[CoreplexNetwork.scala 35:13] + node _T_770 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_772 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_773 = and(_T_770, _T_772) @[Parameters.scala 63:37] + node _T_774 = or(UInt<1>("h00"), _T_773) @[Parameters.scala 132:31] + node _T_776 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_777 = cvt(_T_776) @[Parameters.scala 117:49] + node _T_779 = and(_T_777, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_780 = asSInt(_T_779) @[Parameters.scala 117:52] + node _T_782 = eq(_T_780, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_784 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_785 = cvt(_T_784) @[Parameters.scala 117:49] + node _T_787 = and(_T_785, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_788 = asSInt(_T_787) @[Parameters.scala 117:52] + node _T_790 = eq(_T_788, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_792 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_793 = cvt(_T_792) @[Parameters.scala 117:49] + node _T_795 = and(_T_793, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_796 = asSInt(_T_795) @[Parameters.scala 117:52] + node _T_798 = eq(_T_796, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_799 = or(_T_782, _T_790) @[Parameters.scala 133:42] + node _T_800 = or(_T_799, _T_798) @[Parameters.scala 133:42] + node _T_801 = and(_T_774, _T_800) @[Parameters.scala 132:56] + node _T_803 = or(UInt<1>("h00"), _T_801) @[Parameters.scala 134:30] + node _T_804 = or(_T_803, reset) @[CoreplexNetwork.scala 35:13] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_806 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_807 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_809 = eq(_T_807, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_809 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_810 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_812 = eq(_T_810, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_812 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_814 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_815 = or(_T_814, reset) @[CoreplexNetwork.scala 35:13] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_817 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_818 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 35:13] + node _T_819 = or(_T_818, reset) @[CoreplexNetwork.scala 35:13] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_821 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_823 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_823 : @[CoreplexNetwork.scala 35:13] + node _T_826 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_828 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_829 = and(_T_826, _T_828) @[Parameters.scala 63:37] + node _T_830 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 132:31] + node _T_832 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_833 = cvt(_T_832) @[Parameters.scala 117:49] + node _T_835 = and(_T_833, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_836 = asSInt(_T_835) @[Parameters.scala 117:52] + node _T_838 = eq(_T_836, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_840 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_841 = cvt(_T_840) @[Parameters.scala 117:49] + node _T_843 = and(_T_841, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_844 = asSInt(_T_843) @[Parameters.scala 117:52] + node _T_846 = eq(_T_844, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_848 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_849 = cvt(_T_848) @[Parameters.scala 117:49] + node _T_851 = and(_T_849, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_852 = asSInt(_T_851) @[Parameters.scala 117:52] + node _T_854 = eq(_T_852, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_855 = or(_T_838, _T_846) @[Parameters.scala 133:42] + node _T_856 = or(_T_855, _T_854) @[Parameters.scala 133:42] + node _T_857 = and(_T_830, _T_856) @[Parameters.scala 132:56] + node _T_859 = or(UInt<1>("h00"), _T_857) @[Parameters.scala 134:30] + node _T_860 = or(_T_859, reset) @[CoreplexNetwork.scala 35:13] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_862 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_863 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_865 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_866 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_868 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_870 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_871 = or(_T_870, reset) @[CoreplexNetwork.scala 35:13] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_873 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_874 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 35:13] + node _T_875 = or(_T_874, reset) @[CoreplexNetwork.scala 35:13] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_877 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_879 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 35:13] + when _T_879 : @[CoreplexNetwork.scala 35:13] + node _T_882 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_884 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_885 = and(_T_882, _T_884) @[Parameters.scala 63:37] + node _T_886 = or(UInt<1>("h00"), _T_885) @[Parameters.scala 132:31] + node _T_888 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_889 = cvt(_T_888) @[Parameters.scala 117:49] + node _T_891 = and(_T_889, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_892 = asSInt(_T_891) @[Parameters.scala 117:52] + node _T_894 = eq(_T_892, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_897 = cvt(_T_896) @[Parameters.scala 117:49] + node _T_899 = and(_T_897, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_900 = asSInt(_T_899) @[Parameters.scala 117:52] + node _T_902 = eq(_T_900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_905 = cvt(_T_904) @[Parameters.scala 117:49] + node _T_907 = and(_T_905, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_908 = asSInt(_T_907) @[Parameters.scala 117:52] + node _T_910 = eq(_T_908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_911 = or(_T_894, _T_902) @[Parameters.scala 133:42] + node _T_912 = or(_T_911, _T_910) @[Parameters.scala 133:42] + node _T_913 = and(_T_886, _T_912) @[Parameters.scala 132:56] + node _T_915 = or(UInt<1>("h00"), _T_913) @[Parameters.scala 134:30] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 35:13] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_918 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_919 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_921 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_922 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_924 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_926 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_927 = or(_T_926, reset) @[CoreplexNetwork.scala 35:13] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_929 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_930 = not(_T_706) @[CoreplexNetwork.scala 35:13] + node _T_931 = and(io.in[0].a.bits.mask, _T_930) @[CoreplexNetwork.scala 35:13] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_934 = or(_T_933, reset) @[CoreplexNetwork.scala 35:13] + node _T_936 = eq(_T_934, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_936 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_938 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 35:13] + when _T_938 : @[CoreplexNetwork.scala 35:13] + node _T_941 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_943 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_944 = cvt(_T_943) @[Parameters.scala 117:49] + node _T_946 = and(_T_944, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_947 = asSInt(_T_946) @[Parameters.scala 117:52] + node _T_949 = eq(_T_947, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_951 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_959 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_960 = cvt(_T_959) @[Parameters.scala 117:49] + node _T_962 = and(_T_960, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_963 = asSInt(_T_962) @[Parameters.scala 117:52] + node _T_965 = eq(_T_963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_966 = or(_T_949, _T_957) @[Parameters.scala 133:42] + node _T_967 = or(_T_966, _T_965) @[Parameters.scala 133:42] + node _T_968 = and(_T_941, _T_967) @[Parameters.scala 132:56] + node _T_970 = or(UInt<1>("h00"), _T_968) @[Parameters.scala 134:30] + node _T_971 = or(_T_970, reset) @[CoreplexNetwork.scala 35:13] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_973 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_974 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_976 = eq(_T_974, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_976 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_977 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_979 = eq(_T_977, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_979 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_981 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_982 = or(_T_981, reset) @[CoreplexNetwork.scala 35:13] + node _T_984 = eq(_T_982, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_984 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_985 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 35:13] + node _T_986 = or(_T_985, reset) @[CoreplexNetwork.scala 35:13] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_988 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_990 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + when _T_990 : @[CoreplexNetwork.scala 35:13] + node _T_993 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_995 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_996 = cvt(_T_995) @[Parameters.scala 117:49] + node _T_998 = and(_T_996, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_999 = asSInt(_T_998) @[Parameters.scala 117:52] + node _T_1001 = eq(_T_999, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1003 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1012 = cvt(_T_1011) @[Parameters.scala 117:49] + node _T_1014 = and(_T_1012, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1015 = asSInt(_T_1014) @[Parameters.scala 117:52] + node _T_1017 = eq(_T_1015, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1018 = or(_T_1001, _T_1009) @[Parameters.scala 133:42] + node _T_1019 = or(_T_1018, _T_1017) @[Parameters.scala 133:42] + node _T_1020 = and(_T_993, _T_1019) @[Parameters.scala 132:56] + node _T_1022 = or(UInt<1>("h00"), _T_1020) @[Parameters.scala 134:30] + node _T_1023 = or(_T_1022, reset) @[CoreplexNetwork.scala 35:13] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1025 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1026 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_1028 = eq(_T_1026, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1028 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1029 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1031 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1033 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1034 = or(_T_1033, reset) @[CoreplexNetwork.scala 35:13] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1036 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 35:13] + node _T_1038 = or(_T_1037, reset) @[CoreplexNetwork.scala 35:13] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1040 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1042 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 35:13] + when _T_1042 : @[CoreplexNetwork.scala 35:13] + node _T_1045 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1047 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1063 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1064 = cvt(_T_1063) @[Parameters.scala 117:49] + node _T_1066 = and(_T_1064, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1067 = asSInt(_T_1066) @[Parameters.scala 117:52] + node _T_1069 = eq(_T_1067, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1070 = or(_T_1053, _T_1061) @[Parameters.scala 133:42] + node _T_1071 = or(_T_1070, _T_1069) @[Parameters.scala 133:42] + node _T_1072 = and(_T_1045, _T_1071) @[Parameters.scala 132:56] + node _T_1074 = or(UInt<1>("h00"), _T_1072) @[Parameters.scala 134:30] + node _T_1075 = or(_T_1074, reset) @[CoreplexNetwork.scala 35:13] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1077 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1078 = or(_T_630, reset) @[CoreplexNetwork.scala 35:13] + node _T_1080 = eq(_T_1078, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1080 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1081 = or(_T_638, reset) @[CoreplexNetwork.scala 35:13] + node _T_1083 = eq(_T_1081, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1083 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1084 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 35:13] + node _T_1085 = or(_T_1084, reset) @[CoreplexNetwork.scala 35:13] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1087 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + when io.in[0].b.valid : @[CoreplexNetwork.scala 35:13] + node _T_1089 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1090 = or(_T_1089, reset) @[CoreplexNetwork.scala 35:13] + node _T_1092 = eq(_T_1090, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1092 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1094 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1095 = cvt(_T_1094) @[Parameters.scala 117:49] + node _T_1097 = and(_T_1095, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1098 = asSInt(_T_1097) @[Parameters.scala 117:52] + node _T_1100 = eq(_T_1098, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1102 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1103 = cvt(_T_1102) @[Parameters.scala 117:49] + node _T_1105 = and(_T_1103, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1106 = asSInt(_T_1105) @[Parameters.scala 117:52] + node _T_1108 = eq(_T_1106, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1110 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1111 = cvt(_T_1110) @[Parameters.scala 117:49] + node _T_1113 = and(_T_1111, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1114 = asSInt(_T_1113) @[Parameters.scala 117:52] + node _T_1116 = eq(_T_1114, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1119 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1119 is invalid @[Parameters.scala 110:36] + _T_1119[0] <= _T_1100 @[Parameters.scala 110:36] + _T_1119[1] <= _T_1108 @[Parameters.scala 110:36] + _T_1119[2] <= _T_1116 @[Parameters.scala 110:36] + node _T_1125 = or(_T_1119[0], _T_1119[1]) @[Parameters.scala 119:64] + node _T_1126 = or(_T_1125, _T_1119[2]) @[Parameters.scala 119:64] + node _T_1128 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1129 = dshl(_T_1128, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1130 = bits(_T_1129, 5, 0) @[package.scala 19:76] + node _T_1131 = not(_T_1130) @[package.scala 19:40] + node _T_1132 = and(io.in[0].b.bits.address, _T_1131) @[Edges.scala 17:16] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1136 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1137 = dshl(UInt<1>("h01"), _T_1136) @[OneHot.scala 49:12] + node _T_1138 = bits(_T_1137, 2, 0) @[OneHot.scala 49:37] + node _T_1140 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1142 = bits(_T_1138, 2, 2) @[package.scala 44:26] + node _T_1143 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[package.scala 46:20] + node _T_1146 = and(UInt<1>("h01"), _T_1145) @[package.scala 49:27] + node _T_1147 = and(_T_1142, _T_1146) @[package.scala 50:38] + node _T_1148 = or(_T_1140, _T_1147) @[package.scala 50:29] + node _T_1149 = and(UInt<1>("h01"), _T_1143) @[package.scala 49:27] + node _T_1150 = and(_T_1142, _T_1149) @[package.scala 50:38] + node _T_1151 = or(_T_1140, _T_1150) @[package.scala 50:29] + node _T_1152 = bits(_T_1138, 1, 1) @[package.scala 44:26] + node _T_1153 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[package.scala 46:20] + node _T_1156 = and(_T_1146, _T_1155) @[package.scala 49:27] + node _T_1157 = and(_T_1152, _T_1156) @[package.scala 50:38] + node _T_1158 = or(_T_1148, _T_1157) @[package.scala 50:29] + node _T_1159 = and(_T_1146, _T_1153) @[package.scala 49:27] + node _T_1160 = and(_T_1152, _T_1159) @[package.scala 50:38] + node _T_1161 = or(_T_1148, _T_1160) @[package.scala 50:29] + node _T_1162 = and(_T_1149, _T_1155) @[package.scala 49:27] + node _T_1163 = and(_T_1152, _T_1162) @[package.scala 50:38] + node _T_1164 = or(_T_1151, _T_1163) @[package.scala 50:29] + node _T_1165 = and(_T_1149, _T_1153) @[package.scala 49:27] + node _T_1166 = and(_T_1152, _T_1165) @[package.scala 50:38] + node _T_1167 = or(_T_1151, _T_1166) @[package.scala 50:29] + node _T_1168 = bits(_T_1138, 0, 0) @[package.scala 44:26] + node _T_1169 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1171 = eq(_T_1169, UInt<1>("h00")) @[package.scala 46:20] + node _T_1172 = and(_T_1156, _T_1171) @[package.scala 49:27] + node _T_1173 = and(_T_1168, _T_1172) @[package.scala 50:38] + node _T_1174 = or(_T_1158, _T_1173) @[package.scala 50:29] + node _T_1175 = and(_T_1156, _T_1169) @[package.scala 49:27] + node _T_1176 = and(_T_1168, _T_1175) @[package.scala 50:38] + node _T_1177 = or(_T_1158, _T_1176) @[package.scala 50:29] + node _T_1178 = and(_T_1159, _T_1171) @[package.scala 49:27] + node _T_1179 = and(_T_1168, _T_1178) @[package.scala 50:38] + node _T_1180 = or(_T_1161, _T_1179) @[package.scala 50:29] + node _T_1181 = and(_T_1159, _T_1169) @[package.scala 49:27] + node _T_1182 = and(_T_1168, _T_1181) @[package.scala 50:38] + node _T_1183 = or(_T_1161, _T_1182) @[package.scala 50:29] + node _T_1184 = and(_T_1162, _T_1171) @[package.scala 49:27] + node _T_1185 = and(_T_1168, _T_1184) @[package.scala 50:38] + node _T_1186 = or(_T_1164, _T_1185) @[package.scala 50:29] + node _T_1187 = and(_T_1162, _T_1169) @[package.scala 49:27] + node _T_1188 = and(_T_1168, _T_1187) @[package.scala 50:38] + node _T_1189 = or(_T_1164, _T_1188) @[package.scala 50:29] + node _T_1190 = and(_T_1165, _T_1171) @[package.scala 49:27] + node _T_1191 = and(_T_1168, _T_1190) @[package.scala 50:38] + node _T_1192 = or(_T_1167, _T_1191) @[package.scala 50:29] + node _T_1193 = and(_T_1165, _T_1169) @[package.scala 49:27] + node _T_1194 = and(_T_1168, _T_1193) @[package.scala 50:38] + node _T_1195 = or(_T_1167, _T_1194) @[package.scala 50:29] + node _T_1196 = cat(_T_1177, _T_1174) @[Cat.scala 30:58] + node _T_1197 = cat(_T_1183, _T_1180) @[Cat.scala 30:58] + node _T_1198 = cat(_T_1197, _T_1196) @[Cat.scala 30:58] + node _T_1199 = cat(_T_1189, _T_1186) @[Cat.scala 30:58] + node _T_1200 = cat(_T_1195, _T_1192) @[Cat.scala 30:58] + node _T_1201 = cat(_T_1200, _T_1199) @[Cat.scala 30:58] + node _T_1202 = cat(_T_1201, _T_1198) @[Cat.scala 30:58] + node _T_1204 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 35:13] + when _T_1204 : @[CoreplexNetwork.scala 35:13] + node _T_1206 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1207 = not(_T_1206) @[Parameters.scala 37:9] + node _T_1209 = or(_T_1207, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1210 = not(_T_1209) @[Parameters.scala 37:7] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1214 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1216 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1219 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1219 is invalid @[Parameters.scala 228:27] + _T_1219[0] <= _T_1212 @[Parameters.scala 228:27] + _T_1219[1] <= _T_1214 @[Parameters.scala 228:27] + _T_1219[2] <= _T_1216 @[Parameters.scala 228:27] + node _T_1227 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1229 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1230 = and(_T_1227, _T_1229) @[Parameters.scala 63:37] + node _T_1233 = mux(_T_1219[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1235 = mux(_T_1219[1], _T_1230, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1237 = mux(_T_1219[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1239 = or(_T_1233, _T_1235) @[Mux.scala 19:72] + node _T_1240 = or(_T_1239, _T_1237) @[Mux.scala 19:72] + wire _T_1242 : UInt<1> @[Mux.scala 19:72] + _T_1242 is invalid @[Mux.scala 19:72] + _T_1242 <= _T_1240 @[Mux.scala 19:72] + node _T_1243 = or(_T_1242, reset) @[CoreplexNetwork.scala 35:13] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1245 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1246 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1248 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1250 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1251 = or(_T_1250, reset) @[CoreplexNetwork.scala 35:13] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1253 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1254 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1256 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1258 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1259 = or(_T_1258, reset) @[CoreplexNetwork.scala 35:13] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1261 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1262 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 35:13] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1265 = or(_T_1264, reset) @[CoreplexNetwork.scala 35:13] + node _T_1267 = eq(_T_1265, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1267 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1269 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 35:13] + when _T_1269 : @[CoreplexNetwork.scala 35:13] + node _T_1271 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1273 = eq(_T_1271, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1273 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1274 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1276 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1277 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1279 = eq(_T_1277, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1279 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1281 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1282 = or(_T_1281, reset) @[CoreplexNetwork.scala 35:13] + node _T_1284 = eq(_T_1282, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1284 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1285 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1286 = or(_T_1285, reset) @[CoreplexNetwork.scala 35:13] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1288 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1290 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1290 : @[CoreplexNetwork.scala 35:13] + node _T_1292 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1294 = eq(_T_1292, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1294 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1295 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1297 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1298 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1300 = eq(_T_1298, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1300 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1302 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1303 = or(_T_1302, reset) @[CoreplexNetwork.scala 35:13] + node _T_1305 = eq(_T_1303, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1305 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1306 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1307 = or(_T_1306, reset) @[CoreplexNetwork.scala 35:13] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1309 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1311 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 35:13] + when _T_1311 : @[CoreplexNetwork.scala 35:13] + node _T_1313 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1315 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1316 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1318 = eq(_T_1316, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1318 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1319 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1321 = eq(_T_1319, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1321 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1323 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1324 = or(_T_1323, reset) @[CoreplexNetwork.scala 35:13] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1326 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1327 = not(_T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1328 = and(io.in[0].b.bits.mask, _T_1327) @[CoreplexNetwork.scala 35:13] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1331 = or(_T_1330, reset) @[CoreplexNetwork.scala 35:13] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1333 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1335 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 35:13] + when _T_1335 : @[CoreplexNetwork.scala 35:13] + node _T_1337 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1339 = eq(_T_1337, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1339 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1340 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1342 = eq(_T_1340, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1342 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1343 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1345 = eq(_T_1343, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1345 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1347 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1348 = or(_T_1347, reset) @[CoreplexNetwork.scala 35:13] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1350 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1351 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1352 = or(_T_1351, reset) @[CoreplexNetwork.scala 35:13] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1354 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1356 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + when _T_1356 : @[CoreplexNetwork.scala 35:13] + node _T_1358 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1360 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1361 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1363 = eq(_T_1361, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1363 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1364 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1366 = eq(_T_1364, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1366 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1368 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1369 = or(_T_1368, reset) @[CoreplexNetwork.scala 35:13] + node _T_1371 = eq(_T_1369, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1371 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1372 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1373 = or(_T_1372, reset) @[CoreplexNetwork.scala 35:13] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1375 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1377 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 35:13] + when _T_1377 : @[CoreplexNetwork.scala 35:13] + node _T_1379 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 35:13] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1381 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1382 = or(_T_1126, reset) @[CoreplexNetwork.scala 35:13] + node _T_1384 = eq(_T_1382, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1384 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1385 = or(_T_1134, reset) @[CoreplexNetwork.scala 35:13] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1387 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1388 = eq(io.in[0].b.bits.mask, _T_1202) @[CoreplexNetwork.scala 35:13] + node _T_1389 = or(_T_1388, reset) @[CoreplexNetwork.scala 35:13] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1391 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + when io.in[0].c.valid : @[CoreplexNetwork.scala 35:13] + node _T_1393 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1394 = or(_T_1393, reset) @[CoreplexNetwork.scala 35:13] + node _T_1396 = eq(_T_1394, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1396 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1398 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1399 = not(_T_1398) @[Parameters.scala 37:9] + node _T_1401 = or(_T_1399, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1402 = not(_T_1401) @[Parameters.scala 37:7] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1406 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1408 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1411 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1411 is invalid @[Parameters.scala 228:27] + _T_1411[0] <= _T_1404 @[Parameters.scala 228:27] + _T_1411[1] <= _T_1406 @[Parameters.scala 228:27] + _T_1411[2] <= _T_1408 @[Parameters.scala 228:27] + node _T_1417 = or(_T_1411[0], _T_1411[1]) @[Parameters.scala 229:46] + node _T_1418 = or(_T_1417, _T_1411[2]) @[Parameters.scala 229:46] + node _T_1420 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1421 = dshl(_T_1420, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1422 = bits(_T_1421, 5, 0) @[package.scala 19:76] + node _T_1423 = not(_T_1422) @[package.scala 19:40] + node _T_1424 = and(io.in[0].c.bits.address, _T_1423) @[Edges.scala 17:16] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1428 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1429 = cvt(_T_1428) @[Parameters.scala 117:49] + node _T_1431 = and(_T_1429, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1432 = asSInt(_T_1431) @[Parameters.scala 117:52] + node _T_1434 = eq(_T_1432, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1436 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1437 = cvt(_T_1436) @[Parameters.scala 117:49] + node _T_1439 = and(_T_1437, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1440 = asSInt(_T_1439) @[Parameters.scala 117:52] + node _T_1442 = eq(_T_1440, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1444 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1445 = cvt(_T_1444) @[Parameters.scala 117:49] + node _T_1447 = and(_T_1445, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1448 = asSInt(_T_1447) @[Parameters.scala 117:52] + node _T_1450 = eq(_T_1448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1453 : UInt<1>[3] @[Parameters.scala 110:36] + _T_1453 is invalid @[Parameters.scala 110:36] + _T_1453[0] <= _T_1434 @[Parameters.scala 110:36] + _T_1453[1] <= _T_1442 @[Parameters.scala 110:36] + _T_1453[2] <= _T_1450 @[Parameters.scala 110:36] + node _T_1459 = or(_T_1453[0], _T_1453[1]) @[Parameters.scala 119:64] + node _T_1460 = or(_T_1459, _T_1453[2]) @[Parameters.scala 119:64] + node _T_1462 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 35:13] + when _T_1462 : @[CoreplexNetwork.scala 35:13] + node _T_1463 = or(_T_1460, reset) @[CoreplexNetwork.scala 35:13] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1465 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1466 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1468 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1470 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 35:13] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1473 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1474 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1476 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1478 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 35:13] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1481 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1483 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1484 = or(_T_1483, reset) @[CoreplexNetwork.scala 35:13] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1486 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1488 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 35:13] + when _T_1488 : @[CoreplexNetwork.scala 35:13] + node _T_1489 = or(_T_1460, reset) @[CoreplexNetwork.scala 35:13] + node _T_1491 = eq(_T_1489, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1491 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1492 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1494 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1496 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1497 = or(_T_1496, reset) @[CoreplexNetwork.scala 35:13] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1499 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1500 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1502 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1504 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1505 = or(_T_1504, reset) @[CoreplexNetwork.scala 35:13] + node _T_1507 = eq(_T_1505, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1507 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1509 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1510 = or(_T_1509, reset) @[CoreplexNetwork.scala 35:13] + node _T_1512 = eq(_T_1510, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1512 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1514 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 35:13] + when _T_1514 : @[CoreplexNetwork.scala 35:13] + node _T_1517 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1519 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1520 = cvt(_T_1519) @[Parameters.scala 117:49] + node _T_1522 = and(_T_1520, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1523 = asSInt(_T_1522) @[Parameters.scala 117:52] + node _T_1525 = eq(_T_1523, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1527 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1528 = cvt(_T_1527) @[Parameters.scala 117:49] + node _T_1530 = and(_T_1528, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1531 = asSInt(_T_1530) @[Parameters.scala 117:52] + node _T_1533 = eq(_T_1531, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1535 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1536 = cvt(_T_1535) @[Parameters.scala 117:49] + node _T_1538 = and(_T_1536, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1539 = asSInt(_T_1538) @[Parameters.scala 117:52] + node _T_1541 = eq(_T_1539, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1542 = or(_T_1525, _T_1533) @[Parameters.scala 133:42] + node _T_1543 = or(_T_1542, _T_1541) @[Parameters.scala 133:42] + node _T_1544 = and(_T_1517, _T_1543) @[Parameters.scala 132:56] + node _T_1546 = or(UInt<1>("h00"), _T_1544) @[Parameters.scala 134:30] + node _T_1547 = or(_T_1546, reset) @[CoreplexNetwork.scala 35:13] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1549 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1550 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1552 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1554 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1555 = or(_T_1554, reset) @[CoreplexNetwork.scala 35:13] + node _T_1557 = eq(_T_1555, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1557 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1558 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1560 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1562 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1563 = or(_T_1562, reset) @[CoreplexNetwork.scala 35:13] + node _T_1565 = eq(_T_1563, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1565 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1567 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1568 = or(_T_1567, reset) @[CoreplexNetwork.scala 35:13] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1570 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1572 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 35:13] + when _T_1572 : @[CoreplexNetwork.scala 35:13] + node _T_1575 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1577 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1578 = cvt(_T_1577) @[Parameters.scala 117:49] + node _T_1580 = and(_T_1578, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1581 = asSInt(_T_1580) @[Parameters.scala 117:52] + node _T_1583 = eq(_T_1581, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1585 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1586 = cvt(_T_1585) @[Parameters.scala 117:49] + node _T_1588 = and(_T_1586, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1589 = asSInt(_T_1588) @[Parameters.scala 117:52] + node _T_1591 = eq(_T_1589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1593 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1594 = cvt(_T_1593) @[Parameters.scala 117:49] + node _T_1596 = and(_T_1594, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1597 = asSInt(_T_1596) @[Parameters.scala 117:52] + node _T_1599 = eq(_T_1597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1600 = or(_T_1583, _T_1591) @[Parameters.scala 133:42] + node _T_1601 = or(_T_1600, _T_1599) @[Parameters.scala 133:42] + node _T_1602 = and(_T_1575, _T_1601) @[Parameters.scala 132:56] + node _T_1604 = or(UInt<1>("h00"), _T_1602) @[Parameters.scala 134:30] + node _T_1605 = or(_T_1604, reset) @[CoreplexNetwork.scala 35:13] + node _T_1607 = eq(_T_1605, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1607 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1608 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1610 = eq(_T_1608, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1610 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1612 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1613 = or(_T_1612, reset) @[CoreplexNetwork.scala 35:13] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1615 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1616 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1618 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1620 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1621 = or(_T_1620, reset) @[CoreplexNetwork.scala 35:13] + node _T_1623 = eq(_T_1621, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1623 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1625 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1626 = or(_T_1625, reset) @[CoreplexNetwork.scala 35:13] + node _T_1628 = eq(_T_1626, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1628 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1630 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1630 : @[CoreplexNetwork.scala 35:13] + node _T_1631 = or(_T_1460, reset) @[CoreplexNetwork.scala 35:13] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1633 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1634 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1636 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1637 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1639 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1641 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1642 = or(_T_1641, reset) @[CoreplexNetwork.scala 35:13] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1644 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1646 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 35:13] + when _T_1646 : @[CoreplexNetwork.scala 35:13] + node _T_1647 = or(_T_1460, reset) @[CoreplexNetwork.scala 35:13] + node _T_1649 = eq(_T_1647, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1649 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1650 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1652 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1653 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1655 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1657 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1658 = or(_T_1657, reset) @[CoreplexNetwork.scala 35:13] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1660 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1662 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 35:13] + when _T_1662 : @[CoreplexNetwork.scala 35:13] + node _T_1663 = or(_T_1460, reset) @[CoreplexNetwork.scala 35:13] + node _T_1665 = eq(_T_1663, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1665 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1666 = or(_T_1418, reset) @[CoreplexNetwork.scala 35:13] + node _T_1668 = eq(_T_1666, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1668 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1669 = or(_T_1426, reset) @[CoreplexNetwork.scala 35:13] + node _T_1671 = eq(_T_1669, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1671 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1673 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1674 = or(_T_1673, reset) @[CoreplexNetwork.scala 35:13] + node _T_1676 = eq(_T_1674, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1676 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1678 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1679 = or(_T_1678, reset) @[CoreplexNetwork.scala 35:13] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1681 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + when io.in[0].d.valid : @[CoreplexNetwork.scala 35:13] + node _T_1683 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1684 = or(_T_1683, reset) @[CoreplexNetwork.scala 35:13] + node _T_1686 = eq(_T_1684, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1686 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1688 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1689 = not(_T_1688) @[Parameters.scala 37:9] + node _T_1691 = or(_T_1689, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1692 = not(_T_1691) @[Parameters.scala 37:7] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1696 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1698 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1701 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1701 is invalid @[Parameters.scala 228:27] + _T_1701[0] <= _T_1694 @[Parameters.scala 228:27] + _T_1701[1] <= _T_1696 @[Parameters.scala 228:27] + _T_1701[2] <= _T_1698 @[Parameters.scala 228:27] + node _T_1707 = or(_T_1701[0], _T_1701[1]) @[Parameters.scala 229:46] + node _T_1708 = or(_T_1707, _T_1701[2]) @[Parameters.scala 229:46] + node _T_1710 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1711 = dshl(_T_1710, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1712 = bits(_T_1711, 5, 0) @[package.scala 19:76] + node _T_1713 = not(_T_1712) @[package.scala 19:40] + node _T_1714 = and(io.in[0].d.bits.addr_lo, _T_1713) @[Edges.scala 17:16] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1718 = lt(io.in[0].d.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1720 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 35:13] + when _T_1720 : @[CoreplexNetwork.scala 35:13] + node _T_1721 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1723 = eq(_T_1721, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1723 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1724 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1726 = eq(_T_1724, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1726 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1727 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1729 = eq(_T_1727, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1729 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1731 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1732 = or(_T_1731, reset) @[CoreplexNetwork.scala 35:13] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1734 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1736 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1737 = or(_T_1736, reset) @[CoreplexNetwork.scala 35:13] + node _T_1739 = eq(_T_1737, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1739 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1741 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1742 = or(_T_1741, reset) @[CoreplexNetwork.scala 35:13] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1744 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1746 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 35:13] + when _T_1746 : @[CoreplexNetwork.scala 35:13] + node _T_1747 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1749 = eq(_T_1747, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1749 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1750 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1752 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1753 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1755 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1757 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1758 = or(_T_1757, reset) @[CoreplexNetwork.scala 35:13] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1760 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1762 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1763 = or(_T_1762, reset) @[CoreplexNetwork.scala 35:13] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1765 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1767 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 35:13] + when _T_1767 : @[CoreplexNetwork.scala 35:13] + node _T_1768 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1770 = eq(_T_1768, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1770 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1771 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1773 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1774 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1776 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1778 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1779 = or(_T_1778, reset) @[CoreplexNetwork.scala 35:13] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1781 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1783 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1784 = or(_T_1783, reset) @[CoreplexNetwork.scala 35:13] + node _T_1786 = eq(_T_1784, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1786 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1788 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1788 : @[CoreplexNetwork.scala 35:13] + node _T_1789 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1791 = eq(_T_1789, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1791 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1792 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1794 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1795 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1797 = eq(_T_1795, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1797 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1799 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1800 = or(_T_1799, reset) @[CoreplexNetwork.scala 35:13] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1802 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1804 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 35:13] + when _T_1804 : @[CoreplexNetwork.scala 35:13] + node _T_1805 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1807 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1808 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1810 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1811 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1813 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1815 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1816 = or(_T_1815, reset) @[CoreplexNetwork.scala 35:13] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1818 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1820 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 35:13] + when _T_1820 : @[CoreplexNetwork.scala 35:13] + node _T_1821 = or(_T_1708, reset) @[CoreplexNetwork.scala 35:13] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1823 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1824 = or(_T_1716, reset) @[CoreplexNetwork.scala 35:13] + node _T_1826 = eq(_T_1824, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1826 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1827 = or(_T_1718, reset) @[CoreplexNetwork.scala 35:13] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1829 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1831 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1832 = or(_T_1831, reset) @[CoreplexNetwork.scala 35:13] + node _T_1834 = eq(_T_1832, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1834 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1836 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1837 = or(_T_1836, reset) @[CoreplexNetwork.scala 35:13] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1839 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + when io.in[0].e.valid : @[CoreplexNetwork.scala 35:13] + node _T_1841 = lt(io.in[0].e.bits.sink, UInt<2>("h03")) @[CoreplexNetwork.scala 35:13] + node _T_1842 = or(_T_1841, reset) @[CoreplexNetwork.scala 35:13] + node _T_1844 = eq(_T_1842, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1844 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1845 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1847 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1848 = dshl(_T_1847, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1849 = bits(_T_1848, 5, 0) @[package.scala 19:76] + node _T_1850 = not(_T_1849) @[package.scala 19:40] + node _T_1851 = shr(_T_1850, 3) @[Edges.scala 198:59] + node _T_1852 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1854 = eq(_T_1852, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1856 = mux(_T_1854, _T_1851, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1858 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1860 = sub(_T_1858, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1861 = asUInt(_T_1860) @[Edges.scala 208:28] + node _T_1862 = tail(_T_1861, 1) @[Edges.scala 208:28] + node _T_1864 = eq(_T_1858, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1866 = eq(_T_1858, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1868 = eq(_T_1856, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1869 = or(_T_1866, _T_1868) @[Edges.scala 210:37] + node _T_1870 = and(_T_1869, _T_1845) @[Edges.scala 211:22] + node _T_1871 = not(_T_1862) @[Edges.scala 212:27] + node _T_1872 = and(_T_1856, _T_1871) @[Edges.scala 212:25] + when _T_1845 : @[Edges.scala 213:17] + node _T_1873 = mux(_T_1864, _T_1856, _T_1862) @[Edges.scala 214:21] + _T_1858 <= _T_1873 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1875 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1877 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1879 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1881 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1883 : UInt, clock @[CoreplexNetwork.scala 35:13] + node _T_1885 = eq(_T_1864, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1886 = and(io.in[0].a.valid, _T_1885) @[CoreplexNetwork.scala 35:13] + when _T_1886 : @[CoreplexNetwork.scala 35:13] + node _T_1887 = eq(io.in[0].a.bits.opcode, _T_1875) @[CoreplexNetwork.scala 35:13] + node _T_1888 = or(_T_1887, reset) @[CoreplexNetwork.scala 35:13] + node _T_1890 = eq(_T_1888, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1890 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1891 = eq(io.in[0].a.bits.param, _T_1877) @[CoreplexNetwork.scala 35:13] + node _T_1892 = or(_T_1891, reset) @[CoreplexNetwork.scala 35:13] + node _T_1894 = eq(_T_1892, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1894 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1895 = eq(io.in[0].a.bits.size, _T_1879) @[CoreplexNetwork.scala 35:13] + node _T_1896 = or(_T_1895, reset) @[CoreplexNetwork.scala 35:13] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1898 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1899 = eq(io.in[0].a.bits.source, _T_1881) @[CoreplexNetwork.scala 35:13] + node _T_1900 = or(_T_1899, reset) @[CoreplexNetwork.scala 35:13] + node _T_1902 = eq(_T_1900, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1902 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1903 = eq(io.in[0].a.bits.address, _T_1883) @[CoreplexNetwork.scala 35:13] + node _T_1904 = or(_T_1903, reset) @[CoreplexNetwork.scala 35:13] + node _T_1906 = eq(_T_1904, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1906 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1907 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1908 = and(_T_1907, _T_1864) @[CoreplexNetwork.scala 35:13] + when _T_1908 : @[CoreplexNetwork.scala 35:13] + _T_1875 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 35:13] + _T_1877 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 35:13] + _T_1879 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 35:13] + _T_1881 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 35:13] + _T_1883 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1909 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1911 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1912 = dshl(_T_1911, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1913 = bits(_T_1912, 5, 0) @[package.scala 19:76] + node _T_1914 = not(_T_1913) @[package.scala 19:40] + node _T_1915 = shr(_T_1914, 3) @[Edges.scala 198:59] + node _T_1916 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1918 = eq(_T_1916, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1921 = mux(UInt<1>("h00"), _T_1915, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1923 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1925 = sub(_T_1923, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1926 = asUInt(_T_1925) @[Edges.scala 208:28] + node _T_1927 = tail(_T_1926, 1) @[Edges.scala 208:28] + node _T_1929 = eq(_T_1923, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1931 = eq(_T_1923, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1933 = eq(_T_1921, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1934 = or(_T_1931, _T_1933) @[Edges.scala 210:37] + node _T_1935 = and(_T_1934, _T_1909) @[Edges.scala 211:22] + node _T_1936 = not(_T_1927) @[Edges.scala 212:27] + node _T_1937 = and(_T_1921, _T_1936) @[Edges.scala 212:25] + when _T_1909 : @[Edges.scala 213:17] + node _T_1938 = mux(_T_1929, _T_1921, _T_1927) @[Edges.scala 214:21] + _T_1923 <= _T_1938 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1940 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1942 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1944 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1946 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_1948 : UInt, clock @[CoreplexNetwork.scala 35:13] + node _T_1950 = eq(_T_1929, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_1951 = and(io.in[0].b.valid, _T_1950) @[CoreplexNetwork.scala 35:13] + when _T_1951 : @[CoreplexNetwork.scala 35:13] + node _T_1952 = eq(io.in[0].b.bits.opcode, _T_1940) @[CoreplexNetwork.scala 35:13] + node _T_1953 = or(_T_1952, reset) @[CoreplexNetwork.scala 35:13] + node _T_1955 = eq(_T_1953, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1955 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1956 = eq(io.in[0].b.bits.param, _T_1942) @[CoreplexNetwork.scala 35:13] + node _T_1957 = or(_T_1956, reset) @[CoreplexNetwork.scala 35:13] + node _T_1959 = eq(_T_1957, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1959 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1960 = eq(io.in[0].b.bits.size, _T_1944) @[CoreplexNetwork.scala 35:13] + node _T_1961 = or(_T_1960, reset) @[CoreplexNetwork.scala 35:13] + node _T_1963 = eq(_T_1961, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1963 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1964 = eq(io.in[0].b.bits.source, _T_1946) @[CoreplexNetwork.scala 35:13] + node _T_1965 = or(_T_1964, reset) @[CoreplexNetwork.scala 35:13] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1967 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1968 = eq(io.in[0].b.bits.address, _T_1948) @[CoreplexNetwork.scala 35:13] + node _T_1969 = or(_T_1968, reset) @[CoreplexNetwork.scala 35:13] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_1971 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1972 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1973 = and(_T_1972, _T_1929) @[CoreplexNetwork.scala 35:13] + when _T_1973 : @[CoreplexNetwork.scala 35:13] + _T_1940 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 35:13] + _T_1942 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 35:13] + _T_1944 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 35:13] + _T_1946 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 35:13] + _T_1948 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_1974 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1976 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1977 = dshl(_T_1976, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1978 = bits(_T_1977, 5, 0) @[package.scala 19:76] + node _T_1979 = not(_T_1978) @[package.scala 19:40] + node _T_1980 = shr(_T_1979, 3) @[Edges.scala 198:59] + node _T_1981 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1983 = mux(_T_1981, _T_1980, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1985 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1987 = sub(_T_1985, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1988 = asUInt(_T_1987) @[Edges.scala 208:28] + node _T_1989 = tail(_T_1988, 1) @[Edges.scala 208:28] + node _T_1991 = eq(_T_1985, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1993 = eq(_T_1985, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1995 = eq(_T_1983, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1996 = or(_T_1993, _T_1995) @[Edges.scala 210:37] + node _T_1997 = and(_T_1996, _T_1974) @[Edges.scala 211:22] + node _T_1998 = not(_T_1989) @[Edges.scala 212:27] + node _T_1999 = and(_T_1983, _T_1998) @[Edges.scala 212:25] + when _T_1974 : @[Edges.scala 213:17] + node _T_2000 = mux(_T_1991, _T_1983, _T_1989) @[Edges.scala 214:21] + _T_1985 <= _T_2000 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2002 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2004 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2006 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2008 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2010 : UInt, clock @[CoreplexNetwork.scala 35:13] + node _T_2012 = eq(_T_1991, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_2013 = and(io.in[0].c.valid, _T_2012) @[CoreplexNetwork.scala 35:13] + when _T_2013 : @[CoreplexNetwork.scala 35:13] + node _T_2014 = eq(io.in[0].c.bits.opcode, _T_2002) @[CoreplexNetwork.scala 35:13] + node _T_2015 = or(_T_2014, reset) @[CoreplexNetwork.scala 35:13] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2017 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2018 = eq(io.in[0].c.bits.param, _T_2004) @[CoreplexNetwork.scala 35:13] + node _T_2019 = or(_T_2018, reset) @[CoreplexNetwork.scala 35:13] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2021 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2022 = eq(io.in[0].c.bits.size, _T_2006) @[CoreplexNetwork.scala 35:13] + node _T_2023 = or(_T_2022, reset) @[CoreplexNetwork.scala 35:13] + node _T_2025 = eq(_T_2023, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2025 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2026 = eq(io.in[0].c.bits.source, _T_2008) @[CoreplexNetwork.scala 35:13] + node _T_2027 = or(_T_2026, reset) @[CoreplexNetwork.scala 35:13] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2029 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2030 = eq(io.in[0].c.bits.address, _T_2010) @[CoreplexNetwork.scala 35:13] + node _T_2031 = or(_T_2030, reset) @[CoreplexNetwork.scala 35:13] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2033 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2034 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2035 = and(_T_2034, _T_1991) @[CoreplexNetwork.scala 35:13] + when _T_2035 : @[CoreplexNetwork.scala 35:13] + _T_2002 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 35:13] + _T_2004 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 35:13] + _T_2006 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 35:13] + _T_2008 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 35:13] + _T_2010 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2036 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2038 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2039 = dshl(_T_2038, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2040 = bits(_T_2039, 5, 0) @[package.scala 19:76] + node _T_2041 = not(_T_2040) @[package.scala 19:40] + node _T_2042 = shr(_T_2041, 3) @[Edges.scala 198:59] + node _T_2043 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2045 = mux(_T_2043, _T_2042, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2047 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2049 = sub(_T_2047, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2050 = asUInt(_T_2049) @[Edges.scala 208:28] + node _T_2051 = tail(_T_2050, 1) @[Edges.scala 208:28] + node _T_2053 = eq(_T_2047, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2055 = eq(_T_2047, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2057 = eq(_T_2045, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2058 = or(_T_2055, _T_2057) @[Edges.scala 210:37] + node _T_2059 = and(_T_2058, _T_2036) @[Edges.scala 211:22] + node _T_2060 = not(_T_2051) @[Edges.scala 212:27] + node _T_2061 = and(_T_2045, _T_2060) @[Edges.scala 212:25] + when _T_2036 : @[Edges.scala 213:17] + node _T_2062 = mux(_T_2053, _T_2045, _T_2051) @[Edges.scala 214:21] + _T_2047 <= _T_2062 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2064 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2066 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2068 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2070 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2072 : UInt, clock @[CoreplexNetwork.scala 35:13] + reg _T_2074 : UInt, clock @[CoreplexNetwork.scala 35:13] + node _T_2076 = eq(_T_2053, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_2077 = and(io.in[0].d.valid, _T_2076) @[CoreplexNetwork.scala 35:13] + when _T_2077 : @[CoreplexNetwork.scala 35:13] + node _T_2078 = eq(io.in[0].d.bits.opcode, _T_2064) @[CoreplexNetwork.scala 35:13] + node _T_2079 = or(_T_2078, reset) @[CoreplexNetwork.scala 35:13] + node _T_2081 = eq(_T_2079, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2081 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2082 = eq(io.in[0].d.bits.param, _T_2066) @[CoreplexNetwork.scala 35:13] + node _T_2083 = or(_T_2082, reset) @[CoreplexNetwork.scala 35:13] + node _T_2085 = eq(_T_2083, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2085 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2086 = eq(io.in[0].d.bits.size, _T_2068) @[CoreplexNetwork.scala 35:13] + node _T_2087 = or(_T_2086, reset) @[CoreplexNetwork.scala 35:13] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2089 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2090 = eq(io.in[0].d.bits.source, _T_2070) @[CoreplexNetwork.scala 35:13] + node _T_2091 = or(_T_2090, reset) @[CoreplexNetwork.scala 35:13] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2093 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2094 = eq(io.in[0].d.bits.sink, _T_2072) @[CoreplexNetwork.scala 35:13] + node _T_2095 = or(_T_2094, reset) @[CoreplexNetwork.scala 35:13] + node _T_2097 = eq(_T_2095, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2097 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2098 = eq(io.in[0].d.bits.addr_lo, _T_2074) @[CoreplexNetwork.scala 35:13] + node _T_2099 = or(_T_2098, reset) @[CoreplexNetwork.scala 35:13] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2101 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2102 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2103 = and(_T_2102, _T_2053) @[CoreplexNetwork.scala 35:13] + when _T_2103 : @[CoreplexNetwork.scala 35:13] + _T_2064 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 35:13] + _T_2066 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 35:13] + _T_2068 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 35:13] + _T_2070 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 35:13] + _T_2072 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 35:13] + _T_2074 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + reg _T_2105 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2106 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2108 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2109 = dshl(_T_2108, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2110 = bits(_T_2109, 5, 0) @[package.scala 19:76] + node _T_2111 = not(_T_2110) @[package.scala 19:40] + node _T_2112 = shr(_T_2111, 3) @[Edges.scala 198:59] + node _T_2113 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2115 = eq(_T_2113, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2117 = mux(_T_2115, _T_2112, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2119 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2121 = sub(_T_2119, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2122 = asUInt(_T_2121) @[Edges.scala 208:28] + node _T_2123 = tail(_T_2122, 1) @[Edges.scala 208:28] + node _T_2125 = eq(_T_2119, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2127 = eq(_T_2119, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2129 = eq(_T_2117, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2130 = or(_T_2127, _T_2129) @[Edges.scala 210:37] + node _T_2131 = and(_T_2130, _T_2106) @[Edges.scala 211:22] + node _T_2132 = not(_T_2123) @[Edges.scala 212:27] + node _T_2133 = and(_T_2117, _T_2132) @[Edges.scala 212:25] + when _T_2106 : @[Edges.scala 213:17] + node _T_2134 = mux(_T_2125, _T_2117, _T_2123) @[Edges.scala 214:21] + _T_2119 <= _T_2134 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2135 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2137 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2138 = dshl(_T_2137, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2139 = bits(_T_2138, 5, 0) @[package.scala 19:76] + node _T_2140 = not(_T_2139) @[package.scala 19:40] + node _T_2141 = shr(_T_2140, 3) @[Edges.scala 198:59] + node _T_2142 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2144 = mux(_T_2142, _T_2141, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2146 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2148 = sub(_T_2146, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2149 = asUInt(_T_2148) @[Edges.scala 208:28] + node _T_2150 = tail(_T_2149, 1) @[Edges.scala 208:28] + node _T_2152 = eq(_T_2146, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2154 = eq(_T_2146, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2156 = eq(_T_2144, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2157 = or(_T_2154, _T_2156) @[Edges.scala 210:37] + node _T_2158 = and(_T_2157, _T_2135) @[Edges.scala 211:22] + node _T_2159 = not(_T_2150) @[Edges.scala 212:27] + node _T_2160 = and(_T_2144, _T_2159) @[Edges.scala 212:25] + when _T_2135 : @[Edges.scala 213:17] + node _T_2161 = mux(_T_2152, _T_2144, _T_2150) @[Edges.scala 214:21] + _T_2146 <= _T_2161 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_2163 : UInt<6> + _T_2163 is invalid + _T_2163 <= UInt<6>("h00") + node _T_2164 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2164 : @[CoreplexNetwork.scala 35:13] + when _T_2130 : @[CoreplexNetwork.scala 35:13] + node _T_2166 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2163 <= _T_2166 @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2167 = dshr(_T_2105, io.in[0].a.bits.source) @[CoreplexNetwork.scala 35:13] + node _T_2168 = bits(_T_2167, 0, 0) @[CoreplexNetwork.scala 35:13] + node _T_2170 = eq(_T_2168, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + node _T_2171 = or(_T_2170, reset) @[CoreplexNetwork.scala 35:13] + node _T_2173 = eq(_T_2171, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2173 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + wire _T_2175 : UInt<6> + _T_2175 is invalid + _T_2175 <= UInt<6>("h00") + node _T_2176 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2178 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 35:13] + node _T_2179 = and(_T_2176, _T_2178) @[CoreplexNetwork.scala 35:13] + when _T_2179 : @[CoreplexNetwork.scala 35:13] + when _T_2157 : @[CoreplexNetwork.scala 35:13] + node _T_2181 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2175 <= _T_2181 @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2182 = or(_T_2163, _T_2105) @[CoreplexNetwork.scala 35:13] + node _T_2183 = dshr(_T_2182, io.in[0].d.bits.source) @[CoreplexNetwork.scala 35:13] + node _T_2184 = bits(_T_2183, 0, 0) @[CoreplexNetwork.scala 35:13] + node _T_2185 = or(_T_2184, reset) @[CoreplexNetwork.scala 35:13] + node _T_2187 = eq(_T_2185, UInt<1>("h00")) @[CoreplexNetwork.scala 35:13] + when _T_2187 : @[CoreplexNetwork.scala 35:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:35:13)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 35:13] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + skip @[CoreplexNetwork.scala 35:13] + node _T_2188 = or(_T_2105, _T_2163) @[CoreplexNetwork.scala 35:13] + node _T_2189 = not(_T_2175) @[CoreplexNetwork.scala 35:13] + node _T_2190 = and(_T_2188, _T_2189) @[CoreplexNetwork.scala 35:13] + _T_2105 <= _T_2190 @[CoreplexNetwork.scala 35:13] - module BroadcastAcquireTracker_28 : - input clk : Clock + module TLWidthWidget_socBus : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<2>("h03") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<2>("h03") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<2>("h03") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<2>("h03") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<2>("h03") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<2>("h03") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<2>("h03") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + io.out.0.a <- io.in.0.a @[WidthWidget.scala 131:13] + io.in.0.d <- io.out.0.d @[WidthWidget.scala 131:13] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_19 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 42:36] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 42:36] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_608 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 7, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + when _T_708 : @[CoreplexNetwork.scala 42:36] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_728 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_729 = and(_T_711, _T_728) @[Parameters.scala 132:56] + node _T_731 = or(UInt<1>("h00"), _T_729) @[Parameters.scala 134:30] + node _T_732 = or(_T_731, reset) @[CoreplexNetwork.scala 42:36] + node _T_734 = eq(_T_732, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_734 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_735 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_737 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_739 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_740 = or(_T_739, reset) @[CoreplexNetwork.scala 42:36] + node _T_742 = eq(_T_740, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_742 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_743 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_745 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_747 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_748 = or(_T_747, reset) @[CoreplexNetwork.scala 42:36] + node _T_750 = eq(_T_748, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_750 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_751 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 42:36] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_754 = or(_T_753, reset) @[CoreplexNetwork.scala 42:36] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_756 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_758 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 42:36] + when _T_758 : @[CoreplexNetwork.scala 42:36] + node _T_761 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_763 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_764 = and(_T_761, _T_763) @[Parameters.scala 63:37] + node _T_765 = or(UInt<1>("h00"), _T_764) @[Parameters.scala 132:31] + node _T_767 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_768 = cvt(_T_767) @[Parameters.scala 117:49] + node _T_770 = and(_T_768, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_771 = asSInt(_T_770) @[Parameters.scala 117:52] + node _T_773 = eq(_T_771, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_774 = and(_T_765, _T_773) @[Parameters.scala 132:56] + node _T_777 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_779 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_780 = and(_T_777, _T_779) @[Parameters.scala 63:37] + node _T_781 = or(UInt<1>("h00"), _T_780) @[Parameters.scala 132:31] + node _T_783 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_784 = cvt(_T_783) @[Parameters.scala 117:49] + node _T_786 = and(_T_784, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_787 = asSInt(_T_786) @[Parameters.scala 117:52] + node _T_789 = eq(_T_787, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_790 = and(_T_781, _T_789) @[Parameters.scala 132:56] + node _T_792 = or(UInt<1>("h00"), _T_774) @[Parameters.scala 134:30] + node _T_793 = or(_T_792, _T_790) @[Parameters.scala 134:30] + node _T_794 = or(_T_793, reset) @[CoreplexNetwork.scala 42:36] + node _T_796 = eq(_T_794, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_796 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_797 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_799 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_800 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_802 = eq(_T_800, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_802 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_804 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_805 = or(_T_804, reset) @[CoreplexNetwork.scala 42:36] + node _T_807 = eq(_T_805, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_807 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_808 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 42:36] + node _T_809 = or(_T_808, reset) @[CoreplexNetwork.scala 42:36] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_811 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_813 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_813 : @[CoreplexNetwork.scala 42:36] + node _T_816 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_818 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_819 = and(_T_816, _T_818) @[Parameters.scala 63:37] + node _T_820 = or(UInt<1>("h00"), _T_819) @[Parameters.scala 132:31] + node _T_822 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_823 = cvt(_T_822) @[Parameters.scala 117:49] + node _T_825 = and(_T_823, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_826 = asSInt(_T_825) @[Parameters.scala 117:52] + node _T_828 = eq(_T_826, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_829 = and(_T_820, _T_828) @[Parameters.scala 132:56] + node _T_832 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, _T_841) @[Parameters.scala 134:30] + node _T_845 = or(_T_844, reset) @[CoreplexNetwork.scala 42:36] + node _T_847 = eq(_T_845, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_847 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_848 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_850 = eq(_T_848, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_850 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_851 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_853 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_855 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_856 = or(_T_855, reset) @[CoreplexNetwork.scala 42:36] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_858 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_859 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 42:36] + node _T_860 = or(_T_859, reset) @[CoreplexNetwork.scala 42:36] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_862 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_864 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 42:36] + when _T_864 : @[CoreplexNetwork.scala 42:36] + node _T_867 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_869 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_870 = and(_T_867, _T_869) @[Parameters.scala 63:37] + node _T_871 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 132:31] + node _T_873 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_874 = cvt(_T_873) @[Parameters.scala 117:49] + node _T_876 = and(_T_874, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_877 = asSInt(_T_876) @[Parameters.scala 117:52] + node _T_879 = eq(_T_877, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_880 = and(_T_871, _T_879) @[Parameters.scala 132:56] + node _T_883 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_885 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_892 = and(_T_883, _T_891) @[Parameters.scala 132:56] + node _T_894 = or(UInt<1>("h00"), _T_880) @[Parameters.scala 134:30] + node _T_895 = or(_T_894, _T_892) @[Parameters.scala 134:30] + node _T_896 = or(_T_895, reset) @[CoreplexNetwork.scala 42:36] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_898 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_899 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_901 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_902 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_904 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_906 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_907 = or(_T_906, reset) @[CoreplexNetwork.scala 42:36] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_909 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_910 = not(_T_706) @[CoreplexNetwork.scala 42:36] + node _T_911 = and(io.in[0].a.bits.mask, _T_910) @[CoreplexNetwork.scala 42:36] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_914 = or(_T_913, reset) @[CoreplexNetwork.scala 42:36] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_916 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_918 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + when _T_918 : @[CoreplexNetwork.scala 42:36] + node _T_921 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_923 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_924 = cvt(_T_923) @[Parameters.scala 117:49] + node _T_926 = and(_T_924, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_927 = asSInt(_T_926) @[Parameters.scala 117:52] + node _T_929 = eq(_T_927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = or(_T_929, _T_937) @[Parameters.scala 133:42] + node _T_939 = and(_T_921, _T_938) @[Parameters.scala 132:56] + node _T_941 = or(UInt<1>("h00"), _T_939) @[Parameters.scala 134:30] + node _T_942 = or(_T_941, reset) @[CoreplexNetwork.scala 42:36] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_944 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_945 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_947 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_948 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_950 = eq(_T_948, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_950 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_952 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_953 = or(_T_952, reset) @[CoreplexNetwork.scala 42:36] + node _T_955 = eq(_T_953, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_955 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_956 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 42:36] + node _T_957 = or(_T_956, reset) @[CoreplexNetwork.scala 42:36] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_959 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_961 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + when _T_961 : @[CoreplexNetwork.scala 42:36] + node _T_964 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_966 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_967 = cvt(_T_966) @[Parameters.scala 117:49] + node _T_969 = and(_T_967, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_970 = asSInt(_T_969) @[Parameters.scala 117:52] + node _T_972 = eq(_T_970, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_975 = cvt(_T_974) @[Parameters.scala 117:49] + node _T_977 = and(_T_975, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_978 = asSInt(_T_977) @[Parameters.scala 117:52] + node _T_980 = eq(_T_978, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = or(_T_972, _T_980) @[Parameters.scala 133:42] + node _T_982 = and(_T_964, _T_981) @[Parameters.scala 132:56] + node _T_984 = or(UInt<1>("h00"), _T_982) @[Parameters.scala 134:30] + node _T_985 = or(_T_984, reset) @[CoreplexNetwork.scala 42:36] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_987 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_988 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_990 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_991 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_993 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_995 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_996 = or(_T_995, reset) @[CoreplexNetwork.scala 42:36] + node _T_998 = eq(_T_996, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_998 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_999 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 42:36] + node _T_1000 = or(_T_999, reset) @[CoreplexNetwork.scala 42:36] + node _T_1002 = eq(_T_1000, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1002 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1004 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 42:36] + when _T_1004 : @[CoreplexNetwork.scala 42:36] + node _T_1007 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1009 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1010 = cvt(_T_1009) @[Parameters.scala 117:49] + node _T_1012 = and(_T_1010, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1013 = asSInt(_T_1012) @[Parameters.scala 117:52] + node _T_1015 = eq(_T_1013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1018 = cvt(_T_1017) @[Parameters.scala 117:49] + node _T_1020 = and(_T_1018, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1021 = asSInt(_T_1020) @[Parameters.scala 117:52] + node _T_1023 = eq(_T_1021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = or(_T_1015, _T_1023) @[Parameters.scala 133:42] + node _T_1025 = and(_T_1007, _T_1024) @[Parameters.scala 132:56] + node _T_1027 = or(UInt<1>("h00"), _T_1025) @[Parameters.scala 134:30] + node _T_1028 = or(_T_1027, reset) @[CoreplexNetwork.scala 42:36] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1030 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1031 = or(_T_630, reset) @[CoreplexNetwork.scala 42:36] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1033 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1034 = or(_T_638, reset) @[CoreplexNetwork.scala 42:36] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1036 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 42:36] + node _T_1038 = or(_T_1037, reset) @[CoreplexNetwork.scala 42:36] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1040 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + when io.in[0].b.valid : @[CoreplexNetwork.scala 42:36] + node _T_1042 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1043 = or(_T_1042, reset) @[CoreplexNetwork.scala 42:36] + node _T_1045 = eq(_T_1043, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1045 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1047 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1064 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1064 is invalid @[Parameters.scala 110:36] + _T_1064[0] <= _T_1053 @[Parameters.scala 110:36] + _T_1064[1] <= _T_1061 @[Parameters.scala 110:36] + node _T_1069 = or(_T_1064[0], _T_1064[1]) @[Parameters.scala 119:64] + node _T_1071 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1072 = dshl(_T_1071, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1073 = bits(_T_1072, 7, 0) @[package.scala 19:76] + node _T_1074 = not(_T_1073) @[package.scala 19:40] + node _T_1075 = and(io.in[0].b.bits.address, _T_1074) @[Edges.scala 17:16] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1079 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1080 = dshl(UInt<1>("h01"), _T_1079) @[OneHot.scala 49:12] + node _T_1081 = bits(_T_1080, 2, 0) @[OneHot.scala 49:37] + node _T_1083 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1085 = bits(_T_1081, 2, 2) @[package.scala 44:26] + node _T_1086 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[package.scala 46:20] + node _T_1089 = and(UInt<1>("h01"), _T_1088) @[package.scala 49:27] + node _T_1090 = and(_T_1085, _T_1089) @[package.scala 50:38] + node _T_1091 = or(_T_1083, _T_1090) @[package.scala 50:29] + node _T_1092 = and(UInt<1>("h01"), _T_1086) @[package.scala 49:27] + node _T_1093 = and(_T_1085, _T_1092) @[package.scala 50:38] + node _T_1094 = or(_T_1083, _T_1093) @[package.scala 50:29] + node _T_1095 = bits(_T_1081, 1, 1) @[package.scala 44:26] + node _T_1096 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1098 = eq(_T_1096, UInt<1>("h00")) @[package.scala 46:20] + node _T_1099 = and(_T_1089, _T_1098) @[package.scala 49:27] + node _T_1100 = and(_T_1095, _T_1099) @[package.scala 50:38] + node _T_1101 = or(_T_1091, _T_1100) @[package.scala 50:29] + node _T_1102 = and(_T_1089, _T_1096) @[package.scala 49:27] + node _T_1103 = and(_T_1095, _T_1102) @[package.scala 50:38] + node _T_1104 = or(_T_1091, _T_1103) @[package.scala 50:29] + node _T_1105 = and(_T_1092, _T_1098) @[package.scala 49:27] + node _T_1106 = and(_T_1095, _T_1105) @[package.scala 50:38] + node _T_1107 = or(_T_1094, _T_1106) @[package.scala 50:29] + node _T_1108 = and(_T_1092, _T_1096) @[package.scala 49:27] + node _T_1109 = and(_T_1095, _T_1108) @[package.scala 50:38] + node _T_1110 = or(_T_1094, _T_1109) @[package.scala 50:29] + node _T_1111 = bits(_T_1081, 0, 0) @[package.scala 44:26] + node _T_1112 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[package.scala 46:20] + node _T_1115 = and(_T_1099, _T_1114) @[package.scala 49:27] + node _T_1116 = and(_T_1111, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1101, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1099, _T_1112) @[package.scala 49:27] + node _T_1119 = and(_T_1111, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1101, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1102, _T_1114) @[package.scala 49:27] + node _T_1122 = and(_T_1111, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1104, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1102, _T_1112) @[package.scala 49:27] + node _T_1125 = and(_T_1111, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1104, _T_1125) @[package.scala 50:29] + node _T_1127 = and(_T_1105, _T_1114) @[package.scala 49:27] + node _T_1128 = and(_T_1111, _T_1127) @[package.scala 50:38] + node _T_1129 = or(_T_1107, _T_1128) @[package.scala 50:29] + node _T_1130 = and(_T_1105, _T_1112) @[package.scala 49:27] + node _T_1131 = and(_T_1111, _T_1130) @[package.scala 50:38] + node _T_1132 = or(_T_1107, _T_1131) @[package.scala 50:29] + node _T_1133 = and(_T_1108, _T_1114) @[package.scala 49:27] + node _T_1134 = and(_T_1111, _T_1133) @[package.scala 50:38] + node _T_1135 = or(_T_1110, _T_1134) @[package.scala 50:29] + node _T_1136 = and(_T_1108, _T_1112) @[package.scala 49:27] + node _T_1137 = and(_T_1111, _T_1136) @[package.scala 50:38] + node _T_1138 = or(_T_1110, _T_1137) @[package.scala 50:29] + node _T_1139 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + when _T_1147 : @[CoreplexNetwork.scala 42:36] + node _T_1149 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1150 = not(_T_1149) @[Parameters.scala 37:9] + node _T_1152 = or(_T_1150, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1153 = not(_T_1152) @[Parameters.scala 37:7] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1157 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1159 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1162 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1162 is invalid @[Parameters.scala 228:27] + _T_1162[0] <= _T_1155 @[Parameters.scala 228:27] + _T_1162[1] <= _T_1157 @[Parameters.scala 228:27] + _T_1162[2] <= _T_1159 @[Parameters.scala 228:27] + node _T_1170 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1172 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1173 = and(_T_1170, _T_1172) @[Parameters.scala 63:37] + node _T_1176 = mux(_T_1162[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1178 = mux(_T_1162[1], _T_1173, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1180 = mux(_T_1162[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1182 = or(_T_1176, _T_1178) @[Mux.scala 19:72] + node _T_1183 = or(_T_1182, _T_1180) @[Mux.scala 19:72] + wire _T_1185 : UInt<1> @[Mux.scala 19:72] + _T_1185 is invalid @[Mux.scala 19:72] + _T_1185 <= _T_1183 @[Mux.scala 19:72] + node _T_1186 = or(_T_1185, reset) @[CoreplexNetwork.scala 42:36] + node _T_1188 = eq(_T_1186, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1188 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1189 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1191 = eq(_T_1189, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1191 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1193 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1194 = or(_T_1193, reset) @[CoreplexNetwork.scala 42:36] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1196 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1197 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1199 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1202 = or(_T_1201, reset) @[CoreplexNetwork.scala 42:36] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1204 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1205 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 42:36] + node _T_1207 = eq(_T_1205, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1208 = or(_T_1207, reset) @[CoreplexNetwork.scala 42:36] + node _T_1210 = eq(_T_1208, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1210 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1212 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 42:36] + when _T_1212 : @[CoreplexNetwork.scala 42:36] + node _T_1214 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1216 = eq(_T_1214, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1216 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1217 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1219 = eq(_T_1217, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1219 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1220 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1222 = eq(_T_1220, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1222 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1224 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1225 = or(_T_1224, reset) @[CoreplexNetwork.scala 42:36] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1227 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1228 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1229 = or(_T_1228, reset) @[CoreplexNetwork.scala 42:36] + node _T_1231 = eq(_T_1229, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1231 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1233 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1233 : @[CoreplexNetwork.scala 42:36] + node _T_1235 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1237 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1238 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1240 = eq(_T_1238, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1240 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1241 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1243 = eq(_T_1241, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1243 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1245 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1246 = or(_T_1245, reset) @[CoreplexNetwork.scala 42:36] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1248 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1249 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1250 = or(_T_1249, reset) @[CoreplexNetwork.scala 42:36] + node _T_1252 = eq(_T_1250, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1252 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1254 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 42:36] + when _T_1254 : @[CoreplexNetwork.scala 42:36] + node _T_1256 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1258 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1259 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1261 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1262 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1264 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1266 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1267 = or(_T_1266, reset) @[CoreplexNetwork.scala 42:36] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1269 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1270 = not(_T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1271 = and(io.in[0].b.bits.mask, _T_1270) @[CoreplexNetwork.scala 42:36] + node _T_1273 = eq(_T_1271, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1274 = or(_T_1273, reset) @[CoreplexNetwork.scala 42:36] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1276 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1278 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + when _T_1278 : @[CoreplexNetwork.scala 42:36] + node _T_1280 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1282 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1283 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1285 = eq(_T_1283, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1285 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1286 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1288 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1290 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1291 = or(_T_1290, reset) @[CoreplexNetwork.scala 42:36] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1293 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1294 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1295 = or(_T_1294, reset) @[CoreplexNetwork.scala 42:36] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1297 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1299 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + when _T_1299 : @[CoreplexNetwork.scala 42:36] + node _T_1301 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1303 = eq(_T_1301, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1303 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1304 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1306 = eq(_T_1304, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1306 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1307 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1309 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1311 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1312 = or(_T_1311, reset) @[CoreplexNetwork.scala 42:36] + node _T_1314 = eq(_T_1312, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1314 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1315 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1316 = or(_T_1315, reset) @[CoreplexNetwork.scala 42:36] + node _T_1318 = eq(_T_1316, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1318 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1320 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 42:36] + when _T_1320 : @[CoreplexNetwork.scala 42:36] + node _T_1322 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 42:36] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1324 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1325 = or(_T_1069, reset) @[CoreplexNetwork.scala 42:36] + node _T_1327 = eq(_T_1325, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1327 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1328 = or(_T_1077, reset) @[CoreplexNetwork.scala 42:36] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1330 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1331 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 42:36] + node _T_1332 = or(_T_1331, reset) @[CoreplexNetwork.scala 42:36] + node _T_1334 = eq(_T_1332, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1334 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + when io.in[0].c.valid : @[CoreplexNetwork.scala 42:36] + node _T_1336 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1337 = or(_T_1336, reset) @[CoreplexNetwork.scala 42:36] + node _T_1339 = eq(_T_1337, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1339 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1341 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1342 = not(_T_1341) @[Parameters.scala 37:9] + node _T_1344 = or(_T_1342, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1345 = not(_T_1344) @[Parameters.scala 37:7] + node _T_1347 = eq(_T_1345, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1349 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1351 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1354 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1354 is invalid @[Parameters.scala 228:27] + _T_1354[0] <= _T_1347 @[Parameters.scala 228:27] + _T_1354[1] <= _T_1349 @[Parameters.scala 228:27] + _T_1354[2] <= _T_1351 @[Parameters.scala 228:27] + node _T_1360 = or(_T_1354[0], _T_1354[1]) @[Parameters.scala 229:46] + node _T_1361 = or(_T_1360, _T_1354[2]) @[Parameters.scala 229:46] + node _T_1363 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1364 = dshl(_T_1363, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1365 = bits(_T_1364, 7, 0) @[package.scala 19:76] + node _T_1366 = not(_T_1365) @[package.scala 19:40] + node _T_1367 = and(io.in[0].c.bits.address, _T_1366) @[Edges.scala 17:16] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1371 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1372 = cvt(_T_1371) @[Parameters.scala 117:49] + node _T_1374 = and(_T_1372, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1375 = asSInt(_T_1374) @[Parameters.scala 117:52] + node _T_1377 = eq(_T_1375, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1379 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1380 = cvt(_T_1379) @[Parameters.scala 117:49] + node _T_1382 = and(_T_1380, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1383 = asSInt(_T_1382) @[Parameters.scala 117:52] + node _T_1385 = eq(_T_1383, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1388 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1388 is invalid @[Parameters.scala 110:36] + _T_1388[0] <= _T_1377 @[Parameters.scala 110:36] + _T_1388[1] <= _T_1385 @[Parameters.scala 110:36] + node _T_1393 = or(_T_1388[0], _T_1388[1]) @[Parameters.scala 119:64] + node _T_1395 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 42:36] + when _T_1395 : @[CoreplexNetwork.scala 42:36] + node _T_1396 = or(_T_1393, reset) @[CoreplexNetwork.scala 42:36] + node _T_1398 = eq(_T_1396, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1398 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1399 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1401 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1403 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1404 = or(_T_1403, reset) @[CoreplexNetwork.scala 42:36] + node _T_1406 = eq(_T_1404, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1406 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1407 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1409 = eq(_T_1407, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1409 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1411 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1412 = or(_T_1411, reset) @[CoreplexNetwork.scala 42:36] + node _T_1414 = eq(_T_1412, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1414 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1416 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1417 = or(_T_1416, reset) @[CoreplexNetwork.scala 42:36] + node _T_1419 = eq(_T_1417, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1419 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1421 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 42:36] + when _T_1421 : @[CoreplexNetwork.scala 42:36] + node _T_1422 = or(_T_1393, reset) @[CoreplexNetwork.scala 42:36] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1424 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1425 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1427 = eq(_T_1425, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1427 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1429 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1430 = or(_T_1429, reset) @[CoreplexNetwork.scala 42:36] + node _T_1432 = eq(_T_1430, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1432 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1433 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1435 = eq(_T_1433, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1435 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1437 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1438 = or(_T_1437, reset) @[CoreplexNetwork.scala 42:36] + node _T_1440 = eq(_T_1438, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1440 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1442 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1443 = or(_T_1442, reset) @[CoreplexNetwork.scala 42:36] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1445 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1447 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + when _T_1447 : @[CoreplexNetwork.scala 42:36] + node _T_1450 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1452 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1453 = cvt(_T_1452) @[Parameters.scala 117:49] + node _T_1455 = and(_T_1453, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1456 = asSInt(_T_1455) @[Parameters.scala 117:52] + node _T_1458 = eq(_T_1456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1460 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1461 = cvt(_T_1460) @[Parameters.scala 117:49] + node _T_1463 = and(_T_1461, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1464 = asSInt(_T_1463) @[Parameters.scala 117:52] + node _T_1466 = eq(_T_1464, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1467 = or(_T_1458, _T_1466) @[Parameters.scala 133:42] + node _T_1468 = and(_T_1450, _T_1467) @[Parameters.scala 132:56] + node _T_1470 = or(UInt<1>("h00"), _T_1468) @[Parameters.scala 134:30] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 42:36] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1473 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1474 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1476 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1478 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 42:36] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1481 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1482 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1484 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1486 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1487 = or(_T_1486, reset) @[CoreplexNetwork.scala 42:36] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1489 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1491 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1492 = or(_T_1491, reset) @[CoreplexNetwork.scala 42:36] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1494 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 42:36] + when _T_1496 : @[CoreplexNetwork.scala 42:36] + node _T_1499 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1501 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1502 = cvt(_T_1501) @[Parameters.scala 117:49] + node _T_1504 = and(_T_1502, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1505 = asSInt(_T_1504) @[Parameters.scala 117:52] + node _T_1507 = eq(_T_1505, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1509 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1510 = cvt(_T_1509) @[Parameters.scala 117:49] + node _T_1512 = and(_T_1510, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1513 = asSInt(_T_1512) @[Parameters.scala 117:52] + node _T_1515 = eq(_T_1513, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1516 = or(_T_1507, _T_1515) @[Parameters.scala 133:42] + node _T_1517 = and(_T_1499, _T_1516) @[Parameters.scala 132:56] + node _T_1519 = or(UInt<1>("h00"), _T_1517) @[Parameters.scala 134:30] + node _T_1520 = or(_T_1519, reset) @[CoreplexNetwork.scala 42:36] + node _T_1522 = eq(_T_1520, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1522 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1523 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1525 = eq(_T_1523, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1525 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1527 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1528 = or(_T_1527, reset) @[CoreplexNetwork.scala 42:36] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1530 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1531 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1533 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1535 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1536 = or(_T_1535, reset) @[CoreplexNetwork.scala 42:36] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1538 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1540 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1541 = or(_T_1540, reset) @[CoreplexNetwork.scala 42:36] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1543 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1545 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1545 : @[CoreplexNetwork.scala 42:36] + node _T_1546 = or(_T_1393, reset) @[CoreplexNetwork.scala 42:36] + node _T_1548 = eq(_T_1546, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1548 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1549 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1551 = eq(_T_1549, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1551 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1552 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1554 = eq(_T_1552, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1554 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1556 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1557 = or(_T_1556, reset) @[CoreplexNetwork.scala 42:36] + node _T_1559 = eq(_T_1557, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1559 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1561 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 42:36] + when _T_1561 : @[CoreplexNetwork.scala 42:36] + node _T_1562 = or(_T_1393, reset) @[CoreplexNetwork.scala 42:36] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1564 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1565 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1567 = eq(_T_1565, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1567 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1568 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1570 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1572 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1573 = or(_T_1572, reset) @[CoreplexNetwork.scala 42:36] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1575 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1577 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + when _T_1577 : @[CoreplexNetwork.scala 42:36] + node _T_1578 = or(_T_1393, reset) @[CoreplexNetwork.scala 42:36] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1580 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1581 = or(_T_1361, reset) @[CoreplexNetwork.scala 42:36] + node _T_1583 = eq(_T_1581, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1583 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1584 = or(_T_1369, reset) @[CoreplexNetwork.scala 42:36] + node _T_1586 = eq(_T_1584, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1586 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1588 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1589 = or(_T_1588, reset) @[CoreplexNetwork.scala 42:36] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1591 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1593 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1594 = or(_T_1593, reset) @[CoreplexNetwork.scala 42:36] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1596 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + when io.in[0].d.valid : @[CoreplexNetwork.scala 42:36] + node _T_1598 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1599 = or(_T_1598, reset) @[CoreplexNetwork.scala 42:36] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1601 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1603 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1604 = not(_T_1603) @[Parameters.scala 37:9] + node _T_1606 = or(_T_1604, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1607 = not(_T_1606) @[Parameters.scala 37:7] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1611 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1613 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1616 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1616 is invalid @[Parameters.scala 228:27] + _T_1616[0] <= _T_1609 @[Parameters.scala 228:27] + _T_1616[1] <= _T_1611 @[Parameters.scala 228:27] + _T_1616[2] <= _T_1613 @[Parameters.scala 228:27] + node _T_1622 = or(_T_1616[0], _T_1616[1]) @[Parameters.scala 229:46] + node _T_1623 = or(_T_1622, _T_1616[2]) @[Parameters.scala 229:46] + node _T_1625 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1626 = dshl(_T_1625, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1627 = bits(_T_1626, 7, 0) @[package.scala 19:76] + node _T_1628 = not(_T_1627) @[package.scala 19:40] + node _T_1629 = and(io.in[0].d.bits.addr_lo, _T_1628) @[Edges.scala 17:16] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1633 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + node _T_1635 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + when _T_1635 : @[CoreplexNetwork.scala 42:36] + node _T_1636 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1638 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1639 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1641 = eq(_T_1639, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1641 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1642 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1644 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1646 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1647 = or(_T_1646, reset) @[CoreplexNetwork.scala 42:36] + node _T_1649 = eq(_T_1647, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1649 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1651 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1652 = or(_T_1651, reset) @[CoreplexNetwork.scala 42:36] + node _T_1654 = eq(_T_1652, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1654 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1656 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1657 = or(_T_1656, reset) @[CoreplexNetwork.scala 42:36] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1659 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1661 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 42:36] + when _T_1661 : @[CoreplexNetwork.scala 42:36] + node _T_1662 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1664 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1665 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1667 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1668 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1670 = eq(_T_1668, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1670 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1672 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1673 = or(_T_1672, reset) @[CoreplexNetwork.scala 42:36] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1675 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1677 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1678 = or(_T_1677, reset) @[CoreplexNetwork.scala 42:36] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1680 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1682 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 42:36] + when _T_1682 : @[CoreplexNetwork.scala 42:36] + node _T_1683 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1685 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1686 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1688 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1689 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1691 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1693 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 42:36] + node _T_1694 = or(_T_1693, reset) @[CoreplexNetwork.scala 42:36] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1696 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1698 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1699 = or(_T_1698, reset) @[CoreplexNetwork.scala 42:36] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1701 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1703 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1703 : @[CoreplexNetwork.scala 42:36] + node _T_1704 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1706 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1707 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1709 = eq(_T_1707, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1709 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1710 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1712 = eq(_T_1710, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1712 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1714 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1715 = or(_T_1714, reset) @[CoreplexNetwork.scala 42:36] + node _T_1717 = eq(_T_1715, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1717 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1719 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 42:36] + when _T_1719 : @[CoreplexNetwork.scala 42:36] + node _T_1720 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1722 = eq(_T_1720, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1722 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1723 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1725 = eq(_T_1723, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1725 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1726 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1728 = eq(_T_1726, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1728 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1730 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1731 = or(_T_1730, reset) @[CoreplexNetwork.scala 42:36] + node _T_1733 = eq(_T_1731, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1733 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1735 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + when _T_1735 : @[CoreplexNetwork.scala 42:36] + node _T_1736 = or(_T_1623, reset) @[CoreplexNetwork.scala 42:36] + node _T_1738 = eq(_T_1736, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1738 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1739 = or(_T_1631, reset) @[CoreplexNetwork.scala 42:36] + node _T_1741 = eq(_T_1739, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1741 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1742 = or(_T_1633, reset) @[CoreplexNetwork.scala 42:36] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1744 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1746 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1747 = or(_T_1746, reset) @[CoreplexNetwork.scala 42:36] + node _T_1749 = eq(_T_1747, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1749 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1751 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1752 = or(_T_1751, reset) @[CoreplexNetwork.scala 42:36] + node _T_1754 = eq(_T_1752, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1754 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + when io.in[0].e.valid : @[CoreplexNetwork.scala 42:36] + node _T_1756 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 42:36] + node _T_1757 = or(_T_1756, reset) @[CoreplexNetwork.scala 42:36] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1759 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1760 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1762 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1763 = dshl(_T_1762, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1764 = bits(_T_1763, 7, 0) @[package.scala 19:76] + node _T_1765 = not(_T_1764) @[package.scala 19:40] + node _T_1766 = shr(_T_1765, 3) @[Edges.scala 198:59] + node _T_1767 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1771 = mux(_T_1769, _T_1766, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1773 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1775 = sub(_T_1773, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1776 = asUInt(_T_1775) @[Edges.scala 208:28] + node _T_1777 = tail(_T_1776, 1) @[Edges.scala 208:28] + node _T_1779 = eq(_T_1773, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1781 = eq(_T_1773, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1783 = eq(_T_1771, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1784 = or(_T_1781, _T_1783) @[Edges.scala 210:37] + node _T_1785 = and(_T_1784, _T_1760) @[Edges.scala 211:22] + node _T_1786 = not(_T_1777) @[Edges.scala 212:27] + node _T_1787 = and(_T_1771, _T_1786) @[Edges.scala 212:25] + when _T_1760 : @[Edges.scala 213:17] + node _T_1788 = mux(_T_1779, _T_1771, _T_1777) @[Edges.scala 214:21] + _T_1773 <= _T_1788 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1790 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1792 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1794 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1796 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1798 : UInt, clock @[CoreplexNetwork.scala 42:36] + node _T_1800 = eq(_T_1779, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1801 = and(io.in[0].a.valid, _T_1800) @[CoreplexNetwork.scala 42:36] + when _T_1801 : @[CoreplexNetwork.scala 42:36] + node _T_1802 = eq(io.in[0].a.bits.opcode, _T_1790) @[CoreplexNetwork.scala 42:36] + node _T_1803 = or(_T_1802, reset) @[CoreplexNetwork.scala 42:36] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1805 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1806 = eq(io.in[0].a.bits.param, _T_1792) @[CoreplexNetwork.scala 42:36] + node _T_1807 = or(_T_1806, reset) @[CoreplexNetwork.scala 42:36] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1809 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1810 = eq(io.in[0].a.bits.size, _T_1794) @[CoreplexNetwork.scala 42:36] + node _T_1811 = or(_T_1810, reset) @[CoreplexNetwork.scala 42:36] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1813 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1814 = eq(io.in[0].a.bits.source, _T_1796) @[CoreplexNetwork.scala 42:36] + node _T_1815 = or(_T_1814, reset) @[CoreplexNetwork.scala 42:36] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1817 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1818 = eq(io.in[0].a.bits.address, _T_1798) @[CoreplexNetwork.scala 42:36] + node _T_1819 = or(_T_1818, reset) @[CoreplexNetwork.scala 42:36] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1821 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1822 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1823 = and(_T_1822, _T_1779) @[CoreplexNetwork.scala 42:36] + when _T_1823 : @[CoreplexNetwork.scala 42:36] + _T_1790 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 42:36] + _T_1792 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 42:36] + _T_1794 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 42:36] + _T_1796 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 42:36] + _T_1798 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1824 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1826 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1827 = dshl(_T_1826, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1828 = bits(_T_1827, 7, 0) @[package.scala 19:76] + node _T_1829 = not(_T_1828) @[package.scala 19:40] + node _T_1830 = shr(_T_1829, 3) @[Edges.scala 198:59] + node _T_1831 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1836 = mux(UInt<1>("h00"), _T_1830, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1838 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1840 = sub(_T_1838, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1841 = asUInt(_T_1840) @[Edges.scala 208:28] + node _T_1842 = tail(_T_1841, 1) @[Edges.scala 208:28] + node _T_1844 = eq(_T_1838, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1846 = eq(_T_1838, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1848 = eq(_T_1836, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1849 = or(_T_1846, _T_1848) @[Edges.scala 210:37] + node _T_1850 = and(_T_1849, _T_1824) @[Edges.scala 211:22] + node _T_1851 = not(_T_1842) @[Edges.scala 212:27] + node _T_1852 = and(_T_1836, _T_1851) @[Edges.scala 212:25] + when _T_1824 : @[Edges.scala 213:17] + node _T_1853 = mux(_T_1844, _T_1836, _T_1842) @[Edges.scala 214:21] + _T_1838 <= _T_1853 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1855 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1857 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1859 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1861 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1863 : UInt, clock @[CoreplexNetwork.scala 42:36] + node _T_1865 = eq(_T_1844, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1866 = and(io.in[0].b.valid, _T_1865) @[CoreplexNetwork.scala 42:36] + when _T_1866 : @[CoreplexNetwork.scala 42:36] + node _T_1867 = eq(io.in[0].b.bits.opcode, _T_1855) @[CoreplexNetwork.scala 42:36] + node _T_1868 = or(_T_1867, reset) @[CoreplexNetwork.scala 42:36] + node _T_1870 = eq(_T_1868, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1870 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1871 = eq(io.in[0].b.bits.param, _T_1857) @[CoreplexNetwork.scala 42:36] + node _T_1872 = or(_T_1871, reset) @[CoreplexNetwork.scala 42:36] + node _T_1874 = eq(_T_1872, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1874 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1875 = eq(io.in[0].b.bits.size, _T_1859) @[CoreplexNetwork.scala 42:36] + node _T_1876 = or(_T_1875, reset) @[CoreplexNetwork.scala 42:36] + node _T_1878 = eq(_T_1876, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1878 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1879 = eq(io.in[0].b.bits.source, _T_1861) @[CoreplexNetwork.scala 42:36] + node _T_1880 = or(_T_1879, reset) @[CoreplexNetwork.scala 42:36] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1882 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1883 = eq(io.in[0].b.bits.address, _T_1863) @[CoreplexNetwork.scala 42:36] + node _T_1884 = or(_T_1883, reset) @[CoreplexNetwork.scala 42:36] + node _T_1886 = eq(_T_1884, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1886 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1887 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1888 = and(_T_1887, _T_1844) @[CoreplexNetwork.scala 42:36] + when _T_1888 : @[CoreplexNetwork.scala 42:36] + _T_1855 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 42:36] + _T_1857 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 42:36] + _T_1859 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 42:36] + _T_1861 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 42:36] + _T_1863 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1889 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1891 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1892 = dshl(_T_1891, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1893 = bits(_T_1892, 7, 0) @[package.scala 19:76] + node _T_1894 = not(_T_1893) @[package.scala 19:40] + node _T_1895 = shr(_T_1894, 3) @[Edges.scala 198:59] + node _T_1896 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1898 = mux(_T_1896, _T_1895, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1900 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1902 = sub(_T_1900, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1903 = asUInt(_T_1902) @[Edges.scala 208:28] + node _T_1904 = tail(_T_1903, 1) @[Edges.scala 208:28] + node _T_1906 = eq(_T_1900, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1908 = eq(_T_1900, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1910 = eq(_T_1898, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1911 = or(_T_1908, _T_1910) @[Edges.scala 210:37] + node _T_1912 = and(_T_1911, _T_1889) @[Edges.scala 211:22] + node _T_1913 = not(_T_1904) @[Edges.scala 212:27] + node _T_1914 = and(_T_1898, _T_1913) @[Edges.scala 212:25] + when _T_1889 : @[Edges.scala 213:17] + node _T_1915 = mux(_T_1906, _T_1898, _T_1904) @[Edges.scala 214:21] + _T_1900 <= _T_1915 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1917 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1919 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1921 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1923 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1925 : UInt, clock @[CoreplexNetwork.scala 42:36] + node _T_1927 = eq(_T_1906, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1928 = and(io.in[0].c.valid, _T_1927) @[CoreplexNetwork.scala 42:36] + when _T_1928 : @[CoreplexNetwork.scala 42:36] + node _T_1929 = eq(io.in[0].c.bits.opcode, _T_1917) @[CoreplexNetwork.scala 42:36] + node _T_1930 = or(_T_1929, reset) @[CoreplexNetwork.scala 42:36] + node _T_1932 = eq(_T_1930, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1932 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1933 = eq(io.in[0].c.bits.param, _T_1919) @[CoreplexNetwork.scala 42:36] + node _T_1934 = or(_T_1933, reset) @[CoreplexNetwork.scala 42:36] + node _T_1936 = eq(_T_1934, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1936 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1937 = eq(io.in[0].c.bits.size, _T_1921) @[CoreplexNetwork.scala 42:36] + node _T_1938 = or(_T_1937, reset) @[CoreplexNetwork.scala 42:36] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1940 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1941 = eq(io.in[0].c.bits.source, _T_1923) @[CoreplexNetwork.scala 42:36] + node _T_1942 = or(_T_1941, reset) @[CoreplexNetwork.scala 42:36] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1944 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1945 = eq(io.in[0].c.bits.address, _T_1925) @[CoreplexNetwork.scala 42:36] + node _T_1946 = or(_T_1945, reset) @[CoreplexNetwork.scala 42:36] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1948 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1949 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1950 = and(_T_1949, _T_1906) @[CoreplexNetwork.scala 42:36] + when _T_1950 : @[CoreplexNetwork.scala 42:36] + _T_1917 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 42:36] + _T_1919 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 42:36] + _T_1921 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 42:36] + _T_1923 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 42:36] + _T_1925 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1951 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1953 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1954 = dshl(_T_1953, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1955 = bits(_T_1954, 7, 0) @[package.scala 19:76] + node _T_1956 = not(_T_1955) @[package.scala 19:40] + node _T_1957 = shr(_T_1956, 3) @[Edges.scala 198:59] + node _T_1958 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1960 = mux(_T_1958, _T_1957, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1962 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1964 = sub(_T_1962, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1965 = asUInt(_T_1964) @[Edges.scala 208:28] + node _T_1966 = tail(_T_1965, 1) @[Edges.scala 208:28] + node _T_1968 = eq(_T_1962, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1970 = eq(_T_1962, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1972 = eq(_T_1960, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1973 = or(_T_1970, _T_1972) @[Edges.scala 210:37] + node _T_1974 = and(_T_1973, _T_1951) @[Edges.scala 211:22] + node _T_1975 = not(_T_1966) @[Edges.scala 212:27] + node _T_1976 = and(_T_1960, _T_1975) @[Edges.scala 212:25] + when _T_1951 : @[Edges.scala 213:17] + node _T_1977 = mux(_T_1968, _T_1960, _T_1966) @[Edges.scala 214:21] + _T_1962 <= _T_1977 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1979 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1981 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1983 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1985 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1987 : UInt, clock @[CoreplexNetwork.scala 42:36] + reg _T_1989 : UInt, clock @[CoreplexNetwork.scala 42:36] + node _T_1991 = eq(_T_1968, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_1992 = and(io.in[0].d.valid, _T_1991) @[CoreplexNetwork.scala 42:36] + when _T_1992 : @[CoreplexNetwork.scala 42:36] + node _T_1993 = eq(io.in[0].d.bits.opcode, _T_1979) @[CoreplexNetwork.scala 42:36] + node _T_1994 = or(_T_1993, reset) @[CoreplexNetwork.scala 42:36] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_1996 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_1997 = eq(io.in[0].d.bits.param, _T_1981) @[CoreplexNetwork.scala 42:36] + node _T_1998 = or(_T_1997, reset) @[CoreplexNetwork.scala 42:36] + node _T_2000 = eq(_T_1998, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2000 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2001 = eq(io.in[0].d.bits.size, _T_1983) @[CoreplexNetwork.scala 42:36] + node _T_2002 = or(_T_2001, reset) @[CoreplexNetwork.scala 42:36] + node _T_2004 = eq(_T_2002, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2004 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2005 = eq(io.in[0].d.bits.source, _T_1985) @[CoreplexNetwork.scala 42:36] + node _T_2006 = or(_T_2005, reset) @[CoreplexNetwork.scala 42:36] + node _T_2008 = eq(_T_2006, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2008 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2009 = eq(io.in[0].d.bits.sink, _T_1987) @[CoreplexNetwork.scala 42:36] + node _T_2010 = or(_T_2009, reset) @[CoreplexNetwork.scala 42:36] + node _T_2012 = eq(_T_2010, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2012 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2013 = eq(io.in[0].d.bits.addr_lo, _T_1989) @[CoreplexNetwork.scala 42:36] + node _T_2014 = or(_T_2013, reset) @[CoreplexNetwork.scala 42:36] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2016 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2017 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2018 = and(_T_2017, _T_1968) @[CoreplexNetwork.scala 42:36] + when _T_2018 : @[CoreplexNetwork.scala 42:36] + _T_1979 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 42:36] + _T_1981 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 42:36] + _T_1983 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 42:36] + _T_1985 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 42:36] + _T_1987 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 42:36] + _T_1989 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + reg _T_2020 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2021 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2023 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2024 = dshl(_T_2023, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2025 = bits(_T_2024, 7, 0) @[package.scala 19:76] + node _T_2026 = not(_T_2025) @[package.scala 19:40] + node _T_2027 = shr(_T_2026, 3) @[Edges.scala 198:59] + node _T_2028 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2032 = mux(_T_2030, _T_2027, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2034 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2036 = sub(_T_2034, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2037 = asUInt(_T_2036) @[Edges.scala 208:28] + node _T_2038 = tail(_T_2037, 1) @[Edges.scala 208:28] + node _T_2040 = eq(_T_2034, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2042 = eq(_T_2034, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2044 = eq(_T_2032, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2045 = or(_T_2042, _T_2044) @[Edges.scala 210:37] + node _T_2046 = and(_T_2045, _T_2021) @[Edges.scala 211:22] + node _T_2047 = not(_T_2038) @[Edges.scala 212:27] + node _T_2048 = and(_T_2032, _T_2047) @[Edges.scala 212:25] + when _T_2021 : @[Edges.scala 213:17] + node _T_2049 = mux(_T_2040, _T_2032, _T_2038) @[Edges.scala 214:21] + _T_2034 <= _T_2049 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2050 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2052 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2053 = dshl(_T_2052, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2054 = bits(_T_2053, 7, 0) @[package.scala 19:76] + node _T_2055 = not(_T_2054) @[package.scala 19:40] + node _T_2056 = shr(_T_2055, 3) @[Edges.scala 198:59] + node _T_2057 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2059 = mux(_T_2057, _T_2056, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2061 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2063 = sub(_T_2061, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2064 = asUInt(_T_2063) @[Edges.scala 208:28] + node _T_2065 = tail(_T_2064, 1) @[Edges.scala 208:28] + node _T_2067 = eq(_T_2061, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2069 = eq(_T_2061, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2071 = eq(_T_2059, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2072 = or(_T_2069, _T_2071) @[Edges.scala 210:37] + node _T_2073 = and(_T_2072, _T_2050) @[Edges.scala 211:22] + node _T_2074 = not(_T_2065) @[Edges.scala 212:27] + node _T_2075 = and(_T_2059, _T_2074) @[Edges.scala 212:25] + when _T_2050 : @[Edges.scala 213:17] + node _T_2076 = mux(_T_2067, _T_2059, _T_2065) @[Edges.scala 214:21] + _T_2061 <= _T_2076 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2078 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + node _T_2079 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 42:36] + node _T_2080 = or(_T_2078, _T_2079) @[CoreplexNetwork.scala 42:36] + node _T_2082 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_2083 = or(_T_2080, _T_2082) @[CoreplexNetwork.scala 42:36] + node _T_2085 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_2086 = or(_T_2083, _T_2085) @[CoreplexNetwork.scala 42:36] + node _T_2087 = or(_T_2086, reset) @[CoreplexNetwork.scala 42:36] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2089 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + wire _T_2091 : UInt<6> + _T_2091 is invalid + _T_2091 <= UInt<6>("h00") + node _T_2092 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2092 : @[CoreplexNetwork.scala 42:36] + when _T_2045 : @[CoreplexNetwork.scala 42:36] + node _T_2094 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2091 <= _T_2094 @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2095 = dshr(_T_2020, io.in[0].a.bits.source) @[CoreplexNetwork.scala 42:36] + node _T_2096 = bits(_T_2095, 0, 0) @[CoreplexNetwork.scala 42:36] + node _T_2098 = eq(_T_2096, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + node _T_2099 = or(_T_2098, reset) @[CoreplexNetwork.scala 42:36] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2101 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + wire _T_2103 : UInt<6> + _T_2103 is invalid + _T_2103 <= UInt<6>("h00") + node _T_2104 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2106 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 42:36] + node _T_2107 = and(_T_2104, _T_2106) @[CoreplexNetwork.scala 42:36] + when _T_2107 : @[CoreplexNetwork.scala 42:36] + when _T_2072 : @[CoreplexNetwork.scala 42:36] + node _T_2109 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2103 <= _T_2109 @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2110 = or(_T_2091, _T_2020) @[CoreplexNetwork.scala 42:36] + node _T_2111 = dshr(_T_2110, io.in[0].d.bits.source) @[CoreplexNetwork.scala 42:36] + node _T_2112 = bits(_T_2111, 0, 0) @[CoreplexNetwork.scala 42:36] + node _T_2113 = or(_T_2112, reset) @[CoreplexNetwork.scala 42:36] + node _T_2115 = eq(_T_2113, UInt<1>("h00")) @[CoreplexNetwork.scala 42:36] + when _T_2115 : @[CoreplexNetwork.scala 42:36] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:42:36)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 42:36] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + skip @[CoreplexNetwork.scala 42:36] + node _T_2116 = or(_T_2020, _T_2091) @[CoreplexNetwork.scala 42:36] + node _T_2117 = not(_T_2103) @[CoreplexNetwork.scala 42:36] + node _T_2118 = and(_T_2116, _T_2117) @[CoreplexNetwork.scala 42:36] + _T_2020 <= _T_2118 @[CoreplexNetwork.scala 42:36] + + module TLMonitor_20 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 41:8] + node _T_781 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_782 = or(_T_781, reset) @[CoreplexNetwork.scala 41:8] + node _T_784 = eq(_T_782, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_784 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_786 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_787 = not(_T_786) @[Parameters.scala 37:9] + node _T_789 = or(_T_787, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_790 = not(_T_789) @[Parameters.scala 37:7] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_794 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_796 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_799 : UInt<1>[3] @[Parameters.scala 228:27] + _T_799 is invalid @[Parameters.scala 228:27] + _T_799[0] <= _T_792 @[Parameters.scala 228:27] + _T_799[1] <= _T_794 @[Parameters.scala 228:27] + _T_799[2] <= _T_796 @[Parameters.scala 228:27] + node _T_805 = or(_T_799[0], _T_799[1]) @[Parameters.scala 229:46] + node _T_806 = or(_T_805, _T_799[2]) @[Parameters.scala 229:46] + node _T_808 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_809 = dshl(_T_808, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_810 = bits(_T_809, 7, 0) @[package.scala 19:76] + node _T_811 = not(_T_810) @[package.scala 19:40] + node _T_812 = and(io.in[0].a.bits.address, _T_811) @[Edges.scala 17:16] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_816 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_817 = dshl(UInt<1>("h01"), _T_816) @[OneHot.scala 49:12] + node _T_818 = bits(_T_817, 2, 0) @[OneHot.scala 49:37] + node _T_820 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_822 = bits(_T_818, 2, 2) @[package.scala 44:26] + node _T_823 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_825 = eq(_T_823, UInt<1>("h00")) @[package.scala 46:20] + node _T_826 = and(UInt<1>("h01"), _T_825) @[package.scala 49:27] + node _T_827 = and(_T_822, _T_826) @[package.scala 50:38] + node _T_828 = or(_T_820, _T_827) @[package.scala 50:29] + node _T_829 = and(UInt<1>("h01"), _T_823) @[package.scala 49:27] + node _T_830 = and(_T_822, _T_829) @[package.scala 50:38] + node _T_831 = or(_T_820, _T_830) @[package.scala 50:29] + node _T_832 = bits(_T_818, 1, 1) @[package.scala 44:26] + node _T_833 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_835 = eq(_T_833, UInt<1>("h00")) @[package.scala 46:20] + node _T_836 = and(_T_826, _T_835) @[package.scala 49:27] + node _T_837 = and(_T_832, _T_836) @[package.scala 50:38] + node _T_838 = or(_T_828, _T_837) @[package.scala 50:29] + node _T_839 = and(_T_826, _T_833) @[package.scala 49:27] + node _T_840 = and(_T_832, _T_839) @[package.scala 50:38] + node _T_841 = or(_T_828, _T_840) @[package.scala 50:29] + node _T_842 = and(_T_829, _T_835) @[package.scala 49:27] + node _T_843 = and(_T_832, _T_842) @[package.scala 50:38] + node _T_844 = or(_T_831, _T_843) @[package.scala 50:29] + node _T_845 = and(_T_829, _T_833) @[package.scala 49:27] + node _T_846 = and(_T_832, _T_845) @[package.scala 50:38] + node _T_847 = or(_T_831, _T_846) @[package.scala 50:29] + node _T_848 = bits(_T_818, 0, 0) @[package.scala 44:26] + node _T_849 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_851 = eq(_T_849, UInt<1>("h00")) @[package.scala 46:20] + node _T_852 = and(_T_836, _T_851) @[package.scala 49:27] + node _T_853 = and(_T_848, _T_852) @[package.scala 50:38] + node _T_854 = or(_T_838, _T_853) @[package.scala 50:29] + node _T_855 = and(_T_836, _T_849) @[package.scala 49:27] + node _T_856 = and(_T_848, _T_855) @[package.scala 50:38] + node _T_857 = or(_T_838, _T_856) @[package.scala 50:29] + node _T_858 = and(_T_839, _T_851) @[package.scala 49:27] + node _T_859 = and(_T_848, _T_858) @[package.scala 50:38] + node _T_860 = or(_T_841, _T_859) @[package.scala 50:29] + node _T_861 = and(_T_839, _T_849) @[package.scala 49:27] + node _T_862 = and(_T_848, _T_861) @[package.scala 50:38] + node _T_863 = or(_T_841, _T_862) @[package.scala 50:29] + node _T_864 = and(_T_842, _T_851) @[package.scala 49:27] + node _T_865 = and(_T_848, _T_864) @[package.scala 50:38] + node _T_866 = or(_T_844, _T_865) @[package.scala 50:29] + node _T_867 = and(_T_842, _T_849) @[package.scala 49:27] + node _T_868 = and(_T_848, _T_867) @[package.scala 50:38] + node _T_869 = or(_T_844, _T_868) @[package.scala 50:29] + node _T_870 = and(_T_845, _T_851) @[package.scala 49:27] + node _T_871 = and(_T_848, _T_870) @[package.scala 50:38] + node _T_872 = or(_T_847, _T_871) @[package.scala 50:29] + node _T_873 = and(_T_845, _T_849) @[package.scala 49:27] + node _T_874 = and(_T_848, _T_873) @[package.scala 50:38] + node _T_875 = or(_T_847, _T_874) @[package.scala 50:29] + node _T_876 = cat(_T_857, _T_854) @[Cat.scala 30:58] + node _T_877 = cat(_T_863, _T_860) @[Cat.scala 30:58] + node _T_878 = cat(_T_877, _T_876) @[Cat.scala 30:58] + node _T_879 = cat(_T_869, _T_866) @[Cat.scala 30:58] + node _T_880 = cat(_T_875, _T_872) @[Cat.scala 30:58] + node _T_881 = cat(_T_880, _T_879) @[Cat.scala 30:58] + node _T_882 = cat(_T_881, _T_878) @[Cat.scala 30:58] + node _T_884 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + when _T_884 : @[CoreplexNetwork.scala 41:8] + node _T_887 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_889 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_890 = cvt(_T_889) @[Parameters.scala 117:49] + node _T_892 = and(_T_890, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_893 = asSInt(_T_892) @[Parameters.scala 117:52] + node _T_895 = eq(_T_893, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_897 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_898 = cvt(_T_897) @[Parameters.scala 117:49] + node _T_900 = and(_T_898, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_901 = asSInt(_T_900) @[Parameters.scala 117:52] + node _T_903 = eq(_T_901, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = or(_T_895, _T_903) @[Parameters.scala 133:42] + node _T_905 = and(_T_887, _T_904) @[Parameters.scala 132:56] + node _T_907 = or(UInt<1>("h00"), _T_905) @[Parameters.scala 134:30] + node _T_908 = or(_T_907, reset) @[CoreplexNetwork.scala 41:8] + node _T_910 = eq(_T_908, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_910 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_911 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_913 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_915 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 41:8] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_918 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_919 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_921 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_923 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_924 = or(_T_923, reset) @[CoreplexNetwork.scala 41:8] + node _T_926 = eq(_T_924, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_926 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_927 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 41:8] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_930 = or(_T_929, reset) @[CoreplexNetwork.scala 41:8] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_932 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 41:8] + when _T_934 : @[CoreplexNetwork.scala 41:8] + node _T_937 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_939 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_940 = and(_T_937, _T_939) @[Parameters.scala 63:37] + node _T_941 = or(UInt<1>("h00"), _T_940) @[Parameters.scala 132:31] + node _T_943 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_944 = cvt(_T_943) @[Parameters.scala 117:49] + node _T_946 = and(_T_944, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_947 = asSInt(_T_946) @[Parameters.scala 117:52] + node _T_949 = eq(_T_947, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_950 = and(_T_941, _T_949) @[Parameters.scala 132:56] + node _T_953 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_955 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_956 = and(_T_953, _T_955) @[Parameters.scala 63:37] + node _T_957 = or(UInt<1>("h00"), _T_956) @[Parameters.scala 132:31] + node _T_959 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_960 = cvt(_T_959) @[Parameters.scala 117:49] + node _T_962 = and(_T_960, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_963 = asSInt(_T_962) @[Parameters.scala 117:52] + node _T_965 = eq(_T_963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_966 = and(_T_957, _T_965) @[Parameters.scala 132:56] + node _T_968 = or(UInt<1>("h00"), _T_950) @[Parameters.scala 134:30] + node _T_969 = or(_T_968, _T_966) @[Parameters.scala 134:30] + node _T_970 = or(_T_969, reset) @[CoreplexNetwork.scala 41:8] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_972 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_973 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_975 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_976 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_978 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_980 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_981 = or(_T_980, reset) @[CoreplexNetwork.scala 41:8] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_983 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_984 = eq(io.in[0].a.bits.mask, _T_882) @[CoreplexNetwork.scala 41:8] + node _T_985 = or(_T_984, reset) @[CoreplexNetwork.scala 41:8] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_987 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_989 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_989 : @[CoreplexNetwork.scala 41:8] + node _T_992 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_994 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_995 = and(_T_992, _T_994) @[Parameters.scala 63:37] + node _T_996 = or(UInt<1>("h00"), _T_995) @[Parameters.scala 132:31] + node _T_998 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_999 = cvt(_T_998) @[Parameters.scala 117:49] + node _T_1001 = and(_T_999, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1002 = asSInt(_T_1001) @[Parameters.scala 117:52] + node _T_1004 = eq(_T_1002, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1005 = and(_T_996, _T_1004) @[Parameters.scala 132:56] + node _T_1008 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1010 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1011 = cvt(_T_1010) @[Parameters.scala 117:49] + node _T_1013 = and(_T_1011, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1014 = asSInt(_T_1013) @[Parameters.scala 117:52] + node _T_1016 = eq(_T_1014, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = and(_T_1008, _T_1016) @[Parameters.scala 132:56] + node _T_1019 = or(UInt<1>("h00"), _T_1005) @[Parameters.scala 134:30] + node _T_1020 = or(_T_1019, _T_1017) @[Parameters.scala 134:30] + node _T_1021 = or(_T_1020, reset) @[CoreplexNetwork.scala 41:8] + node _T_1023 = eq(_T_1021, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1023 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1024 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_1026 = eq(_T_1024, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1026 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1027 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_1029 = eq(_T_1027, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1029 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1031 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1032 = or(_T_1031, reset) @[CoreplexNetwork.scala 41:8] + node _T_1034 = eq(_T_1032, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1034 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1035 = eq(io.in[0].a.bits.mask, _T_882) @[CoreplexNetwork.scala 41:8] + node _T_1036 = or(_T_1035, reset) @[CoreplexNetwork.scala 41:8] + node _T_1038 = eq(_T_1036, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1038 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1040 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 41:8] + when _T_1040 : @[CoreplexNetwork.scala 41:8] + node _T_1043 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1045 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1046 = and(_T_1043, _T_1045) @[Parameters.scala 63:37] + node _T_1047 = or(UInt<1>("h00"), _T_1046) @[Parameters.scala 132:31] + node _T_1049 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1050 = cvt(_T_1049) @[Parameters.scala 117:49] + node _T_1052 = and(_T_1050, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1053 = asSInt(_T_1052) @[Parameters.scala 117:52] + node _T_1055 = eq(_T_1053, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1056 = and(_T_1047, _T_1055) @[Parameters.scala 132:56] + node _T_1059 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1061 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1062 = cvt(_T_1061) @[Parameters.scala 117:49] + node _T_1064 = and(_T_1062, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1065 = asSInt(_T_1064) @[Parameters.scala 117:52] + node _T_1067 = eq(_T_1065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1068 = and(_T_1059, _T_1067) @[Parameters.scala 132:56] + node _T_1070 = or(UInt<1>("h00"), _T_1056) @[Parameters.scala 134:30] + node _T_1071 = or(_T_1070, _T_1068) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, reset) @[CoreplexNetwork.scala 41:8] + node _T_1074 = eq(_T_1072, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1074 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1075 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1077 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1078 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_1080 = eq(_T_1078, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1080 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1082 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1083 = or(_T_1082, reset) @[CoreplexNetwork.scala 41:8] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1085 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1086 = not(_T_882) @[CoreplexNetwork.scala 41:8] + node _T_1087 = and(io.in[0].a.bits.mask, _T_1086) @[CoreplexNetwork.scala 41:8] + node _T_1089 = eq(_T_1087, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1090 = or(_T_1089, reset) @[CoreplexNetwork.scala 41:8] + node _T_1092 = eq(_T_1090, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1092 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1094 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + when _T_1094 : @[CoreplexNetwork.scala 41:8] + node _T_1097 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1099 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1100 = cvt(_T_1099) @[Parameters.scala 117:49] + node _T_1102 = and(_T_1100, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1103 = asSInt(_T_1102) @[Parameters.scala 117:52] + node _T_1105 = eq(_T_1103, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1107 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1108 = cvt(_T_1107) @[Parameters.scala 117:49] + node _T_1110 = and(_T_1108, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1111 = asSInt(_T_1110) @[Parameters.scala 117:52] + node _T_1113 = eq(_T_1111, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1114 = or(_T_1105, _T_1113) @[Parameters.scala 133:42] + node _T_1115 = and(_T_1097, _T_1114) @[Parameters.scala 132:56] + node _T_1117 = or(UInt<1>("h00"), _T_1115) @[Parameters.scala 134:30] + node _T_1118 = or(_T_1117, reset) @[CoreplexNetwork.scala 41:8] + node _T_1120 = eq(_T_1118, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1120 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1121 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1123 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1124 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1126 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1128 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1129 = or(_T_1128, reset) @[CoreplexNetwork.scala 41:8] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1131 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1132 = eq(io.in[0].a.bits.mask, _T_882) @[CoreplexNetwork.scala 41:8] + node _T_1133 = or(_T_1132, reset) @[CoreplexNetwork.scala 41:8] + node _T_1135 = eq(_T_1133, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1135 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1137 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + when _T_1137 : @[CoreplexNetwork.scala 41:8] + node _T_1140 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1142 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1143 = cvt(_T_1142) @[Parameters.scala 117:49] + node _T_1145 = and(_T_1143, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1146 = asSInt(_T_1145) @[Parameters.scala 117:52] + node _T_1148 = eq(_T_1146, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1150 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1151 = cvt(_T_1150) @[Parameters.scala 117:49] + node _T_1153 = and(_T_1151, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1154 = asSInt(_T_1153) @[Parameters.scala 117:52] + node _T_1156 = eq(_T_1154, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1157 = or(_T_1148, _T_1156) @[Parameters.scala 133:42] + node _T_1158 = and(_T_1140, _T_1157) @[Parameters.scala 132:56] + node _T_1160 = or(UInt<1>("h00"), _T_1158) @[Parameters.scala 134:30] + node _T_1161 = or(_T_1160, reset) @[CoreplexNetwork.scala 41:8] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1163 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1164 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1166 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1167 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1169 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1171 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1172 = or(_T_1171, reset) @[CoreplexNetwork.scala 41:8] + node _T_1174 = eq(_T_1172, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1174 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1175 = eq(io.in[0].a.bits.mask, _T_882) @[CoreplexNetwork.scala 41:8] + node _T_1176 = or(_T_1175, reset) @[CoreplexNetwork.scala 41:8] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1178 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1180 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 41:8] + when _T_1180 : @[CoreplexNetwork.scala 41:8] + node _T_1183 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1185 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1186 = cvt(_T_1185) @[Parameters.scala 117:49] + node _T_1188 = and(_T_1186, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1189 = asSInt(_T_1188) @[Parameters.scala 117:52] + node _T_1191 = eq(_T_1189, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1193 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1194 = cvt(_T_1193) @[Parameters.scala 117:49] + node _T_1196 = and(_T_1194, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1197 = asSInt(_T_1196) @[Parameters.scala 117:52] + node _T_1199 = eq(_T_1197, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1200 = or(_T_1191, _T_1199) @[Parameters.scala 133:42] + node _T_1201 = and(_T_1183, _T_1200) @[Parameters.scala 132:56] + node _T_1203 = or(UInt<1>("h00"), _T_1201) @[Parameters.scala 134:30] + node _T_1204 = or(_T_1203, reset) @[CoreplexNetwork.scala 41:8] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1206 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1207 = or(_T_806, reset) @[CoreplexNetwork.scala 41:8] + node _T_1209 = eq(_T_1207, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1209 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1210 = or(_T_814, reset) @[CoreplexNetwork.scala 41:8] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1212 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1213 = eq(io.in[0].a.bits.mask, _T_882) @[CoreplexNetwork.scala 41:8] + node _T_1214 = or(_T_1213, reset) @[CoreplexNetwork.scala 41:8] + node _T_1216 = eq(_T_1214, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1216 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + when io.in[0].b.valid : @[CoreplexNetwork.scala 41:8] + node _T_1218 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1219 = or(_T_1218, reset) @[CoreplexNetwork.scala 41:8] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1221 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1223 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1224 = cvt(_T_1223) @[Parameters.scala 117:49] + node _T_1226 = and(_T_1224, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1227 = asSInt(_T_1226) @[Parameters.scala 117:52] + node _T_1229 = eq(_T_1227, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1231 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1240 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1240 is invalid @[Parameters.scala 110:36] + _T_1240[0] <= _T_1229 @[Parameters.scala 110:36] + _T_1240[1] <= _T_1237 @[Parameters.scala 110:36] + node _T_1245 = or(_T_1240[0], _T_1240[1]) @[Parameters.scala 119:64] + node _T_1247 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1248 = dshl(_T_1247, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1249 = bits(_T_1248, 7, 0) @[package.scala 19:76] + node _T_1250 = not(_T_1249) @[package.scala 19:40] + node _T_1251 = and(io.in[0].b.bits.address, _T_1250) @[Edges.scala 17:16] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1255 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1256 = dshl(UInt<1>("h01"), _T_1255) @[OneHot.scala 49:12] + node _T_1257 = bits(_T_1256, 2, 0) @[OneHot.scala 49:37] + node _T_1259 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1261 = bits(_T_1257, 2, 2) @[package.scala 44:26] + node _T_1262 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[package.scala 46:20] + node _T_1265 = and(UInt<1>("h01"), _T_1264) @[package.scala 49:27] + node _T_1266 = and(_T_1261, _T_1265) @[package.scala 50:38] + node _T_1267 = or(_T_1259, _T_1266) @[package.scala 50:29] + node _T_1268 = and(UInt<1>("h01"), _T_1262) @[package.scala 49:27] + node _T_1269 = and(_T_1261, _T_1268) @[package.scala 50:38] + node _T_1270 = or(_T_1259, _T_1269) @[package.scala 50:29] + node _T_1271 = bits(_T_1257, 1, 1) @[package.scala 44:26] + node _T_1272 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[package.scala 46:20] + node _T_1275 = and(_T_1265, _T_1274) @[package.scala 49:27] + node _T_1276 = and(_T_1271, _T_1275) @[package.scala 50:38] + node _T_1277 = or(_T_1267, _T_1276) @[package.scala 50:29] + node _T_1278 = and(_T_1265, _T_1272) @[package.scala 49:27] + node _T_1279 = and(_T_1271, _T_1278) @[package.scala 50:38] + node _T_1280 = or(_T_1267, _T_1279) @[package.scala 50:29] + node _T_1281 = and(_T_1268, _T_1274) @[package.scala 49:27] + node _T_1282 = and(_T_1271, _T_1281) @[package.scala 50:38] + node _T_1283 = or(_T_1270, _T_1282) @[package.scala 50:29] + node _T_1284 = and(_T_1268, _T_1272) @[package.scala 49:27] + node _T_1285 = and(_T_1271, _T_1284) @[package.scala 50:38] + node _T_1286 = or(_T_1270, _T_1285) @[package.scala 50:29] + node _T_1287 = bits(_T_1257, 0, 0) @[package.scala 44:26] + node _T_1288 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[package.scala 46:20] + node _T_1291 = and(_T_1275, _T_1290) @[package.scala 49:27] + node _T_1292 = and(_T_1287, _T_1291) @[package.scala 50:38] + node _T_1293 = or(_T_1277, _T_1292) @[package.scala 50:29] + node _T_1294 = and(_T_1275, _T_1288) @[package.scala 49:27] + node _T_1295 = and(_T_1287, _T_1294) @[package.scala 50:38] + node _T_1296 = or(_T_1277, _T_1295) @[package.scala 50:29] + node _T_1297 = and(_T_1278, _T_1290) @[package.scala 49:27] + node _T_1298 = and(_T_1287, _T_1297) @[package.scala 50:38] + node _T_1299 = or(_T_1280, _T_1298) @[package.scala 50:29] + node _T_1300 = and(_T_1278, _T_1288) @[package.scala 49:27] + node _T_1301 = and(_T_1287, _T_1300) @[package.scala 50:38] + node _T_1302 = or(_T_1280, _T_1301) @[package.scala 50:29] + node _T_1303 = and(_T_1281, _T_1290) @[package.scala 49:27] + node _T_1304 = and(_T_1287, _T_1303) @[package.scala 50:38] + node _T_1305 = or(_T_1283, _T_1304) @[package.scala 50:29] + node _T_1306 = and(_T_1281, _T_1288) @[package.scala 49:27] + node _T_1307 = and(_T_1287, _T_1306) @[package.scala 50:38] + node _T_1308 = or(_T_1283, _T_1307) @[package.scala 50:29] + node _T_1309 = and(_T_1284, _T_1290) @[package.scala 49:27] + node _T_1310 = and(_T_1287, _T_1309) @[package.scala 50:38] + node _T_1311 = or(_T_1286, _T_1310) @[package.scala 50:29] + node _T_1312 = and(_T_1284, _T_1288) @[package.scala 49:27] + node _T_1313 = and(_T_1287, _T_1312) @[package.scala 50:38] + node _T_1314 = or(_T_1286, _T_1313) @[package.scala 50:29] + node _T_1315 = cat(_T_1296, _T_1293) @[Cat.scala 30:58] + node _T_1316 = cat(_T_1302, _T_1299) @[Cat.scala 30:58] + node _T_1317 = cat(_T_1316, _T_1315) @[Cat.scala 30:58] + node _T_1318 = cat(_T_1308, _T_1305) @[Cat.scala 30:58] + node _T_1319 = cat(_T_1314, _T_1311) @[Cat.scala 30:58] + node _T_1320 = cat(_T_1319, _T_1318) @[Cat.scala 30:58] + node _T_1321 = cat(_T_1320, _T_1317) @[Cat.scala 30:58] + node _T_1323 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + when _T_1323 : @[CoreplexNetwork.scala 41:8] + node _T_1325 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1326 = not(_T_1325) @[Parameters.scala 37:9] + node _T_1328 = or(_T_1326, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1329 = not(_T_1328) @[Parameters.scala 37:7] + node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1333 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1335 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1338 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1338 is invalid @[Parameters.scala 228:27] + _T_1338[0] <= _T_1331 @[Parameters.scala 228:27] + _T_1338[1] <= _T_1333 @[Parameters.scala 228:27] + _T_1338[2] <= _T_1335 @[Parameters.scala 228:27] + node _T_1346 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1348 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1349 = and(_T_1346, _T_1348) @[Parameters.scala 63:37] + node _T_1352 = mux(_T_1338[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1354 = mux(_T_1338[1], _T_1349, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1356 = mux(_T_1338[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1358 = or(_T_1352, _T_1354) @[Mux.scala 19:72] + node _T_1359 = or(_T_1358, _T_1356) @[Mux.scala 19:72] + wire _T_1361 : UInt<1> @[Mux.scala 19:72] + _T_1361 is invalid @[Mux.scala 19:72] + _T_1361 <= _T_1359 @[Mux.scala 19:72] + node _T_1362 = or(_T_1361, reset) @[CoreplexNetwork.scala 41:8] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1364 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1365 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1367 = eq(_T_1365, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1367 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1369 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1370 = or(_T_1369, reset) @[CoreplexNetwork.scala 41:8] + node _T_1372 = eq(_T_1370, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1372 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1373 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1375 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1377 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1378 = or(_T_1377, reset) @[CoreplexNetwork.scala 41:8] + node _T_1380 = eq(_T_1378, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1380 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1381 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 41:8] + node _T_1383 = eq(_T_1381, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1384 = or(_T_1383, reset) @[CoreplexNetwork.scala 41:8] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1386 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1388 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 41:8] + when _T_1388 : @[CoreplexNetwork.scala 41:8] + node _T_1390 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1392 = eq(_T_1390, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1392 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1393 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1395 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1396 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1398 = eq(_T_1396, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1398 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1400 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1401 = or(_T_1400, reset) @[CoreplexNetwork.scala 41:8] + node _T_1403 = eq(_T_1401, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1403 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1404 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1405 = or(_T_1404, reset) @[CoreplexNetwork.scala 41:8] + node _T_1407 = eq(_T_1405, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1407 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1409 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1409 : @[CoreplexNetwork.scala 41:8] + node _T_1411 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1413 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1414 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1416 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1417 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1419 = eq(_T_1417, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1419 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1421 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1422 = or(_T_1421, reset) @[CoreplexNetwork.scala 41:8] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1424 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1425 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1426 = or(_T_1425, reset) @[CoreplexNetwork.scala 41:8] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1428 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1430 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 41:8] + when _T_1430 : @[CoreplexNetwork.scala 41:8] + node _T_1432 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1434 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1435 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1437 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1438 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1440 = eq(_T_1438, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1440 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1442 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1443 = or(_T_1442, reset) @[CoreplexNetwork.scala 41:8] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1445 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1446 = not(_T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1447 = and(io.in[0].b.bits.mask, _T_1446) @[CoreplexNetwork.scala 41:8] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1450 = or(_T_1449, reset) @[CoreplexNetwork.scala 41:8] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1452 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1454 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + when _T_1454 : @[CoreplexNetwork.scala 41:8] + node _T_1456 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1458 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1459 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1461 = eq(_T_1459, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1461 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1462 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1464 = eq(_T_1462, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1464 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1466 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1467 = or(_T_1466, reset) @[CoreplexNetwork.scala 41:8] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1469 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1470 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 41:8] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1473 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1475 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + when _T_1475 : @[CoreplexNetwork.scala 41:8] + node _T_1477 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1479 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1480 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1482 = eq(_T_1480, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1482 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1483 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1485 = eq(_T_1483, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1485 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1487 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1488 = or(_T_1487, reset) @[CoreplexNetwork.scala 41:8] + node _T_1490 = eq(_T_1488, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1490 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1491 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1492 = or(_T_1491, reset) @[CoreplexNetwork.scala 41:8] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1494 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1496 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 41:8] + when _T_1496 : @[CoreplexNetwork.scala 41:8] + node _T_1498 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 41:8] + node _T_1500 = eq(_T_1498, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1500 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1501 = or(_T_1245, reset) @[CoreplexNetwork.scala 41:8] + node _T_1503 = eq(_T_1501, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1503 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1504 = or(_T_1253, reset) @[CoreplexNetwork.scala 41:8] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1506 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1507 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 41:8] + node _T_1508 = or(_T_1507, reset) @[CoreplexNetwork.scala 41:8] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1510 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + when io.in[0].c.valid : @[CoreplexNetwork.scala 41:8] + node _T_1512 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1513 = or(_T_1512, reset) @[CoreplexNetwork.scala 41:8] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1515 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1517 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1518 = not(_T_1517) @[Parameters.scala 37:9] + node _T_1520 = or(_T_1518, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1521 = not(_T_1520) @[Parameters.scala 37:7] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1525 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1527 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1530 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1530 is invalid @[Parameters.scala 228:27] + _T_1530[0] <= _T_1523 @[Parameters.scala 228:27] + _T_1530[1] <= _T_1525 @[Parameters.scala 228:27] + _T_1530[2] <= _T_1527 @[Parameters.scala 228:27] + node _T_1536 = or(_T_1530[0], _T_1530[1]) @[Parameters.scala 229:46] + node _T_1537 = or(_T_1536, _T_1530[2]) @[Parameters.scala 229:46] + node _T_1539 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1540 = dshl(_T_1539, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1541 = bits(_T_1540, 7, 0) @[package.scala 19:76] + node _T_1542 = not(_T_1541) @[package.scala 19:40] + node _T_1543 = and(io.in[0].c.bits.address, _T_1542) @[Edges.scala 17:16] + node _T_1545 = eq(_T_1543, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1547 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1548 = cvt(_T_1547) @[Parameters.scala 117:49] + node _T_1550 = and(_T_1548, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1551 = asSInt(_T_1550) @[Parameters.scala 117:52] + node _T_1553 = eq(_T_1551, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1555 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1556 = cvt(_T_1555) @[Parameters.scala 117:49] + node _T_1558 = and(_T_1556, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1559 = asSInt(_T_1558) @[Parameters.scala 117:52] + node _T_1561 = eq(_T_1559, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1564 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1564 is invalid @[Parameters.scala 110:36] + _T_1564[0] <= _T_1553 @[Parameters.scala 110:36] + _T_1564[1] <= _T_1561 @[Parameters.scala 110:36] + node _T_1569 = or(_T_1564[0], _T_1564[1]) @[Parameters.scala 119:64] + node _T_1571 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 41:8] + when _T_1571 : @[CoreplexNetwork.scala 41:8] + node _T_1572 = or(_T_1569, reset) @[CoreplexNetwork.scala 41:8] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1574 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1575 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1577 = eq(_T_1575, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1577 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1579 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1580 = or(_T_1579, reset) @[CoreplexNetwork.scala 41:8] + node _T_1582 = eq(_T_1580, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1582 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1583 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1585 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1587 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1588 = or(_T_1587, reset) @[CoreplexNetwork.scala 41:8] + node _T_1590 = eq(_T_1588, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1590 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1592 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1593 = or(_T_1592, reset) @[CoreplexNetwork.scala 41:8] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1595 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1597 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 41:8] + when _T_1597 : @[CoreplexNetwork.scala 41:8] + node _T_1598 = or(_T_1569, reset) @[CoreplexNetwork.scala 41:8] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1600 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1601 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1603 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1605 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1606 = or(_T_1605, reset) @[CoreplexNetwork.scala 41:8] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1608 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1609 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1611 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1613 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1614 = or(_T_1613, reset) @[CoreplexNetwork.scala 41:8] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1616 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1618 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1619 = or(_T_1618, reset) @[CoreplexNetwork.scala 41:8] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1621 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1623 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + when _T_1623 : @[CoreplexNetwork.scala 41:8] + node _T_1626 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1628 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1629 = cvt(_T_1628) @[Parameters.scala 117:49] + node _T_1631 = and(_T_1629, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1632 = asSInt(_T_1631) @[Parameters.scala 117:52] + node _T_1634 = eq(_T_1632, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1636 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1637 = cvt(_T_1636) @[Parameters.scala 117:49] + node _T_1639 = and(_T_1637, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1640 = asSInt(_T_1639) @[Parameters.scala 117:52] + node _T_1642 = eq(_T_1640, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1643 = or(_T_1634, _T_1642) @[Parameters.scala 133:42] + node _T_1644 = and(_T_1626, _T_1643) @[Parameters.scala 132:56] + node _T_1646 = or(UInt<1>("h00"), _T_1644) @[Parameters.scala 134:30] + node _T_1647 = or(_T_1646, reset) @[CoreplexNetwork.scala 41:8] + node _T_1649 = eq(_T_1647, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1649 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1650 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1652 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1654 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1655 = or(_T_1654, reset) @[CoreplexNetwork.scala 41:8] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1657 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1658 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1660 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1662 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1663 = or(_T_1662, reset) @[CoreplexNetwork.scala 41:8] + node _T_1665 = eq(_T_1663, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1665 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1667 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1668 = or(_T_1667, reset) @[CoreplexNetwork.scala 41:8] + node _T_1670 = eq(_T_1668, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1670 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1672 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 41:8] + when _T_1672 : @[CoreplexNetwork.scala 41:8] + node _T_1675 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1677 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1678 = cvt(_T_1677) @[Parameters.scala 117:49] + node _T_1680 = and(_T_1678, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1681 = asSInt(_T_1680) @[Parameters.scala 117:52] + node _T_1683 = eq(_T_1681, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1685 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1686 = cvt(_T_1685) @[Parameters.scala 117:49] + node _T_1688 = and(_T_1686, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1689 = asSInt(_T_1688) @[Parameters.scala 117:52] + node _T_1691 = eq(_T_1689, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1692 = or(_T_1683, _T_1691) @[Parameters.scala 133:42] + node _T_1693 = and(_T_1675, _T_1692) @[Parameters.scala 132:56] + node _T_1695 = or(UInt<1>("h00"), _T_1693) @[Parameters.scala 134:30] + node _T_1696 = or(_T_1695, reset) @[CoreplexNetwork.scala 41:8] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1698 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1699 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1701 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1703 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1704 = or(_T_1703, reset) @[CoreplexNetwork.scala 41:8] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1706 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1707 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1709 = eq(_T_1707, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1709 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1711 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1712 = or(_T_1711, reset) @[CoreplexNetwork.scala 41:8] + node _T_1714 = eq(_T_1712, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1714 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1716 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1717 = or(_T_1716, reset) @[CoreplexNetwork.scala 41:8] + node _T_1719 = eq(_T_1717, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1719 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1721 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1721 : @[CoreplexNetwork.scala 41:8] + node _T_1722 = or(_T_1569, reset) @[CoreplexNetwork.scala 41:8] + node _T_1724 = eq(_T_1722, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1724 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1725 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1727 = eq(_T_1725, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1727 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1728 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1730 = eq(_T_1728, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1730 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1732 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1733 = or(_T_1732, reset) @[CoreplexNetwork.scala 41:8] + node _T_1735 = eq(_T_1733, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1735 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1737 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 41:8] + when _T_1737 : @[CoreplexNetwork.scala 41:8] + node _T_1738 = or(_T_1569, reset) @[CoreplexNetwork.scala 41:8] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1740 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1741 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1743 = eq(_T_1741, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1743 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1744 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1746 = eq(_T_1744, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1746 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1748 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1749 = or(_T_1748, reset) @[CoreplexNetwork.scala 41:8] + node _T_1751 = eq(_T_1749, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1751 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1753 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + when _T_1753 : @[CoreplexNetwork.scala 41:8] + node _T_1754 = or(_T_1569, reset) @[CoreplexNetwork.scala 41:8] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1756 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1757 = or(_T_1537, reset) @[CoreplexNetwork.scala 41:8] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1759 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1760 = or(_T_1545, reset) @[CoreplexNetwork.scala 41:8] + node _T_1762 = eq(_T_1760, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1762 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1764 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1765 = or(_T_1764, reset) @[CoreplexNetwork.scala 41:8] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1767 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1769 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1770 = or(_T_1769, reset) @[CoreplexNetwork.scala 41:8] + node _T_1772 = eq(_T_1770, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1772 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + when io.in[0].d.valid : @[CoreplexNetwork.scala 41:8] + node _T_1774 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1775 = or(_T_1774, reset) @[CoreplexNetwork.scala 41:8] + node _T_1777 = eq(_T_1775, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1777 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1779 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1780 = not(_T_1779) @[Parameters.scala 37:9] + node _T_1782 = or(_T_1780, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1783 = not(_T_1782) @[Parameters.scala 37:7] + node _T_1785 = eq(_T_1783, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1787 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1789 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1792 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1792 is invalid @[Parameters.scala 228:27] + _T_1792[0] <= _T_1785 @[Parameters.scala 228:27] + _T_1792[1] <= _T_1787 @[Parameters.scala 228:27] + _T_1792[2] <= _T_1789 @[Parameters.scala 228:27] + node _T_1798 = or(_T_1792[0], _T_1792[1]) @[Parameters.scala 229:46] + node _T_1799 = or(_T_1798, _T_1792[2]) @[Parameters.scala 229:46] + node _T_1801 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1802 = dshl(_T_1801, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1803 = bits(_T_1802, 7, 0) @[package.scala 19:76] + node _T_1804 = not(_T_1803) @[package.scala 19:40] + node _T_1805 = and(io.in[0].d.bits.addr_lo, _T_1804) @[Edges.scala 17:16] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1809 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + node _T_1811 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + when _T_1811 : @[CoreplexNetwork.scala 41:8] + node _T_1812 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1814 = eq(_T_1812, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1814 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1815 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1817 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1818 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1820 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1822 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1823 = or(_T_1822, reset) @[CoreplexNetwork.scala 41:8] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1825 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1827 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1828 = or(_T_1827, reset) @[CoreplexNetwork.scala 41:8] + node _T_1830 = eq(_T_1828, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1830 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1832 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1833 = or(_T_1832, reset) @[CoreplexNetwork.scala 41:8] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1835 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1837 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 41:8] + when _T_1837 : @[CoreplexNetwork.scala 41:8] + node _T_1838 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1840 = eq(_T_1838, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1840 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1841 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1843 = eq(_T_1841, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1843 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1844 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1846 = eq(_T_1844, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1846 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1848 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1849 = or(_T_1848, reset) @[CoreplexNetwork.scala 41:8] + node _T_1851 = eq(_T_1849, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1851 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1853 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1854 = or(_T_1853, reset) @[CoreplexNetwork.scala 41:8] + node _T_1856 = eq(_T_1854, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1856 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1858 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 41:8] + when _T_1858 : @[CoreplexNetwork.scala 41:8] + node _T_1859 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1861 = eq(_T_1859, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1861 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1862 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1864 = eq(_T_1862, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1864 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1865 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1867 = eq(_T_1865, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1867 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1869 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 41:8] + node _T_1870 = or(_T_1869, reset) @[CoreplexNetwork.scala 41:8] + node _T_1872 = eq(_T_1870, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1872 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1874 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1875 = or(_T_1874, reset) @[CoreplexNetwork.scala 41:8] + node _T_1877 = eq(_T_1875, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1877 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1879 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1879 : @[CoreplexNetwork.scala 41:8] + node _T_1880 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1882 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1883 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1885 = eq(_T_1883, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1885 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1886 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1888 = eq(_T_1886, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1888 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1890 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1891 = or(_T_1890, reset) @[CoreplexNetwork.scala 41:8] + node _T_1893 = eq(_T_1891, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1893 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1895 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 41:8] + when _T_1895 : @[CoreplexNetwork.scala 41:8] + node _T_1896 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1898 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1899 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1901 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1902 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1904 = eq(_T_1902, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1904 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1906 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1907 = or(_T_1906, reset) @[CoreplexNetwork.scala 41:8] + node _T_1909 = eq(_T_1907, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1909 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1911 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + when _T_1911 : @[CoreplexNetwork.scala 41:8] + node _T_1912 = or(_T_1799, reset) @[CoreplexNetwork.scala 41:8] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1914 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1915 = or(_T_1807, reset) @[CoreplexNetwork.scala 41:8] + node _T_1917 = eq(_T_1915, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1917 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1918 = or(_T_1809, reset) @[CoreplexNetwork.scala 41:8] + node _T_1920 = eq(_T_1918, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1920 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1922 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1923 = or(_T_1922, reset) @[CoreplexNetwork.scala 41:8] + node _T_1925 = eq(_T_1923, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1925 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1927 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1928 = or(_T_1927, reset) @[CoreplexNetwork.scala 41:8] + node _T_1930 = eq(_T_1928, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1930 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + when io.in[0].e.valid : @[CoreplexNetwork.scala 41:8] + node _T_1932 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 41:8] + node _T_1933 = or(_T_1932, reset) @[CoreplexNetwork.scala 41:8] + node _T_1935 = eq(_T_1933, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1935 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1936 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1938 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1939 = dshl(_T_1938, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1940 = bits(_T_1939, 7, 0) @[package.scala 19:76] + node _T_1941 = not(_T_1940) @[package.scala 19:40] + node _T_1942 = shr(_T_1941, 3) @[Edges.scala 198:59] + node _T_1943 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1945 = eq(_T_1943, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1947 = mux(_T_1945, _T_1942, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1949 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1951 = sub(_T_1949, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1952 = asUInt(_T_1951) @[Edges.scala 208:28] + node _T_1953 = tail(_T_1952, 1) @[Edges.scala 208:28] + node _T_1955 = eq(_T_1949, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1957 = eq(_T_1949, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1959 = eq(_T_1947, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1960 = or(_T_1957, _T_1959) @[Edges.scala 210:37] + node _T_1961 = and(_T_1960, _T_1936) @[Edges.scala 211:22] + node _T_1962 = not(_T_1953) @[Edges.scala 212:27] + node _T_1963 = and(_T_1947, _T_1962) @[Edges.scala 212:25] + when _T_1936 : @[Edges.scala 213:17] + node _T_1964 = mux(_T_1955, _T_1947, _T_1953) @[Edges.scala 214:21] + _T_1949 <= _T_1964 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1966 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_1968 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_1970 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_1972 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_1974 : UInt, clock @[CoreplexNetwork.scala 41:8] + node _T_1976 = eq(_T_1955, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_1977 = and(io.in[0].a.valid, _T_1976) @[CoreplexNetwork.scala 41:8] + when _T_1977 : @[CoreplexNetwork.scala 41:8] + node _T_1978 = eq(io.in[0].a.bits.opcode, _T_1966) @[CoreplexNetwork.scala 41:8] + node _T_1979 = or(_T_1978, reset) @[CoreplexNetwork.scala 41:8] + node _T_1981 = eq(_T_1979, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1981 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1982 = eq(io.in[0].a.bits.param, _T_1968) @[CoreplexNetwork.scala 41:8] + node _T_1983 = or(_T_1982, reset) @[CoreplexNetwork.scala 41:8] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1985 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1986 = eq(io.in[0].a.bits.size, _T_1970) @[CoreplexNetwork.scala 41:8] + node _T_1987 = or(_T_1986, reset) @[CoreplexNetwork.scala 41:8] + node _T_1989 = eq(_T_1987, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1989 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1990 = eq(io.in[0].a.bits.source, _T_1972) @[CoreplexNetwork.scala 41:8] + node _T_1991 = or(_T_1990, reset) @[CoreplexNetwork.scala 41:8] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1993 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1994 = eq(io.in[0].a.bits.address, _T_1974) @[CoreplexNetwork.scala 41:8] + node _T_1995 = or(_T_1994, reset) @[CoreplexNetwork.scala 41:8] + node _T_1997 = eq(_T_1995, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_1997 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_1998 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1999 = and(_T_1998, _T_1955) @[CoreplexNetwork.scala 41:8] + when _T_1999 : @[CoreplexNetwork.scala 41:8] + _T_1966 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 41:8] + _T_1968 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 41:8] + _T_1970 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 41:8] + _T_1972 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 41:8] + _T_1974 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2000 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2002 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2003 = dshl(_T_2002, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2004 = bits(_T_2003, 7, 0) @[package.scala 19:76] + node _T_2005 = not(_T_2004) @[package.scala 19:40] + node _T_2006 = shr(_T_2005, 3) @[Edges.scala 198:59] + node _T_2007 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2009 = eq(_T_2007, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2012 = mux(UInt<1>("h00"), _T_2006, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2014 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2016 = sub(_T_2014, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2017 = asUInt(_T_2016) @[Edges.scala 208:28] + node _T_2018 = tail(_T_2017, 1) @[Edges.scala 208:28] + node _T_2020 = eq(_T_2014, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2022 = eq(_T_2014, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2024 = eq(_T_2012, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2025 = or(_T_2022, _T_2024) @[Edges.scala 210:37] + node _T_2026 = and(_T_2025, _T_2000) @[Edges.scala 211:22] + node _T_2027 = not(_T_2018) @[Edges.scala 212:27] + node _T_2028 = and(_T_2012, _T_2027) @[Edges.scala 212:25] + when _T_2000 : @[Edges.scala 213:17] + node _T_2029 = mux(_T_2020, _T_2012, _T_2018) @[Edges.scala 214:21] + _T_2014 <= _T_2029 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2031 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2033 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2035 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2037 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2039 : UInt, clock @[CoreplexNetwork.scala 41:8] + node _T_2041 = eq(_T_2020, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2042 = and(io.in[0].b.valid, _T_2041) @[CoreplexNetwork.scala 41:8] + when _T_2042 : @[CoreplexNetwork.scala 41:8] + node _T_2043 = eq(io.in[0].b.bits.opcode, _T_2031) @[CoreplexNetwork.scala 41:8] + node _T_2044 = or(_T_2043, reset) @[CoreplexNetwork.scala 41:8] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2046 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2047 = eq(io.in[0].b.bits.param, _T_2033) @[CoreplexNetwork.scala 41:8] + node _T_2048 = or(_T_2047, reset) @[CoreplexNetwork.scala 41:8] + node _T_2050 = eq(_T_2048, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2050 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2051 = eq(io.in[0].b.bits.size, _T_2035) @[CoreplexNetwork.scala 41:8] + node _T_2052 = or(_T_2051, reset) @[CoreplexNetwork.scala 41:8] + node _T_2054 = eq(_T_2052, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2054 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2055 = eq(io.in[0].b.bits.source, _T_2037) @[CoreplexNetwork.scala 41:8] + node _T_2056 = or(_T_2055, reset) @[CoreplexNetwork.scala 41:8] + node _T_2058 = eq(_T_2056, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2058 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2059 = eq(io.in[0].b.bits.address, _T_2039) @[CoreplexNetwork.scala 41:8] + node _T_2060 = or(_T_2059, reset) @[CoreplexNetwork.scala 41:8] + node _T_2062 = eq(_T_2060, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2062 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2063 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2064 = and(_T_2063, _T_2020) @[CoreplexNetwork.scala 41:8] + when _T_2064 : @[CoreplexNetwork.scala 41:8] + _T_2031 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 41:8] + _T_2033 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 41:8] + _T_2035 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 41:8] + _T_2037 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 41:8] + _T_2039 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2065 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2067 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2068 = dshl(_T_2067, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2069 = bits(_T_2068, 7, 0) @[package.scala 19:76] + node _T_2070 = not(_T_2069) @[package.scala 19:40] + node _T_2071 = shr(_T_2070, 3) @[Edges.scala 198:59] + node _T_2072 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2074 = mux(_T_2072, _T_2071, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2076 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2078 = sub(_T_2076, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2079 = asUInt(_T_2078) @[Edges.scala 208:28] + node _T_2080 = tail(_T_2079, 1) @[Edges.scala 208:28] + node _T_2082 = eq(_T_2076, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2084 = eq(_T_2076, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2086 = eq(_T_2074, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2087 = or(_T_2084, _T_2086) @[Edges.scala 210:37] + node _T_2088 = and(_T_2087, _T_2065) @[Edges.scala 211:22] + node _T_2089 = not(_T_2080) @[Edges.scala 212:27] + node _T_2090 = and(_T_2074, _T_2089) @[Edges.scala 212:25] + when _T_2065 : @[Edges.scala 213:17] + node _T_2091 = mux(_T_2082, _T_2074, _T_2080) @[Edges.scala 214:21] + _T_2076 <= _T_2091 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2093 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2095 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2097 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2099 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2101 : UInt, clock @[CoreplexNetwork.scala 41:8] + node _T_2103 = eq(_T_2082, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2104 = and(io.in[0].c.valid, _T_2103) @[CoreplexNetwork.scala 41:8] + when _T_2104 : @[CoreplexNetwork.scala 41:8] + node _T_2105 = eq(io.in[0].c.bits.opcode, _T_2093) @[CoreplexNetwork.scala 41:8] + node _T_2106 = or(_T_2105, reset) @[CoreplexNetwork.scala 41:8] + node _T_2108 = eq(_T_2106, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2108 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2109 = eq(io.in[0].c.bits.param, _T_2095) @[CoreplexNetwork.scala 41:8] + node _T_2110 = or(_T_2109, reset) @[CoreplexNetwork.scala 41:8] + node _T_2112 = eq(_T_2110, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2112 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2113 = eq(io.in[0].c.bits.size, _T_2097) @[CoreplexNetwork.scala 41:8] + node _T_2114 = or(_T_2113, reset) @[CoreplexNetwork.scala 41:8] + node _T_2116 = eq(_T_2114, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2116 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2117 = eq(io.in[0].c.bits.source, _T_2099) @[CoreplexNetwork.scala 41:8] + node _T_2118 = or(_T_2117, reset) @[CoreplexNetwork.scala 41:8] + node _T_2120 = eq(_T_2118, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2120 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2121 = eq(io.in[0].c.bits.address, _T_2101) @[CoreplexNetwork.scala 41:8] + node _T_2122 = or(_T_2121, reset) @[CoreplexNetwork.scala 41:8] + node _T_2124 = eq(_T_2122, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2124 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2125 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2126 = and(_T_2125, _T_2082) @[CoreplexNetwork.scala 41:8] + when _T_2126 : @[CoreplexNetwork.scala 41:8] + _T_2093 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 41:8] + _T_2095 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 41:8] + _T_2097 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 41:8] + _T_2099 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 41:8] + _T_2101 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2127 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2129 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2130 = dshl(_T_2129, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2131 = bits(_T_2130, 7, 0) @[package.scala 19:76] + node _T_2132 = not(_T_2131) @[package.scala 19:40] + node _T_2133 = shr(_T_2132, 3) @[Edges.scala 198:59] + node _T_2134 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2136 = mux(_T_2134, _T_2133, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2138 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2140 = sub(_T_2138, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2141 = asUInt(_T_2140) @[Edges.scala 208:28] + node _T_2142 = tail(_T_2141, 1) @[Edges.scala 208:28] + node _T_2144 = eq(_T_2138, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2146 = eq(_T_2138, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2148 = eq(_T_2136, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2149 = or(_T_2146, _T_2148) @[Edges.scala 210:37] + node _T_2150 = and(_T_2149, _T_2127) @[Edges.scala 211:22] + node _T_2151 = not(_T_2142) @[Edges.scala 212:27] + node _T_2152 = and(_T_2136, _T_2151) @[Edges.scala 212:25] + when _T_2127 : @[Edges.scala 213:17] + node _T_2153 = mux(_T_2144, _T_2136, _T_2142) @[Edges.scala 214:21] + _T_2138 <= _T_2153 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2155 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2157 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2159 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2161 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2163 : UInt, clock @[CoreplexNetwork.scala 41:8] + reg _T_2165 : UInt, clock @[CoreplexNetwork.scala 41:8] + node _T_2167 = eq(_T_2144, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2168 = and(io.in[0].d.valid, _T_2167) @[CoreplexNetwork.scala 41:8] + when _T_2168 : @[CoreplexNetwork.scala 41:8] + node _T_2169 = eq(io.in[0].d.bits.opcode, _T_2155) @[CoreplexNetwork.scala 41:8] + node _T_2170 = or(_T_2169, reset) @[CoreplexNetwork.scala 41:8] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2172 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2173 = eq(io.in[0].d.bits.param, _T_2157) @[CoreplexNetwork.scala 41:8] + node _T_2174 = or(_T_2173, reset) @[CoreplexNetwork.scala 41:8] + node _T_2176 = eq(_T_2174, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2176 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2177 = eq(io.in[0].d.bits.size, _T_2159) @[CoreplexNetwork.scala 41:8] + node _T_2178 = or(_T_2177, reset) @[CoreplexNetwork.scala 41:8] + node _T_2180 = eq(_T_2178, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2180 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2181 = eq(io.in[0].d.bits.source, _T_2161) @[CoreplexNetwork.scala 41:8] + node _T_2182 = or(_T_2181, reset) @[CoreplexNetwork.scala 41:8] + node _T_2184 = eq(_T_2182, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2184 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2185 = eq(io.in[0].d.bits.sink, _T_2163) @[CoreplexNetwork.scala 41:8] + node _T_2186 = or(_T_2185, reset) @[CoreplexNetwork.scala 41:8] + node _T_2188 = eq(_T_2186, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2188 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2189 = eq(io.in[0].d.bits.addr_lo, _T_2165) @[CoreplexNetwork.scala 41:8] + node _T_2190 = or(_T_2189, reset) @[CoreplexNetwork.scala 41:8] + node _T_2192 = eq(_T_2190, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2192 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2193 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2194 = and(_T_2193, _T_2144) @[CoreplexNetwork.scala 41:8] + when _T_2194 : @[CoreplexNetwork.scala 41:8] + _T_2155 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 41:8] + _T_2157 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 41:8] + _T_2159 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 41:8] + _T_2161 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 41:8] + _T_2163 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 41:8] + _T_2165 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + reg _T_2196 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2197 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2199 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2200 = dshl(_T_2199, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2201 = bits(_T_2200, 7, 0) @[package.scala 19:76] + node _T_2202 = not(_T_2201) @[package.scala 19:40] + node _T_2203 = shr(_T_2202, 3) @[Edges.scala 198:59] + node _T_2204 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2206 = eq(_T_2204, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2208 = mux(_T_2206, _T_2203, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2210 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2212 = sub(_T_2210, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2213 = asUInt(_T_2212) @[Edges.scala 208:28] + node _T_2214 = tail(_T_2213, 1) @[Edges.scala 208:28] + node _T_2216 = eq(_T_2210, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2218 = eq(_T_2210, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2220 = eq(_T_2208, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2221 = or(_T_2218, _T_2220) @[Edges.scala 210:37] + node _T_2222 = and(_T_2221, _T_2197) @[Edges.scala 211:22] + node _T_2223 = not(_T_2214) @[Edges.scala 212:27] + node _T_2224 = and(_T_2208, _T_2223) @[Edges.scala 212:25] + when _T_2197 : @[Edges.scala 213:17] + node _T_2225 = mux(_T_2216, _T_2208, _T_2214) @[Edges.scala 214:21] + _T_2210 <= _T_2225 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2226 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2228 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2229 = dshl(_T_2228, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2230 = bits(_T_2229, 7, 0) @[package.scala 19:76] + node _T_2231 = not(_T_2230) @[package.scala 19:40] + node _T_2232 = shr(_T_2231, 3) @[Edges.scala 198:59] + node _T_2233 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2235 = mux(_T_2233, _T_2232, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2237 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2239 = sub(_T_2237, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2240 = asUInt(_T_2239) @[Edges.scala 208:28] + node _T_2241 = tail(_T_2240, 1) @[Edges.scala 208:28] + node _T_2243 = eq(_T_2237, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2245 = eq(_T_2237, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2247 = eq(_T_2235, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2248 = or(_T_2245, _T_2247) @[Edges.scala 210:37] + node _T_2249 = and(_T_2248, _T_2226) @[Edges.scala 211:22] + node _T_2250 = not(_T_2241) @[Edges.scala 212:27] + node _T_2251 = and(_T_2235, _T_2250) @[Edges.scala 212:25] + when _T_2226 : @[Edges.scala 213:17] + node _T_2252 = mux(_T_2243, _T_2235, _T_2241) @[Edges.scala 214:21] + _T_2237 <= _T_2252 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2254 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + node _T_2255 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 41:8] + node _T_2256 = or(_T_2254, _T_2255) @[CoreplexNetwork.scala 41:8] + node _T_2258 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2259 = or(_T_2256, _T_2258) @[CoreplexNetwork.scala 41:8] + node _T_2261 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2262 = or(_T_2259, _T_2261) @[CoreplexNetwork.scala 41:8] + node _T_2263 = or(_T_2262, reset) @[CoreplexNetwork.scala 41:8] + node _T_2265 = eq(_T_2263, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2265 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + wire _T_2267 : UInt<6> + _T_2267 is invalid + _T_2267 <= UInt<6>("h00") + node _T_2268 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2268 : @[CoreplexNetwork.scala 41:8] + when _T_2221 : @[CoreplexNetwork.scala 41:8] + node _T_2270 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2267 <= _T_2270 @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2271 = dshr(_T_2196, io.in[0].a.bits.source) @[CoreplexNetwork.scala 41:8] + node _T_2272 = bits(_T_2271, 0, 0) @[CoreplexNetwork.scala 41:8] + node _T_2274 = eq(_T_2272, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + node _T_2275 = or(_T_2274, reset) @[CoreplexNetwork.scala 41:8] + node _T_2277 = eq(_T_2275, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2277 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + wire _T_2279 : UInt<6> + _T_2279 is invalid + _T_2279 <= UInt<6>("h00") + node _T_2280 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2282 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 41:8] + node _T_2283 = and(_T_2280, _T_2282) @[CoreplexNetwork.scala 41:8] + when _T_2283 : @[CoreplexNetwork.scala 41:8] + when _T_2248 : @[CoreplexNetwork.scala 41:8] + node _T_2285 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2279 <= _T_2285 @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2286 = or(_T_2267, _T_2196) @[CoreplexNetwork.scala 41:8] + node _T_2287 = dshr(_T_2286, io.in[0].d.bits.source) @[CoreplexNetwork.scala 41:8] + node _T_2288 = bits(_T_2287, 0, 0) @[CoreplexNetwork.scala 41:8] + node _T_2289 = or(_T_2288, reset) @[CoreplexNetwork.scala 41:8] + node _T_2291 = eq(_T_2289, UInt<1>("h00")) @[CoreplexNetwork.scala 41:8] + when _T_2291 : @[CoreplexNetwork.scala 41:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:41:8)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 41:8] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + skip @[CoreplexNetwork.scala 41:8] + node _T_2292 = or(_T_2196, _T_2267) @[CoreplexNetwork.scala 41:8] + node _T_2293 = not(_T_2279) @[CoreplexNetwork.scala 41:8] + node _T_2294 = and(_T_2292, _T_2293) @[CoreplexNetwork.scala 41:8] + _T_2196 <= _T_2294 @[CoreplexNetwork.scala 41:8] + + module Queue_31 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, count : UInt<4>} + + io is invalid + io is invalid + cmem ram : {mask : UInt<8>, data : UInt<64>}[8] @[Decoupled.scala 182:24] + reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module TLBroadcastTracker : + input clock : Clock + input reset : UInt<1> + output io : {flip in_a_first : UInt<1>, flip in_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, out_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip probe : UInt<1>, flip probenack : UInt<1>, flip probedack : UInt<1>, flip d_last : UInt<1>, flip e_last : UInt<1>, source : UInt, line : UInt, idle : UInt<1>} + + io is invalid + io is invalid + reg idle : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[Reg.scala 26:44] + reg opcode : UInt<3>, clock @[Broadcast.scala 230:20] + reg param : UInt<3>, clock @[Broadcast.scala 231:20] + reg size : UInt<3>, clock @[Broadcast.scala 232:20] + reg source : UInt<3>, clock @[Broadcast.scala 233:20] + reg address : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + reg count : UInt<1>, clock @[Broadcast.scala 235:20] + node _T_102 = and(io.in_a.ready, io.in_a.valid) @[Decoupled.scala 30:37] + node _T_103 = and(_T_102, io.in_a_first) @[Broadcast.scala 237:24] + when _T_103 : @[Broadcast.scala 237:42] + node _T_104 = or(idle, reset) @[Broadcast.scala 238:12] + node _T_106 = eq(_T_104, UInt<1>("h00")) @[Broadcast.scala 238:12] + when _T_106 : @[Broadcast.scala 238:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:238 assert (idle)\n") @[Broadcast.scala 238:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 238:12] + skip @[Broadcast.scala 238:12] + idle <= UInt<1>("h00") @[Broadcast.scala 239:13] + opcode <= io.in_a.bits.opcode @[Broadcast.scala 240:13] + param <= io.in_a.bits.param @[Broadcast.scala 241:13] + size <= io.in_a.bits.size @[Broadcast.scala 242:13] + source <= io.in_a.bits.source @[Broadcast.scala 243:13] + address <= io.in_a.bits.address @[Broadcast.scala 244:13] + count <= io.probe @[Broadcast.scala 245:13] + skip @[Broadcast.scala 237:42] + when io.d_last : @[Broadcast.scala 247:20] + node _T_109 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 248:13] + node _T_110 = or(_T_109, reset) @[Broadcast.scala 248:12] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[Broadcast.scala 248:12] + when _T_112 : @[Broadcast.scala 248:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:248 assert (!idle)\n") @[Broadcast.scala 248:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 248:12] + skip @[Broadcast.scala 248:12] + node _T_114 = neq(opcode, UInt<3>("h06")) @[Broadcast.scala 249:20] + idle <= _T_114 @[Broadcast.scala 249:10] + skip @[Broadcast.scala 247:20] + when io.e_last : @[Broadcast.scala 251:20] + node _T_116 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 252:13] + node _T_117 = or(_T_116, reset) @[Broadcast.scala 252:12] + node _T_119 = eq(_T_117, UInt<1>("h00")) @[Broadcast.scala 252:12] + when _T_119 : @[Broadcast.scala 252:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:252 assert (!idle)\n") @[Broadcast.scala 252:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 252:12] + skip @[Broadcast.scala 252:12] + idle <= UInt<1>("h01") @[Broadcast.scala 253:10] + skip @[Broadcast.scala 251:20] + node _T_121 = or(io.probenack, io.probedack) @[Broadcast.scala 256:22] + when _T_121 : @[Broadcast.scala 256:39] + node _T_123 = gt(count, UInt<1>("h00")) @[Broadcast.scala 257:19] + node _T_124 = or(_T_123, reset) @[Broadcast.scala 257:12] + node _T_126 = eq(_T_124, UInt<1>("h00")) @[Broadcast.scala 257:12] + when _T_126 : @[Broadcast.scala 257:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:257 assert (count > UInt(0))\n") @[Broadcast.scala 257:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 257:12] + skip @[Broadcast.scala 257:12] + node _T_127 = and(io.probenack, io.probedack) @[Broadcast.scala 258:39] + node _T_130 = mux(_T_127, UInt<2>("h02"), UInt<1>("h01")) @[Broadcast.scala 258:25] + node _T_131 = sub(count, _T_130) @[Broadcast.scala 258:20] + node _T_132 = asUInt(_T_131) @[Broadcast.scala 258:20] + node _T_133 = tail(_T_132, 1) @[Broadcast.scala 258:20] + count <= _T_133 @[Broadcast.scala 258:11] + skip @[Broadcast.scala 256:39] + io.idle <= idle @[Broadcast.scala 261:11] + io.source <= source @[Broadcast.scala 262:13] + node _T_134 = shr(address, 6) @[Broadcast.scala 263:22] + io.line <= _T_134 @[Broadcast.scala 263:11] + wire i_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}} @[Broadcast.scala 265:20] + i_data is invalid @[Broadcast.scala 265:20] + inst o_data of Queue_31 @[Decoupled.scala 253:19] + o_data.io is invalid + o_data.clock <= clock + o_data.reset <= reset + o_data.io.enq.valid <= i_data.valid @[Decoupled.scala 254:20] + o_data.io.enq.bits <- i_data.bits @[Decoupled.scala 255:19] + i_data.ready <= o_data.io.enq.ready @[Decoupled.scala 256:15] + node _T_163 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 268:29] + node _T_164 = or(idle, _T_163) @[Broadcast.scala 268:26] + node _T_165 = and(_T_164, i_data.ready) @[Broadcast.scala 268:45] + io.in_a.ready <= _T_165 @[Broadcast.scala 268:17] + node _T_167 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 269:28] + node _T_168 = or(idle, _T_167) @[Broadcast.scala 269:25] + node _T_169 = and(_T_168, io.in_a.valid) @[Broadcast.scala 269:44] + i_data.valid <= _T_169 @[Broadcast.scala 269:16] + i_data.bits.mask <= io.in_a.bits.mask @[Broadcast.scala 270:20] + i_data.bits.data <= io.in_a.bits.data @[Broadcast.scala 271:20] + node probe_done = eq(count, UInt<1>("h00")) @[Broadcast.scala 273:26] + node acquire = eq(opcode, UInt<3>("h06")) @[Broadcast.scala 274:24] + wire _T_173 : UInt<2> @[Broadcast.scala 276:40] + _T_173 is invalid @[Broadcast.scala 276:40] + node _T_180 = eq(UInt<2>("h02"), param) @[Mux.scala 46:19] + node _T_181 = mux(_T_180, UInt<2>("h03"), _T_173) @[Mux.scala 46:16] + node _T_182 = eq(UInt<2>("h01"), param) @[Mux.scala 46:19] + node _T_183 = mux(_T_182, UInt<2>("h03"), _T_181) @[Mux.scala 46:16] + node _T_184 = eq(UInt<2>("h00"), param) @[Mux.scala 46:19] + node transform = mux(_T_184, UInt<2>("h02"), _T_183) @[Mux.scala 46:16] + node _T_185 = and(io.out_a.ready, probe_done) @[Broadcast.scala 281:34] + o_data.io.deq.ready <= _T_185 @[Broadcast.scala 281:16] + node _T_186 = and(o_data.io.deq.valid, probe_done) @[Broadcast.scala 282:34] + io.out_a.valid <= _T_186 @[Broadcast.scala 282:18] + node _T_188 = mux(acquire, UInt<3>("h04"), opcode) @[Broadcast.scala 283:31] + io.out_a.bits.opcode <= _T_188 @[Broadcast.scala 283:25] + node _T_190 = mux(acquire, UInt<1>("h00"), param) @[Broadcast.scala 284:31] + io.out_a.bits.param <= _T_190 @[Broadcast.scala 284:25] + io.out_a.bits.size <= size @[Broadcast.scala 285:25] + node _T_192 = mux(acquire, transform, UInt<1>("h00")) @[Broadcast.scala 286:35] + node _T_193 = cat(_T_192, source) @[Cat.scala 30:58] + io.out_a.bits.source <= _T_193 @[Broadcast.scala 286:25] + io.out_a.bits.address <= address @[Broadcast.scala 287:25] + io.out_a.bits.mask <= o_data.io.deq.bits.mask @[Broadcast.scala 288:25] + io.out_a.bits.data <= o_data.io.deq.bits.data @[Broadcast.scala 289:25] + + module Queue_32 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, count : UInt<4>} + + io is invalid + io is invalid + cmem ram : {mask : UInt<8>, data : UInt<64>}[8] @[Decoupled.scala 182:24] + reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module TLBroadcastTracker_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in_a_first : UInt<1>, flip in_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, out_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip probe : UInt<1>, flip probenack : UInt<1>, flip probedack : UInt<1>, flip d_last : UInt<1>, flip e_last : UInt<1>, source : UInt, line : UInt, idle : UInt<1>} + + io is invalid + io is invalid + reg idle : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[Reg.scala 26:44] + reg opcode : UInt<3>, clock @[Broadcast.scala 230:20] + reg param : UInt<3>, clock @[Broadcast.scala 231:20] + reg size : UInt<3>, clock @[Broadcast.scala 232:20] + reg source : UInt<3>, clock @[Broadcast.scala 233:20] + reg address : UInt<32>, clock with : (reset => (reset, UInt<32>("h040"))) @[Reg.scala 26:44] + reg count : UInt<1>, clock @[Broadcast.scala 235:20] + node _T_102 = and(io.in_a.ready, io.in_a.valid) @[Decoupled.scala 30:37] + node _T_103 = and(_T_102, io.in_a_first) @[Broadcast.scala 237:24] + when _T_103 : @[Broadcast.scala 237:42] + node _T_104 = or(idle, reset) @[Broadcast.scala 238:12] + node _T_106 = eq(_T_104, UInt<1>("h00")) @[Broadcast.scala 238:12] + when _T_106 : @[Broadcast.scala 238:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:238 assert (idle)\n") @[Broadcast.scala 238:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 238:12] + skip @[Broadcast.scala 238:12] + idle <= UInt<1>("h00") @[Broadcast.scala 239:13] + opcode <= io.in_a.bits.opcode @[Broadcast.scala 240:13] + param <= io.in_a.bits.param @[Broadcast.scala 241:13] + size <= io.in_a.bits.size @[Broadcast.scala 242:13] + source <= io.in_a.bits.source @[Broadcast.scala 243:13] + address <= io.in_a.bits.address @[Broadcast.scala 244:13] + count <= io.probe @[Broadcast.scala 245:13] + skip @[Broadcast.scala 237:42] + when io.d_last : @[Broadcast.scala 247:20] + node _T_109 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 248:13] + node _T_110 = or(_T_109, reset) @[Broadcast.scala 248:12] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[Broadcast.scala 248:12] + when _T_112 : @[Broadcast.scala 248:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:248 assert (!idle)\n") @[Broadcast.scala 248:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 248:12] + skip @[Broadcast.scala 248:12] + node _T_114 = neq(opcode, UInt<3>("h06")) @[Broadcast.scala 249:20] + idle <= _T_114 @[Broadcast.scala 249:10] + skip @[Broadcast.scala 247:20] + when io.e_last : @[Broadcast.scala 251:20] + node _T_116 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 252:13] + node _T_117 = or(_T_116, reset) @[Broadcast.scala 252:12] + node _T_119 = eq(_T_117, UInt<1>("h00")) @[Broadcast.scala 252:12] + when _T_119 : @[Broadcast.scala 252:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:252 assert (!idle)\n") @[Broadcast.scala 252:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 252:12] + skip @[Broadcast.scala 252:12] + idle <= UInt<1>("h01") @[Broadcast.scala 253:10] + skip @[Broadcast.scala 251:20] + node _T_121 = or(io.probenack, io.probedack) @[Broadcast.scala 256:22] + when _T_121 : @[Broadcast.scala 256:39] + node _T_123 = gt(count, UInt<1>("h00")) @[Broadcast.scala 257:19] + node _T_124 = or(_T_123, reset) @[Broadcast.scala 257:12] + node _T_126 = eq(_T_124, UInt<1>("h00")) @[Broadcast.scala 257:12] + when _T_126 : @[Broadcast.scala 257:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:257 assert (count > UInt(0))\n") @[Broadcast.scala 257:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 257:12] + skip @[Broadcast.scala 257:12] + node _T_127 = and(io.probenack, io.probedack) @[Broadcast.scala 258:39] + node _T_130 = mux(_T_127, UInt<2>("h02"), UInt<1>("h01")) @[Broadcast.scala 258:25] + node _T_131 = sub(count, _T_130) @[Broadcast.scala 258:20] + node _T_132 = asUInt(_T_131) @[Broadcast.scala 258:20] + node _T_133 = tail(_T_132, 1) @[Broadcast.scala 258:20] + count <= _T_133 @[Broadcast.scala 258:11] + skip @[Broadcast.scala 256:39] + io.idle <= idle @[Broadcast.scala 261:11] + io.source <= source @[Broadcast.scala 262:13] + node _T_134 = shr(address, 6) @[Broadcast.scala 263:22] + io.line <= _T_134 @[Broadcast.scala 263:11] + wire i_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}} @[Broadcast.scala 265:20] + i_data is invalid @[Broadcast.scala 265:20] + inst o_data of Queue_32 @[Decoupled.scala 253:19] + o_data.io is invalid + o_data.clock <= clock + o_data.reset <= reset + o_data.io.enq.valid <= i_data.valid @[Decoupled.scala 254:20] + o_data.io.enq.bits <- i_data.bits @[Decoupled.scala 255:19] + i_data.ready <= o_data.io.enq.ready @[Decoupled.scala 256:15] + node _T_163 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 268:29] + node _T_164 = or(idle, _T_163) @[Broadcast.scala 268:26] + node _T_165 = and(_T_164, i_data.ready) @[Broadcast.scala 268:45] + io.in_a.ready <= _T_165 @[Broadcast.scala 268:17] + node _T_167 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 269:28] + node _T_168 = or(idle, _T_167) @[Broadcast.scala 269:25] + node _T_169 = and(_T_168, io.in_a.valid) @[Broadcast.scala 269:44] + i_data.valid <= _T_169 @[Broadcast.scala 269:16] + i_data.bits.mask <= io.in_a.bits.mask @[Broadcast.scala 270:20] + i_data.bits.data <= io.in_a.bits.data @[Broadcast.scala 271:20] + node probe_done = eq(count, UInt<1>("h00")) @[Broadcast.scala 273:26] + node acquire = eq(opcode, UInt<3>("h06")) @[Broadcast.scala 274:24] + wire _T_173 : UInt<2> @[Broadcast.scala 276:40] + _T_173 is invalid @[Broadcast.scala 276:40] + node _T_180 = eq(UInt<2>("h02"), param) @[Mux.scala 46:19] + node _T_181 = mux(_T_180, UInt<2>("h03"), _T_173) @[Mux.scala 46:16] + node _T_182 = eq(UInt<2>("h01"), param) @[Mux.scala 46:19] + node _T_183 = mux(_T_182, UInt<2>("h03"), _T_181) @[Mux.scala 46:16] + node _T_184 = eq(UInt<2>("h00"), param) @[Mux.scala 46:19] + node transform = mux(_T_184, UInt<2>("h02"), _T_183) @[Mux.scala 46:16] + node _T_185 = and(io.out_a.ready, probe_done) @[Broadcast.scala 281:34] + o_data.io.deq.ready <= _T_185 @[Broadcast.scala 281:16] + node _T_186 = and(o_data.io.deq.valid, probe_done) @[Broadcast.scala 282:34] + io.out_a.valid <= _T_186 @[Broadcast.scala 282:18] + node _T_188 = mux(acquire, UInt<3>("h04"), opcode) @[Broadcast.scala 283:31] + io.out_a.bits.opcode <= _T_188 @[Broadcast.scala 283:25] + node _T_190 = mux(acquire, UInt<1>("h00"), param) @[Broadcast.scala 284:31] + io.out_a.bits.param <= _T_190 @[Broadcast.scala 284:25] + io.out_a.bits.size <= size @[Broadcast.scala 285:25] + node _T_192 = mux(acquire, transform, UInt<1>("h00")) @[Broadcast.scala 286:35] + node _T_193 = cat(_T_192, source) @[Cat.scala 30:58] + io.out_a.bits.source <= _T_193 @[Broadcast.scala 286:25] + io.out_a.bits.address <= address @[Broadcast.scala 287:25] + io.out_a.bits.mask <= o_data.io.deq.bits.mask @[Broadcast.scala 288:25] + io.out_a.bits.data <= o_data.io.deq.bits.data @[Broadcast.scala 289:25] + + module Queue_33 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, count : UInt<4>} + + io is invalid + io is invalid + cmem ram : {mask : UInt<8>, data : UInt<64>}[8] @[Decoupled.scala 182:24] + reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module TLBroadcastTracker_2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in_a_first : UInt<1>, flip in_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, out_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip probe : UInt<1>, flip probenack : UInt<1>, flip probedack : UInt<1>, flip d_last : UInt<1>, flip e_last : UInt<1>, source : UInt, line : UInt, idle : UInt<1>} + + io is invalid + io is invalid + reg idle : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[Reg.scala 26:44] + reg opcode : UInt<3>, clock @[Broadcast.scala 230:20] + reg param : UInt<3>, clock @[Broadcast.scala 231:20] + reg size : UInt<3>, clock @[Broadcast.scala 232:20] + reg source : UInt<3>, clock @[Broadcast.scala 233:20] + reg address : UInt<32>, clock with : (reset => (reset, UInt<32>("h080"))) @[Reg.scala 26:44] + reg count : UInt<1>, clock @[Broadcast.scala 235:20] + node _T_102 = and(io.in_a.ready, io.in_a.valid) @[Decoupled.scala 30:37] + node _T_103 = and(_T_102, io.in_a_first) @[Broadcast.scala 237:24] + when _T_103 : @[Broadcast.scala 237:42] + node _T_104 = or(idle, reset) @[Broadcast.scala 238:12] + node _T_106 = eq(_T_104, UInt<1>("h00")) @[Broadcast.scala 238:12] + when _T_106 : @[Broadcast.scala 238:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:238 assert (idle)\n") @[Broadcast.scala 238:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 238:12] + skip @[Broadcast.scala 238:12] + idle <= UInt<1>("h00") @[Broadcast.scala 239:13] + opcode <= io.in_a.bits.opcode @[Broadcast.scala 240:13] + param <= io.in_a.bits.param @[Broadcast.scala 241:13] + size <= io.in_a.bits.size @[Broadcast.scala 242:13] + source <= io.in_a.bits.source @[Broadcast.scala 243:13] + address <= io.in_a.bits.address @[Broadcast.scala 244:13] + count <= io.probe @[Broadcast.scala 245:13] + skip @[Broadcast.scala 237:42] + when io.d_last : @[Broadcast.scala 247:20] + node _T_109 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 248:13] + node _T_110 = or(_T_109, reset) @[Broadcast.scala 248:12] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[Broadcast.scala 248:12] + when _T_112 : @[Broadcast.scala 248:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:248 assert (!idle)\n") @[Broadcast.scala 248:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 248:12] + skip @[Broadcast.scala 248:12] + node _T_114 = neq(opcode, UInt<3>("h06")) @[Broadcast.scala 249:20] + idle <= _T_114 @[Broadcast.scala 249:10] + skip @[Broadcast.scala 247:20] + when io.e_last : @[Broadcast.scala 251:20] + node _T_116 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 252:13] + node _T_117 = or(_T_116, reset) @[Broadcast.scala 252:12] + node _T_119 = eq(_T_117, UInt<1>("h00")) @[Broadcast.scala 252:12] + when _T_119 : @[Broadcast.scala 252:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:252 assert (!idle)\n") @[Broadcast.scala 252:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 252:12] + skip @[Broadcast.scala 252:12] + idle <= UInt<1>("h01") @[Broadcast.scala 253:10] + skip @[Broadcast.scala 251:20] + node _T_121 = or(io.probenack, io.probedack) @[Broadcast.scala 256:22] + when _T_121 : @[Broadcast.scala 256:39] + node _T_123 = gt(count, UInt<1>("h00")) @[Broadcast.scala 257:19] + node _T_124 = or(_T_123, reset) @[Broadcast.scala 257:12] + node _T_126 = eq(_T_124, UInt<1>("h00")) @[Broadcast.scala 257:12] + when _T_126 : @[Broadcast.scala 257:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:257 assert (count > UInt(0))\n") @[Broadcast.scala 257:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 257:12] + skip @[Broadcast.scala 257:12] + node _T_127 = and(io.probenack, io.probedack) @[Broadcast.scala 258:39] + node _T_130 = mux(_T_127, UInt<2>("h02"), UInt<1>("h01")) @[Broadcast.scala 258:25] + node _T_131 = sub(count, _T_130) @[Broadcast.scala 258:20] + node _T_132 = asUInt(_T_131) @[Broadcast.scala 258:20] + node _T_133 = tail(_T_132, 1) @[Broadcast.scala 258:20] + count <= _T_133 @[Broadcast.scala 258:11] + skip @[Broadcast.scala 256:39] + io.idle <= idle @[Broadcast.scala 261:11] + io.source <= source @[Broadcast.scala 262:13] + node _T_134 = shr(address, 6) @[Broadcast.scala 263:22] + io.line <= _T_134 @[Broadcast.scala 263:11] + wire i_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}} @[Broadcast.scala 265:20] + i_data is invalid @[Broadcast.scala 265:20] + inst o_data of Queue_33 @[Decoupled.scala 253:19] + o_data.io is invalid + o_data.clock <= clock + o_data.reset <= reset + o_data.io.enq.valid <= i_data.valid @[Decoupled.scala 254:20] + o_data.io.enq.bits <- i_data.bits @[Decoupled.scala 255:19] + i_data.ready <= o_data.io.enq.ready @[Decoupled.scala 256:15] + node _T_163 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 268:29] + node _T_164 = or(idle, _T_163) @[Broadcast.scala 268:26] + node _T_165 = and(_T_164, i_data.ready) @[Broadcast.scala 268:45] + io.in_a.ready <= _T_165 @[Broadcast.scala 268:17] + node _T_167 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 269:28] + node _T_168 = or(idle, _T_167) @[Broadcast.scala 269:25] + node _T_169 = and(_T_168, io.in_a.valid) @[Broadcast.scala 269:44] + i_data.valid <= _T_169 @[Broadcast.scala 269:16] + i_data.bits.mask <= io.in_a.bits.mask @[Broadcast.scala 270:20] + i_data.bits.data <= io.in_a.bits.data @[Broadcast.scala 271:20] + node probe_done = eq(count, UInt<1>("h00")) @[Broadcast.scala 273:26] + node acquire = eq(opcode, UInt<3>("h06")) @[Broadcast.scala 274:24] + wire _T_173 : UInt<2> @[Broadcast.scala 276:40] + _T_173 is invalid @[Broadcast.scala 276:40] + node _T_180 = eq(UInt<2>("h02"), param) @[Mux.scala 46:19] + node _T_181 = mux(_T_180, UInt<2>("h03"), _T_173) @[Mux.scala 46:16] + node _T_182 = eq(UInt<2>("h01"), param) @[Mux.scala 46:19] + node _T_183 = mux(_T_182, UInt<2>("h03"), _T_181) @[Mux.scala 46:16] + node _T_184 = eq(UInt<2>("h00"), param) @[Mux.scala 46:19] + node transform = mux(_T_184, UInt<2>("h02"), _T_183) @[Mux.scala 46:16] + node _T_185 = and(io.out_a.ready, probe_done) @[Broadcast.scala 281:34] + o_data.io.deq.ready <= _T_185 @[Broadcast.scala 281:16] + node _T_186 = and(o_data.io.deq.valid, probe_done) @[Broadcast.scala 282:34] + io.out_a.valid <= _T_186 @[Broadcast.scala 282:18] + node _T_188 = mux(acquire, UInt<3>("h04"), opcode) @[Broadcast.scala 283:31] + io.out_a.bits.opcode <= _T_188 @[Broadcast.scala 283:25] + node _T_190 = mux(acquire, UInt<1>("h00"), param) @[Broadcast.scala 284:31] + io.out_a.bits.param <= _T_190 @[Broadcast.scala 284:25] + io.out_a.bits.size <= size @[Broadcast.scala 285:25] + node _T_192 = mux(acquire, transform, UInt<1>("h00")) @[Broadcast.scala 286:35] + node _T_193 = cat(_T_192, source) @[Cat.scala 30:58] + io.out_a.bits.source <= _T_193 @[Broadcast.scala 286:25] + io.out_a.bits.address <= address @[Broadcast.scala 287:25] + io.out_a.bits.mask <= o_data.io.deq.bits.mask @[Broadcast.scala 288:25] + io.out_a.bits.data <= o_data.io.deq.bits.data @[Broadcast.scala 289:25] + + module Queue_34 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}}, count : UInt<4>} + + io is invalid + io is invalid + cmem ram : {mask : UInt<8>, data : UInt<64>}[8] @[Decoupled.scala 182:24] + reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<3>("h07")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module TLBroadcastTracker_3 : + input clock : Clock + input reset : UInt<1> + output io : {flip in_a_first : UInt<1>, flip in_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, out_a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip probe : UInt<1>, flip probenack : UInt<1>, flip probedack : UInt<1>, flip d_last : UInt<1>, flip e_last : UInt<1>, source : UInt, line : UInt, idle : UInt<1>} + + io is invalid + io is invalid + reg idle : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[Reg.scala 26:44] + reg opcode : UInt<3>, clock @[Broadcast.scala 230:20] + reg param : UInt<3>, clock @[Broadcast.scala 231:20] + reg size : UInt<3>, clock @[Broadcast.scala 232:20] + reg source : UInt<3>, clock @[Broadcast.scala 233:20] + reg address : UInt<32>, clock with : (reset => (reset, UInt<32>("h0c0"))) @[Reg.scala 26:44] + reg count : UInt<1>, clock @[Broadcast.scala 235:20] + node _T_102 = and(io.in_a.ready, io.in_a.valid) @[Decoupled.scala 30:37] + node _T_103 = and(_T_102, io.in_a_first) @[Broadcast.scala 237:24] + when _T_103 : @[Broadcast.scala 237:42] + node _T_104 = or(idle, reset) @[Broadcast.scala 238:12] + node _T_106 = eq(_T_104, UInt<1>("h00")) @[Broadcast.scala 238:12] + when _T_106 : @[Broadcast.scala 238:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:238 assert (idle)\n") @[Broadcast.scala 238:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 238:12] + skip @[Broadcast.scala 238:12] + idle <= UInt<1>("h00") @[Broadcast.scala 239:13] + opcode <= io.in_a.bits.opcode @[Broadcast.scala 240:13] + param <= io.in_a.bits.param @[Broadcast.scala 241:13] + size <= io.in_a.bits.size @[Broadcast.scala 242:13] + source <= io.in_a.bits.source @[Broadcast.scala 243:13] + address <= io.in_a.bits.address @[Broadcast.scala 244:13] + count <= io.probe @[Broadcast.scala 245:13] + skip @[Broadcast.scala 237:42] + when io.d_last : @[Broadcast.scala 247:20] + node _T_109 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 248:13] + node _T_110 = or(_T_109, reset) @[Broadcast.scala 248:12] + node _T_112 = eq(_T_110, UInt<1>("h00")) @[Broadcast.scala 248:12] + when _T_112 : @[Broadcast.scala 248:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:248 assert (!idle)\n") @[Broadcast.scala 248:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 248:12] + skip @[Broadcast.scala 248:12] + node _T_114 = neq(opcode, UInt<3>("h06")) @[Broadcast.scala 249:20] + idle <= _T_114 @[Broadcast.scala 249:10] + skip @[Broadcast.scala 247:20] + when io.e_last : @[Broadcast.scala 251:20] + node _T_116 = eq(idle, UInt<1>("h00")) @[Broadcast.scala 252:13] + node _T_117 = or(_T_116, reset) @[Broadcast.scala 252:12] + node _T_119 = eq(_T_117, UInt<1>("h00")) @[Broadcast.scala 252:12] + when _T_119 : @[Broadcast.scala 252:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:252 assert (!idle)\n") @[Broadcast.scala 252:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 252:12] + skip @[Broadcast.scala 252:12] + idle <= UInt<1>("h01") @[Broadcast.scala 253:10] + skip @[Broadcast.scala 251:20] + node _T_121 = or(io.probenack, io.probedack) @[Broadcast.scala 256:22] + when _T_121 : @[Broadcast.scala 256:39] + node _T_123 = gt(count, UInt<1>("h00")) @[Broadcast.scala 257:19] + node _T_124 = or(_T_123, reset) @[Broadcast.scala 257:12] + node _T_126 = eq(_T_124, UInt<1>("h00")) @[Broadcast.scala 257:12] + when _T_126 : @[Broadcast.scala 257:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:257 assert (count > UInt(0))\n") @[Broadcast.scala 257:12] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 257:12] + skip @[Broadcast.scala 257:12] + node _T_127 = and(io.probenack, io.probedack) @[Broadcast.scala 258:39] + node _T_130 = mux(_T_127, UInt<2>("h02"), UInt<1>("h01")) @[Broadcast.scala 258:25] + node _T_131 = sub(count, _T_130) @[Broadcast.scala 258:20] + node _T_132 = asUInt(_T_131) @[Broadcast.scala 258:20] + node _T_133 = tail(_T_132, 1) @[Broadcast.scala 258:20] + count <= _T_133 @[Broadcast.scala 258:11] + skip @[Broadcast.scala 256:39] + io.idle <= idle @[Broadcast.scala 261:11] + io.source <= source @[Broadcast.scala 262:13] + node _T_134 = shr(address, 6) @[Broadcast.scala 263:22] + io.line <= _T_134 @[Broadcast.scala 263:11] + wire i_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {mask : UInt<8>, data : UInt<64>}} @[Broadcast.scala 265:20] + i_data is invalid @[Broadcast.scala 265:20] + inst o_data of Queue_34 @[Decoupled.scala 253:19] + o_data.io is invalid + o_data.clock <= clock + o_data.reset <= reset + o_data.io.enq.valid <= i_data.valid @[Decoupled.scala 254:20] + o_data.io.enq.bits <- i_data.bits @[Decoupled.scala 255:19] + i_data.ready <= o_data.io.enq.ready @[Decoupled.scala 256:15] + node _T_163 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 268:29] + node _T_164 = or(idle, _T_163) @[Broadcast.scala 268:26] + node _T_165 = and(_T_164, i_data.ready) @[Broadcast.scala 268:45] + io.in_a.ready <= _T_165 @[Broadcast.scala 268:17] + node _T_167 = eq(io.in_a_first, UInt<1>("h00")) @[Broadcast.scala 269:28] + node _T_168 = or(idle, _T_167) @[Broadcast.scala 269:25] + node _T_169 = and(_T_168, io.in_a.valid) @[Broadcast.scala 269:44] + i_data.valid <= _T_169 @[Broadcast.scala 269:16] + i_data.bits.mask <= io.in_a.bits.mask @[Broadcast.scala 270:20] + i_data.bits.data <= io.in_a.bits.data @[Broadcast.scala 271:20] + node probe_done = eq(count, UInt<1>("h00")) @[Broadcast.scala 273:26] + node acquire = eq(opcode, UInt<3>("h06")) @[Broadcast.scala 274:24] + wire _T_173 : UInt<2> @[Broadcast.scala 276:40] + _T_173 is invalid @[Broadcast.scala 276:40] + node _T_180 = eq(UInt<2>("h02"), param) @[Mux.scala 46:19] + node _T_181 = mux(_T_180, UInt<2>("h03"), _T_173) @[Mux.scala 46:16] + node _T_182 = eq(UInt<2>("h01"), param) @[Mux.scala 46:19] + node _T_183 = mux(_T_182, UInt<2>("h03"), _T_181) @[Mux.scala 46:16] + node _T_184 = eq(UInt<2>("h00"), param) @[Mux.scala 46:19] + node transform = mux(_T_184, UInt<2>("h02"), _T_183) @[Mux.scala 46:16] + node _T_185 = and(io.out_a.ready, probe_done) @[Broadcast.scala 281:34] + o_data.io.deq.ready <= _T_185 @[Broadcast.scala 281:16] + node _T_186 = and(o_data.io.deq.valid, probe_done) @[Broadcast.scala 282:34] + io.out_a.valid <= _T_186 @[Broadcast.scala 282:18] + node _T_188 = mux(acquire, UInt<3>("h04"), opcode) @[Broadcast.scala 283:31] + io.out_a.bits.opcode <= _T_188 @[Broadcast.scala 283:25] + node _T_190 = mux(acquire, UInt<1>("h00"), param) @[Broadcast.scala 284:31] + io.out_a.bits.param <= _T_190 @[Broadcast.scala 284:25] + io.out_a.bits.size <= size @[Broadcast.scala 285:25] + node _T_192 = mux(acquire, transform, UInt<1>("h00")) @[Broadcast.scala 286:35] + node _T_193 = cat(_T_192, source) @[Cat.scala 30:58] + io.out_a.bits.source <= _T_193 @[Broadcast.scala 286:25] + io.out_a.bits.address <= address @[Broadcast.scala 287:25] + io.out_a.bits.mask <= o_data.io.deq.bits.mask @[Broadcast.scala 288:25] + io.out_a.bits.data <= o_data.io.deq.bits.data @[Broadcast.scala 289:25] + + module TLBroadcast_mem_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + inst TLBroadcastTracker of TLBroadcastTracker @[Broadcast.scala 73:15] + TLBroadcastTracker.io is invalid + TLBroadcastTracker.clock <= clock + TLBroadcastTracker.reset <= reset + inst TLBroadcastTracker_1 of TLBroadcastTracker_1 @[Broadcast.scala 73:15] + TLBroadcastTracker_1.io is invalid + TLBroadcastTracker_1.clock <= clock + TLBroadcastTracker_1.reset <= reset + inst TLBroadcastTracker_2 of TLBroadcastTracker_2 @[Broadcast.scala 73:15] + TLBroadcastTracker_2.io is invalid + TLBroadcastTracker_2.clock <= clock + TLBroadcastTracker_2.reset <= reset + inst TLBroadcastTracker_3 of TLBroadcastTracker_3 @[Broadcast.scala 73:15] + TLBroadcastTracker_3.io is invalid + TLBroadcastTracker_3.clock <= clock + TLBroadcastTracker_3.reset <= reset + io.in.0.e.ready <= UInt<1>("h01") @[Broadcast.scala 77:18] + node _T_533 = dshl(UInt<1>("h01"), io.in.0.e.bits.sink) @[OneHot.scala 47:11] + node _T_534 = bits(_T_533, 0, 0) @[Broadcast.scala 78:46] + node _T_535 = bits(_T_533, 1, 1) @[Broadcast.scala 78:46] + node _T_536 = bits(_T_533, 2, 2) @[Broadcast.scala 78:46] + node _T_537 = bits(_T_533, 3, 3) @[Broadcast.scala 78:46] + node _T_538 = and(io.in.0.e.ready, io.in.0.e.valid) @[Decoupled.scala 30:37] + node _T_539 = and(_T_534, _T_538) @[Broadcast.scala 79:34] + TLBroadcastTracker.io.e_last <= _T_539 @[Broadcast.scala 79:24] + node _T_540 = and(io.in.0.e.ready, io.in.0.e.valid) @[Decoupled.scala 30:37] + node _T_541 = and(_T_535, _T_540) @[Broadcast.scala 79:34] + TLBroadcastTracker_1.io.e_last <= _T_541 @[Broadcast.scala 79:24] + node _T_542 = and(io.in.0.e.ready, io.in.0.e.valid) @[Decoupled.scala 30:37] + node _T_543 = and(_T_536, _T_542) @[Broadcast.scala 79:34] + TLBroadcastTracker_2.io.e_last <= _T_543 @[Broadcast.scala 79:24] + node _T_544 = and(io.in.0.e.ready, io.in.0.e.valid) @[Decoupled.scala 30:37] + node _T_545 = and(_T_537, _T_544) @[Broadcast.scala 79:34] + TLBroadcastTracker_3.io.e_last <= _T_545 @[Broadcast.scala 79:24] + node _T_546 = bits(io.out.0.d.bits.source, 4, 3) @[Broadcast.scala 84:37] + node _T_548 = eq(_T_546, UInt<1>("h01")) @[Broadcast.scala 85:27] + node _T_549 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + wire _T_550 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Broadcast.scala 87:26] + _T_550 is invalid @[Broadcast.scala 87:26] + node _T_574 = eq(TLBroadcastTracker.io.idle, UInt<1>("h00")) @[Broadcast.scala 88:49] + node _T_575 = eq(TLBroadcastTracker.io.source, _T_550.bits.source) @[Broadcast.scala 88:69] + node _T_576 = and(_T_574, _T_575) @[Broadcast.scala 88:57] + node _T_578 = eq(TLBroadcastTracker_1.io.idle, UInt<1>("h00")) @[Broadcast.scala 88:49] + node _T_579 = eq(TLBroadcastTracker_1.io.source, _T_550.bits.source) @[Broadcast.scala 88:69] + node _T_580 = and(_T_578, _T_579) @[Broadcast.scala 88:57] + node _T_582 = eq(TLBroadcastTracker_2.io.idle, UInt<1>("h00")) @[Broadcast.scala 88:49] + node _T_583 = eq(TLBroadcastTracker_2.io.source, _T_550.bits.source) @[Broadcast.scala 88:69] + node _T_584 = and(_T_582, _T_583) @[Broadcast.scala 88:57] + node _T_586 = eq(TLBroadcastTracker_3.io.idle, UInt<1>("h00")) @[Broadcast.scala 88:49] + node _T_587 = eq(TLBroadcastTracker_3.io.source, _T_550.bits.source) @[Broadcast.scala 88:69] + node _T_588 = and(_T_586, _T_587) @[Broadcast.scala 88:57] + wire _T_591 : UInt<1>[4] @[Broadcast.scala 88:28] + _T_591 is invalid @[Broadcast.scala 88:28] + _T_591[0] <= _T_576 @[Broadcast.scala 88:28] + _T_591[1] <= _T_580 @[Broadcast.scala 88:28] + _T_591[2] <= _T_584 @[Broadcast.scala 88:28] + _T_591[3] <= _T_588 @[Broadcast.scala 88:28] + node _T_598 = cat(_T_591[1], _T_591[0]) @[Broadcast.scala 88:97] + node _T_599 = cat(_T_591[3], _T_591[2]) @[Broadcast.scala 88:97] + node _T_600 = cat(_T_599, _T_598) @[Broadcast.scala 88:97] + node _T_602 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Broadcast.scala 90:15] + node _T_604 = eq(_T_548, UInt<1>("h00")) @[Broadcast.scala 90:31] + node _T_605 = or(_T_602, _T_604) @[Broadcast.scala 90:28] + node _T_607 = eq(io.out.0.d.bits.opcode, UInt<1>("h00")) @[Broadcast.scala 90:60] + node _T_608 = or(_T_605, _T_607) @[Broadcast.scala 90:39] + node _T_609 = or(_T_608, reset) @[Broadcast.scala 90:14] + node _T_611 = eq(_T_609, UInt<1>("h00")) @[Broadcast.scala 90:14] + when _T_611 : @[Broadcast.scala 90:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:90 assert (!out.d.valid || !d_drop || out.d.bits.opcode === TLMessages.AccessAck)\n") @[Broadcast.scala 90:14] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 90:14] + skip @[Broadcast.scala 90:14] + node _T_612 = or(_T_550.ready, _T_548) @[Broadcast.scala 92:37] + io.out.0.d.ready <= _T_612 @[Broadcast.scala 92:19] + node _T_614 = eq(_T_548, UInt<1>("h00")) @[Broadcast.scala 93:40] + node _T_615 = and(io.out.0.d.valid, _T_614) @[Broadcast.scala 93:37] + _T_550.valid <= _T_615 @[Broadcast.scala 93:22] + _T_550.bits <- io.out.0.d.bits @[Broadcast.scala 94:21] + node _T_616 = bits(_T_546, 1, 1) @[Broadcast.scala 95:19] + when _T_616 : @[Broadcast.scala 95:24] + node _T_619 = mux(_T_549, UInt<3>("h05"), UInt<3>("h06")) @[Broadcast.scala 96:36] + _T_550.bits.opcode <= _T_619 @[Broadcast.scala 96:30] + node _T_620 = bits(_T_546, 0, 0) @[Broadcast.scala 97:58] + node _T_623 = mux(_T_620, UInt<2>("h00"), UInt<2>("h01")) @[Broadcast.scala 97:51] + node _T_625 = mux(_T_549, _T_623, UInt<1>("h00")) @[Broadcast.scala 97:36] + _T_550.bits.param <= _T_625 @[Broadcast.scala 97:30] + skip @[Broadcast.scala 95:24] + node _T_626 = bits(_T_600, 3, 2) @[OneHot.scala 26:18] + node _T_627 = bits(_T_600, 1, 0) @[OneHot.scala 27:18] + node _T_629 = neq(_T_626, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_630 = or(_T_626, _T_627) @[OneHot.scala 28:28] + node _T_631 = bits(_T_630, 1, 1) @[CircuitMath.scala 30:8] + node _T_632 = cat(_T_629, _T_631) @[Cat.scala 30:58] + _T_550.bits.sink <= _T_632 @[Broadcast.scala 99:26] + node _T_634 = eq(_T_550.valid, UInt<1>("h00")) @[Broadcast.scala 100:15] + node _T_636 = neq(_T_600, UInt<1>("h00")) @[Broadcast.scala 100:50] + node _T_638 = eq(_T_550.bits.opcode, UInt<3>("h06")) @[Broadcast.scala 100:77] + node _T_639 = or(_T_636, _T_638) @[Broadcast.scala 100:53] + node _T_640 = or(_T_634, _T_639) @[Broadcast.scala 100:31] + node _T_641 = or(_T_640, reset) @[Broadcast.scala 100:14] + node _T_643 = eq(_T_641, UInt<1>("h00")) @[Broadcast.scala 100:14] + when _T_643 : @[Broadcast.scala 100:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Broadcast.scala:100 assert (!d_normal.valid || (d_trackerOH.orR() || d_normal.bits.opcode === TLMessages.ReleaseAck))\n") @[Broadcast.scala 100:14] + stop(clock, UInt<1>(1), 1) @[Broadcast.scala 100:14] + skip @[Broadcast.scala 100:14] + node _T_644 = bits(_T_546, 1, 1) @[Broadcast.scala 103:44] + node _T_646 = eq(_T_644, UInt<1>("h00")) @[Broadcast.scala 103:37] + node _T_647 = or(_T_549, _T_646) @[Broadcast.scala 103:34] + node _T_648 = and(_T_550.ready, _T_550.valid) @[Decoupled.scala 30:37] + node _T_650 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_651 = dshl(_T_650, _T_550.bits.size) @[package.scala 19:71] + node _T_652 = bits(_T_651, 5, 0) @[package.scala 19:76] + node _T_653 = not(_T_652) @[package.scala 19:40] + node _T_654 = shr(_T_653, 3) @[Edges.scala 198:59] + node _T_655 = bits(_T_550.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_657 = mux(_T_655, _T_654, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_659 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_661 = sub(_T_659, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_662 = asUInt(_T_661) @[Edges.scala 208:28] + node _T_663 = tail(_T_662, 1) @[Edges.scala 208:28] + node _T_665 = eq(_T_659, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_667 = eq(_T_659, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_669 = eq(_T_657, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_670 = or(_T_667, _T_669) @[Edges.scala 210:37] + node _T_671 = and(_T_670, _T_648) @[Edges.scala 211:22] + node _T_672 = not(_T_663) @[Edges.scala 212:27] + node _T_673 = and(_T_657, _T_672) @[Edges.scala 212:25] + when _T_648 : @[Edges.scala 213:17] + node _T_674 = mux(_T_665, _T_657, _T_663) @[Edges.scala 214:21] + _T_659 <= _T_674 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_675 = bits(_T_600, 0, 0) @[Broadcast.scala 105:33] + node _T_676 = bits(_T_600, 1, 1) @[Broadcast.scala 105:33] + node _T_677 = bits(_T_600, 2, 2) @[Broadcast.scala 105:33] + node _T_678 = bits(_T_600, 3, 3) @[Broadcast.scala 105:33] + node _T_679 = and(_T_550.ready, _T_550.valid) @[Decoupled.scala 30:37] + node _T_680 = and(_T_675, _T_679) @[Broadcast.scala 106:34] + node _T_681 = and(_T_680, _T_647) @[Broadcast.scala 106:53] + node _T_682 = and(_T_681, _T_670) @[Broadcast.scala 106:67] + TLBroadcastTracker.io.d_last <= _T_682 @[Broadcast.scala 106:24] + node _T_683 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + node _T_684 = and(_T_675, _T_683) @[Broadcast.scala 107:37] + node _T_685 = and(_T_684, _T_548) @[Broadcast.scala 107:53] + TLBroadcastTracker.io.probedack <= _T_685 @[Broadcast.scala 107:27] + node _T_686 = and(_T_550.ready, _T_550.valid) @[Decoupled.scala 30:37] + node _T_687 = and(_T_676, _T_686) @[Broadcast.scala 106:34] + node _T_688 = and(_T_687, _T_647) @[Broadcast.scala 106:53] + node _T_689 = and(_T_688, _T_670) @[Broadcast.scala 106:67] + TLBroadcastTracker_1.io.d_last <= _T_689 @[Broadcast.scala 106:24] + node _T_690 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + node _T_691 = and(_T_676, _T_690) @[Broadcast.scala 107:37] + node _T_692 = and(_T_691, _T_548) @[Broadcast.scala 107:53] + TLBroadcastTracker_1.io.probedack <= _T_692 @[Broadcast.scala 107:27] + node _T_693 = and(_T_550.ready, _T_550.valid) @[Decoupled.scala 30:37] + node _T_694 = and(_T_677, _T_693) @[Broadcast.scala 106:34] + node _T_695 = and(_T_694, _T_647) @[Broadcast.scala 106:53] + node _T_696 = and(_T_695, _T_670) @[Broadcast.scala 106:67] + TLBroadcastTracker_2.io.d_last <= _T_696 @[Broadcast.scala 106:24] + node _T_697 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + node _T_698 = and(_T_677, _T_697) @[Broadcast.scala 107:37] + node _T_699 = and(_T_698, _T_548) @[Broadcast.scala 107:53] + TLBroadcastTracker_2.io.probedack <= _T_699 @[Broadcast.scala 107:27] + node _T_700 = and(_T_550.ready, _T_550.valid) @[Decoupled.scala 30:37] + node _T_701 = and(_T_678, _T_700) @[Broadcast.scala 106:34] + node _T_702 = and(_T_701, _T_647) @[Broadcast.scala 106:53] + node _T_703 = and(_T_702, _T_670) @[Broadcast.scala 106:67] + TLBroadcastTracker_3.io.d_last <= _T_703 @[Broadcast.scala 106:24] + node _T_704 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + node _T_705 = and(_T_678, _T_704) @[Broadcast.scala 107:37] + node _T_706 = and(_T_705, _T_548) @[Broadcast.scala 107:53] + TLBroadcastTracker_3.io.probedack <= _T_706 @[Broadcast.scala 107:27] + node _T_708 = eq(io.in.0.c.bits.opcode, UInt<3>("h04")) @[Broadcast.scala 116:45] + node _T_710 = eq(io.in.0.c.bits.opcode, UInt<3>("h05")) @[Broadcast.scala 117:45] + node _T_712 = eq(io.in.0.c.bits.opcode, UInt<3>("h07")) @[Broadcast.scala 118:45] + node _T_714 = eq(io.in.0.c.bits.opcode, UInt<3>("h06")) @[Broadcast.scala 119:45] + node _T_715 = shr(io.in.0.c.bits.address, 6) @[Broadcast.scala 120:78] + node _T_716 = eq(TLBroadcastTracker.io.line, _T_715) @[Broadcast.scala 120:55] + node _T_717 = shr(io.in.0.c.bits.address, 6) @[Broadcast.scala 120:78] + node _T_718 = eq(TLBroadcastTracker_1.io.line, _T_717) @[Broadcast.scala 120:55] + node _T_719 = shr(io.in.0.c.bits.address, 6) @[Broadcast.scala 120:78] + node _T_720 = eq(TLBroadcastTracker_2.io.line, _T_719) @[Broadcast.scala 120:55] + node _T_721 = shr(io.in.0.c.bits.address, 6) @[Broadcast.scala 120:78] + node _T_722 = eq(TLBroadcastTracker_3.io.line, _T_721) @[Broadcast.scala 120:55] + node _T_724 = mux(_T_716, TLBroadcastTracker.io.source, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_726 = mux(_T_718, TLBroadcastTracker_1.io.source, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_728 = mux(_T_720, TLBroadcastTracker_2.io.source, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_730 = mux(_T_722, TLBroadcastTracker_3.io.source, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_732 = or(_T_724, _T_726) @[Mux.scala 19:72] + node _T_733 = or(_T_732, _T_728) @[Mux.scala 19:72] + node _T_734 = or(_T_733, _T_730) @[Mux.scala 19:72] + wire _T_736 : UInt @[Mux.scala 19:72] + _T_736 is invalid @[Mux.scala 19:72] + _T_736 <= _T_734 @[Mux.scala 19:72] + node _T_737 = and(io.in.0.c.ready, io.in.0.c.valid) @[Decoupled.scala 30:37] + node _T_738 = and(_T_737, _T_708) @[Broadcast.scala 125:42] + node _T_739 = and(_T_738, _T_716) @[Broadcast.scala 125:56] + TLBroadcastTracker.io.probenack <= _T_739 @[Broadcast.scala 125:27] + node _T_740 = and(io.in.0.c.ready, io.in.0.c.valid) @[Decoupled.scala 30:37] + node _T_741 = and(_T_740, _T_708) @[Broadcast.scala 125:42] + node _T_742 = and(_T_741, _T_718) @[Broadcast.scala 125:56] + TLBroadcastTracker_1.io.probenack <= _T_742 @[Broadcast.scala 125:27] + node _T_743 = and(io.in.0.c.ready, io.in.0.c.valid) @[Decoupled.scala 30:37] + node _T_744 = and(_T_743, _T_708) @[Broadcast.scala 125:42] + node _T_745 = and(_T_744, _T_720) @[Broadcast.scala 125:56] + TLBroadcastTracker_2.io.probenack <= _T_745 @[Broadcast.scala 125:27] + node _T_746 = and(io.in.0.c.ready, io.in.0.c.valid) @[Decoupled.scala 30:37] + node _T_747 = and(_T_746, _T_708) @[Broadcast.scala 125:42] + node _T_748 = and(_T_747, _T_722) @[Broadcast.scala 125:56] + TLBroadcastTracker_3.io.probenack <= _T_748 @[Broadcast.scala 125:27] + wire _T_749 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Broadcast.scala 128:28] + _T_749 is invalid @[Broadcast.scala 128:28] + wire _T_772 : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Broadcast.scala 129:25] + _T_772 is invalid @[Broadcast.scala 129:25] + node _T_793 = mux(_T_714, _T_749.ready, _T_772.ready) @[Broadcast.scala 131:38] + node _T_794 = or(_T_708, _T_793) @[Broadcast.scala 131:32] + io.in.0.c.ready <= _T_794 @[Broadcast.scala 131:18] + node _T_795 = and(io.in.0.c.valid, _T_714) @[Broadcast.scala 133:38] + _T_749.valid <= _T_795 @[Broadcast.scala 133:24] + wire _T_806 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 516:17] + _T_806 is invalid @[Edges.scala 516:17] + _T_806.opcode <= UInt<3>("h06") @[Edges.scala 517:15] + _T_806.param <= UInt<1>("h00") @[Edges.scala 518:15] + _T_806.size <= io.in.0.c.bits.size @[Edges.scala 519:15] + _T_806.source <= io.in.0.c.bits.source @[Edges.scala 520:15] + _T_806.sink <= UInt<1>("h00") @[Edges.scala 521:15] + node _T_817 = bits(io.in.0.c.bits.address, 2, 0) @[Edges.scala 172:47] + _T_806.addr_lo <= _T_817 @[Edges.scala 522:15] + _T_806.data <= UInt<1>("h00") @[Edges.scala 523:15] + _T_806.error <= UInt<1>("h00") @[Edges.scala 524:15] + _T_749.bits <- _T_806 @[Broadcast.scala 134:24] + node _T_822 = mux(_T_712, UInt<2>("h02"), UInt<1>("h01")) @[Broadcast.scala 136:25] + node _T_823 = mux(_T_712, io.in.0.c.bits.source, _T_736) @[Broadcast.scala 137:25] + node _T_824 = or(_T_710, _T_712) @[Broadcast.scala 138:54] + node _T_825 = and(io.in.0.c.valid, _T_824) @[Broadcast.scala 138:35] + _T_772.valid <= _T_825 @[Broadcast.scala 138:21] + node _T_826 = cat(_T_822, _T_823) @[Cat.scala 30:58] + node _T_829 = leq(UInt<1>("h00"), io.in.0.c.bits.size) @[Parameters.scala 63:32] + node _T_831 = leq(io.in.0.c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_832 = and(_T_829, _T_831) @[Parameters.scala 63:37] + node _T_833 = or(UInt<1>("h00"), _T_832) @[Parameters.scala 132:31] + node _T_835 = xor(io.in.0.c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = and(_T_833, _T_841) @[Parameters.scala 132:56] + node _T_845 = leq(UInt<1>("h00"), io.in.0.c.bits.size) @[Parameters.scala 63:32] + node _T_847 = leq(io.in.0.c.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_848 = and(_T_845, _T_847) @[Parameters.scala 63:37] + node _T_849 = or(UInt<1>("h00"), _T_848) @[Parameters.scala 132:31] + node _T_851 = xor(io.in.0.c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_852 = cvt(_T_851) @[Parameters.scala 117:49] + node _T_854 = and(_T_852, asSInt(UInt<33>("h080000000"))) @[Parameters.scala 117:52] + node _T_855 = asSInt(_T_854) @[Parameters.scala 117:52] + node _T_857 = eq(_T_855, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_858 = and(_T_849, _T_857) @[Parameters.scala 132:56] + node _T_860 = or(UInt<1>("h00"), _T_842) @[Parameters.scala 134:30] + node _T_861 = or(_T_860, _T_858) @[Parameters.scala 134:30] + wire _T_870 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 356:17] + _T_870 is invalid @[Edges.scala 356:17] + _T_870.opcode <= UInt<1>("h00") @[Edges.scala 357:15] + _T_870.param <= UInt<1>("h00") @[Edges.scala 358:15] + _T_870.size <= io.in.0.c.bits.size @[Edges.scala 359:15] + _T_870.source <= _T_826 @[Edges.scala 360:15] + _T_870.address <= io.in.0.c.bits.address @[Edges.scala 361:15] + node _T_881 = bits(io.in.0.c.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_882 = dshl(UInt<1>("h01"), _T_881) @[OneHot.scala 49:12] + node _T_883 = bits(_T_882, 2, 0) @[OneHot.scala 49:37] + node _T_885 = geq(io.in.0.c.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_887 = bits(_T_883, 2, 2) @[package.scala 44:26] + node _T_888 = bits(io.in.0.c.bits.address, 2, 2) @[package.scala 45:26] + node _T_890 = eq(_T_888, UInt<1>("h00")) @[package.scala 46:20] + node _T_891 = and(UInt<1>("h01"), _T_890) @[package.scala 49:27] + node _T_892 = and(_T_887, _T_891) @[package.scala 50:38] + node _T_893 = or(_T_885, _T_892) @[package.scala 50:29] + node _T_894 = and(UInt<1>("h01"), _T_888) @[package.scala 49:27] + node _T_895 = and(_T_887, _T_894) @[package.scala 50:38] + node _T_896 = or(_T_885, _T_895) @[package.scala 50:29] + node _T_897 = bits(_T_883, 1, 1) @[package.scala 44:26] + node _T_898 = bits(io.in.0.c.bits.address, 1, 1) @[package.scala 45:26] + node _T_900 = eq(_T_898, UInt<1>("h00")) @[package.scala 46:20] + node _T_901 = and(_T_891, _T_900) @[package.scala 49:27] + node _T_902 = and(_T_897, _T_901) @[package.scala 50:38] + node _T_903 = or(_T_893, _T_902) @[package.scala 50:29] + node _T_904 = and(_T_891, _T_898) @[package.scala 49:27] + node _T_905 = and(_T_897, _T_904) @[package.scala 50:38] + node _T_906 = or(_T_893, _T_905) @[package.scala 50:29] + node _T_907 = and(_T_894, _T_900) @[package.scala 49:27] + node _T_908 = and(_T_897, _T_907) @[package.scala 50:38] + node _T_909 = or(_T_896, _T_908) @[package.scala 50:29] + node _T_910 = and(_T_894, _T_898) @[package.scala 49:27] + node _T_911 = and(_T_897, _T_910) @[package.scala 50:38] + node _T_912 = or(_T_896, _T_911) @[package.scala 50:29] + node _T_913 = bits(_T_883, 0, 0) @[package.scala 44:26] + node _T_914 = bits(io.in.0.c.bits.address, 0, 0) @[package.scala 45:26] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[package.scala 46:20] + node _T_917 = and(_T_901, _T_916) @[package.scala 49:27] + node _T_918 = and(_T_913, _T_917) @[package.scala 50:38] + node _T_919 = or(_T_903, _T_918) @[package.scala 50:29] + node _T_920 = and(_T_901, _T_914) @[package.scala 49:27] + node _T_921 = and(_T_913, _T_920) @[package.scala 50:38] + node _T_922 = or(_T_903, _T_921) @[package.scala 50:29] + node _T_923 = and(_T_904, _T_916) @[package.scala 49:27] + node _T_924 = and(_T_913, _T_923) @[package.scala 50:38] + node _T_925 = or(_T_906, _T_924) @[package.scala 50:29] + node _T_926 = and(_T_904, _T_914) @[package.scala 49:27] + node _T_927 = and(_T_913, _T_926) @[package.scala 50:38] + node _T_928 = or(_T_906, _T_927) @[package.scala 50:29] + node _T_929 = and(_T_907, _T_916) @[package.scala 49:27] + node _T_930 = and(_T_913, _T_929) @[package.scala 50:38] + node _T_931 = or(_T_909, _T_930) @[package.scala 50:29] + node _T_932 = and(_T_907, _T_914) @[package.scala 49:27] + node _T_933 = and(_T_913, _T_932) @[package.scala 50:38] + node _T_934 = or(_T_909, _T_933) @[package.scala 50:29] + node _T_935 = and(_T_910, _T_916) @[package.scala 49:27] + node _T_936 = and(_T_913, _T_935) @[package.scala 50:38] + node _T_937 = or(_T_912, _T_936) @[package.scala 50:29] + node _T_938 = and(_T_910, _T_914) @[package.scala 49:27] + node _T_939 = and(_T_913, _T_938) @[package.scala 50:38] + node _T_940 = or(_T_912, _T_939) @[package.scala 50:29] + node _T_941 = cat(_T_922, _T_919) @[Cat.scala 30:58] + node _T_942 = cat(_T_928, _T_925) @[Cat.scala 30:58] + node _T_943 = cat(_T_942, _T_941) @[Cat.scala 30:58] + node _T_944 = cat(_T_934, _T_931) @[Cat.scala 30:58] + node _T_945 = cat(_T_940, _T_937) @[Cat.scala 30:58] + node _T_946 = cat(_T_945, _T_944) @[Cat.scala 30:58] + node _T_947 = cat(_T_946, _T_943) @[Cat.scala 30:58] + _T_870.mask <= _T_947 @[Edges.scala 362:15] + _T_870.data <= io.in.0.c.bits.data @[Edges.scala 363:15] + _T_772.bits <- _T_870 @[Broadcast.scala 139:20] + node _T_949 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_950 = dshl(_T_949, _T_749.bits.size) @[package.scala 19:71] + node _T_951 = bits(_T_950, 7, 0) @[package.scala 19:76] + node _T_952 = not(_T_951) @[package.scala 19:40] + node _T_953 = shr(_T_952, 3) @[Edges.scala 198:59] + node _T_954 = bits(_T_749.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_956 = mux(_T_954, _T_953, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_958 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_959 = dshl(_T_958, _T_550.bits.size) @[package.scala 19:71] + node _T_960 = bits(_T_959, 7, 0) @[package.scala 19:76] + node _T_961 = not(_T_960) @[package.scala 19:40] + node _T_962 = shr(_T_961, 3) @[Edges.scala 198:59] + node _T_963 = bits(_T_550.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_965 = mux(_T_963, _T_962, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_967 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_970 = and(_T_969, io.in.0.d.ready) @[Arbiter.scala 35:24] + node _T_973 = eq(_T_749.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_974 = and(UInt<1>("h01"), _T_973) @[Arbiter.scala 14:35] + node _T_976 = eq(_T_550.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_977 = and(_T_974, _T_976) @[Arbiter.scala 14:35] + wire _T_980 : UInt<1>[2] @[Arbiter.scala 40:23] + _T_980 is invalid @[Arbiter.scala 40:23] + _T_980[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_980[1] <= _T_974 @[Arbiter.scala 40:23] + node _T_985 = and(_T_980[0], _T_749.valid) @[Arbiter.scala 42:65] + node _T_986 = and(_T_980[1], _T_550.valid) @[Arbiter.scala 42:65] + wire _T_989 : UInt<1>[2] @[Arbiter.scala 42:23] + _T_989 is invalid @[Arbiter.scala 42:23] + _T_989[0] <= _T_985 @[Arbiter.scala 42:23] + _T_989[1] <= _T_986 @[Arbiter.scala 42:23] + node _T_995 = or(UInt<1>("h00"), _T_989[0]) @[Arbiter.scala 47:52] + node _T_996 = or(_T_995, _T_989[1]) @[Arbiter.scala 47:52] + node _T_998 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1000 = eq(_T_989[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1001 = or(_T_998, _T_1000) @[Arbiter.scala 48:59] + node _T_1003 = eq(_T_995, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1005 = eq(_T_989[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1006 = or(_T_1003, _T_1005) @[Arbiter.scala 48:59] + node _T_1007 = and(_T_1001, _T_1006) @[Arbiter.scala 48:77] + node _T_1008 = or(_T_1007, reset) @[Arbiter.scala 48:13] + node _T_1010 = eq(_T_1008, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_1010 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_1011 = or(_T_749.valid, _T_550.valid) @[Arbiter.scala 50:31] + node _T_1013 = eq(_T_1011, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_1014 = or(_T_989[0], _T_989[1]) @[Arbiter.scala 50:54] + node _T_1015 = or(_T_1013, _T_1014) @[Arbiter.scala 50:36] + node _T_1016 = or(_T_1015, reset) @[Arbiter.scala 50:14] + node _T_1018 = eq(_T_1016, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_1018 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_1020 = mux(_T_989[0], _T_956, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1022 = mux(_T_989[1], _T_965, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1023 = or(_T_1020, _T_1022) @[Arbiter.scala 54:44] + node _T_1024 = and(io.in.0.d.ready, io.in.0.d.valid) @[Decoupled.scala 30:37] + node _T_1025 = sub(_T_967, _T_1024) @[Arbiter.scala 55:52] + node _T_1026 = asUInt(_T_1025) @[Arbiter.scala 55:52] + node _T_1027 = tail(_T_1026, 1) @[Arbiter.scala 55:52] + node _T_1028 = mux(_T_970, _T_1023, _T_1027) @[Arbiter.scala 55:23] + _T_967 <= _T_1028 @[Arbiter.scala 55:17] + wire _T_1033 : UInt<1>[2] @[Arbiter.scala 58:49] + _T_1033 is invalid @[Arbiter.scala 58:49] + _T_1033[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1033[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_1038 : UInt<1>[2], clock with : (reset => (reset, _T_1033)) @[Reg.scala 26:44] + node _T_1046 = mux(_T_969, _T_989, _T_1038) @[Arbiter.scala 59:25] + _T_1038 <- _T_1046 @[Arbiter.scala 60:13] + node _T_1054 = mux(_T_969, _T_980, _T_1038) @[Arbiter.scala 63:26] + node _T_1062 = and(io.in.0.d.ready, _T_1054[0]) @[Arbiter.scala 65:33] + _T_749.ready <= _T_1062 @[Arbiter.scala 65:19] + node _T_1063 = and(io.in.0.d.ready, _T_1054[1]) @[Arbiter.scala 65:33] + _T_550.ready <= _T_1063 @[Arbiter.scala 65:19] + node _T_1064 = or(_T_749.valid, _T_550.valid) @[Arbiter.scala 71:46] + node _T_1066 = mux(_T_1038[0], _T_749.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1068 = mux(_T_1038[1], _T_550.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1070 = or(_T_1066, _T_1068) @[Mux.scala 19:72] + wire _T_1072 : UInt<1> @[Mux.scala 19:72] + _T_1072 is invalid @[Mux.scala 19:72] + _T_1072 <= _T_1070 @[Mux.scala 19:72] + node _T_1073 = mux(_T_969, _T_1064, _T_1072) @[Arbiter.scala 71:24] + io.in.0.d.valid <= _T_1073 @[Arbiter.scala 71:18] + node _T_1074 = cat(_T_749.bits.data, _T_749.bits.error) @[Mux.scala 19:72] + node _T_1075 = cat(_T_749.bits.sink, _T_749.bits.addr_lo) @[Mux.scala 19:72] + node _T_1076 = cat(_T_1075, _T_1074) @[Mux.scala 19:72] + node _T_1077 = cat(_T_749.bits.size, _T_749.bits.source) @[Mux.scala 19:72] + node _T_1078 = cat(_T_749.bits.opcode, _T_749.bits.param) @[Mux.scala 19:72] + node _T_1079 = cat(_T_1078, _T_1077) @[Mux.scala 19:72] + node _T_1080 = cat(_T_1079, _T_1076) @[Mux.scala 19:72] + node _T_1082 = mux(_T_1046[0], _T_1080, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1083 = cat(_T_550.bits.data, _T_550.bits.error) @[Mux.scala 19:72] + node _T_1084 = cat(_T_550.bits.sink, _T_550.bits.addr_lo) @[Mux.scala 19:72] + node _T_1085 = cat(_T_1084, _T_1083) @[Mux.scala 19:72] + node _T_1086 = cat(_T_550.bits.size, _T_550.bits.source) @[Mux.scala 19:72] + node _T_1087 = cat(_T_550.bits.opcode, _T_550.bits.param) @[Mux.scala 19:72] + node _T_1088 = cat(_T_1087, _T_1086) @[Mux.scala 19:72] + node _T_1089 = cat(_T_1088, _T_1085) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1046[1], _T_1089, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1101 = or(_T_1082, _T_1091) @[Mux.scala 19:72] + wire _T_1111 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Mux.scala 19:72] + _T_1111 is invalid @[Mux.scala 19:72] + wire _T_1121 : UInt<81> + _T_1121 is invalid + _T_1121 <= _T_1101 + node _T_1122 = bits(_T_1121, 0, 0) @[Mux.scala 19:72] + _T_1111.error <= _T_1122 @[Mux.scala 19:72] + node _T_1123 = bits(_T_1121, 64, 1) @[Mux.scala 19:72] + _T_1111.data <= _T_1123 @[Mux.scala 19:72] + node _T_1124 = bits(_T_1121, 67, 65) @[Mux.scala 19:72] + _T_1111.addr_lo <= _T_1124 @[Mux.scala 19:72] + node _T_1125 = bits(_T_1121, 69, 68) @[Mux.scala 19:72] + _T_1111.sink <= _T_1125 @[Mux.scala 19:72] + node _T_1126 = bits(_T_1121, 72, 70) @[Mux.scala 19:72] + _T_1111.source <= _T_1126 @[Mux.scala 19:72] + node _T_1127 = bits(_T_1121, 75, 73) @[Mux.scala 19:72] + _T_1111.size <= _T_1127 @[Mux.scala 19:72] + node _T_1128 = bits(_T_1121, 77, 76) @[Mux.scala 19:72] + _T_1111.param <= _T_1128 @[Mux.scala 19:72] + node _T_1129 = bits(_T_1121, 80, 78) @[Mux.scala 19:72] + _T_1111.opcode <= _T_1129 @[Mux.scala 19:72] + io.in.0.d.bits <- _T_1111 @[Arbiter.scala 72:17] + node _T_1131 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1132 = dshl(_T_1131, _T_772.bits.size) @[package.scala 19:71] + node _T_1133 = bits(_T_1132, 7, 0) @[package.scala 19:76] + node _T_1134 = not(_T_1133) @[package.scala 19:40] + node _T_1135 = shr(_T_1134, 3) @[Edges.scala 198:59] + node _T_1136 = bits(_T_772.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1140 = mux(_T_1138, _T_1135, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_1142 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1143 = dshl(_T_1142, TLBroadcastTracker.io.out_a.bits.size) @[package.scala 19:71] + node _T_1144 = bits(_T_1143, 7, 0) @[package.scala 19:76] + node _T_1145 = not(_T_1144) @[package.scala 19:40] + node _T_1146 = shr(_T_1145, 3) @[Edges.scala 198:59] + node _T_1147 = bits(TLBroadcastTracker.io.out_a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1149 = eq(_T_1147, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1151 = mux(_T_1149, _T_1146, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_1153 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1154 = dshl(_T_1153, TLBroadcastTracker_1.io.out_a.bits.size) @[package.scala 19:71] + node _T_1155 = bits(_T_1154, 7, 0) @[package.scala 19:76] + node _T_1156 = not(_T_1155) @[package.scala 19:40] + node _T_1157 = shr(_T_1156, 3) @[Edges.scala 198:59] + node _T_1158 = bits(TLBroadcastTracker_1.io.out_a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1160 = eq(_T_1158, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1162 = mux(_T_1160, _T_1157, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_1164 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1165 = dshl(_T_1164, TLBroadcastTracker_2.io.out_a.bits.size) @[package.scala 19:71] + node _T_1166 = bits(_T_1165, 7, 0) @[package.scala 19:76] + node _T_1167 = not(_T_1166) @[package.scala 19:40] + node _T_1168 = shr(_T_1167, 3) @[Edges.scala 198:59] + node _T_1169 = bits(TLBroadcastTracker_2.io.out_a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1171 = eq(_T_1169, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1173 = mux(_T_1171, _T_1168, UInt<1>("h00")) @[Edges.scala 199:14] + node _T_1175 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1176 = dshl(_T_1175, TLBroadcastTracker_3.io.out_a.bits.size) @[package.scala 19:71] + node _T_1177 = bits(_T_1176, 7, 0) @[package.scala 19:76] + node _T_1178 = not(_T_1177) @[package.scala 19:40] + node _T_1179 = shr(_T_1178, 3) @[Edges.scala 198:59] + node _T_1180 = bits(TLBroadcastTracker_3.io.out_a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1182 = eq(_T_1180, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1184 = mux(_T_1182, _T_1179, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1186 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_1188 = eq(_T_1186, UInt<1>("h00")) @[Arbiter.scala 34:28] + node _T_1189 = and(_T_1188, io.out.0.a.ready) @[Arbiter.scala 35:24] + node _T_1192 = eq(_T_772.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1193 = and(UInt<1>("h01"), _T_1192) @[Arbiter.scala 14:35] + node _T_1195 = eq(TLBroadcastTracker.io.out_a.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1196 = and(_T_1193, _T_1195) @[Arbiter.scala 14:35] + node _T_1198 = eq(TLBroadcastTracker_1.io.out_a.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1199 = and(_T_1196, _T_1198) @[Arbiter.scala 14:35] + node _T_1201 = eq(TLBroadcastTracker_2.io.out_a.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1202 = and(_T_1199, _T_1201) @[Arbiter.scala 14:35] + node _T_1204 = eq(TLBroadcastTracker_3.io.out_a.valid, UInt<1>("h00")) @[Arbiter.scala 14:38] + node _T_1205 = and(_T_1202, _T_1204) @[Arbiter.scala 14:35] + wire _T_1208 : UInt<1>[5] @[Arbiter.scala 40:23] + _T_1208 is invalid @[Arbiter.scala 40:23] + _T_1208[0] <= UInt<1>("h01") @[Arbiter.scala 40:23] + _T_1208[1] <= _T_1193 @[Arbiter.scala 40:23] + _T_1208[2] <= _T_1196 @[Arbiter.scala 40:23] + _T_1208[3] <= _T_1199 @[Arbiter.scala 40:23] + _T_1208[4] <= _T_1202 @[Arbiter.scala 40:23] + node _T_1216 = and(_T_1208[0], _T_772.valid) @[Arbiter.scala 42:65] + node _T_1217 = and(_T_1208[1], TLBroadcastTracker.io.out_a.valid) @[Arbiter.scala 42:65] + node _T_1218 = and(_T_1208[2], TLBroadcastTracker_1.io.out_a.valid) @[Arbiter.scala 42:65] + node _T_1219 = and(_T_1208[3], TLBroadcastTracker_2.io.out_a.valid) @[Arbiter.scala 42:65] + node _T_1220 = and(_T_1208[4], TLBroadcastTracker_3.io.out_a.valid) @[Arbiter.scala 42:65] + wire _T_1223 : UInt<1>[5] @[Arbiter.scala 42:23] + _T_1223 is invalid @[Arbiter.scala 42:23] + _T_1223[0] <= _T_1216 @[Arbiter.scala 42:23] + _T_1223[1] <= _T_1217 @[Arbiter.scala 42:23] + _T_1223[2] <= _T_1218 @[Arbiter.scala 42:23] + _T_1223[3] <= _T_1219 @[Arbiter.scala 42:23] + _T_1223[4] <= _T_1220 @[Arbiter.scala 42:23] + node _T_1232 = or(UInt<1>("h00"), _T_1223[0]) @[Arbiter.scala 47:52] + node _T_1233 = or(_T_1232, _T_1223[1]) @[Arbiter.scala 47:52] + node _T_1234 = or(_T_1233, _T_1223[2]) @[Arbiter.scala 47:52] + node _T_1235 = or(_T_1234, _T_1223[3]) @[Arbiter.scala 47:52] + node _T_1236 = or(_T_1235, _T_1223[4]) @[Arbiter.scala 47:52] + node _T_1238 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1240 = eq(_T_1223[0], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1241 = or(_T_1238, _T_1240) @[Arbiter.scala 48:59] + node _T_1243 = eq(_T_1232, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1245 = eq(_T_1223[1], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1246 = or(_T_1243, _T_1245) @[Arbiter.scala 48:59] + node _T_1248 = eq(_T_1233, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1250 = eq(_T_1223[2], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1251 = or(_T_1248, _T_1250) @[Arbiter.scala 48:59] + node _T_1253 = eq(_T_1234, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1255 = eq(_T_1223[3], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1256 = or(_T_1253, _T_1255) @[Arbiter.scala 48:59] + node _T_1258 = eq(_T_1235, UInt<1>("h00")) @[Arbiter.scala 48:56] + node _T_1260 = eq(_T_1223[4], UInt<1>("h00")) @[Arbiter.scala 48:62] + node _T_1261 = or(_T_1258, _T_1260) @[Arbiter.scala 48:59] + node _T_1262 = and(_T_1241, _T_1246) @[Arbiter.scala 48:77] + node _T_1263 = and(_T_1262, _T_1251) @[Arbiter.scala 48:77] + node _T_1264 = and(_T_1263, _T_1256) @[Arbiter.scala 48:77] + node _T_1265 = and(_T_1264, _T_1261) @[Arbiter.scala 48:77] + node _T_1266 = or(_T_1265, reset) @[Arbiter.scala 48:13] + node _T_1268 = eq(_T_1266, UInt<1>("h00")) @[Arbiter.scala 48:13] + when _T_1268 : @[Arbiter.scala 48:13] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:48 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") @[Arbiter.scala 48:13] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 48:13] + skip @[Arbiter.scala 48:13] + node _T_1269 = or(_T_772.valid, TLBroadcastTracker.io.out_a.valid) @[Arbiter.scala 50:31] + node _T_1270 = or(_T_1269, TLBroadcastTracker_1.io.out_a.valid) @[Arbiter.scala 50:31] + node _T_1271 = or(_T_1270, TLBroadcastTracker_2.io.out_a.valid) @[Arbiter.scala 50:31] + node _T_1272 = or(_T_1271, TLBroadcastTracker_3.io.out_a.valid) @[Arbiter.scala 50:31] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[Arbiter.scala 50:15] + node _T_1275 = or(_T_1223[0], _T_1223[1]) @[Arbiter.scala 50:54] + node _T_1276 = or(_T_1275, _T_1223[2]) @[Arbiter.scala 50:54] + node _T_1277 = or(_T_1276, _T_1223[3]) @[Arbiter.scala 50:54] + node _T_1278 = or(_T_1277, _T_1223[4]) @[Arbiter.scala 50:54] + node _T_1279 = or(_T_1274, _T_1278) @[Arbiter.scala 50:36] + node _T_1280 = or(_T_1279, reset) @[Arbiter.scala 50:14] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Arbiter.scala 50:14] + when _T_1282 : @[Arbiter.scala 50:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Arbiter.scala:50 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") @[Arbiter.scala 50:14] + stop(clock, UInt<1>(1), 1) @[Arbiter.scala 50:14] + skip @[Arbiter.scala 50:14] + node _T_1284 = mux(_T_1223[0], _T_1140, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1286 = mux(_T_1223[1], _T_1151, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1288 = mux(_T_1223[2], _T_1162, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1290 = mux(_T_1223[3], _T_1173, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1292 = mux(_T_1223[4], _T_1184, UInt<1>("h00")) @[Arbiter.scala 53:69] + node _T_1293 = or(_T_1284, _T_1286) @[Arbiter.scala 54:44] + node _T_1294 = or(_T_1293, _T_1288) @[Arbiter.scala 54:44] + node _T_1295 = or(_T_1294, _T_1290) @[Arbiter.scala 54:44] + node _T_1296 = or(_T_1295, _T_1292) @[Arbiter.scala 54:44] + node _T_1297 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + node _T_1298 = sub(_T_1186, _T_1297) @[Arbiter.scala 55:52] + node _T_1299 = asUInt(_T_1298) @[Arbiter.scala 55:52] + node _T_1300 = tail(_T_1299, 1) @[Arbiter.scala 55:52] + node _T_1301 = mux(_T_1189, _T_1296, _T_1300) @[Arbiter.scala 55:23] + _T_1186 <= _T_1301 @[Arbiter.scala 55:17] + wire _T_1309 : UInt<1>[5] @[Arbiter.scala 58:49] + _T_1309 is invalid @[Arbiter.scala 58:49] + _T_1309[0] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1309[1] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1309[2] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1309[3] <= UInt<1>("h00") @[Arbiter.scala 58:49] + _T_1309[4] <= UInt<1>("h00") @[Arbiter.scala 58:49] + reg _T_1317 : UInt<1>[5], clock with : (reset => (reset, _T_1309)) @[Reg.scala 26:44] + node _T_1331 = mux(_T_1188, _T_1223, _T_1317) @[Arbiter.scala 59:25] + _T_1317 <- _T_1331 @[Arbiter.scala 60:13] + node _T_1345 = mux(_T_1188, _T_1208, _T_1317) @[Arbiter.scala 63:26] + node _T_1359 = and(io.out.0.a.ready, _T_1345[0]) @[Arbiter.scala 65:33] + _T_772.ready <= _T_1359 @[Arbiter.scala 65:19] + node _T_1360 = and(io.out.0.a.ready, _T_1345[1]) @[Arbiter.scala 65:33] + TLBroadcastTracker.io.out_a.ready <= _T_1360 @[Arbiter.scala 65:19] + node _T_1361 = and(io.out.0.a.ready, _T_1345[2]) @[Arbiter.scala 65:33] + TLBroadcastTracker_1.io.out_a.ready <= _T_1361 @[Arbiter.scala 65:19] + node _T_1362 = and(io.out.0.a.ready, _T_1345[3]) @[Arbiter.scala 65:33] + TLBroadcastTracker_2.io.out_a.ready <= _T_1362 @[Arbiter.scala 65:19] + node _T_1363 = and(io.out.0.a.ready, _T_1345[4]) @[Arbiter.scala 65:33] + TLBroadcastTracker_3.io.out_a.ready <= _T_1363 @[Arbiter.scala 65:19] + node _T_1364 = or(_T_772.valid, TLBroadcastTracker.io.out_a.valid) @[Arbiter.scala 71:46] + node _T_1365 = or(_T_1364, TLBroadcastTracker_1.io.out_a.valid) @[Arbiter.scala 71:46] + node _T_1366 = or(_T_1365, TLBroadcastTracker_2.io.out_a.valid) @[Arbiter.scala 71:46] + node _T_1367 = or(_T_1366, TLBroadcastTracker_3.io.out_a.valid) @[Arbiter.scala 71:46] + node _T_1369 = mux(_T_1317[0], _T_772.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1371 = mux(_T_1317[1], TLBroadcastTracker.io.out_a.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1373 = mux(_T_1317[2], TLBroadcastTracker_1.io.out_a.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1375 = mux(_T_1317[3], TLBroadcastTracker_2.io.out_a.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1377 = mux(_T_1317[4], TLBroadcastTracker_3.io.out_a.valid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1379 = or(_T_1369, _T_1371) @[Mux.scala 19:72] + node _T_1380 = or(_T_1379, _T_1373) @[Mux.scala 19:72] + node _T_1381 = or(_T_1380, _T_1375) @[Mux.scala 19:72] + node _T_1382 = or(_T_1381, _T_1377) @[Mux.scala 19:72] + wire _T_1384 : UInt<1> @[Mux.scala 19:72] + _T_1384 is invalid @[Mux.scala 19:72] + _T_1384 <= _T_1382 @[Mux.scala 19:72] + node _T_1385 = mux(_T_1188, _T_1367, _T_1384) @[Arbiter.scala 71:24] + io.out.0.a.valid <= _T_1385 @[Arbiter.scala 71:18] + node _T_1386 = cat(_T_772.bits.address, _T_772.bits.mask) @[Mux.scala 19:72] + node _T_1387 = cat(_T_1386, _T_772.bits.data) @[Mux.scala 19:72] + node _T_1388 = cat(_T_772.bits.size, _T_772.bits.source) @[Mux.scala 19:72] + node _T_1389 = cat(_T_772.bits.opcode, _T_772.bits.param) @[Mux.scala 19:72] + node _T_1390 = cat(_T_1389, _T_1388) @[Mux.scala 19:72] + node _T_1391 = cat(_T_1390, _T_1387) @[Mux.scala 19:72] + node _T_1393 = mux(_T_1331[0], _T_1391, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1394 = cat(TLBroadcastTracker.io.out_a.bits.address, TLBroadcastTracker.io.out_a.bits.mask) @[Mux.scala 19:72] + node _T_1395 = cat(_T_1394, TLBroadcastTracker.io.out_a.bits.data) @[Mux.scala 19:72] + node _T_1396 = cat(TLBroadcastTracker.io.out_a.bits.size, TLBroadcastTracker.io.out_a.bits.source) @[Mux.scala 19:72] + node _T_1397 = cat(TLBroadcastTracker.io.out_a.bits.opcode, TLBroadcastTracker.io.out_a.bits.param) @[Mux.scala 19:72] + node _T_1398 = cat(_T_1397, _T_1396) @[Mux.scala 19:72] + node _T_1399 = cat(_T_1398, _T_1395) @[Mux.scala 19:72] + node _T_1401 = mux(_T_1331[1], _T_1399, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1402 = cat(TLBroadcastTracker_1.io.out_a.bits.address, TLBroadcastTracker_1.io.out_a.bits.mask) @[Mux.scala 19:72] + node _T_1403 = cat(_T_1402, TLBroadcastTracker_1.io.out_a.bits.data) @[Mux.scala 19:72] + node _T_1404 = cat(TLBroadcastTracker_1.io.out_a.bits.size, TLBroadcastTracker_1.io.out_a.bits.source) @[Mux.scala 19:72] + node _T_1405 = cat(TLBroadcastTracker_1.io.out_a.bits.opcode, TLBroadcastTracker_1.io.out_a.bits.param) @[Mux.scala 19:72] + node _T_1406 = cat(_T_1405, _T_1404) @[Mux.scala 19:72] + node _T_1407 = cat(_T_1406, _T_1403) @[Mux.scala 19:72] + node _T_1409 = mux(_T_1331[2], _T_1407, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1410 = cat(TLBroadcastTracker_2.io.out_a.bits.address, TLBroadcastTracker_2.io.out_a.bits.mask) @[Mux.scala 19:72] + node _T_1411 = cat(_T_1410, TLBroadcastTracker_2.io.out_a.bits.data) @[Mux.scala 19:72] + node _T_1412 = cat(TLBroadcastTracker_2.io.out_a.bits.size, TLBroadcastTracker_2.io.out_a.bits.source) @[Mux.scala 19:72] + node _T_1413 = cat(TLBroadcastTracker_2.io.out_a.bits.opcode, TLBroadcastTracker_2.io.out_a.bits.param) @[Mux.scala 19:72] + node _T_1414 = cat(_T_1413, _T_1412) @[Mux.scala 19:72] + node _T_1415 = cat(_T_1414, _T_1411) @[Mux.scala 19:72] + node _T_1417 = mux(_T_1331[3], _T_1415, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1418 = cat(TLBroadcastTracker_3.io.out_a.bits.address, TLBroadcastTracker_3.io.out_a.bits.mask) @[Mux.scala 19:72] + node _T_1419 = cat(_T_1418, TLBroadcastTracker_3.io.out_a.bits.data) @[Mux.scala 19:72] + node _T_1420 = cat(TLBroadcastTracker_3.io.out_a.bits.size, TLBroadcastTracker_3.io.out_a.bits.source) @[Mux.scala 19:72] + node _T_1421 = cat(TLBroadcastTracker_3.io.out_a.bits.opcode, TLBroadcastTracker_3.io.out_a.bits.param) @[Mux.scala 19:72] + node _T_1422 = cat(_T_1421, _T_1420) @[Mux.scala 19:72] + node _T_1423 = cat(_T_1422, _T_1419) @[Mux.scala 19:72] + node _T_1425 = mux(_T_1331[4], _T_1423, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1434 = or(_T_1393, _T_1401) @[Mux.scala 19:72] + node _T_1435 = or(_T_1434, _T_1409) @[Mux.scala 19:72] + node _T_1436 = or(_T_1435, _T_1417) @[Mux.scala 19:72] + node _T_1437 = or(_T_1436, _T_1425) @[Mux.scala 19:72] + wire _T_1446 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Mux.scala 19:72] + _T_1446 is invalid @[Mux.scala 19:72] + wire _T_1455 : UInt<119> + _T_1455 is invalid + _T_1455 <= _T_1437 + node _T_1456 = bits(_T_1455, 63, 0) @[Mux.scala 19:72] + _T_1446.data <= _T_1456 @[Mux.scala 19:72] + node _T_1457 = bits(_T_1455, 71, 64) @[Mux.scala 19:72] + _T_1446.mask <= _T_1457 @[Mux.scala 19:72] + node _T_1458 = bits(_T_1455, 103, 72) @[Mux.scala 19:72] + _T_1446.address <= _T_1458 @[Mux.scala 19:72] + node _T_1459 = bits(_T_1455, 108, 104) @[Mux.scala 19:72] + _T_1446.source <= _T_1459 @[Mux.scala 19:72] + node _T_1460 = bits(_T_1455, 112, 109) @[Mux.scala 19:72] + _T_1446.size <= _T_1460 @[Mux.scala 19:72] + node _T_1461 = bits(_T_1455, 115, 113) @[Mux.scala 19:72] + _T_1446.param <= _T_1461 @[Mux.scala 19:72] + node _T_1462 = bits(_T_1455, 118, 116) @[Mux.scala 19:72] + _T_1446.opcode <= _T_1462 @[Mux.scala 19:72] + io.out.0.a.bits <- _T_1446 @[Arbiter.scala 72:17] + reg _T_1464 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_1466 : UInt, clock @[Broadcast.scala 148:27] + reg _T_1468 : UInt<2>, clock @[Broadcast.scala 149:28] + node _T_1469 = shl(_T_1464, 1) @[Broadcast.scala 150:58] + node _T_1470 = not(_T_1469) @[Broadcast.scala 150:37] + node _T_1471 = and(_T_1464, _T_1470) @[Broadcast.scala 150:35] + node _T_1473 = neq(_T_1464, UInt<1>("h00")) @[Broadcast.scala 151:38] + node _T_1474 = bits(_T_1471, 0, 0) @[Mux.scala 21:36] + io.in.0.b.valid <= _T_1473 @[Broadcast.scala 155:18] + node _T_1475 = shl(_T_1466, 6) @[Broadcast.scala 157:46] + node _T_1478 = xor(UInt<1>("h00"), UInt<3>("h05")) @[Parameters.scala 37:23] + node _T_1479 = not(_T_1478) @[Parameters.scala 37:9] + node _T_1481 = or(_T_1479, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1482 = not(_T_1481) @[Parameters.scala 37:7] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1486 = eq(UInt<3>("h05"), UInt<3>("h05")) @[Parameters.scala 35:39] + node _T_1488 = eq(UInt<3>("h04"), UInt<3>("h05")) @[Parameters.scala 35:39] + wire _T_1491 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1491 is invalid @[Parameters.scala 228:27] + _T_1491[0] <= _T_1484 @[Parameters.scala 228:27] + _T_1491[1] <= _T_1486 @[Parameters.scala 228:27] + _T_1491[2] <= _T_1488 @[Parameters.scala 228:27] + node _T_1499 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_1501 = leq(UInt<3>("h06"), UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1502 = and(_T_1499, _T_1501) @[Parameters.scala 63:37] + node _T_1505 = mux(_T_1491[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1507 = mux(_T_1491[1], _T_1502, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1509 = mux(_T_1491[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1511 = or(_T_1505, _T_1507) @[Mux.scala 19:72] + node _T_1512 = or(_T_1511, _T_1509) @[Mux.scala 19:72] + wire _T_1514 : UInt<1> @[Mux.scala 19:72] + _T_1514 is invalid @[Mux.scala 19:72] + _T_1514 <= _T_1512 @[Mux.scala 19:72] + wire _T_1523 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 476:17] + _T_1523 is invalid @[Edges.scala 476:17] + _T_1523.opcode <= UInt<3>("h06") @[Edges.scala 477:15] + _T_1523.param <= _T_1468 @[Edges.scala 478:15] + _T_1523.size <= UInt<3>("h06") @[Edges.scala 479:15] + _T_1523.source <= UInt<3>("h05") @[Edges.scala 480:15] + _T_1523.address <= _T_1475 @[Edges.scala 481:15] + node _T_1534 = dshl(UInt<1>("h01"), UInt<2>("h02")) @[OneHot.scala 49:12] + node _T_1535 = bits(_T_1534, 2, 0) @[OneHot.scala 49:37] + node _T_1537 = geq(UInt<3>("h06"), UInt<2>("h03")) @[package.scala 41:21] + node _T_1539 = bits(_T_1535, 2, 2) @[package.scala 44:26] + node _T_1540 = bits(_T_1475, 2, 2) @[package.scala 45:26] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[package.scala 46:20] + node _T_1543 = and(UInt<1>("h01"), _T_1542) @[package.scala 49:27] + node _T_1544 = and(_T_1539, _T_1543) @[package.scala 50:38] + node _T_1545 = or(_T_1537, _T_1544) @[package.scala 50:29] + node _T_1546 = and(UInt<1>("h01"), _T_1540) @[package.scala 49:27] + node _T_1547 = and(_T_1539, _T_1546) @[package.scala 50:38] + node _T_1548 = or(_T_1537, _T_1547) @[package.scala 50:29] + node _T_1549 = bits(_T_1535, 1, 1) @[package.scala 44:26] + node _T_1550 = bits(_T_1475, 1, 1) @[package.scala 45:26] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[package.scala 46:20] + node _T_1553 = and(_T_1543, _T_1552) @[package.scala 49:27] + node _T_1554 = and(_T_1549, _T_1553) @[package.scala 50:38] + node _T_1555 = or(_T_1545, _T_1554) @[package.scala 50:29] + node _T_1556 = and(_T_1543, _T_1550) @[package.scala 49:27] + node _T_1557 = and(_T_1549, _T_1556) @[package.scala 50:38] + node _T_1558 = or(_T_1545, _T_1557) @[package.scala 50:29] + node _T_1559 = and(_T_1546, _T_1552) @[package.scala 49:27] + node _T_1560 = and(_T_1549, _T_1559) @[package.scala 50:38] + node _T_1561 = or(_T_1548, _T_1560) @[package.scala 50:29] + node _T_1562 = and(_T_1546, _T_1550) @[package.scala 49:27] + node _T_1563 = and(_T_1549, _T_1562) @[package.scala 50:38] + node _T_1564 = or(_T_1548, _T_1563) @[package.scala 50:29] + node _T_1565 = bits(_T_1535, 0, 0) @[package.scala 44:26] + node _T_1566 = bits(_T_1475, 0, 0) @[package.scala 45:26] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[package.scala 46:20] + node _T_1569 = and(_T_1553, _T_1568) @[package.scala 49:27] + node _T_1570 = and(_T_1565, _T_1569) @[package.scala 50:38] + node _T_1571 = or(_T_1555, _T_1570) @[package.scala 50:29] + node _T_1572 = and(_T_1553, _T_1566) @[package.scala 49:27] + node _T_1573 = and(_T_1565, _T_1572) @[package.scala 50:38] + node _T_1574 = or(_T_1555, _T_1573) @[package.scala 50:29] + node _T_1575 = and(_T_1556, _T_1568) @[package.scala 49:27] + node _T_1576 = and(_T_1565, _T_1575) @[package.scala 50:38] + node _T_1577 = or(_T_1558, _T_1576) @[package.scala 50:29] + node _T_1578 = and(_T_1556, _T_1566) @[package.scala 49:27] + node _T_1579 = and(_T_1565, _T_1578) @[package.scala 50:38] + node _T_1580 = or(_T_1558, _T_1579) @[package.scala 50:29] + node _T_1581 = and(_T_1559, _T_1568) @[package.scala 49:27] + node _T_1582 = and(_T_1565, _T_1581) @[package.scala 50:38] + node _T_1583 = or(_T_1561, _T_1582) @[package.scala 50:29] + node _T_1584 = and(_T_1559, _T_1566) @[package.scala 49:27] + node _T_1585 = and(_T_1565, _T_1584) @[package.scala 50:38] + node _T_1586 = or(_T_1561, _T_1585) @[package.scala 50:29] + node _T_1587 = and(_T_1562, _T_1568) @[package.scala 49:27] + node _T_1588 = and(_T_1565, _T_1587) @[package.scala 50:38] + node _T_1589 = or(_T_1564, _T_1588) @[package.scala 50:29] + node _T_1590 = and(_T_1562, _T_1566) @[package.scala 49:27] + node _T_1591 = and(_T_1565, _T_1590) @[package.scala 50:38] + node _T_1592 = or(_T_1564, _T_1591) @[package.scala 50:29] + node _T_1593 = cat(_T_1574, _T_1571) @[Cat.scala 30:58] + node _T_1594 = cat(_T_1580, _T_1577) @[Cat.scala 30:58] + node _T_1595 = cat(_T_1594, _T_1593) @[Cat.scala 30:58] + node _T_1596 = cat(_T_1586, _T_1583) @[Cat.scala 30:58] + node _T_1597 = cat(_T_1592, _T_1589) @[Cat.scala 30:58] + node _T_1598 = cat(_T_1597, _T_1596) @[Cat.scala 30:58] + node _T_1599 = cat(_T_1598, _T_1595) @[Cat.scala 30:58] + _T_1523.mask <= _T_1599 @[Edges.scala 482:15] + _T_1523.data <= UInt<1>("h00") @[Edges.scala 483:15] + io.in.0.b.bits <- _T_1523 @[Broadcast.scala 157:19] + node _T_1601 = and(io.in.0.b.ready, io.in.0.b.valid) @[Decoupled.scala 30:37] + when _T_1601 : @[Broadcast.scala 159:26] + node _T_1602 = not(_T_1471) @[Broadcast.scala 159:55] + node _T_1603 = and(_T_1464, _T_1602) @[Broadcast.scala 159:53] + _T_1464 <= _T_1603 @[Broadcast.scala 159:39] + skip @[Broadcast.scala 159:26] + node _T_1605 = eq(UInt<3>("h05"), io.in.0.a.bits.source) @[Parameters.scala 35:39] + wire _T_1608 : UInt<1>[1] @[Broadcast.scala 162:59] + _T_1608 is invalid @[Broadcast.scala 162:59] + _T_1608[0] <= _T_1605 @[Broadcast.scala 162:59] + node _T_1612 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_1614 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1615 = dshl(_T_1614, io.in.0.a.bits.size) @[package.scala 19:71] + node _T_1616 = bits(_T_1615, 5, 0) @[package.scala 19:76] + node _T_1617 = not(_T_1616) @[package.scala 19:40] + node _T_1618 = shr(_T_1617, 3) @[Edges.scala 198:59] + node _T_1619 = bits(io.in.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1623 = mux(_T_1621, _T_1618, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1625 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1627 = sub(_T_1625, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1628 = asUInt(_T_1627) @[Edges.scala 208:28] + node _T_1629 = tail(_T_1628, 1) @[Edges.scala 208:28] + node _T_1631 = eq(_T_1625, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1633 = eq(_T_1625, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1635 = eq(_T_1623, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1636 = or(_T_1633, _T_1635) @[Edges.scala 210:37] + node _T_1637 = and(_T_1636, _T_1612) @[Edges.scala 211:22] + node _T_1638 = not(_T_1629) @[Edges.scala 212:27] + node _T_1639 = and(_T_1623, _T_1638) @[Edges.scala 212:25] + when _T_1612 : @[Edges.scala 213:17] + node _T_1640 = mux(_T_1631, _T_1623, _T_1629) @[Edges.scala 214:21] + _T_1625 <= _T_1640 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1643 : UInt<1>[4] @[Broadcast.scala 166:29] + _T_1643 is invalid @[Broadcast.scala 166:29] + _T_1643[0] <= TLBroadcastTracker.io.idle @[Broadcast.scala 166:29] + _T_1643[1] <= TLBroadcastTracker_1.io.idle @[Broadcast.scala 166:29] + _T_1643[2] <= TLBroadcastTracker_2.io.idle @[Broadcast.scala 166:29] + _T_1643[3] <= TLBroadcastTracker_3.io.idle @[Broadcast.scala 166:29] + node _T_1650 = cat(_T_1643[1], _T_1643[0]) @[Broadcast.scala 166:60] + node _T_1651 = cat(_T_1643[3], _T_1643[2]) @[Broadcast.scala 166:60] + node _T_1652 = cat(_T_1651, _T_1650) @[Broadcast.scala 166:60] + node _T_1654 = neq(_T_1652, UInt<1>("h00")) @[Broadcast.scala 167:41] + node _T_1655 = shr(io.in.0.a.bits.address, 6) @[Broadcast.scala 168:80] + node _T_1656 = eq(TLBroadcastTracker.io.line, _T_1655) @[Broadcast.scala 168:58] + node _T_1657 = shr(io.in.0.a.bits.address, 6) @[Broadcast.scala 168:80] + node _T_1658 = eq(TLBroadcastTracker_1.io.line, _T_1657) @[Broadcast.scala 168:58] + node _T_1659 = shr(io.in.0.a.bits.address, 6) @[Broadcast.scala 168:80] + node _T_1660 = eq(TLBroadcastTracker_2.io.line, _T_1659) @[Broadcast.scala 168:58] + node _T_1661 = shr(io.in.0.a.bits.address, 6) @[Broadcast.scala 168:80] + node _T_1662 = eq(TLBroadcastTracker_3.io.line, _T_1661) @[Broadcast.scala 168:58] + wire _T_1665 : UInt<1>[4] @[Broadcast.scala 168:30] + _T_1665 is invalid @[Broadcast.scala 168:30] + _T_1665[0] <= _T_1656 @[Broadcast.scala 168:30] + _T_1665[1] <= _T_1658 @[Broadcast.scala 168:30] + _T_1665[2] <= _T_1660 @[Broadcast.scala 168:30] + _T_1665[3] <= _T_1662 @[Broadcast.scala 168:30] + node _T_1672 = cat(_T_1665[1], _T_1665[0]) @[Broadcast.scala 168:96] + node _T_1673 = cat(_T_1665[3], _T_1665[2]) @[Broadcast.scala 168:96] + node _T_1674 = cat(_T_1673, _T_1672) @[Broadcast.scala 168:96] + node _T_1676 = neq(_T_1674, UInt<1>("h00")) @[Broadcast.scala 169:43] + node _T_1677 = shl(_T_1652, 1) @[package.scala 25:45] + node _T_1678 = bits(_T_1677, 3, 0) @[package.scala 25:50] + node _T_1679 = or(_T_1652, _T_1678) @[package.scala 25:40] + node _T_1680 = shl(_T_1679, 2) @[package.scala 25:45] + node _T_1681 = bits(_T_1680, 3, 0) @[package.scala 25:50] + node _T_1682 = or(_T_1679, _T_1681) @[package.scala 25:40] + node _T_1683 = shl(_T_1682, 1) @[Broadcast.scala 170:64] + node _T_1684 = not(_T_1683) @[Broadcast.scala 170:41] + node _T_1685 = and(_T_1652, _T_1684) @[Broadcast.scala 170:39] + node _T_1686 = mux(_T_1676, _T_1674, _T_1685) @[Broadcast.scala 171:30] + wire _T_1689 : UInt<1>[4] @[Broadcast.scala 173:29] + _T_1689 is invalid @[Broadcast.scala 173:29] + _T_1689[0] <= TLBroadcastTracker.io.in_a.ready @[Broadcast.scala 173:29] + _T_1689[1] <= TLBroadcastTracker_1.io.in_a.ready @[Broadcast.scala 173:29] + _T_1689[2] <= TLBroadcastTracker_2.io.in_a.ready @[Broadcast.scala 173:29] + _T_1689[3] <= TLBroadcastTracker_3.io.in_a.ready @[Broadcast.scala 173:29] + node _T_1696 = cat(_T_1689[1], _T_1689[0]) @[Broadcast.scala 173:58] + node _T_1697 = cat(_T_1689[3], _T_1689[2]) @[Broadcast.scala 173:58] + node _T_1698 = cat(_T_1697, _T_1696) @[Broadcast.scala 173:58] + node _T_1700 = eq(_T_1631, UInt<1>("h00")) @[Broadcast.scala 174:22] + node _T_1702 = eq(_T_1473, UInt<1>("h00")) @[Broadcast.scala 174:34] + node _T_1703 = or(_T_1700, _T_1702) @[Broadcast.scala 174:31] + node _T_1704 = and(_T_1686, _T_1698) @[Broadcast.scala 174:65] + node _T_1706 = neq(_T_1704, UInt<1>("h00")) @[Broadcast.scala 174:84] + node _T_1707 = and(_T_1703, _T_1706) @[Broadcast.scala 174:47] + io.in.0.a.ready <= _T_1707 @[Broadcast.scala 174:18] + node _T_1708 = bits(_T_1686, 0, 0) @[Broadcast.scala 175:35] + node _T_1709 = bits(_T_1686, 1, 1) @[Broadcast.scala 175:35] + node _T_1710 = bits(_T_1686, 2, 2) @[Broadcast.scala 175:35] + node _T_1711 = bits(_T_1686, 3, 3) @[Broadcast.scala 175:35] + node _T_1712 = bits(_T_1686, 4, 4) @[Broadcast.scala 175:35] + node _T_1713 = and(io.in.0.a.valid, _T_1708) @[Broadcast.scala 176:36] + node _T_1715 = eq(_T_1631, UInt<1>("h00")) @[Broadcast.scala 176:50] + node _T_1717 = eq(_T_1473, UInt<1>("h00")) @[Broadcast.scala 176:62] + node _T_1718 = or(_T_1715, _T_1717) @[Broadcast.scala 176:59] + node _T_1719 = and(_T_1713, _T_1718) @[Broadcast.scala 176:46] + TLBroadcastTracker.io.in_a.valid <= _T_1719 @[Broadcast.scala 176:22] + TLBroadcastTracker.io.in_a.bits <- io.in.0.a.bits @[Broadcast.scala 177:21] + TLBroadcastTracker.io.in_a_first <= _T_1631 @[Broadcast.scala 178:22] + node _T_1721 = neq(_T_1608[0], UInt<1>("h00")) @[Broadcast.scala 179:71] + node _T_1724 = mux(_T_1721, UInt<1>("h00"), UInt<1>("h01")) @[Broadcast.scala 179:59] + TLBroadcastTracker.io.probe <= _T_1724 @[Broadcast.scala 179:17] + node _T_1725 = and(io.in.0.a.valid, _T_1709) @[Broadcast.scala 176:36] + node _T_1727 = eq(_T_1631, UInt<1>("h00")) @[Broadcast.scala 176:50] + node _T_1729 = eq(_T_1473, UInt<1>("h00")) @[Broadcast.scala 176:62] + node _T_1730 = or(_T_1727, _T_1729) @[Broadcast.scala 176:59] + node _T_1731 = and(_T_1725, _T_1730) @[Broadcast.scala 176:46] + TLBroadcastTracker_1.io.in_a.valid <= _T_1731 @[Broadcast.scala 176:22] + TLBroadcastTracker_1.io.in_a.bits <- io.in.0.a.bits @[Broadcast.scala 177:21] + TLBroadcastTracker_1.io.in_a_first <= _T_1631 @[Broadcast.scala 178:22] + node _T_1733 = neq(_T_1608[0], UInt<1>("h00")) @[Broadcast.scala 179:71] + node _T_1736 = mux(_T_1733, UInt<1>("h00"), UInt<1>("h01")) @[Broadcast.scala 179:59] + TLBroadcastTracker_1.io.probe <= _T_1736 @[Broadcast.scala 179:17] + node _T_1737 = and(io.in.0.a.valid, _T_1710) @[Broadcast.scala 176:36] + node _T_1739 = eq(_T_1631, UInt<1>("h00")) @[Broadcast.scala 176:50] + node _T_1741 = eq(_T_1473, UInt<1>("h00")) @[Broadcast.scala 176:62] + node _T_1742 = or(_T_1739, _T_1741) @[Broadcast.scala 176:59] + node _T_1743 = and(_T_1737, _T_1742) @[Broadcast.scala 176:46] + TLBroadcastTracker_2.io.in_a.valid <= _T_1743 @[Broadcast.scala 176:22] + TLBroadcastTracker_2.io.in_a.bits <- io.in.0.a.bits @[Broadcast.scala 177:21] + TLBroadcastTracker_2.io.in_a_first <= _T_1631 @[Broadcast.scala 178:22] + node _T_1745 = neq(_T_1608[0], UInt<1>("h00")) @[Broadcast.scala 179:71] + node _T_1748 = mux(_T_1745, UInt<1>("h00"), UInt<1>("h01")) @[Broadcast.scala 179:59] + TLBroadcastTracker_2.io.probe <= _T_1748 @[Broadcast.scala 179:17] + node _T_1749 = and(io.in.0.a.valid, _T_1711) @[Broadcast.scala 176:36] + node _T_1751 = eq(_T_1631, UInt<1>("h00")) @[Broadcast.scala 176:50] + node _T_1753 = eq(_T_1473, UInt<1>("h00")) @[Broadcast.scala 176:62] + node _T_1754 = or(_T_1751, _T_1753) @[Broadcast.scala 176:59] + node _T_1755 = and(_T_1749, _T_1754) @[Broadcast.scala 176:46] + TLBroadcastTracker_3.io.in_a.valid <= _T_1755 @[Broadcast.scala 176:22] + TLBroadcastTracker_3.io.in_a.bits <- io.in.0.a.bits @[Broadcast.scala 177:21] + TLBroadcastTracker_3.io.in_a_first <= _T_1631 @[Broadcast.scala 178:22] + node _T_1757 = neq(_T_1608[0], UInt<1>("h00")) @[Broadcast.scala 179:71] + node _T_1760 = mux(_T_1757, UInt<1>("h00"), UInt<1>("h01")) @[Broadcast.scala 179:59] + TLBroadcastTracker_3.io.probe <= _T_1760 @[Broadcast.scala 179:17] + node _T_1761 = and(io.in.0.a.ready, io.in.0.a.valid) @[Decoupled.scala 30:37] + node _T_1762 = and(_T_1761, _T_1631) @[Broadcast.scala 182:25] + when _T_1762 : @[Broadcast.scala 182:37] + node _T_1763 = not(_T_1608[0]) @[Broadcast.scala 183:24] + _T_1464 <= _T_1763 @[Broadcast.scala 183:21] + node _T_1764 = shr(io.in.0.a.bits.address, 6) @[Broadcast.scala 184:42] + _T_1466 <= _T_1764 @[Broadcast.scala 184:21] + wire _T_1766 : UInt<2> @[Broadcast.scala 185:56] + _T_1766 is invalid @[Broadcast.scala 185:56] + wire _T_1779 : UInt<2> @[Broadcast.scala 191:71] + _T_1779 is invalid @[Broadcast.scala 191:71] + node _T_1784 = eq(UInt<1>("h01"), io.in.0.a.bits.param) @[Mux.scala 46:19] + node _T_1785 = mux(_T_1784, UInt<2>("h02"), _T_1779) @[Mux.scala 46:16] + node _T_1786 = eq(UInt<1>("h00"), io.in.0.a.bits.param) @[Mux.scala 46:19] + node _T_1787 = mux(_T_1786, UInt<2>("h01"), _T_1785) @[Mux.scala 46:16] + wire _T_1790 : UInt<2> @[Broadcast.scala 194:71] + _T_1790 is invalid @[Broadcast.scala 194:71] + node _T_1797 = eq(UInt<2>("h02"), io.in.0.a.bits.param) @[Mux.scala 46:19] + node _T_1798 = mux(_T_1797, UInt<2>("h02"), _T_1790) @[Mux.scala 46:16] + node _T_1799 = eq(UInt<2>("h01"), io.in.0.a.bits.param) @[Mux.scala 46:19] + node _T_1800 = mux(_T_1799, UInt<2>("h02"), _T_1798) @[Mux.scala 46:16] + node _T_1801 = eq(UInt<2>("h00"), io.in.0.a.bits.param) @[Mux.scala 46:19] + node _T_1802 = mux(_T_1801, UInt<2>("h01"), _T_1800) @[Mux.scala 46:16] + node _T_1803 = eq(UInt<3>("h06"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1804 = mux(_T_1803, _T_1802, _T_1766) @[Mux.scala 46:16] + node _T_1805 = eq(UInt<3>("h05"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1806 = mux(_T_1805, _T_1787, _T_1804) @[Mux.scala 46:16] + node _T_1807 = eq(UInt<3>("h04"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1808 = mux(_T_1807, UInt<2>("h01"), _T_1806) @[Mux.scala 46:16] + node _T_1809 = eq(UInt<2>("h03"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1810 = mux(_T_1809, UInt<2>("h02"), _T_1808) @[Mux.scala 46:16] + node _T_1811 = eq(UInt<2>("h02"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1812 = mux(_T_1811, UInt<2>("h02"), _T_1810) @[Mux.scala 46:16] + node _T_1813 = eq(UInt<1>("h01"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1814 = mux(_T_1813, UInt<2>("h02"), _T_1812) @[Mux.scala 46:16] + node _T_1815 = eq(UInt<1>("h00"), io.in.0.a.bits.opcode) @[Mux.scala 46:19] + node _T_1816 = mux(_T_1815, UInt<2>("h02"), _T_1814) @[Mux.scala 46:16] + _T_1468 <= _T_1816 @[Broadcast.scala 185:21] + skip @[Broadcast.scala 182:37] + io.out.0.b.ready <= UInt<1>("h01") @[Broadcast.scala 201:19] + io.out.0.c.valid <= UInt<1>("h00") @[Broadcast.scala 202:19] + io.out.0.e.valid <= UInt<1>("h00") @[Broadcast.scala 203:19] + + module TLWidthWidget_mem_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + io.out.0.a <- io.in.0.a @[WidthWidget.scala 131:13] + io.in.0.d <- io.out.0.d @[WidthWidget.scala 131:13] + io.in.0.b.valid <= UInt<1>("h00") @[WidthWidget.scala 153:20] + io.in.0.c.ready <= UInt<1>("h01") @[WidthWidget.scala 154:20] + io.in.0.e.ready <= UInt<1>("h01") @[WidthWidget.scala 155:20] + io.out.0.b.ready <= UInt<1>("h01") @[WidthWidget.scala 156:21] + io.out.0.c.valid <= UInt<1>("h00") @[WidthWidget.scala 157:21] + io.out.0.e.valid <= UInt<1>("h00") @[WidthWidget.scala 158:21] + + module TLMonitor_21 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[BaseCoreplex.scala 36:13] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[BaseCoreplex.scala 36:13] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_608 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + when _T_700 : @[BaseCoreplex.scala 36:13] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = or(_T_711, _T_719) @[Parameters.scala 133:42] + node _T_721 = and(_T_703, _T_720) @[Parameters.scala 132:56] + node _T_723 = or(UInt<1>("h00"), _T_721) @[Parameters.scala 134:30] + node _T_724 = or(_T_723, reset) @[BaseCoreplex.scala 36:13] + node _T_726 = eq(_T_724, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_726 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_727 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_729 = eq(_T_727, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_729 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_731 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_732 = or(_T_731, reset) @[BaseCoreplex.scala 36:13] + node _T_734 = eq(_T_732, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_734 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_735 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_737 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_739 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_740 = or(_T_739, reset) @[BaseCoreplex.scala 36:13] + node _T_742 = eq(_T_740, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_742 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_743 = not(io.in[0].a.bits.mask) @[BaseCoreplex.scala 36:13] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_746 = or(_T_745, reset) @[BaseCoreplex.scala 36:13] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_748 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_750 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[BaseCoreplex.scala 36:13] + when _T_750 : @[BaseCoreplex.scala 36:13] + node _T_753 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_755 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_756 = and(_T_753, _T_755) @[Parameters.scala 63:37] + node _T_757 = or(UInt<1>("h00"), _T_756) @[Parameters.scala 132:31] + node _T_759 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_760 = cvt(_T_759) @[Parameters.scala 117:49] + node _T_762 = and(_T_760, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_763 = asSInt(_T_762) @[Parameters.scala 117:52] + node _T_765 = eq(_T_763, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_766 = and(_T_757, _T_765) @[Parameters.scala 132:56] + node _T_769 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_771 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_772 = and(_T_769, _T_771) @[Parameters.scala 63:37] + node _T_773 = or(UInt<1>("h00"), _T_772) @[Parameters.scala 132:31] + node _T_775 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_776 = cvt(_T_775) @[Parameters.scala 117:49] + node _T_778 = and(_T_776, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_779 = asSInt(_T_778) @[Parameters.scala 117:52] + node _T_781 = eq(_T_779, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_782 = and(_T_773, _T_781) @[Parameters.scala 132:56] + node _T_784 = or(UInt<1>("h00"), _T_766) @[Parameters.scala 134:30] + node _T_785 = or(_T_784, _T_782) @[Parameters.scala 134:30] + node _T_786 = or(_T_785, reset) @[BaseCoreplex.scala 36:13] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_788 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_789 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_791 = eq(_T_789, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_791 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_792 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_794 = eq(_T_792, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_794 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_796 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_797 = or(_T_796, reset) @[BaseCoreplex.scala 36:13] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_799 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_800 = eq(io.in[0].a.bits.mask, _T_698) @[BaseCoreplex.scala 36:13] + node _T_801 = or(_T_800, reset) @[BaseCoreplex.scala 36:13] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_803 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_805 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_805 : @[BaseCoreplex.scala 36:13] + node _T_808 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_810 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_811 = and(_T_808, _T_810) @[Parameters.scala 63:37] + node _T_812 = or(UInt<1>("h00"), _T_811) @[Parameters.scala 132:31] + node _T_814 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_815 = cvt(_T_814) @[Parameters.scala 117:49] + node _T_817 = and(_T_815, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_818 = asSInt(_T_817) @[Parameters.scala 117:52] + node _T_820 = eq(_T_818, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_821 = and(_T_812, _T_820) @[Parameters.scala 132:56] + node _T_824 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_826 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_827 = and(_T_824, _T_826) @[Parameters.scala 63:37] + node _T_828 = or(UInt<1>("h00"), _T_827) @[Parameters.scala 132:31] + node _T_830 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_831 = cvt(_T_830) @[Parameters.scala 117:49] + node _T_833 = and(_T_831, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_834 = asSInt(_T_833) @[Parameters.scala 117:52] + node _T_836 = eq(_T_834, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_837 = and(_T_828, _T_836) @[Parameters.scala 132:56] + node _T_839 = or(UInt<1>("h00"), _T_821) @[Parameters.scala 134:30] + node _T_840 = or(_T_839, _T_837) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[BaseCoreplex.scala 36:13] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_843 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_844 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_846 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_847 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_849 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_851 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_852 = or(_T_851, reset) @[BaseCoreplex.scala 36:13] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_854 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_855 = eq(io.in[0].a.bits.mask, _T_698) @[BaseCoreplex.scala 36:13] + node _T_856 = or(_T_855, reset) @[BaseCoreplex.scala 36:13] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_858 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[BaseCoreplex.scala 36:13] + when _T_860 : @[BaseCoreplex.scala 36:13] + node _T_863 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_865 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_866 = and(_T_863, _T_865) @[Parameters.scala 63:37] + node _T_867 = or(UInt<1>("h00"), _T_866) @[Parameters.scala 132:31] + node _T_869 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_870 = cvt(_T_869) @[Parameters.scala 117:49] + node _T_872 = and(_T_870, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_873 = asSInt(_T_872) @[Parameters.scala 117:52] + node _T_875 = eq(_T_873, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_876 = and(_T_867, _T_875) @[Parameters.scala 132:56] + node _T_879 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_881 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_882 = and(_T_879, _T_881) @[Parameters.scala 63:37] + node _T_883 = or(UInt<1>("h00"), _T_882) @[Parameters.scala 132:31] + node _T_885 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_892 = and(_T_883, _T_891) @[Parameters.scala 132:56] + node _T_894 = or(UInt<1>("h00"), _T_876) @[Parameters.scala 134:30] + node _T_895 = or(_T_894, _T_892) @[Parameters.scala 134:30] + node _T_896 = or(_T_895, reset) @[BaseCoreplex.scala 36:13] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_898 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_899 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_901 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_902 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_904 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_906 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_907 = or(_T_906, reset) @[BaseCoreplex.scala 36:13] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_909 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_910 = not(_T_698) @[BaseCoreplex.scala 36:13] + node _T_911 = and(io.in[0].a.bits.mask, _T_910) @[BaseCoreplex.scala 36:13] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_914 = or(_T_913, reset) @[BaseCoreplex.scala 36:13] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_916 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_918 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + when _T_918 : @[BaseCoreplex.scala 36:13] + node _T_921 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_923 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_924 = cvt(_T_923) @[Parameters.scala 117:49] + node _T_926 = and(_T_924, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_927 = asSInt(_T_926) @[Parameters.scala 117:52] + node _T_929 = eq(_T_927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = or(_T_929, _T_937) @[Parameters.scala 133:42] + node _T_939 = and(_T_921, _T_938) @[Parameters.scala 132:56] + node _T_941 = or(UInt<1>("h00"), _T_939) @[Parameters.scala 134:30] + node _T_942 = or(_T_941, reset) @[BaseCoreplex.scala 36:13] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_944 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_945 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_947 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_948 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_950 = eq(_T_948, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_950 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_952 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_953 = or(_T_952, reset) @[BaseCoreplex.scala 36:13] + node _T_955 = eq(_T_953, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_955 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_956 = eq(io.in[0].a.bits.mask, _T_698) @[BaseCoreplex.scala 36:13] + node _T_957 = or(_T_956, reset) @[BaseCoreplex.scala 36:13] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_959 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_961 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + when _T_961 : @[BaseCoreplex.scala 36:13] + node _T_964 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_966 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_967 = cvt(_T_966) @[Parameters.scala 117:49] + node _T_969 = and(_T_967, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_970 = asSInt(_T_969) @[Parameters.scala 117:52] + node _T_972 = eq(_T_970, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_975 = cvt(_T_974) @[Parameters.scala 117:49] + node _T_977 = and(_T_975, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_978 = asSInt(_T_977) @[Parameters.scala 117:52] + node _T_980 = eq(_T_978, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = or(_T_972, _T_980) @[Parameters.scala 133:42] + node _T_982 = and(_T_964, _T_981) @[Parameters.scala 132:56] + node _T_984 = or(UInt<1>("h00"), _T_982) @[Parameters.scala 134:30] + node _T_985 = or(_T_984, reset) @[BaseCoreplex.scala 36:13] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_987 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_988 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_990 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_991 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_993 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_995 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_996 = or(_T_995, reset) @[BaseCoreplex.scala 36:13] + node _T_998 = eq(_T_996, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_998 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_999 = eq(io.in[0].a.bits.mask, _T_698) @[BaseCoreplex.scala 36:13] + node _T_1000 = or(_T_999, reset) @[BaseCoreplex.scala 36:13] + node _T_1002 = eq(_T_1000, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1002 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1004 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[BaseCoreplex.scala 36:13] + when _T_1004 : @[BaseCoreplex.scala 36:13] + node _T_1007 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1009 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1010 = cvt(_T_1009) @[Parameters.scala 117:49] + node _T_1012 = and(_T_1010, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1013 = asSInt(_T_1012) @[Parameters.scala 117:52] + node _T_1015 = eq(_T_1013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1018 = cvt(_T_1017) @[Parameters.scala 117:49] + node _T_1020 = and(_T_1018, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1021 = asSInt(_T_1020) @[Parameters.scala 117:52] + node _T_1023 = eq(_T_1021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = or(_T_1015, _T_1023) @[Parameters.scala 133:42] + node _T_1025 = and(_T_1007, _T_1024) @[Parameters.scala 132:56] + node _T_1027 = or(UInt<1>("h00"), _T_1025) @[Parameters.scala 134:30] + node _T_1028 = or(_T_1027, reset) @[BaseCoreplex.scala 36:13] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1030 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1031 = or(_T_619[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1033 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1034 = or(_T_630, reset) @[BaseCoreplex.scala 36:13] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1036 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_698) @[BaseCoreplex.scala 36:13] + node _T_1038 = or(_T_1037, reset) @[BaseCoreplex.scala 36:13] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1040 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + when io.in[0].b.valid : @[BaseCoreplex.scala 36:13] + node _T_1042 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1043 = or(_T_1042, reset) @[BaseCoreplex.scala 36:13] + node _T_1045 = eq(_T_1043, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1045 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1047 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1064 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1064 is invalid @[Parameters.scala 110:36] + _T_1064[0] <= _T_1053 @[Parameters.scala 110:36] + _T_1064[1] <= _T_1061 @[Parameters.scala 110:36] + node _T_1069 = or(_T_1064[0], _T_1064[1]) @[Parameters.scala 119:64] + node _T_1071 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1072 = dshl(_T_1071, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1073 = bits(_T_1072, 7, 0) @[package.scala 19:76] + node _T_1074 = not(_T_1073) @[package.scala 19:40] + node _T_1075 = and(io.in[0].b.bits.address, _T_1074) @[Edges.scala 17:16] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1079 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1080 = dshl(UInt<1>("h01"), _T_1079) @[OneHot.scala 49:12] + node _T_1081 = bits(_T_1080, 2, 0) @[OneHot.scala 49:37] + node _T_1083 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1085 = bits(_T_1081, 2, 2) @[package.scala 44:26] + node _T_1086 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[package.scala 46:20] + node _T_1089 = and(UInt<1>("h01"), _T_1088) @[package.scala 49:27] + node _T_1090 = and(_T_1085, _T_1089) @[package.scala 50:38] + node _T_1091 = or(_T_1083, _T_1090) @[package.scala 50:29] + node _T_1092 = and(UInt<1>("h01"), _T_1086) @[package.scala 49:27] + node _T_1093 = and(_T_1085, _T_1092) @[package.scala 50:38] + node _T_1094 = or(_T_1083, _T_1093) @[package.scala 50:29] + node _T_1095 = bits(_T_1081, 1, 1) @[package.scala 44:26] + node _T_1096 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1098 = eq(_T_1096, UInt<1>("h00")) @[package.scala 46:20] + node _T_1099 = and(_T_1089, _T_1098) @[package.scala 49:27] + node _T_1100 = and(_T_1095, _T_1099) @[package.scala 50:38] + node _T_1101 = or(_T_1091, _T_1100) @[package.scala 50:29] + node _T_1102 = and(_T_1089, _T_1096) @[package.scala 49:27] + node _T_1103 = and(_T_1095, _T_1102) @[package.scala 50:38] + node _T_1104 = or(_T_1091, _T_1103) @[package.scala 50:29] + node _T_1105 = and(_T_1092, _T_1098) @[package.scala 49:27] + node _T_1106 = and(_T_1095, _T_1105) @[package.scala 50:38] + node _T_1107 = or(_T_1094, _T_1106) @[package.scala 50:29] + node _T_1108 = and(_T_1092, _T_1096) @[package.scala 49:27] + node _T_1109 = and(_T_1095, _T_1108) @[package.scala 50:38] + node _T_1110 = or(_T_1094, _T_1109) @[package.scala 50:29] + node _T_1111 = bits(_T_1081, 0, 0) @[package.scala 44:26] + node _T_1112 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[package.scala 46:20] + node _T_1115 = and(_T_1099, _T_1114) @[package.scala 49:27] + node _T_1116 = and(_T_1111, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1101, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1099, _T_1112) @[package.scala 49:27] + node _T_1119 = and(_T_1111, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1101, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1102, _T_1114) @[package.scala 49:27] + node _T_1122 = and(_T_1111, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1104, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1102, _T_1112) @[package.scala 49:27] + node _T_1125 = and(_T_1111, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1104, _T_1125) @[package.scala 50:29] + node _T_1127 = and(_T_1105, _T_1114) @[package.scala 49:27] + node _T_1128 = and(_T_1111, _T_1127) @[package.scala 50:38] + node _T_1129 = or(_T_1107, _T_1128) @[package.scala 50:29] + node _T_1130 = and(_T_1105, _T_1112) @[package.scala 49:27] + node _T_1131 = and(_T_1111, _T_1130) @[package.scala 50:38] + node _T_1132 = or(_T_1107, _T_1131) @[package.scala 50:29] + node _T_1133 = and(_T_1108, _T_1114) @[package.scala 49:27] + node _T_1134 = and(_T_1111, _T_1133) @[package.scala 50:38] + node _T_1135 = or(_T_1110, _T_1134) @[package.scala 50:29] + node _T_1136 = and(_T_1108, _T_1112) @[package.scala 49:27] + node _T_1137 = and(_T_1111, _T_1136) @[package.scala 50:38] + node _T_1138 = or(_T_1110, _T_1137) @[package.scala 50:29] + node _T_1139 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + when _T_1147 : @[BaseCoreplex.scala 36:13] + node _T_1149 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1151 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1152 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1154 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1156 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1157 = or(_T_1156, reset) @[BaseCoreplex.scala 36:13] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1159 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1160 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1162 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1164 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1165 = or(_T_1164, reset) @[BaseCoreplex.scala 36:13] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1167 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1168 = not(io.in[0].b.bits.mask) @[BaseCoreplex.scala 36:13] + node _T_1170 = eq(_T_1168, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1171 = or(_T_1170, reset) @[BaseCoreplex.scala 36:13] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1173 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1175 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[BaseCoreplex.scala 36:13] + when _T_1175 : @[BaseCoreplex.scala 36:13] + node _T_1177 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1179 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1180 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1182 = eq(_T_1180, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1182 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1183 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1185 = eq(_T_1183, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1185 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1187 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1188 = or(_T_1187, reset) @[BaseCoreplex.scala 36:13] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1190 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1191 = eq(io.in[0].b.bits.mask, _T_1145) @[BaseCoreplex.scala 36:13] + node _T_1192 = or(_T_1191, reset) @[BaseCoreplex.scala 36:13] + node _T_1194 = eq(_T_1192, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1194 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1196 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1196 : @[BaseCoreplex.scala 36:13] + node _T_1198 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1200 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1201 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1203 = eq(_T_1201, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1203 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1204 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1206 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1208 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1209 = or(_T_1208, reset) @[BaseCoreplex.scala 36:13] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1211 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1212 = eq(io.in[0].b.bits.mask, _T_1145) @[BaseCoreplex.scala 36:13] + node _T_1213 = or(_T_1212, reset) @[BaseCoreplex.scala 36:13] + node _T_1215 = eq(_T_1213, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1215 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1217 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[BaseCoreplex.scala 36:13] + when _T_1217 : @[BaseCoreplex.scala 36:13] + node _T_1219 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1221 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1222 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1224 = eq(_T_1222, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1224 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1225 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1227 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1229 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1230 = or(_T_1229, reset) @[BaseCoreplex.scala 36:13] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1232 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1233 = not(_T_1145) @[BaseCoreplex.scala 36:13] + node _T_1234 = and(io.in[0].b.bits.mask, _T_1233) @[BaseCoreplex.scala 36:13] + node _T_1236 = eq(_T_1234, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1237 = or(_T_1236, reset) @[BaseCoreplex.scala 36:13] + node _T_1239 = eq(_T_1237, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1239 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1241 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + when _T_1241 : @[BaseCoreplex.scala 36:13] + node _T_1243 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1245 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1246 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1248 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1249 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1251 = eq(_T_1249, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1251 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1253 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1254 = or(_T_1253, reset) @[BaseCoreplex.scala 36:13] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1256 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1257 = eq(io.in[0].b.bits.mask, _T_1145) @[BaseCoreplex.scala 36:13] + node _T_1258 = or(_T_1257, reset) @[BaseCoreplex.scala 36:13] + node _T_1260 = eq(_T_1258, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1260 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1262 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + when _T_1262 : @[BaseCoreplex.scala 36:13] + node _T_1264 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1266 = eq(_T_1264, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1266 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1267 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1269 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1270 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1272 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1274 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1275 = or(_T_1274, reset) @[BaseCoreplex.scala 36:13] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1277 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1278 = eq(io.in[0].b.bits.mask, _T_1145) @[BaseCoreplex.scala 36:13] + node _T_1279 = or(_T_1278, reset) @[BaseCoreplex.scala 36:13] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1281 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1283 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[BaseCoreplex.scala 36:13] + when _T_1283 : @[BaseCoreplex.scala 36:13] + node _T_1285 = or(UInt<1>("h00"), reset) @[BaseCoreplex.scala 36:13] + node _T_1287 = eq(_T_1285, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1287 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1288 = or(_T_1069, reset) @[BaseCoreplex.scala 36:13] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1290 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1291 = or(_T_1077, reset) @[BaseCoreplex.scala 36:13] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1293 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1294 = eq(io.in[0].b.bits.mask, _T_1145) @[BaseCoreplex.scala 36:13] + node _T_1295 = or(_T_1294, reset) @[BaseCoreplex.scala 36:13] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1297 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + when io.in[0].c.valid : @[BaseCoreplex.scala 36:13] + node _T_1299 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1300 = or(_T_1299, reset) @[BaseCoreplex.scala 36:13] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1302 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1304 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1305 = not(_T_1304) @[Parameters.scala 37:9] + node _T_1307 = or(_T_1305, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1308 = not(_T_1307) @[Parameters.scala 37:7] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1313 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1313 is invalid @[Parameters.scala 228:27] + _T_1313[0] <= _T_1310 @[Parameters.scala 228:27] + node _T_1318 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1319 = dshl(_T_1318, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1320 = bits(_T_1319, 7, 0) @[package.scala 19:76] + node _T_1321 = not(_T_1320) @[package.scala 19:40] + node _T_1322 = and(io.in[0].c.bits.address, _T_1321) @[Edges.scala 17:16] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1326 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1327 = cvt(_T_1326) @[Parameters.scala 117:49] + node _T_1329 = and(_T_1327, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1330 = asSInt(_T_1329) @[Parameters.scala 117:52] + node _T_1332 = eq(_T_1330, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1334 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1335 = cvt(_T_1334) @[Parameters.scala 117:49] + node _T_1337 = and(_T_1335, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1338 = asSInt(_T_1337) @[Parameters.scala 117:52] + node _T_1340 = eq(_T_1338, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1343 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1343 is invalid @[Parameters.scala 110:36] + _T_1343[0] <= _T_1332 @[Parameters.scala 110:36] + _T_1343[1] <= _T_1340 @[Parameters.scala 110:36] + node _T_1348 = or(_T_1343[0], _T_1343[1]) @[Parameters.scala 119:64] + node _T_1350 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[BaseCoreplex.scala 36:13] + when _T_1350 : @[BaseCoreplex.scala 36:13] + node _T_1351 = or(_T_1348, reset) @[BaseCoreplex.scala 36:13] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1353 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1354 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1356 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1358 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1359 = or(_T_1358, reset) @[BaseCoreplex.scala 36:13] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1361 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1362 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1364 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1366 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1367 = or(_T_1366, reset) @[BaseCoreplex.scala 36:13] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1369 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1371 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1372 = or(_T_1371, reset) @[BaseCoreplex.scala 36:13] + node _T_1374 = eq(_T_1372, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1374 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1376 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[BaseCoreplex.scala 36:13] + when _T_1376 : @[BaseCoreplex.scala 36:13] + node _T_1377 = or(_T_1348, reset) @[BaseCoreplex.scala 36:13] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1379 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1380 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1382 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1384 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1385 = or(_T_1384, reset) @[BaseCoreplex.scala 36:13] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1387 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1388 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1390 = eq(_T_1388, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1390 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1392 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1393 = or(_T_1392, reset) @[BaseCoreplex.scala 36:13] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1395 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1397 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1398 = or(_T_1397, reset) @[BaseCoreplex.scala 36:13] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1400 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1402 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + when _T_1402 : @[BaseCoreplex.scala 36:13] + node _T_1405 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1407 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1422 = or(_T_1413, _T_1421) @[Parameters.scala 133:42] + node _T_1423 = and(_T_1405, _T_1422) @[Parameters.scala 132:56] + node _T_1425 = or(UInt<1>("h00"), _T_1423) @[Parameters.scala 134:30] + node _T_1426 = or(_T_1425, reset) @[BaseCoreplex.scala 36:13] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1428 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1429 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1431 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1433 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1434 = or(_T_1433, reset) @[BaseCoreplex.scala 36:13] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1436 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1437 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1439 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1441 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1442 = or(_T_1441, reset) @[BaseCoreplex.scala 36:13] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1444 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1446 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1447 = or(_T_1446, reset) @[BaseCoreplex.scala 36:13] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1449 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1451 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[BaseCoreplex.scala 36:13] + when _T_1451 : @[BaseCoreplex.scala 36:13] + node _T_1454 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1456 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1457 = cvt(_T_1456) @[Parameters.scala 117:49] + node _T_1459 = and(_T_1457, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1460 = asSInt(_T_1459) @[Parameters.scala 117:52] + node _T_1462 = eq(_T_1460, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1464 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1465 = cvt(_T_1464) @[Parameters.scala 117:49] + node _T_1467 = and(_T_1465, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1468 = asSInt(_T_1467) @[Parameters.scala 117:52] + node _T_1470 = eq(_T_1468, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1471 = or(_T_1462, _T_1470) @[Parameters.scala 133:42] + node _T_1472 = and(_T_1454, _T_1471) @[Parameters.scala 132:56] + node _T_1474 = or(UInt<1>("h00"), _T_1472) @[Parameters.scala 134:30] + node _T_1475 = or(_T_1474, reset) @[BaseCoreplex.scala 36:13] + node _T_1477 = eq(_T_1475, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1477 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1478 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1480 = eq(_T_1478, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1480 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1482 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1483 = or(_T_1482, reset) @[BaseCoreplex.scala 36:13] + node _T_1485 = eq(_T_1483, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1485 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1486 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1488 = eq(_T_1486, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1488 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1490 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1491 = or(_T_1490, reset) @[BaseCoreplex.scala 36:13] + node _T_1493 = eq(_T_1491, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1493 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1495 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1496 = or(_T_1495, reset) @[BaseCoreplex.scala 36:13] + node _T_1498 = eq(_T_1496, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1498 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1500 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1500 : @[BaseCoreplex.scala 36:13] + node _T_1501 = or(_T_1348, reset) @[BaseCoreplex.scala 36:13] + node _T_1503 = eq(_T_1501, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1503 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1504 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1506 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1507 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1509 = eq(_T_1507, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1509 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1511 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1512 = or(_T_1511, reset) @[BaseCoreplex.scala 36:13] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1514 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1516 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[BaseCoreplex.scala 36:13] + when _T_1516 : @[BaseCoreplex.scala 36:13] + node _T_1517 = or(_T_1348, reset) @[BaseCoreplex.scala 36:13] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1519 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1520 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1522 = eq(_T_1520, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1522 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1523 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1525 = eq(_T_1523, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1525 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1527 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1528 = or(_T_1527, reset) @[BaseCoreplex.scala 36:13] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1530 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1532 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + when _T_1532 : @[BaseCoreplex.scala 36:13] + node _T_1533 = or(_T_1348, reset) @[BaseCoreplex.scala 36:13] + node _T_1535 = eq(_T_1533, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1535 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1536 = or(_T_1313[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1538 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1539 = or(_T_1324, reset) @[BaseCoreplex.scala 36:13] + node _T_1541 = eq(_T_1539, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1541 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1543 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1544 = or(_T_1543, reset) @[BaseCoreplex.scala 36:13] + node _T_1546 = eq(_T_1544, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1546 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1548 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1549 = or(_T_1548, reset) @[BaseCoreplex.scala 36:13] + node _T_1551 = eq(_T_1549, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1551 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + when io.in[0].d.valid : @[BaseCoreplex.scala 36:13] + node _T_1553 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1554 = or(_T_1553, reset) @[BaseCoreplex.scala 36:13] + node _T_1556 = eq(_T_1554, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1556 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1558 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1559 = not(_T_1558) @[Parameters.scala 37:9] + node _T_1561 = or(_T_1559, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1562 = not(_T_1561) @[Parameters.scala 37:7] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1567 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1567 is invalid @[Parameters.scala 228:27] + _T_1567[0] <= _T_1564 @[Parameters.scala 228:27] + node _T_1572 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1573 = dshl(_T_1572, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1574 = bits(_T_1573, 7, 0) @[package.scala 19:76] + node _T_1575 = not(_T_1574) @[package.scala 19:40] + node _T_1576 = and(io.in[0].d.bits.addr_lo, _T_1575) @[Edges.scala 17:16] + node _T_1578 = eq(_T_1576, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1580 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + node _T_1582 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + when _T_1582 : @[BaseCoreplex.scala 36:13] + node _T_1583 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1585 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1586 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1588 = eq(_T_1586, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1588 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1589 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1591 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1593 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1594 = or(_T_1593, reset) @[BaseCoreplex.scala 36:13] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1596 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1598 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1599 = or(_T_1598, reset) @[BaseCoreplex.scala 36:13] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1601 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1603 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1604 = or(_T_1603, reset) @[BaseCoreplex.scala 36:13] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1606 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1608 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[BaseCoreplex.scala 36:13] + when _T_1608 : @[BaseCoreplex.scala 36:13] + node _T_1609 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1611 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1612 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1614 = eq(_T_1612, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1614 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1615 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1617 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1619 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1620 = or(_T_1619, reset) @[BaseCoreplex.scala 36:13] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1622 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1624 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1625 = or(_T_1624, reset) @[BaseCoreplex.scala 36:13] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1627 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1629 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[BaseCoreplex.scala 36:13] + when _T_1629 : @[BaseCoreplex.scala 36:13] + node _T_1630 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1632 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1633 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1635 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1636 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1638 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1640 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[BaseCoreplex.scala 36:13] + node _T_1641 = or(_T_1640, reset) @[BaseCoreplex.scala 36:13] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1643 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1645 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1646 = or(_T_1645, reset) @[BaseCoreplex.scala 36:13] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1648 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1650 : @[BaseCoreplex.scala 36:13] + node _T_1651 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1653 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1654 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1656 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1657 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1659 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1662 = or(_T_1661, reset) @[BaseCoreplex.scala 36:13] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1664 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[BaseCoreplex.scala 36:13] + when _T_1666 : @[BaseCoreplex.scala 36:13] + node _T_1667 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1669 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1670 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1672 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1673 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1675 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1678 = or(_T_1677, reset) @[BaseCoreplex.scala 36:13] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1680 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1682 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + when _T_1682 : @[BaseCoreplex.scala 36:13] + node _T_1683 = or(_T_1567[0], reset) @[BaseCoreplex.scala 36:13] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1685 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1686 = or(_T_1578, reset) @[BaseCoreplex.scala 36:13] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1688 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1689 = or(_T_1580, reset) @[BaseCoreplex.scala 36:13] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1691 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1693 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1694 = or(_T_1693, reset) @[BaseCoreplex.scala 36:13] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1696 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1698 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1699 = or(_T_1698, reset) @[BaseCoreplex.scala 36:13] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1701 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + when io.in[0].e.valid : @[BaseCoreplex.scala 36:13] + node _T_1703 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[BaseCoreplex.scala 36:13] + node _T_1704 = or(_T_1703, reset) @[BaseCoreplex.scala 36:13] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1706 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1707 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 7, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1718 = mux(_T_1716, _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1720 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1722 = sub(_T_1720, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1723 = asUInt(_T_1722) @[Edges.scala 208:28] + node _T_1724 = tail(_T_1723, 1) @[Edges.scala 208:28] + node _T_1726 = eq(_T_1720, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1728 = eq(_T_1720, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1730 = eq(_T_1718, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1731 = or(_T_1728, _T_1730) @[Edges.scala 210:37] + node _T_1732 = and(_T_1731, _T_1707) @[Edges.scala 211:22] + node _T_1733 = not(_T_1724) @[Edges.scala 212:27] + node _T_1734 = and(_T_1718, _T_1733) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1735 = mux(_T_1726, _T_1718, _T_1724) @[Edges.scala 214:21] + _T_1720 <= _T_1735 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1737 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1739 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1741 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1743 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1745 : UInt, clock @[BaseCoreplex.scala 36:13] + node _T_1747 = eq(_T_1726, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1748 = and(io.in[0].a.valid, _T_1747) @[BaseCoreplex.scala 36:13] + when _T_1748 : @[BaseCoreplex.scala 36:13] + node _T_1749 = eq(io.in[0].a.bits.opcode, _T_1737) @[BaseCoreplex.scala 36:13] + node _T_1750 = or(_T_1749, reset) @[BaseCoreplex.scala 36:13] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1752 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1753 = eq(io.in[0].a.bits.param, _T_1739) @[BaseCoreplex.scala 36:13] + node _T_1754 = or(_T_1753, reset) @[BaseCoreplex.scala 36:13] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1756 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1757 = eq(io.in[0].a.bits.size, _T_1741) @[BaseCoreplex.scala 36:13] + node _T_1758 = or(_T_1757, reset) @[BaseCoreplex.scala 36:13] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1760 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1761 = eq(io.in[0].a.bits.source, _T_1743) @[BaseCoreplex.scala 36:13] + node _T_1762 = or(_T_1761, reset) @[BaseCoreplex.scala 36:13] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1764 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1765 = eq(io.in[0].a.bits.address, _T_1745) @[BaseCoreplex.scala 36:13] + node _T_1766 = or(_T_1765, reset) @[BaseCoreplex.scala 36:13] + node _T_1768 = eq(_T_1766, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1768 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1769 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1770 = and(_T_1769, _T_1726) @[BaseCoreplex.scala 36:13] + when _T_1770 : @[BaseCoreplex.scala 36:13] + _T_1737 <= io.in[0].a.bits.opcode @[BaseCoreplex.scala 36:13] + _T_1739 <= io.in[0].a.bits.param @[BaseCoreplex.scala 36:13] + _T_1741 <= io.in[0].a.bits.size @[BaseCoreplex.scala 36:13] + _T_1743 <= io.in[0].a.bits.source @[BaseCoreplex.scala 36:13] + _T_1745 <= io.in[0].a.bits.address @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1771 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1773 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1774 = dshl(_T_1773, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1775 = bits(_T_1774, 7, 0) @[package.scala 19:76] + node _T_1776 = not(_T_1775) @[package.scala 19:40] + node _T_1777 = shr(_T_1776, 3) @[Edges.scala 198:59] + node _T_1778 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1780 = eq(_T_1778, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1783 = mux(UInt<1>("h00"), _T_1777, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1771) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1771 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1804 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1806 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1808 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1810 : UInt, clock @[BaseCoreplex.scala 36:13] + node _T_1812 = eq(_T_1791, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1813 = and(io.in[0].b.valid, _T_1812) @[BaseCoreplex.scala 36:13] + when _T_1813 : @[BaseCoreplex.scala 36:13] + node _T_1814 = eq(io.in[0].b.bits.opcode, _T_1802) @[BaseCoreplex.scala 36:13] + node _T_1815 = or(_T_1814, reset) @[BaseCoreplex.scala 36:13] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1817 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1818 = eq(io.in[0].b.bits.param, _T_1804) @[BaseCoreplex.scala 36:13] + node _T_1819 = or(_T_1818, reset) @[BaseCoreplex.scala 36:13] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1821 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1822 = eq(io.in[0].b.bits.size, _T_1806) @[BaseCoreplex.scala 36:13] + node _T_1823 = or(_T_1822, reset) @[BaseCoreplex.scala 36:13] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1825 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1826 = eq(io.in[0].b.bits.source, _T_1808) @[BaseCoreplex.scala 36:13] + node _T_1827 = or(_T_1826, reset) @[BaseCoreplex.scala 36:13] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1829 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1830 = eq(io.in[0].b.bits.address, _T_1810) @[BaseCoreplex.scala 36:13] + node _T_1831 = or(_T_1830, reset) @[BaseCoreplex.scala 36:13] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1833 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1834 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1835 = and(_T_1834, _T_1791) @[BaseCoreplex.scala 36:13] + when _T_1835 : @[BaseCoreplex.scala 36:13] + _T_1802 <= io.in[0].b.bits.opcode @[BaseCoreplex.scala 36:13] + _T_1804 <= io.in[0].b.bits.param @[BaseCoreplex.scala 36:13] + _T_1806 <= io.in[0].b.bits.size @[BaseCoreplex.scala 36:13] + _T_1808 <= io.in[0].b.bits.source @[BaseCoreplex.scala 36:13] + _T_1810 <= io.in[0].b.bits.address @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1836 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1838 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1839 = dshl(_T_1838, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1840 = bits(_T_1839, 7, 0) @[package.scala 19:76] + node _T_1841 = not(_T_1840) @[package.scala 19:40] + node _T_1842 = shr(_T_1841, 3) @[Edges.scala 198:59] + node _T_1843 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1846 = mux(UInt<1>("h00"), _T_1842, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1836) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1836 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1865 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1867 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1869 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1871 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1873 : UInt, clock @[BaseCoreplex.scala 36:13] + node _T_1875 = eq(_T_1854, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1876 = and(io.in[0].c.valid, _T_1875) @[BaseCoreplex.scala 36:13] + when _T_1876 : @[BaseCoreplex.scala 36:13] + node _T_1877 = eq(io.in[0].c.bits.opcode, _T_1865) @[BaseCoreplex.scala 36:13] + node _T_1878 = or(_T_1877, reset) @[BaseCoreplex.scala 36:13] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1880 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1881 = eq(io.in[0].c.bits.param, _T_1867) @[BaseCoreplex.scala 36:13] + node _T_1882 = or(_T_1881, reset) @[BaseCoreplex.scala 36:13] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1884 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1885 = eq(io.in[0].c.bits.size, _T_1869) @[BaseCoreplex.scala 36:13] + node _T_1886 = or(_T_1885, reset) @[BaseCoreplex.scala 36:13] + node _T_1888 = eq(_T_1886, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1888 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1889 = eq(io.in[0].c.bits.source, _T_1871) @[BaseCoreplex.scala 36:13] + node _T_1890 = or(_T_1889, reset) @[BaseCoreplex.scala 36:13] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1892 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1893 = eq(io.in[0].c.bits.address, _T_1873) @[BaseCoreplex.scala 36:13] + node _T_1894 = or(_T_1893, reset) @[BaseCoreplex.scala 36:13] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1896 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1897 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1898 = and(_T_1897, _T_1854) @[BaseCoreplex.scala 36:13] + when _T_1898 : @[BaseCoreplex.scala 36:13] + _T_1865 <= io.in[0].c.bits.opcode @[BaseCoreplex.scala 36:13] + _T_1867 <= io.in[0].c.bits.param @[BaseCoreplex.scala 36:13] + _T_1869 <= io.in[0].c.bits.size @[BaseCoreplex.scala 36:13] + _T_1871 <= io.in[0].c.bits.source @[BaseCoreplex.scala 36:13] + _T_1873 <= io.in[0].c.bits.address @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1899 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1902 = dshl(_T_1901, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1903 = bits(_T_1902, 7, 0) @[package.scala 19:76] + node _T_1904 = not(_T_1903) @[package.scala 19:40] + node _T_1905 = shr(_T_1904, 3) @[Edges.scala 198:59] + node _T_1906 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1908 = mux(_T_1906, _T_1905, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1910 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1912 = sub(_T_1910, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1913 = asUInt(_T_1912) @[Edges.scala 208:28] + node _T_1914 = tail(_T_1913, 1) @[Edges.scala 208:28] + node _T_1916 = eq(_T_1910, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1918 = eq(_T_1910, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1920 = eq(_T_1908, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1921 = or(_T_1918, _T_1920) @[Edges.scala 210:37] + node _T_1922 = and(_T_1921, _T_1899) @[Edges.scala 211:22] + node _T_1923 = not(_T_1914) @[Edges.scala 212:27] + node _T_1924 = and(_T_1908, _T_1923) @[Edges.scala 212:25] + when _T_1899 : @[Edges.scala 213:17] + node _T_1925 = mux(_T_1916, _T_1908, _T_1914) @[Edges.scala 214:21] + _T_1910 <= _T_1925 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1927 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1929 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1931 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1933 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1935 : UInt, clock @[BaseCoreplex.scala 36:13] + reg _T_1937 : UInt, clock @[BaseCoreplex.scala 36:13] + node _T_1939 = eq(_T_1916, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_1940 = and(io.in[0].d.valid, _T_1939) @[BaseCoreplex.scala 36:13] + when _T_1940 : @[BaseCoreplex.scala 36:13] + node _T_1941 = eq(io.in[0].d.bits.opcode, _T_1927) @[BaseCoreplex.scala 36:13] + node _T_1942 = or(_T_1941, reset) @[BaseCoreplex.scala 36:13] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1944 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1945 = eq(io.in[0].d.bits.param, _T_1929) @[BaseCoreplex.scala 36:13] + node _T_1946 = or(_T_1945, reset) @[BaseCoreplex.scala 36:13] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1948 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1949 = eq(io.in[0].d.bits.size, _T_1931) @[BaseCoreplex.scala 36:13] + node _T_1950 = or(_T_1949, reset) @[BaseCoreplex.scala 36:13] + node _T_1952 = eq(_T_1950, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1952 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1953 = eq(io.in[0].d.bits.source, _T_1933) @[BaseCoreplex.scala 36:13] + node _T_1954 = or(_T_1953, reset) @[BaseCoreplex.scala 36:13] + node _T_1956 = eq(_T_1954, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1956 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1957 = eq(io.in[0].d.bits.sink, _T_1935) @[BaseCoreplex.scala 36:13] + node _T_1958 = or(_T_1957, reset) @[BaseCoreplex.scala 36:13] + node _T_1960 = eq(_T_1958, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1960 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1961 = eq(io.in[0].d.bits.addr_lo, _T_1937) @[BaseCoreplex.scala 36:13] + node _T_1962 = or(_T_1961, reset) @[BaseCoreplex.scala 36:13] + node _T_1964 = eq(_T_1962, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_1964 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_1965 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1966 = and(_T_1965, _T_1916) @[BaseCoreplex.scala 36:13] + when _T_1966 : @[BaseCoreplex.scala 36:13] + _T_1927 <= io.in[0].d.bits.opcode @[BaseCoreplex.scala 36:13] + _T_1929 <= io.in[0].d.bits.param @[BaseCoreplex.scala 36:13] + _T_1931 <= io.in[0].d.bits.size @[BaseCoreplex.scala 36:13] + _T_1933 <= io.in[0].d.bits.source @[BaseCoreplex.scala 36:13] + _T_1935 <= io.in[0].d.bits.sink @[BaseCoreplex.scala 36:13] + _T_1937 <= io.in[0].d.bits.addr_lo @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + reg _T_1968 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_1969 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1971 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1972 = dshl(_T_1971, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1973 = bits(_T_1972, 7, 0) @[package.scala 19:76] + node _T_1974 = not(_T_1973) @[package.scala 19:40] + node _T_1975 = shr(_T_1974, 3) @[Edges.scala 198:59] + node _T_1976 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1978 = eq(_T_1976, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1980 = mux(_T_1978, _T_1975, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1982 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1984 = sub(_T_1982, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1985 = asUInt(_T_1984) @[Edges.scala 208:28] + node _T_1986 = tail(_T_1985, 1) @[Edges.scala 208:28] + node _T_1988 = eq(_T_1982, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1990 = eq(_T_1982, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1992 = eq(_T_1980, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1993 = or(_T_1990, _T_1992) @[Edges.scala 210:37] + node _T_1994 = and(_T_1993, _T_1969) @[Edges.scala 211:22] + node _T_1995 = not(_T_1986) @[Edges.scala 212:27] + node _T_1996 = and(_T_1980, _T_1995) @[Edges.scala 212:25] + when _T_1969 : @[Edges.scala 213:17] + node _T_1997 = mux(_T_1988, _T_1980, _T_1986) @[Edges.scala 214:21] + _T_1982 <= _T_1997 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1998 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2000 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2001 = dshl(_T_2000, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2002 = bits(_T_2001, 7, 0) @[package.scala 19:76] + node _T_2003 = not(_T_2002) @[package.scala 19:40] + node _T_2004 = shr(_T_2003, 3) @[Edges.scala 198:59] + node _T_2005 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2007 = mux(_T_2005, _T_2004, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2009 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2011 = sub(_T_2009, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2012 = asUInt(_T_2011) @[Edges.scala 208:28] + node _T_2013 = tail(_T_2012, 1) @[Edges.scala 208:28] + node _T_2015 = eq(_T_2009, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2017 = eq(_T_2009, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2019 = eq(_T_2007, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2020 = or(_T_2017, _T_2019) @[Edges.scala 210:37] + node _T_2021 = and(_T_2020, _T_1998) @[Edges.scala 211:22] + node _T_2022 = not(_T_2013) @[Edges.scala 212:27] + node _T_2023 = and(_T_2007, _T_2022) @[Edges.scala 212:25] + when _T_1998 : @[Edges.scala 213:17] + node _T_2024 = mux(_T_2015, _T_2007, _T_2013) @[Edges.scala 214:21] + _T_2009 <= _T_2024 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2026 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + node _T_2027 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[BaseCoreplex.scala 36:13] + node _T_2028 = or(_T_2026, _T_2027) @[BaseCoreplex.scala 36:13] + node _T_2030 = eq(io.in[0].a.valid, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_2031 = or(_T_2028, _T_2030) @[BaseCoreplex.scala 36:13] + node _T_2033 = eq(io.in[0].d.valid, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_2034 = or(_T_2031, _T_2033) @[BaseCoreplex.scala 36:13] + node _T_2035 = or(_T_2034, reset) @[BaseCoreplex.scala 36:13] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_2037 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + wire _T_2039 : UInt<32> + _T_2039 is invalid + _T_2039 <= UInt<32>("h00") + node _T_2040 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2040 : @[BaseCoreplex.scala 36:13] + when _T_1993 : @[BaseCoreplex.scala 36:13] + node _T_2042 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2039 <= _T_2042 @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_2043 = dshr(_T_1968, io.in[0].a.bits.source) @[BaseCoreplex.scala 36:13] + node _T_2044 = bits(_T_2043, 0, 0) @[BaseCoreplex.scala 36:13] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + node _T_2047 = or(_T_2046, reset) @[BaseCoreplex.scala 36:13] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_2049 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + wire _T_2051 : UInt<32> + _T_2051 is invalid + _T_2051 <= UInt<32>("h00") + node _T_2052 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2054 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[BaseCoreplex.scala 36:13] + node _T_2055 = and(_T_2052, _T_2054) @[BaseCoreplex.scala 36:13] + when _T_2055 : @[BaseCoreplex.scala 36:13] + when _T_2020 : @[BaseCoreplex.scala 36:13] + node _T_2057 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2051 <= _T_2057 @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_2058 = or(_T_2039, _T_1968) @[BaseCoreplex.scala 36:13] + node _T_2059 = dshr(_T_2058, io.in[0].d.bits.source) @[BaseCoreplex.scala 36:13] + node _T_2060 = bits(_T_2059, 0, 0) @[BaseCoreplex.scala 36:13] + node _T_2061 = or(_T_2060, reset) @[BaseCoreplex.scala 36:13] + node _T_2063 = eq(_T_2061, UInt<1>("h00")) @[BaseCoreplex.scala 36:13] + when _T_2063 : @[BaseCoreplex.scala 36:13] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BaseCoreplex.scala:36:13)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[BaseCoreplex.scala 36:13] + stop(clock, UInt<1>(1), 1) @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + skip @[BaseCoreplex.scala 36:13] + node _T_2064 = or(_T_1968, _T_2039) @[BaseCoreplex.scala 36:13] + node _T_2065 = not(_T_2051) @[BaseCoreplex.scala 36:13] + node _T_2066 = and(_T_2064, _T_2065) @[BaseCoreplex.scala 36:13] + _T_1968 <= _T_2066 @[BaseCoreplex.scala 36:13] + + module TLMonitor_22 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 133:10] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 133:10] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_608 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + when _T_708 : @[CoreplexNetwork.scala 133:10] + node _T_711 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_713 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_714 = and(_T_711, _T_713) @[Parameters.scala 63:37] + node _T_715 = or(UInt<1>("h00"), _T_714) @[Parameters.scala 132:31] + node _T_717 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_718 = cvt(_T_717) @[Parameters.scala 117:49] + node _T_720 = and(_T_718, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_721 = asSInt(_T_720) @[Parameters.scala 117:52] + node _T_723 = eq(_T_721, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_725 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_726 = cvt(_T_725) @[Parameters.scala 117:49] + node _T_728 = and(_T_726, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_729 = asSInt(_T_728) @[Parameters.scala 117:52] + node _T_731 = eq(_T_729, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_732 = or(_T_723, _T_731) @[Parameters.scala 133:42] + node _T_733 = and(_T_715, _T_732) @[Parameters.scala 132:56] + node _T_735 = or(UInt<1>("h00"), _T_733) @[Parameters.scala 134:30] + node _T_736 = or(_T_735, reset) @[CoreplexNetwork.scala 133:10] + node _T_738 = eq(_T_736, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_738 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_739 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_741 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_743 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_744 = or(_T_743, reset) @[CoreplexNetwork.scala 133:10] + node _T_746 = eq(_T_744, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_746 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_747 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_749 = eq(_T_747, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_749 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_751 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_752 = or(_T_751, reset) @[CoreplexNetwork.scala 133:10] + node _T_754 = eq(_T_752, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_754 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_755 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 133:10] + node _T_757 = eq(_T_755, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_758 = or(_T_757, reset) @[CoreplexNetwork.scala 133:10] + node _T_760 = eq(_T_758, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_760 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_762 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + when _T_762 : @[CoreplexNetwork.scala 133:10] + node _T_765 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_767 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_768 = and(_T_765, _T_767) @[Parameters.scala 63:37] + node _T_769 = or(UInt<1>("h00"), _T_768) @[Parameters.scala 132:31] + node _T_771 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_772 = cvt(_T_771) @[Parameters.scala 117:49] + node _T_774 = and(_T_772, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_775 = asSInt(_T_774) @[Parameters.scala 117:52] + node _T_777 = eq(_T_775, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_779 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_780 = cvt(_T_779) @[Parameters.scala 117:49] + node _T_782 = and(_T_780, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_783 = asSInt(_T_782) @[Parameters.scala 117:52] + node _T_785 = eq(_T_783, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_786 = or(_T_777, _T_785) @[Parameters.scala 133:42] + node _T_787 = and(_T_769, _T_786) @[Parameters.scala 132:56] + node _T_789 = or(UInt<1>("h00"), _T_787) @[Parameters.scala 134:30] + node _T_790 = or(_T_789, reset) @[CoreplexNetwork.scala 133:10] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_792 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_793 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_795 = eq(_T_793, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_795 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_796 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_798 = eq(_T_796, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_798 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_800 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_801 = or(_T_800, reset) @[CoreplexNetwork.scala 133:10] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_803 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_804 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 133:10] + node _T_805 = or(_T_804, reset) @[CoreplexNetwork.scala 133:10] + node _T_807 = eq(_T_805, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_807 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_809 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_809 : @[CoreplexNetwork.scala 133:10] + node _T_812 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_814 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_815 = and(_T_812, _T_814) @[Parameters.scala 63:37] + node _T_816 = or(UInt<1>("h00"), _T_815) @[Parameters.scala 132:31] + node _T_818 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_819 = cvt(_T_818) @[Parameters.scala 117:49] + node _T_821 = and(_T_819, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_822 = asSInt(_T_821) @[Parameters.scala 117:52] + node _T_824 = eq(_T_822, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_826 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_827 = cvt(_T_826) @[Parameters.scala 117:49] + node _T_829 = and(_T_827, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_830 = asSInt(_T_829) @[Parameters.scala 117:52] + node _T_832 = eq(_T_830, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_833 = or(_T_824, _T_832) @[Parameters.scala 133:42] + node _T_834 = and(_T_816, _T_833) @[Parameters.scala 132:56] + node _T_836 = or(UInt<1>("h00"), _T_834) @[Parameters.scala 134:30] + node _T_837 = or(_T_836, reset) @[CoreplexNetwork.scala 133:10] + node _T_839 = eq(_T_837, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_839 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_840 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_842 = eq(_T_840, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_842 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_843 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_845 = eq(_T_843, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_845 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_847 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_848 = or(_T_847, reset) @[CoreplexNetwork.scala 133:10] + node _T_850 = eq(_T_848, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_850 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_851 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 133:10] + node _T_852 = or(_T_851, reset) @[CoreplexNetwork.scala 133:10] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_854 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_856 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 133:10] + when _T_856 : @[CoreplexNetwork.scala 133:10] + node _T_859 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_861 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_862 = and(_T_859, _T_861) @[Parameters.scala 63:37] + node _T_863 = or(UInt<1>("h00"), _T_862) @[Parameters.scala 132:31] + node _T_865 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_873 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_874 = cvt(_T_873) @[Parameters.scala 117:49] + node _T_876 = and(_T_874, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_877 = asSInt(_T_876) @[Parameters.scala 117:52] + node _T_879 = eq(_T_877, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_880 = or(_T_871, _T_879) @[Parameters.scala 133:42] + node _T_881 = and(_T_863, _T_880) @[Parameters.scala 132:56] + node _T_883 = or(UInt<1>("h00"), _T_881) @[Parameters.scala 134:30] + node _T_884 = or(_T_883, reset) @[CoreplexNetwork.scala 133:10] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_886 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_887 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_889 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_890 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_892 = eq(_T_890, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_892 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_894 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_895 = or(_T_894, reset) @[CoreplexNetwork.scala 133:10] + node _T_897 = eq(_T_895, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_897 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_898 = not(_T_706) @[CoreplexNetwork.scala 133:10] + node _T_899 = and(io.in[0].a.bits.mask, _T_898) @[CoreplexNetwork.scala 133:10] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_902 = or(_T_901, reset) @[CoreplexNetwork.scala 133:10] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_904 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_906 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 133:10] + when _T_906 : @[CoreplexNetwork.scala 133:10] + node _T_909 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_911 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_912 = cvt(_T_911) @[Parameters.scala 117:49] + node _T_914 = and(_T_912, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_915 = asSInt(_T_914) @[Parameters.scala 117:52] + node _T_917 = eq(_T_915, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_919 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_920 = cvt(_T_919) @[Parameters.scala 117:49] + node _T_922 = and(_T_920, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_923 = asSInt(_T_922) @[Parameters.scala 117:52] + node _T_925 = eq(_T_923, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_926 = or(_T_917, _T_925) @[Parameters.scala 133:42] + node _T_927 = and(_T_909, _T_926) @[Parameters.scala 132:56] + node _T_929 = or(UInt<1>("h00"), _T_927) @[Parameters.scala 134:30] + node _T_930 = or(_T_929, reset) @[CoreplexNetwork.scala 133:10] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_932 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_933 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_935 = eq(_T_933, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_935 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_936 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_938 = eq(_T_936, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_938 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_940 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_941 = or(_T_940, reset) @[CoreplexNetwork.scala 133:10] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_943 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_944 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 133:10] + node _T_945 = or(_T_944, reset) @[CoreplexNetwork.scala 133:10] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_947 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_949 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + when _T_949 : @[CoreplexNetwork.scala 133:10] + node _T_952 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_954 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_955 = cvt(_T_954) @[Parameters.scala 117:49] + node _T_957 = and(_T_955, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_958 = asSInt(_T_957) @[Parameters.scala 117:52] + node _T_960 = eq(_T_958, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_962 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_963 = cvt(_T_962) @[Parameters.scala 117:49] + node _T_965 = and(_T_963, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_966 = asSInt(_T_965) @[Parameters.scala 117:52] + node _T_968 = eq(_T_966, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_969 = or(_T_960, _T_968) @[Parameters.scala 133:42] + node _T_970 = and(_T_952, _T_969) @[Parameters.scala 132:56] + node _T_972 = or(UInt<1>("h00"), _T_970) @[Parameters.scala 134:30] + node _T_973 = or(_T_972, reset) @[CoreplexNetwork.scala 133:10] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_975 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_976 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_978 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_979 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_981 = eq(_T_979, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_981 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_983 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_984 = or(_T_983, reset) @[CoreplexNetwork.scala 133:10] + node _T_986 = eq(_T_984, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_986 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_987 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 133:10] + node _T_988 = or(_T_987, reset) @[CoreplexNetwork.scala 133:10] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_990 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_992 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 133:10] + when _T_992 : @[CoreplexNetwork.scala 133:10] + node _T_995 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_997 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_998 = cvt(_T_997) @[Parameters.scala 117:49] + node _T_1000 = and(_T_998, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1001 = asSInt(_T_1000) @[Parameters.scala 117:52] + node _T_1003 = eq(_T_1001, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1005 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1006 = cvt(_T_1005) @[Parameters.scala 117:49] + node _T_1008 = and(_T_1006, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1009 = asSInt(_T_1008) @[Parameters.scala 117:52] + node _T_1011 = eq(_T_1009, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1012 = or(_T_1003, _T_1011) @[Parameters.scala 133:42] + node _T_1013 = and(_T_995, _T_1012) @[Parameters.scala 132:56] + node _T_1015 = or(UInt<1>("h00"), _T_1013) @[Parameters.scala 134:30] + node _T_1016 = or(_T_1015, reset) @[CoreplexNetwork.scala 133:10] + node _T_1018 = eq(_T_1016, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1018 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1019 = or(_T_630, reset) @[CoreplexNetwork.scala 133:10] + node _T_1021 = eq(_T_1019, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1021 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1022 = or(_T_638, reset) @[CoreplexNetwork.scala 133:10] + node _T_1024 = eq(_T_1022, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1024 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1025 = eq(io.in[0].a.bits.mask, _T_706) @[CoreplexNetwork.scala 133:10] + node _T_1026 = or(_T_1025, reset) @[CoreplexNetwork.scala 133:10] + node _T_1028 = eq(_T_1026, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1028 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + when io.in[0].b.valid : @[CoreplexNetwork.scala 133:10] + node _T_1030 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1031 = or(_T_1030, reset) @[CoreplexNetwork.scala 133:10] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1033 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1035 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1036 = cvt(_T_1035) @[Parameters.scala 117:49] + node _T_1038 = and(_T_1036, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1039 = asSInt(_T_1038) @[Parameters.scala 117:52] + node _T_1041 = eq(_T_1039, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1043 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1044 = cvt(_T_1043) @[Parameters.scala 117:49] + node _T_1046 = and(_T_1044, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1047 = asSInt(_T_1046) @[Parameters.scala 117:52] + node _T_1049 = eq(_T_1047, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1052 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1052 is invalid @[Parameters.scala 110:36] + _T_1052[0] <= _T_1041 @[Parameters.scala 110:36] + _T_1052[1] <= _T_1049 @[Parameters.scala 110:36] + node _T_1057 = or(_T_1052[0], _T_1052[1]) @[Parameters.scala 119:64] + node _T_1059 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1060 = dshl(_T_1059, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1061 = bits(_T_1060, 5, 0) @[package.scala 19:76] + node _T_1062 = not(_T_1061) @[package.scala 19:40] + node _T_1063 = and(io.in[0].b.bits.address, _T_1062) @[Edges.scala 17:16] + node _T_1065 = eq(_T_1063, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1067 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1068 = dshl(UInt<1>("h01"), _T_1067) @[OneHot.scala 49:12] + node _T_1069 = bits(_T_1068, 2, 0) @[OneHot.scala 49:37] + node _T_1071 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1073 = bits(_T_1069, 2, 2) @[package.scala 44:26] + node _T_1074 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[package.scala 46:20] + node _T_1077 = and(UInt<1>("h01"), _T_1076) @[package.scala 49:27] + node _T_1078 = and(_T_1073, _T_1077) @[package.scala 50:38] + node _T_1079 = or(_T_1071, _T_1078) @[package.scala 50:29] + node _T_1080 = and(UInt<1>("h01"), _T_1074) @[package.scala 49:27] + node _T_1081 = and(_T_1073, _T_1080) @[package.scala 50:38] + node _T_1082 = or(_T_1071, _T_1081) @[package.scala 50:29] + node _T_1083 = bits(_T_1069, 1, 1) @[package.scala 44:26] + node _T_1084 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1086 = eq(_T_1084, UInt<1>("h00")) @[package.scala 46:20] + node _T_1087 = and(_T_1077, _T_1086) @[package.scala 49:27] + node _T_1088 = and(_T_1083, _T_1087) @[package.scala 50:38] + node _T_1089 = or(_T_1079, _T_1088) @[package.scala 50:29] + node _T_1090 = and(_T_1077, _T_1084) @[package.scala 49:27] + node _T_1091 = and(_T_1083, _T_1090) @[package.scala 50:38] + node _T_1092 = or(_T_1079, _T_1091) @[package.scala 50:29] + node _T_1093 = and(_T_1080, _T_1086) @[package.scala 49:27] + node _T_1094 = and(_T_1083, _T_1093) @[package.scala 50:38] + node _T_1095 = or(_T_1082, _T_1094) @[package.scala 50:29] + node _T_1096 = and(_T_1080, _T_1084) @[package.scala 49:27] + node _T_1097 = and(_T_1083, _T_1096) @[package.scala 50:38] + node _T_1098 = or(_T_1082, _T_1097) @[package.scala 50:29] + node _T_1099 = bits(_T_1069, 0, 0) @[package.scala 44:26] + node _T_1100 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[package.scala 46:20] + node _T_1103 = and(_T_1087, _T_1102) @[package.scala 49:27] + node _T_1104 = and(_T_1099, _T_1103) @[package.scala 50:38] + node _T_1105 = or(_T_1089, _T_1104) @[package.scala 50:29] + node _T_1106 = and(_T_1087, _T_1100) @[package.scala 49:27] + node _T_1107 = and(_T_1099, _T_1106) @[package.scala 50:38] + node _T_1108 = or(_T_1089, _T_1107) @[package.scala 50:29] + node _T_1109 = and(_T_1090, _T_1102) @[package.scala 49:27] + node _T_1110 = and(_T_1099, _T_1109) @[package.scala 50:38] + node _T_1111 = or(_T_1092, _T_1110) @[package.scala 50:29] + node _T_1112 = and(_T_1090, _T_1100) @[package.scala 49:27] + node _T_1113 = and(_T_1099, _T_1112) @[package.scala 50:38] + node _T_1114 = or(_T_1092, _T_1113) @[package.scala 50:29] + node _T_1115 = and(_T_1093, _T_1102) @[package.scala 49:27] + node _T_1116 = and(_T_1099, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1095, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1093, _T_1100) @[package.scala 49:27] + node _T_1119 = and(_T_1099, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1095, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1096, _T_1102) @[package.scala 49:27] + node _T_1122 = and(_T_1099, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1098, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1096, _T_1100) @[package.scala 49:27] + node _T_1125 = and(_T_1099, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1098, _T_1125) @[package.scala 50:29] + node _T_1127 = cat(_T_1108, _T_1105) @[Cat.scala 30:58] + node _T_1128 = cat(_T_1114, _T_1111) @[Cat.scala 30:58] + node _T_1129 = cat(_T_1128, _T_1127) @[Cat.scala 30:58] + node _T_1130 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1131 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1132 = cat(_T_1131, _T_1130) @[Cat.scala 30:58] + node _T_1133 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1135 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + when _T_1135 : @[CoreplexNetwork.scala 133:10] + node _T_1137 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1138 = not(_T_1137) @[Parameters.scala 37:9] + node _T_1140 = or(_T_1138, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1141 = not(_T_1140) @[Parameters.scala 37:7] + node _T_1143 = eq(_T_1141, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1145 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1147 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1150 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1150 is invalid @[Parameters.scala 228:27] + _T_1150[0] <= _T_1143 @[Parameters.scala 228:27] + _T_1150[1] <= _T_1145 @[Parameters.scala 228:27] + _T_1150[2] <= _T_1147 @[Parameters.scala 228:27] + node _T_1158 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1160 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1161 = and(_T_1158, _T_1160) @[Parameters.scala 63:37] + node _T_1164 = mux(_T_1150[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1166 = mux(_T_1150[1], _T_1161, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1168 = mux(_T_1150[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1170 = or(_T_1164, _T_1166) @[Mux.scala 19:72] + node _T_1171 = or(_T_1170, _T_1168) @[Mux.scala 19:72] + wire _T_1173 : UInt<1> @[Mux.scala 19:72] + _T_1173 is invalid @[Mux.scala 19:72] + _T_1173 <= _T_1171 @[Mux.scala 19:72] + node _T_1174 = or(_T_1173, reset) @[CoreplexNetwork.scala 133:10] + node _T_1176 = eq(_T_1174, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1176 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1177 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1179 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1181 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1182 = or(_T_1181, reset) @[CoreplexNetwork.scala 133:10] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1184 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1185 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1187 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1189 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1190 = or(_T_1189, reset) @[CoreplexNetwork.scala 133:10] + node _T_1192 = eq(_T_1190, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1192 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1193 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 133:10] + node _T_1195 = eq(_T_1193, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1196 = or(_T_1195, reset) @[CoreplexNetwork.scala 133:10] + node _T_1198 = eq(_T_1196, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1198 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1200 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + when _T_1200 : @[CoreplexNetwork.scala 133:10] + node _T_1202 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1204 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1205 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1207 = eq(_T_1205, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1207 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1208 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1210 = eq(_T_1208, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1210 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1212 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1213 = or(_T_1212, reset) @[CoreplexNetwork.scala 133:10] + node _T_1215 = eq(_T_1213, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1215 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1216 = eq(io.in[0].b.bits.mask, _T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1217 = or(_T_1216, reset) @[CoreplexNetwork.scala 133:10] + node _T_1219 = eq(_T_1217, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1219 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1221 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1221 : @[CoreplexNetwork.scala 133:10] + node _T_1223 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1225 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1226 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1228 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1229 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1231 = eq(_T_1229, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1231 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1233 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1234 = or(_T_1233, reset) @[CoreplexNetwork.scala 133:10] + node _T_1236 = eq(_T_1234, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1236 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1237 = eq(io.in[0].b.bits.mask, _T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1238 = or(_T_1237, reset) @[CoreplexNetwork.scala 133:10] + node _T_1240 = eq(_T_1238, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1240 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1242 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 133:10] + when _T_1242 : @[CoreplexNetwork.scala 133:10] + node _T_1244 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1246 = eq(_T_1244, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1246 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1247 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1249 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1250 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1252 = eq(_T_1250, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1252 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1254 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1255 = or(_T_1254, reset) @[CoreplexNetwork.scala 133:10] + node _T_1257 = eq(_T_1255, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1257 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1258 = not(_T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1259 = and(io.in[0].b.bits.mask, _T_1258) @[CoreplexNetwork.scala 133:10] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1262 = or(_T_1261, reset) @[CoreplexNetwork.scala 133:10] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1264 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1266 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 133:10] + when _T_1266 : @[CoreplexNetwork.scala 133:10] + node _T_1268 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1270 = eq(_T_1268, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1270 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1271 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1273 = eq(_T_1271, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1273 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1274 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1276 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1278 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1279 = or(_T_1278, reset) @[CoreplexNetwork.scala 133:10] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1281 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1282 = eq(io.in[0].b.bits.mask, _T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1283 = or(_T_1282, reset) @[CoreplexNetwork.scala 133:10] + node _T_1285 = eq(_T_1283, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1285 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1287 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + when _T_1287 : @[CoreplexNetwork.scala 133:10] + node _T_1289 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1291 = eq(_T_1289, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1291 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1292 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1294 = eq(_T_1292, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1294 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1295 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1297 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1299 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1300 = or(_T_1299, reset) @[CoreplexNetwork.scala 133:10] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1302 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1303 = eq(io.in[0].b.bits.mask, _T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1304 = or(_T_1303, reset) @[CoreplexNetwork.scala 133:10] + node _T_1306 = eq(_T_1304, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1306 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1308 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 133:10] + when _T_1308 : @[CoreplexNetwork.scala 133:10] + node _T_1310 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 133:10] + node _T_1312 = eq(_T_1310, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1312 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1313 = or(_T_1057, reset) @[CoreplexNetwork.scala 133:10] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1315 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1316 = or(_T_1065, reset) @[CoreplexNetwork.scala 133:10] + node _T_1318 = eq(_T_1316, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1318 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1319 = eq(io.in[0].b.bits.mask, _T_1133) @[CoreplexNetwork.scala 133:10] + node _T_1320 = or(_T_1319, reset) @[CoreplexNetwork.scala 133:10] + node _T_1322 = eq(_T_1320, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1322 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + when io.in[0].c.valid : @[CoreplexNetwork.scala 133:10] + node _T_1324 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1325 = or(_T_1324, reset) @[CoreplexNetwork.scala 133:10] + node _T_1327 = eq(_T_1325, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1327 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1329 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1330 = not(_T_1329) @[Parameters.scala 37:9] + node _T_1332 = or(_T_1330, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1333 = not(_T_1332) @[Parameters.scala 37:7] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1337 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1339 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1342 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1342 is invalid @[Parameters.scala 228:27] + _T_1342[0] <= _T_1335 @[Parameters.scala 228:27] + _T_1342[1] <= _T_1337 @[Parameters.scala 228:27] + _T_1342[2] <= _T_1339 @[Parameters.scala 228:27] + node _T_1348 = or(_T_1342[0], _T_1342[1]) @[Parameters.scala 229:46] + node _T_1349 = or(_T_1348, _T_1342[2]) @[Parameters.scala 229:46] + node _T_1351 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1352 = dshl(_T_1351, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1353 = bits(_T_1352, 5, 0) @[package.scala 19:76] + node _T_1354 = not(_T_1353) @[package.scala 19:40] + node _T_1355 = and(io.in[0].c.bits.address, _T_1354) @[Edges.scala 17:16] + node _T_1357 = eq(_T_1355, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1359 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1360 = cvt(_T_1359) @[Parameters.scala 117:49] + node _T_1362 = and(_T_1360, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1363 = asSInt(_T_1362) @[Parameters.scala 117:52] + node _T_1365 = eq(_T_1363, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1367 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1376 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1376 is invalid @[Parameters.scala 110:36] + _T_1376[0] <= _T_1365 @[Parameters.scala 110:36] + _T_1376[1] <= _T_1373 @[Parameters.scala 110:36] + node _T_1381 = or(_T_1376[0], _T_1376[1]) @[Parameters.scala 119:64] + node _T_1383 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + when _T_1383 : @[CoreplexNetwork.scala 133:10] + node _T_1384 = or(_T_1381, reset) @[CoreplexNetwork.scala 133:10] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1386 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1387 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1389 = eq(_T_1387, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1389 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1391 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1392 = or(_T_1391, reset) @[CoreplexNetwork.scala 133:10] + node _T_1394 = eq(_T_1392, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1394 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1395 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1397 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1399 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1400 = or(_T_1399, reset) @[CoreplexNetwork.scala 133:10] + node _T_1402 = eq(_T_1400, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1402 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1404 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1405 = or(_T_1404, reset) @[CoreplexNetwork.scala 133:10] + node _T_1407 = eq(_T_1405, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1407 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1409 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 133:10] + when _T_1409 : @[CoreplexNetwork.scala 133:10] + node _T_1410 = or(_T_1381, reset) @[CoreplexNetwork.scala 133:10] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1412 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1413 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1415 = eq(_T_1413, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1415 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1417 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1418 = or(_T_1417, reset) @[CoreplexNetwork.scala 133:10] + node _T_1420 = eq(_T_1418, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1420 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1421 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1423 = eq(_T_1421, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1423 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1425 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1426 = or(_T_1425, reset) @[CoreplexNetwork.scala 133:10] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1428 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1430 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1431 = or(_T_1430, reset) @[CoreplexNetwork.scala 133:10] + node _T_1433 = eq(_T_1431, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1433 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1435 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + when _T_1435 : @[CoreplexNetwork.scala 133:10] + node _T_1438 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1440 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1441 = and(_T_1438, _T_1440) @[Parameters.scala 63:37] + node _T_1442 = or(UInt<1>("h00"), _T_1441) @[Parameters.scala 132:31] + node _T_1444 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1445 = cvt(_T_1444) @[Parameters.scala 117:49] + node _T_1447 = and(_T_1445, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1448 = asSInt(_T_1447) @[Parameters.scala 117:52] + node _T_1450 = eq(_T_1448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1452 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1453 = cvt(_T_1452) @[Parameters.scala 117:49] + node _T_1455 = and(_T_1453, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1456 = asSInt(_T_1455) @[Parameters.scala 117:52] + node _T_1458 = eq(_T_1456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1459 = or(_T_1450, _T_1458) @[Parameters.scala 133:42] + node _T_1460 = and(_T_1442, _T_1459) @[Parameters.scala 132:56] + node _T_1462 = or(UInt<1>("h00"), _T_1460) @[Parameters.scala 134:30] + node _T_1463 = or(_T_1462, reset) @[CoreplexNetwork.scala 133:10] + node _T_1465 = eq(_T_1463, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1465 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1466 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1468 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1470 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 133:10] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1473 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1474 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1476 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1478 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1479 = or(_T_1478, reset) @[CoreplexNetwork.scala 133:10] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1481 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1483 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1484 = or(_T_1483, reset) @[CoreplexNetwork.scala 133:10] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1486 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1488 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 133:10] + when _T_1488 : @[CoreplexNetwork.scala 133:10] + node _T_1491 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1493 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1494 = and(_T_1491, _T_1493) @[Parameters.scala 63:37] + node _T_1495 = or(UInt<1>("h00"), _T_1494) @[Parameters.scala 132:31] + node _T_1497 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1498 = cvt(_T_1497) @[Parameters.scala 117:49] + node _T_1500 = and(_T_1498, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1501 = asSInt(_T_1500) @[Parameters.scala 117:52] + node _T_1503 = eq(_T_1501, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1505 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1506 = cvt(_T_1505) @[Parameters.scala 117:49] + node _T_1508 = and(_T_1506, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1509 = asSInt(_T_1508) @[Parameters.scala 117:52] + node _T_1511 = eq(_T_1509, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1512 = or(_T_1503, _T_1511) @[Parameters.scala 133:42] + node _T_1513 = and(_T_1495, _T_1512) @[Parameters.scala 132:56] + node _T_1515 = or(UInt<1>("h00"), _T_1513) @[Parameters.scala 134:30] + node _T_1516 = or(_T_1515, reset) @[CoreplexNetwork.scala 133:10] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1518 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1519 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1521 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1523 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1524 = or(_T_1523, reset) @[CoreplexNetwork.scala 133:10] + node _T_1526 = eq(_T_1524, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1526 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1527 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1529 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1531 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1532 = or(_T_1531, reset) @[CoreplexNetwork.scala 133:10] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1534 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1536 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1537 = or(_T_1536, reset) @[CoreplexNetwork.scala 133:10] + node _T_1539 = eq(_T_1537, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1539 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1541 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1541 : @[CoreplexNetwork.scala 133:10] + node _T_1542 = or(_T_1381, reset) @[CoreplexNetwork.scala 133:10] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1544 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1545 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1547 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1548 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1550 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1552 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1553 = or(_T_1552, reset) @[CoreplexNetwork.scala 133:10] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1555 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1557 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 133:10] + when _T_1557 : @[CoreplexNetwork.scala 133:10] + node _T_1558 = or(_T_1381, reset) @[CoreplexNetwork.scala 133:10] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1560 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1561 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1563 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1564 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1566 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1568 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1569 = or(_T_1568, reset) @[CoreplexNetwork.scala 133:10] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1571 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1573 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 133:10] + when _T_1573 : @[CoreplexNetwork.scala 133:10] + node _T_1574 = or(_T_1381, reset) @[CoreplexNetwork.scala 133:10] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1576 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1577 = or(_T_1349, reset) @[CoreplexNetwork.scala 133:10] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1579 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1580 = or(_T_1357, reset) @[CoreplexNetwork.scala 133:10] + node _T_1582 = eq(_T_1580, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1582 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1584 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1585 = or(_T_1584, reset) @[CoreplexNetwork.scala 133:10] + node _T_1587 = eq(_T_1585, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1587 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1589 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1590 = or(_T_1589, reset) @[CoreplexNetwork.scala 133:10] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1592 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + when io.in[0].d.valid : @[CoreplexNetwork.scala 133:10] + node _T_1594 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1595 = or(_T_1594, reset) @[CoreplexNetwork.scala 133:10] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1597 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1599 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1600 = not(_T_1599) @[Parameters.scala 37:9] + node _T_1602 = or(_T_1600, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1603 = not(_T_1602) @[Parameters.scala 37:7] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1607 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1609 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1612 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1612 is invalid @[Parameters.scala 228:27] + _T_1612[0] <= _T_1605 @[Parameters.scala 228:27] + _T_1612[1] <= _T_1607 @[Parameters.scala 228:27] + _T_1612[2] <= _T_1609 @[Parameters.scala 228:27] + node _T_1618 = or(_T_1612[0], _T_1612[1]) @[Parameters.scala 229:46] + node _T_1619 = or(_T_1618, _T_1612[2]) @[Parameters.scala 229:46] + node _T_1621 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1622 = dshl(_T_1621, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1623 = bits(_T_1622, 5, 0) @[package.scala 19:76] + node _T_1624 = not(_T_1623) @[package.scala 19:40] + node _T_1625 = and(io.in[0].d.bits.addr_lo, _T_1624) @[Edges.scala 17:16] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1629 = lt(io.in[0].d.bits.sink, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + node _T_1631 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + when _T_1631 : @[CoreplexNetwork.scala 133:10] + node _T_1632 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1634 = eq(_T_1632, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1634 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1635 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1637 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1638 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1640 = eq(_T_1638, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1640 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1642 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1643 = or(_T_1642, reset) @[CoreplexNetwork.scala 133:10] + node _T_1645 = eq(_T_1643, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1645 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1647 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1648 = or(_T_1647, reset) @[CoreplexNetwork.scala 133:10] + node _T_1650 = eq(_T_1648, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1650 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1652 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1653 = or(_T_1652, reset) @[CoreplexNetwork.scala 133:10] + node _T_1655 = eq(_T_1653, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1655 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1657 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + when _T_1657 : @[CoreplexNetwork.scala 133:10] + node _T_1658 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1660 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1661 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1663 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1664 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1666 = eq(_T_1664, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1666 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1668 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1669 = or(_T_1668, reset) @[CoreplexNetwork.scala 133:10] + node _T_1671 = eq(_T_1669, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1671 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1673 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1674 = or(_T_1673, reset) @[CoreplexNetwork.scala 133:10] + node _T_1676 = eq(_T_1674, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1676 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1678 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 133:10] + when _T_1678 : @[CoreplexNetwork.scala 133:10] + node _T_1679 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1681 = eq(_T_1679, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1681 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1682 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1684 = eq(_T_1682, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1684 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1685 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1687 = eq(_T_1685, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1687 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1689 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 133:10] + node _T_1690 = or(_T_1689, reset) @[CoreplexNetwork.scala 133:10] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1692 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1694 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1695 = or(_T_1694, reset) @[CoreplexNetwork.scala 133:10] + node _T_1697 = eq(_T_1695, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1697 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1699 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1699 : @[CoreplexNetwork.scala 133:10] + node _T_1700 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1702 = eq(_T_1700, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1702 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1703 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1705 = eq(_T_1703, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1705 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1706 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1708 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1710 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1711 = or(_T_1710, reset) @[CoreplexNetwork.scala 133:10] + node _T_1713 = eq(_T_1711, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1713 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1715 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 133:10] + when _T_1715 : @[CoreplexNetwork.scala 133:10] + node _T_1716 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1718 = eq(_T_1716, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1718 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1719 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1721 = eq(_T_1719, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1721 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1722 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1724 = eq(_T_1722, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1724 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1726 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1727 = or(_T_1726, reset) @[CoreplexNetwork.scala 133:10] + node _T_1729 = eq(_T_1727, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1729 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1731 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 133:10] + when _T_1731 : @[CoreplexNetwork.scala 133:10] + node _T_1732 = or(_T_1619, reset) @[CoreplexNetwork.scala 133:10] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1734 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1735 = or(_T_1627, reset) @[CoreplexNetwork.scala 133:10] + node _T_1737 = eq(_T_1735, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1737 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1738 = or(_T_1629, reset) @[CoreplexNetwork.scala 133:10] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1740 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1742 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1743 = or(_T_1742, reset) @[CoreplexNetwork.scala 133:10] + node _T_1745 = eq(_T_1743, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1745 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1747 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1748 = or(_T_1747, reset) @[CoreplexNetwork.scala 133:10] + node _T_1750 = eq(_T_1748, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1750 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + when io.in[0].e.valid : @[CoreplexNetwork.scala 133:10] + node _T_1752 = lt(io.in[0].e.bits.sink, UInt<3>("h04")) @[CoreplexNetwork.scala 133:10] + node _T_1753 = or(_T_1752, reset) @[CoreplexNetwork.scala 133:10] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1755 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1756 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1758 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1759 = dshl(_T_1758, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1760 = bits(_T_1759, 5, 0) @[package.scala 19:76] + node _T_1761 = not(_T_1760) @[package.scala 19:40] + node _T_1762 = shr(_T_1761, 3) @[Edges.scala 198:59] + node _T_1763 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1767 = mux(_T_1765, _T_1762, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1769 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1771 = sub(_T_1769, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1772 = asUInt(_T_1771) @[Edges.scala 208:28] + node _T_1773 = tail(_T_1772, 1) @[Edges.scala 208:28] + node _T_1775 = eq(_T_1769, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1777 = eq(_T_1769, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1779 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1780 = or(_T_1777, _T_1779) @[Edges.scala 210:37] + node _T_1781 = and(_T_1780, _T_1756) @[Edges.scala 211:22] + node _T_1782 = not(_T_1773) @[Edges.scala 212:27] + node _T_1783 = and(_T_1767, _T_1782) @[Edges.scala 212:25] + when _T_1756 : @[Edges.scala 213:17] + node _T_1784 = mux(_T_1775, _T_1767, _T_1773) @[Edges.scala 214:21] + _T_1769 <= _T_1784 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1786 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1788 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1790 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1792 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1794 : UInt, clock @[CoreplexNetwork.scala 133:10] + node _T_1796 = eq(_T_1775, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1797 = and(io.in[0].a.valid, _T_1796) @[CoreplexNetwork.scala 133:10] + when _T_1797 : @[CoreplexNetwork.scala 133:10] + node _T_1798 = eq(io.in[0].a.bits.opcode, _T_1786) @[CoreplexNetwork.scala 133:10] + node _T_1799 = or(_T_1798, reset) @[CoreplexNetwork.scala 133:10] + node _T_1801 = eq(_T_1799, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1801 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1802 = eq(io.in[0].a.bits.param, _T_1788) @[CoreplexNetwork.scala 133:10] + node _T_1803 = or(_T_1802, reset) @[CoreplexNetwork.scala 133:10] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1805 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1806 = eq(io.in[0].a.bits.size, _T_1790) @[CoreplexNetwork.scala 133:10] + node _T_1807 = or(_T_1806, reset) @[CoreplexNetwork.scala 133:10] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1809 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1810 = eq(io.in[0].a.bits.source, _T_1792) @[CoreplexNetwork.scala 133:10] + node _T_1811 = or(_T_1810, reset) @[CoreplexNetwork.scala 133:10] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1813 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1814 = eq(io.in[0].a.bits.address, _T_1794) @[CoreplexNetwork.scala 133:10] + node _T_1815 = or(_T_1814, reset) @[CoreplexNetwork.scala 133:10] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1817 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1818 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1819 = and(_T_1818, _T_1775) @[CoreplexNetwork.scala 133:10] + when _T_1819 : @[CoreplexNetwork.scala 133:10] + _T_1786 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 133:10] + _T_1788 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 133:10] + _T_1790 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 133:10] + _T_1792 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 133:10] + _T_1794 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1820 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1822 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1823 = dshl(_T_1822, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1824 = bits(_T_1823, 5, 0) @[package.scala 19:76] + node _T_1825 = not(_T_1824) @[package.scala 19:40] + node _T_1826 = shr(_T_1825, 3) @[Edges.scala 198:59] + node _T_1827 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1832 = mux(UInt<1>("h00"), _T_1826, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1834 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1836 = sub(_T_1834, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1837 = asUInt(_T_1836) @[Edges.scala 208:28] + node _T_1838 = tail(_T_1837, 1) @[Edges.scala 208:28] + node _T_1840 = eq(_T_1834, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1842 = eq(_T_1834, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1844 = eq(_T_1832, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1845 = or(_T_1842, _T_1844) @[Edges.scala 210:37] + node _T_1846 = and(_T_1845, _T_1820) @[Edges.scala 211:22] + node _T_1847 = not(_T_1838) @[Edges.scala 212:27] + node _T_1848 = and(_T_1832, _T_1847) @[Edges.scala 212:25] + when _T_1820 : @[Edges.scala 213:17] + node _T_1849 = mux(_T_1840, _T_1832, _T_1838) @[Edges.scala 214:21] + _T_1834 <= _T_1849 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1851 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1853 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1855 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1857 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1859 : UInt, clock @[CoreplexNetwork.scala 133:10] + node _T_1861 = eq(_T_1840, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1862 = and(io.in[0].b.valid, _T_1861) @[CoreplexNetwork.scala 133:10] + when _T_1862 : @[CoreplexNetwork.scala 133:10] + node _T_1863 = eq(io.in[0].b.bits.opcode, _T_1851) @[CoreplexNetwork.scala 133:10] + node _T_1864 = or(_T_1863, reset) @[CoreplexNetwork.scala 133:10] + node _T_1866 = eq(_T_1864, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1866 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1867 = eq(io.in[0].b.bits.param, _T_1853) @[CoreplexNetwork.scala 133:10] + node _T_1868 = or(_T_1867, reset) @[CoreplexNetwork.scala 133:10] + node _T_1870 = eq(_T_1868, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1870 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1871 = eq(io.in[0].b.bits.size, _T_1855) @[CoreplexNetwork.scala 133:10] + node _T_1872 = or(_T_1871, reset) @[CoreplexNetwork.scala 133:10] + node _T_1874 = eq(_T_1872, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1874 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1875 = eq(io.in[0].b.bits.source, _T_1857) @[CoreplexNetwork.scala 133:10] + node _T_1876 = or(_T_1875, reset) @[CoreplexNetwork.scala 133:10] + node _T_1878 = eq(_T_1876, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1878 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1879 = eq(io.in[0].b.bits.address, _T_1859) @[CoreplexNetwork.scala 133:10] + node _T_1880 = or(_T_1879, reset) @[CoreplexNetwork.scala 133:10] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1882 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1883 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1884 = and(_T_1883, _T_1840) @[CoreplexNetwork.scala 133:10] + when _T_1884 : @[CoreplexNetwork.scala 133:10] + _T_1851 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 133:10] + _T_1853 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 133:10] + _T_1855 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 133:10] + _T_1857 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 133:10] + _T_1859 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1885 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1887 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1888 = dshl(_T_1887, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1889 = bits(_T_1888, 5, 0) @[package.scala 19:76] + node _T_1890 = not(_T_1889) @[package.scala 19:40] + node _T_1891 = shr(_T_1890, 3) @[Edges.scala 198:59] + node _T_1892 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1894 = mux(_T_1892, _T_1891, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1896 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1898 = sub(_T_1896, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1899 = asUInt(_T_1898) @[Edges.scala 208:28] + node _T_1900 = tail(_T_1899, 1) @[Edges.scala 208:28] + node _T_1902 = eq(_T_1896, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1904 = eq(_T_1896, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1906 = eq(_T_1894, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1907 = or(_T_1904, _T_1906) @[Edges.scala 210:37] + node _T_1908 = and(_T_1907, _T_1885) @[Edges.scala 211:22] + node _T_1909 = not(_T_1900) @[Edges.scala 212:27] + node _T_1910 = and(_T_1894, _T_1909) @[Edges.scala 212:25] + when _T_1885 : @[Edges.scala 213:17] + node _T_1911 = mux(_T_1902, _T_1894, _T_1900) @[Edges.scala 214:21] + _T_1896 <= _T_1911 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1913 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1915 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1917 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1919 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1921 : UInt, clock @[CoreplexNetwork.scala 133:10] + node _T_1923 = eq(_T_1902, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1924 = and(io.in[0].c.valid, _T_1923) @[CoreplexNetwork.scala 133:10] + when _T_1924 : @[CoreplexNetwork.scala 133:10] + node _T_1925 = eq(io.in[0].c.bits.opcode, _T_1913) @[CoreplexNetwork.scala 133:10] + node _T_1926 = or(_T_1925, reset) @[CoreplexNetwork.scala 133:10] + node _T_1928 = eq(_T_1926, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1928 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1929 = eq(io.in[0].c.bits.param, _T_1915) @[CoreplexNetwork.scala 133:10] + node _T_1930 = or(_T_1929, reset) @[CoreplexNetwork.scala 133:10] + node _T_1932 = eq(_T_1930, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1932 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1933 = eq(io.in[0].c.bits.size, _T_1917) @[CoreplexNetwork.scala 133:10] + node _T_1934 = or(_T_1933, reset) @[CoreplexNetwork.scala 133:10] + node _T_1936 = eq(_T_1934, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1936 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1937 = eq(io.in[0].c.bits.source, _T_1919) @[CoreplexNetwork.scala 133:10] + node _T_1938 = or(_T_1937, reset) @[CoreplexNetwork.scala 133:10] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1940 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1941 = eq(io.in[0].c.bits.address, _T_1921) @[CoreplexNetwork.scala 133:10] + node _T_1942 = or(_T_1941, reset) @[CoreplexNetwork.scala 133:10] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1944 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1945 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1946 = and(_T_1945, _T_1902) @[CoreplexNetwork.scala 133:10] + when _T_1946 : @[CoreplexNetwork.scala 133:10] + _T_1913 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 133:10] + _T_1915 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 133:10] + _T_1917 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 133:10] + _T_1919 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 133:10] + _T_1921 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1947 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1949 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1950 = dshl(_T_1949, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1951 = bits(_T_1950, 5, 0) @[package.scala 19:76] + node _T_1952 = not(_T_1951) @[package.scala 19:40] + node _T_1953 = shr(_T_1952, 3) @[Edges.scala 198:59] + node _T_1954 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1956 = mux(_T_1954, _T_1953, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1958 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1960 = sub(_T_1958, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1961 = asUInt(_T_1960) @[Edges.scala 208:28] + node _T_1962 = tail(_T_1961, 1) @[Edges.scala 208:28] + node _T_1964 = eq(_T_1958, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1966 = eq(_T_1958, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1968 = eq(_T_1956, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1969 = or(_T_1966, _T_1968) @[Edges.scala 210:37] + node _T_1970 = and(_T_1969, _T_1947) @[Edges.scala 211:22] + node _T_1971 = not(_T_1962) @[Edges.scala 212:27] + node _T_1972 = and(_T_1956, _T_1971) @[Edges.scala 212:25] + when _T_1947 : @[Edges.scala 213:17] + node _T_1973 = mux(_T_1964, _T_1956, _T_1962) @[Edges.scala 214:21] + _T_1958 <= _T_1973 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1975 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1977 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1979 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1981 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1983 : UInt, clock @[CoreplexNetwork.scala 133:10] + reg _T_1985 : UInt, clock @[CoreplexNetwork.scala 133:10] + node _T_1987 = eq(_T_1964, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_1988 = and(io.in[0].d.valid, _T_1987) @[CoreplexNetwork.scala 133:10] + when _T_1988 : @[CoreplexNetwork.scala 133:10] + node _T_1989 = eq(io.in[0].d.bits.opcode, _T_1975) @[CoreplexNetwork.scala 133:10] + node _T_1990 = or(_T_1989, reset) @[CoreplexNetwork.scala 133:10] + node _T_1992 = eq(_T_1990, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1992 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1993 = eq(io.in[0].d.bits.param, _T_1977) @[CoreplexNetwork.scala 133:10] + node _T_1994 = or(_T_1993, reset) @[CoreplexNetwork.scala 133:10] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_1996 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_1997 = eq(io.in[0].d.bits.size, _T_1979) @[CoreplexNetwork.scala 133:10] + node _T_1998 = or(_T_1997, reset) @[CoreplexNetwork.scala 133:10] + node _T_2000 = eq(_T_1998, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2000 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2001 = eq(io.in[0].d.bits.source, _T_1981) @[CoreplexNetwork.scala 133:10] + node _T_2002 = or(_T_2001, reset) @[CoreplexNetwork.scala 133:10] + node _T_2004 = eq(_T_2002, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2004 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2005 = eq(io.in[0].d.bits.sink, _T_1983) @[CoreplexNetwork.scala 133:10] + node _T_2006 = or(_T_2005, reset) @[CoreplexNetwork.scala 133:10] + node _T_2008 = eq(_T_2006, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2008 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2009 = eq(io.in[0].d.bits.addr_lo, _T_1985) @[CoreplexNetwork.scala 133:10] + node _T_2010 = or(_T_2009, reset) @[CoreplexNetwork.scala 133:10] + node _T_2012 = eq(_T_2010, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2012 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2013 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2014 = and(_T_2013, _T_1964) @[CoreplexNetwork.scala 133:10] + when _T_2014 : @[CoreplexNetwork.scala 133:10] + _T_1975 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 133:10] + _T_1977 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 133:10] + _T_1979 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 133:10] + _T_1981 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 133:10] + _T_1983 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 133:10] + _T_1985 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + reg _T_2016 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2017 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2019 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2020 = dshl(_T_2019, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2021 = bits(_T_2020, 5, 0) @[package.scala 19:76] + node _T_2022 = not(_T_2021) @[package.scala 19:40] + node _T_2023 = shr(_T_2022, 3) @[Edges.scala 198:59] + node _T_2024 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2026 = eq(_T_2024, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2028 = mux(_T_2026, _T_2023, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2030 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2032 = sub(_T_2030, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2033 = asUInt(_T_2032) @[Edges.scala 208:28] + node _T_2034 = tail(_T_2033, 1) @[Edges.scala 208:28] + node _T_2036 = eq(_T_2030, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2038 = eq(_T_2030, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2040 = eq(_T_2028, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2041 = or(_T_2038, _T_2040) @[Edges.scala 210:37] + node _T_2042 = and(_T_2041, _T_2017) @[Edges.scala 211:22] + node _T_2043 = not(_T_2034) @[Edges.scala 212:27] + node _T_2044 = and(_T_2028, _T_2043) @[Edges.scala 212:25] + when _T_2017 : @[Edges.scala 213:17] + node _T_2045 = mux(_T_2036, _T_2028, _T_2034) @[Edges.scala 214:21] + _T_2030 <= _T_2045 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2046 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2048 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_2049 = dshl(_T_2048, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2050 = bits(_T_2049, 5, 0) @[package.scala 19:76] + node _T_2051 = not(_T_2050) @[package.scala 19:40] + node _T_2052 = shr(_T_2051, 3) @[Edges.scala 198:59] + node _T_2053 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2055 = mux(_T_2053, _T_2052, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2057 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_2059 = sub(_T_2057, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2060 = asUInt(_T_2059) @[Edges.scala 208:28] + node _T_2061 = tail(_T_2060, 1) @[Edges.scala 208:28] + node _T_2063 = eq(_T_2057, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2065 = eq(_T_2057, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2067 = eq(_T_2055, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2068 = or(_T_2065, _T_2067) @[Edges.scala 210:37] + node _T_2069 = and(_T_2068, _T_2046) @[Edges.scala 211:22] + node _T_2070 = not(_T_2061) @[Edges.scala 212:27] + node _T_2071 = and(_T_2055, _T_2070) @[Edges.scala 212:25] + when _T_2046 : @[Edges.scala 213:17] + node _T_2072 = mux(_T_2063, _T_2055, _T_2061) @[Edges.scala 214:21] + _T_2057 <= _T_2072 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2074 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + node _T_2075 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 133:10] + node _T_2076 = or(_T_2074, _T_2075) @[CoreplexNetwork.scala 133:10] + node _T_2078 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_2079 = or(_T_2076, _T_2078) @[CoreplexNetwork.scala 133:10] + node _T_2081 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_2082 = or(_T_2079, _T_2081) @[CoreplexNetwork.scala 133:10] + node _T_2083 = or(_T_2082, reset) @[CoreplexNetwork.scala 133:10] + node _T_2085 = eq(_T_2083, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2085 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + wire _T_2087 : UInt<6> + _T_2087 is invalid + _T_2087 <= UInt<6>("h00") + node _T_2088 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2088 : @[CoreplexNetwork.scala 133:10] + when _T_2041 : @[CoreplexNetwork.scala 133:10] + node _T_2090 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2087 <= _T_2090 @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2091 = dshr(_T_2016, io.in[0].a.bits.source) @[CoreplexNetwork.scala 133:10] + node _T_2092 = bits(_T_2091, 0, 0) @[CoreplexNetwork.scala 133:10] + node _T_2094 = eq(_T_2092, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + node _T_2095 = or(_T_2094, reset) @[CoreplexNetwork.scala 133:10] + node _T_2097 = eq(_T_2095, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2097 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + wire _T_2099 : UInt<6> + _T_2099 is invalid + _T_2099 <= UInt<6>("h00") + node _T_2100 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2102 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 133:10] + node _T_2103 = and(_T_2100, _T_2102) @[CoreplexNetwork.scala 133:10] + when _T_2103 : @[CoreplexNetwork.scala 133:10] + when _T_2068 : @[CoreplexNetwork.scala 133:10] + node _T_2105 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2099 <= _T_2105 @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2106 = or(_T_2087, _T_2016) @[CoreplexNetwork.scala 133:10] + node _T_2107 = dshr(_T_2106, io.in[0].d.bits.source) @[CoreplexNetwork.scala 133:10] + node _T_2108 = bits(_T_2107, 0, 0) @[CoreplexNetwork.scala 133:10] + node _T_2109 = or(_T_2108, reset) @[CoreplexNetwork.scala 133:10] + node _T_2111 = eq(_T_2109, UInt<1>("h00")) @[CoreplexNetwork.scala 133:10] + when _T_2111 : @[CoreplexNetwork.scala 133:10] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:133:10)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 133:10] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + skip @[CoreplexNetwork.scala 133:10] + node _T_2112 = or(_T_2016, _T_2087) @[CoreplexNetwork.scala 133:10] + node _T_2113 = not(_T_2099) @[CoreplexNetwork.scala 133:10] + node _T_2114 = and(_T_2112, _T_2113) @[CoreplexNetwork.scala 133:10] + _T_2016 <= _T_2114 @[CoreplexNetwork.scala 133:10] + + module TLFilter_mem_0 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + io.out <- io.in @[Filter.scala 42:12] + + module TLMonitor_23 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 134:68] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[CoreplexNetwork.scala 134:68] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_608 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + when _T_700 : @[CoreplexNetwork.scala 134:68] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = or(_T_711, _T_719) @[Parameters.scala 133:42] + node _T_721 = and(_T_703, _T_720) @[Parameters.scala 132:56] + node _T_723 = or(UInt<1>("h00"), _T_721) @[Parameters.scala 134:30] + node _T_724 = or(_T_723, reset) @[CoreplexNetwork.scala 134:68] + node _T_726 = eq(_T_724, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_726 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_727 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_729 = eq(_T_727, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_729 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_731 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_732 = or(_T_731, reset) @[CoreplexNetwork.scala 134:68] + node _T_734 = eq(_T_732, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_734 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_735 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_737 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_739 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_740 = or(_T_739, reset) @[CoreplexNetwork.scala 134:68] + node _T_742 = eq(_T_740, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_742 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_743 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 134:68] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_746 = or(_T_745, reset) @[CoreplexNetwork.scala 134:68] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_748 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_750 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:68] + when _T_750 : @[CoreplexNetwork.scala 134:68] + node _T_753 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_755 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_756 = and(_T_753, _T_755) @[Parameters.scala 63:37] + node _T_757 = or(UInt<1>("h00"), _T_756) @[Parameters.scala 132:31] + node _T_759 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_760 = cvt(_T_759) @[Parameters.scala 117:49] + node _T_762 = and(_T_760, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_763 = asSInt(_T_762) @[Parameters.scala 117:52] + node _T_765 = eq(_T_763, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_766 = and(_T_757, _T_765) @[Parameters.scala 132:56] + node _T_769 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_771 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_772 = and(_T_769, _T_771) @[Parameters.scala 63:37] + node _T_773 = or(UInt<1>("h00"), _T_772) @[Parameters.scala 132:31] + node _T_775 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_776 = cvt(_T_775) @[Parameters.scala 117:49] + node _T_778 = and(_T_776, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_779 = asSInt(_T_778) @[Parameters.scala 117:52] + node _T_781 = eq(_T_779, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_782 = and(_T_773, _T_781) @[Parameters.scala 132:56] + node _T_784 = or(UInt<1>("h00"), _T_766) @[Parameters.scala 134:30] + node _T_785 = or(_T_784, _T_782) @[Parameters.scala 134:30] + node _T_786 = or(_T_785, reset) @[CoreplexNetwork.scala 134:68] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_788 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_789 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_791 = eq(_T_789, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_791 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_792 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_794 = eq(_T_792, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_794 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_796 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_797 = or(_T_796, reset) @[CoreplexNetwork.scala 134:68] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_799 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_800 = eq(io.in[0].a.bits.mask, _T_698) @[CoreplexNetwork.scala 134:68] + node _T_801 = or(_T_800, reset) @[CoreplexNetwork.scala 134:68] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_803 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_805 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_805 : @[CoreplexNetwork.scala 134:68] + node _T_808 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_810 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_811 = and(_T_808, _T_810) @[Parameters.scala 63:37] + node _T_812 = or(UInt<1>("h00"), _T_811) @[Parameters.scala 132:31] + node _T_814 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_815 = cvt(_T_814) @[Parameters.scala 117:49] + node _T_817 = and(_T_815, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_818 = asSInt(_T_817) @[Parameters.scala 117:52] + node _T_820 = eq(_T_818, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_821 = and(_T_812, _T_820) @[Parameters.scala 132:56] + node _T_824 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_826 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_827 = and(_T_824, _T_826) @[Parameters.scala 63:37] + node _T_828 = or(UInt<1>("h00"), _T_827) @[Parameters.scala 132:31] + node _T_830 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_831 = cvt(_T_830) @[Parameters.scala 117:49] + node _T_833 = and(_T_831, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_834 = asSInt(_T_833) @[Parameters.scala 117:52] + node _T_836 = eq(_T_834, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_837 = and(_T_828, _T_836) @[Parameters.scala 132:56] + node _T_839 = or(UInt<1>("h00"), _T_821) @[Parameters.scala 134:30] + node _T_840 = or(_T_839, _T_837) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[CoreplexNetwork.scala 134:68] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_843 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_844 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_846 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_847 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_849 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_851 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_852 = or(_T_851, reset) @[CoreplexNetwork.scala 134:68] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_854 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_855 = eq(io.in[0].a.bits.mask, _T_698) @[CoreplexNetwork.scala 134:68] + node _T_856 = or(_T_855, reset) @[CoreplexNetwork.scala 134:68] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_858 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:68] + when _T_860 : @[CoreplexNetwork.scala 134:68] + node _T_863 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_865 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_866 = and(_T_863, _T_865) @[Parameters.scala 63:37] + node _T_867 = or(UInt<1>("h00"), _T_866) @[Parameters.scala 132:31] + node _T_869 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_870 = cvt(_T_869) @[Parameters.scala 117:49] + node _T_872 = and(_T_870, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_873 = asSInt(_T_872) @[Parameters.scala 117:52] + node _T_875 = eq(_T_873, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_876 = and(_T_867, _T_875) @[Parameters.scala 132:56] + node _T_879 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_881 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_882 = and(_T_879, _T_881) @[Parameters.scala 63:37] + node _T_883 = or(UInt<1>("h00"), _T_882) @[Parameters.scala 132:31] + node _T_885 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_892 = and(_T_883, _T_891) @[Parameters.scala 132:56] + node _T_894 = or(UInt<1>("h00"), _T_876) @[Parameters.scala 134:30] + node _T_895 = or(_T_894, _T_892) @[Parameters.scala 134:30] + node _T_896 = or(_T_895, reset) @[CoreplexNetwork.scala 134:68] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_898 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_899 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_901 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_902 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_904 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_906 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_907 = or(_T_906, reset) @[CoreplexNetwork.scala 134:68] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_909 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_910 = not(_T_698) @[CoreplexNetwork.scala 134:68] + node _T_911 = and(io.in[0].a.bits.mask, _T_910) @[CoreplexNetwork.scala 134:68] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_914 = or(_T_913, reset) @[CoreplexNetwork.scala 134:68] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_916 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_918 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + when _T_918 : @[CoreplexNetwork.scala 134:68] + node _T_921 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_923 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_924 = cvt(_T_923) @[Parameters.scala 117:49] + node _T_926 = and(_T_924, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_927 = asSInt(_T_926) @[Parameters.scala 117:52] + node _T_929 = eq(_T_927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = or(_T_929, _T_937) @[Parameters.scala 133:42] + node _T_939 = and(_T_921, _T_938) @[Parameters.scala 132:56] + node _T_941 = or(UInt<1>("h00"), _T_939) @[Parameters.scala 134:30] + node _T_942 = or(_T_941, reset) @[CoreplexNetwork.scala 134:68] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_944 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_945 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_947 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_948 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_950 = eq(_T_948, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_950 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_952 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_953 = or(_T_952, reset) @[CoreplexNetwork.scala 134:68] + node _T_955 = eq(_T_953, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_955 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_956 = eq(io.in[0].a.bits.mask, _T_698) @[CoreplexNetwork.scala 134:68] + node _T_957 = or(_T_956, reset) @[CoreplexNetwork.scala 134:68] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_959 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_961 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + when _T_961 : @[CoreplexNetwork.scala 134:68] + node _T_964 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_966 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_967 = cvt(_T_966) @[Parameters.scala 117:49] + node _T_969 = and(_T_967, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_970 = asSInt(_T_969) @[Parameters.scala 117:52] + node _T_972 = eq(_T_970, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_975 = cvt(_T_974) @[Parameters.scala 117:49] + node _T_977 = and(_T_975, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_978 = asSInt(_T_977) @[Parameters.scala 117:52] + node _T_980 = eq(_T_978, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = or(_T_972, _T_980) @[Parameters.scala 133:42] + node _T_982 = and(_T_964, _T_981) @[Parameters.scala 132:56] + node _T_984 = or(UInt<1>("h00"), _T_982) @[Parameters.scala 134:30] + node _T_985 = or(_T_984, reset) @[CoreplexNetwork.scala 134:68] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_987 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_988 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_990 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_991 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_993 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_995 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_996 = or(_T_995, reset) @[CoreplexNetwork.scala 134:68] + node _T_998 = eq(_T_996, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_998 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_999 = eq(io.in[0].a.bits.mask, _T_698) @[CoreplexNetwork.scala 134:68] + node _T_1000 = or(_T_999, reset) @[CoreplexNetwork.scala 134:68] + node _T_1002 = eq(_T_1000, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1002 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1004 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:68] + when _T_1004 : @[CoreplexNetwork.scala 134:68] + node _T_1007 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1009 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1010 = cvt(_T_1009) @[Parameters.scala 117:49] + node _T_1012 = and(_T_1010, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1013 = asSInt(_T_1012) @[Parameters.scala 117:52] + node _T_1015 = eq(_T_1013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1018 = cvt(_T_1017) @[Parameters.scala 117:49] + node _T_1020 = and(_T_1018, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1021 = asSInt(_T_1020) @[Parameters.scala 117:52] + node _T_1023 = eq(_T_1021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = or(_T_1015, _T_1023) @[Parameters.scala 133:42] + node _T_1025 = and(_T_1007, _T_1024) @[Parameters.scala 132:56] + node _T_1027 = or(UInt<1>("h00"), _T_1025) @[Parameters.scala 134:30] + node _T_1028 = or(_T_1027, reset) @[CoreplexNetwork.scala 134:68] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1030 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1031 = or(_T_619[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1033 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1034 = or(_T_630, reset) @[CoreplexNetwork.scala 134:68] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1036 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_698) @[CoreplexNetwork.scala 134:68] + node _T_1038 = or(_T_1037, reset) @[CoreplexNetwork.scala 134:68] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1040 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + when io.in[0].b.valid : @[CoreplexNetwork.scala 134:68] + node _T_1042 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1043 = or(_T_1042, reset) @[CoreplexNetwork.scala 134:68] + node _T_1045 = eq(_T_1043, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1045 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1047 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1064 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1064 is invalid @[Parameters.scala 110:36] + _T_1064[0] <= _T_1053 @[Parameters.scala 110:36] + _T_1064[1] <= _T_1061 @[Parameters.scala 110:36] + node _T_1069 = or(_T_1064[0], _T_1064[1]) @[Parameters.scala 119:64] + node _T_1071 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1072 = dshl(_T_1071, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1073 = bits(_T_1072, 7, 0) @[package.scala 19:76] + node _T_1074 = not(_T_1073) @[package.scala 19:40] + node _T_1075 = and(io.in[0].b.bits.address, _T_1074) @[Edges.scala 17:16] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1079 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1080 = dshl(UInt<1>("h01"), _T_1079) @[OneHot.scala 49:12] + node _T_1081 = bits(_T_1080, 2, 0) @[OneHot.scala 49:37] + node _T_1083 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1085 = bits(_T_1081, 2, 2) @[package.scala 44:26] + node _T_1086 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[package.scala 46:20] + node _T_1089 = and(UInt<1>("h01"), _T_1088) @[package.scala 49:27] + node _T_1090 = and(_T_1085, _T_1089) @[package.scala 50:38] + node _T_1091 = or(_T_1083, _T_1090) @[package.scala 50:29] + node _T_1092 = and(UInt<1>("h01"), _T_1086) @[package.scala 49:27] + node _T_1093 = and(_T_1085, _T_1092) @[package.scala 50:38] + node _T_1094 = or(_T_1083, _T_1093) @[package.scala 50:29] + node _T_1095 = bits(_T_1081, 1, 1) @[package.scala 44:26] + node _T_1096 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1098 = eq(_T_1096, UInt<1>("h00")) @[package.scala 46:20] + node _T_1099 = and(_T_1089, _T_1098) @[package.scala 49:27] + node _T_1100 = and(_T_1095, _T_1099) @[package.scala 50:38] + node _T_1101 = or(_T_1091, _T_1100) @[package.scala 50:29] + node _T_1102 = and(_T_1089, _T_1096) @[package.scala 49:27] + node _T_1103 = and(_T_1095, _T_1102) @[package.scala 50:38] + node _T_1104 = or(_T_1091, _T_1103) @[package.scala 50:29] + node _T_1105 = and(_T_1092, _T_1098) @[package.scala 49:27] + node _T_1106 = and(_T_1095, _T_1105) @[package.scala 50:38] + node _T_1107 = or(_T_1094, _T_1106) @[package.scala 50:29] + node _T_1108 = and(_T_1092, _T_1096) @[package.scala 49:27] + node _T_1109 = and(_T_1095, _T_1108) @[package.scala 50:38] + node _T_1110 = or(_T_1094, _T_1109) @[package.scala 50:29] + node _T_1111 = bits(_T_1081, 0, 0) @[package.scala 44:26] + node _T_1112 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[package.scala 46:20] + node _T_1115 = and(_T_1099, _T_1114) @[package.scala 49:27] + node _T_1116 = and(_T_1111, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1101, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1099, _T_1112) @[package.scala 49:27] + node _T_1119 = and(_T_1111, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1101, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1102, _T_1114) @[package.scala 49:27] + node _T_1122 = and(_T_1111, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1104, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1102, _T_1112) @[package.scala 49:27] + node _T_1125 = and(_T_1111, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1104, _T_1125) @[package.scala 50:29] + node _T_1127 = and(_T_1105, _T_1114) @[package.scala 49:27] + node _T_1128 = and(_T_1111, _T_1127) @[package.scala 50:38] + node _T_1129 = or(_T_1107, _T_1128) @[package.scala 50:29] + node _T_1130 = and(_T_1105, _T_1112) @[package.scala 49:27] + node _T_1131 = and(_T_1111, _T_1130) @[package.scala 50:38] + node _T_1132 = or(_T_1107, _T_1131) @[package.scala 50:29] + node _T_1133 = and(_T_1108, _T_1114) @[package.scala 49:27] + node _T_1134 = and(_T_1111, _T_1133) @[package.scala 50:38] + node _T_1135 = or(_T_1110, _T_1134) @[package.scala 50:29] + node _T_1136 = and(_T_1108, _T_1112) @[package.scala 49:27] + node _T_1137 = and(_T_1111, _T_1136) @[package.scala 50:38] + node _T_1138 = or(_T_1110, _T_1137) @[package.scala 50:29] + node _T_1139 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + when _T_1147 : @[CoreplexNetwork.scala 134:68] + node _T_1149 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1151 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1152 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1154 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1156 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1157 = or(_T_1156, reset) @[CoreplexNetwork.scala 134:68] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1159 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1160 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1162 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1164 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1165 = or(_T_1164, reset) @[CoreplexNetwork.scala 134:68] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1167 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1168 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 134:68] + node _T_1170 = eq(_T_1168, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1171 = or(_T_1170, reset) @[CoreplexNetwork.scala 134:68] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1173 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1175 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:68] + when _T_1175 : @[CoreplexNetwork.scala 134:68] + node _T_1177 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1179 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1180 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1182 = eq(_T_1180, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1182 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1183 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1185 = eq(_T_1183, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1185 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1187 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1188 = or(_T_1187, reset) @[CoreplexNetwork.scala 134:68] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1190 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1191 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1192 = or(_T_1191, reset) @[CoreplexNetwork.scala 134:68] + node _T_1194 = eq(_T_1192, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1194 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1196 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1196 : @[CoreplexNetwork.scala 134:68] + node _T_1198 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1200 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1201 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1203 = eq(_T_1201, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1203 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1204 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1206 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1208 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1209 = or(_T_1208, reset) @[CoreplexNetwork.scala 134:68] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1211 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1212 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1213 = or(_T_1212, reset) @[CoreplexNetwork.scala 134:68] + node _T_1215 = eq(_T_1213, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1215 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1217 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:68] + when _T_1217 : @[CoreplexNetwork.scala 134:68] + node _T_1219 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1221 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1222 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1224 = eq(_T_1222, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1224 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1225 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1227 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1229 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1230 = or(_T_1229, reset) @[CoreplexNetwork.scala 134:68] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1232 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1233 = not(_T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1234 = and(io.in[0].b.bits.mask, _T_1233) @[CoreplexNetwork.scala 134:68] + node _T_1236 = eq(_T_1234, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1237 = or(_T_1236, reset) @[CoreplexNetwork.scala 134:68] + node _T_1239 = eq(_T_1237, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1239 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1241 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + when _T_1241 : @[CoreplexNetwork.scala 134:68] + node _T_1243 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1245 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1246 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1248 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1249 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1251 = eq(_T_1249, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1251 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1253 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1254 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:68] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1256 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1257 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1258 = or(_T_1257, reset) @[CoreplexNetwork.scala 134:68] + node _T_1260 = eq(_T_1258, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1260 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1262 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + when _T_1262 : @[CoreplexNetwork.scala 134:68] + node _T_1264 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1266 = eq(_T_1264, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1266 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1267 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1269 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1270 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1272 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1274 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1275 = or(_T_1274, reset) @[CoreplexNetwork.scala 134:68] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1277 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1278 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1279 = or(_T_1278, reset) @[CoreplexNetwork.scala 134:68] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1281 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1283 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:68] + when _T_1283 : @[CoreplexNetwork.scala 134:68] + node _T_1285 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:68] + node _T_1287 = eq(_T_1285, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1287 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1288 = or(_T_1069, reset) @[CoreplexNetwork.scala 134:68] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1290 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1291 = or(_T_1077, reset) @[CoreplexNetwork.scala 134:68] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1293 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1294 = eq(io.in[0].b.bits.mask, _T_1145) @[CoreplexNetwork.scala 134:68] + node _T_1295 = or(_T_1294, reset) @[CoreplexNetwork.scala 134:68] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1297 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + when io.in[0].c.valid : @[CoreplexNetwork.scala 134:68] + node _T_1299 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1300 = or(_T_1299, reset) @[CoreplexNetwork.scala 134:68] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1302 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1304 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1305 = not(_T_1304) @[Parameters.scala 37:9] + node _T_1307 = or(_T_1305, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1308 = not(_T_1307) @[Parameters.scala 37:7] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1313 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1313 is invalid @[Parameters.scala 228:27] + _T_1313[0] <= _T_1310 @[Parameters.scala 228:27] + node _T_1318 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1319 = dshl(_T_1318, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1320 = bits(_T_1319, 7, 0) @[package.scala 19:76] + node _T_1321 = not(_T_1320) @[package.scala 19:40] + node _T_1322 = and(io.in[0].c.bits.address, _T_1321) @[Edges.scala 17:16] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1326 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1327 = cvt(_T_1326) @[Parameters.scala 117:49] + node _T_1329 = and(_T_1327, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1330 = asSInt(_T_1329) @[Parameters.scala 117:52] + node _T_1332 = eq(_T_1330, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1334 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1335 = cvt(_T_1334) @[Parameters.scala 117:49] + node _T_1337 = and(_T_1335, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1338 = asSInt(_T_1337) @[Parameters.scala 117:52] + node _T_1340 = eq(_T_1338, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1343 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1343 is invalid @[Parameters.scala 110:36] + _T_1343[0] <= _T_1332 @[Parameters.scala 110:36] + _T_1343[1] <= _T_1340 @[Parameters.scala 110:36] + node _T_1348 = or(_T_1343[0], _T_1343[1]) @[Parameters.scala 119:64] + node _T_1350 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:68] + when _T_1350 : @[CoreplexNetwork.scala 134:68] + node _T_1351 = or(_T_1348, reset) @[CoreplexNetwork.scala 134:68] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1353 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1354 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1356 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1358 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1359 = or(_T_1358, reset) @[CoreplexNetwork.scala 134:68] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1361 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1362 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1364 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1366 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1367 = or(_T_1366, reset) @[CoreplexNetwork.scala 134:68] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1369 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1371 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1372 = or(_T_1371, reset) @[CoreplexNetwork.scala 134:68] + node _T_1374 = eq(_T_1372, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1374 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1376 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:68] + when _T_1376 : @[CoreplexNetwork.scala 134:68] + node _T_1377 = or(_T_1348, reset) @[CoreplexNetwork.scala 134:68] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1379 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1380 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1382 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1384 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1385 = or(_T_1384, reset) @[CoreplexNetwork.scala 134:68] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1387 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1388 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1390 = eq(_T_1388, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1390 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1392 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1393 = or(_T_1392, reset) @[CoreplexNetwork.scala 134:68] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1395 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1397 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1398 = or(_T_1397, reset) @[CoreplexNetwork.scala 134:68] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1400 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1402 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + when _T_1402 : @[CoreplexNetwork.scala 134:68] + node _T_1405 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1407 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1422 = or(_T_1413, _T_1421) @[Parameters.scala 133:42] + node _T_1423 = and(_T_1405, _T_1422) @[Parameters.scala 132:56] + node _T_1425 = or(UInt<1>("h00"), _T_1423) @[Parameters.scala 134:30] + node _T_1426 = or(_T_1425, reset) @[CoreplexNetwork.scala 134:68] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1428 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1429 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1431 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1433 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1434 = or(_T_1433, reset) @[CoreplexNetwork.scala 134:68] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1436 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1437 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1439 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1441 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1442 = or(_T_1441, reset) @[CoreplexNetwork.scala 134:68] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1444 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1446 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1447 = or(_T_1446, reset) @[CoreplexNetwork.scala 134:68] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1449 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1451 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 134:68] + when _T_1451 : @[CoreplexNetwork.scala 134:68] + node _T_1454 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1456 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1457 = cvt(_T_1456) @[Parameters.scala 117:49] + node _T_1459 = and(_T_1457, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1460 = asSInt(_T_1459) @[Parameters.scala 117:52] + node _T_1462 = eq(_T_1460, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1464 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1465 = cvt(_T_1464) @[Parameters.scala 117:49] + node _T_1467 = and(_T_1465, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1468 = asSInt(_T_1467) @[Parameters.scala 117:52] + node _T_1470 = eq(_T_1468, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1471 = or(_T_1462, _T_1470) @[Parameters.scala 133:42] + node _T_1472 = and(_T_1454, _T_1471) @[Parameters.scala 132:56] + node _T_1474 = or(UInt<1>("h00"), _T_1472) @[Parameters.scala 134:30] + node _T_1475 = or(_T_1474, reset) @[CoreplexNetwork.scala 134:68] + node _T_1477 = eq(_T_1475, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1477 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1478 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1480 = eq(_T_1478, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1480 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1482 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1483 = or(_T_1482, reset) @[CoreplexNetwork.scala 134:68] + node _T_1485 = eq(_T_1483, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1485 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1486 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1488 = eq(_T_1486, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1488 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1490 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1491 = or(_T_1490, reset) @[CoreplexNetwork.scala 134:68] + node _T_1493 = eq(_T_1491, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1493 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1495 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1496 = or(_T_1495, reset) @[CoreplexNetwork.scala 134:68] + node _T_1498 = eq(_T_1496, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1498 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1500 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1500 : @[CoreplexNetwork.scala 134:68] + node _T_1501 = or(_T_1348, reset) @[CoreplexNetwork.scala 134:68] + node _T_1503 = eq(_T_1501, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1503 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1504 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1506 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1507 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1509 = eq(_T_1507, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1509 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1511 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1512 = or(_T_1511, reset) @[CoreplexNetwork.scala 134:68] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1514 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1516 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:68] + when _T_1516 : @[CoreplexNetwork.scala 134:68] + node _T_1517 = or(_T_1348, reset) @[CoreplexNetwork.scala 134:68] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1519 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1520 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1522 = eq(_T_1520, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1522 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1523 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1525 = eq(_T_1523, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1525 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1527 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1528 = or(_T_1527, reset) @[CoreplexNetwork.scala 134:68] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1530 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1532 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + when _T_1532 : @[CoreplexNetwork.scala 134:68] + node _T_1533 = or(_T_1348, reset) @[CoreplexNetwork.scala 134:68] + node _T_1535 = eq(_T_1533, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1535 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1536 = or(_T_1313[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1538 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1539 = or(_T_1324, reset) @[CoreplexNetwork.scala 134:68] + node _T_1541 = eq(_T_1539, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1541 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1543 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1544 = or(_T_1543, reset) @[CoreplexNetwork.scala 134:68] + node _T_1546 = eq(_T_1544, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1546 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1548 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1549 = or(_T_1548, reset) @[CoreplexNetwork.scala 134:68] + node _T_1551 = eq(_T_1549, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1551 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + when io.in[0].d.valid : @[CoreplexNetwork.scala 134:68] + node _T_1553 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1554 = or(_T_1553, reset) @[CoreplexNetwork.scala 134:68] + node _T_1556 = eq(_T_1554, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1556 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1558 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1559 = not(_T_1558) @[Parameters.scala 37:9] + node _T_1561 = or(_T_1559, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1562 = not(_T_1561) @[Parameters.scala 37:7] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1567 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1567 is invalid @[Parameters.scala 228:27] + _T_1567[0] <= _T_1564 @[Parameters.scala 228:27] + node _T_1572 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1573 = dshl(_T_1572, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1574 = bits(_T_1573, 7, 0) @[package.scala 19:76] + node _T_1575 = not(_T_1574) @[package.scala 19:40] + node _T_1576 = and(io.in[0].d.bits.addr_lo, _T_1575) @[Edges.scala 17:16] + node _T_1578 = eq(_T_1576, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1580 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + node _T_1582 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + when _T_1582 : @[CoreplexNetwork.scala 134:68] + node _T_1583 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1585 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1586 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1588 = eq(_T_1586, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1588 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1589 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1591 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1593 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1594 = or(_T_1593, reset) @[CoreplexNetwork.scala 134:68] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1596 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1598 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1599 = or(_T_1598, reset) @[CoreplexNetwork.scala 134:68] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1601 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1603 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1604 = or(_T_1603, reset) @[CoreplexNetwork.scala 134:68] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1606 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1608 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:68] + when _T_1608 : @[CoreplexNetwork.scala 134:68] + node _T_1609 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1611 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1612 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1614 = eq(_T_1612, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1614 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1615 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1617 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1619 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1620 = or(_T_1619, reset) @[CoreplexNetwork.scala 134:68] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1622 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1624 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1625 = or(_T_1624, reset) @[CoreplexNetwork.scala 134:68] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1627 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1629 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:68] + when _T_1629 : @[CoreplexNetwork.scala 134:68] + node _T_1630 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1632 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1633 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1635 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1636 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1638 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1640 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:68] + node _T_1641 = or(_T_1640, reset) @[CoreplexNetwork.scala 134:68] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1643 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1645 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1646 = or(_T_1645, reset) @[CoreplexNetwork.scala 134:68] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1648 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1650 : @[CoreplexNetwork.scala 134:68] + node _T_1651 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1653 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1654 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1656 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1657 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1659 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1662 = or(_T_1661, reset) @[CoreplexNetwork.scala 134:68] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1664 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:68] + when _T_1666 : @[CoreplexNetwork.scala 134:68] + node _T_1667 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1669 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1670 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1672 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1673 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1675 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1678 = or(_T_1677, reset) @[CoreplexNetwork.scala 134:68] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1680 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1682 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + when _T_1682 : @[CoreplexNetwork.scala 134:68] + node _T_1683 = or(_T_1567[0], reset) @[CoreplexNetwork.scala 134:68] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1685 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1686 = or(_T_1578, reset) @[CoreplexNetwork.scala 134:68] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1688 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1689 = or(_T_1580, reset) @[CoreplexNetwork.scala 134:68] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1691 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1693 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1694 = or(_T_1693, reset) @[CoreplexNetwork.scala 134:68] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1696 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1698 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1699 = or(_T_1698, reset) @[CoreplexNetwork.scala 134:68] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1701 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + when io.in[0].e.valid : @[CoreplexNetwork.scala 134:68] + node _T_1703 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 134:68] + node _T_1704 = or(_T_1703, reset) @[CoreplexNetwork.scala 134:68] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1706 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1707 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 7, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1718 = mux(_T_1716, _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1720 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1722 = sub(_T_1720, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1723 = asUInt(_T_1722) @[Edges.scala 208:28] + node _T_1724 = tail(_T_1723, 1) @[Edges.scala 208:28] + node _T_1726 = eq(_T_1720, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1728 = eq(_T_1720, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1730 = eq(_T_1718, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1731 = or(_T_1728, _T_1730) @[Edges.scala 210:37] + node _T_1732 = and(_T_1731, _T_1707) @[Edges.scala 211:22] + node _T_1733 = not(_T_1724) @[Edges.scala 212:27] + node _T_1734 = and(_T_1718, _T_1733) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1735 = mux(_T_1726, _T_1718, _T_1724) @[Edges.scala 214:21] + _T_1720 <= _T_1735 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1737 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1739 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1741 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1743 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1745 : UInt, clock @[CoreplexNetwork.scala 134:68] + node _T_1747 = eq(_T_1726, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1748 = and(io.in[0].a.valid, _T_1747) @[CoreplexNetwork.scala 134:68] + when _T_1748 : @[CoreplexNetwork.scala 134:68] + node _T_1749 = eq(io.in[0].a.bits.opcode, _T_1737) @[CoreplexNetwork.scala 134:68] + node _T_1750 = or(_T_1749, reset) @[CoreplexNetwork.scala 134:68] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1752 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1753 = eq(io.in[0].a.bits.param, _T_1739) @[CoreplexNetwork.scala 134:68] + node _T_1754 = or(_T_1753, reset) @[CoreplexNetwork.scala 134:68] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1756 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1757 = eq(io.in[0].a.bits.size, _T_1741) @[CoreplexNetwork.scala 134:68] + node _T_1758 = or(_T_1757, reset) @[CoreplexNetwork.scala 134:68] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1760 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1761 = eq(io.in[0].a.bits.source, _T_1743) @[CoreplexNetwork.scala 134:68] + node _T_1762 = or(_T_1761, reset) @[CoreplexNetwork.scala 134:68] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1764 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1765 = eq(io.in[0].a.bits.address, _T_1745) @[CoreplexNetwork.scala 134:68] + node _T_1766 = or(_T_1765, reset) @[CoreplexNetwork.scala 134:68] + node _T_1768 = eq(_T_1766, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1768 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1769 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1770 = and(_T_1769, _T_1726) @[CoreplexNetwork.scala 134:68] + when _T_1770 : @[CoreplexNetwork.scala 134:68] + _T_1737 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 134:68] + _T_1739 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 134:68] + _T_1741 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 134:68] + _T_1743 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 134:68] + _T_1745 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1771 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1773 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1774 = dshl(_T_1773, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1775 = bits(_T_1774, 7, 0) @[package.scala 19:76] + node _T_1776 = not(_T_1775) @[package.scala 19:40] + node _T_1777 = shr(_T_1776, 3) @[Edges.scala 198:59] + node _T_1778 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1780 = eq(_T_1778, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1783 = mux(UInt<1>("h00"), _T_1777, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1771) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1771 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1804 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1806 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1808 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1810 : UInt, clock @[CoreplexNetwork.scala 134:68] + node _T_1812 = eq(_T_1791, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1813 = and(io.in[0].b.valid, _T_1812) @[CoreplexNetwork.scala 134:68] + when _T_1813 : @[CoreplexNetwork.scala 134:68] + node _T_1814 = eq(io.in[0].b.bits.opcode, _T_1802) @[CoreplexNetwork.scala 134:68] + node _T_1815 = or(_T_1814, reset) @[CoreplexNetwork.scala 134:68] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1817 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1818 = eq(io.in[0].b.bits.param, _T_1804) @[CoreplexNetwork.scala 134:68] + node _T_1819 = or(_T_1818, reset) @[CoreplexNetwork.scala 134:68] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1821 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1822 = eq(io.in[0].b.bits.size, _T_1806) @[CoreplexNetwork.scala 134:68] + node _T_1823 = or(_T_1822, reset) @[CoreplexNetwork.scala 134:68] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1825 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1826 = eq(io.in[0].b.bits.source, _T_1808) @[CoreplexNetwork.scala 134:68] + node _T_1827 = or(_T_1826, reset) @[CoreplexNetwork.scala 134:68] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1829 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1830 = eq(io.in[0].b.bits.address, _T_1810) @[CoreplexNetwork.scala 134:68] + node _T_1831 = or(_T_1830, reset) @[CoreplexNetwork.scala 134:68] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1833 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1834 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1835 = and(_T_1834, _T_1791) @[CoreplexNetwork.scala 134:68] + when _T_1835 : @[CoreplexNetwork.scala 134:68] + _T_1802 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 134:68] + _T_1804 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 134:68] + _T_1806 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 134:68] + _T_1808 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 134:68] + _T_1810 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1836 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1838 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1839 = dshl(_T_1838, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1840 = bits(_T_1839, 7, 0) @[package.scala 19:76] + node _T_1841 = not(_T_1840) @[package.scala 19:40] + node _T_1842 = shr(_T_1841, 3) @[Edges.scala 198:59] + node _T_1843 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1846 = mux(UInt<1>("h00"), _T_1842, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1836) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1836 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1865 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1867 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1869 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1871 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1873 : UInt, clock @[CoreplexNetwork.scala 134:68] + node _T_1875 = eq(_T_1854, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1876 = and(io.in[0].c.valid, _T_1875) @[CoreplexNetwork.scala 134:68] + when _T_1876 : @[CoreplexNetwork.scala 134:68] + node _T_1877 = eq(io.in[0].c.bits.opcode, _T_1865) @[CoreplexNetwork.scala 134:68] + node _T_1878 = or(_T_1877, reset) @[CoreplexNetwork.scala 134:68] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1880 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1881 = eq(io.in[0].c.bits.param, _T_1867) @[CoreplexNetwork.scala 134:68] + node _T_1882 = or(_T_1881, reset) @[CoreplexNetwork.scala 134:68] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1884 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1885 = eq(io.in[0].c.bits.size, _T_1869) @[CoreplexNetwork.scala 134:68] + node _T_1886 = or(_T_1885, reset) @[CoreplexNetwork.scala 134:68] + node _T_1888 = eq(_T_1886, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1888 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1889 = eq(io.in[0].c.bits.source, _T_1871) @[CoreplexNetwork.scala 134:68] + node _T_1890 = or(_T_1889, reset) @[CoreplexNetwork.scala 134:68] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1892 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1893 = eq(io.in[0].c.bits.address, _T_1873) @[CoreplexNetwork.scala 134:68] + node _T_1894 = or(_T_1893, reset) @[CoreplexNetwork.scala 134:68] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1896 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1897 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1898 = and(_T_1897, _T_1854) @[CoreplexNetwork.scala 134:68] + when _T_1898 : @[CoreplexNetwork.scala 134:68] + _T_1865 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 134:68] + _T_1867 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 134:68] + _T_1869 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 134:68] + _T_1871 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 134:68] + _T_1873 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1899 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1902 = dshl(_T_1901, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1903 = bits(_T_1902, 7, 0) @[package.scala 19:76] + node _T_1904 = not(_T_1903) @[package.scala 19:40] + node _T_1905 = shr(_T_1904, 3) @[Edges.scala 198:59] + node _T_1906 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1908 = mux(_T_1906, _T_1905, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1910 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1912 = sub(_T_1910, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1913 = asUInt(_T_1912) @[Edges.scala 208:28] + node _T_1914 = tail(_T_1913, 1) @[Edges.scala 208:28] + node _T_1916 = eq(_T_1910, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1918 = eq(_T_1910, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1920 = eq(_T_1908, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1921 = or(_T_1918, _T_1920) @[Edges.scala 210:37] + node _T_1922 = and(_T_1921, _T_1899) @[Edges.scala 211:22] + node _T_1923 = not(_T_1914) @[Edges.scala 212:27] + node _T_1924 = and(_T_1908, _T_1923) @[Edges.scala 212:25] + when _T_1899 : @[Edges.scala 213:17] + node _T_1925 = mux(_T_1916, _T_1908, _T_1914) @[Edges.scala 214:21] + _T_1910 <= _T_1925 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1927 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1929 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1931 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1933 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1935 : UInt, clock @[CoreplexNetwork.scala 134:68] + reg _T_1937 : UInt, clock @[CoreplexNetwork.scala 134:68] + node _T_1939 = eq(_T_1916, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_1940 = and(io.in[0].d.valid, _T_1939) @[CoreplexNetwork.scala 134:68] + when _T_1940 : @[CoreplexNetwork.scala 134:68] + node _T_1941 = eq(io.in[0].d.bits.opcode, _T_1927) @[CoreplexNetwork.scala 134:68] + node _T_1942 = or(_T_1941, reset) @[CoreplexNetwork.scala 134:68] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1944 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1945 = eq(io.in[0].d.bits.param, _T_1929) @[CoreplexNetwork.scala 134:68] + node _T_1946 = or(_T_1945, reset) @[CoreplexNetwork.scala 134:68] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1948 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1949 = eq(io.in[0].d.bits.size, _T_1931) @[CoreplexNetwork.scala 134:68] + node _T_1950 = or(_T_1949, reset) @[CoreplexNetwork.scala 134:68] + node _T_1952 = eq(_T_1950, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1952 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1953 = eq(io.in[0].d.bits.source, _T_1933) @[CoreplexNetwork.scala 134:68] + node _T_1954 = or(_T_1953, reset) @[CoreplexNetwork.scala 134:68] + node _T_1956 = eq(_T_1954, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1956 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1957 = eq(io.in[0].d.bits.sink, _T_1935) @[CoreplexNetwork.scala 134:68] + node _T_1958 = or(_T_1957, reset) @[CoreplexNetwork.scala 134:68] + node _T_1960 = eq(_T_1958, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1960 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1961 = eq(io.in[0].d.bits.addr_lo, _T_1937) @[CoreplexNetwork.scala 134:68] + node _T_1962 = or(_T_1961, reset) @[CoreplexNetwork.scala 134:68] + node _T_1964 = eq(_T_1962, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_1964 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_1965 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1966 = and(_T_1965, _T_1916) @[CoreplexNetwork.scala 134:68] + when _T_1966 : @[CoreplexNetwork.scala 134:68] + _T_1927 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 134:68] + _T_1929 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 134:68] + _T_1931 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 134:68] + _T_1933 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 134:68] + _T_1935 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 134:68] + _T_1937 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + reg _T_1968 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_1969 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1971 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1972 = dshl(_T_1971, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1973 = bits(_T_1972, 7, 0) @[package.scala 19:76] + node _T_1974 = not(_T_1973) @[package.scala 19:40] + node _T_1975 = shr(_T_1974, 3) @[Edges.scala 198:59] + node _T_1976 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1978 = eq(_T_1976, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1980 = mux(_T_1978, _T_1975, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1982 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1984 = sub(_T_1982, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1985 = asUInt(_T_1984) @[Edges.scala 208:28] + node _T_1986 = tail(_T_1985, 1) @[Edges.scala 208:28] + node _T_1988 = eq(_T_1982, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1990 = eq(_T_1982, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1992 = eq(_T_1980, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1993 = or(_T_1990, _T_1992) @[Edges.scala 210:37] + node _T_1994 = and(_T_1993, _T_1969) @[Edges.scala 211:22] + node _T_1995 = not(_T_1986) @[Edges.scala 212:27] + node _T_1996 = and(_T_1980, _T_1995) @[Edges.scala 212:25] + when _T_1969 : @[Edges.scala 213:17] + node _T_1997 = mux(_T_1988, _T_1980, _T_1986) @[Edges.scala 214:21] + _T_1982 <= _T_1997 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1998 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2000 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2001 = dshl(_T_2000, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2002 = bits(_T_2001, 7, 0) @[package.scala 19:76] + node _T_2003 = not(_T_2002) @[package.scala 19:40] + node _T_2004 = shr(_T_2003, 3) @[Edges.scala 198:59] + node _T_2005 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2007 = mux(_T_2005, _T_2004, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2009 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2011 = sub(_T_2009, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2012 = asUInt(_T_2011) @[Edges.scala 208:28] + node _T_2013 = tail(_T_2012, 1) @[Edges.scala 208:28] + node _T_2015 = eq(_T_2009, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2017 = eq(_T_2009, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2019 = eq(_T_2007, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2020 = or(_T_2017, _T_2019) @[Edges.scala 210:37] + node _T_2021 = and(_T_2020, _T_1998) @[Edges.scala 211:22] + node _T_2022 = not(_T_2013) @[Edges.scala 212:27] + node _T_2023 = and(_T_2007, _T_2022) @[Edges.scala 212:25] + when _T_1998 : @[Edges.scala 213:17] + node _T_2024 = mux(_T_2015, _T_2007, _T_2013) @[Edges.scala 214:21] + _T_2009 <= _T_2024 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2026 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + node _T_2027 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 134:68] + node _T_2028 = or(_T_2026, _T_2027) @[CoreplexNetwork.scala 134:68] + node _T_2030 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_2031 = or(_T_2028, _T_2030) @[CoreplexNetwork.scala 134:68] + node _T_2033 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_2034 = or(_T_2031, _T_2033) @[CoreplexNetwork.scala 134:68] + node _T_2035 = or(_T_2034, reset) @[CoreplexNetwork.scala 134:68] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_2037 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + wire _T_2039 : UInt<32> + _T_2039 is invalid + _T_2039 <= UInt<32>("h00") + node _T_2040 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2040 : @[CoreplexNetwork.scala 134:68] + when _T_1993 : @[CoreplexNetwork.scala 134:68] + node _T_2042 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2039 <= _T_2042 @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_2043 = dshr(_T_1968, io.in[0].a.bits.source) @[CoreplexNetwork.scala 134:68] + node _T_2044 = bits(_T_2043, 0, 0) @[CoreplexNetwork.scala 134:68] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + node _T_2047 = or(_T_2046, reset) @[CoreplexNetwork.scala 134:68] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_2049 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + wire _T_2051 : UInt<32> + _T_2051 is invalid + _T_2051 <= UInt<32>("h00") + node _T_2052 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2054 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:68] + node _T_2055 = and(_T_2052, _T_2054) @[CoreplexNetwork.scala 134:68] + when _T_2055 : @[CoreplexNetwork.scala 134:68] + when _T_2020 : @[CoreplexNetwork.scala 134:68] + node _T_2057 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2051 <= _T_2057 @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_2058 = or(_T_2039, _T_1968) @[CoreplexNetwork.scala 134:68] + node _T_2059 = dshr(_T_2058, io.in[0].d.bits.source) @[CoreplexNetwork.scala 134:68] + node _T_2060 = bits(_T_2059, 0, 0) @[CoreplexNetwork.scala 134:68] + node _T_2061 = or(_T_2060, reset) @[CoreplexNetwork.scala 134:68] + node _T_2063 = eq(_T_2061, UInt<1>("h00")) @[CoreplexNetwork.scala 134:68] + when _T_2063 : @[CoreplexNetwork.scala 134:68] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:134:68)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 134:68] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + skip @[CoreplexNetwork.scala 134:68] + node _T_2064 = or(_T_1968, _T_2039) @[CoreplexNetwork.scala 134:68] + node _T_2065 = not(_T_2051) @[CoreplexNetwork.scala 134:68] + node _T_2066 = and(_T_2064, _T_2065) @[CoreplexNetwork.scala 134:68] + _T_1968 <= _T_2066 @[CoreplexNetwork.scala 134:68] + + module TLMonitor_24 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[CoreplexNetwork.scala 134:12] + node _T_781 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_782 = or(_T_781, reset) @[CoreplexNetwork.scala 134:12] + node _T_784 = eq(_T_782, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_784 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_786 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_787 = not(_T_786) @[Parameters.scala 37:9] + node _T_789 = or(_T_787, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_790 = not(_T_789) @[Parameters.scala 37:7] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_795 : UInt<1>[1] @[Parameters.scala 228:27] + _T_795 is invalid @[Parameters.scala 228:27] + _T_795[0] <= _T_792 @[Parameters.scala 228:27] + node _T_800 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_801 = dshl(_T_800, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_802 = bits(_T_801, 7, 0) @[package.scala 19:76] + node _T_803 = not(_T_802) @[package.scala 19:40] + node _T_804 = and(io.in[0].a.bits.address, _T_803) @[Edges.scala 17:16] + node _T_806 = eq(_T_804, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_808 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_809 = dshl(UInt<1>("h01"), _T_808) @[OneHot.scala 49:12] + node _T_810 = bits(_T_809, 2, 0) @[OneHot.scala 49:37] + node _T_812 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_814 = bits(_T_810, 2, 2) @[package.scala 44:26] + node _T_815 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_817 = eq(_T_815, UInt<1>("h00")) @[package.scala 46:20] + node _T_818 = and(UInt<1>("h01"), _T_817) @[package.scala 49:27] + node _T_819 = and(_T_814, _T_818) @[package.scala 50:38] + node _T_820 = or(_T_812, _T_819) @[package.scala 50:29] + node _T_821 = and(UInt<1>("h01"), _T_815) @[package.scala 49:27] + node _T_822 = and(_T_814, _T_821) @[package.scala 50:38] + node _T_823 = or(_T_812, _T_822) @[package.scala 50:29] + node _T_824 = bits(_T_810, 1, 1) @[package.scala 44:26] + node _T_825 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_827 = eq(_T_825, UInt<1>("h00")) @[package.scala 46:20] + node _T_828 = and(_T_818, _T_827) @[package.scala 49:27] + node _T_829 = and(_T_824, _T_828) @[package.scala 50:38] + node _T_830 = or(_T_820, _T_829) @[package.scala 50:29] + node _T_831 = and(_T_818, _T_825) @[package.scala 49:27] + node _T_832 = and(_T_824, _T_831) @[package.scala 50:38] + node _T_833 = or(_T_820, _T_832) @[package.scala 50:29] + node _T_834 = and(_T_821, _T_827) @[package.scala 49:27] + node _T_835 = and(_T_824, _T_834) @[package.scala 50:38] + node _T_836 = or(_T_823, _T_835) @[package.scala 50:29] + node _T_837 = and(_T_821, _T_825) @[package.scala 49:27] + node _T_838 = and(_T_824, _T_837) @[package.scala 50:38] + node _T_839 = or(_T_823, _T_838) @[package.scala 50:29] + node _T_840 = bits(_T_810, 0, 0) @[package.scala 44:26] + node _T_841 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[package.scala 46:20] + node _T_844 = and(_T_828, _T_843) @[package.scala 49:27] + node _T_845 = and(_T_840, _T_844) @[package.scala 50:38] + node _T_846 = or(_T_830, _T_845) @[package.scala 50:29] + node _T_847 = and(_T_828, _T_841) @[package.scala 49:27] + node _T_848 = and(_T_840, _T_847) @[package.scala 50:38] + node _T_849 = or(_T_830, _T_848) @[package.scala 50:29] + node _T_850 = and(_T_831, _T_843) @[package.scala 49:27] + node _T_851 = and(_T_840, _T_850) @[package.scala 50:38] + node _T_852 = or(_T_833, _T_851) @[package.scala 50:29] + node _T_853 = and(_T_831, _T_841) @[package.scala 49:27] + node _T_854 = and(_T_840, _T_853) @[package.scala 50:38] + node _T_855 = or(_T_833, _T_854) @[package.scala 50:29] + node _T_856 = and(_T_834, _T_843) @[package.scala 49:27] + node _T_857 = and(_T_840, _T_856) @[package.scala 50:38] + node _T_858 = or(_T_836, _T_857) @[package.scala 50:29] + node _T_859 = and(_T_834, _T_841) @[package.scala 49:27] + node _T_860 = and(_T_840, _T_859) @[package.scala 50:38] + node _T_861 = or(_T_836, _T_860) @[package.scala 50:29] + node _T_862 = and(_T_837, _T_843) @[package.scala 49:27] + node _T_863 = and(_T_840, _T_862) @[package.scala 50:38] + node _T_864 = or(_T_839, _T_863) @[package.scala 50:29] + node _T_865 = and(_T_837, _T_841) @[package.scala 49:27] + node _T_866 = and(_T_840, _T_865) @[package.scala 50:38] + node _T_867 = or(_T_839, _T_866) @[package.scala 50:29] + node _T_868 = cat(_T_849, _T_846) @[Cat.scala 30:58] + node _T_869 = cat(_T_855, _T_852) @[Cat.scala 30:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 30:58] + node _T_871 = cat(_T_861, _T_858) @[Cat.scala 30:58] + node _T_872 = cat(_T_867, _T_864) @[Cat.scala 30:58] + node _T_873 = cat(_T_872, _T_871) @[Cat.scala 30:58] + node _T_874 = cat(_T_873, _T_870) @[Cat.scala 30:58] + node _T_876 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + when _T_876 : @[CoreplexNetwork.scala 134:12] + node _T_879 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_881 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_882 = cvt(_T_881) @[Parameters.scala 117:49] + node _T_884 = and(_T_882, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_885 = asSInt(_T_884) @[Parameters.scala 117:52] + node _T_887 = eq(_T_885, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_889 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_890 = cvt(_T_889) @[Parameters.scala 117:49] + node _T_892 = and(_T_890, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_893 = asSInt(_T_892) @[Parameters.scala 117:52] + node _T_895 = eq(_T_893, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = or(_T_887, _T_895) @[Parameters.scala 133:42] + node _T_897 = and(_T_879, _T_896) @[Parameters.scala 132:56] + node _T_899 = or(UInt<1>("h00"), _T_897) @[Parameters.scala 134:30] + node _T_900 = or(_T_899, reset) @[CoreplexNetwork.scala 134:12] + node _T_902 = eq(_T_900, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_902 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_903 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_905 = eq(_T_903, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_905 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_907 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_908 = or(_T_907, reset) @[CoreplexNetwork.scala 134:12] + node _T_910 = eq(_T_908, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_910 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_911 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_913 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_915 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_916 = or(_T_915, reset) @[CoreplexNetwork.scala 134:12] + node _T_918 = eq(_T_916, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_918 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_919 = not(io.in[0].a.bits.mask) @[CoreplexNetwork.scala 134:12] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_922 = or(_T_921, reset) @[CoreplexNetwork.scala 134:12] + node _T_924 = eq(_T_922, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_924 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_926 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:12] + when _T_926 : @[CoreplexNetwork.scala 134:12] + node _T_929 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_931 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_932 = and(_T_929, _T_931) @[Parameters.scala 63:37] + node _T_933 = or(UInt<1>("h00"), _T_932) @[Parameters.scala 132:31] + node _T_935 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_936 = cvt(_T_935) @[Parameters.scala 117:49] + node _T_938 = and(_T_936, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_939 = asSInt(_T_938) @[Parameters.scala 117:52] + node _T_941 = eq(_T_939, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_942 = and(_T_933, _T_941) @[Parameters.scala 132:56] + node _T_945 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_947 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_948 = and(_T_945, _T_947) @[Parameters.scala 63:37] + node _T_949 = or(UInt<1>("h00"), _T_948) @[Parameters.scala 132:31] + node _T_951 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_958 = and(_T_949, _T_957) @[Parameters.scala 132:56] + node _T_960 = or(UInt<1>("h00"), _T_942) @[Parameters.scala 134:30] + node _T_961 = or(_T_960, _T_958) @[Parameters.scala 134:30] + node _T_962 = or(_T_961, reset) @[CoreplexNetwork.scala 134:12] + node _T_964 = eq(_T_962, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_964 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_965 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_967 = eq(_T_965, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_967 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_968 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_970 = eq(_T_968, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_970 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_972 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_973 = or(_T_972, reset) @[CoreplexNetwork.scala 134:12] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_975 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_976 = eq(io.in[0].a.bits.mask, _T_874) @[CoreplexNetwork.scala 134:12] + node _T_977 = or(_T_976, reset) @[CoreplexNetwork.scala 134:12] + node _T_979 = eq(_T_977, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_979 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_981 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_981 : @[CoreplexNetwork.scala 134:12] + node _T_984 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_986 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_987 = and(_T_984, _T_986) @[Parameters.scala 63:37] + node _T_988 = or(UInt<1>("h00"), _T_987) @[Parameters.scala 132:31] + node _T_990 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_991 = cvt(_T_990) @[Parameters.scala 117:49] + node _T_993 = and(_T_991, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_994 = asSInt(_T_993) @[Parameters.scala 117:52] + node _T_996 = eq(_T_994, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_997 = and(_T_988, _T_996) @[Parameters.scala 132:56] + node _T_1000 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1002 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1003 = and(_T_1000, _T_1002) @[Parameters.scala 63:37] + node _T_1004 = or(UInt<1>("h00"), _T_1003) @[Parameters.scala 132:31] + node _T_1006 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1007 = cvt(_T_1006) @[Parameters.scala 117:49] + node _T_1009 = and(_T_1007, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1010 = asSInt(_T_1009) @[Parameters.scala 117:52] + node _T_1012 = eq(_T_1010, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1013 = and(_T_1004, _T_1012) @[Parameters.scala 132:56] + node _T_1015 = or(UInt<1>("h00"), _T_997) @[Parameters.scala 134:30] + node _T_1016 = or(_T_1015, _T_1013) @[Parameters.scala 134:30] + node _T_1017 = or(_T_1016, reset) @[CoreplexNetwork.scala 134:12] + node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1019 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1020 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1022 = eq(_T_1020, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1022 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1023 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1025 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1027 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1028 = or(_T_1027, reset) @[CoreplexNetwork.scala 134:12] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1030 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1031 = eq(io.in[0].a.bits.mask, _T_874) @[CoreplexNetwork.scala 134:12] + node _T_1032 = or(_T_1031, reset) @[CoreplexNetwork.scala 134:12] + node _T_1034 = eq(_T_1032, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1034 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1036 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:12] + when _T_1036 : @[CoreplexNetwork.scala 134:12] + node _T_1039 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1041 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1042 = and(_T_1039, _T_1041) @[Parameters.scala 63:37] + node _T_1043 = or(UInt<1>("h00"), _T_1042) @[Parameters.scala 132:31] + node _T_1045 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1046 = cvt(_T_1045) @[Parameters.scala 117:49] + node _T_1048 = and(_T_1046, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1049 = asSInt(_T_1048) @[Parameters.scala 117:52] + node _T_1051 = eq(_T_1049, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1052 = and(_T_1043, _T_1051) @[Parameters.scala 132:56] + node _T_1055 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1057 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1058 = and(_T_1055, _T_1057) @[Parameters.scala 63:37] + node _T_1059 = or(UInt<1>("h00"), _T_1058) @[Parameters.scala 132:31] + node _T_1061 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1062 = cvt(_T_1061) @[Parameters.scala 117:49] + node _T_1064 = and(_T_1062, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1065 = asSInt(_T_1064) @[Parameters.scala 117:52] + node _T_1067 = eq(_T_1065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1068 = and(_T_1059, _T_1067) @[Parameters.scala 132:56] + node _T_1070 = or(UInt<1>("h00"), _T_1052) @[Parameters.scala 134:30] + node _T_1071 = or(_T_1070, _T_1068) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, reset) @[CoreplexNetwork.scala 134:12] + node _T_1074 = eq(_T_1072, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1074 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1075 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1077 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1078 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_1080 = eq(_T_1078, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1080 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1082 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1083 = or(_T_1082, reset) @[CoreplexNetwork.scala 134:12] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1085 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1086 = not(_T_874) @[CoreplexNetwork.scala 134:12] + node _T_1087 = and(io.in[0].a.bits.mask, _T_1086) @[CoreplexNetwork.scala 134:12] + node _T_1089 = eq(_T_1087, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1090 = or(_T_1089, reset) @[CoreplexNetwork.scala 134:12] + node _T_1092 = eq(_T_1090, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1092 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1094 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + when _T_1094 : @[CoreplexNetwork.scala 134:12] + node _T_1097 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1099 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1100 = cvt(_T_1099) @[Parameters.scala 117:49] + node _T_1102 = and(_T_1100, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1103 = asSInt(_T_1102) @[Parameters.scala 117:52] + node _T_1105 = eq(_T_1103, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1107 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1108 = cvt(_T_1107) @[Parameters.scala 117:49] + node _T_1110 = and(_T_1108, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1111 = asSInt(_T_1110) @[Parameters.scala 117:52] + node _T_1113 = eq(_T_1111, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1114 = or(_T_1105, _T_1113) @[Parameters.scala 133:42] + node _T_1115 = and(_T_1097, _T_1114) @[Parameters.scala 132:56] + node _T_1117 = or(UInt<1>("h00"), _T_1115) @[Parameters.scala 134:30] + node _T_1118 = or(_T_1117, reset) @[CoreplexNetwork.scala 134:12] + node _T_1120 = eq(_T_1118, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1120 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1121 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1123 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1124 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1126 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1128 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1129 = or(_T_1128, reset) @[CoreplexNetwork.scala 134:12] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1131 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1132 = eq(io.in[0].a.bits.mask, _T_874) @[CoreplexNetwork.scala 134:12] + node _T_1133 = or(_T_1132, reset) @[CoreplexNetwork.scala 134:12] + node _T_1135 = eq(_T_1133, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1135 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1137 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + when _T_1137 : @[CoreplexNetwork.scala 134:12] + node _T_1140 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1142 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1143 = cvt(_T_1142) @[Parameters.scala 117:49] + node _T_1145 = and(_T_1143, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1146 = asSInt(_T_1145) @[Parameters.scala 117:52] + node _T_1148 = eq(_T_1146, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1150 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1151 = cvt(_T_1150) @[Parameters.scala 117:49] + node _T_1153 = and(_T_1151, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1154 = asSInt(_T_1153) @[Parameters.scala 117:52] + node _T_1156 = eq(_T_1154, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1157 = or(_T_1148, _T_1156) @[Parameters.scala 133:42] + node _T_1158 = and(_T_1140, _T_1157) @[Parameters.scala 132:56] + node _T_1160 = or(UInt<1>("h00"), _T_1158) @[Parameters.scala 134:30] + node _T_1161 = or(_T_1160, reset) @[CoreplexNetwork.scala 134:12] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1163 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1164 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1166 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1167 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1169 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1171 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1172 = or(_T_1171, reset) @[CoreplexNetwork.scala 134:12] + node _T_1174 = eq(_T_1172, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1174 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1175 = eq(io.in[0].a.bits.mask, _T_874) @[CoreplexNetwork.scala 134:12] + node _T_1176 = or(_T_1175, reset) @[CoreplexNetwork.scala 134:12] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1178 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1180 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:12] + when _T_1180 : @[CoreplexNetwork.scala 134:12] + node _T_1183 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1185 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1186 = cvt(_T_1185) @[Parameters.scala 117:49] + node _T_1188 = and(_T_1186, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1189 = asSInt(_T_1188) @[Parameters.scala 117:52] + node _T_1191 = eq(_T_1189, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1193 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1194 = cvt(_T_1193) @[Parameters.scala 117:49] + node _T_1196 = and(_T_1194, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1197 = asSInt(_T_1196) @[Parameters.scala 117:52] + node _T_1199 = eq(_T_1197, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1200 = or(_T_1191, _T_1199) @[Parameters.scala 133:42] + node _T_1201 = and(_T_1183, _T_1200) @[Parameters.scala 132:56] + node _T_1203 = or(UInt<1>("h00"), _T_1201) @[Parameters.scala 134:30] + node _T_1204 = or(_T_1203, reset) @[CoreplexNetwork.scala 134:12] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1206 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1207 = or(_T_795[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1209 = eq(_T_1207, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1209 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1210 = or(_T_806, reset) @[CoreplexNetwork.scala 134:12] + node _T_1212 = eq(_T_1210, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1212 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1213 = eq(io.in[0].a.bits.mask, _T_874) @[CoreplexNetwork.scala 134:12] + node _T_1214 = or(_T_1213, reset) @[CoreplexNetwork.scala 134:12] + node _T_1216 = eq(_T_1214, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1216 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + when io.in[0].b.valid : @[CoreplexNetwork.scala 134:12] + node _T_1218 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1219 = or(_T_1218, reset) @[CoreplexNetwork.scala 134:12] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1221 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1223 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1224 = cvt(_T_1223) @[Parameters.scala 117:49] + node _T_1226 = and(_T_1224, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1227 = asSInt(_T_1226) @[Parameters.scala 117:52] + node _T_1229 = eq(_T_1227, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1231 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1240 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1240 is invalid @[Parameters.scala 110:36] + _T_1240[0] <= _T_1229 @[Parameters.scala 110:36] + _T_1240[1] <= _T_1237 @[Parameters.scala 110:36] + node _T_1245 = or(_T_1240[0], _T_1240[1]) @[Parameters.scala 119:64] + node _T_1247 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1248 = dshl(_T_1247, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1249 = bits(_T_1248, 7, 0) @[package.scala 19:76] + node _T_1250 = not(_T_1249) @[package.scala 19:40] + node _T_1251 = and(io.in[0].b.bits.address, _T_1250) @[Edges.scala 17:16] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1255 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1256 = dshl(UInt<1>("h01"), _T_1255) @[OneHot.scala 49:12] + node _T_1257 = bits(_T_1256, 2, 0) @[OneHot.scala 49:37] + node _T_1259 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1261 = bits(_T_1257, 2, 2) @[package.scala 44:26] + node _T_1262 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[package.scala 46:20] + node _T_1265 = and(UInt<1>("h01"), _T_1264) @[package.scala 49:27] + node _T_1266 = and(_T_1261, _T_1265) @[package.scala 50:38] + node _T_1267 = or(_T_1259, _T_1266) @[package.scala 50:29] + node _T_1268 = and(UInt<1>("h01"), _T_1262) @[package.scala 49:27] + node _T_1269 = and(_T_1261, _T_1268) @[package.scala 50:38] + node _T_1270 = or(_T_1259, _T_1269) @[package.scala 50:29] + node _T_1271 = bits(_T_1257, 1, 1) @[package.scala 44:26] + node _T_1272 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[package.scala 46:20] + node _T_1275 = and(_T_1265, _T_1274) @[package.scala 49:27] + node _T_1276 = and(_T_1271, _T_1275) @[package.scala 50:38] + node _T_1277 = or(_T_1267, _T_1276) @[package.scala 50:29] + node _T_1278 = and(_T_1265, _T_1272) @[package.scala 49:27] + node _T_1279 = and(_T_1271, _T_1278) @[package.scala 50:38] + node _T_1280 = or(_T_1267, _T_1279) @[package.scala 50:29] + node _T_1281 = and(_T_1268, _T_1274) @[package.scala 49:27] + node _T_1282 = and(_T_1271, _T_1281) @[package.scala 50:38] + node _T_1283 = or(_T_1270, _T_1282) @[package.scala 50:29] + node _T_1284 = and(_T_1268, _T_1272) @[package.scala 49:27] + node _T_1285 = and(_T_1271, _T_1284) @[package.scala 50:38] + node _T_1286 = or(_T_1270, _T_1285) @[package.scala 50:29] + node _T_1287 = bits(_T_1257, 0, 0) @[package.scala 44:26] + node _T_1288 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[package.scala 46:20] + node _T_1291 = and(_T_1275, _T_1290) @[package.scala 49:27] + node _T_1292 = and(_T_1287, _T_1291) @[package.scala 50:38] + node _T_1293 = or(_T_1277, _T_1292) @[package.scala 50:29] + node _T_1294 = and(_T_1275, _T_1288) @[package.scala 49:27] + node _T_1295 = and(_T_1287, _T_1294) @[package.scala 50:38] + node _T_1296 = or(_T_1277, _T_1295) @[package.scala 50:29] + node _T_1297 = and(_T_1278, _T_1290) @[package.scala 49:27] + node _T_1298 = and(_T_1287, _T_1297) @[package.scala 50:38] + node _T_1299 = or(_T_1280, _T_1298) @[package.scala 50:29] + node _T_1300 = and(_T_1278, _T_1288) @[package.scala 49:27] + node _T_1301 = and(_T_1287, _T_1300) @[package.scala 50:38] + node _T_1302 = or(_T_1280, _T_1301) @[package.scala 50:29] + node _T_1303 = and(_T_1281, _T_1290) @[package.scala 49:27] + node _T_1304 = and(_T_1287, _T_1303) @[package.scala 50:38] + node _T_1305 = or(_T_1283, _T_1304) @[package.scala 50:29] + node _T_1306 = and(_T_1281, _T_1288) @[package.scala 49:27] + node _T_1307 = and(_T_1287, _T_1306) @[package.scala 50:38] + node _T_1308 = or(_T_1283, _T_1307) @[package.scala 50:29] + node _T_1309 = and(_T_1284, _T_1290) @[package.scala 49:27] + node _T_1310 = and(_T_1287, _T_1309) @[package.scala 50:38] + node _T_1311 = or(_T_1286, _T_1310) @[package.scala 50:29] + node _T_1312 = and(_T_1284, _T_1288) @[package.scala 49:27] + node _T_1313 = and(_T_1287, _T_1312) @[package.scala 50:38] + node _T_1314 = or(_T_1286, _T_1313) @[package.scala 50:29] + node _T_1315 = cat(_T_1296, _T_1293) @[Cat.scala 30:58] + node _T_1316 = cat(_T_1302, _T_1299) @[Cat.scala 30:58] + node _T_1317 = cat(_T_1316, _T_1315) @[Cat.scala 30:58] + node _T_1318 = cat(_T_1308, _T_1305) @[Cat.scala 30:58] + node _T_1319 = cat(_T_1314, _T_1311) @[Cat.scala 30:58] + node _T_1320 = cat(_T_1319, _T_1318) @[Cat.scala 30:58] + node _T_1321 = cat(_T_1320, _T_1317) @[Cat.scala 30:58] + node _T_1323 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + when _T_1323 : @[CoreplexNetwork.scala 134:12] + node _T_1325 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1327 = eq(_T_1325, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1327 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1328 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1330 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1332 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1333 = or(_T_1332, reset) @[CoreplexNetwork.scala 134:12] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1335 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1336 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1338 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1340 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1341 = or(_T_1340, reset) @[CoreplexNetwork.scala 134:12] + node _T_1343 = eq(_T_1341, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1343 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1344 = not(io.in[0].b.bits.mask) @[CoreplexNetwork.scala 134:12] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1347 = or(_T_1346, reset) @[CoreplexNetwork.scala 134:12] + node _T_1349 = eq(_T_1347, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1349 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1351 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:12] + when _T_1351 : @[CoreplexNetwork.scala 134:12] + node _T_1353 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1355 = eq(_T_1353, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1355 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1356 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1358 = eq(_T_1356, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1358 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1359 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1361 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1363 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1364 = or(_T_1363, reset) @[CoreplexNetwork.scala 134:12] + node _T_1366 = eq(_T_1364, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1366 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1367 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1368 = or(_T_1367, reset) @[CoreplexNetwork.scala 134:12] + node _T_1370 = eq(_T_1368, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1370 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1372 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1372 : @[CoreplexNetwork.scala 134:12] + node _T_1374 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1376 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1377 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1379 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1380 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1382 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1384 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1385 = or(_T_1384, reset) @[CoreplexNetwork.scala 134:12] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1387 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1388 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1389 = or(_T_1388, reset) @[CoreplexNetwork.scala 134:12] + node _T_1391 = eq(_T_1389, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1391 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1393 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:12] + when _T_1393 : @[CoreplexNetwork.scala 134:12] + node _T_1395 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1397 = eq(_T_1395, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1397 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1398 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1400 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1401 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1403 = eq(_T_1401, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1403 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1405 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1406 = or(_T_1405, reset) @[CoreplexNetwork.scala 134:12] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1408 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1409 = not(_T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1410 = and(io.in[0].b.bits.mask, _T_1409) @[CoreplexNetwork.scala 134:12] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1413 = or(_T_1412, reset) @[CoreplexNetwork.scala 134:12] + node _T_1415 = eq(_T_1413, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1415 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1417 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + when _T_1417 : @[CoreplexNetwork.scala 134:12] + node _T_1419 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1421 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1422 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1424 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1425 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1427 = eq(_T_1425, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1427 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1429 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1430 = or(_T_1429, reset) @[CoreplexNetwork.scala 134:12] + node _T_1432 = eq(_T_1430, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1432 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1433 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1434 = or(_T_1433, reset) @[CoreplexNetwork.scala 134:12] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1436 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1438 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + when _T_1438 : @[CoreplexNetwork.scala 134:12] + node _T_1440 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1442 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1443 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1445 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1446 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1448 = eq(_T_1446, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1448 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1450 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1451 = or(_T_1450, reset) @[CoreplexNetwork.scala 134:12] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1453 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1454 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1455 = or(_T_1454, reset) @[CoreplexNetwork.scala 134:12] + node _T_1457 = eq(_T_1455, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1457 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1459 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:12] + when _T_1459 : @[CoreplexNetwork.scala 134:12] + node _T_1461 = or(UInt<1>("h00"), reset) @[CoreplexNetwork.scala 134:12] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1463 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1464 = or(_T_1245, reset) @[CoreplexNetwork.scala 134:12] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1466 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1467 = or(_T_1253, reset) @[CoreplexNetwork.scala 134:12] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1469 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1470 = eq(io.in[0].b.bits.mask, _T_1321) @[CoreplexNetwork.scala 134:12] + node _T_1471 = or(_T_1470, reset) @[CoreplexNetwork.scala 134:12] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1473 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + when io.in[0].c.valid : @[CoreplexNetwork.scala 134:12] + node _T_1475 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1476 = or(_T_1475, reset) @[CoreplexNetwork.scala 134:12] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1478 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1480 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1481 = not(_T_1480) @[Parameters.scala 37:9] + node _T_1483 = or(_T_1481, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1484 = not(_T_1483) @[Parameters.scala 37:7] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1489 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1489 is invalid @[Parameters.scala 228:27] + _T_1489[0] <= _T_1486 @[Parameters.scala 228:27] + node _T_1494 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1495 = dshl(_T_1494, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1496 = bits(_T_1495, 7, 0) @[package.scala 19:76] + node _T_1497 = not(_T_1496) @[package.scala 19:40] + node _T_1498 = and(io.in[0].c.bits.address, _T_1497) @[Edges.scala 17:16] + node _T_1500 = eq(_T_1498, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1502 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1503 = cvt(_T_1502) @[Parameters.scala 117:49] + node _T_1505 = and(_T_1503, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1506 = asSInt(_T_1505) @[Parameters.scala 117:52] + node _T_1508 = eq(_T_1506, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1510 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1511 = cvt(_T_1510) @[Parameters.scala 117:49] + node _T_1513 = and(_T_1511, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1514 = asSInt(_T_1513) @[Parameters.scala 117:52] + node _T_1516 = eq(_T_1514, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1519 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1519 is invalid @[Parameters.scala 110:36] + _T_1519[0] <= _T_1508 @[Parameters.scala 110:36] + _T_1519[1] <= _T_1516 @[Parameters.scala 110:36] + node _T_1524 = or(_T_1519[0], _T_1519[1]) @[Parameters.scala 119:64] + node _T_1526 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:12] + when _T_1526 : @[CoreplexNetwork.scala 134:12] + node _T_1527 = or(_T_1524, reset) @[CoreplexNetwork.scala 134:12] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1529 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1530 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1532 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1534 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1535 = or(_T_1534, reset) @[CoreplexNetwork.scala 134:12] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1537 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1538 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1540 = eq(_T_1538, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1540 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1542 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1543 = or(_T_1542, reset) @[CoreplexNetwork.scala 134:12] + node _T_1545 = eq(_T_1543, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1545 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1547 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1548 = or(_T_1547, reset) @[CoreplexNetwork.scala 134:12] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1550 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1552 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:12] + when _T_1552 : @[CoreplexNetwork.scala 134:12] + node _T_1553 = or(_T_1524, reset) @[CoreplexNetwork.scala 134:12] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1555 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1556 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1558 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1560 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1561 = or(_T_1560, reset) @[CoreplexNetwork.scala 134:12] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1563 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1564 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1566 = eq(_T_1564, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1566 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1568 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1569 = or(_T_1568, reset) @[CoreplexNetwork.scala 134:12] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1571 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1573 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1574 = or(_T_1573, reset) @[CoreplexNetwork.scala 134:12] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1576 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1578 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + when _T_1578 : @[CoreplexNetwork.scala 134:12] + node _T_1581 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1583 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1584 = cvt(_T_1583) @[Parameters.scala 117:49] + node _T_1586 = and(_T_1584, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1587 = asSInt(_T_1586) @[Parameters.scala 117:52] + node _T_1589 = eq(_T_1587, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1591 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1592 = cvt(_T_1591) @[Parameters.scala 117:49] + node _T_1594 = and(_T_1592, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1595 = asSInt(_T_1594) @[Parameters.scala 117:52] + node _T_1597 = eq(_T_1595, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1598 = or(_T_1589, _T_1597) @[Parameters.scala 133:42] + node _T_1599 = and(_T_1581, _T_1598) @[Parameters.scala 132:56] + node _T_1601 = or(UInt<1>("h00"), _T_1599) @[Parameters.scala 134:30] + node _T_1602 = or(_T_1601, reset) @[CoreplexNetwork.scala 134:12] + node _T_1604 = eq(_T_1602, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1604 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1605 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1607 = eq(_T_1605, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1607 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1609 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1610 = or(_T_1609, reset) @[CoreplexNetwork.scala 134:12] + node _T_1612 = eq(_T_1610, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1612 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1613 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1615 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1617 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1618 = or(_T_1617, reset) @[CoreplexNetwork.scala 134:12] + node _T_1620 = eq(_T_1618, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1620 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1622 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1623 = or(_T_1622, reset) @[CoreplexNetwork.scala 134:12] + node _T_1625 = eq(_T_1623, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1625 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1627 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[CoreplexNetwork.scala 134:12] + when _T_1627 : @[CoreplexNetwork.scala 134:12] + node _T_1630 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1632 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1633 = cvt(_T_1632) @[Parameters.scala 117:49] + node _T_1635 = and(_T_1633, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1636 = asSInt(_T_1635) @[Parameters.scala 117:52] + node _T_1638 = eq(_T_1636, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1640 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1641 = cvt(_T_1640) @[Parameters.scala 117:49] + node _T_1643 = and(_T_1641, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1644 = asSInt(_T_1643) @[Parameters.scala 117:52] + node _T_1646 = eq(_T_1644, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1647 = or(_T_1638, _T_1646) @[Parameters.scala 133:42] + node _T_1648 = and(_T_1630, _T_1647) @[Parameters.scala 132:56] + node _T_1650 = or(UInt<1>("h00"), _T_1648) @[Parameters.scala 134:30] + node _T_1651 = or(_T_1650, reset) @[CoreplexNetwork.scala 134:12] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1653 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1654 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1656 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1658 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1659 = or(_T_1658, reset) @[CoreplexNetwork.scala 134:12] + node _T_1661 = eq(_T_1659, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1661 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1662 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1664 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1666 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1667 = or(_T_1666, reset) @[CoreplexNetwork.scala 134:12] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1669 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1671 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1672 = or(_T_1671, reset) @[CoreplexNetwork.scala 134:12] + node _T_1674 = eq(_T_1672, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1674 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1676 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1676 : @[CoreplexNetwork.scala 134:12] + node _T_1677 = or(_T_1524, reset) @[CoreplexNetwork.scala 134:12] + node _T_1679 = eq(_T_1677, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1679 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1680 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1682 = eq(_T_1680, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1682 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1683 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1685 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1687 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1688 = or(_T_1687, reset) @[CoreplexNetwork.scala 134:12] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1690 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1692 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:12] + when _T_1692 : @[CoreplexNetwork.scala 134:12] + node _T_1693 = or(_T_1524, reset) @[CoreplexNetwork.scala 134:12] + node _T_1695 = eq(_T_1693, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1695 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1696 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1698 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1699 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1701 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1703 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1704 = or(_T_1703, reset) @[CoreplexNetwork.scala 134:12] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1706 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1708 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + when _T_1708 : @[CoreplexNetwork.scala 134:12] + node _T_1709 = or(_T_1524, reset) @[CoreplexNetwork.scala 134:12] + node _T_1711 = eq(_T_1709, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1711 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1712 = or(_T_1489[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1714 = eq(_T_1712, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1714 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1715 = or(_T_1500, reset) @[CoreplexNetwork.scala 134:12] + node _T_1717 = eq(_T_1715, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1717 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1719 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1720 = or(_T_1719, reset) @[CoreplexNetwork.scala 134:12] + node _T_1722 = eq(_T_1720, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1722 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1724 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1725 = or(_T_1724, reset) @[CoreplexNetwork.scala 134:12] + node _T_1727 = eq(_T_1725, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1727 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + when io.in[0].d.valid : @[CoreplexNetwork.scala 134:12] + node _T_1729 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1730 = or(_T_1729, reset) @[CoreplexNetwork.scala 134:12] + node _T_1732 = eq(_T_1730, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1732 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1734 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1735 = not(_T_1734) @[Parameters.scala 37:9] + node _T_1737 = or(_T_1735, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1738 = not(_T_1737) @[Parameters.scala 37:7] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1743 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1743 is invalid @[Parameters.scala 228:27] + _T_1743[0] <= _T_1740 @[Parameters.scala 228:27] + node _T_1748 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1749 = dshl(_T_1748, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1750 = bits(_T_1749, 7, 0) @[package.scala 19:76] + node _T_1751 = not(_T_1750) @[package.scala 19:40] + node _T_1752 = and(io.in[0].d.bits.addr_lo, _T_1751) @[Edges.scala 17:16] + node _T_1754 = eq(_T_1752, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1756 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + node _T_1758 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + when _T_1758 : @[CoreplexNetwork.scala 134:12] + node _T_1759 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1761 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1762 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1764 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1765 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1767 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1769 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1770 = or(_T_1769, reset) @[CoreplexNetwork.scala 134:12] + node _T_1772 = eq(_T_1770, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1772 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1774 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1775 = or(_T_1774, reset) @[CoreplexNetwork.scala 134:12] + node _T_1777 = eq(_T_1775, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1777 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1779 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1780 = or(_T_1779, reset) @[CoreplexNetwork.scala 134:12] + node _T_1782 = eq(_T_1780, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1782 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1784 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[CoreplexNetwork.scala 134:12] + when _T_1784 : @[CoreplexNetwork.scala 134:12] + node _T_1785 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1787 = eq(_T_1785, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1787 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1788 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1790 = eq(_T_1788, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1790 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1791 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1793 = eq(_T_1791, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1793 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1795 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1796 = or(_T_1795, reset) @[CoreplexNetwork.scala 134:12] + node _T_1798 = eq(_T_1796, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1798 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1800 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1801 = or(_T_1800, reset) @[CoreplexNetwork.scala 134:12] + node _T_1803 = eq(_T_1801, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1803 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1805 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[CoreplexNetwork.scala 134:12] + when _T_1805 : @[CoreplexNetwork.scala 134:12] + node _T_1806 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1808 = eq(_T_1806, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1808 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1809 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1811 = eq(_T_1809, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1811 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1812 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1814 = eq(_T_1812, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1814 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1816 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[CoreplexNetwork.scala 134:12] + node _T_1817 = or(_T_1816, reset) @[CoreplexNetwork.scala 134:12] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1819 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1821 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1822 = or(_T_1821, reset) @[CoreplexNetwork.scala 134:12] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1824 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1826 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1826 : @[CoreplexNetwork.scala 134:12] + node _T_1827 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1829 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1830 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1832 = eq(_T_1830, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1832 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1833 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1835 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1837 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1838 = or(_T_1837, reset) @[CoreplexNetwork.scala 134:12] + node _T_1840 = eq(_T_1838, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1840 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1842 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[CoreplexNetwork.scala 134:12] + when _T_1842 : @[CoreplexNetwork.scala 134:12] + node _T_1843 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1845 = eq(_T_1843, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1845 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1846 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1848 = eq(_T_1846, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1848 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1849 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1851 = eq(_T_1849, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1851 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1853 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1854 = or(_T_1853, reset) @[CoreplexNetwork.scala 134:12] + node _T_1856 = eq(_T_1854, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1856 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1858 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + when _T_1858 : @[CoreplexNetwork.scala 134:12] + node _T_1859 = or(_T_1743[0], reset) @[CoreplexNetwork.scala 134:12] + node _T_1861 = eq(_T_1859, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1861 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1862 = or(_T_1754, reset) @[CoreplexNetwork.scala 134:12] + node _T_1864 = eq(_T_1862, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1864 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1865 = or(_T_1756, reset) @[CoreplexNetwork.scala 134:12] + node _T_1867 = eq(_T_1865, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1867 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1869 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1870 = or(_T_1869, reset) @[CoreplexNetwork.scala 134:12] + node _T_1872 = eq(_T_1870, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1872 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1874 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1875 = or(_T_1874, reset) @[CoreplexNetwork.scala 134:12] + node _T_1877 = eq(_T_1875, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1877 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + when io.in[0].e.valid : @[CoreplexNetwork.scala 134:12] + node _T_1879 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[CoreplexNetwork.scala 134:12] + node _T_1880 = or(_T_1879, reset) @[CoreplexNetwork.scala 134:12] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1882 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1883 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1885 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1886 = dshl(_T_1885, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1887 = bits(_T_1886, 7, 0) @[package.scala 19:76] + node _T_1888 = not(_T_1887) @[package.scala 19:40] + node _T_1889 = shr(_T_1888, 3) @[Edges.scala 198:59] + node _T_1890 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1894 = mux(_T_1892, _T_1889, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1896 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1898 = sub(_T_1896, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1899 = asUInt(_T_1898) @[Edges.scala 208:28] + node _T_1900 = tail(_T_1899, 1) @[Edges.scala 208:28] + node _T_1902 = eq(_T_1896, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1904 = eq(_T_1896, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1906 = eq(_T_1894, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1907 = or(_T_1904, _T_1906) @[Edges.scala 210:37] + node _T_1908 = and(_T_1907, _T_1883) @[Edges.scala 211:22] + node _T_1909 = not(_T_1900) @[Edges.scala 212:27] + node _T_1910 = and(_T_1894, _T_1909) @[Edges.scala 212:25] + when _T_1883 : @[Edges.scala 213:17] + node _T_1911 = mux(_T_1902, _T_1894, _T_1900) @[Edges.scala 214:21] + _T_1896 <= _T_1911 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1913 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1915 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1917 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1919 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1921 : UInt, clock @[CoreplexNetwork.scala 134:12] + node _T_1923 = eq(_T_1902, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1924 = and(io.in[0].a.valid, _T_1923) @[CoreplexNetwork.scala 134:12] + when _T_1924 : @[CoreplexNetwork.scala 134:12] + node _T_1925 = eq(io.in[0].a.bits.opcode, _T_1913) @[CoreplexNetwork.scala 134:12] + node _T_1926 = or(_T_1925, reset) @[CoreplexNetwork.scala 134:12] + node _T_1928 = eq(_T_1926, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1928 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1929 = eq(io.in[0].a.bits.param, _T_1915) @[CoreplexNetwork.scala 134:12] + node _T_1930 = or(_T_1929, reset) @[CoreplexNetwork.scala 134:12] + node _T_1932 = eq(_T_1930, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1932 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1933 = eq(io.in[0].a.bits.size, _T_1917) @[CoreplexNetwork.scala 134:12] + node _T_1934 = or(_T_1933, reset) @[CoreplexNetwork.scala 134:12] + node _T_1936 = eq(_T_1934, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1936 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1937 = eq(io.in[0].a.bits.source, _T_1919) @[CoreplexNetwork.scala 134:12] + node _T_1938 = or(_T_1937, reset) @[CoreplexNetwork.scala 134:12] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1940 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1941 = eq(io.in[0].a.bits.address, _T_1921) @[CoreplexNetwork.scala 134:12] + node _T_1942 = or(_T_1941, reset) @[CoreplexNetwork.scala 134:12] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1944 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1945 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1946 = and(_T_1945, _T_1902) @[CoreplexNetwork.scala 134:12] + when _T_1946 : @[CoreplexNetwork.scala 134:12] + _T_1913 <= io.in[0].a.bits.opcode @[CoreplexNetwork.scala 134:12] + _T_1915 <= io.in[0].a.bits.param @[CoreplexNetwork.scala 134:12] + _T_1917 <= io.in[0].a.bits.size @[CoreplexNetwork.scala 134:12] + _T_1919 <= io.in[0].a.bits.source @[CoreplexNetwork.scala 134:12] + _T_1921 <= io.in[0].a.bits.address @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1947 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1949 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1950 = dshl(_T_1949, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1951 = bits(_T_1950, 7, 0) @[package.scala 19:76] + node _T_1952 = not(_T_1951) @[package.scala 19:40] + node _T_1953 = shr(_T_1952, 3) @[Edges.scala 198:59] + node _T_1954 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1956 = eq(_T_1954, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1959 = mux(UInt<1>("h00"), _T_1953, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1961 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1963 = sub(_T_1961, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1964 = asUInt(_T_1963) @[Edges.scala 208:28] + node _T_1965 = tail(_T_1964, 1) @[Edges.scala 208:28] + node _T_1967 = eq(_T_1961, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1969 = eq(_T_1961, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1971 = eq(_T_1959, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1972 = or(_T_1969, _T_1971) @[Edges.scala 210:37] + node _T_1973 = and(_T_1972, _T_1947) @[Edges.scala 211:22] + node _T_1974 = not(_T_1965) @[Edges.scala 212:27] + node _T_1975 = and(_T_1959, _T_1974) @[Edges.scala 212:25] + when _T_1947 : @[Edges.scala 213:17] + node _T_1976 = mux(_T_1967, _T_1959, _T_1965) @[Edges.scala 214:21] + _T_1961 <= _T_1976 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1978 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1980 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1982 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1984 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_1986 : UInt, clock @[CoreplexNetwork.scala 134:12] + node _T_1988 = eq(_T_1967, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_1989 = and(io.in[0].b.valid, _T_1988) @[CoreplexNetwork.scala 134:12] + when _T_1989 : @[CoreplexNetwork.scala 134:12] + node _T_1990 = eq(io.in[0].b.bits.opcode, _T_1978) @[CoreplexNetwork.scala 134:12] + node _T_1991 = or(_T_1990, reset) @[CoreplexNetwork.scala 134:12] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1993 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1994 = eq(io.in[0].b.bits.param, _T_1980) @[CoreplexNetwork.scala 134:12] + node _T_1995 = or(_T_1994, reset) @[CoreplexNetwork.scala 134:12] + node _T_1997 = eq(_T_1995, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_1997 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_1998 = eq(io.in[0].b.bits.size, _T_1982) @[CoreplexNetwork.scala 134:12] + node _T_1999 = or(_T_1998, reset) @[CoreplexNetwork.scala 134:12] + node _T_2001 = eq(_T_1999, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2001 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2002 = eq(io.in[0].b.bits.source, _T_1984) @[CoreplexNetwork.scala 134:12] + node _T_2003 = or(_T_2002, reset) @[CoreplexNetwork.scala 134:12] + node _T_2005 = eq(_T_2003, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2005 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2006 = eq(io.in[0].b.bits.address, _T_1986) @[CoreplexNetwork.scala 134:12] + node _T_2007 = or(_T_2006, reset) @[CoreplexNetwork.scala 134:12] + node _T_2009 = eq(_T_2007, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2009 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2010 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2011 = and(_T_2010, _T_1967) @[CoreplexNetwork.scala 134:12] + when _T_2011 : @[CoreplexNetwork.scala 134:12] + _T_1978 <= io.in[0].b.bits.opcode @[CoreplexNetwork.scala 134:12] + _T_1980 <= io.in[0].b.bits.param @[CoreplexNetwork.scala 134:12] + _T_1982 <= io.in[0].b.bits.size @[CoreplexNetwork.scala 134:12] + _T_1984 <= io.in[0].b.bits.source @[CoreplexNetwork.scala 134:12] + _T_1986 <= io.in[0].b.bits.address @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2012 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2014 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2015 = dshl(_T_2014, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2016 = bits(_T_2015, 7, 0) @[package.scala 19:76] + node _T_2017 = not(_T_2016) @[package.scala 19:40] + node _T_2018 = shr(_T_2017, 3) @[Edges.scala 198:59] + node _T_2019 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2022 = mux(UInt<1>("h00"), _T_2018, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2024 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2026 = sub(_T_2024, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2027 = asUInt(_T_2026) @[Edges.scala 208:28] + node _T_2028 = tail(_T_2027, 1) @[Edges.scala 208:28] + node _T_2030 = eq(_T_2024, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2032 = eq(_T_2024, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2034 = eq(_T_2022, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2035 = or(_T_2032, _T_2034) @[Edges.scala 210:37] + node _T_2036 = and(_T_2035, _T_2012) @[Edges.scala 211:22] + node _T_2037 = not(_T_2028) @[Edges.scala 212:27] + node _T_2038 = and(_T_2022, _T_2037) @[Edges.scala 212:25] + when _T_2012 : @[Edges.scala 213:17] + node _T_2039 = mux(_T_2030, _T_2022, _T_2028) @[Edges.scala 214:21] + _T_2024 <= _T_2039 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2041 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2043 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2045 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2047 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2049 : UInt, clock @[CoreplexNetwork.scala 134:12] + node _T_2051 = eq(_T_2030, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_2052 = and(io.in[0].c.valid, _T_2051) @[CoreplexNetwork.scala 134:12] + when _T_2052 : @[CoreplexNetwork.scala 134:12] + node _T_2053 = eq(io.in[0].c.bits.opcode, _T_2041) @[CoreplexNetwork.scala 134:12] + node _T_2054 = or(_T_2053, reset) @[CoreplexNetwork.scala 134:12] + node _T_2056 = eq(_T_2054, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2056 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2057 = eq(io.in[0].c.bits.param, _T_2043) @[CoreplexNetwork.scala 134:12] + node _T_2058 = or(_T_2057, reset) @[CoreplexNetwork.scala 134:12] + node _T_2060 = eq(_T_2058, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2060 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2061 = eq(io.in[0].c.bits.size, _T_2045) @[CoreplexNetwork.scala 134:12] + node _T_2062 = or(_T_2061, reset) @[CoreplexNetwork.scala 134:12] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2064 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2065 = eq(io.in[0].c.bits.source, _T_2047) @[CoreplexNetwork.scala 134:12] + node _T_2066 = or(_T_2065, reset) @[CoreplexNetwork.scala 134:12] + node _T_2068 = eq(_T_2066, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2068 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2069 = eq(io.in[0].c.bits.address, _T_2049) @[CoreplexNetwork.scala 134:12] + node _T_2070 = or(_T_2069, reset) @[CoreplexNetwork.scala 134:12] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2072 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2073 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2074 = and(_T_2073, _T_2030) @[CoreplexNetwork.scala 134:12] + when _T_2074 : @[CoreplexNetwork.scala 134:12] + _T_2041 <= io.in[0].c.bits.opcode @[CoreplexNetwork.scala 134:12] + _T_2043 <= io.in[0].c.bits.param @[CoreplexNetwork.scala 134:12] + _T_2045 <= io.in[0].c.bits.size @[CoreplexNetwork.scala 134:12] + _T_2047 <= io.in[0].c.bits.source @[CoreplexNetwork.scala 134:12] + _T_2049 <= io.in[0].c.bits.address @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2075 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2077 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2078 = dshl(_T_2077, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2079 = bits(_T_2078, 7, 0) @[package.scala 19:76] + node _T_2080 = not(_T_2079) @[package.scala 19:40] + node _T_2081 = shr(_T_2080, 3) @[Edges.scala 198:59] + node _T_2082 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2084 = mux(_T_2082, _T_2081, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2086 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2088 = sub(_T_2086, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2089 = asUInt(_T_2088) @[Edges.scala 208:28] + node _T_2090 = tail(_T_2089, 1) @[Edges.scala 208:28] + node _T_2092 = eq(_T_2086, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2094 = eq(_T_2086, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2096 = eq(_T_2084, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2097 = or(_T_2094, _T_2096) @[Edges.scala 210:37] + node _T_2098 = and(_T_2097, _T_2075) @[Edges.scala 211:22] + node _T_2099 = not(_T_2090) @[Edges.scala 212:27] + node _T_2100 = and(_T_2084, _T_2099) @[Edges.scala 212:25] + when _T_2075 : @[Edges.scala 213:17] + node _T_2101 = mux(_T_2092, _T_2084, _T_2090) @[Edges.scala 214:21] + _T_2086 <= _T_2101 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2103 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2105 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2107 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2109 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2111 : UInt, clock @[CoreplexNetwork.scala 134:12] + reg _T_2113 : UInt, clock @[CoreplexNetwork.scala 134:12] + node _T_2115 = eq(_T_2092, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_2116 = and(io.in[0].d.valid, _T_2115) @[CoreplexNetwork.scala 134:12] + when _T_2116 : @[CoreplexNetwork.scala 134:12] + node _T_2117 = eq(io.in[0].d.bits.opcode, _T_2103) @[CoreplexNetwork.scala 134:12] + node _T_2118 = or(_T_2117, reset) @[CoreplexNetwork.scala 134:12] + node _T_2120 = eq(_T_2118, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2120 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2121 = eq(io.in[0].d.bits.param, _T_2105) @[CoreplexNetwork.scala 134:12] + node _T_2122 = or(_T_2121, reset) @[CoreplexNetwork.scala 134:12] + node _T_2124 = eq(_T_2122, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2124 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2125 = eq(io.in[0].d.bits.size, _T_2107) @[CoreplexNetwork.scala 134:12] + node _T_2126 = or(_T_2125, reset) @[CoreplexNetwork.scala 134:12] + node _T_2128 = eq(_T_2126, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2128 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2129 = eq(io.in[0].d.bits.source, _T_2109) @[CoreplexNetwork.scala 134:12] + node _T_2130 = or(_T_2129, reset) @[CoreplexNetwork.scala 134:12] + node _T_2132 = eq(_T_2130, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2132 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2133 = eq(io.in[0].d.bits.sink, _T_2111) @[CoreplexNetwork.scala 134:12] + node _T_2134 = or(_T_2133, reset) @[CoreplexNetwork.scala 134:12] + node _T_2136 = eq(_T_2134, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2136 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2137 = eq(io.in[0].d.bits.addr_lo, _T_2113) @[CoreplexNetwork.scala 134:12] + node _T_2138 = or(_T_2137, reset) @[CoreplexNetwork.scala 134:12] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2140 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2141 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2142 = and(_T_2141, _T_2092) @[CoreplexNetwork.scala 134:12] + when _T_2142 : @[CoreplexNetwork.scala 134:12] + _T_2103 <= io.in[0].d.bits.opcode @[CoreplexNetwork.scala 134:12] + _T_2105 <= io.in[0].d.bits.param @[CoreplexNetwork.scala 134:12] + _T_2107 <= io.in[0].d.bits.size @[CoreplexNetwork.scala 134:12] + _T_2109 <= io.in[0].d.bits.source @[CoreplexNetwork.scala 134:12] + _T_2111 <= io.in[0].d.bits.sink @[CoreplexNetwork.scala 134:12] + _T_2113 <= io.in[0].d.bits.addr_lo @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + reg _T_2144 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_2145 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2147 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2148 = dshl(_T_2147, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2149 = bits(_T_2148, 7, 0) @[package.scala 19:76] + node _T_2150 = not(_T_2149) @[package.scala 19:40] + node _T_2151 = shr(_T_2150, 3) @[Edges.scala 198:59] + node _T_2152 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2154 = eq(_T_2152, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2156 = mux(_T_2154, _T_2151, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2158 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2160 = sub(_T_2158, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2161 = asUInt(_T_2160) @[Edges.scala 208:28] + node _T_2162 = tail(_T_2161, 1) @[Edges.scala 208:28] + node _T_2164 = eq(_T_2158, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2166 = eq(_T_2158, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2168 = eq(_T_2156, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2169 = or(_T_2166, _T_2168) @[Edges.scala 210:37] + node _T_2170 = and(_T_2169, _T_2145) @[Edges.scala 211:22] + node _T_2171 = not(_T_2162) @[Edges.scala 212:27] + node _T_2172 = and(_T_2156, _T_2171) @[Edges.scala 212:25] + when _T_2145 : @[Edges.scala 213:17] + node _T_2173 = mux(_T_2164, _T_2156, _T_2162) @[Edges.scala 214:21] + _T_2158 <= _T_2173 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2174 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2176 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2177 = dshl(_T_2176, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2178 = bits(_T_2177, 7, 0) @[package.scala 19:76] + node _T_2179 = not(_T_2178) @[package.scala 19:40] + node _T_2180 = shr(_T_2179, 3) @[Edges.scala 198:59] + node _T_2181 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2183 = mux(_T_2181, _T_2180, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2185 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2187 = sub(_T_2185, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2188 = asUInt(_T_2187) @[Edges.scala 208:28] + node _T_2189 = tail(_T_2188, 1) @[Edges.scala 208:28] + node _T_2191 = eq(_T_2185, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2193 = eq(_T_2185, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2195 = eq(_T_2183, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2196 = or(_T_2193, _T_2195) @[Edges.scala 210:37] + node _T_2197 = and(_T_2196, _T_2174) @[Edges.scala 211:22] + node _T_2198 = not(_T_2189) @[Edges.scala 212:27] + node _T_2199 = and(_T_2183, _T_2198) @[Edges.scala 212:25] + when _T_2174 : @[Edges.scala 213:17] + node _T_2200 = mux(_T_2191, _T_2183, _T_2189) @[Edges.scala 214:21] + _T_2185 <= _T_2200 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2202 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + node _T_2203 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[CoreplexNetwork.scala 134:12] + node _T_2204 = or(_T_2202, _T_2203) @[CoreplexNetwork.scala 134:12] + node _T_2206 = eq(io.in[0].a.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_2207 = or(_T_2204, _T_2206) @[CoreplexNetwork.scala 134:12] + node _T_2209 = eq(io.in[0].d.valid, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_2210 = or(_T_2207, _T_2209) @[CoreplexNetwork.scala 134:12] + node _T_2211 = or(_T_2210, reset) @[CoreplexNetwork.scala 134:12] + node _T_2213 = eq(_T_2211, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2213 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + wire _T_2215 : UInt<32> + _T_2215 is invalid + _T_2215 <= UInt<32>("h00") + node _T_2216 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2216 : @[CoreplexNetwork.scala 134:12] + when _T_2169 : @[CoreplexNetwork.scala 134:12] + node _T_2218 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2215 <= _T_2218 @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2219 = dshr(_T_2144, io.in[0].a.bits.source) @[CoreplexNetwork.scala 134:12] + node _T_2220 = bits(_T_2219, 0, 0) @[CoreplexNetwork.scala 134:12] + node _T_2222 = eq(_T_2220, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + node _T_2223 = or(_T_2222, reset) @[CoreplexNetwork.scala 134:12] + node _T_2225 = eq(_T_2223, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2225 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + wire _T_2227 : UInt<32> + _T_2227 is invalid + _T_2227 <= UInt<32>("h00") + node _T_2228 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2230 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[CoreplexNetwork.scala 134:12] + node _T_2231 = and(_T_2228, _T_2230) @[CoreplexNetwork.scala 134:12] + when _T_2231 : @[CoreplexNetwork.scala 134:12] + when _T_2196 : @[CoreplexNetwork.scala 134:12] + node _T_2233 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2227 <= _T_2233 @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2234 = or(_T_2215, _T_2144) @[CoreplexNetwork.scala 134:12] + node _T_2235 = dshr(_T_2234, io.in[0].d.bits.source) @[CoreplexNetwork.scala 134:12] + node _T_2236 = bits(_T_2235, 0, 0) @[CoreplexNetwork.scala 134:12] + node _T_2237 = or(_T_2236, reset) @[CoreplexNetwork.scala 134:12] + node _T_2239 = eq(_T_2237, UInt<1>("h00")) @[CoreplexNetwork.scala 134:12] + when _T_2239 : @[CoreplexNetwork.scala 134:12] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CoreplexNetwork.scala:134:12)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[CoreplexNetwork.scala 134:12] + stop(clock, UInt<1>(1), 1) @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + skip @[CoreplexNetwork.scala 134:12] + node _T_2240 = or(_T_2144, _T_2215) @[CoreplexNetwork.scala 134:12] + node _T_2241 = not(_T_2227) @[CoreplexNetwork.scala 134:12] + node _T_2242 = and(_T_2240, _T_2241) @[CoreplexNetwork.scala 134:12] + _T_2144 <= _T_2242 @[CoreplexNetwork.scala 134:12] + + module TLDebugModule_debug : + input clock : Clock + input reset : UInt<1> + output io : {interrupts : {}, flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, flip db : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}}, debugInterrupts : UInt<1>[1], ndreset : UInt<1>, fullreset : UInt<1>} + + io is invalid + io is invalid + wire CONTROLReset : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 459:26] + CONTROLReset is invalid @[Debug.scala 459:26] + wire CONTROLWrEn : UInt<1> @[Debug.scala 460:25] + CONTROLWrEn is invalid @[Debug.scala 460:25] + reg CONTROLReg : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>}, clock @[Debug.scala 461:23] + wire CONTROLWrData : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 462:28] + CONTROLWrData is invalid @[Debug.scala 462:28] + wire CONTROLRdData : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 463:28] + CONTROLRdData is invalid @[Debug.scala 463:28] + reg ndresetCtrReg : UInt<1>, clock @[Debug.scala 464:26] + wire DMINFORdData : {reserved0 : UInt<2>, abussize : UInt<7>, serialcount : UInt<4>, access128 : UInt<1>, access64 : UInt<1>, access32 : UInt<1>, access16 : UInt<1>, accesss8 : UInt<1>, dramsize : UInt<6>, haltsum : UInt<1>, reserved1 : UInt<3>, authenticated : UInt<1>, authbusy : UInt<1>, authtype : UInt<2>, version : UInt<2>} @[Debug.scala 466:27] + DMINFORdData is invalid @[Debug.scala 466:27] + wire HALTSUMRdData : {serialfull : UInt<1>, serialvalid : UInt<1>, acks : UInt<32>} @[Debug.scala 468:28] + HALTSUMRdData is invalid @[Debug.scala 468:28] + wire RAMWrData : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 470:24] + RAMWrData is invalid @[Debug.scala 470:24] + wire RAMRdData : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 471:24] + RAMRdData is invalid @[Debug.scala 471:24] + wire SETHALTNOTWrEn : UInt<1> @[Debug.scala 475:28] + SETHALTNOTWrEn is invalid @[Debug.scala 475:28] + wire SETHALTNOTWrData : UInt<10> @[Debug.scala 476:30] + SETHALTNOTWrData is invalid @[Debug.scala 476:30] + wire CLEARDEBINTWrEn : UInt<1> @[Debug.scala 477:29] + CLEARDEBINTWrEn is invalid @[Debug.scala 477:29] + wire CLEARDEBINTWrData : UInt<10> @[Debug.scala 478:31] + CLEARDEBINTWrData is invalid @[Debug.scala 478:31] + wire _T_599 : UInt<1>[1] @[Debug.scala 482:57] + _T_599 is invalid @[Debug.scala 482:57] + _T_599[0] <= UInt<1>("h00") @[Debug.scala 482:57] + reg interruptRegs : UInt<1>[1], clock with : (reset => (reset, _T_599)) @[Debug.scala 482:26] + wire _T_611 : UInt<1>[1] @[Debug.scala 484:59] + _T_611 is invalid @[Debug.scala 484:59] + _T_611[0] <= UInt<1>("h00") @[Debug.scala 484:59] + reg haltnotRegs : UInt<1>[1], clock with : (reset => (reset, _T_611)) @[Debug.scala 484:28] + wire haltnotStatus : UInt<32>[1] @[Debug.scala 487:27] + haltnotStatus is invalid @[Debug.scala 487:27] + wire rdHaltnotStatus : UInt<32> @[Debug.scala 488:29] + rdHaltnotStatus is invalid @[Debug.scala 488:29] + node haltnotSummary = neq(haltnotStatus[0], UInt<1>("h00")) @[Debug.scala 490:48] + wire _T_694 : UInt<8>[64] @[Debug.scala 498:58] + _T_694 is invalid @[Debug.scala 498:58] + _T_694[0] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[1] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[2] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[3] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[4] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[5] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[6] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[7] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[8] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[9] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[10] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[11] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[12] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[13] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[14] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[15] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[16] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[17] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[18] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[19] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[20] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[21] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[22] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[23] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[24] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[25] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[26] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[27] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[28] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[29] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[30] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[31] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[32] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[33] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[34] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[35] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[36] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[37] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[38] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[39] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[40] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[41] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[42] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[43] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[44] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[45] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[46] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[47] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[48] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[49] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[50] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[51] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[52] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[53] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[54] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[55] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[56] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[57] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[58] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[59] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[60] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[61] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[62] <= UInt<8>("h00") @[Debug.scala 498:58] + _T_694[63] <= UInt<8>("h00") @[Debug.scala 498:58] + reg ramMem : UInt<8>[64], clock with : (reset => (reset, _T_694)) @[Debug.scala 498:22] + wire dbRamAddr : UInt<4> @[Debug.scala 500:25] + dbRamAddr is invalid @[Debug.scala 500:25] + wire dbRamAddrValid : UInt<1> @[Debug.scala 501:30] + dbRamAddrValid is invalid @[Debug.scala 501:30] + wire dbRamRdData : UInt<32> @[Debug.scala 502:26] + dbRamRdData is invalid @[Debug.scala 502:26] + wire dbRamWrData : UInt<32> @[Debug.scala 503:25] + dbRamWrData is invalid @[Debug.scala 503:25] + wire dbRamWrEn : UInt<1> @[Debug.scala 504:25] + dbRamWrEn is invalid @[Debug.scala 504:25] + wire dbRamRdEn : UInt<1> @[Debug.scala 505:25] + dbRamRdEn is invalid @[Debug.scala 505:25] + wire dbRamWrEnFinal : UInt<1> @[Debug.scala 506:30] + dbRamWrEnFinal is invalid @[Debug.scala 506:30] + wire dbRamRdEnFinal : UInt<1> @[Debug.scala 507:30] + dbRamRdEnFinal is invalid @[Debug.scala 507:30] + wire dbRdEn : UInt<1> @[Debug.scala 514:22] + dbRdEn is invalid @[Debug.scala 514:22] + wire dbWrEn : UInt<1> @[Debug.scala 515:22] + dbWrEn is invalid @[Debug.scala 515:22] + wire dbRdData : UInt<34> @[Debug.scala 516:22] + dbRdData is invalid @[Debug.scala 516:22] + reg dbStateReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Debug.scala 519:23] + wire dbResult : {data : UInt<34>, resp : UInt<2>} @[Debug.scala 521:23] + dbResult is invalid @[Debug.scala 521:23] + wire dbReq : {addr : UInt<5>, data : UInt<34>, op : UInt<2>} @[Debug.scala 523:23] + dbReq is invalid @[Debug.scala 523:23] + reg dbRespReg : {data : UInt<34>, resp : UInt<2>}, clock @[Debug.scala 524:22] + wire rdCondWrFailure : UInt<1> @[Debug.scala 526:29] + rdCondWrFailure is invalid @[Debug.scala 526:29] + wire dbWrNeeded : UInt<1> @[Debug.scala 527:24] + dbWrNeeded is invalid @[Debug.scala 527:24] + io.debugInterrupts[0] <= interruptRegs[0] @[Debug.scala 534:35] + when CONTROLWrEn : @[Debug.scala 544:24] + node _T_914 = eq(CONTROLWrData.hartid, UInt<1>("h00")) @[Debug.scala 545:34] + when _T_914 : @[Debug.scala 545:55] + node _T_915 = or(interruptRegs[0], CONTROLWrData.interrupt) @[Debug.scala 546:62] + interruptRegs[0] <= _T_915 @[Debug.scala 546:34] + skip @[Debug.scala 545:55] + skip @[Debug.scala 544:24] + node _T_917 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 544:24] + node _T_918 = and(_T_917, dbRamWrEn) @[Debug.scala 548:28] + when _T_918 : @[Debug.scala 548:28] + node _T_920 = eq(CONTROLReg.hartid, UInt<1>("h00")) @[Debug.scala 549:31] + when _T_920 : @[Debug.scala 549:51] + node _T_921 = or(interruptRegs[0], RAMWrData.interrupt) @[Debug.scala 550:63] + interruptRegs[0] <= _T_921 @[Debug.scala 550:34] + skip @[Debug.scala 549:51] + skip @[Debug.scala 548:28] + node _T_923 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 544:24] + node _T_925 = eq(dbRamWrEn, UInt<1>("h00")) @[Debug.scala 548:28] + node _T_926 = and(_T_923, _T_925) @[Debug.scala 548:28] + node _T_927 = and(_T_926, CLEARDEBINTWrEn) @[Debug.scala 552:33] + when _T_927 : @[Debug.scala 552:33] + node _T_929 = eq(CLEARDEBINTWrData, UInt<10>("h00")) @[Debug.scala 553:31] + when _T_929 : @[Debug.scala 553:71] + interruptRegs[0] <= UInt<1>("h00") @[Debug.scala 554:34] + skip @[Debug.scala 553:71] + skip @[Debug.scala 552:33] + when SETHALTNOTWrEn : @[Debug.scala 570:26] + node _T_932 = eq(SETHALTNOTWrData, UInt<10>("h00")) @[Debug.scala 571:30] + when _T_932 : @[Debug.scala 571:70] + haltnotRegs[0] <= UInt<1>("h01") @[Debug.scala 572:32] + skip @[Debug.scala 571:70] + skip @[Debug.scala 570:26] + node _T_935 = eq(SETHALTNOTWrEn, UInt<1>("h00")) @[Debug.scala 570:26] + node _T_936 = and(_T_935, CONTROLWrEn) @[Debug.scala 574:31] + when _T_936 : @[Debug.scala 574:31] + node _T_938 = eq(CONTROLWrData.hartid, UInt<1>("h00")) @[Debug.scala 575:34] + when _T_938 : @[Debug.scala 575:55] + node _T_939 = and(haltnotRegs[0], CONTROLWrData.haltnot) @[Debug.scala 576:58] + haltnotRegs[0] <= _T_939 @[Debug.scala 576:32] + skip @[Debug.scala 575:55] + skip @[Debug.scala 574:31] + node _T_941 = eq(SETHALTNOTWrEn, UInt<1>("h00")) @[Debug.scala 570:26] + node _T_943 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 574:31] + node _T_944 = and(_T_941, _T_943) @[Debug.scala 574:31] + node _T_945 = and(_T_944, dbRamWrEn) @[Debug.scala 578:28] + when _T_945 : @[Debug.scala 578:28] + node _T_947 = eq(CONTROLReg.hartid, UInt<1>("h00")) @[Debug.scala 579:31] + when _T_947 : @[Debug.scala 579:51] + node _T_948 = and(haltnotRegs[0], RAMWrData.haltnot) @[Debug.scala 580:59] + haltnotRegs[0] <= _T_948 @[Debug.scala 580:32] + skip @[Debug.scala 579:51] + skip @[Debug.scala 578:28] + haltnotStatus[0] <= haltnotRegs[0] @[Debug.scala 586:23] + CONTROLReset.interrupt <= UInt<1>("h00") @[Debug.scala 593:30] + CONTROLReset.haltnot <= UInt<1>("h00") @[Debug.scala 594:30] + CONTROLReset.reserved0 <= UInt<1>("h00") @[Debug.scala 595:30] + CONTROLReset.buserror <= UInt<1>("h00") @[Debug.scala 596:30] + CONTROLReset.serial <= UInt<1>("h00") @[Debug.scala 597:30] + CONTROLReset.autoincrement <= UInt<1>("h00") @[Debug.scala 598:30] + CONTROLReset.access <= UInt<2>("h02") @[Debug.scala 599:30] + CONTROLReset.hartid <= UInt<1>("h00") @[Debug.scala 600:30] + CONTROLReset.ndreset <= UInt<1>("h00") @[Debug.scala 601:30] + CONTROLReset.fullreset <= UInt<1>("h00") @[Debug.scala 602:30] + DMINFORdData.reserved0 <= UInt<1>("h00") @[Debug.scala 607:30] + DMINFORdData.abussize <= UInt<1>("h00") @[Debug.scala 608:30] + DMINFORdData.serialcount <= UInt<1>("h00") @[Debug.scala 609:30] + DMINFORdData.access128 <= UInt<1>("h00") @[Debug.scala 610:30] + DMINFORdData.access64 <= UInt<1>("h00") @[Debug.scala 611:30] + DMINFORdData.access32 <= UInt<1>("h00") @[Debug.scala 612:30] + DMINFORdData.access16 <= UInt<1>("h00") @[Debug.scala 613:30] + DMINFORdData.accesss8 <= UInt<1>("h00") @[Debug.scala 614:30] + DMINFORdData.dramsize <= UInt<4>("h0f") @[Debug.scala 615:30] + DMINFORdData.haltsum <= UInt<1>("h00") @[Debug.scala 616:30] + DMINFORdData.reserved1 <= UInt<1>("h00") @[Debug.scala 617:30] + DMINFORdData.authenticated <= UInt<1>("h01") @[Debug.scala 618:30] + DMINFORdData.authbusy <= UInt<1>("h00") @[Debug.scala 619:30] + DMINFORdData.authtype <= UInt<1>("h00") @[Debug.scala 620:30] + DMINFORdData.version <= UInt<1>("h01") @[Debug.scala 621:30] + HALTSUMRdData.serialfull <= UInt<1>("h00") @[Debug.scala 623:29] + HALTSUMRdData.serialvalid <= UInt<1>("h00") @[Debug.scala 624:29] + HALTSUMRdData.acks <= haltnotSummary @[Debug.scala 625:29] + dbReq <- io.db.req.bits @[Debug.scala 631:9] + node _T_976 = bits(dbReq.addr, 3, 0) @[Debug.scala 635:28] + dbRamAddr <= _T_976 @[Debug.scala 635:15] + dbRamWrData <= dbReq.data @[Debug.scala 636:15] + node _T_977 = bits(dbReq.addr, 3, 0) @[Debug.scala 637:32] + node _T_979 = leq(_T_977, UInt<5>("h010")) @[Debug.scala 637:38] + dbRamAddrValid <= _T_979 @[Debug.scala 637:18] + node _T_980 = cat(ramMem[1], ramMem[0]) @[Cat.scala 30:58] + node _T_981 = cat(ramMem[2], _T_980) @[Cat.scala 30:58] + node dbRamRdDataFields_0 = cat(ramMem[3], _T_981) @[Cat.scala 30:58] + node _T_982 = cat(ramMem[5], ramMem[4]) @[Cat.scala 30:58] + node _T_983 = cat(ramMem[6], _T_982) @[Cat.scala 30:58] + node dbRamRdDataFields_1 = cat(ramMem[7], _T_983) @[Cat.scala 30:58] + node _T_984 = cat(ramMem[9], ramMem[8]) @[Cat.scala 30:58] + node _T_985 = cat(ramMem[10], _T_984) @[Cat.scala 30:58] + node dbRamRdDataFields_2 = cat(ramMem[11], _T_985) @[Cat.scala 30:58] + node _T_986 = cat(ramMem[13], ramMem[12]) @[Cat.scala 30:58] + node _T_987 = cat(ramMem[14], _T_986) @[Cat.scala 30:58] + node dbRamRdDataFields_3 = cat(ramMem[15], _T_987) @[Cat.scala 30:58] + node _T_988 = cat(ramMem[17], ramMem[16]) @[Cat.scala 30:58] + node _T_989 = cat(ramMem[18], _T_988) @[Cat.scala 30:58] + node dbRamRdDataFields_4 = cat(ramMem[19], _T_989) @[Cat.scala 30:58] + node _T_990 = cat(ramMem[21], ramMem[20]) @[Cat.scala 30:58] + node _T_991 = cat(ramMem[22], _T_990) @[Cat.scala 30:58] + node dbRamRdDataFields_5 = cat(ramMem[23], _T_991) @[Cat.scala 30:58] + node _T_992 = cat(ramMem[25], ramMem[24]) @[Cat.scala 30:58] + node _T_993 = cat(ramMem[26], _T_992) @[Cat.scala 30:58] + node dbRamRdDataFields_6 = cat(ramMem[27], _T_993) @[Cat.scala 30:58] + node _T_994 = cat(ramMem[29], ramMem[28]) @[Cat.scala 30:58] + node _T_995 = cat(ramMem[30], _T_994) @[Cat.scala 30:58] + node dbRamRdDataFields_7 = cat(ramMem[31], _T_995) @[Cat.scala 30:58] + node _T_996 = cat(ramMem[33], ramMem[32]) @[Cat.scala 30:58] + node _T_997 = cat(ramMem[34], _T_996) @[Cat.scala 30:58] + node dbRamRdDataFields_8 = cat(ramMem[35], _T_997) @[Cat.scala 30:58] + node _T_998 = cat(ramMem[37], ramMem[36]) @[Cat.scala 30:58] + node _T_999 = cat(ramMem[38], _T_998) @[Cat.scala 30:58] + node dbRamRdDataFields_9 = cat(ramMem[39], _T_999) @[Cat.scala 30:58] + node _T_1000 = cat(ramMem[41], ramMem[40]) @[Cat.scala 30:58] + node _T_1001 = cat(ramMem[42], _T_1000) @[Cat.scala 30:58] + node dbRamRdDataFields_10 = cat(ramMem[43], _T_1001) @[Cat.scala 30:58] + node _T_1002 = cat(ramMem[45], ramMem[44]) @[Cat.scala 30:58] + node _T_1003 = cat(ramMem[46], _T_1002) @[Cat.scala 30:58] + node dbRamRdDataFields_11 = cat(ramMem[47], _T_1003) @[Cat.scala 30:58] + node _T_1004 = cat(ramMem[49], ramMem[48]) @[Cat.scala 30:58] + node _T_1005 = cat(ramMem[50], _T_1004) @[Cat.scala 30:58] + node dbRamRdDataFields_12 = cat(ramMem[51], _T_1005) @[Cat.scala 30:58] + node _T_1006 = cat(ramMem[53], ramMem[52]) @[Cat.scala 30:58] + node _T_1007 = cat(ramMem[54], _T_1006) @[Cat.scala 30:58] + node dbRamRdDataFields_13 = cat(ramMem[55], _T_1007) @[Cat.scala 30:58] + node _T_1008 = cat(ramMem[57], ramMem[56]) @[Cat.scala 30:58] + node _T_1009 = cat(ramMem[58], _T_1008) @[Cat.scala 30:58] + node dbRamRdDataFields_14 = cat(ramMem[59], _T_1009) @[Cat.scala 30:58] + node _T_1010 = cat(ramMem[61], ramMem[60]) @[Cat.scala 30:58] + node _T_1011 = cat(ramMem[62], _T_1010) @[Cat.scala 30:58] + node dbRamRdDataFields_15 = cat(ramMem[63], _T_1011) @[Cat.scala 30:58] + node _T_1013 = and(dbRamAddr, UInt<3>("h07")) @[Package.scala 18:26] + node _T_1015 = geq(dbRamAddr, UInt<4>("h08")) @[Package.scala 19:17] + node _T_1017 = and(_T_1013, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1019 = geq(_T_1013, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1021 = and(_T_1017, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1023 = geq(_T_1017, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1025 = and(_T_1021, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1027 = geq(_T_1021, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1028 = mux(_T_1027, dbRamRdDataFields_15, dbRamRdDataFields_14) @[Package.scala 19:12] + node _T_1030 = and(_T_1021, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1032 = geq(_T_1021, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1033 = mux(_T_1032, dbRamRdDataFields_13, dbRamRdDataFields_12) @[Package.scala 19:12] + node _T_1034 = mux(_T_1023, _T_1028, _T_1033) @[Package.scala 19:12] + node _T_1036 = and(_T_1017, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1038 = geq(_T_1017, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1040 = and(_T_1036, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1042 = geq(_T_1036, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1043 = mux(_T_1042, dbRamRdDataFields_11, dbRamRdDataFields_10) @[Package.scala 19:12] + node _T_1045 = and(_T_1036, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1047 = geq(_T_1036, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1048 = mux(_T_1047, dbRamRdDataFields_9, dbRamRdDataFields_8) @[Package.scala 19:12] + node _T_1049 = mux(_T_1038, _T_1043, _T_1048) @[Package.scala 19:12] + node _T_1050 = mux(_T_1019, _T_1034, _T_1049) @[Package.scala 19:12] + node _T_1052 = and(_T_1013, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1054 = geq(_T_1013, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1056 = and(_T_1052, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1058 = geq(_T_1052, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1060 = and(_T_1056, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1062 = geq(_T_1056, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1063 = mux(_T_1062, dbRamRdDataFields_7, dbRamRdDataFields_6) @[Package.scala 19:12] + node _T_1065 = and(_T_1056, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1067 = geq(_T_1056, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1068 = mux(_T_1067, dbRamRdDataFields_5, dbRamRdDataFields_4) @[Package.scala 19:12] + node _T_1069 = mux(_T_1058, _T_1063, _T_1068) @[Package.scala 19:12] + node _T_1071 = and(_T_1052, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1073 = geq(_T_1052, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1075 = and(_T_1071, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1077 = geq(_T_1071, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1078 = mux(_T_1077, dbRamRdDataFields_3, dbRamRdDataFields_2) @[Package.scala 19:12] + node _T_1080 = and(_T_1071, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1082 = geq(_T_1071, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1083 = mux(_T_1082, dbRamRdDataFields_1, dbRamRdDataFields_0) @[Package.scala 19:12] + node _T_1084 = mux(_T_1073, _T_1078, _T_1083) @[Package.scala 19:12] + node _T_1085 = mux(_T_1054, _T_1069, _T_1084) @[Package.scala 19:12] + node _T_1086 = mux(_T_1015, _T_1050, _T_1085) @[Package.scala 19:12] + dbRamRdData <= _T_1086 @[Debug.scala 644:15] + when dbRamWrEnFinal : @[Debug.scala 646:25] + node _T_1088 = dshl(dbRamAddr, UInt<2>("h02")) @[Debug.scala 648:25] + node _T_1090 = add(_T_1088, UInt<1>("h00")) @[Debug.scala 648:51] + node _T_1091 = tail(_T_1090, 1) @[Debug.scala 648:51] + node _T_1094 = bits(_T_1091, 5, 0) + node _T_1095 = bits(dbRamWrData, 7, 0) @[Debug.scala 648:77] + ramMem[_T_1094] <= _T_1095 @[Debug.scala 648:63] + node _T_1097 = dshl(dbRamAddr, UInt<2>("h02")) @[Debug.scala 648:25] + node _T_1099 = add(_T_1097, UInt<1>("h01")) @[Debug.scala 648:51] + node _T_1100 = tail(_T_1099, 1) @[Debug.scala 648:51] + node _T_1103 = bits(_T_1100, 5, 0) + node _T_1104 = bits(dbRamWrData, 15, 8) @[Debug.scala 648:77] + ramMem[_T_1103] <= _T_1104 @[Debug.scala 648:63] + node _T_1106 = dshl(dbRamAddr, UInt<2>("h02")) @[Debug.scala 648:25] + node _T_1108 = add(_T_1106, UInt<2>("h02")) @[Debug.scala 648:51] + node _T_1109 = tail(_T_1108, 1) @[Debug.scala 648:51] + node _T_1112 = bits(_T_1109, 5, 0) + node _T_1113 = bits(dbRamWrData, 23, 16) @[Debug.scala 648:77] + ramMem[_T_1112] <= _T_1113 @[Debug.scala 648:63] + node _T_1115 = dshl(dbRamAddr, UInt<2>("h02")) @[Debug.scala 648:25] + node _T_1117 = add(_T_1115, UInt<2>("h03")) @[Debug.scala 648:51] + node _T_1118 = tail(_T_1117, 1) @[Debug.scala 648:51] + node _T_1121 = bits(_T_1118, 5, 0) + node _T_1122 = bits(dbRamWrData, 31, 24) @[Debug.scala 648:77] + ramMem[_T_1121] <= _T_1122 @[Debug.scala 648:63] + skip @[Debug.scala 646:25] + wire _T_1145 : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 666:48] + _T_1145 is invalid @[Debug.scala 666:48] + wire _T_1157 : UInt<34> + _T_1157 is invalid + _T_1157 <= dbReq.data + node _T_1158 = bits(_T_1157, 0, 0) @[Debug.scala 666:48] + _T_1145.fullreset <= _T_1158 @[Debug.scala 666:48] + node _T_1159 = bits(_T_1157, 1, 1) @[Debug.scala 666:48] + _T_1145.ndreset <= _T_1159 @[Debug.scala 666:48] + node _T_1160 = bits(_T_1157, 11, 2) @[Debug.scala 666:48] + _T_1145.hartid <= _T_1160 @[Debug.scala 666:48] + node _T_1161 = bits(_T_1157, 14, 12) @[Debug.scala 666:48] + _T_1145.access <= _T_1161 @[Debug.scala 666:48] + node _T_1162 = bits(_T_1157, 15, 15) @[Debug.scala 666:48] + _T_1145.autoincrement <= _T_1162 @[Debug.scala 666:48] + node _T_1163 = bits(_T_1157, 18, 16) @[Debug.scala 666:48] + _T_1145.serial <= _T_1163 @[Debug.scala 666:48] + node _T_1164 = bits(_T_1157, 21, 19) @[Debug.scala 666:48] + _T_1145.buserror <= _T_1164 @[Debug.scala 666:48] + node _T_1165 = bits(_T_1157, 31, 22) @[Debug.scala 666:48] + _T_1145.reserved0 <= _T_1165 @[Debug.scala 666:48] + node _T_1166 = bits(_T_1157, 32, 32) @[Debug.scala 666:48] + _T_1145.haltnot <= _T_1166 @[Debug.scala 666:48] + node _T_1167 = bits(_T_1157, 33, 33) @[Debug.scala 666:48] + _T_1145.interrupt <= _T_1167 @[Debug.scala 666:48] + CONTROLWrData <- _T_1145 @[Debug.scala 666:17] + wire _T_1176 : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 667:44] + _T_1176 is invalid @[Debug.scala 667:44] + wire _T_1181 : UInt<34> + _T_1181 is invalid + _T_1181 <= dbReq.data + node _T_1182 = bits(_T_1181, 31, 0) @[Debug.scala 667:44] + _T_1176.data <= _T_1182 @[Debug.scala 667:44] + node _T_1183 = bits(_T_1181, 32, 32) @[Debug.scala 667:44] + _T_1176.haltnot <= _T_1183 @[Debug.scala 667:44] + node _T_1184 = bits(_T_1181, 33, 33) @[Debug.scala 667:44] + _T_1176.interrupt <= _T_1184 @[Debug.scala 667:44] + RAMWrData <- _T_1176 @[Debug.scala 667:17] + dbRamWrEn <= UInt<1>("h00") @[Debug.scala 669:19] + dbRamWrEnFinal <= UInt<1>("h00") @[Debug.scala 670:19] + CONTROLWrEn <= UInt<1>("h00") @[Debug.scala 671:19] + node _T_1188 = shr(dbReq.addr, 4) @[Debug.scala 672:21] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[Debug.scala 672:27] + when _T_1190 : @[Debug.scala 672:40] + dbRamWrEn <= dbWrEn @[Debug.scala 673:15] + when dbRamAddrValid : @[Debug.scala 674:27] + dbRamWrEnFinal <= dbWrEn @[Debug.scala 675:22] + skip @[Debug.scala 674:27] + skip @[Debug.scala 672:40] + node _T_1192 = eq(dbReq.addr, UInt<5>("h010")) @[Debug.scala 677:26] + node _T_1194 = eq(_T_1190, UInt<1>("h00")) @[Debug.scala 672:40] + node _T_1195 = and(_T_1194, _T_1192) @[Debug.scala 677:41] + when _T_1195 : @[Debug.scala 677:41] + CONTROLWrEn <= dbWrEn @[Debug.scala 678:18] + skip @[Debug.scala 677:41] + node _T_1197 = eq(_T_1190, UInt<1>("h00")) @[Debug.scala 672:40] + node _T_1199 = eq(_T_1192, UInt<1>("h00")) @[Debug.scala 677:41] + node _T_1200 = and(_T_1197, _T_1199) @[Debug.scala 677:41] + when _T_1200 : @[Debug.scala 679:15] + skip @[Debug.scala 679:15] + when reset : @[Debug.scala 683:16] + CONTROLReg <- CONTROLReset @[Debug.scala 684:16] + ndresetCtrReg <= UInt<1>("h00") @[Debug.scala 685:19] + skip @[Debug.scala 683:16] + node _T_1203 = eq(reset, UInt<1>("h00")) @[Debug.scala 683:16] + node _T_1204 = and(_T_1203, CONTROLWrEn) @[Debug.scala 686:28] + when _T_1204 : @[Debug.scala 686:28] + CONTROLReg.hartid <= CONTROLWrData.hartid @[Debug.scala 698:30] + node _T_1205 = or(CONTROLReg.fullreset, CONTROLWrData.fullreset) @[Debug.scala 699:54] + CONTROLReg.fullreset <= _T_1205 @[Debug.scala 699:30] + when CONTROLWrData.ndreset : @[Debug.scala 700:33] + ndresetCtrReg <= UInt<1>("h01") @[Debug.scala 701:21] + skip @[Debug.scala 700:33] + node _T_1208 = eq(CONTROLWrData.ndreset, UInt<1>("h00")) @[Debug.scala 700:33] + when _T_1208 : @[Debug.scala 702:17] + node _T_1210 = eq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 703:42] + node _T_1213 = sub(ndresetCtrReg, UInt<1>("h01")) @[Debug.scala 703:79] + node _T_1214 = asUInt(_T_1213) @[Debug.scala 703:79] + node _T_1215 = tail(_T_1214, 1) @[Debug.scala 703:79] + node _T_1216 = mux(_T_1210, UInt<1>("h00"), _T_1215) @[Debug.scala 703:27] + ndresetCtrReg <= _T_1216 @[Debug.scala 703:21] + skip @[Debug.scala 702:17] + skip @[Debug.scala 686:28] + node _T_1218 = eq(reset, UInt<1>("h00")) @[Debug.scala 683:16] + node _T_1220 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 686:28] + node _T_1221 = and(_T_1218, _T_1220) @[Debug.scala 686:28] + when _T_1221 : @[Debug.scala 705:15] + node _T_1223 = eq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 706:40] + node _T_1226 = sub(ndresetCtrReg, UInt<1>("h01")) @[Debug.scala 706:77] + node _T_1227 = asUInt(_T_1226) @[Debug.scala 706:77] + node _T_1228 = tail(_T_1227, 1) @[Debug.scala 706:77] + node _T_1229 = mux(_T_1223, UInt<1>("h00"), _T_1228) @[Debug.scala 706:25] + ndresetCtrReg <= _T_1229 @[Debug.scala 706:19] + skip @[Debug.scala 705:15] + CONTROLRdData <- CONTROLReg @[Debug.scala 712:17] + CONTROLRdData.interrupt <= interruptRegs[UInt<1>("h00")] @[Debug.scala 713:27] + CONTROLRdData.haltnot <= haltnotRegs[UInt<1>("h00")] @[Debug.scala 714:27] + node _T_1237 = neq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 715:44] + CONTROLRdData.ndreset <= _T_1237 @[Debug.scala 715:27] + RAMRdData.interrupt <= interruptRegs[UInt<1>("h00")] @[Debug.scala 717:23] + RAMRdData.haltnot <= haltnotRegs[UInt<1>("h00")] @[Debug.scala 718:23] + RAMRdData.data <= dbRamRdData @[Debug.scala 719:23] + dbRdData <= UInt<1>("h00") @[Debug.scala 721:12] + rdHaltnotStatus <= UInt<1>("h00") @[Debug.scala 725:19] + node _T_1246 = bits(dbReq.addr, 1, 0) @[Debug.scala 727:21] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[Debug.scala 727:28] + when _T_1248 : @[Debug.scala 727:42] + rdHaltnotStatus <= haltnotStatus[0] @[Debug.scala 728:23] + skip @[Debug.scala 727:42] + dbRamRdEn <= UInt<1>("h00") @[Debug.scala 732:18] + dbRamRdEnFinal <= UInt<1>("h00") @[Debug.scala 733:18] + node _T_1251 = shr(dbReq.addr, 4) @[Debug.scala 734:21] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[Debug.scala 734:27] + when _T_1253 : @[Debug.scala 734:40] + dbRamRdEn <= dbRdEn @[Debug.scala 735:15] + when dbRamAddrValid : @[Debug.scala 736:27] + node _T_1254 = cat(RAMRdData.interrupt, RAMRdData.haltnot) @[Debug.scala 737:30] + node _T_1255 = cat(_T_1254, RAMRdData.data) @[Debug.scala 737:30] + dbRdData <= _T_1255 @[Debug.scala 737:17] + dbRamRdEnFinal <= dbRdEn @[Debug.scala 738:22] + skip @[Debug.scala 736:27] + skip @[Debug.scala 734:40] + node _T_1257 = eq(dbReq.addr, UInt<5>("h010")) @[Debug.scala 740:26] + node _T_1259 = eq(_T_1253, UInt<1>("h00")) @[Debug.scala 734:40] + node _T_1260 = and(_T_1259, _T_1257) @[Debug.scala 740:41] + when _T_1260 : @[Debug.scala 740:41] + node _T_1261 = cat(CONTROLRdData.ndreset, CONTROLRdData.fullreset) @[Debug.scala 741:31] + node _T_1262 = cat(CONTROLRdData.autoincrement, CONTROLRdData.access) @[Debug.scala 741:31] + node _T_1263 = cat(_T_1262, CONTROLRdData.hartid) @[Debug.scala 741:31] + node _T_1264 = cat(_T_1263, _T_1261) @[Debug.scala 741:31] + node _T_1265 = cat(CONTROLRdData.buserror, CONTROLRdData.serial) @[Debug.scala 741:31] + node _T_1266 = cat(CONTROLRdData.interrupt, CONTROLRdData.haltnot) @[Debug.scala 741:31] + node _T_1267 = cat(_T_1266, CONTROLRdData.reserved0) @[Debug.scala 741:31] + node _T_1268 = cat(_T_1267, _T_1265) @[Debug.scala 741:31] + node _T_1269 = cat(_T_1268, _T_1264) @[Debug.scala 741:31] + dbRdData <= _T_1269 @[Debug.scala 741:14] + skip @[Debug.scala 740:41] + node _T_1271 = eq(dbReq.addr, UInt<5>("h011")) @[Debug.scala 742:26] + node _T_1273 = eq(_T_1253, UInt<1>("h00")) @[Debug.scala 734:40] + node _T_1275 = eq(_T_1257, UInt<1>("h00")) @[Debug.scala 740:41] + node _T_1276 = and(_T_1273, _T_1275) @[Debug.scala 740:41] + node _T_1277 = and(_T_1276, _T_1271) @[Debug.scala 742:38] + when _T_1277 : @[Debug.scala 742:38] + node _T_1278 = cat(DMINFORdData.authbusy, DMINFORdData.authtype) @[Debug.scala 743:30] + node _T_1279 = cat(_T_1278, DMINFORdData.version) @[Debug.scala 743:30] + node _T_1280 = cat(DMINFORdData.reserved1, DMINFORdData.authenticated) @[Debug.scala 743:30] + node _T_1281 = cat(DMINFORdData.dramsize, DMINFORdData.haltsum) @[Debug.scala 743:30] + node _T_1282 = cat(_T_1281, _T_1280) @[Debug.scala 743:30] + node _T_1283 = cat(_T_1282, _T_1279) @[Debug.scala 743:30] + node _T_1284 = cat(DMINFORdData.access16, DMINFORdData.accesss8) @[Debug.scala 743:30] + node _T_1285 = cat(DMINFORdData.access64, DMINFORdData.access32) @[Debug.scala 743:30] + node _T_1286 = cat(_T_1285, _T_1284) @[Debug.scala 743:30] + node _T_1287 = cat(DMINFORdData.serialcount, DMINFORdData.access128) @[Debug.scala 743:30] + node _T_1288 = cat(DMINFORdData.reserved0, DMINFORdData.abussize) @[Debug.scala 743:30] + node _T_1289 = cat(_T_1288, _T_1287) @[Debug.scala 743:30] + node _T_1290 = cat(_T_1289, _T_1286) @[Debug.scala 743:30] + node _T_1291 = cat(_T_1290, _T_1283) @[Debug.scala 743:30] + dbRdData <= _T_1291 @[Debug.scala 743:14] + skip @[Debug.scala 742:38] + node _T_1293 = eq(dbReq.addr, UInt<5>("h01b")) @[Debug.scala 744:26] + node _T_1295 = eq(_T_1253, UInt<1>("h00")) @[Debug.scala 734:40] + node _T_1297 = eq(_T_1257, UInt<1>("h00")) @[Debug.scala 740:41] + node _T_1298 = and(_T_1295, _T_1297) @[Debug.scala 740:41] + node _T_1300 = eq(_T_1271, UInt<1>("h00")) @[Debug.scala 742:38] + node _T_1301 = and(_T_1298, _T_1300) @[Debug.scala 742:38] + node _T_1302 = and(_T_1301, _T_1293) @[Debug.scala 744:39] + when _T_1302 : @[Debug.scala 744:39] + dbRdData <= UInt<1>("h00") @[Debug.scala 748:16] + skip @[Debug.scala 744:39] + node _T_1304 = shr(dbReq.addr, 2) @[Debug.scala 750:27] + node _T_1306 = eq(_T_1304, UInt<3>("h07")) @[Debug.scala 750:33] + node _T_1308 = eq(_T_1253, UInt<1>("h00")) @[Debug.scala 734:40] + node _T_1310 = eq(_T_1257, UInt<1>("h00")) @[Debug.scala 740:41] + node _T_1311 = and(_T_1308, _T_1310) @[Debug.scala 740:41] + node _T_1313 = eq(_T_1271, UInt<1>("h00")) @[Debug.scala 742:38] + node _T_1314 = and(_T_1311, _T_1313) @[Debug.scala 742:38] + node _T_1316 = eq(_T_1293, UInt<1>("h00")) @[Debug.scala 744:39] + node _T_1317 = and(_T_1314, _T_1316) @[Debug.scala 744:39] + node _T_1318 = and(_T_1317, _T_1306) @[Debug.scala 750:46] + when _T_1318 : @[Debug.scala 750:46] + dbRdData <= rdHaltnotStatus @[Debug.scala 751:14] + skip @[Debug.scala 750:46] + node _T_1320 = eq(_T_1253, UInt<1>("h00")) @[Debug.scala 734:40] + node _T_1322 = eq(_T_1257, UInt<1>("h00")) @[Debug.scala 740:41] + node _T_1323 = and(_T_1320, _T_1322) @[Debug.scala 740:41] + node _T_1325 = eq(_T_1271, UInt<1>("h00")) @[Debug.scala 742:38] + node _T_1326 = and(_T_1323, _T_1325) @[Debug.scala 742:38] + node _T_1328 = eq(_T_1293, UInt<1>("h00")) @[Debug.scala 744:39] + node _T_1329 = and(_T_1326, _T_1328) @[Debug.scala 744:39] + node _T_1331 = eq(_T_1306, UInt<1>("h00")) @[Debug.scala 750:46] + node _T_1332 = and(_T_1329, _T_1331) @[Debug.scala 750:46] + when _T_1332 : @[Debug.scala 752:16] + dbRdData <= UInt<1>("h00") @[Debug.scala 767:14] + skip @[Debug.scala 752:16] + node _T_1334 = bits(dbRdData, 33, 33) @[Debug.scala 771:30] + node _T_1336 = eq(dbReq.op, UInt<2>("h03")) @[Debug.scala 772:13] + node _T_1337 = and(_T_1334, _T_1336) @[Debug.scala 771:48] + rdCondWrFailure <= _T_1337 @[Debug.scala 771:19] + node _T_1339 = eq(dbReq.op, UInt<2>("h02")) @[Debug.scala 774:27] + node _T_1341 = eq(dbReq.op, UInt<2>("h03")) @[Debug.scala 775:14] + node _T_1342 = not(rdCondWrFailure) @[Debug.scala 775:44] + node _T_1343 = and(_T_1341, _T_1342) @[Debug.scala 775:41] + node _T_1344 = or(_T_1339, _T_1343) @[Debug.scala 774:49] + dbWrNeeded <= _T_1344 @[Debug.scala 774:14] + node _T_1347 = mux(rdCondWrFailure, UInt<1>("h01"), UInt<1>("h00")) @[Debug.scala 778:23] + dbResult.resp <= _T_1347 @[Debug.scala 778:17] + dbResult.data <= dbRdData @[Debug.scala 781:17] + node _T_1348 = eq(dbStateReg, UInt<1>("h00")) @[Debug.scala 785:34] + node _T_1349 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 786:15] + node _T_1350 = and(io.db.resp.ready, io.db.resp.valid) @[Decoupled.scala 30:37] + node _T_1351 = and(_T_1349, _T_1350) @[Debug.scala 786:29] + node _T_1352 = or(_T_1348, _T_1351) @[Debug.scala 785:50] + io.db.req.ready <= _T_1352 @[Debug.scala 785:19] + node _T_1353 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 788:35] + io.db.resp.valid <= _T_1353 @[Debug.scala 788:20] + io.db.resp.bits <- dbRespReg @[Debug.scala 789:20] + node _T_1354 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 30:37] + dbRdEn <= _T_1354 @[Debug.scala 791:10] + node _T_1355 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 30:37] + node _T_1356 = and(dbWrNeeded, _T_1355) @[Debug.scala 792:24] + dbWrEn <= _T_1356 @[Debug.scala 792:10] + node _T_1357 = eq(dbStateReg, UInt<1>("h00")) @[Debug.scala 797:20] + when _T_1357 : @[Debug.scala 797:35] + node _T_1358 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 30:37] + when _T_1358 : @[Debug.scala 798:28] + dbStateReg <= UInt<1>("h01") @[Debug.scala 799:18] + dbRespReg <- dbResult @[Debug.scala 800:17] + skip @[Debug.scala 798:28] + skip @[Debug.scala 797:35] + node _T_1359 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 802:27] + node _T_1361 = eq(_T_1357, UInt<1>("h00")) @[Debug.scala 797:35] + node _T_1362 = and(_T_1361, _T_1359) @[Debug.scala 802:41] + when _T_1362 : @[Debug.scala 802:41] + node _T_1363 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 30:37] + when _T_1363 : @[Debug.scala 803:28] + dbStateReg <= UInt<1>("h01") @[Debug.scala 804:18] + dbRespReg <- dbResult @[Debug.scala 805:17] + skip @[Debug.scala 803:28] + node _T_1364 = and(io.db.resp.ready, io.db.resp.valid) @[Decoupled.scala 30:37] + node _T_1366 = eq(_T_1363, UInt<1>("h00")) @[Debug.scala 803:28] + node _T_1367 = and(_T_1366, _T_1364) @[Debug.scala 806:35] + when _T_1367 : @[Debug.scala 806:35] + dbStateReg <= UInt<1>("h00") @[Debug.scala 807:18] + skip @[Debug.scala 806:35] + skip @[Debug.scala 802:41] + wire _T_1507 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegisterRouter.scala 47:18] + _T_1507 is invalid @[RegisterRouter.scala 47:18] + node _T_1525 = eq(io.in.0.a.bits.opcode, UInt<3>("h04")) @[RegisterRouter.scala 48:36] + _T_1507.bits.read <= _T_1525 @[RegisterRouter.scala 48:19] + node _T_1526 = shr(io.in.0.a.bits.address, 3) @[Edges.scala 170:34] + _T_1507.bits.index <= _T_1526 @[RegisterRouter.scala 49:19] + _T_1507.bits.data <= io.in.0.a.bits.data @[RegisterRouter.scala 50:19] + _T_1507.bits.mask <= io.in.0.a.bits.mask @[RegisterRouter.scala 51:19] + node _T_1527 = bits(io.in.0.a.bits.address, 2, 0) @[Edges.scala 172:47] + node _T_1528 = cat(_T_1527, io.in.0.a.bits.source) @[Cat.scala 30:58] + node _T_1529 = cat(_T_1528, io.in.0.a.bits.size) @[Cat.scala 30:58] + _T_1507.bits.extra <= _T_1529 @[RegisterRouter.scala 52:19] + wire _T_1547 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, data : UInt<64>, extra : UInt<12>}} @[RegMapper.scala 56:19] + _T_1547 is invalid @[RegMapper.scala 56:19] + wire _T_1583 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegMapper.scala 57:21] + _T_1583 is invalid @[RegMapper.scala 57:21] + _T_1583.bits <- _T_1507.bits @[RegMapper.scala 58:16] + node _T_1601 = not(UInt<9>("h012f")) @[RegMapper.scala 74:21] + node _T_1731 = xor(_T_1583.bits.index, UInt<9>("h010d")) @[RegMapper.scala 93:47] + node _T_1732 = and(_T_1731, _T_1601) @[RegMapper.scala 93:55] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1735 = xor(_T_1583.bits.index, UInt<9>("h010d")) @[RegMapper.scala 94:47] + node _T_1736 = and(_T_1735, _T_1601) @[RegMapper.scala 94:55] + node _T_1738 = eq(_T_1736, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1740 = xor(_T_1583.bits.index, UInt<9>("h0101")) @[RegMapper.scala 93:47] + node _T_1741 = and(_T_1740, _T_1601) @[RegMapper.scala 93:55] + node _T_1743 = eq(_T_1741, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1744 = xor(_T_1583.bits.index, UInt<9>("h0101")) @[RegMapper.scala 94:47] + node _T_1745 = and(_T_1744, _T_1601) @[RegMapper.scala 94:55] + node _T_1747 = eq(_T_1745, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1749 = xor(_T_1583.bits.index, UInt<9>("h0105")) @[RegMapper.scala 93:47] + node _T_1750 = and(_T_1749, _T_1601) @[RegMapper.scala 93:55] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1753 = xor(_T_1583.bits.index, UInt<9>("h0105")) @[RegMapper.scala 94:47] + node _T_1754 = and(_T_1753, _T_1601) @[RegMapper.scala 94:55] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1758 = xor(_T_1583.bits.index, UInt<9>("h084")) @[RegMapper.scala 93:47] + node _T_1759 = and(_T_1758, _T_1601) @[RegMapper.scala 93:55] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1762 = xor(_T_1583.bits.index, UInt<9>("h084")) @[RegMapper.scala 94:47] + node _T_1763 = and(_T_1762, _T_1601) @[RegMapper.scala 94:55] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1767 = xor(_T_1583.bits.index, UInt<9>("h085")) @[RegMapper.scala 93:47] + node _T_1768 = and(_T_1767, _T_1601) @[RegMapper.scala 93:55] + node _T_1770 = eq(_T_1768, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1771 = xor(_T_1583.bits.index, UInt<9>("h085")) @[RegMapper.scala 94:47] + node _T_1772 = and(_T_1771, _T_1601) @[RegMapper.scala 94:55] + node _T_1774 = eq(_T_1772, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1776 = xor(_T_1583.bits.index, UInt<9>("h0109")) @[RegMapper.scala 93:47] + node _T_1777 = and(_T_1776, _T_1601) @[RegMapper.scala 93:55] + node _T_1779 = eq(_T_1777, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1780 = xor(_T_1583.bits.index, UInt<9>("h0109")) @[RegMapper.scala 94:47] + node _T_1781 = and(_T_1780, _T_1601) @[RegMapper.scala 94:55] + node _T_1783 = eq(_T_1781, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1785 = xor(_T_1583.bits.index, UInt<9>("h010e")) @[RegMapper.scala 93:47] + node _T_1786 = and(_T_1785, _T_1601) @[RegMapper.scala 93:55] + node _T_1788 = eq(_T_1786, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1789 = xor(_T_1583.bits.index, UInt<9>("h010e")) @[RegMapper.scala 94:47] + node _T_1790 = and(_T_1789, _T_1601) @[RegMapper.scala 94:55] + node _T_1792 = eq(_T_1790, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1794 = xor(_T_1583.bits.index, UInt<9>("h0104")) @[RegMapper.scala 93:47] + node _T_1795 = and(_T_1794, _T_1601) @[RegMapper.scala 93:55] + node _T_1797 = eq(_T_1795, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1798 = xor(_T_1583.bits.index, UInt<9>("h0104")) @[RegMapper.scala 94:47] + node _T_1799 = and(_T_1798, _T_1601) @[RegMapper.scala 94:55] + node _T_1801 = eq(_T_1799, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1803 = xor(_T_1583.bits.index, UInt<9>("h021")) @[RegMapper.scala 93:47] + node _T_1804 = and(_T_1803, _T_1601) @[RegMapper.scala 93:55] + node _T_1806 = eq(_T_1804, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1807 = xor(_T_1583.bits.index, UInt<9>("h021")) @[RegMapper.scala 94:47] + node _T_1808 = and(_T_1807, _T_1601) @[RegMapper.scala 94:55] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1812 = xor(_T_1583.bits.index, UInt<9>("h0100")) @[RegMapper.scala 93:47] + node _T_1813 = and(_T_1812, _T_1601) @[RegMapper.scala 93:55] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1816 = xor(_T_1583.bits.index, UInt<9>("h0100")) @[RegMapper.scala 94:47] + node _T_1817 = and(_T_1816, _T_1601) @[RegMapper.scala 94:55] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1821 = xor(_T_1583.bits.index, UInt<9>("h081")) @[RegMapper.scala 93:47] + node _T_1822 = and(_T_1821, _T_1601) @[RegMapper.scala 93:55] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1825 = xor(_T_1583.bits.index, UInt<9>("h081")) @[RegMapper.scala 94:47] + node _T_1826 = and(_T_1825, _T_1601) @[RegMapper.scala 94:55] + node _T_1828 = eq(_T_1826, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1830 = xor(_T_1583.bits.index, UInt<9>("h086")) @[RegMapper.scala 93:47] + node _T_1831 = and(_T_1830, _T_1601) @[RegMapper.scala 93:55] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1834 = xor(_T_1583.bits.index, UInt<9>("h086")) @[RegMapper.scala 94:47] + node _T_1835 = and(_T_1834, _T_1601) @[RegMapper.scala 94:55] + node _T_1837 = eq(_T_1835, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1839 = xor(_T_1583.bits.index, UInt<9>("h080")) @[RegMapper.scala 93:47] + node _T_1840 = and(_T_1839, _T_1601) @[RegMapper.scala 93:55] + node _T_1842 = eq(_T_1840, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1843 = xor(_T_1583.bits.index, UInt<9>("h080")) @[RegMapper.scala 94:47] + node _T_1844 = and(_T_1843, _T_1601) @[RegMapper.scala 94:55] + node _T_1846 = eq(_T_1844, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1848 = xor(_T_1583.bits.index, UInt<9>("h010a")) @[RegMapper.scala 93:47] + node _T_1849 = and(_T_1848, _T_1601) @[RegMapper.scala 93:55] + node _T_1851 = eq(_T_1849, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1852 = xor(_T_1583.bits.index, UInt<9>("h010a")) @[RegMapper.scala 94:47] + node _T_1853 = and(_T_1852, _T_1601) @[RegMapper.scala 94:55] + node _T_1855 = eq(_T_1853, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1857 = xor(_T_1583.bits.index, UInt<9>("h020")) @[RegMapper.scala 93:47] + node _T_1858 = and(_T_1857, _T_1601) @[RegMapper.scala 93:55] + node _T_1860 = eq(_T_1858, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1861 = xor(_T_1583.bits.index, UInt<9>("h020")) @[RegMapper.scala 94:47] + node _T_1862 = and(_T_1861, _T_1601) @[RegMapper.scala 94:55] + node _T_1864 = eq(_T_1862, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1866 = xor(_T_1583.bits.index, UInt<9>("h0108")) @[RegMapper.scala 93:47] + node _T_1867 = and(_T_1866, _T_1601) @[RegMapper.scala 93:55] + node _T_1869 = eq(_T_1867, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1870 = xor(_T_1583.bits.index, UInt<9>("h0108")) @[RegMapper.scala 94:47] + node _T_1871 = and(_T_1870, _T_1601) @[RegMapper.scala 94:55] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1875 = xor(_T_1583.bits.index, UInt<9>("h0103")) @[RegMapper.scala 93:47] + node _T_1876 = and(_T_1875, _T_1601) @[RegMapper.scala 93:55] + node _T_1878 = eq(_T_1876, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1879 = xor(_T_1583.bits.index, UInt<9>("h0103")) @[RegMapper.scala 94:47] + node _T_1880 = and(_T_1879, _T_1601) @[RegMapper.scala 94:55] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1884 = xor(_T_1583.bits.index, UInt<9>("h082")) @[RegMapper.scala 93:47] + node _T_1885 = and(_T_1884, _T_1601) @[RegMapper.scala 93:55] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1888 = xor(_T_1583.bits.index, UInt<9>("h082")) @[RegMapper.scala 94:47] + node _T_1889 = and(_T_1888, _T_1601) @[RegMapper.scala 94:55] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1893 = xor(_T_1583.bits.index, UInt<9>("h087")) @[RegMapper.scala 93:47] + node _T_1894 = and(_T_1893, _T_1601) @[RegMapper.scala 93:55] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1897 = xor(_T_1583.bits.index, UInt<9>("h087")) @[RegMapper.scala 94:47] + node _T_1898 = and(_T_1897, _T_1601) @[RegMapper.scala 94:55] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1902 = xor(_T_1583.bits.index, UInt<9>("h010b")) @[RegMapper.scala 93:47] + node _T_1903 = and(_T_1902, _T_1601) @[RegMapper.scala 93:55] + node _T_1905 = eq(_T_1903, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1906 = xor(_T_1583.bits.index, UInt<9>("h010b")) @[RegMapper.scala 94:47] + node _T_1907 = and(_T_1906, _T_1601) @[RegMapper.scala 94:55] + node _T_1909 = eq(_T_1907, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1911 = xor(_T_1583.bits.index, UInt<9>("h0107")) @[RegMapper.scala 93:47] + node _T_1912 = and(_T_1911, _T_1601) @[RegMapper.scala 93:55] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1915 = xor(_T_1583.bits.index, UInt<9>("h0107")) @[RegMapper.scala 94:47] + node _T_1916 = and(_T_1915, _T_1601) @[RegMapper.scala 94:55] + node _T_1918 = eq(_T_1916, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1920 = xor(_T_1583.bits.index, UInt<9>("h0102")) @[RegMapper.scala 93:47] + node _T_1921 = and(_T_1920, _T_1601) @[RegMapper.scala 93:55] + node _T_1923 = eq(_T_1921, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1924 = xor(_T_1583.bits.index, UInt<9>("h0102")) @[RegMapper.scala 94:47] + node _T_1925 = and(_T_1924, _T_1601) @[RegMapper.scala 94:55] + node _T_1927 = eq(_T_1925, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1929 = xor(_T_1583.bits.index, UInt<9>("h0106")) @[RegMapper.scala 93:47] + node _T_1930 = and(_T_1929, _T_1601) @[RegMapper.scala 93:55] + node _T_1932 = eq(_T_1930, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1933 = xor(_T_1583.bits.index, UInt<9>("h0106")) @[RegMapper.scala 94:47] + node _T_1934 = and(_T_1933, _T_1601) @[RegMapper.scala 94:55] + node _T_1936 = eq(_T_1934, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1938 = xor(_T_1583.bits.index, UInt<9>("h010c")) @[RegMapper.scala 93:47] + node _T_1939 = and(_T_1938, _T_1601) @[RegMapper.scala 93:55] + node _T_1941 = eq(_T_1939, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1942 = xor(_T_1583.bits.index, UInt<9>("h010c")) @[RegMapper.scala 94:47] + node _T_1943 = and(_T_1942, _T_1601) @[RegMapper.scala 94:55] + node _T_1945 = eq(_T_1943, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_1947 = xor(_T_1583.bits.index, UInt<9>("h083")) @[RegMapper.scala 93:47] + node _T_1948 = and(_T_1947, _T_1601) @[RegMapper.scala 93:55] + node _T_1950 = eq(_T_1948, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_1951 = xor(_T_1583.bits.index, UInt<9>("h083")) @[RegMapper.scala 94:47] + node _T_1952 = and(_T_1951, _T_1601) @[RegMapper.scala 94:55] + node _T_1954 = eq(_T_1952, UInt<1>("h00")) @[RegMapper.scala 94:68] + wire _T_1958 : UInt<1>[182] @[RegMapper.scala 107:23] + _T_1958 is invalid @[RegMapper.scala 107:23] + wire _T_2146 : UInt<1>[182] @[RegMapper.scala 108:23] + _T_2146 is invalid @[RegMapper.scala 108:23] + wire _T_2334 : UInt<1>[182] @[RegMapper.scala 109:23] + _T_2334 is invalid @[RegMapper.scala 109:23] + wire _T_2522 : UInt<1>[182] @[RegMapper.scala 110:23] + _T_2522 is invalid @[RegMapper.scala 110:23] + wire _T_2710 : UInt<1>[182] @[RegMapper.scala 111:23] + _T_2710 is invalid @[RegMapper.scala 111:23] + wire _T_2898 : UInt<1>[182] @[RegMapper.scala 112:23] + _T_2898 is invalid @[RegMapper.scala 112:23] + wire _T_3086 : UInt<1>[182] @[RegMapper.scala 113:23] + _T_3086 is invalid @[RegMapper.scala 113:23] + wire _T_3274 : UInt<1>[182] @[RegMapper.scala 114:23] + _T_3274 is invalid @[RegMapper.scala 114:23] + node _T_3779 = bits(_T_1583.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_3780 = bits(_T_1583.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_3781 = bits(_T_1583.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_3782 = bits(_T_1583.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_3783 = bits(_T_1583.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_3784 = bits(_T_1583.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_3785 = bits(_T_1583.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_3786 = bits(_T_1583.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_3787 = bits(_T_3779, 0, 0) @[Bitwise.scala 71:15] + node _T_3790 = mux(_T_3787, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3791 = bits(_T_3780, 0, 0) @[Bitwise.scala 71:15] + node _T_3794 = mux(_T_3791, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3795 = bits(_T_3781, 0, 0) @[Bitwise.scala 71:15] + node _T_3798 = mux(_T_3795, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3799 = bits(_T_3782, 0, 0) @[Bitwise.scala 71:15] + node _T_3802 = mux(_T_3799, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3803 = bits(_T_3783, 0, 0) @[Bitwise.scala 71:15] + node _T_3806 = mux(_T_3803, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3807 = bits(_T_3784, 0, 0) @[Bitwise.scala 71:15] + node _T_3810 = mux(_T_3807, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3811 = bits(_T_3785, 0, 0) @[Bitwise.scala 71:15] + node _T_3814 = mux(_T_3811, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3815 = bits(_T_3786, 0, 0) @[Bitwise.scala 71:15] + node _T_3818 = mux(_T_3815, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3819 = cat(_T_3794, _T_3790) @[Cat.scala 30:58] + node _T_3820 = cat(_T_3802, _T_3798) @[Cat.scala 30:58] + node _T_3821 = cat(_T_3820, _T_3819) @[Cat.scala 30:58] + node _T_3822 = cat(_T_3810, _T_3806) @[Cat.scala 30:58] + node _T_3823 = cat(_T_3818, _T_3814) @[Cat.scala 30:58] + node _T_3824 = cat(_T_3823, _T_3822) @[Cat.scala 30:58] + node _T_3825 = cat(_T_3824, _T_3821) @[Cat.scala 30:58] + node _T_3826 = bits(_T_1583.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_3827 = bits(_T_1583.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_3828 = bits(_T_1583.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_3829 = bits(_T_1583.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_3830 = bits(_T_1583.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_3831 = bits(_T_1583.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_3832 = bits(_T_1583.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_3833 = bits(_T_1583.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_3834 = bits(_T_3826, 0, 0) @[Bitwise.scala 71:15] + node _T_3837 = mux(_T_3834, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3838 = bits(_T_3827, 0, 0) @[Bitwise.scala 71:15] + node _T_3841 = mux(_T_3838, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3842 = bits(_T_3828, 0, 0) @[Bitwise.scala 71:15] + node _T_3845 = mux(_T_3842, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3846 = bits(_T_3829, 0, 0) @[Bitwise.scala 71:15] + node _T_3849 = mux(_T_3846, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3850 = bits(_T_3830, 0, 0) @[Bitwise.scala 71:15] + node _T_3853 = mux(_T_3850, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3854 = bits(_T_3831, 0, 0) @[Bitwise.scala 71:15] + node _T_3857 = mux(_T_3854, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3858 = bits(_T_3832, 0, 0) @[Bitwise.scala 71:15] + node _T_3861 = mux(_T_3858, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3862 = bits(_T_3833, 0, 0) @[Bitwise.scala 71:15] + node _T_3865 = mux(_T_3862, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_3866 = cat(_T_3841, _T_3837) @[Cat.scala 30:58] + node _T_3867 = cat(_T_3849, _T_3845) @[Cat.scala 30:58] + node _T_3868 = cat(_T_3867, _T_3866) @[Cat.scala 30:58] + node _T_3869 = cat(_T_3857, _T_3853) @[Cat.scala 30:58] + node _T_3870 = cat(_T_3865, _T_3861) @[Cat.scala 30:58] + node _T_3871 = cat(_T_3870, _T_3869) @[Cat.scala 30:58] + node _T_3872 = cat(_T_3871, _T_3868) @[Cat.scala 30:58] + node _T_3873 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_3875 = neq(_T_3873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3876 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_3877 = not(_T_3876) @[RegMapper.scala 136:45] + node _T_3879 = eq(_T_3877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3880 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_3882 = neq(_T_3880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3883 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_3884 = not(_T_3883) @[RegMapper.scala 138:44] + node _T_3886 = eq(_T_3884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3887 = and(_T_1958[0], _T_3875) @[RegMapper.scala 140:69] + node _T_3888 = and(_T_3086[0], _T_3882) @[RegMapper.scala 140:91] + node _T_3891 = and(_T_2146[0], _T_3879) @[RegMapper.scala 141:62] + node _T_3892 = and(_T_3274[0], _T_3886) @[RegMapper.scala 141:84] + node _T_3893 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_3897 = eq(_T_3875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3898 = or(UInt<1>("h01"), _T_3897) @[RegMapper.scala 142:31] + _T_2334[0] <= _T_3898 @[RegMapper.scala 142:18] + node _T_3900 = eq(_T_3879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3901 = or(UInt<1>("h01"), _T_3900) @[RegMapper.scala 143:31] + _T_2522[0] <= _T_3901 @[RegMapper.scala 143:18] + node _T_3903 = eq(_T_3882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3904 = or(UInt<1>("h01"), _T_3903) @[RegMapper.scala 144:31] + _T_2710[0] <= _T_3904 @[RegMapper.scala 144:18] + node _T_3906 = eq(_T_3886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3907 = or(UInt<1>("h01"), _T_3906) @[RegMapper.scala 145:31] + _T_2898[0] <= _T_3907 @[RegMapper.scala 145:18] + node _T_3908 = shl(UInt<5>("h013"), 0) @[RegMapper.scala 150:47] + node _T_3910 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_3911 = and(_T_3908, _T_3910) @[RegMapper.scala 150:55] + node _T_3912 = or(UInt<1>("h00"), _T_3911) @[RegMapper.scala 150:35] + node _T_3913 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_3915 = neq(_T_3913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3916 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_3917 = not(_T_3916) @[RegMapper.scala 136:45] + node _T_3919 = eq(_T_3917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3920 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_3922 = neq(_T_3920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3923 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_3924 = not(_T_3923) @[RegMapper.scala 138:44] + node _T_3926 = eq(_T_3924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3927 = and(_T_1958[1], _T_3915) @[RegMapper.scala 140:69] + node _T_3928 = and(_T_3086[1], _T_3922) @[RegMapper.scala 140:91] + node _T_3931 = and(_T_2146[1], _T_3919) @[RegMapper.scala 141:62] + node _T_3932 = and(_T_3274[1], _T_3926) @[RegMapper.scala 141:84] + node _T_3933 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_3937 = eq(_T_3915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3938 = or(UInt<1>("h01"), _T_3937) @[RegMapper.scala 142:31] + _T_2334[1] <= _T_3938 @[RegMapper.scala 142:18] + node _T_3940 = eq(_T_3919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3941 = or(UInt<1>("h01"), _T_3940) @[RegMapper.scala 143:31] + _T_2522[1] <= _T_3941 @[RegMapper.scala 143:18] + node _T_3943 = eq(_T_3922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3944 = or(UInt<1>("h01"), _T_3943) @[RegMapper.scala 144:31] + _T_2710[1] <= _T_3944 @[RegMapper.scala 144:18] + node _T_3946 = eq(_T_3926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3947 = or(UInt<1>("h01"), _T_3946) @[RegMapper.scala 145:31] + _T_2898[1] <= _T_3947 @[RegMapper.scala 145:18] + node _T_3948 = shl(UInt<7>("h074"), 8) @[RegMapper.scala 150:47] + node _T_3950 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_3951 = and(_T_3948, _T_3950) @[RegMapper.scala 150:55] + node _T_3952 = or(_T_3912, _T_3951) @[RegMapper.scala 150:35] + node _T_3953 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_3955 = neq(_T_3953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3956 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_3957 = not(_T_3956) @[RegMapper.scala 136:45] + node _T_3959 = eq(_T_3957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3960 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_3962 = neq(_T_3960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3963 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_3964 = not(_T_3963) @[RegMapper.scala 138:44] + node _T_3966 = eq(_T_3964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3967 = and(_T_1958[2], _T_3955) @[RegMapper.scala 140:69] + node _T_3968 = and(_T_3086[2], _T_3962) @[RegMapper.scala 140:91] + node _T_3971 = and(_T_2146[2], _T_3959) @[RegMapper.scala 141:62] + node _T_3972 = and(_T_3274[2], _T_3966) @[RegMapper.scala 141:84] + node _T_3973 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_3977 = eq(_T_3955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3978 = or(UInt<1>("h01"), _T_3977) @[RegMapper.scala 142:31] + _T_2334[2] <= _T_3978 @[RegMapper.scala 142:18] + node _T_3980 = eq(_T_3959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3981 = or(UInt<1>("h01"), _T_3980) @[RegMapper.scala 143:31] + _T_2522[2] <= _T_3981 @[RegMapper.scala 143:18] + node _T_3983 = eq(_T_3962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3984 = or(UInt<1>("h01"), _T_3983) @[RegMapper.scala 144:31] + _T_2710[2] <= _T_3984 @[RegMapper.scala 144:18] + node _T_3986 = eq(_T_3966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3987 = or(UInt<1>("h01"), _T_3986) @[RegMapper.scala 145:31] + _T_2898[2] <= _T_3987 @[RegMapper.scala 145:18] + node _T_3988 = shl(UInt<3>("h04"), 16) @[RegMapper.scala 150:47] + node _T_3990 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_3991 = and(_T_3988, _T_3990) @[RegMapper.scala 150:55] + node _T_3992 = or(_T_3952, _T_3991) @[RegMapper.scala 150:35] + node _T_3993 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_3995 = neq(_T_3993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3996 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_3997 = not(_T_3996) @[RegMapper.scala 136:45] + node _T_3999 = eq(_T_3997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4000 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_4002 = neq(_T_4000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4003 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_4004 = not(_T_4003) @[RegMapper.scala 138:44] + node _T_4006 = eq(_T_4004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4007 = and(_T_1958[3], _T_3995) @[RegMapper.scala 140:69] + node _T_4008 = and(_T_3086[3], _T_4002) @[RegMapper.scala 140:91] + node _T_4011 = and(_T_2146[3], _T_3999) @[RegMapper.scala 141:62] + node _T_4012 = and(_T_3274[3], _T_4006) @[RegMapper.scala 141:84] + node _T_4013 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_4017 = eq(_T_3995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4018 = or(UInt<1>("h01"), _T_4017) @[RegMapper.scala 142:31] + _T_2334[3] <= _T_4018 @[RegMapper.scala 142:18] + node _T_4020 = eq(_T_3999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4021 = or(UInt<1>("h01"), _T_4020) @[RegMapper.scala 143:31] + _T_2522[3] <= _T_4021 @[RegMapper.scala 143:18] + node _T_4023 = eq(_T_4002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4024 = or(UInt<1>("h01"), _T_4023) @[RegMapper.scala 144:31] + _T_2710[3] <= _T_4024 @[RegMapper.scala 144:18] + node _T_4026 = eq(_T_4006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4027 = or(UInt<1>("h01"), _T_4026) @[RegMapper.scala 145:31] + _T_2898[3] <= _T_4027 @[RegMapper.scala 145:18] + node _T_4028 = shl(UInt<2>("h02"), 24) @[RegMapper.scala 150:47] + node _T_4030 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_4031 = and(_T_4028, _T_4030) @[RegMapper.scala 150:55] + node _T_4032 = or(_T_3992, _T_4031) @[RegMapper.scala 150:35] + node _T_4033 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_4035 = neq(_T_4033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4036 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_4037 = not(_T_4036) @[RegMapper.scala 136:45] + node _T_4039 = eq(_T_4037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4040 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_4042 = neq(_T_4040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4043 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_4044 = not(_T_4043) @[RegMapper.scala 138:44] + node _T_4046 = eq(_T_4044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4047 = and(_T_1958[4], _T_4035) @[RegMapper.scala 140:69] + node _T_4048 = and(_T_3086[4], _T_4042) @[RegMapper.scala 140:91] + node _T_4051 = and(_T_2146[4], _T_4039) @[RegMapper.scala 141:62] + node _T_4052 = and(_T_3274[4], _T_4046) @[RegMapper.scala 141:84] + node _T_4053 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_4057 = eq(_T_4035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4058 = or(UInt<1>("h01"), _T_4057) @[RegMapper.scala 142:31] + _T_2334[4] <= _T_4058 @[RegMapper.scala 142:18] + node _T_4060 = eq(_T_4039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4061 = or(UInt<1>("h01"), _T_4060) @[RegMapper.scala 143:31] + _T_2522[4] <= _T_4061 @[RegMapper.scala 143:18] + node _T_4063 = eq(_T_4042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4064 = or(UInt<1>("h01"), _T_4063) @[RegMapper.scala 144:31] + _T_2710[4] <= _T_4064 @[RegMapper.scala 144:18] + node _T_4066 = eq(_T_4046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4067 = or(UInt<1>("h01"), _T_4066) @[RegMapper.scala 145:31] + _T_2898[4] <= _T_4067 @[RegMapper.scala 145:18] + node _T_4068 = shl(UInt<8>("h0e3"), 32) @[RegMapper.scala 150:47] + node _T_4070 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_4071 = and(_T_4068, _T_4070) @[RegMapper.scala 150:55] + node _T_4072 = or(_T_4032, _T_4071) @[RegMapper.scala 150:35] + node _T_4073 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_4075 = neq(_T_4073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4076 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_4077 = not(_T_4076) @[RegMapper.scala 136:45] + node _T_4079 = eq(_T_4077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4080 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_4082 = neq(_T_4080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4083 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_4084 = not(_T_4083) @[RegMapper.scala 138:44] + node _T_4086 = eq(_T_4084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4087 = and(_T_1958[5], _T_4075) @[RegMapper.scala 140:69] + node _T_4088 = and(_T_3086[5], _T_4082) @[RegMapper.scala 140:91] + node _T_4091 = and(_T_2146[5], _T_4079) @[RegMapper.scala 141:62] + node _T_4092 = and(_T_3274[5], _T_4086) @[RegMapper.scala 141:84] + node _T_4093 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_4097 = eq(_T_4075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4098 = or(UInt<1>("h01"), _T_4097) @[RegMapper.scala 142:31] + _T_2334[5] <= _T_4098 @[RegMapper.scala 142:18] + node _T_4100 = eq(_T_4079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4101 = or(UInt<1>("h01"), _T_4100) @[RegMapper.scala 143:31] + _T_2522[5] <= _T_4101 @[RegMapper.scala 143:18] + node _T_4103 = eq(_T_4082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4104 = or(UInt<1>("h01"), _T_4103) @[RegMapper.scala 144:31] + _T_2710[5] <= _T_4104 @[RegMapper.scala 144:18] + node _T_4106 = eq(_T_4086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4107 = or(UInt<1>("h01"), _T_4106) @[RegMapper.scala 145:31] + _T_2898[5] <= _T_4107 @[RegMapper.scala 145:18] + node _T_4108 = shl(UInt<4>("h0c"), 40) @[RegMapper.scala 150:47] + node _T_4110 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_4111 = and(_T_4108, _T_4110) @[RegMapper.scala 150:55] + node _T_4112 = or(_T_4072, _T_4111) @[RegMapper.scala 150:35] + node _T_4113 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_4115 = neq(_T_4113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4116 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_4117 = not(_T_4116) @[RegMapper.scala 136:45] + node _T_4119 = eq(_T_4117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4120 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_4122 = neq(_T_4120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4123 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_4124 = not(_T_4123) @[RegMapper.scala 138:44] + node _T_4126 = eq(_T_4124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4127 = and(_T_1958[6], _T_4115) @[RegMapper.scala 140:69] + node _T_4128 = and(_T_3086[6], _T_4122) @[RegMapper.scala 140:91] + node _T_4131 = and(_T_2146[6], _T_4119) @[RegMapper.scala 141:62] + node _T_4132 = and(_T_3274[6], _T_4126) @[RegMapper.scala 141:84] + node _T_4133 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_4137 = eq(_T_4115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4138 = or(UInt<1>("h01"), _T_4137) @[RegMapper.scala 142:31] + _T_2334[6] <= _T_4138 @[RegMapper.scala 142:18] + node _T_4140 = eq(_T_4119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4141 = or(UInt<1>("h01"), _T_4140) @[RegMapper.scala 143:31] + _T_2522[6] <= _T_4141 @[RegMapper.scala 143:18] + node _T_4143 = eq(_T_4122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4144 = or(UInt<1>("h01"), _T_4143) @[RegMapper.scala 144:31] + _T_2710[6] <= _T_4144 @[RegMapper.scala 144:18] + node _T_4146 = eq(_T_4126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4147 = or(UInt<1>("h01"), _T_4146) @[RegMapper.scala 145:31] + _T_2898[6] <= _T_4147 @[RegMapper.scala 145:18] + node _T_4148 = shl(UInt<3>("h04"), 48) @[RegMapper.scala 150:47] + node _T_4150 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_4151 = and(_T_4148, _T_4150) @[RegMapper.scala 150:55] + node _T_4152 = or(_T_4112, _T_4151) @[RegMapper.scala 150:35] + node _T_4153 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_4155 = neq(_T_4153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4156 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_4157 = not(_T_4156) @[RegMapper.scala 136:45] + node _T_4159 = eq(_T_4157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4160 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_4162 = neq(_T_4160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4163 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_4164 = not(_T_4163) @[RegMapper.scala 138:44] + node _T_4166 = eq(_T_4164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4167 = and(_T_1958[7], _T_4155) @[RegMapper.scala 140:69] + node _T_4168 = and(_T_3086[7], _T_4162) @[RegMapper.scala 140:91] + node _T_4171 = and(_T_2146[7], _T_4159) @[RegMapper.scala 141:62] + node _T_4172 = and(_T_3274[7], _T_4166) @[RegMapper.scala 141:84] + node _T_4173 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_4177 = eq(_T_4155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4178 = or(UInt<1>("h01"), _T_4177) @[RegMapper.scala 142:31] + _T_2334[7] <= _T_4178 @[RegMapper.scala 142:18] + node _T_4180 = eq(_T_4159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4181 = or(UInt<1>("h01"), _T_4180) @[RegMapper.scala 143:31] + _T_2522[7] <= _T_4181 @[RegMapper.scala 143:18] + node _T_4183 = eq(_T_4162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4184 = or(UInt<1>("h01"), _T_4183) @[RegMapper.scala 144:31] + _T_2710[7] <= _T_4184 @[RegMapper.scala 144:18] + node _T_4186 = eq(_T_4166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4187 = or(UInt<1>("h01"), _T_4186) @[RegMapper.scala 145:31] + _T_2898[7] <= _T_4187 @[RegMapper.scala 145:18] + node _T_4188 = shl(UInt<8>("h0fe"), 56) @[RegMapper.scala 150:47] + node _T_4190 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_4191 = and(_T_4188, _T_4190) @[RegMapper.scala 150:55] + node _T_4192 = or(_T_4152, _T_4191) @[RegMapper.scala 150:35] + node _T_4193 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_4195 = neq(_T_4193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4196 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_4197 = not(_T_4196) @[RegMapper.scala 136:45] + node _T_4199 = eq(_T_4197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4200 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_4202 = neq(_T_4200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4203 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_4204 = not(_T_4203) @[RegMapper.scala 138:44] + node _T_4206 = eq(_T_4204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4207 = and(_T_1958[8], _T_4195) @[RegMapper.scala 140:69] + node _T_4208 = and(_T_3086[8], _T_4202) @[RegMapper.scala 140:91] + node _T_4211 = and(_T_2146[8], _T_4199) @[RegMapper.scala 141:62] + node _T_4212 = and(_T_3274[8], _T_4206) @[RegMapper.scala 141:84] + node _T_4213 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_4217 = eq(_T_4195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4218 = or(UInt<1>("h01"), _T_4217) @[RegMapper.scala 142:31] + _T_2334[8] <= _T_4218 @[RegMapper.scala 142:18] + node _T_4220 = eq(_T_4199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4221 = or(UInt<1>("h01"), _T_4220) @[RegMapper.scala 143:31] + _T_2522[8] <= _T_4221 @[RegMapper.scala 143:18] + node _T_4223 = eq(_T_4202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4224 = or(UInt<1>("h01"), _T_4223) @[RegMapper.scala 144:31] + _T_2710[8] <= _T_4224 @[RegMapper.scala 144:18] + node _T_4226 = eq(_T_4206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4227 = or(UInt<1>("h01"), _T_4226) @[RegMapper.scala 145:31] + _T_2898[8] <= _T_4227 @[RegMapper.scala 145:18] + node _T_4228 = shl(UInt<5>("h013"), 0) @[RegMapper.scala 150:47] + node _T_4230 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_4231 = and(_T_4228, _T_4230) @[RegMapper.scala 150:55] + node _T_4232 = or(UInt<1>("h00"), _T_4231) @[RegMapper.scala 150:35] + node _T_4233 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_4235 = neq(_T_4233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4236 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_4237 = not(_T_4236) @[RegMapper.scala 136:45] + node _T_4239 = eq(_T_4237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4240 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_4242 = neq(_T_4240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4243 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_4244 = not(_T_4243) @[RegMapper.scala 138:44] + node _T_4246 = eq(_T_4244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4247 = and(_T_1958[9], _T_4235) @[RegMapper.scala 140:69] + node _T_4248 = and(_T_3086[9], _T_4242) @[RegMapper.scala 140:91] + node _T_4251 = and(_T_2146[9], _T_4239) @[RegMapper.scala 141:62] + node _T_4252 = and(_T_3274[9], _T_4246) @[RegMapper.scala 141:84] + node _T_4253 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_4257 = eq(_T_4235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4258 = or(UInt<1>("h01"), _T_4257) @[RegMapper.scala 142:31] + _T_2334[9] <= _T_4258 @[RegMapper.scala 142:18] + node _T_4260 = eq(_T_4239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4261 = or(UInt<1>("h01"), _T_4260) @[RegMapper.scala 143:31] + _T_2522[9] <= _T_4261 @[RegMapper.scala 143:18] + node _T_4263 = eq(_T_4242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4264 = or(UInt<1>("h01"), _T_4263) @[RegMapper.scala 144:31] + _T_2710[9] <= _T_4264 @[RegMapper.scala 144:18] + node _T_4266 = eq(_T_4246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4267 = or(UInt<1>("h01"), _T_4266) @[RegMapper.scala 145:31] + _T_2898[9] <= _T_4267 @[RegMapper.scala 145:18] + node _T_4268 = shl(UInt<3>("h04"), 8) @[RegMapper.scala 150:47] + node _T_4270 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_4271 = and(_T_4268, _T_4270) @[RegMapper.scala 150:55] + node _T_4272 = or(_T_4232, _T_4271) @[RegMapper.scala 150:35] + node _T_4273 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_4275 = neq(_T_4273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4276 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_4277 = not(_T_4276) @[RegMapper.scala 136:45] + node _T_4279 = eq(_T_4277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4280 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_4282 = neq(_T_4280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4283 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_4284 = not(_T_4283) @[RegMapper.scala 138:44] + node _T_4286 = eq(_T_4284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4287 = and(_T_1958[10], _T_4275) @[RegMapper.scala 140:69] + node _T_4288 = and(_T_3086[10], _T_4282) @[RegMapper.scala 140:91] + node _T_4291 = and(_T_2146[10], _T_4279) @[RegMapper.scala 141:62] + node _T_4292 = and(_T_3274[10], _T_4286) @[RegMapper.scala 141:84] + node _T_4293 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_4297 = eq(_T_4275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4298 = or(UInt<1>("h01"), _T_4297) @[RegMapper.scala 142:31] + _T_2334[10] <= _T_4298 @[RegMapper.scala 142:18] + node _T_4300 = eq(_T_4279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4301 = or(UInt<1>("h01"), _T_4300) @[RegMapper.scala 143:31] + _T_2522[10] <= _T_4301 @[RegMapper.scala 143:18] + node _T_4303 = eq(_T_4282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4304 = or(UInt<1>("h01"), _T_4303) @[RegMapper.scala 144:31] + _T_2710[10] <= _T_4304 @[RegMapper.scala 144:18] + node _T_4306 = eq(_T_4286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4307 = or(UInt<1>("h01"), _T_4306) @[RegMapper.scala 145:31] + _T_2898[10] <= _T_4307 @[RegMapper.scala 145:18] + node _T_4308 = shl(UInt<8>("h0f0"), 16) @[RegMapper.scala 150:47] + node _T_4310 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_4311 = and(_T_4308, _T_4310) @[RegMapper.scala 150:55] + node _T_4312 = or(_T_4272, _T_4311) @[RegMapper.scala 150:35] + node _T_4313 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_4315 = neq(_T_4313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4316 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_4317 = not(_T_4316) @[RegMapper.scala 136:45] + node _T_4319 = eq(_T_4317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4320 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_4322 = neq(_T_4320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4323 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_4324 = not(_T_4323) @[RegMapper.scala 138:44] + node _T_4326 = eq(_T_4324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4327 = and(_T_1958[11], _T_4315) @[RegMapper.scala 140:69] + node _T_4328 = and(_T_3086[11], _T_4322) @[RegMapper.scala 140:91] + node _T_4331 = and(_T_2146[11], _T_4319) @[RegMapper.scala 141:62] + node _T_4332 = and(_T_3274[11], _T_4326) @[RegMapper.scala 141:84] + node _T_4333 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_4337 = eq(_T_4315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4338 = or(UInt<1>("h01"), _T_4337) @[RegMapper.scala 142:31] + _T_2334[11] <= _T_4338 @[RegMapper.scala 142:18] + node _T_4340 = eq(_T_4319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4341 = or(UInt<1>("h01"), _T_4340) @[RegMapper.scala 143:31] + _T_2522[11] <= _T_4341 @[RegMapper.scala 143:18] + node _T_4343 = eq(_T_4322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4344 = or(UInt<1>("h01"), _T_4343) @[RegMapper.scala 144:31] + _T_2710[11] <= _T_4344 @[RegMapper.scala 144:18] + node _T_4346 = eq(_T_4326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4347 = or(UInt<1>("h01"), _T_4346) @[RegMapper.scala 145:31] + _T_2898[11] <= _T_4347 @[RegMapper.scala 145:18] + node _T_4348 = shl(UInt<8>("h0ff"), 24) @[RegMapper.scala 150:47] + node _T_4350 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_4351 = and(_T_4348, _T_4350) @[RegMapper.scala 150:55] + node _T_4352 = or(_T_4312, _T_4351) @[RegMapper.scala 150:35] + node _T_4353 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_4355 = neq(_T_4353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4356 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_4357 = not(_T_4356) @[RegMapper.scala 136:45] + node _T_4359 = eq(_T_4357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4360 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_4362 = neq(_T_4360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4363 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_4364 = not(_T_4363) @[RegMapper.scala 138:44] + node _T_4366 = eq(_T_4364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4367 = and(_T_1958[12], _T_4355) @[RegMapper.scala 140:69] + node _T_4368 = and(_T_3086[12], _T_4362) @[RegMapper.scala 140:91] + node _T_4371 = and(_T_2146[12], _T_4359) @[RegMapper.scala 141:62] + node _T_4372 = and(_T_3274[12], _T_4366) @[RegMapper.scala 141:84] + node _T_4373 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_4377 = eq(_T_4355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4378 = or(UInt<1>("h01"), _T_4377) @[RegMapper.scala 142:31] + _T_2334[12] <= _T_4378 @[RegMapper.scala 142:18] + node _T_4380 = eq(_T_4359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4381 = or(UInt<1>("h01"), _T_4380) @[RegMapper.scala 143:31] + _T_2522[12] <= _T_4381 @[RegMapper.scala 143:18] + node _T_4383 = eq(_T_4362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4384 = or(UInt<1>("h01"), _T_4383) @[RegMapper.scala 144:31] + _T_2710[12] <= _T_4384 @[RegMapper.scala 144:18] + node _T_4386 = eq(_T_4366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4387 = or(UInt<1>("h01"), _T_4386) @[RegMapper.scala 145:31] + _T_2898[12] <= _T_4387 @[RegMapper.scala 145:18] + node _T_4388 = shl(UInt<7>("h06f"), 32) @[RegMapper.scala 150:47] + node _T_4390 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_4391 = and(_T_4388, _T_4390) @[RegMapper.scala 150:55] + node _T_4392 = or(_T_4352, _T_4391) @[RegMapper.scala 150:35] + node _T_4393 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_4395 = neq(_T_4393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4396 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_4397 = not(_T_4396) @[RegMapper.scala 136:45] + node _T_4399 = eq(_T_4397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4400 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_4402 = neq(_T_4400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4403 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_4404 = not(_T_4403) @[RegMapper.scala 138:44] + node _T_4406 = eq(_T_4404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4407 = and(_T_1958[13], _T_4395) @[RegMapper.scala 140:69] + node _T_4408 = and(_T_3086[13], _T_4402) @[RegMapper.scala 140:91] + node _T_4411 = and(_T_2146[13], _T_4399) @[RegMapper.scala 141:62] + node _T_4412 = and(_T_3274[13], _T_4406) @[RegMapper.scala 141:84] + node _T_4413 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_4417 = eq(_T_4395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4418 = or(UInt<1>("h01"), _T_4417) @[RegMapper.scala 142:31] + _T_2334[13] <= _T_4418 @[RegMapper.scala 142:18] + node _T_4420 = eq(_T_4399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4421 = or(UInt<1>("h01"), _T_4420) @[RegMapper.scala 143:31] + _T_2522[13] <= _T_4421 @[RegMapper.scala 143:18] + node _T_4423 = eq(_T_4402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4424 = or(UInt<1>("h01"), _T_4423) @[RegMapper.scala 144:31] + _T_2710[13] <= _T_4424 @[RegMapper.scala 144:18] + node _T_4426 = eq(_T_4406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4427 = or(UInt<1>("h01"), _T_4426) @[RegMapper.scala 145:31] + _T_2898[13] <= _T_4427 @[RegMapper.scala 145:18] + node _T_4428 = shl(UInt<1>("h00"), 40) @[RegMapper.scala 150:47] + node _T_4430 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_4431 = and(_T_4428, _T_4430) @[RegMapper.scala 150:55] + node _T_4432 = or(_T_4392, _T_4431) @[RegMapper.scala 150:35] + node _T_4433 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_4435 = neq(_T_4433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4436 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_4437 = not(_T_4436) @[RegMapper.scala 136:45] + node _T_4439 = eq(_T_4437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4440 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_4442 = neq(_T_4440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4443 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_4444 = not(_T_4443) @[RegMapper.scala 138:44] + node _T_4446 = eq(_T_4444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4447 = and(_T_1958[14], _T_4435) @[RegMapper.scala 140:69] + node _T_4448 = and(_T_3086[14], _T_4442) @[RegMapper.scala 140:91] + node _T_4451 = and(_T_2146[14], _T_4439) @[RegMapper.scala 141:62] + node _T_4452 = and(_T_3274[14], _T_4446) @[RegMapper.scala 141:84] + node _T_4453 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_4457 = eq(_T_4435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4458 = or(UInt<1>("h01"), _T_4457) @[RegMapper.scala 142:31] + _T_2334[14] <= _T_4458 @[RegMapper.scala 142:18] + node _T_4460 = eq(_T_4439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4461 = or(UInt<1>("h01"), _T_4460) @[RegMapper.scala 143:31] + _T_2522[14] <= _T_4461 @[RegMapper.scala 143:18] + node _T_4463 = eq(_T_4442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4464 = or(UInt<1>("h01"), _T_4463) @[RegMapper.scala 144:31] + _T_2710[14] <= _T_4464 @[RegMapper.scala 144:18] + node _T_4466 = eq(_T_4446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4467 = or(UInt<1>("h01"), _T_4466) @[RegMapper.scala 145:31] + _T_2898[14] <= _T_4467 @[RegMapper.scala 145:18] + node _T_4468 = shl(UInt<8>("h080"), 48) @[RegMapper.scala 150:47] + node _T_4470 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_4471 = and(_T_4468, _T_4470) @[RegMapper.scala 150:55] + node _T_4472 = or(_T_4432, _T_4471) @[RegMapper.scala 150:35] + node _T_4473 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_4475 = neq(_T_4473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4476 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_4477 = not(_T_4476) @[RegMapper.scala 136:45] + node _T_4479 = eq(_T_4477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4480 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_4482 = neq(_T_4480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4483 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_4484 = not(_T_4483) @[RegMapper.scala 138:44] + node _T_4486 = eq(_T_4484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4487 = and(_T_1958[15], _T_4475) @[RegMapper.scala 140:69] + node _T_4488 = and(_T_3086[15], _T_4482) @[RegMapper.scala 140:91] + node _T_4491 = and(_T_2146[15], _T_4479) @[RegMapper.scala 141:62] + node _T_4492 = and(_T_3274[15], _T_4486) @[RegMapper.scala 141:84] + node _T_4493 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_4497 = eq(_T_4475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4498 = or(UInt<1>("h01"), _T_4497) @[RegMapper.scala 142:31] + _T_2334[15] <= _T_4498 @[RegMapper.scala 142:18] + node _T_4500 = eq(_T_4479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4501 = or(UInt<1>("h01"), _T_4500) @[RegMapper.scala 143:31] + _T_2522[15] <= _T_4501 @[RegMapper.scala 143:18] + node _T_4503 = eq(_T_4482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4504 = or(UInt<1>("h01"), _T_4503) @[RegMapper.scala 144:31] + _T_2710[15] <= _T_4504 @[RegMapper.scala 144:18] + node _T_4506 = eq(_T_4486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4507 = or(UInt<1>("h01"), _T_4506) @[RegMapper.scala 145:31] + _T_2898[15] <= _T_4507 @[RegMapper.scala 145:18] + node _T_4508 = shl(UInt<1>("h00"), 56) @[RegMapper.scala 150:47] + node _T_4510 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_4511 = and(_T_4508, _T_4510) @[RegMapper.scala 150:55] + node _T_4512 = or(_T_4472, _T_4511) @[RegMapper.scala 150:35] + node _T_4513 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_4515 = neq(_T_4513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4516 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_4517 = not(_T_4516) @[RegMapper.scala 136:45] + node _T_4519 = eq(_T_4517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4520 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_4522 = neq(_T_4520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4523 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_4524 = not(_T_4523) @[RegMapper.scala 138:44] + node _T_4526 = eq(_T_4524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4527 = and(_T_1958[16], _T_4515) @[RegMapper.scala 140:69] + node _T_4528 = and(_T_3086[16], _T_4522) @[RegMapper.scala 140:91] + node _T_4531 = and(_T_2146[16], _T_4519) @[RegMapper.scala 141:62] + node _T_4532 = and(_T_3274[16], _T_4526) @[RegMapper.scala 141:84] + node _T_4533 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_4537 = eq(_T_4515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4538 = or(UInt<1>("h01"), _T_4537) @[RegMapper.scala 142:31] + _T_2334[16] <= _T_4538 @[RegMapper.scala 142:18] + node _T_4540 = eq(_T_4519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4541 = or(UInt<1>("h01"), _T_4540) @[RegMapper.scala 143:31] + _T_2522[16] <= _T_4541 @[RegMapper.scala 143:18] + node _T_4543 = eq(_T_4522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4544 = or(UInt<1>("h01"), _T_4543) @[RegMapper.scala 144:31] + _T_2710[16] <= _T_4544 @[RegMapper.scala 144:18] + node _T_4546 = eq(_T_4526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4547 = or(UInt<1>("h01"), _T_4546) @[RegMapper.scala 145:31] + _T_2898[16] <= _T_4547 @[RegMapper.scala 145:18] + node _T_4548 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_4550 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_4551 = and(_T_4548, _T_4550) @[RegMapper.scala 150:55] + node _T_4552 = or(UInt<1>("h00"), _T_4551) @[RegMapper.scala 150:35] + node _T_4553 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_4555 = neq(_T_4553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4556 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_4557 = not(_T_4556) @[RegMapper.scala 136:45] + node _T_4559 = eq(_T_4557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4560 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_4562 = neq(_T_4560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4563 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_4564 = not(_T_4563) @[RegMapper.scala 138:44] + node _T_4566 = eq(_T_4564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4567 = and(_T_1958[17], _T_4555) @[RegMapper.scala 140:69] + node _T_4568 = and(_T_3086[17], _T_4562) @[RegMapper.scala 140:91] + node _T_4571 = and(_T_2146[17], _T_4559) @[RegMapper.scala 141:62] + node _T_4572 = and(_T_3274[17], _T_4566) @[RegMapper.scala 141:84] + node _T_4573 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_4577 = eq(_T_4555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4578 = or(UInt<1>("h01"), _T_4577) @[RegMapper.scala 142:31] + _T_2334[17] <= _T_4578 @[RegMapper.scala 142:18] + node _T_4580 = eq(_T_4559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4581 = or(UInt<1>("h01"), _T_4580) @[RegMapper.scala 143:31] + _T_2522[17] <= _T_4581 @[RegMapper.scala 143:18] + node _T_4583 = eq(_T_4562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4584 = or(UInt<1>("h01"), _T_4583) @[RegMapper.scala 144:31] + _T_2710[17] <= _T_4584 @[RegMapper.scala 144:18] + node _T_4586 = eq(_T_4566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4587 = or(UInt<1>("h01"), _T_4586) @[RegMapper.scala 145:31] + _T_2898[17] <= _T_4587 @[RegMapper.scala 145:18] + node _T_4588 = shl(UInt<6>("h024"), 8) @[RegMapper.scala 150:47] + node _T_4590 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_4591 = and(_T_4588, _T_4590) @[RegMapper.scala 150:55] + node _T_4592 = or(_T_4552, _T_4591) @[RegMapper.scala 150:35] + node _T_4593 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_4595 = neq(_T_4593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4596 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_4597 = not(_T_4596) @[RegMapper.scala 136:45] + node _T_4599 = eq(_T_4597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4600 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_4602 = neq(_T_4600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4603 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_4604 = not(_T_4603) @[RegMapper.scala 138:44] + node _T_4606 = eq(_T_4604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4607 = and(_T_1958[18], _T_4595) @[RegMapper.scala 140:69] + node _T_4608 = and(_T_3086[18], _T_4602) @[RegMapper.scala 140:91] + node _T_4611 = and(_T_2146[18], _T_4599) @[RegMapper.scala 141:62] + node _T_4612 = and(_T_3274[18], _T_4606) @[RegMapper.scala 141:84] + node _T_4613 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_4617 = eq(_T_4595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4618 = or(UInt<1>("h01"), _T_4617) @[RegMapper.scala 142:31] + _T_2334[18] <= _T_4618 @[RegMapper.scala 142:18] + node _T_4620 = eq(_T_4599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4621 = or(UInt<1>("h01"), _T_4620) @[RegMapper.scala 143:31] + _T_2522[18] <= _T_4621 @[RegMapper.scala 143:18] + node _T_4623 = eq(_T_4602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4624 = or(UInt<1>("h01"), _T_4623) @[RegMapper.scala 144:31] + _T_2710[18] <= _T_4624 @[RegMapper.scala 144:18] + node _T_4626 = eq(_T_4606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4627 = or(UInt<1>("h01"), _T_4626) @[RegMapper.scala 145:31] + _T_2898[18] <= _T_4627 @[RegMapper.scala 145:18] + node _T_4628 = shl(UInt<1>("h00"), 16) @[RegMapper.scala 150:47] + node _T_4630 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_4631 = and(_T_4628, _T_4630) @[RegMapper.scala 150:55] + node _T_4632 = or(_T_4592, _T_4631) @[RegMapper.scala 150:35] + node _T_4633 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_4635 = neq(_T_4633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4636 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_4637 = not(_T_4636) @[RegMapper.scala 136:45] + node _T_4639 = eq(_T_4637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4640 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_4642 = neq(_T_4640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4643 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_4644 = not(_T_4643) @[RegMapper.scala 138:44] + node _T_4646 = eq(_T_4644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4647 = and(_T_1958[19], _T_4635) @[RegMapper.scala 140:69] + node _T_4648 = and(_T_3086[19], _T_4642) @[RegMapper.scala 140:91] + node _T_4651 = and(_T_2146[19], _T_4639) @[RegMapper.scala 141:62] + node _T_4652 = and(_T_3274[19], _T_4646) @[RegMapper.scala 141:84] + node _T_4653 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_4657 = eq(_T_4635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4658 = or(UInt<1>("h01"), _T_4657) @[RegMapper.scala 142:31] + _T_2334[19] <= _T_4658 @[RegMapper.scala 142:18] + node _T_4660 = eq(_T_4639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4661 = or(UInt<1>("h01"), _T_4660) @[RegMapper.scala 143:31] + _T_2522[19] <= _T_4661 @[RegMapper.scala 143:18] + node _T_4663 = eq(_T_4642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4664 = or(UInt<1>("h01"), _T_4663) @[RegMapper.scala 144:31] + _T_2710[19] <= _T_4664 @[RegMapper.scala 144:18] + node _T_4666 = eq(_T_4646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4667 = or(UInt<1>("h01"), _T_4666) @[RegMapper.scala 145:31] + _T_2898[19] <= _T_4667 @[RegMapper.scala 145:18] + node _T_4668 = shl(UInt<7>("h07b"), 24) @[RegMapper.scala 150:47] + node _T_4670 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_4671 = and(_T_4668, _T_4670) @[RegMapper.scala 150:55] + node _T_4672 = or(_T_4632, _T_4671) @[RegMapper.scala 150:35] + node _T_4673 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_4675 = neq(_T_4673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4676 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_4677 = not(_T_4676) @[RegMapper.scala 136:45] + node _T_4679 = eq(_T_4677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4680 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_4682 = neq(_T_4680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4683 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_4684 = not(_T_4683) @[RegMapper.scala 138:44] + node _T_4686 = eq(_T_4684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4687 = and(_T_1958[20], _T_4675) @[RegMapper.scala 140:69] + node _T_4688 = and(_T_3086[20], _T_4682) @[RegMapper.scala 140:91] + node _T_4691 = and(_T_2146[20], _T_4679) @[RegMapper.scala 141:62] + node _T_4692 = and(_T_3274[20], _T_4686) @[RegMapper.scala 141:84] + node _T_4693 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_4697 = eq(_T_4675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4698 = or(UInt<1>("h01"), _T_4697) @[RegMapper.scala 142:31] + _T_2334[20] <= _T_4698 @[RegMapper.scala 142:18] + node _T_4700 = eq(_T_4679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4701 = or(UInt<1>("h01"), _T_4700) @[RegMapper.scala 143:31] + _T_2522[20] <= _T_4701 @[RegMapper.scala 143:18] + node _T_4703 = eq(_T_4682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4704 = or(UInt<1>("h01"), _T_4703) @[RegMapper.scala 144:31] + _T_2710[20] <= _T_4704 @[RegMapper.scala 144:18] + node _T_4706 = eq(_T_4686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4707 = or(UInt<1>("h01"), _T_4706) @[RegMapper.scala 145:31] + _T_2898[20] <= _T_4707 @[RegMapper.scala 145:18] + node _T_4708 = shl(UInt<5>("h013"), 32) @[RegMapper.scala 150:47] + node _T_4710 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_4711 = and(_T_4708, _T_4710) @[RegMapper.scala 150:55] + node _T_4712 = or(_T_4672, _T_4711) @[RegMapper.scala 150:35] + node _T_4713 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_4715 = neq(_T_4713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4716 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_4717 = not(_T_4716) @[RegMapper.scala 136:45] + node _T_4719 = eq(_T_4717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4720 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_4722 = neq(_T_4720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4723 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_4724 = not(_T_4723) @[RegMapper.scala 138:44] + node _T_4726 = eq(_T_4724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4727 = and(_T_1958[21], _T_4715) @[RegMapper.scala 140:69] + node _T_4728 = and(_T_3086[21], _T_4722) @[RegMapper.scala 140:91] + node _T_4731 = and(_T_2146[21], _T_4719) @[RegMapper.scala 141:62] + node _T_4732 = and(_T_3274[21], _T_4726) @[RegMapper.scala 141:84] + node _T_4733 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_4737 = eq(_T_4715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4738 = or(UInt<1>("h01"), _T_4737) @[RegMapper.scala 142:31] + _T_2334[21] <= _T_4738 @[RegMapper.scala 142:18] + node _T_4740 = eq(_T_4719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4741 = or(UInt<1>("h01"), _T_4740) @[RegMapper.scala 143:31] + _T_2522[21] <= _T_4741 @[RegMapper.scala 143:18] + node _T_4743 = eq(_T_4722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4744 = or(UInt<1>("h01"), _T_4743) @[RegMapper.scala 144:31] + _T_2710[21] <= _T_4744 @[RegMapper.scala 144:18] + node _T_4746 = eq(_T_4726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4747 = or(UInt<1>("h01"), _T_4746) @[RegMapper.scala 145:31] + _T_2898[21] <= _T_4747 @[RegMapper.scala 145:18] + node _T_4748 = shl(UInt<7>("h074"), 40) @[RegMapper.scala 150:47] + node _T_4750 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_4751 = and(_T_4748, _T_4750) @[RegMapper.scala 150:55] + node _T_4752 = or(_T_4712, _T_4751) @[RegMapper.scala 150:35] + node _T_4753 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_4755 = neq(_T_4753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4756 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_4757 = not(_T_4756) @[RegMapper.scala 136:45] + node _T_4759 = eq(_T_4757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4760 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_4762 = neq(_T_4760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4763 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_4764 = not(_T_4763) @[RegMapper.scala 138:44] + node _T_4766 = eq(_T_4764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4767 = and(_T_1958[22], _T_4755) @[RegMapper.scala 140:69] + node _T_4768 = and(_T_3086[22], _T_4762) @[RegMapper.scala 140:91] + node _T_4771 = and(_T_2146[22], _T_4759) @[RegMapper.scala 141:62] + node _T_4772 = and(_T_3274[22], _T_4766) @[RegMapper.scala 141:84] + node _T_4773 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_4777 = eq(_T_4755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4778 = or(UInt<1>("h01"), _T_4777) @[RegMapper.scala 142:31] + _T_2334[22] <= _T_4778 @[RegMapper.scala 142:18] + node _T_4780 = eq(_T_4759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4781 = or(UInt<1>("h01"), _T_4780) @[RegMapper.scala 143:31] + _T_2522[22] <= _T_4781 @[RegMapper.scala 143:18] + node _T_4783 = eq(_T_4762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4784 = or(UInt<1>("h01"), _T_4783) @[RegMapper.scala 144:31] + _T_2710[22] <= _T_4784 @[RegMapper.scala 144:18] + node _T_4786 = eq(_T_4766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4787 = or(UInt<1>("h01"), _T_4786) @[RegMapper.scala 145:31] + _T_2898[22] <= _T_4787 @[RegMapper.scala 145:18] + node _T_4788 = shl(UInt<8>("h084"), 48) @[RegMapper.scala 150:47] + node _T_4790 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_4791 = and(_T_4788, _T_4790) @[RegMapper.scala 150:55] + node _T_4792 = or(_T_4752, _T_4791) @[RegMapper.scala 150:35] + node _T_4793 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_4795 = neq(_T_4793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4796 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_4797 = not(_T_4796) @[RegMapper.scala 136:45] + node _T_4799 = eq(_T_4797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4800 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_4802 = neq(_T_4800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4803 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_4804 = not(_T_4803) @[RegMapper.scala 138:44] + node _T_4806 = eq(_T_4804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4807 = and(_T_1958[23], _T_4795) @[RegMapper.scala 140:69] + node _T_4808 = and(_T_3086[23], _T_4802) @[RegMapper.scala 140:91] + node _T_4811 = and(_T_2146[23], _T_4799) @[RegMapper.scala 141:62] + node _T_4812 = and(_T_3274[23], _T_4806) @[RegMapper.scala 141:84] + node _T_4813 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_4817 = eq(_T_4795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4818 = or(UInt<1>("h01"), _T_4817) @[RegMapper.scala 142:31] + _T_2334[23] <= _T_4818 @[RegMapper.scala 142:18] + node _T_4820 = eq(_T_4799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4821 = or(UInt<1>("h01"), _T_4820) @[RegMapper.scala 143:31] + _T_2522[23] <= _T_4821 @[RegMapper.scala 143:18] + node _T_4823 = eq(_T_4802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4824 = or(UInt<1>("h01"), _T_4823) @[RegMapper.scala 144:31] + _T_2710[23] <= _T_4824 @[RegMapper.scala 144:18] + node _T_4826 = eq(_T_4806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4827 = or(UInt<1>("h01"), _T_4826) @[RegMapper.scala 145:31] + _T_2898[23] <= _T_4827 @[RegMapper.scala 145:18] + node _T_4828 = shl(UInt<1>("h00"), 56) @[RegMapper.scala 150:47] + node _T_4830 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_4831 = and(_T_4828, _T_4830) @[RegMapper.scala 150:55] + node _T_4832 = or(_T_4792, _T_4831) @[RegMapper.scala 150:35] + node _T_4833 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_4835 = neq(_T_4833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4836 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_4837 = not(_T_4836) @[RegMapper.scala 136:45] + node _T_4839 = eq(_T_4837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4840 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_4842 = neq(_T_4840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4843 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_4844 = not(_T_4843) @[RegMapper.scala 138:44] + node _T_4846 = eq(_T_4844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4847 = and(_T_1958[24], _T_4835) @[RegMapper.scala 140:69] + node _T_4848 = and(_T_3086[24], _T_4842) @[RegMapper.scala 140:91] + node _T_4851 = and(_T_2146[24], _T_4839) @[RegMapper.scala 141:62] + node _T_4852 = and(_T_3274[24], _T_4846) @[RegMapper.scala 141:84] + node _T_4853 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_4852 : @[RegField.scala 70:88] + ramMem[32] <= _T_4853 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_4857 = eq(_T_4835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4858 = or(UInt<1>("h01"), _T_4857) @[RegMapper.scala 142:31] + _T_2334[24] <= _T_4858 @[RegMapper.scala 142:18] + node _T_4860 = eq(_T_4839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4861 = or(UInt<1>("h01"), _T_4860) @[RegMapper.scala 143:31] + _T_2522[24] <= _T_4861 @[RegMapper.scala 143:18] + node _T_4863 = eq(_T_4842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4864 = or(UInt<1>("h01"), _T_4863) @[RegMapper.scala 144:31] + _T_2710[24] <= _T_4864 @[RegMapper.scala 144:18] + node _T_4866 = eq(_T_4846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4867 = or(UInt<1>("h01"), _T_4866) @[RegMapper.scala 145:31] + _T_2898[24] <= _T_4867 @[RegMapper.scala 145:18] + node _T_4868 = shl(ramMem[32], 0) @[RegMapper.scala 150:47] + node _T_4870 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_4871 = and(_T_4868, _T_4870) @[RegMapper.scala 150:55] + node _T_4872 = or(UInt<1>("h00"), _T_4871) @[RegMapper.scala 150:35] + node _T_4873 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_4875 = neq(_T_4873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4876 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_4877 = not(_T_4876) @[RegMapper.scala 136:45] + node _T_4879 = eq(_T_4877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4880 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_4882 = neq(_T_4880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4883 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_4884 = not(_T_4883) @[RegMapper.scala 138:44] + node _T_4886 = eq(_T_4884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4887 = and(_T_1958[25], _T_4875) @[RegMapper.scala 140:69] + node _T_4888 = and(_T_3086[25], _T_4882) @[RegMapper.scala 140:91] + node _T_4891 = and(_T_2146[25], _T_4879) @[RegMapper.scala 141:62] + node _T_4892 = and(_T_3274[25], _T_4886) @[RegMapper.scala 141:84] + node _T_4893 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_4892 : @[RegField.scala 70:88] + ramMem[33] <= _T_4893 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_4897 = eq(_T_4875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4898 = or(UInt<1>("h01"), _T_4897) @[RegMapper.scala 142:31] + _T_2334[25] <= _T_4898 @[RegMapper.scala 142:18] + node _T_4900 = eq(_T_4879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4901 = or(UInt<1>("h01"), _T_4900) @[RegMapper.scala 143:31] + _T_2522[25] <= _T_4901 @[RegMapper.scala 143:18] + node _T_4903 = eq(_T_4882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4904 = or(UInt<1>("h01"), _T_4903) @[RegMapper.scala 144:31] + _T_2710[25] <= _T_4904 @[RegMapper.scala 144:18] + node _T_4906 = eq(_T_4886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4907 = or(UInt<1>("h01"), _T_4906) @[RegMapper.scala 145:31] + _T_2898[25] <= _T_4907 @[RegMapper.scala 145:18] + node _T_4908 = shl(ramMem[33], 8) @[RegMapper.scala 150:47] + node _T_4910 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_4911 = and(_T_4908, _T_4910) @[RegMapper.scala 150:55] + node _T_4912 = or(_T_4872, _T_4911) @[RegMapper.scala 150:35] + node _T_4913 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_4915 = neq(_T_4913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4916 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_4917 = not(_T_4916) @[RegMapper.scala 136:45] + node _T_4919 = eq(_T_4917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4920 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_4922 = neq(_T_4920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4923 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_4924 = not(_T_4923) @[RegMapper.scala 138:44] + node _T_4926 = eq(_T_4924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4927 = and(_T_1958[26], _T_4915) @[RegMapper.scala 140:69] + node _T_4928 = and(_T_3086[26], _T_4922) @[RegMapper.scala 140:91] + node _T_4931 = and(_T_2146[26], _T_4919) @[RegMapper.scala 141:62] + node _T_4932 = and(_T_3274[26], _T_4926) @[RegMapper.scala 141:84] + node _T_4933 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_4932 : @[RegField.scala 70:88] + ramMem[34] <= _T_4933 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_4937 = eq(_T_4915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4938 = or(UInt<1>("h01"), _T_4937) @[RegMapper.scala 142:31] + _T_2334[26] <= _T_4938 @[RegMapper.scala 142:18] + node _T_4940 = eq(_T_4919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4941 = or(UInt<1>("h01"), _T_4940) @[RegMapper.scala 143:31] + _T_2522[26] <= _T_4941 @[RegMapper.scala 143:18] + node _T_4943 = eq(_T_4922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4944 = or(UInt<1>("h01"), _T_4943) @[RegMapper.scala 144:31] + _T_2710[26] <= _T_4944 @[RegMapper.scala 144:18] + node _T_4946 = eq(_T_4926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4947 = or(UInt<1>("h01"), _T_4946) @[RegMapper.scala 145:31] + _T_2898[26] <= _T_4947 @[RegMapper.scala 145:18] + node _T_4948 = shl(ramMem[34], 16) @[RegMapper.scala 150:47] + node _T_4950 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_4951 = and(_T_4948, _T_4950) @[RegMapper.scala 150:55] + node _T_4952 = or(_T_4912, _T_4951) @[RegMapper.scala 150:35] + node _T_4953 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_4955 = neq(_T_4953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4956 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_4957 = not(_T_4956) @[RegMapper.scala 136:45] + node _T_4959 = eq(_T_4957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_4960 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_4962 = neq(_T_4960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_4963 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_4964 = not(_T_4963) @[RegMapper.scala 138:44] + node _T_4966 = eq(_T_4964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_4967 = and(_T_1958[27], _T_4955) @[RegMapper.scala 140:69] + node _T_4968 = and(_T_3086[27], _T_4962) @[RegMapper.scala 140:91] + node _T_4971 = and(_T_2146[27], _T_4959) @[RegMapper.scala 141:62] + node _T_4972 = and(_T_3274[27], _T_4966) @[RegMapper.scala 141:84] + node _T_4973 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_4972 : @[RegField.scala 70:88] + ramMem[35] <= _T_4973 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_4977 = eq(_T_4955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_4978 = or(UInt<1>("h01"), _T_4977) @[RegMapper.scala 142:31] + _T_2334[27] <= _T_4978 @[RegMapper.scala 142:18] + node _T_4980 = eq(_T_4959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_4981 = or(UInt<1>("h01"), _T_4980) @[RegMapper.scala 143:31] + _T_2522[27] <= _T_4981 @[RegMapper.scala 143:18] + node _T_4983 = eq(_T_4962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_4984 = or(UInt<1>("h01"), _T_4983) @[RegMapper.scala 144:31] + _T_2710[27] <= _T_4984 @[RegMapper.scala 144:18] + node _T_4986 = eq(_T_4966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_4987 = or(UInt<1>("h01"), _T_4986) @[RegMapper.scala 145:31] + _T_2898[27] <= _T_4987 @[RegMapper.scala 145:18] + node _T_4988 = shl(ramMem[35], 24) @[RegMapper.scala 150:47] + node _T_4990 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_4991 = and(_T_4988, _T_4990) @[RegMapper.scala 150:55] + node _T_4992 = or(_T_4952, _T_4991) @[RegMapper.scala 150:35] + node _T_4993 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_4995 = neq(_T_4993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_4996 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_4997 = not(_T_4996) @[RegMapper.scala 136:45] + node _T_4999 = eq(_T_4997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5000 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_5002 = neq(_T_5000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5003 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_5004 = not(_T_5003) @[RegMapper.scala 138:44] + node _T_5006 = eq(_T_5004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5007 = and(_T_1958[28], _T_4995) @[RegMapper.scala 140:69] + node _T_5008 = and(_T_3086[28], _T_5002) @[RegMapper.scala 140:91] + node _T_5011 = and(_T_2146[28], _T_4999) @[RegMapper.scala 141:62] + node _T_5012 = and(_T_3274[28], _T_5006) @[RegMapper.scala 141:84] + node _T_5013 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_5012 : @[RegField.scala 70:88] + ramMem[36] <= _T_5013 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5017 = eq(_T_4995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5018 = or(UInt<1>("h01"), _T_5017) @[RegMapper.scala 142:31] + _T_2334[28] <= _T_5018 @[RegMapper.scala 142:18] + node _T_5020 = eq(_T_4999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5021 = or(UInt<1>("h01"), _T_5020) @[RegMapper.scala 143:31] + _T_2522[28] <= _T_5021 @[RegMapper.scala 143:18] + node _T_5023 = eq(_T_5002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5024 = or(UInt<1>("h01"), _T_5023) @[RegMapper.scala 144:31] + _T_2710[28] <= _T_5024 @[RegMapper.scala 144:18] + node _T_5026 = eq(_T_5006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5027 = or(UInt<1>("h01"), _T_5026) @[RegMapper.scala 145:31] + _T_2898[28] <= _T_5027 @[RegMapper.scala 145:18] + node _T_5028 = shl(ramMem[36], 32) @[RegMapper.scala 150:47] + node _T_5030 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_5031 = and(_T_5028, _T_5030) @[RegMapper.scala 150:55] + node _T_5032 = or(_T_4992, _T_5031) @[RegMapper.scala 150:35] + node _T_5033 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_5035 = neq(_T_5033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5036 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_5037 = not(_T_5036) @[RegMapper.scala 136:45] + node _T_5039 = eq(_T_5037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5040 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_5042 = neq(_T_5040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5043 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_5044 = not(_T_5043) @[RegMapper.scala 138:44] + node _T_5046 = eq(_T_5044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5047 = and(_T_1958[29], _T_5035) @[RegMapper.scala 140:69] + node _T_5048 = and(_T_3086[29], _T_5042) @[RegMapper.scala 140:91] + node _T_5051 = and(_T_2146[29], _T_5039) @[RegMapper.scala 141:62] + node _T_5052 = and(_T_3274[29], _T_5046) @[RegMapper.scala 141:84] + node _T_5053 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_5052 : @[RegField.scala 70:88] + ramMem[37] <= _T_5053 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5057 = eq(_T_5035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5058 = or(UInt<1>("h01"), _T_5057) @[RegMapper.scala 142:31] + _T_2334[29] <= _T_5058 @[RegMapper.scala 142:18] + node _T_5060 = eq(_T_5039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5061 = or(UInt<1>("h01"), _T_5060) @[RegMapper.scala 143:31] + _T_2522[29] <= _T_5061 @[RegMapper.scala 143:18] + node _T_5063 = eq(_T_5042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5064 = or(UInt<1>("h01"), _T_5063) @[RegMapper.scala 144:31] + _T_2710[29] <= _T_5064 @[RegMapper.scala 144:18] + node _T_5066 = eq(_T_5046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5067 = or(UInt<1>("h01"), _T_5066) @[RegMapper.scala 145:31] + _T_2898[29] <= _T_5067 @[RegMapper.scala 145:18] + node _T_5068 = shl(ramMem[37], 40) @[RegMapper.scala 150:47] + node _T_5070 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_5071 = and(_T_5068, _T_5070) @[RegMapper.scala 150:55] + node _T_5072 = or(_T_5032, _T_5071) @[RegMapper.scala 150:35] + node _T_5073 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_5075 = neq(_T_5073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5076 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_5077 = not(_T_5076) @[RegMapper.scala 136:45] + node _T_5079 = eq(_T_5077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5080 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_5082 = neq(_T_5080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5083 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_5084 = not(_T_5083) @[RegMapper.scala 138:44] + node _T_5086 = eq(_T_5084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5087 = and(_T_1958[30], _T_5075) @[RegMapper.scala 140:69] + node _T_5088 = and(_T_3086[30], _T_5082) @[RegMapper.scala 140:91] + node _T_5091 = and(_T_2146[30], _T_5079) @[RegMapper.scala 141:62] + node _T_5092 = and(_T_3274[30], _T_5086) @[RegMapper.scala 141:84] + node _T_5093 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_5092 : @[RegField.scala 70:88] + ramMem[38] <= _T_5093 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5097 = eq(_T_5075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5098 = or(UInt<1>("h01"), _T_5097) @[RegMapper.scala 142:31] + _T_2334[30] <= _T_5098 @[RegMapper.scala 142:18] + node _T_5100 = eq(_T_5079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5101 = or(UInt<1>("h01"), _T_5100) @[RegMapper.scala 143:31] + _T_2522[30] <= _T_5101 @[RegMapper.scala 143:18] + node _T_5103 = eq(_T_5082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5104 = or(UInt<1>("h01"), _T_5103) @[RegMapper.scala 144:31] + _T_2710[30] <= _T_5104 @[RegMapper.scala 144:18] + node _T_5106 = eq(_T_5086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5107 = or(UInt<1>("h01"), _T_5106) @[RegMapper.scala 145:31] + _T_2898[30] <= _T_5107 @[RegMapper.scala 145:18] + node _T_5108 = shl(ramMem[38], 48) @[RegMapper.scala 150:47] + node _T_5110 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_5111 = and(_T_5108, _T_5110) @[RegMapper.scala 150:55] + node _T_5112 = or(_T_5072, _T_5111) @[RegMapper.scala 150:35] + node _T_5113 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_5115 = neq(_T_5113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5116 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_5117 = not(_T_5116) @[RegMapper.scala 136:45] + node _T_5119 = eq(_T_5117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5120 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_5122 = neq(_T_5120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5123 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_5124 = not(_T_5123) @[RegMapper.scala 138:44] + node _T_5126 = eq(_T_5124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5127 = and(_T_1958[31], _T_5115) @[RegMapper.scala 140:69] + node _T_5128 = and(_T_3086[31], _T_5122) @[RegMapper.scala 140:91] + node _T_5131 = and(_T_2146[31], _T_5119) @[RegMapper.scala 141:62] + node _T_5132 = and(_T_3274[31], _T_5126) @[RegMapper.scala 141:84] + node _T_5133 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_5132 : @[RegField.scala 70:88] + ramMem[39] <= _T_5133 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5137 = eq(_T_5115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5138 = or(UInt<1>("h01"), _T_5137) @[RegMapper.scala 142:31] + _T_2334[31] <= _T_5138 @[RegMapper.scala 142:18] + node _T_5140 = eq(_T_5119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5141 = or(UInt<1>("h01"), _T_5140) @[RegMapper.scala 143:31] + _T_2522[31] <= _T_5141 @[RegMapper.scala 143:18] + node _T_5143 = eq(_T_5122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5144 = or(UInt<1>("h01"), _T_5143) @[RegMapper.scala 144:31] + _T_2710[31] <= _T_5144 @[RegMapper.scala 144:18] + node _T_5146 = eq(_T_5126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5147 = or(UInt<1>("h01"), _T_5146) @[RegMapper.scala 145:31] + _T_2898[31] <= _T_5147 @[RegMapper.scala 145:18] + node _T_5148 = shl(ramMem[39], 56) @[RegMapper.scala 150:47] + node _T_5150 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_5151 = and(_T_5148, _T_5150) @[RegMapper.scala 150:55] + node _T_5152 = or(_T_5112, _T_5151) @[RegMapper.scala 150:35] + node _T_5153 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_5155 = neq(_T_5153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5156 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_5157 = not(_T_5156) @[RegMapper.scala 136:45] + node _T_5159 = eq(_T_5157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5160 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_5162 = neq(_T_5160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5163 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_5164 = not(_T_5163) @[RegMapper.scala 138:44] + node _T_5166 = eq(_T_5164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5167 = and(_T_1958[32], _T_5155) @[RegMapper.scala 140:69] + node _T_5168 = and(_T_3086[32], _T_5162) @[RegMapper.scala 140:91] + node _T_5171 = and(_T_2146[32], _T_5159) @[RegMapper.scala 141:62] + node _T_5172 = and(_T_3274[32], _T_5166) @[RegMapper.scala 141:84] + node _T_5173 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_5172 : @[RegField.scala 70:88] + ramMem[40] <= _T_5173 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5177 = eq(_T_5155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5178 = or(UInt<1>("h01"), _T_5177) @[RegMapper.scala 142:31] + _T_2334[32] <= _T_5178 @[RegMapper.scala 142:18] + node _T_5180 = eq(_T_5159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5181 = or(UInt<1>("h01"), _T_5180) @[RegMapper.scala 143:31] + _T_2522[32] <= _T_5181 @[RegMapper.scala 143:18] + node _T_5183 = eq(_T_5162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5184 = or(UInt<1>("h01"), _T_5183) @[RegMapper.scala 144:31] + _T_2710[32] <= _T_5184 @[RegMapper.scala 144:18] + node _T_5186 = eq(_T_5166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5187 = or(UInt<1>("h01"), _T_5186) @[RegMapper.scala 145:31] + _T_2898[32] <= _T_5187 @[RegMapper.scala 145:18] + node _T_5188 = shl(ramMem[40], 0) @[RegMapper.scala 150:47] + node _T_5190 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_5191 = and(_T_5188, _T_5190) @[RegMapper.scala 150:55] + node _T_5192 = or(UInt<1>("h00"), _T_5191) @[RegMapper.scala 150:35] + node _T_5193 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_5195 = neq(_T_5193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5196 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_5197 = not(_T_5196) @[RegMapper.scala 136:45] + node _T_5199 = eq(_T_5197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5200 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_5202 = neq(_T_5200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5203 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_5204 = not(_T_5203) @[RegMapper.scala 138:44] + node _T_5206 = eq(_T_5204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5207 = and(_T_1958[33], _T_5195) @[RegMapper.scala 140:69] + node _T_5208 = and(_T_3086[33], _T_5202) @[RegMapper.scala 140:91] + node _T_5211 = and(_T_2146[33], _T_5199) @[RegMapper.scala 141:62] + node _T_5212 = and(_T_3274[33], _T_5206) @[RegMapper.scala 141:84] + node _T_5213 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_5212 : @[RegField.scala 70:88] + ramMem[41] <= _T_5213 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5217 = eq(_T_5195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5218 = or(UInt<1>("h01"), _T_5217) @[RegMapper.scala 142:31] + _T_2334[33] <= _T_5218 @[RegMapper.scala 142:18] + node _T_5220 = eq(_T_5199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5221 = or(UInt<1>("h01"), _T_5220) @[RegMapper.scala 143:31] + _T_2522[33] <= _T_5221 @[RegMapper.scala 143:18] + node _T_5223 = eq(_T_5202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5224 = or(UInt<1>("h01"), _T_5223) @[RegMapper.scala 144:31] + _T_2710[33] <= _T_5224 @[RegMapper.scala 144:18] + node _T_5226 = eq(_T_5206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5227 = or(UInt<1>("h01"), _T_5226) @[RegMapper.scala 145:31] + _T_2898[33] <= _T_5227 @[RegMapper.scala 145:18] + node _T_5228 = shl(ramMem[41], 8) @[RegMapper.scala 150:47] + node _T_5230 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_5231 = and(_T_5228, _T_5230) @[RegMapper.scala 150:55] + node _T_5232 = or(_T_5192, _T_5231) @[RegMapper.scala 150:35] + node _T_5233 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_5235 = neq(_T_5233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5236 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_5237 = not(_T_5236) @[RegMapper.scala 136:45] + node _T_5239 = eq(_T_5237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5240 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_5242 = neq(_T_5240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5243 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_5244 = not(_T_5243) @[RegMapper.scala 138:44] + node _T_5246 = eq(_T_5244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5247 = and(_T_1958[34], _T_5235) @[RegMapper.scala 140:69] + node _T_5248 = and(_T_3086[34], _T_5242) @[RegMapper.scala 140:91] + node _T_5251 = and(_T_2146[34], _T_5239) @[RegMapper.scala 141:62] + node _T_5252 = and(_T_3274[34], _T_5246) @[RegMapper.scala 141:84] + node _T_5253 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_5252 : @[RegField.scala 70:88] + ramMem[42] <= _T_5253 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5257 = eq(_T_5235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5258 = or(UInt<1>("h01"), _T_5257) @[RegMapper.scala 142:31] + _T_2334[34] <= _T_5258 @[RegMapper.scala 142:18] + node _T_5260 = eq(_T_5239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5261 = or(UInt<1>("h01"), _T_5260) @[RegMapper.scala 143:31] + _T_2522[34] <= _T_5261 @[RegMapper.scala 143:18] + node _T_5263 = eq(_T_5242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5264 = or(UInt<1>("h01"), _T_5263) @[RegMapper.scala 144:31] + _T_2710[34] <= _T_5264 @[RegMapper.scala 144:18] + node _T_5266 = eq(_T_5246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5267 = or(UInt<1>("h01"), _T_5266) @[RegMapper.scala 145:31] + _T_2898[34] <= _T_5267 @[RegMapper.scala 145:18] + node _T_5268 = shl(ramMem[42], 16) @[RegMapper.scala 150:47] + node _T_5270 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_5271 = and(_T_5268, _T_5270) @[RegMapper.scala 150:55] + node _T_5272 = or(_T_5232, _T_5271) @[RegMapper.scala 150:35] + node _T_5273 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_5275 = neq(_T_5273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5276 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_5277 = not(_T_5276) @[RegMapper.scala 136:45] + node _T_5279 = eq(_T_5277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5280 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_5282 = neq(_T_5280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5283 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_5284 = not(_T_5283) @[RegMapper.scala 138:44] + node _T_5286 = eq(_T_5284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5287 = and(_T_1958[35], _T_5275) @[RegMapper.scala 140:69] + node _T_5288 = and(_T_3086[35], _T_5282) @[RegMapper.scala 140:91] + node _T_5291 = and(_T_2146[35], _T_5279) @[RegMapper.scala 141:62] + node _T_5292 = and(_T_3274[35], _T_5286) @[RegMapper.scala 141:84] + node _T_5293 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_5292 : @[RegField.scala 70:88] + ramMem[43] <= _T_5293 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5297 = eq(_T_5275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5298 = or(UInt<1>("h01"), _T_5297) @[RegMapper.scala 142:31] + _T_2334[35] <= _T_5298 @[RegMapper.scala 142:18] + node _T_5300 = eq(_T_5279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5301 = or(UInt<1>("h01"), _T_5300) @[RegMapper.scala 143:31] + _T_2522[35] <= _T_5301 @[RegMapper.scala 143:18] + node _T_5303 = eq(_T_5282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5304 = or(UInt<1>("h01"), _T_5303) @[RegMapper.scala 144:31] + _T_2710[35] <= _T_5304 @[RegMapper.scala 144:18] + node _T_5306 = eq(_T_5286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5307 = or(UInt<1>("h01"), _T_5306) @[RegMapper.scala 145:31] + _T_2898[35] <= _T_5307 @[RegMapper.scala 145:18] + node _T_5308 = shl(ramMem[43], 24) @[RegMapper.scala 150:47] + node _T_5310 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_5311 = and(_T_5308, _T_5310) @[RegMapper.scala 150:55] + node _T_5312 = or(_T_5272, _T_5311) @[RegMapper.scala 150:35] + node _T_5313 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_5315 = neq(_T_5313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5316 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_5317 = not(_T_5316) @[RegMapper.scala 136:45] + node _T_5319 = eq(_T_5317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5320 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_5322 = neq(_T_5320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5323 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_5324 = not(_T_5323) @[RegMapper.scala 138:44] + node _T_5326 = eq(_T_5324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5327 = and(_T_1958[36], _T_5315) @[RegMapper.scala 140:69] + node _T_5328 = and(_T_3086[36], _T_5322) @[RegMapper.scala 140:91] + node _T_5331 = and(_T_2146[36], _T_5319) @[RegMapper.scala 141:62] + node _T_5332 = and(_T_3274[36], _T_5326) @[RegMapper.scala 141:84] + node _T_5333 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_5332 : @[RegField.scala 70:88] + ramMem[44] <= _T_5333 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5337 = eq(_T_5315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5338 = or(UInt<1>("h01"), _T_5337) @[RegMapper.scala 142:31] + _T_2334[36] <= _T_5338 @[RegMapper.scala 142:18] + node _T_5340 = eq(_T_5319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5341 = or(UInt<1>("h01"), _T_5340) @[RegMapper.scala 143:31] + _T_2522[36] <= _T_5341 @[RegMapper.scala 143:18] + node _T_5343 = eq(_T_5322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5344 = or(UInt<1>("h01"), _T_5343) @[RegMapper.scala 144:31] + _T_2710[36] <= _T_5344 @[RegMapper.scala 144:18] + node _T_5346 = eq(_T_5326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5347 = or(UInt<1>("h01"), _T_5346) @[RegMapper.scala 145:31] + _T_2898[36] <= _T_5347 @[RegMapper.scala 145:18] + node _T_5348 = shl(ramMem[44], 32) @[RegMapper.scala 150:47] + node _T_5350 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_5351 = and(_T_5348, _T_5350) @[RegMapper.scala 150:55] + node _T_5352 = or(_T_5312, _T_5351) @[RegMapper.scala 150:35] + node _T_5353 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_5355 = neq(_T_5353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5356 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_5357 = not(_T_5356) @[RegMapper.scala 136:45] + node _T_5359 = eq(_T_5357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5360 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_5362 = neq(_T_5360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5363 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_5364 = not(_T_5363) @[RegMapper.scala 138:44] + node _T_5366 = eq(_T_5364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5367 = and(_T_1958[37], _T_5355) @[RegMapper.scala 140:69] + node _T_5368 = and(_T_3086[37], _T_5362) @[RegMapper.scala 140:91] + node _T_5371 = and(_T_2146[37], _T_5359) @[RegMapper.scala 141:62] + node _T_5372 = and(_T_3274[37], _T_5366) @[RegMapper.scala 141:84] + node _T_5373 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_5372 : @[RegField.scala 70:88] + ramMem[45] <= _T_5373 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5377 = eq(_T_5355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5378 = or(UInt<1>("h01"), _T_5377) @[RegMapper.scala 142:31] + _T_2334[37] <= _T_5378 @[RegMapper.scala 142:18] + node _T_5380 = eq(_T_5359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5381 = or(UInt<1>("h01"), _T_5380) @[RegMapper.scala 143:31] + _T_2522[37] <= _T_5381 @[RegMapper.scala 143:18] + node _T_5383 = eq(_T_5362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5384 = or(UInt<1>("h01"), _T_5383) @[RegMapper.scala 144:31] + _T_2710[37] <= _T_5384 @[RegMapper.scala 144:18] + node _T_5386 = eq(_T_5366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5387 = or(UInt<1>("h01"), _T_5386) @[RegMapper.scala 145:31] + _T_2898[37] <= _T_5387 @[RegMapper.scala 145:18] + node _T_5388 = shl(ramMem[45], 40) @[RegMapper.scala 150:47] + node _T_5390 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_5391 = and(_T_5388, _T_5390) @[RegMapper.scala 150:55] + node _T_5392 = or(_T_5352, _T_5391) @[RegMapper.scala 150:35] + node _T_5393 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_5395 = neq(_T_5393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5396 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_5397 = not(_T_5396) @[RegMapper.scala 136:45] + node _T_5399 = eq(_T_5397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5400 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_5402 = neq(_T_5400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5403 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_5404 = not(_T_5403) @[RegMapper.scala 138:44] + node _T_5406 = eq(_T_5404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5407 = and(_T_1958[38], _T_5395) @[RegMapper.scala 140:69] + node _T_5408 = and(_T_3086[38], _T_5402) @[RegMapper.scala 140:91] + node _T_5411 = and(_T_2146[38], _T_5399) @[RegMapper.scala 141:62] + node _T_5412 = and(_T_3274[38], _T_5406) @[RegMapper.scala 141:84] + node _T_5413 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_5412 : @[RegField.scala 70:88] + ramMem[46] <= _T_5413 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5417 = eq(_T_5395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5418 = or(UInt<1>("h01"), _T_5417) @[RegMapper.scala 142:31] + _T_2334[38] <= _T_5418 @[RegMapper.scala 142:18] + node _T_5420 = eq(_T_5399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5421 = or(UInt<1>("h01"), _T_5420) @[RegMapper.scala 143:31] + _T_2522[38] <= _T_5421 @[RegMapper.scala 143:18] + node _T_5423 = eq(_T_5402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5424 = or(UInt<1>("h01"), _T_5423) @[RegMapper.scala 144:31] + _T_2710[38] <= _T_5424 @[RegMapper.scala 144:18] + node _T_5426 = eq(_T_5406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5427 = or(UInt<1>("h01"), _T_5426) @[RegMapper.scala 145:31] + _T_2898[38] <= _T_5427 @[RegMapper.scala 145:18] + node _T_5428 = shl(ramMem[46], 48) @[RegMapper.scala 150:47] + node _T_5430 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_5431 = and(_T_5428, _T_5430) @[RegMapper.scala 150:55] + node _T_5432 = or(_T_5392, _T_5431) @[RegMapper.scala 150:35] + node _T_5433 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_5435 = neq(_T_5433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5436 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_5437 = not(_T_5436) @[RegMapper.scala 136:45] + node _T_5439 = eq(_T_5437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5440 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_5442 = neq(_T_5440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5443 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_5444 = not(_T_5443) @[RegMapper.scala 138:44] + node _T_5446 = eq(_T_5444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5447 = and(_T_1958[39], _T_5435) @[RegMapper.scala 140:69] + node _T_5448 = and(_T_3086[39], _T_5442) @[RegMapper.scala 140:91] + node _T_5451 = and(_T_2146[39], _T_5439) @[RegMapper.scala 141:62] + node _T_5452 = and(_T_3274[39], _T_5446) @[RegMapper.scala 141:84] + node _T_5453 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_5452 : @[RegField.scala 70:88] + ramMem[47] <= _T_5453 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_5457 = eq(_T_5435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5458 = or(UInt<1>("h01"), _T_5457) @[RegMapper.scala 142:31] + _T_2334[39] <= _T_5458 @[RegMapper.scala 142:18] + node _T_5460 = eq(_T_5439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5461 = or(UInt<1>("h01"), _T_5460) @[RegMapper.scala 143:31] + _T_2522[39] <= _T_5461 @[RegMapper.scala 143:18] + node _T_5463 = eq(_T_5442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5464 = or(UInt<1>("h01"), _T_5463) @[RegMapper.scala 144:31] + _T_2710[39] <= _T_5464 @[RegMapper.scala 144:18] + node _T_5466 = eq(_T_5446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5467 = or(UInt<1>("h01"), _T_5466) @[RegMapper.scala 145:31] + _T_2898[39] <= _T_5467 @[RegMapper.scala 145:18] + node _T_5468 = shl(ramMem[47], 56) @[RegMapper.scala 150:47] + node _T_5470 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_5471 = and(_T_5468, _T_5470) @[RegMapper.scala 150:55] + node _T_5472 = or(_T_5432, _T_5471) @[RegMapper.scala 150:35] + node _T_5473 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_5475 = neq(_T_5473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5476 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_5477 = not(_T_5476) @[RegMapper.scala 136:45] + node _T_5479 = eq(_T_5477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5480 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_5482 = neq(_T_5480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5483 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_5484 = not(_T_5483) @[RegMapper.scala 138:44] + node _T_5486 = eq(_T_5484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5487 = and(_T_1958[40], _T_5475) @[RegMapper.scala 140:69] + node _T_5488 = and(_T_3086[40], _T_5482) @[RegMapper.scala 140:91] + node _T_5491 = and(_T_2146[40], _T_5479) @[RegMapper.scala 141:62] + node _T_5492 = and(_T_3274[40], _T_5486) @[RegMapper.scala 141:84] + node _T_5493 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_5497 = eq(_T_5475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5498 = or(UInt<1>("h01"), _T_5497) @[RegMapper.scala 142:31] + _T_2334[40] <= _T_5498 @[RegMapper.scala 142:18] + node _T_5500 = eq(_T_5479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5501 = or(UInt<1>("h01"), _T_5500) @[RegMapper.scala 143:31] + _T_2522[40] <= _T_5501 @[RegMapper.scala 143:18] + node _T_5503 = eq(_T_5482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5504 = or(UInt<1>("h01"), _T_5503) @[RegMapper.scala 144:31] + _T_2710[40] <= _T_5504 @[RegMapper.scala 144:18] + node _T_5506 = eq(_T_5486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5507 = or(UInt<1>("h01"), _T_5506) @[RegMapper.scala 145:31] + _T_2898[40] <= _T_5507 @[RegMapper.scala 145:18] + node _T_5508 = shl(UInt<5>("h013"), 0) @[RegMapper.scala 150:47] + node _T_5510 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_5511 = and(_T_5508, _T_5510) @[RegMapper.scala 150:55] + node _T_5512 = or(UInt<1>("h00"), _T_5511) @[RegMapper.scala 150:35] + node _T_5513 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_5515 = neq(_T_5513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5516 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_5517 = not(_T_5516) @[RegMapper.scala 136:45] + node _T_5519 = eq(_T_5517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5520 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_5522 = neq(_T_5520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5523 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_5524 = not(_T_5523) @[RegMapper.scala 138:44] + node _T_5526 = eq(_T_5524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5527 = and(_T_1958[41], _T_5515) @[RegMapper.scala 140:69] + node _T_5528 = and(_T_3086[41], _T_5522) @[RegMapper.scala 140:91] + node _T_5531 = and(_T_2146[41], _T_5519) @[RegMapper.scala 141:62] + node _T_5532 = and(_T_3274[41], _T_5526) @[RegMapper.scala 141:84] + node _T_5533 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_5537 = eq(_T_5515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5538 = or(UInt<1>("h01"), _T_5537) @[RegMapper.scala 142:31] + _T_2334[41] <= _T_5538 @[RegMapper.scala 142:18] + node _T_5540 = eq(_T_5519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5541 = or(UInt<1>("h01"), _T_5540) @[RegMapper.scala 143:31] + _T_2522[41] <= _T_5541 @[RegMapper.scala 143:18] + node _T_5543 = eq(_T_5522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5544 = or(UInt<1>("h01"), _T_5543) @[RegMapper.scala 144:31] + _T_2710[41] <= _T_5544 @[RegMapper.scala 144:18] + node _T_5546 = eq(_T_5526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5547 = or(UInt<1>("h01"), _T_5546) @[RegMapper.scala 145:31] + _T_2898[41] <= _T_5547 @[RegMapper.scala 145:18] + node _T_5548 = shl(UInt<3>("h04"), 8) @[RegMapper.scala 150:47] + node _T_5550 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_5551 = and(_T_5548, _T_5550) @[RegMapper.scala 150:55] + node _T_5552 = or(_T_5512, _T_5551) @[RegMapper.scala 150:35] + node _T_5553 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_5555 = neq(_T_5553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5556 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_5557 = not(_T_5556) @[RegMapper.scala 136:45] + node _T_5559 = eq(_T_5557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5560 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_5562 = neq(_T_5560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5563 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_5564 = not(_T_5563) @[RegMapper.scala 138:44] + node _T_5566 = eq(_T_5564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5567 = and(_T_1958[42], _T_5555) @[RegMapper.scala 140:69] + node _T_5568 = and(_T_3086[42], _T_5562) @[RegMapper.scala 140:91] + node _T_5571 = and(_T_2146[42], _T_5559) @[RegMapper.scala 141:62] + node _T_5572 = and(_T_3274[42], _T_5566) @[RegMapper.scala 141:84] + node _T_5573 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_5577 = eq(_T_5555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5578 = or(UInt<1>("h01"), _T_5577) @[RegMapper.scala 142:31] + _T_2334[42] <= _T_5578 @[RegMapper.scala 142:18] + node _T_5580 = eq(_T_5559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5581 = or(UInt<1>("h01"), _T_5580) @[RegMapper.scala 143:31] + _T_2522[42] <= _T_5581 @[RegMapper.scala 143:18] + node _T_5583 = eq(_T_5562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5584 = or(UInt<1>("h01"), _T_5583) @[RegMapper.scala 144:31] + _T_2710[42] <= _T_5584 @[RegMapper.scala 144:18] + node _T_5586 = eq(_T_5566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5587 = or(UInt<1>("h01"), _T_5586) @[RegMapper.scala 145:31] + _T_2898[42] <= _T_5587 @[RegMapper.scala 145:18] + node _T_5588 = shl(UInt<3>("h04"), 16) @[RegMapper.scala 150:47] + node _T_5590 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_5591 = and(_T_5588, _T_5590) @[RegMapper.scala 150:55] + node _T_5592 = or(_T_5552, _T_5591) @[RegMapper.scala 150:35] + node _T_5593 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_5595 = neq(_T_5593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5596 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_5597 = not(_T_5596) @[RegMapper.scala 136:45] + node _T_5599 = eq(_T_5597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5600 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_5602 = neq(_T_5600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5603 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_5604 = not(_T_5603) @[RegMapper.scala 138:44] + node _T_5606 = eq(_T_5604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5607 = and(_T_1958[43], _T_5595) @[RegMapper.scala 140:69] + node _T_5608 = and(_T_3086[43], _T_5602) @[RegMapper.scala 140:91] + node _T_5611 = and(_T_2146[43], _T_5599) @[RegMapper.scala 141:62] + node _T_5612 = and(_T_3274[43], _T_5606) @[RegMapper.scala 141:84] + node _T_5613 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_5617 = eq(_T_5595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5618 = or(UInt<1>("h01"), _T_5617) @[RegMapper.scala 142:31] + _T_2334[43] <= _T_5618 @[RegMapper.scala 142:18] + node _T_5620 = eq(_T_5599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5621 = or(UInt<1>("h01"), _T_5620) @[RegMapper.scala 143:31] + _T_2522[43] <= _T_5621 @[RegMapper.scala 143:18] + node _T_5623 = eq(_T_5602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5624 = or(UInt<1>("h01"), _T_5623) @[RegMapper.scala 144:31] + _T_2710[43] <= _T_5624 @[RegMapper.scala 144:18] + node _T_5626 = eq(_T_5606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5627 = or(UInt<1>("h01"), _T_5626) @[RegMapper.scala 145:31] + _T_2898[43] <= _T_5627 @[RegMapper.scala 145:18] + node _T_5628 = shl(UInt<8>("h0f4"), 24) @[RegMapper.scala 150:47] + node _T_5630 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_5631 = and(_T_5628, _T_5630) @[RegMapper.scala 150:55] + node _T_5632 = or(_T_5592, _T_5631) @[RegMapper.scala 150:35] + node _T_5633 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_5635 = neq(_T_5633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5636 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_5637 = not(_T_5636) @[RegMapper.scala 136:45] + node _T_5639 = eq(_T_5637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5640 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_5642 = neq(_T_5640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5643 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_5644 = not(_T_5643) @[RegMapper.scala 138:44] + node _T_5646 = eq(_T_5644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5647 = and(_T_1958[44], _T_5635) @[RegMapper.scala 140:69] + node _T_5648 = and(_T_3086[44], _T_5642) @[RegMapper.scala 140:91] + node _T_5651 = and(_T_2146[44], _T_5639) @[RegMapper.scala 141:62] + node _T_5652 = and(_T_3274[44], _T_5646) @[RegMapper.scala 141:84] + node _T_5653 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_5657 = eq(_T_5635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5658 = or(UInt<1>("h01"), _T_5657) @[RegMapper.scala 142:31] + _T_2334[44] <= _T_5658 @[RegMapper.scala 142:18] + node _T_5660 = eq(_T_5639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5661 = or(UInt<1>("h01"), _T_5660) @[RegMapper.scala 143:31] + _T_2522[44] <= _T_5661 @[RegMapper.scala 143:18] + node _T_5663 = eq(_T_5642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5664 = or(UInt<1>("h01"), _T_5663) @[RegMapper.scala 144:31] + _T_2710[44] <= _T_5664 @[RegMapper.scala 144:18] + node _T_5666 = eq(_T_5646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5667 = or(UInt<1>("h01"), _T_5666) @[RegMapper.scala 145:31] + _T_2898[44] <= _T_5667 @[RegMapper.scala 145:18] + node _T_5668 = shl(UInt<7>("h063"), 32) @[RegMapper.scala 150:47] + node _T_5670 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_5671 = and(_T_5668, _T_5670) @[RegMapper.scala 150:55] + node _T_5672 = or(_T_5632, _T_5671) @[RegMapper.scala 150:35] + node _T_5673 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_5675 = neq(_T_5673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5676 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_5677 = not(_T_5676) @[RegMapper.scala 136:45] + node _T_5679 = eq(_T_5677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5680 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_5682 = neq(_T_5680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5683 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_5684 = not(_T_5683) @[RegMapper.scala 138:44] + node _T_5686 = eq(_T_5684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5687 = and(_T_1958[45], _T_5675) @[RegMapper.scala 140:69] + node _T_5688 = and(_T_3086[45], _T_5682) @[RegMapper.scala 140:91] + node _T_5691 = and(_T_2146[45], _T_5679) @[RegMapper.scala 141:62] + node _T_5692 = and(_T_3274[45], _T_5686) @[RegMapper.scala 141:84] + node _T_5693 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_5697 = eq(_T_5675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5698 = or(UInt<1>("h01"), _T_5697) @[RegMapper.scala 142:31] + _T_2334[45] <= _T_5698 @[RegMapper.scala 142:18] + node _T_5700 = eq(_T_5679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5701 = or(UInt<1>("h01"), _T_5700) @[RegMapper.scala 143:31] + _T_2522[45] <= _T_5701 @[RegMapper.scala 143:18] + node _T_5703 = eq(_T_5682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5704 = or(UInt<1>("h01"), _T_5703) @[RegMapper.scala 144:31] + _T_2710[45] <= _T_5704 @[RegMapper.scala 144:18] + node _T_5706 = eq(_T_5686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5707 = or(UInt<1>("h01"), _T_5706) @[RegMapper.scala 145:31] + _T_2898[45] <= _T_5707 @[RegMapper.scala 145:18] + node _T_5708 = shl(UInt<5>("h016"), 40) @[RegMapper.scala 150:47] + node _T_5710 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_5711 = and(_T_5708, _T_5710) @[RegMapper.scala 150:55] + node _T_5712 = or(_T_5672, _T_5711) @[RegMapper.scala 150:35] + node _T_5713 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_5715 = neq(_T_5713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5716 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_5717 = not(_T_5716) @[RegMapper.scala 136:45] + node _T_5719 = eq(_T_5717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5720 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_5722 = neq(_T_5720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5723 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_5724 = not(_T_5723) @[RegMapper.scala 138:44] + node _T_5726 = eq(_T_5724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5727 = and(_T_1958[46], _T_5715) @[RegMapper.scala 140:69] + node _T_5728 = and(_T_3086[46], _T_5722) @[RegMapper.scala 140:91] + node _T_5731 = and(_T_2146[46], _T_5719) @[RegMapper.scala 141:62] + node _T_5732 = and(_T_3274[46], _T_5726) @[RegMapper.scala 141:84] + node _T_5733 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_5737 = eq(_T_5715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5738 = or(UInt<1>("h01"), _T_5737) @[RegMapper.scala 142:31] + _T_2334[46] <= _T_5738 @[RegMapper.scala 142:18] + node _T_5740 = eq(_T_5719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5741 = or(UInt<1>("h01"), _T_5740) @[RegMapper.scala 143:31] + _T_2522[46] <= _T_5741 @[RegMapper.scala 143:18] + node _T_5743 = eq(_T_5722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5744 = or(UInt<1>("h01"), _T_5743) @[RegMapper.scala 144:31] + _T_2710[46] <= _T_5744 @[RegMapper.scala 144:18] + node _T_5746 = eq(_T_5726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5747 = or(UInt<1>("h01"), _T_5746) @[RegMapper.scala 145:31] + _T_2898[46] <= _T_5747 @[RegMapper.scala 145:18] + node _T_5748 = shl(UInt<3>("h04"), 48) @[RegMapper.scala 150:47] + node _T_5750 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_5751 = and(_T_5748, _T_5750) @[RegMapper.scala 150:55] + node _T_5752 = or(_T_5712, _T_5751) @[RegMapper.scala 150:35] + node _T_5753 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_5755 = neq(_T_5753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5756 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_5757 = not(_T_5756) @[RegMapper.scala 136:45] + node _T_5759 = eq(_T_5757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5760 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_5762 = neq(_T_5760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5763 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_5764 = not(_T_5763) @[RegMapper.scala 138:44] + node _T_5766 = eq(_T_5764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5767 = and(_T_1958[47], _T_5755) @[RegMapper.scala 140:69] + node _T_5768 = and(_T_3086[47], _T_5762) @[RegMapper.scala 140:91] + node _T_5771 = and(_T_2146[47], _T_5759) @[RegMapper.scala 141:62] + node _T_5772 = and(_T_3274[47], _T_5766) @[RegMapper.scala 141:84] + node _T_5773 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_5777 = eq(_T_5755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5778 = or(UInt<1>("h01"), _T_5777) @[RegMapper.scala 142:31] + _T_2334[47] <= _T_5778 @[RegMapper.scala 142:18] + node _T_5780 = eq(_T_5759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5781 = or(UInt<1>("h01"), _T_5780) @[RegMapper.scala 143:31] + _T_2522[47] <= _T_5781 @[RegMapper.scala 143:18] + node _T_5783 = eq(_T_5762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5784 = or(UInt<1>("h01"), _T_5783) @[RegMapper.scala 144:31] + _T_2710[47] <= _T_5784 @[RegMapper.scala 144:18] + node _T_5786 = eq(_T_5766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5787 = or(UInt<1>("h01"), _T_5786) @[RegMapper.scala 145:31] + _T_2898[47] <= _T_5787 @[RegMapper.scala 145:18] + node _T_5788 = shl(UInt<1>("h00"), 56) @[RegMapper.scala 150:47] + node _T_5790 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_5791 = and(_T_5788, _T_5790) @[RegMapper.scala 150:55] + node _T_5792 = or(_T_5752, _T_5791) @[RegMapper.scala 150:35] + node _T_5793 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_5795 = neq(_T_5793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5796 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_5797 = not(_T_5796) @[RegMapper.scala 136:45] + node _T_5799 = eq(_T_5797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5800 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_5802 = neq(_T_5800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5803 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_5804 = not(_T_5803) @[RegMapper.scala 138:44] + node _T_5806 = eq(_T_5804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5807 = and(_T_1958[48], _T_5795) @[RegMapper.scala 140:69] + node _T_5808 = and(_T_3086[48], _T_5802) @[RegMapper.scala 140:91] + node _T_5811 = and(_T_2146[48], _T_5799) @[RegMapper.scala 141:62] + node _T_5812 = and(_T_3274[48], _T_5806) @[RegMapper.scala 141:84] + node _T_5813 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_5817 = eq(_T_5795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5818 = or(UInt<1>("h01"), _T_5817) @[RegMapper.scala 142:31] + _T_2334[48] <= _T_5818 @[RegMapper.scala 142:18] + node _T_5820 = eq(_T_5799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5821 = or(UInt<1>("h01"), _T_5820) @[RegMapper.scala 143:31] + _T_2522[48] <= _T_5821 @[RegMapper.scala 143:18] + node _T_5823 = eq(_T_5802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5824 = or(UInt<1>("h01"), _T_5823) @[RegMapper.scala 144:31] + _T_2710[48] <= _T_5824 @[RegMapper.scala 144:18] + node _T_5826 = eq(_T_5806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5827 = or(UInt<1>("h01"), _T_5826) @[RegMapper.scala 145:31] + _T_2898[48] <= _T_5827 @[RegMapper.scala 145:18] + node _T_5828 = shl(UInt<7>("h06f"), 0) @[RegMapper.scala 150:47] + node _T_5830 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_5831 = and(_T_5828, _T_5830) @[RegMapper.scala 150:55] + node _T_5832 = or(UInt<1>("h00"), _T_5831) @[RegMapper.scala 150:35] + node _T_5833 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_5835 = neq(_T_5833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5836 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_5837 = not(_T_5836) @[RegMapper.scala 136:45] + node _T_5839 = eq(_T_5837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5840 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_5842 = neq(_T_5840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5843 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_5844 = not(_T_5843) @[RegMapper.scala 138:44] + node _T_5846 = eq(_T_5844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5847 = and(_T_1958[49], _T_5835) @[RegMapper.scala 140:69] + node _T_5848 = and(_T_3086[49], _T_5842) @[RegMapper.scala 140:91] + node _T_5851 = and(_T_2146[49], _T_5839) @[RegMapper.scala 141:62] + node _T_5852 = and(_T_3274[49], _T_5846) @[RegMapper.scala 141:84] + node _T_5853 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_5857 = eq(_T_5835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5858 = or(UInt<1>("h01"), _T_5857) @[RegMapper.scala 142:31] + _T_2334[49] <= _T_5858 @[RegMapper.scala 142:18] + node _T_5860 = eq(_T_5839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5861 = or(UInt<1>("h01"), _T_5860) @[RegMapper.scala 143:31] + _T_2522[49] <= _T_5861 @[RegMapper.scala 143:18] + node _T_5863 = eq(_T_5842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5864 = or(UInt<1>("h01"), _T_5863) @[RegMapper.scala 144:31] + _T_2710[49] <= _T_5864 @[RegMapper.scala 144:18] + node _T_5866 = eq(_T_5846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5867 = or(UInt<1>("h01"), _T_5866) @[RegMapper.scala 145:31] + _T_2898[49] <= _T_5867 @[RegMapper.scala 145:18] + node _T_5868 = shl(UInt<8>("h0f0"), 8) @[RegMapper.scala 150:47] + node _T_5870 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_5871 = and(_T_5868, _T_5870) @[RegMapper.scala 150:55] + node _T_5872 = or(_T_5832, _T_5871) @[RegMapper.scala 150:35] + node _T_5873 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_5875 = neq(_T_5873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5876 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_5877 = not(_T_5876) @[RegMapper.scala 136:45] + node _T_5879 = eq(_T_5877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5880 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_5882 = neq(_T_5880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5883 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_5884 = not(_T_5883) @[RegMapper.scala 138:44] + node _T_5886 = eq(_T_5884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5887 = and(_T_1958[50], _T_5875) @[RegMapper.scala 140:69] + node _T_5888 = and(_T_3086[50], _T_5882) @[RegMapper.scala 140:91] + node _T_5891 = and(_T_2146[50], _T_5879) @[RegMapper.scala 141:62] + node _T_5892 = and(_T_3274[50], _T_5886) @[RegMapper.scala 141:84] + node _T_5893 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_5897 = eq(_T_5875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5898 = or(UInt<1>("h01"), _T_5897) @[RegMapper.scala 142:31] + _T_2334[50] <= _T_5898 @[RegMapper.scala 142:18] + node _T_5900 = eq(_T_5879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5901 = or(UInt<1>("h01"), _T_5900) @[RegMapper.scala 143:31] + _T_2522[50] <= _T_5901 @[RegMapper.scala 143:18] + node _T_5903 = eq(_T_5882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5904 = or(UInt<1>("h01"), _T_5903) @[RegMapper.scala 144:31] + _T_2710[50] <= _T_5904 @[RegMapper.scala 144:18] + node _T_5906 = eq(_T_5886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5907 = or(UInt<1>("h01"), _T_5906) @[RegMapper.scala 145:31] + _T_2898[50] <= _T_5907 @[RegMapper.scala 145:18] + node _T_5908 = shl(UInt<5>("h01f"), 16) @[RegMapper.scala 150:47] + node _T_5910 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_5911 = and(_T_5908, _T_5910) @[RegMapper.scala 150:55] + node _T_5912 = or(_T_5872, _T_5911) @[RegMapper.scala 150:35] + node _T_5913 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_5915 = neq(_T_5913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5916 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_5917 = not(_T_5916) @[RegMapper.scala 136:45] + node _T_5919 = eq(_T_5917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5920 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_5922 = neq(_T_5920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5923 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_5924 = not(_T_5923) @[RegMapper.scala 138:44] + node _T_5926 = eq(_T_5924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5927 = and(_T_1958[51], _T_5915) @[RegMapper.scala 140:69] + node _T_5928 = and(_T_3086[51], _T_5922) @[RegMapper.scala 140:91] + node _T_5931 = and(_T_2146[51], _T_5919) @[RegMapper.scala 141:62] + node _T_5932 = and(_T_3274[51], _T_5926) @[RegMapper.scala 141:84] + node _T_5933 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_5937 = eq(_T_5915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5938 = or(UInt<1>("h01"), _T_5937) @[RegMapper.scala 142:31] + _T_2334[51] <= _T_5938 @[RegMapper.scala 142:18] + node _T_5940 = eq(_T_5919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5941 = or(UInt<1>("h01"), _T_5940) @[RegMapper.scala 143:31] + _T_2522[51] <= _T_5941 @[RegMapper.scala 143:18] + node _T_5943 = eq(_T_5922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5944 = or(UInt<1>("h01"), _T_5943) @[RegMapper.scala 144:31] + _T_2710[51] <= _T_5944 @[RegMapper.scala 144:18] + node _T_5946 = eq(_T_5926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5947 = or(UInt<1>("h01"), _T_5946) @[RegMapper.scala 145:31] + _T_2898[51] <= _T_5947 @[RegMapper.scala 145:18] + node _T_5948 = shl(UInt<8>("h0fe"), 24) @[RegMapper.scala 150:47] + node _T_5950 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_5951 = and(_T_5948, _T_5950) @[RegMapper.scala 150:55] + node _T_5952 = or(_T_5912, _T_5951) @[RegMapper.scala 150:35] + node _T_5953 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_5955 = neq(_T_5953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5956 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_5957 = not(_T_5956) @[RegMapper.scala 136:45] + node _T_5959 = eq(_T_5957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_5960 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_5962 = neq(_T_5960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_5963 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_5964 = not(_T_5963) @[RegMapper.scala 138:44] + node _T_5966 = eq(_T_5964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_5967 = and(_T_1958[52], _T_5955) @[RegMapper.scala 140:69] + node _T_5968 = and(_T_3086[52], _T_5962) @[RegMapper.scala 140:91] + node _T_5971 = and(_T_2146[52], _T_5959) @[RegMapper.scala 141:62] + node _T_5972 = and(_T_3274[52], _T_5966) @[RegMapper.scala 141:84] + node _T_5973 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_5977 = eq(_T_5955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_5978 = or(UInt<1>("h01"), _T_5977) @[RegMapper.scala 142:31] + _T_2334[52] <= _T_5978 @[RegMapper.scala 142:18] + node _T_5980 = eq(_T_5959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_5981 = or(UInt<1>("h01"), _T_5980) @[RegMapper.scala 143:31] + _T_2522[52] <= _T_5981 @[RegMapper.scala 143:18] + node _T_5983 = eq(_T_5962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_5984 = or(UInt<1>("h01"), _T_5983) @[RegMapper.scala 144:31] + _T_2710[52] <= _T_5984 @[RegMapper.scala 144:18] + node _T_5986 = eq(_T_5966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_5987 = or(UInt<1>("h01"), _T_5986) @[RegMapper.scala 145:31] + _T_2898[52] <= _T_5987 @[RegMapper.scala 145:18] + node _T_5988 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_5990 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_5991 = and(_T_5988, _T_5990) @[RegMapper.scala 150:55] + node _T_5992 = or(UInt<1>("h00"), _T_5991) @[RegMapper.scala 150:35] + node _T_5993 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_5995 = neq(_T_5993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_5996 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_5997 = not(_T_5996) @[RegMapper.scala 136:45] + node _T_5999 = eq(_T_5997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6000 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_6002 = neq(_T_6000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6003 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_6004 = not(_T_6003) @[RegMapper.scala 138:44] + node _T_6006 = eq(_T_6004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6007 = and(_T_1958[53], _T_5995) @[RegMapper.scala 140:69] + node _T_6008 = and(_T_3086[53], _T_6002) @[RegMapper.scala 140:91] + node _T_6011 = and(_T_2146[53], _T_5999) @[RegMapper.scala 141:62] + node _T_6012 = and(_T_3274[53], _T_6006) @[RegMapper.scala 141:84] + node _T_6013 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_6017 = eq(_T_5995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6018 = or(UInt<1>("h01"), _T_6017) @[RegMapper.scala 142:31] + _T_2334[53] <= _T_6018 @[RegMapper.scala 142:18] + node _T_6020 = eq(_T_5999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6021 = or(UInt<1>("h01"), _T_6020) @[RegMapper.scala 143:31] + _T_2522[53] <= _T_6021 @[RegMapper.scala 143:18] + node _T_6023 = eq(_T_6002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6024 = or(UInt<1>("h01"), _T_6023) @[RegMapper.scala 144:31] + _T_2710[53] <= _T_6024 @[RegMapper.scala 144:18] + node _T_6026 = eq(_T_6006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6027 = or(UInt<1>("h01"), _T_6026) @[RegMapper.scala 145:31] + _T_2898[53] <= _T_6027 @[RegMapper.scala 145:18] + node _T_6028 = shl(UInt<6>("h024"), 8) @[RegMapper.scala 150:47] + node _T_6030 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_6031 = and(_T_6028, _T_6030) @[RegMapper.scala 150:55] + node _T_6032 = or(_T_5992, _T_6031) @[RegMapper.scala 150:35] + node _T_6033 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_6035 = neq(_T_6033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6036 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_6037 = not(_T_6036) @[RegMapper.scala 136:45] + node _T_6039 = eq(_T_6037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6040 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_6042 = neq(_T_6040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6043 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_6044 = not(_T_6043) @[RegMapper.scala 138:44] + node _T_6046 = eq(_T_6044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6047 = and(_T_1958[54], _T_6035) @[RegMapper.scala 140:69] + node _T_6048 = and(_T_3086[54], _T_6042) @[RegMapper.scala 140:91] + node _T_6051 = and(_T_2146[54], _T_6039) @[RegMapper.scala 141:62] + node _T_6052 = and(_T_3274[54], _T_6046) @[RegMapper.scala 141:84] + node _T_6053 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_6057 = eq(_T_6035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6058 = or(UInt<1>("h01"), _T_6057) @[RegMapper.scala 142:31] + _T_2334[54] <= _T_6058 @[RegMapper.scala 142:18] + node _T_6060 = eq(_T_6039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6061 = or(UInt<1>("h01"), _T_6060) @[RegMapper.scala 143:31] + _T_2522[54] <= _T_6061 @[RegMapper.scala 143:18] + node _T_6063 = eq(_T_6042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6064 = or(UInt<1>("h01"), _T_6063) @[RegMapper.scala 144:31] + _T_2710[54] <= _T_6064 @[RegMapper.scala 144:18] + node _T_6066 = eq(_T_6046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6067 = or(UInt<1>("h01"), _T_6066) @[RegMapper.scala 145:31] + _T_2898[54] <= _T_6067 @[RegMapper.scala 145:18] + node _T_6068 = shl(UInt<7>("h040"), 16) @[RegMapper.scala 150:47] + node _T_6070 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_6071 = and(_T_6068, _T_6070) @[RegMapper.scala 150:55] + node _T_6072 = or(_T_6032, _T_6071) @[RegMapper.scala 150:35] + node _T_6073 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_6075 = neq(_T_6073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6076 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_6077 = not(_T_6076) @[RegMapper.scala 136:45] + node _T_6079 = eq(_T_6077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6080 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_6082 = neq(_T_6080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6083 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_6084 = not(_T_6083) @[RegMapper.scala 138:44] + node _T_6086 = eq(_T_6084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6087 = and(_T_1958[55], _T_6075) @[RegMapper.scala 140:69] + node _T_6088 = and(_T_3086[55], _T_6082) @[RegMapper.scala 140:91] + node _T_6091 = and(_T_2146[55], _T_6079) @[RegMapper.scala 141:62] + node _T_6092 = and(_T_3274[55], _T_6086) @[RegMapper.scala 141:84] + node _T_6093 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_6097 = eq(_T_6075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6098 = or(UInt<1>("h01"), _T_6097) @[RegMapper.scala 142:31] + _T_2334[55] <= _T_6098 @[RegMapper.scala 142:18] + node _T_6100 = eq(_T_6079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6101 = or(UInt<1>("h01"), _T_6100) @[RegMapper.scala 143:31] + _T_2522[55] <= _T_6101 @[RegMapper.scala 143:18] + node _T_6103 = eq(_T_6082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6104 = or(UInt<1>("h01"), _T_6103) @[RegMapper.scala 144:31] + _T_2710[55] <= _T_6104 @[RegMapper.scala 144:18] + node _T_6106 = eq(_T_6086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6107 = or(UInt<1>("h01"), _T_6106) @[RegMapper.scala 145:31] + _T_2898[55] <= _T_6107 @[RegMapper.scala 145:18] + node _T_6108 = shl(UInt<8>("h0f1"), 24) @[RegMapper.scala 150:47] + node _T_6110 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_6111 = and(_T_6108, _T_6110) @[RegMapper.scala 150:55] + node _T_6112 = or(_T_6072, _T_6111) @[RegMapper.scala 150:35] + node _T_6113 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_6115 = neq(_T_6113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6116 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_6117 = not(_T_6116) @[RegMapper.scala 136:45] + node _T_6119 = eq(_T_6117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6120 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_6122 = neq(_T_6120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6123 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_6124 = not(_T_6123) @[RegMapper.scala 138:44] + node _T_6126 = eq(_T_6124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6127 = and(_T_1958[56], _T_6115) @[RegMapper.scala 140:69] + node _T_6128 = and(_T_3086[56], _T_6122) @[RegMapper.scala 140:91] + node _T_6131 = and(_T_2146[56], _T_6119) @[RegMapper.scala 141:62] + node _T_6132 = and(_T_3274[56], _T_6126) @[RegMapper.scala 141:84] + node _T_6133 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_6137 = eq(_T_6115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6138 = or(UInt<1>("h01"), _T_6137) @[RegMapper.scala 142:31] + _T_2334[56] <= _T_6138 @[RegMapper.scala 142:18] + node _T_6140 = eq(_T_6119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6141 = or(UInt<1>("h01"), _T_6140) @[RegMapper.scala 143:31] + _T_2522[56] <= _T_6141 @[RegMapper.scala 143:18] + node _T_6143 = eq(_T_6122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6144 = or(UInt<1>("h01"), _T_6143) @[RegMapper.scala 144:31] + _T_2710[56] <= _T_6144 @[RegMapper.scala 144:18] + node _T_6146 = eq(_T_6126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6147 = or(UInt<1>("h01"), _T_6146) @[RegMapper.scala 145:31] + _T_2898[56] <= _T_6147 @[RegMapper.scala 145:18] + node _T_6148 = shl(UInt<6>("h023"), 32) @[RegMapper.scala 150:47] + node _T_6150 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_6151 = and(_T_6148, _T_6150) @[RegMapper.scala 150:55] + node _T_6152 = or(_T_6112, _T_6151) @[RegMapper.scala 150:35] + node _T_6153 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_6155 = neq(_T_6153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6156 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_6157 = not(_T_6156) @[RegMapper.scala 136:45] + node _T_6159 = eq(_T_6157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6160 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_6162 = neq(_T_6160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6163 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_6164 = not(_T_6163) @[RegMapper.scala 138:44] + node _T_6166 = eq(_T_6164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6167 = and(_T_1958[57], _T_6155) @[RegMapper.scala 140:69] + node _T_6168 = and(_T_3086[57], _T_6162) @[RegMapper.scala 140:91] + node _T_6171 = and(_T_2146[57], _T_6159) @[RegMapper.scala 141:62] + node _T_6172 = and(_T_3274[57], _T_6166) @[RegMapper.scala 141:84] + node _T_6173 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_6177 = eq(_T_6155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6178 = or(UInt<1>("h01"), _T_6177) @[RegMapper.scala 142:31] + _T_2334[57] <= _T_6178 @[RegMapper.scala 142:18] + node _T_6180 = eq(_T_6159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6181 = or(UInt<1>("h01"), _T_6180) @[RegMapper.scala 143:31] + _T_2522[57] <= _T_6181 @[RegMapper.scala 143:18] + node _T_6183 = eq(_T_6162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6184 = or(UInt<1>("h01"), _T_6183) @[RegMapper.scala 144:31] + _T_2710[57] <= _T_6184 @[RegMapper.scala 144:18] + node _T_6186 = eq(_T_6166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6187 = or(UInt<1>("h01"), _T_6186) @[RegMapper.scala 145:31] + _T_2898[57] <= _T_6187 @[RegMapper.scala 145:18] + node _T_6188 = shl(UInt<6>("h020"), 40) @[RegMapper.scala 150:47] + node _T_6190 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_6191 = and(_T_6188, _T_6190) @[RegMapper.scala 150:55] + node _T_6192 = or(_T_6152, _T_6191) @[RegMapper.scala 150:35] + node _T_6193 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_6195 = neq(_T_6193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6196 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_6197 = not(_T_6196) @[RegMapper.scala 136:45] + node _T_6199 = eq(_T_6197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6200 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_6202 = neq(_T_6200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6203 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_6204 = not(_T_6203) @[RegMapper.scala 138:44] + node _T_6206 = eq(_T_6204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6207 = and(_T_1958[58], _T_6195) @[RegMapper.scala 140:69] + node _T_6208 = and(_T_3086[58], _T_6202) @[RegMapper.scala 140:91] + node _T_6211 = and(_T_2146[58], _T_6199) @[RegMapper.scala 141:62] + node _T_6212 = and(_T_3274[58], _T_6206) @[RegMapper.scala 141:84] + node _T_6213 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_6217 = eq(_T_6195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6218 = or(UInt<1>("h01"), _T_6217) @[RegMapper.scala 142:31] + _T_2334[58] <= _T_6218 @[RegMapper.scala 142:18] + node _T_6220 = eq(_T_6199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6221 = or(UInt<1>("h01"), _T_6220) @[RegMapper.scala 143:31] + _T_2522[58] <= _T_6221 @[RegMapper.scala 143:18] + node _T_6223 = eq(_T_6202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6224 = or(UInt<1>("h01"), _T_6223) @[RegMapper.scala 144:31] + _T_2710[58] <= _T_6224 @[RegMapper.scala 144:18] + node _T_6226 = eq(_T_6206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6227 = or(UInt<1>("h01"), _T_6226) @[RegMapper.scala 145:31] + _T_2898[58] <= _T_6227 @[RegMapper.scala 145:18] + node _T_6228 = shl(UInt<8>("h080"), 48) @[RegMapper.scala 150:47] + node _T_6230 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_6231 = and(_T_6228, _T_6230) @[RegMapper.scala 150:55] + node _T_6232 = or(_T_6192, _T_6231) @[RegMapper.scala 150:35] + node _T_6233 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_6235 = neq(_T_6233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6236 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_6237 = not(_T_6236) @[RegMapper.scala 136:45] + node _T_6239 = eq(_T_6237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6240 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_6242 = neq(_T_6240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6243 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_6244 = not(_T_6243) @[RegMapper.scala 138:44] + node _T_6246 = eq(_T_6244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6247 = and(_T_1958[59], _T_6235) @[RegMapper.scala 140:69] + node _T_6248 = and(_T_3086[59], _T_6242) @[RegMapper.scala 140:91] + node _T_6251 = and(_T_2146[59], _T_6239) @[RegMapper.scala 141:62] + node _T_6252 = and(_T_3274[59], _T_6246) @[RegMapper.scala 141:84] + node _T_6253 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_6257 = eq(_T_6235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6258 = or(UInt<1>("h01"), _T_6257) @[RegMapper.scala 142:31] + _T_2334[59] <= _T_6258 @[RegMapper.scala 142:18] + node _T_6260 = eq(_T_6239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6261 = or(UInt<1>("h01"), _T_6260) @[RegMapper.scala 143:31] + _T_2522[59] <= _T_6261 @[RegMapper.scala 143:18] + node _T_6263 = eq(_T_6242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6264 = or(UInt<1>("h01"), _T_6263) @[RegMapper.scala 144:31] + _T_2710[59] <= _T_6264 @[RegMapper.scala 144:18] + node _T_6266 = eq(_T_6246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6267 = or(UInt<1>("h01"), _T_6266) @[RegMapper.scala 145:31] + _T_2898[59] <= _T_6267 @[RegMapper.scala 145:18] + node _T_6268 = shl(UInt<5>("h010"), 56) @[RegMapper.scala 150:47] + node _T_6270 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_6271 = and(_T_6268, _T_6270) @[RegMapper.scala 150:55] + node _T_6272 = or(_T_6232, _T_6271) @[RegMapper.scala 150:35] + node _T_6273 = bits(_T_3825, 41, 32) @[RegMapper.scala 135:29] + node _T_6275 = neq(_T_6273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6276 = bits(_T_3825, 41, 32) @[RegMapper.scala 136:29] + node _T_6277 = not(_T_6276) @[RegMapper.scala 136:45] + node _T_6279 = eq(_T_6277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6280 = bits(_T_3872, 41, 32) @[RegMapper.scala 137:28] + node _T_6282 = neq(_T_6280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6283 = bits(_T_3872, 41, 32) @[RegMapper.scala 138:28] + node _T_6284 = not(_T_6283) @[RegMapper.scala 138:44] + node _T_6286 = eq(_T_6284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6287 = and(_T_1958[60], _T_6275) @[RegMapper.scala 140:69] + node _T_6288 = and(_T_3086[60], _T_6282) @[RegMapper.scala 140:91] + node _T_6291 = and(_T_2146[60], _T_6279) @[RegMapper.scala 141:62] + node _T_6292 = and(_T_3274[60], _T_6286) @[RegMapper.scala 141:84] + node _T_6293 = bits(_T_1583.bits.data, 41, 32) @[RegMapper.scala 141:99] + SETHALTNOTWrEn <= _T_6292 @[Debug.scala 828:57] + SETHALTNOTWrData <= _T_6293 @[Debug.scala 828:74] + node _T_6297 = eq(_T_6275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6298 = or(UInt<1>("h01"), _T_6297) @[RegMapper.scala 142:31] + _T_2334[60] <= _T_6298 @[RegMapper.scala 142:18] + node _T_6300 = eq(_T_6279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6301 = or(UInt<1>("h01"), _T_6300) @[RegMapper.scala 143:31] + _T_2522[60] <= _T_6301 @[RegMapper.scala 143:18] + node _T_6303 = eq(_T_6282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6304 = or(UInt<1>("h01"), _T_6303) @[RegMapper.scala 144:31] + _T_2710[60] <= _T_6304 @[RegMapper.scala 144:18] + node _T_6306 = eq(_T_6286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6307 = or(UInt<1>("h01"), _T_6306) @[RegMapper.scala 145:31] + _T_2898[60] <= _T_6307 @[RegMapper.scala 145:18] + node _T_6308 = shl(SETHALTNOTWrData, 32) @[RegMapper.scala 150:47] + node _T_6310 = not(UInt<42>("h00")) @[RegMapper.scala 150:58] + node _T_6311 = and(_T_6308, _T_6310) @[RegMapper.scala 150:55] + node _T_6312 = or(UInt<1>("h00"), _T_6311) @[RegMapper.scala 150:35] + node _T_6313 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_6315 = neq(_T_6313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6316 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_6317 = not(_T_6316) @[RegMapper.scala 136:45] + node _T_6319 = eq(_T_6317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6320 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_6322 = neq(_T_6320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6323 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_6324 = not(_T_6323) @[RegMapper.scala 138:44] + node _T_6326 = eq(_T_6324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6327 = and(_T_1958[61], _T_6315) @[RegMapper.scala 140:69] + node _T_6328 = and(_T_3086[61], _T_6322) @[RegMapper.scala 140:91] + node _T_6331 = and(_T_2146[61], _T_6319) @[RegMapper.scala 141:62] + node _T_6332 = and(_T_3274[61], _T_6326) @[RegMapper.scala 141:84] + node _T_6333 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_6337 = eq(_T_6315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6338 = or(UInt<1>("h01"), _T_6337) @[RegMapper.scala 142:31] + _T_2334[61] <= _T_6338 @[RegMapper.scala 142:18] + node _T_6340 = eq(_T_6319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6341 = or(UInt<1>("h01"), _T_6340) @[RegMapper.scala 143:31] + _T_2522[61] <= _T_6341 @[RegMapper.scala 143:18] + node _T_6343 = eq(_T_6322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6344 = or(UInt<1>("h01"), _T_6343) @[RegMapper.scala 144:31] + _T_2710[61] <= _T_6344 @[RegMapper.scala 144:18] + node _T_6346 = eq(_T_6326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6347 = or(UInt<1>("h01"), _T_6346) @[RegMapper.scala 145:31] + _T_2898[61] <= _T_6347 @[RegMapper.scala 145:18] + node _T_6348 = shl(UInt<7>("h06f"), 0) @[RegMapper.scala 150:47] + node _T_6350 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_6351 = and(_T_6348, _T_6350) @[RegMapper.scala 150:55] + node _T_6352 = or(UInt<1>("h00"), _T_6351) @[RegMapper.scala 150:35] + node _T_6353 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_6355 = neq(_T_6353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6356 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_6357 = not(_T_6356) @[RegMapper.scala 136:45] + node _T_6359 = eq(_T_6357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6360 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_6362 = neq(_T_6360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6363 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_6364 = not(_T_6363) @[RegMapper.scala 138:44] + node _T_6366 = eq(_T_6364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6367 = and(_T_1958[62], _T_6355) @[RegMapper.scala 140:69] + node _T_6368 = and(_T_3086[62], _T_6362) @[RegMapper.scala 140:91] + node _T_6371 = and(_T_2146[62], _T_6359) @[RegMapper.scala 141:62] + node _T_6372 = and(_T_3274[62], _T_6366) @[RegMapper.scala 141:84] + node _T_6373 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_6377 = eq(_T_6355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6378 = or(UInt<1>("h01"), _T_6377) @[RegMapper.scala 142:31] + _T_2334[62] <= _T_6378 @[RegMapper.scala 142:18] + node _T_6380 = eq(_T_6359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6381 = or(UInt<1>("h01"), _T_6380) @[RegMapper.scala 143:31] + _T_2522[62] <= _T_6381 @[RegMapper.scala 143:18] + node _T_6383 = eq(_T_6362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6384 = or(UInt<1>("h01"), _T_6383) @[RegMapper.scala 144:31] + _T_2710[62] <= _T_6384 @[RegMapper.scala 144:18] + node _T_6386 = eq(_T_6366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6387 = or(UInt<1>("h01"), _T_6386) @[RegMapper.scala 145:31] + _T_2898[62] <= _T_6387 @[RegMapper.scala 145:18] + node _T_6388 = shl(UInt<1>("h00"), 8) @[RegMapper.scala 150:47] + node _T_6390 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_6391 = and(_T_6388, _T_6390) @[RegMapper.scala 150:55] + node _T_6392 = or(_T_6352, _T_6391) @[RegMapper.scala 150:35] + node _T_6393 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_6395 = neq(_T_6393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6396 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_6397 = not(_T_6396) @[RegMapper.scala 136:45] + node _T_6399 = eq(_T_6397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6400 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_6402 = neq(_T_6400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6403 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_6404 = not(_T_6403) @[RegMapper.scala 138:44] + node _T_6406 = eq(_T_6404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6407 = and(_T_1958[63], _T_6395) @[RegMapper.scala 140:69] + node _T_6408 = and(_T_3086[63], _T_6402) @[RegMapper.scala 140:91] + node _T_6411 = and(_T_2146[63], _T_6399) @[RegMapper.scala 141:62] + node _T_6412 = and(_T_3274[63], _T_6406) @[RegMapper.scala 141:84] + node _T_6413 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_6417 = eq(_T_6395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6418 = or(UInt<1>("h01"), _T_6417) @[RegMapper.scala 142:31] + _T_2334[63] <= _T_6418 @[RegMapper.scala 142:18] + node _T_6420 = eq(_T_6399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6421 = or(UInt<1>("h01"), _T_6420) @[RegMapper.scala 143:31] + _T_2522[63] <= _T_6421 @[RegMapper.scala 143:18] + node _T_6423 = eq(_T_6402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6424 = or(UInt<1>("h01"), _T_6423) @[RegMapper.scala 144:31] + _T_2710[63] <= _T_6424 @[RegMapper.scala 144:18] + node _T_6426 = eq(_T_6406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6427 = or(UInt<1>("h01"), _T_6426) @[RegMapper.scala 145:31] + _T_2898[63] <= _T_6427 @[RegMapper.scala 145:18] + node _T_6428 = shl(UInt<8>("h0c0"), 16) @[RegMapper.scala 150:47] + node _T_6430 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_6431 = and(_T_6428, _T_6430) @[RegMapper.scala 150:55] + node _T_6432 = or(_T_6392, _T_6431) @[RegMapper.scala 150:35] + node _T_6433 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_6435 = neq(_T_6433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6436 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_6437 = not(_T_6436) @[RegMapper.scala 136:45] + node _T_6439 = eq(_T_6437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6440 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_6442 = neq(_T_6440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6443 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_6444 = not(_T_6443) @[RegMapper.scala 138:44] + node _T_6446 = eq(_T_6444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6447 = and(_T_1958[64], _T_6435) @[RegMapper.scala 140:69] + node _T_6448 = and(_T_3086[64], _T_6442) @[RegMapper.scala 140:91] + node _T_6451 = and(_T_2146[64], _T_6439) @[RegMapper.scala 141:62] + node _T_6452 = and(_T_3274[64], _T_6446) @[RegMapper.scala 141:84] + node _T_6453 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_6457 = eq(_T_6435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6458 = or(UInt<1>("h01"), _T_6457) @[RegMapper.scala 142:31] + _T_2334[64] <= _T_6458 @[RegMapper.scala 142:18] + node _T_6460 = eq(_T_6439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6461 = or(UInt<1>("h01"), _T_6460) @[RegMapper.scala 143:31] + _T_2522[64] <= _T_6461 @[RegMapper.scala 143:18] + node _T_6463 = eq(_T_6442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6464 = or(UInt<1>("h01"), _T_6463) @[RegMapper.scala 144:31] + _T_2710[64] <= _T_6464 @[RegMapper.scala 144:18] + node _T_6466 = eq(_T_6446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6467 = or(UInt<1>("h01"), _T_6466) @[RegMapper.scala 145:31] + _T_2898[64] <= _T_6467 @[RegMapper.scala 145:18] + node _T_6468 = shl(UInt<2>("h03"), 24) @[RegMapper.scala 150:47] + node _T_6470 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_6471 = and(_T_6468, _T_6470) @[RegMapper.scala 150:55] + node _T_6472 = or(_T_6432, _T_6471) @[RegMapper.scala 150:35] + node _T_6473 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_6475 = neq(_T_6473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6476 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_6477 = not(_T_6476) @[RegMapper.scala 136:45] + node _T_6479 = eq(_T_6477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6480 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_6482 = neq(_T_6480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6483 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_6484 = not(_T_6483) @[RegMapper.scala 138:44] + node _T_6486 = eq(_T_6484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6487 = and(_T_1958[65], _T_6475) @[RegMapper.scala 140:69] + node _T_6488 = and(_T_3086[65], _T_6482) @[RegMapper.scala 140:91] + node _T_6491 = and(_T_2146[65], _T_6479) @[RegMapper.scala 141:62] + node _T_6492 = and(_T_3274[65], _T_6486) @[RegMapper.scala 141:84] + node _T_6493 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_6497 = eq(_T_6475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6498 = or(UInt<1>("h01"), _T_6497) @[RegMapper.scala 142:31] + _T_2334[65] <= _T_6498 @[RegMapper.scala 142:18] + node _T_6500 = eq(_T_6479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6501 = or(UInt<1>("h01"), _T_6500) @[RegMapper.scala 143:31] + _T_2522[65] <= _T_6501 @[RegMapper.scala 143:18] + node _T_6503 = eq(_T_6482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6504 = or(UInt<1>("h01"), _T_6503) @[RegMapper.scala 144:31] + _T_2710[65] <= _T_6504 @[RegMapper.scala 144:18] + node _T_6506 = eq(_T_6486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6507 = or(UInt<1>("h01"), _T_6506) @[RegMapper.scala 145:31] + _T_2898[65] <= _T_6507 @[RegMapper.scala 145:18] + node _T_6508 = shl(UInt<7>("h06f"), 32) @[RegMapper.scala 150:47] + node _T_6510 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_6511 = and(_T_6508, _T_6510) @[RegMapper.scala 150:55] + node _T_6512 = or(_T_6472, _T_6511) @[RegMapper.scala 150:35] + node _T_6513 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_6515 = neq(_T_6513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6516 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_6517 = not(_T_6516) @[RegMapper.scala 136:45] + node _T_6519 = eq(_T_6517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6520 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_6522 = neq(_T_6520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6523 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_6524 = not(_T_6523) @[RegMapper.scala 138:44] + node _T_6526 = eq(_T_6524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6527 = and(_T_1958[66], _T_6515) @[RegMapper.scala 140:69] + node _T_6528 = and(_T_3086[66], _T_6522) @[RegMapper.scala 140:91] + node _T_6531 = and(_T_2146[66], _T_6519) @[RegMapper.scala 141:62] + node _T_6532 = and(_T_3274[66], _T_6526) @[RegMapper.scala 141:84] + node _T_6533 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_6537 = eq(_T_6515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6538 = or(UInt<1>("h01"), _T_6537) @[RegMapper.scala 142:31] + _T_2334[66] <= _T_6538 @[RegMapper.scala 142:18] + node _T_6540 = eq(_T_6519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6541 = or(UInt<1>("h01"), _T_6540) @[RegMapper.scala 143:31] + _T_2522[66] <= _T_6541 @[RegMapper.scala 143:18] + node _T_6543 = eq(_T_6522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6544 = or(UInt<1>("h01"), _T_6543) @[RegMapper.scala 144:31] + _T_2710[66] <= _T_6544 @[RegMapper.scala 144:18] + node _T_6546 = eq(_T_6526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6547 = or(UInt<1>("h01"), _T_6546) @[RegMapper.scala 145:31] + _T_2898[66] <= _T_6547 @[RegMapper.scala 145:18] + node _T_6548 = shl(UInt<1>("h00"), 40) @[RegMapper.scala 150:47] + node _T_6550 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_6551 = and(_T_6548, _T_6550) @[RegMapper.scala 150:55] + node _T_6552 = or(_T_6512, _T_6551) @[RegMapper.scala 150:35] + node _T_6553 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_6555 = neq(_T_6553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6556 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_6557 = not(_T_6556) @[RegMapper.scala 136:45] + node _T_6559 = eq(_T_6557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6560 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_6562 = neq(_T_6560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6563 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_6564 = not(_T_6563) @[RegMapper.scala 138:44] + node _T_6566 = eq(_T_6564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6567 = and(_T_1958[67], _T_6555) @[RegMapper.scala 140:69] + node _T_6568 = and(_T_3086[67], _T_6562) @[RegMapper.scala 140:91] + node _T_6571 = and(_T_2146[67], _T_6559) @[RegMapper.scala 141:62] + node _T_6572 = and(_T_3274[67], _T_6566) @[RegMapper.scala 141:84] + node _T_6573 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_6577 = eq(_T_6555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6578 = or(UInt<1>("h01"), _T_6577) @[RegMapper.scala 142:31] + _T_2334[67] <= _T_6578 @[RegMapper.scala 142:18] + node _T_6580 = eq(_T_6559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6581 = or(UInt<1>("h01"), _T_6580) @[RegMapper.scala 143:31] + _T_2522[67] <= _T_6581 @[RegMapper.scala 143:18] + node _T_6583 = eq(_T_6562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6584 = or(UInt<1>("h01"), _T_6583) @[RegMapper.scala 144:31] + _T_2710[67] <= _T_6584 @[RegMapper.scala 144:18] + node _T_6586 = eq(_T_6566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6587 = or(UInt<1>("h01"), _T_6586) @[RegMapper.scala 145:31] + _T_2898[67] <= _T_6587 @[RegMapper.scala 145:18] + node _T_6588 = shl(UInt<8>("h0c0"), 48) @[RegMapper.scala 150:47] + node _T_6590 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_6591 = and(_T_6588, _T_6590) @[RegMapper.scala 150:55] + node _T_6592 = or(_T_6552, _T_6591) @[RegMapper.scala 150:35] + node _T_6593 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_6595 = neq(_T_6593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6596 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_6597 = not(_T_6596) @[RegMapper.scala 136:45] + node _T_6599 = eq(_T_6597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6600 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_6602 = neq(_T_6600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6603 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_6604 = not(_T_6603) @[RegMapper.scala 138:44] + node _T_6606 = eq(_T_6604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6607 = and(_T_1958[68], _T_6595) @[RegMapper.scala 140:69] + node _T_6608 = and(_T_3086[68], _T_6602) @[RegMapper.scala 140:91] + node _T_6611 = and(_T_2146[68], _T_6599) @[RegMapper.scala 141:62] + node _T_6612 = and(_T_3274[68], _T_6606) @[RegMapper.scala 141:84] + node _T_6613 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_6617 = eq(_T_6595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6618 = or(UInt<1>("h01"), _T_6617) @[RegMapper.scala 142:31] + _T_2334[68] <= _T_6618 @[RegMapper.scala 142:18] + node _T_6620 = eq(_T_6599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6621 = or(UInt<1>("h01"), _T_6620) @[RegMapper.scala 143:31] + _T_2522[68] <= _T_6621 @[RegMapper.scala 143:18] + node _T_6623 = eq(_T_6602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6624 = or(UInt<1>("h01"), _T_6623) @[RegMapper.scala 144:31] + _T_2710[68] <= _T_6624 @[RegMapper.scala 144:18] + node _T_6626 = eq(_T_6606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6627 = or(UInt<1>("h01"), _T_6626) @[RegMapper.scala 145:31] + _T_2898[68] <= _T_6627 @[RegMapper.scala 145:18] + node _T_6628 = shl(UInt<1>("h00"), 56) @[RegMapper.scala 150:47] + node _T_6630 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_6631 = and(_T_6628, _T_6630) @[RegMapper.scala 150:55] + node _T_6632 = or(_T_6592, _T_6631) @[RegMapper.scala 150:35] + node _T_6633 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_6635 = neq(_T_6633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6636 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_6637 = not(_T_6636) @[RegMapper.scala 136:45] + node _T_6639 = eq(_T_6637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6640 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_6642 = neq(_T_6640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6643 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_6644 = not(_T_6643) @[RegMapper.scala 138:44] + node _T_6646 = eq(_T_6644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6647 = and(_T_1958[69], _T_6635) @[RegMapper.scala 140:69] + node _T_6648 = and(_T_3086[69], _T_6642) @[RegMapper.scala 140:91] + node _T_6651 = and(_T_2146[69], _T_6639) @[RegMapper.scala 141:62] + node _T_6652 = and(_T_3274[69], _T_6646) @[RegMapper.scala 141:84] + node _T_6653 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_6652 : @[RegField.scala 70:88] + ramMem[8] <= _T_6653 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6657 = eq(_T_6635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6658 = or(UInt<1>("h01"), _T_6657) @[RegMapper.scala 142:31] + _T_2334[69] <= _T_6658 @[RegMapper.scala 142:18] + node _T_6660 = eq(_T_6639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6661 = or(UInt<1>("h01"), _T_6660) @[RegMapper.scala 143:31] + _T_2522[69] <= _T_6661 @[RegMapper.scala 143:18] + node _T_6663 = eq(_T_6642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6664 = or(UInt<1>("h01"), _T_6663) @[RegMapper.scala 144:31] + _T_2710[69] <= _T_6664 @[RegMapper.scala 144:18] + node _T_6666 = eq(_T_6646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6667 = or(UInt<1>("h01"), _T_6666) @[RegMapper.scala 145:31] + _T_2898[69] <= _T_6667 @[RegMapper.scala 145:18] + node _T_6668 = shl(ramMem[8], 0) @[RegMapper.scala 150:47] + node _T_6670 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_6671 = and(_T_6668, _T_6670) @[RegMapper.scala 150:55] + node _T_6672 = or(UInt<1>("h00"), _T_6671) @[RegMapper.scala 150:35] + node _T_6673 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_6675 = neq(_T_6673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6676 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_6677 = not(_T_6676) @[RegMapper.scala 136:45] + node _T_6679 = eq(_T_6677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6680 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_6682 = neq(_T_6680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6683 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_6684 = not(_T_6683) @[RegMapper.scala 138:44] + node _T_6686 = eq(_T_6684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6687 = and(_T_1958[70], _T_6675) @[RegMapper.scala 140:69] + node _T_6688 = and(_T_3086[70], _T_6682) @[RegMapper.scala 140:91] + node _T_6691 = and(_T_2146[70], _T_6679) @[RegMapper.scala 141:62] + node _T_6692 = and(_T_3274[70], _T_6686) @[RegMapper.scala 141:84] + node _T_6693 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_6692 : @[RegField.scala 70:88] + ramMem[9] <= _T_6693 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6697 = eq(_T_6675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6698 = or(UInt<1>("h01"), _T_6697) @[RegMapper.scala 142:31] + _T_2334[70] <= _T_6698 @[RegMapper.scala 142:18] + node _T_6700 = eq(_T_6679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6701 = or(UInt<1>("h01"), _T_6700) @[RegMapper.scala 143:31] + _T_2522[70] <= _T_6701 @[RegMapper.scala 143:18] + node _T_6703 = eq(_T_6682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6704 = or(UInt<1>("h01"), _T_6703) @[RegMapper.scala 144:31] + _T_2710[70] <= _T_6704 @[RegMapper.scala 144:18] + node _T_6706 = eq(_T_6686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6707 = or(UInt<1>("h01"), _T_6706) @[RegMapper.scala 145:31] + _T_2898[70] <= _T_6707 @[RegMapper.scala 145:18] + node _T_6708 = shl(ramMem[9], 8) @[RegMapper.scala 150:47] + node _T_6710 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_6711 = and(_T_6708, _T_6710) @[RegMapper.scala 150:55] + node _T_6712 = or(_T_6672, _T_6711) @[RegMapper.scala 150:35] + node _T_6713 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_6715 = neq(_T_6713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6716 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_6717 = not(_T_6716) @[RegMapper.scala 136:45] + node _T_6719 = eq(_T_6717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6720 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_6722 = neq(_T_6720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6723 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_6724 = not(_T_6723) @[RegMapper.scala 138:44] + node _T_6726 = eq(_T_6724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6727 = and(_T_1958[71], _T_6715) @[RegMapper.scala 140:69] + node _T_6728 = and(_T_3086[71], _T_6722) @[RegMapper.scala 140:91] + node _T_6731 = and(_T_2146[71], _T_6719) @[RegMapper.scala 141:62] + node _T_6732 = and(_T_3274[71], _T_6726) @[RegMapper.scala 141:84] + node _T_6733 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_6732 : @[RegField.scala 70:88] + ramMem[10] <= _T_6733 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6737 = eq(_T_6715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6738 = or(UInt<1>("h01"), _T_6737) @[RegMapper.scala 142:31] + _T_2334[71] <= _T_6738 @[RegMapper.scala 142:18] + node _T_6740 = eq(_T_6719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6741 = or(UInt<1>("h01"), _T_6740) @[RegMapper.scala 143:31] + _T_2522[71] <= _T_6741 @[RegMapper.scala 143:18] + node _T_6743 = eq(_T_6722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6744 = or(UInt<1>("h01"), _T_6743) @[RegMapper.scala 144:31] + _T_2710[71] <= _T_6744 @[RegMapper.scala 144:18] + node _T_6746 = eq(_T_6726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6747 = or(UInt<1>("h01"), _T_6746) @[RegMapper.scala 145:31] + _T_2898[71] <= _T_6747 @[RegMapper.scala 145:18] + node _T_6748 = shl(ramMem[10], 16) @[RegMapper.scala 150:47] + node _T_6750 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_6751 = and(_T_6748, _T_6750) @[RegMapper.scala 150:55] + node _T_6752 = or(_T_6712, _T_6751) @[RegMapper.scala 150:35] + node _T_6753 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_6755 = neq(_T_6753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6756 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_6757 = not(_T_6756) @[RegMapper.scala 136:45] + node _T_6759 = eq(_T_6757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6760 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_6762 = neq(_T_6760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6763 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_6764 = not(_T_6763) @[RegMapper.scala 138:44] + node _T_6766 = eq(_T_6764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6767 = and(_T_1958[72], _T_6755) @[RegMapper.scala 140:69] + node _T_6768 = and(_T_3086[72], _T_6762) @[RegMapper.scala 140:91] + node _T_6771 = and(_T_2146[72], _T_6759) @[RegMapper.scala 141:62] + node _T_6772 = and(_T_3274[72], _T_6766) @[RegMapper.scala 141:84] + node _T_6773 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_6772 : @[RegField.scala 70:88] + ramMem[11] <= _T_6773 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6777 = eq(_T_6755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6778 = or(UInt<1>("h01"), _T_6777) @[RegMapper.scala 142:31] + _T_2334[72] <= _T_6778 @[RegMapper.scala 142:18] + node _T_6780 = eq(_T_6759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6781 = or(UInt<1>("h01"), _T_6780) @[RegMapper.scala 143:31] + _T_2522[72] <= _T_6781 @[RegMapper.scala 143:18] + node _T_6783 = eq(_T_6762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6784 = or(UInt<1>("h01"), _T_6783) @[RegMapper.scala 144:31] + _T_2710[72] <= _T_6784 @[RegMapper.scala 144:18] + node _T_6786 = eq(_T_6766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6787 = or(UInt<1>("h01"), _T_6786) @[RegMapper.scala 145:31] + _T_2898[72] <= _T_6787 @[RegMapper.scala 145:18] + node _T_6788 = shl(ramMem[11], 24) @[RegMapper.scala 150:47] + node _T_6790 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_6791 = and(_T_6788, _T_6790) @[RegMapper.scala 150:55] + node _T_6792 = or(_T_6752, _T_6791) @[RegMapper.scala 150:35] + node _T_6793 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_6795 = neq(_T_6793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6796 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_6797 = not(_T_6796) @[RegMapper.scala 136:45] + node _T_6799 = eq(_T_6797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6800 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_6802 = neq(_T_6800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6803 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_6804 = not(_T_6803) @[RegMapper.scala 138:44] + node _T_6806 = eq(_T_6804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6807 = and(_T_1958[73], _T_6795) @[RegMapper.scala 140:69] + node _T_6808 = and(_T_3086[73], _T_6802) @[RegMapper.scala 140:91] + node _T_6811 = and(_T_2146[73], _T_6799) @[RegMapper.scala 141:62] + node _T_6812 = and(_T_3274[73], _T_6806) @[RegMapper.scala 141:84] + node _T_6813 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_6812 : @[RegField.scala 70:88] + ramMem[12] <= _T_6813 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6817 = eq(_T_6795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6818 = or(UInt<1>("h01"), _T_6817) @[RegMapper.scala 142:31] + _T_2334[73] <= _T_6818 @[RegMapper.scala 142:18] + node _T_6820 = eq(_T_6799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6821 = or(UInt<1>("h01"), _T_6820) @[RegMapper.scala 143:31] + _T_2522[73] <= _T_6821 @[RegMapper.scala 143:18] + node _T_6823 = eq(_T_6802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6824 = or(UInt<1>("h01"), _T_6823) @[RegMapper.scala 144:31] + _T_2710[73] <= _T_6824 @[RegMapper.scala 144:18] + node _T_6826 = eq(_T_6806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6827 = or(UInt<1>("h01"), _T_6826) @[RegMapper.scala 145:31] + _T_2898[73] <= _T_6827 @[RegMapper.scala 145:18] + node _T_6828 = shl(ramMem[12], 32) @[RegMapper.scala 150:47] + node _T_6830 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_6831 = and(_T_6828, _T_6830) @[RegMapper.scala 150:55] + node _T_6832 = or(_T_6792, _T_6831) @[RegMapper.scala 150:35] + node _T_6833 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_6835 = neq(_T_6833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6836 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_6837 = not(_T_6836) @[RegMapper.scala 136:45] + node _T_6839 = eq(_T_6837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6840 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_6842 = neq(_T_6840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6843 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_6844 = not(_T_6843) @[RegMapper.scala 138:44] + node _T_6846 = eq(_T_6844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6847 = and(_T_1958[74], _T_6835) @[RegMapper.scala 140:69] + node _T_6848 = and(_T_3086[74], _T_6842) @[RegMapper.scala 140:91] + node _T_6851 = and(_T_2146[74], _T_6839) @[RegMapper.scala 141:62] + node _T_6852 = and(_T_3274[74], _T_6846) @[RegMapper.scala 141:84] + node _T_6853 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_6852 : @[RegField.scala 70:88] + ramMem[13] <= _T_6853 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6857 = eq(_T_6835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6858 = or(UInt<1>("h01"), _T_6857) @[RegMapper.scala 142:31] + _T_2334[74] <= _T_6858 @[RegMapper.scala 142:18] + node _T_6860 = eq(_T_6839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6861 = or(UInt<1>("h01"), _T_6860) @[RegMapper.scala 143:31] + _T_2522[74] <= _T_6861 @[RegMapper.scala 143:18] + node _T_6863 = eq(_T_6842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6864 = or(UInt<1>("h01"), _T_6863) @[RegMapper.scala 144:31] + _T_2710[74] <= _T_6864 @[RegMapper.scala 144:18] + node _T_6866 = eq(_T_6846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6867 = or(UInt<1>("h01"), _T_6866) @[RegMapper.scala 145:31] + _T_2898[74] <= _T_6867 @[RegMapper.scala 145:18] + node _T_6868 = shl(ramMem[13], 40) @[RegMapper.scala 150:47] + node _T_6870 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_6871 = and(_T_6868, _T_6870) @[RegMapper.scala 150:55] + node _T_6872 = or(_T_6832, _T_6871) @[RegMapper.scala 150:35] + node _T_6873 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_6875 = neq(_T_6873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6876 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_6877 = not(_T_6876) @[RegMapper.scala 136:45] + node _T_6879 = eq(_T_6877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6880 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_6882 = neq(_T_6880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6883 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_6884 = not(_T_6883) @[RegMapper.scala 138:44] + node _T_6886 = eq(_T_6884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6887 = and(_T_1958[75], _T_6875) @[RegMapper.scala 140:69] + node _T_6888 = and(_T_3086[75], _T_6882) @[RegMapper.scala 140:91] + node _T_6891 = and(_T_2146[75], _T_6879) @[RegMapper.scala 141:62] + node _T_6892 = and(_T_3274[75], _T_6886) @[RegMapper.scala 141:84] + node _T_6893 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_6892 : @[RegField.scala 70:88] + ramMem[14] <= _T_6893 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6897 = eq(_T_6875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6898 = or(UInt<1>("h01"), _T_6897) @[RegMapper.scala 142:31] + _T_2334[75] <= _T_6898 @[RegMapper.scala 142:18] + node _T_6900 = eq(_T_6879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6901 = or(UInt<1>("h01"), _T_6900) @[RegMapper.scala 143:31] + _T_2522[75] <= _T_6901 @[RegMapper.scala 143:18] + node _T_6903 = eq(_T_6882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6904 = or(UInt<1>("h01"), _T_6903) @[RegMapper.scala 144:31] + _T_2710[75] <= _T_6904 @[RegMapper.scala 144:18] + node _T_6906 = eq(_T_6886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6907 = or(UInt<1>("h01"), _T_6906) @[RegMapper.scala 145:31] + _T_2898[75] <= _T_6907 @[RegMapper.scala 145:18] + node _T_6908 = shl(ramMem[14], 48) @[RegMapper.scala 150:47] + node _T_6910 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_6911 = and(_T_6908, _T_6910) @[RegMapper.scala 150:55] + node _T_6912 = or(_T_6872, _T_6911) @[RegMapper.scala 150:35] + node _T_6913 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_6915 = neq(_T_6913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6916 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_6917 = not(_T_6916) @[RegMapper.scala 136:45] + node _T_6919 = eq(_T_6917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6920 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_6922 = neq(_T_6920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6923 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_6924 = not(_T_6923) @[RegMapper.scala 138:44] + node _T_6926 = eq(_T_6924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6927 = and(_T_1958[76], _T_6915) @[RegMapper.scala 140:69] + node _T_6928 = and(_T_3086[76], _T_6922) @[RegMapper.scala 140:91] + node _T_6931 = and(_T_2146[76], _T_6919) @[RegMapper.scala 141:62] + node _T_6932 = and(_T_3274[76], _T_6926) @[RegMapper.scala 141:84] + node _T_6933 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_6932 : @[RegField.scala 70:88] + ramMem[15] <= _T_6933 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6937 = eq(_T_6915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6938 = or(UInt<1>("h01"), _T_6937) @[RegMapper.scala 142:31] + _T_2334[76] <= _T_6938 @[RegMapper.scala 142:18] + node _T_6940 = eq(_T_6919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6941 = or(UInt<1>("h01"), _T_6940) @[RegMapper.scala 143:31] + _T_2522[76] <= _T_6941 @[RegMapper.scala 143:18] + node _T_6943 = eq(_T_6922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6944 = or(UInt<1>("h01"), _T_6943) @[RegMapper.scala 144:31] + _T_2710[76] <= _T_6944 @[RegMapper.scala 144:18] + node _T_6946 = eq(_T_6926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6947 = or(UInt<1>("h01"), _T_6946) @[RegMapper.scala 145:31] + _T_2898[76] <= _T_6947 @[RegMapper.scala 145:18] + node _T_6948 = shl(ramMem[15], 56) @[RegMapper.scala 150:47] + node _T_6950 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_6951 = and(_T_6948, _T_6950) @[RegMapper.scala 150:55] + node _T_6952 = or(_T_6912, _T_6951) @[RegMapper.scala 150:35] + node _T_6953 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_6955 = neq(_T_6953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6956 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_6957 = not(_T_6956) @[RegMapper.scala 136:45] + node _T_6959 = eq(_T_6957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_6960 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_6962 = neq(_T_6960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_6963 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_6964 = not(_T_6963) @[RegMapper.scala 138:44] + node _T_6966 = eq(_T_6964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_6967 = and(_T_1958[77], _T_6955) @[RegMapper.scala 140:69] + node _T_6968 = and(_T_3086[77], _T_6962) @[RegMapper.scala 140:91] + node _T_6971 = and(_T_2146[77], _T_6959) @[RegMapper.scala 141:62] + node _T_6972 = and(_T_3274[77], _T_6966) @[RegMapper.scala 141:84] + node _T_6973 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_6972 : @[RegField.scala 70:88] + ramMem[48] <= _T_6973 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_6977 = eq(_T_6955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_6978 = or(UInt<1>("h01"), _T_6977) @[RegMapper.scala 142:31] + _T_2334[77] <= _T_6978 @[RegMapper.scala 142:18] + node _T_6980 = eq(_T_6959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_6981 = or(UInt<1>("h01"), _T_6980) @[RegMapper.scala 143:31] + _T_2522[77] <= _T_6981 @[RegMapper.scala 143:18] + node _T_6983 = eq(_T_6962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_6984 = or(UInt<1>("h01"), _T_6983) @[RegMapper.scala 144:31] + _T_2710[77] <= _T_6984 @[RegMapper.scala 144:18] + node _T_6986 = eq(_T_6966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_6987 = or(UInt<1>("h01"), _T_6986) @[RegMapper.scala 145:31] + _T_2898[77] <= _T_6987 @[RegMapper.scala 145:18] + node _T_6988 = shl(ramMem[48], 0) @[RegMapper.scala 150:47] + node _T_6990 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_6991 = and(_T_6988, _T_6990) @[RegMapper.scala 150:55] + node _T_6992 = or(UInt<1>("h00"), _T_6991) @[RegMapper.scala 150:35] + node _T_6993 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_6995 = neq(_T_6993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_6996 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_6997 = not(_T_6996) @[RegMapper.scala 136:45] + node _T_6999 = eq(_T_6997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7000 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_7002 = neq(_T_7000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7003 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_7004 = not(_T_7003) @[RegMapper.scala 138:44] + node _T_7006 = eq(_T_7004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7007 = and(_T_1958[78], _T_6995) @[RegMapper.scala 140:69] + node _T_7008 = and(_T_3086[78], _T_7002) @[RegMapper.scala 140:91] + node _T_7011 = and(_T_2146[78], _T_6999) @[RegMapper.scala 141:62] + node _T_7012 = and(_T_3274[78], _T_7006) @[RegMapper.scala 141:84] + node _T_7013 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_7012 : @[RegField.scala 70:88] + ramMem[49] <= _T_7013 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7017 = eq(_T_6995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7018 = or(UInt<1>("h01"), _T_7017) @[RegMapper.scala 142:31] + _T_2334[78] <= _T_7018 @[RegMapper.scala 142:18] + node _T_7020 = eq(_T_6999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7021 = or(UInt<1>("h01"), _T_7020) @[RegMapper.scala 143:31] + _T_2522[78] <= _T_7021 @[RegMapper.scala 143:18] + node _T_7023 = eq(_T_7002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7024 = or(UInt<1>("h01"), _T_7023) @[RegMapper.scala 144:31] + _T_2710[78] <= _T_7024 @[RegMapper.scala 144:18] + node _T_7026 = eq(_T_7006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7027 = or(UInt<1>("h01"), _T_7026) @[RegMapper.scala 145:31] + _T_2898[78] <= _T_7027 @[RegMapper.scala 145:18] + node _T_7028 = shl(ramMem[49], 8) @[RegMapper.scala 150:47] + node _T_7030 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_7031 = and(_T_7028, _T_7030) @[RegMapper.scala 150:55] + node _T_7032 = or(_T_6992, _T_7031) @[RegMapper.scala 150:35] + node _T_7033 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_7035 = neq(_T_7033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7036 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_7037 = not(_T_7036) @[RegMapper.scala 136:45] + node _T_7039 = eq(_T_7037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7040 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_7042 = neq(_T_7040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7043 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_7044 = not(_T_7043) @[RegMapper.scala 138:44] + node _T_7046 = eq(_T_7044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7047 = and(_T_1958[79], _T_7035) @[RegMapper.scala 140:69] + node _T_7048 = and(_T_3086[79], _T_7042) @[RegMapper.scala 140:91] + node _T_7051 = and(_T_2146[79], _T_7039) @[RegMapper.scala 141:62] + node _T_7052 = and(_T_3274[79], _T_7046) @[RegMapper.scala 141:84] + node _T_7053 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_7052 : @[RegField.scala 70:88] + ramMem[50] <= _T_7053 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7057 = eq(_T_7035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7058 = or(UInt<1>("h01"), _T_7057) @[RegMapper.scala 142:31] + _T_2334[79] <= _T_7058 @[RegMapper.scala 142:18] + node _T_7060 = eq(_T_7039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7061 = or(UInt<1>("h01"), _T_7060) @[RegMapper.scala 143:31] + _T_2522[79] <= _T_7061 @[RegMapper.scala 143:18] + node _T_7063 = eq(_T_7042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7064 = or(UInt<1>("h01"), _T_7063) @[RegMapper.scala 144:31] + _T_2710[79] <= _T_7064 @[RegMapper.scala 144:18] + node _T_7066 = eq(_T_7046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7067 = or(UInt<1>("h01"), _T_7066) @[RegMapper.scala 145:31] + _T_2898[79] <= _T_7067 @[RegMapper.scala 145:18] + node _T_7068 = shl(ramMem[50], 16) @[RegMapper.scala 150:47] + node _T_7070 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_7071 = and(_T_7068, _T_7070) @[RegMapper.scala 150:55] + node _T_7072 = or(_T_7032, _T_7071) @[RegMapper.scala 150:35] + node _T_7073 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_7075 = neq(_T_7073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7076 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_7077 = not(_T_7076) @[RegMapper.scala 136:45] + node _T_7079 = eq(_T_7077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7080 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_7082 = neq(_T_7080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7083 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_7084 = not(_T_7083) @[RegMapper.scala 138:44] + node _T_7086 = eq(_T_7084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7087 = and(_T_1958[80], _T_7075) @[RegMapper.scala 140:69] + node _T_7088 = and(_T_3086[80], _T_7082) @[RegMapper.scala 140:91] + node _T_7091 = and(_T_2146[80], _T_7079) @[RegMapper.scala 141:62] + node _T_7092 = and(_T_3274[80], _T_7086) @[RegMapper.scala 141:84] + node _T_7093 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_7092 : @[RegField.scala 70:88] + ramMem[51] <= _T_7093 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7097 = eq(_T_7075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7098 = or(UInt<1>("h01"), _T_7097) @[RegMapper.scala 142:31] + _T_2334[80] <= _T_7098 @[RegMapper.scala 142:18] + node _T_7100 = eq(_T_7079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7101 = or(UInt<1>("h01"), _T_7100) @[RegMapper.scala 143:31] + _T_2522[80] <= _T_7101 @[RegMapper.scala 143:18] + node _T_7103 = eq(_T_7082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7104 = or(UInt<1>("h01"), _T_7103) @[RegMapper.scala 144:31] + _T_2710[80] <= _T_7104 @[RegMapper.scala 144:18] + node _T_7106 = eq(_T_7086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7107 = or(UInt<1>("h01"), _T_7106) @[RegMapper.scala 145:31] + _T_2898[80] <= _T_7107 @[RegMapper.scala 145:18] + node _T_7108 = shl(ramMem[51], 24) @[RegMapper.scala 150:47] + node _T_7110 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_7111 = and(_T_7108, _T_7110) @[RegMapper.scala 150:55] + node _T_7112 = or(_T_7072, _T_7111) @[RegMapper.scala 150:35] + node _T_7113 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_7115 = neq(_T_7113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7116 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_7117 = not(_T_7116) @[RegMapper.scala 136:45] + node _T_7119 = eq(_T_7117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7120 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_7122 = neq(_T_7120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7123 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_7124 = not(_T_7123) @[RegMapper.scala 138:44] + node _T_7126 = eq(_T_7124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7127 = and(_T_1958[81], _T_7115) @[RegMapper.scala 140:69] + node _T_7128 = and(_T_3086[81], _T_7122) @[RegMapper.scala 140:91] + node _T_7131 = and(_T_2146[81], _T_7119) @[RegMapper.scala 141:62] + node _T_7132 = and(_T_3274[81], _T_7126) @[RegMapper.scala 141:84] + node _T_7133 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_7132 : @[RegField.scala 70:88] + ramMem[52] <= _T_7133 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7137 = eq(_T_7115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7138 = or(UInt<1>("h01"), _T_7137) @[RegMapper.scala 142:31] + _T_2334[81] <= _T_7138 @[RegMapper.scala 142:18] + node _T_7140 = eq(_T_7119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7141 = or(UInt<1>("h01"), _T_7140) @[RegMapper.scala 143:31] + _T_2522[81] <= _T_7141 @[RegMapper.scala 143:18] + node _T_7143 = eq(_T_7122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7144 = or(UInt<1>("h01"), _T_7143) @[RegMapper.scala 144:31] + _T_2710[81] <= _T_7144 @[RegMapper.scala 144:18] + node _T_7146 = eq(_T_7126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7147 = or(UInt<1>("h01"), _T_7146) @[RegMapper.scala 145:31] + _T_2898[81] <= _T_7147 @[RegMapper.scala 145:18] + node _T_7148 = shl(ramMem[52], 32) @[RegMapper.scala 150:47] + node _T_7150 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_7151 = and(_T_7148, _T_7150) @[RegMapper.scala 150:55] + node _T_7152 = or(_T_7112, _T_7151) @[RegMapper.scala 150:35] + node _T_7153 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_7155 = neq(_T_7153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7156 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_7157 = not(_T_7156) @[RegMapper.scala 136:45] + node _T_7159 = eq(_T_7157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7160 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_7162 = neq(_T_7160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7163 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_7164 = not(_T_7163) @[RegMapper.scala 138:44] + node _T_7166 = eq(_T_7164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7167 = and(_T_1958[82], _T_7155) @[RegMapper.scala 140:69] + node _T_7168 = and(_T_3086[82], _T_7162) @[RegMapper.scala 140:91] + node _T_7171 = and(_T_2146[82], _T_7159) @[RegMapper.scala 141:62] + node _T_7172 = and(_T_3274[82], _T_7166) @[RegMapper.scala 141:84] + node _T_7173 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_7172 : @[RegField.scala 70:88] + ramMem[53] <= _T_7173 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7177 = eq(_T_7155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7178 = or(UInt<1>("h01"), _T_7177) @[RegMapper.scala 142:31] + _T_2334[82] <= _T_7178 @[RegMapper.scala 142:18] + node _T_7180 = eq(_T_7159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7181 = or(UInt<1>("h01"), _T_7180) @[RegMapper.scala 143:31] + _T_2522[82] <= _T_7181 @[RegMapper.scala 143:18] + node _T_7183 = eq(_T_7162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7184 = or(UInt<1>("h01"), _T_7183) @[RegMapper.scala 144:31] + _T_2710[82] <= _T_7184 @[RegMapper.scala 144:18] + node _T_7186 = eq(_T_7166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7187 = or(UInt<1>("h01"), _T_7186) @[RegMapper.scala 145:31] + _T_2898[82] <= _T_7187 @[RegMapper.scala 145:18] + node _T_7188 = shl(ramMem[53], 40) @[RegMapper.scala 150:47] + node _T_7190 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_7191 = and(_T_7188, _T_7190) @[RegMapper.scala 150:55] + node _T_7192 = or(_T_7152, _T_7191) @[RegMapper.scala 150:35] + node _T_7193 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_7195 = neq(_T_7193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7196 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_7197 = not(_T_7196) @[RegMapper.scala 136:45] + node _T_7199 = eq(_T_7197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7200 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_7202 = neq(_T_7200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7203 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_7204 = not(_T_7203) @[RegMapper.scala 138:44] + node _T_7206 = eq(_T_7204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7207 = and(_T_1958[83], _T_7195) @[RegMapper.scala 140:69] + node _T_7208 = and(_T_3086[83], _T_7202) @[RegMapper.scala 140:91] + node _T_7211 = and(_T_2146[83], _T_7199) @[RegMapper.scala 141:62] + node _T_7212 = and(_T_3274[83], _T_7206) @[RegMapper.scala 141:84] + node _T_7213 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_7212 : @[RegField.scala 70:88] + ramMem[54] <= _T_7213 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7217 = eq(_T_7195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7218 = or(UInt<1>("h01"), _T_7217) @[RegMapper.scala 142:31] + _T_2334[83] <= _T_7218 @[RegMapper.scala 142:18] + node _T_7220 = eq(_T_7199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7221 = or(UInt<1>("h01"), _T_7220) @[RegMapper.scala 143:31] + _T_2522[83] <= _T_7221 @[RegMapper.scala 143:18] + node _T_7223 = eq(_T_7202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7224 = or(UInt<1>("h01"), _T_7223) @[RegMapper.scala 144:31] + _T_2710[83] <= _T_7224 @[RegMapper.scala 144:18] + node _T_7226 = eq(_T_7206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7227 = or(UInt<1>("h01"), _T_7226) @[RegMapper.scala 145:31] + _T_2898[83] <= _T_7227 @[RegMapper.scala 145:18] + node _T_7228 = shl(ramMem[54], 48) @[RegMapper.scala 150:47] + node _T_7230 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_7231 = and(_T_7228, _T_7230) @[RegMapper.scala 150:55] + node _T_7232 = or(_T_7192, _T_7231) @[RegMapper.scala 150:35] + node _T_7233 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_7235 = neq(_T_7233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7236 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_7237 = not(_T_7236) @[RegMapper.scala 136:45] + node _T_7239 = eq(_T_7237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7240 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_7242 = neq(_T_7240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7243 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_7244 = not(_T_7243) @[RegMapper.scala 138:44] + node _T_7246 = eq(_T_7244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7247 = and(_T_1958[84], _T_7235) @[RegMapper.scala 140:69] + node _T_7248 = and(_T_3086[84], _T_7242) @[RegMapper.scala 140:91] + node _T_7251 = and(_T_2146[84], _T_7239) @[RegMapper.scala 141:62] + node _T_7252 = and(_T_3274[84], _T_7246) @[RegMapper.scala 141:84] + node _T_7253 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_7252 : @[RegField.scala 70:88] + ramMem[55] <= _T_7253 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7257 = eq(_T_7235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7258 = or(UInt<1>("h01"), _T_7257) @[RegMapper.scala 142:31] + _T_2334[84] <= _T_7258 @[RegMapper.scala 142:18] + node _T_7260 = eq(_T_7239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7261 = or(UInt<1>("h01"), _T_7260) @[RegMapper.scala 143:31] + _T_2522[84] <= _T_7261 @[RegMapper.scala 143:18] + node _T_7263 = eq(_T_7242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7264 = or(UInt<1>("h01"), _T_7263) @[RegMapper.scala 144:31] + _T_2710[84] <= _T_7264 @[RegMapper.scala 144:18] + node _T_7266 = eq(_T_7246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7267 = or(UInt<1>("h01"), _T_7266) @[RegMapper.scala 145:31] + _T_2898[84] <= _T_7267 @[RegMapper.scala 145:18] + node _T_7268 = shl(ramMem[55], 56) @[RegMapper.scala 150:47] + node _T_7270 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_7271 = and(_T_7268, _T_7270) @[RegMapper.scala 150:55] + node _T_7272 = or(_T_7232, _T_7271) @[RegMapper.scala 150:35] + node _T_7273 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_7275 = neq(_T_7273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7276 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_7277 = not(_T_7276) @[RegMapper.scala 136:45] + node _T_7279 = eq(_T_7277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7280 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_7282 = neq(_T_7280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7283 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_7284 = not(_T_7283) @[RegMapper.scala 138:44] + node _T_7286 = eq(_T_7284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7287 = and(_T_1958[85], _T_7275) @[RegMapper.scala 140:69] + node _T_7288 = and(_T_3086[85], _T_7282) @[RegMapper.scala 140:91] + node _T_7291 = and(_T_2146[85], _T_7279) @[RegMapper.scala 141:62] + node _T_7292 = and(_T_3274[85], _T_7286) @[RegMapper.scala 141:84] + node _T_7293 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_7292 : @[RegField.scala 70:88] + ramMem[0] <= _T_7293 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7297 = eq(_T_7275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7298 = or(UInt<1>("h01"), _T_7297) @[RegMapper.scala 142:31] + _T_2334[85] <= _T_7298 @[RegMapper.scala 142:18] + node _T_7300 = eq(_T_7279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7301 = or(UInt<1>("h01"), _T_7300) @[RegMapper.scala 143:31] + _T_2522[85] <= _T_7301 @[RegMapper.scala 143:18] + node _T_7303 = eq(_T_7282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7304 = or(UInt<1>("h01"), _T_7303) @[RegMapper.scala 144:31] + _T_2710[85] <= _T_7304 @[RegMapper.scala 144:18] + node _T_7306 = eq(_T_7286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7307 = or(UInt<1>("h01"), _T_7306) @[RegMapper.scala 145:31] + _T_2898[85] <= _T_7307 @[RegMapper.scala 145:18] + node _T_7308 = shl(ramMem[0], 0) @[RegMapper.scala 150:47] + node _T_7310 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_7311 = and(_T_7308, _T_7310) @[RegMapper.scala 150:55] + node _T_7312 = or(UInt<1>("h00"), _T_7311) @[RegMapper.scala 150:35] + node _T_7313 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_7315 = neq(_T_7313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7316 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_7317 = not(_T_7316) @[RegMapper.scala 136:45] + node _T_7319 = eq(_T_7317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7320 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_7322 = neq(_T_7320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7323 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_7324 = not(_T_7323) @[RegMapper.scala 138:44] + node _T_7326 = eq(_T_7324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7327 = and(_T_1958[86], _T_7315) @[RegMapper.scala 140:69] + node _T_7328 = and(_T_3086[86], _T_7322) @[RegMapper.scala 140:91] + node _T_7331 = and(_T_2146[86], _T_7319) @[RegMapper.scala 141:62] + node _T_7332 = and(_T_3274[86], _T_7326) @[RegMapper.scala 141:84] + node _T_7333 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_7332 : @[RegField.scala 70:88] + ramMem[1] <= _T_7333 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7337 = eq(_T_7315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7338 = or(UInt<1>("h01"), _T_7337) @[RegMapper.scala 142:31] + _T_2334[86] <= _T_7338 @[RegMapper.scala 142:18] + node _T_7340 = eq(_T_7319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7341 = or(UInt<1>("h01"), _T_7340) @[RegMapper.scala 143:31] + _T_2522[86] <= _T_7341 @[RegMapper.scala 143:18] + node _T_7343 = eq(_T_7322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7344 = or(UInt<1>("h01"), _T_7343) @[RegMapper.scala 144:31] + _T_2710[86] <= _T_7344 @[RegMapper.scala 144:18] + node _T_7346 = eq(_T_7326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7347 = or(UInt<1>("h01"), _T_7346) @[RegMapper.scala 145:31] + _T_2898[86] <= _T_7347 @[RegMapper.scala 145:18] + node _T_7348 = shl(ramMem[1], 8) @[RegMapper.scala 150:47] + node _T_7350 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_7351 = and(_T_7348, _T_7350) @[RegMapper.scala 150:55] + node _T_7352 = or(_T_7312, _T_7351) @[RegMapper.scala 150:35] + node _T_7353 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_7355 = neq(_T_7353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7356 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_7357 = not(_T_7356) @[RegMapper.scala 136:45] + node _T_7359 = eq(_T_7357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7360 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_7362 = neq(_T_7360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7363 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_7364 = not(_T_7363) @[RegMapper.scala 138:44] + node _T_7366 = eq(_T_7364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7367 = and(_T_1958[87], _T_7355) @[RegMapper.scala 140:69] + node _T_7368 = and(_T_3086[87], _T_7362) @[RegMapper.scala 140:91] + node _T_7371 = and(_T_2146[87], _T_7359) @[RegMapper.scala 141:62] + node _T_7372 = and(_T_3274[87], _T_7366) @[RegMapper.scala 141:84] + node _T_7373 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_7372 : @[RegField.scala 70:88] + ramMem[2] <= _T_7373 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7377 = eq(_T_7355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7378 = or(UInt<1>("h01"), _T_7377) @[RegMapper.scala 142:31] + _T_2334[87] <= _T_7378 @[RegMapper.scala 142:18] + node _T_7380 = eq(_T_7359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7381 = or(UInt<1>("h01"), _T_7380) @[RegMapper.scala 143:31] + _T_2522[87] <= _T_7381 @[RegMapper.scala 143:18] + node _T_7383 = eq(_T_7362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7384 = or(UInt<1>("h01"), _T_7383) @[RegMapper.scala 144:31] + _T_2710[87] <= _T_7384 @[RegMapper.scala 144:18] + node _T_7386 = eq(_T_7366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7387 = or(UInt<1>("h01"), _T_7386) @[RegMapper.scala 145:31] + _T_2898[87] <= _T_7387 @[RegMapper.scala 145:18] + node _T_7388 = shl(ramMem[2], 16) @[RegMapper.scala 150:47] + node _T_7390 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_7391 = and(_T_7388, _T_7390) @[RegMapper.scala 150:55] + node _T_7392 = or(_T_7352, _T_7391) @[RegMapper.scala 150:35] + node _T_7393 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_7395 = neq(_T_7393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7396 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_7397 = not(_T_7396) @[RegMapper.scala 136:45] + node _T_7399 = eq(_T_7397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7400 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_7402 = neq(_T_7400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7403 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_7404 = not(_T_7403) @[RegMapper.scala 138:44] + node _T_7406 = eq(_T_7404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7407 = and(_T_1958[88], _T_7395) @[RegMapper.scala 140:69] + node _T_7408 = and(_T_3086[88], _T_7402) @[RegMapper.scala 140:91] + node _T_7411 = and(_T_2146[88], _T_7399) @[RegMapper.scala 141:62] + node _T_7412 = and(_T_3274[88], _T_7406) @[RegMapper.scala 141:84] + node _T_7413 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_7412 : @[RegField.scala 70:88] + ramMem[3] <= _T_7413 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7417 = eq(_T_7395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7418 = or(UInt<1>("h01"), _T_7417) @[RegMapper.scala 142:31] + _T_2334[88] <= _T_7418 @[RegMapper.scala 142:18] + node _T_7420 = eq(_T_7399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7421 = or(UInt<1>("h01"), _T_7420) @[RegMapper.scala 143:31] + _T_2522[88] <= _T_7421 @[RegMapper.scala 143:18] + node _T_7423 = eq(_T_7402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7424 = or(UInt<1>("h01"), _T_7423) @[RegMapper.scala 144:31] + _T_2710[88] <= _T_7424 @[RegMapper.scala 144:18] + node _T_7426 = eq(_T_7406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7427 = or(UInt<1>("h01"), _T_7426) @[RegMapper.scala 145:31] + _T_2898[88] <= _T_7427 @[RegMapper.scala 145:18] + node _T_7428 = shl(ramMem[3], 24) @[RegMapper.scala 150:47] + node _T_7430 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_7431 = and(_T_7428, _T_7430) @[RegMapper.scala 150:55] + node _T_7432 = or(_T_7392, _T_7431) @[RegMapper.scala 150:35] + node _T_7433 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_7435 = neq(_T_7433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7436 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_7437 = not(_T_7436) @[RegMapper.scala 136:45] + node _T_7439 = eq(_T_7437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7440 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_7442 = neq(_T_7440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7443 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_7444 = not(_T_7443) @[RegMapper.scala 138:44] + node _T_7446 = eq(_T_7444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7447 = and(_T_1958[89], _T_7435) @[RegMapper.scala 140:69] + node _T_7448 = and(_T_3086[89], _T_7442) @[RegMapper.scala 140:91] + node _T_7451 = and(_T_2146[89], _T_7439) @[RegMapper.scala 141:62] + node _T_7452 = and(_T_3274[89], _T_7446) @[RegMapper.scala 141:84] + node _T_7453 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_7452 : @[RegField.scala 70:88] + ramMem[4] <= _T_7453 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7457 = eq(_T_7435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7458 = or(UInt<1>("h01"), _T_7457) @[RegMapper.scala 142:31] + _T_2334[89] <= _T_7458 @[RegMapper.scala 142:18] + node _T_7460 = eq(_T_7439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7461 = or(UInt<1>("h01"), _T_7460) @[RegMapper.scala 143:31] + _T_2522[89] <= _T_7461 @[RegMapper.scala 143:18] + node _T_7463 = eq(_T_7442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7464 = or(UInt<1>("h01"), _T_7463) @[RegMapper.scala 144:31] + _T_2710[89] <= _T_7464 @[RegMapper.scala 144:18] + node _T_7466 = eq(_T_7446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7467 = or(UInt<1>("h01"), _T_7466) @[RegMapper.scala 145:31] + _T_2898[89] <= _T_7467 @[RegMapper.scala 145:18] + node _T_7468 = shl(ramMem[4], 32) @[RegMapper.scala 150:47] + node _T_7470 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_7471 = and(_T_7468, _T_7470) @[RegMapper.scala 150:55] + node _T_7472 = or(_T_7432, _T_7471) @[RegMapper.scala 150:35] + node _T_7473 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_7475 = neq(_T_7473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7476 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_7477 = not(_T_7476) @[RegMapper.scala 136:45] + node _T_7479 = eq(_T_7477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7480 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_7482 = neq(_T_7480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7483 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_7484 = not(_T_7483) @[RegMapper.scala 138:44] + node _T_7486 = eq(_T_7484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7487 = and(_T_1958[90], _T_7475) @[RegMapper.scala 140:69] + node _T_7488 = and(_T_3086[90], _T_7482) @[RegMapper.scala 140:91] + node _T_7491 = and(_T_2146[90], _T_7479) @[RegMapper.scala 141:62] + node _T_7492 = and(_T_3274[90], _T_7486) @[RegMapper.scala 141:84] + node _T_7493 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_7492 : @[RegField.scala 70:88] + ramMem[5] <= _T_7493 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7497 = eq(_T_7475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7498 = or(UInt<1>("h01"), _T_7497) @[RegMapper.scala 142:31] + _T_2334[90] <= _T_7498 @[RegMapper.scala 142:18] + node _T_7500 = eq(_T_7479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7501 = or(UInt<1>("h01"), _T_7500) @[RegMapper.scala 143:31] + _T_2522[90] <= _T_7501 @[RegMapper.scala 143:18] + node _T_7503 = eq(_T_7482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7504 = or(UInt<1>("h01"), _T_7503) @[RegMapper.scala 144:31] + _T_2710[90] <= _T_7504 @[RegMapper.scala 144:18] + node _T_7506 = eq(_T_7486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7507 = or(UInt<1>("h01"), _T_7506) @[RegMapper.scala 145:31] + _T_2898[90] <= _T_7507 @[RegMapper.scala 145:18] + node _T_7508 = shl(ramMem[5], 40) @[RegMapper.scala 150:47] + node _T_7510 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_7511 = and(_T_7508, _T_7510) @[RegMapper.scala 150:55] + node _T_7512 = or(_T_7472, _T_7511) @[RegMapper.scala 150:35] + node _T_7513 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_7515 = neq(_T_7513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7516 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_7517 = not(_T_7516) @[RegMapper.scala 136:45] + node _T_7519 = eq(_T_7517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7520 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_7522 = neq(_T_7520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7523 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_7524 = not(_T_7523) @[RegMapper.scala 138:44] + node _T_7526 = eq(_T_7524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7527 = and(_T_1958[91], _T_7515) @[RegMapper.scala 140:69] + node _T_7528 = and(_T_3086[91], _T_7522) @[RegMapper.scala 140:91] + node _T_7531 = and(_T_2146[91], _T_7519) @[RegMapper.scala 141:62] + node _T_7532 = and(_T_3274[91], _T_7526) @[RegMapper.scala 141:84] + node _T_7533 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_7532 : @[RegField.scala 70:88] + ramMem[6] <= _T_7533 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7537 = eq(_T_7515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7538 = or(UInt<1>("h01"), _T_7537) @[RegMapper.scala 142:31] + _T_2334[91] <= _T_7538 @[RegMapper.scala 142:18] + node _T_7540 = eq(_T_7519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7541 = or(UInt<1>("h01"), _T_7540) @[RegMapper.scala 143:31] + _T_2522[91] <= _T_7541 @[RegMapper.scala 143:18] + node _T_7543 = eq(_T_7522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7544 = or(UInt<1>("h01"), _T_7543) @[RegMapper.scala 144:31] + _T_2710[91] <= _T_7544 @[RegMapper.scala 144:18] + node _T_7546 = eq(_T_7526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7547 = or(UInt<1>("h01"), _T_7546) @[RegMapper.scala 145:31] + _T_2898[91] <= _T_7547 @[RegMapper.scala 145:18] + node _T_7548 = shl(ramMem[6], 48) @[RegMapper.scala 150:47] + node _T_7550 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_7551 = and(_T_7548, _T_7550) @[RegMapper.scala 150:55] + node _T_7552 = or(_T_7512, _T_7551) @[RegMapper.scala 150:35] + node _T_7553 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_7555 = neq(_T_7553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7556 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_7557 = not(_T_7556) @[RegMapper.scala 136:45] + node _T_7559 = eq(_T_7557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7560 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_7562 = neq(_T_7560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7563 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_7564 = not(_T_7563) @[RegMapper.scala 138:44] + node _T_7566 = eq(_T_7564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7567 = and(_T_1958[92], _T_7555) @[RegMapper.scala 140:69] + node _T_7568 = and(_T_3086[92], _T_7562) @[RegMapper.scala 140:91] + node _T_7571 = and(_T_2146[92], _T_7559) @[RegMapper.scala 141:62] + node _T_7572 = and(_T_3274[92], _T_7566) @[RegMapper.scala 141:84] + node _T_7573 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_7572 : @[RegField.scala 70:88] + ramMem[7] <= _T_7573 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_7577 = eq(_T_7555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7578 = or(UInt<1>("h01"), _T_7577) @[RegMapper.scala 142:31] + _T_2334[92] <= _T_7578 @[RegMapper.scala 142:18] + node _T_7580 = eq(_T_7559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7581 = or(UInt<1>("h01"), _T_7580) @[RegMapper.scala 143:31] + _T_2522[92] <= _T_7581 @[RegMapper.scala 143:18] + node _T_7583 = eq(_T_7562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7584 = or(UInt<1>("h01"), _T_7583) @[RegMapper.scala 144:31] + _T_2710[92] <= _T_7584 @[RegMapper.scala 144:18] + node _T_7586 = eq(_T_7566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7587 = or(UInt<1>("h01"), _T_7586) @[RegMapper.scala 145:31] + _T_2898[92] <= _T_7587 @[RegMapper.scala 145:18] + node _T_7588 = shl(ramMem[7], 56) @[RegMapper.scala 150:47] + node _T_7590 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_7591 = and(_T_7588, _T_7590) @[RegMapper.scala 150:55] + node _T_7592 = or(_T_7552, _T_7591) @[RegMapper.scala 150:35] + node _T_7593 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_7595 = neq(_T_7593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7596 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_7597 = not(_T_7596) @[RegMapper.scala 136:45] + node _T_7599 = eq(_T_7597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7600 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_7602 = neq(_T_7600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7603 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_7604 = not(_T_7603) @[RegMapper.scala 138:44] + node _T_7606 = eq(_T_7604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7607 = and(_T_1958[93], _T_7595) @[RegMapper.scala 140:69] + node _T_7608 = and(_T_3086[93], _T_7602) @[RegMapper.scala 140:91] + node _T_7611 = and(_T_2146[93], _T_7599) @[RegMapper.scala 141:62] + node _T_7612 = and(_T_3274[93], _T_7606) @[RegMapper.scala 141:84] + node _T_7613 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_7617 = eq(_T_7595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7618 = or(UInt<1>("h01"), _T_7617) @[RegMapper.scala 142:31] + _T_2334[93] <= _T_7618 @[RegMapper.scala 142:18] + node _T_7620 = eq(_T_7599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7621 = or(UInt<1>("h01"), _T_7620) @[RegMapper.scala 143:31] + _T_2522[93] <= _T_7621 @[RegMapper.scala 143:18] + node _T_7623 = eq(_T_7602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7624 = or(UInt<1>("h01"), _T_7623) @[RegMapper.scala 144:31] + _T_2710[93] <= _T_7624 @[RegMapper.scala 144:18] + node _T_7626 = eq(_T_7606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7627 = or(UInt<1>("h01"), _T_7626) @[RegMapper.scala 145:31] + _T_2898[93] <= _T_7627 @[RegMapper.scala 145:18] + node _T_7628 = shl(UInt<6>("h023"), 0) @[RegMapper.scala 150:47] + node _T_7630 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_7631 = and(_T_7628, _T_7630) @[RegMapper.scala 150:55] + node _T_7632 = or(UInt<1>("h00"), _T_7631) @[RegMapper.scala 150:35] + node _T_7633 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_7635 = neq(_T_7633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7636 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_7637 = not(_T_7636) @[RegMapper.scala 136:45] + node _T_7639 = eq(_T_7637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7640 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_7642 = neq(_T_7640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7643 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_7644 = not(_T_7643) @[RegMapper.scala 138:44] + node _T_7646 = eq(_T_7644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7647 = and(_T_1958[94], _T_7635) @[RegMapper.scala 140:69] + node _T_7648 = and(_T_3086[94], _T_7642) @[RegMapper.scala 140:91] + node _T_7651 = and(_T_2146[94], _T_7639) @[RegMapper.scala 141:62] + node _T_7652 = and(_T_3274[94], _T_7646) @[RegMapper.scala 141:84] + node _T_7653 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_7657 = eq(_T_7635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7658 = or(UInt<1>("h01"), _T_7657) @[RegMapper.scala 142:31] + _T_2334[94] <= _T_7658 @[RegMapper.scala 142:18] + node _T_7660 = eq(_T_7639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7661 = or(UInt<1>("h01"), _T_7660) @[RegMapper.scala 143:31] + _T_2522[94] <= _T_7661 @[RegMapper.scala 143:18] + node _T_7663 = eq(_T_7642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7664 = or(UInt<1>("h01"), _T_7663) @[RegMapper.scala 144:31] + _T_2710[94] <= _T_7664 @[RegMapper.scala 144:18] + node _T_7666 = eq(_T_7646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7667 = or(UInt<1>("h01"), _T_7666) @[RegMapper.scala 145:31] + _T_2898[94] <= _T_7667 @[RegMapper.scala 145:18] + node _T_7668 = shl(UInt<6>("h03c"), 8) @[RegMapper.scala 150:47] + node _T_7670 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_7671 = and(_T_7668, _T_7670) @[RegMapper.scala 150:55] + node _T_7672 = or(_T_7632, _T_7671) @[RegMapper.scala 150:35] + node _T_7673 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_7675 = neq(_T_7673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7676 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_7677 = not(_T_7676) @[RegMapper.scala 136:45] + node _T_7679 = eq(_T_7677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7680 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_7682 = neq(_T_7680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7683 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_7684 = not(_T_7683) @[RegMapper.scala 138:44] + node _T_7686 = eq(_T_7684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7687 = and(_T_1958[95], _T_7675) @[RegMapper.scala 140:69] + node _T_7688 = and(_T_3086[95], _T_7682) @[RegMapper.scala 140:91] + node _T_7691 = and(_T_2146[95], _T_7679) @[RegMapper.scala 141:62] + node _T_7692 = and(_T_3274[95], _T_7686) @[RegMapper.scala 141:84] + node _T_7693 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_7697 = eq(_T_7675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7698 = or(UInt<1>("h01"), _T_7697) @[RegMapper.scala 142:31] + _T_2334[95] <= _T_7698 @[RegMapper.scala 142:18] + node _T_7700 = eq(_T_7679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7701 = or(UInt<1>("h01"), _T_7700) @[RegMapper.scala 143:31] + _T_2522[95] <= _T_7701 @[RegMapper.scala 143:18] + node _T_7703 = eq(_T_7682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7704 = or(UInt<1>("h01"), _T_7703) @[RegMapper.scala 144:31] + _T_2710[95] <= _T_7704 @[RegMapper.scala 144:18] + node _T_7706 = eq(_T_7686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7707 = or(UInt<1>("h01"), _T_7706) @[RegMapper.scala 145:31] + _T_2898[95] <= _T_7707 @[RegMapper.scala 145:18] + node _T_7708 = shl(UInt<8>("h090"), 16) @[RegMapper.scala 150:47] + node _T_7710 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_7711 = and(_T_7708, _T_7710) @[RegMapper.scala 150:55] + node _T_7712 = or(_T_7672, _T_7711) @[RegMapper.scala 150:35] + node _T_7713 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_7715 = neq(_T_7713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7716 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_7717 = not(_T_7716) @[RegMapper.scala 136:45] + node _T_7719 = eq(_T_7717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7720 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_7722 = neq(_T_7720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7723 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_7724 = not(_T_7723) @[RegMapper.scala 138:44] + node _T_7726 = eq(_T_7724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7727 = and(_T_1958[96], _T_7715) @[RegMapper.scala 140:69] + node _T_7728 = and(_T_3086[96], _T_7722) @[RegMapper.scala 140:91] + node _T_7731 = and(_T_2146[96], _T_7719) @[RegMapper.scala 141:62] + node _T_7732 = and(_T_3274[96], _T_7726) @[RegMapper.scala 141:84] + node _T_7733 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_7737 = eq(_T_7715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7738 = or(UInt<1>("h01"), _T_7737) @[RegMapper.scala 142:31] + _T_2334[96] <= _T_7738 @[RegMapper.scala 142:18] + node _T_7740 = eq(_T_7719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7741 = or(UInt<1>("h01"), _T_7740) @[RegMapper.scala 143:31] + _T_2522[96] <= _T_7741 @[RegMapper.scala 143:18] + node _T_7743 = eq(_T_7722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7744 = or(UInt<1>("h01"), _T_7743) @[RegMapper.scala 144:31] + _T_2710[96] <= _T_7744 @[RegMapper.scala 144:18] + node _T_7746 = eq(_T_7726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7747 = or(UInt<1>("h01"), _T_7746) @[RegMapper.scala 145:31] + _T_2898[96] <= _T_7747 @[RegMapper.scala 145:18] + node _T_7748 = shl(UInt<7>("h042"), 24) @[RegMapper.scala 150:47] + node _T_7750 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_7751 = and(_T_7748, _T_7750) @[RegMapper.scala 150:55] + node _T_7752 = or(_T_7712, _T_7751) @[RegMapper.scala 150:35] + node _T_7753 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_7755 = neq(_T_7753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7756 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_7757 = not(_T_7756) @[RegMapper.scala 136:45] + node _T_7759 = eq(_T_7757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7760 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_7762 = neq(_T_7760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7763 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_7764 = not(_T_7763) @[RegMapper.scala 138:44] + node _T_7766 = eq(_T_7764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7767 = and(_T_1958[97], _T_7755) @[RegMapper.scala 140:69] + node _T_7768 = and(_T_3086[97], _T_7762) @[RegMapper.scala 140:91] + node _T_7771 = and(_T_2146[97], _T_7759) @[RegMapper.scala 141:62] + node _T_7772 = and(_T_3274[97], _T_7766) @[RegMapper.scala 141:84] + node _T_7773 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_7777 = eq(_T_7755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7778 = or(UInt<1>("h01"), _T_7777) @[RegMapper.scala 142:31] + _T_2334[97] <= _T_7778 @[RegMapper.scala 142:18] + node _T_7780 = eq(_T_7759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7781 = or(UInt<1>("h01"), _T_7780) @[RegMapper.scala 143:31] + _T_2522[97] <= _T_7781 @[RegMapper.scala 143:18] + node _T_7783 = eq(_T_7762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7784 = or(UInt<1>("h01"), _T_7783) @[RegMapper.scala 144:31] + _T_2710[97] <= _T_7784 @[RegMapper.scala 144:18] + node _T_7786 = eq(_T_7766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7787 = or(UInt<1>("h01"), _T_7786) @[RegMapper.scala 145:31] + _T_2898[97] <= _T_7787 @[RegMapper.scala 145:18] + node _T_7788 = shl(UInt<7>("h067"), 32) @[RegMapper.scala 150:47] + node _T_7790 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_7791 = and(_T_7788, _T_7790) @[RegMapper.scala 150:55] + node _T_7792 = or(_T_7752, _T_7791) @[RegMapper.scala 150:35] + node _T_7793 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_7795 = neq(_T_7793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7796 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_7797 = not(_T_7796) @[RegMapper.scala 136:45] + node _T_7799 = eq(_T_7797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7800 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_7802 = neq(_T_7800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7803 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_7804 = not(_T_7803) @[RegMapper.scala 138:44] + node _T_7806 = eq(_T_7804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7807 = and(_T_1958[98], _T_7795) @[RegMapper.scala 140:69] + node _T_7808 = and(_T_3086[98], _T_7802) @[RegMapper.scala 140:91] + node _T_7811 = and(_T_2146[98], _T_7799) @[RegMapper.scala 141:62] + node _T_7812 = and(_T_3274[98], _T_7806) @[RegMapper.scala 141:84] + node _T_7813 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_7817 = eq(_T_7795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7818 = or(UInt<1>("h01"), _T_7817) @[RegMapper.scala 142:31] + _T_2334[98] <= _T_7818 @[RegMapper.scala 142:18] + node _T_7820 = eq(_T_7799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7821 = or(UInt<1>("h01"), _T_7820) @[RegMapper.scala 143:31] + _T_2522[98] <= _T_7821 @[RegMapper.scala 143:18] + node _T_7823 = eq(_T_7802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7824 = or(UInt<1>("h01"), _T_7823) @[RegMapper.scala 144:31] + _T_2710[98] <= _T_7824 @[RegMapper.scala 144:18] + node _T_7826 = eq(_T_7806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7827 = or(UInt<1>("h01"), _T_7826) @[RegMapper.scala 145:31] + _T_2898[98] <= _T_7827 @[RegMapper.scala 145:18] + node _T_7828 = shl(UInt<1>("h00"), 40) @[RegMapper.scala 150:47] + node _T_7830 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_7831 = and(_T_7828, _T_7830) @[RegMapper.scala 150:55] + node _T_7832 = or(_T_7792, _T_7831) @[RegMapper.scala 150:35] + node _T_7833 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_7835 = neq(_T_7833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7836 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_7837 = not(_T_7836) @[RegMapper.scala 136:45] + node _T_7839 = eq(_T_7837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7840 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_7842 = neq(_T_7840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7843 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_7844 = not(_T_7843) @[RegMapper.scala 138:44] + node _T_7846 = eq(_T_7844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7847 = and(_T_1958[99], _T_7835) @[RegMapper.scala 140:69] + node _T_7848 = and(_T_3086[99], _T_7842) @[RegMapper.scala 140:91] + node _T_7851 = and(_T_2146[99], _T_7839) @[RegMapper.scala 141:62] + node _T_7852 = and(_T_3274[99], _T_7846) @[RegMapper.scala 141:84] + node _T_7853 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_7857 = eq(_T_7835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7858 = or(UInt<1>("h01"), _T_7857) @[RegMapper.scala 142:31] + _T_2334[99] <= _T_7858 @[RegMapper.scala 142:18] + node _T_7860 = eq(_T_7839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7861 = or(UInt<1>("h01"), _T_7860) @[RegMapper.scala 143:31] + _T_2522[99] <= _T_7861 @[RegMapper.scala 143:18] + node _T_7863 = eq(_T_7842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7864 = or(UInt<1>("h01"), _T_7863) @[RegMapper.scala 144:31] + _T_2710[99] <= _T_7864 @[RegMapper.scala 144:18] + node _T_7866 = eq(_T_7846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7867 = or(UInt<1>("h01"), _T_7866) @[RegMapper.scala 145:31] + _T_2898[99] <= _T_7867 @[RegMapper.scala 145:18] + node _T_7868 = shl(UInt<1>("h00"), 48) @[RegMapper.scala 150:47] + node _T_7870 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_7871 = and(_T_7868, _T_7870) @[RegMapper.scala 150:55] + node _T_7872 = or(_T_7832, _T_7871) @[RegMapper.scala 150:35] + node _T_7873 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_7875 = neq(_T_7873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7876 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_7877 = not(_T_7876) @[RegMapper.scala 136:45] + node _T_7879 = eq(_T_7877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7880 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_7882 = neq(_T_7880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7883 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_7884 = not(_T_7883) @[RegMapper.scala 138:44] + node _T_7886 = eq(_T_7884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7887 = and(_T_1958[100], _T_7875) @[RegMapper.scala 140:69] + node _T_7888 = and(_T_3086[100], _T_7882) @[RegMapper.scala 140:91] + node _T_7891 = and(_T_2146[100], _T_7879) @[RegMapper.scala 141:62] + node _T_7892 = and(_T_3274[100], _T_7886) @[RegMapper.scala 141:84] + node _T_7893 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_7897 = eq(_T_7875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7898 = or(UInt<1>("h01"), _T_7897) @[RegMapper.scala 142:31] + _T_2334[100] <= _T_7898 @[RegMapper.scala 142:18] + node _T_7900 = eq(_T_7879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7901 = or(UInt<1>("h01"), _T_7900) @[RegMapper.scala 143:31] + _T_2522[100] <= _T_7901 @[RegMapper.scala 143:18] + node _T_7903 = eq(_T_7882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7904 = or(UInt<1>("h01"), _T_7903) @[RegMapper.scala 144:31] + _T_2710[100] <= _T_7904 @[RegMapper.scala 144:18] + node _T_7906 = eq(_T_7886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7907 = or(UInt<1>("h01"), _T_7906) @[RegMapper.scala 145:31] + _T_2898[100] <= _T_7907 @[RegMapper.scala 145:18] + node _T_7908 = shl(UInt<7>("h040"), 56) @[RegMapper.scala 150:47] + node _T_7910 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_7911 = and(_T_7908, _T_7910) @[RegMapper.scala 150:55] + node _T_7912 = or(_T_7872, _T_7911) @[RegMapper.scala 150:35] + node _T_7913 = bits(_T_3825, 9, 0) @[RegMapper.scala 135:29] + node _T_7915 = neq(_T_7913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7916 = bits(_T_3825, 9, 0) @[RegMapper.scala 136:29] + node _T_7917 = not(_T_7916) @[RegMapper.scala 136:45] + node _T_7919 = eq(_T_7917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7920 = bits(_T_3872, 9, 0) @[RegMapper.scala 137:28] + node _T_7922 = neq(_T_7920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7923 = bits(_T_3872, 9, 0) @[RegMapper.scala 138:28] + node _T_7924 = not(_T_7923) @[RegMapper.scala 138:44] + node _T_7926 = eq(_T_7924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7927 = and(_T_1958[101], _T_7915) @[RegMapper.scala 140:69] + node _T_7928 = and(_T_3086[101], _T_7922) @[RegMapper.scala 140:91] + node _T_7931 = and(_T_2146[101], _T_7919) @[RegMapper.scala 141:62] + node _T_7932 = and(_T_3274[101], _T_7926) @[RegMapper.scala 141:84] + node _T_7933 = bits(_T_1583.bits.data, 9, 0) @[RegMapper.scala 141:99] + CLEARDEBINTWrEn <= _T_7932 @[Debug.scala 828:57] + CLEARDEBINTWrData <= _T_7933 @[Debug.scala 828:74] + node _T_7937 = eq(_T_7915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7938 = or(UInt<1>("h01"), _T_7937) @[RegMapper.scala 142:31] + _T_2334[101] <= _T_7938 @[RegMapper.scala 142:18] + node _T_7940 = eq(_T_7919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7941 = or(UInt<1>("h01"), _T_7940) @[RegMapper.scala 143:31] + _T_2522[101] <= _T_7941 @[RegMapper.scala 143:18] + node _T_7943 = eq(_T_7922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7944 = or(UInt<1>("h01"), _T_7943) @[RegMapper.scala 144:31] + _T_2710[101] <= _T_7944 @[RegMapper.scala 144:18] + node _T_7946 = eq(_T_7926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7947 = or(UInt<1>("h01"), _T_7946) @[RegMapper.scala 145:31] + _T_2898[101] <= _T_7947 @[RegMapper.scala 145:18] + node _T_7948 = shl(CLEARDEBINTWrData, 0) @[RegMapper.scala 150:47] + node _T_7950 = not(UInt<10>("h00")) @[RegMapper.scala 150:58] + node _T_7951 = and(_T_7948, _T_7950) @[RegMapper.scala 150:55] + node _T_7952 = or(UInt<1>("h00"), _T_7951) @[RegMapper.scala 150:35] + node _T_7953 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_7955 = neq(_T_7953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7956 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_7957 = not(_T_7956) @[RegMapper.scala 136:45] + node _T_7959 = eq(_T_7957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_7960 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_7962 = neq(_T_7960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_7963 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_7964 = not(_T_7963) @[RegMapper.scala 138:44] + node _T_7966 = eq(_T_7964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_7967 = and(_T_1958[102], _T_7955) @[RegMapper.scala 140:69] + node _T_7968 = and(_T_3086[102], _T_7962) @[RegMapper.scala 140:91] + node _T_7971 = and(_T_2146[102], _T_7959) @[RegMapper.scala 141:62] + node _T_7972 = and(_T_3274[102], _T_7966) @[RegMapper.scala 141:84] + node _T_7973 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_7977 = eq(_T_7955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_7978 = or(UInt<1>("h01"), _T_7977) @[RegMapper.scala 142:31] + _T_2334[102] <= _T_7978 @[RegMapper.scala 142:18] + node _T_7980 = eq(_T_7959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_7981 = or(UInt<1>("h01"), _T_7980) @[RegMapper.scala 143:31] + _T_2522[102] <= _T_7981 @[RegMapper.scala 143:18] + node _T_7983 = eq(_T_7962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_7984 = or(UInt<1>("h01"), _T_7983) @[RegMapper.scala 144:31] + _T_2710[102] <= _T_7984 @[RegMapper.scala 144:18] + node _T_7986 = eq(_T_7966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_7987 = or(UInt<1>("h01"), _T_7986) @[RegMapper.scala 145:31] + _T_2898[102] <= _T_7987 @[RegMapper.scala 145:18] + node _T_7988 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_7990 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_7991 = and(_T_7988, _T_7990) @[RegMapper.scala 150:55] + node _T_7992 = or(UInt<1>("h00"), _T_7991) @[RegMapper.scala 150:35] + node _T_7993 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_7995 = neq(_T_7993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_7996 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_7997 = not(_T_7996) @[RegMapper.scala 136:45] + node _T_7999 = eq(_T_7997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8000 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_8002 = neq(_T_8000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8003 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_8004 = not(_T_8003) @[RegMapper.scala 138:44] + node _T_8006 = eq(_T_8004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8007 = and(_T_1958[103], _T_7995) @[RegMapper.scala 140:69] + node _T_8008 = and(_T_3086[103], _T_8002) @[RegMapper.scala 140:91] + node _T_8011 = and(_T_2146[103], _T_7999) @[RegMapper.scala 141:62] + node _T_8012 = and(_T_3274[103], _T_8006) @[RegMapper.scala 141:84] + node _T_8013 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_8017 = eq(_T_7995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8018 = or(UInt<1>("h01"), _T_8017) @[RegMapper.scala 142:31] + _T_2334[103] <= _T_8018 @[RegMapper.scala 142:18] + node _T_8020 = eq(_T_7999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8021 = or(UInt<1>("h01"), _T_8020) @[RegMapper.scala 143:31] + _T_2522[103] <= _T_8021 @[RegMapper.scala 143:18] + node _T_8023 = eq(_T_8002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8024 = or(UInt<1>("h01"), _T_8023) @[RegMapper.scala 144:31] + _T_2710[103] <= _T_8024 @[RegMapper.scala 144:18] + node _T_8026 = eq(_T_8006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8027 = or(UInt<1>("h01"), _T_8026) @[RegMapper.scala 145:31] + _T_2898[103] <= _T_8027 @[RegMapper.scala 145:18] + node _T_8028 = shl(UInt<6>("h024"), 8) @[RegMapper.scala 150:47] + node _T_8030 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_8031 = and(_T_8028, _T_8030) @[RegMapper.scala 150:55] + node _T_8032 = or(_T_7992, _T_8031) @[RegMapper.scala 150:35] + node _T_8033 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_8035 = neq(_T_8033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8036 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_8037 = not(_T_8036) @[RegMapper.scala 136:45] + node _T_8039 = eq(_T_8037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8040 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_8042 = neq(_T_8040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8043 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_8044 = not(_T_8043) @[RegMapper.scala 138:44] + node _T_8046 = eq(_T_8044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8047 = and(_T_1958[104], _T_8035) @[RegMapper.scala 140:69] + node _T_8048 = and(_T_3086[104], _T_8042) @[RegMapper.scala 140:91] + node _T_8051 = and(_T_2146[104], _T_8039) @[RegMapper.scala 141:62] + node _T_8052 = and(_T_3274[104], _T_8046) @[RegMapper.scala 141:84] + node _T_8053 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_8057 = eq(_T_8035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8058 = or(UInt<1>("h01"), _T_8057) @[RegMapper.scala 142:31] + _T_2334[104] <= _T_8058 @[RegMapper.scala 142:18] + node _T_8060 = eq(_T_8039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8061 = or(UInt<1>("h01"), _T_8060) @[RegMapper.scala 143:31] + _T_2522[104] <= _T_8061 @[RegMapper.scala 143:18] + node _T_8063 = eq(_T_8042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8064 = or(UInt<1>("h01"), _T_8063) @[RegMapper.scala 144:31] + _T_2710[104] <= _T_8064 @[RegMapper.scala 144:18] + node _T_8066 = eq(_T_8046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8067 = or(UInt<1>("h01"), _T_8066) @[RegMapper.scala 145:31] + _T_2898[104] <= _T_8067 @[RegMapper.scala 145:18] + node _T_8068 = shl(UInt<1>("h00"), 16) @[RegMapper.scala 150:47] + node _T_8070 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_8071 = and(_T_8068, _T_8070) @[RegMapper.scala 150:55] + node _T_8072 = or(_T_8032, _T_8071) @[RegMapper.scala 150:35] + node _T_8073 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_8075 = neq(_T_8073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8076 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_8077 = not(_T_8076) @[RegMapper.scala 136:45] + node _T_8079 = eq(_T_8077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8080 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_8082 = neq(_T_8080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8083 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_8084 = not(_T_8083) @[RegMapper.scala 138:44] + node _T_8086 = eq(_T_8084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8087 = and(_T_1958[105], _T_8075) @[RegMapper.scala 140:69] + node _T_8088 = and(_T_3086[105], _T_8082) @[RegMapper.scala 140:91] + node _T_8091 = and(_T_2146[105], _T_8079) @[RegMapper.scala 141:62] + node _T_8092 = and(_T_3274[105], _T_8086) @[RegMapper.scala 141:84] + node _T_8093 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_8097 = eq(_T_8075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8098 = or(UInt<1>("h01"), _T_8097) @[RegMapper.scala 142:31] + _T_2334[105] <= _T_8098 @[RegMapper.scala 142:18] + node _T_8100 = eq(_T_8079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8101 = or(UInt<1>("h01"), _T_8100) @[RegMapper.scala 143:31] + _T_2522[105] <= _T_8101 @[RegMapper.scala 143:18] + node _T_8103 = eq(_T_8082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8104 = or(UInt<1>("h01"), _T_8103) @[RegMapper.scala 144:31] + _T_2710[105] <= _T_8104 @[RegMapper.scala 144:18] + node _T_8106 = eq(_T_8086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8107 = or(UInt<1>("h01"), _T_8106) @[RegMapper.scala 145:31] + _T_2898[105] <= _T_8107 @[RegMapper.scala 145:18] + node _T_8108 = shl(UInt<7>("h07b"), 24) @[RegMapper.scala 150:47] + node _T_8110 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_8111 = and(_T_8108, _T_8110) @[RegMapper.scala 150:55] + node _T_8112 = or(_T_8072, _T_8111) @[RegMapper.scala 150:35] + node _T_8113 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_8115 = neq(_T_8113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8116 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_8117 = not(_T_8116) @[RegMapper.scala 136:45] + node _T_8119 = eq(_T_8117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8120 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_8122 = neq(_T_8120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8123 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_8124 = not(_T_8123) @[RegMapper.scala 138:44] + node _T_8126 = eq(_T_8124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8127 = and(_T_1958[106], _T_8115) @[RegMapper.scala 140:69] + node _T_8128 = and(_T_3086[106], _T_8122) @[RegMapper.scala 140:91] + node _T_8131 = and(_T_2146[106], _T_8119) @[RegMapper.scala 141:62] + node _T_8132 = and(_T_3274[106], _T_8126) @[RegMapper.scala 141:84] + node _T_8133 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_8137 = eq(_T_8115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8138 = or(UInt<1>("h01"), _T_8137) @[RegMapper.scala 142:31] + _T_2334[106] <= _T_8138 @[RegMapper.scala 142:18] + node _T_8140 = eq(_T_8119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8141 = or(UInt<1>("h01"), _T_8140) @[RegMapper.scala 143:31] + _T_2522[106] <= _T_8141 @[RegMapper.scala 143:18] + node _T_8143 = eq(_T_8122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8144 = or(UInt<1>("h01"), _T_8143) @[RegMapper.scala 144:31] + _T_2710[106] <= _T_8144 @[RegMapper.scala 144:18] + node _T_8146 = eq(_T_8126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8147 = or(UInt<1>("h01"), _T_8146) @[RegMapper.scala 145:31] + _T_2898[106] <= _T_8147 @[RegMapper.scala 145:18] + node _T_8148 = shl(UInt<5>("h013"), 32) @[RegMapper.scala 150:47] + node _T_8150 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_8151 = and(_T_8148, _T_8150) @[RegMapper.scala 150:55] + node _T_8152 = or(_T_8112, _T_8151) @[RegMapper.scala 150:35] + node _T_8153 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_8155 = neq(_T_8153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8156 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_8157 = not(_T_8156) @[RegMapper.scala 136:45] + node _T_8159 = eq(_T_8157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8160 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_8162 = neq(_T_8160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8163 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_8164 = not(_T_8163) @[RegMapper.scala 138:44] + node _T_8166 = eq(_T_8164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8167 = and(_T_1958[107], _T_8155) @[RegMapper.scala 140:69] + node _T_8168 = and(_T_3086[107], _T_8162) @[RegMapper.scala 140:91] + node _T_8171 = and(_T_2146[107], _T_8159) @[RegMapper.scala 141:62] + node _T_8172 = and(_T_3274[107], _T_8166) @[RegMapper.scala 141:84] + node _T_8173 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_8177 = eq(_T_8155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8178 = or(UInt<1>("h01"), _T_8177) @[RegMapper.scala 142:31] + _T_2334[107] <= _T_8178 @[RegMapper.scala 142:18] + node _T_8180 = eq(_T_8159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8181 = or(UInt<1>("h01"), _T_8180) @[RegMapper.scala 143:31] + _T_2522[107] <= _T_8181 @[RegMapper.scala 143:18] + node _T_8183 = eq(_T_8162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8184 = or(UInt<1>("h01"), _T_8183) @[RegMapper.scala 144:31] + _T_2710[107] <= _T_8184 @[RegMapper.scala 144:18] + node _T_8186 = eq(_T_8166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8187 = or(UInt<1>("h01"), _T_8186) @[RegMapper.scala 145:31] + _T_2898[107] <= _T_8187 @[RegMapper.scala 145:18] + node _T_8188 = shl(UInt<7>("h074"), 40) @[RegMapper.scala 150:47] + node _T_8190 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_8191 = and(_T_8188, _T_8190) @[RegMapper.scala 150:55] + node _T_8192 = or(_T_8152, _T_8191) @[RegMapper.scala 150:35] + node _T_8193 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_8195 = neq(_T_8193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8196 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_8197 = not(_T_8196) @[RegMapper.scala 136:45] + node _T_8199 = eq(_T_8197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8200 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_8202 = neq(_T_8200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8203 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_8204 = not(_T_8203) @[RegMapper.scala 138:44] + node _T_8206 = eq(_T_8204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8207 = and(_T_1958[108], _T_8195) @[RegMapper.scala 140:69] + node _T_8208 = and(_T_3086[108], _T_8202) @[RegMapper.scala 140:91] + node _T_8211 = and(_T_2146[108], _T_8199) @[RegMapper.scala 141:62] + node _T_8212 = and(_T_3274[108], _T_8206) @[RegMapper.scala 141:84] + node _T_8213 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_8217 = eq(_T_8195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8218 = or(UInt<1>("h01"), _T_8217) @[RegMapper.scala 142:31] + _T_2334[108] <= _T_8218 @[RegMapper.scala 142:18] + node _T_8220 = eq(_T_8199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8221 = or(UInt<1>("h01"), _T_8220) @[RegMapper.scala 143:31] + _T_2522[108] <= _T_8221 @[RegMapper.scala 143:18] + node _T_8223 = eq(_T_8202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8224 = or(UInt<1>("h01"), _T_8223) @[RegMapper.scala 144:31] + _T_2710[108] <= _T_8224 @[RegMapper.scala 144:18] + node _T_8226 = eq(_T_8206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8227 = or(UInt<1>("h01"), _T_8226) @[RegMapper.scala 145:31] + _T_2898[108] <= _T_8227 @[RegMapper.scala 145:18] + node _T_8228 = shl(UInt<3>("h04"), 48) @[RegMapper.scala 150:47] + node _T_8230 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_8231 = and(_T_8228, _T_8230) @[RegMapper.scala 150:55] + node _T_8232 = or(_T_8192, _T_8231) @[RegMapper.scala 150:35] + node _T_8233 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_8235 = neq(_T_8233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8236 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_8237 = not(_T_8236) @[RegMapper.scala 136:45] + node _T_8239 = eq(_T_8237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8240 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_8242 = neq(_T_8240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8243 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_8244 = not(_T_8243) @[RegMapper.scala 138:44] + node _T_8246 = eq(_T_8244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8247 = and(_T_1958[109], _T_8235) @[RegMapper.scala 140:69] + node _T_8248 = and(_T_3086[109], _T_8242) @[RegMapper.scala 140:91] + node _T_8251 = and(_T_2146[109], _T_8239) @[RegMapper.scala 141:62] + node _T_8252 = and(_T_3274[109], _T_8246) @[RegMapper.scala 141:84] + node _T_8253 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_8257 = eq(_T_8235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8258 = or(UInt<1>("h01"), _T_8257) @[RegMapper.scala 142:31] + _T_2334[109] <= _T_8258 @[RegMapper.scala 142:18] + node _T_8260 = eq(_T_8239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8261 = or(UInt<1>("h01"), _T_8260) @[RegMapper.scala 143:31] + _T_2522[109] <= _T_8261 @[RegMapper.scala 143:18] + node _T_8263 = eq(_T_8242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8264 = or(UInt<1>("h01"), _T_8263) @[RegMapper.scala 144:31] + _T_2710[109] <= _T_8264 @[RegMapper.scala 144:18] + node _T_8266 = eq(_T_8246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8267 = or(UInt<1>("h01"), _T_8266) @[RegMapper.scala 145:31] + _T_2898[109] <= _T_8267 @[RegMapper.scala 145:18] + node _T_8268 = shl(UInt<5>("h01c"), 56) @[RegMapper.scala 150:47] + node _T_8270 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_8271 = and(_T_8268, _T_8270) @[RegMapper.scala 150:55] + node _T_8272 = or(_T_8232, _T_8271) @[RegMapper.scala 150:35] + node _T_8273 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_8275 = neq(_T_8273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8276 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_8277 = not(_T_8276) @[RegMapper.scala 136:45] + node _T_8279 = eq(_T_8277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8280 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_8282 = neq(_T_8280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8283 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_8284 = not(_T_8283) @[RegMapper.scala 138:44] + node _T_8286 = eq(_T_8284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8287 = and(_T_1958[110], _T_8275) @[RegMapper.scala 140:69] + node _T_8288 = and(_T_3086[110], _T_8282) @[RegMapper.scala 140:91] + node _T_8291 = and(_T_2146[110], _T_8279) @[RegMapper.scala 141:62] + node _T_8292 = and(_T_3274[110], _T_8286) @[RegMapper.scala 141:84] + node _T_8293 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_8297 = eq(_T_8275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8298 = or(UInt<1>("h01"), _T_8297) @[RegMapper.scala 142:31] + _T_2334[110] <= _T_8298 @[RegMapper.scala 142:18] + node _T_8300 = eq(_T_8279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8301 = or(UInt<1>("h01"), _T_8300) @[RegMapper.scala 143:31] + _T_2522[110] <= _T_8301 @[RegMapper.scala 143:18] + node _T_8303 = eq(_T_8282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8304 = or(UInt<1>("h01"), _T_8303) @[RegMapper.scala 144:31] + _T_2710[110] <= _T_8304 @[RegMapper.scala 144:18] + node _T_8306 = eq(_T_8286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8307 = or(UInt<1>("h01"), _T_8306) @[RegMapper.scala 145:31] + _T_2898[110] <= _T_8307 @[RegMapper.scala 145:18] + node _T_8308 = shl(UInt<8>("h083"), 0) @[RegMapper.scala 150:47] + node _T_8310 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_8311 = and(_T_8308, _T_8310) @[RegMapper.scala 150:55] + node _T_8312 = or(UInt<1>("h00"), _T_8311) @[RegMapper.scala 150:35] + node _T_8313 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_8315 = neq(_T_8313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8316 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_8317 = not(_T_8316) @[RegMapper.scala 136:45] + node _T_8319 = eq(_T_8317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8320 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_8322 = neq(_T_8320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8323 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_8324 = not(_T_8323) @[RegMapper.scala 138:44] + node _T_8326 = eq(_T_8324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8327 = and(_T_1958[111], _T_8315) @[RegMapper.scala 140:69] + node _T_8328 = and(_T_3086[111], _T_8322) @[RegMapper.scala 140:91] + node _T_8331 = and(_T_2146[111], _T_8319) @[RegMapper.scala 141:62] + node _T_8332 = and(_T_3274[111], _T_8326) @[RegMapper.scala 141:84] + node _T_8333 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_8337 = eq(_T_8315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8338 = or(UInt<1>("h01"), _T_8337) @[RegMapper.scala 142:31] + _T_2334[111] <= _T_8338 @[RegMapper.scala 142:18] + node _T_8340 = eq(_T_8319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8341 = or(UInt<1>("h01"), _T_8340) @[RegMapper.scala 143:31] + _T_2522[111] <= _T_8341 @[RegMapper.scala 143:18] + node _T_8343 = eq(_T_8322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8344 = or(UInt<1>("h01"), _T_8343) @[RegMapper.scala 144:31] + _T_2710[111] <= _T_8344 @[RegMapper.scala 144:18] + node _T_8346 = eq(_T_8326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8347 = or(UInt<1>("h01"), _T_8346) @[RegMapper.scala 145:31] + _T_2898[111] <= _T_8347 @[RegMapper.scala 145:18] + node _T_8348 = shl(UInt<6>("h034"), 8) @[RegMapper.scala 150:47] + node _T_8350 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_8351 = and(_T_8348, _T_8350) @[RegMapper.scala 150:55] + node _T_8352 = or(_T_8312, _T_8351) @[RegMapper.scala 150:35] + node _T_8353 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_8355 = neq(_T_8353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8356 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_8357 = not(_T_8356) @[RegMapper.scala 136:45] + node _T_8359 = eq(_T_8357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8360 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_8362 = neq(_T_8360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8363 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_8364 = not(_T_8363) @[RegMapper.scala 138:44] + node _T_8366 = eq(_T_8364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8367 = and(_T_1958[112], _T_8355) @[RegMapper.scala 140:69] + node _T_8368 = and(_T_3086[112], _T_8362) @[RegMapper.scala 140:91] + node _T_8371 = and(_T_2146[112], _T_8359) @[RegMapper.scala 141:62] + node _T_8372 = and(_T_3274[112], _T_8366) @[RegMapper.scala 141:84] + node _T_8373 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_8377 = eq(_T_8355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8378 = or(UInt<1>("h01"), _T_8377) @[RegMapper.scala 142:31] + _T_2334[112] <= _T_8378 @[RegMapper.scala 142:18] + node _T_8380 = eq(_T_8359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8381 = or(UInt<1>("h01"), _T_8380) @[RegMapper.scala 143:31] + _T_2522[112] <= _T_8381 @[RegMapper.scala 143:18] + node _T_8383 = eq(_T_8362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8384 = or(UInt<1>("h01"), _T_8383) @[RegMapper.scala 144:31] + _T_2710[112] <= _T_8384 @[RegMapper.scala 144:18] + node _T_8386 = eq(_T_8366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8387 = or(UInt<1>("h01"), _T_8386) @[RegMapper.scala 145:31] + _T_2898[112] <= _T_8387 @[RegMapper.scala 145:18] + node _T_8388 = shl(UInt<8>("h080"), 16) @[RegMapper.scala 150:47] + node _T_8390 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_8391 = and(_T_8388, _T_8390) @[RegMapper.scala 150:55] + node _T_8392 = or(_T_8352, _T_8391) @[RegMapper.scala 150:35] + node _T_8393 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_8395 = neq(_T_8393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8396 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_8397 = not(_T_8396) @[RegMapper.scala 136:45] + node _T_8399 = eq(_T_8397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8400 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_8402 = neq(_T_8400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8403 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_8404 = not(_T_8403) @[RegMapper.scala 138:44] + node _T_8406 = eq(_T_8404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8407 = and(_T_1958[113], _T_8395) @[RegMapper.scala 140:69] + node _T_8408 = and(_T_3086[113], _T_8402) @[RegMapper.scala 140:91] + node _T_8411 = and(_T_2146[113], _T_8399) @[RegMapper.scala 141:62] + node _T_8412 = and(_T_3274[113], _T_8406) @[RegMapper.scala 141:84] + node _T_8413 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_8417 = eq(_T_8395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8418 = or(UInt<1>("h01"), _T_8417) @[RegMapper.scala 142:31] + _T_2334[113] <= _T_8418 @[RegMapper.scala 142:18] + node _T_8420 = eq(_T_8399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8421 = or(UInt<1>("h01"), _T_8420) @[RegMapper.scala 143:31] + _T_2522[113] <= _T_8421 @[RegMapper.scala 143:18] + node _T_8423 = eq(_T_8402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8424 = or(UInt<1>("h01"), _T_8423) @[RegMapper.scala 144:31] + _T_2710[113] <= _T_8424 @[RegMapper.scala 144:18] + node _T_8426 = eq(_T_8406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8427 = or(UInt<1>("h01"), _T_8426) @[RegMapper.scala 145:31] + _T_2898[113] <= _T_8427 @[RegMapper.scala 145:18] + node _T_8428 = shl(UInt<7>("h043"), 24) @[RegMapper.scala 150:47] + node _T_8430 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_8431 = and(_T_8428, _T_8430) @[RegMapper.scala 150:55] + node _T_8432 = or(_T_8392, _T_8431) @[RegMapper.scala 150:35] + node _T_8433 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_8435 = neq(_T_8433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8436 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_8437 = not(_T_8436) @[RegMapper.scala 136:45] + node _T_8439 = eq(_T_8437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8440 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_8442 = neq(_T_8440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8443 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_8444 = not(_T_8443) @[RegMapper.scala 138:44] + node _T_8446 = eq(_T_8444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8447 = and(_T_1958[114], _T_8435) @[RegMapper.scala 140:69] + node _T_8448 = and(_T_3086[114], _T_8442) @[RegMapper.scala 140:91] + node _T_8451 = and(_T_2146[114], _T_8439) @[RegMapper.scala 141:62] + node _T_8452 = and(_T_3274[114], _T_8446) @[RegMapper.scala 141:84] + node _T_8453 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_8457 = eq(_T_8435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8458 = or(UInt<1>("h01"), _T_8457) @[RegMapper.scala 142:31] + _T_2334[114] <= _T_8458 @[RegMapper.scala 142:18] + node _T_8460 = eq(_T_8439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8461 = or(UInt<1>("h01"), _T_8460) @[RegMapper.scala 143:31] + _T_2522[114] <= _T_8461 @[RegMapper.scala 143:18] + node _T_8463 = eq(_T_8442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8464 = or(UInt<1>("h01"), _T_8463) @[RegMapper.scala 144:31] + _T_2710[114] <= _T_8464 @[RegMapper.scala 144:18] + node _T_8466 = eq(_T_8446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8467 = or(UInt<1>("h01"), _T_8466) @[RegMapper.scala 145:31] + _T_2898[114] <= _T_8467 @[RegMapper.scala 145:18] + node _T_8468 = shl(UInt<6>("h023"), 32) @[RegMapper.scala 150:47] + node _T_8470 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_8471 = and(_T_8468, _T_8470) @[RegMapper.scala 150:55] + node _T_8472 = or(_T_8432, _T_8471) @[RegMapper.scala 150:35] + node _T_8473 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_8475 = neq(_T_8473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8476 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_8477 = not(_T_8476) @[RegMapper.scala 136:45] + node _T_8479 = eq(_T_8477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8480 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_8482 = neq(_T_8480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8483 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_8484 = not(_T_8483) @[RegMapper.scala 138:44] + node _T_8486 = eq(_T_8484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8487 = and(_T_1958[115], _T_8475) @[RegMapper.scala 140:69] + node _T_8488 = and(_T_3086[115], _T_8482) @[RegMapper.scala 140:91] + node _T_8491 = and(_T_2146[115], _T_8479) @[RegMapper.scala 141:62] + node _T_8492 = and(_T_3274[115], _T_8486) @[RegMapper.scala 141:84] + node _T_8493 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_8497 = eq(_T_8475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8498 = or(UInt<1>("h01"), _T_8497) @[RegMapper.scala 142:31] + _T_2334[115] <= _T_8498 @[RegMapper.scala 142:18] + node _T_8500 = eq(_T_8479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8501 = or(UInt<1>("h01"), _T_8500) @[RegMapper.scala 143:31] + _T_2522[115] <= _T_8501 @[RegMapper.scala 143:18] + node _T_8503 = eq(_T_8482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8504 = or(UInt<1>("h01"), _T_8503) @[RegMapper.scala 144:31] + _T_2710[115] <= _T_8504 @[RegMapper.scala 144:18] + node _T_8506 = eq(_T_8486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8507 = or(UInt<1>("h01"), _T_8506) @[RegMapper.scala 145:31] + _T_2898[115] <= _T_8507 @[RegMapper.scala 145:18] + node _T_8508 = shl(UInt<6>("h02e"), 40) @[RegMapper.scala 150:47] + node _T_8510 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_8511 = and(_T_8508, _T_8510) @[RegMapper.scala 150:55] + node _T_8512 = or(_T_8472, _T_8511) @[RegMapper.scala 150:35] + node _T_8513 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_8515 = neq(_T_8513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8516 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_8517 = not(_T_8516) @[RegMapper.scala 136:45] + node _T_8519 = eq(_T_8517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8520 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_8522 = neq(_T_8520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8523 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_8524 = not(_T_8523) @[RegMapper.scala 138:44] + node _T_8526 = eq(_T_8524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8527 = and(_T_1958[116], _T_8515) @[RegMapper.scala 140:69] + node _T_8528 = and(_T_3086[116], _T_8522) @[RegMapper.scala 140:91] + node _T_8531 = and(_T_2146[116], _T_8519) @[RegMapper.scala 141:62] + node _T_8532 = and(_T_3274[116], _T_8526) @[RegMapper.scala 141:84] + node _T_8533 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_8537 = eq(_T_8515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8538 = or(UInt<1>("h01"), _T_8537) @[RegMapper.scala 142:31] + _T_2334[116] <= _T_8538 @[RegMapper.scala 142:18] + node _T_8540 = eq(_T_8519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8541 = or(UInt<1>("h01"), _T_8540) @[RegMapper.scala 143:31] + _T_2522[116] <= _T_8541 @[RegMapper.scala 143:18] + node _T_8543 = eq(_T_8522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8544 = or(UInt<1>("h01"), _T_8543) @[RegMapper.scala 144:31] + _T_2710[116] <= _T_8544 @[RegMapper.scala 144:18] + node _T_8546 = eq(_T_8526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8547 = or(UInt<1>("h01"), _T_8546) @[RegMapper.scala 145:31] + _T_2898[116] <= _T_8547 @[RegMapper.scala 145:18] + node _T_8548 = shl(UInt<8>("h080"), 48) @[RegMapper.scala 150:47] + node _T_8550 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_8551 = and(_T_8548, _T_8550) @[RegMapper.scala 150:55] + node _T_8552 = or(_T_8512, _T_8551) @[RegMapper.scala 150:35] + node _T_8553 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_8555 = neq(_T_8553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8556 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_8557 = not(_T_8556) @[RegMapper.scala 136:45] + node _T_8559 = eq(_T_8557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8560 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_8562 = neq(_T_8560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8563 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_8564 = not(_T_8563) @[RegMapper.scala 138:44] + node _T_8566 = eq(_T_8564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8567 = and(_T_1958[117], _T_8555) @[RegMapper.scala 140:69] + node _T_8568 = and(_T_3086[117], _T_8562) @[RegMapper.scala 140:91] + node _T_8571 = and(_T_2146[117], _T_8559) @[RegMapper.scala 141:62] + node _T_8572 = and(_T_3274[117], _T_8566) @[RegMapper.scala 141:84] + node _T_8573 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_8577 = eq(_T_8555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8578 = or(UInt<1>("h01"), _T_8577) @[RegMapper.scala 142:31] + _T_2334[117] <= _T_8578 @[RegMapper.scala 142:18] + node _T_8580 = eq(_T_8559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8581 = or(UInt<1>("h01"), _T_8580) @[RegMapper.scala 143:31] + _T_2522[117] <= _T_8581 @[RegMapper.scala 143:18] + node _T_8583 = eq(_T_8562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8584 = or(UInt<1>("h01"), _T_8583) @[RegMapper.scala 144:31] + _T_2710[117] <= _T_8584 @[RegMapper.scala 144:18] + node _T_8586 = eq(_T_8566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8587 = or(UInt<1>("h01"), _T_8586) @[RegMapper.scala 145:31] + _T_2898[117] <= _T_8587 @[RegMapper.scala 145:18] + node _T_8588 = shl(UInt<7>("h042"), 56) @[RegMapper.scala 150:47] + node _T_8590 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_8591 = and(_T_8588, _T_8590) @[RegMapper.scala 150:55] + node _T_8592 = or(_T_8552, _T_8591) @[RegMapper.scala 150:35] + node _T_8593 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_8595 = neq(_T_8593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8596 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_8597 = not(_T_8596) @[RegMapper.scala 136:45] + node _T_8599 = eq(_T_8597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8600 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_8602 = neq(_T_8600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8603 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_8604 = not(_T_8603) @[RegMapper.scala 138:44] + node _T_8606 = eq(_T_8604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8607 = and(_T_1958[118], _T_8595) @[RegMapper.scala 140:69] + node _T_8608 = and(_T_3086[118], _T_8602) @[RegMapper.scala 140:91] + node _T_8611 = and(_T_2146[118], _T_8599) @[RegMapper.scala 141:62] + node _T_8612 = and(_T_3274[118], _T_8606) @[RegMapper.scala 141:84] + node _T_8613 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_8612 : @[RegField.scala 70:88] + ramMem[16] <= _T_8613 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8617 = eq(_T_8595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8618 = or(UInt<1>("h01"), _T_8617) @[RegMapper.scala 142:31] + _T_2334[118] <= _T_8618 @[RegMapper.scala 142:18] + node _T_8620 = eq(_T_8599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8621 = or(UInt<1>("h01"), _T_8620) @[RegMapper.scala 143:31] + _T_2522[118] <= _T_8621 @[RegMapper.scala 143:18] + node _T_8623 = eq(_T_8602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8624 = or(UInt<1>("h01"), _T_8623) @[RegMapper.scala 144:31] + _T_2710[118] <= _T_8624 @[RegMapper.scala 144:18] + node _T_8626 = eq(_T_8606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8627 = or(UInt<1>("h01"), _T_8626) @[RegMapper.scala 145:31] + _T_2898[118] <= _T_8627 @[RegMapper.scala 145:18] + node _T_8628 = shl(ramMem[16], 0) @[RegMapper.scala 150:47] + node _T_8630 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_8631 = and(_T_8628, _T_8630) @[RegMapper.scala 150:55] + node _T_8632 = or(UInt<1>("h00"), _T_8631) @[RegMapper.scala 150:35] + node _T_8633 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_8635 = neq(_T_8633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8636 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_8637 = not(_T_8636) @[RegMapper.scala 136:45] + node _T_8639 = eq(_T_8637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8640 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_8642 = neq(_T_8640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8643 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_8644 = not(_T_8643) @[RegMapper.scala 138:44] + node _T_8646 = eq(_T_8644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8647 = and(_T_1958[119], _T_8635) @[RegMapper.scala 140:69] + node _T_8648 = and(_T_3086[119], _T_8642) @[RegMapper.scala 140:91] + node _T_8651 = and(_T_2146[119], _T_8639) @[RegMapper.scala 141:62] + node _T_8652 = and(_T_3274[119], _T_8646) @[RegMapper.scala 141:84] + node _T_8653 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_8652 : @[RegField.scala 70:88] + ramMem[17] <= _T_8653 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8657 = eq(_T_8635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8658 = or(UInt<1>("h01"), _T_8657) @[RegMapper.scala 142:31] + _T_2334[119] <= _T_8658 @[RegMapper.scala 142:18] + node _T_8660 = eq(_T_8639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8661 = or(UInt<1>("h01"), _T_8660) @[RegMapper.scala 143:31] + _T_2522[119] <= _T_8661 @[RegMapper.scala 143:18] + node _T_8663 = eq(_T_8642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8664 = or(UInt<1>("h01"), _T_8663) @[RegMapper.scala 144:31] + _T_2710[119] <= _T_8664 @[RegMapper.scala 144:18] + node _T_8666 = eq(_T_8646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8667 = or(UInt<1>("h01"), _T_8666) @[RegMapper.scala 145:31] + _T_2898[119] <= _T_8667 @[RegMapper.scala 145:18] + node _T_8668 = shl(ramMem[17], 8) @[RegMapper.scala 150:47] + node _T_8670 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_8671 = and(_T_8668, _T_8670) @[RegMapper.scala 150:55] + node _T_8672 = or(_T_8632, _T_8671) @[RegMapper.scala 150:35] + node _T_8673 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_8675 = neq(_T_8673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8676 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_8677 = not(_T_8676) @[RegMapper.scala 136:45] + node _T_8679 = eq(_T_8677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8680 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_8682 = neq(_T_8680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8683 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_8684 = not(_T_8683) @[RegMapper.scala 138:44] + node _T_8686 = eq(_T_8684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8687 = and(_T_1958[120], _T_8675) @[RegMapper.scala 140:69] + node _T_8688 = and(_T_3086[120], _T_8682) @[RegMapper.scala 140:91] + node _T_8691 = and(_T_2146[120], _T_8679) @[RegMapper.scala 141:62] + node _T_8692 = and(_T_3274[120], _T_8686) @[RegMapper.scala 141:84] + node _T_8693 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_8692 : @[RegField.scala 70:88] + ramMem[18] <= _T_8693 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8697 = eq(_T_8675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8698 = or(UInt<1>("h01"), _T_8697) @[RegMapper.scala 142:31] + _T_2334[120] <= _T_8698 @[RegMapper.scala 142:18] + node _T_8700 = eq(_T_8679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8701 = or(UInt<1>("h01"), _T_8700) @[RegMapper.scala 143:31] + _T_2522[120] <= _T_8701 @[RegMapper.scala 143:18] + node _T_8703 = eq(_T_8682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8704 = or(UInt<1>("h01"), _T_8703) @[RegMapper.scala 144:31] + _T_2710[120] <= _T_8704 @[RegMapper.scala 144:18] + node _T_8706 = eq(_T_8686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8707 = or(UInt<1>("h01"), _T_8706) @[RegMapper.scala 145:31] + _T_2898[120] <= _T_8707 @[RegMapper.scala 145:18] + node _T_8708 = shl(ramMem[18], 16) @[RegMapper.scala 150:47] + node _T_8710 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_8711 = and(_T_8708, _T_8710) @[RegMapper.scala 150:55] + node _T_8712 = or(_T_8672, _T_8711) @[RegMapper.scala 150:35] + node _T_8713 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_8715 = neq(_T_8713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8716 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_8717 = not(_T_8716) @[RegMapper.scala 136:45] + node _T_8719 = eq(_T_8717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8720 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_8722 = neq(_T_8720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8723 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_8724 = not(_T_8723) @[RegMapper.scala 138:44] + node _T_8726 = eq(_T_8724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8727 = and(_T_1958[121], _T_8715) @[RegMapper.scala 140:69] + node _T_8728 = and(_T_3086[121], _T_8722) @[RegMapper.scala 140:91] + node _T_8731 = and(_T_2146[121], _T_8719) @[RegMapper.scala 141:62] + node _T_8732 = and(_T_3274[121], _T_8726) @[RegMapper.scala 141:84] + node _T_8733 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_8732 : @[RegField.scala 70:88] + ramMem[19] <= _T_8733 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8737 = eq(_T_8715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8738 = or(UInt<1>("h01"), _T_8737) @[RegMapper.scala 142:31] + _T_2334[121] <= _T_8738 @[RegMapper.scala 142:18] + node _T_8740 = eq(_T_8719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8741 = or(UInt<1>("h01"), _T_8740) @[RegMapper.scala 143:31] + _T_2522[121] <= _T_8741 @[RegMapper.scala 143:18] + node _T_8743 = eq(_T_8722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8744 = or(UInt<1>("h01"), _T_8743) @[RegMapper.scala 144:31] + _T_2710[121] <= _T_8744 @[RegMapper.scala 144:18] + node _T_8746 = eq(_T_8726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8747 = or(UInt<1>("h01"), _T_8746) @[RegMapper.scala 145:31] + _T_2898[121] <= _T_8747 @[RegMapper.scala 145:18] + node _T_8748 = shl(ramMem[19], 24) @[RegMapper.scala 150:47] + node _T_8750 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_8751 = and(_T_8748, _T_8750) @[RegMapper.scala 150:55] + node _T_8752 = or(_T_8712, _T_8751) @[RegMapper.scala 150:35] + node _T_8753 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_8755 = neq(_T_8753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8756 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_8757 = not(_T_8756) @[RegMapper.scala 136:45] + node _T_8759 = eq(_T_8757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8760 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_8762 = neq(_T_8760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8763 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_8764 = not(_T_8763) @[RegMapper.scala 138:44] + node _T_8766 = eq(_T_8764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8767 = and(_T_1958[122], _T_8755) @[RegMapper.scala 140:69] + node _T_8768 = and(_T_3086[122], _T_8762) @[RegMapper.scala 140:91] + node _T_8771 = and(_T_2146[122], _T_8759) @[RegMapper.scala 141:62] + node _T_8772 = and(_T_3274[122], _T_8766) @[RegMapper.scala 141:84] + node _T_8773 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_8772 : @[RegField.scala 70:88] + ramMem[20] <= _T_8773 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8777 = eq(_T_8755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8778 = or(UInt<1>("h01"), _T_8777) @[RegMapper.scala 142:31] + _T_2334[122] <= _T_8778 @[RegMapper.scala 142:18] + node _T_8780 = eq(_T_8759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8781 = or(UInt<1>("h01"), _T_8780) @[RegMapper.scala 143:31] + _T_2522[122] <= _T_8781 @[RegMapper.scala 143:18] + node _T_8783 = eq(_T_8762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8784 = or(UInt<1>("h01"), _T_8783) @[RegMapper.scala 144:31] + _T_2710[122] <= _T_8784 @[RegMapper.scala 144:18] + node _T_8786 = eq(_T_8766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8787 = or(UInt<1>("h01"), _T_8786) @[RegMapper.scala 145:31] + _T_2898[122] <= _T_8787 @[RegMapper.scala 145:18] + node _T_8788 = shl(ramMem[20], 32) @[RegMapper.scala 150:47] + node _T_8790 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_8791 = and(_T_8788, _T_8790) @[RegMapper.scala 150:55] + node _T_8792 = or(_T_8752, _T_8791) @[RegMapper.scala 150:35] + node _T_8793 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_8795 = neq(_T_8793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8796 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_8797 = not(_T_8796) @[RegMapper.scala 136:45] + node _T_8799 = eq(_T_8797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8800 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_8802 = neq(_T_8800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8803 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_8804 = not(_T_8803) @[RegMapper.scala 138:44] + node _T_8806 = eq(_T_8804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8807 = and(_T_1958[123], _T_8795) @[RegMapper.scala 140:69] + node _T_8808 = and(_T_3086[123], _T_8802) @[RegMapper.scala 140:91] + node _T_8811 = and(_T_2146[123], _T_8799) @[RegMapper.scala 141:62] + node _T_8812 = and(_T_3274[123], _T_8806) @[RegMapper.scala 141:84] + node _T_8813 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_8812 : @[RegField.scala 70:88] + ramMem[21] <= _T_8813 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8817 = eq(_T_8795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8818 = or(UInt<1>("h01"), _T_8817) @[RegMapper.scala 142:31] + _T_2334[123] <= _T_8818 @[RegMapper.scala 142:18] + node _T_8820 = eq(_T_8799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8821 = or(UInt<1>("h01"), _T_8820) @[RegMapper.scala 143:31] + _T_2522[123] <= _T_8821 @[RegMapper.scala 143:18] + node _T_8823 = eq(_T_8802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8824 = or(UInt<1>("h01"), _T_8823) @[RegMapper.scala 144:31] + _T_2710[123] <= _T_8824 @[RegMapper.scala 144:18] + node _T_8826 = eq(_T_8806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8827 = or(UInt<1>("h01"), _T_8826) @[RegMapper.scala 145:31] + _T_2898[123] <= _T_8827 @[RegMapper.scala 145:18] + node _T_8828 = shl(ramMem[21], 40) @[RegMapper.scala 150:47] + node _T_8830 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_8831 = and(_T_8828, _T_8830) @[RegMapper.scala 150:55] + node _T_8832 = or(_T_8792, _T_8831) @[RegMapper.scala 150:35] + node _T_8833 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_8835 = neq(_T_8833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8836 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_8837 = not(_T_8836) @[RegMapper.scala 136:45] + node _T_8839 = eq(_T_8837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8840 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_8842 = neq(_T_8840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8843 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_8844 = not(_T_8843) @[RegMapper.scala 138:44] + node _T_8846 = eq(_T_8844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8847 = and(_T_1958[124], _T_8835) @[RegMapper.scala 140:69] + node _T_8848 = and(_T_3086[124], _T_8842) @[RegMapper.scala 140:91] + node _T_8851 = and(_T_2146[124], _T_8839) @[RegMapper.scala 141:62] + node _T_8852 = and(_T_3274[124], _T_8846) @[RegMapper.scala 141:84] + node _T_8853 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_8852 : @[RegField.scala 70:88] + ramMem[22] <= _T_8853 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8857 = eq(_T_8835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8858 = or(UInt<1>("h01"), _T_8857) @[RegMapper.scala 142:31] + _T_2334[124] <= _T_8858 @[RegMapper.scala 142:18] + node _T_8860 = eq(_T_8839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8861 = or(UInt<1>("h01"), _T_8860) @[RegMapper.scala 143:31] + _T_2522[124] <= _T_8861 @[RegMapper.scala 143:18] + node _T_8863 = eq(_T_8842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8864 = or(UInt<1>("h01"), _T_8863) @[RegMapper.scala 144:31] + _T_2710[124] <= _T_8864 @[RegMapper.scala 144:18] + node _T_8866 = eq(_T_8846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8867 = or(UInt<1>("h01"), _T_8866) @[RegMapper.scala 145:31] + _T_2898[124] <= _T_8867 @[RegMapper.scala 145:18] + node _T_8868 = shl(ramMem[22], 48) @[RegMapper.scala 150:47] + node _T_8870 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_8871 = and(_T_8868, _T_8870) @[RegMapper.scala 150:55] + node _T_8872 = or(_T_8832, _T_8871) @[RegMapper.scala 150:35] + node _T_8873 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_8875 = neq(_T_8873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8876 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_8877 = not(_T_8876) @[RegMapper.scala 136:45] + node _T_8879 = eq(_T_8877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8880 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_8882 = neq(_T_8880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8883 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_8884 = not(_T_8883) @[RegMapper.scala 138:44] + node _T_8886 = eq(_T_8884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8887 = and(_T_1958[125], _T_8875) @[RegMapper.scala 140:69] + node _T_8888 = and(_T_3086[125], _T_8882) @[RegMapper.scala 140:91] + node _T_8891 = and(_T_2146[125], _T_8879) @[RegMapper.scala 141:62] + node _T_8892 = and(_T_3274[125], _T_8886) @[RegMapper.scala 141:84] + node _T_8893 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_8892 : @[RegField.scala 70:88] + ramMem[23] <= _T_8893 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8897 = eq(_T_8875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8898 = or(UInt<1>("h01"), _T_8897) @[RegMapper.scala 142:31] + _T_2334[125] <= _T_8898 @[RegMapper.scala 142:18] + node _T_8900 = eq(_T_8879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8901 = or(UInt<1>("h01"), _T_8900) @[RegMapper.scala 143:31] + _T_2522[125] <= _T_8901 @[RegMapper.scala 143:18] + node _T_8903 = eq(_T_8882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8904 = or(UInt<1>("h01"), _T_8903) @[RegMapper.scala 144:31] + _T_2710[125] <= _T_8904 @[RegMapper.scala 144:18] + node _T_8906 = eq(_T_8886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8907 = or(UInt<1>("h01"), _T_8906) @[RegMapper.scala 145:31] + _T_2898[125] <= _T_8907 @[RegMapper.scala 145:18] + node _T_8908 = shl(ramMem[23], 56) @[RegMapper.scala 150:47] + node _T_8910 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_8911 = and(_T_8908, _T_8910) @[RegMapper.scala 150:55] + node _T_8912 = or(_T_8872, _T_8911) @[RegMapper.scala 150:35] + node _T_8913 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_8915 = neq(_T_8913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8916 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_8917 = not(_T_8916) @[RegMapper.scala 136:45] + node _T_8919 = eq(_T_8917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8920 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_8922 = neq(_T_8920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8923 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_8924 = not(_T_8923) @[RegMapper.scala 138:44] + node _T_8926 = eq(_T_8924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8927 = and(_T_1958[126], _T_8915) @[RegMapper.scala 140:69] + node _T_8928 = and(_T_3086[126], _T_8922) @[RegMapper.scala 140:91] + node _T_8931 = and(_T_2146[126], _T_8919) @[RegMapper.scala 141:62] + node _T_8932 = and(_T_3274[126], _T_8926) @[RegMapper.scala 141:84] + node _T_8933 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_8932 : @[RegField.scala 70:88] + ramMem[56] <= _T_8933 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8937 = eq(_T_8915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8938 = or(UInt<1>("h01"), _T_8937) @[RegMapper.scala 142:31] + _T_2334[126] <= _T_8938 @[RegMapper.scala 142:18] + node _T_8940 = eq(_T_8919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8941 = or(UInt<1>("h01"), _T_8940) @[RegMapper.scala 143:31] + _T_2522[126] <= _T_8941 @[RegMapper.scala 143:18] + node _T_8943 = eq(_T_8922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8944 = or(UInt<1>("h01"), _T_8943) @[RegMapper.scala 144:31] + _T_2710[126] <= _T_8944 @[RegMapper.scala 144:18] + node _T_8946 = eq(_T_8926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8947 = or(UInt<1>("h01"), _T_8946) @[RegMapper.scala 145:31] + _T_2898[126] <= _T_8947 @[RegMapper.scala 145:18] + node _T_8948 = shl(ramMem[56], 0) @[RegMapper.scala 150:47] + node _T_8950 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_8951 = and(_T_8948, _T_8950) @[RegMapper.scala 150:55] + node _T_8952 = or(UInt<1>("h00"), _T_8951) @[RegMapper.scala 150:35] + node _T_8953 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_8955 = neq(_T_8953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8956 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_8957 = not(_T_8956) @[RegMapper.scala 136:45] + node _T_8959 = eq(_T_8957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_8960 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_8962 = neq(_T_8960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_8963 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_8964 = not(_T_8963) @[RegMapper.scala 138:44] + node _T_8966 = eq(_T_8964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_8967 = and(_T_1958[127], _T_8955) @[RegMapper.scala 140:69] + node _T_8968 = and(_T_3086[127], _T_8962) @[RegMapper.scala 140:91] + node _T_8971 = and(_T_2146[127], _T_8959) @[RegMapper.scala 141:62] + node _T_8972 = and(_T_3274[127], _T_8966) @[RegMapper.scala 141:84] + node _T_8973 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_8972 : @[RegField.scala 70:88] + ramMem[57] <= _T_8973 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_8977 = eq(_T_8955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_8978 = or(UInt<1>("h01"), _T_8977) @[RegMapper.scala 142:31] + _T_2334[127] <= _T_8978 @[RegMapper.scala 142:18] + node _T_8980 = eq(_T_8959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_8981 = or(UInt<1>("h01"), _T_8980) @[RegMapper.scala 143:31] + _T_2522[127] <= _T_8981 @[RegMapper.scala 143:18] + node _T_8983 = eq(_T_8962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_8984 = or(UInt<1>("h01"), _T_8983) @[RegMapper.scala 144:31] + _T_2710[127] <= _T_8984 @[RegMapper.scala 144:18] + node _T_8986 = eq(_T_8966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_8987 = or(UInt<1>("h01"), _T_8986) @[RegMapper.scala 145:31] + _T_2898[127] <= _T_8987 @[RegMapper.scala 145:18] + node _T_8988 = shl(ramMem[57], 8) @[RegMapper.scala 150:47] + node _T_8990 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_8991 = and(_T_8988, _T_8990) @[RegMapper.scala 150:55] + node _T_8992 = or(_T_8952, _T_8991) @[RegMapper.scala 150:35] + node _T_8993 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_8995 = neq(_T_8993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_8996 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_8997 = not(_T_8996) @[RegMapper.scala 136:45] + node _T_8999 = eq(_T_8997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9000 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_9002 = neq(_T_9000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9003 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_9004 = not(_T_9003) @[RegMapper.scala 138:44] + node _T_9006 = eq(_T_9004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9007 = and(_T_1958[128], _T_8995) @[RegMapper.scala 140:69] + node _T_9008 = and(_T_3086[128], _T_9002) @[RegMapper.scala 140:91] + node _T_9011 = and(_T_2146[128], _T_8999) @[RegMapper.scala 141:62] + node _T_9012 = and(_T_3274[128], _T_9006) @[RegMapper.scala 141:84] + node _T_9013 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_9012 : @[RegField.scala 70:88] + ramMem[58] <= _T_9013 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9017 = eq(_T_8995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9018 = or(UInt<1>("h01"), _T_9017) @[RegMapper.scala 142:31] + _T_2334[128] <= _T_9018 @[RegMapper.scala 142:18] + node _T_9020 = eq(_T_8999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9021 = or(UInt<1>("h01"), _T_9020) @[RegMapper.scala 143:31] + _T_2522[128] <= _T_9021 @[RegMapper.scala 143:18] + node _T_9023 = eq(_T_9002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9024 = or(UInt<1>("h01"), _T_9023) @[RegMapper.scala 144:31] + _T_2710[128] <= _T_9024 @[RegMapper.scala 144:18] + node _T_9026 = eq(_T_9006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9027 = or(UInt<1>("h01"), _T_9026) @[RegMapper.scala 145:31] + _T_2898[128] <= _T_9027 @[RegMapper.scala 145:18] + node _T_9028 = shl(ramMem[58], 16) @[RegMapper.scala 150:47] + node _T_9030 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_9031 = and(_T_9028, _T_9030) @[RegMapper.scala 150:55] + node _T_9032 = or(_T_8992, _T_9031) @[RegMapper.scala 150:35] + node _T_9033 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_9035 = neq(_T_9033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9036 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_9037 = not(_T_9036) @[RegMapper.scala 136:45] + node _T_9039 = eq(_T_9037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9040 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_9042 = neq(_T_9040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9043 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_9044 = not(_T_9043) @[RegMapper.scala 138:44] + node _T_9046 = eq(_T_9044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9047 = and(_T_1958[129], _T_9035) @[RegMapper.scala 140:69] + node _T_9048 = and(_T_3086[129], _T_9042) @[RegMapper.scala 140:91] + node _T_9051 = and(_T_2146[129], _T_9039) @[RegMapper.scala 141:62] + node _T_9052 = and(_T_3274[129], _T_9046) @[RegMapper.scala 141:84] + node _T_9053 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_9052 : @[RegField.scala 70:88] + ramMem[59] <= _T_9053 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9057 = eq(_T_9035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9058 = or(UInt<1>("h01"), _T_9057) @[RegMapper.scala 142:31] + _T_2334[129] <= _T_9058 @[RegMapper.scala 142:18] + node _T_9060 = eq(_T_9039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9061 = or(UInt<1>("h01"), _T_9060) @[RegMapper.scala 143:31] + _T_2522[129] <= _T_9061 @[RegMapper.scala 143:18] + node _T_9063 = eq(_T_9042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9064 = or(UInt<1>("h01"), _T_9063) @[RegMapper.scala 144:31] + _T_2710[129] <= _T_9064 @[RegMapper.scala 144:18] + node _T_9066 = eq(_T_9046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9067 = or(UInt<1>("h01"), _T_9066) @[RegMapper.scala 145:31] + _T_2898[129] <= _T_9067 @[RegMapper.scala 145:18] + node _T_9068 = shl(ramMem[59], 24) @[RegMapper.scala 150:47] + node _T_9070 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_9071 = and(_T_9068, _T_9070) @[RegMapper.scala 150:55] + node _T_9072 = or(_T_9032, _T_9071) @[RegMapper.scala 150:35] + node _T_9073 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_9075 = neq(_T_9073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9076 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_9077 = not(_T_9076) @[RegMapper.scala 136:45] + node _T_9079 = eq(_T_9077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9080 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_9082 = neq(_T_9080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9083 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_9084 = not(_T_9083) @[RegMapper.scala 138:44] + node _T_9086 = eq(_T_9084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9087 = and(_T_1958[130], _T_9075) @[RegMapper.scala 140:69] + node _T_9088 = and(_T_3086[130], _T_9082) @[RegMapper.scala 140:91] + node _T_9091 = and(_T_2146[130], _T_9079) @[RegMapper.scala 141:62] + node _T_9092 = and(_T_3274[130], _T_9086) @[RegMapper.scala 141:84] + node _T_9093 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_9092 : @[RegField.scala 70:88] + ramMem[60] <= _T_9093 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9097 = eq(_T_9075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9098 = or(UInt<1>("h01"), _T_9097) @[RegMapper.scala 142:31] + _T_2334[130] <= _T_9098 @[RegMapper.scala 142:18] + node _T_9100 = eq(_T_9079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9101 = or(UInt<1>("h01"), _T_9100) @[RegMapper.scala 143:31] + _T_2522[130] <= _T_9101 @[RegMapper.scala 143:18] + node _T_9103 = eq(_T_9082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9104 = or(UInt<1>("h01"), _T_9103) @[RegMapper.scala 144:31] + _T_2710[130] <= _T_9104 @[RegMapper.scala 144:18] + node _T_9106 = eq(_T_9086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9107 = or(UInt<1>("h01"), _T_9106) @[RegMapper.scala 145:31] + _T_2898[130] <= _T_9107 @[RegMapper.scala 145:18] + node _T_9108 = shl(ramMem[60], 32) @[RegMapper.scala 150:47] + node _T_9110 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_9111 = and(_T_9108, _T_9110) @[RegMapper.scala 150:55] + node _T_9112 = or(_T_9072, _T_9111) @[RegMapper.scala 150:35] + node _T_9113 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_9115 = neq(_T_9113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9116 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_9117 = not(_T_9116) @[RegMapper.scala 136:45] + node _T_9119 = eq(_T_9117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9120 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_9122 = neq(_T_9120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9123 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_9124 = not(_T_9123) @[RegMapper.scala 138:44] + node _T_9126 = eq(_T_9124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9127 = and(_T_1958[131], _T_9115) @[RegMapper.scala 140:69] + node _T_9128 = and(_T_3086[131], _T_9122) @[RegMapper.scala 140:91] + node _T_9131 = and(_T_2146[131], _T_9119) @[RegMapper.scala 141:62] + node _T_9132 = and(_T_3274[131], _T_9126) @[RegMapper.scala 141:84] + node _T_9133 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_9132 : @[RegField.scala 70:88] + ramMem[61] <= _T_9133 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9137 = eq(_T_9115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9138 = or(UInt<1>("h01"), _T_9137) @[RegMapper.scala 142:31] + _T_2334[131] <= _T_9138 @[RegMapper.scala 142:18] + node _T_9140 = eq(_T_9119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9141 = or(UInt<1>("h01"), _T_9140) @[RegMapper.scala 143:31] + _T_2522[131] <= _T_9141 @[RegMapper.scala 143:18] + node _T_9143 = eq(_T_9122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9144 = or(UInt<1>("h01"), _T_9143) @[RegMapper.scala 144:31] + _T_2710[131] <= _T_9144 @[RegMapper.scala 144:18] + node _T_9146 = eq(_T_9126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9147 = or(UInt<1>("h01"), _T_9146) @[RegMapper.scala 145:31] + _T_2898[131] <= _T_9147 @[RegMapper.scala 145:18] + node _T_9148 = shl(ramMem[61], 40) @[RegMapper.scala 150:47] + node _T_9150 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_9151 = and(_T_9148, _T_9150) @[RegMapper.scala 150:55] + node _T_9152 = or(_T_9112, _T_9151) @[RegMapper.scala 150:35] + node _T_9153 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_9155 = neq(_T_9153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9156 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_9157 = not(_T_9156) @[RegMapper.scala 136:45] + node _T_9159 = eq(_T_9157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9160 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_9162 = neq(_T_9160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9163 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_9164 = not(_T_9163) @[RegMapper.scala 138:44] + node _T_9166 = eq(_T_9164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9167 = and(_T_1958[132], _T_9155) @[RegMapper.scala 140:69] + node _T_9168 = and(_T_3086[132], _T_9162) @[RegMapper.scala 140:91] + node _T_9171 = and(_T_2146[132], _T_9159) @[RegMapper.scala 141:62] + node _T_9172 = and(_T_3274[132], _T_9166) @[RegMapper.scala 141:84] + node _T_9173 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_9172 : @[RegField.scala 70:88] + ramMem[62] <= _T_9173 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9177 = eq(_T_9155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9178 = or(UInt<1>("h01"), _T_9177) @[RegMapper.scala 142:31] + _T_2334[132] <= _T_9178 @[RegMapper.scala 142:18] + node _T_9180 = eq(_T_9159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9181 = or(UInt<1>("h01"), _T_9180) @[RegMapper.scala 143:31] + _T_2522[132] <= _T_9181 @[RegMapper.scala 143:18] + node _T_9183 = eq(_T_9162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9184 = or(UInt<1>("h01"), _T_9183) @[RegMapper.scala 144:31] + _T_2710[132] <= _T_9184 @[RegMapper.scala 144:18] + node _T_9186 = eq(_T_9166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9187 = or(UInt<1>("h01"), _T_9186) @[RegMapper.scala 145:31] + _T_2898[132] <= _T_9187 @[RegMapper.scala 145:18] + node _T_9188 = shl(ramMem[62], 48) @[RegMapper.scala 150:47] + node _T_9190 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_9191 = and(_T_9188, _T_9190) @[RegMapper.scala 150:55] + node _T_9192 = or(_T_9152, _T_9191) @[RegMapper.scala 150:35] + node _T_9193 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_9195 = neq(_T_9193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9196 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_9197 = not(_T_9196) @[RegMapper.scala 136:45] + node _T_9199 = eq(_T_9197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9200 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_9202 = neq(_T_9200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9203 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_9204 = not(_T_9203) @[RegMapper.scala 138:44] + node _T_9206 = eq(_T_9204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9207 = and(_T_1958[133], _T_9195) @[RegMapper.scala 140:69] + node _T_9208 = and(_T_3086[133], _T_9202) @[RegMapper.scala 140:91] + node _T_9211 = and(_T_2146[133], _T_9199) @[RegMapper.scala 141:62] + node _T_9212 = and(_T_3274[133], _T_9206) @[RegMapper.scala 141:84] + node _T_9213 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_9212 : @[RegField.scala 70:88] + ramMem[63] <= _T_9213 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_9217 = eq(_T_9195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9218 = or(UInt<1>("h01"), _T_9217) @[RegMapper.scala 142:31] + _T_2334[133] <= _T_9218 @[RegMapper.scala 142:18] + node _T_9220 = eq(_T_9199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9221 = or(UInt<1>("h01"), _T_9220) @[RegMapper.scala 143:31] + _T_2522[133] <= _T_9221 @[RegMapper.scala 143:18] + node _T_9223 = eq(_T_9202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9224 = or(UInt<1>("h01"), _T_9223) @[RegMapper.scala 144:31] + _T_2710[133] <= _T_9224 @[RegMapper.scala 144:18] + node _T_9226 = eq(_T_9206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9227 = or(UInt<1>("h01"), _T_9226) @[RegMapper.scala 145:31] + _T_2898[133] <= _T_9227 @[RegMapper.scala 145:18] + node _T_9228 = shl(ramMem[63], 56) @[RegMapper.scala 150:47] + node _T_9230 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_9231 = and(_T_9228, _T_9230) @[RegMapper.scala 150:55] + node _T_9232 = or(_T_9192, _T_9231) @[RegMapper.scala 150:35] + node _T_9233 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_9235 = neq(_T_9233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9236 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_9237 = not(_T_9236) @[RegMapper.scala 136:45] + node _T_9239 = eq(_T_9237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9240 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_9242 = neq(_T_9240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9243 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_9244 = not(_T_9243) @[RegMapper.scala 138:44] + node _T_9246 = eq(_T_9244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9247 = and(_T_1958[134], _T_9235) @[RegMapper.scala 140:69] + node _T_9248 = and(_T_3086[134], _T_9242) @[RegMapper.scala 140:91] + node _T_9251 = and(_T_2146[134], _T_9239) @[RegMapper.scala 141:62] + node _T_9252 = and(_T_3274[134], _T_9246) @[RegMapper.scala 141:84] + node _T_9253 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_9257 = eq(_T_9235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9258 = or(UInt<1>("h01"), _T_9257) @[RegMapper.scala 142:31] + _T_2334[134] <= _T_9258 @[RegMapper.scala 142:18] + node _T_9260 = eq(_T_9239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9261 = or(UInt<1>("h01"), _T_9260) @[RegMapper.scala 143:31] + _T_2522[134] <= _T_9261 @[RegMapper.scala 143:18] + node _T_9263 = eq(_T_9242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9264 = or(UInt<1>("h01"), _T_9263) @[RegMapper.scala 144:31] + _T_2710[134] <= _T_9264 @[RegMapper.scala 144:18] + node _T_9266 = eq(_T_9246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9267 = or(UInt<1>("h01"), _T_9266) @[RegMapper.scala 145:31] + _T_2898[134] <= _T_9267 @[RegMapper.scala 145:18] + node _T_9268 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_9270 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_9271 = and(_T_9268, _T_9270) @[RegMapper.scala 150:55] + node _T_9272 = or(UInt<1>("h00"), _T_9271) @[RegMapper.scala 150:35] + node _T_9273 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_9275 = neq(_T_9273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9276 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_9277 = not(_T_9276) @[RegMapper.scala 136:45] + node _T_9279 = eq(_T_9277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9280 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_9282 = neq(_T_9280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9283 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_9284 = not(_T_9283) @[RegMapper.scala 138:44] + node _T_9286 = eq(_T_9284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9287 = and(_T_1958[135], _T_9275) @[RegMapper.scala 140:69] + node _T_9288 = and(_T_3086[135], _T_9282) @[RegMapper.scala 140:91] + node _T_9291 = and(_T_2146[135], _T_9279) @[RegMapper.scala 141:62] + node _T_9292 = and(_T_3274[135], _T_9286) @[RegMapper.scala 141:84] + node _T_9293 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_9297 = eq(_T_9275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9298 = or(UInt<1>("h01"), _T_9297) @[RegMapper.scala 142:31] + _T_2334[135] <= _T_9298 @[RegMapper.scala 142:18] + node _T_9300 = eq(_T_9279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9301 = or(UInt<1>("h01"), _T_9300) @[RegMapper.scala 143:31] + _T_2522[135] <= _T_9301 @[RegMapper.scala 143:18] + node _T_9303 = eq(_T_9282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9304 = or(UInt<1>("h01"), _T_9303) @[RegMapper.scala 144:31] + _T_2710[135] <= _T_9304 @[RegMapper.scala 144:18] + node _T_9306 = eq(_T_9286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9307 = or(UInt<1>("h01"), _T_9306) @[RegMapper.scala 145:31] + _T_2898[135] <= _T_9307 @[RegMapper.scala 145:18] + node _T_9308 = shl(UInt<6>("h024"), 8) @[RegMapper.scala 150:47] + node _T_9310 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_9311 = and(_T_9308, _T_9310) @[RegMapper.scala 150:55] + node _T_9312 = or(_T_9272, _T_9311) @[RegMapper.scala 150:35] + node _T_9313 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_9315 = neq(_T_9313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9316 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_9317 = not(_T_9316) @[RegMapper.scala 136:45] + node _T_9319 = eq(_T_9317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9320 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_9322 = neq(_T_9320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9323 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_9324 = not(_T_9323) @[RegMapper.scala 138:44] + node _T_9326 = eq(_T_9324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9327 = and(_T_1958[136], _T_9315) @[RegMapper.scala 140:69] + node _T_9328 = and(_T_3086[136], _T_9322) @[RegMapper.scala 140:91] + node _T_9331 = and(_T_2146[136], _T_9319) @[RegMapper.scala 141:62] + node _T_9332 = and(_T_3274[136], _T_9326) @[RegMapper.scala 141:84] + node _T_9333 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_9337 = eq(_T_9315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9338 = or(UInt<1>("h01"), _T_9337) @[RegMapper.scala 142:31] + _T_2334[136] <= _T_9338 @[RegMapper.scala 142:18] + node _T_9340 = eq(_T_9319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9341 = or(UInt<1>("h01"), _T_9340) @[RegMapper.scala 143:31] + _T_2522[136] <= _T_9341 @[RegMapper.scala 143:18] + node _T_9343 = eq(_T_9322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9344 = or(UInt<1>("h01"), _T_9343) @[RegMapper.scala 144:31] + _T_2710[136] <= _T_9344 @[RegMapper.scala 144:18] + node _T_9346 = eq(_T_9326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9347 = or(UInt<1>("h01"), _T_9346) @[RegMapper.scala 145:31] + _T_2898[136] <= _T_9347 @[RegMapper.scala 145:18] + node _T_9348 = shl(UInt<7>("h040"), 16) @[RegMapper.scala 150:47] + node _T_9350 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_9351 = and(_T_9348, _T_9350) @[RegMapper.scala 150:55] + node _T_9352 = or(_T_9312, _T_9351) @[RegMapper.scala 150:35] + node _T_9353 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_9355 = neq(_T_9353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9356 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_9357 = not(_T_9356) @[RegMapper.scala 136:45] + node _T_9359 = eq(_T_9357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9360 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_9362 = neq(_T_9360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9363 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_9364 = not(_T_9363) @[RegMapper.scala 138:44] + node _T_9366 = eq(_T_9364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9367 = and(_T_1958[137], _T_9355) @[RegMapper.scala 140:69] + node _T_9368 = and(_T_3086[137], _T_9362) @[RegMapper.scala 140:91] + node _T_9371 = and(_T_2146[137], _T_9359) @[RegMapper.scala 141:62] + node _T_9372 = and(_T_3274[137], _T_9366) @[RegMapper.scala 141:84] + node _T_9373 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_9377 = eq(_T_9355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9378 = or(UInt<1>("h01"), _T_9377) @[RegMapper.scala 142:31] + _T_2334[137] <= _T_9378 @[RegMapper.scala 142:18] + node _T_9380 = eq(_T_9359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9381 = or(UInt<1>("h01"), _T_9380) @[RegMapper.scala 143:31] + _T_2522[137] <= _T_9381 @[RegMapper.scala 143:18] + node _T_9383 = eq(_T_9362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9384 = or(UInt<1>("h01"), _T_9383) @[RegMapper.scala 144:31] + _T_2710[137] <= _T_9384 @[RegMapper.scala 144:18] + node _T_9386 = eq(_T_9366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9387 = or(UInt<1>("h01"), _T_9386) @[RegMapper.scala 145:31] + _T_2898[137] <= _T_9387 @[RegMapper.scala 145:18] + node _T_9388 = shl(UInt<8>("h0f1"), 24) @[RegMapper.scala 150:47] + node _T_9390 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_9391 = and(_T_9388, _T_9390) @[RegMapper.scala 150:55] + node _T_9392 = or(_T_9352, _T_9391) @[RegMapper.scala 150:35] + node _T_9393 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_9395 = neq(_T_9393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9396 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_9397 = not(_T_9396) @[RegMapper.scala 136:45] + node _T_9399 = eq(_T_9397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9400 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_9402 = neq(_T_9400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9403 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_9404 = not(_T_9403) @[RegMapper.scala 138:44] + node _T_9406 = eq(_T_9404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9407 = and(_T_1958[138], _T_9395) @[RegMapper.scala 140:69] + node _T_9408 = and(_T_3086[138], _T_9402) @[RegMapper.scala 140:91] + node _T_9411 = and(_T_2146[138], _T_9399) @[RegMapper.scala 141:62] + node _T_9412 = and(_T_3274[138], _T_9406) @[RegMapper.scala 141:84] + node _T_9413 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_9417 = eq(_T_9395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9418 = or(UInt<1>("h01"), _T_9417) @[RegMapper.scala 142:31] + _T_2334[138] <= _T_9418 @[RegMapper.scala 142:18] + node _T_9420 = eq(_T_9399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9421 = or(UInt<1>("h01"), _T_9420) @[RegMapper.scala 143:31] + _T_2522[138] <= _T_9421 @[RegMapper.scala 143:18] + node _T_9423 = eq(_T_9402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9424 = or(UInt<1>("h01"), _T_9423) @[RegMapper.scala 144:31] + _T_2710[138] <= _T_9424 @[RegMapper.scala 144:18] + node _T_9426 = eq(_T_9406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9427 = or(UInt<1>("h01"), _T_9426) @[RegMapper.scala 145:31] + _T_2898[138] <= _T_9427 @[RegMapper.scala 145:18] + node _T_9428 = shl(UInt<6>("h023"), 32) @[RegMapper.scala 150:47] + node _T_9430 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_9431 = and(_T_9428, _T_9430) @[RegMapper.scala 150:55] + node _T_9432 = or(_T_9392, _T_9431) @[RegMapper.scala 150:35] + node _T_9433 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_9435 = neq(_T_9433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9436 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_9437 = not(_T_9436) @[RegMapper.scala 136:45] + node _T_9439 = eq(_T_9437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9440 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_9442 = neq(_T_9440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9443 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_9444 = not(_T_9443) @[RegMapper.scala 138:44] + node _T_9446 = eq(_T_9444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9447 = and(_T_1958[139], _T_9435) @[RegMapper.scala 140:69] + node _T_9448 = and(_T_3086[139], _T_9442) @[RegMapper.scala 140:91] + node _T_9451 = and(_T_2146[139], _T_9439) @[RegMapper.scala 141:62] + node _T_9452 = and(_T_3274[139], _T_9446) @[RegMapper.scala 141:84] + node _T_9453 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_9457 = eq(_T_9435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9458 = or(UInt<1>("h01"), _T_9457) @[RegMapper.scala 142:31] + _T_2334[139] <= _T_9458 @[RegMapper.scala 142:18] + node _T_9460 = eq(_T_9439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9461 = or(UInt<1>("h01"), _T_9460) @[RegMapper.scala 143:31] + _T_2522[139] <= _T_9461 @[RegMapper.scala 143:18] + node _T_9463 = eq(_T_9442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9464 = or(UInt<1>("h01"), _T_9463) @[RegMapper.scala 144:31] + _T_2710[139] <= _T_9464 @[RegMapper.scala 144:18] + node _T_9466 = eq(_T_9446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9467 = or(UInt<1>("h01"), _T_9466) @[RegMapper.scala 145:31] + _T_2898[139] <= _T_9467 @[RegMapper.scala 145:18] + node _T_9468 = shl(UInt<6>("h026"), 40) @[RegMapper.scala 150:47] + node _T_9470 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_9471 = and(_T_9468, _T_9470) @[RegMapper.scala 150:55] + node _T_9472 = or(_T_9432, _T_9471) @[RegMapper.scala 150:35] + node _T_9473 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_9475 = neq(_T_9473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9476 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_9477 = not(_T_9476) @[RegMapper.scala 136:45] + node _T_9479 = eq(_T_9477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9480 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_9482 = neq(_T_9480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9483 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_9484 = not(_T_9483) @[RegMapper.scala 138:44] + node _T_9486 = eq(_T_9484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9487 = and(_T_1958[140], _T_9475) @[RegMapper.scala 140:69] + node _T_9488 = and(_T_3086[140], _T_9482) @[RegMapper.scala 140:91] + node _T_9491 = and(_T_2146[140], _T_9479) @[RegMapper.scala 141:62] + node _T_9492 = and(_T_3274[140], _T_9486) @[RegMapper.scala 141:84] + node _T_9493 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_9497 = eq(_T_9475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9498 = or(UInt<1>("h01"), _T_9497) @[RegMapper.scala 142:31] + _T_2334[140] <= _T_9498 @[RegMapper.scala 142:18] + node _T_9500 = eq(_T_9479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9501 = or(UInt<1>("h01"), _T_9500) @[RegMapper.scala 143:31] + _T_2522[140] <= _T_9501 @[RegMapper.scala 143:18] + node _T_9503 = eq(_T_9482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9504 = or(UInt<1>("h01"), _T_9503) @[RegMapper.scala 144:31] + _T_2710[140] <= _T_9504 @[RegMapper.scala 144:18] + node _T_9506 = eq(_T_9486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9507 = or(UInt<1>("h01"), _T_9506) @[RegMapper.scala 145:31] + _T_2898[140] <= _T_9507 @[RegMapper.scala 145:18] + node _T_9508 = shl(UInt<8>("h080"), 48) @[RegMapper.scala 150:47] + node _T_9510 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_9511 = and(_T_9508, _T_9510) @[RegMapper.scala 150:55] + node _T_9512 = or(_T_9472, _T_9511) @[RegMapper.scala 150:35] + node _T_9513 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_9515 = neq(_T_9513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9516 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_9517 = not(_T_9516) @[RegMapper.scala 136:45] + node _T_9519 = eq(_T_9517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9520 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_9522 = neq(_T_9520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9523 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_9524 = not(_T_9523) @[RegMapper.scala 138:44] + node _T_9526 = eq(_T_9524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9527 = and(_T_1958[141], _T_9515) @[RegMapper.scala 140:69] + node _T_9528 = and(_T_3086[141], _T_9522) @[RegMapper.scala 140:91] + node _T_9531 = and(_T_2146[141], _T_9519) @[RegMapper.scala 141:62] + node _T_9532 = and(_T_3274[141], _T_9526) @[RegMapper.scala 141:84] + node _T_9533 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_9537 = eq(_T_9515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9538 = or(UInt<1>("h01"), _T_9537) @[RegMapper.scala 142:31] + _T_2334[141] <= _T_9538 @[RegMapper.scala 142:18] + node _T_9540 = eq(_T_9519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9541 = or(UInt<1>("h01"), _T_9540) @[RegMapper.scala 143:31] + _T_2522[141] <= _T_9541 @[RegMapper.scala 143:18] + node _T_9543 = eq(_T_9522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9544 = or(UInt<1>("h01"), _T_9543) @[RegMapper.scala 144:31] + _T_2710[141] <= _T_9544 @[RegMapper.scala 144:18] + node _T_9546 = eq(_T_9526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9547 = or(UInt<1>("h01"), _T_9546) @[RegMapper.scala 145:31] + _T_2898[141] <= _T_9547 @[RegMapper.scala 145:18] + node _T_9548 = shl(UInt<5>("h010"), 56) @[RegMapper.scala 150:47] + node _T_9550 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_9551 = and(_T_9548, _T_9550) @[RegMapper.scala 150:55] + node _T_9552 = or(_T_9512, _T_9551) @[RegMapper.scala 150:35] + node _T_9553 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_9555 = neq(_T_9553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9556 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_9557 = not(_T_9556) @[RegMapper.scala 136:45] + node _T_9559 = eq(_T_9557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9560 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_9562 = neq(_T_9560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9563 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_9564 = not(_T_9563) @[RegMapper.scala 138:44] + node _T_9566 = eq(_T_9564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9567 = and(_T_1958[142], _T_9555) @[RegMapper.scala 140:69] + node _T_9568 = and(_T_3086[142], _T_9562) @[RegMapper.scala 140:91] + node _T_9571 = and(_T_2146[142], _T_9559) @[RegMapper.scala 141:62] + node _T_9572 = and(_T_3274[142], _T_9566) @[RegMapper.scala 141:84] + node _T_9573 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_9577 = eq(_T_9555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9578 = or(UInt<1>("h01"), _T_9577) @[RegMapper.scala 142:31] + _T_2334[142] <= _T_9578 @[RegMapper.scala 142:18] + node _T_9580 = eq(_T_9559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9581 = or(UInt<1>("h01"), _T_9580) @[RegMapper.scala 143:31] + _T_2522[142] <= _T_9581 @[RegMapper.scala 143:18] + node _T_9583 = eq(_T_9562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9584 = or(UInt<1>("h01"), _T_9583) @[RegMapper.scala 144:31] + _T_2710[142] <= _T_9584 @[RegMapper.scala 144:18] + node _T_9586 = eq(_T_9566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9587 = or(UInt<1>("h01"), _T_9586) @[RegMapper.scala 145:31] + _T_2898[142] <= _T_9587 @[RegMapper.scala 145:18] + node _T_9588 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_9590 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_9591 = and(_T_9588, _T_9590) @[RegMapper.scala 150:55] + node _T_9592 = or(UInt<1>("h00"), _T_9591) @[RegMapper.scala 150:35] + node _T_9593 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_9595 = neq(_T_9593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9596 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_9597 = not(_T_9596) @[RegMapper.scala 136:45] + node _T_9599 = eq(_T_9597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9600 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_9602 = neq(_T_9600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9603 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_9604 = not(_T_9603) @[RegMapper.scala 138:44] + node _T_9606 = eq(_T_9604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9607 = and(_T_1958[143], _T_9595) @[RegMapper.scala 140:69] + node _T_9608 = and(_T_3086[143], _T_9602) @[RegMapper.scala 140:91] + node _T_9611 = and(_T_2146[143], _T_9599) @[RegMapper.scala 141:62] + node _T_9612 = and(_T_3274[143], _T_9606) @[RegMapper.scala 141:84] + node _T_9613 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_9617 = eq(_T_9595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9618 = or(UInt<1>("h01"), _T_9617) @[RegMapper.scala 142:31] + _T_2334[143] <= _T_9618 @[RegMapper.scala 142:18] + node _T_9620 = eq(_T_9599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9621 = or(UInt<1>("h01"), _T_9620) @[RegMapper.scala 143:31] + _T_2522[143] <= _T_9621 @[RegMapper.scala 143:18] + node _T_9623 = eq(_T_9602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9624 = or(UInt<1>("h01"), _T_9623) @[RegMapper.scala 144:31] + _T_2710[143] <= _T_9624 @[RegMapper.scala 144:18] + node _T_9626 = eq(_T_9606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9627 = or(UInt<1>("h01"), _T_9626) @[RegMapper.scala 145:31] + _T_2898[143] <= _T_9627 @[RegMapper.scala 145:18] + node _T_9628 = shl(UInt<1>("h00"), 8) @[RegMapper.scala 150:47] + node _T_9630 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_9631 = and(_T_9628, _T_9630) @[RegMapper.scala 150:55] + node _T_9632 = or(_T_9592, _T_9631) @[RegMapper.scala 150:35] + node _T_9633 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_9635 = neq(_T_9633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9636 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_9637 = not(_T_9636) @[RegMapper.scala 136:45] + node _T_9639 = eq(_T_9637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9640 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_9642 = neq(_T_9640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9643 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_9644 = not(_T_9643) @[RegMapper.scala 138:44] + node _T_9646 = eq(_T_9644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9647 = and(_T_1958[144], _T_9635) @[RegMapper.scala 140:69] + node _T_9648 = and(_T_3086[144], _T_9642) @[RegMapper.scala 140:91] + node _T_9651 = and(_T_2146[144], _T_9639) @[RegMapper.scala 141:62] + node _T_9652 = and(_T_3274[144], _T_9646) @[RegMapper.scala 141:84] + node _T_9653 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_9657 = eq(_T_9635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9658 = or(UInt<1>("h01"), _T_9657) @[RegMapper.scala 142:31] + _T_2334[144] <= _T_9658 @[RegMapper.scala 142:18] + node _T_9660 = eq(_T_9639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9661 = or(UInt<1>("h01"), _T_9660) @[RegMapper.scala 143:31] + _T_2522[144] <= _T_9661 @[RegMapper.scala 143:18] + node _T_9663 = eq(_T_9642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9664 = or(UInt<1>("h01"), _T_9663) @[RegMapper.scala 144:31] + _T_2710[144] <= _T_9664 @[RegMapper.scala 144:18] + node _T_9666 = eq(_T_9646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9667 = or(UInt<1>("h01"), _T_9666) @[RegMapper.scala 145:31] + _T_2898[144] <= _T_9667 @[RegMapper.scala 145:18] + node _T_9668 = shl(UInt<6>("h020"), 16) @[RegMapper.scala 150:47] + node _T_9670 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_9671 = and(_T_9668, _T_9670) @[RegMapper.scala 150:55] + node _T_9672 = or(_T_9632, _T_9671) @[RegMapper.scala 150:35] + node _T_9673 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_9675 = neq(_T_9673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9676 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_9677 = not(_T_9676) @[RegMapper.scala 136:45] + node _T_9679 = eq(_T_9677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9680 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_9682 = neq(_T_9680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9683 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_9684 = not(_T_9683) @[RegMapper.scala 138:44] + node _T_9686 = eq(_T_9684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9687 = and(_T_1958[145], _T_9675) @[RegMapper.scala 140:69] + node _T_9688 = and(_T_3086[145], _T_9682) @[RegMapper.scala 140:91] + node _T_9691 = and(_T_2146[145], _T_9679) @[RegMapper.scala 141:62] + node _T_9692 = and(_T_3274[145], _T_9686) @[RegMapper.scala 141:84] + node _T_9693 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_9697 = eq(_T_9675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9698 = or(UInt<1>("h01"), _T_9697) @[RegMapper.scala 142:31] + _T_2334[145] <= _T_9698 @[RegMapper.scala 142:18] + node _T_9700 = eq(_T_9679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9701 = or(UInt<1>("h01"), _T_9700) @[RegMapper.scala 143:31] + _T_2522[145] <= _T_9701 @[RegMapper.scala 143:18] + node _T_9703 = eq(_T_9682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9704 = or(UInt<1>("h01"), _T_9703) @[RegMapper.scala 144:31] + _T_2710[145] <= _T_9704 @[RegMapper.scala 144:18] + node _T_9706 = eq(_T_9686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9707 = or(UInt<1>("h01"), _T_9706) @[RegMapper.scala 145:31] + _T_2898[145] <= _T_9707 @[RegMapper.scala 145:18] + node _T_9708 = shl(UInt<7>("h07b"), 24) @[RegMapper.scala 150:47] + node _T_9710 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_9711 = and(_T_9708, _T_9710) @[RegMapper.scala 150:55] + node _T_9712 = or(_T_9672, _T_9711) @[RegMapper.scala 150:35] + node _T_9713 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_9715 = neq(_T_9713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9716 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_9717 = not(_T_9716) @[RegMapper.scala 136:45] + node _T_9719 = eq(_T_9717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9720 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_9722 = neq(_T_9720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9723 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_9724 = not(_T_9723) @[RegMapper.scala 138:44] + node _T_9726 = eq(_T_9724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9727 = and(_T_1958[146], _T_9715) @[RegMapper.scala 140:69] + node _T_9728 = and(_T_3086[146], _T_9722) @[RegMapper.scala 140:91] + node _T_9731 = and(_T_2146[146], _T_9719) @[RegMapper.scala 141:62] + node _T_9732 = and(_T_3274[146], _T_9726) @[RegMapper.scala 141:84] + node _T_9733 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_9737 = eq(_T_9715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9738 = or(UInt<1>("h01"), _T_9737) @[RegMapper.scala 142:31] + _T_2334[146] <= _T_9738 @[RegMapper.scala 142:18] + node _T_9740 = eq(_T_9719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9741 = or(UInt<1>("h01"), _T_9740) @[RegMapper.scala 143:31] + _T_2522[146] <= _T_9741 @[RegMapper.scala 143:18] + node _T_9743 = eq(_T_9722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9744 = or(UInt<1>("h01"), _T_9743) @[RegMapper.scala 144:31] + _T_2710[146] <= _T_9744 @[RegMapper.scala 144:18] + node _T_9746 = eq(_T_9726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9747 = or(UInt<1>("h01"), _T_9746) @[RegMapper.scala 145:31] + _T_2898[146] <= _T_9747 @[RegMapper.scala 145:18] + node _T_9748 = shl(UInt<7>("h073"), 32) @[RegMapper.scala 150:47] + node _T_9750 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_9751 = and(_T_9748, _T_9750) @[RegMapper.scala 150:55] + node _T_9752 = or(_T_9712, _T_9751) @[RegMapper.scala 150:35] + node _T_9753 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_9755 = neq(_T_9753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9756 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_9757 = not(_T_9756) @[RegMapper.scala 136:45] + node _T_9759 = eq(_T_9757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9760 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_9762 = neq(_T_9760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9763 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_9764 = not(_T_9763) @[RegMapper.scala 138:44] + node _T_9766 = eq(_T_9764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9767 = and(_T_1958[147], _T_9755) @[RegMapper.scala 140:69] + node _T_9768 = and(_T_3086[147], _T_9762) @[RegMapper.scala 140:91] + node _T_9771 = and(_T_2146[147], _T_9759) @[RegMapper.scala 141:62] + node _T_9772 = and(_T_3274[147], _T_9766) @[RegMapper.scala 141:84] + node _T_9773 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_9777 = eq(_T_9755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9778 = or(UInt<1>("h01"), _T_9777) @[RegMapper.scala 142:31] + _T_2334[147] <= _T_9778 @[RegMapper.scala 142:18] + node _T_9780 = eq(_T_9759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9781 = or(UInt<1>("h01"), _T_9780) @[RegMapper.scala 143:31] + _T_2522[147] <= _T_9781 @[RegMapper.scala 143:18] + node _T_9783 = eq(_T_9762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9784 = or(UInt<1>("h01"), _T_9783) @[RegMapper.scala 144:31] + _T_2710[147] <= _T_9784 @[RegMapper.scala 144:18] + node _T_9786 = eq(_T_9766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9787 = or(UInt<1>("h01"), _T_9786) @[RegMapper.scala 145:31] + _T_2898[147] <= _T_9787 @[RegMapper.scala 145:18] + node _T_9788 = shl(UInt<5>("h010"), 40) @[RegMapper.scala 150:47] + node _T_9790 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_9791 = and(_T_9788, _T_9790) @[RegMapper.scala 150:55] + node _T_9792 = or(_T_9752, _T_9791) @[RegMapper.scala 150:35] + node _T_9793 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_9795 = neq(_T_9793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9796 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_9797 = not(_T_9796) @[RegMapper.scala 136:45] + node _T_9799 = eq(_T_9797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9800 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_9802 = neq(_T_9800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9803 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_9804 = not(_T_9803) @[RegMapper.scala 138:44] + node _T_9806 = eq(_T_9804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9807 = and(_T_1958[148], _T_9795) @[RegMapper.scala 140:69] + node _T_9808 = and(_T_3086[148], _T_9802) @[RegMapper.scala 140:91] + node _T_9811 = and(_T_2146[148], _T_9799) @[RegMapper.scala 141:62] + node _T_9812 = and(_T_3274[148], _T_9806) @[RegMapper.scala 141:84] + node _T_9813 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_9817 = eq(_T_9795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9818 = or(UInt<1>("h01"), _T_9817) @[RegMapper.scala 142:31] + _T_2334[148] <= _T_9818 @[RegMapper.scala 142:18] + node _T_9820 = eq(_T_9799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9821 = or(UInt<1>("h01"), _T_9820) @[RegMapper.scala 143:31] + _T_2522[148] <= _T_9821 @[RegMapper.scala 143:18] + node _T_9823 = eq(_T_9802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9824 = or(UInt<1>("h01"), _T_9823) @[RegMapper.scala 144:31] + _T_2710[148] <= _T_9824 @[RegMapper.scala 144:18] + node _T_9826 = eq(_T_9806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9827 = or(UInt<1>("h01"), _T_9826) @[RegMapper.scala 145:31] + _T_2898[148] <= _T_9827 @[RegMapper.scala 145:18] + node _T_9828 = shl(UInt<6>("h024"), 48) @[RegMapper.scala 150:47] + node _T_9830 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_9831 = and(_T_9828, _T_9830) @[RegMapper.scala 150:55] + node _T_9832 = or(_T_9792, _T_9831) @[RegMapper.scala 150:35] + node _T_9833 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_9835 = neq(_T_9833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9836 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_9837 = not(_T_9836) @[RegMapper.scala 136:45] + node _T_9839 = eq(_T_9837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9840 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_9842 = neq(_T_9840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9843 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_9844 = not(_T_9843) @[RegMapper.scala 138:44] + node _T_9846 = eq(_T_9844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9847 = and(_T_1958[149], _T_9835) @[RegMapper.scala 140:69] + node _T_9848 = and(_T_3086[149], _T_9842) @[RegMapper.scala 140:91] + node _T_9851 = and(_T_2146[149], _T_9839) @[RegMapper.scala 141:62] + node _T_9852 = and(_T_3274[149], _T_9846) @[RegMapper.scala 141:84] + node _T_9853 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_9857 = eq(_T_9835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9858 = or(UInt<1>("h01"), _T_9857) @[RegMapper.scala 142:31] + _T_2334[149] <= _T_9858 @[RegMapper.scala 142:18] + node _T_9860 = eq(_T_9839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9861 = or(UInt<1>("h01"), _T_9860) @[RegMapper.scala 143:31] + _T_2522[149] <= _T_9861 @[RegMapper.scala 143:18] + node _T_9863 = eq(_T_9842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9864 = or(UInt<1>("h01"), _T_9863) @[RegMapper.scala 144:31] + _T_2710[149] <= _T_9864 @[RegMapper.scala 144:18] + node _T_9866 = eq(_T_9846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9867 = or(UInt<1>("h01"), _T_9866) @[RegMapper.scala 145:31] + _T_2898[149] <= _T_9867 @[RegMapper.scala 145:18] + node _T_9868 = shl(UInt<7>("h07b"), 56) @[RegMapper.scala 150:47] + node _T_9870 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_9871 = and(_T_9868, _T_9870) @[RegMapper.scala 150:55] + node _T_9872 = or(_T_9832, _T_9871) @[RegMapper.scala 150:35] + node _T_9873 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_9875 = neq(_T_9873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9876 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_9877 = not(_T_9876) @[RegMapper.scala 136:45] + node _T_9879 = eq(_T_9877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9880 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_9882 = neq(_T_9880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9883 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_9884 = not(_T_9883) @[RegMapper.scala 138:44] + node _T_9886 = eq(_T_9884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9887 = and(_T_1958[150], _T_9875) @[RegMapper.scala 140:69] + node _T_9888 = and(_T_3086[150], _T_9882) @[RegMapper.scala 140:91] + node _T_9891 = and(_T_2146[150], _T_9879) @[RegMapper.scala 141:62] + node _T_9892 = and(_T_3274[150], _T_9886) @[RegMapper.scala 141:84] + node _T_9893 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_9897 = eq(_T_9875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9898 = or(UInt<1>("h01"), _T_9897) @[RegMapper.scala 142:31] + _T_2334[150] <= _T_9898 @[RegMapper.scala 142:18] + node _T_9900 = eq(_T_9879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9901 = or(UInt<1>("h01"), _T_9900) @[RegMapper.scala 143:31] + _T_2522[150] <= _T_9901 @[RegMapper.scala 143:18] + node _T_9903 = eq(_T_9882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9904 = or(UInt<1>("h01"), _T_9903) @[RegMapper.scala 144:31] + _T_2710[150] <= _T_9904 @[RegMapper.scala 144:18] + node _T_9906 = eq(_T_9886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9907 = or(UInt<1>("h01"), _T_9906) @[RegMapper.scala 145:31] + _T_2898[150] <= _T_9907 @[RegMapper.scala 145:18] + node _T_9908 = shl(UInt<5>("h013"), 0) @[RegMapper.scala 150:47] + node _T_9910 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_9911 = and(_T_9908, _T_9910) @[RegMapper.scala 150:55] + node _T_9912 = or(UInt<1>("h00"), _T_9911) @[RegMapper.scala 150:35] + node _T_9913 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_9915 = neq(_T_9913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9916 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_9917 = not(_T_9916) @[RegMapper.scala 136:45] + node _T_9919 = eq(_T_9917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9920 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_9922 = neq(_T_9920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9923 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_9924 = not(_T_9923) @[RegMapper.scala 138:44] + node _T_9926 = eq(_T_9924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9927 = and(_T_1958[151], _T_9915) @[RegMapper.scala 140:69] + node _T_9928 = and(_T_3086[151], _T_9922) @[RegMapper.scala 140:91] + node _T_9931 = and(_T_2146[151], _T_9919) @[RegMapper.scala 141:62] + node _T_9932 = and(_T_3274[151], _T_9926) @[RegMapper.scala 141:84] + node _T_9933 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_9937 = eq(_T_9915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9938 = or(UInt<1>("h01"), _T_9937) @[RegMapper.scala 142:31] + _T_2334[151] <= _T_9938 @[RegMapper.scala 142:18] + node _T_9940 = eq(_T_9919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9941 = or(UInt<1>("h01"), _T_9940) @[RegMapper.scala 143:31] + _T_2522[151] <= _T_9941 @[RegMapper.scala 143:18] + node _T_9943 = eq(_T_9922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9944 = or(UInt<1>("h01"), _T_9943) @[RegMapper.scala 144:31] + _T_2710[151] <= _T_9944 @[RegMapper.scala 144:18] + node _T_9946 = eq(_T_9926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9947 = or(UInt<1>("h01"), _T_9946) @[RegMapper.scala 145:31] + _T_2898[151] <= _T_9947 @[RegMapper.scala 145:18] + node _T_9948 = shl(UInt<3>("h04"), 8) @[RegMapper.scala 150:47] + node _T_9950 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_9951 = and(_T_9948, _T_9950) @[RegMapper.scala 150:55] + node _T_9952 = or(_T_9912, _T_9951) @[RegMapper.scala 150:35] + node _T_9953 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_9955 = neq(_T_9953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9956 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_9957 = not(_T_9956) @[RegMapper.scala 136:45] + node _T_9959 = eq(_T_9957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_9960 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_9962 = neq(_T_9960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_9963 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_9964 = not(_T_9963) @[RegMapper.scala 138:44] + node _T_9966 = eq(_T_9964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_9967 = and(_T_1958[152], _T_9955) @[RegMapper.scala 140:69] + node _T_9968 = and(_T_3086[152], _T_9962) @[RegMapper.scala 140:91] + node _T_9971 = and(_T_2146[152], _T_9959) @[RegMapper.scala 141:62] + node _T_9972 = and(_T_3274[152], _T_9966) @[RegMapper.scala 141:84] + node _T_9973 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_9977 = eq(_T_9955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_9978 = or(UInt<1>("h01"), _T_9977) @[RegMapper.scala 142:31] + _T_2334[152] <= _T_9978 @[RegMapper.scala 142:18] + node _T_9980 = eq(_T_9959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_9981 = or(UInt<1>("h01"), _T_9980) @[RegMapper.scala 143:31] + _T_2522[152] <= _T_9981 @[RegMapper.scala 143:18] + node _T_9983 = eq(_T_9962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_9984 = or(UInt<1>("h01"), _T_9983) @[RegMapper.scala 144:31] + _T_2710[152] <= _T_9984 @[RegMapper.scala 144:18] + node _T_9986 = eq(_T_9966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_9987 = or(UInt<1>("h01"), _T_9986) @[RegMapper.scala 145:31] + _T_2898[152] <= _T_9987 @[RegMapper.scala 145:18] + node _T_9988 = shl(UInt<1>("h00"), 16) @[RegMapper.scala 150:47] + node _T_9990 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_9991 = and(_T_9988, _T_9990) @[RegMapper.scala 150:55] + node _T_9992 = or(_T_9952, _T_9991) @[RegMapper.scala 150:35] + node _T_9993 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_9995 = neq(_T_9993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_9996 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_9997 = not(_T_9996) @[RegMapper.scala 136:45] + node _T_9999 = eq(_T_9997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10000 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_10002 = neq(_T_10000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10003 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_10004 = not(_T_10003) @[RegMapper.scala 138:44] + node _T_10006 = eq(_T_10004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10007 = and(_T_1958[153], _T_9995) @[RegMapper.scala 140:69] + node _T_10008 = and(_T_3086[153], _T_10002) @[RegMapper.scala 140:91] + node _T_10011 = and(_T_2146[153], _T_9999) @[RegMapper.scala 141:62] + node _T_10012 = and(_T_3274[153], _T_10006) @[RegMapper.scala 141:84] + node _T_10013 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_10017 = eq(_T_9995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10018 = or(UInt<1>("h01"), _T_10017) @[RegMapper.scala 142:31] + _T_2334[153] <= _T_10018 @[RegMapper.scala 142:18] + node _T_10020 = eq(_T_9999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10021 = or(UInt<1>("h01"), _T_10020) @[RegMapper.scala 143:31] + _T_2522[153] <= _T_10021 @[RegMapper.scala 143:18] + node _T_10023 = eq(_T_10002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10024 = or(UInt<1>("h01"), _T_10023) @[RegMapper.scala 144:31] + _T_2710[153] <= _T_10024 @[RegMapper.scala 144:18] + node _T_10026 = eq(_T_10006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10027 = or(UInt<1>("h01"), _T_10026) @[RegMapper.scala 145:31] + _T_2898[153] <= _T_10027 @[RegMapper.scala 145:18] + node _T_10028 = shl(UInt<1>("h00"), 24) @[RegMapper.scala 150:47] + node _T_10030 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_10031 = and(_T_10028, _T_10030) @[RegMapper.scala 150:55] + node _T_10032 = or(_T_9992, _T_10031) @[RegMapper.scala 150:35] + node _T_10033 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_10035 = neq(_T_10033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10036 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_10037 = not(_T_10036) @[RegMapper.scala 136:45] + node _T_10039 = eq(_T_10037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10040 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_10042 = neq(_T_10040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10043 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_10044 = not(_T_10043) @[RegMapper.scala 138:44] + node _T_10046 = eq(_T_10044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10047 = and(_T_1958[154], _T_10035) @[RegMapper.scala 140:69] + node _T_10048 = and(_T_3086[154], _T_10042) @[RegMapper.scala 140:91] + node _T_10051 = and(_T_2146[154], _T_10039) @[RegMapper.scala 141:62] + node _T_10052 = and(_T_3274[154], _T_10046) @[RegMapper.scala 141:84] + node _T_10053 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_10057 = eq(_T_10035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10058 = or(UInt<1>("h01"), _T_10057) @[RegMapper.scala 142:31] + _T_2334[154] <= _T_10058 @[RegMapper.scala 142:18] + node _T_10060 = eq(_T_10039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10061 = or(UInt<1>("h01"), _T_10060) @[RegMapper.scala 143:31] + _T_2522[154] <= _T_10061 @[RegMapper.scala 143:18] + node _T_10063 = eq(_T_10042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10064 = or(UInt<1>("h01"), _T_10063) @[RegMapper.scala 144:31] + _T_2710[154] <= _T_10064 @[RegMapper.scala 144:18] + node _T_10066 = eq(_T_10046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10067 = or(UInt<1>("h01"), _T_10066) @[RegMapper.scala 145:31] + _T_2898[154] <= _T_10067 @[RegMapper.scala 145:18] + node _T_10068 = shl(UInt<4>("h0f"), 32) @[RegMapper.scala 150:47] + node _T_10070 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_10071 = and(_T_10068, _T_10070) @[RegMapper.scala 150:55] + node _T_10072 = or(_T_10032, _T_10071) @[RegMapper.scala 150:35] + node _T_10073 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_10075 = neq(_T_10073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10076 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_10077 = not(_T_10076) @[RegMapper.scala 136:45] + node _T_10079 = eq(_T_10077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10080 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_10082 = neq(_T_10080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10083 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_10084 = not(_T_10083) @[RegMapper.scala 138:44] + node _T_10086 = eq(_T_10084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10087 = and(_T_1958[155], _T_10075) @[RegMapper.scala 140:69] + node _T_10088 = and(_T_3086[155], _T_10082) @[RegMapper.scala 140:91] + node _T_10091 = and(_T_2146[155], _T_10079) @[RegMapper.scala 141:62] + node _T_10092 = and(_T_3274[155], _T_10086) @[RegMapper.scala 141:84] + node _T_10093 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_10097 = eq(_T_10075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10098 = or(UInt<1>("h01"), _T_10097) @[RegMapper.scala 142:31] + _T_2334[155] <= _T_10098 @[RegMapper.scala 142:18] + node _T_10100 = eq(_T_10079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10101 = or(UInt<1>("h01"), _T_10100) @[RegMapper.scala 143:31] + _T_2522[155] <= _T_10101 @[RegMapper.scala 143:18] + node _T_10103 = eq(_T_10082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10104 = or(UInt<1>("h01"), _T_10103) @[RegMapper.scala 144:31] + _T_2710[155] <= _T_10104 @[RegMapper.scala 144:18] + node _T_10106 = eq(_T_10086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10107 = or(UInt<1>("h01"), _T_10106) @[RegMapper.scala 145:31] + _T_2898[155] <= _T_10107 @[RegMapper.scala 145:18] + node _T_10108 = shl(UInt<1>("h00"), 40) @[RegMapper.scala 150:47] + node _T_10110 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_10111 = and(_T_10108, _T_10110) @[RegMapper.scala 150:55] + node _T_10112 = or(_T_10072, _T_10111) @[RegMapper.scala 150:35] + node _T_10113 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_10115 = neq(_T_10113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10116 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_10117 = not(_T_10116) @[RegMapper.scala 136:45] + node _T_10119 = eq(_T_10117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10120 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_10122 = neq(_T_10120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10123 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_10124 = not(_T_10123) @[RegMapper.scala 138:44] + node _T_10126 = eq(_T_10124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10127 = and(_T_1958[156], _T_10115) @[RegMapper.scala 140:69] + node _T_10128 = and(_T_3086[156], _T_10122) @[RegMapper.scala 140:91] + node _T_10131 = and(_T_2146[156], _T_10119) @[RegMapper.scala 141:62] + node _T_10132 = and(_T_3274[156], _T_10126) @[RegMapper.scala 141:84] + node _T_10133 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_10137 = eq(_T_10115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10138 = or(UInt<1>("h01"), _T_10137) @[RegMapper.scala 142:31] + _T_2334[156] <= _T_10138 @[RegMapper.scala 142:18] + node _T_10140 = eq(_T_10119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10141 = or(UInt<1>("h01"), _T_10140) @[RegMapper.scala 143:31] + _T_2522[156] <= _T_10141 @[RegMapper.scala 143:18] + node _T_10143 = eq(_T_10122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10144 = or(UInt<1>("h01"), _T_10143) @[RegMapper.scala 144:31] + _T_2710[156] <= _T_10144 @[RegMapper.scala 144:18] + node _T_10146 = eq(_T_10126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10147 = or(UInt<1>("h01"), _T_10146) @[RegMapper.scala 145:31] + _T_2898[156] <= _T_10147 @[RegMapper.scala 145:18] + node _T_10148 = shl(UInt<8>("h0f0"), 48) @[RegMapper.scala 150:47] + node _T_10150 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_10151 = and(_T_10148, _T_10150) @[RegMapper.scala 150:55] + node _T_10152 = or(_T_10112, _T_10151) @[RegMapper.scala 150:35] + node _T_10153 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_10155 = neq(_T_10153, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10156 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_10157 = not(_T_10156) @[RegMapper.scala 136:45] + node _T_10159 = eq(_T_10157, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10160 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_10162 = neq(_T_10160, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10163 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_10164 = not(_T_10163) @[RegMapper.scala 138:44] + node _T_10166 = eq(_T_10164, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10167 = and(_T_1958[157], _T_10155) @[RegMapper.scala 140:69] + node _T_10168 = and(_T_3086[157], _T_10162) @[RegMapper.scala 140:91] + node _T_10171 = and(_T_2146[157], _T_10159) @[RegMapper.scala 141:62] + node _T_10172 = and(_T_3274[157], _T_10166) @[RegMapper.scala 141:84] + node _T_10173 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_10177 = eq(_T_10155, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10178 = or(UInt<1>("h01"), _T_10177) @[RegMapper.scala 142:31] + _T_2334[157] <= _T_10178 @[RegMapper.scala 142:18] + node _T_10180 = eq(_T_10159, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10181 = or(UInt<1>("h01"), _T_10180) @[RegMapper.scala 143:31] + _T_2522[157] <= _T_10181 @[RegMapper.scala 143:18] + node _T_10183 = eq(_T_10162, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10184 = or(UInt<1>("h01"), _T_10183) @[RegMapper.scala 144:31] + _T_2710[157] <= _T_10184 @[RegMapper.scala 144:18] + node _T_10186 = eq(_T_10166, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10187 = or(UInt<1>("h01"), _T_10186) @[RegMapper.scala 145:31] + _T_2898[157] <= _T_10187 @[RegMapper.scala 145:18] + node _T_10188 = shl(UInt<4>("h0f"), 56) @[RegMapper.scala 150:47] + node _T_10190 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_10191 = and(_T_10188, _T_10190) @[RegMapper.scala 150:55] + node _T_10192 = or(_T_10152, _T_10191) @[RegMapper.scala 150:35] + node _T_10193 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_10195 = neq(_T_10193, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10196 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_10197 = not(_T_10196) @[RegMapper.scala 136:45] + node _T_10199 = eq(_T_10197, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10200 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_10202 = neq(_T_10200, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10203 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_10204 = not(_T_10203) @[RegMapper.scala 138:44] + node _T_10206 = eq(_T_10204, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10207 = and(_T_1958[158], _T_10195) @[RegMapper.scala 140:69] + node _T_10208 = and(_T_3086[158], _T_10202) @[RegMapper.scala 140:91] + node _T_10211 = and(_T_2146[158], _T_10199) @[RegMapper.scala 141:62] + node _T_10212 = and(_T_3274[158], _T_10206) @[RegMapper.scala 141:84] + node _T_10213 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_10217 = eq(_T_10195, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10218 = or(UInt<1>("h01"), _T_10217) @[RegMapper.scala 142:31] + _T_2334[158] <= _T_10218 @[RegMapper.scala 142:18] + node _T_10220 = eq(_T_10199, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10221 = or(UInt<1>("h01"), _T_10220) @[RegMapper.scala 143:31] + _T_2522[158] <= _T_10221 @[RegMapper.scala 143:18] + node _T_10223 = eq(_T_10202, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10224 = or(UInt<1>("h01"), _T_10223) @[RegMapper.scala 144:31] + _T_2710[158] <= _T_10224 @[RegMapper.scala 144:18] + node _T_10226 = eq(_T_10206, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10227 = or(UInt<1>("h01"), _T_10226) @[RegMapper.scala 145:31] + _T_2898[158] <= _T_10227 @[RegMapper.scala 145:18] + node _T_10228 = shl(UInt<7>("h063"), 0) @[RegMapper.scala 150:47] + node _T_10230 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_10231 = and(_T_10228, _T_10230) @[RegMapper.scala 150:55] + node _T_10232 = or(UInt<1>("h00"), _T_10231) @[RegMapper.scala 150:35] + node _T_10233 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_10235 = neq(_T_10233, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10236 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_10237 = not(_T_10236) @[RegMapper.scala 136:45] + node _T_10239 = eq(_T_10237, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10240 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_10242 = neq(_T_10240, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10243 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_10244 = not(_T_10243) @[RegMapper.scala 138:44] + node _T_10246 = eq(_T_10244, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10247 = and(_T_1958[159], _T_10235) @[RegMapper.scala 140:69] + node _T_10248 = and(_T_3086[159], _T_10242) @[RegMapper.scala 140:91] + node _T_10251 = and(_T_2146[159], _T_10239) @[RegMapper.scala 141:62] + node _T_10252 = and(_T_3274[159], _T_10246) @[RegMapper.scala 141:84] + node _T_10253 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_10257 = eq(_T_10235, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10258 = or(UInt<1>("h01"), _T_10257) @[RegMapper.scala 142:31] + _T_2334[159] <= _T_10258 @[RegMapper.scala 142:18] + node _T_10260 = eq(_T_10239, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10261 = or(UInt<1>("h01"), _T_10260) @[RegMapper.scala 143:31] + _T_2522[159] <= _T_10261 @[RegMapper.scala 143:18] + node _T_10263 = eq(_T_10242, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10264 = or(UInt<1>("h01"), _T_10263) @[RegMapper.scala 144:31] + _T_2710[159] <= _T_10264 @[RegMapper.scala 144:18] + node _T_10266 = eq(_T_10246, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10267 = or(UInt<1>("h01"), _T_10266) @[RegMapper.scala 145:31] + _T_2898[159] <= _T_10267 @[RegMapper.scala 145:18] + node _T_10268 = shl(UInt<5>("h01a"), 8) @[RegMapper.scala 150:47] + node _T_10270 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_10271 = and(_T_10268, _T_10270) @[RegMapper.scala 150:55] + node _T_10272 = or(_T_10232, _T_10271) @[RegMapper.scala 150:35] + node _T_10273 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_10275 = neq(_T_10273, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10276 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_10277 = not(_T_10276) @[RegMapper.scala 136:45] + node _T_10279 = eq(_T_10277, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10280 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_10282 = neq(_T_10280, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10283 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_10284 = not(_T_10283) @[RegMapper.scala 138:44] + node _T_10286 = eq(_T_10284, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10287 = and(_T_1958[160], _T_10275) @[RegMapper.scala 140:69] + node _T_10288 = and(_T_3086[160], _T_10282) @[RegMapper.scala 140:91] + node _T_10291 = and(_T_2146[160], _T_10279) @[RegMapper.scala 141:62] + node _T_10292 = and(_T_3274[160], _T_10286) @[RegMapper.scala 141:84] + node _T_10293 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_10297 = eq(_T_10275, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10298 = or(UInt<1>("h01"), _T_10297) @[RegMapper.scala 142:31] + _T_2334[160] <= _T_10298 @[RegMapper.scala 142:18] + node _T_10300 = eq(_T_10279, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10301 = or(UInt<1>("h01"), _T_10300) @[RegMapper.scala 143:31] + _T_2522[160] <= _T_10301 @[RegMapper.scala 143:18] + node _T_10303 = eq(_T_10282, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10304 = or(UInt<1>("h01"), _T_10303) @[RegMapper.scala 144:31] + _T_2710[160] <= _T_10304 @[RegMapper.scala 144:18] + node _T_10306 = eq(_T_10286, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10307 = or(UInt<1>("h01"), _T_10306) @[RegMapper.scala 145:31] + _T_2898[160] <= _T_10307 @[RegMapper.scala 145:18] + node _T_10308 = shl(UInt<3>("h04"), 16) @[RegMapper.scala 150:47] + node _T_10310 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_10311 = and(_T_10308, _T_10310) @[RegMapper.scala 150:55] + node _T_10312 = or(_T_10272, _T_10311) @[RegMapper.scala 150:35] + node _T_10313 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_10315 = neq(_T_10313, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10316 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_10317 = not(_T_10316) @[RegMapper.scala 136:45] + node _T_10319 = eq(_T_10317, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10320 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_10322 = neq(_T_10320, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10323 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_10324 = not(_T_10323) @[RegMapper.scala 138:44] + node _T_10326 = eq(_T_10324, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10327 = and(_T_1958[161], _T_10315) @[RegMapper.scala 140:69] + node _T_10328 = and(_T_3086[161], _T_10322) @[RegMapper.scala 140:91] + node _T_10331 = and(_T_2146[161], _T_10319) @[RegMapper.scala 141:62] + node _T_10332 = and(_T_3274[161], _T_10326) @[RegMapper.scala 141:84] + node _T_10333 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_10337 = eq(_T_10315, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10338 = or(UInt<1>("h01"), _T_10337) @[RegMapper.scala 142:31] + _T_2334[161] <= _T_10338 @[RegMapper.scala 142:18] + node _T_10340 = eq(_T_10319, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10341 = or(UInt<1>("h01"), _T_10340) @[RegMapper.scala 143:31] + _T_2522[161] <= _T_10341 @[RegMapper.scala 143:18] + node _T_10343 = eq(_T_10322, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10344 = or(UInt<1>("h01"), _T_10343) @[RegMapper.scala 144:31] + _T_2710[161] <= _T_10344 @[RegMapper.scala 144:18] + node _T_10346 = eq(_T_10326, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10347 = or(UInt<1>("h01"), _T_10346) @[RegMapper.scala 145:31] + _T_2898[161] <= _T_10347 @[RegMapper.scala 145:18] + node _T_10348 = shl(UInt<2>("h02"), 24) @[RegMapper.scala 150:47] + node _T_10350 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_10351 = and(_T_10348, _T_10350) @[RegMapper.scala 150:55] + node _T_10352 = or(_T_10312, _T_10351) @[RegMapper.scala 150:35] + node _T_10353 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_10355 = neq(_T_10353, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10356 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_10357 = not(_T_10356) @[RegMapper.scala 136:45] + node _T_10359 = eq(_T_10357, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10360 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_10362 = neq(_T_10360, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10363 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_10364 = not(_T_10363) @[RegMapper.scala 138:44] + node _T_10366 = eq(_T_10364, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10367 = and(_T_1958[162], _T_10355) @[RegMapper.scala 140:69] + node _T_10368 = and(_T_3086[162], _T_10362) @[RegMapper.scala 140:91] + node _T_10371 = and(_T_2146[162], _T_10359) @[RegMapper.scala 141:62] + node _T_10372 = and(_T_3274[162], _T_10366) @[RegMapper.scala 141:84] + node _T_10373 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_10377 = eq(_T_10355, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10378 = or(UInt<1>("h01"), _T_10377) @[RegMapper.scala 142:31] + _T_2334[162] <= _T_10378 @[RegMapper.scala 142:18] + node _T_10380 = eq(_T_10359, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10381 = or(UInt<1>("h01"), _T_10380) @[RegMapper.scala 143:31] + _T_2522[162] <= _T_10381 @[RegMapper.scala 143:18] + node _T_10383 = eq(_T_10362, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10384 = or(UInt<1>("h01"), _T_10383) @[RegMapper.scala 144:31] + _T_2710[162] <= _T_10384 @[RegMapper.scala 144:18] + node _T_10386 = eq(_T_10366, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10387 = or(UInt<1>("h01"), _T_10386) @[RegMapper.scala 145:31] + _T_2898[162] <= _T_10387 @[RegMapper.scala 145:18] + node _T_10388 = shl(UInt<7>("h073"), 32) @[RegMapper.scala 150:47] + node _T_10390 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_10391 = and(_T_10388, _T_10390) @[RegMapper.scala 150:55] + node _T_10392 = or(_T_10352, _T_10391) @[RegMapper.scala 150:35] + node _T_10393 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_10395 = neq(_T_10393, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10396 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_10397 = not(_T_10396) @[RegMapper.scala 136:45] + node _T_10399 = eq(_T_10397, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10400 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_10402 = neq(_T_10400, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10403 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_10404 = not(_T_10403) @[RegMapper.scala 138:44] + node _T_10406 = eq(_T_10404, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10407 = and(_T_1958[163], _T_10395) @[RegMapper.scala 140:69] + node _T_10408 = and(_T_3086[163], _T_10402) @[RegMapper.scala 140:91] + node _T_10411 = and(_T_2146[163], _T_10399) @[RegMapper.scala 141:62] + node _T_10412 = and(_T_3274[163], _T_10406) @[RegMapper.scala 141:84] + node _T_10413 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_10417 = eq(_T_10395, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10418 = or(UInt<1>("h01"), _T_10417) @[RegMapper.scala 142:31] + _T_2334[163] <= _T_10418 @[RegMapper.scala 142:18] + node _T_10420 = eq(_T_10399, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10421 = or(UInt<1>("h01"), _T_10420) @[RegMapper.scala 143:31] + _T_2522[163] <= _T_10421 @[RegMapper.scala 143:18] + node _T_10423 = eq(_T_10402, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10424 = or(UInt<1>("h01"), _T_10423) @[RegMapper.scala 144:31] + _T_2710[163] <= _T_10424 @[RegMapper.scala 144:18] + node _T_10426 = eq(_T_10406, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10427 = or(UInt<1>("h01"), _T_10426) @[RegMapper.scala 145:31] + _T_2898[163] <= _T_10427 @[RegMapper.scala 145:18] + node _T_10428 = shl(UInt<6>("h024"), 40) @[RegMapper.scala 150:47] + node _T_10430 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_10431 = and(_T_10428, _T_10430) @[RegMapper.scala 150:55] + node _T_10432 = or(_T_10392, _T_10431) @[RegMapper.scala 150:35] + node _T_10433 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_10435 = neq(_T_10433, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10436 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_10437 = not(_T_10436) @[RegMapper.scala 136:45] + node _T_10439 = eq(_T_10437, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10440 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_10442 = neq(_T_10440, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10443 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_10444 = not(_T_10443) @[RegMapper.scala 138:44] + node _T_10446 = eq(_T_10444, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10447 = and(_T_1958[164], _T_10435) @[RegMapper.scala 140:69] + node _T_10448 = and(_T_3086[164], _T_10442) @[RegMapper.scala 140:91] + node _T_10451 = and(_T_2146[164], _T_10439) @[RegMapper.scala 141:62] + node _T_10452 = and(_T_3274[164], _T_10446) @[RegMapper.scala 141:84] + node _T_10453 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_10457 = eq(_T_10435, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10458 = or(UInt<1>("h01"), _T_10457) @[RegMapper.scala 142:31] + _T_2334[164] <= _T_10458 @[RegMapper.scala 142:18] + node _T_10460 = eq(_T_10439, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10461 = or(UInt<1>("h01"), _T_10460) @[RegMapper.scala 143:31] + _T_2522[164] <= _T_10461 @[RegMapper.scala 143:18] + node _T_10463 = eq(_T_10442, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10464 = or(UInt<1>("h01"), _T_10463) @[RegMapper.scala 144:31] + _T_2710[164] <= _T_10464 @[RegMapper.scala 144:18] + node _T_10466 = eq(_T_10446, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10467 = or(UInt<1>("h01"), _T_10466) @[RegMapper.scala 145:31] + _T_2898[164] <= _T_10467 @[RegMapper.scala 145:18] + node _T_10468 = shl(UInt<6>("h020"), 48) @[RegMapper.scala 150:47] + node _T_10470 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_10471 = and(_T_10468, _T_10470) @[RegMapper.scala 150:55] + node _T_10472 = or(_T_10432, _T_10471) @[RegMapper.scala 150:35] + node _T_10473 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_10475 = neq(_T_10473, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10476 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_10477 = not(_T_10476) @[RegMapper.scala 136:45] + node _T_10479 = eq(_T_10477, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10480 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_10482 = neq(_T_10480, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10483 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_10484 = not(_T_10483) @[RegMapper.scala 138:44] + node _T_10486 = eq(_T_10484, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10487 = and(_T_1958[165], _T_10475) @[RegMapper.scala 140:69] + node _T_10488 = and(_T_3086[165], _T_10482) @[RegMapper.scala 140:91] + node _T_10491 = and(_T_2146[165], _T_10479) @[RegMapper.scala 141:62] + node _T_10492 = and(_T_3274[165], _T_10486) @[RegMapper.scala 141:84] + node _T_10493 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_10497 = eq(_T_10475, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10498 = or(UInt<1>("h01"), _T_10497) @[RegMapper.scala 142:31] + _T_2334[165] <= _T_10498 @[RegMapper.scala 142:18] + node _T_10500 = eq(_T_10479, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10501 = or(UInt<1>("h01"), _T_10500) @[RegMapper.scala 143:31] + _T_2522[165] <= _T_10501 @[RegMapper.scala 143:18] + node _T_10503 = eq(_T_10482, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10504 = or(UInt<1>("h01"), _T_10503) @[RegMapper.scala 144:31] + _T_2710[165] <= _T_10504 @[RegMapper.scala 144:18] + node _T_10506 = eq(_T_10486, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10507 = or(UInt<1>("h01"), _T_10506) @[RegMapper.scala 145:31] + _T_2898[165] <= _T_10507 @[RegMapper.scala 145:18] + node _T_10508 = shl(UInt<7>("h07b"), 56) @[RegMapper.scala 150:47] + node _T_10510 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_10511 = and(_T_10508, _T_10510) @[RegMapper.scala 150:55] + node _T_10512 = or(_T_10472, _T_10511) @[RegMapper.scala 150:35] + node _T_10513 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_10515 = neq(_T_10513, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10516 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_10517 = not(_T_10516) @[RegMapper.scala 136:45] + node _T_10519 = eq(_T_10517, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10520 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_10522 = neq(_T_10520, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10523 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_10524 = not(_T_10523) @[RegMapper.scala 138:44] + node _T_10526 = eq(_T_10524, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10527 = and(_T_1958[166], _T_10515) @[RegMapper.scala 140:69] + node _T_10528 = and(_T_3086[166], _T_10522) @[RegMapper.scala 140:91] + node _T_10531 = and(_T_2146[166], _T_10519) @[RegMapper.scala 141:62] + node _T_10532 = and(_T_3274[166], _T_10526) @[RegMapper.scala 141:84] + node _T_10533 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + node _T_10537 = eq(_T_10515, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10538 = or(UInt<1>("h01"), _T_10537) @[RegMapper.scala 142:31] + _T_2334[166] <= _T_10538 @[RegMapper.scala 142:18] + node _T_10540 = eq(_T_10519, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10541 = or(UInt<1>("h01"), _T_10540) @[RegMapper.scala 143:31] + _T_2522[166] <= _T_10541 @[RegMapper.scala 143:18] + node _T_10543 = eq(_T_10522, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10544 = or(UInt<1>("h01"), _T_10543) @[RegMapper.scala 144:31] + _T_2710[166] <= _T_10544 @[RegMapper.scala 144:18] + node _T_10546 = eq(_T_10526, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10547 = or(UInt<1>("h01"), _T_10546) @[RegMapper.scala 145:31] + _T_2898[166] <= _T_10547 @[RegMapper.scala 145:18] + node _T_10548 = shl(UInt<7>("h073"), 0) @[RegMapper.scala 150:47] + node _T_10550 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_10551 = and(_T_10548, _T_10550) @[RegMapper.scala 150:55] + node _T_10552 = or(UInt<1>("h00"), _T_10551) @[RegMapper.scala 150:35] + node _T_10553 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_10555 = neq(_T_10553, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10556 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_10557 = not(_T_10556) @[RegMapper.scala 136:45] + node _T_10559 = eq(_T_10557, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10560 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_10562 = neq(_T_10560, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10563 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_10564 = not(_T_10563) @[RegMapper.scala 138:44] + node _T_10566 = eq(_T_10564, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10567 = and(_T_1958[167], _T_10555) @[RegMapper.scala 140:69] + node _T_10568 = and(_T_3086[167], _T_10562) @[RegMapper.scala 140:91] + node _T_10571 = and(_T_2146[167], _T_10559) @[RegMapper.scala 141:62] + node _T_10572 = and(_T_3274[167], _T_10566) @[RegMapper.scala 141:84] + node _T_10573 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + node _T_10577 = eq(_T_10555, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10578 = or(UInt<1>("h01"), _T_10577) @[RegMapper.scala 142:31] + _T_2334[167] <= _T_10578 @[RegMapper.scala 142:18] + node _T_10580 = eq(_T_10559, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10581 = or(UInt<1>("h01"), _T_10580) @[RegMapper.scala 143:31] + _T_2522[167] <= _T_10581 @[RegMapper.scala 143:18] + node _T_10583 = eq(_T_10562, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10584 = or(UInt<1>("h01"), _T_10583) @[RegMapper.scala 144:31] + _T_2710[167] <= _T_10584 @[RegMapper.scala 144:18] + node _T_10586 = eq(_T_10566, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10587 = or(UInt<1>("h01"), _T_10586) @[RegMapper.scala 145:31] + _T_2898[167] <= _T_10587 @[RegMapper.scala 145:18] + node _T_10588 = shl(UInt<7>("h060"), 8) @[RegMapper.scala 150:47] + node _T_10590 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_10591 = and(_T_10588, _T_10590) @[RegMapper.scala 150:55] + node _T_10592 = or(_T_10552, _T_10591) @[RegMapper.scala 150:35] + node _T_10593 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_10595 = neq(_T_10593, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10596 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_10597 = not(_T_10596) @[RegMapper.scala 136:45] + node _T_10599 = eq(_T_10597, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10600 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_10602 = neq(_T_10600, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10603 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_10604 = not(_T_10603) @[RegMapper.scala 138:44] + node _T_10606 = eq(_T_10604, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10607 = and(_T_1958[168], _T_10595) @[RegMapper.scala 140:69] + node _T_10608 = and(_T_3086[168], _T_10602) @[RegMapper.scala 140:91] + node _T_10611 = and(_T_2146[168], _T_10599) @[RegMapper.scala 141:62] + node _T_10612 = and(_T_3274[168], _T_10606) @[RegMapper.scala 141:84] + node _T_10613 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + node _T_10617 = eq(_T_10595, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10618 = or(UInt<1>("h01"), _T_10617) @[RegMapper.scala 142:31] + _T_2334[168] <= _T_10618 @[RegMapper.scala 142:18] + node _T_10620 = eq(_T_10599, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10621 = or(UInt<1>("h01"), _T_10620) @[RegMapper.scala 143:31] + _T_2522[168] <= _T_10621 @[RegMapper.scala 143:18] + node _T_10623 = eq(_T_10602, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10624 = or(UInt<1>("h01"), _T_10623) @[RegMapper.scala 144:31] + _T_2710[168] <= _T_10624 @[RegMapper.scala 144:18] + node _T_10626 = eq(_T_10606, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10627 = or(UInt<1>("h01"), _T_10626) @[RegMapper.scala 145:31] + _T_2898[168] <= _T_10627 @[RegMapper.scala 145:18] + node _T_10628 = shl(UInt<3>("h04"), 16) @[RegMapper.scala 150:47] + node _T_10630 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_10631 = and(_T_10628, _T_10630) @[RegMapper.scala 150:55] + node _T_10632 = or(_T_10592, _T_10631) @[RegMapper.scala 150:35] + node _T_10633 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_10635 = neq(_T_10633, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10636 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_10637 = not(_T_10636) @[RegMapper.scala 136:45] + node _T_10639 = eq(_T_10637, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10640 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_10642 = neq(_T_10640, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10643 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_10644 = not(_T_10643) @[RegMapper.scala 138:44] + node _T_10646 = eq(_T_10644, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10647 = and(_T_1958[169], _T_10635) @[RegMapper.scala 140:69] + node _T_10648 = and(_T_3086[169], _T_10642) @[RegMapper.scala 140:91] + node _T_10651 = and(_T_2146[169], _T_10639) @[RegMapper.scala 141:62] + node _T_10652 = and(_T_3274[169], _T_10646) @[RegMapper.scala 141:84] + node _T_10653 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + node _T_10657 = eq(_T_10635, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10658 = or(UInt<1>("h01"), _T_10657) @[RegMapper.scala 142:31] + _T_2334[169] <= _T_10658 @[RegMapper.scala 142:18] + node _T_10660 = eq(_T_10639, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10661 = or(UInt<1>("h01"), _T_10660) @[RegMapper.scala 143:31] + _T_2522[169] <= _T_10661 @[RegMapper.scala 143:18] + node _T_10663 = eq(_T_10642, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10664 = or(UInt<1>("h01"), _T_10663) @[RegMapper.scala 144:31] + _T_2710[169] <= _T_10664 @[RegMapper.scala 144:18] + node _T_10666 = eq(_T_10646, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10667 = or(UInt<1>("h01"), _T_10666) @[RegMapper.scala 145:31] + _T_2898[169] <= _T_10667 @[RegMapper.scala 145:18] + node _T_10668 = shl(UInt<7>("h07b"), 24) @[RegMapper.scala 150:47] + node _T_10670 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_10671 = and(_T_10668, _T_10670) @[RegMapper.scala 150:55] + node _T_10672 = or(_T_10632, _T_10671) @[RegMapper.scala 150:35] + node _T_10673 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_10675 = neq(_T_10673, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10676 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_10677 = not(_T_10676) @[RegMapper.scala 136:45] + node _T_10679 = eq(_T_10677, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10680 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_10682 = neq(_T_10680, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10683 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_10684 = not(_T_10683) @[RegMapper.scala 138:44] + node _T_10686 = eq(_T_10684, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10687 = and(_T_1958[170], _T_10675) @[RegMapper.scala 140:69] + node _T_10688 = and(_T_3086[170], _T_10682) @[RegMapper.scala 140:91] + node _T_10691 = and(_T_2146[170], _T_10679) @[RegMapper.scala 141:62] + node _T_10692 = and(_T_3274[170], _T_10686) @[RegMapper.scala 141:84] + node _T_10693 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + node _T_10697 = eq(_T_10675, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10698 = or(UInt<1>("h01"), _T_10697) @[RegMapper.scala 142:31] + _T_2334[170] <= _T_10698 @[RegMapper.scala 142:18] + node _T_10700 = eq(_T_10679, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10701 = or(UInt<1>("h01"), _T_10700) @[RegMapper.scala 143:31] + _T_2522[170] <= _T_10701 @[RegMapper.scala 143:18] + node _T_10703 = eq(_T_10682, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10704 = or(UInt<1>("h01"), _T_10703) @[RegMapper.scala 144:31] + _T_2710[170] <= _T_10704 @[RegMapper.scala 144:18] + node _T_10706 = eq(_T_10686, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10707 = or(UInt<1>("h01"), _T_10706) @[RegMapper.scala 145:31] + _T_2898[170] <= _T_10707 @[RegMapper.scala 145:18] + node _T_10708 = shl(UInt<7>("h073"), 32) @[RegMapper.scala 150:47] + node _T_10710 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_10711 = and(_T_10708, _T_10710) @[RegMapper.scala 150:55] + node _T_10712 = or(_T_10672, _T_10711) @[RegMapper.scala 150:35] + node _T_10713 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_10715 = neq(_T_10713, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10716 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_10717 = not(_T_10716) @[RegMapper.scala 136:45] + node _T_10719 = eq(_T_10717, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10720 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_10722 = neq(_T_10720, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10723 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_10724 = not(_T_10723) @[RegMapper.scala 138:44] + node _T_10726 = eq(_T_10724, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10727 = and(_T_1958[171], _T_10715) @[RegMapper.scala 140:69] + node _T_10728 = and(_T_3086[171], _T_10722) @[RegMapper.scala 140:91] + node _T_10731 = and(_T_2146[171], _T_10719) @[RegMapper.scala 141:62] + node _T_10732 = and(_T_3274[171], _T_10726) @[RegMapper.scala 141:84] + node _T_10733 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + node _T_10737 = eq(_T_10715, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10738 = or(UInt<1>("h01"), _T_10737) @[RegMapper.scala 142:31] + _T_2334[171] <= _T_10738 @[RegMapper.scala 142:18] + node _T_10740 = eq(_T_10719, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10741 = or(UInt<1>("h01"), _T_10740) @[RegMapper.scala 143:31] + _T_2522[171] <= _T_10741 @[RegMapper.scala 143:18] + node _T_10743 = eq(_T_10722, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10744 = or(UInt<1>("h01"), _T_10743) @[RegMapper.scala 144:31] + _T_2710[171] <= _T_10744 @[RegMapper.scala 144:18] + node _T_10746 = eq(_T_10726, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10747 = or(UInt<1>("h01"), _T_10746) @[RegMapper.scala 145:31] + _T_2898[171] <= _T_10747 @[RegMapper.scala 145:18] + node _T_10748 = shl(UInt<6>("h024"), 40) @[RegMapper.scala 150:47] + node _T_10750 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_10751 = and(_T_10748, _T_10750) @[RegMapper.scala 150:55] + node _T_10752 = or(_T_10712, _T_10751) @[RegMapper.scala 150:35] + node _T_10753 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_10755 = neq(_T_10753, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10756 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_10757 = not(_T_10756) @[RegMapper.scala 136:45] + node _T_10759 = eq(_T_10757, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10760 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_10762 = neq(_T_10760, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10763 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_10764 = not(_T_10763) @[RegMapper.scala 138:44] + node _T_10766 = eq(_T_10764, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10767 = and(_T_1958[172], _T_10755) @[RegMapper.scala 140:69] + node _T_10768 = and(_T_3086[172], _T_10762) @[RegMapper.scala 140:91] + node _T_10771 = and(_T_2146[172], _T_10759) @[RegMapper.scala 141:62] + node _T_10772 = and(_T_3274[172], _T_10766) @[RegMapper.scala 141:84] + node _T_10773 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + node _T_10777 = eq(_T_10755, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10778 = or(UInt<1>("h01"), _T_10777) @[RegMapper.scala 142:31] + _T_2334[172] <= _T_10778 @[RegMapper.scala 142:18] + node _T_10780 = eq(_T_10759, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10781 = or(UInt<1>("h01"), _T_10780) @[RegMapper.scala 143:31] + _T_2522[172] <= _T_10781 @[RegMapper.scala 143:18] + node _T_10783 = eq(_T_10762, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10784 = or(UInt<1>("h01"), _T_10783) @[RegMapper.scala 144:31] + _T_2710[172] <= _T_10784 @[RegMapper.scala 144:18] + node _T_10786 = eq(_T_10766, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10787 = or(UInt<1>("h01"), _T_10786) @[RegMapper.scala 145:31] + _T_2898[172] <= _T_10787 @[RegMapper.scala 145:18] + node _T_10788 = shl(UInt<1>("h00"), 48) @[RegMapper.scala 150:47] + node _T_10790 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_10791 = and(_T_10788, _T_10790) @[RegMapper.scala 150:55] + node _T_10792 = or(_T_10752, _T_10791) @[RegMapper.scala 150:35] + node _T_10793 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_10795 = neq(_T_10793, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10796 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_10797 = not(_T_10796) @[RegMapper.scala 136:45] + node _T_10799 = eq(_T_10797, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10800 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_10802 = neq(_T_10800, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10803 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_10804 = not(_T_10803) @[RegMapper.scala 138:44] + node _T_10806 = eq(_T_10804, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10807 = and(_T_1958[173], _T_10795) @[RegMapper.scala 140:69] + node _T_10808 = and(_T_3086[173], _T_10802) @[RegMapper.scala 140:91] + node _T_10811 = and(_T_2146[173], _T_10799) @[RegMapper.scala 141:62] + node _T_10812 = and(_T_3274[173], _T_10806) @[RegMapper.scala 141:84] + node _T_10813 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + node _T_10817 = eq(_T_10795, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10818 = or(UInt<1>("h01"), _T_10817) @[RegMapper.scala 142:31] + _T_2334[173] <= _T_10818 @[RegMapper.scala 142:18] + node _T_10820 = eq(_T_10799, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10821 = or(UInt<1>("h01"), _T_10820) @[RegMapper.scala 143:31] + _T_2522[173] <= _T_10821 @[RegMapper.scala 143:18] + node _T_10823 = eq(_T_10802, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10824 = or(UInt<1>("h01"), _T_10823) @[RegMapper.scala 144:31] + _T_2710[173] <= _T_10824 @[RegMapper.scala 144:18] + node _T_10826 = eq(_T_10806, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10827 = or(UInt<1>("h01"), _T_10826) @[RegMapper.scala 145:31] + _T_2898[173] <= _T_10827 @[RegMapper.scala 145:18] + node _T_10828 = shl(UInt<7>("h07b"), 56) @[RegMapper.scala 150:47] + node _T_10830 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_10831 = and(_T_10828, _T_10830) @[RegMapper.scala 150:55] + node _T_10832 = or(_T_10792, _T_10831) @[RegMapper.scala 150:35] + node _T_10833 = bits(_T_3825, 7, 0) @[RegMapper.scala 135:29] + node _T_10835 = neq(_T_10833, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10836 = bits(_T_3825, 7, 0) @[RegMapper.scala 136:29] + node _T_10837 = not(_T_10836) @[RegMapper.scala 136:45] + node _T_10839 = eq(_T_10837, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10840 = bits(_T_3872, 7, 0) @[RegMapper.scala 137:28] + node _T_10842 = neq(_T_10840, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10843 = bits(_T_3872, 7, 0) @[RegMapper.scala 138:28] + node _T_10844 = not(_T_10843) @[RegMapper.scala 138:44] + node _T_10846 = eq(_T_10844, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10847 = and(_T_1958[174], _T_10835) @[RegMapper.scala 140:69] + node _T_10848 = and(_T_3086[174], _T_10842) @[RegMapper.scala 140:91] + node _T_10851 = and(_T_2146[174], _T_10839) @[RegMapper.scala 141:62] + node _T_10852 = and(_T_3274[174], _T_10846) @[RegMapper.scala 141:84] + node _T_10853 = bits(_T_1583.bits.data, 7, 0) @[RegMapper.scala 141:99] + when _T_10852 : @[RegField.scala 70:88] + ramMem[24] <= _T_10853 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_10857 = eq(_T_10835, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10858 = or(UInt<1>("h01"), _T_10857) @[RegMapper.scala 142:31] + _T_2334[174] <= _T_10858 @[RegMapper.scala 142:18] + node _T_10860 = eq(_T_10839, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10861 = or(UInt<1>("h01"), _T_10860) @[RegMapper.scala 143:31] + _T_2522[174] <= _T_10861 @[RegMapper.scala 143:18] + node _T_10863 = eq(_T_10842, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10864 = or(UInt<1>("h01"), _T_10863) @[RegMapper.scala 144:31] + _T_2710[174] <= _T_10864 @[RegMapper.scala 144:18] + node _T_10866 = eq(_T_10846, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10867 = or(UInt<1>("h01"), _T_10866) @[RegMapper.scala 145:31] + _T_2898[174] <= _T_10867 @[RegMapper.scala 145:18] + node _T_10868 = shl(ramMem[24], 0) @[RegMapper.scala 150:47] + node _T_10870 = not(UInt<8>("h00")) @[RegMapper.scala 150:58] + node _T_10871 = and(_T_10868, _T_10870) @[RegMapper.scala 150:55] + node _T_10872 = or(UInt<1>("h00"), _T_10871) @[RegMapper.scala 150:35] + node _T_10873 = bits(_T_3825, 15, 8) @[RegMapper.scala 135:29] + node _T_10875 = neq(_T_10873, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10876 = bits(_T_3825, 15, 8) @[RegMapper.scala 136:29] + node _T_10877 = not(_T_10876) @[RegMapper.scala 136:45] + node _T_10879 = eq(_T_10877, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10880 = bits(_T_3872, 15, 8) @[RegMapper.scala 137:28] + node _T_10882 = neq(_T_10880, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10883 = bits(_T_3872, 15, 8) @[RegMapper.scala 138:28] + node _T_10884 = not(_T_10883) @[RegMapper.scala 138:44] + node _T_10886 = eq(_T_10884, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10887 = and(_T_1958[175], _T_10875) @[RegMapper.scala 140:69] + node _T_10888 = and(_T_3086[175], _T_10882) @[RegMapper.scala 140:91] + node _T_10891 = and(_T_2146[175], _T_10879) @[RegMapper.scala 141:62] + node _T_10892 = and(_T_3274[175], _T_10886) @[RegMapper.scala 141:84] + node _T_10893 = bits(_T_1583.bits.data, 15, 8) @[RegMapper.scala 141:99] + when _T_10892 : @[RegField.scala 70:88] + ramMem[25] <= _T_10893 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_10897 = eq(_T_10875, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10898 = or(UInt<1>("h01"), _T_10897) @[RegMapper.scala 142:31] + _T_2334[175] <= _T_10898 @[RegMapper.scala 142:18] + node _T_10900 = eq(_T_10879, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10901 = or(UInt<1>("h01"), _T_10900) @[RegMapper.scala 143:31] + _T_2522[175] <= _T_10901 @[RegMapper.scala 143:18] + node _T_10903 = eq(_T_10882, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10904 = or(UInt<1>("h01"), _T_10903) @[RegMapper.scala 144:31] + _T_2710[175] <= _T_10904 @[RegMapper.scala 144:18] + node _T_10906 = eq(_T_10886, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10907 = or(UInt<1>("h01"), _T_10906) @[RegMapper.scala 145:31] + _T_2898[175] <= _T_10907 @[RegMapper.scala 145:18] + node _T_10908 = shl(ramMem[25], 8) @[RegMapper.scala 150:47] + node _T_10910 = not(UInt<16>("h00")) @[RegMapper.scala 150:58] + node _T_10911 = and(_T_10908, _T_10910) @[RegMapper.scala 150:55] + node _T_10912 = or(_T_10872, _T_10911) @[RegMapper.scala 150:35] + node _T_10913 = bits(_T_3825, 23, 16) @[RegMapper.scala 135:29] + node _T_10915 = neq(_T_10913, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10916 = bits(_T_3825, 23, 16) @[RegMapper.scala 136:29] + node _T_10917 = not(_T_10916) @[RegMapper.scala 136:45] + node _T_10919 = eq(_T_10917, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10920 = bits(_T_3872, 23, 16) @[RegMapper.scala 137:28] + node _T_10922 = neq(_T_10920, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10923 = bits(_T_3872, 23, 16) @[RegMapper.scala 138:28] + node _T_10924 = not(_T_10923) @[RegMapper.scala 138:44] + node _T_10926 = eq(_T_10924, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10927 = and(_T_1958[176], _T_10915) @[RegMapper.scala 140:69] + node _T_10928 = and(_T_3086[176], _T_10922) @[RegMapper.scala 140:91] + node _T_10931 = and(_T_2146[176], _T_10919) @[RegMapper.scala 141:62] + node _T_10932 = and(_T_3274[176], _T_10926) @[RegMapper.scala 141:84] + node _T_10933 = bits(_T_1583.bits.data, 23, 16) @[RegMapper.scala 141:99] + when _T_10932 : @[RegField.scala 70:88] + ramMem[26] <= _T_10933 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_10937 = eq(_T_10915, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10938 = or(UInt<1>("h01"), _T_10937) @[RegMapper.scala 142:31] + _T_2334[176] <= _T_10938 @[RegMapper.scala 142:18] + node _T_10940 = eq(_T_10919, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10941 = or(UInt<1>("h01"), _T_10940) @[RegMapper.scala 143:31] + _T_2522[176] <= _T_10941 @[RegMapper.scala 143:18] + node _T_10943 = eq(_T_10922, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10944 = or(UInt<1>("h01"), _T_10943) @[RegMapper.scala 144:31] + _T_2710[176] <= _T_10944 @[RegMapper.scala 144:18] + node _T_10946 = eq(_T_10926, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10947 = or(UInt<1>("h01"), _T_10946) @[RegMapper.scala 145:31] + _T_2898[176] <= _T_10947 @[RegMapper.scala 145:18] + node _T_10948 = shl(ramMem[26], 16) @[RegMapper.scala 150:47] + node _T_10950 = not(UInt<24>("h00")) @[RegMapper.scala 150:58] + node _T_10951 = and(_T_10948, _T_10950) @[RegMapper.scala 150:55] + node _T_10952 = or(_T_10912, _T_10951) @[RegMapper.scala 150:35] + node _T_10953 = bits(_T_3825, 31, 24) @[RegMapper.scala 135:29] + node _T_10955 = neq(_T_10953, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10956 = bits(_T_3825, 31, 24) @[RegMapper.scala 136:29] + node _T_10957 = not(_T_10956) @[RegMapper.scala 136:45] + node _T_10959 = eq(_T_10957, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_10960 = bits(_T_3872, 31, 24) @[RegMapper.scala 137:28] + node _T_10962 = neq(_T_10960, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_10963 = bits(_T_3872, 31, 24) @[RegMapper.scala 138:28] + node _T_10964 = not(_T_10963) @[RegMapper.scala 138:44] + node _T_10966 = eq(_T_10964, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_10967 = and(_T_1958[177], _T_10955) @[RegMapper.scala 140:69] + node _T_10968 = and(_T_3086[177], _T_10962) @[RegMapper.scala 140:91] + node _T_10971 = and(_T_2146[177], _T_10959) @[RegMapper.scala 141:62] + node _T_10972 = and(_T_3274[177], _T_10966) @[RegMapper.scala 141:84] + node _T_10973 = bits(_T_1583.bits.data, 31, 24) @[RegMapper.scala 141:99] + when _T_10972 : @[RegField.scala 70:88] + ramMem[27] <= _T_10973 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_10977 = eq(_T_10955, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_10978 = or(UInt<1>("h01"), _T_10977) @[RegMapper.scala 142:31] + _T_2334[177] <= _T_10978 @[RegMapper.scala 142:18] + node _T_10980 = eq(_T_10959, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_10981 = or(UInt<1>("h01"), _T_10980) @[RegMapper.scala 143:31] + _T_2522[177] <= _T_10981 @[RegMapper.scala 143:18] + node _T_10983 = eq(_T_10962, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_10984 = or(UInt<1>("h01"), _T_10983) @[RegMapper.scala 144:31] + _T_2710[177] <= _T_10984 @[RegMapper.scala 144:18] + node _T_10986 = eq(_T_10966, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_10987 = or(UInt<1>("h01"), _T_10986) @[RegMapper.scala 145:31] + _T_2898[177] <= _T_10987 @[RegMapper.scala 145:18] + node _T_10988 = shl(ramMem[27], 24) @[RegMapper.scala 150:47] + node _T_10990 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_10991 = and(_T_10988, _T_10990) @[RegMapper.scala 150:55] + node _T_10992 = or(_T_10952, _T_10991) @[RegMapper.scala 150:35] + node _T_10993 = bits(_T_3825, 39, 32) @[RegMapper.scala 135:29] + node _T_10995 = neq(_T_10993, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_10996 = bits(_T_3825, 39, 32) @[RegMapper.scala 136:29] + node _T_10997 = not(_T_10996) @[RegMapper.scala 136:45] + node _T_10999 = eq(_T_10997, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_11000 = bits(_T_3872, 39, 32) @[RegMapper.scala 137:28] + node _T_11002 = neq(_T_11000, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_11003 = bits(_T_3872, 39, 32) @[RegMapper.scala 138:28] + node _T_11004 = not(_T_11003) @[RegMapper.scala 138:44] + node _T_11006 = eq(_T_11004, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_11007 = and(_T_1958[178], _T_10995) @[RegMapper.scala 140:69] + node _T_11008 = and(_T_3086[178], _T_11002) @[RegMapper.scala 140:91] + node _T_11011 = and(_T_2146[178], _T_10999) @[RegMapper.scala 141:62] + node _T_11012 = and(_T_3274[178], _T_11006) @[RegMapper.scala 141:84] + node _T_11013 = bits(_T_1583.bits.data, 39, 32) @[RegMapper.scala 141:99] + when _T_11012 : @[RegField.scala 70:88] + ramMem[28] <= _T_11013 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_11017 = eq(_T_10995, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_11018 = or(UInt<1>("h01"), _T_11017) @[RegMapper.scala 142:31] + _T_2334[178] <= _T_11018 @[RegMapper.scala 142:18] + node _T_11020 = eq(_T_10999, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_11021 = or(UInt<1>("h01"), _T_11020) @[RegMapper.scala 143:31] + _T_2522[178] <= _T_11021 @[RegMapper.scala 143:18] + node _T_11023 = eq(_T_11002, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_11024 = or(UInt<1>("h01"), _T_11023) @[RegMapper.scala 144:31] + _T_2710[178] <= _T_11024 @[RegMapper.scala 144:18] + node _T_11026 = eq(_T_11006, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_11027 = or(UInt<1>("h01"), _T_11026) @[RegMapper.scala 145:31] + _T_2898[178] <= _T_11027 @[RegMapper.scala 145:18] + node _T_11028 = shl(ramMem[28], 32) @[RegMapper.scala 150:47] + node _T_11030 = not(UInt<40>("h00")) @[RegMapper.scala 150:58] + node _T_11031 = and(_T_11028, _T_11030) @[RegMapper.scala 150:55] + node _T_11032 = or(_T_10992, _T_11031) @[RegMapper.scala 150:35] + node _T_11033 = bits(_T_3825, 47, 40) @[RegMapper.scala 135:29] + node _T_11035 = neq(_T_11033, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_11036 = bits(_T_3825, 47, 40) @[RegMapper.scala 136:29] + node _T_11037 = not(_T_11036) @[RegMapper.scala 136:45] + node _T_11039 = eq(_T_11037, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_11040 = bits(_T_3872, 47, 40) @[RegMapper.scala 137:28] + node _T_11042 = neq(_T_11040, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_11043 = bits(_T_3872, 47, 40) @[RegMapper.scala 138:28] + node _T_11044 = not(_T_11043) @[RegMapper.scala 138:44] + node _T_11046 = eq(_T_11044, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_11047 = and(_T_1958[179], _T_11035) @[RegMapper.scala 140:69] + node _T_11048 = and(_T_3086[179], _T_11042) @[RegMapper.scala 140:91] + node _T_11051 = and(_T_2146[179], _T_11039) @[RegMapper.scala 141:62] + node _T_11052 = and(_T_3274[179], _T_11046) @[RegMapper.scala 141:84] + node _T_11053 = bits(_T_1583.bits.data, 47, 40) @[RegMapper.scala 141:99] + when _T_11052 : @[RegField.scala 70:88] + ramMem[29] <= _T_11053 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_11057 = eq(_T_11035, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_11058 = or(UInt<1>("h01"), _T_11057) @[RegMapper.scala 142:31] + _T_2334[179] <= _T_11058 @[RegMapper.scala 142:18] + node _T_11060 = eq(_T_11039, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_11061 = or(UInt<1>("h01"), _T_11060) @[RegMapper.scala 143:31] + _T_2522[179] <= _T_11061 @[RegMapper.scala 143:18] + node _T_11063 = eq(_T_11042, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_11064 = or(UInt<1>("h01"), _T_11063) @[RegMapper.scala 144:31] + _T_2710[179] <= _T_11064 @[RegMapper.scala 144:18] + node _T_11066 = eq(_T_11046, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_11067 = or(UInt<1>("h01"), _T_11066) @[RegMapper.scala 145:31] + _T_2898[179] <= _T_11067 @[RegMapper.scala 145:18] + node _T_11068 = shl(ramMem[29], 40) @[RegMapper.scala 150:47] + node _T_11070 = not(UInt<48>("h00")) @[RegMapper.scala 150:58] + node _T_11071 = and(_T_11068, _T_11070) @[RegMapper.scala 150:55] + node _T_11072 = or(_T_11032, _T_11071) @[RegMapper.scala 150:35] + node _T_11073 = bits(_T_3825, 55, 48) @[RegMapper.scala 135:29] + node _T_11075 = neq(_T_11073, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_11076 = bits(_T_3825, 55, 48) @[RegMapper.scala 136:29] + node _T_11077 = not(_T_11076) @[RegMapper.scala 136:45] + node _T_11079 = eq(_T_11077, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_11080 = bits(_T_3872, 55, 48) @[RegMapper.scala 137:28] + node _T_11082 = neq(_T_11080, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_11083 = bits(_T_3872, 55, 48) @[RegMapper.scala 138:28] + node _T_11084 = not(_T_11083) @[RegMapper.scala 138:44] + node _T_11086 = eq(_T_11084, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_11087 = and(_T_1958[180], _T_11075) @[RegMapper.scala 140:69] + node _T_11088 = and(_T_3086[180], _T_11082) @[RegMapper.scala 140:91] + node _T_11091 = and(_T_2146[180], _T_11079) @[RegMapper.scala 141:62] + node _T_11092 = and(_T_3274[180], _T_11086) @[RegMapper.scala 141:84] + node _T_11093 = bits(_T_1583.bits.data, 55, 48) @[RegMapper.scala 141:99] + when _T_11092 : @[RegField.scala 70:88] + ramMem[30] <= _T_11093 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_11097 = eq(_T_11075, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_11098 = or(UInt<1>("h01"), _T_11097) @[RegMapper.scala 142:31] + _T_2334[180] <= _T_11098 @[RegMapper.scala 142:18] + node _T_11100 = eq(_T_11079, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_11101 = or(UInt<1>("h01"), _T_11100) @[RegMapper.scala 143:31] + _T_2522[180] <= _T_11101 @[RegMapper.scala 143:18] + node _T_11103 = eq(_T_11082, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_11104 = or(UInt<1>("h01"), _T_11103) @[RegMapper.scala 144:31] + _T_2710[180] <= _T_11104 @[RegMapper.scala 144:18] + node _T_11106 = eq(_T_11086, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_11107 = or(UInt<1>("h01"), _T_11106) @[RegMapper.scala 145:31] + _T_2898[180] <= _T_11107 @[RegMapper.scala 145:18] + node _T_11108 = shl(ramMem[30], 48) @[RegMapper.scala 150:47] + node _T_11110 = not(UInt<56>("h00")) @[RegMapper.scala 150:58] + node _T_11111 = and(_T_11108, _T_11110) @[RegMapper.scala 150:55] + node _T_11112 = or(_T_11072, _T_11111) @[RegMapper.scala 150:35] + node _T_11113 = bits(_T_3825, 63, 56) @[RegMapper.scala 135:29] + node _T_11115 = neq(_T_11113, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_11116 = bits(_T_3825, 63, 56) @[RegMapper.scala 136:29] + node _T_11117 = not(_T_11116) @[RegMapper.scala 136:45] + node _T_11119 = eq(_T_11117, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_11120 = bits(_T_3872, 63, 56) @[RegMapper.scala 137:28] + node _T_11122 = neq(_T_11120, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_11123 = bits(_T_3872, 63, 56) @[RegMapper.scala 138:28] + node _T_11124 = not(_T_11123) @[RegMapper.scala 138:44] + node _T_11126 = eq(_T_11124, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_11127 = and(_T_1958[181], _T_11115) @[RegMapper.scala 140:69] + node _T_11128 = and(_T_3086[181], _T_11122) @[RegMapper.scala 140:91] + node _T_11131 = and(_T_2146[181], _T_11119) @[RegMapper.scala 141:62] + node _T_11132 = and(_T_3274[181], _T_11126) @[RegMapper.scala 141:84] + node _T_11133 = bits(_T_1583.bits.data, 63, 56) @[RegMapper.scala 141:99] + when _T_11132 : @[RegField.scala 70:88] + ramMem[31] <= _T_11133 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_11137 = eq(_T_11115, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_11138 = or(UInt<1>("h01"), _T_11137) @[RegMapper.scala 142:31] + _T_2334[181] <= _T_11138 @[RegMapper.scala 142:18] + node _T_11140 = eq(_T_11119, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_11141 = or(UInt<1>("h01"), _T_11140) @[RegMapper.scala 143:31] + _T_2522[181] <= _T_11141 @[RegMapper.scala 143:18] + node _T_11143 = eq(_T_11122, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_11144 = or(UInt<1>("h01"), _T_11143) @[RegMapper.scala 144:31] + _T_2710[181] <= _T_11144 @[RegMapper.scala 144:18] + node _T_11146 = eq(_T_11126, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_11147 = or(UInt<1>("h01"), _T_11146) @[RegMapper.scala 145:31] + _T_2898[181] <= _T_11147 @[RegMapper.scala 145:18] + node _T_11148 = shl(ramMem[31], 56) @[RegMapper.scala 150:47] + node _T_11150 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_11151 = and(_T_11148, _T_11150) @[RegMapper.scala 150:55] + node _T_11152 = or(_T_11112, _T_11151) @[RegMapper.scala 150:35] + node _T_11154 = eq(_T_1842, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11155 = and(_T_2334[92], _T_2334[91]) @[RegMapper.scala 154:98] + node _T_11156 = and(_T_11155, _T_2334[90]) @[RegMapper.scala 154:98] + node _T_11157 = and(_T_11156, _T_2334[89]) @[RegMapper.scala 154:98] + node _T_11158 = and(_T_11157, _T_2334[88]) @[RegMapper.scala 154:98] + node _T_11159 = and(_T_11158, _T_2334[87]) @[RegMapper.scala 154:98] + node _T_11160 = and(_T_11159, _T_2334[86]) @[RegMapper.scala 154:98] + node _T_11161 = and(_T_11160, _T_2334[85]) @[RegMapper.scala 154:98] + node _T_11162 = and(_T_11161, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11163 = or(_T_11154, _T_11162) @[RegMapper.scala 154:82] + node _T_11165 = eq(_T_1824, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11166 = and(_T_2334[76], _T_2334[75]) @[RegMapper.scala 154:98] + node _T_11167 = and(_T_11166, _T_2334[74]) @[RegMapper.scala 154:98] + node _T_11168 = and(_T_11167, _T_2334[73]) @[RegMapper.scala 154:98] + node _T_11169 = and(_T_11168, _T_2334[72]) @[RegMapper.scala 154:98] + node _T_11170 = and(_T_11169, _T_2334[71]) @[RegMapper.scala 154:98] + node _T_11171 = and(_T_11170, _T_2334[70]) @[RegMapper.scala 154:98] + node _T_11172 = and(_T_11171, _T_2334[69]) @[RegMapper.scala 154:98] + node _T_11173 = and(_T_11172, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11174 = or(_T_11165, _T_11173) @[RegMapper.scala 154:82] + node _T_11176 = eq(_T_1887, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11177 = and(_T_2334[125], _T_2334[124]) @[RegMapper.scala 154:98] + node _T_11178 = and(_T_11177, _T_2334[123]) @[RegMapper.scala 154:98] + node _T_11179 = and(_T_11178, _T_2334[122]) @[RegMapper.scala 154:98] + node _T_11180 = and(_T_11179, _T_2334[121]) @[RegMapper.scala 154:98] + node _T_11181 = and(_T_11180, _T_2334[120]) @[RegMapper.scala 154:98] + node _T_11182 = and(_T_11181, _T_2334[119]) @[RegMapper.scala 154:98] + node _T_11183 = and(_T_11182, _T_2334[118]) @[RegMapper.scala 154:98] + node _T_11184 = and(_T_11183, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11185 = or(_T_11176, _T_11184) @[RegMapper.scala 154:82] + node _T_11187 = eq(_T_1950, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11188 = and(_T_2334[181], _T_2334[180]) @[RegMapper.scala 154:98] + node _T_11189 = and(_T_11188, _T_2334[179]) @[RegMapper.scala 154:98] + node _T_11190 = and(_T_11189, _T_2334[178]) @[RegMapper.scala 154:98] + node _T_11191 = and(_T_11190, _T_2334[177]) @[RegMapper.scala 154:98] + node _T_11192 = and(_T_11191, _T_2334[176]) @[RegMapper.scala 154:98] + node _T_11193 = and(_T_11192, _T_2334[175]) @[RegMapper.scala 154:98] + node _T_11194 = and(_T_11193, _T_2334[174]) @[RegMapper.scala 154:98] + node _T_11195 = and(_T_11194, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11196 = or(_T_11187, _T_11195) @[RegMapper.scala 154:82] + node _T_11198 = eq(_T_1761, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11199 = and(_T_2334[31], _T_2334[30]) @[RegMapper.scala 154:98] + node _T_11200 = and(_T_11199, _T_2334[29]) @[RegMapper.scala 154:98] + node _T_11201 = and(_T_11200, _T_2334[28]) @[RegMapper.scala 154:98] + node _T_11202 = and(_T_11201, _T_2334[27]) @[RegMapper.scala 154:98] + node _T_11203 = and(_T_11202, _T_2334[26]) @[RegMapper.scala 154:98] + node _T_11204 = and(_T_11203, _T_2334[25]) @[RegMapper.scala 154:98] + node _T_11205 = and(_T_11204, _T_2334[24]) @[RegMapper.scala 154:98] + node _T_11206 = and(_T_11205, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11207 = or(_T_11198, _T_11206) @[RegMapper.scala 154:82] + node _T_11209 = eq(_T_1770, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11210 = and(_T_2334[39], _T_2334[38]) @[RegMapper.scala 154:98] + node _T_11211 = and(_T_11210, _T_2334[37]) @[RegMapper.scala 154:98] + node _T_11212 = and(_T_11211, _T_2334[36]) @[RegMapper.scala 154:98] + node _T_11213 = and(_T_11212, _T_2334[35]) @[RegMapper.scala 154:98] + node _T_11214 = and(_T_11213, _T_2334[34]) @[RegMapper.scala 154:98] + node _T_11215 = and(_T_11214, _T_2334[33]) @[RegMapper.scala 154:98] + node _T_11216 = and(_T_11215, _T_2334[32]) @[RegMapper.scala 154:98] + node _T_11217 = and(_T_11216, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11218 = or(_T_11209, _T_11217) @[RegMapper.scala 154:82] + node _T_11220 = eq(_T_1833, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11221 = and(_T_2334[84], _T_2334[83]) @[RegMapper.scala 154:98] + node _T_11222 = and(_T_11221, _T_2334[82]) @[RegMapper.scala 154:98] + node _T_11223 = and(_T_11222, _T_2334[81]) @[RegMapper.scala 154:98] + node _T_11224 = and(_T_11223, _T_2334[80]) @[RegMapper.scala 154:98] + node _T_11225 = and(_T_11224, _T_2334[79]) @[RegMapper.scala 154:98] + node _T_11226 = and(_T_11225, _T_2334[78]) @[RegMapper.scala 154:98] + node _T_11227 = and(_T_11226, _T_2334[77]) @[RegMapper.scala 154:98] + node _T_11228 = and(_T_11227, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11229 = or(_T_11220, _T_11228) @[RegMapper.scala 154:82] + node _T_11231 = eq(_T_1896, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11232 = and(_T_2334[133], _T_2334[132]) @[RegMapper.scala 154:98] + node _T_11233 = and(_T_11232, _T_2334[131]) @[RegMapper.scala 154:98] + node _T_11234 = and(_T_11233, _T_2334[130]) @[RegMapper.scala 154:98] + node _T_11235 = and(_T_11234, _T_2334[129]) @[RegMapper.scala 154:98] + node _T_11236 = and(_T_11235, _T_2334[128]) @[RegMapper.scala 154:98] + node _T_11237 = and(_T_11236, _T_2334[127]) @[RegMapper.scala 154:98] + node _T_11238 = and(_T_11237, _T_2334[126]) @[RegMapper.scala 154:98] + node _T_11239 = and(_T_11238, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11240 = or(_T_11231, _T_11239) @[RegMapper.scala 154:82] + node _T_11242 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11243 = or(_T_11242, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11245 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11246 = or(_T_11245, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11248 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11249 = or(_T_11248, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11251 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11252 = or(_T_11251, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11254 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11255 = or(_T_11254, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11257 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11258 = or(_T_11257, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11260 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11261 = or(_T_11260, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11263 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11264 = or(_T_11263, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11266 = eq(_T_1860, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11267 = and(_T_2334[101], UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11268 = or(_T_11266, _T_11267) @[RegMapper.scala 154:82] + node _T_11270 = eq(_T_1806, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11271 = and(_T_2334[60], UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11272 = or(_T_11270, _T_11271) @[RegMapper.scala 154:82] + node _T_11274 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11275 = or(_T_11274, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11277 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11278 = or(_T_11277, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11280 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11281 = or(_T_11280, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11283 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11284 = or(_T_11283, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11286 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11287 = or(_T_11286, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11289 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11290 = or(_T_11289, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11292 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11293 = or(_T_11292, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11295 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11296 = or(_T_11295, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11298 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11299 = or(_T_11298, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11301 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11302 = or(_T_11301, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11304 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11305 = or(_T_11304, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11307 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11308 = or(_T_11307, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11310 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11311 = or(_T_11310, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11313 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11314 = or(_T_11313, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11316 = eq(_T_1815, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11317 = and(_T_2334[68], _T_2334[67]) @[RegMapper.scala 154:98] + node _T_11318 = and(_T_11317, _T_2334[66]) @[RegMapper.scala 154:98] + node _T_11319 = and(_T_11318, _T_2334[65]) @[RegMapper.scala 154:98] + node _T_11320 = and(_T_11319, _T_2334[64]) @[RegMapper.scala 154:98] + node _T_11321 = and(_T_11320, _T_2334[63]) @[RegMapper.scala 154:98] + node _T_11322 = and(_T_11321, _T_2334[62]) @[RegMapper.scala 154:98] + node _T_11323 = and(_T_11322, _T_2334[61]) @[RegMapper.scala 154:98] + node _T_11324 = and(_T_11323, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11325 = or(_T_11316, _T_11324) @[RegMapper.scala 154:82] + node _T_11327 = eq(_T_1743, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11328 = and(_T_2334[15], _T_2334[14]) @[RegMapper.scala 154:98] + node _T_11329 = and(_T_11328, _T_2334[13]) @[RegMapper.scala 154:98] + node _T_11330 = and(_T_11329, _T_2334[12]) @[RegMapper.scala 154:98] + node _T_11331 = and(_T_11330, _T_2334[11]) @[RegMapper.scala 154:98] + node _T_11332 = and(_T_11331, _T_2334[10]) @[RegMapper.scala 154:98] + node _T_11333 = and(_T_11332, _T_2334[9]) @[RegMapper.scala 154:98] + node _T_11334 = and(_T_11333, _T_2334[8]) @[RegMapper.scala 154:98] + node _T_11335 = and(_T_11334, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11336 = or(_T_11327, _T_11335) @[RegMapper.scala 154:82] + node _T_11338 = eq(_T_1923, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11339 = and(_T_2334[157], _T_2334[156]) @[RegMapper.scala 154:98] + node _T_11340 = and(_T_11339, _T_2334[155]) @[RegMapper.scala 154:98] + node _T_11341 = and(_T_11340, _T_2334[154]) @[RegMapper.scala 154:98] + node _T_11342 = and(_T_11341, _T_2334[153]) @[RegMapper.scala 154:98] + node _T_11343 = and(_T_11342, _T_2334[152]) @[RegMapper.scala 154:98] + node _T_11344 = and(_T_11343, _T_2334[151]) @[RegMapper.scala 154:98] + node _T_11345 = and(_T_11344, _T_2334[150]) @[RegMapper.scala 154:98] + node _T_11346 = and(_T_11345, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11347 = or(_T_11338, _T_11346) @[RegMapper.scala 154:82] + node _T_11349 = eq(_T_1878, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11350 = and(_T_2334[117], _T_2334[116]) @[RegMapper.scala 154:98] + node _T_11351 = and(_T_11350, _T_2334[115]) @[RegMapper.scala 154:98] + node _T_11352 = and(_T_11351, _T_2334[114]) @[RegMapper.scala 154:98] + node _T_11353 = and(_T_11352, _T_2334[113]) @[RegMapper.scala 154:98] + node _T_11354 = and(_T_11353, _T_2334[112]) @[RegMapper.scala 154:98] + node _T_11355 = and(_T_11354, _T_2334[111]) @[RegMapper.scala 154:98] + node _T_11356 = and(_T_11355, _T_2334[110]) @[RegMapper.scala 154:98] + node _T_11357 = and(_T_11356, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11358 = or(_T_11349, _T_11357) @[RegMapper.scala 154:82] + node _T_11360 = eq(_T_1797, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11361 = and(_T_2334[59], _T_2334[58]) @[RegMapper.scala 154:98] + node _T_11362 = and(_T_11361, _T_2334[57]) @[RegMapper.scala 154:98] + node _T_11363 = and(_T_11362, _T_2334[56]) @[RegMapper.scala 154:98] + node _T_11364 = and(_T_11363, _T_2334[55]) @[RegMapper.scala 154:98] + node _T_11365 = and(_T_11364, _T_2334[54]) @[RegMapper.scala 154:98] + node _T_11366 = and(_T_11365, _T_2334[53]) @[RegMapper.scala 154:98] + node _T_11367 = and(_T_11366, _T_2334[52]) @[RegMapper.scala 154:98] + node _T_11368 = and(_T_11367, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11369 = or(_T_11360, _T_11368) @[RegMapper.scala 154:82] + node _T_11371 = eq(_T_1752, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11372 = and(_T_2334[23], _T_2334[22]) @[RegMapper.scala 154:98] + node _T_11373 = and(_T_11372, _T_2334[21]) @[RegMapper.scala 154:98] + node _T_11374 = and(_T_11373, _T_2334[20]) @[RegMapper.scala 154:98] + node _T_11375 = and(_T_11374, _T_2334[19]) @[RegMapper.scala 154:98] + node _T_11376 = and(_T_11375, _T_2334[18]) @[RegMapper.scala 154:98] + node _T_11377 = and(_T_11376, _T_2334[17]) @[RegMapper.scala 154:98] + node _T_11378 = and(_T_11377, _T_2334[16]) @[RegMapper.scala 154:98] + node _T_11379 = and(_T_11378, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11380 = or(_T_11371, _T_11379) @[RegMapper.scala 154:82] + node _T_11382 = eq(_T_1932, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11383 = and(_T_2334[165], _T_2334[164]) @[RegMapper.scala 154:98] + node _T_11384 = and(_T_11383, _T_2334[163]) @[RegMapper.scala 154:98] + node _T_11385 = and(_T_11384, _T_2334[162]) @[RegMapper.scala 154:98] + node _T_11386 = and(_T_11385, _T_2334[161]) @[RegMapper.scala 154:98] + node _T_11387 = and(_T_11386, _T_2334[160]) @[RegMapper.scala 154:98] + node _T_11388 = and(_T_11387, _T_2334[159]) @[RegMapper.scala 154:98] + node _T_11389 = and(_T_11388, _T_2334[158]) @[RegMapper.scala 154:98] + node _T_11390 = and(_T_11389, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11391 = or(_T_11382, _T_11390) @[RegMapper.scala 154:82] + node _T_11393 = eq(_T_1914, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11394 = and(_T_2334[149], _T_2334[148]) @[RegMapper.scala 154:98] + node _T_11395 = and(_T_11394, _T_2334[147]) @[RegMapper.scala 154:98] + node _T_11396 = and(_T_11395, _T_2334[146]) @[RegMapper.scala 154:98] + node _T_11397 = and(_T_11396, _T_2334[145]) @[RegMapper.scala 154:98] + node _T_11398 = and(_T_11397, _T_2334[144]) @[RegMapper.scala 154:98] + node _T_11399 = and(_T_11398, _T_2334[143]) @[RegMapper.scala 154:98] + node _T_11400 = and(_T_11399, _T_2334[142]) @[RegMapper.scala 154:98] + node _T_11401 = and(_T_11400, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11402 = or(_T_11393, _T_11401) @[RegMapper.scala 154:82] + node _T_11404 = eq(_T_1869, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11405 = and(_T_2334[109], _T_2334[108]) @[RegMapper.scala 154:98] + node _T_11406 = and(_T_11405, _T_2334[107]) @[RegMapper.scala 154:98] + node _T_11407 = and(_T_11406, _T_2334[106]) @[RegMapper.scala 154:98] + node _T_11408 = and(_T_11407, _T_2334[105]) @[RegMapper.scala 154:98] + node _T_11409 = and(_T_11408, _T_2334[104]) @[RegMapper.scala 154:98] + node _T_11410 = and(_T_11409, _T_2334[103]) @[RegMapper.scala 154:98] + node _T_11411 = and(_T_11410, _T_2334[102]) @[RegMapper.scala 154:98] + node _T_11412 = and(_T_11411, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11413 = or(_T_11404, _T_11412) @[RegMapper.scala 154:82] + node _T_11415 = eq(_T_1779, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11416 = and(_T_2334[47], _T_2334[46]) @[RegMapper.scala 154:98] + node _T_11417 = and(_T_11416, _T_2334[45]) @[RegMapper.scala 154:98] + node _T_11418 = and(_T_11417, _T_2334[44]) @[RegMapper.scala 154:98] + node _T_11419 = and(_T_11418, _T_2334[43]) @[RegMapper.scala 154:98] + node _T_11420 = and(_T_11419, _T_2334[42]) @[RegMapper.scala 154:98] + node _T_11421 = and(_T_11420, _T_2334[41]) @[RegMapper.scala 154:98] + node _T_11422 = and(_T_11421, _T_2334[40]) @[RegMapper.scala 154:98] + node _T_11423 = and(_T_11422, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11424 = or(_T_11415, _T_11423) @[RegMapper.scala 154:82] + node _T_11426 = eq(_T_1851, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11427 = and(_T_2334[100], _T_2334[99]) @[RegMapper.scala 154:98] + node _T_11428 = and(_T_11427, _T_2334[98]) @[RegMapper.scala 154:98] + node _T_11429 = and(_T_11428, _T_2334[97]) @[RegMapper.scala 154:98] + node _T_11430 = and(_T_11429, _T_2334[96]) @[RegMapper.scala 154:98] + node _T_11431 = and(_T_11430, _T_2334[95]) @[RegMapper.scala 154:98] + node _T_11432 = and(_T_11431, _T_2334[94]) @[RegMapper.scala 154:98] + node _T_11433 = and(_T_11432, _T_2334[93]) @[RegMapper.scala 154:98] + node _T_11434 = and(_T_11433, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11435 = or(_T_11426, _T_11434) @[RegMapper.scala 154:82] + node _T_11437 = eq(_T_1905, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11438 = and(_T_2334[141], _T_2334[140]) @[RegMapper.scala 154:98] + node _T_11439 = and(_T_11438, _T_2334[139]) @[RegMapper.scala 154:98] + node _T_11440 = and(_T_11439, _T_2334[138]) @[RegMapper.scala 154:98] + node _T_11441 = and(_T_11440, _T_2334[137]) @[RegMapper.scala 154:98] + node _T_11442 = and(_T_11441, _T_2334[136]) @[RegMapper.scala 154:98] + node _T_11443 = and(_T_11442, _T_2334[135]) @[RegMapper.scala 154:98] + node _T_11444 = and(_T_11443, _T_2334[134]) @[RegMapper.scala 154:98] + node _T_11445 = and(_T_11444, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11446 = or(_T_11437, _T_11445) @[RegMapper.scala 154:82] + node _T_11448 = eq(_T_1941, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11449 = and(_T_2334[173], _T_2334[172]) @[RegMapper.scala 154:98] + node _T_11450 = and(_T_11449, _T_2334[171]) @[RegMapper.scala 154:98] + node _T_11451 = and(_T_11450, _T_2334[170]) @[RegMapper.scala 154:98] + node _T_11452 = and(_T_11451, _T_2334[169]) @[RegMapper.scala 154:98] + node _T_11453 = and(_T_11452, _T_2334[168]) @[RegMapper.scala 154:98] + node _T_11454 = and(_T_11453, _T_2334[167]) @[RegMapper.scala 154:98] + node _T_11455 = and(_T_11454, _T_2334[166]) @[RegMapper.scala 154:98] + node _T_11456 = and(_T_11455, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11457 = or(_T_11448, _T_11456) @[RegMapper.scala 154:82] + node _T_11459 = eq(_T_1734, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11460 = and(_T_2334[7], _T_2334[6]) @[RegMapper.scala 154:98] + node _T_11461 = and(_T_11460, _T_2334[5]) @[RegMapper.scala 154:98] + node _T_11462 = and(_T_11461, _T_2334[4]) @[RegMapper.scala 154:98] + node _T_11463 = and(_T_11462, _T_2334[3]) @[RegMapper.scala 154:98] + node _T_11464 = and(_T_11463, _T_2334[2]) @[RegMapper.scala 154:98] + node _T_11465 = and(_T_11464, _T_2334[1]) @[RegMapper.scala 154:98] + node _T_11466 = and(_T_11465, _T_2334[0]) @[RegMapper.scala 154:98] + node _T_11467 = and(_T_11466, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11468 = or(_T_11459, _T_11467) @[RegMapper.scala 154:82] + node _T_11470 = eq(_T_1788, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11471 = and(_T_2334[51], _T_2334[50]) @[RegMapper.scala 154:98] + node _T_11472 = and(_T_11471, _T_2334[49]) @[RegMapper.scala 154:98] + node _T_11473 = and(_T_11472, _T_2334[48]) @[RegMapper.scala 154:98] + node _T_11474 = and(_T_11473, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_11475 = or(_T_11470, _T_11474) @[RegMapper.scala 154:82] + node _T_11477 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11478 = or(_T_11477, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11480 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11481 = or(_T_11480, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11483 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11484 = or(_T_11483, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11486 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11487 = or(_T_11486, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11489 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11490 = or(_T_11489, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11492 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11493 = or(_T_11492, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11495 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11496 = or(_T_11495, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11498 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11499 = or(_T_11498, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11501 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11502 = or(_T_11501, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11504 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11505 = or(_T_11504, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11507 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11508 = or(_T_11507, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11510 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11511 = or(_T_11510, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11513 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11514 = or(_T_11513, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11516 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11517 = or(_T_11516, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11519 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11520 = or(_T_11519, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11522 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11523 = or(_T_11522, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_11525 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_11526 = or(_T_11525, UInt<1>("h01")) @[RegMapper.scala 154:82] + wire _T_11529 : UInt<1>[64] @[RegMapper.scala 154:24] + _T_11529 is invalid @[RegMapper.scala 154:24] + _T_11529[0] <= _T_11163 @[RegMapper.scala 154:24] + _T_11529[1] <= _T_11174 @[RegMapper.scala 154:24] + _T_11529[2] <= _T_11185 @[RegMapper.scala 154:24] + _T_11529[3] <= _T_11196 @[RegMapper.scala 154:24] + _T_11529[4] <= _T_11207 @[RegMapper.scala 154:24] + _T_11529[5] <= _T_11218 @[RegMapper.scala 154:24] + _T_11529[6] <= _T_11229 @[RegMapper.scala 154:24] + _T_11529[7] <= _T_11240 @[RegMapper.scala 154:24] + _T_11529[8] <= _T_11243 @[RegMapper.scala 154:24] + _T_11529[9] <= _T_11246 @[RegMapper.scala 154:24] + _T_11529[10] <= _T_11249 @[RegMapper.scala 154:24] + _T_11529[11] <= _T_11252 @[RegMapper.scala 154:24] + _T_11529[12] <= _T_11255 @[RegMapper.scala 154:24] + _T_11529[13] <= _T_11258 @[RegMapper.scala 154:24] + _T_11529[14] <= _T_11261 @[RegMapper.scala 154:24] + _T_11529[15] <= _T_11264 @[RegMapper.scala 154:24] + _T_11529[16] <= _T_11268 @[RegMapper.scala 154:24] + _T_11529[17] <= _T_11272 @[RegMapper.scala 154:24] + _T_11529[18] <= _T_11275 @[RegMapper.scala 154:24] + _T_11529[19] <= _T_11278 @[RegMapper.scala 154:24] + _T_11529[20] <= _T_11281 @[RegMapper.scala 154:24] + _T_11529[21] <= _T_11284 @[RegMapper.scala 154:24] + _T_11529[22] <= _T_11287 @[RegMapper.scala 154:24] + _T_11529[23] <= _T_11290 @[RegMapper.scala 154:24] + _T_11529[24] <= _T_11293 @[RegMapper.scala 154:24] + _T_11529[25] <= _T_11296 @[RegMapper.scala 154:24] + _T_11529[26] <= _T_11299 @[RegMapper.scala 154:24] + _T_11529[27] <= _T_11302 @[RegMapper.scala 154:24] + _T_11529[28] <= _T_11305 @[RegMapper.scala 154:24] + _T_11529[29] <= _T_11308 @[RegMapper.scala 154:24] + _T_11529[30] <= _T_11311 @[RegMapper.scala 154:24] + _T_11529[31] <= _T_11314 @[RegMapper.scala 154:24] + _T_11529[32] <= _T_11325 @[RegMapper.scala 154:24] + _T_11529[33] <= _T_11336 @[RegMapper.scala 154:24] + _T_11529[34] <= _T_11347 @[RegMapper.scala 154:24] + _T_11529[35] <= _T_11358 @[RegMapper.scala 154:24] + _T_11529[36] <= _T_11369 @[RegMapper.scala 154:24] + _T_11529[37] <= _T_11380 @[RegMapper.scala 154:24] + _T_11529[38] <= _T_11391 @[RegMapper.scala 154:24] + _T_11529[39] <= _T_11402 @[RegMapper.scala 154:24] + _T_11529[40] <= _T_11413 @[RegMapper.scala 154:24] + _T_11529[41] <= _T_11424 @[RegMapper.scala 154:24] + _T_11529[42] <= _T_11435 @[RegMapper.scala 154:24] + _T_11529[43] <= _T_11446 @[RegMapper.scala 154:24] + _T_11529[44] <= _T_11457 @[RegMapper.scala 154:24] + _T_11529[45] <= _T_11468 @[RegMapper.scala 154:24] + _T_11529[46] <= _T_11475 @[RegMapper.scala 154:24] + _T_11529[47] <= _T_11478 @[RegMapper.scala 154:24] + _T_11529[48] <= _T_11481 @[RegMapper.scala 154:24] + _T_11529[49] <= _T_11484 @[RegMapper.scala 154:24] + _T_11529[50] <= _T_11487 @[RegMapper.scala 154:24] + _T_11529[51] <= _T_11490 @[RegMapper.scala 154:24] + _T_11529[52] <= _T_11493 @[RegMapper.scala 154:24] + _T_11529[53] <= _T_11496 @[RegMapper.scala 154:24] + _T_11529[54] <= _T_11499 @[RegMapper.scala 154:24] + _T_11529[55] <= _T_11502 @[RegMapper.scala 154:24] + _T_11529[56] <= _T_11505 @[RegMapper.scala 154:24] + _T_11529[57] <= _T_11508 @[RegMapper.scala 154:24] + _T_11529[58] <= _T_11511 @[RegMapper.scala 154:24] + _T_11529[59] <= _T_11514 @[RegMapper.scala 154:24] + _T_11529[60] <= _T_11517 @[RegMapper.scala 154:24] + _T_11529[61] <= _T_11520 @[RegMapper.scala 154:24] + _T_11529[62] <= _T_11523 @[RegMapper.scala 154:24] + _T_11529[63] <= _T_11526 @[RegMapper.scala 154:24] + node _T_11597 = eq(_T_1842, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11598 = and(_T_2522[92], _T_2522[91]) @[RegMapper.scala 155:98] + node _T_11599 = and(_T_11598, _T_2522[90]) @[RegMapper.scala 155:98] + node _T_11600 = and(_T_11599, _T_2522[89]) @[RegMapper.scala 155:98] + node _T_11601 = and(_T_11600, _T_2522[88]) @[RegMapper.scala 155:98] + node _T_11602 = and(_T_11601, _T_2522[87]) @[RegMapper.scala 155:98] + node _T_11603 = and(_T_11602, _T_2522[86]) @[RegMapper.scala 155:98] + node _T_11604 = and(_T_11603, _T_2522[85]) @[RegMapper.scala 155:98] + node _T_11605 = and(_T_11604, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11606 = or(_T_11597, _T_11605) @[RegMapper.scala 155:82] + node _T_11608 = eq(_T_1824, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11609 = and(_T_2522[76], _T_2522[75]) @[RegMapper.scala 155:98] + node _T_11610 = and(_T_11609, _T_2522[74]) @[RegMapper.scala 155:98] + node _T_11611 = and(_T_11610, _T_2522[73]) @[RegMapper.scala 155:98] + node _T_11612 = and(_T_11611, _T_2522[72]) @[RegMapper.scala 155:98] + node _T_11613 = and(_T_11612, _T_2522[71]) @[RegMapper.scala 155:98] + node _T_11614 = and(_T_11613, _T_2522[70]) @[RegMapper.scala 155:98] + node _T_11615 = and(_T_11614, _T_2522[69]) @[RegMapper.scala 155:98] + node _T_11616 = and(_T_11615, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11617 = or(_T_11608, _T_11616) @[RegMapper.scala 155:82] + node _T_11619 = eq(_T_1887, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11620 = and(_T_2522[125], _T_2522[124]) @[RegMapper.scala 155:98] + node _T_11621 = and(_T_11620, _T_2522[123]) @[RegMapper.scala 155:98] + node _T_11622 = and(_T_11621, _T_2522[122]) @[RegMapper.scala 155:98] + node _T_11623 = and(_T_11622, _T_2522[121]) @[RegMapper.scala 155:98] + node _T_11624 = and(_T_11623, _T_2522[120]) @[RegMapper.scala 155:98] + node _T_11625 = and(_T_11624, _T_2522[119]) @[RegMapper.scala 155:98] + node _T_11626 = and(_T_11625, _T_2522[118]) @[RegMapper.scala 155:98] + node _T_11627 = and(_T_11626, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11628 = or(_T_11619, _T_11627) @[RegMapper.scala 155:82] + node _T_11630 = eq(_T_1950, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11631 = and(_T_2522[181], _T_2522[180]) @[RegMapper.scala 155:98] + node _T_11632 = and(_T_11631, _T_2522[179]) @[RegMapper.scala 155:98] + node _T_11633 = and(_T_11632, _T_2522[178]) @[RegMapper.scala 155:98] + node _T_11634 = and(_T_11633, _T_2522[177]) @[RegMapper.scala 155:98] + node _T_11635 = and(_T_11634, _T_2522[176]) @[RegMapper.scala 155:98] + node _T_11636 = and(_T_11635, _T_2522[175]) @[RegMapper.scala 155:98] + node _T_11637 = and(_T_11636, _T_2522[174]) @[RegMapper.scala 155:98] + node _T_11638 = and(_T_11637, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11639 = or(_T_11630, _T_11638) @[RegMapper.scala 155:82] + node _T_11641 = eq(_T_1761, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11642 = and(_T_2522[31], _T_2522[30]) @[RegMapper.scala 155:98] + node _T_11643 = and(_T_11642, _T_2522[29]) @[RegMapper.scala 155:98] + node _T_11644 = and(_T_11643, _T_2522[28]) @[RegMapper.scala 155:98] + node _T_11645 = and(_T_11644, _T_2522[27]) @[RegMapper.scala 155:98] + node _T_11646 = and(_T_11645, _T_2522[26]) @[RegMapper.scala 155:98] + node _T_11647 = and(_T_11646, _T_2522[25]) @[RegMapper.scala 155:98] + node _T_11648 = and(_T_11647, _T_2522[24]) @[RegMapper.scala 155:98] + node _T_11649 = and(_T_11648, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11650 = or(_T_11641, _T_11649) @[RegMapper.scala 155:82] + node _T_11652 = eq(_T_1770, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11653 = and(_T_2522[39], _T_2522[38]) @[RegMapper.scala 155:98] + node _T_11654 = and(_T_11653, _T_2522[37]) @[RegMapper.scala 155:98] + node _T_11655 = and(_T_11654, _T_2522[36]) @[RegMapper.scala 155:98] + node _T_11656 = and(_T_11655, _T_2522[35]) @[RegMapper.scala 155:98] + node _T_11657 = and(_T_11656, _T_2522[34]) @[RegMapper.scala 155:98] + node _T_11658 = and(_T_11657, _T_2522[33]) @[RegMapper.scala 155:98] + node _T_11659 = and(_T_11658, _T_2522[32]) @[RegMapper.scala 155:98] + node _T_11660 = and(_T_11659, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11661 = or(_T_11652, _T_11660) @[RegMapper.scala 155:82] + node _T_11663 = eq(_T_1833, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11664 = and(_T_2522[84], _T_2522[83]) @[RegMapper.scala 155:98] + node _T_11665 = and(_T_11664, _T_2522[82]) @[RegMapper.scala 155:98] + node _T_11666 = and(_T_11665, _T_2522[81]) @[RegMapper.scala 155:98] + node _T_11667 = and(_T_11666, _T_2522[80]) @[RegMapper.scala 155:98] + node _T_11668 = and(_T_11667, _T_2522[79]) @[RegMapper.scala 155:98] + node _T_11669 = and(_T_11668, _T_2522[78]) @[RegMapper.scala 155:98] + node _T_11670 = and(_T_11669, _T_2522[77]) @[RegMapper.scala 155:98] + node _T_11671 = and(_T_11670, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11672 = or(_T_11663, _T_11671) @[RegMapper.scala 155:82] + node _T_11674 = eq(_T_1896, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11675 = and(_T_2522[133], _T_2522[132]) @[RegMapper.scala 155:98] + node _T_11676 = and(_T_11675, _T_2522[131]) @[RegMapper.scala 155:98] + node _T_11677 = and(_T_11676, _T_2522[130]) @[RegMapper.scala 155:98] + node _T_11678 = and(_T_11677, _T_2522[129]) @[RegMapper.scala 155:98] + node _T_11679 = and(_T_11678, _T_2522[128]) @[RegMapper.scala 155:98] + node _T_11680 = and(_T_11679, _T_2522[127]) @[RegMapper.scala 155:98] + node _T_11681 = and(_T_11680, _T_2522[126]) @[RegMapper.scala 155:98] + node _T_11682 = and(_T_11681, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11683 = or(_T_11674, _T_11682) @[RegMapper.scala 155:82] + node _T_11685 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11686 = or(_T_11685, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11688 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11689 = or(_T_11688, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11691 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11692 = or(_T_11691, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11694 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11695 = or(_T_11694, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11697 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11698 = or(_T_11697, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11700 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11701 = or(_T_11700, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11703 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11704 = or(_T_11703, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11706 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11707 = or(_T_11706, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11709 = eq(_T_1860, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11710 = and(_T_2522[101], UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11711 = or(_T_11709, _T_11710) @[RegMapper.scala 155:82] + node _T_11713 = eq(_T_1806, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11714 = and(_T_2522[60], UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11715 = or(_T_11713, _T_11714) @[RegMapper.scala 155:82] + node _T_11717 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11718 = or(_T_11717, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11720 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11721 = or(_T_11720, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11723 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11724 = or(_T_11723, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11726 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11727 = or(_T_11726, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11729 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11730 = or(_T_11729, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11732 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11733 = or(_T_11732, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11735 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11736 = or(_T_11735, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11738 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11739 = or(_T_11738, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11741 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11742 = or(_T_11741, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11744 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11745 = or(_T_11744, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11747 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11748 = or(_T_11747, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11750 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11751 = or(_T_11750, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11753 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11754 = or(_T_11753, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11756 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11757 = or(_T_11756, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11759 = eq(_T_1815, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11760 = and(_T_2522[68], _T_2522[67]) @[RegMapper.scala 155:98] + node _T_11761 = and(_T_11760, _T_2522[66]) @[RegMapper.scala 155:98] + node _T_11762 = and(_T_11761, _T_2522[65]) @[RegMapper.scala 155:98] + node _T_11763 = and(_T_11762, _T_2522[64]) @[RegMapper.scala 155:98] + node _T_11764 = and(_T_11763, _T_2522[63]) @[RegMapper.scala 155:98] + node _T_11765 = and(_T_11764, _T_2522[62]) @[RegMapper.scala 155:98] + node _T_11766 = and(_T_11765, _T_2522[61]) @[RegMapper.scala 155:98] + node _T_11767 = and(_T_11766, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11768 = or(_T_11759, _T_11767) @[RegMapper.scala 155:82] + node _T_11770 = eq(_T_1743, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11771 = and(_T_2522[15], _T_2522[14]) @[RegMapper.scala 155:98] + node _T_11772 = and(_T_11771, _T_2522[13]) @[RegMapper.scala 155:98] + node _T_11773 = and(_T_11772, _T_2522[12]) @[RegMapper.scala 155:98] + node _T_11774 = and(_T_11773, _T_2522[11]) @[RegMapper.scala 155:98] + node _T_11775 = and(_T_11774, _T_2522[10]) @[RegMapper.scala 155:98] + node _T_11776 = and(_T_11775, _T_2522[9]) @[RegMapper.scala 155:98] + node _T_11777 = and(_T_11776, _T_2522[8]) @[RegMapper.scala 155:98] + node _T_11778 = and(_T_11777, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11779 = or(_T_11770, _T_11778) @[RegMapper.scala 155:82] + node _T_11781 = eq(_T_1923, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11782 = and(_T_2522[157], _T_2522[156]) @[RegMapper.scala 155:98] + node _T_11783 = and(_T_11782, _T_2522[155]) @[RegMapper.scala 155:98] + node _T_11784 = and(_T_11783, _T_2522[154]) @[RegMapper.scala 155:98] + node _T_11785 = and(_T_11784, _T_2522[153]) @[RegMapper.scala 155:98] + node _T_11786 = and(_T_11785, _T_2522[152]) @[RegMapper.scala 155:98] + node _T_11787 = and(_T_11786, _T_2522[151]) @[RegMapper.scala 155:98] + node _T_11788 = and(_T_11787, _T_2522[150]) @[RegMapper.scala 155:98] + node _T_11789 = and(_T_11788, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11790 = or(_T_11781, _T_11789) @[RegMapper.scala 155:82] + node _T_11792 = eq(_T_1878, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11793 = and(_T_2522[117], _T_2522[116]) @[RegMapper.scala 155:98] + node _T_11794 = and(_T_11793, _T_2522[115]) @[RegMapper.scala 155:98] + node _T_11795 = and(_T_11794, _T_2522[114]) @[RegMapper.scala 155:98] + node _T_11796 = and(_T_11795, _T_2522[113]) @[RegMapper.scala 155:98] + node _T_11797 = and(_T_11796, _T_2522[112]) @[RegMapper.scala 155:98] + node _T_11798 = and(_T_11797, _T_2522[111]) @[RegMapper.scala 155:98] + node _T_11799 = and(_T_11798, _T_2522[110]) @[RegMapper.scala 155:98] + node _T_11800 = and(_T_11799, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11801 = or(_T_11792, _T_11800) @[RegMapper.scala 155:82] + node _T_11803 = eq(_T_1797, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11804 = and(_T_2522[59], _T_2522[58]) @[RegMapper.scala 155:98] + node _T_11805 = and(_T_11804, _T_2522[57]) @[RegMapper.scala 155:98] + node _T_11806 = and(_T_11805, _T_2522[56]) @[RegMapper.scala 155:98] + node _T_11807 = and(_T_11806, _T_2522[55]) @[RegMapper.scala 155:98] + node _T_11808 = and(_T_11807, _T_2522[54]) @[RegMapper.scala 155:98] + node _T_11809 = and(_T_11808, _T_2522[53]) @[RegMapper.scala 155:98] + node _T_11810 = and(_T_11809, _T_2522[52]) @[RegMapper.scala 155:98] + node _T_11811 = and(_T_11810, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11812 = or(_T_11803, _T_11811) @[RegMapper.scala 155:82] + node _T_11814 = eq(_T_1752, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11815 = and(_T_2522[23], _T_2522[22]) @[RegMapper.scala 155:98] + node _T_11816 = and(_T_11815, _T_2522[21]) @[RegMapper.scala 155:98] + node _T_11817 = and(_T_11816, _T_2522[20]) @[RegMapper.scala 155:98] + node _T_11818 = and(_T_11817, _T_2522[19]) @[RegMapper.scala 155:98] + node _T_11819 = and(_T_11818, _T_2522[18]) @[RegMapper.scala 155:98] + node _T_11820 = and(_T_11819, _T_2522[17]) @[RegMapper.scala 155:98] + node _T_11821 = and(_T_11820, _T_2522[16]) @[RegMapper.scala 155:98] + node _T_11822 = and(_T_11821, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11823 = or(_T_11814, _T_11822) @[RegMapper.scala 155:82] + node _T_11825 = eq(_T_1932, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11826 = and(_T_2522[165], _T_2522[164]) @[RegMapper.scala 155:98] + node _T_11827 = and(_T_11826, _T_2522[163]) @[RegMapper.scala 155:98] + node _T_11828 = and(_T_11827, _T_2522[162]) @[RegMapper.scala 155:98] + node _T_11829 = and(_T_11828, _T_2522[161]) @[RegMapper.scala 155:98] + node _T_11830 = and(_T_11829, _T_2522[160]) @[RegMapper.scala 155:98] + node _T_11831 = and(_T_11830, _T_2522[159]) @[RegMapper.scala 155:98] + node _T_11832 = and(_T_11831, _T_2522[158]) @[RegMapper.scala 155:98] + node _T_11833 = and(_T_11832, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11834 = or(_T_11825, _T_11833) @[RegMapper.scala 155:82] + node _T_11836 = eq(_T_1914, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11837 = and(_T_2522[149], _T_2522[148]) @[RegMapper.scala 155:98] + node _T_11838 = and(_T_11837, _T_2522[147]) @[RegMapper.scala 155:98] + node _T_11839 = and(_T_11838, _T_2522[146]) @[RegMapper.scala 155:98] + node _T_11840 = and(_T_11839, _T_2522[145]) @[RegMapper.scala 155:98] + node _T_11841 = and(_T_11840, _T_2522[144]) @[RegMapper.scala 155:98] + node _T_11842 = and(_T_11841, _T_2522[143]) @[RegMapper.scala 155:98] + node _T_11843 = and(_T_11842, _T_2522[142]) @[RegMapper.scala 155:98] + node _T_11844 = and(_T_11843, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11845 = or(_T_11836, _T_11844) @[RegMapper.scala 155:82] + node _T_11847 = eq(_T_1869, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11848 = and(_T_2522[109], _T_2522[108]) @[RegMapper.scala 155:98] + node _T_11849 = and(_T_11848, _T_2522[107]) @[RegMapper.scala 155:98] + node _T_11850 = and(_T_11849, _T_2522[106]) @[RegMapper.scala 155:98] + node _T_11851 = and(_T_11850, _T_2522[105]) @[RegMapper.scala 155:98] + node _T_11852 = and(_T_11851, _T_2522[104]) @[RegMapper.scala 155:98] + node _T_11853 = and(_T_11852, _T_2522[103]) @[RegMapper.scala 155:98] + node _T_11854 = and(_T_11853, _T_2522[102]) @[RegMapper.scala 155:98] + node _T_11855 = and(_T_11854, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11856 = or(_T_11847, _T_11855) @[RegMapper.scala 155:82] + node _T_11858 = eq(_T_1779, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11859 = and(_T_2522[47], _T_2522[46]) @[RegMapper.scala 155:98] + node _T_11860 = and(_T_11859, _T_2522[45]) @[RegMapper.scala 155:98] + node _T_11861 = and(_T_11860, _T_2522[44]) @[RegMapper.scala 155:98] + node _T_11862 = and(_T_11861, _T_2522[43]) @[RegMapper.scala 155:98] + node _T_11863 = and(_T_11862, _T_2522[42]) @[RegMapper.scala 155:98] + node _T_11864 = and(_T_11863, _T_2522[41]) @[RegMapper.scala 155:98] + node _T_11865 = and(_T_11864, _T_2522[40]) @[RegMapper.scala 155:98] + node _T_11866 = and(_T_11865, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11867 = or(_T_11858, _T_11866) @[RegMapper.scala 155:82] + node _T_11869 = eq(_T_1851, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11870 = and(_T_2522[100], _T_2522[99]) @[RegMapper.scala 155:98] + node _T_11871 = and(_T_11870, _T_2522[98]) @[RegMapper.scala 155:98] + node _T_11872 = and(_T_11871, _T_2522[97]) @[RegMapper.scala 155:98] + node _T_11873 = and(_T_11872, _T_2522[96]) @[RegMapper.scala 155:98] + node _T_11874 = and(_T_11873, _T_2522[95]) @[RegMapper.scala 155:98] + node _T_11875 = and(_T_11874, _T_2522[94]) @[RegMapper.scala 155:98] + node _T_11876 = and(_T_11875, _T_2522[93]) @[RegMapper.scala 155:98] + node _T_11877 = and(_T_11876, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11878 = or(_T_11869, _T_11877) @[RegMapper.scala 155:82] + node _T_11880 = eq(_T_1905, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11881 = and(_T_2522[141], _T_2522[140]) @[RegMapper.scala 155:98] + node _T_11882 = and(_T_11881, _T_2522[139]) @[RegMapper.scala 155:98] + node _T_11883 = and(_T_11882, _T_2522[138]) @[RegMapper.scala 155:98] + node _T_11884 = and(_T_11883, _T_2522[137]) @[RegMapper.scala 155:98] + node _T_11885 = and(_T_11884, _T_2522[136]) @[RegMapper.scala 155:98] + node _T_11886 = and(_T_11885, _T_2522[135]) @[RegMapper.scala 155:98] + node _T_11887 = and(_T_11886, _T_2522[134]) @[RegMapper.scala 155:98] + node _T_11888 = and(_T_11887, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11889 = or(_T_11880, _T_11888) @[RegMapper.scala 155:82] + node _T_11891 = eq(_T_1941, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11892 = and(_T_2522[173], _T_2522[172]) @[RegMapper.scala 155:98] + node _T_11893 = and(_T_11892, _T_2522[171]) @[RegMapper.scala 155:98] + node _T_11894 = and(_T_11893, _T_2522[170]) @[RegMapper.scala 155:98] + node _T_11895 = and(_T_11894, _T_2522[169]) @[RegMapper.scala 155:98] + node _T_11896 = and(_T_11895, _T_2522[168]) @[RegMapper.scala 155:98] + node _T_11897 = and(_T_11896, _T_2522[167]) @[RegMapper.scala 155:98] + node _T_11898 = and(_T_11897, _T_2522[166]) @[RegMapper.scala 155:98] + node _T_11899 = and(_T_11898, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11900 = or(_T_11891, _T_11899) @[RegMapper.scala 155:82] + node _T_11902 = eq(_T_1734, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11903 = and(_T_2522[7], _T_2522[6]) @[RegMapper.scala 155:98] + node _T_11904 = and(_T_11903, _T_2522[5]) @[RegMapper.scala 155:98] + node _T_11905 = and(_T_11904, _T_2522[4]) @[RegMapper.scala 155:98] + node _T_11906 = and(_T_11905, _T_2522[3]) @[RegMapper.scala 155:98] + node _T_11907 = and(_T_11906, _T_2522[2]) @[RegMapper.scala 155:98] + node _T_11908 = and(_T_11907, _T_2522[1]) @[RegMapper.scala 155:98] + node _T_11909 = and(_T_11908, _T_2522[0]) @[RegMapper.scala 155:98] + node _T_11910 = and(_T_11909, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11911 = or(_T_11902, _T_11910) @[RegMapper.scala 155:82] + node _T_11913 = eq(_T_1788, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11914 = and(_T_2522[51], _T_2522[50]) @[RegMapper.scala 155:98] + node _T_11915 = and(_T_11914, _T_2522[49]) @[RegMapper.scala 155:98] + node _T_11916 = and(_T_11915, _T_2522[48]) @[RegMapper.scala 155:98] + node _T_11917 = and(_T_11916, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_11918 = or(_T_11913, _T_11917) @[RegMapper.scala 155:82] + node _T_11920 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11921 = or(_T_11920, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11923 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11924 = or(_T_11923, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11926 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11927 = or(_T_11926, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11929 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11930 = or(_T_11929, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11932 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11933 = or(_T_11932, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11935 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11936 = or(_T_11935, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11938 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11939 = or(_T_11938, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11941 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11942 = or(_T_11941, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11944 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11945 = or(_T_11944, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11947 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11948 = or(_T_11947, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11950 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11951 = or(_T_11950, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11953 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11954 = or(_T_11953, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11956 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11957 = or(_T_11956, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11959 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11960 = or(_T_11959, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11962 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11963 = or(_T_11962, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11965 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11966 = or(_T_11965, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_11968 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_11969 = or(_T_11968, UInt<1>("h01")) @[RegMapper.scala 155:82] + wire _T_11972 : UInt<1>[64] @[RegMapper.scala 155:24] + _T_11972 is invalid @[RegMapper.scala 155:24] + _T_11972[0] <= _T_11606 @[RegMapper.scala 155:24] + _T_11972[1] <= _T_11617 @[RegMapper.scala 155:24] + _T_11972[2] <= _T_11628 @[RegMapper.scala 155:24] + _T_11972[3] <= _T_11639 @[RegMapper.scala 155:24] + _T_11972[4] <= _T_11650 @[RegMapper.scala 155:24] + _T_11972[5] <= _T_11661 @[RegMapper.scala 155:24] + _T_11972[6] <= _T_11672 @[RegMapper.scala 155:24] + _T_11972[7] <= _T_11683 @[RegMapper.scala 155:24] + _T_11972[8] <= _T_11686 @[RegMapper.scala 155:24] + _T_11972[9] <= _T_11689 @[RegMapper.scala 155:24] + _T_11972[10] <= _T_11692 @[RegMapper.scala 155:24] + _T_11972[11] <= _T_11695 @[RegMapper.scala 155:24] + _T_11972[12] <= _T_11698 @[RegMapper.scala 155:24] + _T_11972[13] <= _T_11701 @[RegMapper.scala 155:24] + _T_11972[14] <= _T_11704 @[RegMapper.scala 155:24] + _T_11972[15] <= _T_11707 @[RegMapper.scala 155:24] + _T_11972[16] <= _T_11711 @[RegMapper.scala 155:24] + _T_11972[17] <= _T_11715 @[RegMapper.scala 155:24] + _T_11972[18] <= _T_11718 @[RegMapper.scala 155:24] + _T_11972[19] <= _T_11721 @[RegMapper.scala 155:24] + _T_11972[20] <= _T_11724 @[RegMapper.scala 155:24] + _T_11972[21] <= _T_11727 @[RegMapper.scala 155:24] + _T_11972[22] <= _T_11730 @[RegMapper.scala 155:24] + _T_11972[23] <= _T_11733 @[RegMapper.scala 155:24] + _T_11972[24] <= _T_11736 @[RegMapper.scala 155:24] + _T_11972[25] <= _T_11739 @[RegMapper.scala 155:24] + _T_11972[26] <= _T_11742 @[RegMapper.scala 155:24] + _T_11972[27] <= _T_11745 @[RegMapper.scala 155:24] + _T_11972[28] <= _T_11748 @[RegMapper.scala 155:24] + _T_11972[29] <= _T_11751 @[RegMapper.scala 155:24] + _T_11972[30] <= _T_11754 @[RegMapper.scala 155:24] + _T_11972[31] <= _T_11757 @[RegMapper.scala 155:24] + _T_11972[32] <= _T_11768 @[RegMapper.scala 155:24] + _T_11972[33] <= _T_11779 @[RegMapper.scala 155:24] + _T_11972[34] <= _T_11790 @[RegMapper.scala 155:24] + _T_11972[35] <= _T_11801 @[RegMapper.scala 155:24] + _T_11972[36] <= _T_11812 @[RegMapper.scala 155:24] + _T_11972[37] <= _T_11823 @[RegMapper.scala 155:24] + _T_11972[38] <= _T_11834 @[RegMapper.scala 155:24] + _T_11972[39] <= _T_11845 @[RegMapper.scala 155:24] + _T_11972[40] <= _T_11856 @[RegMapper.scala 155:24] + _T_11972[41] <= _T_11867 @[RegMapper.scala 155:24] + _T_11972[42] <= _T_11878 @[RegMapper.scala 155:24] + _T_11972[43] <= _T_11889 @[RegMapper.scala 155:24] + _T_11972[44] <= _T_11900 @[RegMapper.scala 155:24] + _T_11972[45] <= _T_11911 @[RegMapper.scala 155:24] + _T_11972[46] <= _T_11918 @[RegMapper.scala 155:24] + _T_11972[47] <= _T_11921 @[RegMapper.scala 155:24] + _T_11972[48] <= _T_11924 @[RegMapper.scala 155:24] + _T_11972[49] <= _T_11927 @[RegMapper.scala 155:24] + _T_11972[50] <= _T_11930 @[RegMapper.scala 155:24] + _T_11972[51] <= _T_11933 @[RegMapper.scala 155:24] + _T_11972[52] <= _T_11936 @[RegMapper.scala 155:24] + _T_11972[53] <= _T_11939 @[RegMapper.scala 155:24] + _T_11972[54] <= _T_11942 @[RegMapper.scala 155:24] + _T_11972[55] <= _T_11945 @[RegMapper.scala 155:24] + _T_11972[56] <= _T_11948 @[RegMapper.scala 155:24] + _T_11972[57] <= _T_11951 @[RegMapper.scala 155:24] + _T_11972[58] <= _T_11954 @[RegMapper.scala 155:24] + _T_11972[59] <= _T_11957 @[RegMapper.scala 155:24] + _T_11972[60] <= _T_11960 @[RegMapper.scala 155:24] + _T_11972[61] <= _T_11963 @[RegMapper.scala 155:24] + _T_11972[62] <= _T_11966 @[RegMapper.scala 155:24] + _T_11972[63] <= _T_11969 @[RegMapper.scala 155:24] + node _T_12040 = eq(_T_1846, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12041 = and(_T_2710[92], _T_2710[91]) @[RegMapper.scala 156:98] + node _T_12042 = and(_T_12041, _T_2710[90]) @[RegMapper.scala 156:98] + node _T_12043 = and(_T_12042, _T_2710[89]) @[RegMapper.scala 156:98] + node _T_12044 = and(_T_12043, _T_2710[88]) @[RegMapper.scala 156:98] + node _T_12045 = and(_T_12044, _T_2710[87]) @[RegMapper.scala 156:98] + node _T_12046 = and(_T_12045, _T_2710[86]) @[RegMapper.scala 156:98] + node _T_12047 = and(_T_12046, _T_2710[85]) @[RegMapper.scala 156:98] + node _T_12048 = and(_T_12047, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12049 = or(_T_12040, _T_12048) @[RegMapper.scala 156:82] + node _T_12051 = eq(_T_1828, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12052 = and(_T_2710[76], _T_2710[75]) @[RegMapper.scala 156:98] + node _T_12053 = and(_T_12052, _T_2710[74]) @[RegMapper.scala 156:98] + node _T_12054 = and(_T_12053, _T_2710[73]) @[RegMapper.scala 156:98] + node _T_12055 = and(_T_12054, _T_2710[72]) @[RegMapper.scala 156:98] + node _T_12056 = and(_T_12055, _T_2710[71]) @[RegMapper.scala 156:98] + node _T_12057 = and(_T_12056, _T_2710[70]) @[RegMapper.scala 156:98] + node _T_12058 = and(_T_12057, _T_2710[69]) @[RegMapper.scala 156:98] + node _T_12059 = and(_T_12058, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12060 = or(_T_12051, _T_12059) @[RegMapper.scala 156:82] + node _T_12062 = eq(_T_1891, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12063 = and(_T_2710[125], _T_2710[124]) @[RegMapper.scala 156:98] + node _T_12064 = and(_T_12063, _T_2710[123]) @[RegMapper.scala 156:98] + node _T_12065 = and(_T_12064, _T_2710[122]) @[RegMapper.scala 156:98] + node _T_12066 = and(_T_12065, _T_2710[121]) @[RegMapper.scala 156:98] + node _T_12067 = and(_T_12066, _T_2710[120]) @[RegMapper.scala 156:98] + node _T_12068 = and(_T_12067, _T_2710[119]) @[RegMapper.scala 156:98] + node _T_12069 = and(_T_12068, _T_2710[118]) @[RegMapper.scala 156:98] + node _T_12070 = and(_T_12069, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12071 = or(_T_12062, _T_12070) @[RegMapper.scala 156:82] + node _T_12073 = eq(_T_1954, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12074 = and(_T_2710[181], _T_2710[180]) @[RegMapper.scala 156:98] + node _T_12075 = and(_T_12074, _T_2710[179]) @[RegMapper.scala 156:98] + node _T_12076 = and(_T_12075, _T_2710[178]) @[RegMapper.scala 156:98] + node _T_12077 = and(_T_12076, _T_2710[177]) @[RegMapper.scala 156:98] + node _T_12078 = and(_T_12077, _T_2710[176]) @[RegMapper.scala 156:98] + node _T_12079 = and(_T_12078, _T_2710[175]) @[RegMapper.scala 156:98] + node _T_12080 = and(_T_12079, _T_2710[174]) @[RegMapper.scala 156:98] + node _T_12081 = and(_T_12080, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12082 = or(_T_12073, _T_12081) @[RegMapper.scala 156:82] + node _T_12084 = eq(_T_1765, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12085 = and(_T_2710[31], _T_2710[30]) @[RegMapper.scala 156:98] + node _T_12086 = and(_T_12085, _T_2710[29]) @[RegMapper.scala 156:98] + node _T_12087 = and(_T_12086, _T_2710[28]) @[RegMapper.scala 156:98] + node _T_12088 = and(_T_12087, _T_2710[27]) @[RegMapper.scala 156:98] + node _T_12089 = and(_T_12088, _T_2710[26]) @[RegMapper.scala 156:98] + node _T_12090 = and(_T_12089, _T_2710[25]) @[RegMapper.scala 156:98] + node _T_12091 = and(_T_12090, _T_2710[24]) @[RegMapper.scala 156:98] + node _T_12092 = and(_T_12091, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12093 = or(_T_12084, _T_12092) @[RegMapper.scala 156:82] + node _T_12095 = eq(_T_1774, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12096 = and(_T_2710[39], _T_2710[38]) @[RegMapper.scala 156:98] + node _T_12097 = and(_T_12096, _T_2710[37]) @[RegMapper.scala 156:98] + node _T_12098 = and(_T_12097, _T_2710[36]) @[RegMapper.scala 156:98] + node _T_12099 = and(_T_12098, _T_2710[35]) @[RegMapper.scala 156:98] + node _T_12100 = and(_T_12099, _T_2710[34]) @[RegMapper.scala 156:98] + node _T_12101 = and(_T_12100, _T_2710[33]) @[RegMapper.scala 156:98] + node _T_12102 = and(_T_12101, _T_2710[32]) @[RegMapper.scala 156:98] + node _T_12103 = and(_T_12102, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12104 = or(_T_12095, _T_12103) @[RegMapper.scala 156:82] + node _T_12106 = eq(_T_1837, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12107 = and(_T_2710[84], _T_2710[83]) @[RegMapper.scala 156:98] + node _T_12108 = and(_T_12107, _T_2710[82]) @[RegMapper.scala 156:98] + node _T_12109 = and(_T_12108, _T_2710[81]) @[RegMapper.scala 156:98] + node _T_12110 = and(_T_12109, _T_2710[80]) @[RegMapper.scala 156:98] + node _T_12111 = and(_T_12110, _T_2710[79]) @[RegMapper.scala 156:98] + node _T_12112 = and(_T_12111, _T_2710[78]) @[RegMapper.scala 156:98] + node _T_12113 = and(_T_12112, _T_2710[77]) @[RegMapper.scala 156:98] + node _T_12114 = and(_T_12113, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12115 = or(_T_12106, _T_12114) @[RegMapper.scala 156:82] + node _T_12117 = eq(_T_1900, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12118 = and(_T_2710[133], _T_2710[132]) @[RegMapper.scala 156:98] + node _T_12119 = and(_T_12118, _T_2710[131]) @[RegMapper.scala 156:98] + node _T_12120 = and(_T_12119, _T_2710[130]) @[RegMapper.scala 156:98] + node _T_12121 = and(_T_12120, _T_2710[129]) @[RegMapper.scala 156:98] + node _T_12122 = and(_T_12121, _T_2710[128]) @[RegMapper.scala 156:98] + node _T_12123 = and(_T_12122, _T_2710[127]) @[RegMapper.scala 156:98] + node _T_12124 = and(_T_12123, _T_2710[126]) @[RegMapper.scala 156:98] + node _T_12125 = and(_T_12124, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12126 = or(_T_12117, _T_12125) @[RegMapper.scala 156:82] + node _T_12128 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12129 = or(_T_12128, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12131 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12132 = or(_T_12131, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12134 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12135 = or(_T_12134, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12137 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12138 = or(_T_12137, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12140 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12141 = or(_T_12140, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12143 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12144 = or(_T_12143, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12146 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12147 = or(_T_12146, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12149 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12150 = or(_T_12149, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12152 = eq(_T_1864, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12153 = and(_T_2710[101], UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12154 = or(_T_12152, _T_12153) @[RegMapper.scala 156:82] + node _T_12156 = eq(_T_1810, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12157 = and(_T_2710[60], UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12158 = or(_T_12156, _T_12157) @[RegMapper.scala 156:82] + node _T_12160 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12161 = or(_T_12160, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12163 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12164 = or(_T_12163, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12166 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12167 = or(_T_12166, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12169 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12170 = or(_T_12169, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12172 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12173 = or(_T_12172, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12175 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12176 = or(_T_12175, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12178 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12179 = or(_T_12178, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12181 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12182 = or(_T_12181, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12184 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12185 = or(_T_12184, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12187 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12188 = or(_T_12187, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12190 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12191 = or(_T_12190, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12193 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12194 = or(_T_12193, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12196 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12197 = or(_T_12196, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12199 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12200 = or(_T_12199, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12202 = eq(_T_1819, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12203 = and(_T_2710[68], _T_2710[67]) @[RegMapper.scala 156:98] + node _T_12204 = and(_T_12203, _T_2710[66]) @[RegMapper.scala 156:98] + node _T_12205 = and(_T_12204, _T_2710[65]) @[RegMapper.scala 156:98] + node _T_12206 = and(_T_12205, _T_2710[64]) @[RegMapper.scala 156:98] + node _T_12207 = and(_T_12206, _T_2710[63]) @[RegMapper.scala 156:98] + node _T_12208 = and(_T_12207, _T_2710[62]) @[RegMapper.scala 156:98] + node _T_12209 = and(_T_12208, _T_2710[61]) @[RegMapper.scala 156:98] + node _T_12210 = and(_T_12209, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12211 = or(_T_12202, _T_12210) @[RegMapper.scala 156:82] + node _T_12213 = eq(_T_1747, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12214 = and(_T_2710[15], _T_2710[14]) @[RegMapper.scala 156:98] + node _T_12215 = and(_T_12214, _T_2710[13]) @[RegMapper.scala 156:98] + node _T_12216 = and(_T_12215, _T_2710[12]) @[RegMapper.scala 156:98] + node _T_12217 = and(_T_12216, _T_2710[11]) @[RegMapper.scala 156:98] + node _T_12218 = and(_T_12217, _T_2710[10]) @[RegMapper.scala 156:98] + node _T_12219 = and(_T_12218, _T_2710[9]) @[RegMapper.scala 156:98] + node _T_12220 = and(_T_12219, _T_2710[8]) @[RegMapper.scala 156:98] + node _T_12221 = and(_T_12220, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12222 = or(_T_12213, _T_12221) @[RegMapper.scala 156:82] + node _T_12224 = eq(_T_1927, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12225 = and(_T_2710[157], _T_2710[156]) @[RegMapper.scala 156:98] + node _T_12226 = and(_T_12225, _T_2710[155]) @[RegMapper.scala 156:98] + node _T_12227 = and(_T_12226, _T_2710[154]) @[RegMapper.scala 156:98] + node _T_12228 = and(_T_12227, _T_2710[153]) @[RegMapper.scala 156:98] + node _T_12229 = and(_T_12228, _T_2710[152]) @[RegMapper.scala 156:98] + node _T_12230 = and(_T_12229, _T_2710[151]) @[RegMapper.scala 156:98] + node _T_12231 = and(_T_12230, _T_2710[150]) @[RegMapper.scala 156:98] + node _T_12232 = and(_T_12231, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12233 = or(_T_12224, _T_12232) @[RegMapper.scala 156:82] + node _T_12235 = eq(_T_1882, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12236 = and(_T_2710[117], _T_2710[116]) @[RegMapper.scala 156:98] + node _T_12237 = and(_T_12236, _T_2710[115]) @[RegMapper.scala 156:98] + node _T_12238 = and(_T_12237, _T_2710[114]) @[RegMapper.scala 156:98] + node _T_12239 = and(_T_12238, _T_2710[113]) @[RegMapper.scala 156:98] + node _T_12240 = and(_T_12239, _T_2710[112]) @[RegMapper.scala 156:98] + node _T_12241 = and(_T_12240, _T_2710[111]) @[RegMapper.scala 156:98] + node _T_12242 = and(_T_12241, _T_2710[110]) @[RegMapper.scala 156:98] + node _T_12243 = and(_T_12242, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12244 = or(_T_12235, _T_12243) @[RegMapper.scala 156:82] + node _T_12246 = eq(_T_1801, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12247 = and(_T_2710[59], _T_2710[58]) @[RegMapper.scala 156:98] + node _T_12248 = and(_T_12247, _T_2710[57]) @[RegMapper.scala 156:98] + node _T_12249 = and(_T_12248, _T_2710[56]) @[RegMapper.scala 156:98] + node _T_12250 = and(_T_12249, _T_2710[55]) @[RegMapper.scala 156:98] + node _T_12251 = and(_T_12250, _T_2710[54]) @[RegMapper.scala 156:98] + node _T_12252 = and(_T_12251, _T_2710[53]) @[RegMapper.scala 156:98] + node _T_12253 = and(_T_12252, _T_2710[52]) @[RegMapper.scala 156:98] + node _T_12254 = and(_T_12253, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12255 = or(_T_12246, _T_12254) @[RegMapper.scala 156:82] + node _T_12257 = eq(_T_1756, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12258 = and(_T_2710[23], _T_2710[22]) @[RegMapper.scala 156:98] + node _T_12259 = and(_T_12258, _T_2710[21]) @[RegMapper.scala 156:98] + node _T_12260 = and(_T_12259, _T_2710[20]) @[RegMapper.scala 156:98] + node _T_12261 = and(_T_12260, _T_2710[19]) @[RegMapper.scala 156:98] + node _T_12262 = and(_T_12261, _T_2710[18]) @[RegMapper.scala 156:98] + node _T_12263 = and(_T_12262, _T_2710[17]) @[RegMapper.scala 156:98] + node _T_12264 = and(_T_12263, _T_2710[16]) @[RegMapper.scala 156:98] + node _T_12265 = and(_T_12264, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12266 = or(_T_12257, _T_12265) @[RegMapper.scala 156:82] + node _T_12268 = eq(_T_1936, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12269 = and(_T_2710[165], _T_2710[164]) @[RegMapper.scala 156:98] + node _T_12270 = and(_T_12269, _T_2710[163]) @[RegMapper.scala 156:98] + node _T_12271 = and(_T_12270, _T_2710[162]) @[RegMapper.scala 156:98] + node _T_12272 = and(_T_12271, _T_2710[161]) @[RegMapper.scala 156:98] + node _T_12273 = and(_T_12272, _T_2710[160]) @[RegMapper.scala 156:98] + node _T_12274 = and(_T_12273, _T_2710[159]) @[RegMapper.scala 156:98] + node _T_12275 = and(_T_12274, _T_2710[158]) @[RegMapper.scala 156:98] + node _T_12276 = and(_T_12275, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12277 = or(_T_12268, _T_12276) @[RegMapper.scala 156:82] + node _T_12279 = eq(_T_1918, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12280 = and(_T_2710[149], _T_2710[148]) @[RegMapper.scala 156:98] + node _T_12281 = and(_T_12280, _T_2710[147]) @[RegMapper.scala 156:98] + node _T_12282 = and(_T_12281, _T_2710[146]) @[RegMapper.scala 156:98] + node _T_12283 = and(_T_12282, _T_2710[145]) @[RegMapper.scala 156:98] + node _T_12284 = and(_T_12283, _T_2710[144]) @[RegMapper.scala 156:98] + node _T_12285 = and(_T_12284, _T_2710[143]) @[RegMapper.scala 156:98] + node _T_12286 = and(_T_12285, _T_2710[142]) @[RegMapper.scala 156:98] + node _T_12287 = and(_T_12286, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12288 = or(_T_12279, _T_12287) @[RegMapper.scala 156:82] + node _T_12290 = eq(_T_1873, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12291 = and(_T_2710[109], _T_2710[108]) @[RegMapper.scala 156:98] + node _T_12292 = and(_T_12291, _T_2710[107]) @[RegMapper.scala 156:98] + node _T_12293 = and(_T_12292, _T_2710[106]) @[RegMapper.scala 156:98] + node _T_12294 = and(_T_12293, _T_2710[105]) @[RegMapper.scala 156:98] + node _T_12295 = and(_T_12294, _T_2710[104]) @[RegMapper.scala 156:98] + node _T_12296 = and(_T_12295, _T_2710[103]) @[RegMapper.scala 156:98] + node _T_12297 = and(_T_12296, _T_2710[102]) @[RegMapper.scala 156:98] + node _T_12298 = and(_T_12297, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12299 = or(_T_12290, _T_12298) @[RegMapper.scala 156:82] + node _T_12301 = eq(_T_1783, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12302 = and(_T_2710[47], _T_2710[46]) @[RegMapper.scala 156:98] + node _T_12303 = and(_T_12302, _T_2710[45]) @[RegMapper.scala 156:98] + node _T_12304 = and(_T_12303, _T_2710[44]) @[RegMapper.scala 156:98] + node _T_12305 = and(_T_12304, _T_2710[43]) @[RegMapper.scala 156:98] + node _T_12306 = and(_T_12305, _T_2710[42]) @[RegMapper.scala 156:98] + node _T_12307 = and(_T_12306, _T_2710[41]) @[RegMapper.scala 156:98] + node _T_12308 = and(_T_12307, _T_2710[40]) @[RegMapper.scala 156:98] + node _T_12309 = and(_T_12308, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12310 = or(_T_12301, _T_12309) @[RegMapper.scala 156:82] + node _T_12312 = eq(_T_1855, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12313 = and(_T_2710[100], _T_2710[99]) @[RegMapper.scala 156:98] + node _T_12314 = and(_T_12313, _T_2710[98]) @[RegMapper.scala 156:98] + node _T_12315 = and(_T_12314, _T_2710[97]) @[RegMapper.scala 156:98] + node _T_12316 = and(_T_12315, _T_2710[96]) @[RegMapper.scala 156:98] + node _T_12317 = and(_T_12316, _T_2710[95]) @[RegMapper.scala 156:98] + node _T_12318 = and(_T_12317, _T_2710[94]) @[RegMapper.scala 156:98] + node _T_12319 = and(_T_12318, _T_2710[93]) @[RegMapper.scala 156:98] + node _T_12320 = and(_T_12319, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12321 = or(_T_12312, _T_12320) @[RegMapper.scala 156:82] + node _T_12323 = eq(_T_1909, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12324 = and(_T_2710[141], _T_2710[140]) @[RegMapper.scala 156:98] + node _T_12325 = and(_T_12324, _T_2710[139]) @[RegMapper.scala 156:98] + node _T_12326 = and(_T_12325, _T_2710[138]) @[RegMapper.scala 156:98] + node _T_12327 = and(_T_12326, _T_2710[137]) @[RegMapper.scala 156:98] + node _T_12328 = and(_T_12327, _T_2710[136]) @[RegMapper.scala 156:98] + node _T_12329 = and(_T_12328, _T_2710[135]) @[RegMapper.scala 156:98] + node _T_12330 = and(_T_12329, _T_2710[134]) @[RegMapper.scala 156:98] + node _T_12331 = and(_T_12330, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12332 = or(_T_12323, _T_12331) @[RegMapper.scala 156:82] + node _T_12334 = eq(_T_1945, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12335 = and(_T_2710[173], _T_2710[172]) @[RegMapper.scala 156:98] + node _T_12336 = and(_T_12335, _T_2710[171]) @[RegMapper.scala 156:98] + node _T_12337 = and(_T_12336, _T_2710[170]) @[RegMapper.scala 156:98] + node _T_12338 = and(_T_12337, _T_2710[169]) @[RegMapper.scala 156:98] + node _T_12339 = and(_T_12338, _T_2710[168]) @[RegMapper.scala 156:98] + node _T_12340 = and(_T_12339, _T_2710[167]) @[RegMapper.scala 156:98] + node _T_12341 = and(_T_12340, _T_2710[166]) @[RegMapper.scala 156:98] + node _T_12342 = and(_T_12341, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12343 = or(_T_12334, _T_12342) @[RegMapper.scala 156:82] + node _T_12345 = eq(_T_1738, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12346 = and(_T_2710[7], _T_2710[6]) @[RegMapper.scala 156:98] + node _T_12347 = and(_T_12346, _T_2710[5]) @[RegMapper.scala 156:98] + node _T_12348 = and(_T_12347, _T_2710[4]) @[RegMapper.scala 156:98] + node _T_12349 = and(_T_12348, _T_2710[3]) @[RegMapper.scala 156:98] + node _T_12350 = and(_T_12349, _T_2710[2]) @[RegMapper.scala 156:98] + node _T_12351 = and(_T_12350, _T_2710[1]) @[RegMapper.scala 156:98] + node _T_12352 = and(_T_12351, _T_2710[0]) @[RegMapper.scala 156:98] + node _T_12353 = and(_T_12352, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12354 = or(_T_12345, _T_12353) @[RegMapper.scala 156:82] + node _T_12356 = eq(_T_1792, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12357 = and(_T_2710[51], _T_2710[50]) @[RegMapper.scala 156:98] + node _T_12358 = and(_T_12357, _T_2710[49]) @[RegMapper.scala 156:98] + node _T_12359 = and(_T_12358, _T_2710[48]) @[RegMapper.scala 156:98] + node _T_12360 = and(_T_12359, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_12361 = or(_T_12356, _T_12360) @[RegMapper.scala 156:82] + node _T_12363 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12364 = or(_T_12363, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12366 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12367 = or(_T_12366, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12369 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12370 = or(_T_12369, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12372 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12373 = or(_T_12372, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12375 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12376 = or(_T_12375, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12378 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12379 = or(_T_12378, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12381 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12382 = or(_T_12381, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12384 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12385 = or(_T_12384, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12387 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12388 = or(_T_12387, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12390 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12391 = or(_T_12390, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12393 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12394 = or(_T_12393, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12396 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12397 = or(_T_12396, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12399 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12400 = or(_T_12399, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12402 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12403 = or(_T_12402, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12405 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12406 = or(_T_12405, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12408 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12409 = or(_T_12408, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_12411 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_12412 = or(_T_12411, UInt<1>("h01")) @[RegMapper.scala 156:82] + wire _T_12415 : UInt<1>[64] @[RegMapper.scala 156:24] + _T_12415 is invalid @[RegMapper.scala 156:24] + _T_12415[0] <= _T_12049 @[RegMapper.scala 156:24] + _T_12415[1] <= _T_12060 @[RegMapper.scala 156:24] + _T_12415[2] <= _T_12071 @[RegMapper.scala 156:24] + _T_12415[3] <= _T_12082 @[RegMapper.scala 156:24] + _T_12415[4] <= _T_12093 @[RegMapper.scala 156:24] + _T_12415[5] <= _T_12104 @[RegMapper.scala 156:24] + _T_12415[6] <= _T_12115 @[RegMapper.scala 156:24] + _T_12415[7] <= _T_12126 @[RegMapper.scala 156:24] + _T_12415[8] <= _T_12129 @[RegMapper.scala 156:24] + _T_12415[9] <= _T_12132 @[RegMapper.scala 156:24] + _T_12415[10] <= _T_12135 @[RegMapper.scala 156:24] + _T_12415[11] <= _T_12138 @[RegMapper.scala 156:24] + _T_12415[12] <= _T_12141 @[RegMapper.scala 156:24] + _T_12415[13] <= _T_12144 @[RegMapper.scala 156:24] + _T_12415[14] <= _T_12147 @[RegMapper.scala 156:24] + _T_12415[15] <= _T_12150 @[RegMapper.scala 156:24] + _T_12415[16] <= _T_12154 @[RegMapper.scala 156:24] + _T_12415[17] <= _T_12158 @[RegMapper.scala 156:24] + _T_12415[18] <= _T_12161 @[RegMapper.scala 156:24] + _T_12415[19] <= _T_12164 @[RegMapper.scala 156:24] + _T_12415[20] <= _T_12167 @[RegMapper.scala 156:24] + _T_12415[21] <= _T_12170 @[RegMapper.scala 156:24] + _T_12415[22] <= _T_12173 @[RegMapper.scala 156:24] + _T_12415[23] <= _T_12176 @[RegMapper.scala 156:24] + _T_12415[24] <= _T_12179 @[RegMapper.scala 156:24] + _T_12415[25] <= _T_12182 @[RegMapper.scala 156:24] + _T_12415[26] <= _T_12185 @[RegMapper.scala 156:24] + _T_12415[27] <= _T_12188 @[RegMapper.scala 156:24] + _T_12415[28] <= _T_12191 @[RegMapper.scala 156:24] + _T_12415[29] <= _T_12194 @[RegMapper.scala 156:24] + _T_12415[30] <= _T_12197 @[RegMapper.scala 156:24] + _T_12415[31] <= _T_12200 @[RegMapper.scala 156:24] + _T_12415[32] <= _T_12211 @[RegMapper.scala 156:24] + _T_12415[33] <= _T_12222 @[RegMapper.scala 156:24] + _T_12415[34] <= _T_12233 @[RegMapper.scala 156:24] + _T_12415[35] <= _T_12244 @[RegMapper.scala 156:24] + _T_12415[36] <= _T_12255 @[RegMapper.scala 156:24] + _T_12415[37] <= _T_12266 @[RegMapper.scala 156:24] + _T_12415[38] <= _T_12277 @[RegMapper.scala 156:24] + _T_12415[39] <= _T_12288 @[RegMapper.scala 156:24] + _T_12415[40] <= _T_12299 @[RegMapper.scala 156:24] + _T_12415[41] <= _T_12310 @[RegMapper.scala 156:24] + _T_12415[42] <= _T_12321 @[RegMapper.scala 156:24] + _T_12415[43] <= _T_12332 @[RegMapper.scala 156:24] + _T_12415[44] <= _T_12343 @[RegMapper.scala 156:24] + _T_12415[45] <= _T_12354 @[RegMapper.scala 156:24] + _T_12415[46] <= _T_12361 @[RegMapper.scala 156:24] + _T_12415[47] <= _T_12364 @[RegMapper.scala 156:24] + _T_12415[48] <= _T_12367 @[RegMapper.scala 156:24] + _T_12415[49] <= _T_12370 @[RegMapper.scala 156:24] + _T_12415[50] <= _T_12373 @[RegMapper.scala 156:24] + _T_12415[51] <= _T_12376 @[RegMapper.scala 156:24] + _T_12415[52] <= _T_12379 @[RegMapper.scala 156:24] + _T_12415[53] <= _T_12382 @[RegMapper.scala 156:24] + _T_12415[54] <= _T_12385 @[RegMapper.scala 156:24] + _T_12415[55] <= _T_12388 @[RegMapper.scala 156:24] + _T_12415[56] <= _T_12391 @[RegMapper.scala 156:24] + _T_12415[57] <= _T_12394 @[RegMapper.scala 156:24] + _T_12415[58] <= _T_12397 @[RegMapper.scala 156:24] + _T_12415[59] <= _T_12400 @[RegMapper.scala 156:24] + _T_12415[60] <= _T_12403 @[RegMapper.scala 156:24] + _T_12415[61] <= _T_12406 @[RegMapper.scala 156:24] + _T_12415[62] <= _T_12409 @[RegMapper.scala 156:24] + _T_12415[63] <= _T_12412 @[RegMapper.scala 156:24] + node _T_12483 = eq(_T_1846, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12484 = and(_T_2898[92], _T_2898[91]) @[RegMapper.scala 157:98] + node _T_12485 = and(_T_12484, _T_2898[90]) @[RegMapper.scala 157:98] + node _T_12486 = and(_T_12485, _T_2898[89]) @[RegMapper.scala 157:98] + node _T_12487 = and(_T_12486, _T_2898[88]) @[RegMapper.scala 157:98] + node _T_12488 = and(_T_12487, _T_2898[87]) @[RegMapper.scala 157:98] + node _T_12489 = and(_T_12488, _T_2898[86]) @[RegMapper.scala 157:98] + node _T_12490 = and(_T_12489, _T_2898[85]) @[RegMapper.scala 157:98] + node _T_12491 = and(_T_12490, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12492 = or(_T_12483, _T_12491) @[RegMapper.scala 157:82] + node _T_12494 = eq(_T_1828, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12495 = and(_T_2898[76], _T_2898[75]) @[RegMapper.scala 157:98] + node _T_12496 = and(_T_12495, _T_2898[74]) @[RegMapper.scala 157:98] + node _T_12497 = and(_T_12496, _T_2898[73]) @[RegMapper.scala 157:98] + node _T_12498 = and(_T_12497, _T_2898[72]) @[RegMapper.scala 157:98] + node _T_12499 = and(_T_12498, _T_2898[71]) @[RegMapper.scala 157:98] + node _T_12500 = and(_T_12499, _T_2898[70]) @[RegMapper.scala 157:98] + node _T_12501 = and(_T_12500, _T_2898[69]) @[RegMapper.scala 157:98] + node _T_12502 = and(_T_12501, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12503 = or(_T_12494, _T_12502) @[RegMapper.scala 157:82] + node _T_12505 = eq(_T_1891, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12506 = and(_T_2898[125], _T_2898[124]) @[RegMapper.scala 157:98] + node _T_12507 = and(_T_12506, _T_2898[123]) @[RegMapper.scala 157:98] + node _T_12508 = and(_T_12507, _T_2898[122]) @[RegMapper.scala 157:98] + node _T_12509 = and(_T_12508, _T_2898[121]) @[RegMapper.scala 157:98] + node _T_12510 = and(_T_12509, _T_2898[120]) @[RegMapper.scala 157:98] + node _T_12511 = and(_T_12510, _T_2898[119]) @[RegMapper.scala 157:98] + node _T_12512 = and(_T_12511, _T_2898[118]) @[RegMapper.scala 157:98] + node _T_12513 = and(_T_12512, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12514 = or(_T_12505, _T_12513) @[RegMapper.scala 157:82] + node _T_12516 = eq(_T_1954, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12517 = and(_T_2898[181], _T_2898[180]) @[RegMapper.scala 157:98] + node _T_12518 = and(_T_12517, _T_2898[179]) @[RegMapper.scala 157:98] + node _T_12519 = and(_T_12518, _T_2898[178]) @[RegMapper.scala 157:98] + node _T_12520 = and(_T_12519, _T_2898[177]) @[RegMapper.scala 157:98] + node _T_12521 = and(_T_12520, _T_2898[176]) @[RegMapper.scala 157:98] + node _T_12522 = and(_T_12521, _T_2898[175]) @[RegMapper.scala 157:98] + node _T_12523 = and(_T_12522, _T_2898[174]) @[RegMapper.scala 157:98] + node _T_12524 = and(_T_12523, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12525 = or(_T_12516, _T_12524) @[RegMapper.scala 157:82] + node _T_12527 = eq(_T_1765, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12528 = and(_T_2898[31], _T_2898[30]) @[RegMapper.scala 157:98] + node _T_12529 = and(_T_12528, _T_2898[29]) @[RegMapper.scala 157:98] + node _T_12530 = and(_T_12529, _T_2898[28]) @[RegMapper.scala 157:98] + node _T_12531 = and(_T_12530, _T_2898[27]) @[RegMapper.scala 157:98] + node _T_12532 = and(_T_12531, _T_2898[26]) @[RegMapper.scala 157:98] + node _T_12533 = and(_T_12532, _T_2898[25]) @[RegMapper.scala 157:98] + node _T_12534 = and(_T_12533, _T_2898[24]) @[RegMapper.scala 157:98] + node _T_12535 = and(_T_12534, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12536 = or(_T_12527, _T_12535) @[RegMapper.scala 157:82] + node _T_12538 = eq(_T_1774, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12539 = and(_T_2898[39], _T_2898[38]) @[RegMapper.scala 157:98] + node _T_12540 = and(_T_12539, _T_2898[37]) @[RegMapper.scala 157:98] + node _T_12541 = and(_T_12540, _T_2898[36]) @[RegMapper.scala 157:98] + node _T_12542 = and(_T_12541, _T_2898[35]) @[RegMapper.scala 157:98] + node _T_12543 = and(_T_12542, _T_2898[34]) @[RegMapper.scala 157:98] + node _T_12544 = and(_T_12543, _T_2898[33]) @[RegMapper.scala 157:98] + node _T_12545 = and(_T_12544, _T_2898[32]) @[RegMapper.scala 157:98] + node _T_12546 = and(_T_12545, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12547 = or(_T_12538, _T_12546) @[RegMapper.scala 157:82] + node _T_12549 = eq(_T_1837, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12550 = and(_T_2898[84], _T_2898[83]) @[RegMapper.scala 157:98] + node _T_12551 = and(_T_12550, _T_2898[82]) @[RegMapper.scala 157:98] + node _T_12552 = and(_T_12551, _T_2898[81]) @[RegMapper.scala 157:98] + node _T_12553 = and(_T_12552, _T_2898[80]) @[RegMapper.scala 157:98] + node _T_12554 = and(_T_12553, _T_2898[79]) @[RegMapper.scala 157:98] + node _T_12555 = and(_T_12554, _T_2898[78]) @[RegMapper.scala 157:98] + node _T_12556 = and(_T_12555, _T_2898[77]) @[RegMapper.scala 157:98] + node _T_12557 = and(_T_12556, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12558 = or(_T_12549, _T_12557) @[RegMapper.scala 157:82] + node _T_12560 = eq(_T_1900, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12561 = and(_T_2898[133], _T_2898[132]) @[RegMapper.scala 157:98] + node _T_12562 = and(_T_12561, _T_2898[131]) @[RegMapper.scala 157:98] + node _T_12563 = and(_T_12562, _T_2898[130]) @[RegMapper.scala 157:98] + node _T_12564 = and(_T_12563, _T_2898[129]) @[RegMapper.scala 157:98] + node _T_12565 = and(_T_12564, _T_2898[128]) @[RegMapper.scala 157:98] + node _T_12566 = and(_T_12565, _T_2898[127]) @[RegMapper.scala 157:98] + node _T_12567 = and(_T_12566, _T_2898[126]) @[RegMapper.scala 157:98] + node _T_12568 = and(_T_12567, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12569 = or(_T_12560, _T_12568) @[RegMapper.scala 157:82] + node _T_12571 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12572 = or(_T_12571, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12574 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12575 = or(_T_12574, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12577 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12578 = or(_T_12577, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12580 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12581 = or(_T_12580, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12583 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12584 = or(_T_12583, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12586 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12587 = or(_T_12586, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12589 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12590 = or(_T_12589, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12592 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12593 = or(_T_12592, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12595 = eq(_T_1864, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12596 = and(_T_2898[101], UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12597 = or(_T_12595, _T_12596) @[RegMapper.scala 157:82] + node _T_12599 = eq(_T_1810, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12600 = and(_T_2898[60], UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12601 = or(_T_12599, _T_12600) @[RegMapper.scala 157:82] + node _T_12603 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12604 = or(_T_12603, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12606 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12607 = or(_T_12606, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12609 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12610 = or(_T_12609, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12612 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12613 = or(_T_12612, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12615 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12616 = or(_T_12615, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12618 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12619 = or(_T_12618, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12621 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12622 = or(_T_12621, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12624 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12625 = or(_T_12624, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12627 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12628 = or(_T_12627, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12630 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12631 = or(_T_12630, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12633 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12634 = or(_T_12633, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12636 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12637 = or(_T_12636, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12639 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12640 = or(_T_12639, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12642 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12643 = or(_T_12642, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12645 = eq(_T_1819, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12646 = and(_T_2898[68], _T_2898[67]) @[RegMapper.scala 157:98] + node _T_12647 = and(_T_12646, _T_2898[66]) @[RegMapper.scala 157:98] + node _T_12648 = and(_T_12647, _T_2898[65]) @[RegMapper.scala 157:98] + node _T_12649 = and(_T_12648, _T_2898[64]) @[RegMapper.scala 157:98] + node _T_12650 = and(_T_12649, _T_2898[63]) @[RegMapper.scala 157:98] + node _T_12651 = and(_T_12650, _T_2898[62]) @[RegMapper.scala 157:98] + node _T_12652 = and(_T_12651, _T_2898[61]) @[RegMapper.scala 157:98] + node _T_12653 = and(_T_12652, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12654 = or(_T_12645, _T_12653) @[RegMapper.scala 157:82] + node _T_12656 = eq(_T_1747, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12657 = and(_T_2898[15], _T_2898[14]) @[RegMapper.scala 157:98] + node _T_12658 = and(_T_12657, _T_2898[13]) @[RegMapper.scala 157:98] + node _T_12659 = and(_T_12658, _T_2898[12]) @[RegMapper.scala 157:98] + node _T_12660 = and(_T_12659, _T_2898[11]) @[RegMapper.scala 157:98] + node _T_12661 = and(_T_12660, _T_2898[10]) @[RegMapper.scala 157:98] + node _T_12662 = and(_T_12661, _T_2898[9]) @[RegMapper.scala 157:98] + node _T_12663 = and(_T_12662, _T_2898[8]) @[RegMapper.scala 157:98] + node _T_12664 = and(_T_12663, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12665 = or(_T_12656, _T_12664) @[RegMapper.scala 157:82] + node _T_12667 = eq(_T_1927, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12668 = and(_T_2898[157], _T_2898[156]) @[RegMapper.scala 157:98] + node _T_12669 = and(_T_12668, _T_2898[155]) @[RegMapper.scala 157:98] + node _T_12670 = and(_T_12669, _T_2898[154]) @[RegMapper.scala 157:98] + node _T_12671 = and(_T_12670, _T_2898[153]) @[RegMapper.scala 157:98] + node _T_12672 = and(_T_12671, _T_2898[152]) @[RegMapper.scala 157:98] + node _T_12673 = and(_T_12672, _T_2898[151]) @[RegMapper.scala 157:98] + node _T_12674 = and(_T_12673, _T_2898[150]) @[RegMapper.scala 157:98] + node _T_12675 = and(_T_12674, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12676 = or(_T_12667, _T_12675) @[RegMapper.scala 157:82] + node _T_12678 = eq(_T_1882, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12679 = and(_T_2898[117], _T_2898[116]) @[RegMapper.scala 157:98] + node _T_12680 = and(_T_12679, _T_2898[115]) @[RegMapper.scala 157:98] + node _T_12681 = and(_T_12680, _T_2898[114]) @[RegMapper.scala 157:98] + node _T_12682 = and(_T_12681, _T_2898[113]) @[RegMapper.scala 157:98] + node _T_12683 = and(_T_12682, _T_2898[112]) @[RegMapper.scala 157:98] + node _T_12684 = and(_T_12683, _T_2898[111]) @[RegMapper.scala 157:98] + node _T_12685 = and(_T_12684, _T_2898[110]) @[RegMapper.scala 157:98] + node _T_12686 = and(_T_12685, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12687 = or(_T_12678, _T_12686) @[RegMapper.scala 157:82] + node _T_12689 = eq(_T_1801, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12690 = and(_T_2898[59], _T_2898[58]) @[RegMapper.scala 157:98] + node _T_12691 = and(_T_12690, _T_2898[57]) @[RegMapper.scala 157:98] + node _T_12692 = and(_T_12691, _T_2898[56]) @[RegMapper.scala 157:98] + node _T_12693 = and(_T_12692, _T_2898[55]) @[RegMapper.scala 157:98] + node _T_12694 = and(_T_12693, _T_2898[54]) @[RegMapper.scala 157:98] + node _T_12695 = and(_T_12694, _T_2898[53]) @[RegMapper.scala 157:98] + node _T_12696 = and(_T_12695, _T_2898[52]) @[RegMapper.scala 157:98] + node _T_12697 = and(_T_12696, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12698 = or(_T_12689, _T_12697) @[RegMapper.scala 157:82] + node _T_12700 = eq(_T_1756, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12701 = and(_T_2898[23], _T_2898[22]) @[RegMapper.scala 157:98] + node _T_12702 = and(_T_12701, _T_2898[21]) @[RegMapper.scala 157:98] + node _T_12703 = and(_T_12702, _T_2898[20]) @[RegMapper.scala 157:98] + node _T_12704 = and(_T_12703, _T_2898[19]) @[RegMapper.scala 157:98] + node _T_12705 = and(_T_12704, _T_2898[18]) @[RegMapper.scala 157:98] + node _T_12706 = and(_T_12705, _T_2898[17]) @[RegMapper.scala 157:98] + node _T_12707 = and(_T_12706, _T_2898[16]) @[RegMapper.scala 157:98] + node _T_12708 = and(_T_12707, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12709 = or(_T_12700, _T_12708) @[RegMapper.scala 157:82] + node _T_12711 = eq(_T_1936, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12712 = and(_T_2898[165], _T_2898[164]) @[RegMapper.scala 157:98] + node _T_12713 = and(_T_12712, _T_2898[163]) @[RegMapper.scala 157:98] + node _T_12714 = and(_T_12713, _T_2898[162]) @[RegMapper.scala 157:98] + node _T_12715 = and(_T_12714, _T_2898[161]) @[RegMapper.scala 157:98] + node _T_12716 = and(_T_12715, _T_2898[160]) @[RegMapper.scala 157:98] + node _T_12717 = and(_T_12716, _T_2898[159]) @[RegMapper.scala 157:98] + node _T_12718 = and(_T_12717, _T_2898[158]) @[RegMapper.scala 157:98] + node _T_12719 = and(_T_12718, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12720 = or(_T_12711, _T_12719) @[RegMapper.scala 157:82] + node _T_12722 = eq(_T_1918, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12723 = and(_T_2898[149], _T_2898[148]) @[RegMapper.scala 157:98] + node _T_12724 = and(_T_12723, _T_2898[147]) @[RegMapper.scala 157:98] + node _T_12725 = and(_T_12724, _T_2898[146]) @[RegMapper.scala 157:98] + node _T_12726 = and(_T_12725, _T_2898[145]) @[RegMapper.scala 157:98] + node _T_12727 = and(_T_12726, _T_2898[144]) @[RegMapper.scala 157:98] + node _T_12728 = and(_T_12727, _T_2898[143]) @[RegMapper.scala 157:98] + node _T_12729 = and(_T_12728, _T_2898[142]) @[RegMapper.scala 157:98] + node _T_12730 = and(_T_12729, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12731 = or(_T_12722, _T_12730) @[RegMapper.scala 157:82] + node _T_12733 = eq(_T_1873, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12734 = and(_T_2898[109], _T_2898[108]) @[RegMapper.scala 157:98] + node _T_12735 = and(_T_12734, _T_2898[107]) @[RegMapper.scala 157:98] + node _T_12736 = and(_T_12735, _T_2898[106]) @[RegMapper.scala 157:98] + node _T_12737 = and(_T_12736, _T_2898[105]) @[RegMapper.scala 157:98] + node _T_12738 = and(_T_12737, _T_2898[104]) @[RegMapper.scala 157:98] + node _T_12739 = and(_T_12738, _T_2898[103]) @[RegMapper.scala 157:98] + node _T_12740 = and(_T_12739, _T_2898[102]) @[RegMapper.scala 157:98] + node _T_12741 = and(_T_12740, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12742 = or(_T_12733, _T_12741) @[RegMapper.scala 157:82] + node _T_12744 = eq(_T_1783, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12745 = and(_T_2898[47], _T_2898[46]) @[RegMapper.scala 157:98] + node _T_12746 = and(_T_12745, _T_2898[45]) @[RegMapper.scala 157:98] + node _T_12747 = and(_T_12746, _T_2898[44]) @[RegMapper.scala 157:98] + node _T_12748 = and(_T_12747, _T_2898[43]) @[RegMapper.scala 157:98] + node _T_12749 = and(_T_12748, _T_2898[42]) @[RegMapper.scala 157:98] + node _T_12750 = and(_T_12749, _T_2898[41]) @[RegMapper.scala 157:98] + node _T_12751 = and(_T_12750, _T_2898[40]) @[RegMapper.scala 157:98] + node _T_12752 = and(_T_12751, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12753 = or(_T_12744, _T_12752) @[RegMapper.scala 157:82] + node _T_12755 = eq(_T_1855, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12756 = and(_T_2898[100], _T_2898[99]) @[RegMapper.scala 157:98] + node _T_12757 = and(_T_12756, _T_2898[98]) @[RegMapper.scala 157:98] + node _T_12758 = and(_T_12757, _T_2898[97]) @[RegMapper.scala 157:98] + node _T_12759 = and(_T_12758, _T_2898[96]) @[RegMapper.scala 157:98] + node _T_12760 = and(_T_12759, _T_2898[95]) @[RegMapper.scala 157:98] + node _T_12761 = and(_T_12760, _T_2898[94]) @[RegMapper.scala 157:98] + node _T_12762 = and(_T_12761, _T_2898[93]) @[RegMapper.scala 157:98] + node _T_12763 = and(_T_12762, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12764 = or(_T_12755, _T_12763) @[RegMapper.scala 157:82] + node _T_12766 = eq(_T_1909, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12767 = and(_T_2898[141], _T_2898[140]) @[RegMapper.scala 157:98] + node _T_12768 = and(_T_12767, _T_2898[139]) @[RegMapper.scala 157:98] + node _T_12769 = and(_T_12768, _T_2898[138]) @[RegMapper.scala 157:98] + node _T_12770 = and(_T_12769, _T_2898[137]) @[RegMapper.scala 157:98] + node _T_12771 = and(_T_12770, _T_2898[136]) @[RegMapper.scala 157:98] + node _T_12772 = and(_T_12771, _T_2898[135]) @[RegMapper.scala 157:98] + node _T_12773 = and(_T_12772, _T_2898[134]) @[RegMapper.scala 157:98] + node _T_12774 = and(_T_12773, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12775 = or(_T_12766, _T_12774) @[RegMapper.scala 157:82] + node _T_12777 = eq(_T_1945, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12778 = and(_T_2898[173], _T_2898[172]) @[RegMapper.scala 157:98] + node _T_12779 = and(_T_12778, _T_2898[171]) @[RegMapper.scala 157:98] + node _T_12780 = and(_T_12779, _T_2898[170]) @[RegMapper.scala 157:98] + node _T_12781 = and(_T_12780, _T_2898[169]) @[RegMapper.scala 157:98] + node _T_12782 = and(_T_12781, _T_2898[168]) @[RegMapper.scala 157:98] + node _T_12783 = and(_T_12782, _T_2898[167]) @[RegMapper.scala 157:98] + node _T_12784 = and(_T_12783, _T_2898[166]) @[RegMapper.scala 157:98] + node _T_12785 = and(_T_12784, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12786 = or(_T_12777, _T_12785) @[RegMapper.scala 157:82] + node _T_12788 = eq(_T_1738, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12789 = and(_T_2898[7], _T_2898[6]) @[RegMapper.scala 157:98] + node _T_12790 = and(_T_12789, _T_2898[5]) @[RegMapper.scala 157:98] + node _T_12791 = and(_T_12790, _T_2898[4]) @[RegMapper.scala 157:98] + node _T_12792 = and(_T_12791, _T_2898[3]) @[RegMapper.scala 157:98] + node _T_12793 = and(_T_12792, _T_2898[2]) @[RegMapper.scala 157:98] + node _T_12794 = and(_T_12793, _T_2898[1]) @[RegMapper.scala 157:98] + node _T_12795 = and(_T_12794, _T_2898[0]) @[RegMapper.scala 157:98] + node _T_12796 = and(_T_12795, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12797 = or(_T_12788, _T_12796) @[RegMapper.scala 157:82] + node _T_12799 = eq(_T_1792, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12800 = and(_T_2898[51], _T_2898[50]) @[RegMapper.scala 157:98] + node _T_12801 = and(_T_12800, _T_2898[49]) @[RegMapper.scala 157:98] + node _T_12802 = and(_T_12801, _T_2898[48]) @[RegMapper.scala 157:98] + node _T_12803 = and(_T_12802, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_12804 = or(_T_12799, _T_12803) @[RegMapper.scala 157:82] + node _T_12806 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12807 = or(_T_12806, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12809 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12810 = or(_T_12809, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12812 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12813 = or(_T_12812, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12815 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12816 = or(_T_12815, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12818 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12819 = or(_T_12818, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12821 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12822 = or(_T_12821, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12824 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12825 = or(_T_12824, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12827 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12828 = or(_T_12827, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12830 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12831 = or(_T_12830, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12833 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12834 = or(_T_12833, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12836 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12837 = or(_T_12836, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12839 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12840 = or(_T_12839, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12842 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12843 = or(_T_12842, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12845 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12846 = or(_T_12845, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12848 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12849 = or(_T_12848, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12851 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12852 = or(_T_12851, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_12854 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_12855 = or(_T_12854, UInt<1>("h01")) @[RegMapper.scala 157:82] + wire _T_12858 : UInt<1>[64] @[RegMapper.scala 157:24] + _T_12858 is invalid @[RegMapper.scala 157:24] + _T_12858[0] <= _T_12492 @[RegMapper.scala 157:24] + _T_12858[1] <= _T_12503 @[RegMapper.scala 157:24] + _T_12858[2] <= _T_12514 @[RegMapper.scala 157:24] + _T_12858[3] <= _T_12525 @[RegMapper.scala 157:24] + _T_12858[4] <= _T_12536 @[RegMapper.scala 157:24] + _T_12858[5] <= _T_12547 @[RegMapper.scala 157:24] + _T_12858[6] <= _T_12558 @[RegMapper.scala 157:24] + _T_12858[7] <= _T_12569 @[RegMapper.scala 157:24] + _T_12858[8] <= _T_12572 @[RegMapper.scala 157:24] + _T_12858[9] <= _T_12575 @[RegMapper.scala 157:24] + _T_12858[10] <= _T_12578 @[RegMapper.scala 157:24] + _T_12858[11] <= _T_12581 @[RegMapper.scala 157:24] + _T_12858[12] <= _T_12584 @[RegMapper.scala 157:24] + _T_12858[13] <= _T_12587 @[RegMapper.scala 157:24] + _T_12858[14] <= _T_12590 @[RegMapper.scala 157:24] + _T_12858[15] <= _T_12593 @[RegMapper.scala 157:24] + _T_12858[16] <= _T_12597 @[RegMapper.scala 157:24] + _T_12858[17] <= _T_12601 @[RegMapper.scala 157:24] + _T_12858[18] <= _T_12604 @[RegMapper.scala 157:24] + _T_12858[19] <= _T_12607 @[RegMapper.scala 157:24] + _T_12858[20] <= _T_12610 @[RegMapper.scala 157:24] + _T_12858[21] <= _T_12613 @[RegMapper.scala 157:24] + _T_12858[22] <= _T_12616 @[RegMapper.scala 157:24] + _T_12858[23] <= _T_12619 @[RegMapper.scala 157:24] + _T_12858[24] <= _T_12622 @[RegMapper.scala 157:24] + _T_12858[25] <= _T_12625 @[RegMapper.scala 157:24] + _T_12858[26] <= _T_12628 @[RegMapper.scala 157:24] + _T_12858[27] <= _T_12631 @[RegMapper.scala 157:24] + _T_12858[28] <= _T_12634 @[RegMapper.scala 157:24] + _T_12858[29] <= _T_12637 @[RegMapper.scala 157:24] + _T_12858[30] <= _T_12640 @[RegMapper.scala 157:24] + _T_12858[31] <= _T_12643 @[RegMapper.scala 157:24] + _T_12858[32] <= _T_12654 @[RegMapper.scala 157:24] + _T_12858[33] <= _T_12665 @[RegMapper.scala 157:24] + _T_12858[34] <= _T_12676 @[RegMapper.scala 157:24] + _T_12858[35] <= _T_12687 @[RegMapper.scala 157:24] + _T_12858[36] <= _T_12698 @[RegMapper.scala 157:24] + _T_12858[37] <= _T_12709 @[RegMapper.scala 157:24] + _T_12858[38] <= _T_12720 @[RegMapper.scala 157:24] + _T_12858[39] <= _T_12731 @[RegMapper.scala 157:24] + _T_12858[40] <= _T_12742 @[RegMapper.scala 157:24] + _T_12858[41] <= _T_12753 @[RegMapper.scala 157:24] + _T_12858[42] <= _T_12764 @[RegMapper.scala 157:24] + _T_12858[43] <= _T_12775 @[RegMapper.scala 157:24] + _T_12858[44] <= _T_12786 @[RegMapper.scala 157:24] + _T_12858[45] <= _T_12797 @[RegMapper.scala 157:24] + _T_12858[46] <= _T_12804 @[RegMapper.scala 157:24] + _T_12858[47] <= _T_12807 @[RegMapper.scala 157:24] + _T_12858[48] <= _T_12810 @[RegMapper.scala 157:24] + _T_12858[49] <= _T_12813 @[RegMapper.scala 157:24] + _T_12858[50] <= _T_12816 @[RegMapper.scala 157:24] + _T_12858[51] <= _T_12819 @[RegMapper.scala 157:24] + _T_12858[52] <= _T_12822 @[RegMapper.scala 157:24] + _T_12858[53] <= _T_12825 @[RegMapper.scala 157:24] + _T_12858[54] <= _T_12828 @[RegMapper.scala 157:24] + _T_12858[55] <= _T_12831 @[RegMapper.scala 157:24] + _T_12858[56] <= _T_12834 @[RegMapper.scala 157:24] + _T_12858[57] <= _T_12837 @[RegMapper.scala 157:24] + _T_12858[58] <= _T_12840 @[RegMapper.scala 157:24] + _T_12858[59] <= _T_12843 @[RegMapper.scala 157:24] + _T_12858[60] <= _T_12846 @[RegMapper.scala 157:24] + _T_12858[61] <= _T_12849 @[RegMapper.scala 157:24] + _T_12858[62] <= _T_12852 @[RegMapper.scala 157:24] + _T_12858[63] <= _T_12855 @[RegMapper.scala 157:24] + node _T_12925 = bits(_T_1583.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_12926 = bits(_T_1583.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_12927 = bits(_T_1583.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_12928 = bits(_T_1583.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_12929 = bits(_T_1583.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_12930 = bits(_T_1583.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_12931 = bits(_T_1583.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_12932 = bits(_T_1583.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_12933 = bits(_T_1583.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_12934 = cat(_T_12927, _T_12926) @[Cat.scala 30:58] + node _T_12935 = cat(_T_12934, _T_12925) @[Cat.scala 30:58] + node _T_12936 = cat(_T_12933, _T_12930) @[Cat.scala 30:58] + node _T_12937 = cat(_T_12936, _T_12928) @[Cat.scala 30:58] + node _T_12938 = cat(_T_12937, _T_12935) @[Cat.scala 30:58] + node _T_12939 = bits(_T_1583.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_12940 = bits(_T_1583.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_12941 = bits(_T_1583.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_12942 = bits(_T_1583.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_12943 = bits(_T_1583.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_12944 = bits(_T_1583.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_12945 = bits(_T_1583.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_12946 = bits(_T_1583.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_12947 = bits(_T_1583.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_12948 = cat(_T_12941, _T_12940) @[Cat.scala 30:58] + node _T_12949 = cat(_T_12948, _T_12939) @[Cat.scala 30:58] + node _T_12950 = cat(_T_12947, _T_12944) @[Cat.scala 30:58] + node _T_12951 = cat(_T_12950, _T_12942) @[Cat.scala 30:58] + node _T_12952 = cat(_T_12951, _T_12949) @[Cat.scala 30:58] + node _T_12955 = mux(_T_1583.bits.read, _T_11529[_T_12938], _T_11972[_T_12938]) @[RegMapper.scala 160:21] + node _T_12958 = mux(_T_1583.bits.read, _T_12415[_T_12952], _T_12858[_T_12952]) @[RegMapper.scala 161:21] + node _T_12959 = and(_T_1583.ready, _T_12955) @[RegMapper.scala 164:32] + _T_1507.ready <= _T_12959 @[RegMapper.scala 164:17] + node _T_12960 = and(_T_1507.valid, _T_12955) @[RegMapper.scala 165:32] + _T_1583.valid <= _T_12960 @[RegMapper.scala 165:17] + node _T_12961 = and(_T_1547.ready, _T_12958) @[RegMapper.scala 166:32] + _T_1583.ready <= _T_12961 @[RegMapper.scala 166:17] + node _T_12962 = and(_T_1583.valid, _T_12958) @[RegMapper.scala 167:32] + _T_1547.valid <= _T_12962 @[RegMapper.scala 167:17] + node _T_12964 = dshl(UInt<1>("h01"), _T_12938) @[OneHot.scala 47:11] + node _T_12965 = cat(_T_1824, _T_1842) @[Cat.scala 30:58] + node _T_12966 = cat(_T_1950, _T_1887) @[Cat.scala 30:58] + node _T_12967 = cat(_T_12966, _T_12965) @[Cat.scala 30:58] + node _T_12968 = cat(_T_1770, _T_1761) @[Cat.scala 30:58] + node _T_12969 = cat(_T_1896, _T_1833) @[Cat.scala 30:58] + node _T_12970 = cat(_T_12969, _T_12968) @[Cat.scala 30:58] + node _T_12971 = cat(_T_12970, _T_12967) @[Cat.scala 30:58] + node _T_12972 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12973 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12974 = cat(_T_12973, _T_12972) @[Cat.scala 30:58] + node _T_12975 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12976 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12977 = cat(_T_12976, _T_12975) @[Cat.scala 30:58] + node _T_12978 = cat(_T_12977, _T_12974) @[Cat.scala 30:58] + node _T_12979 = cat(_T_12978, _T_12971) @[Cat.scala 30:58] + node _T_12980 = cat(_T_1806, _T_1860) @[Cat.scala 30:58] + node _T_12981 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12982 = cat(_T_12981, _T_12980) @[Cat.scala 30:58] + node _T_12983 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12984 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12985 = cat(_T_12984, _T_12983) @[Cat.scala 30:58] + node _T_12986 = cat(_T_12985, _T_12982) @[Cat.scala 30:58] + node _T_12987 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12988 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12989 = cat(_T_12988, _T_12987) @[Cat.scala 30:58] + node _T_12990 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12991 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_12992 = cat(_T_12991, _T_12990) @[Cat.scala 30:58] + node _T_12993 = cat(_T_12992, _T_12989) @[Cat.scala 30:58] + node _T_12994 = cat(_T_12993, _T_12986) @[Cat.scala 30:58] + node _T_12995 = cat(_T_12994, _T_12979) @[Cat.scala 30:58] + node _T_12996 = cat(_T_1743, _T_1815) @[Cat.scala 30:58] + node _T_12997 = cat(_T_1878, _T_1923) @[Cat.scala 30:58] + node _T_12998 = cat(_T_12997, _T_12996) @[Cat.scala 30:58] + node _T_12999 = cat(_T_1752, _T_1797) @[Cat.scala 30:58] + node _T_13000 = cat(_T_1914, _T_1932) @[Cat.scala 30:58] + node _T_13001 = cat(_T_13000, _T_12999) @[Cat.scala 30:58] + node _T_13002 = cat(_T_13001, _T_12998) @[Cat.scala 30:58] + node _T_13003 = cat(_T_1779, _T_1869) @[Cat.scala 30:58] + node _T_13004 = cat(_T_1905, _T_1851) @[Cat.scala 30:58] + node _T_13005 = cat(_T_13004, _T_13003) @[Cat.scala 30:58] + node _T_13006 = cat(_T_1734, _T_1941) @[Cat.scala 30:58] + node _T_13007 = cat(UInt<1>("h01"), _T_1788) @[Cat.scala 30:58] + node _T_13008 = cat(_T_13007, _T_13006) @[Cat.scala 30:58] + node _T_13009 = cat(_T_13008, _T_13005) @[Cat.scala 30:58] + node _T_13010 = cat(_T_13009, _T_13002) @[Cat.scala 30:58] + node _T_13011 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13012 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13013 = cat(_T_13012, _T_13011) @[Cat.scala 30:58] + node _T_13014 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13015 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13016 = cat(_T_13015, _T_13014) @[Cat.scala 30:58] + node _T_13017 = cat(_T_13016, _T_13013) @[Cat.scala 30:58] + node _T_13018 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13019 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13020 = cat(_T_13019, _T_13018) @[Cat.scala 30:58] + node _T_13021 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13022 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13023 = cat(_T_13022, _T_13021) @[Cat.scala 30:58] + node _T_13024 = cat(_T_13023, _T_13020) @[Cat.scala 30:58] + node _T_13025 = cat(_T_13024, _T_13017) @[Cat.scala 30:58] + node _T_13026 = cat(_T_13025, _T_13010) @[Cat.scala 30:58] + node _T_13027 = cat(_T_13026, _T_12995) @[Cat.scala 30:58] + node _T_13028 = and(_T_12964, _T_13027) @[RegMapper.scala 170:37] + node _T_13030 = dshl(UInt<1>("h01"), _T_12952) @[OneHot.scala 47:11] + node _T_13031 = cat(_T_1828, _T_1846) @[Cat.scala 30:58] + node _T_13032 = cat(_T_1954, _T_1891) @[Cat.scala 30:58] + node _T_13033 = cat(_T_13032, _T_13031) @[Cat.scala 30:58] + node _T_13034 = cat(_T_1774, _T_1765) @[Cat.scala 30:58] + node _T_13035 = cat(_T_1900, _T_1837) @[Cat.scala 30:58] + node _T_13036 = cat(_T_13035, _T_13034) @[Cat.scala 30:58] + node _T_13037 = cat(_T_13036, _T_13033) @[Cat.scala 30:58] + node _T_13038 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13039 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13040 = cat(_T_13039, _T_13038) @[Cat.scala 30:58] + node _T_13041 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13042 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13043 = cat(_T_13042, _T_13041) @[Cat.scala 30:58] + node _T_13044 = cat(_T_13043, _T_13040) @[Cat.scala 30:58] + node _T_13045 = cat(_T_13044, _T_13037) @[Cat.scala 30:58] + node _T_13046 = cat(_T_1810, _T_1864) @[Cat.scala 30:58] + node _T_13047 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13048 = cat(_T_13047, _T_13046) @[Cat.scala 30:58] + node _T_13049 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13050 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13051 = cat(_T_13050, _T_13049) @[Cat.scala 30:58] + node _T_13052 = cat(_T_13051, _T_13048) @[Cat.scala 30:58] + node _T_13053 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13054 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13055 = cat(_T_13054, _T_13053) @[Cat.scala 30:58] + node _T_13056 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13057 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13058 = cat(_T_13057, _T_13056) @[Cat.scala 30:58] + node _T_13059 = cat(_T_13058, _T_13055) @[Cat.scala 30:58] + node _T_13060 = cat(_T_13059, _T_13052) @[Cat.scala 30:58] + node _T_13061 = cat(_T_13060, _T_13045) @[Cat.scala 30:58] + node _T_13062 = cat(_T_1747, _T_1819) @[Cat.scala 30:58] + node _T_13063 = cat(_T_1882, _T_1927) @[Cat.scala 30:58] + node _T_13064 = cat(_T_13063, _T_13062) @[Cat.scala 30:58] + node _T_13065 = cat(_T_1756, _T_1801) @[Cat.scala 30:58] + node _T_13066 = cat(_T_1918, _T_1936) @[Cat.scala 30:58] + node _T_13067 = cat(_T_13066, _T_13065) @[Cat.scala 30:58] + node _T_13068 = cat(_T_13067, _T_13064) @[Cat.scala 30:58] + node _T_13069 = cat(_T_1783, _T_1873) @[Cat.scala 30:58] + node _T_13070 = cat(_T_1909, _T_1855) @[Cat.scala 30:58] + node _T_13071 = cat(_T_13070, _T_13069) @[Cat.scala 30:58] + node _T_13072 = cat(_T_1738, _T_1945) @[Cat.scala 30:58] + node _T_13073 = cat(UInt<1>("h01"), _T_1792) @[Cat.scala 30:58] + node _T_13074 = cat(_T_13073, _T_13072) @[Cat.scala 30:58] + node _T_13075 = cat(_T_13074, _T_13071) @[Cat.scala 30:58] + node _T_13076 = cat(_T_13075, _T_13068) @[Cat.scala 30:58] + node _T_13077 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13078 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13079 = cat(_T_13078, _T_13077) @[Cat.scala 30:58] + node _T_13080 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13081 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13082 = cat(_T_13081, _T_13080) @[Cat.scala 30:58] + node _T_13083 = cat(_T_13082, _T_13079) @[Cat.scala 30:58] + node _T_13084 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13085 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13086 = cat(_T_13085, _T_13084) @[Cat.scala 30:58] + node _T_13087 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13088 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_13089 = cat(_T_13088, _T_13087) @[Cat.scala 30:58] + node _T_13090 = cat(_T_13089, _T_13086) @[Cat.scala 30:58] + node _T_13091 = cat(_T_13090, _T_13083) @[Cat.scala 30:58] + node _T_13092 = cat(_T_13091, _T_13076) @[Cat.scala 30:58] + node _T_13093 = cat(_T_13092, _T_13061) @[Cat.scala 30:58] + node _T_13094 = and(_T_13030, _T_13093) @[RegMapper.scala 171:37] + node _T_13095 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13096 = and(_T_13095, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13097 = bits(_T_13028, 0, 0) @[RegMapper.scala 175:77] + node _T_13098 = and(_T_13096, _T_13097) @[RegMapper.scala 175:66] + node _T_13099 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13101 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13102 = and(_T_13099, _T_13101) @[RegMapper.scala 176:46] + node _T_13103 = bits(_T_13028, 0, 0) @[RegMapper.scala 176:77] + node _T_13104 = and(_T_13102, _T_13103) @[RegMapper.scala 176:66] + node _T_13105 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13106 = and(_T_13105, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13107 = bits(_T_13094, 0, 0) @[RegMapper.scala 177:77] + node _T_13108 = and(_T_13106, _T_13107) @[RegMapper.scala 177:66] + node _T_13109 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13111 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13112 = and(_T_13109, _T_13111) @[RegMapper.scala 178:46] + node _T_13113 = bits(_T_13094, 0, 0) @[RegMapper.scala 178:77] + node _T_13114 = and(_T_13112, _T_13113) @[RegMapper.scala 178:66] + node _T_13115 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13116 = and(_T_13115, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13117 = bits(_T_13028, 1, 1) @[RegMapper.scala 175:77] + node _T_13118 = and(_T_13116, _T_13117) @[RegMapper.scala 175:66] + node _T_13119 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13121 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13122 = and(_T_13119, _T_13121) @[RegMapper.scala 176:46] + node _T_13123 = bits(_T_13028, 1, 1) @[RegMapper.scala 176:77] + node _T_13124 = and(_T_13122, _T_13123) @[RegMapper.scala 176:66] + node _T_13125 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13126 = and(_T_13125, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13127 = bits(_T_13094, 1, 1) @[RegMapper.scala 177:77] + node _T_13128 = and(_T_13126, _T_13127) @[RegMapper.scala 177:66] + node _T_13129 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13131 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13132 = and(_T_13129, _T_13131) @[RegMapper.scala 178:46] + node _T_13133 = bits(_T_13094, 1, 1) @[RegMapper.scala 178:77] + node _T_13134 = and(_T_13132, _T_13133) @[RegMapper.scala 178:66] + node _T_13135 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13136 = and(_T_13135, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13137 = bits(_T_13028, 2, 2) @[RegMapper.scala 175:77] + node _T_13138 = and(_T_13136, _T_13137) @[RegMapper.scala 175:66] + node _T_13139 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13141 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13142 = and(_T_13139, _T_13141) @[RegMapper.scala 176:46] + node _T_13143 = bits(_T_13028, 2, 2) @[RegMapper.scala 176:77] + node _T_13144 = and(_T_13142, _T_13143) @[RegMapper.scala 176:66] + node _T_13145 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13146 = and(_T_13145, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13147 = bits(_T_13094, 2, 2) @[RegMapper.scala 177:77] + node _T_13148 = and(_T_13146, _T_13147) @[RegMapper.scala 177:66] + node _T_13149 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13151 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13152 = and(_T_13149, _T_13151) @[RegMapper.scala 178:46] + node _T_13153 = bits(_T_13094, 2, 2) @[RegMapper.scala 178:77] + node _T_13154 = and(_T_13152, _T_13153) @[RegMapper.scala 178:66] + node _T_13155 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13156 = and(_T_13155, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13157 = bits(_T_13028, 3, 3) @[RegMapper.scala 175:77] + node _T_13158 = and(_T_13156, _T_13157) @[RegMapper.scala 175:66] + node _T_13159 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13161 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13162 = and(_T_13159, _T_13161) @[RegMapper.scala 176:46] + node _T_13163 = bits(_T_13028, 3, 3) @[RegMapper.scala 176:77] + node _T_13164 = and(_T_13162, _T_13163) @[RegMapper.scala 176:66] + node _T_13165 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13166 = and(_T_13165, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13167 = bits(_T_13094, 3, 3) @[RegMapper.scala 177:77] + node _T_13168 = and(_T_13166, _T_13167) @[RegMapper.scala 177:66] + node _T_13169 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13171 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13172 = and(_T_13169, _T_13171) @[RegMapper.scala 178:46] + node _T_13173 = bits(_T_13094, 3, 3) @[RegMapper.scala 178:77] + node _T_13174 = and(_T_13172, _T_13173) @[RegMapper.scala 178:66] + node _T_13175 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13176 = and(_T_13175, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13177 = bits(_T_13028, 4, 4) @[RegMapper.scala 175:77] + node _T_13178 = and(_T_13176, _T_13177) @[RegMapper.scala 175:66] + node _T_13179 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13181 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13182 = and(_T_13179, _T_13181) @[RegMapper.scala 176:46] + node _T_13183 = bits(_T_13028, 4, 4) @[RegMapper.scala 176:77] + node _T_13184 = and(_T_13182, _T_13183) @[RegMapper.scala 176:66] + node _T_13185 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13186 = and(_T_13185, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13187 = bits(_T_13094, 4, 4) @[RegMapper.scala 177:77] + node _T_13188 = and(_T_13186, _T_13187) @[RegMapper.scala 177:66] + node _T_13189 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13191 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13192 = and(_T_13189, _T_13191) @[RegMapper.scala 178:46] + node _T_13193 = bits(_T_13094, 4, 4) @[RegMapper.scala 178:77] + node _T_13194 = and(_T_13192, _T_13193) @[RegMapper.scala 178:66] + node _T_13195 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13196 = and(_T_13195, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13197 = bits(_T_13028, 5, 5) @[RegMapper.scala 175:77] + node _T_13198 = and(_T_13196, _T_13197) @[RegMapper.scala 175:66] + node _T_13199 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13201 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13202 = and(_T_13199, _T_13201) @[RegMapper.scala 176:46] + node _T_13203 = bits(_T_13028, 5, 5) @[RegMapper.scala 176:77] + node _T_13204 = and(_T_13202, _T_13203) @[RegMapper.scala 176:66] + node _T_13205 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13206 = and(_T_13205, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13207 = bits(_T_13094, 5, 5) @[RegMapper.scala 177:77] + node _T_13208 = and(_T_13206, _T_13207) @[RegMapper.scala 177:66] + node _T_13209 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13211 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13212 = and(_T_13209, _T_13211) @[RegMapper.scala 178:46] + node _T_13213 = bits(_T_13094, 5, 5) @[RegMapper.scala 178:77] + node _T_13214 = and(_T_13212, _T_13213) @[RegMapper.scala 178:66] + node _T_13215 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13216 = and(_T_13215, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13217 = bits(_T_13028, 6, 6) @[RegMapper.scala 175:77] + node _T_13218 = and(_T_13216, _T_13217) @[RegMapper.scala 175:66] + node _T_13219 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13221 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13222 = and(_T_13219, _T_13221) @[RegMapper.scala 176:46] + node _T_13223 = bits(_T_13028, 6, 6) @[RegMapper.scala 176:77] + node _T_13224 = and(_T_13222, _T_13223) @[RegMapper.scala 176:66] + node _T_13225 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13226 = and(_T_13225, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13227 = bits(_T_13094, 6, 6) @[RegMapper.scala 177:77] + node _T_13228 = and(_T_13226, _T_13227) @[RegMapper.scala 177:66] + node _T_13229 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13231 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13232 = and(_T_13229, _T_13231) @[RegMapper.scala 178:46] + node _T_13233 = bits(_T_13094, 6, 6) @[RegMapper.scala 178:77] + node _T_13234 = and(_T_13232, _T_13233) @[RegMapper.scala 178:66] + node _T_13235 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13236 = and(_T_13235, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13237 = bits(_T_13028, 7, 7) @[RegMapper.scala 175:77] + node _T_13238 = and(_T_13236, _T_13237) @[RegMapper.scala 175:66] + node _T_13239 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13241 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13242 = and(_T_13239, _T_13241) @[RegMapper.scala 176:46] + node _T_13243 = bits(_T_13028, 7, 7) @[RegMapper.scala 176:77] + node _T_13244 = and(_T_13242, _T_13243) @[RegMapper.scala 176:66] + node _T_13245 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13246 = and(_T_13245, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13247 = bits(_T_13094, 7, 7) @[RegMapper.scala 177:77] + node _T_13248 = and(_T_13246, _T_13247) @[RegMapper.scala 177:66] + node _T_13249 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13251 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13252 = and(_T_13249, _T_13251) @[RegMapper.scala 178:46] + node _T_13253 = bits(_T_13094, 7, 7) @[RegMapper.scala 178:77] + node _T_13254 = and(_T_13252, _T_13253) @[RegMapper.scala 178:66] + node _T_13255 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13256 = and(_T_13255, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13257 = bits(_T_13028, 8, 8) @[RegMapper.scala 175:77] + node _T_13258 = and(_T_13256, _T_13257) @[RegMapper.scala 175:66] + node _T_13259 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13261 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13262 = and(_T_13259, _T_13261) @[RegMapper.scala 176:46] + node _T_13263 = bits(_T_13028, 8, 8) @[RegMapper.scala 176:77] + node _T_13264 = and(_T_13262, _T_13263) @[RegMapper.scala 176:66] + node _T_13265 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13266 = and(_T_13265, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13267 = bits(_T_13094, 8, 8) @[RegMapper.scala 177:77] + node _T_13268 = and(_T_13266, _T_13267) @[RegMapper.scala 177:66] + node _T_13269 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13271 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13272 = and(_T_13269, _T_13271) @[RegMapper.scala 178:46] + node _T_13273 = bits(_T_13094, 8, 8) @[RegMapper.scala 178:77] + node _T_13274 = and(_T_13272, _T_13273) @[RegMapper.scala 178:66] + node _T_13275 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13276 = and(_T_13275, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13277 = bits(_T_13028, 9, 9) @[RegMapper.scala 175:77] + node _T_13278 = and(_T_13276, _T_13277) @[RegMapper.scala 175:66] + node _T_13279 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13281 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13282 = and(_T_13279, _T_13281) @[RegMapper.scala 176:46] + node _T_13283 = bits(_T_13028, 9, 9) @[RegMapper.scala 176:77] + node _T_13284 = and(_T_13282, _T_13283) @[RegMapper.scala 176:66] + node _T_13285 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13286 = and(_T_13285, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13287 = bits(_T_13094, 9, 9) @[RegMapper.scala 177:77] + node _T_13288 = and(_T_13286, _T_13287) @[RegMapper.scala 177:66] + node _T_13289 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13291 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13292 = and(_T_13289, _T_13291) @[RegMapper.scala 178:46] + node _T_13293 = bits(_T_13094, 9, 9) @[RegMapper.scala 178:77] + node _T_13294 = and(_T_13292, _T_13293) @[RegMapper.scala 178:66] + node _T_13295 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13296 = and(_T_13295, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13297 = bits(_T_13028, 10, 10) @[RegMapper.scala 175:77] + node _T_13298 = and(_T_13296, _T_13297) @[RegMapper.scala 175:66] + node _T_13299 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13301 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13302 = and(_T_13299, _T_13301) @[RegMapper.scala 176:46] + node _T_13303 = bits(_T_13028, 10, 10) @[RegMapper.scala 176:77] + node _T_13304 = and(_T_13302, _T_13303) @[RegMapper.scala 176:66] + node _T_13305 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13306 = and(_T_13305, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13307 = bits(_T_13094, 10, 10) @[RegMapper.scala 177:77] + node _T_13308 = and(_T_13306, _T_13307) @[RegMapper.scala 177:66] + node _T_13309 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13311 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13312 = and(_T_13309, _T_13311) @[RegMapper.scala 178:46] + node _T_13313 = bits(_T_13094, 10, 10) @[RegMapper.scala 178:77] + node _T_13314 = and(_T_13312, _T_13313) @[RegMapper.scala 178:66] + node _T_13315 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13316 = and(_T_13315, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13317 = bits(_T_13028, 11, 11) @[RegMapper.scala 175:77] + node _T_13318 = and(_T_13316, _T_13317) @[RegMapper.scala 175:66] + node _T_13319 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13321 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13322 = and(_T_13319, _T_13321) @[RegMapper.scala 176:46] + node _T_13323 = bits(_T_13028, 11, 11) @[RegMapper.scala 176:77] + node _T_13324 = and(_T_13322, _T_13323) @[RegMapper.scala 176:66] + node _T_13325 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13326 = and(_T_13325, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13327 = bits(_T_13094, 11, 11) @[RegMapper.scala 177:77] + node _T_13328 = and(_T_13326, _T_13327) @[RegMapper.scala 177:66] + node _T_13329 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13331 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13332 = and(_T_13329, _T_13331) @[RegMapper.scala 178:46] + node _T_13333 = bits(_T_13094, 11, 11) @[RegMapper.scala 178:77] + node _T_13334 = and(_T_13332, _T_13333) @[RegMapper.scala 178:66] + node _T_13335 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13336 = and(_T_13335, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13337 = bits(_T_13028, 12, 12) @[RegMapper.scala 175:77] + node _T_13338 = and(_T_13336, _T_13337) @[RegMapper.scala 175:66] + node _T_13339 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13341 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13342 = and(_T_13339, _T_13341) @[RegMapper.scala 176:46] + node _T_13343 = bits(_T_13028, 12, 12) @[RegMapper.scala 176:77] + node _T_13344 = and(_T_13342, _T_13343) @[RegMapper.scala 176:66] + node _T_13345 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13346 = and(_T_13345, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13347 = bits(_T_13094, 12, 12) @[RegMapper.scala 177:77] + node _T_13348 = and(_T_13346, _T_13347) @[RegMapper.scala 177:66] + node _T_13349 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13351 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13352 = and(_T_13349, _T_13351) @[RegMapper.scala 178:46] + node _T_13353 = bits(_T_13094, 12, 12) @[RegMapper.scala 178:77] + node _T_13354 = and(_T_13352, _T_13353) @[RegMapper.scala 178:66] + node _T_13355 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13356 = and(_T_13355, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13357 = bits(_T_13028, 13, 13) @[RegMapper.scala 175:77] + node _T_13358 = and(_T_13356, _T_13357) @[RegMapper.scala 175:66] + node _T_13359 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13361 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13362 = and(_T_13359, _T_13361) @[RegMapper.scala 176:46] + node _T_13363 = bits(_T_13028, 13, 13) @[RegMapper.scala 176:77] + node _T_13364 = and(_T_13362, _T_13363) @[RegMapper.scala 176:66] + node _T_13365 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13366 = and(_T_13365, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13367 = bits(_T_13094, 13, 13) @[RegMapper.scala 177:77] + node _T_13368 = and(_T_13366, _T_13367) @[RegMapper.scala 177:66] + node _T_13369 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13371 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13372 = and(_T_13369, _T_13371) @[RegMapper.scala 178:46] + node _T_13373 = bits(_T_13094, 13, 13) @[RegMapper.scala 178:77] + node _T_13374 = and(_T_13372, _T_13373) @[RegMapper.scala 178:66] + node _T_13375 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13376 = and(_T_13375, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13377 = bits(_T_13028, 14, 14) @[RegMapper.scala 175:77] + node _T_13378 = and(_T_13376, _T_13377) @[RegMapper.scala 175:66] + node _T_13379 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13381 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13382 = and(_T_13379, _T_13381) @[RegMapper.scala 176:46] + node _T_13383 = bits(_T_13028, 14, 14) @[RegMapper.scala 176:77] + node _T_13384 = and(_T_13382, _T_13383) @[RegMapper.scala 176:66] + node _T_13385 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13386 = and(_T_13385, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13387 = bits(_T_13094, 14, 14) @[RegMapper.scala 177:77] + node _T_13388 = and(_T_13386, _T_13387) @[RegMapper.scala 177:66] + node _T_13389 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13391 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13392 = and(_T_13389, _T_13391) @[RegMapper.scala 178:46] + node _T_13393 = bits(_T_13094, 14, 14) @[RegMapper.scala 178:77] + node _T_13394 = and(_T_13392, _T_13393) @[RegMapper.scala 178:66] + node _T_13395 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13396 = and(_T_13395, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13397 = bits(_T_13028, 15, 15) @[RegMapper.scala 175:77] + node _T_13398 = and(_T_13396, _T_13397) @[RegMapper.scala 175:66] + node _T_13399 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13401 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13402 = and(_T_13399, _T_13401) @[RegMapper.scala 176:46] + node _T_13403 = bits(_T_13028, 15, 15) @[RegMapper.scala 176:77] + node _T_13404 = and(_T_13402, _T_13403) @[RegMapper.scala 176:66] + node _T_13405 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13406 = and(_T_13405, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13407 = bits(_T_13094, 15, 15) @[RegMapper.scala 177:77] + node _T_13408 = and(_T_13406, _T_13407) @[RegMapper.scala 177:66] + node _T_13409 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13411 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13412 = and(_T_13409, _T_13411) @[RegMapper.scala 178:46] + node _T_13413 = bits(_T_13094, 15, 15) @[RegMapper.scala 178:77] + node _T_13414 = and(_T_13412, _T_13413) @[RegMapper.scala 178:66] + node _T_13415 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13416 = and(_T_13415, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13417 = bits(_T_13028, 16, 16) @[RegMapper.scala 175:77] + node _T_13418 = and(_T_13416, _T_13417) @[RegMapper.scala 175:66] + node _T_13419 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13421 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13422 = and(_T_13419, _T_13421) @[RegMapper.scala 176:46] + node _T_13423 = bits(_T_13028, 16, 16) @[RegMapper.scala 176:77] + node _T_13424 = and(_T_13422, _T_13423) @[RegMapper.scala 176:66] + node _T_13425 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13426 = and(_T_13425, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13427 = bits(_T_13094, 16, 16) @[RegMapper.scala 177:77] + node _T_13428 = and(_T_13426, _T_13427) @[RegMapper.scala 177:66] + node _T_13429 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13431 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13432 = and(_T_13429, _T_13431) @[RegMapper.scala 178:46] + node _T_13433 = bits(_T_13094, 16, 16) @[RegMapper.scala 178:77] + node _T_13434 = and(_T_13432, _T_13433) @[RegMapper.scala 178:66] + node _T_13435 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13436 = and(_T_13435, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13437 = bits(_T_13028, 17, 17) @[RegMapper.scala 175:77] + node _T_13438 = and(_T_13436, _T_13437) @[RegMapper.scala 175:66] + node _T_13439 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13441 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13442 = and(_T_13439, _T_13441) @[RegMapper.scala 176:46] + node _T_13443 = bits(_T_13028, 17, 17) @[RegMapper.scala 176:77] + node _T_13444 = and(_T_13442, _T_13443) @[RegMapper.scala 176:66] + node _T_13445 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13446 = and(_T_13445, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13447 = bits(_T_13094, 17, 17) @[RegMapper.scala 177:77] + node _T_13448 = and(_T_13446, _T_13447) @[RegMapper.scala 177:66] + node _T_13449 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13451 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13452 = and(_T_13449, _T_13451) @[RegMapper.scala 178:46] + node _T_13453 = bits(_T_13094, 17, 17) @[RegMapper.scala 178:77] + node _T_13454 = and(_T_13452, _T_13453) @[RegMapper.scala 178:66] + node _T_13455 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13456 = and(_T_13455, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13457 = bits(_T_13028, 18, 18) @[RegMapper.scala 175:77] + node _T_13458 = and(_T_13456, _T_13457) @[RegMapper.scala 175:66] + node _T_13459 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13461 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13462 = and(_T_13459, _T_13461) @[RegMapper.scala 176:46] + node _T_13463 = bits(_T_13028, 18, 18) @[RegMapper.scala 176:77] + node _T_13464 = and(_T_13462, _T_13463) @[RegMapper.scala 176:66] + node _T_13465 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13466 = and(_T_13465, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13467 = bits(_T_13094, 18, 18) @[RegMapper.scala 177:77] + node _T_13468 = and(_T_13466, _T_13467) @[RegMapper.scala 177:66] + node _T_13469 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13471 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13472 = and(_T_13469, _T_13471) @[RegMapper.scala 178:46] + node _T_13473 = bits(_T_13094, 18, 18) @[RegMapper.scala 178:77] + node _T_13474 = and(_T_13472, _T_13473) @[RegMapper.scala 178:66] + node _T_13475 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13476 = and(_T_13475, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13477 = bits(_T_13028, 19, 19) @[RegMapper.scala 175:77] + node _T_13478 = and(_T_13476, _T_13477) @[RegMapper.scala 175:66] + node _T_13479 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13481 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13482 = and(_T_13479, _T_13481) @[RegMapper.scala 176:46] + node _T_13483 = bits(_T_13028, 19, 19) @[RegMapper.scala 176:77] + node _T_13484 = and(_T_13482, _T_13483) @[RegMapper.scala 176:66] + node _T_13485 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13486 = and(_T_13485, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13487 = bits(_T_13094, 19, 19) @[RegMapper.scala 177:77] + node _T_13488 = and(_T_13486, _T_13487) @[RegMapper.scala 177:66] + node _T_13489 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13491 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13492 = and(_T_13489, _T_13491) @[RegMapper.scala 178:46] + node _T_13493 = bits(_T_13094, 19, 19) @[RegMapper.scala 178:77] + node _T_13494 = and(_T_13492, _T_13493) @[RegMapper.scala 178:66] + node _T_13495 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13496 = and(_T_13495, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13497 = bits(_T_13028, 20, 20) @[RegMapper.scala 175:77] + node _T_13498 = and(_T_13496, _T_13497) @[RegMapper.scala 175:66] + node _T_13499 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13501 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13502 = and(_T_13499, _T_13501) @[RegMapper.scala 176:46] + node _T_13503 = bits(_T_13028, 20, 20) @[RegMapper.scala 176:77] + node _T_13504 = and(_T_13502, _T_13503) @[RegMapper.scala 176:66] + node _T_13505 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13506 = and(_T_13505, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13507 = bits(_T_13094, 20, 20) @[RegMapper.scala 177:77] + node _T_13508 = and(_T_13506, _T_13507) @[RegMapper.scala 177:66] + node _T_13509 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13511 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13512 = and(_T_13509, _T_13511) @[RegMapper.scala 178:46] + node _T_13513 = bits(_T_13094, 20, 20) @[RegMapper.scala 178:77] + node _T_13514 = and(_T_13512, _T_13513) @[RegMapper.scala 178:66] + node _T_13515 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13516 = and(_T_13515, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13517 = bits(_T_13028, 21, 21) @[RegMapper.scala 175:77] + node _T_13518 = and(_T_13516, _T_13517) @[RegMapper.scala 175:66] + node _T_13519 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13521 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13522 = and(_T_13519, _T_13521) @[RegMapper.scala 176:46] + node _T_13523 = bits(_T_13028, 21, 21) @[RegMapper.scala 176:77] + node _T_13524 = and(_T_13522, _T_13523) @[RegMapper.scala 176:66] + node _T_13525 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13526 = and(_T_13525, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13527 = bits(_T_13094, 21, 21) @[RegMapper.scala 177:77] + node _T_13528 = and(_T_13526, _T_13527) @[RegMapper.scala 177:66] + node _T_13529 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13531 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13532 = and(_T_13529, _T_13531) @[RegMapper.scala 178:46] + node _T_13533 = bits(_T_13094, 21, 21) @[RegMapper.scala 178:77] + node _T_13534 = and(_T_13532, _T_13533) @[RegMapper.scala 178:66] + node _T_13535 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13536 = and(_T_13535, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13537 = bits(_T_13028, 22, 22) @[RegMapper.scala 175:77] + node _T_13538 = and(_T_13536, _T_13537) @[RegMapper.scala 175:66] + node _T_13539 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13541 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13542 = and(_T_13539, _T_13541) @[RegMapper.scala 176:46] + node _T_13543 = bits(_T_13028, 22, 22) @[RegMapper.scala 176:77] + node _T_13544 = and(_T_13542, _T_13543) @[RegMapper.scala 176:66] + node _T_13545 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13546 = and(_T_13545, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13547 = bits(_T_13094, 22, 22) @[RegMapper.scala 177:77] + node _T_13548 = and(_T_13546, _T_13547) @[RegMapper.scala 177:66] + node _T_13549 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13551 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13552 = and(_T_13549, _T_13551) @[RegMapper.scala 178:46] + node _T_13553 = bits(_T_13094, 22, 22) @[RegMapper.scala 178:77] + node _T_13554 = and(_T_13552, _T_13553) @[RegMapper.scala 178:66] + node _T_13555 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13556 = and(_T_13555, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13557 = bits(_T_13028, 23, 23) @[RegMapper.scala 175:77] + node _T_13558 = and(_T_13556, _T_13557) @[RegMapper.scala 175:66] + node _T_13559 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13561 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13562 = and(_T_13559, _T_13561) @[RegMapper.scala 176:46] + node _T_13563 = bits(_T_13028, 23, 23) @[RegMapper.scala 176:77] + node _T_13564 = and(_T_13562, _T_13563) @[RegMapper.scala 176:66] + node _T_13565 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13566 = and(_T_13565, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13567 = bits(_T_13094, 23, 23) @[RegMapper.scala 177:77] + node _T_13568 = and(_T_13566, _T_13567) @[RegMapper.scala 177:66] + node _T_13569 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13571 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13572 = and(_T_13569, _T_13571) @[RegMapper.scala 178:46] + node _T_13573 = bits(_T_13094, 23, 23) @[RegMapper.scala 178:77] + node _T_13574 = and(_T_13572, _T_13573) @[RegMapper.scala 178:66] + node _T_13575 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13576 = and(_T_13575, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13577 = bits(_T_13028, 24, 24) @[RegMapper.scala 175:77] + node _T_13578 = and(_T_13576, _T_13577) @[RegMapper.scala 175:66] + node _T_13579 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13581 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13582 = and(_T_13579, _T_13581) @[RegMapper.scala 176:46] + node _T_13583 = bits(_T_13028, 24, 24) @[RegMapper.scala 176:77] + node _T_13584 = and(_T_13582, _T_13583) @[RegMapper.scala 176:66] + node _T_13585 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13586 = and(_T_13585, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13587 = bits(_T_13094, 24, 24) @[RegMapper.scala 177:77] + node _T_13588 = and(_T_13586, _T_13587) @[RegMapper.scala 177:66] + node _T_13589 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13591 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13592 = and(_T_13589, _T_13591) @[RegMapper.scala 178:46] + node _T_13593 = bits(_T_13094, 24, 24) @[RegMapper.scala 178:77] + node _T_13594 = and(_T_13592, _T_13593) @[RegMapper.scala 178:66] + node _T_13595 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13596 = and(_T_13595, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13597 = bits(_T_13028, 25, 25) @[RegMapper.scala 175:77] + node _T_13598 = and(_T_13596, _T_13597) @[RegMapper.scala 175:66] + node _T_13599 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13601 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13602 = and(_T_13599, _T_13601) @[RegMapper.scala 176:46] + node _T_13603 = bits(_T_13028, 25, 25) @[RegMapper.scala 176:77] + node _T_13604 = and(_T_13602, _T_13603) @[RegMapper.scala 176:66] + node _T_13605 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13606 = and(_T_13605, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13607 = bits(_T_13094, 25, 25) @[RegMapper.scala 177:77] + node _T_13608 = and(_T_13606, _T_13607) @[RegMapper.scala 177:66] + node _T_13609 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13611 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13612 = and(_T_13609, _T_13611) @[RegMapper.scala 178:46] + node _T_13613 = bits(_T_13094, 25, 25) @[RegMapper.scala 178:77] + node _T_13614 = and(_T_13612, _T_13613) @[RegMapper.scala 178:66] + node _T_13615 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13616 = and(_T_13615, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13617 = bits(_T_13028, 26, 26) @[RegMapper.scala 175:77] + node _T_13618 = and(_T_13616, _T_13617) @[RegMapper.scala 175:66] + node _T_13619 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13621 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13622 = and(_T_13619, _T_13621) @[RegMapper.scala 176:46] + node _T_13623 = bits(_T_13028, 26, 26) @[RegMapper.scala 176:77] + node _T_13624 = and(_T_13622, _T_13623) @[RegMapper.scala 176:66] + node _T_13625 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13626 = and(_T_13625, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13627 = bits(_T_13094, 26, 26) @[RegMapper.scala 177:77] + node _T_13628 = and(_T_13626, _T_13627) @[RegMapper.scala 177:66] + node _T_13629 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13631 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13632 = and(_T_13629, _T_13631) @[RegMapper.scala 178:46] + node _T_13633 = bits(_T_13094, 26, 26) @[RegMapper.scala 178:77] + node _T_13634 = and(_T_13632, _T_13633) @[RegMapper.scala 178:66] + node _T_13635 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13636 = and(_T_13635, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13637 = bits(_T_13028, 27, 27) @[RegMapper.scala 175:77] + node _T_13638 = and(_T_13636, _T_13637) @[RegMapper.scala 175:66] + node _T_13639 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13641 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13642 = and(_T_13639, _T_13641) @[RegMapper.scala 176:46] + node _T_13643 = bits(_T_13028, 27, 27) @[RegMapper.scala 176:77] + node _T_13644 = and(_T_13642, _T_13643) @[RegMapper.scala 176:66] + node _T_13645 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13646 = and(_T_13645, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13647 = bits(_T_13094, 27, 27) @[RegMapper.scala 177:77] + node _T_13648 = and(_T_13646, _T_13647) @[RegMapper.scala 177:66] + node _T_13649 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13651 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13652 = and(_T_13649, _T_13651) @[RegMapper.scala 178:46] + node _T_13653 = bits(_T_13094, 27, 27) @[RegMapper.scala 178:77] + node _T_13654 = and(_T_13652, _T_13653) @[RegMapper.scala 178:66] + node _T_13655 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13656 = and(_T_13655, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13657 = bits(_T_13028, 28, 28) @[RegMapper.scala 175:77] + node _T_13658 = and(_T_13656, _T_13657) @[RegMapper.scala 175:66] + node _T_13659 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13661 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13662 = and(_T_13659, _T_13661) @[RegMapper.scala 176:46] + node _T_13663 = bits(_T_13028, 28, 28) @[RegMapper.scala 176:77] + node _T_13664 = and(_T_13662, _T_13663) @[RegMapper.scala 176:66] + node _T_13665 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13666 = and(_T_13665, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13667 = bits(_T_13094, 28, 28) @[RegMapper.scala 177:77] + node _T_13668 = and(_T_13666, _T_13667) @[RegMapper.scala 177:66] + node _T_13669 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13671 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13672 = and(_T_13669, _T_13671) @[RegMapper.scala 178:46] + node _T_13673 = bits(_T_13094, 28, 28) @[RegMapper.scala 178:77] + node _T_13674 = and(_T_13672, _T_13673) @[RegMapper.scala 178:66] + node _T_13675 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13676 = and(_T_13675, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13677 = bits(_T_13028, 29, 29) @[RegMapper.scala 175:77] + node _T_13678 = and(_T_13676, _T_13677) @[RegMapper.scala 175:66] + node _T_13679 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13681 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13682 = and(_T_13679, _T_13681) @[RegMapper.scala 176:46] + node _T_13683 = bits(_T_13028, 29, 29) @[RegMapper.scala 176:77] + node _T_13684 = and(_T_13682, _T_13683) @[RegMapper.scala 176:66] + node _T_13685 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13686 = and(_T_13685, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13687 = bits(_T_13094, 29, 29) @[RegMapper.scala 177:77] + node _T_13688 = and(_T_13686, _T_13687) @[RegMapper.scala 177:66] + node _T_13689 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13691 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13692 = and(_T_13689, _T_13691) @[RegMapper.scala 178:46] + node _T_13693 = bits(_T_13094, 29, 29) @[RegMapper.scala 178:77] + node _T_13694 = and(_T_13692, _T_13693) @[RegMapper.scala 178:66] + node _T_13695 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13696 = and(_T_13695, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13697 = bits(_T_13028, 30, 30) @[RegMapper.scala 175:77] + node _T_13698 = and(_T_13696, _T_13697) @[RegMapper.scala 175:66] + node _T_13699 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13701 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13702 = and(_T_13699, _T_13701) @[RegMapper.scala 176:46] + node _T_13703 = bits(_T_13028, 30, 30) @[RegMapper.scala 176:77] + node _T_13704 = and(_T_13702, _T_13703) @[RegMapper.scala 176:66] + node _T_13705 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13706 = and(_T_13705, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13707 = bits(_T_13094, 30, 30) @[RegMapper.scala 177:77] + node _T_13708 = and(_T_13706, _T_13707) @[RegMapper.scala 177:66] + node _T_13709 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13711 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13712 = and(_T_13709, _T_13711) @[RegMapper.scala 178:46] + node _T_13713 = bits(_T_13094, 30, 30) @[RegMapper.scala 178:77] + node _T_13714 = and(_T_13712, _T_13713) @[RegMapper.scala 178:66] + node _T_13715 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13716 = and(_T_13715, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13717 = bits(_T_13028, 31, 31) @[RegMapper.scala 175:77] + node _T_13718 = and(_T_13716, _T_13717) @[RegMapper.scala 175:66] + node _T_13719 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13721 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13722 = and(_T_13719, _T_13721) @[RegMapper.scala 176:46] + node _T_13723 = bits(_T_13028, 31, 31) @[RegMapper.scala 176:77] + node _T_13724 = and(_T_13722, _T_13723) @[RegMapper.scala 176:66] + node _T_13725 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13726 = and(_T_13725, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13727 = bits(_T_13094, 31, 31) @[RegMapper.scala 177:77] + node _T_13728 = and(_T_13726, _T_13727) @[RegMapper.scala 177:66] + node _T_13729 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13731 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13732 = and(_T_13729, _T_13731) @[RegMapper.scala 178:46] + node _T_13733 = bits(_T_13094, 31, 31) @[RegMapper.scala 178:77] + node _T_13734 = and(_T_13732, _T_13733) @[RegMapper.scala 178:66] + node _T_13735 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13736 = and(_T_13735, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13737 = bits(_T_13028, 32, 32) @[RegMapper.scala 175:77] + node _T_13738 = and(_T_13736, _T_13737) @[RegMapper.scala 175:66] + node _T_13739 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13741 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13742 = and(_T_13739, _T_13741) @[RegMapper.scala 176:46] + node _T_13743 = bits(_T_13028, 32, 32) @[RegMapper.scala 176:77] + node _T_13744 = and(_T_13742, _T_13743) @[RegMapper.scala 176:66] + node _T_13745 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13746 = and(_T_13745, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13747 = bits(_T_13094, 32, 32) @[RegMapper.scala 177:77] + node _T_13748 = and(_T_13746, _T_13747) @[RegMapper.scala 177:66] + node _T_13749 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13751 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13752 = and(_T_13749, _T_13751) @[RegMapper.scala 178:46] + node _T_13753 = bits(_T_13094, 32, 32) @[RegMapper.scala 178:77] + node _T_13754 = and(_T_13752, _T_13753) @[RegMapper.scala 178:66] + node _T_13755 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13756 = and(_T_13755, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13757 = bits(_T_13028, 33, 33) @[RegMapper.scala 175:77] + node _T_13758 = and(_T_13756, _T_13757) @[RegMapper.scala 175:66] + node _T_13759 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13761 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13762 = and(_T_13759, _T_13761) @[RegMapper.scala 176:46] + node _T_13763 = bits(_T_13028, 33, 33) @[RegMapper.scala 176:77] + node _T_13764 = and(_T_13762, _T_13763) @[RegMapper.scala 176:66] + node _T_13765 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13766 = and(_T_13765, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13767 = bits(_T_13094, 33, 33) @[RegMapper.scala 177:77] + node _T_13768 = and(_T_13766, _T_13767) @[RegMapper.scala 177:66] + node _T_13769 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13771 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13772 = and(_T_13769, _T_13771) @[RegMapper.scala 178:46] + node _T_13773 = bits(_T_13094, 33, 33) @[RegMapper.scala 178:77] + node _T_13774 = and(_T_13772, _T_13773) @[RegMapper.scala 178:66] + node _T_13775 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13776 = and(_T_13775, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13777 = bits(_T_13028, 34, 34) @[RegMapper.scala 175:77] + node _T_13778 = and(_T_13776, _T_13777) @[RegMapper.scala 175:66] + node _T_13779 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13781 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13782 = and(_T_13779, _T_13781) @[RegMapper.scala 176:46] + node _T_13783 = bits(_T_13028, 34, 34) @[RegMapper.scala 176:77] + node _T_13784 = and(_T_13782, _T_13783) @[RegMapper.scala 176:66] + node _T_13785 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13786 = and(_T_13785, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13787 = bits(_T_13094, 34, 34) @[RegMapper.scala 177:77] + node _T_13788 = and(_T_13786, _T_13787) @[RegMapper.scala 177:66] + node _T_13789 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13791 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13792 = and(_T_13789, _T_13791) @[RegMapper.scala 178:46] + node _T_13793 = bits(_T_13094, 34, 34) @[RegMapper.scala 178:77] + node _T_13794 = and(_T_13792, _T_13793) @[RegMapper.scala 178:66] + node _T_13795 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13796 = and(_T_13795, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13797 = bits(_T_13028, 35, 35) @[RegMapper.scala 175:77] + node _T_13798 = and(_T_13796, _T_13797) @[RegMapper.scala 175:66] + node _T_13799 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13801 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13802 = and(_T_13799, _T_13801) @[RegMapper.scala 176:46] + node _T_13803 = bits(_T_13028, 35, 35) @[RegMapper.scala 176:77] + node _T_13804 = and(_T_13802, _T_13803) @[RegMapper.scala 176:66] + node _T_13805 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13806 = and(_T_13805, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13807 = bits(_T_13094, 35, 35) @[RegMapper.scala 177:77] + node _T_13808 = and(_T_13806, _T_13807) @[RegMapper.scala 177:66] + node _T_13809 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13811 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13812 = and(_T_13809, _T_13811) @[RegMapper.scala 178:46] + node _T_13813 = bits(_T_13094, 35, 35) @[RegMapper.scala 178:77] + node _T_13814 = and(_T_13812, _T_13813) @[RegMapper.scala 178:66] + node _T_13815 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13816 = and(_T_13815, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13817 = bits(_T_13028, 36, 36) @[RegMapper.scala 175:77] + node _T_13818 = and(_T_13816, _T_13817) @[RegMapper.scala 175:66] + node _T_13819 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13821 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13822 = and(_T_13819, _T_13821) @[RegMapper.scala 176:46] + node _T_13823 = bits(_T_13028, 36, 36) @[RegMapper.scala 176:77] + node _T_13824 = and(_T_13822, _T_13823) @[RegMapper.scala 176:66] + node _T_13825 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13826 = and(_T_13825, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13827 = bits(_T_13094, 36, 36) @[RegMapper.scala 177:77] + node _T_13828 = and(_T_13826, _T_13827) @[RegMapper.scala 177:66] + node _T_13829 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13831 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13832 = and(_T_13829, _T_13831) @[RegMapper.scala 178:46] + node _T_13833 = bits(_T_13094, 36, 36) @[RegMapper.scala 178:77] + node _T_13834 = and(_T_13832, _T_13833) @[RegMapper.scala 178:66] + node _T_13835 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13836 = and(_T_13835, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13837 = bits(_T_13028, 37, 37) @[RegMapper.scala 175:77] + node _T_13838 = and(_T_13836, _T_13837) @[RegMapper.scala 175:66] + node _T_13839 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13841 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13842 = and(_T_13839, _T_13841) @[RegMapper.scala 176:46] + node _T_13843 = bits(_T_13028, 37, 37) @[RegMapper.scala 176:77] + node _T_13844 = and(_T_13842, _T_13843) @[RegMapper.scala 176:66] + node _T_13845 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13846 = and(_T_13845, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13847 = bits(_T_13094, 37, 37) @[RegMapper.scala 177:77] + node _T_13848 = and(_T_13846, _T_13847) @[RegMapper.scala 177:66] + node _T_13849 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13851 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13852 = and(_T_13849, _T_13851) @[RegMapper.scala 178:46] + node _T_13853 = bits(_T_13094, 37, 37) @[RegMapper.scala 178:77] + node _T_13854 = and(_T_13852, _T_13853) @[RegMapper.scala 178:66] + node _T_13855 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13856 = and(_T_13855, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13857 = bits(_T_13028, 38, 38) @[RegMapper.scala 175:77] + node _T_13858 = and(_T_13856, _T_13857) @[RegMapper.scala 175:66] + node _T_13859 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13861 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13862 = and(_T_13859, _T_13861) @[RegMapper.scala 176:46] + node _T_13863 = bits(_T_13028, 38, 38) @[RegMapper.scala 176:77] + node _T_13864 = and(_T_13862, _T_13863) @[RegMapper.scala 176:66] + node _T_13865 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13866 = and(_T_13865, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13867 = bits(_T_13094, 38, 38) @[RegMapper.scala 177:77] + node _T_13868 = and(_T_13866, _T_13867) @[RegMapper.scala 177:66] + node _T_13869 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13871 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13872 = and(_T_13869, _T_13871) @[RegMapper.scala 178:46] + node _T_13873 = bits(_T_13094, 38, 38) @[RegMapper.scala 178:77] + node _T_13874 = and(_T_13872, _T_13873) @[RegMapper.scala 178:66] + node _T_13875 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13876 = and(_T_13875, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13877 = bits(_T_13028, 39, 39) @[RegMapper.scala 175:77] + node _T_13878 = and(_T_13876, _T_13877) @[RegMapper.scala 175:66] + node _T_13879 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13881 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13882 = and(_T_13879, _T_13881) @[RegMapper.scala 176:46] + node _T_13883 = bits(_T_13028, 39, 39) @[RegMapper.scala 176:77] + node _T_13884 = and(_T_13882, _T_13883) @[RegMapper.scala 176:66] + node _T_13885 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13886 = and(_T_13885, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13887 = bits(_T_13094, 39, 39) @[RegMapper.scala 177:77] + node _T_13888 = and(_T_13886, _T_13887) @[RegMapper.scala 177:66] + node _T_13889 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13891 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13892 = and(_T_13889, _T_13891) @[RegMapper.scala 178:46] + node _T_13893 = bits(_T_13094, 39, 39) @[RegMapper.scala 178:77] + node _T_13894 = and(_T_13892, _T_13893) @[RegMapper.scala 178:66] + node _T_13895 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13896 = and(_T_13895, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13897 = bits(_T_13028, 40, 40) @[RegMapper.scala 175:77] + node _T_13898 = and(_T_13896, _T_13897) @[RegMapper.scala 175:66] + node _T_13899 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13901 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13902 = and(_T_13899, _T_13901) @[RegMapper.scala 176:46] + node _T_13903 = bits(_T_13028, 40, 40) @[RegMapper.scala 176:77] + node _T_13904 = and(_T_13902, _T_13903) @[RegMapper.scala 176:66] + node _T_13905 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13906 = and(_T_13905, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13907 = bits(_T_13094, 40, 40) @[RegMapper.scala 177:77] + node _T_13908 = and(_T_13906, _T_13907) @[RegMapper.scala 177:66] + node _T_13909 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13911 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13912 = and(_T_13909, _T_13911) @[RegMapper.scala 178:46] + node _T_13913 = bits(_T_13094, 40, 40) @[RegMapper.scala 178:77] + node _T_13914 = and(_T_13912, _T_13913) @[RegMapper.scala 178:66] + node _T_13915 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13916 = and(_T_13915, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13917 = bits(_T_13028, 41, 41) @[RegMapper.scala 175:77] + node _T_13918 = and(_T_13916, _T_13917) @[RegMapper.scala 175:66] + node _T_13919 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13921 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13922 = and(_T_13919, _T_13921) @[RegMapper.scala 176:46] + node _T_13923 = bits(_T_13028, 41, 41) @[RegMapper.scala 176:77] + node _T_13924 = and(_T_13922, _T_13923) @[RegMapper.scala 176:66] + node _T_13925 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13926 = and(_T_13925, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13927 = bits(_T_13094, 41, 41) @[RegMapper.scala 177:77] + node _T_13928 = and(_T_13926, _T_13927) @[RegMapper.scala 177:66] + node _T_13929 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13931 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13932 = and(_T_13929, _T_13931) @[RegMapper.scala 178:46] + node _T_13933 = bits(_T_13094, 41, 41) @[RegMapper.scala 178:77] + node _T_13934 = and(_T_13932, _T_13933) @[RegMapper.scala 178:66] + node _T_13935 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13936 = and(_T_13935, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13937 = bits(_T_13028, 42, 42) @[RegMapper.scala 175:77] + node _T_13938 = and(_T_13936, _T_13937) @[RegMapper.scala 175:66] + node _T_13939 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13941 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13942 = and(_T_13939, _T_13941) @[RegMapper.scala 176:46] + node _T_13943 = bits(_T_13028, 42, 42) @[RegMapper.scala 176:77] + node _T_13944 = and(_T_13942, _T_13943) @[RegMapper.scala 176:66] + node _T_13945 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13946 = and(_T_13945, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13947 = bits(_T_13094, 42, 42) @[RegMapper.scala 177:77] + node _T_13948 = and(_T_13946, _T_13947) @[RegMapper.scala 177:66] + node _T_13949 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13951 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13952 = and(_T_13949, _T_13951) @[RegMapper.scala 178:46] + node _T_13953 = bits(_T_13094, 42, 42) @[RegMapper.scala 178:77] + node _T_13954 = and(_T_13952, _T_13953) @[RegMapper.scala 178:66] + node _T_13955 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13956 = and(_T_13955, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13957 = bits(_T_13028, 43, 43) @[RegMapper.scala 175:77] + node _T_13958 = and(_T_13956, _T_13957) @[RegMapper.scala 175:66] + node _T_13959 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13961 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13962 = and(_T_13959, _T_13961) @[RegMapper.scala 176:46] + node _T_13963 = bits(_T_13028, 43, 43) @[RegMapper.scala 176:77] + node _T_13964 = and(_T_13962, _T_13963) @[RegMapper.scala 176:66] + node _T_13965 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13966 = and(_T_13965, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13967 = bits(_T_13094, 43, 43) @[RegMapper.scala 177:77] + node _T_13968 = and(_T_13966, _T_13967) @[RegMapper.scala 177:66] + node _T_13969 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13971 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13972 = and(_T_13969, _T_13971) @[RegMapper.scala 178:46] + node _T_13973 = bits(_T_13094, 43, 43) @[RegMapper.scala 178:77] + node _T_13974 = and(_T_13972, _T_13973) @[RegMapper.scala 178:66] + node _T_13975 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13976 = and(_T_13975, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13977 = bits(_T_13028, 44, 44) @[RegMapper.scala 175:77] + node _T_13978 = and(_T_13976, _T_13977) @[RegMapper.scala 175:66] + node _T_13979 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_13981 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13982 = and(_T_13979, _T_13981) @[RegMapper.scala 176:46] + node _T_13983 = bits(_T_13028, 44, 44) @[RegMapper.scala 176:77] + node _T_13984 = and(_T_13982, _T_13983) @[RegMapper.scala 176:66] + node _T_13985 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_13986 = and(_T_13985, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_13987 = bits(_T_13094, 44, 44) @[RegMapper.scala 177:77] + node _T_13988 = and(_T_13986, _T_13987) @[RegMapper.scala 177:66] + node _T_13989 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_13991 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13992 = and(_T_13989, _T_13991) @[RegMapper.scala 178:46] + node _T_13993 = bits(_T_13094, 44, 44) @[RegMapper.scala 178:77] + node _T_13994 = and(_T_13992, _T_13993) @[RegMapper.scala 178:66] + node _T_13995 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_13996 = and(_T_13995, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_13997 = bits(_T_13028, 45, 45) @[RegMapper.scala 175:77] + node _T_13998 = and(_T_13996, _T_13997) @[RegMapper.scala 175:66] + node _T_13999 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14001 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14002 = and(_T_13999, _T_14001) @[RegMapper.scala 176:46] + node _T_14003 = bits(_T_13028, 45, 45) @[RegMapper.scala 176:77] + node _T_14004 = and(_T_14002, _T_14003) @[RegMapper.scala 176:66] + node _T_14005 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14006 = and(_T_14005, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14007 = bits(_T_13094, 45, 45) @[RegMapper.scala 177:77] + node _T_14008 = and(_T_14006, _T_14007) @[RegMapper.scala 177:66] + node _T_14009 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14011 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14012 = and(_T_14009, _T_14011) @[RegMapper.scala 178:46] + node _T_14013 = bits(_T_13094, 45, 45) @[RegMapper.scala 178:77] + node _T_14014 = and(_T_14012, _T_14013) @[RegMapper.scala 178:66] + node _T_14015 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14016 = and(_T_14015, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14017 = bits(_T_13028, 46, 46) @[RegMapper.scala 175:77] + node _T_14018 = and(_T_14016, _T_14017) @[RegMapper.scala 175:66] + node _T_14019 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14021 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14022 = and(_T_14019, _T_14021) @[RegMapper.scala 176:46] + node _T_14023 = bits(_T_13028, 46, 46) @[RegMapper.scala 176:77] + node _T_14024 = and(_T_14022, _T_14023) @[RegMapper.scala 176:66] + node _T_14025 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14026 = and(_T_14025, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14027 = bits(_T_13094, 46, 46) @[RegMapper.scala 177:77] + node _T_14028 = and(_T_14026, _T_14027) @[RegMapper.scala 177:66] + node _T_14029 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14031 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14032 = and(_T_14029, _T_14031) @[RegMapper.scala 178:46] + node _T_14033 = bits(_T_13094, 46, 46) @[RegMapper.scala 178:77] + node _T_14034 = and(_T_14032, _T_14033) @[RegMapper.scala 178:66] + node _T_14035 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14036 = and(_T_14035, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14037 = bits(_T_13028, 47, 47) @[RegMapper.scala 175:77] + node _T_14038 = and(_T_14036, _T_14037) @[RegMapper.scala 175:66] + node _T_14039 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14041 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14042 = and(_T_14039, _T_14041) @[RegMapper.scala 176:46] + node _T_14043 = bits(_T_13028, 47, 47) @[RegMapper.scala 176:77] + node _T_14044 = and(_T_14042, _T_14043) @[RegMapper.scala 176:66] + node _T_14045 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14046 = and(_T_14045, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14047 = bits(_T_13094, 47, 47) @[RegMapper.scala 177:77] + node _T_14048 = and(_T_14046, _T_14047) @[RegMapper.scala 177:66] + node _T_14049 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14051 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14052 = and(_T_14049, _T_14051) @[RegMapper.scala 178:46] + node _T_14053 = bits(_T_13094, 47, 47) @[RegMapper.scala 178:77] + node _T_14054 = and(_T_14052, _T_14053) @[RegMapper.scala 178:66] + node _T_14055 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14056 = and(_T_14055, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14057 = bits(_T_13028, 48, 48) @[RegMapper.scala 175:77] + node _T_14058 = and(_T_14056, _T_14057) @[RegMapper.scala 175:66] + node _T_14059 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14061 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14062 = and(_T_14059, _T_14061) @[RegMapper.scala 176:46] + node _T_14063 = bits(_T_13028, 48, 48) @[RegMapper.scala 176:77] + node _T_14064 = and(_T_14062, _T_14063) @[RegMapper.scala 176:66] + node _T_14065 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14066 = and(_T_14065, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14067 = bits(_T_13094, 48, 48) @[RegMapper.scala 177:77] + node _T_14068 = and(_T_14066, _T_14067) @[RegMapper.scala 177:66] + node _T_14069 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14071 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14072 = and(_T_14069, _T_14071) @[RegMapper.scala 178:46] + node _T_14073 = bits(_T_13094, 48, 48) @[RegMapper.scala 178:77] + node _T_14074 = and(_T_14072, _T_14073) @[RegMapper.scala 178:66] + node _T_14075 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14076 = and(_T_14075, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14077 = bits(_T_13028, 49, 49) @[RegMapper.scala 175:77] + node _T_14078 = and(_T_14076, _T_14077) @[RegMapper.scala 175:66] + node _T_14079 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14081 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14082 = and(_T_14079, _T_14081) @[RegMapper.scala 176:46] + node _T_14083 = bits(_T_13028, 49, 49) @[RegMapper.scala 176:77] + node _T_14084 = and(_T_14082, _T_14083) @[RegMapper.scala 176:66] + node _T_14085 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14086 = and(_T_14085, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14087 = bits(_T_13094, 49, 49) @[RegMapper.scala 177:77] + node _T_14088 = and(_T_14086, _T_14087) @[RegMapper.scala 177:66] + node _T_14089 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14091 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14092 = and(_T_14089, _T_14091) @[RegMapper.scala 178:46] + node _T_14093 = bits(_T_13094, 49, 49) @[RegMapper.scala 178:77] + node _T_14094 = and(_T_14092, _T_14093) @[RegMapper.scala 178:66] + node _T_14095 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14096 = and(_T_14095, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14097 = bits(_T_13028, 50, 50) @[RegMapper.scala 175:77] + node _T_14098 = and(_T_14096, _T_14097) @[RegMapper.scala 175:66] + node _T_14099 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14101 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14102 = and(_T_14099, _T_14101) @[RegMapper.scala 176:46] + node _T_14103 = bits(_T_13028, 50, 50) @[RegMapper.scala 176:77] + node _T_14104 = and(_T_14102, _T_14103) @[RegMapper.scala 176:66] + node _T_14105 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14106 = and(_T_14105, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14107 = bits(_T_13094, 50, 50) @[RegMapper.scala 177:77] + node _T_14108 = and(_T_14106, _T_14107) @[RegMapper.scala 177:66] + node _T_14109 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14111 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14112 = and(_T_14109, _T_14111) @[RegMapper.scala 178:46] + node _T_14113 = bits(_T_13094, 50, 50) @[RegMapper.scala 178:77] + node _T_14114 = and(_T_14112, _T_14113) @[RegMapper.scala 178:66] + node _T_14115 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14116 = and(_T_14115, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14117 = bits(_T_13028, 51, 51) @[RegMapper.scala 175:77] + node _T_14118 = and(_T_14116, _T_14117) @[RegMapper.scala 175:66] + node _T_14119 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14121 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14122 = and(_T_14119, _T_14121) @[RegMapper.scala 176:46] + node _T_14123 = bits(_T_13028, 51, 51) @[RegMapper.scala 176:77] + node _T_14124 = and(_T_14122, _T_14123) @[RegMapper.scala 176:66] + node _T_14125 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14126 = and(_T_14125, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14127 = bits(_T_13094, 51, 51) @[RegMapper.scala 177:77] + node _T_14128 = and(_T_14126, _T_14127) @[RegMapper.scala 177:66] + node _T_14129 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14131 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14132 = and(_T_14129, _T_14131) @[RegMapper.scala 178:46] + node _T_14133 = bits(_T_13094, 51, 51) @[RegMapper.scala 178:77] + node _T_14134 = and(_T_14132, _T_14133) @[RegMapper.scala 178:66] + node _T_14135 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14136 = and(_T_14135, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14137 = bits(_T_13028, 52, 52) @[RegMapper.scala 175:77] + node _T_14138 = and(_T_14136, _T_14137) @[RegMapper.scala 175:66] + node _T_14139 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14141 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14142 = and(_T_14139, _T_14141) @[RegMapper.scala 176:46] + node _T_14143 = bits(_T_13028, 52, 52) @[RegMapper.scala 176:77] + node _T_14144 = and(_T_14142, _T_14143) @[RegMapper.scala 176:66] + node _T_14145 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14146 = and(_T_14145, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14147 = bits(_T_13094, 52, 52) @[RegMapper.scala 177:77] + node _T_14148 = and(_T_14146, _T_14147) @[RegMapper.scala 177:66] + node _T_14149 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14151 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14152 = and(_T_14149, _T_14151) @[RegMapper.scala 178:46] + node _T_14153 = bits(_T_13094, 52, 52) @[RegMapper.scala 178:77] + node _T_14154 = and(_T_14152, _T_14153) @[RegMapper.scala 178:66] + node _T_14155 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14156 = and(_T_14155, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14157 = bits(_T_13028, 53, 53) @[RegMapper.scala 175:77] + node _T_14158 = and(_T_14156, _T_14157) @[RegMapper.scala 175:66] + node _T_14159 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14161 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14162 = and(_T_14159, _T_14161) @[RegMapper.scala 176:46] + node _T_14163 = bits(_T_13028, 53, 53) @[RegMapper.scala 176:77] + node _T_14164 = and(_T_14162, _T_14163) @[RegMapper.scala 176:66] + node _T_14165 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14166 = and(_T_14165, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14167 = bits(_T_13094, 53, 53) @[RegMapper.scala 177:77] + node _T_14168 = and(_T_14166, _T_14167) @[RegMapper.scala 177:66] + node _T_14169 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14171 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14172 = and(_T_14169, _T_14171) @[RegMapper.scala 178:46] + node _T_14173 = bits(_T_13094, 53, 53) @[RegMapper.scala 178:77] + node _T_14174 = and(_T_14172, _T_14173) @[RegMapper.scala 178:66] + node _T_14175 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14176 = and(_T_14175, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14177 = bits(_T_13028, 54, 54) @[RegMapper.scala 175:77] + node _T_14178 = and(_T_14176, _T_14177) @[RegMapper.scala 175:66] + node _T_14179 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14181 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14182 = and(_T_14179, _T_14181) @[RegMapper.scala 176:46] + node _T_14183 = bits(_T_13028, 54, 54) @[RegMapper.scala 176:77] + node _T_14184 = and(_T_14182, _T_14183) @[RegMapper.scala 176:66] + node _T_14185 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14186 = and(_T_14185, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14187 = bits(_T_13094, 54, 54) @[RegMapper.scala 177:77] + node _T_14188 = and(_T_14186, _T_14187) @[RegMapper.scala 177:66] + node _T_14189 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14191 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14192 = and(_T_14189, _T_14191) @[RegMapper.scala 178:46] + node _T_14193 = bits(_T_13094, 54, 54) @[RegMapper.scala 178:77] + node _T_14194 = and(_T_14192, _T_14193) @[RegMapper.scala 178:66] + node _T_14195 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14196 = and(_T_14195, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14197 = bits(_T_13028, 55, 55) @[RegMapper.scala 175:77] + node _T_14198 = and(_T_14196, _T_14197) @[RegMapper.scala 175:66] + node _T_14199 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14201 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14202 = and(_T_14199, _T_14201) @[RegMapper.scala 176:46] + node _T_14203 = bits(_T_13028, 55, 55) @[RegMapper.scala 176:77] + node _T_14204 = and(_T_14202, _T_14203) @[RegMapper.scala 176:66] + node _T_14205 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14206 = and(_T_14205, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14207 = bits(_T_13094, 55, 55) @[RegMapper.scala 177:77] + node _T_14208 = and(_T_14206, _T_14207) @[RegMapper.scala 177:66] + node _T_14209 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14211 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14212 = and(_T_14209, _T_14211) @[RegMapper.scala 178:46] + node _T_14213 = bits(_T_13094, 55, 55) @[RegMapper.scala 178:77] + node _T_14214 = and(_T_14212, _T_14213) @[RegMapper.scala 178:66] + node _T_14215 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14216 = and(_T_14215, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14217 = bits(_T_13028, 56, 56) @[RegMapper.scala 175:77] + node _T_14218 = and(_T_14216, _T_14217) @[RegMapper.scala 175:66] + node _T_14219 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14221 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14222 = and(_T_14219, _T_14221) @[RegMapper.scala 176:46] + node _T_14223 = bits(_T_13028, 56, 56) @[RegMapper.scala 176:77] + node _T_14224 = and(_T_14222, _T_14223) @[RegMapper.scala 176:66] + node _T_14225 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14226 = and(_T_14225, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14227 = bits(_T_13094, 56, 56) @[RegMapper.scala 177:77] + node _T_14228 = and(_T_14226, _T_14227) @[RegMapper.scala 177:66] + node _T_14229 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14231 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14232 = and(_T_14229, _T_14231) @[RegMapper.scala 178:46] + node _T_14233 = bits(_T_13094, 56, 56) @[RegMapper.scala 178:77] + node _T_14234 = and(_T_14232, _T_14233) @[RegMapper.scala 178:66] + node _T_14235 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14236 = and(_T_14235, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14237 = bits(_T_13028, 57, 57) @[RegMapper.scala 175:77] + node _T_14238 = and(_T_14236, _T_14237) @[RegMapper.scala 175:66] + node _T_14239 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14241 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14242 = and(_T_14239, _T_14241) @[RegMapper.scala 176:46] + node _T_14243 = bits(_T_13028, 57, 57) @[RegMapper.scala 176:77] + node _T_14244 = and(_T_14242, _T_14243) @[RegMapper.scala 176:66] + node _T_14245 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14246 = and(_T_14245, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14247 = bits(_T_13094, 57, 57) @[RegMapper.scala 177:77] + node _T_14248 = and(_T_14246, _T_14247) @[RegMapper.scala 177:66] + node _T_14249 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14251 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14252 = and(_T_14249, _T_14251) @[RegMapper.scala 178:46] + node _T_14253 = bits(_T_13094, 57, 57) @[RegMapper.scala 178:77] + node _T_14254 = and(_T_14252, _T_14253) @[RegMapper.scala 178:66] + node _T_14255 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14256 = and(_T_14255, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14257 = bits(_T_13028, 58, 58) @[RegMapper.scala 175:77] + node _T_14258 = and(_T_14256, _T_14257) @[RegMapper.scala 175:66] + node _T_14259 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14261 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14262 = and(_T_14259, _T_14261) @[RegMapper.scala 176:46] + node _T_14263 = bits(_T_13028, 58, 58) @[RegMapper.scala 176:77] + node _T_14264 = and(_T_14262, _T_14263) @[RegMapper.scala 176:66] + node _T_14265 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14266 = and(_T_14265, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14267 = bits(_T_13094, 58, 58) @[RegMapper.scala 177:77] + node _T_14268 = and(_T_14266, _T_14267) @[RegMapper.scala 177:66] + node _T_14269 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14271 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14272 = and(_T_14269, _T_14271) @[RegMapper.scala 178:46] + node _T_14273 = bits(_T_13094, 58, 58) @[RegMapper.scala 178:77] + node _T_14274 = and(_T_14272, _T_14273) @[RegMapper.scala 178:66] + node _T_14275 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14276 = and(_T_14275, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14277 = bits(_T_13028, 59, 59) @[RegMapper.scala 175:77] + node _T_14278 = and(_T_14276, _T_14277) @[RegMapper.scala 175:66] + node _T_14279 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14281 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14282 = and(_T_14279, _T_14281) @[RegMapper.scala 176:46] + node _T_14283 = bits(_T_13028, 59, 59) @[RegMapper.scala 176:77] + node _T_14284 = and(_T_14282, _T_14283) @[RegMapper.scala 176:66] + node _T_14285 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14286 = and(_T_14285, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14287 = bits(_T_13094, 59, 59) @[RegMapper.scala 177:77] + node _T_14288 = and(_T_14286, _T_14287) @[RegMapper.scala 177:66] + node _T_14289 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14291 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14292 = and(_T_14289, _T_14291) @[RegMapper.scala 178:46] + node _T_14293 = bits(_T_13094, 59, 59) @[RegMapper.scala 178:77] + node _T_14294 = and(_T_14292, _T_14293) @[RegMapper.scala 178:66] + node _T_14295 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14296 = and(_T_14295, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14297 = bits(_T_13028, 60, 60) @[RegMapper.scala 175:77] + node _T_14298 = and(_T_14296, _T_14297) @[RegMapper.scala 175:66] + node _T_14299 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14301 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14302 = and(_T_14299, _T_14301) @[RegMapper.scala 176:46] + node _T_14303 = bits(_T_13028, 60, 60) @[RegMapper.scala 176:77] + node _T_14304 = and(_T_14302, _T_14303) @[RegMapper.scala 176:66] + node _T_14305 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14306 = and(_T_14305, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14307 = bits(_T_13094, 60, 60) @[RegMapper.scala 177:77] + node _T_14308 = and(_T_14306, _T_14307) @[RegMapper.scala 177:66] + node _T_14309 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14311 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14312 = and(_T_14309, _T_14311) @[RegMapper.scala 178:46] + node _T_14313 = bits(_T_13094, 60, 60) @[RegMapper.scala 178:77] + node _T_14314 = and(_T_14312, _T_14313) @[RegMapper.scala 178:66] + node _T_14315 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14316 = and(_T_14315, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14317 = bits(_T_13028, 61, 61) @[RegMapper.scala 175:77] + node _T_14318 = and(_T_14316, _T_14317) @[RegMapper.scala 175:66] + node _T_14319 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14321 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14322 = and(_T_14319, _T_14321) @[RegMapper.scala 176:46] + node _T_14323 = bits(_T_13028, 61, 61) @[RegMapper.scala 176:77] + node _T_14324 = and(_T_14322, _T_14323) @[RegMapper.scala 176:66] + node _T_14325 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14326 = and(_T_14325, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14327 = bits(_T_13094, 61, 61) @[RegMapper.scala 177:77] + node _T_14328 = and(_T_14326, _T_14327) @[RegMapper.scala 177:66] + node _T_14329 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14331 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14332 = and(_T_14329, _T_14331) @[RegMapper.scala 178:46] + node _T_14333 = bits(_T_13094, 61, 61) @[RegMapper.scala 178:77] + node _T_14334 = and(_T_14332, _T_14333) @[RegMapper.scala 178:66] + node _T_14335 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14336 = and(_T_14335, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14337 = bits(_T_13028, 62, 62) @[RegMapper.scala 175:77] + node _T_14338 = and(_T_14336, _T_14337) @[RegMapper.scala 175:66] + node _T_14339 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14341 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14342 = and(_T_14339, _T_14341) @[RegMapper.scala 176:46] + node _T_14343 = bits(_T_13028, 62, 62) @[RegMapper.scala 176:77] + node _T_14344 = and(_T_14342, _T_14343) @[RegMapper.scala 176:66] + node _T_14345 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14346 = and(_T_14345, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14347 = bits(_T_13094, 62, 62) @[RegMapper.scala 177:77] + node _T_14348 = and(_T_14346, _T_14347) @[RegMapper.scala 177:66] + node _T_14349 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14351 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14352 = and(_T_14349, _T_14351) @[RegMapper.scala 178:46] + node _T_14353 = bits(_T_13094, 62, 62) @[RegMapper.scala 178:77] + node _T_14354 = and(_T_14352, _T_14353) @[RegMapper.scala 178:66] + node _T_14355 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 175:31] + node _T_14356 = and(_T_14355, _T_1583.bits.read) @[RegMapper.scala 175:46] + node _T_14357 = bits(_T_13028, 63, 63) @[RegMapper.scala 175:77] + node _T_14358 = and(_T_14356, _T_14357) @[RegMapper.scala 175:66] + node _T_14359 = and(_T_1507.valid, _T_1583.ready) @[RegMapper.scala 176:31] + node _T_14361 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_14362 = and(_T_14359, _T_14361) @[RegMapper.scala 176:46] + node _T_14363 = bits(_T_13028, 63, 63) @[RegMapper.scala 176:77] + node _T_14364 = and(_T_14362, _T_14363) @[RegMapper.scala 176:66] + node _T_14365 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 177:33] + node _T_14366 = and(_T_14365, _T_1583.bits.read) @[RegMapper.scala 177:46] + node _T_14367 = bits(_T_13094, 63, 63) @[RegMapper.scala 177:77] + node _T_14368 = and(_T_14366, _T_14367) @[RegMapper.scala 177:66] + node _T_14369 = and(_T_1583.valid, _T_1547.ready) @[RegMapper.scala 178:33] + node _T_14371 = eq(_T_1583.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_14372 = and(_T_14369, _T_14371) @[RegMapper.scala 178:46] + node _T_14373 = bits(_T_13094, 63, 63) @[RegMapper.scala 178:77] + node _T_14374 = and(_T_14372, _T_14373) @[RegMapper.scala 178:66] + node _T_14375 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14376 = and(_T_14375, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14377 = and(_T_14376, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14378 = and(_T_14377, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14379 = and(_T_14378, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14380 = and(_T_14379, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14381 = and(_T_14380, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14382 = and(_T_14381, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[0] <= _T_14382 @[RegMapper.scala 184:18] + node _T_14383 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14384 = and(_T_14383, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14385 = and(_T_14384, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14386 = and(_T_14385, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14387 = and(_T_14386, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14388 = and(_T_14387, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14389 = and(_T_14388, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14390 = and(_T_14389, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[0] <= _T_14390 @[RegMapper.scala 185:18] + node _T_14391 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14392 = and(_T_14391, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14393 = and(_T_14392, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14394 = and(_T_14393, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14395 = and(_T_14394, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14396 = and(_T_14395, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14397 = and(_T_14396, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14398 = and(_T_14397, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[0] <= _T_14398 @[RegMapper.scala 186:18] + node _T_14399 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14400 = and(_T_14399, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14401 = and(_T_14400, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14402 = and(_T_14401, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14403 = and(_T_14402, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14404 = and(_T_14403, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14405 = and(_T_14404, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14406 = and(_T_14405, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[0] <= _T_14406 @[RegMapper.scala 187:18] + node _T_14407 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14408 = and(_T_14407, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14409 = and(_T_14408, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14410 = and(_T_14409, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14411 = and(_T_14410, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14412 = and(_T_14411, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14413 = and(_T_14412, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14414 = and(_T_14413, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[1] <= _T_14414 @[RegMapper.scala 184:18] + node _T_14415 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14416 = and(_T_14415, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14417 = and(_T_14416, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14418 = and(_T_14417, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14419 = and(_T_14418, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14420 = and(_T_14419, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14421 = and(_T_14420, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14422 = and(_T_14421, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[1] <= _T_14422 @[RegMapper.scala 185:18] + node _T_14423 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14424 = and(_T_14423, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14425 = and(_T_14424, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14426 = and(_T_14425, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14427 = and(_T_14426, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14428 = and(_T_14427, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14429 = and(_T_14428, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14430 = and(_T_14429, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[1] <= _T_14430 @[RegMapper.scala 186:18] + node _T_14431 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14432 = and(_T_14431, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14433 = and(_T_14432, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14434 = and(_T_14433, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14435 = and(_T_14434, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14436 = and(_T_14435, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14437 = and(_T_14436, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14438 = and(_T_14437, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[1] <= _T_14438 @[RegMapper.scala 187:18] + node _T_14439 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14440 = and(_T_14439, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14441 = and(_T_14440, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14442 = and(_T_14441, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14443 = and(_T_14442, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14444 = and(_T_14443, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14445 = and(_T_14444, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14446 = and(_T_14445, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[2] <= _T_14446 @[RegMapper.scala 184:18] + node _T_14447 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14448 = and(_T_14447, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14449 = and(_T_14448, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14450 = and(_T_14449, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14451 = and(_T_14450, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14452 = and(_T_14451, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14453 = and(_T_14452, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14454 = and(_T_14453, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[2] <= _T_14454 @[RegMapper.scala 185:18] + node _T_14455 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14456 = and(_T_14455, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14457 = and(_T_14456, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14458 = and(_T_14457, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14459 = and(_T_14458, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14460 = and(_T_14459, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14461 = and(_T_14460, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14462 = and(_T_14461, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[2] <= _T_14462 @[RegMapper.scala 186:18] + node _T_14463 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14464 = and(_T_14463, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14465 = and(_T_14464, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14466 = and(_T_14465, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14467 = and(_T_14466, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14468 = and(_T_14467, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14469 = and(_T_14468, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14470 = and(_T_14469, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[2] <= _T_14470 @[RegMapper.scala 187:18] + node _T_14471 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14472 = and(_T_14471, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14473 = and(_T_14472, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14474 = and(_T_14473, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14475 = and(_T_14474, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14476 = and(_T_14475, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14477 = and(_T_14476, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14478 = and(_T_14477, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[3] <= _T_14478 @[RegMapper.scala 184:18] + node _T_14479 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14480 = and(_T_14479, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14481 = and(_T_14480, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14482 = and(_T_14481, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14483 = and(_T_14482, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14484 = and(_T_14483, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14485 = and(_T_14484, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14486 = and(_T_14485, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[3] <= _T_14486 @[RegMapper.scala 185:18] + node _T_14487 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14488 = and(_T_14487, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14489 = and(_T_14488, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14490 = and(_T_14489, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14491 = and(_T_14490, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14492 = and(_T_14491, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14493 = and(_T_14492, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14494 = and(_T_14493, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[3] <= _T_14494 @[RegMapper.scala 186:18] + node _T_14495 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14496 = and(_T_14495, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14497 = and(_T_14496, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14498 = and(_T_14497, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14499 = and(_T_14498, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14500 = and(_T_14499, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14501 = and(_T_14500, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14502 = and(_T_14501, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[3] <= _T_14502 @[RegMapper.scala 187:18] + node _T_14503 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14504 = and(_T_14503, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14505 = and(_T_14504, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14506 = and(_T_14505, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14507 = and(_T_14506, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14508 = and(_T_14507, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14509 = and(_T_14508, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14510 = and(_T_14509, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[4] <= _T_14510 @[RegMapper.scala 184:18] + node _T_14511 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14512 = and(_T_14511, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14513 = and(_T_14512, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14514 = and(_T_14513, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14515 = and(_T_14514, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14516 = and(_T_14515, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14517 = and(_T_14516, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14518 = and(_T_14517, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[4] <= _T_14518 @[RegMapper.scala 185:18] + node _T_14519 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14520 = and(_T_14519, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14521 = and(_T_14520, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14522 = and(_T_14521, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14523 = and(_T_14522, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14524 = and(_T_14523, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14525 = and(_T_14524, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14526 = and(_T_14525, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[4] <= _T_14526 @[RegMapper.scala 186:18] + node _T_14527 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14528 = and(_T_14527, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14529 = and(_T_14528, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14530 = and(_T_14529, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14531 = and(_T_14530, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14532 = and(_T_14531, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14533 = and(_T_14532, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14534 = and(_T_14533, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[4] <= _T_14534 @[RegMapper.scala 187:18] + node _T_14535 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14536 = and(_T_14535, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14537 = and(_T_14536, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14538 = and(_T_14537, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14539 = and(_T_14538, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14540 = and(_T_14539, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14541 = and(_T_14540, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14542 = and(_T_14541, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[5] <= _T_14542 @[RegMapper.scala 184:18] + node _T_14543 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14544 = and(_T_14543, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14545 = and(_T_14544, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14546 = and(_T_14545, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14547 = and(_T_14546, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14548 = and(_T_14547, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14549 = and(_T_14548, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14550 = and(_T_14549, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[5] <= _T_14550 @[RegMapper.scala 185:18] + node _T_14551 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14552 = and(_T_14551, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14553 = and(_T_14552, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14554 = and(_T_14553, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14555 = and(_T_14554, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14556 = and(_T_14555, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14557 = and(_T_14556, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14558 = and(_T_14557, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[5] <= _T_14558 @[RegMapper.scala 186:18] + node _T_14559 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14560 = and(_T_14559, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14561 = and(_T_14560, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14562 = and(_T_14561, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14563 = and(_T_14562, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14564 = and(_T_14563, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14565 = and(_T_14564, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14566 = and(_T_14565, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[5] <= _T_14566 @[RegMapper.scala 187:18] + node _T_14567 = and(_T_13998, _T_2334[7]) @[RegMapper.scala 184:66] + node _T_14568 = and(_T_14567, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14569 = and(_T_14568, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14570 = and(_T_14569, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14571 = and(_T_14570, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14572 = and(_T_14571, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14573 = and(_T_14572, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14574 = and(_T_14573, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[6] <= _T_14574 @[RegMapper.scala 184:18] + node _T_14575 = and(_T_14004, _T_2522[7]) @[RegMapper.scala 185:66] + node _T_14576 = and(_T_14575, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14577 = and(_T_14576, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14578 = and(_T_14577, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14579 = and(_T_14578, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14580 = and(_T_14579, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14581 = and(_T_14580, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14582 = and(_T_14581, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[6] <= _T_14582 @[RegMapper.scala 185:18] + node _T_14583 = and(_T_14008, _T_2710[7]) @[RegMapper.scala 186:66] + node _T_14584 = and(_T_14583, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14585 = and(_T_14584, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14586 = and(_T_14585, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14587 = and(_T_14586, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14588 = and(_T_14587, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14589 = and(_T_14588, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14590 = and(_T_14589, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[6] <= _T_14590 @[RegMapper.scala 186:18] + node _T_14591 = and(_T_14014, _T_2898[7]) @[RegMapper.scala 187:66] + node _T_14592 = and(_T_14591, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14593 = and(_T_14592, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14594 = and(_T_14593, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14595 = and(_T_14594, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14596 = and(_T_14595, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14597 = and(_T_14596, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14598 = and(_T_14597, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[6] <= _T_14598 @[RegMapper.scala 187:18] + node _T_14599 = and(_T_13998, _T_2334[6]) @[RegMapper.scala 184:66] + node _T_14600 = and(_T_14599, _T_2334[5]) @[RegMapper.scala 184:66] + node _T_14601 = and(_T_14600, _T_2334[4]) @[RegMapper.scala 184:66] + node _T_14602 = and(_T_14601, _T_2334[3]) @[RegMapper.scala 184:66] + node _T_14603 = and(_T_14602, _T_2334[2]) @[RegMapper.scala 184:66] + node _T_14604 = and(_T_14603, _T_2334[1]) @[RegMapper.scala 184:66] + node _T_14605 = and(_T_14604, _T_2334[0]) @[RegMapper.scala 184:66] + node _T_14606 = and(_T_14605, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[7] <= _T_14606 @[RegMapper.scala 184:18] + node _T_14607 = and(_T_14004, _T_2522[6]) @[RegMapper.scala 185:66] + node _T_14608 = and(_T_14607, _T_2522[5]) @[RegMapper.scala 185:66] + node _T_14609 = and(_T_14608, _T_2522[4]) @[RegMapper.scala 185:66] + node _T_14610 = and(_T_14609, _T_2522[3]) @[RegMapper.scala 185:66] + node _T_14611 = and(_T_14610, _T_2522[2]) @[RegMapper.scala 185:66] + node _T_14612 = and(_T_14611, _T_2522[1]) @[RegMapper.scala 185:66] + node _T_14613 = and(_T_14612, _T_2522[0]) @[RegMapper.scala 185:66] + node _T_14614 = and(_T_14613, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[7] <= _T_14614 @[RegMapper.scala 185:18] + node _T_14615 = and(_T_14008, _T_2710[6]) @[RegMapper.scala 186:66] + node _T_14616 = and(_T_14615, _T_2710[5]) @[RegMapper.scala 186:66] + node _T_14617 = and(_T_14616, _T_2710[4]) @[RegMapper.scala 186:66] + node _T_14618 = and(_T_14617, _T_2710[3]) @[RegMapper.scala 186:66] + node _T_14619 = and(_T_14618, _T_2710[2]) @[RegMapper.scala 186:66] + node _T_14620 = and(_T_14619, _T_2710[1]) @[RegMapper.scala 186:66] + node _T_14621 = and(_T_14620, _T_2710[0]) @[RegMapper.scala 186:66] + node _T_14622 = and(_T_14621, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[7] <= _T_14622 @[RegMapper.scala 186:18] + node _T_14623 = and(_T_14014, _T_2898[6]) @[RegMapper.scala 187:66] + node _T_14624 = and(_T_14623, _T_2898[5]) @[RegMapper.scala 187:66] + node _T_14625 = and(_T_14624, _T_2898[4]) @[RegMapper.scala 187:66] + node _T_14626 = and(_T_14625, _T_2898[3]) @[RegMapper.scala 187:66] + node _T_14627 = and(_T_14626, _T_2898[2]) @[RegMapper.scala 187:66] + node _T_14628 = and(_T_14627, _T_2898[1]) @[RegMapper.scala 187:66] + node _T_14629 = and(_T_14628, _T_2898[0]) @[RegMapper.scala 187:66] + node _T_14630 = and(_T_14629, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[7] <= _T_14630 @[RegMapper.scala 187:18] + node _T_14631 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14632 = and(_T_14631, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14633 = and(_T_14632, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14634 = and(_T_14633, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14635 = and(_T_14634, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14636 = and(_T_14635, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14637 = and(_T_14636, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14638 = and(_T_14637, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[8] <= _T_14638 @[RegMapper.scala 184:18] + node _T_14639 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14640 = and(_T_14639, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14641 = and(_T_14640, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14642 = and(_T_14641, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14643 = and(_T_14642, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14644 = and(_T_14643, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14645 = and(_T_14644, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14646 = and(_T_14645, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[8] <= _T_14646 @[RegMapper.scala 185:18] + node _T_14647 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14648 = and(_T_14647, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14649 = and(_T_14648, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14650 = and(_T_14649, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14651 = and(_T_14650, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14652 = and(_T_14651, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14653 = and(_T_14652, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14654 = and(_T_14653, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[8] <= _T_14654 @[RegMapper.scala 186:18] + node _T_14655 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14656 = and(_T_14655, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14657 = and(_T_14656, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14658 = and(_T_14657, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14659 = and(_T_14658, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14660 = and(_T_14659, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14661 = and(_T_14660, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14662 = and(_T_14661, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[8] <= _T_14662 @[RegMapper.scala 187:18] + node _T_14663 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14664 = and(_T_14663, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14665 = and(_T_14664, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14666 = and(_T_14665, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14667 = and(_T_14666, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14668 = and(_T_14667, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14669 = and(_T_14668, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14670 = and(_T_14669, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[9] <= _T_14670 @[RegMapper.scala 184:18] + node _T_14671 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14672 = and(_T_14671, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14673 = and(_T_14672, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14674 = and(_T_14673, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14675 = and(_T_14674, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14676 = and(_T_14675, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14677 = and(_T_14676, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14678 = and(_T_14677, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[9] <= _T_14678 @[RegMapper.scala 185:18] + node _T_14679 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14680 = and(_T_14679, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14681 = and(_T_14680, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14682 = and(_T_14681, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14683 = and(_T_14682, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14684 = and(_T_14683, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14685 = and(_T_14684, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14686 = and(_T_14685, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[9] <= _T_14686 @[RegMapper.scala 186:18] + node _T_14687 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14688 = and(_T_14687, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14689 = and(_T_14688, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14690 = and(_T_14689, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14691 = and(_T_14690, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14692 = and(_T_14691, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14693 = and(_T_14692, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14694 = and(_T_14693, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[9] <= _T_14694 @[RegMapper.scala 187:18] + node _T_14695 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14696 = and(_T_14695, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14697 = and(_T_14696, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14698 = and(_T_14697, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14699 = and(_T_14698, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14700 = and(_T_14699, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14701 = and(_T_14700, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14702 = and(_T_14701, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[10] <= _T_14702 @[RegMapper.scala 184:18] + node _T_14703 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14704 = and(_T_14703, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14705 = and(_T_14704, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14706 = and(_T_14705, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14707 = and(_T_14706, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14708 = and(_T_14707, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14709 = and(_T_14708, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14710 = and(_T_14709, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[10] <= _T_14710 @[RegMapper.scala 185:18] + node _T_14711 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14712 = and(_T_14711, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14713 = and(_T_14712, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14714 = and(_T_14713, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14715 = and(_T_14714, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14716 = and(_T_14715, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14717 = and(_T_14716, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14718 = and(_T_14717, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[10] <= _T_14718 @[RegMapper.scala 186:18] + node _T_14719 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14720 = and(_T_14719, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14721 = and(_T_14720, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14722 = and(_T_14721, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14723 = and(_T_14722, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14724 = and(_T_14723, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14725 = and(_T_14724, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14726 = and(_T_14725, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[10] <= _T_14726 @[RegMapper.scala 187:18] + node _T_14727 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14728 = and(_T_14727, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14729 = and(_T_14728, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14730 = and(_T_14729, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14731 = and(_T_14730, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14732 = and(_T_14731, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14733 = and(_T_14732, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14734 = and(_T_14733, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[11] <= _T_14734 @[RegMapper.scala 184:18] + node _T_14735 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14736 = and(_T_14735, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14737 = and(_T_14736, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14738 = and(_T_14737, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14739 = and(_T_14738, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14740 = and(_T_14739, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14741 = and(_T_14740, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14742 = and(_T_14741, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[11] <= _T_14742 @[RegMapper.scala 185:18] + node _T_14743 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14744 = and(_T_14743, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14745 = and(_T_14744, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14746 = and(_T_14745, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14747 = and(_T_14746, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14748 = and(_T_14747, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14749 = and(_T_14748, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14750 = and(_T_14749, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[11] <= _T_14750 @[RegMapper.scala 186:18] + node _T_14751 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14752 = and(_T_14751, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14753 = and(_T_14752, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14754 = and(_T_14753, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14755 = and(_T_14754, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14756 = and(_T_14755, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14757 = and(_T_14756, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14758 = and(_T_14757, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[11] <= _T_14758 @[RegMapper.scala 187:18] + node _T_14759 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14760 = and(_T_14759, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14761 = and(_T_14760, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14762 = and(_T_14761, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14763 = and(_T_14762, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14764 = and(_T_14763, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14765 = and(_T_14764, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14766 = and(_T_14765, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[12] <= _T_14766 @[RegMapper.scala 184:18] + node _T_14767 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14768 = and(_T_14767, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14769 = and(_T_14768, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14770 = and(_T_14769, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14771 = and(_T_14770, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14772 = and(_T_14771, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14773 = and(_T_14772, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14774 = and(_T_14773, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[12] <= _T_14774 @[RegMapper.scala 185:18] + node _T_14775 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14776 = and(_T_14775, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14777 = and(_T_14776, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14778 = and(_T_14777, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14779 = and(_T_14778, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14780 = and(_T_14779, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14781 = and(_T_14780, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14782 = and(_T_14781, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[12] <= _T_14782 @[RegMapper.scala 186:18] + node _T_14783 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14784 = and(_T_14783, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14785 = and(_T_14784, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14786 = and(_T_14785, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14787 = and(_T_14786, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14788 = and(_T_14787, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14789 = and(_T_14788, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14790 = and(_T_14789, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[12] <= _T_14790 @[RegMapper.scala 187:18] + node _T_14791 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14792 = and(_T_14791, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14793 = and(_T_14792, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14794 = and(_T_14793, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14795 = and(_T_14794, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14796 = and(_T_14795, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14797 = and(_T_14796, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14798 = and(_T_14797, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[13] <= _T_14798 @[RegMapper.scala 184:18] + node _T_14799 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14800 = and(_T_14799, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14801 = and(_T_14800, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14802 = and(_T_14801, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14803 = and(_T_14802, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14804 = and(_T_14803, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14805 = and(_T_14804, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14806 = and(_T_14805, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[13] <= _T_14806 @[RegMapper.scala 185:18] + node _T_14807 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14808 = and(_T_14807, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14809 = and(_T_14808, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14810 = and(_T_14809, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14811 = and(_T_14810, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14812 = and(_T_14811, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14813 = and(_T_14812, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14814 = and(_T_14813, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[13] <= _T_14814 @[RegMapper.scala 186:18] + node _T_14815 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14816 = and(_T_14815, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14817 = and(_T_14816, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14818 = and(_T_14817, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14819 = and(_T_14818, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14820 = and(_T_14819, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14821 = and(_T_14820, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14822 = and(_T_14821, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[13] <= _T_14822 @[RegMapper.scala 187:18] + node _T_14823 = and(_T_13758, _T_2334[15]) @[RegMapper.scala 184:66] + node _T_14824 = and(_T_14823, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14825 = and(_T_14824, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14826 = and(_T_14825, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14827 = and(_T_14826, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14828 = and(_T_14827, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14829 = and(_T_14828, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14830 = and(_T_14829, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[14] <= _T_14830 @[RegMapper.scala 184:18] + node _T_14831 = and(_T_13764, _T_2522[15]) @[RegMapper.scala 185:66] + node _T_14832 = and(_T_14831, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14833 = and(_T_14832, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14834 = and(_T_14833, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14835 = and(_T_14834, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14836 = and(_T_14835, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14837 = and(_T_14836, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14838 = and(_T_14837, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[14] <= _T_14838 @[RegMapper.scala 185:18] + node _T_14839 = and(_T_13768, _T_2710[15]) @[RegMapper.scala 186:66] + node _T_14840 = and(_T_14839, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14841 = and(_T_14840, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14842 = and(_T_14841, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14843 = and(_T_14842, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14844 = and(_T_14843, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14845 = and(_T_14844, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14846 = and(_T_14845, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[14] <= _T_14846 @[RegMapper.scala 186:18] + node _T_14847 = and(_T_13774, _T_2898[15]) @[RegMapper.scala 187:66] + node _T_14848 = and(_T_14847, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14849 = and(_T_14848, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14850 = and(_T_14849, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14851 = and(_T_14850, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14852 = and(_T_14851, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14853 = and(_T_14852, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14854 = and(_T_14853, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[14] <= _T_14854 @[RegMapper.scala 187:18] + node _T_14855 = and(_T_13758, _T_2334[14]) @[RegMapper.scala 184:66] + node _T_14856 = and(_T_14855, _T_2334[13]) @[RegMapper.scala 184:66] + node _T_14857 = and(_T_14856, _T_2334[12]) @[RegMapper.scala 184:66] + node _T_14858 = and(_T_14857, _T_2334[11]) @[RegMapper.scala 184:66] + node _T_14859 = and(_T_14858, _T_2334[10]) @[RegMapper.scala 184:66] + node _T_14860 = and(_T_14859, _T_2334[9]) @[RegMapper.scala 184:66] + node _T_14861 = and(_T_14860, _T_2334[8]) @[RegMapper.scala 184:66] + node _T_14862 = and(_T_14861, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[15] <= _T_14862 @[RegMapper.scala 184:18] + node _T_14863 = and(_T_13764, _T_2522[14]) @[RegMapper.scala 185:66] + node _T_14864 = and(_T_14863, _T_2522[13]) @[RegMapper.scala 185:66] + node _T_14865 = and(_T_14864, _T_2522[12]) @[RegMapper.scala 185:66] + node _T_14866 = and(_T_14865, _T_2522[11]) @[RegMapper.scala 185:66] + node _T_14867 = and(_T_14866, _T_2522[10]) @[RegMapper.scala 185:66] + node _T_14868 = and(_T_14867, _T_2522[9]) @[RegMapper.scala 185:66] + node _T_14869 = and(_T_14868, _T_2522[8]) @[RegMapper.scala 185:66] + node _T_14870 = and(_T_14869, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[15] <= _T_14870 @[RegMapper.scala 185:18] + node _T_14871 = and(_T_13768, _T_2710[14]) @[RegMapper.scala 186:66] + node _T_14872 = and(_T_14871, _T_2710[13]) @[RegMapper.scala 186:66] + node _T_14873 = and(_T_14872, _T_2710[12]) @[RegMapper.scala 186:66] + node _T_14874 = and(_T_14873, _T_2710[11]) @[RegMapper.scala 186:66] + node _T_14875 = and(_T_14874, _T_2710[10]) @[RegMapper.scala 186:66] + node _T_14876 = and(_T_14875, _T_2710[9]) @[RegMapper.scala 186:66] + node _T_14877 = and(_T_14876, _T_2710[8]) @[RegMapper.scala 186:66] + node _T_14878 = and(_T_14877, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[15] <= _T_14878 @[RegMapper.scala 186:18] + node _T_14879 = and(_T_13774, _T_2898[14]) @[RegMapper.scala 187:66] + node _T_14880 = and(_T_14879, _T_2898[13]) @[RegMapper.scala 187:66] + node _T_14881 = and(_T_14880, _T_2898[12]) @[RegMapper.scala 187:66] + node _T_14882 = and(_T_14881, _T_2898[11]) @[RegMapper.scala 187:66] + node _T_14883 = and(_T_14882, _T_2898[10]) @[RegMapper.scala 187:66] + node _T_14884 = and(_T_14883, _T_2898[9]) @[RegMapper.scala 187:66] + node _T_14885 = and(_T_14884, _T_2898[8]) @[RegMapper.scala 187:66] + node _T_14886 = and(_T_14885, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[15] <= _T_14886 @[RegMapper.scala 187:18] + node _T_14887 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_14888 = and(_T_14887, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_14889 = and(_T_14888, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_14890 = and(_T_14889, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_14891 = and(_T_14890, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_14892 = and(_T_14891, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_14893 = and(_T_14892, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_14894 = and(_T_14893, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[16] <= _T_14894 @[RegMapper.scala 184:18] + node _T_14895 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_14896 = and(_T_14895, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_14897 = and(_T_14896, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_14898 = and(_T_14897, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_14899 = and(_T_14898, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_14900 = and(_T_14899, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_14901 = and(_T_14900, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_14902 = and(_T_14901, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[16] <= _T_14902 @[RegMapper.scala 185:18] + node _T_14903 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_14904 = and(_T_14903, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_14905 = and(_T_14904, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_14906 = and(_T_14905, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_14907 = and(_T_14906, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_14908 = and(_T_14907, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_14909 = and(_T_14908, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_14910 = and(_T_14909, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[16] <= _T_14910 @[RegMapper.scala 186:18] + node _T_14911 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_14912 = and(_T_14911, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_14913 = and(_T_14912, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_14914 = and(_T_14913, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_14915 = and(_T_14914, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_14916 = and(_T_14915, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_14917 = and(_T_14916, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_14918 = and(_T_14917, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[16] <= _T_14918 @[RegMapper.scala 187:18] + node _T_14919 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_14920 = and(_T_14919, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_14921 = and(_T_14920, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_14922 = and(_T_14921, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_14923 = and(_T_14922, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_14924 = and(_T_14923, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_14925 = and(_T_14924, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_14926 = and(_T_14925, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[17] <= _T_14926 @[RegMapper.scala 184:18] + node _T_14927 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_14928 = and(_T_14927, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_14929 = and(_T_14928, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_14930 = and(_T_14929, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_14931 = and(_T_14930, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_14932 = and(_T_14931, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_14933 = and(_T_14932, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_14934 = and(_T_14933, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[17] <= _T_14934 @[RegMapper.scala 185:18] + node _T_14935 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_14936 = and(_T_14935, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_14937 = and(_T_14936, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_14938 = and(_T_14937, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_14939 = and(_T_14938, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_14940 = and(_T_14939, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_14941 = and(_T_14940, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_14942 = and(_T_14941, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[17] <= _T_14942 @[RegMapper.scala 186:18] + node _T_14943 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_14944 = and(_T_14943, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_14945 = and(_T_14944, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_14946 = and(_T_14945, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_14947 = and(_T_14946, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_14948 = and(_T_14947, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_14949 = and(_T_14948, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_14950 = and(_T_14949, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[17] <= _T_14950 @[RegMapper.scala 187:18] + node _T_14951 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_14952 = and(_T_14951, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_14953 = and(_T_14952, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_14954 = and(_T_14953, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_14955 = and(_T_14954, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_14956 = and(_T_14955, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_14957 = and(_T_14956, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_14958 = and(_T_14957, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[18] <= _T_14958 @[RegMapper.scala 184:18] + node _T_14959 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_14960 = and(_T_14959, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_14961 = and(_T_14960, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_14962 = and(_T_14961, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_14963 = and(_T_14962, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_14964 = and(_T_14963, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_14965 = and(_T_14964, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_14966 = and(_T_14965, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[18] <= _T_14966 @[RegMapper.scala 185:18] + node _T_14967 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_14968 = and(_T_14967, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_14969 = and(_T_14968, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_14970 = and(_T_14969, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_14971 = and(_T_14970, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_14972 = and(_T_14971, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_14973 = and(_T_14972, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_14974 = and(_T_14973, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[18] <= _T_14974 @[RegMapper.scala 186:18] + node _T_14975 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_14976 = and(_T_14975, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_14977 = and(_T_14976, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_14978 = and(_T_14977, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_14979 = and(_T_14978, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_14980 = and(_T_14979, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_14981 = and(_T_14980, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_14982 = and(_T_14981, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[18] <= _T_14982 @[RegMapper.scala 187:18] + node _T_14983 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_14984 = and(_T_14983, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_14985 = and(_T_14984, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_14986 = and(_T_14985, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_14987 = and(_T_14986, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_14988 = and(_T_14987, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_14989 = and(_T_14988, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_14990 = and(_T_14989, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[19] <= _T_14990 @[RegMapper.scala 184:18] + node _T_14991 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_14992 = and(_T_14991, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_14993 = and(_T_14992, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_14994 = and(_T_14993, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_14995 = and(_T_14994, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_14996 = and(_T_14995, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_14997 = and(_T_14996, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_14998 = and(_T_14997, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[19] <= _T_14998 @[RegMapper.scala 185:18] + node _T_14999 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_15000 = and(_T_14999, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_15001 = and(_T_15000, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_15002 = and(_T_15001, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_15003 = and(_T_15002, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_15004 = and(_T_15003, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_15005 = and(_T_15004, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_15006 = and(_T_15005, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[19] <= _T_15006 @[RegMapper.scala 186:18] + node _T_15007 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_15008 = and(_T_15007, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_15009 = and(_T_15008, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_15010 = and(_T_15009, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_15011 = and(_T_15010, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_15012 = and(_T_15011, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_15013 = and(_T_15012, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_15014 = and(_T_15013, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[19] <= _T_15014 @[RegMapper.scala 187:18] + node _T_15015 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_15016 = and(_T_15015, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_15017 = and(_T_15016, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_15018 = and(_T_15017, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_15019 = and(_T_15018, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_15020 = and(_T_15019, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_15021 = and(_T_15020, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_15022 = and(_T_15021, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[20] <= _T_15022 @[RegMapper.scala 184:18] + node _T_15023 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_15024 = and(_T_15023, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_15025 = and(_T_15024, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_15026 = and(_T_15025, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_15027 = and(_T_15026, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_15028 = and(_T_15027, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_15029 = and(_T_15028, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_15030 = and(_T_15029, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[20] <= _T_15030 @[RegMapper.scala 185:18] + node _T_15031 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_15032 = and(_T_15031, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_15033 = and(_T_15032, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_15034 = and(_T_15033, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_15035 = and(_T_15034, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_15036 = and(_T_15035, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_15037 = and(_T_15036, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_15038 = and(_T_15037, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[20] <= _T_15038 @[RegMapper.scala 186:18] + node _T_15039 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_15040 = and(_T_15039, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_15041 = and(_T_15040, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_15042 = and(_T_15041, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_15043 = and(_T_15042, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_15044 = and(_T_15043, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_15045 = and(_T_15044, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_15046 = and(_T_15045, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[20] <= _T_15046 @[RegMapper.scala 187:18] + node _T_15047 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_15048 = and(_T_15047, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_15049 = and(_T_15048, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_15050 = and(_T_15049, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_15051 = and(_T_15050, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_15052 = and(_T_15051, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_15053 = and(_T_15052, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_15054 = and(_T_15053, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[21] <= _T_15054 @[RegMapper.scala 184:18] + node _T_15055 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_15056 = and(_T_15055, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_15057 = and(_T_15056, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_15058 = and(_T_15057, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_15059 = and(_T_15058, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_15060 = and(_T_15059, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_15061 = and(_T_15060, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_15062 = and(_T_15061, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[21] <= _T_15062 @[RegMapper.scala 185:18] + node _T_15063 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_15064 = and(_T_15063, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_15065 = and(_T_15064, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_15066 = and(_T_15065, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_15067 = and(_T_15066, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_15068 = and(_T_15067, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_15069 = and(_T_15068, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_15070 = and(_T_15069, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[21] <= _T_15070 @[RegMapper.scala 186:18] + node _T_15071 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_15072 = and(_T_15071, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_15073 = and(_T_15072, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_15074 = and(_T_15073, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_15075 = and(_T_15074, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_15076 = and(_T_15075, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_15077 = and(_T_15076, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_15078 = and(_T_15077, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[21] <= _T_15078 @[RegMapper.scala 187:18] + node _T_15079 = and(_T_13838, _T_2334[23]) @[RegMapper.scala 184:66] + node _T_15080 = and(_T_15079, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_15081 = and(_T_15080, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_15082 = and(_T_15081, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_15083 = and(_T_15082, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_15084 = and(_T_15083, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_15085 = and(_T_15084, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_15086 = and(_T_15085, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[22] <= _T_15086 @[RegMapper.scala 184:18] + node _T_15087 = and(_T_13844, _T_2522[23]) @[RegMapper.scala 185:66] + node _T_15088 = and(_T_15087, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_15089 = and(_T_15088, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_15090 = and(_T_15089, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_15091 = and(_T_15090, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_15092 = and(_T_15091, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_15093 = and(_T_15092, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_15094 = and(_T_15093, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[22] <= _T_15094 @[RegMapper.scala 185:18] + node _T_15095 = and(_T_13848, _T_2710[23]) @[RegMapper.scala 186:66] + node _T_15096 = and(_T_15095, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_15097 = and(_T_15096, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_15098 = and(_T_15097, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_15099 = and(_T_15098, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_15100 = and(_T_15099, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_15101 = and(_T_15100, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_15102 = and(_T_15101, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[22] <= _T_15102 @[RegMapper.scala 186:18] + node _T_15103 = and(_T_13854, _T_2898[23]) @[RegMapper.scala 187:66] + node _T_15104 = and(_T_15103, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_15105 = and(_T_15104, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_15106 = and(_T_15105, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_15107 = and(_T_15106, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_15108 = and(_T_15107, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_15109 = and(_T_15108, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_15110 = and(_T_15109, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[22] <= _T_15110 @[RegMapper.scala 187:18] + node _T_15111 = and(_T_13838, _T_2334[22]) @[RegMapper.scala 184:66] + node _T_15112 = and(_T_15111, _T_2334[21]) @[RegMapper.scala 184:66] + node _T_15113 = and(_T_15112, _T_2334[20]) @[RegMapper.scala 184:66] + node _T_15114 = and(_T_15113, _T_2334[19]) @[RegMapper.scala 184:66] + node _T_15115 = and(_T_15114, _T_2334[18]) @[RegMapper.scala 184:66] + node _T_15116 = and(_T_15115, _T_2334[17]) @[RegMapper.scala 184:66] + node _T_15117 = and(_T_15116, _T_2334[16]) @[RegMapper.scala 184:66] + node _T_15118 = and(_T_15117, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[23] <= _T_15118 @[RegMapper.scala 184:18] + node _T_15119 = and(_T_13844, _T_2522[22]) @[RegMapper.scala 185:66] + node _T_15120 = and(_T_15119, _T_2522[21]) @[RegMapper.scala 185:66] + node _T_15121 = and(_T_15120, _T_2522[20]) @[RegMapper.scala 185:66] + node _T_15122 = and(_T_15121, _T_2522[19]) @[RegMapper.scala 185:66] + node _T_15123 = and(_T_15122, _T_2522[18]) @[RegMapper.scala 185:66] + node _T_15124 = and(_T_15123, _T_2522[17]) @[RegMapper.scala 185:66] + node _T_15125 = and(_T_15124, _T_2522[16]) @[RegMapper.scala 185:66] + node _T_15126 = and(_T_15125, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[23] <= _T_15126 @[RegMapper.scala 185:18] + node _T_15127 = and(_T_13848, _T_2710[22]) @[RegMapper.scala 186:66] + node _T_15128 = and(_T_15127, _T_2710[21]) @[RegMapper.scala 186:66] + node _T_15129 = and(_T_15128, _T_2710[20]) @[RegMapper.scala 186:66] + node _T_15130 = and(_T_15129, _T_2710[19]) @[RegMapper.scala 186:66] + node _T_15131 = and(_T_15130, _T_2710[18]) @[RegMapper.scala 186:66] + node _T_15132 = and(_T_15131, _T_2710[17]) @[RegMapper.scala 186:66] + node _T_15133 = and(_T_15132, _T_2710[16]) @[RegMapper.scala 186:66] + node _T_15134 = and(_T_15133, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[23] <= _T_15134 @[RegMapper.scala 186:18] + node _T_15135 = and(_T_13854, _T_2898[22]) @[RegMapper.scala 187:66] + node _T_15136 = and(_T_15135, _T_2898[21]) @[RegMapper.scala 187:66] + node _T_15137 = and(_T_15136, _T_2898[20]) @[RegMapper.scala 187:66] + node _T_15138 = and(_T_15137, _T_2898[19]) @[RegMapper.scala 187:66] + node _T_15139 = and(_T_15138, _T_2898[18]) @[RegMapper.scala 187:66] + node _T_15140 = and(_T_15139, _T_2898[17]) @[RegMapper.scala 187:66] + node _T_15141 = and(_T_15140, _T_2898[16]) @[RegMapper.scala 187:66] + node _T_15142 = and(_T_15141, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[23] <= _T_15142 @[RegMapper.scala 187:18] + node _T_15143 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15144 = and(_T_15143, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15145 = and(_T_15144, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15146 = and(_T_15145, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15147 = and(_T_15146, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15148 = and(_T_15147, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15149 = and(_T_15148, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15150 = and(_T_15149, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[24] <= _T_15150 @[RegMapper.scala 184:18] + node _T_15151 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15152 = and(_T_15151, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15153 = and(_T_15152, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15154 = and(_T_15153, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15155 = and(_T_15154, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15156 = and(_T_15155, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15157 = and(_T_15156, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15158 = and(_T_15157, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[24] <= _T_15158 @[RegMapper.scala 185:18] + node _T_15159 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15160 = and(_T_15159, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15161 = and(_T_15160, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15162 = and(_T_15161, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15163 = and(_T_15162, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15164 = and(_T_15163, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15165 = and(_T_15164, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15166 = and(_T_15165, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[24] <= _T_15166 @[RegMapper.scala 186:18] + node _T_15167 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15168 = and(_T_15167, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15169 = and(_T_15168, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15170 = and(_T_15169, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15171 = and(_T_15170, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15172 = and(_T_15171, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15173 = and(_T_15172, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15174 = and(_T_15173, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[24] <= _T_15174 @[RegMapper.scala 187:18] + node _T_15175 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15176 = and(_T_15175, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15177 = and(_T_15176, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15178 = and(_T_15177, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15179 = and(_T_15178, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15180 = and(_T_15179, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15181 = and(_T_15180, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15182 = and(_T_15181, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[25] <= _T_15182 @[RegMapper.scala 184:18] + node _T_15183 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15184 = and(_T_15183, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15185 = and(_T_15184, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15186 = and(_T_15185, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15187 = and(_T_15186, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15188 = and(_T_15187, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15189 = and(_T_15188, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15190 = and(_T_15189, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[25] <= _T_15190 @[RegMapper.scala 185:18] + node _T_15191 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15192 = and(_T_15191, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15193 = and(_T_15192, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15194 = and(_T_15193, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15195 = and(_T_15194, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15196 = and(_T_15195, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15197 = and(_T_15196, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15198 = and(_T_15197, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[25] <= _T_15198 @[RegMapper.scala 186:18] + node _T_15199 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15200 = and(_T_15199, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15201 = and(_T_15200, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15202 = and(_T_15201, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15203 = and(_T_15202, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15204 = and(_T_15203, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15205 = and(_T_15204, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15206 = and(_T_15205, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[25] <= _T_15206 @[RegMapper.scala 187:18] + node _T_15207 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15208 = and(_T_15207, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15209 = and(_T_15208, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15210 = and(_T_15209, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15211 = and(_T_15210, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15212 = and(_T_15211, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15213 = and(_T_15212, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15214 = and(_T_15213, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[26] <= _T_15214 @[RegMapper.scala 184:18] + node _T_15215 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15216 = and(_T_15215, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15217 = and(_T_15216, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15218 = and(_T_15217, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15219 = and(_T_15218, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15220 = and(_T_15219, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15221 = and(_T_15220, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15222 = and(_T_15221, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[26] <= _T_15222 @[RegMapper.scala 185:18] + node _T_15223 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15224 = and(_T_15223, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15225 = and(_T_15224, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15226 = and(_T_15225, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15227 = and(_T_15226, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15228 = and(_T_15227, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15229 = and(_T_15228, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15230 = and(_T_15229, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[26] <= _T_15230 @[RegMapper.scala 186:18] + node _T_15231 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15232 = and(_T_15231, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15233 = and(_T_15232, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15234 = and(_T_15233, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15235 = and(_T_15234, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15236 = and(_T_15235, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15237 = and(_T_15236, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15238 = and(_T_15237, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[26] <= _T_15238 @[RegMapper.scala 187:18] + node _T_15239 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15240 = and(_T_15239, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15241 = and(_T_15240, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15242 = and(_T_15241, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15243 = and(_T_15242, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15244 = and(_T_15243, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15245 = and(_T_15244, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15246 = and(_T_15245, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[27] <= _T_15246 @[RegMapper.scala 184:18] + node _T_15247 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15248 = and(_T_15247, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15249 = and(_T_15248, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15250 = and(_T_15249, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15251 = and(_T_15250, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15252 = and(_T_15251, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15253 = and(_T_15252, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15254 = and(_T_15253, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[27] <= _T_15254 @[RegMapper.scala 185:18] + node _T_15255 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15256 = and(_T_15255, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15257 = and(_T_15256, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15258 = and(_T_15257, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15259 = and(_T_15258, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15260 = and(_T_15259, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15261 = and(_T_15260, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15262 = and(_T_15261, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[27] <= _T_15262 @[RegMapper.scala 186:18] + node _T_15263 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15264 = and(_T_15263, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15265 = and(_T_15264, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15266 = and(_T_15265, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15267 = and(_T_15266, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15268 = and(_T_15267, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15269 = and(_T_15268, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15270 = and(_T_15269, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[27] <= _T_15270 @[RegMapper.scala 187:18] + node _T_15271 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15272 = and(_T_15271, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15273 = and(_T_15272, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15274 = and(_T_15273, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15275 = and(_T_15274, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15276 = and(_T_15275, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15277 = and(_T_15276, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15278 = and(_T_15277, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[28] <= _T_15278 @[RegMapper.scala 184:18] + node _T_15279 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15280 = and(_T_15279, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15281 = and(_T_15280, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15282 = and(_T_15281, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15283 = and(_T_15282, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15284 = and(_T_15283, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15285 = and(_T_15284, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15286 = and(_T_15285, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[28] <= _T_15286 @[RegMapper.scala 185:18] + node _T_15287 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15288 = and(_T_15287, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15289 = and(_T_15288, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15290 = and(_T_15289, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15291 = and(_T_15290, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15292 = and(_T_15291, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15293 = and(_T_15292, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15294 = and(_T_15293, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[28] <= _T_15294 @[RegMapper.scala 186:18] + node _T_15295 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15296 = and(_T_15295, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15297 = and(_T_15296, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15298 = and(_T_15297, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15299 = and(_T_15298, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15300 = and(_T_15299, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15301 = and(_T_15300, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15302 = and(_T_15301, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[28] <= _T_15302 @[RegMapper.scala 187:18] + node _T_15303 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15304 = and(_T_15303, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15305 = and(_T_15304, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15306 = and(_T_15305, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15307 = and(_T_15306, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15308 = and(_T_15307, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15309 = and(_T_15308, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15310 = and(_T_15309, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[29] <= _T_15310 @[RegMapper.scala 184:18] + node _T_15311 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15312 = and(_T_15311, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15313 = and(_T_15312, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15314 = and(_T_15313, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15315 = and(_T_15314, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15316 = and(_T_15315, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15317 = and(_T_15316, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15318 = and(_T_15317, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[29] <= _T_15318 @[RegMapper.scala 185:18] + node _T_15319 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15320 = and(_T_15319, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15321 = and(_T_15320, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15322 = and(_T_15321, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15323 = and(_T_15322, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15324 = and(_T_15323, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15325 = and(_T_15324, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15326 = and(_T_15325, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[29] <= _T_15326 @[RegMapper.scala 186:18] + node _T_15327 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15328 = and(_T_15327, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15329 = and(_T_15328, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15330 = and(_T_15329, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15331 = and(_T_15330, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15332 = and(_T_15331, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15333 = and(_T_15332, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15334 = and(_T_15333, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[29] <= _T_15334 @[RegMapper.scala 187:18] + node _T_15335 = and(_T_13178, _T_2334[31]) @[RegMapper.scala 184:66] + node _T_15336 = and(_T_15335, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15337 = and(_T_15336, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15338 = and(_T_15337, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15339 = and(_T_15338, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15340 = and(_T_15339, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15341 = and(_T_15340, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15342 = and(_T_15341, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[30] <= _T_15342 @[RegMapper.scala 184:18] + node _T_15343 = and(_T_13184, _T_2522[31]) @[RegMapper.scala 185:66] + node _T_15344 = and(_T_15343, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15345 = and(_T_15344, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15346 = and(_T_15345, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15347 = and(_T_15346, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15348 = and(_T_15347, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15349 = and(_T_15348, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15350 = and(_T_15349, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[30] <= _T_15350 @[RegMapper.scala 185:18] + node _T_15351 = and(_T_13188, _T_2710[31]) @[RegMapper.scala 186:66] + node _T_15352 = and(_T_15351, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15353 = and(_T_15352, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15354 = and(_T_15353, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15355 = and(_T_15354, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15356 = and(_T_15355, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15357 = and(_T_15356, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15358 = and(_T_15357, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[30] <= _T_15358 @[RegMapper.scala 186:18] + node _T_15359 = and(_T_13194, _T_2898[31]) @[RegMapper.scala 187:66] + node _T_15360 = and(_T_15359, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15361 = and(_T_15360, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15362 = and(_T_15361, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15363 = and(_T_15362, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15364 = and(_T_15363, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15365 = and(_T_15364, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15366 = and(_T_15365, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[30] <= _T_15366 @[RegMapper.scala 187:18] + node _T_15367 = and(_T_13178, _T_2334[30]) @[RegMapper.scala 184:66] + node _T_15368 = and(_T_15367, _T_2334[29]) @[RegMapper.scala 184:66] + node _T_15369 = and(_T_15368, _T_2334[28]) @[RegMapper.scala 184:66] + node _T_15370 = and(_T_15369, _T_2334[27]) @[RegMapper.scala 184:66] + node _T_15371 = and(_T_15370, _T_2334[26]) @[RegMapper.scala 184:66] + node _T_15372 = and(_T_15371, _T_2334[25]) @[RegMapper.scala 184:66] + node _T_15373 = and(_T_15372, _T_2334[24]) @[RegMapper.scala 184:66] + node _T_15374 = and(_T_15373, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[31] <= _T_15374 @[RegMapper.scala 184:18] + node _T_15375 = and(_T_13184, _T_2522[30]) @[RegMapper.scala 185:66] + node _T_15376 = and(_T_15375, _T_2522[29]) @[RegMapper.scala 185:66] + node _T_15377 = and(_T_15376, _T_2522[28]) @[RegMapper.scala 185:66] + node _T_15378 = and(_T_15377, _T_2522[27]) @[RegMapper.scala 185:66] + node _T_15379 = and(_T_15378, _T_2522[26]) @[RegMapper.scala 185:66] + node _T_15380 = and(_T_15379, _T_2522[25]) @[RegMapper.scala 185:66] + node _T_15381 = and(_T_15380, _T_2522[24]) @[RegMapper.scala 185:66] + node _T_15382 = and(_T_15381, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[31] <= _T_15382 @[RegMapper.scala 185:18] + node _T_15383 = and(_T_13188, _T_2710[30]) @[RegMapper.scala 186:66] + node _T_15384 = and(_T_15383, _T_2710[29]) @[RegMapper.scala 186:66] + node _T_15385 = and(_T_15384, _T_2710[28]) @[RegMapper.scala 186:66] + node _T_15386 = and(_T_15385, _T_2710[27]) @[RegMapper.scala 186:66] + node _T_15387 = and(_T_15386, _T_2710[26]) @[RegMapper.scala 186:66] + node _T_15388 = and(_T_15387, _T_2710[25]) @[RegMapper.scala 186:66] + node _T_15389 = and(_T_15388, _T_2710[24]) @[RegMapper.scala 186:66] + node _T_15390 = and(_T_15389, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[31] <= _T_15390 @[RegMapper.scala 186:18] + node _T_15391 = and(_T_13194, _T_2898[30]) @[RegMapper.scala 187:66] + node _T_15392 = and(_T_15391, _T_2898[29]) @[RegMapper.scala 187:66] + node _T_15393 = and(_T_15392, _T_2898[28]) @[RegMapper.scala 187:66] + node _T_15394 = and(_T_15393, _T_2898[27]) @[RegMapper.scala 187:66] + node _T_15395 = and(_T_15394, _T_2898[26]) @[RegMapper.scala 187:66] + node _T_15396 = and(_T_15395, _T_2898[25]) @[RegMapper.scala 187:66] + node _T_15397 = and(_T_15396, _T_2898[24]) @[RegMapper.scala 187:66] + node _T_15398 = and(_T_15397, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[31] <= _T_15398 @[RegMapper.scala 187:18] + node _T_15399 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15400 = and(_T_15399, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15401 = and(_T_15400, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15402 = and(_T_15401, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15403 = and(_T_15402, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15404 = and(_T_15403, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15405 = and(_T_15404, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15406 = and(_T_15405, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[32] <= _T_15406 @[RegMapper.scala 184:18] + node _T_15407 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15408 = and(_T_15407, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15409 = and(_T_15408, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15410 = and(_T_15409, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15411 = and(_T_15410, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15412 = and(_T_15411, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15413 = and(_T_15412, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15414 = and(_T_15413, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[32] <= _T_15414 @[RegMapper.scala 185:18] + node _T_15415 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15416 = and(_T_15415, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15417 = and(_T_15416, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15418 = and(_T_15417, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15419 = and(_T_15418, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15420 = and(_T_15419, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15421 = and(_T_15420, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15422 = and(_T_15421, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[32] <= _T_15422 @[RegMapper.scala 186:18] + node _T_15423 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15424 = and(_T_15423, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15425 = and(_T_15424, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15426 = and(_T_15425, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15427 = and(_T_15426, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15428 = and(_T_15427, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15429 = and(_T_15428, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15430 = and(_T_15429, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[32] <= _T_15430 @[RegMapper.scala 187:18] + node _T_15431 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15432 = and(_T_15431, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15433 = and(_T_15432, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15434 = and(_T_15433, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15435 = and(_T_15434, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15436 = and(_T_15435, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15437 = and(_T_15436, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15438 = and(_T_15437, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[33] <= _T_15438 @[RegMapper.scala 184:18] + node _T_15439 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15440 = and(_T_15439, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15441 = and(_T_15440, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15442 = and(_T_15441, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15443 = and(_T_15442, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15444 = and(_T_15443, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15445 = and(_T_15444, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15446 = and(_T_15445, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[33] <= _T_15446 @[RegMapper.scala 185:18] + node _T_15447 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15448 = and(_T_15447, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15449 = and(_T_15448, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15450 = and(_T_15449, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15451 = and(_T_15450, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15452 = and(_T_15451, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15453 = and(_T_15452, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15454 = and(_T_15453, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[33] <= _T_15454 @[RegMapper.scala 186:18] + node _T_15455 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15456 = and(_T_15455, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15457 = and(_T_15456, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15458 = and(_T_15457, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15459 = and(_T_15458, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15460 = and(_T_15459, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15461 = and(_T_15460, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15462 = and(_T_15461, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[33] <= _T_15462 @[RegMapper.scala 187:18] + node _T_15463 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15464 = and(_T_15463, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15465 = and(_T_15464, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15466 = and(_T_15465, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15467 = and(_T_15466, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15468 = and(_T_15467, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15469 = and(_T_15468, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15470 = and(_T_15469, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[34] <= _T_15470 @[RegMapper.scala 184:18] + node _T_15471 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15472 = and(_T_15471, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15473 = and(_T_15472, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15474 = and(_T_15473, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15475 = and(_T_15474, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15476 = and(_T_15475, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15477 = and(_T_15476, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15478 = and(_T_15477, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[34] <= _T_15478 @[RegMapper.scala 185:18] + node _T_15479 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15480 = and(_T_15479, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15481 = and(_T_15480, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15482 = and(_T_15481, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15483 = and(_T_15482, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15484 = and(_T_15483, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15485 = and(_T_15484, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15486 = and(_T_15485, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[34] <= _T_15486 @[RegMapper.scala 186:18] + node _T_15487 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15488 = and(_T_15487, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15489 = and(_T_15488, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15490 = and(_T_15489, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15491 = and(_T_15490, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15492 = and(_T_15491, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15493 = and(_T_15492, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15494 = and(_T_15493, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[34] <= _T_15494 @[RegMapper.scala 187:18] + node _T_15495 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15496 = and(_T_15495, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15497 = and(_T_15496, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15498 = and(_T_15497, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15499 = and(_T_15498, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15500 = and(_T_15499, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15501 = and(_T_15500, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15502 = and(_T_15501, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[35] <= _T_15502 @[RegMapper.scala 184:18] + node _T_15503 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15504 = and(_T_15503, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15505 = and(_T_15504, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15506 = and(_T_15505, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15507 = and(_T_15506, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15508 = and(_T_15507, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15509 = and(_T_15508, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15510 = and(_T_15509, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[35] <= _T_15510 @[RegMapper.scala 185:18] + node _T_15511 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15512 = and(_T_15511, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15513 = and(_T_15512, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15514 = and(_T_15513, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15515 = and(_T_15514, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15516 = and(_T_15515, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15517 = and(_T_15516, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15518 = and(_T_15517, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[35] <= _T_15518 @[RegMapper.scala 186:18] + node _T_15519 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15520 = and(_T_15519, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15521 = and(_T_15520, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15522 = and(_T_15521, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15523 = and(_T_15522, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15524 = and(_T_15523, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15525 = and(_T_15524, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15526 = and(_T_15525, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[35] <= _T_15526 @[RegMapper.scala 187:18] + node _T_15527 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15528 = and(_T_15527, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15529 = and(_T_15528, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15530 = and(_T_15529, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15531 = and(_T_15530, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15532 = and(_T_15531, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15533 = and(_T_15532, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15534 = and(_T_15533, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[36] <= _T_15534 @[RegMapper.scala 184:18] + node _T_15535 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15536 = and(_T_15535, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15537 = and(_T_15536, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15538 = and(_T_15537, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15539 = and(_T_15538, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15540 = and(_T_15539, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15541 = and(_T_15540, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15542 = and(_T_15541, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[36] <= _T_15542 @[RegMapper.scala 185:18] + node _T_15543 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15544 = and(_T_15543, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15545 = and(_T_15544, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15546 = and(_T_15545, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15547 = and(_T_15546, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15548 = and(_T_15547, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15549 = and(_T_15548, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15550 = and(_T_15549, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[36] <= _T_15550 @[RegMapper.scala 186:18] + node _T_15551 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15552 = and(_T_15551, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15553 = and(_T_15552, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15554 = and(_T_15553, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15555 = and(_T_15554, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15556 = and(_T_15555, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15557 = and(_T_15556, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15558 = and(_T_15557, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[36] <= _T_15558 @[RegMapper.scala 187:18] + node _T_15559 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15560 = and(_T_15559, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15561 = and(_T_15560, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15562 = and(_T_15561, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15563 = and(_T_15562, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15564 = and(_T_15563, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15565 = and(_T_15564, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15566 = and(_T_15565, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[37] <= _T_15566 @[RegMapper.scala 184:18] + node _T_15567 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15568 = and(_T_15567, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15569 = and(_T_15568, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15570 = and(_T_15569, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15571 = and(_T_15570, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15572 = and(_T_15571, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15573 = and(_T_15572, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15574 = and(_T_15573, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[37] <= _T_15574 @[RegMapper.scala 185:18] + node _T_15575 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15576 = and(_T_15575, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15577 = and(_T_15576, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15578 = and(_T_15577, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15579 = and(_T_15578, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15580 = and(_T_15579, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15581 = and(_T_15580, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15582 = and(_T_15581, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[37] <= _T_15582 @[RegMapper.scala 186:18] + node _T_15583 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15584 = and(_T_15583, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15585 = and(_T_15584, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15586 = and(_T_15585, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15587 = and(_T_15586, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15588 = and(_T_15587, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15589 = and(_T_15588, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15590 = and(_T_15589, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[37] <= _T_15590 @[RegMapper.scala 187:18] + node _T_15591 = and(_T_13198, _T_2334[39]) @[RegMapper.scala 184:66] + node _T_15592 = and(_T_15591, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15593 = and(_T_15592, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15594 = and(_T_15593, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15595 = and(_T_15594, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15596 = and(_T_15595, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15597 = and(_T_15596, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15598 = and(_T_15597, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[38] <= _T_15598 @[RegMapper.scala 184:18] + node _T_15599 = and(_T_13204, _T_2522[39]) @[RegMapper.scala 185:66] + node _T_15600 = and(_T_15599, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15601 = and(_T_15600, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15602 = and(_T_15601, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15603 = and(_T_15602, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15604 = and(_T_15603, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15605 = and(_T_15604, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15606 = and(_T_15605, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[38] <= _T_15606 @[RegMapper.scala 185:18] + node _T_15607 = and(_T_13208, _T_2710[39]) @[RegMapper.scala 186:66] + node _T_15608 = and(_T_15607, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15609 = and(_T_15608, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15610 = and(_T_15609, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15611 = and(_T_15610, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15612 = and(_T_15611, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15613 = and(_T_15612, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15614 = and(_T_15613, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[38] <= _T_15614 @[RegMapper.scala 186:18] + node _T_15615 = and(_T_13214, _T_2898[39]) @[RegMapper.scala 187:66] + node _T_15616 = and(_T_15615, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15617 = and(_T_15616, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15618 = and(_T_15617, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15619 = and(_T_15618, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15620 = and(_T_15619, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15621 = and(_T_15620, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15622 = and(_T_15621, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[38] <= _T_15622 @[RegMapper.scala 187:18] + node _T_15623 = and(_T_13198, _T_2334[38]) @[RegMapper.scala 184:66] + node _T_15624 = and(_T_15623, _T_2334[37]) @[RegMapper.scala 184:66] + node _T_15625 = and(_T_15624, _T_2334[36]) @[RegMapper.scala 184:66] + node _T_15626 = and(_T_15625, _T_2334[35]) @[RegMapper.scala 184:66] + node _T_15627 = and(_T_15626, _T_2334[34]) @[RegMapper.scala 184:66] + node _T_15628 = and(_T_15627, _T_2334[33]) @[RegMapper.scala 184:66] + node _T_15629 = and(_T_15628, _T_2334[32]) @[RegMapper.scala 184:66] + node _T_15630 = and(_T_15629, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[39] <= _T_15630 @[RegMapper.scala 184:18] + node _T_15631 = and(_T_13204, _T_2522[38]) @[RegMapper.scala 185:66] + node _T_15632 = and(_T_15631, _T_2522[37]) @[RegMapper.scala 185:66] + node _T_15633 = and(_T_15632, _T_2522[36]) @[RegMapper.scala 185:66] + node _T_15634 = and(_T_15633, _T_2522[35]) @[RegMapper.scala 185:66] + node _T_15635 = and(_T_15634, _T_2522[34]) @[RegMapper.scala 185:66] + node _T_15636 = and(_T_15635, _T_2522[33]) @[RegMapper.scala 185:66] + node _T_15637 = and(_T_15636, _T_2522[32]) @[RegMapper.scala 185:66] + node _T_15638 = and(_T_15637, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[39] <= _T_15638 @[RegMapper.scala 185:18] + node _T_15639 = and(_T_13208, _T_2710[38]) @[RegMapper.scala 186:66] + node _T_15640 = and(_T_15639, _T_2710[37]) @[RegMapper.scala 186:66] + node _T_15641 = and(_T_15640, _T_2710[36]) @[RegMapper.scala 186:66] + node _T_15642 = and(_T_15641, _T_2710[35]) @[RegMapper.scala 186:66] + node _T_15643 = and(_T_15642, _T_2710[34]) @[RegMapper.scala 186:66] + node _T_15644 = and(_T_15643, _T_2710[33]) @[RegMapper.scala 186:66] + node _T_15645 = and(_T_15644, _T_2710[32]) @[RegMapper.scala 186:66] + node _T_15646 = and(_T_15645, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[39] <= _T_15646 @[RegMapper.scala 186:18] + node _T_15647 = and(_T_13214, _T_2898[38]) @[RegMapper.scala 187:66] + node _T_15648 = and(_T_15647, _T_2898[37]) @[RegMapper.scala 187:66] + node _T_15649 = and(_T_15648, _T_2898[36]) @[RegMapper.scala 187:66] + node _T_15650 = and(_T_15649, _T_2898[35]) @[RegMapper.scala 187:66] + node _T_15651 = and(_T_15650, _T_2898[34]) @[RegMapper.scala 187:66] + node _T_15652 = and(_T_15651, _T_2898[33]) @[RegMapper.scala 187:66] + node _T_15653 = and(_T_15652, _T_2898[32]) @[RegMapper.scala 187:66] + node _T_15654 = and(_T_15653, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[39] <= _T_15654 @[RegMapper.scala 187:18] + node _T_15655 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15656 = and(_T_15655, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15657 = and(_T_15656, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15658 = and(_T_15657, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15659 = and(_T_15658, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15660 = and(_T_15659, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15661 = and(_T_15660, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15662 = and(_T_15661, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[40] <= _T_15662 @[RegMapper.scala 184:18] + node _T_15663 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15664 = and(_T_15663, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15665 = and(_T_15664, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15666 = and(_T_15665, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15667 = and(_T_15666, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15668 = and(_T_15667, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15669 = and(_T_15668, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15670 = and(_T_15669, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[40] <= _T_15670 @[RegMapper.scala 185:18] + node _T_15671 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15672 = and(_T_15671, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15673 = and(_T_15672, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15674 = and(_T_15673, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15675 = and(_T_15674, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15676 = and(_T_15675, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15677 = and(_T_15676, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15678 = and(_T_15677, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[40] <= _T_15678 @[RegMapper.scala 186:18] + node _T_15679 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15680 = and(_T_15679, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15681 = and(_T_15680, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15682 = and(_T_15681, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15683 = and(_T_15682, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15684 = and(_T_15683, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15685 = and(_T_15684, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15686 = and(_T_15685, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[40] <= _T_15686 @[RegMapper.scala 187:18] + node _T_15687 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15688 = and(_T_15687, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15689 = and(_T_15688, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15690 = and(_T_15689, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15691 = and(_T_15690, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15692 = and(_T_15691, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15693 = and(_T_15692, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15694 = and(_T_15693, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[41] <= _T_15694 @[RegMapper.scala 184:18] + node _T_15695 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15696 = and(_T_15695, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15697 = and(_T_15696, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15698 = and(_T_15697, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15699 = and(_T_15698, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15700 = and(_T_15699, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15701 = and(_T_15700, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15702 = and(_T_15701, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[41] <= _T_15702 @[RegMapper.scala 185:18] + node _T_15703 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15704 = and(_T_15703, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15705 = and(_T_15704, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15706 = and(_T_15705, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15707 = and(_T_15706, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15708 = and(_T_15707, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15709 = and(_T_15708, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15710 = and(_T_15709, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[41] <= _T_15710 @[RegMapper.scala 186:18] + node _T_15711 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15712 = and(_T_15711, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15713 = and(_T_15712, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15714 = and(_T_15713, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15715 = and(_T_15714, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15716 = and(_T_15715, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15717 = and(_T_15716, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15718 = and(_T_15717, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[41] <= _T_15718 @[RegMapper.scala 187:18] + node _T_15719 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15720 = and(_T_15719, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15721 = and(_T_15720, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15722 = and(_T_15721, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15723 = and(_T_15722, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15724 = and(_T_15723, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15725 = and(_T_15724, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15726 = and(_T_15725, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[42] <= _T_15726 @[RegMapper.scala 184:18] + node _T_15727 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15728 = and(_T_15727, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15729 = and(_T_15728, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15730 = and(_T_15729, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15731 = and(_T_15730, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15732 = and(_T_15731, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15733 = and(_T_15732, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15734 = and(_T_15733, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[42] <= _T_15734 @[RegMapper.scala 185:18] + node _T_15735 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15736 = and(_T_15735, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15737 = and(_T_15736, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15738 = and(_T_15737, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15739 = and(_T_15738, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15740 = and(_T_15739, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15741 = and(_T_15740, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15742 = and(_T_15741, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[42] <= _T_15742 @[RegMapper.scala 186:18] + node _T_15743 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15744 = and(_T_15743, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15745 = and(_T_15744, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15746 = and(_T_15745, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15747 = and(_T_15746, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15748 = and(_T_15747, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15749 = and(_T_15748, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15750 = and(_T_15749, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[42] <= _T_15750 @[RegMapper.scala 187:18] + node _T_15751 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15752 = and(_T_15751, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15753 = and(_T_15752, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15754 = and(_T_15753, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15755 = and(_T_15754, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15756 = and(_T_15755, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15757 = and(_T_15756, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15758 = and(_T_15757, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[43] <= _T_15758 @[RegMapper.scala 184:18] + node _T_15759 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15760 = and(_T_15759, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15761 = and(_T_15760, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15762 = and(_T_15761, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15763 = and(_T_15762, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15764 = and(_T_15763, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15765 = and(_T_15764, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15766 = and(_T_15765, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[43] <= _T_15766 @[RegMapper.scala 185:18] + node _T_15767 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15768 = and(_T_15767, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15769 = and(_T_15768, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15770 = and(_T_15769, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15771 = and(_T_15770, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15772 = and(_T_15771, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15773 = and(_T_15772, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15774 = and(_T_15773, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[43] <= _T_15774 @[RegMapper.scala 186:18] + node _T_15775 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15776 = and(_T_15775, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15777 = and(_T_15776, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15778 = and(_T_15777, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15779 = and(_T_15778, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15780 = and(_T_15779, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15781 = and(_T_15780, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15782 = and(_T_15781, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[43] <= _T_15782 @[RegMapper.scala 187:18] + node _T_15783 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15784 = and(_T_15783, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15785 = and(_T_15784, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15786 = and(_T_15785, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15787 = and(_T_15786, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15788 = and(_T_15787, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15789 = and(_T_15788, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15790 = and(_T_15789, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[44] <= _T_15790 @[RegMapper.scala 184:18] + node _T_15791 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15792 = and(_T_15791, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15793 = and(_T_15792, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15794 = and(_T_15793, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15795 = and(_T_15794, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15796 = and(_T_15795, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15797 = and(_T_15796, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15798 = and(_T_15797, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[44] <= _T_15798 @[RegMapper.scala 185:18] + node _T_15799 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15800 = and(_T_15799, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15801 = and(_T_15800, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15802 = and(_T_15801, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15803 = and(_T_15802, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15804 = and(_T_15803, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15805 = and(_T_15804, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15806 = and(_T_15805, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[44] <= _T_15806 @[RegMapper.scala 186:18] + node _T_15807 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15808 = and(_T_15807, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15809 = and(_T_15808, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15810 = and(_T_15809, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15811 = and(_T_15810, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15812 = and(_T_15811, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15813 = and(_T_15812, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15814 = and(_T_15813, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[44] <= _T_15814 @[RegMapper.scala 187:18] + node _T_15815 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15816 = and(_T_15815, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15817 = and(_T_15816, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15818 = and(_T_15817, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15819 = and(_T_15818, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15820 = and(_T_15819, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15821 = and(_T_15820, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15822 = and(_T_15821, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[45] <= _T_15822 @[RegMapper.scala 184:18] + node _T_15823 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15824 = and(_T_15823, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15825 = and(_T_15824, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15826 = and(_T_15825, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15827 = and(_T_15826, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15828 = and(_T_15827, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15829 = and(_T_15828, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15830 = and(_T_15829, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[45] <= _T_15830 @[RegMapper.scala 185:18] + node _T_15831 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15832 = and(_T_15831, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15833 = and(_T_15832, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15834 = and(_T_15833, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15835 = and(_T_15834, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15836 = and(_T_15835, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15837 = and(_T_15836, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15838 = and(_T_15837, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[45] <= _T_15838 @[RegMapper.scala 186:18] + node _T_15839 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15840 = and(_T_15839, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15841 = and(_T_15840, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15842 = and(_T_15841, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15843 = and(_T_15842, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15844 = and(_T_15843, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15845 = and(_T_15844, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15846 = and(_T_15845, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[45] <= _T_15846 @[RegMapper.scala 187:18] + node _T_15847 = and(_T_13918, _T_2334[47]) @[RegMapper.scala 184:66] + node _T_15848 = and(_T_15847, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15849 = and(_T_15848, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15850 = and(_T_15849, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15851 = and(_T_15850, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15852 = and(_T_15851, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15853 = and(_T_15852, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15854 = and(_T_15853, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[46] <= _T_15854 @[RegMapper.scala 184:18] + node _T_15855 = and(_T_13924, _T_2522[47]) @[RegMapper.scala 185:66] + node _T_15856 = and(_T_15855, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15857 = and(_T_15856, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15858 = and(_T_15857, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15859 = and(_T_15858, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15860 = and(_T_15859, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15861 = and(_T_15860, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15862 = and(_T_15861, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[46] <= _T_15862 @[RegMapper.scala 185:18] + node _T_15863 = and(_T_13928, _T_2710[47]) @[RegMapper.scala 186:66] + node _T_15864 = and(_T_15863, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15865 = and(_T_15864, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15866 = and(_T_15865, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15867 = and(_T_15866, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15868 = and(_T_15867, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15869 = and(_T_15868, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15870 = and(_T_15869, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[46] <= _T_15870 @[RegMapper.scala 186:18] + node _T_15871 = and(_T_13934, _T_2898[47]) @[RegMapper.scala 187:66] + node _T_15872 = and(_T_15871, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15873 = and(_T_15872, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15874 = and(_T_15873, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15875 = and(_T_15874, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15876 = and(_T_15875, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15877 = and(_T_15876, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15878 = and(_T_15877, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[46] <= _T_15878 @[RegMapper.scala 187:18] + node _T_15879 = and(_T_13918, _T_2334[46]) @[RegMapper.scala 184:66] + node _T_15880 = and(_T_15879, _T_2334[45]) @[RegMapper.scala 184:66] + node _T_15881 = and(_T_15880, _T_2334[44]) @[RegMapper.scala 184:66] + node _T_15882 = and(_T_15881, _T_2334[43]) @[RegMapper.scala 184:66] + node _T_15883 = and(_T_15882, _T_2334[42]) @[RegMapper.scala 184:66] + node _T_15884 = and(_T_15883, _T_2334[41]) @[RegMapper.scala 184:66] + node _T_15885 = and(_T_15884, _T_2334[40]) @[RegMapper.scala 184:66] + node _T_15886 = and(_T_15885, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[47] <= _T_15886 @[RegMapper.scala 184:18] + node _T_15887 = and(_T_13924, _T_2522[46]) @[RegMapper.scala 185:66] + node _T_15888 = and(_T_15887, _T_2522[45]) @[RegMapper.scala 185:66] + node _T_15889 = and(_T_15888, _T_2522[44]) @[RegMapper.scala 185:66] + node _T_15890 = and(_T_15889, _T_2522[43]) @[RegMapper.scala 185:66] + node _T_15891 = and(_T_15890, _T_2522[42]) @[RegMapper.scala 185:66] + node _T_15892 = and(_T_15891, _T_2522[41]) @[RegMapper.scala 185:66] + node _T_15893 = and(_T_15892, _T_2522[40]) @[RegMapper.scala 185:66] + node _T_15894 = and(_T_15893, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[47] <= _T_15894 @[RegMapper.scala 185:18] + node _T_15895 = and(_T_13928, _T_2710[46]) @[RegMapper.scala 186:66] + node _T_15896 = and(_T_15895, _T_2710[45]) @[RegMapper.scala 186:66] + node _T_15897 = and(_T_15896, _T_2710[44]) @[RegMapper.scala 186:66] + node _T_15898 = and(_T_15897, _T_2710[43]) @[RegMapper.scala 186:66] + node _T_15899 = and(_T_15898, _T_2710[42]) @[RegMapper.scala 186:66] + node _T_15900 = and(_T_15899, _T_2710[41]) @[RegMapper.scala 186:66] + node _T_15901 = and(_T_15900, _T_2710[40]) @[RegMapper.scala 186:66] + node _T_15902 = and(_T_15901, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[47] <= _T_15902 @[RegMapper.scala 186:18] + node _T_15903 = and(_T_13934, _T_2898[46]) @[RegMapper.scala 187:66] + node _T_15904 = and(_T_15903, _T_2898[45]) @[RegMapper.scala 187:66] + node _T_15905 = and(_T_15904, _T_2898[44]) @[RegMapper.scala 187:66] + node _T_15906 = and(_T_15905, _T_2898[43]) @[RegMapper.scala 187:66] + node _T_15907 = and(_T_15906, _T_2898[42]) @[RegMapper.scala 187:66] + node _T_15908 = and(_T_15907, _T_2898[41]) @[RegMapper.scala 187:66] + node _T_15909 = and(_T_15908, _T_2898[40]) @[RegMapper.scala 187:66] + node _T_15910 = and(_T_15909, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[47] <= _T_15910 @[RegMapper.scala 187:18] + node _T_15911 = and(_T_14018, _T_2334[51]) @[RegMapper.scala 184:66] + node _T_15912 = and(_T_15911, _T_2334[50]) @[RegMapper.scala 184:66] + node _T_15913 = and(_T_15912, _T_2334[49]) @[RegMapper.scala 184:66] + node _T_15914 = and(_T_15913, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[48] <= _T_15914 @[RegMapper.scala 184:18] + node _T_15915 = and(_T_14024, _T_2522[51]) @[RegMapper.scala 185:66] + node _T_15916 = and(_T_15915, _T_2522[50]) @[RegMapper.scala 185:66] + node _T_15917 = and(_T_15916, _T_2522[49]) @[RegMapper.scala 185:66] + node _T_15918 = and(_T_15917, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[48] <= _T_15918 @[RegMapper.scala 185:18] + node _T_15919 = and(_T_14028, _T_2710[51]) @[RegMapper.scala 186:66] + node _T_15920 = and(_T_15919, _T_2710[50]) @[RegMapper.scala 186:66] + node _T_15921 = and(_T_15920, _T_2710[49]) @[RegMapper.scala 186:66] + node _T_15922 = and(_T_15921, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[48] <= _T_15922 @[RegMapper.scala 186:18] + node _T_15923 = and(_T_14034, _T_2898[51]) @[RegMapper.scala 187:66] + node _T_15924 = and(_T_15923, _T_2898[50]) @[RegMapper.scala 187:66] + node _T_15925 = and(_T_15924, _T_2898[49]) @[RegMapper.scala 187:66] + node _T_15926 = and(_T_15925, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[48] <= _T_15926 @[RegMapper.scala 187:18] + node _T_15927 = and(_T_14018, _T_2334[51]) @[RegMapper.scala 184:66] + node _T_15928 = and(_T_15927, _T_2334[50]) @[RegMapper.scala 184:66] + node _T_15929 = and(_T_15928, _T_2334[48]) @[RegMapper.scala 184:66] + node _T_15930 = and(_T_15929, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[49] <= _T_15930 @[RegMapper.scala 184:18] + node _T_15931 = and(_T_14024, _T_2522[51]) @[RegMapper.scala 185:66] + node _T_15932 = and(_T_15931, _T_2522[50]) @[RegMapper.scala 185:66] + node _T_15933 = and(_T_15932, _T_2522[48]) @[RegMapper.scala 185:66] + node _T_15934 = and(_T_15933, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[49] <= _T_15934 @[RegMapper.scala 185:18] + node _T_15935 = and(_T_14028, _T_2710[51]) @[RegMapper.scala 186:66] + node _T_15936 = and(_T_15935, _T_2710[50]) @[RegMapper.scala 186:66] + node _T_15937 = and(_T_15936, _T_2710[48]) @[RegMapper.scala 186:66] + node _T_15938 = and(_T_15937, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[49] <= _T_15938 @[RegMapper.scala 186:18] + node _T_15939 = and(_T_14034, _T_2898[51]) @[RegMapper.scala 187:66] + node _T_15940 = and(_T_15939, _T_2898[50]) @[RegMapper.scala 187:66] + node _T_15941 = and(_T_15940, _T_2898[48]) @[RegMapper.scala 187:66] + node _T_15942 = and(_T_15941, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[49] <= _T_15942 @[RegMapper.scala 187:18] + node _T_15943 = and(_T_14018, _T_2334[51]) @[RegMapper.scala 184:66] + node _T_15944 = and(_T_15943, _T_2334[49]) @[RegMapper.scala 184:66] + node _T_15945 = and(_T_15944, _T_2334[48]) @[RegMapper.scala 184:66] + node _T_15946 = and(_T_15945, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[50] <= _T_15946 @[RegMapper.scala 184:18] + node _T_15947 = and(_T_14024, _T_2522[51]) @[RegMapper.scala 185:66] + node _T_15948 = and(_T_15947, _T_2522[49]) @[RegMapper.scala 185:66] + node _T_15949 = and(_T_15948, _T_2522[48]) @[RegMapper.scala 185:66] + node _T_15950 = and(_T_15949, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[50] <= _T_15950 @[RegMapper.scala 185:18] + node _T_15951 = and(_T_14028, _T_2710[51]) @[RegMapper.scala 186:66] + node _T_15952 = and(_T_15951, _T_2710[49]) @[RegMapper.scala 186:66] + node _T_15953 = and(_T_15952, _T_2710[48]) @[RegMapper.scala 186:66] + node _T_15954 = and(_T_15953, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[50] <= _T_15954 @[RegMapper.scala 186:18] + node _T_15955 = and(_T_14034, _T_2898[51]) @[RegMapper.scala 187:66] + node _T_15956 = and(_T_15955, _T_2898[49]) @[RegMapper.scala 187:66] + node _T_15957 = and(_T_15956, _T_2898[48]) @[RegMapper.scala 187:66] + node _T_15958 = and(_T_15957, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[50] <= _T_15958 @[RegMapper.scala 187:18] + node _T_15959 = and(_T_14018, _T_2334[50]) @[RegMapper.scala 184:66] + node _T_15960 = and(_T_15959, _T_2334[49]) @[RegMapper.scala 184:66] + node _T_15961 = and(_T_15960, _T_2334[48]) @[RegMapper.scala 184:66] + node _T_15962 = and(_T_15961, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[51] <= _T_15962 @[RegMapper.scala 184:18] + node _T_15963 = and(_T_14024, _T_2522[50]) @[RegMapper.scala 185:66] + node _T_15964 = and(_T_15963, _T_2522[49]) @[RegMapper.scala 185:66] + node _T_15965 = and(_T_15964, _T_2522[48]) @[RegMapper.scala 185:66] + node _T_15966 = and(_T_15965, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[51] <= _T_15966 @[RegMapper.scala 185:18] + node _T_15967 = and(_T_14028, _T_2710[50]) @[RegMapper.scala 186:66] + node _T_15968 = and(_T_15967, _T_2710[49]) @[RegMapper.scala 186:66] + node _T_15969 = and(_T_15968, _T_2710[48]) @[RegMapper.scala 186:66] + node _T_15970 = and(_T_15969, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[51] <= _T_15970 @[RegMapper.scala 186:18] + node _T_15971 = and(_T_14034, _T_2898[50]) @[RegMapper.scala 187:66] + node _T_15972 = and(_T_15971, _T_2898[49]) @[RegMapper.scala 187:66] + node _T_15973 = and(_T_15972, _T_2898[48]) @[RegMapper.scala 187:66] + node _T_15974 = and(_T_15973, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[51] <= _T_15974 @[RegMapper.scala 187:18] + node _T_15975 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_15976 = and(_T_15975, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_15977 = and(_T_15976, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_15978 = and(_T_15977, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_15979 = and(_T_15978, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_15980 = and(_T_15979, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_15981 = and(_T_15980, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_15982 = and(_T_15981, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[52] <= _T_15982 @[RegMapper.scala 184:18] + node _T_15983 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_15984 = and(_T_15983, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_15985 = and(_T_15984, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_15986 = and(_T_15985, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_15987 = and(_T_15986, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_15988 = and(_T_15987, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_15989 = and(_T_15988, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_15990 = and(_T_15989, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[52] <= _T_15990 @[RegMapper.scala 185:18] + node _T_15991 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_15992 = and(_T_15991, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_15993 = and(_T_15992, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_15994 = and(_T_15993, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_15995 = and(_T_15994, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_15996 = and(_T_15995, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_15997 = and(_T_15996, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_15998 = and(_T_15997, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[52] <= _T_15998 @[RegMapper.scala 186:18] + node _T_15999 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16000 = and(_T_15999, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16001 = and(_T_16000, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16002 = and(_T_16001, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16003 = and(_T_16002, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16004 = and(_T_16003, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16005 = and(_T_16004, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16006 = and(_T_16005, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[52] <= _T_16006 @[RegMapper.scala 187:18] + node _T_16007 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16008 = and(_T_16007, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16009 = and(_T_16008, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16010 = and(_T_16009, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16011 = and(_T_16010, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16012 = and(_T_16011, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16013 = and(_T_16012, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16014 = and(_T_16013, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[53] <= _T_16014 @[RegMapper.scala 184:18] + node _T_16015 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16016 = and(_T_16015, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16017 = and(_T_16016, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16018 = and(_T_16017, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16019 = and(_T_16018, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16020 = and(_T_16019, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16021 = and(_T_16020, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16022 = and(_T_16021, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[53] <= _T_16022 @[RegMapper.scala 185:18] + node _T_16023 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16024 = and(_T_16023, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16025 = and(_T_16024, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16026 = and(_T_16025, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16027 = and(_T_16026, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16028 = and(_T_16027, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16029 = and(_T_16028, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16030 = and(_T_16029, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[53] <= _T_16030 @[RegMapper.scala 186:18] + node _T_16031 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16032 = and(_T_16031, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16033 = and(_T_16032, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16034 = and(_T_16033, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16035 = and(_T_16034, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16036 = and(_T_16035, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16037 = and(_T_16036, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16038 = and(_T_16037, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[53] <= _T_16038 @[RegMapper.scala 187:18] + node _T_16039 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16040 = and(_T_16039, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16041 = and(_T_16040, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16042 = and(_T_16041, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16043 = and(_T_16042, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16044 = and(_T_16043, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16045 = and(_T_16044, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16046 = and(_T_16045, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[54] <= _T_16046 @[RegMapper.scala 184:18] + node _T_16047 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16048 = and(_T_16047, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16049 = and(_T_16048, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16050 = and(_T_16049, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16051 = and(_T_16050, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16052 = and(_T_16051, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16053 = and(_T_16052, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16054 = and(_T_16053, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[54] <= _T_16054 @[RegMapper.scala 185:18] + node _T_16055 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16056 = and(_T_16055, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16057 = and(_T_16056, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16058 = and(_T_16057, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16059 = and(_T_16058, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16060 = and(_T_16059, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16061 = and(_T_16060, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16062 = and(_T_16061, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[54] <= _T_16062 @[RegMapper.scala 186:18] + node _T_16063 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16064 = and(_T_16063, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16065 = and(_T_16064, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16066 = and(_T_16065, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16067 = and(_T_16066, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16068 = and(_T_16067, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16069 = and(_T_16068, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16070 = and(_T_16069, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[54] <= _T_16070 @[RegMapper.scala 187:18] + node _T_16071 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16072 = and(_T_16071, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16073 = and(_T_16072, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16074 = and(_T_16073, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16075 = and(_T_16074, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16076 = and(_T_16075, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16077 = and(_T_16076, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16078 = and(_T_16077, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[55] <= _T_16078 @[RegMapper.scala 184:18] + node _T_16079 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16080 = and(_T_16079, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16081 = and(_T_16080, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16082 = and(_T_16081, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16083 = and(_T_16082, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16084 = and(_T_16083, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16085 = and(_T_16084, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16086 = and(_T_16085, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[55] <= _T_16086 @[RegMapper.scala 185:18] + node _T_16087 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16088 = and(_T_16087, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16089 = and(_T_16088, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16090 = and(_T_16089, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16091 = and(_T_16090, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16092 = and(_T_16091, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16093 = and(_T_16092, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16094 = and(_T_16093, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[55] <= _T_16094 @[RegMapper.scala 186:18] + node _T_16095 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16096 = and(_T_16095, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16097 = and(_T_16096, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16098 = and(_T_16097, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16099 = and(_T_16098, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16100 = and(_T_16099, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16101 = and(_T_16100, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16102 = and(_T_16101, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[55] <= _T_16102 @[RegMapper.scala 187:18] + node _T_16103 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16104 = and(_T_16103, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16105 = and(_T_16104, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16106 = and(_T_16105, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16107 = and(_T_16106, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16108 = and(_T_16107, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16109 = and(_T_16108, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16110 = and(_T_16109, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[56] <= _T_16110 @[RegMapper.scala 184:18] + node _T_16111 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16112 = and(_T_16111, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16113 = and(_T_16112, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16114 = and(_T_16113, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16115 = and(_T_16114, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16116 = and(_T_16115, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16117 = and(_T_16116, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16118 = and(_T_16117, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[56] <= _T_16118 @[RegMapper.scala 185:18] + node _T_16119 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16120 = and(_T_16119, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16121 = and(_T_16120, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16122 = and(_T_16121, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16123 = and(_T_16122, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16124 = and(_T_16123, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16125 = and(_T_16124, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16126 = and(_T_16125, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[56] <= _T_16126 @[RegMapper.scala 186:18] + node _T_16127 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16128 = and(_T_16127, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16129 = and(_T_16128, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16130 = and(_T_16129, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16131 = and(_T_16130, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16132 = and(_T_16131, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16133 = and(_T_16132, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16134 = and(_T_16133, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[56] <= _T_16134 @[RegMapper.scala 187:18] + node _T_16135 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16136 = and(_T_16135, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16137 = and(_T_16136, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16138 = and(_T_16137, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16139 = and(_T_16138, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16140 = and(_T_16139, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16141 = and(_T_16140, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16142 = and(_T_16141, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[57] <= _T_16142 @[RegMapper.scala 184:18] + node _T_16143 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16144 = and(_T_16143, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16145 = and(_T_16144, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16146 = and(_T_16145, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16147 = and(_T_16146, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16148 = and(_T_16147, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16149 = and(_T_16148, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16150 = and(_T_16149, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[57] <= _T_16150 @[RegMapper.scala 185:18] + node _T_16151 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16152 = and(_T_16151, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16153 = and(_T_16152, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16154 = and(_T_16153, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16155 = and(_T_16154, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16156 = and(_T_16155, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16157 = and(_T_16156, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16158 = and(_T_16157, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[57] <= _T_16158 @[RegMapper.scala 186:18] + node _T_16159 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16160 = and(_T_16159, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16161 = and(_T_16160, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16162 = and(_T_16161, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16163 = and(_T_16162, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16164 = and(_T_16163, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16165 = and(_T_16164, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16166 = and(_T_16165, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[57] <= _T_16166 @[RegMapper.scala 187:18] + node _T_16167 = and(_T_13818, _T_2334[59]) @[RegMapper.scala 184:66] + node _T_16168 = and(_T_16167, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16169 = and(_T_16168, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16170 = and(_T_16169, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16171 = and(_T_16170, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16172 = and(_T_16171, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16173 = and(_T_16172, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16174 = and(_T_16173, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[58] <= _T_16174 @[RegMapper.scala 184:18] + node _T_16175 = and(_T_13824, _T_2522[59]) @[RegMapper.scala 185:66] + node _T_16176 = and(_T_16175, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16177 = and(_T_16176, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16178 = and(_T_16177, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16179 = and(_T_16178, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16180 = and(_T_16179, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16181 = and(_T_16180, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16182 = and(_T_16181, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[58] <= _T_16182 @[RegMapper.scala 185:18] + node _T_16183 = and(_T_13828, _T_2710[59]) @[RegMapper.scala 186:66] + node _T_16184 = and(_T_16183, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16185 = and(_T_16184, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16186 = and(_T_16185, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16187 = and(_T_16186, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16188 = and(_T_16187, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16189 = and(_T_16188, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16190 = and(_T_16189, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[58] <= _T_16190 @[RegMapper.scala 186:18] + node _T_16191 = and(_T_13834, _T_2898[59]) @[RegMapper.scala 187:66] + node _T_16192 = and(_T_16191, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16193 = and(_T_16192, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16194 = and(_T_16193, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16195 = and(_T_16194, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16196 = and(_T_16195, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16197 = and(_T_16196, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16198 = and(_T_16197, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[58] <= _T_16198 @[RegMapper.scala 187:18] + node _T_16199 = and(_T_13818, _T_2334[58]) @[RegMapper.scala 184:66] + node _T_16200 = and(_T_16199, _T_2334[57]) @[RegMapper.scala 184:66] + node _T_16201 = and(_T_16200, _T_2334[56]) @[RegMapper.scala 184:66] + node _T_16202 = and(_T_16201, _T_2334[55]) @[RegMapper.scala 184:66] + node _T_16203 = and(_T_16202, _T_2334[54]) @[RegMapper.scala 184:66] + node _T_16204 = and(_T_16203, _T_2334[53]) @[RegMapper.scala 184:66] + node _T_16205 = and(_T_16204, _T_2334[52]) @[RegMapper.scala 184:66] + node _T_16206 = and(_T_16205, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[59] <= _T_16206 @[RegMapper.scala 184:18] + node _T_16207 = and(_T_13824, _T_2522[58]) @[RegMapper.scala 185:66] + node _T_16208 = and(_T_16207, _T_2522[57]) @[RegMapper.scala 185:66] + node _T_16209 = and(_T_16208, _T_2522[56]) @[RegMapper.scala 185:66] + node _T_16210 = and(_T_16209, _T_2522[55]) @[RegMapper.scala 185:66] + node _T_16211 = and(_T_16210, _T_2522[54]) @[RegMapper.scala 185:66] + node _T_16212 = and(_T_16211, _T_2522[53]) @[RegMapper.scala 185:66] + node _T_16213 = and(_T_16212, _T_2522[52]) @[RegMapper.scala 185:66] + node _T_16214 = and(_T_16213, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[59] <= _T_16214 @[RegMapper.scala 185:18] + node _T_16215 = and(_T_13828, _T_2710[58]) @[RegMapper.scala 186:66] + node _T_16216 = and(_T_16215, _T_2710[57]) @[RegMapper.scala 186:66] + node _T_16217 = and(_T_16216, _T_2710[56]) @[RegMapper.scala 186:66] + node _T_16218 = and(_T_16217, _T_2710[55]) @[RegMapper.scala 186:66] + node _T_16219 = and(_T_16218, _T_2710[54]) @[RegMapper.scala 186:66] + node _T_16220 = and(_T_16219, _T_2710[53]) @[RegMapper.scala 186:66] + node _T_16221 = and(_T_16220, _T_2710[52]) @[RegMapper.scala 186:66] + node _T_16222 = and(_T_16221, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[59] <= _T_16222 @[RegMapper.scala 186:18] + node _T_16223 = and(_T_13834, _T_2898[58]) @[RegMapper.scala 187:66] + node _T_16224 = and(_T_16223, _T_2898[57]) @[RegMapper.scala 187:66] + node _T_16225 = and(_T_16224, _T_2898[56]) @[RegMapper.scala 187:66] + node _T_16226 = and(_T_16225, _T_2898[55]) @[RegMapper.scala 187:66] + node _T_16227 = and(_T_16226, _T_2898[54]) @[RegMapper.scala 187:66] + node _T_16228 = and(_T_16227, _T_2898[53]) @[RegMapper.scala 187:66] + node _T_16229 = and(_T_16228, _T_2898[52]) @[RegMapper.scala 187:66] + node _T_16230 = and(_T_16229, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[59] <= _T_16230 @[RegMapper.scala 187:18] + node _T_16231 = and(_T_13438, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[60] <= _T_16231 @[RegMapper.scala 184:18] + node _T_16232 = and(_T_13444, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[60] <= _T_16232 @[RegMapper.scala 185:18] + node _T_16233 = and(_T_13448, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[60] <= _T_16233 @[RegMapper.scala 186:18] + node _T_16234 = and(_T_13454, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[60] <= _T_16234 @[RegMapper.scala 187:18] + node _T_16235 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16236 = and(_T_16235, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16237 = and(_T_16236, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16238 = and(_T_16237, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16239 = and(_T_16238, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16240 = and(_T_16239, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16241 = and(_T_16240, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16242 = and(_T_16241, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[61] <= _T_16242 @[RegMapper.scala 184:18] + node _T_16243 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16244 = and(_T_16243, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16245 = and(_T_16244, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16246 = and(_T_16245, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16247 = and(_T_16246, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16248 = and(_T_16247, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16249 = and(_T_16248, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16250 = and(_T_16249, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[61] <= _T_16250 @[RegMapper.scala 185:18] + node _T_16251 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16252 = and(_T_16251, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16253 = and(_T_16252, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16254 = and(_T_16253, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16255 = and(_T_16254, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16256 = and(_T_16255, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16257 = and(_T_16256, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16258 = and(_T_16257, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[61] <= _T_16258 @[RegMapper.scala 186:18] + node _T_16259 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16260 = and(_T_16259, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16261 = and(_T_16260, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16262 = and(_T_16261, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16263 = and(_T_16262, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16264 = and(_T_16263, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16265 = and(_T_16264, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16266 = and(_T_16265, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[61] <= _T_16266 @[RegMapper.scala 187:18] + node _T_16267 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16268 = and(_T_16267, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16269 = and(_T_16268, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16270 = and(_T_16269, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16271 = and(_T_16270, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16272 = and(_T_16271, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16273 = and(_T_16272, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16274 = and(_T_16273, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[62] <= _T_16274 @[RegMapper.scala 184:18] + node _T_16275 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16276 = and(_T_16275, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16277 = and(_T_16276, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16278 = and(_T_16277, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16279 = and(_T_16278, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16280 = and(_T_16279, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16281 = and(_T_16280, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16282 = and(_T_16281, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[62] <= _T_16282 @[RegMapper.scala 185:18] + node _T_16283 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16284 = and(_T_16283, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16285 = and(_T_16284, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16286 = and(_T_16285, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16287 = and(_T_16286, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16288 = and(_T_16287, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16289 = and(_T_16288, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16290 = and(_T_16289, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[62] <= _T_16290 @[RegMapper.scala 186:18] + node _T_16291 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16292 = and(_T_16291, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16293 = and(_T_16292, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16294 = and(_T_16293, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16295 = and(_T_16294, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16296 = and(_T_16295, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16297 = and(_T_16296, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16298 = and(_T_16297, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[62] <= _T_16298 @[RegMapper.scala 187:18] + node _T_16299 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16300 = and(_T_16299, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16301 = and(_T_16300, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16302 = and(_T_16301, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16303 = and(_T_16302, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16304 = and(_T_16303, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16305 = and(_T_16304, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16306 = and(_T_16305, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[63] <= _T_16306 @[RegMapper.scala 184:18] + node _T_16307 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16308 = and(_T_16307, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16309 = and(_T_16308, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16310 = and(_T_16309, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16311 = and(_T_16310, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16312 = and(_T_16311, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16313 = and(_T_16312, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16314 = and(_T_16313, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[63] <= _T_16314 @[RegMapper.scala 185:18] + node _T_16315 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16316 = and(_T_16315, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16317 = and(_T_16316, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16318 = and(_T_16317, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16319 = and(_T_16318, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16320 = and(_T_16319, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16321 = and(_T_16320, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16322 = and(_T_16321, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[63] <= _T_16322 @[RegMapper.scala 186:18] + node _T_16323 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16324 = and(_T_16323, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16325 = and(_T_16324, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16326 = and(_T_16325, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16327 = and(_T_16326, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16328 = and(_T_16327, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16329 = and(_T_16328, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16330 = and(_T_16329, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[63] <= _T_16330 @[RegMapper.scala 187:18] + node _T_16331 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16332 = and(_T_16331, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16333 = and(_T_16332, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16334 = and(_T_16333, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16335 = and(_T_16334, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16336 = and(_T_16335, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16337 = and(_T_16336, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16338 = and(_T_16337, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[64] <= _T_16338 @[RegMapper.scala 184:18] + node _T_16339 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16340 = and(_T_16339, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16341 = and(_T_16340, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16342 = and(_T_16341, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16343 = and(_T_16342, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16344 = and(_T_16343, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16345 = and(_T_16344, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16346 = and(_T_16345, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[64] <= _T_16346 @[RegMapper.scala 185:18] + node _T_16347 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16348 = and(_T_16347, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16349 = and(_T_16348, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16350 = and(_T_16349, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16351 = and(_T_16350, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16352 = and(_T_16351, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16353 = and(_T_16352, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16354 = and(_T_16353, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[64] <= _T_16354 @[RegMapper.scala 186:18] + node _T_16355 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16356 = and(_T_16355, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16357 = and(_T_16356, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16358 = and(_T_16357, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16359 = and(_T_16358, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16360 = and(_T_16359, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16361 = and(_T_16360, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16362 = and(_T_16361, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[64] <= _T_16362 @[RegMapper.scala 187:18] + node _T_16363 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16364 = and(_T_16363, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16365 = and(_T_16364, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16366 = and(_T_16365, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16367 = and(_T_16366, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16368 = and(_T_16367, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16369 = and(_T_16368, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16370 = and(_T_16369, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[65] <= _T_16370 @[RegMapper.scala 184:18] + node _T_16371 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16372 = and(_T_16371, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16373 = and(_T_16372, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16374 = and(_T_16373, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16375 = and(_T_16374, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16376 = and(_T_16375, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16377 = and(_T_16376, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16378 = and(_T_16377, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[65] <= _T_16378 @[RegMapper.scala 185:18] + node _T_16379 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16380 = and(_T_16379, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16381 = and(_T_16380, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16382 = and(_T_16381, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16383 = and(_T_16382, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16384 = and(_T_16383, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16385 = and(_T_16384, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16386 = and(_T_16385, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[65] <= _T_16386 @[RegMapper.scala 186:18] + node _T_16387 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16388 = and(_T_16387, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16389 = and(_T_16388, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16390 = and(_T_16389, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16391 = and(_T_16390, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16392 = and(_T_16391, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16393 = and(_T_16392, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16394 = and(_T_16393, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[65] <= _T_16394 @[RegMapper.scala 187:18] + node _T_16395 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16396 = and(_T_16395, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16397 = and(_T_16396, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16398 = and(_T_16397, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16399 = and(_T_16398, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16400 = and(_T_16399, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16401 = and(_T_16400, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16402 = and(_T_16401, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[66] <= _T_16402 @[RegMapper.scala 184:18] + node _T_16403 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16404 = and(_T_16403, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16405 = and(_T_16404, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16406 = and(_T_16405, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16407 = and(_T_16406, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16408 = and(_T_16407, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16409 = and(_T_16408, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16410 = and(_T_16409, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[66] <= _T_16410 @[RegMapper.scala 185:18] + node _T_16411 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16412 = and(_T_16411, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16413 = and(_T_16412, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16414 = and(_T_16413, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16415 = and(_T_16414, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16416 = and(_T_16415, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16417 = and(_T_16416, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16418 = and(_T_16417, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[66] <= _T_16418 @[RegMapper.scala 186:18] + node _T_16419 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16420 = and(_T_16419, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16421 = and(_T_16420, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16422 = and(_T_16421, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16423 = and(_T_16422, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16424 = and(_T_16423, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16425 = and(_T_16424, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16426 = and(_T_16425, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[66] <= _T_16426 @[RegMapper.scala 187:18] + node _T_16427 = and(_T_13738, _T_2334[68]) @[RegMapper.scala 184:66] + node _T_16428 = and(_T_16427, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16429 = and(_T_16428, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16430 = and(_T_16429, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16431 = and(_T_16430, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16432 = and(_T_16431, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16433 = and(_T_16432, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16434 = and(_T_16433, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[67] <= _T_16434 @[RegMapper.scala 184:18] + node _T_16435 = and(_T_13744, _T_2522[68]) @[RegMapper.scala 185:66] + node _T_16436 = and(_T_16435, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16437 = and(_T_16436, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16438 = and(_T_16437, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16439 = and(_T_16438, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16440 = and(_T_16439, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16441 = and(_T_16440, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16442 = and(_T_16441, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[67] <= _T_16442 @[RegMapper.scala 185:18] + node _T_16443 = and(_T_13748, _T_2710[68]) @[RegMapper.scala 186:66] + node _T_16444 = and(_T_16443, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16445 = and(_T_16444, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16446 = and(_T_16445, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16447 = and(_T_16446, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16448 = and(_T_16447, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16449 = and(_T_16448, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16450 = and(_T_16449, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[67] <= _T_16450 @[RegMapper.scala 186:18] + node _T_16451 = and(_T_13754, _T_2898[68]) @[RegMapper.scala 187:66] + node _T_16452 = and(_T_16451, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16453 = and(_T_16452, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16454 = and(_T_16453, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16455 = and(_T_16454, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16456 = and(_T_16455, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16457 = and(_T_16456, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16458 = and(_T_16457, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[67] <= _T_16458 @[RegMapper.scala 187:18] + node _T_16459 = and(_T_13738, _T_2334[67]) @[RegMapper.scala 184:66] + node _T_16460 = and(_T_16459, _T_2334[66]) @[RegMapper.scala 184:66] + node _T_16461 = and(_T_16460, _T_2334[65]) @[RegMapper.scala 184:66] + node _T_16462 = and(_T_16461, _T_2334[64]) @[RegMapper.scala 184:66] + node _T_16463 = and(_T_16462, _T_2334[63]) @[RegMapper.scala 184:66] + node _T_16464 = and(_T_16463, _T_2334[62]) @[RegMapper.scala 184:66] + node _T_16465 = and(_T_16464, _T_2334[61]) @[RegMapper.scala 184:66] + node _T_16466 = and(_T_16465, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[68] <= _T_16466 @[RegMapper.scala 184:18] + node _T_16467 = and(_T_13744, _T_2522[67]) @[RegMapper.scala 185:66] + node _T_16468 = and(_T_16467, _T_2522[66]) @[RegMapper.scala 185:66] + node _T_16469 = and(_T_16468, _T_2522[65]) @[RegMapper.scala 185:66] + node _T_16470 = and(_T_16469, _T_2522[64]) @[RegMapper.scala 185:66] + node _T_16471 = and(_T_16470, _T_2522[63]) @[RegMapper.scala 185:66] + node _T_16472 = and(_T_16471, _T_2522[62]) @[RegMapper.scala 185:66] + node _T_16473 = and(_T_16472, _T_2522[61]) @[RegMapper.scala 185:66] + node _T_16474 = and(_T_16473, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[68] <= _T_16474 @[RegMapper.scala 185:18] + node _T_16475 = and(_T_13748, _T_2710[67]) @[RegMapper.scala 186:66] + node _T_16476 = and(_T_16475, _T_2710[66]) @[RegMapper.scala 186:66] + node _T_16477 = and(_T_16476, _T_2710[65]) @[RegMapper.scala 186:66] + node _T_16478 = and(_T_16477, _T_2710[64]) @[RegMapper.scala 186:66] + node _T_16479 = and(_T_16478, _T_2710[63]) @[RegMapper.scala 186:66] + node _T_16480 = and(_T_16479, _T_2710[62]) @[RegMapper.scala 186:66] + node _T_16481 = and(_T_16480, _T_2710[61]) @[RegMapper.scala 186:66] + node _T_16482 = and(_T_16481, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[68] <= _T_16482 @[RegMapper.scala 186:18] + node _T_16483 = and(_T_13754, _T_2898[67]) @[RegMapper.scala 187:66] + node _T_16484 = and(_T_16483, _T_2898[66]) @[RegMapper.scala 187:66] + node _T_16485 = and(_T_16484, _T_2898[65]) @[RegMapper.scala 187:66] + node _T_16486 = and(_T_16485, _T_2898[64]) @[RegMapper.scala 187:66] + node _T_16487 = and(_T_16486, _T_2898[63]) @[RegMapper.scala 187:66] + node _T_16488 = and(_T_16487, _T_2898[62]) @[RegMapper.scala 187:66] + node _T_16489 = and(_T_16488, _T_2898[61]) @[RegMapper.scala 187:66] + node _T_16490 = and(_T_16489, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[68] <= _T_16490 @[RegMapper.scala 187:18] + node _T_16491 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16492 = and(_T_16491, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16493 = and(_T_16492, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16494 = and(_T_16493, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16495 = and(_T_16494, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16496 = and(_T_16495, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16497 = and(_T_16496, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16498 = and(_T_16497, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[69] <= _T_16498 @[RegMapper.scala 184:18] + node _T_16499 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16500 = and(_T_16499, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16501 = and(_T_16500, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16502 = and(_T_16501, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16503 = and(_T_16502, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16504 = and(_T_16503, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16505 = and(_T_16504, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16506 = and(_T_16505, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[69] <= _T_16506 @[RegMapper.scala 185:18] + node _T_16507 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16508 = and(_T_16507, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16509 = and(_T_16508, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16510 = and(_T_16509, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16511 = and(_T_16510, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16512 = and(_T_16511, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16513 = and(_T_16512, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16514 = and(_T_16513, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[69] <= _T_16514 @[RegMapper.scala 186:18] + node _T_16515 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16516 = and(_T_16515, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16517 = and(_T_16516, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16518 = and(_T_16517, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16519 = and(_T_16518, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16520 = and(_T_16519, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16521 = and(_T_16520, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16522 = and(_T_16521, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[69] <= _T_16522 @[RegMapper.scala 187:18] + node _T_16523 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16524 = and(_T_16523, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16525 = and(_T_16524, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16526 = and(_T_16525, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16527 = and(_T_16526, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16528 = and(_T_16527, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16529 = and(_T_16528, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16530 = and(_T_16529, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[70] <= _T_16530 @[RegMapper.scala 184:18] + node _T_16531 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16532 = and(_T_16531, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16533 = and(_T_16532, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16534 = and(_T_16533, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16535 = and(_T_16534, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16536 = and(_T_16535, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16537 = and(_T_16536, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16538 = and(_T_16537, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[70] <= _T_16538 @[RegMapper.scala 185:18] + node _T_16539 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16540 = and(_T_16539, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16541 = and(_T_16540, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16542 = and(_T_16541, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16543 = and(_T_16542, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16544 = and(_T_16543, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16545 = and(_T_16544, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16546 = and(_T_16545, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[70] <= _T_16546 @[RegMapper.scala 186:18] + node _T_16547 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16548 = and(_T_16547, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16549 = and(_T_16548, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16550 = and(_T_16549, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16551 = and(_T_16550, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16552 = and(_T_16551, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16553 = and(_T_16552, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16554 = and(_T_16553, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[70] <= _T_16554 @[RegMapper.scala 187:18] + node _T_16555 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16556 = and(_T_16555, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16557 = and(_T_16556, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16558 = and(_T_16557, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16559 = and(_T_16558, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16560 = and(_T_16559, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16561 = and(_T_16560, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16562 = and(_T_16561, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[71] <= _T_16562 @[RegMapper.scala 184:18] + node _T_16563 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16564 = and(_T_16563, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16565 = and(_T_16564, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16566 = and(_T_16565, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16567 = and(_T_16566, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16568 = and(_T_16567, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16569 = and(_T_16568, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16570 = and(_T_16569, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[71] <= _T_16570 @[RegMapper.scala 185:18] + node _T_16571 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16572 = and(_T_16571, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16573 = and(_T_16572, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16574 = and(_T_16573, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16575 = and(_T_16574, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16576 = and(_T_16575, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16577 = and(_T_16576, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16578 = and(_T_16577, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[71] <= _T_16578 @[RegMapper.scala 186:18] + node _T_16579 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16580 = and(_T_16579, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16581 = and(_T_16580, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16582 = and(_T_16581, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16583 = and(_T_16582, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16584 = and(_T_16583, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16585 = and(_T_16584, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16586 = and(_T_16585, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[71] <= _T_16586 @[RegMapper.scala 187:18] + node _T_16587 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16588 = and(_T_16587, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16589 = and(_T_16588, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16590 = and(_T_16589, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16591 = and(_T_16590, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16592 = and(_T_16591, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16593 = and(_T_16592, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16594 = and(_T_16593, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[72] <= _T_16594 @[RegMapper.scala 184:18] + node _T_16595 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16596 = and(_T_16595, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16597 = and(_T_16596, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16598 = and(_T_16597, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16599 = and(_T_16598, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16600 = and(_T_16599, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16601 = and(_T_16600, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16602 = and(_T_16601, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[72] <= _T_16602 @[RegMapper.scala 185:18] + node _T_16603 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16604 = and(_T_16603, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16605 = and(_T_16604, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16606 = and(_T_16605, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16607 = and(_T_16606, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16608 = and(_T_16607, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16609 = and(_T_16608, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16610 = and(_T_16609, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[72] <= _T_16610 @[RegMapper.scala 186:18] + node _T_16611 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16612 = and(_T_16611, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16613 = and(_T_16612, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16614 = and(_T_16613, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16615 = and(_T_16614, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16616 = and(_T_16615, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16617 = and(_T_16616, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16618 = and(_T_16617, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[72] <= _T_16618 @[RegMapper.scala 187:18] + node _T_16619 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16620 = and(_T_16619, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16621 = and(_T_16620, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16622 = and(_T_16621, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16623 = and(_T_16622, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16624 = and(_T_16623, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16625 = and(_T_16624, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16626 = and(_T_16625, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[73] <= _T_16626 @[RegMapper.scala 184:18] + node _T_16627 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16628 = and(_T_16627, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16629 = and(_T_16628, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16630 = and(_T_16629, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16631 = and(_T_16630, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16632 = and(_T_16631, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16633 = and(_T_16632, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16634 = and(_T_16633, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[73] <= _T_16634 @[RegMapper.scala 185:18] + node _T_16635 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16636 = and(_T_16635, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16637 = and(_T_16636, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16638 = and(_T_16637, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16639 = and(_T_16638, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16640 = and(_T_16639, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16641 = and(_T_16640, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16642 = and(_T_16641, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[73] <= _T_16642 @[RegMapper.scala 186:18] + node _T_16643 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16644 = and(_T_16643, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16645 = and(_T_16644, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16646 = and(_T_16645, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16647 = and(_T_16646, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16648 = and(_T_16647, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16649 = and(_T_16648, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16650 = and(_T_16649, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[73] <= _T_16650 @[RegMapper.scala 187:18] + node _T_16651 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16652 = and(_T_16651, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16653 = and(_T_16652, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16654 = and(_T_16653, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16655 = and(_T_16654, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16656 = and(_T_16655, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16657 = and(_T_16656, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16658 = and(_T_16657, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[74] <= _T_16658 @[RegMapper.scala 184:18] + node _T_16659 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16660 = and(_T_16659, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16661 = and(_T_16660, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16662 = and(_T_16661, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16663 = and(_T_16662, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16664 = and(_T_16663, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16665 = and(_T_16664, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16666 = and(_T_16665, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[74] <= _T_16666 @[RegMapper.scala 185:18] + node _T_16667 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16668 = and(_T_16667, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16669 = and(_T_16668, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16670 = and(_T_16669, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16671 = and(_T_16670, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16672 = and(_T_16671, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16673 = and(_T_16672, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16674 = and(_T_16673, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[74] <= _T_16674 @[RegMapper.scala 186:18] + node _T_16675 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16676 = and(_T_16675, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16677 = and(_T_16676, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16678 = and(_T_16677, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16679 = and(_T_16678, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16680 = and(_T_16679, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16681 = and(_T_16680, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16682 = and(_T_16681, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[74] <= _T_16682 @[RegMapper.scala 187:18] + node _T_16683 = and(_T_13118, _T_2334[76]) @[RegMapper.scala 184:66] + node _T_16684 = and(_T_16683, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16685 = and(_T_16684, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16686 = and(_T_16685, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16687 = and(_T_16686, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16688 = and(_T_16687, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16689 = and(_T_16688, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16690 = and(_T_16689, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[75] <= _T_16690 @[RegMapper.scala 184:18] + node _T_16691 = and(_T_13124, _T_2522[76]) @[RegMapper.scala 185:66] + node _T_16692 = and(_T_16691, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16693 = and(_T_16692, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16694 = and(_T_16693, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16695 = and(_T_16694, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16696 = and(_T_16695, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16697 = and(_T_16696, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16698 = and(_T_16697, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[75] <= _T_16698 @[RegMapper.scala 185:18] + node _T_16699 = and(_T_13128, _T_2710[76]) @[RegMapper.scala 186:66] + node _T_16700 = and(_T_16699, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16701 = and(_T_16700, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16702 = and(_T_16701, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16703 = and(_T_16702, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16704 = and(_T_16703, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16705 = and(_T_16704, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16706 = and(_T_16705, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[75] <= _T_16706 @[RegMapper.scala 186:18] + node _T_16707 = and(_T_13134, _T_2898[76]) @[RegMapper.scala 187:66] + node _T_16708 = and(_T_16707, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16709 = and(_T_16708, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16710 = and(_T_16709, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16711 = and(_T_16710, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16712 = and(_T_16711, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16713 = and(_T_16712, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16714 = and(_T_16713, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[75] <= _T_16714 @[RegMapper.scala 187:18] + node _T_16715 = and(_T_13118, _T_2334[75]) @[RegMapper.scala 184:66] + node _T_16716 = and(_T_16715, _T_2334[74]) @[RegMapper.scala 184:66] + node _T_16717 = and(_T_16716, _T_2334[73]) @[RegMapper.scala 184:66] + node _T_16718 = and(_T_16717, _T_2334[72]) @[RegMapper.scala 184:66] + node _T_16719 = and(_T_16718, _T_2334[71]) @[RegMapper.scala 184:66] + node _T_16720 = and(_T_16719, _T_2334[70]) @[RegMapper.scala 184:66] + node _T_16721 = and(_T_16720, _T_2334[69]) @[RegMapper.scala 184:66] + node _T_16722 = and(_T_16721, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[76] <= _T_16722 @[RegMapper.scala 184:18] + node _T_16723 = and(_T_13124, _T_2522[75]) @[RegMapper.scala 185:66] + node _T_16724 = and(_T_16723, _T_2522[74]) @[RegMapper.scala 185:66] + node _T_16725 = and(_T_16724, _T_2522[73]) @[RegMapper.scala 185:66] + node _T_16726 = and(_T_16725, _T_2522[72]) @[RegMapper.scala 185:66] + node _T_16727 = and(_T_16726, _T_2522[71]) @[RegMapper.scala 185:66] + node _T_16728 = and(_T_16727, _T_2522[70]) @[RegMapper.scala 185:66] + node _T_16729 = and(_T_16728, _T_2522[69]) @[RegMapper.scala 185:66] + node _T_16730 = and(_T_16729, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[76] <= _T_16730 @[RegMapper.scala 185:18] + node _T_16731 = and(_T_13128, _T_2710[75]) @[RegMapper.scala 186:66] + node _T_16732 = and(_T_16731, _T_2710[74]) @[RegMapper.scala 186:66] + node _T_16733 = and(_T_16732, _T_2710[73]) @[RegMapper.scala 186:66] + node _T_16734 = and(_T_16733, _T_2710[72]) @[RegMapper.scala 186:66] + node _T_16735 = and(_T_16734, _T_2710[71]) @[RegMapper.scala 186:66] + node _T_16736 = and(_T_16735, _T_2710[70]) @[RegMapper.scala 186:66] + node _T_16737 = and(_T_16736, _T_2710[69]) @[RegMapper.scala 186:66] + node _T_16738 = and(_T_16737, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[76] <= _T_16738 @[RegMapper.scala 186:18] + node _T_16739 = and(_T_13134, _T_2898[75]) @[RegMapper.scala 187:66] + node _T_16740 = and(_T_16739, _T_2898[74]) @[RegMapper.scala 187:66] + node _T_16741 = and(_T_16740, _T_2898[73]) @[RegMapper.scala 187:66] + node _T_16742 = and(_T_16741, _T_2898[72]) @[RegMapper.scala 187:66] + node _T_16743 = and(_T_16742, _T_2898[71]) @[RegMapper.scala 187:66] + node _T_16744 = and(_T_16743, _T_2898[70]) @[RegMapper.scala 187:66] + node _T_16745 = and(_T_16744, _T_2898[69]) @[RegMapper.scala 187:66] + node _T_16746 = and(_T_16745, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[76] <= _T_16746 @[RegMapper.scala 187:18] + node _T_16747 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16748 = and(_T_16747, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16749 = and(_T_16748, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16750 = and(_T_16749, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16751 = and(_T_16750, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16752 = and(_T_16751, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16753 = and(_T_16752, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16754 = and(_T_16753, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[77] <= _T_16754 @[RegMapper.scala 184:18] + node _T_16755 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16756 = and(_T_16755, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16757 = and(_T_16756, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16758 = and(_T_16757, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16759 = and(_T_16758, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16760 = and(_T_16759, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16761 = and(_T_16760, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16762 = and(_T_16761, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[77] <= _T_16762 @[RegMapper.scala 185:18] + node _T_16763 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16764 = and(_T_16763, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16765 = and(_T_16764, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16766 = and(_T_16765, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16767 = and(_T_16766, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16768 = and(_T_16767, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16769 = and(_T_16768, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16770 = and(_T_16769, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[77] <= _T_16770 @[RegMapper.scala 186:18] + node _T_16771 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16772 = and(_T_16771, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16773 = and(_T_16772, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16774 = and(_T_16773, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16775 = and(_T_16774, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16776 = and(_T_16775, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16777 = and(_T_16776, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16778 = and(_T_16777, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[77] <= _T_16778 @[RegMapper.scala 187:18] + node _T_16779 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16780 = and(_T_16779, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16781 = and(_T_16780, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16782 = and(_T_16781, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16783 = and(_T_16782, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16784 = and(_T_16783, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16785 = and(_T_16784, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16786 = and(_T_16785, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[78] <= _T_16786 @[RegMapper.scala 184:18] + node _T_16787 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16788 = and(_T_16787, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16789 = and(_T_16788, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16790 = and(_T_16789, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16791 = and(_T_16790, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16792 = and(_T_16791, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16793 = and(_T_16792, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16794 = and(_T_16793, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[78] <= _T_16794 @[RegMapper.scala 185:18] + node _T_16795 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16796 = and(_T_16795, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16797 = and(_T_16796, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16798 = and(_T_16797, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16799 = and(_T_16798, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16800 = and(_T_16799, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16801 = and(_T_16800, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16802 = and(_T_16801, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[78] <= _T_16802 @[RegMapper.scala 186:18] + node _T_16803 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16804 = and(_T_16803, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16805 = and(_T_16804, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16806 = and(_T_16805, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16807 = and(_T_16806, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16808 = and(_T_16807, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16809 = and(_T_16808, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16810 = and(_T_16809, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[78] <= _T_16810 @[RegMapper.scala 187:18] + node _T_16811 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16812 = and(_T_16811, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16813 = and(_T_16812, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16814 = and(_T_16813, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16815 = and(_T_16814, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16816 = and(_T_16815, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16817 = and(_T_16816, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16818 = and(_T_16817, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[79] <= _T_16818 @[RegMapper.scala 184:18] + node _T_16819 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16820 = and(_T_16819, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16821 = and(_T_16820, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16822 = and(_T_16821, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16823 = and(_T_16822, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16824 = and(_T_16823, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16825 = and(_T_16824, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16826 = and(_T_16825, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[79] <= _T_16826 @[RegMapper.scala 185:18] + node _T_16827 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16828 = and(_T_16827, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16829 = and(_T_16828, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16830 = and(_T_16829, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16831 = and(_T_16830, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16832 = and(_T_16831, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16833 = and(_T_16832, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16834 = and(_T_16833, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[79] <= _T_16834 @[RegMapper.scala 186:18] + node _T_16835 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16836 = and(_T_16835, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16837 = and(_T_16836, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16838 = and(_T_16837, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16839 = and(_T_16838, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16840 = and(_T_16839, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16841 = and(_T_16840, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16842 = and(_T_16841, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[79] <= _T_16842 @[RegMapper.scala 187:18] + node _T_16843 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16844 = and(_T_16843, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16845 = and(_T_16844, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16846 = and(_T_16845, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16847 = and(_T_16846, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16848 = and(_T_16847, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16849 = and(_T_16848, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16850 = and(_T_16849, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[80] <= _T_16850 @[RegMapper.scala 184:18] + node _T_16851 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16852 = and(_T_16851, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16853 = and(_T_16852, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16854 = and(_T_16853, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16855 = and(_T_16854, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16856 = and(_T_16855, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16857 = and(_T_16856, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16858 = and(_T_16857, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[80] <= _T_16858 @[RegMapper.scala 185:18] + node _T_16859 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16860 = and(_T_16859, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16861 = and(_T_16860, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16862 = and(_T_16861, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16863 = and(_T_16862, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16864 = and(_T_16863, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16865 = and(_T_16864, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16866 = and(_T_16865, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[80] <= _T_16866 @[RegMapper.scala 186:18] + node _T_16867 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16868 = and(_T_16867, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16869 = and(_T_16868, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16870 = and(_T_16869, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16871 = and(_T_16870, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16872 = and(_T_16871, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16873 = and(_T_16872, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16874 = and(_T_16873, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[80] <= _T_16874 @[RegMapper.scala 187:18] + node _T_16875 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16876 = and(_T_16875, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16877 = and(_T_16876, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16878 = and(_T_16877, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16879 = and(_T_16878, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16880 = and(_T_16879, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16881 = and(_T_16880, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16882 = and(_T_16881, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[81] <= _T_16882 @[RegMapper.scala 184:18] + node _T_16883 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16884 = and(_T_16883, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16885 = and(_T_16884, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16886 = and(_T_16885, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16887 = and(_T_16886, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16888 = and(_T_16887, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16889 = and(_T_16888, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16890 = and(_T_16889, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[81] <= _T_16890 @[RegMapper.scala 185:18] + node _T_16891 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16892 = and(_T_16891, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16893 = and(_T_16892, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16894 = and(_T_16893, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16895 = and(_T_16894, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16896 = and(_T_16895, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16897 = and(_T_16896, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16898 = and(_T_16897, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[81] <= _T_16898 @[RegMapper.scala 186:18] + node _T_16899 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16900 = and(_T_16899, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16901 = and(_T_16900, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16902 = and(_T_16901, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16903 = and(_T_16902, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16904 = and(_T_16903, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16905 = and(_T_16904, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16906 = and(_T_16905, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[81] <= _T_16906 @[RegMapper.scala 187:18] + node _T_16907 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16908 = and(_T_16907, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16909 = and(_T_16908, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16910 = and(_T_16909, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16911 = and(_T_16910, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16912 = and(_T_16911, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16913 = and(_T_16912, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16914 = and(_T_16913, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[82] <= _T_16914 @[RegMapper.scala 184:18] + node _T_16915 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16916 = and(_T_16915, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16917 = and(_T_16916, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16918 = and(_T_16917, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16919 = and(_T_16918, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16920 = and(_T_16919, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16921 = and(_T_16920, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16922 = and(_T_16921, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[82] <= _T_16922 @[RegMapper.scala 185:18] + node _T_16923 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16924 = and(_T_16923, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16925 = and(_T_16924, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16926 = and(_T_16925, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16927 = and(_T_16926, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16928 = and(_T_16927, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16929 = and(_T_16928, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16930 = and(_T_16929, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[82] <= _T_16930 @[RegMapper.scala 186:18] + node _T_16931 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16932 = and(_T_16931, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16933 = and(_T_16932, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16934 = and(_T_16933, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16935 = and(_T_16934, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16936 = and(_T_16935, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16937 = and(_T_16936, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16938 = and(_T_16937, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[82] <= _T_16938 @[RegMapper.scala 187:18] + node _T_16939 = and(_T_13218, _T_2334[84]) @[RegMapper.scala 184:66] + node _T_16940 = and(_T_16939, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16941 = and(_T_16940, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16942 = and(_T_16941, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16943 = and(_T_16942, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16944 = and(_T_16943, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16945 = and(_T_16944, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16946 = and(_T_16945, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[83] <= _T_16946 @[RegMapper.scala 184:18] + node _T_16947 = and(_T_13224, _T_2522[84]) @[RegMapper.scala 185:66] + node _T_16948 = and(_T_16947, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16949 = and(_T_16948, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16950 = and(_T_16949, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16951 = and(_T_16950, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16952 = and(_T_16951, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16953 = and(_T_16952, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16954 = and(_T_16953, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[83] <= _T_16954 @[RegMapper.scala 185:18] + node _T_16955 = and(_T_13228, _T_2710[84]) @[RegMapper.scala 186:66] + node _T_16956 = and(_T_16955, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16957 = and(_T_16956, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16958 = and(_T_16957, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16959 = and(_T_16958, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16960 = and(_T_16959, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16961 = and(_T_16960, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16962 = and(_T_16961, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[83] <= _T_16962 @[RegMapper.scala 186:18] + node _T_16963 = and(_T_13234, _T_2898[84]) @[RegMapper.scala 187:66] + node _T_16964 = and(_T_16963, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16965 = and(_T_16964, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16966 = and(_T_16965, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16967 = and(_T_16966, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_16968 = and(_T_16967, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_16969 = and(_T_16968, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_16970 = and(_T_16969, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[83] <= _T_16970 @[RegMapper.scala 187:18] + node _T_16971 = and(_T_13218, _T_2334[83]) @[RegMapper.scala 184:66] + node _T_16972 = and(_T_16971, _T_2334[82]) @[RegMapper.scala 184:66] + node _T_16973 = and(_T_16972, _T_2334[81]) @[RegMapper.scala 184:66] + node _T_16974 = and(_T_16973, _T_2334[80]) @[RegMapper.scala 184:66] + node _T_16975 = and(_T_16974, _T_2334[79]) @[RegMapper.scala 184:66] + node _T_16976 = and(_T_16975, _T_2334[78]) @[RegMapper.scala 184:66] + node _T_16977 = and(_T_16976, _T_2334[77]) @[RegMapper.scala 184:66] + node _T_16978 = and(_T_16977, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[84] <= _T_16978 @[RegMapper.scala 184:18] + node _T_16979 = and(_T_13224, _T_2522[83]) @[RegMapper.scala 185:66] + node _T_16980 = and(_T_16979, _T_2522[82]) @[RegMapper.scala 185:66] + node _T_16981 = and(_T_16980, _T_2522[81]) @[RegMapper.scala 185:66] + node _T_16982 = and(_T_16981, _T_2522[80]) @[RegMapper.scala 185:66] + node _T_16983 = and(_T_16982, _T_2522[79]) @[RegMapper.scala 185:66] + node _T_16984 = and(_T_16983, _T_2522[78]) @[RegMapper.scala 185:66] + node _T_16985 = and(_T_16984, _T_2522[77]) @[RegMapper.scala 185:66] + node _T_16986 = and(_T_16985, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[84] <= _T_16986 @[RegMapper.scala 185:18] + node _T_16987 = and(_T_13228, _T_2710[83]) @[RegMapper.scala 186:66] + node _T_16988 = and(_T_16987, _T_2710[82]) @[RegMapper.scala 186:66] + node _T_16989 = and(_T_16988, _T_2710[81]) @[RegMapper.scala 186:66] + node _T_16990 = and(_T_16989, _T_2710[80]) @[RegMapper.scala 186:66] + node _T_16991 = and(_T_16990, _T_2710[79]) @[RegMapper.scala 186:66] + node _T_16992 = and(_T_16991, _T_2710[78]) @[RegMapper.scala 186:66] + node _T_16993 = and(_T_16992, _T_2710[77]) @[RegMapper.scala 186:66] + node _T_16994 = and(_T_16993, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[84] <= _T_16994 @[RegMapper.scala 186:18] + node _T_16995 = and(_T_13234, _T_2898[83]) @[RegMapper.scala 187:66] + node _T_16996 = and(_T_16995, _T_2898[82]) @[RegMapper.scala 187:66] + node _T_16997 = and(_T_16996, _T_2898[81]) @[RegMapper.scala 187:66] + node _T_16998 = and(_T_16997, _T_2898[80]) @[RegMapper.scala 187:66] + node _T_16999 = and(_T_16998, _T_2898[79]) @[RegMapper.scala 187:66] + node _T_17000 = and(_T_16999, _T_2898[78]) @[RegMapper.scala 187:66] + node _T_17001 = and(_T_17000, _T_2898[77]) @[RegMapper.scala 187:66] + node _T_17002 = and(_T_17001, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[84] <= _T_17002 @[RegMapper.scala 187:18] + node _T_17003 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17004 = and(_T_17003, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17005 = and(_T_17004, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17006 = and(_T_17005, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17007 = and(_T_17006, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17008 = and(_T_17007, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17009 = and(_T_17008, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17010 = and(_T_17009, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[85] <= _T_17010 @[RegMapper.scala 184:18] + node _T_17011 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17012 = and(_T_17011, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17013 = and(_T_17012, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17014 = and(_T_17013, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17015 = and(_T_17014, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17016 = and(_T_17015, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17017 = and(_T_17016, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17018 = and(_T_17017, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[85] <= _T_17018 @[RegMapper.scala 185:18] + node _T_17019 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17020 = and(_T_17019, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17021 = and(_T_17020, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17022 = and(_T_17021, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17023 = and(_T_17022, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17024 = and(_T_17023, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17025 = and(_T_17024, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17026 = and(_T_17025, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[85] <= _T_17026 @[RegMapper.scala 186:18] + node _T_17027 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17028 = and(_T_17027, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17029 = and(_T_17028, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17030 = and(_T_17029, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17031 = and(_T_17030, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17032 = and(_T_17031, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17033 = and(_T_17032, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17034 = and(_T_17033, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[85] <= _T_17034 @[RegMapper.scala 187:18] + node _T_17035 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17036 = and(_T_17035, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17037 = and(_T_17036, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17038 = and(_T_17037, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17039 = and(_T_17038, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17040 = and(_T_17039, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17041 = and(_T_17040, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17042 = and(_T_17041, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[86] <= _T_17042 @[RegMapper.scala 184:18] + node _T_17043 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17044 = and(_T_17043, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17045 = and(_T_17044, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17046 = and(_T_17045, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17047 = and(_T_17046, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17048 = and(_T_17047, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17049 = and(_T_17048, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17050 = and(_T_17049, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[86] <= _T_17050 @[RegMapper.scala 185:18] + node _T_17051 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17052 = and(_T_17051, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17053 = and(_T_17052, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17054 = and(_T_17053, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17055 = and(_T_17054, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17056 = and(_T_17055, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17057 = and(_T_17056, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17058 = and(_T_17057, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[86] <= _T_17058 @[RegMapper.scala 186:18] + node _T_17059 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17060 = and(_T_17059, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17061 = and(_T_17060, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17062 = and(_T_17061, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17063 = and(_T_17062, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17064 = and(_T_17063, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17065 = and(_T_17064, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17066 = and(_T_17065, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[86] <= _T_17066 @[RegMapper.scala 187:18] + node _T_17067 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17068 = and(_T_17067, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17069 = and(_T_17068, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17070 = and(_T_17069, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17071 = and(_T_17070, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17072 = and(_T_17071, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17073 = and(_T_17072, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17074 = and(_T_17073, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[87] <= _T_17074 @[RegMapper.scala 184:18] + node _T_17075 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17076 = and(_T_17075, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17077 = and(_T_17076, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17078 = and(_T_17077, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17079 = and(_T_17078, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17080 = and(_T_17079, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17081 = and(_T_17080, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17082 = and(_T_17081, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[87] <= _T_17082 @[RegMapper.scala 185:18] + node _T_17083 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17084 = and(_T_17083, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17085 = and(_T_17084, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17086 = and(_T_17085, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17087 = and(_T_17086, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17088 = and(_T_17087, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17089 = and(_T_17088, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17090 = and(_T_17089, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[87] <= _T_17090 @[RegMapper.scala 186:18] + node _T_17091 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17092 = and(_T_17091, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17093 = and(_T_17092, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17094 = and(_T_17093, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17095 = and(_T_17094, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17096 = and(_T_17095, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17097 = and(_T_17096, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17098 = and(_T_17097, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[87] <= _T_17098 @[RegMapper.scala 187:18] + node _T_17099 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17100 = and(_T_17099, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17101 = and(_T_17100, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17102 = and(_T_17101, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17103 = and(_T_17102, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17104 = and(_T_17103, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17105 = and(_T_17104, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17106 = and(_T_17105, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[88] <= _T_17106 @[RegMapper.scala 184:18] + node _T_17107 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17108 = and(_T_17107, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17109 = and(_T_17108, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17110 = and(_T_17109, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17111 = and(_T_17110, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17112 = and(_T_17111, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17113 = and(_T_17112, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17114 = and(_T_17113, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[88] <= _T_17114 @[RegMapper.scala 185:18] + node _T_17115 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17116 = and(_T_17115, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17117 = and(_T_17116, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17118 = and(_T_17117, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17119 = and(_T_17118, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17120 = and(_T_17119, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17121 = and(_T_17120, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17122 = and(_T_17121, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[88] <= _T_17122 @[RegMapper.scala 186:18] + node _T_17123 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17124 = and(_T_17123, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17125 = and(_T_17124, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17126 = and(_T_17125, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17127 = and(_T_17126, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17128 = and(_T_17127, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17129 = and(_T_17128, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17130 = and(_T_17129, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[88] <= _T_17130 @[RegMapper.scala 187:18] + node _T_17131 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17132 = and(_T_17131, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17133 = and(_T_17132, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17134 = and(_T_17133, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17135 = and(_T_17134, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17136 = and(_T_17135, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17137 = and(_T_17136, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17138 = and(_T_17137, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[89] <= _T_17138 @[RegMapper.scala 184:18] + node _T_17139 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17140 = and(_T_17139, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17141 = and(_T_17140, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17142 = and(_T_17141, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17143 = and(_T_17142, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17144 = and(_T_17143, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17145 = and(_T_17144, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17146 = and(_T_17145, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[89] <= _T_17146 @[RegMapper.scala 185:18] + node _T_17147 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17148 = and(_T_17147, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17149 = and(_T_17148, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17150 = and(_T_17149, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17151 = and(_T_17150, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17152 = and(_T_17151, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17153 = and(_T_17152, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17154 = and(_T_17153, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[89] <= _T_17154 @[RegMapper.scala 186:18] + node _T_17155 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17156 = and(_T_17155, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17157 = and(_T_17156, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17158 = and(_T_17157, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17159 = and(_T_17158, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17160 = and(_T_17159, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17161 = and(_T_17160, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17162 = and(_T_17161, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[89] <= _T_17162 @[RegMapper.scala 187:18] + node _T_17163 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17164 = and(_T_17163, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17165 = and(_T_17164, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17166 = and(_T_17165, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17167 = and(_T_17166, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17168 = and(_T_17167, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17169 = and(_T_17168, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17170 = and(_T_17169, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[90] <= _T_17170 @[RegMapper.scala 184:18] + node _T_17171 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17172 = and(_T_17171, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17173 = and(_T_17172, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17174 = and(_T_17173, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17175 = and(_T_17174, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17176 = and(_T_17175, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17177 = and(_T_17176, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17178 = and(_T_17177, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[90] <= _T_17178 @[RegMapper.scala 185:18] + node _T_17179 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17180 = and(_T_17179, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17181 = and(_T_17180, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17182 = and(_T_17181, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17183 = and(_T_17182, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17184 = and(_T_17183, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17185 = and(_T_17184, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17186 = and(_T_17185, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[90] <= _T_17186 @[RegMapper.scala 186:18] + node _T_17187 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17188 = and(_T_17187, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17189 = and(_T_17188, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17190 = and(_T_17189, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17191 = and(_T_17190, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17192 = and(_T_17191, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17193 = and(_T_17192, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17194 = and(_T_17193, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[90] <= _T_17194 @[RegMapper.scala 187:18] + node _T_17195 = and(_T_13098, _T_2334[92]) @[RegMapper.scala 184:66] + node _T_17196 = and(_T_17195, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17197 = and(_T_17196, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17198 = and(_T_17197, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17199 = and(_T_17198, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17200 = and(_T_17199, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17201 = and(_T_17200, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17202 = and(_T_17201, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[91] <= _T_17202 @[RegMapper.scala 184:18] + node _T_17203 = and(_T_13104, _T_2522[92]) @[RegMapper.scala 185:66] + node _T_17204 = and(_T_17203, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17205 = and(_T_17204, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17206 = and(_T_17205, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17207 = and(_T_17206, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17208 = and(_T_17207, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17209 = and(_T_17208, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17210 = and(_T_17209, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[91] <= _T_17210 @[RegMapper.scala 185:18] + node _T_17211 = and(_T_13108, _T_2710[92]) @[RegMapper.scala 186:66] + node _T_17212 = and(_T_17211, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17213 = and(_T_17212, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17214 = and(_T_17213, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17215 = and(_T_17214, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17216 = and(_T_17215, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17217 = and(_T_17216, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17218 = and(_T_17217, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[91] <= _T_17218 @[RegMapper.scala 186:18] + node _T_17219 = and(_T_13114, _T_2898[92]) @[RegMapper.scala 187:66] + node _T_17220 = and(_T_17219, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17221 = and(_T_17220, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17222 = and(_T_17221, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17223 = and(_T_17222, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17224 = and(_T_17223, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17225 = and(_T_17224, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17226 = and(_T_17225, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[91] <= _T_17226 @[RegMapper.scala 187:18] + node _T_17227 = and(_T_13098, _T_2334[91]) @[RegMapper.scala 184:66] + node _T_17228 = and(_T_17227, _T_2334[90]) @[RegMapper.scala 184:66] + node _T_17229 = and(_T_17228, _T_2334[89]) @[RegMapper.scala 184:66] + node _T_17230 = and(_T_17229, _T_2334[88]) @[RegMapper.scala 184:66] + node _T_17231 = and(_T_17230, _T_2334[87]) @[RegMapper.scala 184:66] + node _T_17232 = and(_T_17231, _T_2334[86]) @[RegMapper.scala 184:66] + node _T_17233 = and(_T_17232, _T_2334[85]) @[RegMapper.scala 184:66] + node _T_17234 = and(_T_17233, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[92] <= _T_17234 @[RegMapper.scala 184:18] + node _T_17235 = and(_T_13104, _T_2522[91]) @[RegMapper.scala 185:66] + node _T_17236 = and(_T_17235, _T_2522[90]) @[RegMapper.scala 185:66] + node _T_17237 = and(_T_17236, _T_2522[89]) @[RegMapper.scala 185:66] + node _T_17238 = and(_T_17237, _T_2522[88]) @[RegMapper.scala 185:66] + node _T_17239 = and(_T_17238, _T_2522[87]) @[RegMapper.scala 185:66] + node _T_17240 = and(_T_17239, _T_2522[86]) @[RegMapper.scala 185:66] + node _T_17241 = and(_T_17240, _T_2522[85]) @[RegMapper.scala 185:66] + node _T_17242 = and(_T_17241, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[92] <= _T_17242 @[RegMapper.scala 185:18] + node _T_17243 = and(_T_13108, _T_2710[91]) @[RegMapper.scala 186:66] + node _T_17244 = and(_T_17243, _T_2710[90]) @[RegMapper.scala 186:66] + node _T_17245 = and(_T_17244, _T_2710[89]) @[RegMapper.scala 186:66] + node _T_17246 = and(_T_17245, _T_2710[88]) @[RegMapper.scala 186:66] + node _T_17247 = and(_T_17246, _T_2710[87]) @[RegMapper.scala 186:66] + node _T_17248 = and(_T_17247, _T_2710[86]) @[RegMapper.scala 186:66] + node _T_17249 = and(_T_17248, _T_2710[85]) @[RegMapper.scala 186:66] + node _T_17250 = and(_T_17249, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[92] <= _T_17250 @[RegMapper.scala 186:18] + node _T_17251 = and(_T_13114, _T_2898[91]) @[RegMapper.scala 187:66] + node _T_17252 = and(_T_17251, _T_2898[90]) @[RegMapper.scala 187:66] + node _T_17253 = and(_T_17252, _T_2898[89]) @[RegMapper.scala 187:66] + node _T_17254 = and(_T_17253, _T_2898[88]) @[RegMapper.scala 187:66] + node _T_17255 = and(_T_17254, _T_2898[87]) @[RegMapper.scala 187:66] + node _T_17256 = and(_T_17255, _T_2898[86]) @[RegMapper.scala 187:66] + node _T_17257 = and(_T_17256, _T_2898[85]) @[RegMapper.scala 187:66] + node _T_17258 = and(_T_17257, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[92] <= _T_17258 @[RegMapper.scala 187:18] + node _T_17259 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17260 = and(_T_17259, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17261 = and(_T_17260, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17262 = and(_T_17261, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17263 = and(_T_17262, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17264 = and(_T_17263, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17265 = and(_T_17264, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17266 = and(_T_17265, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[93] <= _T_17266 @[RegMapper.scala 184:18] + node _T_17267 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17268 = and(_T_17267, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17269 = and(_T_17268, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17270 = and(_T_17269, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17271 = and(_T_17270, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17272 = and(_T_17271, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17273 = and(_T_17272, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17274 = and(_T_17273, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[93] <= _T_17274 @[RegMapper.scala 185:18] + node _T_17275 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17276 = and(_T_17275, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17277 = and(_T_17276, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17278 = and(_T_17277, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17279 = and(_T_17278, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17280 = and(_T_17279, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17281 = and(_T_17280, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17282 = and(_T_17281, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[93] <= _T_17282 @[RegMapper.scala 186:18] + node _T_17283 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17284 = and(_T_17283, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17285 = and(_T_17284, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17286 = and(_T_17285, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17287 = and(_T_17286, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17288 = and(_T_17287, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17289 = and(_T_17288, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17290 = and(_T_17289, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[93] <= _T_17290 @[RegMapper.scala 187:18] + node _T_17291 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17292 = and(_T_17291, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17293 = and(_T_17292, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17294 = and(_T_17293, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17295 = and(_T_17294, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17296 = and(_T_17295, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17297 = and(_T_17296, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17298 = and(_T_17297, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[94] <= _T_17298 @[RegMapper.scala 184:18] + node _T_17299 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17300 = and(_T_17299, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17301 = and(_T_17300, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17302 = and(_T_17301, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17303 = and(_T_17302, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17304 = and(_T_17303, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17305 = and(_T_17304, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17306 = and(_T_17305, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[94] <= _T_17306 @[RegMapper.scala 185:18] + node _T_17307 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17308 = and(_T_17307, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17309 = and(_T_17308, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17310 = and(_T_17309, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17311 = and(_T_17310, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17312 = and(_T_17311, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17313 = and(_T_17312, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17314 = and(_T_17313, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[94] <= _T_17314 @[RegMapper.scala 186:18] + node _T_17315 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17316 = and(_T_17315, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17317 = and(_T_17316, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17318 = and(_T_17317, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17319 = and(_T_17318, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17320 = and(_T_17319, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17321 = and(_T_17320, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17322 = and(_T_17321, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[94] <= _T_17322 @[RegMapper.scala 187:18] + node _T_17323 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17324 = and(_T_17323, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17325 = and(_T_17324, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17326 = and(_T_17325, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17327 = and(_T_17326, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17328 = and(_T_17327, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17329 = and(_T_17328, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17330 = and(_T_17329, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[95] <= _T_17330 @[RegMapper.scala 184:18] + node _T_17331 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17332 = and(_T_17331, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17333 = and(_T_17332, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17334 = and(_T_17333, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17335 = and(_T_17334, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17336 = and(_T_17335, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17337 = and(_T_17336, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17338 = and(_T_17337, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[95] <= _T_17338 @[RegMapper.scala 185:18] + node _T_17339 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17340 = and(_T_17339, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17341 = and(_T_17340, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17342 = and(_T_17341, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17343 = and(_T_17342, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17344 = and(_T_17343, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17345 = and(_T_17344, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17346 = and(_T_17345, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[95] <= _T_17346 @[RegMapper.scala 186:18] + node _T_17347 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17348 = and(_T_17347, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17349 = and(_T_17348, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17350 = and(_T_17349, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17351 = and(_T_17350, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17352 = and(_T_17351, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17353 = and(_T_17352, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17354 = and(_T_17353, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[95] <= _T_17354 @[RegMapper.scala 187:18] + node _T_17355 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17356 = and(_T_17355, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17357 = and(_T_17356, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17358 = and(_T_17357, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17359 = and(_T_17358, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17360 = and(_T_17359, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17361 = and(_T_17360, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17362 = and(_T_17361, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[96] <= _T_17362 @[RegMapper.scala 184:18] + node _T_17363 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17364 = and(_T_17363, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17365 = and(_T_17364, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17366 = and(_T_17365, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17367 = and(_T_17366, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17368 = and(_T_17367, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17369 = and(_T_17368, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17370 = and(_T_17369, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[96] <= _T_17370 @[RegMapper.scala 185:18] + node _T_17371 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17372 = and(_T_17371, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17373 = and(_T_17372, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17374 = and(_T_17373, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17375 = and(_T_17374, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17376 = and(_T_17375, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17377 = and(_T_17376, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17378 = and(_T_17377, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[96] <= _T_17378 @[RegMapper.scala 186:18] + node _T_17379 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17380 = and(_T_17379, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17381 = and(_T_17380, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17382 = and(_T_17381, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17383 = and(_T_17382, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17384 = and(_T_17383, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17385 = and(_T_17384, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17386 = and(_T_17385, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[96] <= _T_17386 @[RegMapper.scala 187:18] + node _T_17387 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17388 = and(_T_17387, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17389 = and(_T_17388, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17390 = and(_T_17389, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17391 = and(_T_17390, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17392 = and(_T_17391, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17393 = and(_T_17392, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17394 = and(_T_17393, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[97] <= _T_17394 @[RegMapper.scala 184:18] + node _T_17395 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17396 = and(_T_17395, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17397 = and(_T_17396, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17398 = and(_T_17397, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17399 = and(_T_17398, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17400 = and(_T_17399, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17401 = and(_T_17400, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17402 = and(_T_17401, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[97] <= _T_17402 @[RegMapper.scala 185:18] + node _T_17403 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17404 = and(_T_17403, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17405 = and(_T_17404, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17406 = and(_T_17405, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17407 = and(_T_17406, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17408 = and(_T_17407, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17409 = and(_T_17408, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17410 = and(_T_17409, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[97] <= _T_17410 @[RegMapper.scala 186:18] + node _T_17411 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17412 = and(_T_17411, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17413 = and(_T_17412, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17414 = and(_T_17413, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17415 = and(_T_17414, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17416 = and(_T_17415, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17417 = and(_T_17416, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17418 = and(_T_17417, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[97] <= _T_17418 @[RegMapper.scala 187:18] + node _T_17419 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17420 = and(_T_17419, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17421 = and(_T_17420, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17422 = and(_T_17421, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17423 = and(_T_17422, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17424 = and(_T_17423, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17425 = and(_T_17424, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17426 = and(_T_17425, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[98] <= _T_17426 @[RegMapper.scala 184:18] + node _T_17427 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17428 = and(_T_17427, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17429 = and(_T_17428, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17430 = and(_T_17429, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17431 = and(_T_17430, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17432 = and(_T_17431, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17433 = and(_T_17432, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17434 = and(_T_17433, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[98] <= _T_17434 @[RegMapper.scala 185:18] + node _T_17435 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17436 = and(_T_17435, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17437 = and(_T_17436, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17438 = and(_T_17437, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17439 = and(_T_17438, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17440 = and(_T_17439, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17441 = and(_T_17440, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17442 = and(_T_17441, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[98] <= _T_17442 @[RegMapper.scala 186:18] + node _T_17443 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17444 = and(_T_17443, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17445 = and(_T_17444, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17446 = and(_T_17445, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17447 = and(_T_17446, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17448 = and(_T_17447, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17449 = and(_T_17448, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17450 = and(_T_17449, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[98] <= _T_17450 @[RegMapper.scala 187:18] + node _T_17451 = and(_T_13938, _T_2334[100]) @[RegMapper.scala 184:66] + node _T_17452 = and(_T_17451, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17453 = and(_T_17452, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17454 = and(_T_17453, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17455 = and(_T_17454, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17456 = and(_T_17455, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17457 = and(_T_17456, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17458 = and(_T_17457, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[99] <= _T_17458 @[RegMapper.scala 184:18] + node _T_17459 = and(_T_13944, _T_2522[100]) @[RegMapper.scala 185:66] + node _T_17460 = and(_T_17459, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17461 = and(_T_17460, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17462 = and(_T_17461, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17463 = and(_T_17462, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17464 = and(_T_17463, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17465 = and(_T_17464, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17466 = and(_T_17465, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[99] <= _T_17466 @[RegMapper.scala 185:18] + node _T_17467 = and(_T_13948, _T_2710[100]) @[RegMapper.scala 186:66] + node _T_17468 = and(_T_17467, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17469 = and(_T_17468, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17470 = and(_T_17469, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17471 = and(_T_17470, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17472 = and(_T_17471, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17473 = and(_T_17472, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17474 = and(_T_17473, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[99] <= _T_17474 @[RegMapper.scala 186:18] + node _T_17475 = and(_T_13954, _T_2898[100]) @[RegMapper.scala 187:66] + node _T_17476 = and(_T_17475, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17477 = and(_T_17476, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17478 = and(_T_17477, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17479 = and(_T_17478, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17480 = and(_T_17479, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17481 = and(_T_17480, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17482 = and(_T_17481, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[99] <= _T_17482 @[RegMapper.scala 187:18] + node _T_17483 = and(_T_13938, _T_2334[99]) @[RegMapper.scala 184:66] + node _T_17484 = and(_T_17483, _T_2334[98]) @[RegMapper.scala 184:66] + node _T_17485 = and(_T_17484, _T_2334[97]) @[RegMapper.scala 184:66] + node _T_17486 = and(_T_17485, _T_2334[96]) @[RegMapper.scala 184:66] + node _T_17487 = and(_T_17486, _T_2334[95]) @[RegMapper.scala 184:66] + node _T_17488 = and(_T_17487, _T_2334[94]) @[RegMapper.scala 184:66] + node _T_17489 = and(_T_17488, _T_2334[93]) @[RegMapper.scala 184:66] + node _T_17490 = and(_T_17489, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[100] <= _T_17490 @[RegMapper.scala 184:18] + node _T_17491 = and(_T_13944, _T_2522[99]) @[RegMapper.scala 185:66] + node _T_17492 = and(_T_17491, _T_2522[98]) @[RegMapper.scala 185:66] + node _T_17493 = and(_T_17492, _T_2522[97]) @[RegMapper.scala 185:66] + node _T_17494 = and(_T_17493, _T_2522[96]) @[RegMapper.scala 185:66] + node _T_17495 = and(_T_17494, _T_2522[95]) @[RegMapper.scala 185:66] + node _T_17496 = and(_T_17495, _T_2522[94]) @[RegMapper.scala 185:66] + node _T_17497 = and(_T_17496, _T_2522[93]) @[RegMapper.scala 185:66] + node _T_17498 = and(_T_17497, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[100] <= _T_17498 @[RegMapper.scala 185:18] + node _T_17499 = and(_T_13948, _T_2710[99]) @[RegMapper.scala 186:66] + node _T_17500 = and(_T_17499, _T_2710[98]) @[RegMapper.scala 186:66] + node _T_17501 = and(_T_17500, _T_2710[97]) @[RegMapper.scala 186:66] + node _T_17502 = and(_T_17501, _T_2710[96]) @[RegMapper.scala 186:66] + node _T_17503 = and(_T_17502, _T_2710[95]) @[RegMapper.scala 186:66] + node _T_17504 = and(_T_17503, _T_2710[94]) @[RegMapper.scala 186:66] + node _T_17505 = and(_T_17504, _T_2710[93]) @[RegMapper.scala 186:66] + node _T_17506 = and(_T_17505, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[100] <= _T_17506 @[RegMapper.scala 186:18] + node _T_17507 = and(_T_13954, _T_2898[99]) @[RegMapper.scala 187:66] + node _T_17508 = and(_T_17507, _T_2898[98]) @[RegMapper.scala 187:66] + node _T_17509 = and(_T_17508, _T_2898[97]) @[RegMapper.scala 187:66] + node _T_17510 = and(_T_17509, _T_2898[96]) @[RegMapper.scala 187:66] + node _T_17511 = and(_T_17510, _T_2898[95]) @[RegMapper.scala 187:66] + node _T_17512 = and(_T_17511, _T_2898[94]) @[RegMapper.scala 187:66] + node _T_17513 = and(_T_17512, _T_2898[93]) @[RegMapper.scala 187:66] + node _T_17514 = and(_T_17513, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[100] <= _T_17514 @[RegMapper.scala 187:18] + node _T_17515 = and(_T_13418, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[101] <= _T_17515 @[RegMapper.scala 184:18] + node _T_17516 = and(_T_13424, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[101] <= _T_17516 @[RegMapper.scala 185:18] + node _T_17517 = and(_T_13428, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[101] <= _T_17517 @[RegMapper.scala 186:18] + node _T_17518 = and(_T_13434, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[101] <= _T_17518 @[RegMapper.scala 187:18] + node _T_17519 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17520 = and(_T_17519, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17521 = and(_T_17520, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17522 = and(_T_17521, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17523 = and(_T_17522, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17524 = and(_T_17523, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17525 = and(_T_17524, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17526 = and(_T_17525, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[102] <= _T_17526 @[RegMapper.scala 184:18] + node _T_17527 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17528 = and(_T_17527, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17529 = and(_T_17528, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17530 = and(_T_17529, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17531 = and(_T_17530, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17532 = and(_T_17531, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17533 = and(_T_17532, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17534 = and(_T_17533, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[102] <= _T_17534 @[RegMapper.scala 185:18] + node _T_17535 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17536 = and(_T_17535, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17537 = and(_T_17536, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17538 = and(_T_17537, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17539 = and(_T_17538, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17540 = and(_T_17539, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17541 = and(_T_17540, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17542 = and(_T_17541, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[102] <= _T_17542 @[RegMapper.scala 186:18] + node _T_17543 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17544 = and(_T_17543, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17545 = and(_T_17544, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17546 = and(_T_17545, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17547 = and(_T_17546, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17548 = and(_T_17547, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17549 = and(_T_17548, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17550 = and(_T_17549, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[102] <= _T_17550 @[RegMapper.scala 187:18] + node _T_17551 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17552 = and(_T_17551, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17553 = and(_T_17552, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17554 = and(_T_17553, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17555 = and(_T_17554, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17556 = and(_T_17555, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17557 = and(_T_17556, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17558 = and(_T_17557, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[103] <= _T_17558 @[RegMapper.scala 184:18] + node _T_17559 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17560 = and(_T_17559, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17561 = and(_T_17560, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17562 = and(_T_17561, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17563 = and(_T_17562, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17564 = and(_T_17563, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17565 = and(_T_17564, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17566 = and(_T_17565, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[103] <= _T_17566 @[RegMapper.scala 185:18] + node _T_17567 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17568 = and(_T_17567, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17569 = and(_T_17568, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17570 = and(_T_17569, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17571 = and(_T_17570, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17572 = and(_T_17571, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17573 = and(_T_17572, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17574 = and(_T_17573, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[103] <= _T_17574 @[RegMapper.scala 186:18] + node _T_17575 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17576 = and(_T_17575, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17577 = and(_T_17576, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17578 = and(_T_17577, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17579 = and(_T_17578, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17580 = and(_T_17579, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17581 = and(_T_17580, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17582 = and(_T_17581, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[103] <= _T_17582 @[RegMapper.scala 187:18] + node _T_17583 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17584 = and(_T_17583, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17585 = and(_T_17584, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17586 = and(_T_17585, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17587 = and(_T_17586, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17588 = and(_T_17587, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17589 = and(_T_17588, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17590 = and(_T_17589, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[104] <= _T_17590 @[RegMapper.scala 184:18] + node _T_17591 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17592 = and(_T_17591, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17593 = and(_T_17592, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17594 = and(_T_17593, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17595 = and(_T_17594, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17596 = and(_T_17595, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17597 = and(_T_17596, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17598 = and(_T_17597, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[104] <= _T_17598 @[RegMapper.scala 185:18] + node _T_17599 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17600 = and(_T_17599, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17601 = and(_T_17600, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17602 = and(_T_17601, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17603 = and(_T_17602, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17604 = and(_T_17603, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17605 = and(_T_17604, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17606 = and(_T_17605, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[104] <= _T_17606 @[RegMapper.scala 186:18] + node _T_17607 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17608 = and(_T_17607, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17609 = and(_T_17608, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17610 = and(_T_17609, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17611 = and(_T_17610, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17612 = and(_T_17611, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17613 = and(_T_17612, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17614 = and(_T_17613, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[104] <= _T_17614 @[RegMapper.scala 187:18] + node _T_17615 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17616 = and(_T_17615, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17617 = and(_T_17616, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17618 = and(_T_17617, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17619 = and(_T_17618, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17620 = and(_T_17619, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17621 = and(_T_17620, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17622 = and(_T_17621, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[105] <= _T_17622 @[RegMapper.scala 184:18] + node _T_17623 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17624 = and(_T_17623, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17625 = and(_T_17624, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17626 = and(_T_17625, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17627 = and(_T_17626, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17628 = and(_T_17627, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17629 = and(_T_17628, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17630 = and(_T_17629, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[105] <= _T_17630 @[RegMapper.scala 185:18] + node _T_17631 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17632 = and(_T_17631, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17633 = and(_T_17632, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17634 = and(_T_17633, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17635 = and(_T_17634, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17636 = and(_T_17635, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17637 = and(_T_17636, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17638 = and(_T_17637, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[105] <= _T_17638 @[RegMapper.scala 186:18] + node _T_17639 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17640 = and(_T_17639, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17641 = and(_T_17640, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17642 = and(_T_17641, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17643 = and(_T_17642, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17644 = and(_T_17643, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17645 = and(_T_17644, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17646 = and(_T_17645, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[105] <= _T_17646 @[RegMapper.scala 187:18] + node _T_17647 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17648 = and(_T_17647, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17649 = and(_T_17648, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17650 = and(_T_17649, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17651 = and(_T_17650, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17652 = and(_T_17651, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17653 = and(_T_17652, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17654 = and(_T_17653, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[106] <= _T_17654 @[RegMapper.scala 184:18] + node _T_17655 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17656 = and(_T_17655, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17657 = and(_T_17656, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17658 = and(_T_17657, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17659 = and(_T_17658, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17660 = and(_T_17659, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17661 = and(_T_17660, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17662 = and(_T_17661, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[106] <= _T_17662 @[RegMapper.scala 185:18] + node _T_17663 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17664 = and(_T_17663, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17665 = and(_T_17664, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17666 = and(_T_17665, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17667 = and(_T_17666, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17668 = and(_T_17667, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17669 = and(_T_17668, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17670 = and(_T_17669, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[106] <= _T_17670 @[RegMapper.scala 186:18] + node _T_17671 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17672 = and(_T_17671, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17673 = and(_T_17672, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17674 = and(_T_17673, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17675 = and(_T_17674, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17676 = and(_T_17675, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17677 = and(_T_17676, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17678 = and(_T_17677, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[106] <= _T_17678 @[RegMapper.scala 187:18] + node _T_17679 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17680 = and(_T_17679, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17681 = and(_T_17680, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17682 = and(_T_17681, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17683 = and(_T_17682, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17684 = and(_T_17683, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17685 = and(_T_17684, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17686 = and(_T_17685, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[107] <= _T_17686 @[RegMapper.scala 184:18] + node _T_17687 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17688 = and(_T_17687, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17689 = and(_T_17688, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17690 = and(_T_17689, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17691 = and(_T_17690, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17692 = and(_T_17691, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17693 = and(_T_17692, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17694 = and(_T_17693, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[107] <= _T_17694 @[RegMapper.scala 185:18] + node _T_17695 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17696 = and(_T_17695, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17697 = and(_T_17696, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17698 = and(_T_17697, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17699 = and(_T_17698, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17700 = and(_T_17699, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17701 = and(_T_17700, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17702 = and(_T_17701, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[107] <= _T_17702 @[RegMapper.scala 186:18] + node _T_17703 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17704 = and(_T_17703, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17705 = and(_T_17704, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17706 = and(_T_17705, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17707 = and(_T_17706, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17708 = and(_T_17707, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17709 = and(_T_17708, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17710 = and(_T_17709, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[107] <= _T_17710 @[RegMapper.scala 187:18] + node _T_17711 = and(_T_13898, _T_2334[109]) @[RegMapper.scala 184:66] + node _T_17712 = and(_T_17711, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17713 = and(_T_17712, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17714 = and(_T_17713, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17715 = and(_T_17714, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17716 = and(_T_17715, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17717 = and(_T_17716, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17718 = and(_T_17717, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[108] <= _T_17718 @[RegMapper.scala 184:18] + node _T_17719 = and(_T_13904, _T_2522[109]) @[RegMapper.scala 185:66] + node _T_17720 = and(_T_17719, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17721 = and(_T_17720, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17722 = and(_T_17721, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17723 = and(_T_17722, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17724 = and(_T_17723, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17725 = and(_T_17724, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17726 = and(_T_17725, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[108] <= _T_17726 @[RegMapper.scala 185:18] + node _T_17727 = and(_T_13908, _T_2710[109]) @[RegMapper.scala 186:66] + node _T_17728 = and(_T_17727, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17729 = and(_T_17728, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17730 = and(_T_17729, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17731 = and(_T_17730, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17732 = and(_T_17731, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17733 = and(_T_17732, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17734 = and(_T_17733, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[108] <= _T_17734 @[RegMapper.scala 186:18] + node _T_17735 = and(_T_13914, _T_2898[109]) @[RegMapper.scala 187:66] + node _T_17736 = and(_T_17735, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17737 = and(_T_17736, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17738 = and(_T_17737, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17739 = and(_T_17738, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17740 = and(_T_17739, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17741 = and(_T_17740, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17742 = and(_T_17741, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[108] <= _T_17742 @[RegMapper.scala 187:18] + node _T_17743 = and(_T_13898, _T_2334[108]) @[RegMapper.scala 184:66] + node _T_17744 = and(_T_17743, _T_2334[107]) @[RegMapper.scala 184:66] + node _T_17745 = and(_T_17744, _T_2334[106]) @[RegMapper.scala 184:66] + node _T_17746 = and(_T_17745, _T_2334[105]) @[RegMapper.scala 184:66] + node _T_17747 = and(_T_17746, _T_2334[104]) @[RegMapper.scala 184:66] + node _T_17748 = and(_T_17747, _T_2334[103]) @[RegMapper.scala 184:66] + node _T_17749 = and(_T_17748, _T_2334[102]) @[RegMapper.scala 184:66] + node _T_17750 = and(_T_17749, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[109] <= _T_17750 @[RegMapper.scala 184:18] + node _T_17751 = and(_T_13904, _T_2522[108]) @[RegMapper.scala 185:66] + node _T_17752 = and(_T_17751, _T_2522[107]) @[RegMapper.scala 185:66] + node _T_17753 = and(_T_17752, _T_2522[106]) @[RegMapper.scala 185:66] + node _T_17754 = and(_T_17753, _T_2522[105]) @[RegMapper.scala 185:66] + node _T_17755 = and(_T_17754, _T_2522[104]) @[RegMapper.scala 185:66] + node _T_17756 = and(_T_17755, _T_2522[103]) @[RegMapper.scala 185:66] + node _T_17757 = and(_T_17756, _T_2522[102]) @[RegMapper.scala 185:66] + node _T_17758 = and(_T_17757, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[109] <= _T_17758 @[RegMapper.scala 185:18] + node _T_17759 = and(_T_13908, _T_2710[108]) @[RegMapper.scala 186:66] + node _T_17760 = and(_T_17759, _T_2710[107]) @[RegMapper.scala 186:66] + node _T_17761 = and(_T_17760, _T_2710[106]) @[RegMapper.scala 186:66] + node _T_17762 = and(_T_17761, _T_2710[105]) @[RegMapper.scala 186:66] + node _T_17763 = and(_T_17762, _T_2710[104]) @[RegMapper.scala 186:66] + node _T_17764 = and(_T_17763, _T_2710[103]) @[RegMapper.scala 186:66] + node _T_17765 = and(_T_17764, _T_2710[102]) @[RegMapper.scala 186:66] + node _T_17766 = and(_T_17765, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[109] <= _T_17766 @[RegMapper.scala 186:18] + node _T_17767 = and(_T_13914, _T_2898[108]) @[RegMapper.scala 187:66] + node _T_17768 = and(_T_17767, _T_2898[107]) @[RegMapper.scala 187:66] + node _T_17769 = and(_T_17768, _T_2898[106]) @[RegMapper.scala 187:66] + node _T_17770 = and(_T_17769, _T_2898[105]) @[RegMapper.scala 187:66] + node _T_17771 = and(_T_17770, _T_2898[104]) @[RegMapper.scala 187:66] + node _T_17772 = and(_T_17771, _T_2898[103]) @[RegMapper.scala 187:66] + node _T_17773 = and(_T_17772, _T_2898[102]) @[RegMapper.scala 187:66] + node _T_17774 = and(_T_17773, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[109] <= _T_17774 @[RegMapper.scala 187:18] + node _T_17775 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17776 = and(_T_17775, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17777 = and(_T_17776, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17778 = and(_T_17777, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17779 = and(_T_17778, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17780 = and(_T_17779, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17781 = and(_T_17780, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17782 = and(_T_17781, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[110] <= _T_17782 @[RegMapper.scala 184:18] + node _T_17783 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17784 = and(_T_17783, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17785 = and(_T_17784, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17786 = and(_T_17785, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17787 = and(_T_17786, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17788 = and(_T_17787, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17789 = and(_T_17788, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17790 = and(_T_17789, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[110] <= _T_17790 @[RegMapper.scala 185:18] + node _T_17791 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17792 = and(_T_17791, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17793 = and(_T_17792, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17794 = and(_T_17793, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17795 = and(_T_17794, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17796 = and(_T_17795, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17797 = and(_T_17796, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17798 = and(_T_17797, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[110] <= _T_17798 @[RegMapper.scala 186:18] + node _T_17799 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17800 = and(_T_17799, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17801 = and(_T_17800, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17802 = and(_T_17801, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17803 = and(_T_17802, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17804 = and(_T_17803, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17805 = and(_T_17804, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17806 = and(_T_17805, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[110] <= _T_17806 @[RegMapper.scala 187:18] + node _T_17807 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17808 = and(_T_17807, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17809 = and(_T_17808, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17810 = and(_T_17809, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17811 = and(_T_17810, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17812 = and(_T_17811, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17813 = and(_T_17812, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17814 = and(_T_17813, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[111] <= _T_17814 @[RegMapper.scala 184:18] + node _T_17815 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17816 = and(_T_17815, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17817 = and(_T_17816, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17818 = and(_T_17817, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17819 = and(_T_17818, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17820 = and(_T_17819, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17821 = and(_T_17820, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17822 = and(_T_17821, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[111] <= _T_17822 @[RegMapper.scala 185:18] + node _T_17823 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17824 = and(_T_17823, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17825 = and(_T_17824, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17826 = and(_T_17825, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17827 = and(_T_17826, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17828 = and(_T_17827, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17829 = and(_T_17828, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17830 = and(_T_17829, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[111] <= _T_17830 @[RegMapper.scala 186:18] + node _T_17831 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17832 = and(_T_17831, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17833 = and(_T_17832, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17834 = and(_T_17833, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17835 = and(_T_17834, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17836 = and(_T_17835, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17837 = and(_T_17836, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17838 = and(_T_17837, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[111] <= _T_17838 @[RegMapper.scala 187:18] + node _T_17839 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17840 = and(_T_17839, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17841 = and(_T_17840, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17842 = and(_T_17841, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17843 = and(_T_17842, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17844 = and(_T_17843, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17845 = and(_T_17844, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17846 = and(_T_17845, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[112] <= _T_17846 @[RegMapper.scala 184:18] + node _T_17847 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17848 = and(_T_17847, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17849 = and(_T_17848, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17850 = and(_T_17849, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17851 = and(_T_17850, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17852 = and(_T_17851, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17853 = and(_T_17852, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17854 = and(_T_17853, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[112] <= _T_17854 @[RegMapper.scala 185:18] + node _T_17855 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17856 = and(_T_17855, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17857 = and(_T_17856, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17858 = and(_T_17857, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17859 = and(_T_17858, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17860 = and(_T_17859, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17861 = and(_T_17860, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17862 = and(_T_17861, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[112] <= _T_17862 @[RegMapper.scala 186:18] + node _T_17863 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17864 = and(_T_17863, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17865 = and(_T_17864, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17866 = and(_T_17865, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17867 = and(_T_17866, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17868 = and(_T_17867, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17869 = and(_T_17868, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17870 = and(_T_17869, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[112] <= _T_17870 @[RegMapper.scala 187:18] + node _T_17871 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17872 = and(_T_17871, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17873 = and(_T_17872, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17874 = and(_T_17873, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17875 = and(_T_17874, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17876 = and(_T_17875, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17877 = and(_T_17876, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17878 = and(_T_17877, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[113] <= _T_17878 @[RegMapper.scala 184:18] + node _T_17879 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17880 = and(_T_17879, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17881 = and(_T_17880, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17882 = and(_T_17881, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17883 = and(_T_17882, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17884 = and(_T_17883, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17885 = and(_T_17884, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17886 = and(_T_17885, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[113] <= _T_17886 @[RegMapper.scala 185:18] + node _T_17887 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17888 = and(_T_17887, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17889 = and(_T_17888, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17890 = and(_T_17889, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17891 = and(_T_17890, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17892 = and(_T_17891, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17893 = and(_T_17892, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17894 = and(_T_17893, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[113] <= _T_17894 @[RegMapper.scala 186:18] + node _T_17895 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17896 = and(_T_17895, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17897 = and(_T_17896, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17898 = and(_T_17897, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17899 = and(_T_17898, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17900 = and(_T_17899, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17901 = and(_T_17900, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17902 = and(_T_17901, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[113] <= _T_17902 @[RegMapper.scala 187:18] + node _T_17903 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17904 = and(_T_17903, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17905 = and(_T_17904, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17906 = and(_T_17905, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17907 = and(_T_17906, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17908 = and(_T_17907, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17909 = and(_T_17908, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17910 = and(_T_17909, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[114] <= _T_17910 @[RegMapper.scala 184:18] + node _T_17911 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17912 = and(_T_17911, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17913 = and(_T_17912, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17914 = and(_T_17913, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17915 = and(_T_17914, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17916 = and(_T_17915, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17917 = and(_T_17916, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17918 = and(_T_17917, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[114] <= _T_17918 @[RegMapper.scala 185:18] + node _T_17919 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17920 = and(_T_17919, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17921 = and(_T_17920, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17922 = and(_T_17921, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17923 = and(_T_17922, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17924 = and(_T_17923, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17925 = and(_T_17924, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17926 = and(_T_17925, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[114] <= _T_17926 @[RegMapper.scala 186:18] + node _T_17927 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17928 = and(_T_17927, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17929 = and(_T_17928, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17930 = and(_T_17929, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17931 = and(_T_17930, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17932 = and(_T_17931, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17933 = and(_T_17932, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17934 = and(_T_17933, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[114] <= _T_17934 @[RegMapper.scala 187:18] + node _T_17935 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17936 = and(_T_17935, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_17937 = and(_T_17936, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17938 = and(_T_17937, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17939 = and(_T_17938, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17940 = and(_T_17939, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17941 = and(_T_17940, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17942 = and(_T_17941, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[115] <= _T_17942 @[RegMapper.scala 184:18] + node _T_17943 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17944 = and(_T_17943, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_17945 = and(_T_17944, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17946 = and(_T_17945, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17947 = and(_T_17946, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17948 = and(_T_17947, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17949 = and(_T_17948, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17950 = and(_T_17949, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[115] <= _T_17950 @[RegMapper.scala 185:18] + node _T_17951 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17952 = and(_T_17951, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_17953 = and(_T_17952, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17954 = and(_T_17953, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17955 = and(_T_17954, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17956 = and(_T_17955, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17957 = and(_T_17956, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17958 = and(_T_17957, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[115] <= _T_17958 @[RegMapper.scala 186:18] + node _T_17959 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17960 = and(_T_17959, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_17961 = and(_T_17960, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17962 = and(_T_17961, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17963 = and(_T_17962, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17964 = and(_T_17963, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17965 = and(_T_17964, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17966 = and(_T_17965, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[115] <= _T_17966 @[RegMapper.scala 187:18] + node _T_17967 = and(_T_13798, _T_2334[117]) @[RegMapper.scala 184:66] + node _T_17968 = and(_T_17967, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_17969 = and(_T_17968, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_17970 = and(_T_17969, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_17971 = and(_T_17970, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_17972 = and(_T_17971, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_17973 = and(_T_17972, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_17974 = and(_T_17973, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[116] <= _T_17974 @[RegMapper.scala 184:18] + node _T_17975 = and(_T_13804, _T_2522[117]) @[RegMapper.scala 185:66] + node _T_17976 = and(_T_17975, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_17977 = and(_T_17976, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_17978 = and(_T_17977, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_17979 = and(_T_17978, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_17980 = and(_T_17979, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_17981 = and(_T_17980, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_17982 = and(_T_17981, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[116] <= _T_17982 @[RegMapper.scala 185:18] + node _T_17983 = and(_T_13808, _T_2710[117]) @[RegMapper.scala 186:66] + node _T_17984 = and(_T_17983, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_17985 = and(_T_17984, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_17986 = and(_T_17985, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_17987 = and(_T_17986, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_17988 = and(_T_17987, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_17989 = and(_T_17988, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_17990 = and(_T_17989, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[116] <= _T_17990 @[RegMapper.scala 186:18] + node _T_17991 = and(_T_13814, _T_2898[117]) @[RegMapper.scala 187:66] + node _T_17992 = and(_T_17991, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_17993 = and(_T_17992, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_17994 = and(_T_17993, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_17995 = and(_T_17994, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_17996 = and(_T_17995, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_17997 = and(_T_17996, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_17998 = and(_T_17997, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[116] <= _T_17998 @[RegMapper.scala 187:18] + node _T_17999 = and(_T_13798, _T_2334[116]) @[RegMapper.scala 184:66] + node _T_18000 = and(_T_17999, _T_2334[115]) @[RegMapper.scala 184:66] + node _T_18001 = and(_T_18000, _T_2334[114]) @[RegMapper.scala 184:66] + node _T_18002 = and(_T_18001, _T_2334[113]) @[RegMapper.scala 184:66] + node _T_18003 = and(_T_18002, _T_2334[112]) @[RegMapper.scala 184:66] + node _T_18004 = and(_T_18003, _T_2334[111]) @[RegMapper.scala 184:66] + node _T_18005 = and(_T_18004, _T_2334[110]) @[RegMapper.scala 184:66] + node _T_18006 = and(_T_18005, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[117] <= _T_18006 @[RegMapper.scala 184:18] + node _T_18007 = and(_T_13804, _T_2522[116]) @[RegMapper.scala 185:66] + node _T_18008 = and(_T_18007, _T_2522[115]) @[RegMapper.scala 185:66] + node _T_18009 = and(_T_18008, _T_2522[114]) @[RegMapper.scala 185:66] + node _T_18010 = and(_T_18009, _T_2522[113]) @[RegMapper.scala 185:66] + node _T_18011 = and(_T_18010, _T_2522[112]) @[RegMapper.scala 185:66] + node _T_18012 = and(_T_18011, _T_2522[111]) @[RegMapper.scala 185:66] + node _T_18013 = and(_T_18012, _T_2522[110]) @[RegMapper.scala 185:66] + node _T_18014 = and(_T_18013, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[117] <= _T_18014 @[RegMapper.scala 185:18] + node _T_18015 = and(_T_13808, _T_2710[116]) @[RegMapper.scala 186:66] + node _T_18016 = and(_T_18015, _T_2710[115]) @[RegMapper.scala 186:66] + node _T_18017 = and(_T_18016, _T_2710[114]) @[RegMapper.scala 186:66] + node _T_18018 = and(_T_18017, _T_2710[113]) @[RegMapper.scala 186:66] + node _T_18019 = and(_T_18018, _T_2710[112]) @[RegMapper.scala 186:66] + node _T_18020 = and(_T_18019, _T_2710[111]) @[RegMapper.scala 186:66] + node _T_18021 = and(_T_18020, _T_2710[110]) @[RegMapper.scala 186:66] + node _T_18022 = and(_T_18021, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[117] <= _T_18022 @[RegMapper.scala 186:18] + node _T_18023 = and(_T_13814, _T_2898[116]) @[RegMapper.scala 187:66] + node _T_18024 = and(_T_18023, _T_2898[115]) @[RegMapper.scala 187:66] + node _T_18025 = and(_T_18024, _T_2898[114]) @[RegMapper.scala 187:66] + node _T_18026 = and(_T_18025, _T_2898[113]) @[RegMapper.scala 187:66] + node _T_18027 = and(_T_18026, _T_2898[112]) @[RegMapper.scala 187:66] + node _T_18028 = and(_T_18027, _T_2898[111]) @[RegMapper.scala 187:66] + node _T_18029 = and(_T_18028, _T_2898[110]) @[RegMapper.scala 187:66] + node _T_18030 = and(_T_18029, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[117] <= _T_18030 @[RegMapper.scala 187:18] + node _T_18031 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18032 = and(_T_18031, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18033 = and(_T_18032, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18034 = and(_T_18033, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18035 = and(_T_18034, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18036 = and(_T_18035, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18037 = and(_T_18036, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18038 = and(_T_18037, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[118] <= _T_18038 @[RegMapper.scala 184:18] + node _T_18039 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18040 = and(_T_18039, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18041 = and(_T_18040, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18042 = and(_T_18041, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18043 = and(_T_18042, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18044 = and(_T_18043, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18045 = and(_T_18044, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18046 = and(_T_18045, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[118] <= _T_18046 @[RegMapper.scala 185:18] + node _T_18047 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18048 = and(_T_18047, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18049 = and(_T_18048, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18050 = and(_T_18049, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18051 = and(_T_18050, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18052 = and(_T_18051, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18053 = and(_T_18052, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18054 = and(_T_18053, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[118] <= _T_18054 @[RegMapper.scala 186:18] + node _T_18055 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18056 = and(_T_18055, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18057 = and(_T_18056, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18058 = and(_T_18057, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18059 = and(_T_18058, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18060 = and(_T_18059, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18061 = and(_T_18060, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18062 = and(_T_18061, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[118] <= _T_18062 @[RegMapper.scala 187:18] + node _T_18063 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18064 = and(_T_18063, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18065 = and(_T_18064, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18066 = and(_T_18065, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18067 = and(_T_18066, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18068 = and(_T_18067, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18069 = and(_T_18068, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18070 = and(_T_18069, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[119] <= _T_18070 @[RegMapper.scala 184:18] + node _T_18071 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18072 = and(_T_18071, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18073 = and(_T_18072, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18074 = and(_T_18073, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18075 = and(_T_18074, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18076 = and(_T_18075, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18077 = and(_T_18076, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18078 = and(_T_18077, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[119] <= _T_18078 @[RegMapper.scala 185:18] + node _T_18079 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18080 = and(_T_18079, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18081 = and(_T_18080, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18082 = and(_T_18081, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18083 = and(_T_18082, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18084 = and(_T_18083, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18085 = and(_T_18084, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18086 = and(_T_18085, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[119] <= _T_18086 @[RegMapper.scala 186:18] + node _T_18087 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18088 = and(_T_18087, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18089 = and(_T_18088, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18090 = and(_T_18089, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18091 = and(_T_18090, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18092 = and(_T_18091, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18093 = and(_T_18092, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18094 = and(_T_18093, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[119] <= _T_18094 @[RegMapper.scala 187:18] + node _T_18095 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18096 = and(_T_18095, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18097 = and(_T_18096, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18098 = and(_T_18097, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18099 = and(_T_18098, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18100 = and(_T_18099, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18101 = and(_T_18100, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18102 = and(_T_18101, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[120] <= _T_18102 @[RegMapper.scala 184:18] + node _T_18103 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18104 = and(_T_18103, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18105 = and(_T_18104, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18106 = and(_T_18105, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18107 = and(_T_18106, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18108 = and(_T_18107, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18109 = and(_T_18108, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18110 = and(_T_18109, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[120] <= _T_18110 @[RegMapper.scala 185:18] + node _T_18111 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18112 = and(_T_18111, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18113 = and(_T_18112, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18114 = and(_T_18113, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18115 = and(_T_18114, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18116 = and(_T_18115, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18117 = and(_T_18116, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18118 = and(_T_18117, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[120] <= _T_18118 @[RegMapper.scala 186:18] + node _T_18119 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18120 = and(_T_18119, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18121 = and(_T_18120, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18122 = and(_T_18121, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18123 = and(_T_18122, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18124 = and(_T_18123, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18125 = and(_T_18124, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18126 = and(_T_18125, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[120] <= _T_18126 @[RegMapper.scala 187:18] + node _T_18127 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18128 = and(_T_18127, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18129 = and(_T_18128, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18130 = and(_T_18129, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18131 = and(_T_18130, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18132 = and(_T_18131, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18133 = and(_T_18132, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18134 = and(_T_18133, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[121] <= _T_18134 @[RegMapper.scala 184:18] + node _T_18135 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18136 = and(_T_18135, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18137 = and(_T_18136, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18138 = and(_T_18137, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18139 = and(_T_18138, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18140 = and(_T_18139, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18141 = and(_T_18140, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18142 = and(_T_18141, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[121] <= _T_18142 @[RegMapper.scala 185:18] + node _T_18143 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18144 = and(_T_18143, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18145 = and(_T_18144, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18146 = and(_T_18145, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18147 = and(_T_18146, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18148 = and(_T_18147, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18149 = and(_T_18148, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18150 = and(_T_18149, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[121] <= _T_18150 @[RegMapper.scala 186:18] + node _T_18151 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18152 = and(_T_18151, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18153 = and(_T_18152, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18154 = and(_T_18153, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18155 = and(_T_18154, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18156 = and(_T_18155, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18157 = and(_T_18156, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18158 = and(_T_18157, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[121] <= _T_18158 @[RegMapper.scala 187:18] + node _T_18159 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18160 = and(_T_18159, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18161 = and(_T_18160, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18162 = and(_T_18161, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18163 = and(_T_18162, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18164 = and(_T_18163, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18165 = and(_T_18164, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18166 = and(_T_18165, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[122] <= _T_18166 @[RegMapper.scala 184:18] + node _T_18167 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18168 = and(_T_18167, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18169 = and(_T_18168, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18170 = and(_T_18169, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18171 = and(_T_18170, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18172 = and(_T_18171, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18173 = and(_T_18172, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18174 = and(_T_18173, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[122] <= _T_18174 @[RegMapper.scala 185:18] + node _T_18175 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18176 = and(_T_18175, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18177 = and(_T_18176, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18178 = and(_T_18177, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18179 = and(_T_18178, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18180 = and(_T_18179, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18181 = and(_T_18180, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18182 = and(_T_18181, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[122] <= _T_18182 @[RegMapper.scala 186:18] + node _T_18183 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18184 = and(_T_18183, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18185 = and(_T_18184, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18186 = and(_T_18185, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18187 = and(_T_18186, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18188 = and(_T_18187, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18189 = and(_T_18188, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18190 = and(_T_18189, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[122] <= _T_18190 @[RegMapper.scala 187:18] + node _T_18191 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18192 = and(_T_18191, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18193 = and(_T_18192, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18194 = and(_T_18193, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18195 = and(_T_18194, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18196 = and(_T_18195, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18197 = and(_T_18196, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18198 = and(_T_18197, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[123] <= _T_18198 @[RegMapper.scala 184:18] + node _T_18199 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18200 = and(_T_18199, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18201 = and(_T_18200, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18202 = and(_T_18201, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18203 = and(_T_18202, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18204 = and(_T_18203, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18205 = and(_T_18204, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18206 = and(_T_18205, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[123] <= _T_18206 @[RegMapper.scala 185:18] + node _T_18207 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18208 = and(_T_18207, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18209 = and(_T_18208, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18210 = and(_T_18209, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18211 = and(_T_18210, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18212 = and(_T_18211, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18213 = and(_T_18212, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18214 = and(_T_18213, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[123] <= _T_18214 @[RegMapper.scala 186:18] + node _T_18215 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18216 = and(_T_18215, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18217 = and(_T_18216, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18218 = and(_T_18217, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18219 = and(_T_18218, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18220 = and(_T_18219, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18221 = and(_T_18220, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18222 = and(_T_18221, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[123] <= _T_18222 @[RegMapper.scala 187:18] + node _T_18223 = and(_T_13138, _T_2334[125]) @[RegMapper.scala 184:66] + node _T_18224 = and(_T_18223, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18225 = and(_T_18224, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18226 = and(_T_18225, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18227 = and(_T_18226, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18228 = and(_T_18227, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18229 = and(_T_18228, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18230 = and(_T_18229, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[124] <= _T_18230 @[RegMapper.scala 184:18] + node _T_18231 = and(_T_13144, _T_2522[125]) @[RegMapper.scala 185:66] + node _T_18232 = and(_T_18231, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18233 = and(_T_18232, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18234 = and(_T_18233, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18235 = and(_T_18234, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18236 = and(_T_18235, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18237 = and(_T_18236, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18238 = and(_T_18237, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[124] <= _T_18238 @[RegMapper.scala 185:18] + node _T_18239 = and(_T_13148, _T_2710[125]) @[RegMapper.scala 186:66] + node _T_18240 = and(_T_18239, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18241 = and(_T_18240, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18242 = and(_T_18241, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18243 = and(_T_18242, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18244 = and(_T_18243, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18245 = and(_T_18244, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18246 = and(_T_18245, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[124] <= _T_18246 @[RegMapper.scala 186:18] + node _T_18247 = and(_T_13154, _T_2898[125]) @[RegMapper.scala 187:66] + node _T_18248 = and(_T_18247, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18249 = and(_T_18248, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18250 = and(_T_18249, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18251 = and(_T_18250, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18252 = and(_T_18251, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18253 = and(_T_18252, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18254 = and(_T_18253, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[124] <= _T_18254 @[RegMapper.scala 187:18] + node _T_18255 = and(_T_13138, _T_2334[124]) @[RegMapper.scala 184:66] + node _T_18256 = and(_T_18255, _T_2334[123]) @[RegMapper.scala 184:66] + node _T_18257 = and(_T_18256, _T_2334[122]) @[RegMapper.scala 184:66] + node _T_18258 = and(_T_18257, _T_2334[121]) @[RegMapper.scala 184:66] + node _T_18259 = and(_T_18258, _T_2334[120]) @[RegMapper.scala 184:66] + node _T_18260 = and(_T_18259, _T_2334[119]) @[RegMapper.scala 184:66] + node _T_18261 = and(_T_18260, _T_2334[118]) @[RegMapper.scala 184:66] + node _T_18262 = and(_T_18261, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[125] <= _T_18262 @[RegMapper.scala 184:18] + node _T_18263 = and(_T_13144, _T_2522[124]) @[RegMapper.scala 185:66] + node _T_18264 = and(_T_18263, _T_2522[123]) @[RegMapper.scala 185:66] + node _T_18265 = and(_T_18264, _T_2522[122]) @[RegMapper.scala 185:66] + node _T_18266 = and(_T_18265, _T_2522[121]) @[RegMapper.scala 185:66] + node _T_18267 = and(_T_18266, _T_2522[120]) @[RegMapper.scala 185:66] + node _T_18268 = and(_T_18267, _T_2522[119]) @[RegMapper.scala 185:66] + node _T_18269 = and(_T_18268, _T_2522[118]) @[RegMapper.scala 185:66] + node _T_18270 = and(_T_18269, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[125] <= _T_18270 @[RegMapper.scala 185:18] + node _T_18271 = and(_T_13148, _T_2710[124]) @[RegMapper.scala 186:66] + node _T_18272 = and(_T_18271, _T_2710[123]) @[RegMapper.scala 186:66] + node _T_18273 = and(_T_18272, _T_2710[122]) @[RegMapper.scala 186:66] + node _T_18274 = and(_T_18273, _T_2710[121]) @[RegMapper.scala 186:66] + node _T_18275 = and(_T_18274, _T_2710[120]) @[RegMapper.scala 186:66] + node _T_18276 = and(_T_18275, _T_2710[119]) @[RegMapper.scala 186:66] + node _T_18277 = and(_T_18276, _T_2710[118]) @[RegMapper.scala 186:66] + node _T_18278 = and(_T_18277, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[125] <= _T_18278 @[RegMapper.scala 186:18] + node _T_18279 = and(_T_13154, _T_2898[124]) @[RegMapper.scala 187:66] + node _T_18280 = and(_T_18279, _T_2898[123]) @[RegMapper.scala 187:66] + node _T_18281 = and(_T_18280, _T_2898[122]) @[RegMapper.scala 187:66] + node _T_18282 = and(_T_18281, _T_2898[121]) @[RegMapper.scala 187:66] + node _T_18283 = and(_T_18282, _T_2898[120]) @[RegMapper.scala 187:66] + node _T_18284 = and(_T_18283, _T_2898[119]) @[RegMapper.scala 187:66] + node _T_18285 = and(_T_18284, _T_2898[118]) @[RegMapper.scala 187:66] + node _T_18286 = and(_T_18285, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[125] <= _T_18286 @[RegMapper.scala 187:18] + node _T_18287 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18288 = and(_T_18287, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18289 = and(_T_18288, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18290 = and(_T_18289, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18291 = and(_T_18290, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18292 = and(_T_18291, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18293 = and(_T_18292, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18294 = and(_T_18293, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[126] <= _T_18294 @[RegMapper.scala 184:18] + node _T_18295 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18296 = and(_T_18295, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18297 = and(_T_18296, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18298 = and(_T_18297, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18299 = and(_T_18298, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18300 = and(_T_18299, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18301 = and(_T_18300, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18302 = and(_T_18301, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[126] <= _T_18302 @[RegMapper.scala 185:18] + node _T_18303 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18304 = and(_T_18303, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18305 = and(_T_18304, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18306 = and(_T_18305, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18307 = and(_T_18306, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18308 = and(_T_18307, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18309 = and(_T_18308, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18310 = and(_T_18309, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[126] <= _T_18310 @[RegMapper.scala 186:18] + node _T_18311 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18312 = and(_T_18311, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18313 = and(_T_18312, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18314 = and(_T_18313, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18315 = and(_T_18314, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18316 = and(_T_18315, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18317 = and(_T_18316, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18318 = and(_T_18317, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[126] <= _T_18318 @[RegMapper.scala 187:18] + node _T_18319 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18320 = and(_T_18319, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18321 = and(_T_18320, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18322 = and(_T_18321, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18323 = and(_T_18322, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18324 = and(_T_18323, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18325 = and(_T_18324, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18326 = and(_T_18325, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[127] <= _T_18326 @[RegMapper.scala 184:18] + node _T_18327 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18328 = and(_T_18327, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18329 = and(_T_18328, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18330 = and(_T_18329, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18331 = and(_T_18330, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18332 = and(_T_18331, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18333 = and(_T_18332, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18334 = and(_T_18333, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[127] <= _T_18334 @[RegMapper.scala 185:18] + node _T_18335 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18336 = and(_T_18335, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18337 = and(_T_18336, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18338 = and(_T_18337, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18339 = and(_T_18338, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18340 = and(_T_18339, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18341 = and(_T_18340, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18342 = and(_T_18341, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[127] <= _T_18342 @[RegMapper.scala 186:18] + node _T_18343 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18344 = and(_T_18343, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18345 = and(_T_18344, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18346 = and(_T_18345, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18347 = and(_T_18346, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18348 = and(_T_18347, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18349 = and(_T_18348, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18350 = and(_T_18349, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[127] <= _T_18350 @[RegMapper.scala 187:18] + node _T_18351 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18352 = and(_T_18351, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18353 = and(_T_18352, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18354 = and(_T_18353, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18355 = and(_T_18354, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18356 = and(_T_18355, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18357 = and(_T_18356, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18358 = and(_T_18357, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[128] <= _T_18358 @[RegMapper.scala 184:18] + node _T_18359 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18360 = and(_T_18359, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18361 = and(_T_18360, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18362 = and(_T_18361, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18363 = and(_T_18362, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18364 = and(_T_18363, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18365 = and(_T_18364, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18366 = and(_T_18365, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[128] <= _T_18366 @[RegMapper.scala 185:18] + node _T_18367 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18368 = and(_T_18367, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18369 = and(_T_18368, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18370 = and(_T_18369, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18371 = and(_T_18370, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18372 = and(_T_18371, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18373 = and(_T_18372, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18374 = and(_T_18373, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[128] <= _T_18374 @[RegMapper.scala 186:18] + node _T_18375 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18376 = and(_T_18375, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18377 = and(_T_18376, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18378 = and(_T_18377, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18379 = and(_T_18378, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18380 = and(_T_18379, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18381 = and(_T_18380, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18382 = and(_T_18381, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[128] <= _T_18382 @[RegMapper.scala 187:18] + node _T_18383 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18384 = and(_T_18383, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18385 = and(_T_18384, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18386 = and(_T_18385, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18387 = and(_T_18386, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18388 = and(_T_18387, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18389 = and(_T_18388, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18390 = and(_T_18389, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[129] <= _T_18390 @[RegMapper.scala 184:18] + node _T_18391 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18392 = and(_T_18391, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18393 = and(_T_18392, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18394 = and(_T_18393, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18395 = and(_T_18394, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18396 = and(_T_18395, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18397 = and(_T_18396, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18398 = and(_T_18397, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[129] <= _T_18398 @[RegMapper.scala 185:18] + node _T_18399 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18400 = and(_T_18399, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18401 = and(_T_18400, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18402 = and(_T_18401, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18403 = and(_T_18402, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18404 = and(_T_18403, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18405 = and(_T_18404, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18406 = and(_T_18405, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[129] <= _T_18406 @[RegMapper.scala 186:18] + node _T_18407 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18408 = and(_T_18407, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18409 = and(_T_18408, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18410 = and(_T_18409, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18411 = and(_T_18410, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18412 = and(_T_18411, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18413 = and(_T_18412, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18414 = and(_T_18413, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[129] <= _T_18414 @[RegMapper.scala 187:18] + node _T_18415 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18416 = and(_T_18415, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18417 = and(_T_18416, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18418 = and(_T_18417, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18419 = and(_T_18418, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18420 = and(_T_18419, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18421 = and(_T_18420, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18422 = and(_T_18421, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[130] <= _T_18422 @[RegMapper.scala 184:18] + node _T_18423 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18424 = and(_T_18423, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18425 = and(_T_18424, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18426 = and(_T_18425, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18427 = and(_T_18426, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18428 = and(_T_18427, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18429 = and(_T_18428, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18430 = and(_T_18429, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[130] <= _T_18430 @[RegMapper.scala 185:18] + node _T_18431 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18432 = and(_T_18431, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18433 = and(_T_18432, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18434 = and(_T_18433, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18435 = and(_T_18434, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18436 = and(_T_18435, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18437 = and(_T_18436, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18438 = and(_T_18437, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[130] <= _T_18438 @[RegMapper.scala 186:18] + node _T_18439 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18440 = and(_T_18439, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18441 = and(_T_18440, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18442 = and(_T_18441, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18443 = and(_T_18442, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18444 = and(_T_18443, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18445 = and(_T_18444, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18446 = and(_T_18445, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[130] <= _T_18446 @[RegMapper.scala 187:18] + node _T_18447 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18448 = and(_T_18447, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18449 = and(_T_18448, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18450 = and(_T_18449, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18451 = and(_T_18450, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18452 = and(_T_18451, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18453 = and(_T_18452, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18454 = and(_T_18453, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[131] <= _T_18454 @[RegMapper.scala 184:18] + node _T_18455 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18456 = and(_T_18455, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18457 = and(_T_18456, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18458 = and(_T_18457, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18459 = and(_T_18458, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18460 = and(_T_18459, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18461 = and(_T_18460, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18462 = and(_T_18461, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[131] <= _T_18462 @[RegMapper.scala 185:18] + node _T_18463 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18464 = and(_T_18463, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18465 = and(_T_18464, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18466 = and(_T_18465, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18467 = and(_T_18466, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18468 = and(_T_18467, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18469 = and(_T_18468, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18470 = and(_T_18469, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[131] <= _T_18470 @[RegMapper.scala 186:18] + node _T_18471 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18472 = and(_T_18471, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18473 = and(_T_18472, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18474 = and(_T_18473, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18475 = and(_T_18474, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18476 = and(_T_18475, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18477 = and(_T_18476, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18478 = and(_T_18477, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[131] <= _T_18478 @[RegMapper.scala 187:18] + node _T_18479 = and(_T_13238, _T_2334[133]) @[RegMapper.scala 184:66] + node _T_18480 = and(_T_18479, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18481 = and(_T_18480, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18482 = and(_T_18481, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18483 = and(_T_18482, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18484 = and(_T_18483, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18485 = and(_T_18484, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18486 = and(_T_18485, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[132] <= _T_18486 @[RegMapper.scala 184:18] + node _T_18487 = and(_T_13244, _T_2522[133]) @[RegMapper.scala 185:66] + node _T_18488 = and(_T_18487, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18489 = and(_T_18488, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18490 = and(_T_18489, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18491 = and(_T_18490, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18492 = and(_T_18491, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18493 = and(_T_18492, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18494 = and(_T_18493, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[132] <= _T_18494 @[RegMapper.scala 185:18] + node _T_18495 = and(_T_13248, _T_2710[133]) @[RegMapper.scala 186:66] + node _T_18496 = and(_T_18495, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18497 = and(_T_18496, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18498 = and(_T_18497, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18499 = and(_T_18498, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18500 = and(_T_18499, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18501 = and(_T_18500, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18502 = and(_T_18501, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[132] <= _T_18502 @[RegMapper.scala 186:18] + node _T_18503 = and(_T_13254, _T_2898[133]) @[RegMapper.scala 187:66] + node _T_18504 = and(_T_18503, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18505 = and(_T_18504, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18506 = and(_T_18505, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18507 = and(_T_18506, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18508 = and(_T_18507, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18509 = and(_T_18508, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18510 = and(_T_18509, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[132] <= _T_18510 @[RegMapper.scala 187:18] + node _T_18511 = and(_T_13238, _T_2334[132]) @[RegMapper.scala 184:66] + node _T_18512 = and(_T_18511, _T_2334[131]) @[RegMapper.scala 184:66] + node _T_18513 = and(_T_18512, _T_2334[130]) @[RegMapper.scala 184:66] + node _T_18514 = and(_T_18513, _T_2334[129]) @[RegMapper.scala 184:66] + node _T_18515 = and(_T_18514, _T_2334[128]) @[RegMapper.scala 184:66] + node _T_18516 = and(_T_18515, _T_2334[127]) @[RegMapper.scala 184:66] + node _T_18517 = and(_T_18516, _T_2334[126]) @[RegMapper.scala 184:66] + node _T_18518 = and(_T_18517, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[133] <= _T_18518 @[RegMapper.scala 184:18] + node _T_18519 = and(_T_13244, _T_2522[132]) @[RegMapper.scala 185:66] + node _T_18520 = and(_T_18519, _T_2522[131]) @[RegMapper.scala 185:66] + node _T_18521 = and(_T_18520, _T_2522[130]) @[RegMapper.scala 185:66] + node _T_18522 = and(_T_18521, _T_2522[129]) @[RegMapper.scala 185:66] + node _T_18523 = and(_T_18522, _T_2522[128]) @[RegMapper.scala 185:66] + node _T_18524 = and(_T_18523, _T_2522[127]) @[RegMapper.scala 185:66] + node _T_18525 = and(_T_18524, _T_2522[126]) @[RegMapper.scala 185:66] + node _T_18526 = and(_T_18525, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[133] <= _T_18526 @[RegMapper.scala 185:18] + node _T_18527 = and(_T_13248, _T_2710[132]) @[RegMapper.scala 186:66] + node _T_18528 = and(_T_18527, _T_2710[131]) @[RegMapper.scala 186:66] + node _T_18529 = and(_T_18528, _T_2710[130]) @[RegMapper.scala 186:66] + node _T_18530 = and(_T_18529, _T_2710[129]) @[RegMapper.scala 186:66] + node _T_18531 = and(_T_18530, _T_2710[128]) @[RegMapper.scala 186:66] + node _T_18532 = and(_T_18531, _T_2710[127]) @[RegMapper.scala 186:66] + node _T_18533 = and(_T_18532, _T_2710[126]) @[RegMapper.scala 186:66] + node _T_18534 = and(_T_18533, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[133] <= _T_18534 @[RegMapper.scala 186:18] + node _T_18535 = and(_T_13254, _T_2898[132]) @[RegMapper.scala 187:66] + node _T_18536 = and(_T_18535, _T_2898[131]) @[RegMapper.scala 187:66] + node _T_18537 = and(_T_18536, _T_2898[130]) @[RegMapper.scala 187:66] + node _T_18538 = and(_T_18537, _T_2898[129]) @[RegMapper.scala 187:66] + node _T_18539 = and(_T_18538, _T_2898[128]) @[RegMapper.scala 187:66] + node _T_18540 = and(_T_18539, _T_2898[127]) @[RegMapper.scala 187:66] + node _T_18541 = and(_T_18540, _T_2898[126]) @[RegMapper.scala 187:66] + node _T_18542 = and(_T_18541, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[133] <= _T_18542 @[RegMapper.scala 187:18] + node _T_18543 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18544 = and(_T_18543, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18545 = and(_T_18544, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18546 = and(_T_18545, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18547 = and(_T_18546, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18548 = and(_T_18547, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18549 = and(_T_18548, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18550 = and(_T_18549, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[134] <= _T_18550 @[RegMapper.scala 184:18] + node _T_18551 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18552 = and(_T_18551, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18553 = and(_T_18552, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18554 = and(_T_18553, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18555 = and(_T_18554, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18556 = and(_T_18555, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18557 = and(_T_18556, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18558 = and(_T_18557, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[134] <= _T_18558 @[RegMapper.scala 185:18] + node _T_18559 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18560 = and(_T_18559, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18561 = and(_T_18560, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18562 = and(_T_18561, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18563 = and(_T_18562, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18564 = and(_T_18563, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18565 = and(_T_18564, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18566 = and(_T_18565, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[134] <= _T_18566 @[RegMapper.scala 186:18] + node _T_18567 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18568 = and(_T_18567, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18569 = and(_T_18568, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18570 = and(_T_18569, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18571 = and(_T_18570, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18572 = and(_T_18571, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18573 = and(_T_18572, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18574 = and(_T_18573, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[134] <= _T_18574 @[RegMapper.scala 187:18] + node _T_18575 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18576 = and(_T_18575, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18577 = and(_T_18576, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18578 = and(_T_18577, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18579 = and(_T_18578, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18580 = and(_T_18579, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18581 = and(_T_18580, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18582 = and(_T_18581, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[135] <= _T_18582 @[RegMapper.scala 184:18] + node _T_18583 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18584 = and(_T_18583, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18585 = and(_T_18584, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18586 = and(_T_18585, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18587 = and(_T_18586, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18588 = and(_T_18587, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18589 = and(_T_18588, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18590 = and(_T_18589, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[135] <= _T_18590 @[RegMapper.scala 185:18] + node _T_18591 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18592 = and(_T_18591, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18593 = and(_T_18592, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18594 = and(_T_18593, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18595 = and(_T_18594, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18596 = and(_T_18595, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18597 = and(_T_18596, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18598 = and(_T_18597, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[135] <= _T_18598 @[RegMapper.scala 186:18] + node _T_18599 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18600 = and(_T_18599, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18601 = and(_T_18600, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18602 = and(_T_18601, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18603 = and(_T_18602, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18604 = and(_T_18603, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18605 = and(_T_18604, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18606 = and(_T_18605, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[135] <= _T_18606 @[RegMapper.scala 187:18] + node _T_18607 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18608 = and(_T_18607, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18609 = and(_T_18608, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18610 = and(_T_18609, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18611 = and(_T_18610, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18612 = and(_T_18611, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18613 = and(_T_18612, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18614 = and(_T_18613, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[136] <= _T_18614 @[RegMapper.scala 184:18] + node _T_18615 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18616 = and(_T_18615, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18617 = and(_T_18616, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18618 = and(_T_18617, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18619 = and(_T_18618, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18620 = and(_T_18619, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18621 = and(_T_18620, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18622 = and(_T_18621, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[136] <= _T_18622 @[RegMapper.scala 185:18] + node _T_18623 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18624 = and(_T_18623, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18625 = and(_T_18624, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18626 = and(_T_18625, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18627 = and(_T_18626, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18628 = and(_T_18627, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18629 = and(_T_18628, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18630 = and(_T_18629, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[136] <= _T_18630 @[RegMapper.scala 186:18] + node _T_18631 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18632 = and(_T_18631, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18633 = and(_T_18632, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18634 = and(_T_18633, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18635 = and(_T_18634, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18636 = and(_T_18635, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18637 = and(_T_18636, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18638 = and(_T_18637, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[136] <= _T_18638 @[RegMapper.scala 187:18] + node _T_18639 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18640 = and(_T_18639, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18641 = and(_T_18640, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18642 = and(_T_18641, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18643 = and(_T_18642, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18644 = and(_T_18643, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18645 = and(_T_18644, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18646 = and(_T_18645, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[137] <= _T_18646 @[RegMapper.scala 184:18] + node _T_18647 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18648 = and(_T_18647, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18649 = and(_T_18648, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18650 = and(_T_18649, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18651 = and(_T_18650, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18652 = and(_T_18651, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18653 = and(_T_18652, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18654 = and(_T_18653, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[137] <= _T_18654 @[RegMapper.scala 185:18] + node _T_18655 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18656 = and(_T_18655, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18657 = and(_T_18656, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18658 = and(_T_18657, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18659 = and(_T_18658, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18660 = and(_T_18659, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18661 = and(_T_18660, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18662 = and(_T_18661, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[137] <= _T_18662 @[RegMapper.scala 186:18] + node _T_18663 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18664 = and(_T_18663, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18665 = and(_T_18664, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18666 = and(_T_18665, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18667 = and(_T_18666, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18668 = and(_T_18667, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18669 = and(_T_18668, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18670 = and(_T_18669, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[137] <= _T_18670 @[RegMapper.scala 187:18] + node _T_18671 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18672 = and(_T_18671, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18673 = and(_T_18672, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18674 = and(_T_18673, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18675 = and(_T_18674, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18676 = and(_T_18675, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18677 = and(_T_18676, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18678 = and(_T_18677, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[138] <= _T_18678 @[RegMapper.scala 184:18] + node _T_18679 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18680 = and(_T_18679, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18681 = and(_T_18680, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18682 = and(_T_18681, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18683 = and(_T_18682, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18684 = and(_T_18683, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18685 = and(_T_18684, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18686 = and(_T_18685, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[138] <= _T_18686 @[RegMapper.scala 185:18] + node _T_18687 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18688 = and(_T_18687, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18689 = and(_T_18688, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18690 = and(_T_18689, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18691 = and(_T_18690, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18692 = and(_T_18691, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18693 = and(_T_18692, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18694 = and(_T_18693, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[138] <= _T_18694 @[RegMapper.scala 186:18] + node _T_18695 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18696 = and(_T_18695, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18697 = and(_T_18696, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18698 = and(_T_18697, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18699 = and(_T_18698, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18700 = and(_T_18699, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18701 = and(_T_18700, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18702 = and(_T_18701, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[138] <= _T_18702 @[RegMapper.scala 187:18] + node _T_18703 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18704 = and(_T_18703, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18705 = and(_T_18704, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18706 = and(_T_18705, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18707 = and(_T_18706, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18708 = and(_T_18707, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18709 = and(_T_18708, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18710 = and(_T_18709, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[139] <= _T_18710 @[RegMapper.scala 184:18] + node _T_18711 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18712 = and(_T_18711, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18713 = and(_T_18712, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18714 = and(_T_18713, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18715 = and(_T_18714, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18716 = and(_T_18715, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18717 = and(_T_18716, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18718 = and(_T_18717, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[139] <= _T_18718 @[RegMapper.scala 185:18] + node _T_18719 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18720 = and(_T_18719, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18721 = and(_T_18720, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18722 = and(_T_18721, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18723 = and(_T_18722, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18724 = and(_T_18723, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18725 = and(_T_18724, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18726 = and(_T_18725, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[139] <= _T_18726 @[RegMapper.scala 186:18] + node _T_18727 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18728 = and(_T_18727, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18729 = and(_T_18728, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18730 = and(_T_18729, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18731 = and(_T_18730, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18732 = and(_T_18731, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18733 = and(_T_18732, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18734 = and(_T_18733, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[139] <= _T_18734 @[RegMapper.scala 187:18] + node _T_18735 = and(_T_13958, _T_2334[141]) @[RegMapper.scala 184:66] + node _T_18736 = and(_T_18735, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18737 = and(_T_18736, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18738 = and(_T_18737, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18739 = and(_T_18738, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18740 = and(_T_18739, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18741 = and(_T_18740, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18742 = and(_T_18741, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[140] <= _T_18742 @[RegMapper.scala 184:18] + node _T_18743 = and(_T_13964, _T_2522[141]) @[RegMapper.scala 185:66] + node _T_18744 = and(_T_18743, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18745 = and(_T_18744, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18746 = and(_T_18745, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18747 = and(_T_18746, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18748 = and(_T_18747, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18749 = and(_T_18748, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18750 = and(_T_18749, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[140] <= _T_18750 @[RegMapper.scala 185:18] + node _T_18751 = and(_T_13968, _T_2710[141]) @[RegMapper.scala 186:66] + node _T_18752 = and(_T_18751, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18753 = and(_T_18752, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18754 = and(_T_18753, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18755 = and(_T_18754, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18756 = and(_T_18755, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18757 = and(_T_18756, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18758 = and(_T_18757, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[140] <= _T_18758 @[RegMapper.scala 186:18] + node _T_18759 = and(_T_13974, _T_2898[141]) @[RegMapper.scala 187:66] + node _T_18760 = and(_T_18759, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18761 = and(_T_18760, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18762 = and(_T_18761, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18763 = and(_T_18762, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18764 = and(_T_18763, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18765 = and(_T_18764, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18766 = and(_T_18765, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[140] <= _T_18766 @[RegMapper.scala 187:18] + node _T_18767 = and(_T_13958, _T_2334[140]) @[RegMapper.scala 184:66] + node _T_18768 = and(_T_18767, _T_2334[139]) @[RegMapper.scala 184:66] + node _T_18769 = and(_T_18768, _T_2334[138]) @[RegMapper.scala 184:66] + node _T_18770 = and(_T_18769, _T_2334[137]) @[RegMapper.scala 184:66] + node _T_18771 = and(_T_18770, _T_2334[136]) @[RegMapper.scala 184:66] + node _T_18772 = and(_T_18771, _T_2334[135]) @[RegMapper.scala 184:66] + node _T_18773 = and(_T_18772, _T_2334[134]) @[RegMapper.scala 184:66] + node _T_18774 = and(_T_18773, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[141] <= _T_18774 @[RegMapper.scala 184:18] + node _T_18775 = and(_T_13964, _T_2522[140]) @[RegMapper.scala 185:66] + node _T_18776 = and(_T_18775, _T_2522[139]) @[RegMapper.scala 185:66] + node _T_18777 = and(_T_18776, _T_2522[138]) @[RegMapper.scala 185:66] + node _T_18778 = and(_T_18777, _T_2522[137]) @[RegMapper.scala 185:66] + node _T_18779 = and(_T_18778, _T_2522[136]) @[RegMapper.scala 185:66] + node _T_18780 = and(_T_18779, _T_2522[135]) @[RegMapper.scala 185:66] + node _T_18781 = and(_T_18780, _T_2522[134]) @[RegMapper.scala 185:66] + node _T_18782 = and(_T_18781, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[141] <= _T_18782 @[RegMapper.scala 185:18] + node _T_18783 = and(_T_13968, _T_2710[140]) @[RegMapper.scala 186:66] + node _T_18784 = and(_T_18783, _T_2710[139]) @[RegMapper.scala 186:66] + node _T_18785 = and(_T_18784, _T_2710[138]) @[RegMapper.scala 186:66] + node _T_18786 = and(_T_18785, _T_2710[137]) @[RegMapper.scala 186:66] + node _T_18787 = and(_T_18786, _T_2710[136]) @[RegMapper.scala 186:66] + node _T_18788 = and(_T_18787, _T_2710[135]) @[RegMapper.scala 186:66] + node _T_18789 = and(_T_18788, _T_2710[134]) @[RegMapper.scala 186:66] + node _T_18790 = and(_T_18789, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[141] <= _T_18790 @[RegMapper.scala 186:18] + node _T_18791 = and(_T_13974, _T_2898[140]) @[RegMapper.scala 187:66] + node _T_18792 = and(_T_18791, _T_2898[139]) @[RegMapper.scala 187:66] + node _T_18793 = and(_T_18792, _T_2898[138]) @[RegMapper.scala 187:66] + node _T_18794 = and(_T_18793, _T_2898[137]) @[RegMapper.scala 187:66] + node _T_18795 = and(_T_18794, _T_2898[136]) @[RegMapper.scala 187:66] + node _T_18796 = and(_T_18795, _T_2898[135]) @[RegMapper.scala 187:66] + node _T_18797 = and(_T_18796, _T_2898[134]) @[RegMapper.scala 187:66] + node _T_18798 = and(_T_18797, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[141] <= _T_18798 @[RegMapper.scala 187:18] + node _T_18799 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18800 = and(_T_18799, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18801 = and(_T_18800, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18802 = and(_T_18801, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18803 = and(_T_18802, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18804 = and(_T_18803, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18805 = and(_T_18804, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18806 = and(_T_18805, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[142] <= _T_18806 @[RegMapper.scala 184:18] + node _T_18807 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18808 = and(_T_18807, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18809 = and(_T_18808, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_18810 = and(_T_18809, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_18811 = and(_T_18810, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_18812 = and(_T_18811, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_18813 = and(_T_18812, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_18814 = and(_T_18813, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[142] <= _T_18814 @[RegMapper.scala 185:18] + node _T_18815 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18816 = and(_T_18815, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18817 = and(_T_18816, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_18818 = and(_T_18817, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_18819 = and(_T_18818, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_18820 = and(_T_18819, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_18821 = and(_T_18820, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_18822 = and(_T_18821, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[142] <= _T_18822 @[RegMapper.scala 186:18] + node _T_18823 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18824 = and(_T_18823, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18825 = and(_T_18824, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_18826 = and(_T_18825, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_18827 = and(_T_18826, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_18828 = and(_T_18827, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_18829 = and(_T_18828, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_18830 = and(_T_18829, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[142] <= _T_18830 @[RegMapper.scala 187:18] + node _T_18831 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18832 = and(_T_18831, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18833 = and(_T_18832, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18834 = and(_T_18833, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18835 = and(_T_18834, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18836 = and(_T_18835, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18837 = and(_T_18836, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18838 = and(_T_18837, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[143] <= _T_18838 @[RegMapper.scala 184:18] + node _T_18839 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18840 = and(_T_18839, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18841 = and(_T_18840, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_18842 = and(_T_18841, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_18843 = and(_T_18842, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_18844 = and(_T_18843, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_18845 = and(_T_18844, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_18846 = and(_T_18845, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[143] <= _T_18846 @[RegMapper.scala 185:18] + node _T_18847 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18848 = and(_T_18847, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18849 = and(_T_18848, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_18850 = and(_T_18849, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_18851 = and(_T_18850, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_18852 = and(_T_18851, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_18853 = and(_T_18852, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_18854 = and(_T_18853, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[143] <= _T_18854 @[RegMapper.scala 186:18] + node _T_18855 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18856 = and(_T_18855, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18857 = and(_T_18856, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_18858 = and(_T_18857, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_18859 = and(_T_18858, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_18860 = and(_T_18859, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_18861 = and(_T_18860, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_18862 = and(_T_18861, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[143] <= _T_18862 @[RegMapper.scala 187:18] + node _T_18863 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18864 = and(_T_18863, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18865 = and(_T_18864, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18866 = and(_T_18865, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18867 = and(_T_18866, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18868 = and(_T_18867, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18869 = and(_T_18868, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18870 = and(_T_18869, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[144] <= _T_18870 @[RegMapper.scala 184:18] + node _T_18871 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18872 = and(_T_18871, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18873 = and(_T_18872, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_18874 = and(_T_18873, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_18875 = and(_T_18874, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_18876 = and(_T_18875, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_18877 = and(_T_18876, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_18878 = and(_T_18877, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[144] <= _T_18878 @[RegMapper.scala 185:18] + node _T_18879 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18880 = and(_T_18879, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18881 = and(_T_18880, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_18882 = and(_T_18881, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_18883 = and(_T_18882, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_18884 = and(_T_18883, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_18885 = and(_T_18884, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_18886 = and(_T_18885, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[144] <= _T_18886 @[RegMapper.scala 186:18] + node _T_18887 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18888 = and(_T_18887, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18889 = and(_T_18888, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_18890 = and(_T_18889, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_18891 = and(_T_18890, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_18892 = and(_T_18891, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_18893 = and(_T_18892, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_18894 = and(_T_18893, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[144] <= _T_18894 @[RegMapper.scala 187:18] + node _T_18895 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18896 = and(_T_18895, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18897 = and(_T_18896, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18898 = and(_T_18897, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18899 = and(_T_18898, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18900 = and(_T_18899, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18901 = and(_T_18900, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18902 = and(_T_18901, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[145] <= _T_18902 @[RegMapper.scala 184:18] + node _T_18903 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18904 = and(_T_18903, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18905 = and(_T_18904, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_18906 = and(_T_18905, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_18907 = and(_T_18906, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_18908 = and(_T_18907, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_18909 = and(_T_18908, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_18910 = and(_T_18909, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[145] <= _T_18910 @[RegMapper.scala 185:18] + node _T_18911 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18912 = and(_T_18911, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18913 = and(_T_18912, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_18914 = and(_T_18913, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_18915 = and(_T_18914, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_18916 = and(_T_18915, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_18917 = and(_T_18916, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_18918 = and(_T_18917, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[145] <= _T_18918 @[RegMapper.scala 186:18] + node _T_18919 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18920 = and(_T_18919, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18921 = and(_T_18920, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_18922 = and(_T_18921, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_18923 = and(_T_18922, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_18924 = and(_T_18923, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_18925 = and(_T_18924, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_18926 = and(_T_18925, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[145] <= _T_18926 @[RegMapper.scala 187:18] + node _T_18927 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18928 = and(_T_18927, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18929 = and(_T_18928, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18930 = and(_T_18929, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18931 = and(_T_18930, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18932 = and(_T_18931, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18933 = and(_T_18932, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18934 = and(_T_18933, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[146] <= _T_18934 @[RegMapper.scala 184:18] + node _T_18935 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18936 = and(_T_18935, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18937 = and(_T_18936, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_18938 = and(_T_18937, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_18939 = and(_T_18938, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_18940 = and(_T_18939, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_18941 = and(_T_18940, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_18942 = and(_T_18941, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[146] <= _T_18942 @[RegMapper.scala 185:18] + node _T_18943 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18944 = and(_T_18943, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18945 = and(_T_18944, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_18946 = and(_T_18945, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_18947 = and(_T_18946, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_18948 = and(_T_18947, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_18949 = and(_T_18948, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_18950 = and(_T_18949, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[146] <= _T_18950 @[RegMapper.scala 186:18] + node _T_18951 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18952 = and(_T_18951, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18953 = and(_T_18952, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_18954 = and(_T_18953, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_18955 = and(_T_18954, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_18956 = and(_T_18955, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_18957 = and(_T_18956, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_18958 = and(_T_18957, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[146] <= _T_18958 @[RegMapper.scala 187:18] + node _T_18959 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18960 = and(_T_18959, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_18961 = and(_T_18960, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18962 = and(_T_18961, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18963 = and(_T_18962, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18964 = and(_T_18963, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18965 = and(_T_18964, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18966 = and(_T_18965, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[147] <= _T_18966 @[RegMapper.scala 184:18] + node _T_18967 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_18968 = and(_T_18967, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_18969 = and(_T_18968, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_18970 = and(_T_18969, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_18971 = and(_T_18970, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_18972 = and(_T_18971, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_18973 = and(_T_18972, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_18974 = and(_T_18973, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[147] <= _T_18974 @[RegMapper.scala 185:18] + node _T_18975 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_18976 = and(_T_18975, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_18977 = and(_T_18976, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_18978 = and(_T_18977, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_18979 = and(_T_18978, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_18980 = and(_T_18979, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_18981 = and(_T_18980, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_18982 = and(_T_18981, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[147] <= _T_18982 @[RegMapper.scala 186:18] + node _T_18983 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_18984 = and(_T_18983, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_18985 = and(_T_18984, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_18986 = and(_T_18985, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_18987 = and(_T_18986, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_18988 = and(_T_18987, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_18989 = and(_T_18988, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_18990 = and(_T_18989, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[147] <= _T_18990 @[RegMapper.scala 187:18] + node _T_18991 = and(_T_13878, _T_2334[149]) @[RegMapper.scala 184:66] + node _T_18992 = and(_T_18991, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_18993 = and(_T_18992, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_18994 = and(_T_18993, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_18995 = and(_T_18994, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_18996 = and(_T_18995, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_18997 = and(_T_18996, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_18998 = and(_T_18997, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[148] <= _T_18998 @[RegMapper.scala 184:18] + node _T_18999 = and(_T_13884, _T_2522[149]) @[RegMapper.scala 185:66] + node _T_19000 = and(_T_18999, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_19001 = and(_T_19000, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_19002 = and(_T_19001, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_19003 = and(_T_19002, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_19004 = and(_T_19003, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_19005 = and(_T_19004, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_19006 = and(_T_19005, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[148] <= _T_19006 @[RegMapper.scala 185:18] + node _T_19007 = and(_T_13888, _T_2710[149]) @[RegMapper.scala 186:66] + node _T_19008 = and(_T_19007, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_19009 = and(_T_19008, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_19010 = and(_T_19009, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_19011 = and(_T_19010, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_19012 = and(_T_19011, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_19013 = and(_T_19012, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_19014 = and(_T_19013, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[148] <= _T_19014 @[RegMapper.scala 186:18] + node _T_19015 = and(_T_13894, _T_2898[149]) @[RegMapper.scala 187:66] + node _T_19016 = and(_T_19015, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_19017 = and(_T_19016, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_19018 = and(_T_19017, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_19019 = and(_T_19018, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_19020 = and(_T_19019, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_19021 = and(_T_19020, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_19022 = and(_T_19021, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[148] <= _T_19022 @[RegMapper.scala 187:18] + node _T_19023 = and(_T_13878, _T_2334[148]) @[RegMapper.scala 184:66] + node _T_19024 = and(_T_19023, _T_2334[147]) @[RegMapper.scala 184:66] + node _T_19025 = and(_T_19024, _T_2334[146]) @[RegMapper.scala 184:66] + node _T_19026 = and(_T_19025, _T_2334[145]) @[RegMapper.scala 184:66] + node _T_19027 = and(_T_19026, _T_2334[144]) @[RegMapper.scala 184:66] + node _T_19028 = and(_T_19027, _T_2334[143]) @[RegMapper.scala 184:66] + node _T_19029 = and(_T_19028, _T_2334[142]) @[RegMapper.scala 184:66] + node _T_19030 = and(_T_19029, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[149] <= _T_19030 @[RegMapper.scala 184:18] + node _T_19031 = and(_T_13884, _T_2522[148]) @[RegMapper.scala 185:66] + node _T_19032 = and(_T_19031, _T_2522[147]) @[RegMapper.scala 185:66] + node _T_19033 = and(_T_19032, _T_2522[146]) @[RegMapper.scala 185:66] + node _T_19034 = and(_T_19033, _T_2522[145]) @[RegMapper.scala 185:66] + node _T_19035 = and(_T_19034, _T_2522[144]) @[RegMapper.scala 185:66] + node _T_19036 = and(_T_19035, _T_2522[143]) @[RegMapper.scala 185:66] + node _T_19037 = and(_T_19036, _T_2522[142]) @[RegMapper.scala 185:66] + node _T_19038 = and(_T_19037, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[149] <= _T_19038 @[RegMapper.scala 185:18] + node _T_19039 = and(_T_13888, _T_2710[148]) @[RegMapper.scala 186:66] + node _T_19040 = and(_T_19039, _T_2710[147]) @[RegMapper.scala 186:66] + node _T_19041 = and(_T_19040, _T_2710[146]) @[RegMapper.scala 186:66] + node _T_19042 = and(_T_19041, _T_2710[145]) @[RegMapper.scala 186:66] + node _T_19043 = and(_T_19042, _T_2710[144]) @[RegMapper.scala 186:66] + node _T_19044 = and(_T_19043, _T_2710[143]) @[RegMapper.scala 186:66] + node _T_19045 = and(_T_19044, _T_2710[142]) @[RegMapper.scala 186:66] + node _T_19046 = and(_T_19045, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[149] <= _T_19046 @[RegMapper.scala 186:18] + node _T_19047 = and(_T_13894, _T_2898[148]) @[RegMapper.scala 187:66] + node _T_19048 = and(_T_19047, _T_2898[147]) @[RegMapper.scala 187:66] + node _T_19049 = and(_T_19048, _T_2898[146]) @[RegMapper.scala 187:66] + node _T_19050 = and(_T_19049, _T_2898[145]) @[RegMapper.scala 187:66] + node _T_19051 = and(_T_19050, _T_2898[144]) @[RegMapper.scala 187:66] + node _T_19052 = and(_T_19051, _T_2898[143]) @[RegMapper.scala 187:66] + node _T_19053 = and(_T_19052, _T_2898[142]) @[RegMapper.scala 187:66] + node _T_19054 = and(_T_19053, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[149] <= _T_19054 @[RegMapper.scala 187:18] + node _T_19055 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19056 = and(_T_19055, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19057 = and(_T_19056, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19058 = and(_T_19057, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19059 = and(_T_19058, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19060 = and(_T_19059, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19061 = and(_T_19060, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19062 = and(_T_19061, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[150] <= _T_19062 @[RegMapper.scala 184:18] + node _T_19063 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19064 = and(_T_19063, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19065 = and(_T_19064, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19066 = and(_T_19065, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19067 = and(_T_19066, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19068 = and(_T_19067, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19069 = and(_T_19068, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19070 = and(_T_19069, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[150] <= _T_19070 @[RegMapper.scala 185:18] + node _T_19071 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19072 = and(_T_19071, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19073 = and(_T_19072, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19074 = and(_T_19073, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19075 = and(_T_19074, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19076 = and(_T_19075, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19077 = and(_T_19076, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19078 = and(_T_19077, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[150] <= _T_19078 @[RegMapper.scala 186:18] + node _T_19079 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19080 = and(_T_19079, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19081 = and(_T_19080, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19082 = and(_T_19081, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19083 = and(_T_19082, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19084 = and(_T_19083, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19085 = and(_T_19084, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19086 = and(_T_19085, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[150] <= _T_19086 @[RegMapper.scala 187:18] + node _T_19087 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19088 = and(_T_19087, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19089 = and(_T_19088, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19090 = and(_T_19089, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19091 = and(_T_19090, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19092 = and(_T_19091, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19093 = and(_T_19092, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19094 = and(_T_19093, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[151] <= _T_19094 @[RegMapper.scala 184:18] + node _T_19095 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19096 = and(_T_19095, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19097 = and(_T_19096, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19098 = and(_T_19097, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19099 = and(_T_19098, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19100 = and(_T_19099, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19101 = and(_T_19100, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19102 = and(_T_19101, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[151] <= _T_19102 @[RegMapper.scala 185:18] + node _T_19103 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19104 = and(_T_19103, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19105 = and(_T_19104, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19106 = and(_T_19105, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19107 = and(_T_19106, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19108 = and(_T_19107, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19109 = and(_T_19108, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19110 = and(_T_19109, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[151] <= _T_19110 @[RegMapper.scala 186:18] + node _T_19111 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19112 = and(_T_19111, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19113 = and(_T_19112, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19114 = and(_T_19113, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19115 = and(_T_19114, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19116 = and(_T_19115, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19117 = and(_T_19116, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19118 = and(_T_19117, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[151] <= _T_19118 @[RegMapper.scala 187:18] + node _T_19119 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19120 = and(_T_19119, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19121 = and(_T_19120, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19122 = and(_T_19121, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19123 = and(_T_19122, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19124 = and(_T_19123, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19125 = and(_T_19124, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19126 = and(_T_19125, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[152] <= _T_19126 @[RegMapper.scala 184:18] + node _T_19127 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19128 = and(_T_19127, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19129 = and(_T_19128, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19130 = and(_T_19129, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19131 = and(_T_19130, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19132 = and(_T_19131, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19133 = and(_T_19132, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19134 = and(_T_19133, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[152] <= _T_19134 @[RegMapper.scala 185:18] + node _T_19135 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19136 = and(_T_19135, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19137 = and(_T_19136, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19138 = and(_T_19137, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19139 = and(_T_19138, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19140 = and(_T_19139, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19141 = and(_T_19140, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19142 = and(_T_19141, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[152] <= _T_19142 @[RegMapper.scala 186:18] + node _T_19143 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19144 = and(_T_19143, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19145 = and(_T_19144, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19146 = and(_T_19145, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19147 = and(_T_19146, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19148 = and(_T_19147, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19149 = and(_T_19148, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19150 = and(_T_19149, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[152] <= _T_19150 @[RegMapper.scala 187:18] + node _T_19151 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19152 = and(_T_19151, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19153 = and(_T_19152, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19154 = and(_T_19153, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19155 = and(_T_19154, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19156 = and(_T_19155, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19157 = and(_T_19156, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19158 = and(_T_19157, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[153] <= _T_19158 @[RegMapper.scala 184:18] + node _T_19159 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19160 = and(_T_19159, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19161 = and(_T_19160, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19162 = and(_T_19161, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19163 = and(_T_19162, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19164 = and(_T_19163, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19165 = and(_T_19164, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19166 = and(_T_19165, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[153] <= _T_19166 @[RegMapper.scala 185:18] + node _T_19167 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19168 = and(_T_19167, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19169 = and(_T_19168, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19170 = and(_T_19169, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19171 = and(_T_19170, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19172 = and(_T_19171, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19173 = and(_T_19172, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19174 = and(_T_19173, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[153] <= _T_19174 @[RegMapper.scala 186:18] + node _T_19175 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19176 = and(_T_19175, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19177 = and(_T_19176, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19178 = and(_T_19177, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19179 = and(_T_19178, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19180 = and(_T_19179, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19181 = and(_T_19180, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19182 = and(_T_19181, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[153] <= _T_19182 @[RegMapper.scala 187:18] + node _T_19183 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19184 = and(_T_19183, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19185 = and(_T_19184, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19186 = and(_T_19185, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19187 = and(_T_19186, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19188 = and(_T_19187, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19189 = and(_T_19188, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19190 = and(_T_19189, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[154] <= _T_19190 @[RegMapper.scala 184:18] + node _T_19191 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19192 = and(_T_19191, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19193 = and(_T_19192, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19194 = and(_T_19193, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19195 = and(_T_19194, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19196 = and(_T_19195, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19197 = and(_T_19196, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19198 = and(_T_19197, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[154] <= _T_19198 @[RegMapper.scala 185:18] + node _T_19199 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19200 = and(_T_19199, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19201 = and(_T_19200, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19202 = and(_T_19201, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19203 = and(_T_19202, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19204 = and(_T_19203, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19205 = and(_T_19204, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19206 = and(_T_19205, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[154] <= _T_19206 @[RegMapper.scala 186:18] + node _T_19207 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19208 = and(_T_19207, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19209 = and(_T_19208, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19210 = and(_T_19209, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19211 = and(_T_19210, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19212 = and(_T_19211, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19213 = and(_T_19212, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19214 = and(_T_19213, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[154] <= _T_19214 @[RegMapper.scala 187:18] + node _T_19215 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19216 = and(_T_19215, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19217 = and(_T_19216, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19218 = and(_T_19217, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19219 = and(_T_19218, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19220 = and(_T_19219, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19221 = and(_T_19220, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19222 = and(_T_19221, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[155] <= _T_19222 @[RegMapper.scala 184:18] + node _T_19223 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19224 = and(_T_19223, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19225 = and(_T_19224, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19226 = and(_T_19225, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19227 = and(_T_19226, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19228 = and(_T_19227, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19229 = and(_T_19228, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19230 = and(_T_19229, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[155] <= _T_19230 @[RegMapper.scala 185:18] + node _T_19231 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19232 = and(_T_19231, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19233 = and(_T_19232, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19234 = and(_T_19233, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19235 = and(_T_19234, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19236 = and(_T_19235, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19237 = and(_T_19236, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19238 = and(_T_19237, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[155] <= _T_19238 @[RegMapper.scala 186:18] + node _T_19239 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19240 = and(_T_19239, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19241 = and(_T_19240, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19242 = and(_T_19241, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19243 = and(_T_19242, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19244 = and(_T_19243, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19245 = and(_T_19244, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19246 = and(_T_19245, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[155] <= _T_19246 @[RegMapper.scala 187:18] + node _T_19247 = and(_T_13778, _T_2334[157]) @[RegMapper.scala 184:66] + node _T_19248 = and(_T_19247, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19249 = and(_T_19248, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19250 = and(_T_19249, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19251 = and(_T_19250, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19252 = and(_T_19251, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19253 = and(_T_19252, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19254 = and(_T_19253, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[156] <= _T_19254 @[RegMapper.scala 184:18] + node _T_19255 = and(_T_13784, _T_2522[157]) @[RegMapper.scala 185:66] + node _T_19256 = and(_T_19255, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19257 = and(_T_19256, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19258 = and(_T_19257, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19259 = and(_T_19258, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19260 = and(_T_19259, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19261 = and(_T_19260, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19262 = and(_T_19261, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[156] <= _T_19262 @[RegMapper.scala 185:18] + node _T_19263 = and(_T_13788, _T_2710[157]) @[RegMapper.scala 186:66] + node _T_19264 = and(_T_19263, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19265 = and(_T_19264, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19266 = and(_T_19265, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19267 = and(_T_19266, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19268 = and(_T_19267, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19269 = and(_T_19268, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19270 = and(_T_19269, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[156] <= _T_19270 @[RegMapper.scala 186:18] + node _T_19271 = and(_T_13794, _T_2898[157]) @[RegMapper.scala 187:66] + node _T_19272 = and(_T_19271, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19273 = and(_T_19272, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19274 = and(_T_19273, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19275 = and(_T_19274, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19276 = and(_T_19275, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19277 = and(_T_19276, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19278 = and(_T_19277, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[156] <= _T_19278 @[RegMapper.scala 187:18] + node _T_19279 = and(_T_13778, _T_2334[156]) @[RegMapper.scala 184:66] + node _T_19280 = and(_T_19279, _T_2334[155]) @[RegMapper.scala 184:66] + node _T_19281 = and(_T_19280, _T_2334[154]) @[RegMapper.scala 184:66] + node _T_19282 = and(_T_19281, _T_2334[153]) @[RegMapper.scala 184:66] + node _T_19283 = and(_T_19282, _T_2334[152]) @[RegMapper.scala 184:66] + node _T_19284 = and(_T_19283, _T_2334[151]) @[RegMapper.scala 184:66] + node _T_19285 = and(_T_19284, _T_2334[150]) @[RegMapper.scala 184:66] + node _T_19286 = and(_T_19285, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[157] <= _T_19286 @[RegMapper.scala 184:18] + node _T_19287 = and(_T_13784, _T_2522[156]) @[RegMapper.scala 185:66] + node _T_19288 = and(_T_19287, _T_2522[155]) @[RegMapper.scala 185:66] + node _T_19289 = and(_T_19288, _T_2522[154]) @[RegMapper.scala 185:66] + node _T_19290 = and(_T_19289, _T_2522[153]) @[RegMapper.scala 185:66] + node _T_19291 = and(_T_19290, _T_2522[152]) @[RegMapper.scala 185:66] + node _T_19292 = and(_T_19291, _T_2522[151]) @[RegMapper.scala 185:66] + node _T_19293 = and(_T_19292, _T_2522[150]) @[RegMapper.scala 185:66] + node _T_19294 = and(_T_19293, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[157] <= _T_19294 @[RegMapper.scala 185:18] + node _T_19295 = and(_T_13788, _T_2710[156]) @[RegMapper.scala 186:66] + node _T_19296 = and(_T_19295, _T_2710[155]) @[RegMapper.scala 186:66] + node _T_19297 = and(_T_19296, _T_2710[154]) @[RegMapper.scala 186:66] + node _T_19298 = and(_T_19297, _T_2710[153]) @[RegMapper.scala 186:66] + node _T_19299 = and(_T_19298, _T_2710[152]) @[RegMapper.scala 186:66] + node _T_19300 = and(_T_19299, _T_2710[151]) @[RegMapper.scala 186:66] + node _T_19301 = and(_T_19300, _T_2710[150]) @[RegMapper.scala 186:66] + node _T_19302 = and(_T_19301, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[157] <= _T_19302 @[RegMapper.scala 186:18] + node _T_19303 = and(_T_13794, _T_2898[156]) @[RegMapper.scala 187:66] + node _T_19304 = and(_T_19303, _T_2898[155]) @[RegMapper.scala 187:66] + node _T_19305 = and(_T_19304, _T_2898[154]) @[RegMapper.scala 187:66] + node _T_19306 = and(_T_19305, _T_2898[153]) @[RegMapper.scala 187:66] + node _T_19307 = and(_T_19306, _T_2898[152]) @[RegMapper.scala 187:66] + node _T_19308 = and(_T_19307, _T_2898[151]) @[RegMapper.scala 187:66] + node _T_19309 = and(_T_19308, _T_2898[150]) @[RegMapper.scala 187:66] + node _T_19310 = and(_T_19309, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[157] <= _T_19310 @[RegMapper.scala 187:18] + node _T_19311 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19312 = and(_T_19311, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19313 = and(_T_19312, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19314 = and(_T_19313, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19315 = and(_T_19314, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19316 = and(_T_19315, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19317 = and(_T_19316, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19318 = and(_T_19317, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[158] <= _T_19318 @[RegMapper.scala 184:18] + node _T_19319 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19320 = and(_T_19319, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19321 = and(_T_19320, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19322 = and(_T_19321, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19323 = and(_T_19322, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19324 = and(_T_19323, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19325 = and(_T_19324, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19326 = and(_T_19325, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[158] <= _T_19326 @[RegMapper.scala 185:18] + node _T_19327 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19328 = and(_T_19327, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19329 = and(_T_19328, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19330 = and(_T_19329, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19331 = and(_T_19330, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19332 = and(_T_19331, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19333 = and(_T_19332, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19334 = and(_T_19333, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[158] <= _T_19334 @[RegMapper.scala 186:18] + node _T_19335 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19336 = and(_T_19335, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19337 = and(_T_19336, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19338 = and(_T_19337, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19339 = and(_T_19338, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19340 = and(_T_19339, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19341 = and(_T_19340, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19342 = and(_T_19341, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[158] <= _T_19342 @[RegMapper.scala 187:18] + node _T_19343 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19344 = and(_T_19343, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19345 = and(_T_19344, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19346 = and(_T_19345, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19347 = and(_T_19346, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19348 = and(_T_19347, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19349 = and(_T_19348, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19350 = and(_T_19349, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[159] <= _T_19350 @[RegMapper.scala 184:18] + node _T_19351 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19352 = and(_T_19351, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19353 = and(_T_19352, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19354 = and(_T_19353, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19355 = and(_T_19354, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19356 = and(_T_19355, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19357 = and(_T_19356, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19358 = and(_T_19357, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[159] <= _T_19358 @[RegMapper.scala 185:18] + node _T_19359 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19360 = and(_T_19359, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19361 = and(_T_19360, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19362 = and(_T_19361, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19363 = and(_T_19362, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19364 = and(_T_19363, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19365 = and(_T_19364, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19366 = and(_T_19365, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[159] <= _T_19366 @[RegMapper.scala 186:18] + node _T_19367 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19368 = and(_T_19367, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19369 = and(_T_19368, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19370 = and(_T_19369, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19371 = and(_T_19370, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19372 = and(_T_19371, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19373 = and(_T_19372, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19374 = and(_T_19373, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[159] <= _T_19374 @[RegMapper.scala 187:18] + node _T_19375 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19376 = and(_T_19375, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19377 = and(_T_19376, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19378 = and(_T_19377, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19379 = and(_T_19378, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19380 = and(_T_19379, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19381 = and(_T_19380, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19382 = and(_T_19381, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[160] <= _T_19382 @[RegMapper.scala 184:18] + node _T_19383 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19384 = and(_T_19383, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19385 = and(_T_19384, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19386 = and(_T_19385, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19387 = and(_T_19386, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19388 = and(_T_19387, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19389 = and(_T_19388, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19390 = and(_T_19389, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[160] <= _T_19390 @[RegMapper.scala 185:18] + node _T_19391 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19392 = and(_T_19391, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19393 = and(_T_19392, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19394 = and(_T_19393, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19395 = and(_T_19394, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19396 = and(_T_19395, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19397 = and(_T_19396, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19398 = and(_T_19397, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[160] <= _T_19398 @[RegMapper.scala 186:18] + node _T_19399 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19400 = and(_T_19399, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19401 = and(_T_19400, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19402 = and(_T_19401, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19403 = and(_T_19402, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19404 = and(_T_19403, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19405 = and(_T_19404, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19406 = and(_T_19405, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[160] <= _T_19406 @[RegMapper.scala 187:18] + node _T_19407 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19408 = and(_T_19407, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19409 = and(_T_19408, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19410 = and(_T_19409, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19411 = and(_T_19410, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19412 = and(_T_19411, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19413 = and(_T_19412, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19414 = and(_T_19413, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[161] <= _T_19414 @[RegMapper.scala 184:18] + node _T_19415 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19416 = and(_T_19415, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19417 = and(_T_19416, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19418 = and(_T_19417, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19419 = and(_T_19418, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19420 = and(_T_19419, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19421 = and(_T_19420, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19422 = and(_T_19421, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[161] <= _T_19422 @[RegMapper.scala 185:18] + node _T_19423 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19424 = and(_T_19423, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19425 = and(_T_19424, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19426 = and(_T_19425, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19427 = and(_T_19426, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19428 = and(_T_19427, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19429 = and(_T_19428, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19430 = and(_T_19429, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[161] <= _T_19430 @[RegMapper.scala 186:18] + node _T_19431 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19432 = and(_T_19431, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19433 = and(_T_19432, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19434 = and(_T_19433, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19435 = and(_T_19434, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19436 = and(_T_19435, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19437 = and(_T_19436, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19438 = and(_T_19437, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[161] <= _T_19438 @[RegMapper.scala 187:18] + node _T_19439 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19440 = and(_T_19439, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19441 = and(_T_19440, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19442 = and(_T_19441, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19443 = and(_T_19442, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19444 = and(_T_19443, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19445 = and(_T_19444, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19446 = and(_T_19445, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[162] <= _T_19446 @[RegMapper.scala 184:18] + node _T_19447 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19448 = and(_T_19447, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19449 = and(_T_19448, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19450 = and(_T_19449, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19451 = and(_T_19450, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19452 = and(_T_19451, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19453 = and(_T_19452, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19454 = and(_T_19453, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[162] <= _T_19454 @[RegMapper.scala 185:18] + node _T_19455 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19456 = and(_T_19455, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19457 = and(_T_19456, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19458 = and(_T_19457, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19459 = and(_T_19458, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19460 = and(_T_19459, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19461 = and(_T_19460, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19462 = and(_T_19461, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[162] <= _T_19462 @[RegMapper.scala 186:18] + node _T_19463 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19464 = and(_T_19463, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19465 = and(_T_19464, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19466 = and(_T_19465, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19467 = and(_T_19466, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19468 = and(_T_19467, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19469 = and(_T_19468, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19470 = and(_T_19469, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[162] <= _T_19470 @[RegMapper.scala 187:18] + node _T_19471 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19472 = and(_T_19471, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19473 = and(_T_19472, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19474 = and(_T_19473, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19475 = and(_T_19474, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19476 = and(_T_19475, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19477 = and(_T_19476, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19478 = and(_T_19477, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[163] <= _T_19478 @[RegMapper.scala 184:18] + node _T_19479 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19480 = and(_T_19479, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19481 = and(_T_19480, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19482 = and(_T_19481, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19483 = and(_T_19482, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19484 = and(_T_19483, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19485 = and(_T_19484, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19486 = and(_T_19485, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[163] <= _T_19486 @[RegMapper.scala 185:18] + node _T_19487 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19488 = and(_T_19487, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19489 = and(_T_19488, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19490 = and(_T_19489, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19491 = and(_T_19490, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19492 = and(_T_19491, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19493 = and(_T_19492, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19494 = and(_T_19493, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[163] <= _T_19494 @[RegMapper.scala 186:18] + node _T_19495 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19496 = and(_T_19495, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19497 = and(_T_19496, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19498 = and(_T_19497, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19499 = and(_T_19498, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19500 = and(_T_19499, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19501 = and(_T_19500, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19502 = and(_T_19501, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[163] <= _T_19502 @[RegMapper.scala 187:18] + node _T_19503 = and(_T_13858, _T_2334[165]) @[RegMapper.scala 184:66] + node _T_19504 = and(_T_19503, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19505 = and(_T_19504, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19506 = and(_T_19505, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19507 = and(_T_19506, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19508 = and(_T_19507, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19509 = and(_T_19508, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19510 = and(_T_19509, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[164] <= _T_19510 @[RegMapper.scala 184:18] + node _T_19511 = and(_T_13864, _T_2522[165]) @[RegMapper.scala 185:66] + node _T_19512 = and(_T_19511, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19513 = and(_T_19512, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19514 = and(_T_19513, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19515 = and(_T_19514, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19516 = and(_T_19515, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19517 = and(_T_19516, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19518 = and(_T_19517, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[164] <= _T_19518 @[RegMapper.scala 185:18] + node _T_19519 = and(_T_13868, _T_2710[165]) @[RegMapper.scala 186:66] + node _T_19520 = and(_T_19519, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19521 = and(_T_19520, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19522 = and(_T_19521, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19523 = and(_T_19522, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19524 = and(_T_19523, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19525 = and(_T_19524, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19526 = and(_T_19525, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[164] <= _T_19526 @[RegMapper.scala 186:18] + node _T_19527 = and(_T_13874, _T_2898[165]) @[RegMapper.scala 187:66] + node _T_19528 = and(_T_19527, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19529 = and(_T_19528, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19530 = and(_T_19529, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19531 = and(_T_19530, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19532 = and(_T_19531, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19533 = and(_T_19532, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19534 = and(_T_19533, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[164] <= _T_19534 @[RegMapper.scala 187:18] + node _T_19535 = and(_T_13858, _T_2334[164]) @[RegMapper.scala 184:66] + node _T_19536 = and(_T_19535, _T_2334[163]) @[RegMapper.scala 184:66] + node _T_19537 = and(_T_19536, _T_2334[162]) @[RegMapper.scala 184:66] + node _T_19538 = and(_T_19537, _T_2334[161]) @[RegMapper.scala 184:66] + node _T_19539 = and(_T_19538, _T_2334[160]) @[RegMapper.scala 184:66] + node _T_19540 = and(_T_19539, _T_2334[159]) @[RegMapper.scala 184:66] + node _T_19541 = and(_T_19540, _T_2334[158]) @[RegMapper.scala 184:66] + node _T_19542 = and(_T_19541, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[165] <= _T_19542 @[RegMapper.scala 184:18] + node _T_19543 = and(_T_13864, _T_2522[164]) @[RegMapper.scala 185:66] + node _T_19544 = and(_T_19543, _T_2522[163]) @[RegMapper.scala 185:66] + node _T_19545 = and(_T_19544, _T_2522[162]) @[RegMapper.scala 185:66] + node _T_19546 = and(_T_19545, _T_2522[161]) @[RegMapper.scala 185:66] + node _T_19547 = and(_T_19546, _T_2522[160]) @[RegMapper.scala 185:66] + node _T_19548 = and(_T_19547, _T_2522[159]) @[RegMapper.scala 185:66] + node _T_19549 = and(_T_19548, _T_2522[158]) @[RegMapper.scala 185:66] + node _T_19550 = and(_T_19549, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[165] <= _T_19550 @[RegMapper.scala 185:18] + node _T_19551 = and(_T_13868, _T_2710[164]) @[RegMapper.scala 186:66] + node _T_19552 = and(_T_19551, _T_2710[163]) @[RegMapper.scala 186:66] + node _T_19553 = and(_T_19552, _T_2710[162]) @[RegMapper.scala 186:66] + node _T_19554 = and(_T_19553, _T_2710[161]) @[RegMapper.scala 186:66] + node _T_19555 = and(_T_19554, _T_2710[160]) @[RegMapper.scala 186:66] + node _T_19556 = and(_T_19555, _T_2710[159]) @[RegMapper.scala 186:66] + node _T_19557 = and(_T_19556, _T_2710[158]) @[RegMapper.scala 186:66] + node _T_19558 = and(_T_19557, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[165] <= _T_19558 @[RegMapper.scala 186:18] + node _T_19559 = and(_T_13874, _T_2898[164]) @[RegMapper.scala 187:66] + node _T_19560 = and(_T_19559, _T_2898[163]) @[RegMapper.scala 187:66] + node _T_19561 = and(_T_19560, _T_2898[162]) @[RegMapper.scala 187:66] + node _T_19562 = and(_T_19561, _T_2898[161]) @[RegMapper.scala 187:66] + node _T_19563 = and(_T_19562, _T_2898[160]) @[RegMapper.scala 187:66] + node _T_19564 = and(_T_19563, _T_2898[159]) @[RegMapper.scala 187:66] + node _T_19565 = and(_T_19564, _T_2898[158]) @[RegMapper.scala 187:66] + node _T_19566 = and(_T_19565, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[165] <= _T_19566 @[RegMapper.scala 187:18] + node _T_19567 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19568 = and(_T_19567, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19569 = and(_T_19568, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19570 = and(_T_19569, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19571 = and(_T_19570, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19572 = and(_T_19571, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19573 = and(_T_19572, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19574 = and(_T_19573, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[166] <= _T_19574 @[RegMapper.scala 184:18] + node _T_19575 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19576 = and(_T_19575, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19577 = and(_T_19576, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19578 = and(_T_19577, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19579 = and(_T_19578, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19580 = and(_T_19579, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19581 = and(_T_19580, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19582 = and(_T_19581, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[166] <= _T_19582 @[RegMapper.scala 185:18] + node _T_19583 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19584 = and(_T_19583, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19585 = and(_T_19584, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19586 = and(_T_19585, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19587 = and(_T_19586, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19588 = and(_T_19587, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19589 = and(_T_19588, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19590 = and(_T_19589, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[166] <= _T_19590 @[RegMapper.scala 186:18] + node _T_19591 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19592 = and(_T_19591, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19593 = and(_T_19592, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19594 = and(_T_19593, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19595 = and(_T_19594, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19596 = and(_T_19595, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19597 = and(_T_19596, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19598 = and(_T_19597, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[166] <= _T_19598 @[RegMapper.scala 187:18] + node _T_19599 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19600 = and(_T_19599, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19601 = and(_T_19600, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19602 = and(_T_19601, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19603 = and(_T_19602, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19604 = and(_T_19603, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19605 = and(_T_19604, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19606 = and(_T_19605, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[167] <= _T_19606 @[RegMapper.scala 184:18] + node _T_19607 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19608 = and(_T_19607, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19609 = and(_T_19608, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19610 = and(_T_19609, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19611 = and(_T_19610, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19612 = and(_T_19611, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19613 = and(_T_19612, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19614 = and(_T_19613, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[167] <= _T_19614 @[RegMapper.scala 185:18] + node _T_19615 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19616 = and(_T_19615, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19617 = and(_T_19616, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19618 = and(_T_19617, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19619 = and(_T_19618, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19620 = and(_T_19619, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19621 = and(_T_19620, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19622 = and(_T_19621, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[167] <= _T_19622 @[RegMapper.scala 186:18] + node _T_19623 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19624 = and(_T_19623, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19625 = and(_T_19624, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19626 = and(_T_19625, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19627 = and(_T_19626, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19628 = and(_T_19627, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19629 = and(_T_19628, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19630 = and(_T_19629, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[167] <= _T_19630 @[RegMapper.scala 187:18] + node _T_19631 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19632 = and(_T_19631, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19633 = and(_T_19632, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19634 = and(_T_19633, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19635 = and(_T_19634, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19636 = and(_T_19635, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19637 = and(_T_19636, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19638 = and(_T_19637, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[168] <= _T_19638 @[RegMapper.scala 184:18] + node _T_19639 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19640 = and(_T_19639, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19641 = and(_T_19640, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19642 = and(_T_19641, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19643 = and(_T_19642, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19644 = and(_T_19643, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19645 = and(_T_19644, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19646 = and(_T_19645, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[168] <= _T_19646 @[RegMapper.scala 185:18] + node _T_19647 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19648 = and(_T_19647, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19649 = and(_T_19648, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19650 = and(_T_19649, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19651 = and(_T_19650, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19652 = and(_T_19651, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19653 = and(_T_19652, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19654 = and(_T_19653, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[168] <= _T_19654 @[RegMapper.scala 186:18] + node _T_19655 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19656 = and(_T_19655, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19657 = and(_T_19656, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19658 = and(_T_19657, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19659 = and(_T_19658, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19660 = and(_T_19659, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19661 = and(_T_19660, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19662 = and(_T_19661, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[168] <= _T_19662 @[RegMapper.scala 187:18] + node _T_19663 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19664 = and(_T_19663, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19665 = and(_T_19664, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19666 = and(_T_19665, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19667 = and(_T_19666, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19668 = and(_T_19667, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19669 = and(_T_19668, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19670 = and(_T_19669, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[169] <= _T_19670 @[RegMapper.scala 184:18] + node _T_19671 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19672 = and(_T_19671, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19673 = and(_T_19672, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19674 = and(_T_19673, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19675 = and(_T_19674, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19676 = and(_T_19675, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19677 = and(_T_19676, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19678 = and(_T_19677, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[169] <= _T_19678 @[RegMapper.scala 185:18] + node _T_19679 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19680 = and(_T_19679, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19681 = and(_T_19680, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19682 = and(_T_19681, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19683 = and(_T_19682, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19684 = and(_T_19683, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19685 = and(_T_19684, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19686 = and(_T_19685, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[169] <= _T_19686 @[RegMapper.scala 186:18] + node _T_19687 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19688 = and(_T_19687, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19689 = and(_T_19688, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19690 = and(_T_19689, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19691 = and(_T_19690, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19692 = and(_T_19691, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19693 = and(_T_19692, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19694 = and(_T_19693, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[169] <= _T_19694 @[RegMapper.scala 187:18] + node _T_19695 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19696 = and(_T_19695, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19697 = and(_T_19696, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19698 = and(_T_19697, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19699 = and(_T_19698, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19700 = and(_T_19699, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19701 = and(_T_19700, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19702 = and(_T_19701, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[170] <= _T_19702 @[RegMapper.scala 184:18] + node _T_19703 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19704 = and(_T_19703, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19705 = and(_T_19704, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19706 = and(_T_19705, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19707 = and(_T_19706, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19708 = and(_T_19707, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19709 = and(_T_19708, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19710 = and(_T_19709, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[170] <= _T_19710 @[RegMapper.scala 185:18] + node _T_19711 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19712 = and(_T_19711, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19713 = and(_T_19712, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19714 = and(_T_19713, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19715 = and(_T_19714, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19716 = and(_T_19715, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19717 = and(_T_19716, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19718 = and(_T_19717, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[170] <= _T_19718 @[RegMapper.scala 186:18] + node _T_19719 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19720 = and(_T_19719, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19721 = and(_T_19720, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19722 = and(_T_19721, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19723 = and(_T_19722, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19724 = and(_T_19723, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19725 = and(_T_19724, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19726 = and(_T_19725, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[170] <= _T_19726 @[RegMapper.scala 187:18] + node _T_19727 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19728 = and(_T_19727, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19729 = and(_T_19728, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19730 = and(_T_19729, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19731 = and(_T_19730, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19732 = and(_T_19731, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19733 = and(_T_19732, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19734 = and(_T_19733, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[171] <= _T_19734 @[RegMapper.scala 184:18] + node _T_19735 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19736 = and(_T_19735, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19737 = and(_T_19736, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19738 = and(_T_19737, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19739 = and(_T_19738, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19740 = and(_T_19739, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19741 = and(_T_19740, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19742 = and(_T_19741, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[171] <= _T_19742 @[RegMapper.scala 185:18] + node _T_19743 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19744 = and(_T_19743, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19745 = and(_T_19744, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19746 = and(_T_19745, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19747 = and(_T_19746, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19748 = and(_T_19747, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19749 = and(_T_19748, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19750 = and(_T_19749, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[171] <= _T_19750 @[RegMapper.scala 186:18] + node _T_19751 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19752 = and(_T_19751, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19753 = and(_T_19752, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19754 = and(_T_19753, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19755 = and(_T_19754, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19756 = and(_T_19755, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19757 = and(_T_19756, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19758 = and(_T_19757, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[171] <= _T_19758 @[RegMapper.scala 187:18] + node _T_19759 = and(_T_13978, _T_2334[173]) @[RegMapper.scala 184:66] + node _T_19760 = and(_T_19759, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19761 = and(_T_19760, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19762 = and(_T_19761, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19763 = and(_T_19762, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19764 = and(_T_19763, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19765 = and(_T_19764, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19766 = and(_T_19765, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[172] <= _T_19766 @[RegMapper.scala 184:18] + node _T_19767 = and(_T_13984, _T_2522[173]) @[RegMapper.scala 185:66] + node _T_19768 = and(_T_19767, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19769 = and(_T_19768, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19770 = and(_T_19769, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19771 = and(_T_19770, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19772 = and(_T_19771, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19773 = and(_T_19772, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19774 = and(_T_19773, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[172] <= _T_19774 @[RegMapper.scala 185:18] + node _T_19775 = and(_T_13988, _T_2710[173]) @[RegMapper.scala 186:66] + node _T_19776 = and(_T_19775, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19777 = and(_T_19776, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19778 = and(_T_19777, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19779 = and(_T_19778, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19780 = and(_T_19779, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19781 = and(_T_19780, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19782 = and(_T_19781, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[172] <= _T_19782 @[RegMapper.scala 186:18] + node _T_19783 = and(_T_13994, _T_2898[173]) @[RegMapper.scala 187:66] + node _T_19784 = and(_T_19783, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19785 = and(_T_19784, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19786 = and(_T_19785, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19787 = and(_T_19786, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19788 = and(_T_19787, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19789 = and(_T_19788, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19790 = and(_T_19789, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[172] <= _T_19790 @[RegMapper.scala 187:18] + node _T_19791 = and(_T_13978, _T_2334[172]) @[RegMapper.scala 184:66] + node _T_19792 = and(_T_19791, _T_2334[171]) @[RegMapper.scala 184:66] + node _T_19793 = and(_T_19792, _T_2334[170]) @[RegMapper.scala 184:66] + node _T_19794 = and(_T_19793, _T_2334[169]) @[RegMapper.scala 184:66] + node _T_19795 = and(_T_19794, _T_2334[168]) @[RegMapper.scala 184:66] + node _T_19796 = and(_T_19795, _T_2334[167]) @[RegMapper.scala 184:66] + node _T_19797 = and(_T_19796, _T_2334[166]) @[RegMapper.scala 184:66] + node _T_19798 = and(_T_19797, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[173] <= _T_19798 @[RegMapper.scala 184:18] + node _T_19799 = and(_T_13984, _T_2522[172]) @[RegMapper.scala 185:66] + node _T_19800 = and(_T_19799, _T_2522[171]) @[RegMapper.scala 185:66] + node _T_19801 = and(_T_19800, _T_2522[170]) @[RegMapper.scala 185:66] + node _T_19802 = and(_T_19801, _T_2522[169]) @[RegMapper.scala 185:66] + node _T_19803 = and(_T_19802, _T_2522[168]) @[RegMapper.scala 185:66] + node _T_19804 = and(_T_19803, _T_2522[167]) @[RegMapper.scala 185:66] + node _T_19805 = and(_T_19804, _T_2522[166]) @[RegMapper.scala 185:66] + node _T_19806 = and(_T_19805, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[173] <= _T_19806 @[RegMapper.scala 185:18] + node _T_19807 = and(_T_13988, _T_2710[172]) @[RegMapper.scala 186:66] + node _T_19808 = and(_T_19807, _T_2710[171]) @[RegMapper.scala 186:66] + node _T_19809 = and(_T_19808, _T_2710[170]) @[RegMapper.scala 186:66] + node _T_19810 = and(_T_19809, _T_2710[169]) @[RegMapper.scala 186:66] + node _T_19811 = and(_T_19810, _T_2710[168]) @[RegMapper.scala 186:66] + node _T_19812 = and(_T_19811, _T_2710[167]) @[RegMapper.scala 186:66] + node _T_19813 = and(_T_19812, _T_2710[166]) @[RegMapper.scala 186:66] + node _T_19814 = and(_T_19813, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[173] <= _T_19814 @[RegMapper.scala 186:18] + node _T_19815 = and(_T_13994, _T_2898[172]) @[RegMapper.scala 187:66] + node _T_19816 = and(_T_19815, _T_2898[171]) @[RegMapper.scala 187:66] + node _T_19817 = and(_T_19816, _T_2898[170]) @[RegMapper.scala 187:66] + node _T_19818 = and(_T_19817, _T_2898[169]) @[RegMapper.scala 187:66] + node _T_19819 = and(_T_19818, _T_2898[168]) @[RegMapper.scala 187:66] + node _T_19820 = and(_T_19819, _T_2898[167]) @[RegMapper.scala 187:66] + node _T_19821 = and(_T_19820, _T_2898[166]) @[RegMapper.scala 187:66] + node _T_19822 = and(_T_19821, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[173] <= _T_19822 @[RegMapper.scala 187:18] + node _T_19823 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19824 = and(_T_19823, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19825 = and(_T_19824, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_19826 = and(_T_19825, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_19827 = and(_T_19826, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_19828 = and(_T_19827, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_19829 = and(_T_19828, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_19830 = and(_T_19829, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[174] <= _T_19830 @[RegMapper.scala 184:18] + node _T_19831 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19832 = and(_T_19831, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19833 = and(_T_19832, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_19834 = and(_T_19833, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_19835 = and(_T_19834, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_19836 = and(_T_19835, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_19837 = and(_T_19836, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_19838 = and(_T_19837, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[174] <= _T_19838 @[RegMapper.scala 185:18] + node _T_19839 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_19840 = and(_T_19839, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_19841 = and(_T_19840, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_19842 = and(_T_19841, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_19843 = and(_T_19842, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_19844 = and(_T_19843, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_19845 = and(_T_19844, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_19846 = and(_T_19845, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[174] <= _T_19846 @[RegMapper.scala 186:18] + node _T_19847 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_19848 = and(_T_19847, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_19849 = and(_T_19848, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_19850 = and(_T_19849, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_19851 = and(_T_19850, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_19852 = and(_T_19851, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_19853 = and(_T_19852, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_19854 = and(_T_19853, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[174] <= _T_19854 @[RegMapper.scala 187:18] + node _T_19855 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19856 = and(_T_19855, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19857 = and(_T_19856, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_19858 = and(_T_19857, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_19859 = and(_T_19858, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_19860 = and(_T_19859, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_19861 = and(_T_19860, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_19862 = and(_T_19861, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[175] <= _T_19862 @[RegMapper.scala 184:18] + node _T_19863 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19864 = and(_T_19863, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19865 = and(_T_19864, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_19866 = and(_T_19865, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_19867 = and(_T_19866, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_19868 = and(_T_19867, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_19869 = and(_T_19868, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_19870 = and(_T_19869, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[175] <= _T_19870 @[RegMapper.scala 185:18] + node _T_19871 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_19872 = and(_T_19871, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_19873 = and(_T_19872, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_19874 = and(_T_19873, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_19875 = and(_T_19874, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_19876 = and(_T_19875, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_19877 = and(_T_19876, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_19878 = and(_T_19877, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[175] <= _T_19878 @[RegMapper.scala 186:18] + node _T_19879 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_19880 = and(_T_19879, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_19881 = and(_T_19880, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_19882 = and(_T_19881, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_19883 = and(_T_19882, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_19884 = and(_T_19883, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_19885 = and(_T_19884, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_19886 = and(_T_19885, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[175] <= _T_19886 @[RegMapper.scala 187:18] + node _T_19887 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19888 = and(_T_19887, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19889 = and(_T_19888, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_19890 = and(_T_19889, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_19891 = and(_T_19890, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_19892 = and(_T_19891, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_19893 = and(_T_19892, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_19894 = and(_T_19893, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[176] <= _T_19894 @[RegMapper.scala 184:18] + node _T_19895 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19896 = and(_T_19895, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19897 = and(_T_19896, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_19898 = and(_T_19897, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_19899 = and(_T_19898, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_19900 = and(_T_19899, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_19901 = and(_T_19900, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_19902 = and(_T_19901, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[176] <= _T_19902 @[RegMapper.scala 185:18] + node _T_19903 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_19904 = and(_T_19903, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_19905 = and(_T_19904, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_19906 = and(_T_19905, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_19907 = and(_T_19906, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_19908 = and(_T_19907, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_19909 = and(_T_19908, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_19910 = and(_T_19909, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[176] <= _T_19910 @[RegMapper.scala 186:18] + node _T_19911 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_19912 = and(_T_19911, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_19913 = and(_T_19912, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_19914 = and(_T_19913, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_19915 = and(_T_19914, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_19916 = and(_T_19915, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_19917 = and(_T_19916, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_19918 = and(_T_19917, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[176] <= _T_19918 @[RegMapper.scala 187:18] + node _T_19919 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19920 = and(_T_19919, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19921 = and(_T_19920, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_19922 = and(_T_19921, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_19923 = and(_T_19922, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_19924 = and(_T_19923, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_19925 = and(_T_19924, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_19926 = and(_T_19925, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[177] <= _T_19926 @[RegMapper.scala 184:18] + node _T_19927 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19928 = and(_T_19927, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19929 = and(_T_19928, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_19930 = and(_T_19929, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_19931 = and(_T_19930, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_19932 = and(_T_19931, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_19933 = and(_T_19932, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_19934 = and(_T_19933, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[177] <= _T_19934 @[RegMapper.scala 185:18] + node _T_19935 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_19936 = and(_T_19935, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_19937 = and(_T_19936, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_19938 = and(_T_19937, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_19939 = and(_T_19938, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_19940 = and(_T_19939, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_19941 = and(_T_19940, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_19942 = and(_T_19941, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[177] <= _T_19942 @[RegMapper.scala 186:18] + node _T_19943 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_19944 = and(_T_19943, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_19945 = and(_T_19944, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_19946 = and(_T_19945, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_19947 = and(_T_19946, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_19948 = and(_T_19947, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_19949 = and(_T_19948, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_19950 = and(_T_19949, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[177] <= _T_19950 @[RegMapper.scala 187:18] + node _T_19951 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19952 = and(_T_19951, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19953 = and(_T_19952, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_19954 = and(_T_19953, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_19955 = and(_T_19954, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_19956 = and(_T_19955, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_19957 = and(_T_19956, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_19958 = and(_T_19957, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[178] <= _T_19958 @[RegMapper.scala 184:18] + node _T_19959 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19960 = and(_T_19959, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19961 = and(_T_19960, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_19962 = and(_T_19961, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_19963 = and(_T_19962, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_19964 = and(_T_19963, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_19965 = and(_T_19964, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_19966 = and(_T_19965, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[178] <= _T_19966 @[RegMapper.scala 185:18] + node _T_19967 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_19968 = and(_T_19967, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_19969 = and(_T_19968, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_19970 = and(_T_19969, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_19971 = and(_T_19970, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_19972 = and(_T_19971, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_19973 = and(_T_19972, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_19974 = and(_T_19973, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[178] <= _T_19974 @[RegMapper.scala 186:18] + node _T_19975 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_19976 = and(_T_19975, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_19977 = and(_T_19976, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_19978 = and(_T_19977, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_19979 = and(_T_19978, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_19980 = and(_T_19979, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_19981 = and(_T_19980, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_19982 = and(_T_19981, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[178] <= _T_19982 @[RegMapper.scala 187:18] + node _T_19983 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_19984 = and(_T_19983, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_19985 = and(_T_19984, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_19986 = and(_T_19985, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_19987 = and(_T_19986, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_19988 = and(_T_19987, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_19989 = and(_T_19988, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_19990 = and(_T_19989, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[179] <= _T_19990 @[RegMapper.scala 184:18] + node _T_19991 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_19992 = and(_T_19991, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_19993 = and(_T_19992, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_19994 = and(_T_19993, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_19995 = and(_T_19994, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_19996 = and(_T_19995, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_19997 = and(_T_19996, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_19998 = and(_T_19997, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[179] <= _T_19998 @[RegMapper.scala 185:18] + node _T_19999 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_20000 = and(_T_19999, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_20001 = and(_T_20000, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_20002 = and(_T_20001, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_20003 = and(_T_20002, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_20004 = and(_T_20003, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_20005 = and(_T_20004, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_20006 = and(_T_20005, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[179] <= _T_20006 @[RegMapper.scala 186:18] + node _T_20007 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_20008 = and(_T_20007, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_20009 = and(_T_20008, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_20010 = and(_T_20009, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_20011 = and(_T_20010, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_20012 = and(_T_20011, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_20013 = and(_T_20012, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_20014 = and(_T_20013, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[179] <= _T_20014 @[RegMapper.scala 187:18] + node _T_20015 = and(_T_13158, _T_2334[181]) @[RegMapper.scala 184:66] + node _T_20016 = and(_T_20015, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_20017 = and(_T_20016, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_20018 = and(_T_20017, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_20019 = and(_T_20018, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_20020 = and(_T_20019, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_20021 = and(_T_20020, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_20022 = and(_T_20021, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[180] <= _T_20022 @[RegMapper.scala 184:18] + node _T_20023 = and(_T_13164, _T_2522[181]) @[RegMapper.scala 185:66] + node _T_20024 = and(_T_20023, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_20025 = and(_T_20024, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_20026 = and(_T_20025, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_20027 = and(_T_20026, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_20028 = and(_T_20027, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_20029 = and(_T_20028, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_20030 = and(_T_20029, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[180] <= _T_20030 @[RegMapper.scala 185:18] + node _T_20031 = and(_T_13168, _T_2710[181]) @[RegMapper.scala 186:66] + node _T_20032 = and(_T_20031, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_20033 = and(_T_20032, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_20034 = and(_T_20033, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_20035 = and(_T_20034, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_20036 = and(_T_20035, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_20037 = and(_T_20036, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_20038 = and(_T_20037, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[180] <= _T_20038 @[RegMapper.scala 186:18] + node _T_20039 = and(_T_13174, _T_2898[181]) @[RegMapper.scala 187:66] + node _T_20040 = and(_T_20039, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_20041 = and(_T_20040, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_20042 = and(_T_20041, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_20043 = and(_T_20042, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_20044 = and(_T_20043, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_20045 = and(_T_20044, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_20046 = and(_T_20045, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[180] <= _T_20046 @[RegMapper.scala 187:18] + node _T_20047 = and(_T_13158, _T_2334[180]) @[RegMapper.scala 184:66] + node _T_20048 = and(_T_20047, _T_2334[179]) @[RegMapper.scala 184:66] + node _T_20049 = and(_T_20048, _T_2334[178]) @[RegMapper.scala 184:66] + node _T_20050 = and(_T_20049, _T_2334[177]) @[RegMapper.scala 184:66] + node _T_20051 = and(_T_20050, _T_2334[176]) @[RegMapper.scala 184:66] + node _T_20052 = and(_T_20051, _T_2334[175]) @[RegMapper.scala 184:66] + node _T_20053 = and(_T_20052, _T_2334[174]) @[RegMapper.scala 184:66] + node _T_20054 = and(_T_20053, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1958[181] <= _T_20054 @[RegMapper.scala 184:18] + node _T_20055 = and(_T_13164, _T_2522[180]) @[RegMapper.scala 185:66] + node _T_20056 = and(_T_20055, _T_2522[179]) @[RegMapper.scala 185:66] + node _T_20057 = and(_T_20056, _T_2522[178]) @[RegMapper.scala 185:66] + node _T_20058 = and(_T_20057, _T_2522[177]) @[RegMapper.scala 185:66] + node _T_20059 = and(_T_20058, _T_2522[176]) @[RegMapper.scala 185:66] + node _T_20060 = and(_T_20059, _T_2522[175]) @[RegMapper.scala 185:66] + node _T_20061 = and(_T_20060, _T_2522[174]) @[RegMapper.scala 185:66] + node _T_20062 = and(_T_20061, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_2146[181] <= _T_20062 @[RegMapper.scala 185:18] + node _T_20063 = and(_T_13168, _T_2710[180]) @[RegMapper.scala 186:66] + node _T_20064 = and(_T_20063, _T_2710[179]) @[RegMapper.scala 186:66] + node _T_20065 = and(_T_20064, _T_2710[178]) @[RegMapper.scala 186:66] + node _T_20066 = and(_T_20065, _T_2710[177]) @[RegMapper.scala 186:66] + node _T_20067 = and(_T_20066, _T_2710[176]) @[RegMapper.scala 186:66] + node _T_20068 = and(_T_20067, _T_2710[175]) @[RegMapper.scala 186:66] + node _T_20069 = and(_T_20068, _T_2710[174]) @[RegMapper.scala 186:66] + node _T_20070 = and(_T_20069, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_3086[181] <= _T_20070 @[RegMapper.scala 186:18] + node _T_20071 = and(_T_13174, _T_2898[180]) @[RegMapper.scala 187:66] + node _T_20072 = and(_T_20071, _T_2898[179]) @[RegMapper.scala 187:66] + node _T_20073 = and(_T_20072, _T_2898[178]) @[RegMapper.scala 187:66] + node _T_20074 = and(_T_20073, _T_2898[177]) @[RegMapper.scala 187:66] + node _T_20075 = and(_T_20074, _T_2898[176]) @[RegMapper.scala 187:66] + node _T_20076 = and(_T_20075, _T_2898[175]) @[RegMapper.scala 187:66] + node _T_20077 = and(_T_20076, _T_2898[174]) @[RegMapper.scala 187:66] + node _T_20078 = and(_T_20077, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_3274[181] <= _T_20078 @[RegMapper.scala 187:18] + _T_1547.bits.read <= _T_1583.bits.read @[RegMapper.scala 190:20] + wire _T_20081 : UInt<1>[64] @[RegMapper.scala 191:30] + _T_20081 is invalid @[RegMapper.scala 191:30] + _T_20081[0] <= _T_1846 @[RegMapper.scala 191:30] + _T_20081[1] <= _T_1828 @[RegMapper.scala 191:30] + _T_20081[2] <= _T_1891 @[RegMapper.scala 191:30] + _T_20081[3] <= _T_1954 @[RegMapper.scala 191:30] + _T_20081[4] <= _T_1765 @[RegMapper.scala 191:30] + _T_20081[5] <= _T_1774 @[RegMapper.scala 191:30] + _T_20081[6] <= _T_1837 @[RegMapper.scala 191:30] + _T_20081[7] <= _T_1900 @[RegMapper.scala 191:30] + _T_20081[8] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[9] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[10] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[11] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[12] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[13] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[14] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[15] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[16] <= _T_1864 @[RegMapper.scala 191:30] + _T_20081[17] <= _T_1810 @[RegMapper.scala 191:30] + _T_20081[18] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[19] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[20] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[21] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[22] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[23] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[24] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[25] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[26] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[27] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[28] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[29] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[30] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[31] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[32] <= _T_1819 @[RegMapper.scala 191:30] + _T_20081[33] <= _T_1747 @[RegMapper.scala 191:30] + _T_20081[34] <= _T_1927 @[RegMapper.scala 191:30] + _T_20081[35] <= _T_1882 @[RegMapper.scala 191:30] + _T_20081[36] <= _T_1801 @[RegMapper.scala 191:30] + _T_20081[37] <= _T_1756 @[RegMapper.scala 191:30] + _T_20081[38] <= _T_1936 @[RegMapper.scala 191:30] + _T_20081[39] <= _T_1918 @[RegMapper.scala 191:30] + _T_20081[40] <= _T_1873 @[RegMapper.scala 191:30] + _T_20081[41] <= _T_1783 @[RegMapper.scala 191:30] + _T_20081[42] <= _T_1855 @[RegMapper.scala 191:30] + _T_20081[43] <= _T_1909 @[RegMapper.scala 191:30] + _T_20081[44] <= _T_1945 @[RegMapper.scala 191:30] + _T_20081[45] <= _T_1738 @[RegMapper.scala 191:30] + _T_20081[46] <= _T_1792 @[RegMapper.scala 191:30] + _T_20081[47] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[48] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[49] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[50] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[51] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[52] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[53] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[54] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[55] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[56] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[57] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[58] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[59] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[60] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[61] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[62] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_20081[63] <= UInt<1>("h01") @[RegMapper.scala 191:30] + wire _T_20151 : UInt<64>[64] @[RegMapper.scala 191:54] + _T_20151 is invalid @[RegMapper.scala 191:54] + _T_20151[0] <= _T_7592 @[RegMapper.scala 191:54] + _T_20151[1] <= _T_6952 @[RegMapper.scala 191:54] + _T_20151[2] <= _T_8912 @[RegMapper.scala 191:54] + _T_20151[3] <= _T_11152 @[RegMapper.scala 191:54] + _T_20151[4] <= _T_5152 @[RegMapper.scala 191:54] + _T_20151[5] <= _T_5472 @[RegMapper.scala 191:54] + _T_20151[6] <= _T_7272 @[RegMapper.scala 191:54] + _T_20151[7] <= _T_9232 @[RegMapper.scala 191:54] + _T_20151[8] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[9] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[10] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[11] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[12] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[13] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[14] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[15] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[16] <= _T_7952 @[RegMapper.scala 191:54] + _T_20151[17] <= _T_6312 @[RegMapper.scala 191:54] + _T_20151[18] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[19] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[20] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[21] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[22] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[23] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[24] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[25] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[26] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[27] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[28] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[29] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[30] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[31] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[32] <= _T_6632 @[RegMapper.scala 191:54] + _T_20151[33] <= _T_4512 @[RegMapper.scala 191:54] + _T_20151[34] <= _T_10192 @[RegMapper.scala 191:54] + _T_20151[35] <= _T_8592 @[RegMapper.scala 191:54] + _T_20151[36] <= _T_6272 @[RegMapper.scala 191:54] + _T_20151[37] <= _T_4832 @[RegMapper.scala 191:54] + _T_20151[38] <= _T_10512 @[RegMapper.scala 191:54] + _T_20151[39] <= _T_9872 @[RegMapper.scala 191:54] + _T_20151[40] <= _T_8272 @[RegMapper.scala 191:54] + _T_20151[41] <= _T_5792 @[RegMapper.scala 191:54] + _T_20151[42] <= _T_7912 @[RegMapper.scala 191:54] + _T_20151[43] <= _T_9552 @[RegMapper.scala 191:54] + _T_20151[44] <= _T_10832 @[RegMapper.scala 191:54] + _T_20151[45] <= _T_4192 @[RegMapper.scala 191:54] + _T_20151[46] <= _T_5952 @[RegMapper.scala 191:54] + _T_20151[47] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[48] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[49] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[50] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[51] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[52] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[53] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[54] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[55] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[56] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[57] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[58] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[59] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[60] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[61] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[62] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_20151[63] <= UInt<1>("h00") @[RegMapper.scala 191:54] + node _T_20220 = mux(_T_20081[_T_12952], _T_20151[_T_12952], UInt<1>("h00")) @[RegMapper.scala 191:26] + _T_1547.bits.data <= _T_20220 @[RegMapper.scala 191:20] + _T_1547.bits.extra <= _T_1583.bits.extra @[RegMapper.scala 192:20] + _T_1507.valid <= io.in.0.a.valid @[RegisterRouter.scala 58:15] + io.in.0.a.ready <= _T_1507.ready @[RegisterRouter.scala 59:15] + io.in.0.d.valid <= _T_1547.valid @[RegisterRouter.scala 60:15] + _T_1547.ready <= io.in.0.d.ready @[RegisterRouter.scala 61:15] + node _T_20221 = bits(_T_1547.bits.extra, 11, 9) @[RegisterRouter.scala 65:35] + node _T_20223 = bits(_T_1547.bits.extra, 8, 3) @[RegisterRouter.scala 67:35] + node _T_20224 = bits(_T_1547.bits.extra, 2, 0) @[RegisterRouter.scala 68:35] + wire _T_20235 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_20235 is invalid @[Edges.scala 617:17] + _T_20235.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_20235.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_20235.size <= _T_20224 @[Edges.scala 620:15] + _T_20235.source <= _T_20223 @[Edges.scala 621:15] + _T_20235.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_20246 = bits(_T_20221, 2, 0) @[Edges.scala 172:47] + _T_20235.addr_lo <= _T_20246 @[Edges.scala 623:15] + _T_20235.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_20235.error <= UInt<1>("h00") @[Edges.scala 625:15] + io.in.0.d.bits <- _T_20235 @[RegisterRouter.scala 64:12] + io.in.0.d.bits.data <= _T_1547.bits.data @[RegisterRouter.scala 71:17] + node _T_20250 = mux(_T_1547.bits.read, UInt<1>("h01"), UInt<1>("h00")) @[RegisterRouter.scala 72:25] + io.in.0.d.bits.opcode <= _T_20250 @[RegisterRouter.scala 72:19] + io.in.0.b.valid <= UInt<1>("h00") @[RegisterRouter.scala 75:25] + io.in.0.c.ready <= UInt<1>("h01") @[RegisterRouter.scala 76:25] + io.in.0.e.ready <= UInt<1>("h01") @[RegisterRouter.scala 77:25] + node _T_20255 = neq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 842:33] + io.ndreset <= _T_20255 @[Debug.scala 842:16] + io.fullreset <= CONTROLReg.fullreset @[Debug.scala 843:16] + + module LevelGateway : + input clock : Clock + input reset : UInt<1> + output io : {flip interrupt : UInt<1>, plic : {valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} + + io is invalid + io is invalid + reg inFlight : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Plic.scala 28:21] + node _T_12 = and(io.interrupt, io.plic.ready) @[Plic.scala 29:22] + when _T_12 : @[Plic.scala 29:40] + inFlight <= UInt<1>("h01") @[Plic.scala 29:51] + skip @[Plic.scala 29:40] + when io.plic.complete : @[Plic.scala 30:27] + inFlight <= UInt<1>("h00") @[Plic.scala 30:38] + skip @[Plic.scala 30:27] + node _T_16 = eq(inFlight, UInt<1>("h00")) @[Plic.scala 31:36] + node _T_17 = and(io.interrupt, _T_16) @[Plic.scala 31:33] + io.plic.valid <= _T_17 @[Plic.scala 31:17] + + module LevelGateway_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip interrupt : UInt<1>, plic : {valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} + + io is invalid + io is invalid + reg inFlight : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Plic.scala 28:21] + node _T_12 = and(io.interrupt, io.plic.ready) @[Plic.scala 29:22] + when _T_12 : @[Plic.scala 29:40] + inFlight <= UInt<1>("h01") @[Plic.scala 29:51] + skip @[Plic.scala 29:40] + when io.plic.complete : @[Plic.scala 30:27] + inFlight <= UInt<1>("h00") @[Plic.scala 30:38] + skip @[Plic.scala 30:27] + node _T_16 = eq(inFlight, UInt<1>("h00")) @[Plic.scala 31:36] + node _T_17 = and(io.interrupt, _T_16) @[Plic.scala 31:33] + io.plic.valid <= _T_17 @[Plic.scala 31:17] + + module TLPLIC_plic : + input clock : Clock + input reset : UInt<1> + output io : {flip tl_in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, flip devices : {0 : UInt<1>[2]}, harts : {1 : UInt<1>[1], 0 : UInt<1>[1]}} + + io is invalid + io is invalid + inst LevelGateway of LevelGateway @[Plic.scala 131:27] + LevelGateway.io is invalid + LevelGateway.clock <= clock + LevelGateway.reset <= reset + LevelGateway.io.interrupt <= io.devices.0[0] @[Plic.scala 132:28] + inst LevelGateway_1 of LevelGateway_1 @[Plic.scala 131:27] + LevelGateway_1.io is invalid + LevelGateway_1.clock <= clock + LevelGateway_1.reset <= reset + LevelGateway_1.io.interrupt <= io.devices.0[1] @[Plic.scala 132:28] + wire gateways : {valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}[2] @[Plic.scala 130:23] + gateways is invalid @[Plic.scala 130:23] + gateways[0] <- LevelGateway.io.plic @[Plic.scala 130:23] + gateways[1] <- LevelGateway_1.io.plic @[Plic.scala 130:23] + reg priority : UInt<2>[3], clock @[Plic.scala 137:31] + reg threshold : UInt<2>[2], clock @[Plic.scala 140:31] + wire _T_451 : UInt<1>[3] @[Plic.scala 142:48] + _T_451 is invalid @[Plic.scala 142:48] + _T_451[0] <= UInt<1>("h00") @[Plic.scala 142:48] + _T_451[1] <= UInt<1>("h00") @[Plic.scala 142:48] + _T_451[2] <= UInt<1>("h00") @[Plic.scala 142:48] + reg pending : UInt<1>[3], clock with : (reset => (reset, _T_451)) @[Plic.scala 142:22] + reg enables : UInt<1>[3][2], clock @[Plic.scala 143:22] + node _T_533 = eq(pending[1], UInt<1>("h00")) @[Plic.scala 146:18] + gateways[0].ready <= _T_533 @[Plic.scala 146:15] + gateways[0].complete <= UInt<1>("h00") @[Plic.scala 147:18] + when gateways[0].valid : @[Plic.scala 148:22] + pending[1] <= UInt<1>("h01") @[Plic.scala 148:26] + skip @[Plic.scala 148:22] + node _T_537 = eq(pending[2], UInt<1>("h00")) @[Plic.scala 146:18] + gateways[1].ready <= _T_537 @[Plic.scala 146:15] + gateways[1].complete <= UInt<1>("h00") @[Plic.scala 147:18] + when gateways[1].valid : @[Plic.scala 148:22] + pending[2] <= UInt<1>("h01") @[Plic.scala 148:26] + skip @[Plic.scala 148:22] + reg maxDevs : UInt<2>[2], clock @[Plic.scala 161:22] + node _T_547 = and(pending[1], enables[0][1]) @[Plic.scala 165:23] + node _T_548 = cat(_T_547, priority[1]) @[Cat.scala 30:58] + node _T_549 = and(pending[2], enables[0][2]) @[Plic.scala 165:23] + node _T_550 = cat(_T_549, priority[2]) @[Cat.scala 30:58] + node _T_552 = shl(UInt<1>("h01"), 2) @[Plic.scala 166:47] + node _T_555 = geq(_T_552, _T_548) @[Plic.scala 156:31] + node _T_556 = mux(_T_555, _T_552, _T_548) @[Plic.scala 157:13] + node _T_558 = or(UInt<1>("h01"), UInt<1>("h00")) @[Plic.scala 157:75] + node _T_559 = mux(_T_555, UInt<1>("h00"), _T_558) @[Plic.scala 157:45] + node _T_561 = geq(_T_556, _T_550) @[Plic.scala 156:31] + node _T_562 = mux(_T_561, _T_556, _T_550) @[Plic.scala 157:13] + node _T_564 = or(UInt<2>("h02"), UInt<1>("h00")) @[Plic.scala 157:75] + node _T_565 = mux(_T_561, _T_559, _T_564) @[Plic.scala 157:45] + maxDevs[0] <= _T_565 @[Plic.scala 168:21] + reg _T_566 : UInt, clock @[Plic.scala 169:25] + _T_566 <= _T_562 @[Plic.scala 169:25] + node _T_568 = cat(UInt<1>("h01"), threshold[0]) @[Cat.scala 30:58] + node _T_569 = gt(_T_566, _T_568) @[Plic.scala 169:41] + io.harts.0[0] <= _T_569 @[Plic.scala 169:19] + node _T_570 = and(pending[1], enables[1][1]) @[Plic.scala 165:23] + node _T_571 = cat(_T_570, priority[1]) @[Cat.scala 30:58] + node _T_572 = and(pending[2], enables[1][2]) @[Plic.scala 165:23] + node _T_573 = cat(_T_572, priority[2]) @[Cat.scala 30:58] + node _T_575 = shl(UInt<1>("h01"), 2) @[Plic.scala 166:47] + node _T_578 = geq(_T_575, _T_571) @[Plic.scala 156:31] + node _T_579 = mux(_T_578, _T_575, _T_571) @[Plic.scala 157:13] + node _T_581 = or(UInt<1>("h01"), UInt<1>("h00")) @[Plic.scala 157:75] + node _T_582 = mux(_T_578, UInt<1>("h00"), _T_581) @[Plic.scala 157:45] + node _T_584 = geq(_T_579, _T_573) @[Plic.scala 156:31] + node _T_585 = mux(_T_584, _T_579, _T_573) @[Plic.scala 157:13] + node _T_587 = or(UInt<2>("h02"), UInt<1>("h00")) @[Plic.scala 157:75] + node _T_588 = mux(_T_584, _T_582, _T_587) @[Plic.scala 157:45] + maxDevs[1] <= _T_588 @[Plic.scala 168:21] + reg _T_589 : UInt, clock @[Plic.scala 169:25] + _T_589 <= _T_585 @[Plic.scala 169:25] + node _T_591 = cat(UInt<1>("h01"), threshold[1]) @[Cat.scala 30:58] + node _T_592 = gt(_T_589, _T_591) @[Plic.scala 169:41] + io.harts.1[0] <= _T_592 @[Plic.scala 169:19] + wire _T_616 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegisterRouter.scala 47:18] + _T_616 is invalid @[RegisterRouter.scala 47:18] + node _T_634 = eq(io.tl_in.0.a.bits.opcode, UInt<3>("h04")) @[RegisterRouter.scala 48:36] + _T_616.bits.read <= _T_634 @[RegisterRouter.scala 48:19] + node _T_635 = shr(io.tl_in.0.a.bits.address, 3) @[Edges.scala 170:34] + _T_616.bits.index <= _T_635 @[RegisterRouter.scala 49:19] + _T_616.bits.data <= io.tl_in.0.a.bits.data @[RegisterRouter.scala 50:19] + _T_616.bits.mask <= io.tl_in.0.a.bits.mask @[RegisterRouter.scala 51:19] + node _T_636 = bits(io.tl_in.0.a.bits.address, 2, 0) @[Edges.scala 172:47] + node _T_637 = cat(_T_636, io.tl_in.0.a.bits.source) @[Cat.scala 30:58] + node _T_638 = cat(_T_637, io.tl_in.0.a.bits.size) @[Cat.scala 30:58] + _T_616.bits.extra <= _T_638 @[RegisterRouter.scala 52:19] + wire _T_656 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, data : UInt<64>, extra : UInt<12>}} @[RegMapper.scala 56:19] + _T_656 is invalid @[RegMapper.scala 56:19] + wire _T_692 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegMapper.scala 57:21] + _T_692 is invalid @[RegMapper.scala 57:21] + _T_692.bits <- _T_616.bits @[RegMapper.scala 58:16] + node _T_710 = not(UInt<23>("h04061f")) @[RegMapper.scala 74:21] + wire _T_1233 : UInt<1>[16] @[RegMapper.scala 107:23] + _T_1233 is invalid @[RegMapper.scala 107:23] + wire _T_1255 : UInt<1>[16] @[RegMapper.scala 108:23] + _T_1255 is invalid @[RegMapper.scala 108:23] + wire _T_1277 : UInt<1>[16] @[RegMapper.scala 109:23] + _T_1277 is invalid @[RegMapper.scala 109:23] + wire _T_1299 : UInt<1>[16] @[RegMapper.scala 110:23] + _T_1299 is invalid @[RegMapper.scala 110:23] + wire _T_1321 : UInt<1>[16] @[RegMapper.scala 111:23] + _T_1321 is invalid @[RegMapper.scala 111:23] + wire _T_1343 : UInt<1>[16] @[RegMapper.scala 112:23] + _T_1343 is invalid @[RegMapper.scala 112:23] + wire _T_1365 : UInt<1>[16] @[RegMapper.scala 113:23] + _T_1365 is invalid @[RegMapper.scala 113:23] + wire _T_1387 : UInt<1>[16] @[RegMapper.scala 114:23] + _T_1387 is invalid @[RegMapper.scala 114:23] + node _T_2686 = bits(_T_692.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_2687 = bits(_T_692.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_2688 = bits(_T_692.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_2689 = bits(_T_692.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_2690 = bits(_T_692.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_2691 = bits(_T_692.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_2692 = bits(_T_692.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_2693 = bits(_T_692.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_2694 = bits(_T_2686, 0, 0) @[Bitwise.scala 71:15] + node _T_2697 = mux(_T_2694, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2698 = bits(_T_2687, 0, 0) @[Bitwise.scala 71:15] + node _T_2701 = mux(_T_2698, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2702 = bits(_T_2688, 0, 0) @[Bitwise.scala 71:15] + node _T_2705 = mux(_T_2702, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2706 = bits(_T_2689, 0, 0) @[Bitwise.scala 71:15] + node _T_2709 = mux(_T_2706, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2710 = bits(_T_2690, 0, 0) @[Bitwise.scala 71:15] + node _T_2713 = mux(_T_2710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2714 = bits(_T_2691, 0, 0) @[Bitwise.scala 71:15] + node _T_2717 = mux(_T_2714, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2718 = bits(_T_2692, 0, 0) @[Bitwise.scala 71:15] + node _T_2721 = mux(_T_2718, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2722 = bits(_T_2693, 0, 0) @[Bitwise.scala 71:15] + node _T_2725 = mux(_T_2722, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2726 = cat(_T_2701, _T_2697) @[Cat.scala 30:58] + node _T_2727 = cat(_T_2709, _T_2705) @[Cat.scala 30:58] + node _T_2728 = cat(_T_2727, _T_2726) @[Cat.scala 30:58] + node _T_2729 = cat(_T_2717, _T_2713) @[Cat.scala 30:58] + node _T_2730 = cat(_T_2725, _T_2721) @[Cat.scala 30:58] + node _T_2731 = cat(_T_2730, _T_2729) @[Cat.scala 30:58] + node _T_2732 = cat(_T_2731, _T_2728) @[Cat.scala 30:58] + node _T_2733 = bits(_T_692.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_2734 = bits(_T_692.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_2735 = bits(_T_692.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_2736 = bits(_T_692.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_2737 = bits(_T_692.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_2738 = bits(_T_692.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_2739 = bits(_T_692.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_2740 = bits(_T_692.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_2741 = bits(_T_2733, 0, 0) @[Bitwise.scala 71:15] + node _T_2744 = mux(_T_2741, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2745 = bits(_T_2734, 0, 0) @[Bitwise.scala 71:15] + node _T_2748 = mux(_T_2745, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2749 = bits(_T_2735, 0, 0) @[Bitwise.scala 71:15] + node _T_2752 = mux(_T_2749, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2753 = bits(_T_2736, 0, 0) @[Bitwise.scala 71:15] + node _T_2756 = mux(_T_2753, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2757 = bits(_T_2737, 0, 0) @[Bitwise.scala 71:15] + node _T_2760 = mux(_T_2757, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2761 = bits(_T_2738, 0, 0) @[Bitwise.scala 71:15] + node _T_2764 = mux(_T_2761, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2765 = bits(_T_2739, 0, 0) @[Bitwise.scala 71:15] + node _T_2768 = mux(_T_2765, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2769 = bits(_T_2740, 0, 0) @[Bitwise.scala 71:15] + node _T_2772 = mux(_T_2769, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_2773 = cat(_T_2748, _T_2744) @[Cat.scala 30:58] + node _T_2774 = cat(_T_2756, _T_2752) @[Cat.scala 30:58] + node _T_2775 = cat(_T_2774, _T_2773) @[Cat.scala 30:58] + node _T_2776 = cat(_T_2764, _T_2760) @[Cat.scala 30:58] + node _T_2777 = cat(_T_2772, _T_2768) @[Cat.scala 30:58] + node _T_2778 = cat(_T_2777, _T_2776) @[Cat.scala 30:58] + node _T_2779 = cat(_T_2778, _T_2775) @[Cat.scala 30:58] + node _T_2780 = bits(_T_2732, 0, 0) @[RegMapper.scala 135:29] + node _T_2782 = neq(_T_2780, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2783 = bits(_T_2732, 0, 0) @[RegMapper.scala 136:29] + node _T_2784 = not(_T_2783) @[RegMapper.scala 136:45] + node _T_2786 = eq(_T_2784, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2787 = bits(_T_2779, 0, 0) @[RegMapper.scala 137:28] + node _T_2789 = neq(_T_2787, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2790 = bits(_T_2779, 0, 0) @[RegMapper.scala 138:28] + node _T_2791 = not(_T_2790) @[RegMapper.scala 138:44] + node _T_2793 = eq(_T_2791, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2794 = and(_T_1233[0], _T_2782) @[RegMapper.scala 140:69] + node _T_2795 = and(_T_1365[0], _T_2789) @[RegMapper.scala 140:91] + node _T_2798 = and(_T_1255[0], _T_2786) @[RegMapper.scala 141:62] + node _T_2799 = and(_T_1387[0], _T_2793) @[RegMapper.scala 141:84] + node _T_2800 = bits(_T_692.bits.data, 0, 0) @[RegMapper.scala 141:99] + when _T_2799 : @[RegField.scala 70:88] + enables[0][0] <= _T_2800 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_2804 = eq(_T_2782, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_2805 = or(UInt<1>("h01"), _T_2804) @[RegMapper.scala 142:31] + _T_1277[0] <= _T_2805 @[RegMapper.scala 142:18] + node _T_2807 = eq(_T_2786, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_2808 = or(UInt<1>("h01"), _T_2807) @[RegMapper.scala 143:31] + _T_1299[0] <= _T_2808 @[RegMapper.scala 143:18] + node _T_2810 = eq(_T_2789, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_2811 = or(UInt<1>("h01"), _T_2810) @[RegMapper.scala 144:31] + _T_1321[0] <= _T_2811 @[RegMapper.scala 144:18] + node _T_2813 = eq(_T_2793, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_2814 = or(UInt<1>("h01"), _T_2813) @[RegMapper.scala 145:31] + _T_1343[0] <= _T_2814 @[RegMapper.scala 145:18] + node _T_2815 = shl(enables[0][0], 0) @[RegMapper.scala 150:47] + node _T_2817 = not(UInt<1>("h00")) @[RegMapper.scala 150:58] + node _T_2818 = and(_T_2815, _T_2817) @[RegMapper.scala 150:55] + node _T_2819 = or(UInt<1>("h00"), _T_2818) @[RegMapper.scala 150:35] + node _T_2820 = bits(_T_2732, 1, 1) @[RegMapper.scala 135:29] + node _T_2822 = neq(_T_2820, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2823 = bits(_T_2732, 1, 1) @[RegMapper.scala 136:29] + node _T_2824 = not(_T_2823) @[RegMapper.scala 136:45] + node _T_2826 = eq(_T_2824, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2827 = bits(_T_2779, 1, 1) @[RegMapper.scala 137:28] + node _T_2829 = neq(_T_2827, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2830 = bits(_T_2779, 1, 1) @[RegMapper.scala 138:28] + node _T_2831 = not(_T_2830) @[RegMapper.scala 138:44] + node _T_2833 = eq(_T_2831, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2834 = and(_T_1233[1], _T_2822) @[RegMapper.scala 140:69] + node _T_2835 = and(_T_1365[1], _T_2829) @[RegMapper.scala 140:91] + node _T_2838 = and(_T_1255[1], _T_2826) @[RegMapper.scala 141:62] + node _T_2839 = and(_T_1387[1], _T_2833) @[RegMapper.scala 141:84] + node _T_2840 = bits(_T_692.bits.data, 1, 1) @[RegMapper.scala 141:99] + when _T_2839 : @[RegField.scala 70:88] + enables[0][1] <= _T_2840 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_2844 = eq(_T_2822, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_2845 = or(UInt<1>("h01"), _T_2844) @[RegMapper.scala 142:31] + _T_1277[1] <= _T_2845 @[RegMapper.scala 142:18] + node _T_2847 = eq(_T_2826, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_2848 = or(UInt<1>("h01"), _T_2847) @[RegMapper.scala 143:31] + _T_1299[1] <= _T_2848 @[RegMapper.scala 143:18] + node _T_2850 = eq(_T_2829, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_2851 = or(UInt<1>("h01"), _T_2850) @[RegMapper.scala 144:31] + _T_1321[1] <= _T_2851 @[RegMapper.scala 144:18] + node _T_2853 = eq(_T_2833, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_2854 = or(UInt<1>("h01"), _T_2853) @[RegMapper.scala 145:31] + _T_1343[1] <= _T_2854 @[RegMapper.scala 145:18] + node _T_2855 = shl(enables[0][1], 1) @[RegMapper.scala 150:47] + node _T_2857 = not(UInt<2>("h00")) @[RegMapper.scala 150:58] + node _T_2858 = and(_T_2855, _T_2857) @[RegMapper.scala 150:55] + node _T_2859 = or(_T_2819, _T_2858) @[RegMapper.scala 150:35] + node _T_2860 = bits(_T_2732, 2, 2) @[RegMapper.scala 135:29] + node _T_2862 = neq(_T_2860, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2863 = bits(_T_2732, 2, 2) @[RegMapper.scala 136:29] + node _T_2864 = not(_T_2863) @[RegMapper.scala 136:45] + node _T_2866 = eq(_T_2864, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2867 = bits(_T_2779, 2, 2) @[RegMapper.scala 137:28] + node _T_2869 = neq(_T_2867, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2870 = bits(_T_2779, 2, 2) @[RegMapper.scala 138:28] + node _T_2871 = not(_T_2870) @[RegMapper.scala 138:44] + node _T_2873 = eq(_T_2871, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2874 = and(_T_1233[2], _T_2862) @[RegMapper.scala 140:69] + node _T_2875 = and(_T_1365[2], _T_2869) @[RegMapper.scala 140:91] + node _T_2878 = and(_T_1255[2], _T_2866) @[RegMapper.scala 141:62] + node _T_2879 = and(_T_1387[2], _T_2873) @[RegMapper.scala 141:84] + node _T_2880 = bits(_T_692.bits.data, 2, 2) @[RegMapper.scala 141:99] + when _T_2879 : @[RegField.scala 70:88] + enables[0][2] <= _T_2880 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_2884 = eq(_T_2862, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_2885 = or(UInt<1>("h01"), _T_2884) @[RegMapper.scala 142:31] + _T_1277[2] <= _T_2885 @[RegMapper.scala 142:18] + node _T_2887 = eq(_T_2866, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_2888 = or(UInt<1>("h01"), _T_2887) @[RegMapper.scala 143:31] + _T_1299[2] <= _T_2888 @[RegMapper.scala 143:18] + node _T_2890 = eq(_T_2869, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_2891 = or(UInt<1>("h01"), _T_2890) @[RegMapper.scala 144:31] + _T_1321[2] <= _T_2891 @[RegMapper.scala 144:18] + node _T_2893 = eq(_T_2873, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_2894 = or(UInt<1>("h01"), _T_2893) @[RegMapper.scala 145:31] + _T_1343[2] <= _T_2894 @[RegMapper.scala 145:18] + node _T_2895 = shl(enables[0][2], 2) @[RegMapper.scala 150:47] + node _T_2897 = not(UInt<3>("h00")) @[RegMapper.scala 150:58] + node _T_2898 = and(_T_2895, _T_2897) @[RegMapper.scala 150:55] + node _T_2899 = or(_T_2859, _T_2898) @[RegMapper.scala 150:35] + node _T_2900 = bits(_T_2732, 31, 0) @[RegMapper.scala 135:29] + node _T_2902 = neq(_T_2900, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2903 = bits(_T_2732, 31, 0) @[RegMapper.scala 136:29] + node _T_2904 = not(_T_2903) @[RegMapper.scala 136:45] + node _T_2906 = eq(_T_2904, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2907 = bits(_T_2779, 31, 0) @[RegMapper.scala 137:28] + node _T_2909 = neq(_T_2907, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2910 = bits(_T_2779, 31, 0) @[RegMapper.scala 138:28] + node _T_2911 = not(_T_2910) @[RegMapper.scala 138:44] + node _T_2913 = eq(_T_2911, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2914 = and(_T_1233[3], _T_2902) @[RegMapper.scala 140:69] + node _T_2915 = and(_T_1365[3], _T_2909) @[RegMapper.scala 140:91] + node _T_2918 = and(_T_1255[3], _T_2906) @[RegMapper.scala 141:62] + node _T_2919 = and(_T_1387[3], _T_2913) @[RegMapper.scala 141:84] + node _T_2920 = bits(_T_692.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_2919 : @[RegField.scala 70:88] + priority[0] <= _T_2920 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_2924 = eq(_T_2902, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_2925 = or(UInt<1>("h01"), _T_2924) @[RegMapper.scala 142:31] + _T_1277[3] <= _T_2925 @[RegMapper.scala 142:18] + node _T_2927 = eq(_T_2906, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_2928 = or(UInt<1>("h01"), _T_2927) @[RegMapper.scala 143:31] + _T_1299[3] <= _T_2928 @[RegMapper.scala 143:18] + node _T_2930 = eq(_T_2909, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_2931 = or(UInt<1>("h01"), _T_2930) @[RegMapper.scala 144:31] + _T_1321[3] <= _T_2931 @[RegMapper.scala 144:18] + node _T_2933 = eq(_T_2913, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_2934 = or(UInt<1>("h01"), _T_2933) @[RegMapper.scala 145:31] + _T_1343[3] <= _T_2934 @[RegMapper.scala 145:18] + node _T_2935 = shl(priority[0], 0) @[RegMapper.scala 150:47] + node _T_2937 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_2938 = and(_T_2935, _T_2937) @[RegMapper.scala 150:55] + node _T_2939 = or(UInt<1>("h00"), _T_2938) @[RegMapper.scala 150:35] + node _T_2940 = bits(_T_2732, 63, 32) @[RegMapper.scala 135:29] + node _T_2942 = neq(_T_2940, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2943 = bits(_T_2732, 63, 32) @[RegMapper.scala 136:29] + node _T_2944 = not(_T_2943) @[RegMapper.scala 136:45] + node _T_2946 = eq(_T_2944, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2947 = bits(_T_2779, 63, 32) @[RegMapper.scala 137:28] + node _T_2949 = neq(_T_2947, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2950 = bits(_T_2779, 63, 32) @[RegMapper.scala 138:28] + node _T_2951 = not(_T_2950) @[RegMapper.scala 138:44] + node _T_2953 = eq(_T_2951, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2954 = and(_T_1233[4], _T_2942) @[RegMapper.scala 140:69] + node _T_2955 = and(_T_1365[4], _T_2949) @[RegMapper.scala 140:91] + node _T_2958 = and(_T_1255[4], _T_2946) @[RegMapper.scala 141:62] + node _T_2959 = and(_T_1387[4], _T_2953) @[RegMapper.scala 141:84] + node _T_2960 = bits(_T_692.bits.data, 63, 32) @[RegMapper.scala 141:99] + when _T_2959 : @[RegField.scala 70:88] + priority[1] <= _T_2960 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_2964 = eq(_T_2942, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_2965 = or(UInt<1>("h01"), _T_2964) @[RegMapper.scala 142:31] + _T_1277[4] <= _T_2965 @[RegMapper.scala 142:18] + node _T_2967 = eq(_T_2946, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_2968 = or(UInt<1>("h01"), _T_2967) @[RegMapper.scala 143:31] + _T_1299[4] <= _T_2968 @[RegMapper.scala 143:18] + node _T_2970 = eq(_T_2949, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_2971 = or(UInt<1>("h01"), _T_2970) @[RegMapper.scala 144:31] + _T_1321[4] <= _T_2971 @[RegMapper.scala 144:18] + node _T_2973 = eq(_T_2953, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_2974 = or(UInt<1>("h01"), _T_2973) @[RegMapper.scala 145:31] + _T_1343[4] <= _T_2974 @[RegMapper.scala 145:18] + node _T_2975 = shl(priority[1], 32) @[RegMapper.scala 150:47] + node _T_2977 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_2978 = and(_T_2975, _T_2977) @[RegMapper.scala 150:55] + node _T_2979 = or(_T_2939, _T_2978) @[RegMapper.scala 150:35] + node _T_2980 = bits(_T_2732, 0, 0) @[RegMapper.scala 135:29] + node _T_2982 = neq(_T_2980, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_2983 = bits(_T_2732, 0, 0) @[RegMapper.scala 136:29] + node _T_2984 = not(_T_2983) @[RegMapper.scala 136:45] + node _T_2986 = eq(_T_2984, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_2987 = bits(_T_2779, 0, 0) @[RegMapper.scala 137:28] + node _T_2989 = neq(_T_2987, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_2990 = bits(_T_2779, 0, 0) @[RegMapper.scala 138:28] + node _T_2991 = not(_T_2990) @[RegMapper.scala 138:44] + node _T_2993 = eq(_T_2991, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_2994 = and(_T_1233[5], _T_2982) @[RegMapper.scala 140:69] + node _T_2995 = and(_T_1365[5], _T_2989) @[RegMapper.scala 140:91] + node _T_2998 = and(_T_1255[5], _T_2986) @[RegMapper.scala 141:62] + node _T_2999 = and(_T_1387[5], _T_2993) @[RegMapper.scala 141:84] + node _T_3000 = bits(_T_692.bits.data, 0, 0) @[RegMapper.scala 141:99] + when _T_2999 : @[RegField.scala 70:88] + enables[1][0] <= _T_3000 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3004 = eq(_T_2982, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3005 = or(UInt<1>("h01"), _T_3004) @[RegMapper.scala 142:31] + _T_1277[5] <= _T_3005 @[RegMapper.scala 142:18] + node _T_3007 = eq(_T_2986, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3008 = or(UInt<1>("h01"), _T_3007) @[RegMapper.scala 143:31] + _T_1299[5] <= _T_3008 @[RegMapper.scala 143:18] + node _T_3010 = eq(_T_2989, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3011 = or(UInt<1>("h01"), _T_3010) @[RegMapper.scala 144:31] + _T_1321[5] <= _T_3011 @[RegMapper.scala 144:18] + node _T_3013 = eq(_T_2993, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3014 = or(UInt<1>("h01"), _T_3013) @[RegMapper.scala 145:31] + _T_1343[5] <= _T_3014 @[RegMapper.scala 145:18] + node _T_3015 = shl(enables[1][0], 0) @[RegMapper.scala 150:47] + node _T_3017 = not(UInt<1>("h00")) @[RegMapper.scala 150:58] + node _T_3018 = and(_T_3015, _T_3017) @[RegMapper.scala 150:55] + node _T_3019 = or(UInt<1>("h00"), _T_3018) @[RegMapper.scala 150:35] + node _T_3020 = bits(_T_2732, 1, 1) @[RegMapper.scala 135:29] + node _T_3022 = neq(_T_3020, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3023 = bits(_T_2732, 1, 1) @[RegMapper.scala 136:29] + node _T_3024 = not(_T_3023) @[RegMapper.scala 136:45] + node _T_3026 = eq(_T_3024, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3027 = bits(_T_2779, 1, 1) @[RegMapper.scala 137:28] + node _T_3029 = neq(_T_3027, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3030 = bits(_T_2779, 1, 1) @[RegMapper.scala 138:28] + node _T_3031 = not(_T_3030) @[RegMapper.scala 138:44] + node _T_3033 = eq(_T_3031, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3034 = and(_T_1233[6], _T_3022) @[RegMapper.scala 140:69] + node _T_3035 = and(_T_1365[6], _T_3029) @[RegMapper.scala 140:91] + node _T_3038 = and(_T_1255[6], _T_3026) @[RegMapper.scala 141:62] + node _T_3039 = and(_T_1387[6], _T_3033) @[RegMapper.scala 141:84] + node _T_3040 = bits(_T_692.bits.data, 1, 1) @[RegMapper.scala 141:99] + when _T_3039 : @[RegField.scala 70:88] + enables[1][1] <= _T_3040 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3044 = eq(_T_3022, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3045 = or(UInt<1>("h01"), _T_3044) @[RegMapper.scala 142:31] + _T_1277[6] <= _T_3045 @[RegMapper.scala 142:18] + node _T_3047 = eq(_T_3026, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3048 = or(UInt<1>("h01"), _T_3047) @[RegMapper.scala 143:31] + _T_1299[6] <= _T_3048 @[RegMapper.scala 143:18] + node _T_3050 = eq(_T_3029, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3051 = or(UInt<1>("h01"), _T_3050) @[RegMapper.scala 144:31] + _T_1321[6] <= _T_3051 @[RegMapper.scala 144:18] + node _T_3053 = eq(_T_3033, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3054 = or(UInt<1>("h01"), _T_3053) @[RegMapper.scala 145:31] + _T_1343[6] <= _T_3054 @[RegMapper.scala 145:18] + node _T_3055 = shl(enables[1][1], 1) @[RegMapper.scala 150:47] + node _T_3057 = not(UInt<2>("h00")) @[RegMapper.scala 150:58] + node _T_3058 = and(_T_3055, _T_3057) @[RegMapper.scala 150:55] + node _T_3059 = or(_T_3019, _T_3058) @[RegMapper.scala 150:35] + node _T_3060 = bits(_T_2732, 2, 2) @[RegMapper.scala 135:29] + node _T_3062 = neq(_T_3060, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3063 = bits(_T_2732, 2, 2) @[RegMapper.scala 136:29] + node _T_3064 = not(_T_3063) @[RegMapper.scala 136:45] + node _T_3066 = eq(_T_3064, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3067 = bits(_T_2779, 2, 2) @[RegMapper.scala 137:28] + node _T_3069 = neq(_T_3067, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3070 = bits(_T_2779, 2, 2) @[RegMapper.scala 138:28] + node _T_3071 = not(_T_3070) @[RegMapper.scala 138:44] + node _T_3073 = eq(_T_3071, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3074 = and(_T_1233[7], _T_3062) @[RegMapper.scala 140:69] + node _T_3075 = and(_T_1365[7], _T_3069) @[RegMapper.scala 140:91] + node _T_3078 = and(_T_1255[7], _T_3066) @[RegMapper.scala 141:62] + node _T_3079 = and(_T_1387[7], _T_3073) @[RegMapper.scala 141:84] + node _T_3080 = bits(_T_692.bits.data, 2, 2) @[RegMapper.scala 141:99] + when _T_3079 : @[RegField.scala 70:88] + enables[1][2] <= _T_3080 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3084 = eq(_T_3062, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3085 = or(UInt<1>("h01"), _T_3084) @[RegMapper.scala 142:31] + _T_1277[7] <= _T_3085 @[RegMapper.scala 142:18] + node _T_3087 = eq(_T_3066, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3088 = or(UInt<1>("h01"), _T_3087) @[RegMapper.scala 143:31] + _T_1299[7] <= _T_3088 @[RegMapper.scala 143:18] + node _T_3090 = eq(_T_3069, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3091 = or(UInt<1>("h01"), _T_3090) @[RegMapper.scala 144:31] + _T_1321[7] <= _T_3091 @[RegMapper.scala 144:18] + node _T_3093 = eq(_T_3073, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3094 = or(UInt<1>("h01"), _T_3093) @[RegMapper.scala 145:31] + _T_1343[7] <= _T_3094 @[RegMapper.scala 145:18] + node _T_3095 = shl(enables[1][2], 2) @[RegMapper.scala 150:47] + node _T_3097 = not(UInt<3>("h00")) @[RegMapper.scala 150:58] + node _T_3098 = and(_T_3095, _T_3097) @[RegMapper.scala 150:55] + node _T_3099 = or(_T_3059, _T_3098) @[RegMapper.scala 150:35] + node _T_3100 = bits(_T_2732, 31, 0) @[RegMapper.scala 135:29] + node _T_3102 = neq(_T_3100, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3103 = bits(_T_2732, 31, 0) @[RegMapper.scala 136:29] + node _T_3104 = not(_T_3103) @[RegMapper.scala 136:45] + node _T_3106 = eq(_T_3104, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3107 = bits(_T_2779, 31, 0) @[RegMapper.scala 137:28] + node _T_3109 = neq(_T_3107, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3110 = bits(_T_2779, 31, 0) @[RegMapper.scala 138:28] + node _T_3111 = not(_T_3110) @[RegMapper.scala 138:44] + node _T_3113 = eq(_T_3111, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3114 = and(_T_1233[8], _T_3102) @[RegMapper.scala 140:69] + node _T_3115 = and(_T_1365[8], _T_3109) @[RegMapper.scala 140:91] + node _T_3118 = and(_T_1255[8], _T_3106) @[RegMapper.scala 141:62] + node _T_3119 = and(_T_1387[8], _T_3113) @[RegMapper.scala 141:84] + node _T_3120 = bits(_T_692.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_3119 : @[RegField.scala 70:88] + priority[2] <= _T_3120 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3124 = eq(_T_3102, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3125 = or(UInt<1>("h01"), _T_3124) @[RegMapper.scala 142:31] + _T_1277[8] <= _T_3125 @[RegMapper.scala 142:18] + node _T_3127 = eq(_T_3106, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3128 = or(UInt<1>("h01"), _T_3127) @[RegMapper.scala 143:31] + _T_1299[8] <= _T_3128 @[RegMapper.scala 143:18] + node _T_3130 = eq(_T_3109, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3131 = or(UInt<1>("h01"), _T_3130) @[RegMapper.scala 144:31] + _T_1321[8] <= _T_3131 @[RegMapper.scala 144:18] + node _T_3133 = eq(_T_3113, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3134 = or(UInt<1>("h01"), _T_3133) @[RegMapper.scala 145:31] + _T_1343[8] <= _T_3134 @[RegMapper.scala 145:18] + node _T_3135 = shl(priority[2], 0) @[RegMapper.scala 150:47] + node _T_3137 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_3138 = and(_T_3135, _T_3137) @[RegMapper.scala 150:55] + node _T_3139 = or(UInt<1>("h00"), _T_3138) @[RegMapper.scala 150:35] + node _T_3140 = bits(_T_2732, 0, 0) @[RegMapper.scala 135:29] + node _T_3142 = neq(_T_3140, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3143 = bits(_T_2732, 0, 0) @[RegMapper.scala 136:29] + node _T_3144 = not(_T_3143) @[RegMapper.scala 136:45] + node _T_3146 = eq(_T_3144, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3147 = bits(_T_2779, 0, 0) @[RegMapper.scala 137:28] + node _T_3149 = neq(_T_3147, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3150 = bits(_T_2779, 0, 0) @[RegMapper.scala 138:28] + node _T_3151 = not(_T_3150) @[RegMapper.scala 138:44] + node _T_3153 = eq(_T_3151, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3154 = and(_T_1233[9], _T_3142) @[RegMapper.scala 140:69] + node _T_3155 = and(_T_1365[9], _T_3149) @[RegMapper.scala 140:91] + node _T_3158 = and(_T_1255[9], _T_3146) @[RegMapper.scala 141:62] + node _T_3159 = and(_T_1387[9], _T_3153) @[RegMapper.scala 141:84] + node _T_3160 = bits(_T_692.bits.data, 0, 0) @[RegMapper.scala 141:99] + node _T_3164 = eq(_T_3142, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3165 = or(UInt<1>("h01"), _T_3164) @[RegMapper.scala 142:31] + _T_1277[9] <= _T_3165 @[RegMapper.scala 142:18] + node _T_3167 = eq(_T_3146, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3168 = or(UInt<1>("h01"), _T_3167) @[RegMapper.scala 143:31] + _T_1299[9] <= _T_3168 @[RegMapper.scala 143:18] + node _T_3170 = eq(_T_3149, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3171 = or(UInt<1>("h01"), _T_3170) @[RegMapper.scala 144:31] + _T_1321[9] <= _T_3171 @[RegMapper.scala 144:18] + node _T_3173 = eq(_T_3153, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3174 = or(UInt<1>("h01"), _T_3173) @[RegMapper.scala 145:31] + _T_1343[9] <= _T_3174 @[RegMapper.scala 145:18] + node _T_3175 = shl(pending[0], 0) @[RegMapper.scala 150:47] + node _T_3177 = not(UInt<1>("h00")) @[RegMapper.scala 150:58] + node _T_3178 = and(_T_3175, _T_3177) @[RegMapper.scala 150:55] + node _T_3179 = or(UInt<1>("h00"), _T_3178) @[RegMapper.scala 150:35] + node _T_3180 = bits(_T_2732, 1, 1) @[RegMapper.scala 135:29] + node _T_3182 = neq(_T_3180, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3183 = bits(_T_2732, 1, 1) @[RegMapper.scala 136:29] + node _T_3184 = not(_T_3183) @[RegMapper.scala 136:45] + node _T_3186 = eq(_T_3184, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3187 = bits(_T_2779, 1, 1) @[RegMapper.scala 137:28] + node _T_3189 = neq(_T_3187, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3190 = bits(_T_2779, 1, 1) @[RegMapper.scala 138:28] + node _T_3191 = not(_T_3190) @[RegMapper.scala 138:44] + node _T_3193 = eq(_T_3191, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3194 = and(_T_1233[10], _T_3182) @[RegMapper.scala 140:69] + node _T_3195 = and(_T_1365[10], _T_3189) @[RegMapper.scala 140:91] + node _T_3198 = and(_T_1255[10], _T_3186) @[RegMapper.scala 141:62] + node _T_3199 = and(_T_1387[10], _T_3193) @[RegMapper.scala 141:84] + node _T_3200 = bits(_T_692.bits.data, 1, 1) @[RegMapper.scala 141:99] + node _T_3204 = eq(_T_3182, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3205 = or(UInt<1>("h01"), _T_3204) @[RegMapper.scala 142:31] + _T_1277[10] <= _T_3205 @[RegMapper.scala 142:18] + node _T_3207 = eq(_T_3186, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3208 = or(UInt<1>("h01"), _T_3207) @[RegMapper.scala 143:31] + _T_1299[10] <= _T_3208 @[RegMapper.scala 143:18] + node _T_3210 = eq(_T_3189, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3211 = or(UInt<1>("h01"), _T_3210) @[RegMapper.scala 144:31] + _T_1321[10] <= _T_3211 @[RegMapper.scala 144:18] + node _T_3213 = eq(_T_3193, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3214 = or(UInt<1>("h01"), _T_3213) @[RegMapper.scala 145:31] + _T_1343[10] <= _T_3214 @[RegMapper.scala 145:18] + node _T_3215 = shl(pending[1], 1) @[RegMapper.scala 150:47] + node _T_3217 = not(UInt<2>("h00")) @[RegMapper.scala 150:58] + node _T_3218 = and(_T_3215, _T_3217) @[RegMapper.scala 150:55] + node _T_3219 = or(_T_3179, _T_3218) @[RegMapper.scala 150:35] + node _T_3220 = bits(_T_2732, 2, 2) @[RegMapper.scala 135:29] + node _T_3222 = neq(_T_3220, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3223 = bits(_T_2732, 2, 2) @[RegMapper.scala 136:29] + node _T_3224 = not(_T_3223) @[RegMapper.scala 136:45] + node _T_3226 = eq(_T_3224, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3227 = bits(_T_2779, 2, 2) @[RegMapper.scala 137:28] + node _T_3229 = neq(_T_3227, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3230 = bits(_T_2779, 2, 2) @[RegMapper.scala 138:28] + node _T_3231 = not(_T_3230) @[RegMapper.scala 138:44] + node _T_3233 = eq(_T_3231, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3234 = and(_T_1233[11], _T_3222) @[RegMapper.scala 140:69] + node _T_3235 = and(_T_1365[11], _T_3229) @[RegMapper.scala 140:91] + node _T_3238 = and(_T_1255[11], _T_3226) @[RegMapper.scala 141:62] + node _T_3239 = and(_T_1387[11], _T_3233) @[RegMapper.scala 141:84] + node _T_3240 = bits(_T_692.bits.data, 2, 2) @[RegMapper.scala 141:99] + node _T_3244 = eq(_T_3222, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3245 = or(UInt<1>("h01"), _T_3244) @[RegMapper.scala 142:31] + _T_1277[11] <= _T_3245 @[RegMapper.scala 142:18] + node _T_3247 = eq(_T_3226, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3248 = or(UInt<1>("h01"), _T_3247) @[RegMapper.scala 143:31] + _T_1299[11] <= _T_3248 @[RegMapper.scala 143:18] + node _T_3250 = eq(_T_3229, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3251 = or(UInt<1>("h01"), _T_3250) @[RegMapper.scala 144:31] + _T_1321[11] <= _T_3251 @[RegMapper.scala 144:18] + node _T_3253 = eq(_T_3233, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3254 = or(UInt<1>("h01"), _T_3253) @[RegMapper.scala 145:31] + _T_1343[11] <= _T_3254 @[RegMapper.scala 145:18] + node _T_3255 = shl(pending[2], 2) @[RegMapper.scala 150:47] + node _T_3257 = not(UInt<3>("h00")) @[RegMapper.scala 150:58] + node _T_3258 = and(_T_3255, _T_3257) @[RegMapper.scala 150:55] + node _T_3259 = or(_T_3219, _T_3258) @[RegMapper.scala 150:35] + node _T_3260 = bits(_T_2732, 31, 0) @[RegMapper.scala 135:29] + node _T_3262 = neq(_T_3260, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3263 = bits(_T_2732, 31, 0) @[RegMapper.scala 136:29] + node _T_3264 = not(_T_3263) @[RegMapper.scala 136:45] + node _T_3266 = eq(_T_3264, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3267 = bits(_T_2779, 31, 0) @[RegMapper.scala 137:28] + node _T_3269 = neq(_T_3267, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3270 = bits(_T_2779, 31, 0) @[RegMapper.scala 138:28] + node _T_3271 = not(_T_3270) @[RegMapper.scala 138:44] + node _T_3273 = eq(_T_3271, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3274 = and(_T_1233[12], _T_3262) @[RegMapper.scala 140:69] + node _T_3275 = and(_T_1365[12], _T_3269) @[RegMapper.scala 140:91] + node _T_3278 = and(_T_1255[12], _T_3266) @[RegMapper.scala 141:62] + node _T_3279 = and(_T_1387[12], _T_3273) @[RegMapper.scala 141:84] + node _T_3280 = bits(_T_692.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_3279 : @[RegField.scala 70:88] + threshold[1] <= _T_3280 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3284 = eq(_T_3262, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3285 = or(UInt<1>("h01"), _T_3284) @[RegMapper.scala 142:31] + _T_1277[12] <= _T_3285 @[RegMapper.scala 142:18] + node _T_3287 = eq(_T_3266, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3288 = or(UInt<1>("h01"), _T_3287) @[RegMapper.scala 143:31] + _T_1299[12] <= _T_3288 @[RegMapper.scala 143:18] + node _T_3290 = eq(_T_3269, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3291 = or(UInt<1>("h01"), _T_3290) @[RegMapper.scala 144:31] + _T_1321[12] <= _T_3291 @[RegMapper.scala 144:18] + node _T_3293 = eq(_T_3273, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3294 = or(UInt<1>("h01"), _T_3293) @[RegMapper.scala 145:31] + _T_1343[12] <= _T_3294 @[RegMapper.scala 145:18] + node _T_3295 = shl(threshold[1], 0) @[RegMapper.scala 150:47] + node _T_3297 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_3298 = and(_T_3295, _T_3297) @[RegMapper.scala 150:55] + node _T_3299 = or(UInt<1>("h00"), _T_3298) @[RegMapper.scala 150:35] + node _T_3300 = bits(_T_2732, 63, 32) @[RegMapper.scala 135:29] + node _T_3302 = neq(_T_3300, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3303 = bits(_T_2732, 63, 32) @[RegMapper.scala 136:29] + node _T_3304 = not(_T_3303) @[RegMapper.scala 136:45] + node _T_3306 = eq(_T_3304, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3307 = bits(_T_2779, 63, 32) @[RegMapper.scala 137:28] + node _T_3309 = neq(_T_3307, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3310 = bits(_T_2779, 63, 32) @[RegMapper.scala 138:28] + node _T_3311 = not(_T_3310) @[RegMapper.scala 138:44] + node _T_3313 = eq(_T_3311, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3314 = and(_T_1233[13], _T_3302) @[RegMapper.scala 140:69] + node _T_3315 = and(_T_1365[13], _T_3309) @[RegMapper.scala 140:91] + when _T_3315 : @[Plic.scala 185:26] + pending[maxDevs[1]] <= UInt<1>("h00") @[Plic.scala 186:35] + maxDevs[1] <= UInt<1>("h00") @[Plic.scala 187:26] + skip @[Plic.scala 185:26] + node _T_3322 = and(_T_1255[13], _T_3306) @[RegMapper.scala 141:62] + node _T_3323 = and(_T_1387[13], _T_3313) @[RegMapper.scala 141:84] + node _T_3324 = bits(_T_692.bits.data, 63, 32) @[RegMapper.scala 141:99] + node _T_3328 = bits(_T_3324, 1, 0) + node _T_3329 = and(_T_3323, enables[1][_T_3328]) @[Plic.scala 192:25] + when _T_3329 : @[Plic.scala 192:46] + node _T_3331 = sub(_T_3324, UInt<1>("h01")) @[Plic.scala 193:29] + node _T_3332 = asUInt(_T_3331) @[Plic.scala 193:29] + node _T_3333 = tail(_T_3332, 1) @[Plic.scala 193:29] + node _T_3347 = bits(_T_3333, 0, 0) + gateways[_T_3347].complete <= UInt<1>("h01") @[Plic.scala 193:49] + skip @[Plic.scala 192:46] + node _T_3351 = eq(_T_3302, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3352 = or(UInt<1>("h01"), _T_3351) @[RegMapper.scala 142:31] + _T_1277[13] <= _T_3352 @[RegMapper.scala 142:18] + node _T_3354 = eq(_T_3306, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3355 = or(UInt<1>("h01"), _T_3354) @[RegMapper.scala 143:31] + _T_1299[13] <= _T_3355 @[RegMapper.scala 143:18] + node _T_3357 = eq(_T_3309, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3358 = or(UInt<1>("h01"), _T_3357) @[RegMapper.scala 144:31] + _T_1321[13] <= _T_3358 @[RegMapper.scala 144:18] + node _T_3360 = eq(_T_3313, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3361 = or(UInt<1>("h01"), _T_3360) @[RegMapper.scala 145:31] + _T_1343[13] <= _T_3361 @[RegMapper.scala 145:18] + node _T_3362 = shl(maxDevs[1], 32) @[RegMapper.scala 150:47] + node _T_3364 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_3365 = and(_T_3362, _T_3364) @[RegMapper.scala 150:55] + node _T_3366 = or(_T_3299, _T_3365) @[RegMapper.scala 150:35] + node _T_3367 = bits(_T_2732, 31, 0) @[RegMapper.scala 135:29] + node _T_3369 = neq(_T_3367, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3370 = bits(_T_2732, 31, 0) @[RegMapper.scala 136:29] + node _T_3371 = not(_T_3370) @[RegMapper.scala 136:45] + node _T_3373 = eq(_T_3371, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3374 = bits(_T_2779, 31, 0) @[RegMapper.scala 137:28] + node _T_3376 = neq(_T_3374, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3377 = bits(_T_2779, 31, 0) @[RegMapper.scala 138:28] + node _T_3378 = not(_T_3377) @[RegMapper.scala 138:44] + node _T_3380 = eq(_T_3378, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3381 = and(_T_1233[14], _T_3369) @[RegMapper.scala 140:69] + node _T_3382 = and(_T_1365[14], _T_3376) @[RegMapper.scala 140:91] + node _T_3385 = and(_T_1255[14], _T_3373) @[RegMapper.scala 141:62] + node _T_3386 = and(_T_1387[14], _T_3380) @[RegMapper.scala 141:84] + node _T_3387 = bits(_T_692.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_3386 : @[RegField.scala 70:88] + threshold[0] <= _T_3387 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_3391 = eq(_T_3369, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3392 = or(UInt<1>("h01"), _T_3391) @[RegMapper.scala 142:31] + _T_1277[14] <= _T_3392 @[RegMapper.scala 142:18] + node _T_3394 = eq(_T_3373, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3395 = or(UInt<1>("h01"), _T_3394) @[RegMapper.scala 143:31] + _T_1299[14] <= _T_3395 @[RegMapper.scala 143:18] + node _T_3397 = eq(_T_3376, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3398 = or(UInt<1>("h01"), _T_3397) @[RegMapper.scala 144:31] + _T_1321[14] <= _T_3398 @[RegMapper.scala 144:18] + node _T_3400 = eq(_T_3380, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3401 = or(UInt<1>("h01"), _T_3400) @[RegMapper.scala 145:31] + _T_1343[14] <= _T_3401 @[RegMapper.scala 145:18] + node _T_3402 = shl(threshold[0], 0) @[RegMapper.scala 150:47] + node _T_3404 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_3405 = and(_T_3402, _T_3404) @[RegMapper.scala 150:55] + node _T_3406 = or(UInt<1>("h00"), _T_3405) @[RegMapper.scala 150:35] + node _T_3407 = bits(_T_2732, 63, 32) @[RegMapper.scala 135:29] + node _T_3409 = neq(_T_3407, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_3410 = bits(_T_2732, 63, 32) @[RegMapper.scala 136:29] + node _T_3411 = not(_T_3410) @[RegMapper.scala 136:45] + node _T_3413 = eq(_T_3411, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_3414 = bits(_T_2779, 63, 32) @[RegMapper.scala 137:28] + node _T_3416 = neq(_T_3414, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_3417 = bits(_T_2779, 63, 32) @[RegMapper.scala 138:28] + node _T_3418 = not(_T_3417) @[RegMapper.scala 138:44] + node _T_3420 = eq(_T_3418, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_3421 = and(_T_1233[15], _T_3409) @[RegMapper.scala 140:69] + node _T_3422 = and(_T_1365[15], _T_3416) @[RegMapper.scala 140:91] + when _T_3422 : @[Plic.scala 185:26] + pending[maxDevs[0]] <= UInt<1>("h00") @[Plic.scala 186:35] + maxDevs[0] <= UInt<1>("h00") @[Plic.scala 187:26] + skip @[Plic.scala 185:26] + node _T_3429 = and(_T_1255[15], _T_3413) @[RegMapper.scala 141:62] + node _T_3430 = and(_T_1387[15], _T_3420) @[RegMapper.scala 141:84] + node _T_3431 = bits(_T_692.bits.data, 63, 32) @[RegMapper.scala 141:99] + node _T_3435 = bits(_T_3431, 1, 0) + node _T_3436 = and(_T_3430, enables[0][_T_3435]) @[Plic.scala 192:25] + when _T_3436 : @[Plic.scala 192:46] + node _T_3438 = sub(_T_3431, UInt<1>("h01")) @[Plic.scala 193:29] + node _T_3439 = asUInt(_T_3438) @[Plic.scala 193:29] + node _T_3440 = tail(_T_3439, 1) @[Plic.scala 193:29] + node _T_3454 = bits(_T_3440, 0, 0) + gateways[_T_3454].complete <= UInt<1>("h01") @[Plic.scala 193:49] + skip @[Plic.scala 192:46] + node _T_3458 = eq(_T_3409, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_3459 = or(UInt<1>("h01"), _T_3458) @[RegMapper.scala 142:31] + _T_1277[15] <= _T_3459 @[RegMapper.scala 142:18] + node _T_3461 = eq(_T_3413, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_3462 = or(UInt<1>("h01"), _T_3461) @[RegMapper.scala 143:31] + _T_1299[15] <= _T_3462 @[RegMapper.scala 143:18] + node _T_3464 = eq(_T_3416, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_3465 = or(UInt<1>("h01"), _T_3464) @[RegMapper.scala 144:31] + _T_1321[15] <= _T_3465 @[RegMapper.scala 144:18] + node _T_3467 = eq(_T_3420, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_3468 = or(UInt<1>("h01"), _T_3467) @[RegMapper.scala 145:31] + _T_1343[15] <= _T_3468 @[RegMapper.scala 145:18] + node _T_3469 = shl(maxDevs[0], 32) @[RegMapper.scala 150:47] + node _T_3471 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_3472 = and(_T_3469, _T_3471) @[RegMapper.scala 150:55] + node _T_3473 = or(_T_3406, _T_3472) @[RegMapper.scala 150:35] + node _T_3475 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3476 = and(_T_1277[4], _T_1277[3]) @[RegMapper.scala 154:98] + node _T_3477 = and(_T_3476, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3478 = or(_T_3475, _T_3477) @[RegMapper.scala 154:82] + node _T_3480 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3481 = and(_T_1277[8], UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3482 = or(_T_3480, _T_3481) @[RegMapper.scala 154:82] + node _T_3484 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3485 = or(_T_3484, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3487 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3488 = or(_T_3487, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3490 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3491 = or(_T_3490, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3493 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3494 = or(_T_3493, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3496 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3497 = or(_T_3496, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3499 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3500 = or(_T_3499, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3502 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3503 = or(_T_3502, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3505 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3506 = or(_T_3505, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3508 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3509 = or(_T_3508, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3511 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3512 = or(_T_3511, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3514 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3515 = or(_T_3514, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3517 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3518 = or(_T_3517, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3520 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3521 = or(_T_3520, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3523 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3524 = or(_T_3523, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3526 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3527 = or(_T_3526, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3529 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3530 = or(_T_3529, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3532 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3533 = or(_T_3532, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3535 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3536 = or(_T_3535, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3538 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3539 = or(_T_3538, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3541 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3542 = or(_T_3541, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3544 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3545 = or(_T_3544, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3547 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3548 = or(_T_3547, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3550 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3551 = or(_T_3550, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3553 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3554 = or(_T_3553, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3556 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3557 = or(_T_3556, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3559 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3560 = or(_T_3559, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3562 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3563 = or(_T_3562, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3565 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3566 = or(_T_3565, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3568 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3569 = or(_T_3568, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3571 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3572 = or(_T_3571, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3574 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3575 = and(_T_1277[11], _T_1277[10]) @[RegMapper.scala 154:98] + node _T_3576 = and(_T_3575, _T_1277[9]) @[RegMapper.scala 154:98] + node _T_3577 = and(_T_3576, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3578 = or(_T_3574, _T_3577) @[RegMapper.scala 154:82] + node _T_3580 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3581 = or(_T_3580, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3583 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3584 = or(_T_3583, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3586 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3587 = or(_T_3586, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3589 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3590 = or(_T_3589, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3592 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3593 = or(_T_3592, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3595 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3596 = or(_T_3595, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3598 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3599 = or(_T_3598, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3601 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3602 = or(_T_3601, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3604 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3605 = or(_T_3604, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3607 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3608 = or(_T_3607, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3610 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3611 = or(_T_3610, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3613 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3614 = or(_T_3613, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3616 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3617 = or(_T_3616, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3619 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3620 = or(_T_3619, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3622 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3623 = or(_T_3622, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3625 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3626 = or(_T_3625, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3628 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3629 = or(_T_3628, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3631 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3632 = or(_T_3631, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3634 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3635 = or(_T_3634, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3637 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3638 = or(_T_3637, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3640 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3641 = or(_T_3640, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3643 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3644 = or(_T_3643, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3646 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3647 = or(_T_3646, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3649 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3650 = or(_T_3649, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3652 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3653 = or(_T_3652, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3656 = or(_T_3655, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3658 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3659 = or(_T_3658, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3661 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3662 = or(_T_3661, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3664 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3665 = or(_T_3664, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3667 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3668 = or(_T_3667, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3670 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3671 = or(_T_3670, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3673 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3674 = and(_T_1277[2], _T_1277[1]) @[RegMapper.scala 154:98] + node _T_3675 = and(_T_3674, _T_1277[0]) @[RegMapper.scala 154:98] + node _T_3676 = and(_T_3675, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3677 = or(_T_3673, _T_3676) @[RegMapper.scala 154:82] + node _T_3679 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3680 = or(_T_3679, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3682 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3683 = or(_T_3682, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3685 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3686 = or(_T_3685, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3688 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3689 = or(_T_3688, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3691 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3692 = or(_T_3691, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3694 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3695 = or(_T_3694, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3697 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3698 = or(_T_3697, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3700 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3701 = or(_T_3700, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3703 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3704 = or(_T_3703, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3706 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3707 = or(_T_3706, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3709 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3710 = or(_T_3709, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3712 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3713 = or(_T_3712, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3715 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3716 = or(_T_3715, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3718 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3719 = or(_T_3718, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3721 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3722 = or(_T_3721, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3724 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3725 = and(_T_1277[7], _T_1277[6]) @[RegMapper.scala 154:98] + node _T_3726 = and(_T_3725, _T_1277[5]) @[RegMapper.scala 154:98] + node _T_3727 = and(_T_3726, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3728 = or(_T_3724, _T_3727) @[RegMapper.scala 154:82] + node _T_3730 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3731 = or(_T_3730, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3733 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3734 = or(_T_3733, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3736 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3737 = or(_T_3736, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3739 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3740 = or(_T_3739, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3742 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3743 = or(_T_3742, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3745 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3746 = or(_T_3745, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3748 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3749 = or(_T_3748, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3751 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3752 = or(_T_3751, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3755 = or(_T_3754, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3757 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3758 = or(_T_3757, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3760 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3761 = or(_T_3760, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3763 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3764 = or(_T_3763, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3766 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3767 = or(_T_3766, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3769 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3770 = or(_T_3769, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3772 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3773 = or(_T_3772, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3775 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3776 = or(_T_3775, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3778 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3779 = or(_T_3778, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3781 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3782 = or(_T_3781, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3784 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3785 = or(_T_3784, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3787 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3788 = or(_T_3787, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3790 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3791 = or(_T_3790, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3793 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3794 = or(_T_3793, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3796 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3797 = or(_T_3796, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3799 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3800 = or(_T_3799, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3802 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3803 = or(_T_3802, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3805 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3806 = or(_T_3805, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3808 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3809 = or(_T_3808, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3811 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3812 = or(_T_3811, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3814 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3815 = or(_T_3814, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3817 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3818 = or(_T_3817, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3820 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3821 = or(_T_3820, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3823 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3824 = or(_T_3823, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3826 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3827 = or(_T_3826, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3829 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3830 = or(_T_3829, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3832 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3833 = or(_T_3832, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3835 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3836 = or(_T_3835, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3838 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3839 = or(_T_3838, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3841 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3842 = or(_T_3841, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3844 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3845 = or(_T_3844, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3847 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3848 = or(_T_3847, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3850 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3851 = or(_T_3850, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3853 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3854 = or(_T_3853, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3856 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3857 = or(_T_3856, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3859 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3860 = or(_T_3859, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3862 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3863 = or(_T_3862, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3865 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3866 = or(_T_3865, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3868 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3869 = or(_T_3868, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3871 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3872 = and(_T_1277[15], _T_1277[14]) @[RegMapper.scala 154:98] + node _T_3873 = and(_T_3872, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3874 = or(_T_3871, _T_3873) @[RegMapper.scala 154:82] + node _T_3876 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3877 = or(_T_3876, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3879 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3880 = or(_T_3879, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3882 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3883 = or(_T_3882, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3885 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3886 = or(_T_3885, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3888 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3889 = or(_T_3888, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3891 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3892 = or(_T_3891, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3894 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3895 = or(_T_3894, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3897 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3898 = or(_T_3897, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3900 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3901 = or(_T_3900, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3903 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3904 = or(_T_3903, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3906 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3907 = or(_T_3906, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3909 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3910 = or(_T_3909, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3912 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3913 = or(_T_3912, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3915 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3916 = or(_T_3915, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3918 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3919 = or(_T_3918, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3921 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3922 = or(_T_3921, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3924 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3925 = or(_T_3924, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3927 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3928 = or(_T_3927, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3930 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3931 = or(_T_3930, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3933 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3934 = or(_T_3933, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3936 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3937 = or(_T_3936, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3939 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3940 = or(_T_3939, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3942 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3943 = or(_T_3942, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3945 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3946 = or(_T_3945, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3948 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3949 = or(_T_3948, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3951 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3952 = or(_T_3951, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3954 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3955 = or(_T_3954, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3957 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3958 = or(_T_3957, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3960 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3961 = or(_T_3960, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3963 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3964 = or(_T_3963, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3966 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3967 = or(_T_3966, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3969 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3970 = and(_T_1277[13], _T_1277[12]) @[RegMapper.scala 154:98] + node _T_3971 = and(_T_3970, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_3972 = or(_T_3969, _T_3971) @[RegMapper.scala 154:82] + node _T_3974 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3975 = or(_T_3974, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3977 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3978 = or(_T_3977, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3980 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3981 = or(_T_3980, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3983 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3984 = or(_T_3983, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3986 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3987 = or(_T_3986, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3989 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3990 = or(_T_3989, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3992 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3993 = or(_T_3992, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3995 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3996 = or(_T_3995, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_3998 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_3999 = or(_T_3998, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4001 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4002 = or(_T_4001, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4004 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4005 = or(_T_4004, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4007 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4008 = or(_T_4007, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4010 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4011 = or(_T_4010, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4013 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4014 = or(_T_4013, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4016 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4017 = or(_T_4016, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4019 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4020 = or(_T_4019, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4022 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4023 = or(_T_4022, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4025 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4026 = or(_T_4025, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4028 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4029 = or(_T_4028, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4031 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4032 = or(_T_4031, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4034 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4035 = or(_T_4034, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4037 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4038 = or(_T_4037, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4040 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4041 = or(_T_4040, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4043 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4044 = or(_T_4043, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4046 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4047 = or(_T_4046, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4049 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4050 = or(_T_4049, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4052 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4053 = or(_T_4052, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4055 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4056 = or(_T_4055, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4058 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4059 = or(_T_4058, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4061 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4062 = or(_T_4061, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4064 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4065 = or(_T_4064, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4067 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4068 = or(_T_4067, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4070 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4071 = or(_T_4070, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4073 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4074 = or(_T_4073, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4076 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4077 = or(_T_4076, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4079 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4080 = or(_T_4079, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4082 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4083 = or(_T_4082, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4085 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4086 = or(_T_4085, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4088 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4089 = or(_T_4088, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4091 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4092 = or(_T_4091, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4094 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4095 = or(_T_4094, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4097 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4098 = or(_T_4097, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4100 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4101 = or(_T_4100, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4103 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4104 = or(_T_4103, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4106 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4107 = or(_T_4106, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4109 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4110 = or(_T_4109, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4112 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4113 = or(_T_4112, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4115 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4116 = or(_T_4115, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4118 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4119 = or(_T_4118, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4121 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4122 = or(_T_4121, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4124 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4125 = or(_T_4124, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4127 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4128 = or(_T_4127, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4130 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4131 = or(_T_4130, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4133 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4134 = or(_T_4133, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4136 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4137 = or(_T_4136, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4139 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4140 = or(_T_4139, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4142 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4143 = or(_T_4142, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4145 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4146 = or(_T_4145, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4148 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4149 = or(_T_4148, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4151 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4152 = or(_T_4151, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4154 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4155 = or(_T_4154, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4157 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4158 = or(_T_4157, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4160 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4161 = or(_T_4160, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4163 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4164 = or(_T_4163, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4166 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4167 = or(_T_4166, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4169 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4170 = or(_T_4169, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4172 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4173 = or(_T_4172, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4175 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4176 = or(_T_4175, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4178 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4179 = or(_T_4178, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4181 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4182 = or(_T_4181, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4184 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4185 = or(_T_4184, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4187 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4188 = or(_T_4187, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4190 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4191 = or(_T_4190, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4193 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4194 = or(_T_4193, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4196 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4197 = or(_T_4196, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4199 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4200 = or(_T_4199, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4202 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4203 = or(_T_4202, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4205 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4206 = or(_T_4205, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4208 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4209 = or(_T_4208, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4211 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4212 = or(_T_4211, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4214 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4215 = or(_T_4214, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4217 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4218 = or(_T_4217, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4220 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4221 = or(_T_4220, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4223 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4224 = or(_T_4223, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4226 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4227 = or(_T_4226, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4229 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4230 = or(_T_4229, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4232 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4233 = or(_T_4232, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4235 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4236 = or(_T_4235, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4238 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4239 = or(_T_4238, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4241 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4242 = or(_T_4241, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4244 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4245 = or(_T_4244, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4247 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4248 = or(_T_4247, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4250 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4251 = or(_T_4250, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4253 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4254 = or(_T_4253, UInt<1>("h01")) @[RegMapper.scala 154:82] + node _T_4256 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_4257 = or(_T_4256, UInt<1>("h01")) @[RegMapper.scala 154:82] + wire _T_4260 : UInt<1>[256] @[RegMapper.scala 154:24] + _T_4260 is invalid @[RegMapper.scala 154:24] + _T_4260[0] <= _T_3478 @[RegMapper.scala 154:24] + _T_4260[1] <= _T_3482 @[RegMapper.scala 154:24] + _T_4260[2] <= _T_3485 @[RegMapper.scala 154:24] + _T_4260[3] <= _T_3488 @[RegMapper.scala 154:24] + _T_4260[4] <= _T_3491 @[RegMapper.scala 154:24] + _T_4260[5] <= _T_3494 @[RegMapper.scala 154:24] + _T_4260[6] <= _T_3497 @[RegMapper.scala 154:24] + _T_4260[7] <= _T_3500 @[RegMapper.scala 154:24] + _T_4260[8] <= _T_3503 @[RegMapper.scala 154:24] + _T_4260[9] <= _T_3506 @[RegMapper.scala 154:24] + _T_4260[10] <= _T_3509 @[RegMapper.scala 154:24] + _T_4260[11] <= _T_3512 @[RegMapper.scala 154:24] + _T_4260[12] <= _T_3515 @[RegMapper.scala 154:24] + _T_4260[13] <= _T_3518 @[RegMapper.scala 154:24] + _T_4260[14] <= _T_3521 @[RegMapper.scala 154:24] + _T_4260[15] <= _T_3524 @[RegMapper.scala 154:24] + _T_4260[16] <= _T_3527 @[RegMapper.scala 154:24] + _T_4260[17] <= _T_3530 @[RegMapper.scala 154:24] + _T_4260[18] <= _T_3533 @[RegMapper.scala 154:24] + _T_4260[19] <= _T_3536 @[RegMapper.scala 154:24] + _T_4260[20] <= _T_3539 @[RegMapper.scala 154:24] + _T_4260[21] <= _T_3542 @[RegMapper.scala 154:24] + _T_4260[22] <= _T_3545 @[RegMapper.scala 154:24] + _T_4260[23] <= _T_3548 @[RegMapper.scala 154:24] + _T_4260[24] <= _T_3551 @[RegMapper.scala 154:24] + _T_4260[25] <= _T_3554 @[RegMapper.scala 154:24] + _T_4260[26] <= _T_3557 @[RegMapper.scala 154:24] + _T_4260[27] <= _T_3560 @[RegMapper.scala 154:24] + _T_4260[28] <= _T_3563 @[RegMapper.scala 154:24] + _T_4260[29] <= _T_3566 @[RegMapper.scala 154:24] + _T_4260[30] <= _T_3569 @[RegMapper.scala 154:24] + _T_4260[31] <= _T_3572 @[RegMapper.scala 154:24] + _T_4260[32] <= _T_3578 @[RegMapper.scala 154:24] + _T_4260[33] <= _T_3581 @[RegMapper.scala 154:24] + _T_4260[34] <= _T_3584 @[RegMapper.scala 154:24] + _T_4260[35] <= _T_3587 @[RegMapper.scala 154:24] + _T_4260[36] <= _T_3590 @[RegMapper.scala 154:24] + _T_4260[37] <= _T_3593 @[RegMapper.scala 154:24] + _T_4260[38] <= _T_3596 @[RegMapper.scala 154:24] + _T_4260[39] <= _T_3599 @[RegMapper.scala 154:24] + _T_4260[40] <= _T_3602 @[RegMapper.scala 154:24] + _T_4260[41] <= _T_3605 @[RegMapper.scala 154:24] + _T_4260[42] <= _T_3608 @[RegMapper.scala 154:24] + _T_4260[43] <= _T_3611 @[RegMapper.scala 154:24] + _T_4260[44] <= _T_3614 @[RegMapper.scala 154:24] + _T_4260[45] <= _T_3617 @[RegMapper.scala 154:24] + _T_4260[46] <= _T_3620 @[RegMapper.scala 154:24] + _T_4260[47] <= _T_3623 @[RegMapper.scala 154:24] + _T_4260[48] <= _T_3626 @[RegMapper.scala 154:24] + _T_4260[49] <= _T_3629 @[RegMapper.scala 154:24] + _T_4260[50] <= _T_3632 @[RegMapper.scala 154:24] + _T_4260[51] <= _T_3635 @[RegMapper.scala 154:24] + _T_4260[52] <= _T_3638 @[RegMapper.scala 154:24] + _T_4260[53] <= _T_3641 @[RegMapper.scala 154:24] + _T_4260[54] <= _T_3644 @[RegMapper.scala 154:24] + _T_4260[55] <= _T_3647 @[RegMapper.scala 154:24] + _T_4260[56] <= _T_3650 @[RegMapper.scala 154:24] + _T_4260[57] <= _T_3653 @[RegMapper.scala 154:24] + _T_4260[58] <= _T_3656 @[RegMapper.scala 154:24] + _T_4260[59] <= _T_3659 @[RegMapper.scala 154:24] + _T_4260[60] <= _T_3662 @[RegMapper.scala 154:24] + _T_4260[61] <= _T_3665 @[RegMapper.scala 154:24] + _T_4260[62] <= _T_3668 @[RegMapper.scala 154:24] + _T_4260[63] <= _T_3671 @[RegMapper.scala 154:24] + _T_4260[64] <= _T_3677 @[RegMapper.scala 154:24] + _T_4260[65] <= _T_3680 @[RegMapper.scala 154:24] + _T_4260[66] <= _T_3683 @[RegMapper.scala 154:24] + _T_4260[67] <= _T_3686 @[RegMapper.scala 154:24] + _T_4260[68] <= _T_3689 @[RegMapper.scala 154:24] + _T_4260[69] <= _T_3692 @[RegMapper.scala 154:24] + _T_4260[70] <= _T_3695 @[RegMapper.scala 154:24] + _T_4260[71] <= _T_3698 @[RegMapper.scala 154:24] + _T_4260[72] <= _T_3701 @[RegMapper.scala 154:24] + _T_4260[73] <= _T_3704 @[RegMapper.scala 154:24] + _T_4260[74] <= _T_3707 @[RegMapper.scala 154:24] + _T_4260[75] <= _T_3710 @[RegMapper.scala 154:24] + _T_4260[76] <= _T_3713 @[RegMapper.scala 154:24] + _T_4260[77] <= _T_3716 @[RegMapper.scala 154:24] + _T_4260[78] <= _T_3719 @[RegMapper.scala 154:24] + _T_4260[79] <= _T_3722 @[RegMapper.scala 154:24] + _T_4260[80] <= _T_3728 @[RegMapper.scala 154:24] + _T_4260[81] <= _T_3731 @[RegMapper.scala 154:24] + _T_4260[82] <= _T_3734 @[RegMapper.scala 154:24] + _T_4260[83] <= _T_3737 @[RegMapper.scala 154:24] + _T_4260[84] <= _T_3740 @[RegMapper.scala 154:24] + _T_4260[85] <= _T_3743 @[RegMapper.scala 154:24] + _T_4260[86] <= _T_3746 @[RegMapper.scala 154:24] + _T_4260[87] <= _T_3749 @[RegMapper.scala 154:24] + _T_4260[88] <= _T_3752 @[RegMapper.scala 154:24] + _T_4260[89] <= _T_3755 @[RegMapper.scala 154:24] + _T_4260[90] <= _T_3758 @[RegMapper.scala 154:24] + _T_4260[91] <= _T_3761 @[RegMapper.scala 154:24] + _T_4260[92] <= _T_3764 @[RegMapper.scala 154:24] + _T_4260[93] <= _T_3767 @[RegMapper.scala 154:24] + _T_4260[94] <= _T_3770 @[RegMapper.scala 154:24] + _T_4260[95] <= _T_3773 @[RegMapper.scala 154:24] + _T_4260[96] <= _T_3776 @[RegMapper.scala 154:24] + _T_4260[97] <= _T_3779 @[RegMapper.scala 154:24] + _T_4260[98] <= _T_3782 @[RegMapper.scala 154:24] + _T_4260[99] <= _T_3785 @[RegMapper.scala 154:24] + _T_4260[100] <= _T_3788 @[RegMapper.scala 154:24] + _T_4260[101] <= _T_3791 @[RegMapper.scala 154:24] + _T_4260[102] <= _T_3794 @[RegMapper.scala 154:24] + _T_4260[103] <= _T_3797 @[RegMapper.scala 154:24] + _T_4260[104] <= _T_3800 @[RegMapper.scala 154:24] + _T_4260[105] <= _T_3803 @[RegMapper.scala 154:24] + _T_4260[106] <= _T_3806 @[RegMapper.scala 154:24] + _T_4260[107] <= _T_3809 @[RegMapper.scala 154:24] + _T_4260[108] <= _T_3812 @[RegMapper.scala 154:24] + _T_4260[109] <= _T_3815 @[RegMapper.scala 154:24] + _T_4260[110] <= _T_3818 @[RegMapper.scala 154:24] + _T_4260[111] <= _T_3821 @[RegMapper.scala 154:24] + _T_4260[112] <= _T_3824 @[RegMapper.scala 154:24] + _T_4260[113] <= _T_3827 @[RegMapper.scala 154:24] + _T_4260[114] <= _T_3830 @[RegMapper.scala 154:24] + _T_4260[115] <= _T_3833 @[RegMapper.scala 154:24] + _T_4260[116] <= _T_3836 @[RegMapper.scala 154:24] + _T_4260[117] <= _T_3839 @[RegMapper.scala 154:24] + _T_4260[118] <= _T_3842 @[RegMapper.scala 154:24] + _T_4260[119] <= _T_3845 @[RegMapper.scala 154:24] + _T_4260[120] <= _T_3848 @[RegMapper.scala 154:24] + _T_4260[121] <= _T_3851 @[RegMapper.scala 154:24] + _T_4260[122] <= _T_3854 @[RegMapper.scala 154:24] + _T_4260[123] <= _T_3857 @[RegMapper.scala 154:24] + _T_4260[124] <= _T_3860 @[RegMapper.scala 154:24] + _T_4260[125] <= _T_3863 @[RegMapper.scala 154:24] + _T_4260[126] <= _T_3866 @[RegMapper.scala 154:24] + _T_4260[127] <= _T_3869 @[RegMapper.scala 154:24] + _T_4260[128] <= _T_3874 @[RegMapper.scala 154:24] + _T_4260[129] <= _T_3877 @[RegMapper.scala 154:24] + _T_4260[130] <= _T_3880 @[RegMapper.scala 154:24] + _T_4260[131] <= _T_3883 @[RegMapper.scala 154:24] + _T_4260[132] <= _T_3886 @[RegMapper.scala 154:24] + _T_4260[133] <= _T_3889 @[RegMapper.scala 154:24] + _T_4260[134] <= _T_3892 @[RegMapper.scala 154:24] + _T_4260[135] <= _T_3895 @[RegMapper.scala 154:24] + _T_4260[136] <= _T_3898 @[RegMapper.scala 154:24] + _T_4260[137] <= _T_3901 @[RegMapper.scala 154:24] + _T_4260[138] <= _T_3904 @[RegMapper.scala 154:24] + _T_4260[139] <= _T_3907 @[RegMapper.scala 154:24] + _T_4260[140] <= _T_3910 @[RegMapper.scala 154:24] + _T_4260[141] <= _T_3913 @[RegMapper.scala 154:24] + _T_4260[142] <= _T_3916 @[RegMapper.scala 154:24] + _T_4260[143] <= _T_3919 @[RegMapper.scala 154:24] + _T_4260[144] <= _T_3922 @[RegMapper.scala 154:24] + _T_4260[145] <= _T_3925 @[RegMapper.scala 154:24] + _T_4260[146] <= _T_3928 @[RegMapper.scala 154:24] + _T_4260[147] <= _T_3931 @[RegMapper.scala 154:24] + _T_4260[148] <= _T_3934 @[RegMapper.scala 154:24] + _T_4260[149] <= _T_3937 @[RegMapper.scala 154:24] + _T_4260[150] <= _T_3940 @[RegMapper.scala 154:24] + _T_4260[151] <= _T_3943 @[RegMapper.scala 154:24] + _T_4260[152] <= _T_3946 @[RegMapper.scala 154:24] + _T_4260[153] <= _T_3949 @[RegMapper.scala 154:24] + _T_4260[154] <= _T_3952 @[RegMapper.scala 154:24] + _T_4260[155] <= _T_3955 @[RegMapper.scala 154:24] + _T_4260[156] <= _T_3958 @[RegMapper.scala 154:24] + _T_4260[157] <= _T_3961 @[RegMapper.scala 154:24] + _T_4260[158] <= _T_3964 @[RegMapper.scala 154:24] + _T_4260[159] <= _T_3967 @[RegMapper.scala 154:24] + _T_4260[160] <= _T_3972 @[RegMapper.scala 154:24] + _T_4260[161] <= _T_3975 @[RegMapper.scala 154:24] + _T_4260[162] <= _T_3978 @[RegMapper.scala 154:24] + _T_4260[163] <= _T_3981 @[RegMapper.scala 154:24] + _T_4260[164] <= _T_3984 @[RegMapper.scala 154:24] + _T_4260[165] <= _T_3987 @[RegMapper.scala 154:24] + _T_4260[166] <= _T_3990 @[RegMapper.scala 154:24] + _T_4260[167] <= _T_3993 @[RegMapper.scala 154:24] + _T_4260[168] <= _T_3996 @[RegMapper.scala 154:24] + _T_4260[169] <= _T_3999 @[RegMapper.scala 154:24] + _T_4260[170] <= _T_4002 @[RegMapper.scala 154:24] + _T_4260[171] <= _T_4005 @[RegMapper.scala 154:24] + _T_4260[172] <= _T_4008 @[RegMapper.scala 154:24] + _T_4260[173] <= _T_4011 @[RegMapper.scala 154:24] + _T_4260[174] <= _T_4014 @[RegMapper.scala 154:24] + _T_4260[175] <= _T_4017 @[RegMapper.scala 154:24] + _T_4260[176] <= _T_4020 @[RegMapper.scala 154:24] + _T_4260[177] <= _T_4023 @[RegMapper.scala 154:24] + _T_4260[178] <= _T_4026 @[RegMapper.scala 154:24] + _T_4260[179] <= _T_4029 @[RegMapper.scala 154:24] + _T_4260[180] <= _T_4032 @[RegMapper.scala 154:24] + _T_4260[181] <= _T_4035 @[RegMapper.scala 154:24] + _T_4260[182] <= _T_4038 @[RegMapper.scala 154:24] + _T_4260[183] <= _T_4041 @[RegMapper.scala 154:24] + _T_4260[184] <= _T_4044 @[RegMapper.scala 154:24] + _T_4260[185] <= _T_4047 @[RegMapper.scala 154:24] + _T_4260[186] <= _T_4050 @[RegMapper.scala 154:24] + _T_4260[187] <= _T_4053 @[RegMapper.scala 154:24] + _T_4260[188] <= _T_4056 @[RegMapper.scala 154:24] + _T_4260[189] <= _T_4059 @[RegMapper.scala 154:24] + _T_4260[190] <= _T_4062 @[RegMapper.scala 154:24] + _T_4260[191] <= _T_4065 @[RegMapper.scala 154:24] + _T_4260[192] <= _T_4068 @[RegMapper.scala 154:24] + _T_4260[193] <= _T_4071 @[RegMapper.scala 154:24] + _T_4260[194] <= _T_4074 @[RegMapper.scala 154:24] + _T_4260[195] <= _T_4077 @[RegMapper.scala 154:24] + _T_4260[196] <= _T_4080 @[RegMapper.scala 154:24] + _T_4260[197] <= _T_4083 @[RegMapper.scala 154:24] + _T_4260[198] <= _T_4086 @[RegMapper.scala 154:24] + _T_4260[199] <= _T_4089 @[RegMapper.scala 154:24] + _T_4260[200] <= _T_4092 @[RegMapper.scala 154:24] + _T_4260[201] <= _T_4095 @[RegMapper.scala 154:24] + _T_4260[202] <= _T_4098 @[RegMapper.scala 154:24] + _T_4260[203] <= _T_4101 @[RegMapper.scala 154:24] + _T_4260[204] <= _T_4104 @[RegMapper.scala 154:24] + _T_4260[205] <= _T_4107 @[RegMapper.scala 154:24] + _T_4260[206] <= _T_4110 @[RegMapper.scala 154:24] + _T_4260[207] <= _T_4113 @[RegMapper.scala 154:24] + _T_4260[208] <= _T_4116 @[RegMapper.scala 154:24] + _T_4260[209] <= _T_4119 @[RegMapper.scala 154:24] + _T_4260[210] <= _T_4122 @[RegMapper.scala 154:24] + _T_4260[211] <= _T_4125 @[RegMapper.scala 154:24] + _T_4260[212] <= _T_4128 @[RegMapper.scala 154:24] + _T_4260[213] <= _T_4131 @[RegMapper.scala 154:24] + _T_4260[214] <= _T_4134 @[RegMapper.scala 154:24] + _T_4260[215] <= _T_4137 @[RegMapper.scala 154:24] + _T_4260[216] <= _T_4140 @[RegMapper.scala 154:24] + _T_4260[217] <= _T_4143 @[RegMapper.scala 154:24] + _T_4260[218] <= _T_4146 @[RegMapper.scala 154:24] + _T_4260[219] <= _T_4149 @[RegMapper.scala 154:24] + _T_4260[220] <= _T_4152 @[RegMapper.scala 154:24] + _T_4260[221] <= _T_4155 @[RegMapper.scala 154:24] + _T_4260[222] <= _T_4158 @[RegMapper.scala 154:24] + _T_4260[223] <= _T_4161 @[RegMapper.scala 154:24] + _T_4260[224] <= _T_4164 @[RegMapper.scala 154:24] + _T_4260[225] <= _T_4167 @[RegMapper.scala 154:24] + _T_4260[226] <= _T_4170 @[RegMapper.scala 154:24] + _T_4260[227] <= _T_4173 @[RegMapper.scala 154:24] + _T_4260[228] <= _T_4176 @[RegMapper.scala 154:24] + _T_4260[229] <= _T_4179 @[RegMapper.scala 154:24] + _T_4260[230] <= _T_4182 @[RegMapper.scala 154:24] + _T_4260[231] <= _T_4185 @[RegMapper.scala 154:24] + _T_4260[232] <= _T_4188 @[RegMapper.scala 154:24] + _T_4260[233] <= _T_4191 @[RegMapper.scala 154:24] + _T_4260[234] <= _T_4194 @[RegMapper.scala 154:24] + _T_4260[235] <= _T_4197 @[RegMapper.scala 154:24] + _T_4260[236] <= _T_4200 @[RegMapper.scala 154:24] + _T_4260[237] <= _T_4203 @[RegMapper.scala 154:24] + _T_4260[238] <= _T_4206 @[RegMapper.scala 154:24] + _T_4260[239] <= _T_4209 @[RegMapper.scala 154:24] + _T_4260[240] <= _T_4212 @[RegMapper.scala 154:24] + _T_4260[241] <= _T_4215 @[RegMapper.scala 154:24] + _T_4260[242] <= _T_4218 @[RegMapper.scala 154:24] + _T_4260[243] <= _T_4221 @[RegMapper.scala 154:24] + _T_4260[244] <= _T_4224 @[RegMapper.scala 154:24] + _T_4260[245] <= _T_4227 @[RegMapper.scala 154:24] + _T_4260[246] <= _T_4230 @[RegMapper.scala 154:24] + _T_4260[247] <= _T_4233 @[RegMapper.scala 154:24] + _T_4260[248] <= _T_4236 @[RegMapper.scala 154:24] + _T_4260[249] <= _T_4239 @[RegMapper.scala 154:24] + _T_4260[250] <= _T_4242 @[RegMapper.scala 154:24] + _T_4260[251] <= _T_4245 @[RegMapper.scala 154:24] + _T_4260[252] <= _T_4248 @[RegMapper.scala 154:24] + _T_4260[253] <= _T_4251 @[RegMapper.scala 154:24] + _T_4260[254] <= _T_4254 @[RegMapper.scala 154:24] + _T_4260[255] <= _T_4257 @[RegMapper.scala 154:24] + node _T_4520 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4521 = and(_T_1299[4], _T_1299[3]) @[RegMapper.scala 155:98] + node _T_4522 = and(_T_4521, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4523 = or(_T_4520, _T_4522) @[RegMapper.scala 155:82] + node _T_4525 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4526 = and(_T_1299[8], UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4527 = or(_T_4525, _T_4526) @[RegMapper.scala 155:82] + node _T_4529 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4530 = or(_T_4529, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4532 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4533 = or(_T_4532, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4535 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4536 = or(_T_4535, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4538 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4539 = or(_T_4538, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4541 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4542 = or(_T_4541, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4544 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4545 = or(_T_4544, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4547 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4548 = or(_T_4547, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4550 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4551 = or(_T_4550, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4553 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4554 = or(_T_4553, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4556 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4557 = or(_T_4556, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4559 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4560 = or(_T_4559, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4562 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4563 = or(_T_4562, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4565 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4566 = or(_T_4565, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4568 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4569 = or(_T_4568, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4571 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4572 = or(_T_4571, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4574 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4575 = or(_T_4574, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4577 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4578 = or(_T_4577, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4580 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4581 = or(_T_4580, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4583 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4584 = or(_T_4583, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4586 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4587 = or(_T_4586, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4589 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4590 = or(_T_4589, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4592 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4593 = or(_T_4592, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4595 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4596 = or(_T_4595, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4598 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4599 = or(_T_4598, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4601 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4602 = or(_T_4601, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4604 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4605 = or(_T_4604, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4607 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4608 = or(_T_4607, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4610 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4611 = or(_T_4610, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4613 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4614 = or(_T_4613, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4616 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4617 = or(_T_4616, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4619 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4620 = and(_T_1299[11], _T_1299[10]) @[RegMapper.scala 155:98] + node _T_4621 = and(_T_4620, _T_1299[9]) @[RegMapper.scala 155:98] + node _T_4622 = and(_T_4621, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4623 = or(_T_4619, _T_4622) @[RegMapper.scala 155:82] + node _T_4625 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4626 = or(_T_4625, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4628 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4629 = or(_T_4628, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4631 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4632 = or(_T_4631, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4634 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4635 = or(_T_4634, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4637 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4638 = or(_T_4637, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4640 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4641 = or(_T_4640, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4643 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4644 = or(_T_4643, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4646 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4647 = or(_T_4646, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4649 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4650 = or(_T_4649, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4652 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4653 = or(_T_4652, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4656 = or(_T_4655, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4658 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4659 = or(_T_4658, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4661 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4662 = or(_T_4661, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4664 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4665 = or(_T_4664, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4667 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4668 = or(_T_4667, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4670 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4671 = or(_T_4670, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4673 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4674 = or(_T_4673, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4676 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4677 = or(_T_4676, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4679 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4680 = or(_T_4679, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4682 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4683 = or(_T_4682, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4685 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4686 = or(_T_4685, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4688 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4689 = or(_T_4688, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4691 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4692 = or(_T_4691, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4694 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4695 = or(_T_4694, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4697 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4698 = or(_T_4697, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4700 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4701 = or(_T_4700, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4703 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4704 = or(_T_4703, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4706 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4707 = or(_T_4706, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4709 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4710 = or(_T_4709, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4712 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4713 = or(_T_4712, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4715 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4716 = or(_T_4715, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4718 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4719 = and(_T_1299[2], _T_1299[1]) @[RegMapper.scala 155:98] + node _T_4720 = and(_T_4719, _T_1299[0]) @[RegMapper.scala 155:98] + node _T_4721 = and(_T_4720, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4722 = or(_T_4718, _T_4721) @[RegMapper.scala 155:82] + node _T_4724 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4725 = or(_T_4724, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4727 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4728 = or(_T_4727, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4730 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4731 = or(_T_4730, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4733 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4734 = or(_T_4733, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4736 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4737 = or(_T_4736, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4739 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4740 = or(_T_4739, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4742 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4743 = or(_T_4742, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4745 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4746 = or(_T_4745, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4748 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4749 = or(_T_4748, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4751 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4752 = or(_T_4751, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4755 = or(_T_4754, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4757 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4758 = or(_T_4757, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4760 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4761 = or(_T_4760, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4763 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4764 = or(_T_4763, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4766 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4767 = or(_T_4766, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4769 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4770 = and(_T_1299[7], _T_1299[6]) @[RegMapper.scala 155:98] + node _T_4771 = and(_T_4770, _T_1299[5]) @[RegMapper.scala 155:98] + node _T_4772 = and(_T_4771, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4773 = or(_T_4769, _T_4772) @[RegMapper.scala 155:82] + node _T_4775 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4776 = or(_T_4775, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4778 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4779 = or(_T_4778, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4781 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4782 = or(_T_4781, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4784 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4785 = or(_T_4784, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4787 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4788 = or(_T_4787, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4790 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4791 = or(_T_4790, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4793 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4794 = or(_T_4793, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4796 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4797 = or(_T_4796, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4799 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4800 = or(_T_4799, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4802 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4803 = or(_T_4802, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4805 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4806 = or(_T_4805, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4808 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4809 = or(_T_4808, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4811 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4812 = or(_T_4811, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4814 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4815 = or(_T_4814, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4817 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4818 = or(_T_4817, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4820 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4821 = or(_T_4820, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4823 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4824 = or(_T_4823, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4826 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4827 = or(_T_4826, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4829 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4830 = or(_T_4829, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4832 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4833 = or(_T_4832, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4835 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4836 = or(_T_4835, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4838 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4839 = or(_T_4838, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4841 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4842 = or(_T_4841, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4844 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4845 = or(_T_4844, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4847 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4848 = or(_T_4847, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4850 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4851 = or(_T_4850, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4853 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4854 = or(_T_4853, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4856 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4857 = or(_T_4856, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4859 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4860 = or(_T_4859, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4862 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4863 = or(_T_4862, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4865 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4866 = or(_T_4865, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4868 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4869 = or(_T_4868, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4871 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4872 = or(_T_4871, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4874 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4875 = or(_T_4874, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4877 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4878 = or(_T_4877, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4880 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4881 = or(_T_4880, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4883 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4884 = or(_T_4883, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4886 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4887 = or(_T_4886, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4889 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4890 = or(_T_4889, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4892 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4893 = or(_T_4892, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4895 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4896 = or(_T_4895, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4898 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4899 = or(_T_4898, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4901 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4902 = or(_T_4901, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4904 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4905 = or(_T_4904, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4907 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4908 = or(_T_4907, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4910 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4911 = or(_T_4910, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4913 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4914 = or(_T_4913, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4916 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4917 = and(_T_1299[15], _T_1299[14]) @[RegMapper.scala 155:98] + node _T_4918 = and(_T_4917, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_4919 = or(_T_4916, _T_4918) @[RegMapper.scala 155:82] + node _T_4921 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4922 = or(_T_4921, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4924 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4925 = or(_T_4924, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4927 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4928 = or(_T_4927, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4930 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4931 = or(_T_4930, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4933 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4934 = or(_T_4933, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4936 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4937 = or(_T_4936, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4939 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4940 = or(_T_4939, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4942 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4943 = or(_T_4942, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4945 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4946 = or(_T_4945, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4948 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4949 = or(_T_4948, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4951 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4952 = or(_T_4951, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4954 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4955 = or(_T_4954, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4957 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4958 = or(_T_4957, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4960 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4961 = or(_T_4960, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4963 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4964 = or(_T_4963, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4966 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4967 = or(_T_4966, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4969 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4970 = or(_T_4969, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4972 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4973 = or(_T_4972, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4975 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4976 = or(_T_4975, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4978 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4979 = or(_T_4978, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4981 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4982 = or(_T_4981, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4984 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4985 = or(_T_4984, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4987 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4988 = or(_T_4987, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4990 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4991 = or(_T_4990, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4993 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4994 = or(_T_4993, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4996 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_4997 = or(_T_4996, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_4999 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5000 = or(_T_4999, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5002 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5003 = or(_T_5002, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5005 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5006 = or(_T_5005, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5008 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5009 = or(_T_5008, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5011 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5012 = or(_T_5011, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5014 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5015 = and(_T_1299[13], _T_1299[12]) @[RegMapper.scala 155:98] + node _T_5016 = and(_T_5015, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_5017 = or(_T_5014, _T_5016) @[RegMapper.scala 155:82] + node _T_5019 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5020 = or(_T_5019, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5022 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5023 = or(_T_5022, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5025 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5026 = or(_T_5025, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5028 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5029 = or(_T_5028, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5031 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5032 = or(_T_5031, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5034 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5035 = or(_T_5034, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5037 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5038 = or(_T_5037, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5040 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5041 = or(_T_5040, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5043 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5044 = or(_T_5043, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5046 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5047 = or(_T_5046, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5049 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5050 = or(_T_5049, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5052 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5053 = or(_T_5052, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5055 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5056 = or(_T_5055, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5058 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5059 = or(_T_5058, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5061 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5062 = or(_T_5061, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5064 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5065 = or(_T_5064, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5067 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5068 = or(_T_5067, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5070 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5071 = or(_T_5070, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5073 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5074 = or(_T_5073, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5076 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5077 = or(_T_5076, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5079 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5080 = or(_T_5079, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5082 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5083 = or(_T_5082, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5085 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5086 = or(_T_5085, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5088 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5089 = or(_T_5088, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5091 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5092 = or(_T_5091, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5094 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5095 = or(_T_5094, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5097 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5098 = or(_T_5097, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5100 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5101 = or(_T_5100, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5103 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5104 = or(_T_5103, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5106 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5107 = or(_T_5106, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5109 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5110 = or(_T_5109, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5112 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5113 = or(_T_5112, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5115 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5116 = or(_T_5115, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5118 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5119 = or(_T_5118, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5121 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5122 = or(_T_5121, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5124 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5125 = or(_T_5124, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5127 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5128 = or(_T_5127, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5130 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5131 = or(_T_5130, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5133 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5134 = or(_T_5133, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5136 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5137 = or(_T_5136, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5139 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5140 = or(_T_5139, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5142 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5143 = or(_T_5142, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5145 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5146 = or(_T_5145, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5148 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5149 = or(_T_5148, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5151 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5152 = or(_T_5151, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5154 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5155 = or(_T_5154, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5157 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5158 = or(_T_5157, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5160 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5161 = or(_T_5160, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5163 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5164 = or(_T_5163, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5166 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5167 = or(_T_5166, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5169 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5170 = or(_T_5169, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5172 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5173 = or(_T_5172, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5175 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5176 = or(_T_5175, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5178 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5179 = or(_T_5178, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5181 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5182 = or(_T_5181, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5184 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5185 = or(_T_5184, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5187 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5188 = or(_T_5187, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5190 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5191 = or(_T_5190, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5193 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5194 = or(_T_5193, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5196 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5197 = or(_T_5196, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5199 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5200 = or(_T_5199, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5202 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5203 = or(_T_5202, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5205 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5206 = or(_T_5205, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5208 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5209 = or(_T_5208, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5211 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5212 = or(_T_5211, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5214 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5215 = or(_T_5214, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5217 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5218 = or(_T_5217, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5220 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5221 = or(_T_5220, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5223 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5224 = or(_T_5223, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5226 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5227 = or(_T_5226, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5229 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5230 = or(_T_5229, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5232 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5233 = or(_T_5232, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5235 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5236 = or(_T_5235, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5238 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5239 = or(_T_5238, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5241 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5242 = or(_T_5241, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5244 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5245 = or(_T_5244, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5247 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5248 = or(_T_5247, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5250 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5251 = or(_T_5250, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5253 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5254 = or(_T_5253, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5256 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5257 = or(_T_5256, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5259 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5260 = or(_T_5259, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5262 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5263 = or(_T_5262, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5265 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5266 = or(_T_5265, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5268 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5269 = or(_T_5268, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5271 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5272 = or(_T_5271, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5274 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5275 = or(_T_5274, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5277 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5278 = or(_T_5277, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5280 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5281 = or(_T_5280, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5283 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5284 = or(_T_5283, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5286 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5287 = or(_T_5286, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5289 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5290 = or(_T_5289, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5292 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5293 = or(_T_5292, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5295 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5296 = or(_T_5295, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5298 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5299 = or(_T_5298, UInt<1>("h01")) @[RegMapper.scala 155:82] + node _T_5301 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_5302 = or(_T_5301, UInt<1>("h01")) @[RegMapper.scala 155:82] + wire _T_5305 : UInt<1>[256] @[RegMapper.scala 155:24] + _T_5305 is invalid @[RegMapper.scala 155:24] + _T_5305[0] <= _T_4523 @[RegMapper.scala 155:24] + _T_5305[1] <= _T_4527 @[RegMapper.scala 155:24] + _T_5305[2] <= _T_4530 @[RegMapper.scala 155:24] + _T_5305[3] <= _T_4533 @[RegMapper.scala 155:24] + _T_5305[4] <= _T_4536 @[RegMapper.scala 155:24] + _T_5305[5] <= _T_4539 @[RegMapper.scala 155:24] + _T_5305[6] <= _T_4542 @[RegMapper.scala 155:24] + _T_5305[7] <= _T_4545 @[RegMapper.scala 155:24] + _T_5305[8] <= _T_4548 @[RegMapper.scala 155:24] + _T_5305[9] <= _T_4551 @[RegMapper.scala 155:24] + _T_5305[10] <= _T_4554 @[RegMapper.scala 155:24] + _T_5305[11] <= _T_4557 @[RegMapper.scala 155:24] + _T_5305[12] <= _T_4560 @[RegMapper.scala 155:24] + _T_5305[13] <= _T_4563 @[RegMapper.scala 155:24] + _T_5305[14] <= _T_4566 @[RegMapper.scala 155:24] + _T_5305[15] <= _T_4569 @[RegMapper.scala 155:24] + _T_5305[16] <= _T_4572 @[RegMapper.scala 155:24] + _T_5305[17] <= _T_4575 @[RegMapper.scala 155:24] + _T_5305[18] <= _T_4578 @[RegMapper.scala 155:24] + _T_5305[19] <= _T_4581 @[RegMapper.scala 155:24] + _T_5305[20] <= _T_4584 @[RegMapper.scala 155:24] + _T_5305[21] <= _T_4587 @[RegMapper.scala 155:24] + _T_5305[22] <= _T_4590 @[RegMapper.scala 155:24] + _T_5305[23] <= _T_4593 @[RegMapper.scala 155:24] + _T_5305[24] <= _T_4596 @[RegMapper.scala 155:24] + _T_5305[25] <= _T_4599 @[RegMapper.scala 155:24] + _T_5305[26] <= _T_4602 @[RegMapper.scala 155:24] + _T_5305[27] <= _T_4605 @[RegMapper.scala 155:24] + _T_5305[28] <= _T_4608 @[RegMapper.scala 155:24] + _T_5305[29] <= _T_4611 @[RegMapper.scala 155:24] + _T_5305[30] <= _T_4614 @[RegMapper.scala 155:24] + _T_5305[31] <= _T_4617 @[RegMapper.scala 155:24] + _T_5305[32] <= _T_4623 @[RegMapper.scala 155:24] + _T_5305[33] <= _T_4626 @[RegMapper.scala 155:24] + _T_5305[34] <= _T_4629 @[RegMapper.scala 155:24] + _T_5305[35] <= _T_4632 @[RegMapper.scala 155:24] + _T_5305[36] <= _T_4635 @[RegMapper.scala 155:24] + _T_5305[37] <= _T_4638 @[RegMapper.scala 155:24] + _T_5305[38] <= _T_4641 @[RegMapper.scala 155:24] + _T_5305[39] <= _T_4644 @[RegMapper.scala 155:24] + _T_5305[40] <= _T_4647 @[RegMapper.scala 155:24] + _T_5305[41] <= _T_4650 @[RegMapper.scala 155:24] + _T_5305[42] <= _T_4653 @[RegMapper.scala 155:24] + _T_5305[43] <= _T_4656 @[RegMapper.scala 155:24] + _T_5305[44] <= _T_4659 @[RegMapper.scala 155:24] + _T_5305[45] <= _T_4662 @[RegMapper.scala 155:24] + _T_5305[46] <= _T_4665 @[RegMapper.scala 155:24] + _T_5305[47] <= _T_4668 @[RegMapper.scala 155:24] + _T_5305[48] <= _T_4671 @[RegMapper.scala 155:24] + _T_5305[49] <= _T_4674 @[RegMapper.scala 155:24] + _T_5305[50] <= _T_4677 @[RegMapper.scala 155:24] + _T_5305[51] <= _T_4680 @[RegMapper.scala 155:24] + _T_5305[52] <= _T_4683 @[RegMapper.scala 155:24] + _T_5305[53] <= _T_4686 @[RegMapper.scala 155:24] + _T_5305[54] <= _T_4689 @[RegMapper.scala 155:24] + _T_5305[55] <= _T_4692 @[RegMapper.scala 155:24] + _T_5305[56] <= _T_4695 @[RegMapper.scala 155:24] + _T_5305[57] <= _T_4698 @[RegMapper.scala 155:24] + _T_5305[58] <= _T_4701 @[RegMapper.scala 155:24] + _T_5305[59] <= _T_4704 @[RegMapper.scala 155:24] + _T_5305[60] <= _T_4707 @[RegMapper.scala 155:24] + _T_5305[61] <= _T_4710 @[RegMapper.scala 155:24] + _T_5305[62] <= _T_4713 @[RegMapper.scala 155:24] + _T_5305[63] <= _T_4716 @[RegMapper.scala 155:24] + _T_5305[64] <= _T_4722 @[RegMapper.scala 155:24] + _T_5305[65] <= _T_4725 @[RegMapper.scala 155:24] + _T_5305[66] <= _T_4728 @[RegMapper.scala 155:24] + _T_5305[67] <= _T_4731 @[RegMapper.scala 155:24] + _T_5305[68] <= _T_4734 @[RegMapper.scala 155:24] + _T_5305[69] <= _T_4737 @[RegMapper.scala 155:24] + _T_5305[70] <= _T_4740 @[RegMapper.scala 155:24] + _T_5305[71] <= _T_4743 @[RegMapper.scala 155:24] + _T_5305[72] <= _T_4746 @[RegMapper.scala 155:24] + _T_5305[73] <= _T_4749 @[RegMapper.scala 155:24] + _T_5305[74] <= _T_4752 @[RegMapper.scala 155:24] + _T_5305[75] <= _T_4755 @[RegMapper.scala 155:24] + _T_5305[76] <= _T_4758 @[RegMapper.scala 155:24] + _T_5305[77] <= _T_4761 @[RegMapper.scala 155:24] + _T_5305[78] <= _T_4764 @[RegMapper.scala 155:24] + _T_5305[79] <= _T_4767 @[RegMapper.scala 155:24] + _T_5305[80] <= _T_4773 @[RegMapper.scala 155:24] + _T_5305[81] <= _T_4776 @[RegMapper.scala 155:24] + _T_5305[82] <= _T_4779 @[RegMapper.scala 155:24] + _T_5305[83] <= _T_4782 @[RegMapper.scala 155:24] + _T_5305[84] <= _T_4785 @[RegMapper.scala 155:24] + _T_5305[85] <= _T_4788 @[RegMapper.scala 155:24] + _T_5305[86] <= _T_4791 @[RegMapper.scala 155:24] + _T_5305[87] <= _T_4794 @[RegMapper.scala 155:24] + _T_5305[88] <= _T_4797 @[RegMapper.scala 155:24] + _T_5305[89] <= _T_4800 @[RegMapper.scala 155:24] + _T_5305[90] <= _T_4803 @[RegMapper.scala 155:24] + _T_5305[91] <= _T_4806 @[RegMapper.scala 155:24] + _T_5305[92] <= _T_4809 @[RegMapper.scala 155:24] + _T_5305[93] <= _T_4812 @[RegMapper.scala 155:24] + _T_5305[94] <= _T_4815 @[RegMapper.scala 155:24] + _T_5305[95] <= _T_4818 @[RegMapper.scala 155:24] + _T_5305[96] <= _T_4821 @[RegMapper.scala 155:24] + _T_5305[97] <= _T_4824 @[RegMapper.scala 155:24] + _T_5305[98] <= _T_4827 @[RegMapper.scala 155:24] + _T_5305[99] <= _T_4830 @[RegMapper.scala 155:24] + _T_5305[100] <= _T_4833 @[RegMapper.scala 155:24] + _T_5305[101] <= _T_4836 @[RegMapper.scala 155:24] + _T_5305[102] <= _T_4839 @[RegMapper.scala 155:24] + _T_5305[103] <= _T_4842 @[RegMapper.scala 155:24] + _T_5305[104] <= _T_4845 @[RegMapper.scala 155:24] + _T_5305[105] <= _T_4848 @[RegMapper.scala 155:24] + _T_5305[106] <= _T_4851 @[RegMapper.scala 155:24] + _T_5305[107] <= _T_4854 @[RegMapper.scala 155:24] + _T_5305[108] <= _T_4857 @[RegMapper.scala 155:24] + _T_5305[109] <= _T_4860 @[RegMapper.scala 155:24] + _T_5305[110] <= _T_4863 @[RegMapper.scala 155:24] + _T_5305[111] <= _T_4866 @[RegMapper.scala 155:24] + _T_5305[112] <= _T_4869 @[RegMapper.scala 155:24] + _T_5305[113] <= _T_4872 @[RegMapper.scala 155:24] + _T_5305[114] <= _T_4875 @[RegMapper.scala 155:24] + _T_5305[115] <= _T_4878 @[RegMapper.scala 155:24] + _T_5305[116] <= _T_4881 @[RegMapper.scala 155:24] + _T_5305[117] <= _T_4884 @[RegMapper.scala 155:24] + _T_5305[118] <= _T_4887 @[RegMapper.scala 155:24] + _T_5305[119] <= _T_4890 @[RegMapper.scala 155:24] + _T_5305[120] <= _T_4893 @[RegMapper.scala 155:24] + _T_5305[121] <= _T_4896 @[RegMapper.scala 155:24] + _T_5305[122] <= _T_4899 @[RegMapper.scala 155:24] + _T_5305[123] <= _T_4902 @[RegMapper.scala 155:24] + _T_5305[124] <= _T_4905 @[RegMapper.scala 155:24] + _T_5305[125] <= _T_4908 @[RegMapper.scala 155:24] + _T_5305[126] <= _T_4911 @[RegMapper.scala 155:24] + _T_5305[127] <= _T_4914 @[RegMapper.scala 155:24] + _T_5305[128] <= _T_4919 @[RegMapper.scala 155:24] + _T_5305[129] <= _T_4922 @[RegMapper.scala 155:24] + _T_5305[130] <= _T_4925 @[RegMapper.scala 155:24] + _T_5305[131] <= _T_4928 @[RegMapper.scala 155:24] + _T_5305[132] <= _T_4931 @[RegMapper.scala 155:24] + _T_5305[133] <= _T_4934 @[RegMapper.scala 155:24] + _T_5305[134] <= _T_4937 @[RegMapper.scala 155:24] + _T_5305[135] <= _T_4940 @[RegMapper.scala 155:24] + _T_5305[136] <= _T_4943 @[RegMapper.scala 155:24] + _T_5305[137] <= _T_4946 @[RegMapper.scala 155:24] + _T_5305[138] <= _T_4949 @[RegMapper.scala 155:24] + _T_5305[139] <= _T_4952 @[RegMapper.scala 155:24] + _T_5305[140] <= _T_4955 @[RegMapper.scala 155:24] + _T_5305[141] <= _T_4958 @[RegMapper.scala 155:24] + _T_5305[142] <= _T_4961 @[RegMapper.scala 155:24] + _T_5305[143] <= _T_4964 @[RegMapper.scala 155:24] + _T_5305[144] <= _T_4967 @[RegMapper.scala 155:24] + _T_5305[145] <= _T_4970 @[RegMapper.scala 155:24] + _T_5305[146] <= _T_4973 @[RegMapper.scala 155:24] + _T_5305[147] <= _T_4976 @[RegMapper.scala 155:24] + _T_5305[148] <= _T_4979 @[RegMapper.scala 155:24] + _T_5305[149] <= _T_4982 @[RegMapper.scala 155:24] + _T_5305[150] <= _T_4985 @[RegMapper.scala 155:24] + _T_5305[151] <= _T_4988 @[RegMapper.scala 155:24] + _T_5305[152] <= _T_4991 @[RegMapper.scala 155:24] + _T_5305[153] <= _T_4994 @[RegMapper.scala 155:24] + _T_5305[154] <= _T_4997 @[RegMapper.scala 155:24] + _T_5305[155] <= _T_5000 @[RegMapper.scala 155:24] + _T_5305[156] <= _T_5003 @[RegMapper.scala 155:24] + _T_5305[157] <= _T_5006 @[RegMapper.scala 155:24] + _T_5305[158] <= _T_5009 @[RegMapper.scala 155:24] + _T_5305[159] <= _T_5012 @[RegMapper.scala 155:24] + _T_5305[160] <= _T_5017 @[RegMapper.scala 155:24] + _T_5305[161] <= _T_5020 @[RegMapper.scala 155:24] + _T_5305[162] <= _T_5023 @[RegMapper.scala 155:24] + _T_5305[163] <= _T_5026 @[RegMapper.scala 155:24] + _T_5305[164] <= _T_5029 @[RegMapper.scala 155:24] + _T_5305[165] <= _T_5032 @[RegMapper.scala 155:24] + _T_5305[166] <= _T_5035 @[RegMapper.scala 155:24] + _T_5305[167] <= _T_5038 @[RegMapper.scala 155:24] + _T_5305[168] <= _T_5041 @[RegMapper.scala 155:24] + _T_5305[169] <= _T_5044 @[RegMapper.scala 155:24] + _T_5305[170] <= _T_5047 @[RegMapper.scala 155:24] + _T_5305[171] <= _T_5050 @[RegMapper.scala 155:24] + _T_5305[172] <= _T_5053 @[RegMapper.scala 155:24] + _T_5305[173] <= _T_5056 @[RegMapper.scala 155:24] + _T_5305[174] <= _T_5059 @[RegMapper.scala 155:24] + _T_5305[175] <= _T_5062 @[RegMapper.scala 155:24] + _T_5305[176] <= _T_5065 @[RegMapper.scala 155:24] + _T_5305[177] <= _T_5068 @[RegMapper.scala 155:24] + _T_5305[178] <= _T_5071 @[RegMapper.scala 155:24] + _T_5305[179] <= _T_5074 @[RegMapper.scala 155:24] + _T_5305[180] <= _T_5077 @[RegMapper.scala 155:24] + _T_5305[181] <= _T_5080 @[RegMapper.scala 155:24] + _T_5305[182] <= _T_5083 @[RegMapper.scala 155:24] + _T_5305[183] <= _T_5086 @[RegMapper.scala 155:24] + _T_5305[184] <= _T_5089 @[RegMapper.scala 155:24] + _T_5305[185] <= _T_5092 @[RegMapper.scala 155:24] + _T_5305[186] <= _T_5095 @[RegMapper.scala 155:24] + _T_5305[187] <= _T_5098 @[RegMapper.scala 155:24] + _T_5305[188] <= _T_5101 @[RegMapper.scala 155:24] + _T_5305[189] <= _T_5104 @[RegMapper.scala 155:24] + _T_5305[190] <= _T_5107 @[RegMapper.scala 155:24] + _T_5305[191] <= _T_5110 @[RegMapper.scala 155:24] + _T_5305[192] <= _T_5113 @[RegMapper.scala 155:24] + _T_5305[193] <= _T_5116 @[RegMapper.scala 155:24] + _T_5305[194] <= _T_5119 @[RegMapper.scala 155:24] + _T_5305[195] <= _T_5122 @[RegMapper.scala 155:24] + _T_5305[196] <= _T_5125 @[RegMapper.scala 155:24] + _T_5305[197] <= _T_5128 @[RegMapper.scala 155:24] + _T_5305[198] <= _T_5131 @[RegMapper.scala 155:24] + _T_5305[199] <= _T_5134 @[RegMapper.scala 155:24] + _T_5305[200] <= _T_5137 @[RegMapper.scala 155:24] + _T_5305[201] <= _T_5140 @[RegMapper.scala 155:24] + _T_5305[202] <= _T_5143 @[RegMapper.scala 155:24] + _T_5305[203] <= _T_5146 @[RegMapper.scala 155:24] + _T_5305[204] <= _T_5149 @[RegMapper.scala 155:24] + _T_5305[205] <= _T_5152 @[RegMapper.scala 155:24] + _T_5305[206] <= _T_5155 @[RegMapper.scala 155:24] + _T_5305[207] <= _T_5158 @[RegMapper.scala 155:24] + _T_5305[208] <= _T_5161 @[RegMapper.scala 155:24] + _T_5305[209] <= _T_5164 @[RegMapper.scala 155:24] + _T_5305[210] <= _T_5167 @[RegMapper.scala 155:24] + _T_5305[211] <= _T_5170 @[RegMapper.scala 155:24] + _T_5305[212] <= _T_5173 @[RegMapper.scala 155:24] + _T_5305[213] <= _T_5176 @[RegMapper.scala 155:24] + _T_5305[214] <= _T_5179 @[RegMapper.scala 155:24] + _T_5305[215] <= _T_5182 @[RegMapper.scala 155:24] + _T_5305[216] <= _T_5185 @[RegMapper.scala 155:24] + _T_5305[217] <= _T_5188 @[RegMapper.scala 155:24] + _T_5305[218] <= _T_5191 @[RegMapper.scala 155:24] + _T_5305[219] <= _T_5194 @[RegMapper.scala 155:24] + _T_5305[220] <= _T_5197 @[RegMapper.scala 155:24] + _T_5305[221] <= _T_5200 @[RegMapper.scala 155:24] + _T_5305[222] <= _T_5203 @[RegMapper.scala 155:24] + _T_5305[223] <= _T_5206 @[RegMapper.scala 155:24] + _T_5305[224] <= _T_5209 @[RegMapper.scala 155:24] + _T_5305[225] <= _T_5212 @[RegMapper.scala 155:24] + _T_5305[226] <= _T_5215 @[RegMapper.scala 155:24] + _T_5305[227] <= _T_5218 @[RegMapper.scala 155:24] + _T_5305[228] <= _T_5221 @[RegMapper.scala 155:24] + _T_5305[229] <= _T_5224 @[RegMapper.scala 155:24] + _T_5305[230] <= _T_5227 @[RegMapper.scala 155:24] + _T_5305[231] <= _T_5230 @[RegMapper.scala 155:24] + _T_5305[232] <= _T_5233 @[RegMapper.scala 155:24] + _T_5305[233] <= _T_5236 @[RegMapper.scala 155:24] + _T_5305[234] <= _T_5239 @[RegMapper.scala 155:24] + _T_5305[235] <= _T_5242 @[RegMapper.scala 155:24] + _T_5305[236] <= _T_5245 @[RegMapper.scala 155:24] + _T_5305[237] <= _T_5248 @[RegMapper.scala 155:24] + _T_5305[238] <= _T_5251 @[RegMapper.scala 155:24] + _T_5305[239] <= _T_5254 @[RegMapper.scala 155:24] + _T_5305[240] <= _T_5257 @[RegMapper.scala 155:24] + _T_5305[241] <= _T_5260 @[RegMapper.scala 155:24] + _T_5305[242] <= _T_5263 @[RegMapper.scala 155:24] + _T_5305[243] <= _T_5266 @[RegMapper.scala 155:24] + _T_5305[244] <= _T_5269 @[RegMapper.scala 155:24] + _T_5305[245] <= _T_5272 @[RegMapper.scala 155:24] + _T_5305[246] <= _T_5275 @[RegMapper.scala 155:24] + _T_5305[247] <= _T_5278 @[RegMapper.scala 155:24] + _T_5305[248] <= _T_5281 @[RegMapper.scala 155:24] + _T_5305[249] <= _T_5284 @[RegMapper.scala 155:24] + _T_5305[250] <= _T_5287 @[RegMapper.scala 155:24] + _T_5305[251] <= _T_5290 @[RegMapper.scala 155:24] + _T_5305[252] <= _T_5293 @[RegMapper.scala 155:24] + _T_5305[253] <= _T_5296 @[RegMapper.scala 155:24] + _T_5305[254] <= _T_5299 @[RegMapper.scala 155:24] + _T_5305[255] <= _T_5302 @[RegMapper.scala 155:24] + node _T_5565 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5566 = and(_T_1321[4], _T_1321[3]) @[RegMapper.scala 156:98] + node _T_5567 = and(_T_5566, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5568 = or(_T_5565, _T_5567) @[RegMapper.scala 156:82] + node _T_5570 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5571 = and(_T_1321[8], UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5572 = or(_T_5570, _T_5571) @[RegMapper.scala 156:82] + node _T_5574 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5575 = or(_T_5574, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5577 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5578 = or(_T_5577, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5580 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5581 = or(_T_5580, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5583 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5584 = or(_T_5583, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5586 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5587 = or(_T_5586, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5589 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5590 = or(_T_5589, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5592 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5593 = or(_T_5592, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5595 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5596 = or(_T_5595, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5598 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5599 = or(_T_5598, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5601 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5602 = or(_T_5601, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5604 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5605 = or(_T_5604, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5607 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5608 = or(_T_5607, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5610 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5611 = or(_T_5610, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5613 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5614 = or(_T_5613, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5616 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5617 = or(_T_5616, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5619 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5620 = or(_T_5619, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5622 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5623 = or(_T_5622, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5625 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5626 = or(_T_5625, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5628 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5629 = or(_T_5628, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5631 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5632 = or(_T_5631, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5634 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5635 = or(_T_5634, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5637 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5638 = or(_T_5637, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5640 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5641 = or(_T_5640, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5643 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5644 = or(_T_5643, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5646 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5647 = or(_T_5646, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5649 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5650 = or(_T_5649, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5652 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5653 = or(_T_5652, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5656 = or(_T_5655, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5658 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5659 = or(_T_5658, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5661 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5662 = or(_T_5661, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5664 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5665 = and(_T_1321[11], _T_1321[10]) @[RegMapper.scala 156:98] + node _T_5666 = and(_T_5665, _T_1321[9]) @[RegMapper.scala 156:98] + node _T_5667 = and(_T_5666, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5668 = or(_T_5664, _T_5667) @[RegMapper.scala 156:82] + node _T_5670 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5671 = or(_T_5670, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5673 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5674 = or(_T_5673, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5676 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5677 = or(_T_5676, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5679 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5680 = or(_T_5679, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5682 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5683 = or(_T_5682, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5685 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5686 = or(_T_5685, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5688 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5689 = or(_T_5688, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5691 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5692 = or(_T_5691, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5694 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5695 = or(_T_5694, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5697 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5698 = or(_T_5697, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5700 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5701 = or(_T_5700, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5703 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5704 = or(_T_5703, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5706 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5707 = or(_T_5706, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5709 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5710 = or(_T_5709, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5712 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5713 = or(_T_5712, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5715 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5716 = or(_T_5715, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5718 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5719 = or(_T_5718, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5721 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5722 = or(_T_5721, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5724 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5725 = or(_T_5724, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5727 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5728 = or(_T_5727, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5730 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5731 = or(_T_5730, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5733 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5734 = or(_T_5733, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5736 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5737 = or(_T_5736, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5739 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5740 = or(_T_5739, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5742 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5743 = or(_T_5742, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5745 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5746 = or(_T_5745, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5748 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5749 = or(_T_5748, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5751 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5752 = or(_T_5751, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5755 = or(_T_5754, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5757 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5758 = or(_T_5757, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5760 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5761 = or(_T_5760, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5763 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5764 = and(_T_1321[2], _T_1321[1]) @[RegMapper.scala 156:98] + node _T_5765 = and(_T_5764, _T_1321[0]) @[RegMapper.scala 156:98] + node _T_5766 = and(_T_5765, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5767 = or(_T_5763, _T_5766) @[RegMapper.scala 156:82] + node _T_5769 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5770 = or(_T_5769, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5772 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5773 = or(_T_5772, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5775 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5776 = or(_T_5775, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5778 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5779 = or(_T_5778, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5781 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5782 = or(_T_5781, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5784 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5785 = or(_T_5784, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5787 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5788 = or(_T_5787, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5790 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5791 = or(_T_5790, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5793 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5794 = or(_T_5793, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5796 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5797 = or(_T_5796, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5799 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5800 = or(_T_5799, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5802 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5803 = or(_T_5802, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5805 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5806 = or(_T_5805, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5808 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5809 = or(_T_5808, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5811 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5812 = or(_T_5811, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5814 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5815 = and(_T_1321[7], _T_1321[6]) @[RegMapper.scala 156:98] + node _T_5816 = and(_T_5815, _T_1321[5]) @[RegMapper.scala 156:98] + node _T_5817 = and(_T_5816, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5818 = or(_T_5814, _T_5817) @[RegMapper.scala 156:82] + node _T_5820 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5821 = or(_T_5820, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5823 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5824 = or(_T_5823, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5826 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5827 = or(_T_5826, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5829 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5830 = or(_T_5829, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5832 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5833 = or(_T_5832, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5835 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5836 = or(_T_5835, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5838 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5839 = or(_T_5838, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5841 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5842 = or(_T_5841, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5844 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5845 = or(_T_5844, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5847 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5848 = or(_T_5847, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5850 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5851 = or(_T_5850, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5853 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5854 = or(_T_5853, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5856 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5857 = or(_T_5856, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5859 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5860 = or(_T_5859, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5862 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5863 = or(_T_5862, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5865 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5866 = or(_T_5865, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5868 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5869 = or(_T_5868, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5871 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5872 = or(_T_5871, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5874 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5875 = or(_T_5874, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5877 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5878 = or(_T_5877, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5880 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5881 = or(_T_5880, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5883 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5884 = or(_T_5883, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5886 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5887 = or(_T_5886, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5889 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5890 = or(_T_5889, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5892 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5893 = or(_T_5892, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5895 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5896 = or(_T_5895, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5898 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5899 = or(_T_5898, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5901 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5902 = or(_T_5901, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5904 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5905 = or(_T_5904, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5907 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5908 = or(_T_5907, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5910 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5911 = or(_T_5910, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5913 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5914 = or(_T_5913, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5916 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5917 = or(_T_5916, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5919 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5920 = or(_T_5919, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5922 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5923 = or(_T_5922, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5925 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5926 = or(_T_5925, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5928 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5929 = or(_T_5928, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5931 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5932 = or(_T_5931, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5934 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5935 = or(_T_5934, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5937 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5938 = or(_T_5937, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5940 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5941 = or(_T_5940, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5943 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5944 = or(_T_5943, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5946 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5947 = or(_T_5946, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5949 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5950 = or(_T_5949, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5952 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5953 = or(_T_5952, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5955 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5956 = or(_T_5955, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5958 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5959 = or(_T_5958, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5961 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5962 = and(_T_1321[15], _T_1321[14]) @[RegMapper.scala 156:98] + node _T_5963 = and(_T_5962, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_5964 = or(_T_5961, _T_5963) @[RegMapper.scala 156:82] + node _T_5966 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5967 = or(_T_5966, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5969 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5970 = or(_T_5969, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5972 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5973 = or(_T_5972, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5975 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5976 = or(_T_5975, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5978 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5979 = or(_T_5978, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5981 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5982 = or(_T_5981, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5984 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5985 = or(_T_5984, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5987 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5988 = or(_T_5987, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5990 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5991 = or(_T_5990, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5993 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5994 = or(_T_5993, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5996 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_5997 = or(_T_5996, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_5999 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6000 = or(_T_5999, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6002 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6003 = or(_T_6002, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6005 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6006 = or(_T_6005, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6008 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6009 = or(_T_6008, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6011 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6012 = or(_T_6011, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6014 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6015 = or(_T_6014, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6017 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6018 = or(_T_6017, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6020 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6021 = or(_T_6020, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6023 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6024 = or(_T_6023, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6026 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6027 = or(_T_6026, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6029 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6030 = or(_T_6029, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6032 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6033 = or(_T_6032, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6035 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6036 = or(_T_6035, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6038 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6039 = or(_T_6038, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6041 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6042 = or(_T_6041, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6044 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6045 = or(_T_6044, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6047 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6048 = or(_T_6047, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6050 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6051 = or(_T_6050, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6053 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6054 = or(_T_6053, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6056 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6057 = or(_T_6056, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6059 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6060 = and(_T_1321[13], _T_1321[12]) @[RegMapper.scala 156:98] + node _T_6061 = and(_T_6060, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_6062 = or(_T_6059, _T_6061) @[RegMapper.scala 156:82] + node _T_6064 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6065 = or(_T_6064, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6067 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6068 = or(_T_6067, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6070 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6071 = or(_T_6070, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6073 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6074 = or(_T_6073, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6076 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6077 = or(_T_6076, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6079 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6080 = or(_T_6079, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6082 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6083 = or(_T_6082, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6085 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6086 = or(_T_6085, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6088 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6089 = or(_T_6088, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6091 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6092 = or(_T_6091, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6094 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6095 = or(_T_6094, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6097 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6098 = or(_T_6097, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6100 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6101 = or(_T_6100, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6103 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6104 = or(_T_6103, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6106 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6107 = or(_T_6106, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6109 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6110 = or(_T_6109, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6112 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6113 = or(_T_6112, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6115 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6116 = or(_T_6115, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6118 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6119 = or(_T_6118, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6121 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6122 = or(_T_6121, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6124 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6125 = or(_T_6124, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6127 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6128 = or(_T_6127, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6130 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6131 = or(_T_6130, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6133 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6134 = or(_T_6133, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6136 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6137 = or(_T_6136, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6139 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6140 = or(_T_6139, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6142 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6143 = or(_T_6142, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6145 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6146 = or(_T_6145, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6148 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6149 = or(_T_6148, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6151 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6152 = or(_T_6151, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6154 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6155 = or(_T_6154, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6157 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6158 = or(_T_6157, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6160 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6161 = or(_T_6160, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6163 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6164 = or(_T_6163, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6166 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6167 = or(_T_6166, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6169 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6170 = or(_T_6169, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6172 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6173 = or(_T_6172, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6175 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6176 = or(_T_6175, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6178 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6179 = or(_T_6178, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6181 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6182 = or(_T_6181, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6184 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6185 = or(_T_6184, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6187 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6188 = or(_T_6187, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6190 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6191 = or(_T_6190, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6193 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6194 = or(_T_6193, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6196 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6197 = or(_T_6196, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6199 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6200 = or(_T_6199, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6202 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6203 = or(_T_6202, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6205 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6206 = or(_T_6205, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6208 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6209 = or(_T_6208, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6211 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6212 = or(_T_6211, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6214 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6215 = or(_T_6214, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6217 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6218 = or(_T_6217, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6220 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6221 = or(_T_6220, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6223 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6224 = or(_T_6223, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6226 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6227 = or(_T_6226, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6229 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6230 = or(_T_6229, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6232 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6233 = or(_T_6232, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6235 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6236 = or(_T_6235, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6238 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6239 = or(_T_6238, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6241 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6242 = or(_T_6241, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6244 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6245 = or(_T_6244, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6247 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6248 = or(_T_6247, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6250 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6251 = or(_T_6250, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6253 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6254 = or(_T_6253, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6256 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6257 = or(_T_6256, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6259 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6260 = or(_T_6259, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6262 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6263 = or(_T_6262, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6265 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6266 = or(_T_6265, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6268 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6269 = or(_T_6268, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6271 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6272 = or(_T_6271, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6274 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6275 = or(_T_6274, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6277 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6278 = or(_T_6277, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6280 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6281 = or(_T_6280, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6283 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6284 = or(_T_6283, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6286 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6287 = or(_T_6286, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6289 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6290 = or(_T_6289, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6292 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6293 = or(_T_6292, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6295 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6296 = or(_T_6295, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6298 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6299 = or(_T_6298, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6301 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6302 = or(_T_6301, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6304 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6305 = or(_T_6304, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6307 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6308 = or(_T_6307, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6310 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6311 = or(_T_6310, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6313 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6314 = or(_T_6313, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6316 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6317 = or(_T_6316, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6319 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6320 = or(_T_6319, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6322 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6323 = or(_T_6322, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6325 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6326 = or(_T_6325, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6328 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6329 = or(_T_6328, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6331 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6332 = or(_T_6331, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6334 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6335 = or(_T_6334, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6337 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6338 = or(_T_6337, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6340 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6341 = or(_T_6340, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6343 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6344 = or(_T_6343, UInt<1>("h01")) @[RegMapper.scala 156:82] + node _T_6346 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_6347 = or(_T_6346, UInt<1>("h01")) @[RegMapper.scala 156:82] + wire _T_6350 : UInt<1>[256] @[RegMapper.scala 156:24] + _T_6350 is invalid @[RegMapper.scala 156:24] + _T_6350[0] <= _T_5568 @[RegMapper.scala 156:24] + _T_6350[1] <= _T_5572 @[RegMapper.scala 156:24] + _T_6350[2] <= _T_5575 @[RegMapper.scala 156:24] + _T_6350[3] <= _T_5578 @[RegMapper.scala 156:24] + _T_6350[4] <= _T_5581 @[RegMapper.scala 156:24] + _T_6350[5] <= _T_5584 @[RegMapper.scala 156:24] + _T_6350[6] <= _T_5587 @[RegMapper.scala 156:24] + _T_6350[7] <= _T_5590 @[RegMapper.scala 156:24] + _T_6350[8] <= _T_5593 @[RegMapper.scala 156:24] + _T_6350[9] <= _T_5596 @[RegMapper.scala 156:24] + _T_6350[10] <= _T_5599 @[RegMapper.scala 156:24] + _T_6350[11] <= _T_5602 @[RegMapper.scala 156:24] + _T_6350[12] <= _T_5605 @[RegMapper.scala 156:24] + _T_6350[13] <= _T_5608 @[RegMapper.scala 156:24] + _T_6350[14] <= _T_5611 @[RegMapper.scala 156:24] + _T_6350[15] <= _T_5614 @[RegMapper.scala 156:24] + _T_6350[16] <= _T_5617 @[RegMapper.scala 156:24] + _T_6350[17] <= _T_5620 @[RegMapper.scala 156:24] + _T_6350[18] <= _T_5623 @[RegMapper.scala 156:24] + _T_6350[19] <= _T_5626 @[RegMapper.scala 156:24] + _T_6350[20] <= _T_5629 @[RegMapper.scala 156:24] + _T_6350[21] <= _T_5632 @[RegMapper.scala 156:24] + _T_6350[22] <= _T_5635 @[RegMapper.scala 156:24] + _T_6350[23] <= _T_5638 @[RegMapper.scala 156:24] + _T_6350[24] <= _T_5641 @[RegMapper.scala 156:24] + _T_6350[25] <= _T_5644 @[RegMapper.scala 156:24] + _T_6350[26] <= _T_5647 @[RegMapper.scala 156:24] + _T_6350[27] <= _T_5650 @[RegMapper.scala 156:24] + _T_6350[28] <= _T_5653 @[RegMapper.scala 156:24] + _T_6350[29] <= _T_5656 @[RegMapper.scala 156:24] + _T_6350[30] <= _T_5659 @[RegMapper.scala 156:24] + _T_6350[31] <= _T_5662 @[RegMapper.scala 156:24] + _T_6350[32] <= _T_5668 @[RegMapper.scala 156:24] + _T_6350[33] <= _T_5671 @[RegMapper.scala 156:24] + _T_6350[34] <= _T_5674 @[RegMapper.scala 156:24] + _T_6350[35] <= _T_5677 @[RegMapper.scala 156:24] + _T_6350[36] <= _T_5680 @[RegMapper.scala 156:24] + _T_6350[37] <= _T_5683 @[RegMapper.scala 156:24] + _T_6350[38] <= _T_5686 @[RegMapper.scala 156:24] + _T_6350[39] <= _T_5689 @[RegMapper.scala 156:24] + _T_6350[40] <= _T_5692 @[RegMapper.scala 156:24] + _T_6350[41] <= _T_5695 @[RegMapper.scala 156:24] + _T_6350[42] <= _T_5698 @[RegMapper.scala 156:24] + _T_6350[43] <= _T_5701 @[RegMapper.scala 156:24] + _T_6350[44] <= _T_5704 @[RegMapper.scala 156:24] + _T_6350[45] <= _T_5707 @[RegMapper.scala 156:24] + _T_6350[46] <= _T_5710 @[RegMapper.scala 156:24] + _T_6350[47] <= _T_5713 @[RegMapper.scala 156:24] + _T_6350[48] <= _T_5716 @[RegMapper.scala 156:24] + _T_6350[49] <= _T_5719 @[RegMapper.scala 156:24] + _T_6350[50] <= _T_5722 @[RegMapper.scala 156:24] + _T_6350[51] <= _T_5725 @[RegMapper.scala 156:24] + _T_6350[52] <= _T_5728 @[RegMapper.scala 156:24] + _T_6350[53] <= _T_5731 @[RegMapper.scala 156:24] + _T_6350[54] <= _T_5734 @[RegMapper.scala 156:24] + _T_6350[55] <= _T_5737 @[RegMapper.scala 156:24] + _T_6350[56] <= _T_5740 @[RegMapper.scala 156:24] + _T_6350[57] <= _T_5743 @[RegMapper.scala 156:24] + _T_6350[58] <= _T_5746 @[RegMapper.scala 156:24] + _T_6350[59] <= _T_5749 @[RegMapper.scala 156:24] + _T_6350[60] <= _T_5752 @[RegMapper.scala 156:24] + _T_6350[61] <= _T_5755 @[RegMapper.scala 156:24] + _T_6350[62] <= _T_5758 @[RegMapper.scala 156:24] + _T_6350[63] <= _T_5761 @[RegMapper.scala 156:24] + _T_6350[64] <= _T_5767 @[RegMapper.scala 156:24] + _T_6350[65] <= _T_5770 @[RegMapper.scala 156:24] + _T_6350[66] <= _T_5773 @[RegMapper.scala 156:24] + _T_6350[67] <= _T_5776 @[RegMapper.scala 156:24] + _T_6350[68] <= _T_5779 @[RegMapper.scala 156:24] + _T_6350[69] <= _T_5782 @[RegMapper.scala 156:24] + _T_6350[70] <= _T_5785 @[RegMapper.scala 156:24] + _T_6350[71] <= _T_5788 @[RegMapper.scala 156:24] + _T_6350[72] <= _T_5791 @[RegMapper.scala 156:24] + _T_6350[73] <= _T_5794 @[RegMapper.scala 156:24] + _T_6350[74] <= _T_5797 @[RegMapper.scala 156:24] + _T_6350[75] <= _T_5800 @[RegMapper.scala 156:24] + _T_6350[76] <= _T_5803 @[RegMapper.scala 156:24] + _T_6350[77] <= _T_5806 @[RegMapper.scala 156:24] + _T_6350[78] <= _T_5809 @[RegMapper.scala 156:24] + _T_6350[79] <= _T_5812 @[RegMapper.scala 156:24] + _T_6350[80] <= _T_5818 @[RegMapper.scala 156:24] + _T_6350[81] <= _T_5821 @[RegMapper.scala 156:24] + _T_6350[82] <= _T_5824 @[RegMapper.scala 156:24] + _T_6350[83] <= _T_5827 @[RegMapper.scala 156:24] + _T_6350[84] <= _T_5830 @[RegMapper.scala 156:24] + _T_6350[85] <= _T_5833 @[RegMapper.scala 156:24] + _T_6350[86] <= _T_5836 @[RegMapper.scala 156:24] + _T_6350[87] <= _T_5839 @[RegMapper.scala 156:24] + _T_6350[88] <= _T_5842 @[RegMapper.scala 156:24] + _T_6350[89] <= _T_5845 @[RegMapper.scala 156:24] + _T_6350[90] <= _T_5848 @[RegMapper.scala 156:24] + _T_6350[91] <= _T_5851 @[RegMapper.scala 156:24] + _T_6350[92] <= _T_5854 @[RegMapper.scala 156:24] + _T_6350[93] <= _T_5857 @[RegMapper.scala 156:24] + _T_6350[94] <= _T_5860 @[RegMapper.scala 156:24] + _T_6350[95] <= _T_5863 @[RegMapper.scala 156:24] + _T_6350[96] <= _T_5866 @[RegMapper.scala 156:24] + _T_6350[97] <= _T_5869 @[RegMapper.scala 156:24] + _T_6350[98] <= _T_5872 @[RegMapper.scala 156:24] + _T_6350[99] <= _T_5875 @[RegMapper.scala 156:24] + _T_6350[100] <= _T_5878 @[RegMapper.scala 156:24] + _T_6350[101] <= _T_5881 @[RegMapper.scala 156:24] + _T_6350[102] <= _T_5884 @[RegMapper.scala 156:24] + _T_6350[103] <= _T_5887 @[RegMapper.scala 156:24] + _T_6350[104] <= _T_5890 @[RegMapper.scala 156:24] + _T_6350[105] <= _T_5893 @[RegMapper.scala 156:24] + _T_6350[106] <= _T_5896 @[RegMapper.scala 156:24] + _T_6350[107] <= _T_5899 @[RegMapper.scala 156:24] + _T_6350[108] <= _T_5902 @[RegMapper.scala 156:24] + _T_6350[109] <= _T_5905 @[RegMapper.scala 156:24] + _T_6350[110] <= _T_5908 @[RegMapper.scala 156:24] + _T_6350[111] <= _T_5911 @[RegMapper.scala 156:24] + _T_6350[112] <= _T_5914 @[RegMapper.scala 156:24] + _T_6350[113] <= _T_5917 @[RegMapper.scala 156:24] + _T_6350[114] <= _T_5920 @[RegMapper.scala 156:24] + _T_6350[115] <= _T_5923 @[RegMapper.scala 156:24] + _T_6350[116] <= _T_5926 @[RegMapper.scala 156:24] + _T_6350[117] <= _T_5929 @[RegMapper.scala 156:24] + _T_6350[118] <= _T_5932 @[RegMapper.scala 156:24] + _T_6350[119] <= _T_5935 @[RegMapper.scala 156:24] + _T_6350[120] <= _T_5938 @[RegMapper.scala 156:24] + _T_6350[121] <= _T_5941 @[RegMapper.scala 156:24] + _T_6350[122] <= _T_5944 @[RegMapper.scala 156:24] + _T_6350[123] <= _T_5947 @[RegMapper.scala 156:24] + _T_6350[124] <= _T_5950 @[RegMapper.scala 156:24] + _T_6350[125] <= _T_5953 @[RegMapper.scala 156:24] + _T_6350[126] <= _T_5956 @[RegMapper.scala 156:24] + _T_6350[127] <= _T_5959 @[RegMapper.scala 156:24] + _T_6350[128] <= _T_5964 @[RegMapper.scala 156:24] + _T_6350[129] <= _T_5967 @[RegMapper.scala 156:24] + _T_6350[130] <= _T_5970 @[RegMapper.scala 156:24] + _T_6350[131] <= _T_5973 @[RegMapper.scala 156:24] + _T_6350[132] <= _T_5976 @[RegMapper.scala 156:24] + _T_6350[133] <= _T_5979 @[RegMapper.scala 156:24] + _T_6350[134] <= _T_5982 @[RegMapper.scala 156:24] + _T_6350[135] <= _T_5985 @[RegMapper.scala 156:24] + _T_6350[136] <= _T_5988 @[RegMapper.scala 156:24] + _T_6350[137] <= _T_5991 @[RegMapper.scala 156:24] + _T_6350[138] <= _T_5994 @[RegMapper.scala 156:24] + _T_6350[139] <= _T_5997 @[RegMapper.scala 156:24] + _T_6350[140] <= _T_6000 @[RegMapper.scala 156:24] + _T_6350[141] <= _T_6003 @[RegMapper.scala 156:24] + _T_6350[142] <= _T_6006 @[RegMapper.scala 156:24] + _T_6350[143] <= _T_6009 @[RegMapper.scala 156:24] + _T_6350[144] <= _T_6012 @[RegMapper.scala 156:24] + _T_6350[145] <= _T_6015 @[RegMapper.scala 156:24] + _T_6350[146] <= _T_6018 @[RegMapper.scala 156:24] + _T_6350[147] <= _T_6021 @[RegMapper.scala 156:24] + _T_6350[148] <= _T_6024 @[RegMapper.scala 156:24] + _T_6350[149] <= _T_6027 @[RegMapper.scala 156:24] + _T_6350[150] <= _T_6030 @[RegMapper.scala 156:24] + _T_6350[151] <= _T_6033 @[RegMapper.scala 156:24] + _T_6350[152] <= _T_6036 @[RegMapper.scala 156:24] + _T_6350[153] <= _T_6039 @[RegMapper.scala 156:24] + _T_6350[154] <= _T_6042 @[RegMapper.scala 156:24] + _T_6350[155] <= _T_6045 @[RegMapper.scala 156:24] + _T_6350[156] <= _T_6048 @[RegMapper.scala 156:24] + _T_6350[157] <= _T_6051 @[RegMapper.scala 156:24] + _T_6350[158] <= _T_6054 @[RegMapper.scala 156:24] + _T_6350[159] <= _T_6057 @[RegMapper.scala 156:24] + _T_6350[160] <= _T_6062 @[RegMapper.scala 156:24] + _T_6350[161] <= _T_6065 @[RegMapper.scala 156:24] + _T_6350[162] <= _T_6068 @[RegMapper.scala 156:24] + _T_6350[163] <= _T_6071 @[RegMapper.scala 156:24] + _T_6350[164] <= _T_6074 @[RegMapper.scala 156:24] + _T_6350[165] <= _T_6077 @[RegMapper.scala 156:24] + _T_6350[166] <= _T_6080 @[RegMapper.scala 156:24] + _T_6350[167] <= _T_6083 @[RegMapper.scala 156:24] + _T_6350[168] <= _T_6086 @[RegMapper.scala 156:24] + _T_6350[169] <= _T_6089 @[RegMapper.scala 156:24] + _T_6350[170] <= _T_6092 @[RegMapper.scala 156:24] + _T_6350[171] <= _T_6095 @[RegMapper.scala 156:24] + _T_6350[172] <= _T_6098 @[RegMapper.scala 156:24] + _T_6350[173] <= _T_6101 @[RegMapper.scala 156:24] + _T_6350[174] <= _T_6104 @[RegMapper.scala 156:24] + _T_6350[175] <= _T_6107 @[RegMapper.scala 156:24] + _T_6350[176] <= _T_6110 @[RegMapper.scala 156:24] + _T_6350[177] <= _T_6113 @[RegMapper.scala 156:24] + _T_6350[178] <= _T_6116 @[RegMapper.scala 156:24] + _T_6350[179] <= _T_6119 @[RegMapper.scala 156:24] + _T_6350[180] <= _T_6122 @[RegMapper.scala 156:24] + _T_6350[181] <= _T_6125 @[RegMapper.scala 156:24] + _T_6350[182] <= _T_6128 @[RegMapper.scala 156:24] + _T_6350[183] <= _T_6131 @[RegMapper.scala 156:24] + _T_6350[184] <= _T_6134 @[RegMapper.scala 156:24] + _T_6350[185] <= _T_6137 @[RegMapper.scala 156:24] + _T_6350[186] <= _T_6140 @[RegMapper.scala 156:24] + _T_6350[187] <= _T_6143 @[RegMapper.scala 156:24] + _T_6350[188] <= _T_6146 @[RegMapper.scala 156:24] + _T_6350[189] <= _T_6149 @[RegMapper.scala 156:24] + _T_6350[190] <= _T_6152 @[RegMapper.scala 156:24] + _T_6350[191] <= _T_6155 @[RegMapper.scala 156:24] + _T_6350[192] <= _T_6158 @[RegMapper.scala 156:24] + _T_6350[193] <= _T_6161 @[RegMapper.scala 156:24] + _T_6350[194] <= _T_6164 @[RegMapper.scala 156:24] + _T_6350[195] <= _T_6167 @[RegMapper.scala 156:24] + _T_6350[196] <= _T_6170 @[RegMapper.scala 156:24] + _T_6350[197] <= _T_6173 @[RegMapper.scala 156:24] + _T_6350[198] <= _T_6176 @[RegMapper.scala 156:24] + _T_6350[199] <= _T_6179 @[RegMapper.scala 156:24] + _T_6350[200] <= _T_6182 @[RegMapper.scala 156:24] + _T_6350[201] <= _T_6185 @[RegMapper.scala 156:24] + _T_6350[202] <= _T_6188 @[RegMapper.scala 156:24] + _T_6350[203] <= _T_6191 @[RegMapper.scala 156:24] + _T_6350[204] <= _T_6194 @[RegMapper.scala 156:24] + _T_6350[205] <= _T_6197 @[RegMapper.scala 156:24] + _T_6350[206] <= _T_6200 @[RegMapper.scala 156:24] + _T_6350[207] <= _T_6203 @[RegMapper.scala 156:24] + _T_6350[208] <= _T_6206 @[RegMapper.scala 156:24] + _T_6350[209] <= _T_6209 @[RegMapper.scala 156:24] + _T_6350[210] <= _T_6212 @[RegMapper.scala 156:24] + _T_6350[211] <= _T_6215 @[RegMapper.scala 156:24] + _T_6350[212] <= _T_6218 @[RegMapper.scala 156:24] + _T_6350[213] <= _T_6221 @[RegMapper.scala 156:24] + _T_6350[214] <= _T_6224 @[RegMapper.scala 156:24] + _T_6350[215] <= _T_6227 @[RegMapper.scala 156:24] + _T_6350[216] <= _T_6230 @[RegMapper.scala 156:24] + _T_6350[217] <= _T_6233 @[RegMapper.scala 156:24] + _T_6350[218] <= _T_6236 @[RegMapper.scala 156:24] + _T_6350[219] <= _T_6239 @[RegMapper.scala 156:24] + _T_6350[220] <= _T_6242 @[RegMapper.scala 156:24] + _T_6350[221] <= _T_6245 @[RegMapper.scala 156:24] + _T_6350[222] <= _T_6248 @[RegMapper.scala 156:24] + _T_6350[223] <= _T_6251 @[RegMapper.scala 156:24] + _T_6350[224] <= _T_6254 @[RegMapper.scala 156:24] + _T_6350[225] <= _T_6257 @[RegMapper.scala 156:24] + _T_6350[226] <= _T_6260 @[RegMapper.scala 156:24] + _T_6350[227] <= _T_6263 @[RegMapper.scala 156:24] + _T_6350[228] <= _T_6266 @[RegMapper.scala 156:24] + _T_6350[229] <= _T_6269 @[RegMapper.scala 156:24] + _T_6350[230] <= _T_6272 @[RegMapper.scala 156:24] + _T_6350[231] <= _T_6275 @[RegMapper.scala 156:24] + _T_6350[232] <= _T_6278 @[RegMapper.scala 156:24] + _T_6350[233] <= _T_6281 @[RegMapper.scala 156:24] + _T_6350[234] <= _T_6284 @[RegMapper.scala 156:24] + _T_6350[235] <= _T_6287 @[RegMapper.scala 156:24] + _T_6350[236] <= _T_6290 @[RegMapper.scala 156:24] + _T_6350[237] <= _T_6293 @[RegMapper.scala 156:24] + _T_6350[238] <= _T_6296 @[RegMapper.scala 156:24] + _T_6350[239] <= _T_6299 @[RegMapper.scala 156:24] + _T_6350[240] <= _T_6302 @[RegMapper.scala 156:24] + _T_6350[241] <= _T_6305 @[RegMapper.scala 156:24] + _T_6350[242] <= _T_6308 @[RegMapper.scala 156:24] + _T_6350[243] <= _T_6311 @[RegMapper.scala 156:24] + _T_6350[244] <= _T_6314 @[RegMapper.scala 156:24] + _T_6350[245] <= _T_6317 @[RegMapper.scala 156:24] + _T_6350[246] <= _T_6320 @[RegMapper.scala 156:24] + _T_6350[247] <= _T_6323 @[RegMapper.scala 156:24] + _T_6350[248] <= _T_6326 @[RegMapper.scala 156:24] + _T_6350[249] <= _T_6329 @[RegMapper.scala 156:24] + _T_6350[250] <= _T_6332 @[RegMapper.scala 156:24] + _T_6350[251] <= _T_6335 @[RegMapper.scala 156:24] + _T_6350[252] <= _T_6338 @[RegMapper.scala 156:24] + _T_6350[253] <= _T_6341 @[RegMapper.scala 156:24] + _T_6350[254] <= _T_6344 @[RegMapper.scala 156:24] + _T_6350[255] <= _T_6347 @[RegMapper.scala 156:24] + node _T_6610 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6611 = and(_T_1343[4], _T_1343[3]) @[RegMapper.scala 157:98] + node _T_6612 = and(_T_6611, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_6613 = or(_T_6610, _T_6612) @[RegMapper.scala 157:82] + node _T_6615 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6616 = and(_T_1343[8], UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_6617 = or(_T_6615, _T_6616) @[RegMapper.scala 157:82] + node _T_6619 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6620 = or(_T_6619, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6622 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6623 = or(_T_6622, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6625 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6626 = or(_T_6625, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6628 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6629 = or(_T_6628, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6631 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6632 = or(_T_6631, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6634 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6635 = or(_T_6634, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6637 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6638 = or(_T_6637, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6640 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6641 = or(_T_6640, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6643 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6644 = or(_T_6643, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6646 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6647 = or(_T_6646, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6649 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6650 = or(_T_6649, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6652 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6653 = or(_T_6652, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6656 = or(_T_6655, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6658 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6659 = or(_T_6658, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6661 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6662 = or(_T_6661, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6664 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6665 = or(_T_6664, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6667 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6668 = or(_T_6667, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6670 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6671 = or(_T_6670, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6673 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6674 = or(_T_6673, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6676 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6677 = or(_T_6676, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6679 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6680 = or(_T_6679, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6682 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6683 = or(_T_6682, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6685 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6686 = or(_T_6685, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6688 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6689 = or(_T_6688, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6691 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6692 = or(_T_6691, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6694 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6695 = or(_T_6694, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6697 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6698 = or(_T_6697, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6700 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6701 = or(_T_6700, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6703 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6704 = or(_T_6703, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6706 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6707 = or(_T_6706, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6709 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6710 = and(_T_1343[11], _T_1343[10]) @[RegMapper.scala 157:98] + node _T_6711 = and(_T_6710, _T_1343[9]) @[RegMapper.scala 157:98] + node _T_6712 = and(_T_6711, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_6713 = or(_T_6709, _T_6712) @[RegMapper.scala 157:82] + node _T_6715 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6716 = or(_T_6715, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6718 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6719 = or(_T_6718, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6721 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6722 = or(_T_6721, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6724 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6725 = or(_T_6724, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6727 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6728 = or(_T_6727, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6730 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6731 = or(_T_6730, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6733 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6734 = or(_T_6733, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6736 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6737 = or(_T_6736, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6739 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6740 = or(_T_6739, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6742 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6743 = or(_T_6742, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6745 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6746 = or(_T_6745, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6748 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6749 = or(_T_6748, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6751 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6752 = or(_T_6751, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6755 = or(_T_6754, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6757 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6758 = or(_T_6757, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6760 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6761 = or(_T_6760, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6763 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6764 = or(_T_6763, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6766 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6767 = or(_T_6766, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6769 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6770 = or(_T_6769, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6772 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6773 = or(_T_6772, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6775 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6776 = or(_T_6775, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6778 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6779 = or(_T_6778, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6781 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6782 = or(_T_6781, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6784 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6785 = or(_T_6784, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6787 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6788 = or(_T_6787, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6790 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6791 = or(_T_6790, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6793 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6794 = or(_T_6793, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6796 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6797 = or(_T_6796, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6799 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6800 = or(_T_6799, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6802 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6803 = or(_T_6802, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6805 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6806 = or(_T_6805, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6808 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6809 = and(_T_1343[2], _T_1343[1]) @[RegMapper.scala 157:98] + node _T_6810 = and(_T_6809, _T_1343[0]) @[RegMapper.scala 157:98] + node _T_6811 = and(_T_6810, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_6812 = or(_T_6808, _T_6811) @[RegMapper.scala 157:82] + node _T_6814 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6815 = or(_T_6814, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6817 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6818 = or(_T_6817, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6820 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6821 = or(_T_6820, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6823 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6824 = or(_T_6823, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6826 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6827 = or(_T_6826, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6829 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6830 = or(_T_6829, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6832 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6833 = or(_T_6832, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6835 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6836 = or(_T_6835, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6838 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6839 = or(_T_6838, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6841 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6842 = or(_T_6841, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6844 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6845 = or(_T_6844, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6847 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6848 = or(_T_6847, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6850 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6851 = or(_T_6850, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6853 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6854 = or(_T_6853, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6856 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6857 = or(_T_6856, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6859 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6860 = and(_T_1343[7], _T_1343[6]) @[RegMapper.scala 157:98] + node _T_6861 = and(_T_6860, _T_1343[5]) @[RegMapper.scala 157:98] + node _T_6862 = and(_T_6861, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_6863 = or(_T_6859, _T_6862) @[RegMapper.scala 157:82] + node _T_6865 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6866 = or(_T_6865, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6868 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6869 = or(_T_6868, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6871 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6872 = or(_T_6871, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6874 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6875 = or(_T_6874, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6877 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6878 = or(_T_6877, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6880 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6881 = or(_T_6880, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6883 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6884 = or(_T_6883, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6886 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6887 = or(_T_6886, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6889 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6890 = or(_T_6889, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6892 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6893 = or(_T_6892, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6895 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6896 = or(_T_6895, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6898 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6899 = or(_T_6898, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6901 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6902 = or(_T_6901, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6904 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6905 = or(_T_6904, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6907 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6908 = or(_T_6907, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6910 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6911 = or(_T_6910, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6913 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6914 = or(_T_6913, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6916 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6917 = or(_T_6916, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6919 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6920 = or(_T_6919, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6922 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6923 = or(_T_6922, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6925 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6926 = or(_T_6925, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6928 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6929 = or(_T_6928, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6931 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6932 = or(_T_6931, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6934 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6935 = or(_T_6934, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6937 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6938 = or(_T_6937, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6940 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6941 = or(_T_6940, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6943 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6944 = or(_T_6943, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6946 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6947 = or(_T_6946, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6949 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6950 = or(_T_6949, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6952 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6953 = or(_T_6952, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6955 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6956 = or(_T_6955, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6958 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6959 = or(_T_6958, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6961 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6962 = or(_T_6961, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6964 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6965 = or(_T_6964, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6967 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6968 = or(_T_6967, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6970 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6971 = or(_T_6970, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6973 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6974 = or(_T_6973, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6976 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6977 = or(_T_6976, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6979 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6980 = or(_T_6979, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6982 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6983 = or(_T_6982, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6985 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6986 = or(_T_6985, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6988 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6989 = or(_T_6988, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6991 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6992 = or(_T_6991, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6994 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6995 = or(_T_6994, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_6997 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_6998 = or(_T_6997, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7000 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7001 = or(_T_7000, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7003 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7004 = or(_T_7003, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7006 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7007 = and(_T_1343[15], _T_1343[14]) @[RegMapper.scala 157:98] + node _T_7008 = and(_T_7007, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_7009 = or(_T_7006, _T_7008) @[RegMapper.scala 157:82] + node _T_7011 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7012 = or(_T_7011, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7014 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7015 = or(_T_7014, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7017 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7018 = or(_T_7017, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7020 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7021 = or(_T_7020, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7023 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7024 = or(_T_7023, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7026 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7027 = or(_T_7026, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7029 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7030 = or(_T_7029, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7032 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7033 = or(_T_7032, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7035 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7036 = or(_T_7035, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7038 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7039 = or(_T_7038, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7041 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7042 = or(_T_7041, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7044 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7045 = or(_T_7044, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7047 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7048 = or(_T_7047, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7050 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7051 = or(_T_7050, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7053 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7054 = or(_T_7053, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7056 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7057 = or(_T_7056, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7059 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7060 = or(_T_7059, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7062 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7063 = or(_T_7062, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7065 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7066 = or(_T_7065, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7068 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7069 = or(_T_7068, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7071 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7072 = or(_T_7071, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7074 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7075 = or(_T_7074, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7077 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7078 = or(_T_7077, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7080 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7081 = or(_T_7080, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7083 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7084 = or(_T_7083, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7086 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7087 = or(_T_7086, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7089 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7090 = or(_T_7089, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7092 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7093 = or(_T_7092, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7095 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7096 = or(_T_7095, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7098 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7099 = or(_T_7098, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7101 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7102 = or(_T_7101, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7104 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7105 = and(_T_1343[13], _T_1343[12]) @[RegMapper.scala 157:98] + node _T_7106 = and(_T_7105, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_7107 = or(_T_7104, _T_7106) @[RegMapper.scala 157:82] + node _T_7109 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7110 = or(_T_7109, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7112 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7113 = or(_T_7112, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7115 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7116 = or(_T_7115, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7118 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7119 = or(_T_7118, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7121 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7122 = or(_T_7121, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7124 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7125 = or(_T_7124, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7127 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7128 = or(_T_7127, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7130 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7131 = or(_T_7130, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7133 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7134 = or(_T_7133, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7136 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7137 = or(_T_7136, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7139 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7140 = or(_T_7139, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7142 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7143 = or(_T_7142, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7145 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7146 = or(_T_7145, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7148 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7149 = or(_T_7148, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7151 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7152 = or(_T_7151, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7154 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7155 = or(_T_7154, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7157 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7158 = or(_T_7157, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7160 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7161 = or(_T_7160, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7163 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7164 = or(_T_7163, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7166 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7167 = or(_T_7166, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7169 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7170 = or(_T_7169, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7172 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7173 = or(_T_7172, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7175 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7176 = or(_T_7175, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7178 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7179 = or(_T_7178, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7181 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7182 = or(_T_7181, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7184 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7185 = or(_T_7184, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7187 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7188 = or(_T_7187, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7190 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7191 = or(_T_7190, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7193 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7194 = or(_T_7193, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7196 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7197 = or(_T_7196, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7199 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7200 = or(_T_7199, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7202 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7203 = or(_T_7202, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7205 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7206 = or(_T_7205, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7208 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7209 = or(_T_7208, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7211 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7212 = or(_T_7211, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7214 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7215 = or(_T_7214, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7217 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7218 = or(_T_7217, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7220 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7221 = or(_T_7220, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7223 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7224 = or(_T_7223, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7226 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7227 = or(_T_7226, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7229 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7230 = or(_T_7229, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7232 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7233 = or(_T_7232, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7235 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7236 = or(_T_7235, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7238 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7239 = or(_T_7238, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7241 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7242 = or(_T_7241, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7244 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7245 = or(_T_7244, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7247 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7248 = or(_T_7247, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7250 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7251 = or(_T_7250, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7253 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7254 = or(_T_7253, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7256 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7257 = or(_T_7256, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7259 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7260 = or(_T_7259, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7262 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7263 = or(_T_7262, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7265 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7266 = or(_T_7265, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7268 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7269 = or(_T_7268, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7271 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7272 = or(_T_7271, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7274 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7275 = or(_T_7274, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7277 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7278 = or(_T_7277, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7280 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7281 = or(_T_7280, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7283 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7284 = or(_T_7283, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7286 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7287 = or(_T_7286, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7289 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7290 = or(_T_7289, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7292 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7293 = or(_T_7292, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7295 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7296 = or(_T_7295, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7298 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7299 = or(_T_7298, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7301 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7302 = or(_T_7301, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7304 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7305 = or(_T_7304, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7307 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7308 = or(_T_7307, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7310 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7311 = or(_T_7310, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7313 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7314 = or(_T_7313, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7316 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7317 = or(_T_7316, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7319 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7320 = or(_T_7319, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7322 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7323 = or(_T_7322, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7325 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7326 = or(_T_7325, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7328 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7329 = or(_T_7328, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7331 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7332 = or(_T_7331, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7334 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7335 = or(_T_7334, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7337 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7338 = or(_T_7337, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7340 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7341 = or(_T_7340, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7343 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7344 = or(_T_7343, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7346 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7347 = or(_T_7346, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7349 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7350 = or(_T_7349, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7352 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7353 = or(_T_7352, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7355 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7356 = or(_T_7355, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7358 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7359 = or(_T_7358, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7361 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7362 = or(_T_7361, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7364 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7365 = or(_T_7364, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7367 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7368 = or(_T_7367, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7370 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7371 = or(_T_7370, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7373 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7374 = or(_T_7373, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7376 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7377 = or(_T_7376, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7379 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7380 = or(_T_7379, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7382 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7383 = or(_T_7382, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7385 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7386 = or(_T_7385, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7388 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7389 = or(_T_7388, UInt<1>("h01")) @[RegMapper.scala 157:82] + node _T_7391 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_7392 = or(_T_7391, UInt<1>("h01")) @[RegMapper.scala 157:82] + wire _T_7395 : UInt<1>[256] @[RegMapper.scala 157:24] + _T_7395 is invalid @[RegMapper.scala 157:24] + _T_7395[0] <= _T_6613 @[RegMapper.scala 157:24] + _T_7395[1] <= _T_6617 @[RegMapper.scala 157:24] + _T_7395[2] <= _T_6620 @[RegMapper.scala 157:24] + _T_7395[3] <= _T_6623 @[RegMapper.scala 157:24] + _T_7395[4] <= _T_6626 @[RegMapper.scala 157:24] + _T_7395[5] <= _T_6629 @[RegMapper.scala 157:24] + _T_7395[6] <= _T_6632 @[RegMapper.scala 157:24] + _T_7395[7] <= _T_6635 @[RegMapper.scala 157:24] + _T_7395[8] <= _T_6638 @[RegMapper.scala 157:24] + _T_7395[9] <= _T_6641 @[RegMapper.scala 157:24] + _T_7395[10] <= _T_6644 @[RegMapper.scala 157:24] + _T_7395[11] <= _T_6647 @[RegMapper.scala 157:24] + _T_7395[12] <= _T_6650 @[RegMapper.scala 157:24] + _T_7395[13] <= _T_6653 @[RegMapper.scala 157:24] + _T_7395[14] <= _T_6656 @[RegMapper.scala 157:24] + _T_7395[15] <= _T_6659 @[RegMapper.scala 157:24] + _T_7395[16] <= _T_6662 @[RegMapper.scala 157:24] + _T_7395[17] <= _T_6665 @[RegMapper.scala 157:24] + _T_7395[18] <= _T_6668 @[RegMapper.scala 157:24] + _T_7395[19] <= _T_6671 @[RegMapper.scala 157:24] + _T_7395[20] <= _T_6674 @[RegMapper.scala 157:24] + _T_7395[21] <= _T_6677 @[RegMapper.scala 157:24] + _T_7395[22] <= _T_6680 @[RegMapper.scala 157:24] + _T_7395[23] <= _T_6683 @[RegMapper.scala 157:24] + _T_7395[24] <= _T_6686 @[RegMapper.scala 157:24] + _T_7395[25] <= _T_6689 @[RegMapper.scala 157:24] + _T_7395[26] <= _T_6692 @[RegMapper.scala 157:24] + _T_7395[27] <= _T_6695 @[RegMapper.scala 157:24] + _T_7395[28] <= _T_6698 @[RegMapper.scala 157:24] + _T_7395[29] <= _T_6701 @[RegMapper.scala 157:24] + _T_7395[30] <= _T_6704 @[RegMapper.scala 157:24] + _T_7395[31] <= _T_6707 @[RegMapper.scala 157:24] + _T_7395[32] <= _T_6713 @[RegMapper.scala 157:24] + _T_7395[33] <= _T_6716 @[RegMapper.scala 157:24] + _T_7395[34] <= _T_6719 @[RegMapper.scala 157:24] + _T_7395[35] <= _T_6722 @[RegMapper.scala 157:24] + _T_7395[36] <= _T_6725 @[RegMapper.scala 157:24] + _T_7395[37] <= _T_6728 @[RegMapper.scala 157:24] + _T_7395[38] <= _T_6731 @[RegMapper.scala 157:24] + _T_7395[39] <= _T_6734 @[RegMapper.scala 157:24] + _T_7395[40] <= _T_6737 @[RegMapper.scala 157:24] + _T_7395[41] <= _T_6740 @[RegMapper.scala 157:24] + _T_7395[42] <= _T_6743 @[RegMapper.scala 157:24] + _T_7395[43] <= _T_6746 @[RegMapper.scala 157:24] + _T_7395[44] <= _T_6749 @[RegMapper.scala 157:24] + _T_7395[45] <= _T_6752 @[RegMapper.scala 157:24] + _T_7395[46] <= _T_6755 @[RegMapper.scala 157:24] + _T_7395[47] <= _T_6758 @[RegMapper.scala 157:24] + _T_7395[48] <= _T_6761 @[RegMapper.scala 157:24] + _T_7395[49] <= _T_6764 @[RegMapper.scala 157:24] + _T_7395[50] <= _T_6767 @[RegMapper.scala 157:24] + _T_7395[51] <= _T_6770 @[RegMapper.scala 157:24] + _T_7395[52] <= _T_6773 @[RegMapper.scala 157:24] + _T_7395[53] <= _T_6776 @[RegMapper.scala 157:24] + _T_7395[54] <= _T_6779 @[RegMapper.scala 157:24] + _T_7395[55] <= _T_6782 @[RegMapper.scala 157:24] + _T_7395[56] <= _T_6785 @[RegMapper.scala 157:24] + _T_7395[57] <= _T_6788 @[RegMapper.scala 157:24] + _T_7395[58] <= _T_6791 @[RegMapper.scala 157:24] + _T_7395[59] <= _T_6794 @[RegMapper.scala 157:24] + _T_7395[60] <= _T_6797 @[RegMapper.scala 157:24] + _T_7395[61] <= _T_6800 @[RegMapper.scala 157:24] + _T_7395[62] <= _T_6803 @[RegMapper.scala 157:24] + _T_7395[63] <= _T_6806 @[RegMapper.scala 157:24] + _T_7395[64] <= _T_6812 @[RegMapper.scala 157:24] + _T_7395[65] <= _T_6815 @[RegMapper.scala 157:24] + _T_7395[66] <= _T_6818 @[RegMapper.scala 157:24] + _T_7395[67] <= _T_6821 @[RegMapper.scala 157:24] + _T_7395[68] <= _T_6824 @[RegMapper.scala 157:24] + _T_7395[69] <= _T_6827 @[RegMapper.scala 157:24] + _T_7395[70] <= _T_6830 @[RegMapper.scala 157:24] + _T_7395[71] <= _T_6833 @[RegMapper.scala 157:24] + _T_7395[72] <= _T_6836 @[RegMapper.scala 157:24] + _T_7395[73] <= _T_6839 @[RegMapper.scala 157:24] + _T_7395[74] <= _T_6842 @[RegMapper.scala 157:24] + _T_7395[75] <= _T_6845 @[RegMapper.scala 157:24] + _T_7395[76] <= _T_6848 @[RegMapper.scala 157:24] + _T_7395[77] <= _T_6851 @[RegMapper.scala 157:24] + _T_7395[78] <= _T_6854 @[RegMapper.scala 157:24] + _T_7395[79] <= _T_6857 @[RegMapper.scala 157:24] + _T_7395[80] <= _T_6863 @[RegMapper.scala 157:24] + _T_7395[81] <= _T_6866 @[RegMapper.scala 157:24] + _T_7395[82] <= _T_6869 @[RegMapper.scala 157:24] + _T_7395[83] <= _T_6872 @[RegMapper.scala 157:24] + _T_7395[84] <= _T_6875 @[RegMapper.scala 157:24] + _T_7395[85] <= _T_6878 @[RegMapper.scala 157:24] + _T_7395[86] <= _T_6881 @[RegMapper.scala 157:24] + _T_7395[87] <= _T_6884 @[RegMapper.scala 157:24] + _T_7395[88] <= _T_6887 @[RegMapper.scala 157:24] + _T_7395[89] <= _T_6890 @[RegMapper.scala 157:24] + _T_7395[90] <= _T_6893 @[RegMapper.scala 157:24] + _T_7395[91] <= _T_6896 @[RegMapper.scala 157:24] + _T_7395[92] <= _T_6899 @[RegMapper.scala 157:24] + _T_7395[93] <= _T_6902 @[RegMapper.scala 157:24] + _T_7395[94] <= _T_6905 @[RegMapper.scala 157:24] + _T_7395[95] <= _T_6908 @[RegMapper.scala 157:24] + _T_7395[96] <= _T_6911 @[RegMapper.scala 157:24] + _T_7395[97] <= _T_6914 @[RegMapper.scala 157:24] + _T_7395[98] <= _T_6917 @[RegMapper.scala 157:24] + _T_7395[99] <= _T_6920 @[RegMapper.scala 157:24] + _T_7395[100] <= _T_6923 @[RegMapper.scala 157:24] + _T_7395[101] <= _T_6926 @[RegMapper.scala 157:24] + _T_7395[102] <= _T_6929 @[RegMapper.scala 157:24] + _T_7395[103] <= _T_6932 @[RegMapper.scala 157:24] + _T_7395[104] <= _T_6935 @[RegMapper.scala 157:24] + _T_7395[105] <= _T_6938 @[RegMapper.scala 157:24] + _T_7395[106] <= _T_6941 @[RegMapper.scala 157:24] + _T_7395[107] <= _T_6944 @[RegMapper.scala 157:24] + _T_7395[108] <= _T_6947 @[RegMapper.scala 157:24] + _T_7395[109] <= _T_6950 @[RegMapper.scala 157:24] + _T_7395[110] <= _T_6953 @[RegMapper.scala 157:24] + _T_7395[111] <= _T_6956 @[RegMapper.scala 157:24] + _T_7395[112] <= _T_6959 @[RegMapper.scala 157:24] + _T_7395[113] <= _T_6962 @[RegMapper.scala 157:24] + _T_7395[114] <= _T_6965 @[RegMapper.scala 157:24] + _T_7395[115] <= _T_6968 @[RegMapper.scala 157:24] + _T_7395[116] <= _T_6971 @[RegMapper.scala 157:24] + _T_7395[117] <= _T_6974 @[RegMapper.scala 157:24] + _T_7395[118] <= _T_6977 @[RegMapper.scala 157:24] + _T_7395[119] <= _T_6980 @[RegMapper.scala 157:24] + _T_7395[120] <= _T_6983 @[RegMapper.scala 157:24] + _T_7395[121] <= _T_6986 @[RegMapper.scala 157:24] + _T_7395[122] <= _T_6989 @[RegMapper.scala 157:24] + _T_7395[123] <= _T_6992 @[RegMapper.scala 157:24] + _T_7395[124] <= _T_6995 @[RegMapper.scala 157:24] + _T_7395[125] <= _T_6998 @[RegMapper.scala 157:24] + _T_7395[126] <= _T_7001 @[RegMapper.scala 157:24] + _T_7395[127] <= _T_7004 @[RegMapper.scala 157:24] + _T_7395[128] <= _T_7009 @[RegMapper.scala 157:24] + _T_7395[129] <= _T_7012 @[RegMapper.scala 157:24] + _T_7395[130] <= _T_7015 @[RegMapper.scala 157:24] + _T_7395[131] <= _T_7018 @[RegMapper.scala 157:24] + _T_7395[132] <= _T_7021 @[RegMapper.scala 157:24] + _T_7395[133] <= _T_7024 @[RegMapper.scala 157:24] + _T_7395[134] <= _T_7027 @[RegMapper.scala 157:24] + _T_7395[135] <= _T_7030 @[RegMapper.scala 157:24] + _T_7395[136] <= _T_7033 @[RegMapper.scala 157:24] + _T_7395[137] <= _T_7036 @[RegMapper.scala 157:24] + _T_7395[138] <= _T_7039 @[RegMapper.scala 157:24] + _T_7395[139] <= _T_7042 @[RegMapper.scala 157:24] + _T_7395[140] <= _T_7045 @[RegMapper.scala 157:24] + _T_7395[141] <= _T_7048 @[RegMapper.scala 157:24] + _T_7395[142] <= _T_7051 @[RegMapper.scala 157:24] + _T_7395[143] <= _T_7054 @[RegMapper.scala 157:24] + _T_7395[144] <= _T_7057 @[RegMapper.scala 157:24] + _T_7395[145] <= _T_7060 @[RegMapper.scala 157:24] + _T_7395[146] <= _T_7063 @[RegMapper.scala 157:24] + _T_7395[147] <= _T_7066 @[RegMapper.scala 157:24] + _T_7395[148] <= _T_7069 @[RegMapper.scala 157:24] + _T_7395[149] <= _T_7072 @[RegMapper.scala 157:24] + _T_7395[150] <= _T_7075 @[RegMapper.scala 157:24] + _T_7395[151] <= _T_7078 @[RegMapper.scala 157:24] + _T_7395[152] <= _T_7081 @[RegMapper.scala 157:24] + _T_7395[153] <= _T_7084 @[RegMapper.scala 157:24] + _T_7395[154] <= _T_7087 @[RegMapper.scala 157:24] + _T_7395[155] <= _T_7090 @[RegMapper.scala 157:24] + _T_7395[156] <= _T_7093 @[RegMapper.scala 157:24] + _T_7395[157] <= _T_7096 @[RegMapper.scala 157:24] + _T_7395[158] <= _T_7099 @[RegMapper.scala 157:24] + _T_7395[159] <= _T_7102 @[RegMapper.scala 157:24] + _T_7395[160] <= _T_7107 @[RegMapper.scala 157:24] + _T_7395[161] <= _T_7110 @[RegMapper.scala 157:24] + _T_7395[162] <= _T_7113 @[RegMapper.scala 157:24] + _T_7395[163] <= _T_7116 @[RegMapper.scala 157:24] + _T_7395[164] <= _T_7119 @[RegMapper.scala 157:24] + _T_7395[165] <= _T_7122 @[RegMapper.scala 157:24] + _T_7395[166] <= _T_7125 @[RegMapper.scala 157:24] + _T_7395[167] <= _T_7128 @[RegMapper.scala 157:24] + _T_7395[168] <= _T_7131 @[RegMapper.scala 157:24] + _T_7395[169] <= _T_7134 @[RegMapper.scala 157:24] + _T_7395[170] <= _T_7137 @[RegMapper.scala 157:24] + _T_7395[171] <= _T_7140 @[RegMapper.scala 157:24] + _T_7395[172] <= _T_7143 @[RegMapper.scala 157:24] + _T_7395[173] <= _T_7146 @[RegMapper.scala 157:24] + _T_7395[174] <= _T_7149 @[RegMapper.scala 157:24] + _T_7395[175] <= _T_7152 @[RegMapper.scala 157:24] + _T_7395[176] <= _T_7155 @[RegMapper.scala 157:24] + _T_7395[177] <= _T_7158 @[RegMapper.scala 157:24] + _T_7395[178] <= _T_7161 @[RegMapper.scala 157:24] + _T_7395[179] <= _T_7164 @[RegMapper.scala 157:24] + _T_7395[180] <= _T_7167 @[RegMapper.scala 157:24] + _T_7395[181] <= _T_7170 @[RegMapper.scala 157:24] + _T_7395[182] <= _T_7173 @[RegMapper.scala 157:24] + _T_7395[183] <= _T_7176 @[RegMapper.scala 157:24] + _T_7395[184] <= _T_7179 @[RegMapper.scala 157:24] + _T_7395[185] <= _T_7182 @[RegMapper.scala 157:24] + _T_7395[186] <= _T_7185 @[RegMapper.scala 157:24] + _T_7395[187] <= _T_7188 @[RegMapper.scala 157:24] + _T_7395[188] <= _T_7191 @[RegMapper.scala 157:24] + _T_7395[189] <= _T_7194 @[RegMapper.scala 157:24] + _T_7395[190] <= _T_7197 @[RegMapper.scala 157:24] + _T_7395[191] <= _T_7200 @[RegMapper.scala 157:24] + _T_7395[192] <= _T_7203 @[RegMapper.scala 157:24] + _T_7395[193] <= _T_7206 @[RegMapper.scala 157:24] + _T_7395[194] <= _T_7209 @[RegMapper.scala 157:24] + _T_7395[195] <= _T_7212 @[RegMapper.scala 157:24] + _T_7395[196] <= _T_7215 @[RegMapper.scala 157:24] + _T_7395[197] <= _T_7218 @[RegMapper.scala 157:24] + _T_7395[198] <= _T_7221 @[RegMapper.scala 157:24] + _T_7395[199] <= _T_7224 @[RegMapper.scala 157:24] + _T_7395[200] <= _T_7227 @[RegMapper.scala 157:24] + _T_7395[201] <= _T_7230 @[RegMapper.scala 157:24] + _T_7395[202] <= _T_7233 @[RegMapper.scala 157:24] + _T_7395[203] <= _T_7236 @[RegMapper.scala 157:24] + _T_7395[204] <= _T_7239 @[RegMapper.scala 157:24] + _T_7395[205] <= _T_7242 @[RegMapper.scala 157:24] + _T_7395[206] <= _T_7245 @[RegMapper.scala 157:24] + _T_7395[207] <= _T_7248 @[RegMapper.scala 157:24] + _T_7395[208] <= _T_7251 @[RegMapper.scala 157:24] + _T_7395[209] <= _T_7254 @[RegMapper.scala 157:24] + _T_7395[210] <= _T_7257 @[RegMapper.scala 157:24] + _T_7395[211] <= _T_7260 @[RegMapper.scala 157:24] + _T_7395[212] <= _T_7263 @[RegMapper.scala 157:24] + _T_7395[213] <= _T_7266 @[RegMapper.scala 157:24] + _T_7395[214] <= _T_7269 @[RegMapper.scala 157:24] + _T_7395[215] <= _T_7272 @[RegMapper.scala 157:24] + _T_7395[216] <= _T_7275 @[RegMapper.scala 157:24] + _T_7395[217] <= _T_7278 @[RegMapper.scala 157:24] + _T_7395[218] <= _T_7281 @[RegMapper.scala 157:24] + _T_7395[219] <= _T_7284 @[RegMapper.scala 157:24] + _T_7395[220] <= _T_7287 @[RegMapper.scala 157:24] + _T_7395[221] <= _T_7290 @[RegMapper.scala 157:24] + _T_7395[222] <= _T_7293 @[RegMapper.scala 157:24] + _T_7395[223] <= _T_7296 @[RegMapper.scala 157:24] + _T_7395[224] <= _T_7299 @[RegMapper.scala 157:24] + _T_7395[225] <= _T_7302 @[RegMapper.scala 157:24] + _T_7395[226] <= _T_7305 @[RegMapper.scala 157:24] + _T_7395[227] <= _T_7308 @[RegMapper.scala 157:24] + _T_7395[228] <= _T_7311 @[RegMapper.scala 157:24] + _T_7395[229] <= _T_7314 @[RegMapper.scala 157:24] + _T_7395[230] <= _T_7317 @[RegMapper.scala 157:24] + _T_7395[231] <= _T_7320 @[RegMapper.scala 157:24] + _T_7395[232] <= _T_7323 @[RegMapper.scala 157:24] + _T_7395[233] <= _T_7326 @[RegMapper.scala 157:24] + _T_7395[234] <= _T_7329 @[RegMapper.scala 157:24] + _T_7395[235] <= _T_7332 @[RegMapper.scala 157:24] + _T_7395[236] <= _T_7335 @[RegMapper.scala 157:24] + _T_7395[237] <= _T_7338 @[RegMapper.scala 157:24] + _T_7395[238] <= _T_7341 @[RegMapper.scala 157:24] + _T_7395[239] <= _T_7344 @[RegMapper.scala 157:24] + _T_7395[240] <= _T_7347 @[RegMapper.scala 157:24] + _T_7395[241] <= _T_7350 @[RegMapper.scala 157:24] + _T_7395[242] <= _T_7353 @[RegMapper.scala 157:24] + _T_7395[243] <= _T_7356 @[RegMapper.scala 157:24] + _T_7395[244] <= _T_7359 @[RegMapper.scala 157:24] + _T_7395[245] <= _T_7362 @[RegMapper.scala 157:24] + _T_7395[246] <= _T_7365 @[RegMapper.scala 157:24] + _T_7395[247] <= _T_7368 @[RegMapper.scala 157:24] + _T_7395[248] <= _T_7371 @[RegMapper.scala 157:24] + _T_7395[249] <= _T_7374 @[RegMapper.scala 157:24] + _T_7395[250] <= _T_7377 @[RegMapper.scala 157:24] + _T_7395[251] <= _T_7380 @[RegMapper.scala 157:24] + _T_7395[252] <= _T_7383 @[RegMapper.scala 157:24] + _T_7395[253] <= _T_7386 @[RegMapper.scala 157:24] + _T_7395[254] <= _T_7389 @[RegMapper.scala 157:24] + _T_7395[255] <= _T_7392 @[RegMapper.scala 157:24] + node _T_7654 = bits(_T_692.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_7655 = bits(_T_692.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_7656 = bits(_T_692.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_7657 = bits(_T_692.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_7658 = bits(_T_692.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_7659 = bits(_T_692.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_7660 = bits(_T_692.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_7661 = bits(_T_692.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_7662 = bits(_T_692.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_7663 = bits(_T_692.bits.index, 9, 9) @[RegMapper.scala 82:29] + node _T_7664 = bits(_T_692.bits.index, 10, 10) @[RegMapper.scala 82:29] + node _T_7665 = bits(_T_692.bits.index, 11, 11) @[RegMapper.scala 82:29] + node _T_7666 = bits(_T_692.bits.index, 12, 12) @[RegMapper.scala 82:29] + node _T_7667 = bits(_T_692.bits.index, 13, 13) @[RegMapper.scala 82:29] + node _T_7668 = bits(_T_692.bits.index, 14, 14) @[RegMapper.scala 82:29] + node _T_7669 = bits(_T_692.bits.index, 15, 15) @[RegMapper.scala 82:29] + node _T_7670 = bits(_T_692.bits.index, 16, 16) @[RegMapper.scala 82:29] + node _T_7671 = bits(_T_692.bits.index, 17, 17) @[RegMapper.scala 82:29] + node _T_7672 = bits(_T_692.bits.index, 18, 18) @[RegMapper.scala 82:29] + node _T_7673 = bits(_T_692.bits.index, 19, 19) @[RegMapper.scala 82:29] + node _T_7674 = bits(_T_692.bits.index, 20, 20) @[RegMapper.scala 82:29] + node _T_7675 = bits(_T_692.bits.index, 21, 21) @[RegMapper.scala 82:29] + node _T_7676 = bits(_T_692.bits.index, 22, 22) @[RegMapper.scala 82:29] + node _T_7677 = cat(_T_7655, _T_7654) @[Cat.scala 30:58] + node _T_7678 = cat(_T_7657, _T_7656) @[Cat.scala 30:58] + node _T_7679 = cat(_T_7678, _T_7677) @[Cat.scala 30:58] + node _T_7680 = cat(_T_7663, _T_7658) @[Cat.scala 30:58] + node _T_7681 = cat(_T_7672, _T_7664) @[Cat.scala 30:58] + node _T_7682 = cat(_T_7681, _T_7680) @[Cat.scala 30:58] + node _T_7683 = cat(_T_7682, _T_7679) @[Cat.scala 30:58] + node _T_7684 = bits(_T_692.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_7685 = bits(_T_692.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_7686 = bits(_T_692.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_7687 = bits(_T_692.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_7688 = bits(_T_692.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_7689 = bits(_T_692.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_7690 = bits(_T_692.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_7691 = bits(_T_692.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_7692 = bits(_T_692.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_7693 = bits(_T_692.bits.index, 9, 9) @[RegMapper.scala 82:29] + node _T_7694 = bits(_T_692.bits.index, 10, 10) @[RegMapper.scala 82:29] + node _T_7695 = bits(_T_692.bits.index, 11, 11) @[RegMapper.scala 82:29] + node _T_7696 = bits(_T_692.bits.index, 12, 12) @[RegMapper.scala 82:29] + node _T_7697 = bits(_T_692.bits.index, 13, 13) @[RegMapper.scala 82:29] + node _T_7698 = bits(_T_692.bits.index, 14, 14) @[RegMapper.scala 82:29] + node _T_7699 = bits(_T_692.bits.index, 15, 15) @[RegMapper.scala 82:29] + node _T_7700 = bits(_T_692.bits.index, 16, 16) @[RegMapper.scala 82:29] + node _T_7701 = bits(_T_692.bits.index, 17, 17) @[RegMapper.scala 82:29] + node _T_7702 = bits(_T_692.bits.index, 18, 18) @[RegMapper.scala 82:29] + node _T_7703 = bits(_T_692.bits.index, 19, 19) @[RegMapper.scala 82:29] + node _T_7704 = bits(_T_692.bits.index, 20, 20) @[RegMapper.scala 82:29] + node _T_7705 = bits(_T_692.bits.index, 21, 21) @[RegMapper.scala 82:29] + node _T_7706 = bits(_T_692.bits.index, 22, 22) @[RegMapper.scala 82:29] + node _T_7707 = cat(_T_7685, _T_7684) @[Cat.scala 30:58] + node _T_7708 = cat(_T_7687, _T_7686) @[Cat.scala 30:58] + node _T_7709 = cat(_T_7708, _T_7707) @[Cat.scala 30:58] + node _T_7710 = cat(_T_7693, _T_7688) @[Cat.scala 30:58] + node _T_7711 = cat(_T_7702, _T_7694) @[Cat.scala 30:58] + node _T_7712 = cat(_T_7711, _T_7710) @[Cat.scala 30:58] + node _T_7713 = cat(_T_7712, _T_7709) @[Cat.scala 30:58] + node _T_7716 = mux(_T_692.bits.read, _T_4260[_T_7683], _T_5305[_T_7683]) @[RegMapper.scala 160:21] + node _T_7719 = mux(_T_692.bits.read, _T_6350[_T_7713], _T_7395[_T_7713]) @[RegMapper.scala 161:21] + node _T_7720 = and(_T_692.ready, _T_7716) @[RegMapper.scala 164:32] + _T_616.ready <= _T_7720 @[RegMapper.scala 164:17] + node _T_7721 = and(_T_616.valid, _T_7716) @[RegMapper.scala 165:32] + _T_692.valid <= _T_7721 @[RegMapper.scala 165:17] + node _T_7722 = and(_T_656.ready, _T_7719) @[RegMapper.scala 166:32] + _T_692.ready <= _T_7722 @[RegMapper.scala 166:17] + node _T_7723 = and(_T_692.valid, _T_7719) @[RegMapper.scala 167:32] + _T_656.valid <= _T_7723 @[RegMapper.scala 167:17] + node _T_7725 = dshl(UInt<1>("h01"), _T_7683) @[OneHot.scala 47:11] + node _T_7726 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7727 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7728 = cat(_T_7727, _T_7726) @[Cat.scala 30:58] + node _T_7729 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7730 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7731 = cat(_T_7730, _T_7729) @[Cat.scala 30:58] + node _T_7732 = cat(_T_7731, _T_7728) @[Cat.scala 30:58] + node _T_7733 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7734 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7735 = cat(_T_7734, _T_7733) @[Cat.scala 30:58] + node _T_7736 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7737 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7738 = cat(_T_7737, _T_7736) @[Cat.scala 30:58] + node _T_7739 = cat(_T_7738, _T_7735) @[Cat.scala 30:58] + node _T_7740 = cat(_T_7739, _T_7732) @[Cat.scala 30:58] + node _T_7741 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7742 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7743 = cat(_T_7742, _T_7741) @[Cat.scala 30:58] + node _T_7744 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7745 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7746 = cat(_T_7745, _T_7744) @[Cat.scala 30:58] + node _T_7747 = cat(_T_7746, _T_7743) @[Cat.scala 30:58] + node _T_7748 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7749 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7750 = cat(_T_7749, _T_7748) @[Cat.scala 30:58] + node _T_7751 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7752 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7753 = cat(_T_7752, _T_7751) @[Cat.scala 30:58] + node _T_7754 = cat(_T_7753, _T_7750) @[Cat.scala 30:58] + node _T_7755 = cat(_T_7754, _T_7747) @[Cat.scala 30:58] + node _T_7756 = cat(_T_7755, _T_7740) @[Cat.scala 30:58] + node _T_7757 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7758 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7759 = cat(_T_7758, _T_7757) @[Cat.scala 30:58] + node _T_7760 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7761 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7762 = cat(_T_7761, _T_7760) @[Cat.scala 30:58] + node _T_7763 = cat(_T_7762, _T_7759) @[Cat.scala 30:58] + node _T_7764 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7765 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7766 = cat(_T_7765, _T_7764) @[Cat.scala 30:58] + node _T_7767 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7768 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7769 = cat(_T_7768, _T_7767) @[Cat.scala 30:58] + node _T_7770 = cat(_T_7769, _T_7766) @[Cat.scala 30:58] + node _T_7771 = cat(_T_7770, _T_7763) @[Cat.scala 30:58] + node _T_7772 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7773 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7774 = cat(_T_7773, _T_7772) @[Cat.scala 30:58] + node _T_7775 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7776 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7777 = cat(_T_7776, _T_7775) @[Cat.scala 30:58] + node _T_7778 = cat(_T_7777, _T_7774) @[Cat.scala 30:58] + node _T_7779 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7780 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7781 = cat(_T_7780, _T_7779) @[Cat.scala 30:58] + node _T_7782 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7783 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7784 = cat(_T_7783, _T_7782) @[Cat.scala 30:58] + node _T_7785 = cat(_T_7784, _T_7781) @[Cat.scala 30:58] + node _T_7786 = cat(_T_7785, _T_7778) @[Cat.scala 30:58] + node _T_7787 = cat(_T_7786, _T_7771) @[Cat.scala 30:58] + node _T_7788 = cat(_T_7787, _T_7756) @[Cat.scala 30:58] + node _T_7789 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7790 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7791 = cat(_T_7790, _T_7789) @[Cat.scala 30:58] + node _T_7792 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7793 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7794 = cat(_T_7793, _T_7792) @[Cat.scala 30:58] + node _T_7795 = cat(_T_7794, _T_7791) @[Cat.scala 30:58] + node _T_7796 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7797 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7798 = cat(_T_7797, _T_7796) @[Cat.scala 30:58] + node _T_7799 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7800 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7801 = cat(_T_7800, _T_7799) @[Cat.scala 30:58] + node _T_7802 = cat(_T_7801, _T_7798) @[Cat.scala 30:58] + node _T_7803 = cat(_T_7802, _T_7795) @[Cat.scala 30:58] + node _T_7804 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7805 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7806 = cat(_T_7805, _T_7804) @[Cat.scala 30:58] + node _T_7807 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7808 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7809 = cat(_T_7808, _T_7807) @[Cat.scala 30:58] + node _T_7810 = cat(_T_7809, _T_7806) @[Cat.scala 30:58] + node _T_7811 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7812 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7813 = cat(_T_7812, _T_7811) @[Cat.scala 30:58] + node _T_7814 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7815 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7816 = cat(_T_7815, _T_7814) @[Cat.scala 30:58] + node _T_7817 = cat(_T_7816, _T_7813) @[Cat.scala 30:58] + node _T_7818 = cat(_T_7817, _T_7810) @[Cat.scala 30:58] + node _T_7819 = cat(_T_7818, _T_7803) @[Cat.scala 30:58] + node _T_7820 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7821 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7822 = cat(_T_7821, _T_7820) @[Cat.scala 30:58] + node _T_7823 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7824 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7825 = cat(_T_7824, _T_7823) @[Cat.scala 30:58] + node _T_7826 = cat(_T_7825, _T_7822) @[Cat.scala 30:58] + node _T_7827 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7828 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7829 = cat(_T_7828, _T_7827) @[Cat.scala 30:58] + node _T_7830 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7831 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7832 = cat(_T_7831, _T_7830) @[Cat.scala 30:58] + node _T_7833 = cat(_T_7832, _T_7829) @[Cat.scala 30:58] + node _T_7834 = cat(_T_7833, _T_7826) @[Cat.scala 30:58] + node _T_7835 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7836 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7837 = cat(_T_7836, _T_7835) @[Cat.scala 30:58] + node _T_7838 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7839 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7840 = cat(_T_7839, _T_7838) @[Cat.scala 30:58] + node _T_7841 = cat(_T_7840, _T_7837) @[Cat.scala 30:58] + node _T_7842 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7843 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7844 = cat(_T_7843, _T_7842) @[Cat.scala 30:58] + node _T_7845 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7846 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7847 = cat(_T_7846, _T_7845) @[Cat.scala 30:58] + node _T_7848 = cat(_T_7847, _T_7844) @[Cat.scala 30:58] + node _T_7849 = cat(_T_7848, _T_7841) @[Cat.scala 30:58] + node _T_7850 = cat(_T_7849, _T_7834) @[Cat.scala 30:58] + node _T_7851 = cat(_T_7850, _T_7819) @[Cat.scala 30:58] + node _T_7852 = cat(_T_7851, _T_7788) @[Cat.scala 30:58] + node _T_7853 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7854 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7855 = cat(_T_7854, _T_7853) @[Cat.scala 30:58] + node _T_7856 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7857 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7858 = cat(_T_7857, _T_7856) @[Cat.scala 30:58] + node _T_7859 = cat(_T_7858, _T_7855) @[Cat.scala 30:58] + node _T_7860 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7861 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7862 = cat(_T_7861, _T_7860) @[Cat.scala 30:58] + node _T_7863 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7864 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7865 = cat(_T_7864, _T_7863) @[Cat.scala 30:58] + node _T_7866 = cat(_T_7865, _T_7862) @[Cat.scala 30:58] + node _T_7867 = cat(_T_7866, _T_7859) @[Cat.scala 30:58] + node _T_7868 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7869 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7870 = cat(_T_7869, _T_7868) @[Cat.scala 30:58] + node _T_7871 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7872 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7873 = cat(_T_7872, _T_7871) @[Cat.scala 30:58] + node _T_7874 = cat(_T_7873, _T_7870) @[Cat.scala 30:58] + node _T_7875 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7876 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7877 = cat(_T_7876, _T_7875) @[Cat.scala 30:58] + node _T_7878 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7879 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7880 = cat(_T_7879, _T_7878) @[Cat.scala 30:58] + node _T_7881 = cat(_T_7880, _T_7877) @[Cat.scala 30:58] + node _T_7882 = cat(_T_7881, _T_7874) @[Cat.scala 30:58] + node _T_7883 = cat(_T_7882, _T_7867) @[Cat.scala 30:58] + node _T_7884 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7885 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7886 = cat(_T_7885, _T_7884) @[Cat.scala 30:58] + node _T_7887 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7888 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7889 = cat(_T_7888, _T_7887) @[Cat.scala 30:58] + node _T_7890 = cat(_T_7889, _T_7886) @[Cat.scala 30:58] + node _T_7891 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7892 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7893 = cat(_T_7892, _T_7891) @[Cat.scala 30:58] + node _T_7894 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7895 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7896 = cat(_T_7895, _T_7894) @[Cat.scala 30:58] + node _T_7897 = cat(_T_7896, _T_7893) @[Cat.scala 30:58] + node _T_7898 = cat(_T_7897, _T_7890) @[Cat.scala 30:58] + node _T_7899 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7900 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7901 = cat(_T_7900, _T_7899) @[Cat.scala 30:58] + node _T_7902 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7903 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7904 = cat(_T_7903, _T_7902) @[Cat.scala 30:58] + node _T_7905 = cat(_T_7904, _T_7901) @[Cat.scala 30:58] + node _T_7906 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7907 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7908 = cat(_T_7907, _T_7906) @[Cat.scala 30:58] + node _T_7909 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7910 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7911 = cat(_T_7910, _T_7909) @[Cat.scala 30:58] + node _T_7912 = cat(_T_7911, _T_7908) @[Cat.scala 30:58] + node _T_7913 = cat(_T_7912, _T_7905) @[Cat.scala 30:58] + node _T_7914 = cat(_T_7913, _T_7898) @[Cat.scala 30:58] + node _T_7915 = cat(_T_7914, _T_7883) @[Cat.scala 30:58] + node _T_7916 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7917 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7918 = cat(_T_7917, _T_7916) @[Cat.scala 30:58] + node _T_7919 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7920 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7921 = cat(_T_7920, _T_7919) @[Cat.scala 30:58] + node _T_7922 = cat(_T_7921, _T_7918) @[Cat.scala 30:58] + node _T_7923 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7924 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7925 = cat(_T_7924, _T_7923) @[Cat.scala 30:58] + node _T_7926 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7927 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7928 = cat(_T_7927, _T_7926) @[Cat.scala 30:58] + node _T_7929 = cat(_T_7928, _T_7925) @[Cat.scala 30:58] + node _T_7930 = cat(_T_7929, _T_7922) @[Cat.scala 30:58] + node _T_7931 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7932 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7933 = cat(_T_7932, _T_7931) @[Cat.scala 30:58] + node _T_7934 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7935 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7936 = cat(_T_7935, _T_7934) @[Cat.scala 30:58] + node _T_7937 = cat(_T_7936, _T_7933) @[Cat.scala 30:58] + node _T_7938 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7939 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7940 = cat(_T_7939, _T_7938) @[Cat.scala 30:58] + node _T_7941 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7942 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7943 = cat(_T_7942, _T_7941) @[Cat.scala 30:58] + node _T_7944 = cat(_T_7943, _T_7940) @[Cat.scala 30:58] + node _T_7945 = cat(_T_7944, _T_7937) @[Cat.scala 30:58] + node _T_7946 = cat(_T_7945, _T_7930) @[Cat.scala 30:58] + node _T_7947 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7948 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7949 = cat(_T_7948, _T_7947) @[Cat.scala 30:58] + node _T_7950 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7951 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7952 = cat(_T_7951, _T_7950) @[Cat.scala 30:58] + node _T_7953 = cat(_T_7952, _T_7949) @[Cat.scala 30:58] + node _T_7954 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7955 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7956 = cat(_T_7955, _T_7954) @[Cat.scala 30:58] + node _T_7957 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7958 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7959 = cat(_T_7958, _T_7957) @[Cat.scala 30:58] + node _T_7960 = cat(_T_7959, _T_7956) @[Cat.scala 30:58] + node _T_7961 = cat(_T_7960, _T_7953) @[Cat.scala 30:58] + node _T_7962 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7963 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7964 = cat(_T_7963, _T_7962) @[Cat.scala 30:58] + node _T_7965 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7966 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7967 = cat(_T_7966, _T_7965) @[Cat.scala 30:58] + node _T_7968 = cat(_T_7967, _T_7964) @[Cat.scala 30:58] + node _T_7969 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7970 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7971 = cat(_T_7970, _T_7969) @[Cat.scala 30:58] + node _T_7972 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7973 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7974 = cat(_T_7973, _T_7972) @[Cat.scala 30:58] + node _T_7975 = cat(_T_7974, _T_7971) @[Cat.scala 30:58] + node _T_7976 = cat(_T_7975, _T_7968) @[Cat.scala 30:58] + node _T_7977 = cat(_T_7976, _T_7961) @[Cat.scala 30:58] + node _T_7978 = cat(_T_7977, _T_7946) @[Cat.scala 30:58] + node _T_7979 = cat(_T_7978, _T_7915) @[Cat.scala 30:58] + node _T_7980 = cat(_T_7979, _T_7852) @[Cat.scala 30:58] + node _T_7981 = and(_T_7725, _T_7980) @[RegMapper.scala 170:37] + node _T_7983 = dshl(UInt<1>("h01"), _T_7713) @[OneHot.scala 47:11] + node _T_7984 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7985 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7986 = cat(_T_7985, _T_7984) @[Cat.scala 30:58] + node _T_7987 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7988 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7989 = cat(_T_7988, _T_7987) @[Cat.scala 30:58] + node _T_7990 = cat(_T_7989, _T_7986) @[Cat.scala 30:58] + node _T_7991 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7992 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7993 = cat(_T_7992, _T_7991) @[Cat.scala 30:58] + node _T_7994 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7995 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_7996 = cat(_T_7995, _T_7994) @[Cat.scala 30:58] + node _T_7997 = cat(_T_7996, _T_7993) @[Cat.scala 30:58] + node _T_7998 = cat(_T_7997, _T_7990) @[Cat.scala 30:58] + node _T_7999 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8000 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8001 = cat(_T_8000, _T_7999) @[Cat.scala 30:58] + node _T_8002 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8003 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8004 = cat(_T_8003, _T_8002) @[Cat.scala 30:58] + node _T_8005 = cat(_T_8004, _T_8001) @[Cat.scala 30:58] + node _T_8006 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8007 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8008 = cat(_T_8007, _T_8006) @[Cat.scala 30:58] + node _T_8009 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8010 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8011 = cat(_T_8010, _T_8009) @[Cat.scala 30:58] + node _T_8012 = cat(_T_8011, _T_8008) @[Cat.scala 30:58] + node _T_8013 = cat(_T_8012, _T_8005) @[Cat.scala 30:58] + node _T_8014 = cat(_T_8013, _T_7998) @[Cat.scala 30:58] + node _T_8015 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8016 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8017 = cat(_T_8016, _T_8015) @[Cat.scala 30:58] + node _T_8018 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8019 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8020 = cat(_T_8019, _T_8018) @[Cat.scala 30:58] + node _T_8021 = cat(_T_8020, _T_8017) @[Cat.scala 30:58] + node _T_8022 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8023 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8024 = cat(_T_8023, _T_8022) @[Cat.scala 30:58] + node _T_8025 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8026 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8027 = cat(_T_8026, _T_8025) @[Cat.scala 30:58] + node _T_8028 = cat(_T_8027, _T_8024) @[Cat.scala 30:58] + node _T_8029 = cat(_T_8028, _T_8021) @[Cat.scala 30:58] + node _T_8030 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8031 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8032 = cat(_T_8031, _T_8030) @[Cat.scala 30:58] + node _T_8033 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8034 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8035 = cat(_T_8034, _T_8033) @[Cat.scala 30:58] + node _T_8036 = cat(_T_8035, _T_8032) @[Cat.scala 30:58] + node _T_8037 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8038 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8039 = cat(_T_8038, _T_8037) @[Cat.scala 30:58] + node _T_8040 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8041 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8042 = cat(_T_8041, _T_8040) @[Cat.scala 30:58] + node _T_8043 = cat(_T_8042, _T_8039) @[Cat.scala 30:58] + node _T_8044 = cat(_T_8043, _T_8036) @[Cat.scala 30:58] + node _T_8045 = cat(_T_8044, _T_8029) @[Cat.scala 30:58] + node _T_8046 = cat(_T_8045, _T_8014) @[Cat.scala 30:58] + node _T_8047 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8048 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8049 = cat(_T_8048, _T_8047) @[Cat.scala 30:58] + node _T_8050 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8051 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8052 = cat(_T_8051, _T_8050) @[Cat.scala 30:58] + node _T_8053 = cat(_T_8052, _T_8049) @[Cat.scala 30:58] + node _T_8054 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8055 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8056 = cat(_T_8055, _T_8054) @[Cat.scala 30:58] + node _T_8057 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8058 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8059 = cat(_T_8058, _T_8057) @[Cat.scala 30:58] + node _T_8060 = cat(_T_8059, _T_8056) @[Cat.scala 30:58] + node _T_8061 = cat(_T_8060, _T_8053) @[Cat.scala 30:58] + node _T_8062 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8063 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8064 = cat(_T_8063, _T_8062) @[Cat.scala 30:58] + node _T_8065 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8066 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8067 = cat(_T_8066, _T_8065) @[Cat.scala 30:58] + node _T_8068 = cat(_T_8067, _T_8064) @[Cat.scala 30:58] + node _T_8069 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8070 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8071 = cat(_T_8070, _T_8069) @[Cat.scala 30:58] + node _T_8072 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8073 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8074 = cat(_T_8073, _T_8072) @[Cat.scala 30:58] + node _T_8075 = cat(_T_8074, _T_8071) @[Cat.scala 30:58] + node _T_8076 = cat(_T_8075, _T_8068) @[Cat.scala 30:58] + node _T_8077 = cat(_T_8076, _T_8061) @[Cat.scala 30:58] + node _T_8078 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8079 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8080 = cat(_T_8079, _T_8078) @[Cat.scala 30:58] + node _T_8081 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8082 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8083 = cat(_T_8082, _T_8081) @[Cat.scala 30:58] + node _T_8084 = cat(_T_8083, _T_8080) @[Cat.scala 30:58] + node _T_8085 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8086 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8087 = cat(_T_8086, _T_8085) @[Cat.scala 30:58] + node _T_8088 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8089 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8090 = cat(_T_8089, _T_8088) @[Cat.scala 30:58] + node _T_8091 = cat(_T_8090, _T_8087) @[Cat.scala 30:58] + node _T_8092 = cat(_T_8091, _T_8084) @[Cat.scala 30:58] + node _T_8093 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8094 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8095 = cat(_T_8094, _T_8093) @[Cat.scala 30:58] + node _T_8096 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8097 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8098 = cat(_T_8097, _T_8096) @[Cat.scala 30:58] + node _T_8099 = cat(_T_8098, _T_8095) @[Cat.scala 30:58] + node _T_8100 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8101 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8102 = cat(_T_8101, _T_8100) @[Cat.scala 30:58] + node _T_8103 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8104 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8105 = cat(_T_8104, _T_8103) @[Cat.scala 30:58] + node _T_8106 = cat(_T_8105, _T_8102) @[Cat.scala 30:58] + node _T_8107 = cat(_T_8106, _T_8099) @[Cat.scala 30:58] + node _T_8108 = cat(_T_8107, _T_8092) @[Cat.scala 30:58] + node _T_8109 = cat(_T_8108, _T_8077) @[Cat.scala 30:58] + node _T_8110 = cat(_T_8109, _T_8046) @[Cat.scala 30:58] + node _T_8111 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8112 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8113 = cat(_T_8112, _T_8111) @[Cat.scala 30:58] + node _T_8114 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8115 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8116 = cat(_T_8115, _T_8114) @[Cat.scala 30:58] + node _T_8117 = cat(_T_8116, _T_8113) @[Cat.scala 30:58] + node _T_8118 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8119 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8120 = cat(_T_8119, _T_8118) @[Cat.scala 30:58] + node _T_8121 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8122 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8123 = cat(_T_8122, _T_8121) @[Cat.scala 30:58] + node _T_8124 = cat(_T_8123, _T_8120) @[Cat.scala 30:58] + node _T_8125 = cat(_T_8124, _T_8117) @[Cat.scala 30:58] + node _T_8126 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8127 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8128 = cat(_T_8127, _T_8126) @[Cat.scala 30:58] + node _T_8129 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8130 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8131 = cat(_T_8130, _T_8129) @[Cat.scala 30:58] + node _T_8132 = cat(_T_8131, _T_8128) @[Cat.scala 30:58] + node _T_8133 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8134 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8135 = cat(_T_8134, _T_8133) @[Cat.scala 30:58] + node _T_8136 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8137 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8138 = cat(_T_8137, _T_8136) @[Cat.scala 30:58] + node _T_8139 = cat(_T_8138, _T_8135) @[Cat.scala 30:58] + node _T_8140 = cat(_T_8139, _T_8132) @[Cat.scala 30:58] + node _T_8141 = cat(_T_8140, _T_8125) @[Cat.scala 30:58] + node _T_8142 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8143 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8144 = cat(_T_8143, _T_8142) @[Cat.scala 30:58] + node _T_8145 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8146 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8147 = cat(_T_8146, _T_8145) @[Cat.scala 30:58] + node _T_8148 = cat(_T_8147, _T_8144) @[Cat.scala 30:58] + node _T_8149 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8150 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8151 = cat(_T_8150, _T_8149) @[Cat.scala 30:58] + node _T_8152 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8153 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8154 = cat(_T_8153, _T_8152) @[Cat.scala 30:58] + node _T_8155 = cat(_T_8154, _T_8151) @[Cat.scala 30:58] + node _T_8156 = cat(_T_8155, _T_8148) @[Cat.scala 30:58] + node _T_8157 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8158 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8159 = cat(_T_8158, _T_8157) @[Cat.scala 30:58] + node _T_8160 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8161 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8162 = cat(_T_8161, _T_8160) @[Cat.scala 30:58] + node _T_8163 = cat(_T_8162, _T_8159) @[Cat.scala 30:58] + node _T_8164 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8165 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8166 = cat(_T_8165, _T_8164) @[Cat.scala 30:58] + node _T_8167 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8168 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8169 = cat(_T_8168, _T_8167) @[Cat.scala 30:58] + node _T_8170 = cat(_T_8169, _T_8166) @[Cat.scala 30:58] + node _T_8171 = cat(_T_8170, _T_8163) @[Cat.scala 30:58] + node _T_8172 = cat(_T_8171, _T_8156) @[Cat.scala 30:58] + node _T_8173 = cat(_T_8172, _T_8141) @[Cat.scala 30:58] + node _T_8174 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8175 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8176 = cat(_T_8175, _T_8174) @[Cat.scala 30:58] + node _T_8177 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8178 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8179 = cat(_T_8178, _T_8177) @[Cat.scala 30:58] + node _T_8180 = cat(_T_8179, _T_8176) @[Cat.scala 30:58] + node _T_8181 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8182 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8183 = cat(_T_8182, _T_8181) @[Cat.scala 30:58] + node _T_8184 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8185 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8186 = cat(_T_8185, _T_8184) @[Cat.scala 30:58] + node _T_8187 = cat(_T_8186, _T_8183) @[Cat.scala 30:58] + node _T_8188 = cat(_T_8187, _T_8180) @[Cat.scala 30:58] + node _T_8189 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8190 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8191 = cat(_T_8190, _T_8189) @[Cat.scala 30:58] + node _T_8192 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8193 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8194 = cat(_T_8193, _T_8192) @[Cat.scala 30:58] + node _T_8195 = cat(_T_8194, _T_8191) @[Cat.scala 30:58] + node _T_8196 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8197 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8198 = cat(_T_8197, _T_8196) @[Cat.scala 30:58] + node _T_8199 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8200 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8201 = cat(_T_8200, _T_8199) @[Cat.scala 30:58] + node _T_8202 = cat(_T_8201, _T_8198) @[Cat.scala 30:58] + node _T_8203 = cat(_T_8202, _T_8195) @[Cat.scala 30:58] + node _T_8204 = cat(_T_8203, _T_8188) @[Cat.scala 30:58] + node _T_8205 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8206 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8207 = cat(_T_8206, _T_8205) @[Cat.scala 30:58] + node _T_8208 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8209 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8210 = cat(_T_8209, _T_8208) @[Cat.scala 30:58] + node _T_8211 = cat(_T_8210, _T_8207) @[Cat.scala 30:58] + node _T_8212 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8213 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8214 = cat(_T_8213, _T_8212) @[Cat.scala 30:58] + node _T_8215 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8216 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8217 = cat(_T_8216, _T_8215) @[Cat.scala 30:58] + node _T_8218 = cat(_T_8217, _T_8214) @[Cat.scala 30:58] + node _T_8219 = cat(_T_8218, _T_8211) @[Cat.scala 30:58] + node _T_8220 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8221 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8222 = cat(_T_8221, _T_8220) @[Cat.scala 30:58] + node _T_8223 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8224 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8225 = cat(_T_8224, _T_8223) @[Cat.scala 30:58] + node _T_8226 = cat(_T_8225, _T_8222) @[Cat.scala 30:58] + node _T_8227 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8228 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8229 = cat(_T_8228, _T_8227) @[Cat.scala 30:58] + node _T_8230 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8231 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_8232 = cat(_T_8231, _T_8230) @[Cat.scala 30:58] + node _T_8233 = cat(_T_8232, _T_8229) @[Cat.scala 30:58] + node _T_8234 = cat(_T_8233, _T_8226) @[Cat.scala 30:58] + node _T_8235 = cat(_T_8234, _T_8219) @[Cat.scala 30:58] + node _T_8236 = cat(_T_8235, _T_8204) @[Cat.scala 30:58] + node _T_8237 = cat(_T_8236, _T_8173) @[Cat.scala 30:58] + node _T_8238 = cat(_T_8237, _T_8110) @[Cat.scala 30:58] + node _T_8239 = and(_T_7983, _T_8238) @[RegMapper.scala 171:37] + node _T_8240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8241 = and(_T_8240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8242 = bits(_T_7981, 0, 0) @[RegMapper.scala 175:77] + node _T_8243 = and(_T_8241, _T_8242) @[RegMapper.scala 175:66] + node _T_8244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8247 = and(_T_8244, _T_8246) @[RegMapper.scala 176:46] + node _T_8248 = bits(_T_7981, 0, 0) @[RegMapper.scala 176:77] + node _T_8249 = and(_T_8247, _T_8248) @[RegMapper.scala 176:66] + node _T_8250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8251 = and(_T_8250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8252 = bits(_T_8239, 0, 0) @[RegMapper.scala 177:77] + node _T_8253 = and(_T_8251, _T_8252) @[RegMapper.scala 177:66] + node _T_8254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8257 = and(_T_8254, _T_8256) @[RegMapper.scala 178:46] + node _T_8258 = bits(_T_8239, 0, 0) @[RegMapper.scala 178:77] + node _T_8259 = and(_T_8257, _T_8258) @[RegMapper.scala 178:66] + node _T_8260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8261 = and(_T_8260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8262 = bits(_T_7981, 1, 1) @[RegMapper.scala 175:77] + node _T_8263 = and(_T_8261, _T_8262) @[RegMapper.scala 175:66] + node _T_8264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8267 = and(_T_8264, _T_8266) @[RegMapper.scala 176:46] + node _T_8268 = bits(_T_7981, 1, 1) @[RegMapper.scala 176:77] + node _T_8269 = and(_T_8267, _T_8268) @[RegMapper.scala 176:66] + node _T_8270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8271 = and(_T_8270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8272 = bits(_T_8239, 1, 1) @[RegMapper.scala 177:77] + node _T_8273 = and(_T_8271, _T_8272) @[RegMapper.scala 177:66] + node _T_8274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8277 = and(_T_8274, _T_8276) @[RegMapper.scala 178:46] + node _T_8278 = bits(_T_8239, 1, 1) @[RegMapper.scala 178:77] + node _T_8279 = and(_T_8277, _T_8278) @[RegMapper.scala 178:66] + node _T_8280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8281 = and(_T_8280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8282 = bits(_T_7981, 2, 2) @[RegMapper.scala 175:77] + node _T_8283 = and(_T_8281, _T_8282) @[RegMapper.scala 175:66] + node _T_8284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8287 = and(_T_8284, _T_8286) @[RegMapper.scala 176:46] + node _T_8288 = bits(_T_7981, 2, 2) @[RegMapper.scala 176:77] + node _T_8289 = and(_T_8287, _T_8288) @[RegMapper.scala 176:66] + node _T_8290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8291 = and(_T_8290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8292 = bits(_T_8239, 2, 2) @[RegMapper.scala 177:77] + node _T_8293 = and(_T_8291, _T_8292) @[RegMapper.scala 177:66] + node _T_8294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8297 = and(_T_8294, _T_8296) @[RegMapper.scala 178:46] + node _T_8298 = bits(_T_8239, 2, 2) @[RegMapper.scala 178:77] + node _T_8299 = and(_T_8297, _T_8298) @[RegMapper.scala 178:66] + node _T_8300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8301 = and(_T_8300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8302 = bits(_T_7981, 3, 3) @[RegMapper.scala 175:77] + node _T_8303 = and(_T_8301, _T_8302) @[RegMapper.scala 175:66] + node _T_8304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8307 = and(_T_8304, _T_8306) @[RegMapper.scala 176:46] + node _T_8308 = bits(_T_7981, 3, 3) @[RegMapper.scala 176:77] + node _T_8309 = and(_T_8307, _T_8308) @[RegMapper.scala 176:66] + node _T_8310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8311 = and(_T_8310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8312 = bits(_T_8239, 3, 3) @[RegMapper.scala 177:77] + node _T_8313 = and(_T_8311, _T_8312) @[RegMapper.scala 177:66] + node _T_8314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8317 = and(_T_8314, _T_8316) @[RegMapper.scala 178:46] + node _T_8318 = bits(_T_8239, 3, 3) @[RegMapper.scala 178:77] + node _T_8319 = and(_T_8317, _T_8318) @[RegMapper.scala 178:66] + node _T_8320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8321 = and(_T_8320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8322 = bits(_T_7981, 4, 4) @[RegMapper.scala 175:77] + node _T_8323 = and(_T_8321, _T_8322) @[RegMapper.scala 175:66] + node _T_8324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8327 = and(_T_8324, _T_8326) @[RegMapper.scala 176:46] + node _T_8328 = bits(_T_7981, 4, 4) @[RegMapper.scala 176:77] + node _T_8329 = and(_T_8327, _T_8328) @[RegMapper.scala 176:66] + node _T_8330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8331 = and(_T_8330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8332 = bits(_T_8239, 4, 4) @[RegMapper.scala 177:77] + node _T_8333 = and(_T_8331, _T_8332) @[RegMapper.scala 177:66] + node _T_8334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8337 = and(_T_8334, _T_8336) @[RegMapper.scala 178:46] + node _T_8338 = bits(_T_8239, 4, 4) @[RegMapper.scala 178:77] + node _T_8339 = and(_T_8337, _T_8338) @[RegMapper.scala 178:66] + node _T_8340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8341 = and(_T_8340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8342 = bits(_T_7981, 5, 5) @[RegMapper.scala 175:77] + node _T_8343 = and(_T_8341, _T_8342) @[RegMapper.scala 175:66] + node _T_8344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8347 = and(_T_8344, _T_8346) @[RegMapper.scala 176:46] + node _T_8348 = bits(_T_7981, 5, 5) @[RegMapper.scala 176:77] + node _T_8349 = and(_T_8347, _T_8348) @[RegMapper.scala 176:66] + node _T_8350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8351 = and(_T_8350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8352 = bits(_T_8239, 5, 5) @[RegMapper.scala 177:77] + node _T_8353 = and(_T_8351, _T_8352) @[RegMapper.scala 177:66] + node _T_8354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8357 = and(_T_8354, _T_8356) @[RegMapper.scala 178:46] + node _T_8358 = bits(_T_8239, 5, 5) @[RegMapper.scala 178:77] + node _T_8359 = and(_T_8357, _T_8358) @[RegMapper.scala 178:66] + node _T_8360 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8361 = and(_T_8360, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8362 = bits(_T_7981, 6, 6) @[RegMapper.scala 175:77] + node _T_8363 = and(_T_8361, _T_8362) @[RegMapper.scala 175:66] + node _T_8364 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8366 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8367 = and(_T_8364, _T_8366) @[RegMapper.scala 176:46] + node _T_8368 = bits(_T_7981, 6, 6) @[RegMapper.scala 176:77] + node _T_8369 = and(_T_8367, _T_8368) @[RegMapper.scala 176:66] + node _T_8370 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8371 = and(_T_8370, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8372 = bits(_T_8239, 6, 6) @[RegMapper.scala 177:77] + node _T_8373 = and(_T_8371, _T_8372) @[RegMapper.scala 177:66] + node _T_8374 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8376 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8377 = and(_T_8374, _T_8376) @[RegMapper.scala 178:46] + node _T_8378 = bits(_T_8239, 6, 6) @[RegMapper.scala 178:77] + node _T_8379 = and(_T_8377, _T_8378) @[RegMapper.scala 178:66] + node _T_8380 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8381 = and(_T_8380, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8382 = bits(_T_7981, 7, 7) @[RegMapper.scala 175:77] + node _T_8383 = and(_T_8381, _T_8382) @[RegMapper.scala 175:66] + node _T_8384 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8386 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8387 = and(_T_8384, _T_8386) @[RegMapper.scala 176:46] + node _T_8388 = bits(_T_7981, 7, 7) @[RegMapper.scala 176:77] + node _T_8389 = and(_T_8387, _T_8388) @[RegMapper.scala 176:66] + node _T_8390 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8391 = and(_T_8390, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8392 = bits(_T_8239, 7, 7) @[RegMapper.scala 177:77] + node _T_8393 = and(_T_8391, _T_8392) @[RegMapper.scala 177:66] + node _T_8394 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8396 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8397 = and(_T_8394, _T_8396) @[RegMapper.scala 178:46] + node _T_8398 = bits(_T_8239, 7, 7) @[RegMapper.scala 178:77] + node _T_8399 = and(_T_8397, _T_8398) @[RegMapper.scala 178:66] + node _T_8400 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8401 = and(_T_8400, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8402 = bits(_T_7981, 8, 8) @[RegMapper.scala 175:77] + node _T_8403 = and(_T_8401, _T_8402) @[RegMapper.scala 175:66] + node _T_8404 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8406 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8407 = and(_T_8404, _T_8406) @[RegMapper.scala 176:46] + node _T_8408 = bits(_T_7981, 8, 8) @[RegMapper.scala 176:77] + node _T_8409 = and(_T_8407, _T_8408) @[RegMapper.scala 176:66] + node _T_8410 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8411 = and(_T_8410, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8412 = bits(_T_8239, 8, 8) @[RegMapper.scala 177:77] + node _T_8413 = and(_T_8411, _T_8412) @[RegMapper.scala 177:66] + node _T_8414 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8416 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8417 = and(_T_8414, _T_8416) @[RegMapper.scala 178:46] + node _T_8418 = bits(_T_8239, 8, 8) @[RegMapper.scala 178:77] + node _T_8419 = and(_T_8417, _T_8418) @[RegMapper.scala 178:66] + node _T_8420 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8421 = and(_T_8420, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8422 = bits(_T_7981, 9, 9) @[RegMapper.scala 175:77] + node _T_8423 = and(_T_8421, _T_8422) @[RegMapper.scala 175:66] + node _T_8424 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8426 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8427 = and(_T_8424, _T_8426) @[RegMapper.scala 176:46] + node _T_8428 = bits(_T_7981, 9, 9) @[RegMapper.scala 176:77] + node _T_8429 = and(_T_8427, _T_8428) @[RegMapper.scala 176:66] + node _T_8430 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8431 = and(_T_8430, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8432 = bits(_T_8239, 9, 9) @[RegMapper.scala 177:77] + node _T_8433 = and(_T_8431, _T_8432) @[RegMapper.scala 177:66] + node _T_8434 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8436 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8437 = and(_T_8434, _T_8436) @[RegMapper.scala 178:46] + node _T_8438 = bits(_T_8239, 9, 9) @[RegMapper.scala 178:77] + node _T_8439 = and(_T_8437, _T_8438) @[RegMapper.scala 178:66] + node _T_8440 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8441 = and(_T_8440, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8442 = bits(_T_7981, 10, 10) @[RegMapper.scala 175:77] + node _T_8443 = and(_T_8441, _T_8442) @[RegMapper.scala 175:66] + node _T_8444 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8446 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8447 = and(_T_8444, _T_8446) @[RegMapper.scala 176:46] + node _T_8448 = bits(_T_7981, 10, 10) @[RegMapper.scala 176:77] + node _T_8449 = and(_T_8447, _T_8448) @[RegMapper.scala 176:66] + node _T_8450 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8451 = and(_T_8450, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8452 = bits(_T_8239, 10, 10) @[RegMapper.scala 177:77] + node _T_8453 = and(_T_8451, _T_8452) @[RegMapper.scala 177:66] + node _T_8454 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8456 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8457 = and(_T_8454, _T_8456) @[RegMapper.scala 178:46] + node _T_8458 = bits(_T_8239, 10, 10) @[RegMapper.scala 178:77] + node _T_8459 = and(_T_8457, _T_8458) @[RegMapper.scala 178:66] + node _T_8460 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8461 = and(_T_8460, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8462 = bits(_T_7981, 11, 11) @[RegMapper.scala 175:77] + node _T_8463 = and(_T_8461, _T_8462) @[RegMapper.scala 175:66] + node _T_8464 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8466 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8467 = and(_T_8464, _T_8466) @[RegMapper.scala 176:46] + node _T_8468 = bits(_T_7981, 11, 11) @[RegMapper.scala 176:77] + node _T_8469 = and(_T_8467, _T_8468) @[RegMapper.scala 176:66] + node _T_8470 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8471 = and(_T_8470, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8472 = bits(_T_8239, 11, 11) @[RegMapper.scala 177:77] + node _T_8473 = and(_T_8471, _T_8472) @[RegMapper.scala 177:66] + node _T_8474 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8476 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8477 = and(_T_8474, _T_8476) @[RegMapper.scala 178:46] + node _T_8478 = bits(_T_8239, 11, 11) @[RegMapper.scala 178:77] + node _T_8479 = and(_T_8477, _T_8478) @[RegMapper.scala 178:66] + node _T_8480 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8481 = and(_T_8480, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8482 = bits(_T_7981, 12, 12) @[RegMapper.scala 175:77] + node _T_8483 = and(_T_8481, _T_8482) @[RegMapper.scala 175:66] + node _T_8484 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8486 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8487 = and(_T_8484, _T_8486) @[RegMapper.scala 176:46] + node _T_8488 = bits(_T_7981, 12, 12) @[RegMapper.scala 176:77] + node _T_8489 = and(_T_8487, _T_8488) @[RegMapper.scala 176:66] + node _T_8490 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8491 = and(_T_8490, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8492 = bits(_T_8239, 12, 12) @[RegMapper.scala 177:77] + node _T_8493 = and(_T_8491, _T_8492) @[RegMapper.scala 177:66] + node _T_8494 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8496 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8497 = and(_T_8494, _T_8496) @[RegMapper.scala 178:46] + node _T_8498 = bits(_T_8239, 12, 12) @[RegMapper.scala 178:77] + node _T_8499 = and(_T_8497, _T_8498) @[RegMapper.scala 178:66] + node _T_8500 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8501 = and(_T_8500, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8502 = bits(_T_7981, 13, 13) @[RegMapper.scala 175:77] + node _T_8503 = and(_T_8501, _T_8502) @[RegMapper.scala 175:66] + node _T_8504 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8506 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8507 = and(_T_8504, _T_8506) @[RegMapper.scala 176:46] + node _T_8508 = bits(_T_7981, 13, 13) @[RegMapper.scala 176:77] + node _T_8509 = and(_T_8507, _T_8508) @[RegMapper.scala 176:66] + node _T_8510 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8511 = and(_T_8510, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8512 = bits(_T_8239, 13, 13) @[RegMapper.scala 177:77] + node _T_8513 = and(_T_8511, _T_8512) @[RegMapper.scala 177:66] + node _T_8514 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8516 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8517 = and(_T_8514, _T_8516) @[RegMapper.scala 178:46] + node _T_8518 = bits(_T_8239, 13, 13) @[RegMapper.scala 178:77] + node _T_8519 = and(_T_8517, _T_8518) @[RegMapper.scala 178:66] + node _T_8520 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8521 = and(_T_8520, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8522 = bits(_T_7981, 14, 14) @[RegMapper.scala 175:77] + node _T_8523 = and(_T_8521, _T_8522) @[RegMapper.scala 175:66] + node _T_8524 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8526 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8527 = and(_T_8524, _T_8526) @[RegMapper.scala 176:46] + node _T_8528 = bits(_T_7981, 14, 14) @[RegMapper.scala 176:77] + node _T_8529 = and(_T_8527, _T_8528) @[RegMapper.scala 176:66] + node _T_8530 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8531 = and(_T_8530, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8532 = bits(_T_8239, 14, 14) @[RegMapper.scala 177:77] + node _T_8533 = and(_T_8531, _T_8532) @[RegMapper.scala 177:66] + node _T_8534 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8536 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8537 = and(_T_8534, _T_8536) @[RegMapper.scala 178:46] + node _T_8538 = bits(_T_8239, 14, 14) @[RegMapper.scala 178:77] + node _T_8539 = and(_T_8537, _T_8538) @[RegMapper.scala 178:66] + node _T_8540 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8541 = and(_T_8540, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8542 = bits(_T_7981, 15, 15) @[RegMapper.scala 175:77] + node _T_8543 = and(_T_8541, _T_8542) @[RegMapper.scala 175:66] + node _T_8544 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8546 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8547 = and(_T_8544, _T_8546) @[RegMapper.scala 176:46] + node _T_8548 = bits(_T_7981, 15, 15) @[RegMapper.scala 176:77] + node _T_8549 = and(_T_8547, _T_8548) @[RegMapper.scala 176:66] + node _T_8550 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8551 = and(_T_8550, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8552 = bits(_T_8239, 15, 15) @[RegMapper.scala 177:77] + node _T_8553 = and(_T_8551, _T_8552) @[RegMapper.scala 177:66] + node _T_8554 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8556 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8557 = and(_T_8554, _T_8556) @[RegMapper.scala 178:46] + node _T_8558 = bits(_T_8239, 15, 15) @[RegMapper.scala 178:77] + node _T_8559 = and(_T_8557, _T_8558) @[RegMapper.scala 178:66] + node _T_8560 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8561 = and(_T_8560, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8562 = bits(_T_7981, 16, 16) @[RegMapper.scala 175:77] + node _T_8563 = and(_T_8561, _T_8562) @[RegMapper.scala 175:66] + node _T_8564 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8566 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8567 = and(_T_8564, _T_8566) @[RegMapper.scala 176:46] + node _T_8568 = bits(_T_7981, 16, 16) @[RegMapper.scala 176:77] + node _T_8569 = and(_T_8567, _T_8568) @[RegMapper.scala 176:66] + node _T_8570 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8571 = and(_T_8570, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8572 = bits(_T_8239, 16, 16) @[RegMapper.scala 177:77] + node _T_8573 = and(_T_8571, _T_8572) @[RegMapper.scala 177:66] + node _T_8574 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8576 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8577 = and(_T_8574, _T_8576) @[RegMapper.scala 178:46] + node _T_8578 = bits(_T_8239, 16, 16) @[RegMapper.scala 178:77] + node _T_8579 = and(_T_8577, _T_8578) @[RegMapper.scala 178:66] + node _T_8580 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8581 = and(_T_8580, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8582 = bits(_T_7981, 17, 17) @[RegMapper.scala 175:77] + node _T_8583 = and(_T_8581, _T_8582) @[RegMapper.scala 175:66] + node _T_8584 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8586 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8587 = and(_T_8584, _T_8586) @[RegMapper.scala 176:46] + node _T_8588 = bits(_T_7981, 17, 17) @[RegMapper.scala 176:77] + node _T_8589 = and(_T_8587, _T_8588) @[RegMapper.scala 176:66] + node _T_8590 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8591 = and(_T_8590, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8592 = bits(_T_8239, 17, 17) @[RegMapper.scala 177:77] + node _T_8593 = and(_T_8591, _T_8592) @[RegMapper.scala 177:66] + node _T_8594 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8596 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8597 = and(_T_8594, _T_8596) @[RegMapper.scala 178:46] + node _T_8598 = bits(_T_8239, 17, 17) @[RegMapper.scala 178:77] + node _T_8599 = and(_T_8597, _T_8598) @[RegMapper.scala 178:66] + node _T_8600 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8601 = and(_T_8600, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8602 = bits(_T_7981, 18, 18) @[RegMapper.scala 175:77] + node _T_8603 = and(_T_8601, _T_8602) @[RegMapper.scala 175:66] + node _T_8604 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8606 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8607 = and(_T_8604, _T_8606) @[RegMapper.scala 176:46] + node _T_8608 = bits(_T_7981, 18, 18) @[RegMapper.scala 176:77] + node _T_8609 = and(_T_8607, _T_8608) @[RegMapper.scala 176:66] + node _T_8610 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8611 = and(_T_8610, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8612 = bits(_T_8239, 18, 18) @[RegMapper.scala 177:77] + node _T_8613 = and(_T_8611, _T_8612) @[RegMapper.scala 177:66] + node _T_8614 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8616 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8617 = and(_T_8614, _T_8616) @[RegMapper.scala 178:46] + node _T_8618 = bits(_T_8239, 18, 18) @[RegMapper.scala 178:77] + node _T_8619 = and(_T_8617, _T_8618) @[RegMapper.scala 178:66] + node _T_8620 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8621 = and(_T_8620, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8622 = bits(_T_7981, 19, 19) @[RegMapper.scala 175:77] + node _T_8623 = and(_T_8621, _T_8622) @[RegMapper.scala 175:66] + node _T_8624 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8626 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8627 = and(_T_8624, _T_8626) @[RegMapper.scala 176:46] + node _T_8628 = bits(_T_7981, 19, 19) @[RegMapper.scala 176:77] + node _T_8629 = and(_T_8627, _T_8628) @[RegMapper.scala 176:66] + node _T_8630 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8631 = and(_T_8630, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8632 = bits(_T_8239, 19, 19) @[RegMapper.scala 177:77] + node _T_8633 = and(_T_8631, _T_8632) @[RegMapper.scala 177:66] + node _T_8634 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8636 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8637 = and(_T_8634, _T_8636) @[RegMapper.scala 178:46] + node _T_8638 = bits(_T_8239, 19, 19) @[RegMapper.scala 178:77] + node _T_8639 = and(_T_8637, _T_8638) @[RegMapper.scala 178:66] + node _T_8640 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8641 = and(_T_8640, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8642 = bits(_T_7981, 20, 20) @[RegMapper.scala 175:77] + node _T_8643 = and(_T_8641, _T_8642) @[RegMapper.scala 175:66] + node _T_8644 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8646 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8647 = and(_T_8644, _T_8646) @[RegMapper.scala 176:46] + node _T_8648 = bits(_T_7981, 20, 20) @[RegMapper.scala 176:77] + node _T_8649 = and(_T_8647, _T_8648) @[RegMapper.scala 176:66] + node _T_8650 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8651 = and(_T_8650, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8652 = bits(_T_8239, 20, 20) @[RegMapper.scala 177:77] + node _T_8653 = and(_T_8651, _T_8652) @[RegMapper.scala 177:66] + node _T_8654 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8656 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8657 = and(_T_8654, _T_8656) @[RegMapper.scala 178:46] + node _T_8658 = bits(_T_8239, 20, 20) @[RegMapper.scala 178:77] + node _T_8659 = and(_T_8657, _T_8658) @[RegMapper.scala 178:66] + node _T_8660 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8661 = and(_T_8660, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8662 = bits(_T_7981, 21, 21) @[RegMapper.scala 175:77] + node _T_8663 = and(_T_8661, _T_8662) @[RegMapper.scala 175:66] + node _T_8664 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8666 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8667 = and(_T_8664, _T_8666) @[RegMapper.scala 176:46] + node _T_8668 = bits(_T_7981, 21, 21) @[RegMapper.scala 176:77] + node _T_8669 = and(_T_8667, _T_8668) @[RegMapper.scala 176:66] + node _T_8670 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8671 = and(_T_8670, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8672 = bits(_T_8239, 21, 21) @[RegMapper.scala 177:77] + node _T_8673 = and(_T_8671, _T_8672) @[RegMapper.scala 177:66] + node _T_8674 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8676 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8677 = and(_T_8674, _T_8676) @[RegMapper.scala 178:46] + node _T_8678 = bits(_T_8239, 21, 21) @[RegMapper.scala 178:77] + node _T_8679 = and(_T_8677, _T_8678) @[RegMapper.scala 178:66] + node _T_8680 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8681 = and(_T_8680, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8682 = bits(_T_7981, 22, 22) @[RegMapper.scala 175:77] + node _T_8683 = and(_T_8681, _T_8682) @[RegMapper.scala 175:66] + node _T_8684 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8686 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8687 = and(_T_8684, _T_8686) @[RegMapper.scala 176:46] + node _T_8688 = bits(_T_7981, 22, 22) @[RegMapper.scala 176:77] + node _T_8689 = and(_T_8687, _T_8688) @[RegMapper.scala 176:66] + node _T_8690 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8691 = and(_T_8690, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8692 = bits(_T_8239, 22, 22) @[RegMapper.scala 177:77] + node _T_8693 = and(_T_8691, _T_8692) @[RegMapper.scala 177:66] + node _T_8694 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8696 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8697 = and(_T_8694, _T_8696) @[RegMapper.scala 178:46] + node _T_8698 = bits(_T_8239, 22, 22) @[RegMapper.scala 178:77] + node _T_8699 = and(_T_8697, _T_8698) @[RegMapper.scala 178:66] + node _T_8700 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8701 = and(_T_8700, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8702 = bits(_T_7981, 23, 23) @[RegMapper.scala 175:77] + node _T_8703 = and(_T_8701, _T_8702) @[RegMapper.scala 175:66] + node _T_8704 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8706 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8707 = and(_T_8704, _T_8706) @[RegMapper.scala 176:46] + node _T_8708 = bits(_T_7981, 23, 23) @[RegMapper.scala 176:77] + node _T_8709 = and(_T_8707, _T_8708) @[RegMapper.scala 176:66] + node _T_8710 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8711 = and(_T_8710, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8712 = bits(_T_8239, 23, 23) @[RegMapper.scala 177:77] + node _T_8713 = and(_T_8711, _T_8712) @[RegMapper.scala 177:66] + node _T_8714 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8716 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8717 = and(_T_8714, _T_8716) @[RegMapper.scala 178:46] + node _T_8718 = bits(_T_8239, 23, 23) @[RegMapper.scala 178:77] + node _T_8719 = and(_T_8717, _T_8718) @[RegMapper.scala 178:66] + node _T_8720 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8721 = and(_T_8720, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8722 = bits(_T_7981, 24, 24) @[RegMapper.scala 175:77] + node _T_8723 = and(_T_8721, _T_8722) @[RegMapper.scala 175:66] + node _T_8724 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8726 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8727 = and(_T_8724, _T_8726) @[RegMapper.scala 176:46] + node _T_8728 = bits(_T_7981, 24, 24) @[RegMapper.scala 176:77] + node _T_8729 = and(_T_8727, _T_8728) @[RegMapper.scala 176:66] + node _T_8730 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8731 = and(_T_8730, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8732 = bits(_T_8239, 24, 24) @[RegMapper.scala 177:77] + node _T_8733 = and(_T_8731, _T_8732) @[RegMapper.scala 177:66] + node _T_8734 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8736 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8737 = and(_T_8734, _T_8736) @[RegMapper.scala 178:46] + node _T_8738 = bits(_T_8239, 24, 24) @[RegMapper.scala 178:77] + node _T_8739 = and(_T_8737, _T_8738) @[RegMapper.scala 178:66] + node _T_8740 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8741 = and(_T_8740, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8742 = bits(_T_7981, 25, 25) @[RegMapper.scala 175:77] + node _T_8743 = and(_T_8741, _T_8742) @[RegMapper.scala 175:66] + node _T_8744 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8746 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8747 = and(_T_8744, _T_8746) @[RegMapper.scala 176:46] + node _T_8748 = bits(_T_7981, 25, 25) @[RegMapper.scala 176:77] + node _T_8749 = and(_T_8747, _T_8748) @[RegMapper.scala 176:66] + node _T_8750 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8751 = and(_T_8750, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8752 = bits(_T_8239, 25, 25) @[RegMapper.scala 177:77] + node _T_8753 = and(_T_8751, _T_8752) @[RegMapper.scala 177:66] + node _T_8754 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8756 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8757 = and(_T_8754, _T_8756) @[RegMapper.scala 178:46] + node _T_8758 = bits(_T_8239, 25, 25) @[RegMapper.scala 178:77] + node _T_8759 = and(_T_8757, _T_8758) @[RegMapper.scala 178:66] + node _T_8760 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8761 = and(_T_8760, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8762 = bits(_T_7981, 26, 26) @[RegMapper.scala 175:77] + node _T_8763 = and(_T_8761, _T_8762) @[RegMapper.scala 175:66] + node _T_8764 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8766 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8767 = and(_T_8764, _T_8766) @[RegMapper.scala 176:46] + node _T_8768 = bits(_T_7981, 26, 26) @[RegMapper.scala 176:77] + node _T_8769 = and(_T_8767, _T_8768) @[RegMapper.scala 176:66] + node _T_8770 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8771 = and(_T_8770, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8772 = bits(_T_8239, 26, 26) @[RegMapper.scala 177:77] + node _T_8773 = and(_T_8771, _T_8772) @[RegMapper.scala 177:66] + node _T_8774 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8776 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8777 = and(_T_8774, _T_8776) @[RegMapper.scala 178:46] + node _T_8778 = bits(_T_8239, 26, 26) @[RegMapper.scala 178:77] + node _T_8779 = and(_T_8777, _T_8778) @[RegMapper.scala 178:66] + node _T_8780 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8781 = and(_T_8780, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8782 = bits(_T_7981, 27, 27) @[RegMapper.scala 175:77] + node _T_8783 = and(_T_8781, _T_8782) @[RegMapper.scala 175:66] + node _T_8784 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8786 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8787 = and(_T_8784, _T_8786) @[RegMapper.scala 176:46] + node _T_8788 = bits(_T_7981, 27, 27) @[RegMapper.scala 176:77] + node _T_8789 = and(_T_8787, _T_8788) @[RegMapper.scala 176:66] + node _T_8790 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8791 = and(_T_8790, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8792 = bits(_T_8239, 27, 27) @[RegMapper.scala 177:77] + node _T_8793 = and(_T_8791, _T_8792) @[RegMapper.scala 177:66] + node _T_8794 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8796 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8797 = and(_T_8794, _T_8796) @[RegMapper.scala 178:46] + node _T_8798 = bits(_T_8239, 27, 27) @[RegMapper.scala 178:77] + node _T_8799 = and(_T_8797, _T_8798) @[RegMapper.scala 178:66] + node _T_8800 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8801 = and(_T_8800, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8802 = bits(_T_7981, 28, 28) @[RegMapper.scala 175:77] + node _T_8803 = and(_T_8801, _T_8802) @[RegMapper.scala 175:66] + node _T_8804 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8806 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8807 = and(_T_8804, _T_8806) @[RegMapper.scala 176:46] + node _T_8808 = bits(_T_7981, 28, 28) @[RegMapper.scala 176:77] + node _T_8809 = and(_T_8807, _T_8808) @[RegMapper.scala 176:66] + node _T_8810 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8811 = and(_T_8810, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8812 = bits(_T_8239, 28, 28) @[RegMapper.scala 177:77] + node _T_8813 = and(_T_8811, _T_8812) @[RegMapper.scala 177:66] + node _T_8814 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8816 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8817 = and(_T_8814, _T_8816) @[RegMapper.scala 178:46] + node _T_8818 = bits(_T_8239, 28, 28) @[RegMapper.scala 178:77] + node _T_8819 = and(_T_8817, _T_8818) @[RegMapper.scala 178:66] + node _T_8820 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8821 = and(_T_8820, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8822 = bits(_T_7981, 29, 29) @[RegMapper.scala 175:77] + node _T_8823 = and(_T_8821, _T_8822) @[RegMapper.scala 175:66] + node _T_8824 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8826 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8827 = and(_T_8824, _T_8826) @[RegMapper.scala 176:46] + node _T_8828 = bits(_T_7981, 29, 29) @[RegMapper.scala 176:77] + node _T_8829 = and(_T_8827, _T_8828) @[RegMapper.scala 176:66] + node _T_8830 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8831 = and(_T_8830, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8832 = bits(_T_8239, 29, 29) @[RegMapper.scala 177:77] + node _T_8833 = and(_T_8831, _T_8832) @[RegMapper.scala 177:66] + node _T_8834 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8836 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8837 = and(_T_8834, _T_8836) @[RegMapper.scala 178:46] + node _T_8838 = bits(_T_8239, 29, 29) @[RegMapper.scala 178:77] + node _T_8839 = and(_T_8837, _T_8838) @[RegMapper.scala 178:66] + node _T_8840 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8841 = and(_T_8840, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8842 = bits(_T_7981, 30, 30) @[RegMapper.scala 175:77] + node _T_8843 = and(_T_8841, _T_8842) @[RegMapper.scala 175:66] + node _T_8844 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8846 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8847 = and(_T_8844, _T_8846) @[RegMapper.scala 176:46] + node _T_8848 = bits(_T_7981, 30, 30) @[RegMapper.scala 176:77] + node _T_8849 = and(_T_8847, _T_8848) @[RegMapper.scala 176:66] + node _T_8850 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8851 = and(_T_8850, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8852 = bits(_T_8239, 30, 30) @[RegMapper.scala 177:77] + node _T_8853 = and(_T_8851, _T_8852) @[RegMapper.scala 177:66] + node _T_8854 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8856 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8857 = and(_T_8854, _T_8856) @[RegMapper.scala 178:46] + node _T_8858 = bits(_T_8239, 30, 30) @[RegMapper.scala 178:77] + node _T_8859 = and(_T_8857, _T_8858) @[RegMapper.scala 178:66] + node _T_8860 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8861 = and(_T_8860, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8862 = bits(_T_7981, 31, 31) @[RegMapper.scala 175:77] + node _T_8863 = and(_T_8861, _T_8862) @[RegMapper.scala 175:66] + node _T_8864 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8866 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8867 = and(_T_8864, _T_8866) @[RegMapper.scala 176:46] + node _T_8868 = bits(_T_7981, 31, 31) @[RegMapper.scala 176:77] + node _T_8869 = and(_T_8867, _T_8868) @[RegMapper.scala 176:66] + node _T_8870 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8871 = and(_T_8870, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8872 = bits(_T_8239, 31, 31) @[RegMapper.scala 177:77] + node _T_8873 = and(_T_8871, _T_8872) @[RegMapper.scala 177:66] + node _T_8874 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8876 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8877 = and(_T_8874, _T_8876) @[RegMapper.scala 178:46] + node _T_8878 = bits(_T_8239, 31, 31) @[RegMapper.scala 178:77] + node _T_8879 = and(_T_8877, _T_8878) @[RegMapper.scala 178:66] + node _T_8880 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8881 = and(_T_8880, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8882 = bits(_T_7981, 32, 32) @[RegMapper.scala 175:77] + node _T_8883 = and(_T_8881, _T_8882) @[RegMapper.scala 175:66] + node _T_8884 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8886 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8887 = and(_T_8884, _T_8886) @[RegMapper.scala 176:46] + node _T_8888 = bits(_T_7981, 32, 32) @[RegMapper.scala 176:77] + node _T_8889 = and(_T_8887, _T_8888) @[RegMapper.scala 176:66] + node _T_8890 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8891 = and(_T_8890, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8892 = bits(_T_8239, 32, 32) @[RegMapper.scala 177:77] + node _T_8893 = and(_T_8891, _T_8892) @[RegMapper.scala 177:66] + node _T_8894 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8896 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8897 = and(_T_8894, _T_8896) @[RegMapper.scala 178:46] + node _T_8898 = bits(_T_8239, 32, 32) @[RegMapper.scala 178:77] + node _T_8899 = and(_T_8897, _T_8898) @[RegMapper.scala 178:66] + node _T_8900 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8901 = and(_T_8900, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8902 = bits(_T_7981, 33, 33) @[RegMapper.scala 175:77] + node _T_8903 = and(_T_8901, _T_8902) @[RegMapper.scala 175:66] + node _T_8904 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8906 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8907 = and(_T_8904, _T_8906) @[RegMapper.scala 176:46] + node _T_8908 = bits(_T_7981, 33, 33) @[RegMapper.scala 176:77] + node _T_8909 = and(_T_8907, _T_8908) @[RegMapper.scala 176:66] + node _T_8910 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8911 = and(_T_8910, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8912 = bits(_T_8239, 33, 33) @[RegMapper.scala 177:77] + node _T_8913 = and(_T_8911, _T_8912) @[RegMapper.scala 177:66] + node _T_8914 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8916 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8917 = and(_T_8914, _T_8916) @[RegMapper.scala 178:46] + node _T_8918 = bits(_T_8239, 33, 33) @[RegMapper.scala 178:77] + node _T_8919 = and(_T_8917, _T_8918) @[RegMapper.scala 178:66] + node _T_8920 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8921 = and(_T_8920, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8922 = bits(_T_7981, 34, 34) @[RegMapper.scala 175:77] + node _T_8923 = and(_T_8921, _T_8922) @[RegMapper.scala 175:66] + node _T_8924 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8926 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8927 = and(_T_8924, _T_8926) @[RegMapper.scala 176:46] + node _T_8928 = bits(_T_7981, 34, 34) @[RegMapper.scala 176:77] + node _T_8929 = and(_T_8927, _T_8928) @[RegMapper.scala 176:66] + node _T_8930 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8931 = and(_T_8930, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8932 = bits(_T_8239, 34, 34) @[RegMapper.scala 177:77] + node _T_8933 = and(_T_8931, _T_8932) @[RegMapper.scala 177:66] + node _T_8934 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8936 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8937 = and(_T_8934, _T_8936) @[RegMapper.scala 178:46] + node _T_8938 = bits(_T_8239, 34, 34) @[RegMapper.scala 178:77] + node _T_8939 = and(_T_8937, _T_8938) @[RegMapper.scala 178:66] + node _T_8940 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8941 = and(_T_8940, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8942 = bits(_T_7981, 35, 35) @[RegMapper.scala 175:77] + node _T_8943 = and(_T_8941, _T_8942) @[RegMapper.scala 175:66] + node _T_8944 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8946 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8947 = and(_T_8944, _T_8946) @[RegMapper.scala 176:46] + node _T_8948 = bits(_T_7981, 35, 35) @[RegMapper.scala 176:77] + node _T_8949 = and(_T_8947, _T_8948) @[RegMapper.scala 176:66] + node _T_8950 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8951 = and(_T_8950, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8952 = bits(_T_8239, 35, 35) @[RegMapper.scala 177:77] + node _T_8953 = and(_T_8951, _T_8952) @[RegMapper.scala 177:66] + node _T_8954 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8956 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8957 = and(_T_8954, _T_8956) @[RegMapper.scala 178:46] + node _T_8958 = bits(_T_8239, 35, 35) @[RegMapper.scala 178:77] + node _T_8959 = and(_T_8957, _T_8958) @[RegMapper.scala 178:66] + node _T_8960 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8961 = and(_T_8960, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8962 = bits(_T_7981, 36, 36) @[RegMapper.scala 175:77] + node _T_8963 = and(_T_8961, _T_8962) @[RegMapper.scala 175:66] + node _T_8964 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8966 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8967 = and(_T_8964, _T_8966) @[RegMapper.scala 176:46] + node _T_8968 = bits(_T_7981, 36, 36) @[RegMapper.scala 176:77] + node _T_8969 = and(_T_8967, _T_8968) @[RegMapper.scala 176:66] + node _T_8970 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8971 = and(_T_8970, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8972 = bits(_T_8239, 36, 36) @[RegMapper.scala 177:77] + node _T_8973 = and(_T_8971, _T_8972) @[RegMapper.scala 177:66] + node _T_8974 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8976 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8977 = and(_T_8974, _T_8976) @[RegMapper.scala 178:46] + node _T_8978 = bits(_T_8239, 36, 36) @[RegMapper.scala 178:77] + node _T_8979 = and(_T_8977, _T_8978) @[RegMapper.scala 178:66] + node _T_8980 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_8981 = and(_T_8980, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_8982 = bits(_T_7981, 37, 37) @[RegMapper.scala 175:77] + node _T_8983 = and(_T_8981, _T_8982) @[RegMapper.scala 175:66] + node _T_8984 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_8986 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_8987 = and(_T_8984, _T_8986) @[RegMapper.scala 176:46] + node _T_8988 = bits(_T_7981, 37, 37) @[RegMapper.scala 176:77] + node _T_8989 = and(_T_8987, _T_8988) @[RegMapper.scala 176:66] + node _T_8990 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_8991 = and(_T_8990, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_8992 = bits(_T_8239, 37, 37) @[RegMapper.scala 177:77] + node _T_8993 = and(_T_8991, _T_8992) @[RegMapper.scala 177:66] + node _T_8994 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_8996 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_8997 = and(_T_8994, _T_8996) @[RegMapper.scala 178:46] + node _T_8998 = bits(_T_8239, 37, 37) @[RegMapper.scala 178:77] + node _T_8999 = and(_T_8997, _T_8998) @[RegMapper.scala 178:66] + node _T_9000 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9001 = and(_T_9000, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9002 = bits(_T_7981, 38, 38) @[RegMapper.scala 175:77] + node _T_9003 = and(_T_9001, _T_9002) @[RegMapper.scala 175:66] + node _T_9004 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9006 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9007 = and(_T_9004, _T_9006) @[RegMapper.scala 176:46] + node _T_9008 = bits(_T_7981, 38, 38) @[RegMapper.scala 176:77] + node _T_9009 = and(_T_9007, _T_9008) @[RegMapper.scala 176:66] + node _T_9010 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9011 = and(_T_9010, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9012 = bits(_T_8239, 38, 38) @[RegMapper.scala 177:77] + node _T_9013 = and(_T_9011, _T_9012) @[RegMapper.scala 177:66] + node _T_9014 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9016 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9017 = and(_T_9014, _T_9016) @[RegMapper.scala 178:46] + node _T_9018 = bits(_T_8239, 38, 38) @[RegMapper.scala 178:77] + node _T_9019 = and(_T_9017, _T_9018) @[RegMapper.scala 178:66] + node _T_9020 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9021 = and(_T_9020, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9022 = bits(_T_7981, 39, 39) @[RegMapper.scala 175:77] + node _T_9023 = and(_T_9021, _T_9022) @[RegMapper.scala 175:66] + node _T_9024 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9026 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9027 = and(_T_9024, _T_9026) @[RegMapper.scala 176:46] + node _T_9028 = bits(_T_7981, 39, 39) @[RegMapper.scala 176:77] + node _T_9029 = and(_T_9027, _T_9028) @[RegMapper.scala 176:66] + node _T_9030 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9031 = and(_T_9030, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9032 = bits(_T_8239, 39, 39) @[RegMapper.scala 177:77] + node _T_9033 = and(_T_9031, _T_9032) @[RegMapper.scala 177:66] + node _T_9034 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9036 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9037 = and(_T_9034, _T_9036) @[RegMapper.scala 178:46] + node _T_9038 = bits(_T_8239, 39, 39) @[RegMapper.scala 178:77] + node _T_9039 = and(_T_9037, _T_9038) @[RegMapper.scala 178:66] + node _T_9040 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9041 = and(_T_9040, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9042 = bits(_T_7981, 40, 40) @[RegMapper.scala 175:77] + node _T_9043 = and(_T_9041, _T_9042) @[RegMapper.scala 175:66] + node _T_9044 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9046 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9047 = and(_T_9044, _T_9046) @[RegMapper.scala 176:46] + node _T_9048 = bits(_T_7981, 40, 40) @[RegMapper.scala 176:77] + node _T_9049 = and(_T_9047, _T_9048) @[RegMapper.scala 176:66] + node _T_9050 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9051 = and(_T_9050, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9052 = bits(_T_8239, 40, 40) @[RegMapper.scala 177:77] + node _T_9053 = and(_T_9051, _T_9052) @[RegMapper.scala 177:66] + node _T_9054 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9056 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9057 = and(_T_9054, _T_9056) @[RegMapper.scala 178:46] + node _T_9058 = bits(_T_8239, 40, 40) @[RegMapper.scala 178:77] + node _T_9059 = and(_T_9057, _T_9058) @[RegMapper.scala 178:66] + node _T_9060 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9061 = and(_T_9060, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9062 = bits(_T_7981, 41, 41) @[RegMapper.scala 175:77] + node _T_9063 = and(_T_9061, _T_9062) @[RegMapper.scala 175:66] + node _T_9064 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9066 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9067 = and(_T_9064, _T_9066) @[RegMapper.scala 176:46] + node _T_9068 = bits(_T_7981, 41, 41) @[RegMapper.scala 176:77] + node _T_9069 = and(_T_9067, _T_9068) @[RegMapper.scala 176:66] + node _T_9070 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9071 = and(_T_9070, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9072 = bits(_T_8239, 41, 41) @[RegMapper.scala 177:77] + node _T_9073 = and(_T_9071, _T_9072) @[RegMapper.scala 177:66] + node _T_9074 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9076 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9077 = and(_T_9074, _T_9076) @[RegMapper.scala 178:46] + node _T_9078 = bits(_T_8239, 41, 41) @[RegMapper.scala 178:77] + node _T_9079 = and(_T_9077, _T_9078) @[RegMapper.scala 178:66] + node _T_9080 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9081 = and(_T_9080, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9082 = bits(_T_7981, 42, 42) @[RegMapper.scala 175:77] + node _T_9083 = and(_T_9081, _T_9082) @[RegMapper.scala 175:66] + node _T_9084 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9086 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9087 = and(_T_9084, _T_9086) @[RegMapper.scala 176:46] + node _T_9088 = bits(_T_7981, 42, 42) @[RegMapper.scala 176:77] + node _T_9089 = and(_T_9087, _T_9088) @[RegMapper.scala 176:66] + node _T_9090 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9091 = and(_T_9090, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9092 = bits(_T_8239, 42, 42) @[RegMapper.scala 177:77] + node _T_9093 = and(_T_9091, _T_9092) @[RegMapper.scala 177:66] + node _T_9094 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9096 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9097 = and(_T_9094, _T_9096) @[RegMapper.scala 178:46] + node _T_9098 = bits(_T_8239, 42, 42) @[RegMapper.scala 178:77] + node _T_9099 = and(_T_9097, _T_9098) @[RegMapper.scala 178:66] + node _T_9100 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9101 = and(_T_9100, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9102 = bits(_T_7981, 43, 43) @[RegMapper.scala 175:77] + node _T_9103 = and(_T_9101, _T_9102) @[RegMapper.scala 175:66] + node _T_9104 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9106 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9107 = and(_T_9104, _T_9106) @[RegMapper.scala 176:46] + node _T_9108 = bits(_T_7981, 43, 43) @[RegMapper.scala 176:77] + node _T_9109 = and(_T_9107, _T_9108) @[RegMapper.scala 176:66] + node _T_9110 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9111 = and(_T_9110, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9112 = bits(_T_8239, 43, 43) @[RegMapper.scala 177:77] + node _T_9113 = and(_T_9111, _T_9112) @[RegMapper.scala 177:66] + node _T_9114 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9116 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9117 = and(_T_9114, _T_9116) @[RegMapper.scala 178:46] + node _T_9118 = bits(_T_8239, 43, 43) @[RegMapper.scala 178:77] + node _T_9119 = and(_T_9117, _T_9118) @[RegMapper.scala 178:66] + node _T_9120 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9121 = and(_T_9120, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9122 = bits(_T_7981, 44, 44) @[RegMapper.scala 175:77] + node _T_9123 = and(_T_9121, _T_9122) @[RegMapper.scala 175:66] + node _T_9124 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9126 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9127 = and(_T_9124, _T_9126) @[RegMapper.scala 176:46] + node _T_9128 = bits(_T_7981, 44, 44) @[RegMapper.scala 176:77] + node _T_9129 = and(_T_9127, _T_9128) @[RegMapper.scala 176:66] + node _T_9130 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9131 = and(_T_9130, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9132 = bits(_T_8239, 44, 44) @[RegMapper.scala 177:77] + node _T_9133 = and(_T_9131, _T_9132) @[RegMapper.scala 177:66] + node _T_9134 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9136 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9137 = and(_T_9134, _T_9136) @[RegMapper.scala 178:46] + node _T_9138 = bits(_T_8239, 44, 44) @[RegMapper.scala 178:77] + node _T_9139 = and(_T_9137, _T_9138) @[RegMapper.scala 178:66] + node _T_9140 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9141 = and(_T_9140, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9142 = bits(_T_7981, 45, 45) @[RegMapper.scala 175:77] + node _T_9143 = and(_T_9141, _T_9142) @[RegMapper.scala 175:66] + node _T_9144 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9146 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9147 = and(_T_9144, _T_9146) @[RegMapper.scala 176:46] + node _T_9148 = bits(_T_7981, 45, 45) @[RegMapper.scala 176:77] + node _T_9149 = and(_T_9147, _T_9148) @[RegMapper.scala 176:66] + node _T_9150 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9151 = and(_T_9150, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9152 = bits(_T_8239, 45, 45) @[RegMapper.scala 177:77] + node _T_9153 = and(_T_9151, _T_9152) @[RegMapper.scala 177:66] + node _T_9154 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9156 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9157 = and(_T_9154, _T_9156) @[RegMapper.scala 178:46] + node _T_9158 = bits(_T_8239, 45, 45) @[RegMapper.scala 178:77] + node _T_9159 = and(_T_9157, _T_9158) @[RegMapper.scala 178:66] + node _T_9160 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9161 = and(_T_9160, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9162 = bits(_T_7981, 46, 46) @[RegMapper.scala 175:77] + node _T_9163 = and(_T_9161, _T_9162) @[RegMapper.scala 175:66] + node _T_9164 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9166 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9167 = and(_T_9164, _T_9166) @[RegMapper.scala 176:46] + node _T_9168 = bits(_T_7981, 46, 46) @[RegMapper.scala 176:77] + node _T_9169 = and(_T_9167, _T_9168) @[RegMapper.scala 176:66] + node _T_9170 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9171 = and(_T_9170, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9172 = bits(_T_8239, 46, 46) @[RegMapper.scala 177:77] + node _T_9173 = and(_T_9171, _T_9172) @[RegMapper.scala 177:66] + node _T_9174 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9176 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9177 = and(_T_9174, _T_9176) @[RegMapper.scala 178:46] + node _T_9178 = bits(_T_8239, 46, 46) @[RegMapper.scala 178:77] + node _T_9179 = and(_T_9177, _T_9178) @[RegMapper.scala 178:66] + node _T_9180 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9181 = and(_T_9180, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9182 = bits(_T_7981, 47, 47) @[RegMapper.scala 175:77] + node _T_9183 = and(_T_9181, _T_9182) @[RegMapper.scala 175:66] + node _T_9184 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9186 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9187 = and(_T_9184, _T_9186) @[RegMapper.scala 176:46] + node _T_9188 = bits(_T_7981, 47, 47) @[RegMapper.scala 176:77] + node _T_9189 = and(_T_9187, _T_9188) @[RegMapper.scala 176:66] + node _T_9190 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9191 = and(_T_9190, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9192 = bits(_T_8239, 47, 47) @[RegMapper.scala 177:77] + node _T_9193 = and(_T_9191, _T_9192) @[RegMapper.scala 177:66] + node _T_9194 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9196 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9197 = and(_T_9194, _T_9196) @[RegMapper.scala 178:46] + node _T_9198 = bits(_T_8239, 47, 47) @[RegMapper.scala 178:77] + node _T_9199 = and(_T_9197, _T_9198) @[RegMapper.scala 178:66] + node _T_9200 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9201 = and(_T_9200, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9202 = bits(_T_7981, 48, 48) @[RegMapper.scala 175:77] + node _T_9203 = and(_T_9201, _T_9202) @[RegMapper.scala 175:66] + node _T_9204 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9206 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9207 = and(_T_9204, _T_9206) @[RegMapper.scala 176:46] + node _T_9208 = bits(_T_7981, 48, 48) @[RegMapper.scala 176:77] + node _T_9209 = and(_T_9207, _T_9208) @[RegMapper.scala 176:66] + node _T_9210 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9211 = and(_T_9210, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9212 = bits(_T_8239, 48, 48) @[RegMapper.scala 177:77] + node _T_9213 = and(_T_9211, _T_9212) @[RegMapper.scala 177:66] + node _T_9214 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9216 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9217 = and(_T_9214, _T_9216) @[RegMapper.scala 178:46] + node _T_9218 = bits(_T_8239, 48, 48) @[RegMapper.scala 178:77] + node _T_9219 = and(_T_9217, _T_9218) @[RegMapper.scala 178:66] + node _T_9220 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9221 = and(_T_9220, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9222 = bits(_T_7981, 49, 49) @[RegMapper.scala 175:77] + node _T_9223 = and(_T_9221, _T_9222) @[RegMapper.scala 175:66] + node _T_9224 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9226 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9227 = and(_T_9224, _T_9226) @[RegMapper.scala 176:46] + node _T_9228 = bits(_T_7981, 49, 49) @[RegMapper.scala 176:77] + node _T_9229 = and(_T_9227, _T_9228) @[RegMapper.scala 176:66] + node _T_9230 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9231 = and(_T_9230, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9232 = bits(_T_8239, 49, 49) @[RegMapper.scala 177:77] + node _T_9233 = and(_T_9231, _T_9232) @[RegMapper.scala 177:66] + node _T_9234 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9236 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9237 = and(_T_9234, _T_9236) @[RegMapper.scala 178:46] + node _T_9238 = bits(_T_8239, 49, 49) @[RegMapper.scala 178:77] + node _T_9239 = and(_T_9237, _T_9238) @[RegMapper.scala 178:66] + node _T_9240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9241 = and(_T_9240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9242 = bits(_T_7981, 50, 50) @[RegMapper.scala 175:77] + node _T_9243 = and(_T_9241, _T_9242) @[RegMapper.scala 175:66] + node _T_9244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9247 = and(_T_9244, _T_9246) @[RegMapper.scala 176:46] + node _T_9248 = bits(_T_7981, 50, 50) @[RegMapper.scala 176:77] + node _T_9249 = and(_T_9247, _T_9248) @[RegMapper.scala 176:66] + node _T_9250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9251 = and(_T_9250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9252 = bits(_T_8239, 50, 50) @[RegMapper.scala 177:77] + node _T_9253 = and(_T_9251, _T_9252) @[RegMapper.scala 177:66] + node _T_9254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9257 = and(_T_9254, _T_9256) @[RegMapper.scala 178:46] + node _T_9258 = bits(_T_8239, 50, 50) @[RegMapper.scala 178:77] + node _T_9259 = and(_T_9257, _T_9258) @[RegMapper.scala 178:66] + node _T_9260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9261 = and(_T_9260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9262 = bits(_T_7981, 51, 51) @[RegMapper.scala 175:77] + node _T_9263 = and(_T_9261, _T_9262) @[RegMapper.scala 175:66] + node _T_9264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9267 = and(_T_9264, _T_9266) @[RegMapper.scala 176:46] + node _T_9268 = bits(_T_7981, 51, 51) @[RegMapper.scala 176:77] + node _T_9269 = and(_T_9267, _T_9268) @[RegMapper.scala 176:66] + node _T_9270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9271 = and(_T_9270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9272 = bits(_T_8239, 51, 51) @[RegMapper.scala 177:77] + node _T_9273 = and(_T_9271, _T_9272) @[RegMapper.scala 177:66] + node _T_9274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9277 = and(_T_9274, _T_9276) @[RegMapper.scala 178:46] + node _T_9278 = bits(_T_8239, 51, 51) @[RegMapper.scala 178:77] + node _T_9279 = and(_T_9277, _T_9278) @[RegMapper.scala 178:66] + node _T_9280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9281 = and(_T_9280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9282 = bits(_T_7981, 52, 52) @[RegMapper.scala 175:77] + node _T_9283 = and(_T_9281, _T_9282) @[RegMapper.scala 175:66] + node _T_9284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9287 = and(_T_9284, _T_9286) @[RegMapper.scala 176:46] + node _T_9288 = bits(_T_7981, 52, 52) @[RegMapper.scala 176:77] + node _T_9289 = and(_T_9287, _T_9288) @[RegMapper.scala 176:66] + node _T_9290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9291 = and(_T_9290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9292 = bits(_T_8239, 52, 52) @[RegMapper.scala 177:77] + node _T_9293 = and(_T_9291, _T_9292) @[RegMapper.scala 177:66] + node _T_9294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9297 = and(_T_9294, _T_9296) @[RegMapper.scala 178:46] + node _T_9298 = bits(_T_8239, 52, 52) @[RegMapper.scala 178:77] + node _T_9299 = and(_T_9297, _T_9298) @[RegMapper.scala 178:66] + node _T_9300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9301 = and(_T_9300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9302 = bits(_T_7981, 53, 53) @[RegMapper.scala 175:77] + node _T_9303 = and(_T_9301, _T_9302) @[RegMapper.scala 175:66] + node _T_9304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9307 = and(_T_9304, _T_9306) @[RegMapper.scala 176:46] + node _T_9308 = bits(_T_7981, 53, 53) @[RegMapper.scala 176:77] + node _T_9309 = and(_T_9307, _T_9308) @[RegMapper.scala 176:66] + node _T_9310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9311 = and(_T_9310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9312 = bits(_T_8239, 53, 53) @[RegMapper.scala 177:77] + node _T_9313 = and(_T_9311, _T_9312) @[RegMapper.scala 177:66] + node _T_9314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9317 = and(_T_9314, _T_9316) @[RegMapper.scala 178:46] + node _T_9318 = bits(_T_8239, 53, 53) @[RegMapper.scala 178:77] + node _T_9319 = and(_T_9317, _T_9318) @[RegMapper.scala 178:66] + node _T_9320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9321 = and(_T_9320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9322 = bits(_T_7981, 54, 54) @[RegMapper.scala 175:77] + node _T_9323 = and(_T_9321, _T_9322) @[RegMapper.scala 175:66] + node _T_9324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9327 = and(_T_9324, _T_9326) @[RegMapper.scala 176:46] + node _T_9328 = bits(_T_7981, 54, 54) @[RegMapper.scala 176:77] + node _T_9329 = and(_T_9327, _T_9328) @[RegMapper.scala 176:66] + node _T_9330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9331 = and(_T_9330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9332 = bits(_T_8239, 54, 54) @[RegMapper.scala 177:77] + node _T_9333 = and(_T_9331, _T_9332) @[RegMapper.scala 177:66] + node _T_9334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9337 = and(_T_9334, _T_9336) @[RegMapper.scala 178:46] + node _T_9338 = bits(_T_8239, 54, 54) @[RegMapper.scala 178:77] + node _T_9339 = and(_T_9337, _T_9338) @[RegMapper.scala 178:66] + node _T_9340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9341 = and(_T_9340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9342 = bits(_T_7981, 55, 55) @[RegMapper.scala 175:77] + node _T_9343 = and(_T_9341, _T_9342) @[RegMapper.scala 175:66] + node _T_9344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9347 = and(_T_9344, _T_9346) @[RegMapper.scala 176:46] + node _T_9348 = bits(_T_7981, 55, 55) @[RegMapper.scala 176:77] + node _T_9349 = and(_T_9347, _T_9348) @[RegMapper.scala 176:66] + node _T_9350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9351 = and(_T_9350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9352 = bits(_T_8239, 55, 55) @[RegMapper.scala 177:77] + node _T_9353 = and(_T_9351, _T_9352) @[RegMapper.scala 177:66] + node _T_9354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9357 = and(_T_9354, _T_9356) @[RegMapper.scala 178:46] + node _T_9358 = bits(_T_8239, 55, 55) @[RegMapper.scala 178:77] + node _T_9359 = and(_T_9357, _T_9358) @[RegMapper.scala 178:66] + node _T_9360 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9361 = and(_T_9360, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9362 = bits(_T_7981, 56, 56) @[RegMapper.scala 175:77] + node _T_9363 = and(_T_9361, _T_9362) @[RegMapper.scala 175:66] + node _T_9364 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9366 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9367 = and(_T_9364, _T_9366) @[RegMapper.scala 176:46] + node _T_9368 = bits(_T_7981, 56, 56) @[RegMapper.scala 176:77] + node _T_9369 = and(_T_9367, _T_9368) @[RegMapper.scala 176:66] + node _T_9370 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9371 = and(_T_9370, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9372 = bits(_T_8239, 56, 56) @[RegMapper.scala 177:77] + node _T_9373 = and(_T_9371, _T_9372) @[RegMapper.scala 177:66] + node _T_9374 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9376 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9377 = and(_T_9374, _T_9376) @[RegMapper.scala 178:46] + node _T_9378 = bits(_T_8239, 56, 56) @[RegMapper.scala 178:77] + node _T_9379 = and(_T_9377, _T_9378) @[RegMapper.scala 178:66] + node _T_9380 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9381 = and(_T_9380, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9382 = bits(_T_7981, 57, 57) @[RegMapper.scala 175:77] + node _T_9383 = and(_T_9381, _T_9382) @[RegMapper.scala 175:66] + node _T_9384 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9386 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9387 = and(_T_9384, _T_9386) @[RegMapper.scala 176:46] + node _T_9388 = bits(_T_7981, 57, 57) @[RegMapper.scala 176:77] + node _T_9389 = and(_T_9387, _T_9388) @[RegMapper.scala 176:66] + node _T_9390 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9391 = and(_T_9390, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9392 = bits(_T_8239, 57, 57) @[RegMapper.scala 177:77] + node _T_9393 = and(_T_9391, _T_9392) @[RegMapper.scala 177:66] + node _T_9394 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9396 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9397 = and(_T_9394, _T_9396) @[RegMapper.scala 178:46] + node _T_9398 = bits(_T_8239, 57, 57) @[RegMapper.scala 178:77] + node _T_9399 = and(_T_9397, _T_9398) @[RegMapper.scala 178:66] + node _T_9400 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9401 = and(_T_9400, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9402 = bits(_T_7981, 58, 58) @[RegMapper.scala 175:77] + node _T_9403 = and(_T_9401, _T_9402) @[RegMapper.scala 175:66] + node _T_9404 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9406 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9407 = and(_T_9404, _T_9406) @[RegMapper.scala 176:46] + node _T_9408 = bits(_T_7981, 58, 58) @[RegMapper.scala 176:77] + node _T_9409 = and(_T_9407, _T_9408) @[RegMapper.scala 176:66] + node _T_9410 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9411 = and(_T_9410, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9412 = bits(_T_8239, 58, 58) @[RegMapper.scala 177:77] + node _T_9413 = and(_T_9411, _T_9412) @[RegMapper.scala 177:66] + node _T_9414 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9416 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9417 = and(_T_9414, _T_9416) @[RegMapper.scala 178:46] + node _T_9418 = bits(_T_8239, 58, 58) @[RegMapper.scala 178:77] + node _T_9419 = and(_T_9417, _T_9418) @[RegMapper.scala 178:66] + node _T_9420 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9421 = and(_T_9420, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9422 = bits(_T_7981, 59, 59) @[RegMapper.scala 175:77] + node _T_9423 = and(_T_9421, _T_9422) @[RegMapper.scala 175:66] + node _T_9424 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9426 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9427 = and(_T_9424, _T_9426) @[RegMapper.scala 176:46] + node _T_9428 = bits(_T_7981, 59, 59) @[RegMapper.scala 176:77] + node _T_9429 = and(_T_9427, _T_9428) @[RegMapper.scala 176:66] + node _T_9430 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9431 = and(_T_9430, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9432 = bits(_T_8239, 59, 59) @[RegMapper.scala 177:77] + node _T_9433 = and(_T_9431, _T_9432) @[RegMapper.scala 177:66] + node _T_9434 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9436 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9437 = and(_T_9434, _T_9436) @[RegMapper.scala 178:46] + node _T_9438 = bits(_T_8239, 59, 59) @[RegMapper.scala 178:77] + node _T_9439 = and(_T_9437, _T_9438) @[RegMapper.scala 178:66] + node _T_9440 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9441 = and(_T_9440, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9442 = bits(_T_7981, 60, 60) @[RegMapper.scala 175:77] + node _T_9443 = and(_T_9441, _T_9442) @[RegMapper.scala 175:66] + node _T_9444 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9446 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9447 = and(_T_9444, _T_9446) @[RegMapper.scala 176:46] + node _T_9448 = bits(_T_7981, 60, 60) @[RegMapper.scala 176:77] + node _T_9449 = and(_T_9447, _T_9448) @[RegMapper.scala 176:66] + node _T_9450 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9451 = and(_T_9450, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9452 = bits(_T_8239, 60, 60) @[RegMapper.scala 177:77] + node _T_9453 = and(_T_9451, _T_9452) @[RegMapper.scala 177:66] + node _T_9454 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9456 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9457 = and(_T_9454, _T_9456) @[RegMapper.scala 178:46] + node _T_9458 = bits(_T_8239, 60, 60) @[RegMapper.scala 178:77] + node _T_9459 = and(_T_9457, _T_9458) @[RegMapper.scala 178:66] + node _T_9460 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9461 = and(_T_9460, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9462 = bits(_T_7981, 61, 61) @[RegMapper.scala 175:77] + node _T_9463 = and(_T_9461, _T_9462) @[RegMapper.scala 175:66] + node _T_9464 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9466 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9467 = and(_T_9464, _T_9466) @[RegMapper.scala 176:46] + node _T_9468 = bits(_T_7981, 61, 61) @[RegMapper.scala 176:77] + node _T_9469 = and(_T_9467, _T_9468) @[RegMapper.scala 176:66] + node _T_9470 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9471 = and(_T_9470, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9472 = bits(_T_8239, 61, 61) @[RegMapper.scala 177:77] + node _T_9473 = and(_T_9471, _T_9472) @[RegMapper.scala 177:66] + node _T_9474 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9476 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9477 = and(_T_9474, _T_9476) @[RegMapper.scala 178:46] + node _T_9478 = bits(_T_8239, 61, 61) @[RegMapper.scala 178:77] + node _T_9479 = and(_T_9477, _T_9478) @[RegMapper.scala 178:66] + node _T_9480 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9481 = and(_T_9480, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9482 = bits(_T_7981, 62, 62) @[RegMapper.scala 175:77] + node _T_9483 = and(_T_9481, _T_9482) @[RegMapper.scala 175:66] + node _T_9484 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9486 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9487 = and(_T_9484, _T_9486) @[RegMapper.scala 176:46] + node _T_9488 = bits(_T_7981, 62, 62) @[RegMapper.scala 176:77] + node _T_9489 = and(_T_9487, _T_9488) @[RegMapper.scala 176:66] + node _T_9490 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9491 = and(_T_9490, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9492 = bits(_T_8239, 62, 62) @[RegMapper.scala 177:77] + node _T_9493 = and(_T_9491, _T_9492) @[RegMapper.scala 177:66] + node _T_9494 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9496 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9497 = and(_T_9494, _T_9496) @[RegMapper.scala 178:46] + node _T_9498 = bits(_T_8239, 62, 62) @[RegMapper.scala 178:77] + node _T_9499 = and(_T_9497, _T_9498) @[RegMapper.scala 178:66] + node _T_9500 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9501 = and(_T_9500, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9502 = bits(_T_7981, 63, 63) @[RegMapper.scala 175:77] + node _T_9503 = and(_T_9501, _T_9502) @[RegMapper.scala 175:66] + node _T_9504 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9506 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9507 = and(_T_9504, _T_9506) @[RegMapper.scala 176:46] + node _T_9508 = bits(_T_7981, 63, 63) @[RegMapper.scala 176:77] + node _T_9509 = and(_T_9507, _T_9508) @[RegMapper.scala 176:66] + node _T_9510 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9511 = and(_T_9510, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9512 = bits(_T_8239, 63, 63) @[RegMapper.scala 177:77] + node _T_9513 = and(_T_9511, _T_9512) @[RegMapper.scala 177:66] + node _T_9514 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9516 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9517 = and(_T_9514, _T_9516) @[RegMapper.scala 178:46] + node _T_9518 = bits(_T_8239, 63, 63) @[RegMapper.scala 178:77] + node _T_9519 = and(_T_9517, _T_9518) @[RegMapper.scala 178:66] + node _T_9520 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9521 = and(_T_9520, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9522 = bits(_T_7981, 64, 64) @[RegMapper.scala 175:77] + node _T_9523 = and(_T_9521, _T_9522) @[RegMapper.scala 175:66] + node _T_9524 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9526 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9527 = and(_T_9524, _T_9526) @[RegMapper.scala 176:46] + node _T_9528 = bits(_T_7981, 64, 64) @[RegMapper.scala 176:77] + node _T_9529 = and(_T_9527, _T_9528) @[RegMapper.scala 176:66] + node _T_9530 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9531 = and(_T_9530, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9532 = bits(_T_8239, 64, 64) @[RegMapper.scala 177:77] + node _T_9533 = and(_T_9531, _T_9532) @[RegMapper.scala 177:66] + node _T_9534 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9536 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9537 = and(_T_9534, _T_9536) @[RegMapper.scala 178:46] + node _T_9538 = bits(_T_8239, 64, 64) @[RegMapper.scala 178:77] + node _T_9539 = and(_T_9537, _T_9538) @[RegMapper.scala 178:66] + node _T_9540 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9541 = and(_T_9540, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9542 = bits(_T_7981, 65, 65) @[RegMapper.scala 175:77] + node _T_9543 = and(_T_9541, _T_9542) @[RegMapper.scala 175:66] + node _T_9544 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9546 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9547 = and(_T_9544, _T_9546) @[RegMapper.scala 176:46] + node _T_9548 = bits(_T_7981, 65, 65) @[RegMapper.scala 176:77] + node _T_9549 = and(_T_9547, _T_9548) @[RegMapper.scala 176:66] + node _T_9550 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9551 = and(_T_9550, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9552 = bits(_T_8239, 65, 65) @[RegMapper.scala 177:77] + node _T_9553 = and(_T_9551, _T_9552) @[RegMapper.scala 177:66] + node _T_9554 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9556 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9557 = and(_T_9554, _T_9556) @[RegMapper.scala 178:46] + node _T_9558 = bits(_T_8239, 65, 65) @[RegMapper.scala 178:77] + node _T_9559 = and(_T_9557, _T_9558) @[RegMapper.scala 178:66] + node _T_9560 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9561 = and(_T_9560, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9562 = bits(_T_7981, 66, 66) @[RegMapper.scala 175:77] + node _T_9563 = and(_T_9561, _T_9562) @[RegMapper.scala 175:66] + node _T_9564 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9566 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9567 = and(_T_9564, _T_9566) @[RegMapper.scala 176:46] + node _T_9568 = bits(_T_7981, 66, 66) @[RegMapper.scala 176:77] + node _T_9569 = and(_T_9567, _T_9568) @[RegMapper.scala 176:66] + node _T_9570 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9571 = and(_T_9570, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9572 = bits(_T_8239, 66, 66) @[RegMapper.scala 177:77] + node _T_9573 = and(_T_9571, _T_9572) @[RegMapper.scala 177:66] + node _T_9574 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9576 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9577 = and(_T_9574, _T_9576) @[RegMapper.scala 178:46] + node _T_9578 = bits(_T_8239, 66, 66) @[RegMapper.scala 178:77] + node _T_9579 = and(_T_9577, _T_9578) @[RegMapper.scala 178:66] + node _T_9580 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9581 = and(_T_9580, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9582 = bits(_T_7981, 67, 67) @[RegMapper.scala 175:77] + node _T_9583 = and(_T_9581, _T_9582) @[RegMapper.scala 175:66] + node _T_9584 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9586 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9587 = and(_T_9584, _T_9586) @[RegMapper.scala 176:46] + node _T_9588 = bits(_T_7981, 67, 67) @[RegMapper.scala 176:77] + node _T_9589 = and(_T_9587, _T_9588) @[RegMapper.scala 176:66] + node _T_9590 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9591 = and(_T_9590, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9592 = bits(_T_8239, 67, 67) @[RegMapper.scala 177:77] + node _T_9593 = and(_T_9591, _T_9592) @[RegMapper.scala 177:66] + node _T_9594 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9596 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9597 = and(_T_9594, _T_9596) @[RegMapper.scala 178:46] + node _T_9598 = bits(_T_8239, 67, 67) @[RegMapper.scala 178:77] + node _T_9599 = and(_T_9597, _T_9598) @[RegMapper.scala 178:66] + node _T_9600 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9601 = and(_T_9600, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9602 = bits(_T_7981, 68, 68) @[RegMapper.scala 175:77] + node _T_9603 = and(_T_9601, _T_9602) @[RegMapper.scala 175:66] + node _T_9604 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9606 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9607 = and(_T_9604, _T_9606) @[RegMapper.scala 176:46] + node _T_9608 = bits(_T_7981, 68, 68) @[RegMapper.scala 176:77] + node _T_9609 = and(_T_9607, _T_9608) @[RegMapper.scala 176:66] + node _T_9610 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9611 = and(_T_9610, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9612 = bits(_T_8239, 68, 68) @[RegMapper.scala 177:77] + node _T_9613 = and(_T_9611, _T_9612) @[RegMapper.scala 177:66] + node _T_9614 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9616 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9617 = and(_T_9614, _T_9616) @[RegMapper.scala 178:46] + node _T_9618 = bits(_T_8239, 68, 68) @[RegMapper.scala 178:77] + node _T_9619 = and(_T_9617, _T_9618) @[RegMapper.scala 178:66] + node _T_9620 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9621 = and(_T_9620, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9622 = bits(_T_7981, 69, 69) @[RegMapper.scala 175:77] + node _T_9623 = and(_T_9621, _T_9622) @[RegMapper.scala 175:66] + node _T_9624 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9626 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9627 = and(_T_9624, _T_9626) @[RegMapper.scala 176:46] + node _T_9628 = bits(_T_7981, 69, 69) @[RegMapper.scala 176:77] + node _T_9629 = and(_T_9627, _T_9628) @[RegMapper.scala 176:66] + node _T_9630 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9631 = and(_T_9630, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9632 = bits(_T_8239, 69, 69) @[RegMapper.scala 177:77] + node _T_9633 = and(_T_9631, _T_9632) @[RegMapper.scala 177:66] + node _T_9634 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9636 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9637 = and(_T_9634, _T_9636) @[RegMapper.scala 178:46] + node _T_9638 = bits(_T_8239, 69, 69) @[RegMapper.scala 178:77] + node _T_9639 = and(_T_9637, _T_9638) @[RegMapper.scala 178:66] + node _T_9640 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9641 = and(_T_9640, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9642 = bits(_T_7981, 70, 70) @[RegMapper.scala 175:77] + node _T_9643 = and(_T_9641, _T_9642) @[RegMapper.scala 175:66] + node _T_9644 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9646 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9647 = and(_T_9644, _T_9646) @[RegMapper.scala 176:46] + node _T_9648 = bits(_T_7981, 70, 70) @[RegMapper.scala 176:77] + node _T_9649 = and(_T_9647, _T_9648) @[RegMapper.scala 176:66] + node _T_9650 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9651 = and(_T_9650, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9652 = bits(_T_8239, 70, 70) @[RegMapper.scala 177:77] + node _T_9653 = and(_T_9651, _T_9652) @[RegMapper.scala 177:66] + node _T_9654 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9656 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9657 = and(_T_9654, _T_9656) @[RegMapper.scala 178:46] + node _T_9658 = bits(_T_8239, 70, 70) @[RegMapper.scala 178:77] + node _T_9659 = and(_T_9657, _T_9658) @[RegMapper.scala 178:66] + node _T_9660 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9661 = and(_T_9660, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9662 = bits(_T_7981, 71, 71) @[RegMapper.scala 175:77] + node _T_9663 = and(_T_9661, _T_9662) @[RegMapper.scala 175:66] + node _T_9664 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9666 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9667 = and(_T_9664, _T_9666) @[RegMapper.scala 176:46] + node _T_9668 = bits(_T_7981, 71, 71) @[RegMapper.scala 176:77] + node _T_9669 = and(_T_9667, _T_9668) @[RegMapper.scala 176:66] + node _T_9670 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9671 = and(_T_9670, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9672 = bits(_T_8239, 71, 71) @[RegMapper.scala 177:77] + node _T_9673 = and(_T_9671, _T_9672) @[RegMapper.scala 177:66] + node _T_9674 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9676 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9677 = and(_T_9674, _T_9676) @[RegMapper.scala 178:46] + node _T_9678 = bits(_T_8239, 71, 71) @[RegMapper.scala 178:77] + node _T_9679 = and(_T_9677, _T_9678) @[RegMapper.scala 178:66] + node _T_9680 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9681 = and(_T_9680, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9682 = bits(_T_7981, 72, 72) @[RegMapper.scala 175:77] + node _T_9683 = and(_T_9681, _T_9682) @[RegMapper.scala 175:66] + node _T_9684 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9686 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9687 = and(_T_9684, _T_9686) @[RegMapper.scala 176:46] + node _T_9688 = bits(_T_7981, 72, 72) @[RegMapper.scala 176:77] + node _T_9689 = and(_T_9687, _T_9688) @[RegMapper.scala 176:66] + node _T_9690 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9691 = and(_T_9690, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9692 = bits(_T_8239, 72, 72) @[RegMapper.scala 177:77] + node _T_9693 = and(_T_9691, _T_9692) @[RegMapper.scala 177:66] + node _T_9694 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9696 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9697 = and(_T_9694, _T_9696) @[RegMapper.scala 178:46] + node _T_9698 = bits(_T_8239, 72, 72) @[RegMapper.scala 178:77] + node _T_9699 = and(_T_9697, _T_9698) @[RegMapper.scala 178:66] + node _T_9700 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9701 = and(_T_9700, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9702 = bits(_T_7981, 73, 73) @[RegMapper.scala 175:77] + node _T_9703 = and(_T_9701, _T_9702) @[RegMapper.scala 175:66] + node _T_9704 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9706 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9707 = and(_T_9704, _T_9706) @[RegMapper.scala 176:46] + node _T_9708 = bits(_T_7981, 73, 73) @[RegMapper.scala 176:77] + node _T_9709 = and(_T_9707, _T_9708) @[RegMapper.scala 176:66] + node _T_9710 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9711 = and(_T_9710, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9712 = bits(_T_8239, 73, 73) @[RegMapper.scala 177:77] + node _T_9713 = and(_T_9711, _T_9712) @[RegMapper.scala 177:66] + node _T_9714 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9716 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9717 = and(_T_9714, _T_9716) @[RegMapper.scala 178:46] + node _T_9718 = bits(_T_8239, 73, 73) @[RegMapper.scala 178:77] + node _T_9719 = and(_T_9717, _T_9718) @[RegMapper.scala 178:66] + node _T_9720 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9721 = and(_T_9720, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9722 = bits(_T_7981, 74, 74) @[RegMapper.scala 175:77] + node _T_9723 = and(_T_9721, _T_9722) @[RegMapper.scala 175:66] + node _T_9724 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9726 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9727 = and(_T_9724, _T_9726) @[RegMapper.scala 176:46] + node _T_9728 = bits(_T_7981, 74, 74) @[RegMapper.scala 176:77] + node _T_9729 = and(_T_9727, _T_9728) @[RegMapper.scala 176:66] + node _T_9730 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9731 = and(_T_9730, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9732 = bits(_T_8239, 74, 74) @[RegMapper.scala 177:77] + node _T_9733 = and(_T_9731, _T_9732) @[RegMapper.scala 177:66] + node _T_9734 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9736 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9737 = and(_T_9734, _T_9736) @[RegMapper.scala 178:46] + node _T_9738 = bits(_T_8239, 74, 74) @[RegMapper.scala 178:77] + node _T_9739 = and(_T_9737, _T_9738) @[RegMapper.scala 178:66] + node _T_9740 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9741 = and(_T_9740, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9742 = bits(_T_7981, 75, 75) @[RegMapper.scala 175:77] + node _T_9743 = and(_T_9741, _T_9742) @[RegMapper.scala 175:66] + node _T_9744 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9746 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9747 = and(_T_9744, _T_9746) @[RegMapper.scala 176:46] + node _T_9748 = bits(_T_7981, 75, 75) @[RegMapper.scala 176:77] + node _T_9749 = and(_T_9747, _T_9748) @[RegMapper.scala 176:66] + node _T_9750 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9751 = and(_T_9750, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9752 = bits(_T_8239, 75, 75) @[RegMapper.scala 177:77] + node _T_9753 = and(_T_9751, _T_9752) @[RegMapper.scala 177:66] + node _T_9754 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9756 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9757 = and(_T_9754, _T_9756) @[RegMapper.scala 178:46] + node _T_9758 = bits(_T_8239, 75, 75) @[RegMapper.scala 178:77] + node _T_9759 = and(_T_9757, _T_9758) @[RegMapper.scala 178:66] + node _T_9760 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9761 = and(_T_9760, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9762 = bits(_T_7981, 76, 76) @[RegMapper.scala 175:77] + node _T_9763 = and(_T_9761, _T_9762) @[RegMapper.scala 175:66] + node _T_9764 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9766 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9767 = and(_T_9764, _T_9766) @[RegMapper.scala 176:46] + node _T_9768 = bits(_T_7981, 76, 76) @[RegMapper.scala 176:77] + node _T_9769 = and(_T_9767, _T_9768) @[RegMapper.scala 176:66] + node _T_9770 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9771 = and(_T_9770, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9772 = bits(_T_8239, 76, 76) @[RegMapper.scala 177:77] + node _T_9773 = and(_T_9771, _T_9772) @[RegMapper.scala 177:66] + node _T_9774 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9776 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9777 = and(_T_9774, _T_9776) @[RegMapper.scala 178:46] + node _T_9778 = bits(_T_8239, 76, 76) @[RegMapper.scala 178:77] + node _T_9779 = and(_T_9777, _T_9778) @[RegMapper.scala 178:66] + node _T_9780 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9781 = and(_T_9780, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9782 = bits(_T_7981, 77, 77) @[RegMapper.scala 175:77] + node _T_9783 = and(_T_9781, _T_9782) @[RegMapper.scala 175:66] + node _T_9784 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9786 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9787 = and(_T_9784, _T_9786) @[RegMapper.scala 176:46] + node _T_9788 = bits(_T_7981, 77, 77) @[RegMapper.scala 176:77] + node _T_9789 = and(_T_9787, _T_9788) @[RegMapper.scala 176:66] + node _T_9790 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9791 = and(_T_9790, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9792 = bits(_T_8239, 77, 77) @[RegMapper.scala 177:77] + node _T_9793 = and(_T_9791, _T_9792) @[RegMapper.scala 177:66] + node _T_9794 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9796 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9797 = and(_T_9794, _T_9796) @[RegMapper.scala 178:46] + node _T_9798 = bits(_T_8239, 77, 77) @[RegMapper.scala 178:77] + node _T_9799 = and(_T_9797, _T_9798) @[RegMapper.scala 178:66] + node _T_9800 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9801 = and(_T_9800, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9802 = bits(_T_7981, 78, 78) @[RegMapper.scala 175:77] + node _T_9803 = and(_T_9801, _T_9802) @[RegMapper.scala 175:66] + node _T_9804 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9806 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9807 = and(_T_9804, _T_9806) @[RegMapper.scala 176:46] + node _T_9808 = bits(_T_7981, 78, 78) @[RegMapper.scala 176:77] + node _T_9809 = and(_T_9807, _T_9808) @[RegMapper.scala 176:66] + node _T_9810 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9811 = and(_T_9810, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9812 = bits(_T_8239, 78, 78) @[RegMapper.scala 177:77] + node _T_9813 = and(_T_9811, _T_9812) @[RegMapper.scala 177:66] + node _T_9814 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9816 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9817 = and(_T_9814, _T_9816) @[RegMapper.scala 178:46] + node _T_9818 = bits(_T_8239, 78, 78) @[RegMapper.scala 178:77] + node _T_9819 = and(_T_9817, _T_9818) @[RegMapper.scala 178:66] + node _T_9820 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9821 = and(_T_9820, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9822 = bits(_T_7981, 79, 79) @[RegMapper.scala 175:77] + node _T_9823 = and(_T_9821, _T_9822) @[RegMapper.scala 175:66] + node _T_9824 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9826 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9827 = and(_T_9824, _T_9826) @[RegMapper.scala 176:46] + node _T_9828 = bits(_T_7981, 79, 79) @[RegMapper.scala 176:77] + node _T_9829 = and(_T_9827, _T_9828) @[RegMapper.scala 176:66] + node _T_9830 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9831 = and(_T_9830, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9832 = bits(_T_8239, 79, 79) @[RegMapper.scala 177:77] + node _T_9833 = and(_T_9831, _T_9832) @[RegMapper.scala 177:66] + node _T_9834 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9836 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9837 = and(_T_9834, _T_9836) @[RegMapper.scala 178:46] + node _T_9838 = bits(_T_8239, 79, 79) @[RegMapper.scala 178:77] + node _T_9839 = and(_T_9837, _T_9838) @[RegMapper.scala 178:66] + node _T_9840 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9841 = and(_T_9840, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9842 = bits(_T_7981, 80, 80) @[RegMapper.scala 175:77] + node _T_9843 = and(_T_9841, _T_9842) @[RegMapper.scala 175:66] + node _T_9844 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9846 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9847 = and(_T_9844, _T_9846) @[RegMapper.scala 176:46] + node _T_9848 = bits(_T_7981, 80, 80) @[RegMapper.scala 176:77] + node _T_9849 = and(_T_9847, _T_9848) @[RegMapper.scala 176:66] + node _T_9850 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9851 = and(_T_9850, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9852 = bits(_T_8239, 80, 80) @[RegMapper.scala 177:77] + node _T_9853 = and(_T_9851, _T_9852) @[RegMapper.scala 177:66] + node _T_9854 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9856 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9857 = and(_T_9854, _T_9856) @[RegMapper.scala 178:46] + node _T_9858 = bits(_T_8239, 80, 80) @[RegMapper.scala 178:77] + node _T_9859 = and(_T_9857, _T_9858) @[RegMapper.scala 178:66] + node _T_9860 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9861 = and(_T_9860, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9862 = bits(_T_7981, 81, 81) @[RegMapper.scala 175:77] + node _T_9863 = and(_T_9861, _T_9862) @[RegMapper.scala 175:66] + node _T_9864 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9866 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9867 = and(_T_9864, _T_9866) @[RegMapper.scala 176:46] + node _T_9868 = bits(_T_7981, 81, 81) @[RegMapper.scala 176:77] + node _T_9869 = and(_T_9867, _T_9868) @[RegMapper.scala 176:66] + node _T_9870 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9871 = and(_T_9870, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9872 = bits(_T_8239, 81, 81) @[RegMapper.scala 177:77] + node _T_9873 = and(_T_9871, _T_9872) @[RegMapper.scala 177:66] + node _T_9874 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9876 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9877 = and(_T_9874, _T_9876) @[RegMapper.scala 178:46] + node _T_9878 = bits(_T_8239, 81, 81) @[RegMapper.scala 178:77] + node _T_9879 = and(_T_9877, _T_9878) @[RegMapper.scala 178:66] + node _T_9880 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9881 = and(_T_9880, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9882 = bits(_T_7981, 82, 82) @[RegMapper.scala 175:77] + node _T_9883 = and(_T_9881, _T_9882) @[RegMapper.scala 175:66] + node _T_9884 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9886 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9887 = and(_T_9884, _T_9886) @[RegMapper.scala 176:46] + node _T_9888 = bits(_T_7981, 82, 82) @[RegMapper.scala 176:77] + node _T_9889 = and(_T_9887, _T_9888) @[RegMapper.scala 176:66] + node _T_9890 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9891 = and(_T_9890, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9892 = bits(_T_8239, 82, 82) @[RegMapper.scala 177:77] + node _T_9893 = and(_T_9891, _T_9892) @[RegMapper.scala 177:66] + node _T_9894 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9896 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9897 = and(_T_9894, _T_9896) @[RegMapper.scala 178:46] + node _T_9898 = bits(_T_8239, 82, 82) @[RegMapper.scala 178:77] + node _T_9899 = and(_T_9897, _T_9898) @[RegMapper.scala 178:66] + node _T_9900 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9901 = and(_T_9900, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9902 = bits(_T_7981, 83, 83) @[RegMapper.scala 175:77] + node _T_9903 = and(_T_9901, _T_9902) @[RegMapper.scala 175:66] + node _T_9904 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9906 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9907 = and(_T_9904, _T_9906) @[RegMapper.scala 176:46] + node _T_9908 = bits(_T_7981, 83, 83) @[RegMapper.scala 176:77] + node _T_9909 = and(_T_9907, _T_9908) @[RegMapper.scala 176:66] + node _T_9910 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9911 = and(_T_9910, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9912 = bits(_T_8239, 83, 83) @[RegMapper.scala 177:77] + node _T_9913 = and(_T_9911, _T_9912) @[RegMapper.scala 177:66] + node _T_9914 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9916 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9917 = and(_T_9914, _T_9916) @[RegMapper.scala 178:46] + node _T_9918 = bits(_T_8239, 83, 83) @[RegMapper.scala 178:77] + node _T_9919 = and(_T_9917, _T_9918) @[RegMapper.scala 178:66] + node _T_9920 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9921 = and(_T_9920, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9922 = bits(_T_7981, 84, 84) @[RegMapper.scala 175:77] + node _T_9923 = and(_T_9921, _T_9922) @[RegMapper.scala 175:66] + node _T_9924 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9926 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9927 = and(_T_9924, _T_9926) @[RegMapper.scala 176:46] + node _T_9928 = bits(_T_7981, 84, 84) @[RegMapper.scala 176:77] + node _T_9929 = and(_T_9927, _T_9928) @[RegMapper.scala 176:66] + node _T_9930 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9931 = and(_T_9930, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9932 = bits(_T_8239, 84, 84) @[RegMapper.scala 177:77] + node _T_9933 = and(_T_9931, _T_9932) @[RegMapper.scala 177:66] + node _T_9934 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9936 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9937 = and(_T_9934, _T_9936) @[RegMapper.scala 178:46] + node _T_9938 = bits(_T_8239, 84, 84) @[RegMapper.scala 178:77] + node _T_9939 = and(_T_9937, _T_9938) @[RegMapper.scala 178:66] + node _T_9940 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9941 = and(_T_9940, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9942 = bits(_T_7981, 85, 85) @[RegMapper.scala 175:77] + node _T_9943 = and(_T_9941, _T_9942) @[RegMapper.scala 175:66] + node _T_9944 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9946 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9947 = and(_T_9944, _T_9946) @[RegMapper.scala 176:46] + node _T_9948 = bits(_T_7981, 85, 85) @[RegMapper.scala 176:77] + node _T_9949 = and(_T_9947, _T_9948) @[RegMapper.scala 176:66] + node _T_9950 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9951 = and(_T_9950, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9952 = bits(_T_8239, 85, 85) @[RegMapper.scala 177:77] + node _T_9953 = and(_T_9951, _T_9952) @[RegMapper.scala 177:66] + node _T_9954 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9956 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9957 = and(_T_9954, _T_9956) @[RegMapper.scala 178:46] + node _T_9958 = bits(_T_8239, 85, 85) @[RegMapper.scala 178:77] + node _T_9959 = and(_T_9957, _T_9958) @[RegMapper.scala 178:66] + node _T_9960 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9961 = and(_T_9960, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9962 = bits(_T_7981, 86, 86) @[RegMapper.scala 175:77] + node _T_9963 = and(_T_9961, _T_9962) @[RegMapper.scala 175:66] + node _T_9964 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9966 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9967 = and(_T_9964, _T_9966) @[RegMapper.scala 176:46] + node _T_9968 = bits(_T_7981, 86, 86) @[RegMapper.scala 176:77] + node _T_9969 = and(_T_9967, _T_9968) @[RegMapper.scala 176:66] + node _T_9970 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9971 = and(_T_9970, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9972 = bits(_T_8239, 86, 86) @[RegMapper.scala 177:77] + node _T_9973 = and(_T_9971, _T_9972) @[RegMapper.scala 177:66] + node _T_9974 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9976 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9977 = and(_T_9974, _T_9976) @[RegMapper.scala 178:46] + node _T_9978 = bits(_T_8239, 86, 86) @[RegMapper.scala 178:77] + node _T_9979 = and(_T_9977, _T_9978) @[RegMapper.scala 178:66] + node _T_9980 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_9981 = and(_T_9980, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_9982 = bits(_T_7981, 87, 87) @[RegMapper.scala 175:77] + node _T_9983 = and(_T_9981, _T_9982) @[RegMapper.scala 175:66] + node _T_9984 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_9986 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_9987 = and(_T_9984, _T_9986) @[RegMapper.scala 176:46] + node _T_9988 = bits(_T_7981, 87, 87) @[RegMapper.scala 176:77] + node _T_9989 = and(_T_9987, _T_9988) @[RegMapper.scala 176:66] + node _T_9990 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_9991 = and(_T_9990, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_9992 = bits(_T_8239, 87, 87) @[RegMapper.scala 177:77] + node _T_9993 = and(_T_9991, _T_9992) @[RegMapper.scala 177:66] + node _T_9994 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_9996 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_9997 = and(_T_9994, _T_9996) @[RegMapper.scala 178:46] + node _T_9998 = bits(_T_8239, 87, 87) @[RegMapper.scala 178:77] + node _T_9999 = and(_T_9997, _T_9998) @[RegMapper.scala 178:66] + node _T_10000 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10001 = and(_T_10000, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10002 = bits(_T_7981, 88, 88) @[RegMapper.scala 175:77] + node _T_10003 = and(_T_10001, _T_10002) @[RegMapper.scala 175:66] + node _T_10004 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10006 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10007 = and(_T_10004, _T_10006) @[RegMapper.scala 176:46] + node _T_10008 = bits(_T_7981, 88, 88) @[RegMapper.scala 176:77] + node _T_10009 = and(_T_10007, _T_10008) @[RegMapper.scala 176:66] + node _T_10010 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10011 = and(_T_10010, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10012 = bits(_T_8239, 88, 88) @[RegMapper.scala 177:77] + node _T_10013 = and(_T_10011, _T_10012) @[RegMapper.scala 177:66] + node _T_10014 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10016 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10017 = and(_T_10014, _T_10016) @[RegMapper.scala 178:46] + node _T_10018 = bits(_T_8239, 88, 88) @[RegMapper.scala 178:77] + node _T_10019 = and(_T_10017, _T_10018) @[RegMapper.scala 178:66] + node _T_10020 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10021 = and(_T_10020, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10022 = bits(_T_7981, 89, 89) @[RegMapper.scala 175:77] + node _T_10023 = and(_T_10021, _T_10022) @[RegMapper.scala 175:66] + node _T_10024 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10026 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10027 = and(_T_10024, _T_10026) @[RegMapper.scala 176:46] + node _T_10028 = bits(_T_7981, 89, 89) @[RegMapper.scala 176:77] + node _T_10029 = and(_T_10027, _T_10028) @[RegMapper.scala 176:66] + node _T_10030 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10031 = and(_T_10030, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10032 = bits(_T_8239, 89, 89) @[RegMapper.scala 177:77] + node _T_10033 = and(_T_10031, _T_10032) @[RegMapper.scala 177:66] + node _T_10034 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10036 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10037 = and(_T_10034, _T_10036) @[RegMapper.scala 178:46] + node _T_10038 = bits(_T_8239, 89, 89) @[RegMapper.scala 178:77] + node _T_10039 = and(_T_10037, _T_10038) @[RegMapper.scala 178:66] + node _T_10040 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10041 = and(_T_10040, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10042 = bits(_T_7981, 90, 90) @[RegMapper.scala 175:77] + node _T_10043 = and(_T_10041, _T_10042) @[RegMapper.scala 175:66] + node _T_10044 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10046 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10047 = and(_T_10044, _T_10046) @[RegMapper.scala 176:46] + node _T_10048 = bits(_T_7981, 90, 90) @[RegMapper.scala 176:77] + node _T_10049 = and(_T_10047, _T_10048) @[RegMapper.scala 176:66] + node _T_10050 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10051 = and(_T_10050, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10052 = bits(_T_8239, 90, 90) @[RegMapper.scala 177:77] + node _T_10053 = and(_T_10051, _T_10052) @[RegMapper.scala 177:66] + node _T_10054 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10056 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10057 = and(_T_10054, _T_10056) @[RegMapper.scala 178:46] + node _T_10058 = bits(_T_8239, 90, 90) @[RegMapper.scala 178:77] + node _T_10059 = and(_T_10057, _T_10058) @[RegMapper.scala 178:66] + node _T_10060 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10061 = and(_T_10060, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10062 = bits(_T_7981, 91, 91) @[RegMapper.scala 175:77] + node _T_10063 = and(_T_10061, _T_10062) @[RegMapper.scala 175:66] + node _T_10064 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10066 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10067 = and(_T_10064, _T_10066) @[RegMapper.scala 176:46] + node _T_10068 = bits(_T_7981, 91, 91) @[RegMapper.scala 176:77] + node _T_10069 = and(_T_10067, _T_10068) @[RegMapper.scala 176:66] + node _T_10070 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10071 = and(_T_10070, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10072 = bits(_T_8239, 91, 91) @[RegMapper.scala 177:77] + node _T_10073 = and(_T_10071, _T_10072) @[RegMapper.scala 177:66] + node _T_10074 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10076 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10077 = and(_T_10074, _T_10076) @[RegMapper.scala 178:46] + node _T_10078 = bits(_T_8239, 91, 91) @[RegMapper.scala 178:77] + node _T_10079 = and(_T_10077, _T_10078) @[RegMapper.scala 178:66] + node _T_10080 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10081 = and(_T_10080, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10082 = bits(_T_7981, 92, 92) @[RegMapper.scala 175:77] + node _T_10083 = and(_T_10081, _T_10082) @[RegMapper.scala 175:66] + node _T_10084 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10086 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10087 = and(_T_10084, _T_10086) @[RegMapper.scala 176:46] + node _T_10088 = bits(_T_7981, 92, 92) @[RegMapper.scala 176:77] + node _T_10089 = and(_T_10087, _T_10088) @[RegMapper.scala 176:66] + node _T_10090 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10091 = and(_T_10090, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10092 = bits(_T_8239, 92, 92) @[RegMapper.scala 177:77] + node _T_10093 = and(_T_10091, _T_10092) @[RegMapper.scala 177:66] + node _T_10094 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10096 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10097 = and(_T_10094, _T_10096) @[RegMapper.scala 178:46] + node _T_10098 = bits(_T_8239, 92, 92) @[RegMapper.scala 178:77] + node _T_10099 = and(_T_10097, _T_10098) @[RegMapper.scala 178:66] + node _T_10100 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10101 = and(_T_10100, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10102 = bits(_T_7981, 93, 93) @[RegMapper.scala 175:77] + node _T_10103 = and(_T_10101, _T_10102) @[RegMapper.scala 175:66] + node _T_10104 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10106 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10107 = and(_T_10104, _T_10106) @[RegMapper.scala 176:46] + node _T_10108 = bits(_T_7981, 93, 93) @[RegMapper.scala 176:77] + node _T_10109 = and(_T_10107, _T_10108) @[RegMapper.scala 176:66] + node _T_10110 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10111 = and(_T_10110, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10112 = bits(_T_8239, 93, 93) @[RegMapper.scala 177:77] + node _T_10113 = and(_T_10111, _T_10112) @[RegMapper.scala 177:66] + node _T_10114 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10116 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10117 = and(_T_10114, _T_10116) @[RegMapper.scala 178:46] + node _T_10118 = bits(_T_8239, 93, 93) @[RegMapper.scala 178:77] + node _T_10119 = and(_T_10117, _T_10118) @[RegMapper.scala 178:66] + node _T_10120 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10121 = and(_T_10120, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10122 = bits(_T_7981, 94, 94) @[RegMapper.scala 175:77] + node _T_10123 = and(_T_10121, _T_10122) @[RegMapper.scala 175:66] + node _T_10124 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10126 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10127 = and(_T_10124, _T_10126) @[RegMapper.scala 176:46] + node _T_10128 = bits(_T_7981, 94, 94) @[RegMapper.scala 176:77] + node _T_10129 = and(_T_10127, _T_10128) @[RegMapper.scala 176:66] + node _T_10130 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10131 = and(_T_10130, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10132 = bits(_T_8239, 94, 94) @[RegMapper.scala 177:77] + node _T_10133 = and(_T_10131, _T_10132) @[RegMapper.scala 177:66] + node _T_10134 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10136 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10137 = and(_T_10134, _T_10136) @[RegMapper.scala 178:46] + node _T_10138 = bits(_T_8239, 94, 94) @[RegMapper.scala 178:77] + node _T_10139 = and(_T_10137, _T_10138) @[RegMapper.scala 178:66] + node _T_10140 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10141 = and(_T_10140, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10142 = bits(_T_7981, 95, 95) @[RegMapper.scala 175:77] + node _T_10143 = and(_T_10141, _T_10142) @[RegMapper.scala 175:66] + node _T_10144 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10146 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10147 = and(_T_10144, _T_10146) @[RegMapper.scala 176:46] + node _T_10148 = bits(_T_7981, 95, 95) @[RegMapper.scala 176:77] + node _T_10149 = and(_T_10147, _T_10148) @[RegMapper.scala 176:66] + node _T_10150 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10151 = and(_T_10150, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10152 = bits(_T_8239, 95, 95) @[RegMapper.scala 177:77] + node _T_10153 = and(_T_10151, _T_10152) @[RegMapper.scala 177:66] + node _T_10154 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10156 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10157 = and(_T_10154, _T_10156) @[RegMapper.scala 178:46] + node _T_10158 = bits(_T_8239, 95, 95) @[RegMapper.scala 178:77] + node _T_10159 = and(_T_10157, _T_10158) @[RegMapper.scala 178:66] + node _T_10160 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10161 = and(_T_10160, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10162 = bits(_T_7981, 96, 96) @[RegMapper.scala 175:77] + node _T_10163 = and(_T_10161, _T_10162) @[RegMapper.scala 175:66] + node _T_10164 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10166 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10167 = and(_T_10164, _T_10166) @[RegMapper.scala 176:46] + node _T_10168 = bits(_T_7981, 96, 96) @[RegMapper.scala 176:77] + node _T_10169 = and(_T_10167, _T_10168) @[RegMapper.scala 176:66] + node _T_10170 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10171 = and(_T_10170, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10172 = bits(_T_8239, 96, 96) @[RegMapper.scala 177:77] + node _T_10173 = and(_T_10171, _T_10172) @[RegMapper.scala 177:66] + node _T_10174 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10176 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10177 = and(_T_10174, _T_10176) @[RegMapper.scala 178:46] + node _T_10178 = bits(_T_8239, 96, 96) @[RegMapper.scala 178:77] + node _T_10179 = and(_T_10177, _T_10178) @[RegMapper.scala 178:66] + node _T_10180 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10181 = and(_T_10180, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10182 = bits(_T_7981, 97, 97) @[RegMapper.scala 175:77] + node _T_10183 = and(_T_10181, _T_10182) @[RegMapper.scala 175:66] + node _T_10184 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10186 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10187 = and(_T_10184, _T_10186) @[RegMapper.scala 176:46] + node _T_10188 = bits(_T_7981, 97, 97) @[RegMapper.scala 176:77] + node _T_10189 = and(_T_10187, _T_10188) @[RegMapper.scala 176:66] + node _T_10190 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10191 = and(_T_10190, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10192 = bits(_T_8239, 97, 97) @[RegMapper.scala 177:77] + node _T_10193 = and(_T_10191, _T_10192) @[RegMapper.scala 177:66] + node _T_10194 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10196 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10197 = and(_T_10194, _T_10196) @[RegMapper.scala 178:46] + node _T_10198 = bits(_T_8239, 97, 97) @[RegMapper.scala 178:77] + node _T_10199 = and(_T_10197, _T_10198) @[RegMapper.scala 178:66] + node _T_10200 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10201 = and(_T_10200, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10202 = bits(_T_7981, 98, 98) @[RegMapper.scala 175:77] + node _T_10203 = and(_T_10201, _T_10202) @[RegMapper.scala 175:66] + node _T_10204 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10206 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10207 = and(_T_10204, _T_10206) @[RegMapper.scala 176:46] + node _T_10208 = bits(_T_7981, 98, 98) @[RegMapper.scala 176:77] + node _T_10209 = and(_T_10207, _T_10208) @[RegMapper.scala 176:66] + node _T_10210 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10211 = and(_T_10210, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10212 = bits(_T_8239, 98, 98) @[RegMapper.scala 177:77] + node _T_10213 = and(_T_10211, _T_10212) @[RegMapper.scala 177:66] + node _T_10214 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10216 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10217 = and(_T_10214, _T_10216) @[RegMapper.scala 178:46] + node _T_10218 = bits(_T_8239, 98, 98) @[RegMapper.scala 178:77] + node _T_10219 = and(_T_10217, _T_10218) @[RegMapper.scala 178:66] + node _T_10220 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10221 = and(_T_10220, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10222 = bits(_T_7981, 99, 99) @[RegMapper.scala 175:77] + node _T_10223 = and(_T_10221, _T_10222) @[RegMapper.scala 175:66] + node _T_10224 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10226 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10227 = and(_T_10224, _T_10226) @[RegMapper.scala 176:46] + node _T_10228 = bits(_T_7981, 99, 99) @[RegMapper.scala 176:77] + node _T_10229 = and(_T_10227, _T_10228) @[RegMapper.scala 176:66] + node _T_10230 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10231 = and(_T_10230, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10232 = bits(_T_8239, 99, 99) @[RegMapper.scala 177:77] + node _T_10233 = and(_T_10231, _T_10232) @[RegMapper.scala 177:66] + node _T_10234 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10236 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10237 = and(_T_10234, _T_10236) @[RegMapper.scala 178:46] + node _T_10238 = bits(_T_8239, 99, 99) @[RegMapper.scala 178:77] + node _T_10239 = and(_T_10237, _T_10238) @[RegMapper.scala 178:66] + node _T_10240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10241 = and(_T_10240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10242 = bits(_T_7981, 100, 100) @[RegMapper.scala 175:77] + node _T_10243 = and(_T_10241, _T_10242) @[RegMapper.scala 175:66] + node _T_10244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10247 = and(_T_10244, _T_10246) @[RegMapper.scala 176:46] + node _T_10248 = bits(_T_7981, 100, 100) @[RegMapper.scala 176:77] + node _T_10249 = and(_T_10247, _T_10248) @[RegMapper.scala 176:66] + node _T_10250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10251 = and(_T_10250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10252 = bits(_T_8239, 100, 100) @[RegMapper.scala 177:77] + node _T_10253 = and(_T_10251, _T_10252) @[RegMapper.scala 177:66] + node _T_10254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10257 = and(_T_10254, _T_10256) @[RegMapper.scala 178:46] + node _T_10258 = bits(_T_8239, 100, 100) @[RegMapper.scala 178:77] + node _T_10259 = and(_T_10257, _T_10258) @[RegMapper.scala 178:66] + node _T_10260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10261 = and(_T_10260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10262 = bits(_T_7981, 101, 101) @[RegMapper.scala 175:77] + node _T_10263 = and(_T_10261, _T_10262) @[RegMapper.scala 175:66] + node _T_10264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10267 = and(_T_10264, _T_10266) @[RegMapper.scala 176:46] + node _T_10268 = bits(_T_7981, 101, 101) @[RegMapper.scala 176:77] + node _T_10269 = and(_T_10267, _T_10268) @[RegMapper.scala 176:66] + node _T_10270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10271 = and(_T_10270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10272 = bits(_T_8239, 101, 101) @[RegMapper.scala 177:77] + node _T_10273 = and(_T_10271, _T_10272) @[RegMapper.scala 177:66] + node _T_10274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10277 = and(_T_10274, _T_10276) @[RegMapper.scala 178:46] + node _T_10278 = bits(_T_8239, 101, 101) @[RegMapper.scala 178:77] + node _T_10279 = and(_T_10277, _T_10278) @[RegMapper.scala 178:66] + node _T_10280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10281 = and(_T_10280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10282 = bits(_T_7981, 102, 102) @[RegMapper.scala 175:77] + node _T_10283 = and(_T_10281, _T_10282) @[RegMapper.scala 175:66] + node _T_10284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10287 = and(_T_10284, _T_10286) @[RegMapper.scala 176:46] + node _T_10288 = bits(_T_7981, 102, 102) @[RegMapper.scala 176:77] + node _T_10289 = and(_T_10287, _T_10288) @[RegMapper.scala 176:66] + node _T_10290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10291 = and(_T_10290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10292 = bits(_T_8239, 102, 102) @[RegMapper.scala 177:77] + node _T_10293 = and(_T_10291, _T_10292) @[RegMapper.scala 177:66] + node _T_10294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10297 = and(_T_10294, _T_10296) @[RegMapper.scala 178:46] + node _T_10298 = bits(_T_8239, 102, 102) @[RegMapper.scala 178:77] + node _T_10299 = and(_T_10297, _T_10298) @[RegMapper.scala 178:66] + node _T_10300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10301 = and(_T_10300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10302 = bits(_T_7981, 103, 103) @[RegMapper.scala 175:77] + node _T_10303 = and(_T_10301, _T_10302) @[RegMapper.scala 175:66] + node _T_10304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10307 = and(_T_10304, _T_10306) @[RegMapper.scala 176:46] + node _T_10308 = bits(_T_7981, 103, 103) @[RegMapper.scala 176:77] + node _T_10309 = and(_T_10307, _T_10308) @[RegMapper.scala 176:66] + node _T_10310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10311 = and(_T_10310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10312 = bits(_T_8239, 103, 103) @[RegMapper.scala 177:77] + node _T_10313 = and(_T_10311, _T_10312) @[RegMapper.scala 177:66] + node _T_10314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10317 = and(_T_10314, _T_10316) @[RegMapper.scala 178:46] + node _T_10318 = bits(_T_8239, 103, 103) @[RegMapper.scala 178:77] + node _T_10319 = and(_T_10317, _T_10318) @[RegMapper.scala 178:66] + node _T_10320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10321 = and(_T_10320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10322 = bits(_T_7981, 104, 104) @[RegMapper.scala 175:77] + node _T_10323 = and(_T_10321, _T_10322) @[RegMapper.scala 175:66] + node _T_10324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10327 = and(_T_10324, _T_10326) @[RegMapper.scala 176:46] + node _T_10328 = bits(_T_7981, 104, 104) @[RegMapper.scala 176:77] + node _T_10329 = and(_T_10327, _T_10328) @[RegMapper.scala 176:66] + node _T_10330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10331 = and(_T_10330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10332 = bits(_T_8239, 104, 104) @[RegMapper.scala 177:77] + node _T_10333 = and(_T_10331, _T_10332) @[RegMapper.scala 177:66] + node _T_10334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10337 = and(_T_10334, _T_10336) @[RegMapper.scala 178:46] + node _T_10338 = bits(_T_8239, 104, 104) @[RegMapper.scala 178:77] + node _T_10339 = and(_T_10337, _T_10338) @[RegMapper.scala 178:66] + node _T_10340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10341 = and(_T_10340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10342 = bits(_T_7981, 105, 105) @[RegMapper.scala 175:77] + node _T_10343 = and(_T_10341, _T_10342) @[RegMapper.scala 175:66] + node _T_10344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10347 = and(_T_10344, _T_10346) @[RegMapper.scala 176:46] + node _T_10348 = bits(_T_7981, 105, 105) @[RegMapper.scala 176:77] + node _T_10349 = and(_T_10347, _T_10348) @[RegMapper.scala 176:66] + node _T_10350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10351 = and(_T_10350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10352 = bits(_T_8239, 105, 105) @[RegMapper.scala 177:77] + node _T_10353 = and(_T_10351, _T_10352) @[RegMapper.scala 177:66] + node _T_10354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10357 = and(_T_10354, _T_10356) @[RegMapper.scala 178:46] + node _T_10358 = bits(_T_8239, 105, 105) @[RegMapper.scala 178:77] + node _T_10359 = and(_T_10357, _T_10358) @[RegMapper.scala 178:66] + node _T_10360 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10361 = and(_T_10360, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10362 = bits(_T_7981, 106, 106) @[RegMapper.scala 175:77] + node _T_10363 = and(_T_10361, _T_10362) @[RegMapper.scala 175:66] + node _T_10364 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10366 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10367 = and(_T_10364, _T_10366) @[RegMapper.scala 176:46] + node _T_10368 = bits(_T_7981, 106, 106) @[RegMapper.scala 176:77] + node _T_10369 = and(_T_10367, _T_10368) @[RegMapper.scala 176:66] + node _T_10370 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10371 = and(_T_10370, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10372 = bits(_T_8239, 106, 106) @[RegMapper.scala 177:77] + node _T_10373 = and(_T_10371, _T_10372) @[RegMapper.scala 177:66] + node _T_10374 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10376 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10377 = and(_T_10374, _T_10376) @[RegMapper.scala 178:46] + node _T_10378 = bits(_T_8239, 106, 106) @[RegMapper.scala 178:77] + node _T_10379 = and(_T_10377, _T_10378) @[RegMapper.scala 178:66] + node _T_10380 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10381 = and(_T_10380, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10382 = bits(_T_7981, 107, 107) @[RegMapper.scala 175:77] + node _T_10383 = and(_T_10381, _T_10382) @[RegMapper.scala 175:66] + node _T_10384 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10386 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10387 = and(_T_10384, _T_10386) @[RegMapper.scala 176:46] + node _T_10388 = bits(_T_7981, 107, 107) @[RegMapper.scala 176:77] + node _T_10389 = and(_T_10387, _T_10388) @[RegMapper.scala 176:66] + node _T_10390 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10391 = and(_T_10390, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10392 = bits(_T_8239, 107, 107) @[RegMapper.scala 177:77] + node _T_10393 = and(_T_10391, _T_10392) @[RegMapper.scala 177:66] + node _T_10394 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10396 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10397 = and(_T_10394, _T_10396) @[RegMapper.scala 178:46] + node _T_10398 = bits(_T_8239, 107, 107) @[RegMapper.scala 178:77] + node _T_10399 = and(_T_10397, _T_10398) @[RegMapper.scala 178:66] + node _T_10400 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10401 = and(_T_10400, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10402 = bits(_T_7981, 108, 108) @[RegMapper.scala 175:77] + node _T_10403 = and(_T_10401, _T_10402) @[RegMapper.scala 175:66] + node _T_10404 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10406 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10407 = and(_T_10404, _T_10406) @[RegMapper.scala 176:46] + node _T_10408 = bits(_T_7981, 108, 108) @[RegMapper.scala 176:77] + node _T_10409 = and(_T_10407, _T_10408) @[RegMapper.scala 176:66] + node _T_10410 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10411 = and(_T_10410, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10412 = bits(_T_8239, 108, 108) @[RegMapper.scala 177:77] + node _T_10413 = and(_T_10411, _T_10412) @[RegMapper.scala 177:66] + node _T_10414 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10416 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10417 = and(_T_10414, _T_10416) @[RegMapper.scala 178:46] + node _T_10418 = bits(_T_8239, 108, 108) @[RegMapper.scala 178:77] + node _T_10419 = and(_T_10417, _T_10418) @[RegMapper.scala 178:66] + node _T_10420 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10421 = and(_T_10420, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10422 = bits(_T_7981, 109, 109) @[RegMapper.scala 175:77] + node _T_10423 = and(_T_10421, _T_10422) @[RegMapper.scala 175:66] + node _T_10424 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10426 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10427 = and(_T_10424, _T_10426) @[RegMapper.scala 176:46] + node _T_10428 = bits(_T_7981, 109, 109) @[RegMapper.scala 176:77] + node _T_10429 = and(_T_10427, _T_10428) @[RegMapper.scala 176:66] + node _T_10430 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10431 = and(_T_10430, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10432 = bits(_T_8239, 109, 109) @[RegMapper.scala 177:77] + node _T_10433 = and(_T_10431, _T_10432) @[RegMapper.scala 177:66] + node _T_10434 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10436 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10437 = and(_T_10434, _T_10436) @[RegMapper.scala 178:46] + node _T_10438 = bits(_T_8239, 109, 109) @[RegMapper.scala 178:77] + node _T_10439 = and(_T_10437, _T_10438) @[RegMapper.scala 178:66] + node _T_10440 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10441 = and(_T_10440, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10442 = bits(_T_7981, 110, 110) @[RegMapper.scala 175:77] + node _T_10443 = and(_T_10441, _T_10442) @[RegMapper.scala 175:66] + node _T_10444 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10446 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10447 = and(_T_10444, _T_10446) @[RegMapper.scala 176:46] + node _T_10448 = bits(_T_7981, 110, 110) @[RegMapper.scala 176:77] + node _T_10449 = and(_T_10447, _T_10448) @[RegMapper.scala 176:66] + node _T_10450 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10451 = and(_T_10450, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10452 = bits(_T_8239, 110, 110) @[RegMapper.scala 177:77] + node _T_10453 = and(_T_10451, _T_10452) @[RegMapper.scala 177:66] + node _T_10454 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10456 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10457 = and(_T_10454, _T_10456) @[RegMapper.scala 178:46] + node _T_10458 = bits(_T_8239, 110, 110) @[RegMapper.scala 178:77] + node _T_10459 = and(_T_10457, _T_10458) @[RegMapper.scala 178:66] + node _T_10460 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10461 = and(_T_10460, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10462 = bits(_T_7981, 111, 111) @[RegMapper.scala 175:77] + node _T_10463 = and(_T_10461, _T_10462) @[RegMapper.scala 175:66] + node _T_10464 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10466 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10467 = and(_T_10464, _T_10466) @[RegMapper.scala 176:46] + node _T_10468 = bits(_T_7981, 111, 111) @[RegMapper.scala 176:77] + node _T_10469 = and(_T_10467, _T_10468) @[RegMapper.scala 176:66] + node _T_10470 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10471 = and(_T_10470, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10472 = bits(_T_8239, 111, 111) @[RegMapper.scala 177:77] + node _T_10473 = and(_T_10471, _T_10472) @[RegMapper.scala 177:66] + node _T_10474 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10476 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10477 = and(_T_10474, _T_10476) @[RegMapper.scala 178:46] + node _T_10478 = bits(_T_8239, 111, 111) @[RegMapper.scala 178:77] + node _T_10479 = and(_T_10477, _T_10478) @[RegMapper.scala 178:66] + node _T_10480 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10481 = and(_T_10480, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10482 = bits(_T_7981, 112, 112) @[RegMapper.scala 175:77] + node _T_10483 = and(_T_10481, _T_10482) @[RegMapper.scala 175:66] + node _T_10484 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10486 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10487 = and(_T_10484, _T_10486) @[RegMapper.scala 176:46] + node _T_10488 = bits(_T_7981, 112, 112) @[RegMapper.scala 176:77] + node _T_10489 = and(_T_10487, _T_10488) @[RegMapper.scala 176:66] + node _T_10490 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10491 = and(_T_10490, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10492 = bits(_T_8239, 112, 112) @[RegMapper.scala 177:77] + node _T_10493 = and(_T_10491, _T_10492) @[RegMapper.scala 177:66] + node _T_10494 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10496 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10497 = and(_T_10494, _T_10496) @[RegMapper.scala 178:46] + node _T_10498 = bits(_T_8239, 112, 112) @[RegMapper.scala 178:77] + node _T_10499 = and(_T_10497, _T_10498) @[RegMapper.scala 178:66] + node _T_10500 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10501 = and(_T_10500, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10502 = bits(_T_7981, 113, 113) @[RegMapper.scala 175:77] + node _T_10503 = and(_T_10501, _T_10502) @[RegMapper.scala 175:66] + node _T_10504 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10506 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10507 = and(_T_10504, _T_10506) @[RegMapper.scala 176:46] + node _T_10508 = bits(_T_7981, 113, 113) @[RegMapper.scala 176:77] + node _T_10509 = and(_T_10507, _T_10508) @[RegMapper.scala 176:66] + node _T_10510 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10511 = and(_T_10510, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10512 = bits(_T_8239, 113, 113) @[RegMapper.scala 177:77] + node _T_10513 = and(_T_10511, _T_10512) @[RegMapper.scala 177:66] + node _T_10514 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10516 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10517 = and(_T_10514, _T_10516) @[RegMapper.scala 178:46] + node _T_10518 = bits(_T_8239, 113, 113) @[RegMapper.scala 178:77] + node _T_10519 = and(_T_10517, _T_10518) @[RegMapper.scala 178:66] + node _T_10520 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10521 = and(_T_10520, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10522 = bits(_T_7981, 114, 114) @[RegMapper.scala 175:77] + node _T_10523 = and(_T_10521, _T_10522) @[RegMapper.scala 175:66] + node _T_10524 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10526 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10527 = and(_T_10524, _T_10526) @[RegMapper.scala 176:46] + node _T_10528 = bits(_T_7981, 114, 114) @[RegMapper.scala 176:77] + node _T_10529 = and(_T_10527, _T_10528) @[RegMapper.scala 176:66] + node _T_10530 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10531 = and(_T_10530, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10532 = bits(_T_8239, 114, 114) @[RegMapper.scala 177:77] + node _T_10533 = and(_T_10531, _T_10532) @[RegMapper.scala 177:66] + node _T_10534 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10536 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10537 = and(_T_10534, _T_10536) @[RegMapper.scala 178:46] + node _T_10538 = bits(_T_8239, 114, 114) @[RegMapper.scala 178:77] + node _T_10539 = and(_T_10537, _T_10538) @[RegMapper.scala 178:66] + node _T_10540 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10541 = and(_T_10540, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10542 = bits(_T_7981, 115, 115) @[RegMapper.scala 175:77] + node _T_10543 = and(_T_10541, _T_10542) @[RegMapper.scala 175:66] + node _T_10544 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10546 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10547 = and(_T_10544, _T_10546) @[RegMapper.scala 176:46] + node _T_10548 = bits(_T_7981, 115, 115) @[RegMapper.scala 176:77] + node _T_10549 = and(_T_10547, _T_10548) @[RegMapper.scala 176:66] + node _T_10550 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10551 = and(_T_10550, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10552 = bits(_T_8239, 115, 115) @[RegMapper.scala 177:77] + node _T_10553 = and(_T_10551, _T_10552) @[RegMapper.scala 177:66] + node _T_10554 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10556 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10557 = and(_T_10554, _T_10556) @[RegMapper.scala 178:46] + node _T_10558 = bits(_T_8239, 115, 115) @[RegMapper.scala 178:77] + node _T_10559 = and(_T_10557, _T_10558) @[RegMapper.scala 178:66] + node _T_10560 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10561 = and(_T_10560, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10562 = bits(_T_7981, 116, 116) @[RegMapper.scala 175:77] + node _T_10563 = and(_T_10561, _T_10562) @[RegMapper.scala 175:66] + node _T_10564 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10566 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10567 = and(_T_10564, _T_10566) @[RegMapper.scala 176:46] + node _T_10568 = bits(_T_7981, 116, 116) @[RegMapper.scala 176:77] + node _T_10569 = and(_T_10567, _T_10568) @[RegMapper.scala 176:66] + node _T_10570 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10571 = and(_T_10570, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10572 = bits(_T_8239, 116, 116) @[RegMapper.scala 177:77] + node _T_10573 = and(_T_10571, _T_10572) @[RegMapper.scala 177:66] + node _T_10574 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10576 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10577 = and(_T_10574, _T_10576) @[RegMapper.scala 178:46] + node _T_10578 = bits(_T_8239, 116, 116) @[RegMapper.scala 178:77] + node _T_10579 = and(_T_10577, _T_10578) @[RegMapper.scala 178:66] + node _T_10580 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10581 = and(_T_10580, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10582 = bits(_T_7981, 117, 117) @[RegMapper.scala 175:77] + node _T_10583 = and(_T_10581, _T_10582) @[RegMapper.scala 175:66] + node _T_10584 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10586 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10587 = and(_T_10584, _T_10586) @[RegMapper.scala 176:46] + node _T_10588 = bits(_T_7981, 117, 117) @[RegMapper.scala 176:77] + node _T_10589 = and(_T_10587, _T_10588) @[RegMapper.scala 176:66] + node _T_10590 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10591 = and(_T_10590, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10592 = bits(_T_8239, 117, 117) @[RegMapper.scala 177:77] + node _T_10593 = and(_T_10591, _T_10592) @[RegMapper.scala 177:66] + node _T_10594 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10596 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10597 = and(_T_10594, _T_10596) @[RegMapper.scala 178:46] + node _T_10598 = bits(_T_8239, 117, 117) @[RegMapper.scala 178:77] + node _T_10599 = and(_T_10597, _T_10598) @[RegMapper.scala 178:66] + node _T_10600 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10601 = and(_T_10600, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10602 = bits(_T_7981, 118, 118) @[RegMapper.scala 175:77] + node _T_10603 = and(_T_10601, _T_10602) @[RegMapper.scala 175:66] + node _T_10604 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10606 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10607 = and(_T_10604, _T_10606) @[RegMapper.scala 176:46] + node _T_10608 = bits(_T_7981, 118, 118) @[RegMapper.scala 176:77] + node _T_10609 = and(_T_10607, _T_10608) @[RegMapper.scala 176:66] + node _T_10610 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10611 = and(_T_10610, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10612 = bits(_T_8239, 118, 118) @[RegMapper.scala 177:77] + node _T_10613 = and(_T_10611, _T_10612) @[RegMapper.scala 177:66] + node _T_10614 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10616 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10617 = and(_T_10614, _T_10616) @[RegMapper.scala 178:46] + node _T_10618 = bits(_T_8239, 118, 118) @[RegMapper.scala 178:77] + node _T_10619 = and(_T_10617, _T_10618) @[RegMapper.scala 178:66] + node _T_10620 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10621 = and(_T_10620, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10622 = bits(_T_7981, 119, 119) @[RegMapper.scala 175:77] + node _T_10623 = and(_T_10621, _T_10622) @[RegMapper.scala 175:66] + node _T_10624 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10626 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10627 = and(_T_10624, _T_10626) @[RegMapper.scala 176:46] + node _T_10628 = bits(_T_7981, 119, 119) @[RegMapper.scala 176:77] + node _T_10629 = and(_T_10627, _T_10628) @[RegMapper.scala 176:66] + node _T_10630 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10631 = and(_T_10630, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10632 = bits(_T_8239, 119, 119) @[RegMapper.scala 177:77] + node _T_10633 = and(_T_10631, _T_10632) @[RegMapper.scala 177:66] + node _T_10634 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10636 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10637 = and(_T_10634, _T_10636) @[RegMapper.scala 178:46] + node _T_10638 = bits(_T_8239, 119, 119) @[RegMapper.scala 178:77] + node _T_10639 = and(_T_10637, _T_10638) @[RegMapper.scala 178:66] + node _T_10640 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10641 = and(_T_10640, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10642 = bits(_T_7981, 120, 120) @[RegMapper.scala 175:77] + node _T_10643 = and(_T_10641, _T_10642) @[RegMapper.scala 175:66] + node _T_10644 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10646 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10647 = and(_T_10644, _T_10646) @[RegMapper.scala 176:46] + node _T_10648 = bits(_T_7981, 120, 120) @[RegMapper.scala 176:77] + node _T_10649 = and(_T_10647, _T_10648) @[RegMapper.scala 176:66] + node _T_10650 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10651 = and(_T_10650, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10652 = bits(_T_8239, 120, 120) @[RegMapper.scala 177:77] + node _T_10653 = and(_T_10651, _T_10652) @[RegMapper.scala 177:66] + node _T_10654 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10656 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10657 = and(_T_10654, _T_10656) @[RegMapper.scala 178:46] + node _T_10658 = bits(_T_8239, 120, 120) @[RegMapper.scala 178:77] + node _T_10659 = and(_T_10657, _T_10658) @[RegMapper.scala 178:66] + node _T_10660 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10661 = and(_T_10660, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10662 = bits(_T_7981, 121, 121) @[RegMapper.scala 175:77] + node _T_10663 = and(_T_10661, _T_10662) @[RegMapper.scala 175:66] + node _T_10664 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10666 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10667 = and(_T_10664, _T_10666) @[RegMapper.scala 176:46] + node _T_10668 = bits(_T_7981, 121, 121) @[RegMapper.scala 176:77] + node _T_10669 = and(_T_10667, _T_10668) @[RegMapper.scala 176:66] + node _T_10670 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10671 = and(_T_10670, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10672 = bits(_T_8239, 121, 121) @[RegMapper.scala 177:77] + node _T_10673 = and(_T_10671, _T_10672) @[RegMapper.scala 177:66] + node _T_10674 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10676 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10677 = and(_T_10674, _T_10676) @[RegMapper.scala 178:46] + node _T_10678 = bits(_T_8239, 121, 121) @[RegMapper.scala 178:77] + node _T_10679 = and(_T_10677, _T_10678) @[RegMapper.scala 178:66] + node _T_10680 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10681 = and(_T_10680, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10682 = bits(_T_7981, 122, 122) @[RegMapper.scala 175:77] + node _T_10683 = and(_T_10681, _T_10682) @[RegMapper.scala 175:66] + node _T_10684 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10686 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10687 = and(_T_10684, _T_10686) @[RegMapper.scala 176:46] + node _T_10688 = bits(_T_7981, 122, 122) @[RegMapper.scala 176:77] + node _T_10689 = and(_T_10687, _T_10688) @[RegMapper.scala 176:66] + node _T_10690 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10691 = and(_T_10690, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10692 = bits(_T_8239, 122, 122) @[RegMapper.scala 177:77] + node _T_10693 = and(_T_10691, _T_10692) @[RegMapper.scala 177:66] + node _T_10694 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10696 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10697 = and(_T_10694, _T_10696) @[RegMapper.scala 178:46] + node _T_10698 = bits(_T_8239, 122, 122) @[RegMapper.scala 178:77] + node _T_10699 = and(_T_10697, _T_10698) @[RegMapper.scala 178:66] + node _T_10700 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10701 = and(_T_10700, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10702 = bits(_T_7981, 123, 123) @[RegMapper.scala 175:77] + node _T_10703 = and(_T_10701, _T_10702) @[RegMapper.scala 175:66] + node _T_10704 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10706 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10707 = and(_T_10704, _T_10706) @[RegMapper.scala 176:46] + node _T_10708 = bits(_T_7981, 123, 123) @[RegMapper.scala 176:77] + node _T_10709 = and(_T_10707, _T_10708) @[RegMapper.scala 176:66] + node _T_10710 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10711 = and(_T_10710, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10712 = bits(_T_8239, 123, 123) @[RegMapper.scala 177:77] + node _T_10713 = and(_T_10711, _T_10712) @[RegMapper.scala 177:66] + node _T_10714 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10716 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10717 = and(_T_10714, _T_10716) @[RegMapper.scala 178:46] + node _T_10718 = bits(_T_8239, 123, 123) @[RegMapper.scala 178:77] + node _T_10719 = and(_T_10717, _T_10718) @[RegMapper.scala 178:66] + node _T_10720 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10721 = and(_T_10720, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10722 = bits(_T_7981, 124, 124) @[RegMapper.scala 175:77] + node _T_10723 = and(_T_10721, _T_10722) @[RegMapper.scala 175:66] + node _T_10724 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10726 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10727 = and(_T_10724, _T_10726) @[RegMapper.scala 176:46] + node _T_10728 = bits(_T_7981, 124, 124) @[RegMapper.scala 176:77] + node _T_10729 = and(_T_10727, _T_10728) @[RegMapper.scala 176:66] + node _T_10730 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10731 = and(_T_10730, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10732 = bits(_T_8239, 124, 124) @[RegMapper.scala 177:77] + node _T_10733 = and(_T_10731, _T_10732) @[RegMapper.scala 177:66] + node _T_10734 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10736 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10737 = and(_T_10734, _T_10736) @[RegMapper.scala 178:46] + node _T_10738 = bits(_T_8239, 124, 124) @[RegMapper.scala 178:77] + node _T_10739 = and(_T_10737, _T_10738) @[RegMapper.scala 178:66] + node _T_10740 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10741 = and(_T_10740, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10742 = bits(_T_7981, 125, 125) @[RegMapper.scala 175:77] + node _T_10743 = and(_T_10741, _T_10742) @[RegMapper.scala 175:66] + node _T_10744 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10746 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10747 = and(_T_10744, _T_10746) @[RegMapper.scala 176:46] + node _T_10748 = bits(_T_7981, 125, 125) @[RegMapper.scala 176:77] + node _T_10749 = and(_T_10747, _T_10748) @[RegMapper.scala 176:66] + node _T_10750 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10751 = and(_T_10750, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10752 = bits(_T_8239, 125, 125) @[RegMapper.scala 177:77] + node _T_10753 = and(_T_10751, _T_10752) @[RegMapper.scala 177:66] + node _T_10754 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10756 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10757 = and(_T_10754, _T_10756) @[RegMapper.scala 178:46] + node _T_10758 = bits(_T_8239, 125, 125) @[RegMapper.scala 178:77] + node _T_10759 = and(_T_10757, _T_10758) @[RegMapper.scala 178:66] + node _T_10760 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10761 = and(_T_10760, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10762 = bits(_T_7981, 126, 126) @[RegMapper.scala 175:77] + node _T_10763 = and(_T_10761, _T_10762) @[RegMapper.scala 175:66] + node _T_10764 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10766 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10767 = and(_T_10764, _T_10766) @[RegMapper.scala 176:46] + node _T_10768 = bits(_T_7981, 126, 126) @[RegMapper.scala 176:77] + node _T_10769 = and(_T_10767, _T_10768) @[RegMapper.scala 176:66] + node _T_10770 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10771 = and(_T_10770, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10772 = bits(_T_8239, 126, 126) @[RegMapper.scala 177:77] + node _T_10773 = and(_T_10771, _T_10772) @[RegMapper.scala 177:66] + node _T_10774 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10776 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10777 = and(_T_10774, _T_10776) @[RegMapper.scala 178:46] + node _T_10778 = bits(_T_8239, 126, 126) @[RegMapper.scala 178:77] + node _T_10779 = and(_T_10777, _T_10778) @[RegMapper.scala 178:66] + node _T_10780 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10781 = and(_T_10780, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10782 = bits(_T_7981, 127, 127) @[RegMapper.scala 175:77] + node _T_10783 = and(_T_10781, _T_10782) @[RegMapper.scala 175:66] + node _T_10784 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10786 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10787 = and(_T_10784, _T_10786) @[RegMapper.scala 176:46] + node _T_10788 = bits(_T_7981, 127, 127) @[RegMapper.scala 176:77] + node _T_10789 = and(_T_10787, _T_10788) @[RegMapper.scala 176:66] + node _T_10790 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10791 = and(_T_10790, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10792 = bits(_T_8239, 127, 127) @[RegMapper.scala 177:77] + node _T_10793 = and(_T_10791, _T_10792) @[RegMapper.scala 177:66] + node _T_10794 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10796 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10797 = and(_T_10794, _T_10796) @[RegMapper.scala 178:46] + node _T_10798 = bits(_T_8239, 127, 127) @[RegMapper.scala 178:77] + node _T_10799 = and(_T_10797, _T_10798) @[RegMapper.scala 178:66] + node _T_10800 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10801 = and(_T_10800, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10802 = bits(_T_7981, 128, 128) @[RegMapper.scala 175:77] + node _T_10803 = and(_T_10801, _T_10802) @[RegMapper.scala 175:66] + node _T_10804 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10806 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10807 = and(_T_10804, _T_10806) @[RegMapper.scala 176:46] + node _T_10808 = bits(_T_7981, 128, 128) @[RegMapper.scala 176:77] + node _T_10809 = and(_T_10807, _T_10808) @[RegMapper.scala 176:66] + node _T_10810 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10811 = and(_T_10810, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10812 = bits(_T_8239, 128, 128) @[RegMapper.scala 177:77] + node _T_10813 = and(_T_10811, _T_10812) @[RegMapper.scala 177:66] + node _T_10814 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10816 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10817 = and(_T_10814, _T_10816) @[RegMapper.scala 178:46] + node _T_10818 = bits(_T_8239, 128, 128) @[RegMapper.scala 178:77] + node _T_10819 = and(_T_10817, _T_10818) @[RegMapper.scala 178:66] + node _T_10820 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10821 = and(_T_10820, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10822 = bits(_T_7981, 129, 129) @[RegMapper.scala 175:77] + node _T_10823 = and(_T_10821, _T_10822) @[RegMapper.scala 175:66] + node _T_10824 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10826 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10827 = and(_T_10824, _T_10826) @[RegMapper.scala 176:46] + node _T_10828 = bits(_T_7981, 129, 129) @[RegMapper.scala 176:77] + node _T_10829 = and(_T_10827, _T_10828) @[RegMapper.scala 176:66] + node _T_10830 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10831 = and(_T_10830, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10832 = bits(_T_8239, 129, 129) @[RegMapper.scala 177:77] + node _T_10833 = and(_T_10831, _T_10832) @[RegMapper.scala 177:66] + node _T_10834 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10836 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10837 = and(_T_10834, _T_10836) @[RegMapper.scala 178:46] + node _T_10838 = bits(_T_8239, 129, 129) @[RegMapper.scala 178:77] + node _T_10839 = and(_T_10837, _T_10838) @[RegMapper.scala 178:66] + node _T_10840 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10841 = and(_T_10840, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10842 = bits(_T_7981, 130, 130) @[RegMapper.scala 175:77] + node _T_10843 = and(_T_10841, _T_10842) @[RegMapper.scala 175:66] + node _T_10844 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10846 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10847 = and(_T_10844, _T_10846) @[RegMapper.scala 176:46] + node _T_10848 = bits(_T_7981, 130, 130) @[RegMapper.scala 176:77] + node _T_10849 = and(_T_10847, _T_10848) @[RegMapper.scala 176:66] + node _T_10850 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10851 = and(_T_10850, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10852 = bits(_T_8239, 130, 130) @[RegMapper.scala 177:77] + node _T_10853 = and(_T_10851, _T_10852) @[RegMapper.scala 177:66] + node _T_10854 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10856 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10857 = and(_T_10854, _T_10856) @[RegMapper.scala 178:46] + node _T_10858 = bits(_T_8239, 130, 130) @[RegMapper.scala 178:77] + node _T_10859 = and(_T_10857, _T_10858) @[RegMapper.scala 178:66] + node _T_10860 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10861 = and(_T_10860, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10862 = bits(_T_7981, 131, 131) @[RegMapper.scala 175:77] + node _T_10863 = and(_T_10861, _T_10862) @[RegMapper.scala 175:66] + node _T_10864 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10866 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10867 = and(_T_10864, _T_10866) @[RegMapper.scala 176:46] + node _T_10868 = bits(_T_7981, 131, 131) @[RegMapper.scala 176:77] + node _T_10869 = and(_T_10867, _T_10868) @[RegMapper.scala 176:66] + node _T_10870 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10871 = and(_T_10870, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10872 = bits(_T_8239, 131, 131) @[RegMapper.scala 177:77] + node _T_10873 = and(_T_10871, _T_10872) @[RegMapper.scala 177:66] + node _T_10874 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10876 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10877 = and(_T_10874, _T_10876) @[RegMapper.scala 178:46] + node _T_10878 = bits(_T_8239, 131, 131) @[RegMapper.scala 178:77] + node _T_10879 = and(_T_10877, _T_10878) @[RegMapper.scala 178:66] + node _T_10880 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10881 = and(_T_10880, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10882 = bits(_T_7981, 132, 132) @[RegMapper.scala 175:77] + node _T_10883 = and(_T_10881, _T_10882) @[RegMapper.scala 175:66] + node _T_10884 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10886 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10887 = and(_T_10884, _T_10886) @[RegMapper.scala 176:46] + node _T_10888 = bits(_T_7981, 132, 132) @[RegMapper.scala 176:77] + node _T_10889 = and(_T_10887, _T_10888) @[RegMapper.scala 176:66] + node _T_10890 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10891 = and(_T_10890, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10892 = bits(_T_8239, 132, 132) @[RegMapper.scala 177:77] + node _T_10893 = and(_T_10891, _T_10892) @[RegMapper.scala 177:66] + node _T_10894 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10896 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10897 = and(_T_10894, _T_10896) @[RegMapper.scala 178:46] + node _T_10898 = bits(_T_8239, 132, 132) @[RegMapper.scala 178:77] + node _T_10899 = and(_T_10897, _T_10898) @[RegMapper.scala 178:66] + node _T_10900 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10901 = and(_T_10900, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10902 = bits(_T_7981, 133, 133) @[RegMapper.scala 175:77] + node _T_10903 = and(_T_10901, _T_10902) @[RegMapper.scala 175:66] + node _T_10904 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10906 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10907 = and(_T_10904, _T_10906) @[RegMapper.scala 176:46] + node _T_10908 = bits(_T_7981, 133, 133) @[RegMapper.scala 176:77] + node _T_10909 = and(_T_10907, _T_10908) @[RegMapper.scala 176:66] + node _T_10910 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10911 = and(_T_10910, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10912 = bits(_T_8239, 133, 133) @[RegMapper.scala 177:77] + node _T_10913 = and(_T_10911, _T_10912) @[RegMapper.scala 177:66] + node _T_10914 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10916 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10917 = and(_T_10914, _T_10916) @[RegMapper.scala 178:46] + node _T_10918 = bits(_T_8239, 133, 133) @[RegMapper.scala 178:77] + node _T_10919 = and(_T_10917, _T_10918) @[RegMapper.scala 178:66] + node _T_10920 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10921 = and(_T_10920, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10922 = bits(_T_7981, 134, 134) @[RegMapper.scala 175:77] + node _T_10923 = and(_T_10921, _T_10922) @[RegMapper.scala 175:66] + node _T_10924 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10926 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10927 = and(_T_10924, _T_10926) @[RegMapper.scala 176:46] + node _T_10928 = bits(_T_7981, 134, 134) @[RegMapper.scala 176:77] + node _T_10929 = and(_T_10927, _T_10928) @[RegMapper.scala 176:66] + node _T_10930 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10931 = and(_T_10930, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10932 = bits(_T_8239, 134, 134) @[RegMapper.scala 177:77] + node _T_10933 = and(_T_10931, _T_10932) @[RegMapper.scala 177:66] + node _T_10934 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10936 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10937 = and(_T_10934, _T_10936) @[RegMapper.scala 178:46] + node _T_10938 = bits(_T_8239, 134, 134) @[RegMapper.scala 178:77] + node _T_10939 = and(_T_10937, _T_10938) @[RegMapper.scala 178:66] + node _T_10940 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10941 = and(_T_10940, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10942 = bits(_T_7981, 135, 135) @[RegMapper.scala 175:77] + node _T_10943 = and(_T_10941, _T_10942) @[RegMapper.scala 175:66] + node _T_10944 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10946 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10947 = and(_T_10944, _T_10946) @[RegMapper.scala 176:46] + node _T_10948 = bits(_T_7981, 135, 135) @[RegMapper.scala 176:77] + node _T_10949 = and(_T_10947, _T_10948) @[RegMapper.scala 176:66] + node _T_10950 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10951 = and(_T_10950, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10952 = bits(_T_8239, 135, 135) @[RegMapper.scala 177:77] + node _T_10953 = and(_T_10951, _T_10952) @[RegMapper.scala 177:66] + node _T_10954 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10956 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10957 = and(_T_10954, _T_10956) @[RegMapper.scala 178:46] + node _T_10958 = bits(_T_8239, 135, 135) @[RegMapper.scala 178:77] + node _T_10959 = and(_T_10957, _T_10958) @[RegMapper.scala 178:66] + node _T_10960 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10961 = and(_T_10960, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10962 = bits(_T_7981, 136, 136) @[RegMapper.scala 175:77] + node _T_10963 = and(_T_10961, _T_10962) @[RegMapper.scala 175:66] + node _T_10964 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10966 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10967 = and(_T_10964, _T_10966) @[RegMapper.scala 176:46] + node _T_10968 = bits(_T_7981, 136, 136) @[RegMapper.scala 176:77] + node _T_10969 = and(_T_10967, _T_10968) @[RegMapper.scala 176:66] + node _T_10970 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10971 = and(_T_10970, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10972 = bits(_T_8239, 136, 136) @[RegMapper.scala 177:77] + node _T_10973 = and(_T_10971, _T_10972) @[RegMapper.scala 177:66] + node _T_10974 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10976 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10977 = and(_T_10974, _T_10976) @[RegMapper.scala 178:46] + node _T_10978 = bits(_T_8239, 136, 136) @[RegMapper.scala 178:77] + node _T_10979 = and(_T_10977, _T_10978) @[RegMapper.scala 178:66] + node _T_10980 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_10981 = and(_T_10980, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_10982 = bits(_T_7981, 137, 137) @[RegMapper.scala 175:77] + node _T_10983 = and(_T_10981, _T_10982) @[RegMapper.scala 175:66] + node _T_10984 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_10986 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_10987 = and(_T_10984, _T_10986) @[RegMapper.scala 176:46] + node _T_10988 = bits(_T_7981, 137, 137) @[RegMapper.scala 176:77] + node _T_10989 = and(_T_10987, _T_10988) @[RegMapper.scala 176:66] + node _T_10990 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_10991 = and(_T_10990, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_10992 = bits(_T_8239, 137, 137) @[RegMapper.scala 177:77] + node _T_10993 = and(_T_10991, _T_10992) @[RegMapper.scala 177:66] + node _T_10994 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_10996 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_10997 = and(_T_10994, _T_10996) @[RegMapper.scala 178:46] + node _T_10998 = bits(_T_8239, 137, 137) @[RegMapper.scala 178:77] + node _T_10999 = and(_T_10997, _T_10998) @[RegMapper.scala 178:66] + node _T_11000 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11001 = and(_T_11000, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11002 = bits(_T_7981, 138, 138) @[RegMapper.scala 175:77] + node _T_11003 = and(_T_11001, _T_11002) @[RegMapper.scala 175:66] + node _T_11004 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11006 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11007 = and(_T_11004, _T_11006) @[RegMapper.scala 176:46] + node _T_11008 = bits(_T_7981, 138, 138) @[RegMapper.scala 176:77] + node _T_11009 = and(_T_11007, _T_11008) @[RegMapper.scala 176:66] + node _T_11010 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11011 = and(_T_11010, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11012 = bits(_T_8239, 138, 138) @[RegMapper.scala 177:77] + node _T_11013 = and(_T_11011, _T_11012) @[RegMapper.scala 177:66] + node _T_11014 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11016 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11017 = and(_T_11014, _T_11016) @[RegMapper.scala 178:46] + node _T_11018 = bits(_T_8239, 138, 138) @[RegMapper.scala 178:77] + node _T_11019 = and(_T_11017, _T_11018) @[RegMapper.scala 178:66] + node _T_11020 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11021 = and(_T_11020, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11022 = bits(_T_7981, 139, 139) @[RegMapper.scala 175:77] + node _T_11023 = and(_T_11021, _T_11022) @[RegMapper.scala 175:66] + node _T_11024 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11026 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11027 = and(_T_11024, _T_11026) @[RegMapper.scala 176:46] + node _T_11028 = bits(_T_7981, 139, 139) @[RegMapper.scala 176:77] + node _T_11029 = and(_T_11027, _T_11028) @[RegMapper.scala 176:66] + node _T_11030 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11031 = and(_T_11030, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11032 = bits(_T_8239, 139, 139) @[RegMapper.scala 177:77] + node _T_11033 = and(_T_11031, _T_11032) @[RegMapper.scala 177:66] + node _T_11034 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11036 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11037 = and(_T_11034, _T_11036) @[RegMapper.scala 178:46] + node _T_11038 = bits(_T_8239, 139, 139) @[RegMapper.scala 178:77] + node _T_11039 = and(_T_11037, _T_11038) @[RegMapper.scala 178:66] + node _T_11040 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11041 = and(_T_11040, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11042 = bits(_T_7981, 140, 140) @[RegMapper.scala 175:77] + node _T_11043 = and(_T_11041, _T_11042) @[RegMapper.scala 175:66] + node _T_11044 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11046 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11047 = and(_T_11044, _T_11046) @[RegMapper.scala 176:46] + node _T_11048 = bits(_T_7981, 140, 140) @[RegMapper.scala 176:77] + node _T_11049 = and(_T_11047, _T_11048) @[RegMapper.scala 176:66] + node _T_11050 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11051 = and(_T_11050, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11052 = bits(_T_8239, 140, 140) @[RegMapper.scala 177:77] + node _T_11053 = and(_T_11051, _T_11052) @[RegMapper.scala 177:66] + node _T_11054 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11056 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11057 = and(_T_11054, _T_11056) @[RegMapper.scala 178:46] + node _T_11058 = bits(_T_8239, 140, 140) @[RegMapper.scala 178:77] + node _T_11059 = and(_T_11057, _T_11058) @[RegMapper.scala 178:66] + node _T_11060 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11061 = and(_T_11060, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11062 = bits(_T_7981, 141, 141) @[RegMapper.scala 175:77] + node _T_11063 = and(_T_11061, _T_11062) @[RegMapper.scala 175:66] + node _T_11064 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11066 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11067 = and(_T_11064, _T_11066) @[RegMapper.scala 176:46] + node _T_11068 = bits(_T_7981, 141, 141) @[RegMapper.scala 176:77] + node _T_11069 = and(_T_11067, _T_11068) @[RegMapper.scala 176:66] + node _T_11070 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11071 = and(_T_11070, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11072 = bits(_T_8239, 141, 141) @[RegMapper.scala 177:77] + node _T_11073 = and(_T_11071, _T_11072) @[RegMapper.scala 177:66] + node _T_11074 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11076 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11077 = and(_T_11074, _T_11076) @[RegMapper.scala 178:46] + node _T_11078 = bits(_T_8239, 141, 141) @[RegMapper.scala 178:77] + node _T_11079 = and(_T_11077, _T_11078) @[RegMapper.scala 178:66] + node _T_11080 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11081 = and(_T_11080, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11082 = bits(_T_7981, 142, 142) @[RegMapper.scala 175:77] + node _T_11083 = and(_T_11081, _T_11082) @[RegMapper.scala 175:66] + node _T_11084 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11086 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11087 = and(_T_11084, _T_11086) @[RegMapper.scala 176:46] + node _T_11088 = bits(_T_7981, 142, 142) @[RegMapper.scala 176:77] + node _T_11089 = and(_T_11087, _T_11088) @[RegMapper.scala 176:66] + node _T_11090 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11091 = and(_T_11090, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11092 = bits(_T_8239, 142, 142) @[RegMapper.scala 177:77] + node _T_11093 = and(_T_11091, _T_11092) @[RegMapper.scala 177:66] + node _T_11094 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11096 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11097 = and(_T_11094, _T_11096) @[RegMapper.scala 178:46] + node _T_11098 = bits(_T_8239, 142, 142) @[RegMapper.scala 178:77] + node _T_11099 = and(_T_11097, _T_11098) @[RegMapper.scala 178:66] + node _T_11100 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11101 = and(_T_11100, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11102 = bits(_T_7981, 143, 143) @[RegMapper.scala 175:77] + node _T_11103 = and(_T_11101, _T_11102) @[RegMapper.scala 175:66] + node _T_11104 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11106 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11107 = and(_T_11104, _T_11106) @[RegMapper.scala 176:46] + node _T_11108 = bits(_T_7981, 143, 143) @[RegMapper.scala 176:77] + node _T_11109 = and(_T_11107, _T_11108) @[RegMapper.scala 176:66] + node _T_11110 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11111 = and(_T_11110, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11112 = bits(_T_8239, 143, 143) @[RegMapper.scala 177:77] + node _T_11113 = and(_T_11111, _T_11112) @[RegMapper.scala 177:66] + node _T_11114 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11116 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11117 = and(_T_11114, _T_11116) @[RegMapper.scala 178:46] + node _T_11118 = bits(_T_8239, 143, 143) @[RegMapper.scala 178:77] + node _T_11119 = and(_T_11117, _T_11118) @[RegMapper.scala 178:66] + node _T_11120 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11121 = and(_T_11120, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11122 = bits(_T_7981, 144, 144) @[RegMapper.scala 175:77] + node _T_11123 = and(_T_11121, _T_11122) @[RegMapper.scala 175:66] + node _T_11124 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11126 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11127 = and(_T_11124, _T_11126) @[RegMapper.scala 176:46] + node _T_11128 = bits(_T_7981, 144, 144) @[RegMapper.scala 176:77] + node _T_11129 = and(_T_11127, _T_11128) @[RegMapper.scala 176:66] + node _T_11130 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11131 = and(_T_11130, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11132 = bits(_T_8239, 144, 144) @[RegMapper.scala 177:77] + node _T_11133 = and(_T_11131, _T_11132) @[RegMapper.scala 177:66] + node _T_11134 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11136 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11137 = and(_T_11134, _T_11136) @[RegMapper.scala 178:46] + node _T_11138 = bits(_T_8239, 144, 144) @[RegMapper.scala 178:77] + node _T_11139 = and(_T_11137, _T_11138) @[RegMapper.scala 178:66] + node _T_11140 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11141 = and(_T_11140, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11142 = bits(_T_7981, 145, 145) @[RegMapper.scala 175:77] + node _T_11143 = and(_T_11141, _T_11142) @[RegMapper.scala 175:66] + node _T_11144 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11146 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11147 = and(_T_11144, _T_11146) @[RegMapper.scala 176:46] + node _T_11148 = bits(_T_7981, 145, 145) @[RegMapper.scala 176:77] + node _T_11149 = and(_T_11147, _T_11148) @[RegMapper.scala 176:66] + node _T_11150 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11151 = and(_T_11150, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11152 = bits(_T_8239, 145, 145) @[RegMapper.scala 177:77] + node _T_11153 = and(_T_11151, _T_11152) @[RegMapper.scala 177:66] + node _T_11154 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11156 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11157 = and(_T_11154, _T_11156) @[RegMapper.scala 178:46] + node _T_11158 = bits(_T_8239, 145, 145) @[RegMapper.scala 178:77] + node _T_11159 = and(_T_11157, _T_11158) @[RegMapper.scala 178:66] + node _T_11160 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11161 = and(_T_11160, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11162 = bits(_T_7981, 146, 146) @[RegMapper.scala 175:77] + node _T_11163 = and(_T_11161, _T_11162) @[RegMapper.scala 175:66] + node _T_11164 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11166 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11167 = and(_T_11164, _T_11166) @[RegMapper.scala 176:46] + node _T_11168 = bits(_T_7981, 146, 146) @[RegMapper.scala 176:77] + node _T_11169 = and(_T_11167, _T_11168) @[RegMapper.scala 176:66] + node _T_11170 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11171 = and(_T_11170, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11172 = bits(_T_8239, 146, 146) @[RegMapper.scala 177:77] + node _T_11173 = and(_T_11171, _T_11172) @[RegMapper.scala 177:66] + node _T_11174 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11176 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11177 = and(_T_11174, _T_11176) @[RegMapper.scala 178:46] + node _T_11178 = bits(_T_8239, 146, 146) @[RegMapper.scala 178:77] + node _T_11179 = and(_T_11177, _T_11178) @[RegMapper.scala 178:66] + node _T_11180 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11181 = and(_T_11180, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11182 = bits(_T_7981, 147, 147) @[RegMapper.scala 175:77] + node _T_11183 = and(_T_11181, _T_11182) @[RegMapper.scala 175:66] + node _T_11184 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11186 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11187 = and(_T_11184, _T_11186) @[RegMapper.scala 176:46] + node _T_11188 = bits(_T_7981, 147, 147) @[RegMapper.scala 176:77] + node _T_11189 = and(_T_11187, _T_11188) @[RegMapper.scala 176:66] + node _T_11190 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11191 = and(_T_11190, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11192 = bits(_T_8239, 147, 147) @[RegMapper.scala 177:77] + node _T_11193 = and(_T_11191, _T_11192) @[RegMapper.scala 177:66] + node _T_11194 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11196 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11197 = and(_T_11194, _T_11196) @[RegMapper.scala 178:46] + node _T_11198 = bits(_T_8239, 147, 147) @[RegMapper.scala 178:77] + node _T_11199 = and(_T_11197, _T_11198) @[RegMapper.scala 178:66] + node _T_11200 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11201 = and(_T_11200, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11202 = bits(_T_7981, 148, 148) @[RegMapper.scala 175:77] + node _T_11203 = and(_T_11201, _T_11202) @[RegMapper.scala 175:66] + node _T_11204 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11206 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11207 = and(_T_11204, _T_11206) @[RegMapper.scala 176:46] + node _T_11208 = bits(_T_7981, 148, 148) @[RegMapper.scala 176:77] + node _T_11209 = and(_T_11207, _T_11208) @[RegMapper.scala 176:66] + node _T_11210 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11211 = and(_T_11210, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11212 = bits(_T_8239, 148, 148) @[RegMapper.scala 177:77] + node _T_11213 = and(_T_11211, _T_11212) @[RegMapper.scala 177:66] + node _T_11214 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11216 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11217 = and(_T_11214, _T_11216) @[RegMapper.scala 178:46] + node _T_11218 = bits(_T_8239, 148, 148) @[RegMapper.scala 178:77] + node _T_11219 = and(_T_11217, _T_11218) @[RegMapper.scala 178:66] + node _T_11220 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11221 = and(_T_11220, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11222 = bits(_T_7981, 149, 149) @[RegMapper.scala 175:77] + node _T_11223 = and(_T_11221, _T_11222) @[RegMapper.scala 175:66] + node _T_11224 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11226 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11227 = and(_T_11224, _T_11226) @[RegMapper.scala 176:46] + node _T_11228 = bits(_T_7981, 149, 149) @[RegMapper.scala 176:77] + node _T_11229 = and(_T_11227, _T_11228) @[RegMapper.scala 176:66] + node _T_11230 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11231 = and(_T_11230, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11232 = bits(_T_8239, 149, 149) @[RegMapper.scala 177:77] + node _T_11233 = and(_T_11231, _T_11232) @[RegMapper.scala 177:66] + node _T_11234 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11236 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11237 = and(_T_11234, _T_11236) @[RegMapper.scala 178:46] + node _T_11238 = bits(_T_8239, 149, 149) @[RegMapper.scala 178:77] + node _T_11239 = and(_T_11237, _T_11238) @[RegMapper.scala 178:66] + node _T_11240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11241 = and(_T_11240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11242 = bits(_T_7981, 150, 150) @[RegMapper.scala 175:77] + node _T_11243 = and(_T_11241, _T_11242) @[RegMapper.scala 175:66] + node _T_11244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11247 = and(_T_11244, _T_11246) @[RegMapper.scala 176:46] + node _T_11248 = bits(_T_7981, 150, 150) @[RegMapper.scala 176:77] + node _T_11249 = and(_T_11247, _T_11248) @[RegMapper.scala 176:66] + node _T_11250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11251 = and(_T_11250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11252 = bits(_T_8239, 150, 150) @[RegMapper.scala 177:77] + node _T_11253 = and(_T_11251, _T_11252) @[RegMapper.scala 177:66] + node _T_11254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11257 = and(_T_11254, _T_11256) @[RegMapper.scala 178:46] + node _T_11258 = bits(_T_8239, 150, 150) @[RegMapper.scala 178:77] + node _T_11259 = and(_T_11257, _T_11258) @[RegMapper.scala 178:66] + node _T_11260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11261 = and(_T_11260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11262 = bits(_T_7981, 151, 151) @[RegMapper.scala 175:77] + node _T_11263 = and(_T_11261, _T_11262) @[RegMapper.scala 175:66] + node _T_11264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11267 = and(_T_11264, _T_11266) @[RegMapper.scala 176:46] + node _T_11268 = bits(_T_7981, 151, 151) @[RegMapper.scala 176:77] + node _T_11269 = and(_T_11267, _T_11268) @[RegMapper.scala 176:66] + node _T_11270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11271 = and(_T_11270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11272 = bits(_T_8239, 151, 151) @[RegMapper.scala 177:77] + node _T_11273 = and(_T_11271, _T_11272) @[RegMapper.scala 177:66] + node _T_11274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11277 = and(_T_11274, _T_11276) @[RegMapper.scala 178:46] + node _T_11278 = bits(_T_8239, 151, 151) @[RegMapper.scala 178:77] + node _T_11279 = and(_T_11277, _T_11278) @[RegMapper.scala 178:66] + node _T_11280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11281 = and(_T_11280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11282 = bits(_T_7981, 152, 152) @[RegMapper.scala 175:77] + node _T_11283 = and(_T_11281, _T_11282) @[RegMapper.scala 175:66] + node _T_11284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11287 = and(_T_11284, _T_11286) @[RegMapper.scala 176:46] + node _T_11288 = bits(_T_7981, 152, 152) @[RegMapper.scala 176:77] + node _T_11289 = and(_T_11287, _T_11288) @[RegMapper.scala 176:66] + node _T_11290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11291 = and(_T_11290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11292 = bits(_T_8239, 152, 152) @[RegMapper.scala 177:77] + node _T_11293 = and(_T_11291, _T_11292) @[RegMapper.scala 177:66] + node _T_11294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11297 = and(_T_11294, _T_11296) @[RegMapper.scala 178:46] + node _T_11298 = bits(_T_8239, 152, 152) @[RegMapper.scala 178:77] + node _T_11299 = and(_T_11297, _T_11298) @[RegMapper.scala 178:66] + node _T_11300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11301 = and(_T_11300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11302 = bits(_T_7981, 153, 153) @[RegMapper.scala 175:77] + node _T_11303 = and(_T_11301, _T_11302) @[RegMapper.scala 175:66] + node _T_11304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11307 = and(_T_11304, _T_11306) @[RegMapper.scala 176:46] + node _T_11308 = bits(_T_7981, 153, 153) @[RegMapper.scala 176:77] + node _T_11309 = and(_T_11307, _T_11308) @[RegMapper.scala 176:66] + node _T_11310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11311 = and(_T_11310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11312 = bits(_T_8239, 153, 153) @[RegMapper.scala 177:77] + node _T_11313 = and(_T_11311, _T_11312) @[RegMapper.scala 177:66] + node _T_11314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11317 = and(_T_11314, _T_11316) @[RegMapper.scala 178:46] + node _T_11318 = bits(_T_8239, 153, 153) @[RegMapper.scala 178:77] + node _T_11319 = and(_T_11317, _T_11318) @[RegMapper.scala 178:66] + node _T_11320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11321 = and(_T_11320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11322 = bits(_T_7981, 154, 154) @[RegMapper.scala 175:77] + node _T_11323 = and(_T_11321, _T_11322) @[RegMapper.scala 175:66] + node _T_11324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11327 = and(_T_11324, _T_11326) @[RegMapper.scala 176:46] + node _T_11328 = bits(_T_7981, 154, 154) @[RegMapper.scala 176:77] + node _T_11329 = and(_T_11327, _T_11328) @[RegMapper.scala 176:66] + node _T_11330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11331 = and(_T_11330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11332 = bits(_T_8239, 154, 154) @[RegMapper.scala 177:77] + node _T_11333 = and(_T_11331, _T_11332) @[RegMapper.scala 177:66] + node _T_11334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11337 = and(_T_11334, _T_11336) @[RegMapper.scala 178:46] + node _T_11338 = bits(_T_8239, 154, 154) @[RegMapper.scala 178:77] + node _T_11339 = and(_T_11337, _T_11338) @[RegMapper.scala 178:66] + node _T_11340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11341 = and(_T_11340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11342 = bits(_T_7981, 155, 155) @[RegMapper.scala 175:77] + node _T_11343 = and(_T_11341, _T_11342) @[RegMapper.scala 175:66] + node _T_11344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11347 = and(_T_11344, _T_11346) @[RegMapper.scala 176:46] + node _T_11348 = bits(_T_7981, 155, 155) @[RegMapper.scala 176:77] + node _T_11349 = and(_T_11347, _T_11348) @[RegMapper.scala 176:66] + node _T_11350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11351 = and(_T_11350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11352 = bits(_T_8239, 155, 155) @[RegMapper.scala 177:77] + node _T_11353 = and(_T_11351, _T_11352) @[RegMapper.scala 177:66] + node _T_11354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11357 = and(_T_11354, _T_11356) @[RegMapper.scala 178:46] + node _T_11358 = bits(_T_8239, 155, 155) @[RegMapper.scala 178:77] + node _T_11359 = and(_T_11357, _T_11358) @[RegMapper.scala 178:66] + node _T_11360 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11361 = and(_T_11360, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11362 = bits(_T_7981, 156, 156) @[RegMapper.scala 175:77] + node _T_11363 = and(_T_11361, _T_11362) @[RegMapper.scala 175:66] + node _T_11364 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11366 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11367 = and(_T_11364, _T_11366) @[RegMapper.scala 176:46] + node _T_11368 = bits(_T_7981, 156, 156) @[RegMapper.scala 176:77] + node _T_11369 = and(_T_11367, _T_11368) @[RegMapper.scala 176:66] + node _T_11370 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11371 = and(_T_11370, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11372 = bits(_T_8239, 156, 156) @[RegMapper.scala 177:77] + node _T_11373 = and(_T_11371, _T_11372) @[RegMapper.scala 177:66] + node _T_11374 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11376 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11377 = and(_T_11374, _T_11376) @[RegMapper.scala 178:46] + node _T_11378 = bits(_T_8239, 156, 156) @[RegMapper.scala 178:77] + node _T_11379 = and(_T_11377, _T_11378) @[RegMapper.scala 178:66] + node _T_11380 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11381 = and(_T_11380, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11382 = bits(_T_7981, 157, 157) @[RegMapper.scala 175:77] + node _T_11383 = and(_T_11381, _T_11382) @[RegMapper.scala 175:66] + node _T_11384 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11386 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11387 = and(_T_11384, _T_11386) @[RegMapper.scala 176:46] + node _T_11388 = bits(_T_7981, 157, 157) @[RegMapper.scala 176:77] + node _T_11389 = and(_T_11387, _T_11388) @[RegMapper.scala 176:66] + node _T_11390 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11391 = and(_T_11390, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11392 = bits(_T_8239, 157, 157) @[RegMapper.scala 177:77] + node _T_11393 = and(_T_11391, _T_11392) @[RegMapper.scala 177:66] + node _T_11394 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11396 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11397 = and(_T_11394, _T_11396) @[RegMapper.scala 178:46] + node _T_11398 = bits(_T_8239, 157, 157) @[RegMapper.scala 178:77] + node _T_11399 = and(_T_11397, _T_11398) @[RegMapper.scala 178:66] + node _T_11400 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11401 = and(_T_11400, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11402 = bits(_T_7981, 158, 158) @[RegMapper.scala 175:77] + node _T_11403 = and(_T_11401, _T_11402) @[RegMapper.scala 175:66] + node _T_11404 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11406 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11407 = and(_T_11404, _T_11406) @[RegMapper.scala 176:46] + node _T_11408 = bits(_T_7981, 158, 158) @[RegMapper.scala 176:77] + node _T_11409 = and(_T_11407, _T_11408) @[RegMapper.scala 176:66] + node _T_11410 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11411 = and(_T_11410, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11412 = bits(_T_8239, 158, 158) @[RegMapper.scala 177:77] + node _T_11413 = and(_T_11411, _T_11412) @[RegMapper.scala 177:66] + node _T_11414 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11416 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11417 = and(_T_11414, _T_11416) @[RegMapper.scala 178:46] + node _T_11418 = bits(_T_8239, 158, 158) @[RegMapper.scala 178:77] + node _T_11419 = and(_T_11417, _T_11418) @[RegMapper.scala 178:66] + node _T_11420 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11421 = and(_T_11420, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11422 = bits(_T_7981, 159, 159) @[RegMapper.scala 175:77] + node _T_11423 = and(_T_11421, _T_11422) @[RegMapper.scala 175:66] + node _T_11424 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11426 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11427 = and(_T_11424, _T_11426) @[RegMapper.scala 176:46] + node _T_11428 = bits(_T_7981, 159, 159) @[RegMapper.scala 176:77] + node _T_11429 = and(_T_11427, _T_11428) @[RegMapper.scala 176:66] + node _T_11430 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11431 = and(_T_11430, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11432 = bits(_T_8239, 159, 159) @[RegMapper.scala 177:77] + node _T_11433 = and(_T_11431, _T_11432) @[RegMapper.scala 177:66] + node _T_11434 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11436 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11437 = and(_T_11434, _T_11436) @[RegMapper.scala 178:46] + node _T_11438 = bits(_T_8239, 159, 159) @[RegMapper.scala 178:77] + node _T_11439 = and(_T_11437, _T_11438) @[RegMapper.scala 178:66] + node _T_11440 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11441 = and(_T_11440, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11442 = bits(_T_7981, 160, 160) @[RegMapper.scala 175:77] + node _T_11443 = and(_T_11441, _T_11442) @[RegMapper.scala 175:66] + node _T_11444 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11446 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11447 = and(_T_11444, _T_11446) @[RegMapper.scala 176:46] + node _T_11448 = bits(_T_7981, 160, 160) @[RegMapper.scala 176:77] + node _T_11449 = and(_T_11447, _T_11448) @[RegMapper.scala 176:66] + node _T_11450 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11451 = and(_T_11450, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11452 = bits(_T_8239, 160, 160) @[RegMapper.scala 177:77] + node _T_11453 = and(_T_11451, _T_11452) @[RegMapper.scala 177:66] + node _T_11454 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11456 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11457 = and(_T_11454, _T_11456) @[RegMapper.scala 178:46] + node _T_11458 = bits(_T_8239, 160, 160) @[RegMapper.scala 178:77] + node _T_11459 = and(_T_11457, _T_11458) @[RegMapper.scala 178:66] + node _T_11460 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11461 = and(_T_11460, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11462 = bits(_T_7981, 161, 161) @[RegMapper.scala 175:77] + node _T_11463 = and(_T_11461, _T_11462) @[RegMapper.scala 175:66] + node _T_11464 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11466 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11467 = and(_T_11464, _T_11466) @[RegMapper.scala 176:46] + node _T_11468 = bits(_T_7981, 161, 161) @[RegMapper.scala 176:77] + node _T_11469 = and(_T_11467, _T_11468) @[RegMapper.scala 176:66] + node _T_11470 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11471 = and(_T_11470, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11472 = bits(_T_8239, 161, 161) @[RegMapper.scala 177:77] + node _T_11473 = and(_T_11471, _T_11472) @[RegMapper.scala 177:66] + node _T_11474 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11476 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11477 = and(_T_11474, _T_11476) @[RegMapper.scala 178:46] + node _T_11478 = bits(_T_8239, 161, 161) @[RegMapper.scala 178:77] + node _T_11479 = and(_T_11477, _T_11478) @[RegMapper.scala 178:66] + node _T_11480 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11481 = and(_T_11480, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11482 = bits(_T_7981, 162, 162) @[RegMapper.scala 175:77] + node _T_11483 = and(_T_11481, _T_11482) @[RegMapper.scala 175:66] + node _T_11484 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11486 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11487 = and(_T_11484, _T_11486) @[RegMapper.scala 176:46] + node _T_11488 = bits(_T_7981, 162, 162) @[RegMapper.scala 176:77] + node _T_11489 = and(_T_11487, _T_11488) @[RegMapper.scala 176:66] + node _T_11490 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11491 = and(_T_11490, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11492 = bits(_T_8239, 162, 162) @[RegMapper.scala 177:77] + node _T_11493 = and(_T_11491, _T_11492) @[RegMapper.scala 177:66] + node _T_11494 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11496 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11497 = and(_T_11494, _T_11496) @[RegMapper.scala 178:46] + node _T_11498 = bits(_T_8239, 162, 162) @[RegMapper.scala 178:77] + node _T_11499 = and(_T_11497, _T_11498) @[RegMapper.scala 178:66] + node _T_11500 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11501 = and(_T_11500, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11502 = bits(_T_7981, 163, 163) @[RegMapper.scala 175:77] + node _T_11503 = and(_T_11501, _T_11502) @[RegMapper.scala 175:66] + node _T_11504 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11506 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11507 = and(_T_11504, _T_11506) @[RegMapper.scala 176:46] + node _T_11508 = bits(_T_7981, 163, 163) @[RegMapper.scala 176:77] + node _T_11509 = and(_T_11507, _T_11508) @[RegMapper.scala 176:66] + node _T_11510 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11511 = and(_T_11510, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11512 = bits(_T_8239, 163, 163) @[RegMapper.scala 177:77] + node _T_11513 = and(_T_11511, _T_11512) @[RegMapper.scala 177:66] + node _T_11514 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11516 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11517 = and(_T_11514, _T_11516) @[RegMapper.scala 178:46] + node _T_11518 = bits(_T_8239, 163, 163) @[RegMapper.scala 178:77] + node _T_11519 = and(_T_11517, _T_11518) @[RegMapper.scala 178:66] + node _T_11520 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11521 = and(_T_11520, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11522 = bits(_T_7981, 164, 164) @[RegMapper.scala 175:77] + node _T_11523 = and(_T_11521, _T_11522) @[RegMapper.scala 175:66] + node _T_11524 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11526 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11527 = and(_T_11524, _T_11526) @[RegMapper.scala 176:46] + node _T_11528 = bits(_T_7981, 164, 164) @[RegMapper.scala 176:77] + node _T_11529 = and(_T_11527, _T_11528) @[RegMapper.scala 176:66] + node _T_11530 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11531 = and(_T_11530, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11532 = bits(_T_8239, 164, 164) @[RegMapper.scala 177:77] + node _T_11533 = and(_T_11531, _T_11532) @[RegMapper.scala 177:66] + node _T_11534 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11536 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11537 = and(_T_11534, _T_11536) @[RegMapper.scala 178:46] + node _T_11538 = bits(_T_8239, 164, 164) @[RegMapper.scala 178:77] + node _T_11539 = and(_T_11537, _T_11538) @[RegMapper.scala 178:66] + node _T_11540 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11541 = and(_T_11540, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11542 = bits(_T_7981, 165, 165) @[RegMapper.scala 175:77] + node _T_11543 = and(_T_11541, _T_11542) @[RegMapper.scala 175:66] + node _T_11544 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11546 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11547 = and(_T_11544, _T_11546) @[RegMapper.scala 176:46] + node _T_11548 = bits(_T_7981, 165, 165) @[RegMapper.scala 176:77] + node _T_11549 = and(_T_11547, _T_11548) @[RegMapper.scala 176:66] + node _T_11550 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11551 = and(_T_11550, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11552 = bits(_T_8239, 165, 165) @[RegMapper.scala 177:77] + node _T_11553 = and(_T_11551, _T_11552) @[RegMapper.scala 177:66] + node _T_11554 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11556 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11557 = and(_T_11554, _T_11556) @[RegMapper.scala 178:46] + node _T_11558 = bits(_T_8239, 165, 165) @[RegMapper.scala 178:77] + node _T_11559 = and(_T_11557, _T_11558) @[RegMapper.scala 178:66] + node _T_11560 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11561 = and(_T_11560, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11562 = bits(_T_7981, 166, 166) @[RegMapper.scala 175:77] + node _T_11563 = and(_T_11561, _T_11562) @[RegMapper.scala 175:66] + node _T_11564 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11566 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11567 = and(_T_11564, _T_11566) @[RegMapper.scala 176:46] + node _T_11568 = bits(_T_7981, 166, 166) @[RegMapper.scala 176:77] + node _T_11569 = and(_T_11567, _T_11568) @[RegMapper.scala 176:66] + node _T_11570 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11571 = and(_T_11570, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11572 = bits(_T_8239, 166, 166) @[RegMapper.scala 177:77] + node _T_11573 = and(_T_11571, _T_11572) @[RegMapper.scala 177:66] + node _T_11574 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11576 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11577 = and(_T_11574, _T_11576) @[RegMapper.scala 178:46] + node _T_11578 = bits(_T_8239, 166, 166) @[RegMapper.scala 178:77] + node _T_11579 = and(_T_11577, _T_11578) @[RegMapper.scala 178:66] + node _T_11580 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11581 = and(_T_11580, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11582 = bits(_T_7981, 167, 167) @[RegMapper.scala 175:77] + node _T_11583 = and(_T_11581, _T_11582) @[RegMapper.scala 175:66] + node _T_11584 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11586 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11587 = and(_T_11584, _T_11586) @[RegMapper.scala 176:46] + node _T_11588 = bits(_T_7981, 167, 167) @[RegMapper.scala 176:77] + node _T_11589 = and(_T_11587, _T_11588) @[RegMapper.scala 176:66] + node _T_11590 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11591 = and(_T_11590, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11592 = bits(_T_8239, 167, 167) @[RegMapper.scala 177:77] + node _T_11593 = and(_T_11591, _T_11592) @[RegMapper.scala 177:66] + node _T_11594 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11596 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11597 = and(_T_11594, _T_11596) @[RegMapper.scala 178:46] + node _T_11598 = bits(_T_8239, 167, 167) @[RegMapper.scala 178:77] + node _T_11599 = and(_T_11597, _T_11598) @[RegMapper.scala 178:66] + node _T_11600 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11601 = and(_T_11600, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11602 = bits(_T_7981, 168, 168) @[RegMapper.scala 175:77] + node _T_11603 = and(_T_11601, _T_11602) @[RegMapper.scala 175:66] + node _T_11604 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11606 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11607 = and(_T_11604, _T_11606) @[RegMapper.scala 176:46] + node _T_11608 = bits(_T_7981, 168, 168) @[RegMapper.scala 176:77] + node _T_11609 = and(_T_11607, _T_11608) @[RegMapper.scala 176:66] + node _T_11610 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11611 = and(_T_11610, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11612 = bits(_T_8239, 168, 168) @[RegMapper.scala 177:77] + node _T_11613 = and(_T_11611, _T_11612) @[RegMapper.scala 177:66] + node _T_11614 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11616 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11617 = and(_T_11614, _T_11616) @[RegMapper.scala 178:46] + node _T_11618 = bits(_T_8239, 168, 168) @[RegMapper.scala 178:77] + node _T_11619 = and(_T_11617, _T_11618) @[RegMapper.scala 178:66] + node _T_11620 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11621 = and(_T_11620, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11622 = bits(_T_7981, 169, 169) @[RegMapper.scala 175:77] + node _T_11623 = and(_T_11621, _T_11622) @[RegMapper.scala 175:66] + node _T_11624 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11626 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11627 = and(_T_11624, _T_11626) @[RegMapper.scala 176:46] + node _T_11628 = bits(_T_7981, 169, 169) @[RegMapper.scala 176:77] + node _T_11629 = and(_T_11627, _T_11628) @[RegMapper.scala 176:66] + node _T_11630 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11631 = and(_T_11630, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11632 = bits(_T_8239, 169, 169) @[RegMapper.scala 177:77] + node _T_11633 = and(_T_11631, _T_11632) @[RegMapper.scala 177:66] + node _T_11634 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11636 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11637 = and(_T_11634, _T_11636) @[RegMapper.scala 178:46] + node _T_11638 = bits(_T_8239, 169, 169) @[RegMapper.scala 178:77] + node _T_11639 = and(_T_11637, _T_11638) @[RegMapper.scala 178:66] + node _T_11640 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11641 = and(_T_11640, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11642 = bits(_T_7981, 170, 170) @[RegMapper.scala 175:77] + node _T_11643 = and(_T_11641, _T_11642) @[RegMapper.scala 175:66] + node _T_11644 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11646 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11647 = and(_T_11644, _T_11646) @[RegMapper.scala 176:46] + node _T_11648 = bits(_T_7981, 170, 170) @[RegMapper.scala 176:77] + node _T_11649 = and(_T_11647, _T_11648) @[RegMapper.scala 176:66] + node _T_11650 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11651 = and(_T_11650, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11652 = bits(_T_8239, 170, 170) @[RegMapper.scala 177:77] + node _T_11653 = and(_T_11651, _T_11652) @[RegMapper.scala 177:66] + node _T_11654 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11656 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11657 = and(_T_11654, _T_11656) @[RegMapper.scala 178:46] + node _T_11658 = bits(_T_8239, 170, 170) @[RegMapper.scala 178:77] + node _T_11659 = and(_T_11657, _T_11658) @[RegMapper.scala 178:66] + node _T_11660 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11661 = and(_T_11660, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11662 = bits(_T_7981, 171, 171) @[RegMapper.scala 175:77] + node _T_11663 = and(_T_11661, _T_11662) @[RegMapper.scala 175:66] + node _T_11664 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11666 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11667 = and(_T_11664, _T_11666) @[RegMapper.scala 176:46] + node _T_11668 = bits(_T_7981, 171, 171) @[RegMapper.scala 176:77] + node _T_11669 = and(_T_11667, _T_11668) @[RegMapper.scala 176:66] + node _T_11670 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11671 = and(_T_11670, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11672 = bits(_T_8239, 171, 171) @[RegMapper.scala 177:77] + node _T_11673 = and(_T_11671, _T_11672) @[RegMapper.scala 177:66] + node _T_11674 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11676 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11677 = and(_T_11674, _T_11676) @[RegMapper.scala 178:46] + node _T_11678 = bits(_T_8239, 171, 171) @[RegMapper.scala 178:77] + node _T_11679 = and(_T_11677, _T_11678) @[RegMapper.scala 178:66] + node _T_11680 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11681 = and(_T_11680, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11682 = bits(_T_7981, 172, 172) @[RegMapper.scala 175:77] + node _T_11683 = and(_T_11681, _T_11682) @[RegMapper.scala 175:66] + node _T_11684 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11686 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11687 = and(_T_11684, _T_11686) @[RegMapper.scala 176:46] + node _T_11688 = bits(_T_7981, 172, 172) @[RegMapper.scala 176:77] + node _T_11689 = and(_T_11687, _T_11688) @[RegMapper.scala 176:66] + node _T_11690 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11691 = and(_T_11690, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11692 = bits(_T_8239, 172, 172) @[RegMapper.scala 177:77] + node _T_11693 = and(_T_11691, _T_11692) @[RegMapper.scala 177:66] + node _T_11694 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11696 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11697 = and(_T_11694, _T_11696) @[RegMapper.scala 178:46] + node _T_11698 = bits(_T_8239, 172, 172) @[RegMapper.scala 178:77] + node _T_11699 = and(_T_11697, _T_11698) @[RegMapper.scala 178:66] + node _T_11700 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11701 = and(_T_11700, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11702 = bits(_T_7981, 173, 173) @[RegMapper.scala 175:77] + node _T_11703 = and(_T_11701, _T_11702) @[RegMapper.scala 175:66] + node _T_11704 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11706 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11707 = and(_T_11704, _T_11706) @[RegMapper.scala 176:46] + node _T_11708 = bits(_T_7981, 173, 173) @[RegMapper.scala 176:77] + node _T_11709 = and(_T_11707, _T_11708) @[RegMapper.scala 176:66] + node _T_11710 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11711 = and(_T_11710, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11712 = bits(_T_8239, 173, 173) @[RegMapper.scala 177:77] + node _T_11713 = and(_T_11711, _T_11712) @[RegMapper.scala 177:66] + node _T_11714 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11716 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11717 = and(_T_11714, _T_11716) @[RegMapper.scala 178:46] + node _T_11718 = bits(_T_8239, 173, 173) @[RegMapper.scala 178:77] + node _T_11719 = and(_T_11717, _T_11718) @[RegMapper.scala 178:66] + node _T_11720 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11721 = and(_T_11720, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11722 = bits(_T_7981, 174, 174) @[RegMapper.scala 175:77] + node _T_11723 = and(_T_11721, _T_11722) @[RegMapper.scala 175:66] + node _T_11724 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11726 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11727 = and(_T_11724, _T_11726) @[RegMapper.scala 176:46] + node _T_11728 = bits(_T_7981, 174, 174) @[RegMapper.scala 176:77] + node _T_11729 = and(_T_11727, _T_11728) @[RegMapper.scala 176:66] + node _T_11730 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11731 = and(_T_11730, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11732 = bits(_T_8239, 174, 174) @[RegMapper.scala 177:77] + node _T_11733 = and(_T_11731, _T_11732) @[RegMapper.scala 177:66] + node _T_11734 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11736 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11737 = and(_T_11734, _T_11736) @[RegMapper.scala 178:46] + node _T_11738 = bits(_T_8239, 174, 174) @[RegMapper.scala 178:77] + node _T_11739 = and(_T_11737, _T_11738) @[RegMapper.scala 178:66] + node _T_11740 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11741 = and(_T_11740, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11742 = bits(_T_7981, 175, 175) @[RegMapper.scala 175:77] + node _T_11743 = and(_T_11741, _T_11742) @[RegMapper.scala 175:66] + node _T_11744 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11746 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11747 = and(_T_11744, _T_11746) @[RegMapper.scala 176:46] + node _T_11748 = bits(_T_7981, 175, 175) @[RegMapper.scala 176:77] + node _T_11749 = and(_T_11747, _T_11748) @[RegMapper.scala 176:66] + node _T_11750 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11751 = and(_T_11750, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11752 = bits(_T_8239, 175, 175) @[RegMapper.scala 177:77] + node _T_11753 = and(_T_11751, _T_11752) @[RegMapper.scala 177:66] + node _T_11754 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11756 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11757 = and(_T_11754, _T_11756) @[RegMapper.scala 178:46] + node _T_11758 = bits(_T_8239, 175, 175) @[RegMapper.scala 178:77] + node _T_11759 = and(_T_11757, _T_11758) @[RegMapper.scala 178:66] + node _T_11760 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11761 = and(_T_11760, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11762 = bits(_T_7981, 176, 176) @[RegMapper.scala 175:77] + node _T_11763 = and(_T_11761, _T_11762) @[RegMapper.scala 175:66] + node _T_11764 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11766 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11767 = and(_T_11764, _T_11766) @[RegMapper.scala 176:46] + node _T_11768 = bits(_T_7981, 176, 176) @[RegMapper.scala 176:77] + node _T_11769 = and(_T_11767, _T_11768) @[RegMapper.scala 176:66] + node _T_11770 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11771 = and(_T_11770, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11772 = bits(_T_8239, 176, 176) @[RegMapper.scala 177:77] + node _T_11773 = and(_T_11771, _T_11772) @[RegMapper.scala 177:66] + node _T_11774 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11776 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11777 = and(_T_11774, _T_11776) @[RegMapper.scala 178:46] + node _T_11778 = bits(_T_8239, 176, 176) @[RegMapper.scala 178:77] + node _T_11779 = and(_T_11777, _T_11778) @[RegMapper.scala 178:66] + node _T_11780 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11781 = and(_T_11780, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11782 = bits(_T_7981, 177, 177) @[RegMapper.scala 175:77] + node _T_11783 = and(_T_11781, _T_11782) @[RegMapper.scala 175:66] + node _T_11784 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11786 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11787 = and(_T_11784, _T_11786) @[RegMapper.scala 176:46] + node _T_11788 = bits(_T_7981, 177, 177) @[RegMapper.scala 176:77] + node _T_11789 = and(_T_11787, _T_11788) @[RegMapper.scala 176:66] + node _T_11790 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11791 = and(_T_11790, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11792 = bits(_T_8239, 177, 177) @[RegMapper.scala 177:77] + node _T_11793 = and(_T_11791, _T_11792) @[RegMapper.scala 177:66] + node _T_11794 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11796 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11797 = and(_T_11794, _T_11796) @[RegMapper.scala 178:46] + node _T_11798 = bits(_T_8239, 177, 177) @[RegMapper.scala 178:77] + node _T_11799 = and(_T_11797, _T_11798) @[RegMapper.scala 178:66] + node _T_11800 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11801 = and(_T_11800, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11802 = bits(_T_7981, 178, 178) @[RegMapper.scala 175:77] + node _T_11803 = and(_T_11801, _T_11802) @[RegMapper.scala 175:66] + node _T_11804 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11806 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11807 = and(_T_11804, _T_11806) @[RegMapper.scala 176:46] + node _T_11808 = bits(_T_7981, 178, 178) @[RegMapper.scala 176:77] + node _T_11809 = and(_T_11807, _T_11808) @[RegMapper.scala 176:66] + node _T_11810 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11811 = and(_T_11810, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11812 = bits(_T_8239, 178, 178) @[RegMapper.scala 177:77] + node _T_11813 = and(_T_11811, _T_11812) @[RegMapper.scala 177:66] + node _T_11814 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11816 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11817 = and(_T_11814, _T_11816) @[RegMapper.scala 178:46] + node _T_11818 = bits(_T_8239, 178, 178) @[RegMapper.scala 178:77] + node _T_11819 = and(_T_11817, _T_11818) @[RegMapper.scala 178:66] + node _T_11820 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11821 = and(_T_11820, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11822 = bits(_T_7981, 179, 179) @[RegMapper.scala 175:77] + node _T_11823 = and(_T_11821, _T_11822) @[RegMapper.scala 175:66] + node _T_11824 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11826 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11827 = and(_T_11824, _T_11826) @[RegMapper.scala 176:46] + node _T_11828 = bits(_T_7981, 179, 179) @[RegMapper.scala 176:77] + node _T_11829 = and(_T_11827, _T_11828) @[RegMapper.scala 176:66] + node _T_11830 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11831 = and(_T_11830, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11832 = bits(_T_8239, 179, 179) @[RegMapper.scala 177:77] + node _T_11833 = and(_T_11831, _T_11832) @[RegMapper.scala 177:66] + node _T_11834 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11836 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11837 = and(_T_11834, _T_11836) @[RegMapper.scala 178:46] + node _T_11838 = bits(_T_8239, 179, 179) @[RegMapper.scala 178:77] + node _T_11839 = and(_T_11837, _T_11838) @[RegMapper.scala 178:66] + node _T_11840 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11841 = and(_T_11840, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11842 = bits(_T_7981, 180, 180) @[RegMapper.scala 175:77] + node _T_11843 = and(_T_11841, _T_11842) @[RegMapper.scala 175:66] + node _T_11844 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11846 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11847 = and(_T_11844, _T_11846) @[RegMapper.scala 176:46] + node _T_11848 = bits(_T_7981, 180, 180) @[RegMapper.scala 176:77] + node _T_11849 = and(_T_11847, _T_11848) @[RegMapper.scala 176:66] + node _T_11850 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11851 = and(_T_11850, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11852 = bits(_T_8239, 180, 180) @[RegMapper.scala 177:77] + node _T_11853 = and(_T_11851, _T_11852) @[RegMapper.scala 177:66] + node _T_11854 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11856 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11857 = and(_T_11854, _T_11856) @[RegMapper.scala 178:46] + node _T_11858 = bits(_T_8239, 180, 180) @[RegMapper.scala 178:77] + node _T_11859 = and(_T_11857, _T_11858) @[RegMapper.scala 178:66] + node _T_11860 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11861 = and(_T_11860, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11862 = bits(_T_7981, 181, 181) @[RegMapper.scala 175:77] + node _T_11863 = and(_T_11861, _T_11862) @[RegMapper.scala 175:66] + node _T_11864 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11866 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11867 = and(_T_11864, _T_11866) @[RegMapper.scala 176:46] + node _T_11868 = bits(_T_7981, 181, 181) @[RegMapper.scala 176:77] + node _T_11869 = and(_T_11867, _T_11868) @[RegMapper.scala 176:66] + node _T_11870 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11871 = and(_T_11870, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11872 = bits(_T_8239, 181, 181) @[RegMapper.scala 177:77] + node _T_11873 = and(_T_11871, _T_11872) @[RegMapper.scala 177:66] + node _T_11874 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11876 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11877 = and(_T_11874, _T_11876) @[RegMapper.scala 178:46] + node _T_11878 = bits(_T_8239, 181, 181) @[RegMapper.scala 178:77] + node _T_11879 = and(_T_11877, _T_11878) @[RegMapper.scala 178:66] + node _T_11880 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11881 = and(_T_11880, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11882 = bits(_T_7981, 182, 182) @[RegMapper.scala 175:77] + node _T_11883 = and(_T_11881, _T_11882) @[RegMapper.scala 175:66] + node _T_11884 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11886 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11887 = and(_T_11884, _T_11886) @[RegMapper.scala 176:46] + node _T_11888 = bits(_T_7981, 182, 182) @[RegMapper.scala 176:77] + node _T_11889 = and(_T_11887, _T_11888) @[RegMapper.scala 176:66] + node _T_11890 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11891 = and(_T_11890, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11892 = bits(_T_8239, 182, 182) @[RegMapper.scala 177:77] + node _T_11893 = and(_T_11891, _T_11892) @[RegMapper.scala 177:66] + node _T_11894 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11896 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11897 = and(_T_11894, _T_11896) @[RegMapper.scala 178:46] + node _T_11898 = bits(_T_8239, 182, 182) @[RegMapper.scala 178:77] + node _T_11899 = and(_T_11897, _T_11898) @[RegMapper.scala 178:66] + node _T_11900 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11901 = and(_T_11900, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11902 = bits(_T_7981, 183, 183) @[RegMapper.scala 175:77] + node _T_11903 = and(_T_11901, _T_11902) @[RegMapper.scala 175:66] + node _T_11904 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11906 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11907 = and(_T_11904, _T_11906) @[RegMapper.scala 176:46] + node _T_11908 = bits(_T_7981, 183, 183) @[RegMapper.scala 176:77] + node _T_11909 = and(_T_11907, _T_11908) @[RegMapper.scala 176:66] + node _T_11910 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11911 = and(_T_11910, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11912 = bits(_T_8239, 183, 183) @[RegMapper.scala 177:77] + node _T_11913 = and(_T_11911, _T_11912) @[RegMapper.scala 177:66] + node _T_11914 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11916 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11917 = and(_T_11914, _T_11916) @[RegMapper.scala 178:46] + node _T_11918 = bits(_T_8239, 183, 183) @[RegMapper.scala 178:77] + node _T_11919 = and(_T_11917, _T_11918) @[RegMapper.scala 178:66] + node _T_11920 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11921 = and(_T_11920, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11922 = bits(_T_7981, 184, 184) @[RegMapper.scala 175:77] + node _T_11923 = and(_T_11921, _T_11922) @[RegMapper.scala 175:66] + node _T_11924 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11926 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11927 = and(_T_11924, _T_11926) @[RegMapper.scala 176:46] + node _T_11928 = bits(_T_7981, 184, 184) @[RegMapper.scala 176:77] + node _T_11929 = and(_T_11927, _T_11928) @[RegMapper.scala 176:66] + node _T_11930 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11931 = and(_T_11930, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11932 = bits(_T_8239, 184, 184) @[RegMapper.scala 177:77] + node _T_11933 = and(_T_11931, _T_11932) @[RegMapper.scala 177:66] + node _T_11934 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11936 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11937 = and(_T_11934, _T_11936) @[RegMapper.scala 178:46] + node _T_11938 = bits(_T_8239, 184, 184) @[RegMapper.scala 178:77] + node _T_11939 = and(_T_11937, _T_11938) @[RegMapper.scala 178:66] + node _T_11940 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11941 = and(_T_11940, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11942 = bits(_T_7981, 185, 185) @[RegMapper.scala 175:77] + node _T_11943 = and(_T_11941, _T_11942) @[RegMapper.scala 175:66] + node _T_11944 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11946 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11947 = and(_T_11944, _T_11946) @[RegMapper.scala 176:46] + node _T_11948 = bits(_T_7981, 185, 185) @[RegMapper.scala 176:77] + node _T_11949 = and(_T_11947, _T_11948) @[RegMapper.scala 176:66] + node _T_11950 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11951 = and(_T_11950, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11952 = bits(_T_8239, 185, 185) @[RegMapper.scala 177:77] + node _T_11953 = and(_T_11951, _T_11952) @[RegMapper.scala 177:66] + node _T_11954 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11956 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11957 = and(_T_11954, _T_11956) @[RegMapper.scala 178:46] + node _T_11958 = bits(_T_8239, 185, 185) @[RegMapper.scala 178:77] + node _T_11959 = and(_T_11957, _T_11958) @[RegMapper.scala 178:66] + node _T_11960 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11961 = and(_T_11960, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11962 = bits(_T_7981, 186, 186) @[RegMapper.scala 175:77] + node _T_11963 = and(_T_11961, _T_11962) @[RegMapper.scala 175:66] + node _T_11964 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11966 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11967 = and(_T_11964, _T_11966) @[RegMapper.scala 176:46] + node _T_11968 = bits(_T_7981, 186, 186) @[RegMapper.scala 176:77] + node _T_11969 = and(_T_11967, _T_11968) @[RegMapper.scala 176:66] + node _T_11970 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11971 = and(_T_11970, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11972 = bits(_T_8239, 186, 186) @[RegMapper.scala 177:77] + node _T_11973 = and(_T_11971, _T_11972) @[RegMapper.scala 177:66] + node _T_11974 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11976 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11977 = and(_T_11974, _T_11976) @[RegMapper.scala 178:46] + node _T_11978 = bits(_T_8239, 186, 186) @[RegMapper.scala 178:77] + node _T_11979 = and(_T_11977, _T_11978) @[RegMapper.scala 178:66] + node _T_11980 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_11981 = and(_T_11980, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_11982 = bits(_T_7981, 187, 187) @[RegMapper.scala 175:77] + node _T_11983 = and(_T_11981, _T_11982) @[RegMapper.scala 175:66] + node _T_11984 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_11986 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_11987 = and(_T_11984, _T_11986) @[RegMapper.scala 176:46] + node _T_11988 = bits(_T_7981, 187, 187) @[RegMapper.scala 176:77] + node _T_11989 = and(_T_11987, _T_11988) @[RegMapper.scala 176:66] + node _T_11990 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_11991 = and(_T_11990, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_11992 = bits(_T_8239, 187, 187) @[RegMapper.scala 177:77] + node _T_11993 = and(_T_11991, _T_11992) @[RegMapper.scala 177:66] + node _T_11994 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_11996 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_11997 = and(_T_11994, _T_11996) @[RegMapper.scala 178:46] + node _T_11998 = bits(_T_8239, 187, 187) @[RegMapper.scala 178:77] + node _T_11999 = and(_T_11997, _T_11998) @[RegMapper.scala 178:66] + node _T_12000 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12001 = and(_T_12000, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12002 = bits(_T_7981, 188, 188) @[RegMapper.scala 175:77] + node _T_12003 = and(_T_12001, _T_12002) @[RegMapper.scala 175:66] + node _T_12004 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12006 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12007 = and(_T_12004, _T_12006) @[RegMapper.scala 176:46] + node _T_12008 = bits(_T_7981, 188, 188) @[RegMapper.scala 176:77] + node _T_12009 = and(_T_12007, _T_12008) @[RegMapper.scala 176:66] + node _T_12010 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12011 = and(_T_12010, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12012 = bits(_T_8239, 188, 188) @[RegMapper.scala 177:77] + node _T_12013 = and(_T_12011, _T_12012) @[RegMapper.scala 177:66] + node _T_12014 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12016 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12017 = and(_T_12014, _T_12016) @[RegMapper.scala 178:46] + node _T_12018 = bits(_T_8239, 188, 188) @[RegMapper.scala 178:77] + node _T_12019 = and(_T_12017, _T_12018) @[RegMapper.scala 178:66] + node _T_12020 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12021 = and(_T_12020, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12022 = bits(_T_7981, 189, 189) @[RegMapper.scala 175:77] + node _T_12023 = and(_T_12021, _T_12022) @[RegMapper.scala 175:66] + node _T_12024 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12026 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12027 = and(_T_12024, _T_12026) @[RegMapper.scala 176:46] + node _T_12028 = bits(_T_7981, 189, 189) @[RegMapper.scala 176:77] + node _T_12029 = and(_T_12027, _T_12028) @[RegMapper.scala 176:66] + node _T_12030 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12031 = and(_T_12030, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12032 = bits(_T_8239, 189, 189) @[RegMapper.scala 177:77] + node _T_12033 = and(_T_12031, _T_12032) @[RegMapper.scala 177:66] + node _T_12034 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12036 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12037 = and(_T_12034, _T_12036) @[RegMapper.scala 178:46] + node _T_12038 = bits(_T_8239, 189, 189) @[RegMapper.scala 178:77] + node _T_12039 = and(_T_12037, _T_12038) @[RegMapper.scala 178:66] + node _T_12040 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12041 = and(_T_12040, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12042 = bits(_T_7981, 190, 190) @[RegMapper.scala 175:77] + node _T_12043 = and(_T_12041, _T_12042) @[RegMapper.scala 175:66] + node _T_12044 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12046 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12047 = and(_T_12044, _T_12046) @[RegMapper.scala 176:46] + node _T_12048 = bits(_T_7981, 190, 190) @[RegMapper.scala 176:77] + node _T_12049 = and(_T_12047, _T_12048) @[RegMapper.scala 176:66] + node _T_12050 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12051 = and(_T_12050, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12052 = bits(_T_8239, 190, 190) @[RegMapper.scala 177:77] + node _T_12053 = and(_T_12051, _T_12052) @[RegMapper.scala 177:66] + node _T_12054 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12056 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12057 = and(_T_12054, _T_12056) @[RegMapper.scala 178:46] + node _T_12058 = bits(_T_8239, 190, 190) @[RegMapper.scala 178:77] + node _T_12059 = and(_T_12057, _T_12058) @[RegMapper.scala 178:66] + node _T_12060 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12061 = and(_T_12060, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12062 = bits(_T_7981, 191, 191) @[RegMapper.scala 175:77] + node _T_12063 = and(_T_12061, _T_12062) @[RegMapper.scala 175:66] + node _T_12064 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12066 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12067 = and(_T_12064, _T_12066) @[RegMapper.scala 176:46] + node _T_12068 = bits(_T_7981, 191, 191) @[RegMapper.scala 176:77] + node _T_12069 = and(_T_12067, _T_12068) @[RegMapper.scala 176:66] + node _T_12070 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12071 = and(_T_12070, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12072 = bits(_T_8239, 191, 191) @[RegMapper.scala 177:77] + node _T_12073 = and(_T_12071, _T_12072) @[RegMapper.scala 177:66] + node _T_12074 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12076 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12077 = and(_T_12074, _T_12076) @[RegMapper.scala 178:46] + node _T_12078 = bits(_T_8239, 191, 191) @[RegMapper.scala 178:77] + node _T_12079 = and(_T_12077, _T_12078) @[RegMapper.scala 178:66] + node _T_12080 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12081 = and(_T_12080, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12082 = bits(_T_7981, 192, 192) @[RegMapper.scala 175:77] + node _T_12083 = and(_T_12081, _T_12082) @[RegMapper.scala 175:66] + node _T_12084 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12086 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12087 = and(_T_12084, _T_12086) @[RegMapper.scala 176:46] + node _T_12088 = bits(_T_7981, 192, 192) @[RegMapper.scala 176:77] + node _T_12089 = and(_T_12087, _T_12088) @[RegMapper.scala 176:66] + node _T_12090 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12091 = and(_T_12090, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12092 = bits(_T_8239, 192, 192) @[RegMapper.scala 177:77] + node _T_12093 = and(_T_12091, _T_12092) @[RegMapper.scala 177:66] + node _T_12094 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12096 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12097 = and(_T_12094, _T_12096) @[RegMapper.scala 178:46] + node _T_12098 = bits(_T_8239, 192, 192) @[RegMapper.scala 178:77] + node _T_12099 = and(_T_12097, _T_12098) @[RegMapper.scala 178:66] + node _T_12100 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12101 = and(_T_12100, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12102 = bits(_T_7981, 193, 193) @[RegMapper.scala 175:77] + node _T_12103 = and(_T_12101, _T_12102) @[RegMapper.scala 175:66] + node _T_12104 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12106 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12107 = and(_T_12104, _T_12106) @[RegMapper.scala 176:46] + node _T_12108 = bits(_T_7981, 193, 193) @[RegMapper.scala 176:77] + node _T_12109 = and(_T_12107, _T_12108) @[RegMapper.scala 176:66] + node _T_12110 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12111 = and(_T_12110, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12112 = bits(_T_8239, 193, 193) @[RegMapper.scala 177:77] + node _T_12113 = and(_T_12111, _T_12112) @[RegMapper.scala 177:66] + node _T_12114 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12116 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12117 = and(_T_12114, _T_12116) @[RegMapper.scala 178:46] + node _T_12118 = bits(_T_8239, 193, 193) @[RegMapper.scala 178:77] + node _T_12119 = and(_T_12117, _T_12118) @[RegMapper.scala 178:66] + node _T_12120 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12121 = and(_T_12120, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12122 = bits(_T_7981, 194, 194) @[RegMapper.scala 175:77] + node _T_12123 = and(_T_12121, _T_12122) @[RegMapper.scala 175:66] + node _T_12124 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12126 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12127 = and(_T_12124, _T_12126) @[RegMapper.scala 176:46] + node _T_12128 = bits(_T_7981, 194, 194) @[RegMapper.scala 176:77] + node _T_12129 = and(_T_12127, _T_12128) @[RegMapper.scala 176:66] + node _T_12130 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12131 = and(_T_12130, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12132 = bits(_T_8239, 194, 194) @[RegMapper.scala 177:77] + node _T_12133 = and(_T_12131, _T_12132) @[RegMapper.scala 177:66] + node _T_12134 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12136 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12137 = and(_T_12134, _T_12136) @[RegMapper.scala 178:46] + node _T_12138 = bits(_T_8239, 194, 194) @[RegMapper.scala 178:77] + node _T_12139 = and(_T_12137, _T_12138) @[RegMapper.scala 178:66] + node _T_12140 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12141 = and(_T_12140, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12142 = bits(_T_7981, 195, 195) @[RegMapper.scala 175:77] + node _T_12143 = and(_T_12141, _T_12142) @[RegMapper.scala 175:66] + node _T_12144 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12146 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12147 = and(_T_12144, _T_12146) @[RegMapper.scala 176:46] + node _T_12148 = bits(_T_7981, 195, 195) @[RegMapper.scala 176:77] + node _T_12149 = and(_T_12147, _T_12148) @[RegMapper.scala 176:66] + node _T_12150 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12151 = and(_T_12150, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12152 = bits(_T_8239, 195, 195) @[RegMapper.scala 177:77] + node _T_12153 = and(_T_12151, _T_12152) @[RegMapper.scala 177:66] + node _T_12154 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12156 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12157 = and(_T_12154, _T_12156) @[RegMapper.scala 178:46] + node _T_12158 = bits(_T_8239, 195, 195) @[RegMapper.scala 178:77] + node _T_12159 = and(_T_12157, _T_12158) @[RegMapper.scala 178:66] + node _T_12160 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12161 = and(_T_12160, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12162 = bits(_T_7981, 196, 196) @[RegMapper.scala 175:77] + node _T_12163 = and(_T_12161, _T_12162) @[RegMapper.scala 175:66] + node _T_12164 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12166 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12167 = and(_T_12164, _T_12166) @[RegMapper.scala 176:46] + node _T_12168 = bits(_T_7981, 196, 196) @[RegMapper.scala 176:77] + node _T_12169 = and(_T_12167, _T_12168) @[RegMapper.scala 176:66] + node _T_12170 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12171 = and(_T_12170, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12172 = bits(_T_8239, 196, 196) @[RegMapper.scala 177:77] + node _T_12173 = and(_T_12171, _T_12172) @[RegMapper.scala 177:66] + node _T_12174 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12176 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12177 = and(_T_12174, _T_12176) @[RegMapper.scala 178:46] + node _T_12178 = bits(_T_8239, 196, 196) @[RegMapper.scala 178:77] + node _T_12179 = and(_T_12177, _T_12178) @[RegMapper.scala 178:66] + node _T_12180 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12181 = and(_T_12180, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12182 = bits(_T_7981, 197, 197) @[RegMapper.scala 175:77] + node _T_12183 = and(_T_12181, _T_12182) @[RegMapper.scala 175:66] + node _T_12184 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12186 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12187 = and(_T_12184, _T_12186) @[RegMapper.scala 176:46] + node _T_12188 = bits(_T_7981, 197, 197) @[RegMapper.scala 176:77] + node _T_12189 = and(_T_12187, _T_12188) @[RegMapper.scala 176:66] + node _T_12190 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12191 = and(_T_12190, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12192 = bits(_T_8239, 197, 197) @[RegMapper.scala 177:77] + node _T_12193 = and(_T_12191, _T_12192) @[RegMapper.scala 177:66] + node _T_12194 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12196 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12197 = and(_T_12194, _T_12196) @[RegMapper.scala 178:46] + node _T_12198 = bits(_T_8239, 197, 197) @[RegMapper.scala 178:77] + node _T_12199 = and(_T_12197, _T_12198) @[RegMapper.scala 178:66] + node _T_12200 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12201 = and(_T_12200, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12202 = bits(_T_7981, 198, 198) @[RegMapper.scala 175:77] + node _T_12203 = and(_T_12201, _T_12202) @[RegMapper.scala 175:66] + node _T_12204 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12206 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12207 = and(_T_12204, _T_12206) @[RegMapper.scala 176:46] + node _T_12208 = bits(_T_7981, 198, 198) @[RegMapper.scala 176:77] + node _T_12209 = and(_T_12207, _T_12208) @[RegMapper.scala 176:66] + node _T_12210 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12211 = and(_T_12210, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12212 = bits(_T_8239, 198, 198) @[RegMapper.scala 177:77] + node _T_12213 = and(_T_12211, _T_12212) @[RegMapper.scala 177:66] + node _T_12214 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12216 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12217 = and(_T_12214, _T_12216) @[RegMapper.scala 178:46] + node _T_12218 = bits(_T_8239, 198, 198) @[RegMapper.scala 178:77] + node _T_12219 = and(_T_12217, _T_12218) @[RegMapper.scala 178:66] + node _T_12220 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12221 = and(_T_12220, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12222 = bits(_T_7981, 199, 199) @[RegMapper.scala 175:77] + node _T_12223 = and(_T_12221, _T_12222) @[RegMapper.scala 175:66] + node _T_12224 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12226 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12227 = and(_T_12224, _T_12226) @[RegMapper.scala 176:46] + node _T_12228 = bits(_T_7981, 199, 199) @[RegMapper.scala 176:77] + node _T_12229 = and(_T_12227, _T_12228) @[RegMapper.scala 176:66] + node _T_12230 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12231 = and(_T_12230, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12232 = bits(_T_8239, 199, 199) @[RegMapper.scala 177:77] + node _T_12233 = and(_T_12231, _T_12232) @[RegMapper.scala 177:66] + node _T_12234 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12236 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12237 = and(_T_12234, _T_12236) @[RegMapper.scala 178:46] + node _T_12238 = bits(_T_8239, 199, 199) @[RegMapper.scala 178:77] + node _T_12239 = and(_T_12237, _T_12238) @[RegMapper.scala 178:66] + node _T_12240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12241 = and(_T_12240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12242 = bits(_T_7981, 200, 200) @[RegMapper.scala 175:77] + node _T_12243 = and(_T_12241, _T_12242) @[RegMapper.scala 175:66] + node _T_12244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12247 = and(_T_12244, _T_12246) @[RegMapper.scala 176:46] + node _T_12248 = bits(_T_7981, 200, 200) @[RegMapper.scala 176:77] + node _T_12249 = and(_T_12247, _T_12248) @[RegMapper.scala 176:66] + node _T_12250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12251 = and(_T_12250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12252 = bits(_T_8239, 200, 200) @[RegMapper.scala 177:77] + node _T_12253 = and(_T_12251, _T_12252) @[RegMapper.scala 177:66] + node _T_12254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12257 = and(_T_12254, _T_12256) @[RegMapper.scala 178:46] + node _T_12258 = bits(_T_8239, 200, 200) @[RegMapper.scala 178:77] + node _T_12259 = and(_T_12257, _T_12258) @[RegMapper.scala 178:66] + node _T_12260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12261 = and(_T_12260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12262 = bits(_T_7981, 201, 201) @[RegMapper.scala 175:77] + node _T_12263 = and(_T_12261, _T_12262) @[RegMapper.scala 175:66] + node _T_12264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12267 = and(_T_12264, _T_12266) @[RegMapper.scala 176:46] + node _T_12268 = bits(_T_7981, 201, 201) @[RegMapper.scala 176:77] + node _T_12269 = and(_T_12267, _T_12268) @[RegMapper.scala 176:66] + node _T_12270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12271 = and(_T_12270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12272 = bits(_T_8239, 201, 201) @[RegMapper.scala 177:77] + node _T_12273 = and(_T_12271, _T_12272) @[RegMapper.scala 177:66] + node _T_12274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12277 = and(_T_12274, _T_12276) @[RegMapper.scala 178:46] + node _T_12278 = bits(_T_8239, 201, 201) @[RegMapper.scala 178:77] + node _T_12279 = and(_T_12277, _T_12278) @[RegMapper.scala 178:66] + node _T_12280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12281 = and(_T_12280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12282 = bits(_T_7981, 202, 202) @[RegMapper.scala 175:77] + node _T_12283 = and(_T_12281, _T_12282) @[RegMapper.scala 175:66] + node _T_12284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12287 = and(_T_12284, _T_12286) @[RegMapper.scala 176:46] + node _T_12288 = bits(_T_7981, 202, 202) @[RegMapper.scala 176:77] + node _T_12289 = and(_T_12287, _T_12288) @[RegMapper.scala 176:66] + node _T_12290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12291 = and(_T_12290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12292 = bits(_T_8239, 202, 202) @[RegMapper.scala 177:77] + node _T_12293 = and(_T_12291, _T_12292) @[RegMapper.scala 177:66] + node _T_12294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12297 = and(_T_12294, _T_12296) @[RegMapper.scala 178:46] + node _T_12298 = bits(_T_8239, 202, 202) @[RegMapper.scala 178:77] + node _T_12299 = and(_T_12297, _T_12298) @[RegMapper.scala 178:66] + node _T_12300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12301 = and(_T_12300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12302 = bits(_T_7981, 203, 203) @[RegMapper.scala 175:77] + node _T_12303 = and(_T_12301, _T_12302) @[RegMapper.scala 175:66] + node _T_12304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12307 = and(_T_12304, _T_12306) @[RegMapper.scala 176:46] + node _T_12308 = bits(_T_7981, 203, 203) @[RegMapper.scala 176:77] + node _T_12309 = and(_T_12307, _T_12308) @[RegMapper.scala 176:66] + node _T_12310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12311 = and(_T_12310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12312 = bits(_T_8239, 203, 203) @[RegMapper.scala 177:77] + node _T_12313 = and(_T_12311, _T_12312) @[RegMapper.scala 177:66] + node _T_12314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12317 = and(_T_12314, _T_12316) @[RegMapper.scala 178:46] + node _T_12318 = bits(_T_8239, 203, 203) @[RegMapper.scala 178:77] + node _T_12319 = and(_T_12317, _T_12318) @[RegMapper.scala 178:66] + node _T_12320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12321 = and(_T_12320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12322 = bits(_T_7981, 204, 204) @[RegMapper.scala 175:77] + node _T_12323 = and(_T_12321, _T_12322) @[RegMapper.scala 175:66] + node _T_12324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12327 = and(_T_12324, _T_12326) @[RegMapper.scala 176:46] + node _T_12328 = bits(_T_7981, 204, 204) @[RegMapper.scala 176:77] + node _T_12329 = and(_T_12327, _T_12328) @[RegMapper.scala 176:66] + node _T_12330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12331 = and(_T_12330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12332 = bits(_T_8239, 204, 204) @[RegMapper.scala 177:77] + node _T_12333 = and(_T_12331, _T_12332) @[RegMapper.scala 177:66] + node _T_12334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12337 = and(_T_12334, _T_12336) @[RegMapper.scala 178:46] + node _T_12338 = bits(_T_8239, 204, 204) @[RegMapper.scala 178:77] + node _T_12339 = and(_T_12337, _T_12338) @[RegMapper.scala 178:66] + node _T_12340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12341 = and(_T_12340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12342 = bits(_T_7981, 205, 205) @[RegMapper.scala 175:77] + node _T_12343 = and(_T_12341, _T_12342) @[RegMapper.scala 175:66] + node _T_12344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12347 = and(_T_12344, _T_12346) @[RegMapper.scala 176:46] + node _T_12348 = bits(_T_7981, 205, 205) @[RegMapper.scala 176:77] + node _T_12349 = and(_T_12347, _T_12348) @[RegMapper.scala 176:66] + node _T_12350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12351 = and(_T_12350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12352 = bits(_T_8239, 205, 205) @[RegMapper.scala 177:77] + node _T_12353 = and(_T_12351, _T_12352) @[RegMapper.scala 177:66] + node _T_12354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12357 = and(_T_12354, _T_12356) @[RegMapper.scala 178:46] + node _T_12358 = bits(_T_8239, 205, 205) @[RegMapper.scala 178:77] + node _T_12359 = and(_T_12357, _T_12358) @[RegMapper.scala 178:66] + node _T_12360 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12361 = and(_T_12360, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12362 = bits(_T_7981, 206, 206) @[RegMapper.scala 175:77] + node _T_12363 = and(_T_12361, _T_12362) @[RegMapper.scala 175:66] + node _T_12364 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12366 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12367 = and(_T_12364, _T_12366) @[RegMapper.scala 176:46] + node _T_12368 = bits(_T_7981, 206, 206) @[RegMapper.scala 176:77] + node _T_12369 = and(_T_12367, _T_12368) @[RegMapper.scala 176:66] + node _T_12370 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12371 = and(_T_12370, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12372 = bits(_T_8239, 206, 206) @[RegMapper.scala 177:77] + node _T_12373 = and(_T_12371, _T_12372) @[RegMapper.scala 177:66] + node _T_12374 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12376 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12377 = and(_T_12374, _T_12376) @[RegMapper.scala 178:46] + node _T_12378 = bits(_T_8239, 206, 206) @[RegMapper.scala 178:77] + node _T_12379 = and(_T_12377, _T_12378) @[RegMapper.scala 178:66] + node _T_12380 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12381 = and(_T_12380, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12382 = bits(_T_7981, 207, 207) @[RegMapper.scala 175:77] + node _T_12383 = and(_T_12381, _T_12382) @[RegMapper.scala 175:66] + node _T_12384 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12386 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12387 = and(_T_12384, _T_12386) @[RegMapper.scala 176:46] + node _T_12388 = bits(_T_7981, 207, 207) @[RegMapper.scala 176:77] + node _T_12389 = and(_T_12387, _T_12388) @[RegMapper.scala 176:66] + node _T_12390 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12391 = and(_T_12390, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12392 = bits(_T_8239, 207, 207) @[RegMapper.scala 177:77] + node _T_12393 = and(_T_12391, _T_12392) @[RegMapper.scala 177:66] + node _T_12394 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12396 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12397 = and(_T_12394, _T_12396) @[RegMapper.scala 178:46] + node _T_12398 = bits(_T_8239, 207, 207) @[RegMapper.scala 178:77] + node _T_12399 = and(_T_12397, _T_12398) @[RegMapper.scala 178:66] + node _T_12400 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12401 = and(_T_12400, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12402 = bits(_T_7981, 208, 208) @[RegMapper.scala 175:77] + node _T_12403 = and(_T_12401, _T_12402) @[RegMapper.scala 175:66] + node _T_12404 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12406 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12407 = and(_T_12404, _T_12406) @[RegMapper.scala 176:46] + node _T_12408 = bits(_T_7981, 208, 208) @[RegMapper.scala 176:77] + node _T_12409 = and(_T_12407, _T_12408) @[RegMapper.scala 176:66] + node _T_12410 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12411 = and(_T_12410, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12412 = bits(_T_8239, 208, 208) @[RegMapper.scala 177:77] + node _T_12413 = and(_T_12411, _T_12412) @[RegMapper.scala 177:66] + node _T_12414 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12416 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12417 = and(_T_12414, _T_12416) @[RegMapper.scala 178:46] + node _T_12418 = bits(_T_8239, 208, 208) @[RegMapper.scala 178:77] + node _T_12419 = and(_T_12417, _T_12418) @[RegMapper.scala 178:66] + node _T_12420 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12421 = and(_T_12420, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12422 = bits(_T_7981, 209, 209) @[RegMapper.scala 175:77] + node _T_12423 = and(_T_12421, _T_12422) @[RegMapper.scala 175:66] + node _T_12424 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12426 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12427 = and(_T_12424, _T_12426) @[RegMapper.scala 176:46] + node _T_12428 = bits(_T_7981, 209, 209) @[RegMapper.scala 176:77] + node _T_12429 = and(_T_12427, _T_12428) @[RegMapper.scala 176:66] + node _T_12430 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12431 = and(_T_12430, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12432 = bits(_T_8239, 209, 209) @[RegMapper.scala 177:77] + node _T_12433 = and(_T_12431, _T_12432) @[RegMapper.scala 177:66] + node _T_12434 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12436 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12437 = and(_T_12434, _T_12436) @[RegMapper.scala 178:46] + node _T_12438 = bits(_T_8239, 209, 209) @[RegMapper.scala 178:77] + node _T_12439 = and(_T_12437, _T_12438) @[RegMapper.scala 178:66] + node _T_12440 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12441 = and(_T_12440, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12442 = bits(_T_7981, 210, 210) @[RegMapper.scala 175:77] + node _T_12443 = and(_T_12441, _T_12442) @[RegMapper.scala 175:66] + node _T_12444 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12446 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12447 = and(_T_12444, _T_12446) @[RegMapper.scala 176:46] + node _T_12448 = bits(_T_7981, 210, 210) @[RegMapper.scala 176:77] + node _T_12449 = and(_T_12447, _T_12448) @[RegMapper.scala 176:66] + node _T_12450 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12451 = and(_T_12450, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12452 = bits(_T_8239, 210, 210) @[RegMapper.scala 177:77] + node _T_12453 = and(_T_12451, _T_12452) @[RegMapper.scala 177:66] + node _T_12454 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12456 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12457 = and(_T_12454, _T_12456) @[RegMapper.scala 178:46] + node _T_12458 = bits(_T_8239, 210, 210) @[RegMapper.scala 178:77] + node _T_12459 = and(_T_12457, _T_12458) @[RegMapper.scala 178:66] + node _T_12460 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12461 = and(_T_12460, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12462 = bits(_T_7981, 211, 211) @[RegMapper.scala 175:77] + node _T_12463 = and(_T_12461, _T_12462) @[RegMapper.scala 175:66] + node _T_12464 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12466 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12467 = and(_T_12464, _T_12466) @[RegMapper.scala 176:46] + node _T_12468 = bits(_T_7981, 211, 211) @[RegMapper.scala 176:77] + node _T_12469 = and(_T_12467, _T_12468) @[RegMapper.scala 176:66] + node _T_12470 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12471 = and(_T_12470, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12472 = bits(_T_8239, 211, 211) @[RegMapper.scala 177:77] + node _T_12473 = and(_T_12471, _T_12472) @[RegMapper.scala 177:66] + node _T_12474 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12476 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12477 = and(_T_12474, _T_12476) @[RegMapper.scala 178:46] + node _T_12478 = bits(_T_8239, 211, 211) @[RegMapper.scala 178:77] + node _T_12479 = and(_T_12477, _T_12478) @[RegMapper.scala 178:66] + node _T_12480 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12481 = and(_T_12480, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12482 = bits(_T_7981, 212, 212) @[RegMapper.scala 175:77] + node _T_12483 = and(_T_12481, _T_12482) @[RegMapper.scala 175:66] + node _T_12484 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12486 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12487 = and(_T_12484, _T_12486) @[RegMapper.scala 176:46] + node _T_12488 = bits(_T_7981, 212, 212) @[RegMapper.scala 176:77] + node _T_12489 = and(_T_12487, _T_12488) @[RegMapper.scala 176:66] + node _T_12490 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12491 = and(_T_12490, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12492 = bits(_T_8239, 212, 212) @[RegMapper.scala 177:77] + node _T_12493 = and(_T_12491, _T_12492) @[RegMapper.scala 177:66] + node _T_12494 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12496 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12497 = and(_T_12494, _T_12496) @[RegMapper.scala 178:46] + node _T_12498 = bits(_T_8239, 212, 212) @[RegMapper.scala 178:77] + node _T_12499 = and(_T_12497, _T_12498) @[RegMapper.scala 178:66] + node _T_12500 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12501 = and(_T_12500, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12502 = bits(_T_7981, 213, 213) @[RegMapper.scala 175:77] + node _T_12503 = and(_T_12501, _T_12502) @[RegMapper.scala 175:66] + node _T_12504 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12506 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12507 = and(_T_12504, _T_12506) @[RegMapper.scala 176:46] + node _T_12508 = bits(_T_7981, 213, 213) @[RegMapper.scala 176:77] + node _T_12509 = and(_T_12507, _T_12508) @[RegMapper.scala 176:66] + node _T_12510 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12511 = and(_T_12510, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12512 = bits(_T_8239, 213, 213) @[RegMapper.scala 177:77] + node _T_12513 = and(_T_12511, _T_12512) @[RegMapper.scala 177:66] + node _T_12514 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12516 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12517 = and(_T_12514, _T_12516) @[RegMapper.scala 178:46] + node _T_12518 = bits(_T_8239, 213, 213) @[RegMapper.scala 178:77] + node _T_12519 = and(_T_12517, _T_12518) @[RegMapper.scala 178:66] + node _T_12520 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12521 = and(_T_12520, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12522 = bits(_T_7981, 214, 214) @[RegMapper.scala 175:77] + node _T_12523 = and(_T_12521, _T_12522) @[RegMapper.scala 175:66] + node _T_12524 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12526 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12527 = and(_T_12524, _T_12526) @[RegMapper.scala 176:46] + node _T_12528 = bits(_T_7981, 214, 214) @[RegMapper.scala 176:77] + node _T_12529 = and(_T_12527, _T_12528) @[RegMapper.scala 176:66] + node _T_12530 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12531 = and(_T_12530, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12532 = bits(_T_8239, 214, 214) @[RegMapper.scala 177:77] + node _T_12533 = and(_T_12531, _T_12532) @[RegMapper.scala 177:66] + node _T_12534 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12536 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12537 = and(_T_12534, _T_12536) @[RegMapper.scala 178:46] + node _T_12538 = bits(_T_8239, 214, 214) @[RegMapper.scala 178:77] + node _T_12539 = and(_T_12537, _T_12538) @[RegMapper.scala 178:66] + node _T_12540 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12541 = and(_T_12540, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12542 = bits(_T_7981, 215, 215) @[RegMapper.scala 175:77] + node _T_12543 = and(_T_12541, _T_12542) @[RegMapper.scala 175:66] + node _T_12544 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12546 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12547 = and(_T_12544, _T_12546) @[RegMapper.scala 176:46] + node _T_12548 = bits(_T_7981, 215, 215) @[RegMapper.scala 176:77] + node _T_12549 = and(_T_12547, _T_12548) @[RegMapper.scala 176:66] + node _T_12550 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12551 = and(_T_12550, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12552 = bits(_T_8239, 215, 215) @[RegMapper.scala 177:77] + node _T_12553 = and(_T_12551, _T_12552) @[RegMapper.scala 177:66] + node _T_12554 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12556 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12557 = and(_T_12554, _T_12556) @[RegMapper.scala 178:46] + node _T_12558 = bits(_T_8239, 215, 215) @[RegMapper.scala 178:77] + node _T_12559 = and(_T_12557, _T_12558) @[RegMapper.scala 178:66] + node _T_12560 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12561 = and(_T_12560, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12562 = bits(_T_7981, 216, 216) @[RegMapper.scala 175:77] + node _T_12563 = and(_T_12561, _T_12562) @[RegMapper.scala 175:66] + node _T_12564 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12566 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12567 = and(_T_12564, _T_12566) @[RegMapper.scala 176:46] + node _T_12568 = bits(_T_7981, 216, 216) @[RegMapper.scala 176:77] + node _T_12569 = and(_T_12567, _T_12568) @[RegMapper.scala 176:66] + node _T_12570 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12571 = and(_T_12570, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12572 = bits(_T_8239, 216, 216) @[RegMapper.scala 177:77] + node _T_12573 = and(_T_12571, _T_12572) @[RegMapper.scala 177:66] + node _T_12574 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12576 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12577 = and(_T_12574, _T_12576) @[RegMapper.scala 178:46] + node _T_12578 = bits(_T_8239, 216, 216) @[RegMapper.scala 178:77] + node _T_12579 = and(_T_12577, _T_12578) @[RegMapper.scala 178:66] + node _T_12580 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12581 = and(_T_12580, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12582 = bits(_T_7981, 217, 217) @[RegMapper.scala 175:77] + node _T_12583 = and(_T_12581, _T_12582) @[RegMapper.scala 175:66] + node _T_12584 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12586 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12587 = and(_T_12584, _T_12586) @[RegMapper.scala 176:46] + node _T_12588 = bits(_T_7981, 217, 217) @[RegMapper.scala 176:77] + node _T_12589 = and(_T_12587, _T_12588) @[RegMapper.scala 176:66] + node _T_12590 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12591 = and(_T_12590, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12592 = bits(_T_8239, 217, 217) @[RegMapper.scala 177:77] + node _T_12593 = and(_T_12591, _T_12592) @[RegMapper.scala 177:66] + node _T_12594 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12596 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12597 = and(_T_12594, _T_12596) @[RegMapper.scala 178:46] + node _T_12598 = bits(_T_8239, 217, 217) @[RegMapper.scala 178:77] + node _T_12599 = and(_T_12597, _T_12598) @[RegMapper.scala 178:66] + node _T_12600 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12601 = and(_T_12600, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12602 = bits(_T_7981, 218, 218) @[RegMapper.scala 175:77] + node _T_12603 = and(_T_12601, _T_12602) @[RegMapper.scala 175:66] + node _T_12604 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12606 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12607 = and(_T_12604, _T_12606) @[RegMapper.scala 176:46] + node _T_12608 = bits(_T_7981, 218, 218) @[RegMapper.scala 176:77] + node _T_12609 = and(_T_12607, _T_12608) @[RegMapper.scala 176:66] + node _T_12610 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12611 = and(_T_12610, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12612 = bits(_T_8239, 218, 218) @[RegMapper.scala 177:77] + node _T_12613 = and(_T_12611, _T_12612) @[RegMapper.scala 177:66] + node _T_12614 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12616 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12617 = and(_T_12614, _T_12616) @[RegMapper.scala 178:46] + node _T_12618 = bits(_T_8239, 218, 218) @[RegMapper.scala 178:77] + node _T_12619 = and(_T_12617, _T_12618) @[RegMapper.scala 178:66] + node _T_12620 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12621 = and(_T_12620, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12622 = bits(_T_7981, 219, 219) @[RegMapper.scala 175:77] + node _T_12623 = and(_T_12621, _T_12622) @[RegMapper.scala 175:66] + node _T_12624 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12626 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12627 = and(_T_12624, _T_12626) @[RegMapper.scala 176:46] + node _T_12628 = bits(_T_7981, 219, 219) @[RegMapper.scala 176:77] + node _T_12629 = and(_T_12627, _T_12628) @[RegMapper.scala 176:66] + node _T_12630 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12631 = and(_T_12630, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12632 = bits(_T_8239, 219, 219) @[RegMapper.scala 177:77] + node _T_12633 = and(_T_12631, _T_12632) @[RegMapper.scala 177:66] + node _T_12634 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12636 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12637 = and(_T_12634, _T_12636) @[RegMapper.scala 178:46] + node _T_12638 = bits(_T_8239, 219, 219) @[RegMapper.scala 178:77] + node _T_12639 = and(_T_12637, _T_12638) @[RegMapper.scala 178:66] + node _T_12640 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12641 = and(_T_12640, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12642 = bits(_T_7981, 220, 220) @[RegMapper.scala 175:77] + node _T_12643 = and(_T_12641, _T_12642) @[RegMapper.scala 175:66] + node _T_12644 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12646 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12647 = and(_T_12644, _T_12646) @[RegMapper.scala 176:46] + node _T_12648 = bits(_T_7981, 220, 220) @[RegMapper.scala 176:77] + node _T_12649 = and(_T_12647, _T_12648) @[RegMapper.scala 176:66] + node _T_12650 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12651 = and(_T_12650, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12652 = bits(_T_8239, 220, 220) @[RegMapper.scala 177:77] + node _T_12653 = and(_T_12651, _T_12652) @[RegMapper.scala 177:66] + node _T_12654 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12656 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12657 = and(_T_12654, _T_12656) @[RegMapper.scala 178:46] + node _T_12658 = bits(_T_8239, 220, 220) @[RegMapper.scala 178:77] + node _T_12659 = and(_T_12657, _T_12658) @[RegMapper.scala 178:66] + node _T_12660 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12661 = and(_T_12660, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12662 = bits(_T_7981, 221, 221) @[RegMapper.scala 175:77] + node _T_12663 = and(_T_12661, _T_12662) @[RegMapper.scala 175:66] + node _T_12664 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12666 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12667 = and(_T_12664, _T_12666) @[RegMapper.scala 176:46] + node _T_12668 = bits(_T_7981, 221, 221) @[RegMapper.scala 176:77] + node _T_12669 = and(_T_12667, _T_12668) @[RegMapper.scala 176:66] + node _T_12670 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12671 = and(_T_12670, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12672 = bits(_T_8239, 221, 221) @[RegMapper.scala 177:77] + node _T_12673 = and(_T_12671, _T_12672) @[RegMapper.scala 177:66] + node _T_12674 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12676 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12677 = and(_T_12674, _T_12676) @[RegMapper.scala 178:46] + node _T_12678 = bits(_T_8239, 221, 221) @[RegMapper.scala 178:77] + node _T_12679 = and(_T_12677, _T_12678) @[RegMapper.scala 178:66] + node _T_12680 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12681 = and(_T_12680, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12682 = bits(_T_7981, 222, 222) @[RegMapper.scala 175:77] + node _T_12683 = and(_T_12681, _T_12682) @[RegMapper.scala 175:66] + node _T_12684 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12686 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12687 = and(_T_12684, _T_12686) @[RegMapper.scala 176:46] + node _T_12688 = bits(_T_7981, 222, 222) @[RegMapper.scala 176:77] + node _T_12689 = and(_T_12687, _T_12688) @[RegMapper.scala 176:66] + node _T_12690 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12691 = and(_T_12690, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12692 = bits(_T_8239, 222, 222) @[RegMapper.scala 177:77] + node _T_12693 = and(_T_12691, _T_12692) @[RegMapper.scala 177:66] + node _T_12694 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12696 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12697 = and(_T_12694, _T_12696) @[RegMapper.scala 178:46] + node _T_12698 = bits(_T_8239, 222, 222) @[RegMapper.scala 178:77] + node _T_12699 = and(_T_12697, _T_12698) @[RegMapper.scala 178:66] + node _T_12700 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12701 = and(_T_12700, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12702 = bits(_T_7981, 223, 223) @[RegMapper.scala 175:77] + node _T_12703 = and(_T_12701, _T_12702) @[RegMapper.scala 175:66] + node _T_12704 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12706 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12707 = and(_T_12704, _T_12706) @[RegMapper.scala 176:46] + node _T_12708 = bits(_T_7981, 223, 223) @[RegMapper.scala 176:77] + node _T_12709 = and(_T_12707, _T_12708) @[RegMapper.scala 176:66] + node _T_12710 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12711 = and(_T_12710, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12712 = bits(_T_8239, 223, 223) @[RegMapper.scala 177:77] + node _T_12713 = and(_T_12711, _T_12712) @[RegMapper.scala 177:66] + node _T_12714 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12716 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12717 = and(_T_12714, _T_12716) @[RegMapper.scala 178:46] + node _T_12718 = bits(_T_8239, 223, 223) @[RegMapper.scala 178:77] + node _T_12719 = and(_T_12717, _T_12718) @[RegMapper.scala 178:66] + node _T_12720 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12721 = and(_T_12720, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12722 = bits(_T_7981, 224, 224) @[RegMapper.scala 175:77] + node _T_12723 = and(_T_12721, _T_12722) @[RegMapper.scala 175:66] + node _T_12724 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12726 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12727 = and(_T_12724, _T_12726) @[RegMapper.scala 176:46] + node _T_12728 = bits(_T_7981, 224, 224) @[RegMapper.scala 176:77] + node _T_12729 = and(_T_12727, _T_12728) @[RegMapper.scala 176:66] + node _T_12730 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12731 = and(_T_12730, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12732 = bits(_T_8239, 224, 224) @[RegMapper.scala 177:77] + node _T_12733 = and(_T_12731, _T_12732) @[RegMapper.scala 177:66] + node _T_12734 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12736 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12737 = and(_T_12734, _T_12736) @[RegMapper.scala 178:46] + node _T_12738 = bits(_T_8239, 224, 224) @[RegMapper.scala 178:77] + node _T_12739 = and(_T_12737, _T_12738) @[RegMapper.scala 178:66] + node _T_12740 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12741 = and(_T_12740, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12742 = bits(_T_7981, 225, 225) @[RegMapper.scala 175:77] + node _T_12743 = and(_T_12741, _T_12742) @[RegMapper.scala 175:66] + node _T_12744 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12746 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12747 = and(_T_12744, _T_12746) @[RegMapper.scala 176:46] + node _T_12748 = bits(_T_7981, 225, 225) @[RegMapper.scala 176:77] + node _T_12749 = and(_T_12747, _T_12748) @[RegMapper.scala 176:66] + node _T_12750 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12751 = and(_T_12750, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12752 = bits(_T_8239, 225, 225) @[RegMapper.scala 177:77] + node _T_12753 = and(_T_12751, _T_12752) @[RegMapper.scala 177:66] + node _T_12754 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12756 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12757 = and(_T_12754, _T_12756) @[RegMapper.scala 178:46] + node _T_12758 = bits(_T_8239, 225, 225) @[RegMapper.scala 178:77] + node _T_12759 = and(_T_12757, _T_12758) @[RegMapper.scala 178:66] + node _T_12760 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12761 = and(_T_12760, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12762 = bits(_T_7981, 226, 226) @[RegMapper.scala 175:77] + node _T_12763 = and(_T_12761, _T_12762) @[RegMapper.scala 175:66] + node _T_12764 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12766 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12767 = and(_T_12764, _T_12766) @[RegMapper.scala 176:46] + node _T_12768 = bits(_T_7981, 226, 226) @[RegMapper.scala 176:77] + node _T_12769 = and(_T_12767, _T_12768) @[RegMapper.scala 176:66] + node _T_12770 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12771 = and(_T_12770, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12772 = bits(_T_8239, 226, 226) @[RegMapper.scala 177:77] + node _T_12773 = and(_T_12771, _T_12772) @[RegMapper.scala 177:66] + node _T_12774 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12776 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12777 = and(_T_12774, _T_12776) @[RegMapper.scala 178:46] + node _T_12778 = bits(_T_8239, 226, 226) @[RegMapper.scala 178:77] + node _T_12779 = and(_T_12777, _T_12778) @[RegMapper.scala 178:66] + node _T_12780 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12781 = and(_T_12780, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12782 = bits(_T_7981, 227, 227) @[RegMapper.scala 175:77] + node _T_12783 = and(_T_12781, _T_12782) @[RegMapper.scala 175:66] + node _T_12784 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12786 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12787 = and(_T_12784, _T_12786) @[RegMapper.scala 176:46] + node _T_12788 = bits(_T_7981, 227, 227) @[RegMapper.scala 176:77] + node _T_12789 = and(_T_12787, _T_12788) @[RegMapper.scala 176:66] + node _T_12790 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12791 = and(_T_12790, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12792 = bits(_T_8239, 227, 227) @[RegMapper.scala 177:77] + node _T_12793 = and(_T_12791, _T_12792) @[RegMapper.scala 177:66] + node _T_12794 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12796 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12797 = and(_T_12794, _T_12796) @[RegMapper.scala 178:46] + node _T_12798 = bits(_T_8239, 227, 227) @[RegMapper.scala 178:77] + node _T_12799 = and(_T_12797, _T_12798) @[RegMapper.scala 178:66] + node _T_12800 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12801 = and(_T_12800, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12802 = bits(_T_7981, 228, 228) @[RegMapper.scala 175:77] + node _T_12803 = and(_T_12801, _T_12802) @[RegMapper.scala 175:66] + node _T_12804 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12806 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12807 = and(_T_12804, _T_12806) @[RegMapper.scala 176:46] + node _T_12808 = bits(_T_7981, 228, 228) @[RegMapper.scala 176:77] + node _T_12809 = and(_T_12807, _T_12808) @[RegMapper.scala 176:66] + node _T_12810 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12811 = and(_T_12810, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12812 = bits(_T_8239, 228, 228) @[RegMapper.scala 177:77] + node _T_12813 = and(_T_12811, _T_12812) @[RegMapper.scala 177:66] + node _T_12814 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12816 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12817 = and(_T_12814, _T_12816) @[RegMapper.scala 178:46] + node _T_12818 = bits(_T_8239, 228, 228) @[RegMapper.scala 178:77] + node _T_12819 = and(_T_12817, _T_12818) @[RegMapper.scala 178:66] + node _T_12820 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12821 = and(_T_12820, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12822 = bits(_T_7981, 229, 229) @[RegMapper.scala 175:77] + node _T_12823 = and(_T_12821, _T_12822) @[RegMapper.scala 175:66] + node _T_12824 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12826 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12827 = and(_T_12824, _T_12826) @[RegMapper.scala 176:46] + node _T_12828 = bits(_T_7981, 229, 229) @[RegMapper.scala 176:77] + node _T_12829 = and(_T_12827, _T_12828) @[RegMapper.scala 176:66] + node _T_12830 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12831 = and(_T_12830, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12832 = bits(_T_8239, 229, 229) @[RegMapper.scala 177:77] + node _T_12833 = and(_T_12831, _T_12832) @[RegMapper.scala 177:66] + node _T_12834 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12836 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12837 = and(_T_12834, _T_12836) @[RegMapper.scala 178:46] + node _T_12838 = bits(_T_8239, 229, 229) @[RegMapper.scala 178:77] + node _T_12839 = and(_T_12837, _T_12838) @[RegMapper.scala 178:66] + node _T_12840 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12841 = and(_T_12840, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12842 = bits(_T_7981, 230, 230) @[RegMapper.scala 175:77] + node _T_12843 = and(_T_12841, _T_12842) @[RegMapper.scala 175:66] + node _T_12844 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12846 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12847 = and(_T_12844, _T_12846) @[RegMapper.scala 176:46] + node _T_12848 = bits(_T_7981, 230, 230) @[RegMapper.scala 176:77] + node _T_12849 = and(_T_12847, _T_12848) @[RegMapper.scala 176:66] + node _T_12850 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12851 = and(_T_12850, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12852 = bits(_T_8239, 230, 230) @[RegMapper.scala 177:77] + node _T_12853 = and(_T_12851, _T_12852) @[RegMapper.scala 177:66] + node _T_12854 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12856 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12857 = and(_T_12854, _T_12856) @[RegMapper.scala 178:46] + node _T_12858 = bits(_T_8239, 230, 230) @[RegMapper.scala 178:77] + node _T_12859 = and(_T_12857, _T_12858) @[RegMapper.scala 178:66] + node _T_12860 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12861 = and(_T_12860, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12862 = bits(_T_7981, 231, 231) @[RegMapper.scala 175:77] + node _T_12863 = and(_T_12861, _T_12862) @[RegMapper.scala 175:66] + node _T_12864 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12866 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12867 = and(_T_12864, _T_12866) @[RegMapper.scala 176:46] + node _T_12868 = bits(_T_7981, 231, 231) @[RegMapper.scala 176:77] + node _T_12869 = and(_T_12867, _T_12868) @[RegMapper.scala 176:66] + node _T_12870 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12871 = and(_T_12870, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12872 = bits(_T_8239, 231, 231) @[RegMapper.scala 177:77] + node _T_12873 = and(_T_12871, _T_12872) @[RegMapper.scala 177:66] + node _T_12874 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12876 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12877 = and(_T_12874, _T_12876) @[RegMapper.scala 178:46] + node _T_12878 = bits(_T_8239, 231, 231) @[RegMapper.scala 178:77] + node _T_12879 = and(_T_12877, _T_12878) @[RegMapper.scala 178:66] + node _T_12880 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12881 = and(_T_12880, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12882 = bits(_T_7981, 232, 232) @[RegMapper.scala 175:77] + node _T_12883 = and(_T_12881, _T_12882) @[RegMapper.scala 175:66] + node _T_12884 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12886 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12887 = and(_T_12884, _T_12886) @[RegMapper.scala 176:46] + node _T_12888 = bits(_T_7981, 232, 232) @[RegMapper.scala 176:77] + node _T_12889 = and(_T_12887, _T_12888) @[RegMapper.scala 176:66] + node _T_12890 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12891 = and(_T_12890, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12892 = bits(_T_8239, 232, 232) @[RegMapper.scala 177:77] + node _T_12893 = and(_T_12891, _T_12892) @[RegMapper.scala 177:66] + node _T_12894 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12896 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12897 = and(_T_12894, _T_12896) @[RegMapper.scala 178:46] + node _T_12898 = bits(_T_8239, 232, 232) @[RegMapper.scala 178:77] + node _T_12899 = and(_T_12897, _T_12898) @[RegMapper.scala 178:66] + node _T_12900 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12901 = and(_T_12900, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12902 = bits(_T_7981, 233, 233) @[RegMapper.scala 175:77] + node _T_12903 = and(_T_12901, _T_12902) @[RegMapper.scala 175:66] + node _T_12904 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12906 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12907 = and(_T_12904, _T_12906) @[RegMapper.scala 176:46] + node _T_12908 = bits(_T_7981, 233, 233) @[RegMapper.scala 176:77] + node _T_12909 = and(_T_12907, _T_12908) @[RegMapper.scala 176:66] + node _T_12910 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12911 = and(_T_12910, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12912 = bits(_T_8239, 233, 233) @[RegMapper.scala 177:77] + node _T_12913 = and(_T_12911, _T_12912) @[RegMapper.scala 177:66] + node _T_12914 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12916 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12917 = and(_T_12914, _T_12916) @[RegMapper.scala 178:46] + node _T_12918 = bits(_T_8239, 233, 233) @[RegMapper.scala 178:77] + node _T_12919 = and(_T_12917, _T_12918) @[RegMapper.scala 178:66] + node _T_12920 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12921 = and(_T_12920, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12922 = bits(_T_7981, 234, 234) @[RegMapper.scala 175:77] + node _T_12923 = and(_T_12921, _T_12922) @[RegMapper.scala 175:66] + node _T_12924 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12926 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12927 = and(_T_12924, _T_12926) @[RegMapper.scala 176:46] + node _T_12928 = bits(_T_7981, 234, 234) @[RegMapper.scala 176:77] + node _T_12929 = and(_T_12927, _T_12928) @[RegMapper.scala 176:66] + node _T_12930 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12931 = and(_T_12930, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12932 = bits(_T_8239, 234, 234) @[RegMapper.scala 177:77] + node _T_12933 = and(_T_12931, _T_12932) @[RegMapper.scala 177:66] + node _T_12934 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12936 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12937 = and(_T_12934, _T_12936) @[RegMapper.scala 178:46] + node _T_12938 = bits(_T_8239, 234, 234) @[RegMapper.scala 178:77] + node _T_12939 = and(_T_12937, _T_12938) @[RegMapper.scala 178:66] + node _T_12940 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12941 = and(_T_12940, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12942 = bits(_T_7981, 235, 235) @[RegMapper.scala 175:77] + node _T_12943 = and(_T_12941, _T_12942) @[RegMapper.scala 175:66] + node _T_12944 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12946 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12947 = and(_T_12944, _T_12946) @[RegMapper.scala 176:46] + node _T_12948 = bits(_T_7981, 235, 235) @[RegMapper.scala 176:77] + node _T_12949 = and(_T_12947, _T_12948) @[RegMapper.scala 176:66] + node _T_12950 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12951 = and(_T_12950, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12952 = bits(_T_8239, 235, 235) @[RegMapper.scala 177:77] + node _T_12953 = and(_T_12951, _T_12952) @[RegMapper.scala 177:66] + node _T_12954 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12956 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12957 = and(_T_12954, _T_12956) @[RegMapper.scala 178:46] + node _T_12958 = bits(_T_8239, 235, 235) @[RegMapper.scala 178:77] + node _T_12959 = and(_T_12957, _T_12958) @[RegMapper.scala 178:66] + node _T_12960 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12961 = and(_T_12960, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12962 = bits(_T_7981, 236, 236) @[RegMapper.scala 175:77] + node _T_12963 = and(_T_12961, _T_12962) @[RegMapper.scala 175:66] + node _T_12964 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12966 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12967 = and(_T_12964, _T_12966) @[RegMapper.scala 176:46] + node _T_12968 = bits(_T_7981, 236, 236) @[RegMapper.scala 176:77] + node _T_12969 = and(_T_12967, _T_12968) @[RegMapper.scala 176:66] + node _T_12970 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12971 = and(_T_12970, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12972 = bits(_T_8239, 236, 236) @[RegMapper.scala 177:77] + node _T_12973 = and(_T_12971, _T_12972) @[RegMapper.scala 177:66] + node _T_12974 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12976 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12977 = and(_T_12974, _T_12976) @[RegMapper.scala 178:46] + node _T_12978 = bits(_T_8239, 236, 236) @[RegMapper.scala 178:77] + node _T_12979 = and(_T_12977, _T_12978) @[RegMapper.scala 178:66] + node _T_12980 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_12981 = and(_T_12980, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_12982 = bits(_T_7981, 237, 237) @[RegMapper.scala 175:77] + node _T_12983 = and(_T_12981, _T_12982) @[RegMapper.scala 175:66] + node _T_12984 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_12986 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_12987 = and(_T_12984, _T_12986) @[RegMapper.scala 176:46] + node _T_12988 = bits(_T_7981, 237, 237) @[RegMapper.scala 176:77] + node _T_12989 = and(_T_12987, _T_12988) @[RegMapper.scala 176:66] + node _T_12990 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_12991 = and(_T_12990, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_12992 = bits(_T_8239, 237, 237) @[RegMapper.scala 177:77] + node _T_12993 = and(_T_12991, _T_12992) @[RegMapper.scala 177:66] + node _T_12994 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_12996 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_12997 = and(_T_12994, _T_12996) @[RegMapper.scala 178:46] + node _T_12998 = bits(_T_8239, 237, 237) @[RegMapper.scala 178:77] + node _T_12999 = and(_T_12997, _T_12998) @[RegMapper.scala 178:66] + node _T_13000 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13001 = and(_T_13000, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13002 = bits(_T_7981, 238, 238) @[RegMapper.scala 175:77] + node _T_13003 = and(_T_13001, _T_13002) @[RegMapper.scala 175:66] + node _T_13004 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13006 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13007 = and(_T_13004, _T_13006) @[RegMapper.scala 176:46] + node _T_13008 = bits(_T_7981, 238, 238) @[RegMapper.scala 176:77] + node _T_13009 = and(_T_13007, _T_13008) @[RegMapper.scala 176:66] + node _T_13010 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13011 = and(_T_13010, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13012 = bits(_T_8239, 238, 238) @[RegMapper.scala 177:77] + node _T_13013 = and(_T_13011, _T_13012) @[RegMapper.scala 177:66] + node _T_13014 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13016 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13017 = and(_T_13014, _T_13016) @[RegMapper.scala 178:46] + node _T_13018 = bits(_T_8239, 238, 238) @[RegMapper.scala 178:77] + node _T_13019 = and(_T_13017, _T_13018) @[RegMapper.scala 178:66] + node _T_13020 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13021 = and(_T_13020, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13022 = bits(_T_7981, 239, 239) @[RegMapper.scala 175:77] + node _T_13023 = and(_T_13021, _T_13022) @[RegMapper.scala 175:66] + node _T_13024 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13026 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13027 = and(_T_13024, _T_13026) @[RegMapper.scala 176:46] + node _T_13028 = bits(_T_7981, 239, 239) @[RegMapper.scala 176:77] + node _T_13029 = and(_T_13027, _T_13028) @[RegMapper.scala 176:66] + node _T_13030 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13031 = and(_T_13030, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13032 = bits(_T_8239, 239, 239) @[RegMapper.scala 177:77] + node _T_13033 = and(_T_13031, _T_13032) @[RegMapper.scala 177:66] + node _T_13034 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13036 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13037 = and(_T_13034, _T_13036) @[RegMapper.scala 178:46] + node _T_13038 = bits(_T_8239, 239, 239) @[RegMapper.scala 178:77] + node _T_13039 = and(_T_13037, _T_13038) @[RegMapper.scala 178:66] + node _T_13040 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13041 = and(_T_13040, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13042 = bits(_T_7981, 240, 240) @[RegMapper.scala 175:77] + node _T_13043 = and(_T_13041, _T_13042) @[RegMapper.scala 175:66] + node _T_13044 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13046 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13047 = and(_T_13044, _T_13046) @[RegMapper.scala 176:46] + node _T_13048 = bits(_T_7981, 240, 240) @[RegMapper.scala 176:77] + node _T_13049 = and(_T_13047, _T_13048) @[RegMapper.scala 176:66] + node _T_13050 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13051 = and(_T_13050, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13052 = bits(_T_8239, 240, 240) @[RegMapper.scala 177:77] + node _T_13053 = and(_T_13051, _T_13052) @[RegMapper.scala 177:66] + node _T_13054 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13056 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13057 = and(_T_13054, _T_13056) @[RegMapper.scala 178:46] + node _T_13058 = bits(_T_8239, 240, 240) @[RegMapper.scala 178:77] + node _T_13059 = and(_T_13057, _T_13058) @[RegMapper.scala 178:66] + node _T_13060 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13061 = and(_T_13060, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13062 = bits(_T_7981, 241, 241) @[RegMapper.scala 175:77] + node _T_13063 = and(_T_13061, _T_13062) @[RegMapper.scala 175:66] + node _T_13064 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13066 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13067 = and(_T_13064, _T_13066) @[RegMapper.scala 176:46] + node _T_13068 = bits(_T_7981, 241, 241) @[RegMapper.scala 176:77] + node _T_13069 = and(_T_13067, _T_13068) @[RegMapper.scala 176:66] + node _T_13070 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13071 = and(_T_13070, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13072 = bits(_T_8239, 241, 241) @[RegMapper.scala 177:77] + node _T_13073 = and(_T_13071, _T_13072) @[RegMapper.scala 177:66] + node _T_13074 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13076 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13077 = and(_T_13074, _T_13076) @[RegMapper.scala 178:46] + node _T_13078 = bits(_T_8239, 241, 241) @[RegMapper.scala 178:77] + node _T_13079 = and(_T_13077, _T_13078) @[RegMapper.scala 178:66] + node _T_13080 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13081 = and(_T_13080, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13082 = bits(_T_7981, 242, 242) @[RegMapper.scala 175:77] + node _T_13083 = and(_T_13081, _T_13082) @[RegMapper.scala 175:66] + node _T_13084 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13086 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13087 = and(_T_13084, _T_13086) @[RegMapper.scala 176:46] + node _T_13088 = bits(_T_7981, 242, 242) @[RegMapper.scala 176:77] + node _T_13089 = and(_T_13087, _T_13088) @[RegMapper.scala 176:66] + node _T_13090 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13091 = and(_T_13090, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13092 = bits(_T_8239, 242, 242) @[RegMapper.scala 177:77] + node _T_13093 = and(_T_13091, _T_13092) @[RegMapper.scala 177:66] + node _T_13094 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13096 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13097 = and(_T_13094, _T_13096) @[RegMapper.scala 178:46] + node _T_13098 = bits(_T_8239, 242, 242) @[RegMapper.scala 178:77] + node _T_13099 = and(_T_13097, _T_13098) @[RegMapper.scala 178:66] + node _T_13100 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13101 = and(_T_13100, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13102 = bits(_T_7981, 243, 243) @[RegMapper.scala 175:77] + node _T_13103 = and(_T_13101, _T_13102) @[RegMapper.scala 175:66] + node _T_13104 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13106 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13107 = and(_T_13104, _T_13106) @[RegMapper.scala 176:46] + node _T_13108 = bits(_T_7981, 243, 243) @[RegMapper.scala 176:77] + node _T_13109 = and(_T_13107, _T_13108) @[RegMapper.scala 176:66] + node _T_13110 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13111 = and(_T_13110, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13112 = bits(_T_8239, 243, 243) @[RegMapper.scala 177:77] + node _T_13113 = and(_T_13111, _T_13112) @[RegMapper.scala 177:66] + node _T_13114 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13116 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13117 = and(_T_13114, _T_13116) @[RegMapper.scala 178:46] + node _T_13118 = bits(_T_8239, 243, 243) @[RegMapper.scala 178:77] + node _T_13119 = and(_T_13117, _T_13118) @[RegMapper.scala 178:66] + node _T_13120 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13121 = and(_T_13120, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13122 = bits(_T_7981, 244, 244) @[RegMapper.scala 175:77] + node _T_13123 = and(_T_13121, _T_13122) @[RegMapper.scala 175:66] + node _T_13124 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13126 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13127 = and(_T_13124, _T_13126) @[RegMapper.scala 176:46] + node _T_13128 = bits(_T_7981, 244, 244) @[RegMapper.scala 176:77] + node _T_13129 = and(_T_13127, _T_13128) @[RegMapper.scala 176:66] + node _T_13130 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13131 = and(_T_13130, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13132 = bits(_T_8239, 244, 244) @[RegMapper.scala 177:77] + node _T_13133 = and(_T_13131, _T_13132) @[RegMapper.scala 177:66] + node _T_13134 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13136 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13137 = and(_T_13134, _T_13136) @[RegMapper.scala 178:46] + node _T_13138 = bits(_T_8239, 244, 244) @[RegMapper.scala 178:77] + node _T_13139 = and(_T_13137, _T_13138) @[RegMapper.scala 178:66] + node _T_13140 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13141 = and(_T_13140, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13142 = bits(_T_7981, 245, 245) @[RegMapper.scala 175:77] + node _T_13143 = and(_T_13141, _T_13142) @[RegMapper.scala 175:66] + node _T_13144 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13146 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13147 = and(_T_13144, _T_13146) @[RegMapper.scala 176:46] + node _T_13148 = bits(_T_7981, 245, 245) @[RegMapper.scala 176:77] + node _T_13149 = and(_T_13147, _T_13148) @[RegMapper.scala 176:66] + node _T_13150 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13151 = and(_T_13150, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13152 = bits(_T_8239, 245, 245) @[RegMapper.scala 177:77] + node _T_13153 = and(_T_13151, _T_13152) @[RegMapper.scala 177:66] + node _T_13154 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13156 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13157 = and(_T_13154, _T_13156) @[RegMapper.scala 178:46] + node _T_13158 = bits(_T_8239, 245, 245) @[RegMapper.scala 178:77] + node _T_13159 = and(_T_13157, _T_13158) @[RegMapper.scala 178:66] + node _T_13160 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13161 = and(_T_13160, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13162 = bits(_T_7981, 246, 246) @[RegMapper.scala 175:77] + node _T_13163 = and(_T_13161, _T_13162) @[RegMapper.scala 175:66] + node _T_13164 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13166 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13167 = and(_T_13164, _T_13166) @[RegMapper.scala 176:46] + node _T_13168 = bits(_T_7981, 246, 246) @[RegMapper.scala 176:77] + node _T_13169 = and(_T_13167, _T_13168) @[RegMapper.scala 176:66] + node _T_13170 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13171 = and(_T_13170, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13172 = bits(_T_8239, 246, 246) @[RegMapper.scala 177:77] + node _T_13173 = and(_T_13171, _T_13172) @[RegMapper.scala 177:66] + node _T_13174 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13176 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13177 = and(_T_13174, _T_13176) @[RegMapper.scala 178:46] + node _T_13178 = bits(_T_8239, 246, 246) @[RegMapper.scala 178:77] + node _T_13179 = and(_T_13177, _T_13178) @[RegMapper.scala 178:66] + node _T_13180 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13181 = and(_T_13180, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13182 = bits(_T_7981, 247, 247) @[RegMapper.scala 175:77] + node _T_13183 = and(_T_13181, _T_13182) @[RegMapper.scala 175:66] + node _T_13184 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13186 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13187 = and(_T_13184, _T_13186) @[RegMapper.scala 176:46] + node _T_13188 = bits(_T_7981, 247, 247) @[RegMapper.scala 176:77] + node _T_13189 = and(_T_13187, _T_13188) @[RegMapper.scala 176:66] + node _T_13190 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13191 = and(_T_13190, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13192 = bits(_T_8239, 247, 247) @[RegMapper.scala 177:77] + node _T_13193 = and(_T_13191, _T_13192) @[RegMapper.scala 177:66] + node _T_13194 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13196 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13197 = and(_T_13194, _T_13196) @[RegMapper.scala 178:46] + node _T_13198 = bits(_T_8239, 247, 247) @[RegMapper.scala 178:77] + node _T_13199 = and(_T_13197, _T_13198) @[RegMapper.scala 178:66] + node _T_13200 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13201 = and(_T_13200, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13202 = bits(_T_7981, 248, 248) @[RegMapper.scala 175:77] + node _T_13203 = and(_T_13201, _T_13202) @[RegMapper.scala 175:66] + node _T_13204 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13206 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13207 = and(_T_13204, _T_13206) @[RegMapper.scala 176:46] + node _T_13208 = bits(_T_7981, 248, 248) @[RegMapper.scala 176:77] + node _T_13209 = and(_T_13207, _T_13208) @[RegMapper.scala 176:66] + node _T_13210 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13211 = and(_T_13210, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13212 = bits(_T_8239, 248, 248) @[RegMapper.scala 177:77] + node _T_13213 = and(_T_13211, _T_13212) @[RegMapper.scala 177:66] + node _T_13214 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13216 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13217 = and(_T_13214, _T_13216) @[RegMapper.scala 178:46] + node _T_13218 = bits(_T_8239, 248, 248) @[RegMapper.scala 178:77] + node _T_13219 = and(_T_13217, _T_13218) @[RegMapper.scala 178:66] + node _T_13220 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13221 = and(_T_13220, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13222 = bits(_T_7981, 249, 249) @[RegMapper.scala 175:77] + node _T_13223 = and(_T_13221, _T_13222) @[RegMapper.scala 175:66] + node _T_13224 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13226 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13227 = and(_T_13224, _T_13226) @[RegMapper.scala 176:46] + node _T_13228 = bits(_T_7981, 249, 249) @[RegMapper.scala 176:77] + node _T_13229 = and(_T_13227, _T_13228) @[RegMapper.scala 176:66] + node _T_13230 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13231 = and(_T_13230, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13232 = bits(_T_8239, 249, 249) @[RegMapper.scala 177:77] + node _T_13233 = and(_T_13231, _T_13232) @[RegMapper.scala 177:66] + node _T_13234 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13236 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13237 = and(_T_13234, _T_13236) @[RegMapper.scala 178:46] + node _T_13238 = bits(_T_8239, 249, 249) @[RegMapper.scala 178:77] + node _T_13239 = and(_T_13237, _T_13238) @[RegMapper.scala 178:66] + node _T_13240 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13241 = and(_T_13240, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13242 = bits(_T_7981, 250, 250) @[RegMapper.scala 175:77] + node _T_13243 = and(_T_13241, _T_13242) @[RegMapper.scala 175:66] + node _T_13244 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13246 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13247 = and(_T_13244, _T_13246) @[RegMapper.scala 176:46] + node _T_13248 = bits(_T_7981, 250, 250) @[RegMapper.scala 176:77] + node _T_13249 = and(_T_13247, _T_13248) @[RegMapper.scala 176:66] + node _T_13250 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13251 = and(_T_13250, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13252 = bits(_T_8239, 250, 250) @[RegMapper.scala 177:77] + node _T_13253 = and(_T_13251, _T_13252) @[RegMapper.scala 177:66] + node _T_13254 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13256 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13257 = and(_T_13254, _T_13256) @[RegMapper.scala 178:46] + node _T_13258 = bits(_T_8239, 250, 250) @[RegMapper.scala 178:77] + node _T_13259 = and(_T_13257, _T_13258) @[RegMapper.scala 178:66] + node _T_13260 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13261 = and(_T_13260, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13262 = bits(_T_7981, 251, 251) @[RegMapper.scala 175:77] + node _T_13263 = and(_T_13261, _T_13262) @[RegMapper.scala 175:66] + node _T_13264 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13266 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13267 = and(_T_13264, _T_13266) @[RegMapper.scala 176:46] + node _T_13268 = bits(_T_7981, 251, 251) @[RegMapper.scala 176:77] + node _T_13269 = and(_T_13267, _T_13268) @[RegMapper.scala 176:66] + node _T_13270 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13271 = and(_T_13270, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13272 = bits(_T_8239, 251, 251) @[RegMapper.scala 177:77] + node _T_13273 = and(_T_13271, _T_13272) @[RegMapper.scala 177:66] + node _T_13274 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13276 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13277 = and(_T_13274, _T_13276) @[RegMapper.scala 178:46] + node _T_13278 = bits(_T_8239, 251, 251) @[RegMapper.scala 178:77] + node _T_13279 = and(_T_13277, _T_13278) @[RegMapper.scala 178:66] + node _T_13280 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13281 = and(_T_13280, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13282 = bits(_T_7981, 252, 252) @[RegMapper.scala 175:77] + node _T_13283 = and(_T_13281, _T_13282) @[RegMapper.scala 175:66] + node _T_13284 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13286 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13287 = and(_T_13284, _T_13286) @[RegMapper.scala 176:46] + node _T_13288 = bits(_T_7981, 252, 252) @[RegMapper.scala 176:77] + node _T_13289 = and(_T_13287, _T_13288) @[RegMapper.scala 176:66] + node _T_13290 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13291 = and(_T_13290, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13292 = bits(_T_8239, 252, 252) @[RegMapper.scala 177:77] + node _T_13293 = and(_T_13291, _T_13292) @[RegMapper.scala 177:66] + node _T_13294 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13296 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13297 = and(_T_13294, _T_13296) @[RegMapper.scala 178:46] + node _T_13298 = bits(_T_8239, 252, 252) @[RegMapper.scala 178:77] + node _T_13299 = and(_T_13297, _T_13298) @[RegMapper.scala 178:66] + node _T_13300 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13301 = and(_T_13300, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13302 = bits(_T_7981, 253, 253) @[RegMapper.scala 175:77] + node _T_13303 = and(_T_13301, _T_13302) @[RegMapper.scala 175:66] + node _T_13304 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13306 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13307 = and(_T_13304, _T_13306) @[RegMapper.scala 176:46] + node _T_13308 = bits(_T_7981, 253, 253) @[RegMapper.scala 176:77] + node _T_13309 = and(_T_13307, _T_13308) @[RegMapper.scala 176:66] + node _T_13310 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13311 = and(_T_13310, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13312 = bits(_T_8239, 253, 253) @[RegMapper.scala 177:77] + node _T_13313 = and(_T_13311, _T_13312) @[RegMapper.scala 177:66] + node _T_13314 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13316 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13317 = and(_T_13314, _T_13316) @[RegMapper.scala 178:46] + node _T_13318 = bits(_T_8239, 253, 253) @[RegMapper.scala 178:77] + node _T_13319 = and(_T_13317, _T_13318) @[RegMapper.scala 178:66] + node _T_13320 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13321 = and(_T_13320, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13322 = bits(_T_7981, 254, 254) @[RegMapper.scala 175:77] + node _T_13323 = and(_T_13321, _T_13322) @[RegMapper.scala 175:66] + node _T_13324 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13326 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13327 = and(_T_13324, _T_13326) @[RegMapper.scala 176:46] + node _T_13328 = bits(_T_7981, 254, 254) @[RegMapper.scala 176:77] + node _T_13329 = and(_T_13327, _T_13328) @[RegMapper.scala 176:66] + node _T_13330 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13331 = and(_T_13330, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13332 = bits(_T_8239, 254, 254) @[RegMapper.scala 177:77] + node _T_13333 = and(_T_13331, _T_13332) @[RegMapper.scala 177:66] + node _T_13334 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13336 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13337 = and(_T_13334, _T_13336) @[RegMapper.scala 178:46] + node _T_13338 = bits(_T_8239, 254, 254) @[RegMapper.scala 178:77] + node _T_13339 = and(_T_13337, _T_13338) @[RegMapper.scala 178:66] + node _T_13340 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 175:31] + node _T_13341 = and(_T_13340, _T_692.bits.read) @[RegMapper.scala 175:46] + node _T_13342 = bits(_T_7981, 255, 255) @[RegMapper.scala 175:77] + node _T_13343 = and(_T_13341, _T_13342) @[RegMapper.scala 175:66] + node _T_13344 = and(_T_616.valid, _T_692.ready) @[RegMapper.scala 176:31] + node _T_13346 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_13347 = and(_T_13344, _T_13346) @[RegMapper.scala 176:46] + node _T_13348 = bits(_T_7981, 255, 255) @[RegMapper.scala 176:77] + node _T_13349 = and(_T_13347, _T_13348) @[RegMapper.scala 176:66] + node _T_13350 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 177:33] + node _T_13351 = and(_T_13350, _T_692.bits.read) @[RegMapper.scala 177:46] + node _T_13352 = bits(_T_8239, 255, 255) @[RegMapper.scala 177:77] + node _T_13353 = and(_T_13351, _T_13352) @[RegMapper.scala 177:66] + node _T_13354 = and(_T_692.valid, _T_656.ready) @[RegMapper.scala 178:33] + node _T_13356 = eq(_T_692.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_13357 = and(_T_13354, _T_13356) @[RegMapper.scala 178:46] + node _T_13358 = bits(_T_8239, 255, 255) @[RegMapper.scala 178:77] + node _T_13359 = and(_T_13357, _T_13358) @[RegMapper.scala 178:66] + node _T_13360 = and(_T_9523, _T_1277[2]) @[RegMapper.scala 184:66] + node _T_13361 = and(_T_13360, _T_1277[1]) @[RegMapper.scala 184:66] + node _T_13362 = and(_T_13361, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[0] <= _T_13362 @[RegMapper.scala 184:18] + node _T_13363 = and(_T_9529, _T_1299[2]) @[RegMapper.scala 185:66] + node _T_13364 = and(_T_13363, _T_1299[1]) @[RegMapper.scala 185:66] + node _T_13365 = and(_T_13364, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[0] <= _T_13365 @[RegMapper.scala 185:18] + node _T_13366 = and(_T_9533, _T_1321[2]) @[RegMapper.scala 186:66] + node _T_13367 = and(_T_13366, _T_1321[1]) @[RegMapper.scala 186:66] + node _T_13368 = and(_T_13367, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[0] <= _T_13368 @[RegMapper.scala 186:18] + node _T_13369 = and(_T_9539, _T_1343[2]) @[RegMapper.scala 187:66] + node _T_13370 = and(_T_13369, _T_1343[1]) @[RegMapper.scala 187:66] + node _T_13371 = and(_T_13370, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[0] <= _T_13371 @[RegMapper.scala 187:18] + node _T_13372 = and(_T_9523, _T_1277[2]) @[RegMapper.scala 184:66] + node _T_13373 = and(_T_13372, _T_1277[0]) @[RegMapper.scala 184:66] + node _T_13374 = and(_T_13373, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[1] <= _T_13374 @[RegMapper.scala 184:18] + node _T_13375 = and(_T_9529, _T_1299[2]) @[RegMapper.scala 185:66] + node _T_13376 = and(_T_13375, _T_1299[0]) @[RegMapper.scala 185:66] + node _T_13377 = and(_T_13376, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[1] <= _T_13377 @[RegMapper.scala 185:18] + node _T_13378 = and(_T_9533, _T_1321[2]) @[RegMapper.scala 186:66] + node _T_13379 = and(_T_13378, _T_1321[0]) @[RegMapper.scala 186:66] + node _T_13380 = and(_T_13379, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[1] <= _T_13380 @[RegMapper.scala 186:18] + node _T_13381 = and(_T_9539, _T_1343[2]) @[RegMapper.scala 187:66] + node _T_13382 = and(_T_13381, _T_1343[0]) @[RegMapper.scala 187:66] + node _T_13383 = and(_T_13382, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[1] <= _T_13383 @[RegMapper.scala 187:18] + node _T_13384 = and(_T_9523, _T_1277[1]) @[RegMapper.scala 184:66] + node _T_13385 = and(_T_13384, _T_1277[0]) @[RegMapper.scala 184:66] + node _T_13386 = and(_T_13385, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[2] <= _T_13386 @[RegMapper.scala 184:18] + node _T_13387 = and(_T_9529, _T_1299[1]) @[RegMapper.scala 185:66] + node _T_13388 = and(_T_13387, _T_1299[0]) @[RegMapper.scala 185:66] + node _T_13389 = and(_T_13388, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[2] <= _T_13389 @[RegMapper.scala 185:18] + node _T_13390 = and(_T_9533, _T_1321[1]) @[RegMapper.scala 186:66] + node _T_13391 = and(_T_13390, _T_1321[0]) @[RegMapper.scala 186:66] + node _T_13392 = and(_T_13391, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[2] <= _T_13392 @[RegMapper.scala 186:18] + node _T_13393 = and(_T_9539, _T_1343[1]) @[RegMapper.scala 187:66] + node _T_13394 = and(_T_13393, _T_1343[0]) @[RegMapper.scala 187:66] + node _T_13395 = and(_T_13394, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[2] <= _T_13395 @[RegMapper.scala 187:18] + node _T_13396 = and(_T_8243, _T_1277[4]) @[RegMapper.scala 184:66] + node _T_13397 = and(_T_13396, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[3] <= _T_13397 @[RegMapper.scala 184:18] + node _T_13398 = and(_T_8249, _T_1299[4]) @[RegMapper.scala 185:66] + node _T_13399 = and(_T_13398, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[3] <= _T_13399 @[RegMapper.scala 185:18] + node _T_13400 = and(_T_8253, _T_1321[4]) @[RegMapper.scala 186:66] + node _T_13401 = and(_T_13400, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[3] <= _T_13401 @[RegMapper.scala 186:18] + node _T_13402 = and(_T_8259, _T_1343[4]) @[RegMapper.scala 187:66] + node _T_13403 = and(_T_13402, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[3] <= _T_13403 @[RegMapper.scala 187:18] + node _T_13404 = and(_T_8243, _T_1277[3]) @[RegMapper.scala 184:66] + node _T_13405 = and(_T_13404, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[4] <= _T_13405 @[RegMapper.scala 184:18] + node _T_13406 = and(_T_8249, _T_1299[3]) @[RegMapper.scala 185:66] + node _T_13407 = and(_T_13406, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[4] <= _T_13407 @[RegMapper.scala 185:18] + node _T_13408 = and(_T_8253, _T_1321[3]) @[RegMapper.scala 186:66] + node _T_13409 = and(_T_13408, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[4] <= _T_13409 @[RegMapper.scala 186:18] + node _T_13410 = and(_T_8259, _T_1343[3]) @[RegMapper.scala 187:66] + node _T_13411 = and(_T_13410, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[4] <= _T_13411 @[RegMapper.scala 187:18] + node _T_13412 = and(_T_9843, _T_1277[7]) @[RegMapper.scala 184:66] + node _T_13413 = and(_T_13412, _T_1277[6]) @[RegMapper.scala 184:66] + node _T_13414 = and(_T_13413, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[5] <= _T_13414 @[RegMapper.scala 184:18] + node _T_13415 = and(_T_9849, _T_1299[7]) @[RegMapper.scala 185:66] + node _T_13416 = and(_T_13415, _T_1299[6]) @[RegMapper.scala 185:66] + node _T_13417 = and(_T_13416, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[5] <= _T_13417 @[RegMapper.scala 185:18] + node _T_13418 = and(_T_9853, _T_1321[7]) @[RegMapper.scala 186:66] + node _T_13419 = and(_T_13418, _T_1321[6]) @[RegMapper.scala 186:66] + node _T_13420 = and(_T_13419, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[5] <= _T_13420 @[RegMapper.scala 186:18] + node _T_13421 = and(_T_9859, _T_1343[7]) @[RegMapper.scala 187:66] + node _T_13422 = and(_T_13421, _T_1343[6]) @[RegMapper.scala 187:66] + node _T_13423 = and(_T_13422, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[5] <= _T_13423 @[RegMapper.scala 187:18] + node _T_13424 = and(_T_9843, _T_1277[7]) @[RegMapper.scala 184:66] + node _T_13425 = and(_T_13424, _T_1277[5]) @[RegMapper.scala 184:66] + node _T_13426 = and(_T_13425, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[6] <= _T_13426 @[RegMapper.scala 184:18] + node _T_13427 = and(_T_9849, _T_1299[7]) @[RegMapper.scala 185:66] + node _T_13428 = and(_T_13427, _T_1299[5]) @[RegMapper.scala 185:66] + node _T_13429 = and(_T_13428, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[6] <= _T_13429 @[RegMapper.scala 185:18] + node _T_13430 = and(_T_9853, _T_1321[7]) @[RegMapper.scala 186:66] + node _T_13431 = and(_T_13430, _T_1321[5]) @[RegMapper.scala 186:66] + node _T_13432 = and(_T_13431, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[6] <= _T_13432 @[RegMapper.scala 186:18] + node _T_13433 = and(_T_9859, _T_1343[7]) @[RegMapper.scala 187:66] + node _T_13434 = and(_T_13433, _T_1343[5]) @[RegMapper.scala 187:66] + node _T_13435 = and(_T_13434, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[6] <= _T_13435 @[RegMapper.scala 187:18] + node _T_13436 = and(_T_9843, _T_1277[6]) @[RegMapper.scala 184:66] + node _T_13437 = and(_T_13436, _T_1277[5]) @[RegMapper.scala 184:66] + node _T_13438 = and(_T_13437, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[7] <= _T_13438 @[RegMapper.scala 184:18] + node _T_13439 = and(_T_9849, _T_1299[6]) @[RegMapper.scala 185:66] + node _T_13440 = and(_T_13439, _T_1299[5]) @[RegMapper.scala 185:66] + node _T_13441 = and(_T_13440, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[7] <= _T_13441 @[RegMapper.scala 185:18] + node _T_13442 = and(_T_9853, _T_1321[6]) @[RegMapper.scala 186:66] + node _T_13443 = and(_T_13442, _T_1321[5]) @[RegMapper.scala 186:66] + node _T_13444 = and(_T_13443, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[7] <= _T_13444 @[RegMapper.scala 186:18] + node _T_13445 = and(_T_9859, _T_1343[6]) @[RegMapper.scala 187:66] + node _T_13446 = and(_T_13445, _T_1343[5]) @[RegMapper.scala 187:66] + node _T_13447 = and(_T_13446, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[7] <= _T_13447 @[RegMapper.scala 187:18] + node _T_13448 = and(_T_8263, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[8] <= _T_13448 @[RegMapper.scala 184:18] + node _T_13449 = and(_T_8269, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[8] <= _T_13449 @[RegMapper.scala 185:18] + node _T_13450 = and(_T_8273, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[8] <= _T_13450 @[RegMapper.scala 186:18] + node _T_13451 = and(_T_8279, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[8] <= _T_13451 @[RegMapper.scala 187:18] + node _T_13452 = and(_T_8883, _T_1277[11]) @[RegMapper.scala 184:66] + node _T_13453 = and(_T_13452, _T_1277[10]) @[RegMapper.scala 184:66] + node _T_13454 = and(_T_13453, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[9] <= _T_13454 @[RegMapper.scala 184:18] + node _T_13455 = and(_T_8889, _T_1299[11]) @[RegMapper.scala 185:66] + node _T_13456 = and(_T_13455, _T_1299[10]) @[RegMapper.scala 185:66] + node _T_13457 = and(_T_13456, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[9] <= _T_13457 @[RegMapper.scala 185:18] + node _T_13458 = and(_T_8893, _T_1321[11]) @[RegMapper.scala 186:66] + node _T_13459 = and(_T_13458, _T_1321[10]) @[RegMapper.scala 186:66] + node _T_13460 = and(_T_13459, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[9] <= _T_13460 @[RegMapper.scala 186:18] + node _T_13461 = and(_T_8899, _T_1343[11]) @[RegMapper.scala 187:66] + node _T_13462 = and(_T_13461, _T_1343[10]) @[RegMapper.scala 187:66] + node _T_13463 = and(_T_13462, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[9] <= _T_13463 @[RegMapper.scala 187:18] + node _T_13464 = and(_T_8883, _T_1277[11]) @[RegMapper.scala 184:66] + node _T_13465 = and(_T_13464, _T_1277[9]) @[RegMapper.scala 184:66] + node _T_13466 = and(_T_13465, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[10] <= _T_13466 @[RegMapper.scala 184:18] + node _T_13467 = and(_T_8889, _T_1299[11]) @[RegMapper.scala 185:66] + node _T_13468 = and(_T_13467, _T_1299[9]) @[RegMapper.scala 185:66] + node _T_13469 = and(_T_13468, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[10] <= _T_13469 @[RegMapper.scala 185:18] + node _T_13470 = and(_T_8893, _T_1321[11]) @[RegMapper.scala 186:66] + node _T_13471 = and(_T_13470, _T_1321[9]) @[RegMapper.scala 186:66] + node _T_13472 = and(_T_13471, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[10] <= _T_13472 @[RegMapper.scala 186:18] + node _T_13473 = and(_T_8899, _T_1343[11]) @[RegMapper.scala 187:66] + node _T_13474 = and(_T_13473, _T_1343[9]) @[RegMapper.scala 187:66] + node _T_13475 = and(_T_13474, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[10] <= _T_13475 @[RegMapper.scala 187:18] + node _T_13476 = and(_T_8883, _T_1277[10]) @[RegMapper.scala 184:66] + node _T_13477 = and(_T_13476, _T_1277[9]) @[RegMapper.scala 184:66] + node _T_13478 = and(_T_13477, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[11] <= _T_13478 @[RegMapper.scala 184:18] + node _T_13479 = and(_T_8889, _T_1299[10]) @[RegMapper.scala 185:66] + node _T_13480 = and(_T_13479, _T_1299[9]) @[RegMapper.scala 185:66] + node _T_13481 = and(_T_13480, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[11] <= _T_13481 @[RegMapper.scala 185:18] + node _T_13482 = and(_T_8893, _T_1321[10]) @[RegMapper.scala 186:66] + node _T_13483 = and(_T_13482, _T_1321[9]) @[RegMapper.scala 186:66] + node _T_13484 = and(_T_13483, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[11] <= _T_13484 @[RegMapper.scala 186:18] + node _T_13485 = and(_T_8899, _T_1343[10]) @[RegMapper.scala 187:66] + node _T_13486 = and(_T_13485, _T_1343[9]) @[RegMapper.scala 187:66] + node _T_13487 = and(_T_13486, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[11] <= _T_13487 @[RegMapper.scala 187:18] + node _T_13488 = and(_T_11443, _T_1277[13]) @[RegMapper.scala 184:66] + node _T_13489 = and(_T_13488, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[12] <= _T_13489 @[RegMapper.scala 184:18] + node _T_13490 = and(_T_11449, _T_1299[13]) @[RegMapper.scala 185:66] + node _T_13491 = and(_T_13490, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[12] <= _T_13491 @[RegMapper.scala 185:18] + node _T_13492 = and(_T_11453, _T_1321[13]) @[RegMapper.scala 186:66] + node _T_13493 = and(_T_13492, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[12] <= _T_13493 @[RegMapper.scala 186:18] + node _T_13494 = and(_T_11459, _T_1343[13]) @[RegMapper.scala 187:66] + node _T_13495 = and(_T_13494, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[12] <= _T_13495 @[RegMapper.scala 187:18] + node _T_13496 = and(_T_11443, _T_1277[12]) @[RegMapper.scala 184:66] + node _T_13497 = and(_T_13496, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[13] <= _T_13497 @[RegMapper.scala 184:18] + node _T_13498 = and(_T_11449, _T_1299[12]) @[RegMapper.scala 185:66] + node _T_13499 = and(_T_13498, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[13] <= _T_13499 @[RegMapper.scala 185:18] + node _T_13500 = and(_T_11453, _T_1321[12]) @[RegMapper.scala 186:66] + node _T_13501 = and(_T_13500, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[13] <= _T_13501 @[RegMapper.scala 186:18] + node _T_13502 = and(_T_11459, _T_1343[12]) @[RegMapper.scala 187:66] + node _T_13503 = and(_T_13502, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[13] <= _T_13503 @[RegMapper.scala 187:18] + node _T_13504 = and(_T_10803, _T_1277[15]) @[RegMapper.scala 184:66] + node _T_13505 = and(_T_13504, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[14] <= _T_13505 @[RegMapper.scala 184:18] + node _T_13506 = and(_T_10809, _T_1299[15]) @[RegMapper.scala 185:66] + node _T_13507 = and(_T_13506, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[14] <= _T_13507 @[RegMapper.scala 185:18] + node _T_13508 = and(_T_10813, _T_1321[15]) @[RegMapper.scala 186:66] + node _T_13509 = and(_T_13508, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[14] <= _T_13509 @[RegMapper.scala 186:18] + node _T_13510 = and(_T_10819, _T_1343[15]) @[RegMapper.scala 187:66] + node _T_13511 = and(_T_13510, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[14] <= _T_13511 @[RegMapper.scala 187:18] + node _T_13512 = and(_T_10803, _T_1277[14]) @[RegMapper.scala 184:66] + node _T_13513 = and(_T_13512, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_1233[15] <= _T_13513 @[RegMapper.scala 184:18] + node _T_13514 = and(_T_10809, _T_1299[14]) @[RegMapper.scala 185:66] + node _T_13515 = and(_T_13514, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_1255[15] <= _T_13515 @[RegMapper.scala 185:18] + node _T_13516 = and(_T_10813, _T_1321[14]) @[RegMapper.scala 186:66] + node _T_13517 = and(_T_13516, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_1365[15] <= _T_13517 @[RegMapper.scala 186:18] + node _T_13518 = and(_T_10819, _T_1343[14]) @[RegMapper.scala 187:66] + node _T_13519 = and(_T_13518, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_1387[15] <= _T_13519 @[RegMapper.scala 187:18] + _T_656.bits.read <= _T_692.bits.read @[RegMapper.scala 190:20] + wire _T_13522 : UInt<1>[256] @[RegMapper.scala 191:30] + _T_13522 is invalid @[RegMapper.scala 191:30] + _T_13522[0] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[1] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[2] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[3] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[4] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[5] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[6] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[7] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[8] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[9] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[10] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[11] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[12] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[13] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[14] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[15] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[16] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[17] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[18] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[19] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[20] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[21] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[22] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[23] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[24] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[25] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[26] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[27] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[28] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[29] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[30] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[31] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[32] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[33] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[34] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[35] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[36] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[37] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[38] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[39] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[40] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[41] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[42] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[43] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[44] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[45] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[46] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[47] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[48] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[49] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[50] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[51] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[52] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[53] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[54] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[55] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[56] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[57] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[58] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[59] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[60] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[61] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[62] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[63] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[64] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[65] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[66] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[67] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[68] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[69] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[70] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[71] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[72] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[73] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[74] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[75] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[76] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[77] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[78] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[79] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[80] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[81] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[82] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[83] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[84] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[85] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[86] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[87] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[88] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[89] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[90] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[91] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[92] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[93] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[94] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[95] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[96] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[97] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[98] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[99] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[100] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[101] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[102] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[103] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[104] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[105] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[106] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[107] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[108] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[109] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[110] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[111] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[112] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[113] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[114] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[115] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[116] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[117] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[118] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[119] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[120] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[121] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[122] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[123] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[124] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[125] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[126] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[127] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[128] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[129] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[130] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[131] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[132] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[133] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[134] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[135] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[136] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[137] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[138] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[139] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[140] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[141] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[142] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[143] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[144] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[145] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[146] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[147] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[148] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[149] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[150] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[151] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[152] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[153] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[154] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[155] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[156] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[157] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[158] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[159] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[160] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[161] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[162] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[163] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[164] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[165] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[166] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[167] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[168] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[169] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[170] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[171] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[172] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[173] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[174] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[175] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[176] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[177] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[178] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[179] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[180] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[181] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[182] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[183] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[184] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[185] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[186] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[187] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[188] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[189] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[190] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[191] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[192] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[193] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[194] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[195] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[196] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[197] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[198] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[199] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[200] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[201] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[202] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[203] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[204] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[205] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[206] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[207] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[208] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[209] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[210] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[211] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[212] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[213] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[214] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[215] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[216] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[217] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[218] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[219] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[220] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[221] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[222] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[223] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[224] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[225] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[226] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[227] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[228] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[229] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[230] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[231] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[232] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[233] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[234] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[235] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[236] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[237] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[238] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[239] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[240] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[241] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[242] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[243] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[244] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[245] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[246] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[247] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[248] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[249] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[250] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[251] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[252] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[253] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[254] <= UInt<1>("h01") @[RegMapper.scala 191:30] + _T_13522[255] <= UInt<1>("h01") @[RegMapper.scala 191:30] + wire _T_13784 : UInt<64>[256] @[RegMapper.scala 191:54] + _T_13784 is invalid @[RegMapper.scala 191:54] + _T_13784[0] <= _T_2979 @[RegMapper.scala 191:54] + _T_13784[1] <= _T_3139 @[RegMapper.scala 191:54] + _T_13784[2] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[3] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[4] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[5] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[6] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[7] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[8] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[9] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[10] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[11] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[12] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[13] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[14] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[15] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[16] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[17] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[18] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[19] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[20] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[21] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[22] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[23] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[24] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[25] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[26] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[27] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[28] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[29] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[30] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[31] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[32] <= _T_3259 @[RegMapper.scala 191:54] + _T_13784[33] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[34] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[35] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[36] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[37] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[38] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[39] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[40] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[41] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[42] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[43] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[44] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[45] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[46] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[47] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[48] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[49] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[50] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[51] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[52] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[53] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[54] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[55] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[56] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[57] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[58] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[59] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[60] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[61] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[62] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[63] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[64] <= _T_2899 @[RegMapper.scala 191:54] + _T_13784[65] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[66] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[67] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[68] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[69] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[70] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[71] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[72] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[73] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[74] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[75] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[76] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[77] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[78] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[79] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[80] <= _T_3099 @[RegMapper.scala 191:54] + _T_13784[81] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[82] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[83] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[84] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[85] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[86] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[87] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[88] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[89] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[90] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[91] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[92] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[93] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[94] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[95] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[96] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[97] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[98] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[99] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[100] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[101] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[102] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[103] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[104] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[105] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[106] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[107] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[108] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[109] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[110] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[111] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[112] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[113] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[114] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[115] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[116] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[117] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[118] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[119] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[120] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[121] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[122] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[123] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[124] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[125] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[126] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[127] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[128] <= _T_3473 @[RegMapper.scala 191:54] + _T_13784[129] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[130] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[131] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[132] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[133] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[134] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[135] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[136] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[137] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[138] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[139] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[140] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[141] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[142] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[143] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[144] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[145] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[146] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[147] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[148] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[149] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[150] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[151] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[152] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[153] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[154] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[155] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[156] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[157] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[158] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[159] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[160] <= _T_3366 @[RegMapper.scala 191:54] + _T_13784[161] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[162] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[163] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[164] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[165] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[166] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[167] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[168] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[169] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[170] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[171] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[172] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[173] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[174] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[175] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[176] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[177] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[178] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[179] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[180] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[181] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[182] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[183] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[184] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[185] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[186] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[187] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[188] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[189] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[190] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[191] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[192] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[193] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[194] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[195] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[196] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[197] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[198] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[199] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[200] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[201] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[202] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[203] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[204] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[205] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[206] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[207] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[208] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[209] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[210] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[211] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[212] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[213] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[214] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[215] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[216] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[217] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[218] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[219] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[220] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[221] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[222] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[223] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[224] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[225] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[226] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[227] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[228] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[229] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[230] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[231] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[232] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[233] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[234] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[235] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[236] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[237] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[238] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[239] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[240] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[241] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[242] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[243] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[244] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[245] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[246] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[247] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[248] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[249] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[250] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[251] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[252] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[253] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[254] <= UInt<1>("h00") @[RegMapper.scala 191:54] + _T_13784[255] <= UInt<1>("h00") @[RegMapper.scala 191:54] + node _T_14045 = mux(_T_13522[_T_7713], _T_13784[_T_7713], UInt<1>("h00")) @[RegMapper.scala 191:26] + _T_656.bits.data <= _T_14045 @[RegMapper.scala 191:20] + _T_656.bits.extra <= _T_692.bits.extra @[RegMapper.scala 192:20] + _T_616.valid <= io.tl_in.0.a.valid @[RegisterRouter.scala 58:15] + io.tl_in.0.a.ready <= _T_616.ready @[RegisterRouter.scala 59:15] + io.tl_in.0.d.valid <= _T_656.valid @[RegisterRouter.scala 60:15] + _T_656.ready <= io.tl_in.0.d.ready @[RegisterRouter.scala 61:15] + node _T_14046 = bits(_T_656.bits.extra, 11, 9) @[RegisterRouter.scala 65:35] + node _T_14048 = bits(_T_656.bits.extra, 8, 3) @[RegisterRouter.scala 67:35] + node _T_14049 = bits(_T_656.bits.extra, 2, 0) @[RegisterRouter.scala 68:35] + wire _T_14060 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_14060 is invalid @[Edges.scala 617:17] + _T_14060.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_14060.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_14060.size <= _T_14049 @[Edges.scala 620:15] + _T_14060.source <= _T_14048 @[Edges.scala 621:15] + _T_14060.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_14071 = bits(_T_14046, 2, 0) @[Edges.scala 172:47] + _T_14060.addr_lo <= _T_14071 @[Edges.scala 623:15] + _T_14060.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_14060.error <= UInt<1>("h00") @[Edges.scala 625:15] + io.tl_in.0.d.bits <- _T_14060 @[RegisterRouter.scala 64:12] + io.tl_in.0.d.bits.data <= _T_656.bits.data @[RegisterRouter.scala 71:17] + node _T_14075 = mux(_T_656.bits.read, UInt<1>("h01"), UInt<1>("h00")) @[RegisterRouter.scala 72:25] + io.tl_in.0.d.bits.opcode <= _T_14075 @[RegisterRouter.scala 72:19] + io.tl_in.0.b.valid <= UInt<1>("h00") @[RegisterRouter.scala 75:25] + io.tl_in.0.c.ready <= UInt<1>("h01") @[RegisterRouter.scala 76:25] + io.tl_in.0.e.ready <= UInt<1>("h01") @[RegisterRouter.scala 77:25] + priority[0] <= UInt<1>("h00") @[Plic.scala 203:17] + pending[0] <= UInt<1>("h00") @[Plic.scala 204:16] + enables[0][0] <= UInt<1>("h00") @[Plic.scala 206:12] + enables[1][0] <= UInt<1>("h00") @[Plic.scala 206:12] + + module CoreplexLocalInterrupter_clint : + input clock : Clock + input reset : UInt<1> + output io : {flip rtcTick : UInt<1>, int : {0 : UInt<1>[2]}, flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg time_0 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Prci.scala 60:48] + reg time_1 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Prci.scala 60:48] + when io.rtcTick : @[Prci.scala 61:23] + node _T_362 = cat(time_1, time_0) @[Cat.scala 30:58] + node _T_364 = add(_T_362, UInt<1>("h01")) @[Prci.scala 62:33] + node _T_365 = tail(_T_364, 1) @[Prci.scala 62:33] + node _T_366 = shr(_T_365, 0) @[Prci.scala 64:24] + time_0 <= _T_366 @[Prci.scala 64:13] + node _T_367 = shr(_T_365, 32) @[Prci.scala 64:24] + time_1 <= _T_367 @[Prci.scala 64:13] + skip @[Prci.scala 61:23] + reg timecmp_0_0 : UInt<32>, clock @[Prci.scala 67:73] + reg timecmp_0_1 : UInt<32>, clock @[Prci.scala 67:73] + reg ipi_0 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_371 = bits(ipi_0, 0, 0) @[Prci.scala 71:23] + io.int.0[0] <= _T_371 @[Prci.scala 71:14] + node _T_372 = cat(time_1, time_0) @[Cat.scala 30:58] + node _T_373 = cat(timecmp_0_1, timecmp_0_0) @[Cat.scala 30:58] + node _T_374 = geq(_T_372, _T_373) @[Prci.scala 72:29] + io.int.0[1] <= _T_374 @[Prci.scala 72:14] + wire _T_398 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegisterRouter.scala 47:18] + _T_398 is invalid @[RegisterRouter.scala 47:18] + node _T_416 = eq(io.in.0.a.bits.opcode, UInt<3>("h04")) @[RegisterRouter.scala 48:36] + _T_398.bits.read <= _T_416 @[RegisterRouter.scala 48:19] + node _T_417 = shr(io.in.0.a.bits.address, 3) @[Edges.scala 170:34] + _T_398.bits.index <= _T_417 @[RegisterRouter.scala 49:19] + _T_398.bits.data <= io.in.0.a.bits.data @[RegisterRouter.scala 50:19] + _T_398.bits.mask <= io.in.0.a.bits.mask @[RegisterRouter.scala 51:19] + node _T_418 = bits(io.in.0.a.bits.address, 2, 0) @[Edges.scala 172:47] + node _T_419 = cat(_T_418, io.in.0.a.bits.source) @[Cat.scala 30:58] + node _T_420 = cat(_T_419, io.in.0.a.bits.size) @[Cat.scala 30:58] + _T_398.bits.extra <= _T_420 @[RegisterRouter.scala 52:19] + wire _T_438 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, data : UInt<64>, extra : UInt<12>}} @[RegMapper.scala 56:19] + _T_438 is invalid @[RegMapper.scala 56:19] + wire _T_474 : {flip ready : UInt<1>, valid : UInt<1>, bits : {read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : UInt<12>}} @[RegMapper.scala 57:21] + _T_474 is invalid @[RegMapper.scala 57:21] + _T_474.bits <- _T_398.bits @[RegMapper.scala 58:16] + node _T_492 = not(UInt<13>("h0801")) @[RegMapper.scala 74:21] + node _T_502 = xor(_T_474.bits.index, UInt<13>("h0800")) @[RegMapper.scala 93:47] + node _T_503 = and(_T_502, _T_492) @[RegMapper.scala 93:55] + node _T_505 = eq(_T_503, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_506 = xor(_T_474.bits.index, UInt<13>("h0800")) @[RegMapper.scala 94:47] + node _T_507 = and(_T_506, _T_492) @[RegMapper.scala 94:55] + node _T_509 = eq(_T_507, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_511 = xor(_T_474.bits.index, UInt<13>("h017ff")) @[RegMapper.scala 93:47] + node _T_512 = and(_T_511, _T_492) @[RegMapper.scala 93:55] + node _T_514 = eq(_T_512, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_515 = xor(_T_474.bits.index, UInt<13>("h017ff")) @[RegMapper.scala 94:47] + node _T_516 = and(_T_515, _T_492) @[RegMapper.scala 94:55] + node _T_518 = eq(_T_516, UInt<1>("h00")) @[RegMapper.scala 94:68] + node _T_520 = xor(_T_474.bits.index, UInt<13>("h00")) @[RegMapper.scala 93:47] + node _T_521 = and(_T_520, _T_492) @[RegMapper.scala 93:55] + node _T_523 = eq(_T_521, UInt<1>("h00")) @[RegMapper.scala 93:68] + node _T_524 = xor(_T_474.bits.index, UInt<13>("h00")) @[RegMapper.scala 94:47] + node _T_525 = and(_T_524, _T_492) @[RegMapper.scala 94:55] + node _T_527 = eq(_T_525, UInt<1>("h00")) @[RegMapper.scala 94:68] + wire _T_531 : UInt<1>[5] @[RegMapper.scala 107:23] + _T_531 is invalid @[RegMapper.scala 107:23] + wire _T_542 : UInt<1>[5] @[RegMapper.scala 108:23] + _T_542 is invalid @[RegMapper.scala 108:23] + wire _T_553 : UInt<1>[5] @[RegMapper.scala 109:23] + _T_553 is invalid @[RegMapper.scala 109:23] + wire _T_564 : UInt<1>[5] @[RegMapper.scala 110:23] + _T_564 is invalid @[RegMapper.scala 110:23] + wire _T_575 : UInt<1>[5] @[RegMapper.scala 111:23] + _T_575 is invalid @[RegMapper.scala 111:23] + wire _T_586 : UInt<1>[5] @[RegMapper.scala 112:23] + _T_586 is invalid @[RegMapper.scala 112:23] + wire _T_597 : UInt<1>[5] @[RegMapper.scala 113:23] + _T_597 is invalid @[RegMapper.scala 113:23] + wire _T_608 : UInt<1>[5] @[RegMapper.scala 114:23] + _T_608 is invalid @[RegMapper.scala 114:23] + node _T_636 = bits(_T_474.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_637 = bits(_T_474.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_638 = bits(_T_474.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_639 = bits(_T_474.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_640 = bits(_T_474.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_641 = bits(_T_474.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_642 = bits(_T_474.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_643 = bits(_T_474.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_644 = bits(_T_636, 0, 0) @[Bitwise.scala 71:15] + node _T_647 = mux(_T_644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_648 = bits(_T_637, 0, 0) @[Bitwise.scala 71:15] + node _T_651 = mux(_T_648, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_652 = bits(_T_638, 0, 0) @[Bitwise.scala 71:15] + node _T_655 = mux(_T_652, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_656 = bits(_T_639, 0, 0) @[Bitwise.scala 71:15] + node _T_659 = mux(_T_656, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_660 = bits(_T_640, 0, 0) @[Bitwise.scala 71:15] + node _T_663 = mux(_T_660, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_664 = bits(_T_641, 0, 0) @[Bitwise.scala 71:15] + node _T_667 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_668 = bits(_T_642, 0, 0) @[Bitwise.scala 71:15] + node _T_671 = mux(_T_668, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_672 = bits(_T_643, 0, 0) @[Bitwise.scala 71:15] + node _T_675 = mux(_T_672, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_676 = cat(_T_651, _T_647) @[Cat.scala 30:58] + node _T_677 = cat(_T_659, _T_655) @[Cat.scala 30:58] + node _T_678 = cat(_T_677, _T_676) @[Cat.scala 30:58] + node _T_679 = cat(_T_667, _T_663) @[Cat.scala 30:58] + node _T_680 = cat(_T_675, _T_671) @[Cat.scala 30:58] + node _T_681 = cat(_T_680, _T_679) @[Cat.scala 30:58] + node _T_682 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_683 = bits(_T_474.bits.mask, 0, 0) @[Bitwise.scala 27:51] + node _T_684 = bits(_T_474.bits.mask, 1, 1) @[Bitwise.scala 27:51] + node _T_685 = bits(_T_474.bits.mask, 2, 2) @[Bitwise.scala 27:51] + node _T_686 = bits(_T_474.bits.mask, 3, 3) @[Bitwise.scala 27:51] + node _T_687 = bits(_T_474.bits.mask, 4, 4) @[Bitwise.scala 27:51] + node _T_688 = bits(_T_474.bits.mask, 5, 5) @[Bitwise.scala 27:51] + node _T_689 = bits(_T_474.bits.mask, 6, 6) @[Bitwise.scala 27:51] + node _T_690 = bits(_T_474.bits.mask, 7, 7) @[Bitwise.scala 27:51] + node _T_691 = bits(_T_683, 0, 0) @[Bitwise.scala 71:15] + node _T_694 = mux(_T_691, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_695 = bits(_T_684, 0, 0) @[Bitwise.scala 71:15] + node _T_698 = mux(_T_695, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_699 = bits(_T_685, 0, 0) @[Bitwise.scala 71:15] + node _T_702 = mux(_T_699, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_703 = bits(_T_686, 0, 0) @[Bitwise.scala 71:15] + node _T_706 = mux(_T_703, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_707 = bits(_T_687, 0, 0) @[Bitwise.scala 71:15] + node _T_710 = mux(_T_707, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_711 = bits(_T_688, 0, 0) @[Bitwise.scala 71:15] + node _T_714 = mux(_T_711, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_715 = bits(_T_689, 0, 0) @[Bitwise.scala 71:15] + node _T_718 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_719 = bits(_T_690, 0, 0) @[Bitwise.scala 71:15] + node _T_722 = mux(_T_719, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_723 = cat(_T_698, _T_694) @[Cat.scala 30:58] + node _T_724 = cat(_T_706, _T_702) @[Cat.scala 30:58] + node _T_725 = cat(_T_724, _T_723) @[Cat.scala 30:58] + node _T_726 = cat(_T_714, _T_710) @[Cat.scala 30:58] + node _T_727 = cat(_T_722, _T_718) @[Cat.scala 30:58] + node _T_728 = cat(_T_727, _T_726) @[Cat.scala 30:58] + node _T_729 = cat(_T_728, _T_725) @[Cat.scala 30:58] + node _T_730 = bits(_T_682, 31, 0) @[RegMapper.scala 135:29] + node _T_732 = neq(_T_730, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_733 = bits(_T_682, 31, 0) @[RegMapper.scala 136:29] + node _T_734 = not(_T_733) @[RegMapper.scala 136:45] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_737 = bits(_T_729, 31, 0) @[RegMapper.scala 137:28] + node _T_739 = neq(_T_737, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_740 = bits(_T_729, 31, 0) @[RegMapper.scala 138:28] + node _T_741 = not(_T_740) @[RegMapper.scala 138:44] + node _T_743 = eq(_T_741, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_744 = and(_T_531[0], _T_732) @[RegMapper.scala 140:69] + node _T_745 = and(_T_597[0], _T_739) @[RegMapper.scala 140:91] + node _T_748 = and(_T_542[0], _T_736) @[RegMapper.scala 141:62] + node _T_749 = and(_T_608[0], _T_743) @[RegMapper.scala 141:84] + node _T_750 = bits(_T_474.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_749 : @[RegField.scala 70:88] + timecmp_0_0 <= _T_750 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_754 = eq(_T_732, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_755 = or(UInt<1>("h01"), _T_754) @[RegMapper.scala 142:31] + _T_553[0] <= _T_755 @[RegMapper.scala 142:18] + node _T_757 = eq(_T_736, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_758 = or(UInt<1>("h01"), _T_757) @[RegMapper.scala 143:31] + _T_564[0] <= _T_758 @[RegMapper.scala 143:18] + node _T_760 = eq(_T_739, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_761 = or(UInt<1>("h01"), _T_760) @[RegMapper.scala 144:31] + _T_575[0] <= _T_761 @[RegMapper.scala 144:18] + node _T_763 = eq(_T_743, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_764 = or(UInt<1>("h01"), _T_763) @[RegMapper.scala 145:31] + _T_586[0] <= _T_764 @[RegMapper.scala 145:18] + node _T_765 = shl(timecmp_0_0, 0) @[RegMapper.scala 150:47] + node _T_767 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_768 = and(_T_765, _T_767) @[RegMapper.scala 150:55] + node _T_769 = or(UInt<1>("h00"), _T_768) @[RegMapper.scala 150:35] + node _T_770 = bits(_T_682, 63, 32) @[RegMapper.scala 135:29] + node _T_772 = neq(_T_770, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_773 = bits(_T_682, 63, 32) @[RegMapper.scala 136:29] + node _T_774 = not(_T_773) @[RegMapper.scala 136:45] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_777 = bits(_T_729, 63, 32) @[RegMapper.scala 137:28] + node _T_779 = neq(_T_777, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_780 = bits(_T_729, 63, 32) @[RegMapper.scala 138:28] + node _T_781 = not(_T_780) @[RegMapper.scala 138:44] + node _T_783 = eq(_T_781, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_784 = and(_T_531[1], _T_772) @[RegMapper.scala 140:69] + node _T_785 = and(_T_597[1], _T_779) @[RegMapper.scala 140:91] + node _T_788 = and(_T_542[1], _T_776) @[RegMapper.scala 141:62] + node _T_789 = and(_T_608[1], _T_783) @[RegMapper.scala 141:84] + node _T_790 = bits(_T_474.bits.data, 63, 32) @[RegMapper.scala 141:99] + when _T_789 : @[RegField.scala 70:88] + timecmp_0_1 <= _T_790 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_794 = eq(_T_772, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_795 = or(UInt<1>("h01"), _T_794) @[RegMapper.scala 142:31] + _T_553[1] <= _T_795 @[RegMapper.scala 142:18] + node _T_797 = eq(_T_776, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_798 = or(UInt<1>("h01"), _T_797) @[RegMapper.scala 143:31] + _T_564[1] <= _T_798 @[RegMapper.scala 143:18] + node _T_800 = eq(_T_779, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_801 = or(UInt<1>("h01"), _T_800) @[RegMapper.scala 144:31] + _T_575[1] <= _T_801 @[RegMapper.scala 144:18] + node _T_803 = eq(_T_783, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_804 = or(UInt<1>("h01"), _T_803) @[RegMapper.scala 145:31] + _T_586[1] <= _T_804 @[RegMapper.scala 145:18] + node _T_805 = shl(timecmp_0_1, 32) @[RegMapper.scala 150:47] + node _T_807 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_808 = and(_T_805, _T_807) @[RegMapper.scala 150:55] + node _T_809 = or(_T_769, _T_808) @[RegMapper.scala 150:35] + node _T_810 = bits(_T_682, 31, 0) @[RegMapper.scala 135:29] + node _T_812 = neq(_T_810, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_813 = bits(_T_682, 31, 0) @[RegMapper.scala 136:29] + node _T_814 = not(_T_813) @[RegMapper.scala 136:45] + node _T_816 = eq(_T_814, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_817 = bits(_T_729, 31, 0) @[RegMapper.scala 137:28] + node _T_819 = neq(_T_817, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_820 = bits(_T_729, 31, 0) @[RegMapper.scala 138:28] + node _T_821 = not(_T_820) @[RegMapper.scala 138:44] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_824 = and(_T_531[2], _T_812) @[RegMapper.scala 140:69] + node _T_825 = and(_T_597[2], _T_819) @[RegMapper.scala 140:91] + node _T_828 = and(_T_542[2], _T_816) @[RegMapper.scala 141:62] + node _T_829 = and(_T_608[2], _T_823) @[RegMapper.scala 141:84] + node _T_830 = bits(_T_474.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_829 : @[RegField.scala 70:88] + time_0 <= _T_830 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_834 = eq(_T_812, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_835 = or(UInt<1>("h01"), _T_834) @[RegMapper.scala 142:31] + _T_553[2] <= _T_835 @[RegMapper.scala 142:18] + node _T_837 = eq(_T_816, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_838 = or(UInt<1>("h01"), _T_837) @[RegMapper.scala 143:31] + _T_564[2] <= _T_838 @[RegMapper.scala 143:18] + node _T_840 = eq(_T_819, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_841 = or(UInt<1>("h01"), _T_840) @[RegMapper.scala 144:31] + _T_575[2] <= _T_841 @[RegMapper.scala 144:18] + node _T_843 = eq(_T_823, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_844 = or(UInt<1>("h01"), _T_843) @[RegMapper.scala 145:31] + _T_586[2] <= _T_844 @[RegMapper.scala 145:18] + node _T_845 = shl(time_0, 0) @[RegMapper.scala 150:47] + node _T_847 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_848 = and(_T_845, _T_847) @[RegMapper.scala 150:55] + node _T_849 = or(UInt<1>("h00"), _T_848) @[RegMapper.scala 150:35] + node _T_850 = bits(_T_682, 63, 32) @[RegMapper.scala 135:29] + node _T_852 = neq(_T_850, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_853 = bits(_T_682, 63, 32) @[RegMapper.scala 136:29] + node _T_854 = not(_T_853) @[RegMapper.scala 136:45] + node _T_856 = eq(_T_854, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_857 = bits(_T_729, 63, 32) @[RegMapper.scala 137:28] + node _T_859 = neq(_T_857, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_860 = bits(_T_729, 63, 32) @[RegMapper.scala 138:28] + node _T_861 = not(_T_860) @[RegMapper.scala 138:44] + node _T_863 = eq(_T_861, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_864 = and(_T_531[3], _T_852) @[RegMapper.scala 140:69] + node _T_865 = and(_T_597[3], _T_859) @[RegMapper.scala 140:91] + node _T_868 = and(_T_542[3], _T_856) @[RegMapper.scala 141:62] + node _T_869 = and(_T_608[3], _T_863) @[RegMapper.scala 141:84] + node _T_870 = bits(_T_474.bits.data, 63, 32) @[RegMapper.scala 141:99] + when _T_869 : @[RegField.scala 70:88] + time_1 <= _T_870 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_874 = eq(_T_852, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_875 = or(UInt<1>("h01"), _T_874) @[RegMapper.scala 142:31] + _T_553[3] <= _T_875 @[RegMapper.scala 142:18] + node _T_877 = eq(_T_856, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_878 = or(UInt<1>("h01"), _T_877) @[RegMapper.scala 143:31] + _T_564[3] <= _T_878 @[RegMapper.scala 143:18] + node _T_880 = eq(_T_859, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_881 = or(UInt<1>("h01"), _T_880) @[RegMapper.scala 144:31] + _T_575[3] <= _T_881 @[RegMapper.scala 144:18] + node _T_883 = eq(_T_863, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_884 = or(UInt<1>("h01"), _T_883) @[RegMapper.scala 145:31] + _T_586[3] <= _T_884 @[RegMapper.scala 145:18] + node _T_885 = shl(time_1, 32) @[RegMapper.scala 150:47] + node _T_887 = not(UInt<64>("h00")) @[RegMapper.scala 150:58] + node _T_888 = and(_T_885, _T_887) @[RegMapper.scala 150:55] + node _T_889 = or(_T_849, _T_888) @[RegMapper.scala 150:35] + node _T_890 = bits(_T_682, 31, 0) @[RegMapper.scala 135:29] + node _T_892 = neq(_T_890, UInt<1>("h00")) @[RegMapper.scala 135:44] + node _T_893 = bits(_T_682, 31, 0) @[RegMapper.scala 136:29] + node _T_894 = not(_T_893) @[RegMapper.scala 136:45] + node _T_896 = eq(_T_894, UInt<1>("h00")) @[RegMapper.scala 136:45] + node _T_897 = bits(_T_729, 31, 0) @[RegMapper.scala 137:28] + node _T_899 = neq(_T_897, UInt<1>("h00")) @[RegMapper.scala 137:43] + node _T_900 = bits(_T_729, 31, 0) @[RegMapper.scala 138:28] + node _T_901 = not(_T_900) @[RegMapper.scala 138:44] + node _T_903 = eq(_T_901, UInt<1>("h00")) @[RegMapper.scala 138:44] + node _T_904 = and(_T_531[4], _T_892) @[RegMapper.scala 140:69] + node _T_905 = and(_T_597[4], _T_899) @[RegMapper.scala 140:91] + node _T_908 = and(_T_542[4], _T_896) @[RegMapper.scala 141:62] + node _T_909 = and(_T_608[4], _T_903) @[RegMapper.scala 141:84] + node _T_910 = bits(_T_474.bits.data, 31, 0) @[RegMapper.scala 141:99] + when _T_909 : @[RegField.scala 70:88] + ipi_0 <= _T_910 @[RegField.scala 70:92] + skip @[RegField.scala 70:88] + node _T_914 = eq(_T_892, UInt<1>("h00")) @[RegMapper.scala 142:34] + node _T_915 = or(UInt<1>("h01"), _T_914) @[RegMapper.scala 142:31] + _T_553[4] <= _T_915 @[RegMapper.scala 142:18] + node _T_917 = eq(_T_896, UInt<1>("h00")) @[RegMapper.scala 143:34] + node _T_918 = or(UInt<1>("h01"), _T_917) @[RegMapper.scala 143:31] + _T_564[4] <= _T_918 @[RegMapper.scala 143:18] + node _T_920 = eq(_T_899, UInt<1>("h00")) @[RegMapper.scala 144:34] + node _T_921 = or(UInt<1>("h01"), _T_920) @[RegMapper.scala 144:31] + _T_575[4] <= _T_921 @[RegMapper.scala 144:18] + node _T_923 = eq(_T_903, UInt<1>("h00")) @[RegMapper.scala 145:34] + node _T_924 = or(UInt<1>("h01"), _T_923) @[RegMapper.scala 145:31] + _T_586[4] <= _T_924 @[RegMapper.scala 145:18] + node _T_925 = shl(ipi_0, 0) @[RegMapper.scala 150:47] + node _T_927 = not(UInt<32>("h00")) @[RegMapper.scala 150:58] + node _T_928 = and(_T_925, _T_927) @[RegMapper.scala 150:55] + node _T_929 = or(UInt<1>("h00"), _T_928) @[RegMapper.scala 150:35] + node _T_931 = eq(_T_523, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_932 = and(_T_553[4], UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_933 = or(_T_931, _T_932) @[RegMapper.scala 154:82] + node _T_935 = eq(_T_514, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_936 = and(_T_553[3], _T_553[2]) @[RegMapper.scala 154:98] + node _T_937 = and(_T_936, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_938 = or(_T_935, _T_937) @[RegMapper.scala 154:82] + node _T_940 = eq(_T_505, UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_941 = and(_T_553[1], _T_553[0]) @[RegMapper.scala 154:98] + node _T_942 = and(_T_941, UInt<1>("h01")) @[RegMapper.scala 154:98] + node _T_943 = or(_T_940, _T_942) @[RegMapper.scala 154:82] + node _T_945 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 154:68] + node _T_946 = or(_T_945, UInt<1>("h01")) @[RegMapper.scala 154:82] + wire _T_949 : UInt<1>[4] @[RegMapper.scala 154:24] + _T_949 is invalid @[RegMapper.scala 154:24] + _T_949[0] <= _T_933 @[RegMapper.scala 154:24] + _T_949[1] <= _T_938 @[RegMapper.scala 154:24] + _T_949[2] <= _T_943 @[RegMapper.scala 154:24] + _T_949[3] <= _T_946 @[RegMapper.scala 154:24] + node _T_957 = eq(_T_523, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_958 = and(_T_564[4], UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_959 = or(_T_957, _T_958) @[RegMapper.scala 155:82] + node _T_961 = eq(_T_514, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_962 = and(_T_564[3], _T_564[2]) @[RegMapper.scala 155:98] + node _T_963 = and(_T_962, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_964 = or(_T_961, _T_963) @[RegMapper.scala 155:82] + node _T_966 = eq(_T_505, UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_967 = and(_T_564[1], _T_564[0]) @[RegMapper.scala 155:98] + node _T_968 = and(_T_967, UInt<1>("h01")) @[RegMapper.scala 155:98] + node _T_969 = or(_T_966, _T_968) @[RegMapper.scala 155:82] + node _T_971 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 155:68] + node _T_972 = or(_T_971, UInt<1>("h01")) @[RegMapper.scala 155:82] + wire _T_975 : UInt<1>[4] @[RegMapper.scala 155:24] + _T_975 is invalid @[RegMapper.scala 155:24] + _T_975[0] <= _T_959 @[RegMapper.scala 155:24] + _T_975[1] <= _T_964 @[RegMapper.scala 155:24] + _T_975[2] <= _T_969 @[RegMapper.scala 155:24] + _T_975[3] <= _T_972 @[RegMapper.scala 155:24] + node _T_983 = eq(_T_527, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_984 = and(_T_575[4], UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_985 = or(_T_983, _T_984) @[RegMapper.scala 156:82] + node _T_987 = eq(_T_518, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_988 = and(_T_575[3], _T_575[2]) @[RegMapper.scala 156:98] + node _T_989 = and(_T_988, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_990 = or(_T_987, _T_989) @[RegMapper.scala 156:82] + node _T_992 = eq(_T_509, UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_993 = and(_T_575[1], _T_575[0]) @[RegMapper.scala 156:98] + node _T_994 = and(_T_993, UInt<1>("h01")) @[RegMapper.scala 156:98] + node _T_995 = or(_T_992, _T_994) @[RegMapper.scala 156:82] + node _T_997 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 156:68] + node _T_998 = or(_T_997, UInt<1>("h01")) @[RegMapper.scala 156:82] + wire _T_1001 : UInt<1>[4] @[RegMapper.scala 156:24] + _T_1001 is invalid @[RegMapper.scala 156:24] + _T_1001[0] <= _T_985 @[RegMapper.scala 156:24] + _T_1001[1] <= _T_990 @[RegMapper.scala 156:24] + _T_1001[2] <= _T_995 @[RegMapper.scala 156:24] + _T_1001[3] <= _T_998 @[RegMapper.scala 156:24] + node _T_1009 = eq(_T_527, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_1010 = and(_T_586[4], UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_1011 = or(_T_1009, _T_1010) @[RegMapper.scala 157:82] + node _T_1013 = eq(_T_518, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_1014 = and(_T_586[3], _T_586[2]) @[RegMapper.scala 157:98] + node _T_1015 = and(_T_1014, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_1016 = or(_T_1013, _T_1015) @[RegMapper.scala 157:82] + node _T_1018 = eq(_T_509, UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_1019 = and(_T_586[1], _T_586[0]) @[RegMapper.scala 157:98] + node _T_1020 = and(_T_1019, UInt<1>("h01")) @[RegMapper.scala 157:98] + node _T_1021 = or(_T_1018, _T_1020) @[RegMapper.scala 157:82] + node _T_1023 = eq(UInt<1>("h01"), UInt<1>("h00")) @[RegMapper.scala 157:68] + node _T_1024 = or(_T_1023, UInt<1>("h01")) @[RegMapper.scala 157:82] + wire _T_1027 : UInt<1>[4] @[RegMapper.scala 157:24] + _T_1027 is invalid @[RegMapper.scala 157:24] + _T_1027[0] <= _T_1011 @[RegMapper.scala 157:24] + _T_1027[1] <= _T_1016 @[RegMapper.scala 157:24] + _T_1027[2] <= _T_1021 @[RegMapper.scala 157:24] + _T_1027[3] <= _T_1024 @[RegMapper.scala 157:24] + node _T_1034 = bits(_T_474.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_1035 = bits(_T_474.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_1036 = bits(_T_474.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_1037 = bits(_T_474.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_1038 = bits(_T_474.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_1039 = bits(_T_474.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_1040 = bits(_T_474.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_1041 = bits(_T_474.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_1042 = bits(_T_474.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_1043 = bits(_T_474.bits.index, 9, 9) @[RegMapper.scala 82:29] + node _T_1044 = bits(_T_474.bits.index, 10, 10) @[RegMapper.scala 82:29] + node _T_1045 = bits(_T_474.bits.index, 11, 11) @[RegMapper.scala 82:29] + node _T_1046 = bits(_T_474.bits.index, 12, 12) @[RegMapper.scala 82:29] + node _T_1047 = cat(_T_1045, _T_1034) @[Cat.scala 30:58] + node _T_1048 = bits(_T_474.bits.index, 0, 0) @[RegMapper.scala 82:29] + node _T_1049 = bits(_T_474.bits.index, 1, 1) @[RegMapper.scala 82:29] + node _T_1050 = bits(_T_474.bits.index, 2, 2) @[RegMapper.scala 82:29] + node _T_1051 = bits(_T_474.bits.index, 3, 3) @[RegMapper.scala 82:29] + node _T_1052 = bits(_T_474.bits.index, 4, 4) @[RegMapper.scala 82:29] + node _T_1053 = bits(_T_474.bits.index, 5, 5) @[RegMapper.scala 82:29] + node _T_1054 = bits(_T_474.bits.index, 6, 6) @[RegMapper.scala 82:29] + node _T_1055 = bits(_T_474.bits.index, 7, 7) @[RegMapper.scala 82:29] + node _T_1056 = bits(_T_474.bits.index, 8, 8) @[RegMapper.scala 82:29] + node _T_1057 = bits(_T_474.bits.index, 9, 9) @[RegMapper.scala 82:29] + node _T_1058 = bits(_T_474.bits.index, 10, 10) @[RegMapper.scala 82:29] + node _T_1059 = bits(_T_474.bits.index, 11, 11) @[RegMapper.scala 82:29] + node _T_1060 = bits(_T_474.bits.index, 12, 12) @[RegMapper.scala 82:29] + node _T_1061 = cat(_T_1059, _T_1048) @[Cat.scala 30:58] + node _T_1064 = mux(_T_474.bits.read, _T_949[_T_1047], _T_975[_T_1047]) @[RegMapper.scala 160:21] + node _T_1067 = mux(_T_474.bits.read, _T_1001[_T_1061], _T_1027[_T_1061]) @[RegMapper.scala 161:21] + node _T_1068 = and(_T_474.ready, _T_1064) @[RegMapper.scala 164:32] + _T_398.ready <= _T_1068 @[RegMapper.scala 164:17] + node _T_1069 = and(_T_398.valid, _T_1064) @[RegMapper.scala 165:32] + _T_474.valid <= _T_1069 @[RegMapper.scala 165:17] + node _T_1070 = and(_T_438.ready, _T_1067) @[RegMapper.scala 166:32] + _T_474.ready <= _T_1070 @[RegMapper.scala 166:17] + node _T_1071 = and(_T_474.valid, _T_1067) @[RegMapper.scala 167:32] + _T_438.valid <= _T_1071 @[RegMapper.scala 167:17] + node _T_1073 = dshl(UInt<1>("h01"), _T_1047) @[OneHot.scala 47:11] + node _T_1074 = cat(_T_514, _T_523) @[Cat.scala 30:58] + node _T_1075 = cat(UInt<1>("h01"), _T_505) @[Cat.scala 30:58] + node _T_1076 = cat(_T_1075, _T_1074) @[Cat.scala 30:58] + node _T_1077 = and(_T_1073, _T_1076) @[RegMapper.scala 170:37] + node _T_1079 = dshl(UInt<1>("h01"), _T_1061) @[OneHot.scala 47:11] + node _T_1080 = cat(_T_518, _T_527) @[Cat.scala 30:58] + node _T_1081 = cat(UInt<1>("h01"), _T_509) @[Cat.scala 30:58] + node _T_1082 = cat(_T_1081, _T_1080) @[Cat.scala 30:58] + node _T_1083 = and(_T_1079, _T_1082) @[RegMapper.scala 171:37] + node _T_1084 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 175:31] + node _T_1085 = and(_T_1084, _T_474.bits.read) @[RegMapper.scala 175:46] + node _T_1086 = bits(_T_1077, 0, 0) @[RegMapper.scala 175:77] + node _T_1087 = and(_T_1085, _T_1086) @[RegMapper.scala 175:66] + node _T_1088 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 176:31] + node _T_1090 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_1091 = and(_T_1088, _T_1090) @[RegMapper.scala 176:46] + node _T_1092 = bits(_T_1077, 0, 0) @[RegMapper.scala 176:77] + node _T_1093 = and(_T_1091, _T_1092) @[RegMapper.scala 176:66] + node _T_1094 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 177:33] + node _T_1095 = and(_T_1094, _T_474.bits.read) @[RegMapper.scala 177:46] + node _T_1096 = bits(_T_1083, 0, 0) @[RegMapper.scala 177:77] + node _T_1097 = and(_T_1095, _T_1096) @[RegMapper.scala 177:66] + node _T_1098 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 178:33] + node _T_1100 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_1101 = and(_T_1098, _T_1100) @[RegMapper.scala 178:46] + node _T_1102 = bits(_T_1083, 0, 0) @[RegMapper.scala 178:77] + node _T_1103 = and(_T_1101, _T_1102) @[RegMapper.scala 178:66] + node _T_1104 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 175:31] + node _T_1105 = and(_T_1104, _T_474.bits.read) @[RegMapper.scala 175:46] + node _T_1106 = bits(_T_1077, 1, 1) @[RegMapper.scala 175:77] + node _T_1107 = and(_T_1105, _T_1106) @[RegMapper.scala 175:66] + node _T_1108 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 176:31] + node _T_1110 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_1111 = and(_T_1108, _T_1110) @[RegMapper.scala 176:46] + node _T_1112 = bits(_T_1077, 1, 1) @[RegMapper.scala 176:77] + node _T_1113 = and(_T_1111, _T_1112) @[RegMapper.scala 176:66] + node _T_1114 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 177:33] + node _T_1115 = and(_T_1114, _T_474.bits.read) @[RegMapper.scala 177:46] + node _T_1116 = bits(_T_1083, 1, 1) @[RegMapper.scala 177:77] + node _T_1117 = and(_T_1115, _T_1116) @[RegMapper.scala 177:66] + node _T_1118 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 178:33] + node _T_1120 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_1121 = and(_T_1118, _T_1120) @[RegMapper.scala 178:46] + node _T_1122 = bits(_T_1083, 1, 1) @[RegMapper.scala 178:77] + node _T_1123 = and(_T_1121, _T_1122) @[RegMapper.scala 178:66] + node _T_1124 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 175:31] + node _T_1125 = and(_T_1124, _T_474.bits.read) @[RegMapper.scala 175:46] + node _T_1126 = bits(_T_1077, 2, 2) @[RegMapper.scala 175:77] + node _T_1127 = and(_T_1125, _T_1126) @[RegMapper.scala 175:66] + node _T_1128 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 176:31] + node _T_1130 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_1131 = and(_T_1128, _T_1130) @[RegMapper.scala 176:46] + node _T_1132 = bits(_T_1077, 2, 2) @[RegMapper.scala 176:77] + node _T_1133 = and(_T_1131, _T_1132) @[RegMapper.scala 176:66] + node _T_1134 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 177:33] + node _T_1135 = and(_T_1134, _T_474.bits.read) @[RegMapper.scala 177:46] + node _T_1136 = bits(_T_1083, 2, 2) @[RegMapper.scala 177:77] + node _T_1137 = and(_T_1135, _T_1136) @[RegMapper.scala 177:66] + node _T_1138 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 178:33] + node _T_1140 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_1141 = and(_T_1138, _T_1140) @[RegMapper.scala 178:46] + node _T_1142 = bits(_T_1083, 2, 2) @[RegMapper.scala 178:77] + node _T_1143 = and(_T_1141, _T_1142) @[RegMapper.scala 178:66] + node _T_1144 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 175:31] + node _T_1145 = and(_T_1144, _T_474.bits.read) @[RegMapper.scala 175:46] + node _T_1146 = bits(_T_1077, 3, 3) @[RegMapper.scala 175:77] + node _T_1147 = and(_T_1145, _T_1146) @[RegMapper.scala 175:66] + node _T_1148 = and(_T_398.valid, _T_474.ready) @[RegMapper.scala 176:31] + node _T_1150 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 176:49] + node _T_1151 = and(_T_1148, _T_1150) @[RegMapper.scala 176:46] + node _T_1152 = bits(_T_1077, 3, 3) @[RegMapper.scala 176:77] + node _T_1153 = and(_T_1151, _T_1152) @[RegMapper.scala 176:66] + node _T_1154 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 177:33] + node _T_1155 = and(_T_1154, _T_474.bits.read) @[RegMapper.scala 177:46] + node _T_1156 = bits(_T_1083, 3, 3) @[RegMapper.scala 177:77] + node _T_1157 = and(_T_1155, _T_1156) @[RegMapper.scala 177:66] + node _T_1158 = and(_T_474.valid, _T_438.ready) @[RegMapper.scala 178:33] + node _T_1160 = eq(_T_474.bits.read, UInt<1>("h00")) @[RegMapper.scala 178:49] + node _T_1161 = and(_T_1158, _T_1160) @[RegMapper.scala 178:46] + node _T_1162 = bits(_T_1083, 3, 3) @[RegMapper.scala 178:77] + node _T_1163 = and(_T_1161, _T_1162) @[RegMapper.scala 178:66] + node _T_1164 = and(_T_1127, _T_553[1]) @[RegMapper.scala 184:66] + node _T_1165 = and(_T_1164, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_531[0] <= _T_1165 @[RegMapper.scala 184:18] + node _T_1166 = and(_T_1133, _T_564[1]) @[RegMapper.scala 185:66] + node _T_1167 = and(_T_1166, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_542[0] <= _T_1167 @[RegMapper.scala 185:18] + node _T_1168 = and(_T_1137, _T_575[1]) @[RegMapper.scala 186:66] + node _T_1169 = and(_T_1168, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_597[0] <= _T_1169 @[RegMapper.scala 186:18] + node _T_1170 = and(_T_1143, _T_586[1]) @[RegMapper.scala 187:66] + node _T_1171 = and(_T_1170, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_608[0] <= _T_1171 @[RegMapper.scala 187:18] + node _T_1172 = and(_T_1127, _T_553[0]) @[RegMapper.scala 184:66] + node _T_1173 = and(_T_1172, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_531[1] <= _T_1173 @[RegMapper.scala 184:18] + node _T_1174 = and(_T_1133, _T_564[0]) @[RegMapper.scala 185:66] + node _T_1175 = and(_T_1174, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_542[1] <= _T_1175 @[RegMapper.scala 185:18] + node _T_1176 = and(_T_1137, _T_575[0]) @[RegMapper.scala 186:66] + node _T_1177 = and(_T_1176, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_597[1] <= _T_1177 @[RegMapper.scala 186:18] + node _T_1178 = and(_T_1143, _T_586[0]) @[RegMapper.scala 187:66] + node _T_1179 = and(_T_1178, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_608[1] <= _T_1179 @[RegMapper.scala 187:18] + node _T_1180 = and(_T_1107, _T_553[3]) @[RegMapper.scala 184:66] + node _T_1181 = and(_T_1180, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_531[2] <= _T_1181 @[RegMapper.scala 184:18] + node _T_1182 = and(_T_1113, _T_564[3]) @[RegMapper.scala 185:66] + node _T_1183 = and(_T_1182, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_542[2] <= _T_1183 @[RegMapper.scala 185:18] + node _T_1184 = and(_T_1117, _T_575[3]) @[RegMapper.scala 186:66] + node _T_1185 = and(_T_1184, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_597[2] <= _T_1185 @[RegMapper.scala 186:18] + node _T_1186 = and(_T_1123, _T_586[3]) @[RegMapper.scala 187:66] + node _T_1187 = and(_T_1186, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_608[2] <= _T_1187 @[RegMapper.scala 187:18] + node _T_1188 = and(_T_1107, _T_553[2]) @[RegMapper.scala 184:66] + node _T_1189 = and(_T_1188, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_531[3] <= _T_1189 @[RegMapper.scala 184:18] + node _T_1190 = and(_T_1113, _T_564[2]) @[RegMapper.scala 185:66] + node _T_1191 = and(_T_1190, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_542[3] <= _T_1191 @[RegMapper.scala 185:18] + node _T_1192 = and(_T_1117, _T_575[2]) @[RegMapper.scala 186:66] + node _T_1193 = and(_T_1192, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_597[3] <= _T_1193 @[RegMapper.scala 186:18] + node _T_1194 = and(_T_1123, _T_586[2]) @[RegMapper.scala 187:66] + node _T_1195 = and(_T_1194, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_608[3] <= _T_1195 @[RegMapper.scala 187:18] + node _T_1196 = and(_T_1087, UInt<1>("h01")) @[RegMapper.scala 184:66] + _T_531[4] <= _T_1196 @[RegMapper.scala 184:18] + node _T_1197 = and(_T_1093, UInt<1>("h01")) @[RegMapper.scala 185:66] + _T_542[4] <= _T_1197 @[RegMapper.scala 185:18] + node _T_1198 = and(_T_1097, UInt<1>("h01")) @[RegMapper.scala 186:66] + _T_597[4] <= _T_1198 @[RegMapper.scala 186:18] + node _T_1199 = and(_T_1103, UInt<1>("h01")) @[RegMapper.scala 187:66] + _T_608[4] <= _T_1199 @[RegMapper.scala 187:18] + _T_438.bits.read <= _T_474.bits.read @[RegMapper.scala 190:20] + wire _T_1202 : UInt<1>[4] @[RegMapper.scala 191:30] + _T_1202 is invalid @[RegMapper.scala 191:30] + _T_1202[0] <= _T_527 @[RegMapper.scala 191:30] + _T_1202[1] <= _T_518 @[RegMapper.scala 191:30] + _T_1202[2] <= _T_509 @[RegMapper.scala 191:30] + _T_1202[3] <= UInt<1>("h01") @[RegMapper.scala 191:30] + wire _T_1212 : UInt<64>[4] @[RegMapper.scala 191:54] + _T_1212 is invalid @[RegMapper.scala 191:54] + _T_1212[0] <= _T_929 @[RegMapper.scala 191:54] + _T_1212[1] <= _T_889 @[RegMapper.scala 191:54] + _T_1212[2] <= _T_809 @[RegMapper.scala 191:54] + _T_1212[3] <= UInt<1>("h00") @[RegMapper.scala 191:54] + node _T_1221 = mux(_T_1202[_T_1061], _T_1212[_T_1061], UInt<1>("h00")) @[RegMapper.scala 191:26] + _T_438.bits.data <= _T_1221 @[RegMapper.scala 191:20] + _T_438.bits.extra <= _T_474.bits.extra @[RegMapper.scala 192:20] + _T_398.valid <= io.in.0.a.valid @[RegisterRouter.scala 58:15] + io.in.0.a.ready <= _T_398.ready @[RegisterRouter.scala 59:15] + io.in.0.d.valid <= _T_438.valid @[RegisterRouter.scala 60:15] + _T_438.ready <= io.in.0.d.ready @[RegisterRouter.scala 61:15] + node _T_1222 = bits(_T_438.bits.extra, 11, 9) @[RegisterRouter.scala 65:35] + node _T_1224 = bits(_T_438.bits.extra, 8, 3) @[RegisterRouter.scala 67:35] + node _T_1225 = bits(_T_438.bits.extra, 2, 0) @[RegisterRouter.scala 68:35] + wire _T_1236 : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>} @[Edges.scala 617:17] + _T_1236 is invalid @[Edges.scala 617:17] + _T_1236.opcode <= UInt<1>("h00") @[Edges.scala 618:15] + _T_1236.param <= UInt<1>("h00") @[Edges.scala 619:15] + _T_1236.size <= _T_1225 @[Edges.scala 620:15] + _T_1236.source <= _T_1224 @[Edges.scala 621:15] + _T_1236.sink <= UInt<1>("h00") @[Edges.scala 622:15] + node _T_1247 = bits(_T_1222, 2, 0) @[Edges.scala 172:47] + _T_1236.addr_lo <= _T_1247 @[Edges.scala 623:15] + _T_1236.data <= UInt<1>("h00") @[Edges.scala 624:15] + _T_1236.error <= UInt<1>("h00") @[Edges.scala 625:15] + io.in.0.d.bits <- _T_1236 @[RegisterRouter.scala 64:12] + io.in.0.d.bits.data <= _T_438.bits.data @[RegisterRouter.scala 71:17] + node _T_1251 = mux(_T_438.bits.read, UInt<1>("h01"), UInt<1>("h00")) @[RegisterRouter.scala 72:25] + io.in.0.d.bits.opcode <= _T_1251 @[RegisterRouter.scala 72:19] + io.in.0.b.valid <= UInt<1>("h00") @[RegisterRouter.scala 75:25] + io.in.0.c.ready <= UInt<1>("h01") @[RegisterRouter.scala 76:25] + io.in.0.e.ready <= UInt<1>("h01") @[RegisterRouter.scala 77:25] + + module Repeater_3 : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLFragmenter_debug : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg _T_531 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + reg _T_533 : UInt, clock @[Fragmenter.scala 136:22] + node _T_534 = bits(io.out.0.d.bits.source, 2, 0) @[Fragmenter.scala 137:39] + node _T_536 = eq(_T_531, UInt<1>("h00")) @[Fragmenter.scala 138:27] + node _T_538 = bits(io.out.0.d.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_539 = dshl(UInt<1>("h01"), _T_538) @[OneHot.scala 49:12] + node _T_540 = bits(_T_539, 3, 0) @[OneHot.scala 49:37] + node _T_542 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_543 = dshl(_T_542, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_544 = bits(_T_543, 2, 0) @[package.scala 19:76] + node _T_545 = not(_T_544) @[package.scala 19:40] + node _T_546 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_547 = shl(_T_534, 0) @[Fragmenter.scala 144:38] + node _T_548 = shr(_T_545, 3) @[Fragmenter.scala 145:34] + node _T_550 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Fragmenter.scala 146:15] + node _T_551 = and(_T_547, _T_548) @[Fragmenter.scala 146:48] + node _T_553 = eq(_T_551, UInt<1>("h00")) @[Fragmenter.scala 146:63] + node _T_554 = or(_T_550, _T_553) @[Fragmenter.scala 146:28] + node _T_555 = or(_T_554, reset) @[Fragmenter.scala 146:14] + node _T_557 = eq(_T_555, UInt<1>("h00")) @[Fragmenter.scala 146:14] + when _T_557 : @[Fragmenter.scala 146:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:146 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n") @[Fragmenter.scala 146:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 146:14] + skip @[Fragmenter.scala 146:14] + node _T_559 = mux(_T_546, _T_548, UInt<1>("h00")) @[Fragmenter.scala 147:48] + node _T_560 = or(_T_547, _T_559) @[Fragmenter.scala 147:43] + node _T_562 = shr(_T_540, 3) @[Fragmenter.scala 148:58] + node _T_563 = mux(_T_546, UInt<1>("h01"), _T_562) @[Fragmenter.scala 148:30] + node _T_564 = shl(_T_534, 3) @[Fragmenter.scala 150:45] + node _T_565 = or(_T_564, _T_545) @[Fragmenter.scala 150:67] + node _T_566 = shl(_T_565, 1) @[package.scala 17:29] + node _T_568 = or(_T_566, UInt<1>("h01")) @[package.scala 17:34] + node _T_570 = cat(UInt<1>("h00"), _T_565) @[Cat.scala 30:58] + node _T_571 = not(_T_570) @[package.scala 17:47] + node _T_572 = and(_T_568, _T_571) @[package.scala 17:45] + node _T_573 = bits(_T_572, 6, 4) @[OneHot.scala 26:18] + node _T_574 = bits(_T_572, 3, 0) @[OneHot.scala 27:18] + node _T_576 = neq(_T_573, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_577 = or(_T_573, _T_574) @[OneHot.scala 28:28] + node _T_578 = bits(_T_577, 3, 2) @[OneHot.scala 26:18] + node _T_579 = bits(_T_577, 1, 0) @[OneHot.scala 27:18] + node _T_581 = neq(_T_578, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_582 = or(_T_578, _T_579) @[OneHot.scala 28:28] + node _T_583 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_584 = cat(_T_581, _T_583) @[Cat.scala 30:58] + node _T_585 = cat(_T_576, _T_584) @[Cat.scala 30:58] + node _T_586 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_586 : @[Fragmenter.scala 152:27] + node _T_587 = sub(_T_531, _T_563) @[Fragmenter.scala 153:53] + node _T_588 = asUInt(_T_587) @[Fragmenter.scala 153:53] + node _T_589 = tail(_T_588, 1) @[Fragmenter.scala 153:53] + node _T_590 = mux(_T_536, _T_560, _T_589) @[Fragmenter.scala 153:22] + _T_531 <= _T_590 @[Fragmenter.scala 153:16] + when _T_536 : @[Fragmenter.scala 154:23] + _T_533 <= _T_585 @[Fragmenter.scala 154:31] + skip @[Fragmenter.scala 154:23] + skip @[Fragmenter.scala 152:27] + node _T_592 = eq(_T_546, UInt<1>("h00")) @[Fragmenter.scala 158:18] + node _T_594 = neq(_T_534, UInt<1>("h00")) @[Fragmenter.scala 158:41] + node _T_595 = and(_T_592, _T_594) @[Fragmenter.scala 158:28] + node _T_596 = or(io.in.0.d.ready, _T_595) @[Fragmenter.scala 159:33] + io.out.0.d.ready <= _T_596 @[Fragmenter.scala 159:19] + node _T_598 = eq(_T_595, UInt<1>("h00")) @[Fragmenter.scala 160:37] + node _T_599 = and(io.out.0.d.valid, _T_598) @[Fragmenter.scala 160:34] + io.in.0.d.valid <= _T_599 @[Fragmenter.scala 160:19] + io.in.0.d.bits <- io.out.0.d.bits @[Fragmenter.scala 161:19] + node _T_600 = not(_T_545) @[Fragmenter.scala 162:49] + node _T_601 = and(io.out.0.d.bits.addr_lo, _T_600) @[Fragmenter.scala 162:47] + io.in.0.d.bits.addr_lo <= _T_601 @[Fragmenter.scala 162:25] + node _T_602 = shr(io.out.0.d.bits.source, 3) @[Fragmenter.scala 163:45] + io.in.0.d.bits.source <= _T_602 @[Fragmenter.scala 163:24] + node _T_603 = mux(_T_536, _T_585, _T_533) @[Fragmenter.scala 164:30] + io.in.0.d.bits.size <= _T_603 @[Fragmenter.scala 164:24] + reg _T_605 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_606 = or(_T_605, io.out.0.d.bits.error) @[Fragmenter.scala 168:29] + node _T_607 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_607 : @[Fragmenter.scala 169:27] + node _T_609 = mux(_T_595, _T_606, UInt<1>("h00")) @[Fragmenter.scala 169:43] + _T_605 <= _T_609 @[Fragmenter.scala 169:37] + skip @[Fragmenter.scala 169:27] + io.in.0.d.bits.error <= _T_606 @[Fragmenter.scala 170:23] + inst Repeater of Repeater_3 @[Fragmenter.scala 190:28] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.enq <- io.in.0.a @[Fragmenter.scala 191:23] + node _T_615 = xor(Repeater.io.deq.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_616 = cvt(_T_615) @[Parameters.scala 117:49] + node _T_618 = and(_T_616, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_619 = asSInt(_T_618) @[Parameters.scala 117:52] + node _T_621 = eq(_T_619, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_624 : UInt<1>[1] @[Parameters.scala 112:36] + _T_624 is invalid @[Parameters.scala 112:36] + _T_624[0] <= _T_621 @[Parameters.scala 112:36] + node _T_634 = eq(UInt<3>("h05"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_635 = mux(_T_634, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 46:16] + node _T_636 = eq(UInt<3>("h04"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_637 = mux(_T_636, UInt<2>("h03"), _T_635) @[Mux.scala 46:16] + node _T_638 = eq(UInt<2>("h03"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_639 = mux(_T_638, UInt<2>("h03"), _T_637) @[Mux.scala 46:16] + node _T_640 = eq(UInt<2>("h02"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_641 = mux(_T_640, UInt<2>("h03"), _T_639) @[Mux.scala 46:16] + node _T_642 = eq(UInt<1>("h01"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_643 = mux(_T_642, UInt<2>("h03"), _T_641) @[Mux.scala 46:16] + node _T_644 = eq(UInt<1>("h00"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_645 = mux(_T_644, UInt<2>("h03"), _T_643) @[Mux.scala 46:16] + node _T_646 = gt(Repeater.io.deq.bits.size, _T_645) @[Fragmenter.scala 213:29] + node _T_647 = mux(_T_646, _T_645, Repeater.io.deq.bits.size) @[Fragmenter.scala 213:22] + node _T_649 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_650 = dshl(_T_649, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_651 = bits(_T_650, 5, 0) @[package.scala 19:76] + node _T_652 = not(_T_651) @[package.scala 19:40] + node _T_654 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_655 = dshl(_T_654, _T_647) @[package.scala 19:71] + node _T_656 = bits(_T_655, 2, 0) @[package.scala 19:76] + node _T_657 = not(_T_656) @[package.scala 19:40] + node _T_658 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_660 = eq(_T_658, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_662 = mux(_T_660, UInt<1>("h00"), _T_657) @[Fragmenter.scala 217:22] + reg _T_664 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[Fragmenter.scala 220:27] + node _T_667 = shr(_T_652, 3) @[Fragmenter.scala 221:46] + node _T_669 = sub(_T_664, UInt<1>("h01")) @[Fragmenter.scala 221:77] + node _T_670 = asUInt(_T_669) @[Fragmenter.scala 221:77] + node _T_671 = tail(_T_670, 1) @[Fragmenter.scala 221:77] + node _T_672 = mux(_T_666, _T_667, _T_671) @[Fragmenter.scala 221:28] + node _T_673 = not(_T_672) @[Fragmenter.scala 222:26] + node _T_674 = shr(_T_662, 3) @[Fragmenter.scala 222:48] + node _T_675 = or(_T_673, _T_674) @[Fragmenter.scala 222:39] + node _T_676 = not(_T_675) @[Fragmenter.scala 222:24] + node _T_677 = shr(_T_672, 0) @[Fragmenter.scala 223:38] + node _T_678 = not(_T_677) @[Fragmenter.scala 223:24] + node _T_679 = shr(_T_657, 3) @[Fragmenter.scala 223:82] + node _T_680 = or(_T_678, _T_679) @[Fragmenter.scala 223:70] + node _T_681 = not(_T_680) @[Fragmenter.scala 223:22] + node _T_682 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Fragmenter.scala 225:27] + _T_664 <= _T_676 @[Fragmenter.scala 225:36] + skip @[Fragmenter.scala 225:27] + node _T_684 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 227:29] + node _T_686 = neq(_T_681, UInt<1>("h00")) @[Fragmenter.scala 227:51] + node _T_687 = and(_T_684, _T_686) @[Fragmenter.scala 227:39] + Repeater.io.repeat <= _T_687 @[Fragmenter.scala 227:26] + io.out.0.a <- Repeater.io.deq @[Fragmenter.scala 228:13] + node _T_688 = not(_T_681) @[Fragmenter.scala 229:50] + node _T_689 = shl(_T_688, 3) @[Fragmenter.scala 229:60] + node _T_690 = and(_T_689, _T_652) @[Fragmenter.scala 229:81] + node _T_691 = or(Repeater.io.deq.bits.address, _T_690) @[Fragmenter.scala 229:47] + io.out.0.a.bits.address <= _T_691 @[Fragmenter.scala 229:26] + node _T_692 = cat(Repeater.io.deq.bits.source, _T_681) @[Cat.scala 30:58] + io.out.0.a.bits.source <= _T_692 @[Fragmenter.scala 230:25] + io.out.0.a.bits.size <= _T_647 @[Fragmenter.scala 231:23] + node _T_694 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 234:15] + node _T_696 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 234:36] + node _T_697 = or(_T_694, _T_696) @[Fragmenter.scala 234:33] + node _T_698 = or(_T_697, reset) @[Fragmenter.scala 234:14] + node _T_700 = eq(_T_698, UInt<1>("h00")) @[Fragmenter.scala 234:14] + when _T_700 : @[Fragmenter.scala 234:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:234 assert (!repeater.io.full || !aHasData)\n") @[Fragmenter.scala 234:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 234:14] + skip @[Fragmenter.scala 234:14] + io.out.0.a.bits.data <= io.in.0.a.bits.data @[Fragmenter.scala 235:23] + node _T_703 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 237:15] + node _T_704 = eq(Repeater.io.deq.bits.mask, UInt<8>("h0ff")) @[Fragmenter.scala 237:51] + node _T_705 = or(_T_703, _T_704) @[Fragmenter.scala 237:33] + node _T_706 = or(_T_705, reset) @[Fragmenter.scala 237:14] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 237:14] + when _T_708 : @[Fragmenter.scala 237:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") @[Fragmenter.scala 237:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 237:14] + skip @[Fragmenter.scala 237:14] + node _T_709 = mux(Repeater.io.full, UInt<8>("h0ff"), io.in.0.a.bits.mask) @[Fragmenter.scala 238:29] + io.out.0.a.bits.mask <= _T_709 @[Fragmenter.scala 238:23] + io.in.0.b.valid <= UInt<1>("h00") @[Fragmenter.scala 241:18] + io.in.0.c.ready <= UInt<1>("h01") @[Fragmenter.scala 242:18] + io.in.0.e.ready <= UInt<1>("h01") @[Fragmenter.scala 243:18] + io.out.0.b.ready <= UInt<1>("h01") @[Fragmenter.scala 244:19] + io.out.0.c.valid <= UInt<1>("h00") @[Fragmenter.scala 245:19] + io.out.0.e.valid <= UInt<1>("h00") @[Fragmenter.scala 246:19] + + module TLMonitor_25 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 21:61] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 21:61] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_608 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:61] + when _T_708 : @[RISCVPlatform.scala 21:61] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[RISCVPlatform.scala 21:61] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_725 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_726 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_728 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_731 = or(_T_730, reset) @[RISCVPlatform.scala 21:61] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_733 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_734 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_736 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[RISCVPlatform.scala 21:61] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_741 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_742 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 21:61] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_745 = or(_T_744, reset) @[RISCVPlatform.scala 21:61] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_747 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:61] + when _T_749 : @[RISCVPlatform.scala 21:61] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[RISCVPlatform.scala 21:61] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_770 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_771 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_773 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_774 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_776 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_779 = or(_T_778, reset) @[RISCVPlatform.scala 21:61] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_781 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 21:61] + node _T_783 = or(_T_782, reset) @[RISCVPlatform.scala 21:61] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_785 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_787 : @[RISCVPlatform.scala 21:61] + node _T_790 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_792 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_793 = and(_T_790, _T_792) @[Parameters.scala 63:37] + node _T_794 = or(UInt<1>("h00"), _T_793) @[Parameters.scala 132:31] + node _T_796 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_797 = cvt(_T_796) @[Parameters.scala 117:49] + node _T_799 = and(_T_797, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_800 = asSInt(_T_799) @[Parameters.scala 117:52] + node _T_802 = eq(_T_800, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = and(_T_794, _T_802) @[Parameters.scala 132:56] + node _T_805 = or(UInt<1>("h00"), _T_803) @[Parameters.scala 134:30] + node _T_806 = or(_T_805, reset) @[RISCVPlatform.scala 21:61] + node _T_808 = eq(_T_806, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_808 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_809 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_811 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_812 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_814 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_816 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_817 = or(_T_816, reset) @[RISCVPlatform.scala 21:61] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_819 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_820 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 21:61] + node _T_821 = or(_T_820, reset) @[RISCVPlatform.scala 21:61] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_823 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_825 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + when _T_825 : @[RISCVPlatform.scala 21:61] + node _T_828 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_830 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_831 = and(_T_828, _T_830) @[Parameters.scala 63:37] + node _T_832 = or(UInt<1>("h00"), _T_831) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_841) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, reset) @[RISCVPlatform.scala 21:61] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_846 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_847 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_849 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_850 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_852 = eq(_T_850, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_852 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_854 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_855 = or(_T_854, reset) @[RISCVPlatform.scala 21:61] + node _T_857 = eq(_T_855, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_857 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_858 = not(_T_706) @[RISCVPlatform.scala 21:61] + node _T_859 = and(io.in[0].a.bits.mask, _T_858) @[RISCVPlatform.scala 21:61] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_862 = or(_T_861, reset) @[RISCVPlatform.scala 21:61] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_864 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_866 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:61] + when _T_866 : @[RISCVPlatform.scala 21:61] + node _T_869 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_871 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_872 = cvt(_T_871) @[Parameters.scala 117:49] + node _T_874 = and(_T_872, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_875 = asSInt(_T_874) @[Parameters.scala 117:52] + node _T_877 = eq(_T_875, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = and(_T_869, _T_877) @[Parameters.scala 132:56] + node _T_880 = or(UInt<1>("h00"), _T_878) @[Parameters.scala 134:30] + node _T_881 = or(_T_880, reset) @[RISCVPlatform.scala 21:61] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_883 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_884 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_886 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_887 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_889 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_891 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_892 = or(_T_891, reset) @[RISCVPlatform.scala 21:61] + node _T_894 = eq(_T_892, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_894 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_895 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 21:61] + node _T_896 = or(_T_895, reset) @[RISCVPlatform.scala 21:61] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_898 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_900 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + when _T_900 : @[RISCVPlatform.scala 21:61] + node _T_903 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_905 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_906 = cvt(_T_905) @[Parameters.scala 117:49] + node _T_908 = and(_T_906, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_909 = asSInt(_T_908) @[Parameters.scala 117:52] + node _T_911 = eq(_T_909, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = and(_T_903, _T_911) @[Parameters.scala 132:56] + node _T_914 = or(UInt<1>("h00"), _T_912) @[Parameters.scala 134:30] + node _T_915 = or(_T_914, reset) @[RISCVPlatform.scala 21:61] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_917 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_918 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_920 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_921 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_923 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_925 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_926 = or(_T_925, reset) @[RISCVPlatform.scala 21:61] + node _T_928 = eq(_T_926, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_928 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_929 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 21:61] + node _T_930 = or(_T_929, reset) @[RISCVPlatform.scala 21:61] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_932 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:61] + when _T_934 : @[RISCVPlatform.scala 21:61] + node _T_937 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_939 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_940 = cvt(_T_939) @[Parameters.scala 117:49] + node _T_942 = and(_T_940, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_943 = asSInt(_T_942) @[Parameters.scala 117:52] + node _T_945 = eq(_T_943, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_946 = and(_T_937, _T_945) @[Parameters.scala 132:56] + node _T_948 = or(UInt<1>("h00"), _T_946) @[Parameters.scala 134:30] + node _T_949 = or(_T_948, reset) @[RISCVPlatform.scala 21:61] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_951 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_952 = or(_T_630, reset) @[RISCVPlatform.scala 21:61] + node _T_954 = eq(_T_952, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_954 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_955 = or(_T_638, reset) @[RISCVPlatform.scala 21:61] + node _T_957 = eq(_T_955, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_957 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_958 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 21:61] + node _T_959 = or(_T_958, reset) @[RISCVPlatform.scala 21:61] + node _T_961 = eq(_T_959, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_961 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + when io.in[0].b.valid : @[RISCVPlatform.scala 21:61] + node _T_963 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_964 = or(_T_963, reset) @[RISCVPlatform.scala 21:61] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_966 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_968 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_977 : UInt<1>[1] @[Parameters.scala 110:36] + _T_977 is invalid @[Parameters.scala 110:36] + _T_977[0] <= _T_974 @[Parameters.scala 110:36] + node _T_982 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_983 = dshl(_T_982, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_984 = bits(_T_983, 5, 0) @[package.scala 19:76] + node _T_985 = not(_T_984) @[package.scala 19:40] + node _T_986 = and(io.in[0].b.bits.address, _T_985) @[Edges.scala 17:16] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_990 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_991 = dshl(UInt<1>("h01"), _T_990) @[OneHot.scala 49:12] + node _T_992 = bits(_T_991, 2, 0) @[OneHot.scala 49:37] + node _T_994 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_996 = bits(_T_992, 2, 2) @[package.scala 44:26] + node _T_997 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_999 = eq(_T_997, UInt<1>("h00")) @[package.scala 46:20] + node _T_1000 = and(UInt<1>("h01"), _T_999) @[package.scala 49:27] + node _T_1001 = and(_T_996, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_994, _T_1001) @[package.scala 50:29] + node _T_1003 = and(UInt<1>("h01"), _T_997) @[package.scala 49:27] + node _T_1004 = and(_T_996, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_994, _T_1004) @[package.scala 50:29] + node _T_1006 = bits(_T_992, 1, 1) @[package.scala 44:26] + node _T_1007 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1009 = eq(_T_1007, UInt<1>("h00")) @[package.scala 46:20] + node _T_1010 = and(_T_1000, _T_1009) @[package.scala 49:27] + node _T_1011 = and(_T_1006, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_1002, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_1000, _T_1007) @[package.scala 49:27] + node _T_1014 = and(_T_1006, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_1002, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_1003, _T_1009) @[package.scala 49:27] + node _T_1017 = and(_T_1006, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_1005, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1003, _T_1007) @[package.scala 49:27] + node _T_1020 = and(_T_1006, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1005, _T_1020) @[package.scala 50:29] + node _T_1022 = bits(_T_992, 0, 0) @[package.scala 44:26] + node _T_1023 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[package.scala 46:20] + node _T_1026 = and(_T_1010, _T_1025) @[package.scala 49:27] + node _T_1027 = and(_T_1022, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1012, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1010, _T_1023) @[package.scala 49:27] + node _T_1030 = and(_T_1022, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1012, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1013, _T_1025) @[package.scala 49:27] + node _T_1033 = and(_T_1022, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1015, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1013, _T_1023) @[package.scala 49:27] + node _T_1036 = and(_T_1022, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1015, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1016, _T_1025) @[package.scala 49:27] + node _T_1039 = and(_T_1022, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1018, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1016, _T_1023) @[package.scala 49:27] + node _T_1042 = and(_T_1022, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1018, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1019, _T_1025) @[package.scala 49:27] + node _T_1045 = and(_T_1022, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1021, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1019, _T_1023) @[package.scala 49:27] + node _T_1048 = and(_T_1022, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1021, _T_1048) @[package.scala 50:29] + node _T_1050 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1050) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1054 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1058 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:61] + when _T_1058 : @[RISCVPlatform.scala 21:61] + node _T_1060 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1061 = not(_T_1060) @[Parameters.scala 37:9] + node _T_1063 = or(_T_1061, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1064 = not(_T_1063) @[Parameters.scala 37:7] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1068 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1070 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1073 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1073 is invalid @[Parameters.scala 228:27] + _T_1073[0] <= _T_1066 @[Parameters.scala 228:27] + _T_1073[1] <= _T_1068 @[Parameters.scala 228:27] + _T_1073[2] <= _T_1070 @[Parameters.scala 228:27] + node _T_1081 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1083 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1084 = and(_T_1081, _T_1083) @[Parameters.scala 63:37] + node _T_1087 = mux(_T_1073[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1089 = mux(_T_1073[1], _T_1084, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1073[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1093 = or(_T_1087, _T_1089) @[Mux.scala 19:72] + node _T_1094 = or(_T_1093, _T_1091) @[Mux.scala 19:72] + wire _T_1096 : UInt<1> @[Mux.scala 19:72] + _T_1096 is invalid @[Mux.scala 19:72] + _T_1096 <= _T_1094 @[Mux.scala 19:72] + node _T_1097 = or(_T_1096, reset) @[RISCVPlatform.scala 21:61] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1099 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1100 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1102 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1104 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1105 = or(_T_1104, reset) @[RISCVPlatform.scala 21:61] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1107 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1108 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1110 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1112 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1113 = or(_T_1112, reset) @[RISCVPlatform.scala 21:61] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1115 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1116 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 21:61] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1119 = or(_T_1118, reset) @[RISCVPlatform.scala 21:61] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1121 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1123 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:61] + when _T_1123 : @[RISCVPlatform.scala 21:61] + node _T_1125 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1127 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1128 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1130 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1131 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1133 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1135 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1136 = or(_T_1135, reset) @[RISCVPlatform.scala 21:61] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1138 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1139 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 21:61] + node _T_1140 = or(_T_1139, reset) @[RISCVPlatform.scala 21:61] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1142 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1144 : @[RISCVPlatform.scala 21:61] + node _T_1146 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1148 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1149 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1151 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1152 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1154 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1156 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1157 = or(_T_1156, reset) @[RISCVPlatform.scala 21:61] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1159 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 21:61] + node _T_1161 = or(_T_1160, reset) @[RISCVPlatform.scala 21:61] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1163 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + when _T_1165 : @[RISCVPlatform.scala 21:61] + node _T_1167 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1169 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1170 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1172 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1173 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1175 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1177 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1178 = or(_T_1177, reset) @[RISCVPlatform.scala 21:61] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1180 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1181 = not(_T_1056) @[RISCVPlatform.scala 21:61] + node _T_1182 = and(io.in[0].b.bits.mask, _T_1181) @[RISCVPlatform.scala 21:61] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 21:61] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1187 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:61] + when _T_1189 : @[RISCVPlatform.scala 21:61] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1193 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1194 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1196 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1197 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1199 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 21:61] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1204 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1205 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 21:61] + node _T_1206 = or(_T_1205, reset) @[RISCVPlatform.scala 21:61] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1208 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1210 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + when _T_1210 : @[RISCVPlatform.scala 21:61] + node _T_1212 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1214 = eq(_T_1212, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1214 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1215 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1217 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1218 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1220 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1222 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1223 = or(_T_1222, reset) @[RISCVPlatform.scala 21:61] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1225 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1226 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 21:61] + node _T_1227 = or(_T_1226, reset) @[RISCVPlatform.scala 21:61] + node _T_1229 = eq(_T_1227, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1229 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1231 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:61] + when _T_1231 : @[RISCVPlatform.scala 21:61] + node _T_1233 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:61] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1235 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1236 = or(_T_977[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1238 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1239 = or(_T_988, reset) @[RISCVPlatform.scala 21:61] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1241 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1242 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 21:61] + node _T_1243 = or(_T_1242, reset) @[RISCVPlatform.scala 21:61] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1245 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + when io.in[0].c.valid : @[RISCVPlatform.scala 21:61] + node _T_1247 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1248 = or(_T_1247, reset) @[RISCVPlatform.scala 21:61] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1250 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1252 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1253 = not(_T_1252) @[Parameters.scala 37:9] + node _T_1255 = or(_T_1253, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1256 = not(_T_1255) @[Parameters.scala 37:7] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1260 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1262 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1265 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1265 is invalid @[Parameters.scala 228:27] + _T_1265[0] <= _T_1258 @[Parameters.scala 228:27] + _T_1265[1] <= _T_1260 @[Parameters.scala 228:27] + _T_1265[2] <= _T_1262 @[Parameters.scala 228:27] + node _T_1271 = or(_T_1265[0], _T_1265[1]) @[Parameters.scala 229:46] + node _T_1272 = or(_T_1271, _T_1265[2]) @[Parameters.scala 229:46] + node _T_1274 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1275 = dshl(_T_1274, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1276 = bits(_T_1275, 5, 0) @[package.scala 19:76] + node _T_1277 = not(_T_1276) @[package.scala 19:40] + node _T_1278 = and(io.in[0].c.bits.address, _T_1277) @[Edges.scala 17:16] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1282 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1283 = cvt(_T_1282) @[Parameters.scala 117:49] + node _T_1285 = and(_T_1283, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1286 = asSInt(_T_1285) @[Parameters.scala 117:52] + node _T_1288 = eq(_T_1286, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1291 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1291 is invalid @[Parameters.scala 110:36] + _T_1291[0] <= _T_1288 @[Parameters.scala 110:36] + node _T_1296 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:61] + when _T_1296 : @[RISCVPlatform.scala 21:61] + node _T_1297 = or(_T_1291[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1299 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1300 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1302 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1304 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1305 = or(_T_1304, reset) @[RISCVPlatform.scala 21:61] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1307 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1308 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1310 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1312 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1313 = or(_T_1312, reset) @[RISCVPlatform.scala 21:61] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1315 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1317 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1318 = or(_T_1317, reset) @[RISCVPlatform.scala 21:61] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1320 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1322 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:61] + when _T_1322 : @[RISCVPlatform.scala 21:61] + node _T_1323 = or(_T_1291[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1325 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1326 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1328 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1330 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1331 = or(_T_1330, reset) @[RISCVPlatform.scala 21:61] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1333 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1334 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1336 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1338 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1339 = or(_T_1338, reset) @[RISCVPlatform.scala 21:61] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1341 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1343 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1344 = or(_T_1343, reset) @[RISCVPlatform.scala 21:61] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1346 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1348 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:61] + when _T_1348 : @[RISCVPlatform.scala 21:61] + node _T_1351 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1353 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1354 = cvt(_T_1353) @[Parameters.scala 117:49] + node _T_1356 = and(_T_1354, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1357 = asSInt(_T_1356) @[Parameters.scala 117:52] + node _T_1359 = eq(_T_1357, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1360 = and(_T_1351, _T_1359) @[Parameters.scala 132:56] + node _T_1362 = or(UInt<1>("h00"), _T_1360) @[Parameters.scala 134:30] + node _T_1363 = or(_T_1362, reset) @[RISCVPlatform.scala 21:61] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1365 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1366 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1368 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1370 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1371 = or(_T_1370, reset) @[RISCVPlatform.scala 21:61] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1373 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1374 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1376 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1378 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1379 = or(_T_1378, reset) @[RISCVPlatform.scala 21:61] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1381 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1383 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1384 = or(_T_1383, reset) @[RISCVPlatform.scala 21:61] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1386 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 21:61] + when _T_1388 : @[RISCVPlatform.scala 21:61] + node _T_1391 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1393 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + node _T_1403 = or(_T_1402, reset) @[RISCVPlatform.scala 21:61] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1405 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1406 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1408 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1410 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1411 = or(_T_1410, reset) @[RISCVPlatform.scala 21:61] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1413 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1414 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1416 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1418 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1419 = or(_T_1418, reset) @[RISCVPlatform.scala 21:61] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1421 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1424 = or(_T_1423, reset) @[RISCVPlatform.scala 21:61] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1426 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1428 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1428 : @[RISCVPlatform.scala 21:61] + node _T_1429 = or(_T_1291[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1431 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1432 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1434 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1435 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1437 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1439 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1440 = or(_T_1439, reset) @[RISCVPlatform.scala 21:61] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1442 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1444 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + when _T_1444 : @[RISCVPlatform.scala 21:61] + node _T_1445 = or(_T_1291[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1447 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1448 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1450 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1451 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1453 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1455 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1456 = or(_T_1455, reset) @[RISCVPlatform.scala 21:61] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1458 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1460 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:61] + when _T_1460 : @[RISCVPlatform.scala 21:61] + node _T_1461 = or(_T_1291[0], reset) @[RISCVPlatform.scala 21:61] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1463 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1464 = or(_T_1272, reset) @[RISCVPlatform.scala 21:61] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1466 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1467 = or(_T_1280, reset) @[RISCVPlatform.scala 21:61] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1469 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1471 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1472 = or(_T_1471, reset) @[RISCVPlatform.scala 21:61] + node _T_1474 = eq(_T_1472, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1474 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1476 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1477 = or(_T_1476, reset) @[RISCVPlatform.scala 21:61] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1479 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + when io.in[0].d.valid : @[RISCVPlatform.scala 21:61] + node _T_1481 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1482 = or(_T_1481, reset) @[RISCVPlatform.scala 21:61] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1484 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1486 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1487 = not(_T_1486) @[Parameters.scala 37:9] + node _T_1489 = or(_T_1487, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1490 = not(_T_1489) @[Parameters.scala 37:7] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1494 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1496 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1499 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1499 is invalid @[Parameters.scala 228:27] + _T_1499[0] <= _T_1492 @[Parameters.scala 228:27] + _T_1499[1] <= _T_1494 @[Parameters.scala 228:27] + _T_1499[2] <= _T_1496 @[Parameters.scala 228:27] + node _T_1505 = or(_T_1499[0], _T_1499[1]) @[Parameters.scala 229:46] + node _T_1506 = or(_T_1505, _T_1499[2]) @[Parameters.scala 229:46] + node _T_1508 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1509 = dshl(_T_1508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1510 = bits(_T_1509, 5, 0) @[package.scala 19:76] + node _T_1511 = not(_T_1510) @[package.scala 19:40] + node _T_1512 = and(io.in[0].d.bits.addr_lo, _T_1511) @[Edges.scala 17:16] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1516 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + node _T_1518 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:61] + when _T_1518 : @[RISCVPlatform.scala 21:61] + node _T_1519 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1521 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1522 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1524 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1525 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1527 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1529 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1530 = or(_T_1529, reset) @[RISCVPlatform.scala 21:61] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1532 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1534 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1535 = or(_T_1534, reset) @[RISCVPlatform.scala 21:61] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1537 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1539 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1540 = or(_T_1539, reset) @[RISCVPlatform.scala 21:61] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1542 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1544 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:61] + when _T_1544 : @[RISCVPlatform.scala 21:61] + node _T_1545 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1547 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1548 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1550 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1551 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1553 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1555 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1556 = or(_T_1555, reset) @[RISCVPlatform.scala 21:61] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1558 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1560 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1561 = or(_T_1560, reset) @[RISCVPlatform.scala 21:61] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1563 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1565 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:61] + when _T_1565 : @[RISCVPlatform.scala 21:61] + node _T_1566 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1568 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1569 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1571 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1572 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1574 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1576 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:61] + node _T_1577 = or(_T_1576, reset) @[RISCVPlatform.scala 21:61] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1579 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1581 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1582 = or(_T_1581, reset) @[RISCVPlatform.scala 21:61] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1584 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1586 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1586 : @[RISCVPlatform.scala 21:61] + node _T_1587 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1589 = eq(_T_1587, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1589 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1590 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1592 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1593 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1595 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1597 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1598 = or(_T_1597, reset) @[RISCVPlatform.scala 21:61] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1600 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1602 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + when _T_1602 : @[RISCVPlatform.scala 21:61] + node _T_1603 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1605 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1606 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1608 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1609 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1611 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1613 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1614 = or(_T_1613, reset) @[RISCVPlatform.scala 21:61] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1616 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1618 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:61] + when _T_1618 : @[RISCVPlatform.scala 21:61] + node _T_1619 = or(_T_1506, reset) @[RISCVPlatform.scala 21:61] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1621 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1622 = or(_T_1514, reset) @[RISCVPlatform.scala 21:61] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1624 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1625 = or(_T_1516, reset) @[RISCVPlatform.scala 21:61] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1627 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1629 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 21:61] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1632 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1634 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1635 = or(_T_1634, reset) @[RISCVPlatform.scala 21:61] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1637 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + when io.in[0].e.valid : @[RISCVPlatform.scala 21:61] + node _T_1639 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 21:61] + node _T_1640 = or(_T_1639, reset) @[RISCVPlatform.scala 21:61] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1642 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1643 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1646 = dshl(_T_1645, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1647 = bits(_T_1646, 5, 0) @[package.scala 19:76] + node _T_1648 = not(_T_1647) @[package.scala 19:40] + node _T_1649 = shr(_T_1648, 3) @[Edges.scala 198:59] + node _T_1650 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1654 = mux(_T_1652, _T_1649, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1656 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1658 = sub(_T_1656, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1659 = asUInt(_T_1658) @[Edges.scala 208:28] + node _T_1660 = tail(_T_1659, 1) @[Edges.scala 208:28] + node _T_1662 = eq(_T_1656, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1664 = eq(_T_1656, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1666 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1667 = or(_T_1664, _T_1666) @[Edges.scala 210:37] + node _T_1668 = and(_T_1667, _T_1643) @[Edges.scala 211:22] + node _T_1669 = not(_T_1660) @[Edges.scala 212:27] + node _T_1670 = and(_T_1654, _T_1669) @[Edges.scala 212:25] + when _T_1643 : @[Edges.scala 213:17] + node _T_1671 = mux(_T_1662, _T_1654, _T_1660) @[Edges.scala 214:21] + _T_1656 <= _T_1671 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1673 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1675 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1677 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1679 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1681 : UInt, clock @[RISCVPlatform.scala 21:61] + node _T_1683 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1684 = and(io.in[0].a.valid, _T_1683) @[RISCVPlatform.scala 21:61] + when _T_1684 : @[RISCVPlatform.scala 21:61] + node _T_1685 = eq(io.in[0].a.bits.opcode, _T_1673) @[RISCVPlatform.scala 21:61] + node _T_1686 = or(_T_1685, reset) @[RISCVPlatform.scala 21:61] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1688 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1689 = eq(io.in[0].a.bits.param, _T_1675) @[RISCVPlatform.scala 21:61] + node _T_1690 = or(_T_1689, reset) @[RISCVPlatform.scala 21:61] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1692 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1693 = eq(io.in[0].a.bits.size, _T_1677) @[RISCVPlatform.scala 21:61] + node _T_1694 = or(_T_1693, reset) @[RISCVPlatform.scala 21:61] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1696 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1697 = eq(io.in[0].a.bits.source, _T_1679) @[RISCVPlatform.scala 21:61] + node _T_1698 = or(_T_1697, reset) @[RISCVPlatform.scala 21:61] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1700 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1701 = eq(io.in[0].a.bits.address, _T_1681) @[RISCVPlatform.scala 21:61] + node _T_1702 = or(_T_1701, reset) @[RISCVPlatform.scala 21:61] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1704 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1705 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1706 = and(_T_1705, _T_1662) @[RISCVPlatform.scala 21:61] + when _T_1706 : @[RISCVPlatform.scala 21:61] + _T_1673 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 21:61] + _T_1675 <= io.in[0].a.bits.param @[RISCVPlatform.scala 21:61] + _T_1677 <= io.in[0].a.bits.size @[RISCVPlatform.scala 21:61] + _T_1679 <= io.in[0].a.bits.source @[RISCVPlatform.scala 21:61] + _T_1681 <= io.in[0].a.bits.address @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1707 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 5, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1719 = mux(UInt<1>("h00"), _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1721 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1723 = sub(_T_1721, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1724 = asUInt(_T_1723) @[Edges.scala 208:28] + node _T_1725 = tail(_T_1724, 1) @[Edges.scala 208:28] + node _T_1727 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1729 = eq(_T_1721, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1731 = eq(_T_1719, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1732 = or(_T_1729, _T_1731) @[Edges.scala 210:37] + node _T_1733 = and(_T_1732, _T_1707) @[Edges.scala 211:22] + node _T_1734 = not(_T_1725) @[Edges.scala 212:27] + node _T_1735 = and(_T_1719, _T_1734) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1736 = mux(_T_1727, _T_1719, _T_1725) @[Edges.scala 214:21] + _T_1721 <= _T_1736 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1738 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1740 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1742 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1744 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1746 : UInt, clock @[RISCVPlatform.scala 21:61] + node _T_1748 = eq(_T_1727, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1749 = and(io.in[0].b.valid, _T_1748) @[RISCVPlatform.scala 21:61] + when _T_1749 : @[RISCVPlatform.scala 21:61] + node _T_1750 = eq(io.in[0].b.bits.opcode, _T_1738) @[RISCVPlatform.scala 21:61] + node _T_1751 = or(_T_1750, reset) @[RISCVPlatform.scala 21:61] + node _T_1753 = eq(_T_1751, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1753 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1754 = eq(io.in[0].b.bits.param, _T_1740) @[RISCVPlatform.scala 21:61] + node _T_1755 = or(_T_1754, reset) @[RISCVPlatform.scala 21:61] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1757 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1758 = eq(io.in[0].b.bits.size, _T_1742) @[RISCVPlatform.scala 21:61] + node _T_1759 = or(_T_1758, reset) @[RISCVPlatform.scala 21:61] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1761 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1762 = eq(io.in[0].b.bits.source, _T_1744) @[RISCVPlatform.scala 21:61] + node _T_1763 = or(_T_1762, reset) @[RISCVPlatform.scala 21:61] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1765 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1766 = eq(io.in[0].b.bits.address, _T_1746) @[RISCVPlatform.scala 21:61] + node _T_1767 = or(_T_1766, reset) @[RISCVPlatform.scala 21:61] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1769 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1770 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1771 = and(_T_1770, _T_1727) @[RISCVPlatform.scala 21:61] + when _T_1771 : @[RISCVPlatform.scala 21:61] + _T_1738 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 21:61] + _T_1740 <= io.in[0].b.bits.param @[RISCVPlatform.scala 21:61] + _T_1742 <= io.in[0].b.bits.size @[RISCVPlatform.scala 21:61] + _T_1744 <= io.in[0].b.bits.source @[RISCVPlatform.scala 21:61] + _T_1746 <= io.in[0].b.bits.address @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1774 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1775 = dshl(_T_1774, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1776 = bits(_T_1775, 5, 0) @[package.scala 19:76] + node _T_1777 = not(_T_1776) @[package.scala 19:40] + node _T_1778 = shr(_T_1777, 3) @[Edges.scala 198:59] + node _T_1779 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1781 = mux(_T_1779, _T_1778, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1783 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1785 = sub(_T_1783, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1786 = asUInt(_T_1785) @[Edges.scala 208:28] + node _T_1787 = tail(_T_1786, 1) @[Edges.scala 208:28] + node _T_1789 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1791 = eq(_T_1783, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1793 = eq(_T_1781, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1794 = or(_T_1791, _T_1793) @[Edges.scala 210:37] + node _T_1795 = and(_T_1794, _T_1772) @[Edges.scala 211:22] + node _T_1796 = not(_T_1787) @[Edges.scala 212:27] + node _T_1797 = and(_T_1781, _T_1796) @[Edges.scala 212:25] + when _T_1772 : @[Edges.scala 213:17] + node _T_1798 = mux(_T_1789, _T_1781, _T_1787) @[Edges.scala 214:21] + _T_1783 <= _T_1798 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1800 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1802 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1804 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1806 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1808 : UInt, clock @[RISCVPlatform.scala 21:61] + node _T_1810 = eq(_T_1789, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1811 = and(io.in[0].c.valid, _T_1810) @[RISCVPlatform.scala 21:61] + when _T_1811 : @[RISCVPlatform.scala 21:61] + node _T_1812 = eq(io.in[0].c.bits.opcode, _T_1800) @[RISCVPlatform.scala 21:61] + node _T_1813 = or(_T_1812, reset) @[RISCVPlatform.scala 21:61] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1815 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1816 = eq(io.in[0].c.bits.param, _T_1802) @[RISCVPlatform.scala 21:61] + node _T_1817 = or(_T_1816, reset) @[RISCVPlatform.scala 21:61] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1819 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1820 = eq(io.in[0].c.bits.size, _T_1804) @[RISCVPlatform.scala 21:61] + node _T_1821 = or(_T_1820, reset) @[RISCVPlatform.scala 21:61] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1823 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1824 = eq(io.in[0].c.bits.source, _T_1806) @[RISCVPlatform.scala 21:61] + node _T_1825 = or(_T_1824, reset) @[RISCVPlatform.scala 21:61] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1827 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1828 = eq(io.in[0].c.bits.address, _T_1808) @[RISCVPlatform.scala 21:61] + node _T_1829 = or(_T_1828, reset) @[RISCVPlatform.scala 21:61] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1831 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1832 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1833 = and(_T_1832, _T_1789) @[RISCVPlatform.scala 21:61] + when _T_1833 : @[RISCVPlatform.scala 21:61] + _T_1800 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 21:61] + _T_1802 <= io.in[0].c.bits.param @[RISCVPlatform.scala 21:61] + _T_1804 <= io.in[0].c.bits.size @[RISCVPlatform.scala 21:61] + _T_1806 <= io.in[0].c.bits.source @[RISCVPlatform.scala 21:61] + _T_1808 <= io.in[0].c.bits.address @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1834 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 3) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1843 = mux(_T_1841, _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1845 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1847 = sub(_T_1845, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1848 = asUInt(_T_1847) @[Edges.scala 208:28] + node _T_1849 = tail(_T_1848, 1) @[Edges.scala 208:28] + node _T_1851 = eq(_T_1845, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1853 = eq(_T_1845, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1855 = eq(_T_1843, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1856 = or(_T_1853, _T_1855) @[Edges.scala 210:37] + node _T_1857 = and(_T_1856, _T_1834) @[Edges.scala 211:22] + node _T_1858 = not(_T_1849) @[Edges.scala 212:27] + node _T_1859 = and(_T_1843, _T_1858) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1860 = mux(_T_1851, _T_1843, _T_1849) @[Edges.scala 214:21] + _T_1845 <= _T_1860 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1862 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1864 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1866 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1868 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1870 : UInt, clock @[RISCVPlatform.scala 21:61] + reg _T_1872 : UInt, clock @[RISCVPlatform.scala 21:61] + node _T_1874 = eq(_T_1851, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1875 = and(io.in[0].d.valid, _T_1874) @[RISCVPlatform.scala 21:61] + when _T_1875 : @[RISCVPlatform.scala 21:61] + node _T_1876 = eq(io.in[0].d.bits.opcode, _T_1862) @[RISCVPlatform.scala 21:61] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 21:61] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1879 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1880 = eq(io.in[0].d.bits.param, _T_1864) @[RISCVPlatform.scala 21:61] + node _T_1881 = or(_T_1880, reset) @[RISCVPlatform.scala 21:61] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1883 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1884 = eq(io.in[0].d.bits.size, _T_1866) @[RISCVPlatform.scala 21:61] + node _T_1885 = or(_T_1884, reset) @[RISCVPlatform.scala 21:61] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1887 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1888 = eq(io.in[0].d.bits.source, _T_1868) @[RISCVPlatform.scala 21:61] + node _T_1889 = or(_T_1888, reset) @[RISCVPlatform.scala 21:61] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1891 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1892 = eq(io.in[0].d.bits.sink, _T_1870) @[RISCVPlatform.scala 21:61] + node _T_1893 = or(_T_1892, reset) @[RISCVPlatform.scala 21:61] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1895 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1896 = eq(io.in[0].d.bits.addr_lo, _T_1872) @[RISCVPlatform.scala 21:61] + node _T_1897 = or(_T_1896, reset) @[RISCVPlatform.scala 21:61] + node _T_1899 = eq(_T_1897, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1899 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1900 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = and(_T_1900, _T_1851) @[RISCVPlatform.scala 21:61] + when _T_1901 : @[RISCVPlatform.scala 21:61] + _T_1862 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 21:61] + _T_1864 <= io.in[0].d.bits.param @[RISCVPlatform.scala 21:61] + _T_1866 <= io.in[0].d.bits.size @[RISCVPlatform.scala 21:61] + _T_1868 <= io.in[0].d.bits.source @[RISCVPlatform.scala 21:61] + _T_1870 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 21:61] + _T_1872 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + reg _T_1903 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1904 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1906 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1907 = dshl(_T_1906, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1908 = bits(_T_1907, 5, 0) @[package.scala 19:76] + node _T_1909 = not(_T_1908) @[package.scala 19:40] + node _T_1910 = shr(_T_1909, 3) @[Edges.scala 198:59] + node _T_1911 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1915 = mux(_T_1913, _T_1910, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1917 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1919 = sub(_T_1917, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1920 = asUInt(_T_1919) @[Edges.scala 208:28] + node _T_1921 = tail(_T_1920, 1) @[Edges.scala 208:28] + node _T_1923 = eq(_T_1917, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1925 = eq(_T_1917, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1927 = eq(_T_1915, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1928 = or(_T_1925, _T_1927) @[Edges.scala 210:37] + node _T_1929 = and(_T_1928, _T_1904) @[Edges.scala 211:22] + node _T_1930 = not(_T_1921) @[Edges.scala 212:27] + node _T_1931 = and(_T_1915, _T_1930) @[Edges.scala 212:25] + when _T_1904 : @[Edges.scala 213:17] + node _T_1932 = mux(_T_1923, _T_1915, _T_1921) @[Edges.scala 214:21] + _T_1917 <= _T_1932 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1933 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1935 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1936 = dshl(_T_1935, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1937 = bits(_T_1936, 5, 0) @[package.scala 19:76] + node _T_1938 = not(_T_1937) @[package.scala 19:40] + node _T_1939 = shr(_T_1938, 3) @[Edges.scala 198:59] + node _T_1940 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1942 = mux(_T_1940, _T_1939, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1944 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1946 = sub(_T_1944, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1947 = asUInt(_T_1946) @[Edges.scala 208:28] + node _T_1948 = tail(_T_1947, 1) @[Edges.scala 208:28] + node _T_1950 = eq(_T_1944, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1952 = eq(_T_1944, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1954 = eq(_T_1942, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1955 = or(_T_1952, _T_1954) @[Edges.scala 210:37] + node _T_1956 = and(_T_1955, _T_1933) @[Edges.scala 211:22] + node _T_1957 = not(_T_1948) @[Edges.scala 212:27] + node _T_1958 = and(_T_1942, _T_1957) @[Edges.scala 212:25] + when _T_1933 : @[Edges.scala 213:17] + node _T_1959 = mux(_T_1950, _T_1942, _T_1948) @[Edges.scala 214:21] + _T_1944 <= _T_1959 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1961 : UInt<6> + _T_1961 is invalid + _T_1961 <= UInt<6>("h00") + node _T_1962 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1962 : @[RISCVPlatform.scala 21:61] + when _T_1928 : @[RISCVPlatform.scala 21:61] + node _T_1964 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1961 <= _T_1964 @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1965 = dshr(_T_1903, io.in[0].a.bits.source) @[RISCVPlatform.scala 21:61] + node _T_1966 = bits(_T_1965, 0, 0) @[RISCVPlatform.scala 21:61] + node _T_1968 = eq(_T_1966, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + node _T_1969 = or(_T_1968, reset) @[RISCVPlatform.scala 21:61] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1971 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + wire _T_1973 : UInt<6> + _T_1973 is invalid + _T_1973 <= UInt<6>("h00") + node _T_1974 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1976 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:61] + node _T_1977 = and(_T_1974, _T_1976) @[RISCVPlatform.scala 21:61] + when _T_1977 : @[RISCVPlatform.scala 21:61] + when _T_1955 : @[RISCVPlatform.scala 21:61] + node _T_1979 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1973 <= _T_1979 @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1980 = or(_T_1961, _T_1903) @[RISCVPlatform.scala 21:61] + node _T_1981 = dshr(_T_1980, io.in[0].d.bits.source) @[RISCVPlatform.scala 21:61] + node _T_1982 = bits(_T_1981, 0, 0) @[RISCVPlatform.scala 21:61] + node _T_1983 = or(_T_1982, reset) @[RISCVPlatform.scala 21:61] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[RISCVPlatform.scala 21:61] + when _T_1985 : @[RISCVPlatform.scala 21:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:21:61)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 21:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + skip @[RISCVPlatform.scala 21:61] + node _T_1986 = or(_T_1903, _T_1961) @[RISCVPlatform.scala 21:61] + node _T_1987 = not(_T_1973) @[RISCVPlatform.scala 21:61] + node _T_1988 = and(_T_1986, _T_1987) @[RISCVPlatform.scala 21:61] + _T_1903 <= _T_1988 @[RISCVPlatform.scala 21:61] + + module TLMonitor_26 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 21:14] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 21:14] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_608 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = xor(UInt<6>("h028"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_619 = not(_T_618) @[Parameters.scala 37:9] + node _T_621 = or(_T_619, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_622 = not(_T_621) @[Parameters.scala 37:7] + node _T_624 = eq(_T_622, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_626 = xor(UInt<6>("h020"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_627 = not(_T_626) @[Parameters.scala 37:9] + node _T_629 = or(_T_627, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_630 = not(_T_629) @[Parameters.scala 37:7] + node _T_632 = eq(_T_630, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_635 : UInt<1>[3] @[Parameters.scala 228:27] + _T_635 is invalid @[Parameters.scala 228:27] + _T_635[0] <= _T_616 @[Parameters.scala 228:27] + _T_635[1] <= _T_624 @[Parameters.scala 228:27] + _T_635[2] <= _T_632 @[Parameters.scala 228:27] + node _T_641 = or(_T_635[0], _T_635[1]) @[Parameters.scala 229:46] + node _T_642 = or(_T_641, _T_635[2]) @[Parameters.scala 229:46] + node _T_644 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_645 = dshl(_T_644, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_646 = bits(_T_645, 5, 0) @[package.scala 19:76] + node _T_647 = not(_T_646) @[package.scala 19:40] + node _T_648 = and(io.in[0].a.bits.address, _T_647) @[Edges.scala 17:16] + node _T_650 = eq(_T_648, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_652 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_653 = dshl(UInt<1>("h01"), _T_652) @[OneHot.scala 49:12] + node _T_654 = bits(_T_653, 2, 0) @[OneHot.scala 49:37] + node _T_656 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_658 = bits(_T_654, 2, 2) @[package.scala 44:26] + node _T_659 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_661 = eq(_T_659, UInt<1>("h00")) @[package.scala 46:20] + node _T_662 = and(UInt<1>("h01"), _T_661) @[package.scala 49:27] + node _T_663 = and(_T_658, _T_662) @[package.scala 50:38] + node _T_664 = or(_T_656, _T_663) @[package.scala 50:29] + node _T_665 = and(UInt<1>("h01"), _T_659) @[package.scala 49:27] + node _T_666 = and(_T_658, _T_665) @[package.scala 50:38] + node _T_667 = or(_T_656, _T_666) @[package.scala 50:29] + node _T_668 = bits(_T_654, 1, 1) @[package.scala 44:26] + node _T_669 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_671 = eq(_T_669, UInt<1>("h00")) @[package.scala 46:20] + node _T_672 = and(_T_662, _T_671) @[package.scala 49:27] + node _T_673 = and(_T_668, _T_672) @[package.scala 50:38] + node _T_674 = or(_T_664, _T_673) @[package.scala 50:29] + node _T_675 = and(_T_662, _T_669) @[package.scala 49:27] + node _T_676 = and(_T_668, _T_675) @[package.scala 50:38] + node _T_677 = or(_T_664, _T_676) @[package.scala 50:29] + node _T_678 = and(_T_665, _T_671) @[package.scala 49:27] + node _T_679 = and(_T_668, _T_678) @[package.scala 50:38] + node _T_680 = or(_T_667, _T_679) @[package.scala 50:29] + node _T_681 = and(_T_665, _T_669) @[package.scala 49:27] + node _T_682 = and(_T_668, _T_681) @[package.scala 50:38] + node _T_683 = or(_T_667, _T_682) @[package.scala 50:29] + node _T_684 = bits(_T_654, 0, 0) @[package.scala 44:26] + node _T_685 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_687 = eq(_T_685, UInt<1>("h00")) @[package.scala 46:20] + node _T_688 = and(_T_672, _T_687) @[package.scala 49:27] + node _T_689 = and(_T_684, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_674, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_672, _T_685) @[package.scala 49:27] + node _T_692 = and(_T_684, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_674, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_675, _T_687) @[package.scala 49:27] + node _T_695 = and(_T_684, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_677, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_675, _T_685) @[package.scala 49:27] + node _T_698 = and(_T_684, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_677, _T_698) @[package.scala 50:29] + node _T_700 = and(_T_678, _T_687) @[package.scala 49:27] + node _T_701 = and(_T_684, _T_700) @[package.scala 50:38] + node _T_702 = or(_T_680, _T_701) @[package.scala 50:29] + node _T_703 = and(_T_678, _T_685) @[package.scala 49:27] + node _T_704 = and(_T_684, _T_703) @[package.scala 50:38] + node _T_705 = or(_T_680, _T_704) @[package.scala 50:29] + node _T_706 = and(_T_681, _T_687) @[package.scala 49:27] + node _T_707 = and(_T_684, _T_706) @[package.scala 50:38] + node _T_708 = or(_T_683, _T_707) @[package.scala 50:29] + node _T_709 = and(_T_681, _T_685) @[package.scala 49:27] + node _T_710 = and(_T_684, _T_709) @[package.scala 50:38] + node _T_711 = or(_T_683, _T_710) @[package.scala 50:29] + node _T_712 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_713 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_714 = cat(_T_713, _T_712) @[Cat.scala 30:58] + node _T_715 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_716 = cat(_T_711, _T_708) @[Cat.scala 30:58] + node _T_717 = cat(_T_716, _T_715) @[Cat.scala 30:58] + node _T_718 = cat(_T_717, _T_714) @[Cat.scala 30:58] + node _T_720 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:14] + when _T_720 : @[RISCVPlatform.scala 21:14] + node _T_723 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_725 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_726 = cvt(_T_725) @[Parameters.scala 117:49] + node _T_728 = and(_T_726, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_729 = asSInt(_T_728) @[Parameters.scala 117:52] + node _T_731 = eq(_T_729, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_732 = and(_T_723, _T_731) @[Parameters.scala 132:56] + node _T_734 = or(UInt<1>("h00"), _T_732) @[Parameters.scala 134:30] + node _T_735 = or(_T_734, reset) @[RISCVPlatform.scala 21:14] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_737 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_738 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_740 = eq(_T_738, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_740 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_742 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_743 = or(_T_742, reset) @[RISCVPlatform.scala 21:14] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_745 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_746 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_748 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_750 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_751 = or(_T_750, reset) @[RISCVPlatform.scala 21:14] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_753 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_754 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 21:14] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_757 = or(_T_756, reset) @[RISCVPlatform.scala 21:14] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_759 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_761 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:14] + when _T_761 : @[RISCVPlatform.scala 21:14] + node _T_764 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_766 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_767 = and(_T_764, _T_766) @[Parameters.scala 63:37] + node _T_768 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 132:31] + node _T_770 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_771 = cvt(_T_770) @[Parameters.scala 117:49] + node _T_773 = and(_T_771, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_774 = asSInt(_T_773) @[Parameters.scala 117:52] + node _T_776 = eq(_T_774, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_777 = and(_T_768, _T_776) @[Parameters.scala 132:56] + node _T_779 = or(UInt<1>("h00"), _T_777) @[Parameters.scala 134:30] + node _T_780 = or(_T_779, reset) @[RISCVPlatform.scala 21:14] + node _T_782 = eq(_T_780, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_782 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_783 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_785 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_786 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_788 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_790 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_791 = or(_T_790, reset) @[RISCVPlatform.scala 21:14] + node _T_793 = eq(_T_791, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_793 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_794 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 21:14] + node _T_795 = or(_T_794, reset) @[RISCVPlatform.scala 21:14] + node _T_797 = eq(_T_795, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_797 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_799 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_799 : @[RISCVPlatform.scala 21:14] + node _T_802 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_804 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_805 = and(_T_802, _T_804) @[Parameters.scala 63:37] + node _T_806 = or(UInt<1>("h00"), _T_805) @[Parameters.scala 132:31] + node _T_808 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_809 = cvt(_T_808) @[Parameters.scala 117:49] + node _T_811 = and(_T_809, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_812 = asSInt(_T_811) @[Parameters.scala 117:52] + node _T_814 = eq(_T_812, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_815 = and(_T_806, _T_814) @[Parameters.scala 132:56] + node _T_817 = or(UInt<1>("h00"), _T_815) @[Parameters.scala 134:30] + node _T_818 = or(_T_817, reset) @[RISCVPlatform.scala 21:14] + node _T_820 = eq(_T_818, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_820 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_821 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_823 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_824 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_826 = eq(_T_824, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_826 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_828 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_829 = or(_T_828, reset) @[RISCVPlatform.scala 21:14] + node _T_831 = eq(_T_829, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_831 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_832 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 21:14] + node _T_833 = or(_T_832, reset) @[RISCVPlatform.scala 21:14] + node _T_835 = eq(_T_833, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_835 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_837 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + when _T_837 : @[RISCVPlatform.scala 21:14] + node _T_840 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_842 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_843 = and(_T_840, _T_842) @[Parameters.scala 63:37] + node _T_844 = or(UInt<1>("h00"), _T_843) @[Parameters.scala 132:31] + node _T_846 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_847 = cvt(_T_846) @[Parameters.scala 117:49] + node _T_849 = and(_T_847, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_850 = asSInt(_T_849) @[Parameters.scala 117:52] + node _T_852 = eq(_T_850, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_853 = and(_T_844, _T_852) @[Parameters.scala 132:56] + node _T_855 = or(UInt<1>("h00"), _T_853) @[Parameters.scala 134:30] + node _T_856 = or(_T_855, reset) @[RISCVPlatform.scala 21:14] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_858 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_859 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_861 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_862 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_864 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_866 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_867 = or(_T_866, reset) @[RISCVPlatform.scala 21:14] + node _T_869 = eq(_T_867, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_869 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_870 = not(_T_718) @[RISCVPlatform.scala 21:14] + node _T_871 = and(io.in[0].a.bits.mask, _T_870) @[RISCVPlatform.scala 21:14] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_874 = or(_T_873, reset) @[RISCVPlatform.scala 21:14] + node _T_876 = eq(_T_874, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_876 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_878 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:14] + when _T_878 : @[RISCVPlatform.scala 21:14] + node _T_881 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_883 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_884 = cvt(_T_883) @[Parameters.scala 117:49] + node _T_886 = and(_T_884, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_887 = asSInt(_T_886) @[Parameters.scala 117:52] + node _T_889 = eq(_T_887, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_890 = and(_T_881, _T_889) @[Parameters.scala 132:56] + node _T_892 = or(UInt<1>("h00"), _T_890) @[Parameters.scala 134:30] + node _T_893 = or(_T_892, reset) @[RISCVPlatform.scala 21:14] + node _T_895 = eq(_T_893, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_895 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_896 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_898 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_899 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_901 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_903 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_904 = or(_T_903, reset) @[RISCVPlatform.scala 21:14] + node _T_906 = eq(_T_904, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_906 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_907 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 21:14] + node _T_908 = or(_T_907, reset) @[RISCVPlatform.scala 21:14] + node _T_910 = eq(_T_908, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_910 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_912 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + when _T_912 : @[RISCVPlatform.scala 21:14] + node _T_915 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_917 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_918 = cvt(_T_917) @[Parameters.scala 117:49] + node _T_920 = and(_T_918, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_921 = asSInt(_T_920) @[Parameters.scala 117:52] + node _T_923 = eq(_T_921, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_924 = and(_T_915, _T_923) @[Parameters.scala 132:56] + node _T_926 = or(UInt<1>("h00"), _T_924) @[Parameters.scala 134:30] + node _T_927 = or(_T_926, reset) @[RISCVPlatform.scala 21:14] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_929 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_930 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_932 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_933 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_935 = eq(_T_933, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_935 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_937 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_938 = or(_T_937, reset) @[RISCVPlatform.scala 21:14] + node _T_940 = eq(_T_938, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_940 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_941 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 21:14] + node _T_942 = or(_T_941, reset) @[RISCVPlatform.scala 21:14] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_944 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_946 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:14] + when _T_946 : @[RISCVPlatform.scala 21:14] + node _T_949 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_951 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_958 = and(_T_949, _T_957) @[Parameters.scala 132:56] + node _T_960 = or(UInt<1>("h00"), _T_958) @[Parameters.scala 134:30] + node _T_961 = or(_T_960, reset) @[RISCVPlatform.scala 21:14] + node _T_963 = eq(_T_961, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_963 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_964 = or(_T_642, reset) @[RISCVPlatform.scala 21:14] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_966 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_967 = or(_T_650, reset) @[RISCVPlatform.scala 21:14] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_969 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_970 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 21:14] + node _T_971 = or(_T_970, reset) @[RISCVPlatform.scala 21:14] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_973 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + when io.in[0].b.valid : @[RISCVPlatform.scala 21:14] + node _T_975 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_976 = or(_T_975, reset) @[RISCVPlatform.scala 21:14] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_978 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_980 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_981 = cvt(_T_980) @[Parameters.scala 117:49] + node _T_983 = and(_T_981, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_984 = asSInt(_T_983) @[Parameters.scala 117:52] + node _T_986 = eq(_T_984, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_989 : UInt<1>[1] @[Parameters.scala 110:36] + _T_989 is invalid @[Parameters.scala 110:36] + _T_989[0] <= _T_986 @[Parameters.scala 110:36] + node _T_994 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_995 = dshl(_T_994, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_996 = bits(_T_995, 5, 0) @[package.scala 19:76] + node _T_997 = not(_T_996) @[package.scala 19:40] + node _T_998 = and(io.in[0].b.bits.address, _T_997) @[Edges.scala 17:16] + node _T_1000 = eq(_T_998, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1002 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1003 = dshl(UInt<1>("h01"), _T_1002) @[OneHot.scala 49:12] + node _T_1004 = bits(_T_1003, 2, 0) @[OneHot.scala 49:37] + node _T_1006 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1008 = bits(_T_1004, 2, 2) @[package.scala 44:26] + node _T_1009 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1011 = eq(_T_1009, UInt<1>("h00")) @[package.scala 46:20] + node _T_1012 = and(UInt<1>("h01"), _T_1011) @[package.scala 49:27] + node _T_1013 = and(_T_1008, _T_1012) @[package.scala 50:38] + node _T_1014 = or(_T_1006, _T_1013) @[package.scala 50:29] + node _T_1015 = and(UInt<1>("h01"), _T_1009) @[package.scala 49:27] + node _T_1016 = and(_T_1008, _T_1015) @[package.scala 50:38] + node _T_1017 = or(_T_1006, _T_1016) @[package.scala 50:29] + node _T_1018 = bits(_T_1004, 1, 1) @[package.scala 44:26] + node _T_1019 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1021 = eq(_T_1019, UInt<1>("h00")) @[package.scala 46:20] + node _T_1022 = and(_T_1012, _T_1021) @[package.scala 49:27] + node _T_1023 = and(_T_1018, _T_1022) @[package.scala 50:38] + node _T_1024 = or(_T_1014, _T_1023) @[package.scala 50:29] + node _T_1025 = and(_T_1012, _T_1019) @[package.scala 49:27] + node _T_1026 = and(_T_1018, _T_1025) @[package.scala 50:38] + node _T_1027 = or(_T_1014, _T_1026) @[package.scala 50:29] + node _T_1028 = and(_T_1015, _T_1021) @[package.scala 49:27] + node _T_1029 = and(_T_1018, _T_1028) @[package.scala 50:38] + node _T_1030 = or(_T_1017, _T_1029) @[package.scala 50:29] + node _T_1031 = and(_T_1015, _T_1019) @[package.scala 49:27] + node _T_1032 = and(_T_1018, _T_1031) @[package.scala 50:38] + node _T_1033 = or(_T_1017, _T_1032) @[package.scala 50:29] + node _T_1034 = bits(_T_1004, 0, 0) @[package.scala 44:26] + node _T_1035 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1037 = eq(_T_1035, UInt<1>("h00")) @[package.scala 46:20] + node _T_1038 = and(_T_1022, _T_1037) @[package.scala 49:27] + node _T_1039 = and(_T_1034, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1024, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1022, _T_1035) @[package.scala 49:27] + node _T_1042 = and(_T_1034, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1024, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1025, _T_1037) @[package.scala 49:27] + node _T_1045 = and(_T_1034, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1027, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1025, _T_1035) @[package.scala 49:27] + node _T_1048 = and(_T_1034, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1027, _T_1048) @[package.scala 50:29] + node _T_1050 = and(_T_1028, _T_1037) @[package.scala 49:27] + node _T_1051 = and(_T_1034, _T_1050) @[package.scala 50:38] + node _T_1052 = or(_T_1030, _T_1051) @[package.scala 50:29] + node _T_1053 = and(_T_1028, _T_1035) @[package.scala 49:27] + node _T_1054 = and(_T_1034, _T_1053) @[package.scala 50:38] + node _T_1055 = or(_T_1030, _T_1054) @[package.scala 50:29] + node _T_1056 = and(_T_1031, _T_1037) @[package.scala 49:27] + node _T_1057 = and(_T_1034, _T_1056) @[package.scala 50:38] + node _T_1058 = or(_T_1033, _T_1057) @[package.scala 50:29] + node _T_1059 = and(_T_1031, _T_1035) @[package.scala 49:27] + node _T_1060 = and(_T_1034, _T_1059) @[package.scala 50:38] + node _T_1061 = or(_T_1033, _T_1060) @[package.scala 50:29] + node _T_1062 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1063 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1064 = cat(_T_1063, _T_1062) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1066 = cat(_T_1061, _T_1058) @[Cat.scala 30:58] + node _T_1067 = cat(_T_1066, _T_1065) @[Cat.scala 30:58] + node _T_1068 = cat(_T_1067, _T_1064) @[Cat.scala 30:58] + node _T_1070 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:14] + when _T_1070 : @[RISCVPlatform.scala 21:14] + node _T_1072 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1073 = not(_T_1072) @[Parameters.scala 37:9] + node _T_1075 = or(_T_1073, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1076 = not(_T_1075) @[Parameters.scala 37:7] + node _T_1078 = eq(_T_1076, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1080 = xor(UInt<6>("h028"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1081 = not(_T_1080) @[Parameters.scala 37:9] + node _T_1083 = or(_T_1081, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1084 = not(_T_1083) @[Parameters.scala 37:7] + node _T_1086 = eq(_T_1084, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1088 = xor(UInt<6>("h020"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1089 = not(_T_1088) @[Parameters.scala 37:9] + node _T_1091 = or(_T_1089, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1092 = not(_T_1091) @[Parameters.scala 37:7] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1097 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1097 is invalid @[Parameters.scala 228:27] + _T_1097[0] <= _T_1078 @[Parameters.scala 228:27] + _T_1097[1] <= _T_1086 @[Parameters.scala 228:27] + _T_1097[2] <= _T_1094 @[Parameters.scala 228:27] + node _T_1105 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1107 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1108 = and(_T_1105, _T_1107) @[Parameters.scala 63:37] + node _T_1111 = mux(_T_1097[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1113 = mux(_T_1097[1], _T_1108, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1115 = mux(_T_1097[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1117 = or(_T_1111, _T_1113) @[Mux.scala 19:72] + node _T_1118 = or(_T_1117, _T_1115) @[Mux.scala 19:72] + wire _T_1120 : UInt<1> @[Mux.scala 19:72] + _T_1120 is invalid @[Mux.scala 19:72] + _T_1120 <= _T_1118 @[Mux.scala 19:72] + node _T_1121 = or(_T_1120, reset) @[RISCVPlatform.scala 21:14] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1123 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1124 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1126 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1128 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1129 = or(_T_1128, reset) @[RISCVPlatform.scala 21:14] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1131 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1132 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1134 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1136 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1137 = or(_T_1136, reset) @[RISCVPlatform.scala 21:14] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1139 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1140 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 21:14] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1143 = or(_T_1142, reset) @[RISCVPlatform.scala 21:14] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1145 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:14] + when _T_1147 : @[RISCVPlatform.scala 21:14] + node _T_1149 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1151 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1152 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1154 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1155 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1157 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1159 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1160 = or(_T_1159, reset) @[RISCVPlatform.scala 21:14] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1162 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1163 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 21:14] + node _T_1164 = or(_T_1163, reset) @[RISCVPlatform.scala 21:14] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1166 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1168 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1168 : @[RISCVPlatform.scala 21:14] + node _T_1170 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1172 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1173 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1175 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1176 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1178 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1180 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1181 = or(_T_1180, reset) @[RISCVPlatform.scala 21:14] + node _T_1183 = eq(_T_1181, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1183 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1184 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 21:14] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 21:14] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1187 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + when _T_1189 : @[RISCVPlatform.scala 21:14] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1193 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1194 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1196 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1197 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1199 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1201 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 21:14] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1204 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1205 = not(_T_1068) @[RISCVPlatform.scala 21:14] + node _T_1206 = and(io.in[0].b.bits.mask, _T_1205) @[RISCVPlatform.scala 21:14] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1209 = or(_T_1208, reset) @[RISCVPlatform.scala 21:14] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1211 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1213 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:14] + when _T_1213 : @[RISCVPlatform.scala 21:14] + node _T_1215 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1217 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1218 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1220 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1221 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1223 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1225 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1226 = or(_T_1225, reset) @[RISCVPlatform.scala 21:14] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1228 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1229 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 21:14] + node _T_1230 = or(_T_1229, reset) @[RISCVPlatform.scala 21:14] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1232 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1234 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + when _T_1234 : @[RISCVPlatform.scala 21:14] + node _T_1236 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1238 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1239 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1241 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1242 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1244 = eq(_T_1242, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1244 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1246 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1247 = or(_T_1246, reset) @[RISCVPlatform.scala 21:14] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1249 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1250 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 21:14] + node _T_1251 = or(_T_1250, reset) @[RISCVPlatform.scala 21:14] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1253 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1255 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:14] + when _T_1255 : @[RISCVPlatform.scala 21:14] + node _T_1257 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 21:14] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1259 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1260 = or(_T_989[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1262 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1263 = or(_T_1000, reset) @[RISCVPlatform.scala 21:14] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1265 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1266 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 21:14] + node _T_1267 = or(_T_1266, reset) @[RISCVPlatform.scala 21:14] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1269 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + when io.in[0].c.valid : @[RISCVPlatform.scala 21:14] + node _T_1271 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1272 = or(_T_1271, reset) @[RISCVPlatform.scala 21:14] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1274 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1276 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1277 = not(_T_1276) @[Parameters.scala 37:9] + node _T_1279 = or(_T_1277, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1280 = not(_T_1279) @[Parameters.scala 37:7] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1284 = xor(UInt<6>("h028"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1285 = not(_T_1284) @[Parameters.scala 37:9] + node _T_1287 = or(_T_1285, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1288 = not(_T_1287) @[Parameters.scala 37:7] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1292 = xor(UInt<6>("h020"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1293 = not(_T_1292) @[Parameters.scala 37:9] + node _T_1295 = or(_T_1293, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1296 = not(_T_1295) @[Parameters.scala 37:7] + node _T_1298 = eq(_T_1296, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1301 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1301 is invalid @[Parameters.scala 228:27] + _T_1301[0] <= _T_1282 @[Parameters.scala 228:27] + _T_1301[1] <= _T_1290 @[Parameters.scala 228:27] + _T_1301[2] <= _T_1298 @[Parameters.scala 228:27] + node _T_1307 = or(_T_1301[0], _T_1301[1]) @[Parameters.scala 229:46] + node _T_1308 = or(_T_1307, _T_1301[2]) @[Parameters.scala 229:46] + node _T_1310 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1311 = dshl(_T_1310, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1312 = bits(_T_1311, 5, 0) @[package.scala 19:76] + node _T_1313 = not(_T_1312) @[package.scala 19:40] + node _T_1314 = and(io.in[0].c.bits.address, _T_1313) @[Edges.scala 17:16] + node _T_1316 = eq(_T_1314, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1318 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1319 = cvt(_T_1318) @[Parameters.scala 117:49] + node _T_1321 = and(_T_1319, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1322 = asSInt(_T_1321) @[Parameters.scala 117:52] + node _T_1324 = eq(_T_1322, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1327 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1327 is invalid @[Parameters.scala 110:36] + _T_1327[0] <= _T_1324 @[Parameters.scala 110:36] + node _T_1332 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:14] + when _T_1332 : @[RISCVPlatform.scala 21:14] + node _T_1333 = or(_T_1327[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1335 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1336 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1338 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1340 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1341 = or(_T_1340, reset) @[RISCVPlatform.scala 21:14] + node _T_1343 = eq(_T_1341, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1343 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1344 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1346 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1348 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1349 = or(_T_1348, reset) @[RISCVPlatform.scala 21:14] + node _T_1351 = eq(_T_1349, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1351 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1353 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1354 = or(_T_1353, reset) @[RISCVPlatform.scala 21:14] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1356 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1358 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:14] + when _T_1358 : @[RISCVPlatform.scala 21:14] + node _T_1359 = or(_T_1327[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1361 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1362 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1364 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1366 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1367 = or(_T_1366, reset) @[RISCVPlatform.scala 21:14] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1369 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1370 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1372 = eq(_T_1370, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1372 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1374 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1375 = or(_T_1374, reset) @[RISCVPlatform.scala 21:14] + node _T_1377 = eq(_T_1375, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1377 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1379 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1380 = or(_T_1379, reset) @[RISCVPlatform.scala 21:14] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1382 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1384 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:14] + when _T_1384 : @[RISCVPlatform.scala 21:14] + node _T_1387 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1389 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1390 = cvt(_T_1389) @[Parameters.scala 117:49] + node _T_1392 = and(_T_1390, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1393 = asSInt(_T_1392) @[Parameters.scala 117:52] + node _T_1395 = eq(_T_1393, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1396 = and(_T_1387, _T_1395) @[Parameters.scala 132:56] + node _T_1398 = or(UInt<1>("h00"), _T_1396) @[Parameters.scala 134:30] + node _T_1399 = or(_T_1398, reset) @[RISCVPlatform.scala 21:14] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1401 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1402 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1404 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1406 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1407 = or(_T_1406, reset) @[RISCVPlatform.scala 21:14] + node _T_1409 = eq(_T_1407, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1409 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1410 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1412 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1414 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1415 = or(_T_1414, reset) @[RISCVPlatform.scala 21:14] + node _T_1417 = eq(_T_1415, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1417 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1419 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1420 = or(_T_1419, reset) @[RISCVPlatform.scala 21:14] + node _T_1422 = eq(_T_1420, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1422 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1424 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 21:14] + when _T_1424 : @[RISCVPlatform.scala 21:14] + node _T_1427 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1429 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1430 = cvt(_T_1429) @[Parameters.scala 117:49] + node _T_1432 = and(_T_1430, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1433 = asSInt(_T_1432) @[Parameters.scala 117:52] + node _T_1435 = eq(_T_1433, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1436 = and(_T_1427, _T_1435) @[Parameters.scala 132:56] + node _T_1438 = or(UInt<1>("h00"), _T_1436) @[Parameters.scala 134:30] + node _T_1439 = or(_T_1438, reset) @[RISCVPlatform.scala 21:14] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1441 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1442 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1444 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1446 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1447 = or(_T_1446, reset) @[RISCVPlatform.scala 21:14] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1449 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1450 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1452 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1454 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1455 = or(_T_1454, reset) @[RISCVPlatform.scala 21:14] + node _T_1457 = eq(_T_1455, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1457 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1459 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1460 = or(_T_1459, reset) @[RISCVPlatform.scala 21:14] + node _T_1462 = eq(_T_1460, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1462 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1464 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1464 : @[RISCVPlatform.scala 21:14] + node _T_1465 = or(_T_1327[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1467 = eq(_T_1465, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1467 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1468 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1470 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1471 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1473 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1475 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1476 = or(_T_1475, reset) @[RISCVPlatform.scala 21:14] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1478 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1480 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + when _T_1480 : @[RISCVPlatform.scala 21:14] + node _T_1481 = or(_T_1327[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1483 = eq(_T_1481, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1483 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1484 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1486 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1487 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1489 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1491 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1492 = or(_T_1491, reset) @[RISCVPlatform.scala 21:14] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1494 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:14] + when _T_1496 : @[RISCVPlatform.scala 21:14] + node _T_1497 = or(_T_1327[0], reset) @[RISCVPlatform.scala 21:14] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1499 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1500 = or(_T_1308, reset) @[RISCVPlatform.scala 21:14] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1502 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1503 = or(_T_1316, reset) @[RISCVPlatform.scala 21:14] + node _T_1505 = eq(_T_1503, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1505 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1507 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1508 = or(_T_1507, reset) @[RISCVPlatform.scala 21:14] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1510 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1512 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1513 = or(_T_1512, reset) @[RISCVPlatform.scala 21:14] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1515 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + when io.in[0].d.valid : @[RISCVPlatform.scala 21:14] + node _T_1517 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1518 = or(_T_1517, reset) @[RISCVPlatform.scala 21:14] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1520 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1522 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1523 = not(_T_1522) @[Parameters.scala 37:9] + node _T_1525 = or(_T_1523, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1526 = not(_T_1525) @[Parameters.scala 37:7] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1530 = xor(UInt<6>("h028"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1531 = not(_T_1530) @[Parameters.scala 37:9] + node _T_1533 = or(_T_1531, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1534 = not(_T_1533) @[Parameters.scala 37:7] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1538 = xor(UInt<6>("h020"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1539 = not(_T_1538) @[Parameters.scala 37:9] + node _T_1541 = or(_T_1539, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1542 = not(_T_1541) @[Parameters.scala 37:7] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1547 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1547 is invalid @[Parameters.scala 228:27] + _T_1547[0] <= _T_1528 @[Parameters.scala 228:27] + _T_1547[1] <= _T_1536 @[Parameters.scala 228:27] + _T_1547[2] <= _T_1544 @[Parameters.scala 228:27] + node _T_1553 = or(_T_1547[0], _T_1547[1]) @[Parameters.scala 229:46] + node _T_1554 = or(_T_1553, _T_1547[2]) @[Parameters.scala 229:46] + node _T_1556 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1557 = dshl(_T_1556, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1558 = bits(_T_1557, 5, 0) @[package.scala 19:76] + node _T_1559 = not(_T_1558) @[package.scala 19:40] + node _T_1560 = and(io.in[0].d.bits.addr_lo, _T_1559) @[Edges.scala 17:16] + node _T_1562 = eq(_T_1560, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1564 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + node _T_1566 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:14] + when _T_1566 : @[RISCVPlatform.scala 21:14] + node _T_1567 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1569 = eq(_T_1567, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1569 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1570 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1572 = eq(_T_1570, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1572 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1573 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1575 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1577 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1578 = or(_T_1577, reset) @[RISCVPlatform.scala 21:14] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1580 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1582 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1583 = or(_T_1582, reset) @[RISCVPlatform.scala 21:14] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1585 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1587 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1588 = or(_T_1587, reset) @[RISCVPlatform.scala 21:14] + node _T_1590 = eq(_T_1588, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1590 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1592 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 21:14] + when _T_1592 : @[RISCVPlatform.scala 21:14] + node _T_1593 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1595 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1596 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1598 = eq(_T_1596, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1598 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1599 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1601 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1603 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1604 = or(_T_1603, reset) @[RISCVPlatform.scala 21:14] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1606 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1608 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1609 = or(_T_1608, reset) @[RISCVPlatform.scala 21:14] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1611 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1613 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 21:14] + when _T_1613 : @[RISCVPlatform.scala 21:14] + node _T_1614 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1616 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1617 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1619 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1620 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1622 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1624 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 21:14] + node _T_1625 = or(_T_1624, reset) @[RISCVPlatform.scala 21:14] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1627 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1629 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 21:14] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1632 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1634 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1634 : @[RISCVPlatform.scala 21:14] + node _T_1635 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1637 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1638 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1640 = eq(_T_1638, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1640 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1641 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1643 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1645 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1646 = or(_T_1645, reset) @[RISCVPlatform.scala 21:14] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1648 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + when _T_1650 : @[RISCVPlatform.scala 21:14] + node _T_1651 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1653 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1654 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1656 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1657 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1659 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1662 = or(_T_1661, reset) @[RISCVPlatform.scala 21:14] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1664 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 21:14] + when _T_1666 : @[RISCVPlatform.scala 21:14] + node _T_1667 = or(_T_1554, reset) @[RISCVPlatform.scala 21:14] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1669 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1670 = or(_T_1562, reset) @[RISCVPlatform.scala 21:14] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1672 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1673 = or(_T_1564, reset) @[RISCVPlatform.scala 21:14] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1675 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1678 = or(_T_1677, reset) @[RISCVPlatform.scala 21:14] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1680 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1682 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1683 = or(_T_1682, reset) @[RISCVPlatform.scala 21:14] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1685 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + when io.in[0].e.valid : @[RISCVPlatform.scala 21:14] + node _T_1687 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 21:14] + node _T_1688 = or(_T_1687, reset) @[RISCVPlatform.scala 21:14] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1690 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1691 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1693 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1694 = dshl(_T_1693, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1695 = bits(_T_1694, 5, 0) @[package.scala 19:76] + node _T_1696 = not(_T_1695) @[package.scala 19:40] + node _T_1697 = shr(_T_1696, 3) @[Edges.scala 198:59] + node _T_1698 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1702 = mux(_T_1700, _T_1697, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1704 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1706 = sub(_T_1704, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1707 = asUInt(_T_1706) @[Edges.scala 208:28] + node _T_1708 = tail(_T_1707, 1) @[Edges.scala 208:28] + node _T_1710 = eq(_T_1704, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1712 = eq(_T_1704, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1714 = eq(_T_1702, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1715 = or(_T_1712, _T_1714) @[Edges.scala 210:37] + node _T_1716 = and(_T_1715, _T_1691) @[Edges.scala 211:22] + node _T_1717 = not(_T_1708) @[Edges.scala 212:27] + node _T_1718 = and(_T_1702, _T_1717) @[Edges.scala 212:25] + when _T_1691 : @[Edges.scala 213:17] + node _T_1719 = mux(_T_1710, _T_1702, _T_1708) @[Edges.scala 214:21] + _T_1704 <= _T_1719 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1721 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1723 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1725 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1727 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1729 : UInt, clock @[RISCVPlatform.scala 21:14] + node _T_1731 = eq(_T_1710, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1732 = and(io.in[0].a.valid, _T_1731) @[RISCVPlatform.scala 21:14] + when _T_1732 : @[RISCVPlatform.scala 21:14] + node _T_1733 = eq(io.in[0].a.bits.opcode, _T_1721) @[RISCVPlatform.scala 21:14] + node _T_1734 = or(_T_1733, reset) @[RISCVPlatform.scala 21:14] + node _T_1736 = eq(_T_1734, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1736 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1737 = eq(io.in[0].a.bits.param, _T_1723) @[RISCVPlatform.scala 21:14] + node _T_1738 = or(_T_1737, reset) @[RISCVPlatform.scala 21:14] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1740 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1741 = eq(io.in[0].a.bits.size, _T_1725) @[RISCVPlatform.scala 21:14] + node _T_1742 = or(_T_1741, reset) @[RISCVPlatform.scala 21:14] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1744 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1745 = eq(io.in[0].a.bits.source, _T_1727) @[RISCVPlatform.scala 21:14] + node _T_1746 = or(_T_1745, reset) @[RISCVPlatform.scala 21:14] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1748 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1749 = eq(io.in[0].a.bits.address, _T_1729) @[RISCVPlatform.scala 21:14] + node _T_1750 = or(_T_1749, reset) @[RISCVPlatform.scala 21:14] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1752 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1753 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1754 = and(_T_1753, _T_1710) @[RISCVPlatform.scala 21:14] + when _T_1754 : @[RISCVPlatform.scala 21:14] + _T_1721 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 21:14] + _T_1723 <= io.in[0].a.bits.param @[RISCVPlatform.scala 21:14] + _T_1725 <= io.in[0].a.bits.size @[RISCVPlatform.scala 21:14] + _T_1727 <= io.in[0].a.bits.source @[RISCVPlatform.scala 21:14] + _T_1729 <= io.in[0].a.bits.address @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1755 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1757 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1758 = dshl(_T_1757, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1759 = bits(_T_1758, 5, 0) @[package.scala 19:76] + node _T_1760 = not(_T_1759) @[package.scala 19:40] + node _T_1761 = shr(_T_1760, 3) @[Edges.scala 198:59] + node _T_1762 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1767 = mux(UInt<1>("h00"), _T_1761, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1769 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1771 = sub(_T_1769, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1772 = asUInt(_T_1771) @[Edges.scala 208:28] + node _T_1773 = tail(_T_1772, 1) @[Edges.scala 208:28] + node _T_1775 = eq(_T_1769, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1777 = eq(_T_1769, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1779 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1780 = or(_T_1777, _T_1779) @[Edges.scala 210:37] + node _T_1781 = and(_T_1780, _T_1755) @[Edges.scala 211:22] + node _T_1782 = not(_T_1773) @[Edges.scala 212:27] + node _T_1783 = and(_T_1767, _T_1782) @[Edges.scala 212:25] + when _T_1755 : @[Edges.scala 213:17] + node _T_1784 = mux(_T_1775, _T_1767, _T_1773) @[Edges.scala 214:21] + _T_1769 <= _T_1784 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1786 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1788 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1790 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1792 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1794 : UInt, clock @[RISCVPlatform.scala 21:14] + node _T_1796 = eq(_T_1775, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1797 = and(io.in[0].b.valid, _T_1796) @[RISCVPlatform.scala 21:14] + when _T_1797 : @[RISCVPlatform.scala 21:14] + node _T_1798 = eq(io.in[0].b.bits.opcode, _T_1786) @[RISCVPlatform.scala 21:14] + node _T_1799 = or(_T_1798, reset) @[RISCVPlatform.scala 21:14] + node _T_1801 = eq(_T_1799, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1801 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1802 = eq(io.in[0].b.bits.param, _T_1788) @[RISCVPlatform.scala 21:14] + node _T_1803 = or(_T_1802, reset) @[RISCVPlatform.scala 21:14] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1805 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1806 = eq(io.in[0].b.bits.size, _T_1790) @[RISCVPlatform.scala 21:14] + node _T_1807 = or(_T_1806, reset) @[RISCVPlatform.scala 21:14] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1809 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1810 = eq(io.in[0].b.bits.source, _T_1792) @[RISCVPlatform.scala 21:14] + node _T_1811 = or(_T_1810, reset) @[RISCVPlatform.scala 21:14] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1813 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1814 = eq(io.in[0].b.bits.address, _T_1794) @[RISCVPlatform.scala 21:14] + node _T_1815 = or(_T_1814, reset) @[RISCVPlatform.scala 21:14] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1817 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1818 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1819 = and(_T_1818, _T_1775) @[RISCVPlatform.scala 21:14] + when _T_1819 : @[RISCVPlatform.scala 21:14] + _T_1786 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 21:14] + _T_1788 <= io.in[0].b.bits.param @[RISCVPlatform.scala 21:14] + _T_1790 <= io.in[0].b.bits.size @[RISCVPlatform.scala 21:14] + _T_1792 <= io.in[0].b.bits.source @[RISCVPlatform.scala 21:14] + _T_1794 <= io.in[0].b.bits.address @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1820 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1822 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1823 = dshl(_T_1822, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1824 = bits(_T_1823, 5, 0) @[package.scala 19:76] + node _T_1825 = not(_T_1824) @[package.scala 19:40] + node _T_1826 = shr(_T_1825, 3) @[Edges.scala 198:59] + node _T_1827 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1829 = mux(_T_1827, _T_1826, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1831 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1833 = sub(_T_1831, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1834 = asUInt(_T_1833) @[Edges.scala 208:28] + node _T_1835 = tail(_T_1834, 1) @[Edges.scala 208:28] + node _T_1837 = eq(_T_1831, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1839 = eq(_T_1831, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1841 = eq(_T_1829, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1842 = or(_T_1839, _T_1841) @[Edges.scala 210:37] + node _T_1843 = and(_T_1842, _T_1820) @[Edges.scala 211:22] + node _T_1844 = not(_T_1835) @[Edges.scala 212:27] + node _T_1845 = and(_T_1829, _T_1844) @[Edges.scala 212:25] + when _T_1820 : @[Edges.scala 213:17] + node _T_1846 = mux(_T_1837, _T_1829, _T_1835) @[Edges.scala 214:21] + _T_1831 <= _T_1846 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1848 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1850 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1852 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1854 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1856 : UInt, clock @[RISCVPlatform.scala 21:14] + node _T_1858 = eq(_T_1837, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1859 = and(io.in[0].c.valid, _T_1858) @[RISCVPlatform.scala 21:14] + when _T_1859 : @[RISCVPlatform.scala 21:14] + node _T_1860 = eq(io.in[0].c.bits.opcode, _T_1848) @[RISCVPlatform.scala 21:14] + node _T_1861 = or(_T_1860, reset) @[RISCVPlatform.scala 21:14] + node _T_1863 = eq(_T_1861, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1863 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1864 = eq(io.in[0].c.bits.param, _T_1850) @[RISCVPlatform.scala 21:14] + node _T_1865 = or(_T_1864, reset) @[RISCVPlatform.scala 21:14] + node _T_1867 = eq(_T_1865, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1867 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1868 = eq(io.in[0].c.bits.size, _T_1852) @[RISCVPlatform.scala 21:14] + node _T_1869 = or(_T_1868, reset) @[RISCVPlatform.scala 21:14] + node _T_1871 = eq(_T_1869, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1871 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1872 = eq(io.in[0].c.bits.source, _T_1854) @[RISCVPlatform.scala 21:14] + node _T_1873 = or(_T_1872, reset) @[RISCVPlatform.scala 21:14] + node _T_1875 = eq(_T_1873, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1875 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1876 = eq(io.in[0].c.bits.address, _T_1856) @[RISCVPlatform.scala 21:14] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 21:14] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1879 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1880 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1881 = and(_T_1880, _T_1837) @[RISCVPlatform.scala 21:14] + when _T_1881 : @[RISCVPlatform.scala 21:14] + _T_1848 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 21:14] + _T_1850 <= io.in[0].c.bits.param @[RISCVPlatform.scala 21:14] + _T_1852 <= io.in[0].c.bits.size @[RISCVPlatform.scala 21:14] + _T_1854 <= io.in[0].c.bits.source @[RISCVPlatform.scala 21:14] + _T_1856 <= io.in[0].c.bits.address @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1882 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1884 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1885 = dshl(_T_1884, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1886 = bits(_T_1885, 5, 0) @[package.scala 19:76] + node _T_1887 = not(_T_1886) @[package.scala 19:40] + node _T_1888 = shr(_T_1887, 3) @[Edges.scala 198:59] + node _T_1889 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1891 = mux(_T_1889, _T_1888, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1893 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1895 = sub(_T_1893, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1896 = asUInt(_T_1895) @[Edges.scala 208:28] + node _T_1897 = tail(_T_1896, 1) @[Edges.scala 208:28] + node _T_1899 = eq(_T_1893, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1901 = eq(_T_1893, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1903 = eq(_T_1891, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1904 = or(_T_1901, _T_1903) @[Edges.scala 210:37] + node _T_1905 = and(_T_1904, _T_1882) @[Edges.scala 211:22] + node _T_1906 = not(_T_1897) @[Edges.scala 212:27] + node _T_1907 = and(_T_1891, _T_1906) @[Edges.scala 212:25] + when _T_1882 : @[Edges.scala 213:17] + node _T_1908 = mux(_T_1899, _T_1891, _T_1897) @[Edges.scala 214:21] + _T_1893 <= _T_1908 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1910 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1912 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1914 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1916 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1918 : UInt, clock @[RISCVPlatform.scala 21:14] + reg _T_1920 : UInt, clock @[RISCVPlatform.scala 21:14] + node _T_1922 = eq(_T_1899, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_1923 = and(io.in[0].d.valid, _T_1922) @[RISCVPlatform.scala 21:14] + when _T_1923 : @[RISCVPlatform.scala 21:14] + node _T_1924 = eq(io.in[0].d.bits.opcode, _T_1910) @[RISCVPlatform.scala 21:14] + node _T_1925 = or(_T_1924, reset) @[RISCVPlatform.scala 21:14] + node _T_1927 = eq(_T_1925, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1927 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1928 = eq(io.in[0].d.bits.param, _T_1912) @[RISCVPlatform.scala 21:14] + node _T_1929 = or(_T_1928, reset) @[RISCVPlatform.scala 21:14] + node _T_1931 = eq(_T_1929, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1931 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1932 = eq(io.in[0].d.bits.size, _T_1914) @[RISCVPlatform.scala 21:14] + node _T_1933 = or(_T_1932, reset) @[RISCVPlatform.scala 21:14] + node _T_1935 = eq(_T_1933, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1935 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1936 = eq(io.in[0].d.bits.source, _T_1916) @[RISCVPlatform.scala 21:14] + node _T_1937 = or(_T_1936, reset) @[RISCVPlatform.scala 21:14] + node _T_1939 = eq(_T_1937, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1939 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1940 = eq(io.in[0].d.bits.sink, _T_1918) @[RISCVPlatform.scala 21:14] + node _T_1941 = or(_T_1940, reset) @[RISCVPlatform.scala 21:14] + node _T_1943 = eq(_T_1941, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1943 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1944 = eq(io.in[0].d.bits.addr_lo, _T_1920) @[RISCVPlatform.scala 21:14] + node _T_1945 = or(_T_1944, reset) @[RISCVPlatform.scala 21:14] + node _T_1947 = eq(_T_1945, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_1947 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_1948 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1949 = and(_T_1948, _T_1899) @[RISCVPlatform.scala 21:14] + when _T_1949 : @[RISCVPlatform.scala 21:14] + _T_1910 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 21:14] + _T_1912 <= io.in[0].d.bits.param @[RISCVPlatform.scala 21:14] + _T_1914 <= io.in[0].d.bits.size @[RISCVPlatform.scala 21:14] + _T_1916 <= io.in[0].d.bits.source @[RISCVPlatform.scala 21:14] + _T_1918 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 21:14] + _T_1920 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + reg _T_1951 : UInt<48>, clock with : (reset => (reset, UInt<48>("h00"))) @[Reg.scala 26:44] + node _T_1952 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1954 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1955 = dshl(_T_1954, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1956 = bits(_T_1955, 5, 0) @[package.scala 19:76] + node _T_1957 = not(_T_1956) @[package.scala 19:40] + node _T_1958 = shr(_T_1957, 3) @[Edges.scala 198:59] + node _T_1959 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1961 = eq(_T_1959, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1963 = mux(_T_1961, _T_1958, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1965 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1967 = sub(_T_1965, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1968 = asUInt(_T_1967) @[Edges.scala 208:28] + node _T_1969 = tail(_T_1968, 1) @[Edges.scala 208:28] + node _T_1971 = eq(_T_1965, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1973 = eq(_T_1965, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1975 = eq(_T_1963, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1976 = or(_T_1973, _T_1975) @[Edges.scala 210:37] + node _T_1977 = and(_T_1976, _T_1952) @[Edges.scala 211:22] + node _T_1978 = not(_T_1969) @[Edges.scala 212:27] + node _T_1979 = and(_T_1963, _T_1978) @[Edges.scala 212:25] + when _T_1952 : @[Edges.scala 213:17] + node _T_1980 = mux(_T_1971, _T_1963, _T_1969) @[Edges.scala 214:21] + _T_1965 <= _T_1980 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1981 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1983 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1984 = dshl(_T_1983, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1985 = bits(_T_1984, 5, 0) @[package.scala 19:76] + node _T_1986 = not(_T_1985) @[package.scala 19:40] + node _T_1987 = shr(_T_1986, 3) @[Edges.scala 198:59] + node _T_1988 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1990 = mux(_T_1988, _T_1987, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1992 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1994 = sub(_T_1992, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1995 = asUInt(_T_1994) @[Edges.scala 208:28] + node _T_1996 = tail(_T_1995, 1) @[Edges.scala 208:28] + node _T_1998 = eq(_T_1992, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2000 = eq(_T_1992, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2002 = eq(_T_1990, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2003 = or(_T_2000, _T_2002) @[Edges.scala 210:37] + node _T_2004 = and(_T_2003, _T_1981) @[Edges.scala 211:22] + node _T_2005 = not(_T_1996) @[Edges.scala 212:27] + node _T_2006 = and(_T_1990, _T_2005) @[Edges.scala 212:25] + when _T_1981 : @[Edges.scala 213:17] + node _T_2007 = mux(_T_1998, _T_1990, _T_1996) @[Edges.scala 214:21] + _T_1992 <= _T_2007 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_2009 : UInt<48> + _T_2009 is invalid + _T_2009 <= UInt<48>("h00") + node _T_2010 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2010 : @[RISCVPlatform.scala 21:14] + when _T_1976 : @[RISCVPlatform.scala 21:14] + node _T_2012 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2009 <= _T_2012 @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_2013 = dshr(_T_1951, io.in[0].a.bits.source) @[RISCVPlatform.scala 21:14] + node _T_2014 = bits(_T_2013, 0, 0) @[RISCVPlatform.scala 21:14] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + node _T_2017 = or(_T_2016, reset) @[RISCVPlatform.scala 21:14] + node _T_2019 = eq(_T_2017, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_2019 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + wire _T_2021 : UInt<48> + _T_2021 is invalid + _T_2021 <= UInt<48>("h00") + node _T_2022 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2024 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 21:14] + node _T_2025 = and(_T_2022, _T_2024) @[RISCVPlatform.scala 21:14] + when _T_2025 : @[RISCVPlatform.scala 21:14] + when _T_2003 : @[RISCVPlatform.scala 21:14] + node _T_2027 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2021 <= _T_2027 @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_2028 = or(_T_2009, _T_1951) @[RISCVPlatform.scala 21:14] + node _T_2029 = dshr(_T_2028, io.in[0].d.bits.source) @[RISCVPlatform.scala 21:14] + node _T_2030 = bits(_T_2029, 0, 0) @[RISCVPlatform.scala 21:14] + node _T_2031 = or(_T_2030, reset) @[RISCVPlatform.scala 21:14] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[RISCVPlatform.scala 21:14] + when _T_2033 : @[RISCVPlatform.scala 21:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:21:14)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 21:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + skip @[RISCVPlatform.scala 21:14] + node _T_2034 = or(_T_1951, _T_2009) @[RISCVPlatform.scala 21:14] + node _T_2035 = not(_T_2021) @[RISCVPlatform.scala 21:14] + node _T_2036 = and(_T_2034, _T_2035) @[RISCVPlatform.scala 21:14] + _T_1951 <= _T_2036 @[RISCVPlatform.scala 21:14] + + module Repeater_4 : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLFragmenter_plic : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg _T_531 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + reg _T_533 : UInt, clock @[Fragmenter.scala 136:22] + node _T_534 = bits(io.out.0.d.bits.source, 2, 0) @[Fragmenter.scala 137:39] + node _T_536 = eq(_T_531, UInt<1>("h00")) @[Fragmenter.scala 138:27] + node _T_538 = bits(io.out.0.d.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_539 = dshl(UInt<1>("h01"), _T_538) @[OneHot.scala 49:12] + node _T_540 = bits(_T_539, 3, 0) @[OneHot.scala 49:37] + node _T_542 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_543 = dshl(_T_542, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_544 = bits(_T_543, 2, 0) @[package.scala 19:76] + node _T_545 = not(_T_544) @[package.scala 19:40] + node _T_546 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_547 = shl(_T_534, 0) @[Fragmenter.scala 144:38] + node _T_548 = shr(_T_545, 3) @[Fragmenter.scala 145:34] + node _T_550 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Fragmenter.scala 146:15] + node _T_551 = and(_T_547, _T_548) @[Fragmenter.scala 146:48] + node _T_553 = eq(_T_551, UInt<1>("h00")) @[Fragmenter.scala 146:63] + node _T_554 = or(_T_550, _T_553) @[Fragmenter.scala 146:28] + node _T_555 = or(_T_554, reset) @[Fragmenter.scala 146:14] + node _T_557 = eq(_T_555, UInt<1>("h00")) @[Fragmenter.scala 146:14] + when _T_557 : @[Fragmenter.scala 146:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:146 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n") @[Fragmenter.scala 146:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 146:14] + skip @[Fragmenter.scala 146:14] + node _T_559 = mux(_T_546, _T_548, UInt<1>("h00")) @[Fragmenter.scala 147:48] + node _T_560 = or(_T_547, _T_559) @[Fragmenter.scala 147:43] + node _T_562 = shr(_T_540, 3) @[Fragmenter.scala 148:58] + node _T_563 = mux(_T_546, UInt<1>("h01"), _T_562) @[Fragmenter.scala 148:30] + node _T_564 = shl(_T_534, 3) @[Fragmenter.scala 150:45] + node _T_565 = or(_T_564, _T_545) @[Fragmenter.scala 150:67] + node _T_566 = shl(_T_565, 1) @[package.scala 17:29] + node _T_568 = or(_T_566, UInt<1>("h01")) @[package.scala 17:34] + node _T_570 = cat(UInt<1>("h00"), _T_565) @[Cat.scala 30:58] + node _T_571 = not(_T_570) @[package.scala 17:47] + node _T_572 = and(_T_568, _T_571) @[package.scala 17:45] + node _T_573 = bits(_T_572, 6, 4) @[OneHot.scala 26:18] + node _T_574 = bits(_T_572, 3, 0) @[OneHot.scala 27:18] + node _T_576 = neq(_T_573, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_577 = or(_T_573, _T_574) @[OneHot.scala 28:28] + node _T_578 = bits(_T_577, 3, 2) @[OneHot.scala 26:18] + node _T_579 = bits(_T_577, 1, 0) @[OneHot.scala 27:18] + node _T_581 = neq(_T_578, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_582 = or(_T_578, _T_579) @[OneHot.scala 28:28] + node _T_583 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_584 = cat(_T_581, _T_583) @[Cat.scala 30:58] + node _T_585 = cat(_T_576, _T_584) @[Cat.scala 30:58] + node _T_586 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_586 : @[Fragmenter.scala 152:27] + node _T_587 = sub(_T_531, _T_563) @[Fragmenter.scala 153:53] + node _T_588 = asUInt(_T_587) @[Fragmenter.scala 153:53] + node _T_589 = tail(_T_588, 1) @[Fragmenter.scala 153:53] + node _T_590 = mux(_T_536, _T_560, _T_589) @[Fragmenter.scala 153:22] + _T_531 <= _T_590 @[Fragmenter.scala 153:16] + when _T_536 : @[Fragmenter.scala 154:23] + _T_533 <= _T_585 @[Fragmenter.scala 154:31] + skip @[Fragmenter.scala 154:23] + skip @[Fragmenter.scala 152:27] + node _T_592 = eq(_T_546, UInt<1>("h00")) @[Fragmenter.scala 158:18] + node _T_594 = neq(_T_534, UInt<1>("h00")) @[Fragmenter.scala 158:41] + node _T_595 = and(_T_592, _T_594) @[Fragmenter.scala 158:28] + node _T_596 = or(io.in.0.d.ready, _T_595) @[Fragmenter.scala 159:33] + io.out.0.d.ready <= _T_596 @[Fragmenter.scala 159:19] + node _T_598 = eq(_T_595, UInt<1>("h00")) @[Fragmenter.scala 160:37] + node _T_599 = and(io.out.0.d.valid, _T_598) @[Fragmenter.scala 160:34] + io.in.0.d.valid <= _T_599 @[Fragmenter.scala 160:19] + io.in.0.d.bits <- io.out.0.d.bits @[Fragmenter.scala 161:19] + node _T_600 = not(_T_545) @[Fragmenter.scala 162:49] + node _T_601 = and(io.out.0.d.bits.addr_lo, _T_600) @[Fragmenter.scala 162:47] + io.in.0.d.bits.addr_lo <= _T_601 @[Fragmenter.scala 162:25] + node _T_602 = shr(io.out.0.d.bits.source, 3) @[Fragmenter.scala 163:45] + io.in.0.d.bits.source <= _T_602 @[Fragmenter.scala 163:24] + node _T_603 = mux(_T_536, _T_585, _T_533) @[Fragmenter.scala 164:30] + io.in.0.d.bits.size <= _T_603 @[Fragmenter.scala 164:24] + reg _T_605 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_606 = or(_T_605, io.out.0.d.bits.error) @[Fragmenter.scala 168:29] + node _T_607 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_607 : @[Fragmenter.scala 169:27] + node _T_609 = mux(_T_595, _T_606, UInt<1>("h00")) @[Fragmenter.scala 169:43] + _T_605 <= _T_609 @[Fragmenter.scala 169:37] + skip @[Fragmenter.scala 169:27] + io.in.0.d.bits.error <= _T_606 @[Fragmenter.scala 170:23] + inst Repeater of Repeater_4 @[Fragmenter.scala 190:28] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.enq <- io.in.0.a @[Fragmenter.scala 191:23] + node _T_615 = xor(Repeater.io.deq.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_616 = cvt(_T_615) @[Parameters.scala 117:49] + node _T_618 = and(_T_616, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_619 = asSInt(_T_618) @[Parameters.scala 117:52] + node _T_621 = eq(_T_619, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_624 : UInt<1>[1] @[Parameters.scala 112:36] + _T_624 is invalid @[Parameters.scala 112:36] + _T_624[0] <= _T_621 @[Parameters.scala 112:36] + node _T_634 = eq(UInt<3>("h05"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_635 = mux(_T_634, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 46:16] + node _T_636 = eq(UInt<3>("h04"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_637 = mux(_T_636, UInt<2>("h03"), _T_635) @[Mux.scala 46:16] + node _T_638 = eq(UInt<2>("h03"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_639 = mux(_T_638, UInt<2>("h03"), _T_637) @[Mux.scala 46:16] + node _T_640 = eq(UInt<2>("h02"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_641 = mux(_T_640, UInt<2>("h03"), _T_639) @[Mux.scala 46:16] + node _T_642 = eq(UInt<1>("h01"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_643 = mux(_T_642, UInt<2>("h03"), _T_641) @[Mux.scala 46:16] + node _T_644 = eq(UInt<1>("h00"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_645 = mux(_T_644, UInt<2>("h03"), _T_643) @[Mux.scala 46:16] + node _T_646 = gt(Repeater.io.deq.bits.size, _T_645) @[Fragmenter.scala 213:29] + node _T_647 = mux(_T_646, _T_645, Repeater.io.deq.bits.size) @[Fragmenter.scala 213:22] + node _T_649 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_650 = dshl(_T_649, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_651 = bits(_T_650, 5, 0) @[package.scala 19:76] + node _T_652 = not(_T_651) @[package.scala 19:40] + node _T_654 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_655 = dshl(_T_654, _T_647) @[package.scala 19:71] + node _T_656 = bits(_T_655, 2, 0) @[package.scala 19:76] + node _T_657 = not(_T_656) @[package.scala 19:40] + node _T_658 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_660 = eq(_T_658, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_662 = mux(_T_660, UInt<1>("h00"), _T_657) @[Fragmenter.scala 217:22] + reg _T_664 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[Fragmenter.scala 220:27] + node _T_667 = shr(_T_652, 3) @[Fragmenter.scala 221:46] + node _T_669 = sub(_T_664, UInt<1>("h01")) @[Fragmenter.scala 221:77] + node _T_670 = asUInt(_T_669) @[Fragmenter.scala 221:77] + node _T_671 = tail(_T_670, 1) @[Fragmenter.scala 221:77] + node _T_672 = mux(_T_666, _T_667, _T_671) @[Fragmenter.scala 221:28] + node _T_673 = not(_T_672) @[Fragmenter.scala 222:26] + node _T_674 = shr(_T_662, 3) @[Fragmenter.scala 222:48] + node _T_675 = or(_T_673, _T_674) @[Fragmenter.scala 222:39] + node _T_676 = not(_T_675) @[Fragmenter.scala 222:24] + node _T_677 = shr(_T_672, 0) @[Fragmenter.scala 223:38] + node _T_678 = not(_T_677) @[Fragmenter.scala 223:24] + node _T_679 = shr(_T_657, 3) @[Fragmenter.scala 223:82] + node _T_680 = or(_T_678, _T_679) @[Fragmenter.scala 223:70] + node _T_681 = not(_T_680) @[Fragmenter.scala 223:22] + node _T_682 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Fragmenter.scala 225:27] + _T_664 <= _T_676 @[Fragmenter.scala 225:36] + skip @[Fragmenter.scala 225:27] + node _T_684 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 227:29] + node _T_686 = neq(_T_681, UInt<1>("h00")) @[Fragmenter.scala 227:51] + node _T_687 = and(_T_684, _T_686) @[Fragmenter.scala 227:39] + Repeater.io.repeat <= _T_687 @[Fragmenter.scala 227:26] + io.out.0.a <- Repeater.io.deq @[Fragmenter.scala 228:13] + node _T_688 = not(_T_681) @[Fragmenter.scala 229:50] + node _T_689 = shl(_T_688, 3) @[Fragmenter.scala 229:60] + node _T_690 = and(_T_689, _T_652) @[Fragmenter.scala 229:81] + node _T_691 = or(Repeater.io.deq.bits.address, _T_690) @[Fragmenter.scala 229:47] + io.out.0.a.bits.address <= _T_691 @[Fragmenter.scala 229:26] + node _T_692 = cat(Repeater.io.deq.bits.source, _T_681) @[Cat.scala 30:58] + io.out.0.a.bits.source <= _T_692 @[Fragmenter.scala 230:25] + io.out.0.a.bits.size <= _T_647 @[Fragmenter.scala 231:23] + node _T_694 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 234:15] + node _T_696 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 234:36] + node _T_697 = or(_T_694, _T_696) @[Fragmenter.scala 234:33] + node _T_698 = or(_T_697, reset) @[Fragmenter.scala 234:14] + node _T_700 = eq(_T_698, UInt<1>("h00")) @[Fragmenter.scala 234:14] + when _T_700 : @[Fragmenter.scala 234:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:234 assert (!repeater.io.full || !aHasData)\n") @[Fragmenter.scala 234:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 234:14] + skip @[Fragmenter.scala 234:14] + io.out.0.a.bits.data <= io.in.0.a.bits.data @[Fragmenter.scala 235:23] + node _T_703 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 237:15] + node _T_704 = eq(Repeater.io.deq.bits.mask, UInt<8>("h0ff")) @[Fragmenter.scala 237:51] + node _T_705 = or(_T_703, _T_704) @[Fragmenter.scala 237:33] + node _T_706 = or(_T_705, reset) @[Fragmenter.scala 237:14] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 237:14] + when _T_708 : @[Fragmenter.scala 237:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") @[Fragmenter.scala 237:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 237:14] + skip @[Fragmenter.scala 237:14] + node _T_709 = mux(Repeater.io.full, UInt<8>("h0ff"), io.in.0.a.bits.mask) @[Fragmenter.scala 238:29] + io.out.0.a.bits.mask <= _T_709 @[Fragmenter.scala 238:23] + io.in.0.b.valid <= UInt<1>("h00") @[Fragmenter.scala 241:18] + io.in.0.c.ready <= UInt<1>("h01") @[Fragmenter.scala 242:18] + io.in.0.e.ready <= UInt<1>("h01") @[Fragmenter.scala 243:18] + io.out.0.b.ready <= UInt<1>("h01") @[Fragmenter.scala 244:19] + io.out.0.c.valid <= UInt<1>("h00") @[Fragmenter.scala 245:19] + io.out.0.e.valid <= UInt<1>("h00") @[Fragmenter.scala 246:19] + + module TLMonitor_27 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 22:61] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 22:61] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_608 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:61] + when _T_708 : @[RISCVPlatform.scala 22:61] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[RISCVPlatform.scala 22:61] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_725 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_726 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_728 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_731 = or(_T_730, reset) @[RISCVPlatform.scala 22:61] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_733 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_734 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_736 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[RISCVPlatform.scala 22:61] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_741 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_742 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 22:61] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_745 = or(_T_744, reset) @[RISCVPlatform.scala 22:61] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_747 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:61] + when _T_749 : @[RISCVPlatform.scala 22:61] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[RISCVPlatform.scala 22:61] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_770 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_771 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_773 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_774 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_776 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_779 = or(_T_778, reset) @[RISCVPlatform.scala 22:61] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_781 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 22:61] + node _T_783 = or(_T_782, reset) @[RISCVPlatform.scala 22:61] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_785 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_787 : @[RISCVPlatform.scala 22:61] + node _T_790 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_792 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_793 = and(_T_790, _T_792) @[Parameters.scala 63:37] + node _T_794 = or(UInt<1>("h00"), _T_793) @[Parameters.scala 132:31] + node _T_796 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_797 = cvt(_T_796) @[Parameters.scala 117:49] + node _T_799 = and(_T_797, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_800 = asSInt(_T_799) @[Parameters.scala 117:52] + node _T_802 = eq(_T_800, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = and(_T_794, _T_802) @[Parameters.scala 132:56] + node _T_805 = or(UInt<1>("h00"), _T_803) @[Parameters.scala 134:30] + node _T_806 = or(_T_805, reset) @[RISCVPlatform.scala 22:61] + node _T_808 = eq(_T_806, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_808 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_809 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_811 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_812 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_814 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_816 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_817 = or(_T_816, reset) @[RISCVPlatform.scala 22:61] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_819 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_820 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 22:61] + node _T_821 = or(_T_820, reset) @[RISCVPlatform.scala 22:61] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_823 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_825 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + when _T_825 : @[RISCVPlatform.scala 22:61] + node _T_828 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_830 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_831 = and(_T_828, _T_830) @[Parameters.scala 63:37] + node _T_832 = or(UInt<1>("h00"), _T_831) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_841) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, reset) @[RISCVPlatform.scala 22:61] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_846 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_847 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_849 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_850 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_852 = eq(_T_850, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_852 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_854 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_855 = or(_T_854, reset) @[RISCVPlatform.scala 22:61] + node _T_857 = eq(_T_855, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_857 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_858 = not(_T_706) @[RISCVPlatform.scala 22:61] + node _T_859 = and(io.in[0].a.bits.mask, _T_858) @[RISCVPlatform.scala 22:61] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_862 = or(_T_861, reset) @[RISCVPlatform.scala 22:61] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_864 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_866 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:61] + when _T_866 : @[RISCVPlatform.scala 22:61] + node _T_869 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_871 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_872 = cvt(_T_871) @[Parameters.scala 117:49] + node _T_874 = and(_T_872, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_875 = asSInt(_T_874) @[Parameters.scala 117:52] + node _T_877 = eq(_T_875, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = and(_T_869, _T_877) @[Parameters.scala 132:56] + node _T_880 = or(UInt<1>("h00"), _T_878) @[Parameters.scala 134:30] + node _T_881 = or(_T_880, reset) @[RISCVPlatform.scala 22:61] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_883 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_884 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_886 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_887 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_889 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_891 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_892 = or(_T_891, reset) @[RISCVPlatform.scala 22:61] + node _T_894 = eq(_T_892, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_894 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_895 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 22:61] + node _T_896 = or(_T_895, reset) @[RISCVPlatform.scala 22:61] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_898 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_900 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + when _T_900 : @[RISCVPlatform.scala 22:61] + node _T_903 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_905 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_906 = cvt(_T_905) @[Parameters.scala 117:49] + node _T_908 = and(_T_906, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_909 = asSInt(_T_908) @[Parameters.scala 117:52] + node _T_911 = eq(_T_909, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = and(_T_903, _T_911) @[Parameters.scala 132:56] + node _T_914 = or(UInt<1>("h00"), _T_912) @[Parameters.scala 134:30] + node _T_915 = or(_T_914, reset) @[RISCVPlatform.scala 22:61] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_917 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_918 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_920 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_921 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_923 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_925 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_926 = or(_T_925, reset) @[RISCVPlatform.scala 22:61] + node _T_928 = eq(_T_926, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_928 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_929 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 22:61] + node _T_930 = or(_T_929, reset) @[RISCVPlatform.scala 22:61] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_932 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:61] + when _T_934 : @[RISCVPlatform.scala 22:61] + node _T_937 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_939 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_940 = cvt(_T_939) @[Parameters.scala 117:49] + node _T_942 = and(_T_940, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_943 = asSInt(_T_942) @[Parameters.scala 117:52] + node _T_945 = eq(_T_943, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_946 = and(_T_937, _T_945) @[Parameters.scala 132:56] + node _T_948 = or(UInt<1>("h00"), _T_946) @[Parameters.scala 134:30] + node _T_949 = or(_T_948, reset) @[RISCVPlatform.scala 22:61] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_951 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_952 = or(_T_630, reset) @[RISCVPlatform.scala 22:61] + node _T_954 = eq(_T_952, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_954 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_955 = or(_T_638, reset) @[RISCVPlatform.scala 22:61] + node _T_957 = eq(_T_955, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_957 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_958 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 22:61] + node _T_959 = or(_T_958, reset) @[RISCVPlatform.scala 22:61] + node _T_961 = eq(_T_959, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_961 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + when io.in[0].b.valid : @[RISCVPlatform.scala 22:61] + node _T_963 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_964 = or(_T_963, reset) @[RISCVPlatform.scala 22:61] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_966 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_968 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_977 : UInt<1>[1] @[Parameters.scala 110:36] + _T_977 is invalid @[Parameters.scala 110:36] + _T_977[0] <= _T_974 @[Parameters.scala 110:36] + node _T_982 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_983 = dshl(_T_982, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_984 = bits(_T_983, 5, 0) @[package.scala 19:76] + node _T_985 = not(_T_984) @[package.scala 19:40] + node _T_986 = and(io.in[0].b.bits.address, _T_985) @[Edges.scala 17:16] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_990 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_991 = dshl(UInt<1>("h01"), _T_990) @[OneHot.scala 49:12] + node _T_992 = bits(_T_991, 2, 0) @[OneHot.scala 49:37] + node _T_994 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_996 = bits(_T_992, 2, 2) @[package.scala 44:26] + node _T_997 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_999 = eq(_T_997, UInt<1>("h00")) @[package.scala 46:20] + node _T_1000 = and(UInt<1>("h01"), _T_999) @[package.scala 49:27] + node _T_1001 = and(_T_996, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_994, _T_1001) @[package.scala 50:29] + node _T_1003 = and(UInt<1>("h01"), _T_997) @[package.scala 49:27] + node _T_1004 = and(_T_996, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_994, _T_1004) @[package.scala 50:29] + node _T_1006 = bits(_T_992, 1, 1) @[package.scala 44:26] + node _T_1007 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1009 = eq(_T_1007, UInt<1>("h00")) @[package.scala 46:20] + node _T_1010 = and(_T_1000, _T_1009) @[package.scala 49:27] + node _T_1011 = and(_T_1006, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_1002, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_1000, _T_1007) @[package.scala 49:27] + node _T_1014 = and(_T_1006, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_1002, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_1003, _T_1009) @[package.scala 49:27] + node _T_1017 = and(_T_1006, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_1005, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1003, _T_1007) @[package.scala 49:27] + node _T_1020 = and(_T_1006, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1005, _T_1020) @[package.scala 50:29] + node _T_1022 = bits(_T_992, 0, 0) @[package.scala 44:26] + node _T_1023 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[package.scala 46:20] + node _T_1026 = and(_T_1010, _T_1025) @[package.scala 49:27] + node _T_1027 = and(_T_1022, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1012, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1010, _T_1023) @[package.scala 49:27] + node _T_1030 = and(_T_1022, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1012, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1013, _T_1025) @[package.scala 49:27] + node _T_1033 = and(_T_1022, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1015, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1013, _T_1023) @[package.scala 49:27] + node _T_1036 = and(_T_1022, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1015, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1016, _T_1025) @[package.scala 49:27] + node _T_1039 = and(_T_1022, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1018, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1016, _T_1023) @[package.scala 49:27] + node _T_1042 = and(_T_1022, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1018, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1019, _T_1025) @[package.scala 49:27] + node _T_1045 = and(_T_1022, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1021, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1019, _T_1023) @[package.scala 49:27] + node _T_1048 = and(_T_1022, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1021, _T_1048) @[package.scala 50:29] + node _T_1050 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1050) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1054 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1058 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:61] + when _T_1058 : @[RISCVPlatform.scala 22:61] + node _T_1060 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1061 = not(_T_1060) @[Parameters.scala 37:9] + node _T_1063 = or(_T_1061, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1064 = not(_T_1063) @[Parameters.scala 37:7] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1068 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1070 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1073 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1073 is invalid @[Parameters.scala 228:27] + _T_1073[0] <= _T_1066 @[Parameters.scala 228:27] + _T_1073[1] <= _T_1068 @[Parameters.scala 228:27] + _T_1073[2] <= _T_1070 @[Parameters.scala 228:27] + node _T_1081 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1083 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1084 = and(_T_1081, _T_1083) @[Parameters.scala 63:37] + node _T_1087 = mux(_T_1073[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1089 = mux(_T_1073[1], _T_1084, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1073[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1093 = or(_T_1087, _T_1089) @[Mux.scala 19:72] + node _T_1094 = or(_T_1093, _T_1091) @[Mux.scala 19:72] + wire _T_1096 : UInt<1> @[Mux.scala 19:72] + _T_1096 is invalid @[Mux.scala 19:72] + _T_1096 <= _T_1094 @[Mux.scala 19:72] + node _T_1097 = or(_T_1096, reset) @[RISCVPlatform.scala 22:61] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1099 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1100 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1102 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1104 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1105 = or(_T_1104, reset) @[RISCVPlatform.scala 22:61] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1107 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1108 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1110 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1112 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1113 = or(_T_1112, reset) @[RISCVPlatform.scala 22:61] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1115 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1116 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 22:61] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1119 = or(_T_1118, reset) @[RISCVPlatform.scala 22:61] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1121 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1123 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:61] + when _T_1123 : @[RISCVPlatform.scala 22:61] + node _T_1125 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1127 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1128 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1130 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1131 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1133 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1135 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1136 = or(_T_1135, reset) @[RISCVPlatform.scala 22:61] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1138 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1139 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 22:61] + node _T_1140 = or(_T_1139, reset) @[RISCVPlatform.scala 22:61] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1142 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1144 : @[RISCVPlatform.scala 22:61] + node _T_1146 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1148 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1149 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1151 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1152 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1154 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1156 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1157 = or(_T_1156, reset) @[RISCVPlatform.scala 22:61] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1159 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 22:61] + node _T_1161 = or(_T_1160, reset) @[RISCVPlatform.scala 22:61] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1163 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + when _T_1165 : @[RISCVPlatform.scala 22:61] + node _T_1167 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1169 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1170 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1172 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1173 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1175 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1177 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1178 = or(_T_1177, reset) @[RISCVPlatform.scala 22:61] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1180 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1181 = not(_T_1056) @[RISCVPlatform.scala 22:61] + node _T_1182 = and(io.in[0].b.bits.mask, _T_1181) @[RISCVPlatform.scala 22:61] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 22:61] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1187 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:61] + when _T_1189 : @[RISCVPlatform.scala 22:61] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1193 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1194 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1196 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1197 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1199 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 22:61] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1204 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1205 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 22:61] + node _T_1206 = or(_T_1205, reset) @[RISCVPlatform.scala 22:61] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1208 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1210 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + when _T_1210 : @[RISCVPlatform.scala 22:61] + node _T_1212 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1214 = eq(_T_1212, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1214 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1215 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1217 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1218 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1220 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1222 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1223 = or(_T_1222, reset) @[RISCVPlatform.scala 22:61] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1225 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1226 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 22:61] + node _T_1227 = or(_T_1226, reset) @[RISCVPlatform.scala 22:61] + node _T_1229 = eq(_T_1227, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1229 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1231 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:61] + when _T_1231 : @[RISCVPlatform.scala 22:61] + node _T_1233 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:61] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1235 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1236 = or(_T_977[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1238 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1239 = or(_T_988, reset) @[RISCVPlatform.scala 22:61] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1241 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1242 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 22:61] + node _T_1243 = or(_T_1242, reset) @[RISCVPlatform.scala 22:61] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1245 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + when io.in[0].c.valid : @[RISCVPlatform.scala 22:61] + node _T_1247 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1248 = or(_T_1247, reset) @[RISCVPlatform.scala 22:61] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1250 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1252 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1253 = not(_T_1252) @[Parameters.scala 37:9] + node _T_1255 = or(_T_1253, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1256 = not(_T_1255) @[Parameters.scala 37:7] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1260 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1262 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1265 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1265 is invalid @[Parameters.scala 228:27] + _T_1265[0] <= _T_1258 @[Parameters.scala 228:27] + _T_1265[1] <= _T_1260 @[Parameters.scala 228:27] + _T_1265[2] <= _T_1262 @[Parameters.scala 228:27] + node _T_1271 = or(_T_1265[0], _T_1265[1]) @[Parameters.scala 229:46] + node _T_1272 = or(_T_1271, _T_1265[2]) @[Parameters.scala 229:46] + node _T_1274 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1275 = dshl(_T_1274, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1276 = bits(_T_1275, 5, 0) @[package.scala 19:76] + node _T_1277 = not(_T_1276) @[package.scala 19:40] + node _T_1278 = and(io.in[0].c.bits.address, _T_1277) @[Edges.scala 17:16] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1282 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1283 = cvt(_T_1282) @[Parameters.scala 117:49] + node _T_1285 = and(_T_1283, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1286 = asSInt(_T_1285) @[Parameters.scala 117:52] + node _T_1288 = eq(_T_1286, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1291 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1291 is invalid @[Parameters.scala 110:36] + _T_1291[0] <= _T_1288 @[Parameters.scala 110:36] + node _T_1296 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:61] + when _T_1296 : @[RISCVPlatform.scala 22:61] + node _T_1297 = or(_T_1291[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1299 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1300 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1302 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1304 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1305 = or(_T_1304, reset) @[RISCVPlatform.scala 22:61] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1307 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1308 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1310 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1312 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1313 = or(_T_1312, reset) @[RISCVPlatform.scala 22:61] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1315 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1317 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1318 = or(_T_1317, reset) @[RISCVPlatform.scala 22:61] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1320 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1322 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:61] + when _T_1322 : @[RISCVPlatform.scala 22:61] + node _T_1323 = or(_T_1291[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1325 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1326 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1328 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1330 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1331 = or(_T_1330, reset) @[RISCVPlatform.scala 22:61] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1333 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1334 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1336 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1338 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1339 = or(_T_1338, reset) @[RISCVPlatform.scala 22:61] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1341 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1343 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1344 = or(_T_1343, reset) @[RISCVPlatform.scala 22:61] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1346 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1348 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:61] + when _T_1348 : @[RISCVPlatform.scala 22:61] + node _T_1351 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1353 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1354 = cvt(_T_1353) @[Parameters.scala 117:49] + node _T_1356 = and(_T_1354, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1357 = asSInt(_T_1356) @[Parameters.scala 117:52] + node _T_1359 = eq(_T_1357, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1360 = and(_T_1351, _T_1359) @[Parameters.scala 132:56] + node _T_1362 = or(UInt<1>("h00"), _T_1360) @[Parameters.scala 134:30] + node _T_1363 = or(_T_1362, reset) @[RISCVPlatform.scala 22:61] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1365 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1366 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1368 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1370 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1371 = or(_T_1370, reset) @[RISCVPlatform.scala 22:61] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1373 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1374 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1376 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1378 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1379 = or(_T_1378, reset) @[RISCVPlatform.scala 22:61] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1381 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1383 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1384 = or(_T_1383, reset) @[RISCVPlatform.scala 22:61] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1386 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 22:61] + when _T_1388 : @[RISCVPlatform.scala 22:61] + node _T_1391 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1393 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + node _T_1403 = or(_T_1402, reset) @[RISCVPlatform.scala 22:61] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1405 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1406 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1408 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1410 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1411 = or(_T_1410, reset) @[RISCVPlatform.scala 22:61] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1413 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1414 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1416 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1418 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1419 = or(_T_1418, reset) @[RISCVPlatform.scala 22:61] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1421 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1424 = or(_T_1423, reset) @[RISCVPlatform.scala 22:61] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1426 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1428 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1428 : @[RISCVPlatform.scala 22:61] + node _T_1429 = or(_T_1291[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1431 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1432 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1434 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1435 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1437 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1439 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1440 = or(_T_1439, reset) @[RISCVPlatform.scala 22:61] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1442 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1444 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + when _T_1444 : @[RISCVPlatform.scala 22:61] + node _T_1445 = or(_T_1291[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1447 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1448 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1450 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1451 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1453 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1455 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1456 = or(_T_1455, reset) @[RISCVPlatform.scala 22:61] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1458 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1460 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:61] + when _T_1460 : @[RISCVPlatform.scala 22:61] + node _T_1461 = or(_T_1291[0], reset) @[RISCVPlatform.scala 22:61] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1463 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1464 = or(_T_1272, reset) @[RISCVPlatform.scala 22:61] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1466 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1467 = or(_T_1280, reset) @[RISCVPlatform.scala 22:61] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1469 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1471 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1472 = or(_T_1471, reset) @[RISCVPlatform.scala 22:61] + node _T_1474 = eq(_T_1472, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1474 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1476 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1477 = or(_T_1476, reset) @[RISCVPlatform.scala 22:61] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1479 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + when io.in[0].d.valid : @[RISCVPlatform.scala 22:61] + node _T_1481 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1482 = or(_T_1481, reset) @[RISCVPlatform.scala 22:61] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1484 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1486 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1487 = not(_T_1486) @[Parameters.scala 37:9] + node _T_1489 = or(_T_1487, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1490 = not(_T_1489) @[Parameters.scala 37:7] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1494 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1496 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1499 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1499 is invalid @[Parameters.scala 228:27] + _T_1499[0] <= _T_1492 @[Parameters.scala 228:27] + _T_1499[1] <= _T_1494 @[Parameters.scala 228:27] + _T_1499[2] <= _T_1496 @[Parameters.scala 228:27] + node _T_1505 = or(_T_1499[0], _T_1499[1]) @[Parameters.scala 229:46] + node _T_1506 = or(_T_1505, _T_1499[2]) @[Parameters.scala 229:46] + node _T_1508 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1509 = dshl(_T_1508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1510 = bits(_T_1509, 5, 0) @[package.scala 19:76] + node _T_1511 = not(_T_1510) @[package.scala 19:40] + node _T_1512 = and(io.in[0].d.bits.addr_lo, _T_1511) @[Edges.scala 17:16] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1516 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + node _T_1518 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:61] + when _T_1518 : @[RISCVPlatform.scala 22:61] + node _T_1519 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1521 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1522 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1524 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1525 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1527 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1529 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1530 = or(_T_1529, reset) @[RISCVPlatform.scala 22:61] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1532 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1534 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1535 = or(_T_1534, reset) @[RISCVPlatform.scala 22:61] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1537 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1539 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1540 = or(_T_1539, reset) @[RISCVPlatform.scala 22:61] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1542 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1544 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:61] + when _T_1544 : @[RISCVPlatform.scala 22:61] + node _T_1545 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1547 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1548 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1550 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1551 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1553 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1555 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1556 = or(_T_1555, reset) @[RISCVPlatform.scala 22:61] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1558 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1560 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1561 = or(_T_1560, reset) @[RISCVPlatform.scala 22:61] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1563 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1565 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:61] + when _T_1565 : @[RISCVPlatform.scala 22:61] + node _T_1566 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1568 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1569 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1571 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1572 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1574 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1576 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:61] + node _T_1577 = or(_T_1576, reset) @[RISCVPlatform.scala 22:61] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1579 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1581 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1582 = or(_T_1581, reset) @[RISCVPlatform.scala 22:61] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1584 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1586 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1586 : @[RISCVPlatform.scala 22:61] + node _T_1587 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1589 = eq(_T_1587, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1589 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1590 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1592 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1593 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1595 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1597 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1598 = or(_T_1597, reset) @[RISCVPlatform.scala 22:61] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1600 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1602 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + when _T_1602 : @[RISCVPlatform.scala 22:61] + node _T_1603 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1605 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1606 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1608 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1609 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1611 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1613 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1614 = or(_T_1613, reset) @[RISCVPlatform.scala 22:61] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1616 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1618 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:61] + when _T_1618 : @[RISCVPlatform.scala 22:61] + node _T_1619 = or(_T_1506, reset) @[RISCVPlatform.scala 22:61] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1621 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1622 = or(_T_1514, reset) @[RISCVPlatform.scala 22:61] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1624 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1625 = or(_T_1516, reset) @[RISCVPlatform.scala 22:61] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1627 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1629 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 22:61] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1632 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1634 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1635 = or(_T_1634, reset) @[RISCVPlatform.scala 22:61] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1637 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + when io.in[0].e.valid : @[RISCVPlatform.scala 22:61] + node _T_1639 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 22:61] + node _T_1640 = or(_T_1639, reset) @[RISCVPlatform.scala 22:61] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1642 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1643 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1646 = dshl(_T_1645, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1647 = bits(_T_1646, 5, 0) @[package.scala 19:76] + node _T_1648 = not(_T_1647) @[package.scala 19:40] + node _T_1649 = shr(_T_1648, 3) @[Edges.scala 198:59] + node _T_1650 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1654 = mux(_T_1652, _T_1649, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1656 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1658 = sub(_T_1656, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1659 = asUInt(_T_1658) @[Edges.scala 208:28] + node _T_1660 = tail(_T_1659, 1) @[Edges.scala 208:28] + node _T_1662 = eq(_T_1656, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1664 = eq(_T_1656, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1666 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1667 = or(_T_1664, _T_1666) @[Edges.scala 210:37] + node _T_1668 = and(_T_1667, _T_1643) @[Edges.scala 211:22] + node _T_1669 = not(_T_1660) @[Edges.scala 212:27] + node _T_1670 = and(_T_1654, _T_1669) @[Edges.scala 212:25] + when _T_1643 : @[Edges.scala 213:17] + node _T_1671 = mux(_T_1662, _T_1654, _T_1660) @[Edges.scala 214:21] + _T_1656 <= _T_1671 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1673 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1675 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1677 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1679 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1681 : UInt, clock @[RISCVPlatform.scala 22:61] + node _T_1683 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1684 = and(io.in[0].a.valid, _T_1683) @[RISCVPlatform.scala 22:61] + when _T_1684 : @[RISCVPlatform.scala 22:61] + node _T_1685 = eq(io.in[0].a.bits.opcode, _T_1673) @[RISCVPlatform.scala 22:61] + node _T_1686 = or(_T_1685, reset) @[RISCVPlatform.scala 22:61] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1688 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1689 = eq(io.in[0].a.bits.param, _T_1675) @[RISCVPlatform.scala 22:61] + node _T_1690 = or(_T_1689, reset) @[RISCVPlatform.scala 22:61] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1692 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1693 = eq(io.in[0].a.bits.size, _T_1677) @[RISCVPlatform.scala 22:61] + node _T_1694 = or(_T_1693, reset) @[RISCVPlatform.scala 22:61] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1696 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1697 = eq(io.in[0].a.bits.source, _T_1679) @[RISCVPlatform.scala 22:61] + node _T_1698 = or(_T_1697, reset) @[RISCVPlatform.scala 22:61] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1700 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1701 = eq(io.in[0].a.bits.address, _T_1681) @[RISCVPlatform.scala 22:61] + node _T_1702 = or(_T_1701, reset) @[RISCVPlatform.scala 22:61] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1704 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1705 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1706 = and(_T_1705, _T_1662) @[RISCVPlatform.scala 22:61] + when _T_1706 : @[RISCVPlatform.scala 22:61] + _T_1673 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 22:61] + _T_1675 <= io.in[0].a.bits.param @[RISCVPlatform.scala 22:61] + _T_1677 <= io.in[0].a.bits.size @[RISCVPlatform.scala 22:61] + _T_1679 <= io.in[0].a.bits.source @[RISCVPlatform.scala 22:61] + _T_1681 <= io.in[0].a.bits.address @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1707 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 5, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1719 = mux(UInt<1>("h00"), _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1721 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1723 = sub(_T_1721, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1724 = asUInt(_T_1723) @[Edges.scala 208:28] + node _T_1725 = tail(_T_1724, 1) @[Edges.scala 208:28] + node _T_1727 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1729 = eq(_T_1721, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1731 = eq(_T_1719, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1732 = or(_T_1729, _T_1731) @[Edges.scala 210:37] + node _T_1733 = and(_T_1732, _T_1707) @[Edges.scala 211:22] + node _T_1734 = not(_T_1725) @[Edges.scala 212:27] + node _T_1735 = and(_T_1719, _T_1734) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1736 = mux(_T_1727, _T_1719, _T_1725) @[Edges.scala 214:21] + _T_1721 <= _T_1736 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1738 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1740 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1742 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1744 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1746 : UInt, clock @[RISCVPlatform.scala 22:61] + node _T_1748 = eq(_T_1727, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1749 = and(io.in[0].b.valid, _T_1748) @[RISCVPlatform.scala 22:61] + when _T_1749 : @[RISCVPlatform.scala 22:61] + node _T_1750 = eq(io.in[0].b.bits.opcode, _T_1738) @[RISCVPlatform.scala 22:61] + node _T_1751 = or(_T_1750, reset) @[RISCVPlatform.scala 22:61] + node _T_1753 = eq(_T_1751, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1753 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1754 = eq(io.in[0].b.bits.param, _T_1740) @[RISCVPlatform.scala 22:61] + node _T_1755 = or(_T_1754, reset) @[RISCVPlatform.scala 22:61] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1757 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1758 = eq(io.in[0].b.bits.size, _T_1742) @[RISCVPlatform.scala 22:61] + node _T_1759 = or(_T_1758, reset) @[RISCVPlatform.scala 22:61] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1761 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1762 = eq(io.in[0].b.bits.source, _T_1744) @[RISCVPlatform.scala 22:61] + node _T_1763 = or(_T_1762, reset) @[RISCVPlatform.scala 22:61] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1765 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1766 = eq(io.in[0].b.bits.address, _T_1746) @[RISCVPlatform.scala 22:61] + node _T_1767 = or(_T_1766, reset) @[RISCVPlatform.scala 22:61] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1769 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1770 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1771 = and(_T_1770, _T_1727) @[RISCVPlatform.scala 22:61] + when _T_1771 : @[RISCVPlatform.scala 22:61] + _T_1738 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 22:61] + _T_1740 <= io.in[0].b.bits.param @[RISCVPlatform.scala 22:61] + _T_1742 <= io.in[0].b.bits.size @[RISCVPlatform.scala 22:61] + _T_1744 <= io.in[0].b.bits.source @[RISCVPlatform.scala 22:61] + _T_1746 <= io.in[0].b.bits.address @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1774 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1775 = dshl(_T_1774, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1776 = bits(_T_1775, 5, 0) @[package.scala 19:76] + node _T_1777 = not(_T_1776) @[package.scala 19:40] + node _T_1778 = shr(_T_1777, 3) @[Edges.scala 198:59] + node _T_1779 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1781 = mux(_T_1779, _T_1778, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1783 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1785 = sub(_T_1783, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1786 = asUInt(_T_1785) @[Edges.scala 208:28] + node _T_1787 = tail(_T_1786, 1) @[Edges.scala 208:28] + node _T_1789 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1791 = eq(_T_1783, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1793 = eq(_T_1781, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1794 = or(_T_1791, _T_1793) @[Edges.scala 210:37] + node _T_1795 = and(_T_1794, _T_1772) @[Edges.scala 211:22] + node _T_1796 = not(_T_1787) @[Edges.scala 212:27] + node _T_1797 = and(_T_1781, _T_1796) @[Edges.scala 212:25] + when _T_1772 : @[Edges.scala 213:17] + node _T_1798 = mux(_T_1789, _T_1781, _T_1787) @[Edges.scala 214:21] + _T_1783 <= _T_1798 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1800 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1802 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1804 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1806 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1808 : UInt, clock @[RISCVPlatform.scala 22:61] + node _T_1810 = eq(_T_1789, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1811 = and(io.in[0].c.valid, _T_1810) @[RISCVPlatform.scala 22:61] + when _T_1811 : @[RISCVPlatform.scala 22:61] + node _T_1812 = eq(io.in[0].c.bits.opcode, _T_1800) @[RISCVPlatform.scala 22:61] + node _T_1813 = or(_T_1812, reset) @[RISCVPlatform.scala 22:61] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1815 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1816 = eq(io.in[0].c.bits.param, _T_1802) @[RISCVPlatform.scala 22:61] + node _T_1817 = or(_T_1816, reset) @[RISCVPlatform.scala 22:61] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1819 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1820 = eq(io.in[0].c.bits.size, _T_1804) @[RISCVPlatform.scala 22:61] + node _T_1821 = or(_T_1820, reset) @[RISCVPlatform.scala 22:61] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1823 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1824 = eq(io.in[0].c.bits.source, _T_1806) @[RISCVPlatform.scala 22:61] + node _T_1825 = or(_T_1824, reset) @[RISCVPlatform.scala 22:61] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1827 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1828 = eq(io.in[0].c.bits.address, _T_1808) @[RISCVPlatform.scala 22:61] + node _T_1829 = or(_T_1828, reset) @[RISCVPlatform.scala 22:61] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1831 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1832 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1833 = and(_T_1832, _T_1789) @[RISCVPlatform.scala 22:61] + when _T_1833 : @[RISCVPlatform.scala 22:61] + _T_1800 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 22:61] + _T_1802 <= io.in[0].c.bits.param @[RISCVPlatform.scala 22:61] + _T_1804 <= io.in[0].c.bits.size @[RISCVPlatform.scala 22:61] + _T_1806 <= io.in[0].c.bits.source @[RISCVPlatform.scala 22:61] + _T_1808 <= io.in[0].c.bits.address @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1834 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 3) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1843 = mux(_T_1841, _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1845 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1847 = sub(_T_1845, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1848 = asUInt(_T_1847) @[Edges.scala 208:28] + node _T_1849 = tail(_T_1848, 1) @[Edges.scala 208:28] + node _T_1851 = eq(_T_1845, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1853 = eq(_T_1845, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1855 = eq(_T_1843, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1856 = or(_T_1853, _T_1855) @[Edges.scala 210:37] + node _T_1857 = and(_T_1856, _T_1834) @[Edges.scala 211:22] + node _T_1858 = not(_T_1849) @[Edges.scala 212:27] + node _T_1859 = and(_T_1843, _T_1858) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1860 = mux(_T_1851, _T_1843, _T_1849) @[Edges.scala 214:21] + _T_1845 <= _T_1860 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1862 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1864 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1866 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1868 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1870 : UInt, clock @[RISCVPlatform.scala 22:61] + reg _T_1872 : UInt, clock @[RISCVPlatform.scala 22:61] + node _T_1874 = eq(_T_1851, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1875 = and(io.in[0].d.valid, _T_1874) @[RISCVPlatform.scala 22:61] + when _T_1875 : @[RISCVPlatform.scala 22:61] + node _T_1876 = eq(io.in[0].d.bits.opcode, _T_1862) @[RISCVPlatform.scala 22:61] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 22:61] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1879 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1880 = eq(io.in[0].d.bits.param, _T_1864) @[RISCVPlatform.scala 22:61] + node _T_1881 = or(_T_1880, reset) @[RISCVPlatform.scala 22:61] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1883 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1884 = eq(io.in[0].d.bits.size, _T_1866) @[RISCVPlatform.scala 22:61] + node _T_1885 = or(_T_1884, reset) @[RISCVPlatform.scala 22:61] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1887 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1888 = eq(io.in[0].d.bits.source, _T_1868) @[RISCVPlatform.scala 22:61] + node _T_1889 = or(_T_1888, reset) @[RISCVPlatform.scala 22:61] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1891 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1892 = eq(io.in[0].d.bits.sink, _T_1870) @[RISCVPlatform.scala 22:61] + node _T_1893 = or(_T_1892, reset) @[RISCVPlatform.scala 22:61] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1895 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1896 = eq(io.in[0].d.bits.addr_lo, _T_1872) @[RISCVPlatform.scala 22:61] + node _T_1897 = or(_T_1896, reset) @[RISCVPlatform.scala 22:61] + node _T_1899 = eq(_T_1897, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1899 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1900 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = and(_T_1900, _T_1851) @[RISCVPlatform.scala 22:61] + when _T_1901 : @[RISCVPlatform.scala 22:61] + _T_1862 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 22:61] + _T_1864 <= io.in[0].d.bits.param @[RISCVPlatform.scala 22:61] + _T_1866 <= io.in[0].d.bits.size @[RISCVPlatform.scala 22:61] + _T_1868 <= io.in[0].d.bits.source @[RISCVPlatform.scala 22:61] + _T_1870 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 22:61] + _T_1872 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + reg _T_1903 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1904 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1906 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1907 = dshl(_T_1906, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1908 = bits(_T_1907, 5, 0) @[package.scala 19:76] + node _T_1909 = not(_T_1908) @[package.scala 19:40] + node _T_1910 = shr(_T_1909, 3) @[Edges.scala 198:59] + node _T_1911 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1915 = mux(_T_1913, _T_1910, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1917 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1919 = sub(_T_1917, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1920 = asUInt(_T_1919) @[Edges.scala 208:28] + node _T_1921 = tail(_T_1920, 1) @[Edges.scala 208:28] + node _T_1923 = eq(_T_1917, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1925 = eq(_T_1917, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1927 = eq(_T_1915, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1928 = or(_T_1925, _T_1927) @[Edges.scala 210:37] + node _T_1929 = and(_T_1928, _T_1904) @[Edges.scala 211:22] + node _T_1930 = not(_T_1921) @[Edges.scala 212:27] + node _T_1931 = and(_T_1915, _T_1930) @[Edges.scala 212:25] + when _T_1904 : @[Edges.scala 213:17] + node _T_1932 = mux(_T_1923, _T_1915, _T_1921) @[Edges.scala 214:21] + _T_1917 <= _T_1932 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1933 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1935 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1936 = dshl(_T_1935, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1937 = bits(_T_1936, 5, 0) @[package.scala 19:76] + node _T_1938 = not(_T_1937) @[package.scala 19:40] + node _T_1939 = shr(_T_1938, 3) @[Edges.scala 198:59] + node _T_1940 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1942 = mux(_T_1940, _T_1939, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1944 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1946 = sub(_T_1944, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1947 = asUInt(_T_1946) @[Edges.scala 208:28] + node _T_1948 = tail(_T_1947, 1) @[Edges.scala 208:28] + node _T_1950 = eq(_T_1944, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1952 = eq(_T_1944, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1954 = eq(_T_1942, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1955 = or(_T_1952, _T_1954) @[Edges.scala 210:37] + node _T_1956 = and(_T_1955, _T_1933) @[Edges.scala 211:22] + node _T_1957 = not(_T_1948) @[Edges.scala 212:27] + node _T_1958 = and(_T_1942, _T_1957) @[Edges.scala 212:25] + when _T_1933 : @[Edges.scala 213:17] + node _T_1959 = mux(_T_1950, _T_1942, _T_1948) @[Edges.scala 214:21] + _T_1944 <= _T_1959 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1961 : UInt<6> + _T_1961 is invalid + _T_1961 <= UInt<6>("h00") + node _T_1962 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1962 : @[RISCVPlatform.scala 22:61] + when _T_1928 : @[RISCVPlatform.scala 22:61] + node _T_1964 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1961 <= _T_1964 @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1965 = dshr(_T_1903, io.in[0].a.bits.source) @[RISCVPlatform.scala 22:61] + node _T_1966 = bits(_T_1965, 0, 0) @[RISCVPlatform.scala 22:61] + node _T_1968 = eq(_T_1966, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + node _T_1969 = or(_T_1968, reset) @[RISCVPlatform.scala 22:61] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1971 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + wire _T_1973 : UInt<6> + _T_1973 is invalid + _T_1973 <= UInt<6>("h00") + node _T_1974 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1976 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:61] + node _T_1977 = and(_T_1974, _T_1976) @[RISCVPlatform.scala 22:61] + when _T_1977 : @[RISCVPlatform.scala 22:61] + when _T_1955 : @[RISCVPlatform.scala 22:61] + node _T_1979 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1973 <= _T_1979 @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1980 = or(_T_1961, _T_1903) @[RISCVPlatform.scala 22:61] + node _T_1981 = dshr(_T_1980, io.in[0].d.bits.source) @[RISCVPlatform.scala 22:61] + node _T_1982 = bits(_T_1981, 0, 0) @[RISCVPlatform.scala 22:61] + node _T_1983 = or(_T_1982, reset) @[RISCVPlatform.scala 22:61] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[RISCVPlatform.scala 22:61] + when _T_1985 : @[RISCVPlatform.scala 22:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:22:61)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 22:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + skip @[RISCVPlatform.scala 22:61] + node _T_1986 = or(_T_1903, _T_1961) @[RISCVPlatform.scala 22:61] + node _T_1987 = not(_T_1973) @[RISCVPlatform.scala 22:61] + node _T_1988 = and(_T_1986, _T_1987) @[RISCVPlatform.scala 22:61] + _T_1903 <= _T_1988 @[RISCVPlatform.scala 22:61] + + module TLMonitor_28 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 22:14] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 22:14] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_608 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = xor(UInt<6>("h028"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_619 = not(_T_618) @[Parameters.scala 37:9] + node _T_621 = or(_T_619, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_622 = not(_T_621) @[Parameters.scala 37:7] + node _T_624 = eq(_T_622, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_626 = xor(UInt<6>("h020"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_627 = not(_T_626) @[Parameters.scala 37:9] + node _T_629 = or(_T_627, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_630 = not(_T_629) @[Parameters.scala 37:7] + node _T_632 = eq(_T_630, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_635 : UInt<1>[3] @[Parameters.scala 228:27] + _T_635 is invalid @[Parameters.scala 228:27] + _T_635[0] <= _T_616 @[Parameters.scala 228:27] + _T_635[1] <= _T_624 @[Parameters.scala 228:27] + _T_635[2] <= _T_632 @[Parameters.scala 228:27] + node _T_641 = or(_T_635[0], _T_635[1]) @[Parameters.scala 229:46] + node _T_642 = or(_T_641, _T_635[2]) @[Parameters.scala 229:46] + node _T_644 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_645 = dshl(_T_644, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_646 = bits(_T_645, 5, 0) @[package.scala 19:76] + node _T_647 = not(_T_646) @[package.scala 19:40] + node _T_648 = and(io.in[0].a.bits.address, _T_647) @[Edges.scala 17:16] + node _T_650 = eq(_T_648, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_652 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_653 = dshl(UInt<1>("h01"), _T_652) @[OneHot.scala 49:12] + node _T_654 = bits(_T_653, 2, 0) @[OneHot.scala 49:37] + node _T_656 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_658 = bits(_T_654, 2, 2) @[package.scala 44:26] + node _T_659 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_661 = eq(_T_659, UInt<1>("h00")) @[package.scala 46:20] + node _T_662 = and(UInt<1>("h01"), _T_661) @[package.scala 49:27] + node _T_663 = and(_T_658, _T_662) @[package.scala 50:38] + node _T_664 = or(_T_656, _T_663) @[package.scala 50:29] + node _T_665 = and(UInt<1>("h01"), _T_659) @[package.scala 49:27] + node _T_666 = and(_T_658, _T_665) @[package.scala 50:38] + node _T_667 = or(_T_656, _T_666) @[package.scala 50:29] + node _T_668 = bits(_T_654, 1, 1) @[package.scala 44:26] + node _T_669 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_671 = eq(_T_669, UInt<1>("h00")) @[package.scala 46:20] + node _T_672 = and(_T_662, _T_671) @[package.scala 49:27] + node _T_673 = and(_T_668, _T_672) @[package.scala 50:38] + node _T_674 = or(_T_664, _T_673) @[package.scala 50:29] + node _T_675 = and(_T_662, _T_669) @[package.scala 49:27] + node _T_676 = and(_T_668, _T_675) @[package.scala 50:38] + node _T_677 = or(_T_664, _T_676) @[package.scala 50:29] + node _T_678 = and(_T_665, _T_671) @[package.scala 49:27] + node _T_679 = and(_T_668, _T_678) @[package.scala 50:38] + node _T_680 = or(_T_667, _T_679) @[package.scala 50:29] + node _T_681 = and(_T_665, _T_669) @[package.scala 49:27] + node _T_682 = and(_T_668, _T_681) @[package.scala 50:38] + node _T_683 = or(_T_667, _T_682) @[package.scala 50:29] + node _T_684 = bits(_T_654, 0, 0) @[package.scala 44:26] + node _T_685 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_687 = eq(_T_685, UInt<1>("h00")) @[package.scala 46:20] + node _T_688 = and(_T_672, _T_687) @[package.scala 49:27] + node _T_689 = and(_T_684, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_674, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_672, _T_685) @[package.scala 49:27] + node _T_692 = and(_T_684, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_674, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_675, _T_687) @[package.scala 49:27] + node _T_695 = and(_T_684, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_677, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_675, _T_685) @[package.scala 49:27] + node _T_698 = and(_T_684, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_677, _T_698) @[package.scala 50:29] + node _T_700 = and(_T_678, _T_687) @[package.scala 49:27] + node _T_701 = and(_T_684, _T_700) @[package.scala 50:38] + node _T_702 = or(_T_680, _T_701) @[package.scala 50:29] + node _T_703 = and(_T_678, _T_685) @[package.scala 49:27] + node _T_704 = and(_T_684, _T_703) @[package.scala 50:38] + node _T_705 = or(_T_680, _T_704) @[package.scala 50:29] + node _T_706 = and(_T_681, _T_687) @[package.scala 49:27] + node _T_707 = and(_T_684, _T_706) @[package.scala 50:38] + node _T_708 = or(_T_683, _T_707) @[package.scala 50:29] + node _T_709 = and(_T_681, _T_685) @[package.scala 49:27] + node _T_710 = and(_T_684, _T_709) @[package.scala 50:38] + node _T_711 = or(_T_683, _T_710) @[package.scala 50:29] + node _T_712 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_713 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_714 = cat(_T_713, _T_712) @[Cat.scala 30:58] + node _T_715 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_716 = cat(_T_711, _T_708) @[Cat.scala 30:58] + node _T_717 = cat(_T_716, _T_715) @[Cat.scala 30:58] + node _T_718 = cat(_T_717, _T_714) @[Cat.scala 30:58] + node _T_720 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:14] + when _T_720 : @[RISCVPlatform.scala 22:14] + node _T_723 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_725 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_726 = cvt(_T_725) @[Parameters.scala 117:49] + node _T_728 = and(_T_726, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_729 = asSInt(_T_728) @[Parameters.scala 117:52] + node _T_731 = eq(_T_729, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_732 = and(_T_723, _T_731) @[Parameters.scala 132:56] + node _T_734 = or(UInt<1>("h00"), _T_732) @[Parameters.scala 134:30] + node _T_735 = or(_T_734, reset) @[RISCVPlatform.scala 22:14] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_737 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_738 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_740 = eq(_T_738, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_740 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_742 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_743 = or(_T_742, reset) @[RISCVPlatform.scala 22:14] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_745 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_746 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_748 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_750 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_751 = or(_T_750, reset) @[RISCVPlatform.scala 22:14] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_753 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_754 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 22:14] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_757 = or(_T_756, reset) @[RISCVPlatform.scala 22:14] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_759 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_761 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:14] + when _T_761 : @[RISCVPlatform.scala 22:14] + node _T_764 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_766 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_767 = and(_T_764, _T_766) @[Parameters.scala 63:37] + node _T_768 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 132:31] + node _T_770 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_771 = cvt(_T_770) @[Parameters.scala 117:49] + node _T_773 = and(_T_771, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_774 = asSInt(_T_773) @[Parameters.scala 117:52] + node _T_776 = eq(_T_774, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_777 = and(_T_768, _T_776) @[Parameters.scala 132:56] + node _T_779 = or(UInt<1>("h00"), _T_777) @[Parameters.scala 134:30] + node _T_780 = or(_T_779, reset) @[RISCVPlatform.scala 22:14] + node _T_782 = eq(_T_780, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_782 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_783 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_785 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_786 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_788 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_790 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_791 = or(_T_790, reset) @[RISCVPlatform.scala 22:14] + node _T_793 = eq(_T_791, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_793 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_794 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 22:14] + node _T_795 = or(_T_794, reset) @[RISCVPlatform.scala 22:14] + node _T_797 = eq(_T_795, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_797 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_799 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_799 : @[RISCVPlatform.scala 22:14] + node _T_802 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_804 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_805 = and(_T_802, _T_804) @[Parameters.scala 63:37] + node _T_806 = or(UInt<1>("h00"), _T_805) @[Parameters.scala 132:31] + node _T_808 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_809 = cvt(_T_808) @[Parameters.scala 117:49] + node _T_811 = and(_T_809, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_812 = asSInt(_T_811) @[Parameters.scala 117:52] + node _T_814 = eq(_T_812, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_815 = and(_T_806, _T_814) @[Parameters.scala 132:56] + node _T_817 = or(UInt<1>("h00"), _T_815) @[Parameters.scala 134:30] + node _T_818 = or(_T_817, reset) @[RISCVPlatform.scala 22:14] + node _T_820 = eq(_T_818, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_820 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_821 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_823 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_824 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_826 = eq(_T_824, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_826 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_828 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_829 = or(_T_828, reset) @[RISCVPlatform.scala 22:14] + node _T_831 = eq(_T_829, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_831 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_832 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 22:14] + node _T_833 = or(_T_832, reset) @[RISCVPlatform.scala 22:14] + node _T_835 = eq(_T_833, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_835 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_837 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + when _T_837 : @[RISCVPlatform.scala 22:14] + node _T_840 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_842 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_843 = and(_T_840, _T_842) @[Parameters.scala 63:37] + node _T_844 = or(UInt<1>("h00"), _T_843) @[Parameters.scala 132:31] + node _T_846 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_847 = cvt(_T_846) @[Parameters.scala 117:49] + node _T_849 = and(_T_847, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_850 = asSInt(_T_849) @[Parameters.scala 117:52] + node _T_852 = eq(_T_850, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_853 = and(_T_844, _T_852) @[Parameters.scala 132:56] + node _T_855 = or(UInt<1>("h00"), _T_853) @[Parameters.scala 134:30] + node _T_856 = or(_T_855, reset) @[RISCVPlatform.scala 22:14] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_858 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_859 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_861 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_862 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_864 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_866 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_867 = or(_T_866, reset) @[RISCVPlatform.scala 22:14] + node _T_869 = eq(_T_867, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_869 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_870 = not(_T_718) @[RISCVPlatform.scala 22:14] + node _T_871 = and(io.in[0].a.bits.mask, _T_870) @[RISCVPlatform.scala 22:14] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_874 = or(_T_873, reset) @[RISCVPlatform.scala 22:14] + node _T_876 = eq(_T_874, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_876 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_878 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:14] + when _T_878 : @[RISCVPlatform.scala 22:14] + node _T_881 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_883 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_884 = cvt(_T_883) @[Parameters.scala 117:49] + node _T_886 = and(_T_884, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_887 = asSInt(_T_886) @[Parameters.scala 117:52] + node _T_889 = eq(_T_887, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_890 = and(_T_881, _T_889) @[Parameters.scala 132:56] + node _T_892 = or(UInt<1>("h00"), _T_890) @[Parameters.scala 134:30] + node _T_893 = or(_T_892, reset) @[RISCVPlatform.scala 22:14] + node _T_895 = eq(_T_893, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_895 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_896 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_898 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_899 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_901 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_903 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_904 = or(_T_903, reset) @[RISCVPlatform.scala 22:14] + node _T_906 = eq(_T_904, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_906 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_907 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 22:14] + node _T_908 = or(_T_907, reset) @[RISCVPlatform.scala 22:14] + node _T_910 = eq(_T_908, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_910 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_912 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + when _T_912 : @[RISCVPlatform.scala 22:14] + node _T_915 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_917 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_918 = cvt(_T_917) @[Parameters.scala 117:49] + node _T_920 = and(_T_918, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_921 = asSInt(_T_920) @[Parameters.scala 117:52] + node _T_923 = eq(_T_921, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_924 = and(_T_915, _T_923) @[Parameters.scala 132:56] + node _T_926 = or(UInt<1>("h00"), _T_924) @[Parameters.scala 134:30] + node _T_927 = or(_T_926, reset) @[RISCVPlatform.scala 22:14] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_929 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_930 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_932 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_933 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_935 = eq(_T_933, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_935 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_937 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_938 = or(_T_937, reset) @[RISCVPlatform.scala 22:14] + node _T_940 = eq(_T_938, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_940 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_941 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 22:14] + node _T_942 = or(_T_941, reset) @[RISCVPlatform.scala 22:14] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_944 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_946 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:14] + when _T_946 : @[RISCVPlatform.scala 22:14] + node _T_949 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_951 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_958 = and(_T_949, _T_957) @[Parameters.scala 132:56] + node _T_960 = or(UInt<1>("h00"), _T_958) @[Parameters.scala 134:30] + node _T_961 = or(_T_960, reset) @[RISCVPlatform.scala 22:14] + node _T_963 = eq(_T_961, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_963 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_964 = or(_T_642, reset) @[RISCVPlatform.scala 22:14] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_966 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_967 = or(_T_650, reset) @[RISCVPlatform.scala 22:14] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_969 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_970 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 22:14] + node _T_971 = or(_T_970, reset) @[RISCVPlatform.scala 22:14] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_973 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + when io.in[0].b.valid : @[RISCVPlatform.scala 22:14] + node _T_975 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_976 = or(_T_975, reset) @[RISCVPlatform.scala 22:14] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_978 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_980 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_981 = cvt(_T_980) @[Parameters.scala 117:49] + node _T_983 = and(_T_981, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_984 = asSInt(_T_983) @[Parameters.scala 117:52] + node _T_986 = eq(_T_984, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_989 : UInt<1>[1] @[Parameters.scala 110:36] + _T_989 is invalid @[Parameters.scala 110:36] + _T_989[0] <= _T_986 @[Parameters.scala 110:36] + node _T_994 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_995 = dshl(_T_994, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_996 = bits(_T_995, 5, 0) @[package.scala 19:76] + node _T_997 = not(_T_996) @[package.scala 19:40] + node _T_998 = and(io.in[0].b.bits.address, _T_997) @[Edges.scala 17:16] + node _T_1000 = eq(_T_998, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1002 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1003 = dshl(UInt<1>("h01"), _T_1002) @[OneHot.scala 49:12] + node _T_1004 = bits(_T_1003, 2, 0) @[OneHot.scala 49:37] + node _T_1006 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1008 = bits(_T_1004, 2, 2) @[package.scala 44:26] + node _T_1009 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1011 = eq(_T_1009, UInt<1>("h00")) @[package.scala 46:20] + node _T_1012 = and(UInt<1>("h01"), _T_1011) @[package.scala 49:27] + node _T_1013 = and(_T_1008, _T_1012) @[package.scala 50:38] + node _T_1014 = or(_T_1006, _T_1013) @[package.scala 50:29] + node _T_1015 = and(UInt<1>("h01"), _T_1009) @[package.scala 49:27] + node _T_1016 = and(_T_1008, _T_1015) @[package.scala 50:38] + node _T_1017 = or(_T_1006, _T_1016) @[package.scala 50:29] + node _T_1018 = bits(_T_1004, 1, 1) @[package.scala 44:26] + node _T_1019 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1021 = eq(_T_1019, UInt<1>("h00")) @[package.scala 46:20] + node _T_1022 = and(_T_1012, _T_1021) @[package.scala 49:27] + node _T_1023 = and(_T_1018, _T_1022) @[package.scala 50:38] + node _T_1024 = or(_T_1014, _T_1023) @[package.scala 50:29] + node _T_1025 = and(_T_1012, _T_1019) @[package.scala 49:27] + node _T_1026 = and(_T_1018, _T_1025) @[package.scala 50:38] + node _T_1027 = or(_T_1014, _T_1026) @[package.scala 50:29] + node _T_1028 = and(_T_1015, _T_1021) @[package.scala 49:27] + node _T_1029 = and(_T_1018, _T_1028) @[package.scala 50:38] + node _T_1030 = or(_T_1017, _T_1029) @[package.scala 50:29] + node _T_1031 = and(_T_1015, _T_1019) @[package.scala 49:27] + node _T_1032 = and(_T_1018, _T_1031) @[package.scala 50:38] + node _T_1033 = or(_T_1017, _T_1032) @[package.scala 50:29] + node _T_1034 = bits(_T_1004, 0, 0) @[package.scala 44:26] + node _T_1035 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1037 = eq(_T_1035, UInt<1>("h00")) @[package.scala 46:20] + node _T_1038 = and(_T_1022, _T_1037) @[package.scala 49:27] + node _T_1039 = and(_T_1034, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1024, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1022, _T_1035) @[package.scala 49:27] + node _T_1042 = and(_T_1034, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1024, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1025, _T_1037) @[package.scala 49:27] + node _T_1045 = and(_T_1034, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1027, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1025, _T_1035) @[package.scala 49:27] + node _T_1048 = and(_T_1034, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1027, _T_1048) @[package.scala 50:29] + node _T_1050 = and(_T_1028, _T_1037) @[package.scala 49:27] + node _T_1051 = and(_T_1034, _T_1050) @[package.scala 50:38] + node _T_1052 = or(_T_1030, _T_1051) @[package.scala 50:29] + node _T_1053 = and(_T_1028, _T_1035) @[package.scala 49:27] + node _T_1054 = and(_T_1034, _T_1053) @[package.scala 50:38] + node _T_1055 = or(_T_1030, _T_1054) @[package.scala 50:29] + node _T_1056 = and(_T_1031, _T_1037) @[package.scala 49:27] + node _T_1057 = and(_T_1034, _T_1056) @[package.scala 50:38] + node _T_1058 = or(_T_1033, _T_1057) @[package.scala 50:29] + node _T_1059 = and(_T_1031, _T_1035) @[package.scala 49:27] + node _T_1060 = and(_T_1034, _T_1059) @[package.scala 50:38] + node _T_1061 = or(_T_1033, _T_1060) @[package.scala 50:29] + node _T_1062 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1063 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1064 = cat(_T_1063, _T_1062) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1066 = cat(_T_1061, _T_1058) @[Cat.scala 30:58] + node _T_1067 = cat(_T_1066, _T_1065) @[Cat.scala 30:58] + node _T_1068 = cat(_T_1067, _T_1064) @[Cat.scala 30:58] + node _T_1070 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:14] + when _T_1070 : @[RISCVPlatform.scala 22:14] + node _T_1072 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1073 = not(_T_1072) @[Parameters.scala 37:9] + node _T_1075 = or(_T_1073, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1076 = not(_T_1075) @[Parameters.scala 37:7] + node _T_1078 = eq(_T_1076, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1080 = xor(UInt<6>("h028"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1081 = not(_T_1080) @[Parameters.scala 37:9] + node _T_1083 = or(_T_1081, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1084 = not(_T_1083) @[Parameters.scala 37:7] + node _T_1086 = eq(_T_1084, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1088 = xor(UInt<6>("h020"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1089 = not(_T_1088) @[Parameters.scala 37:9] + node _T_1091 = or(_T_1089, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1092 = not(_T_1091) @[Parameters.scala 37:7] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1097 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1097 is invalid @[Parameters.scala 228:27] + _T_1097[0] <= _T_1078 @[Parameters.scala 228:27] + _T_1097[1] <= _T_1086 @[Parameters.scala 228:27] + _T_1097[2] <= _T_1094 @[Parameters.scala 228:27] + node _T_1105 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1107 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1108 = and(_T_1105, _T_1107) @[Parameters.scala 63:37] + node _T_1111 = mux(_T_1097[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1113 = mux(_T_1097[1], _T_1108, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1115 = mux(_T_1097[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1117 = or(_T_1111, _T_1113) @[Mux.scala 19:72] + node _T_1118 = or(_T_1117, _T_1115) @[Mux.scala 19:72] + wire _T_1120 : UInt<1> @[Mux.scala 19:72] + _T_1120 is invalid @[Mux.scala 19:72] + _T_1120 <= _T_1118 @[Mux.scala 19:72] + node _T_1121 = or(_T_1120, reset) @[RISCVPlatform.scala 22:14] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1123 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1124 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1126 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1128 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1129 = or(_T_1128, reset) @[RISCVPlatform.scala 22:14] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1131 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1132 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1134 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1136 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1137 = or(_T_1136, reset) @[RISCVPlatform.scala 22:14] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1139 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1140 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 22:14] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1143 = or(_T_1142, reset) @[RISCVPlatform.scala 22:14] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1145 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:14] + when _T_1147 : @[RISCVPlatform.scala 22:14] + node _T_1149 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1151 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1152 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1154 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1155 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1157 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1159 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1160 = or(_T_1159, reset) @[RISCVPlatform.scala 22:14] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1162 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1163 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 22:14] + node _T_1164 = or(_T_1163, reset) @[RISCVPlatform.scala 22:14] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1166 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1168 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1168 : @[RISCVPlatform.scala 22:14] + node _T_1170 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1172 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1173 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1175 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1176 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1178 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1180 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1181 = or(_T_1180, reset) @[RISCVPlatform.scala 22:14] + node _T_1183 = eq(_T_1181, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1183 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1184 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 22:14] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 22:14] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1187 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + when _T_1189 : @[RISCVPlatform.scala 22:14] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1193 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1194 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1196 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1197 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1199 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1201 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 22:14] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1204 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1205 = not(_T_1068) @[RISCVPlatform.scala 22:14] + node _T_1206 = and(io.in[0].b.bits.mask, _T_1205) @[RISCVPlatform.scala 22:14] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1209 = or(_T_1208, reset) @[RISCVPlatform.scala 22:14] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1211 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1213 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:14] + when _T_1213 : @[RISCVPlatform.scala 22:14] + node _T_1215 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1217 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1218 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1220 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1221 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1223 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1225 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1226 = or(_T_1225, reset) @[RISCVPlatform.scala 22:14] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1228 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1229 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 22:14] + node _T_1230 = or(_T_1229, reset) @[RISCVPlatform.scala 22:14] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1232 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1234 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + when _T_1234 : @[RISCVPlatform.scala 22:14] + node _T_1236 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1238 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1239 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1241 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1242 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1244 = eq(_T_1242, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1244 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1246 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1247 = or(_T_1246, reset) @[RISCVPlatform.scala 22:14] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1249 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1250 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 22:14] + node _T_1251 = or(_T_1250, reset) @[RISCVPlatform.scala 22:14] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1253 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1255 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:14] + when _T_1255 : @[RISCVPlatform.scala 22:14] + node _T_1257 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 22:14] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1259 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1260 = or(_T_989[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1262 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1263 = or(_T_1000, reset) @[RISCVPlatform.scala 22:14] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1265 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1266 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 22:14] + node _T_1267 = or(_T_1266, reset) @[RISCVPlatform.scala 22:14] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1269 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + when io.in[0].c.valid : @[RISCVPlatform.scala 22:14] + node _T_1271 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1272 = or(_T_1271, reset) @[RISCVPlatform.scala 22:14] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1274 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1276 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1277 = not(_T_1276) @[Parameters.scala 37:9] + node _T_1279 = or(_T_1277, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1280 = not(_T_1279) @[Parameters.scala 37:7] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1284 = xor(UInt<6>("h028"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1285 = not(_T_1284) @[Parameters.scala 37:9] + node _T_1287 = or(_T_1285, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1288 = not(_T_1287) @[Parameters.scala 37:7] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1292 = xor(UInt<6>("h020"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1293 = not(_T_1292) @[Parameters.scala 37:9] + node _T_1295 = or(_T_1293, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1296 = not(_T_1295) @[Parameters.scala 37:7] + node _T_1298 = eq(_T_1296, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1301 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1301 is invalid @[Parameters.scala 228:27] + _T_1301[0] <= _T_1282 @[Parameters.scala 228:27] + _T_1301[1] <= _T_1290 @[Parameters.scala 228:27] + _T_1301[2] <= _T_1298 @[Parameters.scala 228:27] + node _T_1307 = or(_T_1301[0], _T_1301[1]) @[Parameters.scala 229:46] + node _T_1308 = or(_T_1307, _T_1301[2]) @[Parameters.scala 229:46] + node _T_1310 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1311 = dshl(_T_1310, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1312 = bits(_T_1311, 5, 0) @[package.scala 19:76] + node _T_1313 = not(_T_1312) @[package.scala 19:40] + node _T_1314 = and(io.in[0].c.bits.address, _T_1313) @[Edges.scala 17:16] + node _T_1316 = eq(_T_1314, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1318 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1319 = cvt(_T_1318) @[Parameters.scala 117:49] + node _T_1321 = and(_T_1319, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1322 = asSInt(_T_1321) @[Parameters.scala 117:52] + node _T_1324 = eq(_T_1322, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1327 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1327 is invalid @[Parameters.scala 110:36] + _T_1327[0] <= _T_1324 @[Parameters.scala 110:36] + node _T_1332 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:14] + when _T_1332 : @[RISCVPlatform.scala 22:14] + node _T_1333 = or(_T_1327[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1335 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1336 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1338 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1340 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1341 = or(_T_1340, reset) @[RISCVPlatform.scala 22:14] + node _T_1343 = eq(_T_1341, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1343 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1344 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1346 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1348 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1349 = or(_T_1348, reset) @[RISCVPlatform.scala 22:14] + node _T_1351 = eq(_T_1349, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1351 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1353 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1354 = or(_T_1353, reset) @[RISCVPlatform.scala 22:14] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1356 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1358 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:14] + when _T_1358 : @[RISCVPlatform.scala 22:14] + node _T_1359 = or(_T_1327[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1361 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1362 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1364 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1366 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1367 = or(_T_1366, reset) @[RISCVPlatform.scala 22:14] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1369 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1370 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1372 = eq(_T_1370, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1372 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1374 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1375 = or(_T_1374, reset) @[RISCVPlatform.scala 22:14] + node _T_1377 = eq(_T_1375, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1377 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1379 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1380 = or(_T_1379, reset) @[RISCVPlatform.scala 22:14] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1382 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1384 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:14] + when _T_1384 : @[RISCVPlatform.scala 22:14] + node _T_1387 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1389 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1390 = cvt(_T_1389) @[Parameters.scala 117:49] + node _T_1392 = and(_T_1390, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1393 = asSInt(_T_1392) @[Parameters.scala 117:52] + node _T_1395 = eq(_T_1393, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1396 = and(_T_1387, _T_1395) @[Parameters.scala 132:56] + node _T_1398 = or(UInt<1>("h00"), _T_1396) @[Parameters.scala 134:30] + node _T_1399 = or(_T_1398, reset) @[RISCVPlatform.scala 22:14] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1401 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1402 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1404 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1406 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1407 = or(_T_1406, reset) @[RISCVPlatform.scala 22:14] + node _T_1409 = eq(_T_1407, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1409 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1410 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1412 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1414 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1415 = or(_T_1414, reset) @[RISCVPlatform.scala 22:14] + node _T_1417 = eq(_T_1415, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1417 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1419 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1420 = or(_T_1419, reset) @[RISCVPlatform.scala 22:14] + node _T_1422 = eq(_T_1420, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1422 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1424 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 22:14] + when _T_1424 : @[RISCVPlatform.scala 22:14] + node _T_1427 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1429 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1430 = cvt(_T_1429) @[Parameters.scala 117:49] + node _T_1432 = and(_T_1430, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1433 = asSInt(_T_1432) @[Parameters.scala 117:52] + node _T_1435 = eq(_T_1433, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1436 = and(_T_1427, _T_1435) @[Parameters.scala 132:56] + node _T_1438 = or(UInt<1>("h00"), _T_1436) @[Parameters.scala 134:30] + node _T_1439 = or(_T_1438, reset) @[RISCVPlatform.scala 22:14] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1441 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1442 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1444 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1446 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1447 = or(_T_1446, reset) @[RISCVPlatform.scala 22:14] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1449 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1450 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1452 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1454 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1455 = or(_T_1454, reset) @[RISCVPlatform.scala 22:14] + node _T_1457 = eq(_T_1455, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1457 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1459 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1460 = or(_T_1459, reset) @[RISCVPlatform.scala 22:14] + node _T_1462 = eq(_T_1460, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1462 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1464 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1464 : @[RISCVPlatform.scala 22:14] + node _T_1465 = or(_T_1327[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1467 = eq(_T_1465, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1467 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1468 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1470 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1471 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1473 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1475 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1476 = or(_T_1475, reset) @[RISCVPlatform.scala 22:14] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1478 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1480 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + when _T_1480 : @[RISCVPlatform.scala 22:14] + node _T_1481 = or(_T_1327[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1483 = eq(_T_1481, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1483 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1484 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1486 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1487 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1489 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1491 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1492 = or(_T_1491, reset) @[RISCVPlatform.scala 22:14] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1494 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:14] + when _T_1496 : @[RISCVPlatform.scala 22:14] + node _T_1497 = or(_T_1327[0], reset) @[RISCVPlatform.scala 22:14] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1499 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1500 = or(_T_1308, reset) @[RISCVPlatform.scala 22:14] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1502 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1503 = or(_T_1316, reset) @[RISCVPlatform.scala 22:14] + node _T_1505 = eq(_T_1503, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1505 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1507 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1508 = or(_T_1507, reset) @[RISCVPlatform.scala 22:14] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1510 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1512 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1513 = or(_T_1512, reset) @[RISCVPlatform.scala 22:14] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1515 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + when io.in[0].d.valid : @[RISCVPlatform.scala 22:14] + node _T_1517 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1518 = or(_T_1517, reset) @[RISCVPlatform.scala 22:14] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1520 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1522 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1523 = not(_T_1522) @[Parameters.scala 37:9] + node _T_1525 = or(_T_1523, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1526 = not(_T_1525) @[Parameters.scala 37:7] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1530 = xor(UInt<6>("h028"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1531 = not(_T_1530) @[Parameters.scala 37:9] + node _T_1533 = or(_T_1531, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1534 = not(_T_1533) @[Parameters.scala 37:7] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1538 = xor(UInt<6>("h020"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1539 = not(_T_1538) @[Parameters.scala 37:9] + node _T_1541 = or(_T_1539, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1542 = not(_T_1541) @[Parameters.scala 37:7] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1547 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1547 is invalid @[Parameters.scala 228:27] + _T_1547[0] <= _T_1528 @[Parameters.scala 228:27] + _T_1547[1] <= _T_1536 @[Parameters.scala 228:27] + _T_1547[2] <= _T_1544 @[Parameters.scala 228:27] + node _T_1553 = or(_T_1547[0], _T_1547[1]) @[Parameters.scala 229:46] + node _T_1554 = or(_T_1553, _T_1547[2]) @[Parameters.scala 229:46] + node _T_1556 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1557 = dshl(_T_1556, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1558 = bits(_T_1557, 5, 0) @[package.scala 19:76] + node _T_1559 = not(_T_1558) @[package.scala 19:40] + node _T_1560 = and(io.in[0].d.bits.addr_lo, _T_1559) @[Edges.scala 17:16] + node _T_1562 = eq(_T_1560, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1564 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + node _T_1566 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:14] + when _T_1566 : @[RISCVPlatform.scala 22:14] + node _T_1567 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1569 = eq(_T_1567, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1569 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1570 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1572 = eq(_T_1570, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1572 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1573 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1575 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1577 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1578 = or(_T_1577, reset) @[RISCVPlatform.scala 22:14] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1580 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1582 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1583 = or(_T_1582, reset) @[RISCVPlatform.scala 22:14] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1585 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1587 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1588 = or(_T_1587, reset) @[RISCVPlatform.scala 22:14] + node _T_1590 = eq(_T_1588, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1590 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1592 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 22:14] + when _T_1592 : @[RISCVPlatform.scala 22:14] + node _T_1593 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1595 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1596 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1598 = eq(_T_1596, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1598 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1599 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1601 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1603 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1604 = or(_T_1603, reset) @[RISCVPlatform.scala 22:14] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1606 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1608 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1609 = or(_T_1608, reset) @[RISCVPlatform.scala 22:14] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1611 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1613 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 22:14] + when _T_1613 : @[RISCVPlatform.scala 22:14] + node _T_1614 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1616 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1617 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1619 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1620 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1622 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1624 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 22:14] + node _T_1625 = or(_T_1624, reset) @[RISCVPlatform.scala 22:14] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1627 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1629 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 22:14] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1632 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1634 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1634 : @[RISCVPlatform.scala 22:14] + node _T_1635 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1637 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1638 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1640 = eq(_T_1638, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1640 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1641 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1643 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1645 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1646 = or(_T_1645, reset) @[RISCVPlatform.scala 22:14] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1648 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + when _T_1650 : @[RISCVPlatform.scala 22:14] + node _T_1651 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1653 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1654 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1656 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1657 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1659 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1662 = or(_T_1661, reset) @[RISCVPlatform.scala 22:14] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1664 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 22:14] + when _T_1666 : @[RISCVPlatform.scala 22:14] + node _T_1667 = or(_T_1554, reset) @[RISCVPlatform.scala 22:14] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1669 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1670 = or(_T_1562, reset) @[RISCVPlatform.scala 22:14] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1672 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1673 = or(_T_1564, reset) @[RISCVPlatform.scala 22:14] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1675 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1678 = or(_T_1677, reset) @[RISCVPlatform.scala 22:14] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1680 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1682 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1683 = or(_T_1682, reset) @[RISCVPlatform.scala 22:14] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1685 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + when io.in[0].e.valid : @[RISCVPlatform.scala 22:14] + node _T_1687 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 22:14] + node _T_1688 = or(_T_1687, reset) @[RISCVPlatform.scala 22:14] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1690 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1691 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1693 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1694 = dshl(_T_1693, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1695 = bits(_T_1694, 5, 0) @[package.scala 19:76] + node _T_1696 = not(_T_1695) @[package.scala 19:40] + node _T_1697 = shr(_T_1696, 3) @[Edges.scala 198:59] + node _T_1698 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1702 = mux(_T_1700, _T_1697, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1704 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1706 = sub(_T_1704, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1707 = asUInt(_T_1706) @[Edges.scala 208:28] + node _T_1708 = tail(_T_1707, 1) @[Edges.scala 208:28] + node _T_1710 = eq(_T_1704, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1712 = eq(_T_1704, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1714 = eq(_T_1702, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1715 = or(_T_1712, _T_1714) @[Edges.scala 210:37] + node _T_1716 = and(_T_1715, _T_1691) @[Edges.scala 211:22] + node _T_1717 = not(_T_1708) @[Edges.scala 212:27] + node _T_1718 = and(_T_1702, _T_1717) @[Edges.scala 212:25] + when _T_1691 : @[Edges.scala 213:17] + node _T_1719 = mux(_T_1710, _T_1702, _T_1708) @[Edges.scala 214:21] + _T_1704 <= _T_1719 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1721 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1723 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1725 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1727 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1729 : UInt, clock @[RISCVPlatform.scala 22:14] + node _T_1731 = eq(_T_1710, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1732 = and(io.in[0].a.valid, _T_1731) @[RISCVPlatform.scala 22:14] + when _T_1732 : @[RISCVPlatform.scala 22:14] + node _T_1733 = eq(io.in[0].a.bits.opcode, _T_1721) @[RISCVPlatform.scala 22:14] + node _T_1734 = or(_T_1733, reset) @[RISCVPlatform.scala 22:14] + node _T_1736 = eq(_T_1734, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1736 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1737 = eq(io.in[0].a.bits.param, _T_1723) @[RISCVPlatform.scala 22:14] + node _T_1738 = or(_T_1737, reset) @[RISCVPlatform.scala 22:14] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1740 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1741 = eq(io.in[0].a.bits.size, _T_1725) @[RISCVPlatform.scala 22:14] + node _T_1742 = or(_T_1741, reset) @[RISCVPlatform.scala 22:14] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1744 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1745 = eq(io.in[0].a.bits.source, _T_1727) @[RISCVPlatform.scala 22:14] + node _T_1746 = or(_T_1745, reset) @[RISCVPlatform.scala 22:14] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1748 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1749 = eq(io.in[0].a.bits.address, _T_1729) @[RISCVPlatform.scala 22:14] + node _T_1750 = or(_T_1749, reset) @[RISCVPlatform.scala 22:14] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1752 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1753 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1754 = and(_T_1753, _T_1710) @[RISCVPlatform.scala 22:14] + when _T_1754 : @[RISCVPlatform.scala 22:14] + _T_1721 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 22:14] + _T_1723 <= io.in[0].a.bits.param @[RISCVPlatform.scala 22:14] + _T_1725 <= io.in[0].a.bits.size @[RISCVPlatform.scala 22:14] + _T_1727 <= io.in[0].a.bits.source @[RISCVPlatform.scala 22:14] + _T_1729 <= io.in[0].a.bits.address @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1755 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1757 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1758 = dshl(_T_1757, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1759 = bits(_T_1758, 5, 0) @[package.scala 19:76] + node _T_1760 = not(_T_1759) @[package.scala 19:40] + node _T_1761 = shr(_T_1760, 3) @[Edges.scala 198:59] + node _T_1762 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1767 = mux(UInt<1>("h00"), _T_1761, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1769 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1771 = sub(_T_1769, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1772 = asUInt(_T_1771) @[Edges.scala 208:28] + node _T_1773 = tail(_T_1772, 1) @[Edges.scala 208:28] + node _T_1775 = eq(_T_1769, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1777 = eq(_T_1769, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1779 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1780 = or(_T_1777, _T_1779) @[Edges.scala 210:37] + node _T_1781 = and(_T_1780, _T_1755) @[Edges.scala 211:22] + node _T_1782 = not(_T_1773) @[Edges.scala 212:27] + node _T_1783 = and(_T_1767, _T_1782) @[Edges.scala 212:25] + when _T_1755 : @[Edges.scala 213:17] + node _T_1784 = mux(_T_1775, _T_1767, _T_1773) @[Edges.scala 214:21] + _T_1769 <= _T_1784 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1786 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1788 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1790 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1792 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1794 : UInt, clock @[RISCVPlatform.scala 22:14] + node _T_1796 = eq(_T_1775, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1797 = and(io.in[0].b.valid, _T_1796) @[RISCVPlatform.scala 22:14] + when _T_1797 : @[RISCVPlatform.scala 22:14] + node _T_1798 = eq(io.in[0].b.bits.opcode, _T_1786) @[RISCVPlatform.scala 22:14] + node _T_1799 = or(_T_1798, reset) @[RISCVPlatform.scala 22:14] + node _T_1801 = eq(_T_1799, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1801 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1802 = eq(io.in[0].b.bits.param, _T_1788) @[RISCVPlatform.scala 22:14] + node _T_1803 = or(_T_1802, reset) @[RISCVPlatform.scala 22:14] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1805 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1806 = eq(io.in[0].b.bits.size, _T_1790) @[RISCVPlatform.scala 22:14] + node _T_1807 = or(_T_1806, reset) @[RISCVPlatform.scala 22:14] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1809 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1810 = eq(io.in[0].b.bits.source, _T_1792) @[RISCVPlatform.scala 22:14] + node _T_1811 = or(_T_1810, reset) @[RISCVPlatform.scala 22:14] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1813 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1814 = eq(io.in[0].b.bits.address, _T_1794) @[RISCVPlatform.scala 22:14] + node _T_1815 = or(_T_1814, reset) @[RISCVPlatform.scala 22:14] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1817 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1818 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1819 = and(_T_1818, _T_1775) @[RISCVPlatform.scala 22:14] + when _T_1819 : @[RISCVPlatform.scala 22:14] + _T_1786 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 22:14] + _T_1788 <= io.in[0].b.bits.param @[RISCVPlatform.scala 22:14] + _T_1790 <= io.in[0].b.bits.size @[RISCVPlatform.scala 22:14] + _T_1792 <= io.in[0].b.bits.source @[RISCVPlatform.scala 22:14] + _T_1794 <= io.in[0].b.bits.address @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1820 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1822 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1823 = dshl(_T_1822, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1824 = bits(_T_1823, 5, 0) @[package.scala 19:76] + node _T_1825 = not(_T_1824) @[package.scala 19:40] + node _T_1826 = shr(_T_1825, 3) @[Edges.scala 198:59] + node _T_1827 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1829 = mux(_T_1827, _T_1826, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1831 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1833 = sub(_T_1831, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1834 = asUInt(_T_1833) @[Edges.scala 208:28] + node _T_1835 = tail(_T_1834, 1) @[Edges.scala 208:28] + node _T_1837 = eq(_T_1831, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1839 = eq(_T_1831, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1841 = eq(_T_1829, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1842 = or(_T_1839, _T_1841) @[Edges.scala 210:37] + node _T_1843 = and(_T_1842, _T_1820) @[Edges.scala 211:22] + node _T_1844 = not(_T_1835) @[Edges.scala 212:27] + node _T_1845 = and(_T_1829, _T_1844) @[Edges.scala 212:25] + when _T_1820 : @[Edges.scala 213:17] + node _T_1846 = mux(_T_1837, _T_1829, _T_1835) @[Edges.scala 214:21] + _T_1831 <= _T_1846 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1848 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1850 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1852 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1854 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1856 : UInt, clock @[RISCVPlatform.scala 22:14] + node _T_1858 = eq(_T_1837, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1859 = and(io.in[0].c.valid, _T_1858) @[RISCVPlatform.scala 22:14] + when _T_1859 : @[RISCVPlatform.scala 22:14] + node _T_1860 = eq(io.in[0].c.bits.opcode, _T_1848) @[RISCVPlatform.scala 22:14] + node _T_1861 = or(_T_1860, reset) @[RISCVPlatform.scala 22:14] + node _T_1863 = eq(_T_1861, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1863 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1864 = eq(io.in[0].c.bits.param, _T_1850) @[RISCVPlatform.scala 22:14] + node _T_1865 = or(_T_1864, reset) @[RISCVPlatform.scala 22:14] + node _T_1867 = eq(_T_1865, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1867 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1868 = eq(io.in[0].c.bits.size, _T_1852) @[RISCVPlatform.scala 22:14] + node _T_1869 = or(_T_1868, reset) @[RISCVPlatform.scala 22:14] + node _T_1871 = eq(_T_1869, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1871 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1872 = eq(io.in[0].c.bits.source, _T_1854) @[RISCVPlatform.scala 22:14] + node _T_1873 = or(_T_1872, reset) @[RISCVPlatform.scala 22:14] + node _T_1875 = eq(_T_1873, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1875 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1876 = eq(io.in[0].c.bits.address, _T_1856) @[RISCVPlatform.scala 22:14] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 22:14] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1879 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1880 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1881 = and(_T_1880, _T_1837) @[RISCVPlatform.scala 22:14] + when _T_1881 : @[RISCVPlatform.scala 22:14] + _T_1848 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 22:14] + _T_1850 <= io.in[0].c.bits.param @[RISCVPlatform.scala 22:14] + _T_1852 <= io.in[0].c.bits.size @[RISCVPlatform.scala 22:14] + _T_1854 <= io.in[0].c.bits.source @[RISCVPlatform.scala 22:14] + _T_1856 <= io.in[0].c.bits.address @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1882 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1884 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1885 = dshl(_T_1884, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1886 = bits(_T_1885, 5, 0) @[package.scala 19:76] + node _T_1887 = not(_T_1886) @[package.scala 19:40] + node _T_1888 = shr(_T_1887, 3) @[Edges.scala 198:59] + node _T_1889 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1891 = mux(_T_1889, _T_1888, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1893 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1895 = sub(_T_1893, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1896 = asUInt(_T_1895) @[Edges.scala 208:28] + node _T_1897 = tail(_T_1896, 1) @[Edges.scala 208:28] + node _T_1899 = eq(_T_1893, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1901 = eq(_T_1893, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1903 = eq(_T_1891, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1904 = or(_T_1901, _T_1903) @[Edges.scala 210:37] + node _T_1905 = and(_T_1904, _T_1882) @[Edges.scala 211:22] + node _T_1906 = not(_T_1897) @[Edges.scala 212:27] + node _T_1907 = and(_T_1891, _T_1906) @[Edges.scala 212:25] + when _T_1882 : @[Edges.scala 213:17] + node _T_1908 = mux(_T_1899, _T_1891, _T_1897) @[Edges.scala 214:21] + _T_1893 <= _T_1908 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1910 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1912 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1914 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1916 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1918 : UInt, clock @[RISCVPlatform.scala 22:14] + reg _T_1920 : UInt, clock @[RISCVPlatform.scala 22:14] + node _T_1922 = eq(_T_1899, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_1923 = and(io.in[0].d.valid, _T_1922) @[RISCVPlatform.scala 22:14] + when _T_1923 : @[RISCVPlatform.scala 22:14] + node _T_1924 = eq(io.in[0].d.bits.opcode, _T_1910) @[RISCVPlatform.scala 22:14] + node _T_1925 = or(_T_1924, reset) @[RISCVPlatform.scala 22:14] + node _T_1927 = eq(_T_1925, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1927 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1928 = eq(io.in[0].d.bits.param, _T_1912) @[RISCVPlatform.scala 22:14] + node _T_1929 = or(_T_1928, reset) @[RISCVPlatform.scala 22:14] + node _T_1931 = eq(_T_1929, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1931 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1932 = eq(io.in[0].d.bits.size, _T_1914) @[RISCVPlatform.scala 22:14] + node _T_1933 = or(_T_1932, reset) @[RISCVPlatform.scala 22:14] + node _T_1935 = eq(_T_1933, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1935 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1936 = eq(io.in[0].d.bits.source, _T_1916) @[RISCVPlatform.scala 22:14] + node _T_1937 = or(_T_1936, reset) @[RISCVPlatform.scala 22:14] + node _T_1939 = eq(_T_1937, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1939 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1940 = eq(io.in[0].d.bits.sink, _T_1918) @[RISCVPlatform.scala 22:14] + node _T_1941 = or(_T_1940, reset) @[RISCVPlatform.scala 22:14] + node _T_1943 = eq(_T_1941, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1943 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1944 = eq(io.in[0].d.bits.addr_lo, _T_1920) @[RISCVPlatform.scala 22:14] + node _T_1945 = or(_T_1944, reset) @[RISCVPlatform.scala 22:14] + node _T_1947 = eq(_T_1945, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_1947 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_1948 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1949 = and(_T_1948, _T_1899) @[RISCVPlatform.scala 22:14] + when _T_1949 : @[RISCVPlatform.scala 22:14] + _T_1910 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 22:14] + _T_1912 <= io.in[0].d.bits.param @[RISCVPlatform.scala 22:14] + _T_1914 <= io.in[0].d.bits.size @[RISCVPlatform.scala 22:14] + _T_1916 <= io.in[0].d.bits.source @[RISCVPlatform.scala 22:14] + _T_1918 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 22:14] + _T_1920 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + reg _T_1951 : UInt<48>, clock with : (reset => (reset, UInt<48>("h00"))) @[Reg.scala 26:44] + node _T_1952 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1954 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1955 = dshl(_T_1954, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1956 = bits(_T_1955, 5, 0) @[package.scala 19:76] + node _T_1957 = not(_T_1956) @[package.scala 19:40] + node _T_1958 = shr(_T_1957, 3) @[Edges.scala 198:59] + node _T_1959 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1961 = eq(_T_1959, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1963 = mux(_T_1961, _T_1958, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1965 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1967 = sub(_T_1965, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1968 = asUInt(_T_1967) @[Edges.scala 208:28] + node _T_1969 = tail(_T_1968, 1) @[Edges.scala 208:28] + node _T_1971 = eq(_T_1965, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1973 = eq(_T_1965, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1975 = eq(_T_1963, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1976 = or(_T_1973, _T_1975) @[Edges.scala 210:37] + node _T_1977 = and(_T_1976, _T_1952) @[Edges.scala 211:22] + node _T_1978 = not(_T_1969) @[Edges.scala 212:27] + node _T_1979 = and(_T_1963, _T_1978) @[Edges.scala 212:25] + when _T_1952 : @[Edges.scala 213:17] + node _T_1980 = mux(_T_1971, _T_1963, _T_1969) @[Edges.scala 214:21] + _T_1965 <= _T_1980 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1981 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1983 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1984 = dshl(_T_1983, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1985 = bits(_T_1984, 5, 0) @[package.scala 19:76] + node _T_1986 = not(_T_1985) @[package.scala 19:40] + node _T_1987 = shr(_T_1986, 3) @[Edges.scala 198:59] + node _T_1988 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1990 = mux(_T_1988, _T_1987, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1992 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1994 = sub(_T_1992, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1995 = asUInt(_T_1994) @[Edges.scala 208:28] + node _T_1996 = tail(_T_1995, 1) @[Edges.scala 208:28] + node _T_1998 = eq(_T_1992, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2000 = eq(_T_1992, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2002 = eq(_T_1990, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2003 = or(_T_2000, _T_2002) @[Edges.scala 210:37] + node _T_2004 = and(_T_2003, _T_1981) @[Edges.scala 211:22] + node _T_2005 = not(_T_1996) @[Edges.scala 212:27] + node _T_2006 = and(_T_1990, _T_2005) @[Edges.scala 212:25] + when _T_1981 : @[Edges.scala 213:17] + node _T_2007 = mux(_T_1998, _T_1990, _T_1996) @[Edges.scala 214:21] + _T_1992 <= _T_2007 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_2009 : UInt<48> + _T_2009 is invalid + _T_2009 <= UInt<48>("h00") + node _T_2010 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2010 : @[RISCVPlatform.scala 22:14] + when _T_1976 : @[RISCVPlatform.scala 22:14] + node _T_2012 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2009 <= _T_2012 @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_2013 = dshr(_T_1951, io.in[0].a.bits.source) @[RISCVPlatform.scala 22:14] + node _T_2014 = bits(_T_2013, 0, 0) @[RISCVPlatform.scala 22:14] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + node _T_2017 = or(_T_2016, reset) @[RISCVPlatform.scala 22:14] + node _T_2019 = eq(_T_2017, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_2019 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + wire _T_2021 : UInt<48> + _T_2021 is invalid + _T_2021 <= UInt<48>("h00") + node _T_2022 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2024 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 22:14] + node _T_2025 = and(_T_2022, _T_2024) @[RISCVPlatform.scala 22:14] + when _T_2025 : @[RISCVPlatform.scala 22:14] + when _T_2003 : @[RISCVPlatform.scala 22:14] + node _T_2027 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2021 <= _T_2027 @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_2028 = or(_T_2009, _T_1951) @[RISCVPlatform.scala 22:14] + node _T_2029 = dshr(_T_2028, io.in[0].d.bits.source) @[RISCVPlatform.scala 22:14] + node _T_2030 = bits(_T_2029, 0, 0) @[RISCVPlatform.scala 22:14] + node _T_2031 = or(_T_2030, reset) @[RISCVPlatform.scala 22:14] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[RISCVPlatform.scala 22:14] + when _T_2033 : @[RISCVPlatform.scala 22:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:22:14)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 22:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + skip @[RISCVPlatform.scala 22:14] + node _T_2034 = or(_T_1951, _T_2009) @[RISCVPlatform.scala 22:14] + node _T_2035 = not(_T_2021) @[RISCVPlatform.scala 22:14] + node _T_2036 = and(_T_2034, _T_2035) @[RISCVPlatform.scala 22:14] + _T_1951 <= _T_2036 @[RISCVPlatform.scala 22:14] + + module Repeater_5 : + input clock : Clock + input reset : UInt<1> + output io : {flip repeat : UInt<1>, full : UInt<1>, flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}} + + io is invalid + io is invalid + reg full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg saved : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}, clock @[Repeater.scala 19:18] + node _T_77 = or(io.enq.valid, full) @[Repeater.scala 22:32] + io.deq.valid <= _T_77 @[Repeater.scala 22:16] + node _T_79 = eq(full, UInt<1>("h00")) @[Repeater.scala 23:35] + node _T_80 = and(io.deq.ready, _T_79) @[Repeater.scala 23:32] + io.enq.ready <= _T_80 @[Repeater.scala 23:16] + node _T_81 = mux(full, saved, io.enq.bits) @[Repeater.scala 24:21] + io.deq.bits <- _T_81 @[Repeater.scala 24:15] + io.full <= full @[Repeater.scala 25:11] + node _T_89 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_90 = and(_T_89, io.repeat) @[Repeater.scala 27:23] + when _T_90 : @[Repeater.scala 27:38] + full <= UInt<1>("h01") @[Repeater.scala 27:45] + saved <- io.enq.bits @[Repeater.scala 27:66] + skip @[Repeater.scala 27:38] + node _T_92 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_94 = eq(io.repeat, UInt<1>("h00")) @[Repeater.scala 28:26] + node _T_95 = and(_T_92, _T_94) @[Repeater.scala 28:23] + when _T_95 : @[Repeater.scala 28:38] + full <= UInt<1>("h00") @[Repeater.scala 28:45] + skip @[Repeater.scala 28:38] + + module TLFragmenter_clint : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, out : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}} + + io is invalid + io is invalid + reg _T_531 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + reg _T_533 : UInt, clock @[Fragmenter.scala 136:22] + node _T_534 = bits(io.out.0.d.bits.source, 2, 0) @[Fragmenter.scala 137:39] + node _T_536 = eq(_T_531, UInt<1>("h00")) @[Fragmenter.scala 138:27] + node _T_538 = bits(io.out.0.d.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_539 = dshl(UInt<1>("h01"), _T_538) @[OneHot.scala 49:12] + node _T_540 = bits(_T_539, 3, 0) @[OneHot.scala 49:37] + node _T_542 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_543 = dshl(_T_542, io.out.0.d.bits.size) @[package.scala 19:71] + node _T_544 = bits(_T_543, 2, 0) @[package.scala 19:76] + node _T_545 = not(_T_544) @[package.scala 19:40] + node _T_546 = bits(io.out.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_547 = shl(_T_534, 0) @[Fragmenter.scala 144:38] + node _T_548 = shr(_T_545, 3) @[Fragmenter.scala 145:34] + node _T_550 = eq(io.out.0.d.valid, UInt<1>("h00")) @[Fragmenter.scala 146:15] + node _T_551 = and(_T_547, _T_548) @[Fragmenter.scala 146:48] + node _T_553 = eq(_T_551, UInt<1>("h00")) @[Fragmenter.scala 146:63] + node _T_554 = or(_T_550, _T_553) @[Fragmenter.scala 146:28] + node _T_555 = or(_T_554, reset) @[Fragmenter.scala 146:14] + node _T_557 = eq(_T_555, UInt<1>("h00")) @[Fragmenter.scala 146:14] + when _T_557 : @[Fragmenter.scala 146:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:146 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n") @[Fragmenter.scala 146:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 146:14] + skip @[Fragmenter.scala 146:14] + node _T_559 = mux(_T_546, _T_548, UInt<1>("h00")) @[Fragmenter.scala 147:48] + node _T_560 = or(_T_547, _T_559) @[Fragmenter.scala 147:43] + node _T_562 = shr(_T_540, 3) @[Fragmenter.scala 148:58] + node _T_563 = mux(_T_546, UInt<1>("h01"), _T_562) @[Fragmenter.scala 148:30] + node _T_564 = shl(_T_534, 3) @[Fragmenter.scala 150:45] + node _T_565 = or(_T_564, _T_545) @[Fragmenter.scala 150:67] + node _T_566 = shl(_T_565, 1) @[package.scala 17:29] + node _T_568 = or(_T_566, UInt<1>("h01")) @[package.scala 17:34] + node _T_570 = cat(UInt<1>("h00"), _T_565) @[Cat.scala 30:58] + node _T_571 = not(_T_570) @[package.scala 17:47] + node _T_572 = and(_T_568, _T_571) @[package.scala 17:45] + node _T_573 = bits(_T_572, 6, 4) @[OneHot.scala 26:18] + node _T_574 = bits(_T_572, 3, 0) @[OneHot.scala 27:18] + node _T_576 = neq(_T_573, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_577 = or(_T_573, _T_574) @[OneHot.scala 28:28] + node _T_578 = bits(_T_577, 3, 2) @[OneHot.scala 26:18] + node _T_579 = bits(_T_577, 1, 0) @[OneHot.scala 27:18] + node _T_581 = neq(_T_578, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_582 = or(_T_578, _T_579) @[OneHot.scala 28:28] + node _T_583 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_584 = cat(_T_581, _T_583) @[Cat.scala 30:58] + node _T_585 = cat(_T_576, _T_584) @[Cat.scala 30:58] + node _T_586 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_586 : @[Fragmenter.scala 152:27] + node _T_587 = sub(_T_531, _T_563) @[Fragmenter.scala 153:53] + node _T_588 = asUInt(_T_587) @[Fragmenter.scala 153:53] + node _T_589 = tail(_T_588, 1) @[Fragmenter.scala 153:53] + node _T_590 = mux(_T_536, _T_560, _T_589) @[Fragmenter.scala 153:22] + _T_531 <= _T_590 @[Fragmenter.scala 153:16] + when _T_536 : @[Fragmenter.scala 154:23] + _T_533 <= _T_585 @[Fragmenter.scala 154:31] + skip @[Fragmenter.scala 154:23] + skip @[Fragmenter.scala 152:27] + node _T_592 = eq(_T_546, UInt<1>("h00")) @[Fragmenter.scala 158:18] + node _T_594 = neq(_T_534, UInt<1>("h00")) @[Fragmenter.scala 158:41] + node _T_595 = and(_T_592, _T_594) @[Fragmenter.scala 158:28] + node _T_596 = or(io.in.0.d.ready, _T_595) @[Fragmenter.scala 159:33] + io.out.0.d.ready <= _T_596 @[Fragmenter.scala 159:19] + node _T_598 = eq(_T_595, UInt<1>("h00")) @[Fragmenter.scala 160:37] + node _T_599 = and(io.out.0.d.valid, _T_598) @[Fragmenter.scala 160:34] + io.in.0.d.valid <= _T_599 @[Fragmenter.scala 160:19] + io.in.0.d.bits <- io.out.0.d.bits @[Fragmenter.scala 161:19] + node _T_600 = not(_T_545) @[Fragmenter.scala 162:49] + node _T_601 = and(io.out.0.d.bits.addr_lo, _T_600) @[Fragmenter.scala 162:47] + io.in.0.d.bits.addr_lo <= _T_601 @[Fragmenter.scala 162:25] + node _T_602 = shr(io.out.0.d.bits.source, 3) @[Fragmenter.scala 163:45] + io.in.0.d.bits.source <= _T_602 @[Fragmenter.scala 163:24] + node _T_603 = mux(_T_536, _T_585, _T_533) @[Fragmenter.scala 164:30] + io.in.0.d.bits.size <= _T_603 @[Fragmenter.scala 164:24] + reg _T_605 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_606 = or(_T_605, io.out.0.d.bits.error) @[Fragmenter.scala 168:29] + node _T_607 = and(io.out.0.d.ready, io.out.0.d.valid) @[Decoupled.scala 30:37] + when _T_607 : @[Fragmenter.scala 169:27] + node _T_609 = mux(_T_595, _T_606, UInt<1>("h00")) @[Fragmenter.scala 169:43] + _T_605 <= _T_609 @[Fragmenter.scala 169:37] + skip @[Fragmenter.scala 169:27] + io.in.0.d.bits.error <= _T_606 @[Fragmenter.scala 170:23] + inst Repeater of Repeater_5 @[Fragmenter.scala 190:28] + Repeater.io is invalid + Repeater.clock <= clock + Repeater.reset <= reset + Repeater.io.enq <- io.in.0.a @[Fragmenter.scala 191:23] + node _T_615 = xor(Repeater.io.deq.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_616 = cvt(_T_615) @[Parameters.scala 117:49] + node _T_618 = and(_T_616, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_619 = asSInt(_T_618) @[Parameters.scala 117:52] + node _T_621 = eq(_T_619, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_624 : UInt<1>[1] @[Parameters.scala 112:36] + _T_624 is invalid @[Parameters.scala 112:36] + _T_624[0] <= _T_621 @[Parameters.scala 112:36] + node _T_634 = eq(UInt<3>("h05"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_635 = mux(_T_634, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 46:16] + node _T_636 = eq(UInt<3>("h04"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_637 = mux(_T_636, UInt<2>("h03"), _T_635) @[Mux.scala 46:16] + node _T_638 = eq(UInt<2>("h03"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_639 = mux(_T_638, UInt<2>("h03"), _T_637) @[Mux.scala 46:16] + node _T_640 = eq(UInt<2>("h02"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_641 = mux(_T_640, UInt<2>("h03"), _T_639) @[Mux.scala 46:16] + node _T_642 = eq(UInt<1>("h01"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_643 = mux(_T_642, UInt<2>("h03"), _T_641) @[Mux.scala 46:16] + node _T_644 = eq(UInt<1>("h00"), Repeater.io.deq.bits.opcode) @[Mux.scala 46:19] + node _T_645 = mux(_T_644, UInt<2>("h03"), _T_643) @[Mux.scala 46:16] + node _T_646 = gt(Repeater.io.deq.bits.size, _T_645) @[Fragmenter.scala 213:29] + node _T_647 = mux(_T_646, _T_645, Repeater.io.deq.bits.size) @[Fragmenter.scala 213:22] + node _T_649 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_650 = dshl(_T_649, Repeater.io.deq.bits.size) @[package.scala 19:71] + node _T_651 = bits(_T_650, 5, 0) @[package.scala 19:76] + node _T_652 = not(_T_651) @[package.scala 19:40] + node _T_654 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_655 = dshl(_T_654, _T_647) @[package.scala 19:71] + node _T_656 = bits(_T_655, 2, 0) @[package.scala 19:76] + node _T_657 = not(_T_656) @[package.scala 19:40] + node _T_658 = bits(Repeater.io.deq.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_660 = eq(_T_658, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_662 = mux(_T_660, UInt<1>("h00"), _T_657) @[Fragmenter.scala 217:22] + reg _T_664 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_666 = eq(_T_664, UInt<1>("h00")) @[Fragmenter.scala 220:27] + node _T_667 = shr(_T_652, 3) @[Fragmenter.scala 221:46] + node _T_669 = sub(_T_664, UInt<1>("h01")) @[Fragmenter.scala 221:77] + node _T_670 = asUInt(_T_669) @[Fragmenter.scala 221:77] + node _T_671 = tail(_T_670, 1) @[Fragmenter.scala 221:77] + node _T_672 = mux(_T_666, _T_667, _T_671) @[Fragmenter.scala 221:28] + node _T_673 = not(_T_672) @[Fragmenter.scala 222:26] + node _T_674 = shr(_T_662, 3) @[Fragmenter.scala 222:48] + node _T_675 = or(_T_673, _T_674) @[Fragmenter.scala 222:39] + node _T_676 = not(_T_675) @[Fragmenter.scala 222:24] + node _T_677 = shr(_T_672, 0) @[Fragmenter.scala 223:38] + node _T_678 = not(_T_677) @[Fragmenter.scala 223:24] + node _T_679 = shr(_T_657, 3) @[Fragmenter.scala 223:82] + node _T_680 = or(_T_678, _T_679) @[Fragmenter.scala 223:70] + node _T_681 = not(_T_680) @[Fragmenter.scala 223:22] + node _T_682 = and(io.out.0.a.ready, io.out.0.a.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Fragmenter.scala 225:27] + _T_664 <= _T_676 @[Fragmenter.scala 225:36] + skip @[Fragmenter.scala 225:27] + node _T_684 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 227:29] + node _T_686 = neq(_T_681, UInt<1>("h00")) @[Fragmenter.scala 227:51] + node _T_687 = and(_T_684, _T_686) @[Fragmenter.scala 227:39] + Repeater.io.repeat <= _T_687 @[Fragmenter.scala 227:26] + io.out.0.a <- Repeater.io.deq @[Fragmenter.scala 228:13] + node _T_688 = not(_T_681) @[Fragmenter.scala 229:50] + node _T_689 = shl(_T_688, 3) @[Fragmenter.scala 229:60] + node _T_690 = and(_T_689, _T_652) @[Fragmenter.scala 229:81] + node _T_691 = or(Repeater.io.deq.bits.address, _T_690) @[Fragmenter.scala 229:47] + io.out.0.a.bits.address <= _T_691 @[Fragmenter.scala 229:26] + node _T_692 = cat(Repeater.io.deq.bits.source, _T_681) @[Cat.scala 30:58] + io.out.0.a.bits.source <= _T_692 @[Fragmenter.scala 230:25] + io.out.0.a.bits.size <= _T_647 @[Fragmenter.scala 231:23] + node _T_694 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 234:15] + node _T_696 = eq(_T_660, UInt<1>("h00")) @[Fragmenter.scala 234:36] + node _T_697 = or(_T_694, _T_696) @[Fragmenter.scala 234:33] + node _T_698 = or(_T_697, reset) @[Fragmenter.scala 234:14] + node _T_700 = eq(_T_698, UInt<1>("h00")) @[Fragmenter.scala 234:14] + when _T_700 : @[Fragmenter.scala 234:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:234 assert (!repeater.io.full || !aHasData)\n") @[Fragmenter.scala 234:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 234:14] + skip @[Fragmenter.scala 234:14] + io.out.0.a.bits.data <= io.in.0.a.bits.data @[Fragmenter.scala 235:23] + node _T_703 = eq(Repeater.io.full, UInt<1>("h00")) @[Fragmenter.scala 237:15] + node _T_704 = eq(Repeater.io.deq.bits.mask, UInt<8>("h0ff")) @[Fragmenter.scala 237:51] + node _T_705 = or(_T_703, _T_704) @[Fragmenter.scala 237:33] + node _T_706 = or(_T_705, reset) @[Fragmenter.scala 237:14] + node _T_708 = eq(_T_706, UInt<1>("h00")) @[Fragmenter.scala 237:14] + when _T_708 : @[Fragmenter.scala 237:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") @[Fragmenter.scala 237:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 237:14] + skip @[Fragmenter.scala 237:14] + node _T_709 = mux(Repeater.io.full, UInt<8>("h0ff"), io.in.0.a.bits.mask) @[Fragmenter.scala 238:29] + io.out.0.a.bits.mask <= _T_709 @[Fragmenter.scala 238:23] + io.in.0.b.valid <= UInt<1>("h00") @[Fragmenter.scala 241:18] + io.in.0.c.ready <= UInt<1>("h01") @[Fragmenter.scala 242:18] + io.in.0.e.ready <= UInt<1>("h01") @[Fragmenter.scala 243:18] + io.out.0.b.ready <= UInt<1>("h01") @[Fragmenter.scala 244:19] + io.out.0.c.valid <= UInt<1>("h00") @[Fragmenter.scala 245:19] + io.out.0.e.valid <= UInt<1>("h00") @[Fragmenter.scala 246:19] + + module TLMonitor_29 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 23:61] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 23:61] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_608 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 5, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:61] + when _T_708 : @[RISCVPlatform.scala 23:61] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = and(_T_711, _T_719) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), _T_720) @[Parameters.scala 134:30] + node _T_723 = or(_T_722, reset) @[RISCVPlatform.scala 23:61] + node _T_725 = eq(_T_723, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_725 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_726 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_728 = eq(_T_726, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_728 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_730 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_731 = or(_T_730, reset) @[RISCVPlatform.scala 23:61] + node _T_733 = eq(_T_731, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_733 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_734 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_736 = eq(_T_734, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_736 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_738 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_739 = or(_T_738, reset) @[RISCVPlatform.scala 23:61] + node _T_741 = eq(_T_739, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_741 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_742 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 23:61] + node _T_744 = eq(_T_742, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_745 = or(_T_744, reset) @[RISCVPlatform.scala 23:61] + node _T_747 = eq(_T_745, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_747 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_749 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:61] + when _T_749 : @[RISCVPlatform.scala 23:61] + node _T_752 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_754 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_755 = and(_T_752, _T_754) @[Parameters.scala 63:37] + node _T_756 = or(UInt<1>("h00"), _T_755) @[Parameters.scala 132:31] + node _T_758 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_759 = cvt(_T_758) @[Parameters.scala 117:49] + node _T_761 = and(_T_759, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_762 = asSInt(_T_761) @[Parameters.scala 117:52] + node _T_764 = eq(_T_762, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_765 = and(_T_756, _T_764) @[Parameters.scala 132:56] + node _T_767 = or(UInt<1>("h00"), _T_765) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[RISCVPlatform.scala 23:61] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_770 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_771 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_773 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_774 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_776 = eq(_T_774, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_776 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_778 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_779 = or(_T_778, reset) @[RISCVPlatform.scala 23:61] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_781 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_782 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 23:61] + node _T_783 = or(_T_782, reset) @[RISCVPlatform.scala 23:61] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_785 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_787 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_787 : @[RISCVPlatform.scala 23:61] + node _T_790 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_792 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_793 = and(_T_790, _T_792) @[Parameters.scala 63:37] + node _T_794 = or(UInt<1>("h00"), _T_793) @[Parameters.scala 132:31] + node _T_796 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_797 = cvt(_T_796) @[Parameters.scala 117:49] + node _T_799 = and(_T_797, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_800 = asSInt(_T_799) @[Parameters.scala 117:52] + node _T_802 = eq(_T_800, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = and(_T_794, _T_802) @[Parameters.scala 132:56] + node _T_805 = or(UInt<1>("h00"), _T_803) @[Parameters.scala 134:30] + node _T_806 = or(_T_805, reset) @[RISCVPlatform.scala 23:61] + node _T_808 = eq(_T_806, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_808 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_809 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_811 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_812 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_814 = eq(_T_812, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_814 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_816 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_817 = or(_T_816, reset) @[RISCVPlatform.scala 23:61] + node _T_819 = eq(_T_817, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_819 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_820 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 23:61] + node _T_821 = or(_T_820, reset) @[RISCVPlatform.scala 23:61] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_823 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_825 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + when _T_825 : @[RISCVPlatform.scala 23:61] + node _T_828 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_830 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_831 = and(_T_828, _T_830) @[Parameters.scala 63:37] + node _T_832 = or(UInt<1>("h00"), _T_831) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_841) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, reset) @[RISCVPlatform.scala 23:61] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_846 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_847 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_849 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_850 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_852 = eq(_T_850, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_852 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_854 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_855 = or(_T_854, reset) @[RISCVPlatform.scala 23:61] + node _T_857 = eq(_T_855, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_857 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_858 = not(_T_706) @[RISCVPlatform.scala 23:61] + node _T_859 = and(io.in[0].a.bits.mask, _T_858) @[RISCVPlatform.scala 23:61] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_862 = or(_T_861, reset) @[RISCVPlatform.scala 23:61] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_864 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_866 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:61] + when _T_866 : @[RISCVPlatform.scala 23:61] + node _T_869 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_871 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_872 = cvt(_T_871) @[Parameters.scala 117:49] + node _T_874 = and(_T_872, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_875 = asSInt(_T_874) @[Parameters.scala 117:52] + node _T_877 = eq(_T_875, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_878 = and(_T_869, _T_877) @[Parameters.scala 132:56] + node _T_880 = or(UInt<1>("h00"), _T_878) @[Parameters.scala 134:30] + node _T_881 = or(_T_880, reset) @[RISCVPlatform.scala 23:61] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_883 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_884 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_886 = eq(_T_884, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_886 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_887 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_889 = eq(_T_887, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_889 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_891 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_892 = or(_T_891, reset) @[RISCVPlatform.scala 23:61] + node _T_894 = eq(_T_892, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_894 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_895 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 23:61] + node _T_896 = or(_T_895, reset) @[RISCVPlatform.scala 23:61] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_898 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_900 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + when _T_900 : @[RISCVPlatform.scala 23:61] + node _T_903 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_905 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_906 = cvt(_T_905) @[Parameters.scala 117:49] + node _T_908 = and(_T_906, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_909 = asSInt(_T_908) @[Parameters.scala 117:52] + node _T_911 = eq(_T_909, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = and(_T_903, _T_911) @[Parameters.scala 132:56] + node _T_914 = or(UInt<1>("h00"), _T_912) @[Parameters.scala 134:30] + node _T_915 = or(_T_914, reset) @[RISCVPlatform.scala 23:61] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_917 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_918 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_920 = eq(_T_918, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_920 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_921 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_923 = eq(_T_921, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_923 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_925 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_926 = or(_T_925, reset) @[RISCVPlatform.scala 23:61] + node _T_928 = eq(_T_926, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_928 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_929 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 23:61] + node _T_930 = or(_T_929, reset) @[RISCVPlatform.scala 23:61] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_932 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_934 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:61] + when _T_934 : @[RISCVPlatform.scala 23:61] + node _T_937 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_939 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_940 = cvt(_T_939) @[Parameters.scala 117:49] + node _T_942 = and(_T_940, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_943 = asSInt(_T_942) @[Parameters.scala 117:52] + node _T_945 = eq(_T_943, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_946 = and(_T_937, _T_945) @[Parameters.scala 132:56] + node _T_948 = or(UInt<1>("h00"), _T_946) @[Parameters.scala 134:30] + node _T_949 = or(_T_948, reset) @[RISCVPlatform.scala 23:61] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_951 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_952 = or(_T_630, reset) @[RISCVPlatform.scala 23:61] + node _T_954 = eq(_T_952, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_954 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_955 = or(_T_638, reset) @[RISCVPlatform.scala 23:61] + node _T_957 = eq(_T_955, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_957 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_958 = eq(io.in[0].a.bits.mask, _T_706) @[RISCVPlatform.scala 23:61] + node _T_959 = or(_T_958, reset) @[RISCVPlatform.scala 23:61] + node _T_961 = eq(_T_959, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_961 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + when io.in[0].b.valid : @[RISCVPlatform.scala 23:61] + node _T_963 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_964 = or(_T_963, reset) @[RISCVPlatform.scala 23:61] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_966 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_968 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_977 : UInt<1>[1] @[Parameters.scala 110:36] + _T_977 is invalid @[Parameters.scala 110:36] + _T_977[0] <= _T_974 @[Parameters.scala 110:36] + node _T_982 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_983 = dshl(_T_982, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_984 = bits(_T_983, 5, 0) @[package.scala 19:76] + node _T_985 = not(_T_984) @[package.scala 19:40] + node _T_986 = and(io.in[0].b.bits.address, _T_985) @[Edges.scala 17:16] + node _T_988 = eq(_T_986, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_990 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_991 = dshl(UInt<1>("h01"), _T_990) @[OneHot.scala 49:12] + node _T_992 = bits(_T_991, 2, 0) @[OneHot.scala 49:37] + node _T_994 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_996 = bits(_T_992, 2, 2) @[package.scala 44:26] + node _T_997 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_999 = eq(_T_997, UInt<1>("h00")) @[package.scala 46:20] + node _T_1000 = and(UInt<1>("h01"), _T_999) @[package.scala 49:27] + node _T_1001 = and(_T_996, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_994, _T_1001) @[package.scala 50:29] + node _T_1003 = and(UInt<1>("h01"), _T_997) @[package.scala 49:27] + node _T_1004 = and(_T_996, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_994, _T_1004) @[package.scala 50:29] + node _T_1006 = bits(_T_992, 1, 1) @[package.scala 44:26] + node _T_1007 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1009 = eq(_T_1007, UInt<1>("h00")) @[package.scala 46:20] + node _T_1010 = and(_T_1000, _T_1009) @[package.scala 49:27] + node _T_1011 = and(_T_1006, _T_1010) @[package.scala 50:38] + node _T_1012 = or(_T_1002, _T_1011) @[package.scala 50:29] + node _T_1013 = and(_T_1000, _T_1007) @[package.scala 49:27] + node _T_1014 = and(_T_1006, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_1002, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_1003, _T_1009) @[package.scala 49:27] + node _T_1017 = and(_T_1006, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_1005, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1003, _T_1007) @[package.scala 49:27] + node _T_1020 = and(_T_1006, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1005, _T_1020) @[package.scala 50:29] + node _T_1022 = bits(_T_992, 0, 0) @[package.scala 44:26] + node _T_1023 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1025 = eq(_T_1023, UInt<1>("h00")) @[package.scala 46:20] + node _T_1026 = and(_T_1010, _T_1025) @[package.scala 49:27] + node _T_1027 = and(_T_1022, _T_1026) @[package.scala 50:38] + node _T_1028 = or(_T_1012, _T_1027) @[package.scala 50:29] + node _T_1029 = and(_T_1010, _T_1023) @[package.scala 49:27] + node _T_1030 = and(_T_1022, _T_1029) @[package.scala 50:38] + node _T_1031 = or(_T_1012, _T_1030) @[package.scala 50:29] + node _T_1032 = and(_T_1013, _T_1025) @[package.scala 49:27] + node _T_1033 = and(_T_1022, _T_1032) @[package.scala 50:38] + node _T_1034 = or(_T_1015, _T_1033) @[package.scala 50:29] + node _T_1035 = and(_T_1013, _T_1023) @[package.scala 49:27] + node _T_1036 = and(_T_1022, _T_1035) @[package.scala 50:38] + node _T_1037 = or(_T_1015, _T_1036) @[package.scala 50:29] + node _T_1038 = and(_T_1016, _T_1025) @[package.scala 49:27] + node _T_1039 = and(_T_1022, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1018, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1016, _T_1023) @[package.scala 49:27] + node _T_1042 = and(_T_1022, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1018, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1019, _T_1025) @[package.scala 49:27] + node _T_1045 = and(_T_1022, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1021, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1019, _T_1023) @[package.scala 49:27] + node _T_1048 = and(_T_1022, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1021, _T_1048) @[package.scala 50:29] + node _T_1050 = cat(_T_1031, _T_1028) @[Cat.scala 30:58] + node _T_1051 = cat(_T_1037, _T_1034) @[Cat.scala 30:58] + node _T_1052 = cat(_T_1051, _T_1050) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1054 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1055 = cat(_T_1054, _T_1053) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1058 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:61] + when _T_1058 : @[RISCVPlatform.scala 23:61] + node _T_1060 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1061 = not(_T_1060) @[Parameters.scala 37:9] + node _T_1063 = or(_T_1061, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1064 = not(_T_1063) @[Parameters.scala 37:7] + node _T_1066 = eq(_T_1064, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1068 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1070 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1073 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1073 is invalid @[Parameters.scala 228:27] + _T_1073[0] <= _T_1066 @[Parameters.scala 228:27] + _T_1073[1] <= _T_1068 @[Parameters.scala 228:27] + _T_1073[2] <= _T_1070 @[Parameters.scala 228:27] + node _T_1081 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1083 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1084 = and(_T_1081, _T_1083) @[Parameters.scala 63:37] + node _T_1087 = mux(_T_1073[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1089 = mux(_T_1073[1], _T_1084, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1091 = mux(_T_1073[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1093 = or(_T_1087, _T_1089) @[Mux.scala 19:72] + node _T_1094 = or(_T_1093, _T_1091) @[Mux.scala 19:72] + wire _T_1096 : UInt<1> @[Mux.scala 19:72] + _T_1096 is invalid @[Mux.scala 19:72] + _T_1096 <= _T_1094 @[Mux.scala 19:72] + node _T_1097 = or(_T_1096, reset) @[RISCVPlatform.scala 23:61] + node _T_1099 = eq(_T_1097, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1099 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1100 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1102 = eq(_T_1100, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1102 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1104 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1105 = or(_T_1104, reset) @[RISCVPlatform.scala 23:61] + node _T_1107 = eq(_T_1105, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1107 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1108 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1110 = eq(_T_1108, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1110 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1112 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1113 = or(_T_1112, reset) @[RISCVPlatform.scala 23:61] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1115 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1116 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 23:61] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1119 = or(_T_1118, reset) @[RISCVPlatform.scala 23:61] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1121 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1123 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:61] + when _T_1123 : @[RISCVPlatform.scala 23:61] + node _T_1125 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1127 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1128 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1130 = eq(_T_1128, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1130 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1131 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1133 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1135 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1136 = or(_T_1135, reset) @[RISCVPlatform.scala 23:61] + node _T_1138 = eq(_T_1136, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1138 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1139 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 23:61] + node _T_1140 = or(_T_1139, reset) @[RISCVPlatform.scala 23:61] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1142 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1144 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1144 : @[RISCVPlatform.scala 23:61] + node _T_1146 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1148 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1149 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1151 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1152 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1154 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1156 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1157 = or(_T_1156, reset) @[RISCVPlatform.scala 23:61] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1159 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1160 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 23:61] + node _T_1161 = or(_T_1160, reset) @[RISCVPlatform.scala 23:61] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1163 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1165 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + when _T_1165 : @[RISCVPlatform.scala 23:61] + node _T_1167 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1169 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1170 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1172 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1173 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1175 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1177 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1178 = or(_T_1177, reset) @[RISCVPlatform.scala 23:61] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1180 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1181 = not(_T_1056) @[RISCVPlatform.scala 23:61] + node _T_1182 = and(io.in[0].b.bits.mask, _T_1181) @[RISCVPlatform.scala 23:61] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 23:61] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1187 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:61] + when _T_1189 : @[RISCVPlatform.scala 23:61] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1193 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1194 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1196 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1197 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1199 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 23:61] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1204 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1205 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 23:61] + node _T_1206 = or(_T_1205, reset) @[RISCVPlatform.scala 23:61] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1208 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1210 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + when _T_1210 : @[RISCVPlatform.scala 23:61] + node _T_1212 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1214 = eq(_T_1212, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1214 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1215 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1217 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1218 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1220 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1222 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1223 = or(_T_1222, reset) @[RISCVPlatform.scala 23:61] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1225 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1226 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 23:61] + node _T_1227 = or(_T_1226, reset) @[RISCVPlatform.scala 23:61] + node _T_1229 = eq(_T_1227, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1229 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1231 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:61] + when _T_1231 : @[RISCVPlatform.scala 23:61] + node _T_1233 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:61] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1235 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1236 = or(_T_977[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1238 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1239 = or(_T_988, reset) @[RISCVPlatform.scala 23:61] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1241 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1242 = eq(io.in[0].b.bits.mask, _T_1056) @[RISCVPlatform.scala 23:61] + node _T_1243 = or(_T_1242, reset) @[RISCVPlatform.scala 23:61] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1245 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + when io.in[0].c.valid : @[RISCVPlatform.scala 23:61] + node _T_1247 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1248 = or(_T_1247, reset) @[RISCVPlatform.scala 23:61] + node _T_1250 = eq(_T_1248, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1250 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1252 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1253 = not(_T_1252) @[Parameters.scala 37:9] + node _T_1255 = or(_T_1253, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1256 = not(_T_1255) @[Parameters.scala 37:7] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1260 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1262 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1265 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1265 is invalid @[Parameters.scala 228:27] + _T_1265[0] <= _T_1258 @[Parameters.scala 228:27] + _T_1265[1] <= _T_1260 @[Parameters.scala 228:27] + _T_1265[2] <= _T_1262 @[Parameters.scala 228:27] + node _T_1271 = or(_T_1265[0], _T_1265[1]) @[Parameters.scala 229:46] + node _T_1272 = or(_T_1271, _T_1265[2]) @[Parameters.scala 229:46] + node _T_1274 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1275 = dshl(_T_1274, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1276 = bits(_T_1275, 5, 0) @[package.scala 19:76] + node _T_1277 = not(_T_1276) @[package.scala 19:40] + node _T_1278 = and(io.in[0].c.bits.address, _T_1277) @[Edges.scala 17:16] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1282 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1283 = cvt(_T_1282) @[Parameters.scala 117:49] + node _T_1285 = and(_T_1283, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1286 = asSInt(_T_1285) @[Parameters.scala 117:52] + node _T_1288 = eq(_T_1286, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1291 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1291 is invalid @[Parameters.scala 110:36] + _T_1291[0] <= _T_1288 @[Parameters.scala 110:36] + node _T_1296 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:61] + when _T_1296 : @[RISCVPlatform.scala 23:61] + node _T_1297 = or(_T_1291[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1299 = eq(_T_1297, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1299 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1300 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1302 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1304 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1305 = or(_T_1304, reset) @[RISCVPlatform.scala 23:61] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1307 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1308 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1310 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1312 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1313 = or(_T_1312, reset) @[RISCVPlatform.scala 23:61] + node _T_1315 = eq(_T_1313, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1315 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1317 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1318 = or(_T_1317, reset) @[RISCVPlatform.scala 23:61] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1320 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1322 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:61] + when _T_1322 : @[RISCVPlatform.scala 23:61] + node _T_1323 = or(_T_1291[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1325 = eq(_T_1323, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1325 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1326 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1328 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1330 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1331 = or(_T_1330, reset) @[RISCVPlatform.scala 23:61] + node _T_1333 = eq(_T_1331, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1333 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1334 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1336 = eq(_T_1334, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1336 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1338 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1339 = or(_T_1338, reset) @[RISCVPlatform.scala 23:61] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1341 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1343 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1344 = or(_T_1343, reset) @[RISCVPlatform.scala 23:61] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1346 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1348 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:61] + when _T_1348 : @[RISCVPlatform.scala 23:61] + node _T_1351 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1353 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1354 = cvt(_T_1353) @[Parameters.scala 117:49] + node _T_1356 = and(_T_1354, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1357 = asSInt(_T_1356) @[Parameters.scala 117:52] + node _T_1359 = eq(_T_1357, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1360 = and(_T_1351, _T_1359) @[Parameters.scala 132:56] + node _T_1362 = or(UInt<1>("h00"), _T_1360) @[Parameters.scala 134:30] + node _T_1363 = or(_T_1362, reset) @[RISCVPlatform.scala 23:61] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1365 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1366 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1368 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1370 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1371 = or(_T_1370, reset) @[RISCVPlatform.scala 23:61] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1373 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1374 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1376 = eq(_T_1374, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1376 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1378 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1379 = or(_T_1378, reset) @[RISCVPlatform.scala 23:61] + node _T_1381 = eq(_T_1379, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1381 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1383 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1384 = or(_T_1383, reset) @[RISCVPlatform.scala 23:61] + node _T_1386 = eq(_T_1384, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1386 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1388 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 23:61] + when _T_1388 : @[RISCVPlatform.scala 23:61] + node _T_1391 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1393 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1400 = and(_T_1391, _T_1399) @[Parameters.scala 132:56] + node _T_1402 = or(UInt<1>("h00"), _T_1400) @[Parameters.scala 134:30] + node _T_1403 = or(_T_1402, reset) @[RISCVPlatform.scala 23:61] + node _T_1405 = eq(_T_1403, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1405 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1406 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1408 = eq(_T_1406, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1408 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1410 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1411 = or(_T_1410, reset) @[RISCVPlatform.scala 23:61] + node _T_1413 = eq(_T_1411, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1413 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1414 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1416 = eq(_T_1414, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1416 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1418 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1419 = or(_T_1418, reset) @[RISCVPlatform.scala 23:61] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1421 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1423 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1424 = or(_T_1423, reset) @[RISCVPlatform.scala 23:61] + node _T_1426 = eq(_T_1424, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1426 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1428 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1428 : @[RISCVPlatform.scala 23:61] + node _T_1429 = or(_T_1291[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1431 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1432 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1434 = eq(_T_1432, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1434 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1435 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1437 = eq(_T_1435, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1437 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1439 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1440 = or(_T_1439, reset) @[RISCVPlatform.scala 23:61] + node _T_1442 = eq(_T_1440, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1442 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1444 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + when _T_1444 : @[RISCVPlatform.scala 23:61] + node _T_1445 = or(_T_1291[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1447 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1448 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1450 = eq(_T_1448, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1450 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1451 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1453 = eq(_T_1451, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1453 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1455 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1456 = or(_T_1455, reset) @[RISCVPlatform.scala 23:61] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1458 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1460 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:61] + when _T_1460 : @[RISCVPlatform.scala 23:61] + node _T_1461 = or(_T_1291[0], reset) @[RISCVPlatform.scala 23:61] + node _T_1463 = eq(_T_1461, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1463 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1464 = or(_T_1272, reset) @[RISCVPlatform.scala 23:61] + node _T_1466 = eq(_T_1464, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1466 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1467 = or(_T_1280, reset) @[RISCVPlatform.scala 23:61] + node _T_1469 = eq(_T_1467, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1469 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1471 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1472 = or(_T_1471, reset) @[RISCVPlatform.scala 23:61] + node _T_1474 = eq(_T_1472, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1474 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1476 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1477 = or(_T_1476, reset) @[RISCVPlatform.scala 23:61] + node _T_1479 = eq(_T_1477, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1479 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + when io.in[0].d.valid : @[RISCVPlatform.scala 23:61] + node _T_1481 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1482 = or(_T_1481, reset) @[RISCVPlatform.scala 23:61] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1484 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1486 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1487 = not(_T_1486) @[Parameters.scala 37:9] + node _T_1489 = or(_T_1487, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1490 = not(_T_1489) @[Parameters.scala 37:7] + node _T_1492 = eq(_T_1490, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1494 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1496 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1499 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1499 is invalid @[Parameters.scala 228:27] + _T_1499[0] <= _T_1492 @[Parameters.scala 228:27] + _T_1499[1] <= _T_1494 @[Parameters.scala 228:27] + _T_1499[2] <= _T_1496 @[Parameters.scala 228:27] + node _T_1505 = or(_T_1499[0], _T_1499[1]) @[Parameters.scala 229:46] + node _T_1506 = or(_T_1505, _T_1499[2]) @[Parameters.scala 229:46] + node _T_1508 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1509 = dshl(_T_1508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1510 = bits(_T_1509, 5, 0) @[package.scala 19:76] + node _T_1511 = not(_T_1510) @[package.scala 19:40] + node _T_1512 = and(io.in[0].d.bits.addr_lo, _T_1511) @[Edges.scala 17:16] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1516 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + node _T_1518 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:61] + when _T_1518 : @[RISCVPlatform.scala 23:61] + node _T_1519 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1521 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1522 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1524 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1525 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1527 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1529 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1530 = or(_T_1529, reset) @[RISCVPlatform.scala 23:61] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1532 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1534 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1535 = or(_T_1534, reset) @[RISCVPlatform.scala 23:61] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1537 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1539 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1540 = or(_T_1539, reset) @[RISCVPlatform.scala 23:61] + node _T_1542 = eq(_T_1540, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1542 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1544 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:61] + when _T_1544 : @[RISCVPlatform.scala 23:61] + node _T_1545 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1547 = eq(_T_1545, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1547 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1548 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1550 = eq(_T_1548, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1550 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1551 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1553 = eq(_T_1551, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1553 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1555 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1556 = or(_T_1555, reset) @[RISCVPlatform.scala 23:61] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1558 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1560 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1561 = or(_T_1560, reset) @[RISCVPlatform.scala 23:61] + node _T_1563 = eq(_T_1561, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1563 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1565 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:61] + when _T_1565 : @[RISCVPlatform.scala 23:61] + node _T_1566 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1568 = eq(_T_1566, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1568 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1569 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1571 = eq(_T_1569, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1571 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1572 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1574 = eq(_T_1572, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1574 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1576 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:61] + node _T_1577 = or(_T_1576, reset) @[RISCVPlatform.scala 23:61] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1579 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1581 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1582 = or(_T_1581, reset) @[RISCVPlatform.scala 23:61] + node _T_1584 = eq(_T_1582, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1584 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1586 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1586 : @[RISCVPlatform.scala 23:61] + node _T_1587 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1589 = eq(_T_1587, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1589 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1590 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1592 = eq(_T_1590, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1592 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1593 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1595 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1597 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1598 = or(_T_1597, reset) @[RISCVPlatform.scala 23:61] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1600 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1602 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + when _T_1602 : @[RISCVPlatform.scala 23:61] + node _T_1603 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1605 = eq(_T_1603, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1605 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1606 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1608 = eq(_T_1606, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1608 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1609 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1611 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1613 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1614 = or(_T_1613, reset) @[RISCVPlatform.scala 23:61] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1616 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1618 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:61] + when _T_1618 : @[RISCVPlatform.scala 23:61] + node _T_1619 = or(_T_1506, reset) @[RISCVPlatform.scala 23:61] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1621 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1622 = or(_T_1514, reset) @[RISCVPlatform.scala 23:61] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1624 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1625 = or(_T_1516, reset) @[RISCVPlatform.scala 23:61] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1627 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1629 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 23:61] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1632 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1634 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1635 = or(_T_1634, reset) @[RISCVPlatform.scala 23:61] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1637 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + when io.in[0].e.valid : @[RISCVPlatform.scala 23:61] + node _T_1639 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 23:61] + node _T_1640 = or(_T_1639, reset) @[RISCVPlatform.scala 23:61] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1642 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1643 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1645 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1646 = dshl(_T_1645, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1647 = bits(_T_1646, 5, 0) @[package.scala 19:76] + node _T_1648 = not(_T_1647) @[package.scala 19:40] + node _T_1649 = shr(_T_1648, 3) @[Edges.scala 198:59] + node _T_1650 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1652 = eq(_T_1650, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1654 = mux(_T_1652, _T_1649, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1656 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1658 = sub(_T_1656, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1659 = asUInt(_T_1658) @[Edges.scala 208:28] + node _T_1660 = tail(_T_1659, 1) @[Edges.scala 208:28] + node _T_1662 = eq(_T_1656, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1664 = eq(_T_1656, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1666 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1667 = or(_T_1664, _T_1666) @[Edges.scala 210:37] + node _T_1668 = and(_T_1667, _T_1643) @[Edges.scala 211:22] + node _T_1669 = not(_T_1660) @[Edges.scala 212:27] + node _T_1670 = and(_T_1654, _T_1669) @[Edges.scala 212:25] + when _T_1643 : @[Edges.scala 213:17] + node _T_1671 = mux(_T_1662, _T_1654, _T_1660) @[Edges.scala 214:21] + _T_1656 <= _T_1671 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1673 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1675 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1677 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1679 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1681 : UInt, clock @[RISCVPlatform.scala 23:61] + node _T_1683 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1684 = and(io.in[0].a.valid, _T_1683) @[RISCVPlatform.scala 23:61] + when _T_1684 : @[RISCVPlatform.scala 23:61] + node _T_1685 = eq(io.in[0].a.bits.opcode, _T_1673) @[RISCVPlatform.scala 23:61] + node _T_1686 = or(_T_1685, reset) @[RISCVPlatform.scala 23:61] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1688 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1689 = eq(io.in[0].a.bits.param, _T_1675) @[RISCVPlatform.scala 23:61] + node _T_1690 = or(_T_1689, reset) @[RISCVPlatform.scala 23:61] + node _T_1692 = eq(_T_1690, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1692 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1693 = eq(io.in[0].a.bits.size, _T_1677) @[RISCVPlatform.scala 23:61] + node _T_1694 = or(_T_1693, reset) @[RISCVPlatform.scala 23:61] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1696 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1697 = eq(io.in[0].a.bits.source, _T_1679) @[RISCVPlatform.scala 23:61] + node _T_1698 = or(_T_1697, reset) @[RISCVPlatform.scala 23:61] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1700 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1701 = eq(io.in[0].a.bits.address, _T_1681) @[RISCVPlatform.scala 23:61] + node _T_1702 = or(_T_1701, reset) @[RISCVPlatform.scala 23:61] + node _T_1704 = eq(_T_1702, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1704 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1705 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1706 = and(_T_1705, _T_1662) @[RISCVPlatform.scala 23:61] + when _T_1706 : @[RISCVPlatform.scala 23:61] + _T_1673 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 23:61] + _T_1675 <= io.in[0].a.bits.param @[RISCVPlatform.scala 23:61] + _T_1677 <= io.in[0].a.bits.size @[RISCVPlatform.scala 23:61] + _T_1679 <= io.in[0].a.bits.source @[RISCVPlatform.scala 23:61] + _T_1681 <= io.in[0].a.bits.address @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1707 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 5, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1719 = mux(UInt<1>("h00"), _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1721 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1723 = sub(_T_1721, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1724 = asUInt(_T_1723) @[Edges.scala 208:28] + node _T_1725 = tail(_T_1724, 1) @[Edges.scala 208:28] + node _T_1727 = eq(_T_1721, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1729 = eq(_T_1721, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1731 = eq(_T_1719, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1732 = or(_T_1729, _T_1731) @[Edges.scala 210:37] + node _T_1733 = and(_T_1732, _T_1707) @[Edges.scala 211:22] + node _T_1734 = not(_T_1725) @[Edges.scala 212:27] + node _T_1735 = and(_T_1719, _T_1734) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1736 = mux(_T_1727, _T_1719, _T_1725) @[Edges.scala 214:21] + _T_1721 <= _T_1736 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1738 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1740 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1742 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1744 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1746 : UInt, clock @[RISCVPlatform.scala 23:61] + node _T_1748 = eq(_T_1727, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1749 = and(io.in[0].b.valid, _T_1748) @[RISCVPlatform.scala 23:61] + when _T_1749 : @[RISCVPlatform.scala 23:61] + node _T_1750 = eq(io.in[0].b.bits.opcode, _T_1738) @[RISCVPlatform.scala 23:61] + node _T_1751 = or(_T_1750, reset) @[RISCVPlatform.scala 23:61] + node _T_1753 = eq(_T_1751, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1753 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1754 = eq(io.in[0].b.bits.param, _T_1740) @[RISCVPlatform.scala 23:61] + node _T_1755 = or(_T_1754, reset) @[RISCVPlatform.scala 23:61] + node _T_1757 = eq(_T_1755, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1757 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1758 = eq(io.in[0].b.bits.size, _T_1742) @[RISCVPlatform.scala 23:61] + node _T_1759 = or(_T_1758, reset) @[RISCVPlatform.scala 23:61] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1761 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1762 = eq(io.in[0].b.bits.source, _T_1744) @[RISCVPlatform.scala 23:61] + node _T_1763 = or(_T_1762, reset) @[RISCVPlatform.scala 23:61] + node _T_1765 = eq(_T_1763, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1765 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1766 = eq(io.in[0].b.bits.address, _T_1746) @[RISCVPlatform.scala 23:61] + node _T_1767 = or(_T_1766, reset) @[RISCVPlatform.scala 23:61] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1769 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1770 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1771 = and(_T_1770, _T_1727) @[RISCVPlatform.scala 23:61] + when _T_1771 : @[RISCVPlatform.scala 23:61] + _T_1738 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 23:61] + _T_1740 <= io.in[0].b.bits.param @[RISCVPlatform.scala 23:61] + _T_1742 <= io.in[0].b.bits.size @[RISCVPlatform.scala 23:61] + _T_1744 <= io.in[0].b.bits.source @[RISCVPlatform.scala 23:61] + _T_1746 <= io.in[0].b.bits.address @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1772 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1774 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1775 = dshl(_T_1774, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1776 = bits(_T_1775, 5, 0) @[package.scala 19:76] + node _T_1777 = not(_T_1776) @[package.scala 19:40] + node _T_1778 = shr(_T_1777, 3) @[Edges.scala 198:59] + node _T_1779 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1781 = mux(_T_1779, _T_1778, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1783 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1785 = sub(_T_1783, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1786 = asUInt(_T_1785) @[Edges.scala 208:28] + node _T_1787 = tail(_T_1786, 1) @[Edges.scala 208:28] + node _T_1789 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1791 = eq(_T_1783, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1793 = eq(_T_1781, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1794 = or(_T_1791, _T_1793) @[Edges.scala 210:37] + node _T_1795 = and(_T_1794, _T_1772) @[Edges.scala 211:22] + node _T_1796 = not(_T_1787) @[Edges.scala 212:27] + node _T_1797 = and(_T_1781, _T_1796) @[Edges.scala 212:25] + when _T_1772 : @[Edges.scala 213:17] + node _T_1798 = mux(_T_1789, _T_1781, _T_1787) @[Edges.scala 214:21] + _T_1783 <= _T_1798 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1800 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1802 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1804 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1806 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1808 : UInt, clock @[RISCVPlatform.scala 23:61] + node _T_1810 = eq(_T_1789, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1811 = and(io.in[0].c.valid, _T_1810) @[RISCVPlatform.scala 23:61] + when _T_1811 : @[RISCVPlatform.scala 23:61] + node _T_1812 = eq(io.in[0].c.bits.opcode, _T_1800) @[RISCVPlatform.scala 23:61] + node _T_1813 = or(_T_1812, reset) @[RISCVPlatform.scala 23:61] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1815 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1816 = eq(io.in[0].c.bits.param, _T_1802) @[RISCVPlatform.scala 23:61] + node _T_1817 = or(_T_1816, reset) @[RISCVPlatform.scala 23:61] + node _T_1819 = eq(_T_1817, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1819 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1820 = eq(io.in[0].c.bits.size, _T_1804) @[RISCVPlatform.scala 23:61] + node _T_1821 = or(_T_1820, reset) @[RISCVPlatform.scala 23:61] + node _T_1823 = eq(_T_1821, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1823 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1824 = eq(io.in[0].c.bits.source, _T_1806) @[RISCVPlatform.scala 23:61] + node _T_1825 = or(_T_1824, reset) @[RISCVPlatform.scala 23:61] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1827 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1828 = eq(io.in[0].c.bits.address, _T_1808) @[RISCVPlatform.scala 23:61] + node _T_1829 = or(_T_1828, reset) @[RISCVPlatform.scala 23:61] + node _T_1831 = eq(_T_1829, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1831 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1832 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1833 = and(_T_1832, _T_1789) @[RISCVPlatform.scala 23:61] + when _T_1833 : @[RISCVPlatform.scala 23:61] + _T_1800 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 23:61] + _T_1802 <= io.in[0].c.bits.param @[RISCVPlatform.scala 23:61] + _T_1804 <= io.in[0].c.bits.size @[RISCVPlatform.scala 23:61] + _T_1806 <= io.in[0].c.bits.source @[RISCVPlatform.scala 23:61] + _T_1808 <= io.in[0].c.bits.address @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1834 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1836 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1837 = dshl(_T_1836, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1838 = bits(_T_1837, 5, 0) @[package.scala 19:76] + node _T_1839 = not(_T_1838) @[package.scala 19:40] + node _T_1840 = shr(_T_1839, 3) @[Edges.scala 198:59] + node _T_1841 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1843 = mux(_T_1841, _T_1840, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1845 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1847 = sub(_T_1845, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1848 = asUInt(_T_1847) @[Edges.scala 208:28] + node _T_1849 = tail(_T_1848, 1) @[Edges.scala 208:28] + node _T_1851 = eq(_T_1845, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1853 = eq(_T_1845, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1855 = eq(_T_1843, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1856 = or(_T_1853, _T_1855) @[Edges.scala 210:37] + node _T_1857 = and(_T_1856, _T_1834) @[Edges.scala 211:22] + node _T_1858 = not(_T_1849) @[Edges.scala 212:27] + node _T_1859 = and(_T_1843, _T_1858) @[Edges.scala 212:25] + when _T_1834 : @[Edges.scala 213:17] + node _T_1860 = mux(_T_1851, _T_1843, _T_1849) @[Edges.scala 214:21] + _T_1845 <= _T_1860 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1862 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1864 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1866 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1868 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1870 : UInt, clock @[RISCVPlatform.scala 23:61] + reg _T_1872 : UInt, clock @[RISCVPlatform.scala 23:61] + node _T_1874 = eq(_T_1851, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1875 = and(io.in[0].d.valid, _T_1874) @[RISCVPlatform.scala 23:61] + when _T_1875 : @[RISCVPlatform.scala 23:61] + node _T_1876 = eq(io.in[0].d.bits.opcode, _T_1862) @[RISCVPlatform.scala 23:61] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 23:61] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1879 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1880 = eq(io.in[0].d.bits.param, _T_1864) @[RISCVPlatform.scala 23:61] + node _T_1881 = or(_T_1880, reset) @[RISCVPlatform.scala 23:61] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1883 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1884 = eq(io.in[0].d.bits.size, _T_1866) @[RISCVPlatform.scala 23:61] + node _T_1885 = or(_T_1884, reset) @[RISCVPlatform.scala 23:61] + node _T_1887 = eq(_T_1885, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1887 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1888 = eq(io.in[0].d.bits.source, _T_1868) @[RISCVPlatform.scala 23:61] + node _T_1889 = or(_T_1888, reset) @[RISCVPlatform.scala 23:61] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1891 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1892 = eq(io.in[0].d.bits.sink, _T_1870) @[RISCVPlatform.scala 23:61] + node _T_1893 = or(_T_1892, reset) @[RISCVPlatform.scala 23:61] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1895 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1896 = eq(io.in[0].d.bits.addr_lo, _T_1872) @[RISCVPlatform.scala 23:61] + node _T_1897 = or(_T_1896, reset) @[RISCVPlatform.scala 23:61] + node _T_1899 = eq(_T_1897, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1899 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1900 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = and(_T_1900, _T_1851) @[RISCVPlatform.scala 23:61] + when _T_1901 : @[RISCVPlatform.scala 23:61] + _T_1862 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 23:61] + _T_1864 <= io.in[0].d.bits.param @[RISCVPlatform.scala 23:61] + _T_1866 <= io.in[0].d.bits.size @[RISCVPlatform.scala 23:61] + _T_1868 <= io.in[0].d.bits.source @[RISCVPlatform.scala 23:61] + _T_1870 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 23:61] + _T_1872 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + reg _T_1903 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_1904 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1906 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1907 = dshl(_T_1906, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1908 = bits(_T_1907, 5, 0) @[package.scala 19:76] + node _T_1909 = not(_T_1908) @[package.scala 19:40] + node _T_1910 = shr(_T_1909, 3) @[Edges.scala 198:59] + node _T_1911 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1915 = mux(_T_1913, _T_1910, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1917 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1919 = sub(_T_1917, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1920 = asUInt(_T_1919) @[Edges.scala 208:28] + node _T_1921 = tail(_T_1920, 1) @[Edges.scala 208:28] + node _T_1923 = eq(_T_1917, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1925 = eq(_T_1917, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1927 = eq(_T_1915, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1928 = or(_T_1925, _T_1927) @[Edges.scala 210:37] + node _T_1929 = and(_T_1928, _T_1904) @[Edges.scala 211:22] + node _T_1930 = not(_T_1921) @[Edges.scala 212:27] + node _T_1931 = and(_T_1915, _T_1930) @[Edges.scala 212:25] + when _T_1904 : @[Edges.scala 213:17] + node _T_1932 = mux(_T_1923, _T_1915, _T_1921) @[Edges.scala 214:21] + _T_1917 <= _T_1932 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1933 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1935 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1936 = dshl(_T_1935, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1937 = bits(_T_1936, 5, 0) @[package.scala 19:76] + node _T_1938 = not(_T_1937) @[package.scala 19:40] + node _T_1939 = shr(_T_1938, 3) @[Edges.scala 198:59] + node _T_1940 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1942 = mux(_T_1940, _T_1939, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1944 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1946 = sub(_T_1944, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1947 = asUInt(_T_1946) @[Edges.scala 208:28] + node _T_1948 = tail(_T_1947, 1) @[Edges.scala 208:28] + node _T_1950 = eq(_T_1944, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1952 = eq(_T_1944, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1954 = eq(_T_1942, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1955 = or(_T_1952, _T_1954) @[Edges.scala 210:37] + node _T_1956 = and(_T_1955, _T_1933) @[Edges.scala 211:22] + node _T_1957 = not(_T_1948) @[Edges.scala 212:27] + node _T_1958 = and(_T_1942, _T_1957) @[Edges.scala 212:25] + when _T_1933 : @[Edges.scala 213:17] + node _T_1959 = mux(_T_1950, _T_1942, _T_1948) @[Edges.scala 214:21] + _T_1944 <= _T_1959 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_1961 : UInt<6> + _T_1961 is invalid + _T_1961 <= UInt<6>("h00") + node _T_1962 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_1962 : @[RISCVPlatform.scala 23:61] + when _T_1928 : @[RISCVPlatform.scala 23:61] + node _T_1964 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_1961 <= _T_1964 @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1965 = dshr(_T_1903, io.in[0].a.bits.source) @[RISCVPlatform.scala 23:61] + node _T_1966 = bits(_T_1965, 0, 0) @[RISCVPlatform.scala 23:61] + node _T_1968 = eq(_T_1966, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + node _T_1969 = or(_T_1968, reset) @[RISCVPlatform.scala 23:61] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1971 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + wire _T_1973 : UInt<6> + _T_1973 is invalid + _T_1973 <= UInt<6>("h00") + node _T_1974 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1976 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:61] + node _T_1977 = and(_T_1974, _T_1976) @[RISCVPlatform.scala 23:61] + when _T_1977 : @[RISCVPlatform.scala 23:61] + when _T_1955 : @[RISCVPlatform.scala 23:61] + node _T_1979 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_1973 <= _T_1979 @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1980 = or(_T_1961, _T_1903) @[RISCVPlatform.scala 23:61] + node _T_1981 = dshr(_T_1980, io.in[0].d.bits.source) @[RISCVPlatform.scala 23:61] + node _T_1982 = bits(_T_1981, 0, 0) @[RISCVPlatform.scala 23:61] + node _T_1983 = or(_T_1982, reset) @[RISCVPlatform.scala 23:61] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[RISCVPlatform.scala 23:61] + when _T_1985 : @[RISCVPlatform.scala 23:61] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:23:61)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 23:61] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + skip @[RISCVPlatform.scala 23:61] + node _T_1986 = or(_T_1903, _T_1961) @[RISCVPlatform.scala 23:61] + node _T_1987 = not(_T_1973) @[RISCVPlatform.scala 23:61] + node _T_1988 = and(_T_1986, _T_1987) @[RISCVPlatform.scala 23:61] + _T_1903 <= _T_1988 @[RISCVPlatform.scala 23:61] + + module TLMonitor_30 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RISCVPlatform.scala 23:14] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RISCVPlatform.scala 23:14] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_608 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = xor(UInt<6>("h028"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_619 = not(_T_618) @[Parameters.scala 37:9] + node _T_621 = or(_T_619, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_622 = not(_T_621) @[Parameters.scala 37:7] + node _T_624 = eq(_T_622, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_626 = xor(UInt<6>("h020"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_627 = not(_T_626) @[Parameters.scala 37:9] + node _T_629 = or(_T_627, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_630 = not(_T_629) @[Parameters.scala 37:7] + node _T_632 = eq(_T_630, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_635 : UInt<1>[3] @[Parameters.scala 228:27] + _T_635 is invalid @[Parameters.scala 228:27] + _T_635[0] <= _T_616 @[Parameters.scala 228:27] + _T_635[1] <= _T_624 @[Parameters.scala 228:27] + _T_635[2] <= _T_632 @[Parameters.scala 228:27] + node _T_641 = or(_T_635[0], _T_635[1]) @[Parameters.scala 229:46] + node _T_642 = or(_T_641, _T_635[2]) @[Parameters.scala 229:46] + node _T_644 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_645 = dshl(_T_644, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_646 = bits(_T_645, 5, 0) @[package.scala 19:76] + node _T_647 = not(_T_646) @[package.scala 19:40] + node _T_648 = and(io.in[0].a.bits.address, _T_647) @[Edges.scala 17:16] + node _T_650 = eq(_T_648, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_652 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_653 = dshl(UInt<1>("h01"), _T_652) @[OneHot.scala 49:12] + node _T_654 = bits(_T_653, 2, 0) @[OneHot.scala 49:37] + node _T_656 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_658 = bits(_T_654, 2, 2) @[package.scala 44:26] + node _T_659 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_661 = eq(_T_659, UInt<1>("h00")) @[package.scala 46:20] + node _T_662 = and(UInt<1>("h01"), _T_661) @[package.scala 49:27] + node _T_663 = and(_T_658, _T_662) @[package.scala 50:38] + node _T_664 = or(_T_656, _T_663) @[package.scala 50:29] + node _T_665 = and(UInt<1>("h01"), _T_659) @[package.scala 49:27] + node _T_666 = and(_T_658, _T_665) @[package.scala 50:38] + node _T_667 = or(_T_656, _T_666) @[package.scala 50:29] + node _T_668 = bits(_T_654, 1, 1) @[package.scala 44:26] + node _T_669 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_671 = eq(_T_669, UInt<1>("h00")) @[package.scala 46:20] + node _T_672 = and(_T_662, _T_671) @[package.scala 49:27] + node _T_673 = and(_T_668, _T_672) @[package.scala 50:38] + node _T_674 = or(_T_664, _T_673) @[package.scala 50:29] + node _T_675 = and(_T_662, _T_669) @[package.scala 49:27] + node _T_676 = and(_T_668, _T_675) @[package.scala 50:38] + node _T_677 = or(_T_664, _T_676) @[package.scala 50:29] + node _T_678 = and(_T_665, _T_671) @[package.scala 49:27] + node _T_679 = and(_T_668, _T_678) @[package.scala 50:38] + node _T_680 = or(_T_667, _T_679) @[package.scala 50:29] + node _T_681 = and(_T_665, _T_669) @[package.scala 49:27] + node _T_682 = and(_T_668, _T_681) @[package.scala 50:38] + node _T_683 = or(_T_667, _T_682) @[package.scala 50:29] + node _T_684 = bits(_T_654, 0, 0) @[package.scala 44:26] + node _T_685 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_687 = eq(_T_685, UInt<1>("h00")) @[package.scala 46:20] + node _T_688 = and(_T_672, _T_687) @[package.scala 49:27] + node _T_689 = and(_T_684, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_674, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_672, _T_685) @[package.scala 49:27] + node _T_692 = and(_T_684, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_674, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_675, _T_687) @[package.scala 49:27] + node _T_695 = and(_T_684, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_677, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_675, _T_685) @[package.scala 49:27] + node _T_698 = and(_T_684, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_677, _T_698) @[package.scala 50:29] + node _T_700 = and(_T_678, _T_687) @[package.scala 49:27] + node _T_701 = and(_T_684, _T_700) @[package.scala 50:38] + node _T_702 = or(_T_680, _T_701) @[package.scala 50:29] + node _T_703 = and(_T_678, _T_685) @[package.scala 49:27] + node _T_704 = and(_T_684, _T_703) @[package.scala 50:38] + node _T_705 = or(_T_680, _T_704) @[package.scala 50:29] + node _T_706 = and(_T_681, _T_687) @[package.scala 49:27] + node _T_707 = and(_T_684, _T_706) @[package.scala 50:38] + node _T_708 = or(_T_683, _T_707) @[package.scala 50:29] + node _T_709 = and(_T_681, _T_685) @[package.scala 49:27] + node _T_710 = and(_T_684, _T_709) @[package.scala 50:38] + node _T_711 = or(_T_683, _T_710) @[package.scala 50:29] + node _T_712 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_713 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_714 = cat(_T_713, _T_712) @[Cat.scala 30:58] + node _T_715 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_716 = cat(_T_711, _T_708) @[Cat.scala 30:58] + node _T_717 = cat(_T_716, _T_715) @[Cat.scala 30:58] + node _T_718 = cat(_T_717, _T_714) @[Cat.scala 30:58] + node _T_720 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:14] + when _T_720 : @[RISCVPlatform.scala 23:14] + node _T_723 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_725 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_726 = cvt(_T_725) @[Parameters.scala 117:49] + node _T_728 = and(_T_726, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_729 = asSInt(_T_728) @[Parameters.scala 117:52] + node _T_731 = eq(_T_729, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_732 = and(_T_723, _T_731) @[Parameters.scala 132:56] + node _T_734 = or(UInt<1>("h00"), _T_732) @[Parameters.scala 134:30] + node _T_735 = or(_T_734, reset) @[RISCVPlatform.scala 23:14] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_737 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_738 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_740 = eq(_T_738, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_740 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_742 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_743 = or(_T_742, reset) @[RISCVPlatform.scala 23:14] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_745 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_746 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_748 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_750 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_751 = or(_T_750, reset) @[RISCVPlatform.scala 23:14] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_753 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_754 = not(io.in[0].a.bits.mask) @[RISCVPlatform.scala 23:14] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_757 = or(_T_756, reset) @[RISCVPlatform.scala 23:14] + node _T_759 = eq(_T_757, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_759 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_761 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:14] + when _T_761 : @[RISCVPlatform.scala 23:14] + node _T_764 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_766 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_767 = and(_T_764, _T_766) @[Parameters.scala 63:37] + node _T_768 = or(UInt<1>("h00"), _T_767) @[Parameters.scala 132:31] + node _T_770 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_771 = cvt(_T_770) @[Parameters.scala 117:49] + node _T_773 = and(_T_771, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_774 = asSInt(_T_773) @[Parameters.scala 117:52] + node _T_776 = eq(_T_774, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_777 = and(_T_768, _T_776) @[Parameters.scala 132:56] + node _T_779 = or(UInt<1>("h00"), _T_777) @[Parameters.scala 134:30] + node _T_780 = or(_T_779, reset) @[RISCVPlatform.scala 23:14] + node _T_782 = eq(_T_780, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_782 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_783 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_785 = eq(_T_783, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_785 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_786 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_788 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_790 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_791 = or(_T_790, reset) @[RISCVPlatform.scala 23:14] + node _T_793 = eq(_T_791, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_793 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_794 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 23:14] + node _T_795 = or(_T_794, reset) @[RISCVPlatform.scala 23:14] + node _T_797 = eq(_T_795, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_797 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_799 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_799 : @[RISCVPlatform.scala 23:14] + node _T_802 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_804 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_805 = and(_T_802, _T_804) @[Parameters.scala 63:37] + node _T_806 = or(UInt<1>("h00"), _T_805) @[Parameters.scala 132:31] + node _T_808 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_809 = cvt(_T_808) @[Parameters.scala 117:49] + node _T_811 = and(_T_809, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_812 = asSInt(_T_811) @[Parameters.scala 117:52] + node _T_814 = eq(_T_812, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_815 = and(_T_806, _T_814) @[Parameters.scala 132:56] + node _T_817 = or(UInt<1>("h00"), _T_815) @[Parameters.scala 134:30] + node _T_818 = or(_T_817, reset) @[RISCVPlatform.scala 23:14] + node _T_820 = eq(_T_818, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_820 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_821 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_823 = eq(_T_821, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_823 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_824 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_826 = eq(_T_824, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_826 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_828 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_829 = or(_T_828, reset) @[RISCVPlatform.scala 23:14] + node _T_831 = eq(_T_829, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_831 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_832 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 23:14] + node _T_833 = or(_T_832, reset) @[RISCVPlatform.scala 23:14] + node _T_835 = eq(_T_833, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_835 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_837 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + when _T_837 : @[RISCVPlatform.scala 23:14] + node _T_840 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_842 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_843 = and(_T_840, _T_842) @[Parameters.scala 63:37] + node _T_844 = or(UInt<1>("h00"), _T_843) @[Parameters.scala 132:31] + node _T_846 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_847 = cvt(_T_846) @[Parameters.scala 117:49] + node _T_849 = and(_T_847, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_850 = asSInt(_T_849) @[Parameters.scala 117:52] + node _T_852 = eq(_T_850, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_853 = and(_T_844, _T_852) @[Parameters.scala 132:56] + node _T_855 = or(UInt<1>("h00"), _T_853) @[Parameters.scala 134:30] + node _T_856 = or(_T_855, reset) @[RISCVPlatform.scala 23:14] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_858 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_859 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_861 = eq(_T_859, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_861 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_862 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_864 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_866 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_867 = or(_T_866, reset) @[RISCVPlatform.scala 23:14] + node _T_869 = eq(_T_867, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_869 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_870 = not(_T_718) @[RISCVPlatform.scala 23:14] + node _T_871 = and(io.in[0].a.bits.mask, _T_870) @[RISCVPlatform.scala 23:14] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_874 = or(_T_873, reset) @[RISCVPlatform.scala 23:14] + node _T_876 = eq(_T_874, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_876 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_878 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:14] + when _T_878 : @[RISCVPlatform.scala 23:14] + node _T_881 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_883 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_884 = cvt(_T_883) @[Parameters.scala 117:49] + node _T_886 = and(_T_884, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_887 = asSInt(_T_886) @[Parameters.scala 117:52] + node _T_889 = eq(_T_887, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_890 = and(_T_881, _T_889) @[Parameters.scala 132:56] + node _T_892 = or(UInt<1>("h00"), _T_890) @[Parameters.scala 134:30] + node _T_893 = or(_T_892, reset) @[RISCVPlatform.scala 23:14] + node _T_895 = eq(_T_893, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_895 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_896 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_898 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_899 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_901 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_903 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_904 = or(_T_903, reset) @[RISCVPlatform.scala 23:14] + node _T_906 = eq(_T_904, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_906 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_907 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 23:14] + node _T_908 = or(_T_907, reset) @[RISCVPlatform.scala 23:14] + node _T_910 = eq(_T_908, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_910 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_912 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + when _T_912 : @[RISCVPlatform.scala 23:14] + node _T_915 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_917 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_918 = cvt(_T_917) @[Parameters.scala 117:49] + node _T_920 = and(_T_918, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_921 = asSInt(_T_920) @[Parameters.scala 117:52] + node _T_923 = eq(_T_921, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_924 = and(_T_915, _T_923) @[Parameters.scala 132:56] + node _T_926 = or(UInt<1>("h00"), _T_924) @[Parameters.scala 134:30] + node _T_927 = or(_T_926, reset) @[RISCVPlatform.scala 23:14] + node _T_929 = eq(_T_927, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_929 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_930 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_932 = eq(_T_930, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_932 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_933 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_935 = eq(_T_933, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_935 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_937 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_938 = or(_T_937, reset) @[RISCVPlatform.scala 23:14] + node _T_940 = eq(_T_938, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_940 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_941 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 23:14] + node _T_942 = or(_T_941, reset) @[RISCVPlatform.scala 23:14] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_944 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_946 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:14] + when _T_946 : @[RISCVPlatform.scala 23:14] + node _T_949 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_951 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_952 = cvt(_T_951) @[Parameters.scala 117:49] + node _T_954 = and(_T_952, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_955 = asSInt(_T_954) @[Parameters.scala 117:52] + node _T_957 = eq(_T_955, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_958 = and(_T_949, _T_957) @[Parameters.scala 132:56] + node _T_960 = or(UInt<1>("h00"), _T_958) @[Parameters.scala 134:30] + node _T_961 = or(_T_960, reset) @[RISCVPlatform.scala 23:14] + node _T_963 = eq(_T_961, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_963 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_964 = or(_T_642, reset) @[RISCVPlatform.scala 23:14] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_966 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_967 = or(_T_650, reset) @[RISCVPlatform.scala 23:14] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_969 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_970 = eq(io.in[0].a.bits.mask, _T_718) @[RISCVPlatform.scala 23:14] + node _T_971 = or(_T_970, reset) @[RISCVPlatform.scala 23:14] + node _T_973 = eq(_T_971, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_973 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + when io.in[0].b.valid : @[RISCVPlatform.scala 23:14] + node _T_975 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_976 = or(_T_975, reset) @[RISCVPlatform.scala 23:14] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_978 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_980 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_981 = cvt(_T_980) @[Parameters.scala 117:49] + node _T_983 = and(_T_981, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_984 = asSInt(_T_983) @[Parameters.scala 117:52] + node _T_986 = eq(_T_984, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_989 : UInt<1>[1] @[Parameters.scala 110:36] + _T_989 is invalid @[Parameters.scala 110:36] + _T_989[0] <= _T_986 @[Parameters.scala 110:36] + node _T_994 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_995 = dshl(_T_994, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_996 = bits(_T_995, 5, 0) @[package.scala 19:76] + node _T_997 = not(_T_996) @[package.scala 19:40] + node _T_998 = and(io.in[0].b.bits.address, _T_997) @[Edges.scala 17:16] + node _T_1000 = eq(_T_998, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1002 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1003 = dshl(UInt<1>("h01"), _T_1002) @[OneHot.scala 49:12] + node _T_1004 = bits(_T_1003, 2, 0) @[OneHot.scala 49:37] + node _T_1006 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1008 = bits(_T_1004, 2, 2) @[package.scala 44:26] + node _T_1009 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1011 = eq(_T_1009, UInt<1>("h00")) @[package.scala 46:20] + node _T_1012 = and(UInt<1>("h01"), _T_1011) @[package.scala 49:27] + node _T_1013 = and(_T_1008, _T_1012) @[package.scala 50:38] + node _T_1014 = or(_T_1006, _T_1013) @[package.scala 50:29] + node _T_1015 = and(UInt<1>("h01"), _T_1009) @[package.scala 49:27] + node _T_1016 = and(_T_1008, _T_1015) @[package.scala 50:38] + node _T_1017 = or(_T_1006, _T_1016) @[package.scala 50:29] + node _T_1018 = bits(_T_1004, 1, 1) @[package.scala 44:26] + node _T_1019 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1021 = eq(_T_1019, UInt<1>("h00")) @[package.scala 46:20] + node _T_1022 = and(_T_1012, _T_1021) @[package.scala 49:27] + node _T_1023 = and(_T_1018, _T_1022) @[package.scala 50:38] + node _T_1024 = or(_T_1014, _T_1023) @[package.scala 50:29] + node _T_1025 = and(_T_1012, _T_1019) @[package.scala 49:27] + node _T_1026 = and(_T_1018, _T_1025) @[package.scala 50:38] + node _T_1027 = or(_T_1014, _T_1026) @[package.scala 50:29] + node _T_1028 = and(_T_1015, _T_1021) @[package.scala 49:27] + node _T_1029 = and(_T_1018, _T_1028) @[package.scala 50:38] + node _T_1030 = or(_T_1017, _T_1029) @[package.scala 50:29] + node _T_1031 = and(_T_1015, _T_1019) @[package.scala 49:27] + node _T_1032 = and(_T_1018, _T_1031) @[package.scala 50:38] + node _T_1033 = or(_T_1017, _T_1032) @[package.scala 50:29] + node _T_1034 = bits(_T_1004, 0, 0) @[package.scala 44:26] + node _T_1035 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1037 = eq(_T_1035, UInt<1>("h00")) @[package.scala 46:20] + node _T_1038 = and(_T_1022, _T_1037) @[package.scala 49:27] + node _T_1039 = and(_T_1034, _T_1038) @[package.scala 50:38] + node _T_1040 = or(_T_1024, _T_1039) @[package.scala 50:29] + node _T_1041 = and(_T_1022, _T_1035) @[package.scala 49:27] + node _T_1042 = and(_T_1034, _T_1041) @[package.scala 50:38] + node _T_1043 = or(_T_1024, _T_1042) @[package.scala 50:29] + node _T_1044 = and(_T_1025, _T_1037) @[package.scala 49:27] + node _T_1045 = and(_T_1034, _T_1044) @[package.scala 50:38] + node _T_1046 = or(_T_1027, _T_1045) @[package.scala 50:29] + node _T_1047 = and(_T_1025, _T_1035) @[package.scala 49:27] + node _T_1048 = and(_T_1034, _T_1047) @[package.scala 50:38] + node _T_1049 = or(_T_1027, _T_1048) @[package.scala 50:29] + node _T_1050 = and(_T_1028, _T_1037) @[package.scala 49:27] + node _T_1051 = and(_T_1034, _T_1050) @[package.scala 50:38] + node _T_1052 = or(_T_1030, _T_1051) @[package.scala 50:29] + node _T_1053 = and(_T_1028, _T_1035) @[package.scala 49:27] + node _T_1054 = and(_T_1034, _T_1053) @[package.scala 50:38] + node _T_1055 = or(_T_1030, _T_1054) @[package.scala 50:29] + node _T_1056 = and(_T_1031, _T_1037) @[package.scala 49:27] + node _T_1057 = and(_T_1034, _T_1056) @[package.scala 50:38] + node _T_1058 = or(_T_1033, _T_1057) @[package.scala 50:29] + node _T_1059 = and(_T_1031, _T_1035) @[package.scala 49:27] + node _T_1060 = and(_T_1034, _T_1059) @[package.scala 50:38] + node _T_1061 = or(_T_1033, _T_1060) @[package.scala 50:29] + node _T_1062 = cat(_T_1043, _T_1040) @[Cat.scala 30:58] + node _T_1063 = cat(_T_1049, _T_1046) @[Cat.scala 30:58] + node _T_1064 = cat(_T_1063, _T_1062) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1055, _T_1052) @[Cat.scala 30:58] + node _T_1066 = cat(_T_1061, _T_1058) @[Cat.scala 30:58] + node _T_1067 = cat(_T_1066, _T_1065) @[Cat.scala 30:58] + node _T_1068 = cat(_T_1067, _T_1064) @[Cat.scala 30:58] + node _T_1070 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:14] + when _T_1070 : @[RISCVPlatform.scala 23:14] + node _T_1072 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1073 = not(_T_1072) @[Parameters.scala 37:9] + node _T_1075 = or(_T_1073, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1076 = not(_T_1075) @[Parameters.scala 37:7] + node _T_1078 = eq(_T_1076, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1080 = xor(UInt<6>("h028"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1081 = not(_T_1080) @[Parameters.scala 37:9] + node _T_1083 = or(_T_1081, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1084 = not(_T_1083) @[Parameters.scala 37:7] + node _T_1086 = eq(_T_1084, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1088 = xor(UInt<6>("h020"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1089 = not(_T_1088) @[Parameters.scala 37:9] + node _T_1091 = or(_T_1089, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1092 = not(_T_1091) @[Parameters.scala 37:7] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1097 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1097 is invalid @[Parameters.scala 228:27] + _T_1097[0] <= _T_1078 @[Parameters.scala 228:27] + _T_1097[1] <= _T_1086 @[Parameters.scala 228:27] + _T_1097[2] <= _T_1094 @[Parameters.scala 228:27] + node _T_1105 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1107 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1108 = and(_T_1105, _T_1107) @[Parameters.scala 63:37] + node _T_1111 = mux(_T_1097[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1113 = mux(_T_1097[1], _T_1108, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1115 = mux(_T_1097[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1117 = or(_T_1111, _T_1113) @[Mux.scala 19:72] + node _T_1118 = or(_T_1117, _T_1115) @[Mux.scala 19:72] + wire _T_1120 : UInt<1> @[Mux.scala 19:72] + _T_1120 is invalid @[Mux.scala 19:72] + _T_1120 <= _T_1118 @[Mux.scala 19:72] + node _T_1121 = or(_T_1120, reset) @[RISCVPlatform.scala 23:14] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1123 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1124 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1126 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1128 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1129 = or(_T_1128, reset) @[RISCVPlatform.scala 23:14] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1131 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1132 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1134 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1136 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1137 = or(_T_1136, reset) @[RISCVPlatform.scala 23:14] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1139 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1140 = not(io.in[0].b.bits.mask) @[RISCVPlatform.scala 23:14] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1143 = or(_T_1142, reset) @[RISCVPlatform.scala 23:14] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1145 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:14] + when _T_1147 : @[RISCVPlatform.scala 23:14] + node _T_1149 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1151 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1152 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1154 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1155 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1157 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1159 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1160 = or(_T_1159, reset) @[RISCVPlatform.scala 23:14] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1162 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1163 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 23:14] + node _T_1164 = or(_T_1163, reset) @[RISCVPlatform.scala 23:14] + node _T_1166 = eq(_T_1164, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1166 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1168 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1168 : @[RISCVPlatform.scala 23:14] + node _T_1170 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1172 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1173 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1175 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1176 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1178 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1180 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1181 = or(_T_1180, reset) @[RISCVPlatform.scala 23:14] + node _T_1183 = eq(_T_1181, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1183 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1184 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 23:14] + node _T_1185 = or(_T_1184, reset) @[RISCVPlatform.scala 23:14] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1187 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1189 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + when _T_1189 : @[RISCVPlatform.scala 23:14] + node _T_1191 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1193 = eq(_T_1191, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1193 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1194 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1196 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1197 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1199 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1201 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1202 = or(_T_1201, reset) @[RISCVPlatform.scala 23:14] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1204 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1205 = not(_T_1068) @[RISCVPlatform.scala 23:14] + node _T_1206 = and(io.in[0].b.bits.mask, _T_1205) @[RISCVPlatform.scala 23:14] + node _T_1208 = eq(_T_1206, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1209 = or(_T_1208, reset) @[RISCVPlatform.scala 23:14] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1211 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1213 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:14] + when _T_1213 : @[RISCVPlatform.scala 23:14] + node _T_1215 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1217 = eq(_T_1215, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1217 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1218 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1220 = eq(_T_1218, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1220 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1221 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1223 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1225 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1226 = or(_T_1225, reset) @[RISCVPlatform.scala 23:14] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1228 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1229 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 23:14] + node _T_1230 = or(_T_1229, reset) @[RISCVPlatform.scala 23:14] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1232 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1234 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + when _T_1234 : @[RISCVPlatform.scala 23:14] + node _T_1236 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1238 = eq(_T_1236, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1238 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1239 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1241 = eq(_T_1239, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1241 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1242 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1244 = eq(_T_1242, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1244 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1246 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1247 = or(_T_1246, reset) @[RISCVPlatform.scala 23:14] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1249 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1250 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 23:14] + node _T_1251 = or(_T_1250, reset) @[RISCVPlatform.scala 23:14] + node _T_1253 = eq(_T_1251, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1253 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1255 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:14] + when _T_1255 : @[RISCVPlatform.scala 23:14] + node _T_1257 = or(UInt<1>("h00"), reset) @[RISCVPlatform.scala 23:14] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1259 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1260 = or(_T_989[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1262 = eq(_T_1260, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1262 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1263 = or(_T_1000, reset) @[RISCVPlatform.scala 23:14] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1265 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1266 = eq(io.in[0].b.bits.mask, _T_1068) @[RISCVPlatform.scala 23:14] + node _T_1267 = or(_T_1266, reset) @[RISCVPlatform.scala 23:14] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1269 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + when io.in[0].c.valid : @[RISCVPlatform.scala 23:14] + node _T_1271 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1272 = or(_T_1271, reset) @[RISCVPlatform.scala 23:14] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1274 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1276 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1277 = not(_T_1276) @[Parameters.scala 37:9] + node _T_1279 = or(_T_1277, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1280 = not(_T_1279) @[Parameters.scala 37:7] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1284 = xor(UInt<6>("h028"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1285 = not(_T_1284) @[Parameters.scala 37:9] + node _T_1287 = or(_T_1285, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1288 = not(_T_1287) @[Parameters.scala 37:7] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1292 = xor(UInt<6>("h020"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1293 = not(_T_1292) @[Parameters.scala 37:9] + node _T_1295 = or(_T_1293, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1296 = not(_T_1295) @[Parameters.scala 37:7] + node _T_1298 = eq(_T_1296, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1301 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1301 is invalid @[Parameters.scala 228:27] + _T_1301[0] <= _T_1282 @[Parameters.scala 228:27] + _T_1301[1] <= _T_1290 @[Parameters.scala 228:27] + _T_1301[2] <= _T_1298 @[Parameters.scala 228:27] + node _T_1307 = or(_T_1301[0], _T_1301[1]) @[Parameters.scala 229:46] + node _T_1308 = or(_T_1307, _T_1301[2]) @[Parameters.scala 229:46] + node _T_1310 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1311 = dshl(_T_1310, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1312 = bits(_T_1311, 5, 0) @[package.scala 19:76] + node _T_1313 = not(_T_1312) @[package.scala 19:40] + node _T_1314 = and(io.in[0].c.bits.address, _T_1313) @[Edges.scala 17:16] + node _T_1316 = eq(_T_1314, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1318 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1319 = cvt(_T_1318) @[Parameters.scala 117:49] + node _T_1321 = and(_T_1319, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1322 = asSInt(_T_1321) @[Parameters.scala 117:52] + node _T_1324 = eq(_T_1322, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1327 : UInt<1>[1] @[Parameters.scala 110:36] + _T_1327 is invalid @[Parameters.scala 110:36] + _T_1327[0] <= _T_1324 @[Parameters.scala 110:36] + node _T_1332 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:14] + when _T_1332 : @[RISCVPlatform.scala 23:14] + node _T_1333 = or(_T_1327[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1335 = eq(_T_1333, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1335 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1336 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1338 = eq(_T_1336, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1338 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1340 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1341 = or(_T_1340, reset) @[RISCVPlatform.scala 23:14] + node _T_1343 = eq(_T_1341, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1343 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1344 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1346 = eq(_T_1344, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1346 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1348 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1349 = or(_T_1348, reset) @[RISCVPlatform.scala 23:14] + node _T_1351 = eq(_T_1349, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1351 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1353 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1354 = or(_T_1353, reset) @[RISCVPlatform.scala 23:14] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1356 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1358 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:14] + when _T_1358 : @[RISCVPlatform.scala 23:14] + node _T_1359 = or(_T_1327[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1361 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1362 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1364 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1366 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1367 = or(_T_1366, reset) @[RISCVPlatform.scala 23:14] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1369 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1370 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1372 = eq(_T_1370, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1372 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1374 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1375 = or(_T_1374, reset) @[RISCVPlatform.scala 23:14] + node _T_1377 = eq(_T_1375, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1377 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1379 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1380 = or(_T_1379, reset) @[RISCVPlatform.scala 23:14] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1382 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1384 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:14] + when _T_1384 : @[RISCVPlatform.scala 23:14] + node _T_1387 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1389 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1390 = cvt(_T_1389) @[Parameters.scala 117:49] + node _T_1392 = and(_T_1390, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1393 = asSInt(_T_1392) @[Parameters.scala 117:52] + node _T_1395 = eq(_T_1393, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1396 = and(_T_1387, _T_1395) @[Parameters.scala 132:56] + node _T_1398 = or(UInt<1>("h00"), _T_1396) @[Parameters.scala 134:30] + node _T_1399 = or(_T_1398, reset) @[RISCVPlatform.scala 23:14] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1401 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1402 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1404 = eq(_T_1402, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1404 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1406 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1407 = or(_T_1406, reset) @[RISCVPlatform.scala 23:14] + node _T_1409 = eq(_T_1407, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1409 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1410 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1412 = eq(_T_1410, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1412 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1414 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1415 = or(_T_1414, reset) @[RISCVPlatform.scala 23:14] + node _T_1417 = eq(_T_1415, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1417 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1419 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1420 = or(_T_1419, reset) @[RISCVPlatform.scala 23:14] + node _T_1422 = eq(_T_1420, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1422 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1424 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RISCVPlatform.scala 23:14] + when _T_1424 : @[RISCVPlatform.scala 23:14] + node _T_1427 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1429 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1430 = cvt(_T_1429) @[Parameters.scala 117:49] + node _T_1432 = and(_T_1430, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1433 = asSInt(_T_1432) @[Parameters.scala 117:52] + node _T_1435 = eq(_T_1433, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1436 = and(_T_1427, _T_1435) @[Parameters.scala 132:56] + node _T_1438 = or(UInt<1>("h00"), _T_1436) @[Parameters.scala 134:30] + node _T_1439 = or(_T_1438, reset) @[RISCVPlatform.scala 23:14] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1441 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1442 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1444 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1446 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1447 = or(_T_1446, reset) @[RISCVPlatform.scala 23:14] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1449 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1450 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1452 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1454 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1455 = or(_T_1454, reset) @[RISCVPlatform.scala 23:14] + node _T_1457 = eq(_T_1455, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1457 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1459 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1460 = or(_T_1459, reset) @[RISCVPlatform.scala 23:14] + node _T_1462 = eq(_T_1460, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1462 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1464 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1464 : @[RISCVPlatform.scala 23:14] + node _T_1465 = or(_T_1327[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1467 = eq(_T_1465, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1467 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1468 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1470 = eq(_T_1468, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1470 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1471 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1473 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1475 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1476 = or(_T_1475, reset) @[RISCVPlatform.scala 23:14] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1478 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1480 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + when _T_1480 : @[RISCVPlatform.scala 23:14] + node _T_1481 = or(_T_1327[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1483 = eq(_T_1481, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1483 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1484 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1486 = eq(_T_1484, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1486 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1487 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1489 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1491 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1492 = or(_T_1491, reset) @[RISCVPlatform.scala 23:14] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1494 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:14] + when _T_1496 : @[RISCVPlatform.scala 23:14] + node _T_1497 = or(_T_1327[0], reset) @[RISCVPlatform.scala 23:14] + node _T_1499 = eq(_T_1497, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1499 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1500 = or(_T_1308, reset) @[RISCVPlatform.scala 23:14] + node _T_1502 = eq(_T_1500, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1502 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1503 = or(_T_1316, reset) @[RISCVPlatform.scala 23:14] + node _T_1505 = eq(_T_1503, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1505 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1507 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1508 = or(_T_1507, reset) @[RISCVPlatform.scala 23:14] + node _T_1510 = eq(_T_1508, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1510 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1512 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1513 = or(_T_1512, reset) @[RISCVPlatform.scala 23:14] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1515 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + when io.in[0].d.valid : @[RISCVPlatform.scala 23:14] + node _T_1517 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1518 = or(_T_1517, reset) @[RISCVPlatform.scala 23:14] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1520 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1522 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1523 = not(_T_1522) @[Parameters.scala 37:9] + node _T_1525 = or(_T_1523, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1526 = not(_T_1525) @[Parameters.scala 37:7] + node _T_1528 = eq(_T_1526, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1530 = xor(UInt<6>("h028"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1531 = not(_T_1530) @[Parameters.scala 37:9] + node _T_1533 = or(_T_1531, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1534 = not(_T_1533) @[Parameters.scala 37:7] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1538 = xor(UInt<6>("h020"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1539 = not(_T_1538) @[Parameters.scala 37:9] + node _T_1541 = or(_T_1539, UInt<3>("h07")) @[Parameters.scala 37:28] + node _T_1542 = not(_T_1541) @[Parameters.scala 37:7] + node _T_1544 = eq(_T_1542, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1547 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1547 is invalid @[Parameters.scala 228:27] + _T_1547[0] <= _T_1528 @[Parameters.scala 228:27] + _T_1547[1] <= _T_1536 @[Parameters.scala 228:27] + _T_1547[2] <= _T_1544 @[Parameters.scala 228:27] + node _T_1553 = or(_T_1547[0], _T_1547[1]) @[Parameters.scala 229:46] + node _T_1554 = or(_T_1553, _T_1547[2]) @[Parameters.scala 229:46] + node _T_1556 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1557 = dshl(_T_1556, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1558 = bits(_T_1557, 5, 0) @[package.scala 19:76] + node _T_1559 = not(_T_1558) @[package.scala 19:40] + node _T_1560 = and(io.in[0].d.bits.addr_lo, _T_1559) @[Edges.scala 17:16] + node _T_1562 = eq(_T_1560, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1564 = lt(io.in[0].d.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + node _T_1566 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:14] + when _T_1566 : @[RISCVPlatform.scala 23:14] + node _T_1567 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1569 = eq(_T_1567, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1569 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1570 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1572 = eq(_T_1570, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1572 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1573 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1575 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1577 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1578 = or(_T_1577, reset) @[RISCVPlatform.scala 23:14] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1580 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1582 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1583 = or(_T_1582, reset) @[RISCVPlatform.scala 23:14] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1585 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1587 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1588 = or(_T_1587, reset) @[RISCVPlatform.scala 23:14] + node _T_1590 = eq(_T_1588, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1590 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1592 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RISCVPlatform.scala 23:14] + when _T_1592 : @[RISCVPlatform.scala 23:14] + node _T_1593 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1595 = eq(_T_1593, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1595 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1596 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1598 = eq(_T_1596, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1598 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1599 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1601 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1603 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1604 = or(_T_1603, reset) @[RISCVPlatform.scala 23:14] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1606 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1608 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1609 = or(_T_1608, reset) @[RISCVPlatform.scala 23:14] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1611 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1613 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RISCVPlatform.scala 23:14] + when _T_1613 : @[RISCVPlatform.scala 23:14] + node _T_1614 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1616 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1617 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1619 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1620 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1622 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1624 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RISCVPlatform.scala 23:14] + node _T_1625 = or(_T_1624, reset) @[RISCVPlatform.scala 23:14] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1627 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1629 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1630 = or(_T_1629, reset) @[RISCVPlatform.scala 23:14] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1632 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1634 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1634 : @[RISCVPlatform.scala 23:14] + node _T_1635 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1637 = eq(_T_1635, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1637 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1638 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1640 = eq(_T_1638, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1640 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1641 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1643 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1645 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1646 = or(_T_1645, reset) @[RISCVPlatform.scala 23:14] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1648 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + when _T_1650 : @[RISCVPlatform.scala 23:14] + node _T_1651 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1653 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1654 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1656 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1657 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1659 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1662 = or(_T_1661, reset) @[RISCVPlatform.scala 23:14] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1664 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RISCVPlatform.scala 23:14] + when _T_1666 : @[RISCVPlatform.scala 23:14] + node _T_1667 = or(_T_1554, reset) @[RISCVPlatform.scala 23:14] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1669 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1670 = or(_T_1562, reset) @[RISCVPlatform.scala 23:14] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1672 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1673 = or(_T_1564, reset) @[RISCVPlatform.scala 23:14] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1675 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1678 = or(_T_1677, reset) @[RISCVPlatform.scala 23:14] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1680 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1682 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1683 = or(_T_1682, reset) @[RISCVPlatform.scala 23:14] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1685 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + when io.in[0].e.valid : @[RISCVPlatform.scala 23:14] + node _T_1687 = lt(io.in[0].e.bits.sink, UInt<1>("h01")) @[RISCVPlatform.scala 23:14] + node _T_1688 = or(_T_1687, reset) @[RISCVPlatform.scala 23:14] + node _T_1690 = eq(_T_1688, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1690 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1691 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1693 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1694 = dshl(_T_1693, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1695 = bits(_T_1694, 5, 0) @[package.scala 19:76] + node _T_1696 = not(_T_1695) @[package.scala 19:40] + node _T_1697 = shr(_T_1696, 3) @[Edges.scala 198:59] + node _T_1698 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1700 = eq(_T_1698, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1702 = mux(_T_1700, _T_1697, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1704 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1706 = sub(_T_1704, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1707 = asUInt(_T_1706) @[Edges.scala 208:28] + node _T_1708 = tail(_T_1707, 1) @[Edges.scala 208:28] + node _T_1710 = eq(_T_1704, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1712 = eq(_T_1704, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1714 = eq(_T_1702, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1715 = or(_T_1712, _T_1714) @[Edges.scala 210:37] + node _T_1716 = and(_T_1715, _T_1691) @[Edges.scala 211:22] + node _T_1717 = not(_T_1708) @[Edges.scala 212:27] + node _T_1718 = and(_T_1702, _T_1717) @[Edges.scala 212:25] + when _T_1691 : @[Edges.scala 213:17] + node _T_1719 = mux(_T_1710, _T_1702, _T_1708) @[Edges.scala 214:21] + _T_1704 <= _T_1719 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1721 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1723 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1725 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1727 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1729 : UInt, clock @[RISCVPlatform.scala 23:14] + node _T_1731 = eq(_T_1710, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1732 = and(io.in[0].a.valid, _T_1731) @[RISCVPlatform.scala 23:14] + when _T_1732 : @[RISCVPlatform.scala 23:14] + node _T_1733 = eq(io.in[0].a.bits.opcode, _T_1721) @[RISCVPlatform.scala 23:14] + node _T_1734 = or(_T_1733, reset) @[RISCVPlatform.scala 23:14] + node _T_1736 = eq(_T_1734, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1736 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1737 = eq(io.in[0].a.bits.param, _T_1723) @[RISCVPlatform.scala 23:14] + node _T_1738 = or(_T_1737, reset) @[RISCVPlatform.scala 23:14] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1740 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1741 = eq(io.in[0].a.bits.size, _T_1725) @[RISCVPlatform.scala 23:14] + node _T_1742 = or(_T_1741, reset) @[RISCVPlatform.scala 23:14] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1744 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1745 = eq(io.in[0].a.bits.source, _T_1727) @[RISCVPlatform.scala 23:14] + node _T_1746 = or(_T_1745, reset) @[RISCVPlatform.scala 23:14] + node _T_1748 = eq(_T_1746, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1748 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1749 = eq(io.in[0].a.bits.address, _T_1729) @[RISCVPlatform.scala 23:14] + node _T_1750 = or(_T_1749, reset) @[RISCVPlatform.scala 23:14] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1752 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1753 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1754 = and(_T_1753, _T_1710) @[RISCVPlatform.scala 23:14] + when _T_1754 : @[RISCVPlatform.scala 23:14] + _T_1721 <= io.in[0].a.bits.opcode @[RISCVPlatform.scala 23:14] + _T_1723 <= io.in[0].a.bits.param @[RISCVPlatform.scala 23:14] + _T_1725 <= io.in[0].a.bits.size @[RISCVPlatform.scala 23:14] + _T_1727 <= io.in[0].a.bits.source @[RISCVPlatform.scala 23:14] + _T_1729 <= io.in[0].a.bits.address @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1755 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1757 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1758 = dshl(_T_1757, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1759 = bits(_T_1758, 5, 0) @[package.scala 19:76] + node _T_1760 = not(_T_1759) @[package.scala 19:40] + node _T_1761 = shr(_T_1760, 3) @[Edges.scala 198:59] + node _T_1762 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1767 = mux(UInt<1>("h00"), _T_1761, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1769 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1771 = sub(_T_1769, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1772 = asUInt(_T_1771) @[Edges.scala 208:28] + node _T_1773 = tail(_T_1772, 1) @[Edges.scala 208:28] + node _T_1775 = eq(_T_1769, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1777 = eq(_T_1769, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1779 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1780 = or(_T_1777, _T_1779) @[Edges.scala 210:37] + node _T_1781 = and(_T_1780, _T_1755) @[Edges.scala 211:22] + node _T_1782 = not(_T_1773) @[Edges.scala 212:27] + node _T_1783 = and(_T_1767, _T_1782) @[Edges.scala 212:25] + when _T_1755 : @[Edges.scala 213:17] + node _T_1784 = mux(_T_1775, _T_1767, _T_1773) @[Edges.scala 214:21] + _T_1769 <= _T_1784 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1786 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1788 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1790 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1792 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1794 : UInt, clock @[RISCVPlatform.scala 23:14] + node _T_1796 = eq(_T_1775, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1797 = and(io.in[0].b.valid, _T_1796) @[RISCVPlatform.scala 23:14] + when _T_1797 : @[RISCVPlatform.scala 23:14] + node _T_1798 = eq(io.in[0].b.bits.opcode, _T_1786) @[RISCVPlatform.scala 23:14] + node _T_1799 = or(_T_1798, reset) @[RISCVPlatform.scala 23:14] + node _T_1801 = eq(_T_1799, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1801 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1802 = eq(io.in[0].b.bits.param, _T_1788) @[RISCVPlatform.scala 23:14] + node _T_1803 = or(_T_1802, reset) @[RISCVPlatform.scala 23:14] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1805 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1806 = eq(io.in[0].b.bits.size, _T_1790) @[RISCVPlatform.scala 23:14] + node _T_1807 = or(_T_1806, reset) @[RISCVPlatform.scala 23:14] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1809 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1810 = eq(io.in[0].b.bits.source, _T_1792) @[RISCVPlatform.scala 23:14] + node _T_1811 = or(_T_1810, reset) @[RISCVPlatform.scala 23:14] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1813 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1814 = eq(io.in[0].b.bits.address, _T_1794) @[RISCVPlatform.scala 23:14] + node _T_1815 = or(_T_1814, reset) @[RISCVPlatform.scala 23:14] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1817 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1818 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1819 = and(_T_1818, _T_1775) @[RISCVPlatform.scala 23:14] + when _T_1819 : @[RISCVPlatform.scala 23:14] + _T_1786 <= io.in[0].b.bits.opcode @[RISCVPlatform.scala 23:14] + _T_1788 <= io.in[0].b.bits.param @[RISCVPlatform.scala 23:14] + _T_1790 <= io.in[0].b.bits.size @[RISCVPlatform.scala 23:14] + _T_1792 <= io.in[0].b.bits.source @[RISCVPlatform.scala 23:14] + _T_1794 <= io.in[0].b.bits.address @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1820 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1822 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1823 = dshl(_T_1822, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1824 = bits(_T_1823, 5, 0) @[package.scala 19:76] + node _T_1825 = not(_T_1824) @[package.scala 19:40] + node _T_1826 = shr(_T_1825, 3) @[Edges.scala 198:59] + node _T_1827 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1829 = mux(_T_1827, _T_1826, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1831 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1833 = sub(_T_1831, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1834 = asUInt(_T_1833) @[Edges.scala 208:28] + node _T_1835 = tail(_T_1834, 1) @[Edges.scala 208:28] + node _T_1837 = eq(_T_1831, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1839 = eq(_T_1831, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1841 = eq(_T_1829, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1842 = or(_T_1839, _T_1841) @[Edges.scala 210:37] + node _T_1843 = and(_T_1842, _T_1820) @[Edges.scala 211:22] + node _T_1844 = not(_T_1835) @[Edges.scala 212:27] + node _T_1845 = and(_T_1829, _T_1844) @[Edges.scala 212:25] + when _T_1820 : @[Edges.scala 213:17] + node _T_1846 = mux(_T_1837, _T_1829, _T_1835) @[Edges.scala 214:21] + _T_1831 <= _T_1846 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1848 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1850 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1852 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1854 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1856 : UInt, clock @[RISCVPlatform.scala 23:14] + node _T_1858 = eq(_T_1837, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1859 = and(io.in[0].c.valid, _T_1858) @[RISCVPlatform.scala 23:14] + when _T_1859 : @[RISCVPlatform.scala 23:14] + node _T_1860 = eq(io.in[0].c.bits.opcode, _T_1848) @[RISCVPlatform.scala 23:14] + node _T_1861 = or(_T_1860, reset) @[RISCVPlatform.scala 23:14] + node _T_1863 = eq(_T_1861, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1863 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1864 = eq(io.in[0].c.bits.param, _T_1850) @[RISCVPlatform.scala 23:14] + node _T_1865 = or(_T_1864, reset) @[RISCVPlatform.scala 23:14] + node _T_1867 = eq(_T_1865, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1867 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1868 = eq(io.in[0].c.bits.size, _T_1852) @[RISCVPlatform.scala 23:14] + node _T_1869 = or(_T_1868, reset) @[RISCVPlatform.scala 23:14] + node _T_1871 = eq(_T_1869, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1871 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1872 = eq(io.in[0].c.bits.source, _T_1854) @[RISCVPlatform.scala 23:14] + node _T_1873 = or(_T_1872, reset) @[RISCVPlatform.scala 23:14] + node _T_1875 = eq(_T_1873, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1875 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1876 = eq(io.in[0].c.bits.address, _T_1856) @[RISCVPlatform.scala 23:14] + node _T_1877 = or(_T_1876, reset) @[RISCVPlatform.scala 23:14] + node _T_1879 = eq(_T_1877, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1879 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1880 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1881 = and(_T_1880, _T_1837) @[RISCVPlatform.scala 23:14] + when _T_1881 : @[RISCVPlatform.scala 23:14] + _T_1848 <= io.in[0].c.bits.opcode @[RISCVPlatform.scala 23:14] + _T_1850 <= io.in[0].c.bits.param @[RISCVPlatform.scala 23:14] + _T_1852 <= io.in[0].c.bits.size @[RISCVPlatform.scala 23:14] + _T_1854 <= io.in[0].c.bits.source @[RISCVPlatform.scala 23:14] + _T_1856 <= io.in[0].c.bits.address @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1882 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1884 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1885 = dshl(_T_1884, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1886 = bits(_T_1885, 5, 0) @[package.scala 19:76] + node _T_1887 = not(_T_1886) @[package.scala 19:40] + node _T_1888 = shr(_T_1887, 3) @[Edges.scala 198:59] + node _T_1889 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1891 = mux(_T_1889, _T_1888, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1893 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1895 = sub(_T_1893, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1896 = asUInt(_T_1895) @[Edges.scala 208:28] + node _T_1897 = tail(_T_1896, 1) @[Edges.scala 208:28] + node _T_1899 = eq(_T_1893, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1901 = eq(_T_1893, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1903 = eq(_T_1891, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1904 = or(_T_1901, _T_1903) @[Edges.scala 210:37] + node _T_1905 = and(_T_1904, _T_1882) @[Edges.scala 211:22] + node _T_1906 = not(_T_1897) @[Edges.scala 212:27] + node _T_1907 = and(_T_1891, _T_1906) @[Edges.scala 212:25] + when _T_1882 : @[Edges.scala 213:17] + node _T_1908 = mux(_T_1899, _T_1891, _T_1897) @[Edges.scala 214:21] + _T_1893 <= _T_1908 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1910 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1912 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1914 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1916 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1918 : UInt, clock @[RISCVPlatform.scala 23:14] + reg _T_1920 : UInt, clock @[RISCVPlatform.scala 23:14] + node _T_1922 = eq(_T_1899, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_1923 = and(io.in[0].d.valid, _T_1922) @[RISCVPlatform.scala 23:14] + when _T_1923 : @[RISCVPlatform.scala 23:14] + node _T_1924 = eq(io.in[0].d.bits.opcode, _T_1910) @[RISCVPlatform.scala 23:14] + node _T_1925 = or(_T_1924, reset) @[RISCVPlatform.scala 23:14] + node _T_1927 = eq(_T_1925, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1927 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1928 = eq(io.in[0].d.bits.param, _T_1912) @[RISCVPlatform.scala 23:14] + node _T_1929 = or(_T_1928, reset) @[RISCVPlatform.scala 23:14] + node _T_1931 = eq(_T_1929, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1931 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1932 = eq(io.in[0].d.bits.size, _T_1914) @[RISCVPlatform.scala 23:14] + node _T_1933 = or(_T_1932, reset) @[RISCVPlatform.scala 23:14] + node _T_1935 = eq(_T_1933, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1935 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1936 = eq(io.in[0].d.bits.source, _T_1916) @[RISCVPlatform.scala 23:14] + node _T_1937 = or(_T_1936, reset) @[RISCVPlatform.scala 23:14] + node _T_1939 = eq(_T_1937, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1939 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1940 = eq(io.in[0].d.bits.sink, _T_1918) @[RISCVPlatform.scala 23:14] + node _T_1941 = or(_T_1940, reset) @[RISCVPlatform.scala 23:14] + node _T_1943 = eq(_T_1941, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1943 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1944 = eq(io.in[0].d.bits.addr_lo, _T_1920) @[RISCVPlatform.scala 23:14] + node _T_1945 = or(_T_1944, reset) @[RISCVPlatform.scala 23:14] + node _T_1947 = eq(_T_1945, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_1947 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_1948 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1949 = and(_T_1948, _T_1899) @[RISCVPlatform.scala 23:14] + when _T_1949 : @[RISCVPlatform.scala 23:14] + _T_1910 <= io.in[0].d.bits.opcode @[RISCVPlatform.scala 23:14] + _T_1912 <= io.in[0].d.bits.param @[RISCVPlatform.scala 23:14] + _T_1914 <= io.in[0].d.bits.size @[RISCVPlatform.scala 23:14] + _T_1916 <= io.in[0].d.bits.source @[RISCVPlatform.scala 23:14] + _T_1918 <= io.in[0].d.bits.sink @[RISCVPlatform.scala 23:14] + _T_1920 <= io.in[0].d.bits.addr_lo @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + reg _T_1951 : UInt<48>, clock with : (reset => (reset, UInt<48>("h00"))) @[Reg.scala 26:44] + node _T_1952 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1954 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1955 = dshl(_T_1954, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1956 = bits(_T_1955, 5, 0) @[package.scala 19:76] + node _T_1957 = not(_T_1956) @[package.scala 19:40] + node _T_1958 = shr(_T_1957, 3) @[Edges.scala 198:59] + node _T_1959 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1961 = eq(_T_1959, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1963 = mux(_T_1961, _T_1958, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1965 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1967 = sub(_T_1965, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1968 = asUInt(_T_1967) @[Edges.scala 208:28] + node _T_1969 = tail(_T_1968, 1) @[Edges.scala 208:28] + node _T_1971 = eq(_T_1965, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1973 = eq(_T_1965, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1975 = eq(_T_1963, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1976 = or(_T_1973, _T_1975) @[Edges.scala 210:37] + node _T_1977 = and(_T_1976, _T_1952) @[Edges.scala 211:22] + node _T_1978 = not(_T_1969) @[Edges.scala 212:27] + node _T_1979 = and(_T_1963, _T_1978) @[Edges.scala 212:25] + when _T_1952 : @[Edges.scala 213:17] + node _T_1980 = mux(_T_1971, _T_1963, _T_1969) @[Edges.scala 214:21] + _T_1965 <= _T_1980 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1981 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1983 = asUInt(asSInt(UInt<6>("h03f"))) @[package.scala 19:64] + node _T_1984 = dshl(_T_1983, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1985 = bits(_T_1984, 5, 0) @[package.scala 19:76] + node _T_1986 = not(_T_1985) @[package.scala 19:40] + node _T_1987 = shr(_T_1986, 3) @[Edges.scala 198:59] + node _T_1988 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1990 = mux(_T_1988, _T_1987, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1992 : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 26:44] + node _T_1994 = sub(_T_1992, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1995 = asUInt(_T_1994) @[Edges.scala 208:28] + node _T_1996 = tail(_T_1995, 1) @[Edges.scala 208:28] + node _T_1998 = eq(_T_1992, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2000 = eq(_T_1992, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2002 = eq(_T_1990, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2003 = or(_T_2000, _T_2002) @[Edges.scala 210:37] + node _T_2004 = and(_T_2003, _T_1981) @[Edges.scala 211:22] + node _T_2005 = not(_T_1996) @[Edges.scala 212:27] + node _T_2006 = and(_T_1990, _T_2005) @[Edges.scala 212:25] + when _T_1981 : @[Edges.scala 213:17] + node _T_2007 = mux(_T_1998, _T_1990, _T_1996) @[Edges.scala 214:21] + _T_1992 <= _T_2007 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + wire _T_2009 : UInt<48> + _T_2009 is invalid + _T_2009 <= UInt<48>("h00") + node _T_2010 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2010 : @[RISCVPlatform.scala 23:14] + when _T_1976 : @[RISCVPlatform.scala 23:14] + node _T_2012 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2009 <= _T_2012 @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_2013 = dshr(_T_1951, io.in[0].a.bits.source) @[RISCVPlatform.scala 23:14] + node _T_2014 = bits(_T_2013, 0, 0) @[RISCVPlatform.scala 23:14] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + node _T_2017 = or(_T_2016, reset) @[RISCVPlatform.scala 23:14] + node _T_2019 = eq(_T_2017, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_2019 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + wire _T_2021 : UInt<48> + _T_2021 is invalid + _T_2021 <= UInt<48>("h00") + node _T_2022 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2024 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RISCVPlatform.scala 23:14] + node _T_2025 = and(_T_2022, _T_2024) @[RISCVPlatform.scala 23:14] + when _T_2025 : @[RISCVPlatform.scala 23:14] + when _T_2003 : @[RISCVPlatform.scala 23:14] + node _T_2027 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2021 <= _T_2027 @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_2028 = or(_T_2009, _T_1951) @[RISCVPlatform.scala 23:14] + node _T_2029 = dshr(_T_2028, io.in[0].d.bits.source) @[RISCVPlatform.scala 23:14] + node _T_2030 = bits(_T_2029, 0, 0) @[RISCVPlatform.scala 23:14] + node _T_2031 = or(_T_2030, reset) @[RISCVPlatform.scala 23:14] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[RISCVPlatform.scala 23:14] + when _T_2033 : @[RISCVPlatform.scala 23:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RISCVPlatform.scala:23:14)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RISCVPlatform.scala 23:14] + stop(clock, UInt<1>(1), 1) @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + skip @[RISCVPlatform.scala 23:14] + node _T_2034 = or(_T_1951, _T_2009) @[RISCVPlatform.scala 23:14] + node _T_2035 = not(_T_2021) @[RISCVPlatform.scala 23:14] + node _T_2036 = and(_T_2034, _T_2035) @[RISCVPlatform.scala 23:14] + _T_1951 <= _T_2036 @[RISCVPlatform.scala 23:14] + + module IntXbar : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {3 : UInt<1>[1], 2 : UInt<1>[1], 1 : UInt<1>[2], 0 : UInt<1>[1]}, out : {0 : UInt<1>[5]}} + + io is invalid + io is invalid + io.out.0[0] <= io.in.0[0] @[IntNodes.scala 126:24] + io.out.0[1] <= io.in.1[0] @[IntNodes.scala 126:24] + io.out.0[2] <= io.in.1[1] @[IntNodes.scala 126:24] + io.out.0[3] <= io.in.2[0] @[IntNodes.scala 126:24] + io.out.0[4] <= io.in.3[0] @[IntNodes.scala 126:24] + + module Queue_35 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {sink : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_34 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_36 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_37 = and(_T_34, _T_36) @[Decoupled.scala 188:33] + node _T_38 = and(_T_34, maybe_full) @[Decoupled.scala 189:32] + node _T_39 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_39 + node _T_40 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_40 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_42 = ram[UInt<1>("h00")], clock + _T_42 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_46 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_46 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_48 = eq(_T_37, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_48 @[Decoupled.scala 204:16] + node _T_50 = eq(_T_38, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_50 @[Decoupled.scala 205:16] + infer mport _T_52 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_52 @[Decoupled.scala 206:15] + node _T_54 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_55 = asUInt(_T_54) @[Decoupled.scala 221:40] + node _T_56 = tail(_T_55, 1) @[Decoupled.scala 221:40] + node _T_57 = and(maybe_full, _T_34) @[Decoupled.scala 223:32] + node _T_58 = cat(_T_57, _T_56) @[Cat.scala 30:58] + io.count <= _T_58 @[Decoupled.scala 223:14] + + module Arbiter : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, chosen : UInt<2>} + + io is invalid + io is invalid + io.chosen <= UInt<2>("h02") @[Arbiter.scala 118:13] + io.out.bits <- io.in[2].bits @[Arbiter.scala 119:15] + when io.in[1].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h01") @[Arbiter.scala 122:17] + io.out.bits <- io.in[1].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + when io.in[0].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h00") @[Arbiter.scala 122:17] + io.out.bits <- io.in[0].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + node _T_186 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 31:68] + node _T_188 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_190 = eq(_T_186, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_191 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 129:19] + io.in[0].ready <= _T_191 @[Arbiter.scala 129:14] + node _T_192 = and(_T_188, io.out.ready) @[Arbiter.scala 129:19] + io.in[1].ready <= _T_192 @[Arbiter.scala 129:14] + node _T_193 = and(_T_190, io.out.ready) @[Arbiter.scala 129:19] + io.in[2].ready <= _T_193 @[Arbiter.scala 129:14] + node _T_195 = eq(_T_190, UInt<1>("h00")) @[Arbiter.scala 130:19] + node _T_196 = or(_T_195, io.in[2].valid) @[Arbiter.scala 130:31] + io.out.valid <= _T_196 @[Arbiter.scala 130:16] + + module Arbiter_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : {coh : {state : UInt<2>}, tag : UInt<20>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : {coh : {state : UInt<2>}, tag : UInt<20>}}}, chosen : UInt<2>} + + io is invalid + io is invalid + io.chosen <= UInt<2>("h02") @[Arbiter.scala 118:13] + io.out.bits <- io.in[2].bits @[Arbiter.scala 119:15] + when io.in[1].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h01") @[Arbiter.scala 122:17] + io.out.bits <- io.in[1].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + when io.in[0].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h00") @[Arbiter.scala 122:17] + io.out.bits <- io.in[0].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + node _T_298 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 31:68] + node _T_300 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_302 = eq(_T_298, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_303 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 129:19] + io.in[0].ready <= _T_303 @[Arbiter.scala 129:14] + node _T_304 = and(_T_300, io.out.ready) @[Arbiter.scala 129:19] + io.in[1].ready <= _T_304 @[Arbiter.scala 129:14] + node _T_305 = and(_T_302, io.out.ready) @[Arbiter.scala 129:19] + io.in[2].ready <= _T_305 @[Arbiter.scala 129:14] + node _T_307 = eq(_T_302, UInt<1>("h00")) @[Arbiter.scala 130:19] + node _T_308 = or(_T_307, io.in[2].valid) @[Arbiter.scala 130:31] + io.out.valid <= _T_308 @[Arbiter.scala 130:16] + + module DCacheDataArray : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, resp : UInt<64>[4]} + + io is invalid + io is invalid + node addr = shr(io.req.bits.addr, 3) @[DCache.scala 29:31] + smem _T_56 : UInt<8>[8][512] @[DCache.scala 31:23] + node _T_58 = bits(io.req.bits.way_en, 0, 0) @[DCache.scala 32:72] + node _T_59 = or(UInt<1>("h00"), _T_58) @[DCache.scala 32:51] + node _T_60 = and(io.req.valid, _T_59) @[DCache.scala 32:30] + node _T_61 = and(_T_60, io.req.bits.write) @[DCache.scala 33:17] + when _T_61 : @[DCache.scala 33:39] + node _T_62 = bits(io.req.bits.wdata, 7, 0) @[DCache.scala 34:63] + node _T_63 = bits(io.req.bits.wdata, 15, 8) @[DCache.scala 34:63] + node _T_64 = bits(io.req.bits.wdata, 23, 16) @[DCache.scala 34:63] + node _T_65 = bits(io.req.bits.wdata, 31, 24) @[DCache.scala 34:63] + node _T_66 = bits(io.req.bits.wdata, 39, 32) @[DCache.scala 34:63] + node _T_67 = bits(io.req.bits.wdata, 47, 40) @[DCache.scala 34:63] + node _T_68 = bits(io.req.bits.wdata, 55, 48) @[DCache.scala 34:63] + node _T_69 = bits(io.req.bits.wdata, 63, 56) @[DCache.scala 34:63] + wire _T_72 : UInt<8>[8] @[DCache.scala 34:40] + _T_72 is invalid @[DCache.scala 34:40] + _T_72[0] <= _T_62 @[DCache.scala 34:40] + _T_72[1] <= _T_63 @[DCache.scala 34:40] + _T_72[2] <= _T_64 @[DCache.scala 34:40] + _T_72[3] <= _T_65 @[DCache.scala 34:40] + _T_72[4] <= _T_66 @[DCache.scala 34:40] + _T_72[5] <= _T_67 @[DCache.scala 34:40] + _T_72[6] <= _T_68 @[DCache.scala 34:40] + _T_72[7] <= _T_69 @[DCache.scala 34:40] + node _T_83 = bits(io.req.bits.wmask, 0, 0) @[DCache.scala 35:49] + node _T_84 = bits(io.req.bits.wmask, 1, 1) @[DCache.scala 35:49] + node _T_85 = bits(io.req.bits.wmask, 2, 2) @[DCache.scala 35:49] + node _T_86 = bits(io.req.bits.wmask, 3, 3) @[DCache.scala 35:49] + node _T_87 = bits(io.req.bits.wmask, 4, 4) @[DCache.scala 35:49] + node _T_88 = bits(io.req.bits.wmask, 5, 5) @[DCache.scala 35:49] + node _T_89 = bits(io.req.bits.wmask, 6, 6) @[DCache.scala 35:49] + node _T_90 = bits(io.req.bits.wmask, 7, 7) @[DCache.scala 35:49] + write mport _T_91 = _T_56[addr], clock + when _T_83 : + _T_91[0] <= _T_72[0] skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") + when _T_84 : + _T_91[1] <= _T_72[1] skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 + when _T_85 : + _T_91[2] <= _T_72[2] skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 + when _T_86 : + _T_91[3] <= _T_72[3] skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip + when _T_87 : + _T_91[4] <= _T_72[4] skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 + when _T_88 : + _T_91[5] <= _T_72[5] skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") + when _T_89 : + _T_91[6] <= _T_72[6] skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 + when _T_90 : + _T_91[7] <= _T_72[7] skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 + skip @[DCache.scala 33:39] + node _T_112 = eq(io.req.bits.write, UInt<1>("h00")) @[DCache.scala 37:45] + node _T_113 = and(_T_60, _T_112) @[DCache.scala 37:42] + wire _T_115 : UInt + _T_115 is invalid + when _T_113 : + _T_115 <= addr + node _T_117 = or(_T_115, UInt<9>("h00")) + node _T_118 = bits(_T_117, 8, 0) + read mport _T_119 = _T_56[_T_118], clock + skip + node _T_139 = cat(_T_119[1], _T_119[0]) @[DCache.scala 37:65] + node _T_140 = cat(_T_119[3], _T_119[2]) @[DCache.scala 37:65] + node _T_141 = cat(_T_140, _T_139) @[DCache.scala 37:65] + node _T_142 = cat(_T_119[5], _T_119[4]) @[DCache.scala 37:65] + node _T_143 = cat(_T_119[7], _T_119[6]) @[DCache.scala 37:65] + node _T_144 = cat(_T_143, _T_142) @[DCache.scala 37:65] + node _T_145 = cat(_T_144, _T_141) @[DCache.scala 37:65] + io.resp[0] <= _T_145 @[DCache.scala 37:16] + smem _T_160 : UInt<8>[8][512] @[DCache.scala 31:23] + node _T_162 = bits(io.req.bits.way_en, 1, 1) @[DCache.scala 32:72] + node _T_163 = or(UInt<1>("h00"), _T_162) @[DCache.scala 32:51] + node _T_164 = and(io.req.valid, _T_163) @[DCache.scala 32:30] + node _T_165 = and(_T_164, io.req.bits.write) @[DCache.scala 33:17] + when _T_165 : @[DCache.scala 33:39] + node _T_166 = bits(io.req.bits.wdata, 7, 0) @[DCache.scala 34:63] + node _T_167 = bits(io.req.bits.wdata, 15, 8) @[DCache.scala 34:63] + node _T_168 = bits(io.req.bits.wdata, 23, 16) @[DCache.scala 34:63] + node _T_169 = bits(io.req.bits.wdata, 31, 24) @[DCache.scala 34:63] + node _T_170 = bits(io.req.bits.wdata, 39, 32) @[DCache.scala 34:63] + node _T_171 = bits(io.req.bits.wdata, 47, 40) @[DCache.scala 34:63] + node _T_172 = bits(io.req.bits.wdata, 55, 48) @[DCache.scala 34:63] + node _T_173 = bits(io.req.bits.wdata, 63, 56) @[DCache.scala 34:63] + wire _T_176 : UInt<8>[8] @[DCache.scala 34:40] + _T_176 is invalid @[DCache.scala 34:40] + _T_176[0] <= _T_166 @[DCache.scala 34:40] + _T_176[1] <= _T_167 @[DCache.scala 34:40] + _T_176[2] <= _T_168 @[DCache.scala 34:40] + _T_176[3] <= _T_169 @[DCache.scala 34:40] + _T_176[4] <= _T_170 @[DCache.scala 34:40] + _T_176[5] <= _T_171 @[DCache.scala 34:40] + _T_176[6] <= _T_172 @[DCache.scala 34:40] + _T_176[7] <= _T_173 @[DCache.scala 34:40] + node _T_187 = bits(io.req.bits.wmask, 0, 0) @[DCache.scala 35:49] + node _T_188 = bits(io.req.bits.wmask, 1, 1) @[DCache.scala 35:49] + node _T_189 = bits(io.req.bits.wmask, 2, 2) @[DCache.scala 35:49] + node _T_190 = bits(io.req.bits.wmask, 3, 3) @[DCache.scala 35:49] + node _T_191 = bits(io.req.bits.wmask, 4, 4) @[DCache.scala 35:49] + node _T_192 = bits(io.req.bits.wmask, 5, 5) @[DCache.scala 35:49] + node _T_193 = bits(io.req.bits.wmask, 6, 6) @[DCache.scala 35:49] + node _T_194 = bits(io.req.bits.wmask, 7, 7) @[DCache.scala 35:49] + write mport _T_195 = _T_160[addr], clock + when _T_187 : + _T_195[0] <= _T_176[0] skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") + when _T_188 : + _T_195[1] <= _T_176[1] skip - skip - - module BroadcastAcquireTracker_29 : - input clk : Clock - input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) + when _T_189 : + _T_195[2] <= _T_176[2] skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h04") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<3>("h04") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<3>("h04") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<3>("h04") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<3>("h04") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<3>("h04") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h04") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) + when _T_190 : + _T_195[3] <= _T_176[3] skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) + when _T_191 : + _T_195[4] <= _T_176[4] skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) + when _T_192 : + _T_195[5] <= _T_176[5] skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 + when _T_193 : + _T_195[6] <= _T_176[6] skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") + when _T_194 : + _T_195[7] <= _T_176[7] skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") + skip @[DCache.scala 33:39] + node _T_216 = eq(io.req.bits.write, UInt<1>("h00")) @[DCache.scala 37:45] + node _T_217 = and(_T_164, _T_216) @[DCache.scala 37:42] + wire _T_219 : UInt + _T_219 is invalid + when _T_217 : + _T_219 <= addr + node _T_221 = or(_T_219, UInt<9>("h00")) + node _T_222 = bits(_T_221, 8, 0) + read mport _T_223 = _T_160[_T_222], clock + skip + node _T_243 = cat(_T_223[1], _T_223[0]) @[DCache.scala 37:65] + node _T_244 = cat(_T_223[3], _T_223[2]) @[DCache.scala 37:65] + node _T_245 = cat(_T_244, _T_243) @[DCache.scala 37:65] + node _T_246 = cat(_T_223[5], _T_223[4]) @[DCache.scala 37:65] + node _T_247 = cat(_T_223[7], _T_223[6]) @[DCache.scala 37:65] + node _T_248 = cat(_T_247, _T_246) @[DCache.scala 37:65] + node _T_249 = cat(_T_248, _T_245) @[DCache.scala 37:65] + io.resp[1] <= _T_249 @[DCache.scala 37:16] + smem _T_264 : UInt<8>[8][512] @[DCache.scala 31:23] + node _T_266 = bits(io.req.bits.way_en, 2, 2) @[DCache.scala 32:72] + node _T_267 = or(UInt<1>("h00"), _T_266) @[DCache.scala 32:51] + node _T_268 = and(io.req.valid, _T_267) @[DCache.scala 32:30] + node _T_269 = and(_T_268, io.req.bits.write) @[DCache.scala 33:17] + when _T_269 : @[DCache.scala 33:39] + node _T_270 = bits(io.req.bits.wdata, 7, 0) @[DCache.scala 34:63] + node _T_271 = bits(io.req.bits.wdata, 15, 8) @[DCache.scala 34:63] + node _T_272 = bits(io.req.bits.wdata, 23, 16) @[DCache.scala 34:63] + node _T_273 = bits(io.req.bits.wdata, 31, 24) @[DCache.scala 34:63] + node _T_274 = bits(io.req.bits.wdata, 39, 32) @[DCache.scala 34:63] + node _T_275 = bits(io.req.bits.wdata, 47, 40) @[DCache.scala 34:63] + node _T_276 = bits(io.req.bits.wdata, 55, 48) @[DCache.scala 34:63] + node _T_277 = bits(io.req.bits.wdata, 63, 56) @[DCache.scala 34:63] + wire _T_280 : UInt<8>[8] @[DCache.scala 34:40] + _T_280 is invalid @[DCache.scala 34:40] + _T_280[0] <= _T_270 @[DCache.scala 34:40] + _T_280[1] <= _T_271 @[DCache.scala 34:40] + _T_280[2] <= _T_272 @[DCache.scala 34:40] + _T_280[3] <= _T_273 @[DCache.scala 34:40] + _T_280[4] <= _T_274 @[DCache.scala 34:40] + _T_280[5] <= _T_275 @[DCache.scala 34:40] + _T_280[6] <= _T_276 @[DCache.scala 34:40] + _T_280[7] <= _T_277 @[DCache.scala 34:40] + node _T_291 = bits(io.req.bits.wmask, 0, 0) @[DCache.scala 35:49] + node _T_292 = bits(io.req.bits.wmask, 1, 1) @[DCache.scala 35:49] + node _T_293 = bits(io.req.bits.wmask, 2, 2) @[DCache.scala 35:49] + node _T_294 = bits(io.req.bits.wmask, 3, 3) @[DCache.scala 35:49] + node _T_295 = bits(io.req.bits.wmask, 4, 4) @[DCache.scala 35:49] + node _T_296 = bits(io.req.bits.wmask, 5, 5) @[DCache.scala 35:49] + node _T_297 = bits(io.req.bits.wmask, 6, 6) @[DCache.scala 35:49] + node _T_298 = bits(io.req.bits.wmask, 7, 7) @[DCache.scala 35:49] + write mport _T_299 = _T_264[addr], clock + when _T_291 : + _T_299[0] <= _T_280[0] skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 + when _T_292 : + _T_299[1] <= _T_280[1] skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 + when _T_293 : + _T_299[2] <= _T_280[2] skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip + when _T_294 : + _T_299[3] <= _T_280[3] skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 + when _T_295 : + _T_299[4] <= _T_280[4] skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") + when _T_296 : + _T_299[5] <= _T_280[5] skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 + when _T_297 : + _T_299[6] <= _T_280[6] skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 + when _T_298 : + _T_299[7] <= _T_280[7] skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") + skip @[DCache.scala 33:39] + node _T_320 = eq(io.req.bits.write, UInt<1>("h00")) @[DCache.scala 37:45] + node _T_321 = and(_T_268, _T_320) @[DCache.scala 37:42] + wire _T_323 : UInt + _T_323 is invalid + when _T_321 : + _T_323 <= addr + node _T_325 = or(_T_323, UInt<9>("h00")) + node _T_326 = bits(_T_325, 8, 0) + read mport _T_327 = _T_264[_T_326], clock + skip + node _T_347 = cat(_T_327[1], _T_327[0]) @[DCache.scala 37:65] + node _T_348 = cat(_T_327[3], _T_327[2]) @[DCache.scala 37:65] + node _T_349 = cat(_T_348, _T_347) @[DCache.scala 37:65] + node _T_350 = cat(_T_327[5], _T_327[4]) @[DCache.scala 37:65] + node _T_351 = cat(_T_327[7], _T_327[6]) @[DCache.scala 37:65] + node _T_352 = cat(_T_351, _T_350) @[DCache.scala 37:65] + node _T_353 = cat(_T_352, _T_349) @[DCache.scala 37:65] + io.resp[2] <= _T_353 @[DCache.scala 37:16] + smem _T_368 : UInt<8>[8][512] @[DCache.scala 31:23] + node _T_370 = bits(io.req.bits.way_en, 3, 3) @[DCache.scala 32:72] + node _T_371 = or(UInt<1>("h00"), _T_370) @[DCache.scala 32:51] + node _T_372 = and(io.req.valid, _T_371) @[DCache.scala 32:30] + node _T_373 = and(_T_372, io.req.bits.write) @[DCache.scala 33:17] + when _T_373 : @[DCache.scala 33:39] + node _T_374 = bits(io.req.bits.wdata, 7, 0) @[DCache.scala 34:63] + node _T_375 = bits(io.req.bits.wdata, 15, 8) @[DCache.scala 34:63] + node _T_376 = bits(io.req.bits.wdata, 23, 16) @[DCache.scala 34:63] + node _T_377 = bits(io.req.bits.wdata, 31, 24) @[DCache.scala 34:63] + node _T_378 = bits(io.req.bits.wdata, 39, 32) @[DCache.scala 34:63] + node _T_379 = bits(io.req.bits.wdata, 47, 40) @[DCache.scala 34:63] + node _T_380 = bits(io.req.bits.wdata, 55, 48) @[DCache.scala 34:63] + node _T_381 = bits(io.req.bits.wdata, 63, 56) @[DCache.scala 34:63] + wire _T_384 : UInt<8>[8] @[DCache.scala 34:40] + _T_384 is invalid @[DCache.scala 34:40] + _T_384[0] <= _T_374 @[DCache.scala 34:40] + _T_384[1] <= _T_375 @[DCache.scala 34:40] + _T_384[2] <= _T_376 @[DCache.scala 34:40] + _T_384[3] <= _T_377 @[DCache.scala 34:40] + _T_384[4] <= _T_378 @[DCache.scala 34:40] + _T_384[5] <= _T_379 @[DCache.scala 34:40] + _T_384[6] <= _T_380 @[DCache.scala 34:40] + _T_384[7] <= _T_381 @[DCache.scala 34:40] + node _T_395 = bits(io.req.bits.wmask, 0, 0) @[DCache.scala 35:49] + node _T_396 = bits(io.req.bits.wmask, 1, 1) @[DCache.scala 35:49] + node _T_397 = bits(io.req.bits.wmask, 2, 2) @[DCache.scala 35:49] + node _T_398 = bits(io.req.bits.wmask, 3, 3) @[DCache.scala 35:49] + node _T_399 = bits(io.req.bits.wmask, 4, 4) @[DCache.scala 35:49] + node _T_400 = bits(io.req.bits.wmask, 5, 5) @[DCache.scala 35:49] + node _T_401 = bits(io.req.bits.wmask, 6, 6) @[DCache.scala 35:49] + node _T_402 = bits(io.req.bits.wmask, 7, 7) @[DCache.scala 35:49] + write mport _T_403 = _T_368[addr], clock + when _T_395 : + _T_403[0] <= _T_384[0] skip - skip - - module BroadcastAcquireTracker_30 : - input clk : Clock - input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) + when _T_396 : + _T_403[1] <= _T_384[1] skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h05") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<3>("h05") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<3>("h05") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<3>("h05") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<3>("h05") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<3>("h05") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h05") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) + when _T_397 : + _T_403[2] <= _T_384[2] skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) + when _T_398 : + _T_403[3] <= _T_384[3] skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) + when _T_399 : + _T_403[4] <= _T_384[4] skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 + when _T_400 : + _T_403[5] <= _T_384[5] skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") + when _T_401 : + _T_403[6] <= _T_384[6] skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") + when _T_402 : + _T_403[7] <= _T_384[7] skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 + skip @[DCache.scala 33:39] + node _T_424 = eq(io.req.bits.write, UInt<1>("h00")) @[DCache.scala 37:45] + node _T_425 = and(_T_372, _T_424) @[DCache.scala 37:42] + wire _T_427 : UInt + _T_427 is invalid + when _T_425 : + _T_427 <= addr + node _T_429 = or(_T_427, UInt<9>("h00")) + node _T_430 = bits(_T_429, 8, 0) + read mport _T_431 = _T_368[_T_430], clock + skip + node _T_451 = cat(_T_431[1], _T_431[0]) @[DCache.scala 37:65] + node _T_452 = cat(_T_431[3], _T_431[2]) @[DCache.scala 37:65] + node _T_453 = cat(_T_452, _T_451) @[DCache.scala 37:65] + node _T_454 = cat(_T_431[5], _T_431[4]) @[DCache.scala 37:65] + node _T_455 = cat(_T_431[7], _T_431[6]) @[DCache.scala 37:65] + node _T_456 = cat(_T_455, _T_454) @[DCache.scala 37:65] + node _T_457 = cat(_T_456, _T_453) @[DCache.scala 37:65] + io.resp[3] <= _T_457 @[DCache.scala 37:16] + + module Arbiter_2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, chosen : UInt<2>} + + io is invalid + io is invalid + io.chosen <= UInt<2>("h03") @[Arbiter.scala 118:13] + io.out.bits <- io.in[3].bits @[Arbiter.scala 119:15] + when io.in[2].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<2>("h02") @[Arbiter.scala 122:17] + io.out.bits <- io.in[2].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + when io.in[1].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h01") @[Arbiter.scala 122:17] + io.out.bits <- io.in[1].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + when io.in[0].valid : @[Arbiter.scala 121:27] + io.chosen <= UInt<1>("h00") @[Arbiter.scala 122:17] + io.out.bits <- io.in[0].bits @[Arbiter.scala 123:19] + skip @[Arbiter.scala 121:27] + node _T_292 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 31:68] + node _T_293 = or(_T_292, io.in[2].valid) @[Arbiter.scala 31:68] + node _T_295 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_297 = eq(_T_292, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_299 = eq(_T_293, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_300 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 129:19] + io.in[0].ready <= _T_300 @[Arbiter.scala 129:14] + node _T_301 = and(_T_295, io.out.ready) @[Arbiter.scala 129:19] + io.in[1].ready <= _T_301 @[Arbiter.scala 129:14] + node _T_302 = and(_T_297, io.out.ready) @[Arbiter.scala 129:19] + io.in[2].ready <= _T_302 @[Arbiter.scala 129:14] + node _T_303 = and(_T_299, io.out.ready) @[Arbiter.scala 129:19] + io.in[3].ready <= _T_303 @[Arbiter.scala 129:14] + node _T_305 = eq(_T_299, UInt<1>("h00")) @[Arbiter.scala 130:19] + node _T_306 = or(_T_305, io.in[3].valid) @[Arbiter.scala 130:31] + io.out.valid <= _T_306 @[Arbiter.scala 130:16] + + module TLB : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {vaddr : UInt<40>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, paddr : UInt<32>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, cacheable : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>}}, flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} + + io is invalid + io is invalid + reg valid : UInt<9>, clock with : (reset => (reset, UInt<9>("h00"))) @[TLB.scala 45:18] + reg ppns : UInt<20>[9], clock @[TLB.scala 46:17] + reg tags : UInt<27>[9], clock @[TLB.scala 47:17] + reg levels : UInt<2>[9], clock @[TLB.scala 48:19] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[TLB.scala 51:18] + reg r_refill_tag : UInt<27>, clock @[TLB.scala 52:25] + reg r_refill_waddr : UInt<3>, clock @[TLB.scala 53:27] + reg r_req : {vaddr : UInt<40>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock @[TLB.scala 54:18] + node _T_272 = eq(io.req.bits.instruction, UInt<1>("h00")) @[TLB.scala 56:39] + node do_mprv = and(io.ptw.status.mprv, _T_272) @[TLB.scala 56:36] + node priv = mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv) @[TLB.scala 57:17] + node priv_s = eq(priv, UInt<1>("h01")) @[TLB.scala 58:21] + node _T_275 = leq(priv, UInt<1>("h01")) @[TLB.scala 59:27] + node _T_277 = eq(io.ptw.status.debug, UInt<1>("h00")) @[TLB.scala 59:39] + node priv_uses_vm = and(_T_275, _T_277) @[TLB.scala 59:36] + node _T_279 = bits(io.ptw.ptbr.mode, 3, 3) @[TLB.scala 60:53] + node _T_280 = and(UInt<1>("h01"), _T_279) @[TLB.scala 60:34] + node _T_281 = and(_T_280, priv_uses_vm) @[TLB.scala 60:83] + node _T_283 = eq(io.req.bits.passthrough, UInt<1>("h00")) @[TLB.scala 60:102] + node vm_enabled = and(_T_281, _T_283) @[TLB.scala 60:99] + node vpn = bits(io.req.bits.vaddr, 39, 12) @[Misc.scala 123:7] + node pgOffset = bits(io.req.bits.vaddr, 11, 0) @[Misc.scala 123:18] + node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) @[TLB.scala 64:44] + node do_refill = and(UInt<1>("h01"), io.ptw.resp.valid) @[TLB.scala 65:33] + node _T_285 = bits(vpn, 19, 0) @[TLB.scala 67:47] + node _T_286 = mux(vm_enabled, ppns[8], _T_285) @[TLB.scala 67:20] + node mpu_ppn = mux(do_refill, refill_ppn, _T_286) @[TLB.scala 66:20] + node _T_287 = bits(io.req.bits.vaddr, 11, 0) @[TLB.scala 68:52] + node mpu_physaddr = cat(mpu_ppn, _T_287) @[Cat.scala 30:58] + node _T_289 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_290 = cvt(_T_289) @[Parameters.scala 117:49] + node _T_292 = and(_T_290, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_293 = asSInt(_T_292) @[Parameters.scala 117:52] + node _T_295 = eq(_T_293, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_297 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_298 = cvt(_T_297) @[Parameters.scala 117:49] + node _T_300 = and(_T_298, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_301 = asSInt(_T_300) @[Parameters.scala 117:52] + node _T_303 = eq(_T_301, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_305 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_306 = cvt(_T_305) @[Parameters.scala 117:49] + node _T_308 = and(_T_306, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_309 = asSInt(_T_308) @[Parameters.scala 117:52] + node _T_311 = eq(_T_309, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_313 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_314 = cvt(_T_313) @[Parameters.scala 117:49] + node _T_316 = and(_T_314, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_317 = asSInt(_T_316) @[Parameters.scala 117:52] + node _T_319 = eq(_T_317, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_321 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_322 = cvt(_T_321) @[Parameters.scala 117:49] + node _T_324 = and(_T_322, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_325 = asSInt(_T_324) @[Parameters.scala 117:52] + node _T_327 = eq(_T_325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_329 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_330 = cvt(_T_329) @[Parameters.scala 117:49] + node _T_332 = and(_T_330, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_333 = asSInt(_T_332) @[Parameters.scala 117:52] + node _T_335 = eq(_T_333, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_337 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_338 = cvt(_T_337) @[Parameters.scala 117:49] + node _T_340 = and(_T_338, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_341 = asSInt(_T_340) @[Parameters.scala 117:52] + node _T_343 = eq(_T_341, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_346 : UInt<1>[7] @[Parameters.scala 110:36] + _T_346 is invalid @[Parameters.scala 110:36] + _T_346[0] <= _T_295 @[Parameters.scala 110:36] + _T_346[1] <= _T_303 @[Parameters.scala 110:36] + _T_346[2] <= _T_311 @[Parameters.scala 110:36] + _T_346[3] <= _T_319 @[Parameters.scala 110:36] + _T_346[4] <= _T_327 @[Parameters.scala 110:36] + _T_346[5] <= _T_335 @[Parameters.scala 110:36] + _T_346[6] <= _T_343 @[Parameters.scala 110:36] + node _T_356 = or(_T_346[0], _T_346[1]) @[TLB.scala 69:67] + node _T_357 = or(_T_356, _T_346[2]) @[TLB.scala 69:67] + node _T_358 = or(_T_357, _T_346[3]) @[TLB.scala 69:67] + node _T_359 = or(_T_358, _T_346[4]) @[TLB.scala 69:67] + node _T_360 = or(_T_359, _T_346[5]) @[TLB.scala 69:67] + node legal_address = or(_T_360, _T_346[6]) @[TLB.scala 69:67] + node _T_362 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_363 = cvt(_T_362) @[Parameters.scala 117:49] + node _T_365 = and(_T_363, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_366 = asSInt(_T_365) @[Parameters.scala 117:52] + node _T_368 = eq(_T_366, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_370 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_371 = cvt(_T_370) @[Parameters.scala 117:49] + node _T_373 = and(_T_371, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_374 = asSInt(_T_373) @[Parameters.scala 117:52] + node _T_376 = eq(_T_374, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_378 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_379 = cvt(_T_378) @[Parameters.scala 117:49] + node _T_381 = and(_T_379, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_382 = asSInt(_T_381) @[Parameters.scala 117:52] + node _T_384 = eq(_T_382, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_386 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_387 = cvt(_T_386) @[Parameters.scala 117:49] + node _T_389 = and(_T_387, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_390 = asSInt(_T_389) @[Parameters.scala 117:52] + node _T_392 = eq(_T_390, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_394 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_395 = cvt(_T_394) @[Parameters.scala 117:49] + node _T_397 = and(_T_395, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_398 = asSInt(_T_397) @[Parameters.scala 117:52] + node _T_400 = eq(_T_398, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_402 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_403 = cvt(_T_402) @[Parameters.scala 117:49] + node _T_405 = and(_T_403, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_406 = asSInt(_T_405) @[Parameters.scala 117:52] + node _T_408 = eq(_T_406, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_410 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_411 = cvt(_T_410) @[Parameters.scala 117:49] + node _T_413 = and(_T_411, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_414 = asSInt(_T_413) @[Parameters.scala 117:52] + node _T_416 = eq(_T_414, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_419 : UInt<1>[7] @[Parameters.scala 112:36] + _T_419 is invalid @[Parameters.scala 112:36] + _T_419[0] <= _T_368 @[Parameters.scala 112:36] + _T_419[1] <= _T_376 @[Parameters.scala 112:36] + _T_419[2] <= _T_384 @[Parameters.scala 112:36] + _T_419[3] <= _T_392 @[Parameters.scala 112:36] + _T_419[4] <= _T_400 @[Parameters.scala 112:36] + _T_419[5] <= _T_408 @[Parameters.scala 112:36] + _T_419[6] <= _T_416 @[Parameters.scala 112:36] + node _T_437 = mux(_T_419[0], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_439 = mux(_T_419[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_441 = mux(_T_419[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_443 = mux(_T_419[3], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_445 = mux(_T_419[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_447 = mux(_T_419[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_449 = mux(_T_419[6], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_451 = or(_T_437, _T_439) @[Mux.scala 19:72] + node _T_452 = or(_T_451, _T_441) @[Mux.scala 19:72] + node _T_453 = or(_T_452, _T_443) @[Mux.scala 19:72] + node _T_454 = or(_T_453, _T_445) @[Mux.scala 19:72] + node _T_455 = or(_T_454, _T_447) @[Mux.scala 19:72] + node _T_456 = or(_T_455, _T_449) @[Mux.scala 19:72] + wire _T_458 : UInt<1> @[Mux.scala 19:72] + _T_458 is invalid @[Mux.scala 19:72] + _T_458 <= _T_456 @[Mux.scala 19:72] + node prot_r = and(legal_address, _T_458) @[TLB.scala 71:19] + node _T_460 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_461 = cvt(_T_460) @[Parameters.scala 117:49] + node _T_463 = and(_T_461, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_464 = asSInt(_T_463) @[Parameters.scala 117:52] + node _T_466 = eq(_T_464, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_468 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_469 = cvt(_T_468) @[Parameters.scala 117:49] + node _T_471 = and(_T_469, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_472 = asSInt(_T_471) @[Parameters.scala 117:52] + node _T_474 = eq(_T_472, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_476 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_477 = cvt(_T_476) @[Parameters.scala 117:49] + node _T_479 = and(_T_477, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_480 = asSInt(_T_479) @[Parameters.scala 117:52] + node _T_482 = eq(_T_480, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_484 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_485 = cvt(_T_484) @[Parameters.scala 117:49] + node _T_487 = and(_T_485, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_488 = asSInt(_T_487) @[Parameters.scala 117:52] + node _T_490 = eq(_T_488, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_492 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_493 = cvt(_T_492) @[Parameters.scala 117:49] + node _T_495 = and(_T_493, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_496 = asSInt(_T_495) @[Parameters.scala 117:52] + node _T_498 = eq(_T_496, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_500 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_501 = cvt(_T_500) @[Parameters.scala 117:49] + node _T_503 = and(_T_501, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_504 = asSInt(_T_503) @[Parameters.scala 117:52] + node _T_506 = eq(_T_504, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_508 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_509 = cvt(_T_508) @[Parameters.scala 117:49] + node _T_511 = and(_T_509, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_512 = asSInt(_T_511) @[Parameters.scala 117:52] + node _T_514 = eq(_T_512, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_517 : UInt<1>[7] @[Parameters.scala 112:36] + _T_517 is invalid @[Parameters.scala 112:36] + _T_517[0] <= _T_466 @[Parameters.scala 112:36] + _T_517[1] <= _T_474 @[Parameters.scala 112:36] + _T_517[2] <= _T_482 @[Parameters.scala 112:36] + _T_517[3] <= _T_490 @[Parameters.scala 112:36] + _T_517[4] <= _T_498 @[Parameters.scala 112:36] + _T_517[5] <= _T_506 @[Parameters.scala 112:36] + _T_517[6] <= _T_514 @[Parameters.scala 112:36] + node _T_535 = mux(_T_517[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_537 = mux(_T_517[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_539 = mux(_T_517[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_541 = mux(_T_517[3], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_543 = mux(_T_517[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_545 = mux(_T_517[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_547 = mux(_T_517[6], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_549 = or(_T_535, _T_537) @[Mux.scala 19:72] + node _T_550 = or(_T_549, _T_539) @[Mux.scala 19:72] + node _T_551 = or(_T_550, _T_541) @[Mux.scala 19:72] + node _T_552 = or(_T_551, _T_543) @[Mux.scala 19:72] + node _T_553 = or(_T_552, _T_545) @[Mux.scala 19:72] + node _T_554 = or(_T_553, _T_547) @[Mux.scala 19:72] + wire _T_556 : UInt<1> @[Mux.scala 19:72] + _T_556 is invalid @[Mux.scala 19:72] + _T_556 <= _T_554 @[Mux.scala 19:72] + node prot_w = and(legal_address, _T_556) @[TLB.scala 71:19] + node _T_558 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_559 = cvt(_T_558) @[Parameters.scala 117:49] + node _T_561 = and(_T_559, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_562 = asSInt(_T_561) @[Parameters.scala 117:52] + node _T_564 = eq(_T_562, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_566 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_567 = cvt(_T_566) @[Parameters.scala 117:49] + node _T_569 = and(_T_567, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_570 = asSInt(_T_569) @[Parameters.scala 117:52] + node _T_572 = eq(_T_570, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_574 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_575 = cvt(_T_574) @[Parameters.scala 117:49] + node _T_577 = and(_T_575, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_578 = asSInt(_T_577) @[Parameters.scala 117:52] + node _T_580 = eq(_T_578, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_582 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_583 = cvt(_T_582) @[Parameters.scala 117:49] + node _T_585 = and(_T_583, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_586 = asSInt(_T_585) @[Parameters.scala 117:52] + node _T_588 = eq(_T_586, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_590 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_591 = cvt(_T_590) @[Parameters.scala 117:49] + node _T_593 = and(_T_591, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_594 = asSInt(_T_593) @[Parameters.scala 117:52] + node _T_596 = eq(_T_594, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_598 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_599 = cvt(_T_598) @[Parameters.scala 117:49] + node _T_601 = and(_T_599, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_602 = asSInt(_T_601) @[Parameters.scala 117:52] + node _T_604 = eq(_T_602, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_606 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_607 = cvt(_T_606) @[Parameters.scala 117:49] + node _T_609 = and(_T_607, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_610 = asSInt(_T_609) @[Parameters.scala 117:52] + node _T_612 = eq(_T_610, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_615 : UInt<1>[7] @[Parameters.scala 112:36] + _T_615 is invalid @[Parameters.scala 112:36] + _T_615[0] <= _T_564 @[Parameters.scala 112:36] + _T_615[1] <= _T_572 @[Parameters.scala 112:36] + _T_615[2] <= _T_580 @[Parameters.scala 112:36] + _T_615[3] <= _T_588 @[Parameters.scala 112:36] + _T_615[4] <= _T_596 @[Parameters.scala 112:36] + _T_615[5] <= _T_604 @[Parameters.scala 112:36] + _T_615[6] <= _T_612 @[Parameters.scala 112:36] + node _T_633 = mux(_T_615[0], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_635 = mux(_T_615[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_637 = mux(_T_615[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_639 = mux(_T_615[3], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_641 = mux(_T_615[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_643 = mux(_T_615[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_645 = mux(_T_615[6], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_647 = or(_T_633, _T_635) @[Mux.scala 19:72] + node _T_648 = or(_T_647, _T_637) @[Mux.scala 19:72] + node _T_649 = or(_T_648, _T_639) @[Mux.scala 19:72] + node _T_650 = or(_T_649, _T_641) @[Mux.scala 19:72] + node _T_651 = or(_T_650, _T_643) @[Mux.scala 19:72] + node _T_652 = or(_T_651, _T_645) @[Mux.scala 19:72] + wire _T_654 : UInt<1> @[Mux.scala 19:72] + _T_654 is invalid @[Mux.scala 19:72] + _T_654 <= _T_652 @[Mux.scala 19:72] + node prot_x = and(legal_address, _T_654) @[TLB.scala 71:19] + node _T_656 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_657 = cvt(_T_656) @[Parameters.scala 117:49] + node _T_659 = and(_T_657, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_660 = asSInt(_T_659) @[Parameters.scala 117:52] + node _T_662 = eq(_T_660, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_664 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_665 = cvt(_T_664) @[Parameters.scala 117:49] + node _T_667 = and(_T_665, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_668 = asSInt(_T_667) @[Parameters.scala 117:52] + node _T_670 = eq(_T_668, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_672 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_673 = cvt(_T_672) @[Parameters.scala 117:49] + node _T_675 = and(_T_673, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_676 = asSInt(_T_675) @[Parameters.scala 117:52] + node _T_678 = eq(_T_676, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_680 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_681 = cvt(_T_680) @[Parameters.scala 117:49] + node _T_683 = and(_T_681, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_684 = asSInt(_T_683) @[Parameters.scala 117:52] + node _T_686 = eq(_T_684, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_689 = cvt(_T_688) @[Parameters.scala 117:49] + node _T_691 = and(_T_689, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_692 = asSInt(_T_691) @[Parameters.scala 117:52] + node _T_694 = eq(_T_692, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_696 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_697 = cvt(_T_696) @[Parameters.scala 117:49] + node _T_699 = and(_T_697, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_700 = asSInt(_T_699) @[Parameters.scala 117:52] + node _T_702 = eq(_T_700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_704 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_705 = cvt(_T_704) @[Parameters.scala 117:49] + node _T_707 = and(_T_705, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_708 = asSInt(_T_707) @[Parameters.scala 117:52] + node _T_710 = eq(_T_708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_713 : UInt<1>[7] @[Parameters.scala 112:36] + _T_713 is invalid @[Parameters.scala 112:36] + _T_713[0] <= _T_662 @[Parameters.scala 112:36] + _T_713[1] <= _T_670 @[Parameters.scala 112:36] + _T_713[2] <= _T_678 @[Parameters.scala 112:36] + _T_713[3] <= _T_686 @[Parameters.scala 112:36] + _T_713[4] <= _T_694 @[Parameters.scala 112:36] + _T_713[5] <= _T_702 @[Parameters.scala 112:36] + _T_713[6] <= _T_710 @[Parameters.scala 112:36] + node _T_731 = mux(_T_713[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_733 = mux(_T_713[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_735 = mux(_T_713[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_737 = mux(_T_713[3], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_739 = mux(_T_713[4], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_741 = mux(_T_713[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_743 = mux(_T_713[6], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_745 = or(_T_731, _T_733) @[Mux.scala 19:72] + node _T_746 = or(_T_745, _T_735) @[Mux.scala 19:72] + node _T_747 = or(_T_746, _T_737) @[Mux.scala 19:72] + node _T_748 = or(_T_747, _T_739) @[Mux.scala 19:72] + node _T_749 = or(_T_748, _T_741) @[Mux.scala 19:72] + node _T_750 = or(_T_749, _T_743) @[Mux.scala 19:72] + wire _T_752 : UInt<1> @[Mux.scala 19:72] + _T_752 is invalid @[Mux.scala 19:72] + _T_752 <= _T_750 @[Mux.scala 19:72] + node cacheable = and(legal_address, _T_752) @[TLB.scala 71:19] + wire _T_754 : UInt<1> + _T_754 is invalid + _T_754 <= UInt<1>("h00") + node _T_756 = eq(io.ptw.resp.bits.level, UInt<1>("h00")) @[TLB.scala 80:36] + when _T_756 : @[TLB.scala 80:43] + node _T_760 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_763 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_766 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_769 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_772 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_775 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + _T_754 <= UInt<1>("h00") @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node _T_777 = eq(io.ptw.resp.bits.level, UInt<1>("h01")) @[TLB.scala 80:36] + when _T_777 : @[TLB.scala 80:43] + node _T_779 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_780 = cvt(_T_779) @[Parameters.scala 117:49] + node _T_782 = and(_T_780, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_783 = asSInt(_T_782) @[Parameters.scala 117:52] + node _T_785 = eq(_T_783, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_787 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_788 = cvt(_T_787) @[Parameters.scala 117:49] + node _T_790 = and(_T_788, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_791 = asSInt(_T_790) @[Parameters.scala 117:52] + node _T_793 = eq(_T_791, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_795 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_796 = cvt(_T_795) @[Parameters.scala 117:49] + node _T_798 = and(_T_796, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_799 = asSInt(_T_798) @[Parameters.scala 117:52] + node _T_801 = eq(_T_799, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = or(UInt<1>("h00"), _T_785) @[TLBPermissions.scala 89:65] + node _T_812 = or(_T_811, _T_793) @[TLBPermissions.scala 89:65] + node _T_813 = or(_T_812, _T_801) @[TLBPermissions.scala 89:65] + node _T_814 = or(_T_813, _T_809) @[TLBPermissions.scala 89:65] + node _T_817 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_820 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_822 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_823 = cvt(_T_822) @[Parameters.scala 117:49] + node _T_825 = and(_T_823, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_826 = asSInt(_T_825) @[Parameters.scala 117:52] + node _T_828 = eq(_T_826, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_830 = or(UInt<1>("h00"), _T_828) @[TLBPermissions.scala 75:66] + node _T_832 = eq(_T_830, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_834 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_843 = cvt(_T_842) @[Parameters.scala 117:49] + node _T_845 = and(_T_843, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_846 = asSInt(_T_845) @[Parameters.scala 117:52] + node _T_848 = eq(_T_846, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_850 = or(UInt<1>("h00"), _T_840) @[TLBPermissions.scala 75:66] + node _T_851 = or(_T_850, _T_848) @[TLBPermissions.scala 75:66] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_855 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_863 = or(UInt<1>("h00"), _T_861) @[TLBPermissions.scala 73:66] + node _T_865 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_873 = or(UInt<1>("h00"), _T_871) @[TLBPermissions.scala 73:66] + _T_754 <= _T_814 @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node _T_875 = eq(io.ptw.resp.bits.level, UInt<2>("h02")) @[TLB.scala 80:36] + when _T_875 : @[TLB.scala 80:43] + node _T_877 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_878 = cvt(_T_877) @[Parameters.scala 117:49] + node _T_880 = and(_T_878, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_881 = asSInt(_T_880) @[Parameters.scala 117:52] + node _T_883 = eq(_T_881, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_885 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_893 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_894 = cvt(_T_893) @[Parameters.scala 117:49] + node _T_896 = and(_T_894, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_897 = asSInt(_T_896) @[Parameters.scala 117:52] + node _T_899 = eq(_T_897, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_901 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_902 = cvt(_T_901) @[Parameters.scala 117:49] + node _T_904 = and(_T_902, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_905 = asSInt(_T_904) @[Parameters.scala 117:52] + node _T_907 = eq(_T_905, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_909 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_910 = cvt(_T_909) @[Parameters.scala 117:49] + node _T_912 = and(_T_910, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_913 = asSInt(_T_912) @[Parameters.scala 117:52] + node _T_915 = eq(_T_913, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_917 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_918 = cvt(_T_917) @[Parameters.scala 117:49] + node _T_920 = and(_T_918, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_921 = asSInt(_T_920) @[Parameters.scala 117:52] + node _T_923 = eq(_T_921, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_925 = or(UInt<1>("h00"), _T_883) @[TLBPermissions.scala 89:65] + node _T_926 = or(_T_925, _T_891) @[TLBPermissions.scala 89:65] + node _T_927 = or(_T_926, _T_899) @[TLBPermissions.scala 89:65] + node _T_928 = or(_T_927, _T_907) @[TLBPermissions.scala 89:65] + node _T_929 = or(_T_928, _T_915) @[TLBPermissions.scala 89:65] + node _T_930 = or(_T_929, _T_923) @[TLBPermissions.scala 89:65] + node _T_933 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_935 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_936 = cvt(_T_935) @[Parameters.scala 117:49] + node _T_938 = and(_T_936, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_939 = asSInt(_T_938) @[Parameters.scala 117:52] + node _T_941 = eq(_T_939, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_943 = or(UInt<1>("h00"), _T_941) @[TLBPermissions.scala 75:66] + node _T_945 = eq(_T_943, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_947 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_948 = cvt(_T_947) @[Parameters.scala 117:49] + node _T_950 = and(_T_948, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_951 = asSInt(_T_950) @[Parameters.scala 117:52] + node _T_953 = eq(_T_951, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_955 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_956 = cvt(_T_955) @[Parameters.scala 117:49] + node _T_958 = and(_T_956, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_959 = asSInt(_T_958) @[Parameters.scala 117:52] + node _T_961 = eq(_T_959, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_963 = or(UInt<1>("h00"), _T_953) @[TLBPermissions.scala 75:66] + node _T_964 = or(_T_963, _T_961) @[TLBPermissions.scala 75:66] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_968 = xor(mpu_physaddr, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_976 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_977 = cvt(_T_976) @[Parameters.scala 117:49] + node _T_979 = and(_T_977, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_980 = asSInt(_T_979) @[Parameters.scala 117:52] + node _T_982 = eq(_T_980, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_984 = or(UInt<1>("h00"), _T_974) @[TLBPermissions.scala 73:66] + node _T_985 = or(_T_984, _T_982) @[TLBPermissions.scala 73:66] + node _T_987 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_988 = cvt(_T_987) @[Parameters.scala 117:49] + node _T_990 = and(_T_988, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_991 = asSInt(_T_990) @[Parameters.scala 117:52] + node _T_993 = eq(_T_991, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_995 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_996 = cvt(_T_995) @[Parameters.scala 117:49] + node _T_998 = and(_T_996, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_999 = asSInt(_T_998) @[Parameters.scala 117:52] + node _T_1001 = eq(_T_999, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1003 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = or(UInt<1>("h00"), _T_993) @[TLBPermissions.scala 73:66] + node _T_1012 = or(_T_1011, _T_1001) @[TLBPermissions.scala 73:66] + node _T_1013 = or(_T_1012, _T_1009) @[TLBPermissions.scala 73:66] + node _T_1015 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1016 = cvt(_T_1015) @[Parameters.scala 117:49] + node _T_1018 = and(_T_1016, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_1019 = asSInt(_T_1018) @[Parameters.scala 117:52] + node _T_1021 = eq(_T_1019, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1023 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1024 = cvt(_T_1023) @[Parameters.scala 117:49] + node _T_1026 = and(_T_1024, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_1027 = asSInt(_T_1026) @[Parameters.scala 117:52] + node _T_1029 = eq(_T_1027, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1031 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1032 = cvt(_T_1031) @[Parameters.scala 117:49] + node _T_1034 = and(_T_1032, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1035 = asSInt(_T_1034) @[Parameters.scala 117:52] + node _T_1037 = eq(_T_1035, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1039 = or(UInt<1>("h00"), _T_1021) @[TLBPermissions.scala 73:66] + node _T_1040 = or(_T_1039, _T_1029) @[TLBPermissions.scala 73:66] + node _T_1041 = or(_T_1040, _T_1037) @[TLBPermissions.scala 73:66] + _T_754 <= _T_930 @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node isSpecial = eq(_T_754, UInt<1>("h00")) @[TLB.scala 82:5] + node _T_1043 = bits(vpn, 26, 0) @[TLB.scala 85:45] + node lookup_tag = cat(io.ptw.ptbr.asid, _T_1043) @[Cat.scala 30:58] + node _T_1044 = bits(valid, 0, 0) @[TLB.scala 87:25] + node _T_1046 = lt(levels[0], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1047 = bits(tags[0], 26, 18) @[TLB.scala 90:55] + node _T_1048 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1049 = eq(_T_1047, _T_1048) @[TLB.scala 90:86] + node _T_1050 = or(_T_1046, _T_1049) @[TLB.scala 90:45] + node _T_1051 = and(_T_1044, _T_1050) @[TLB.scala 90:27] + node _T_1053 = lt(levels[0], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1054 = bits(tags[0], 17, 9) @[TLB.scala 90:55] + node _T_1055 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1056 = eq(_T_1054, _T_1055) @[TLB.scala 90:86] + node _T_1057 = or(_T_1053, _T_1056) @[TLB.scala 90:45] + node _T_1058 = and(_T_1051, _T_1057) @[TLB.scala 90:27] + node _T_1060 = lt(levels[0], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1061 = bits(tags[0], 8, 0) @[TLB.scala 90:55] + node _T_1062 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1063 = eq(_T_1061, _T_1062) @[TLB.scala 90:86] + node _T_1064 = or(_T_1060, _T_1063) @[TLB.scala 90:45] + node _T_1065 = and(_T_1058, _T_1064) @[TLB.scala 90:27] + node hitsVec_0 = and(vm_enabled, _T_1065) @[TLB.scala 86:62] + node _T_1066 = bits(valid, 1, 1) @[TLB.scala 87:25] + node _T_1068 = lt(levels[1], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1069 = bits(tags[1], 26, 18) @[TLB.scala 90:55] + node _T_1070 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1071 = eq(_T_1069, _T_1070) @[TLB.scala 90:86] + node _T_1072 = or(_T_1068, _T_1071) @[TLB.scala 90:45] + node _T_1073 = and(_T_1066, _T_1072) @[TLB.scala 90:27] + node _T_1075 = lt(levels[1], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1076 = bits(tags[1], 17, 9) @[TLB.scala 90:55] + node _T_1077 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1078 = eq(_T_1076, _T_1077) @[TLB.scala 90:86] + node _T_1079 = or(_T_1075, _T_1078) @[TLB.scala 90:45] + node _T_1080 = and(_T_1073, _T_1079) @[TLB.scala 90:27] + node _T_1082 = lt(levels[1], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1083 = bits(tags[1], 8, 0) @[TLB.scala 90:55] + node _T_1084 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1085 = eq(_T_1083, _T_1084) @[TLB.scala 90:86] + node _T_1086 = or(_T_1082, _T_1085) @[TLB.scala 90:45] + node _T_1087 = and(_T_1080, _T_1086) @[TLB.scala 90:27] + node hitsVec_1 = and(vm_enabled, _T_1087) @[TLB.scala 86:62] + node _T_1088 = bits(valid, 2, 2) @[TLB.scala 87:25] + node _T_1090 = lt(levels[2], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1091 = bits(tags[2], 26, 18) @[TLB.scala 90:55] + node _T_1092 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1093 = eq(_T_1091, _T_1092) @[TLB.scala 90:86] + node _T_1094 = or(_T_1090, _T_1093) @[TLB.scala 90:45] + node _T_1095 = and(_T_1088, _T_1094) @[TLB.scala 90:27] + node _T_1097 = lt(levels[2], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1098 = bits(tags[2], 17, 9) @[TLB.scala 90:55] + node _T_1099 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1100 = eq(_T_1098, _T_1099) @[TLB.scala 90:86] + node _T_1101 = or(_T_1097, _T_1100) @[TLB.scala 90:45] + node _T_1102 = and(_T_1095, _T_1101) @[TLB.scala 90:27] + node _T_1104 = lt(levels[2], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1105 = bits(tags[2], 8, 0) @[TLB.scala 90:55] + node _T_1106 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1107 = eq(_T_1105, _T_1106) @[TLB.scala 90:86] + node _T_1108 = or(_T_1104, _T_1107) @[TLB.scala 90:45] + node _T_1109 = and(_T_1102, _T_1108) @[TLB.scala 90:27] + node hitsVec_2 = and(vm_enabled, _T_1109) @[TLB.scala 86:62] + node _T_1110 = bits(valid, 3, 3) @[TLB.scala 87:25] + node _T_1112 = lt(levels[3], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1113 = bits(tags[3], 26, 18) @[TLB.scala 90:55] + node _T_1114 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1115 = eq(_T_1113, _T_1114) @[TLB.scala 90:86] + node _T_1116 = or(_T_1112, _T_1115) @[TLB.scala 90:45] + node _T_1117 = and(_T_1110, _T_1116) @[TLB.scala 90:27] + node _T_1119 = lt(levels[3], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1120 = bits(tags[3], 17, 9) @[TLB.scala 90:55] + node _T_1121 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1122 = eq(_T_1120, _T_1121) @[TLB.scala 90:86] + node _T_1123 = or(_T_1119, _T_1122) @[TLB.scala 90:45] + node _T_1124 = and(_T_1117, _T_1123) @[TLB.scala 90:27] + node _T_1126 = lt(levels[3], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1127 = bits(tags[3], 8, 0) @[TLB.scala 90:55] + node _T_1128 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1129 = eq(_T_1127, _T_1128) @[TLB.scala 90:86] + node _T_1130 = or(_T_1126, _T_1129) @[TLB.scala 90:45] + node _T_1131 = and(_T_1124, _T_1130) @[TLB.scala 90:27] + node hitsVec_3 = and(vm_enabled, _T_1131) @[TLB.scala 86:62] + node _T_1132 = bits(valid, 4, 4) @[TLB.scala 87:25] + node _T_1134 = lt(levels[4], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1135 = bits(tags[4], 26, 18) @[TLB.scala 90:55] + node _T_1136 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1137 = eq(_T_1135, _T_1136) @[TLB.scala 90:86] + node _T_1138 = or(_T_1134, _T_1137) @[TLB.scala 90:45] + node _T_1139 = and(_T_1132, _T_1138) @[TLB.scala 90:27] + node _T_1141 = lt(levels[4], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1142 = bits(tags[4], 17, 9) @[TLB.scala 90:55] + node _T_1143 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1144 = eq(_T_1142, _T_1143) @[TLB.scala 90:86] + node _T_1145 = or(_T_1141, _T_1144) @[TLB.scala 90:45] + node _T_1146 = and(_T_1139, _T_1145) @[TLB.scala 90:27] + node _T_1148 = lt(levels[4], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1149 = bits(tags[4], 8, 0) @[TLB.scala 90:55] + node _T_1150 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1151 = eq(_T_1149, _T_1150) @[TLB.scala 90:86] + node _T_1152 = or(_T_1148, _T_1151) @[TLB.scala 90:45] + node _T_1153 = and(_T_1146, _T_1152) @[TLB.scala 90:27] + node hitsVec_4 = and(vm_enabled, _T_1153) @[TLB.scala 86:62] + node _T_1154 = bits(valid, 5, 5) @[TLB.scala 87:25] + node _T_1156 = lt(levels[5], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1157 = bits(tags[5], 26, 18) @[TLB.scala 90:55] + node _T_1158 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1159 = eq(_T_1157, _T_1158) @[TLB.scala 90:86] + node _T_1160 = or(_T_1156, _T_1159) @[TLB.scala 90:45] + node _T_1161 = and(_T_1154, _T_1160) @[TLB.scala 90:27] + node _T_1163 = lt(levels[5], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1164 = bits(tags[5], 17, 9) @[TLB.scala 90:55] + node _T_1165 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1166 = eq(_T_1164, _T_1165) @[TLB.scala 90:86] + node _T_1167 = or(_T_1163, _T_1166) @[TLB.scala 90:45] + node _T_1168 = and(_T_1161, _T_1167) @[TLB.scala 90:27] + node _T_1170 = lt(levels[5], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1171 = bits(tags[5], 8, 0) @[TLB.scala 90:55] + node _T_1172 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1173 = eq(_T_1171, _T_1172) @[TLB.scala 90:86] + node _T_1174 = or(_T_1170, _T_1173) @[TLB.scala 90:45] + node _T_1175 = and(_T_1168, _T_1174) @[TLB.scala 90:27] + node hitsVec_5 = and(vm_enabled, _T_1175) @[TLB.scala 86:62] + node _T_1176 = bits(valid, 6, 6) @[TLB.scala 87:25] + node _T_1178 = lt(levels[6], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1179 = bits(tags[6], 26, 18) @[TLB.scala 90:55] + node _T_1180 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1181 = eq(_T_1179, _T_1180) @[TLB.scala 90:86] + node _T_1182 = or(_T_1178, _T_1181) @[TLB.scala 90:45] + node _T_1183 = and(_T_1176, _T_1182) @[TLB.scala 90:27] + node _T_1185 = lt(levels[6], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1186 = bits(tags[6], 17, 9) @[TLB.scala 90:55] + node _T_1187 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1188 = eq(_T_1186, _T_1187) @[TLB.scala 90:86] + node _T_1189 = or(_T_1185, _T_1188) @[TLB.scala 90:45] + node _T_1190 = and(_T_1183, _T_1189) @[TLB.scala 90:27] + node _T_1192 = lt(levels[6], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1193 = bits(tags[6], 8, 0) @[TLB.scala 90:55] + node _T_1194 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1195 = eq(_T_1193, _T_1194) @[TLB.scala 90:86] + node _T_1196 = or(_T_1192, _T_1195) @[TLB.scala 90:45] + node _T_1197 = and(_T_1190, _T_1196) @[TLB.scala 90:27] + node hitsVec_6 = and(vm_enabled, _T_1197) @[TLB.scala 86:62] + node _T_1198 = bits(valid, 7, 7) @[TLB.scala 87:25] + node _T_1200 = lt(levels[7], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1201 = bits(tags[7], 26, 18) @[TLB.scala 90:55] + node _T_1202 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1203 = eq(_T_1201, _T_1202) @[TLB.scala 90:86] + node _T_1204 = or(_T_1200, _T_1203) @[TLB.scala 90:45] + node _T_1205 = and(_T_1198, _T_1204) @[TLB.scala 90:27] + node _T_1207 = lt(levels[7], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1208 = bits(tags[7], 17, 9) @[TLB.scala 90:55] + node _T_1209 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1210 = eq(_T_1208, _T_1209) @[TLB.scala 90:86] + node _T_1211 = or(_T_1207, _T_1210) @[TLB.scala 90:45] + node _T_1212 = and(_T_1205, _T_1211) @[TLB.scala 90:27] + node _T_1214 = lt(levels[7], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1215 = bits(tags[7], 8, 0) @[TLB.scala 90:55] + node _T_1216 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1217 = eq(_T_1215, _T_1216) @[TLB.scala 90:86] + node _T_1218 = or(_T_1214, _T_1217) @[TLB.scala 90:45] + node _T_1219 = and(_T_1212, _T_1218) @[TLB.scala 90:27] + node hitsVec_7 = and(vm_enabled, _T_1219) @[TLB.scala 86:62] + node _T_1220 = bits(valid, 8, 8) @[TLB.scala 87:25] + node _T_1222 = lt(levels[8], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1223 = bits(tags[8], 26, 18) @[TLB.scala 90:55] + node _T_1224 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1225 = eq(_T_1223, _T_1224) @[TLB.scala 90:86] + node _T_1226 = or(_T_1222, _T_1225) @[TLB.scala 90:45] + node _T_1227 = and(_T_1220, _T_1226) @[TLB.scala 90:27] + node _T_1229 = lt(levels[8], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1230 = bits(tags[8], 17, 9) @[TLB.scala 90:55] + node _T_1231 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1232 = eq(_T_1230, _T_1231) @[TLB.scala 90:86] + node _T_1233 = or(_T_1229, _T_1232) @[TLB.scala 90:45] + node _T_1234 = and(_T_1227, _T_1233) @[TLB.scala 90:27] + node _T_1236 = lt(levels[8], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1237 = bits(tags[8], 8, 0) @[TLB.scala 90:55] + node _T_1238 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1239 = eq(_T_1237, _T_1238) @[TLB.scala 90:86] + node _T_1240 = or(_T_1236, _T_1239) @[TLB.scala 90:45] + node _T_1241 = and(_T_1234, _T_1240) @[TLB.scala 90:27] + node hitsVec_8 = and(vm_enabled, _T_1241) @[TLB.scala 86:62] + node hitsVec_9 = eq(vm_enabled, UInt<1>("h00")) @[TLB.scala 93:9] + node _T_1243 = cat(hitsVec_1, hitsVec_0) @[Cat.scala 30:58] + node _T_1244 = cat(hitsVec_4, hitsVec_3) @[Cat.scala 30:58] + node _T_1245 = cat(_T_1244, hitsVec_2) @[Cat.scala 30:58] + node _T_1246 = cat(_T_1245, _T_1243) @[Cat.scala 30:58] + node _T_1247 = cat(hitsVec_6, hitsVec_5) @[Cat.scala 30:58] + node _T_1248 = cat(hitsVec_9, hitsVec_8) @[Cat.scala 30:58] + node _T_1249 = cat(_T_1248, hitsVec_7) @[Cat.scala 30:58] + node _T_1250 = cat(_T_1249, _T_1247) @[Cat.scala 30:58] + node hits = cat(_T_1250, _T_1246) @[Cat.scala 30:58] + node _T_1252 = mux(hitsVec_0, levels[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1254 = mux(hitsVec_1, levels[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1256 = mux(hitsVec_2, levels[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1258 = mux(hitsVec_3, levels[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1260 = mux(hitsVec_4, levels[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1262 = mux(hitsVec_5, levels[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1264 = mux(hitsVec_6, levels[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1266 = mux(hitsVec_7, levels[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1268 = mux(hitsVec_8, levels[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1270 = or(_T_1252, _T_1254) @[Mux.scala 19:72] + node _T_1271 = or(_T_1270, _T_1256) @[Mux.scala 19:72] + node _T_1272 = or(_T_1271, _T_1258) @[Mux.scala 19:72] + node _T_1273 = or(_T_1272, _T_1260) @[Mux.scala 19:72] + node _T_1274 = or(_T_1273, _T_1262) @[Mux.scala 19:72] + node _T_1275 = or(_T_1274, _T_1264) @[Mux.scala 19:72] + node _T_1276 = or(_T_1275, _T_1266) @[Mux.scala 19:72] + node _T_1277 = or(_T_1276, _T_1268) @[Mux.scala 19:72] + wire level : UInt<2> @[Mux.scala 19:72] + level is invalid @[Mux.scala 19:72] + level <= _T_1277 @[Mux.scala 19:72] + node _T_1280 = mux(hitsVec_0, ppns[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1282 = mux(hitsVec_1, ppns[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1284 = mux(hitsVec_2, ppns[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1286 = mux(hitsVec_3, ppns[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1288 = mux(hitsVec_4, ppns[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1290 = mux(hitsVec_5, ppns[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1292 = mux(hitsVec_6, ppns[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1294 = mux(hitsVec_7, ppns[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1296 = mux(hitsVec_8, ppns[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1298 = or(_T_1280, _T_1282) @[Mux.scala 19:72] + node _T_1299 = or(_T_1298, _T_1284) @[Mux.scala 19:72] + node _T_1300 = or(_T_1299, _T_1286) @[Mux.scala 19:72] + node _T_1301 = or(_T_1300, _T_1288) @[Mux.scala 19:72] + node _T_1302 = or(_T_1301, _T_1290) @[Mux.scala 19:72] + node _T_1303 = or(_T_1302, _T_1292) @[Mux.scala 19:72] + node _T_1304 = or(_T_1303, _T_1294) @[Mux.scala 19:72] + node _T_1305 = or(_T_1304, _T_1296) @[Mux.scala 19:72] + wire partialPPN : UInt<20> @[Mux.scala 19:72] + partialPPN is invalid @[Mux.scala 19:72] + partialPPN <= _T_1305 @[Mux.scala 19:72] + node _T_1307 = mux(vm_enabled, partialPPN, vpn) @[TLB.scala 98:18] + node _T_1308 = bits(_T_1307, 26, 18) @[TLB.scala 98:47] + node _T_1310 = lt(level, UInt<1>("h01")) @[TLB.scala 100:33] + node _T_1312 = mux(_T_1310, vpn, UInt<1>("h00")) @[TLB.scala 100:26] + node _T_1313 = or(_T_1312, partialPPN) @[TLB.scala 100:48] + node _T_1314 = bits(_T_1313, 17, 9) @[TLB.scala 100:61] + node _T_1315 = cat(_T_1308, _T_1314) @[Cat.scala 30:58] + node _T_1317 = lt(level, UInt<2>("h02")) @[TLB.scala 100:33] + node _T_1319 = mux(_T_1317, vpn, UInt<1>("h00")) @[TLB.scala 100:26] + node _T_1320 = or(_T_1319, partialPPN) @[TLB.scala 100:48] + node _T_1321 = bits(_T_1320, 8, 0) @[TLB.scala 100:61] + node ppn = cat(_T_1315, _T_1321) @[Cat.scala 30:58] + reg u_array : UInt<9>, clock @[TLB.scala 105:20] + reg sw_array : UInt<9>, clock @[TLB.scala 106:21] + reg sx_array : UInt<9>, clock @[TLB.scala 107:21] + reg sr_array : UInt<9>, clock @[TLB.scala 108:21] + reg xr_array : UInt<9>, clock @[TLB.scala 109:21] + reg cash_array : UInt<8>, clock @[TLB.scala 110:23] + when do_refill : @[TLB.scala 111:20] + node _T_1329 = mux(isSpecial, UInt<4>("h08"), r_refill_waddr) @[TLB.scala 112:20] + ppns[_T_1329] <= io.ptw.resp.bits.pte.ppn @[TLB.scala 114:17] + tags[_T_1329] <= r_refill_tag @[TLB.scala 115:17] + levels[_T_1329] <= io.ptw.resp.bits.level @[TLB.scala 116:19] + node _T_1334 = dshl(UInt<1>("h01"), _T_1329) @[OneHot.scala 47:11] + node _T_1335 = or(valid, _T_1334) @[TLB.scala 119:20] + valid <= _T_1335 @[TLB.scala 119:11] + node _T_1336 = or(u_array, _T_1334) @[TLB.scala 120:35] + node _T_1337 = not(_T_1334) @[TLB.scala 120:53] + node _T_1338 = and(u_array, _T_1337) @[TLB.scala 120:51] + node _T_1339 = mux(io.ptw.resp.bits.pte.u, _T_1336, _T_1338) @[TLB.scala 120:19] + u_array <= _T_1339 @[TLB.scala 120:13] + node _T_1341 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1342 = and(io.ptw.resp.bits.pte.x, _T_1341) @[PTW.scala 56:44] + node _T_1343 = or(io.ptw.resp.bits.pte.r, _T_1342) @[PTW.scala 56:38] + node _T_1344 = and(io.ptw.resp.bits.pte.v, _T_1343) @[PTW.scala 56:32] + node _T_1345 = and(_T_1344, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1346 = and(_T_1345, io.ptw.resp.bits.pte.w) @[PTW.scala 61:35] + node _T_1347 = and(_T_1346, io.ptw.resp.bits.pte.d) @[PTW.scala 61:40] + node _T_1348 = or(isSpecial, prot_w) @[TLB.scala 121:44] + node _T_1349 = and(_T_1347, _T_1348) @[TLB.scala 121:30] + node _T_1350 = or(sw_array, _T_1334) @[TLB.scala 121:65] + node _T_1351 = not(_T_1334) @[TLB.scala 121:84] + node _T_1352 = and(sw_array, _T_1351) @[TLB.scala 121:82] + node _T_1353 = mux(_T_1349, _T_1350, _T_1352) @[TLB.scala 121:20] + sw_array <= _T_1353 @[TLB.scala 121:14] + node _T_1355 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1356 = and(io.ptw.resp.bits.pte.x, _T_1355) @[PTW.scala 56:44] + node _T_1357 = or(io.ptw.resp.bits.pte.r, _T_1356) @[PTW.scala 56:38] + node _T_1358 = and(io.ptw.resp.bits.pte.v, _T_1357) @[PTW.scala 56:32] + node _T_1359 = and(_T_1358, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1360 = and(_T_1359, io.ptw.resp.bits.pte.x) @[PTW.scala 62:35] + node _T_1361 = or(isSpecial, prot_x) @[TLB.scala 122:44] + node _T_1362 = and(_T_1360, _T_1361) @[TLB.scala 122:30] + node _T_1363 = or(sx_array, _T_1334) @[TLB.scala 122:65] + node _T_1364 = not(_T_1334) @[TLB.scala 122:84] + node _T_1365 = and(sx_array, _T_1364) @[TLB.scala 122:82] + node _T_1366 = mux(_T_1362, _T_1363, _T_1365) @[TLB.scala 122:20] + sx_array <= _T_1366 @[TLB.scala 122:14] + node _T_1368 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1369 = and(io.ptw.resp.bits.pte.x, _T_1368) @[PTW.scala 56:44] + node _T_1370 = or(io.ptw.resp.bits.pte.r, _T_1369) @[PTW.scala 56:38] + node _T_1371 = and(io.ptw.resp.bits.pte.v, _T_1370) @[PTW.scala 56:32] + node _T_1372 = and(_T_1371, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1373 = and(_T_1372, io.ptw.resp.bits.pte.r) @[PTW.scala 60:35] + node _T_1374 = or(isSpecial, prot_r) @[TLB.scala 123:44] + node _T_1375 = and(_T_1373, _T_1374) @[TLB.scala 123:30] + node _T_1376 = or(sr_array, _T_1334) @[TLB.scala 123:65] + node _T_1377 = not(_T_1334) @[TLB.scala 123:84] + node _T_1378 = and(sr_array, _T_1377) @[TLB.scala 123:82] + node _T_1379 = mux(_T_1375, _T_1376, _T_1378) @[TLB.scala 123:20] + sr_array <= _T_1379 @[TLB.scala 123:14] + node _T_1381 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1382 = and(io.ptw.resp.bits.pte.x, _T_1381) @[PTW.scala 56:44] + node _T_1383 = or(io.ptw.resp.bits.pte.r, _T_1382) @[PTW.scala 56:38] + node _T_1384 = and(io.ptw.resp.bits.pte.v, _T_1383) @[PTW.scala 56:32] + node _T_1385 = and(_T_1384, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1386 = and(_T_1385, io.ptw.resp.bits.pte.x) @[PTW.scala 62:35] + node _T_1387 = or(isSpecial, prot_r) @[TLB.scala 124:44] + node _T_1388 = and(_T_1386, _T_1387) @[TLB.scala 124:30] + node _T_1389 = or(xr_array, _T_1334) @[TLB.scala 124:65] + node _T_1390 = not(_T_1334) @[TLB.scala 124:84] + node _T_1391 = and(xr_array, _T_1390) @[TLB.scala 124:82] + node _T_1392 = mux(_T_1388, _T_1389, _T_1391) @[TLB.scala 124:20] + xr_array <= _T_1392 @[TLB.scala 124:14] + node _T_1393 = or(cash_array, _T_1334) @[TLB.scala 125:45] + node _T_1394 = not(_T_1334) @[TLB.scala 125:66] + node _T_1395 = and(cash_array, _T_1394) @[TLB.scala 125:64] + node _T_1396 = mux(cacheable, _T_1393, _T_1395) @[TLB.scala 125:22] + cash_array <= _T_1396 @[TLB.scala 125:16] + skip @[TLB.scala 111:20] + reg _T_1398 : UInt<8>, clock @[Replacement.scala 42:22] + node _T_1399 = not(valid) @[TLB.scala 129:31] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[TLB.scala 129:31] + node _T_1403 = eq(_T_1401, UInt<1>("h00")) @[TLB.scala 129:24] + node _T_1404 = not(valid) @[TLB.scala 129:53] + node _T_1405 = bits(_T_1404, 0, 0) @[OneHot.scala 39:40] + node _T_1406 = bits(_T_1404, 1, 1) @[OneHot.scala 39:40] + node _T_1407 = bits(_T_1404, 2, 2) @[OneHot.scala 39:40] + node _T_1408 = bits(_T_1404, 3, 3) @[OneHot.scala 39:40] + node _T_1409 = bits(_T_1404, 4, 4) @[OneHot.scala 39:40] + node _T_1410 = bits(_T_1404, 5, 5) @[OneHot.scala 39:40] + node _T_1411 = bits(_T_1404, 6, 6) @[OneHot.scala 39:40] + node _T_1412 = bits(_T_1404, 7, 7) @[OneHot.scala 39:40] + node _T_1413 = bits(_T_1404, 8, 8) @[OneHot.scala 39:40] + node _T_1423 = mux(_T_1412, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 31:69] + node _T_1424 = mux(_T_1411, UInt<3>("h06"), _T_1423) @[Mux.scala 31:69] + node _T_1425 = mux(_T_1410, UInt<3>("h05"), _T_1424) @[Mux.scala 31:69] + node _T_1426 = mux(_T_1409, UInt<3>("h04"), _T_1425) @[Mux.scala 31:69] + node _T_1427 = mux(_T_1408, UInt<2>("h03"), _T_1426) @[Mux.scala 31:69] + node _T_1428 = mux(_T_1407, UInt<2>("h02"), _T_1427) @[Mux.scala 31:69] + node _T_1429 = mux(_T_1406, UInt<1>("h01"), _T_1428) @[Mux.scala 31:69] + node _T_1430 = mux(_T_1405, UInt<1>("h00"), _T_1429) @[Mux.scala 31:69] + node _T_1432 = dshr(_T_1398, UInt<1>("h01")) @[Replacement.scala 60:27] + node _T_1433 = bits(_T_1432, 0, 0) @[Replacement.scala 60:27] + node _T_1434 = cat(UInt<1>("h01"), _T_1433) @[Cat.scala 30:58] + node _T_1435 = dshr(_T_1398, _T_1434) @[Replacement.scala 60:27] + node _T_1436 = bits(_T_1435, 0, 0) @[Replacement.scala 60:27] + node _T_1437 = cat(_T_1434, _T_1436) @[Cat.scala 30:58] + node _T_1438 = dshr(_T_1398, _T_1437) @[Replacement.scala 60:27] + node _T_1439 = bits(_T_1438, 0, 0) @[Replacement.scala 60:27] + node _T_1440 = cat(_T_1437, _T_1439) @[Cat.scala 30:58] + node _T_1441 = bits(_T_1440, 2, 0) @[Replacement.scala 61:8] + node repl_waddr = mux(_T_1403, _T_1430, _T_1441) @[TLB.scala 129:23] + node _T_1443 = mux(io.ptw.status.pum, u_array, UInt<1>("h00")) @[TLB.scala 131:33] + node _T_1444 = not(_T_1443) @[TLB.scala 131:29] + node priv_ok = mux(priv_s, _T_1444, u_array) @[TLB.scala 131:20] + node _T_1445 = not(prot_w) @[TLB.scala 132:41] + node _T_1446 = shl(_T_1445, 8) @[TLB.scala 132:49] + node _T_1447 = not(_T_1446) @[TLB.scala 132:39] + node _T_1448 = and(priv_ok, _T_1447) @[TLB.scala 132:37] + node _T_1449 = and(_T_1448, sw_array) @[TLB.scala 132:66] + node w_array = cat(prot_w, _T_1449) @[Cat.scala 30:58] + node _T_1450 = not(prot_x) @[TLB.scala 133:41] + node _T_1451 = shl(_T_1450, 8) @[TLB.scala 133:49] + node _T_1452 = not(_T_1451) @[TLB.scala 133:39] + node _T_1453 = and(priv_ok, _T_1452) @[TLB.scala 133:37] + node _T_1454 = and(_T_1453, sx_array) @[TLB.scala 133:66] + node x_array = cat(prot_x, _T_1454) @[Cat.scala 30:58] + node _T_1455 = not(prot_r) @[TLB.scala 134:41] + node _T_1456 = shl(_T_1455, 8) @[TLB.scala 134:49] + node _T_1457 = not(_T_1456) @[TLB.scala 134:39] + node _T_1458 = and(priv_ok, _T_1457) @[TLB.scala 134:37] + node _T_1460 = mux(io.ptw.status.mxr, xr_array, UInt<1>("h00")) @[TLB.scala 134:83] + node _T_1461 = or(sr_array, _T_1460) @[TLB.scala 134:78] + node _T_1462 = and(_T_1458, _T_1461) @[TLB.scala 134:66] + node r_array = cat(prot_r, _T_1462) @[Cat.scala 30:58] + node _T_1463 = cat(cacheable, cacheable) @[Cat.scala 30:58] + node c_array = cat(_T_1463, cash_array) @[Cat.scala 30:58] + node _T_1464 = bits(vpn, 27, 27) @[TLB.scala 139:13] + node _T_1465 = bits(vpn, 26, 26) @[TLB.scala 139:30] + node bad_va = neq(_T_1464, _T_1465) @[TLB.scala 139:23] + node _T_1466 = bits(hits, 8, 0) @[TLB.scala 140:21] + node tlb_hit = neq(_T_1466, UInt<1>("h00")) @[TLB.scala 140:41] + node _T_1469 = eq(bad_va, UInt<1>("h00")) @[TLB.scala 141:32] + node _T_1470 = and(vm_enabled, _T_1469) @[TLB.scala 141:29] + node _T_1472 = eq(tlb_hit, UInt<1>("h00")) @[TLB.scala 141:43] + node tlb_miss = and(_T_1470, _T_1472) @[TLB.scala 141:40] + node _T_1474 = eq(tlb_miss, UInt<1>("h00")) @[TLB.scala 143:25] + node _T_1475 = and(io.req.valid, _T_1474) @[TLB.scala 143:22] + node _T_1476 = bits(hits, 8, 8) @[TLB.scala 143:43] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[TLB.scala 143:38] + node _T_1479 = and(_T_1475, _T_1478) @[TLB.scala 143:35] + when _T_1479 : @[TLB.scala 143:59] + node _T_1480 = bits(hits, 7, 0) @[TLB.scala 144:30] + node _T_1481 = bits(_T_1480, 7, 4) @[OneHot.scala 26:18] + node _T_1482 = bits(_T_1480, 3, 0) @[OneHot.scala 27:18] + node _T_1484 = neq(_T_1481, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1485 = or(_T_1481, _T_1482) @[OneHot.scala 28:28] + node _T_1486 = bits(_T_1485, 3, 2) @[OneHot.scala 26:18] + node _T_1487 = bits(_T_1485, 1, 0) @[OneHot.scala 27:18] + node _T_1489 = neq(_T_1486, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1490 = or(_T_1486, _T_1487) @[OneHot.scala 28:28] + node _T_1491 = bits(_T_1490, 1, 1) @[CircuitMath.scala 30:8] + node _T_1492 = cat(_T_1489, _T_1491) @[Cat.scala 30:58] + node _T_1493 = cat(_T_1484, _T_1492) @[Cat.scala 30:58] + node _T_1495 = bits(_T_1493, 2, 2) @[Replacement.scala 50:20] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1499 = dshl(UInt<1>("h01"), UInt<1>("h01")) @[Replacement.scala 51:37] + node _T_1500 = or(_T_1398, _T_1499) @[Replacement.scala 51:37] + node _T_1501 = not(_T_1398) @[Replacement.scala 51:37] + node _T_1502 = or(_T_1501, _T_1499) @[Replacement.scala 51:37] + node _T_1503 = not(_T_1502) @[Replacement.scala 51:37] + node _T_1504 = mux(_T_1497, _T_1500, _T_1503) @[Replacement.scala 51:37] + node _T_1505 = cat(UInt<1>("h01"), _T_1495) @[Cat.scala 30:58] + node _T_1506 = bits(_T_1493, 1, 1) @[Replacement.scala 50:20] + node _T_1508 = eq(_T_1506, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1510 = dshl(UInt<1>("h01"), _T_1505) @[Replacement.scala 51:37] + node _T_1511 = or(_T_1504, _T_1510) @[Replacement.scala 51:37] + node _T_1512 = not(_T_1504) @[Replacement.scala 51:37] + node _T_1513 = or(_T_1512, _T_1510) @[Replacement.scala 51:37] + node _T_1514 = not(_T_1513) @[Replacement.scala 51:37] + node _T_1515 = mux(_T_1508, _T_1511, _T_1514) @[Replacement.scala 51:37] + node _T_1516 = cat(_T_1505, _T_1506) @[Cat.scala 30:58] + node _T_1517 = bits(_T_1493, 0, 0) @[Replacement.scala 50:20] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1521 = dshl(UInt<1>("h01"), _T_1516) @[Replacement.scala 51:37] + node _T_1522 = or(_T_1515, _T_1521) @[Replacement.scala 51:37] + node _T_1523 = not(_T_1515) @[Replacement.scala 51:37] + node _T_1524 = or(_T_1523, _T_1521) @[Replacement.scala 51:37] + node _T_1525 = not(_T_1524) @[Replacement.scala 51:37] + node _T_1526 = mux(_T_1519, _T_1522, _T_1525) @[Replacement.scala 51:37] + node _T_1527 = cat(_T_1516, _T_1517) @[Cat.scala 30:58] + _T_1398 <= _T_1526 @[Replacement.scala 44:15] + skip @[TLB.scala 143:59] + node _T_1528 = bits(hits, 8, 0) @[TLB.scala 152:42] + node _T_1529 = bits(_T_1528, 3, 0) @[Package.scala 62:39] + node _T_1530 = bits(_T_1529, 1, 0) @[Package.scala 62:39] + node _T_1531 = bits(_T_1530, 0, 0) @[Package.scala 62:39] + node _T_1532 = bits(_T_1531, 0, 0) @[Package.scala 59:20] + node _T_1534 = bits(_T_1530, 1, 1) @[Package.scala 63:41] + node _T_1535 = bits(_T_1534, 0, 0) @[Package.scala 59:20] + node _T_1537 = or(_T_1532, _T_1535) @[Package.scala 64:18] + node _T_1538 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1539 = and(_T_1532, _T_1535) @[Package.scala 64:63] + node _T_1540 = or(_T_1538, _T_1539) @[Package.scala 64:51] + node _T_1541 = bits(_T_1529, 3, 2) @[Package.scala 63:41] + node _T_1542 = bits(_T_1541, 0, 0) @[Package.scala 62:39] + node _T_1543 = bits(_T_1542, 0, 0) @[Package.scala 59:20] + node _T_1545 = bits(_T_1541, 1, 1) @[Package.scala 63:41] + node _T_1546 = bits(_T_1545, 0, 0) @[Package.scala 59:20] + node _T_1548 = or(_T_1543, _T_1546) @[Package.scala 64:18] + node _T_1549 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1550 = and(_T_1543, _T_1546) @[Package.scala 64:63] + node _T_1551 = or(_T_1549, _T_1550) @[Package.scala 64:51] + node _T_1552 = or(_T_1537, _T_1548) @[Package.scala 64:18] + node _T_1553 = or(_T_1540, _T_1551) @[Package.scala 64:39] + node _T_1554 = and(_T_1537, _T_1548) @[Package.scala 64:63] + node _T_1555 = or(_T_1553, _T_1554) @[Package.scala 64:51] + node _T_1556 = bits(_T_1528, 8, 4) @[Package.scala 63:41] + node _T_1557 = bits(_T_1556, 1, 0) @[Package.scala 62:39] + node _T_1558 = bits(_T_1557, 0, 0) @[Package.scala 62:39] + node _T_1559 = bits(_T_1558, 0, 0) @[Package.scala 59:20] + node _T_1561 = bits(_T_1557, 1, 1) @[Package.scala 63:41] + node _T_1562 = bits(_T_1561, 0, 0) @[Package.scala 59:20] + node _T_1564 = or(_T_1559, _T_1562) @[Package.scala 64:18] + node _T_1565 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1566 = and(_T_1559, _T_1562) @[Package.scala 64:63] + node _T_1567 = or(_T_1565, _T_1566) @[Package.scala 64:51] + node _T_1568 = bits(_T_1556, 4, 2) @[Package.scala 63:41] + node _T_1569 = bits(_T_1568, 0, 0) @[Package.scala 62:39] + node _T_1570 = bits(_T_1569, 0, 0) @[Package.scala 59:20] + node _T_1572 = bits(_T_1568, 2, 1) @[Package.scala 63:41] + node _T_1573 = bits(_T_1572, 0, 0) @[Package.scala 62:39] + node _T_1574 = bits(_T_1573, 0, 0) @[Package.scala 59:20] + node _T_1576 = bits(_T_1572, 1, 1) @[Package.scala 63:41] + node _T_1577 = bits(_T_1576, 0, 0) @[Package.scala 59:20] + node _T_1579 = or(_T_1574, _T_1577) @[Package.scala 64:18] + node _T_1580 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1581 = and(_T_1574, _T_1577) @[Package.scala 64:63] + node _T_1582 = or(_T_1580, _T_1581) @[Package.scala 64:51] + node _T_1583 = or(_T_1570, _T_1579) @[Package.scala 64:18] + node _T_1584 = or(UInt<1>("h00"), _T_1582) @[Package.scala 64:39] + node _T_1585 = and(_T_1570, _T_1579) @[Package.scala 64:63] + node _T_1586 = or(_T_1584, _T_1585) @[Package.scala 64:51] + node _T_1587 = or(_T_1564, _T_1583) @[Package.scala 64:18] + node _T_1588 = or(_T_1567, _T_1586) @[Package.scala 64:39] + node _T_1589 = and(_T_1564, _T_1583) @[Package.scala 64:63] + node _T_1590 = or(_T_1588, _T_1589) @[Package.scala 64:51] + node _T_1591 = or(_T_1552, _T_1587) @[Package.scala 64:18] + node _T_1592 = or(_T_1555, _T_1590) @[Package.scala 64:39] + node _T_1593 = and(_T_1552, _T_1587) @[Package.scala 64:63] + node multipleHits = or(_T_1592, _T_1593) @[Package.scala 64:51] + node _T_1594 = eq(state, UInt<2>("h00")) @[TLB.scala 154:25] + io.req.ready <= _T_1594 @[TLB.scala 154:16] + node _T_1595 = not(r_array) @[TLB.scala 155:33] + node _T_1596 = and(_T_1595, hits) @[TLB.scala 155:42] + node _T_1598 = neq(_T_1596, UInt<1>("h00")) @[TLB.scala 155:50] + node _T_1599 = or(bad_va, _T_1598) @[TLB.scala 155:29] + io.resp.xcpt_ld <= _T_1599 @[TLB.scala 155:19] + node _T_1600 = not(w_array) @[TLB.scala 156:33] + node _T_1601 = and(_T_1600, hits) @[TLB.scala 156:42] + node _T_1603 = neq(_T_1601, UInt<1>("h00")) @[TLB.scala 156:50] + node _T_1604 = or(bad_va, _T_1603) @[TLB.scala 156:29] + io.resp.xcpt_st <= _T_1604 @[TLB.scala 156:19] + node _T_1605 = not(x_array) @[TLB.scala 157:33] + node _T_1606 = and(_T_1605, hits) @[TLB.scala 157:42] + node _T_1608 = neq(_T_1606, UInt<1>("h00")) @[TLB.scala 157:50] + node _T_1609 = or(bad_va, _T_1608) @[TLB.scala 157:29] + io.resp.xcpt_if <= _T_1609 @[TLB.scala 157:19] + node _T_1610 = and(c_array, hits) @[TLB.scala 158:33] + node _T_1612 = neq(_T_1610, UInt<1>("h00")) @[TLB.scala 158:41] + io.resp.cacheable <= _T_1612 @[TLB.scala 158:21] + node _T_1613 = or(do_refill, tlb_miss) @[TLB.scala 159:29] + node _T_1614 = or(_T_1613, multipleHits) @[TLB.scala 159:41] + io.resp.miss <= _T_1614 @[TLB.scala 159:16] + node _T_1615 = cat(ppn, pgOffset) @[Cat.scala 30:58] + io.resp.paddr <= _T_1615 @[TLB.scala 160:17] + node _T_1616 = eq(state, UInt<2>("h01")) @[TLB.scala 162:29] + io.ptw.req.valid <= _T_1616 @[TLB.scala 162:20] + io.ptw.req.bits <- io.ptw.status @[TLB.scala 163:19] + io.ptw.req.bits.addr <= r_refill_tag @[TLB.scala 164:24] + io.ptw.req.bits.store <= r_req.store @[TLB.scala 165:25] + io.ptw.req.bits.fetch <= r_req.instruction @[TLB.scala 166:25] + node _T_1617 = and(io.req.ready, io.req.valid) @[Decoupled.scala 30:37] + node _T_1618 = and(_T_1617, tlb_miss) @[TLB.scala 169:25] + when _T_1618 : @[TLB.scala 169:38] + state <= UInt<2>("h01") @[TLB.scala 170:13] + r_refill_tag <= lookup_tag @[TLB.scala 171:20] + r_refill_waddr <= repl_waddr @[TLB.scala 172:22] + r_req <- io.req.bits @[TLB.scala 173:13] + skip @[TLB.scala 169:38] + node _T_1619 = eq(state, UInt<2>("h01")) @[TLB.scala 175:17] + when _T_1619 : @[TLB.scala 175:32] + when io.ptw.invalidate : @[TLB.scala 176:32] + state <= UInt<2>("h00") @[TLB.scala 177:15] + skip @[TLB.scala 176:32] + when io.ptw.req.ready : @[TLB.scala 179:31] + state <= UInt<2>("h02") @[TLB.scala 180:15] + when io.ptw.invalidate : @[TLB.scala 181:34] + state <= UInt<2>("h03") @[TLB.scala 181:42] + skip @[TLB.scala 181:34] + skip @[TLB.scala 179:31] + skip @[TLB.scala 175:32] + node _T_1620 = eq(state, UInt<2>("h02")) @[TLB.scala 184:17] + node _T_1621 = and(_T_1620, io.ptw.invalidate) @[TLB.scala 184:28] + when _T_1621 : @[TLB.scala 184:50] + state <= UInt<2>("h03") @[TLB.scala 185:13] + skip @[TLB.scala 184:50] + when io.ptw.resp.valid : @[TLB.scala 187:30] + state <= UInt<2>("h00") @[TLB.scala 188:13] + skip @[TLB.scala 187:30] + node _T_1622 = or(io.ptw.invalidate, multipleHits) @[TLB.scala 191:29] + when _T_1622 : @[TLB.scala 191:46] + valid <= UInt<1>("h00") @[TLB.scala 192:13] + skip @[TLB.scala 191:46] + + module L1MetadataArray : + input clock : Clock + input reset : UInt<1> + output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : {coh : {state : UInt<2>}, tag : UInt<20>}}}, resp : {coh : {state : UInt<2>}, tag : UInt<20>}[4]} + + io is invalid + io is invalid + wire _T_6 : {state : UInt<2>} @[Metadata.scala 160:20] + _T_6 is invalid @[Metadata.scala 160:20] + _T_6.state <= UInt<2>("h00") @[Metadata.scala 161:16] + wire rstVal : {coh : {state : UInt<2>}, tag : UInt<20>} @[HellaCache.scala 202:20] + rstVal is invalid @[HellaCache.scala 202:20] + rstVal.tag <= UInt<1>("h00") @[HellaCache.scala 203:14] + rstVal.coh <- _T_6 @[HellaCache.scala 204:14] + reg rst_cnt : UInt<7>, clock with : (reset => (reset, UInt<7>("h00"))) @[HellaCache.scala 226:20] + node rst = lt(rst_cnt, UInt<7>("h040")) @[HellaCache.scala 227:21] + node waddr = mux(rst, rst_cnt, io.write.bits.idx) @[HellaCache.scala 228:18] + node _T_155 = mux(rst, rstVal, io.write.bits.data) @[HellaCache.scala 229:18] + node wdata = cat(_T_155.coh.state, _T_155.tag) @[HellaCache.scala 229:52] + node _T_160 = or(rst, UInt<1>("h00")) @[HellaCache.scala 230:23] + node _T_162 = asSInt(io.write.bits.way_en) @[HellaCache.scala 230:75] + node _T_163 = mux(_T_160, asSInt(UInt<1>("h01")), _T_162) @[HellaCache.scala 230:18] + node wmask_0 = bits(_T_163, 0, 0) @[HellaCache.scala 230:83] + node wmask_1 = bits(_T_163, 1, 1) @[HellaCache.scala 230:83] + node wmask_2 = bits(_T_163, 2, 2) @[HellaCache.scala 230:83] + node wmask_3 = bits(_T_163, 3, 3) @[HellaCache.scala 230:83] + node _T_165 = or(rst, UInt<1>("h00")) @[HellaCache.scala 231:23] + node _T_167 = asSInt(io.read.bits.way_en) @[HellaCache.scala 231:74] + node _T_168 = mux(_T_165, asSInt(UInt<1>("h01")), _T_167) @[HellaCache.scala 231:18] + node rmask_0 = bits(_T_168, 0, 0) @[HellaCache.scala 231:82] + node rmask_1 = bits(_T_168, 1, 1) @[HellaCache.scala 231:82] + node rmask_2 = bits(_T_168, 2, 2) @[HellaCache.scala 231:82] + node rmask_3 = bits(_T_168, 3, 3) @[HellaCache.scala 231:82] + when rst : @[HellaCache.scala 232:14] + node _T_170 = add(rst_cnt, UInt<1>("h01")) @[HellaCache.scala 232:34] + node _T_171 = tail(_T_170, 1) @[HellaCache.scala 232:34] + rst_cnt <= _T_171 @[HellaCache.scala 232:24] + skip @[HellaCache.scala 232:14] + smem _T_182 : UInt<22>[4][64] @[HellaCache.scala 246:25] + node _T_183 = or(rst, io.write.valid) @[HellaCache.scala 247:15] + when _T_183 : @[HellaCache.scala 247:34] + wire _T_186 : UInt<22>[4] @[HellaCache.scala 248:43] + _T_186 is invalid @[HellaCache.scala 248:43] + _T_186[0] <= wdata @[HellaCache.scala 248:43] + _T_186[1] <= wdata @[HellaCache.scala 248:43] + _T_186[2] <= wdata @[HellaCache.scala 248:43] + _T_186[3] <= wdata @[HellaCache.scala 248:43] + node _T_193 = bits(waddr, 5, 0) + write mport _T_194 = _T_182[_T_193], clock + when wmask_0 : + _T_194[0] <= _T_186[0] skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 + when wmask_1 : + _T_194[1] <= _T_186[1] skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip + when wmask_2 : + _T_194[2] <= _T_186[2] skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 + when wmask_3 : + _T_194[3] <= _T_186[3] skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") + skip @[HellaCache.scala 247:34] + wire _T_207 : UInt + _T_207 is invalid + when io.read.valid : + _T_207 <= io.read.bits.idx + node _T_209 = or(_T_207, UInt<6>("h00")) + node _T_210 = bits(_T_209, 5, 0) + read mport _T_211 = _T_182[_T_210], clock + skip + wire _T_227 : {coh : {state : UInt<2>}, tag : UInt<20>} @[HellaCache.scala 250:81] + _T_227 is invalid @[HellaCache.scala 250:81] + wire _T_232 : UInt<22> + _T_232 is invalid + _T_232 <= _T_211[0] + node _T_233 = bits(_T_232, 19, 0) @[HellaCache.scala 250:81] + _T_227.tag <= _T_233 @[HellaCache.scala 250:81] + node _T_234 = bits(_T_232, 21, 20) @[HellaCache.scala 250:81] + wire _T_236 : UInt<2> + _T_236 is invalid + _T_236 <= _T_234 + node _T_237 = bits(_T_236, 1, 0) @[HellaCache.scala 250:81] + _T_227.coh.state <= _T_237 @[HellaCache.scala 250:81] + wire _T_242 : {coh : {state : UInt<2>}, tag : UInt<20>} @[HellaCache.scala 250:81] + _T_242 is invalid @[HellaCache.scala 250:81] + wire _T_247 : UInt<22> + _T_247 is invalid + _T_247 <= _T_211[1] + node _T_248 = bits(_T_247, 19, 0) @[HellaCache.scala 250:81] + _T_242.tag <= _T_248 @[HellaCache.scala 250:81] + node _T_249 = bits(_T_247, 21, 20) @[HellaCache.scala 250:81] + wire _T_251 : UInt<2> + _T_251 is invalid + _T_251 <= _T_249 + node _T_252 = bits(_T_251, 1, 0) @[HellaCache.scala 250:81] + _T_242.coh.state <= _T_252 @[HellaCache.scala 250:81] + wire _T_257 : {coh : {state : UInt<2>}, tag : UInt<20>} @[HellaCache.scala 250:81] + _T_257 is invalid @[HellaCache.scala 250:81] + wire _T_262 : UInt<22> + _T_262 is invalid + _T_262 <= _T_211[2] + node _T_263 = bits(_T_262, 19, 0) @[HellaCache.scala 250:81] + _T_257.tag <= _T_263 @[HellaCache.scala 250:81] + node _T_264 = bits(_T_262, 21, 20) @[HellaCache.scala 250:81] + wire _T_266 : UInt<2> + _T_266 is invalid + _T_266 <= _T_264 + node _T_267 = bits(_T_266, 1, 0) @[HellaCache.scala 250:81] + _T_257.coh.state <= _T_267 @[HellaCache.scala 250:81] + wire _T_272 : {coh : {state : UInt<2>}, tag : UInt<20>} @[HellaCache.scala 250:81] + _T_272 is invalid @[HellaCache.scala 250:81] + wire _T_277 : UInt<22> + _T_277 is invalid + _T_277 <= _T_211[3] + node _T_278 = bits(_T_277, 19, 0) @[HellaCache.scala 250:81] + _T_272.tag <= _T_278 @[HellaCache.scala 250:81] + node _T_279 = bits(_T_277, 21, 20) @[HellaCache.scala 250:81] + wire _T_281 : UInt<2> + _T_281 is invalid + _T_281 <= _T_279 + node _T_282 = bits(_T_281, 1, 0) @[HellaCache.scala 250:81] + _T_272.coh.state <= _T_282 @[HellaCache.scala 250:81] + io.resp[0] <- _T_227 @[HellaCache.scala 250:13] + io.resp[1] <- _T_242 @[HellaCache.scala 250:13] + io.resp[2] <- _T_257 @[HellaCache.scala 250:13] + io.resp[3] <- _T_272 @[HellaCache.scala 250:13] + node _T_284 = eq(rst, UInt<1>("h00")) @[HellaCache.scala 253:20] + node _T_286 = eq(io.write.valid, UInt<1>("h00")) @[HellaCache.scala 253:28] + node _T_287 = and(_T_284, _T_286) @[HellaCache.scala 253:25] + io.read.ready <= _T_287 @[HellaCache.scala 253:17] + node _T_289 = eq(rst, UInt<1>("h00")) @[HellaCache.scala 254:21] + io.write.ready <= _T_289 @[HellaCache.scala 254:18] + + module AMOALU : + input clock : Clock + input reset : UInt<1> + output io : {flip addr : UInt<3>, flip cmd : UInt<5>, flip typ : UInt<2>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} + + io is invalid + io is invalid + node _T_14 = bits(io.typ, 1, 0) @[AmoAlu.scala 12:17] + node _T_16 = eq(_T_14, UInt<2>("h02")) @[AmoAlu.scala 28:19] + node _T_17 = bits(io.rhs, 31, 0) @[AmoAlu.scala 28:66] + node _T_18 = cat(_T_17, _T_17) @[Cat.scala 30:58] + node rhs = mux(_T_16, _T_18, io.rhs) @[AmoAlu.scala 28:13] + node _T_20 = eq(io.cmd, UInt<4>("h0c")) @[AmoAlu.scala 73:22] + node _T_22 = eq(io.cmd, UInt<4>("h0d")) @[AmoAlu.scala 73:45] + node sgned = or(_T_20, _T_22) @[AmoAlu.scala 73:35] + node _T_24 = eq(io.cmd, UInt<4>("h0d")) @[AmoAlu.scala 74:20] + node _T_26 = eq(io.cmd, UInt<4>("h0f")) @[AmoAlu.scala 74:43] + node max = or(_T_24, _T_26) @[AmoAlu.scala 74:33] + node _T_28 = eq(io.cmd, UInt<4>("h0c")) @[AmoAlu.scala 75:20] + node _T_30 = eq(io.cmd, UInt<4>("h0e")) @[AmoAlu.scala 75:43] + node min = or(_T_28, _T_30) @[AmoAlu.scala 75:33] + node _T_32 = not(UInt<64>("h00")) @[AmoAlu.scala 80:18] + node _T_33 = bits(io.addr, 2, 2) @[AmoAlu.scala 80:40] + node _T_34 = shl(_T_33, 31) @[AmoAlu.scala 80:44] + node _T_35 = xor(_T_32, _T_34) @[AmoAlu.scala 80:30] + node _T_36 = and(io.lhs, _T_35) @[AmoAlu.scala 81:15] + node _T_37 = and(rhs, _T_35) @[AmoAlu.scala 81:30] + node _T_38 = add(_T_36, _T_37) @[AmoAlu.scala 81:23] + node adder_out = tail(_T_38, 1) @[AmoAlu.scala 81:23] + node _T_39 = bits(io.typ, 0, 0) @[AmoAlu.scala 87:25] + node _T_41 = eq(_T_39, UInt<1>("h00")) @[AmoAlu.scala 87:18] + node _T_42 = bits(io.addr, 2, 2) @[AmoAlu.scala 88:41] + node _T_44 = eq(_T_42, UInt<1>("h00")) @[AmoAlu.scala 88:33] + node _T_45 = and(_T_41, _T_44) @[AmoAlu.scala 88:30] + node _T_46 = bits(io.lhs, 31, 31) @[AmoAlu.scala 88:52] + node _T_47 = bits(io.lhs, 63, 63) @[AmoAlu.scala 88:64] + node _T_48 = mux(_T_45, _T_46, _T_47) @[AmoAlu.scala 88:24] + node _T_49 = bits(io.addr, 2, 2) @[AmoAlu.scala 89:41] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[AmoAlu.scala 89:33] + node _T_52 = and(_T_41, _T_51) @[AmoAlu.scala 89:30] + node _T_53 = bits(rhs, 31, 31) @[AmoAlu.scala 89:49] + node _T_54 = bits(rhs, 63, 63) @[AmoAlu.scala 89:58] + node _T_55 = mux(_T_52, _T_53, _T_54) @[AmoAlu.scala 89:24] + node _T_56 = bits(io.lhs, 31, 0) @[AmoAlu.scala 90:25] + node _T_57 = bits(rhs, 31, 0) @[AmoAlu.scala 90:37] + node _T_58 = lt(_T_56, _T_57) @[AmoAlu.scala 90:32] + node _T_59 = bits(io.lhs, 63, 32) @[AmoAlu.scala 91:25] + node _T_60 = bits(rhs, 63, 32) @[AmoAlu.scala 91:38] + node _T_61 = lt(_T_59, _T_60) @[AmoAlu.scala 91:33] + node _T_62 = bits(io.lhs, 63, 32) @[AmoAlu.scala 92:25] + node _T_63 = bits(rhs, 63, 32) @[AmoAlu.scala 92:40] + node _T_64 = eq(_T_62, _T_63) @[AmoAlu.scala 92:33] + node _T_65 = bits(io.addr, 2, 2) @[AmoAlu.scala 93:37] + node _T_66 = mux(_T_65, _T_61, _T_58) @[AmoAlu.scala 93:29] + node _T_67 = and(_T_64, _T_58) @[AmoAlu.scala 93:72] + node _T_68 = or(_T_61, _T_67) @[AmoAlu.scala 93:63] + node _T_69 = mux(_T_41, _T_66, _T_68) @[AmoAlu.scala 93:19] + node _T_70 = eq(_T_48, _T_55) @[AmoAlu.scala 94:19] + node _T_71 = mux(sgned, _T_48, _T_55) @[AmoAlu.scala 94:39] + node less = mux(_T_70, _T_69, _T_71) @[AmoAlu.scala 94:10] + node _T_73 = eq(io.cmd, UInt<4>("h08")) @[AmoAlu.scala 97:24] + node _T_75 = eq(io.cmd, UInt<4>("h0b")) @[AmoAlu.scala 98:24] + node _T_76 = and(io.lhs, rhs) @[AmoAlu.scala 98:45] + node _T_78 = eq(io.cmd, UInt<4>("h0a")) @[AmoAlu.scala 99:24] + node _T_79 = or(io.lhs, rhs) @[AmoAlu.scala 99:45] + node _T_81 = eq(io.cmd, UInt<4>("h09")) @[AmoAlu.scala 100:24] + node _T_82 = xor(io.lhs, rhs) @[AmoAlu.scala 100:45] + node _T_83 = mux(less, min, max) @[AmoAlu.scala 101:20] + node _T_85 = eq(_T_14, UInt<1>("h00")) @[AmoAlu.scala 28:19] + node _T_86 = bits(io.rhs, 7, 0) @[AmoAlu.scala 28:66] + node _T_87 = cat(_T_86, _T_86) @[Cat.scala 30:58] + node _T_88 = cat(_T_87, _T_87) @[Cat.scala 30:58] + node _T_89 = cat(_T_88, _T_88) @[Cat.scala 30:58] + node _T_91 = eq(_T_14, UInt<1>("h01")) @[AmoAlu.scala 28:19] + node _T_92 = bits(io.rhs, 15, 0) @[AmoAlu.scala 28:66] + node _T_93 = cat(_T_92, _T_92) @[Cat.scala 30:58] + node _T_94 = cat(_T_93, _T_93) @[Cat.scala 30:58] + node _T_96 = eq(_T_14, UInt<2>("h02")) @[AmoAlu.scala 28:19] + node _T_97 = bits(io.rhs, 31, 0) @[AmoAlu.scala 28:66] + node _T_98 = cat(_T_97, _T_97) @[Cat.scala 30:58] + node _T_99 = mux(_T_96, _T_98, io.rhs) @[AmoAlu.scala 28:13] + node _T_100 = mux(_T_91, _T_94, _T_99) @[AmoAlu.scala 28:13] + node _T_101 = mux(_T_85, _T_89, _T_100) @[AmoAlu.scala 28:13] + node _T_102 = mux(_T_83, io.lhs, _T_101) @[AmoAlu.scala 101:16] + node _T_103 = mux(_T_81, _T_82, _T_102) @[AmoAlu.scala 100:16] + node _T_104 = mux(_T_78, _T_79, _T_103) @[AmoAlu.scala 99:16] + node _T_105 = mux(_T_75, _T_76, _T_104) @[AmoAlu.scala 98:16] + node out = mux(_T_73, adder_out, _T_105) @[AmoAlu.scala 97:16] + node _T_107 = bits(io.addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_109 = mux(_T_107, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_111 = geq(_T_14, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_114 = mux(_T_111, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_115 = or(_T_109, _T_114) @[AmoAlu.scala 19:46] + node _T_116 = bits(io.addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_118 = mux(_T_116, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_119 = cat(_T_115, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(io.addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_122 = mux(_T_120, _T_119, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_124 = geq(_T_14, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_127 = mux(_T_124, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_128 = or(_T_122, _T_127) @[AmoAlu.scala 19:46] + node _T_129 = bits(io.addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_131 = mux(_T_129, UInt<1>("h00"), _T_119) @[AmoAlu.scala 20:22] + node _T_132 = cat(_T_128, _T_131) @[Cat.scala 30:58] + node _T_133 = bits(io.addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_135 = mux(_T_133, _T_132, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_137 = geq(_T_14, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_140 = mux(_T_137, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_141 = or(_T_135, _T_140) @[AmoAlu.scala 19:46] + node _T_142 = bits(io.addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_144 = mux(_T_142, UInt<1>("h00"), _T_132) @[AmoAlu.scala 20:22] + node _T_145 = cat(_T_141, _T_144) @[Cat.scala 30:58] + node _T_146 = bits(_T_145, 0, 0) @[Bitwise.scala 27:51] + node _T_147 = bits(_T_145, 1, 1) @[Bitwise.scala 27:51] + node _T_148 = bits(_T_145, 2, 2) @[Bitwise.scala 27:51] + node _T_149 = bits(_T_145, 3, 3) @[Bitwise.scala 27:51] + node _T_150 = bits(_T_145, 4, 4) @[Bitwise.scala 27:51] + node _T_151 = bits(_T_145, 5, 5) @[Bitwise.scala 27:51] + node _T_152 = bits(_T_145, 6, 6) @[Bitwise.scala 27:51] + node _T_153 = bits(_T_145, 7, 7) @[Bitwise.scala 27:51] + node _T_154 = bits(_T_146, 0, 0) @[Bitwise.scala 71:15] + node _T_157 = mux(_T_154, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_158 = bits(_T_147, 0, 0) @[Bitwise.scala 71:15] + node _T_161 = mux(_T_158, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_162 = bits(_T_148, 0, 0) @[Bitwise.scala 71:15] + node _T_165 = mux(_T_162, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_166 = bits(_T_149, 0, 0) @[Bitwise.scala 71:15] + node _T_169 = mux(_T_166, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_170 = bits(_T_150, 0, 0) @[Bitwise.scala 71:15] + node _T_173 = mux(_T_170, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_174 = bits(_T_151, 0, 0) @[Bitwise.scala 71:15] + node _T_177 = mux(_T_174, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_178 = bits(_T_152, 0, 0) @[Bitwise.scala 71:15] + node _T_181 = mux(_T_178, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_182 = bits(_T_153, 0, 0) @[Bitwise.scala 71:15] + node _T_185 = mux(_T_182, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_186 = cat(_T_161, _T_157) @[Cat.scala 30:58] + node _T_187 = cat(_T_169, _T_165) @[Cat.scala 30:58] + node _T_188 = cat(_T_187, _T_186) @[Cat.scala 30:58] + node _T_189 = cat(_T_177, _T_173) @[Cat.scala 30:58] + node _T_190 = cat(_T_185, _T_181) @[Cat.scala 30:58] + node _T_191 = cat(_T_190, _T_189) @[Cat.scala 30:58] + node wmask = cat(_T_191, _T_188) @[Cat.scala 30:58] + node _T_192 = and(wmask, out) @[AmoAlu.scala 105:19] + node _T_193 = not(wmask) @[AmoAlu.scala 105:27] + node _T_194 = and(_T_193, io.lhs) @[AmoAlu.scala 105:34] + node _T_195 = or(_T_192, _T_194) @[AmoAlu.scala 105:25] + io.out <= _T_195 @[AmoAlu.scala 105:10] + + module DCache_dcache : + input clock : Clock + input reset : UInt<1> + output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>}}, flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, mem : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + inst grantackq of Queue_35 @[DCache.scala 48:25] + grantackq.io is invalid + grantackq.clock <= clock + grantackq.reset <= reset + wire _T_570 : UInt<1> @[Replacement.scala 15:29] + _T_570 is invalid @[Replacement.scala 15:29] + _T_570 <= UInt<1>("h00") @[Replacement.scala 16:11] + reg _T_573 : UInt<16>, clock with : (reset => (reset, UInt<16>("h01"))) @[LFSR.scala 22:19] + when _T_570 : @[LFSR.scala 23:22] + node _T_574 = bits(_T_573, 0, 0) @[LFSR.scala 23:40] + node _T_575 = bits(_T_573, 2, 2) @[LFSR.scala 23:48] + node _T_576 = xor(_T_574, _T_575) @[LFSR.scala 23:43] + node _T_577 = bits(_T_573, 3, 3) @[LFSR.scala 23:56] + node _T_578 = xor(_T_576, _T_577) @[LFSR.scala 23:51] + node _T_579 = bits(_T_573, 5, 5) @[LFSR.scala 23:64] + node _T_580 = xor(_T_578, _T_579) @[LFSR.scala 23:59] + node _T_581 = bits(_T_573, 15, 1) @[LFSR.scala 23:73] + node _T_582 = cat(_T_580, _T_581) @[Cat.scala 30:58] + _T_573 <= _T_582 @[LFSR.scala 23:29] + skip @[LFSR.scala 23:22] + inst metaReadArb of Arbiter @[DCache.scala 53:27] + metaReadArb.io is invalid + metaReadArb.clock <= clock + metaReadArb.reset <= reset + inst metaWriteArb of Arbiter_1 @[DCache.scala 54:28] + metaWriteArb.io is invalid + metaWriteArb.clock <= clock + metaWriteArb.reset <= reset + inst data of DCacheDataArray @[DCache.scala 57:20] + data.io is invalid + data.clock <= clock + data.reset <= reset + inst dataArb of Arbiter_2 @[DCache.scala 58:23] + dataArb.io is invalid + dataArb.clock <= clock + dataArb.reset <= reset + data.io.req <- dataArb.io.out @[DCache.scala 59:15] + dataArb.io.out.ready <= UInt<1>("h01") @[DCache.scala 60:24] + node _T_602 = and(io.cpu.req.ready, io.cpu.req.valid) @[Decoupled.scala 30:37] + reg s1_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 62:21] + s1_valid <= _T_602 @[DCache.scala 62:21] + node _T_604 = and(io.mem.0.b.ready, io.mem.0.b.valid) @[Decoupled.scala 30:37] + reg s1_probe : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 63:21] + s1_probe <= _T_604 @[DCache.scala 63:21] + node _T_606 = and(io.mem.0.b.ready, io.mem.0.b.valid) @[Decoupled.scala 30:37] + reg probe_bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}, clock @[Reg.scala 34:16] + when _T_606 : @[Reg.scala 35:19] + probe_bits <- io.mem.0.b.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire s1_nack : UInt<1> + s1_nack is invalid + s1_nack <= UInt<1>("h00") + node _T_624 = eq(io.cpu.s1_kill, UInt<1>("h00")) @[DCache.scala 66:37] + node _T_625 = and(s1_valid, _T_624) @[DCache.scala 66:34] + node _T_626 = cat(io.cpu.xcpt.pf.ld, io.cpu.xcpt.pf.st) @[DCache.scala 66:69] + node _T_627 = cat(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) @[DCache.scala 66:69] + node _T_628 = cat(_T_627, _T_626) @[DCache.scala 66:69] + node _T_630 = neq(_T_628, UInt<1>("h00")) @[DCache.scala 66:76] + node _T_632 = eq(_T_630, UInt<1>("h00")) @[DCache.scala 66:56] + node s1_valid_masked = and(_T_625, _T_632) @[DCache.scala 66:53] + node _T_634 = eq(s1_nack, UInt<1>("h00")) @[DCache.scala 67:48] + node s1_valid_not_nacked = and(s1_valid_masked, _T_634) @[DCache.scala 67:45] + reg s1_req : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clock @[DCache.scala 68:19] + when metaReadArb.io.out.valid : @[DCache.scala 69:35] + s1_req <- io.cpu.req.bits @[DCache.scala 70:12] + node _T_641 = shr(io.cpu.req.bits.addr, 12) @[DCache.scala 71:45] + node _T_642 = bits(io.cpu.req.bits.addr, 5, 0) @[DCache.scala 71:108] + node _T_643 = cat(_T_641, metaReadArb.io.out.bits.idx) @[Cat.scala 30:58] + node _T_644 = cat(_T_643, _T_642) @[Cat.scala 30:58] + s1_req.addr <= _T_644 @[DCache.scala 71:17] + skip @[DCache.scala 69:35] + node _T_646 = eq(s1_req.cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_648 = eq(s1_req.cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_649 = or(_T_646, _T_648) @[Consts.scala 35:41] + node _T_651 = eq(s1_req.cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_652 = or(_T_649, _T_651) @[Consts.scala 35:58] + node _T_653 = bits(s1_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_655 = eq(s1_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_656 = or(_T_653, _T_655) @[Consts.scala 33:33] + node s1_read = or(_T_652, _T_656) @[Consts.scala 35:75] + node _T_658 = eq(s1_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_660 = eq(s1_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_661 = or(_T_658, _T_660) @[Consts.scala 36:42] + node _T_662 = bits(s1_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_664 = eq(s1_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_665 = or(_T_662, _T_664) @[Consts.scala 33:33] + node s1_write = or(_T_661, _T_665) @[Consts.scala 36:59] + node s1_readwrite = or(s1_read, s1_write) @[DCache.scala 75:30] + reg s1_flush_valid : UInt<1>, clock @[DCache.scala 76:27] + reg cached_grant_wait : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 79:30] + reg release_ack_wait : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 80:29] + reg release_state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DCache.scala 81:26] + wire pstore1_valid : UInt<1> @[DCache.scala 82:27] + pstore1_valid is invalid @[DCache.scala 82:27] + reg pstore2_valid : UInt<1>, clock @[DCache.scala 83:26] + node _T_672 = eq(release_state, UInt<3>("h01")) @[Package.scala 7:47] + node _T_673 = eq(release_state, UInt<3>("h02")) @[Package.scala 7:47] + node inWriteback = or(_T_672, _T_673) @[Package.scala 7:62] + wire releaseWay : UInt @[DCache.scala 85:24] + releaseWay is invalid @[DCache.scala 85:24] + node _T_675 = eq(release_state, UInt<3>("h00")) @[DCache.scala 86:38] + node _T_677 = eq(cached_grant_wait, UInt<1>("h00")) @[DCache.scala 86:54] + node _T_678 = and(_T_675, _T_677) @[DCache.scala 86:51] + node _T_680 = eq(s1_nack, UInt<1>("h00")) @[DCache.scala 86:76] + node _T_681 = and(_T_678, _T_680) @[DCache.scala 86:73] + io.cpu.req.ready <= _T_681 @[DCache.scala 86:20] + wire _T_685 : UInt<1>[1] @[DCache.scala 89:64] + _T_685 is invalid @[DCache.scala 89:64] + _T_685[0] <= UInt<1>("h00") @[DCache.scala 89:64] + reg uncachedInFlight : UInt<1>[1], clock with : (reset => (reset, _T_685)) @[DCache.scala 89:29] + reg uncachedReqs : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}[1], clock @[DCache.scala 90:25] + node _T_743 = eq(io.cpu.req.bits.cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_745 = eq(io.cpu.req.bits.cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_746 = or(_T_743, _T_745) @[Consts.scala 35:41] + node _T_748 = eq(io.cpu.req.bits.cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_749 = or(_T_746, _T_748) @[Consts.scala 35:58] + node _T_750 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] + node _T_752 = eq(io.cpu.req.bits.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_753 = or(_T_750, _T_752) @[Consts.scala 33:33] + node _T_754 = or(_T_749, _T_753) @[Consts.scala 35:75] + node _T_755 = and(io.cpu.req.valid, _T_754) @[DCache.scala 93:46] + dataArb.io.in[3].valid <= _T_755 @[DCache.scala 93:26] + dataArb.io.in[3].bits.write <= UInt<1>("h00") @[DCache.scala 94:31] + dataArb.io.in[3].bits.addr <= io.cpu.req.bits.addr @[DCache.scala 95:30] + node _T_758 = not(UInt<4>("h00")) @[DCache.scala 96:35] + dataArb.io.in[3].bits.way_en <= _T_758 @[DCache.scala 96:32] + node _T_760 = eq(dataArb.io.in[3].ready, UInt<1>("h00")) @[DCache.scala 97:9] + node _T_762 = eq(io.cpu.req.bits.cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_764 = eq(io.cpu.req.bits.cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_765 = or(_T_762, _T_764) @[Consts.scala 35:41] + node _T_767 = eq(io.cpu.req.bits.cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_768 = or(_T_765, _T_767) @[Consts.scala 35:58] + node _T_769 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] + node _T_771 = eq(io.cpu.req.bits.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_772 = or(_T_769, _T_771) @[Consts.scala 33:33] + node _T_773 = or(_T_768, _T_772) @[Consts.scala 35:75] + node _T_774 = and(_T_760, _T_773) @[DCache.scala 97:33] + when _T_774 : @[DCache.scala 97:65] + io.cpu.req.ready <= UInt<1>("h00") @[DCache.scala 97:84] + skip @[DCache.scala 97:65] + metaReadArb.io.in[2].valid <= io.cpu.req.valid @[DCache.scala 98:30] + node _T_776 = bits(io.cpu.req.bits.addr, 11, 6) @[DCache.scala 99:56] + metaReadArb.io.in[2].bits.idx <= _T_776 @[DCache.scala 99:33] + node _T_778 = not(UInt<4>("h00")) @[DCache.scala 100:39] + metaReadArb.io.in[2].bits.way_en <= _T_778 @[DCache.scala 100:36] + node _T_780 = eq(metaReadArb.io.in[2].ready, UInt<1>("h00")) @[DCache.scala 101:9] + when _T_780 : @[DCache.scala 101:38] + io.cpu.req.ready <= UInt<1>("h00") @[DCache.scala 101:57] + skip @[DCache.scala 101:38] + inst tlb of TLB @[DCache.scala 104:19] + tlb.io is invalid + tlb.clock <= clock + tlb.reset <= reset + io.ptw <- tlb.io.ptw @[DCache.scala 105:10] + node _T_782 = and(s1_valid_masked, s1_readwrite) @[DCache.scala 106:39] + tlb.io.req.valid <= _T_782 @[DCache.scala 106:20] + tlb.io.req.bits.passthrough <= s1_req.phys @[DCache.scala 107:31] + tlb.io.req.bits.vaddr <= s1_req.addr @[DCache.scala 108:25] + tlb.io.req.bits.instruction <= UInt<1>("h00") @[DCache.scala 109:31] + tlb.io.req.bits.store <= s1_write @[DCache.scala 110:25] + node _T_785 = eq(tlb.io.req.ready, UInt<1>("h00")) @[DCache.scala 111:9] + node _T_787 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) @[DCache.scala 111:30] + node _T_788 = and(_T_785, _T_787) @[DCache.scala 111:27] + when _T_788 : @[DCache.scala 111:53] + io.cpu.req.ready <= UInt<1>("h00") @[DCache.scala 111:72] + skip @[DCache.scala 111:53] + node _T_790 = and(s1_valid, s1_readwrite) @[DCache.scala 112:18] + node _T_791 = and(_T_790, tlb.io.resp.miss) @[DCache.scala 112:34] + when _T_791 : @[DCache.scala 112:55] + s1_nack <= UInt<1>("h01") @[DCache.scala 112:65] + skip @[DCache.scala 112:55] + node _T_793 = mux(s1_probe, probe_bits.address, tlb.io.resp.paddr) @[DCache.scala 115:19] + node s1_tag = bits(_T_793, 31, 12) @[DCache.scala 115:59] + node _T_794 = bits(_T_573, 1, 0) @[Replacement.scala 19:44] + wire s1_victim_way : UInt + s1_victim_way is invalid + s1_victim_way <= _T_794 + inst L1MetadataArray of L1MetadataArray @[DCache.scala 125:24] + L1MetadataArray.io is invalid + L1MetadataArray.clock <= clock + L1MetadataArray.reset <= reset + L1MetadataArray.io.read <- metaReadArb.io.out @[DCache.scala 126:20] + L1MetadataArray.io.write <- metaWriteArb.io.out @[DCache.scala 127:21] + node _T_796 = gt(L1MetadataArray.io.resp[0].coh.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_797 = eq(L1MetadataArray.io.resp[0].tag, s1_tag) @[DCache.scala 129:71] + node _T_798 = and(_T_796, _T_797) @[DCache.scala 129:62] + node _T_800 = gt(L1MetadataArray.io.resp[1].coh.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_801 = eq(L1MetadataArray.io.resp[1].tag, s1_tag) @[DCache.scala 129:71] + node _T_802 = and(_T_800, _T_801) @[DCache.scala 129:62] + node _T_804 = gt(L1MetadataArray.io.resp[2].coh.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_805 = eq(L1MetadataArray.io.resp[2].tag, s1_tag) @[DCache.scala 129:71] + node _T_806 = and(_T_804, _T_805) @[DCache.scala 129:62] + node _T_808 = gt(L1MetadataArray.io.resp[3].coh.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_809 = eq(L1MetadataArray.io.resp[3].tag, s1_tag) @[DCache.scala 129:71] + node _T_810 = and(_T_808, _T_809) @[DCache.scala 129:62] + node _T_811 = cat(_T_802, _T_798) @[Cat.scala 30:58] + node _T_812 = cat(_T_810, _T_806) @[Cat.scala 30:58] + node s1_hit_way = cat(_T_812, _T_811) @[Cat.scala 30:58] + wire _T_816 : {state : UInt<2>} @[Metadata.scala 160:20] + _T_816 is invalid @[Metadata.scala 160:20] + _T_816.state <= UInt<2>("h00") @[Metadata.scala 161:16] + node _T_818 = eq(L1MetadataArray.io.resp[0].tag, s1_tag) @[DCache.scala 131:36] + node _T_820 = mux(_T_818, L1MetadataArray.io.resp[0].coh.state, UInt<1>("h00")) @[DCache.scala 131:29] + node _T_821 = eq(L1MetadataArray.io.resp[1].tag, s1_tag) @[DCache.scala 131:36] + node _T_823 = mux(_T_821, L1MetadataArray.io.resp[1].coh.state, UInt<1>("h00")) @[DCache.scala 131:29] + node _T_824 = eq(L1MetadataArray.io.resp[2].tag, s1_tag) @[DCache.scala 131:36] + node _T_826 = mux(_T_824, L1MetadataArray.io.resp[2].coh.state, UInt<1>("h00")) @[DCache.scala 131:29] + node _T_827 = eq(L1MetadataArray.io.resp[3].tag, s1_tag) @[DCache.scala 131:36] + node _T_829 = mux(_T_827, L1MetadataArray.io.resp[3].coh.state, UInt<1>("h00")) @[DCache.scala 131:29] + node _T_830 = or(_T_820, _T_823) @[DCache.scala 132:19] + node _T_831 = or(_T_830, _T_826) @[DCache.scala 132:19] + node _T_832 = or(_T_831, _T_829) @[DCache.scala 132:19] + wire s1_hit_state : {state : UInt<2>} @[DCache.scala 130:62] + s1_hit_state is invalid @[DCache.scala 130:62] + wire _T_837 : UInt<2> + _T_837 is invalid + _T_837 <= _T_832 + node _T_838 = bits(_T_837, 1, 0) @[DCache.scala 130:62] + s1_hit_state.state <= _T_838 @[DCache.scala 130:62] + node _T_847 = or(s1_victim_way, UInt<2>("h00")) + node _T_848 = bits(_T_847, 1, 0) + node s1_data_way = mux(inWriteback, releaseWay, s1_hit_way) @[DCache.scala 135:24] + node _T_849 = bits(s1_data_way, 0, 0) @[Mux.scala 21:36] + node _T_850 = bits(s1_data_way, 1, 1) @[Mux.scala 21:36] + node _T_851 = bits(s1_data_way, 2, 2) @[Mux.scala 21:36] + node _T_852 = bits(s1_data_way, 3, 3) @[Mux.scala 21:36] + node _T_854 = mux(_T_849, data.io.resp[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_856 = mux(_T_850, data.io.resp[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_858 = mux(_T_851, data.io.resp[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_860 = mux(_T_852, data.io.resp[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_862 = or(_T_854, _T_856) @[Mux.scala 19:72] + node _T_863 = or(_T_862, _T_858) @[Mux.scala 19:72] + node _T_864 = or(_T_863, _T_860) @[Mux.scala 19:72] + wire s1_data : UInt<64> @[Mux.scala 19:72] + s1_data is invalid @[Mux.scala 19:72] + s1_data <= _T_864 @[Mux.scala 19:72] + reg s2_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 138:21] + s2_valid <= s1_valid_masked @[DCache.scala 138:21] + reg s2_probe : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 139:21] + s2_probe <= s1_probe @[DCache.scala 139:21] + node _T_868 = or(s1_probe, s2_probe) @[DCache.scala 140:34] + node _T_869 = neq(release_state, UInt<3>("h00")) @[DCache.scala 140:63] + node releaseInFlight = or(_T_868, _T_869) @[DCache.scala 140:46] + node _T_871 = eq(s1_nack, UInt<1>("h00")) @[DCache.scala 141:48] + reg _T_872 : UInt<1>, clock @[DCache.scala 141:40] + _T_872 <= _T_871 @[DCache.scala 141:40] + node s2_valid_masked = and(s2_valid, _T_872) @[DCache.scala 141:34] + reg s2_req : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clock @[DCache.scala 142:19] + node _T_878 = shr(s2_req.addr, 6) @[DCache.scala 143:40] + node acquire_address = shl(_T_878, 6) @[DCache.scala 143:51] + reg s2_uncached : UInt<1>, clock @[DCache.scala 144:24] + node _T_880 = or(s1_valid_not_nacked, s1_flush_valid) @[DCache.scala 145:29] + when _T_880 : @[DCache.scala 145:48] + s2_req <- s1_req @[DCache.scala 146:12] + s2_req.addr <= tlb.io.resp.paddr @[DCache.scala 147:17] + node _T_882 = eq(tlb.io.resp.cacheable, UInt<1>("h00")) @[DCache.scala 148:20] + node _T_884 = or(_T_882, UInt<1>("h00")) @[DCache.scala 148:43] + s2_uncached <= _T_884 @[DCache.scala 148:17] + skip @[DCache.scala 145:48] + node _T_886 = eq(s2_req.cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_888 = eq(s2_req.cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_889 = or(_T_886, _T_888) @[Consts.scala 35:41] + node _T_891 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_892 = or(_T_889, _T_891) @[Consts.scala 35:58] + node _T_893 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_895 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_896 = or(_T_893, _T_895) @[Consts.scala 33:33] + node s2_read = or(_T_892, _T_896) @[Consts.scala 35:75] + node _T_898 = eq(s2_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_900 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_901 = or(_T_898, _T_900) @[Consts.scala 36:42] + node _T_902 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_904 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_905 = or(_T_902, _T_904) @[Consts.scala 33:33] + node s2_write = or(_T_901, _T_905) @[Consts.scala 36:59] + node s2_readwrite = or(s2_read, s2_write) @[DCache.scala 152:30] + reg s2_flush_valid : UInt<1>, clock @[Reg.scala 14:44] + s2_flush_valid <= s1_flush_valid @[Reg.scala 14:44] + node _T_906 = or(s1_valid, inWriteback) @[DCache.scala 154:45] + reg s2_data : UInt<64>, clock @[Reg.scala 34:16] + when _T_906 : @[Reg.scala 35:19] + s2_data <= s1_data @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg s2_probe_way : UInt<4>, clock @[Reg.scala 34:16] + when s1_probe : @[Reg.scala 35:19] + s2_probe_way <= s1_hit_way @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg s2_probe_state : {state : UInt<2>}, clock @[Reg.scala 34:16] + when s1_probe : @[Reg.scala 35:19] + s2_probe_state <- s1_hit_state @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg s2_hit_way : UInt<4>, clock @[Reg.scala 34:16] + when s1_valid_not_nacked : @[Reg.scala 35:19] + s2_hit_way <= s1_hit_way @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg s2_hit_state : {state : UInt<2>}, clock @[Reg.scala 34:16] + when s1_valid_not_nacked : @[Reg.scala 35:19] + s2_hit_state <- s1_hit_state @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node s2_hit_valid = gt(s2_hit_state.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_918 = eq(s2_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_920 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_921 = or(_T_918, _T_920) @[Consts.scala 36:42] + node _T_922 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_924 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_925 = or(_T_922, _T_924) @[Consts.scala 33:33] + node _T_926 = or(_T_921, _T_925) @[Consts.scala 36:59] + node _T_928 = eq(s2_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_930 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_931 = or(_T_928, _T_930) @[Consts.scala 36:42] + node _T_932 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_934 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_935 = or(_T_932, _T_934) @[Consts.scala 33:33] + node _T_936 = or(_T_931, _T_935) @[Consts.scala 36:59] + node _T_938 = eq(s2_req.cmd, UInt<2>("h03")) @[Consts.scala 37:54] + node _T_939 = or(_T_936, _T_938) @[Consts.scala 37:47] + node _T_941 = eq(s2_req.cmd, UInt<3>("h06")) @[Consts.scala 37:71] + node _T_942 = or(_T_939, _T_941) @[Consts.scala 37:64] + node _T_943 = cat(_T_926, _T_942) @[Cat.scala 30:58] + node _T_944 = cat(_T_943, s2_hit_state.state) @[Cat.scala 30:58] + node _T_949 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_951 = cat(_T_949, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_956 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_958 = cat(_T_956, UInt<2>("h02")) @[Cat.scala 30:58] + node _T_963 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_965 = cat(_T_963, UInt<2>("h01")) @[Cat.scala 30:58] + node _T_970 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_972 = cat(_T_970, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_977 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_979 = cat(_T_977, UInt<2>("h02")) @[Cat.scala 30:58] + node _T_984 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_986 = cat(_T_984, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_991 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_993 = cat(_T_991, UInt<2>("h02")) @[Cat.scala 30:58] + node _T_998 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1000 = cat(_T_998, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1005 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_1007 = cat(_T_1005, UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1012 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_1014 = cat(_T_1012, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1019 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_1021 = cat(_T_1019, UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1026 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_1028 = cat(_T_1026, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1031 = eq(_T_1028, _T_944) @[Misc.scala 50:20] + node _T_1032 = mux(_T_1031, UInt<1>("h00"), UInt<1>("h00")) @[Misc.scala 36:9] + node _T_1033 = mux(_T_1031, UInt<2>("h01"), UInt<1>("h00")) @[Misc.scala 36:36] + node _T_1034 = eq(_T_1021, _T_944) @[Misc.scala 50:20] + node _T_1035 = mux(_T_1034, UInt<1>("h00"), _T_1032) @[Misc.scala 36:9] + node _T_1036 = mux(_T_1034, UInt<2>("h02"), _T_1033) @[Misc.scala 36:36] + node _T_1037 = eq(_T_1014, _T_944) @[Misc.scala 50:20] + node _T_1038 = mux(_T_1037, UInt<1>("h00"), _T_1035) @[Misc.scala 36:9] + node _T_1039 = mux(_T_1037, UInt<2>("h01"), _T_1036) @[Misc.scala 36:36] + node _T_1040 = eq(_T_1007, _T_944) @[Misc.scala 50:20] + node _T_1041 = mux(_T_1040, UInt<1>("h00"), _T_1038) @[Misc.scala 36:9] + node _T_1042 = mux(_T_1040, UInt<2>("h02"), _T_1039) @[Misc.scala 36:36] + node _T_1043 = eq(_T_1000, _T_944) @[Misc.scala 50:20] + node _T_1044 = mux(_T_1043, UInt<1>("h00"), _T_1041) @[Misc.scala 36:9] + node _T_1045 = mux(_T_1043, UInt<2>("h00"), _T_1042) @[Misc.scala 36:36] + node _T_1046 = eq(_T_993, _T_944) @[Misc.scala 50:20] + node _T_1047 = mux(_T_1046, UInt<1>("h01"), _T_1044) @[Misc.scala 36:9] + node _T_1048 = mux(_T_1046, UInt<2>("h03"), _T_1045) @[Misc.scala 36:36] + node _T_1049 = eq(_T_986, _T_944) @[Misc.scala 50:20] + node _T_1050 = mux(_T_1049, UInt<1>("h01"), _T_1047) @[Misc.scala 36:9] + node _T_1051 = mux(_T_1049, UInt<2>("h03"), _T_1048) @[Misc.scala 36:36] + node _T_1052 = eq(_T_979, _T_944) @[Misc.scala 50:20] + node _T_1053 = mux(_T_1052, UInt<1>("h01"), _T_1050) @[Misc.scala 36:9] + node _T_1054 = mux(_T_1052, UInt<2>("h02"), _T_1051) @[Misc.scala 36:36] + node _T_1055 = eq(_T_972, _T_944) @[Misc.scala 50:20] + node _T_1056 = mux(_T_1055, UInt<1>("h01"), _T_1053) @[Misc.scala 36:9] + node _T_1057 = mux(_T_1055, UInt<2>("h03"), _T_1054) @[Misc.scala 36:36] + node _T_1058 = eq(_T_965, _T_944) @[Misc.scala 50:20] + node _T_1059 = mux(_T_1058, UInt<1>("h01"), _T_1056) @[Misc.scala 36:9] + node _T_1060 = mux(_T_1058, UInt<2>("h01"), _T_1057) @[Misc.scala 36:36] + node _T_1061 = eq(_T_958, _T_944) @[Misc.scala 50:20] + node _T_1062 = mux(_T_1061, UInt<1>("h01"), _T_1059) @[Misc.scala 36:9] + node _T_1063 = mux(_T_1061, UInt<2>("h02"), _T_1060) @[Misc.scala 36:36] + node _T_1064 = eq(_T_951, _T_944) @[Misc.scala 50:20] + node s2_hit = mux(_T_1064, UInt<1>("h01"), _T_1062) @[Misc.scala 36:9] + node s2_grow_param = mux(_T_1064, UInt<2>("h03"), _T_1063) @[Misc.scala 36:36] + wire s2_new_hit_state : {state : UInt<2>} @[Metadata.scala 160:20] + s2_new_hit_state is invalid @[Metadata.scala 160:20] + s2_new_hit_state.state <= s2_grow_param @[Metadata.scala 161:16] + node _T_1068 = and(s2_valid_masked, s2_readwrite) @[DCache.scala 161:38] + node s2_valid_hit = and(_T_1068, s2_hit) @[DCache.scala 161:54] + node _T_1069 = and(s2_valid_masked, s2_readwrite) @[DCache.scala 162:39] + node _T_1071 = eq(s2_hit, UInt<1>("h00")) @[DCache.scala 162:58] + node _T_1072 = and(_T_1069, _T_1071) @[DCache.scala 162:55] + node _T_1073 = or(pstore1_valid, pstore2_valid) @[DCache.scala 162:85] + node _T_1075 = eq(_T_1073, UInt<1>("h00")) @[DCache.scala 162:69] + node _T_1076 = and(_T_1072, _T_1075) @[DCache.scala 162:66] + node _T_1078 = eq(release_ack_wait, UInt<1>("h00")) @[DCache.scala 162:106] + node s2_valid_miss = and(_T_1076, _T_1078) @[DCache.scala 162:103] + node _T_1080 = eq(s2_uncached, UInt<1>("h00")) @[DCache.scala 163:47] + node s2_valid_cached_miss = and(s2_valid_miss, _T_1080) @[DCache.scala 163:44] + node s2_victimize = or(s2_valid_cached_miss, s2_flush_valid) @[DCache.scala 164:43] + node s2_valid_uncached = and(s2_valid_miss, s2_uncached) @[DCache.scala 165:41] + node _T_1082 = eq(s2_flush_valid, UInt<1>("h00")) @[DCache.scala 166:43] + node _T_1083 = and(s2_hit_valid, _T_1082) @[DCache.scala 166:40] + node _T_1084 = or(s1_valid_not_nacked, s1_flush_valid) @[DCache.scala 166:126] + reg _T_1086 : UInt, clock @[Reg.scala 34:16] + when _T_1084 : @[Reg.scala 35:19] + _T_1086 <= s1_victim_way @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1088 = dshl(UInt<1>("h01"), _T_1086) @[OneHot.scala 47:11] + node s2_victim_way = mux(_T_1083, s2_hit_way, _T_1088) @[DCache.scala 166:26] + node _T_1089 = or(s1_valid_not_nacked, s1_flush_valid) @[DCache.scala 167:73] + reg s2_victim_tag : UInt<20>, clock @[Reg.scala 34:16] + when _T_1089 : @[Reg.scala 35:19] + s2_victim_tag <= L1MetadataArray.io.resp[_T_848].tag @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1092 = eq(s2_flush_valid, UInt<1>("h00")) @[DCache.scala 168:45] + node _T_1093 = and(s2_hit_valid, _T_1092) @[DCache.scala 168:42] + node _T_1094 = or(s1_valid_not_nacked, s1_flush_valid) @[DCache.scala 168:126] + reg _T_1097 : {state : UInt<2>}, clock @[Reg.scala 34:16] + when _T_1094 : @[Reg.scala 35:19] + _T_1097 <- L1MetadataArray.io.resp[_T_848].coh @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node s2_victim_state = mux(_T_1093, s2_hit_state, _T_1097) @[DCache.scala 168:28] + node s2_victim_valid = gt(s2_victim_state.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_1101 = cat(probe_bits.param, s2_probe_state.state) @[Cat.scala 30:58] + node _T_1107 = cat(UInt<2>("h00"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1113 = cat(UInt<2>("h00"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1119 = cat(UInt<2>("h00"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1125 = cat(UInt<2>("h00"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1131 = cat(UInt<2>("h01"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1137 = cat(UInt<2>("h01"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1143 = cat(UInt<2>("h01"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1149 = cat(UInt<2>("h01"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1155 = cat(UInt<2>("h02"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1161 = cat(UInt<2>("h02"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1167 = cat(UInt<2>("h02"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1173 = cat(UInt<2>("h02"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1177 = eq(_T_1173, _T_1101) @[Misc.scala 57:20] + node _T_1178 = mux(_T_1177, UInt<1>("h00"), UInt<1>("h00")) @[Misc.scala 39:9] + node _T_1179 = mux(_T_1177, UInt<3>("h05"), UInt<1>("h00")) @[Misc.scala 39:36] + node _T_1180 = mux(_T_1177, UInt<2>("h00"), UInt<1>("h00")) @[Misc.scala 39:63] + node _T_1181 = eq(_T_1167, _T_1101) @[Misc.scala 57:20] + node _T_1182 = mux(_T_1181, UInt<1>("h00"), _T_1178) @[Misc.scala 39:9] + node _T_1183 = mux(_T_1181, UInt<3>("h02"), _T_1179) @[Misc.scala 39:36] + node _T_1184 = mux(_T_1181, UInt<2>("h00"), _T_1180) @[Misc.scala 39:63] + node _T_1185 = eq(_T_1161, _T_1101) @[Misc.scala 57:20] + node _T_1186 = mux(_T_1185, UInt<1>("h00"), _T_1182) @[Misc.scala 39:9] + node _T_1187 = mux(_T_1185, UInt<3>("h01"), _T_1183) @[Misc.scala 39:36] + node _T_1188 = mux(_T_1185, UInt<2>("h00"), _T_1184) @[Misc.scala 39:63] + node _T_1189 = eq(_T_1155, _T_1101) @[Misc.scala 57:20] + node _T_1190 = mux(_T_1189, UInt<1>("h01"), _T_1186) @[Misc.scala 39:9] + node _T_1191 = mux(_T_1189, UInt<3>("h01"), _T_1187) @[Misc.scala 39:36] + node _T_1192 = mux(_T_1189, UInt<2>("h00"), _T_1188) @[Misc.scala 39:63] + node _T_1193 = eq(_T_1149, _T_1101) @[Misc.scala 57:20] + node _T_1194 = mux(_T_1193, UInt<1>("h00"), _T_1190) @[Misc.scala 39:9] + node _T_1195 = mux(_T_1193, UInt<3>("h02"), _T_1191) @[Misc.scala 39:36] + node _T_1196 = mux(_T_1193, UInt<2>("h00"), _T_1192) @[Misc.scala 39:63] + node _T_1197 = eq(_T_1143, _T_1101) @[Misc.scala 57:20] + node _T_1198 = mux(_T_1197, UInt<1>("h00"), _T_1194) @[Misc.scala 39:9] + node _T_1199 = mux(_T_1197, UInt<3>("h04"), _T_1195) @[Misc.scala 39:36] + node _T_1200 = mux(_T_1197, UInt<2>("h01"), _T_1196) @[Misc.scala 39:63] + node _T_1201 = eq(_T_1137, _T_1101) @[Misc.scala 57:20] + node _T_1202 = mux(_T_1201, UInt<1>("h00"), _T_1198) @[Misc.scala 39:9] + node _T_1203 = mux(_T_1201, UInt<3>("h00"), _T_1199) @[Misc.scala 39:36] + node _T_1204 = mux(_T_1201, UInt<2>("h01"), _T_1200) @[Misc.scala 39:63] + node _T_1205 = eq(_T_1131, _T_1101) @[Misc.scala 57:20] + node _T_1206 = mux(_T_1205, UInt<1>("h01"), _T_1202) @[Misc.scala 39:9] + node _T_1207 = mux(_T_1205, UInt<3>("h00"), _T_1203) @[Misc.scala 39:36] + node _T_1208 = mux(_T_1205, UInt<2>("h01"), _T_1204) @[Misc.scala 39:63] + node _T_1209 = eq(_T_1125, _T_1101) @[Misc.scala 57:20] + node _T_1210 = mux(_T_1209, UInt<1>("h00"), _T_1206) @[Misc.scala 39:9] + node _T_1211 = mux(_T_1209, UInt<3>("h05"), _T_1207) @[Misc.scala 39:36] + node _T_1212 = mux(_T_1209, UInt<2>("h00"), _T_1208) @[Misc.scala 39:63] + node _T_1213 = eq(_T_1119, _T_1101) @[Misc.scala 57:20] + node _T_1214 = mux(_T_1213, UInt<1>("h00"), _T_1210) @[Misc.scala 39:9] + node _T_1215 = mux(_T_1213, UInt<3>("h04"), _T_1211) @[Misc.scala 39:36] + node _T_1216 = mux(_T_1213, UInt<2>("h01"), _T_1212) @[Misc.scala 39:63] + node _T_1217 = eq(_T_1113, _T_1101) @[Misc.scala 57:20] + node _T_1218 = mux(_T_1217, UInt<1>("h00"), _T_1214) @[Misc.scala 39:9] + node _T_1219 = mux(_T_1217, UInt<3>("h03"), _T_1215) @[Misc.scala 39:36] + node _T_1220 = mux(_T_1217, UInt<2>("h02"), _T_1216) @[Misc.scala 39:63] + node _T_1221 = eq(_T_1107, _T_1101) @[Misc.scala 57:20] + node s2_prb_ack_data = mux(_T_1221, UInt<1>("h01"), _T_1218) @[Misc.scala 39:9] + node s2_report_param = mux(_T_1221, UInt<3>("h03"), _T_1219) @[Misc.scala 39:36] + node _T_1222 = mux(_T_1221, UInt<2>("h02"), _T_1220) @[Misc.scala 39:63] + wire probeNewCoh : {state : UInt<2>} @[Metadata.scala 160:20] + probeNewCoh is invalid @[Metadata.scala 160:20] + probeNewCoh.state <= _T_1222 @[Metadata.scala 161:16] + node _T_1234 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] + node _T_1235 = mux(_T_1234, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] + node _T_1236 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] + node _T_1237 = mux(_T_1236, UInt<2>("h01"), _T_1235) @[Mux.scala 46:16] + node _T_1238 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] + node _T_1239 = mux(_T_1238, UInt<2>("h02"), _T_1237) @[Mux.scala 46:16] + node _T_1240 = cat(_T_1239, s2_victim_state.state) @[Cat.scala 30:58] + node _T_1246 = cat(UInt<2>("h00"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1252 = cat(UInt<2>("h00"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1258 = cat(UInt<2>("h00"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1264 = cat(UInt<2>("h00"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1270 = cat(UInt<2>("h01"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1276 = cat(UInt<2>("h01"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1282 = cat(UInt<2>("h01"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1288 = cat(UInt<2>("h01"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1294 = cat(UInt<2>("h02"), UInt<2>("h03")) @[Cat.scala 30:58] + node _T_1300 = cat(UInt<2>("h02"), UInt<2>("h02")) @[Cat.scala 30:58] + node _T_1306 = cat(UInt<2>("h02"), UInt<2>("h01")) @[Cat.scala 30:58] + node _T_1312 = cat(UInt<2>("h02"), UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1316 = eq(_T_1312, _T_1240) @[Misc.scala 57:20] + node _T_1317 = mux(_T_1316, UInt<1>("h00"), UInt<1>("h00")) @[Misc.scala 39:9] + node _T_1318 = mux(_T_1316, UInt<3>("h05"), UInt<1>("h00")) @[Misc.scala 39:36] + node _T_1319 = mux(_T_1316, UInt<2>("h00"), UInt<1>("h00")) @[Misc.scala 39:63] + node _T_1320 = eq(_T_1306, _T_1240) @[Misc.scala 57:20] + node _T_1321 = mux(_T_1320, UInt<1>("h00"), _T_1317) @[Misc.scala 39:9] + node _T_1322 = mux(_T_1320, UInt<3>("h02"), _T_1318) @[Misc.scala 39:36] + node _T_1323 = mux(_T_1320, UInt<2>("h00"), _T_1319) @[Misc.scala 39:63] + node _T_1324 = eq(_T_1300, _T_1240) @[Misc.scala 57:20] + node _T_1325 = mux(_T_1324, UInt<1>("h00"), _T_1321) @[Misc.scala 39:9] + node _T_1326 = mux(_T_1324, UInt<3>("h01"), _T_1322) @[Misc.scala 39:36] + node _T_1327 = mux(_T_1324, UInt<2>("h00"), _T_1323) @[Misc.scala 39:63] + node _T_1328 = eq(_T_1294, _T_1240) @[Misc.scala 57:20] + node _T_1329 = mux(_T_1328, UInt<1>("h01"), _T_1325) @[Misc.scala 39:9] + node _T_1330 = mux(_T_1328, UInt<3>("h01"), _T_1326) @[Misc.scala 39:36] + node _T_1331 = mux(_T_1328, UInt<2>("h00"), _T_1327) @[Misc.scala 39:63] + node _T_1332 = eq(_T_1288, _T_1240) @[Misc.scala 57:20] + node _T_1333 = mux(_T_1332, UInt<1>("h00"), _T_1329) @[Misc.scala 39:9] + node _T_1334 = mux(_T_1332, UInt<3>("h02"), _T_1330) @[Misc.scala 39:36] + node _T_1335 = mux(_T_1332, UInt<2>("h00"), _T_1331) @[Misc.scala 39:63] + node _T_1336 = eq(_T_1282, _T_1240) @[Misc.scala 57:20] + node _T_1337 = mux(_T_1336, UInt<1>("h00"), _T_1333) @[Misc.scala 39:9] + node _T_1338 = mux(_T_1336, UInt<3>("h04"), _T_1334) @[Misc.scala 39:36] + node _T_1339 = mux(_T_1336, UInt<2>("h01"), _T_1335) @[Misc.scala 39:63] + node _T_1340 = eq(_T_1276, _T_1240) @[Misc.scala 57:20] + node _T_1341 = mux(_T_1340, UInt<1>("h00"), _T_1337) @[Misc.scala 39:9] + node _T_1342 = mux(_T_1340, UInt<3>("h00"), _T_1338) @[Misc.scala 39:36] + node _T_1343 = mux(_T_1340, UInt<2>("h01"), _T_1339) @[Misc.scala 39:63] + node _T_1344 = eq(_T_1270, _T_1240) @[Misc.scala 57:20] + node _T_1345 = mux(_T_1344, UInt<1>("h01"), _T_1341) @[Misc.scala 39:9] + node _T_1346 = mux(_T_1344, UInt<3>("h00"), _T_1342) @[Misc.scala 39:36] + node _T_1347 = mux(_T_1344, UInt<2>("h01"), _T_1343) @[Misc.scala 39:63] + node _T_1348 = eq(_T_1264, _T_1240) @[Misc.scala 57:20] + node _T_1349 = mux(_T_1348, UInt<1>("h00"), _T_1345) @[Misc.scala 39:9] + node _T_1350 = mux(_T_1348, UInt<3>("h05"), _T_1346) @[Misc.scala 39:36] + node _T_1351 = mux(_T_1348, UInt<2>("h00"), _T_1347) @[Misc.scala 39:63] + node _T_1352 = eq(_T_1258, _T_1240) @[Misc.scala 57:20] + node _T_1353 = mux(_T_1352, UInt<1>("h00"), _T_1349) @[Misc.scala 39:9] + node _T_1354 = mux(_T_1352, UInt<3>("h04"), _T_1350) @[Misc.scala 39:36] + node _T_1355 = mux(_T_1352, UInt<2>("h01"), _T_1351) @[Misc.scala 39:63] + node _T_1356 = eq(_T_1252, _T_1240) @[Misc.scala 57:20] + node _T_1357 = mux(_T_1356, UInt<1>("h00"), _T_1353) @[Misc.scala 39:9] + node _T_1358 = mux(_T_1356, UInt<3>("h03"), _T_1354) @[Misc.scala 39:36] + node _T_1359 = mux(_T_1356, UInt<2>("h02"), _T_1355) @[Misc.scala 39:63] + node _T_1360 = eq(_T_1246, _T_1240) @[Misc.scala 57:20] + node s2_victim_dirty = mux(_T_1360, UInt<1>("h01"), _T_1357) @[Misc.scala 39:9] + node s2_shrink_param = mux(_T_1360, UInt<3>("h03"), _T_1358) @[Misc.scala 39:36] + node _T_1361 = mux(_T_1360, UInt<2>("h02"), _T_1359) @[Misc.scala 39:63] + wire voluntaryNewCoh : {state : UInt<2>} @[Metadata.scala 160:20] + voluntaryNewCoh is invalid @[Metadata.scala 160:20] + voluntaryNewCoh.state <= _T_1361 @[Metadata.scala 161:16] + node _T_1365 = eq(s2_hit_state.state, s2_new_hit_state.state) @[Metadata.scala 46:46] + node s2_update_meta = eq(_T_1365, UInt<1>("h00")) @[Metadata.scala 47:40] + node _T_1368 = eq(s2_valid_hit, UInt<1>("h00")) @[DCache.scala 173:33] + node _T_1369 = and(s2_valid, _T_1368) @[DCache.scala 173:30] + node _T_1370 = and(s2_valid_uncached, io.mem.0.a.ready) @[DCache.scala 173:70] + node _T_1371 = not(uncachedInFlight[0]) @[DCache.scala 173:116] + node _T_1373 = eq(_T_1371, UInt<1>("h00")) @[DCache.scala 173:116] + node _T_1375 = eq(_T_1373, UInt<1>("h00")) @[DCache.scala 173:91] + node _T_1376 = and(_T_1370, _T_1375) @[DCache.scala 173:88] + node _T_1378 = eq(_T_1376, UInt<1>("h00")) @[DCache.scala 173:50] + node _T_1379 = and(_T_1369, _T_1378) @[DCache.scala 173:47] + io.cpu.s2_nack <= _T_1379 @[DCache.scala 173:18] + node _T_1381 = eq(s2_valid_hit, UInt<1>("h00")) @[DCache.scala 174:22] + node _T_1382 = or(_T_1381, s2_update_meta) @[DCache.scala 174:36] + node _T_1383 = and(s2_valid, _T_1382) @[DCache.scala 174:18] + when _T_1383 : @[DCache.scala 174:56] + s1_nack <= UInt<1>("h01") @[DCache.scala 174:66] + skip @[DCache.scala 174:56] + node _T_1386 = bits(s1_req.typ, 1, 0) @[AmoAlu.scala 12:17] + node _T_1388 = dshl(UInt<1>("h01"), _T_1386) @[AmoAlu.scala 14:23] + node _T_1390 = sub(_T_1388, UInt<1>("h01")) @[AmoAlu.scala 14:32] + node _T_1391 = asUInt(_T_1390) @[AmoAlu.scala 14:32] + node _T_1392 = tail(_T_1391, 1) @[AmoAlu.scala 14:32] + node _T_1393 = bits(_T_1392, 2, 0) @[AmoAlu.scala 14:42] + node _T_1394 = and(s1_req.addr, _T_1393) @[AmoAlu.scala 14:11] + node _T_1396 = neq(_T_1394, UInt<1>("h00")) @[AmoAlu.scala 14:65] + node _T_1397 = and(s1_read, _T_1396) @[DCache.scala 178:32] + io.cpu.xcpt.ma.ld <= _T_1397 @[DCache.scala 178:21] + node _T_1399 = dshl(UInt<1>("h01"), _T_1386) @[AmoAlu.scala 14:23] + node _T_1401 = sub(_T_1399, UInt<1>("h01")) @[AmoAlu.scala 14:32] + node _T_1402 = asUInt(_T_1401) @[AmoAlu.scala 14:32] + node _T_1403 = tail(_T_1402, 1) @[AmoAlu.scala 14:32] + node _T_1404 = bits(_T_1403, 2, 0) @[AmoAlu.scala 14:42] + node _T_1405 = and(s1_req.addr, _T_1404) @[AmoAlu.scala 14:11] + node _T_1407 = neq(_T_1405, UInt<1>("h00")) @[AmoAlu.scala 14:65] + node _T_1408 = and(s1_write, _T_1407) @[DCache.scala 179:33] + io.cpu.xcpt.ma.st <= _T_1408 @[DCache.scala 179:21] + node _T_1409 = and(s1_read, tlb.io.resp.xcpt_ld) @[DCache.scala 180:32] + io.cpu.xcpt.pf.ld <= _T_1409 @[DCache.scala 180:21] + node _T_1410 = and(s1_write, tlb.io.resp.xcpt_st) @[DCache.scala 181:33] + io.cpu.xcpt.pf.st <= _T_1410 @[DCache.scala 181:21] + node _T_1413 = eq(s2_req.cmd, UInt<3>("h06")) @[DCache.scala 184:48] + node s2_lr = and(UInt<1>("h01"), _T_1413) @[DCache.scala 184:34] + node _T_1416 = eq(s2_req.cmd, UInt<3>("h07")) @[DCache.scala 185:48] + node s2_sc = and(UInt<1>("h01"), _T_1416) @[DCache.scala 185:34] + reg lrscCount : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 186:22] + node lrscValid = gt(lrscCount, UInt<1>("h00")) @[DCache.scala 187:29] + reg lrscAddr : UInt, clock @[DCache.scala 188:21] + node _T_1420 = shr(s2_req.addr, 6) @[DCache.scala 189:70] + node _T_1421 = eq(lrscAddr, _T_1420) @[DCache.scala 189:53] + node _T_1422 = and(lrscValid, _T_1421) @[DCache.scala 189:41] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[DCache.scala 189:29] + node s2_sc_fail = and(s2_sc, _T_1424) @[DCache.scala 189:26] + node _T_1425 = and(s2_valid_hit, s2_lr) @[DCache.scala 190:22] + when _T_1425 : @[DCache.scala 190:32] + lrscCount <= UInt<5>("h01f") @[DCache.scala 191:15] + node _T_1427 = shr(s2_req.addr, 6) @[DCache.scala 192:29] + lrscAddr <= _T_1427 @[DCache.scala 192:14] + skip @[DCache.scala 190:32] + when lrscValid : @[DCache.scala 194:20] + node _T_1429 = sub(lrscCount, UInt<1>("h01")) @[DCache.scala 194:45] + node _T_1430 = asUInt(_T_1429) @[DCache.scala 194:45] + node _T_1431 = tail(_T_1430, 1) @[DCache.scala 194:45] + lrscCount <= _T_1431 @[DCache.scala 194:32] + skip @[DCache.scala 194:20] + node _T_1432 = and(s2_valid_masked, lrscValid) @[DCache.scala 195:26] + node _T_1433 = or(_T_1432, io.cpu.invalidate_lr) @[DCache.scala 195:40] + when _T_1433 : @[DCache.scala 195:65] + lrscCount <= UInt<1>("h00") @[DCache.scala 195:77] + skip @[DCache.scala 195:65] + node _T_1435 = and(s1_valid_not_nacked, s1_write) @[DCache.scala 198:63] + reg pstore1_cmd : UInt<5>, clock @[Reg.scala 34:16] + when _T_1435 : @[Reg.scala 35:19] + pstore1_cmd <= s1_req.cmd @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1437 = and(s1_valid_not_nacked, s1_write) @[DCache.scala 199:63] + reg pstore1_typ : UInt<3>, clock @[Reg.scala 34:16] + when _T_1437 : @[Reg.scala 35:19] + pstore1_typ <= s1_req.typ @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1439 = and(s1_valid_not_nacked, s1_write) @[DCache.scala 200:62] + reg pstore1_addr : UInt<32>, clock @[Reg.scala 34:16] + when _T_1439 : @[Reg.scala 35:19] + pstore1_addr <= tlb.io.resp.paddr @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1441 = and(s1_valid_not_nacked, s1_write) @[DCache.scala 201:68] + reg pstore1_data : UInt<64>, clock @[Reg.scala 34:16] + when _T_1441 : @[Reg.scala 35:19] + pstore1_data <= io.cpu.s1_data @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1443 = and(s1_valid_not_nacked, s1_write) @[DCache.scala 202:63] + reg pstore1_way : UInt<4>, clock @[Reg.scala 34:16] + when _T_1443 : @[Reg.scala 35:19] + pstore1_way <= s1_hit_way @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1445 = bits(pstore1_typ, 1, 0) @[AmoAlu.scala 12:17] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[AmoAlu.scala 28:19] + node _T_1448 = bits(pstore1_data, 7, 0) @[AmoAlu.scala 28:66] + node _T_1449 = cat(_T_1448, _T_1448) @[Cat.scala 30:58] + node _T_1450 = cat(_T_1449, _T_1449) @[Cat.scala 30:58] + node _T_1451 = cat(_T_1450, _T_1450) @[Cat.scala 30:58] + node _T_1453 = eq(_T_1445, UInt<1>("h01")) @[AmoAlu.scala 28:19] + node _T_1454 = bits(pstore1_data, 15, 0) @[AmoAlu.scala 28:66] + node _T_1455 = cat(_T_1454, _T_1454) @[Cat.scala 30:58] + node _T_1456 = cat(_T_1455, _T_1455) @[Cat.scala 30:58] + node _T_1458 = eq(_T_1445, UInt<2>("h02")) @[AmoAlu.scala 28:19] + node _T_1459 = bits(pstore1_data, 31, 0) @[AmoAlu.scala 28:66] + node _T_1460 = cat(_T_1459, _T_1459) @[Cat.scala 30:58] + node _T_1461 = mux(_T_1458, _T_1460, pstore1_data) @[AmoAlu.scala 28:13] + node _T_1462 = mux(_T_1453, _T_1456, _T_1461) @[AmoAlu.scala 28:13] + node _T_1463 = mux(_T_1447, _T_1451, _T_1462) @[AmoAlu.scala 28:13] + wire pstore1_storegen_data : UInt + pstore1_storegen_data is invalid + pstore1_storegen_data <= _T_1463 + node _T_1466 = eq(pstore1_cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_1468 = eq(pstore1_cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_1469 = or(_T_1466, _T_1468) @[Consts.scala 35:41] + node _T_1471 = eq(pstore1_cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_1472 = or(_T_1469, _T_1471) @[Consts.scala 35:58] + node _T_1473 = bits(pstore1_cmd, 3, 3) @[Consts.scala 33:29] + node _T_1475 = eq(pstore1_cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_1476 = or(_T_1473, _T_1475) @[Consts.scala 33:33] + node _T_1477 = or(_T_1472, _T_1476) @[Consts.scala 35:75] + node pstore1_amo = and(UInt<1>("h01"), _T_1477) @[DCache.scala 205:40] + node _T_1478 = and(pstore1_valid, pstore2_valid) @[DCache.scala 206:47] + node _T_1479 = and(s1_valid, s1_write) @[DCache.scala 206:78] + node _T_1480 = or(_T_1479, pstore1_amo) @[DCache.scala 206:91] + node pstore_drain_structural = and(_T_1478, _T_1480) @[DCache.scala 206:64] + node _T_1482 = eq(io.cpu.req.bits.cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_1484 = eq(io.cpu.req.bits.cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_1485 = or(_T_1482, _T_1484) @[Consts.scala 35:41] + node _T_1487 = eq(io.cpu.req.bits.cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_1488 = or(_T_1485, _T_1487) @[Consts.scala 35:58] + node _T_1489 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] + node _T_1491 = eq(io.cpu.req.bits.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_1492 = or(_T_1489, _T_1491) @[Consts.scala 33:33] + node _T_1493 = or(_T_1488, _T_1492) @[Consts.scala 35:75] + node _T_1494 = and(io.cpu.req.valid, _T_1493) @[DCache.scala 207:55] + node pstore_drain_opportunistic = eq(_T_1494, UInt<1>("h00")) @[DCache.scala 207:36] + node pstore_drain_on_miss = or(releaseInFlight, io.cpu.s2_nack) @[DCache.scala 208:46] + node _T_1497 = and(UInt<1>("h01"), pstore_drain_structural) @[DCache.scala 210:24] + node _T_1499 = eq(pstore1_amo, UInt<1>("h00")) @[DCache.scala 211:25] + node _T_1500 = and(pstore1_valid, _T_1499) @[DCache.scala 211:22] + node _T_1501 = or(_T_1500, pstore2_valid) @[DCache.scala 211:39] + node _T_1502 = or(pstore_drain_opportunistic, pstore_drain_on_miss) @[DCache.scala 211:88] + node _T_1503 = and(_T_1501, _T_1502) @[DCache.scala 211:57] + node pstore_drain = or(_T_1497, _T_1503) @[DCache.scala 210:51] + node _T_1504 = and(s2_valid_hit, s2_write) @[DCache.scala 213:39] + node _T_1506 = eq(s2_sc_fail, UInt<1>("h00")) @[DCache.scala 213:54] + node _T_1507 = and(_T_1504, _T_1506) @[DCache.scala 213:51] + reg _T_1509 : UInt<1>, clock @[DCache.scala 214:27] + node _T_1511 = eq(_T_1507, UInt<1>("h00")) @[DCache.scala 215:12] + node _T_1513 = eq(_T_1509, UInt<1>("h00")) @[DCache.scala 215:31] + node _T_1514 = or(_T_1511, _T_1513) @[DCache.scala 215:28] + node _T_1515 = or(_T_1514, reset) @[DCache.scala 215:11] + node _T_1517 = eq(_T_1515, UInt<1>("h00")) @[DCache.scala 215:11] + when _T_1517 : @[DCache.scala 215:11] + printf(clock, UInt<1>(1), "Assertion failed\n at DCache.scala:215 assert(!s2_store_valid || !pstore1_held)\n") @[DCache.scala 215:11] + stop(clock, UInt<1>(1), 1) @[DCache.scala 215:11] + skip @[DCache.scala 215:11] + node _T_1518 = or(_T_1507, _T_1509) @[DCache.scala 216:37] + node _T_1519 = and(_T_1518, pstore2_valid) @[DCache.scala 216:54] + node _T_1521 = eq(pstore_drain, UInt<1>("h00")) @[DCache.scala 216:74] + node _T_1522 = and(_T_1519, _T_1521) @[DCache.scala 216:71] + _T_1509 <= _T_1522 @[DCache.scala 216:18] + node _T_1523 = or(_T_1507, _T_1509) @[DCache.scala 217:20] + pstore1_valid <= _T_1523 @[DCache.scala 212:17] + node _T_1524 = eq(pstore2_valid, pstore_drain) @[DCache.scala 219:57] + node advance_pstore1 = and(pstore1_valid, _T_1524) @[DCache.scala 219:39] + node _T_1526 = eq(pstore_drain, UInt<1>("h00")) @[DCache.scala 220:37] + node _T_1527 = and(pstore2_valid, _T_1526) @[DCache.scala 220:34] + node _T_1528 = or(_T_1527, advance_pstore1) @[DCache.scala 220:51] + pstore2_valid <= _T_1528 @[DCache.scala 220:17] + reg pstore2_addr : UInt<32>, clock @[Reg.scala 34:16] + when advance_pstore1 : @[Reg.scala 35:19] + pstore2_addr <= pstore1_addr @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg pstore2_way : UInt<4>, clock @[Reg.scala 34:16] + when advance_pstore1 : @[Reg.scala 35:19] + pstore2_way <= pstore1_way @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg pstore2_storegen_data : UInt, clock @[Reg.scala 34:16] + when advance_pstore1 : @[Reg.scala 35:19] + pstore2_storegen_data <= pstore1_storegen_data @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1533 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_1535 = mux(_T_1533, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1537 = geq(_T_1445, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_1540 = mux(_T_1537, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1541 = or(_T_1535, _T_1540) @[AmoAlu.scala 19:46] + node _T_1542 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_1544 = mux(_T_1542, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_1545 = cat(_T_1541, _T_1544) @[Cat.scala 30:58] + node _T_1546 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_1548 = mux(_T_1546, _T_1545, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1550 = geq(_T_1445, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_1553 = mux(_T_1550, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1554 = or(_T_1548, _T_1553) @[AmoAlu.scala 19:46] + node _T_1555 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_1557 = mux(_T_1555, UInt<1>("h00"), _T_1545) @[AmoAlu.scala 20:22] + node _T_1558 = cat(_T_1554, _T_1557) @[Cat.scala 30:58] + node _T_1559 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_1561 = mux(_T_1559, _T_1558, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1563 = geq(_T_1445, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_1566 = mux(_T_1563, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1567 = or(_T_1561, _T_1566) @[AmoAlu.scala 19:46] + node _T_1568 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_1570 = mux(_T_1568, UInt<1>("h00"), _T_1558) @[AmoAlu.scala 20:22] + node _T_1571 = cat(_T_1567, _T_1570) @[Cat.scala 30:58] + reg pstore2_storegen_mask : UInt<8>, clock @[Reg.scala 34:16] + when advance_pstore1 : @[Reg.scala 35:19] + pstore2_storegen_mask <= _T_1571 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + dataArb.io.in[0].valid <= pstore_drain @[DCache.scala 225:26] + dataArb.io.in[0].bits.write <= UInt<1>("h01") @[DCache.scala 226:31] + node _T_1574 = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[DCache.scala 227:36] + dataArb.io.in[0].bits.addr <= _T_1574 @[DCache.scala 227:30] + node _T_1575 = mux(pstore2_valid, pstore2_way, pstore1_way) @[DCache.scala 228:38] + dataArb.io.in[0].bits.way_en <= _T_1575 @[DCache.scala 228:32] + node _T_1576 = mux(pstore2_valid, pstore2_storegen_data, pstore1_storegen_data) @[DCache.scala 229:52] + dataArb.io.in[0].bits.wdata <= _T_1576 @[DCache.scala 229:31] + node _T_1577 = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[DCache.scala 230:30] + node pstore_mask_shift = shl(UInt<1>("h00"), 3) @[DCache.scala 230:106] + node _T_1580 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_1582 = mux(_T_1580, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1584 = geq(_T_1445, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_1587 = mux(_T_1584, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1588 = or(_T_1582, _T_1587) @[AmoAlu.scala 19:46] + node _T_1589 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_1591 = mux(_T_1589, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_1592 = cat(_T_1588, _T_1591) @[Cat.scala 30:58] + node _T_1593 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_1595 = mux(_T_1593, _T_1592, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1597 = geq(_T_1445, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_1600 = mux(_T_1597, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1601 = or(_T_1595, _T_1600) @[AmoAlu.scala 19:46] + node _T_1602 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_1604 = mux(_T_1602, UInt<1>("h00"), _T_1592) @[AmoAlu.scala 20:22] + node _T_1605 = cat(_T_1601, _T_1604) @[Cat.scala 30:58] + node _T_1606 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_1608 = mux(_T_1606, _T_1605, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1610 = geq(_T_1445, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_1613 = mux(_T_1610, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1614 = or(_T_1608, _T_1613) @[AmoAlu.scala 19:46] + node _T_1615 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_1617 = mux(_T_1615, UInt<1>("h00"), _T_1605) @[AmoAlu.scala 20:22] + node _T_1618 = cat(_T_1614, _T_1617) @[Cat.scala 30:58] + node _T_1619 = mux(pstore2_valid, pstore2_storegen_mask, _T_1618) @[DCache.scala 231:37] + node _T_1620 = dshl(_T_1619, pstore_mask_shift) @[DCache.scala 231:99] + dataArb.io.in[0].bits.wmask <= _T_1620 @[DCache.scala 231:31] + node s1_idx = bits(s1_req.addr, 11, 3) @[DCache.scala 234:27] + node _T_1621 = bits(pstore1_addr, 11, 3) @[DCache.scala 236:36] + node _T_1622 = eq(_T_1621, s1_idx) @[DCache.scala 236:58] + node _T_1623 = and(pstore1_valid, _T_1622) @[DCache.scala 236:21] + node _T_1625 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_1627 = mux(_T_1625, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1629 = geq(_T_1445, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_1632 = mux(_T_1629, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1633 = or(_T_1627, _T_1632) @[AmoAlu.scala 19:46] + node _T_1634 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_1636 = mux(_T_1634, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_1637 = cat(_T_1633, _T_1636) @[Cat.scala 30:58] + node _T_1638 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_1640 = mux(_T_1638, _T_1637, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1642 = geq(_T_1445, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_1645 = mux(_T_1642, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1646 = or(_T_1640, _T_1645) @[AmoAlu.scala 19:46] + node _T_1647 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_1649 = mux(_T_1647, UInt<1>("h00"), _T_1637) @[AmoAlu.scala 20:22] + node _T_1650 = cat(_T_1646, _T_1649) @[Cat.scala 30:58] + node _T_1651 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_1653 = mux(_T_1651, _T_1650, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1655 = geq(_T_1445, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_1658 = mux(_T_1655, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1659 = or(_T_1653, _T_1658) @[AmoAlu.scala 19:46] + node _T_1660 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_1662 = mux(_T_1660, UInt<1>("h00"), _T_1650) @[AmoAlu.scala 20:22] + node _T_1663 = cat(_T_1659, _T_1662) @[Cat.scala 30:58] + node _T_1665 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_1667 = mux(_T_1665, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1669 = geq(_T_1386, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_1672 = mux(_T_1669, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1673 = or(_T_1667, _T_1672) @[AmoAlu.scala 19:46] + node _T_1674 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_1676 = mux(_T_1674, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_1677 = cat(_T_1673, _T_1676) @[Cat.scala 30:58] + node _T_1678 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_1680 = mux(_T_1678, _T_1677, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1682 = geq(_T_1386, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_1685 = mux(_T_1682, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1686 = or(_T_1680, _T_1685) @[AmoAlu.scala 19:46] + node _T_1687 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_1689 = mux(_T_1687, UInt<1>("h00"), _T_1677) @[AmoAlu.scala 20:22] + node _T_1690 = cat(_T_1686, _T_1689) @[Cat.scala 30:58] + node _T_1691 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_1693 = mux(_T_1691, _T_1690, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1695 = geq(_T_1386, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_1698 = mux(_T_1695, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1699 = or(_T_1693, _T_1698) @[AmoAlu.scala 19:46] + node _T_1700 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_1702 = mux(_T_1700, UInt<1>("h00"), _T_1690) @[AmoAlu.scala 20:22] + node _T_1703 = cat(_T_1699, _T_1702) @[Cat.scala 30:58] + node _T_1704 = and(_T_1663, _T_1703) @[DCache.scala 236:95] + node _T_1706 = neq(_T_1704, UInt<1>("h00")) @[DCache.scala 236:115] + node _T_1707 = and(_T_1623, _T_1706) @[DCache.scala 236:69] + node _T_1708 = bits(pstore2_addr, 11, 3) @[DCache.scala 237:36] + node _T_1709 = eq(_T_1708, s1_idx) @[DCache.scala 237:58] + node _T_1710 = and(pstore2_valid, _T_1709) @[DCache.scala 237:21] + node _T_1712 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 19:27] + node _T_1714 = mux(_T_1712, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1716 = geq(_T_1386, UInt<1>("h01")) @[AmoAlu.scala 19:57] + node _T_1719 = mux(_T_1716, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1720 = or(_T_1714, _T_1719) @[AmoAlu.scala 19:46] + node _T_1721 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 20:27] + node _T_1723 = mux(_T_1721, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 20:22] + node _T_1724 = cat(_T_1720, _T_1723) @[Cat.scala 30:58] + node _T_1725 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 19:27] + node _T_1727 = mux(_T_1725, _T_1724, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1729 = geq(_T_1386, UInt<2>("h02")) @[AmoAlu.scala 19:57] + node _T_1732 = mux(_T_1729, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1733 = or(_T_1727, _T_1732) @[AmoAlu.scala 19:46] + node _T_1734 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 20:27] + node _T_1736 = mux(_T_1734, UInt<1>("h00"), _T_1724) @[AmoAlu.scala 20:22] + node _T_1737 = cat(_T_1733, _T_1736) @[Cat.scala 30:58] + node _T_1738 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 19:27] + node _T_1740 = mux(_T_1738, _T_1737, UInt<1>("h00")) @[AmoAlu.scala 19:22] + node _T_1742 = geq(_T_1386, UInt<2>("h03")) @[AmoAlu.scala 19:57] + node _T_1745 = mux(_T_1742, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 19:51] + node _T_1746 = or(_T_1740, _T_1745) @[AmoAlu.scala 19:46] + node _T_1747 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 20:27] + node _T_1749 = mux(_T_1747, UInt<1>("h00"), _T_1737) @[AmoAlu.scala 20:22] + node _T_1750 = cat(_T_1746, _T_1749) @[Cat.scala 30:58] + node _T_1751 = and(pstore2_storegen_mask, _T_1750) @[DCache.scala 237:95] + node _T_1753 = neq(_T_1751, UInt<1>("h00")) @[DCache.scala 237:115] + node _T_1754 = and(_T_1710, _T_1753) @[DCache.scala 237:69] + node _T_1755 = or(_T_1707, _T_1754) @[DCache.scala 236:120] + node s1_raw_hazard = and(s1_read, _T_1755) @[DCache.scala 235:31] + node _T_1756 = and(s1_valid, s1_raw_hazard) @[DCache.scala 238:18] + when _T_1756 : @[DCache.scala 238:36] + s1_nack <= UInt<1>("h01") @[DCache.scala 238:46] + skip @[DCache.scala 238:36] + node _T_1758 = and(s2_valid_hit, s2_update_meta) @[DCache.scala 240:48] + node _T_1760 = eq(s2_victim_dirty, UInt<1>("h00")) @[DCache.scala 240:87] + node _T_1761 = and(s2_victimize, _T_1760) @[DCache.scala 240:84] + node _T_1762 = or(_T_1758, _T_1761) @[DCache.scala 240:67] + metaWriteArb.io.in[0].valid <= _T_1762 @[DCache.scala 240:31] + metaWriteArb.io.in[0].bits.way_en <= s2_victim_way @[DCache.scala 241:37] + node _T_1763 = bits(s2_req.addr, 11, 6) @[DCache.scala 242:48] + metaWriteArb.io.in[0].bits.idx <= _T_1763 @[DCache.scala 242:34] + wire _T_1767 : {state : UInt<2>} @[Metadata.scala 160:20] + _T_1767 is invalid @[Metadata.scala 160:20] + _T_1767.state <= UInt<2>("h00") @[Metadata.scala 161:16] + node _T_1769 = mux(s2_valid_hit, s2_new_hit_state, _T_1767) @[DCache.scala 243:45] + metaWriteArb.io.in[0].bits.data.coh <- _T_1769 @[DCache.scala 243:39] + node _T_1771 = bits(s2_req.addr, 31, 12) @[DCache.scala 244:53] + metaWriteArb.io.in[0].bits.data.tag <= _T_1771 @[DCache.scala 244:39] + node _T_1772 = not(uncachedInFlight[0]) @[DCache.scala 247:34] + node _T_1773 = bits(_T_1772, 0, 0) @[OneHot.scala 39:40] + node a_size = bits(s2_req.typ, 1, 0) @[DCache.scala 250:26] + node _T_1775 = eq(_T_1445, UInt<1>("h00")) @[AmoAlu.scala 28:19] + node _T_1776 = bits(pstore1_data, 7, 0) @[AmoAlu.scala 28:66] + node _T_1777 = cat(_T_1776, _T_1776) @[Cat.scala 30:58] + node _T_1778 = cat(_T_1777, _T_1777) @[Cat.scala 30:58] + node _T_1779 = cat(_T_1778, _T_1778) @[Cat.scala 30:58] + node _T_1781 = eq(_T_1445, UInt<1>("h01")) @[AmoAlu.scala 28:19] + node _T_1782 = bits(pstore1_data, 15, 0) @[AmoAlu.scala 28:66] + node _T_1783 = cat(_T_1782, _T_1782) @[Cat.scala 30:58] + node _T_1784 = cat(_T_1783, _T_1783) @[Cat.scala 30:58] + node _T_1786 = eq(_T_1445, UInt<2>("h02")) @[AmoAlu.scala 28:19] + node _T_1787 = bits(pstore1_data, 31, 0) @[AmoAlu.scala 28:66] + node _T_1788 = cat(_T_1787, _T_1787) @[Cat.scala 30:58] + node _T_1789 = mux(_T_1786, _T_1788, pstore1_data) @[AmoAlu.scala 28:13] + node _T_1790 = mux(_T_1781, _T_1784, _T_1789) @[AmoAlu.scala 28:13] + node a_data = mux(_T_1775, _T_1779, _T_1790) @[AmoAlu.scala 28:13] + node _T_1794 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_1796 = leq(UInt<3>("h06"), UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1797 = and(_T_1794, _T_1796) @[Parameters.scala 63:37] + node _T_1798 = or(UInt<1>("h00"), _T_1797) @[Parameters.scala 132:31] + node _T_1800 = xor(acquire_address, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_1801 = cvt(_T_1800) @[Parameters.scala 117:49] + node _T_1803 = and(_T_1801, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1804 = asSInt(_T_1803) @[Parameters.scala 117:52] + node _T_1806 = eq(_T_1804, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1808 = xor(acquire_address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1809 = cvt(_T_1808) @[Parameters.scala 117:49] + node _T_1811 = and(_T_1809, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_1812 = asSInt(_T_1811) @[Parameters.scala 117:52] + node _T_1814 = eq(_T_1812, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1815 = or(_T_1806, _T_1814) @[Parameters.scala 133:42] + node _T_1816 = and(_T_1798, _T_1815) @[Parameters.scala 132:56] + node _T_1819 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1821 = xor(acquire_address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1822 = cvt(_T_1821) @[Parameters.scala 117:49] + node _T_1824 = and(_T_1822, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1825 = asSInt(_T_1824) @[Parameters.scala 117:52] + node _T_1827 = eq(_T_1825, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1829 = xor(acquire_address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1830 = cvt(_T_1829) @[Parameters.scala 117:49] + node _T_1832 = and(_T_1830, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_1833 = asSInt(_T_1832) @[Parameters.scala 117:52] + node _T_1835 = eq(_T_1833, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1837 = xor(acquire_address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1838 = cvt(_T_1837) @[Parameters.scala 117:49] + node _T_1840 = and(_T_1838, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1841 = asSInt(_T_1840) @[Parameters.scala 117:52] + node _T_1843 = eq(_T_1841, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1844 = or(_T_1827, _T_1835) @[Parameters.scala 133:42] + node _T_1845 = or(_T_1844, _T_1843) @[Parameters.scala 133:42] + node _T_1846 = and(_T_1819, _T_1845) @[Parameters.scala 132:56] + node _T_1848 = or(UInt<1>("h00"), _T_1816) @[Parameters.scala 134:30] + node _T_1849 = or(_T_1848, _T_1846) @[Parameters.scala 134:30] + wire acquire : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 262:17] + acquire is invalid @[Edges.scala 262:17] + acquire.opcode <= UInt<3>("h06") @[Edges.scala 263:15] + acquire.param <= s2_grow_param @[Edges.scala 264:15] + acquire.size <= UInt<3>("h06") @[Edges.scala 265:15] + acquire.source <= UInt<1>("h00") @[Edges.scala 266:15] + acquire.address <= acquire_address @[Edges.scala 267:15] + node _T_1868 = dshl(UInt<1>("h01"), UInt<2>("h02")) @[OneHot.scala 49:12] + node _T_1869 = bits(_T_1868, 2, 0) @[OneHot.scala 49:37] + node _T_1871 = geq(UInt<3>("h06"), UInt<2>("h03")) @[package.scala 41:21] + node _T_1873 = bits(_T_1869, 2, 2) @[package.scala 44:26] + node _T_1874 = bits(acquire_address, 2, 2) @[package.scala 45:26] + node _T_1876 = eq(_T_1874, UInt<1>("h00")) @[package.scala 46:20] + node _T_1877 = and(UInt<1>("h01"), _T_1876) @[package.scala 49:27] + node _T_1878 = and(_T_1873, _T_1877) @[package.scala 50:38] + node _T_1879 = or(_T_1871, _T_1878) @[package.scala 50:29] + node _T_1880 = and(UInt<1>("h01"), _T_1874) @[package.scala 49:27] + node _T_1881 = and(_T_1873, _T_1880) @[package.scala 50:38] + node _T_1882 = or(_T_1871, _T_1881) @[package.scala 50:29] + node _T_1883 = bits(_T_1869, 1, 1) @[package.scala 44:26] + node _T_1884 = bits(acquire_address, 1, 1) @[package.scala 45:26] + node _T_1886 = eq(_T_1884, UInt<1>("h00")) @[package.scala 46:20] + node _T_1887 = and(_T_1877, _T_1886) @[package.scala 49:27] + node _T_1888 = and(_T_1883, _T_1887) @[package.scala 50:38] + node _T_1889 = or(_T_1879, _T_1888) @[package.scala 50:29] + node _T_1890 = and(_T_1877, _T_1884) @[package.scala 49:27] + node _T_1891 = and(_T_1883, _T_1890) @[package.scala 50:38] + node _T_1892 = or(_T_1879, _T_1891) @[package.scala 50:29] + node _T_1893 = and(_T_1880, _T_1886) @[package.scala 49:27] + node _T_1894 = and(_T_1883, _T_1893) @[package.scala 50:38] + node _T_1895 = or(_T_1882, _T_1894) @[package.scala 50:29] + node _T_1896 = and(_T_1880, _T_1884) @[package.scala 49:27] + node _T_1897 = and(_T_1883, _T_1896) @[package.scala 50:38] + node _T_1898 = or(_T_1882, _T_1897) @[package.scala 50:29] + node _T_1899 = bits(_T_1869, 0, 0) @[package.scala 44:26] + node _T_1900 = bits(acquire_address, 0, 0) @[package.scala 45:26] + node _T_1902 = eq(_T_1900, UInt<1>("h00")) @[package.scala 46:20] + node _T_1903 = and(_T_1887, _T_1902) @[package.scala 49:27] + node _T_1904 = and(_T_1899, _T_1903) @[package.scala 50:38] + node _T_1905 = or(_T_1889, _T_1904) @[package.scala 50:29] + node _T_1906 = and(_T_1887, _T_1900) @[package.scala 49:27] + node _T_1907 = and(_T_1899, _T_1906) @[package.scala 50:38] + node _T_1908 = or(_T_1889, _T_1907) @[package.scala 50:29] + node _T_1909 = and(_T_1890, _T_1902) @[package.scala 49:27] + node _T_1910 = and(_T_1899, _T_1909) @[package.scala 50:38] + node _T_1911 = or(_T_1892, _T_1910) @[package.scala 50:29] + node _T_1912 = and(_T_1890, _T_1900) @[package.scala 49:27] + node _T_1913 = and(_T_1899, _T_1912) @[package.scala 50:38] + node _T_1914 = or(_T_1892, _T_1913) @[package.scala 50:29] + node _T_1915 = and(_T_1893, _T_1902) @[package.scala 49:27] + node _T_1916 = and(_T_1899, _T_1915) @[package.scala 50:38] + node _T_1917 = or(_T_1895, _T_1916) @[package.scala 50:29] + node _T_1918 = and(_T_1893, _T_1900) @[package.scala 49:27] + node _T_1919 = and(_T_1899, _T_1918) @[package.scala 50:38] + node _T_1920 = or(_T_1895, _T_1919) @[package.scala 50:29] + node _T_1921 = and(_T_1896, _T_1902) @[package.scala 49:27] + node _T_1922 = and(_T_1899, _T_1921) @[package.scala 50:38] + node _T_1923 = or(_T_1898, _T_1922) @[package.scala 50:29] + node _T_1924 = and(_T_1896, _T_1900) @[package.scala 49:27] + node _T_1925 = and(_T_1899, _T_1924) @[package.scala 50:38] + node _T_1926 = or(_T_1898, _T_1925) @[package.scala 50:29] + node _T_1927 = cat(_T_1908, _T_1905) @[Cat.scala 30:58] + node _T_1928 = cat(_T_1914, _T_1911) @[Cat.scala 30:58] + node _T_1929 = cat(_T_1928, _T_1927) @[Cat.scala 30:58] + node _T_1930 = cat(_T_1920, _T_1917) @[Cat.scala 30:58] + node _T_1931 = cat(_T_1926, _T_1923) @[Cat.scala 30:58] + node _T_1932 = cat(_T_1931, _T_1930) @[Cat.scala 30:58] + node _T_1933 = cat(_T_1932, _T_1929) @[Cat.scala 30:58] + acquire.mask <= _T_1933 @[Edges.scala 268:15] + acquire.data <= UInt<1>("h00") @[Edges.scala 269:15] + node _T_1937 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_1939 = leq(a_size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1940 = and(_T_1937, _T_1939) @[Parameters.scala 63:37] + node _T_1941 = or(UInt<1>("h00"), _T_1940) @[Parameters.scala 132:31] + node _T_1943 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1944 = cvt(_T_1943) @[Parameters.scala 117:49] + node _T_1946 = and(_T_1944, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_1947 = asSInt(_T_1946) @[Parameters.scala 117:52] + node _T_1949 = eq(_T_1947, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1950 = and(_T_1941, _T_1949) @[Parameters.scala 132:56] + node _T_1953 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_1955 = leq(a_size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1956 = and(_T_1953, _T_1955) @[Parameters.scala 63:37] + node _T_1957 = or(UInt<1>("h00"), _T_1956) @[Parameters.scala 132:31] + node _T_1959 = xor(s2_req.addr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_1960 = cvt(_T_1959) @[Parameters.scala 117:49] + node _T_1962 = and(_T_1960, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_1963 = asSInt(_T_1962) @[Parameters.scala 117:52] + node _T_1965 = eq(_T_1963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1966 = and(_T_1957, _T_1965) @[Parameters.scala 132:56] + node _T_1968 = or(UInt<1>("h00"), _T_1950) @[Parameters.scala 134:30] + node _T_1969 = or(_T_1968, _T_1966) @[Parameters.scala 134:30] + wire get : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 342:17] + get is invalid @[Edges.scala 342:17] + get.opcode <= UInt<3>("h04") @[Edges.scala 343:15] + get.param <= UInt<1>("h00") @[Edges.scala 344:15] + get.size <= a_size @[Edges.scala 345:15] + get.source <= UInt<1>("h00") @[Edges.scala 346:15] + get.address <= s2_req.addr @[Edges.scala 347:15] + node _T_1988 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_1989 = dshl(UInt<1>("h01"), _T_1988) @[OneHot.scala 49:12] + node _T_1990 = bits(_T_1989, 2, 0) @[OneHot.scala 49:37] + node _T_1992 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1994 = bits(_T_1990, 2, 2) @[package.scala 44:26] + node _T_1995 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_1997 = eq(_T_1995, UInt<1>("h00")) @[package.scala 46:20] + node _T_1998 = and(UInt<1>("h01"), _T_1997) @[package.scala 49:27] + node _T_1999 = and(_T_1994, _T_1998) @[package.scala 50:38] + node _T_2000 = or(_T_1992, _T_1999) @[package.scala 50:29] + node _T_2001 = and(UInt<1>("h01"), _T_1995) @[package.scala 49:27] + node _T_2002 = and(_T_1994, _T_2001) @[package.scala 50:38] + node _T_2003 = or(_T_1992, _T_2002) @[package.scala 50:29] + node _T_2004 = bits(_T_1990, 1, 1) @[package.scala 44:26] + node _T_2005 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2007 = eq(_T_2005, UInt<1>("h00")) @[package.scala 46:20] + node _T_2008 = and(_T_1998, _T_2007) @[package.scala 49:27] + node _T_2009 = and(_T_2004, _T_2008) @[package.scala 50:38] + node _T_2010 = or(_T_2000, _T_2009) @[package.scala 50:29] + node _T_2011 = and(_T_1998, _T_2005) @[package.scala 49:27] + node _T_2012 = and(_T_2004, _T_2011) @[package.scala 50:38] + node _T_2013 = or(_T_2000, _T_2012) @[package.scala 50:29] + node _T_2014 = and(_T_2001, _T_2007) @[package.scala 49:27] + node _T_2015 = and(_T_2004, _T_2014) @[package.scala 50:38] + node _T_2016 = or(_T_2003, _T_2015) @[package.scala 50:29] + node _T_2017 = and(_T_2001, _T_2005) @[package.scala 49:27] + node _T_2018 = and(_T_2004, _T_2017) @[package.scala 50:38] + node _T_2019 = or(_T_2003, _T_2018) @[package.scala 50:29] + node _T_2020 = bits(_T_1990, 0, 0) @[package.scala 44:26] + node _T_2021 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2023 = eq(_T_2021, UInt<1>("h00")) @[package.scala 46:20] + node _T_2024 = and(_T_2008, _T_2023) @[package.scala 49:27] + node _T_2025 = and(_T_2020, _T_2024) @[package.scala 50:38] + node _T_2026 = or(_T_2010, _T_2025) @[package.scala 50:29] + node _T_2027 = and(_T_2008, _T_2021) @[package.scala 49:27] + node _T_2028 = and(_T_2020, _T_2027) @[package.scala 50:38] + node _T_2029 = or(_T_2010, _T_2028) @[package.scala 50:29] + node _T_2030 = and(_T_2011, _T_2023) @[package.scala 49:27] + node _T_2031 = and(_T_2020, _T_2030) @[package.scala 50:38] + node _T_2032 = or(_T_2013, _T_2031) @[package.scala 50:29] + node _T_2033 = and(_T_2011, _T_2021) @[package.scala 49:27] + node _T_2034 = and(_T_2020, _T_2033) @[package.scala 50:38] + node _T_2035 = or(_T_2013, _T_2034) @[package.scala 50:29] + node _T_2036 = and(_T_2014, _T_2023) @[package.scala 49:27] + node _T_2037 = and(_T_2020, _T_2036) @[package.scala 50:38] + node _T_2038 = or(_T_2016, _T_2037) @[package.scala 50:29] + node _T_2039 = and(_T_2014, _T_2021) @[package.scala 49:27] + node _T_2040 = and(_T_2020, _T_2039) @[package.scala 50:38] + node _T_2041 = or(_T_2016, _T_2040) @[package.scala 50:29] + node _T_2042 = and(_T_2017, _T_2023) @[package.scala 49:27] + node _T_2043 = and(_T_2020, _T_2042) @[package.scala 50:38] + node _T_2044 = or(_T_2019, _T_2043) @[package.scala 50:29] + node _T_2045 = and(_T_2017, _T_2021) @[package.scala 49:27] + node _T_2046 = and(_T_2020, _T_2045) @[package.scala 50:38] + node _T_2047 = or(_T_2019, _T_2046) @[package.scala 50:29] + node _T_2048 = cat(_T_2029, _T_2026) @[Cat.scala 30:58] + node _T_2049 = cat(_T_2035, _T_2032) @[Cat.scala 30:58] + node _T_2050 = cat(_T_2049, _T_2048) @[Cat.scala 30:58] + node _T_2051 = cat(_T_2041, _T_2038) @[Cat.scala 30:58] + node _T_2052 = cat(_T_2047, _T_2044) @[Cat.scala 30:58] + node _T_2053 = cat(_T_2052, _T_2051) @[Cat.scala 30:58] + node _T_2054 = cat(_T_2053, _T_2050) @[Cat.scala 30:58] + get.mask <= _T_2054 @[Edges.scala 348:15] + get.data <= UInt<1>("h00") @[Edges.scala 349:15] + node _T_2058 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2060 = leq(a_size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2061 = and(_T_2058, _T_2060) @[Parameters.scala 63:37] + node _T_2062 = or(UInt<1>("h00"), _T_2061) @[Parameters.scala 132:31] + node _T_2064 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2065 = cvt(_T_2064) @[Parameters.scala 117:49] + node _T_2067 = and(_T_2065, asSInt(UInt<33>("h0fa000000"))) @[Parameters.scala 117:52] + node _T_2068 = asSInt(_T_2067) @[Parameters.scala 117:52] + node _T_2070 = eq(_T_2068, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2072 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2073 = cvt(_T_2072) @[Parameters.scala 117:49] + node _T_2075 = and(_T_2073, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_2076 = asSInt(_T_2075) @[Parameters.scala 117:52] + node _T_2078 = eq(_T_2076, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2080 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2081 = cvt(_T_2080) @[Parameters.scala 117:49] + node _T_2083 = and(_T_2081, asSInt(UInt<33>("h0fbff0000"))) @[Parameters.scala 117:52] + node _T_2084 = asSInt(_T_2083) @[Parameters.scala 117:52] + node _T_2086 = eq(_T_2084, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2088 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2089 = cvt(_T_2088) @[Parameters.scala 117:49] + node _T_2091 = and(_T_2089, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2092 = asSInt(_T_2091) @[Parameters.scala 117:52] + node _T_2094 = eq(_T_2092, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2096 = xor(s2_req.addr, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_2097 = cvt(_T_2096) @[Parameters.scala 117:49] + node _T_2099 = and(_T_2097, asSInt(UInt<33>("h0f8000000"))) @[Parameters.scala 117:52] + node _T_2100 = asSInt(_T_2099) @[Parameters.scala 117:52] + node _T_2102 = eq(_T_2100, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2103 = or(_T_2070, _T_2078) @[Parameters.scala 133:42] + node _T_2104 = or(_T_2103, _T_2086) @[Parameters.scala 133:42] + node _T_2105 = or(_T_2104, _T_2094) @[Parameters.scala 133:42] + node _T_2106 = or(_T_2105, _T_2102) @[Parameters.scala 133:42] + node _T_2107 = and(_T_2062, _T_2106) @[Parameters.scala 132:56] + node _T_2110 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2112 = leq(a_size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_2113 = and(_T_2110, _T_2112) @[Parameters.scala 63:37] + node _T_2114 = or(UInt<1>("h00"), _T_2113) @[Parameters.scala 132:31] + node _T_2116 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2117 = cvt(_T_2116) @[Parameters.scala 117:49] + node _T_2119 = and(_T_2117, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2120 = asSInt(_T_2119) @[Parameters.scala 117:52] + node _T_2122 = eq(_T_2120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2123 = and(_T_2114, _T_2122) @[Parameters.scala 132:56] + node _T_2126 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2128 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2129 = cvt(_T_2128) @[Parameters.scala 117:49] + node _T_2131 = and(_T_2129, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_2132 = asSInt(_T_2131) @[Parameters.scala 117:52] + node _T_2134 = eq(_T_2132, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2135 = and(_T_2126, _T_2134) @[Parameters.scala 132:56] + node _T_2137 = or(UInt<1>("h00"), _T_2107) @[Parameters.scala 134:30] + node _T_2138 = or(_T_2137, _T_2123) @[Parameters.scala 134:30] + node _T_2139 = or(_T_2138, _T_2135) @[Parameters.scala 134:30] + wire put : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 356:17] + put is invalid @[Edges.scala 356:17] + put.opcode <= UInt<1>("h00") @[Edges.scala 357:15] + put.param <= UInt<1>("h00") @[Edges.scala 358:15] + put.size <= a_size @[Edges.scala 359:15] + put.source <= UInt<1>("h00") @[Edges.scala 360:15] + put.address <= s2_req.addr @[Edges.scala 361:15] + node _T_2158 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2159 = dshl(UInt<1>("h01"), _T_2158) @[OneHot.scala 49:12] + node _T_2160 = bits(_T_2159, 2, 0) @[OneHot.scala 49:37] + node _T_2162 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2164 = bits(_T_2160, 2, 2) @[package.scala 44:26] + node _T_2165 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[package.scala 46:20] + node _T_2168 = and(UInt<1>("h01"), _T_2167) @[package.scala 49:27] + node _T_2169 = and(_T_2164, _T_2168) @[package.scala 50:38] + node _T_2170 = or(_T_2162, _T_2169) @[package.scala 50:29] + node _T_2171 = and(UInt<1>("h01"), _T_2165) @[package.scala 49:27] + node _T_2172 = and(_T_2164, _T_2171) @[package.scala 50:38] + node _T_2173 = or(_T_2162, _T_2172) @[package.scala 50:29] + node _T_2174 = bits(_T_2160, 1, 1) @[package.scala 44:26] + node _T_2175 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2177 = eq(_T_2175, UInt<1>("h00")) @[package.scala 46:20] + node _T_2178 = and(_T_2168, _T_2177) @[package.scala 49:27] + node _T_2179 = and(_T_2174, _T_2178) @[package.scala 50:38] + node _T_2180 = or(_T_2170, _T_2179) @[package.scala 50:29] + node _T_2181 = and(_T_2168, _T_2175) @[package.scala 49:27] + node _T_2182 = and(_T_2174, _T_2181) @[package.scala 50:38] + node _T_2183 = or(_T_2170, _T_2182) @[package.scala 50:29] + node _T_2184 = and(_T_2171, _T_2177) @[package.scala 49:27] + node _T_2185 = and(_T_2174, _T_2184) @[package.scala 50:38] + node _T_2186 = or(_T_2173, _T_2185) @[package.scala 50:29] + node _T_2187 = and(_T_2171, _T_2175) @[package.scala 49:27] + node _T_2188 = and(_T_2174, _T_2187) @[package.scala 50:38] + node _T_2189 = or(_T_2173, _T_2188) @[package.scala 50:29] + node _T_2190 = bits(_T_2160, 0, 0) @[package.scala 44:26] + node _T_2191 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2193 = eq(_T_2191, UInt<1>("h00")) @[package.scala 46:20] + node _T_2194 = and(_T_2178, _T_2193) @[package.scala 49:27] + node _T_2195 = and(_T_2190, _T_2194) @[package.scala 50:38] + node _T_2196 = or(_T_2180, _T_2195) @[package.scala 50:29] + node _T_2197 = and(_T_2178, _T_2191) @[package.scala 49:27] + node _T_2198 = and(_T_2190, _T_2197) @[package.scala 50:38] + node _T_2199 = or(_T_2180, _T_2198) @[package.scala 50:29] + node _T_2200 = and(_T_2181, _T_2193) @[package.scala 49:27] + node _T_2201 = and(_T_2190, _T_2200) @[package.scala 50:38] + node _T_2202 = or(_T_2183, _T_2201) @[package.scala 50:29] + node _T_2203 = and(_T_2181, _T_2191) @[package.scala 49:27] + node _T_2204 = and(_T_2190, _T_2203) @[package.scala 50:38] + node _T_2205 = or(_T_2183, _T_2204) @[package.scala 50:29] + node _T_2206 = and(_T_2184, _T_2193) @[package.scala 49:27] + node _T_2207 = and(_T_2190, _T_2206) @[package.scala 50:38] + node _T_2208 = or(_T_2186, _T_2207) @[package.scala 50:29] + node _T_2209 = and(_T_2184, _T_2191) @[package.scala 49:27] + node _T_2210 = and(_T_2190, _T_2209) @[package.scala 50:38] + node _T_2211 = or(_T_2186, _T_2210) @[package.scala 50:29] + node _T_2212 = and(_T_2187, _T_2193) @[package.scala 49:27] + node _T_2213 = and(_T_2190, _T_2212) @[package.scala 50:38] + node _T_2214 = or(_T_2189, _T_2213) @[package.scala 50:29] + node _T_2215 = and(_T_2187, _T_2191) @[package.scala 49:27] + node _T_2216 = and(_T_2190, _T_2215) @[package.scala 50:38] + node _T_2217 = or(_T_2189, _T_2216) @[package.scala 50:29] + node _T_2218 = cat(_T_2199, _T_2196) @[Cat.scala 30:58] + node _T_2219 = cat(_T_2205, _T_2202) @[Cat.scala 30:58] + node _T_2220 = cat(_T_2219, _T_2218) @[Cat.scala 30:58] + node _T_2221 = cat(_T_2211, _T_2208) @[Cat.scala 30:58] + node _T_2222 = cat(_T_2217, _T_2214) @[Cat.scala 30:58] + node _T_2223 = cat(_T_2222, _T_2221) @[Cat.scala 30:58] + node _T_2224 = cat(_T_2223, _T_2220) @[Cat.scala 30:58] + put.mask <= _T_2224 @[Edges.scala 362:15] + put.data <= a_data @[Edges.scala 363:15] + wire _T_2233 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[DCache.scala 260:31] + _T_2233 is invalid @[DCache.scala 260:31] + node _T_2245 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2247 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_2248 = and(_T_2245, _T_2247) @[Parameters.scala 63:37] + node _T_2249 = or(UInt<1>("h00"), _T_2248) @[Parameters.scala 132:31] + node _T_2251 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2252 = cvt(_T_2251) @[Parameters.scala 117:49] + node _T_2254 = and(_T_2252, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2255 = asSInt(_T_2254) @[Parameters.scala 117:52] + node _T_2257 = eq(_T_2255, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2259 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2260 = cvt(_T_2259) @[Parameters.scala 117:49] + node _T_2262 = and(_T_2260, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_2263 = asSInt(_T_2262) @[Parameters.scala 117:52] + node _T_2265 = eq(_T_2263, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2267 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2268 = cvt(_T_2267) @[Parameters.scala 117:49] + node _T_2270 = and(_T_2268, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_2271 = asSInt(_T_2270) @[Parameters.scala 117:52] + node _T_2273 = eq(_T_2271, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2274 = or(_T_2257, _T_2265) @[Parameters.scala 133:42] + node _T_2275 = or(_T_2274, _T_2273) @[Parameters.scala 133:42] + node _T_2276 = and(_T_2249, _T_2275) @[Parameters.scala 132:56] + node _T_2279 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2281 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2282 = cvt(_T_2281) @[Parameters.scala 117:49] + node _T_2284 = and(_T_2282, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2285 = asSInt(_T_2284) @[Parameters.scala 117:52] + node _T_2287 = eq(_T_2285, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2289 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2290 = cvt(_T_2289) @[Parameters.scala 117:49] + node _T_2292 = and(_T_2290, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_2293 = asSInt(_T_2292) @[Parameters.scala 117:52] + node _T_2295 = eq(_T_2293, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2297 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2298 = cvt(_T_2297) @[Parameters.scala 117:49] + node _T_2300 = and(_T_2298, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2301 = asSInt(_T_2300) @[Parameters.scala 117:52] + node _T_2303 = eq(_T_2301, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2305 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2306 = cvt(_T_2305) @[Parameters.scala 117:49] + node _T_2308 = and(_T_2306, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2309 = asSInt(_T_2308) @[Parameters.scala 117:52] + node _T_2311 = eq(_T_2309, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2312 = or(_T_2287, _T_2295) @[Parameters.scala 133:42] + node _T_2313 = or(_T_2312, _T_2303) @[Parameters.scala 133:42] + node _T_2314 = or(_T_2313, _T_2311) @[Parameters.scala 133:42] + node _T_2315 = and(_T_2279, _T_2314) @[Parameters.scala 132:56] + node _T_2317 = or(UInt<1>("h00"), _T_2276) @[Parameters.scala 134:30] + node _T_2318 = or(_T_2317, _T_2315) @[Parameters.scala 134:30] + wire _T_2327 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 398:17] + _T_2327 is invalid @[Edges.scala 398:17] + _T_2327.opcode <= UInt<2>("h03") @[Edges.scala 399:15] + _T_2327.param <= UInt<3>("h03") @[Edges.scala 400:15] + _T_2327.size <= a_size @[Edges.scala 401:15] + _T_2327.source <= UInt<1>("h00") @[Edges.scala 402:15] + _T_2327.address <= s2_req.addr @[Edges.scala 403:15] + node _T_2337 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2338 = dshl(UInt<1>("h01"), _T_2337) @[OneHot.scala 49:12] + node _T_2339 = bits(_T_2338, 2, 0) @[OneHot.scala 49:37] + node _T_2341 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2343 = bits(_T_2339, 2, 2) @[package.scala 44:26] + node _T_2344 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2346 = eq(_T_2344, UInt<1>("h00")) @[package.scala 46:20] + node _T_2347 = and(UInt<1>("h01"), _T_2346) @[package.scala 49:27] + node _T_2348 = and(_T_2343, _T_2347) @[package.scala 50:38] + node _T_2349 = or(_T_2341, _T_2348) @[package.scala 50:29] + node _T_2350 = and(UInt<1>("h01"), _T_2344) @[package.scala 49:27] + node _T_2351 = and(_T_2343, _T_2350) @[package.scala 50:38] + node _T_2352 = or(_T_2341, _T_2351) @[package.scala 50:29] + node _T_2353 = bits(_T_2339, 1, 1) @[package.scala 44:26] + node _T_2354 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2356 = eq(_T_2354, UInt<1>("h00")) @[package.scala 46:20] + node _T_2357 = and(_T_2347, _T_2356) @[package.scala 49:27] + node _T_2358 = and(_T_2353, _T_2357) @[package.scala 50:38] + node _T_2359 = or(_T_2349, _T_2358) @[package.scala 50:29] + node _T_2360 = and(_T_2347, _T_2354) @[package.scala 49:27] + node _T_2361 = and(_T_2353, _T_2360) @[package.scala 50:38] + node _T_2362 = or(_T_2349, _T_2361) @[package.scala 50:29] + node _T_2363 = and(_T_2350, _T_2356) @[package.scala 49:27] + node _T_2364 = and(_T_2353, _T_2363) @[package.scala 50:38] + node _T_2365 = or(_T_2352, _T_2364) @[package.scala 50:29] + node _T_2366 = and(_T_2350, _T_2354) @[package.scala 49:27] + node _T_2367 = and(_T_2353, _T_2366) @[package.scala 50:38] + node _T_2368 = or(_T_2352, _T_2367) @[package.scala 50:29] + node _T_2369 = bits(_T_2339, 0, 0) @[package.scala 44:26] + node _T_2370 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2372 = eq(_T_2370, UInt<1>("h00")) @[package.scala 46:20] + node _T_2373 = and(_T_2357, _T_2372) @[package.scala 49:27] + node _T_2374 = and(_T_2369, _T_2373) @[package.scala 50:38] + node _T_2375 = or(_T_2359, _T_2374) @[package.scala 50:29] + node _T_2376 = and(_T_2357, _T_2370) @[package.scala 49:27] + node _T_2377 = and(_T_2369, _T_2376) @[package.scala 50:38] + node _T_2378 = or(_T_2359, _T_2377) @[package.scala 50:29] + node _T_2379 = and(_T_2360, _T_2372) @[package.scala 49:27] + node _T_2380 = and(_T_2369, _T_2379) @[package.scala 50:38] + node _T_2381 = or(_T_2362, _T_2380) @[package.scala 50:29] + node _T_2382 = and(_T_2360, _T_2370) @[package.scala 49:27] + node _T_2383 = and(_T_2369, _T_2382) @[package.scala 50:38] + node _T_2384 = or(_T_2362, _T_2383) @[package.scala 50:29] + node _T_2385 = and(_T_2363, _T_2372) @[package.scala 49:27] + node _T_2386 = and(_T_2369, _T_2385) @[package.scala 50:38] + node _T_2387 = or(_T_2365, _T_2386) @[package.scala 50:29] + node _T_2388 = and(_T_2363, _T_2370) @[package.scala 49:27] + node _T_2389 = and(_T_2369, _T_2388) @[package.scala 50:38] + node _T_2390 = or(_T_2365, _T_2389) @[package.scala 50:29] + node _T_2391 = and(_T_2366, _T_2372) @[package.scala 49:27] + node _T_2392 = and(_T_2369, _T_2391) @[package.scala 50:38] + node _T_2393 = or(_T_2368, _T_2392) @[package.scala 50:29] + node _T_2394 = and(_T_2366, _T_2370) @[package.scala 49:27] + node _T_2395 = and(_T_2369, _T_2394) @[package.scala 50:38] + node _T_2396 = or(_T_2368, _T_2395) @[package.scala 50:29] + node _T_2397 = cat(_T_2378, _T_2375) @[Cat.scala 30:58] + node _T_2398 = cat(_T_2384, _T_2381) @[Cat.scala 30:58] + node _T_2399 = cat(_T_2398, _T_2397) @[Cat.scala 30:58] + node _T_2400 = cat(_T_2390, _T_2387) @[Cat.scala 30:58] + node _T_2401 = cat(_T_2396, _T_2393) @[Cat.scala 30:58] + node _T_2402 = cat(_T_2401, _T_2400) @[Cat.scala 30:58] + node _T_2403 = cat(_T_2402, _T_2399) @[Cat.scala 30:58] + _T_2327.mask <= _T_2403 @[Edges.scala 404:15] + _T_2327.data <= a_data @[Edges.scala 405:15] + node _T_2408 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2410 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_2411 = and(_T_2408, _T_2410) @[Parameters.scala 63:37] + node _T_2412 = or(UInt<1>("h00"), _T_2411) @[Parameters.scala 132:31] + node _T_2414 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2415 = cvt(_T_2414) @[Parameters.scala 117:49] + node _T_2417 = and(_T_2415, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2418 = asSInt(_T_2417) @[Parameters.scala 117:52] + node _T_2420 = eq(_T_2418, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2422 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2423 = cvt(_T_2422) @[Parameters.scala 117:49] + node _T_2425 = and(_T_2423, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_2426 = asSInt(_T_2425) @[Parameters.scala 117:52] + node _T_2428 = eq(_T_2426, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2430 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2431 = cvt(_T_2430) @[Parameters.scala 117:49] + node _T_2433 = and(_T_2431, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_2434 = asSInt(_T_2433) @[Parameters.scala 117:52] + node _T_2436 = eq(_T_2434, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2437 = or(_T_2420, _T_2428) @[Parameters.scala 133:42] + node _T_2438 = or(_T_2437, _T_2436) @[Parameters.scala 133:42] + node _T_2439 = and(_T_2412, _T_2438) @[Parameters.scala 132:56] + node _T_2442 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2444 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2445 = cvt(_T_2444) @[Parameters.scala 117:49] + node _T_2447 = and(_T_2445, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2448 = asSInt(_T_2447) @[Parameters.scala 117:52] + node _T_2450 = eq(_T_2448, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2452 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2453 = cvt(_T_2452) @[Parameters.scala 117:49] + node _T_2455 = and(_T_2453, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_2456 = asSInt(_T_2455) @[Parameters.scala 117:52] + node _T_2458 = eq(_T_2456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2460 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2461 = cvt(_T_2460) @[Parameters.scala 117:49] + node _T_2463 = and(_T_2461, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2464 = asSInt(_T_2463) @[Parameters.scala 117:52] + node _T_2466 = eq(_T_2464, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2468 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2469 = cvt(_T_2468) @[Parameters.scala 117:49] + node _T_2471 = and(_T_2469, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2472 = asSInt(_T_2471) @[Parameters.scala 117:52] + node _T_2474 = eq(_T_2472, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2475 = or(_T_2450, _T_2458) @[Parameters.scala 133:42] + node _T_2476 = or(_T_2475, _T_2466) @[Parameters.scala 133:42] + node _T_2477 = or(_T_2476, _T_2474) @[Parameters.scala 133:42] + node _T_2478 = and(_T_2442, _T_2477) @[Parameters.scala 132:56] + node _T_2480 = or(UInt<1>("h00"), _T_2439) @[Parameters.scala 134:30] + node _T_2481 = or(_T_2480, _T_2478) @[Parameters.scala 134:30] + wire _T_2490 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 398:17] + _T_2490 is invalid @[Edges.scala 398:17] + _T_2490.opcode <= UInt<2>("h03") @[Edges.scala 399:15] + _T_2490.param <= UInt<3>("h00") @[Edges.scala 400:15] + _T_2490.size <= a_size @[Edges.scala 401:15] + _T_2490.source <= UInt<1>("h00") @[Edges.scala 402:15] + _T_2490.address <= s2_req.addr @[Edges.scala 403:15] + node _T_2500 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2501 = dshl(UInt<1>("h01"), _T_2500) @[OneHot.scala 49:12] + node _T_2502 = bits(_T_2501, 2, 0) @[OneHot.scala 49:37] + node _T_2504 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2506 = bits(_T_2502, 2, 2) @[package.scala 44:26] + node _T_2507 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2509 = eq(_T_2507, UInt<1>("h00")) @[package.scala 46:20] + node _T_2510 = and(UInt<1>("h01"), _T_2509) @[package.scala 49:27] + node _T_2511 = and(_T_2506, _T_2510) @[package.scala 50:38] + node _T_2512 = or(_T_2504, _T_2511) @[package.scala 50:29] + node _T_2513 = and(UInt<1>("h01"), _T_2507) @[package.scala 49:27] + node _T_2514 = and(_T_2506, _T_2513) @[package.scala 50:38] + node _T_2515 = or(_T_2504, _T_2514) @[package.scala 50:29] + node _T_2516 = bits(_T_2502, 1, 1) @[package.scala 44:26] + node _T_2517 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2519 = eq(_T_2517, UInt<1>("h00")) @[package.scala 46:20] + node _T_2520 = and(_T_2510, _T_2519) @[package.scala 49:27] + node _T_2521 = and(_T_2516, _T_2520) @[package.scala 50:38] + node _T_2522 = or(_T_2512, _T_2521) @[package.scala 50:29] + node _T_2523 = and(_T_2510, _T_2517) @[package.scala 49:27] + node _T_2524 = and(_T_2516, _T_2523) @[package.scala 50:38] + node _T_2525 = or(_T_2512, _T_2524) @[package.scala 50:29] + node _T_2526 = and(_T_2513, _T_2519) @[package.scala 49:27] + node _T_2527 = and(_T_2516, _T_2526) @[package.scala 50:38] + node _T_2528 = or(_T_2515, _T_2527) @[package.scala 50:29] + node _T_2529 = and(_T_2513, _T_2517) @[package.scala 49:27] + node _T_2530 = and(_T_2516, _T_2529) @[package.scala 50:38] + node _T_2531 = or(_T_2515, _T_2530) @[package.scala 50:29] + node _T_2532 = bits(_T_2502, 0, 0) @[package.scala 44:26] + node _T_2533 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2535 = eq(_T_2533, UInt<1>("h00")) @[package.scala 46:20] + node _T_2536 = and(_T_2520, _T_2535) @[package.scala 49:27] + node _T_2537 = and(_T_2532, _T_2536) @[package.scala 50:38] + node _T_2538 = or(_T_2522, _T_2537) @[package.scala 50:29] + node _T_2539 = and(_T_2520, _T_2533) @[package.scala 49:27] + node _T_2540 = and(_T_2532, _T_2539) @[package.scala 50:38] + node _T_2541 = or(_T_2522, _T_2540) @[package.scala 50:29] + node _T_2542 = and(_T_2523, _T_2535) @[package.scala 49:27] + node _T_2543 = and(_T_2532, _T_2542) @[package.scala 50:38] + node _T_2544 = or(_T_2525, _T_2543) @[package.scala 50:29] + node _T_2545 = and(_T_2523, _T_2533) @[package.scala 49:27] + node _T_2546 = and(_T_2532, _T_2545) @[package.scala 50:38] + node _T_2547 = or(_T_2525, _T_2546) @[package.scala 50:29] + node _T_2548 = and(_T_2526, _T_2535) @[package.scala 49:27] + node _T_2549 = and(_T_2532, _T_2548) @[package.scala 50:38] + node _T_2550 = or(_T_2528, _T_2549) @[package.scala 50:29] + node _T_2551 = and(_T_2526, _T_2533) @[package.scala 49:27] + node _T_2552 = and(_T_2532, _T_2551) @[package.scala 50:38] + node _T_2553 = or(_T_2528, _T_2552) @[package.scala 50:29] + node _T_2554 = and(_T_2529, _T_2535) @[package.scala 49:27] + node _T_2555 = and(_T_2532, _T_2554) @[package.scala 50:38] + node _T_2556 = or(_T_2531, _T_2555) @[package.scala 50:29] + node _T_2557 = and(_T_2529, _T_2533) @[package.scala 49:27] + node _T_2558 = and(_T_2532, _T_2557) @[package.scala 50:38] + node _T_2559 = or(_T_2531, _T_2558) @[package.scala 50:29] + node _T_2560 = cat(_T_2541, _T_2538) @[Cat.scala 30:58] + node _T_2561 = cat(_T_2547, _T_2544) @[Cat.scala 30:58] + node _T_2562 = cat(_T_2561, _T_2560) @[Cat.scala 30:58] + node _T_2563 = cat(_T_2553, _T_2550) @[Cat.scala 30:58] + node _T_2564 = cat(_T_2559, _T_2556) @[Cat.scala 30:58] + node _T_2565 = cat(_T_2564, _T_2563) @[Cat.scala 30:58] + node _T_2566 = cat(_T_2565, _T_2562) @[Cat.scala 30:58] + _T_2490.mask <= _T_2566 @[Edges.scala 404:15] + _T_2490.data <= a_data @[Edges.scala 405:15] + node _T_2571 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2573 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_2574 = and(_T_2571, _T_2573) @[Parameters.scala 63:37] + node _T_2575 = or(UInt<1>("h00"), _T_2574) @[Parameters.scala 132:31] + node _T_2577 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2578 = cvt(_T_2577) @[Parameters.scala 117:49] + node _T_2580 = and(_T_2578, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2581 = asSInt(_T_2580) @[Parameters.scala 117:52] + node _T_2583 = eq(_T_2581, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2585 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2586 = cvt(_T_2585) @[Parameters.scala 117:49] + node _T_2588 = and(_T_2586, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_2589 = asSInt(_T_2588) @[Parameters.scala 117:52] + node _T_2591 = eq(_T_2589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2593 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2594 = cvt(_T_2593) @[Parameters.scala 117:49] + node _T_2596 = and(_T_2594, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_2597 = asSInt(_T_2596) @[Parameters.scala 117:52] + node _T_2599 = eq(_T_2597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2600 = or(_T_2583, _T_2591) @[Parameters.scala 133:42] + node _T_2601 = or(_T_2600, _T_2599) @[Parameters.scala 133:42] + node _T_2602 = and(_T_2575, _T_2601) @[Parameters.scala 132:56] + node _T_2605 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2607 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2608 = cvt(_T_2607) @[Parameters.scala 117:49] + node _T_2610 = and(_T_2608, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2611 = asSInt(_T_2610) @[Parameters.scala 117:52] + node _T_2613 = eq(_T_2611, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2615 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2616 = cvt(_T_2615) @[Parameters.scala 117:49] + node _T_2618 = and(_T_2616, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_2619 = asSInt(_T_2618) @[Parameters.scala 117:52] + node _T_2621 = eq(_T_2619, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2623 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2624 = cvt(_T_2623) @[Parameters.scala 117:49] + node _T_2626 = and(_T_2624, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2627 = asSInt(_T_2626) @[Parameters.scala 117:52] + node _T_2629 = eq(_T_2627, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2631 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2632 = cvt(_T_2631) @[Parameters.scala 117:49] + node _T_2634 = and(_T_2632, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2635 = asSInt(_T_2634) @[Parameters.scala 117:52] + node _T_2637 = eq(_T_2635, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2638 = or(_T_2613, _T_2621) @[Parameters.scala 133:42] + node _T_2639 = or(_T_2638, _T_2629) @[Parameters.scala 133:42] + node _T_2640 = or(_T_2639, _T_2637) @[Parameters.scala 133:42] + node _T_2641 = and(_T_2605, _T_2640) @[Parameters.scala 132:56] + node _T_2643 = or(UInt<1>("h00"), _T_2602) @[Parameters.scala 134:30] + node _T_2644 = or(_T_2643, _T_2641) @[Parameters.scala 134:30] + wire _T_2653 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 398:17] + _T_2653 is invalid @[Edges.scala 398:17] + _T_2653.opcode <= UInt<2>("h03") @[Edges.scala 399:15] + _T_2653.param <= UInt<3>("h01") @[Edges.scala 400:15] + _T_2653.size <= a_size @[Edges.scala 401:15] + _T_2653.source <= UInt<1>("h00") @[Edges.scala 402:15] + _T_2653.address <= s2_req.addr @[Edges.scala 403:15] + node _T_2663 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2664 = dshl(UInt<1>("h01"), _T_2663) @[OneHot.scala 49:12] + node _T_2665 = bits(_T_2664, 2, 0) @[OneHot.scala 49:37] + node _T_2667 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2669 = bits(_T_2665, 2, 2) @[package.scala 44:26] + node _T_2670 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2672 = eq(_T_2670, UInt<1>("h00")) @[package.scala 46:20] + node _T_2673 = and(UInt<1>("h01"), _T_2672) @[package.scala 49:27] + node _T_2674 = and(_T_2669, _T_2673) @[package.scala 50:38] + node _T_2675 = or(_T_2667, _T_2674) @[package.scala 50:29] + node _T_2676 = and(UInt<1>("h01"), _T_2670) @[package.scala 49:27] + node _T_2677 = and(_T_2669, _T_2676) @[package.scala 50:38] + node _T_2678 = or(_T_2667, _T_2677) @[package.scala 50:29] + node _T_2679 = bits(_T_2665, 1, 1) @[package.scala 44:26] + node _T_2680 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2682 = eq(_T_2680, UInt<1>("h00")) @[package.scala 46:20] + node _T_2683 = and(_T_2673, _T_2682) @[package.scala 49:27] + node _T_2684 = and(_T_2679, _T_2683) @[package.scala 50:38] + node _T_2685 = or(_T_2675, _T_2684) @[package.scala 50:29] + node _T_2686 = and(_T_2673, _T_2680) @[package.scala 49:27] + node _T_2687 = and(_T_2679, _T_2686) @[package.scala 50:38] + node _T_2688 = or(_T_2675, _T_2687) @[package.scala 50:29] + node _T_2689 = and(_T_2676, _T_2682) @[package.scala 49:27] + node _T_2690 = and(_T_2679, _T_2689) @[package.scala 50:38] + node _T_2691 = or(_T_2678, _T_2690) @[package.scala 50:29] + node _T_2692 = and(_T_2676, _T_2680) @[package.scala 49:27] + node _T_2693 = and(_T_2679, _T_2692) @[package.scala 50:38] + node _T_2694 = or(_T_2678, _T_2693) @[package.scala 50:29] + node _T_2695 = bits(_T_2665, 0, 0) @[package.scala 44:26] + node _T_2696 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2698 = eq(_T_2696, UInt<1>("h00")) @[package.scala 46:20] + node _T_2699 = and(_T_2683, _T_2698) @[package.scala 49:27] + node _T_2700 = and(_T_2695, _T_2699) @[package.scala 50:38] + node _T_2701 = or(_T_2685, _T_2700) @[package.scala 50:29] + node _T_2702 = and(_T_2683, _T_2696) @[package.scala 49:27] + node _T_2703 = and(_T_2695, _T_2702) @[package.scala 50:38] + node _T_2704 = or(_T_2685, _T_2703) @[package.scala 50:29] + node _T_2705 = and(_T_2686, _T_2698) @[package.scala 49:27] + node _T_2706 = and(_T_2695, _T_2705) @[package.scala 50:38] + node _T_2707 = or(_T_2688, _T_2706) @[package.scala 50:29] + node _T_2708 = and(_T_2686, _T_2696) @[package.scala 49:27] + node _T_2709 = and(_T_2695, _T_2708) @[package.scala 50:38] + node _T_2710 = or(_T_2688, _T_2709) @[package.scala 50:29] + node _T_2711 = and(_T_2689, _T_2698) @[package.scala 49:27] + node _T_2712 = and(_T_2695, _T_2711) @[package.scala 50:38] + node _T_2713 = or(_T_2691, _T_2712) @[package.scala 50:29] + node _T_2714 = and(_T_2689, _T_2696) @[package.scala 49:27] + node _T_2715 = and(_T_2695, _T_2714) @[package.scala 50:38] + node _T_2716 = or(_T_2691, _T_2715) @[package.scala 50:29] + node _T_2717 = and(_T_2692, _T_2698) @[package.scala 49:27] + node _T_2718 = and(_T_2695, _T_2717) @[package.scala 50:38] + node _T_2719 = or(_T_2694, _T_2718) @[package.scala 50:29] + node _T_2720 = and(_T_2692, _T_2696) @[package.scala 49:27] + node _T_2721 = and(_T_2695, _T_2720) @[package.scala 50:38] + node _T_2722 = or(_T_2694, _T_2721) @[package.scala 50:29] + node _T_2723 = cat(_T_2704, _T_2701) @[Cat.scala 30:58] + node _T_2724 = cat(_T_2710, _T_2707) @[Cat.scala 30:58] + node _T_2725 = cat(_T_2724, _T_2723) @[Cat.scala 30:58] + node _T_2726 = cat(_T_2716, _T_2713) @[Cat.scala 30:58] + node _T_2727 = cat(_T_2722, _T_2719) @[Cat.scala 30:58] + node _T_2728 = cat(_T_2727, _T_2726) @[Cat.scala 30:58] + node _T_2729 = cat(_T_2728, _T_2725) @[Cat.scala 30:58] + _T_2653.mask <= _T_2729 @[Edges.scala 404:15] + _T_2653.data <= a_data @[Edges.scala 405:15] + node _T_2734 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2736 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_2737 = and(_T_2734, _T_2736) @[Parameters.scala 63:37] + node _T_2738 = or(UInt<1>("h00"), _T_2737) @[Parameters.scala 132:31] + node _T_2740 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2741 = cvt(_T_2740) @[Parameters.scala 117:49] + node _T_2743 = and(_T_2741, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2744 = asSInt(_T_2743) @[Parameters.scala 117:52] + node _T_2746 = eq(_T_2744, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2748 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2749 = cvt(_T_2748) @[Parameters.scala 117:49] + node _T_2751 = and(_T_2749, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_2752 = asSInt(_T_2751) @[Parameters.scala 117:52] + node _T_2754 = eq(_T_2752, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2756 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2757 = cvt(_T_2756) @[Parameters.scala 117:49] + node _T_2759 = and(_T_2757, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_2760 = asSInt(_T_2759) @[Parameters.scala 117:52] + node _T_2762 = eq(_T_2760, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2763 = or(_T_2746, _T_2754) @[Parameters.scala 133:42] + node _T_2764 = or(_T_2763, _T_2762) @[Parameters.scala 133:42] + node _T_2765 = and(_T_2738, _T_2764) @[Parameters.scala 132:56] + node _T_2768 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2770 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2771 = cvt(_T_2770) @[Parameters.scala 117:49] + node _T_2773 = and(_T_2771, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2774 = asSInt(_T_2773) @[Parameters.scala 117:52] + node _T_2776 = eq(_T_2774, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2778 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2779 = cvt(_T_2778) @[Parameters.scala 117:49] + node _T_2781 = and(_T_2779, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_2782 = asSInt(_T_2781) @[Parameters.scala 117:52] + node _T_2784 = eq(_T_2782, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2786 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2787 = cvt(_T_2786) @[Parameters.scala 117:49] + node _T_2789 = and(_T_2787, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2790 = asSInt(_T_2789) @[Parameters.scala 117:52] + node _T_2792 = eq(_T_2790, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2794 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2795 = cvt(_T_2794) @[Parameters.scala 117:49] + node _T_2797 = and(_T_2795, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2798 = asSInt(_T_2797) @[Parameters.scala 117:52] + node _T_2800 = eq(_T_2798, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2801 = or(_T_2776, _T_2784) @[Parameters.scala 133:42] + node _T_2802 = or(_T_2801, _T_2792) @[Parameters.scala 133:42] + node _T_2803 = or(_T_2802, _T_2800) @[Parameters.scala 133:42] + node _T_2804 = and(_T_2768, _T_2803) @[Parameters.scala 132:56] + node _T_2806 = or(UInt<1>("h00"), _T_2765) @[Parameters.scala 134:30] + node _T_2807 = or(_T_2806, _T_2804) @[Parameters.scala 134:30] + wire _T_2816 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 398:17] + _T_2816 is invalid @[Edges.scala 398:17] + _T_2816.opcode <= UInt<2>("h03") @[Edges.scala 399:15] + _T_2816.param <= UInt<3>("h02") @[Edges.scala 400:15] + _T_2816.size <= a_size @[Edges.scala 401:15] + _T_2816.source <= UInt<1>("h00") @[Edges.scala 402:15] + _T_2816.address <= s2_req.addr @[Edges.scala 403:15] + node _T_2826 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2827 = dshl(UInt<1>("h01"), _T_2826) @[OneHot.scala 49:12] + node _T_2828 = bits(_T_2827, 2, 0) @[OneHot.scala 49:37] + node _T_2830 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2832 = bits(_T_2828, 2, 2) @[package.scala 44:26] + node _T_2833 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2835 = eq(_T_2833, UInt<1>("h00")) @[package.scala 46:20] + node _T_2836 = and(UInt<1>("h01"), _T_2835) @[package.scala 49:27] + node _T_2837 = and(_T_2832, _T_2836) @[package.scala 50:38] + node _T_2838 = or(_T_2830, _T_2837) @[package.scala 50:29] + node _T_2839 = and(UInt<1>("h01"), _T_2833) @[package.scala 49:27] + node _T_2840 = and(_T_2832, _T_2839) @[package.scala 50:38] + node _T_2841 = or(_T_2830, _T_2840) @[package.scala 50:29] + node _T_2842 = bits(_T_2828, 1, 1) @[package.scala 44:26] + node _T_2843 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_2845 = eq(_T_2843, UInt<1>("h00")) @[package.scala 46:20] + node _T_2846 = and(_T_2836, _T_2845) @[package.scala 49:27] + node _T_2847 = and(_T_2842, _T_2846) @[package.scala 50:38] + node _T_2848 = or(_T_2838, _T_2847) @[package.scala 50:29] + node _T_2849 = and(_T_2836, _T_2843) @[package.scala 49:27] + node _T_2850 = and(_T_2842, _T_2849) @[package.scala 50:38] + node _T_2851 = or(_T_2838, _T_2850) @[package.scala 50:29] + node _T_2852 = and(_T_2839, _T_2845) @[package.scala 49:27] + node _T_2853 = and(_T_2842, _T_2852) @[package.scala 50:38] + node _T_2854 = or(_T_2841, _T_2853) @[package.scala 50:29] + node _T_2855 = and(_T_2839, _T_2843) @[package.scala 49:27] + node _T_2856 = and(_T_2842, _T_2855) @[package.scala 50:38] + node _T_2857 = or(_T_2841, _T_2856) @[package.scala 50:29] + node _T_2858 = bits(_T_2828, 0, 0) @[package.scala 44:26] + node _T_2859 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_2861 = eq(_T_2859, UInt<1>("h00")) @[package.scala 46:20] + node _T_2862 = and(_T_2846, _T_2861) @[package.scala 49:27] + node _T_2863 = and(_T_2858, _T_2862) @[package.scala 50:38] + node _T_2864 = or(_T_2848, _T_2863) @[package.scala 50:29] + node _T_2865 = and(_T_2846, _T_2859) @[package.scala 49:27] + node _T_2866 = and(_T_2858, _T_2865) @[package.scala 50:38] + node _T_2867 = or(_T_2848, _T_2866) @[package.scala 50:29] + node _T_2868 = and(_T_2849, _T_2861) @[package.scala 49:27] + node _T_2869 = and(_T_2858, _T_2868) @[package.scala 50:38] + node _T_2870 = or(_T_2851, _T_2869) @[package.scala 50:29] + node _T_2871 = and(_T_2849, _T_2859) @[package.scala 49:27] + node _T_2872 = and(_T_2858, _T_2871) @[package.scala 50:38] + node _T_2873 = or(_T_2851, _T_2872) @[package.scala 50:29] + node _T_2874 = and(_T_2852, _T_2861) @[package.scala 49:27] + node _T_2875 = and(_T_2858, _T_2874) @[package.scala 50:38] + node _T_2876 = or(_T_2854, _T_2875) @[package.scala 50:29] + node _T_2877 = and(_T_2852, _T_2859) @[package.scala 49:27] + node _T_2878 = and(_T_2858, _T_2877) @[package.scala 50:38] + node _T_2879 = or(_T_2854, _T_2878) @[package.scala 50:29] + node _T_2880 = and(_T_2855, _T_2861) @[package.scala 49:27] + node _T_2881 = and(_T_2858, _T_2880) @[package.scala 50:38] + node _T_2882 = or(_T_2857, _T_2881) @[package.scala 50:29] + node _T_2883 = and(_T_2855, _T_2859) @[package.scala 49:27] + node _T_2884 = and(_T_2858, _T_2883) @[package.scala 50:38] + node _T_2885 = or(_T_2857, _T_2884) @[package.scala 50:29] + node _T_2886 = cat(_T_2867, _T_2864) @[Cat.scala 30:58] + node _T_2887 = cat(_T_2873, _T_2870) @[Cat.scala 30:58] + node _T_2888 = cat(_T_2887, _T_2886) @[Cat.scala 30:58] + node _T_2889 = cat(_T_2879, _T_2876) @[Cat.scala 30:58] + node _T_2890 = cat(_T_2885, _T_2882) @[Cat.scala 30:58] + node _T_2891 = cat(_T_2890, _T_2889) @[Cat.scala 30:58] + node _T_2892 = cat(_T_2891, _T_2888) @[Cat.scala 30:58] + _T_2816.mask <= _T_2892 @[Edges.scala 404:15] + _T_2816.data <= a_data @[Edges.scala 405:15] + node _T_2897 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_2899 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_2900 = and(_T_2897, _T_2899) @[Parameters.scala 63:37] + node _T_2901 = or(UInt<1>("h00"), _T_2900) @[Parameters.scala 132:31] + node _T_2903 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2904 = cvt(_T_2903) @[Parameters.scala 117:49] + node _T_2906 = and(_T_2904, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2907 = asSInt(_T_2906) @[Parameters.scala 117:52] + node _T_2909 = eq(_T_2907, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2911 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2912 = cvt(_T_2911) @[Parameters.scala 117:49] + node _T_2914 = and(_T_2912, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_2915 = asSInt(_T_2914) @[Parameters.scala 117:52] + node _T_2917 = eq(_T_2915, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2919 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2920 = cvt(_T_2919) @[Parameters.scala 117:49] + node _T_2922 = and(_T_2920, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_2923 = asSInt(_T_2922) @[Parameters.scala 117:52] + node _T_2925 = eq(_T_2923, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2926 = or(_T_2909, _T_2917) @[Parameters.scala 133:42] + node _T_2927 = or(_T_2926, _T_2925) @[Parameters.scala 133:42] + node _T_2928 = and(_T_2901, _T_2927) @[Parameters.scala 132:56] + node _T_2931 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2933 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2934 = cvt(_T_2933) @[Parameters.scala 117:49] + node _T_2936 = and(_T_2934, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_2937 = asSInt(_T_2936) @[Parameters.scala 117:52] + node _T_2939 = eq(_T_2937, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2941 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2942 = cvt(_T_2941) @[Parameters.scala 117:49] + node _T_2944 = and(_T_2942, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_2945 = asSInt(_T_2944) @[Parameters.scala 117:52] + node _T_2947 = eq(_T_2945, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2949 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2950 = cvt(_T_2949) @[Parameters.scala 117:49] + node _T_2952 = and(_T_2950, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_2953 = asSInt(_T_2952) @[Parameters.scala 117:52] + node _T_2955 = eq(_T_2953, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2957 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2958 = cvt(_T_2957) @[Parameters.scala 117:49] + node _T_2960 = and(_T_2958, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_2961 = asSInt(_T_2960) @[Parameters.scala 117:52] + node _T_2963 = eq(_T_2961, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2964 = or(_T_2939, _T_2947) @[Parameters.scala 133:42] + node _T_2965 = or(_T_2964, _T_2955) @[Parameters.scala 133:42] + node _T_2966 = or(_T_2965, _T_2963) @[Parameters.scala 133:42] + node _T_2967 = and(_T_2931, _T_2966) @[Parameters.scala 132:56] + node _T_2969 = or(UInt<1>("h00"), _T_2928) @[Parameters.scala 134:30] + node _T_2970 = or(_T_2969, _T_2967) @[Parameters.scala 134:30] + wire _T_2979 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 384:17] + _T_2979 is invalid @[Edges.scala 384:17] + _T_2979.opcode <= UInt<2>("h02") @[Edges.scala 385:15] + _T_2979.param <= UInt<3>("h04") @[Edges.scala 386:15] + _T_2979.size <= a_size @[Edges.scala 387:15] + _T_2979.source <= UInt<1>("h00") @[Edges.scala 388:15] + _T_2979.address <= s2_req.addr @[Edges.scala 389:15] + node _T_2989 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_2990 = dshl(UInt<1>("h01"), _T_2989) @[OneHot.scala 49:12] + node _T_2991 = bits(_T_2990, 2, 0) @[OneHot.scala 49:37] + node _T_2993 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2995 = bits(_T_2991, 2, 2) @[package.scala 44:26] + node _T_2996 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_2998 = eq(_T_2996, UInt<1>("h00")) @[package.scala 46:20] + node _T_2999 = and(UInt<1>("h01"), _T_2998) @[package.scala 49:27] + node _T_3000 = and(_T_2995, _T_2999) @[package.scala 50:38] + node _T_3001 = or(_T_2993, _T_3000) @[package.scala 50:29] + node _T_3002 = and(UInt<1>("h01"), _T_2996) @[package.scala 49:27] + node _T_3003 = and(_T_2995, _T_3002) @[package.scala 50:38] + node _T_3004 = or(_T_2993, _T_3003) @[package.scala 50:29] + node _T_3005 = bits(_T_2991, 1, 1) @[package.scala 44:26] + node _T_3006 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_3008 = eq(_T_3006, UInt<1>("h00")) @[package.scala 46:20] + node _T_3009 = and(_T_2999, _T_3008) @[package.scala 49:27] + node _T_3010 = and(_T_3005, _T_3009) @[package.scala 50:38] + node _T_3011 = or(_T_3001, _T_3010) @[package.scala 50:29] + node _T_3012 = and(_T_2999, _T_3006) @[package.scala 49:27] + node _T_3013 = and(_T_3005, _T_3012) @[package.scala 50:38] + node _T_3014 = or(_T_3001, _T_3013) @[package.scala 50:29] + node _T_3015 = and(_T_3002, _T_3008) @[package.scala 49:27] + node _T_3016 = and(_T_3005, _T_3015) @[package.scala 50:38] + node _T_3017 = or(_T_3004, _T_3016) @[package.scala 50:29] + node _T_3018 = and(_T_3002, _T_3006) @[package.scala 49:27] + node _T_3019 = and(_T_3005, _T_3018) @[package.scala 50:38] + node _T_3020 = or(_T_3004, _T_3019) @[package.scala 50:29] + node _T_3021 = bits(_T_2991, 0, 0) @[package.scala 44:26] + node _T_3022 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_3024 = eq(_T_3022, UInt<1>("h00")) @[package.scala 46:20] + node _T_3025 = and(_T_3009, _T_3024) @[package.scala 49:27] + node _T_3026 = and(_T_3021, _T_3025) @[package.scala 50:38] + node _T_3027 = or(_T_3011, _T_3026) @[package.scala 50:29] + node _T_3028 = and(_T_3009, _T_3022) @[package.scala 49:27] + node _T_3029 = and(_T_3021, _T_3028) @[package.scala 50:38] + node _T_3030 = or(_T_3011, _T_3029) @[package.scala 50:29] + node _T_3031 = and(_T_3012, _T_3024) @[package.scala 49:27] + node _T_3032 = and(_T_3021, _T_3031) @[package.scala 50:38] + node _T_3033 = or(_T_3014, _T_3032) @[package.scala 50:29] + node _T_3034 = and(_T_3012, _T_3022) @[package.scala 49:27] + node _T_3035 = and(_T_3021, _T_3034) @[package.scala 50:38] + node _T_3036 = or(_T_3014, _T_3035) @[package.scala 50:29] + node _T_3037 = and(_T_3015, _T_3024) @[package.scala 49:27] + node _T_3038 = and(_T_3021, _T_3037) @[package.scala 50:38] + node _T_3039 = or(_T_3017, _T_3038) @[package.scala 50:29] + node _T_3040 = and(_T_3015, _T_3022) @[package.scala 49:27] + node _T_3041 = and(_T_3021, _T_3040) @[package.scala 50:38] + node _T_3042 = or(_T_3017, _T_3041) @[package.scala 50:29] + node _T_3043 = and(_T_3018, _T_3024) @[package.scala 49:27] + node _T_3044 = and(_T_3021, _T_3043) @[package.scala 50:38] + node _T_3045 = or(_T_3020, _T_3044) @[package.scala 50:29] + node _T_3046 = and(_T_3018, _T_3022) @[package.scala 49:27] + node _T_3047 = and(_T_3021, _T_3046) @[package.scala 50:38] + node _T_3048 = or(_T_3020, _T_3047) @[package.scala 50:29] + node _T_3049 = cat(_T_3030, _T_3027) @[Cat.scala 30:58] + node _T_3050 = cat(_T_3036, _T_3033) @[Cat.scala 30:58] + node _T_3051 = cat(_T_3050, _T_3049) @[Cat.scala 30:58] + node _T_3052 = cat(_T_3042, _T_3039) @[Cat.scala 30:58] + node _T_3053 = cat(_T_3048, _T_3045) @[Cat.scala 30:58] + node _T_3054 = cat(_T_3053, _T_3052) @[Cat.scala 30:58] + node _T_3055 = cat(_T_3054, _T_3051) @[Cat.scala 30:58] + _T_2979.mask <= _T_3055 @[Edges.scala 390:15] + _T_2979.data <= a_data @[Edges.scala 391:15] + node _T_3060 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_3062 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3063 = and(_T_3060, _T_3062) @[Parameters.scala 63:37] + node _T_3064 = or(UInt<1>("h00"), _T_3063) @[Parameters.scala 132:31] + node _T_3066 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3067 = cvt(_T_3066) @[Parameters.scala 117:49] + node _T_3069 = and(_T_3067, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3070 = asSInt(_T_3069) @[Parameters.scala 117:52] + node _T_3072 = eq(_T_3070, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3074 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3075 = cvt(_T_3074) @[Parameters.scala 117:49] + node _T_3077 = and(_T_3075, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_3078 = asSInt(_T_3077) @[Parameters.scala 117:52] + node _T_3080 = eq(_T_3078, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3082 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3083 = cvt(_T_3082) @[Parameters.scala 117:49] + node _T_3085 = and(_T_3083, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_3086 = asSInt(_T_3085) @[Parameters.scala 117:52] + node _T_3088 = eq(_T_3086, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3089 = or(_T_3072, _T_3080) @[Parameters.scala 133:42] + node _T_3090 = or(_T_3089, _T_3088) @[Parameters.scala 133:42] + node _T_3091 = and(_T_3064, _T_3090) @[Parameters.scala 132:56] + node _T_3094 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3096 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3097 = cvt(_T_3096) @[Parameters.scala 117:49] + node _T_3099 = and(_T_3097, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3100 = asSInt(_T_3099) @[Parameters.scala 117:52] + node _T_3102 = eq(_T_3100, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3104 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3105 = cvt(_T_3104) @[Parameters.scala 117:49] + node _T_3107 = and(_T_3105, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_3108 = asSInt(_T_3107) @[Parameters.scala 117:52] + node _T_3110 = eq(_T_3108, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3112 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3113 = cvt(_T_3112) @[Parameters.scala 117:49] + node _T_3115 = and(_T_3113, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_3116 = asSInt(_T_3115) @[Parameters.scala 117:52] + node _T_3118 = eq(_T_3116, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3120 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3121 = cvt(_T_3120) @[Parameters.scala 117:49] + node _T_3123 = and(_T_3121, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_3124 = asSInt(_T_3123) @[Parameters.scala 117:52] + node _T_3126 = eq(_T_3124, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3127 = or(_T_3102, _T_3110) @[Parameters.scala 133:42] + node _T_3128 = or(_T_3127, _T_3118) @[Parameters.scala 133:42] + node _T_3129 = or(_T_3128, _T_3126) @[Parameters.scala 133:42] + node _T_3130 = and(_T_3094, _T_3129) @[Parameters.scala 132:56] + node _T_3132 = or(UInt<1>("h00"), _T_3091) @[Parameters.scala 134:30] + node _T_3133 = or(_T_3132, _T_3130) @[Parameters.scala 134:30] + wire _T_3142 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 384:17] + _T_3142 is invalid @[Edges.scala 384:17] + _T_3142.opcode <= UInt<2>("h02") @[Edges.scala 385:15] + _T_3142.param <= UInt<3>("h00") @[Edges.scala 386:15] + _T_3142.size <= a_size @[Edges.scala 387:15] + _T_3142.source <= UInt<1>("h00") @[Edges.scala 388:15] + _T_3142.address <= s2_req.addr @[Edges.scala 389:15] + node _T_3152 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_3153 = dshl(UInt<1>("h01"), _T_3152) @[OneHot.scala 49:12] + node _T_3154 = bits(_T_3153, 2, 0) @[OneHot.scala 49:37] + node _T_3156 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3158 = bits(_T_3154, 2, 2) @[package.scala 44:26] + node _T_3159 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_3161 = eq(_T_3159, UInt<1>("h00")) @[package.scala 46:20] + node _T_3162 = and(UInt<1>("h01"), _T_3161) @[package.scala 49:27] + node _T_3163 = and(_T_3158, _T_3162) @[package.scala 50:38] + node _T_3164 = or(_T_3156, _T_3163) @[package.scala 50:29] + node _T_3165 = and(UInt<1>("h01"), _T_3159) @[package.scala 49:27] + node _T_3166 = and(_T_3158, _T_3165) @[package.scala 50:38] + node _T_3167 = or(_T_3156, _T_3166) @[package.scala 50:29] + node _T_3168 = bits(_T_3154, 1, 1) @[package.scala 44:26] + node _T_3169 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_3171 = eq(_T_3169, UInt<1>("h00")) @[package.scala 46:20] + node _T_3172 = and(_T_3162, _T_3171) @[package.scala 49:27] + node _T_3173 = and(_T_3168, _T_3172) @[package.scala 50:38] + node _T_3174 = or(_T_3164, _T_3173) @[package.scala 50:29] + node _T_3175 = and(_T_3162, _T_3169) @[package.scala 49:27] + node _T_3176 = and(_T_3168, _T_3175) @[package.scala 50:38] + node _T_3177 = or(_T_3164, _T_3176) @[package.scala 50:29] + node _T_3178 = and(_T_3165, _T_3171) @[package.scala 49:27] + node _T_3179 = and(_T_3168, _T_3178) @[package.scala 50:38] + node _T_3180 = or(_T_3167, _T_3179) @[package.scala 50:29] + node _T_3181 = and(_T_3165, _T_3169) @[package.scala 49:27] + node _T_3182 = and(_T_3168, _T_3181) @[package.scala 50:38] + node _T_3183 = or(_T_3167, _T_3182) @[package.scala 50:29] + node _T_3184 = bits(_T_3154, 0, 0) @[package.scala 44:26] + node _T_3185 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_3187 = eq(_T_3185, UInt<1>("h00")) @[package.scala 46:20] + node _T_3188 = and(_T_3172, _T_3187) @[package.scala 49:27] + node _T_3189 = and(_T_3184, _T_3188) @[package.scala 50:38] + node _T_3190 = or(_T_3174, _T_3189) @[package.scala 50:29] + node _T_3191 = and(_T_3172, _T_3185) @[package.scala 49:27] + node _T_3192 = and(_T_3184, _T_3191) @[package.scala 50:38] + node _T_3193 = or(_T_3174, _T_3192) @[package.scala 50:29] + node _T_3194 = and(_T_3175, _T_3187) @[package.scala 49:27] + node _T_3195 = and(_T_3184, _T_3194) @[package.scala 50:38] + node _T_3196 = or(_T_3177, _T_3195) @[package.scala 50:29] + node _T_3197 = and(_T_3175, _T_3185) @[package.scala 49:27] + node _T_3198 = and(_T_3184, _T_3197) @[package.scala 50:38] + node _T_3199 = or(_T_3177, _T_3198) @[package.scala 50:29] + node _T_3200 = and(_T_3178, _T_3187) @[package.scala 49:27] + node _T_3201 = and(_T_3184, _T_3200) @[package.scala 50:38] + node _T_3202 = or(_T_3180, _T_3201) @[package.scala 50:29] + node _T_3203 = and(_T_3178, _T_3185) @[package.scala 49:27] + node _T_3204 = and(_T_3184, _T_3203) @[package.scala 50:38] + node _T_3205 = or(_T_3180, _T_3204) @[package.scala 50:29] + node _T_3206 = and(_T_3181, _T_3187) @[package.scala 49:27] + node _T_3207 = and(_T_3184, _T_3206) @[package.scala 50:38] + node _T_3208 = or(_T_3183, _T_3207) @[package.scala 50:29] + node _T_3209 = and(_T_3181, _T_3185) @[package.scala 49:27] + node _T_3210 = and(_T_3184, _T_3209) @[package.scala 50:38] + node _T_3211 = or(_T_3183, _T_3210) @[package.scala 50:29] + node _T_3212 = cat(_T_3193, _T_3190) @[Cat.scala 30:58] + node _T_3213 = cat(_T_3199, _T_3196) @[Cat.scala 30:58] + node _T_3214 = cat(_T_3213, _T_3212) @[Cat.scala 30:58] + node _T_3215 = cat(_T_3205, _T_3202) @[Cat.scala 30:58] + node _T_3216 = cat(_T_3211, _T_3208) @[Cat.scala 30:58] + node _T_3217 = cat(_T_3216, _T_3215) @[Cat.scala 30:58] + node _T_3218 = cat(_T_3217, _T_3214) @[Cat.scala 30:58] + _T_3142.mask <= _T_3218 @[Edges.scala 390:15] + _T_3142.data <= a_data @[Edges.scala 391:15] + node _T_3223 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_3225 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3226 = and(_T_3223, _T_3225) @[Parameters.scala 63:37] + node _T_3227 = or(UInt<1>("h00"), _T_3226) @[Parameters.scala 132:31] + node _T_3229 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3230 = cvt(_T_3229) @[Parameters.scala 117:49] + node _T_3232 = and(_T_3230, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3233 = asSInt(_T_3232) @[Parameters.scala 117:52] + node _T_3235 = eq(_T_3233, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3237 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3238 = cvt(_T_3237) @[Parameters.scala 117:49] + node _T_3240 = and(_T_3238, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_3241 = asSInt(_T_3240) @[Parameters.scala 117:52] + node _T_3243 = eq(_T_3241, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3245 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3246 = cvt(_T_3245) @[Parameters.scala 117:49] + node _T_3248 = and(_T_3246, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_3249 = asSInt(_T_3248) @[Parameters.scala 117:52] + node _T_3251 = eq(_T_3249, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3252 = or(_T_3235, _T_3243) @[Parameters.scala 133:42] + node _T_3253 = or(_T_3252, _T_3251) @[Parameters.scala 133:42] + node _T_3254 = and(_T_3227, _T_3253) @[Parameters.scala 132:56] + node _T_3257 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3259 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3260 = cvt(_T_3259) @[Parameters.scala 117:49] + node _T_3262 = and(_T_3260, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3263 = asSInt(_T_3262) @[Parameters.scala 117:52] + node _T_3265 = eq(_T_3263, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3267 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3268 = cvt(_T_3267) @[Parameters.scala 117:49] + node _T_3270 = and(_T_3268, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_3271 = asSInt(_T_3270) @[Parameters.scala 117:52] + node _T_3273 = eq(_T_3271, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3275 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3276 = cvt(_T_3275) @[Parameters.scala 117:49] + node _T_3278 = and(_T_3276, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_3279 = asSInt(_T_3278) @[Parameters.scala 117:52] + node _T_3281 = eq(_T_3279, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3283 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3284 = cvt(_T_3283) @[Parameters.scala 117:49] + node _T_3286 = and(_T_3284, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_3287 = asSInt(_T_3286) @[Parameters.scala 117:52] + node _T_3289 = eq(_T_3287, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3290 = or(_T_3265, _T_3273) @[Parameters.scala 133:42] + node _T_3291 = or(_T_3290, _T_3281) @[Parameters.scala 133:42] + node _T_3292 = or(_T_3291, _T_3289) @[Parameters.scala 133:42] + node _T_3293 = and(_T_3257, _T_3292) @[Parameters.scala 132:56] + node _T_3295 = or(UInt<1>("h00"), _T_3254) @[Parameters.scala 134:30] + node _T_3296 = or(_T_3295, _T_3293) @[Parameters.scala 134:30] + wire _T_3305 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 384:17] + _T_3305 is invalid @[Edges.scala 384:17] + _T_3305.opcode <= UInt<2>("h02") @[Edges.scala 385:15] + _T_3305.param <= UInt<3>("h01") @[Edges.scala 386:15] + _T_3305.size <= a_size @[Edges.scala 387:15] + _T_3305.source <= UInt<1>("h00") @[Edges.scala 388:15] + _T_3305.address <= s2_req.addr @[Edges.scala 389:15] + node _T_3315 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_3316 = dshl(UInt<1>("h01"), _T_3315) @[OneHot.scala 49:12] + node _T_3317 = bits(_T_3316, 2, 0) @[OneHot.scala 49:37] + node _T_3319 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3321 = bits(_T_3317, 2, 2) @[package.scala 44:26] + node _T_3322 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_3324 = eq(_T_3322, UInt<1>("h00")) @[package.scala 46:20] + node _T_3325 = and(UInt<1>("h01"), _T_3324) @[package.scala 49:27] + node _T_3326 = and(_T_3321, _T_3325) @[package.scala 50:38] + node _T_3327 = or(_T_3319, _T_3326) @[package.scala 50:29] + node _T_3328 = and(UInt<1>("h01"), _T_3322) @[package.scala 49:27] + node _T_3329 = and(_T_3321, _T_3328) @[package.scala 50:38] + node _T_3330 = or(_T_3319, _T_3329) @[package.scala 50:29] + node _T_3331 = bits(_T_3317, 1, 1) @[package.scala 44:26] + node _T_3332 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_3334 = eq(_T_3332, UInt<1>("h00")) @[package.scala 46:20] + node _T_3335 = and(_T_3325, _T_3334) @[package.scala 49:27] + node _T_3336 = and(_T_3331, _T_3335) @[package.scala 50:38] + node _T_3337 = or(_T_3327, _T_3336) @[package.scala 50:29] + node _T_3338 = and(_T_3325, _T_3332) @[package.scala 49:27] + node _T_3339 = and(_T_3331, _T_3338) @[package.scala 50:38] + node _T_3340 = or(_T_3327, _T_3339) @[package.scala 50:29] + node _T_3341 = and(_T_3328, _T_3334) @[package.scala 49:27] + node _T_3342 = and(_T_3331, _T_3341) @[package.scala 50:38] + node _T_3343 = or(_T_3330, _T_3342) @[package.scala 50:29] + node _T_3344 = and(_T_3328, _T_3332) @[package.scala 49:27] + node _T_3345 = and(_T_3331, _T_3344) @[package.scala 50:38] + node _T_3346 = or(_T_3330, _T_3345) @[package.scala 50:29] + node _T_3347 = bits(_T_3317, 0, 0) @[package.scala 44:26] + node _T_3348 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_3350 = eq(_T_3348, UInt<1>("h00")) @[package.scala 46:20] + node _T_3351 = and(_T_3335, _T_3350) @[package.scala 49:27] + node _T_3352 = and(_T_3347, _T_3351) @[package.scala 50:38] + node _T_3353 = or(_T_3337, _T_3352) @[package.scala 50:29] + node _T_3354 = and(_T_3335, _T_3348) @[package.scala 49:27] + node _T_3355 = and(_T_3347, _T_3354) @[package.scala 50:38] + node _T_3356 = or(_T_3337, _T_3355) @[package.scala 50:29] + node _T_3357 = and(_T_3338, _T_3350) @[package.scala 49:27] + node _T_3358 = and(_T_3347, _T_3357) @[package.scala 50:38] + node _T_3359 = or(_T_3340, _T_3358) @[package.scala 50:29] + node _T_3360 = and(_T_3338, _T_3348) @[package.scala 49:27] + node _T_3361 = and(_T_3347, _T_3360) @[package.scala 50:38] + node _T_3362 = or(_T_3340, _T_3361) @[package.scala 50:29] + node _T_3363 = and(_T_3341, _T_3350) @[package.scala 49:27] + node _T_3364 = and(_T_3347, _T_3363) @[package.scala 50:38] + node _T_3365 = or(_T_3343, _T_3364) @[package.scala 50:29] + node _T_3366 = and(_T_3341, _T_3348) @[package.scala 49:27] + node _T_3367 = and(_T_3347, _T_3366) @[package.scala 50:38] + node _T_3368 = or(_T_3343, _T_3367) @[package.scala 50:29] + node _T_3369 = and(_T_3344, _T_3350) @[package.scala 49:27] + node _T_3370 = and(_T_3347, _T_3369) @[package.scala 50:38] + node _T_3371 = or(_T_3346, _T_3370) @[package.scala 50:29] + node _T_3372 = and(_T_3344, _T_3348) @[package.scala 49:27] + node _T_3373 = and(_T_3347, _T_3372) @[package.scala 50:38] + node _T_3374 = or(_T_3346, _T_3373) @[package.scala 50:29] + node _T_3375 = cat(_T_3356, _T_3353) @[Cat.scala 30:58] + node _T_3376 = cat(_T_3362, _T_3359) @[Cat.scala 30:58] + node _T_3377 = cat(_T_3376, _T_3375) @[Cat.scala 30:58] + node _T_3378 = cat(_T_3368, _T_3365) @[Cat.scala 30:58] + node _T_3379 = cat(_T_3374, _T_3371) @[Cat.scala 30:58] + node _T_3380 = cat(_T_3379, _T_3378) @[Cat.scala 30:58] + node _T_3381 = cat(_T_3380, _T_3377) @[Cat.scala 30:58] + _T_3305.mask <= _T_3381 @[Edges.scala 390:15] + _T_3305.data <= a_data @[Edges.scala 391:15] + node _T_3386 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_3388 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3389 = and(_T_3386, _T_3388) @[Parameters.scala 63:37] + node _T_3390 = or(UInt<1>("h00"), _T_3389) @[Parameters.scala 132:31] + node _T_3392 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3393 = cvt(_T_3392) @[Parameters.scala 117:49] + node _T_3395 = and(_T_3393, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3396 = asSInt(_T_3395) @[Parameters.scala 117:52] + node _T_3398 = eq(_T_3396, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3400 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3401 = cvt(_T_3400) @[Parameters.scala 117:49] + node _T_3403 = and(_T_3401, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_3404 = asSInt(_T_3403) @[Parameters.scala 117:52] + node _T_3406 = eq(_T_3404, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3408 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3409 = cvt(_T_3408) @[Parameters.scala 117:49] + node _T_3411 = and(_T_3409, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_3412 = asSInt(_T_3411) @[Parameters.scala 117:52] + node _T_3414 = eq(_T_3412, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3415 = or(_T_3398, _T_3406) @[Parameters.scala 133:42] + node _T_3416 = or(_T_3415, _T_3414) @[Parameters.scala 133:42] + node _T_3417 = and(_T_3390, _T_3416) @[Parameters.scala 132:56] + node _T_3420 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3422 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3423 = cvt(_T_3422) @[Parameters.scala 117:49] + node _T_3425 = and(_T_3423, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3426 = asSInt(_T_3425) @[Parameters.scala 117:52] + node _T_3428 = eq(_T_3426, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3430 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3431 = cvt(_T_3430) @[Parameters.scala 117:49] + node _T_3433 = and(_T_3431, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_3434 = asSInt(_T_3433) @[Parameters.scala 117:52] + node _T_3436 = eq(_T_3434, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3438 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3439 = cvt(_T_3438) @[Parameters.scala 117:49] + node _T_3441 = and(_T_3439, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_3442 = asSInt(_T_3441) @[Parameters.scala 117:52] + node _T_3444 = eq(_T_3442, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3446 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3447 = cvt(_T_3446) @[Parameters.scala 117:49] + node _T_3449 = and(_T_3447, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_3450 = asSInt(_T_3449) @[Parameters.scala 117:52] + node _T_3452 = eq(_T_3450, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3453 = or(_T_3428, _T_3436) @[Parameters.scala 133:42] + node _T_3454 = or(_T_3453, _T_3444) @[Parameters.scala 133:42] + node _T_3455 = or(_T_3454, _T_3452) @[Parameters.scala 133:42] + node _T_3456 = and(_T_3420, _T_3455) @[Parameters.scala 132:56] + node _T_3458 = or(UInt<1>("h00"), _T_3417) @[Parameters.scala 134:30] + node _T_3459 = or(_T_3458, _T_3456) @[Parameters.scala 134:30] + wire _T_3468 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 384:17] + _T_3468 is invalid @[Edges.scala 384:17] + _T_3468.opcode <= UInt<2>("h02") @[Edges.scala 385:15] + _T_3468.param <= UInt<3>("h02") @[Edges.scala 386:15] + _T_3468.size <= a_size @[Edges.scala 387:15] + _T_3468.source <= UInt<1>("h00") @[Edges.scala 388:15] + _T_3468.address <= s2_req.addr @[Edges.scala 389:15] + node _T_3478 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_3479 = dshl(UInt<1>("h01"), _T_3478) @[OneHot.scala 49:12] + node _T_3480 = bits(_T_3479, 2, 0) @[OneHot.scala 49:37] + node _T_3482 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3484 = bits(_T_3480, 2, 2) @[package.scala 44:26] + node _T_3485 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_3487 = eq(_T_3485, UInt<1>("h00")) @[package.scala 46:20] + node _T_3488 = and(UInt<1>("h01"), _T_3487) @[package.scala 49:27] + node _T_3489 = and(_T_3484, _T_3488) @[package.scala 50:38] + node _T_3490 = or(_T_3482, _T_3489) @[package.scala 50:29] + node _T_3491 = and(UInt<1>("h01"), _T_3485) @[package.scala 49:27] + node _T_3492 = and(_T_3484, _T_3491) @[package.scala 50:38] + node _T_3493 = or(_T_3482, _T_3492) @[package.scala 50:29] + node _T_3494 = bits(_T_3480, 1, 1) @[package.scala 44:26] + node _T_3495 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_3497 = eq(_T_3495, UInt<1>("h00")) @[package.scala 46:20] + node _T_3498 = and(_T_3488, _T_3497) @[package.scala 49:27] + node _T_3499 = and(_T_3494, _T_3498) @[package.scala 50:38] + node _T_3500 = or(_T_3490, _T_3499) @[package.scala 50:29] + node _T_3501 = and(_T_3488, _T_3495) @[package.scala 49:27] + node _T_3502 = and(_T_3494, _T_3501) @[package.scala 50:38] + node _T_3503 = or(_T_3490, _T_3502) @[package.scala 50:29] + node _T_3504 = and(_T_3491, _T_3497) @[package.scala 49:27] + node _T_3505 = and(_T_3494, _T_3504) @[package.scala 50:38] + node _T_3506 = or(_T_3493, _T_3505) @[package.scala 50:29] + node _T_3507 = and(_T_3491, _T_3495) @[package.scala 49:27] + node _T_3508 = and(_T_3494, _T_3507) @[package.scala 50:38] + node _T_3509 = or(_T_3493, _T_3508) @[package.scala 50:29] + node _T_3510 = bits(_T_3480, 0, 0) @[package.scala 44:26] + node _T_3511 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_3513 = eq(_T_3511, UInt<1>("h00")) @[package.scala 46:20] + node _T_3514 = and(_T_3498, _T_3513) @[package.scala 49:27] + node _T_3515 = and(_T_3510, _T_3514) @[package.scala 50:38] + node _T_3516 = or(_T_3500, _T_3515) @[package.scala 50:29] + node _T_3517 = and(_T_3498, _T_3511) @[package.scala 49:27] + node _T_3518 = and(_T_3510, _T_3517) @[package.scala 50:38] + node _T_3519 = or(_T_3500, _T_3518) @[package.scala 50:29] + node _T_3520 = and(_T_3501, _T_3513) @[package.scala 49:27] + node _T_3521 = and(_T_3510, _T_3520) @[package.scala 50:38] + node _T_3522 = or(_T_3503, _T_3521) @[package.scala 50:29] + node _T_3523 = and(_T_3501, _T_3511) @[package.scala 49:27] + node _T_3524 = and(_T_3510, _T_3523) @[package.scala 50:38] + node _T_3525 = or(_T_3503, _T_3524) @[package.scala 50:29] + node _T_3526 = and(_T_3504, _T_3513) @[package.scala 49:27] + node _T_3527 = and(_T_3510, _T_3526) @[package.scala 50:38] + node _T_3528 = or(_T_3506, _T_3527) @[package.scala 50:29] + node _T_3529 = and(_T_3504, _T_3511) @[package.scala 49:27] + node _T_3530 = and(_T_3510, _T_3529) @[package.scala 50:38] + node _T_3531 = or(_T_3506, _T_3530) @[package.scala 50:29] + node _T_3532 = and(_T_3507, _T_3513) @[package.scala 49:27] + node _T_3533 = and(_T_3510, _T_3532) @[package.scala 50:38] + node _T_3534 = or(_T_3509, _T_3533) @[package.scala 50:29] + node _T_3535 = and(_T_3507, _T_3511) @[package.scala 49:27] + node _T_3536 = and(_T_3510, _T_3535) @[package.scala 50:38] + node _T_3537 = or(_T_3509, _T_3536) @[package.scala 50:29] + node _T_3538 = cat(_T_3519, _T_3516) @[Cat.scala 30:58] + node _T_3539 = cat(_T_3525, _T_3522) @[Cat.scala 30:58] + node _T_3540 = cat(_T_3539, _T_3538) @[Cat.scala 30:58] + node _T_3541 = cat(_T_3531, _T_3528) @[Cat.scala 30:58] + node _T_3542 = cat(_T_3537, _T_3534) @[Cat.scala 30:58] + node _T_3543 = cat(_T_3542, _T_3541) @[Cat.scala 30:58] + node _T_3544 = cat(_T_3543, _T_3540) @[Cat.scala 30:58] + _T_3468.mask <= _T_3544 @[Edges.scala 390:15] + _T_3468.data <= a_data @[Edges.scala 391:15] + node _T_3549 = leq(UInt<1>("h00"), a_size) @[Parameters.scala 63:32] + node _T_3551 = leq(a_size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3552 = and(_T_3549, _T_3551) @[Parameters.scala 63:37] + node _T_3553 = or(UInt<1>("h00"), _T_3552) @[Parameters.scala 132:31] + node _T_3555 = xor(s2_req.addr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3556 = cvt(_T_3555) @[Parameters.scala 117:49] + node _T_3558 = and(_T_3556, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3559 = asSInt(_T_3558) @[Parameters.scala 117:52] + node _T_3561 = eq(_T_3559, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3563 = xor(s2_req.addr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3564 = cvt(_T_3563) @[Parameters.scala 117:49] + node _T_3566 = and(_T_3564, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_3567 = asSInt(_T_3566) @[Parameters.scala 117:52] + node _T_3569 = eq(_T_3567, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3571 = xor(s2_req.addr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3572 = cvt(_T_3571) @[Parameters.scala 117:49] + node _T_3574 = and(_T_3572, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_3575 = asSInt(_T_3574) @[Parameters.scala 117:52] + node _T_3577 = eq(_T_3575, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3578 = or(_T_3561, _T_3569) @[Parameters.scala 133:42] + node _T_3579 = or(_T_3578, _T_3577) @[Parameters.scala 133:42] + node _T_3580 = and(_T_3553, _T_3579) @[Parameters.scala 132:56] + node _T_3583 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3585 = xor(s2_req.addr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3586 = cvt(_T_3585) @[Parameters.scala 117:49] + node _T_3588 = and(_T_3586, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_3589 = asSInt(_T_3588) @[Parameters.scala 117:52] + node _T_3591 = eq(_T_3589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3593 = xor(s2_req.addr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3594 = cvt(_T_3593) @[Parameters.scala 117:49] + node _T_3596 = and(_T_3594, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_3597 = asSInt(_T_3596) @[Parameters.scala 117:52] + node _T_3599 = eq(_T_3597, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3601 = xor(s2_req.addr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3602 = cvt(_T_3601) @[Parameters.scala 117:49] + node _T_3604 = and(_T_3602, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_3605 = asSInt(_T_3604) @[Parameters.scala 117:52] + node _T_3607 = eq(_T_3605, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3609 = xor(s2_req.addr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3610 = cvt(_T_3609) @[Parameters.scala 117:49] + node _T_3612 = and(_T_3610, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_3613 = asSInt(_T_3612) @[Parameters.scala 117:52] + node _T_3615 = eq(_T_3613, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3616 = or(_T_3591, _T_3599) @[Parameters.scala 133:42] + node _T_3617 = or(_T_3616, _T_3607) @[Parameters.scala 133:42] + node _T_3618 = or(_T_3617, _T_3615) @[Parameters.scala 133:42] + node _T_3619 = and(_T_3583, _T_3618) @[Parameters.scala 132:56] + node _T_3621 = or(UInt<1>("h00"), _T_3580) @[Parameters.scala 134:30] + node _T_3622 = or(_T_3621, _T_3619) @[Parameters.scala 134:30] + wire _T_3631 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 384:17] + _T_3631 is invalid @[Edges.scala 384:17] + _T_3631.opcode <= UInt<2>("h02") @[Edges.scala 385:15] + _T_3631.param <= UInt<3>("h03") @[Edges.scala 386:15] + _T_3631.size <= a_size @[Edges.scala 387:15] + _T_3631.source <= UInt<1>("h00") @[Edges.scala 388:15] + _T_3631.address <= s2_req.addr @[Edges.scala 389:15] + node _T_3641 = bits(a_size, 1, 0) @[OneHot.scala 49:17] + node _T_3642 = dshl(UInt<1>("h01"), _T_3641) @[OneHot.scala 49:12] + node _T_3643 = bits(_T_3642, 2, 0) @[OneHot.scala 49:37] + node _T_3645 = geq(a_size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3647 = bits(_T_3643, 2, 2) @[package.scala 44:26] + node _T_3648 = bits(s2_req.addr, 2, 2) @[package.scala 45:26] + node _T_3650 = eq(_T_3648, UInt<1>("h00")) @[package.scala 46:20] + node _T_3651 = and(UInt<1>("h01"), _T_3650) @[package.scala 49:27] + node _T_3652 = and(_T_3647, _T_3651) @[package.scala 50:38] + node _T_3653 = or(_T_3645, _T_3652) @[package.scala 50:29] + node _T_3654 = and(UInt<1>("h01"), _T_3648) @[package.scala 49:27] + node _T_3655 = and(_T_3647, _T_3654) @[package.scala 50:38] + node _T_3656 = or(_T_3645, _T_3655) @[package.scala 50:29] + node _T_3657 = bits(_T_3643, 1, 1) @[package.scala 44:26] + node _T_3658 = bits(s2_req.addr, 1, 1) @[package.scala 45:26] + node _T_3660 = eq(_T_3658, UInt<1>("h00")) @[package.scala 46:20] + node _T_3661 = and(_T_3651, _T_3660) @[package.scala 49:27] + node _T_3662 = and(_T_3657, _T_3661) @[package.scala 50:38] + node _T_3663 = or(_T_3653, _T_3662) @[package.scala 50:29] + node _T_3664 = and(_T_3651, _T_3658) @[package.scala 49:27] + node _T_3665 = and(_T_3657, _T_3664) @[package.scala 50:38] + node _T_3666 = or(_T_3653, _T_3665) @[package.scala 50:29] + node _T_3667 = and(_T_3654, _T_3660) @[package.scala 49:27] + node _T_3668 = and(_T_3657, _T_3667) @[package.scala 50:38] + node _T_3669 = or(_T_3656, _T_3668) @[package.scala 50:29] + node _T_3670 = and(_T_3654, _T_3658) @[package.scala 49:27] + node _T_3671 = and(_T_3657, _T_3670) @[package.scala 50:38] + node _T_3672 = or(_T_3656, _T_3671) @[package.scala 50:29] + node _T_3673 = bits(_T_3643, 0, 0) @[package.scala 44:26] + node _T_3674 = bits(s2_req.addr, 0, 0) @[package.scala 45:26] + node _T_3676 = eq(_T_3674, UInt<1>("h00")) @[package.scala 46:20] + node _T_3677 = and(_T_3661, _T_3676) @[package.scala 49:27] + node _T_3678 = and(_T_3673, _T_3677) @[package.scala 50:38] + node _T_3679 = or(_T_3663, _T_3678) @[package.scala 50:29] + node _T_3680 = and(_T_3661, _T_3674) @[package.scala 49:27] + node _T_3681 = and(_T_3673, _T_3680) @[package.scala 50:38] + node _T_3682 = or(_T_3663, _T_3681) @[package.scala 50:29] + node _T_3683 = and(_T_3664, _T_3676) @[package.scala 49:27] + node _T_3684 = and(_T_3673, _T_3683) @[package.scala 50:38] + node _T_3685 = or(_T_3666, _T_3684) @[package.scala 50:29] + node _T_3686 = and(_T_3664, _T_3674) @[package.scala 49:27] + node _T_3687 = and(_T_3673, _T_3686) @[package.scala 50:38] + node _T_3688 = or(_T_3666, _T_3687) @[package.scala 50:29] + node _T_3689 = and(_T_3667, _T_3676) @[package.scala 49:27] + node _T_3690 = and(_T_3673, _T_3689) @[package.scala 50:38] + node _T_3691 = or(_T_3669, _T_3690) @[package.scala 50:29] + node _T_3692 = and(_T_3667, _T_3674) @[package.scala 49:27] + node _T_3693 = and(_T_3673, _T_3692) @[package.scala 50:38] + node _T_3694 = or(_T_3669, _T_3693) @[package.scala 50:29] + node _T_3695 = and(_T_3670, _T_3676) @[package.scala 49:27] + node _T_3696 = and(_T_3673, _T_3695) @[package.scala 50:38] + node _T_3697 = or(_T_3672, _T_3696) @[package.scala 50:29] + node _T_3698 = and(_T_3670, _T_3674) @[package.scala 49:27] + node _T_3699 = and(_T_3673, _T_3698) @[package.scala 50:38] + node _T_3700 = or(_T_3672, _T_3699) @[package.scala 50:29] + node _T_3701 = cat(_T_3682, _T_3679) @[Cat.scala 30:58] + node _T_3702 = cat(_T_3688, _T_3685) @[Cat.scala 30:58] + node _T_3703 = cat(_T_3702, _T_3701) @[Cat.scala 30:58] + node _T_3704 = cat(_T_3694, _T_3691) @[Cat.scala 30:58] + node _T_3705 = cat(_T_3700, _T_3697) @[Cat.scala 30:58] + node _T_3706 = cat(_T_3705, _T_3704) @[Cat.scala 30:58] + node _T_3707 = cat(_T_3706, _T_3703) @[Cat.scala 30:58] + _T_3631.mask <= _T_3707 @[Edges.scala 390:15] + _T_3631.data <= a_data @[Edges.scala 391:15] + node _T_3708 = eq(UInt<4>("h0f"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3709 = mux(_T_3708, _T_3631, _T_2233) @[Mux.scala 46:16] + node _T_3717 = eq(UInt<4>("h0e"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3718 = mux(_T_3717, _T_3468, _T_3709) @[Mux.scala 46:16] + node _T_3726 = eq(UInt<4>("h0d"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3727 = mux(_T_3726, _T_3305, _T_3718) @[Mux.scala 46:16] + node _T_3735 = eq(UInt<4>("h0c"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3736 = mux(_T_3735, _T_3142, _T_3727) @[Mux.scala 46:16] + node _T_3744 = eq(UInt<4>("h08"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3745 = mux(_T_3744, _T_2979, _T_3736) @[Mux.scala 46:16] + node _T_3753 = eq(UInt<4>("h0b"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3754 = mux(_T_3753, _T_2816, _T_3745) @[Mux.scala 46:16] + node _T_3762 = eq(UInt<4>("h0a"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3763 = mux(_T_3762, _T_2653, _T_3754) @[Mux.scala 46:16] + node _T_3771 = eq(UInt<4>("h09"), s2_req.cmd) @[Mux.scala 46:19] + node _T_3772 = mux(_T_3771, _T_2490, _T_3763) @[Mux.scala 46:16] + node _T_3780 = eq(UInt<3>("h04"), s2_req.cmd) @[Mux.scala 46:19] + node atomics = mux(_T_3780, _T_2327, _T_3772) @[Mux.scala 46:16] + node _T_3789 = eq(s2_victim_dirty, UInt<1>("h00")) @[DCache.scala 276:73] + node _T_3790 = and(s2_valid_cached_miss, _T_3789) @[DCache.scala 276:70] + node _T_3791 = not(uncachedInFlight[0]) @[DCache.scala 277:88] + node _T_3793 = eq(_T_3791, UInt<1>("h00")) @[DCache.scala 277:88] + node _T_3795 = eq(_T_3793, UInt<1>("h00")) @[DCache.scala 277:63] + node _T_3796 = and(s2_valid_uncached, _T_3795) @[DCache.scala 277:60] + node _T_3797 = or(_T_3790, _T_3796) @[DCache.scala 276:91] + node _T_3798 = and(grantackq.io.enq.ready, _T_3797) @[DCache.scala 276:44] + io.mem.0.a.valid <= _T_3798 @[DCache.scala 276:18] + node _T_3800 = eq(s2_uncached, UInt<1>("h00")) @[DCache.scala 278:24] + node _T_3802 = eq(s2_write, UInt<1>("h00")) @[DCache.scala 278:51] + node _T_3804 = eq(pstore1_amo, UInt<1>("h00")) @[DCache.scala 278:71] + node _T_3805 = mux(_T_3804, put, atomics) @[DCache.scala 278:70] + node _T_3813 = mux(_T_3802, get, _T_3805) @[DCache.scala 278:50] + node _T_3821 = mux(_T_3800, acquire, _T_3813) @[DCache.scala 278:23] + io.mem.0.a.bits <- _T_3821 @[DCache.scala 278:17] + node _T_3829 = and(io.mem.0.a.ready, io.mem.0.a.valid) @[Decoupled.scala 30:37] + when _T_3829 : @[DCache.scala 281:26] + when s2_uncached : @[DCache.scala 282:24] + uncachedInFlight[UInt<1>("h00")] <= UInt<1>("h01") @[DCache.scala 283:34] + uncachedReqs[UInt<1>("h00")] <- s2_req @[DCache.scala 284:30] + skip @[DCache.scala 282:24] + node _T_3849 = eq(s2_uncached, UInt<1>("h00")) @[DCache.scala 282:24] + when _T_3849 : @[DCache.scala 285:17] + cached_grant_wait <= UInt<1>("h01") @[DCache.scala 286:25] + skip @[DCache.scala 285:17] + skip @[DCache.scala 281:26] + node _T_3851 = and(io.mem.0.d.ready, io.mem.0.d.valid) @[Decoupled.scala 30:37] + node _T_3853 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_3854 = dshl(_T_3853, io.mem.0.d.bits.size) @[package.scala 19:71] + node _T_3855 = bits(_T_3854, 7, 0) @[package.scala 19:76] + node _T_3856 = not(_T_3855) @[package.scala 19:40] + node _T_3857 = shr(_T_3856, 3) @[Edges.scala 198:59] + node _T_3858 = bits(io.mem.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_3860 = mux(_T_3858, _T_3857, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_3862 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_3864 = sub(_T_3862, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_3865 = asUInt(_T_3864) @[Edges.scala 208:28] + node _T_3866 = tail(_T_3865, 1) @[Edges.scala 208:28] + node d_first = eq(_T_3862, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_3869 = eq(_T_3862, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_3871 = eq(_T_3860, UInt<1>("h00")) @[Edges.scala 210:47] + node d_last = or(_T_3869, _T_3871) @[Edges.scala 210:37] + node d_done = and(d_last, _T_3851) @[Edges.scala 211:22] + node _T_3872 = not(_T_3866) @[Edges.scala 212:27] + node _T_3873 = and(_T_3860, _T_3872) @[Edges.scala 212:25] + when _T_3851 : @[Edges.scala 213:17] + node _T_3874 = mux(d_first, _T_3860, _T_3866) @[Edges.scala 214:21] + _T_3862 <= _T_3874 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node d_address_inc = shl(_T_3873, 3) @[Edges.scala 247:29] + node _T_3877 = eq(io.mem.0.d.bits.opcode, UInt<3>("h04")) @[Package.scala 7:47] + node _T_3878 = eq(io.mem.0.d.bits.opcode, UInt<3>("h05")) @[Package.scala 7:47] + node grantIsCached = or(_T_3877, _T_3878) @[Package.scala 7:62] + node _T_3882 = eq(io.mem.0.d.bits.opcode, UInt<1>("h00")) @[Package.scala 7:47] + node _T_3883 = eq(io.mem.0.d.bits.opcode, UInt<1>("h01")) @[Package.scala 7:47] + node _T_3884 = eq(io.mem.0.d.bits.opcode, UInt<2>("h02")) @[Package.scala 7:47] + node _T_3885 = or(_T_3882, _T_3883) @[Package.scala 7:62] + node grantIsUncached = or(_T_3885, _T_3884) @[Package.scala 7:62] + node grantIsVoluntary = eq(io.mem.0.d.bits.opcode, UInt<3>("h06")) @[DCache.scala 294:47] + node grantIsRefill = eq(io.mem.0.d.bits.opcode, UInt<3>("h05")) @[DCache.scala 295:44] + io.mem.0.d.ready <= UInt<1>("h01") @[DCache.scala 296:18] + node _T_3889 = and(io.mem.0.d.ready, io.mem.0.d.valid) @[Decoupled.scala 30:37] + when _T_3889 : @[DCache.scala 297:26] + when grantIsCached : @[DCache.scala 298:26] + node _T_3890 = or(cached_grant_wait, reset) @[DCache.scala 299:13] + node _T_3892 = eq(_T_3890, UInt<1>("h00")) @[DCache.scala 299:13] + when _T_3892 : @[DCache.scala 299:13] + printf(clock, UInt<1>(1), "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:299 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n") @[DCache.scala 299:13] + stop(clock, UInt<1>(1), 1) @[DCache.scala 299:13] + skip @[DCache.scala 299:13] + when d_last : @[DCache.scala 300:20] + cached_grant_wait <= UInt<1>("h00") @[DCache.scala 300:40] + skip @[DCache.scala 300:20] + skip @[DCache.scala 298:26] + node _T_3895 = eq(grantIsCached, UInt<1>("h00")) @[DCache.scala 298:26] + node _T_3896 = and(_T_3895, grantIsUncached) @[DCache.scala 301:35] + when _T_3896 : @[DCache.scala 301:35] + node _T_3914 = or(uncachedInFlight[UInt<1>("h00")], reset) @[DCache.scala 304:13] + node _T_3916 = eq(_T_3914, UInt<1>("h00")) @[DCache.scala 304:13] + when _T_3916 : @[DCache.scala 304:13] + printf(clock, UInt<1>(1), "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:304 assert(uncachedInFlight(id), \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n") @[DCache.scala 304:13] + stop(clock, UInt<1>(1), 1) @[DCache.scala 304:13] + skip @[DCache.scala 304:13] + when d_last : @[DCache.scala 305:20] + uncachedInFlight[UInt<1>("h00")] <= UInt<1>("h00") @[DCache.scala 305:43] + skip @[DCache.scala 305:20] + s2_data <= io.mem.0.d.bits.data @[DCache.scala 306:15] + s2_req.cmd <= uncachedReqs[UInt<1>("h00")].cmd @[DCache.scala 307:18] + s2_req.typ <= uncachedReqs[UInt<1>("h00")].typ @[DCache.scala 308:18] + s2_req.tag <= uncachedReqs[UInt<1>("h00")].tag @[DCache.scala 309:18] + node _T_3921 = shr(tlb.io.resp.paddr, 3) @[DCache.scala 310:35] + node _T_3922 = bits(uncachedReqs[UInt<1>("h00")].addr, 2, 0) @[DCache.scala 310:76] + node _T_3923 = cat(_T_3921, _T_3922) @[Cat.scala 30:58] + s2_req.addr <= _T_3923 @[DCache.scala 310:19] + skip @[DCache.scala 301:35] + node _T_3925 = eq(grantIsCached, UInt<1>("h00")) @[DCache.scala 298:26] + node _T_3927 = eq(grantIsUncached, UInt<1>("h00")) @[DCache.scala 301:35] + node _T_3928 = and(_T_3925, _T_3927) @[DCache.scala 301:35] + node _T_3929 = and(_T_3928, grantIsVoluntary) @[DCache.scala 311:36] + when _T_3929 : @[DCache.scala 311:36] + node _T_3930 = or(release_ack_wait, reset) @[DCache.scala 312:13] + node _T_3932 = eq(_T_3930, UInt<1>("h00")) @[DCache.scala 312:13] + when _T_3932 : @[DCache.scala 312:13] + printf(clock, UInt<1>(1), "Assertion failed: A ReleaseAck was unexpected by the dcache.\n at DCache.scala:312 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n") @[DCache.scala 312:13] + stop(clock, UInt<1>(1), 1) @[DCache.scala 312:13] + skip @[DCache.scala 312:13] + release_ack_wait <= UInt<1>("h00") @[DCache.scala 313:24] + skip @[DCache.scala 311:36] + skip @[DCache.scala 297:26] + node doRefillBeat = and(grantIsRefill, io.mem.0.d.valid) @[DCache.scala 318:36] + dataArb.io.in[1].valid <= doRefillBeat @[DCache.scala 319:26] + node _T_3935 = eq(doRefillBeat, UInt<1>("h00")) @[DCache.scala 320:36] + node _T_3936 = or(dataArb.io.in[1].ready, _T_3935) @[DCache.scala 320:33] + node _T_3937 = or(_T_3936, reset) @[DCache.scala 320:9] + node _T_3939 = eq(_T_3937, UInt<1>("h00")) @[DCache.scala 320:9] + when _T_3939 : @[DCache.scala 320:9] + printf(clock, UInt<1>(1), "Assertion failed\n at DCache.scala:320 assert(dataArb.io.in(1).ready || !doRefillBeat)\n") @[DCache.scala 320:9] + stop(clock, UInt<1>(1), 1) @[DCache.scala 320:9] + skip @[DCache.scala 320:9] + dataArb.io.in[1].bits.write <= UInt<1>("h01") @[DCache.scala 321:31] + node _T_3941 = or(acquire_address, d_address_inc) @[DCache.scala 322:52] + dataArb.io.in[1].bits.addr <= _T_3941 @[DCache.scala 322:30] + dataArb.io.in[1].bits.way_en <= s2_victim_way @[DCache.scala 323:32] + dataArb.io.in[1].bits.wdata <= io.mem.0.d.bits.data @[DCache.scala 324:31] + node _T_3943 = not(UInt<8>("h00")) @[DCache.scala 325:34] + dataArb.io.in[1].bits.wmask <= _T_3943 @[DCache.scala 325:31] + node _T_3944 = and(grantIsCached, d_done) @[DCache.scala 327:48] + metaWriteArb.io.in[1].valid <= _T_3944 @[DCache.scala 327:31] + node _T_3946 = eq(metaWriteArb.io.in[1].valid, UInt<1>("h00")) @[DCache.scala 328:10] + node _T_3947 = or(_T_3946, metaWriteArb.io.in[1].ready) @[DCache.scala 328:39] + node _T_3948 = or(_T_3947, reset) @[DCache.scala 328:9] + node _T_3950 = eq(_T_3948, UInt<1>("h00")) @[DCache.scala 328:9] + when _T_3950 : @[DCache.scala 328:9] + printf(clock, UInt<1>(1), "Assertion failed\n at DCache.scala:328 assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready)\n") @[DCache.scala 328:9] + stop(clock, UInt<1>(1), 1) @[DCache.scala 328:9] + skip @[DCache.scala 328:9] + metaWriteArb.io.in[1].bits.way_en <= s2_victim_way @[DCache.scala 329:37] + node _T_3951 = bits(s2_req.addr, 11, 6) @[DCache.scala 330:48] + metaWriteArb.io.in[1].bits.idx <= _T_3951 @[DCache.scala 330:34] + node _T_3953 = eq(s2_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_3955 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_3956 = or(_T_3953, _T_3955) @[Consts.scala 36:42] + node _T_3957 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_3959 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_3960 = or(_T_3957, _T_3959) @[Consts.scala 33:33] + node _T_3961 = or(_T_3956, _T_3960) @[Consts.scala 36:59] + node _T_3963 = eq(s2_req.cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_3965 = eq(s2_req.cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_3966 = or(_T_3963, _T_3965) @[Consts.scala 36:42] + node _T_3967 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] + node _T_3969 = eq(s2_req.cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_3970 = or(_T_3967, _T_3969) @[Consts.scala 33:33] + node _T_3971 = or(_T_3966, _T_3970) @[Consts.scala 36:59] + node _T_3973 = eq(s2_req.cmd, UInt<2>("h03")) @[Consts.scala 37:54] + node _T_3974 = or(_T_3971, _T_3973) @[Consts.scala 37:47] + node _T_3976 = eq(s2_req.cmd, UInt<3>("h06")) @[Consts.scala 37:71] + node _T_3977 = or(_T_3974, _T_3976) @[Consts.scala 37:64] + node _T_3978 = cat(_T_3961, _T_3977) @[Cat.scala 30:58] + node _T_3979 = cat(_T_3978, io.mem.0.d.bits.param) @[Cat.scala 30:58] + node _T_3983 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_3985 = cat(_T_3983, UInt<2>("h01")) @[Cat.scala 30:58] + node _T_3989 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58] + node _T_3991 = cat(_T_3989, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_3995 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_3997 = cat(_T_3995, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_4001 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 30:58] + node _T_4003 = cat(_T_4001, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_4005 = eq(_T_4003, _T_3979) @[Mux.scala 46:19] + node _T_4006 = mux(_T_4005, UInt<2>("h03"), UInt<2>("h00")) @[Mux.scala 46:16] + node _T_4007 = eq(_T_3997, _T_3979) @[Mux.scala 46:19] + node _T_4008 = mux(_T_4007, UInt<2>("h02"), _T_4006) @[Mux.scala 46:16] + node _T_4009 = eq(_T_3991, _T_3979) @[Mux.scala 46:19] + node _T_4010 = mux(_T_4009, UInt<2>("h02"), _T_4008) @[Mux.scala 46:16] + node _T_4011 = eq(_T_3985, _T_3979) @[Mux.scala 46:19] + node _T_4012 = mux(_T_4011, UInt<2>("h01"), _T_4010) @[Mux.scala 46:16] + wire _T_4015 : {state : UInt<2>} @[Metadata.scala 160:20] + _T_4015 is invalid @[Metadata.scala 160:20] + _T_4015.state <= _T_4012 @[Metadata.scala 161:16] + metaWriteArb.io.in[1].bits.data.coh <- _T_4015 @[DCache.scala 331:39] + node _T_4017 = bits(s2_req.addr, 31, 12) @[DCache.scala 332:53] + metaWriteArb.io.in[1].bits.data.tag <= _T_4017 @[DCache.scala 332:39] + reg blockUncachedGrant : UInt<1>, clock @[DCache.scala 334:31] + blockUncachedGrant <= dataArb.io.out.valid @[DCache.scala 335:22] + when grantIsUncached : @[DCache.scala 336:26] + node _T_4019 = or(blockUncachedGrant, s1_valid) @[DCache.scala 337:44] + node _T_4021 = eq(_T_4019, UInt<1>("h00")) @[DCache.scala 337:23] + io.mem.0.d.ready <= _T_4021 @[DCache.scala 337:20] + node _T_4023 = eq(io.mem.0.d.ready, UInt<1>("h00")) @[DCache.scala 339:29] + node _T_4024 = and(io.mem.0.d.valid, _T_4023) @[DCache.scala 339:26] + when _T_4024 : @[DCache.scala 339:46] + io.cpu.req.ready <= UInt<1>("h00") @[DCache.scala 340:24] + dataArb.io.in[1].valid <= UInt<1>("h01") @[DCache.scala 341:30] + dataArb.io.in[1].bits.write <= UInt<1>("h00") @[DCache.scala 342:35] + node _T_4029 = eq(dataArb.io.in[1].ready, UInt<1>("h00")) @[DCache.scala 343:29] + blockUncachedGrant <= _T_4029 @[DCache.scala 343:26] + skip @[DCache.scala 339:46] + skip @[DCache.scala 336:26] + node _T_4030 = bits(io.mem.0.d.bits.opcode, 2, 2) @[Edges.scala 67:36] + node _T_4031 = bits(io.mem.0.d.bits.opcode, 1, 1) @[Edges.scala 67:52] + node _T_4033 = eq(_T_4031, UInt<1>("h00")) @[Edges.scala 67:43] + node _T_4034 = and(_T_4030, _T_4033) @[Edges.scala 67:40] + node _T_4035 = and(d_done, _T_4034) @[DCache.scala 348:36] + grantackq.io.enq.valid <= _T_4035 @[DCache.scala 348:26] + wire _T_4038 : {sink : UInt<4>} @[Edges.scala 333:17] + _T_4038 is invalid @[Edges.scala 333:17] + _T_4038.sink <= io.mem.0.d.bits.sink @[Edges.scala 334:12] + grantackq.io.enq.bits <- _T_4038 @[DCache.scala 349:25] + io.mem.0.e <- grantackq.io.deq @[DCache.scala 350:12] + node _T_4041 = eq(grantackq.io.enq.valid, UInt<1>("h00")) @[DCache.scala 351:10] + node _T_4042 = or(_T_4041, grantackq.io.enq.ready) @[DCache.scala 351:34] + node _T_4043 = or(_T_4042, reset) @[DCache.scala 351:9] + node _T_4045 = eq(_T_4043, UInt<1>("h00")) @[DCache.scala 351:9] + when _T_4045 : @[DCache.scala 351:9] + printf(clock, UInt<1>(1), "Assertion failed: Too many Grants received by dcache.\n at DCache.scala:351 assert(!grantackq.io.enq.valid || grantackq.io.enq.ready, \"Too many Grants received by dcache.\")\n") @[DCache.scala 351:9] + stop(clock, UInt<1>(1), 1) @[DCache.scala 351:9] + skip @[DCache.scala 351:9] + when d_done : @[DCache.scala 352:17] + _T_570 <= UInt<1>("h01") @[Replacement.scala 20:22] + skip @[DCache.scala 352:17] + node _T_4047 = or(releaseInFlight, lrscValid) @[DCache.scala 355:37] + node _T_4048 = and(s2_valid_hit, s2_lr) @[DCache.scala 355:67] + node block_probe = or(_T_4047, _T_4048) @[DCache.scala 355:50] + node _T_4050 = eq(block_probe, UInt<1>("h00")) @[DCache.scala 356:51] + node _T_4051 = and(io.mem.0.b.valid, _T_4050) @[DCache.scala 356:48] + metaReadArb.io.in[1].valid <= _T_4051 @[DCache.scala 356:30] + node _T_4053 = eq(block_probe, UInt<1>("h00")) @[DCache.scala 357:51] + node _T_4054 = and(metaReadArb.io.in[1].ready, _T_4053) @[DCache.scala 357:48] + node _T_4056 = eq(s1_valid, UInt<1>("h00")) @[DCache.scala 357:67] + node _T_4057 = and(_T_4054, _T_4056) @[DCache.scala 357:64] + node _T_4059 = eq(s2_valid, UInt<1>("h00")) @[DCache.scala 357:81] + node _T_4060 = or(_T_4059, s2_valid_hit) @[DCache.scala 357:91] + node _T_4061 = and(_T_4057, _T_4060) @[DCache.scala 357:77] + io.mem.0.b.ready <= _T_4061 @[DCache.scala 357:18] + node _T_4062 = bits(io.mem.0.b.bits.address, 11, 6) @[DCache.scala 358:57] + metaReadArb.io.in[1].bits.idx <= _T_4062 @[DCache.scala 358:33] + node _T_4064 = not(UInt<4>("h00")) @[DCache.scala 359:39] + metaReadArb.io.in[1].bits.way_en <= _T_4064 @[DCache.scala 359:36] + node _T_4065 = and(io.mem.0.c.ready, io.mem.0.c.valid) @[Decoupled.scala 30:37] + node _T_4067 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4068 = dshl(_T_4067, io.mem.0.c.bits.size) @[package.scala 19:71] + node _T_4069 = bits(_T_4068, 7, 0) @[package.scala 19:76] + node _T_4070 = not(_T_4069) @[package.scala 19:40] + node _T_4071 = shr(_T_4070, 3) @[Edges.scala 198:59] + node _T_4072 = bits(io.mem.0.c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4074 = mux(_T_4072, _T_4071, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4076 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4078 = sub(_T_4076, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4079 = asUInt(_T_4078) @[Edges.scala 208:28] + node _T_4080 = tail(_T_4079, 1) @[Edges.scala 208:28] + node _T_4082 = eq(_T_4076, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4084 = eq(_T_4076, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4086 = eq(_T_4074, UInt<1>("h00")) @[Edges.scala 210:47] + node c_last = or(_T_4084, _T_4086) @[Edges.scala 210:37] + node releaseDone = and(c_last, _T_4065) @[Edges.scala 211:22] + node _T_4087 = not(_T_4080) @[Edges.scala 212:27] + node c_count = and(_T_4074, _T_4087) @[Edges.scala 212:25] + when _T_4065 : @[Edges.scala 213:17] + node _T_4088 = mux(_T_4082, _T_4074, _T_4080) @[Edges.scala 214:21] + _T_4076 <= _T_4088 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_4090 = eq(io.mem.0.c.ready, UInt<1>("h00")) @[DCache.scala 363:43] + node releaseRejected = and(io.mem.0.c.valid, _T_4090) @[DCache.scala 363:40] + node _T_4091 = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid) @[Decoupled.scala 30:37] + reg s1_release_data_valid : UInt<1>, clock @[DCache.scala 364:34] + s1_release_data_valid <= _T_4091 @[DCache.scala 364:34] + node _T_4093 = eq(releaseRejected, UInt<1>("h00")) @[DCache.scala 365:67] + node _T_4094 = and(s1_release_data_valid, _T_4093) @[DCache.scala 365:64] + reg s2_release_data_valid : UInt<1>, clock @[DCache.scala 365:34] + s2_release_data_valid <= _T_4094 @[DCache.scala 365:34] + node _T_4096 = cat(UInt<1>("h00"), c_count) @[Cat.scala 30:58] + node _T_4099 = cat(UInt<1>("h00"), s2_release_data_valid) @[Cat.scala 30:58] + node _T_4100 = add(s1_release_data_valid, _T_4099) @[DCache.scala 366:101] + node _T_4101 = tail(_T_4100, 1) @[DCache.scala 366:101] + node _T_4102 = mux(releaseRejected, UInt<1>("h00"), _T_4101) @[DCache.scala 366:52] + node _T_4103 = add(_T_4096, _T_4102) @[DCache.scala 366:47] + node releaseDataBeat = tail(_T_4103, 1) @[DCache.scala 366:47] + wire nackResponseMessage : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>} @[Edges.scala 305:17] + nackResponseMessage is invalid @[Edges.scala 305:17] + nackResponseMessage.opcode <= UInt<3>("h04") @[Edges.scala 306:15] + nackResponseMessage.param <= UInt<3>("h05") @[Edges.scala 307:15] + nackResponseMessage.size <= probe_bits.size @[Edges.scala 308:15] + nackResponseMessage.source <= probe_bits.source @[Edges.scala 309:15] + nackResponseMessage.address <= probe_bits.address @[Edges.scala 310:15] + nackResponseMessage.data <= UInt<1>("h00") @[Edges.scala 311:15] + nackResponseMessage.error <= UInt<1>("h00") @[Edges.scala 312:15] + node _T_4127 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_4129 = leq(UInt<3>("h06"), UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_4130 = and(_T_4127, _T_4129) @[Parameters.scala 63:37] + node _T_4131 = or(UInt<1>("h00"), _T_4130) @[Parameters.scala 132:31] + node _T_4133 = xor(probe_bits.address, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_4134 = cvt(_T_4133) @[Parameters.scala 117:49] + node _T_4136 = and(_T_4134, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_4137 = asSInt(_T_4136) @[Parameters.scala 117:52] + node _T_4139 = eq(_T_4137, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4141 = xor(probe_bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_4142 = cvt(_T_4141) @[Parameters.scala 117:49] + node _T_4144 = and(_T_4142, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_4145 = asSInt(_T_4144) @[Parameters.scala 117:52] + node _T_4147 = eq(_T_4145, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4148 = or(_T_4139, _T_4147) @[Parameters.scala 133:42] + node _T_4149 = and(_T_4131, _T_4148) @[Parameters.scala 132:56] + node _T_4152 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_4154 = xor(probe_bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4155 = cvt(_T_4154) @[Parameters.scala 117:49] + node _T_4157 = and(_T_4155, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_4158 = asSInt(_T_4157) @[Parameters.scala 117:52] + node _T_4160 = eq(_T_4158, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4162 = xor(probe_bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_4163 = cvt(_T_4162) @[Parameters.scala 117:49] + node _T_4165 = and(_T_4163, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_4166 = asSInt(_T_4165) @[Parameters.scala 117:52] + node _T_4168 = eq(_T_4166, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4170 = xor(probe_bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_4171 = cvt(_T_4170) @[Parameters.scala 117:49] + node _T_4173 = and(_T_4171, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_4174 = asSInt(_T_4173) @[Parameters.scala 117:52] + node _T_4176 = eq(_T_4174, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4177 = or(_T_4160, _T_4168) @[Parameters.scala 133:42] + node _T_4178 = or(_T_4177, _T_4176) @[Parameters.scala 133:42] + node _T_4179 = and(_T_4152, _T_4178) @[Parameters.scala 132:56] + node _T_4181 = or(UInt<1>("h00"), _T_4149) @[Parameters.scala 134:30] + node _T_4182 = or(_T_4181, _T_4179) @[Parameters.scala 134:30] + wire voluntaryReleaseMessage : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>} @[Edges.scala 290:17] + voluntaryReleaseMessage is invalid @[Edges.scala 290:17] + voluntaryReleaseMessage.opcode <= UInt<3>("h07") @[Edges.scala 291:15] + voluntaryReleaseMessage.param <= s2_shrink_param @[Edges.scala 292:15] + voluntaryReleaseMessage.size <= UInt<3>("h06") @[Edges.scala 293:15] + voluntaryReleaseMessage.source <= UInt<1>("h00") @[Edges.scala 294:15] + voluntaryReleaseMessage.address <= probe_bits.address @[Edges.scala 295:15] + voluntaryReleaseMessage.data <= s2_data @[Edges.scala 296:15] + voluntaryReleaseMessage.error <= UInt<1>("h00") @[Edges.scala 297:15] + node _T_4201 = eq(s2_prb_ack_data, UInt<1>("h00")) @[DCache.scala 383:34] + wire _T_4210 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>} @[Edges.scala 305:17] + _T_4210 is invalid @[Edges.scala 305:17] + _T_4210.opcode <= UInt<3>("h04") @[Edges.scala 306:15] + _T_4210.param <= s2_report_param @[Edges.scala 307:15] + _T_4210.size <= probe_bits.size @[Edges.scala 308:15] + _T_4210.source <= probe_bits.source @[Edges.scala 309:15] + _T_4210.address <= probe_bits.address @[Edges.scala 310:15] + _T_4210.data <= UInt<1>("h00") @[Edges.scala 311:15] + _T_4210.error <= UInt<1>("h00") @[Edges.scala 312:15] + wire _T_4229 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>} @[Edges.scala 320:17] + _T_4229 is invalid @[Edges.scala 320:17] + _T_4229.opcode <= UInt<3>("h05") @[Edges.scala 321:15] + _T_4229.param <= s2_report_param @[Edges.scala 322:15] + _T_4229.size <= probe_bits.size @[Edges.scala 323:15] + _T_4229.source <= probe_bits.source @[Edges.scala 324:15] + _T_4229.address <= probe_bits.address @[Edges.scala 325:15] + _T_4229.data <= s2_data @[Edges.scala 326:15] + _T_4229.error <= UInt<1>("h00") @[Edges.scala 327:15] + node probeResponseMessage = mux(_T_4201, _T_4210, _T_4229) @[DCache.scala 383:33] + io.mem.0.c.valid <= s2_release_data_valid @[DCache.scala 392:18] + io.mem.0.c.bits <- nackResponseMessage @[DCache.scala 393:17] + wire newCoh : {state : UInt<2>} + newCoh is invalid + newCoh <- probeNewCoh + releaseWay <= s2_probe_way @[DCache.scala 395:14] + node _T_4247 = and(s2_victimize, s2_victim_dirty) @[DCache.scala 397:22] + when _T_4247 : @[DCache.scala 397:42] + node _T_4248 = and(s2_valid, s2_hit_valid) @[DCache.scala 398:23] + node _T_4250 = eq(_T_4248, UInt<1>("h00")) @[DCache.scala 398:12] + node _T_4251 = or(_T_4250, reset) @[DCache.scala 398:11] + node _T_4253 = eq(_T_4251, UInt<1>("h00")) @[DCache.scala 398:11] + when _T_4253 : @[DCache.scala 398:11] + printf(clock, UInt<1>(1), "Assertion failed\n at DCache.scala:398 assert(!(s2_valid && s2_hit_valid))\n") @[DCache.scala 398:11] + stop(clock, UInt<1>(1), 1) @[DCache.scala 398:11] + skip @[DCache.scala 398:11] + release_state <= UInt<3>("h01") @[DCache.scala 399:19] + node _T_4254 = bits(s2_req.addr, 11, 6) @[DCache.scala 400:57] + node _T_4255 = cat(s2_victim_tag, _T_4254) @[Cat.scala 30:58] + node _T_4256 = shl(_T_4255, 6) @[DCache.scala 400:75] + probe_bits.address <= _T_4256 @[DCache.scala 400:24] + skip @[DCache.scala 397:42] + when s2_probe : @[DCache.scala 402:19] + when s2_prb_ack_data : @[DCache.scala 403:28] + release_state <= UInt<3>("h02") @[DCache.scala 403:44] + skip @[DCache.scala 403:28] + node _T_4258 = gt(s2_probe_state.state, UInt<2>("h00")) @[Metadata.scala 50:45] + node _T_4260 = eq(s2_prb_ack_data, UInt<1>("h00")) @[DCache.scala 403:28] + node _T_4261 = and(_T_4260, _T_4258) @[DCache.scala 404:42] + when _T_4261 : @[DCache.scala 404:42] + release_state <= UInt<3>("h03") @[DCache.scala 404:58] + skip @[DCache.scala 404:42] + node _T_4263 = eq(s2_prb_ack_data, UInt<1>("h00")) @[DCache.scala 403:28] + node _T_4265 = eq(_T_4258, UInt<1>("h00")) @[DCache.scala 404:42] + node _T_4266 = and(_T_4263, _T_4265) @[DCache.scala 404:42] + when _T_4266 : @[DCache.scala 405:16] + io.mem.0.c.valid <= UInt<1>("h01") @[DCache.scala 406:22] + release_state <= UInt<3>("h04") @[DCache.scala 407:21] + skip @[DCache.scala 405:16] + skip @[DCache.scala 402:19] + when releaseDone : @[DCache.scala 410:22] + release_state <= UInt<3>("h00") @[DCache.scala 410:38] + skip @[DCache.scala 410:22] + node _T_4268 = eq(release_state, UInt<3>("h04")) @[Package.scala 7:47] + node _T_4269 = eq(release_state, UInt<3>("h03")) @[Package.scala 7:47] + node _T_4270 = or(_T_4268, _T_4269) @[Package.scala 7:62] + when _T_4270 : @[DCache.scala 411:69] + io.mem.0.c.valid <= UInt<1>("h01") @[DCache.scala 412:20] + skip @[DCache.scala 411:69] + node _T_4272 = eq(release_state, UInt<3>("h03")) @[Package.scala 7:47] + node _T_4273 = eq(release_state, UInt<3>("h02")) @[Package.scala 7:47] + node _T_4274 = or(_T_4272, _T_4273) @[Package.scala 7:62] + when _T_4274 : @[DCache.scala 414:70] + io.mem.0.c.bits <- probeResponseMessage @[DCache.scala 415:19] + when releaseDone : @[DCache.scala 416:24] + release_state <= UInt<3>("h06") @[DCache.scala 416:40] + skip @[DCache.scala 416:24] + skip @[DCache.scala 414:70] + node _T_4275 = eq(release_state, UInt<3>("h01")) @[Package.scala 7:47] + node _T_4276 = eq(release_state, UInt<3>("h05")) @[Package.scala 7:47] + node _T_4277 = or(_T_4275, _T_4276) @[Package.scala 7:62] + when _T_4277 : @[DCache.scala 418:79] + io.mem.0.c.bits <- voluntaryReleaseMessage @[DCache.scala 419:19] + newCoh <- voluntaryNewCoh @[DCache.scala 420:12] + releaseWay <= s2_victim_way @[DCache.scala 421:16] + when releaseDone : @[DCache.scala 422:24] + release_state <= UInt<3>("h05") @[DCache.scala 423:21] + release_ack_wait <= UInt<1>("h01") @[DCache.scala 424:24] + skip @[DCache.scala 422:24] + skip @[DCache.scala 418:79] + node _T_4279 = and(io.mem.0.c.ready, io.mem.0.c.valid) @[Decoupled.scala 30:37] + node _T_4281 = eq(_T_4279, UInt<1>("h00")) @[DCache.scala 427:21] + node _T_4282 = and(s2_probe, _T_4281) @[DCache.scala 427:18] + when _T_4282 : @[DCache.scala 427:39] + s1_nack <= UInt<1>("h01") @[DCache.scala 427:49] + skip @[DCache.scala 427:39] + io.mem.0.c.bits.address <= probe_bits.address @[DCache.scala 428:25] + io.mem.0.c.bits.data <= s2_data @[DCache.scala 429:22] + node _T_4285 = lt(releaseDataBeat, UInt<4>("h08")) @[DCache.scala 431:60] + node _T_4286 = and(inWriteback, _T_4285) @[DCache.scala 431:41] + dataArb.io.in[2].valid <= _T_4286 @[DCache.scala 431:26] + dataArb.io.in[2].bits.write <= UInt<1>("h00") @[DCache.scala 432:31] + node _T_4288 = bits(releaseDataBeat, 2, 0) @[DCache.scala 433:73] + node _T_4289 = shl(_T_4288, 3) @[DCache.scala 433:100] + node _T_4290 = or(io.mem.0.c.bits.address, _T_4289) @[DCache.scala 433:55] + dataArb.io.in[2].bits.addr <= _T_4290 @[DCache.scala 433:30] + node _T_4292 = not(UInt<4>("h00")) @[DCache.scala 434:35] + dataArb.io.in[2].bits.way_en <= _T_4292 @[DCache.scala 434:32] + node _T_4293 = eq(release_state, UInt<3>("h05")) @[Package.scala 7:47] + node _T_4294 = eq(release_state, UInt<3>("h06")) @[Package.scala 7:47] + node _T_4295 = or(_T_4293, _T_4294) @[Package.scala 7:62] + metaWriteArb.io.in[2].valid <= _T_4295 @[DCache.scala 436:31] + metaWriteArb.io.in[2].bits.way_en <= releaseWay @[DCache.scala 437:37] + node _T_4296 = bits(io.mem.0.c.bits.address, 11, 6) @[DCache.scala 438:58] + metaWriteArb.io.in[2].bits.idx <= _T_4296 @[DCache.scala 438:34] + metaWriteArb.io.in[2].bits.data.coh <- newCoh @[DCache.scala 439:39] + node _T_4297 = bits(io.mem.0.c.bits.address, 31, 12) @[DCache.scala 440:63] + metaWriteArb.io.in[2].bits.data.tag <= _T_4297 @[DCache.scala 440:39] + node _T_4298 = and(metaWriteArb.io.in[2].ready, metaWriteArb.io.in[2].valid) @[Decoupled.scala 30:37] + when _T_4298 : @[DCache.scala 441:39] + release_state <= UInt<3>("h00") @[DCache.scala 441:55] + skip @[DCache.scala 441:39] + io.cpu.resp.valid <= s2_valid_hit @[DCache.scala 444:21] + io.cpu.resp.bits <- s2_req @[DCache.scala 445:20] + io.cpu.resp.bits.has_data <= s2_read @[DCache.scala 446:29] + io.cpu.resp.bits.replay <= UInt<1>("h00") @[DCache.scala 447:27] + node _T_4300 = or(s1_valid, s2_valid) @[DCache.scala 448:32] + node _T_4301 = or(_T_4300, cached_grant_wait) @[DCache.scala 448:44] + node _T_4303 = neq(uncachedInFlight[0], UInt<1>("h00")) @[DCache.scala 448:92] + node _T_4304 = or(_T_4301, _T_4303) @[DCache.scala 448:65] + node _T_4306 = eq(_T_4304, UInt<1>("h00")) @[DCache.scala 448:21] + io.cpu.ordered <= _T_4306 @[DCache.scala 448:18] + node _T_4307 = and(io.mem.0.d.ready, io.mem.0.d.valid) @[Decoupled.scala 30:37] + node _T_4308 = and(_T_4307, grantIsUncached) @[DCache.scala 451:41] + io.cpu.replay_next <= _T_4308 @[DCache.scala 451:22] + reg doUncachedResp : UInt<1>, clock @[DCache.scala 452:27] + doUncachedResp <= io.cpu.replay_next @[DCache.scala 452:27] + when doUncachedResp : @[DCache.scala 453:25] + node _T_4310 = eq(s2_valid_hit, UInt<1>("h00")) @[DCache.scala 454:12] + node _T_4311 = or(_T_4310, reset) @[DCache.scala 454:11] + node _T_4313 = eq(_T_4311, UInt<1>("h00")) @[DCache.scala 454:11] + when _T_4313 : @[DCache.scala 454:11] + printf(clock, UInt<1>(1), "Assertion failed\n at DCache.scala:454 assert(!s2_valid_hit)\n") @[DCache.scala 454:11] + stop(clock, UInt<1>(1), 1) @[DCache.scala 454:11] + skip @[DCache.scala 454:11] + io.cpu.resp.valid <= UInt<1>("h01") @[DCache.scala 455:23] + io.cpu.resp.bits.replay <= UInt<1>("h01") @[DCache.scala 456:29] + skip @[DCache.scala 453:25] + node _T_4317 = cat(UInt<1>("h00"), UInt<6>("h00")) @[Cat.scala 30:58] + node s2_data_word = dshr(s2_data, _T_4317) @[DCache.scala 461:30] + node _T_4318 = bits(s2_req.typ, 2, 2) @[Consts.scala 20:31] + node _T_4320 = eq(_T_4318, UInt<1>("h00")) @[Consts.scala 20:28] + node _T_4321 = bits(s2_req.typ, 1, 0) @[AmoAlu.scala 12:17] + node _T_4322 = bits(s2_req.addr, 2, 2) @[AmoAlu.scala 45:29] + node _T_4323 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 45:37] + node _T_4324 = bits(s2_data_word, 31, 0) @[AmoAlu.scala 45:55] + node _T_4325 = mux(_T_4322, _T_4323, _T_4324) @[AmoAlu.scala 45:24] + node _T_4327 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 46:33] + node _T_4329 = mux(_T_4327, UInt<1>("h00"), _T_4325) @[AmoAlu.scala 47:23] + node _T_4331 = eq(_T_4321, UInt<2>("h02")) @[AmoAlu.scala 48:26] + node _T_4332 = or(_T_4331, _T_4327) @[AmoAlu.scala 48:38] + node _T_4333 = bits(_T_4329, 31, 31) @[AmoAlu.scala 48:85] + node _T_4334 = and(_T_4320, _T_4333) @[AmoAlu.scala 48:76] + node _T_4335 = bits(_T_4334, 0, 0) @[Bitwise.scala 71:15] + node _T_4338 = mux(_T_4335, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_4339 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 48:98] + node _T_4340 = mux(_T_4332, _T_4338, _T_4339) @[AmoAlu.scala 48:20] + node _T_4341 = cat(_T_4340, _T_4329) @[Cat.scala 30:58] + node _T_4342 = bits(s2_req.addr, 1, 1) @[AmoAlu.scala 45:29] + node _T_4343 = bits(_T_4341, 31, 16) @[AmoAlu.scala 45:37] + node _T_4344 = bits(_T_4341, 15, 0) @[AmoAlu.scala 45:55] + node _T_4345 = mux(_T_4342, _T_4343, _T_4344) @[AmoAlu.scala 45:24] + node _T_4347 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 46:33] + node _T_4349 = mux(_T_4347, UInt<1>("h00"), _T_4345) @[AmoAlu.scala 47:23] + node _T_4351 = eq(_T_4321, UInt<1>("h01")) @[AmoAlu.scala 48:26] + node _T_4352 = or(_T_4351, _T_4347) @[AmoAlu.scala 48:38] + node _T_4353 = bits(_T_4349, 15, 15) @[AmoAlu.scala 48:85] + node _T_4354 = and(_T_4320, _T_4353) @[AmoAlu.scala 48:76] + node _T_4355 = bits(_T_4354, 0, 0) @[Bitwise.scala 71:15] + node _T_4358 = mux(_T_4355, UInt<48>("h0ffffffffffff"), UInt<48>("h00")) @[Bitwise.scala 71:12] + node _T_4359 = bits(_T_4341, 63, 16) @[AmoAlu.scala 48:98] + node _T_4360 = mux(_T_4352, _T_4358, _T_4359) @[AmoAlu.scala 48:20] + node _T_4361 = cat(_T_4360, _T_4349) @[Cat.scala 30:58] + node _T_4362 = bits(s2_req.addr, 0, 0) @[AmoAlu.scala 45:29] + node _T_4363 = bits(_T_4361, 15, 8) @[AmoAlu.scala 45:37] + node _T_4364 = bits(_T_4361, 7, 0) @[AmoAlu.scala 45:55] + node _T_4365 = mux(_T_4362, _T_4363, _T_4364) @[AmoAlu.scala 45:24] + node _T_4367 = and(UInt<1>("h01"), s2_sc) @[AmoAlu.scala 46:33] + node _T_4369 = mux(_T_4367, UInt<1>("h00"), _T_4365) @[AmoAlu.scala 47:23] + node _T_4371 = eq(_T_4321, UInt<1>("h00")) @[AmoAlu.scala 48:26] + node _T_4372 = or(_T_4371, _T_4367) @[AmoAlu.scala 48:38] + node _T_4373 = bits(_T_4369, 7, 7) @[AmoAlu.scala 48:85] + node _T_4374 = and(_T_4320, _T_4373) @[AmoAlu.scala 48:76] + node _T_4375 = bits(_T_4374, 0, 0) @[Bitwise.scala 71:15] + node _T_4378 = mux(_T_4375, UInt<56>("h0ffffffffffffff"), UInt<56>("h00")) @[Bitwise.scala 71:12] + node _T_4379 = bits(_T_4361, 63, 8) @[AmoAlu.scala 48:98] + node _T_4380 = mux(_T_4372, _T_4378, _T_4379) @[AmoAlu.scala 48:20] + node _T_4381 = cat(_T_4380, _T_4369) @[Cat.scala 30:58] + node _T_4382 = or(_T_4381, s2_sc_fail) @[DCache.scala 463:41] + io.cpu.resp.bits.data <= _T_4382 @[DCache.scala 463:25] + node _T_4383 = bits(s2_req.addr, 2, 2) @[AmoAlu.scala 45:29] + node _T_4384 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 45:37] + node _T_4385 = bits(s2_data_word, 31, 0) @[AmoAlu.scala 45:55] + node _T_4386 = mux(_T_4383, _T_4384, _T_4385) @[AmoAlu.scala 45:24] + node _T_4388 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 46:33] + node _T_4390 = mux(_T_4388, UInt<1>("h00"), _T_4386) @[AmoAlu.scala 47:23] + node _T_4392 = eq(_T_4321, UInt<2>("h02")) @[AmoAlu.scala 48:26] + node _T_4393 = or(_T_4392, _T_4388) @[AmoAlu.scala 48:38] + node _T_4394 = bits(_T_4390, 31, 31) @[AmoAlu.scala 48:85] + node _T_4395 = and(_T_4320, _T_4394) @[AmoAlu.scala 48:76] + node _T_4396 = bits(_T_4395, 0, 0) @[Bitwise.scala 71:15] + node _T_4399 = mux(_T_4396, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_4400 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 48:98] + node _T_4401 = mux(_T_4393, _T_4399, _T_4400) @[AmoAlu.scala 48:20] + node _T_4402 = cat(_T_4401, _T_4390) @[Cat.scala 30:58] + io.cpu.resp.bits.data_word_bypass <= _T_4402 @[DCache.scala 464:37] + io.cpu.resp.bits.store_data <= pstore1_data @[DCache.scala 465:31] + inst AMOALU of AMOALU @[DCache.scala 469:24] + AMOALU.io is invalid + AMOALU.clock <= clock + AMOALU.reset <= reset + AMOALU.io.addr <= pstore1_addr @[DCache.scala 470:20] + AMOALU.io.cmd <= pstore1_cmd @[DCache.scala 471:19] + AMOALU.io.typ <= pstore1_typ @[DCache.scala 472:19] + AMOALU.io.lhs <= s2_data_word @[DCache.scala 473:19] + AMOALU.io.rhs <= pstore1_data @[DCache.scala 474:19] + pstore1_storegen_data <= AMOALU.io.out @[DCache.scala 475:27] + reg flushed : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[DCache.scala 481:20] + reg flushing : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DCache.scala 482:21] + reg value : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[Counter.scala 17:29] + node _T_4406 = and(io.mem.0.a.ready, io.mem.0.a.valid) @[Decoupled.scala 30:37] + node _T_4408 = eq(s2_uncached, UInt<1>("h00")) @[DCache.scala 484:28] + node _T_4409 = and(_T_4406, _T_4408) @[DCache.scala 484:25] + when _T_4409 : @[DCache.scala 484:42] + flushed <= UInt<1>("h00") @[DCache.scala 484:52] + skip @[DCache.scala 484:42] + node _T_4412 = eq(s2_req.cmd, UInt<3>("h05")) @[DCache.scala 485:39] + node _T_4413 = and(s2_valid_masked, _T_4412) @[DCache.scala 485:25] + when _T_4413 : @[DCache.scala 485:56] + node _T_4415 = eq(flushed, UInt<1>("h00")) @[DCache.scala 486:23] + io.cpu.s2_nack <= _T_4415 @[DCache.scala 486:20] + node _T_4417 = eq(flushed, UInt<1>("h00")) @[DCache.scala 487:11] + when _T_4417 : @[DCache.scala 487:21] + node _T_4419 = eq(release_ack_wait, UInt<1>("h00")) @[DCache.scala 488:19] + node _T_4421 = neq(uncachedInFlight[0], UInt<1>("h00")) @[DCache.scala 488:65] + node _T_4423 = eq(_T_4421, UInt<1>("h00")) @[DCache.scala 488:40] + node _T_4424 = and(_T_4419, _T_4423) @[DCache.scala 488:37] + flushing <= _T_4424 @[DCache.scala 488:16] + skip @[DCache.scala 487:21] + skip @[DCache.scala 485:56] + node _T_4425 = and(metaReadArb.io.in[0].ready, metaReadArb.io.in[0].valid) @[Decoupled.scala 30:37] + node _T_4427 = eq(s1_flush_valid, UInt<1>("h00")) @[DCache.scala 491:52] + node _T_4428 = and(_T_4425, _T_4427) @[DCache.scala 491:49] + node _T_4430 = eq(s2_flush_valid, UInt<1>("h00")) @[DCache.scala 491:71] + node _T_4431 = and(_T_4428, _T_4430) @[DCache.scala 491:68] + node _T_4432 = eq(release_state, UInt<3>("h00")) @[DCache.scala 491:104] + node _T_4433 = and(_T_4431, _T_4432) @[DCache.scala 491:87] + node _T_4435 = eq(release_ack_wait, UInt<1>("h00")) @[DCache.scala 491:119] + node _T_4436 = and(_T_4433, _T_4435) @[DCache.scala 491:116] + s1_flush_valid <= _T_4436 @[DCache.scala 491:18] + metaReadArb.io.in[0].valid <= flushing @[DCache.scala 492:30] + metaReadArb.io.in[0].bits.idx <= value @[DCache.scala 493:33] + node _T_4438 = not(UInt<4>("h00")) @[DCache.scala 494:39] + metaReadArb.io.in[0].bits.way_en <= _T_4438 @[DCache.scala 494:36] + when flushing : @[DCache.scala 495:19] + node _T_4439 = shr(value, 6) @[DCache.scala 496:41] + s1_victim_way <= _T_4439 @[DCache.scala 496:19] + when s2_flush_valid : @[DCache.scala 497:27] + node _T_4441 = eq(value, UInt<8>("h0ff")) @[Counter.scala 25:24] + node _T_4443 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_4444 = tail(_T_4443, 1) @[Counter.scala 26:22] + value <= _T_4444 @[Counter.scala 26:13] + when _T_4441 : @[DCache.scala 498:33] + flushed <= UInt<1>("h01") @[DCache.scala 499:17] + skip @[DCache.scala 498:33] + skip @[DCache.scala 497:27] + node _T_4446 = eq(release_state, UInt<3>("h00")) @[DCache.scala 502:36] + node _T_4447 = and(flushed, _T_4446) @[DCache.scala 502:19] + node _T_4449 = eq(release_ack_wait, UInt<1>("h00")) @[DCache.scala 502:51] + node _T_4450 = and(_T_4447, _T_4449) @[DCache.scala 502:48] + when _T_4450 : @[DCache.scala 502:70] + flushing <= UInt<1>("h00") @[DCache.scala 503:16] + skip @[DCache.scala 502:70] + skip @[DCache.scala 495:19] + node _T_4452 = and(io.mem.0.a.ready, io.mem.0.a.valid) @[Decoupled.scala 30:37] + node _T_4454 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4455 = dshl(_T_4454, io.mem.0.a.bits.size) @[package.scala 19:71] + node _T_4456 = bits(_T_4455, 7, 0) @[package.scala 19:76] + node _T_4457 = not(_T_4456) @[package.scala 19:40] + node _T_4458 = shr(_T_4457, 3) @[Edges.scala 198:59] + node _T_4459 = bits(io.mem.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4461 = eq(_T_4459, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4463 = mux(_T_4461, _T_4458, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4465 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4467 = sub(_T_4465, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4468 = asUInt(_T_4467) @[Edges.scala 208:28] + node _T_4469 = tail(_T_4468, 1) @[Edges.scala 208:28] + node _T_4471 = eq(_T_4465, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4473 = eq(_T_4465, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4475 = eq(_T_4463, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4476 = or(_T_4473, _T_4475) @[Edges.scala 210:37] + node _T_4477 = and(_T_4476, _T_4452) @[Edges.scala 211:22] + node _T_4478 = not(_T_4469) @[Edges.scala 212:27] + node _T_4479 = and(_T_4463, _T_4478) @[Edges.scala 212:25] + when _T_4452 : @[Edges.scala 213:17] + node _T_4480 = mux(_T_4471, _T_4463, _T_4469) @[Edges.scala 214:21] + _T_4465 <= _T_4480 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + io.cpu.acquire <= _T_4477 @[DCache.scala 508:18] + node _T_4481 = and(io.mem.0.c.ready, io.mem.0.c.valid) @[Decoupled.scala 30:37] + node _T_4483 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4484 = dshl(_T_4483, io.mem.0.c.bits.size) @[package.scala 19:71] + node _T_4485 = bits(_T_4484, 7, 0) @[package.scala 19:76] + node _T_4486 = not(_T_4485) @[package.scala 19:40] + node _T_4487 = shr(_T_4486, 3) @[Edges.scala 198:59] + node _T_4488 = bits(io.mem.0.c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4490 = mux(_T_4488, _T_4487, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4492 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4494 = sub(_T_4492, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4495 = asUInt(_T_4494) @[Edges.scala 208:28] + node _T_4496 = tail(_T_4495, 1) @[Edges.scala 208:28] + node _T_4498 = eq(_T_4492, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4500 = eq(_T_4492, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4502 = eq(_T_4490, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4503 = or(_T_4500, _T_4502) @[Edges.scala 210:37] + node _T_4504 = and(_T_4503, _T_4481) @[Edges.scala 211:22] + node _T_4505 = not(_T_4496) @[Edges.scala 212:27] + node _T_4506 = and(_T_4490, _T_4505) @[Edges.scala 212:25] + when _T_4481 : @[Edges.scala 213:17] + node _T_4507 = mux(_T_4498, _T_4490, _T_4496) @[Edges.scala 214:21] + _T_4492 <= _T_4507 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + io.cpu.release <= _T_4504 @[DCache.scala 509:18] + + module TLMonitor_31 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[HellaCache.scala 178:14] + node _T_956 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_957 = or(_T_956, reset) @[HellaCache.scala 178:14] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_959 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at HellaCache.scala:178:14)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_961 = eq(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_964 : UInt<1>[1] @[Parameters.scala 228:27] + _T_964 is invalid @[Parameters.scala 228:27] + _T_964[0] <= _T_961 @[Parameters.scala 228:27] + node _T_969 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_970 = dshl(_T_969, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_971 = bits(_T_970, 7, 0) @[package.scala 19:76] + node _T_972 = not(_T_971) @[package.scala 19:40] + node _T_973 = and(io.in[0].a.bits.address, _T_972) @[Edges.scala 17:16] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_977 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_978 = dshl(UInt<1>("h01"), _T_977) @[OneHot.scala 49:12] + node _T_979 = bits(_T_978, 2, 0) @[OneHot.scala 49:37] + node _T_981 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_983 = bits(_T_979, 2, 2) @[package.scala 44:26] + node _T_984 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_986 = eq(_T_984, UInt<1>("h00")) @[package.scala 46:20] + node _T_987 = and(UInt<1>("h01"), _T_986) @[package.scala 49:27] + node _T_988 = and(_T_983, _T_987) @[package.scala 50:38] + node _T_989 = or(_T_981, _T_988) @[package.scala 50:29] + node _T_990 = and(UInt<1>("h01"), _T_984) @[package.scala 49:27] + node _T_991 = and(_T_983, _T_990) @[package.scala 50:38] + node _T_992 = or(_T_981, _T_991) @[package.scala 50:29] + node _T_993 = bits(_T_979, 1, 1) @[package.scala 44:26] + node _T_994 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_996 = eq(_T_994, UInt<1>("h00")) @[package.scala 46:20] + node _T_997 = and(_T_987, _T_996) @[package.scala 49:27] + node _T_998 = and(_T_993, _T_997) @[package.scala 50:38] + node _T_999 = or(_T_989, _T_998) @[package.scala 50:29] + node _T_1000 = and(_T_987, _T_994) @[package.scala 49:27] + node _T_1001 = and(_T_993, _T_1000) @[package.scala 50:38] + node _T_1002 = or(_T_989, _T_1001) @[package.scala 50:29] + node _T_1003 = and(_T_990, _T_996) @[package.scala 49:27] + node _T_1004 = and(_T_993, _T_1003) @[package.scala 50:38] + node _T_1005 = or(_T_992, _T_1004) @[package.scala 50:29] + node _T_1006 = and(_T_990, _T_994) @[package.scala 49:27] + node _T_1007 = and(_T_993, _T_1006) @[package.scala 50:38] + node _T_1008 = or(_T_992, _T_1007) @[package.scala 50:29] + node _T_1009 = bits(_T_979, 0, 0) @[package.scala 44:26] + node _T_1010 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_1012 = eq(_T_1010, UInt<1>("h00")) @[package.scala 46:20] + node _T_1013 = and(_T_997, _T_1012) @[package.scala 49:27] + node _T_1014 = and(_T_1009, _T_1013) @[package.scala 50:38] + node _T_1015 = or(_T_999, _T_1014) @[package.scala 50:29] + node _T_1016 = and(_T_997, _T_1010) @[package.scala 49:27] + node _T_1017 = and(_T_1009, _T_1016) @[package.scala 50:38] + node _T_1018 = or(_T_999, _T_1017) @[package.scala 50:29] + node _T_1019 = and(_T_1000, _T_1012) @[package.scala 49:27] + node _T_1020 = and(_T_1009, _T_1019) @[package.scala 50:38] + node _T_1021 = or(_T_1002, _T_1020) @[package.scala 50:29] + node _T_1022 = and(_T_1000, _T_1010) @[package.scala 49:27] + node _T_1023 = and(_T_1009, _T_1022) @[package.scala 50:38] + node _T_1024 = or(_T_1002, _T_1023) @[package.scala 50:29] + node _T_1025 = and(_T_1003, _T_1012) @[package.scala 49:27] + node _T_1026 = and(_T_1009, _T_1025) @[package.scala 50:38] + node _T_1027 = or(_T_1005, _T_1026) @[package.scala 50:29] + node _T_1028 = and(_T_1003, _T_1010) @[package.scala 49:27] + node _T_1029 = and(_T_1009, _T_1028) @[package.scala 50:38] + node _T_1030 = or(_T_1005, _T_1029) @[package.scala 50:29] + node _T_1031 = and(_T_1006, _T_1012) @[package.scala 49:27] + node _T_1032 = and(_T_1009, _T_1031) @[package.scala 50:38] + node _T_1033 = or(_T_1008, _T_1032) @[package.scala 50:29] + node _T_1034 = and(_T_1006, _T_1010) @[package.scala 49:27] + node _T_1035 = and(_T_1009, _T_1034) @[package.scala 50:38] + node _T_1036 = or(_T_1008, _T_1035) @[package.scala 50:29] + node _T_1037 = cat(_T_1018, _T_1015) @[Cat.scala 30:58] + node _T_1038 = cat(_T_1024, _T_1021) @[Cat.scala 30:58] + node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 30:58] + node _T_1040 = cat(_T_1030, _T_1027) @[Cat.scala 30:58] + node _T_1041 = cat(_T_1036, _T_1033) @[Cat.scala 30:58] + node _T_1042 = cat(_T_1041, _T_1040) @[Cat.scala 30:58] + node _T_1043 = cat(_T_1042, _T_1039) @[Cat.scala 30:58] + node _T_1045 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + when _T_1045 : @[HellaCache.scala 178:14] + node _T_1048 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1050 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1051 = and(_T_1048, _T_1050) @[Parameters.scala 63:37] + node _T_1052 = or(UInt<1>("h00"), _T_1051) @[Parameters.scala 132:31] + node _T_1054 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1055 = cvt(_T_1054) @[Parameters.scala 117:49] + node _T_1057 = and(_T_1055, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1058 = asSInt(_T_1057) @[Parameters.scala 117:52] + node _T_1060 = eq(_T_1058, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1062 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1063 = cvt(_T_1062) @[Parameters.scala 117:49] + node _T_1065 = and(_T_1063, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1066 = asSInt(_T_1065) @[Parameters.scala 117:52] + node _T_1068 = eq(_T_1066, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = or(_T_1060, _T_1068) @[Parameters.scala 133:42] + node _T_1070 = and(_T_1052, _T_1069) @[Parameters.scala 132:56] + node _T_1073 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1075 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1076 = cvt(_T_1075) @[Parameters.scala 117:49] + node _T_1078 = and(_T_1076, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1079 = asSInt(_T_1078) @[Parameters.scala 117:52] + node _T_1081 = eq(_T_1079, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1083 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1084 = cvt(_T_1083) @[Parameters.scala 117:49] + node _T_1086 = and(_T_1084, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1087 = asSInt(_T_1086) @[Parameters.scala 117:52] + node _T_1089 = eq(_T_1087, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1091 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1092 = cvt(_T_1091) @[Parameters.scala 117:49] + node _T_1094 = and(_T_1092, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1095 = asSInt(_T_1094) @[Parameters.scala 117:52] + node _T_1097 = eq(_T_1095, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1099 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1100 = cvt(_T_1099) @[Parameters.scala 117:49] + node _T_1102 = and(_T_1100, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1103 = asSInt(_T_1102) @[Parameters.scala 117:52] + node _T_1105 = eq(_T_1103, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1106 = or(_T_1081, _T_1089) @[Parameters.scala 133:42] + node _T_1107 = or(_T_1106, _T_1097) @[Parameters.scala 133:42] + node _T_1108 = or(_T_1107, _T_1105) @[Parameters.scala 133:42] + node _T_1109 = and(_T_1073, _T_1108) @[Parameters.scala 132:56] + node _T_1111 = or(UInt<1>("h00"), _T_1070) @[Parameters.scala 134:30] + node _T_1112 = or(_T_1111, _T_1109) @[Parameters.scala 134:30] + node _T_1113 = or(_T_1112, reset) @[HellaCache.scala 178:14] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1115 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1116 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1118 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1120 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_1121 = or(_T_1120, reset) @[HellaCache.scala 178:14] + node _T_1123 = eq(_T_1121, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1123 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1124 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1126 = eq(_T_1124, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1126 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1128 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_1129 = or(_T_1128, reset) @[HellaCache.scala 178:14] + node _T_1131 = eq(_T_1129, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1131 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at HellaCache.scala:178:14)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1132 = not(io.in[0].a.bits.mask) @[HellaCache.scala 178:14] + node _T_1134 = eq(_T_1132, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1135 = or(_T_1134, reset) @[HellaCache.scala 178:14] + node _T_1137 = eq(_T_1135, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1137 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1139 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[HellaCache.scala 178:14] + when _T_1139 : @[HellaCache.scala 178:14] + node _T_1142 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1144 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1145 = and(_T_1142, _T_1144) @[Parameters.scala 63:37] + node _T_1146 = or(UInt<1>("h00"), _T_1145) @[Parameters.scala 132:31] + node _T_1148 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1149 = cvt(_T_1148) @[Parameters.scala 117:49] + node _T_1151 = and(_T_1149, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1152 = asSInt(_T_1151) @[Parameters.scala 117:52] + node _T_1154 = eq(_T_1152, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1156 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1157 = cvt(_T_1156) @[Parameters.scala 117:49] + node _T_1159 = and(_T_1157, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1160 = asSInt(_T_1159) @[Parameters.scala 117:52] + node _T_1162 = eq(_T_1160, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1164 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1165 = cvt(_T_1164) @[Parameters.scala 117:49] + node _T_1167 = and(_T_1165, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1168 = asSInt(_T_1167) @[Parameters.scala 117:52] + node _T_1170 = eq(_T_1168, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1172 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1173 = cvt(_T_1172) @[Parameters.scala 117:49] + node _T_1175 = and(_T_1173, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1176 = asSInt(_T_1175) @[Parameters.scala 117:52] + node _T_1178 = eq(_T_1176, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1180 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1181 = cvt(_T_1180) @[Parameters.scala 117:49] + node _T_1183 = and(_T_1181, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1184 = asSInt(_T_1183) @[Parameters.scala 117:52] + node _T_1186 = eq(_T_1184, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1187 = or(_T_1154, _T_1162) @[Parameters.scala 133:42] + node _T_1188 = or(_T_1187, _T_1170) @[Parameters.scala 133:42] + node _T_1189 = or(_T_1188, _T_1178) @[Parameters.scala 133:42] + node _T_1190 = or(_T_1189, _T_1186) @[Parameters.scala 133:42] + node _T_1191 = and(_T_1146, _T_1190) @[Parameters.scala 132:56] + node _T_1194 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1196 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1197 = and(_T_1194, _T_1196) @[Parameters.scala 63:37] + node _T_1198 = or(UInt<1>("h00"), _T_1197) @[Parameters.scala 132:31] + node _T_1200 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1201 = cvt(_T_1200) @[Parameters.scala 117:49] + node _T_1203 = and(_T_1201, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1204 = asSInt(_T_1203) @[Parameters.scala 117:52] + node _T_1206 = eq(_T_1204, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1207 = and(_T_1198, _T_1206) @[Parameters.scala 132:56] + node _T_1209 = or(UInt<1>("h00"), _T_1191) @[Parameters.scala 134:30] + node _T_1210 = or(_T_1209, _T_1207) @[Parameters.scala 134:30] + node _T_1211 = or(_T_1210, reset) @[HellaCache.scala 178:14] + node _T_1213 = eq(_T_1211, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1213 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1214 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1216 = eq(_T_1214, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1216 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1217 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1219 = eq(_T_1217, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1219 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1221 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1222 = or(_T_1221, reset) @[HellaCache.scala 178:14] + node _T_1224 = eq(_T_1222, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1224 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1225 = eq(io.in[0].a.bits.mask, _T_1043) @[HellaCache.scala 178:14] + node _T_1226 = or(_T_1225, reset) @[HellaCache.scala 178:14] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1228 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1230 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1230 : @[HellaCache.scala 178:14] + node _T_1233 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1235 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1236 = and(_T_1233, _T_1235) @[Parameters.scala 63:37] + node _T_1237 = or(UInt<1>("h00"), _T_1236) @[Parameters.scala 132:31] + node _T_1239 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1240 = cvt(_T_1239) @[Parameters.scala 117:49] + node _T_1242 = and(_T_1240, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1243 = asSInt(_T_1242) @[Parameters.scala 117:52] + node _T_1245 = eq(_T_1243, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1247 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1248 = cvt(_T_1247) @[Parameters.scala 117:49] + node _T_1250 = and(_T_1248, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1251 = asSInt(_T_1250) @[Parameters.scala 117:52] + node _T_1253 = eq(_T_1251, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1255 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1256 = cvt(_T_1255) @[Parameters.scala 117:49] + node _T_1258 = and(_T_1256, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1259 = asSInt(_T_1258) @[Parameters.scala 117:52] + node _T_1261 = eq(_T_1259, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1263 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1264 = cvt(_T_1263) @[Parameters.scala 117:49] + node _T_1266 = and(_T_1264, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1267 = asSInt(_T_1266) @[Parameters.scala 117:52] + node _T_1269 = eq(_T_1267, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1271 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1272 = cvt(_T_1271) @[Parameters.scala 117:49] + node _T_1274 = and(_T_1272, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1275 = asSInt(_T_1274) @[Parameters.scala 117:52] + node _T_1277 = eq(_T_1275, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1278 = or(_T_1245, _T_1253) @[Parameters.scala 133:42] + node _T_1279 = or(_T_1278, _T_1261) @[Parameters.scala 133:42] + node _T_1280 = or(_T_1279, _T_1269) @[Parameters.scala 133:42] + node _T_1281 = or(_T_1280, _T_1277) @[Parameters.scala 133:42] + node _T_1282 = and(_T_1237, _T_1281) @[Parameters.scala 132:56] + node _T_1285 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1287 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1288 = and(_T_1285, _T_1287) @[Parameters.scala 63:37] + node _T_1289 = or(UInt<1>("h00"), _T_1288) @[Parameters.scala 132:31] + node _T_1291 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1292 = cvt(_T_1291) @[Parameters.scala 117:49] + node _T_1294 = and(_T_1292, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1295 = asSInt(_T_1294) @[Parameters.scala 117:52] + node _T_1297 = eq(_T_1295, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1298 = and(_T_1289, _T_1297) @[Parameters.scala 132:56] + node _T_1301 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1303 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1304 = cvt(_T_1303) @[Parameters.scala 117:49] + node _T_1306 = and(_T_1304, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1307 = asSInt(_T_1306) @[Parameters.scala 117:52] + node _T_1309 = eq(_T_1307, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1310 = and(_T_1301, _T_1309) @[Parameters.scala 132:56] + node _T_1312 = or(UInt<1>("h00"), _T_1282) @[Parameters.scala 134:30] + node _T_1313 = or(_T_1312, _T_1298) @[Parameters.scala 134:30] + node _T_1314 = or(_T_1313, _T_1310) @[Parameters.scala 134:30] + node _T_1315 = or(_T_1314, reset) @[HellaCache.scala 178:14] + node _T_1317 = eq(_T_1315, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1317 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1318 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1320 = eq(_T_1318, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1320 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1321 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1323 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1325 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1326 = or(_T_1325, reset) @[HellaCache.scala 178:14] + node _T_1328 = eq(_T_1326, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1328 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1329 = eq(io.in[0].a.bits.mask, _T_1043) @[HellaCache.scala 178:14] + node _T_1330 = or(_T_1329, reset) @[HellaCache.scala 178:14] + node _T_1332 = eq(_T_1330, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1332 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1334 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[HellaCache.scala 178:14] + when _T_1334 : @[HellaCache.scala 178:14] + node _T_1337 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1339 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1340 = and(_T_1337, _T_1339) @[Parameters.scala 63:37] + node _T_1341 = or(UInt<1>("h00"), _T_1340) @[Parameters.scala 132:31] + node _T_1343 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1344 = cvt(_T_1343) @[Parameters.scala 117:49] + node _T_1346 = and(_T_1344, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1347 = asSInt(_T_1346) @[Parameters.scala 117:52] + node _T_1349 = eq(_T_1347, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1351 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1352 = cvt(_T_1351) @[Parameters.scala 117:49] + node _T_1354 = and(_T_1352, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1355 = asSInt(_T_1354) @[Parameters.scala 117:52] + node _T_1357 = eq(_T_1355, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1359 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1360 = cvt(_T_1359) @[Parameters.scala 117:49] + node _T_1362 = and(_T_1360, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1363 = asSInt(_T_1362) @[Parameters.scala 117:52] + node _T_1365 = eq(_T_1363, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1367 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1375 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1376 = cvt(_T_1375) @[Parameters.scala 117:49] + node _T_1378 = and(_T_1376, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1379 = asSInt(_T_1378) @[Parameters.scala 117:52] + node _T_1381 = eq(_T_1379, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1382 = or(_T_1349, _T_1357) @[Parameters.scala 133:42] + node _T_1383 = or(_T_1382, _T_1365) @[Parameters.scala 133:42] + node _T_1384 = or(_T_1383, _T_1373) @[Parameters.scala 133:42] + node _T_1385 = or(_T_1384, _T_1381) @[Parameters.scala 133:42] + node _T_1386 = and(_T_1341, _T_1385) @[Parameters.scala 132:56] + node _T_1389 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1391 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1392 = and(_T_1389, _T_1391) @[Parameters.scala 63:37] + node _T_1393 = or(UInt<1>("h00"), _T_1392) @[Parameters.scala 132:31] + node _T_1395 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1396 = cvt(_T_1395) @[Parameters.scala 117:49] + node _T_1398 = and(_T_1396, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1399 = asSInt(_T_1398) @[Parameters.scala 117:52] + node _T_1401 = eq(_T_1399, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1402 = and(_T_1393, _T_1401) @[Parameters.scala 132:56] + node _T_1405 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1407 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1414 = and(_T_1405, _T_1413) @[Parameters.scala 132:56] + node _T_1416 = or(UInt<1>("h00"), _T_1386) @[Parameters.scala 134:30] + node _T_1417 = or(_T_1416, _T_1402) @[Parameters.scala 134:30] + node _T_1418 = or(_T_1417, _T_1414) @[Parameters.scala 134:30] + node _T_1419 = or(_T_1418, reset) @[HellaCache.scala 178:14] + node _T_1421 = eq(_T_1419, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1421 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1422 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1424 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1425 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1427 = eq(_T_1425, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1427 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1429 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1430 = or(_T_1429, reset) @[HellaCache.scala 178:14] + node _T_1432 = eq(_T_1430, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1432 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1433 = not(_T_1043) @[HellaCache.scala 178:14] + node _T_1434 = and(io.in[0].a.bits.mask, _T_1433) @[HellaCache.scala 178:14] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1437 = or(_T_1436, reset) @[HellaCache.scala 178:14] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1439 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1441 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[HellaCache.scala 178:14] + when _T_1441 : @[HellaCache.scala 178:14] + node _T_1444 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1446 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1447 = and(_T_1444, _T_1446) @[Parameters.scala 63:37] + node _T_1448 = or(UInt<1>("h00"), _T_1447) @[Parameters.scala 132:31] + node _T_1450 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1451 = cvt(_T_1450) @[Parameters.scala 117:49] + node _T_1453 = and(_T_1451, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1454 = asSInt(_T_1453) @[Parameters.scala 117:52] + node _T_1456 = eq(_T_1454, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1458 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1459 = cvt(_T_1458) @[Parameters.scala 117:49] + node _T_1461 = and(_T_1459, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1462 = asSInt(_T_1461) @[Parameters.scala 117:52] + node _T_1464 = eq(_T_1462, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1466 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1467 = cvt(_T_1466) @[Parameters.scala 117:49] + node _T_1469 = and(_T_1467, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1470 = asSInt(_T_1469) @[Parameters.scala 117:52] + node _T_1472 = eq(_T_1470, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1473 = or(_T_1456, _T_1464) @[Parameters.scala 133:42] + node _T_1474 = or(_T_1473, _T_1472) @[Parameters.scala 133:42] + node _T_1475 = and(_T_1448, _T_1474) @[Parameters.scala 132:56] + node _T_1478 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1480 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1481 = cvt(_T_1480) @[Parameters.scala 117:49] + node _T_1483 = and(_T_1481, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1484 = asSInt(_T_1483) @[Parameters.scala 117:52] + node _T_1486 = eq(_T_1484, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1488 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1489 = cvt(_T_1488) @[Parameters.scala 117:49] + node _T_1491 = and(_T_1489, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1492 = asSInt(_T_1491) @[Parameters.scala 117:52] + node _T_1494 = eq(_T_1492, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1496 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1497 = cvt(_T_1496) @[Parameters.scala 117:49] + node _T_1499 = and(_T_1497, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1500 = asSInt(_T_1499) @[Parameters.scala 117:52] + node _T_1502 = eq(_T_1500, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1504 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1505 = cvt(_T_1504) @[Parameters.scala 117:49] + node _T_1507 = and(_T_1505, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1508 = asSInt(_T_1507) @[Parameters.scala 117:52] + node _T_1510 = eq(_T_1508, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1511 = or(_T_1486, _T_1494) @[Parameters.scala 133:42] + node _T_1512 = or(_T_1511, _T_1502) @[Parameters.scala 133:42] + node _T_1513 = or(_T_1512, _T_1510) @[Parameters.scala 133:42] + node _T_1514 = and(_T_1478, _T_1513) @[Parameters.scala 132:56] + node _T_1516 = or(UInt<1>("h00"), _T_1475) @[Parameters.scala 134:30] + node _T_1517 = or(_T_1516, _T_1514) @[Parameters.scala 134:30] + node _T_1518 = or(_T_1517, reset) @[HellaCache.scala 178:14] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1520 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1521 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1523 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1524 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1526 = eq(_T_1524, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1526 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1528 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1529 = or(_T_1528, reset) @[HellaCache.scala 178:14] + node _T_1531 = eq(_T_1529, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1531 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at HellaCache.scala:178:14)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1532 = eq(io.in[0].a.bits.mask, _T_1043) @[HellaCache.scala 178:14] + node _T_1533 = or(_T_1532, reset) @[HellaCache.scala 178:14] + node _T_1535 = eq(_T_1533, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1535 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1537 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[HellaCache.scala 178:14] + when _T_1537 : @[HellaCache.scala 178:14] + node _T_1540 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1542 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1543 = and(_T_1540, _T_1542) @[Parameters.scala 63:37] + node _T_1544 = or(UInt<1>("h00"), _T_1543) @[Parameters.scala 132:31] + node _T_1546 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1547 = cvt(_T_1546) @[Parameters.scala 117:49] + node _T_1549 = and(_T_1547, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1550 = asSInt(_T_1549) @[Parameters.scala 117:52] + node _T_1552 = eq(_T_1550, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1554 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1555 = cvt(_T_1554) @[Parameters.scala 117:49] + node _T_1557 = and(_T_1555, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1558 = asSInt(_T_1557) @[Parameters.scala 117:52] + node _T_1560 = eq(_T_1558, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1562 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1563 = cvt(_T_1562) @[Parameters.scala 117:49] + node _T_1565 = and(_T_1563, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1566 = asSInt(_T_1565) @[Parameters.scala 117:52] + node _T_1568 = eq(_T_1566, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1569 = or(_T_1552, _T_1560) @[Parameters.scala 133:42] + node _T_1570 = or(_T_1569, _T_1568) @[Parameters.scala 133:42] + node _T_1571 = and(_T_1544, _T_1570) @[Parameters.scala 132:56] + node _T_1574 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1576 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1577 = cvt(_T_1576) @[Parameters.scala 117:49] + node _T_1579 = and(_T_1577, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1580 = asSInt(_T_1579) @[Parameters.scala 117:52] + node _T_1582 = eq(_T_1580, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1584 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1585 = cvt(_T_1584) @[Parameters.scala 117:49] + node _T_1587 = and(_T_1585, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1588 = asSInt(_T_1587) @[Parameters.scala 117:52] + node _T_1590 = eq(_T_1588, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1592 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1593 = cvt(_T_1592) @[Parameters.scala 117:49] + node _T_1595 = and(_T_1593, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1596 = asSInt(_T_1595) @[Parameters.scala 117:52] + node _T_1598 = eq(_T_1596, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1600 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1601 = cvt(_T_1600) @[Parameters.scala 117:49] + node _T_1603 = and(_T_1601, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1604 = asSInt(_T_1603) @[Parameters.scala 117:52] + node _T_1606 = eq(_T_1604, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1607 = or(_T_1582, _T_1590) @[Parameters.scala 133:42] + node _T_1608 = or(_T_1607, _T_1598) @[Parameters.scala 133:42] + node _T_1609 = or(_T_1608, _T_1606) @[Parameters.scala 133:42] + node _T_1610 = and(_T_1574, _T_1609) @[Parameters.scala 132:56] + node _T_1612 = or(UInt<1>("h00"), _T_1571) @[Parameters.scala 134:30] + node _T_1613 = or(_T_1612, _T_1610) @[Parameters.scala 134:30] + node _T_1614 = or(_T_1613, reset) @[HellaCache.scala 178:14] + node _T_1616 = eq(_T_1614, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1616 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1617 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1619 = eq(_T_1617, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1619 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1620 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1622 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1624 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1625 = or(_T_1624, reset) @[HellaCache.scala 178:14] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1627 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at HellaCache.scala:178:14)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1628 = eq(io.in[0].a.bits.mask, _T_1043) @[HellaCache.scala 178:14] + node _T_1629 = or(_T_1628, reset) @[HellaCache.scala 178:14] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1631 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1633 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[HellaCache.scala 178:14] + when _T_1633 : @[HellaCache.scala 178:14] + node _T_1636 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1638 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1639 = cvt(_T_1638) @[Parameters.scala 117:49] + node _T_1641 = and(_T_1639, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1642 = asSInt(_T_1641) @[Parameters.scala 117:52] + node _T_1644 = eq(_T_1642, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1646 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1647 = cvt(_T_1646) @[Parameters.scala 117:49] + node _T_1649 = and(_T_1647, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1650 = asSInt(_T_1649) @[Parameters.scala 117:52] + node _T_1652 = eq(_T_1650, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1654 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1655 = cvt(_T_1654) @[Parameters.scala 117:49] + node _T_1657 = and(_T_1655, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1658 = asSInt(_T_1657) @[Parameters.scala 117:52] + node _T_1660 = eq(_T_1658, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1662 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1663 = cvt(_T_1662) @[Parameters.scala 117:49] + node _T_1665 = and(_T_1663, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1666 = asSInt(_T_1665) @[Parameters.scala 117:52] + node _T_1668 = eq(_T_1666, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1670 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1671 = cvt(_T_1670) @[Parameters.scala 117:49] + node _T_1673 = and(_T_1671, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1674 = asSInt(_T_1673) @[Parameters.scala 117:52] + node _T_1676 = eq(_T_1674, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1678 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1679 = cvt(_T_1678) @[Parameters.scala 117:49] + node _T_1681 = and(_T_1679, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1682 = asSInt(_T_1681) @[Parameters.scala 117:52] + node _T_1684 = eq(_T_1682, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1685 = or(_T_1644, _T_1652) @[Parameters.scala 133:42] + node _T_1686 = or(_T_1685, _T_1660) @[Parameters.scala 133:42] + node _T_1687 = or(_T_1686, _T_1668) @[Parameters.scala 133:42] + node _T_1688 = or(_T_1687, _T_1676) @[Parameters.scala 133:42] + node _T_1689 = or(_T_1688, _T_1684) @[Parameters.scala 133:42] + node _T_1690 = and(_T_1636, _T_1689) @[Parameters.scala 132:56] + node _T_1692 = or(UInt<1>("h00"), _T_1690) @[Parameters.scala 134:30] + node _T_1693 = or(_T_1692, reset) @[HellaCache.scala 178:14] + node _T_1695 = eq(_T_1693, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1695 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1696 = or(_T_964[0], reset) @[HellaCache.scala 178:14] + node _T_1698 = eq(_T_1696, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1698 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1699 = or(_T_975, reset) @[HellaCache.scala 178:14] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1701 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1702 = eq(io.in[0].a.bits.mask, _T_1043) @[HellaCache.scala 178:14] + node _T_1703 = or(_T_1702, reset) @[HellaCache.scala 178:14] + node _T_1705 = eq(_T_1703, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1705 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + when io.in[0].b.valid : @[HellaCache.scala 178:14] + node _T_1707 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1708 = or(_T_1707, reset) @[HellaCache.scala 178:14] + node _T_1710 = eq(_T_1708, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1710 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at HellaCache.scala:178:14)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1712 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1713 = cvt(_T_1712) @[Parameters.scala 117:49] + node _T_1715 = and(_T_1713, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1716 = asSInt(_T_1715) @[Parameters.scala 117:52] + node _T_1718 = eq(_T_1716, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1720 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1721 = cvt(_T_1720) @[Parameters.scala 117:49] + node _T_1723 = and(_T_1721, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1724 = asSInt(_T_1723) @[Parameters.scala 117:52] + node _T_1726 = eq(_T_1724, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1728 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1729 = cvt(_T_1728) @[Parameters.scala 117:49] + node _T_1731 = and(_T_1729, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1732 = asSInt(_T_1731) @[Parameters.scala 117:52] + node _T_1734 = eq(_T_1732, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1736 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1737 = cvt(_T_1736) @[Parameters.scala 117:49] + node _T_1739 = and(_T_1737, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1740 = asSInt(_T_1739) @[Parameters.scala 117:52] + node _T_1742 = eq(_T_1740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1744 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1745 = cvt(_T_1744) @[Parameters.scala 117:49] + node _T_1747 = and(_T_1745, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1748 = asSInt(_T_1747) @[Parameters.scala 117:52] + node _T_1750 = eq(_T_1748, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1752 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1753 = cvt(_T_1752) @[Parameters.scala 117:49] + node _T_1755 = and(_T_1753, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1756 = asSInt(_T_1755) @[Parameters.scala 117:52] + node _T_1758 = eq(_T_1756, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1760 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1761 = cvt(_T_1760) @[Parameters.scala 117:49] + node _T_1763 = and(_T_1761, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1764 = asSInt(_T_1763) @[Parameters.scala 117:52] + node _T_1766 = eq(_T_1764, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1769 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1769 is invalid @[Parameters.scala 110:36] + _T_1769[0] <= _T_1718 @[Parameters.scala 110:36] + _T_1769[1] <= _T_1726 @[Parameters.scala 110:36] + _T_1769[2] <= _T_1734 @[Parameters.scala 110:36] + _T_1769[3] <= _T_1742 @[Parameters.scala 110:36] + _T_1769[4] <= _T_1750 @[Parameters.scala 110:36] + _T_1769[5] <= _T_1758 @[Parameters.scala 110:36] + _T_1769[6] <= _T_1766 @[Parameters.scala 110:36] + node _T_1779 = or(_T_1769[0], _T_1769[1]) @[Parameters.scala 119:64] + node _T_1780 = or(_T_1779, _T_1769[2]) @[Parameters.scala 119:64] + node _T_1781 = or(_T_1780, _T_1769[3]) @[Parameters.scala 119:64] + node _T_1782 = or(_T_1781, _T_1769[4]) @[Parameters.scala 119:64] + node _T_1783 = or(_T_1782, _T_1769[5]) @[Parameters.scala 119:64] + node _T_1784 = or(_T_1783, _T_1769[6]) @[Parameters.scala 119:64] + node _T_1786 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1787 = dshl(_T_1786, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1788 = bits(_T_1787, 7, 0) @[package.scala 19:76] + node _T_1789 = not(_T_1788) @[package.scala 19:40] + node _T_1790 = and(io.in[0].b.bits.address, _T_1789) @[Edges.scala 17:16] + node _T_1792 = eq(_T_1790, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1794 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1795 = dshl(UInt<1>("h01"), _T_1794) @[OneHot.scala 49:12] + node _T_1796 = bits(_T_1795, 2, 0) @[OneHot.scala 49:37] + node _T_1798 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1800 = bits(_T_1796, 2, 2) @[package.scala 44:26] + node _T_1801 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1803 = eq(_T_1801, UInt<1>("h00")) @[package.scala 46:20] + node _T_1804 = and(UInt<1>("h01"), _T_1803) @[package.scala 49:27] + node _T_1805 = and(_T_1800, _T_1804) @[package.scala 50:38] + node _T_1806 = or(_T_1798, _T_1805) @[package.scala 50:29] + node _T_1807 = and(UInt<1>("h01"), _T_1801) @[package.scala 49:27] + node _T_1808 = and(_T_1800, _T_1807) @[package.scala 50:38] + node _T_1809 = or(_T_1798, _T_1808) @[package.scala 50:29] + node _T_1810 = bits(_T_1796, 1, 1) @[package.scala 44:26] + node _T_1811 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[package.scala 46:20] + node _T_1814 = and(_T_1804, _T_1813) @[package.scala 49:27] + node _T_1815 = and(_T_1810, _T_1814) @[package.scala 50:38] + node _T_1816 = or(_T_1806, _T_1815) @[package.scala 50:29] + node _T_1817 = and(_T_1804, _T_1811) @[package.scala 49:27] + node _T_1818 = and(_T_1810, _T_1817) @[package.scala 50:38] + node _T_1819 = or(_T_1806, _T_1818) @[package.scala 50:29] + node _T_1820 = and(_T_1807, _T_1813) @[package.scala 49:27] + node _T_1821 = and(_T_1810, _T_1820) @[package.scala 50:38] + node _T_1822 = or(_T_1809, _T_1821) @[package.scala 50:29] + node _T_1823 = and(_T_1807, _T_1811) @[package.scala 49:27] + node _T_1824 = and(_T_1810, _T_1823) @[package.scala 50:38] + node _T_1825 = or(_T_1809, _T_1824) @[package.scala 50:29] + node _T_1826 = bits(_T_1796, 0, 0) @[package.scala 44:26] + node _T_1827 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[package.scala 46:20] + node _T_1830 = and(_T_1814, _T_1829) @[package.scala 49:27] + node _T_1831 = and(_T_1826, _T_1830) @[package.scala 50:38] + node _T_1832 = or(_T_1816, _T_1831) @[package.scala 50:29] + node _T_1833 = and(_T_1814, _T_1827) @[package.scala 49:27] + node _T_1834 = and(_T_1826, _T_1833) @[package.scala 50:38] + node _T_1835 = or(_T_1816, _T_1834) @[package.scala 50:29] + node _T_1836 = and(_T_1817, _T_1829) @[package.scala 49:27] + node _T_1837 = and(_T_1826, _T_1836) @[package.scala 50:38] + node _T_1838 = or(_T_1819, _T_1837) @[package.scala 50:29] + node _T_1839 = and(_T_1817, _T_1827) @[package.scala 49:27] + node _T_1840 = and(_T_1826, _T_1839) @[package.scala 50:38] + node _T_1841 = or(_T_1819, _T_1840) @[package.scala 50:29] + node _T_1842 = and(_T_1820, _T_1829) @[package.scala 49:27] + node _T_1843 = and(_T_1826, _T_1842) @[package.scala 50:38] + node _T_1844 = or(_T_1822, _T_1843) @[package.scala 50:29] + node _T_1845 = and(_T_1820, _T_1827) @[package.scala 49:27] + node _T_1846 = and(_T_1826, _T_1845) @[package.scala 50:38] + node _T_1847 = or(_T_1822, _T_1846) @[package.scala 50:29] + node _T_1848 = and(_T_1823, _T_1829) @[package.scala 49:27] + node _T_1849 = and(_T_1826, _T_1848) @[package.scala 50:38] + node _T_1850 = or(_T_1825, _T_1849) @[package.scala 50:29] + node _T_1851 = and(_T_1823, _T_1827) @[package.scala 49:27] + node _T_1852 = and(_T_1826, _T_1851) @[package.scala 50:38] + node _T_1853 = or(_T_1825, _T_1852) @[package.scala 50:29] + node _T_1854 = cat(_T_1835, _T_1832) @[Cat.scala 30:58] + node _T_1855 = cat(_T_1841, _T_1838) @[Cat.scala 30:58] + node _T_1856 = cat(_T_1855, _T_1854) @[Cat.scala 30:58] + node _T_1857 = cat(_T_1847, _T_1844) @[Cat.scala 30:58] + node _T_1858 = cat(_T_1853, _T_1850) @[Cat.scala 30:58] + node _T_1859 = cat(_T_1858, _T_1857) @[Cat.scala 30:58] + node _T_1860 = cat(_T_1859, _T_1856) @[Cat.scala 30:58] + node _T_1862 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + when _T_1862 : @[HellaCache.scala 178:14] + node _T_1864 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1866 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1867 = and(_T_1864, _T_1866) @[Parameters.scala 63:37] + node _T_1868 = or(_T_1867, reset) @[HellaCache.scala 178:14] + node _T_1870 = eq(_T_1868, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1870 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1871 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1873 = eq(_T_1871, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1873 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1875 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_1876 = or(_T_1875, reset) @[HellaCache.scala 178:14] + node _T_1878 = eq(_T_1876, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1878 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1879 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1881 = eq(_T_1879, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1881 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1883 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1884 = or(_T_1883, reset) @[HellaCache.scala 178:14] + node _T_1886 = eq(_T_1884, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1886 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at HellaCache.scala:178:14)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1887 = not(io.in[0].b.bits.mask) @[HellaCache.scala 178:14] + node _T_1889 = eq(_T_1887, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1890 = or(_T_1889, reset) @[HellaCache.scala 178:14] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1892 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1894 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[HellaCache.scala 178:14] + when _T_1894 : @[HellaCache.scala 178:14] + node _T_1896 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_1898 = eq(_T_1896, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1898 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1899 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1901 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1902 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1904 = eq(_T_1902, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1904 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1906 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1907 = or(_T_1906, reset) @[HellaCache.scala 178:14] + node _T_1909 = eq(_T_1907, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1909 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1910 = eq(io.in[0].b.bits.mask, _T_1860) @[HellaCache.scala 178:14] + node _T_1911 = or(_T_1910, reset) @[HellaCache.scala 178:14] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1913 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1915 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1915 : @[HellaCache.scala 178:14] + node _T_1917 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_1919 = eq(_T_1917, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1919 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1920 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1922 = eq(_T_1920, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1922 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1923 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1925 = eq(_T_1923, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1925 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1927 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1928 = or(_T_1927, reset) @[HellaCache.scala 178:14] + node _T_1930 = eq(_T_1928, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1930 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1931 = eq(io.in[0].b.bits.mask, _T_1860) @[HellaCache.scala 178:14] + node _T_1932 = or(_T_1931, reset) @[HellaCache.scala 178:14] + node _T_1934 = eq(_T_1932, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1934 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1936 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[HellaCache.scala 178:14] + when _T_1936 : @[HellaCache.scala 178:14] + node _T_1938 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1940 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1941 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1943 = eq(_T_1941, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1943 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1944 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1946 = eq(_T_1944, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1946 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1948 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1949 = or(_T_1948, reset) @[HellaCache.scala 178:14] + node _T_1951 = eq(_T_1949, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1951 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1952 = not(_T_1860) @[HellaCache.scala 178:14] + node _T_1953 = and(io.in[0].b.bits.mask, _T_1952) @[HellaCache.scala 178:14] + node _T_1955 = eq(_T_1953, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_1956 = or(_T_1955, reset) @[HellaCache.scala 178:14] + node _T_1958 = eq(_T_1956, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1958 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1960 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[HellaCache.scala 178:14] + when _T_1960 : @[HellaCache.scala 178:14] + node _T_1962 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_1964 = eq(_T_1962, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1964 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1965 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1967 = eq(_T_1965, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1967 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1968 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1970 = eq(_T_1968, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1970 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1972 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1973 = or(_T_1972, reset) @[HellaCache.scala 178:14] + node _T_1975 = eq(_T_1973, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1975 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at HellaCache.scala:178:14)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1976 = eq(io.in[0].b.bits.mask, _T_1860) @[HellaCache.scala 178:14] + node _T_1977 = or(_T_1976, reset) @[HellaCache.scala 178:14] + node _T_1979 = eq(_T_1977, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1979 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1981 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[HellaCache.scala 178:14] + when _T_1981 : @[HellaCache.scala 178:14] + node _T_1983 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1985 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1986 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1988 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1989 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_1991 = eq(_T_1989, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1991 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1993 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1994 = or(_T_1993, reset) @[HellaCache.scala 178:14] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_1996 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at HellaCache.scala:178:14)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_1997 = eq(io.in[0].b.bits.mask, _T_1860) @[HellaCache.scala 178:14] + node _T_1998 = or(_T_1997, reset) @[HellaCache.scala 178:14] + node _T_2000 = eq(_T_1998, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2000 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2002 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[HellaCache.scala 178:14] + when _T_2002 : @[HellaCache.scala 178:14] + node _T_2004 = or(UInt<1>("h00"), reset) @[HellaCache.scala 178:14] + node _T_2006 = eq(_T_2004, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2006 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at HellaCache.scala:178:14)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2007 = or(_T_1784, reset) @[HellaCache.scala 178:14] + node _T_2009 = eq(_T_2007, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2009 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2010 = or(_T_1792, reset) @[HellaCache.scala 178:14] + node _T_2012 = eq(_T_2010, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2012 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2013 = eq(io.in[0].b.bits.mask, _T_1860) @[HellaCache.scala 178:14] + node _T_2014 = or(_T_2013, reset) @[HellaCache.scala 178:14] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2016 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at HellaCache.scala:178:14)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + when io.in[0].c.valid : @[HellaCache.scala 178:14] + node _T_2018 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_2019 = or(_T_2018, reset) @[HellaCache.scala 178:14] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2021 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at HellaCache.scala:178:14)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2023 = eq(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_2026 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2026 is invalid @[Parameters.scala 228:27] + _T_2026[0] <= _T_2023 @[Parameters.scala 228:27] + node _T_2031 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2032 = dshl(_T_2031, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2033 = bits(_T_2032, 7, 0) @[package.scala 19:76] + node _T_2034 = not(_T_2033) @[package.scala 19:40] + node _T_2035 = and(io.in[0].c.bits.address, _T_2034) @[Edges.scala 17:16] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2039 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_2040 = cvt(_T_2039) @[Parameters.scala 117:49] + node _T_2042 = and(_T_2040, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_2043 = asSInt(_T_2042) @[Parameters.scala 117:52] + node _T_2045 = eq(_T_2043, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2047 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2048 = cvt(_T_2047) @[Parameters.scala 117:49] + node _T_2050 = and(_T_2048, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2051 = asSInt(_T_2050) @[Parameters.scala 117:52] + node _T_2053 = eq(_T_2051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2055 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2056 = cvt(_T_2055) @[Parameters.scala 117:49] + node _T_2058 = and(_T_2056, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_2059 = asSInt(_T_2058) @[Parameters.scala 117:52] + node _T_2061 = eq(_T_2059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2063 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2064 = cvt(_T_2063) @[Parameters.scala 117:49] + node _T_2066 = and(_T_2064, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2067 = asSInt(_T_2066) @[Parameters.scala 117:52] + node _T_2069 = eq(_T_2067, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2071 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2072 = cvt(_T_2071) @[Parameters.scala 117:49] + node _T_2074 = and(_T_2072, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2075 = asSInt(_T_2074) @[Parameters.scala 117:52] + node _T_2077 = eq(_T_2075, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2079 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2080 = cvt(_T_2079) @[Parameters.scala 117:49] + node _T_2082 = and(_T_2080, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2083 = asSInt(_T_2082) @[Parameters.scala 117:52] + node _T_2085 = eq(_T_2083, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2087 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2088 = cvt(_T_2087) @[Parameters.scala 117:49] + node _T_2090 = and(_T_2088, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2091 = asSInt(_T_2090) @[Parameters.scala 117:52] + node _T_2093 = eq(_T_2091, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_2096 : UInt<1>[7] @[Parameters.scala 110:36] + _T_2096 is invalid @[Parameters.scala 110:36] + _T_2096[0] <= _T_2045 @[Parameters.scala 110:36] + _T_2096[1] <= _T_2053 @[Parameters.scala 110:36] + _T_2096[2] <= _T_2061 @[Parameters.scala 110:36] + _T_2096[3] <= _T_2069 @[Parameters.scala 110:36] + _T_2096[4] <= _T_2077 @[Parameters.scala 110:36] + _T_2096[5] <= _T_2085 @[Parameters.scala 110:36] + _T_2096[6] <= _T_2093 @[Parameters.scala 110:36] + node _T_2106 = or(_T_2096[0], _T_2096[1]) @[Parameters.scala 119:64] + node _T_2107 = or(_T_2106, _T_2096[2]) @[Parameters.scala 119:64] + node _T_2108 = or(_T_2107, _T_2096[3]) @[Parameters.scala 119:64] + node _T_2109 = or(_T_2108, _T_2096[4]) @[Parameters.scala 119:64] + node _T_2110 = or(_T_2109, _T_2096[5]) @[Parameters.scala 119:64] + node _T_2111 = or(_T_2110, _T_2096[6]) @[Parameters.scala 119:64] + node _T_2113 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[HellaCache.scala 178:14] + when _T_2113 : @[HellaCache.scala 178:14] + node _T_2114 = or(_T_2111, reset) @[HellaCache.scala 178:14] + node _T_2116 = eq(_T_2114, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2116 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2117 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2119 = eq(_T_2117, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2119 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2121 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2122 = or(_T_2121, reset) @[HellaCache.scala 178:14] + node _T_2124 = eq(_T_2122, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2124 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2125 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2127 = eq(_T_2125, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2127 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2129 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2130 = or(_T_2129, reset) @[HellaCache.scala 178:14] + node _T_2132 = eq(_T_2130, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2132 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at HellaCache.scala:178:14)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2134 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2135 = or(_T_2134, reset) @[HellaCache.scala 178:14] + node _T_2137 = eq(_T_2135, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2137 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2139 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[HellaCache.scala 178:14] + when _T_2139 : @[HellaCache.scala 178:14] + node _T_2140 = or(_T_2111, reset) @[HellaCache.scala 178:14] + node _T_2142 = eq(_T_2140, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2142 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2143 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2145 = eq(_T_2143, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2145 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2147 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2148 = or(_T_2147, reset) @[HellaCache.scala 178:14] + node _T_2150 = eq(_T_2148, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2150 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2151 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2153 = eq(_T_2151, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2153 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2155 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2156 = or(_T_2155, reset) @[HellaCache.scala 178:14] + node _T_2158 = eq(_T_2156, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2158 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at HellaCache.scala:178:14)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2160 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2161 = or(_T_2160, reset) @[HellaCache.scala 178:14] + node _T_2163 = eq(_T_2161, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2163 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2165 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + when _T_2165 : @[HellaCache.scala 178:14] + node _T_2168 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2170 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2171 = and(_T_2168, _T_2170) @[Parameters.scala 63:37] + node _T_2172 = or(UInt<1>("h00"), _T_2171) @[Parameters.scala 132:31] + node _T_2174 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2175 = cvt(_T_2174) @[Parameters.scala 117:49] + node _T_2177 = and(_T_2175, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2178 = asSInt(_T_2177) @[Parameters.scala 117:52] + node _T_2180 = eq(_T_2178, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2182 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2183 = cvt(_T_2182) @[Parameters.scala 117:49] + node _T_2185 = and(_T_2183, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2186 = asSInt(_T_2185) @[Parameters.scala 117:52] + node _T_2188 = eq(_T_2186, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2189 = or(_T_2180, _T_2188) @[Parameters.scala 133:42] + node _T_2190 = and(_T_2172, _T_2189) @[Parameters.scala 132:56] + node _T_2193 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2195 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2196 = cvt(_T_2195) @[Parameters.scala 117:49] + node _T_2198 = and(_T_2196, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2199 = asSInt(_T_2198) @[Parameters.scala 117:52] + node _T_2201 = eq(_T_2199, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2203 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2204 = cvt(_T_2203) @[Parameters.scala 117:49] + node _T_2206 = and(_T_2204, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2207 = asSInt(_T_2206) @[Parameters.scala 117:52] + node _T_2209 = eq(_T_2207, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2211 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2212 = cvt(_T_2211) @[Parameters.scala 117:49] + node _T_2214 = and(_T_2212, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2215 = asSInt(_T_2214) @[Parameters.scala 117:52] + node _T_2217 = eq(_T_2215, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2219 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2220 = cvt(_T_2219) @[Parameters.scala 117:49] + node _T_2222 = and(_T_2220, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2223 = asSInt(_T_2222) @[Parameters.scala 117:52] + node _T_2225 = eq(_T_2223, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2226 = or(_T_2201, _T_2209) @[Parameters.scala 133:42] + node _T_2227 = or(_T_2226, _T_2217) @[Parameters.scala 133:42] + node _T_2228 = or(_T_2227, _T_2225) @[Parameters.scala 133:42] + node _T_2229 = and(_T_2193, _T_2228) @[Parameters.scala 132:56] + node _T_2231 = or(UInt<1>("h00"), _T_2190) @[Parameters.scala 134:30] + node _T_2232 = or(_T_2231, _T_2229) @[Parameters.scala 134:30] + node _T_2233 = or(_T_2232, reset) @[HellaCache.scala 178:14] + node _T_2235 = eq(_T_2233, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2235 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2236 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2238 = eq(_T_2236, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2238 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2240 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2241 = or(_T_2240, reset) @[HellaCache.scala 178:14] + node _T_2243 = eq(_T_2241, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2243 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2244 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2246 = eq(_T_2244, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2246 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2248 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2249 = or(_T_2248, reset) @[HellaCache.scala 178:14] + node _T_2251 = eq(_T_2249, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2251 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at HellaCache.scala:178:14)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2253 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2254 = or(_T_2253, reset) @[HellaCache.scala 178:14] + node _T_2256 = eq(_T_2254, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2256 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2258 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[HellaCache.scala 178:14] + when _T_2258 : @[HellaCache.scala 178:14] + node _T_2261 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2263 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2264 = and(_T_2261, _T_2263) @[Parameters.scala 63:37] + node _T_2265 = or(UInt<1>("h00"), _T_2264) @[Parameters.scala 132:31] + node _T_2267 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2268 = cvt(_T_2267) @[Parameters.scala 117:49] + node _T_2270 = and(_T_2268, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2271 = asSInt(_T_2270) @[Parameters.scala 117:52] + node _T_2273 = eq(_T_2271, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2275 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2276 = cvt(_T_2275) @[Parameters.scala 117:49] + node _T_2278 = and(_T_2276, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2279 = asSInt(_T_2278) @[Parameters.scala 117:52] + node _T_2281 = eq(_T_2279, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2282 = or(_T_2273, _T_2281) @[Parameters.scala 133:42] + node _T_2283 = and(_T_2265, _T_2282) @[Parameters.scala 132:56] + node _T_2286 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2288 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2289 = cvt(_T_2288) @[Parameters.scala 117:49] + node _T_2291 = and(_T_2289, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2292 = asSInt(_T_2291) @[Parameters.scala 117:52] + node _T_2294 = eq(_T_2292, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2296 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2297 = cvt(_T_2296) @[Parameters.scala 117:49] + node _T_2299 = and(_T_2297, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2300 = asSInt(_T_2299) @[Parameters.scala 117:52] + node _T_2302 = eq(_T_2300, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2304 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2305 = cvt(_T_2304) @[Parameters.scala 117:49] + node _T_2307 = and(_T_2305, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2308 = asSInt(_T_2307) @[Parameters.scala 117:52] + node _T_2310 = eq(_T_2308, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2312 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2313 = cvt(_T_2312) @[Parameters.scala 117:49] + node _T_2315 = and(_T_2313, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2316 = asSInt(_T_2315) @[Parameters.scala 117:52] + node _T_2318 = eq(_T_2316, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2319 = or(_T_2294, _T_2302) @[Parameters.scala 133:42] + node _T_2320 = or(_T_2319, _T_2310) @[Parameters.scala 133:42] + node _T_2321 = or(_T_2320, _T_2318) @[Parameters.scala 133:42] + node _T_2322 = and(_T_2286, _T_2321) @[Parameters.scala 132:56] + node _T_2324 = or(UInt<1>("h00"), _T_2283) @[Parameters.scala 134:30] + node _T_2325 = or(_T_2324, _T_2322) @[Parameters.scala 134:30] + node _T_2326 = or(_T_2325, reset) @[HellaCache.scala 178:14] + node _T_2328 = eq(_T_2326, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2328 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at HellaCache.scala:178:14)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2329 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2331 = eq(_T_2329, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2331 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2333 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2334 = or(_T_2333, reset) @[HellaCache.scala 178:14] + node _T_2336 = eq(_T_2334, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2336 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2337 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2339 = eq(_T_2337, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2339 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2341 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2342 = or(_T_2341, reset) @[HellaCache.scala 178:14] + node _T_2344 = eq(_T_2342, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2344 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at HellaCache.scala:178:14)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2346 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2347 = or(_T_2346, reset) @[HellaCache.scala 178:14] + node _T_2349 = eq(_T_2347, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2349 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2351 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2351 : @[HellaCache.scala 178:14] + node _T_2352 = or(_T_2111, reset) @[HellaCache.scala 178:14] + node _T_2354 = eq(_T_2352, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2354 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2355 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2357 = eq(_T_2355, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2357 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2358 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2360 = eq(_T_2358, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2360 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2362 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2363 = or(_T_2362, reset) @[HellaCache.scala 178:14] + node _T_2365 = eq(_T_2363, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2365 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2367 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[HellaCache.scala 178:14] + when _T_2367 : @[HellaCache.scala 178:14] + node _T_2368 = or(_T_2111, reset) @[HellaCache.scala 178:14] + node _T_2370 = eq(_T_2368, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2370 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2371 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2373 = eq(_T_2371, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2373 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2374 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2376 = eq(_T_2374, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2376 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2378 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2379 = or(_T_2378, reset) @[HellaCache.scala 178:14] + node _T_2381 = eq(_T_2379, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2381 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2383 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[HellaCache.scala 178:14] + when _T_2383 : @[HellaCache.scala 178:14] + node _T_2384 = or(_T_2111, reset) @[HellaCache.scala 178:14] + node _T_2386 = eq(_T_2384, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2386 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at HellaCache.scala:178:14)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2387 = or(_T_2026[0], reset) @[HellaCache.scala 178:14] + node _T_2389 = eq(_T_2387, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2389 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2390 = or(_T_2037, reset) @[HellaCache.scala 178:14] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2392 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2394 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2395 = or(_T_2394, reset) @[HellaCache.scala 178:14] + node _T_2397 = eq(_T_2395, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2397 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2399 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2400 = or(_T_2399, reset) @[HellaCache.scala 178:14] + node _T_2402 = eq(_T_2400, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2402 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + when io.in[0].d.valid : @[HellaCache.scala 178:14] + node _T_2404 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2405 = or(_T_2404, reset) @[HellaCache.scala 178:14] + node _T_2407 = eq(_T_2405, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2407 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at HellaCache.scala:178:14)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2409 = eq(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_2412 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2412 is invalid @[Parameters.scala 228:27] + _T_2412[0] <= _T_2409 @[Parameters.scala 228:27] + node _T_2417 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2418 = dshl(_T_2417, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2419 = bits(_T_2418, 7, 0) @[package.scala 19:76] + node _T_2420 = not(_T_2419) @[package.scala 19:40] + node _T_2421 = and(io.in[0].d.bits.addr_lo, _T_2420) @[Edges.scala 17:16] + node _T_2423 = eq(_T_2421, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2425 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[HellaCache.scala 178:14] + node _T_2427 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + when _T_2427 : @[HellaCache.scala 178:14] + node _T_2428 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2430 = eq(_T_2428, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2430 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2431 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2433 = eq(_T_2431, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2433 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2434 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2436 = eq(_T_2434, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2436 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2438 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2439 = or(_T_2438, reset) @[HellaCache.scala 178:14] + node _T_2441 = eq(_T_2439, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2441 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2443 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2444 = or(_T_2443, reset) @[HellaCache.scala 178:14] + node _T_2446 = eq(_T_2444, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2446 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2448 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2449 = or(_T_2448, reset) @[HellaCache.scala 178:14] + node _T_2451 = eq(_T_2449, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2451 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2453 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[HellaCache.scala 178:14] + when _T_2453 : @[HellaCache.scala 178:14] + node _T_2454 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2456 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2457 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2459 = eq(_T_2457, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2459 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2460 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2462 = eq(_T_2460, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2462 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2464 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2465 = or(_T_2464, reset) @[HellaCache.scala 178:14] + node _T_2467 = eq(_T_2465, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2467 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2469 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2470 = or(_T_2469, reset) @[HellaCache.scala 178:14] + node _T_2472 = eq(_T_2470, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2472 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at HellaCache.scala:178:14)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2474 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[HellaCache.scala 178:14] + when _T_2474 : @[HellaCache.scala 178:14] + node _T_2475 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2477 = eq(_T_2475, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2477 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2478 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2480 = eq(_T_2478, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2480 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2481 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2483 = eq(_T_2481, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2483 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2485 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[HellaCache.scala 178:14] + node _T_2486 = or(_T_2485, reset) @[HellaCache.scala 178:14] + node _T_2488 = eq(_T_2486, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2488 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at HellaCache.scala:178:14)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2490 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2491 = or(_T_2490, reset) @[HellaCache.scala 178:14] + node _T_2493 = eq(_T_2491, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2493 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at HellaCache.scala:178:14)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2495 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2495 : @[HellaCache.scala 178:14] + node _T_2496 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2498 = eq(_T_2496, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2498 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2499 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2501 = eq(_T_2499, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2501 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2502 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2504 = eq(_T_2502, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2504 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2506 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2507 = or(_T_2506, reset) @[HellaCache.scala 178:14] + node _T_2509 = eq(_T_2507, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2509 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2511 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[HellaCache.scala 178:14] + when _T_2511 : @[HellaCache.scala 178:14] + node _T_2512 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2514 = eq(_T_2512, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2514 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2515 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2517 = eq(_T_2515, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2517 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2518 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2520 = eq(_T_2518, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2520 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2522 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2523 = or(_T_2522, reset) @[HellaCache.scala 178:14] + node _T_2525 = eq(_T_2523, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2525 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2527 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[HellaCache.scala 178:14] + when _T_2527 : @[HellaCache.scala 178:14] + node _T_2528 = or(_T_2412[0], reset) @[HellaCache.scala 178:14] + node _T_2530 = eq(_T_2528, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2530 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2531 = or(_T_2423, reset) @[HellaCache.scala 178:14] + node _T_2533 = eq(_T_2531, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2533 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at HellaCache.scala:178:14)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2534 = or(_T_2425, reset) @[HellaCache.scala 178:14] + node _T_2536 = eq(_T_2534, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2536 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2538 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2539 = or(_T_2538, reset) @[HellaCache.scala 178:14] + node _T_2541 = eq(_T_2539, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2541 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at HellaCache.scala:178:14)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2543 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2544 = or(_T_2543, reset) @[HellaCache.scala 178:14] + node _T_2546 = eq(_T_2544, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2546 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at HellaCache.scala:178:14)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + when io.in[0].e.valid : @[HellaCache.scala 178:14] + node _T_2548 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[HellaCache.scala 178:14] + node _T_2549 = or(_T_2548, reset) @[HellaCache.scala 178:14] + node _T_2551 = eq(_T_2549, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2551 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2552 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2554 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2555 = dshl(_T_2554, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2556 = bits(_T_2555, 7, 0) @[package.scala 19:76] + node _T_2557 = not(_T_2556) @[package.scala 19:40] + node _T_2558 = shr(_T_2557, 3) @[Edges.scala 198:59] + node _T_2559 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2561 = eq(_T_2559, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2563 = mux(_T_2561, _T_2558, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2565 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2567 = sub(_T_2565, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2568 = asUInt(_T_2567) @[Edges.scala 208:28] + node _T_2569 = tail(_T_2568, 1) @[Edges.scala 208:28] + node _T_2571 = eq(_T_2565, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2573 = eq(_T_2565, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2575 = eq(_T_2563, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2576 = or(_T_2573, _T_2575) @[Edges.scala 210:37] + node _T_2577 = and(_T_2576, _T_2552) @[Edges.scala 211:22] + node _T_2578 = not(_T_2569) @[Edges.scala 212:27] + node _T_2579 = and(_T_2563, _T_2578) @[Edges.scala 212:25] + when _T_2552 : @[Edges.scala 213:17] + node _T_2580 = mux(_T_2571, _T_2563, _T_2569) @[Edges.scala 214:21] + _T_2565 <= _T_2580 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2582 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2584 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2586 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2588 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2590 : UInt, clock @[HellaCache.scala 178:14] + node _T_2592 = eq(_T_2571, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2593 = and(io.in[0].a.valid, _T_2592) @[HellaCache.scala 178:14] + when _T_2593 : @[HellaCache.scala 178:14] + node _T_2594 = eq(io.in[0].a.bits.opcode, _T_2582) @[HellaCache.scala 178:14] + node _T_2595 = or(_T_2594, reset) @[HellaCache.scala 178:14] + node _T_2597 = eq(_T_2595, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2597 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2598 = eq(io.in[0].a.bits.param, _T_2584) @[HellaCache.scala 178:14] + node _T_2599 = or(_T_2598, reset) @[HellaCache.scala 178:14] + node _T_2601 = eq(_T_2599, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2601 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2602 = eq(io.in[0].a.bits.size, _T_2586) @[HellaCache.scala 178:14] + node _T_2603 = or(_T_2602, reset) @[HellaCache.scala 178:14] + node _T_2605 = eq(_T_2603, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2605 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2606 = eq(io.in[0].a.bits.source, _T_2588) @[HellaCache.scala 178:14] + node _T_2607 = or(_T_2606, reset) @[HellaCache.scala 178:14] + node _T_2609 = eq(_T_2607, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2609 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2610 = eq(io.in[0].a.bits.address, _T_2590) @[HellaCache.scala 178:14] + node _T_2611 = or(_T_2610, reset) @[HellaCache.scala 178:14] + node _T_2613 = eq(_T_2611, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2613 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2614 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2615 = and(_T_2614, _T_2571) @[HellaCache.scala 178:14] + when _T_2615 : @[HellaCache.scala 178:14] + _T_2582 <= io.in[0].a.bits.opcode @[HellaCache.scala 178:14] + _T_2584 <= io.in[0].a.bits.param @[HellaCache.scala 178:14] + _T_2586 <= io.in[0].a.bits.size @[HellaCache.scala 178:14] + _T_2588 <= io.in[0].a.bits.source @[HellaCache.scala 178:14] + _T_2590 <= io.in[0].a.bits.address @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2616 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2618 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2619 = dshl(_T_2618, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2620 = bits(_T_2619, 7, 0) @[package.scala 19:76] + node _T_2621 = not(_T_2620) @[package.scala 19:40] + node _T_2622 = shr(_T_2621, 3) @[Edges.scala 198:59] + node _T_2623 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2625 = eq(_T_2623, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2628 = mux(UInt<1>("h00"), _T_2622, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2630 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2632 = sub(_T_2630, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2633 = asUInt(_T_2632) @[Edges.scala 208:28] + node _T_2634 = tail(_T_2633, 1) @[Edges.scala 208:28] + node _T_2636 = eq(_T_2630, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2638 = eq(_T_2630, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2640 = eq(_T_2628, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2641 = or(_T_2638, _T_2640) @[Edges.scala 210:37] + node _T_2642 = and(_T_2641, _T_2616) @[Edges.scala 211:22] + node _T_2643 = not(_T_2634) @[Edges.scala 212:27] + node _T_2644 = and(_T_2628, _T_2643) @[Edges.scala 212:25] + when _T_2616 : @[Edges.scala 213:17] + node _T_2645 = mux(_T_2636, _T_2628, _T_2634) @[Edges.scala 214:21] + _T_2630 <= _T_2645 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2647 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2649 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2651 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2653 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2655 : UInt, clock @[HellaCache.scala 178:14] + node _T_2657 = eq(_T_2636, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2658 = and(io.in[0].b.valid, _T_2657) @[HellaCache.scala 178:14] + when _T_2658 : @[HellaCache.scala 178:14] + node _T_2659 = eq(io.in[0].b.bits.opcode, _T_2647) @[HellaCache.scala 178:14] + node _T_2660 = or(_T_2659, reset) @[HellaCache.scala 178:14] + node _T_2662 = eq(_T_2660, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2662 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2663 = eq(io.in[0].b.bits.param, _T_2649) @[HellaCache.scala 178:14] + node _T_2664 = or(_T_2663, reset) @[HellaCache.scala 178:14] + node _T_2666 = eq(_T_2664, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2666 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2667 = eq(io.in[0].b.bits.size, _T_2651) @[HellaCache.scala 178:14] + node _T_2668 = or(_T_2667, reset) @[HellaCache.scala 178:14] + node _T_2670 = eq(_T_2668, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2670 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2671 = eq(io.in[0].b.bits.source, _T_2653) @[HellaCache.scala 178:14] + node _T_2672 = or(_T_2671, reset) @[HellaCache.scala 178:14] + node _T_2674 = eq(_T_2672, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2674 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2675 = eq(io.in[0].b.bits.address, _T_2655) @[HellaCache.scala 178:14] + node _T_2676 = or(_T_2675, reset) @[HellaCache.scala 178:14] + node _T_2678 = eq(_T_2676, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2678 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2679 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2680 = and(_T_2679, _T_2636) @[HellaCache.scala 178:14] + when _T_2680 : @[HellaCache.scala 178:14] + _T_2647 <= io.in[0].b.bits.opcode @[HellaCache.scala 178:14] + _T_2649 <= io.in[0].b.bits.param @[HellaCache.scala 178:14] + _T_2651 <= io.in[0].b.bits.size @[HellaCache.scala 178:14] + _T_2653 <= io.in[0].b.bits.source @[HellaCache.scala 178:14] + _T_2655 <= io.in[0].b.bits.address @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2681 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2683 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2684 = dshl(_T_2683, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2685 = bits(_T_2684, 7, 0) @[package.scala 19:76] + node _T_2686 = not(_T_2685) @[package.scala 19:40] + node _T_2687 = shr(_T_2686, 3) @[Edges.scala 198:59] + node _T_2688 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2690 = mux(_T_2688, _T_2687, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2692 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2694 = sub(_T_2692, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2695 = asUInt(_T_2694) @[Edges.scala 208:28] + node _T_2696 = tail(_T_2695, 1) @[Edges.scala 208:28] + node _T_2698 = eq(_T_2692, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2700 = eq(_T_2692, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2702 = eq(_T_2690, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2703 = or(_T_2700, _T_2702) @[Edges.scala 210:37] + node _T_2704 = and(_T_2703, _T_2681) @[Edges.scala 211:22] + node _T_2705 = not(_T_2696) @[Edges.scala 212:27] + node _T_2706 = and(_T_2690, _T_2705) @[Edges.scala 212:25] + when _T_2681 : @[Edges.scala 213:17] + node _T_2707 = mux(_T_2698, _T_2690, _T_2696) @[Edges.scala 214:21] + _T_2692 <= _T_2707 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2709 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2711 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2713 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2715 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2717 : UInt, clock @[HellaCache.scala 178:14] + node _T_2719 = eq(_T_2698, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2720 = and(io.in[0].c.valid, _T_2719) @[HellaCache.scala 178:14] + when _T_2720 : @[HellaCache.scala 178:14] + node _T_2721 = eq(io.in[0].c.bits.opcode, _T_2709) @[HellaCache.scala 178:14] + node _T_2722 = or(_T_2721, reset) @[HellaCache.scala 178:14] + node _T_2724 = eq(_T_2722, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2724 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2725 = eq(io.in[0].c.bits.param, _T_2711) @[HellaCache.scala 178:14] + node _T_2726 = or(_T_2725, reset) @[HellaCache.scala 178:14] + node _T_2728 = eq(_T_2726, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2728 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2729 = eq(io.in[0].c.bits.size, _T_2713) @[HellaCache.scala 178:14] + node _T_2730 = or(_T_2729, reset) @[HellaCache.scala 178:14] + node _T_2732 = eq(_T_2730, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2732 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2733 = eq(io.in[0].c.bits.source, _T_2715) @[HellaCache.scala 178:14] + node _T_2734 = or(_T_2733, reset) @[HellaCache.scala 178:14] + node _T_2736 = eq(_T_2734, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2736 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2737 = eq(io.in[0].c.bits.address, _T_2717) @[HellaCache.scala 178:14] + node _T_2738 = or(_T_2737, reset) @[HellaCache.scala 178:14] + node _T_2740 = eq(_T_2738, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2740 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2741 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2742 = and(_T_2741, _T_2698) @[HellaCache.scala 178:14] + when _T_2742 : @[HellaCache.scala 178:14] + _T_2709 <= io.in[0].c.bits.opcode @[HellaCache.scala 178:14] + _T_2711 <= io.in[0].c.bits.param @[HellaCache.scala 178:14] + _T_2713 <= io.in[0].c.bits.size @[HellaCache.scala 178:14] + _T_2715 <= io.in[0].c.bits.source @[HellaCache.scala 178:14] + _T_2717 <= io.in[0].c.bits.address @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2743 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2745 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2746 = dshl(_T_2745, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2747 = bits(_T_2746, 7, 0) @[package.scala 19:76] + node _T_2748 = not(_T_2747) @[package.scala 19:40] + node _T_2749 = shr(_T_2748, 3) @[Edges.scala 198:59] + node _T_2750 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2752 = mux(_T_2750, _T_2749, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2754 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2756 = sub(_T_2754, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2757 = asUInt(_T_2756) @[Edges.scala 208:28] + node _T_2758 = tail(_T_2757, 1) @[Edges.scala 208:28] + node _T_2760 = eq(_T_2754, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2762 = eq(_T_2754, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2764 = eq(_T_2752, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2765 = or(_T_2762, _T_2764) @[Edges.scala 210:37] + node _T_2766 = and(_T_2765, _T_2743) @[Edges.scala 211:22] + node _T_2767 = not(_T_2758) @[Edges.scala 212:27] + node _T_2768 = and(_T_2752, _T_2767) @[Edges.scala 212:25] + when _T_2743 : @[Edges.scala 213:17] + node _T_2769 = mux(_T_2760, _T_2752, _T_2758) @[Edges.scala 214:21] + _T_2754 <= _T_2769 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2771 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2773 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2775 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2777 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2779 : UInt, clock @[HellaCache.scala 178:14] + reg _T_2781 : UInt, clock @[HellaCache.scala 178:14] + node _T_2783 = eq(_T_2760, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2784 = and(io.in[0].d.valid, _T_2783) @[HellaCache.scala 178:14] + when _T_2784 : @[HellaCache.scala 178:14] + node _T_2785 = eq(io.in[0].d.bits.opcode, _T_2771) @[HellaCache.scala 178:14] + node _T_2786 = or(_T_2785, reset) @[HellaCache.scala 178:14] + node _T_2788 = eq(_T_2786, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2788 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2789 = eq(io.in[0].d.bits.param, _T_2773) @[HellaCache.scala 178:14] + node _T_2790 = or(_T_2789, reset) @[HellaCache.scala 178:14] + node _T_2792 = eq(_T_2790, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2792 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2793 = eq(io.in[0].d.bits.size, _T_2775) @[HellaCache.scala 178:14] + node _T_2794 = or(_T_2793, reset) @[HellaCache.scala 178:14] + node _T_2796 = eq(_T_2794, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2796 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2797 = eq(io.in[0].d.bits.source, _T_2777) @[HellaCache.scala 178:14] + node _T_2798 = or(_T_2797, reset) @[HellaCache.scala 178:14] + node _T_2800 = eq(_T_2798, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2800 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2801 = eq(io.in[0].d.bits.sink, _T_2779) @[HellaCache.scala 178:14] + node _T_2802 = or(_T_2801, reset) @[HellaCache.scala 178:14] + node _T_2804 = eq(_T_2802, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2804 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2805 = eq(io.in[0].d.bits.addr_lo, _T_2781) @[HellaCache.scala 178:14] + node _T_2806 = or(_T_2805, reset) @[HellaCache.scala 178:14] + node _T_2808 = eq(_T_2806, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2808 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at HellaCache.scala:178:14)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2809 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2810 = and(_T_2809, _T_2760) @[HellaCache.scala 178:14] + when _T_2810 : @[HellaCache.scala 178:14] + _T_2771 <= io.in[0].d.bits.opcode @[HellaCache.scala 178:14] + _T_2773 <= io.in[0].d.bits.param @[HellaCache.scala 178:14] + _T_2775 <= io.in[0].d.bits.size @[HellaCache.scala 178:14] + _T_2777 <= io.in[0].d.bits.source @[HellaCache.scala 178:14] + _T_2779 <= io.in[0].d.bits.sink @[HellaCache.scala 178:14] + _T_2781 <= io.in[0].d.bits.addr_lo @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + reg _T_2812 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_2813 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2815 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2816 = dshl(_T_2815, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2817 = bits(_T_2816, 7, 0) @[package.scala 19:76] + node _T_2818 = not(_T_2817) @[package.scala 19:40] + node _T_2819 = shr(_T_2818, 3) @[Edges.scala 198:59] + node _T_2820 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2822 = eq(_T_2820, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2824 = mux(_T_2822, _T_2819, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2826 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2828 = sub(_T_2826, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2829 = asUInt(_T_2828) @[Edges.scala 208:28] + node _T_2830 = tail(_T_2829, 1) @[Edges.scala 208:28] + node _T_2832 = eq(_T_2826, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2834 = eq(_T_2826, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2836 = eq(_T_2824, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2837 = or(_T_2834, _T_2836) @[Edges.scala 210:37] + node _T_2838 = and(_T_2837, _T_2813) @[Edges.scala 211:22] + node _T_2839 = not(_T_2830) @[Edges.scala 212:27] + node _T_2840 = and(_T_2824, _T_2839) @[Edges.scala 212:25] + when _T_2813 : @[Edges.scala 213:17] + node _T_2841 = mux(_T_2832, _T_2824, _T_2830) @[Edges.scala 214:21] + _T_2826 <= _T_2841 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2842 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2844 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2845 = dshl(_T_2844, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2846 = bits(_T_2845, 7, 0) @[package.scala 19:76] + node _T_2847 = not(_T_2846) @[package.scala 19:40] + node _T_2848 = shr(_T_2847, 3) @[Edges.scala 198:59] + node _T_2849 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2851 = mux(_T_2849, _T_2848, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2853 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2855 = sub(_T_2853, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2856 = asUInt(_T_2855) @[Edges.scala 208:28] + node _T_2857 = tail(_T_2856, 1) @[Edges.scala 208:28] + node _T_2859 = eq(_T_2853, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2861 = eq(_T_2853, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2863 = eq(_T_2851, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2864 = or(_T_2861, _T_2863) @[Edges.scala 210:37] + node _T_2865 = and(_T_2864, _T_2842) @[Edges.scala 211:22] + node _T_2866 = not(_T_2857) @[Edges.scala 212:27] + node _T_2867 = and(_T_2851, _T_2866) @[Edges.scala 212:25] + when _T_2842 : @[Edges.scala 213:17] + node _T_2868 = mux(_T_2859, _T_2851, _T_2857) @[Edges.scala 214:21] + _T_2853 <= _T_2868 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2870 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + node _T_2871 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[HellaCache.scala 178:14] + node _T_2872 = or(_T_2870, _T_2871) @[HellaCache.scala 178:14] + node _T_2874 = eq(io.in[0].a.valid, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2875 = or(_T_2872, _T_2874) @[HellaCache.scala 178:14] + node _T_2877 = eq(io.in[0].d.valid, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2878 = or(_T_2875, _T_2877) @[HellaCache.scala 178:14] + node _T_2879 = or(_T_2878, reset) @[HellaCache.scala 178:14] + node _T_2881 = eq(_T_2879, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2881 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at HellaCache.scala:178:14)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + wire _T_2883 : UInt<1> + _T_2883 is invalid + _T_2883 <= UInt<1>("h00") + node _T_2884 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2884 : @[HellaCache.scala 178:14] + when _T_2837 : @[HellaCache.scala 178:14] + node _T_2886 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2883 <= _T_2886 @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2887 = dshr(_T_2812, io.in[0].a.bits.source) @[HellaCache.scala 178:14] + node _T_2888 = bits(_T_2887, 0, 0) @[HellaCache.scala 178:14] + node _T_2890 = eq(_T_2888, UInt<1>("h00")) @[HellaCache.scala 178:14] + node _T_2891 = or(_T_2890, reset) @[HellaCache.scala 178:14] + node _T_2893 = eq(_T_2891, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2893 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at HellaCache.scala:178:14)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + wire _T_2895 : UInt<1> + _T_2895 is invalid + _T_2895 <= UInt<1>("h00") + node _T_2896 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2898 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[HellaCache.scala 178:14] + node _T_2899 = and(_T_2896, _T_2898) @[HellaCache.scala 178:14] + when _T_2899 : @[HellaCache.scala 178:14] + when _T_2864 : @[HellaCache.scala 178:14] + node _T_2901 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2895 <= _T_2901 @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2902 = or(_T_2883, _T_2812) @[HellaCache.scala 178:14] + node _T_2903 = dshr(_T_2902, io.in[0].d.bits.source) @[HellaCache.scala 178:14] + node _T_2904 = bits(_T_2903, 0, 0) @[HellaCache.scala 178:14] + node _T_2905 = or(_T_2904, reset) @[HellaCache.scala 178:14] + node _T_2907 = eq(_T_2905, UInt<1>("h00")) @[HellaCache.scala 178:14] + when _T_2907 : @[HellaCache.scala 178:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:178:14)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[HellaCache.scala 178:14] + stop(clock, UInt<1>(1), 1) @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + skip @[HellaCache.scala 178:14] + node _T_2908 = or(_T_2812, _T_2883) @[HellaCache.scala 178:14] + node _T_2909 = not(_T_2895) @[HellaCache.scala 178:14] + node _T_2910 = and(_T_2908, _T_2909) @[HellaCache.scala 178:14] + _T_2812 <= _T_2910 @[HellaCache.scala 178:14] + + module ICache_icache : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<16>, datablock : UInt<64>}}, flip invalidate : UInt<1>, mem : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[ICache.scala 67:18] + reg invalidated : UInt<1>, clock @[ICache.scala 68:24] + node stall = eq(io.resp.ready, UInt<1>("h00")) @[ICache.scala 69:15] + reg refill_addr : UInt<32>, clock @[ICache.scala 71:24] + wire s1_any_tag_hit : UInt<1> @[ICache.scala 72:28] + s1_any_tag_hit is invalid @[ICache.scala 72:28] + reg s1_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[ICache.scala 74:21] + node _T_221 = eq(io.s1_kill, UInt<1>("h00")) @[ICache.scala 75:31] + node _T_222 = and(s1_valid, _T_221) @[ICache.scala 75:28] + node _T_223 = eq(state, UInt<2>("h00")) @[ICache.scala 75:52] + node out_valid = and(_T_222, _T_223) @[ICache.scala 75:43] + node s1_idx = bits(io.s1_paddr, 11, 6) @[ICache.scala 76:27] + node s1_tag = bits(io.s1_paddr, 31, 12) @[ICache.scala 77:27] + node s1_hit = and(out_valid, s1_any_tag_hit) @[ICache.scala 78:26] + node _T_225 = eq(s1_any_tag_hit, UInt<1>("h00")) @[ICache.scala 79:30] + node s1_miss = and(out_valid, _T_225) @[ICache.scala 79:27] + node _T_226 = eq(state, UInt<2>("h00")) @[ICache.scala 81:40] + node _T_227 = and(io.req.valid, _T_226) @[ICache.scala 81:31] + node _T_228 = and(out_valid, stall) @[ICache.scala 81:67] + node _T_230 = eq(_T_228, UInt<1>("h00")) @[ICache.scala 81:55] + node s0_valid = and(_T_227, _T_230) @[ICache.scala 81:52] + node _T_231 = and(out_valid, stall) @[ICache.scala 84:37] + node _T_232 = or(s0_valid, _T_231) @[ICache.scala 84:24] + s1_valid <= _T_232 @[ICache.scala 84:12] + node _T_233 = eq(state, UInt<2>("h00")) @[ICache.scala 86:26] + node _T_234 = and(s1_miss, _T_233) @[ICache.scala 86:17] + when _T_234 : @[ICache.scala 86:39] + refill_addr <= io.s1_paddr @[ICache.scala 87:17] + skip @[ICache.scala 86:39] + node refill_tag = bits(refill_addr, 31, 12) @[ICache.scala 89:31] + node refill_idx = bits(refill_addr, 11, 6) @[ICache.scala 90:31] + node _T_235 = and(io.mem.0.d.ready, io.mem.0.d.valid) @[Decoupled.scala 30:37] + node _T_237 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_238 = dshl(_T_237, io.mem.0.d.bits.size) @[package.scala 19:71] + node _T_239 = bits(_T_238, 7, 0) @[package.scala 19:76] + node _T_240 = not(_T_239) @[package.scala 19:40] + node _T_241 = shr(_T_240, 3) @[Edges.scala 198:59] + node _T_242 = bits(io.mem.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_244 = mux(_T_242, _T_241, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_246 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_248 = sub(_T_246, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_249 = asUInt(_T_248) @[Edges.scala 208:28] + node _T_250 = tail(_T_249, 1) @[Edges.scala 208:28] + node _T_252 = eq(_T_246, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_254 = eq(_T_246, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_256 = eq(_T_244, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_257 = or(_T_254, _T_256) @[Edges.scala 210:37] + node refill_done = and(_T_257, _T_235) @[Edges.scala 211:22] + node _T_258 = not(_T_250) @[Edges.scala 212:27] + node refill_cnt = and(_T_244, _T_258) @[Edges.scala 212:25] + when _T_235 : @[Edges.scala 213:17] + node _T_259 = mux(_T_252, _T_244, _T_250) @[Edges.scala 214:21] + _T_246 <= _T_259 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + io.mem.0.d.ready <= UInt<1>("h01") @[ICache.scala 92:18] + reg _T_262 : UInt<16>, clock with : (reset => (reset, UInt<16>("h01"))) @[LFSR.scala 22:19] + when s1_miss : @[LFSR.scala 23:22] + node _T_263 = bits(_T_262, 0, 0) @[LFSR.scala 23:40] + node _T_264 = bits(_T_262, 2, 2) @[LFSR.scala 23:48] + node _T_265 = xor(_T_263, _T_264) @[LFSR.scala 23:43] + node _T_266 = bits(_T_262, 3, 3) @[LFSR.scala 23:56] + node _T_267 = xor(_T_265, _T_266) @[LFSR.scala 23:51] + node _T_268 = bits(_T_262, 5, 5) @[LFSR.scala 23:64] + node _T_269 = xor(_T_267, _T_268) @[LFSR.scala 23:59] + node _T_270 = bits(_T_262, 15, 1) @[LFSR.scala 23:73] + node _T_271 = cat(_T_269, _T_270) @[Cat.scala 30:58] + _T_262 <= _T_271 @[LFSR.scala 23:29] + skip @[LFSR.scala 23:22] + node repl_way = bits(_T_262, 1, 0) @[ICache.scala 95:56] + smem tag_array : UInt<20>[4][64] @[ICache.scala 97:25] + node _T_282 = bits(io.req.bits.addr, 11, 6) @[ICache.scala 98:42] + node _T_284 = eq(refill_done, UInt<1>("h00")) @[ICache.scala 98:70] + node _T_285 = and(_T_284, s0_valid) @[ICache.scala 98:83] + wire _T_287 : UInt + _T_287 is invalid + when _T_285 : + _T_287 <= _T_282 + node _T_289 = or(_T_287, UInt<6>("h00")) + node _T_290 = bits(_T_289, 5, 0) + read mport tag_rdata = tag_array[_T_290], clock + skip + when refill_done : @[ICache.scala 99:22] + wire _T_304 : UInt<20>[4] @[ICache.scala 101:48] + _T_304 is invalid @[ICache.scala 101:48] + _T_304[0] <= refill_tag @[ICache.scala 101:48] + _T_304[1] <= refill_tag @[ICache.scala 101:48] + _T_304[2] <= refill_tag @[ICache.scala 101:48] + _T_304[3] <= refill_tag @[ICache.scala 101:48] + node _T_312 = eq(repl_way, UInt<1>("h00")) @[ICache.scala 101:84] + node _T_314 = eq(repl_way, UInt<1>("h01")) @[ICache.scala 101:84] + node _T_316 = eq(repl_way, UInt<2>("h02")) @[ICache.scala 101:84] + node _T_318 = eq(repl_way, UInt<2>("h03")) @[ICache.scala 101:84] + wire _T_321 : UInt<1>[4] @[ICache.scala 101:74] + _T_321 is invalid @[ICache.scala 101:74] + _T_321[0] <= _T_312 @[ICache.scala 101:74] + _T_321[1] <= _T_314 @[ICache.scala 101:74] + _T_321[2] <= _T_316 @[ICache.scala 101:74] + _T_321[3] <= _T_318 @[ICache.scala 101:74] + write mport _T_328 = tag_array[refill_idx], clock + when _T_321[0] : + _T_328[0] <= _T_304[0] skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 + when _T_321[1] : + _T_328[1] <= _T_304[1] skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 + when _T_321[2] : + _T_328[2] <= _T_304[2] skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") + when _T_321[3] : + _T_328[3] <= _T_304[3] skip - skip + skip @[ICache.scala 99:22] + reg vb_array : UInt<256>, clock with : (reset => (reset, UInt<256>("h00"))) @[ICache.scala 104:21] + node _T_342 = eq(invalidated, UInt<1>("h00")) @[ICache.scala 105:24] + node _T_343 = and(refill_done, _T_342) @[ICache.scala 105:21] + when _T_343 : @[ICache.scala 105:38] + node _T_344 = cat(repl_way, refill_idx) @[Cat.scala 30:58] + node _T_347 = dshl(UInt<1>("h01"), _T_344) @[ICache.scala 106:32] + node _T_348 = or(vb_array, _T_347) @[ICache.scala 106:32] + node _T_349 = not(vb_array) @[ICache.scala 106:32] + node _T_350 = or(_T_349, _T_347) @[ICache.scala 106:32] + node _T_351 = not(_T_350) @[ICache.scala 106:32] + node _T_352 = mux(UInt<1>("h01"), _T_348, _T_351) @[ICache.scala 106:32] + vb_array <= _T_352 @[ICache.scala 106:14] + skip @[ICache.scala 105:38] + when io.invalidate : @[ICache.scala 108:24] + vb_array <= UInt<1>("h00") @[ICache.scala 109:14] + invalidated <= UInt<1>("h01") @[ICache.scala 110:17] + skip @[ICache.scala 108:24] + wire s1_disparity : UInt<1>[4] @[ICache.scala 112:26] + s1_disparity is invalid @[ICache.scala 112:26] + node _T_364 = and(s1_valid, s1_disparity[0]) @[ICache.scala 114:20] + when _T_364 : @[ICache.scala 114:40] + node _T_366 = cat(UInt<1>("h00"), s1_idx) @[Cat.scala 30:58] + node _T_369 = dshl(UInt<1>("h01"), _T_366) @[ICache.scala 114:69] + node _T_370 = or(vb_array, _T_369) @[ICache.scala 114:69] + node _T_371 = not(vb_array) @[ICache.scala 114:69] + node _T_372 = or(_T_371, _T_369) @[ICache.scala 114:69] + node _T_373 = not(_T_372) @[ICache.scala 114:69] + node _T_374 = mux(UInt<1>("h00"), _T_370, _T_373) @[ICache.scala 114:69] + vb_array <= _T_374 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_375 = and(s1_valid, s1_disparity[1]) @[ICache.scala 114:20] + when _T_375 : @[ICache.scala 114:40] + node _T_377 = cat(UInt<1>("h01"), s1_idx) @[Cat.scala 30:58] + node _T_380 = dshl(UInt<1>("h01"), _T_377) @[ICache.scala 114:69] + node _T_381 = or(vb_array, _T_380) @[ICache.scala 114:69] + node _T_382 = not(vb_array) @[ICache.scala 114:69] + node _T_383 = or(_T_382, _T_380) @[ICache.scala 114:69] + node _T_384 = not(_T_383) @[ICache.scala 114:69] + node _T_385 = mux(UInt<1>("h00"), _T_381, _T_384) @[ICache.scala 114:69] + vb_array <= _T_385 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_386 = and(s1_valid, s1_disparity[2]) @[ICache.scala 114:20] + when _T_386 : @[ICache.scala 114:40] + node _T_388 = cat(UInt<2>("h02"), s1_idx) @[Cat.scala 30:58] + node _T_391 = dshl(UInt<1>("h01"), _T_388) @[ICache.scala 114:69] + node _T_392 = or(vb_array, _T_391) @[ICache.scala 114:69] + node _T_393 = not(vb_array) @[ICache.scala 114:69] + node _T_394 = or(_T_393, _T_391) @[ICache.scala 114:69] + node _T_395 = not(_T_394) @[ICache.scala 114:69] + node _T_396 = mux(UInt<1>("h00"), _T_392, _T_395) @[ICache.scala 114:69] + vb_array <= _T_396 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_397 = and(s1_valid, s1_disparity[3]) @[ICache.scala 114:20] + when _T_397 : @[ICache.scala 114:40] + node _T_399 = cat(UInt<2>("h03"), s1_idx) @[Cat.scala 30:58] + node _T_402 = dshl(UInt<1>("h01"), _T_399) @[ICache.scala 114:69] + node _T_403 = or(vb_array, _T_402) @[ICache.scala 114:69] + node _T_404 = not(vb_array) @[ICache.scala 114:69] + node _T_405 = or(_T_404, _T_402) @[ICache.scala 114:69] + node _T_406 = not(_T_405) @[ICache.scala 114:69] + node _T_407 = mux(UInt<1>("h00"), _T_403, _T_406) @[ICache.scala 114:69] + vb_array <= _T_407 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + wire s1_tag_match : UInt<1>[4] @[ICache.scala 116:26] + s1_tag_match is invalid @[ICache.scala 116:26] + wire s1_tag_hit : UInt<1>[4] @[ICache.scala 117:24] + s1_tag_hit is invalid @[ICache.scala 117:24] + wire s1_dout : UInt<64>[4] @[ICache.scala 118:21] + s1_dout is invalid @[ICache.scala 118:21] + reg s1_dout_valid : UInt<1>, clock @[Reg.scala 14:44] + s1_dout_valid <= s0_valid @[Reg.scala 14:44] + node _T_436 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_438 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_439 = cat(UInt<1>("h00"), _T_438) @[Cat.scala 30:58] + node _T_440 = dshr(vb_array, _T_439) @[ICache.scala 122:43] + node _T_441 = bits(_T_440, 0, 0) @[ICache.scala 122:43] + node _T_442 = bits(_T_441, 0, 0) @[ICache.scala 122:97] + node _T_443 = and(_T_436, _T_442) @[ICache.scala 122:32] + node _T_446 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_448 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_448 <= _T_446 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_449 = mux(s1_dout_valid, _T_446, _T_448) @[Package.scala 27:42] + node _T_450 = bits(tag_rdata[0], 19, 0) @[ICache.scala 125:32] + node _T_451 = eq(_T_450, s1_tag) @[ICache.scala 125:46] + reg _T_453 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_453 <= _T_451 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_454 = mux(s1_dout_valid, _T_451, _T_453) @[Package.scala 27:42] + s1_tag_match[0] <= _T_454 @[ICache.scala 125:21] + node _T_455 = and(_T_443, s1_tag_match[0]) @[ICache.scala 126:28] + s1_tag_hit[0] <= _T_455 @[ICache.scala 126:19] + node _T_458 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_459 = or(_T_449, _T_458) @[ICache.scala 127:51] + node _T_460 = and(_T_443, _T_459) @[ICache.scala 127:30] + s1_disparity[0] <= _T_460 @[ICache.scala 127:21] + node _T_462 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_464 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_465 = cat(UInt<1>("h01"), _T_464) @[Cat.scala 30:58] + node _T_466 = dshr(vb_array, _T_465) @[ICache.scala 122:43] + node _T_467 = bits(_T_466, 0, 0) @[ICache.scala 122:43] + node _T_468 = bits(_T_467, 0, 0) @[ICache.scala 122:97] + node _T_469 = and(_T_462, _T_468) @[ICache.scala 122:32] + node _T_472 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_474 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_474 <= _T_472 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_475 = mux(s1_dout_valid, _T_472, _T_474) @[Package.scala 27:42] + node _T_476 = bits(tag_rdata[1], 19, 0) @[ICache.scala 125:32] + node _T_477 = eq(_T_476, s1_tag) @[ICache.scala 125:46] + reg _T_479 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_479 <= _T_477 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_480 = mux(s1_dout_valid, _T_477, _T_479) @[Package.scala 27:42] + s1_tag_match[1] <= _T_480 @[ICache.scala 125:21] + node _T_481 = and(_T_469, s1_tag_match[1]) @[ICache.scala 126:28] + s1_tag_hit[1] <= _T_481 @[ICache.scala 126:19] + node _T_484 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_485 = or(_T_475, _T_484) @[ICache.scala 127:51] + node _T_486 = and(_T_469, _T_485) @[ICache.scala 127:30] + s1_disparity[1] <= _T_486 @[ICache.scala 127:21] + node _T_488 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_490 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_491 = cat(UInt<2>("h02"), _T_490) @[Cat.scala 30:58] + node _T_492 = dshr(vb_array, _T_491) @[ICache.scala 122:43] + node _T_493 = bits(_T_492, 0, 0) @[ICache.scala 122:43] + node _T_494 = bits(_T_493, 0, 0) @[ICache.scala 122:97] + node _T_495 = and(_T_488, _T_494) @[ICache.scala 122:32] + node _T_498 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_500 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_500 <= _T_498 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_501 = mux(s1_dout_valid, _T_498, _T_500) @[Package.scala 27:42] + node _T_502 = bits(tag_rdata[2], 19, 0) @[ICache.scala 125:32] + node _T_503 = eq(_T_502, s1_tag) @[ICache.scala 125:46] + reg _T_505 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_505 <= _T_503 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_506 = mux(s1_dout_valid, _T_503, _T_505) @[Package.scala 27:42] + s1_tag_match[2] <= _T_506 @[ICache.scala 125:21] + node _T_507 = and(_T_495, s1_tag_match[2]) @[ICache.scala 126:28] + s1_tag_hit[2] <= _T_507 @[ICache.scala 126:19] + node _T_510 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_511 = or(_T_501, _T_510) @[ICache.scala 127:51] + node _T_512 = and(_T_495, _T_511) @[ICache.scala 127:30] + s1_disparity[2] <= _T_512 @[ICache.scala 127:21] + node _T_514 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_516 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_517 = cat(UInt<2>("h03"), _T_516) @[Cat.scala 30:58] + node _T_518 = dshr(vb_array, _T_517) @[ICache.scala 122:43] + node _T_519 = bits(_T_518, 0, 0) @[ICache.scala 122:43] + node _T_520 = bits(_T_519, 0, 0) @[ICache.scala 122:97] + node _T_521 = and(_T_514, _T_520) @[ICache.scala 122:32] + node _T_524 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_526 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_526 <= _T_524 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_527 = mux(s1_dout_valid, _T_524, _T_526) @[Package.scala 27:42] + node _T_528 = bits(tag_rdata[3], 19, 0) @[ICache.scala 125:32] + node _T_529 = eq(_T_528, s1_tag) @[ICache.scala 125:46] + reg _T_531 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_531 <= _T_529 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_532 = mux(s1_dout_valid, _T_529, _T_531) @[Package.scala 27:42] + s1_tag_match[3] <= _T_532 @[ICache.scala 125:21] + node _T_533 = and(_T_521, s1_tag_match[3]) @[ICache.scala 126:28] + s1_tag_hit[3] <= _T_533 @[ICache.scala 126:19] + node _T_536 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_537 = or(_T_527, _T_536) @[ICache.scala 127:51] + node _T_538 = and(_T_521, _T_537) @[ICache.scala 127:30] + s1_disparity[3] <= _T_538 @[ICache.scala 127:21] + node _T_539 = or(s1_tag_hit[0], s1_tag_hit[1]) @[ICache.scala 129:44] + node _T_540 = or(_T_539, s1_tag_hit[2]) @[ICache.scala 129:44] + node _T_541 = or(_T_540, s1_tag_hit[3]) @[ICache.scala 129:44] + node _T_542 = or(s1_disparity[0], s1_disparity[1]) @[ICache.scala 129:78] + node _T_543 = or(_T_542, s1_disparity[2]) @[ICache.scala 129:78] + node _T_544 = or(_T_543, s1_disparity[3]) @[ICache.scala 129:78] + node _T_546 = eq(_T_544, UInt<1>("h00")) @[ICache.scala 129:52] + node _T_547 = and(_T_541, _T_546) @[ICache.scala 129:49] + s1_any_tag_hit <= _T_547 @[ICache.scala 129:18] + smem _T_550 : UInt<64>[512] @[ICache.scala 132:28] + node _T_552 = eq(repl_way, UInt<1>("h00")) @[ICache.scala 133:42] + node _T_553 = and(io.mem.0.d.valid, _T_552) @[ICache.scala 133:30] + when _T_553 : @[ICache.scala 134:16] + node _T_554 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_555 = or(_T_554, refill_cnt) @[ICache.scala 136:63] + write mport _T_556 = _T_550[_T_555], clock + _T_556 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_557 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_559 = eq(_T_553, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_560 = and(_T_559, s0_valid) @[ICache.scala 139:50] + wire _T_562 : UInt + _T_562 is invalid + when _T_560 : + _T_562 <= _T_557 + node _T_564 = or(_T_562, UInt<9>("h00")) + node _T_565 = bits(_T_564, 8, 0) + read mport _T_566 = _T_550[_T_565], clock + skip + reg _T_568 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_568 <= _T_566 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_569 = mux(s1_dout_valid, _T_566, _T_568) @[Package.scala 27:42] + s1_dout[0] <= _T_569 @[ICache.scala 139:16] + smem _T_572 : UInt<64>[512] @[ICache.scala 132:28] + node _T_574 = eq(repl_way, UInt<1>("h01")) @[ICache.scala 133:42] + node _T_575 = and(io.mem.0.d.valid, _T_574) @[ICache.scala 133:30] + when _T_575 : @[ICache.scala 134:16] + node _T_576 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_577 = or(_T_576, refill_cnt) @[ICache.scala 136:63] + write mport _T_578 = _T_572[_T_577], clock + _T_578 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_579 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_581 = eq(_T_575, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_582 = and(_T_581, s0_valid) @[ICache.scala 139:50] + wire _T_584 : UInt + _T_584 is invalid + when _T_582 : + _T_584 <= _T_579 + node _T_586 = or(_T_584, UInt<9>("h00")) + node _T_587 = bits(_T_586, 8, 0) + read mport _T_588 = _T_572[_T_587], clock + skip + reg _T_590 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_590 <= _T_588 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_591 = mux(s1_dout_valid, _T_588, _T_590) @[Package.scala 27:42] + s1_dout[1] <= _T_591 @[ICache.scala 139:16] + smem _T_594 : UInt<64>[512] @[ICache.scala 132:28] + node _T_596 = eq(repl_way, UInt<2>("h02")) @[ICache.scala 133:42] + node _T_597 = and(io.mem.0.d.valid, _T_596) @[ICache.scala 133:30] + when _T_597 : @[ICache.scala 134:16] + node _T_598 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_599 = or(_T_598, refill_cnt) @[ICache.scala 136:63] + write mport _T_600 = _T_594[_T_599], clock + _T_600 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_601 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_603 = eq(_T_597, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_604 = and(_T_603, s0_valid) @[ICache.scala 139:50] + wire _T_606 : UInt + _T_606 is invalid + when _T_604 : + _T_606 <= _T_601 + node _T_608 = or(_T_606, UInt<9>("h00")) + node _T_609 = bits(_T_608, 8, 0) + read mport _T_610 = _T_594[_T_609], clock + skip + reg _T_612 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_612 <= _T_610 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_613 = mux(s1_dout_valid, _T_610, _T_612) @[Package.scala 27:42] + s1_dout[2] <= _T_613 @[ICache.scala 139:16] + smem _T_616 : UInt<64>[512] @[ICache.scala 132:28] + node _T_618 = eq(repl_way, UInt<2>("h03")) @[ICache.scala 133:42] + node _T_619 = and(io.mem.0.d.valid, _T_618) @[ICache.scala 133:30] + when _T_619 : @[ICache.scala 134:16] + node _T_620 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_621 = or(_T_620, refill_cnt) @[ICache.scala 136:63] + write mport _T_622 = _T_616[_T_621], clock + _T_622 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_623 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_625 = eq(_T_619, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_626 = and(_T_625, s0_valid) @[ICache.scala 139:50] + wire _T_628 : UInt + _T_628 is invalid + when _T_626 : + _T_628 <= _T_623 + node _T_630 = or(_T_628, UInt<9>("h00")) + node _T_631 = bits(_T_630, 8, 0) + read mport _T_632 = _T_616[_T_631], clock + skip + reg _T_634 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_634 <= _T_632 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_635 = mux(s1_dout_valid, _T_632, _T_634) @[Package.scala 27:42] + s1_dout[3] <= _T_635 @[ICache.scala 139:16] + node _T_638 = eq(stall, UInt<1>("h00")) @[ICache.scala 148:51] + reg _T_639 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when _T_638 : @[Reg.scala 43:19] + _T_639 <= s1_hit @[Reg.scala 43:23] + skip @[Reg.scala 43:19] + node _T_641 = eq(stall, UInt<1>("h00")) @[ICache.scala 149:46] + reg _T_654 : UInt<1>[4], clock @[Reg.scala 34:16] + when _T_641 : @[Reg.scala 35:19] + _T_654 <- s1_tag_hit @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_672 = eq(stall, UInt<1>("h00")) @[ICache.scala 150:40] + reg _T_685 : UInt<64>[4], clock @[Reg.scala 34:16] + when _T_672 : @[Reg.scala 35:19] + _T_685 <- s1_dout @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_703 = mux(_T_654[0], _T_685[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_705 = mux(_T_654[1], _T_685[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_707 = mux(_T_654[2], _T_685[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_709 = mux(_T_654[3], _T_685[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_711 = or(_T_703, _T_705) @[Mux.scala 19:72] + node _T_712 = or(_T_711, _T_707) @[Mux.scala 19:72] + node _T_713 = or(_T_712, _T_709) @[Mux.scala 19:72] + wire _T_715 : UInt<64> @[Mux.scala 19:72] + _T_715 is invalid @[Mux.scala 19:72] + _T_715 <= _T_713 @[Mux.scala 19:72] + io.resp.bits.datablock <= _T_715 @[ICache.scala 151:30] + io.resp.valid <= _T_639 @[ICache.scala 152:21] + node _T_716 = eq(state, UInt<2>("h01")) @[ICache.scala 154:27] + node _T_718 = eq(io.s2_kill, UInt<1>("h00")) @[ICache.scala 154:44] + node _T_719 = and(_T_716, _T_718) @[ICache.scala 154:41] + io.mem.0.a.valid <= _T_719 @[ICache.scala 154:18] + node _T_721 = shr(refill_addr, 6) @[ICache.scala 157:46] + node _T_722 = shl(_T_721, 6) @[ICache.scala 157:63] + node _T_726 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_728 = leq(UInt<3>("h06"), UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_729 = and(_T_726, _T_728) @[Parameters.scala 63:37] + node _T_730 = or(UInt<1>("h00"), _T_729) @[Parameters.scala 132:31] + node _T_732 = xor(_T_722, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_733 = cvt(_T_732) @[Parameters.scala 117:49] + node _T_735 = and(_T_733, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_736 = asSInt(_T_735) @[Parameters.scala 117:52] + node _T_738 = eq(_T_736, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_739 = and(_T_730, _T_738) @[Parameters.scala 132:56] + node _T_742 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_744 = leq(UInt<3>("h06"), UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_745 = and(_T_742, _T_744) @[Parameters.scala 63:37] + node _T_746 = or(UInt<1>("h00"), _T_745) @[Parameters.scala 132:31] + node _T_748 = xor(_T_722, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_749 = cvt(_T_748) @[Parameters.scala 117:49] + node _T_751 = and(_T_749, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_752 = asSInt(_T_751) @[Parameters.scala 117:52] + node _T_754 = eq(_T_752, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_755 = and(_T_746, _T_754) @[Parameters.scala 132:56] + node _T_757 = or(UInt<1>("h00"), _T_739) @[Parameters.scala 134:30] + node _T_758 = or(_T_757, _T_755) @[Parameters.scala 134:30] + wire _T_767 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 342:17] + _T_767 is invalid @[Edges.scala 342:17] + _T_767.opcode <= UInt<3>("h04") @[Edges.scala 343:15] + _T_767.param <= UInt<1>("h00") @[Edges.scala 344:15] + _T_767.size <= UInt<3>("h06") @[Edges.scala 345:15] + _T_767.source <= UInt<1>("h00") @[Edges.scala 346:15] + _T_767.address <= _T_722 @[Edges.scala 347:15] + node _T_779 = dshl(UInt<1>("h01"), UInt<2>("h02")) @[OneHot.scala 49:12] + node _T_780 = bits(_T_779, 2, 0) @[OneHot.scala 49:37] + node _T_782 = geq(UInt<3>("h06"), UInt<2>("h03")) @[package.scala 41:21] + node _T_784 = bits(_T_780, 2, 2) @[package.scala 44:26] + node _T_785 = bits(_T_722, 2, 2) @[package.scala 45:26] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[package.scala 46:20] + node _T_788 = and(UInt<1>("h01"), _T_787) @[package.scala 49:27] + node _T_789 = and(_T_784, _T_788) @[package.scala 50:38] + node _T_790 = or(_T_782, _T_789) @[package.scala 50:29] + node _T_791 = and(UInt<1>("h01"), _T_785) @[package.scala 49:27] + node _T_792 = and(_T_784, _T_791) @[package.scala 50:38] + node _T_793 = or(_T_782, _T_792) @[package.scala 50:29] + node _T_794 = bits(_T_780, 1, 1) @[package.scala 44:26] + node _T_795 = bits(_T_722, 1, 1) @[package.scala 45:26] + node _T_797 = eq(_T_795, UInt<1>("h00")) @[package.scala 46:20] + node _T_798 = and(_T_788, _T_797) @[package.scala 49:27] + node _T_799 = and(_T_794, _T_798) @[package.scala 50:38] + node _T_800 = or(_T_790, _T_799) @[package.scala 50:29] + node _T_801 = and(_T_788, _T_795) @[package.scala 49:27] + node _T_802 = and(_T_794, _T_801) @[package.scala 50:38] + node _T_803 = or(_T_790, _T_802) @[package.scala 50:29] + node _T_804 = and(_T_791, _T_797) @[package.scala 49:27] + node _T_805 = and(_T_794, _T_804) @[package.scala 50:38] + node _T_806 = or(_T_793, _T_805) @[package.scala 50:29] + node _T_807 = and(_T_791, _T_795) @[package.scala 49:27] + node _T_808 = and(_T_794, _T_807) @[package.scala 50:38] + node _T_809 = or(_T_793, _T_808) @[package.scala 50:29] + node _T_810 = bits(_T_780, 0, 0) @[package.scala 44:26] + node _T_811 = bits(_T_722, 0, 0) @[package.scala 45:26] + node _T_813 = eq(_T_811, UInt<1>("h00")) @[package.scala 46:20] + node _T_814 = and(_T_798, _T_813) @[package.scala 49:27] + node _T_815 = and(_T_810, _T_814) @[package.scala 50:38] + node _T_816 = or(_T_800, _T_815) @[package.scala 50:29] + node _T_817 = and(_T_798, _T_811) @[package.scala 49:27] + node _T_818 = and(_T_810, _T_817) @[package.scala 50:38] + node _T_819 = or(_T_800, _T_818) @[package.scala 50:29] + node _T_820 = and(_T_801, _T_813) @[package.scala 49:27] + node _T_821 = and(_T_810, _T_820) @[package.scala 50:38] + node _T_822 = or(_T_803, _T_821) @[package.scala 50:29] + node _T_823 = and(_T_801, _T_811) @[package.scala 49:27] + node _T_824 = and(_T_810, _T_823) @[package.scala 50:38] + node _T_825 = or(_T_803, _T_824) @[package.scala 50:29] + node _T_826 = and(_T_804, _T_813) @[package.scala 49:27] + node _T_827 = and(_T_810, _T_826) @[package.scala 50:38] + node _T_828 = or(_T_806, _T_827) @[package.scala 50:29] + node _T_829 = and(_T_804, _T_811) @[package.scala 49:27] + node _T_830 = and(_T_810, _T_829) @[package.scala 50:38] + node _T_831 = or(_T_806, _T_830) @[package.scala 50:29] + node _T_832 = and(_T_807, _T_813) @[package.scala 49:27] + node _T_833 = and(_T_810, _T_832) @[package.scala 50:38] + node _T_834 = or(_T_809, _T_833) @[package.scala 50:29] + node _T_835 = and(_T_807, _T_811) @[package.scala 49:27] + node _T_836 = and(_T_810, _T_835) @[package.scala 50:38] + node _T_837 = or(_T_809, _T_836) @[package.scala 50:29] + node _T_838 = cat(_T_819, _T_816) @[Cat.scala 30:58] + node _T_839 = cat(_T_825, _T_822) @[Cat.scala 30:58] + node _T_840 = cat(_T_839, _T_838) @[Cat.scala 30:58] + node _T_841 = cat(_T_831, _T_828) @[Cat.scala 30:58] + node _T_842 = cat(_T_837, _T_834) @[Cat.scala 30:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 30:58] + node _T_844 = cat(_T_843, _T_840) @[Cat.scala 30:58] + _T_767.mask <= _T_844 @[Edges.scala 348:15] + _T_767.data <= UInt<1>("h00") @[Edges.scala 349:15] + io.mem.0.a.bits <- _T_767 @[ICache.scala 155:17] + io.mem.0.c.valid <= UInt<1>("h00") @[ICache.scala 159:18] + io.mem.0.e.valid <= UInt<1>("h00") @[ICache.scala 160:18] + node _T_848 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_848 : @[Conditional.scala 29:59] + when s1_miss : @[ICache.scala 165:22] + state <= UInt<2>("h01") @[ICache.scala 165:30] + skip @[ICache.scala 165:22] + invalidated <= UInt<1>("h00") @[ICache.scala 166:19] + skip @[Conditional.scala 29:59] + node _T_850 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_850 : @[Conditional.scala 29:59] + when io.mem.0.a.ready : @[ICache.scala 169:29] + state <= UInt<2>("h02") @[ICache.scala 169:37] + skip @[ICache.scala 169:29] + when io.s2_kill : @[ICache.scala 170:25] + state <= UInt<2>("h00") @[ICache.scala 170:33] + skip @[ICache.scala 170:25] + skip @[Conditional.scala 29:59] + node _T_851 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_851 : @[Conditional.scala 29:59] + when io.mem.0.d.valid : @[ICache.scala 173:29] + state <= UInt<2>("h03") @[ICache.scala 173:37] + skip @[ICache.scala 173:29] + skip @[Conditional.scala 29:59] + node _T_852 = eq(UInt<2>("h03"), state) @[Conditional.scala 29:28] + when _T_852 : @[Conditional.scala 29:59] + when refill_done : @[ICache.scala 176:26] + state <= UInt<2>("h00") @[ICache.scala 176:34] + skip @[ICache.scala 176:26] + skip @[Conditional.scala 29:59] + + module TLMonitor_32 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Frontend.scala 48:8] + node _T_781 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_782 = or(_T_781, reset) @[Frontend.scala 48:8] + node _T_784 = eq(_T_782, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_784 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Frontend.scala:48:8)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_786 = eq(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_789 : UInt<1>[1] @[Parameters.scala 228:27] + _T_789 is invalid @[Parameters.scala 228:27] + _T_789[0] <= _T_786 @[Parameters.scala 228:27] + node _T_794 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_795 = dshl(_T_794, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_796 = bits(_T_795, 7, 0) @[package.scala 19:76] + node _T_797 = not(_T_796) @[package.scala 19:40] + node _T_798 = and(io.in[0].a.bits.address, _T_797) @[Edges.scala 17:16] + node _T_800 = eq(_T_798, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_802 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_803 = dshl(UInt<1>("h01"), _T_802) @[OneHot.scala 49:12] + node _T_804 = bits(_T_803, 2, 0) @[OneHot.scala 49:37] + node _T_806 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_808 = bits(_T_804, 2, 2) @[package.scala 44:26] + node _T_809 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[package.scala 46:20] + node _T_812 = and(UInt<1>("h01"), _T_811) @[package.scala 49:27] + node _T_813 = and(_T_808, _T_812) @[package.scala 50:38] + node _T_814 = or(_T_806, _T_813) @[package.scala 50:29] + node _T_815 = and(UInt<1>("h01"), _T_809) @[package.scala 49:27] + node _T_816 = and(_T_808, _T_815) @[package.scala 50:38] + node _T_817 = or(_T_806, _T_816) @[package.scala 50:29] + node _T_818 = bits(_T_804, 1, 1) @[package.scala 44:26] + node _T_819 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_821 = eq(_T_819, UInt<1>("h00")) @[package.scala 46:20] + node _T_822 = and(_T_812, _T_821) @[package.scala 49:27] + node _T_823 = and(_T_818, _T_822) @[package.scala 50:38] + node _T_824 = or(_T_814, _T_823) @[package.scala 50:29] + node _T_825 = and(_T_812, _T_819) @[package.scala 49:27] + node _T_826 = and(_T_818, _T_825) @[package.scala 50:38] + node _T_827 = or(_T_814, _T_826) @[package.scala 50:29] + node _T_828 = and(_T_815, _T_821) @[package.scala 49:27] + node _T_829 = and(_T_818, _T_828) @[package.scala 50:38] + node _T_830 = or(_T_817, _T_829) @[package.scala 50:29] + node _T_831 = and(_T_815, _T_819) @[package.scala 49:27] + node _T_832 = and(_T_818, _T_831) @[package.scala 50:38] + node _T_833 = or(_T_817, _T_832) @[package.scala 50:29] + node _T_834 = bits(_T_804, 0, 0) @[package.scala 44:26] + node _T_835 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_837 = eq(_T_835, UInt<1>("h00")) @[package.scala 46:20] + node _T_838 = and(_T_822, _T_837) @[package.scala 49:27] + node _T_839 = and(_T_834, _T_838) @[package.scala 50:38] + node _T_840 = or(_T_824, _T_839) @[package.scala 50:29] + node _T_841 = and(_T_822, _T_835) @[package.scala 49:27] + node _T_842 = and(_T_834, _T_841) @[package.scala 50:38] + node _T_843 = or(_T_824, _T_842) @[package.scala 50:29] + node _T_844 = and(_T_825, _T_837) @[package.scala 49:27] + node _T_845 = and(_T_834, _T_844) @[package.scala 50:38] + node _T_846 = or(_T_827, _T_845) @[package.scala 50:29] + node _T_847 = and(_T_825, _T_835) @[package.scala 49:27] + node _T_848 = and(_T_834, _T_847) @[package.scala 50:38] + node _T_849 = or(_T_827, _T_848) @[package.scala 50:29] + node _T_850 = and(_T_828, _T_837) @[package.scala 49:27] + node _T_851 = and(_T_834, _T_850) @[package.scala 50:38] + node _T_852 = or(_T_830, _T_851) @[package.scala 50:29] + node _T_853 = and(_T_828, _T_835) @[package.scala 49:27] + node _T_854 = and(_T_834, _T_853) @[package.scala 50:38] + node _T_855 = or(_T_830, _T_854) @[package.scala 50:29] + node _T_856 = and(_T_831, _T_837) @[package.scala 49:27] + node _T_857 = and(_T_834, _T_856) @[package.scala 50:38] + node _T_858 = or(_T_833, _T_857) @[package.scala 50:29] + node _T_859 = and(_T_831, _T_835) @[package.scala 49:27] + node _T_860 = and(_T_834, _T_859) @[package.scala 50:38] + node _T_861 = or(_T_833, _T_860) @[package.scala 50:29] + node _T_862 = cat(_T_843, _T_840) @[Cat.scala 30:58] + node _T_863 = cat(_T_849, _T_846) @[Cat.scala 30:58] + node _T_864 = cat(_T_863, _T_862) @[Cat.scala 30:58] + node _T_865 = cat(_T_855, _T_852) @[Cat.scala 30:58] + node _T_866 = cat(_T_861, _T_858) @[Cat.scala 30:58] + node _T_867 = cat(_T_866, _T_865) @[Cat.scala 30:58] + node _T_868 = cat(_T_867, _T_864) @[Cat.scala 30:58] + node _T_870 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + when _T_870 : @[Frontend.scala 48:8] + node _T_873 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_875 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_876 = and(_T_873, _T_875) @[Parameters.scala 63:37] + node _T_877 = or(UInt<1>("h00"), _T_876) @[Parameters.scala 132:31] + node _T_879 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_880 = cvt(_T_879) @[Parameters.scala 117:49] + node _T_882 = and(_T_880, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_883 = asSInt(_T_882) @[Parameters.scala 117:52] + node _T_885 = eq(_T_883, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_887 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_888 = cvt(_T_887) @[Parameters.scala 117:49] + node _T_890 = and(_T_888, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_891 = asSInt(_T_890) @[Parameters.scala 117:52] + node _T_893 = eq(_T_891, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_894 = or(_T_885, _T_893) @[Parameters.scala 133:42] + node _T_895 = and(_T_877, _T_894) @[Parameters.scala 132:56] + node _T_898 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_900 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_901 = cvt(_T_900) @[Parameters.scala 117:49] + node _T_903 = and(_T_901, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_904 = asSInt(_T_903) @[Parameters.scala 117:52] + node _T_906 = eq(_T_904, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_908 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_909 = cvt(_T_908) @[Parameters.scala 117:49] + node _T_911 = and(_T_909, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_912 = asSInt(_T_911) @[Parameters.scala 117:52] + node _T_914 = eq(_T_912, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_916 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_917 = cvt(_T_916) @[Parameters.scala 117:49] + node _T_919 = and(_T_917, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_920 = asSInt(_T_919) @[Parameters.scala 117:52] + node _T_922 = eq(_T_920, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_924 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_925 = cvt(_T_924) @[Parameters.scala 117:49] + node _T_927 = and(_T_925, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_928 = asSInt(_T_927) @[Parameters.scala 117:52] + node _T_930 = eq(_T_928, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = or(_T_906, _T_914) @[Parameters.scala 133:42] + node _T_932 = or(_T_931, _T_922) @[Parameters.scala 133:42] + node _T_933 = or(_T_932, _T_930) @[Parameters.scala 133:42] + node _T_934 = and(_T_898, _T_933) @[Parameters.scala 132:56] + node _T_936 = or(UInt<1>("h00"), _T_895) @[Parameters.scala 134:30] + node _T_937 = or(_T_936, _T_934) @[Parameters.scala 134:30] + node _T_938 = or(_T_937, reset) @[Frontend.scala 48:8] + node _T_940 = eq(_T_938, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_940 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_941 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_943 = eq(_T_941, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_943 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_945 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_946 = or(_T_945, reset) @[Frontend.scala 48:8] + node _T_948 = eq(_T_946, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_948 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_949 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_951 = eq(_T_949, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_951 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_953 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_954 = or(_T_953, reset) @[Frontend.scala 48:8] + node _T_956 = eq(_T_954, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_956 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Frontend.scala:48:8)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_957 = not(io.in[0].a.bits.mask) @[Frontend.scala 48:8] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_960 = or(_T_959, reset) @[Frontend.scala 48:8] + node _T_962 = eq(_T_960, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_962 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_964 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Frontend.scala 48:8] + when _T_964 : @[Frontend.scala 48:8] + node _T_967 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_969 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_970 = and(_T_967, _T_969) @[Parameters.scala 63:37] + node _T_971 = or(UInt<1>("h00"), _T_970) @[Parameters.scala 132:31] + node _T_973 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_974 = cvt(_T_973) @[Parameters.scala 117:49] + node _T_976 = and(_T_974, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_977 = asSInt(_T_976) @[Parameters.scala 117:52] + node _T_979 = eq(_T_977, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_982 = cvt(_T_981) @[Parameters.scala 117:49] + node _T_984 = and(_T_982, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_985 = asSInt(_T_984) @[Parameters.scala 117:52] + node _T_987 = eq(_T_985, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_989 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_990 = cvt(_T_989) @[Parameters.scala 117:49] + node _T_992 = and(_T_990, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_993 = asSInt(_T_992) @[Parameters.scala 117:52] + node _T_995 = eq(_T_993, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_997 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_998 = cvt(_T_997) @[Parameters.scala 117:49] + node _T_1000 = and(_T_998, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1001 = asSInt(_T_1000) @[Parameters.scala 117:52] + node _T_1003 = eq(_T_1001, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1005 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1006 = cvt(_T_1005) @[Parameters.scala 117:49] + node _T_1008 = and(_T_1006, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1009 = asSInt(_T_1008) @[Parameters.scala 117:52] + node _T_1011 = eq(_T_1009, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1012 = or(_T_979, _T_987) @[Parameters.scala 133:42] + node _T_1013 = or(_T_1012, _T_995) @[Parameters.scala 133:42] + node _T_1014 = or(_T_1013, _T_1003) @[Parameters.scala 133:42] + node _T_1015 = or(_T_1014, _T_1011) @[Parameters.scala 133:42] + node _T_1016 = and(_T_971, _T_1015) @[Parameters.scala 132:56] + node _T_1019 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1021 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1022 = and(_T_1019, _T_1021) @[Parameters.scala 63:37] + node _T_1023 = or(UInt<1>("h00"), _T_1022) @[Parameters.scala 132:31] + node _T_1025 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1026 = cvt(_T_1025) @[Parameters.scala 117:49] + node _T_1028 = and(_T_1026, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1029 = asSInt(_T_1028) @[Parameters.scala 117:52] + node _T_1031 = eq(_T_1029, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1032 = and(_T_1023, _T_1031) @[Parameters.scala 132:56] + node _T_1034 = or(UInt<1>("h00"), _T_1016) @[Parameters.scala 134:30] + node _T_1035 = or(_T_1034, _T_1032) @[Parameters.scala 134:30] + node _T_1036 = or(_T_1035, reset) @[Frontend.scala 48:8] + node _T_1038 = eq(_T_1036, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1038 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1039 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1041 = eq(_T_1039, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1041 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1042 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1044 = eq(_T_1042, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1044 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1046 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1047 = or(_T_1046, reset) @[Frontend.scala 48:8] + node _T_1049 = eq(_T_1047, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1049 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1050 = eq(io.in[0].a.bits.mask, _T_868) @[Frontend.scala 48:8] + node _T_1051 = or(_T_1050, reset) @[Frontend.scala 48:8] + node _T_1053 = eq(_T_1051, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1053 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1055 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1055 : @[Frontend.scala 48:8] + node _T_1058 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1060 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1061 = and(_T_1058, _T_1060) @[Parameters.scala 63:37] + node _T_1062 = or(UInt<1>("h00"), _T_1061) @[Parameters.scala 132:31] + node _T_1064 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1065 = cvt(_T_1064) @[Parameters.scala 117:49] + node _T_1067 = and(_T_1065, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1068 = asSInt(_T_1067) @[Parameters.scala 117:52] + node _T_1070 = eq(_T_1068, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1072 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1073 = cvt(_T_1072) @[Parameters.scala 117:49] + node _T_1075 = and(_T_1073, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1076 = asSInt(_T_1075) @[Parameters.scala 117:52] + node _T_1078 = eq(_T_1076, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1080 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1081 = cvt(_T_1080) @[Parameters.scala 117:49] + node _T_1083 = and(_T_1081, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1084 = asSInt(_T_1083) @[Parameters.scala 117:52] + node _T_1086 = eq(_T_1084, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1088 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1089 = cvt(_T_1088) @[Parameters.scala 117:49] + node _T_1091 = and(_T_1089, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1092 = asSInt(_T_1091) @[Parameters.scala 117:52] + node _T_1094 = eq(_T_1092, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1096 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1097 = cvt(_T_1096) @[Parameters.scala 117:49] + node _T_1099 = and(_T_1097, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1100 = asSInt(_T_1099) @[Parameters.scala 117:52] + node _T_1102 = eq(_T_1100, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1103 = or(_T_1070, _T_1078) @[Parameters.scala 133:42] + node _T_1104 = or(_T_1103, _T_1086) @[Parameters.scala 133:42] + node _T_1105 = or(_T_1104, _T_1094) @[Parameters.scala 133:42] + node _T_1106 = or(_T_1105, _T_1102) @[Parameters.scala 133:42] + node _T_1107 = and(_T_1062, _T_1106) @[Parameters.scala 132:56] + node _T_1110 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1112 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1113 = and(_T_1110, _T_1112) @[Parameters.scala 63:37] + node _T_1114 = or(UInt<1>("h00"), _T_1113) @[Parameters.scala 132:31] + node _T_1116 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1117 = cvt(_T_1116) @[Parameters.scala 117:49] + node _T_1119 = and(_T_1117, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1120 = asSInt(_T_1119) @[Parameters.scala 117:52] + node _T_1122 = eq(_T_1120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1123 = and(_T_1114, _T_1122) @[Parameters.scala 132:56] + node _T_1126 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1128 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1129 = cvt(_T_1128) @[Parameters.scala 117:49] + node _T_1131 = and(_T_1129, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1132 = asSInt(_T_1131) @[Parameters.scala 117:52] + node _T_1134 = eq(_T_1132, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1135 = and(_T_1126, _T_1134) @[Parameters.scala 132:56] + node _T_1137 = or(UInt<1>("h00"), _T_1107) @[Parameters.scala 134:30] + node _T_1138 = or(_T_1137, _T_1123) @[Parameters.scala 134:30] + node _T_1139 = or(_T_1138, _T_1135) @[Parameters.scala 134:30] + node _T_1140 = or(_T_1139, reset) @[Frontend.scala 48:8] + node _T_1142 = eq(_T_1140, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1142 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1143 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1145 = eq(_T_1143, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1145 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1146 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1148 = eq(_T_1146, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1148 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1150 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1151 = or(_T_1150, reset) @[Frontend.scala 48:8] + node _T_1153 = eq(_T_1151, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1153 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1154 = eq(io.in[0].a.bits.mask, _T_868) @[Frontend.scala 48:8] + node _T_1155 = or(_T_1154, reset) @[Frontend.scala 48:8] + node _T_1157 = eq(_T_1155, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1157 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1159 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Frontend.scala 48:8] + when _T_1159 : @[Frontend.scala 48:8] + node _T_1162 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1164 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1165 = and(_T_1162, _T_1164) @[Parameters.scala 63:37] + node _T_1166 = or(UInt<1>("h00"), _T_1165) @[Parameters.scala 132:31] + node _T_1168 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1169 = cvt(_T_1168) @[Parameters.scala 117:49] + node _T_1171 = and(_T_1169, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1172 = asSInt(_T_1171) @[Parameters.scala 117:52] + node _T_1174 = eq(_T_1172, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1176 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1177 = cvt(_T_1176) @[Parameters.scala 117:49] + node _T_1179 = and(_T_1177, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1180 = asSInt(_T_1179) @[Parameters.scala 117:52] + node _T_1182 = eq(_T_1180, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1184 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1185 = cvt(_T_1184) @[Parameters.scala 117:49] + node _T_1187 = and(_T_1185, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1188 = asSInt(_T_1187) @[Parameters.scala 117:52] + node _T_1190 = eq(_T_1188, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1192 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1193 = cvt(_T_1192) @[Parameters.scala 117:49] + node _T_1195 = and(_T_1193, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1196 = asSInt(_T_1195) @[Parameters.scala 117:52] + node _T_1198 = eq(_T_1196, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1200 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1201 = cvt(_T_1200) @[Parameters.scala 117:49] + node _T_1203 = and(_T_1201, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1204 = asSInt(_T_1203) @[Parameters.scala 117:52] + node _T_1206 = eq(_T_1204, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1207 = or(_T_1174, _T_1182) @[Parameters.scala 133:42] + node _T_1208 = or(_T_1207, _T_1190) @[Parameters.scala 133:42] + node _T_1209 = or(_T_1208, _T_1198) @[Parameters.scala 133:42] + node _T_1210 = or(_T_1209, _T_1206) @[Parameters.scala 133:42] + node _T_1211 = and(_T_1166, _T_1210) @[Parameters.scala 132:56] + node _T_1214 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1216 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1217 = and(_T_1214, _T_1216) @[Parameters.scala 63:37] + node _T_1218 = or(UInt<1>("h00"), _T_1217) @[Parameters.scala 132:31] + node _T_1220 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1221 = cvt(_T_1220) @[Parameters.scala 117:49] + node _T_1223 = and(_T_1221, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1224 = asSInt(_T_1223) @[Parameters.scala 117:52] + node _T_1226 = eq(_T_1224, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1227 = and(_T_1218, _T_1226) @[Parameters.scala 132:56] + node _T_1230 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1232 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1233 = cvt(_T_1232) @[Parameters.scala 117:49] + node _T_1235 = and(_T_1233, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1236 = asSInt(_T_1235) @[Parameters.scala 117:52] + node _T_1238 = eq(_T_1236, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1239 = and(_T_1230, _T_1238) @[Parameters.scala 132:56] + node _T_1241 = or(UInt<1>("h00"), _T_1211) @[Parameters.scala 134:30] + node _T_1242 = or(_T_1241, _T_1227) @[Parameters.scala 134:30] + node _T_1243 = or(_T_1242, _T_1239) @[Parameters.scala 134:30] + node _T_1244 = or(_T_1243, reset) @[Frontend.scala 48:8] + node _T_1246 = eq(_T_1244, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1246 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1247 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1249 = eq(_T_1247, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1249 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1250 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1252 = eq(_T_1250, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1252 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1254 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1255 = or(_T_1254, reset) @[Frontend.scala 48:8] + node _T_1257 = eq(_T_1255, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1257 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1258 = not(_T_868) @[Frontend.scala 48:8] + node _T_1259 = and(io.in[0].a.bits.mask, _T_1258) @[Frontend.scala 48:8] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1262 = or(_T_1261, reset) @[Frontend.scala 48:8] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1264 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1266 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Frontend.scala 48:8] + when _T_1266 : @[Frontend.scala 48:8] + node _T_1269 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1271 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1272 = and(_T_1269, _T_1271) @[Parameters.scala 63:37] + node _T_1273 = or(UInt<1>("h00"), _T_1272) @[Parameters.scala 132:31] + node _T_1275 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1276 = cvt(_T_1275) @[Parameters.scala 117:49] + node _T_1278 = and(_T_1276, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1279 = asSInt(_T_1278) @[Parameters.scala 117:52] + node _T_1281 = eq(_T_1279, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1283 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1284 = cvt(_T_1283) @[Parameters.scala 117:49] + node _T_1286 = and(_T_1284, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1287 = asSInt(_T_1286) @[Parameters.scala 117:52] + node _T_1289 = eq(_T_1287, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1291 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1292 = cvt(_T_1291) @[Parameters.scala 117:49] + node _T_1294 = and(_T_1292, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1295 = asSInt(_T_1294) @[Parameters.scala 117:52] + node _T_1297 = eq(_T_1295, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1298 = or(_T_1281, _T_1289) @[Parameters.scala 133:42] + node _T_1299 = or(_T_1298, _T_1297) @[Parameters.scala 133:42] + node _T_1300 = and(_T_1273, _T_1299) @[Parameters.scala 132:56] + node _T_1303 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1305 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1306 = cvt(_T_1305) @[Parameters.scala 117:49] + node _T_1308 = and(_T_1306, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1309 = asSInt(_T_1308) @[Parameters.scala 117:52] + node _T_1311 = eq(_T_1309, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1313 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1314 = cvt(_T_1313) @[Parameters.scala 117:49] + node _T_1316 = and(_T_1314, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1317 = asSInt(_T_1316) @[Parameters.scala 117:52] + node _T_1319 = eq(_T_1317, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1321 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1322 = cvt(_T_1321) @[Parameters.scala 117:49] + node _T_1324 = and(_T_1322, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1325 = asSInt(_T_1324) @[Parameters.scala 117:52] + node _T_1327 = eq(_T_1325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1329 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1330 = cvt(_T_1329) @[Parameters.scala 117:49] + node _T_1332 = and(_T_1330, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1333 = asSInt(_T_1332) @[Parameters.scala 117:52] + node _T_1335 = eq(_T_1333, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1336 = or(_T_1311, _T_1319) @[Parameters.scala 133:42] + node _T_1337 = or(_T_1336, _T_1327) @[Parameters.scala 133:42] + node _T_1338 = or(_T_1337, _T_1335) @[Parameters.scala 133:42] + node _T_1339 = and(_T_1303, _T_1338) @[Parameters.scala 132:56] + node _T_1341 = or(UInt<1>("h00"), _T_1300) @[Parameters.scala 134:30] + node _T_1342 = or(_T_1341, _T_1339) @[Parameters.scala 134:30] + node _T_1343 = or(_T_1342, reset) @[Frontend.scala 48:8] + node _T_1345 = eq(_T_1343, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1345 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1346 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1348 = eq(_T_1346, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1348 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1349 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1351 = eq(_T_1349, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1351 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1353 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1354 = or(_T_1353, reset) @[Frontend.scala 48:8] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1356 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Frontend.scala:48:8)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1357 = eq(io.in[0].a.bits.mask, _T_868) @[Frontend.scala 48:8] + node _T_1358 = or(_T_1357, reset) @[Frontend.scala 48:8] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1360 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1362 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Frontend.scala 48:8] + when _T_1362 : @[Frontend.scala 48:8] + node _T_1365 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1367 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1368 = and(_T_1365, _T_1367) @[Parameters.scala 63:37] + node _T_1369 = or(UInt<1>("h00"), _T_1368) @[Parameters.scala 132:31] + node _T_1371 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1372 = cvt(_T_1371) @[Parameters.scala 117:49] + node _T_1374 = and(_T_1372, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1375 = asSInt(_T_1374) @[Parameters.scala 117:52] + node _T_1377 = eq(_T_1375, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1379 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1380 = cvt(_T_1379) @[Parameters.scala 117:49] + node _T_1382 = and(_T_1380, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1383 = asSInt(_T_1382) @[Parameters.scala 117:52] + node _T_1385 = eq(_T_1383, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1387 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1388 = cvt(_T_1387) @[Parameters.scala 117:49] + node _T_1390 = and(_T_1388, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1391 = asSInt(_T_1390) @[Parameters.scala 117:52] + node _T_1393 = eq(_T_1391, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1394 = or(_T_1377, _T_1385) @[Parameters.scala 133:42] + node _T_1395 = or(_T_1394, _T_1393) @[Parameters.scala 133:42] + node _T_1396 = and(_T_1369, _T_1395) @[Parameters.scala 132:56] + node _T_1399 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1401 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1402 = cvt(_T_1401) @[Parameters.scala 117:49] + node _T_1404 = and(_T_1402, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1405 = asSInt(_T_1404) @[Parameters.scala 117:52] + node _T_1407 = eq(_T_1405, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1409 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1410 = cvt(_T_1409) @[Parameters.scala 117:49] + node _T_1412 = and(_T_1410, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1413 = asSInt(_T_1412) @[Parameters.scala 117:52] + node _T_1415 = eq(_T_1413, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1417 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1418 = cvt(_T_1417) @[Parameters.scala 117:49] + node _T_1420 = and(_T_1418, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1421 = asSInt(_T_1420) @[Parameters.scala 117:52] + node _T_1423 = eq(_T_1421, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1425 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1426 = cvt(_T_1425) @[Parameters.scala 117:49] + node _T_1428 = and(_T_1426, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1429 = asSInt(_T_1428) @[Parameters.scala 117:52] + node _T_1431 = eq(_T_1429, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1432 = or(_T_1407, _T_1415) @[Parameters.scala 133:42] + node _T_1433 = or(_T_1432, _T_1423) @[Parameters.scala 133:42] + node _T_1434 = or(_T_1433, _T_1431) @[Parameters.scala 133:42] + node _T_1435 = and(_T_1399, _T_1434) @[Parameters.scala 132:56] + node _T_1437 = or(UInt<1>("h00"), _T_1396) @[Parameters.scala 134:30] + node _T_1438 = or(_T_1437, _T_1435) @[Parameters.scala 134:30] + node _T_1439 = or(_T_1438, reset) @[Frontend.scala 48:8] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1441 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1442 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1444 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1445 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1447 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1449 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1450 = or(_T_1449, reset) @[Frontend.scala 48:8] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1452 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Frontend.scala:48:8)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1453 = eq(io.in[0].a.bits.mask, _T_868) @[Frontend.scala 48:8] + node _T_1454 = or(_T_1453, reset) @[Frontend.scala 48:8] + node _T_1456 = eq(_T_1454, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1456 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1458 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Frontend.scala 48:8] + when _T_1458 : @[Frontend.scala 48:8] + node _T_1461 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1463 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1464 = cvt(_T_1463) @[Parameters.scala 117:49] + node _T_1466 = and(_T_1464, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1467 = asSInt(_T_1466) @[Parameters.scala 117:52] + node _T_1469 = eq(_T_1467, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1471 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1472 = cvt(_T_1471) @[Parameters.scala 117:49] + node _T_1474 = and(_T_1472, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1475 = asSInt(_T_1474) @[Parameters.scala 117:52] + node _T_1477 = eq(_T_1475, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1479 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1480 = cvt(_T_1479) @[Parameters.scala 117:49] + node _T_1482 = and(_T_1480, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1483 = asSInt(_T_1482) @[Parameters.scala 117:52] + node _T_1485 = eq(_T_1483, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1487 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1488 = cvt(_T_1487) @[Parameters.scala 117:49] + node _T_1490 = and(_T_1488, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1491 = asSInt(_T_1490) @[Parameters.scala 117:52] + node _T_1493 = eq(_T_1491, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1495 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1496 = cvt(_T_1495) @[Parameters.scala 117:49] + node _T_1498 = and(_T_1496, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1499 = asSInt(_T_1498) @[Parameters.scala 117:52] + node _T_1501 = eq(_T_1499, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1503 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1504 = cvt(_T_1503) @[Parameters.scala 117:49] + node _T_1506 = and(_T_1504, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1507 = asSInt(_T_1506) @[Parameters.scala 117:52] + node _T_1509 = eq(_T_1507, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1510 = or(_T_1469, _T_1477) @[Parameters.scala 133:42] + node _T_1511 = or(_T_1510, _T_1485) @[Parameters.scala 133:42] + node _T_1512 = or(_T_1511, _T_1493) @[Parameters.scala 133:42] + node _T_1513 = or(_T_1512, _T_1501) @[Parameters.scala 133:42] + node _T_1514 = or(_T_1513, _T_1509) @[Parameters.scala 133:42] + node _T_1515 = and(_T_1461, _T_1514) @[Parameters.scala 132:56] + node _T_1517 = or(UInt<1>("h00"), _T_1515) @[Parameters.scala 134:30] + node _T_1518 = or(_T_1517, reset) @[Frontend.scala 48:8] + node _T_1520 = eq(_T_1518, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1520 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1521 = or(_T_789[0], reset) @[Frontend.scala 48:8] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1523 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1524 = or(_T_800, reset) @[Frontend.scala 48:8] + node _T_1526 = eq(_T_1524, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1526 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1527 = eq(io.in[0].a.bits.mask, _T_868) @[Frontend.scala 48:8] + node _T_1528 = or(_T_1527, reset) @[Frontend.scala 48:8] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1530 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + when io.in[0].b.valid : @[Frontend.scala 48:8] + node _T_1532 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1533 = or(_T_1532, reset) @[Frontend.scala 48:8] + node _T_1535 = eq(_T_1533, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1535 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Frontend.scala:48:8)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1537 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1538 = cvt(_T_1537) @[Parameters.scala 117:49] + node _T_1540 = and(_T_1538, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1541 = asSInt(_T_1540) @[Parameters.scala 117:52] + node _T_1543 = eq(_T_1541, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1545 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1546 = cvt(_T_1545) @[Parameters.scala 117:49] + node _T_1548 = and(_T_1546, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1549 = asSInt(_T_1548) @[Parameters.scala 117:52] + node _T_1551 = eq(_T_1549, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1553 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1554 = cvt(_T_1553) @[Parameters.scala 117:49] + node _T_1556 = and(_T_1554, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1557 = asSInt(_T_1556) @[Parameters.scala 117:52] + node _T_1559 = eq(_T_1557, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1561 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1562 = cvt(_T_1561) @[Parameters.scala 117:49] + node _T_1564 = and(_T_1562, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1565 = asSInt(_T_1564) @[Parameters.scala 117:52] + node _T_1567 = eq(_T_1565, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1569 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1570 = cvt(_T_1569) @[Parameters.scala 117:49] + node _T_1572 = and(_T_1570, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1573 = asSInt(_T_1572) @[Parameters.scala 117:52] + node _T_1575 = eq(_T_1573, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1577 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1578 = cvt(_T_1577) @[Parameters.scala 117:49] + node _T_1580 = and(_T_1578, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1581 = asSInt(_T_1580) @[Parameters.scala 117:52] + node _T_1583 = eq(_T_1581, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1585 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1586 = cvt(_T_1585) @[Parameters.scala 117:49] + node _T_1588 = and(_T_1586, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1589 = asSInt(_T_1588) @[Parameters.scala 117:52] + node _T_1591 = eq(_T_1589, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1594 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1594 is invalid @[Parameters.scala 110:36] + _T_1594[0] <= _T_1543 @[Parameters.scala 110:36] + _T_1594[1] <= _T_1551 @[Parameters.scala 110:36] + _T_1594[2] <= _T_1559 @[Parameters.scala 110:36] + _T_1594[3] <= _T_1567 @[Parameters.scala 110:36] + _T_1594[4] <= _T_1575 @[Parameters.scala 110:36] + _T_1594[5] <= _T_1583 @[Parameters.scala 110:36] + _T_1594[6] <= _T_1591 @[Parameters.scala 110:36] + node _T_1604 = or(_T_1594[0], _T_1594[1]) @[Parameters.scala 119:64] + node _T_1605 = or(_T_1604, _T_1594[2]) @[Parameters.scala 119:64] + node _T_1606 = or(_T_1605, _T_1594[3]) @[Parameters.scala 119:64] + node _T_1607 = or(_T_1606, _T_1594[4]) @[Parameters.scala 119:64] + node _T_1608 = or(_T_1607, _T_1594[5]) @[Parameters.scala 119:64] + node _T_1609 = or(_T_1608, _T_1594[6]) @[Parameters.scala 119:64] + node _T_1611 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1612 = dshl(_T_1611, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1613 = bits(_T_1612, 7, 0) @[package.scala 19:76] + node _T_1614 = not(_T_1613) @[package.scala 19:40] + node _T_1615 = and(io.in[0].b.bits.address, _T_1614) @[Edges.scala 17:16] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1619 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1620 = dshl(UInt<1>("h01"), _T_1619) @[OneHot.scala 49:12] + node _T_1621 = bits(_T_1620, 2, 0) @[OneHot.scala 49:37] + node _T_1623 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1625 = bits(_T_1621, 2, 2) @[package.scala 44:26] + node _T_1626 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1628 = eq(_T_1626, UInt<1>("h00")) @[package.scala 46:20] + node _T_1629 = and(UInt<1>("h01"), _T_1628) @[package.scala 49:27] + node _T_1630 = and(_T_1625, _T_1629) @[package.scala 50:38] + node _T_1631 = or(_T_1623, _T_1630) @[package.scala 50:29] + node _T_1632 = and(UInt<1>("h01"), _T_1626) @[package.scala 49:27] + node _T_1633 = and(_T_1625, _T_1632) @[package.scala 50:38] + node _T_1634 = or(_T_1623, _T_1633) @[package.scala 50:29] + node _T_1635 = bits(_T_1621, 1, 1) @[package.scala 44:26] + node _T_1636 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[package.scala 46:20] + node _T_1639 = and(_T_1629, _T_1638) @[package.scala 49:27] + node _T_1640 = and(_T_1635, _T_1639) @[package.scala 50:38] + node _T_1641 = or(_T_1631, _T_1640) @[package.scala 50:29] + node _T_1642 = and(_T_1629, _T_1636) @[package.scala 49:27] + node _T_1643 = and(_T_1635, _T_1642) @[package.scala 50:38] + node _T_1644 = or(_T_1631, _T_1643) @[package.scala 50:29] + node _T_1645 = and(_T_1632, _T_1638) @[package.scala 49:27] + node _T_1646 = and(_T_1635, _T_1645) @[package.scala 50:38] + node _T_1647 = or(_T_1634, _T_1646) @[package.scala 50:29] + node _T_1648 = and(_T_1632, _T_1636) @[package.scala 49:27] + node _T_1649 = and(_T_1635, _T_1648) @[package.scala 50:38] + node _T_1650 = or(_T_1634, _T_1649) @[package.scala 50:29] + node _T_1651 = bits(_T_1621, 0, 0) @[package.scala 44:26] + node _T_1652 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1654 = eq(_T_1652, UInt<1>("h00")) @[package.scala 46:20] + node _T_1655 = and(_T_1639, _T_1654) @[package.scala 49:27] + node _T_1656 = and(_T_1651, _T_1655) @[package.scala 50:38] + node _T_1657 = or(_T_1641, _T_1656) @[package.scala 50:29] + node _T_1658 = and(_T_1639, _T_1652) @[package.scala 49:27] + node _T_1659 = and(_T_1651, _T_1658) @[package.scala 50:38] + node _T_1660 = or(_T_1641, _T_1659) @[package.scala 50:29] + node _T_1661 = and(_T_1642, _T_1654) @[package.scala 49:27] + node _T_1662 = and(_T_1651, _T_1661) @[package.scala 50:38] + node _T_1663 = or(_T_1644, _T_1662) @[package.scala 50:29] + node _T_1664 = and(_T_1642, _T_1652) @[package.scala 49:27] + node _T_1665 = and(_T_1651, _T_1664) @[package.scala 50:38] + node _T_1666 = or(_T_1644, _T_1665) @[package.scala 50:29] + node _T_1667 = and(_T_1645, _T_1654) @[package.scala 49:27] + node _T_1668 = and(_T_1651, _T_1667) @[package.scala 50:38] + node _T_1669 = or(_T_1647, _T_1668) @[package.scala 50:29] + node _T_1670 = and(_T_1645, _T_1652) @[package.scala 49:27] + node _T_1671 = and(_T_1651, _T_1670) @[package.scala 50:38] + node _T_1672 = or(_T_1647, _T_1671) @[package.scala 50:29] + node _T_1673 = and(_T_1648, _T_1654) @[package.scala 49:27] + node _T_1674 = and(_T_1651, _T_1673) @[package.scala 50:38] + node _T_1675 = or(_T_1650, _T_1674) @[package.scala 50:29] + node _T_1676 = and(_T_1648, _T_1652) @[package.scala 49:27] + node _T_1677 = and(_T_1651, _T_1676) @[package.scala 50:38] + node _T_1678 = or(_T_1650, _T_1677) @[package.scala 50:29] + node _T_1679 = cat(_T_1660, _T_1657) @[Cat.scala 30:58] + node _T_1680 = cat(_T_1666, _T_1663) @[Cat.scala 30:58] + node _T_1681 = cat(_T_1680, _T_1679) @[Cat.scala 30:58] + node _T_1682 = cat(_T_1672, _T_1669) @[Cat.scala 30:58] + node _T_1683 = cat(_T_1678, _T_1675) @[Cat.scala 30:58] + node _T_1684 = cat(_T_1683, _T_1682) @[Cat.scala 30:58] + node _T_1685 = cat(_T_1684, _T_1681) @[Cat.scala 30:58] + node _T_1687 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + when _T_1687 : @[Frontend.scala 48:8] + node _T_1689 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1691 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1692 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1694 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1696 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_1697 = or(_T_1696, reset) @[Frontend.scala 48:8] + node _T_1699 = eq(_T_1697, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1699 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1700 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1702 = eq(_T_1700, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1702 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1704 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1705 = or(_T_1704, reset) @[Frontend.scala 48:8] + node _T_1707 = eq(_T_1705, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1707 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Frontend.scala:48:8)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1708 = not(io.in[0].b.bits.mask) @[Frontend.scala 48:8] + node _T_1710 = eq(_T_1708, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1711 = or(_T_1710, reset) @[Frontend.scala 48:8] + node _T_1713 = eq(_T_1711, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1713 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1715 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Frontend.scala 48:8] + when _T_1715 : @[Frontend.scala 48:8] + node _T_1717 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1719 = eq(_T_1717, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1719 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1720 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1722 = eq(_T_1720, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1722 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1723 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1725 = eq(_T_1723, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1725 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1727 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1728 = or(_T_1727, reset) @[Frontend.scala 48:8] + node _T_1730 = eq(_T_1728, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1730 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1731 = eq(io.in[0].b.bits.mask, _T_1685) @[Frontend.scala 48:8] + node _T_1732 = or(_T_1731, reset) @[Frontend.scala 48:8] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1734 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1736 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1736 : @[Frontend.scala 48:8] + node _T_1738 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1740 = eq(_T_1738, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1740 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1741 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1743 = eq(_T_1741, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1743 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1744 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1746 = eq(_T_1744, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1746 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1748 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1749 = or(_T_1748, reset) @[Frontend.scala 48:8] + node _T_1751 = eq(_T_1749, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1751 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1752 = eq(io.in[0].b.bits.mask, _T_1685) @[Frontend.scala 48:8] + node _T_1753 = or(_T_1752, reset) @[Frontend.scala 48:8] + node _T_1755 = eq(_T_1753, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1755 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1757 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Frontend.scala 48:8] + when _T_1757 : @[Frontend.scala 48:8] + node _T_1759 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1761 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1762 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1764 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1765 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1767 = eq(_T_1765, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1767 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1769 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1770 = or(_T_1769, reset) @[Frontend.scala 48:8] + node _T_1772 = eq(_T_1770, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1772 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1773 = not(_T_1685) @[Frontend.scala 48:8] + node _T_1774 = and(io.in[0].b.bits.mask, _T_1773) @[Frontend.scala 48:8] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1777 = or(_T_1776, reset) @[Frontend.scala 48:8] + node _T_1779 = eq(_T_1777, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1779 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1781 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Frontend.scala 48:8] + when _T_1781 : @[Frontend.scala 48:8] + node _T_1783 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1785 = eq(_T_1783, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1785 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1786 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1788 = eq(_T_1786, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1788 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1789 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1791 = eq(_T_1789, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1791 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1793 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1794 = or(_T_1793, reset) @[Frontend.scala 48:8] + node _T_1796 = eq(_T_1794, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1796 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Frontend.scala:48:8)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1797 = eq(io.in[0].b.bits.mask, _T_1685) @[Frontend.scala 48:8] + node _T_1798 = or(_T_1797, reset) @[Frontend.scala 48:8] + node _T_1800 = eq(_T_1798, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1800 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1802 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Frontend.scala 48:8] + when _T_1802 : @[Frontend.scala 48:8] + node _T_1804 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1806 = eq(_T_1804, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1806 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1807 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1809 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1810 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1812 = eq(_T_1810, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1812 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1814 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1815 = or(_T_1814, reset) @[Frontend.scala 48:8] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1817 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Frontend.scala:48:8)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1818 = eq(io.in[0].b.bits.mask, _T_1685) @[Frontend.scala 48:8] + node _T_1819 = or(_T_1818, reset) @[Frontend.scala 48:8] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1821 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1823 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Frontend.scala 48:8] + when _T_1823 : @[Frontend.scala 48:8] + node _T_1825 = or(UInt<1>("h00"), reset) @[Frontend.scala 48:8] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1827 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Frontend.scala:48:8)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1828 = or(_T_1609, reset) @[Frontend.scala 48:8] + node _T_1830 = eq(_T_1828, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1830 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1831 = or(_T_1617, reset) @[Frontend.scala 48:8] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1833 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1834 = eq(io.in[0].b.bits.mask, _T_1685) @[Frontend.scala 48:8] + node _T_1835 = or(_T_1834, reset) @[Frontend.scala 48:8] + node _T_1837 = eq(_T_1835, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1837 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Frontend.scala:48:8)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + when io.in[0].c.valid : @[Frontend.scala 48:8] + node _T_1839 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1840 = or(_T_1839, reset) @[Frontend.scala 48:8] + node _T_1842 = eq(_T_1840, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1842 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Frontend.scala:48:8)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1844 = eq(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1847 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1847 is invalid @[Parameters.scala 228:27] + _T_1847[0] <= _T_1844 @[Parameters.scala 228:27] + node _T_1852 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1853 = dshl(_T_1852, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1854 = bits(_T_1853, 7, 0) @[package.scala 19:76] + node _T_1855 = not(_T_1854) @[package.scala 19:40] + node _T_1856 = and(io.in[0].c.bits.address, _T_1855) @[Edges.scala 17:16] + node _T_1858 = eq(_T_1856, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1860 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1861 = cvt(_T_1860) @[Parameters.scala 117:49] + node _T_1863 = and(_T_1861, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1864 = asSInt(_T_1863) @[Parameters.scala 117:52] + node _T_1866 = eq(_T_1864, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1868 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1869 = cvt(_T_1868) @[Parameters.scala 117:49] + node _T_1871 = and(_T_1869, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1872 = asSInt(_T_1871) @[Parameters.scala 117:52] + node _T_1874 = eq(_T_1872, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1876 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1877 = cvt(_T_1876) @[Parameters.scala 117:49] + node _T_1879 = and(_T_1877, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1880 = asSInt(_T_1879) @[Parameters.scala 117:52] + node _T_1882 = eq(_T_1880, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1884 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1885 = cvt(_T_1884) @[Parameters.scala 117:49] + node _T_1887 = and(_T_1885, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1888 = asSInt(_T_1887) @[Parameters.scala 117:52] + node _T_1890 = eq(_T_1888, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1892 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1893 = cvt(_T_1892) @[Parameters.scala 117:49] + node _T_1895 = and(_T_1893, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1896 = asSInt(_T_1895) @[Parameters.scala 117:52] + node _T_1898 = eq(_T_1896, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1900 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1901 = cvt(_T_1900) @[Parameters.scala 117:49] + node _T_1903 = and(_T_1901, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1904 = asSInt(_T_1903) @[Parameters.scala 117:52] + node _T_1906 = eq(_T_1904, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1908 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1909 = cvt(_T_1908) @[Parameters.scala 117:49] + node _T_1911 = and(_T_1909, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1912 = asSInt(_T_1911) @[Parameters.scala 117:52] + node _T_1914 = eq(_T_1912, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1917 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1917 is invalid @[Parameters.scala 110:36] + _T_1917[0] <= _T_1866 @[Parameters.scala 110:36] + _T_1917[1] <= _T_1874 @[Parameters.scala 110:36] + _T_1917[2] <= _T_1882 @[Parameters.scala 110:36] + _T_1917[3] <= _T_1890 @[Parameters.scala 110:36] + _T_1917[4] <= _T_1898 @[Parameters.scala 110:36] + _T_1917[5] <= _T_1906 @[Parameters.scala 110:36] + _T_1917[6] <= _T_1914 @[Parameters.scala 110:36] + node _T_1927 = or(_T_1917[0], _T_1917[1]) @[Parameters.scala 119:64] + node _T_1928 = or(_T_1927, _T_1917[2]) @[Parameters.scala 119:64] + node _T_1929 = or(_T_1928, _T_1917[3]) @[Parameters.scala 119:64] + node _T_1930 = or(_T_1929, _T_1917[4]) @[Parameters.scala 119:64] + node _T_1931 = or(_T_1930, _T_1917[5]) @[Parameters.scala 119:64] + node _T_1932 = or(_T_1931, _T_1917[6]) @[Parameters.scala 119:64] + node _T_1934 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Frontend.scala 48:8] + when _T_1934 : @[Frontend.scala 48:8] + node _T_1935 = or(_T_1932, reset) @[Frontend.scala 48:8] + node _T_1937 = eq(_T_1935, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1937 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1938 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1940 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1942 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_1943 = or(_T_1942, reset) @[Frontend.scala 48:8] + node _T_1945 = eq(_T_1943, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1945 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1946 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1948 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1950 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1951 = or(_T_1950, reset) @[Frontend.scala 48:8] + node _T_1953 = eq(_T_1951, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1953 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Frontend.scala:48:8)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1955 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1956 = or(_T_1955, reset) @[Frontend.scala 48:8] + node _T_1958 = eq(_T_1956, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1958 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1960 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Frontend.scala 48:8] + when _T_1960 : @[Frontend.scala 48:8] + node _T_1961 = or(_T_1932, reset) @[Frontend.scala 48:8] + node _T_1963 = eq(_T_1961, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1963 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1964 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_1966 = eq(_T_1964, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1966 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1968 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_1969 = or(_T_1968, reset) @[Frontend.scala 48:8] + node _T_1971 = eq(_T_1969, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1971 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1972 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_1974 = eq(_T_1972, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1974 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1976 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1977 = or(_T_1976, reset) @[Frontend.scala 48:8] + node _T_1979 = eq(_T_1977, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1979 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Frontend.scala:48:8)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1981 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_1982 = or(_T_1981, reset) @[Frontend.scala 48:8] + node _T_1984 = eq(_T_1982, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_1984 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_1986 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + when _T_1986 : @[Frontend.scala 48:8] + node _T_1989 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1991 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1992 = and(_T_1989, _T_1991) @[Parameters.scala 63:37] + node _T_1993 = or(UInt<1>("h00"), _T_1992) @[Parameters.scala 132:31] + node _T_1995 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1996 = cvt(_T_1995) @[Parameters.scala 117:49] + node _T_1998 = and(_T_1996, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1999 = asSInt(_T_1998) @[Parameters.scala 117:52] + node _T_2001 = eq(_T_1999, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2003 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2004 = cvt(_T_2003) @[Parameters.scala 117:49] + node _T_2006 = and(_T_2004, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2007 = asSInt(_T_2006) @[Parameters.scala 117:52] + node _T_2009 = eq(_T_2007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2010 = or(_T_2001, _T_2009) @[Parameters.scala 133:42] + node _T_2011 = and(_T_1993, _T_2010) @[Parameters.scala 132:56] + node _T_2014 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2016 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2017 = cvt(_T_2016) @[Parameters.scala 117:49] + node _T_2019 = and(_T_2017, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2020 = asSInt(_T_2019) @[Parameters.scala 117:52] + node _T_2022 = eq(_T_2020, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2024 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2025 = cvt(_T_2024) @[Parameters.scala 117:49] + node _T_2027 = and(_T_2025, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2028 = asSInt(_T_2027) @[Parameters.scala 117:52] + node _T_2030 = eq(_T_2028, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2032 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2033 = cvt(_T_2032) @[Parameters.scala 117:49] + node _T_2035 = and(_T_2033, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2036 = asSInt(_T_2035) @[Parameters.scala 117:52] + node _T_2038 = eq(_T_2036, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2040 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2041 = cvt(_T_2040) @[Parameters.scala 117:49] + node _T_2043 = and(_T_2041, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2044 = asSInt(_T_2043) @[Parameters.scala 117:52] + node _T_2046 = eq(_T_2044, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2047 = or(_T_2022, _T_2030) @[Parameters.scala 133:42] + node _T_2048 = or(_T_2047, _T_2038) @[Parameters.scala 133:42] + node _T_2049 = or(_T_2048, _T_2046) @[Parameters.scala 133:42] + node _T_2050 = and(_T_2014, _T_2049) @[Parameters.scala 132:56] + node _T_2052 = or(UInt<1>("h00"), _T_2011) @[Parameters.scala 134:30] + node _T_2053 = or(_T_2052, _T_2050) @[Parameters.scala 134:30] + node _T_2054 = or(_T_2053, reset) @[Frontend.scala 48:8] + node _T_2056 = eq(_T_2054, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2056 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2057 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_2059 = eq(_T_2057, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2059 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2061 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_2062 = or(_T_2061, reset) @[Frontend.scala 48:8] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2064 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2065 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_2067 = eq(_T_2065, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2067 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2069 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2070 = or(_T_2069, reset) @[Frontend.scala 48:8] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2072 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Frontend.scala:48:8)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2074 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2075 = or(_T_2074, reset) @[Frontend.scala 48:8] + node _T_2077 = eq(_T_2075, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2077 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2079 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Frontend.scala 48:8] + when _T_2079 : @[Frontend.scala 48:8] + node _T_2082 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2084 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2085 = and(_T_2082, _T_2084) @[Parameters.scala 63:37] + node _T_2086 = or(UInt<1>("h00"), _T_2085) @[Parameters.scala 132:31] + node _T_2088 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2089 = cvt(_T_2088) @[Parameters.scala 117:49] + node _T_2091 = and(_T_2089, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2092 = asSInt(_T_2091) @[Parameters.scala 117:52] + node _T_2094 = eq(_T_2092, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2096 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2097 = cvt(_T_2096) @[Parameters.scala 117:49] + node _T_2099 = and(_T_2097, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2100 = asSInt(_T_2099) @[Parameters.scala 117:52] + node _T_2102 = eq(_T_2100, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2103 = or(_T_2094, _T_2102) @[Parameters.scala 133:42] + node _T_2104 = and(_T_2086, _T_2103) @[Parameters.scala 132:56] + node _T_2107 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2109 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2110 = cvt(_T_2109) @[Parameters.scala 117:49] + node _T_2112 = and(_T_2110, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2113 = asSInt(_T_2112) @[Parameters.scala 117:52] + node _T_2115 = eq(_T_2113, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2117 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2118 = cvt(_T_2117) @[Parameters.scala 117:49] + node _T_2120 = and(_T_2118, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2121 = asSInt(_T_2120) @[Parameters.scala 117:52] + node _T_2123 = eq(_T_2121, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2125 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2126 = cvt(_T_2125) @[Parameters.scala 117:49] + node _T_2128 = and(_T_2126, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2129 = asSInt(_T_2128) @[Parameters.scala 117:52] + node _T_2131 = eq(_T_2129, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2133 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2134 = cvt(_T_2133) @[Parameters.scala 117:49] + node _T_2136 = and(_T_2134, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2137 = asSInt(_T_2136) @[Parameters.scala 117:52] + node _T_2139 = eq(_T_2137, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2140 = or(_T_2115, _T_2123) @[Parameters.scala 133:42] + node _T_2141 = or(_T_2140, _T_2131) @[Parameters.scala 133:42] + node _T_2142 = or(_T_2141, _T_2139) @[Parameters.scala 133:42] + node _T_2143 = and(_T_2107, _T_2142) @[Parameters.scala 132:56] + node _T_2145 = or(UInt<1>("h00"), _T_2104) @[Parameters.scala 134:30] + node _T_2146 = or(_T_2145, _T_2143) @[Parameters.scala 134:30] + node _T_2147 = or(_T_2146, reset) @[Frontend.scala 48:8] + node _T_2149 = eq(_T_2147, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2149 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Frontend.scala:48:8)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2150 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_2152 = eq(_T_2150, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2152 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2154 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_2155 = or(_T_2154, reset) @[Frontend.scala 48:8] + node _T_2157 = eq(_T_2155, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2157 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2158 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_2160 = eq(_T_2158, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2160 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2162 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2163 = or(_T_2162, reset) @[Frontend.scala 48:8] + node _T_2165 = eq(_T_2163, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2165 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Frontend.scala:48:8)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2167 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2168 = or(_T_2167, reset) @[Frontend.scala 48:8] + node _T_2170 = eq(_T_2168, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2170 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2172 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2172 : @[Frontend.scala 48:8] + node _T_2173 = or(_T_1932, reset) @[Frontend.scala 48:8] + node _T_2175 = eq(_T_2173, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2175 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2176 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_2178 = eq(_T_2176, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2178 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2179 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_2181 = eq(_T_2179, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2181 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2183 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2184 = or(_T_2183, reset) @[Frontend.scala 48:8] + node _T_2186 = eq(_T_2184, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2186 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2188 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Frontend.scala 48:8] + when _T_2188 : @[Frontend.scala 48:8] + node _T_2189 = or(_T_1932, reset) @[Frontend.scala 48:8] + node _T_2191 = eq(_T_2189, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2191 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2192 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_2194 = eq(_T_2192, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2194 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2195 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_2197 = eq(_T_2195, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2197 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2199 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2200 = or(_T_2199, reset) @[Frontend.scala 48:8] + node _T_2202 = eq(_T_2200, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2202 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2204 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Frontend.scala 48:8] + when _T_2204 : @[Frontend.scala 48:8] + node _T_2205 = or(_T_1932, reset) @[Frontend.scala 48:8] + node _T_2207 = eq(_T_2205, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2207 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Frontend.scala:48:8)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2208 = or(_T_1847[0], reset) @[Frontend.scala 48:8] + node _T_2210 = eq(_T_2208, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2210 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2211 = or(_T_1858, reset) @[Frontend.scala 48:8] + node _T_2213 = eq(_T_2211, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2213 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2215 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2216 = or(_T_2215, reset) @[Frontend.scala 48:8] + node _T_2218 = eq(_T_2216, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2218 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2220 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2221 = or(_T_2220, reset) @[Frontend.scala 48:8] + node _T_2223 = eq(_T_2221, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2223 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + when io.in[0].d.valid : @[Frontend.scala 48:8] + node _T_2225 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2226 = or(_T_2225, reset) @[Frontend.scala 48:8] + node _T_2228 = eq(_T_2226, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2228 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Frontend.scala:48:8)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2230 = eq(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_2233 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2233 is invalid @[Parameters.scala 228:27] + _T_2233[0] <= _T_2230 @[Parameters.scala 228:27] + node _T_2238 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2239 = dshl(_T_2238, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2240 = bits(_T_2239, 7, 0) @[package.scala 19:76] + node _T_2241 = not(_T_2240) @[package.scala 19:40] + node _T_2242 = and(io.in[0].d.bits.addr_lo, _T_2241) @[Edges.scala 17:16] + node _T_2244 = eq(_T_2242, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2246 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[Frontend.scala 48:8] + node _T_2248 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + when _T_2248 : @[Frontend.scala 48:8] + node _T_2249 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2251 = eq(_T_2249, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2251 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2252 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2254 = eq(_T_2252, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2254 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2255 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2257 = eq(_T_2255, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2257 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2259 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_2260 = or(_T_2259, reset) @[Frontend.scala 48:8] + node _T_2262 = eq(_T_2260, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2262 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2264 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2265 = or(_T_2264, reset) @[Frontend.scala 48:8] + node _T_2267 = eq(_T_2265, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2267 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2269 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2270 = or(_T_2269, reset) @[Frontend.scala 48:8] + node _T_2272 = eq(_T_2270, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2272 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2274 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Frontend.scala 48:8] + when _T_2274 : @[Frontend.scala 48:8] + node _T_2275 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2277 = eq(_T_2275, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2277 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2278 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2280 = eq(_T_2278, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2280 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2281 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2283 = eq(_T_2281, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2283 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2285 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_2286 = or(_T_2285, reset) @[Frontend.scala 48:8] + node _T_2288 = eq(_T_2286, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2288 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2290 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2291 = or(_T_2290, reset) @[Frontend.scala 48:8] + node _T_2293 = eq(_T_2291, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2293 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Frontend.scala:48:8)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2295 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Frontend.scala 48:8] + when _T_2295 : @[Frontend.scala 48:8] + node _T_2296 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2298 = eq(_T_2296, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2298 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2299 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2301 = eq(_T_2299, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2301 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2302 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2304 = eq(_T_2302, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2304 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2306 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 48:8] + node _T_2307 = or(_T_2306, reset) @[Frontend.scala 48:8] + node _T_2309 = eq(_T_2307, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2309 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Frontend.scala:48:8)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2311 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2312 = or(_T_2311, reset) @[Frontend.scala 48:8] + node _T_2314 = eq(_T_2312, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2314 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Frontend.scala:48:8)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2316 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2316 : @[Frontend.scala 48:8] + node _T_2317 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2319 = eq(_T_2317, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2319 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2320 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2322 = eq(_T_2320, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2322 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2323 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2325 = eq(_T_2323, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2325 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2327 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2328 = or(_T_2327, reset) @[Frontend.scala 48:8] + node _T_2330 = eq(_T_2328, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2330 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2332 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Frontend.scala 48:8] + when _T_2332 : @[Frontend.scala 48:8] + node _T_2333 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2335 = eq(_T_2333, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2335 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2336 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2338 = eq(_T_2336, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2338 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2339 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2341 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2343 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2344 = or(_T_2343, reset) @[Frontend.scala 48:8] + node _T_2346 = eq(_T_2344, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2346 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2348 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Frontend.scala 48:8] + when _T_2348 : @[Frontend.scala 48:8] + node _T_2349 = or(_T_2233[0], reset) @[Frontend.scala 48:8] + node _T_2351 = eq(_T_2349, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2351 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2352 = or(_T_2244, reset) @[Frontend.scala 48:8] + node _T_2354 = eq(_T_2352, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2354 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Frontend.scala:48:8)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2355 = or(_T_2246, reset) @[Frontend.scala 48:8] + node _T_2357 = eq(_T_2355, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2357 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2359 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2360 = or(_T_2359, reset) @[Frontend.scala 48:8] + node _T_2362 = eq(_T_2360, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2362 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Frontend.scala:48:8)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2364 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2365 = or(_T_2364, reset) @[Frontend.scala 48:8] + node _T_2367 = eq(_T_2365, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2367 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Frontend.scala:48:8)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + when io.in[0].e.valid : @[Frontend.scala 48:8] + node _T_2369 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[Frontend.scala 48:8] + node _T_2370 = or(_T_2369, reset) @[Frontend.scala 48:8] + node _T_2372 = eq(_T_2370, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2372 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Frontend.scala:48:8)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2373 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2375 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2376 = dshl(_T_2375, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2377 = bits(_T_2376, 7, 0) @[package.scala 19:76] + node _T_2378 = not(_T_2377) @[package.scala 19:40] + node _T_2379 = shr(_T_2378, 3) @[Edges.scala 198:59] + node _T_2380 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2382 = eq(_T_2380, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2384 = mux(_T_2382, _T_2379, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2386 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2388 = sub(_T_2386, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2389 = asUInt(_T_2388) @[Edges.scala 208:28] + node _T_2390 = tail(_T_2389, 1) @[Edges.scala 208:28] + node _T_2392 = eq(_T_2386, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2394 = eq(_T_2386, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2396 = eq(_T_2384, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2397 = or(_T_2394, _T_2396) @[Edges.scala 210:37] + node _T_2398 = and(_T_2397, _T_2373) @[Edges.scala 211:22] + node _T_2399 = not(_T_2390) @[Edges.scala 212:27] + node _T_2400 = and(_T_2384, _T_2399) @[Edges.scala 212:25] + when _T_2373 : @[Edges.scala 213:17] + node _T_2401 = mux(_T_2392, _T_2384, _T_2390) @[Edges.scala 214:21] + _T_2386 <= _T_2401 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2403 : UInt, clock @[Frontend.scala 48:8] + reg _T_2405 : UInt, clock @[Frontend.scala 48:8] + reg _T_2407 : UInt, clock @[Frontend.scala 48:8] + reg _T_2409 : UInt, clock @[Frontend.scala 48:8] + reg _T_2411 : UInt, clock @[Frontend.scala 48:8] + node _T_2413 = eq(_T_2392, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2414 = and(io.in[0].a.valid, _T_2413) @[Frontend.scala 48:8] + when _T_2414 : @[Frontend.scala 48:8] + node _T_2415 = eq(io.in[0].a.bits.opcode, _T_2403) @[Frontend.scala 48:8] + node _T_2416 = or(_T_2415, reset) @[Frontend.scala 48:8] + node _T_2418 = eq(_T_2416, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2418 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2419 = eq(io.in[0].a.bits.param, _T_2405) @[Frontend.scala 48:8] + node _T_2420 = or(_T_2419, reset) @[Frontend.scala 48:8] + node _T_2422 = eq(_T_2420, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2422 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2423 = eq(io.in[0].a.bits.size, _T_2407) @[Frontend.scala 48:8] + node _T_2424 = or(_T_2423, reset) @[Frontend.scala 48:8] + node _T_2426 = eq(_T_2424, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2426 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2427 = eq(io.in[0].a.bits.source, _T_2409) @[Frontend.scala 48:8] + node _T_2428 = or(_T_2427, reset) @[Frontend.scala 48:8] + node _T_2430 = eq(_T_2428, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2430 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2431 = eq(io.in[0].a.bits.address, _T_2411) @[Frontend.scala 48:8] + node _T_2432 = or(_T_2431, reset) @[Frontend.scala 48:8] + node _T_2434 = eq(_T_2432, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2434 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2435 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2436 = and(_T_2435, _T_2392) @[Frontend.scala 48:8] + when _T_2436 : @[Frontend.scala 48:8] + _T_2403 <= io.in[0].a.bits.opcode @[Frontend.scala 48:8] + _T_2405 <= io.in[0].a.bits.param @[Frontend.scala 48:8] + _T_2407 <= io.in[0].a.bits.size @[Frontend.scala 48:8] + _T_2409 <= io.in[0].a.bits.source @[Frontend.scala 48:8] + _T_2411 <= io.in[0].a.bits.address @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2437 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2439 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2440 = dshl(_T_2439, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2441 = bits(_T_2440, 7, 0) @[package.scala 19:76] + node _T_2442 = not(_T_2441) @[package.scala 19:40] + node _T_2443 = shr(_T_2442, 3) @[Edges.scala 198:59] + node _T_2444 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2446 = eq(_T_2444, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2449 = mux(UInt<1>("h00"), _T_2443, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2451 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2453 = sub(_T_2451, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2454 = asUInt(_T_2453) @[Edges.scala 208:28] + node _T_2455 = tail(_T_2454, 1) @[Edges.scala 208:28] + node _T_2457 = eq(_T_2451, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2459 = eq(_T_2451, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2461 = eq(_T_2449, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2462 = or(_T_2459, _T_2461) @[Edges.scala 210:37] + node _T_2463 = and(_T_2462, _T_2437) @[Edges.scala 211:22] + node _T_2464 = not(_T_2455) @[Edges.scala 212:27] + node _T_2465 = and(_T_2449, _T_2464) @[Edges.scala 212:25] + when _T_2437 : @[Edges.scala 213:17] + node _T_2466 = mux(_T_2457, _T_2449, _T_2455) @[Edges.scala 214:21] + _T_2451 <= _T_2466 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2468 : UInt, clock @[Frontend.scala 48:8] + reg _T_2470 : UInt, clock @[Frontend.scala 48:8] + reg _T_2472 : UInt, clock @[Frontend.scala 48:8] + reg _T_2474 : UInt, clock @[Frontend.scala 48:8] + reg _T_2476 : UInt, clock @[Frontend.scala 48:8] + node _T_2478 = eq(_T_2457, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2479 = and(io.in[0].b.valid, _T_2478) @[Frontend.scala 48:8] + when _T_2479 : @[Frontend.scala 48:8] + node _T_2480 = eq(io.in[0].b.bits.opcode, _T_2468) @[Frontend.scala 48:8] + node _T_2481 = or(_T_2480, reset) @[Frontend.scala 48:8] + node _T_2483 = eq(_T_2481, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2483 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2484 = eq(io.in[0].b.bits.param, _T_2470) @[Frontend.scala 48:8] + node _T_2485 = or(_T_2484, reset) @[Frontend.scala 48:8] + node _T_2487 = eq(_T_2485, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2487 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2488 = eq(io.in[0].b.bits.size, _T_2472) @[Frontend.scala 48:8] + node _T_2489 = or(_T_2488, reset) @[Frontend.scala 48:8] + node _T_2491 = eq(_T_2489, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2491 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2492 = eq(io.in[0].b.bits.source, _T_2474) @[Frontend.scala 48:8] + node _T_2493 = or(_T_2492, reset) @[Frontend.scala 48:8] + node _T_2495 = eq(_T_2493, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2495 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2496 = eq(io.in[0].b.bits.address, _T_2476) @[Frontend.scala 48:8] + node _T_2497 = or(_T_2496, reset) @[Frontend.scala 48:8] + node _T_2499 = eq(_T_2497, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2499 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2500 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2501 = and(_T_2500, _T_2457) @[Frontend.scala 48:8] + when _T_2501 : @[Frontend.scala 48:8] + _T_2468 <= io.in[0].b.bits.opcode @[Frontend.scala 48:8] + _T_2470 <= io.in[0].b.bits.param @[Frontend.scala 48:8] + _T_2472 <= io.in[0].b.bits.size @[Frontend.scala 48:8] + _T_2474 <= io.in[0].b.bits.source @[Frontend.scala 48:8] + _T_2476 <= io.in[0].b.bits.address @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2502 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2504 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2505 = dshl(_T_2504, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2506 = bits(_T_2505, 7, 0) @[package.scala 19:76] + node _T_2507 = not(_T_2506) @[package.scala 19:40] + node _T_2508 = shr(_T_2507, 3) @[Edges.scala 198:59] + node _T_2509 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2512 = mux(UInt<1>("h00"), _T_2508, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2514 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2516 = sub(_T_2514, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2517 = asUInt(_T_2516) @[Edges.scala 208:28] + node _T_2518 = tail(_T_2517, 1) @[Edges.scala 208:28] + node _T_2520 = eq(_T_2514, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2522 = eq(_T_2514, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2524 = eq(_T_2512, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2525 = or(_T_2522, _T_2524) @[Edges.scala 210:37] + node _T_2526 = and(_T_2525, _T_2502) @[Edges.scala 211:22] + node _T_2527 = not(_T_2518) @[Edges.scala 212:27] + node _T_2528 = and(_T_2512, _T_2527) @[Edges.scala 212:25] + when _T_2502 : @[Edges.scala 213:17] + node _T_2529 = mux(_T_2520, _T_2512, _T_2518) @[Edges.scala 214:21] + _T_2514 <= _T_2529 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2531 : UInt, clock @[Frontend.scala 48:8] + reg _T_2533 : UInt, clock @[Frontend.scala 48:8] + reg _T_2535 : UInt, clock @[Frontend.scala 48:8] + reg _T_2537 : UInt, clock @[Frontend.scala 48:8] + reg _T_2539 : UInt, clock @[Frontend.scala 48:8] + node _T_2541 = eq(_T_2520, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2542 = and(io.in[0].c.valid, _T_2541) @[Frontend.scala 48:8] + when _T_2542 : @[Frontend.scala 48:8] + node _T_2543 = eq(io.in[0].c.bits.opcode, _T_2531) @[Frontend.scala 48:8] + node _T_2544 = or(_T_2543, reset) @[Frontend.scala 48:8] + node _T_2546 = eq(_T_2544, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2546 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2547 = eq(io.in[0].c.bits.param, _T_2533) @[Frontend.scala 48:8] + node _T_2548 = or(_T_2547, reset) @[Frontend.scala 48:8] + node _T_2550 = eq(_T_2548, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2550 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2551 = eq(io.in[0].c.bits.size, _T_2535) @[Frontend.scala 48:8] + node _T_2552 = or(_T_2551, reset) @[Frontend.scala 48:8] + node _T_2554 = eq(_T_2552, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2554 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2555 = eq(io.in[0].c.bits.source, _T_2537) @[Frontend.scala 48:8] + node _T_2556 = or(_T_2555, reset) @[Frontend.scala 48:8] + node _T_2558 = eq(_T_2556, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2558 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2559 = eq(io.in[0].c.bits.address, _T_2539) @[Frontend.scala 48:8] + node _T_2560 = or(_T_2559, reset) @[Frontend.scala 48:8] + node _T_2562 = eq(_T_2560, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2562 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2563 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2564 = and(_T_2563, _T_2520) @[Frontend.scala 48:8] + when _T_2564 : @[Frontend.scala 48:8] + _T_2531 <= io.in[0].c.bits.opcode @[Frontend.scala 48:8] + _T_2533 <= io.in[0].c.bits.param @[Frontend.scala 48:8] + _T_2535 <= io.in[0].c.bits.size @[Frontend.scala 48:8] + _T_2537 <= io.in[0].c.bits.source @[Frontend.scala 48:8] + _T_2539 <= io.in[0].c.bits.address @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2565 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2567 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2568 = dshl(_T_2567, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2569 = bits(_T_2568, 7, 0) @[package.scala 19:76] + node _T_2570 = not(_T_2569) @[package.scala 19:40] + node _T_2571 = shr(_T_2570, 3) @[Edges.scala 198:59] + node _T_2572 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2574 = mux(_T_2572, _T_2571, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2576 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2578 = sub(_T_2576, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2579 = asUInt(_T_2578) @[Edges.scala 208:28] + node _T_2580 = tail(_T_2579, 1) @[Edges.scala 208:28] + node _T_2582 = eq(_T_2576, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2584 = eq(_T_2576, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2586 = eq(_T_2574, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2587 = or(_T_2584, _T_2586) @[Edges.scala 210:37] + node _T_2588 = and(_T_2587, _T_2565) @[Edges.scala 211:22] + node _T_2589 = not(_T_2580) @[Edges.scala 212:27] + node _T_2590 = and(_T_2574, _T_2589) @[Edges.scala 212:25] + when _T_2565 : @[Edges.scala 213:17] + node _T_2591 = mux(_T_2582, _T_2574, _T_2580) @[Edges.scala 214:21] + _T_2576 <= _T_2591 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2593 : UInt, clock @[Frontend.scala 48:8] + reg _T_2595 : UInt, clock @[Frontend.scala 48:8] + reg _T_2597 : UInt, clock @[Frontend.scala 48:8] + reg _T_2599 : UInt, clock @[Frontend.scala 48:8] + reg _T_2601 : UInt, clock @[Frontend.scala 48:8] + reg _T_2603 : UInt, clock @[Frontend.scala 48:8] + node _T_2605 = eq(_T_2582, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2606 = and(io.in[0].d.valid, _T_2605) @[Frontend.scala 48:8] + when _T_2606 : @[Frontend.scala 48:8] + node _T_2607 = eq(io.in[0].d.bits.opcode, _T_2593) @[Frontend.scala 48:8] + node _T_2608 = or(_T_2607, reset) @[Frontend.scala 48:8] + node _T_2610 = eq(_T_2608, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2610 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2611 = eq(io.in[0].d.bits.param, _T_2595) @[Frontend.scala 48:8] + node _T_2612 = or(_T_2611, reset) @[Frontend.scala 48:8] + node _T_2614 = eq(_T_2612, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2614 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2615 = eq(io.in[0].d.bits.size, _T_2597) @[Frontend.scala 48:8] + node _T_2616 = or(_T_2615, reset) @[Frontend.scala 48:8] + node _T_2618 = eq(_T_2616, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2618 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2619 = eq(io.in[0].d.bits.source, _T_2599) @[Frontend.scala 48:8] + node _T_2620 = or(_T_2619, reset) @[Frontend.scala 48:8] + node _T_2622 = eq(_T_2620, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2622 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2623 = eq(io.in[0].d.bits.sink, _T_2601) @[Frontend.scala 48:8] + node _T_2624 = or(_T_2623, reset) @[Frontend.scala 48:8] + node _T_2626 = eq(_T_2624, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2626 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2627 = eq(io.in[0].d.bits.addr_lo, _T_2603) @[Frontend.scala 48:8] + node _T_2628 = or(_T_2627, reset) @[Frontend.scala 48:8] + node _T_2630 = eq(_T_2628, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2630 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Frontend.scala:48:8)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2631 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2632 = and(_T_2631, _T_2582) @[Frontend.scala 48:8] + when _T_2632 : @[Frontend.scala 48:8] + _T_2593 <= io.in[0].d.bits.opcode @[Frontend.scala 48:8] + _T_2595 <= io.in[0].d.bits.param @[Frontend.scala 48:8] + _T_2597 <= io.in[0].d.bits.size @[Frontend.scala 48:8] + _T_2599 <= io.in[0].d.bits.source @[Frontend.scala 48:8] + _T_2601 <= io.in[0].d.bits.sink @[Frontend.scala 48:8] + _T_2603 <= io.in[0].d.bits.addr_lo @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + reg _T_2634 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_2635 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2637 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2638 = dshl(_T_2637, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2639 = bits(_T_2638, 7, 0) @[package.scala 19:76] + node _T_2640 = not(_T_2639) @[package.scala 19:40] + node _T_2641 = shr(_T_2640, 3) @[Edges.scala 198:59] + node _T_2642 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2644 = eq(_T_2642, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2646 = mux(_T_2644, _T_2641, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2648 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2650 = sub(_T_2648, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2651 = asUInt(_T_2650) @[Edges.scala 208:28] + node _T_2652 = tail(_T_2651, 1) @[Edges.scala 208:28] + node _T_2654 = eq(_T_2648, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2656 = eq(_T_2648, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2658 = eq(_T_2646, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2659 = or(_T_2656, _T_2658) @[Edges.scala 210:37] + node _T_2660 = and(_T_2659, _T_2635) @[Edges.scala 211:22] + node _T_2661 = not(_T_2652) @[Edges.scala 212:27] + node _T_2662 = and(_T_2646, _T_2661) @[Edges.scala 212:25] + when _T_2635 : @[Edges.scala 213:17] + node _T_2663 = mux(_T_2654, _T_2646, _T_2652) @[Edges.scala 214:21] + _T_2648 <= _T_2663 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2664 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2666 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2667 = dshl(_T_2666, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2668 = bits(_T_2667, 7, 0) @[package.scala 19:76] + node _T_2669 = not(_T_2668) @[package.scala 19:40] + node _T_2670 = shr(_T_2669, 3) @[Edges.scala 198:59] + node _T_2671 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2673 = mux(_T_2671, _T_2670, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2675 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2677 = sub(_T_2675, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2678 = asUInt(_T_2677) @[Edges.scala 208:28] + node _T_2679 = tail(_T_2678, 1) @[Edges.scala 208:28] + node _T_2681 = eq(_T_2675, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2683 = eq(_T_2675, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2685 = eq(_T_2673, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2686 = or(_T_2683, _T_2685) @[Edges.scala 210:37] + node _T_2687 = and(_T_2686, _T_2664) @[Edges.scala 211:22] + node _T_2688 = not(_T_2679) @[Edges.scala 212:27] + node _T_2689 = and(_T_2673, _T_2688) @[Edges.scala 212:25] + when _T_2664 : @[Edges.scala 213:17] + node _T_2690 = mux(_T_2681, _T_2673, _T_2679) @[Edges.scala 214:21] + _T_2675 <= _T_2690 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2692 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + node _T_2693 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Frontend.scala 48:8] + node _T_2694 = or(_T_2692, _T_2693) @[Frontend.scala 48:8] + node _T_2696 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2697 = or(_T_2694, _T_2696) @[Frontend.scala 48:8] + node _T_2699 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2700 = or(_T_2697, _T_2699) @[Frontend.scala 48:8] + node _T_2701 = or(_T_2700, reset) @[Frontend.scala 48:8] + node _T_2703 = eq(_T_2701, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2703 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Frontend.scala:48:8)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + wire _T_2705 : UInt<1> + _T_2705 is invalid + _T_2705 <= UInt<1>("h00") + node _T_2706 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2706 : @[Frontend.scala 48:8] + when _T_2659 : @[Frontend.scala 48:8] + node _T_2708 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2705 <= _T_2708 @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2709 = dshr(_T_2634, io.in[0].a.bits.source) @[Frontend.scala 48:8] + node _T_2710 = bits(_T_2709, 0, 0) @[Frontend.scala 48:8] + node _T_2712 = eq(_T_2710, UInt<1>("h00")) @[Frontend.scala 48:8] + node _T_2713 = or(_T_2712, reset) @[Frontend.scala 48:8] + node _T_2715 = eq(_T_2713, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2715 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Frontend.scala:48:8)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + wire _T_2717 : UInt<1> + _T_2717 is invalid + _T_2717 <= UInt<1>("h00") + node _T_2718 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2720 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 48:8] + node _T_2721 = and(_T_2718, _T_2720) @[Frontend.scala 48:8] + when _T_2721 : @[Frontend.scala 48:8] + when _T_2686 : @[Frontend.scala 48:8] + node _T_2723 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2717 <= _T_2723 @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2724 = or(_T_2705, _T_2634) @[Frontend.scala 48:8] + node _T_2725 = dshr(_T_2724, io.in[0].d.bits.source) @[Frontend.scala 48:8] + node _T_2726 = bits(_T_2725, 0, 0) @[Frontend.scala 48:8] + node _T_2727 = or(_T_2726, reset) @[Frontend.scala 48:8] + node _T_2729 = eq(_T_2727, UInt<1>("h00")) @[Frontend.scala 48:8] + when _T_2729 : @[Frontend.scala 48:8] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:48:8)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Frontend.scala 48:8] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + skip @[Frontend.scala 48:8] + node _T_2730 = or(_T_2634, _T_2705) @[Frontend.scala 48:8] + node _T_2731 = not(_T_2717) @[Frontend.scala 48:8] + node _T_2732 = and(_T_2730, _T_2731) @[Frontend.scala 48:8] + _T_2634 <= _T_2732 @[Frontend.scala 48:8] + + module TLB_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {vaddr : UInt<40>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, paddr : UInt<32>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, cacheable : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>}}, flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} + + io is invalid + io is invalid + reg valid : UInt<9>, clock with : (reset => (reset, UInt<9>("h00"))) @[TLB.scala 45:18] + reg ppns : UInt<20>[9], clock @[TLB.scala 46:17] + reg tags : UInt<27>[9], clock @[TLB.scala 47:17] + reg levels : UInt<2>[9], clock @[TLB.scala 48:19] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[TLB.scala 51:18] + reg r_refill_tag : UInt<27>, clock @[TLB.scala 52:25] + reg r_refill_waddr : UInt<3>, clock @[TLB.scala 53:27] + reg r_req : {vaddr : UInt<40>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock @[TLB.scala 54:18] + node _T_272 = eq(io.req.bits.instruction, UInt<1>("h00")) @[TLB.scala 56:39] + node do_mprv = and(io.ptw.status.mprv, _T_272) @[TLB.scala 56:36] + node priv = mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv) @[TLB.scala 57:17] + node priv_s = eq(priv, UInt<1>("h01")) @[TLB.scala 58:21] + node _T_275 = leq(priv, UInt<1>("h01")) @[TLB.scala 59:27] + node _T_277 = eq(io.ptw.status.debug, UInt<1>("h00")) @[TLB.scala 59:39] + node priv_uses_vm = and(_T_275, _T_277) @[TLB.scala 59:36] + node _T_279 = bits(io.ptw.ptbr.mode, 3, 3) @[TLB.scala 60:53] + node _T_280 = and(UInt<1>("h01"), _T_279) @[TLB.scala 60:34] + node _T_281 = and(_T_280, priv_uses_vm) @[TLB.scala 60:83] + node _T_283 = eq(io.req.bits.passthrough, UInt<1>("h00")) @[TLB.scala 60:102] + node vm_enabled = and(_T_281, _T_283) @[TLB.scala 60:99] + node vpn = bits(io.req.bits.vaddr, 39, 12) @[Misc.scala 123:7] + node pgOffset = bits(io.req.bits.vaddr, 11, 0) @[Misc.scala 123:18] + node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) @[TLB.scala 64:44] + node do_refill = and(UInt<1>("h01"), io.ptw.resp.valid) @[TLB.scala 65:33] + node _T_285 = bits(vpn, 19, 0) @[TLB.scala 67:47] + node _T_286 = mux(vm_enabled, ppns[8], _T_285) @[TLB.scala 67:20] + node mpu_ppn = mux(do_refill, refill_ppn, _T_286) @[TLB.scala 66:20] + node _T_287 = bits(io.req.bits.vaddr, 11, 0) @[TLB.scala 68:52] + node mpu_physaddr = cat(mpu_ppn, _T_287) @[Cat.scala 30:58] + node _T_289 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_290 = cvt(_T_289) @[Parameters.scala 117:49] + node _T_292 = and(_T_290, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_293 = asSInt(_T_292) @[Parameters.scala 117:52] + node _T_295 = eq(_T_293, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_297 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_298 = cvt(_T_297) @[Parameters.scala 117:49] + node _T_300 = and(_T_298, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_301 = asSInt(_T_300) @[Parameters.scala 117:52] + node _T_303 = eq(_T_301, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_305 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_306 = cvt(_T_305) @[Parameters.scala 117:49] + node _T_308 = and(_T_306, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_309 = asSInt(_T_308) @[Parameters.scala 117:52] + node _T_311 = eq(_T_309, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_313 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_314 = cvt(_T_313) @[Parameters.scala 117:49] + node _T_316 = and(_T_314, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_317 = asSInt(_T_316) @[Parameters.scala 117:52] + node _T_319 = eq(_T_317, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_321 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_322 = cvt(_T_321) @[Parameters.scala 117:49] + node _T_324 = and(_T_322, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_325 = asSInt(_T_324) @[Parameters.scala 117:52] + node _T_327 = eq(_T_325, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_329 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_330 = cvt(_T_329) @[Parameters.scala 117:49] + node _T_332 = and(_T_330, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_333 = asSInt(_T_332) @[Parameters.scala 117:52] + node _T_335 = eq(_T_333, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_337 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_338 = cvt(_T_337) @[Parameters.scala 117:49] + node _T_340 = and(_T_338, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_341 = asSInt(_T_340) @[Parameters.scala 117:52] + node _T_343 = eq(_T_341, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_346 : UInt<1>[7] @[Parameters.scala 110:36] + _T_346 is invalid @[Parameters.scala 110:36] + _T_346[0] <= _T_295 @[Parameters.scala 110:36] + _T_346[1] <= _T_303 @[Parameters.scala 110:36] + _T_346[2] <= _T_311 @[Parameters.scala 110:36] + _T_346[3] <= _T_319 @[Parameters.scala 110:36] + _T_346[4] <= _T_327 @[Parameters.scala 110:36] + _T_346[5] <= _T_335 @[Parameters.scala 110:36] + _T_346[6] <= _T_343 @[Parameters.scala 110:36] + node _T_356 = or(_T_346[0], _T_346[1]) @[TLB.scala 69:67] + node _T_357 = or(_T_356, _T_346[2]) @[TLB.scala 69:67] + node _T_358 = or(_T_357, _T_346[3]) @[TLB.scala 69:67] + node _T_359 = or(_T_358, _T_346[4]) @[TLB.scala 69:67] + node _T_360 = or(_T_359, _T_346[5]) @[TLB.scala 69:67] + node legal_address = or(_T_360, _T_346[6]) @[TLB.scala 69:67] + node _T_362 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_363 = cvt(_T_362) @[Parameters.scala 117:49] + node _T_365 = and(_T_363, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_366 = asSInt(_T_365) @[Parameters.scala 117:52] + node _T_368 = eq(_T_366, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_370 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_371 = cvt(_T_370) @[Parameters.scala 117:49] + node _T_373 = and(_T_371, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_374 = asSInt(_T_373) @[Parameters.scala 117:52] + node _T_376 = eq(_T_374, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_378 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_379 = cvt(_T_378) @[Parameters.scala 117:49] + node _T_381 = and(_T_379, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_382 = asSInt(_T_381) @[Parameters.scala 117:52] + node _T_384 = eq(_T_382, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_386 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_387 = cvt(_T_386) @[Parameters.scala 117:49] + node _T_389 = and(_T_387, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_390 = asSInt(_T_389) @[Parameters.scala 117:52] + node _T_392 = eq(_T_390, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_394 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_395 = cvt(_T_394) @[Parameters.scala 117:49] + node _T_397 = and(_T_395, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_398 = asSInt(_T_397) @[Parameters.scala 117:52] + node _T_400 = eq(_T_398, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_402 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_403 = cvt(_T_402) @[Parameters.scala 117:49] + node _T_405 = and(_T_403, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_406 = asSInt(_T_405) @[Parameters.scala 117:52] + node _T_408 = eq(_T_406, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_410 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_411 = cvt(_T_410) @[Parameters.scala 117:49] + node _T_413 = and(_T_411, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_414 = asSInt(_T_413) @[Parameters.scala 117:52] + node _T_416 = eq(_T_414, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_419 : UInt<1>[7] @[Parameters.scala 112:36] + _T_419 is invalid @[Parameters.scala 112:36] + _T_419[0] <= _T_368 @[Parameters.scala 112:36] + _T_419[1] <= _T_376 @[Parameters.scala 112:36] + _T_419[2] <= _T_384 @[Parameters.scala 112:36] + _T_419[3] <= _T_392 @[Parameters.scala 112:36] + _T_419[4] <= _T_400 @[Parameters.scala 112:36] + _T_419[5] <= _T_408 @[Parameters.scala 112:36] + _T_419[6] <= _T_416 @[Parameters.scala 112:36] + node _T_437 = mux(_T_419[0], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_439 = mux(_T_419[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_441 = mux(_T_419[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_443 = mux(_T_419[3], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_445 = mux(_T_419[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_447 = mux(_T_419[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_449 = mux(_T_419[6], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_451 = or(_T_437, _T_439) @[Mux.scala 19:72] + node _T_452 = or(_T_451, _T_441) @[Mux.scala 19:72] + node _T_453 = or(_T_452, _T_443) @[Mux.scala 19:72] + node _T_454 = or(_T_453, _T_445) @[Mux.scala 19:72] + node _T_455 = or(_T_454, _T_447) @[Mux.scala 19:72] + node _T_456 = or(_T_455, _T_449) @[Mux.scala 19:72] + wire _T_458 : UInt<1> @[Mux.scala 19:72] + _T_458 is invalid @[Mux.scala 19:72] + _T_458 <= _T_456 @[Mux.scala 19:72] + node prot_r = and(legal_address, _T_458) @[TLB.scala 71:19] + node _T_460 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_461 = cvt(_T_460) @[Parameters.scala 117:49] + node _T_463 = and(_T_461, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_464 = asSInt(_T_463) @[Parameters.scala 117:52] + node _T_466 = eq(_T_464, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_468 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_469 = cvt(_T_468) @[Parameters.scala 117:49] + node _T_471 = and(_T_469, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_472 = asSInt(_T_471) @[Parameters.scala 117:52] + node _T_474 = eq(_T_472, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_476 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_477 = cvt(_T_476) @[Parameters.scala 117:49] + node _T_479 = and(_T_477, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_480 = asSInt(_T_479) @[Parameters.scala 117:52] + node _T_482 = eq(_T_480, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_484 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_485 = cvt(_T_484) @[Parameters.scala 117:49] + node _T_487 = and(_T_485, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_488 = asSInt(_T_487) @[Parameters.scala 117:52] + node _T_490 = eq(_T_488, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_492 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_493 = cvt(_T_492) @[Parameters.scala 117:49] + node _T_495 = and(_T_493, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_496 = asSInt(_T_495) @[Parameters.scala 117:52] + node _T_498 = eq(_T_496, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_500 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_501 = cvt(_T_500) @[Parameters.scala 117:49] + node _T_503 = and(_T_501, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_504 = asSInt(_T_503) @[Parameters.scala 117:52] + node _T_506 = eq(_T_504, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_508 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_509 = cvt(_T_508) @[Parameters.scala 117:49] + node _T_511 = and(_T_509, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_512 = asSInt(_T_511) @[Parameters.scala 117:52] + node _T_514 = eq(_T_512, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_517 : UInt<1>[7] @[Parameters.scala 112:36] + _T_517 is invalid @[Parameters.scala 112:36] + _T_517[0] <= _T_466 @[Parameters.scala 112:36] + _T_517[1] <= _T_474 @[Parameters.scala 112:36] + _T_517[2] <= _T_482 @[Parameters.scala 112:36] + _T_517[3] <= _T_490 @[Parameters.scala 112:36] + _T_517[4] <= _T_498 @[Parameters.scala 112:36] + _T_517[5] <= _T_506 @[Parameters.scala 112:36] + _T_517[6] <= _T_514 @[Parameters.scala 112:36] + node _T_535 = mux(_T_517[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_537 = mux(_T_517[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_539 = mux(_T_517[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_541 = mux(_T_517[3], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_543 = mux(_T_517[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_545 = mux(_T_517[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_547 = mux(_T_517[6], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_549 = or(_T_535, _T_537) @[Mux.scala 19:72] + node _T_550 = or(_T_549, _T_539) @[Mux.scala 19:72] + node _T_551 = or(_T_550, _T_541) @[Mux.scala 19:72] + node _T_552 = or(_T_551, _T_543) @[Mux.scala 19:72] + node _T_553 = or(_T_552, _T_545) @[Mux.scala 19:72] + node _T_554 = or(_T_553, _T_547) @[Mux.scala 19:72] + wire _T_556 : UInt<1> @[Mux.scala 19:72] + _T_556 is invalid @[Mux.scala 19:72] + _T_556 <= _T_554 @[Mux.scala 19:72] + node prot_w = and(legal_address, _T_556) @[TLB.scala 71:19] + node _T_558 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_559 = cvt(_T_558) @[Parameters.scala 117:49] + node _T_561 = and(_T_559, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_562 = asSInt(_T_561) @[Parameters.scala 117:52] + node _T_564 = eq(_T_562, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_566 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_567 = cvt(_T_566) @[Parameters.scala 117:49] + node _T_569 = and(_T_567, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_570 = asSInt(_T_569) @[Parameters.scala 117:52] + node _T_572 = eq(_T_570, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_574 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_575 = cvt(_T_574) @[Parameters.scala 117:49] + node _T_577 = and(_T_575, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_578 = asSInt(_T_577) @[Parameters.scala 117:52] + node _T_580 = eq(_T_578, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_582 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_583 = cvt(_T_582) @[Parameters.scala 117:49] + node _T_585 = and(_T_583, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_586 = asSInt(_T_585) @[Parameters.scala 117:52] + node _T_588 = eq(_T_586, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_590 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_591 = cvt(_T_590) @[Parameters.scala 117:49] + node _T_593 = and(_T_591, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_594 = asSInt(_T_593) @[Parameters.scala 117:52] + node _T_596 = eq(_T_594, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_598 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_599 = cvt(_T_598) @[Parameters.scala 117:49] + node _T_601 = and(_T_599, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_602 = asSInt(_T_601) @[Parameters.scala 117:52] + node _T_604 = eq(_T_602, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_606 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_607 = cvt(_T_606) @[Parameters.scala 117:49] + node _T_609 = and(_T_607, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_610 = asSInt(_T_609) @[Parameters.scala 117:52] + node _T_612 = eq(_T_610, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_615 : UInt<1>[7] @[Parameters.scala 112:36] + _T_615 is invalid @[Parameters.scala 112:36] + _T_615[0] <= _T_564 @[Parameters.scala 112:36] + _T_615[1] <= _T_572 @[Parameters.scala 112:36] + _T_615[2] <= _T_580 @[Parameters.scala 112:36] + _T_615[3] <= _T_588 @[Parameters.scala 112:36] + _T_615[4] <= _T_596 @[Parameters.scala 112:36] + _T_615[5] <= _T_604 @[Parameters.scala 112:36] + _T_615[6] <= _T_612 @[Parameters.scala 112:36] + node _T_633 = mux(_T_615[0], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_635 = mux(_T_615[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_637 = mux(_T_615[2], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_639 = mux(_T_615[3], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_641 = mux(_T_615[4], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_643 = mux(_T_615[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_645 = mux(_T_615[6], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_647 = or(_T_633, _T_635) @[Mux.scala 19:72] + node _T_648 = or(_T_647, _T_637) @[Mux.scala 19:72] + node _T_649 = or(_T_648, _T_639) @[Mux.scala 19:72] + node _T_650 = or(_T_649, _T_641) @[Mux.scala 19:72] + node _T_651 = or(_T_650, _T_643) @[Mux.scala 19:72] + node _T_652 = or(_T_651, _T_645) @[Mux.scala 19:72] + wire _T_654 : UInt<1> @[Mux.scala 19:72] + _T_654 is invalid @[Mux.scala 19:72] + _T_654 <= _T_652 @[Mux.scala 19:72] + node prot_x = and(legal_address, _T_654) @[TLB.scala 71:19] + node _T_656 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_657 = cvt(_T_656) @[Parameters.scala 117:49] + node _T_659 = and(_T_657, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_660 = asSInt(_T_659) @[Parameters.scala 117:52] + node _T_662 = eq(_T_660, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_664 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_665 = cvt(_T_664) @[Parameters.scala 117:49] + node _T_667 = and(_T_665, asSInt(UInt<33>("h0ae000000"))) @[Parameters.scala 117:52] + node _T_668 = asSInt(_T_667) @[Parameters.scala 117:52] + node _T_670 = eq(_T_668, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_672 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_673 = cvt(_T_672) @[Parameters.scala 117:49] + node _T_675 = and(_T_673, asSInt(UInt<33>("h0afff1000"))) @[Parameters.scala 117:52] + node _T_676 = asSInt(_T_675) @[Parameters.scala 117:52] + node _T_678 = eq(_T_676, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_680 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_681 = cvt(_T_680) @[Parameters.scala 117:49] + node _T_683 = and(_T_681, asSInt(UInt<33>("h0afff0000"))) @[Parameters.scala 117:52] + node _T_684 = asSInt(_T_683) @[Parameters.scala 117:52] + node _T_686 = eq(_T_684, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_688 = xor(mpu_physaddr, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_689 = cvt(_T_688) @[Parameters.scala 117:49] + node _T_691 = and(_T_689, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_692 = asSInt(_T_691) @[Parameters.scala 117:52] + node _T_694 = eq(_T_692, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_696 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_697 = cvt(_T_696) @[Parameters.scala 117:49] + node _T_699 = and(_T_697, asSInt(UInt<33>("h0a0000000"))) @[Parameters.scala 117:52] + node _T_700 = asSInt(_T_699) @[Parameters.scala 117:52] + node _T_702 = eq(_T_700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_704 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_705 = cvt(_T_704) @[Parameters.scala 117:49] + node _T_707 = and(_T_705, asSInt(UInt<33>("h0ac000000"))) @[Parameters.scala 117:52] + node _T_708 = asSInt(_T_707) @[Parameters.scala 117:52] + node _T_710 = eq(_T_708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_713 : UInt<1>[7] @[Parameters.scala 112:36] + _T_713 is invalid @[Parameters.scala 112:36] + _T_713[0] <= _T_662 @[Parameters.scala 112:36] + _T_713[1] <= _T_670 @[Parameters.scala 112:36] + _T_713[2] <= _T_678 @[Parameters.scala 112:36] + _T_713[3] <= _T_686 @[Parameters.scala 112:36] + _T_713[4] <= _T_694 @[Parameters.scala 112:36] + _T_713[5] <= _T_702 @[Parameters.scala 112:36] + _T_713[6] <= _T_710 @[Parameters.scala 112:36] + node _T_731 = mux(_T_713[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_733 = mux(_T_713[1], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_735 = mux(_T_713[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_737 = mux(_T_713[3], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_739 = mux(_T_713[4], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_741 = mux(_T_713[5], UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_743 = mux(_T_713[6], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_745 = or(_T_731, _T_733) @[Mux.scala 19:72] + node _T_746 = or(_T_745, _T_735) @[Mux.scala 19:72] + node _T_747 = or(_T_746, _T_737) @[Mux.scala 19:72] + node _T_748 = or(_T_747, _T_739) @[Mux.scala 19:72] + node _T_749 = or(_T_748, _T_741) @[Mux.scala 19:72] + node _T_750 = or(_T_749, _T_743) @[Mux.scala 19:72] + wire _T_752 : UInt<1> @[Mux.scala 19:72] + _T_752 is invalid @[Mux.scala 19:72] + _T_752 <= _T_750 @[Mux.scala 19:72] + node cacheable = and(legal_address, _T_752) @[TLB.scala 71:19] + wire _T_754 : UInt<1> + _T_754 is invalid + _T_754 <= UInt<1>("h00") + node _T_756 = eq(io.ptw.resp.bits.level, UInt<1>("h00")) @[TLB.scala 80:36] + when _T_756 : @[TLB.scala 80:43] + node _T_760 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_763 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_766 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_769 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_772 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_775 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + _T_754 <= UInt<1>("h00") @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node _T_777 = eq(io.ptw.resp.bits.level, UInt<1>("h01")) @[TLB.scala 80:36] + when _T_777 : @[TLB.scala 80:43] + node _T_779 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_780 = cvt(_T_779) @[Parameters.scala 117:49] + node _T_782 = and(_T_780, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_783 = asSInt(_T_782) @[Parameters.scala 117:52] + node _T_785 = eq(_T_783, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_787 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_788 = cvt(_T_787) @[Parameters.scala 117:49] + node _T_790 = and(_T_788, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_791 = asSInt(_T_790) @[Parameters.scala 117:52] + node _T_793 = eq(_T_791, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_795 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_796 = cvt(_T_795) @[Parameters.scala 117:49] + node _T_798 = and(_T_796, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_799 = asSInt(_T_798) @[Parameters.scala 117:52] + node _T_801 = eq(_T_799, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_803 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = or(UInt<1>("h00"), _T_785) @[TLBPermissions.scala 89:65] + node _T_812 = or(_T_811, _T_793) @[TLBPermissions.scala 89:65] + node _T_813 = or(_T_812, _T_801) @[TLBPermissions.scala 89:65] + node _T_814 = or(_T_813, _T_809) @[TLBPermissions.scala 89:65] + node _T_817 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_820 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_822 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_823 = cvt(_T_822) @[Parameters.scala 117:49] + node _T_825 = and(_T_823, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_826 = asSInt(_T_825) @[Parameters.scala 117:52] + node _T_828 = eq(_T_826, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_830 = or(UInt<1>("h00"), _T_828) @[TLBPermissions.scala 75:66] + node _T_832 = eq(_T_830, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_834 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_843 = cvt(_T_842) @[Parameters.scala 117:49] + node _T_845 = and(_T_843, asSInt(UInt<33>("h0e0000000"))) @[Parameters.scala 117:52] + node _T_846 = asSInt(_T_845) @[Parameters.scala 117:52] + node _T_848 = eq(_T_846, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_850 = or(UInt<1>("h00"), _T_840) @[TLBPermissions.scala 75:66] + node _T_851 = or(_T_850, _T_848) @[TLBPermissions.scala 75:66] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_855 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_863 = or(UInt<1>("h00"), _T_861) @[TLBPermissions.scala 73:66] + node _T_865 = xor(mpu_physaddr, UInt<27>("h04000000")) @[Parameters.scala 117:31] + node _T_866 = cvt(_T_865) @[Parameters.scala 117:49] + node _T_868 = and(_T_866, asSInt(UInt<33>("h0f4000000"))) @[Parameters.scala 117:52] + node _T_869 = asSInt(_T_868) @[Parameters.scala 117:52] + node _T_871 = eq(_T_869, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_873 = or(UInt<1>("h00"), _T_871) @[TLBPermissions.scala 73:66] + _T_754 <= _T_814 @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node _T_875 = eq(io.ptw.resp.bits.level, UInt<2>("h02")) @[TLB.scala 80:36] + when _T_875 : @[TLB.scala 80:43] + node _T_877 = xor(mpu_physaddr, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_878 = cvt(_T_877) @[Parameters.scala 117:49] + node _T_880 = and(_T_878, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_881 = asSInt(_T_880) @[Parameters.scala 117:52] + node _T_883 = eq(_T_881, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_885 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_893 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_894 = cvt(_T_893) @[Parameters.scala 117:49] + node _T_896 = and(_T_894, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_897 = asSInt(_T_896) @[Parameters.scala 117:52] + node _T_899 = eq(_T_897, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_901 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_902 = cvt(_T_901) @[Parameters.scala 117:49] + node _T_904 = and(_T_902, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_905 = asSInt(_T_904) @[Parameters.scala 117:52] + node _T_907 = eq(_T_905, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_909 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_910 = cvt(_T_909) @[Parameters.scala 117:49] + node _T_912 = and(_T_910, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_913 = asSInt(_T_912) @[Parameters.scala 117:52] + node _T_915 = eq(_T_913, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_917 = xor(mpu_physaddr, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_918 = cvt(_T_917) @[Parameters.scala 117:49] + node _T_920 = and(_T_918, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_921 = asSInt(_T_920) @[Parameters.scala 117:52] + node _T_923 = eq(_T_921, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_925 = or(UInt<1>("h00"), _T_883) @[TLBPermissions.scala 89:65] + node _T_926 = or(_T_925, _T_891) @[TLBPermissions.scala 89:65] + node _T_927 = or(_T_926, _T_899) @[TLBPermissions.scala 89:65] + node _T_928 = or(_T_927, _T_907) @[TLBPermissions.scala 89:65] + node _T_929 = or(_T_928, _T_915) @[TLBPermissions.scala 89:65] + node _T_930 = or(_T_929, _T_923) @[TLBPermissions.scala 89:65] + node _T_933 = eq(UInt<1>("h00"), UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_935 = xor(mpu_physaddr, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_936 = cvt(_T_935) @[Parameters.scala 117:49] + node _T_938 = and(_T_936, asSInt(UInt<33>("h0fbff1000"))) @[Parameters.scala 117:52] + node _T_939 = asSInt(_T_938) @[Parameters.scala 117:52] + node _T_941 = eq(_T_939, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_943 = or(UInt<1>("h00"), _T_941) @[TLBPermissions.scala 75:66] + node _T_945 = eq(_T_943, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_947 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_948 = cvt(_T_947) @[Parameters.scala 117:49] + node _T_950 = and(_T_948, asSInt(UInt<33>("h0fe000000"))) @[Parameters.scala 117:52] + node _T_951 = asSInt(_T_950) @[Parameters.scala 117:52] + node _T_953 = eq(_T_951, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_955 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_956 = cvt(_T_955) @[Parameters.scala 117:49] + node _T_958 = and(_T_956, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_959 = asSInt(_T_958) @[Parameters.scala 117:52] + node _T_961 = eq(_T_959, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_963 = or(UInt<1>("h00"), _T_953) @[TLBPermissions.scala 75:66] + node _T_964 = or(_T_963, _T_961) @[TLBPermissions.scala 75:66] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[TLBPermissions.scala 75:22] + node _T_968 = xor(mpu_physaddr, UInt<28>("h08000000")) @[Parameters.scala 117:31] + node _T_969 = cvt(_T_968) @[Parameters.scala 117:49] + node _T_971 = and(_T_969, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_972 = asSInt(_T_971) @[Parameters.scala 117:52] + node _T_974 = eq(_T_972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_976 = xor(mpu_physaddr, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_977 = cvt(_T_976) @[Parameters.scala 117:49] + node _T_979 = and(_T_977, asSInt(UInt<33>("h0f0000000"))) @[Parameters.scala 117:52] + node _T_980 = asSInt(_T_979) @[Parameters.scala 117:52] + node _T_982 = eq(_T_980, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_984 = or(UInt<1>("h00"), _T_974) @[TLBPermissions.scala 73:66] + node _T_985 = or(_T_984, _T_982) @[TLBPermissions.scala 73:66] + node _T_987 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_988 = cvt(_T_987) @[Parameters.scala 117:49] + node _T_990 = and(_T_988, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_991 = asSInt(_T_990) @[Parameters.scala 117:52] + node _T_993 = eq(_T_991, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_995 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_996 = cvt(_T_995) @[Parameters.scala 117:49] + node _T_998 = and(_T_996, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_999 = asSInt(_T_998) @[Parameters.scala 117:52] + node _T_1001 = eq(_T_999, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1003 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1004 = cvt(_T_1003) @[Parameters.scala 117:49] + node _T_1006 = and(_T_1004, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1007 = asSInt(_T_1006) @[Parameters.scala 117:52] + node _T_1009 = eq(_T_1007, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = or(UInt<1>("h00"), _T_993) @[TLBPermissions.scala 73:66] + node _T_1012 = or(_T_1011, _T_1001) @[TLBPermissions.scala 73:66] + node _T_1013 = or(_T_1012, _T_1009) @[TLBPermissions.scala 73:66] + node _T_1015 = xor(mpu_physaddr, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1016 = cvt(_T_1015) @[Parameters.scala 117:49] + node _T_1018 = and(_T_1016, asSInt(UInt<33>("h0ffff1000"))) @[Parameters.scala 117:52] + node _T_1019 = asSInt(_T_1018) @[Parameters.scala 117:52] + node _T_1021 = eq(_T_1019, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1023 = xor(mpu_physaddr, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1024 = cvt(_T_1023) @[Parameters.scala 117:49] + node _T_1026 = and(_T_1024, asSInt(UInt<33>("h0ffff0000"))) @[Parameters.scala 117:52] + node _T_1027 = asSInt(_T_1026) @[Parameters.scala 117:52] + node _T_1029 = eq(_T_1027, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1031 = xor(mpu_physaddr, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1032 = cvt(_T_1031) @[Parameters.scala 117:49] + node _T_1034 = and(_T_1032, asSInt(UInt<33>("h0fc000000"))) @[Parameters.scala 117:52] + node _T_1035 = asSInt(_T_1034) @[Parameters.scala 117:52] + node _T_1037 = eq(_T_1035, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1039 = or(UInt<1>("h00"), _T_1021) @[TLBPermissions.scala 73:66] + node _T_1040 = or(_T_1039, _T_1029) @[TLBPermissions.scala 73:66] + node _T_1041 = or(_T_1040, _T_1037) @[TLBPermissions.scala 73:66] + _T_754 <= _T_930 @[TLB.scala 80:57] + skip @[TLB.scala 80:43] + node isSpecial = eq(_T_754, UInt<1>("h00")) @[TLB.scala 82:5] + node _T_1043 = bits(vpn, 26, 0) @[TLB.scala 85:45] + node lookup_tag = cat(io.ptw.ptbr.asid, _T_1043) @[Cat.scala 30:58] + node _T_1044 = bits(valid, 0, 0) @[TLB.scala 87:25] + node _T_1046 = lt(levels[0], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1047 = bits(tags[0], 26, 18) @[TLB.scala 90:55] + node _T_1048 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1049 = eq(_T_1047, _T_1048) @[TLB.scala 90:86] + node _T_1050 = or(_T_1046, _T_1049) @[TLB.scala 90:45] + node _T_1051 = and(_T_1044, _T_1050) @[TLB.scala 90:27] + node _T_1053 = lt(levels[0], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1054 = bits(tags[0], 17, 9) @[TLB.scala 90:55] + node _T_1055 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1056 = eq(_T_1054, _T_1055) @[TLB.scala 90:86] + node _T_1057 = or(_T_1053, _T_1056) @[TLB.scala 90:45] + node _T_1058 = and(_T_1051, _T_1057) @[TLB.scala 90:27] + node _T_1060 = lt(levels[0], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1061 = bits(tags[0], 8, 0) @[TLB.scala 90:55] + node _T_1062 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1063 = eq(_T_1061, _T_1062) @[TLB.scala 90:86] + node _T_1064 = or(_T_1060, _T_1063) @[TLB.scala 90:45] + node _T_1065 = and(_T_1058, _T_1064) @[TLB.scala 90:27] + node hitsVec_0 = and(vm_enabled, _T_1065) @[TLB.scala 86:62] + node _T_1066 = bits(valid, 1, 1) @[TLB.scala 87:25] + node _T_1068 = lt(levels[1], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1069 = bits(tags[1], 26, 18) @[TLB.scala 90:55] + node _T_1070 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1071 = eq(_T_1069, _T_1070) @[TLB.scala 90:86] + node _T_1072 = or(_T_1068, _T_1071) @[TLB.scala 90:45] + node _T_1073 = and(_T_1066, _T_1072) @[TLB.scala 90:27] + node _T_1075 = lt(levels[1], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1076 = bits(tags[1], 17, 9) @[TLB.scala 90:55] + node _T_1077 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1078 = eq(_T_1076, _T_1077) @[TLB.scala 90:86] + node _T_1079 = or(_T_1075, _T_1078) @[TLB.scala 90:45] + node _T_1080 = and(_T_1073, _T_1079) @[TLB.scala 90:27] + node _T_1082 = lt(levels[1], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1083 = bits(tags[1], 8, 0) @[TLB.scala 90:55] + node _T_1084 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1085 = eq(_T_1083, _T_1084) @[TLB.scala 90:86] + node _T_1086 = or(_T_1082, _T_1085) @[TLB.scala 90:45] + node _T_1087 = and(_T_1080, _T_1086) @[TLB.scala 90:27] + node hitsVec_1 = and(vm_enabled, _T_1087) @[TLB.scala 86:62] + node _T_1088 = bits(valid, 2, 2) @[TLB.scala 87:25] + node _T_1090 = lt(levels[2], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1091 = bits(tags[2], 26, 18) @[TLB.scala 90:55] + node _T_1092 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1093 = eq(_T_1091, _T_1092) @[TLB.scala 90:86] + node _T_1094 = or(_T_1090, _T_1093) @[TLB.scala 90:45] + node _T_1095 = and(_T_1088, _T_1094) @[TLB.scala 90:27] + node _T_1097 = lt(levels[2], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1098 = bits(tags[2], 17, 9) @[TLB.scala 90:55] + node _T_1099 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1100 = eq(_T_1098, _T_1099) @[TLB.scala 90:86] + node _T_1101 = or(_T_1097, _T_1100) @[TLB.scala 90:45] + node _T_1102 = and(_T_1095, _T_1101) @[TLB.scala 90:27] + node _T_1104 = lt(levels[2], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1105 = bits(tags[2], 8, 0) @[TLB.scala 90:55] + node _T_1106 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1107 = eq(_T_1105, _T_1106) @[TLB.scala 90:86] + node _T_1108 = or(_T_1104, _T_1107) @[TLB.scala 90:45] + node _T_1109 = and(_T_1102, _T_1108) @[TLB.scala 90:27] + node hitsVec_2 = and(vm_enabled, _T_1109) @[TLB.scala 86:62] + node _T_1110 = bits(valid, 3, 3) @[TLB.scala 87:25] + node _T_1112 = lt(levels[3], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1113 = bits(tags[3], 26, 18) @[TLB.scala 90:55] + node _T_1114 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1115 = eq(_T_1113, _T_1114) @[TLB.scala 90:86] + node _T_1116 = or(_T_1112, _T_1115) @[TLB.scala 90:45] + node _T_1117 = and(_T_1110, _T_1116) @[TLB.scala 90:27] + node _T_1119 = lt(levels[3], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1120 = bits(tags[3], 17, 9) @[TLB.scala 90:55] + node _T_1121 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1122 = eq(_T_1120, _T_1121) @[TLB.scala 90:86] + node _T_1123 = or(_T_1119, _T_1122) @[TLB.scala 90:45] + node _T_1124 = and(_T_1117, _T_1123) @[TLB.scala 90:27] + node _T_1126 = lt(levels[3], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1127 = bits(tags[3], 8, 0) @[TLB.scala 90:55] + node _T_1128 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1129 = eq(_T_1127, _T_1128) @[TLB.scala 90:86] + node _T_1130 = or(_T_1126, _T_1129) @[TLB.scala 90:45] + node _T_1131 = and(_T_1124, _T_1130) @[TLB.scala 90:27] + node hitsVec_3 = and(vm_enabled, _T_1131) @[TLB.scala 86:62] + node _T_1132 = bits(valid, 4, 4) @[TLB.scala 87:25] + node _T_1134 = lt(levels[4], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1135 = bits(tags[4], 26, 18) @[TLB.scala 90:55] + node _T_1136 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1137 = eq(_T_1135, _T_1136) @[TLB.scala 90:86] + node _T_1138 = or(_T_1134, _T_1137) @[TLB.scala 90:45] + node _T_1139 = and(_T_1132, _T_1138) @[TLB.scala 90:27] + node _T_1141 = lt(levels[4], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1142 = bits(tags[4], 17, 9) @[TLB.scala 90:55] + node _T_1143 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1144 = eq(_T_1142, _T_1143) @[TLB.scala 90:86] + node _T_1145 = or(_T_1141, _T_1144) @[TLB.scala 90:45] + node _T_1146 = and(_T_1139, _T_1145) @[TLB.scala 90:27] + node _T_1148 = lt(levels[4], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1149 = bits(tags[4], 8, 0) @[TLB.scala 90:55] + node _T_1150 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1151 = eq(_T_1149, _T_1150) @[TLB.scala 90:86] + node _T_1152 = or(_T_1148, _T_1151) @[TLB.scala 90:45] + node _T_1153 = and(_T_1146, _T_1152) @[TLB.scala 90:27] + node hitsVec_4 = and(vm_enabled, _T_1153) @[TLB.scala 86:62] + node _T_1154 = bits(valid, 5, 5) @[TLB.scala 87:25] + node _T_1156 = lt(levels[5], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1157 = bits(tags[5], 26, 18) @[TLB.scala 90:55] + node _T_1158 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1159 = eq(_T_1157, _T_1158) @[TLB.scala 90:86] + node _T_1160 = or(_T_1156, _T_1159) @[TLB.scala 90:45] + node _T_1161 = and(_T_1154, _T_1160) @[TLB.scala 90:27] + node _T_1163 = lt(levels[5], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1164 = bits(tags[5], 17, 9) @[TLB.scala 90:55] + node _T_1165 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1166 = eq(_T_1164, _T_1165) @[TLB.scala 90:86] + node _T_1167 = or(_T_1163, _T_1166) @[TLB.scala 90:45] + node _T_1168 = and(_T_1161, _T_1167) @[TLB.scala 90:27] + node _T_1170 = lt(levels[5], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1171 = bits(tags[5], 8, 0) @[TLB.scala 90:55] + node _T_1172 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1173 = eq(_T_1171, _T_1172) @[TLB.scala 90:86] + node _T_1174 = or(_T_1170, _T_1173) @[TLB.scala 90:45] + node _T_1175 = and(_T_1168, _T_1174) @[TLB.scala 90:27] + node hitsVec_5 = and(vm_enabled, _T_1175) @[TLB.scala 86:62] + node _T_1176 = bits(valid, 6, 6) @[TLB.scala 87:25] + node _T_1178 = lt(levels[6], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1179 = bits(tags[6], 26, 18) @[TLB.scala 90:55] + node _T_1180 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1181 = eq(_T_1179, _T_1180) @[TLB.scala 90:86] + node _T_1182 = or(_T_1178, _T_1181) @[TLB.scala 90:45] + node _T_1183 = and(_T_1176, _T_1182) @[TLB.scala 90:27] + node _T_1185 = lt(levels[6], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1186 = bits(tags[6], 17, 9) @[TLB.scala 90:55] + node _T_1187 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1188 = eq(_T_1186, _T_1187) @[TLB.scala 90:86] + node _T_1189 = or(_T_1185, _T_1188) @[TLB.scala 90:45] + node _T_1190 = and(_T_1183, _T_1189) @[TLB.scala 90:27] + node _T_1192 = lt(levels[6], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1193 = bits(tags[6], 8, 0) @[TLB.scala 90:55] + node _T_1194 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1195 = eq(_T_1193, _T_1194) @[TLB.scala 90:86] + node _T_1196 = or(_T_1192, _T_1195) @[TLB.scala 90:45] + node _T_1197 = and(_T_1190, _T_1196) @[TLB.scala 90:27] + node hitsVec_6 = and(vm_enabled, _T_1197) @[TLB.scala 86:62] + node _T_1198 = bits(valid, 7, 7) @[TLB.scala 87:25] + node _T_1200 = lt(levels[7], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1201 = bits(tags[7], 26, 18) @[TLB.scala 90:55] + node _T_1202 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1203 = eq(_T_1201, _T_1202) @[TLB.scala 90:86] + node _T_1204 = or(_T_1200, _T_1203) @[TLB.scala 90:45] + node _T_1205 = and(_T_1198, _T_1204) @[TLB.scala 90:27] + node _T_1207 = lt(levels[7], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1208 = bits(tags[7], 17, 9) @[TLB.scala 90:55] + node _T_1209 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1210 = eq(_T_1208, _T_1209) @[TLB.scala 90:86] + node _T_1211 = or(_T_1207, _T_1210) @[TLB.scala 90:45] + node _T_1212 = and(_T_1205, _T_1211) @[TLB.scala 90:27] + node _T_1214 = lt(levels[7], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1215 = bits(tags[7], 8, 0) @[TLB.scala 90:55] + node _T_1216 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1217 = eq(_T_1215, _T_1216) @[TLB.scala 90:86] + node _T_1218 = or(_T_1214, _T_1217) @[TLB.scala 90:45] + node _T_1219 = and(_T_1212, _T_1218) @[TLB.scala 90:27] + node hitsVec_7 = and(vm_enabled, _T_1219) @[TLB.scala 86:62] + node _T_1220 = bits(valid, 8, 8) @[TLB.scala 87:25] + node _T_1222 = lt(levels[8], UInt<1>("h00")) @[TLB.scala 90:41] + node _T_1223 = bits(tags[8], 26, 18) @[TLB.scala 90:55] + node _T_1224 = bits(vpn, 26, 18) @[TLB.scala 90:93] + node _T_1225 = eq(_T_1223, _T_1224) @[TLB.scala 90:86] + node _T_1226 = or(_T_1222, _T_1225) @[TLB.scala 90:45] + node _T_1227 = and(_T_1220, _T_1226) @[TLB.scala 90:27] + node _T_1229 = lt(levels[8], UInt<1>("h01")) @[TLB.scala 90:41] + node _T_1230 = bits(tags[8], 17, 9) @[TLB.scala 90:55] + node _T_1231 = bits(vpn, 17, 9) @[TLB.scala 90:93] + node _T_1232 = eq(_T_1230, _T_1231) @[TLB.scala 90:86] + node _T_1233 = or(_T_1229, _T_1232) @[TLB.scala 90:45] + node _T_1234 = and(_T_1227, _T_1233) @[TLB.scala 90:27] + node _T_1236 = lt(levels[8], UInt<2>("h02")) @[TLB.scala 90:41] + node _T_1237 = bits(tags[8], 8, 0) @[TLB.scala 90:55] + node _T_1238 = bits(vpn, 8, 0) @[TLB.scala 90:93] + node _T_1239 = eq(_T_1237, _T_1238) @[TLB.scala 90:86] + node _T_1240 = or(_T_1236, _T_1239) @[TLB.scala 90:45] + node _T_1241 = and(_T_1234, _T_1240) @[TLB.scala 90:27] + node hitsVec_8 = and(vm_enabled, _T_1241) @[TLB.scala 86:62] + node hitsVec_9 = eq(vm_enabled, UInt<1>("h00")) @[TLB.scala 93:9] + node _T_1243 = cat(hitsVec_1, hitsVec_0) @[Cat.scala 30:58] + node _T_1244 = cat(hitsVec_4, hitsVec_3) @[Cat.scala 30:58] + node _T_1245 = cat(_T_1244, hitsVec_2) @[Cat.scala 30:58] + node _T_1246 = cat(_T_1245, _T_1243) @[Cat.scala 30:58] + node _T_1247 = cat(hitsVec_6, hitsVec_5) @[Cat.scala 30:58] + node _T_1248 = cat(hitsVec_9, hitsVec_8) @[Cat.scala 30:58] + node _T_1249 = cat(_T_1248, hitsVec_7) @[Cat.scala 30:58] + node _T_1250 = cat(_T_1249, _T_1247) @[Cat.scala 30:58] + node hits = cat(_T_1250, _T_1246) @[Cat.scala 30:58] + node _T_1252 = mux(hitsVec_0, levels[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1254 = mux(hitsVec_1, levels[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1256 = mux(hitsVec_2, levels[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1258 = mux(hitsVec_3, levels[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1260 = mux(hitsVec_4, levels[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1262 = mux(hitsVec_5, levels[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1264 = mux(hitsVec_6, levels[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1266 = mux(hitsVec_7, levels[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1268 = mux(hitsVec_8, levels[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1270 = or(_T_1252, _T_1254) @[Mux.scala 19:72] + node _T_1271 = or(_T_1270, _T_1256) @[Mux.scala 19:72] + node _T_1272 = or(_T_1271, _T_1258) @[Mux.scala 19:72] + node _T_1273 = or(_T_1272, _T_1260) @[Mux.scala 19:72] + node _T_1274 = or(_T_1273, _T_1262) @[Mux.scala 19:72] + node _T_1275 = or(_T_1274, _T_1264) @[Mux.scala 19:72] + node _T_1276 = or(_T_1275, _T_1266) @[Mux.scala 19:72] + node _T_1277 = or(_T_1276, _T_1268) @[Mux.scala 19:72] + wire level : UInt<2> @[Mux.scala 19:72] + level is invalid @[Mux.scala 19:72] + level <= _T_1277 @[Mux.scala 19:72] + node _T_1280 = mux(hitsVec_0, ppns[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1282 = mux(hitsVec_1, ppns[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1284 = mux(hitsVec_2, ppns[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1286 = mux(hitsVec_3, ppns[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1288 = mux(hitsVec_4, ppns[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1290 = mux(hitsVec_5, ppns[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1292 = mux(hitsVec_6, ppns[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1294 = mux(hitsVec_7, ppns[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1296 = mux(hitsVec_8, ppns[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1298 = or(_T_1280, _T_1282) @[Mux.scala 19:72] + node _T_1299 = or(_T_1298, _T_1284) @[Mux.scala 19:72] + node _T_1300 = or(_T_1299, _T_1286) @[Mux.scala 19:72] + node _T_1301 = or(_T_1300, _T_1288) @[Mux.scala 19:72] + node _T_1302 = or(_T_1301, _T_1290) @[Mux.scala 19:72] + node _T_1303 = or(_T_1302, _T_1292) @[Mux.scala 19:72] + node _T_1304 = or(_T_1303, _T_1294) @[Mux.scala 19:72] + node _T_1305 = or(_T_1304, _T_1296) @[Mux.scala 19:72] + wire partialPPN : UInt<20> @[Mux.scala 19:72] + partialPPN is invalid @[Mux.scala 19:72] + partialPPN <= _T_1305 @[Mux.scala 19:72] + node _T_1307 = mux(vm_enabled, partialPPN, vpn) @[TLB.scala 98:18] + node _T_1308 = bits(_T_1307, 26, 18) @[TLB.scala 98:47] + node _T_1310 = lt(level, UInt<1>("h01")) @[TLB.scala 100:33] + node _T_1312 = mux(_T_1310, vpn, UInt<1>("h00")) @[TLB.scala 100:26] + node _T_1313 = or(_T_1312, partialPPN) @[TLB.scala 100:48] + node _T_1314 = bits(_T_1313, 17, 9) @[TLB.scala 100:61] + node _T_1315 = cat(_T_1308, _T_1314) @[Cat.scala 30:58] + node _T_1317 = lt(level, UInt<2>("h02")) @[TLB.scala 100:33] + node _T_1319 = mux(_T_1317, vpn, UInt<1>("h00")) @[TLB.scala 100:26] + node _T_1320 = or(_T_1319, partialPPN) @[TLB.scala 100:48] + node _T_1321 = bits(_T_1320, 8, 0) @[TLB.scala 100:61] + node ppn = cat(_T_1315, _T_1321) @[Cat.scala 30:58] + reg u_array : UInt<9>, clock @[TLB.scala 105:20] + reg sw_array : UInt<9>, clock @[TLB.scala 106:21] + reg sx_array : UInt<9>, clock @[TLB.scala 107:21] + reg sr_array : UInt<9>, clock @[TLB.scala 108:21] + reg xr_array : UInt<9>, clock @[TLB.scala 109:21] + reg cash_array : UInt<8>, clock @[TLB.scala 110:23] + when do_refill : @[TLB.scala 111:20] + node _T_1329 = mux(isSpecial, UInt<4>("h08"), r_refill_waddr) @[TLB.scala 112:20] + ppns[_T_1329] <= io.ptw.resp.bits.pte.ppn @[TLB.scala 114:17] + tags[_T_1329] <= r_refill_tag @[TLB.scala 115:17] + levels[_T_1329] <= io.ptw.resp.bits.level @[TLB.scala 116:19] + node _T_1334 = dshl(UInt<1>("h01"), _T_1329) @[OneHot.scala 47:11] + node _T_1335 = or(valid, _T_1334) @[TLB.scala 119:20] + valid <= _T_1335 @[TLB.scala 119:11] + node _T_1336 = or(u_array, _T_1334) @[TLB.scala 120:35] + node _T_1337 = not(_T_1334) @[TLB.scala 120:53] + node _T_1338 = and(u_array, _T_1337) @[TLB.scala 120:51] + node _T_1339 = mux(io.ptw.resp.bits.pte.u, _T_1336, _T_1338) @[TLB.scala 120:19] + u_array <= _T_1339 @[TLB.scala 120:13] + node _T_1341 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1342 = and(io.ptw.resp.bits.pte.x, _T_1341) @[PTW.scala 56:44] + node _T_1343 = or(io.ptw.resp.bits.pte.r, _T_1342) @[PTW.scala 56:38] + node _T_1344 = and(io.ptw.resp.bits.pte.v, _T_1343) @[PTW.scala 56:32] + node _T_1345 = and(_T_1344, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1346 = and(_T_1345, io.ptw.resp.bits.pte.w) @[PTW.scala 61:35] + node _T_1347 = and(_T_1346, io.ptw.resp.bits.pte.d) @[PTW.scala 61:40] + node _T_1348 = or(isSpecial, prot_w) @[TLB.scala 121:44] + node _T_1349 = and(_T_1347, _T_1348) @[TLB.scala 121:30] + node _T_1350 = or(sw_array, _T_1334) @[TLB.scala 121:65] + node _T_1351 = not(_T_1334) @[TLB.scala 121:84] + node _T_1352 = and(sw_array, _T_1351) @[TLB.scala 121:82] + node _T_1353 = mux(_T_1349, _T_1350, _T_1352) @[TLB.scala 121:20] + sw_array <= _T_1353 @[TLB.scala 121:14] + node _T_1355 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1356 = and(io.ptw.resp.bits.pte.x, _T_1355) @[PTW.scala 56:44] + node _T_1357 = or(io.ptw.resp.bits.pte.r, _T_1356) @[PTW.scala 56:38] + node _T_1358 = and(io.ptw.resp.bits.pte.v, _T_1357) @[PTW.scala 56:32] + node _T_1359 = and(_T_1358, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1360 = and(_T_1359, io.ptw.resp.bits.pte.x) @[PTW.scala 62:35] + node _T_1361 = or(isSpecial, prot_x) @[TLB.scala 122:44] + node _T_1362 = and(_T_1360, _T_1361) @[TLB.scala 122:30] + node _T_1363 = or(sx_array, _T_1334) @[TLB.scala 122:65] + node _T_1364 = not(_T_1334) @[TLB.scala 122:84] + node _T_1365 = and(sx_array, _T_1364) @[TLB.scala 122:82] + node _T_1366 = mux(_T_1362, _T_1363, _T_1365) @[TLB.scala 122:20] + sx_array <= _T_1366 @[TLB.scala 122:14] + node _T_1368 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1369 = and(io.ptw.resp.bits.pte.x, _T_1368) @[PTW.scala 56:44] + node _T_1370 = or(io.ptw.resp.bits.pte.r, _T_1369) @[PTW.scala 56:38] + node _T_1371 = and(io.ptw.resp.bits.pte.v, _T_1370) @[PTW.scala 56:32] + node _T_1372 = and(_T_1371, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1373 = and(_T_1372, io.ptw.resp.bits.pte.r) @[PTW.scala 60:35] + node _T_1374 = or(isSpecial, prot_r) @[TLB.scala 123:44] + node _T_1375 = and(_T_1373, _T_1374) @[TLB.scala 123:30] + node _T_1376 = or(sr_array, _T_1334) @[TLB.scala 123:65] + node _T_1377 = not(_T_1334) @[TLB.scala 123:84] + node _T_1378 = and(sr_array, _T_1377) @[TLB.scala 123:82] + node _T_1379 = mux(_T_1375, _T_1376, _T_1378) @[TLB.scala 123:20] + sr_array <= _T_1379 @[TLB.scala 123:14] + node _T_1381 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[PTW.scala 56:47] + node _T_1382 = and(io.ptw.resp.bits.pte.x, _T_1381) @[PTW.scala 56:44] + node _T_1383 = or(io.ptw.resp.bits.pte.r, _T_1382) @[PTW.scala 56:38] + node _T_1384 = and(io.ptw.resp.bits.pte.v, _T_1383) @[PTW.scala 56:32] + node _T_1385 = and(_T_1384, io.ptw.resp.bits.pte.a) @[PTW.scala 56:52] + node _T_1386 = and(_T_1385, io.ptw.resp.bits.pte.x) @[PTW.scala 62:35] + node _T_1387 = or(isSpecial, prot_r) @[TLB.scala 124:44] + node _T_1388 = and(_T_1386, _T_1387) @[TLB.scala 124:30] + node _T_1389 = or(xr_array, _T_1334) @[TLB.scala 124:65] + node _T_1390 = not(_T_1334) @[TLB.scala 124:84] + node _T_1391 = and(xr_array, _T_1390) @[TLB.scala 124:82] + node _T_1392 = mux(_T_1388, _T_1389, _T_1391) @[TLB.scala 124:20] + xr_array <= _T_1392 @[TLB.scala 124:14] + node _T_1393 = or(cash_array, _T_1334) @[TLB.scala 125:45] + node _T_1394 = not(_T_1334) @[TLB.scala 125:66] + node _T_1395 = and(cash_array, _T_1394) @[TLB.scala 125:64] + node _T_1396 = mux(cacheable, _T_1393, _T_1395) @[TLB.scala 125:22] + cash_array <= _T_1396 @[TLB.scala 125:16] + skip @[TLB.scala 111:20] + reg _T_1398 : UInt<8>, clock @[Replacement.scala 42:22] + node _T_1399 = not(valid) @[TLB.scala 129:31] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[TLB.scala 129:31] + node _T_1403 = eq(_T_1401, UInt<1>("h00")) @[TLB.scala 129:24] + node _T_1404 = not(valid) @[TLB.scala 129:53] + node _T_1405 = bits(_T_1404, 0, 0) @[OneHot.scala 39:40] + node _T_1406 = bits(_T_1404, 1, 1) @[OneHot.scala 39:40] + node _T_1407 = bits(_T_1404, 2, 2) @[OneHot.scala 39:40] + node _T_1408 = bits(_T_1404, 3, 3) @[OneHot.scala 39:40] + node _T_1409 = bits(_T_1404, 4, 4) @[OneHot.scala 39:40] + node _T_1410 = bits(_T_1404, 5, 5) @[OneHot.scala 39:40] + node _T_1411 = bits(_T_1404, 6, 6) @[OneHot.scala 39:40] + node _T_1412 = bits(_T_1404, 7, 7) @[OneHot.scala 39:40] + node _T_1413 = bits(_T_1404, 8, 8) @[OneHot.scala 39:40] + node _T_1423 = mux(_T_1412, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 31:69] + node _T_1424 = mux(_T_1411, UInt<3>("h06"), _T_1423) @[Mux.scala 31:69] + node _T_1425 = mux(_T_1410, UInt<3>("h05"), _T_1424) @[Mux.scala 31:69] + node _T_1426 = mux(_T_1409, UInt<3>("h04"), _T_1425) @[Mux.scala 31:69] + node _T_1427 = mux(_T_1408, UInt<2>("h03"), _T_1426) @[Mux.scala 31:69] + node _T_1428 = mux(_T_1407, UInt<2>("h02"), _T_1427) @[Mux.scala 31:69] + node _T_1429 = mux(_T_1406, UInt<1>("h01"), _T_1428) @[Mux.scala 31:69] + node _T_1430 = mux(_T_1405, UInt<1>("h00"), _T_1429) @[Mux.scala 31:69] + node _T_1432 = dshr(_T_1398, UInt<1>("h01")) @[Replacement.scala 60:27] + node _T_1433 = bits(_T_1432, 0, 0) @[Replacement.scala 60:27] + node _T_1434 = cat(UInt<1>("h01"), _T_1433) @[Cat.scala 30:58] + node _T_1435 = dshr(_T_1398, _T_1434) @[Replacement.scala 60:27] + node _T_1436 = bits(_T_1435, 0, 0) @[Replacement.scala 60:27] + node _T_1437 = cat(_T_1434, _T_1436) @[Cat.scala 30:58] + node _T_1438 = dshr(_T_1398, _T_1437) @[Replacement.scala 60:27] + node _T_1439 = bits(_T_1438, 0, 0) @[Replacement.scala 60:27] + node _T_1440 = cat(_T_1437, _T_1439) @[Cat.scala 30:58] + node _T_1441 = bits(_T_1440, 2, 0) @[Replacement.scala 61:8] + node repl_waddr = mux(_T_1403, _T_1430, _T_1441) @[TLB.scala 129:23] + node _T_1443 = mux(io.ptw.status.pum, u_array, UInt<1>("h00")) @[TLB.scala 131:33] + node _T_1444 = not(_T_1443) @[TLB.scala 131:29] + node priv_ok = mux(priv_s, _T_1444, u_array) @[TLB.scala 131:20] + node _T_1445 = not(prot_w) @[TLB.scala 132:41] + node _T_1446 = shl(_T_1445, 8) @[TLB.scala 132:49] + node _T_1447 = not(_T_1446) @[TLB.scala 132:39] + node _T_1448 = and(priv_ok, _T_1447) @[TLB.scala 132:37] + node _T_1449 = and(_T_1448, sw_array) @[TLB.scala 132:66] + node w_array = cat(prot_w, _T_1449) @[Cat.scala 30:58] + node _T_1450 = not(prot_x) @[TLB.scala 133:41] + node _T_1451 = shl(_T_1450, 8) @[TLB.scala 133:49] + node _T_1452 = not(_T_1451) @[TLB.scala 133:39] + node _T_1453 = and(priv_ok, _T_1452) @[TLB.scala 133:37] + node _T_1454 = and(_T_1453, sx_array) @[TLB.scala 133:66] + node x_array = cat(prot_x, _T_1454) @[Cat.scala 30:58] + node _T_1455 = not(prot_r) @[TLB.scala 134:41] + node _T_1456 = shl(_T_1455, 8) @[TLB.scala 134:49] + node _T_1457 = not(_T_1456) @[TLB.scala 134:39] + node _T_1458 = and(priv_ok, _T_1457) @[TLB.scala 134:37] + node _T_1460 = mux(io.ptw.status.mxr, xr_array, UInt<1>("h00")) @[TLB.scala 134:83] + node _T_1461 = or(sr_array, _T_1460) @[TLB.scala 134:78] + node _T_1462 = and(_T_1458, _T_1461) @[TLB.scala 134:66] + node r_array = cat(prot_r, _T_1462) @[Cat.scala 30:58] + node _T_1463 = cat(cacheable, cacheable) @[Cat.scala 30:58] + node c_array = cat(_T_1463, cash_array) @[Cat.scala 30:58] + node _T_1464 = bits(vpn, 27, 27) @[TLB.scala 139:13] + node _T_1465 = bits(vpn, 26, 26) @[TLB.scala 139:30] + node bad_va = neq(_T_1464, _T_1465) @[TLB.scala 139:23] + node _T_1466 = bits(hits, 8, 0) @[TLB.scala 140:21] + node tlb_hit = neq(_T_1466, UInt<1>("h00")) @[TLB.scala 140:41] + node _T_1469 = eq(bad_va, UInt<1>("h00")) @[TLB.scala 141:32] + node _T_1470 = and(vm_enabled, _T_1469) @[TLB.scala 141:29] + node _T_1472 = eq(tlb_hit, UInt<1>("h00")) @[TLB.scala 141:43] + node tlb_miss = and(_T_1470, _T_1472) @[TLB.scala 141:40] + node _T_1474 = eq(tlb_miss, UInt<1>("h00")) @[TLB.scala 143:25] + node _T_1475 = and(io.req.valid, _T_1474) @[TLB.scala 143:22] + node _T_1476 = bits(hits, 8, 8) @[TLB.scala 143:43] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[TLB.scala 143:38] + node _T_1479 = and(_T_1475, _T_1478) @[TLB.scala 143:35] + when _T_1479 : @[TLB.scala 143:59] + node _T_1480 = bits(hits, 7, 0) @[TLB.scala 144:30] + node _T_1481 = bits(_T_1480, 7, 4) @[OneHot.scala 26:18] + node _T_1482 = bits(_T_1480, 3, 0) @[OneHot.scala 27:18] + node _T_1484 = neq(_T_1481, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1485 = or(_T_1481, _T_1482) @[OneHot.scala 28:28] + node _T_1486 = bits(_T_1485, 3, 2) @[OneHot.scala 26:18] + node _T_1487 = bits(_T_1485, 1, 0) @[OneHot.scala 27:18] + node _T_1489 = neq(_T_1486, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1490 = or(_T_1486, _T_1487) @[OneHot.scala 28:28] + node _T_1491 = bits(_T_1490, 1, 1) @[CircuitMath.scala 30:8] + node _T_1492 = cat(_T_1489, _T_1491) @[Cat.scala 30:58] + node _T_1493 = cat(_T_1484, _T_1492) @[Cat.scala 30:58] + node _T_1495 = bits(_T_1493, 2, 2) @[Replacement.scala 50:20] + node _T_1497 = eq(_T_1495, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1499 = dshl(UInt<1>("h01"), UInt<1>("h01")) @[Replacement.scala 51:37] + node _T_1500 = or(_T_1398, _T_1499) @[Replacement.scala 51:37] + node _T_1501 = not(_T_1398) @[Replacement.scala 51:37] + node _T_1502 = or(_T_1501, _T_1499) @[Replacement.scala 51:37] + node _T_1503 = not(_T_1502) @[Replacement.scala 51:37] + node _T_1504 = mux(_T_1497, _T_1500, _T_1503) @[Replacement.scala 51:37] + node _T_1505 = cat(UInt<1>("h01"), _T_1495) @[Cat.scala 30:58] + node _T_1506 = bits(_T_1493, 1, 1) @[Replacement.scala 50:20] + node _T_1508 = eq(_T_1506, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1510 = dshl(UInt<1>("h01"), _T_1505) @[Replacement.scala 51:37] + node _T_1511 = or(_T_1504, _T_1510) @[Replacement.scala 51:37] + node _T_1512 = not(_T_1504) @[Replacement.scala 51:37] + node _T_1513 = or(_T_1512, _T_1510) @[Replacement.scala 51:37] + node _T_1514 = not(_T_1513) @[Replacement.scala 51:37] + node _T_1515 = mux(_T_1508, _T_1511, _T_1514) @[Replacement.scala 51:37] + node _T_1516 = cat(_T_1505, _T_1506) @[Cat.scala 30:58] + node _T_1517 = bits(_T_1493, 0, 0) @[Replacement.scala 50:20] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_1521 = dshl(UInt<1>("h01"), _T_1516) @[Replacement.scala 51:37] + node _T_1522 = or(_T_1515, _T_1521) @[Replacement.scala 51:37] + node _T_1523 = not(_T_1515) @[Replacement.scala 51:37] + node _T_1524 = or(_T_1523, _T_1521) @[Replacement.scala 51:37] + node _T_1525 = not(_T_1524) @[Replacement.scala 51:37] + node _T_1526 = mux(_T_1519, _T_1522, _T_1525) @[Replacement.scala 51:37] + node _T_1527 = cat(_T_1516, _T_1517) @[Cat.scala 30:58] + _T_1398 <= _T_1526 @[Replacement.scala 44:15] + skip @[TLB.scala 143:59] + node _T_1528 = bits(hits, 8, 0) @[TLB.scala 152:42] + node _T_1529 = bits(_T_1528, 3, 0) @[Package.scala 62:39] + node _T_1530 = bits(_T_1529, 1, 0) @[Package.scala 62:39] + node _T_1531 = bits(_T_1530, 0, 0) @[Package.scala 62:39] + node _T_1532 = bits(_T_1531, 0, 0) @[Package.scala 59:20] + node _T_1534 = bits(_T_1530, 1, 1) @[Package.scala 63:41] + node _T_1535 = bits(_T_1534, 0, 0) @[Package.scala 59:20] + node _T_1537 = or(_T_1532, _T_1535) @[Package.scala 64:18] + node _T_1538 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1539 = and(_T_1532, _T_1535) @[Package.scala 64:63] + node _T_1540 = or(_T_1538, _T_1539) @[Package.scala 64:51] + node _T_1541 = bits(_T_1529, 3, 2) @[Package.scala 63:41] + node _T_1542 = bits(_T_1541, 0, 0) @[Package.scala 62:39] + node _T_1543 = bits(_T_1542, 0, 0) @[Package.scala 59:20] + node _T_1545 = bits(_T_1541, 1, 1) @[Package.scala 63:41] + node _T_1546 = bits(_T_1545, 0, 0) @[Package.scala 59:20] + node _T_1548 = or(_T_1543, _T_1546) @[Package.scala 64:18] + node _T_1549 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1550 = and(_T_1543, _T_1546) @[Package.scala 64:63] + node _T_1551 = or(_T_1549, _T_1550) @[Package.scala 64:51] + node _T_1552 = or(_T_1537, _T_1548) @[Package.scala 64:18] + node _T_1553 = or(_T_1540, _T_1551) @[Package.scala 64:39] + node _T_1554 = and(_T_1537, _T_1548) @[Package.scala 64:63] + node _T_1555 = or(_T_1553, _T_1554) @[Package.scala 64:51] + node _T_1556 = bits(_T_1528, 8, 4) @[Package.scala 63:41] + node _T_1557 = bits(_T_1556, 1, 0) @[Package.scala 62:39] + node _T_1558 = bits(_T_1557, 0, 0) @[Package.scala 62:39] + node _T_1559 = bits(_T_1558, 0, 0) @[Package.scala 59:20] + node _T_1561 = bits(_T_1557, 1, 1) @[Package.scala 63:41] + node _T_1562 = bits(_T_1561, 0, 0) @[Package.scala 59:20] + node _T_1564 = or(_T_1559, _T_1562) @[Package.scala 64:18] + node _T_1565 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1566 = and(_T_1559, _T_1562) @[Package.scala 64:63] + node _T_1567 = or(_T_1565, _T_1566) @[Package.scala 64:51] + node _T_1568 = bits(_T_1556, 4, 2) @[Package.scala 63:41] + node _T_1569 = bits(_T_1568, 0, 0) @[Package.scala 62:39] + node _T_1570 = bits(_T_1569, 0, 0) @[Package.scala 59:20] + node _T_1572 = bits(_T_1568, 2, 1) @[Package.scala 63:41] + node _T_1573 = bits(_T_1572, 0, 0) @[Package.scala 62:39] + node _T_1574 = bits(_T_1573, 0, 0) @[Package.scala 59:20] + node _T_1576 = bits(_T_1572, 1, 1) @[Package.scala 63:41] + node _T_1577 = bits(_T_1576, 0, 0) @[Package.scala 59:20] + node _T_1579 = or(_T_1574, _T_1577) @[Package.scala 64:18] + node _T_1580 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1581 = and(_T_1574, _T_1577) @[Package.scala 64:63] + node _T_1582 = or(_T_1580, _T_1581) @[Package.scala 64:51] + node _T_1583 = or(_T_1570, _T_1579) @[Package.scala 64:18] + node _T_1584 = or(UInt<1>("h00"), _T_1582) @[Package.scala 64:39] + node _T_1585 = and(_T_1570, _T_1579) @[Package.scala 64:63] + node _T_1586 = or(_T_1584, _T_1585) @[Package.scala 64:51] + node _T_1587 = or(_T_1564, _T_1583) @[Package.scala 64:18] + node _T_1588 = or(_T_1567, _T_1586) @[Package.scala 64:39] + node _T_1589 = and(_T_1564, _T_1583) @[Package.scala 64:63] + node _T_1590 = or(_T_1588, _T_1589) @[Package.scala 64:51] + node _T_1591 = or(_T_1552, _T_1587) @[Package.scala 64:18] + node _T_1592 = or(_T_1555, _T_1590) @[Package.scala 64:39] + node _T_1593 = and(_T_1552, _T_1587) @[Package.scala 64:63] + node multipleHits = or(_T_1592, _T_1593) @[Package.scala 64:51] + node _T_1594 = eq(state, UInt<2>("h00")) @[TLB.scala 154:25] + io.req.ready <= _T_1594 @[TLB.scala 154:16] + node _T_1595 = not(r_array) @[TLB.scala 155:33] + node _T_1596 = and(_T_1595, hits) @[TLB.scala 155:42] + node _T_1598 = neq(_T_1596, UInt<1>("h00")) @[TLB.scala 155:50] + node _T_1599 = or(bad_va, _T_1598) @[TLB.scala 155:29] + io.resp.xcpt_ld <= _T_1599 @[TLB.scala 155:19] + node _T_1600 = not(w_array) @[TLB.scala 156:33] + node _T_1601 = and(_T_1600, hits) @[TLB.scala 156:42] + node _T_1603 = neq(_T_1601, UInt<1>("h00")) @[TLB.scala 156:50] + node _T_1604 = or(bad_va, _T_1603) @[TLB.scala 156:29] + io.resp.xcpt_st <= _T_1604 @[TLB.scala 156:19] + node _T_1605 = not(x_array) @[TLB.scala 157:33] + node _T_1606 = and(_T_1605, hits) @[TLB.scala 157:42] + node _T_1608 = neq(_T_1606, UInt<1>("h00")) @[TLB.scala 157:50] + node _T_1609 = or(bad_va, _T_1608) @[TLB.scala 157:29] + io.resp.xcpt_if <= _T_1609 @[TLB.scala 157:19] + node _T_1610 = and(c_array, hits) @[TLB.scala 158:33] + node _T_1612 = neq(_T_1610, UInt<1>("h00")) @[TLB.scala 158:41] + io.resp.cacheable <= _T_1612 @[TLB.scala 158:21] + node _T_1613 = or(do_refill, tlb_miss) @[TLB.scala 159:29] + node _T_1614 = or(_T_1613, multipleHits) @[TLB.scala 159:41] + io.resp.miss <= _T_1614 @[TLB.scala 159:16] + node _T_1615 = cat(ppn, pgOffset) @[Cat.scala 30:58] + io.resp.paddr <= _T_1615 @[TLB.scala 160:17] + node _T_1616 = eq(state, UInt<2>("h01")) @[TLB.scala 162:29] + io.ptw.req.valid <= _T_1616 @[TLB.scala 162:20] + io.ptw.req.bits <- io.ptw.status @[TLB.scala 163:19] + io.ptw.req.bits.addr <= r_refill_tag @[TLB.scala 164:24] + io.ptw.req.bits.store <= r_req.store @[TLB.scala 165:25] + io.ptw.req.bits.fetch <= r_req.instruction @[TLB.scala 166:25] + node _T_1617 = and(io.req.ready, io.req.valid) @[Decoupled.scala 30:37] + node _T_1618 = and(_T_1617, tlb_miss) @[TLB.scala 169:25] + when _T_1618 : @[TLB.scala 169:38] + state <= UInt<2>("h01") @[TLB.scala 170:13] + r_refill_tag <= lookup_tag @[TLB.scala 171:20] + r_refill_waddr <= repl_waddr @[TLB.scala 172:22] + r_req <- io.req.bits @[TLB.scala 173:13] + skip @[TLB.scala 169:38] + node _T_1619 = eq(state, UInt<2>("h01")) @[TLB.scala 175:17] + when _T_1619 : @[TLB.scala 175:32] + when io.ptw.invalidate : @[TLB.scala 176:32] + state <= UInt<2>("h00") @[TLB.scala 177:15] + skip @[TLB.scala 176:32] + when io.ptw.req.ready : @[TLB.scala 179:31] + state <= UInt<2>("h02") @[TLB.scala 180:15] + when io.ptw.invalidate : @[TLB.scala 181:34] + state <= UInt<2>("h03") @[TLB.scala 181:42] + skip @[TLB.scala 181:34] + skip @[TLB.scala 179:31] + skip @[TLB.scala 175:32] + node _T_1620 = eq(state, UInt<2>("h02")) @[TLB.scala 184:17] + node _T_1621 = and(_T_1620, io.ptw.invalidate) @[TLB.scala 184:28] + when _T_1621 : @[TLB.scala 184:50] + state <= UInt<2>("h03") @[TLB.scala 185:13] + skip @[TLB.scala 184:50] + when io.ptw.resp.valid : @[TLB.scala 187:30] + state <= UInt<2>("h00") @[TLB.scala 188:13] + skip @[TLB.scala 187:30] + node _T_1622 = or(io.ptw.invalidate, multipleHits) @[TLB.scala 191:29] + when _T_1622 : @[TLB.scala 191:46] + valid <= UInt<1>("h00") @[TLB.scala 192:13] + skip @[TLB.scala 191:46] + + module BTB : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}} + + io is invalid + io is invalid + reg idxs : UInt<13>[40], clock @[BTB.scala 149:17] + reg idxPages : UInt<3>[40], clock @[BTB.scala 150:21] + reg tgts : UInt<13>[40], clock @[BTB.scala 151:17] + reg tgtPages : UInt<3>[40], clock @[BTB.scala 152:21] + reg pages : UInt<25>[6], clock @[BTB.scala 153:18] + reg pageValid : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[BTB.scala 154:22] + reg isValid : UInt<40>, clock with : (reset => (reset, UInt<40>("h00"))) @[BTB.scala 156:20] + reg isReturn : UInt<40>, clock @[BTB.scala 157:21] + reg isJump : UInt<40>, clock @[BTB.scala 158:19] + reg brIdx : UInt<1>[40], clock @[BTB.scala 159:18] + reg _T_837 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_837 <= io.btb_update.valid @[Valid.scala 47:18] + reg _T_876 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clock @[Reg.scala 34:16] + when io.btb_update.valid : @[Reg.scala 35:19] + _T_876 <- io.btb_update.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} @[Valid.scala 42:21] + r_btb_update is invalid @[Valid.scala 42:21] + r_btb_update.valid <= _T_837 @[Valid.scala 43:17] + r_btb_update.bits <- _T_876 @[Valid.scala 44:16] + node _T_1069 = shr(io.req.bits.addr, 14) @[BTB.scala 161:39] + node _T_1070 = eq(pages[0], _T_1069) @[BTB.scala 164:29] + node _T_1071 = eq(pages[1], _T_1069) @[BTB.scala 164:29] + node _T_1072 = eq(pages[2], _T_1069) @[BTB.scala 164:29] + node _T_1073 = eq(pages[3], _T_1069) @[BTB.scala 164:29] + node _T_1074 = eq(pages[4], _T_1069) @[BTB.scala 164:29] + node _T_1075 = eq(pages[5], _T_1069) @[BTB.scala 164:29] + node _T_1076 = cat(_T_1072, _T_1071) @[Cat.scala 30:58] + node _T_1077 = cat(_T_1076, _T_1070) @[Cat.scala 30:58] + node _T_1078 = cat(_T_1075, _T_1074) @[Cat.scala 30:58] + node _T_1079 = cat(_T_1078, _T_1073) @[Cat.scala 30:58] + node _T_1080 = cat(_T_1079, _T_1077) @[Cat.scala 30:58] + node pageHit = and(pageValid, _T_1080) @[BTB.scala 164:15] + node _T_1081 = bits(io.req.bits.addr, 13, 1) @[BTB.scala 167:19] + node _T_1082 = eq(idxs[0], _T_1081) @[BTB.scala 168:16] + node _T_1083 = eq(idxs[1], _T_1081) @[BTB.scala 168:16] + node _T_1084 = eq(idxs[2], _T_1081) @[BTB.scala 168:16] + node _T_1085 = eq(idxs[3], _T_1081) @[BTB.scala 168:16] + node _T_1086 = eq(idxs[4], _T_1081) @[BTB.scala 168:16] + node _T_1087 = eq(idxs[5], _T_1081) @[BTB.scala 168:16] + node _T_1088 = eq(idxs[6], _T_1081) @[BTB.scala 168:16] + node _T_1089 = eq(idxs[7], _T_1081) @[BTB.scala 168:16] + node _T_1090 = eq(idxs[8], _T_1081) @[BTB.scala 168:16] + node _T_1091 = eq(idxs[9], _T_1081) @[BTB.scala 168:16] + node _T_1092 = eq(idxs[10], _T_1081) @[BTB.scala 168:16] + node _T_1093 = eq(idxs[11], _T_1081) @[BTB.scala 168:16] + node _T_1094 = eq(idxs[12], _T_1081) @[BTB.scala 168:16] + node _T_1095 = eq(idxs[13], _T_1081) @[BTB.scala 168:16] + node _T_1096 = eq(idxs[14], _T_1081) @[BTB.scala 168:16] + node _T_1097 = eq(idxs[15], _T_1081) @[BTB.scala 168:16] + node _T_1098 = eq(idxs[16], _T_1081) @[BTB.scala 168:16] + node _T_1099 = eq(idxs[17], _T_1081) @[BTB.scala 168:16] + node _T_1100 = eq(idxs[18], _T_1081) @[BTB.scala 168:16] + node _T_1101 = eq(idxs[19], _T_1081) @[BTB.scala 168:16] + node _T_1102 = eq(idxs[20], _T_1081) @[BTB.scala 168:16] + node _T_1103 = eq(idxs[21], _T_1081) @[BTB.scala 168:16] + node _T_1104 = eq(idxs[22], _T_1081) @[BTB.scala 168:16] + node _T_1105 = eq(idxs[23], _T_1081) @[BTB.scala 168:16] + node _T_1106 = eq(idxs[24], _T_1081) @[BTB.scala 168:16] + node _T_1107 = eq(idxs[25], _T_1081) @[BTB.scala 168:16] + node _T_1108 = eq(idxs[26], _T_1081) @[BTB.scala 168:16] + node _T_1109 = eq(idxs[27], _T_1081) @[BTB.scala 168:16] + node _T_1110 = eq(idxs[28], _T_1081) @[BTB.scala 168:16] + node _T_1111 = eq(idxs[29], _T_1081) @[BTB.scala 168:16] + node _T_1112 = eq(idxs[30], _T_1081) @[BTB.scala 168:16] + node _T_1113 = eq(idxs[31], _T_1081) @[BTB.scala 168:16] + node _T_1114 = eq(idxs[32], _T_1081) @[BTB.scala 168:16] + node _T_1115 = eq(idxs[33], _T_1081) @[BTB.scala 168:16] + node _T_1116 = eq(idxs[34], _T_1081) @[BTB.scala 168:16] + node _T_1117 = eq(idxs[35], _T_1081) @[BTB.scala 168:16] + node _T_1118 = eq(idxs[36], _T_1081) @[BTB.scala 168:16] + node _T_1119 = eq(idxs[37], _T_1081) @[BTB.scala 168:16] + node _T_1120 = eq(idxs[38], _T_1081) @[BTB.scala 168:16] + node _T_1121 = eq(idxs[39], _T_1081) @[BTB.scala 168:16] + node _T_1122 = cat(_T_1083, _T_1082) @[Cat.scala 30:58] + node _T_1123 = cat(_T_1086, _T_1085) @[Cat.scala 30:58] + node _T_1124 = cat(_T_1123, _T_1084) @[Cat.scala 30:58] + node _T_1125 = cat(_T_1124, _T_1122) @[Cat.scala 30:58] + node _T_1126 = cat(_T_1088, _T_1087) @[Cat.scala 30:58] + node _T_1127 = cat(_T_1091, _T_1090) @[Cat.scala 30:58] + node _T_1128 = cat(_T_1127, _T_1089) @[Cat.scala 30:58] + node _T_1129 = cat(_T_1128, _T_1126) @[Cat.scala 30:58] + node _T_1130 = cat(_T_1129, _T_1125) @[Cat.scala 30:58] + node _T_1131 = cat(_T_1093, _T_1092) @[Cat.scala 30:58] + node _T_1132 = cat(_T_1096, _T_1095) @[Cat.scala 30:58] + node _T_1133 = cat(_T_1132, _T_1094) @[Cat.scala 30:58] + node _T_1134 = cat(_T_1133, _T_1131) @[Cat.scala 30:58] + node _T_1135 = cat(_T_1098, _T_1097) @[Cat.scala 30:58] + node _T_1136 = cat(_T_1101, _T_1100) @[Cat.scala 30:58] + node _T_1137 = cat(_T_1136, _T_1099) @[Cat.scala 30:58] + node _T_1138 = cat(_T_1137, _T_1135) @[Cat.scala 30:58] + node _T_1139 = cat(_T_1138, _T_1134) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1139, _T_1130) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1103, _T_1102) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1106, _T_1105) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1142, _T_1104) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1141) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1108, _T_1107) @[Cat.scala 30:58] + node _T_1146 = cat(_T_1111, _T_1110) @[Cat.scala 30:58] + node _T_1147 = cat(_T_1146, _T_1109) @[Cat.scala 30:58] + node _T_1148 = cat(_T_1147, _T_1145) @[Cat.scala 30:58] + node _T_1149 = cat(_T_1148, _T_1144) @[Cat.scala 30:58] + node _T_1150 = cat(_T_1113, _T_1112) @[Cat.scala 30:58] + node _T_1151 = cat(_T_1116, _T_1115) @[Cat.scala 30:58] + node _T_1152 = cat(_T_1151, _T_1114) @[Cat.scala 30:58] + node _T_1153 = cat(_T_1152, _T_1150) @[Cat.scala 30:58] + node _T_1154 = cat(_T_1118, _T_1117) @[Cat.scala 30:58] + node _T_1155 = cat(_T_1121, _T_1120) @[Cat.scala 30:58] + node _T_1156 = cat(_T_1155, _T_1119) @[Cat.scala 30:58] + node _T_1157 = cat(_T_1156, _T_1154) @[Cat.scala 30:58] + node _T_1158 = cat(_T_1157, _T_1153) @[Cat.scala 30:58] + node _T_1159 = cat(_T_1158, _T_1149) @[Cat.scala 30:58] + node _T_1160 = cat(_T_1159, _T_1140) @[Cat.scala 30:58] + node idxHit = and(_T_1160, isValid) @[BTB.scala 168:32] + node _T_1161 = shr(r_btb_update.bits.pc, 14) @[BTB.scala 161:39] + node _T_1162 = eq(pages[0], _T_1161) @[BTB.scala 164:29] + node _T_1163 = eq(pages[1], _T_1161) @[BTB.scala 164:29] + node _T_1164 = eq(pages[2], _T_1161) @[BTB.scala 164:29] + node _T_1165 = eq(pages[3], _T_1161) @[BTB.scala 164:29] + node _T_1166 = eq(pages[4], _T_1161) @[BTB.scala 164:29] + node _T_1167 = eq(pages[5], _T_1161) @[BTB.scala 164:29] + node _T_1168 = cat(_T_1164, _T_1163) @[Cat.scala 30:58] + node _T_1169 = cat(_T_1168, _T_1162) @[Cat.scala 30:58] + node _T_1170 = cat(_T_1167, _T_1166) @[Cat.scala 30:58] + node _T_1171 = cat(_T_1170, _T_1165) @[Cat.scala 30:58] + node _T_1172 = cat(_T_1171, _T_1169) @[Cat.scala 30:58] + node updatePageHit = and(pageValid, _T_1172) @[BTB.scala 164:15] + node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) @[BTB.scala 184:40] + node usePageHit = neq(pageHit, UInt<1>("h00")) @[BTB.scala 185:28] + node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) @[BTB.scala 186:23] + reg nextPageRepl : UInt<3>, clock @[BTB.scala 187:25] + node _T_1177 = bits(pageHit, 4, 0) @[BTB.scala 188:32] + node _T_1178 = bits(pageHit, 5, 5) @[BTB.scala 188:53] + node _T_1179 = cat(_T_1177, _T_1178) @[Cat.scala 30:58] + node _T_1182 = dshl(UInt<1>("h01"), nextPageRepl) @[OneHot.scala 47:11] + node _T_1183 = mux(usePageHit, UInt<1>("h00"), _T_1182) @[BTB.scala 188:70] + node idxPageRepl = or(_T_1179, _T_1183) @[BTB.scala 188:65] + node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) @[BTB.scala 189:28] + node _T_1184 = bits(idxPageUpdateOH, 7, 4) @[OneHot.scala 26:18] + node _T_1185 = bits(idxPageUpdateOH, 3, 0) @[OneHot.scala 27:18] + node _T_1187 = neq(_T_1184, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1188 = or(_T_1184, _T_1185) @[OneHot.scala 28:28] + node _T_1189 = bits(_T_1188, 3, 2) @[OneHot.scala 26:18] + node _T_1190 = bits(_T_1188, 1, 0) @[OneHot.scala 27:18] + node _T_1192 = neq(_T_1189, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1193 = or(_T_1189, _T_1190) @[OneHot.scala 28:28] + node _T_1194 = bits(_T_1193, 1, 1) @[CircuitMath.scala 30:8] + node _T_1195 = cat(_T_1192, _T_1194) @[Cat.scala 30:58] + node idxPageUpdate = cat(_T_1187, _T_1195) @[Cat.scala 30:58] + node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) @[BTB.scala 191:26] + node _T_1197 = shr(r_btb_update.bits.pc, 14) @[BTB.scala 161:39] + node _T_1198 = shr(io.req.bits.addr, 14) @[BTB.scala 161:39] + node samePage = eq(_T_1197, _T_1198) @[BTB.scala 193:45] + node _T_1200 = eq(samePage, UInt<1>("h00")) @[BTB.scala 194:23] + node _T_1202 = eq(usePageHit, UInt<1>("h00")) @[BTB.scala 194:36] + node doTgtPageRepl = and(_T_1200, _T_1202) @[BTB.scala 194:33] + node _T_1203 = bits(idxPageUpdateOH, 4, 0) @[BTB.scala 195:71] + node _T_1204 = bits(idxPageUpdateOH, 5, 5) @[BTB.scala 195:100] + node _T_1205 = cat(_T_1203, _T_1204) @[Cat.scala 30:58] + node tgtPageRepl = mux(samePage, idxPageUpdateOH, _T_1205) @[BTB.scala 195:24] + node _T_1207 = mux(usePageHit, UInt<1>("h00"), tgtPageRepl) @[BTB.scala 196:45] + node _T_1208 = or(pageHit, _T_1207) @[BTB.scala 196:40] + node _T_1209 = bits(_T_1208, 7, 4) @[OneHot.scala 26:18] + node _T_1210 = bits(_T_1208, 3, 0) @[OneHot.scala 27:18] + node _T_1212 = neq(_T_1209, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1213 = or(_T_1209, _T_1210) @[OneHot.scala 28:28] + node _T_1214 = bits(_T_1213, 3, 2) @[OneHot.scala 26:18] + node _T_1215 = bits(_T_1213, 1, 0) @[OneHot.scala 27:18] + node _T_1217 = neq(_T_1214, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1218 = or(_T_1214, _T_1215) @[OneHot.scala 28:28] + node _T_1219 = bits(_T_1218, 1, 1) @[CircuitMath.scala 30:8] + node _T_1220 = cat(_T_1217, _T_1219) @[Cat.scala 30:58] + node tgtPageUpdate = cat(_T_1212, _T_1220) @[Cat.scala 30:58] + node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) @[BTB.scala 197:26] + node _T_1222 = or(doIdxPageRepl, doTgtPageRepl) @[BTB.scala 199:46] + node _T_1223 = and(r_btb_update.valid, _T_1222) @[BTB.scala 199:28] + when _T_1223 : @[BTB.scala 199:65] + node _T_1224 = and(doIdxPageRepl, doTgtPageRepl) @[BTB.scala 200:30] + node _T_1227 = mux(_T_1224, UInt<2>("h02"), UInt<1>("h01")) @[BTB.scala 201:40] + node _T_1228 = add(nextPageRepl, _T_1227) @[BTB.scala 201:29] + node _T_1229 = tail(_T_1228, 1) @[BTB.scala 201:29] + node _T_1231 = geq(_T_1229, UInt<3>("h06")) @[BTB.scala 202:30] + node _T_1232 = bits(_T_1229, 0, 0) @[BTB.scala 202:45] + node _T_1233 = mux(_T_1231, _T_1232, _T_1229) @[BTB.scala 202:24] + nextPageRepl <= _T_1233 @[BTB.scala 202:18] + skip @[BTB.scala 199:65] + when r_btb_update.valid : @[BTB.scala 205:29] + node _T_1235 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) @[BTB.scala 206:50] + node _T_1236 = and(r_btb_update.valid, _T_1235) @[BTB.scala 206:47] + reg value : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counter.scala 17:29] + when _T_1236 : @[Counter.scala 62:17] + node _T_1239 = eq(value, UInt<6>("h027")) @[Counter.scala 25:24] + node _T_1241 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_1242 = tail(_T_1241, 1) @[Counter.scala 26:22] + value <= _T_1242 @[Counter.scala 26:13] + when _T_1239 : @[Counter.scala 28:21] + value <= UInt<1>("h00") @[Counter.scala 28:29] + skip @[Counter.scala 28:21] + skip @[Counter.scala 62:17] + node _T_1244 = and(_T_1236, _T_1239) @[Counter.scala 63:20] + node _T_1245 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, value) @[BTB.scala 207:20] + node _T_1247 = dshl(UInt<1>("h01"), _T_1245) @[OneHot.scala 47:11] + node _T_1249 = bits(r_btb_update.bits.pc, 13, 1) @[BTB.scala 209:40] + idxs[_T_1245] <= _T_1249 @[BTB.scala 209:17] + node _T_1251 = bits(io.req.bits.addr, 13, 1) @[BTB.scala 210:33] + tgts[_T_1245] <= _T_1251 @[BTB.scala 210:17] + node _T_1254 = add(idxPageUpdate, UInt<1>("h01")) @[BTB.scala 211:38] + idxPages[_T_1245] <= _T_1254 @[BTB.scala 211:21] + tgtPages[_T_1245] <= tgtPageUpdate @[BTB.scala 212:21] + node _T_1256 = or(isValid, _T_1247) @[BTB.scala 213:55] + node _T_1257 = not(_T_1247) @[BTB.scala 213:73] + node _T_1258 = and(isValid, _T_1257) @[BTB.scala 213:71] + node _T_1259 = mux(r_btb_update.bits.isValid, _T_1256, _T_1258) @[BTB.scala 213:19] + isValid <= _T_1259 @[BTB.scala 213:13] + node _T_1260 = or(isReturn, _T_1247) @[BTB.scala 214:58] + node _T_1261 = not(_T_1247) @[BTB.scala 214:77] + node _T_1262 = and(isReturn, _T_1261) @[BTB.scala 214:75] + node _T_1263 = mux(r_btb_update.bits.isReturn, _T_1260, _T_1262) @[BTB.scala 214:20] + isReturn <= _T_1263 @[BTB.scala 214:14] + node _T_1264 = or(isJump, _T_1247) @[BTB.scala 215:52] + node _T_1265 = not(_T_1247) @[BTB.scala 215:69] + node _T_1266 = and(isJump, _T_1265) @[BTB.scala 215:67] + node _T_1267 = mux(r_btb_update.bits.isJump, _T_1264, _T_1266) @[BTB.scala 215:18] + isJump <= _T_1267 @[BTB.scala 215:12] + node _T_1269 = shr(r_btb_update.bits.br_pc, 1) @[BTB.scala 217:47] + brIdx[_T_1245] <= _T_1269 @[BTB.scala 217:20] + node _T_1270 = bits(idxPageUpdate, 0, 0) @[BTB.scala 220:39] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[BTB.scala 220:25] + node _T_1273 = mux(_T_1272, idxPageReplEn, tgtPageReplEn) @[BTB.scala 226:24] + node _T_1274 = shr(r_btb_update.bits.pc, 14) @[BTB.scala 161:39] + node _T_1275 = shr(io.req.bits.addr, 14) @[BTB.scala 161:39] + node _T_1276 = mux(_T_1272, _T_1274, _T_1275) @[BTB.scala 227:10] + node _T_1277 = bits(_T_1273, 0, 0) @[BTB.scala 224:17] + when _T_1277 : @[BTB.scala 224:22] + pages[0] <= _T_1276 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1278 = bits(_T_1273, 2, 2) @[BTB.scala 224:17] + when _T_1278 : @[BTB.scala 224:22] + pages[2] <= _T_1276 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1279 = bits(_T_1273, 4, 4) @[BTB.scala 224:17] + when _T_1279 : @[BTB.scala 224:22] + pages[4] <= _T_1276 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1280 = mux(_T_1272, tgtPageReplEn, idxPageReplEn) @[BTB.scala 228:24] + node _T_1281 = shr(io.req.bits.addr, 14) @[BTB.scala 161:39] + node _T_1282 = shr(r_btb_update.bits.pc, 14) @[BTB.scala 161:39] + node _T_1283 = mux(_T_1272, _T_1281, _T_1282) @[BTB.scala 229:10] + node _T_1284 = bits(_T_1280, 1, 1) @[BTB.scala 224:17] + when _T_1284 : @[BTB.scala 224:22] + pages[1] <= _T_1283 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1285 = bits(_T_1280, 3, 3) @[BTB.scala 224:17] + when _T_1285 : @[BTB.scala 224:22] + pages[3] <= _T_1283 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1286 = bits(_T_1280, 5, 5) @[BTB.scala 224:17] + when _T_1286 : @[BTB.scala 224:22] + pages[5] <= _T_1283 @[BTB.scala 224:33] + skip @[BTB.scala 224:22] + node _T_1287 = or(pageValid, tgtPageReplEn) @[BTB.scala 230:28] + node _T_1288 = or(_T_1287, idxPageReplEn) @[BTB.scala 230:44] + pageValid <= _T_1288 @[BTB.scala 230:15] + skip @[BTB.scala 205:29] + node _T_1289 = shl(pageHit, 1) @[BTB.scala 233:29] + node _T_1290 = bits(idxHit, 0, 0) @[Mux.scala 21:36] + node _T_1291 = bits(idxHit, 1, 1) @[Mux.scala 21:36] + node _T_1292 = bits(idxHit, 2, 2) @[Mux.scala 21:36] + node _T_1293 = bits(idxHit, 3, 3) @[Mux.scala 21:36] + node _T_1294 = bits(idxHit, 4, 4) @[Mux.scala 21:36] + node _T_1295 = bits(idxHit, 5, 5) @[Mux.scala 21:36] + node _T_1296 = bits(idxHit, 6, 6) @[Mux.scala 21:36] + node _T_1297 = bits(idxHit, 7, 7) @[Mux.scala 21:36] + node _T_1298 = bits(idxHit, 8, 8) @[Mux.scala 21:36] + node _T_1299 = bits(idxHit, 9, 9) @[Mux.scala 21:36] + node _T_1300 = bits(idxHit, 10, 10) @[Mux.scala 21:36] + node _T_1301 = bits(idxHit, 11, 11) @[Mux.scala 21:36] + node _T_1302 = bits(idxHit, 12, 12) @[Mux.scala 21:36] + node _T_1303 = bits(idxHit, 13, 13) @[Mux.scala 21:36] + node _T_1304 = bits(idxHit, 14, 14) @[Mux.scala 21:36] + node _T_1305 = bits(idxHit, 15, 15) @[Mux.scala 21:36] + node _T_1306 = bits(idxHit, 16, 16) @[Mux.scala 21:36] + node _T_1307 = bits(idxHit, 17, 17) @[Mux.scala 21:36] + node _T_1308 = bits(idxHit, 18, 18) @[Mux.scala 21:36] + node _T_1309 = bits(idxHit, 19, 19) @[Mux.scala 21:36] + node _T_1310 = bits(idxHit, 20, 20) @[Mux.scala 21:36] + node _T_1311 = bits(idxHit, 21, 21) @[Mux.scala 21:36] + node _T_1312 = bits(idxHit, 22, 22) @[Mux.scala 21:36] + node _T_1313 = bits(idxHit, 23, 23) @[Mux.scala 21:36] + node _T_1314 = bits(idxHit, 24, 24) @[Mux.scala 21:36] + node _T_1315 = bits(idxHit, 25, 25) @[Mux.scala 21:36] + node _T_1316 = bits(idxHit, 26, 26) @[Mux.scala 21:36] + node _T_1317 = bits(idxHit, 27, 27) @[Mux.scala 21:36] + node _T_1318 = bits(idxHit, 28, 28) @[Mux.scala 21:36] + node _T_1319 = bits(idxHit, 29, 29) @[Mux.scala 21:36] + node _T_1320 = bits(idxHit, 30, 30) @[Mux.scala 21:36] + node _T_1321 = bits(idxHit, 31, 31) @[Mux.scala 21:36] + node _T_1322 = bits(idxHit, 32, 32) @[Mux.scala 21:36] + node _T_1323 = bits(idxHit, 33, 33) @[Mux.scala 21:36] + node _T_1324 = bits(idxHit, 34, 34) @[Mux.scala 21:36] + node _T_1325 = bits(idxHit, 35, 35) @[Mux.scala 21:36] + node _T_1326 = bits(idxHit, 36, 36) @[Mux.scala 21:36] + node _T_1327 = bits(idxHit, 37, 37) @[Mux.scala 21:36] + node _T_1328 = bits(idxHit, 38, 38) @[Mux.scala 21:36] + node _T_1329 = bits(idxHit, 39, 39) @[Mux.scala 21:36] + node _T_1331 = mux(_T_1290, idxPages[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1333 = mux(_T_1291, idxPages[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1335 = mux(_T_1292, idxPages[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1337 = mux(_T_1293, idxPages[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1339 = mux(_T_1294, idxPages[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1341 = mux(_T_1295, idxPages[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1343 = mux(_T_1296, idxPages[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1345 = mux(_T_1297, idxPages[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1347 = mux(_T_1298, idxPages[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1349 = mux(_T_1299, idxPages[9], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1351 = mux(_T_1300, idxPages[10], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1353 = mux(_T_1301, idxPages[11], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1355 = mux(_T_1302, idxPages[12], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1357 = mux(_T_1303, idxPages[13], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1359 = mux(_T_1304, idxPages[14], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1361 = mux(_T_1305, idxPages[15], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1363 = mux(_T_1306, idxPages[16], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1365 = mux(_T_1307, idxPages[17], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1367 = mux(_T_1308, idxPages[18], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1369 = mux(_T_1309, idxPages[19], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1371 = mux(_T_1310, idxPages[20], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1373 = mux(_T_1311, idxPages[21], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1375 = mux(_T_1312, idxPages[22], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1377 = mux(_T_1313, idxPages[23], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1379 = mux(_T_1314, idxPages[24], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1381 = mux(_T_1315, idxPages[25], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1383 = mux(_T_1316, idxPages[26], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1385 = mux(_T_1317, idxPages[27], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1387 = mux(_T_1318, idxPages[28], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1389 = mux(_T_1319, idxPages[29], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1391 = mux(_T_1320, idxPages[30], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1393 = mux(_T_1321, idxPages[31], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1395 = mux(_T_1322, idxPages[32], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1397 = mux(_T_1323, idxPages[33], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1399 = mux(_T_1324, idxPages[34], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1401 = mux(_T_1325, idxPages[35], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1403 = mux(_T_1326, idxPages[36], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1405 = mux(_T_1327, idxPages[37], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1407 = mux(_T_1328, idxPages[38], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1409 = mux(_T_1329, idxPages[39], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1411 = or(_T_1331, _T_1333) @[Mux.scala 19:72] + node _T_1412 = or(_T_1411, _T_1335) @[Mux.scala 19:72] + node _T_1413 = or(_T_1412, _T_1337) @[Mux.scala 19:72] + node _T_1414 = or(_T_1413, _T_1339) @[Mux.scala 19:72] + node _T_1415 = or(_T_1414, _T_1341) @[Mux.scala 19:72] + node _T_1416 = or(_T_1415, _T_1343) @[Mux.scala 19:72] + node _T_1417 = or(_T_1416, _T_1345) @[Mux.scala 19:72] + node _T_1418 = or(_T_1417, _T_1347) @[Mux.scala 19:72] + node _T_1419 = or(_T_1418, _T_1349) @[Mux.scala 19:72] + node _T_1420 = or(_T_1419, _T_1351) @[Mux.scala 19:72] + node _T_1421 = or(_T_1420, _T_1353) @[Mux.scala 19:72] + node _T_1422 = or(_T_1421, _T_1355) @[Mux.scala 19:72] + node _T_1423 = or(_T_1422, _T_1357) @[Mux.scala 19:72] + node _T_1424 = or(_T_1423, _T_1359) @[Mux.scala 19:72] + node _T_1425 = or(_T_1424, _T_1361) @[Mux.scala 19:72] + node _T_1426 = or(_T_1425, _T_1363) @[Mux.scala 19:72] + node _T_1427 = or(_T_1426, _T_1365) @[Mux.scala 19:72] + node _T_1428 = or(_T_1427, _T_1367) @[Mux.scala 19:72] + node _T_1429 = or(_T_1428, _T_1369) @[Mux.scala 19:72] + node _T_1430 = or(_T_1429, _T_1371) @[Mux.scala 19:72] + node _T_1431 = or(_T_1430, _T_1373) @[Mux.scala 19:72] + node _T_1432 = or(_T_1431, _T_1375) @[Mux.scala 19:72] + node _T_1433 = or(_T_1432, _T_1377) @[Mux.scala 19:72] + node _T_1434 = or(_T_1433, _T_1379) @[Mux.scala 19:72] + node _T_1435 = or(_T_1434, _T_1381) @[Mux.scala 19:72] + node _T_1436 = or(_T_1435, _T_1383) @[Mux.scala 19:72] + node _T_1437 = or(_T_1436, _T_1385) @[Mux.scala 19:72] + node _T_1438 = or(_T_1437, _T_1387) @[Mux.scala 19:72] + node _T_1439 = or(_T_1438, _T_1389) @[Mux.scala 19:72] + node _T_1440 = or(_T_1439, _T_1391) @[Mux.scala 19:72] + node _T_1441 = or(_T_1440, _T_1393) @[Mux.scala 19:72] + node _T_1442 = or(_T_1441, _T_1395) @[Mux.scala 19:72] + node _T_1443 = or(_T_1442, _T_1397) @[Mux.scala 19:72] + node _T_1444 = or(_T_1443, _T_1399) @[Mux.scala 19:72] + node _T_1445 = or(_T_1444, _T_1401) @[Mux.scala 19:72] + node _T_1446 = or(_T_1445, _T_1403) @[Mux.scala 19:72] + node _T_1447 = or(_T_1446, _T_1405) @[Mux.scala 19:72] + node _T_1448 = or(_T_1447, _T_1407) @[Mux.scala 19:72] + node _T_1449 = or(_T_1448, _T_1409) @[Mux.scala 19:72] + wire _T_1451 : UInt<3> @[Mux.scala 19:72] + _T_1451 is invalid @[Mux.scala 19:72] + _T_1451 <= _T_1449 @[Mux.scala 19:72] + node _T_1452 = dshr(_T_1289, _T_1451) @[BTB.scala 233:34] + node _T_1453 = bits(_T_1452, 0, 0) @[BTB.scala 233:34] + io.resp.valid <= _T_1453 @[BTB.scala 233:17] + io.resp.bits.taken <= UInt<1>("h01") @[BTB.scala 234:22] + node _T_1455 = bits(idxHit, 0, 0) @[Mux.scala 21:36] + node _T_1456 = bits(idxHit, 1, 1) @[Mux.scala 21:36] + node _T_1457 = bits(idxHit, 2, 2) @[Mux.scala 21:36] + node _T_1458 = bits(idxHit, 3, 3) @[Mux.scala 21:36] + node _T_1459 = bits(idxHit, 4, 4) @[Mux.scala 21:36] + node _T_1460 = bits(idxHit, 5, 5) @[Mux.scala 21:36] + node _T_1461 = bits(idxHit, 6, 6) @[Mux.scala 21:36] + node _T_1462 = bits(idxHit, 7, 7) @[Mux.scala 21:36] + node _T_1463 = bits(idxHit, 8, 8) @[Mux.scala 21:36] + node _T_1464 = bits(idxHit, 9, 9) @[Mux.scala 21:36] + node _T_1465 = bits(idxHit, 10, 10) @[Mux.scala 21:36] + node _T_1466 = bits(idxHit, 11, 11) @[Mux.scala 21:36] + node _T_1467 = bits(idxHit, 12, 12) @[Mux.scala 21:36] + node _T_1468 = bits(idxHit, 13, 13) @[Mux.scala 21:36] + node _T_1469 = bits(idxHit, 14, 14) @[Mux.scala 21:36] + node _T_1470 = bits(idxHit, 15, 15) @[Mux.scala 21:36] + node _T_1471 = bits(idxHit, 16, 16) @[Mux.scala 21:36] + node _T_1472 = bits(idxHit, 17, 17) @[Mux.scala 21:36] + node _T_1473 = bits(idxHit, 18, 18) @[Mux.scala 21:36] + node _T_1474 = bits(idxHit, 19, 19) @[Mux.scala 21:36] + node _T_1475 = bits(idxHit, 20, 20) @[Mux.scala 21:36] + node _T_1476 = bits(idxHit, 21, 21) @[Mux.scala 21:36] + node _T_1477 = bits(idxHit, 22, 22) @[Mux.scala 21:36] + node _T_1478 = bits(idxHit, 23, 23) @[Mux.scala 21:36] + node _T_1479 = bits(idxHit, 24, 24) @[Mux.scala 21:36] + node _T_1480 = bits(idxHit, 25, 25) @[Mux.scala 21:36] + node _T_1481 = bits(idxHit, 26, 26) @[Mux.scala 21:36] + node _T_1482 = bits(idxHit, 27, 27) @[Mux.scala 21:36] + node _T_1483 = bits(idxHit, 28, 28) @[Mux.scala 21:36] + node _T_1484 = bits(idxHit, 29, 29) @[Mux.scala 21:36] + node _T_1485 = bits(idxHit, 30, 30) @[Mux.scala 21:36] + node _T_1486 = bits(idxHit, 31, 31) @[Mux.scala 21:36] + node _T_1487 = bits(idxHit, 32, 32) @[Mux.scala 21:36] + node _T_1488 = bits(idxHit, 33, 33) @[Mux.scala 21:36] + node _T_1489 = bits(idxHit, 34, 34) @[Mux.scala 21:36] + node _T_1490 = bits(idxHit, 35, 35) @[Mux.scala 21:36] + node _T_1491 = bits(idxHit, 36, 36) @[Mux.scala 21:36] + node _T_1492 = bits(idxHit, 37, 37) @[Mux.scala 21:36] + node _T_1493 = bits(idxHit, 38, 38) @[Mux.scala 21:36] + node _T_1494 = bits(idxHit, 39, 39) @[Mux.scala 21:36] + node _T_1496 = mux(_T_1455, tgtPages[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1498 = mux(_T_1456, tgtPages[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1500 = mux(_T_1457, tgtPages[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1502 = mux(_T_1458, tgtPages[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1504 = mux(_T_1459, tgtPages[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1506 = mux(_T_1460, tgtPages[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1508 = mux(_T_1461, tgtPages[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1510 = mux(_T_1462, tgtPages[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1512 = mux(_T_1463, tgtPages[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1514 = mux(_T_1464, tgtPages[9], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1516 = mux(_T_1465, tgtPages[10], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1518 = mux(_T_1466, tgtPages[11], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1520 = mux(_T_1467, tgtPages[12], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1522 = mux(_T_1468, tgtPages[13], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1524 = mux(_T_1469, tgtPages[14], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1526 = mux(_T_1470, tgtPages[15], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1528 = mux(_T_1471, tgtPages[16], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1530 = mux(_T_1472, tgtPages[17], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1532 = mux(_T_1473, tgtPages[18], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1534 = mux(_T_1474, tgtPages[19], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1536 = mux(_T_1475, tgtPages[20], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1538 = mux(_T_1476, tgtPages[21], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1540 = mux(_T_1477, tgtPages[22], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1542 = mux(_T_1478, tgtPages[23], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1544 = mux(_T_1479, tgtPages[24], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1546 = mux(_T_1480, tgtPages[25], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1548 = mux(_T_1481, tgtPages[26], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1550 = mux(_T_1482, tgtPages[27], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1552 = mux(_T_1483, tgtPages[28], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1554 = mux(_T_1484, tgtPages[29], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1556 = mux(_T_1485, tgtPages[30], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1558 = mux(_T_1486, tgtPages[31], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1560 = mux(_T_1487, tgtPages[32], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1562 = mux(_T_1488, tgtPages[33], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1564 = mux(_T_1489, tgtPages[34], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1566 = mux(_T_1490, tgtPages[35], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1568 = mux(_T_1491, tgtPages[36], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1570 = mux(_T_1492, tgtPages[37], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1572 = mux(_T_1493, tgtPages[38], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1574 = mux(_T_1494, tgtPages[39], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1576 = or(_T_1496, _T_1498) @[Mux.scala 19:72] + node _T_1577 = or(_T_1576, _T_1500) @[Mux.scala 19:72] + node _T_1578 = or(_T_1577, _T_1502) @[Mux.scala 19:72] + node _T_1579 = or(_T_1578, _T_1504) @[Mux.scala 19:72] + node _T_1580 = or(_T_1579, _T_1506) @[Mux.scala 19:72] + node _T_1581 = or(_T_1580, _T_1508) @[Mux.scala 19:72] + node _T_1582 = or(_T_1581, _T_1510) @[Mux.scala 19:72] + node _T_1583 = or(_T_1582, _T_1512) @[Mux.scala 19:72] + node _T_1584 = or(_T_1583, _T_1514) @[Mux.scala 19:72] + node _T_1585 = or(_T_1584, _T_1516) @[Mux.scala 19:72] + node _T_1586 = or(_T_1585, _T_1518) @[Mux.scala 19:72] + node _T_1587 = or(_T_1586, _T_1520) @[Mux.scala 19:72] + node _T_1588 = or(_T_1587, _T_1522) @[Mux.scala 19:72] + node _T_1589 = or(_T_1588, _T_1524) @[Mux.scala 19:72] + node _T_1590 = or(_T_1589, _T_1526) @[Mux.scala 19:72] + node _T_1591 = or(_T_1590, _T_1528) @[Mux.scala 19:72] + node _T_1592 = or(_T_1591, _T_1530) @[Mux.scala 19:72] + node _T_1593 = or(_T_1592, _T_1532) @[Mux.scala 19:72] + node _T_1594 = or(_T_1593, _T_1534) @[Mux.scala 19:72] + node _T_1595 = or(_T_1594, _T_1536) @[Mux.scala 19:72] + node _T_1596 = or(_T_1595, _T_1538) @[Mux.scala 19:72] + node _T_1597 = or(_T_1596, _T_1540) @[Mux.scala 19:72] + node _T_1598 = or(_T_1597, _T_1542) @[Mux.scala 19:72] + node _T_1599 = or(_T_1598, _T_1544) @[Mux.scala 19:72] + node _T_1600 = or(_T_1599, _T_1546) @[Mux.scala 19:72] + node _T_1601 = or(_T_1600, _T_1548) @[Mux.scala 19:72] + node _T_1602 = or(_T_1601, _T_1550) @[Mux.scala 19:72] + node _T_1603 = or(_T_1602, _T_1552) @[Mux.scala 19:72] + node _T_1604 = or(_T_1603, _T_1554) @[Mux.scala 19:72] + node _T_1605 = or(_T_1604, _T_1556) @[Mux.scala 19:72] + node _T_1606 = or(_T_1605, _T_1558) @[Mux.scala 19:72] + node _T_1607 = or(_T_1606, _T_1560) @[Mux.scala 19:72] + node _T_1608 = or(_T_1607, _T_1562) @[Mux.scala 19:72] + node _T_1609 = or(_T_1608, _T_1564) @[Mux.scala 19:72] + node _T_1610 = or(_T_1609, _T_1566) @[Mux.scala 19:72] + node _T_1611 = or(_T_1610, _T_1568) @[Mux.scala 19:72] + node _T_1612 = or(_T_1611, _T_1570) @[Mux.scala 19:72] + node _T_1613 = or(_T_1612, _T_1572) @[Mux.scala 19:72] + node _T_1614 = or(_T_1613, _T_1574) @[Mux.scala 19:72] + wire _T_1616 : UInt<3> @[Mux.scala 19:72] + _T_1616 is invalid @[Mux.scala 19:72] + _T_1616 <= _T_1614 @[Mux.scala 19:72] + node _T_1618 = bits(idxHit, 0, 0) @[Mux.scala 21:36] + node _T_1619 = bits(idxHit, 1, 1) @[Mux.scala 21:36] + node _T_1620 = bits(idxHit, 2, 2) @[Mux.scala 21:36] + node _T_1621 = bits(idxHit, 3, 3) @[Mux.scala 21:36] + node _T_1622 = bits(idxHit, 4, 4) @[Mux.scala 21:36] + node _T_1623 = bits(idxHit, 5, 5) @[Mux.scala 21:36] + node _T_1624 = bits(idxHit, 6, 6) @[Mux.scala 21:36] + node _T_1625 = bits(idxHit, 7, 7) @[Mux.scala 21:36] + node _T_1626 = bits(idxHit, 8, 8) @[Mux.scala 21:36] + node _T_1627 = bits(idxHit, 9, 9) @[Mux.scala 21:36] + node _T_1628 = bits(idxHit, 10, 10) @[Mux.scala 21:36] + node _T_1629 = bits(idxHit, 11, 11) @[Mux.scala 21:36] + node _T_1630 = bits(idxHit, 12, 12) @[Mux.scala 21:36] + node _T_1631 = bits(idxHit, 13, 13) @[Mux.scala 21:36] + node _T_1632 = bits(idxHit, 14, 14) @[Mux.scala 21:36] + node _T_1633 = bits(idxHit, 15, 15) @[Mux.scala 21:36] + node _T_1634 = bits(idxHit, 16, 16) @[Mux.scala 21:36] + node _T_1635 = bits(idxHit, 17, 17) @[Mux.scala 21:36] + node _T_1636 = bits(idxHit, 18, 18) @[Mux.scala 21:36] + node _T_1637 = bits(idxHit, 19, 19) @[Mux.scala 21:36] + node _T_1638 = bits(idxHit, 20, 20) @[Mux.scala 21:36] + node _T_1639 = bits(idxHit, 21, 21) @[Mux.scala 21:36] + node _T_1640 = bits(idxHit, 22, 22) @[Mux.scala 21:36] + node _T_1641 = bits(idxHit, 23, 23) @[Mux.scala 21:36] + node _T_1642 = bits(idxHit, 24, 24) @[Mux.scala 21:36] + node _T_1643 = bits(idxHit, 25, 25) @[Mux.scala 21:36] + node _T_1644 = bits(idxHit, 26, 26) @[Mux.scala 21:36] + node _T_1645 = bits(idxHit, 27, 27) @[Mux.scala 21:36] + node _T_1646 = bits(idxHit, 28, 28) @[Mux.scala 21:36] + node _T_1647 = bits(idxHit, 29, 29) @[Mux.scala 21:36] + node _T_1648 = bits(idxHit, 30, 30) @[Mux.scala 21:36] + node _T_1649 = bits(idxHit, 31, 31) @[Mux.scala 21:36] + node _T_1650 = bits(idxHit, 32, 32) @[Mux.scala 21:36] + node _T_1651 = bits(idxHit, 33, 33) @[Mux.scala 21:36] + node _T_1652 = bits(idxHit, 34, 34) @[Mux.scala 21:36] + node _T_1653 = bits(idxHit, 35, 35) @[Mux.scala 21:36] + node _T_1654 = bits(idxHit, 36, 36) @[Mux.scala 21:36] + node _T_1655 = bits(idxHit, 37, 37) @[Mux.scala 21:36] + node _T_1656 = bits(idxHit, 38, 38) @[Mux.scala 21:36] + node _T_1657 = bits(idxHit, 39, 39) @[Mux.scala 21:36] + node _T_1659 = mux(_T_1618, tgts[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1661 = mux(_T_1619, tgts[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1663 = mux(_T_1620, tgts[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1665 = mux(_T_1621, tgts[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1667 = mux(_T_1622, tgts[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1669 = mux(_T_1623, tgts[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1671 = mux(_T_1624, tgts[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1673 = mux(_T_1625, tgts[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1675 = mux(_T_1626, tgts[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1677 = mux(_T_1627, tgts[9], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1679 = mux(_T_1628, tgts[10], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1681 = mux(_T_1629, tgts[11], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1683 = mux(_T_1630, tgts[12], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1685 = mux(_T_1631, tgts[13], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1687 = mux(_T_1632, tgts[14], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1689 = mux(_T_1633, tgts[15], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1691 = mux(_T_1634, tgts[16], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1693 = mux(_T_1635, tgts[17], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1695 = mux(_T_1636, tgts[18], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1697 = mux(_T_1637, tgts[19], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1699 = mux(_T_1638, tgts[20], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1701 = mux(_T_1639, tgts[21], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1703 = mux(_T_1640, tgts[22], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1705 = mux(_T_1641, tgts[23], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1707 = mux(_T_1642, tgts[24], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1709 = mux(_T_1643, tgts[25], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1711 = mux(_T_1644, tgts[26], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1713 = mux(_T_1645, tgts[27], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1715 = mux(_T_1646, tgts[28], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1717 = mux(_T_1647, tgts[29], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1719 = mux(_T_1648, tgts[30], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1721 = mux(_T_1649, tgts[31], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1723 = mux(_T_1650, tgts[32], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1725 = mux(_T_1651, tgts[33], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1727 = mux(_T_1652, tgts[34], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1729 = mux(_T_1653, tgts[35], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1731 = mux(_T_1654, tgts[36], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1733 = mux(_T_1655, tgts[37], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1735 = mux(_T_1656, tgts[38], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1737 = mux(_T_1657, tgts[39], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1739 = or(_T_1659, _T_1661) @[Mux.scala 19:72] + node _T_1740 = or(_T_1739, _T_1663) @[Mux.scala 19:72] + node _T_1741 = or(_T_1740, _T_1665) @[Mux.scala 19:72] + node _T_1742 = or(_T_1741, _T_1667) @[Mux.scala 19:72] + node _T_1743 = or(_T_1742, _T_1669) @[Mux.scala 19:72] + node _T_1744 = or(_T_1743, _T_1671) @[Mux.scala 19:72] + node _T_1745 = or(_T_1744, _T_1673) @[Mux.scala 19:72] + node _T_1746 = or(_T_1745, _T_1675) @[Mux.scala 19:72] + node _T_1747 = or(_T_1746, _T_1677) @[Mux.scala 19:72] + node _T_1748 = or(_T_1747, _T_1679) @[Mux.scala 19:72] + node _T_1749 = or(_T_1748, _T_1681) @[Mux.scala 19:72] + node _T_1750 = or(_T_1749, _T_1683) @[Mux.scala 19:72] + node _T_1751 = or(_T_1750, _T_1685) @[Mux.scala 19:72] + node _T_1752 = or(_T_1751, _T_1687) @[Mux.scala 19:72] + node _T_1753 = or(_T_1752, _T_1689) @[Mux.scala 19:72] + node _T_1754 = or(_T_1753, _T_1691) @[Mux.scala 19:72] + node _T_1755 = or(_T_1754, _T_1693) @[Mux.scala 19:72] + node _T_1756 = or(_T_1755, _T_1695) @[Mux.scala 19:72] + node _T_1757 = or(_T_1756, _T_1697) @[Mux.scala 19:72] + node _T_1758 = or(_T_1757, _T_1699) @[Mux.scala 19:72] + node _T_1759 = or(_T_1758, _T_1701) @[Mux.scala 19:72] + node _T_1760 = or(_T_1759, _T_1703) @[Mux.scala 19:72] + node _T_1761 = or(_T_1760, _T_1705) @[Mux.scala 19:72] + node _T_1762 = or(_T_1761, _T_1707) @[Mux.scala 19:72] + node _T_1763 = or(_T_1762, _T_1709) @[Mux.scala 19:72] + node _T_1764 = or(_T_1763, _T_1711) @[Mux.scala 19:72] + node _T_1765 = or(_T_1764, _T_1713) @[Mux.scala 19:72] + node _T_1766 = or(_T_1765, _T_1715) @[Mux.scala 19:72] + node _T_1767 = or(_T_1766, _T_1717) @[Mux.scala 19:72] + node _T_1768 = or(_T_1767, _T_1719) @[Mux.scala 19:72] + node _T_1769 = or(_T_1768, _T_1721) @[Mux.scala 19:72] + node _T_1770 = or(_T_1769, _T_1723) @[Mux.scala 19:72] + node _T_1771 = or(_T_1770, _T_1725) @[Mux.scala 19:72] + node _T_1772 = or(_T_1771, _T_1727) @[Mux.scala 19:72] + node _T_1773 = or(_T_1772, _T_1729) @[Mux.scala 19:72] + node _T_1774 = or(_T_1773, _T_1731) @[Mux.scala 19:72] + node _T_1775 = or(_T_1774, _T_1733) @[Mux.scala 19:72] + node _T_1776 = or(_T_1775, _T_1735) @[Mux.scala 19:72] + node _T_1777 = or(_T_1776, _T_1737) @[Mux.scala 19:72] + wire _T_1779 : UInt<13> @[Mux.scala 19:72] + _T_1779 is invalid @[Mux.scala 19:72] + _T_1779 <= _T_1777 @[Mux.scala 19:72] + node _T_1780 = shl(_T_1779, 1) @[BTB.scala 235:82] + node _T_1781 = cat(pages[_T_1616], _T_1780) @[Cat.scala 30:58] + io.resp.bits.target <= _T_1781 @[BTB.scala 235:23] + node _T_1782 = bits(idxHit, 39, 32) @[OneHot.scala 26:18] + node _T_1783 = bits(idxHit, 31, 0) @[OneHot.scala 27:18] + node _T_1785 = neq(_T_1782, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1786 = or(_T_1782, _T_1783) @[OneHot.scala 28:28] + node _T_1787 = bits(_T_1786, 31, 16) @[OneHot.scala 26:18] + node _T_1788 = bits(_T_1786, 15, 0) @[OneHot.scala 27:18] + node _T_1790 = neq(_T_1787, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1791 = or(_T_1787, _T_1788) @[OneHot.scala 28:28] + node _T_1792 = bits(_T_1791, 15, 8) @[OneHot.scala 26:18] + node _T_1793 = bits(_T_1791, 7, 0) @[OneHot.scala 27:18] + node _T_1795 = neq(_T_1792, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1796 = or(_T_1792, _T_1793) @[OneHot.scala 28:28] + node _T_1797 = bits(_T_1796, 7, 4) @[OneHot.scala 26:18] + node _T_1798 = bits(_T_1796, 3, 0) @[OneHot.scala 27:18] + node _T_1800 = neq(_T_1797, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1801 = or(_T_1797, _T_1798) @[OneHot.scala 28:28] + node _T_1802 = bits(_T_1801, 3, 2) @[OneHot.scala 26:18] + node _T_1803 = bits(_T_1801, 1, 0) @[OneHot.scala 27:18] + node _T_1805 = neq(_T_1802, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_1806 = or(_T_1802, _T_1803) @[OneHot.scala 28:28] + node _T_1807 = bits(_T_1806, 1, 1) @[CircuitMath.scala 30:8] + node _T_1808 = cat(_T_1805, _T_1807) @[Cat.scala 30:58] + node _T_1809 = cat(_T_1800, _T_1808) @[Cat.scala 30:58] + node _T_1810 = cat(_T_1795, _T_1809) @[Cat.scala 30:58] + node _T_1811 = cat(_T_1790, _T_1810) @[Cat.scala 30:58] + node _T_1812 = cat(_T_1785, _T_1811) @[Cat.scala 30:58] + io.resp.bits.entry <= _T_1812 @[BTB.scala 236:22] + node _T_1813 = bits(idxHit, 0, 0) @[Mux.scala 21:36] + node _T_1814 = bits(idxHit, 1, 1) @[Mux.scala 21:36] + node _T_1815 = bits(idxHit, 2, 2) @[Mux.scala 21:36] + node _T_1816 = bits(idxHit, 3, 3) @[Mux.scala 21:36] + node _T_1817 = bits(idxHit, 4, 4) @[Mux.scala 21:36] + node _T_1818 = bits(idxHit, 5, 5) @[Mux.scala 21:36] + node _T_1819 = bits(idxHit, 6, 6) @[Mux.scala 21:36] + node _T_1820 = bits(idxHit, 7, 7) @[Mux.scala 21:36] + node _T_1821 = bits(idxHit, 8, 8) @[Mux.scala 21:36] + node _T_1822 = bits(idxHit, 9, 9) @[Mux.scala 21:36] + node _T_1823 = bits(idxHit, 10, 10) @[Mux.scala 21:36] + node _T_1824 = bits(idxHit, 11, 11) @[Mux.scala 21:36] + node _T_1825 = bits(idxHit, 12, 12) @[Mux.scala 21:36] + node _T_1826 = bits(idxHit, 13, 13) @[Mux.scala 21:36] + node _T_1827 = bits(idxHit, 14, 14) @[Mux.scala 21:36] + node _T_1828 = bits(idxHit, 15, 15) @[Mux.scala 21:36] + node _T_1829 = bits(idxHit, 16, 16) @[Mux.scala 21:36] + node _T_1830 = bits(idxHit, 17, 17) @[Mux.scala 21:36] + node _T_1831 = bits(idxHit, 18, 18) @[Mux.scala 21:36] + node _T_1832 = bits(idxHit, 19, 19) @[Mux.scala 21:36] + node _T_1833 = bits(idxHit, 20, 20) @[Mux.scala 21:36] + node _T_1834 = bits(idxHit, 21, 21) @[Mux.scala 21:36] + node _T_1835 = bits(idxHit, 22, 22) @[Mux.scala 21:36] + node _T_1836 = bits(idxHit, 23, 23) @[Mux.scala 21:36] + node _T_1837 = bits(idxHit, 24, 24) @[Mux.scala 21:36] + node _T_1838 = bits(idxHit, 25, 25) @[Mux.scala 21:36] + node _T_1839 = bits(idxHit, 26, 26) @[Mux.scala 21:36] + node _T_1840 = bits(idxHit, 27, 27) @[Mux.scala 21:36] + node _T_1841 = bits(idxHit, 28, 28) @[Mux.scala 21:36] + node _T_1842 = bits(idxHit, 29, 29) @[Mux.scala 21:36] + node _T_1843 = bits(idxHit, 30, 30) @[Mux.scala 21:36] + node _T_1844 = bits(idxHit, 31, 31) @[Mux.scala 21:36] + node _T_1845 = bits(idxHit, 32, 32) @[Mux.scala 21:36] + node _T_1846 = bits(idxHit, 33, 33) @[Mux.scala 21:36] + node _T_1847 = bits(idxHit, 34, 34) @[Mux.scala 21:36] + node _T_1848 = bits(idxHit, 35, 35) @[Mux.scala 21:36] + node _T_1849 = bits(idxHit, 36, 36) @[Mux.scala 21:36] + node _T_1850 = bits(idxHit, 37, 37) @[Mux.scala 21:36] + node _T_1851 = bits(idxHit, 38, 38) @[Mux.scala 21:36] + node _T_1852 = bits(idxHit, 39, 39) @[Mux.scala 21:36] + node _T_1854 = mux(_T_1813, brIdx[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1856 = mux(_T_1814, brIdx[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1858 = mux(_T_1815, brIdx[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1860 = mux(_T_1816, brIdx[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1862 = mux(_T_1817, brIdx[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1864 = mux(_T_1818, brIdx[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1866 = mux(_T_1819, brIdx[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1868 = mux(_T_1820, brIdx[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1870 = mux(_T_1821, brIdx[8], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1872 = mux(_T_1822, brIdx[9], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1874 = mux(_T_1823, brIdx[10], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1876 = mux(_T_1824, brIdx[11], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1878 = mux(_T_1825, brIdx[12], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1880 = mux(_T_1826, brIdx[13], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1882 = mux(_T_1827, brIdx[14], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1884 = mux(_T_1828, brIdx[15], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1886 = mux(_T_1829, brIdx[16], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1888 = mux(_T_1830, brIdx[17], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1890 = mux(_T_1831, brIdx[18], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1892 = mux(_T_1832, brIdx[19], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1894 = mux(_T_1833, brIdx[20], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1896 = mux(_T_1834, brIdx[21], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1898 = mux(_T_1835, brIdx[22], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1900 = mux(_T_1836, brIdx[23], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1902 = mux(_T_1837, brIdx[24], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1904 = mux(_T_1838, brIdx[25], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1906 = mux(_T_1839, brIdx[26], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1908 = mux(_T_1840, brIdx[27], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1910 = mux(_T_1841, brIdx[28], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1912 = mux(_T_1842, brIdx[29], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1914 = mux(_T_1843, brIdx[30], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1916 = mux(_T_1844, brIdx[31], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1918 = mux(_T_1845, brIdx[32], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1920 = mux(_T_1846, brIdx[33], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1922 = mux(_T_1847, brIdx[34], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1924 = mux(_T_1848, brIdx[35], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1926 = mux(_T_1849, brIdx[36], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1928 = mux(_T_1850, brIdx[37], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1930 = mux(_T_1851, brIdx[38], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1932 = mux(_T_1852, brIdx[39], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1934 = or(_T_1854, _T_1856) @[Mux.scala 19:72] + node _T_1935 = or(_T_1934, _T_1858) @[Mux.scala 19:72] + node _T_1936 = or(_T_1935, _T_1860) @[Mux.scala 19:72] + node _T_1937 = or(_T_1936, _T_1862) @[Mux.scala 19:72] + node _T_1938 = or(_T_1937, _T_1864) @[Mux.scala 19:72] + node _T_1939 = or(_T_1938, _T_1866) @[Mux.scala 19:72] + node _T_1940 = or(_T_1939, _T_1868) @[Mux.scala 19:72] + node _T_1941 = or(_T_1940, _T_1870) @[Mux.scala 19:72] + node _T_1942 = or(_T_1941, _T_1872) @[Mux.scala 19:72] + node _T_1943 = or(_T_1942, _T_1874) @[Mux.scala 19:72] + node _T_1944 = or(_T_1943, _T_1876) @[Mux.scala 19:72] + node _T_1945 = or(_T_1944, _T_1878) @[Mux.scala 19:72] + node _T_1946 = or(_T_1945, _T_1880) @[Mux.scala 19:72] + node _T_1947 = or(_T_1946, _T_1882) @[Mux.scala 19:72] + node _T_1948 = or(_T_1947, _T_1884) @[Mux.scala 19:72] + node _T_1949 = or(_T_1948, _T_1886) @[Mux.scala 19:72] + node _T_1950 = or(_T_1949, _T_1888) @[Mux.scala 19:72] + node _T_1951 = or(_T_1950, _T_1890) @[Mux.scala 19:72] + node _T_1952 = or(_T_1951, _T_1892) @[Mux.scala 19:72] + node _T_1953 = or(_T_1952, _T_1894) @[Mux.scala 19:72] + node _T_1954 = or(_T_1953, _T_1896) @[Mux.scala 19:72] + node _T_1955 = or(_T_1954, _T_1898) @[Mux.scala 19:72] + node _T_1956 = or(_T_1955, _T_1900) @[Mux.scala 19:72] + node _T_1957 = or(_T_1956, _T_1902) @[Mux.scala 19:72] + node _T_1958 = or(_T_1957, _T_1904) @[Mux.scala 19:72] + node _T_1959 = or(_T_1958, _T_1906) @[Mux.scala 19:72] + node _T_1960 = or(_T_1959, _T_1908) @[Mux.scala 19:72] + node _T_1961 = or(_T_1960, _T_1910) @[Mux.scala 19:72] + node _T_1962 = or(_T_1961, _T_1912) @[Mux.scala 19:72] + node _T_1963 = or(_T_1962, _T_1914) @[Mux.scala 19:72] + node _T_1964 = or(_T_1963, _T_1916) @[Mux.scala 19:72] + node _T_1965 = or(_T_1964, _T_1918) @[Mux.scala 19:72] + node _T_1966 = or(_T_1965, _T_1920) @[Mux.scala 19:72] + node _T_1967 = or(_T_1966, _T_1922) @[Mux.scala 19:72] + node _T_1968 = or(_T_1967, _T_1924) @[Mux.scala 19:72] + node _T_1969 = or(_T_1968, _T_1926) @[Mux.scala 19:72] + node _T_1970 = or(_T_1969, _T_1928) @[Mux.scala 19:72] + node _T_1971 = or(_T_1970, _T_1930) @[Mux.scala 19:72] + node _T_1972 = or(_T_1971, _T_1932) @[Mux.scala 19:72] + wire _T_1974 : UInt<1> @[Mux.scala 19:72] + _T_1974 is invalid @[Mux.scala 19:72] + _T_1974 <= _T_1972 @[Mux.scala 19:72] + io.resp.bits.bridx <= _T_1974 @[BTB.scala 237:22] + node _T_1976 = not(io.resp.bits.bridx) @[BTB.scala 238:65] + node _T_1978 = mux(io.resp.bits.taken, _T_1976, UInt<1>("h00")) @[BTB.scala 238:44] + node _T_1979 = not(_T_1978) @[BTB.scala 238:40] + node _T_1980 = dshl(UInt<1>("h01"), _T_1979) @[BTB.scala 238:37] + node _T_1982 = sub(_T_1980, UInt<1>("h01")) @[BTB.scala 238:95] + node _T_1983 = asUInt(_T_1982) @[BTB.scala 238:95] + node _T_1984 = tail(_T_1983, 1) @[BTB.scala 238:95] + node _T_1986 = cat(_T_1984, UInt<1>("h01")) @[Cat.scala 30:58] + io.resp.bits.mask <= _T_1986 @[BTB.scala 238:21] + node _T_1987 = bits(idxHit, 19, 0) @[Package.scala 62:39] + node _T_1988 = bits(_T_1987, 9, 0) @[Package.scala 62:39] + node _T_1989 = bits(_T_1988, 4, 0) @[Package.scala 62:39] + node _T_1990 = bits(_T_1989, 1, 0) @[Package.scala 62:39] + node _T_1991 = bits(_T_1990, 0, 0) @[Package.scala 62:39] + node _T_1992 = bits(_T_1991, 0, 0) @[Package.scala 59:20] + node _T_1994 = bits(_T_1990, 1, 1) @[Package.scala 63:41] + node _T_1995 = bits(_T_1994, 0, 0) @[Package.scala 59:20] + node _T_1997 = or(_T_1992, _T_1995) @[Package.scala 64:18] + node _T_1998 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_1999 = and(_T_1992, _T_1995) @[Package.scala 64:63] + node _T_2000 = or(_T_1998, _T_1999) @[Package.scala 64:51] + node _T_2001 = bits(_T_1989, 4, 2) @[Package.scala 63:41] + node _T_2002 = bits(_T_2001, 0, 0) @[Package.scala 62:39] + node _T_2003 = bits(_T_2002, 0, 0) @[Package.scala 59:20] + node _T_2005 = bits(_T_2001, 2, 1) @[Package.scala 63:41] + node _T_2006 = bits(_T_2005, 0, 0) @[Package.scala 62:39] + node _T_2007 = bits(_T_2006, 0, 0) @[Package.scala 59:20] + node _T_2009 = bits(_T_2005, 1, 1) @[Package.scala 63:41] + node _T_2010 = bits(_T_2009, 0, 0) @[Package.scala 59:20] + node _T_2012 = or(_T_2007, _T_2010) @[Package.scala 64:18] + node _T_2013 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2014 = and(_T_2007, _T_2010) @[Package.scala 64:63] + node _T_2015 = or(_T_2013, _T_2014) @[Package.scala 64:51] + node _T_2016 = or(_T_2003, _T_2012) @[Package.scala 64:18] + node _T_2017 = or(UInt<1>("h00"), _T_2015) @[Package.scala 64:39] + node _T_2018 = and(_T_2003, _T_2012) @[Package.scala 64:63] + node _T_2019 = or(_T_2017, _T_2018) @[Package.scala 64:51] + node _T_2020 = or(_T_1997, _T_2016) @[Package.scala 64:18] + node _T_2021 = or(_T_2000, _T_2019) @[Package.scala 64:39] + node _T_2022 = and(_T_1997, _T_2016) @[Package.scala 64:63] + node _T_2023 = or(_T_2021, _T_2022) @[Package.scala 64:51] + node _T_2024 = bits(_T_1988, 9, 5) @[Package.scala 63:41] + node _T_2025 = bits(_T_2024, 1, 0) @[Package.scala 62:39] + node _T_2026 = bits(_T_2025, 0, 0) @[Package.scala 62:39] + node _T_2027 = bits(_T_2026, 0, 0) @[Package.scala 59:20] + node _T_2029 = bits(_T_2025, 1, 1) @[Package.scala 63:41] + node _T_2030 = bits(_T_2029, 0, 0) @[Package.scala 59:20] + node _T_2032 = or(_T_2027, _T_2030) @[Package.scala 64:18] + node _T_2033 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2034 = and(_T_2027, _T_2030) @[Package.scala 64:63] + node _T_2035 = or(_T_2033, _T_2034) @[Package.scala 64:51] + node _T_2036 = bits(_T_2024, 4, 2) @[Package.scala 63:41] + node _T_2037 = bits(_T_2036, 0, 0) @[Package.scala 62:39] + node _T_2038 = bits(_T_2037, 0, 0) @[Package.scala 59:20] + node _T_2040 = bits(_T_2036, 2, 1) @[Package.scala 63:41] + node _T_2041 = bits(_T_2040, 0, 0) @[Package.scala 62:39] + node _T_2042 = bits(_T_2041, 0, 0) @[Package.scala 59:20] + node _T_2044 = bits(_T_2040, 1, 1) @[Package.scala 63:41] + node _T_2045 = bits(_T_2044, 0, 0) @[Package.scala 59:20] + node _T_2047 = or(_T_2042, _T_2045) @[Package.scala 64:18] + node _T_2048 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2049 = and(_T_2042, _T_2045) @[Package.scala 64:63] + node _T_2050 = or(_T_2048, _T_2049) @[Package.scala 64:51] + node _T_2051 = or(_T_2038, _T_2047) @[Package.scala 64:18] + node _T_2052 = or(UInt<1>("h00"), _T_2050) @[Package.scala 64:39] + node _T_2053 = and(_T_2038, _T_2047) @[Package.scala 64:63] + node _T_2054 = or(_T_2052, _T_2053) @[Package.scala 64:51] + node _T_2055 = or(_T_2032, _T_2051) @[Package.scala 64:18] + node _T_2056 = or(_T_2035, _T_2054) @[Package.scala 64:39] + node _T_2057 = and(_T_2032, _T_2051) @[Package.scala 64:63] + node _T_2058 = or(_T_2056, _T_2057) @[Package.scala 64:51] + node _T_2059 = or(_T_2020, _T_2055) @[Package.scala 64:18] + node _T_2060 = or(_T_2023, _T_2058) @[Package.scala 64:39] + node _T_2061 = and(_T_2020, _T_2055) @[Package.scala 64:63] + node _T_2062 = or(_T_2060, _T_2061) @[Package.scala 64:51] + node _T_2063 = bits(_T_1987, 19, 10) @[Package.scala 63:41] + node _T_2064 = bits(_T_2063, 4, 0) @[Package.scala 62:39] + node _T_2065 = bits(_T_2064, 1, 0) @[Package.scala 62:39] + node _T_2066 = bits(_T_2065, 0, 0) @[Package.scala 62:39] + node _T_2067 = bits(_T_2066, 0, 0) @[Package.scala 59:20] + node _T_2069 = bits(_T_2065, 1, 1) @[Package.scala 63:41] + node _T_2070 = bits(_T_2069, 0, 0) @[Package.scala 59:20] + node _T_2072 = or(_T_2067, _T_2070) @[Package.scala 64:18] + node _T_2073 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2074 = and(_T_2067, _T_2070) @[Package.scala 64:63] + node _T_2075 = or(_T_2073, _T_2074) @[Package.scala 64:51] + node _T_2076 = bits(_T_2064, 4, 2) @[Package.scala 63:41] + node _T_2077 = bits(_T_2076, 0, 0) @[Package.scala 62:39] + node _T_2078 = bits(_T_2077, 0, 0) @[Package.scala 59:20] + node _T_2080 = bits(_T_2076, 2, 1) @[Package.scala 63:41] + node _T_2081 = bits(_T_2080, 0, 0) @[Package.scala 62:39] + node _T_2082 = bits(_T_2081, 0, 0) @[Package.scala 59:20] + node _T_2084 = bits(_T_2080, 1, 1) @[Package.scala 63:41] + node _T_2085 = bits(_T_2084, 0, 0) @[Package.scala 59:20] + node _T_2087 = or(_T_2082, _T_2085) @[Package.scala 64:18] + node _T_2088 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2089 = and(_T_2082, _T_2085) @[Package.scala 64:63] + node _T_2090 = or(_T_2088, _T_2089) @[Package.scala 64:51] + node _T_2091 = or(_T_2078, _T_2087) @[Package.scala 64:18] + node _T_2092 = or(UInt<1>("h00"), _T_2090) @[Package.scala 64:39] + node _T_2093 = and(_T_2078, _T_2087) @[Package.scala 64:63] + node _T_2094 = or(_T_2092, _T_2093) @[Package.scala 64:51] + node _T_2095 = or(_T_2072, _T_2091) @[Package.scala 64:18] + node _T_2096 = or(_T_2075, _T_2094) @[Package.scala 64:39] + node _T_2097 = and(_T_2072, _T_2091) @[Package.scala 64:63] + node _T_2098 = or(_T_2096, _T_2097) @[Package.scala 64:51] + node _T_2099 = bits(_T_2063, 9, 5) @[Package.scala 63:41] + node _T_2100 = bits(_T_2099, 1, 0) @[Package.scala 62:39] + node _T_2101 = bits(_T_2100, 0, 0) @[Package.scala 62:39] + node _T_2102 = bits(_T_2101, 0, 0) @[Package.scala 59:20] + node _T_2104 = bits(_T_2100, 1, 1) @[Package.scala 63:41] + node _T_2105 = bits(_T_2104, 0, 0) @[Package.scala 59:20] + node _T_2107 = or(_T_2102, _T_2105) @[Package.scala 64:18] + node _T_2108 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2109 = and(_T_2102, _T_2105) @[Package.scala 64:63] + node _T_2110 = or(_T_2108, _T_2109) @[Package.scala 64:51] + node _T_2111 = bits(_T_2099, 4, 2) @[Package.scala 63:41] + node _T_2112 = bits(_T_2111, 0, 0) @[Package.scala 62:39] + node _T_2113 = bits(_T_2112, 0, 0) @[Package.scala 59:20] + node _T_2115 = bits(_T_2111, 2, 1) @[Package.scala 63:41] + node _T_2116 = bits(_T_2115, 0, 0) @[Package.scala 62:39] + node _T_2117 = bits(_T_2116, 0, 0) @[Package.scala 59:20] + node _T_2119 = bits(_T_2115, 1, 1) @[Package.scala 63:41] + node _T_2120 = bits(_T_2119, 0, 0) @[Package.scala 59:20] + node _T_2122 = or(_T_2117, _T_2120) @[Package.scala 64:18] + node _T_2123 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2124 = and(_T_2117, _T_2120) @[Package.scala 64:63] + node _T_2125 = or(_T_2123, _T_2124) @[Package.scala 64:51] + node _T_2126 = or(_T_2113, _T_2122) @[Package.scala 64:18] + node _T_2127 = or(UInt<1>("h00"), _T_2125) @[Package.scala 64:39] + node _T_2128 = and(_T_2113, _T_2122) @[Package.scala 64:63] + node _T_2129 = or(_T_2127, _T_2128) @[Package.scala 64:51] + node _T_2130 = or(_T_2107, _T_2126) @[Package.scala 64:18] + node _T_2131 = or(_T_2110, _T_2129) @[Package.scala 64:39] + node _T_2132 = and(_T_2107, _T_2126) @[Package.scala 64:63] + node _T_2133 = or(_T_2131, _T_2132) @[Package.scala 64:51] + node _T_2134 = or(_T_2095, _T_2130) @[Package.scala 64:18] + node _T_2135 = or(_T_2098, _T_2133) @[Package.scala 64:39] + node _T_2136 = and(_T_2095, _T_2130) @[Package.scala 64:63] + node _T_2137 = or(_T_2135, _T_2136) @[Package.scala 64:51] + node _T_2138 = or(_T_2059, _T_2134) @[Package.scala 64:18] + node _T_2139 = or(_T_2062, _T_2137) @[Package.scala 64:39] + node _T_2140 = and(_T_2059, _T_2134) @[Package.scala 64:63] + node _T_2141 = or(_T_2139, _T_2140) @[Package.scala 64:51] + node _T_2142 = bits(idxHit, 39, 20) @[Package.scala 63:41] + node _T_2143 = bits(_T_2142, 9, 0) @[Package.scala 62:39] + node _T_2144 = bits(_T_2143, 4, 0) @[Package.scala 62:39] + node _T_2145 = bits(_T_2144, 1, 0) @[Package.scala 62:39] + node _T_2146 = bits(_T_2145, 0, 0) @[Package.scala 62:39] + node _T_2147 = bits(_T_2146, 0, 0) @[Package.scala 59:20] + node _T_2149 = bits(_T_2145, 1, 1) @[Package.scala 63:41] + node _T_2150 = bits(_T_2149, 0, 0) @[Package.scala 59:20] + node _T_2152 = or(_T_2147, _T_2150) @[Package.scala 64:18] + node _T_2153 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2154 = and(_T_2147, _T_2150) @[Package.scala 64:63] + node _T_2155 = or(_T_2153, _T_2154) @[Package.scala 64:51] + node _T_2156 = bits(_T_2144, 4, 2) @[Package.scala 63:41] + node _T_2157 = bits(_T_2156, 0, 0) @[Package.scala 62:39] + node _T_2158 = bits(_T_2157, 0, 0) @[Package.scala 59:20] + node _T_2160 = bits(_T_2156, 2, 1) @[Package.scala 63:41] + node _T_2161 = bits(_T_2160, 0, 0) @[Package.scala 62:39] + node _T_2162 = bits(_T_2161, 0, 0) @[Package.scala 59:20] + node _T_2164 = bits(_T_2160, 1, 1) @[Package.scala 63:41] + node _T_2165 = bits(_T_2164, 0, 0) @[Package.scala 59:20] + node _T_2167 = or(_T_2162, _T_2165) @[Package.scala 64:18] + node _T_2168 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2169 = and(_T_2162, _T_2165) @[Package.scala 64:63] + node _T_2170 = or(_T_2168, _T_2169) @[Package.scala 64:51] + node _T_2171 = or(_T_2158, _T_2167) @[Package.scala 64:18] + node _T_2172 = or(UInt<1>("h00"), _T_2170) @[Package.scala 64:39] + node _T_2173 = and(_T_2158, _T_2167) @[Package.scala 64:63] + node _T_2174 = or(_T_2172, _T_2173) @[Package.scala 64:51] + node _T_2175 = or(_T_2152, _T_2171) @[Package.scala 64:18] + node _T_2176 = or(_T_2155, _T_2174) @[Package.scala 64:39] + node _T_2177 = and(_T_2152, _T_2171) @[Package.scala 64:63] + node _T_2178 = or(_T_2176, _T_2177) @[Package.scala 64:51] + node _T_2179 = bits(_T_2143, 9, 5) @[Package.scala 63:41] + node _T_2180 = bits(_T_2179, 1, 0) @[Package.scala 62:39] + node _T_2181 = bits(_T_2180, 0, 0) @[Package.scala 62:39] + node _T_2182 = bits(_T_2181, 0, 0) @[Package.scala 59:20] + node _T_2184 = bits(_T_2180, 1, 1) @[Package.scala 63:41] + node _T_2185 = bits(_T_2184, 0, 0) @[Package.scala 59:20] + node _T_2187 = or(_T_2182, _T_2185) @[Package.scala 64:18] + node _T_2188 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2189 = and(_T_2182, _T_2185) @[Package.scala 64:63] + node _T_2190 = or(_T_2188, _T_2189) @[Package.scala 64:51] + node _T_2191 = bits(_T_2179, 4, 2) @[Package.scala 63:41] + node _T_2192 = bits(_T_2191, 0, 0) @[Package.scala 62:39] + node _T_2193 = bits(_T_2192, 0, 0) @[Package.scala 59:20] + node _T_2195 = bits(_T_2191, 2, 1) @[Package.scala 63:41] + node _T_2196 = bits(_T_2195, 0, 0) @[Package.scala 62:39] + node _T_2197 = bits(_T_2196, 0, 0) @[Package.scala 59:20] + node _T_2199 = bits(_T_2195, 1, 1) @[Package.scala 63:41] + node _T_2200 = bits(_T_2199, 0, 0) @[Package.scala 59:20] + node _T_2202 = or(_T_2197, _T_2200) @[Package.scala 64:18] + node _T_2203 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2204 = and(_T_2197, _T_2200) @[Package.scala 64:63] + node _T_2205 = or(_T_2203, _T_2204) @[Package.scala 64:51] + node _T_2206 = or(_T_2193, _T_2202) @[Package.scala 64:18] + node _T_2207 = or(UInt<1>("h00"), _T_2205) @[Package.scala 64:39] + node _T_2208 = and(_T_2193, _T_2202) @[Package.scala 64:63] + node _T_2209 = or(_T_2207, _T_2208) @[Package.scala 64:51] + node _T_2210 = or(_T_2187, _T_2206) @[Package.scala 64:18] + node _T_2211 = or(_T_2190, _T_2209) @[Package.scala 64:39] + node _T_2212 = and(_T_2187, _T_2206) @[Package.scala 64:63] + node _T_2213 = or(_T_2211, _T_2212) @[Package.scala 64:51] + node _T_2214 = or(_T_2175, _T_2210) @[Package.scala 64:18] + node _T_2215 = or(_T_2178, _T_2213) @[Package.scala 64:39] + node _T_2216 = and(_T_2175, _T_2210) @[Package.scala 64:63] + node _T_2217 = or(_T_2215, _T_2216) @[Package.scala 64:51] + node _T_2218 = bits(_T_2142, 19, 10) @[Package.scala 63:41] + node _T_2219 = bits(_T_2218, 4, 0) @[Package.scala 62:39] + node _T_2220 = bits(_T_2219, 1, 0) @[Package.scala 62:39] + node _T_2221 = bits(_T_2220, 0, 0) @[Package.scala 62:39] + node _T_2222 = bits(_T_2221, 0, 0) @[Package.scala 59:20] + node _T_2224 = bits(_T_2220, 1, 1) @[Package.scala 63:41] + node _T_2225 = bits(_T_2224, 0, 0) @[Package.scala 59:20] + node _T_2227 = or(_T_2222, _T_2225) @[Package.scala 64:18] + node _T_2228 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2229 = and(_T_2222, _T_2225) @[Package.scala 64:63] + node _T_2230 = or(_T_2228, _T_2229) @[Package.scala 64:51] + node _T_2231 = bits(_T_2219, 4, 2) @[Package.scala 63:41] + node _T_2232 = bits(_T_2231, 0, 0) @[Package.scala 62:39] + node _T_2233 = bits(_T_2232, 0, 0) @[Package.scala 59:20] + node _T_2235 = bits(_T_2231, 2, 1) @[Package.scala 63:41] + node _T_2236 = bits(_T_2235, 0, 0) @[Package.scala 62:39] + node _T_2237 = bits(_T_2236, 0, 0) @[Package.scala 59:20] + node _T_2239 = bits(_T_2235, 1, 1) @[Package.scala 63:41] + node _T_2240 = bits(_T_2239, 0, 0) @[Package.scala 59:20] + node _T_2242 = or(_T_2237, _T_2240) @[Package.scala 64:18] + node _T_2243 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2244 = and(_T_2237, _T_2240) @[Package.scala 64:63] + node _T_2245 = or(_T_2243, _T_2244) @[Package.scala 64:51] + node _T_2246 = or(_T_2233, _T_2242) @[Package.scala 64:18] + node _T_2247 = or(UInt<1>("h00"), _T_2245) @[Package.scala 64:39] + node _T_2248 = and(_T_2233, _T_2242) @[Package.scala 64:63] + node _T_2249 = or(_T_2247, _T_2248) @[Package.scala 64:51] + node _T_2250 = or(_T_2227, _T_2246) @[Package.scala 64:18] + node _T_2251 = or(_T_2230, _T_2249) @[Package.scala 64:39] + node _T_2252 = and(_T_2227, _T_2246) @[Package.scala 64:63] + node _T_2253 = or(_T_2251, _T_2252) @[Package.scala 64:51] + node _T_2254 = bits(_T_2218, 9, 5) @[Package.scala 63:41] + node _T_2255 = bits(_T_2254, 1, 0) @[Package.scala 62:39] + node _T_2256 = bits(_T_2255, 0, 0) @[Package.scala 62:39] + node _T_2257 = bits(_T_2256, 0, 0) @[Package.scala 59:20] + node _T_2259 = bits(_T_2255, 1, 1) @[Package.scala 63:41] + node _T_2260 = bits(_T_2259, 0, 0) @[Package.scala 59:20] + node _T_2262 = or(_T_2257, _T_2260) @[Package.scala 64:18] + node _T_2263 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2264 = and(_T_2257, _T_2260) @[Package.scala 64:63] + node _T_2265 = or(_T_2263, _T_2264) @[Package.scala 64:51] + node _T_2266 = bits(_T_2254, 4, 2) @[Package.scala 63:41] + node _T_2267 = bits(_T_2266, 0, 0) @[Package.scala 62:39] + node _T_2268 = bits(_T_2267, 0, 0) @[Package.scala 59:20] + node _T_2270 = bits(_T_2266, 2, 1) @[Package.scala 63:41] + node _T_2271 = bits(_T_2270, 0, 0) @[Package.scala 62:39] + node _T_2272 = bits(_T_2271, 0, 0) @[Package.scala 59:20] + node _T_2274 = bits(_T_2270, 1, 1) @[Package.scala 63:41] + node _T_2275 = bits(_T_2274, 0, 0) @[Package.scala 59:20] + node _T_2277 = or(_T_2272, _T_2275) @[Package.scala 64:18] + node _T_2278 = or(UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 64:39] + node _T_2279 = and(_T_2272, _T_2275) @[Package.scala 64:63] + node _T_2280 = or(_T_2278, _T_2279) @[Package.scala 64:51] + node _T_2281 = or(_T_2268, _T_2277) @[Package.scala 64:18] + node _T_2282 = or(UInt<1>("h00"), _T_2280) @[Package.scala 64:39] + node _T_2283 = and(_T_2268, _T_2277) @[Package.scala 64:63] + node _T_2284 = or(_T_2282, _T_2283) @[Package.scala 64:51] + node _T_2285 = or(_T_2262, _T_2281) @[Package.scala 64:18] + node _T_2286 = or(_T_2265, _T_2284) @[Package.scala 64:39] + node _T_2287 = and(_T_2262, _T_2281) @[Package.scala 64:63] + node _T_2288 = or(_T_2286, _T_2287) @[Package.scala 64:51] + node _T_2289 = or(_T_2250, _T_2285) @[Package.scala 64:18] + node _T_2290 = or(_T_2253, _T_2288) @[Package.scala 64:39] + node _T_2291 = and(_T_2250, _T_2285) @[Package.scala 64:63] + node _T_2292 = or(_T_2290, _T_2291) @[Package.scala 64:51] + node _T_2293 = or(_T_2214, _T_2289) @[Package.scala 64:18] + node _T_2294 = or(_T_2217, _T_2292) @[Package.scala 64:39] + node _T_2295 = and(_T_2214, _T_2289) @[Package.scala 64:63] + node _T_2296 = or(_T_2294, _T_2295) @[Package.scala 64:51] + node _T_2297 = or(_T_2138, _T_2293) @[Package.scala 64:18] + node _T_2298 = or(_T_2141, _T_2296) @[Package.scala 64:39] + node _T_2299 = and(_T_2138, _T_2293) @[Package.scala 64:63] + node _T_2300 = or(_T_2298, _T_2299) @[Package.scala 64:51] + when _T_2300 : @[BTB.scala 241:37] + node _T_2301 = not(idxHit) @[BTB.scala 242:26] + node _T_2302 = and(isValid, _T_2301) @[BTB.scala 242:24] + isValid <= _T_2302 @[BTB.scala 242:13] + skip @[BTB.scala 241:37] + cmem _T_2305 : UInt<2>[128] @[BTB.scala 85:26] + reg _T_2307 : UInt<7>, clock @[BTB.scala 86:20] + node _T_2308 = and(idxHit, isJump) @[BTB.scala 247:29] + node _T_2310 = neq(_T_2308, UInt<1>("h00")) @[BTB.scala 247:39] + node _T_2312 = eq(_T_2310, UInt<1>("h00")) @[BTB.scala 247:20] + node _T_2313 = and(io.req.valid, io.resp.valid) @[BTB.scala 248:54] + node _T_2314 = and(_T_2313, _T_2312) @[BTB.scala 248:71] + wire _T_2318 : {history : UInt<7>, value : UInt<2>} @[BTB.scala 71:19] + _T_2318 is invalid @[BTB.scala 71:19] + node _T_2321 = bits(io.req.bits.addr, 8, 1) @[BTB.scala 72:21] + node _T_2322 = xor(_T_2321, _T_2307) @[BTB.scala 72:57] + node _T_2323 = bits(_T_2322, 6, 0) + infer mport _T_2324 = _T_2305[_T_2323], clock + _T_2318.value <= _T_2324 @[BTB.scala 73:15] + _T_2318.history <= _T_2307 @[BTB.scala 74:17] + node _T_2325 = bits(_T_2318.value, 0, 0) @[BTB.scala 75:26] + when _T_2314 : @[BTB.scala 76:19] + node _T_2326 = bits(_T_2307, 6, 1) @[BTB.scala 76:50] + node _T_2327 = cat(_T_2325, _T_2326) @[Cat.scala 30:58] + _T_2307 <= _T_2327 @[BTB.scala 76:29] + skip @[BTB.scala 76:19] + node _T_2328 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) @[BTB.scala 250:31] + when _T_2328 : @[BTB.scala 250:50] + node _T_2329 = bits(io.bht_update.bits.pc, 8, 1) @[BTB.scala 80:21] + node _T_2330 = xor(_T_2329, io.bht_update.bits.prediction.bits.bht.history) @[BTB.scala 80:57] + node _T_2331 = bits(_T_2330, 6, 0) + infer mport _T_2332 = _T_2305[_T_2331], clock + node _T_2333 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) @[BTB.scala 81:40] + node _T_2334 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) @[BTB.scala 81:53] + node _T_2335 = and(_T_2333, _T_2334) @[BTB.scala 81:44] + node _T_2336 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) @[BTB.scala 81:69] + node _T_2337 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) @[BTB.scala 81:82] + node _T_2338 = or(_T_2336, _T_2337) @[BTB.scala 81:73] + node _T_2339 = and(_T_2338, io.bht_update.bits.taken) @[BTB.scala 81:87] + node _T_2340 = or(_T_2335, _T_2339) @[BTB.scala 81:58] + node _T_2341 = cat(io.bht_update.bits.taken, _T_2340) @[Cat.scala 30:58] + _T_2332 <= _T_2341 @[BTB.scala 81:18] + when io.bht_update.bits.mispredict : @[BTB.scala 82:23] + node _T_2342 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) @[BTB.scala 82:56] + node _T_2343 = cat(io.bht_update.bits.taken, _T_2342) @[Cat.scala 30:58] + _T_2307 <= _T_2343 @[BTB.scala 82:33] + skip @[BTB.scala 82:23] + skip @[BTB.scala 250:50] + node _T_2344 = bits(_T_2318.value, 0, 0) @[BTB.scala 253:21] + node _T_2346 = eq(_T_2344, UInt<1>("h00")) @[BTB.scala 253:11] + node _T_2347 = and(_T_2346, _T_2312) @[BTB.scala 253:25] + when _T_2347 : @[BTB.scala 253:38] + io.resp.bits.taken <= UInt<1>("h00") @[BTB.scala 253:59] + skip @[BTB.scala 253:38] + io.resp.bits.bht <- _T_2318 @[BTB.scala 254:22] + reg _T_2350 : UInt<2>, clock @[BTB.scala 49:26] + reg _T_2352 : UInt<1>, clock @[BTB.scala 50:24] + reg _T_2356 : UInt[2], clock @[BTB.scala 51:26] + node _T_2361 = and(idxHit, isReturn) @[BTB.scala 259:26] + node _T_2363 = neq(_T_2361, UInt<1>("h00")) @[BTB.scala 259:38] + node _T_2365 = eq(_T_2350, UInt<1>("h00")) @[BTB.scala 47:29] + node _T_2367 = eq(_T_2365, UInt<1>("h00")) @[BTB.scala 260:11] + node _T_2368 = and(_T_2367, _T_2363) @[BTB.scala 260:24] + when _T_2368 : @[BTB.scala 260:35] + io.resp.bits.target <= _T_2356[_T_2352] @[BTB.scala 261:27] + skip @[BTB.scala 260:35] + when io.ras_update.valid : @[BTB.scala 263:32] + when io.ras_update.bits.isCall : @[BTB.scala 264:40] + node _T_2371 = lt(_T_2350, UInt<2>("h02")) @[BTB.scala 36:17] + when _T_2371 : @[BTB.scala 36:25] + node _T_2373 = add(_T_2350, UInt<1>("h01")) @[BTB.scala 36:42] + node _T_2374 = tail(_T_2373, 1) @[BTB.scala 36:42] + _T_2350 <= _T_2374 @[BTB.scala 36:33] + skip @[BTB.scala 36:25] + node _T_2377 = lt(_T_2352, UInt<1>("h01")) @[BTB.scala 37:49] + node _T_2378 = or(UInt<1>("h01"), _T_2377) @[BTB.scala 37:42] + node _T_2380 = add(_T_2352, UInt<1>("h01")) @[BTB.scala 37:62] + node _T_2381 = tail(_T_2380, 1) @[BTB.scala 37:62] + node _T_2383 = mux(_T_2378, _T_2381, UInt<1>("h00")) @[BTB.scala 37:22] + _T_2356[_T_2383] <= io.ras_update.bits.returnAddr @[BTB.scala 38:20] + _T_2352 <= _T_2383 @[BTB.scala 39:9] + when _T_2363 : @[BTB.scala 266:23] + io.resp.bits.target <= io.ras_update.bits.returnAddr @[BTB.scala 267:31] + skip @[BTB.scala 266:23] + skip @[BTB.scala 264:40] + node _T_2385 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) @[BTB.scala 269:47] + node _T_2387 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) @[BTB.scala 264:40] + node _T_2388 = and(_T_2387, _T_2385) @[BTB.scala 269:87] + when _T_2388 : @[BTB.scala 269:87] + node _T_2390 = eq(_T_2350, UInt<1>("h00")) @[BTB.scala 47:29] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[BTB.scala 42:27] + when _T_2392 : @[BTB.scala 42:37] + node _T_2394 = sub(_T_2350, UInt<1>("h01")) @[BTB.scala 43:20] + node _T_2395 = asUInt(_T_2394) @[BTB.scala 43:20] + node _T_2396 = tail(_T_2395, 1) @[BTB.scala 43:20] + _T_2350 <= _T_2396 @[BTB.scala 43:11] + node _T_2399 = gt(_T_2352, UInt<1>("h00")) @[BTB.scala 44:42] + node _T_2400 = or(UInt<1>("h01"), _T_2399) @[BTB.scala 44:35] + node _T_2402 = sub(_T_2352, UInt<1>("h01")) @[BTB.scala 44:50] + node _T_2403 = asUInt(_T_2402) @[BTB.scala 44:50] + node _T_2404 = tail(_T_2403, 1) @[BTB.scala 44:50] + node _T_2406 = mux(_T_2400, _T_2404, UInt<1>("h01")) @[BTB.scala 44:15] + _T_2352 <= _T_2406 @[BTB.scala 44:9] + skip @[BTB.scala 42:37] + skip @[BTB.scala 269:87] + skip @[BTB.scala 263:32] + + module Frontend_frontend : + input clock : Clock + input reset : UInt<1> + output io : {mem : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>, flip acquire : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>}}, flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip resetVector : UInt<40>} + + io is invalid + io is invalid + inst icache of ICache_icache @[LazyModule.scala 60:13] + icache.io is invalid + icache.clock <= clock + icache.reset <= reset + inst TLMonitor of TLMonitor_32 @[LazyModule.scala 60:13] + TLMonitor.io is invalid + TLMonitor.clock <= clock + TLMonitor.reset <= reset + wire _T_88 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_88 is invalid @[Bundles.scala 234:19] + wire _T_185 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_185 is invalid @[Bundles.scala 214:19] + _T_185.ready <= io.mem.0.a.ready @[Bundles.scala 215:15] + _T_185.valid <= icache.io.mem.0.a.valid @[Bundles.scala 216:15] + _T_185.bits <- icache.io.mem.0.a.bits @[Bundles.scala 217:15] + _T_88.a <- _T_185 @[Bundles.scala 235:11] + wire _T_207 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_207 is invalid @[Bundles.scala 214:19] + _T_207.ready <= icache.io.mem.0.b.ready @[Bundles.scala 215:15] + _T_207.valid <= io.mem.0.b.valid @[Bundles.scala 216:15] + _T_207.bits <- io.mem.0.b.bits @[Bundles.scala 217:15] + _T_88.b <- _T_207 @[Bundles.scala 236:11] + wire _T_229 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_229 is invalid @[Bundles.scala 214:19] + _T_229.ready <= io.mem.0.c.ready @[Bundles.scala 215:15] + _T_229.valid <= icache.io.mem.0.c.valid @[Bundles.scala 216:15] + _T_229.bits <- icache.io.mem.0.c.bits @[Bundles.scala 217:15] + _T_88.c <- _T_229 @[Bundles.scala 237:11] + wire _T_252 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_252 is invalid @[Bundles.scala 214:19] + _T_252.ready <= icache.io.mem.0.d.ready @[Bundles.scala 215:15] + _T_252.valid <= io.mem.0.d.valid @[Bundles.scala 216:15] + _T_252.bits <- io.mem.0.d.bits @[Bundles.scala 217:15] + _T_88.d <- _T_252 @[Bundles.scala 238:11] + wire _T_269 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_269 is invalid @[Bundles.scala 214:19] + _T_269.ready <= io.mem.0.e.ready @[Bundles.scala 215:15] + _T_269.valid <= icache.io.mem.0.e.valid @[Bundles.scala 216:15] + _T_269.bits <- icache.io.mem.0.e.bits @[Bundles.scala 217:15] + _T_88.e <- _T_269 @[Bundles.scala 239:11] + TLMonitor.io.in[0] <- _T_88 @[Frontend.scala 48:8] + io.mem.0 <- icache.io.mem.0 @[Frontend.scala 48:8] + inst tlb of TLB_1 @[Frontend.scala 65:19] + tlb.io is invalid + tlb.clock <= clock + tlb.reset <= reset + reg s1_pc_ : UInt<40>, clock @[Frontend.scala 67:19] + node _T_1519 = not(s1_pc_) @[Frontend.scala 68:17] + node _T_1521 = or(_T_1519, UInt<1>("h01")) @[Frontend.scala 68:25] + node s1_pc = not(_T_1521) @[Frontend.scala 68:15] + reg s1_speculative : UInt<1>, clock @[Frontend.scala 69:27] + reg s1_same_block : UInt<1>, clock @[Frontend.scala 70:26] + reg s2_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[Frontend.scala 71:21] + reg s2_pc : UInt, clock with : (reset => (reset, io.resetVector)) @[Frontend.scala 72:18] + reg s2_btb_resp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Frontend.scala 73:30] + reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Frontend.scala 74:29] + reg s2_xcpt_if : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Frontend.scala 75:23] + reg s2_speculative : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Frontend.scala 76:27] + reg s2_cacheable : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Frontend.scala 77:25] + node _T_1546 = not(s1_pc) @[Frontend.scala 79:16] + node _T_1548 = or(_T_1546, UInt<2>("h03")) @[Frontend.scala 79:23] + node _T_1549 = not(_T_1548) @[Frontend.scala 79:14] + node _T_1551 = add(_T_1549, UInt<3>("h04")) @[Frontend.scala 79:55] + node ntpc = tail(_T_1551, 1) @[Frontend.scala 79:55] + node _T_1553 = and(ntpc, UInt<4>("h08")) @[Frontend.scala 80:31] + node _T_1555 = and(s1_pc, UInt<4>("h08")) @[Frontend.scala 80:54] + node ntpc_same_block = eq(_T_1553, _T_1555) @[Frontend.scala 80:43] + wire predicted_npc : UInt + predicted_npc is invalid + predicted_npc <= ntpc + wire predicted_taken : UInt<1> + predicted_taken is invalid + predicted_taken <= UInt<1>("h00") + node _T_1558 = eq(icache.io.resp.valid, UInt<1>("h00")) @[Frontend.scala 83:28] + node icmiss = and(s2_valid, _T_1558) @[Frontend.scala 83:25] + node npc = mux(icmiss, s2_pc, predicted_npc) @[Frontend.scala 84:16] + node _T_1560 = eq(predicted_taken, UInt<1>("h00")) @[Frontend.scala 85:23] + node _T_1562 = eq(icmiss, UInt<1>("h00")) @[Frontend.scala 85:43] + node _T_1563 = and(_T_1560, _T_1562) @[Frontend.scala 85:40] + node _T_1565 = eq(io.cpu.req.valid, UInt<1>("h00")) @[Frontend.scala 85:54] + node _T_1566 = and(_T_1563, _T_1565) @[Frontend.scala 85:51] + node s0_same_block = and(_T_1566, ntpc_same_block) @[Frontend.scala 85:72] + node _T_1568 = eq(io.cpu.resp.ready, UInt<1>("h00")) @[Frontend.scala 87:36] + node stall = and(io.cpu.resp.valid, _T_1568) @[Frontend.scala 87:33] + node _T_1570 = eq(stall, UInt<1>("h00")) @[Frontend.scala 88:9] + when _T_1570 : @[Frontend.scala 88:17] + node _T_1572 = eq(tlb.io.resp.miss, UInt<1>("h00")) @[Frontend.scala 89:39] + node _T_1573 = and(s0_same_block, _T_1572) @[Frontend.scala 89:36] + s1_same_block <= _T_1573 @[Frontend.scala 89:19] + s1_pc_ <= io.cpu.npc @[Frontend.scala 90:12] + node _T_1575 = eq(s2_speculative, UInt<1>("h00")) @[Frontend.scala 94:58] + node _T_1576 = and(s2_valid, _T_1575) @[Frontend.scala 94:55] + node _T_1577 = or(s1_speculative, _T_1576) @[Frontend.scala 94:43] + node _T_1578 = or(_T_1577, predicted_taken) @[Frontend.scala 94:74] + node _T_1579 = mux(icmiss, s2_speculative, _T_1578) @[Frontend.scala 96:26] + s1_speculative <= _T_1579 @[Frontend.scala 96:20] + node _T_1581 = eq(icmiss, UInt<1>("h00")) @[Frontend.scala 97:17] + s2_valid <= _T_1581 @[Frontend.scala 97:14] + node _T_1583 = eq(icmiss, UInt<1>("h00")) @[Frontend.scala 98:11] + when _T_1583 : @[Frontend.scala 98:20] + s2_pc <= s1_pc @[Frontend.scala 99:13] + s2_speculative <= s1_speculative @[Frontend.scala 100:22] + s2_cacheable <= tlb.io.resp.cacheable @[Frontend.scala 101:20] + node _T_1585 = eq(tlb.io.resp.miss, UInt<1>("h00")) @[Frontend.scala 102:44] + node _T_1586 = and(tlb.io.resp.xcpt_if, _T_1585) @[Frontend.scala 102:41] + s2_xcpt_if <= _T_1586 @[Frontend.scala 102:18] + skip @[Frontend.scala 98:20] + skip @[Frontend.scala 88:17] + when io.cpu.req.valid : @[Frontend.scala 105:27] + s1_same_block <= UInt<1>("h00") @[Frontend.scala 106:19] + s1_pc_ <= io.cpu.npc @[Frontend.scala 107:12] + s1_speculative <= io.cpu.req.bits.speculative @[Frontend.scala 108:20] + s2_valid <= UInt<1>("h00") @[Frontend.scala 109:14] + skip @[Frontend.scala 105:27] + inst BTB of BTB @[Frontend.scala 113:21] + BTB.io is invalid + BTB.clock <= clock + BTB.reset <= reset + BTB.io.req.valid <= UInt<1>("h00") @[Frontend.scala 114:22] + BTB.io.req.bits.addr <= s1_pc_ @[Frontend.scala 115:26] + BTB.io.btb_update <- io.cpu.btb_update @[Frontend.scala 116:23] + BTB.io.bht_update <- io.cpu.bht_update @[Frontend.scala 117:23] + BTB.io.ras_update <- io.cpu.ras_update @[Frontend.scala 118:23] + node _T_1591 = eq(stall, UInt<1>("h00")) @[Frontend.scala 119:11] + node _T_1593 = eq(icmiss, UInt<1>("h00")) @[Frontend.scala 119:21] + node _T_1594 = and(_T_1591, _T_1593) @[Frontend.scala 119:18] + when _T_1594 : @[Frontend.scala 119:30] + BTB.io.req.valid <= UInt<1>("h01") @[Frontend.scala 120:24] + s2_btb_resp_valid <= BTB.io.resp.valid @[Frontend.scala 121:25] + s2_btb_resp_bits <- BTB.io.resp.bits @[Frontend.scala 122:24] + skip @[Frontend.scala 119:30] + node _T_1596 = and(BTB.io.resp.valid, BTB.io.resp.bits.taken) @[Frontend.scala 124:29] + when _T_1596 : @[Frontend.scala 124:56] + node _T_1597 = bits(BTB.io.resp.bits.target, 38, 38) @[Package.scala 40:38] + node _T_1598 = cat(_T_1597, BTB.io.resp.bits.target) @[Cat.scala 30:58] + predicted_npc <= _T_1598 @[Frontend.scala 125:21] + predicted_taken <= UInt<1>("h01") @[Frontend.scala 126:23] + skip @[Frontend.scala 124:56] + io.ptw <- tlb.io.ptw @[Frontend.scala 130:10] + node _T_1601 = eq(stall, UInt<1>("h00")) @[Frontend.scala 131:23] + node _T_1603 = eq(icmiss, UInt<1>("h00")) @[Frontend.scala 131:33] + node _T_1604 = and(_T_1601, _T_1603) @[Frontend.scala 131:30] + tlb.io.req.valid <= _T_1604 @[Frontend.scala 131:20] + tlb.io.req.bits.vaddr <= s1_pc @[Frontend.scala 132:25] + tlb.io.req.bits.passthrough <= UInt<1>("h00") @[Frontend.scala 133:31] + tlb.io.req.bits.instruction <= UInt<1>("h01") @[Frontend.scala 134:31] + tlb.io.req.bits.store <= UInt<1>("h00") @[Frontend.scala 135:25] + node _T_1609 = eq(stall, UInt<1>("h00")) @[Frontend.scala 137:26] + node _T_1611 = eq(s0_same_block, UInt<1>("h00")) @[Frontend.scala 137:36] + node _T_1612 = and(_T_1609, _T_1611) @[Frontend.scala 137:33] + icache.io.req.valid <= _T_1612 @[Frontend.scala 137:23] + icache.io.req.bits.addr <= io.cpu.npc @[Frontend.scala 138:27] + icache.io.invalidate <= io.cpu.flush_icache @[Frontend.scala 139:24] + icache.io.s1_paddr <= tlb.io.resp.paddr @[Frontend.scala 140:22] + node _T_1613 = or(io.cpu.req.valid, tlb.io.resp.miss) @[Frontend.scala 141:41] + node _T_1614 = or(_T_1613, tlb.io.resp.xcpt_if) @[Frontend.scala 141:61] + node _T_1615 = or(_T_1614, icmiss) @[Frontend.scala 141:84] + node _T_1616 = or(_T_1615, io.cpu.flush_tlb) @[Frontend.scala 141:94] + icache.io.s1_kill <= _T_1616 @[Frontend.scala 141:21] + node _T_1618 = eq(s2_cacheable, UInt<1>("h00")) @[Frontend.scala 142:42] + node _T_1619 = and(s2_speculative, _T_1618) @[Frontend.scala 142:39] + icache.io.s2_kill <= _T_1619 @[Frontend.scala 142:21] + node _T_1621 = eq(stall, UInt<1>("h00")) @[Frontend.scala 143:27] + node _T_1623 = eq(s1_same_block, UInt<1>("h00")) @[Frontend.scala 143:37] + node _T_1624 = and(_T_1621, _T_1623) @[Frontend.scala 143:34] + icache.io.resp.ready <= _T_1624 @[Frontend.scala 143:24] + node _T_1625 = or(icache.io.resp.valid, icache.io.s2_kill) @[Frontend.scala 145:58] + node _T_1626 = or(_T_1625, s2_xcpt_if) @[Frontend.scala 145:79] + node _T_1627 = and(s2_valid, _T_1626) @[Frontend.scala 145:33] + io.cpu.resp.valid <= _T_1627 @[Frontend.scala 145:21] + io.cpu.resp.bits.pc <= s2_pc @[Frontend.scala 146:23] + node _T_1628 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) @[Frontend.scala 147:20] + io.cpu.npc <= _T_1628 @[Frontend.scala 147:14] + node _T_1629 = bits(s2_pc, 2, 2) @[Package.scala 44:13] + node _T_1630 = shl(_T_1629, 5) @[Frontend.scala 150:133] + node _T_1631 = dshr(icache.io.resp.bits.datablock, _T_1630) @[Frontend.scala 150:58] + io.cpu.resp.bits.data <= _T_1631 @[Frontend.scala 150:25] + node _T_1633 = bits(s2_pc, 1, 1) @[Package.scala 44:13] + node _T_1634 = dshl(UInt<2>("h03"), _T_1633) @[Frontend.scala 151:54] + io.cpu.resp.bits.mask <= _T_1634 @[Frontend.scala 151:25] + io.cpu.resp.bits.xcpt_if <= s2_xcpt_if @[Frontend.scala 152:28] + node _T_1636 = eq(icache.io.resp.valid, UInt<1>("h00")) @[Frontend.scala 153:51] + node _T_1637 = and(icache.io.s2_kill, _T_1636) @[Frontend.scala 153:48] + node _T_1639 = eq(s2_xcpt_if, UInt<1>("h00")) @[Frontend.scala 153:76] + node _T_1640 = and(_T_1637, _T_1639) @[Frontend.scala 153:73] + io.cpu.resp.bits.replay <= _T_1640 @[Frontend.scala 153:27] + io.cpu.resp.bits.btb.valid <= s2_btb_resp_valid @[Frontend.scala 154:30] + io.cpu.resp.bits.btb.bits <- s2_btb_resp_bits @[Frontend.scala 155:29] + node _T_1641 = and(icache.io.mem.0.a.ready, icache.io.mem.0.a.valid) @[Decoupled.scala 30:37] + node _T_1643 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1644 = dshl(_T_1643, icache.io.mem.0.a.bits.size) @[package.scala 19:71] + node _T_1645 = bits(_T_1644, 7, 0) @[package.scala 19:76] + node _T_1646 = not(_T_1645) @[package.scala 19:40] + node _T_1647 = shr(_T_1646, 3) @[Edges.scala 198:59] + node _T_1648 = bits(icache.io.mem.0.a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1650 = eq(_T_1648, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1652 = mux(_T_1650, _T_1647, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1654 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1656 = sub(_T_1654, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1657 = asUInt(_T_1656) @[Edges.scala 208:28] + node _T_1658 = tail(_T_1657, 1) @[Edges.scala 208:28] + node _T_1660 = eq(_T_1654, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1662 = eq(_T_1654, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1664 = eq(_T_1652, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1665 = or(_T_1662, _T_1664) @[Edges.scala 210:37] + node _T_1666 = and(_T_1665, _T_1641) @[Edges.scala 211:22] + node _T_1667 = not(_T_1658) @[Edges.scala 212:27] + node _T_1668 = and(_T_1652, _T_1667) @[Edges.scala 212:25] + when _T_1641 : @[Edges.scala 213:17] + node _T_1669 = mux(_T_1660, _T_1652, _T_1658) @[Edges.scala 214:21] + _T_1654 <= _T_1669 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + io.cpu.acquire <= _T_1666 @[Frontend.scala 158:18] + + module TLMonitor_33 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[Frontend.scala 165:14] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[Frontend.scala 165:14] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_608 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at Frontend.scala:165:14)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_610 = eq(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_613 : UInt<1>[1] @[Parameters.scala 228:27] + _T_613 is invalid @[Parameters.scala 228:27] + _T_613[0] <= _T_610 @[Parameters.scala 228:27] + node _T_618 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_619 = dshl(_T_618, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_620 = bits(_T_619, 7, 0) @[package.scala 19:76] + node _T_621 = not(_T_620) @[package.scala 19:40] + node _T_622 = and(io.in[0].a.bits.address, _T_621) @[Edges.scala 17:16] + node _T_624 = eq(_T_622, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_626 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_627 = dshl(UInt<1>("h01"), _T_626) @[OneHot.scala 49:12] + node _T_628 = bits(_T_627, 2, 0) @[OneHot.scala 49:37] + node _T_630 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_632 = bits(_T_628, 2, 2) @[package.scala 44:26] + node _T_633 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_635 = eq(_T_633, UInt<1>("h00")) @[package.scala 46:20] + node _T_636 = and(UInt<1>("h01"), _T_635) @[package.scala 49:27] + node _T_637 = and(_T_632, _T_636) @[package.scala 50:38] + node _T_638 = or(_T_630, _T_637) @[package.scala 50:29] + node _T_639 = and(UInt<1>("h01"), _T_633) @[package.scala 49:27] + node _T_640 = and(_T_632, _T_639) @[package.scala 50:38] + node _T_641 = or(_T_630, _T_640) @[package.scala 50:29] + node _T_642 = bits(_T_628, 1, 1) @[package.scala 44:26] + node _T_643 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_645 = eq(_T_643, UInt<1>("h00")) @[package.scala 46:20] + node _T_646 = and(_T_636, _T_645) @[package.scala 49:27] + node _T_647 = and(_T_642, _T_646) @[package.scala 50:38] + node _T_648 = or(_T_638, _T_647) @[package.scala 50:29] + node _T_649 = and(_T_636, _T_643) @[package.scala 49:27] + node _T_650 = and(_T_642, _T_649) @[package.scala 50:38] + node _T_651 = or(_T_638, _T_650) @[package.scala 50:29] + node _T_652 = and(_T_639, _T_645) @[package.scala 49:27] + node _T_653 = and(_T_642, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_641, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_639, _T_643) @[package.scala 49:27] + node _T_656 = and(_T_642, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_641, _T_656) @[package.scala 50:29] + node _T_658 = bits(_T_628, 0, 0) @[package.scala 44:26] + node _T_659 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_661 = eq(_T_659, UInt<1>("h00")) @[package.scala 46:20] + node _T_662 = and(_T_646, _T_661) @[package.scala 49:27] + node _T_663 = and(_T_658, _T_662) @[package.scala 50:38] + node _T_664 = or(_T_648, _T_663) @[package.scala 50:29] + node _T_665 = and(_T_646, _T_659) @[package.scala 49:27] + node _T_666 = and(_T_658, _T_665) @[package.scala 50:38] + node _T_667 = or(_T_648, _T_666) @[package.scala 50:29] + node _T_668 = and(_T_649, _T_661) @[package.scala 49:27] + node _T_669 = and(_T_658, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_651, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_649, _T_659) @[package.scala 49:27] + node _T_672 = and(_T_658, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_651, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_652, _T_661) @[package.scala 49:27] + node _T_675 = and(_T_658, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_654, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_652, _T_659) @[package.scala 49:27] + node _T_678 = and(_T_658, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_654, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_655, _T_661) @[package.scala 49:27] + node _T_681 = and(_T_658, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_657, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_655, _T_659) @[package.scala 49:27] + node _T_684 = and(_T_658, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_657, _T_684) @[package.scala 50:29] + node _T_686 = cat(_T_667, _T_664) @[Cat.scala 30:58] + node _T_687 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_688 = cat(_T_687, _T_686) @[Cat.scala 30:58] + node _T_689 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_690 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_691 = cat(_T_690, _T_689) @[Cat.scala 30:58] + node _T_692 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_694 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + when _T_694 : @[Frontend.scala 165:14] + node _T_697 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_699 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_700 = and(_T_697, _T_699) @[Parameters.scala 63:37] + node _T_701 = or(UInt<1>("h00"), _T_700) @[Parameters.scala 132:31] + node _T_703 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_704 = cvt(_T_703) @[Parameters.scala 117:49] + node _T_706 = and(_T_704, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_707 = asSInt(_T_706) @[Parameters.scala 117:52] + node _T_709 = eq(_T_707, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_711 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_712 = cvt(_T_711) @[Parameters.scala 117:49] + node _T_714 = and(_T_712, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_715 = asSInt(_T_714) @[Parameters.scala 117:52] + node _T_717 = eq(_T_715, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_718 = or(_T_709, _T_717) @[Parameters.scala 133:42] + node _T_719 = and(_T_701, _T_718) @[Parameters.scala 132:56] + node _T_722 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_724 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_725 = cvt(_T_724) @[Parameters.scala 117:49] + node _T_727 = and(_T_725, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_728 = asSInt(_T_727) @[Parameters.scala 117:52] + node _T_730 = eq(_T_728, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_732 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_733 = cvt(_T_732) @[Parameters.scala 117:49] + node _T_735 = and(_T_733, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_736 = asSInt(_T_735) @[Parameters.scala 117:52] + node _T_738 = eq(_T_736, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_740 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_741 = cvt(_T_740) @[Parameters.scala 117:49] + node _T_743 = and(_T_741, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_744 = asSInt(_T_743) @[Parameters.scala 117:52] + node _T_746 = eq(_T_744, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_748 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_749 = cvt(_T_748) @[Parameters.scala 117:49] + node _T_751 = and(_T_749, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_752 = asSInt(_T_751) @[Parameters.scala 117:52] + node _T_754 = eq(_T_752, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_755 = or(_T_730, _T_738) @[Parameters.scala 133:42] + node _T_756 = or(_T_755, _T_746) @[Parameters.scala 133:42] + node _T_757 = or(_T_756, _T_754) @[Parameters.scala 133:42] + node _T_758 = and(_T_722, _T_757) @[Parameters.scala 132:56] + node _T_760 = or(UInt<1>("h00"), _T_719) @[Parameters.scala 134:30] + node _T_761 = or(_T_760, _T_758) @[Parameters.scala 134:30] + node _T_762 = or(_T_761, reset) @[Frontend.scala 165:14] + node _T_764 = eq(_T_762, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_764 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_765 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_767 = eq(_T_765, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_767 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_769 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_770 = or(_T_769, reset) @[Frontend.scala 165:14] + node _T_772 = eq(_T_770, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_772 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_773 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_775 = eq(_T_773, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_775 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_777 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_778 = or(_T_777, reset) @[Frontend.scala 165:14] + node _T_780 = eq(_T_778, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_780 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at Frontend.scala:165:14)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_781 = not(io.in[0].a.bits.mask) @[Frontend.scala 165:14] + node _T_783 = eq(_T_781, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_784 = or(_T_783, reset) @[Frontend.scala 165:14] + node _T_786 = eq(_T_784, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_786 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_788 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[Frontend.scala 165:14] + when _T_788 : @[Frontend.scala 165:14] + node _T_791 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_793 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_794 = and(_T_791, _T_793) @[Parameters.scala 63:37] + node _T_795 = or(UInt<1>("h00"), _T_794) @[Parameters.scala 132:31] + node _T_797 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_798 = cvt(_T_797) @[Parameters.scala 117:49] + node _T_800 = and(_T_798, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_801 = asSInt(_T_800) @[Parameters.scala 117:52] + node _T_803 = eq(_T_801, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_805 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_806 = cvt(_T_805) @[Parameters.scala 117:49] + node _T_808 = and(_T_806, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_809 = asSInt(_T_808) @[Parameters.scala 117:52] + node _T_811 = eq(_T_809, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_813 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_814 = cvt(_T_813) @[Parameters.scala 117:49] + node _T_816 = and(_T_814, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_817 = asSInt(_T_816) @[Parameters.scala 117:52] + node _T_819 = eq(_T_817, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_821 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_822 = cvt(_T_821) @[Parameters.scala 117:49] + node _T_824 = and(_T_822, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_825 = asSInt(_T_824) @[Parameters.scala 117:52] + node _T_827 = eq(_T_825, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_829 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_830 = cvt(_T_829) @[Parameters.scala 117:49] + node _T_832 = and(_T_830, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_833 = asSInt(_T_832) @[Parameters.scala 117:52] + node _T_835 = eq(_T_833, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_836 = or(_T_803, _T_811) @[Parameters.scala 133:42] + node _T_837 = or(_T_836, _T_819) @[Parameters.scala 133:42] + node _T_838 = or(_T_837, _T_827) @[Parameters.scala 133:42] + node _T_839 = or(_T_838, _T_835) @[Parameters.scala 133:42] + node _T_840 = and(_T_795, _T_839) @[Parameters.scala 132:56] + node _T_843 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_845 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_846 = and(_T_843, _T_845) @[Parameters.scala 63:37] + node _T_847 = or(UInt<1>("h00"), _T_846) @[Parameters.scala 132:31] + node _T_849 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_850 = cvt(_T_849) @[Parameters.scala 117:49] + node _T_852 = and(_T_850, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_853 = asSInt(_T_852) @[Parameters.scala 117:52] + node _T_855 = eq(_T_853, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_856 = and(_T_847, _T_855) @[Parameters.scala 132:56] + node _T_858 = or(UInt<1>("h00"), _T_840) @[Parameters.scala 134:30] + node _T_859 = or(_T_858, _T_856) @[Parameters.scala 134:30] + node _T_860 = or(_T_859, reset) @[Frontend.scala 165:14] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_862 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_863 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_865 = eq(_T_863, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_865 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_866 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_868 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_870 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_871 = or(_T_870, reset) @[Frontend.scala 165:14] + node _T_873 = eq(_T_871, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_873 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_874 = eq(io.in[0].a.bits.mask, _T_692) @[Frontend.scala 165:14] + node _T_875 = or(_T_874, reset) @[Frontend.scala 165:14] + node _T_877 = eq(_T_875, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_877 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_879 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_879 : @[Frontend.scala 165:14] + node _T_882 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_884 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_885 = and(_T_882, _T_884) @[Parameters.scala 63:37] + node _T_886 = or(UInt<1>("h00"), _T_885) @[Parameters.scala 132:31] + node _T_888 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_889 = cvt(_T_888) @[Parameters.scala 117:49] + node _T_891 = and(_T_889, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_892 = asSInt(_T_891) @[Parameters.scala 117:52] + node _T_894 = eq(_T_892, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_896 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_897 = cvt(_T_896) @[Parameters.scala 117:49] + node _T_899 = and(_T_897, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_900 = asSInt(_T_899) @[Parameters.scala 117:52] + node _T_902 = eq(_T_900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_904 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_905 = cvt(_T_904) @[Parameters.scala 117:49] + node _T_907 = and(_T_905, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_908 = asSInt(_T_907) @[Parameters.scala 117:52] + node _T_910 = eq(_T_908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_912 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_913 = cvt(_T_912) @[Parameters.scala 117:49] + node _T_915 = and(_T_913, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_916 = asSInt(_T_915) @[Parameters.scala 117:52] + node _T_918 = eq(_T_916, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_920 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_921 = cvt(_T_920) @[Parameters.scala 117:49] + node _T_923 = and(_T_921, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_924 = asSInt(_T_923) @[Parameters.scala 117:52] + node _T_926 = eq(_T_924, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_927 = or(_T_894, _T_902) @[Parameters.scala 133:42] + node _T_928 = or(_T_927, _T_910) @[Parameters.scala 133:42] + node _T_929 = or(_T_928, _T_918) @[Parameters.scala 133:42] + node _T_930 = or(_T_929, _T_926) @[Parameters.scala 133:42] + node _T_931 = and(_T_886, _T_930) @[Parameters.scala 132:56] + node _T_934 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_936 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_937 = and(_T_934, _T_936) @[Parameters.scala 63:37] + node _T_938 = or(UInt<1>("h00"), _T_937) @[Parameters.scala 132:31] + node _T_940 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_941 = cvt(_T_940) @[Parameters.scala 117:49] + node _T_943 = and(_T_941, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_944 = asSInt(_T_943) @[Parameters.scala 117:52] + node _T_946 = eq(_T_944, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_947 = and(_T_938, _T_946) @[Parameters.scala 132:56] + node _T_950 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_952 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_953 = cvt(_T_952) @[Parameters.scala 117:49] + node _T_955 = and(_T_953, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_956 = asSInt(_T_955) @[Parameters.scala 117:52] + node _T_958 = eq(_T_956, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_959 = and(_T_950, _T_958) @[Parameters.scala 132:56] + node _T_961 = or(UInt<1>("h00"), _T_931) @[Parameters.scala 134:30] + node _T_962 = or(_T_961, _T_947) @[Parameters.scala 134:30] + node _T_963 = or(_T_962, _T_959) @[Parameters.scala 134:30] + node _T_964 = or(_T_963, reset) @[Frontend.scala 165:14] + node _T_966 = eq(_T_964, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_966 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_967 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_969 = eq(_T_967, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_969 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_970 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_972 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_974 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_975 = or(_T_974, reset) @[Frontend.scala 165:14] + node _T_977 = eq(_T_975, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_977 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_978 = eq(io.in[0].a.bits.mask, _T_692) @[Frontend.scala 165:14] + node _T_979 = or(_T_978, reset) @[Frontend.scala 165:14] + node _T_981 = eq(_T_979, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_981 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_983 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[Frontend.scala 165:14] + when _T_983 : @[Frontend.scala 165:14] + node _T_986 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_988 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_989 = and(_T_986, _T_988) @[Parameters.scala 63:37] + node _T_990 = or(UInt<1>("h00"), _T_989) @[Parameters.scala 132:31] + node _T_992 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_993 = cvt(_T_992) @[Parameters.scala 117:49] + node _T_995 = and(_T_993, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_996 = asSInt(_T_995) @[Parameters.scala 117:52] + node _T_998 = eq(_T_996, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1000 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1001 = cvt(_T_1000) @[Parameters.scala 117:49] + node _T_1003 = and(_T_1001, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1004 = asSInt(_T_1003) @[Parameters.scala 117:52] + node _T_1006 = eq(_T_1004, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1008 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1009 = cvt(_T_1008) @[Parameters.scala 117:49] + node _T_1011 = and(_T_1009, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1012 = asSInt(_T_1011) @[Parameters.scala 117:52] + node _T_1014 = eq(_T_1012, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1016 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1017 = cvt(_T_1016) @[Parameters.scala 117:49] + node _T_1019 = and(_T_1017, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1020 = asSInt(_T_1019) @[Parameters.scala 117:52] + node _T_1022 = eq(_T_1020, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1025 = cvt(_T_1024) @[Parameters.scala 117:49] + node _T_1027 = and(_T_1025, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1028 = asSInt(_T_1027) @[Parameters.scala 117:52] + node _T_1030 = eq(_T_1028, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1031 = or(_T_998, _T_1006) @[Parameters.scala 133:42] + node _T_1032 = or(_T_1031, _T_1014) @[Parameters.scala 133:42] + node _T_1033 = or(_T_1032, _T_1022) @[Parameters.scala 133:42] + node _T_1034 = or(_T_1033, _T_1030) @[Parameters.scala 133:42] + node _T_1035 = and(_T_990, _T_1034) @[Parameters.scala 132:56] + node _T_1038 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1040 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1041 = and(_T_1038, _T_1040) @[Parameters.scala 63:37] + node _T_1042 = or(UInt<1>("h00"), _T_1041) @[Parameters.scala 132:31] + node _T_1044 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1045 = cvt(_T_1044) @[Parameters.scala 117:49] + node _T_1047 = and(_T_1045, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1048 = asSInt(_T_1047) @[Parameters.scala 117:52] + node _T_1050 = eq(_T_1048, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1051 = and(_T_1042, _T_1050) @[Parameters.scala 132:56] + node _T_1054 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1056 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1057 = cvt(_T_1056) @[Parameters.scala 117:49] + node _T_1059 = and(_T_1057, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1060 = asSInt(_T_1059) @[Parameters.scala 117:52] + node _T_1062 = eq(_T_1060, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1063 = and(_T_1054, _T_1062) @[Parameters.scala 132:56] + node _T_1065 = or(UInt<1>("h00"), _T_1035) @[Parameters.scala 134:30] + node _T_1066 = or(_T_1065, _T_1051) @[Parameters.scala 134:30] + node _T_1067 = or(_T_1066, _T_1063) @[Parameters.scala 134:30] + node _T_1068 = or(_T_1067, reset) @[Frontend.scala 165:14] + node _T_1070 = eq(_T_1068, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1070 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1071 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_1073 = eq(_T_1071, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1073 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1074 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1076 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1078 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1079 = or(_T_1078, reset) @[Frontend.scala 165:14] + node _T_1081 = eq(_T_1079, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1081 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1082 = not(_T_692) @[Frontend.scala 165:14] + node _T_1083 = and(io.in[0].a.bits.mask, _T_1082) @[Frontend.scala 165:14] + node _T_1085 = eq(_T_1083, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1086 = or(_T_1085, reset) @[Frontend.scala 165:14] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1088 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1090 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[Frontend.scala 165:14] + when _T_1090 : @[Frontend.scala 165:14] + node _T_1093 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1095 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1096 = and(_T_1093, _T_1095) @[Parameters.scala 63:37] + node _T_1097 = or(UInt<1>("h00"), _T_1096) @[Parameters.scala 132:31] + node _T_1099 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1100 = cvt(_T_1099) @[Parameters.scala 117:49] + node _T_1102 = and(_T_1100, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1103 = asSInt(_T_1102) @[Parameters.scala 117:52] + node _T_1105 = eq(_T_1103, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1107 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1108 = cvt(_T_1107) @[Parameters.scala 117:49] + node _T_1110 = and(_T_1108, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1111 = asSInt(_T_1110) @[Parameters.scala 117:52] + node _T_1113 = eq(_T_1111, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1115 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1116 = cvt(_T_1115) @[Parameters.scala 117:49] + node _T_1118 = and(_T_1116, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1119 = asSInt(_T_1118) @[Parameters.scala 117:52] + node _T_1121 = eq(_T_1119, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1122 = or(_T_1105, _T_1113) @[Parameters.scala 133:42] + node _T_1123 = or(_T_1122, _T_1121) @[Parameters.scala 133:42] + node _T_1124 = and(_T_1097, _T_1123) @[Parameters.scala 132:56] + node _T_1127 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1129 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1130 = cvt(_T_1129) @[Parameters.scala 117:49] + node _T_1132 = and(_T_1130, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1133 = asSInt(_T_1132) @[Parameters.scala 117:52] + node _T_1135 = eq(_T_1133, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1137 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1138 = cvt(_T_1137) @[Parameters.scala 117:49] + node _T_1140 = and(_T_1138, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1141 = asSInt(_T_1140) @[Parameters.scala 117:52] + node _T_1143 = eq(_T_1141, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1145 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1146 = cvt(_T_1145) @[Parameters.scala 117:49] + node _T_1148 = and(_T_1146, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1149 = asSInt(_T_1148) @[Parameters.scala 117:52] + node _T_1151 = eq(_T_1149, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1153 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1154 = cvt(_T_1153) @[Parameters.scala 117:49] + node _T_1156 = and(_T_1154, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1157 = asSInt(_T_1156) @[Parameters.scala 117:52] + node _T_1159 = eq(_T_1157, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1160 = or(_T_1135, _T_1143) @[Parameters.scala 133:42] + node _T_1161 = or(_T_1160, _T_1151) @[Parameters.scala 133:42] + node _T_1162 = or(_T_1161, _T_1159) @[Parameters.scala 133:42] + node _T_1163 = and(_T_1127, _T_1162) @[Parameters.scala 132:56] + node _T_1165 = or(UInt<1>("h00"), _T_1124) @[Parameters.scala 134:30] + node _T_1166 = or(_T_1165, _T_1163) @[Parameters.scala 134:30] + node _T_1167 = or(_T_1166, reset) @[Frontend.scala 165:14] + node _T_1169 = eq(_T_1167, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1169 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1170 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_1172 = eq(_T_1170, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1172 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1173 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1175 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1177 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1178 = or(_T_1177, reset) @[Frontend.scala 165:14] + node _T_1180 = eq(_T_1178, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1180 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Frontend.scala:165:14)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1181 = eq(io.in[0].a.bits.mask, _T_692) @[Frontend.scala 165:14] + node _T_1182 = or(_T_1181, reset) @[Frontend.scala 165:14] + node _T_1184 = eq(_T_1182, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1184 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1186 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[Frontend.scala 165:14] + when _T_1186 : @[Frontend.scala 165:14] + node _T_1189 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1191 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1192 = and(_T_1189, _T_1191) @[Parameters.scala 63:37] + node _T_1193 = or(UInt<1>("h00"), _T_1192) @[Parameters.scala 132:31] + node _T_1195 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1196 = cvt(_T_1195) @[Parameters.scala 117:49] + node _T_1198 = and(_T_1196, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1199 = asSInt(_T_1198) @[Parameters.scala 117:52] + node _T_1201 = eq(_T_1199, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1203 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1204 = cvt(_T_1203) @[Parameters.scala 117:49] + node _T_1206 = and(_T_1204, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1207 = asSInt(_T_1206) @[Parameters.scala 117:52] + node _T_1209 = eq(_T_1207, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1211 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1212 = cvt(_T_1211) @[Parameters.scala 117:49] + node _T_1214 = and(_T_1212, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1215 = asSInt(_T_1214) @[Parameters.scala 117:52] + node _T_1217 = eq(_T_1215, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1218 = or(_T_1201, _T_1209) @[Parameters.scala 133:42] + node _T_1219 = or(_T_1218, _T_1217) @[Parameters.scala 133:42] + node _T_1220 = and(_T_1193, _T_1219) @[Parameters.scala 132:56] + node _T_1223 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1225 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1226 = cvt(_T_1225) @[Parameters.scala 117:49] + node _T_1228 = and(_T_1226, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1229 = asSInt(_T_1228) @[Parameters.scala 117:52] + node _T_1231 = eq(_T_1229, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1233 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1234 = cvt(_T_1233) @[Parameters.scala 117:49] + node _T_1236 = and(_T_1234, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1237 = asSInt(_T_1236) @[Parameters.scala 117:52] + node _T_1239 = eq(_T_1237, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1241 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1242 = cvt(_T_1241) @[Parameters.scala 117:49] + node _T_1244 = and(_T_1242, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1245 = asSInt(_T_1244) @[Parameters.scala 117:52] + node _T_1247 = eq(_T_1245, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1249 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1250 = cvt(_T_1249) @[Parameters.scala 117:49] + node _T_1252 = and(_T_1250, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1253 = asSInt(_T_1252) @[Parameters.scala 117:52] + node _T_1255 = eq(_T_1253, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1256 = or(_T_1231, _T_1239) @[Parameters.scala 133:42] + node _T_1257 = or(_T_1256, _T_1247) @[Parameters.scala 133:42] + node _T_1258 = or(_T_1257, _T_1255) @[Parameters.scala 133:42] + node _T_1259 = and(_T_1223, _T_1258) @[Parameters.scala 132:56] + node _T_1261 = or(UInt<1>("h00"), _T_1220) @[Parameters.scala 134:30] + node _T_1262 = or(_T_1261, _T_1259) @[Parameters.scala 134:30] + node _T_1263 = or(_T_1262, reset) @[Frontend.scala 165:14] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1265 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1266 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_1268 = eq(_T_1266, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1268 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1269 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1271 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1273 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1274 = or(_T_1273, reset) @[Frontend.scala 165:14] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1276 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Frontend.scala:165:14)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1277 = eq(io.in[0].a.bits.mask, _T_692) @[Frontend.scala 165:14] + node _T_1278 = or(_T_1277, reset) @[Frontend.scala 165:14] + node _T_1280 = eq(_T_1278, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1280 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1282 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[Frontend.scala 165:14] + when _T_1282 : @[Frontend.scala 165:14] + node _T_1285 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1287 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1288 = cvt(_T_1287) @[Parameters.scala 117:49] + node _T_1290 = and(_T_1288, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1291 = asSInt(_T_1290) @[Parameters.scala 117:52] + node _T_1293 = eq(_T_1291, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1295 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1296 = cvt(_T_1295) @[Parameters.scala 117:49] + node _T_1298 = and(_T_1296, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1299 = asSInt(_T_1298) @[Parameters.scala 117:52] + node _T_1301 = eq(_T_1299, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1303 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1304 = cvt(_T_1303) @[Parameters.scala 117:49] + node _T_1306 = and(_T_1304, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1307 = asSInt(_T_1306) @[Parameters.scala 117:52] + node _T_1309 = eq(_T_1307, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1311 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1312 = cvt(_T_1311) @[Parameters.scala 117:49] + node _T_1314 = and(_T_1312, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1315 = asSInt(_T_1314) @[Parameters.scala 117:52] + node _T_1317 = eq(_T_1315, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1319 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1320 = cvt(_T_1319) @[Parameters.scala 117:49] + node _T_1322 = and(_T_1320, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1323 = asSInt(_T_1322) @[Parameters.scala 117:52] + node _T_1325 = eq(_T_1323, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1327 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1328 = cvt(_T_1327) @[Parameters.scala 117:49] + node _T_1330 = and(_T_1328, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1331 = asSInt(_T_1330) @[Parameters.scala 117:52] + node _T_1333 = eq(_T_1331, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1334 = or(_T_1293, _T_1301) @[Parameters.scala 133:42] + node _T_1335 = or(_T_1334, _T_1309) @[Parameters.scala 133:42] + node _T_1336 = or(_T_1335, _T_1317) @[Parameters.scala 133:42] + node _T_1337 = or(_T_1336, _T_1325) @[Parameters.scala 133:42] + node _T_1338 = or(_T_1337, _T_1333) @[Parameters.scala 133:42] + node _T_1339 = and(_T_1285, _T_1338) @[Parameters.scala 132:56] + node _T_1341 = or(UInt<1>("h00"), _T_1339) @[Parameters.scala 134:30] + node _T_1342 = or(_T_1341, reset) @[Frontend.scala 165:14] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1344 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1345 = or(_T_613[0], reset) @[Frontend.scala 165:14] + node _T_1347 = eq(_T_1345, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1347 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1348 = or(_T_624, reset) @[Frontend.scala 165:14] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1350 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1351 = eq(io.in[0].a.bits.mask, _T_692) @[Frontend.scala 165:14] + node _T_1352 = or(_T_1351, reset) @[Frontend.scala 165:14] + node _T_1354 = eq(_T_1352, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1354 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + when io.in[0].b.valid : @[Frontend.scala 165:14] + node _T_1356 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1357 = or(_T_1356, reset) @[Frontend.scala 165:14] + node _T_1359 = eq(_T_1357, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1359 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at Frontend.scala:165:14)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1361 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1362 = cvt(_T_1361) @[Parameters.scala 117:49] + node _T_1364 = and(_T_1362, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1365 = asSInt(_T_1364) @[Parameters.scala 117:52] + node _T_1367 = eq(_T_1365, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1369 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1370 = cvt(_T_1369) @[Parameters.scala 117:49] + node _T_1372 = and(_T_1370, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1373 = asSInt(_T_1372) @[Parameters.scala 117:52] + node _T_1375 = eq(_T_1373, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1377 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1378 = cvt(_T_1377) @[Parameters.scala 117:49] + node _T_1380 = and(_T_1378, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1381 = asSInt(_T_1380) @[Parameters.scala 117:52] + node _T_1383 = eq(_T_1381, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1385 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1386 = cvt(_T_1385) @[Parameters.scala 117:49] + node _T_1388 = and(_T_1386, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1389 = asSInt(_T_1388) @[Parameters.scala 117:52] + node _T_1391 = eq(_T_1389, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1393 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1401 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1402 = cvt(_T_1401) @[Parameters.scala 117:49] + node _T_1404 = and(_T_1402, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1405 = asSInt(_T_1404) @[Parameters.scala 117:52] + node _T_1407 = eq(_T_1405, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1409 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1410 = cvt(_T_1409) @[Parameters.scala 117:49] + node _T_1412 = and(_T_1410, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1413 = asSInt(_T_1412) @[Parameters.scala 117:52] + node _T_1415 = eq(_T_1413, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1418 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1418 is invalid @[Parameters.scala 110:36] + _T_1418[0] <= _T_1367 @[Parameters.scala 110:36] + _T_1418[1] <= _T_1375 @[Parameters.scala 110:36] + _T_1418[2] <= _T_1383 @[Parameters.scala 110:36] + _T_1418[3] <= _T_1391 @[Parameters.scala 110:36] + _T_1418[4] <= _T_1399 @[Parameters.scala 110:36] + _T_1418[5] <= _T_1407 @[Parameters.scala 110:36] + _T_1418[6] <= _T_1415 @[Parameters.scala 110:36] + node _T_1428 = or(_T_1418[0], _T_1418[1]) @[Parameters.scala 119:64] + node _T_1429 = or(_T_1428, _T_1418[2]) @[Parameters.scala 119:64] + node _T_1430 = or(_T_1429, _T_1418[3]) @[Parameters.scala 119:64] + node _T_1431 = or(_T_1430, _T_1418[4]) @[Parameters.scala 119:64] + node _T_1432 = or(_T_1431, _T_1418[5]) @[Parameters.scala 119:64] + node _T_1433 = or(_T_1432, _T_1418[6]) @[Parameters.scala 119:64] + node _T_1435 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1436 = dshl(_T_1435, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1437 = bits(_T_1436, 7, 0) @[package.scala 19:76] + node _T_1438 = not(_T_1437) @[package.scala 19:40] + node _T_1439 = and(io.in[0].b.bits.address, _T_1438) @[Edges.scala 17:16] + node _T_1441 = eq(_T_1439, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1443 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1444 = dshl(UInt<1>("h01"), _T_1443) @[OneHot.scala 49:12] + node _T_1445 = bits(_T_1444, 2, 0) @[OneHot.scala 49:37] + node _T_1447 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1449 = bits(_T_1445, 2, 2) @[package.scala 44:26] + node _T_1450 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1452 = eq(_T_1450, UInt<1>("h00")) @[package.scala 46:20] + node _T_1453 = and(UInt<1>("h01"), _T_1452) @[package.scala 49:27] + node _T_1454 = and(_T_1449, _T_1453) @[package.scala 50:38] + node _T_1455 = or(_T_1447, _T_1454) @[package.scala 50:29] + node _T_1456 = and(UInt<1>("h01"), _T_1450) @[package.scala 49:27] + node _T_1457 = and(_T_1449, _T_1456) @[package.scala 50:38] + node _T_1458 = or(_T_1447, _T_1457) @[package.scala 50:29] + node _T_1459 = bits(_T_1445, 1, 1) @[package.scala 44:26] + node _T_1460 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1462 = eq(_T_1460, UInt<1>("h00")) @[package.scala 46:20] + node _T_1463 = and(_T_1453, _T_1462) @[package.scala 49:27] + node _T_1464 = and(_T_1459, _T_1463) @[package.scala 50:38] + node _T_1465 = or(_T_1455, _T_1464) @[package.scala 50:29] + node _T_1466 = and(_T_1453, _T_1460) @[package.scala 49:27] + node _T_1467 = and(_T_1459, _T_1466) @[package.scala 50:38] + node _T_1468 = or(_T_1455, _T_1467) @[package.scala 50:29] + node _T_1469 = and(_T_1456, _T_1462) @[package.scala 49:27] + node _T_1470 = and(_T_1459, _T_1469) @[package.scala 50:38] + node _T_1471 = or(_T_1458, _T_1470) @[package.scala 50:29] + node _T_1472 = and(_T_1456, _T_1460) @[package.scala 49:27] + node _T_1473 = and(_T_1459, _T_1472) @[package.scala 50:38] + node _T_1474 = or(_T_1458, _T_1473) @[package.scala 50:29] + node _T_1475 = bits(_T_1445, 0, 0) @[package.scala 44:26] + node _T_1476 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1478 = eq(_T_1476, UInt<1>("h00")) @[package.scala 46:20] + node _T_1479 = and(_T_1463, _T_1478) @[package.scala 49:27] + node _T_1480 = and(_T_1475, _T_1479) @[package.scala 50:38] + node _T_1481 = or(_T_1465, _T_1480) @[package.scala 50:29] + node _T_1482 = and(_T_1463, _T_1476) @[package.scala 49:27] + node _T_1483 = and(_T_1475, _T_1482) @[package.scala 50:38] + node _T_1484 = or(_T_1465, _T_1483) @[package.scala 50:29] + node _T_1485 = and(_T_1466, _T_1478) @[package.scala 49:27] + node _T_1486 = and(_T_1475, _T_1485) @[package.scala 50:38] + node _T_1487 = or(_T_1468, _T_1486) @[package.scala 50:29] + node _T_1488 = and(_T_1466, _T_1476) @[package.scala 49:27] + node _T_1489 = and(_T_1475, _T_1488) @[package.scala 50:38] + node _T_1490 = or(_T_1468, _T_1489) @[package.scala 50:29] + node _T_1491 = and(_T_1469, _T_1478) @[package.scala 49:27] + node _T_1492 = and(_T_1475, _T_1491) @[package.scala 50:38] + node _T_1493 = or(_T_1471, _T_1492) @[package.scala 50:29] + node _T_1494 = and(_T_1469, _T_1476) @[package.scala 49:27] + node _T_1495 = and(_T_1475, _T_1494) @[package.scala 50:38] + node _T_1496 = or(_T_1471, _T_1495) @[package.scala 50:29] + node _T_1497 = and(_T_1472, _T_1478) @[package.scala 49:27] + node _T_1498 = and(_T_1475, _T_1497) @[package.scala 50:38] + node _T_1499 = or(_T_1474, _T_1498) @[package.scala 50:29] + node _T_1500 = and(_T_1472, _T_1476) @[package.scala 49:27] + node _T_1501 = and(_T_1475, _T_1500) @[package.scala 50:38] + node _T_1502 = or(_T_1474, _T_1501) @[package.scala 50:29] + node _T_1503 = cat(_T_1484, _T_1481) @[Cat.scala 30:58] + node _T_1504 = cat(_T_1490, _T_1487) @[Cat.scala 30:58] + node _T_1505 = cat(_T_1504, _T_1503) @[Cat.scala 30:58] + node _T_1506 = cat(_T_1496, _T_1493) @[Cat.scala 30:58] + node _T_1507 = cat(_T_1502, _T_1499) @[Cat.scala 30:58] + node _T_1508 = cat(_T_1507, _T_1506) @[Cat.scala 30:58] + node _T_1509 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1511 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + when _T_1511 : @[Frontend.scala 165:14] + node _T_1513 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1515 = eq(_T_1513, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1515 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1516 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1518 = eq(_T_1516, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1518 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1520 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_1521 = or(_T_1520, reset) @[Frontend.scala 165:14] + node _T_1523 = eq(_T_1521, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1523 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1524 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1526 = eq(_T_1524, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1526 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1528 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1529 = or(_T_1528, reset) @[Frontend.scala 165:14] + node _T_1531 = eq(_T_1529, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1531 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at Frontend.scala:165:14)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1532 = not(io.in[0].b.bits.mask) @[Frontend.scala 165:14] + node _T_1534 = eq(_T_1532, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1535 = or(_T_1534, reset) @[Frontend.scala 165:14] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1537 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1539 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[Frontend.scala 165:14] + when _T_1539 : @[Frontend.scala 165:14] + node _T_1541 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1543 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1544 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1546 = eq(_T_1544, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1546 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1547 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1549 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1551 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1552 = or(_T_1551, reset) @[Frontend.scala 165:14] + node _T_1554 = eq(_T_1552, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1554 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1555 = eq(io.in[0].b.bits.mask, _T_1509) @[Frontend.scala 165:14] + node _T_1556 = or(_T_1555, reset) @[Frontend.scala 165:14] + node _T_1558 = eq(_T_1556, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1558 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1560 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1560 : @[Frontend.scala 165:14] + node _T_1562 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1564 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1565 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1567 = eq(_T_1565, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1567 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1568 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1570 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1572 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1573 = or(_T_1572, reset) @[Frontend.scala 165:14] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1575 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1576 = eq(io.in[0].b.bits.mask, _T_1509) @[Frontend.scala 165:14] + node _T_1577 = or(_T_1576, reset) @[Frontend.scala 165:14] + node _T_1579 = eq(_T_1577, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1579 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1581 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[Frontend.scala 165:14] + when _T_1581 : @[Frontend.scala 165:14] + node _T_1583 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1585 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1586 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1588 = eq(_T_1586, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1588 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1589 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1591 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1593 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1594 = or(_T_1593, reset) @[Frontend.scala 165:14] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1596 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1597 = not(_T_1509) @[Frontend.scala 165:14] + node _T_1598 = and(io.in[0].b.bits.mask, _T_1597) @[Frontend.scala 165:14] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1601 = or(_T_1600, reset) @[Frontend.scala 165:14] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1603 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1605 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[Frontend.scala 165:14] + when _T_1605 : @[Frontend.scala 165:14] + node _T_1607 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1609 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1610 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1612 = eq(_T_1610, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1612 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1613 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1615 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1617 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1618 = or(_T_1617, reset) @[Frontend.scala 165:14] + node _T_1620 = eq(_T_1618, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1620 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at Frontend.scala:165:14)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1621 = eq(io.in[0].b.bits.mask, _T_1509) @[Frontend.scala 165:14] + node _T_1622 = or(_T_1621, reset) @[Frontend.scala 165:14] + node _T_1624 = eq(_T_1622, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1624 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1626 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[Frontend.scala 165:14] + when _T_1626 : @[Frontend.scala 165:14] + node _T_1628 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1630 = eq(_T_1628, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1630 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1631 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1633 = eq(_T_1631, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1633 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1634 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1636 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1638 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1639 = or(_T_1638, reset) @[Frontend.scala 165:14] + node _T_1641 = eq(_T_1639, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1641 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at Frontend.scala:165:14)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1642 = eq(io.in[0].b.bits.mask, _T_1509) @[Frontend.scala 165:14] + node _T_1643 = or(_T_1642, reset) @[Frontend.scala 165:14] + node _T_1645 = eq(_T_1643, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1645 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1647 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[Frontend.scala 165:14] + when _T_1647 : @[Frontend.scala 165:14] + node _T_1649 = or(UInt<1>("h00"), reset) @[Frontend.scala 165:14] + node _T_1651 = eq(_T_1649, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1651 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at Frontend.scala:165:14)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1652 = or(_T_1433, reset) @[Frontend.scala 165:14] + node _T_1654 = eq(_T_1652, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1654 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1655 = or(_T_1441, reset) @[Frontend.scala 165:14] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1657 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1658 = eq(io.in[0].b.bits.mask, _T_1509) @[Frontend.scala 165:14] + node _T_1659 = or(_T_1658, reset) @[Frontend.scala 165:14] + node _T_1661 = eq(_T_1659, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1661 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at Frontend.scala:165:14)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + when io.in[0].c.valid : @[Frontend.scala 165:14] + node _T_1663 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1664 = or(_T_1663, reset) @[Frontend.scala 165:14] + node _T_1666 = eq(_T_1664, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1666 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at Frontend.scala:165:14)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1668 = eq(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1671 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1671 is invalid @[Parameters.scala 228:27] + _T_1671[0] <= _T_1668 @[Parameters.scala 228:27] + node _T_1676 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1677 = dshl(_T_1676, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1678 = bits(_T_1677, 7, 0) @[package.scala 19:76] + node _T_1679 = not(_T_1678) @[package.scala 19:40] + node _T_1680 = and(io.in[0].c.bits.address, _T_1679) @[Edges.scala 17:16] + node _T_1682 = eq(_T_1680, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1684 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1685 = cvt(_T_1684) @[Parameters.scala 117:49] + node _T_1687 = and(_T_1685, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1688 = asSInt(_T_1687) @[Parameters.scala 117:52] + node _T_1690 = eq(_T_1688, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1692 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1693 = cvt(_T_1692) @[Parameters.scala 117:49] + node _T_1695 = and(_T_1693, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1696 = asSInt(_T_1695) @[Parameters.scala 117:52] + node _T_1698 = eq(_T_1696, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1700 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1701 = cvt(_T_1700) @[Parameters.scala 117:49] + node _T_1703 = and(_T_1701, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1704 = asSInt(_T_1703) @[Parameters.scala 117:52] + node _T_1706 = eq(_T_1704, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1708 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1709 = cvt(_T_1708) @[Parameters.scala 117:49] + node _T_1711 = and(_T_1709, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1712 = asSInt(_T_1711) @[Parameters.scala 117:52] + node _T_1714 = eq(_T_1712, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1716 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1717 = cvt(_T_1716) @[Parameters.scala 117:49] + node _T_1719 = and(_T_1717, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1720 = asSInt(_T_1719) @[Parameters.scala 117:52] + node _T_1722 = eq(_T_1720, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1724 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1725 = cvt(_T_1724) @[Parameters.scala 117:49] + node _T_1727 = and(_T_1725, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1728 = asSInt(_T_1727) @[Parameters.scala 117:52] + node _T_1730 = eq(_T_1728, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1732 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1733 = cvt(_T_1732) @[Parameters.scala 117:49] + node _T_1735 = and(_T_1733, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1736 = asSInt(_T_1735) @[Parameters.scala 117:52] + node _T_1738 = eq(_T_1736, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1741 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1741 is invalid @[Parameters.scala 110:36] + _T_1741[0] <= _T_1690 @[Parameters.scala 110:36] + _T_1741[1] <= _T_1698 @[Parameters.scala 110:36] + _T_1741[2] <= _T_1706 @[Parameters.scala 110:36] + _T_1741[3] <= _T_1714 @[Parameters.scala 110:36] + _T_1741[4] <= _T_1722 @[Parameters.scala 110:36] + _T_1741[5] <= _T_1730 @[Parameters.scala 110:36] + _T_1741[6] <= _T_1738 @[Parameters.scala 110:36] + node _T_1751 = or(_T_1741[0], _T_1741[1]) @[Parameters.scala 119:64] + node _T_1752 = or(_T_1751, _T_1741[2]) @[Parameters.scala 119:64] + node _T_1753 = or(_T_1752, _T_1741[3]) @[Parameters.scala 119:64] + node _T_1754 = or(_T_1753, _T_1741[4]) @[Parameters.scala 119:64] + node _T_1755 = or(_T_1754, _T_1741[5]) @[Parameters.scala 119:64] + node _T_1756 = or(_T_1755, _T_1741[6]) @[Parameters.scala 119:64] + node _T_1758 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[Frontend.scala 165:14] + when _T_1758 : @[Frontend.scala 165:14] + node _T_1759 = or(_T_1756, reset) @[Frontend.scala 165:14] + node _T_1761 = eq(_T_1759, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1761 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1762 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1764 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1766 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_1767 = or(_T_1766, reset) @[Frontend.scala 165:14] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1769 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1770 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_1772 = eq(_T_1770, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1772 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1774 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1775 = or(_T_1774, reset) @[Frontend.scala 165:14] + node _T_1777 = eq(_T_1775, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1777 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at Frontend.scala:165:14)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1779 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1780 = or(_T_1779, reset) @[Frontend.scala 165:14] + node _T_1782 = eq(_T_1780, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1782 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1784 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[Frontend.scala 165:14] + when _T_1784 : @[Frontend.scala 165:14] + node _T_1785 = or(_T_1756, reset) @[Frontend.scala 165:14] + node _T_1787 = eq(_T_1785, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1787 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1788 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_1790 = eq(_T_1788, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1790 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1792 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_1793 = or(_T_1792, reset) @[Frontend.scala 165:14] + node _T_1795 = eq(_T_1793, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1795 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1796 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_1798 = eq(_T_1796, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1798 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1800 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1801 = or(_T_1800, reset) @[Frontend.scala 165:14] + node _T_1803 = eq(_T_1801, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1803 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at Frontend.scala:165:14)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1805 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1806 = or(_T_1805, reset) @[Frontend.scala 165:14] + node _T_1808 = eq(_T_1806, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1808 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1810 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + when _T_1810 : @[Frontend.scala 165:14] + node _T_1813 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1815 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1816 = and(_T_1813, _T_1815) @[Parameters.scala 63:37] + node _T_1817 = or(UInt<1>("h00"), _T_1816) @[Parameters.scala 132:31] + node _T_1819 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1820 = cvt(_T_1819) @[Parameters.scala 117:49] + node _T_1822 = and(_T_1820, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1823 = asSInt(_T_1822) @[Parameters.scala 117:52] + node _T_1825 = eq(_T_1823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1827 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1828 = cvt(_T_1827) @[Parameters.scala 117:49] + node _T_1830 = and(_T_1828, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1831 = asSInt(_T_1830) @[Parameters.scala 117:52] + node _T_1833 = eq(_T_1831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1834 = or(_T_1825, _T_1833) @[Parameters.scala 133:42] + node _T_1835 = and(_T_1817, _T_1834) @[Parameters.scala 132:56] + node _T_1838 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1840 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1841 = cvt(_T_1840) @[Parameters.scala 117:49] + node _T_1843 = and(_T_1841, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1844 = asSInt(_T_1843) @[Parameters.scala 117:52] + node _T_1846 = eq(_T_1844, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1848 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1849 = cvt(_T_1848) @[Parameters.scala 117:49] + node _T_1851 = and(_T_1849, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1852 = asSInt(_T_1851) @[Parameters.scala 117:52] + node _T_1854 = eq(_T_1852, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1856 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1857 = cvt(_T_1856) @[Parameters.scala 117:49] + node _T_1859 = and(_T_1857, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1860 = asSInt(_T_1859) @[Parameters.scala 117:52] + node _T_1862 = eq(_T_1860, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1864 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1865 = cvt(_T_1864) @[Parameters.scala 117:49] + node _T_1867 = and(_T_1865, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1868 = asSInt(_T_1867) @[Parameters.scala 117:52] + node _T_1870 = eq(_T_1868, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1871 = or(_T_1846, _T_1854) @[Parameters.scala 133:42] + node _T_1872 = or(_T_1871, _T_1862) @[Parameters.scala 133:42] + node _T_1873 = or(_T_1872, _T_1870) @[Parameters.scala 133:42] + node _T_1874 = and(_T_1838, _T_1873) @[Parameters.scala 132:56] + node _T_1876 = or(UInt<1>("h00"), _T_1835) @[Parameters.scala 134:30] + node _T_1877 = or(_T_1876, _T_1874) @[Parameters.scala 134:30] + node _T_1878 = or(_T_1877, reset) @[Frontend.scala 165:14] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1880 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1881 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_1883 = eq(_T_1881, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1883 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1885 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_1886 = or(_T_1885, reset) @[Frontend.scala 165:14] + node _T_1888 = eq(_T_1886, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1888 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1889 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_1891 = eq(_T_1889, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1891 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1893 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1894 = or(_T_1893, reset) @[Frontend.scala 165:14] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1896 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at Frontend.scala:165:14)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1898 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1899 = or(_T_1898, reset) @[Frontend.scala 165:14] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1901 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1903 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Frontend.scala 165:14] + when _T_1903 : @[Frontend.scala 165:14] + node _T_1906 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1908 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1909 = and(_T_1906, _T_1908) @[Parameters.scala 63:37] + node _T_1910 = or(UInt<1>("h00"), _T_1909) @[Parameters.scala 132:31] + node _T_1912 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1913 = cvt(_T_1912) @[Parameters.scala 117:49] + node _T_1915 = and(_T_1913, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1916 = asSInt(_T_1915) @[Parameters.scala 117:52] + node _T_1918 = eq(_T_1916, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1920 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1921 = cvt(_T_1920) @[Parameters.scala 117:49] + node _T_1923 = and(_T_1921, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1924 = asSInt(_T_1923) @[Parameters.scala 117:52] + node _T_1926 = eq(_T_1924, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1927 = or(_T_1918, _T_1926) @[Parameters.scala 133:42] + node _T_1928 = and(_T_1910, _T_1927) @[Parameters.scala 132:56] + node _T_1931 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1933 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1934 = cvt(_T_1933) @[Parameters.scala 117:49] + node _T_1936 = and(_T_1934, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1937 = asSInt(_T_1936) @[Parameters.scala 117:52] + node _T_1939 = eq(_T_1937, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1941 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1942 = cvt(_T_1941) @[Parameters.scala 117:49] + node _T_1944 = and(_T_1942, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1945 = asSInt(_T_1944) @[Parameters.scala 117:52] + node _T_1947 = eq(_T_1945, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1949 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1950 = cvt(_T_1949) @[Parameters.scala 117:49] + node _T_1952 = and(_T_1950, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1953 = asSInt(_T_1952) @[Parameters.scala 117:52] + node _T_1955 = eq(_T_1953, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1957 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1958 = cvt(_T_1957) @[Parameters.scala 117:49] + node _T_1960 = and(_T_1958, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1961 = asSInt(_T_1960) @[Parameters.scala 117:52] + node _T_1963 = eq(_T_1961, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1964 = or(_T_1939, _T_1947) @[Parameters.scala 133:42] + node _T_1965 = or(_T_1964, _T_1955) @[Parameters.scala 133:42] + node _T_1966 = or(_T_1965, _T_1963) @[Parameters.scala 133:42] + node _T_1967 = and(_T_1931, _T_1966) @[Parameters.scala 132:56] + node _T_1969 = or(UInt<1>("h00"), _T_1928) @[Parameters.scala 134:30] + node _T_1970 = or(_T_1969, _T_1967) @[Parameters.scala 134:30] + node _T_1971 = or(_T_1970, reset) @[Frontend.scala 165:14] + node _T_1973 = eq(_T_1971, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1973 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at Frontend.scala:165:14)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1974 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_1976 = eq(_T_1974, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1976 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1978 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_1979 = or(_T_1978, reset) @[Frontend.scala 165:14] + node _T_1981 = eq(_T_1979, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1981 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1982 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_1984 = eq(_T_1982, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1984 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1986 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1987 = or(_T_1986, reset) @[Frontend.scala 165:14] + node _T_1989 = eq(_T_1987, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1989 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at Frontend.scala:165:14)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1991 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_1992 = or(_T_1991, reset) @[Frontend.scala 165:14] + node _T_1994 = eq(_T_1992, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1994 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_1996 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1996 : @[Frontend.scala 165:14] + node _T_1997 = or(_T_1756, reset) @[Frontend.scala 165:14] + node _T_1999 = eq(_T_1997, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_1999 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2000 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_2002 = eq(_T_2000, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2002 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2003 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_2005 = eq(_T_2003, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2005 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2007 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2008 = or(_T_2007, reset) @[Frontend.scala 165:14] + node _T_2010 = eq(_T_2008, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2010 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2012 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[Frontend.scala 165:14] + when _T_2012 : @[Frontend.scala 165:14] + node _T_2013 = or(_T_1756, reset) @[Frontend.scala 165:14] + node _T_2015 = eq(_T_2013, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2015 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2016 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_2018 = eq(_T_2016, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2018 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2019 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2021 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2023 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2024 = or(_T_2023, reset) @[Frontend.scala 165:14] + node _T_2026 = eq(_T_2024, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2026 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2028 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[Frontend.scala 165:14] + when _T_2028 : @[Frontend.scala 165:14] + node _T_2029 = or(_T_1756, reset) @[Frontend.scala 165:14] + node _T_2031 = eq(_T_2029, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2031 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at Frontend.scala:165:14)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2032 = or(_T_1671[0], reset) @[Frontend.scala 165:14] + node _T_2034 = eq(_T_2032, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2034 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2035 = or(_T_1682, reset) @[Frontend.scala 165:14] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2037 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2039 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2040 = or(_T_2039, reset) @[Frontend.scala 165:14] + node _T_2042 = eq(_T_2040, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2042 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2044 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2045 = or(_T_2044, reset) @[Frontend.scala 165:14] + node _T_2047 = eq(_T_2045, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2047 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + when io.in[0].d.valid : @[Frontend.scala 165:14] + node _T_2049 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2050 = or(_T_2049, reset) @[Frontend.scala 165:14] + node _T_2052 = eq(_T_2050, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2052 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at Frontend.scala:165:14)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2054 = eq(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_2057 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2057 is invalid @[Parameters.scala 228:27] + _T_2057[0] <= _T_2054 @[Parameters.scala 228:27] + node _T_2062 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2063 = dshl(_T_2062, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2064 = bits(_T_2063, 7, 0) @[package.scala 19:76] + node _T_2065 = not(_T_2064) @[package.scala 19:40] + node _T_2066 = and(io.in[0].d.bits.addr_lo, _T_2065) @[Edges.scala 17:16] + node _T_2068 = eq(_T_2066, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2070 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[Frontend.scala 165:14] + node _T_2072 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + when _T_2072 : @[Frontend.scala 165:14] + node _T_2073 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2075 = eq(_T_2073, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2075 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2076 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2078 = eq(_T_2076, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2078 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2079 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2081 = eq(_T_2079, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2081 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2083 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_2084 = or(_T_2083, reset) @[Frontend.scala 165:14] + node _T_2086 = eq(_T_2084, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2086 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2088 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2089 = or(_T_2088, reset) @[Frontend.scala 165:14] + node _T_2091 = eq(_T_2089, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2091 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2093 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2094 = or(_T_2093, reset) @[Frontend.scala 165:14] + node _T_2096 = eq(_T_2094, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2096 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2098 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[Frontend.scala 165:14] + when _T_2098 : @[Frontend.scala 165:14] + node _T_2099 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2101 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2102 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2104 = eq(_T_2102, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2104 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2105 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2107 = eq(_T_2105, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2107 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2109 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_2110 = or(_T_2109, reset) @[Frontend.scala 165:14] + node _T_2112 = eq(_T_2110, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2112 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2114 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2115 = or(_T_2114, reset) @[Frontend.scala 165:14] + node _T_2117 = eq(_T_2115, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2117 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Frontend.scala:165:14)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2119 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[Frontend.scala 165:14] + when _T_2119 : @[Frontend.scala 165:14] + node _T_2120 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2122 = eq(_T_2120, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2122 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2123 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2125 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2126 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2128 = eq(_T_2126, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2128 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2130 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[Frontend.scala 165:14] + node _T_2131 = or(_T_2130, reset) @[Frontend.scala 165:14] + node _T_2133 = eq(_T_2131, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2133 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Frontend.scala:165:14)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2135 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2136 = or(_T_2135, reset) @[Frontend.scala 165:14] + node _T_2138 = eq(_T_2136, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2138 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Frontend.scala:165:14)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2140 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2140 : @[Frontend.scala 165:14] + node _T_2141 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2143 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2144 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2146 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2147 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2149 = eq(_T_2147, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2149 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2151 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2152 = or(_T_2151, reset) @[Frontend.scala 165:14] + node _T_2154 = eq(_T_2152, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2154 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2156 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[Frontend.scala 165:14] + when _T_2156 : @[Frontend.scala 165:14] + node _T_2157 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2159 = eq(_T_2157, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2159 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2160 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2162 = eq(_T_2160, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2162 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2163 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2165 = eq(_T_2163, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2165 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2167 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2168 = or(_T_2167, reset) @[Frontend.scala 165:14] + node _T_2170 = eq(_T_2168, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2170 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2172 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[Frontend.scala 165:14] + when _T_2172 : @[Frontend.scala 165:14] + node _T_2173 = or(_T_2057[0], reset) @[Frontend.scala 165:14] + node _T_2175 = eq(_T_2173, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2175 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2176 = or(_T_2068, reset) @[Frontend.scala 165:14] + node _T_2178 = eq(_T_2176, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2178 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at Frontend.scala:165:14)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2179 = or(_T_2070, reset) @[Frontend.scala 165:14] + node _T_2181 = eq(_T_2179, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2181 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2183 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2184 = or(_T_2183, reset) @[Frontend.scala 165:14] + node _T_2186 = eq(_T_2184, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2186 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at Frontend.scala:165:14)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2188 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2189 = or(_T_2188, reset) @[Frontend.scala 165:14] + node _T_2191 = eq(_T_2189, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2191 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at Frontend.scala:165:14)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + when io.in[0].e.valid : @[Frontend.scala 165:14] + node _T_2193 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[Frontend.scala 165:14] + node _T_2194 = or(_T_2193, reset) @[Frontend.scala 165:14] + node _T_2196 = eq(_T_2194, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2196 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at Frontend.scala:165:14)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2197 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2199 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2200 = dshl(_T_2199, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2201 = bits(_T_2200, 7, 0) @[package.scala 19:76] + node _T_2202 = not(_T_2201) @[package.scala 19:40] + node _T_2203 = shr(_T_2202, 3) @[Edges.scala 198:59] + node _T_2204 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2206 = eq(_T_2204, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2208 = mux(_T_2206, _T_2203, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2210 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2212 = sub(_T_2210, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2213 = asUInt(_T_2212) @[Edges.scala 208:28] + node _T_2214 = tail(_T_2213, 1) @[Edges.scala 208:28] + node _T_2216 = eq(_T_2210, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2218 = eq(_T_2210, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2220 = eq(_T_2208, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2221 = or(_T_2218, _T_2220) @[Edges.scala 210:37] + node _T_2222 = and(_T_2221, _T_2197) @[Edges.scala 211:22] + node _T_2223 = not(_T_2214) @[Edges.scala 212:27] + node _T_2224 = and(_T_2208, _T_2223) @[Edges.scala 212:25] + when _T_2197 : @[Edges.scala 213:17] + node _T_2225 = mux(_T_2216, _T_2208, _T_2214) @[Edges.scala 214:21] + _T_2210 <= _T_2225 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2227 : UInt, clock @[Frontend.scala 165:14] + reg _T_2229 : UInt, clock @[Frontend.scala 165:14] + reg _T_2231 : UInt, clock @[Frontend.scala 165:14] + reg _T_2233 : UInt, clock @[Frontend.scala 165:14] + reg _T_2235 : UInt, clock @[Frontend.scala 165:14] + node _T_2237 = eq(_T_2216, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2238 = and(io.in[0].a.valid, _T_2237) @[Frontend.scala 165:14] + when _T_2238 : @[Frontend.scala 165:14] + node _T_2239 = eq(io.in[0].a.bits.opcode, _T_2227) @[Frontend.scala 165:14] + node _T_2240 = or(_T_2239, reset) @[Frontend.scala 165:14] + node _T_2242 = eq(_T_2240, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2242 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2243 = eq(io.in[0].a.bits.param, _T_2229) @[Frontend.scala 165:14] + node _T_2244 = or(_T_2243, reset) @[Frontend.scala 165:14] + node _T_2246 = eq(_T_2244, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2246 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2247 = eq(io.in[0].a.bits.size, _T_2231) @[Frontend.scala 165:14] + node _T_2248 = or(_T_2247, reset) @[Frontend.scala 165:14] + node _T_2250 = eq(_T_2248, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2250 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2251 = eq(io.in[0].a.bits.source, _T_2233) @[Frontend.scala 165:14] + node _T_2252 = or(_T_2251, reset) @[Frontend.scala 165:14] + node _T_2254 = eq(_T_2252, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2254 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2255 = eq(io.in[0].a.bits.address, _T_2235) @[Frontend.scala 165:14] + node _T_2256 = or(_T_2255, reset) @[Frontend.scala 165:14] + node _T_2258 = eq(_T_2256, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2258 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2259 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2260 = and(_T_2259, _T_2216) @[Frontend.scala 165:14] + when _T_2260 : @[Frontend.scala 165:14] + _T_2227 <= io.in[0].a.bits.opcode @[Frontend.scala 165:14] + _T_2229 <= io.in[0].a.bits.param @[Frontend.scala 165:14] + _T_2231 <= io.in[0].a.bits.size @[Frontend.scala 165:14] + _T_2233 <= io.in[0].a.bits.source @[Frontend.scala 165:14] + _T_2235 <= io.in[0].a.bits.address @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2261 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2263 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2264 = dshl(_T_2263, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2265 = bits(_T_2264, 7, 0) @[package.scala 19:76] + node _T_2266 = not(_T_2265) @[package.scala 19:40] + node _T_2267 = shr(_T_2266, 3) @[Edges.scala 198:59] + node _T_2268 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2273 = mux(UInt<1>("h00"), _T_2267, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2275 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2277 = sub(_T_2275, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2278 = asUInt(_T_2277) @[Edges.scala 208:28] + node _T_2279 = tail(_T_2278, 1) @[Edges.scala 208:28] + node _T_2281 = eq(_T_2275, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2283 = eq(_T_2275, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2285 = eq(_T_2273, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2286 = or(_T_2283, _T_2285) @[Edges.scala 210:37] + node _T_2287 = and(_T_2286, _T_2261) @[Edges.scala 211:22] + node _T_2288 = not(_T_2279) @[Edges.scala 212:27] + node _T_2289 = and(_T_2273, _T_2288) @[Edges.scala 212:25] + when _T_2261 : @[Edges.scala 213:17] + node _T_2290 = mux(_T_2281, _T_2273, _T_2279) @[Edges.scala 214:21] + _T_2275 <= _T_2290 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2292 : UInt, clock @[Frontend.scala 165:14] + reg _T_2294 : UInt, clock @[Frontend.scala 165:14] + reg _T_2296 : UInt, clock @[Frontend.scala 165:14] + reg _T_2298 : UInt, clock @[Frontend.scala 165:14] + reg _T_2300 : UInt, clock @[Frontend.scala 165:14] + node _T_2302 = eq(_T_2281, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2303 = and(io.in[0].b.valid, _T_2302) @[Frontend.scala 165:14] + when _T_2303 : @[Frontend.scala 165:14] + node _T_2304 = eq(io.in[0].b.bits.opcode, _T_2292) @[Frontend.scala 165:14] + node _T_2305 = or(_T_2304, reset) @[Frontend.scala 165:14] + node _T_2307 = eq(_T_2305, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2307 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2308 = eq(io.in[0].b.bits.param, _T_2294) @[Frontend.scala 165:14] + node _T_2309 = or(_T_2308, reset) @[Frontend.scala 165:14] + node _T_2311 = eq(_T_2309, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2311 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2312 = eq(io.in[0].b.bits.size, _T_2296) @[Frontend.scala 165:14] + node _T_2313 = or(_T_2312, reset) @[Frontend.scala 165:14] + node _T_2315 = eq(_T_2313, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2315 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2316 = eq(io.in[0].b.bits.source, _T_2298) @[Frontend.scala 165:14] + node _T_2317 = or(_T_2316, reset) @[Frontend.scala 165:14] + node _T_2319 = eq(_T_2317, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2319 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2320 = eq(io.in[0].b.bits.address, _T_2300) @[Frontend.scala 165:14] + node _T_2321 = or(_T_2320, reset) @[Frontend.scala 165:14] + node _T_2323 = eq(_T_2321, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2323 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2324 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2325 = and(_T_2324, _T_2281) @[Frontend.scala 165:14] + when _T_2325 : @[Frontend.scala 165:14] + _T_2292 <= io.in[0].b.bits.opcode @[Frontend.scala 165:14] + _T_2294 <= io.in[0].b.bits.param @[Frontend.scala 165:14] + _T_2296 <= io.in[0].b.bits.size @[Frontend.scala 165:14] + _T_2298 <= io.in[0].b.bits.source @[Frontend.scala 165:14] + _T_2300 <= io.in[0].b.bits.address @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2326 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2328 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2329 = dshl(_T_2328, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2330 = bits(_T_2329, 7, 0) @[package.scala 19:76] + node _T_2331 = not(_T_2330) @[package.scala 19:40] + node _T_2332 = shr(_T_2331, 3) @[Edges.scala 198:59] + node _T_2333 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2336 = mux(UInt<1>("h00"), _T_2332, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2338 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2340 = sub(_T_2338, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2341 = asUInt(_T_2340) @[Edges.scala 208:28] + node _T_2342 = tail(_T_2341, 1) @[Edges.scala 208:28] + node _T_2344 = eq(_T_2338, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2346 = eq(_T_2338, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2348 = eq(_T_2336, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2349 = or(_T_2346, _T_2348) @[Edges.scala 210:37] + node _T_2350 = and(_T_2349, _T_2326) @[Edges.scala 211:22] + node _T_2351 = not(_T_2342) @[Edges.scala 212:27] + node _T_2352 = and(_T_2336, _T_2351) @[Edges.scala 212:25] + when _T_2326 : @[Edges.scala 213:17] + node _T_2353 = mux(_T_2344, _T_2336, _T_2342) @[Edges.scala 214:21] + _T_2338 <= _T_2353 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2355 : UInt, clock @[Frontend.scala 165:14] + reg _T_2357 : UInt, clock @[Frontend.scala 165:14] + reg _T_2359 : UInt, clock @[Frontend.scala 165:14] + reg _T_2361 : UInt, clock @[Frontend.scala 165:14] + reg _T_2363 : UInt, clock @[Frontend.scala 165:14] + node _T_2365 = eq(_T_2344, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2366 = and(io.in[0].c.valid, _T_2365) @[Frontend.scala 165:14] + when _T_2366 : @[Frontend.scala 165:14] + node _T_2367 = eq(io.in[0].c.bits.opcode, _T_2355) @[Frontend.scala 165:14] + node _T_2368 = or(_T_2367, reset) @[Frontend.scala 165:14] + node _T_2370 = eq(_T_2368, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2370 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2371 = eq(io.in[0].c.bits.param, _T_2357) @[Frontend.scala 165:14] + node _T_2372 = or(_T_2371, reset) @[Frontend.scala 165:14] + node _T_2374 = eq(_T_2372, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2374 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2375 = eq(io.in[0].c.bits.size, _T_2359) @[Frontend.scala 165:14] + node _T_2376 = or(_T_2375, reset) @[Frontend.scala 165:14] + node _T_2378 = eq(_T_2376, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2378 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2379 = eq(io.in[0].c.bits.source, _T_2361) @[Frontend.scala 165:14] + node _T_2380 = or(_T_2379, reset) @[Frontend.scala 165:14] + node _T_2382 = eq(_T_2380, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2382 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2383 = eq(io.in[0].c.bits.address, _T_2363) @[Frontend.scala 165:14] + node _T_2384 = or(_T_2383, reset) @[Frontend.scala 165:14] + node _T_2386 = eq(_T_2384, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2386 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2387 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2388 = and(_T_2387, _T_2344) @[Frontend.scala 165:14] + when _T_2388 : @[Frontend.scala 165:14] + _T_2355 <= io.in[0].c.bits.opcode @[Frontend.scala 165:14] + _T_2357 <= io.in[0].c.bits.param @[Frontend.scala 165:14] + _T_2359 <= io.in[0].c.bits.size @[Frontend.scala 165:14] + _T_2361 <= io.in[0].c.bits.source @[Frontend.scala 165:14] + _T_2363 <= io.in[0].c.bits.address @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2389 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2391 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2392 = dshl(_T_2391, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2393 = bits(_T_2392, 7, 0) @[package.scala 19:76] + node _T_2394 = not(_T_2393) @[package.scala 19:40] + node _T_2395 = shr(_T_2394, 3) @[Edges.scala 198:59] + node _T_2396 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2398 = mux(_T_2396, _T_2395, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2400 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2402 = sub(_T_2400, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2403 = asUInt(_T_2402) @[Edges.scala 208:28] + node _T_2404 = tail(_T_2403, 1) @[Edges.scala 208:28] + node _T_2406 = eq(_T_2400, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2408 = eq(_T_2400, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2410 = eq(_T_2398, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2411 = or(_T_2408, _T_2410) @[Edges.scala 210:37] + node _T_2412 = and(_T_2411, _T_2389) @[Edges.scala 211:22] + node _T_2413 = not(_T_2404) @[Edges.scala 212:27] + node _T_2414 = and(_T_2398, _T_2413) @[Edges.scala 212:25] + when _T_2389 : @[Edges.scala 213:17] + node _T_2415 = mux(_T_2406, _T_2398, _T_2404) @[Edges.scala 214:21] + _T_2400 <= _T_2415 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2417 : UInt, clock @[Frontend.scala 165:14] + reg _T_2419 : UInt, clock @[Frontend.scala 165:14] + reg _T_2421 : UInt, clock @[Frontend.scala 165:14] + reg _T_2423 : UInt, clock @[Frontend.scala 165:14] + reg _T_2425 : UInt, clock @[Frontend.scala 165:14] + reg _T_2427 : UInt, clock @[Frontend.scala 165:14] + node _T_2429 = eq(_T_2406, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2430 = and(io.in[0].d.valid, _T_2429) @[Frontend.scala 165:14] + when _T_2430 : @[Frontend.scala 165:14] + node _T_2431 = eq(io.in[0].d.bits.opcode, _T_2417) @[Frontend.scala 165:14] + node _T_2432 = or(_T_2431, reset) @[Frontend.scala 165:14] + node _T_2434 = eq(_T_2432, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2434 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2435 = eq(io.in[0].d.bits.param, _T_2419) @[Frontend.scala 165:14] + node _T_2436 = or(_T_2435, reset) @[Frontend.scala 165:14] + node _T_2438 = eq(_T_2436, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2438 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2439 = eq(io.in[0].d.bits.size, _T_2421) @[Frontend.scala 165:14] + node _T_2440 = or(_T_2439, reset) @[Frontend.scala 165:14] + node _T_2442 = eq(_T_2440, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2442 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2443 = eq(io.in[0].d.bits.source, _T_2423) @[Frontend.scala 165:14] + node _T_2444 = or(_T_2443, reset) @[Frontend.scala 165:14] + node _T_2446 = eq(_T_2444, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2446 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2447 = eq(io.in[0].d.bits.sink, _T_2425) @[Frontend.scala 165:14] + node _T_2448 = or(_T_2447, reset) @[Frontend.scala 165:14] + node _T_2450 = eq(_T_2448, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2450 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2451 = eq(io.in[0].d.bits.addr_lo, _T_2427) @[Frontend.scala 165:14] + node _T_2452 = or(_T_2451, reset) @[Frontend.scala 165:14] + node _T_2454 = eq(_T_2452, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2454 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at Frontend.scala:165:14)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2455 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2456 = and(_T_2455, _T_2406) @[Frontend.scala 165:14] + when _T_2456 : @[Frontend.scala 165:14] + _T_2417 <= io.in[0].d.bits.opcode @[Frontend.scala 165:14] + _T_2419 <= io.in[0].d.bits.param @[Frontend.scala 165:14] + _T_2421 <= io.in[0].d.bits.size @[Frontend.scala 165:14] + _T_2423 <= io.in[0].d.bits.source @[Frontend.scala 165:14] + _T_2425 <= io.in[0].d.bits.sink @[Frontend.scala 165:14] + _T_2427 <= io.in[0].d.bits.addr_lo @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + reg _T_2458 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_2459 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2461 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2462 = dshl(_T_2461, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2463 = bits(_T_2462, 7, 0) @[package.scala 19:76] + node _T_2464 = not(_T_2463) @[package.scala 19:40] + node _T_2465 = shr(_T_2464, 3) @[Edges.scala 198:59] + node _T_2466 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2468 = eq(_T_2466, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2470 = mux(_T_2468, _T_2465, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2472 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2474 = sub(_T_2472, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2475 = asUInt(_T_2474) @[Edges.scala 208:28] + node _T_2476 = tail(_T_2475, 1) @[Edges.scala 208:28] + node _T_2478 = eq(_T_2472, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2480 = eq(_T_2472, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2482 = eq(_T_2470, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2483 = or(_T_2480, _T_2482) @[Edges.scala 210:37] + node _T_2484 = and(_T_2483, _T_2459) @[Edges.scala 211:22] + node _T_2485 = not(_T_2476) @[Edges.scala 212:27] + node _T_2486 = and(_T_2470, _T_2485) @[Edges.scala 212:25] + when _T_2459 : @[Edges.scala 213:17] + node _T_2487 = mux(_T_2478, _T_2470, _T_2476) @[Edges.scala 214:21] + _T_2472 <= _T_2487 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2488 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2490 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2491 = dshl(_T_2490, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2492 = bits(_T_2491, 7, 0) @[package.scala 19:76] + node _T_2493 = not(_T_2492) @[package.scala 19:40] + node _T_2494 = shr(_T_2493, 3) @[Edges.scala 198:59] + node _T_2495 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2497 = mux(_T_2495, _T_2494, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2499 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2501 = sub(_T_2499, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2502 = asUInt(_T_2501) @[Edges.scala 208:28] + node _T_2503 = tail(_T_2502, 1) @[Edges.scala 208:28] + node _T_2505 = eq(_T_2499, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2507 = eq(_T_2499, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2509 = eq(_T_2497, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2510 = or(_T_2507, _T_2509) @[Edges.scala 210:37] + node _T_2511 = and(_T_2510, _T_2488) @[Edges.scala 211:22] + node _T_2512 = not(_T_2503) @[Edges.scala 212:27] + node _T_2513 = and(_T_2497, _T_2512) @[Edges.scala 212:25] + when _T_2488 : @[Edges.scala 213:17] + node _T_2514 = mux(_T_2505, _T_2497, _T_2503) @[Edges.scala 214:21] + _T_2499 <= _T_2514 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2516 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + node _T_2517 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[Frontend.scala 165:14] + node _T_2518 = or(_T_2516, _T_2517) @[Frontend.scala 165:14] + node _T_2520 = eq(io.in[0].a.valid, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2521 = or(_T_2518, _T_2520) @[Frontend.scala 165:14] + node _T_2523 = eq(io.in[0].d.valid, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2524 = or(_T_2521, _T_2523) @[Frontend.scala 165:14] + node _T_2525 = or(_T_2524, reset) @[Frontend.scala 165:14] + node _T_2527 = eq(_T_2525, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2527 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Frontend.scala:165:14)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + wire _T_2529 : UInt<1> + _T_2529 is invalid + _T_2529 <= UInt<1>("h00") + node _T_2530 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2530 : @[Frontend.scala 165:14] + when _T_2483 : @[Frontend.scala 165:14] + node _T_2532 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2529 <= _T_2532 @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2533 = dshr(_T_2458, io.in[0].a.bits.source) @[Frontend.scala 165:14] + node _T_2534 = bits(_T_2533, 0, 0) @[Frontend.scala 165:14] + node _T_2536 = eq(_T_2534, UInt<1>("h00")) @[Frontend.scala 165:14] + node _T_2537 = or(_T_2536, reset) @[Frontend.scala 165:14] + node _T_2539 = eq(_T_2537, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2539 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at Frontend.scala:165:14)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + wire _T_2541 : UInt<1> + _T_2541 is invalid + _T_2541 <= UInt<1>("h00") + node _T_2542 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2544 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Frontend.scala 165:14] + node _T_2545 = and(_T_2542, _T_2544) @[Frontend.scala 165:14] + when _T_2545 : @[Frontend.scala 165:14] + when _T_2510 : @[Frontend.scala 165:14] + node _T_2547 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2541 <= _T_2547 @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2548 = or(_T_2529, _T_2458) @[Frontend.scala 165:14] + node _T_2549 = dshr(_T_2548, io.in[0].d.bits.source) @[Frontend.scala 165:14] + node _T_2550 = bits(_T_2549, 0, 0) @[Frontend.scala 165:14] + node _T_2551 = or(_T_2550, reset) @[Frontend.scala 165:14] + node _T_2553 = eq(_T_2551, UInt<1>("h00")) @[Frontend.scala 165:14] + when _T_2553 : @[Frontend.scala 165:14] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:165:14)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[Frontend.scala 165:14] + stop(clock, UInt<1>(1), 1) @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + skip @[Frontend.scala 165:14] + node _T_2554 = or(_T_2458, _T_2529) @[Frontend.scala 165:14] + node _T_2555 = not(_T_2541) @[Frontend.scala 165:14] + node _T_2556 = and(_T_2554, _T_2555) @[Frontend.scala 165:14] + _T_2458 <= _T_2556 @[Frontend.scala 165:14] + + module FPUDecoder : + input clock : Clock + input reset : UInt<1> + output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}} + + io is invalid + io is invalid + node _T_22 = and(io.inst, UInt<32>("h04")) @[Decode.scala 13:65] + node _T_24 = eq(_T_22, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_26 = and(io.inst, UInt<32>("h08000010")) @[Decode.scala 13:65] + node _T_28 = eq(_T_26, UInt<32>("h08000010")) @[Decode.scala 13:121] + node _T_30 = or(UInt<1>("h00"), _T_24) @[Decode.scala 14:30] + node _T_31 = or(_T_30, _T_28) @[Decode.scala 14:30] + node _T_33 = and(io.inst, UInt<32>("h08")) @[Decode.scala 13:65] + node _T_35 = eq(_T_33, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_37 = and(io.inst, UInt<32>("h010000010")) @[Decode.scala 13:65] + node _T_39 = eq(_T_37, UInt<32>("h010000010")) @[Decode.scala 13:121] + node _T_41 = or(UInt<1>("h00"), _T_35) @[Decode.scala 14:30] + node _T_42 = or(_T_41, _T_39) @[Decode.scala 14:30] + node _T_44 = and(io.inst, UInt<32>("h040")) @[Decode.scala 13:65] + node _T_46 = eq(_T_44, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_48 = and(io.inst, UInt<32>("h020000000")) @[Decode.scala 13:65] + node _T_50 = eq(_T_48, UInt<32>("h020000000")) @[Decode.scala 13:121] + node _T_52 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_53 = or(_T_52, _T_50) @[Decode.scala 14:30] + node _T_55 = and(io.inst, UInt<32>("h040000000")) @[Decode.scala 13:65] + node _T_57 = eq(_T_55, UInt<32>("h040000000")) @[Decode.scala 13:121] + node _T_59 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_60 = or(_T_59, _T_57) @[Decode.scala 14:30] + node _T_62 = and(io.inst, UInt<32>("h010")) @[Decode.scala 13:65] + node _T_64 = eq(_T_62, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_66 = or(UInt<1>("h00"), _T_64) @[Decode.scala 14:30] + node _T_67 = cat(_T_42, _T_31) @[Cat.scala 30:58] + node _T_68 = cat(_T_66, _T_60) @[Cat.scala 30:58] + node _T_69 = cat(_T_68, _T_53) @[Cat.scala 30:58] + node decoder_0 = cat(_T_69, _T_67) @[Cat.scala 30:58] + node decoder_1 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_72 = and(io.inst, UInt<32>("h080000020")) @[Decode.scala 13:65] + node _T_74 = eq(_T_72, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_76 = and(io.inst, UInt<32>("h030")) @[Decode.scala 13:65] + node _T_78 = eq(_T_76, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_80 = and(io.inst, UInt<32>("h010000020")) @[Decode.scala 13:65] + node _T_82 = eq(_T_80, UInt<32>("h010000000")) @[Decode.scala 13:121] + node _T_84 = or(UInt<1>("h00"), _T_74) @[Decode.scala 14:30] + node _T_85 = or(_T_84, _T_78) @[Decode.scala 14:30] + node decoder_2 = or(_T_85, _T_82) @[Decode.scala 14:30] + node _T_87 = and(io.inst, UInt<32>("h080000004")) @[Decode.scala 13:65] + node _T_89 = eq(_T_87, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_91 = and(io.inst, UInt<32>("h010000004")) @[Decode.scala 13:65] + node _T_93 = eq(_T_91, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_95 = and(io.inst, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_97 = eq(_T_95, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_99 = or(UInt<1>("h00"), _T_89) @[Decode.scala 14:30] + node _T_100 = or(_T_99, _T_93) @[Decode.scala 14:30] + node decoder_3 = or(_T_100, _T_97) @[Decode.scala 14:30] + node _T_102 = and(io.inst, UInt<32>("h040000004")) @[Decode.scala 13:65] + node _T_104 = eq(_T_102, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_106 = and(io.inst, UInt<32>("h020")) @[Decode.scala 13:65] + node _T_108 = eq(_T_106, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_111 = or(_T_110, _T_108) @[Decode.scala 14:30] + node decoder_4 = or(_T_111, _T_97) @[Decode.scala 14:30] + node decoder_5 = or(UInt<1>("h00"), _T_97) @[Decode.scala 14:30] + node _T_114 = and(io.inst, UInt<32>("h050000010")) @[Decode.scala 13:65] + node _T_116 = eq(_T_114, UInt<32>("h050000010")) @[Decode.scala 13:121] + node _T_118 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node decoder_6 = or(_T_118, _T_116) @[Decode.scala 14:30] + node _T_120 = and(io.inst, UInt<32>("h030000010")) @[Decode.scala 13:65] + node _T_122 = eq(_T_120, UInt<32>("h010")) @[Decode.scala 13:121] + node decoder_7 = or(UInt<1>("h00"), _T_122) @[Decode.scala 14:30] + node _T_125 = and(io.inst, UInt<32>("h01040")) @[Decode.scala 13:65] + node _T_127 = eq(_T_125, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_129 = and(io.inst, UInt<32>("h02000040")) @[Decode.scala 13:65] + node _T_131 = eq(_T_129, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_133 = or(UInt<1>("h00"), _T_127) @[Decode.scala 14:30] + node decoder_8 = or(_T_133, _T_131) @[Decode.scala 14:30] + node _T_135 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_137 = eq(_T_135, UInt<32>("h090000010")) @[Decode.scala 13:121] + node decoder_9 = or(UInt<1>("h00"), _T_137) @[Decode.scala 14:30] + node _T_140 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_142 = eq(_T_140, UInt<32>("h080000010")) @[Decode.scala 13:121] + node _T_144 = or(UInt<1>("h00"), _T_108) @[Decode.scala 14:30] + node decoder_10 = or(_T_144, _T_142) @[Decode.scala 14:30] + node _T_146 = and(io.inst, UInt<32>("h0a0000010")) @[Decode.scala 13:65] + node _T_148 = eq(_T_146, UInt<32>("h020000010")) @[Decode.scala 13:121] + node _T_150 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65] + node _T_152 = eq(_T_150, UInt<32>("h040000010")) @[Decode.scala 13:121] + node _T_154 = or(UInt<1>("h00"), _T_148) @[Decode.scala 14:30] + node decoder_11 = or(_T_154, _T_152) @[Decode.scala 14:30] + node _T_156 = and(io.inst, UInt<32>("h070000004")) @[Decode.scala 13:65] + node _T_158 = eq(_T_156, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_160 = and(io.inst, UInt<32>("h068000004")) @[Decode.scala 13:65] + node _T_162 = eq(_T_160, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_164 = or(UInt<1>("h00"), _T_158) @[Decode.scala 14:30] + node _T_165 = or(_T_164, _T_162) @[Decode.scala 14:30] + node decoder_12 = or(_T_165, _T_97) @[Decode.scala 14:30] + node _T_167 = and(io.inst, UInt<32>("h058000010")) @[Decode.scala 13:65] + node _T_169 = eq(_T_167, UInt<32>("h018000010")) @[Decode.scala 13:121] + node decoder_13 = or(UInt<1>("h00"), _T_169) @[Decode.scala 14:30] + node _T_172 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65] + node _T_174 = eq(_T_172, UInt<32>("h050000010")) @[Decode.scala 13:121] + node decoder_14 = or(UInt<1>("h00"), _T_174) @[Decode.scala 14:30] + node _T_177 = and(io.inst, UInt<32>("h020000004")) @[Decode.scala 13:65] + node _T_179 = eq(_T_177, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_181 = and(io.inst, UInt<32>("h08002000")) @[Decode.scala 13:65] + node _T_183 = eq(_T_181, UInt<32>("h08000000")) @[Decode.scala 13:121] + node _T_185 = and(io.inst, UInt<32>("h0c0000004")) @[Decode.scala 13:65] + node _T_187 = eq(_T_185, UInt<32>("h080000000")) @[Decode.scala 13:121] + node _T_189 = or(UInt<1>("h00"), _T_179) @[Decode.scala 14:30] + node _T_190 = or(_T_189, _T_97) @[Decode.scala 14:30] + node _T_191 = or(_T_190, _T_183) @[Decode.scala 14:30] + node decoder_15 = or(_T_191, _T_187) @[Decode.scala 14:30] + io.sigs.cmd <= decoder_0 @[FPU.scala 149:40] + io.sigs.ldst <= decoder_1 @[FPU.scala 149:40] + io.sigs.wen <= decoder_2 @[FPU.scala 149:40] + io.sigs.ren1 <= decoder_3 @[FPU.scala 149:40] + io.sigs.ren2 <= decoder_4 @[FPU.scala 149:40] + io.sigs.ren3 <= decoder_5 @[FPU.scala 149:40] + io.sigs.swap12 <= decoder_6 @[FPU.scala 149:40] + io.sigs.swap23 <= decoder_7 @[FPU.scala 149:40] + io.sigs.single <= decoder_8 @[FPU.scala 149:40] + io.sigs.fromint <= decoder_9 @[FPU.scala 149:40] + io.sigs.toint <= decoder_10 @[FPU.scala 149:40] + io.sigs.fastpipe <= decoder_11 @[FPU.scala 149:40] + io.sigs.fma <= decoder_12 @[FPU.scala 149:40] + io.sigs.div <= decoder_13 @[FPU.scala 149:40] + io.sigs.sqrt <= decoder_14 @[FPU.scala 149:40] + io.sigs.wflags <= decoder_15 @[FPU.scala 149:40] + + module MulAddRecFN_preMul : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} + + io is invalid + io is invalid + node signA = bits(io.a, 32, 32) @[MulAddRecFN.scala 102:22] + node expA = bits(io.a, 31, 23) @[MulAddRecFN.scala 103:22] + node fractA = bits(io.a, 22, 0) @[MulAddRecFN.scala 104:22] + node _T_52 = bits(expA, 8, 6) @[MulAddRecFN.scala 105:24] + node isZeroA = eq(_T_52, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] + node _T_55 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] + node sigA = cat(_T_55, fractA) @[Cat.scala 30:58] + node signB = bits(io.b, 32, 32) @[MulAddRecFN.scala 108:22] + node expB = bits(io.b, 31, 23) @[MulAddRecFN.scala 109:22] + node fractB = bits(io.b, 22, 0) @[MulAddRecFN.scala 110:22] + node _T_56 = bits(expB, 8, 6) @[MulAddRecFN.scala 111:24] + node isZeroB = eq(_T_56, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] + node _T_59 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] + node sigB = cat(_T_59, fractB) @[Cat.scala 30:58] + node _T_60 = bits(io.c, 32, 32) @[MulAddRecFN.scala 114:23] + node _T_61 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] + node opSignC = xor(_T_60, _T_61) @[MulAddRecFN.scala 114:45] + node expC = bits(io.c, 31, 23) @[MulAddRecFN.scala 115:22] + node fractC = bits(io.c, 22, 0) @[MulAddRecFN.scala 116:22] + node _T_62 = bits(expC, 8, 6) @[MulAddRecFN.scala 117:24] + node isZeroC = eq(_T_62, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] + node _T_65 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] + node sigC = cat(_T_65, fractC) @[Cat.scala 30:58] + node _T_66 = xor(signA, signB) @[MulAddRecFN.scala 122:26] + node _T_67 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] + node signProd = xor(_T_66, _T_67) @[MulAddRecFN.scala 122:34] + node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] + node _T_68 = bits(expB, 8, 8) @[MulAddRecFN.scala 125:34] + node _T_70 = eq(_T_68, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] + node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 71:15] + node _T_74 = mux(_T_71, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_75 = bits(expB, 7, 0) @[MulAddRecFN.scala 125:51] + node _T_76 = cat(_T_74, _T_75) @[Cat.scala 30:58] + node _T_77 = add(expA, _T_76) @[MulAddRecFN.scala 125:14] + node _T_78 = tail(_T_77, 1) @[MulAddRecFN.scala 125:14] + node _T_80 = add(_T_78, UInt<5>("h01b")) @[MulAddRecFN.scala 125:70] + node sExpAlignedProd = tail(_T_80, 1) @[MulAddRecFN.scala 125:70] + node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] + node _T_81 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] + node _T_82 = asUInt(_T_81) @[MulAddRecFN.scala 132:42] + node sNatCAlignDist = tail(_T_82, 1) @[MulAddRecFN.scala 132:42] + node _T_83 = bits(sNatCAlignDist, 10, 10) @[MulAddRecFN.scala 133:56] + node CAlignDist_floor = or(isZeroProd, _T_83) @[MulAddRecFN.scala 133:39] + node _T_84 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 135:44] + node _T_86 = eq(_T_84, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] + node CAlignDist_0 = or(CAlignDist_floor, _T_86) @[MulAddRecFN.scala 135:26] + node _T_88 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] + node _T_89 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 139:33] + node _T_91 = lt(_T_89, UInt<5>("h019")) @[MulAddRecFN.scala 139:51] + node _T_92 = or(CAlignDist_floor, _T_91) @[MulAddRecFN.scala 138:31] + node isCDominant = and(_T_88, _T_92) @[MulAddRecFN.scala 137:19] + node _T_94 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 143:31] + node _T_96 = lt(_T_94, UInt<7>("h04a")) @[MulAddRecFN.scala 143:49] + node _T_97 = bits(sNatCAlignDist, 6, 0) @[MulAddRecFN.scala 144:31] + node _T_99 = mux(_T_96, _T_97, UInt<7>("h04a")) @[MulAddRecFN.scala 143:16] + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), _T_99) @[MulAddRecFN.scala 141:12] + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] + node _T_100 = bits(CAlignDist, 6, 6) @[primitives.scala 56:25] + node _T_101 = bits(CAlignDist, 5, 0) @[primitives.scala 57:26] + node _T_103 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_101) @[primitives.scala 68:52] + node _T_104 = bits(_T_103, 63, 54) @[primitives.scala 69:26] + node _T_105 = bits(_T_104, 7, 0) @[Bitwise.scala 108:18] + node _T_108 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_109 = xor(UInt<8>("h0ff"), _T_108) @[Bitwise.scala 101:21] + node _T_110 = shr(_T_105, 4) @[Bitwise.scala 102:21] + node _T_111 = and(_T_110, _T_109) @[Bitwise.scala 102:31] + node _T_112 = bits(_T_105, 3, 0) @[Bitwise.scala 102:46] + node _T_113 = shl(_T_112, 4) @[Bitwise.scala 102:65] + node _T_114 = not(_T_109) @[Bitwise.scala 102:77] + node _T_115 = and(_T_113, _T_114) @[Bitwise.scala 102:75] + node _T_116 = or(_T_111, _T_115) @[Bitwise.scala 102:39] + node _T_117 = bits(_T_109, 5, 0) @[Bitwise.scala 101:28] + node _T_118 = shl(_T_117, 2) @[Bitwise.scala 101:47] + node _T_119 = xor(_T_109, _T_118) @[Bitwise.scala 101:21] + node _T_120 = shr(_T_116, 2) @[Bitwise.scala 102:21] + node _T_121 = and(_T_120, _T_119) @[Bitwise.scala 102:31] + node _T_122 = bits(_T_116, 5, 0) @[Bitwise.scala 102:46] + node _T_123 = shl(_T_122, 2) @[Bitwise.scala 102:65] + node _T_124 = not(_T_119) @[Bitwise.scala 102:77] + node _T_125 = and(_T_123, _T_124) @[Bitwise.scala 102:75] + node _T_126 = or(_T_121, _T_125) @[Bitwise.scala 102:39] + node _T_127 = bits(_T_119, 6, 0) @[Bitwise.scala 101:28] + node _T_128 = shl(_T_127, 1) @[Bitwise.scala 101:47] + node _T_129 = xor(_T_119, _T_128) @[Bitwise.scala 101:21] + node _T_130 = shr(_T_126, 1) @[Bitwise.scala 102:21] + node _T_131 = and(_T_130, _T_129) @[Bitwise.scala 102:31] + node _T_132 = bits(_T_126, 6, 0) @[Bitwise.scala 102:46] + node _T_133 = shl(_T_132, 1) @[Bitwise.scala 102:65] + node _T_134 = not(_T_129) @[Bitwise.scala 102:77] + node _T_135 = and(_T_133, _T_134) @[Bitwise.scala 102:75] + node _T_136 = or(_T_131, _T_135) @[Bitwise.scala 102:39] + node _T_137 = bits(_T_104, 9, 8) @[Bitwise.scala 108:44] + node _T_138 = bits(_T_137, 0, 0) @[Bitwise.scala 108:18] + node _T_139 = bits(_T_137, 1, 1) @[Bitwise.scala 108:44] + node _T_140 = cat(_T_138, _T_139) @[Cat.scala 30:58] + node _T_141 = cat(_T_136, _T_140) @[Cat.scala 30:58] + node _T_143 = cat(_T_141, UInt<14>("h03fff")) @[Cat.scala 30:58] + node _T_145 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_101) @[primitives.scala 68:52] + node _T_146 = bits(_T_145, 13, 0) @[primitives.scala 69:26] + node _T_147 = bits(_T_146, 7, 0) @[Bitwise.scala 108:18] + node _T_150 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_151 = xor(UInt<8>("h0ff"), _T_150) @[Bitwise.scala 101:21] + node _T_152 = shr(_T_147, 4) @[Bitwise.scala 102:21] + node _T_153 = and(_T_152, _T_151) @[Bitwise.scala 102:31] + node _T_154 = bits(_T_147, 3, 0) @[Bitwise.scala 102:46] + node _T_155 = shl(_T_154, 4) @[Bitwise.scala 102:65] + node _T_156 = not(_T_151) @[Bitwise.scala 102:77] + node _T_157 = and(_T_155, _T_156) @[Bitwise.scala 102:75] + node _T_158 = or(_T_153, _T_157) @[Bitwise.scala 102:39] + node _T_159 = bits(_T_151, 5, 0) @[Bitwise.scala 101:28] + node _T_160 = shl(_T_159, 2) @[Bitwise.scala 101:47] + node _T_161 = xor(_T_151, _T_160) @[Bitwise.scala 101:21] + node _T_162 = shr(_T_158, 2) @[Bitwise.scala 102:21] + node _T_163 = and(_T_162, _T_161) @[Bitwise.scala 102:31] + node _T_164 = bits(_T_158, 5, 0) @[Bitwise.scala 102:46] + node _T_165 = shl(_T_164, 2) @[Bitwise.scala 102:65] + node _T_166 = not(_T_161) @[Bitwise.scala 102:77] + node _T_167 = and(_T_165, _T_166) @[Bitwise.scala 102:75] + node _T_168 = or(_T_163, _T_167) @[Bitwise.scala 102:39] + node _T_169 = bits(_T_161, 6, 0) @[Bitwise.scala 101:28] + node _T_170 = shl(_T_169, 1) @[Bitwise.scala 101:47] + node _T_171 = xor(_T_161, _T_170) @[Bitwise.scala 101:21] + node _T_172 = shr(_T_168, 1) @[Bitwise.scala 102:21] + node _T_173 = and(_T_172, _T_171) @[Bitwise.scala 102:31] + node _T_174 = bits(_T_168, 6, 0) @[Bitwise.scala 102:46] + node _T_175 = shl(_T_174, 1) @[Bitwise.scala 102:65] + node _T_176 = not(_T_171) @[Bitwise.scala 102:77] + node _T_177 = and(_T_175, _T_176) @[Bitwise.scala 102:75] + node _T_178 = or(_T_173, _T_177) @[Bitwise.scala 102:39] + node _T_179 = bits(_T_146, 13, 8) @[Bitwise.scala 108:44] + node _T_180 = bits(_T_179, 3, 0) @[Bitwise.scala 108:18] + node _T_181 = bits(_T_180, 1, 0) @[Bitwise.scala 108:18] + node _T_182 = bits(_T_181, 0, 0) @[Bitwise.scala 108:18] + node _T_183 = bits(_T_181, 1, 1) @[Bitwise.scala 108:44] + node _T_184 = cat(_T_182, _T_183) @[Cat.scala 30:58] + node _T_185 = bits(_T_180, 3, 2) @[Bitwise.scala 108:44] + node _T_186 = bits(_T_185, 0, 0) @[Bitwise.scala 108:18] + node _T_187 = bits(_T_185, 1, 1) @[Bitwise.scala 108:44] + node _T_188 = cat(_T_186, _T_187) @[Cat.scala 30:58] + node _T_189 = cat(_T_184, _T_188) @[Cat.scala 30:58] + node _T_190 = bits(_T_179, 5, 4) @[Bitwise.scala 108:44] + node _T_191 = bits(_T_190, 0, 0) @[Bitwise.scala 108:18] + node _T_192 = bits(_T_190, 1, 1) @[Bitwise.scala 108:44] + node _T_193 = cat(_T_191, _T_192) @[Cat.scala 30:58] + node _T_194 = cat(_T_189, _T_193) @[Cat.scala 30:58] + node _T_195 = cat(_T_178, _T_194) @[Cat.scala 30:58] + node CExtraMask = mux(_T_100, _T_143, _T_195) @[primitives.scala 61:20] + node _T_196 = not(sigC) @[MulAddRecFN.scala 151:34] + node negSigC = mux(doSubMags, _T_196, sigC) @[MulAddRecFN.scala 151:22] + node _T_197 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_200 = mux(_T_197, UInt<50>("h03ffffffffffff"), UInt<50>("h00")) @[Bitwise.scala 71:12] + node _T_201 = cat(doSubMags, negSigC) @[Cat.scala 30:58] + node _T_202 = cat(_T_201, _T_200) @[Cat.scala 30:58] + node _T_203 = asSInt(_T_202) @[MulAddRecFN.scala 154:64] + node _T_204 = dshr(_T_203, CAlignDist) @[MulAddRecFN.scala 154:70] + node _T_205 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] + node _T_207 = neq(_T_205, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] + node _T_208 = xor(_T_207, doSubMags) @[MulAddRecFN.scala 156:37] + node _T_209 = asUInt(_T_204) @[Cat.scala 30:58] + node _T_210 = cat(_T_209, _T_208) @[Cat.scala 30:58] + node alignedNegSigC = bits(_T_210, 74, 0) @[MulAddRecFN.scala 157:10] + io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] + io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] + node _T_211 = bits(alignedNegSigC, 48, 1) @[MulAddRecFN.scala 161:33] + io.mulAddC <= _T_211 @[MulAddRecFN.scala 161:16] + node _T_212 = bits(expA, 8, 6) @[MulAddRecFN.scala 163:44] + io.toPostMul.highExpA <= _T_212 @[MulAddRecFN.scala 163:37] + node _T_213 = bits(fractA, 22, 22) @[MulAddRecFN.scala 164:46] + io.toPostMul.isNaN_isQuietNaNA <= _T_213 @[MulAddRecFN.scala 164:37] + node _T_214 = bits(expB, 8, 6) @[MulAddRecFN.scala 165:44] + io.toPostMul.highExpB <= _T_214 @[MulAddRecFN.scala 165:37] + node _T_215 = bits(fractB, 22, 22) @[MulAddRecFN.scala 166:46] + io.toPostMul.isNaN_isQuietNaNB <= _T_215 @[MulAddRecFN.scala 166:37] + io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] + io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] + io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] + node _T_216 = bits(expC, 8, 6) @[MulAddRecFN.scala 170:44] + io.toPostMul.highExpC <= _T_216 @[MulAddRecFN.scala 170:37] + node _T_217 = bits(fractC, 22, 22) @[MulAddRecFN.scala 171:46] + io.toPostMul.isNaN_isQuietNaNC <= _T_217 @[MulAddRecFN.scala 171:37] + io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] + io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] + io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] + node _T_218 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] + io.toPostMul.bit0AlignedNegSigC <= _T_218 @[MulAddRecFN.scala 175:37] + node _T_219 = bits(alignedNegSigC, 74, 49) @[MulAddRecFN.scala 177:23] + io.toPostMul.highAlignedNegSigC <= _T_219 @[MulAddRecFN.scala 176:37] + io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] + io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] + + module MulAddRecFN_postMul : + input clock : Clock + input reset : UInt<1> + output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] + node _T_43 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] + node isSpecialA = eq(_T_43, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] + node _T_45 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] + node _T_47 = eq(_T_45, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] + node isInfA = and(isSpecialA, _T_47) @[MulAddRecFN.scala 209:29] + node _T_48 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] + node isNaNA = and(isSpecialA, _T_48) @[MulAddRecFN.scala 210:29] + node _T_50 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] + node isSigNaNA = and(isNaNA, _T_50) @[MulAddRecFN.scala 211:28] + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] + node _T_52 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] + node isSpecialB = eq(_T_52, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] + node _T_54 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] + node _T_56 = eq(_T_54, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] + node isInfB = and(isSpecialB, _T_56) @[MulAddRecFN.scala 215:29] + node _T_57 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] + node isNaNB = and(isSpecialB, _T_57) @[MulAddRecFN.scala 216:29] + node _T_59 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] + node isSigNaNB = and(isNaNB, _T_59) @[MulAddRecFN.scala 217:28] + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] + node _T_61 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] + node isSpecialC = eq(_T_61, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] + node _T_63 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] + node isInfC = and(isSpecialC, _T_65) @[MulAddRecFN.scala 221:29] + node _T_66 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] + node isNaNC = and(isSpecialC, _T_66) @[MulAddRecFN.scala 222:29] + node _T_68 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] + node isSigNaNC = and(isNaNC, _T_68) @[MulAddRecFN.scala 223:28] + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] + node _T_71 = bits(io.mulAddResult, 48, 48) @[MulAddRecFN.scala 237:32] + node _T_73 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] + node _T_74 = tail(_T_73, 1) @[MulAddRecFN.scala 238:50] + node _T_75 = mux(_T_71, _T_74, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] + node _T_76 = bits(io.mulAddResult, 47, 0) @[MulAddRecFN.scala 241:28] + node _T_77 = cat(_T_75, _T_76) @[Cat.scala 30:58] + node sigSum = cat(_T_77, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 30:58] + node _T_79 = bits(sigSum, 50, 1) @[MulAddRecFN.scala 248:38] + node _T_80 = xor(UInt<50>("h00"), _T_79) @[MulAddRecFN.scala 191:27] + node _T_81 = or(UInt<50>("h00"), _T_79) @[MulAddRecFN.scala 191:37] + node _T_82 = shl(_T_81, 1) @[MulAddRecFN.scala 191:41] + node _T_83 = xor(_T_80, _T_82) @[MulAddRecFN.scala 191:32] + node _T_85 = bits(_T_83, 49, 0) @[primitives.scala 79:35] + node _T_86 = bits(_T_85, 49, 32) @[CircuitMath.scala 35:17] + node _T_87 = bits(_T_85, 31, 0) @[CircuitMath.scala 36:17] + node _T_89 = neq(_T_86, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_90 = bits(_T_86, 17, 16) @[CircuitMath.scala 35:17] + node _T_91 = bits(_T_86, 15, 0) @[CircuitMath.scala 36:17] + node _T_93 = neq(_T_90, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_94 = bits(_T_90, 1, 1) @[CircuitMath.scala 30:8] + node _T_95 = bits(_T_91, 15, 8) @[CircuitMath.scala 35:17] + node _T_96 = bits(_T_91, 7, 0) @[CircuitMath.scala 36:17] + node _T_98 = neq(_T_95, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_99 = bits(_T_95, 7, 4) @[CircuitMath.scala 35:17] + node _T_100 = bits(_T_95, 3, 0) @[CircuitMath.scala 36:17] + node _T_102 = neq(_T_99, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_103 = bits(_T_99, 3, 3) @[CircuitMath.scala 32:12] + node _T_105 = bits(_T_99, 2, 2) @[CircuitMath.scala 32:12] + node _T_107 = bits(_T_99, 1, 1) @[CircuitMath.scala 30:8] + node _T_108 = mux(_T_105, UInt<2>("h02"), _T_107) @[CircuitMath.scala 32:10] + node _T_109 = mux(_T_103, UInt<2>("h03"), _T_108) @[CircuitMath.scala 32:10] + node _T_110 = bits(_T_100, 3, 3) @[CircuitMath.scala 32:12] + node _T_112 = bits(_T_100, 2, 2) @[CircuitMath.scala 32:12] + node _T_114 = bits(_T_100, 1, 1) @[CircuitMath.scala 30:8] + node _T_115 = mux(_T_112, UInt<2>("h02"), _T_114) @[CircuitMath.scala 32:10] + node _T_116 = mux(_T_110, UInt<2>("h03"), _T_115) @[CircuitMath.scala 32:10] + node _T_117 = mux(_T_102, _T_109, _T_116) @[CircuitMath.scala 38:21] + node _T_118 = cat(_T_102, _T_117) @[Cat.scala 30:58] + node _T_119 = bits(_T_96, 7, 4) @[CircuitMath.scala 35:17] + node _T_120 = bits(_T_96, 3, 0) @[CircuitMath.scala 36:17] + node _T_122 = neq(_T_119, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_123 = bits(_T_119, 3, 3) @[CircuitMath.scala 32:12] + node _T_125 = bits(_T_119, 2, 2) @[CircuitMath.scala 32:12] + node _T_127 = bits(_T_119, 1, 1) @[CircuitMath.scala 30:8] + node _T_128 = mux(_T_125, UInt<2>("h02"), _T_127) @[CircuitMath.scala 32:10] + node _T_129 = mux(_T_123, UInt<2>("h03"), _T_128) @[CircuitMath.scala 32:10] + node _T_130 = bits(_T_120, 3, 3) @[CircuitMath.scala 32:12] + node _T_132 = bits(_T_120, 2, 2) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_120, 1, 1) @[CircuitMath.scala 30:8] + node _T_135 = mux(_T_132, UInt<2>("h02"), _T_134) @[CircuitMath.scala 32:10] + node _T_136 = mux(_T_130, UInt<2>("h03"), _T_135) @[CircuitMath.scala 32:10] + node _T_137 = mux(_T_122, _T_129, _T_136) @[CircuitMath.scala 38:21] + node _T_138 = cat(_T_122, _T_137) @[Cat.scala 30:58] + node _T_139 = mux(_T_98, _T_118, _T_138) @[CircuitMath.scala 38:21] + node _T_140 = cat(_T_98, _T_139) @[Cat.scala 30:58] + node _T_141 = mux(_T_93, _T_94, _T_140) @[CircuitMath.scala 38:21] + node _T_142 = cat(_T_93, _T_141) @[Cat.scala 30:58] + node _T_143 = bits(_T_87, 31, 16) @[CircuitMath.scala 35:17] + node _T_144 = bits(_T_87, 15, 0) @[CircuitMath.scala 36:17] + node _T_146 = neq(_T_143, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_147 = bits(_T_143, 15, 8) @[CircuitMath.scala 35:17] + node _T_148 = bits(_T_143, 7, 0) @[CircuitMath.scala 36:17] + node _T_150 = neq(_T_147, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_151 = bits(_T_147, 7, 4) @[CircuitMath.scala 35:17] + node _T_152 = bits(_T_147, 3, 0) @[CircuitMath.scala 36:17] + node _T_154 = neq(_T_151, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_155 = bits(_T_151, 3, 3) @[CircuitMath.scala 32:12] + node _T_157 = bits(_T_151, 2, 2) @[CircuitMath.scala 32:12] + node _T_159 = bits(_T_151, 1, 1) @[CircuitMath.scala 30:8] + node _T_160 = mux(_T_157, UInt<2>("h02"), _T_159) @[CircuitMath.scala 32:10] + node _T_161 = mux(_T_155, UInt<2>("h03"), _T_160) @[CircuitMath.scala 32:10] + node _T_162 = bits(_T_152, 3, 3) @[CircuitMath.scala 32:12] + node _T_164 = bits(_T_152, 2, 2) @[CircuitMath.scala 32:12] + node _T_166 = bits(_T_152, 1, 1) @[CircuitMath.scala 30:8] + node _T_167 = mux(_T_164, UInt<2>("h02"), _T_166) @[CircuitMath.scala 32:10] + node _T_168 = mux(_T_162, UInt<2>("h03"), _T_167) @[CircuitMath.scala 32:10] + node _T_169 = mux(_T_154, _T_161, _T_168) @[CircuitMath.scala 38:21] + node _T_170 = cat(_T_154, _T_169) @[Cat.scala 30:58] + node _T_171 = bits(_T_148, 7, 4) @[CircuitMath.scala 35:17] + node _T_172 = bits(_T_148, 3, 0) @[CircuitMath.scala 36:17] + node _T_174 = neq(_T_171, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_175 = bits(_T_171, 3, 3) @[CircuitMath.scala 32:12] + node _T_177 = bits(_T_171, 2, 2) @[CircuitMath.scala 32:12] + node _T_179 = bits(_T_171, 1, 1) @[CircuitMath.scala 30:8] + node _T_180 = mux(_T_177, UInt<2>("h02"), _T_179) @[CircuitMath.scala 32:10] + node _T_181 = mux(_T_175, UInt<2>("h03"), _T_180) @[CircuitMath.scala 32:10] + node _T_182 = bits(_T_172, 3, 3) @[CircuitMath.scala 32:12] + node _T_184 = bits(_T_172, 2, 2) @[CircuitMath.scala 32:12] + node _T_186 = bits(_T_172, 1, 1) @[CircuitMath.scala 30:8] + node _T_187 = mux(_T_184, UInt<2>("h02"), _T_186) @[CircuitMath.scala 32:10] + node _T_188 = mux(_T_182, UInt<2>("h03"), _T_187) @[CircuitMath.scala 32:10] + node _T_189 = mux(_T_174, _T_181, _T_188) @[CircuitMath.scala 38:21] + node _T_190 = cat(_T_174, _T_189) @[Cat.scala 30:58] + node _T_191 = mux(_T_150, _T_170, _T_190) @[CircuitMath.scala 38:21] + node _T_192 = cat(_T_150, _T_191) @[Cat.scala 30:58] + node _T_193 = bits(_T_144, 15, 8) @[CircuitMath.scala 35:17] + node _T_194 = bits(_T_144, 7, 0) @[CircuitMath.scala 36:17] + node _T_196 = neq(_T_193, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_197 = bits(_T_193, 7, 4) @[CircuitMath.scala 35:17] + node _T_198 = bits(_T_193, 3, 0) @[CircuitMath.scala 36:17] + node _T_200 = neq(_T_197, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_201 = bits(_T_197, 3, 3) @[CircuitMath.scala 32:12] + node _T_203 = bits(_T_197, 2, 2) @[CircuitMath.scala 32:12] + node _T_205 = bits(_T_197, 1, 1) @[CircuitMath.scala 30:8] + node _T_206 = mux(_T_203, UInt<2>("h02"), _T_205) @[CircuitMath.scala 32:10] + node _T_207 = mux(_T_201, UInt<2>("h03"), _T_206) @[CircuitMath.scala 32:10] + node _T_208 = bits(_T_198, 3, 3) @[CircuitMath.scala 32:12] + node _T_210 = bits(_T_198, 2, 2) @[CircuitMath.scala 32:12] + node _T_212 = bits(_T_198, 1, 1) @[CircuitMath.scala 30:8] + node _T_213 = mux(_T_210, UInt<2>("h02"), _T_212) @[CircuitMath.scala 32:10] + node _T_214 = mux(_T_208, UInt<2>("h03"), _T_213) @[CircuitMath.scala 32:10] + node _T_215 = mux(_T_200, _T_207, _T_214) @[CircuitMath.scala 38:21] + node _T_216 = cat(_T_200, _T_215) @[Cat.scala 30:58] + node _T_217 = bits(_T_194, 7, 4) @[CircuitMath.scala 35:17] + node _T_218 = bits(_T_194, 3, 0) @[CircuitMath.scala 36:17] + node _T_220 = neq(_T_217, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_221 = bits(_T_217, 3, 3) @[CircuitMath.scala 32:12] + node _T_223 = bits(_T_217, 2, 2) @[CircuitMath.scala 32:12] + node _T_225 = bits(_T_217, 1, 1) @[CircuitMath.scala 30:8] + node _T_226 = mux(_T_223, UInt<2>("h02"), _T_225) @[CircuitMath.scala 32:10] + node _T_227 = mux(_T_221, UInt<2>("h03"), _T_226) @[CircuitMath.scala 32:10] + node _T_228 = bits(_T_218, 3, 3) @[CircuitMath.scala 32:12] + node _T_230 = bits(_T_218, 2, 2) @[CircuitMath.scala 32:12] + node _T_232 = bits(_T_218, 1, 1) @[CircuitMath.scala 30:8] + node _T_233 = mux(_T_230, UInt<2>("h02"), _T_232) @[CircuitMath.scala 32:10] + node _T_234 = mux(_T_228, UInt<2>("h03"), _T_233) @[CircuitMath.scala 32:10] + node _T_235 = mux(_T_220, _T_227, _T_234) @[CircuitMath.scala 38:21] + node _T_236 = cat(_T_220, _T_235) @[Cat.scala 30:58] + node _T_237 = mux(_T_196, _T_216, _T_236) @[CircuitMath.scala 38:21] + node _T_238 = cat(_T_196, _T_237) @[Cat.scala 30:58] + node _T_239 = mux(_T_146, _T_192, _T_238) @[CircuitMath.scala 38:21] + node _T_240 = cat(_T_146, _T_239) @[Cat.scala 30:58] + node _T_241 = mux(_T_89, _T_142, _T_240) @[CircuitMath.scala 38:21] + node _T_242 = cat(_T_89, _T_241) @[Cat.scala 30:58] + node _T_243 = sub(UInt<7>("h049"), _T_242) @[primitives.scala 79:25] + node _T_244 = asUInt(_T_243) @[primitives.scala 79:25] + node estNormNeg_dist = tail(_T_244, 1) @[primitives.scala 79:25] + node _T_245 = bits(sigSum, 33, 18) @[MulAddRecFN.scala 252:19] + node _T_247 = neq(_T_245, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] + node _T_248 = bits(sigSum, 17, 0) @[MulAddRecFN.scala 255:19] + node _T_250 = neq(_T_248, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] + node firstReduceSigSum = cat(_T_247, _T_250) @[Cat.scala 30:58] + node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] + node _T_251 = bits(complSigSum, 33, 18) @[MulAddRecFN.scala 259:24] + node _T_253 = neq(_T_251, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] + node _T_254 = bits(complSigSum, 17, 0) @[MulAddRecFN.scala 262:24] + node _T_256 = neq(_T_254, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] + node firstReduceComplSigSum = cat(_T_253, _T_256) @[Cat.scala 30:58] + node _T_257 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] + node _T_259 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] + node _T_260 = asUInt(_T_259) @[MulAddRecFN.scala 268:39] + node _T_261 = tail(_T_260, 1) @[MulAddRecFN.scala 268:39] + node _T_262 = bits(_T_261, 4, 0) @[MulAddRecFN.scala 268:49] + node CDom_estNormDist = mux(_T_257, io.fromPreMul.CAlignDist, _T_262) @[MulAddRecFN.scala 266:12] + node _T_264 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] + node _T_265 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 271:46] + node _T_267 = eq(_T_265, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] + node _T_268 = and(_T_264, _T_267) @[MulAddRecFN.scala 271:25] + node _T_269 = bits(sigSum, 74, 34) @[MulAddRecFN.scala 272:23] + node _T_271 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] + node _T_272 = cat(_T_269, _T_271) @[Cat.scala 30:58] + node _T_274 = mux(_T_268, _T_272, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] + node _T_276 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] + node _T_277 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 277:44] + node _T_278 = and(_T_276, _T_277) @[MulAddRecFN.scala 277:25] + node _T_279 = bits(sigSum, 58, 18) @[MulAddRecFN.scala 278:23] + node _T_280 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] + node _T_281 = cat(_T_279, _T_280) @[Cat.scala 30:58] + node _T_283 = mux(_T_278, _T_281, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] + node _T_284 = or(_T_274, _T_283) @[MulAddRecFN.scala 276:11] + node _T_285 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 286:44] + node _T_287 = eq(_T_285, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] + node _T_288 = and(doSubMags, _T_287) @[MulAddRecFN.scala 286:23] + node _T_289 = bits(complSigSum, 74, 34) @[MulAddRecFN.scala 287:28] + node _T_291 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] + node _T_292 = cat(_T_289, _T_291) @[Cat.scala 30:58] + node _T_294 = mux(_T_288, _T_292, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] + node _T_295 = or(_T_284, _T_294) @[MulAddRecFN.scala 285:11] + node _T_296 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 292:42] + node _T_297 = and(doSubMags, _T_296) @[MulAddRecFN.scala 292:23] + node _T_298 = bits(complSigSum, 58, 18) @[MulAddRecFN.scala 293:28] + node _T_299 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] + node _T_300 = cat(_T_298, _T_299) @[Cat.scala 30:58] + node _T_302 = mux(_T_297, _T_300, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] + node CDom_firstNormAbsSigSum = or(_T_295, _T_302) @[MulAddRecFN.scala 291:11] + node _T_303 = bits(sigSum, 50, 18) @[MulAddRecFN.scala 308:23] + node _T_304 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] + node _T_306 = eq(_T_304, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] + node _T_307 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] + node _T_308 = mux(doSubMags, _T_306, _T_307) @[MulAddRecFN.scala 309:20] + node _T_309 = cat(_T_303, _T_308) @[Cat.scala 30:58] + node _T_310 = bits(sigSum, 42, 1) @[MulAddRecFN.scala 314:24] + node _T_311 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 338:28] + node _T_312 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 339:33] + node _T_313 = bits(sigSum, 26, 1) @[MulAddRecFN.scala 340:28] + node _T_314 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_317 = mux(_T_314, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 71:12] + node _T_318 = cat(_T_313, _T_317) @[Cat.scala 30:58] + node _T_319 = mux(_T_312, _T_318, _T_310) @[MulAddRecFN.scala 339:17] + node _T_320 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 345:33] + node _T_321 = bits(sigSum, 10, 1) @[MulAddRecFN.scala 347:28] + node _T_322 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_325 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_326 = cat(_T_321, _T_325) @[Cat.scala 30:58] + node _T_327 = mux(_T_320, _T_309, _T_326) @[MulAddRecFN.scala 345:17] + node notCDom_pos_firstNormAbsSigSum = mux(_T_311, _T_319, _T_327) @[MulAddRecFN.scala 338:12] + node _T_328 = bits(complSigSum, 49, 18) @[MulAddRecFN.scala 360:28] + node _T_329 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] + node _T_330 = cat(_T_328, _T_329) @[Cat.scala 30:58] + node _T_331 = bits(complSigSum, 42, 1) @[MulAddRecFN.scala 363:29] + node _T_332 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 379:28] + node _T_333 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 380:33] + node _T_334 = bits(complSigSum, 27, 1) @[MulAddRecFN.scala 381:29] + node _T_335 = shl(_T_334, 16) @[MulAddRecFN.scala 381:64] + node _T_336 = mux(_T_333, _T_335, _T_331) @[MulAddRecFN.scala 380:17] + node _T_337 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 385:33] + node _T_338 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 387:29] + node _T_339 = shl(_T_338, 32) @[MulAddRecFN.scala 387:64] + node _T_340 = mux(_T_337, _T_330, _T_339) @[MulAddRecFN.scala 385:17] + node notCDom_neg_cFirstNormAbsSigSum = mux(_T_332, _T_336, _T_340) @[MulAddRecFN.scala 379:12] + node notCDom_signSigSum = bits(sigSum, 51, 51) @[MulAddRecFN.scala 392:36] + node _T_342 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] + node _T_343 = and(doSubMags, _T_342) @[MulAddRecFN.scala 395:23] + node doNegSignSum = mux(io.fromPreMul.isCDominant, _T_343, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] + node _T_344 = mux(notCDom_signSigSum, estNormNeg_dist, estNormNeg_dist) @[MulAddRecFN.scala 401:16] + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, _T_344) @[MulAddRecFN.scala 399:12] + node _T_345 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] + node _T_346 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, _T_345, _T_346) @[MulAddRecFN.scala 407:12] + node _T_348 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] + node _T_350 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] + node _T_351 = and(_T_348, _T_350) @[MulAddRecFN.scala 418:37] + node doIncrSig = and(_T_351, doSubMags) @[MulAddRecFN.scala 418:61] + node estNormDist_5 = bits(estNormDist, 3, 0) @[MulAddRecFN.scala 419:36] + node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] + node _T_353 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) @[primitives.scala 68:52] + node _T_354 = bits(_T_353, 15, 1) @[primitives.scala 69:26] + node _T_355 = bits(_T_354, 7, 0) @[Bitwise.scala 108:18] + node _T_358 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_359 = xor(UInt<8>("h0ff"), _T_358) @[Bitwise.scala 101:21] + node _T_360 = shr(_T_355, 4) @[Bitwise.scala 102:21] + node _T_361 = and(_T_360, _T_359) @[Bitwise.scala 102:31] + node _T_362 = bits(_T_355, 3, 0) @[Bitwise.scala 102:46] + node _T_363 = shl(_T_362, 4) @[Bitwise.scala 102:65] + node _T_364 = not(_T_359) @[Bitwise.scala 102:77] + node _T_365 = and(_T_363, _T_364) @[Bitwise.scala 102:75] + node _T_366 = or(_T_361, _T_365) @[Bitwise.scala 102:39] + node _T_367 = bits(_T_359, 5, 0) @[Bitwise.scala 101:28] + node _T_368 = shl(_T_367, 2) @[Bitwise.scala 101:47] + node _T_369 = xor(_T_359, _T_368) @[Bitwise.scala 101:21] + node _T_370 = shr(_T_366, 2) @[Bitwise.scala 102:21] + node _T_371 = and(_T_370, _T_369) @[Bitwise.scala 102:31] + node _T_372 = bits(_T_366, 5, 0) @[Bitwise.scala 102:46] + node _T_373 = shl(_T_372, 2) @[Bitwise.scala 102:65] + node _T_374 = not(_T_369) @[Bitwise.scala 102:77] + node _T_375 = and(_T_373, _T_374) @[Bitwise.scala 102:75] + node _T_376 = or(_T_371, _T_375) @[Bitwise.scala 102:39] + node _T_377 = bits(_T_369, 6, 0) @[Bitwise.scala 101:28] + node _T_378 = shl(_T_377, 1) @[Bitwise.scala 101:47] + node _T_379 = xor(_T_369, _T_378) @[Bitwise.scala 101:21] + node _T_380 = shr(_T_376, 1) @[Bitwise.scala 102:21] + node _T_381 = and(_T_380, _T_379) @[Bitwise.scala 102:31] + node _T_382 = bits(_T_376, 6, 0) @[Bitwise.scala 102:46] + node _T_383 = shl(_T_382, 1) @[Bitwise.scala 102:65] + node _T_384 = not(_T_379) @[Bitwise.scala 102:77] + node _T_385 = and(_T_383, _T_384) @[Bitwise.scala 102:75] + node _T_386 = or(_T_381, _T_385) @[Bitwise.scala 102:39] + node _T_387 = bits(_T_354, 14, 8) @[Bitwise.scala 108:44] + node _T_388 = bits(_T_387, 3, 0) @[Bitwise.scala 108:18] + node _T_389 = bits(_T_388, 1, 0) @[Bitwise.scala 108:18] + node _T_390 = bits(_T_389, 0, 0) @[Bitwise.scala 108:18] + node _T_391 = bits(_T_389, 1, 1) @[Bitwise.scala 108:44] + node _T_392 = cat(_T_390, _T_391) @[Cat.scala 30:58] + node _T_393 = bits(_T_388, 3, 2) @[Bitwise.scala 108:44] + node _T_394 = bits(_T_393, 0, 0) @[Bitwise.scala 108:18] + node _T_395 = bits(_T_393, 1, 1) @[Bitwise.scala 108:44] + node _T_396 = cat(_T_394, _T_395) @[Cat.scala 30:58] + node _T_397 = cat(_T_392, _T_396) @[Cat.scala 30:58] + node _T_398 = bits(_T_387, 6, 4) @[Bitwise.scala 108:44] + node _T_399 = bits(_T_398, 1, 0) @[Bitwise.scala 108:18] + node _T_400 = bits(_T_399, 0, 0) @[Bitwise.scala 108:18] + node _T_401 = bits(_T_399, 1, 1) @[Bitwise.scala 108:44] + node _T_402 = cat(_T_400, _T_401) @[Cat.scala 30:58] + node _T_403 = bits(_T_398, 2, 2) @[Bitwise.scala 108:44] + node _T_404 = cat(_T_402, _T_403) @[Cat.scala 30:58] + node _T_405 = cat(_T_397, _T_404) @[Cat.scala 30:58] + node _T_406 = cat(_T_386, _T_405) @[Cat.scala 30:58] + node absSigSumExtraMask = cat(_T_406, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_408 = bits(cFirstNormAbsSigSum, 42, 1) @[MulAddRecFN.scala 424:32] + node _T_409 = dshr(_T_408, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] + node _T_410 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 427:39] + node _T_411 = not(_T_410) @[MulAddRecFN.scala 427:19] + node _T_412 = and(_T_411, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] + node _T_414 = eq(_T_412, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] + node _T_415 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 430:38] + node _T_416 = and(_T_415, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] + node _T_418 = neq(_T_416, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] + node _T_419 = mux(doIncrSig, _T_414, _T_418) @[MulAddRecFN.scala 426:16] + node _T_420 = cat(_T_409, _T_419) @[Cat.scala 30:58] + node sigX3 = bits(_T_420, 27, 0) @[MulAddRecFN.scala 434:10] + node _T_421 = bits(sigX3, 27, 26) @[MulAddRecFN.scala 436:29] + node sigX3Shift1 = eq(_T_421, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] + node _T_423 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] + node _T_424 = asUInt(_T_423) @[MulAddRecFN.scala 437:40] + node sExpX3 = tail(_T_424, 1) @[MulAddRecFN.scala 437:40] + node _T_425 = bits(sigX3, 27, 25) @[MulAddRecFN.scala 439:25] + node isZeroY = eq(_T_425, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] + node _T_427 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] + node signY = mux(isZeroY, signZeroNotEqOpSigns, _T_427) @[MulAddRecFN.scala 442:12] + node sExpX3_13 = bits(sExpX3, 9, 0) @[MulAddRecFN.scala 446:27] + node _T_428 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 448:34] + node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 71:15] + node _T_432 = mux(_T_429, UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 71:12] + node _T_433 = not(sExpX3_13) @[primitives.scala 50:21] + node _T_434 = bits(_T_433, 9, 9) @[primitives.scala 56:25] + node _T_435 = bits(_T_433, 8, 0) @[primitives.scala 57:26] + node _T_436 = bits(_T_435, 8, 8) @[primitives.scala 56:25] + node _T_437 = bits(_T_435, 7, 0) @[primitives.scala 57:26] + node _T_438 = bits(_T_437, 7, 7) @[primitives.scala 56:25] + node _T_439 = bits(_T_437, 6, 0) @[primitives.scala 57:26] + node _T_440 = bits(_T_439, 6, 6) @[primitives.scala 56:25] + node _T_441 = bits(_T_439, 5, 0) @[primitives.scala 57:26] + node _T_444 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_441) @[primitives.scala 68:52] + node _T_445 = bits(_T_444, 63, 43) @[primitives.scala 69:26] + node _T_446 = bits(_T_445, 15, 0) @[Bitwise.scala 108:18] + node _T_449 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_450 = xor(UInt<16>("h0ffff"), _T_449) @[Bitwise.scala 101:21] + node _T_451 = shr(_T_446, 8) @[Bitwise.scala 102:21] + node _T_452 = and(_T_451, _T_450) @[Bitwise.scala 102:31] + node _T_453 = bits(_T_446, 7, 0) @[Bitwise.scala 102:46] + node _T_454 = shl(_T_453, 8) @[Bitwise.scala 102:65] + node _T_455 = not(_T_450) @[Bitwise.scala 102:77] + node _T_456 = and(_T_454, _T_455) @[Bitwise.scala 102:75] + node _T_457 = or(_T_452, _T_456) @[Bitwise.scala 102:39] + node _T_458 = bits(_T_450, 11, 0) @[Bitwise.scala 101:28] + node _T_459 = shl(_T_458, 4) @[Bitwise.scala 101:47] + node _T_460 = xor(_T_450, _T_459) @[Bitwise.scala 101:21] + node _T_461 = shr(_T_457, 4) @[Bitwise.scala 102:21] + node _T_462 = and(_T_461, _T_460) @[Bitwise.scala 102:31] + node _T_463 = bits(_T_457, 11, 0) @[Bitwise.scala 102:46] + node _T_464 = shl(_T_463, 4) @[Bitwise.scala 102:65] + node _T_465 = not(_T_460) @[Bitwise.scala 102:77] + node _T_466 = and(_T_464, _T_465) @[Bitwise.scala 102:75] + node _T_467 = or(_T_462, _T_466) @[Bitwise.scala 102:39] + node _T_468 = bits(_T_460, 13, 0) @[Bitwise.scala 101:28] + node _T_469 = shl(_T_468, 2) @[Bitwise.scala 101:47] + node _T_470 = xor(_T_460, _T_469) @[Bitwise.scala 101:21] + node _T_471 = shr(_T_467, 2) @[Bitwise.scala 102:21] + node _T_472 = and(_T_471, _T_470) @[Bitwise.scala 102:31] + node _T_473 = bits(_T_467, 13, 0) @[Bitwise.scala 102:46] + node _T_474 = shl(_T_473, 2) @[Bitwise.scala 102:65] + node _T_475 = not(_T_470) @[Bitwise.scala 102:77] + node _T_476 = and(_T_474, _T_475) @[Bitwise.scala 102:75] + node _T_477 = or(_T_472, _T_476) @[Bitwise.scala 102:39] + node _T_478 = bits(_T_470, 14, 0) @[Bitwise.scala 101:28] + node _T_479 = shl(_T_478, 1) @[Bitwise.scala 101:47] + node _T_480 = xor(_T_470, _T_479) @[Bitwise.scala 101:21] + node _T_481 = shr(_T_477, 1) @[Bitwise.scala 102:21] + node _T_482 = and(_T_481, _T_480) @[Bitwise.scala 102:31] + node _T_483 = bits(_T_477, 14, 0) @[Bitwise.scala 102:46] + node _T_484 = shl(_T_483, 1) @[Bitwise.scala 102:65] + node _T_485 = not(_T_480) @[Bitwise.scala 102:77] + node _T_486 = and(_T_484, _T_485) @[Bitwise.scala 102:75] + node _T_487 = or(_T_482, _T_486) @[Bitwise.scala 102:39] + node _T_488 = bits(_T_445, 20, 16) @[Bitwise.scala 108:44] + node _T_489 = bits(_T_488, 3, 0) @[Bitwise.scala 108:18] + node _T_490 = bits(_T_489, 1, 0) @[Bitwise.scala 108:18] + node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 108:18] + node _T_492 = bits(_T_490, 1, 1) @[Bitwise.scala 108:44] + node _T_493 = cat(_T_491, _T_492) @[Cat.scala 30:58] + node _T_494 = bits(_T_489, 3, 2) @[Bitwise.scala 108:44] + node _T_495 = bits(_T_494, 0, 0) @[Bitwise.scala 108:18] + node _T_496 = bits(_T_494, 1, 1) @[Bitwise.scala 108:44] + node _T_497 = cat(_T_495, _T_496) @[Cat.scala 30:58] + node _T_498 = cat(_T_493, _T_497) @[Cat.scala 30:58] + node _T_499 = bits(_T_488, 4, 4) @[Bitwise.scala 108:44] + node _T_500 = cat(_T_498, _T_499) @[Cat.scala 30:58] + node _T_501 = cat(_T_487, _T_500) @[Cat.scala 30:58] + node _T_502 = not(_T_501) @[primitives.scala 65:36] + node _T_503 = mux(_T_440, UInt<1>("h00"), _T_502) @[primitives.scala 65:21] + node _T_504 = not(_T_503) @[primitives.scala 65:17] + node _T_506 = cat(_T_504, UInt<4>("h0f")) @[Cat.scala 30:58] + node _T_507 = bits(_T_439, 6, 6) @[primitives.scala 56:25] + node _T_508 = bits(_T_439, 5, 0) @[primitives.scala 57:26] + node _T_510 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_508) @[primitives.scala 68:52] + node _T_511 = bits(_T_510, 3, 0) @[primitives.scala 69:26] + node _T_512 = bits(_T_511, 1, 0) @[Bitwise.scala 108:18] + node _T_513 = bits(_T_512, 0, 0) @[Bitwise.scala 108:18] + node _T_514 = bits(_T_512, 1, 1) @[Bitwise.scala 108:44] + node _T_515 = cat(_T_513, _T_514) @[Cat.scala 30:58] + node _T_516 = bits(_T_511, 3, 2) @[Bitwise.scala 108:44] + node _T_517 = bits(_T_516, 0, 0) @[Bitwise.scala 108:18] + node _T_518 = bits(_T_516, 1, 1) @[Bitwise.scala 108:44] + node _T_519 = cat(_T_517, _T_518) @[Cat.scala 30:58] + node _T_520 = cat(_T_515, _T_519) @[Cat.scala 30:58] + node _T_522 = mux(_T_507, _T_520, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_523 = mux(_T_438, _T_506, _T_522) @[primitives.scala 61:20] + node _T_525 = mux(_T_436, _T_523, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_527 = mux(_T_434, _T_525, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_528 = bits(sigX3, 26, 26) @[MulAddRecFN.scala 450:26] + node _T_529 = or(_T_527, _T_528) @[MulAddRecFN.scala 449:75] + node _T_531 = cat(_T_529, UInt<2>("h03")) @[Cat.scala 30:58] + node roundMask = or(_T_432, _T_531) @[MulAddRecFN.scala 448:50] + node _T_532 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] + node _T_533 = not(_T_532) @[MulAddRecFN.scala 454:24] + node roundPosMask = and(_T_533, roundMask) @[MulAddRecFN.scala 454:40] + node _T_534 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] + node roundPosBit = neq(_T_534, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] + node _T_536 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] + node _T_537 = and(sigX3, _T_536) @[MulAddRecFN.scala 456:34] + node anyRoundExtra = neq(_T_537, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] + node _T_539 = not(sigX3) @[MulAddRecFN.scala 457:27] + node _T_540 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] + node _T_541 = and(_T_539, _T_540) @[MulAddRecFN.scala 457:34] + node allRoundExtra = eq(_T_541, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] + node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] + node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] + node _T_544 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] + node _T_545 = and(_T_544, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] + node _T_546 = and(_T_545, roundPosBit) @[MulAddRecFN.scala 462:51] + node _T_547 = and(_T_546, anyRoundExtra) @[MulAddRecFN.scala 463:60] + node _T_549 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] + node _T_550 = and(_T_549, roundDirectUp) @[MulAddRecFN.scala 464:22] + node _T_551 = and(_T_550, anyRound) @[MulAddRecFN.scala 464:49] + node _T_552 = or(_T_547, _T_551) @[MulAddRecFN.scala 463:78] + node _T_553 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] + node _T_554 = or(_T_552, _T_553) @[MulAddRecFN.scala 464:65] + node _T_555 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] + node _T_556 = and(_T_555, roundPosBit) @[MulAddRecFN.scala 466:49] + node _T_557 = or(_T_554, _T_556) @[MulAddRecFN.scala 465:65] + node _T_558 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] + node _T_560 = and(_T_558, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] + node roundUp = or(_T_557, _T_560) @[MulAddRecFN.scala 466:65] + node _T_562 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] + node _T_563 = and(roundingMode_nearest_even, _T_562) @[MulAddRecFN.scala 470:39] + node _T_564 = and(_T_563, allRoundExtra) @[MulAddRecFN.scala 470:56] + node _T_565 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] + node _T_567 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] + node _T_568 = and(_T_565, _T_567) @[MulAddRecFN.scala 471:56] + node roundEven = mux(doIncrSig, _T_564, _T_568) @[MulAddRecFN.scala 469:12] + node _T_570 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] + node inexactY = mux(doIncrSig, _T_570, anyRound) @[MulAddRecFN.scala 473:27] + node _T_571 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] + node _T_572 = shr(_T_571, 2) @[MulAddRecFN.scala 475:30] + node _T_574 = add(_T_572, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] + node _T_575 = tail(_T_574, 1) @[MulAddRecFN.scala 475:35] + node roundUp_sigY3 = bits(_T_575, 25, 0) @[MulAddRecFN.scala 475:45] + node _T_577 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] + node _T_579 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] + node _T_580 = and(_T_577, _T_579) @[MulAddRecFN.scala 477:23] + node _T_581 = not(roundMask) @[MulAddRecFN.scala 477:48] + node _T_582 = and(sigX3, _T_581) @[MulAddRecFN.scala 477:46] + node _T_583 = shr(_T_582, 2) @[MulAddRecFN.scala 477:59] + node _T_585 = mux(_T_580, _T_583, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] + node _T_587 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] + node _T_588 = or(_T_585, _T_587) @[MulAddRecFN.scala 477:79] + node _T_589 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] + node _T_590 = not(_T_589) @[MulAddRecFN.scala 479:53] + node _T_591 = and(roundUp_sigY3, _T_590) @[MulAddRecFN.scala 479:51] + node _T_593 = mux(roundEven, _T_591, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] + node sigY3 = or(_T_588, _T_593) @[MulAddRecFN.scala 478:79] + node _T_594 = bits(sigY3, 25, 25) @[MulAddRecFN.scala 482:18] + node _T_596 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] + node _T_597 = tail(_T_596, 1) @[MulAddRecFN.scala 482:41] + node _T_599 = mux(_T_594, _T_597, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] + node _T_600 = bits(sigY3, 24, 24) @[MulAddRecFN.scala 483:18] + node _T_602 = mux(_T_600, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] + node _T_603 = or(_T_599, _T_602) @[MulAddRecFN.scala 482:61] + node _T_604 = bits(sigY3, 25, 24) @[MulAddRecFN.scala 484:19] + node _T_606 = eq(_T_604, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] + node _T_608 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] + node _T_609 = asUInt(_T_608) @[MulAddRecFN.scala 485:20] + node _T_610 = tail(_T_609, 1) @[MulAddRecFN.scala 485:20] + node _T_612 = mux(_T_606, _T_610, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] + node sExpY = or(_T_603, _T_612) @[MulAddRecFN.scala 483:61] + node expY = bits(sExpY, 8, 0) @[MulAddRecFN.scala 488:21] + node _T_613 = bits(sigY3, 22, 0) @[MulAddRecFN.scala 490:31] + node _T_614 = bits(sigY3, 23, 1) @[MulAddRecFN.scala 490:55] + node fractY = mux(sigX3Shift1, _T_613, _T_614) @[MulAddRecFN.scala 490:12] + node _T_615 = bits(sExpY, 9, 7) @[MulAddRecFN.scala 492:27] + node overflowY = eq(_T_615, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] + node _T_618 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] + node _T_619 = bits(sExpY, 9, 9) @[MulAddRecFN.scala 496:19] + node _T_620 = bits(sExpY, 8, 0) @[MulAddRecFN.scala 496:43] + node _T_622 = lt(_T_620, UInt<7>("h06b")) @[MulAddRecFN.scala 496:57] + node _T_623 = or(_T_619, _T_622) @[MulAddRecFN.scala 496:34] + node totalUnderflowY = and(_T_618, _T_623) @[MulAddRecFN.scala 495:19] + node _T_624 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 499:20] + node _T_627 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) @[MulAddRecFN.scala 501:26] + node _T_628 = leq(sExpX3_13, _T_627) @[MulAddRecFN.scala 500:29] + node _T_629 = or(_T_624, _T_628) @[MulAddRecFN.scala 499:35] + node underflowY = and(inexactY, _T_629) @[MulAddRecFN.scala 498:22] + node _T_630 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] + node _T_632 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] + node _T_633 = and(roundingMode_max, _T_632) @[MulAddRecFN.scala 506:58] + node roundMagUp = or(_T_630, _T_633) @[MulAddRecFN.scala 506:37] + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] + node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] + node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] + node _T_635 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] + node _T_637 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] + node commonCase = and(_T_635, _T_637) @[MulAddRecFN.scala 514:35] + node _T_638 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] + node _T_639 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] + node _T_640 = or(_T_638, _T_639) @[MulAddRecFN.scala 517:29] + node _T_642 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] + node _T_644 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] + node _T_645 = and(_T_642, _T_644) @[MulAddRecFN.scala 518:23] + node _T_646 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] + node _T_647 = and(_T_645, _T_646) @[MulAddRecFN.scala 518:35] + node _T_648 = and(_T_647, isInfC) @[MulAddRecFN.scala 518:57] + node _T_649 = and(_T_648, doSubMags) @[MulAddRecFN.scala 518:67] + node notSigNaN_invalid = or(_T_640, _T_649) @[MulAddRecFN.scala 517:52] + node _T_650 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] + node _T_651 = or(_T_650, isSigNaNC) @[MulAddRecFN.scala 519:42] + node invalid = or(_T_651, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] + node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] + node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] + node _T_652 = and(commonCase, inexactY) @[MulAddRecFN.scala 522:43] + node inexact = or(overflow, _T_652) @[MulAddRecFN.scala 522:28] + node _T_653 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] + node notSpecial_isZeroOut = or(_T_653, totalUnderflowY) @[MulAddRecFN.scala 525:40] + node _T_654 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] + node pegMinFiniteMagOut = and(_T_654, roundMagUp) @[MulAddRecFN.scala 526:60] + node _T_656 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] + node pegMaxFiniteMagOut = and(overflow, _T_656) @[MulAddRecFN.scala 527:39] + node _T_657 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] + node _T_658 = or(_T_657, isInfC) @[MulAddRecFN.scala 529:26] + node _T_659 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] + node notNaN_isInfOut = or(_T_658, _T_659) @[MulAddRecFN.scala 529:36] + node _T_660 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] + node _T_661 = or(_T_660, isNaNC) @[MulAddRecFN.scala 530:37] + node isNaNOut = or(_T_661, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] + node _T_663 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] + node _T_664 = and(_T_663, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] + node _T_666 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] + node _T_667 = and(mulSpecial, _T_666) @[MulAddRecFN.scala 534:21] + node _T_668 = and(_T_667, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] + node _T_669 = or(_T_664, _T_668) @[MulAddRecFN.scala 533:78] + node _T_671 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] + node _T_672 = and(_T_671, isSpecialC) @[MulAddRecFN.scala 535:23] + node _T_673 = and(_T_672, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] + node _T_674 = or(_T_669, _T_673) @[MulAddRecFN.scala 534:78] + node _T_676 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] + node _T_677 = and(_T_676, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] + node _T_678 = and(_T_677, doSubMags) @[MulAddRecFN.scala 536:46] + node _T_679 = and(_T_678, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] + node uncommonCaseSignOut = or(_T_674, _T_679) @[MulAddRecFN.scala 535:78] + node _T_681 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] + node _T_682 = and(_T_681, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] + node _T_683 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] + node signOut = or(_T_682, _T_683) @[MulAddRecFN.scala 538:55] + node _T_686 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 541:18] + node _T_687 = not(_T_686) @[MulAddRecFN.scala 541:14] + node _T_688 = and(expY, _T_687) @[MulAddRecFN.scala 540:15] + node _T_690 = not(UInt<9>("h06b")) @[MulAddRecFN.scala 546:19] + node _T_692 = mux(pegMinFiniteMagOut, _T_690, UInt<9>("h00")) @[MulAddRecFN.scala 545:18] + node _T_693 = not(_T_692) @[MulAddRecFN.scala 545:14] + node _T_694 = and(_T_688, _T_693) @[MulAddRecFN.scala 544:17] + node _T_697 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) @[MulAddRecFN.scala 549:18] + node _T_698 = not(_T_697) @[MulAddRecFN.scala 549:14] + node _T_699 = and(_T_694, _T_698) @[MulAddRecFN.scala 548:17] + node _T_702 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) @[MulAddRecFN.scala 553:18] + node _T_703 = not(_T_702) @[MulAddRecFN.scala 553:14] + node _T_704 = and(_T_699, _T_703) @[MulAddRecFN.scala 552:17] + node _T_707 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) @[MulAddRecFN.scala 557:16] + node _T_708 = or(_T_704, _T_707) @[MulAddRecFN.scala 556:18] + node _T_711 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) @[MulAddRecFN.scala 558:16] + node _T_712 = or(_T_708, _T_711) @[MulAddRecFN.scala 557:74] + node _T_715 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) @[MulAddRecFN.scala 562:16] + node _T_716 = or(_T_712, _T_715) @[MulAddRecFN.scala 561:15] + node _T_719 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 566:16] + node expOut = or(_T_716, _T_719) @[MulAddRecFN.scala 565:15] + node _T_720 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] + node _T_721 = or(_T_720, isNaNOut) @[MulAddRecFN.scala 568:45] + node _T_723 = shl(UInt<1>("h01"), 22) @[MulAddRecFN.scala 569:34] + node _T_725 = mux(isNaNOut, _T_723, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] + node _T_726 = mux(_T_721, _T_725, fractY) @[MulAddRecFN.scala 568:12] + node _T_727 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_730 = mux(_T_727, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_726, _T_730) @[MulAddRecFN.scala 571:11] + node _T_731 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_732 = cat(_T_731, fractOut) @[Cat.scala 30:58] + io.out <= _T_732 @[MulAddRecFN.scala 574:12] + node _T_734 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_735 = cat(invalid, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_736 = cat(_T_735, overflow) @[Cat.scala 30:58] + node _T_737 = cat(_T_736, _T_734) @[Cat.scala 30:58] + io.exceptionFlags <= _T_737 @[MulAddRecFN.scala 575:23] + + module MulAddRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst mulAddRecFN_preMul of MulAddRecFN_preMul @[MulAddRecFN.scala 598:15] + mulAddRecFN_preMul.io is invalid + mulAddRecFN_preMul.clock <= clock + mulAddRecFN_preMul.reset <= reset + inst mulAddRecFN_postMul of MulAddRecFN_postMul @[MulAddRecFN.scala 600:15] + mulAddRecFN_postMul.io is invalid + mulAddRecFN_postMul.clock <= clock + mulAddRecFN_postMul.reset <= reset + mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] + mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] + mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] + mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] + node _T_16 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] + node _T_18 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 30:58] + node _T_19 = add(_T_16, _T_18) @[MulAddRecFN.scala 610:71] + node _T_20 = tail(_T_19, 1) @[MulAddRecFN.scala 610:71] + mulAddRecFN_postMul.io.mulAddResult <= _T_20 @[MulAddRecFN.scala 609:41] + io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] + + module FPUFMAPipe : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + node one = shl(UInt<1>("h01"), 31) @[FPU.scala 479:21] + node _T_131 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 480:29] + node _T_132 = bits(io.in.bits.in2, 32, 32) @[FPU.scala 480:53] + node _T_133 = xor(_T_131, _T_132) @[FPU.scala 480:37] + node zero = shl(_T_133, 32) @[FPU.scala 480:62] + reg valid : UInt<1>, clock @[FPU.scala 482:18] + valid <= io.in.valid @[FPU.scala 482:18] + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 483:15] + when io.in.valid : @[FPU.scala 484:22] + in <- io.in.bits @[FPU.scala 485:8] + node _T_177 = bits(io.in.bits.cmd, 1, 1) @[FPU.scala 488:33] + node _T_178 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 488:48] + node _T_179 = and(_T_177, _T_178) @[FPU.scala 488:37] + node _T_180 = bits(io.in.bits.cmd, 0, 0) @[FPU.scala 488:78] + node _T_181 = cat(_T_179, _T_180) @[Cat.scala 30:58] + in.cmd <= _T_181 @[FPU.scala 488:12] + when io.in.bits.swap23 : @[FPU.scala 489:23] + in.in2 <= one @[FPU.scala 489:32] + skip @[FPU.scala 489:23] + node _T_182 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 490:21] + node _T_184 = eq(_T_182, UInt<1>("h00")) @[Conditional.scala 19:11] + when _T_184 : @[Conditional.scala 19:15] + in.in3 <= zero @[FPU.scala 490:45] + skip @[Conditional.scala 19:15] + skip @[FPU.scala 484:22] + inst fma of MulAddRecFN @[FPU.scala 493:19] + fma.io is invalid + fma.clock <= clock + fma.reset <= reset + fma.io.op <= in.cmd @[FPU.scala 494:13] + fma.io.roundingMode <= in.rm @[FPU.scala 495:23] + fma.io.a <= in.in1 @[FPU.scala 496:12] + fma.io.b <= in.in2 @[FPU.scala 497:12] + fma.io.c <= in.in3 @[FPU.scala 498:12] + wire res : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 500:17] + res is invalid @[FPU.scala 500:17] + res.data <= fma.io.out @[FPU.scala 501:12] + res.exc <= fma.io.exceptionFlags @[FPU.scala 502:11] + reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_192 <= valid @[Valid.scala 47:18] + reg _T_196 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_196 <- res @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_201 <= _T_192 @[Valid.scala 47:18] + reg _T_205 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_192 : @[Reg.scala 35:19] + _T_205 <- _T_196 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_217 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_217 is invalid @[Valid.scala 42:21] + _T_217.valid <= _T_201 @[Valid.scala 43:17] + _T_217.bits <- _T_205 @[Valid.scala 44:16] + io.out <- _T_217 @[FPU.scala 503:10] + + module CompareRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_16 = bits(io.a, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_17 = bits(_T_16, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_19 = eq(_T_17, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_20 = bits(_T_16, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_22 = eq(_T_20, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + rawA is invalid @[rawFNFromRecFN.scala 54:23] + node _T_36 = bits(io.a, 64, 64) @[rawFNFromRecFN.scala 55:23] + rawA.sign <= _T_36 @[rawFNFromRecFN.scala 55:18] + node _T_37 = bits(_T_16, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_38 = and(_T_22, _T_37) @[rawFNFromRecFN.scala 56:32] + rawA.isNaN <= _T_38 @[rawFNFromRecFN.scala 56:19] + node _T_39 = bits(_T_16, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_41 = eq(_T_39, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_42 = and(_T_22, _T_41) @[rawFNFromRecFN.scala 57:32] + rawA.isInf <= _T_42 @[rawFNFromRecFN.scala 57:19] + rawA.isZero <= _T_19 @[rawFNFromRecFN.scala 58:20] + node _T_43 = cvt(_T_16) @[rawFNFromRecFN.scala 59:25] + rawA.sExp <= _T_43 @[rawFNFromRecFN.scala 59:18] + node _T_46 = eq(_T_19, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_47 = bits(io.a, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_49 = cat(_T_47, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_50 = cat(UInt<1>("h00"), _T_46) @[Cat.scala 30:58] + node _T_51 = cat(_T_50, _T_49) @[Cat.scala 30:58] + rawA.sig <= _T_51 @[rawFNFromRecFN.scala 60:17] + node _T_52 = bits(io.b, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_53 = bits(_T_52, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_55 = eq(_T_53, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_56 = bits(_T_52, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_58 = eq(_T_56, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + rawB is invalid @[rawFNFromRecFN.scala 54:23] + node _T_72 = bits(io.b, 64, 64) @[rawFNFromRecFN.scala 55:23] + rawB.sign <= _T_72 @[rawFNFromRecFN.scala 55:18] + node _T_73 = bits(_T_52, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_74 = and(_T_58, _T_73) @[rawFNFromRecFN.scala 56:32] + rawB.isNaN <= _T_74 @[rawFNFromRecFN.scala 56:19] + node _T_75 = bits(_T_52, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_77 = eq(_T_75, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_78 = and(_T_58, _T_77) @[rawFNFromRecFN.scala 57:32] + rawB.isInf <= _T_78 @[rawFNFromRecFN.scala 57:19] + rawB.isZero <= _T_55 @[rawFNFromRecFN.scala 58:20] + node _T_79 = cvt(_T_52) @[rawFNFromRecFN.scala 59:25] + rawB.sExp <= _T_79 @[rawFNFromRecFN.scala 59:18] + node _T_82 = eq(_T_55, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_83 = bits(io.b, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_85 = cat(_T_83, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_86 = cat(UInt<1>("h00"), _T_82) @[Cat.scala 30:58] + node _T_87 = cat(_T_86, _T_85) @[Cat.scala 30:58] + rawB.sig <= _T_87 @[rawFNFromRecFN.scala 60:17] + node _T_89 = eq(rawA.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:19] + node _T_91 = eq(rawB.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:35] + node ordered = and(_T_89, _T_91) @[CompareRecFN.scala 57:32] + node bothInfs = and(rawA.isInf, rawB.isInf) @[CompareRecFN.scala 58:33] + node bothZeros = and(rawA.isZero, rawB.isZero) @[CompareRecFN.scala 59:33] + node eqExps = eq(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 60:29] + node _T_92 = lt(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 62:20] + node _T_93 = lt(rawA.sig, rawB.sig) @[CompareRecFN.scala 62:57] + node _T_94 = and(eqExps, _T_93) @[CompareRecFN.scala 62:44] + node common_ltMags = or(_T_92, _T_94) @[CompareRecFN.scala 62:33] + node _T_95 = eq(rawA.sig, rawB.sig) @[CompareRecFN.scala 63:45] + node common_eqMags = and(eqExps, _T_95) @[CompareRecFN.scala 63:32] + node _T_97 = eq(bothZeros, UInt<1>("h00")) @[CompareRecFN.scala 66:9] + node _T_99 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 67:28] + node _T_100 = and(rawA.sign, _T_99) @[CompareRecFN.scala 67:25] + node _T_102 = eq(bothInfs, UInt<1>("h00")) @[CompareRecFN.scala 68:19] + node _T_104 = eq(common_ltMags, UInt<1>("h00")) @[CompareRecFN.scala 69:38] + node _T_105 = and(rawA.sign, _T_104) @[CompareRecFN.scala 69:35] + node _T_107 = eq(common_eqMags, UInt<1>("h00")) @[CompareRecFN.scala 69:57] + node _T_108 = and(_T_105, _T_107) @[CompareRecFN.scala 69:54] + node _T_110 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 70:29] + node _T_111 = and(_T_110, common_ltMags) @[CompareRecFN.scala 70:41] + node _T_112 = or(_T_108, _T_111) @[CompareRecFN.scala 69:74] + node _T_113 = and(_T_102, _T_112) @[CompareRecFN.scala 68:30] + node _T_114 = or(_T_100, _T_113) @[CompareRecFN.scala 67:41] + node ordered_lt = and(_T_97, _T_114) @[CompareRecFN.scala 66:21] + node _T_115 = eq(rawA.sign, rawB.sign) @[CompareRecFN.scala 72:34] + node _T_116 = or(bothInfs, common_eqMags) @[CompareRecFN.scala 72:62] + node _T_117 = and(_T_115, _T_116) @[CompareRecFN.scala 72:49] + node ordered_eq = or(bothZeros, _T_117) @[CompareRecFN.scala 72:19] + node _T_118 = bits(rawA.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_120 = eq(_T_118, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node _T_121 = and(rawA.isNaN, _T_120) @[RoundRawFNToRecFN.scala 61:46] + node _T_122 = bits(rawB.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_124 = eq(_T_122, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node _T_125 = and(rawB.isNaN, _T_124) @[RoundRawFNToRecFN.scala 61:46] + node _T_126 = or(_T_121, _T_125) @[CompareRecFN.scala 75:29] + node _T_128 = eq(ordered, UInt<1>("h00")) @[CompareRecFN.scala 76:30] + node _T_129 = and(io.signaling, _T_128) @[CompareRecFN.scala 76:27] + node invalid = or(_T_126, _T_129) @[CompareRecFN.scala 75:52] + node _T_130 = and(ordered, ordered_lt) @[CompareRecFN.scala 78:22] + io.lt <= _T_130 @[CompareRecFN.scala 78:11] + node _T_131 = and(ordered, ordered_eq) @[CompareRecFN.scala 79:22] + io.eq <= _T_131 @[CompareRecFN.scala 79:11] + node _T_133 = eq(ordered_lt, UInt<1>("h00")) @[CompareRecFN.scala 80:25] + node _T_134 = and(ordered, _T_133) @[CompareRecFN.scala 80:22] + node _T_136 = eq(ordered_eq, UInt<1>("h00")) @[CompareRecFN.scala 80:41] + node _T_137 = and(_T_134, _T_136) @[CompareRecFN.scala 80:38] + io.gt <= _T_137 @[CompareRecFN.scala 80:11] + node _T_139 = cat(invalid, UInt<4>("h00")) @[Cat.scala 30:58] + io.exceptionFlags <= _T_139 @[CompareRecFN.scala 82:23] + + module RecFNToIN : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} + + io is invalid + io is invalid + node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] + node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] + node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] + node _T_12 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] + node isZero = eq(_T_12, UInt<1>("h00")) @[RecFNToIN.scala 58:47] + node _T_14 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] + node invalid = eq(_T_14, UInt<2>("h03")) @[RecFNToIN.scala 59:50] + node _T_16 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] + node isNaN = and(invalid, _T_16) @[RecFNToIN.scala 60:27] + node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] + node _T_17 = cat(notSpecial_magGeOne, fract) @[Cat.scala 30:58] + node _T_18 = bits(exp, 4, 0) @[RecFNToIN.scala 74:20] + node _T_20 = mux(notSpecial_magGeOne, _T_18, UInt<1>("h00")) @[RecFNToIN.scala 73:16] + node shiftedSig = dshl(_T_17, _T_20) @[RecFNToIN.scala 72:40] + node unroundedInt = bits(shiftedSig, 83, 52) @[RecFNToIN.scala 82:24] + node _T_21 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] + node _T_22 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] + node _T_24 = neq(_T_22, UInt<1>("h00")) @[RecFNToIN.scala 86:41] + node roundBits = cat(_T_21, _T_24) @[Cat.scala 30:58] + node _T_25 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] + node _T_27 = neq(_T_25, UInt<1>("h00")) @[RecFNToIN.scala 88:65] + node _T_29 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] + node roundInexact = mux(notSpecial_magGeOne, _T_27, _T_29) @[RecFNToIN.scala 88:27] + node _T_30 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] + node _T_31 = not(_T_30) @[RecFNToIN.scala 91:29] + node _T_33 = eq(_T_31, UInt<1>("h00")) @[RecFNToIN.scala 91:29] + node _T_34 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] + node _T_35 = not(_T_34) @[RecFNToIN.scala 91:53] + node _T_37 = eq(_T_35, UInt<1>("h00")) @[RecFNToIN.scala 91:53] + node _T_38 = or(_T_33, _T_37) @[RecFNToIN.scala 91:34] + node _T_39 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] + node _T_40 = not(_T_39) @[RecFNToIN.scala 92:38] + node _T_42 = eq(_T_40, UInt<1>("h00")) @[RecFNToIN.scala 92:38] + node _T_43 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] + node _T_45 = neq(_T_43, UInt<1>("h00")) @[RecFNToIN.scala 92:60] + node _T_47 = mux(_T_42, _T_45, UInt<1>("h00")) @[RecFNToIN.scala 92:16] + node roundIncr_nearestEven = mux(notSpecial_magGeOne, _T_38, _T_47) @[RecFNToIN.scala 90:12] + node _T_48 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] + node _T_49 = and(_T_48, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] + node _T_50 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] + node _T_51 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] + node _T_52 = and(_T_50, _T_51) @[RecFNToIN.scala 96:49] + node _T_53 = or(_T_49, _T_52) @[RecFNToIN.scala 95:78] + node _T_54 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] + node _T_56 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] + node _T_57 = and(_T_56, roundInexact) @[RecFNToIN.scala 97:60] + node _T_58 = and(_T_54, _T_57) @[RecFNToIN.scala 97:49] + node roundIncr = or(_T_53, _T_58) @[RecFNToIN.scala 96:78] + node _T_59 = not(unroundedInt) @[RecFNToIN.scala 98:39] + node complUnroundedInt = mux(sign, _T_59, unroundedInt) @[RecFNToIN.scala 98:32] + node _T_60 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] + node _T_62 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] + node _T_63 = tail(_T_62, 1) @[RecFNToIN.scala 100:49] + node roundedInt = mux(_T_60, _T_63, complUnroundedInt) @[RecFNToIN.scala 100:12] + node _T_64 = bits(unroundedInt, 29, 0) @[RecFNToIN.scala 103:38] + node _T_65 = not(_T_64) @[RecFNToIN.scala 103:56] + node _T_67 = eq(_T_65, UInt<1>("h00")) @[RecFNToIN.scala 103:56] + node roundCarryBut2 = and(_T_67, roundIncr) @[RecFNToIN.scala 103:61] + node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] + node _T_69 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 108:21] + node _T_71 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 109:26] + node _T_73 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] + node _T_74 = bits(unroundedInt, 30, 0) @[RecFNToIN.scala 110:45] + node _T_76 = neq(_T_74, UInt<1>("h00")) @[RecFNToIN.scala 110:63] + node _T_77 = or(_T_73, _T_76) @[RecFNToIN.scala 110:30] + node _T_78 = or(_T_77, roundIncr) @[RecFNToIN.scala 111:27] + node _T_79 = and(_T_71, _T_78) @[RecFNToIN.scala 109:50] + node _T_80 = or(_T_69, _T_79) @[RecFNToIN.scala 108:40] + node _T_82 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] + node _T_84 = eq(posExp, UInt<5>("h01e")) @[RecFNToIN.scala 112:36] + node _T_85 = and(_T_82, _T_84) @[RecFNToIN.scala 112:25] + node _T_86 = and(_T_85, roundCarryBut2) @[RecFNToIN.scala 112:60] + node _T_87 = or(_T_80, _T_86) @[RecFNToIN.scala 111:42] + node overflow_signed = mux(notSpecial_magGeOne, _T_87, UInt<1>("h00")) @[RecFNToIN.scala 107:12] + node _T_90 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 117:29] + node _T_91 = or(sign, _T_90) @[RecFNToIN.scala 117:18] + node _T_93 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 118:26] + node _T_94 = bits(unroundedInt, 30, 30) @[RecFNToIN.scala 119:34] + node _T_95 = and(_T_93, _T_94) @[RecFNToIN.scala 118:50] + node _T_96 = and(_T_95, roundCarryBut2) @[RecFNToIN.scala 119:49] + node _T_97 = or(_T_91, _T_96) @[RecFNToIN.scala 117:48] + node _T_98 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] + node overflow_unsigned = mux(notSpecial_magGeOne, _T_97, _T_98) @[RecFNToIN.scala 116:12] + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] + node _T_100 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] + node excSign = and(sign, _T_100) @[RecFNToIN.scala 124:24] + node _T_101 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] + node _T_103 = shl(UInt<1>("h01"), 31) @[RecFNToIN.scala 126:45] + node _T_105 = mux(_T_101, _T_103, UInt<1>("h00")) @[RecFNToIN.scala 126:12] + node _T_107 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] + node _T_108 = and(io.signedOut, _T_107) @[RecFNToIN.scala 127:26] + node _T_111 = mux(_T_108, UInt<31>("h07fffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] + node _T_112 = or(_T_105, _T_111) @[RecFNToIN.scala 126:72] + node _T_114 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] + node _T_116 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] + node _T_117 = and(_T_114, _T_116) @[RecFNToIN.scala 131:28] + node _T_120 = mux(_T_117, UInt<32>("h0ffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] + node excValue = or(_T_112, _T_120) @[RecFNToIN.scala 130:11] + node _T_122 = eq(invalid, UInt<1>("h00")) @[RecFNToIN.scala 135:35] + node _T_123 = and(roundInexact, _T_122) @[RecFNToIN.scala 135:32] + node _T_125 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] + node inexact = and(_T_123, _T_125) @[RecFNToIN.scala 135:45] + node _T_126 = or(invalid, overflow) @[RecFNToIN.scala 137:27] + node _T_127 = mux(_T_126, excValue, roundedInt) @[RecFNToIN.scala 137:18] + io.out <= _T_127 @[RecFNToIN.scala 137:12] + node _T_128 = cat(invalid, overflow) @[Cat.scala 30:58] + node _T_129 = cat(_T_128, inexact) @[Cat.scala 30:58] + io.intExceptionFlags <= _T_129 @[RecFNToIN.scala 138:26] + + module RecFNToIN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} + + io is invalid + io is invalid + node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] + node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] + node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] + node _T_12 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] + node isZero = eq(_T_12, UInt<1>("h00")) @[RecFNToIN.scala 58:47] + node _T_14 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] + node invalid = eq(_T_14, UInt<2>("h03")) @[RecFNToIN.scala 59:50] + node _T_16 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] + node isNaN = and(invalid, _T_16) @[RecFNToIN.scala 60:27] + node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] + node _T_17 = cat(notSpecial_magGeOne, fract) @[Cat.scala 30:58] + node _T_18 = bits(exp, 5, 0) @[RecFNToIN.scala 74:20] + node _T_20 = mux(notSpecial_magGeOne, _T_18, UInt<1>("h00")) @[RecFNToIN.scala 73:16] + node shiftedSig = dshl(_T_17, _T_20) @[RecFNToIN.scala 72:40] + node unroundedInt = bits(shiftedSig, 115, 52) @[RecFNToIN.scala 82:24] + node _T_21 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] + node _T_22 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] + node _T_24 = neq(_T_22, UInt<1>("h00")) @[RecFNToIN.scala 86:41] + node roundBits = cat(_T_21, _T_24) @[Cat.scala 30:58] + node _T_25 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] + node _T_27 = neq(_T_25, UInt<1>("h00")) @[RecFNToIN.scala 88:65] + node _T_29 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] + node roundInexact = mux(notSpecial_magGeOne, _T_27, _T_29) @[RecFNToIN.scala 88:27] + node _T_30 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] + node _T_31 = not(_T_30) @[RecFNToIN.scala 91:29] + node _T_33 = eq(_T_31, UInt<1>("h00")) @[RecFNToIN.scala 91:29] + node _T_34 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] + node _T_35 = not(_T_34) @[RecFNToIN.scala 91:53] + node _T_37 = eq(_T_35, UInt<1>("h00")) @[RecFNToIN.scala 91:53] + node _T_38 = or(_T_33, _T_37) @[RecFNToIN.scala 91:34] + node _T_39 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] + node _T_40 = not(_T_39) @[RecFNToIN.scala 92:38] + node _T_42 = eq(_T_40, UInt<1>("h00")) @[RecFNToIN.scala 92:38] + node _T_43 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] + node _T_45 = neq(_T_43, UInt<1>("h00")) @[RecFNToIN.scala 92:60] + node _T_47 = mux(_T_42, _T_45, UInt<1>("h00")) @[RecFNToIN.scala 92:16] + node roundIncr_nearestEven = mux(notSpecial_magGeOne, _T_38, _T_47) @[RecFNToIN.scala 90:12] + node _T_48 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] + node _T_49 = and(_T_48, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] + node _T_50 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] + node _T_51 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] + node _T_52 = and(_T_50, _T_51) @[RecFNToIN.scala 96:49] + node _T_53 = or(_T_49, _T_52) @[RecFNToIN.scala 95:78] + node _T_54 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] + node _T_56 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] + node _T_57 = and(_T_56, roundInexact) @[RecFNToIN.scala 97:60] + node _T_58 = and(_T_54, _T_57) @[RecFNToIN.scala 97:49] + node roundIncr = or(_T_53, _T_58) @[RecFNToIN.scala 96:78] + node _T_59 = not(unroundedInt) @[RecFNToIN.scala 98:39] + node complUnroundedInt = mux(sign, _T_59, unroundedInt) @[RecFNToIN.scala 98:32] + node _T_60 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] + node _T_62 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] + node _T_63 = tail(_T_62, 1) @[RecFNToIN.scala 100:49] + node roundedInt = mux(_T_60, _T_63, complUnroundedInt) @[RecFNToIN.scala 100:12] + node _T_64 = bits(unroundedInt, 61, 0) @[RecFNToIN.scala 103:38] + node _T_65 = not(_T_64) @[RecFNToIN.scala 103:56] + node _T_67 = eq(_T_65, UInt<1>("h00")) @[RecFNToIN.scala 103:56] + node roundCarryBut2 = and(_T_67, roundIncr) @[RecFNToIN.scala 103:61] + node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] + node _T_69 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 108:21] + node _T_71 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 109:26] + node _T_73 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] + node _T_74 = bits(unroundedInt, 62, 0) @[RecFNToIN.scala 110:45] + node _T_76 = neq(_T_74, UInt<1>("h00")) @[RecFNToIN.scala 110:63] + node _T_77 = or(_T_73, _T_76) @[RecFNToIN.scala 110:30] + node _T_78 = or(_T_77, roundIncr) @[RecFNToIN.scala 111:27] + node _T_79 = and(_T_71, _T_78) @[RecFNToIN.scala 109:50] + node _T_80 = or(_T_69, _T_79) @[RecFNToIN.scala 108:40] + node _T_82 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] + node _T_84 = eq(posExp, UInt<6>("h03e")) @[RecFNToIN.scala 112:36] + node _T_85 = and(_T_82, _T_84) @[RecFNToIN.scala 112:25] + node _T_86 = and(_T_85, roundCarryBut2) @[RecFNToIN.scala 112:60] + node _T_87 = or(_T_80, _T_86) @[RecFNToIN.scala 111:42] + node overflow_signed = mux(notSpecial_magGeOne, _T_87, UInt<1>("h00")) @[RecFNToIN.scala 107:12] + node _T_90 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 117:29] + node _T_91 = or(sign, _T_90) @[RecFNToIN.scala 117:18] + node _T_93 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 118:26] + node _T_94 = bits(unroundedInt, 62, 62) @[RecFNToIN.scala 119:34] + node _T_95 = and(_T_93, _T_94) @[RecFNToIN.scala 118:50] + node _T_96 = and(_T_95, roundCarryBut2) @[RecFNToIN.scala 119:49] + node _T_97 = or(_T_91, _T_96) @[RecFNToIN.scala 117:48] + node _T_98 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] + node overflow_unsigned = mux(notSpecial_magGeOne, _T_97, _T_98) @[RecFNToIN.scala 116:12] + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] + node _T_100 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] + node excSign = and(sign, _T_100) @[RecFNToIN.scala 124:24] + node _T_101 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] + node _T_103 = shl(UInt<1>("h01"), 63) @[RecFNToIN.scala 126:45] + node _T_105 = mux(_T_101, _T_103, UInt<1>("h00")) @[RecFNToIN.scala 126:12] + node _T_107 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] + node _T_108 = and(io.signedOut, _T_107) @[RecFNToIN.scala 127:26] + node _T_111 = mux(_T_108, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] + node _T_112 = or(_T_105, _T_111) @[RecFNToIN.scala 126:72] + node _T_114 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] + node _T_116 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] + node _T_117 = and(_T_114, _T_116) @[RecFNToIN.scala 131:28] + node _T_120 = mux(_T_117, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] + node excValue = or(_T_112, _T_120) @[RecFNToIN.scala 130:11] + node _T_122 = eq(invalid, UInt<1>("h00")) @[RecFNToIN.scala 135:35] + node _T_123 = and(roundInexact, _T_122) @[RecFNToIN.scala 135:32] + node _T_125 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] + node inexact = and(_T_123, _T_125) @[RecFNToIN.scala 135:45] + node _T_126 = or(invalid, overflow) @[RecFNToIN.scala 137:27] + node _T_127 = mux(_T_126, excValue, roundedInt) @[RecFNToIN.scala 137:18] + io.out <= _T_127 @[RecFNToIN.scala 137:12] + node _T_128 = cat(invalid, overflow) @[Cat.scala 30:58] + node _T_129 = cat(_T_128, inexact) @[Cat.scala 30:58] + io.intExceptionFlags <= _T_129 @[RecFNToIN.scala 138:26] + + module FPToInt : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} + + io is invalid + io is invalid + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 286:15] + reg valid : UInt<1>, clock @[FPU.scala 287:18] + valid <= io.in.valid @[FPU.scala 287:18] + when io.in.valid : @[FPU.scala 291:22] + in <- io.in.bits @[FPU.scala 292:8] + node _T_224 = eq(io.in.bits.ldst, UInt<1>("h00")) @[FPU.scala 293:47] + node _T_225 = and(io.in.bits.single, _T_224) @[FPU.scala 293:44] + node _T_228 = and(io.in.bits.cmd, UInt<4>("h0c")) @[FPU.scala 293:82] + node _T_229 = eq(UInt<4>("h0c"), _T_228) @[FPU.scala 293:82] + node _T_231 = eq(_T_229, UInt<1>("h00")) @[FPU.scala 293:82] + node _T_232 = and(_T_225, _T_231) @[FPU.scala 293:64] + when _T_232 : @[FPU.scala 293:98] + node _T_233 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 237:18] + node _T_234 = bits(io.in.bits.in1, 22, 0) @[FPU.scala 238:21] + node _T_235 = bits(io.in.bits.in1, 31, 23) @[FPU.scala 239:19] + node _T_236 = shl(_T_234, 53) @[FPU.scala 240:28] + node _T_237 = shr(_T_236, 24) @[FPU.scala 240:43] + node _T_238 = bits(_T_235, 8, 6) @[FPU.scala 242:26] + node _T_240 = add(_T_235, UInt<12>("h0800")) @[FPU.scala 243:31] + node _T_241 = tail(_T_240, 1) @[FPU.scala 243:31] + node _T_243 = sub(_T_241, UInt<9>("h0100")) @[FPU.scala 243:53] + node _T_244 = asUInt(_T_243) @[FPU.scala 243:53] + node _T_245 = tail(_T_244, 1) @[FPU.scala 243:53] + node _T_247 = eq(_T_238, UInt<1>("h00")) @[FPU.scala 244:19] + node _T_249 = geq(_T_238, UInt<3>("h06")) @[FPU.scala 244:36] + node _T_250 = or(_T_247, _T_249) @[FPU.scala 244:25] + node _T_251 = bits(_T_245, 8, 0) @[FPU.scala 244:65] + node _T_252 = cat(_T_238, _T_251) @[Cat.scala 30:58] + node _T_253 = bits(_T_245, 11, 0) @[FPU.scala 245:52] + node _T_254 = mux(_T_250, _T_252, _T_253) @[FPU.scala 244:10] + node _T_255 = cat(_T_233, _T_254) @[Cat.scala 30:58] + node _T_256 = cat(_T_255, _T_237) @[Cat.scala 30:58] + in.in1 <= _T_256 @[FPU.scala 294:14] + node _T_257 = bits(io.in.bits.in2, 32, 32) @[FPU.scala 237:18] + node _T_258 = bits(io.in.bits.in2, 22, 0) @[FPU.scala 238:21] + node _T_259 = bits(io.in.bits.in2, 31, 23) @[FPU.scala 239:19] + node _T_260 = shl(_T_258, 53) @[FPU.scala 240:28] + node _T_261 = shr(_T_260, 24) @[FPU.scala 240:43] + node _T_262 = bits(_T_259, 8, 6) @[FPU.scala 242:26] + node _T_264 = add(_T_259, UInt<12>("h0800")) @[FPU.scala 243:31] + node _T_265 = tail(_T_264, 1) @[FPU.scala 243:31] + node _T_267 = sub(_T_265, UInt<9>("h0100")) @[FPU.scala 243:53] + node _T_268 = asUInt(_T_267) @[FPU.scala 243:53] + node _T_269 = tail(_T_268, 1) @[FPU.scala 243:53] + node _T_271 = eq(_T_262, UInt<1>("h00")) @[FPU.scala 244:19] + node _T_273 = geq(_T_262, UInt<3>("h06")) @[FPU.scala 244:36] + node _T_274 = or(_T_271, _T_273) @[FPU.scala 244:25] + node _T_275 = bits(_T_269, 8, 0) @[FPU.scala 244:65] + node _T_276 = cat(_T_262, _T_275) @[Cat.scala 30:58] + node _T_277 = bits(_T_269, 11, 0) @[FPU.scala 245:52] + node _T_278 = mux(_T_274, _T_276, _T_277) @[FPU.scala 244:10] + node _T_279 = cat(_T_257, _T_278) @[Cat.scala 30:58] + node _T_280 = cat(_T_279, _T_261) @[Cat.scala 30:58] + in.in2 <= _T_280 @[FPU.scala 295:14] + skip @[FPU.scala 293:98] + skip @[FPU.scala 291:22] + node _T_281 = bits(in.in1, 32, 32) @[fNFromRecFN.scala 45:22] + node _T_282 = bits(in.in1, 31, 23) @[fNFromRecFN.scala 46:23] + node _T_283 = bits(in.in1, 22, 0) @[fNFromRecFN.scala 47:25] + node _T_284 = bits(_T_282, 6, 0) @[fNFromRecFN.scala 49:39] + node _T_286 = lt(_T_284, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] + node _T_287 = bits(_T_282, 8, 6) @[fNFromRecFN.scala 51:19] + node _T_289 = eq(_T_287, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] + node _T_290 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 52:24] + node _T_292 = eq(_T_290, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] + node _T_293 = and(_T_292, _T_286) @[fNFromRecFN.scala 52:62] + node _T_294 = or(_T_289, _T_293) @[fNFromRecFN.scala 51:57] + node _T_295 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 55:20] + node _T_297 = eq(_T_295, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] + node _T_299 = eq(_T_286, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] + node _T_300 = and(_T_297, _T_299) @[fNFromRecFN.scala 55:58] + node _T_301 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 57:23] + node _T_303 = eq(_T_301, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] + node _T_304 = or(_T_300, _T_303) @[fNFromRecFN.scala 56:39] + node _T_305 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 58:30] + node _T_307 = eq(_T_305, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] + node _T_308 = bits(_T_282, 6, 6) @[fNFromRecFN.scala 59:39] + node _T_309 = and(_T_307, _T_308) @[fNFromRecFN.scala 59:31] + node _T_311 = bits(_T_282, 4, 0) @[fNFromRecFN.scala 61:46] + node _T_312 = sub(UInt<2>("h02"), _T_311) @[fNFromRecFN.scala 61:39] + node _T_313 = asUInt(_T_312) @[fNFromRecFN.scala 61:39] + node _T_314 = tail(_T_313, 1) @[fNFromRecFN.scala 61:39] + node _T_316 = cat(UInt<1>("h01"), _T_283) @[Cat.scala 30:58] + node _T_317 = dshr(_T_316, _T_314) @[fNFromRecFN.scala 63:35] + node _T_318 = bits(_T_317, 22, 0) @[fNFromRecFN.scala 63:53] + node _T_319 = bits(_T_282, 7, 0) @[fNFromRecFN.scala 65:18] + node _T_321 = sub(_T_319, UInt<8>("h081")) @[fNFromRecFN.scala 65:36] + node _T_322 = asUInt(_T_321) @[fNFromRecFN.scala 65:36] + node _T_323 = tail(_T_322, 1) @[fNFromRecFN.scala 65:36] + node _T_324 = bits(_T_307, 0, 0) @[Bitwise.scala 71:15] + node _T_327 = mux(_T_324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_328 = mux(_T_304, _T_323, _T_327) @[fNFromRecFN.scala 68:16] + node _T_329 = or(_T_304, _T_309) @[fNFromRecFN.scala 70:26] + node _T_331 = mux(_T_294, _T_318, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] + node _T_332 = mux(_T_329, _T_283, _T_331) @[fNFromRecFN.scala 70:16] + node _T_333 = cat(_T_281, _T_328) @[Cat.scala 30:58] + node _T_334 = cat(_T_333, _T_332) @[Cat.scala 30:58] + node _T_335 = bits(_T_334, 31, 31) @[Package.scala 40:38] + node _T_336 = bits(_T_335, 0, 0) @[Bitwise.scala 71:15] + node _T_339 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node unrec_s = cat(_T_339, _T_334) @[Cat.scala 30:58] + node _T_340 = bits(in.in1, 64, 64) @[fNFromRecFN.scala 45:22] + node _T_341 = bits(in.in1, 63, 52) @[fNFromRecFN.scala 46:23] + node _T_342 = bits(in.in1, 51, 0) @[fNFromRecFN.scala 47:25] + node _T_343 = bits(_T_341, 9, 0) @[fNFromRecFN.scala 49:39] + node _T_345 = lt(_T_343, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] + node _T_346 = bits(_T_341, 11, 9) @[fNFromRecFN.scala 51:19] + node _T_348 = eq(_T_346, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] + node _T_349 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 52:24] + node _T_351 = eq(_T_349, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] + node _T_352 = and(_T_351, _T_345) @[fNFromRecFN.scala 52:62] + node _T_353 = or(_T_348, _T_352) @[fNFromRecFN.scala 51:57] + node _T_354 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 55:20] + node _T_356 = eq(_T_354, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] + node _T_358 = eq(_T_345, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] + node _T_359 = and(_T_356, _T_358) @[fNFromRecFN.scala 55:58] + node _T_360 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 57:23] + node _T_362 = eq(_T_360, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] + node _T_363 = or(_T_359, _T_362) @[fNFromRecFN.scala 56:39] + node _T_364 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 58:30] + node _T_366 = eq(_T_364, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] + node _T_367 = bits(_T_341, 9, 9) @[fNFromRecFN.scala 59:39] + node _T_368 = and(_T_366, _T_367) @[fNFromRecFN.scala 59:31] + node _T_370 = bits(_T_341, 5, 0) @[fNFromRecFN.scala 61:46] + node _T_371 = sub(UInt<2>("h02"), _T_370) @[fNFromRecFN.scala 61:39] + node _T_372 = asUInt(_T_371) @[fNFromRecFN.scala 61:39] + node _T_373 = tail(_T_372, 1) @[fNFromRecFN.scala 61:39] + node _T_375 = cat(UInt<1>("h01"), _T_342) @[Cat.scala 30:58] + node _T_376 = dshr(_T_375, _T_373) @[fNFromRecFN.scala 63:35] + node _T_377 = bits(_T_376, 51, 0) @[fNFromRecFN.scala 63:53] + node _T_378 = bits(_T_341, 10, 0) @[fNFromRecFN.scala 65:18] + node _T_380 = sub(_T_378, UInt<11>("h0401")) @[fNFromRecFN.scala 65:36] + node _T_381 = asUInt(_T_380) @[fNFromRecFN.scala 65:36] + node _T_382 = tail(_T_381, 1) @[fNFromRecFN.scala 65:36] + node _T_383 = bits(_T_366, 0, 0) @[Bitwise.scala 71:15] + node _T_386 = mux(_T_383, UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 71:12] + node _T_387 = mux(_T_363, _T_382, _T_386) @[fNFromRecFN.scala 68:16] + node _T_388 = or(_T_363, _T_368) @[fNFromRecFN.scala 70:26] + node _T_390 = mux(_T_353, _T_377, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] + node _T_391 = mux(_T_388, _T_342, _T_390) @[fNFromRecFN.scala 70:16] + node _T_392 = cat(_T_340, _T_387) @[Cat.scala 30:58] + node _T_393 = cat(_T_392, _T_391) @[Cat.scala 30:58] + node unrec_int = mux(in.single, unrec_s, _T_393) @[FPU.scala 304:10] + node _T_394 = bits(in.in1, 32, 32) @[FPU.scala 201:18] + node _T_395 = bits(in.in1, 31, 23) @[FPU.scala 202:17] + node _T_396 = bits(in.in1, 22, 0) @[FPU.scala 203:17] + node _T_397 = bits(_T_395, 8, 6) @[FPU.scala 205:26] + node _T_398 = bits(_T_397, 2, 1) @[FPU.scala 206:27] + node _T_400 = eq(_T_398, UInt<2>("h03")) @[FPU.scala 207:30] + node _T_401 = bits(_T_395, 6, 0) @[FPU.scala 209:32] + node _T_403 = lt(_T_401, UInt<2>("h02")) @[FPU.scala 209:48] + node _T_405 = eq(_T_397, UInt<1>("h01")) @[FPU.scala 210:28] + node _T_407 = eq(_T_398, UInt<1>("h01")) @[FPU.scala 210:50] + node _T_408 = and(_T_407, _T_403) @[FPU.scala 210:62] + node _T_409 = or(_T_405, _T_408) @[FPU.scala 210:40] + node _T_411 = eq(_T_398, UInt<1>("h01")) @[FPU.scala 211:27] + node _T_413 = eq(_T_403, UInt<1>("h00")) @[FPU.scala 211:42] + node _T_414 = and(_T_411, _T_413) @[FPU.scala 211:39] + node _T_416 = eq(_T_398, UInt<2>("h02")) @[FPU.scala 211:71] + node _T_417 = or(_T_414, _T_416) @[FPU.scala 211:61] + node _T_419 = eq(_T_397, UInt<1>("h00")) @[FPU.scala 212:23] + node _T_420 = bits(_T_395, 6, 6) @[FPU.scala 213:34] + node _T_422 = eq(_T_420, UInt<1>("h00")) @[FPU.scala 213:30] + node _T_423 = and(_T_400, _T_422) @[FPU.scala 213:27] + node _T_424 = not(_T_397) @[FPU.scala 214:22] + node _T_426 = eq(_T_424, UInt<1>("h00")) @[FPU.scala 214:22] + node _T_427 = bits(_T_396, 22, 22) @[FPU.scala 215:31] + node _T_429 = eq(_T_427, UInt<1>("h00")) @[FPU.scala 215:27] + node _T_430 = and(_T_426, _T_429) @[FPU.scala 215:24] + node _T_431 = bits(_T_396, 22, 22) @[FPU.scala 216:30] + node _T_432 = and(_T_426, _T_431) @[FPU.scala 216:24] + node _T_434 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 218:34] + node _T_435 = and(_T_423, _T_434) @[FPU.scala 218:31] + node _T_437 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 218:53] + node _T_438 = and(_T_417, _T_437) @[FPU.scala 218:50] + node _T_440 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 219:24] + node _T_441 = and(_T_409, _T_440) @[FPU.scala 219:21] + node _T_443 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 219:41] + node _T_444 = and(_T_419, _T_443) @[FPU.scala 219:38] + node _T_445 = and(_T_419, _T_394) @[FPU.scala 219:55] + node _T_446 = and(_T_409, _T_394) @[FPU.scala 220:21] + node _T_447 = and(_T_417, _T_394) @[FPU.scala 220:39] + node _T_448 = and(_T_423, _T_394) @[FPU.scala 220:54] + node _T_449 = cat(_T_447, _T_448) @[Cat.scala 30:58] + node _T_450 = cat(_T_444, _T_445) @[Cat.scala 30:58] + node _T_451 = cat(_T_450, _T_446) @[Cat.scala 30:58] + node _T_452 = cat(_T_451, _T_449) @[Cat.scala 30:58] + node _T_453 = cat(_T_438, _T_441) @[Cat.scala 30:58] + node _T_454 = cat(_T_432, _T_430) @[Cat.scala 30:58] + node _T_455 = cat(_T_454, _T_435) @[Cat.scala 30:58] + node _T_456 = cat(_T_455, _T_453) @[Cat.scala 30:58] + node classify_s = cat(_T_456, _T_452) @[Cat.scala 30:58] + node _T_457 = bits(in.in1, 64, 64) @[FPU.scala 201:18] + node _T_458 = bits(in.in1, 63, 52) @[FPU.scala 202:17] + node _T_459 = bits(in.in1, 51, 0) @[FPU.scala 203:17] + node _T_460 = bits(_T_458, 11, 9) @[FPU.scala 205:26] + node _T_461 = bits(_T_460, 2, 1) @[FPU.scala 206:27] + node _T_463 = eq(_T_461, UInt<2>("h03")) @[FPU.scala 207:30] + node _T_464 = bits(_T_458, 9, 0) @[FPU.scala 209:32] + node _T_466 = lt(_T_464, UInt<2>("h02")) @[FPU.scala 209:48] + node _T_468 = eq(_T_460, UInt<1>("h01")) @[FPU.scala 210:28] + node _T_470 = eq(_T_461, UInt<1>("h01")) @[FPU.scala 210:50] + node _T_471 = and(_T_470, _T_466) @[FPU.scala 210:62] + node _T_472 = or(_T_468, _T_471) @[FPU.scala 210:40] + node _T_474 = eq(_T_461, UInt<1>("h01")) @[FPU.scala 211:27] + node _T_476 = eq(_T_466, UInt<1>("h00")) @[FPU.scala 211:42] + node _T_477 = and(_T_474, _T_476) @[FPU.scala 211:39] + node _T_479 = eq(_T_461, UInt<2>("h02")) @[FPU.scala 211:71] + node _T_480 = or(_T_477, _T_479) @[FPU.scala 211:61] + node _T_482 = eq(_T_460, UInt<1>("h00")) @[FPU.scala 212:23] + node _T_483 = bits(_T_458, 9, 9) @[FPU.scala 213:34] + node _T_485 = eq(_T_483, UInt<1>("h00")) @[FPU.scala 213:30] + node _T_486 = and(_T_463, _T_485) @[FPU.scala 213:27] + node _T_487 = not(_T_460) @[FPU.scala 214:22] + node _T_489 = eq(_T_487, UInt<1>("h00")) @[FPU.scala 214:22] + node _T_490 = bits(_T_459, 51, 51) @[FPU.scala 215:31] + node _T_492 = eq(_T_490, UInt<1>("h00")) @[FPU.scala 215:27] + node _T_493 = and(_T_489, _T_492) @[FPU.scala 215:24] + node _T_494 = bits(_T_459, 51, 51) @[FPU.scala 216:30] + node _T_495 = and(_T_489, _T_494) @[FPU.scala 216:24] + node _T_497 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 218:34] + node _T_498 = and(_T_486, _T_497) @[FPU.scala 218:31] + node _T_500 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 218:53] + node _T_501 = and(_T_480, _T_500) @[FPU.scala 218:50] + node _T_503 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 219:24] + node _T_504 = and(_T_472, _T_503) @[FPU.scala 219:21] + node _T_506 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 219:41] + node _T_507 = and(_T_482, _T_506) @[FPU.scala 219:38] + node _T_508 = and(_T_482, _T_457) @[FPU.scala 219:55] + node _T_509 = and(_T_472, _T_457) @[FPU.scala 220:21] + node _T_510 = and(_T_480, _T_457) @[FPU.scala 220:39] + node _T_511 = and(_T_486, _T_457) @[FPU.scala 220:54] + node _T_512 = cat(_T_510, _T_511) @[Cat.scala 30:58] + node _T_513 = cat(_T_507, _T_508) @[Cat.scala 30:58] + node _T_514 = cat(_T_513, _T_509) @[Cat.scala 30:58] + node _T_515 = cat(_T_514, _T_512) @[Cat.scala 30:58] + node _T_516 = cat(_T_501, _T_504) @[Cat.scala 30:58] + node _T_517 = cat(_T_495, _T_493) @[Cat.scala 30:58] + node _T_518 = cat(_T_517, _T_498) @[Cat.scala 30:58] + node _T_519 = cat(_T_518, _T_516) @[Cat.scala 30:58] + node _T_520 = cat(_T_519, _T_515) @[Cat.scala 30:58] + node classify_out = mux(in.single, classify_s, _T_520) @[FPU.scala 316:10] + inst dcmp of CompareRecFN @[FPU.scala 319:20] + dcmp.io is invalid + dcmp.clock <= clock + dcmp.reset <= reset + dcmp.io.a <= in.in1 @[FPU.scala 320:13] + dcmp.io.b <= in.in2 @[FPU.scala 321:13] + node _T_521 = bits(in.rm, 1, 1) @[FPU.scala 322:30] + node _T_523 = eq(_T_521, UInt<1>("h00")) @[FPU.scala 322:24] + dcmp.io.signaling <= _T_523 @[FPU.scala 322:21] + node _T_524 = bits(in.rm, 0, 0) @[FPU.scala 324:33] + node _T_525 = mux(_T_524, classify_out, unrec_int) @[FPU.scala 324:27] + io.out.bits.toint <= _T_525 @[FPU.scala 324:21] + io.out.bits.store <= unrec_int @[FPU.scala 325:21] + io.out.bits.exc <= UInt<1>("h00") @[FPU.scala 326:19] + node _T_529 = and(in.cmd, UInt<4>("h0c")) @[FPU.scala 328:16] + node _T_530 = eq(UInt<3>("h04"), _T_529) @[FPU.scala 328:16] + when _T_530 : @[FPU.scala 328:30] + node _T_531 = not(in.rm) @[FPU.scala 329:27] + node _T_532 = cat(dcmp.io.lt, dcmp.io.eq) @[Cat.scala 30:58] + node _T_533 = and(_T_531, _T_532) @[FPU.scala 329:34] + node _T_535 = neq(_T_533, UInt<1>("h00")) @[FPU.scala 329:65] + io.out.bits.toint <= _T_535 @[FPU.scala 329:23] + io.out.bits.exc <= dcmp.io.exceptionFlags @[FPU.scala 330:21] + skip @[FPU.scala 328:30] + node _T_538 = and(in.cmd, UInt<4>("h0c")) @[FPU.scala 332:16] + node _T_539 = eq(UInt<4>("h08"), _T_538) @[FPU.scala 332:16] + when _T_539 : @[FPU.scala 332:33] + inst RecFNToIN of RecFNToIN @[FPU.scala 336:24] + RecFNToIN.io is invalid + RecFNToIN.clock <= clock + RecFNToIN.reset <= reset + RecFNToIN.io.in <= in.in1 @[FPU.scala 337:18] + RecFNToIN.io.roundingMode <= in.rm @[FPU.scala 338:28] + node _T_540 = bits(in.typ, 0, 0) @[FPU.scala 339:35] + node _T_541 = not(_T_540) @[FPU.scala 339:28] + RecFNToIN.io.signedOut <= _T_541 @[FPU.scala 339:25] + node _T_542 = bits(in.typ, 1, 1) @[Package.scala 44:13] + node _T_544 = eq(_T_542, UInt<1>("h00")) @[FPU.scala 340:44] + when _T_544 : @[FPU.scala 340:51] + node _T_545 = bits(RecFNToIN.io.out, 31, 31) @[Package.scala 40:38] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 71:15] + node _T_549 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_550 = cat(_T_549, RecFNToIN.io.out) @[Cat.scala 30:58] + io.out.bits.toint <= _T_550 @[FPU.scala 341:27] + node _T_551 = bits(RecFNToIN.io.intExceptionFlags, 2, 1) @[FPU.scala 342:57] + node _T_553 = neq(_T_551, UInt<1>("h00")) @[FPU.scala 342:64] + node _T_555 = bits(RecFNToIN.io.intExceptionFlags, 0, 0) @[FPU.scala 342:106] + node _T_556 = cat(_T_553, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_557 = cat(_T_556, _T_555) @[Cat.scala 30:58] + io.out.bits.exc <= _T_557 @[FPU.scala 342:25] + skip @[FPU.scala 340:51] + inst RecFNToIN_1 of RecFNToIN_1 @[FPU.scala 336:24] + RecFNToIN_1.io is invalid + RecFNToIN_1.clock <= clock + RecFNToIN_1.reset <= reset + RecFNToIN_1.io.in <= in.in1 @[FPU.scala 337:18] + RecFNToIN_1.io.roundingMode <= in.rm @[FPU.scala 338:28] + node _T_558 = bits(in.typ, 0, 0) @[FPU.scala 339:35] + node _T_559 = not(_T_558) @[FPU.scala 339:28] + RecFNToIN_1.io.signedOut <= _T_559 @[FPU.scala 339:25] + node _T_560 = bits(in.typ, 1, 1) @[Package.scala 44:13] + node _T_562 = eq(_T_560, UInt<1>("h01")) @[FPU.scala 340:44] + when _T_562 : @[FPU.scala 340:51] + io.out.bits.toint <= RecFNToIN_1.io.out @[FPU.scala 341:27] + node _T_563 = bits(RecFNToIN_1.io.intExceptionFlags, 2, 1) @[FPU.scala 342:57] + node _T_565 = neq(_T_563, UInt<1>("h00")) @[FPU.scala 342:64] + node _T_567 = bits(RecFNToIN_1.io.intExceptionFlags, 0, 0) @[FPU.scala 342:106] + node _T_568 = cat(_T_565, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_569 = cat(_T_568, _T_567) @[Cat.scala 30:58] + io.out.bits.exc <= _T_569 @[FPU.scala 342:25] + skip @[FPU.scala 340:51] + skip @[FPU.scala 332:33] + io.out.valid <= valid @[FPU.scala 347:16] + io.out.bits.lt <= dcmp.io.lt @[FPU.scala 348:18] + io.as_double <- in @[FPU.scala 349:16] + + module INToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_12 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] + node sign = and(io.signedIn, _T_12) @[INToRecFN.scala 55:28] + node _T_14 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] + node _T_15 = asUInt(_T_14) @[INToRecFN.scala 56:27] + node _T_16 = tail(_T_15, 1) @[INToRecFN.scala 56:27] + node absIn = mux(sign, _T_16, io.in) @[INToRecFN.scala 56:20] + node _T_17 = shl(absIn, 0) @[INToRecFN.scala 57:32] + node _T_18 = bits(_T_17, 63, 32) @[CircuitMath.scala 35:17] + node _T_19 = bits(_T_17, 31, 0) @[CircuitMath.scala 36:17] + node _T_21 = neq(_T_18, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_22 = bits(_T_18, 31, 16) @[CircuitMath.scala 35:17] + node _T_23 = bits(_T_18, 15, 0) @[CircuitMath.scala 36:17] + node _T_25 = neq(_T_22, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_26 = bits(_T_22, 15, 8) @[CircuitMath.scala 35:17] + node _T_27 = bits(_T_22, 7, 0) @[CircuitMath.scala 36:17] + node _T_29 = neq(_T_26, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_30 = bits(_T_26, 7, 4) @[CircuitMath.scala 35:17] + node _T_31 = bits(_T_26, 3, 0) @[CircuitMath.scala 36:17] + node _T_33 = neq(_T_30, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_34 = bits(_T_30, 3, 3) @[CircuitMath.scala 32:12] + node _T_36 = bits(_T_30, 2, 2) @[CircuitMath.scala 32:12] + node _T_38 = bits(_T_30, 1, 1) @[CircuitMath.scala 30:8] + node _T_39 = mux(_T_36, UInt<2>("h02"), _T_38) @[CircuitMath.scala 32:10] + node _T_40 = mux(_T_34, UInt<2>("h03"), _T_39) @[CircuitMath.scala 32:10] + node _T_41 = bits(_T_31, 3, 3) @[CircuitMath.scala 32:12] + node _T_43 = bits(_T_31, 2, 2) @[CircuitMath.scala 32:12] + node _T_45 = bits(_T_31, 1, 1) @[CircuitMath.scala 30:8] + node _T_46 = mux(_T_43, UInt<2>("h02"), _T_45) @[CircuitMath.scala 32:10] + node _T_47 = mux(_T_41, UInt<2>("h03"), _T_46) @[CircuitMath.scala 32:10] + node _T_48 = mux(_T_33, _T_40, _T_47) @[CircuitMath.scala 38:21] + node _T_49 = cat(_T_33, _T_48) @[Cat.scala 30:58] + node _T_50 = bits(_T_27, 7, 4) @[CircuitMath.scala 35:17] + node _T_51 = bits(_T_27, 3, 0) @[CircuitMath.scala 36:17] + node _T_53 = neq(_T_50, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_54 = bits(_T_50, 3, 3) @[CircuitMath.scala 32:12] + node _T_56 = bits(_T_50, 2, 2) @[CircuitMath.scala 32:12] + node _T_58 = bits(_T_50, 1, 1) @[CircuitMath.scala 30:8] + node _T_59 = mux(_T_56, UInt<2>("h02"), _T_58) @[CircuitMath.scala 32:10] + node _T_60 = mux(_T_54, UInt<2>("h03"), _T_59) @[CircuitMath.scala 32:10] + node _T_61 = bits(_T_51, 3, 3) @[CircuitMath.scala 32:12] + node _T_63 = bits(_T_51, 2, 2) @[CircuitMath.scala 32:12] + node _T_65 = bits(_T_51, 1, 1) @[CircuitMath.scala 30:8] + node _T_66 = mux(_T_63, UInt<2>("h02"), _T_65) @[CircuitMath.scala 32:10] + node _T_67 = mux(_T_61, UInt<2>("h03"), _T_66) @[CircuitMath.scala 32:10] + node _T_68 = mux(_T_53, _T_60, _T_67) @[CircuitMath.scala 38:21] + node _T_69 = cat(_T_53, _T_68) @[Cat.scala 30:58] + node _T_70 = mux(_T_29, _T_49, _T_69) @[CircuitMath.scala 38:21] + node _T_71 = cat(_T_29, _T_70) @[Cat.scala 30:58] + node _T_72 = bits(_T_23, 15, 8) @[CircuitMath.scala 35:17] + node _T_73 = bits(_T_23, 7, 0) @[CircuitMath.scala 36:17] + node _T_75 = neq(_T_72, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_76 = bits(_T_72, 7, 4) @[CircuitMath.scala 35:17] + node _T_77 = bits(_T_72, 3, 0) @[CircuitMath.scala 36:17] + node _T_79 = neq(_T_76, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_80 = bits(_T_76, 3, 3) @[CircuitMath.scala 32:12] + node _T_82 = bits(_T_76, 2, 2) @[CircuitMath.scala 32:12] + node _T_84 = bits(_T_76, 1, 1) @[CircuitMath.scala 30:8] + node _T_85 = mux(_T_82, UInt<2>("h02"), _T_84) @[CircuitMath.scala 32:10] + node _T_86 = mux(_T_80, UInt<2>("h03"), _T_85) @[CircuitMath.scala 32:10] + node _T_87 = bits(_T_77, 3, 3) @[CircuitMath.scala 32:12] + node _T_89 = bits(_T_77, 2, 2) @[CircuitMath.scala 32:12] + node _T_91 = bits(_T_77, 1, 1) @[CircuitMath.scala 30:8] + node _T_92 = mux(_T_89, UInt<2>("h02"), _T_91) @[CircuitMath.scala 32:10] + node _T_93 = mux(_T_87, UInt<2>("h03"), _T_92) @[CircuitMath.scala 32:10] + node _T_94 = mux(_T_79, _T_86, _T_93) @[CircuitMath.scala 38:21] + node _T_95 = cat(_T_79, _T_94) @[Cat.scala 30:58] + node _T_96 = bits(_T_73, 7, 4) @[CircuitMath.scala 35:17] + node _T_97 = bits(_T_73, 3, 0) @[CircuitMath.scala 36:17] + node _T_99 = neq(_T_96, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_100 = bits(_T_96, 3, 3) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_96, 2, 2) @[CircuitMath.scala 32:12] + node _T_104 = bits(_T_96, 1, 1) @[CircuitMath.scala 30:8] + node _T_105 = mux(_T_102, UInt<2>("h02"), _T_104) @[CircuitMath.scala 32:10] + node _T_106 = mux(_T_100, UInt<2>("h03"), _T_105) @[CircuitMath.scala 32:10] + node _T_107 = bits(_T_97, 3, 3) @[CircuitMath.scala 32:12] + node _T_109 = bits(_T_97, 2, 2) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_97, 1, 1) @[CircuitMath.scala 30:8] + node _T_112 = mux(_T_109, UInt<2>("h02"), _T_111) @[CircuitMath.scala 32:10] + node _T_113 = mux(_T_107, UInt<2>("h03"), _T_112) @[CircuitMath.scala 32:10] + node _T_114 = mux(_T_99, _T_106, _T_113) @[CircuitMath.scala 38:21] + node _T_115 = cat(_T_99, _T_114) @[Cat.scala 30:58] + node _T_116 = mux(_T_75, _T_95, _T_115) @[CircuitMath.scala 38:21] + node _T_117 = cat(_T_75, _T_116) @[Cat.scala 30:58] + node _T_118 = mux(_T_25, _T_71, _T_117) @[CircuitMath.scala 38:21] + node _T_119 = cat(_T_25, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_19, 31, 16) @[CircuitMath.scala 35:17] + node _T_121 = bits(_T_19, 15, 0) @[CircuitMath.scala 36:17] + node _T_123 = neq(_T_120, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_124 = bits(_T_120, 15, 8) @[CircuitMath.scala 35:17] + node _T_125 = bits(_T_120, 7, 0) @[CircuitMath.scala 36:17] + node _T_127 = neq(_T_124, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_128 = bits(_T_124, 7, 4) @[CircuitMath.scala 35:17] + node _T_129 = bits(_T_124, 3, 0) @[CircuitMath.scala 36:17] + node _T_131 = neq(_T_128, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_132 = bits(_T_128, 3, 3) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_128, 2, 2) @[CircuitMath.scala 32:12] + node _T_136 = bits(_T_128, 1, 1) @[CircuitMath.scala 30:8] + node _T_137 = mux(_T_134, UInt<2>("h02"), _T_136) @[CircuitMath.scala 32:10] + node _T_138 = mux(_T_132, UInt<2>("h03"), _T_137) @[CircuitMath.scala 32:10] + node _T_139 = bits(_T_129, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_129, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_129, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = mux(_T_131, _T_138, _T_145) @[CircuitMath.scala 38:21] + node _T_147 = cat(_T_131, _T_146) @[Cat.scala 30:58] + node _T_148 = bits(_T_125, 7, 4) @[CircuitMath.scala 35:17] + node _T_149 = bits(_T_125, 3, 0) @[CircuitMath.scala 36:17] + node _T_151 = neq(_T_148, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_152 = bits(_T_148, 3, 3) @[CircuitMath.scala 32:12] + node _T_154 = bits(_T_148, 2, 2) @[CircuitMath.scala 32:12] + node _T_156 = bits(_T_148, 1, 1) @[CircuitMath.scala 30:8] + node _T_157 = mux(_T_154, UInt<2>("h02"), _T_156) @[CircuitMath.scala 32:10] + node _T_158 = mux(_T_152, UInt<2>("h03"), _T_157) @[CircuitMath.scala 32:10] + node _T_159 = bits(_T_149, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_149, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_149, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = mux(_T_151, _T_158, _T_165) @[CircuitMath.scala 38:21] + node _T_167 = cat(_T_151, _T_166) @[Cat.scala 30:58] + node _T_168 = mux(_T_127, _T_147, _T_167) @[CircuitMath.scala 38:21] + node _T_169 = cat(_T_127, _T_168) @[Cat.scala 30:58] + node _T_170 = bits(_T_121, 15, 8) @[CircuitMath.scala 35:17] + node _T_171 = bits(_T_121, 7, 0) @[CircuitMath.scala 36:17] + node _T_173 = neq(_T_170, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_174 = bits(_T_170, 7, 4) @[CircuitMath.scala 35:17] + node _T_175 = bits(_T_170, 3, 0) @[CircuitMath.scala 36:17] + node _T_177 = neq(_T_174, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_178 = bits(_T_174, 3, 3) @[CircuitMath.scala 32:12] + node _T_180 = bits(_T_174, 2, 2) @[CircuitMath.scala 32:12] + node _T_182 = bits(_T_174, 1, 1) @[CircuitMath.scala 30:8] + node _T_183 = mux(_T_180, UInt<2>("h02"), _T_182) @[CircuitMath.scala 32:10] + node _T_184 = mux(_T_178, UInt<2>("h03"), _T_183) @[CircuitMath.scala 32:10] + node _T_185 = bits(_T_175, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_175, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_175, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = mux(_T_177, _T_184, _T_191) @[CircuitMath.scala 38:21] + node _T_193 = cat(_T_177, _T_192) @[Cat.scala 30:58] + node _T_194 = bits(_T_171, 7, 4) @[CircuitMath.scala 35:17] + node _T_195 = bits(_T_171, 3, 0) @[CircuitMath.scala 36:17] + node _T_197 = neq(_T_194, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_198 = bits(_T_194, 3, 3) @[CircuitMath.scala 32:12] + node _T_200 = bits(_T_194, 2, 2) @[CircuitMath.scala 32:12] + node _T_202 = bits(_T_194, 1, 1) @[CircuitMath.scala 30:8] + node _T_203 = mux(_T_200, UInt<2>("h02"), _T_202) @[CircuitMath.scala 32:10] + node _T_204 = mux(_T_198, UInt<2>("h03"), _T_203) @[CircuitMath.scala 32:10] + node _T_205 = bits(_T_195, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_195, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_195, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = mux(_T_197, _T_204, _T_211) @[CircuitMath.scala 38:21] + node _T_213 = cat(_T_197, _T_212) @[Cat.scala 30:58] + node _T_214 = mux(_T_173, _T_193, _T_213) @[CircuitMath.scala 38:21] + node _T_215 = cat(_T_173, _T_214) @[Cat.scala 30:58] + node _T_216 = mux(_T_123, _T_169, _T_215) @[CircuitMath.scala 38:21] + node _T_217 = cat(_T_123, _T_216) @[Cat.scala 30:58] + node _T_218 = mux(_T_21, _T_119, _T_217) @[CircuitMath.scala 38:21] + node _T_219 = cat(_T_21, _T_218) @[Cat.scala 30:58] + node normCount = not(_T_219) @[INToRecFN.scala 57:21] + node _T_220 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] + node normAbsIn = bits(_T_220, 63, 0) @[INToRecFN.scala 58:39] + node _T_222 = bits(normAbsIn, 40, 39) @[INToRecFN.scala 63:26] + node _T_223 = bits(normAbsIn, 38, 0) @[INToRecFN.scala 64:26] + node _T_225 = neq(_T_223, UInt<1>("h00")) @[INToRecFN.scala 64:55] + node roundBits = cat(_T_222, _T_225) @[Cat.scala 30:58] + node _T_226 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] + node roundInexact = neq(_T_226, UInt<1>("h00")) @[INToRecFN.scala 72:40] + node _T_228 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] + node _T_229 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] + node _T_230 = not(_T_229) @[INToRecFN.scala 75:29] + node _T_232 = eq(_T_230, UInt<1>("h00")) @[INToRecFN.scala 75:29] + node _T_233 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] + node _T_234 = not(_T_233) @[INToRecFN.scala 75:53] + node _T_236 = eq(_T_234, UInt<1>("h00")) @[INToRecFN.scala 75:53] + node _T_237 = or(_T_232, _T_236) @[INToRecFN.scala 75:34] + node _T_239 = mux(_T_228, _T_237, UInt<1>("h00")) @[INToRecFN.scala 74:12] + node _T_240 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] + node _T_241 = and(sign, roundInexact) @[INToRecFN.scala 79:18] + node _T_243 = mux(_T_240, _T_241, UInt<1>("h00")) @[INToRecFN.scala 78:12] + node _T_244 = or(_T_239, _T_243) @[INToRecFN.scala 77:11] + node _T_245 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] + node _T_247 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] + node _T_248 = and(_T_247, roundInexact) @[INToRecFN.scala 83:20] + node _T_250 = mux(_T_245, _T_248, UInt<1>("h00")) @[INToRecFN.scala 82:12] + node round = or(_T_244, _T_250) @[INToRecFN.scala 81:11] + node _T_252 = bits(normAbsIn, 63, 40) @[INToRecFN.scala 89:34] + node unroundedNorm = cat(UInt<1>("h00"), _T_252) @[Cat.scala 30:58] + node _T_255 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] + node _T_256 = tail(_T_255, 1) @[INToRecFN.scala 94:48] + node roundedNorm = mux(round, _T_256, unroundedNorm) @[INToRecFN.scala 94:26] + node _T_257 = not(normCount) @[INToRecFN.scala 97:24] + node unroundedExp = cat(UInt<1>("h00"), _T_257) @[Cat.scala 30:58] + node _T_260 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 30:58] + node _T_261 = bits(roundedNorm, 24, 24) @[INToRecFN.scala 106:65] + node _T_262 = add(_T_260, _T_261) @[INToRecFN.scala 106:52] + node roundedExp = tail(_T_262, 1) @[INToRecFN.scala 106:52] + node _T_263 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] + node _T_265 = bits(roundedExp, 7, 0) @[INToRecFN.scala 115:27] + node _T_266 = mux(UInt<1>("h00"), UInt<8>("h080"), _T_265) @[INToRecFN.scala 113:16] + node expOut = cat(_T_263, _T_266) @[Cat.scala 30:58] + node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] + node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] + node _T_267 = bits(roundedNorm, 22, 0) @[INToRecFN.scala 122:44] + node _T_268 = cat(sign, expOut) @[Cat.scala 30:58] + node _T_269 = cat(_T_268, _T_267) @[Cat.scala 30:58] + io.out <= _T_269 @[INToRecFN.scala 122:12] + node _T_272 = cat(UInt<1>("h00"), inexact) @[Cat.scala 30:58] + node _T_273 = cat(UInt<2>("h00"), overflow) @[Cat.scala 30:58] + node _T_274 = cat(_T_273, _T_272) @[Cat.scala 30:58] + io.exceptionFlags <= _T_274 @[INToRecFN.scala 123:23] + + module INToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_12 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] + node sign = and(io.signedIn, _T_12) @[INToRecFN.scala 55:28] + node _T_14 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] + node _T_15 = asUInt(_T_14) @[INToRecFN.scala 56:27] + node _T_16 = tail(_T_15, 1) @[INToRecFN.scala 56:27] + node absIn = mux(sign, _T_16, io.in) @[INToRecFN.scala 56:20] + node _T_17 = shl(absIn, 0) @[INToRecFN.scala 57:32] + node _T_18 = bits(_T_17, 63, 32) @[CircuitMath.scala 35:17] + node _T_19 = bits(_T_17, 31, 0) @[CircuitMath.scala 36:17] + node _T_21 = neq(_T_18, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_22 = bits(_T_18, 31, 16) @[CircuitMath.scala 35:17] + node _T_23 = bits(_T_18, 15, 0) @[CircuitMath.scala 36:17] + node _T_25 = neq(_T_22, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_26 = bits(_T_22, 15, 8) @[CircuitMath.scala 35:17] + node _T_27 = bits(_T_22, 7, 0) @[CircuitMath.scala 36:17] + node _T_29 = neq(_T_26, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_30 = bits(_T_26, 7, 4) @[CircuitMath.scala 35:17] + node _T_31 = bits(_T_26, 3, 0) @[CircuitMath.scala 36:17] + node _T_33 = neq(_T_30, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_34 = bits(_T_30, 3, 3) @[CircuitMath.scala 32:12] + node _T_36 = bits(_T_30, 2, 2) @[CircuitMath.scala 32:12] + node _T_38 = bits(_T_30, 1, 1) @[CircuitMath.scala 30:8] + node _T_39 = mux(_T_36, UInt<2>("h02"), _T_38) @[CircuitMath.scala 32:10] + node _T_40 = mux(_T_34, UInt<2>("h03"), _T_39) @[CircuitMath.scala 32:10] + node _T_41 = bits(_T_31, 3, 3) @[CircuitMath.scala 32:12] + node _T_43 = bits(_T_31, 2, 2) @[CircuitMath.scala 32:12] + node _T_45 = bits(_T_31, 1, 1) @[CircuitMath.scala 30:8] + node _T_46 = mux(_T_43, UInt<2>("h02"), _T_45) @[CircuitMath.scala 32:10] + node _T_47 = mux(_T_41, UInt<2>("h03"), _T_46) @[CircuitMath.scala 32:10] + node _T_48 = mux(_T_33, _T_40, _T_47) @[CircuitMath.scala 38:21] + node _T_49 = cat(_T_33, _T_48) @[Cat.scala 30:58] + node _T_50 = bits(_T_27, 7, 4) @[CircuitMath.scala 35:17] + node _T_51 = bits(_T_27, 3, 0) @[CircuitMath.scala 36:17] + node _T_53 = neq(_T_50, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_54 = bits(_T_50, 3, 3) @[CircuitMath.scala 32:12] + node _T_56 = bits(_T_50, 2, 2) @[CircuitMath.scala 32:12] + node _T_58 = bits(_T_50, 1, 1) @[CircuitMath.scala 30:8] + node _T_59 = mux(_T_56, UInt<2>("h02"), _T_58) @[CircuitMath.scala 32:10] + node _T_60 = mux(_T_54, UInt<2>("h03"), _T_59) @[CircuitMath.scala 32:10] + node _T_61 = bits(_T_51, 3, 3) @[CircuitMath.scala 32:12] + node _T_63 = bits(_T_51, 2, 2) @[CircuitMath.scala 32:12] + node _T_65 = bits(_T_51, 1, 1) @[CircuitMath.scala 30:8] + node _T_66 = mux(_T_63, UInt<2>("h02"), _T_65) @[CircuitMath.scala 32:10] + node _T_67 = mux(_T_61, UInt<2>("h03"), _T_66) @[CircuitMath.scala 32:10] + node _T_68 = mux(_T_53, _T_60, _T_67) @[CircuitMath.scala 38:21] + node _T_69 = cat(_T_53, _T_68) @[Cat.scala 30:58] + node _T_70 = mux(_T_29, _T_49, _T_69) @[CircuitMath.scala 38:21] + node _T_71 = cat(_T_29, _T_70) @[Cat.scala 30:58] + node _T_72 = bits(_T_23, 15, 8) @[CircuitMath.scala 35:17] + node _T_73 = bits(_T_23, 7, 0) @[CircuitMath.scala 36:17] + node _T_75 = neq(_T_72, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_76 = bits(_T_72, 7, 4) @[CircuitMath.scala 35:17] + node _T_77 = bits(_T_72, 3, 0) @[CircuitMath.scala 36:17] + node _T_79 = neq(_T_76, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_80 = bits(_T_76, 3, 3) @[CircuitMath.scala 32:12] + node _T_82 = bits(_T_76, 2, 2) @[CircuitMath.scala 32:12] + node _T_84 = bits(_T_76, 1, 1) @[CircuitMath.scala 30:8] + node _T_85 = mux(_T_82, UInt<2>("h02"), _T_84) @[CircuitMath.scala 32:10] + node _T_86 = mux(_T_80, UInt<2>("h03"), _T_85) @[CircuitMath.scala 32:10] + node _T_87 = bits(_T_77, 3, 3) @[CircuitMath.scala 32:12] + node _T_89 = bits(_T_77, 2, 2) @[CircuitMath.scala 32:12] + node _T_91 = bits(_T_77, 1, 1) @[CircuitMath.scala 30:8] + node _T_92 = mux(_T_89, UInt<2>("h02"), _T_91) @[CircuitMath.scala 32:10] + node _T_93 = mux(_T_87, UInt<2>("h03"), _T_92) @[CircuitMath.scala 32:10] + node _T_94 = mux(_T_79, _T_86, _T_93) @[CircuitMath.scala 38:21] + node _T_95 = cat(_T_79, _T_94) @[Cat.scala 30:58] + node _T_96 = bits(_T_73, 7, 4) @[CircuitMath.scala 35:17] + node _T_97 = bits(_T_73, 3, 0) @[CircuitMath.scala 36:17] + node _T_99 = neq(_T_96, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_100 = bits(_T_96, 3, 3) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_96, 2, 2) @[CircuitMath.scala 32:12] + node _T_104 = bits(_T_96, 1, 1) @[CircuitMath.scala 30:8] + node _T_105 = mux(_T_102, UInt<2>("h02"), _T_104) @[CircuitMath.scala 32:10] + node _T_106 = mux(_T_100, UInt<2>("h03"), _T_105) @[CircuitMath.scala 32:10] + node _T_107 = bits(_T_97, 3, 3) @[CircuitMath.scala 32:12] + node _T_109 = bits(_T_97, 2, 2) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_97, 1, 1) @[CircuitMath.scala 30:8] + node _T_112 = mux(_T_109, UInt<2>("h02"), _T_111) @[CircuitMath.scala 32:10] + node _T_113 = mux(_T_107, UInt<2>("h03"), _T_112) @[CircuitMath.scala 32:10] + node _T_114 = mux(_T_99, _T_106, _T_113) @[CircuitMath.scala 38:21] + node _T_115 = cat(_T_99, _T_114) @[Cat.scala 30:58] + node _T_116 = mux(_T_75, _T_95, _T_115) @[CircuitMath.scala 38:21] + node _T_117 = cat(_T_75, _T_116) @[Cat.scala 30:58] + node _T_118 = mux(_T_25, _T_71, _T_117) @[CircuitMath.scala 38:21] + node _T_119 = cat(_T_25, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_19, 31, 16) @[CircuitMath.scala 35:17] + node _T_121 = bits(_T_19, 15, 0) @[CircuitMath.scala 36:17] + node _T_123 = neq(_T_120, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_124 = bits(_T_120, 15, 8) @[CircuitMath.scala 35:17] + node _T_125 = bits(_T_120, 7, 0) @[CircuitMath.scala 36:17] + node _T_127 = neq(_T_124, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_128 = bits(_T_124, 7, 4) @[CircuitMath.scala 35:17] + node _T_129 = bits(_T_124, 3, 0) @[CircuitMath.scala 36:17] + node _T_131 = neq(_T_128, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_132 = bits(_T_128, 3, 3) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_128, 2, 2) @[CircuitMath.scala 32:12] + node _T_136 = bits(_T_128, 1, 1) @[CircuitMath.scala 30:8] + node _T_137 = mux(_T_134, UInt<2>("h02"), _T_136) @[CircuitMath.scala 32:10] + node _T_138 = mux(_T_132, UInt<2>("h03"), _T_137) @[CircuitMath.scala 32:10] + node _T_139 = bits(_T_129, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_129, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_129, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = mux(_T_131, _T_138, _T_145) @[CircuitMath.scala 38:21] + node _T_147 = cat(_T_131, _T_146) @[Cat.scala 30:58] + node _T_148 = bits(_T_125, 7, 4) @[CircuitMath.scala 35:17] + node _T_149 = bits(_T_125, 3, 0) @[CircuitMath.scala 36:17] + node _T_151 = neq(_T_148, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_152 = bits(_T_148, 3, 3) @[CircuitMath.scala 32:12] + node _T_154 = bits(_T_148, 2, 2) @[CircuitMath.scala 32:12] + node _T_156 = bits(_T_148, 1, 1) @[CircuitMath.scala 30:8] + node _T_157 = mux(_T_154, UInt<2>("h02"), _T_156) @[CircuitMath.scala 32:10] + node _T_158 = mux(_T_152, UInt<2>("h03"), _T_157) @[CircuitMath.scala 32:10] + node _T_159 = bits(_T_149, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_149, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_149, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = mux(_T_151, _T_158, _T_165) @[CircuitMath.scala 38:21] + node _T_167 = cat(_T_151, _T_166) @[Cat.scala 30:58] + node _T_168 = mux(_T_127, _T_147, _T_167) @[CircuitMath.scala 38:21] + node _T_169 = cat(_T_127, _T_168) @[Cat.scala 30:58] + node _T_170 = bits(_T_121, 15, 8) @[CircuitMath.scala 35:17] + node _T_171 = bits(_T_121, 7, 0) @[CircuitMath.scala 36:17] + node _T_173 = neq(_T_170, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_174 = bits(_T_170, 7, 4) @[CircuitMath.scala 35:17] + node _T_175 = bits(_T_170, 3, 0) @[CircuitMath.scala 36:17] + node _T_177 = neq(_T_174, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_178 = bits(_T_174, 3, 3) @[CircuitMath.scala 32:12] + node _T_180 = bits(_T_174, 2, 2) @[CircuitMath.scala 32:12] + node _T_182 = bits(_T_174, 1, 1) @[CircuitMath.scala 30:8] + node _T_183 = mux(_T_180, UInt<2>("h02"), _T_182) @[CircuitMath.scala 32:10] + node _T_184 = mux(_T_178, UInt<2>("h03"), _T_183) @[CircuitMath.scala 32:10] + node _T_185 = bits(_T_175, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_175, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_175, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = mux(_T_177, _T_184, _T_191) @[CircuitMath.scala 38:21] + node _T_193 = cat(_T_177, _T_192) @[Cat.scala 30:58] + node _T_194 = bits(_T_171, 7, 4) @[CircuitMath.scala 35:17] + node _T_195 = bits(_T_171, 3, 0) @[CircuitMath.scala 36:17] + node _T_197 = neq(_T_194, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_198 = bits(_T_194, 3, 3) @[CircuitMath.scala 32:12] + node _T_200 = bits(_T_194, 2, 2) @[CircuitMath.scala 32:12] + node _T_202 = bits(_T_194, 1, 1) @[CircuitMath.scala 30:8] + node _T_203 = mux(_T_200, UInt<2>("h02"), _T_202) @[CircuitMath.scala 32:10] + node _T_204 = mux(_T_198, UInt<2>("h03"), _T_203) @[CircuitMath.scala 32:10] + node _T_205 = bits(_T_195, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_195, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_195, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = mux(_T_197, _T_204, _T_211) @[CircuitMath.scala 38:21] + node _T_213 = cat(_T_197, _T_212) @[Cat.scala 30:58] + node _T_214 = mux(_T_173, _T_193, _T_213) @[CircuitMath.scala 38:21] + node _T_215 = cat(_T_173, _T_214) @[Cat.scala 30:58] + node _T_216 = mux(_T_123, _T_169, _T_215) @[CircuitMath.scala 38:21] + node _T_217 = cat(_T_123, _T_216) @[Cat.scala 30:58] + node _T_218 = mux(_T_21, _T_119, _T_217) @[CircuitMath.scala 38:21] + node _T_219 = cat(_T_21, _T_218) @[Cat.scala 30:58] + node normCount = not(_T_219) @[INToRecFN.scala 57:21] + node _T_220 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] + node normAbsIn = bits(_T_220, 63, 0) @[INToRecFN.scala 58:39] + node _T_222 = bits(normAbsIn, 11, 10) @[INToRecFN.scala 63:26] + node _T_223 = bits(normAbsIn, 9, 0) @[INToRecFN.scala 64:26] + node _T_225 = neq(_T_223, UInt<1>("h00")) @[INToRecFN.scala 64:55] + node roundBits = cat(_T_222, _T_225) @[Cat.scala 30:58] + node _T_226 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] + node roundInexact = neq(_T_226, UInt<1>("h00")) @[INToRecFN.scala 72:40] + node _T_228 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] + node _T_229 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] + node _T_230 = not(_T_229) @[INToRecFN.scala 75:29] + node _T_232 = eq(_T_230, UInt<1>("h00")) @[INToRecFN.scala 75:29] + node _T_233 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] + node _T_234 = not(_T_233) @[INToRecFN.scala 75:53] + node _T_236 = eq(_T_234, UInt<1>("h00")) @[INToRecFN.scala 75:53] + node _T_237 = or(_T_232, _T_236) @[INToRecFN.scala 75:34] + node _T_239 = mux(_T_228, _T_237, UInt<1>("h00")) @[INToRecFN.scala 74:12] + node _T_240 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] + node _T_241 = and(sign, roundInexact) @[INToRecFN.scala 79:18] + node _T_243 = mux(_T_240, _T_241, UInt<1>("h00")) @[INToRecFN.scala 78:12] + node _T_244 = or(_T_239, _T_243) @[INToRecFN.scala 77:11] + node _T_245 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] + node _T_247 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] + node _T_248 = and(_T_247, roundInexact) @[INToRecFN.scala 83:20] + node _T_250 = mux(_T_245, _T_248, UInt<1>("h00")) @[INToRecFN.scala 82:12] + node round = or(_T_244, _T_250) @[INToRecFN.scala 81:11] + node _T_252 = bits(normAbsIn, 63, 11) @[INToRecFN.scala 89:34] + node unroundedNorm = cat(UInt<1>("h00"), _T_252) @[Cat.scala 30:58] + node _T_255 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] + node _T_256 = tail(_T_255, 1) @[INToRecFN.scala 94:48] + node roundedNorm = mux(round, _T_256, unroundedNorm) @[INToRecFN.scala 94:26] + node _T_257 = not(normCount) @[INToRecFN.scala 97:24] + node unroundedExp = cat(UInt<4>("h00"), _T_257) @[Cat.scala 30:58] + node _T_260 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 30:58] + node _T_261 = bits(roundedNorm, 53, 53) @[INToRecFN.scala 106:65] + node _T_262 = add(_T_260, _T_261) @[INToRecFN.scala 106:52] + node roundedExp = tail(_T_262, 1) @[INToRecFN.scala 106:52] + node _T_263 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] + node _T_265 = bits(roundedExp, 10, 0) @[INToRecFN.scala 115:27] + node _T_266 = mux(UInt<1>("h00"), UInt<11>("h0400"), _T_265) @[INToRecFN.scala 113:16] + node expOut = cat(_T_263, _T_266) @[Cat.scala 30:58] + node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] + node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] + node _T_267 = bits(roundedNorm, 51, 0) @[INToRecFN.scala 122:44] + node _T_268 = cat(sign, expOut) @[Cat.scala 30:58] + node _T_269 = cat(_T_268, _T_267) @[Cat.scala 30:58] + io.out <= _T_269 @[INToRecFN.scala 122:12] + node _T_272 = cat(UInt<1>("h00"), inexact) @[Cat.scala 30:58] + node _T_273 = cat(UInt<2>("h00"), overflow) @[Cat.scala 30:58] + node _T_274 = cat(_T_273, _T_272) @[Cat.scala 30:58] + io.exceptionFlags <= _T_274 @[INToRecFN.scala 123:23] + + module IntToFP : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_132 <= io.in.valid @[Valid.scala 47:18] + reg _T_155 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[Reg.scala 34:16] + when io.in.valid : @[Reg.scala 35:19] + _T_155 <- io.in.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 42:21] + in is invalid @[Valid.scala 42:21] + in.valid <= _T_132 @[Valid.scala 43:17] + in.bits <- _T_155 @[Valid.scala 44:16] + wire mux : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 360:17] + mux is invalid @[FPU.scala 360:17] + mux.exc <= UInt<1>("h00") @[FPU.scala 361:11] + node _T_276 = bits(in.bits.in1, 31, 31) @[recFNFromFN.scala 47:22] + node _T_277 = bits(in.bits.in1, 30, 23) @[recFNFromFN.scala 48:23] + node _T_278 = bits(in.bits.in1, 22, 0) @[recFNFromFN.scala 49:25] + node _T_280 = eq(_T_277, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_282 = eq(_T_278, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_283 = and(_T_280, _T_282) @[recFNFromFN.scala 53:34] + node _T_284 = shl(_T_278, 9) @[recFNFromFN.scala 56:26] + node _T_285 = bits(_T_284, 31, 16) @[CircuitMath.scala 35:17] + node _T_286 = bits(_T_284, 15, 0) @[CircuitMath.scala 36:17] + node _T_288 = neq(_T_285, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_289 = bits(_T_285, 15, 8) @[CircuitMath.scala 35:17] + node _T_290 = bits(_T_285, 7, 0) @[CircuitMath.scala 36:17] + node _T_292 = neq(_T_289, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_293 = bits(_T_289, 7, 4) @[CircuitMath.scala 35:17] + node _T_294 = bits(_T_289, 3, 0) @[CircuitMath.scala 36:17] + node _T_296 = neq(_T_293, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_297 = bits(_T_293, 3, 3) @[CircuitMath.scala 32:12] + node _T_299 = bits(_T_293, 2, 2) @[CircuitMath.scala 32:12] + node _T_301 = bits(_T_293, 1, 1) @[CircuitMath.scala 30:8] + node _T_302 = mux(_T_299, UInt<2>("h02"), _T_301) @[CircuitMath.scala 32:10] + node _T_303 = mux(_T_297, UInt<2>("h03"), _T_302) @[CircuitMath.scala 32:10] + node _T_304 = bits(_T_294, 3, 3) @[CircuitMath.scala 32:12] + node _T_306 = bits(_T_294, 2, 2) @[CircuitMath.scala 32:12] + node _T_308 = bits(_T_294, 1, 1) @[CircuitMath.scala 30:8] + node _T_309 = mux(_T_306, UInt<2>("h02"), _T_308) @[CircuitMath.scala 32:10] + node _T_310 = mux(_T_304, UInt<2>("h03"), _T_309) @[CircuitMath.scala 32:10] + node _T_311 = mux(_T_296, _T_303, _T_310) @[CircuitMath.scala 38:21] + node _T_312 = cat(_T_296, _T_311) @[Cat.scala 30:58] + node _T_313 = bits(_T_290, 7, 4) @[CircuitMath.scala 35:17] + node _T_314 = bits(_T_290, 3, 0) @[CircuitMath.scala 36:17] + node _T_316 = neq(_T_313, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_317 = bits(_T_313, 3, 3) @[CircuitMath.scala 32:12] + node _T_319 = bits(_T_313, 2, 2) @[CircuitMath.scala 32:12] + node _T_321 = bits(_T_313, 1, 1) @[CircuitMath.scala 30:8] + node _T_322 = mux(_T_319, UInt<2>("h02"), _T_321) @[CircuitMath.scala 32:10] + node _T_323 = mux(_T_317, UInt<2>("h03"), _T_322) @[CircuitMath.scala 32:10] + node _T_324 = bits(_T_314, 3, 3) @[CircuitMath.scala 32:12] + node _T_326 = bits(_T_314, 2, 2) @[CircuitMath.scala 32:12] + node _T_328 = bits(_T_314, 1, 1) @[CircuitMath.scala 30:8] + node _T_329 = mux(_T_326, UInt<2>("h02"), _T_328) @[CircuitMath.scala 32:10] + node _T_330 = mux(_T_324, UInt<2>("h03"), _T_329) @[CircuitMath.scala 32:10] + node _T_331 = mux(_T_316, _T_323, _T_330) @[CircuitMath.scala 38:21] + node _T_332 = cat(_T_316, _T_331) @[Cat.scala 30:58] + node _T_333 = mux(_T_292, _T_312, _T_332) @[CircuitMath.scala 38:21] + node _T_334 = cat(_T_292, _T_333) @[Cat.scala 30:58] + node _T_335 = bits(_T_286, 15, 8) @[CircuitMath.scala 35:17] + node _T_336 = bits(_T_286, 7, 0) @[CircuitMath.scala 36:17] + node _T_338 = neq(_T_335, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_339 = bits(_T_335, 7, 4) @[CircuitMath.scala 35:17] + node _T_340 = bits(_T_335, 3, 0) @[CircuitMath.scala 36:17] + node _T_342 = neq(_T_339, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_343 = bits(_T_339, 3, 3) @[CircuitMath.scala 32:12] + node _T_345 = bits(_T_339, 2, 2) @[CircuitMath.scala 32:12] + node _T_347 = bits(_T_339, 1, 1) @[CircuitMath.scala 30:8] + node _T_348 = mux(_T_345, UInt<2>("h02"), _T_347) @[CircuitMath.scala 32:10] + node _T_349 = mux(_T_343, UInt<2>("h03"), _T_348) @[CircuitMath.scala 32:10] + node _T_350 = bits(_T_340, 3, 3) @[CircuitMath.scala 32:12] + node _T_352 = bits(_T_340, 2, 2) @[CircuitMath.scala 32:12] + node _T_354 = bits(_T_340, 1, 1) @[CircuitMath.scala 30:8] + node _T_355 = mux(_T_352, UInt<2>("h02"), _T_354) @[CircuitMath.scala 32:10] + node _T_356 = mux(_T_350, UInt<2>("h03"), _T_355) @[CircuitMath.scala 32:10] + node _T_357 = mux(_T_342, _T_349, _T_356) @[CircuitMath.scala 38:21] + node _T_358 = cat(_T_342, _T_357) @[Cat.scala 30:58] + node _T_359 = bits(_T_336, 7, 4) @[CircuitMath.scala 35:17] + node _T_360 = bits(_T_336, 3, 0) @[CircuitMath.scala 36:17] + node _T_362 = neq(_T_359, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_363 = bits(_T_359, 3, 3) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_359, 2, 2) @[CircuitMath.scala 32:12] + node _T_367 = bits(_T_359, 1, 1) @[CircuitMath.scala 30:8] + node _T_368 = mux(_T_365, UInt<2>("h02"), _T_367) @[CircuitMath.scala 32:10] + node _T_369 = mux(_T_363, UInt<2>("h03"), _T_368) @[CircuitMath.scala 32:10] + node _T_370 = bits(_T_360, 3, 3) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_360, 2, 2) @[CircuitMath.scala 32:12] + node _T_374 = bits(_T_360, 1, 1) @[CircuitMath.scala 30:8] + node _T_375 = mux(_T_372, UInt<2>("h02"), _T_374) @[CircuitMath.scala 32:10] + node _T_376 = mux(_T_370, UInt<2>("h03"), _T_375) @[CircuitMath.scala 32:10] + node _T_377 = mux(_T_362, _T_369, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_362, _T_377) @[Cat.scala 30:58] + node _T_379 = mux(_T_338, _T_358, _T_378) @[CircuitMath.scala 38:21] + node _T_380 = cat(_T_338, _T_379) @[Cat.scala 30:58] + node _T_381 = mux(_T_288, _T_334, _T_380) @[CircuitMath.scala 38:21] + node _T_382 = cat(_T_288, _T_381) @[Cat.scala 30:58] + node _T_383 = not(_T_382) @[recFNFromFN.scala 56:13] + node _T_384 = dshl(_T_278, _T_383) @[recFNFromFN.scala 58:25] + node _T_385 = bits(_T_384, 21, 0) @[recFNFromFN.scala 58:37] + node _T_387 = cat(_T_385, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_392 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 71:12] + node _T_393 = xor(_T_383, _T_392) @[recFNFromFN.scala 62:27] + node _T_394 = mux(_T_280, _T_393, _T_277) @[recFNFromFN.scala 61:16] + node _T_398 = mux(_T_280, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_399 = or(UInt<8>("h080"), _T_398) @[recFNFromFN.scala 64:42] + node _T_400 = add(_T_394, _T_399) @[recFNFromFN.scala 64:15] + node _T_401 = tail(_T_400, 1) @[recFNFromFN.scala 64:15] + node _T_402 = bits(_T_401, 8, 7) @[recFNFromFN.scala 67:25] + node _T_404 = eq(_T_402, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_406 = eq(_T_282, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_407 = and(_T_404, _T_406) @[recFNFromFN.scala 67:63] + node _T_408 = bits(_T_283, 0, 0) @[Bitwise.scala 71:15] + node _T_411 = mux(_T_408, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_412 = shl(_T_411, 6) @[recFNFromFN.scala 71:45] + node _T_413 = not(_T_412) @[recFNFromFN.scala 71:28] + node _T_414 = and(_T_401, _T_413) @[recFNFromFN.scala 71:26] + node _T_415 = shl(_T_407, 6) @[recFNFromFN.scala 72:22] + node _T_416 = or(_T_414, _T_415) @[recFNFromFN.scala 71:64] + node _T_417 = mux(_T_280, _T_387, _T_278) @[recFNFromFN.scala 73:27] + node _T_418 = cat(_T_276, _T_416) @[Cat.scala 30:58] + node _T_419 = cat(_T_418, _T_417) @[Cat.scala 30:58] + mux.data <= _T_419 @[FPU.scala 362:12] + node _T_421 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 363:24] + when _T_421 : @[FPU.scala 363:41] + node _T_422 = bits(in.bits.in1, 63, 63) @[recFNFromFN.scala 47:22] + node _T_423 = bits(in.bits.in1, 62, 52) @[recFNFromFN.scala 48:23] + node _T_424 = bits(in.bits.in1, 51, 0) @[recFNFromFN.scala 49:25] + node _T_426 = eq(_T_423, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_428 = eq(_T_424, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_429 = and(_T_426, _T_428) @[recFNFromFN.scala 53:34] + node _T_430 = shl(_T_424, 12) @[recFNFromFN.scala 56:26] + node _T_431 = bits(_T_430, 63, 32) @[CircuitMath.scala 35:17] + node _T_432 = bits(_T_430, 31, 0) @[CircuitMath.scala 36:17] + node _T_434 = neq(_T_431, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_435 = bits(_T_431, 31, 16) @[CircuitMath.scala 35:17] + node _T_436 = bits(_T_431, 15, 0) @[CircuitMath.scala 36:17] + node _T_438 = neq(_T_435, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_439 = bits(_T_435, 15, 8) @[CircuitMath.scala 35:17] + node _T_440 = bits(_T_435, 7, 0) @[CircuitMath.scala 36:17] + node _T_442 = neq(_T_439, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_443 = bits(_T_439, 7, 4) @[CircuitMath.scala 35:17] + node _T_444 = bits(_T_439, 3, 0) @[CircuitMath.scala 36:17] + node _T_446 = neq(_T_443, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_447 = bits(_T_443, 3, 3) @[CircuitMath.scala 32:12] + node _T_449 = bits(_T_443, 2, 2) @[CircuitMath.scala 32:12] + node _T_451 = bits(_T_443, 1, 1) @[CircuitMath.scala 30:8] + node _T_452 = mux(_T_449, UInt<2>("h02"), _T_451) @[CircuitMath.scala 32:10] + node _T_453 = mux(_T_447, UInt<2>("h03"), _T_452) @[CircuitMath.scala 32:10] + node _T_454 = bits(_T_444, 3, 3) @[CircuitMath.scala 32:12] + node _T_456 = bits(_T_444, 2, 2) @[CircuitMath.scala 32:12] + node _T_458 = bits(_T_444, 1, 1) @[CircuitMath.scala 30:8] + node _T_459 = mux(_T_456, UInt<2>("h02"), _T_458) @[CircuitMath.scala 32:10] + node _T_460 = mux(_T_454, UInt<2>("h03"), _T_459) @[CircuitMath.scala 32:10] + node _T_461 = mux(_T_446, _T_453, _T_460) @[CircuitMath.scala 38:21] + node _T_462 = cat(_T_446, _T_461) @[Cat.scala 30:58] + node _T_463 = bits(_T_440, 7, 4) @[CircuitMath.scala 35:17] + node _T_464 = bits(_T_440, 3, 0) @[CircuitMath.scala 36:17] + node _T_466 = neq(_T_463, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_467 = bits(_T_463, 3, 3) @[CircuitMath.scala 32:12] + node _T_469 = bits(_T_463, 2, 2) @[CircuitMath.scala 32:12] + node _T_471 = bits(_T_463, 1, 1) @[CircuitMath.scala 30:8] + node _T_472 = mux(_T_469, UInt<2>("h02"), _T_471) @[CircuitMath.scala 32:10] + node _T_473 = mux(_T_467, UInt<2>("h03"), _T_472) @[CircuitMath.scala 32:10] + node _T_474 = bits(_T_464, 3, 3) @[CircuitMath.scala 32:12] + node _T_476 = bits(_T_464, 2, 2) @[CircuitMath.scala 32:12] + node _T_478 = bits(_T_464, 1, 1) @[CircuitMath.scala 30:8] + node _T_479 = mux(_T_476, UInt<2>("h02"), _T_478) @[CircuitMath.scala 32:10] + node _T_480 = mux(_T_474, UInt<2>("h03"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = mux(_T_466, _T_473, _T_480) @[CircuitMath.scala 38:21] + node _T_482 = cat(_T_466, _T_481) @[Cat.scala 30:58] + node _T_483 = mux(_T_442, _T_462, _T_482) @[CircuitMath.scala 38:21] + node _T_484 = cat(_T_442, _T_483) @[Cat.scala 30:58] + node _T_485 = bits(_T_436, 15, 8) @[CircuitMath.scala 35:17] + node _T_486 = bits(_T_436, 7, 0) @[CircuitMath.scala 36:17] + node _T_488 = neq(_T_485, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_489 = bits(_T_485, 7, 4) @[CircuitMath.scala 35:17] + node _T_490 = bits(_T_485, 3, 0) @[CircuitMath.scala 36:17] + node _T_492 = neq(_T_489, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_493 = bits(_T_489, 3, 3) @[CircuitMath.scala 32:12] + node _T_495 = bits(_T_489, 2, 2) @[CircuitMath.scala 32:12] + node _T_497 = bits(_T_489, 1, 1) @[CircuitMath.scala 30:8] + node _T_498 = mux(_T_495, UInt<2>("h02"), _T_497) @[CircuitMath.scala 32:10] + node _T_499 = mux(_T_493, UInt<2>("h03"), _T_498) @[CircuitMath.scala 32:10] + node _T_500 = bits(_T_490, 3, 3) @[CircuitMath.scala 32:12] + node _T_502 = bits(_T_490, 2, 2) @[CircuitMath.scala 32:12] + node _T_504 = bits(_T_490, 1, 1) @[CircuitMath.scala 30:8] + node _T_505 = mux(_T_502, UInt<2>("h02"), _T_504) @[CircuitMath.scala 32:10] + node _T_506 = mux(_T_500, UInt<2>("h03"), _T_505) @[CircuitMath.scala 32:10] + node _T_507 = mux(_T_492, _T_499, _T_506) @[CircuitMath.scala 38:21] + node _T_508 = cat(_T_492, _T_507) @[Cat.scala 30:58] + node _T_509 = bits(_T_486, 7, 4) @[CircuitMath.scala 35:17] + node _T_510 = bits(_T_486, 3, 0) @[CircuitMath.scala 36:17] + node _T_512 = neq(_T_509, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_513 = bits(_T_509, 3, 3) @[CircuitMath.scala 32:12] + node _T_515 = bits(_T_509, 2, 2) @[CircuitMath.scala 32:12] + node _T_517 = bits(_T_509, 1, 1) @[CircuitMath.scala 30:8] + node _T_518 = mux(_T_515, UInt<2>("h02"), _T_517) @[CircuitMath.scala 32:10] + node _T_519 = mux(_T_513, UInt<2>("h03"), _T_518) @[CircuitMath.scala 32:10] + node _T_520 = bits(_T_510, 3, 3) @[CircuitMath.scala 32:12] + node _T_522 = bits(_T_510, 2, 2) @[CircuitMath.scala 32:12] + node _T_524 = bits(_T_510, 1, 1) @[CircuitMath.scala 30:8] + node _T_525 = mux(_T_522, UInt<2>("h02"), _T_524) @[CircuitMath.scala 32:10] + node _T_526 = mux(_T_520, UInt<2>("h03"), _T_525) @[CircuitMath.scala 32:10] + node _T_527 = mux(_T_512, _T_519, _T_526) @[CircuitMath.scala 38:21] + node _T_528 = cat(_T_512, _T_527) @[Cat.scala 30:58] + node _T_529 = mux(_T_488, _T_508, _T_528) @[CircuitMath.scala 38:21] + node _T_530 = cat(_T_488, _T_529) @[Cat.scala 30:58] + node _T_531 = mux(_T_438, _T_484, _T_530) @[CircuitMath.scala 38:21] + node _T_532 = cat(_T_438, _T_531) @[Cat.scala 30:58] + node _T_533 = bits(_T_432, 31, 16) @[CircuitMath.scala 35:17] + node _T_534 = bits(_T_432, 15, 0) @[CircuitMath.scala 36:17] + node _T_536 = neq(_T_533, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_537 = bits(_T_533, 15, 8) @[CircuitMath.scala 35:17] + node _T_538 = bits(_T_533, 7, 0) @[CircuitMath.scala 36:17] + node _T_540 = neq(_T_537, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_541 = bits(_T_537, 7, 4) @[CircuitMath.scala 35:17] + node _T_542 = bits(_T_537, 3, 0) @[CircuitMath.scala 36:17] + node _T_544 = neq(_T_541, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_545 = bits(_T_541, 3, 3) @[CircuitMath.scala 32:12] + node _T_547 = bits(_T_541, 2, 2) @[CircuitMath.scala 32:12] + node _T_549 = bits(_T_541, 1, 1) @[CircuitMath.scala 30:8] + node _T_550 = mux(_T_547, UInt<2>("h02"), _T_549) @[CircuitMath.scala 32:10] + node _T_551 = mux(_T_545, UInt<2>("h03"), _T_550) @[CircuitMath.scala 32:10] + node _T_552 = bits(_T_542, 3, 3) @[CircuitMath.scala 32:12] + node _T_554 = bits(_T_542, 2, 2) @[CircuitMath.scala 32:12] + node _T_556 = bits(_T_542, 1, 1) @[CircuitMath.scala 30:8] + node _T_557 = mux(_T_554, UInt<2>("h02"), _T_556) @[CircuitMath.scala 32:10] + node _T_558 = mux(_T_552, UInt<2>("h03"), _T_557) @[CircuitMath.scala 32:10] + node _T_559 = mux(_T_544, _T_551, _T_558) @[CircuitMath.scala 38:21] + node _T_560 = cat(_T_544, _T_559) @[Cat.scala 30:58] + node _T_561 = bits(_T_538, 7, 4) @[CircuitMath.scala 35:17] + node _T_562 = bits(_T_538, 3, 0) @[CircuitMath.scala 36:17] + node _T_564 = neq(_T_561, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_565 = bits(_T_561, 3, 3) @[CircuitMath.scala 32:12] + node _T_567 = bits(_T_561, 2, 2) @[CircuitMath.scala 32:12] + node _T_569 = bits(_T_561, 1, 1) @[CircuitMath.scala 30:8] + node _T_570 = mux(_T_567, UInt<2>("h02"), _T_569) @[CircuitMath.scala 32:10] + node _T_571 = mux(_T_565, UInt<2>("h03"), _T_570) @[CircuitMath.scala 32:10] + node _T_572 = bits(_T_562, 3, 3) @[CircuitMath.scala 32:12] + node _T_574 = bits(_T_562, 2, 2) @[CircuitMath.scala 32:12] + node _T_576 = bits(_T_562, 1, 1) @[CircuitMath.scala 30:8] + node _T_577 = mux(_T_574, UInt<2>("h02"), _T_576) @[CircuitMath.scala 32:10] + node _T_578 = mux(_T_572, UInt<2>("h03"), _T_577) @[CircuitMath.scala 32:10] + node _T_579 = mux(_T_564, _T_571, _T_578) @[CircuitMath.scala 38:21] + node _T_580 = cat(_T_564, _T_579) @[Cat.scala 30:58] + node _T_581 = mux(_T_540, _T_560, _T_580) @[CircuitMath.scala 38:21] + node _T_582 = cat(_T_540, _T_581) @[Cat.scala 30:58] + node _T_583 = bits(_T_534, 15, 8) @[CircuitMath.scala 35:17] + node _T_584 = bits(_T_534, 7, 0) @[CircuitMath.scala 36:17] + node _T_586 = neq(_T_583, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_587 = bits(_T_583, 7, 4) @[CircuitMath.scala 35:17] + node _T_588 = bits(_T_583, 3, 0) @[CircuitMath.scala 36:17] + node _T_590 = neq(_T_587, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_591 = bits(_T_587, 3, 3) @[CircuitMath.scala 32:12] + node _T_593 = bits(_T_587, 2, 2) @[CircuitMath.scala 32:12] + node _T_595 = bits(_T_587, 1, 1) @[CircuitMath.scala 30:8] + node _T_596 = mux(_T_593, UInt<2>("h02"), _T_595) @[CircuitMath.scala 32:10] + node _T_597 = mux(_T_591, UInt<2>("h03"), _T_596) @[CircuitMath.scala 32:10] + node _T_598 = bits(_T_588, 3, 3) @[CircuitMath.scala 32:12] + node _T_600 = bits(_T_588, 2, 2) @[CircuitMath.scala 32:12] + node _T_602 = bits(_T_588, 1, 1) @[CircuitMath.scala 30:8] + node _T_603 = mux(_T_600, UInt<2>("h02"), _T_602) @[CircuitMath.scala 32:10] + node _T_604 = mux(_T_598, UInt<2>("h03"), _T_603) @[CircuitMath.scala 32:10] + node _T_605 = mux(_T_590, _T_597, _T_604) @[CircuitMath.scala 38:21] + node _T_606 = cat(_T_590, _T_605) @[Cat.scala 30:58] + node _T_607 = bits(_T_584, 7, 4) @[CircuitMath.scala 35:17] + node _T_608 = bits(_T_584, 3, 0) @[CircuitMath.scala 36:17] + node _T_610 = neq(_T_607, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_611 = bits(_T_607, 3, 3) @[CircuitMath.scala 32:12] + node _T_613 = bits(_T_607, 2, 2) @[CircuitMath.scala 32:12] + node _T_615 = bits(_T_607, 1, 1) @[CircuitMath.scala 30:8] + node _T_616 = mux(_T_613, UInt<2>("h02"), _T_615) @[CircuitMath.scala 32:10] + node _T_617 = mux(_T_611, UInt<2>("h03"), _T_616) @[CircuitMath.scala 32:10] + node _T_618 = bits(_T_608, 3, 3) @[CircuitMath.scala 32:12] + node _T_620 = bits(_T_608, 2, 2) @[CircuitMath.scala 32:12] + node _T_622 = bits(_T_608, 1, 1) @[CircuitMath.scala 30:8] + node _T_623 = mux(_T_620, UInt<2>("h02"), _T_622) @[CircuitMath.scala 32:10] + node _T_624 = mux(_T_618, UInt<2>("h03"), _T_623) @[CircuitMath.scala 32:10] + node _T_625 = mux(_T_610, _T_617, _T_624) @[CircuitMath.scala 38:21] + node _T_626 = cat(_T_610, _T_625) @[Cat.scala 30:58] + node _T_627 = mux(_T_586, _T_606, _T_626) @[CircuitMath.scala 38:21] + node _T_628 = cat(_T_586, _T_627) @[Cat.scala 30:58] + node _T_629 = mux(_T_536, _T_582, _T_628) @[CircuitMath.scala 38:21] + node _T_630 = cat(_T_536, _T_629) @[Cat.scala 30:58] + node _T_631 = mux(_T_434, _T_532, _T_630) @[CircuitMath.scala 38:21] + node _T_632 = cat(_T_434, _T_631) @[Cat.scala 30:58] + node _T_633 = not(_T_632) @[recFNFromFN.scala 56:13] + node _T_634 = dshl(_T_424, _T_633) @[recFNFromFN.scala 58:25] + node _T_635 = bits(_T_634, 50, 0) @[recFNFromFN.scala 58:37] + node _T_637 = cat(_T_635, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_642 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 71:12] + node _T_643 = xor(_T_633, _T_642) @[recFNFromFN.scala 62:27] + node _T_644 = mux(_T_426, _T_643, _T_423) @[recFNFromFN.scala 61:16] + node _T_648 = mux(_T_426, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_649 = or(UInt<11>("h0400"), _T_648) @[recFNFromFN.scala 64:42] + node _T_650 = add(_T_644, _T_649) @[recFNFromFN.scala 64:15] + node _T_651 = tail(_T_650, 1) @[recFNFromFN.scala 64:15] + node _T_652 = bits(_T_651, 11, 10) @[recFNFromFN.scala 67:25] + node _T_654 = eq(_T_652, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_656 = eq(_T_428, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_657 = and(_T_654, _T_656) @[recFNFromFN.scala 67:63] + node _T_658 = bits(_T_429, 0, 0) @[Bitwise.scala 71:15] + node _T_661 = mux(_T_658, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_662 = shl(_T_661, 9) @[recFNFromFN.scala 71:45] + node _T_663 = not(_T_662) @[recFNFromFN.scala 71:28] + node _T_664 = and(_T_651, _T_663) @[recFNFromFN.scala 71:26] + node _T_665 = shl(_T_657, 9) @[recFNFromFN.scala 72:22] + node _T_666 = or(_T_664, _T_665) @[recFNFromFN.scala 71:64] + node _T_667 = mux(_T_426, _T_637, _T_424) @[recFNFromFN.scala 73:27] + node _T_668 = cat(_T_422, _T_666) @[Cat.scala 30:58] + node _T_669 = cat(_T_668, _T_667) @[Cat.scala 30:58] + mux.data <= _T_669 @[FPU.scala 364:14] + skip @[FPU.scala 363:41] + node _T_670 = asSInt(in.bits.in1) @[FPU.scala 370:39] + wire _T_671 : SInt + _T_671 is invalid + _T_671 <= _T_670 + node _T_672 = bits(in.bits.in1, 31, 0) @[FPU.scala 372:33] + node _T_673 = bits(in.bits.typ, 1, 1) @[Package.scala 44:13] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[FPU.scala 373:49] + when _T_675 : @[FPU.scala 373:56] + node _T_676 = bits(in.bits.typ, 0, 0) @[FPU.scala 374:31] + node _T_677 = cvt(_T_672) @[FPU.scala 374:45] + node _T_678 = asSInt(_T_672) @[FPU.scala 374:60] + node _T_679 = mux(_T_676, _T_677, _T_678) @[FPU.scala 374:19] + _T_671 <= _T_679 @[FPU.scala 374:13] + skip @[FPU.scala 373:56] + node intValue = asUInt(_T_671) @[FPU.scala 377:9] + node _T_682 = and(in.bits.cmd, UInt<3>("h04")) @[FPU.scala 380:21] + node _T_683 = eq(UInt<1>("h00"), _T_682) @[FPU.scala 380:21] + when _T_683 : @[FPU.scala 380:38] + inst INToRecFN of INToRecFN @[FPU.scala 381:21] + INToRecFN.io is invalid + INToRecFN.clock <= clock + INToRecFN.reset <= reset + node _T_684 = bits(in.bits.typ, 0, 0) @[FPU.scala 382:36] + node _T_685 = not(_T_684) @[FPU.scala 382:24] + INToRecFN.io.signedIn <= _T_685 @[FPU.scala 382:21] + INToRecFN.io.in <= intValue @[FPU.scala 383:15] + INToRecFN.io.roundingMode <= in.bits.rm @[FPU.scala 384:25] + inst INToRecFN_1 of INToRecFN_1 @[FPU.scala 391:25] + INToRecFN_1.io is invalid + INToRecFN_1.clock <= clock + INToRecFN_1.reset <= reset + node _T_686 = bits(in.bits.typ, 0, 0) @[FPU.scala 392:40] + node _T_687 = not(_T_686) @[FPU.scala 392:28] + INToRecFN_1.io.signedIn <= _T_687 @[FPU.scala 392:25] + INToRecFN_1.io.in <= intValue @[FPU.scala 393:19] + INToRecFN_1.io.roundingMode <= in.bits.rm @[FPU.scala 394:29] + node _T_688 = shr(INToRecFN_1.io.out, 33) @[FPU.scala 396:36] + node _T_689 = cat(_T_688, INToRecFN.io.out) @[Cat.scala 30:58] + mux.data <= _T_689 @[FPU.scala 396:18] + mux.exc <= INToRecFN.io.exceptionFlags @[FPU.scala 397:17] + node _T_691 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 398:15] + when _T_691 : @[FPU.scala 398:32] + mux.data <= INToRecFN_1.io.out @[FPU.scala 399:20] + mux.exc <= INToRecFN_1.io.exceptionFlags @[FPU.scala 400:19] + skip @[FPU.scala 398:32] + skip @[FPU.scala 380:38] + reg _T_694 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_694 <= in.valid @[Valid.scala 47:18] + reg _T_698 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when in.valid : @[Reg.scala 35:19] + _T_698 <- mux @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_710 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_710 is invalid @[Valid.scala 42:21] + _T_710.valid <= _T_694 @[Valid.scala 43:17] + _T_710.bits <- _T_698 @[Valid.scala 44:16] + io.out <- _T_710 @[FPU.scala 405:12] + + module RoundRawFNToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) @[RoundRawFNToRecFN.scala 88:54] + node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) @[RoundRawFNToRecFN.scala 89:54] + node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @[RoundRawFNToRecFN.scala 90:54] + node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) @[RoundRawFNToRecFN.scala 91:54] + node _T_26 = and(roundingMode_min, io.in.sign) @[RoundRawFNToRecFN.scala 94:27] + node _T_28 = eq(io.in.sign, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 94:66] + node _T_29 = and(roundingMode_max, _T_28) @[RoundRawFNToRecFN.scala 94:63] + node roundMagUp = or(_T_26, _T_29) @[RoundRawFNToRecFN.scala 94:42] + node doShiftSigDown1 = bits(io.in.sig, 26, 26) @[RoundRawFNToRecFN.scala 98:36] + node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h00"))) @[RoundRawFNToRecFN.scala 99:32] + node _T_31 = bits(isNegExp, 0, 0) @[Bitwise.scala 71:15] + node _T_34 = mux(_T_31, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_35 = bits(io.in.sExp, 8, 0) @[RoundRawFNToRecFN.scala 103:31] + node _T_36 = not(_T_35) @[primitives.scala 50:21] + node _T_37 = bits(_T_36, 8, 8) @[primitives.scala 56:25] + node _T_38 = bits(_T_36, 7, 0) @[primitives.scala 57:26] + node _T_39 = bits(_T_38, 7, 7) @[primitives.scala 56:25] + node _T_40 = bits(_T_38, 6, 0) @[primitives.scala 57:26] + node _T_41 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_42 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_45 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_42) @[primitives.scala 68:52] + node _T_46 = bits(_T_45, 63, 42) @[primitives.scala 69:26] + node _T_47 = bits(_T_46, 15, 0) @[Bitwise.scala 108:18] + node _T_50 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_51 = xor(UInt<16>("h0ffff"), _T_50) @[Bitwise.scala 101:21] + node _T_52 = shr(_T_47, 8) @[Bitwise.scala 102:21] + node _T_53 = and(_T_52, _T_51) @[Bitwise.scala 102:31] + node _T_54 = bits(_T_47, 7, 0) @[Bitwise.scala 102:46] + node _T_55 = shl(_T_54, 8) @[Bitwise.scala 102:65] + node _T_56 = not(_T_51) @[Bitwise.scala 102:77] + node _T_57 = and(_T_55, _T_56) @[Bitwise.scala 102:75] + node _T_58 = or(_T_53, _T_57) @[Bitwise.scala 102:39] + node _T_59 = bits(_T_51, 11, 0) @[Bitwise.scala 101:28] + node _T_60 = shl(_T_59, 4) @[Bitwise.scala 101:47] + node _T_61 = xor(_T_51, _T_60) @[Bitwise.scala 101:21] + node _T_62 = shr(_T_58, 4) @[Bitwise.scala 102:21] + node _T_63 = and(_T_62, _T_61) @[Bitwise.scala 102:31] + node _T_64 = bits(_T_58, 11, 0) @[Bitwise.scala 102:46] + node _T_65 = shl(_T_64, 4) @[Bitwise.scala 102:65] + node _T_66 = not(_T_61) @[Bitwise.scala 102:77] + node _T_67 = and(_T_65, _T_66) @[Bitwise.scala 102:75] + node _T_68 = or(_T_63, _T_67) @[Bitwise.scala 102:39] + node _T_69 = bits(_T_61, 13, 0) @[Bitwise.scala 101:28] + node _T_70 = shl(_T_69, 2) @[Bitwise.scala 101:47] + node _T_71 = xor(_T_61, _T_70) @[Bitwise.scala 101:21] + node _T_72 = shr(_T_68, 2) @[Bitwise.scala 102:21] + node _T_73 = and(_T_72, _T_71) @[Bitwise.scala 102:31] + node _T_74 = bits(_T_68, 13, 0) @[Bitwise.scala 102:46] + node _T_75 = shl(_T_74, 2) @[Bitwise.scala 102:65] + node _T_76 = not(_T_71) @[Bitwise.scala 102:77] + node _T_77 = and(_T_75, _T_76) @[Bitwise.scala 102:75] + node _T_78 = or(_T_73, _T_77) @[Bitwise.scala 102:39] + node _T_79 = bits(_T_71, 14, 0) @[Bitwise.scala 101:28] + node _T_80 = shl(_T_79, 1) @[Bitwise.scala 101:47] + node _T_81 = xor(_T_71, _T_80) @[Bitwise.scala 101:21] + node _T_82 = shr(_T_78, 1) @[Bitwise.scala 102:21] + node _T_83 = and(_T_82, _T_81) @[Bitwise.scala 102:31] + node _T_84 = bits(_T_78, 14, 0) @[Bitwise.scala 102:46] + node _T_85 = shl(_T_84, 1) @[Bitwise.scala 102:65] + node _T_86 = not(_T_81) @[Bitwise.scala 102:77] + node _T_87 = and(_T_85, _T_86) @[Bitwise.scala 102:75] + node _T_88 = or(_T_83, _T_87) @[Bitwise.scala 102:39] + node _T_89 = bits(_T_46, 21, 16) @[Bitwise.scala 108:44] + node _T_90 = bits(_T_89, 3, 0) @[Bitwise.scala 108:18] + node _T_91 = bits(_T_90, 1, 0) @[Bitwise.scala 108:18] + node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 108:18] + node _T_93 = bits(_T_91, 1, 1) @[Bitwise.scala 108:44] + node _T_94 = cat(_T_92, _T_93) @[Cat.scala 30:58] + node _T_95 = bits(_T_90, 3, 2) @[Bitwise.scala 108:44] + node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 108:18] + node _T_97 = bits(_T_95, 1, 1) @[Bitwise.scala 108:44] + node _T_98 = cat(_T_96, _T_97) @[Cat.scala 30:58] + node _T_99 = cat(_T_94, _T_98) @[Cat.scala 30:58] + node _T_100 = bits(_T_89, 5, 4) @[Bitwise.scala 108:44] + node _T_101 = bits(_T_100, 0, 0) @[Bitwise.scala 108:18] + node _T_102 = bits(_T_100, 1, 1) @[Bitwise.scala 108:44] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 30:58] + node _T_104 = cat(_T_99, _T_103) @[Cat.scala 30:58] + node _T_105 = cat(_T_88, _T_104) @[Cat.scala 30:58] + node _T_106 = not(_T_105) @[primitives.scala 65:36] + node _T_107 = mux(_T_41, UInt<1>("h00"), _T_106) @[primitives.scala 65:21] + node _T_108 = not(_T_107) @[primitives.scala 65:17] + node _T_110 = cat(_T_108, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_111 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_112 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_114 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_112) @[primitives.scala 68:52] + node _T_115 = bits(_T_114, 2, 0) @[primitives.scala 69:26] + node _T_116 = bits(_T_115, 1, 0) @[Bitwise.scala 108:18] + node _T_117 = bits(_T_116, 0, 0) @[Bitwise.scala 108:18] + node _T_118 = bits(_T_116, 1, 1) @[Bitwise.scala 108:44] + node _T_119 = cat(_T_117, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_115, 2, 2) @[Bitwise.scala 108:44] + node _T_121 = cat(_T_119, _T_120) @[Cat.scala 30:58] + node _T_123 = mux(_T_111, _T_121, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_124 = mux(_T_39, _T_110, _T_123) @[primitives.scala 61:20] + node _T_126 = mux(_T_37, _T_124, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_127 = or(_T_34, _T_126) @[RoundRawFNToRecFN.scala 101:42] + node _T_128 = or(_T_127, doShiftSigDown1) @[RoundRawFNToRecFN.scala 106:19] + node roundMask = cat(_T_128, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_130 = cat(isNegExp, roundMask) @[Cat.scala 30:58] + node shiftedRoundMask = shr(_T_130, 1) @[RoundRawFNToRecFN.scala 109:52] + node _T_131 = not(shiftedRoundMask) @[RoundRawFNToRecFN.scala 110:24] + node roundPosMask = and(_T_131, roundMask) @[RoundRawFNToRecFN.scala 110:42] + node _T_132 = and(io.in.sig, roundPosMask) @[RoundRawFNToRecFN.scala 111:34] + node roundPosBit = neq(_T_132, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 111:50] + node _T_134 = and(io.in.sig, shiftedRoundMask) @[RoundRawFNToRecFN.scala 112:36] + node anyRoundExtra = neq(_T_134, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 112:56] + node anyRound = or(roundPosBit, anyRoundExtra) @[RoundRawFNToRecFN.scala 113:32] + node _T_136 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 116:40] + node _T_137 = and(roundMagUp, anyRound) @[RoundRawFNToRecFN.scala 117:29] + node _T_138 = or(_T_136, _T_137) @[RoundRawFNToRecFN.scala 116:56] + node _T_139 = or(io.in.sig, roundMask) @[RoundRawFNToRecFN.scala 118:26] + node _T_140 = shr(_T_139, 2) @[RoundRawFNToRecFN.scala 118:38] + node _T_142 = add(_T_140, UInt<1>("h01")) @[RoundRawFNToRecFN.scala 118:43] + node _T_143 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 119:48] + node _T_145 = eq(anyRoundExtra, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 120:26] + node _T_146 = and(_T_143, _T_145) @[RoundRawFNToRecFN.scala 119:63] + node _T_147 = shr(roundMask, 1) @[RoundRawFNToRecFN.scala 121:31] + node _T_149 = mux(_T_146, _T_147, UInt<26>("h00")) @[RoundRawFNToRecFN.scala 119:21] + node _T_150 = not(_T_149) @[RoundRawFNToRecFN.scala 119:17] + node _T_151 = and(_T_142, _T_150) @[RoundRawFNToRecFN.scala 118:55] + node _T_152 = not(roundMask) @[RoundRawFNToRecFN.scala 124:26] + node _T_153 = and(io.in.sig, _T_152) @[RoundRawFNToRecFN.scala 124:24] + node _T_154 = shr(_T_153, 2) @[RoundRawFNToRecFN.scala 124:37] + node roundedSig = mux(_T_138, _T_151, _T_154) @[RoundRawFNToRecFN.scala 116:12] + node _T_155 = shr(roundedSig, 24) @[RoundRawFNToRecFN.scala 127:48] + node _T_156 = cvt(_T_155) @[RoundRawFNToRecFN.scala 127:60] + node sRoundedExp = add(io.in.sExp, _T_156) @[RoundRawFNToRecFN.scala 127:34] + node common_expOut = bits(sRoundedExp, 8, 0) @[RoundRawFNToRecFN.scala 129:36] + node _T_157 = bits(roundedSig, 23, 1) @[RoundRawFNToRecFN.scala 132:23] + node _T_158 = bits(roundedSig, 22, 0) @[RoundRawFNToRecFN.scala 133:23] + node common_fractOut = mux(doShiftSigDown1, _T_157, _T_158) @[RoundRawFNToRecFN.scala 131:12] + node _T_159 = shr(sRoundedExp, 7) @[RoundRawFNToRecFN.scala 136:39] + node common_overflow = geq(_T_159, asSInt(UInt<3>("h03"))) @[RoundRawFNToRecFN.scala 136:56] + node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) @[RoundRawFNToRecFN.scala 138:46] + node _T_164 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) @[RoundRawFNToRecFN.scala 142:21] + node _T_165 = lt(io.in.sExp, _T_164) @[RoundRawFNToRecFN.scala 141:25] + node common_underflow = and(anyRound, _T_165) @[RoundRawFNToRecFN.scala 140:18] + node isNaNOut = or(io.invalidExc, io.in.isNaN) @[RoundRawFNToRecFN.scala 147:34] + node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[RoundRawFNToRecFN.scala 148:49] + node _T_167 = eq(isNaNOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:22] + node _T_169 = eq(notNaN_isSpecialInfOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:36] + node _T_170 = and(_T_167, _T_169) @[RoundRawFNToRecFN.scala 149:33] + node _T_172 = eq(io.in.isZero, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:64] + node commonCase = and(_T_170, _T_172) @[RoundRawFNToRecFN.scala 149:61] + node overflow = and(commonCase, common_overflow) @[RoundRawFNToRecFN.scala 150:32] + node underflow = and(commonCase, common_underflow) @[RoundRawFNToRecFN.scala 151:32] + node _T_173 = and(commonCase, anyRound) @[RoundRawFNToRecFN.scala 152:43] + node inexact = or(overflow, _T_173) @[RoundRawFNToRecFN.scala 152:28] + node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[RoundRawFNToRecFN.scala 154:57] + node _T_174 = and(commonCase, common_totalUnderflow) @[RoundRawFNToRecFN.scala 155:42] + node pegMinNonzeroMagOut = and(_T_174, roundMagUp) @[RoundRawFNToRecFN.scala 155:67] + node _T_175 = and(commonCase, overflow) @[RoundRawFNToRecFN.scala 156:41] + node _T_177 = eq(overflow_roundMagUp, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 156:56] + node pegMaxFiniteMagOut = and(_T_175, _T_177) @[RoundRawFNToRecFN.scala 156:53] + node _T_178 = and(overflow, overflow_roundMagUp) @[RoundRawFNToRecFN.scala 158:45] + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _T_178) @[RoundRawFNToRecFN.scala 158:32] + node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) @[RoundRawFNToRecFN.scala 160:22] + node _T_180 = or(io.in.isZero, common_totalUnderflow) @[RoundRawFNToRecFN.scala 163:32] + node _T_183 = mux(_T_180, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 163:18] + node _T_184 = not(_T_183) @[RoundRawFNToRecFN.scala 163:14] + node _T_185 = and(common_expOut, _T_184) @[RoundRawFNToRecFN.scala 162:24] + node _T_187 = not(UInt<9>("h06b")) @[RoundRawFNToRecFN.scala 168:19] + node _T_189 = mux(pegMinNonzeroMagOut, _T_187, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 167:18] + node _T_190 = not(_T_189) @[RoundRawFNToRecFN.scala 167:14] + node _T_191 = and(_T_185, _T_190) @[RoundRawFNToRecFN.scala 166:17] + node _T_194 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 171:18] + node _T_195 = not(_T_194) @[RoundRawFNToRecFN.scala 171:14] + node _T_196 = and(_T_191, _T_195) @[RoundRawFNToRecFN.scala 170:17] + node _T_199 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 175:18] + node _T_200 = not(_T_199) @[RoundRawFNToRecFN.scala 175:14] + node _T_201 = and(_T_196, _T_200) @[RoundRawFNToRecFN.scala 174:17] + node _T_204 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 179:16] + node _T_205 = or(_T_201, _T_204) @[RoundRawFNToRecFN.scala 178:18] + node _T_208 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 183:16] + node _T_209 = or(_T_205, _T_208) @[RoundRawFNToRecFN.scala 182:15] + node _T_212 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 187:16] + node _T_213 = or(_T_209, _T_212) @[RoundRawFNToRecFN.scala 186:15] + node _T_216 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 188:16] + node expOut = or(_T_213, _T_216) @[RoundRawFNToRecFN.scala 187:71] + node _T_217 = or(common_totalUnderflow, isNaNOut) @[RoundRawFNToRecFN.scala 190:35] + node _T_219 = shl(UInt<1>("h01"), 22) @[RoundRawFNToRecFN.scala 191:34] + node _T_221 = mux(isNaNOut, _T_219, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 191:16] + node _T_222 = mux(_T_217, _T_221, common_fractOut) @[RoundRawFNToRecFN.scala 190:12] + node _T_223 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_226 = mux(_T_223, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_222, _T_226) @[RoundRawFNToRecFN.scala 193:11] + node _T_227 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_228 = cat(_T_227, fractOut) @[Cat.scala 30:58] + io.out <= _T_228 @[RoundRawFNToRecFN.scala 196:12] + node _T_229 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_230 = cat(io.invalidExc, io.infiniteExc) @[Cat.scala 30:58] + node _T_231 = cat(_T_230, overflow) @[Cat.scala 30:58] + node _T_232 = cat(_T_231, _T_229) @[Cat.scala 30:58] + io.exceptionFlags <= _T_232 @[RoundRawFNToRecFN.scala 197:23] + + module RecFNToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_10 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + node _T_63 = lt(_T_48, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] + node _T_64 = bits(_T_48, 12, 9) @[resizeRawFN.scala 61:33] + node _T_66 = neq(_T_64, UInt<1>("h00")) @[resizeRawFN.scala 61:65] + node _T_71 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_73 = cat(_T_71, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_74 = bits(_T_48, 8, 0) @[resizeRawFN.scala 63:33] + node _T_75 = mux(_T_66, _T_73, _T_74) @[resizeRawFN.scala 61:25] + node _T_76 = cat(_T_63, _T_75) @[Cat.scala 30:58] + node _T_77 = asSInt(_T_76) @[resizeRawFN.scala 65:20] + outRawFloat.sExp <= _T_77 @[resizeRawFN.scala 56:18] + node _T_78 = bits(_T_24.sig, 55, 30) @[resizeRawFN.scala 71:28] + node _T_79 = bits(_T_24.sig, 29, 0) @[resizeRawFN.scala 72:28] + node _T_81 = neq(_T_79, UInt<1>("h00")) @[resizeRawFN.scala 72:56] + node _T_82 = cat(_T_78, _T_81) @[Cat.scala 30:58] + outRawFloat.sig <= _T_82 @[resizeRawFN.scala 67:17] + node _T_83 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] + node _T_85 = eq(_T_83, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_85) @[RoundRawFNToRecFN.scala 61:46] + inst RoundRawFNToRecFN of RoundRawFNToRecFN @[RecFNToRecFN.scala 102:19] + RoundRawFNToRecFN.io is invalid + RoundRawFNToRecFN.clock <= clock + RoundRawFNToRecFN.reset <= reset + RoundRawFNToRecFN.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] + RoundRawFNToRecFN.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] + RoundRawFNToRecFN.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] + RoundRawFNToRecFN.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] + io.out <= RoundRawFNToRecFN.io.out @[RecFNToRecFN.scala 107:16] + io.exceptionFlags <= RoundRawFNToRecFN.io.exceptionFlags @[RecFNToRecFN.scala 108:27] + + module RecFNToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_10 = bits(io.in, 31, 23) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 8, 6) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 8, 7) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 32, 32) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 6, 6) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 6, 6) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 22, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0700"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + outRawFloat.sExp <= _T_48 @[resizeRawFN.scala 56:18] + node _T_62 = shl(_T_24.sig, 29) @[resizeRawFN.scala 69:24] + outRawFloat.sig <= _T_62 @[resizeRawFN.scala 67:17] + node _T_63 = bits(outRawFloat.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_65) @[RoundRawFNToRecFN.scala 61:46] + node _T_67 = eq(outRawFloat.isNaN, UInt<1>("h00")) @[RecFNToRecFN.scala 69:40] + node _T_68 = and(outRawFloat.sign, _T_67) @[RecFNToRecFN.scala 69:37] + node _T_69 = bits(outRawFloat.sExp, 11, 0) @[RecFNToRecFN.scala 71:30] + node _T_72 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 72:22] + node _T_73 = not(_T_72) @[RecFNToRecFN.scala 72:18] + node _T_74 = and(_T_69, _T_73) @[RecFNToRecFN.scala 71:47] + node _T_75 = or(outRawFloat.isZero, outRawFloat.isInf) @[RecFNToRecFN.scala 76:42] + node _T_78 = mux(_T_75, UInt<12>("h0200"), UInt<1>("h00")) @[RecFNToRecFN.scala 76:22] + node _T_79 = not(_T_78) @[RecFNToRecFN.scala 76:18] + node _T_80 = and(_T_74, _T_79) @[RecFNToRecFN.scala 75:21] + node _T_83 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 80:20] + node _T_84 = or(_T_80, _T_83) @[RecFNToRecFN.scala 79:22] + node _T_87 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) @[RecFNToRecFN.scala 84:20] + node _T_88 = or(_T_84, _T_87) @[RecFNToRecFN.scala 83:19] + node _T_90 = shl(UInt<1>("h01"), 51) @[RecFNToRecFN.scala 90:24] + node _T_91 = bits(outRawFloat.sig, 53, 2) @[RecFNToRecFN.scala 91:32] + node _T_92 = mux(outRawFloat.isNaN, _T_90, _T_91) @[RecFNToRecFN.scala 89:16] + node _T_93 = cat(_T_68, _T_88) @[Cat.scala 30:58] + node _T_94 = cat(_T_93, _T_92) @[Cat.scala 30:58] + io.out <= _T_94 @[RecFNToRecFN.scala 93:16] + node _T_96 = cat(invalidExc, UInt<4>("h00")) @[Cat.scala 30:58] + io.exceptionFlags <= _T_96 @[RecFNToRecFN.scala 94:27] + + module FPToFP : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} + + io is invalid + io is invalid + reg _T_134 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_134 <= io.in.valid @[Valid.scala 47:18] + reg _T_157 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[Reg.scala 34:16] + when io.in.valid : @[Reg.scala 35:19] + _T_157 <- io.in.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 42:21] + in is invalid @[Valid.scala 42:21] + in.valid <= _T_134 @[Valid.scala 43:17] + in.bits <- _T_157 @[Valid.scala 44:16] + node _T_272 = bits(in.bits.rm, 1, 1) @[FPU.scala 417:33] + node _T_273 = xor(in.bits.in1, in.bits.in2) @[FPU.scala 417:50] + node _T_274 = bits(in.bits.rm, 0, 0) @[FPU.scala 417:79] + node _T_275 = not(in.bits.in2) @[FPU.scala 417:84] + node _T_276 = mux(_T_274, _T_275, in.bits.in2) @[FPU.scala 417:68] + node signNum = mux(_T_272, _T_273, _T_276) @[FPU.scala 417:22] + node _T_277 = bits(signNum, 32, 32) @[FPU.scala 418:30] + node _T_278 = bits(in.bits.in1, 31, 0) @[FPU.scala 418:47] + node fsgnj_s = cat(_T_277, _T_278) @[Cat.scala 30:58] + node _T_279 = shr(in.bits.in1, 33) @[FPU.scala 421:54] + node _T_280 = cat(_T_279, fsgnj_s) @[Cat.scala 30:58] + node _T_281 = bits(signNum, 64, 64) @[FPU.scala 422:49] + node _T_282 = bits(in.bits.in1, 63, 0) @[FPU.scala 422:66] + node _T_283 = cat(_T_281, _T_282) @[Cat.scala 30:58] + node fsgnj = mux(in.bits.single, _T_280, _T_283) @[FPU.scala 421:21] + wire mux : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 424:19] + mux is invalid @[FPU.scala 424:19] + mux.exc <= UInt<1>("h00") @[FPU.scala 425:13] + mux.data <= fsgnj @[FPU.scala 426:14] + node _T_292 = and(in.bits.cmd, UInt<4>("h0d")) @[FPU.scala 428:23] + node _T_293 = eq(UInt<3>("h05"), _T_292) @[FPU.scala 428:23] + when _T_293 : @[FPU.scala 428:40] + node _T_294 = bits(in.bits.in1, 31, 29) @[FPU.scala 226:7] + node _T_295 = not(_T_294) @[FPU.scala 226:58] + node _T_297 = eq(_T_295, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_298 = bits(in.bits.in2, 31, 29) @[FPU.scala 226:7] + node _T_299 = not(_T_298) @[FPU.scala 226:58] + node _T_301 = eq(_T_299, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_302 = bits(in.bits.in1, 31, 29) @[FPU.scala 226:7] + node _T_303 = not(_T_302) @[FPU.scala 226:58] + node _T_305 = eq(_T_303, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_306 = bits(in.bits.in1, 22, 22) @[FPU.scala 231:46] + node _T_308 = eq(_T_306, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_309 = and(_T_305, _T_308) @[FPU.scala 231:40] + node _T_310 = bits(in.bits.in2, 31, 29) @[FPU.scala 226:7] + node _T_311 = not(_T_310) @[FPU.scala 226:58] + node _T_313 = eq(_T_311, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_314 = bits(in.bits.in2, 22, 22) @[FPU.scala 231:46] + node _T_316 = eq(_T_314, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_317 = and(_T_313, _T_316) @[FPU.scala 231:40] + node _T_318 = or(_T_309, _T_317) @[FPU.scala 434:31] + node _T_319 = and(_T_297, _T_301) @[FPU.scala 435:43] + node _T_320 = or(_T_318, _T_319) @[FPU.scala 435:32] + node _T_323 = add(UInt<33>("h0e0400000"), UInt<65>("h0e008000000000000")) @[FPU.scala 436:100] + node _T_324 = tail(_T_323, 1) @[FPU.scala 436:100] + node _T_325 = bits(in.bits.rm, 0, 0) @[FPU.scala 437:30] + node _T_326 = neq(_T_325, io.lt) @[FPU.scala 437:34] + node _T_328 = eq(_T_297, UInt<1>("h00")) @[FPU.scala 437:47] + node _T_329 = and(_T_326, _T_328) @[FPU.scala 437:44] + node _T_330 = or(_T_301, _T_329) @[FPU.scala 437:17] + node _T_331 = bits(in.bits.in1, 63, 61) @[FPU.scala 226:7] + node _T_332 = not(_T_331) @[FPU.scala 226:58] + node _T_334 = eq(_T_332, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_335 = bits(in.bits.in2, 63, 61) @[FPU.scala 226:7] + node _T_336 = not(_T_335) @[FPU.scala 226:58] + node _T_338 = eq(_T_336, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_339 = bits(in.bits.in1, 63, 61) @[FPU.scala 226:7] + node _T_340 = not(_T_339) @[FPU.scala 226:58] + node _T_342 = eq(_T_340, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_343 = bits(in.bits.in1, 51, 51) @[FPU.scala 231:46] + node _T_345 = eq(_T_343, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_346 = and(_T_342, _T_345) @[FPU.scala 231:40] + node _T_347 = bits(in.bits.in2, 63, 61) @[FPU.scala 226:7] + node _T_348 = not(_T_347) @[FPU.scala 226:58] + node _T_350 = eq(_T_348, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_351 = bits(in.bits.in2, 51, 51) @[FPU.scala 231:46] + node _T_353 = eq(_T_351, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_354 = and(_T_350, _T_353) @[FPU.scala 231:40] + node _T_355 = or(_T_346, _T_354) @[FPU.scala 434:31] + node _T_356 = and(_T_334, _T_338) @[FPU.scala 435:43] + node _T_357 = or(_T_355, _T_356) @[FPU.scala 435:32] + node _T_359 = bits(in.bits.rm, 0, 0) @[FPU.scala 437:30] + node _T_360 = neq(_T_359, io.lt) @[FPU.scala 437:34] + node _T_362 = eq(_T_334, UInt<1>("h00")) @[FPU.scala 437:47] + node _T_363 = and(_T_360, _T_362) @[FPU.scala 437:44] + node _T_364 = or(_T_338, _T_363) @[FPU.scala 437:17] + node _T_365 = mux(in.bits.single, _T_330, _T_364) @[Misc.scala 42:9] + node _T_366 = mux(in.bits.single, _T_318, _T_355) @[Misc.scala 42:36] + node _T_367 = mux(in.bits.single, _T_320, _T_357) @[Misc.scala 42:63] + node _T_368 = mux(in.bits.single, _T_324, UInt<65>("h0e008000000000000")) @[Misc.scala 42:90] + node _T_369 = shl(_T_366, 4) @[FPU.scala 443:28] + mux.exc <= _T_369 @[FPU.scala 443:15] + node _T_370 = mux(_T_365, in.bits.in1, in.bits.in2) @[FPU.scala 444:42] + node _T_371 = mux(_T_367, _T_368, _T_370) @[FPU.scala 444:22] + mux.data <= _T_371 @[FPU.scala 444:16] + skip @[FPU.scala 428:40] + node _T_374 = and(in.bits.cmd, UInt<3>("h04")) @[FPU.scala 450:25] + node _T_375 = eq(UInt<1>("h00"), _T_374) @[FPU.scala 450:25] + when _T_375 : @[FPU.scala 450:42] + inst RecFNToRecFN of RecFNToRecFN @[FPU.scala 451:25] + RecFNToRecFN.io is invalid + RecFNToRecFN.clock <= clock + RecFNToRecFN.reset <= reset + RecFNToRecFN.io.in <= in.bits.in1 @[FPU.scala 452:19] + RecFNToRecFN.io.roundingMode <= in.bits.rm @[FPU.scala 453:29] + inst RecFNToRecFN_1 of RecFNToRecFN_1 @[FPU.scala 455:25] + RecFNToRecFN_1.io is invalid + RecFNToRecFN_1.clock <= clock + RecFNToRecFN_1.reset <= reset + RecFNToRecFN_1.io.in <= in.bits.in1 @[FPU.scala 456:19] + RecFNToRecFN_1.io.roundingMode <= in.bits.rm @[FPU.scala 457:29] + when in.bits.single : @[FPU.scala 459:31] + node _T_376 = shr(RecFNToRecFN_1.io.out, 33) @[FPU.scala 460:38] + node _T_377 = cat(_T_376, RecFNToRecFN.io.out) @[Cat.scala 30:58] + mux.data <= _T_377 @[FPU.scala 460:20] + mux.exc <= RecFNToRecFN.io.exceptionFlags @[FPU.scala 461:19] + skip @[FPU.scala 459:31] + node _T_379 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 459:31] + when _T_379 : @[FPU.scala 462:21] + mux.data <= RecFNToRecFN_1.io.out @[FPU.scala 463:20] + mux.exc <= RecFNToRecFN_1.io.exceptionFlags @[FPU.scala 464:19] + skip @[FPU.scala 462:21] + skip @[FPU.scala 450:42] + reg _T_382 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_382 <= in.valid @[Valid.scala 47:18] + reg _T_386 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when in.valid : @[Reg.scala 35:19] + _T_386 <- mux @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_398 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_398 is invalid @[Valid.scala 42:21] + _T_398.valid <= _T_382 @[Valid.scala 43:17] + _T_398.bits <- _T_386 @[Valid.scala 44:16] + io.out <- _T_398 @[FPU.scala 469:10] + + module MulAddRecFN_preMul_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} + + io is invalid + io is invalid + node signA = bits(io.a, 64, 64) @[MulAddRecFN.scala 102:22] + node expA = bits(io.a, 63, 52) @[MulAddRecFN.scala 103:22] + node fractA = bits(io.a, 51, 0) @[MulAddRecFN.scala 104:22] + node _T_52 = bits(expA, 11, 9) @[MulAddRecFN.scala 105:24] + node isZeroA = eq(_T_52, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] + node _T_55 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] + node sigA = cat(_T_55, fractA) @[Cat.scala 30:58] + node signB = bits(io.b, 64, 64) @[MulAddRecFN.scala 108:22] + node expB = bits(io.b, 63, 52) @[MulAddRecFN.scala 109:22] + node fractB = bits(io.b, 51, 0) @[MulAddRecFN.scala 110:22] + node _T_56 = bits(expB, 11, 9) @[MulAddRecFN.scala 111:24] + node isZeroB = eq(_T_56, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] + node _T_59 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] + node sigB = cat(_T_59, fractB) @[Cat.scala 30:58] + node _T_60 = bits(io.c, 64, 64) @[MulAddRecFN.scala 114:23] + node _T_61 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] + node opSignC = xor(_T_60, _T_61) @[MulAddRecFN.scala 114:45] + node expC = bits(io.c, 63, 52) @[MulAddRecFN.scala 115:22] + node fractC = bits(io.c, 51, 0) @[MulAddRecFN.scala 116:22] + node _T_62 = bits(expC, 11, 9) @[MulAddRecFN.scala 117:24] + node isZeroC = eq(_T_62, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] + node _T_65 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] + node sigC = cat(_T_65, fractC) @[Cat.scala 30:58] + node _T_66 = xor(signA, signB) @[MulAddRecFN.scala 122:26] + node _T_67 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] + node signProd = xor(_T_66, _T_67) @[MulAddRecFN.scala 122:34] + node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] + node _T_68 = bits(expB, 11, 11) @[MulAddRecFN.scala 125:34] + node _T_70 = eq(_T_68, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] + node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 71:15] + node _T_74 = mux(_T_71, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_75 = bits(expB, 10, 0) @[MulAddRecFN.scala 125:51] + node _T_76 = cat(_T_74, _T_75) @[Cat.scala 30:58] + node _T_77 = add(expA, _T_76) @[MulAddRecFN.scala 125:14] + node _T_78 = tail(_T_77, 1) @[MulAddRecFN.scala 125:14] + node _T_80 = add(_T_78, UInt<6>("h038")) @[MulAddRecFN.scala 125:70] + node sExpAlignedProd = tail(_T_80, 1) @[MulAddRecFN.scala 125:70] + node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] + node _T_81 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] + node _T_82 = asUInt(_T_81) @[MulAddRecFN.scala 132:42] + node sNatCAlignDist = tail(_T_82, 1) @[MulAddRecFN.scala 132:42] + node _T_83 = bits(sNatCAlignDist, 13, 13) @[MulAddRecFN.scala 133:56] + node CAlignDist_floor = or(isZeroProd, _T_83) @[MulAddRecFN.scala 133:39] + node _T_84 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 135:44] + node _T_86 = eq(_T_84, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] + node CAlignDist_0 = or(CAlignDist_floor, _T_86) @[MulAddRecFN.scala 135:26] + node _T_88 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] + node _T_89 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 139:33] + node _T_91 = lt(_T_89, UInt<6>("h036")) @[MulAddRecFN.scala 139:51] + node _T_92 = or(CAlignDist_floor, _T_91) @[MulAddRecFN.scala 138:31] + node isCDominant = and(_T_88, _T_92) @[MulAddRecFN.scala 137:19] + node _T_94 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 143:31] + node _T_96 = lt(_T_94, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:49] + node _T_97 = bits(sNatCAlignDist, 7, 0) @[MulAddRecFN.scala 144:31] + node _T_99 = mux(_T_96, _T_97, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:16] + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), _T_99) @[MulAddRecFN.scala 141:12] + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] + node _T_100 = bits(CAlignDist, 7, 7) @[primitives.scala 56:25] + node _T_101 = bits(CAlignDist, 6, 0) @[primitives.scala 57:26] + node _T_102 = bits(_T_101, 6, 6) @[primitives.scala 56:25] + node _T_103 = bits(_T_101, 5, 0) @[primitives.scala 57:26] + node _T_106 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_103) @[primitives.scala 68:52] + node _T_107 = bits(_T_106, 63, 31) @[primitives.scala 69:26] + node _T_108 = bits(_T_107, 31, 0) @[Bitwise.scala 108:18] + node _T_111 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_112 = xor(UInt<32>("h0ffffffff"), _T_111) @[Bitwise.scala 101:21] + node _T_113 = shr(_T_108, 16) @[Bitwise.scala 102:21] + node _T_114 = and(_T_113, _T_112) @[Bitwise.scala 102:31] + node _T_115 = bits(_T_108, 15, 0) @[Bitwise.scala 102:46] + node _T_116 = shl(_T_115, 16) @[Bitwise.scala 102:65] + node _T_117 = not(_T_112) @[Bitwise.scala 102:77] + node _T_118 = and(_T_116, _T_117) @[Bitwise.scala 102:75] + node _T_119 = or(_T_114, _T_118) @[Bitwise.scala 102:39] + node _T_120 = bits(_T_112, 23, 0) @[Bitwise.scala 101:28] + node _T_121 = shl(_T_120, 8) @[Bitwise.scala 101:47] + node _T_122 = xor(_T_112, _T_121) @[Bitwise.scala 101:21] + node _T_123 = shr(_T_119, 8) @[Bitwise.scala 102:21] + node _T_124 = and(_T_123, _T_122) @[Bitwise.scala 102:31] + node _T_125 = bits(_T_119, 23, 0) @[Bitwise.scala 102:46] + node _T_126 = shl(_T_125, 8) @[Bitwise.scala 102:65] + node _T_127 = not(_T_122) @[Bitwise.scala 102:77] + node _T_128 = and(_T_126, _T_127) @[Bitwise.scala 102:75] + node _T_129 = or(_T_124, _T_128) @[Bitwise.scala 102:39] + node _T_130 = bits(_T_122, 27, 0) @[Bitwise.scala 101:28] + node _T_131 = shl(_T_130, 4) @[Bitwise.scala 101:47] + node _T_132 = xor(_T_122, _T_131) @[Bitwise.scala 101:21] + node _T_133 = shr(_T_129, 4) @[Bitwise.scala 102:21] + node _T_134 = and(_T_133, _T_132) @[Bitwise.scala 102:31] + node _T_135 = bits(_T_129, 27, 0) @[Bitwise.scala 102:46] + node _T_136 = shl(_T_135, 4) @[Bitwise.scala 102:65] + node _T_137 = not(_T_132) @[Bitwise.scala 102:77] + node _T_138 = and(_T_136, _T_137) @[Bitwise.scala 102:75] + node _T_139 = or(_T_134, _T_138) @[Bitwise.scala 102:39] + node _T_140 = bits(_T_132, 29, 0) @[Bitwise.scala 101:28] + node _T_141 = shl(_T_140, 2) @[Bitwise.scala 101:47] + node _T_142 = xor(_T_132, _T_141) @[Bitwise.scala 101:21] + node _T_143 = shr(_T_139, 2) @[Bitwise.scala 102:21] + node _T_144 = and(_T_143, _T_142) @[Bitwise.scala 102:31] + node _T_145 = bits(_T_139, 29, 0) @[Bitwise.scala 102:46] + node _T_146 = shl(_T_145, 2) @[Bitwise.scala 102:65] + node _T_147 = not(_T_142) @[Bitwise.scala 102:77] + node _T_148 = and(_T_146, _T_147) @[Bitwise.scala 102:75] + node _T_149 = or(_T_144, _T_148) @[Bitwise.scala 102:39] + node _T_150 = bits(_T_142, 30, 0) @[Bitwise.scala 101:28] + node _T_151 = shl(_T_150, 1) @[Bitwise.scala 101:47] + node _T_152 = xor(_T_142, _T_151) @[Bitwise.scala 101:21] + node _T_153 = shr(_T_149, 1) @[Bitwise.scala 102:21] + node _T_154 = and(_T_153, _T_152) @[Bitwise.scala 102:31] + node _T_155 = bits(_T_149, 30, 0) @[Bitwise.scala 102:46] + node _T_156 = shl(_T_155, 1) @[Bitwise.scala 102:65] + node _T_157 = not(_T_152) @[Bitwise.scala 102:77] + node _T_158 = and(_T_156, _T_157) @[Bitwise.scala 102:75] + node _T_159 = or(_T_154, _T_158) @[Bitwise.scala 102:39] + node _T_160 = bits(_T_107, 32, 32) @[Bitwise.scala 108:44] + node _T_161 = cat(_T_159, _T_160) @[Cat.scala 30:58] + node _T_162 = not(_T_161) @[primitives.scala 65:36] + node _T_163 = mux(_T_102, UInt<1>("h00"), _T_162) @[primitives.scala 65:21] + node _T_164 = not(_T_163) @[primitives.scala 65:17] + node _T_166 = cat(_T_164, UInt<20>("h0fffff")) @[Cat.scala 30:58] + node _T_167 = bits(_T_101, 6, 6) @[primitives.scala 56:25] + node _T_168 = bits(_T_101, 5, 0) @[primitives.scala 57:26] + node _T_170 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_168) @[primitives.scala 68:52] + node _T_171 = bits(_T_170, 19, 0) @[primitives.scala 69:26] + node _T_172 = bits(_T_171, 15, 0) @[Bitwise.scala 108:18] + node _T_175 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_176 = xor(UInt<16>("h0ffff"), _T_175) @[Bitwise.scala 101:21] + node _T_177 = shr(_T_172, 8) @[Bitwise.scala 102:21] + node _T_178 = and(_T_177, _T_176) @[Bitwise.scala 102:31] + node _T_179 = bits(_T_172, 7, 0) @[Bitwise.scala 102:46] + node _T_180 = shl(_T_179, 8) @[Bitwise.scala 102:65] + node _T_181 = not(_T_176) @[Bitwise.scala 102:77] + node _T_182 = and(_T_180, _T_181) @[Bitwise.scala 102:75] + node _T_183 = or(_T_178, _T_182) @[Bitwise.scala 102:39] + node _T_184 = bits(_T_176, 11, 0) @[Bitwise.scala 101:28] + node _T_185 = shl(_T_184, 4) @[Bitwise.scala 101:47] + node _T_186 = xor(_T_176, _T_185) @[Bitwise.scala 101:21] + node _T_187 = shr(_T_183, 4) @[Bitwise.scala 102:21] + node _T_188 = and(_T_187, _T_186) @[Bitwise.scala 102:31] + node _T_189 = bits(_T_183, 11, 0) @[Bitwise.scala 102:46] + node _T_190 = shl(_T_189, 4) @[Bitwise.scala 102:65] + node _T_191 = not(_T_186) @[Bitwise.scala 102:77] + node _T_192 = and(_T_190, _T_191) @[Bitwise.scala 102:75] + node _T_193 = or(_T_188, _T_192) @[Bitwise.scala 102:39] + node _T_194 = bits(_T_186, 13, 0) @[Bitwise.scala 101:28] + node _T_195 = shl(_T_194, 2) @[Bitwise.scala 101:47] + node _T_196 = xor(_T_186, _T_195) @[Bitwise.scala 101:21] + node _T_197 = shr(_T_193, 2) @[Bitwise.scala 102:21] + node _T_198 = and(_T_197, _T_196) @[Bitwise.scala 102:31] + node _T_199 = bits(_T_193, 13, 0) @[Bitwise.scala 102:46] + node _T_200 = shl(_T_199, 2) @[Bitwise.scala 102:65] + node _T_201 = not(_T_196) @[Bitwise.scala 102:77] + node _T_202 = and(_T_200, _T_201) @[Bitwise.scala 102:75] + node _T_203 = or(_T_198, _T_202) @[Bitwise.scala 102:39] + node _T_204 = bits(_T_196, 14, 0) @[Bitwise.scala 101:28] + node _T_205 = shl(_T_204, 1) @[Bitwise.scala 101:47] + node _T_206 = xor(_T_196, _T_205) @[Bitwise.scala 101:21] + node _T_207 = shr(_T_203, 1) @[Bitwise.scala 102:21] + node _T_208 = and(_T_207, _T_206) @[Bitwise.scala 102:31] + node _T_209 = bits(_T_203, 14, 0) @[Bitwise.scala 102:46] + node _T_210 = shl(_T_209, 1) @[Bitwise.scala 102:65] + node _T_211 = not(_T_206) @[Bitwise.scala 102:77] + node _T_212 = and(_T_210, _T_211) @[Bitwise.scala 102:75] + node _T_213 = or(_T_208, _T_212) @[Bitwise.scala 102:39] + node _T_214 = bits(_T_171, 19, 16) @[Bitwise.scala 108:44] + node _T_215 = bits(_T_214, 1, 0) @[Bitwise.scala 108:18] + node _T_216 = bits(_T_215, 0, 0) @[Bitwise.scala 108:18] + node _T_217 = bits(_T_215, 1, 1) @[Bitwise.scala 108:44] + node _T_218 = cat(_T_216, _T_217) @[Cat.scala 30:58] + node _T_219 = bits(_T_214, 3, 2) @[Bitwise.scala 108:44] + node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 108:18] + node _T_221 = bits(_T_219, 1, 1) @[Bitwise.scala 108:44] + node _T_222 = cat(_T_220, _T_221) @[Cat.scala 30:58] + node _T_223 = cat(_T_218, _T_222) @[Cat.scala 30:58] + node _T_224 = cat(_T_213, _T_223) @[Cat.scala 30:58] + node _T_226 = mux(_T_167, _T_224, UInt<1>("h00")) @[primitives.scala 59:20] + node CExtraMask = mux(_T_100, _T_166, _T_226) @[primitives.scala 61:20] + node _T_227 = not(sigC) @[MulAddRecFN.scala 151:34] + node negSigC = mux(doSubMags, _T_227, sigC) @[MulAddRecFN.scala 151:22] + node _T_228 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_231 = mux(_T_228, UInt<108>("h0fffffffffffffffffffffffffff"), UInt<108>("h00")) @[Bitwise.scala 71:12] + node _T_232 = cat(doSubMags, negSigC) @[Cat.scala 30:58] + node _T_233 = cat(_T_232, _T_231) @[Cat.scala 30:58] + node _T_234 = asSInt(_T_233) @[MulAddRecFN.scala 154:64] + node _T_235 = dshr(_T_234, CAlignDist) @[MulAddRecFN.scala 154:70] + node _T_236 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] + node _T_238 = neq(_T_236, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] + node _T_239 = xor(_T_238, doSubMags) @[MulAddRecFN.scala 156:37] + node _T_240 = asUInt(_T_235) @[Cat.scala 30:58] + node _T_241 = cat(_T_240, _T_239) @[Cat.scala 30:58] + node alignedNegSigC = bits(_T_241, 161, 0) @[MulAddRecFN.scala 157:10] + io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] + io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] + node _T_242 = bits(alignedNegSigC, 106, 1) @[MulAddRecFN.scala 161:33] + io.mulAddC <= _T_242 @[MulAddRecFN.scala 161:16] + node _T_243 = bits(expA, 11, 9) @[MulAddRecFN.scala 163:44] + io.toPostMul.highExpA <= _T_243 @[MulAddRecFN.scala 163:37] + node _T_244 = bits(fractA, 51, 51) @[MulAddRecFN.scala 164:46] + io.toPostMul.isNaN_isQuietNaNA <= _T_244 @[MulAddRecFN.scala 164:37] + node _T_245 = bits(expB, 11, 9) @[MulAddRecFN.scala 165:44] + io.toPostMul.highExpB <= _T_245 @[MulAddRecFN.scala 165:37] + node _T_246 = bits(fractB, 51, 51) @[MulAddRecFN.scala 166:46] + io.toPostMul.isNaN_isQuietNaNB <= _T_246 @[MulAddRecFN.scala 166:37] + io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] + io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] + io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] + node _T_247 = bits(expC, 11, 9) @[MulAddRecFN.scala 170:44] + io.toPostMul.highExpC <= _T_247 @[MulAddRecFN.scala 170:37] + node _T_248 = bits(fractC, 51, 51) @[MulAddRecFN.scala 171:46] + io.toPostMul.isNaN_isQuietNaNC <= _T_248 @[MulAddRecFN.scala 171:37] + io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] + io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] + io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] + node _T_249 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] + io.toPostMul.bit0AlignedNegSigC <= _T_249 @[MulAddRecFN.scala 175:37] + node _T_250 = bits(alignedNegSigC, 161, 107) @[MulAddRecFN.scala 177:23] + io.toPostMul.highAlignedNegSigC <= _T_250 @[MulAddRecFN.scala 176:37] + io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] + io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] + + module MulAddRecFN_postMul_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] + node _T_43 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] + node isSpecialA = eq(_T_43, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] + node _T_45 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] + node _T_47 = eq(_T_45, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] + node isInfA = and(isSpecialA, _T_47) @[MulAddRecFN.scala 209:29] + node _T_48 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] + node isNaNA = and(isSpecialA, _T_48) @[MulAddRecFN.scala 210:29] + node _T_50 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] + node isSigNaNA = and(isNaNA, _T_50) @[MulAddRecFN.scala 211:28] + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] + node _T_52 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] + node isSpecialB = eq(_T_52, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] + node _T_54 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] + node _T_56 = eq(_T_54, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] + node isInfB = and(isSpecialB, _T_56) @[MulAddRecFN.scala 215:29] + node _T_57 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] + node isNaNB = and(isSpecialB, _T_57) @[MulAddRecFN.scala 216:29] + node _T_59 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] + node isSigNaNB = and(isNaNB, _T_59) @[MulAddRecFN.scala 217:28] + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] + node _T_61 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] + node isSpecialC = eq(_T_61, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] + node _T_63 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] + node isInfC = and(isSpecialC, _T_65) @[MulAddRecFN.scala 221:29] + node _T_66 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] + node isNaNC = and(isSpecialC, _T_66) @[MulAddRecFN.scala 222:29] + node _T_68 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] + node isSigNaNC = and(isNaNC, _T_68) @[MulAddRecFN.scala 223:28] + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] + node _T_71 = bits(io.mulAddResult, 106, 106) @[MulAddRecFN.scala 237:32] + node _T_73 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] + node _T_74 = tail(_T_73, 1) @[MulAddRecFN.scala 238:50] + node _T_75 = mux(_T_71, _T_74, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] + node _T_76 = bits(io.mulAddResult, 105, 0) @[MulAddRecFN.scala 241:28] + node _T_77 = cat(_T_75, _T_76) @[Cat.scala 30:58] + node sigSum = cat(_T_77, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 30:58] + node _T_79 = bits(sigSum, 108, 1) @[MulAddRecFN.scala 248:38] + node _T_80 = xor(UInt<108>("h00"), _T_79) @[MulAddRecFN.scala 191:27] + node _T_81 = or(UInt<108>("h00"), _T_79) @[MulAddRecFN.scala 191:37] + node _T_82 = shl(_T_81, 1) @[MulAddRecFN.scala 191:41] + node _T_83 = xor(_T_80, _T_82) @[MulAddRecFN.scala 191:32] + node _T_85 = bits(_T_83, 107, 0) @[primitives.scala 79:35] + node _T_86 = bits(_T_85, 107, 64) @[CircuitMath.scala 35:17] + node _T_87 = bits(_T_85, 63, 0) @[CircuitMath.scala 36:17] + node _T_89 = neq(_T_86, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_90 = bits(_T_86, 43, 32) @[CircuitMath.scala 35:17] + node _T_91 = bits(_T_86, 31, 0) @[CircuitMath.scala 36:17] + node _T_93 = neq(_T_90, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_94 = bits(_T_90, 11, 8) @[CircuitMath.scala 35:17] + node _T_95 = bits(_T_90, 7, 0) @[CircuitMath.scala 36:17] + node _T_97 = neq(_T_94, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_98 = bits(_T_94, 3, 3) @[CircuitMath.scala 32:12] + node _T_100 = bits(_T_94, 2, 2) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_94, 1, 1) @[CircuitMath.scala 30:8] + node _T_103 = mux(_T_100, UInt<2>("h02"), _T_102) @[CircuitMath.scala 32:10] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[CircuitMath.scala 32:10] + node _T_105 = bits(_T_95, 7, 4) @[CircuitMath.scala 35:17] + node _T_106 = bits(_T_95, 3, 0) @[CircuitMath.scala 36:17] + node _T_108 = neq(_T_105, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_109 = bits(_T_105, 3, 3) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_105, 2, 2) @[CircuitMath.scala 32:12] + node _T_113 = bits(_T_105, 1, 1) @[CircuitMath.scala 30:8] + node _T_114 = mux(_T_111, UInt<2>("h02"), _T_113) @[CircuitMath.scala 32:10] + node _T_115 = mux(_T_109, UInt<2>("h03"), _T_114) @[CircuitMath.scala 32:10] + node _T_116 = bits(_T_106, 3, 3) @[CircuitMath.scala 32:12] + node _T_118 = bits(_T_106, 2, 2) @[CircuitMath.scala 32:12] + node _T_120 = bits(_T_106, 1, 1) @[CircuitMath.scala 30:8] + node _T_121 = mux(_T_118, UInt<2>("h02"), _T_120) @[CircuitMath.scala 32:10] + node _T_122 = mux(_T_116, UInt<2>("h03"), _T_121) @[CircuitMath.scala 32:10] + node _T_123 = mux(_T_108, _T_115, _T_122) @[CircuitMath.scala 38:21] + node _T_124 = cat(_T_108, _T_123) @[Cat.scala 30:58] + node _T_125 = mux(_T_97, _T_104, _T_124) @[CircuitMath.scala 38:21] + node _T_126 = cat(_T_97, _T_125) @[Cat.scala 30:58] + node _T_127 = bits(_T_91, 31, 16) @[CircuitMath.scala 35:17] + node _T_128 = bits(_T_91, 15, 0) @[CircuitMath.scala 36:17] + node _T_130 = neq(_T_127, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_131 = bits(_T_127, 15, 8) @[CircuitMath.scala 35:17] + node _T_132 = bits(_T_127, 7, 0) @[CircuitMath.scala 36:17] + node _T_134 = neq(_T_131, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_135 = bits(_T_131, 7, 4) @[CircuitMath.scala 35:17] + node _T_136 = bits(_T_131, 3, 0) @[CircuitMath.scala 36:17] + node _T_138 = neq(_T_135, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_139 = bits(_T_135, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_135, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_135, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = bits(_T_136, 3, 3) @[CircuitMath.scala 32:12] + node _T_148 = bits(_T_136, 2, 2) @[CircuitMath.scala 32:12] + node _T_150 = bits(_T_136, 1, 1) @[CircuitMath.scala 30:8] + node _T_151 = mux(_T_148, UInt<2>("h02"), _T_150) @[CircuitMath.scala 32:10] + node _T_152 = mux(_T_146, UInt<2>("h03"), _T_151) @[CircuitMath.scala 32:10] + node _T_153 = mux(_T_138, _T_145, _T_152) @[CircuitMath.scala 38:21] + node _T_154 = cat(_T_138, _T_153) @[Cat.scala 30:58] + node _T_155 = bits(_T_132, 7, 4) @[CircuitMath.scala 35:17] + node _T_156 = bits(_T_132, 3, 0) @[CircuitMath.scala 36:17] + node _T_158 = neq(_T_155, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_159 = bits(_T_155, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_155, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_155, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = bits(_T_156, 3, 3) @[CircuitMath.scala 32:12] + node _T_168 = bits(_T_156, 2, 2) @[CircuitMath.scala 32:12] + node _T_170 = bits(_T_156, 1, 1) @[CircuitMath.scala 30:8] + node _T_171 = mux(_T_168, UInt<2>("h02"), _T_170) @[CircuitMath.scala 32:10] + node _T_172 = mux(_T_166, UInt<2>("h03"), _T_171) @[CircuitMath.scala 32:10] + node _T_173 = mux(_T_158, _T_165, _T_172) @[CircuitMath.scala 38:21] + node _T_174 = cat(_T_158, _T_173) @[Cat.scala 30:58] + node _T_175 = mux(_T_134, _T_154, _T_174) @[CircuitMath.scala 38:21] + node _T_176 = cat(_T_134, _T_175) @[Cat.scala 30:58] + node _T_177 = bits(_T_128, 15, 8) @[CircuitMath.scala 35:17] + node _T_178 = bits(_T_128, 7, 0) @[CircuitMath.scala 36:17] + node _T_180 = neq(_T_177, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_181 = bits(_T_177, 7, 4) @[CircuitMath.scala 35:17] + node _T_182 = bits(_T_177, 3, 0) @[CircuitMath.scala 36:17] + node _T_184 = neq(_T_181, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_185 = bits(_T_181, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_181, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_181, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = bits(_T_182, 3, 3) @[CircuitMath.scala 32:12] + node _T_194 = bits(_T_182, 2, 2) @[CircuitMath.scala 32:12] + node _T_196 = bits(_T_182, 1, 1) @[CircuitMath.scala 30:8] + node _T_197 = mux(_T_194, UInt<2>("h02"), _T_196) @[CircuitMath.scala 32:10] + node _T_198 = mux(_T_192, UInt<2>("h03"), _T_197) @[CircuitMath.scala 32:10] + node _T_199 = mux(_T_184, _T_191, _T_198) @[CircuitMath.scala 38:21] + node _T_200 = cat(_T_184, _T_199) @[Cat.scala 30:58] + node _T_201 = bits(_T_178, 7, 4) @[CircuitMath.scala 35:17] + node _T_202 = bits(_T_178, 3, 0) @[CircuitMath.scala 36:17] + node _T_204 = neq(_T_201, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_205 = bits(_T_201, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_201, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_201, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = bits(_T_202, 3, 3) @[CircuitMath.scala 32:12] + node _T_214 = bits(_T_202, 2, 2) @[CircuitMath.scala 32:12] + node _T_216 = bits(_T_202, 1, 1) @[CircuitMath.scala 30:8] + node _T_217 = mux(_T_214, UInt<2>("h02"), _T_216) @[CircuitMath.scala 32:10] + node _T_218 = mux(_T_212, UInt<2>("h03"), _T_217) @[CircuitMath.scala 32:10] + node _T_219 = mux(_T_204, _T_211, _T_218) @[CircuitMath.scala 38:21] + node _T_220 = cat(_T_204, _T_219) @[Cat.scala 30:58] + node _T_221 = mux(_T_180, _T_200, _T_220) @[CircuitMath.scala 38:21] + node _T_222 = cat(_T_180, _T_221) @[Cat.scala 30:58] + node _T_223 = mux(_T_130, _T_176, _T_222) @[CircuitMath.scala 38:21] + node _T_224 = cat(_T_130, _T_223) @[Cat.scala 30:58] + node _T_225 = mux(_T_93, _T_126, _T_224) @[CircuitMath.scala 38:21] + node _T_226 = cat(_T_93, _T_225) @[Cat.scala 30:58] + node _T_227 = bits(_T_87, 63, 32) @[CircuitMath.scala 35:17] + node _T_228 = bits(_T_87, 31, 0) @[CircuitMath.scala 36:17] + node _T_230 = neq(_T_227, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_231 = bits(_T_227, 31, 16) @[CircuitMath.scala 35:17] + node _T_232 = bits(_T_227, 15, 0) @[CircuitMath.scala 36:17] + node _T_234 = neq(_T_231, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_235 = bits(_T_231, 15, 8) @[CircuitMath.scala 35:17] + node _T_236 = bits(_T_231, 7, 0) @[CircuitMath.scala 36:17] + node _T_238 = neq(_T_235, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_239 = bits(_T_235, 7, 4) @[CircuitMath.scala 35:17] + node _T_240 = bits(_T_235, 3, 0) @[CircuitMath.scala 36:17] + node _T_242 = neq(_T_239, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_243 = bits(_T_239, 3, 3) @[CircuitMath.scala 32:12] + node _T_245 = bits(_T_239, 2, 2) @[CircuitMath.scala 32:12] + node _T_247 = bits(_T_239, 1, 1) @[CircuitMath.scala 30:8] + node _T_248 = mux(_T_245, UInt<2>("h02"), _T_247) @[CircuitMath.scala 32:10] + node _T_249 = mux(_T_243, UInt<2>("h03"), _T_248) @[CircuitMath.scala 32:10] + node _T_250 = bits(_T_240, 3, 3) @[CircuitMath.scala 32:12] + node _T_252 = bits(_T_240, 2, 2) @[CircuitMath.scala 32:12] + node _T_254 = bits(_T_240, 1, 1) @[CircuitMath.scala 30:8] + node _T_255 = mux(_T_252, UInt<2>("h02"), _T_254) @[CircuitMath.scala 32:10] + node _T_256 = mux(_T_250, UInt<2>("h03"), _T_255) @[CircuitMath.scala 32:10] + node _T_257 = mux(_T_242, _T_249, _T_256) @[CircuitMath.scala 38:21] + node _T_258 = cat(_T_242, _T_257) @[Cat.scala 30:58] + node _T_259 = bits(_T_236, 7, 4) @[CircuitMath.scala 35:17] + node _T_260 = bits(_T_236, 3, 0) @[CircuitMath.scala 36:17] + node _T_262 = neq(_T_259, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_263 = bits(_T_259, 3, 3) @[CircuitMath.scala 32:12] + node _T_265 = bits(_T_259, 2, 2) @[CircuitMath.scala 32:12] + node _T_267 = bits(_T_259, 1, 1) @[CircuitMath.scala 30:8] + node _T_268 = mux(_T_265, UInt<2>("h02"), _T_267) @[CircuitMath.scala 32:10] + node _T_269 = mux(_T_263, UInt<2>("h03"), _T_268) @[CircuitMath.scala 32:10] + node _T_270 = bits(_T_260, 3, 3) @[CircuitMath.scala 32:12] + node _T_272 = bits(_T_260, 2, 2) @[CircuitMath.scala 32:12] + node _T_274 = bits(_T_260, 1, 1) @[CircuitMath.scala 30:8] + node _T_275 = mux(_T_272, UInt<2>("h02"), _T_274) @[CircuitMath.scala 32:10] + node _T_276 = mux(_T_270, UInt<2>("h03"), _T_275) @[CircuitMath.scala 32:10] + node _T_277 = mux(_T_262, _T_269, _T_276) @[CircuitMath.scala 38:21] + node _T_278 = cat(_T_262, _T_277) @[Cat.scala 30:58] + node _T_279 = mux(_T_238, _T_258, _T_278) @[CircuitMath.scala 38:21] + node _T_280 = cat(_T_238, _T_279) @[Cat.scala 30:58] + node _T_281 = bits(_T_232, 15, 8) @[CircuitMath.scala 35:17] + node _T_282 = bits(_T_232, 7, 0) @[CircuitMath.scala 36:17] + node _T_284 = neq(_T_281, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_285 = bits(_T_281, 7, 4) @[CircuitMath.scala 35:17] + node _T_286 = bits(_T_281, 3, 0) @[CircuitMath.scala 36:17] + node _T_288 = neq(_T_285, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_289 = bits(_T_285, 3, 3) @[CircuitMath.scala 32:12] + node _T_291 = bits(_T_285, 2, 2) @[CircuitMath.scala 32:12] + node _T_293 = bits(_T_285, 1, 1) @[CircuitMath.scala 30:8] + node _T_294 = mux(_T_291, UInt<2>("h02"), _T_293) @[CircuitMath.scala 32:10] + node _T_295 = mux(_T_289, UInt<2>("h03"), _T_294) @[CircuitMath.scala 32:10] + node _T_296 = bits(_T_286, 3, 3) @[CircuitMath.scala 32:12] + node _T_298 = bits(_T_286, 2, 2) @[CircuitMath.scala 32:12] + node _T_300 = bits(_T_286, 1, 1) @[CircuitMath.scala 30:8] + node _T_301 = mux(_T_298, UInt<2>("h02"), _T_300) @[CircuitMath.scala 32:10] + node _T_302 = mux(_T_296, UInt<2>("h03"), _T_301) @[CircuitMath.scala 32:10] + node _T_303 = mux(_T_288, _T_295, _T_302) @[CircuitMath.scala 38:21] + node _T_304 = cat(_T_288, _T_303) @[Cat.scala 30:58] + node _T_305 = bits(_T_282, 7, 4) @[CircuitMath.scala 35:17] + node _T_306 = bits(_T_282, 3, 0) @[CircuitMath.scala 36:17] + node _T_308 = neq(_T_305, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_309 = bits(_T_305, 3, 3) @[CircuitMath.scala 32:12] + node _T_311 = bits(_T_305, 2, 2) @[CircuitMath.scala 32:12] + node _T_313 = bits(_T_305, 1, 1) @[CircuitMath.scala 30:8] + node _T_314 = mux(_T_311, UInt<2>("h02"), _T_313) @[CircuitMath.scala 32:10] + node _T_315 = mux(_T_309, UInt<2>("h03"), _T_314) @[CircuitMath.scala 32:10] + node _T_316 = bits(_T_306, 3, 3) @[CircuitMath.scala 32:12] + node _T_318 = bits(_T_306, 2, 2) @[CircuitMath.scala 32:12] + node _T_320 = bits(_T_306, 1, 1) @[CircuitMath.scala 30:8] + node _T_321 = mux(_T_318, UInt<2>("h02"), _T_320) @[CircuitMath.scala 32:10] + node _T_322 = mux(_T_316, UInt<2>("h03"), _T_321) @[CircuitMath.scala 32:10] + node _T_323 = mux(_T_308, _T_315, _T_322) @[CircuitMath.scala 38:21] + node _T_324 = cat(_T_308, _T_323) @[Cat.scala 30:58] + node _T_325 = mux(_T_284, _T_304, _T_324) @[CircuitMath.scala 38:21] + node _T_326 = cat(_T_284, _T_325) @[Cat.scala 30:58] + node _T_327 = mux(_T_234, _T_280, _T_326) @[CircuitMath.scala 38:21] + node _T_328 = cat(_T_234, _T_327) @[Cat.scala 30:58] + node _T_329 = bits(_T_228, 31, 16) @[CircuitMath.scala 35:17] + node _T_330 = bits(_T_228, 15, 0) @[CircuitMath.scala 36:17] + node _T_332 = neq(_T_329, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_333 = bits(_T_329, 15, 8) @[CircuitMath.scala 35:17] + node _T_334 = bits(_T_329, 7, 0) @[CircuitMath.scala 36:17] + node _T_336 = neq(_T_333, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_337 = bits(_T_333, 7, 4) @[CircuitMath.scala 35:17] + node _T_338 = bits(_T_333, 3, 0) @[CircuitMath.scala 36:17] + node _T_340 = neq(_T_337, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_341 = bits(_T_337, 3, 3) @[CircuitMath.scala 32:12] + node _T_343 = bits(_T_337, 2, 2) @[CircuitMath.scala 32:12] + node _T_345 = bits(_T_337, 1, 1) @[CircuitMath.scala 30:8] + node _T_346 = mux(_T_343, UInt<2>("h02"), _T_345) @[CircuitMath.scala 32:10] + node _T_347 = mux(_T_341, UInt<2>("h03"), _T_346) @[CircuitMath.scala 32:10] + node _T_348 = bits(_T_338, 3, 3) @[CircuitMath.scala 32:12] + node _T_350 = bits(_T_338, 2, 2) @[CircuitMath.scala 32:12] + node _T_352 = bits(_T_338, 1, 1) @[CircuitMath.scala 30:8] + node _T_353 = mux(_T_350, UInt<2>("h02"), _T_352) @[CircuitMath.scala 32:10] + node _T_354 = mux(_T_348, UInt<2>("h03"), _T_353) @[CircuitMath.scala 32:10] + node _T_355 = mux(_T_340, _T_347, _T_354) @[CircuitMath.scala 38:21] + node _T_356 = cat(_T_340, _T_355) @[Cat.scala 30:58] + node _T_357 = bits(_T_334, 7, 4) @[CircuitMath.scala 35:17] + node _T_358 = bits(_T_334, 3, 0) @[CircuitMath.scala 36:17] + node _T_360 = neq(_T_357, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_361 = bits(_T_357, 3, 3) @[CircuitMath.scala 32:12] + node _T_363 = bits(_T_357, 2, 2) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_357, 1, 1) @[CircuitMath.scala 30:8] + node _T_366 = mux(_T_363, UInt<2>("h02"), _T_365) @[CircuitMath.scala 32:10] + node _T_367 = mux(_T_361, UInt<2>("h03"), _T_366) @[CircuitMath.scala 32:10] + node _T_368 = bits(_T_358, 3, 3) @[CircuitMath.scala 32:12] + node _T_370 = bits(_T_358, 2, 2) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_358, 1, 1) @[CircuitMath.scala 30:8] + node _T_373 = mux(_T_370, UInt<2>("h02"), _T_372) @[CircuitMath.scala 32:10] + node _T_374 = mux(_T_368, UInt<2>("h03"), _T_373) @[CircuitMath.scala 32:10] + node _T_375 = mux(_T_360, _T_367, _T_374) @[CircuitMath.scala 38:21] + node _T_376 = cat(_T_360, _T_375) @[Cat.scala 30:58] + node _T_377 = mux(_T_336, _T_356, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_336, _T_377) @[Cat.scala 30:58] + node _T_379 = bits(_T_330, 15, 8) @[CircuitMath.scala 35:17] + node _T_380 = bits(_T_330, 7, 0) @[CircuitMath.scala 36:17] + node _T_382 = neq(_T_379, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_383 = bits(_T_379, 7, 4) @[CircuitMath.scala 35:17] + node _T_384 = bits(_T_379, 3, 0) @[CircuitMath.scala 36:17] + node _T_386 = neq(_T_383, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_387 = bits(_T_383, 3, 3) @[CircuitMath.scala 32:12] + node _T_389 = bits(_T_383, 2, 2) @[CircuitMath.scala 32:12] + node _T_391 = bits(_T_383, 1, 1) @[CircuitMath.scala 30:8] + node _T_392 = mux(_T_389, UInt<2>("h02"), _T_391) @[CircuitMath.scala 32:10] + node _T_393 = mux(_T_387, UInt<2>("h03"), _T_392) @[CircuitMath.scala 32:10] + node _T_394 = bits(_T_384, 3, 3) @[CircuitMath.scala 32:12] + node _T_396 = bits(_T_384, 2, 2) @[CircuitMath.scala 32:12] + node _T_398 = bits(_T_384, 1, 1) @[CircuitMath.scala 30:8] + node _T_399 = mux(_T_396, UInt<2>("h02"), _T_398) @[CircuitMath.scala 32:10] + node _T_400 = mux(_T_394, UInt<2>("h03"), _T_399) @[CircuitMath.scala 32:10] + node _T_401 = mux(_T_386, _T_393, _T_400) @[CircuitMath.scala 38:21] + node _T_402 = cat(_T_386, _T_401) @[Cat.scala 30:58] + node _T_403 = bits(_T_380, 7, 4) @[CircuitMath.scala 35:17] + node _T_404 = bits(_T_380, 3, 0) @[CircuitMath.scala 36:17] + node _T_406 = neq(_T_403, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_407 = bits(_T_403, 3, 3) @[CircuitMath.scala 32:12] + node _T_409 = bits(_T_403, 2, 2) @[CircuitMath.scala 32:12] + node _T_411 = bits(_T_403, 1, 1) @[CircuitMath.scala 30:8] + node _T_412 = mux(_T_409, UInt<2>("h02"), _T_411) @[CircuitMath.scala 32:10] + node _T_413 = mux(_T_407, UInt<2>("h03"), _T_412) @[CircuitMath.scala 32:10] + node _T_414 = bits(_T_404, 3, 3) @[CircuitMath.scala 32:12] + node _T_416 = bits(_T_404, 2, 2) @[CircuitMath.scala 32:12] + node _T_418 = bits(_T_404, 1, 1) @[CircuitMath.scala 30:8] + node _T_419 = mux(_T_416, UInt<2>("h02"), _T_418) @[CircuitMath.scala 32:10] + node _T_420 = mux(_T_414, UInt<2>("h03"), _T_419) @[CircuitMath.scala 32:10] + node _T_421 = mux(_T_406, _T_413, _T_420) @[CircuitMath.scala 38:21] + node _T_422 = cat(_T_406, _T_421) @[Cat.scala 30:58] + node _T_423 = mux(_T_382, _T_402, _T_422) @[CircuitMath.scala 38:21] + node _T_424 = cat(_T_382, _T_423) @[Cat.scala 30:58] + node _T_425 = mux(_T_332, _T_378, _T_424) @[CircuitMath.scala 38:21] + node _T_426 = cat(_T_332, _T_425) @[Cat.scala 30:58] + node _T_427 = mux(_T_230, _T_328, _T_426) @[CircuitMath.scala 38:21] + node _T_428 = cat(_T_230, _T_427) @[Cat.scala 30:58] + node _T_429 = mux(_T_89, _T_226, _T_428) @[CircuitMath.scala 38:21] + node _T_430 = cat(_T_89, _T_429) @[Cat.scala 30:58] + node _T_431 = sub(UInt<8>("h0a0"), _T_430) @[primitives.scala 79:25] + node _T_432 = asUInt(_T_431) @[primitives.scala 79:25] + node estNormNeg_dist = tail(_T_432, 1) @[primitives.scala 79:25] + node _T_433 = bits(sigSum, 75, 44) @[MulAddRecFN.scala 252:19] + node _T_435 = neq(_T_433, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] + node _T_436 = bits(sigSum, 43, 0) @[MulAddRecFN.scala 255:19] + node _T_438 = neq(_T_436, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] + node firstReduceSigSum = cat(_T_435, _T_438) @[Cat.scala 30:58] + node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] + node _T_439 = bits(complSigSum, 75, 44) @[MulAddRecFN.scala 259:24] + node _T_441 = neq(_T_439, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] + node _T_442 = bits(complSigSum, 43, 0) @[MulAddRecFN.scala 262:24] + node _T_444 = neq(_T_442, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] + node firstReduceComplSigSum = cat(_T_441, _T_444) @[Cat.scala 30:58] + node _T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] + node _T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] + node _T_448 = asUInt(_T_447) @[MulAddRecFN.scala 268:39] + node _T_449 = tail(_T_448, 1) @[MulAddRecFN.scala 268:39] + node _T_450 = bits(_T_449, 5, 0) @[MulAddRecFN.scala 268:49] + node CDom_estNormDist = mux(_T_445, io.fromPreMul.CAlignDist, _T_450) @[MulAddRecFN.scala 266:12] + node _T_452 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] + node _T_453 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 271:46] + node _T_455 = eq(_T_453, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] + node _T_456 = and(_T_452, _T_455) @[MulAddRecFN.scala 271:25] + node _T_457 = bits(sigSum, 161, 76) @[MulAddRecFN.scala 272:23] + node _T_459 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] + node _T_460 = cat(_T_457, _T_459) @[Cat.scala 30:58] + node _T_462 = mux(_T_456, _T_460, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] + node _T_464 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] + node _T_465 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 277:44] + node _T_466 = and(_T_464, _T_465) @[MulAddRecFN.scala 277:25] + node _T_467 = bits(sigSum, 129, 44) @[MulAddRecFN.scala 278:23] + node _T_468 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] + node _T_469 = cat(_T_467, _T_468) @[Cat.scala 30:58] + node _T_471 = mux(_T_466, _T_469, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] + node _T_472 = or(_T_462, _T_471) @[MulAddRecFN.scala 276:11] + node _T_473 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 286:44] + node _T_475 = eq(_T_473, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] + node _T_476 = and(doSubMags, _T_475) @[MulAddRecFN.scala 286:23] + node _T_477 = bits(complSigSum, 161, 76) @[MulAddRecFN.scala 287:28] + node _T_479 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] + node _T_480 = cat(_T_477, _T_479) @[Cat.scala 30:58] + node _T_482 = mux(_T_476, _T_480, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] + node _T_483 = or(_T_472, _T_482) @[MulAddRecFN.scala 285:11] + node _T_484 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 292:42] + node _T_485 = and(doSubMags, _T_484) @[MulAddRecFN.scala 292:23] + node _T_486 = bits(complSigSum, 129, 44) @[MulAddRecFN.scala 293:28] + node _T_487 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] + node _T_488 = cat(_T_486, _T_487) @[Cat.scala 30:58] + node _T_490 = mux(_T_485, _T_488, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] + node CDom_firstNormAbsSigSum = or(_T_483, _T_490) @[MulAddRecFN.scala 291:11] + node _T_491 = bits(sigSum, 108, 44) @[MulAddRecFN.scala 308:23] + node _T_492 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] + node _T_494 = eq(_T_492, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] + node _T_495 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] + node _T_496 = mux(doSubMags, _T_494, _T_495) @[MulAddRecFN.scala 309:20] + node _T_497 = cat(_T_491, _T_496) @[Cat.scala 30:58] + node _T_498 = bits(sigSum, 97, 1) @[MulAddRecFN.scala 314:24] + node _T_499 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 316:37] + node _T_500 = bits(sigSum, 1, 1) @[MulAddRecFN.scala 318:32] + node _T_501 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_504 = mux(_T_501, UInt<86>("h03fffffffffffffffffffff"), UInt<86>("h00")) @[Bitwise.scala 71:12] + node _T_505 = cat(_T_500, _T_504) @[Cat.scala 30:58] + node _T_506 = mux(_T_499, _T_497, _T_505) @[MulAddRecFN.scala 316:21] + node _T_507 = bits(sigSum, 97, 12) @[MulAddRecFN.scala 324:28] + node _T_508 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 329:39] + node _T_510 = eq(_T_508, UInt<1>("h00")) @[MulAddRecFN.scala 329:77] + node _T_511 = bits(sigSum, 11, 1) @[MulAddRecFN.scala 331:34] + node _T_513 = neq(_T_511, UInt<1>("h00")) @[MulAddRecFN.scala 331:72] + node _T_514 = mux(doSubMags, _T_510, _T_513) @[MulAddRecFN.scala 328:26] + node _T_515 = cat(_T_507, _T_514) @[Cat.scala 30:58] + node _T_516 = bits(estNormNeg_dist, 6, 6) @[MulAddRecFN.scala 338:28] + node _T_517 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 339:33] + node _T_518 = bits(sigSum, 65, 1) @[MulAddRecFN.scala 340:28] + node _T_519 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_522 = mux(_T_519, UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 71:12] + node _T_523 = cat(_T_518, _T_522) @[Cat.scala 30:58] + node _T_524 = mux(_T_517, _T_523, _T_515) @[MulAddRecFN.scala 339:17] + node _T_525 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 345:33] + node _T_526 = bits(sigSum, 33, 1) @[MulAddRecFN.scala 347:28] + node _T_527 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_530 = mux(_T_527, UInt<54>("h03fffffffffffff"), UInt<54>("h00")) @[Bitwise.scala 71:12] + node _T_531 = cat(_T_526, _T_530) @[Cat.scala 30:58] + node _T_532 = mux(_T_525, _T_506, _T_531) @[MulAddRecFN.scala 345:17] + node notCDom_pos_firstNormAbsSigSum = mux(_T_516, _T_524, _T_532) @[MulAddRecFN.scala 338:12] + node _T_533 = bits(complSigSum, 107, 44) @[MulAddRecFN.scala 360:28] + node _T_534 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] + node _T_535 = cat(_T_533, _T_534) @[Cat.scala 30:58] + node _T_536 = bits(complSigSum, 97, 1) @[MulAddRecFN.scala 363:29] + node _T_537 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 365:37] + node _T_538 = bits(complSigSum, 2, 1) @[MulAddRecFN.scala 367:33] + node _T_539 = shl(_T_538, 86) @[MulAddRecFN.scala 367:68] + node _T_540 = mux(_T_537, _T_535, _T_539) @[MulAddRecFN.scala 365:21] + node _T_541 = bits(complSigSum, 98, 12) @[MulAddRecFN.scala 372:33] + node _T_542 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 376:33] + node _T_544 = neq(_T_542, UInt<1>("h00")) @[MulAddRecFN.scala 376:71] + node _T_545 = cat(_T_541, _T_544) @[Cat.scala 30:58] + node _T_546 = bits(estNormNeg_dist, 6, 6) @[MulAddRecFN.scala 379:28] + node _T_547 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 380:33] + node _T_548 = bits(complSigSum, 66, 1) @[MulAddRecFN.scala 381:29] + node _T_549 = shl(_T_548, 22) @[MulAddRecFN.scala 381:64] + node _T_550 = mux(_T_547, _T_549, _T_545) @[MulAddRecFN.scala 380:17] + node _T_551 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 385:33] + node _T_552 = bits(complSigSum, 34, 1) @[MulAddRecFN.scala 387:29] + node _T_553 = shl(_T_552, 54) @[MulAddRecFN.scala 387:64] + node _T_554 = mux(_T_551, _T_540, _T_553) @[MulAddRecFN.scala 385:17] + node notCDom_neg_cFirstNormAbsSigSum = mux(_T_546, _T_550, _T_554) @[MulAddRecFN.scala 379:12] + node notCDom_signSigSum = bits(sigSum, 109, 109) @[MulAddRecFN.scala 392:36] + node _T_556 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] + node _T_557 = and(doSubMags, _T_556) @[MulAddRecFN.scala 395:23] + node doNegSignSum = mux(io.fromPreMul.isCDominant, _T_557, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] + node _T_558 = mux(notCDom_signSigSum, estNormNeg_dist, estNormNeg_dist) @[MulAddRecFN.scala 401:16] + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, _T_558) @[MulAddRecFN.scala 399:12] + node _T_559 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] + node _T_560 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, _T_559, _T_560) @[MulAddRecFN.scala 407:12] + node _T_562 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] + node _T_564 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] + node _T_565 = and(_T_562, _T_564) @[MulAddRecFN.scala 418:37] + node doIncrSig = and(_T_565, doSubMags) @[MulAddRecFN.scala 418:61] + node estNormDist_5 = bits(estNormDist, 4, 0) @[MulAddRecFN.scala 419:36] + node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] + node _T_567 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) @[primitives.scala 68:52] + node _T_568 = bits(_T_567, 31, 1) @[primitives.scala 69:26] + node _T_569 = bits(_T_568, 15, 0) @[Bitwise.scala 108:18] + node _T_572 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_573 = xor(UInt<16>("h0ffff"), _T_572) @[Bitwise.scala 101:21] + node _T_574 = shr(_T_569, 8) @[Bitwise.scala 102:21] + node _T_575 = and(_T_574, _T_573) @[Bitwise.scala 102:31] + node _T_576 = bits(_T_569, 7, 0) @[Bitwise.scala 102:46] + node _T_577 = shl(_T_576, 8) @[Bitwise.scala 102:65] + node _T_578 = not(_T_573) @[Bitwise.scala 102:77] + node _T_579 = and(_T_577, _T_578) @[Bitwise.scala 102:75] + node _T_580 = or(_T_575, _T_579) @[Bitwise.scala 102:39] + node _T_581 = bits(_T_573, 11, 0) @[Bitwise.scala 101:28] + node _T_582 = shl(_T_581, 4) @[Bitwise.scala 101:47] + node _T_583 = xor(_T_573, _T_582) @[Bitwise.scala 101:21] + node _T_584 = shr(_T_580, 4) @[Bitwise.scala 102:21] + node _T_585 = and(_T_584, _T_583) @[Bitwise.scala 102:31] + node _T_586 = bits(_T_580, 11, 0) @[Bitwise.scala 102:46] + node _T_587 = shl(_T_586, 4) @[Bitwise.scala 102:65] + node _T_588 = not(_T_583) @[Bitwise.scala 102:77] + node _T_589 = and(_T_587, _T_588) @[Bitwise.scala 102:75] + node _T_590 = or(_T_585, _T_589) @[Bitwise.scala 102:39] + node _T_591 = bits(_T_583, 13, 0) @[Bitwise.scala 101:28] + node _T_592 = shl(_T_591, 2) @[Bitwise.scala 101:47] + node _T_593 = xor(_T_583, _T_592) @[Bitwise.scala 101:21] + node _T_594 = shr(_T_590, 2) @[Bitwise.scala 102:21] + node _T_595 = and(_T_594, _T_593) @[Bitwise.scala 102:31] + node _T_596 = bits(_T_590, 13, 0) @[Bitwise.scala 102:46] + node _T_597 = shl(_T_596, 2) @[Bitwise.scala 102:65] + node _T_598 = not(_T_593) @[Bitwise.scala 102:77] + node _T_599 = and(_T_597, _T_598) @[Bitwise.scala 102:75] + node _T_600 = or(_T_595, _T_599) @[Bitwise.scala 102:39] + node _T_601 = bits(_T_593, 14, 0) @[Bitwise.scala 101:28] + node _T_602 = shl(_T_601, 1) @[Bitwise.scala 101:47] + node _T_603 = xor(_T_593, _T_602) @[Bitwise.scala 101:21] + node _T_604 = shr(_T_600, 1) @[Bitwise.scala 102:21] + node _T_605 = and(_T_604, _T_603) @[Bitwise.scala 102:31] + node _T_606 = bits(_T_600, 14, 0) @[Bitwise.scala 102:46] + node _T_607 = shl(_T_606, 1) @[Bitwise.scala 102:65] + node _T_608 = not(_T_603) @[Bitwise.scala 102:77] + node _T_609 = and(_T_607, _T_608) @[Bitwise.scala 102:75] + node _T_610 = or(_T_605, _T_609) @[Bitwise.scala 102:39] + node _T_611 = bits(_T_568, 30, 16) @[Bitwise.scala 108:44] + node _T_612 = bits(_T_611, 7, 0) @[Bitwise.scala 108:18] + node _T_615 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_616 = xor(UInt<8>("h0ff"), _T_615) @[Bitwise.scala 101:21] + node _T_617 = shr(_T_612, 4) @[Bitwise.scala 102:21] + node _T_618 = and(_T_617, _T_616) @[Bitwise.scala 102:31] + node _T_619 = bits(_T_612, 3, 0) @[Bitwise.scala 102:46] + node _T_620 = shl(_T_619, 4) @[Bitwise.scala 102:65] + node _T_621 = not(_T_616) @[Bitwise.scala 102:77] + node _T_622 = and(_T_620, _T_621) @[Bitwise.scala 102:75] + node _T_623 = or(_T_618, _T_622) @[Bitwise.scala 102:39] + node _T_624 = bits(_T_616, 5, 0) @[Bitwise.scala 101:28] + node _T_625 = shl(_T_624, 2) @[Bitwise.scala 101:47] + node _T_626 = xor(_T_616, _T_625) @[Bitwise.scala 101:21] + node _T_627 = shr(_T_623, 2) @[Bitwise.scala 102:21] + node _T_628 = and(_T_627, _T_626) @[Bitwise.scala 102:31] + node _T_629 = bits(_T_623, 5, 0) @[Bitwise.scala 102:46] + node _T_630 = shl(_T_629, 2) @[Bitwise.scala 102:65] + node _T_631 = not(_T_626) @[Bitwise.scala 102:77] + node _T_632 = and(_T_630, _T_631) @[Bitwise.scala 102:75] + node _T_633 = or(_T_628, _T_632) @[Bitwise.scala 102:39] + node _T_634 = bits(_T_626, 6, 0) @[Bitwise.scala 101:28] + node _T_635 = shl(_T_634, 1) @[Bitwise.scala 101:47] + node _T_636 = xor(_T_626, _T_635) @[Bitwise.scala 101:21] + node _T_637 = shr(_T_633, 1) @[Bitwise.scala 102:21] + node _T_638 = and(_T_637, _T_636) @[Bitwise.scala 102:31] + node _T_639 = bits(_T_633, 6, 0) @[Bitwise.scala 102:46] + node _T_640 = shl(_T_639, 1) @[Bitwise.scala 102:65] + node _T_641 = not(_T_636) @[Bitwise.scala 102:77] + node _T_642 = and(_T_640, _T_641) @[Bitwise.scala 102:75] + node _T_643 = or(_T_638, _T_642) @[Bitwise.scala 102:39] + node _T_644 = bits(_T_611, 14, 8) @[Bitwise.scala 108:44] + node _T_645 = bits(_T_644, 3, 0) @[Bitwise.scala 108:18] + node _T_646 = bits(_T_645, 1, 0) @[Bitwise.scala 108:18] + node _T_647 = bits(_T_646, 0, 0) @[Bitwise.scala 108:18] + node _T_648 = bits(_T_646, 1, 1) @[Bitwise.scala 108:44] + node _T_649 = cat(_T_647, _T_648) @[Cat.scala 30:58] + node _T_650 = bits(_T_645, 3, 2) @[Bitwise.scala 108:44] + node _T_651 = bits(_T_650, 0, 0) @[Bitwise.scala 108:18] + node _T_652 = bits(_T_650, 1, 1) @[Bitwise.scala 108:44] + node _T_653 = cat(_T_651, _T_652) @[Cat.scala 30:58] + node _T_654 = cat(_T_649, _T_653) @[Cat.scala 30:58] + node _T_655 = bits(_T_644, 6, 4) @[Bitwise.scala 108:44] + node _T_656 = bits(_T_655, 1, 0) @[Bitwise.scala 108:18] + node _T_657 = bits(_T_656, 0, 0) @[Bitwise.scala 108:18] + node _T_658 = bits(_T_656, 1, 1) @[Bitwise.scala 108:44] + node _T_659 = cat(_T_657, _T_658) @[Cat.scala 30:58] + node _T_660 = bits(_T_655, 2, 2) @[Bitwise.scala 108:44] + node _T_661 = cat(_T_659, _T_660) @[Cat.scala 30:58] + node _T_662 = cat(_T_654, _T_661) @[Cat.scala 30:58] + node _T_663 = cat(_T_643, _T_662) @[Cat.scala 30:58] + node _T_664 = cat(_T_610, _T_663) @[Cat.scala 30:58] + node absSigSumExtraMask = cat(_T_664, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_666 = bits(cFirstNormAbsSigSum, 87, 1) @[MulAddRecFN.scala 424:32] + node _T_667 = dshr(_T_666, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] + node _T_668 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 427:39] + node _T_669 = not(_T_668) @[MulAddRecFN.scala 427:19] + node _T_670 = and(_T_669, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] + node _T_672 = eq(_T_670, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] + node _T_673 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 430:38] + node _T_674 = and(_T_673, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] + node _T_676 = neq(_T_674, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] + node _T_677 = mux(doIncrSig, _T_672, _T_676) @[MulAddRecFN.scala 426:16] + node _T_678 = cat(_T_667, _T_677) @[Cat.scala 30:58] + node sigX3 = bits(_T_678, 56, 0) @[MulAddRecFN.scala 434:10] + node _T_679 = bits(sigX3, 56, 55) @[MulAddRecFN.scala 436:29] + node sigX3Shift1 = eq(_T_679, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] + node _T_681 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] + node _T_682 = asUInt(_T_681) @[MulAddRecFN.scala 437:40] + node sExpX3 = tail(_T_682, 1) @[MulAddRecFN.scala 437:40] + node _T_683 = bits(sigX3, 56, 54) @[MulAddRecFN.scala 439:25] + node isZeroY = eq(_T_683, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] + node _T_685 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] + node signY = mux(isZeroY, signZeroNotEqOpSigns, _T_685) @[MulAddRecFN.scala 442:12] + node sExpX3_13 = bits(sExpX3, 12, 0) @[MulAddRecFN.scala 446:27] + node _T_686 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 448:34] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 71:15] + node _T_690 = mux(_T_687, UInt<56>("h0ffffffffffffff"), UInt<56>("h00")) @[Bitwise.scala 71:12] + node _T_691 = not(sExpX3_13) @[primitives.scala 50:21] + node _T_692 = bits(_T_691, 12, 12) @[primitives.scala 56:25] + node _T_693 = bits(_T_691, 11, 0) @[primitives.scala 57:26] + node _T_694 = bits(_T_693, 11, 11) @[primitives.scala 56:25] + node _T_695 = bits(_T_693, 10, 0) @[primitives.scala 57:26] + node _T_696 = bits(_T_695, 10, 10) @[primitives.scala 56:25] + node _T_697 = bits(_T_695, 9, 0) @[primitives.scala 57:26] + node _T_698 = bits(_T_697, 9, 9) @[primitives.scala 56:25] + node _T_699 = bits(_T_697, 8, 0) @[primitives.scala 57:26] + node _T_701 = bits(_T_699, 8, 8) @[primitives.scala 56:25] + node _T_702 = bits(_T_699, 7, 0) @[primitives.scala 57:26] + node _T_704 = bits(_T_702, 7, 7) @[primitives.scala 56:25] + node _T_705 = bits(_T_702, 6, 0) @[primitives.scala 57:26] + node _T_707 = bits(_T_705, 6, 6) @[primitives.scala 56:25] + node _T_708 = bits(_T_705, 5, 0) @[primitives.scala 57:26] + node _T_711 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_708) @[primitives.scala 68:52] + node _T_712 = bits(_T_711, 63, 14) @[primitives.scala 69:26] + node _T_713 = bits(_T_712, 31, 0) @[Bitwise.scala 108:18] + node _T_716 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_717 = xor(UInt<32>("h0ffffffff"), _T_716) @[Bitwise.scala 101:21] + node _T_718 = shr(_T_713, 16) @[Bitwise.scala 102:21] + node _T_719 = and(_T_718, _T_717) @[Bitwise.scala 102:31] + node _T_720 = bits(_T_713, 15, 0) @[Bitwise.scala 102:46] + node _T_721 = shl(_T_720, 16) @[Bitwise.scala 102:65] + node _T_722 = not(_T_717) @[Bitwise.scala 102:77] + node _T_723 = and(_T_721, _T_722) @[Bitwise.scala 102:75] + node _T_724 = or(_T_719, _T_723) @[Bitwise.scala 102:39] + node _T_725 = bits(_T_717, 23, 0) @[Bitwise.scala 101:28] + node _T_726 = shl(_T_725, 8) @[Bitwise.scala 101:47] + node _T_727 = xor(_T_717, _T_726) @[Bitwise.scala 101:21] + node _T_728 = shr(_T_724, 8) @[Bitwise.scala 102:21] + node _T_729 = and(_T_728, _T_727) @[Bitwise.scala 102:31] + node _T_730 = bits(_T_724, 23, 0) @[Bitwise.scala 102:46] + node _T_731 = shl(_T_730, 8) @[Bitwise.scala 102:65] + node _T_732 = not(_T_727) @[Bitwise.scala 102:77] + node _T_733 = and(_T_731, _T_732) @[Bitwise.scala 102:75] + node _T_734 = or(_T_729, _T_733) @[Bitwise.scala 102:39] + node _T_735 = bits(_T_727, 27, 0) @[Bitwise.scala 101:28] + node _T_736 = shl(_T_735, 4) @[Bitwise.scala 101:47] + node _T_737 = xor(_T_727, _T_736) @[Bitwise.scala 101:21] + node _T_738 = shr(_T_734, 4) @[Bitwise.scala 102:21] + node _T_739 = and(_T_738, _T_737) @[Bitwise.scala 102:31] + node _T_740 = bits(_T_734, 27, 0) @[Bitwise.scala 102:46] + node _T_741 = shl(_T_740, 4) @[Bitwise.scala 102:65] + node _T_742 = not(_T_737) @[Bitwise.scala 102:77] + node _T_743 = and(_T_741, _T_742) @[Bitwise.scala 102:75] + node _T_744 = or(_T_739, _T_743) @[Bitwise.scala 102:39] + node _T_745 = bits(_T_737, 29, 0) @[Bitwise.scala 101:28] + node _T_746 = shl(_T_745, 2) @[Bitwise.scala 101:47] + node _T_747 = xor(_T_737, _T_746) @[Bitwise.scala 101:21] + node _T_748 = shr(_T_744, 2) @[Bitwise.scala 102:21] + node _T_749 = and(_T_748, _T_747) @[Bitwise.scala 102:31] + node _T_750 = bits(_T_744, 29, 0) @[Bitwise.scala 102:46] + node _T_751 = shl(_T_750, 2) @[Bitwise.scala 102:65] + node _T_752 = not(_T_747) @[Bitwise.scala 102:77] + node _T_753 = and(_T_751, _T_752) @[Bitwise.scala 102:75] + node _T_754 = or(_T_749, _T_753) @[Bitwise.scala 102:39] + node _T_755 = bits(_T_747, 30, 0) @[Bitwise.scala 101:28] + node _T_756 = shl(_T_755, 1) @[Bitwise.scala 101:47] + node _T_757 = xor(_T_747, _T_756) @[Bitwise.scala 101:21] + node _T_758 = shr(_T_754, 1) @[Bitwise.scala 102:21] + node _T_759 = and(_T_758, _T_757) @[Bitwise.scala 102:31] + node _T_760 = bits(_T_754, 30, 0) @[Bitwise.scala 102:46] + node _T_761 = shl(_T_760, 1) @[Bitwise.scala 102:65] + node _T_762 = not(_T_757) @[Bitwise.scala 102:77] + node _T_763 = and(_T_761, _T_762) @[Bitwise.scala 102:75] + node _T_764 = or(_T_759, _T_763) @[Bitwise.scala 102:39] + node _T_765 = bits(_T_712, 49, 32) @[Bitwise.scala 108:44] + node _T_766 = bits(_T_765, 15, 0) @[Bitwise.scala 108:18] + node _T_769 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_770 = xor(UInt<16>("h0ffff"), _T_769) @[Bitwise.scala 101:21] + node _T_771 = shr(_T_766, 8) @[Bitwise.scala 102:21] + node _T_772 = and(_T_771, _T_770) @[Bitwise.scala 102:31] + node _T_773 = bits(_T_766, 7, 0) @[Bitwise.scala 102:46] + node _T_774 = shl(_T_773, 8) @[Bitwise.scala 102:65] + node _T_775 = not(_T_770) @[Bitwise.scala 102:77] + node _T_776 = and(_T_774, _T_775) @[Bitwise.scala 102:75] + node _T_777 = or(_T_772, _T_776) @[Bitwise.scala 102:39] + node _T_778 = bits(_T_770, 11, 0) @[Bitwise.scala 101:28] + node _T_779 = shl(_T_778, 4) @[Bitwise.scala 101:47] + node _T_780 = xor(_T_770, _T_779) @[Bitwise.scala 101:21] + node _T_781 = shr(_T_777, 4) @[Bitwise.scala 102:21] + node _T_782 = and(_T_781, _T_780) @[Bitwise.scala 102:31] + node _T_783 = bits(_T_777, 11, 0) @[Bitwise.scala 102:46] + node _T_784 = shl(_T_783, 4) @[Bitwise.scala 102:65] + node _T_785 = not(_T_780) @[Bitwise.scala 102:77] + node _T_786 = and(_T_784, _T_785) @[Bitwise.scala 102:75] + node _T_787 = or(_T_782, _T_786) @[Bitwise.scala 102:39] + node _T_788 = bits(_T_780, 13, 0) @[Bitwise.scala 101:28] + node _T_789 = shl(_T_788, 2) @[Bitwise.scala 101:47] + node _T_790 = xor(_T_780, _T_789) @[Bitwise.scala 101:21] + node _T_791 = shr(_T_787, 2) @[Bitwise.scala 102:21] + node _T_792 = and(_T_791, _T_790) @[Bitwise.scala 102:31] + node _T_793 = bits(_T_787, 13, 0) @[Bitwise.scala 102:46] + node _T_794 = shl(_T_793, 2) @[Bitwise.scala 102:65] + node _T_795 = not(_T_790) @[Bitwise.scala 102:77] + node _T_796 = and(_T_794, _T_795) @[Bitwise.scala 102:75] + node _T_797 = or(_T_792, _T_796) @[Bitwise.scala 102:39] + node _T_798 = bits(_T_790, 14, 0) @[Bitwise.scala 101:28] + node _T_799 = shl(_T_798, 1) @[Bitwise.scala 101:47] + node _T_800 = xor(_T_790, _T_799) @[Bitwise.scala 101:21] + node _T_801 = shr(_T_797, 1) @[Bitwise.scala 102:21] + node _T_802 = and(_T_801, _T_800) @[Bitwise.scala 102:31] + node _T_803 = bits(_T_797, 14, 0) @[Bitwise.scala 102:46] + node _T_804 = shl(_T_803, 1) @[Bitwise.scala 102:65] + node _T_805 = not(_T_800) @[Bitwise.scala 102:77] + node _T_806 = and(_T_804, _T_805) @[Bitwise.scala 102:75] + node _T_807 = or(_T_802, _T_806) @[Bitwise.scala 102:39] + node _T_808 = bits(_T_765, 17, 16) @[Bitwise.scala 108:44] + node _T_809 = bits(_T_808, 0, 0) @[Bitwise.scala 108:18] + node _T_810 = bits(_T_808, 1, 1) @[Bitwise.scala 108:44] + node _T_811 = cat(_T_809, _T_810) @[Cat.scala 30:58] + node _T_812 = cat(_T_807, _T_811) @[Cat.scala 30:58] + node _T_813 = cat(_T_764, _T_812) @[Cat.scala 30:58] + node _T_814 = not(_T_813) @[primitives.scala 65:36] + node _T_815 = mux(_T_707, UInt<1>("h00"), _T_814) @[primitives.scala 65:21] + node _T_816 = not(_T_815) @[primitives.scala 65:17] + node _T_817 = not(_T_816) @[primitives.scala 65:36] + node _T_818 = mux(_T_704, UInt<1>("h00"), _T_817) @[primitives.scala 65:21] + node _T_819 = not(_T_818) @[primitives.scala 65:17] + node _T_820 = not(_T_819) @[primitives.scala 65:36] + node _T_821 = mux(_T_701, UInt<1>("h00"), _T_820) @[primitives.scala 65:21] + node _T_822 = not(_T_821) @[primitives.scala 65:17] + node _T_823 = not(_T_822) @[primitives.scala 65:36] + node _T_824 = mux(_T_698, UInt<1>("h00"), _T_823) @[primitives.scala 65:21] + node _T_825 = not(_T_824) @[primitives.scala 65:17] + node _T_827 = cat(_T_825, UInt<4>("h0f")) @[Cat.scala 30:58] + node _T_828 = bits(_T_697, 9, 9) @[primitives.scala 56:25] + node _T_829 = bits(_T_697, 8, 0) @[primitives.scala 57:26] + node _T_830 = bits(_T_829, 8, 8) @[primitives.scala 56:25] + node _T_831 = bits(_T_829, 7, 0) @[primitives.scala 57:26] + node _T_832 = bits(_T_831, 7, 7) @[primitives.scala 56:25] + node _T_833 = bits(_T_831, 6, 0) @[primitives.scala 57:26] + node _T_834 = bits(_T_833, 6, 6) @[primitives.scala 56:25] + node _T_835 = bits(_T_833, 5, 0) @[primitives.scala 57:26] + node _T_837 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_835) @[primitives.scala 68:52] + node _T_838 = bits(_T_837, 3, 0) @[primitives.scala 69:26] + node _T_839 = bits(_T_838, 1, 0) @[Bitwise.scala 108:18] + node _T_840 = bits(_T_839, 0, 0) @[Bitwise.scala 108:18] + node _T_841 = bits(_T_839, 1, 1) @[Bitwise.scala 108:44] + node _T_842 = cat(_T_840, _T_841) @[Cat.scala 30:58] + node _T_843 = bits(_T_838, 3, 2) @[Bitwise.scala 108:44] + node _T_844 = bits(_T_843, 0, 0) @[Bitwise.scala 108:18] + node _T_845 = bits(_T_843, 1, 1) @[Bitwise.scala 108:44] + node _T_846 = cat(_T_844, _T_845) @[Cat.scala 30:58] + node _T_847 = cat(_T_842, _T_846) @[Cat.scala 30:58] + node _T_849 = mux(_T_834, _T_847, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_851 = mux(_T_832, _T_849, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_853 = mux(_T_830, _T_851, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_855 = mux(_T_828, _T_853, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_856 = mux(_T_696, _T_827, _T_855) @[primitives.scala 61:20] + node _T_858 = mux(_T_694, _T_856, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_860 = mux(_T_692, _T_858, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_861 = bits(sigX3, 55, 55) @[MulAddRecFN.scala 450:26] + node _T_862 = or(_T_860, _T_861) @[MulAddRecFN.scala 449:75] + node _T_864 = cat(_T_862, UInt<2>("h03")) @[Cat.scala 30:58] + node roundMask = or(_T_690, _T_864) @[MulAddRecFN.scala 448:50] + node _T_865 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] + node _T_866 = not(_T_865) @[MulAddRecFN.scala 454:24] + node roundPosMask = and(_T_866, roundMask) @[MulAddRecFN.scala 454:40] + node _T_867 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] + node roundPosBit = neq(_T_867, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] + node _T_869 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] + node _T_870 = and(sigX3, _T_869) @[MulAddRecFN.scala 456:34] + node anyRoundExtra = neq(_T_870, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] + node _T_872 = not(sigX3) @[MulAddRecFN.scala 457:27] + node _T_873 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] + node _T_874 = and(_T_872, _T_873) @[MulAddRecFN.scala 457:34] + node allRoundExtra = eq(_T_874, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] + node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] + node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] + node _T_877 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] + node _T_878 = and(_T_877, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] + node _T_879 = and(_T_878, roundPosBit) @[MulAddRecFN.scala 462:51] + node _T_880 = and(_T_879, anyRoundExtra) @[MulAddRecFN.scala 463:60] + node _T_882 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] + node _T_883 = and(_T_882, roundDirectUp) @[MulAddRecFN.scala 464:22] + node _T_884 = and(_T_883, anyRound) @[MulAddRecFN.scala 464:49] + node _T_885 = or(_T_880, _T_884) @[MulAddRecFN.scala 463:78] + node _T_886 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] + node _T_887 = or(_T_885, _T_886) @[MulAddRecFN.scala 464:65] + node _T_888 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] + node _T_889 = and(_T_888, roundPosBit) @[MulAddRecFN.scala 466:49] + node _T_890 = or(_T_887, _T_889) @[MulAddRecFN.scala 465:65] + node _T_891 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] + node _T_893 = and(_T_891, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] + node roundUp = or(_T_890, _T_893) @[MulAddRecFN.scala 466:65] + node _T_895 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] + node _T_896 = and(roundingMode_nearest_even, _T_895) @[MulAddRecFN.scala 470:39] + node _T_897 = and(_T_896, allRoundExtra) @[MulAddRecFN.scala 470:56] + node _T_898 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] + node _T_900 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] + node _T_901 = and(_T_898, _T_900) @[MulAddRecFN.scala 471:56] + node roundEven = mux(doIncrSig, _T_897, _T_901) @[MulAddRecFN.scala 469:12] + node _T_903 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] + node inexactY = mux(doIncrSig, _T_903, anyRound) @[MulAddRecFN.scala 473:27] + node _T_904 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] + node _T_905 = shr(_T_904, 2) @[MulAddRecFN.scala 475:30] + node _T_907 = add(_T_905, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] + node _T_908 = tail(_T_907, 1) @[MulAddRecFN.scala 475:35] + node roundUp_sigY3 = bits(_T_908, 54, 0) @[MulAddRecFN.scala 475:45] + node _T_910 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] + node _T_912 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] + node _T_913 = and(_T_910, _T_912) @[MulAddRecFN.scala 477:23] + node _T_914 = not(roundMask) @[MulAddRecFN.scala 477:48] + node _T_915 = and(sigX3, _T_914) @[MulAddRecFN.scala 477:46] + node _T_916 = shr(_T_915, 2) @[MulAddRecFN.scala 477:59] + node _T_918 = mux(_T_913, _T_916, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] + node _T_920 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] + node _T_921 = or(_T_918, _T_920) @[MulAddRecFN.scala 477:79] + node _T_922 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] + node _T_923 = not(_T_922) @[MulAddRecFN.scala 479:53] + node _T_924 = and(roundUp_sigY3, _T_923) @[MulAddRecFN.scala 479:51] + node _T_926 = mux(roundEven, _T_924, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] + node sigY3 = or(_T_921, _T_926) @[MulAddRecFN.scala 478:79] + node _T_927 = bits(sigY3, 54, 54) @[MulAddRecFN.scala 482:18] + node _T_929 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] + node _T_930 = tail(_T_929, 1) @[MulAddRecFN.scala 482:41] + node _T_932 = mux(_T_927, _T_930, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] + node _T_933 = bits(sigY3, 53, 53) @[MulAddRecFN.scala 483:18] + node _T_935 = mux(_T_933, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] + node _T_936 = or(_T_932, _T_935) @[MulAddRecFN.scala 482:61] + node _T_937 = bits(sigY3, 54, 53) @[MulAddRecFN.scala 484:19] + node _T_939 = eq(_T_937, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] + node _T_941 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] + node _T_942 = asUInt(_T_941) @[MulAddRecFN.scala 485:20] + node _T_943 = tail(_T_942, 1) @[MulAddRecFN.scala 485:20] + node _T_945 = mux(_T_939, _T_943, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] + node sExpY = or(_T_936, _T_945) @[MulAddRecFN.scala 483:61] + node expY = bits(sExpY, 11, 0) @[MulAddRecFN.scala 488:21] + node _T_946 = bits(sigY3, 51, 0) @[MulAddRecFN.scala 490:31] + node _T_947 = bits(sigY3, 52, 1) @[MulAddRecFN.scala 490:55] + node fractY = mux(sigX3Shift1, _T_946, _T_947) @[MulAddRecFN.scala 490:12] + node _T_948 = bits(sExpY, 12, 10) @[MulAddRecFN.scala 492:27] + node overflowY = eq(_T_948, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] + node _T_951 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] + node _T_952 = bits(sExpY, 12, 12) @[MulAddRecFN.scala 496:19] + node _T_953 = bits(sExpY, 11, 0) @[MulAddRecFN.scala 496:43] + node _T_955 = lt(_T_953, UInt<10>("h03ce")) @[MulAddRecFN.scala 496:57] + node _T_956 = or(_T_952, _T_955) @[MulAddRecFN.scala 496:34] + node totalUnderflowY = and(_T_951, _T_956) @[MulAddRecFN.scala 495:19] + node _T_957 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 499:20] + node _T_960 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) @[MulAddRecFN.scala 501:26] + node _T_961 = leq(sExpX3_13, _T_960) @[MulAddRecFN.scala 500:29] + node _T_962 = or(_T_957, _T_961) @[MulAddRecFN.scala 499:35] + node underflowY = and(inexactY, _T_962) @[MulAddRecFN.scala 498:22] + node _T_963 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] + node _T_965 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] + node _T_966 = and(roundingMode_max, _T_965) @[MulAddRecFN.scala 506:58] + node roundMagUp = or(_T_963, _T_966) @[MulAddRecFN.scala 506:37] + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] + node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] + node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] + node _T_968 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] + node _T_970 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] + node commonCase = and(_T_968, _T_970) @[MulAddRecFN.scala 514:35] + node _T_971 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] + node _T_972 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] + node _T_973 = or(_T_971, _T_972) @[MulAddRecFN.scala 517:29] + node _T_975 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] + node _T_977 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] + node _T_978 = and(_T_975, _T_977) @[MulAddRecFN.scala 518:23] + node _T_979 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] + node _T_980 = and(_T_978, _T_979) @[MulAddRecFN.scala 518:35] + node _T_981 = and(_T_980, isInfC) @[MulAddRecFN.scala 518:57] + node _T_982 = and(_T_981, doSubMags) @[MulAddRecFN.scala 518:67] + node notSigNaN_invalid = or(_T_973, _T_982) @[MulAddRecFN.scala 517:52] + node _T_983 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] + node _T_984 = or(_T_983, isSigNaNC) @[MulAddRecFN.scala 519:42] + node invalid = or(_T_984, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] + node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] + node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] + node _T_985 = and(commonCase, inexactY) @[MulAddRecFN.scala 522:43] + node inexact = or(overflow, _T_985) @[MulAddRecFN.scala 522:28] + node _T_986 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] + node notSpecial_isZeroOut = or(_T_986, totalUnderflowY) @[MulAddRecFN.scala 525:40] + node _T_987 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] + node pegMinFiniteMagOut = and(_T_987, roundMagUp) @[MulAddRecFN.scala 526:60] + node _T_989 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] + node pegMaxFiniteMagOut = and(overflow, _T_989) @[MulAddRecFN.scala 527:39] + node _T_990 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] + node _T_991 = or(_T_990, isInfC) @[MulAddRecFN.scala 529:26] + node _T_992 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] + node notNaN_isInfOut = or(_T_991, _T_992) @[MulAddRecFN.scala 529:36] + node _T_993 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] + node _T_994 = or(_T_993, isNaNC) @[MulAddRecFN.scala 530:37] + node isNaNOut = or(_T_994, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] + node _T_996 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] + node _T_997 = and(_T_996, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] + node _T_999 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] + node _T_1000 = and(mulSpecial, _T_999) @[MulAddRecFN.scala 534:21] + node _T_1001 = and(_T_1000, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] + node _T_1002 = or(_T_997, _T_1001) @[MulAddRecFN.scala 533:78] + node _T_1004 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] + node _T_1005 = and(_T_1004, isSpecialC) @[MulAddRecFN.scala 535:23] + node _T_1006 = and(_T_1005, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] + node _T_1007 = or(_T_1002, _T_1006) @[MulAddRecFN.scala 534:78] + node _T_1009 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] + node _T_1010 = and(_T_1009, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] + node _T_1011 = and(_T_1010, doSubMags) @[MulAddRecFN.scala 536:46] + node _T_1012 = and(_T_1011, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] + node uncommonCaseSignOut = or(_T_1007, _T_1012) @[MulAddRecFN.scala 535:78] + node _T_1014 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] + node _T_1015 = and(_T_1014, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] + node _T_1016 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] + node signOut = or(_T_1015, _T_1016) @[MulAddRecFN.scala 538:55] + node _T_1019 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 541:18] + node _T_1020 = not(_T_1019) @[MulAddRecFN.scala 541:14] + node _T_1021 = and(expY, _T_1020) @[MulAddRecFN.scala 540:15] + node _T_1023 = not(UInt<12>("h03ce")) @[MulAddRecFN.scala 546:19] + node _T_1025 = mux(pegMinFiniteMagOut, _T_1023, UInt<12>("h00")) @[MulAddRecFN.scala 545:18] + node _T_1026 = not(_T_1025) @[MulAddRecFN.scala 545:14] + node _T_1027 = and(_T_1021, _T_1026) @[MulAddRecFN.scala 544:17] + node _T_1030 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) @[MulAddRecFN.scala 549:18] + node _T_1031 = not(_T_1030) @[MulAddRecFN.scala 549:14] + node _T_1032 = and(_T_1027, _T_1031) @[MulAddRecFN.scala 548:17] + node _T_1035 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) @[MulAddRecFN.scala 553:18] + node _T_1036 = not(_T_1035) @[MulAddRecFN.scala 553:14] + node _T_1037 = and(_T_1032, _T_1036) @[MulAddRecFN.scala 552:17] + node _T_1040 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) @[MulAddRecFN.scala 557:16] + node _T_1041 = or(_T_1037, _T_1040) @[MulAddRecFN.scala 556:18] + node _T_1044 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) @[MulAddRecFN.scala 558:16] + node _T_1045 = or(_T_1041, _T_1044) @[MulAddRecFN.scala 557:74] + node _T_1048 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) @[MulAddRecFN.scala 562:16] + node _T_1049 = or(_T_1045, _T_1048) @[MulAddRecFN.scala 561:15] + node _T_1052 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 566:16] + node expOut = or(_T_1049, _T_1052) @[MulAddRecFN.scala 565:15] + node _T_1053 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] + node _T_1054 = or(_T_1053, isNaNOut) @[MulAddRecFN.scala 568:45] + node _T_1056 = shl(UInt<1>("h01"), 51) @[MulAddRecFN.scala 569:34] + node _T_1058 = mux(isNaNOut, _T_1056, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] + node _T_1059 = mux(_T_1054, _T_1058, fractY) @[MulAddRecFN.scala 568:12] + node _T_1060 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_1063 = mux(_T_1060, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_1059, _T_1063) @[MulAddRecFN.scala 571:11] + node _T_1064 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1064, fractOut) @[Cat.scala 30:58] + io.out <= _T_1065 @[MulAddRecFN.scala 574:12] + node _T_1067 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_1068 = cat(invalid, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1069 = cat(_T_1068, overflow) @[Cat.scala 30:58] + node _T_1070 = cat(_T_1069, _T_1067) @[Cat.scala 30:58] + io.exceptionFlags <= _T_1070 @[MulAddRecFN.scala 575:23] + + module MulAddRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst mulAddRecFN_preMul of MulAddRecFN_preMul_1 @[MulAddRecFN.scala 598:15] + mulAddRecFN_preMul.io is invalid + mulAddRecFN_preMul.clock <= clock + mulAddRecFN_preMul.reset <= reset + inst mulAddRecFN_postMul of MulAddRecFN_postMul_1 @[MulAddRecFN.scala 600:15] + mulAddRecFN_postMul.io is invalid + mulAddRecFN_postMul.clock <= clock + mulAddRecFN_postMul.reset <= reset + mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] + mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] + mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] + mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] + node _T_16 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] + node _T_18 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 30:58] + node _T_19 = add(_T_16, _T_18) @[MulAddRecFN.scala 610:71] + node _T_20 = tail(_T_19, 1) @[MulAddRecFN.scala 610:71] + mulAddRecFN_postMul.io.mulAddResult <= _T_20 @[MulAddRecFN.scala 609:41] + io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] + + module FPUFMAPipe_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + node one = shl(UInt<1>("h01"), 63) @[FPU.scala 479:21] + node _T_131 = bits(io.in.bits.in1, 64, 64) @[FPU.scala 480:29] + node _T_132 = bits(io.in.bits.in2, 64, 64) @[FPU.scala 480:53] + node _T_133 = xor(_T_131, _T_132) @[FPU.scala 480:37] + node zero = shl(_T_133, 64) @[FPU.scala 480:62] + reg valid : UInt<1>, clock @[FPU.scala 482:18] + valid <= io.in.valid @[FPU.scala 482:18] + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 483:15] + when io.in.valid : @[FPU.scala 484:22] + in <- io.in.bits @[FPU.scala 485:8] + node _T_177 = bits(io.in.bits.cmd, 1, 1) @[FPU.scala 488:33] + node _T_178 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 488:48] + node _T_179 = and(_T_177, _T_178) @[FPU.scala 488:37] + node _T_180 = bits(io.in.bits.cmd, 0, 0) @[FPU.scala 488:78] + node _T_181 = cat(_T_179, _T_180) @[Cat.scala 30:58] + in.cmd <= _T_181 @[FPU.scala 488:12] + when io.in.bits.swap23 : @[FPU.scala 489:23] + in.in2 <= one @[FPU.scala 489:32] + skip @[FPU.scala 489:23] + node _T_182 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 490:21] + node _T_184 = eq(_T_182, UInt<1>("h00")) @[Conditional.scala 19:11] + when _T_184 : @[Conditional.scala 19:15] + in.in3 <= zero @[FPU.scala 490:45] + skip @[Conditional.scala 19:15] + skip @[FPU.scala 484:22] + inst fma of MulAddRecFN_1 @[FPU.scala 493:19] + fma.io is invalid + fma.clock <= clock + fma.reset <= reset + fma.io.op <= in.cmd @[FPU.scala 494:13] + fma.io.roundingMode <= in.rm @[FPU.scala 495:23] + fma.io.a <= in.in1 @[FPU.scala 496:12] + fma.io.b <= in.in2 @[FPU.scala 497:12] + fma.io.c <= in.in3 @[FPU.scala 498:12] + wire res : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 500:17] + res is invalid @[FPU.scala 500:17] + res.data <= fma.io.out @[FPU.scala 501:12] + res.exc <= fma.io.exceptionFlags @[FPU.scala 502:11] + reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_192 <= valid @[Valid.scala 47:18] + reg _T_196 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_196 <- res @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_201 <= _T_192 @[Valid.scala 47:18] + reg _T_205 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_192 : @[Reg.scala 35:19] + _T_205 <- _T_196 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_210 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_210 <= _T_201 @[Valid.scala 47:18] + reg _T_214 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_201 : @[Reg.scala 35:19] + _T_214 <- _T_205 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_226 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_226 is invalid @[Valid.scala 42:21] + _T_226.valid <= _T_210 @[Valid.scala 43:17] + _T_226.bits <- _T_214 @[Valid.scala 44:16] + io.out <- _T_226 @[FPU.scala 503:10] + + module DivSqrtRecF64_mulAddZ31 : + input clock : Clock + input reset : UInt<1> + output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} + + io is invalid + io is invalid + reg valid_PA : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 78:30] + reg sqrtOp_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 79:30] + reg sign_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 80:30] + reg specialCodeB_PA : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 82:30] + reg fractB_51_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 83:30] + reg roundingMode_PA : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 84:30] + reg specialCodeA_PA : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 85:30] + reg fractA_51_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 86:30] + reg exp_PA : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 87:30] + reg fractB_other_PA : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 88:30] + reg fractA_other_PA : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 89:30] + reg valid_PB : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 91:30] + reg sqrtOp_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 92:30] + reg sign_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 93:30] + reg specialCodeA_PB : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 95:30] + reg fractA_51_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 96:30] + reg specialCodeB_PB : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 97:30] + reg fractB_51_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 98:30] + reg roundingMode_PB : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 99:30] + reg exp_PB : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 100:30] + reg fractA_0_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 101:30] + reg fractB_other_PB : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 102:30] + reg valid_PC : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 104:30] + reg sqrtOp_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 105:30] + reg sign_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 106:30] + reg specialCodeA_PC : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 108:30] + reg fractA_51_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 109:30] + reg specialCodeB_PC : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 110:30] + reg fractB_51_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 111:30] + reg roundingMode_PC : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 112:30] + reg exp_PC : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 113:30] + reg fractA_0_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 114:30] + reg fractB_other_PC : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 115:30] + reg cycleNum_A : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 117:30] + reg cycleNum_B : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 118:30] + reg cycleNum_C : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 119:30] + reg cycleNum_E : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 120:30] + reg fractR0_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 122:30] + reg hiSqrR0_A_sqrt : UInt<10>, clock @[DivSqrtRecF64_mulAddZ31.scala 124:30] + reg partNegSigma0_A : UInt<21>, clock @[DivSqrtRecF64_mulAddZ31.scala 125:30] + reg nextMulAdd9A_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 126:30] + reg nextMulAdd9B_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 127:30] + reg ER1_B_sqrt : UInt<17>, clock @[DivSqrtRecF64_mulAddZ31.scala 128:30] + reg ESqrR1_B_sqrt : UInt<32>, clock @[DivSqrtRecF64_mulAddZ31.scala 130:30] + reg sigX1_B : UInt<58>, clock @[DivSqrtRecF64_mulAddZ31.scala 131:30] + reg sqrSigma1_C : UInt<33>, clock @[DivSqrtRecF64_mulAddZ31.scala 132:30] + reg sigXN_C : UInt<58>, clock @[DivSqrtRecF64_mulAddZ31.scala 133:30] + reg u_C_sqrt : UInt<31>, clock @[DivSqrtRecF64_mulAddZ31.scala 134:30] + reg E_E_div : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 135:30] + reg sigT_E : UInt<53>, clock @[DivSqrtRecF64_mulAddZ31.scala 136:30] + reg extraT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 137:30] + reg isNegRemT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 138:30] + reg isZeroRemT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 139:30] + wire ready_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 143:24] + ready_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 143:24] + wire ready_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 144:24] + ready_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 144:24] + wire ready_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 145:24] + ready_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 145:24] + wire leaving_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 146:26] + leaving_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 146:26] + wire leaving_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 147:26] + leaving_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 147:26] + wire leaving_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 148:26] + leaving_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 148:26] + wire cyc_B10_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 150:28] + cyc_B10_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 150:28] + wire cyc_B9_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 151:28] + cyc_B9_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 151:28] + wire cyc_B8_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 152:28] + cyc_B8_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 152:28] + wire cyc_B7_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 153:28] + cyc_B7_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 153:28] + wire cyc_B6 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 155:22] + cyc_B6 is invalid @[DivSqrtRecF64_mulAddZ31.scala 155:22] + wire cyc_B5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 156:22] + cyc_B5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 156:22] + wire cyc_B4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 157:22] + cyc_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 157:22] + wire cyc_B3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 158:22] + cyc_B3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 158:22] + wire cyc_B2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 159:22] + cyc_B2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 159:22] + wire cyc_B1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 160:22] + cyc_B1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 160:22] + wire cyc_B6_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 162:26] + cyc_B6_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 162:26] + wire cyc_B5_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 163:26] + cyc_B5_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 163:26] + wire cyc_B4_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 164:26] + cyc_B4_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 164:26] + wire cyc_B3_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 165:26] + cyc_B3_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 165:26] + wire cyc_B2_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 166:26] + cyc_B2_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 166:26] + wire cyc_B1_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 167:26] + cyc_B1_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 167:26] + wire cyc_B6_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 169:27] + cyc_B6_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 169:27] + wire cyc_B5_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 170:27] + cyc_B5_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 170:27] + wire cyc_B4_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 171:27] + cyc_B4_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 171:27] + wire cyc_B3_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 172:27] + cyc_B3_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 172:27] + wire cyc_B2_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 173:27] + cyc_B2_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 173:27] + wire cyc_B1_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 174:27] + cyc_B1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 174:27] + wire cyc_C5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 176:22] + cyc_C5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 176:22] + wire cyc_C4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 177:22] + cyc_C4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 177:22] + wire cyc_C3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 178:22] + cyc_C3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 178:22] + wire cyc_C2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 179:22] + cyc_C2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 179:22] + wire cyc_C1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 180:22] + cyc_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 180:22] + wire cyc_E4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 182:22] + cyc_E4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 182:22] + wire cyc_E3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 183:22] + cyc_E3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 183:22] + wire cyc_E2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 184:22] + cyc_E2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 184:22] + wire cyc_E1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 185:22] + cyc_E1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 185:22] + wire zSigma1_B4 : UInt @[DivSqrtRecF64_mulAddZ31.scala 187:34] + zSigma1_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 187:34] + wire sigXNU_B3_CX : UInt @[DivSqrtRecF64_mulAddZ31.scala 188:34] + sigXNU_B3_CX is invalid @[DivSqrtRecF64_mulAddZ31.scala 188:34] + wire zComplSigT_C1_sqrt : UInt @[DivSqrtRecF64_mulAddZ31.scala 189:34] + zComplSigT_C1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 189:34] + wire zComplSigT_C1 : UInt @[DivSqrtRecF64_mulAddZ31.scala 190:34] + zComplSigT_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 190:34] + node _T_133 = eq(cyc_B7_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:21] + node _T_134 = and(ready_PA, _T_133) @[DivSqrtRecF64_mulAddZ31.scala 197:18] + node _T_136 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:38] + node _T_137 = and(_T_134, _T_136) @[DivSqrtRecF64_mulAddZ31.scala 197:35] + node _T_139 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:55] + node _T_140 = and(_T_137, _T_139) @[DivSqrtRecF64_mulAddZ31.scala 197:52] + node _T_142 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:13] + node _T_143 = and(_T_140, _T_142) @[DivSqrtRecF64_mulAddZ31.scala 197:69] + node _T_145 = eq(cyc_B3, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:30] + node _T_146 = and(_T_143, _T_145) @[DivSqrtRecF64_mulAddZ31.scala 198:27] + node _T_148 = eq(cyc_B2, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:42] + node _T_149 = and(_T_146, _T_148) @[DivSqrtRecF64_mulAddZ31.scala 198:39] + node _T_151 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:54] + node _T_152 = and(_T_149, _T_151) @[DivSqrtRecF64_mulAddZ31.scala 198:51] + node _T_154 = eq(cyc_C5, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:13] + node _T_155 = and(_T_152, _T_154) @[DivSqrtRecF64_mulAddZ31.scala 198:68] + node _T_157 = eq(cyc_C4, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:25] + node _T_158 = and(_T_155, _T_157) @[DivSqrtRecF64_mulAddZ31.scala 199:22] + io.inReady_div <= _T_158 @[DivSqrtRecF64_mulAddZ31.scala 195:20] + node _T_160 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:21] + node _T_161 = and(ready_PA, _T_160) @[DivSqrtRecF64_mulAddZ31.scala 201:18] + node _T_163 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:38] + node _T_164 = and(_T_161, _T_163) @[DivSqrtRecF64_mulAddZ31.scala 201:35] + node _T_166 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:55] + node _T_167 = and(_T_164, _T_166) @[DivSqrtRecF64_mulAddZ31.scala 201:52] + node _T_169 = eq(cyc_B2_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:13] + node _T_170 = and(_T_167, _T_169) @[DivSqrtRecF64_mulAddZ31.scala 201:69] + node _T_172 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:29] + node _T_173 = and(_T_170, _T_172) @[DivSqrtRecF64_mulAddZ31.scala 202:26] + io.inReady_sqrt <= _T_173 @[DivSqrtRecF64_mulAddZ31.scala 200:21] + node _T_174 = and(io.inReady_div, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 203:38] + node _T_176 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 203:55] + node cyc_S_div = and(_T_174, _T_176) @[DivSqrtRecF64_mulAddZ31.scala 203:52] + node _T_177 = and(io.inReady_sqrt, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 204:38] + node cyc_S_sqrt = and(_T_177, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 204:52] + node cyc_S = or(cyc_S_div, cyc_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 205:27] + node signA_S = bits(io.a, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 207:24] + node expA_S = bits(io.a, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 208:24] + node fractA_S = bits(io.a, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 209:24] + node specialCodeA_S = bits(expA_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 210:32] + node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 211:40] + node _T_179 = bits(specialCodeA_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 212:39] + node isSpecialA_S = eq(_T_179, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 212:46] + node signB_S = bits(io.b, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 214:24] + node expB_S = bits(io.b, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 215:24] + node fractB_S = bits(io.b, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 216:24] + node specialCodeB_S = bits(expB_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 217:32] + node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 218:40] + node _T_182 = bits(specialCodeB_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 219:39] + node isSpecialB_S = eq(_T_182, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 219:46] + node _T_184 = xor(signA_S, signB_S) @[DivSqrtRecF64_mulAddZ31.scala 221:50] + node sign_S = mux(io.sqrtOp, signB_S, _T_184) @[DivSqrtRecF64_mulAddZ31.scala 221:21] + node _T_186 = eq(isSpecialA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:9] + node _T_188 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:27] + node _T_189 = and(_T_186, _T_188) @[DivSqrtRecF64_mulAddZ31.scala 224:24] + node _T_191 = eq(isZeroA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:45] + node _T_192 = and(_T_189, _T_191) @[DivSqrtRecF64_mulAddZ31.scala 224:42] + node _T_194 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:60] + node normalCase_S_div = and(_T_192, _T_194) @[DivSqrtRecF64_mulAddZ31.scala 224:57] + node _T_196 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:29] + node _T_198 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:47] + node _T_199 = and(_T_196, _T_198) @[DivSqrtRecF64_mulAddZ31.scala 225:44] + node _T_201 = eq(signB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:62] + node normalCase_S_sqrt = and(_T_199, _T_201) @[DivSqrtRecF64_mulAddZ31.scala 225:59] + node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 226:27] + node cyc_A4_div = and(cyc_S_div, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 228:50] + node cyc_A7_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 229:50] + node entering_PA_normalCase = or(cyc_A4_div, cyc_A7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 231:36] + node _T_203 = eq(ready_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 233:58] + node _T_204 = or(valid_PA, _T_203) @[DivSqrtRecF64_mulAddZ31.scala 233:55] + node _T_205 = and(cyc_S, _T_204) @[DivSqrtRecF64_mulAddZ31.scala 233:42] + node entering_PA = or(entering_PA_normalCase, _T_205) @[DivSqrtRecF64_mulAddZ31.scala 233:32] + node _T_207 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:18] + node _T_208 = and(cyc_S, _T_207) @[DivSqrtRecF64_mulAddZ31.scala 235:15] + node _T_210 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:36] + node _T_211 = and(_T_208, _T_210) @[DivSqrtRecF64_mulAddZ31.scala 235:33] + node _T_213 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:29] + node _T_215 = eq(ready_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:43] + node _T_216 = and(_T_213, _T_215) @[DivSqrtRecF64_mulAddZ31.scala 236:40] + node _T_217 = or(leaving_PB, _T_216) @[DivSqrtRecF64_mulAddZ31.scala 236:25] + node entering_PB_S = and(_T_211, _T_217) @[DivSqrtRecF64_mulAddZ31.scala 235:47] + node _T_219 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:18] + node _T_220 = and(cyc_S, _T_219) @[DivSqrtRecF64_mulAddZ31.scala 238:15] + node _T_222 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:36] + node _T_223 = and(_T_220, _T_222) @[DivSqrtRecF64_mulAddZ31.scala 238:33] + node _T_225 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:50] + node _T_226 = and(_T_223, _T_225) @[DivSqrtRecF64_mulAddZ31.scala 238:47] + node entering_PC_S = and(_T_226, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 238:61] + node _T_227 = or(entering_PA, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 240:23] + when _T_227 : @[DivSqrtRecF64_mulAddZ31.scala 240:38] + valid_PA <= entering_PA @[DivSqrtRecF64_mulAddZ31.scala 241:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 240:38] + when entering_PA : @[DivSqrtRecF64_mulAddZ31.scala 243:24] + sqrtOp_PA <= io.sqrtOp @[DivSqrtRecF64_mulAddZ31.scala 244:25] + sign_PA <= sign_S @[DivSqrtRecF64_mulAddZ31.scala 245:25] + specialCodeB_PA <= specialCodeB_S @[DivSqrtRecF64_mulAddZ31.scala 246:25] + node _T_228 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 247:36] + fractB_51_PA <= _T_228 @[DivSqrtRecF64_mulAddZ31.scala 247:25] + roundingMode_PA <= io.roundingMode @[DivSqrtRecF64_mulAddZ31.scala 248:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 243:24] + node _T_230 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 250:26] + node _T_231 = and(entering_PA, _T_230) @[DivSqrtRecF64_mulAddZ31.scala 250:23] + when _T_231 : @[DivSqrtRecF64_mulAddZ31.scala 250:39] + specialCodeA_PA <= specialCodeA_S @[DivSqrtRecF64_mulAddZ31.scala 251:25] + node _T_232 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 252:36] + fractA_51_PA <= _T_232 @[DivSqrtRecF64_mulAddZ31.scala 252:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 250:39] + when entering_PA_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 254:35] + node _T_233 = bits(expB_S, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 258:44] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 71:15] + node _T_237 = mux(_T_234, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_238 = bits(expB_S, 10, 0) @[DivSqrtRecF64_mulAddZ31.scala 258:58] + node _T_239 = not(_T_238) @[DivSqrtRecF64_mulAddZ31.scala 258:51] + node _T_240 = cat(_T_237, _T_239) @[Cat.scala 30:58] + node _T_241 = add(expA_S, _T_240) @[DivSqrtRecF64_mulAddZ31.scala 258:24] + node _T_242 = tail(_T_241, 1) @[DivSqrtRecF64_mulAddZ31.scala 258:24] + node _T_243 = mux(io.sqrtOp, expB_S, _T_242) @[DivSqrtRecF64_mulAddZ31.scala 256:16] + exp_PA <= _T_243 @[DivSqrtRecF64_mulAddZ31.scala 255:16] + node _T_244 = bits(fractB_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 260:36] + fractB_other_PA <= _T_244 @[DivSqrtRecF64_mulAddZ31.scala 260:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 254:35] + when cyc_A4_div : @[DivSqrtRecF64_mulAddZ31.scala 262:39] + node _T_245 = bits(fractA_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 263:36] + fractA_other_PA <= _T_245 @[DivSqrtRecF64_mulAddZ31.scala 263:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 262:39] + node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 266:42] + node _T_247 = bits(specialCodeA_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 267:41] + node isSpecialA_PA = eq(_T_247, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 267:48] + node _T_250 = cat(UInt<1>("h01"), fractA_51_PA) @[Cat.scala 30:58] + node sigA_PA = cat(_T_250, fractA_other_PA) @[Cat.scala 30:58] + node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 270:42] + node _T_252 = bits(specialCodeB_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 271:41] + node isSpecialB_PA = eq(_T_252, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 271:48] + node _T_255 = cat(UInt<1>("h01"), fractB_51_PA) @[Cat.scala 30:58] + node sigB_PA = cat(_T_255, fractB_other_PA) @[Cat.scala 30:58] + node _T_257 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:13] + node _T_259 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:32] + node _T_260 = and(_T_257, _T_259) @[DivSqrtRecF64_mulAddZ31.scala 276:29] + node _T_262 = eq(sign_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:48] + node _T_263 = and(_T_260, _T_262) @[DivSqrtRecF64_mulAddZ31.scala 276:45] + node _T_265 = eq(isSpecialA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:13] + node _T_267 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:32] + node _T_268 = and(_T_265, _T_267) @[DivSqrtRecF64_mulAddZ31.scala 277:29] + node _T_270 = eq(isZeroA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:51] + node _T_271 = and(_T_268, _T_270) @[DivSqrtRecF64_mulAddZ31.scala 277:48] + node _T_273 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:67] + node _T_274 = and(_T_271, _T_273) @[DivSqrtRecF64_mulAddZ31.scala 277:64] + node normalCase_PA = mux(sqrtOp_PA, _T_263, _T_274) @[DivSqrtRecF64_mulAddZ31.scala 275:12] + node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 280:50] + node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) @[DivSqrtRecF64_mulAddZ31.scala 282:12] + node _T_275 = and(valid_PA, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 283:28] + leaving_PA <= _T_275 @[DivSqrtRecF64_mulAddZ31.scala 283:16] + node _T_277 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 284:17] + node _T_278 = or(_T_277, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 284:28] + ready_PA <= _T_278 @[DivSqrtRecF64_mulAddZ31.scala 284:14] + node _T_279 = and(valid_PA, normalCase_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:18] + node entering_PB_normalCase = and(_T_279, valid_normalCase_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:35] + node entering_PB = or(entering_PB_S, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 288:37] + node _T_280 = or(entering_PB, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 290:23] + when _T_280 : @[DivSqrtRecF64_mulAddZ31.scala 290:38] + valid_PB <= entering_PB @[DivSqrtRecF64_mulAddZ31.scala 291:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 290:38] + when entering_PB : @[DivSqrtRecF64_mulAddZ31.scala 293:24] + node _T_281 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 294:31] + sqrtOp_PB <= _T_281 @[DivSqrtRecF64_mulAddZ31.scala 294:25] + node _T_282 = mux(valid_PA, sign_PA, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 295:31] + sign_PB <= _T_282 @[DivSqrtRecF64_mulAddZ31.scala 295:25] + node _T_283 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 296:31] + specialCodeA_PB <= _T_283 @[DivSqrtRecF64_mulAddZ31.scala 296:25] + node _T_284 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 297:67] + node _T_285 = mux(valid_PA, fractA_51_PA, _T_284) @[DivSqrtRecF64_mulAddZ31.scala 297:31] + fractA_51_PB <= _T_285 @[DivSqrtRecF64_mulAddZ31.scala 297:25] + node _T_286 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 298:31] + specialCodeB_PB <= _T_286 @[DivSqrtRecF64_mulAddZ31.scala 298:25] + node _T_287 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 299:67] + node _T_288 = mux(valid_PA, fractB_51_PA, _T_287) @[DivSqrtRecF64_mulAddZ31.scala 299:31] + fractB_51_PB <= _T_288 @[DivSqrtRecF64_mulAddZ31.scala 299:25] + node _T_289 = mux(valid_PA, roundingMode_PA, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 300:31] + roundingMode_PB <= _T_289 @[DivSqrtRecF64_mulAddZ31.scala 300:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 293:24] + when entering_PB_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 302:35] + exp_PB <= exp_PA @[DivSqrtRecF64_mulAddZ31.scala 303:25] + node _T_290 = bits(fractA_other_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 304:43] + fractA_0_PB <= _T_290 @[DivSqrtRecF64_mulAddZ31.scala 304:25] + fractB_other_PB <= fractB_other_PA @[DivSqrtRecF64_mulAddZ31.scala 305:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 302:35] + node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 308:42] + node _T_292 = bits(specialCodeA_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 309:41] + node isSpecialA_PB = eq(_T_292, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 309:48] + node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 310:42] + node _T_295 = bits(specialCodeB_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 311:41] + node isSpecialB_PB = eq(_T_295, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 311:48] + node _T_298 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:13] + node _T_300 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:32] + node _T_301 = and(_T_298, _T_300) @[DivSqrtRecF64_mulAddZ31.scala 314:29] + node _T_303 = eq(sign_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:48] + node _T_304 = and(_T_301, _T_303) @[DivSqrtRecF64_mulAddZ31.scala 314:45] + node _T_306 = eq(isSpecialA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:13] + node _T_308 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:32] + node _T_309 = and(_T_306, _T_308) @[DivSqrtRecF64_mulAddZ31.scala 315:29] + node _T_311 = eq(isZeroA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:51] + node _T_312 = and(_T_309, _T_311) @[DivSqrtRecF64_mulAddZ31.scala 315:48] + node _T_314 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:67] + node _T_315 = and(_T_312, _T_314) @[DivSqrtRecF64_mulAddZ31.scala 315:64] + node normalCase_PB = mux(sqrtOp_PB, _T_304, _T_315) @[DivSqrtRecF64_mulAddZ31.scala 313:12] + node valid_leaving_PB = mux(normalCase_PB, cyc_C3, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 320:12] + node _T_316 = and(valid_PB, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 321:28] + leaving_PB <= _T_316 @[DivSqrtRecF64_mulAddZ31.scala 321:16] + node _T_318 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 322:17] + node _T_319 = or(_T_318, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 322:28] + ready_PB <= _T_319 @[DivSqrtRecF64_mulAddZ31.scala 322:14] + node _T_320 = and(valid_PB, normalCase_PB) @[DivSqrtRecF64_mulAddZ31.scala 325:18] + node entering_PC_normalCase = and(_T_320, cyc_C3) @[DivSqrtRecF64_mulAddZ31.scala 325:35] + node entering_PC = or(entering_PC_S, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 326:37] + node _T_321 = or(entering_PC, leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 328:23] + when _T_321 : @[DivSqrtRecF64_mulAddZ31.scala 328:38] + valid_PC <= entering_PC @[DivSqrtRecF64_mulAddZ31.scala 329:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 328:38] + when entering_PC : @[DivSqrtRecF64_mulAddZ31.scala 331:24] + node _T_322 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 332:31] + sqrtOp_PC <= _T_322 @[DivSqrtRecF64_mulAddZ31.scala 332:25] + node _T_323 = mux(valid_PB, sign_PB, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 333:31] + sign_PC <= _T_323 @[DivSqrtRecF64_mulAddZ31.scala 333:25] + node _T_324 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 334:31] + specialCodeA_PC <= _T_324 @[DivSqrtRecF64_mulAddZ31.scala 334:25] + node _T_325 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 335:67] + node _T_326 = mux(valid_PB, fractA_51_PB, _T_325) @[DivSqrtRecF64_mulAddZ31.scala 335:31] + fractA_51_PC <= _T_326 @[DivSqrtRecF64_mulAddZ31.scala 335:25] + node _T_327 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 336:31] + specialCodeB_PC <= _T_327 @[DivSqrtRecF64_mulAddZ31.scala 336:25] + node _T_328 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 337:67] + node _T_329 = mux(valid_PB, fractB_51_PB, _T_328) @[DivSqrtRecF64_mulAddZ31.scala 337:31] + fractB_51_PC <= _T_329 @[DivSqrtRecF64_mulAddZ31.scala 337:25] + node _T_330 = mux(valid_PB, roundingMode_PB, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 338:31] + roundingMode_PC <= _T_330 @[DivSqrtRecF64_mulAddZ31.scala 338:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 331:24] + when entering_PC_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 340:35] + exp_PC <= exp_PB @[DivSqrtRecF64_mulAddZ31.scala 341:25] + fractA_0_PC <= fractA_0_PB @[DivSqrtRecF64_mulAddZ31.scala 342:25] + fractB_other_PC <= fractB_other_PB @[DivSqrtRecF64_mulAddZ31.scala 343:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 340:35] + node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 346:42] + node _T_332 = bits(specialCodeA_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 347:41] + node isSpecialA_PC = eq(_T_332, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 347:48] + node _T_334 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 348:59] + node _T_336 = eq(_T_334, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 348:42] + node isInfA_PC = and(isSpecialA_PC, _T_336) @[DivSqrtRecF64_mulAddZ31.scala 348:39] + node _T_337 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 349:59] + node isNaNA_PC = and(isSpecialA_PC, _T_337) @[DivSqrtRecF64_mulAddZ31.scala 349:39] + node _T_339 = eq(fractA_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 350:38] + node isSigNaNA_PC = and(isNaNA_PC, _T_339) @[DivSqrtRecF64_mulAddZ31.scala 350:35] + node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 352:42] + node _T_341 = bits(specialCodeB_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 353:41] + node isSpecialB_PC = eq(_T_341, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 353:48] + node _T_343 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 354:59] + node _T_345 = eq(_T_343, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 354:42] + node isInfB_PC = and(isSpecialB_PC, _T_345) @[DivSqrtRecF64_mulAddZ31.scala 354:39] + node _T_346 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 355:59] + node isNaNB_PC = and(isSpecialB_PC, _T_346) @[DivSqrtRecF64_mulAddZ31.scala 355:39] + node _T_348 = eq(fractB_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 356:38] + node isSigNaNB_PC = and(isNaNB_PC, _T_348) @[DivSqrtRecF64_mulAddZ31.scala 356:35] + node _T_350 = cat(UInt<1>("h01"), fractB_51_PC) @[Cat.scala 30:58] + node sigB_PC = cat(_T_350, fractB_other_PC) @[Cat.scala 30:58] + node _T_352 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:24] + node _T_354 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:43] + node _T_355 = and(_T_352, _T_354) @[DivSqrtRecF64_mulAddZ31.scala 360:40] + node _T_357 = eq(sign_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:59] + node _T_358 = and(_T_355, _T_357) @[DivSqrtRecF64_mulAddZ31.scala 360:56] + node _T_360 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:13] + node _T_362 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:32] + node _T_363 = and(_T_360, _T_362) @[DivSqrtRecF64_mulAddZ31.scala 361:29] + node _T_365 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:51] + node _T_366 = and(_T_363, _T_365) @[DivSqrtRecF64_mulAddZ31.scala 361:48] + node _T_368 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:67] + node _T_369 = and(_T_366, _T_368) @[DivSqrtRecF64_mulAddZ31.scala 361:64] + node normalCase_PC = mux(sqrtOp_PC, _T_358, _T_369) @[DivSqrtRecF64_mulAddZ31.scala 360:12] + node _T_371 = add(exp_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 363:27] + node expP2_PC = tail(_T_371, 1) @[DivSqrtRecF64_mulAddZ31.scala 363:27] + node _T_372 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 365:19] + node _T_373 = bits(expP2_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 366:25] + node _T_375 = cat(_T_373, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_376 = bits(exp_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 367:23] + node _T_378 = cat(_T_376, UInt<1>("h01")) @[Cat.scala 30:58] + node expP1_PC = mux(_T_372, _T_375, _T_378) @[DivSqrtRecF64_mulAddZ31.scala 365:12] + node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 370:54] + node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 371:54] + node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 372:54] + node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 373:54] + node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) @[DivSqrtRecF64_mulAddZ31.scala 376:12] + node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 377:61] + node _T_380 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:27] + node _T_382 = eq(roundingMode_near_even_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:46] + node roundMagDown_PC = and(_T_380, _T_382) @[DivSqrtRecF64_mulAddZ31.scala 378:43] + node _T_384 = eq(normalCase_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 380:28] + node valid_leaving_PC = or(_T_384, cyc_E1) @[DivSqrtRecF64_mulAddZ31.scala 380:44] + node _T_385 = and(valid_PC, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 381:28] + leaving_PC <= _T_385 @[DivSqrtRecF64_mulAddZ31.scala 381:16] + node _T_387 = eq(valid_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 382:17] + node _T_388 = or(_T_387, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 382:28] + ready_PC <= _T_388 @[DivSqrtRecF64_mulAddZ31.scala 382:14] + node _T_390 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 383:39] + node _T_391 = and(leaving_PC, _T_390) @[DivSqrtRecF64_mulAddZ31.scala 383:36] + io.outValid_div <= _T_391 @[DivSqrtRecF64_mulAddZ31.scala 383:22] + node _T_392 = and(leaving_PC, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 384:36] + io.outValid_sqrt <= _T_392 @[DivSqrtRecF64_mulAddZ31.scala 384:22] + node _T_394 = neq(cycleNum_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 388:49] + node _T_395 = or(entering_PA_normalCase, _T_394) @[DivSqrtRecF64_mulAddZ31.scala 388:34] + when _T_395 : @[DivSqrtRecF64_mulAddZ31.scala 388:63] + node _T_398 = mux(cyc_A4_div, UInt<2>("h03"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 390:16] + node _T_401 = mux(cyc_A7_sqrt, UInt<3>("h06"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 391:16] + node _T_402 = or(_T_398, _T_401) @[DivSqrtRecF64_mulAddZ31.scala 390:74] + node _T_404 = eq(entering_PA_normalCase, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:17] + node _T_406 = sub(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_407 = asUInt(_T_406) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_408 = tail(_T_407, 1) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_410 = mux(_T_404, _T_408, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:16] + node _T_411 = or(_T_402, _T_410) @[DivSqrtRecF64_mulAddZ31.scala 391:74] + cycleNum_A <= _T_411 @[DivSqrtRecF64_mulAddZ31.scala 389:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 388:63] + node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 396:35] + node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 397:35] + node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 398:35] + node cyc_A4 = or(cyc_A4_sqrt, cyc_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 402:30] + node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 403:30] + node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 404:30] + node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 405:30] + node _T_419 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 407:32] + node cyc_A3_div = and(cyc_A3, _T_419) @[DivSqrtRecF64_mulAddZ31.scala 407:29] + node _T_421 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 408:32] + node cyc_A2_div = and(cyc_A2, _T_421) @[DivSqrtRecF64_mulAddZ31.scala 408:29] + node _T_423 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 409:32] + node cyc_A1_div = and(cyc_A1, _T_423) @[DivSqrtRecF64_mulAddZ31.scala 409:29] + node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 411:30] + node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 412:30] + node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 413:30] + node _T_425 = neq(cycleNum_B, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 415:33] + node _T_426 = or(cyc_A1, _T_425) @[DivSqrtRecF64_mulAddZ31.scala 415:18] + when _T_426 : @[DivSqrtRecF64_mulAddZ31.scala 415:47] + node _T_429 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 418:20] + node _T_431 = sub(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_432 = asUInt(_T_431) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_433 = tail(_T_432, 1) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_434 = mux(cyc_A1, _T_429, _T_433) @[DivSqrtRecF64_mulAddZ31.scala 417:16] + cycleNum_B <= _T_434 @[DivSqrtRecF64_mulAddZ31.scala 416:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 415:47] + node _T_436 = eq(cycleNum_B, UInt<4>("h0a")) @[DivSqrtRecF64_mulAddZ31.scala 423:33] + cyc_B10_sqrt <= _T_436 @[DivSqrtRecF64_mulAddZ31.scala 423:18] + node _T_438 = eq(cycleNum_B, UInt<4>("h09")) @[DivSqrtRecF64_mulAddZ31.scala 424:33] + cyc_B9_sqrt <= _T_438 @[DivSqrtRecF64_mulAddZ31.scala 424:18] + node _T_440 = eq(cycleNum_B, UInt<4>("h08")) @[DivSqrtRecF64_mulAddZ31.scala 425:33] + cyc_B8_sqrt <= _T_440 @[DivSqrtRecF64_mulAddZ31.scala 425:18] + node _T_442 = eq(cycleNum_B, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 426:33] + cyc_B7_sqrt <= _T_442 @[DivSqrtRecF64_mulAddZ31.scala 426:18] + node _T_444 = eq(cycleNum_B, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 428:27] + cyc_B6 <= _T_444 @[DivSqrtRecF64_mulAddZ31.scala 428:12] + node _T_446 = eq(cycleNum_B, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 429:27] + cyc_B5 <= _T_446 @[DivSqrtRecF64_mulAddZ31.scala 429:12] + node _T_448 = eq(cycleNum_B, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 430:27] + cyc_B4 <= _T_448 @[DivSqrtRecF64_mulAddZ31.scala 430:12] + node _T_450 = eq(cycleNum_B, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 431:27] + cyc_B3 <= _T_450 @[DivSqrtRecF64_mulAddZ31.scala 431:12] + node _T_452 = eq(cycleNum_B, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 432:27] + cyc_B2 <= _T_452 @[DivSqrtRecF64_mulAddZ31.scala 432:12] + node _T_454 = eq(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 433:27] + cyc_B1 <= _T_454 @[DivSqrtRecF64_mulAddZ31.scala 433:12] + node _T_455 = and(cyc_B6, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 435:26] + node _T_457 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 435:41] + node _T_458 = and(_T_455, _T_457) @[DivSqrtRecF64_mulAddZ31.scala 435:38] + cyc_B6_div <= _T_458 @[DivSqrtRecF64_mulAddZ31.scala 435:16] + node _T_459 = and(cyc_B5, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 436:26] + node _T_461 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 436:41] + node _T_462 = and(_T_459, _T_461) @[DivSqrtRecF64_mulAddZ31.scala 436:38] + cyc_B5_div <= _T_462 @[DivSqrtRecF64_mulAddZ31.scala 436:16] + node _T_463 = and(cyc_B4, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 437:26] + node _T_465 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 437:41] + node _T_466 = and(_T_463, _T_465) @[DivSqrtRecF64_mulAddZ31.scala 437:38] + cyc_B4_div <= _T_466 @[DivSqrtRecF64_mulAddZ31.scala 437:16] + node _T_468 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 438:29] + node _T_469 = and(cyc_B3, _T_468) @[DivSqrtRecF64_mulAddZ31.scala 438:26] + cyc_B3_div <= _T_469 @[DivSqrtRecF64_mulAddZ31.scala 438:16] + node _T_471 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 439:29] + node _T_472 = and(cyc_B2, _T_471) @[DivSqrtRecF64_mulAddZ31.scala 439:26] + cyc_B2_div <= _T_472 @[DivSqrtRecF64_mulAddZ31.scala 439:16] + node _T_474 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 440:29] + node _T_475 = and(cyc_B1, _T_474) @[DivSqrtRecF64_mulAddZ31.scala 440:26] + cyc_B1_div <= _T_475 @[DivSqrtRecF64_mulAddZ31.scala 440:16] + node _T_476 = and(cyc_B6, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:27] + node _T_477 = and(_T_476, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:39] + cyc_B6_sqrt <= _T_477 @[DivSqrtRecF64_mulAddZ31.scala 442:17] + node _T_478 = and(cyc_B5, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:27] + node _T_479 = and(_T_478, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:39] + cyc_B5_sqrt <= _T_479 @[DivSqrtRecF64_mulAddZ31.scala 443:17] + node _T_480 = and(cyc_B4, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:27] + node _T_481 = and(_T_480, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:39] + cyc_B4_sqrt <= _T_481 @[DivSqrtRecF64_mulAddZ31.scala 444:17] + node _T_482 = and(cyc_B3, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 445:27] + cyc_B3_sqrt <= _T_482 @[DivSqrtRecF64_mulAddZ31.scala 445:17] + node _T_483 = and(cyc_B2, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 446:27] + cyc_B2_sqrt <= _T_483 @[DivSqrtRecF64_mulAddZ31.scala 446:17] + node _T_484 = and(cyc_B1, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 447:27] + cyc_B1_sqrt <= _T_484 @[DivSqrtRecF64_mulAddZ31.scala 447:17] + node _T_486 = neq(cycleNum_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 449:33] + node _T_487 = or(cyc_B1, _T_486) @[DivSqrtRecF64_mulAddZ31.scala 449:18] + when _T_487 : @[DivSqrtRecF64_mulAddZ31.scala 449:47] + node _T_490 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 451:28] + node _T_492 = sub(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_493 = asUInt(_T_492) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_494 = tail(_T_493, 1) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_495 = mux(cyc_B1, _T_490, _T_494) @[DivSqrtRecF64_mulAddZ31.scala 451:16] + cycleNum_C <= _T_495 @[DivSqrtRecF64_mulAddZ31.scala 450:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 449:47] + node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 454:35] + node _T_498 = eq(cycleNum_C, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 456:27] + cyc_C5 <= _T_498 @[DivSqrtRecF64_mulAddZ31.scala 456:12] + node _T_500 = eq(cycleNum_C, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 457:27] + cyc_C4 <= _T_500 @[DivSqrtRecF64_mulAddZ31.scala 457:12] + node _T_502 = eq(cycleNum_C, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 458:27] + cyc_C3 <= _T_502 @[DivSqrtRecF64_mulAddZ31.scala 458:12] + node _T_504 = eq(cycleNum_C, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 459:27] + cyc_C2 <= _T_504 @[DivSqrtRecF64_mulAddZ31.scala 459:12] + node _T_506 = eq(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 460:27] + cyc_C1 <= _T_506 @[DivSqrtRecF64_mulAddZ31.scala 460:12] + node _T_508 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 462:32] + node cyc_C5_div = and(cyc_C5, _T_508) @[DivSqrtRecF64_mulAddZ31.scala 462:29] + node _T_510 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 463:32] + node cyc_C4_div = and(cyc_C4, _T_510) @[DivSqrtRecF64_mulAddZ31.scala 463:29] + node _T_512 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 464:32] + node cyc_C3_div = and(cyc_C3, _T_512) @[DivSqrtRecF64_mulAddZ31.scala 464:29] + node _T_514 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 465:32] + node cyc_C2_div = and(cyc_C2, _T_514) @[DivSqrtRecF64_mulAddZ31.scala 465:29] + node _T_516 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 466:32] + node cyc_C1_div = and(cyc_C1, _T_516) @[DivSqrtRecF64_mulAddZ31.scala 466:29] + node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 468:30] + node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 469:30] + node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 470:30] + node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 471:30] + node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 472:30] + node _T_518 = neq(cycleNum_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 474:33] + node _T_519 = or(cyc_C1, _T_518) @[DivSqrtRecF64_mulAddZ31.scala 474:18] + when _T_519 : @[DivSqrtRecF64_mulAddZ31.scala 474:47] + node _T_522 = sub(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_523 = asUInt(_T_522) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_524 = tail(_T_523, 1) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_525 = mux(cyc_C1, UInt<3>("h04"), _T_524) @[DivSqrtRecF64_mulAddZ31.scala 475:26] + cycleNum_E <= _T_525 @[DivSqrtRecF64_mulAddZ31.scala 475:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 474:47] + node _T_527 = eq(cycleNum_E, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 478:27] + cyc_E4 <= _T_527 @[DivSqrtRecF64_mulAddZ31.scala 478:12] + node _T_529 = eq(cycleNum_E, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 479:27] + cyc_E3 <= _T_529 @[DivSqrtRecF64_mulAddZ31.scala 479:12] + node _T_531 = eq(cycleNum_E, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 480:27] + cyc_E2 <= _T_531 @[DivSqrtRecF64_mulAddZ31.scala 480:12] + node _T_533 = eq(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 481:27] + cyc_E1 <= _T_533 @[DivSqrtRecF64_mulAddZ31.scala 481:12] + node _T_535 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 483:32] + node cyc_E4_div = and(cyc_E4, _T_535) @[DivSqrtRecF64_mulAddZ31.scala 483:29] + node _T_537 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 484:32] + node cyc_E3_div = and(cyc_E3, _T_537) @[DivSqrtRecF64_mulAddZ31.scala 484:29] + node _T_539 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 485:32] + node cyc_E2_div = and(cyc_E2, _T_539) @[DivSqrtRecF64_mulAddZ31.scala 485:29] + node _T_541 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 486:32] + node cyc_E1_div = and(cyc_E1, _T_541) @[DivSqrtRecF64_mulAddZ31.scala 486:29] + node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 488:30] + node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 489:30] + node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 490:30] + node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 491:30] + node zFractB_A4_div = mux(cyc_A4_div, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 496:29] + node _T_543 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 498:53] + node _T_545 = eq(_T_543, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 498:62] + node zLinPiece_0_A4_div = and(cyc_A4_div, _T_545) @[DivSqrtRecF64_mulAddZ31.scala 498:41] + node _T_546 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 499:53] + node _T_548 = eq(_T_546, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 499:62] + node zLinPiece_1_A4_div = and(cyc_A4_div, _T_548) @[DivSqrtRecF64_mulAddZ31.scala 499:41] + node _T_549 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 500:53] + node _T_551 = eq(_T_549, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 500:62] + node zLinPiece_2_A4_div = and(cyc_A4_div, _T_551) @[DivSqrtRecF64_mulAddZ31.scala 500:41] + node _T_552 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 501:53] + node _T_554 = eq(_T_552, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 501:62] + node zLinPiece_3_A4_div = and(cyc_A4_div, _T_554) @[DivSqrtRecF64_mulAddZ31.scala 501:41] + node _T_555 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 502:53] + node _T_557 = eq(_T_555, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 502:62] + node zLinPiece_4_A4_div = and(cyc_A4_div, _T_557) @[DivSqrtRecF64_mulAddZ31.scala 502:41] + node _T_558 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 503:53] + node _T_560 = eq(_T_558, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 503:62] + node zLinPiece_5_A4_div = and(cyc_A4_div, _T_560) @[DivSqrtRecF64_mulAddZ31.scala 503:41] + node _T_561 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 504:53] + node _T_563 = eq(_T_561, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 504:62] + node zLinPiece_6_A4_div = and(cyc_A4_div, _T_563) @[DivSqrtRecF64_mulAddZ31.scala 504:41] + node _T_564 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 505:53] + node _T_566 = eq(_T_564, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 505:62] + node zLinPiece_7_A4_div = and(cyc_A4_div, _T_566) @[DivSqrtRecF64_mulAddZ31.scala 505:41] + node _T_569 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 507:12] + node _T_572 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 508:12] + node _T_573 = or(_T_569, _T_572) @[DivSqrtRecF64_mulAddZ31.scala 507:59] + node _T_576 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 509:12] + node _T_577 = or(_T_573, _T_576) @[DivSqrtRecF64_mulAddZ31.scala 508:59] + node _T_580 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 510:12] + node _T_581 = or(_T_577, _T_580) @[DivSqrtRecF64_mulAddZ31.scala 509:59] + node _T_584 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 511:12] + node _T_585 = or(_T_581, _T_584) @[DivSqrtRecF64_mulAddZ31.scala 510:59] + node _T_588 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 512:12] + node _T_589 = or(_T_585, _T_588) @[DivSqrtRecF64_mulAddZ31.scala 511:59] + node _T_592 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 513:12] + node _T_593 = or(_T_589, _T_592) @[DivSqrtRecF64_mulAddZ31.scala 512:59] + node _T_596 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 514:12] + node zK1_A4_div = or(_T_593, _T_596) @[DivSqrtRecF64_mulAddZ31.scala 513:59] + node _T_598 = not(UInt<12>("h0fe3")) @[DivSqrtRecF64_mulAddZ31.scala 516:33] + node _T_600 = mux(zLinPiece_0_A4_div, _T_598, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 516:12] + node _T_602 = not(UInt<12>("h0c5d")) @[DivSqrtRecF64_mulAddZ31.scala 517:33] + node _T_604 = mux(zLinPiece_1_A4_div, _T_602, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 517:12] + node _T_605 = or(_T_600, _T_604) @[DivSqrtRecF64_mulAddZ31.scala 516:61] + node _T_607 = not(UInt<12>("h098a")) @[DivSqrtRecF64_mulAddZ31.scala 518:33] + node _T_609 = mux(zLinPiece_2_A4_div, _T_607, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 518:12] + node _T_610 = or(_T_605, _T_609) @[DivSqrtRecF64_mulAddZ31.scala 517:61] + node _T_612 = not(UInt<12>("h0739")) @[DivSqrtRecF64_mulAddZ31.scala 519:33] + node _T_614 = mux(zLinPiece_3_A4_div, _T_612, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 519:12] + node _T_615 = or(_T_610, _T_614) @[DivSqrtRecF64_mulAddZ31.scala 518:61] + node _T_617 = not(UInt<12>("h054b")) @[DivSqrtRecF64_mulAddZ31.scala 520:33] + node _T_619 = mux(zLinPiece_4_A4_div, _T_617, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 520:12] + node _T_620 = or(_T_615, _T_619) @[DivSqrtRecF64_mulAddZ31.scala 519:61] + node _T_622 = not(UInt<12>("h03a9")) @[DivSqrtRecF64_mulAddZ31.scala 521:33] + node _T_624 = mux(zLinPiece_5_A4_div, _T_622, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 521:12] + node _T_625 = or(_T_620, _T_624) @[DivSqrtRecF64_mulAddZ31.scala 520:61] + node _T_627 = not(UInt<12>("h0242")) @[DivSqrtRecF64_mulAddZ31.scala 522:33] + node _T_629 = mux(zLinPiece_6_A4_div, _T_627, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 522:12] + node _T_630 = or(_T_625, _T_629) @[DivSqrtRecF64_mulAddZ31.scala 521:61] + node _T_632 = not(UInt<12>("h010b")) @[DivSqrtRecF64_mulAddZ31.scala 523:33] + node _T_634 = mux(zLinPiece_7_A4_div, _T_632, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 523:12] + node zComplFractK0_A4_div = or(_T_630, _T_634) @[DivSqrtRecF64_mulAddZ31.scala 522:61] + node zFractB_A7_sqrt = mux(cyc_A7_sqrt, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 525:30] + node _T_636 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 527:55] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:47] + node _T_639 = and(cyc_A7_sqrt, _T_638) @[DivSqrtRecF64_mulAddZ31.scala 527:44] + node _T_640 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 527:72] + node _T_642 = eq(_T_640, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:62] + node zQuadPiece_0_A7_sqrt = and(_T_639, _T_642) @[DivSqrtRecF64_mulAddZ31.scala 527:59] + node _T_643 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 528:55] + node _T_645 = eq(_T_643, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 528:47] + node _T_646 = and(cyc_A7_sqrt, _T_645) @[DivSqrtRecF64_mulAddZ31.scala 528:44] + node _T_647 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 528:72] + node zQuadPiece_1_A7_sqrt = and(_T_646, _T_647) @[DivSqrtRecF64_mulAddZ31.scala 528:59] + node _T_648 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 529:55] + node _T_649 = and(cyc_A7_sqrt, _T_648) @[DivSqrtRecF64_mulAddZ31.scala 529:44] + node _T_650 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 529:72] + node _T_652 = eq(_T_650, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 529:62] + node zQuadPiece_2_A7_sqrt = and(_T_649, _T_652) @[DivSqrtRecF64_mulAddZ31.scala 529:59] + node _T_653 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 530:55] + node _T_654 = and(cyc_A7_sqrt, _T_653) @[DivSqrtRecF64_mulAddZ31.scala 530:44] + node _T_655 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 530:72] + node zQuadPiece_3_A7_sqrt = and(_T_654, _T_655) @[DivSqrtRecF64_mulAddZ31.scala 530:59] + node _T_658 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 532:12] + node _T_661 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 533:12] + node _T_662 = or(_T_658, _T_661) @[DivSqrtRecF64_mulAddZ31.scala 532:61] + node _T_665 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 534:12] + node _T_666 = or(_T_662, _T_665) @[DivSqrtRecF64_mulAddZ31.scala 533:61] + node _T_669 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 535:12] + node zK2_A7_sqrt = or(_T_666, _T_669) @[DivSqrtRecF64_mulAddZ31.scala 534:61] + node _T_671 = not(UInt<10>("h03d0")) @[DivSqrtRecF64_mulAddZ31.scala 537:35] + node _T_673 = mux(zQuadPiece_0_A7_sqrt, _T_671, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 537:12] + node _T_675 = not(UInt<10>("h0220")) @[DivSqrtRecF64_mulAddZ31.scala 538:35] + node _T_677 = mux(zQuadPiece_1_A7_sqrt, _T_675, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 538:12] + node _T_678 = or(_T_673, _T_677) @[DivSqrtRecF64_mulAddZ31.scala 537:63] + node _T_680 = not(UInt<10>("h02b2")) @[DivSqrtRecF64_mulAddZ31.scala 539:35] + node _T_682 = mux(zQuadPiece_2_A7_sqrt, _T_680, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 539:12] + node _T_683 = or(_T_678, _T_682) @[DivSqrtRecF64_mulAddZ31.scala 538:63] + node _T_685 = not(UInt<10>("h0181")) @[DivSqrtRecF64_mulAddZ31.scala 540:35] + node _T_687 = mux(zQuadPiece_3_A7_sqrt, _T_685, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 540:12] + node zComplK1_A7_sqrt = or(_T_683, _T_687) @[DivSqrtRecF64_mulAddZ31.scala 539:63] + node _T_688 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 542:55] + node _T_690 = eq(_T_688, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:47] + node _T_691 = and(cyc_A6_sqrt, _T_690) @[DivSqrtRecF64_mulAddZ31.scala 542:44] + node _T_692 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 542:71] + node _T_694 = eq(_T_692, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:62] + node zQuadPiece_0_A6_sqrt = and(_T_691, _T_694) @[DivSqrtRecF64_mulAddZ31.scala 542:59] + node _T_695 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 543:55] + node _T_697 = eq(_T_695, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 543:47] + node _T_698 = and(cyc_A6_sqrt, _T_697) @[DivSqrtRecF64_mulAddZ31.scala 543:44] + node _T_699 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 543:71] + node zQuadPiece_1_A6_sqrt = and(_T_698, _T_699) @[DivSqrtRecF64_mulAddZ31.scala 543:59] + node _T_700 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 544:55] + node _T_701 = and(cyc_A6_sqrt, _T_700) @[DivSqrtRecF64_mulAddZ31.scala 544:44] + node _T_702 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 544:71] + node _T_704 = eq(_T_702, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 544:62] + node zQuadPiece_2_A6_sqrt = and(_T_701, _T_704) @[DivSqrtRecF64_mulAddZ31.scala 544:59] + node _T_705 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 545:55] + node _T_706 = and(cyc_A6_sqrt, _T_705) @[DivSqrtRecF64_mulAddZ31.scala 545:44] + node _T_707 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 545:71] + node zQuadPiece_3_A6_sqrt = and(_T_706, _T_707) @[DivSqrtRecF64_mulAddZ31.scala 545:59] + node _T_709 = not(UInt<13>("h01fe5")) @[DivSqrtRecF64_mulAddZ31.scala 547:35] + node _T_711 = mux(zQuadPiece_0_A6_sqrt, _T_709, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 547:12] + node _T_713 = not(UInt<13>("h01435")) @[DivSqrtRecF64_mulAddZ31.scala 548:35] + node _T_715 = mux(zQuadPiece_1_A6_sqrt, _T_713, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 548:12] + node _T_716 = or(_T_711, _T_715) @[DivSqrtRecF64_mulAddZ31.scala 547:64] + node _T_718 = not(UInt<13>("h0d2c")) @[DivSqrtRecF64_mulAddZ31.scala 549:35] + node _T_720 = mux(zQuadPiece_2_A6_sqrt, _T_718, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 549:12] + node _T_721 = or(_T_716, _T_720) @[DivSqrtRecF64_mulAddZ31.scala 548:64] + node _T_723 = not(UInt<13>("h04e8")) @[DivSqrtRecF64_mulAddZ31.scala 550:35] + node _T_725 = mux(zQuadPiece_3_A6_sqrt, _T_723, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 550:12] + node zComplFractK0_A6_sqrt = or(_T_721, _T_725) @[DivSqrtRecF64_mulAddZ31.scala 549:64] + node _T_726 = bits(zFractB_A4_div, 48, 40) @[DivSqrtRecF64_mulAddZ31.scala 553:23] + node _T_727 = or(_T_726, zK2_A7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 553:32] + node _T_729 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:17] + node _T_731 = mux(_T_729, nextMulAdd9A_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:16] + node mulAdd9A_A = or(_T_727, _T_731) @[DivSqrtRecF64_mulAddZ31.scala 553:46] + node _T_732 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 556:37] + node _T_733 = or(zK1_A4_div, _T_732) @[DivSqrtRecF64_mulAddZ31.scala 556:20] + node _T_735 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:17] + node _T_737 = mux(_T_735, nextMulAdd9B_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:16] + node mulAdd9B_A = or(_T_733, _T_737) @[DivSqrtRecF64_mulAddZ31.scala 556:46] + node _T_738 = bits(cyc_A7_sqrt, 0, 0) @[Bitwise.scala 71:15] + node _T_741 = mux(_T_738, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_742 = cat(zComplK1_A7_sqrt, _T_741) @[Cat.scala 30:58] + node _T_743 = bits(cyc_A6_sqrt, 0, 0) @[Bitwise.scala 71:15] + node _T_746 = mux(_T_743, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 71:12] + node _T_747 = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) @[Cat.scala 30:58] + node _T_748 = cat(_T_747, _T_746) @[Cat.scala 30:58] + node _T_749 = or(_T_742, _T_748) @[DivSqrtRecF64_mulAddZ31.scala 559:71] + node _T_750 = bits(cyc_A4_div, 0, 0) @[Bitwise.scala 71:15] + node _T_753 = mux(_T_750, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_754 = cat(cyc_A4_div, zComplFractK0_A4_div) @[Cat.scala 30:58] + node _T_755 = cat(_T_754, _T_753) @[Cat.scala 30:58] + node _T_756 = or(_T_749, _T_755) @[DivSqrtRecF64_mulAddZ31.scala 560:71] + node _T_758 = shl(fractR0_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 563:54] + node _T_759 = add(UInt<20>("h040000"), _T_758) @[DivSqrtRecF64_mulAddZ31.scala 563:42] + node _T_760 = tail(_T_759, 1) @[DivSqrtRecF64_mulAddZ31.scala 563:42] + node _T_762 = mux(cyc_A5_sqrt, _T_760, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 563:12] + node _T_763 = or(_T_756, _T_762) @[DivSqrtRecF64_mulAddZ31.scala 561:71] + node _T_764 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 564:44] + node _T_766 = eq(_T_764, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:28] + node _T_767 = and(cyc_A4_sqrt, _T_766) @[DivSqrtRecF64_mulAddZ31.scala 564:25] + node _T_770 = mux(_T_767, UInt<11>("h0400"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:12] + node _T_771 = or(_T_763, _T_770) @[DivSqrtRecF64_mulAddZ31.scala 563:70] + node _T_772 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 565:43] + node _T_773 = and(cyc_A4_sqrt, _T_772) @[DivSqrtRecF64_mulAddZ31.scala 565:26] + node _T_774 = or(_T_773, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 565:48] + node _T_775 = bits(sigB_PA, 46, 26) @[DivSqrtRecF64_mulAddZ31.scala 566:20] + node _T_777 = add(_T_775, UInt<11>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 566:29] + node _T_778 = tail(_T_777, 1) @[DivSqrtRecF64_mulAddZ31.scala 566:29] + node _T_780 = mux(_T_774, _T_778, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 565:12] + node _T_781 = or(_T_771, _T_780) @[DivSqrtRecF64_mulAddZ31.scala 564:71] + node _T_782 = or(cyc_A3_sqrt, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 569:25] + node _T_784 = mux(_T_782, partNegSigma0_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 569:12] + node _T_785 = or(_T_781, _T_784) @[DivSqrtRecF64_mulAddZ31.scala 568:11] + node _T_786 = shl(fractR0_A, 16) @[DivSqrtRecF64_mulAddZ31.scala 570:45] + node _T_788 = mux(cyc_A1_sqrt, _T_786, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 570:12] + node _T_789 = or(_T_785, _T_788) @[DivSqrtRecF64_mulAddZ31.scala 569:62] + node _T_790 = shl(fractR0_A, 15) @[DivSqrtRecF64_mulAddZ31.scala 571:45] + node _T_792 = mux(cyc_A1_div, _T_790, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 571:12] + node mulAdd9C_A = or(_T_789, _T_792) @[DivSqrtRecF64_mulAddZ31.scala 570:62] + node _T_793 = mul(mulAdd9A_A, mulAdd9B_A) @[DivSqrtRecF64_mulAddZ31.scala 573:20] + node _T_795 = bits(mulAdd9C_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 573:61] + node _T_796 = cat(UInt<1>("h00"), _T_795) @[Cat.scala 30:58] + node _T_797 = add(_T_793, _T_796) @[DivSqrtRecF64_mulAddZ31.scala 573:33] + node loMulAdd9Out_A = tail(_T_797, 1) @[DivSqrtRecF64_mulAddZ31.scala 573:33] + node _T_798 = bits(loMulAdd9Out_A, 18, 18) @[DivSqrtRecF64_mulAddZ31.scala 575:31] + node _T_799 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 576:27] + node _T_801 = add(_T_799, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 576:36] + node _T_802 = tail(_T_801, 1) @[DivSqrtRecF64_mulAddZ31.scala 576:36] + node _T_803 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 577:27] + node _T_804 = mux(_T_798, _T_802, _T_803) @[DivSqrtRecF64_mulAddZ31.scala 575:16] + node _T_805 = bits(loMulAdd9Out_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 579:27] + node mulAdd9Out_A = cat(_T_804, _T_805) @[Cat.scala 30:58] + node _T_806 = bits(mulAdd9Out_A, 19, 19) @[DivSqrtRecF64_mulAddZ31.scala 583:40] + node _T_807 = and(cyc_A6_sqrt, _T_806) @[DivSqrtRecF64_mulAddZ31.scala 583:25] + node _T_808 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 584:13] + node _T_809 = shr(_T_808, 10) @[DivSqrtRecF64_mulAddZ31.scala 584:26] + node _T_811 = mux(_T_807, _T_809, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 583:12] + node zFractR0_A6_sqrt = bits(_T_811, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 586:10] + node _T_812 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 590:35] + node _T_813 = shl(mulAdd9Out_A, 1) @[DivSqrtRecF64_mulAddZ31.scala 590:52] + node sqrR0_A5_sqrt = mux(_T_812, _T_813, mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 590:28] + node _T_814 = bits(mulAdd9Out_A, 20, 20) @[DivSqrtRecF64_mulAddZ31.scala 592:39] + node _T_815 = and(cyc_A4_div, _T_814) @[DivSqrtRecF64_mulAddZ31.scala 592:24] + node _T_816 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 593:13] + node _T_817 = shr(_T_816, 11) @[DivSqrtRecF64_mulAddZ31.scala 593:26] + node _T_819 = mux(_T_815, _T_817, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 592:12] + node zFractR0_A4_div = bits(_T_819, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 595:10] + node _T_820 = bits(mulAdd9Out_A, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 598:35] + node _T_821 = and(cyc_A2, _T_820) @[DivSqrtRecF64_mulAddZ31.scala 598:20] + node _T_822 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 598:41] + node _T_823 = shr(_T_822, 2) @[DivSqrtRecF64_mulAddZ31.scala 598:54] + node _T_825 = mux(_T_821, _T_823, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 598:12] + node zSigma0_A2 = bits(_T_825, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 598:67] + node _T_826 = shr(mulAdd9Out_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 601:36] + node _T_827 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 601:54] + node _T_828 = mux(sqrtOp_PA, _T_826, _T_827) @[DivSqrtRecF64_mulAddZ31.scala 601:12] + node fractR1_A1 = bits(_T_828, 14, 0) @[DivSqrtRecF64_mulAddZ31.scala 601:58] + node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) @[Cat.scala 30:58] + node _T_830 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 603:33] + node _T_831 = shl(r1_A1, 1) @[DivSqrtRecF64_mulAddZ31.scala 603:43] + node ER1_A1_sqrt = mux(_T_830, _T_831, r1_A1) @[DivSqrtRecF64_mulAddZ31.scala 603:26] + node _T_832 = or(cyc_A6_sqrt, cyc_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 605:23] + when _T_832 : @[DivSqrtRecF64_mulAddZ31.scala 605:38] + node _T_833 = or(zFractR0_A6_sqrt, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 606:39] + fractR0_A <= _T_833 @[DivSqrtRecF64_mulAddZ31.scala 606:19] + skip @[DivSqrtRecF64_mulAddZ31.scala 605:38] + when cyc_A5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 609:24] + node _T_834 = shr(sqrR0_A5_sqrt, 10) @[DivSqrtRecF64_mulAddZ31.scala 610:40] + hiSqrR0_A_sqrt <= _T_834 @[DivSqrtRecF64_mulAddZ31.scala 610:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 609:24] + node _T_835 = or(cyc_A4_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 613:23] + when _T_835 : @[DivSqrtRecF64_mulAddZ31.scala 613:34] + node _T_836 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 616:56] + node _T_837 = mux(cyc_A4_sqrt, mulAdd9Out_A, _T_836) @[DivSqrtRecF64_mulAddZ31.scala 616:16] + node _T_838 = bits(_T_837, 20, 0) @[DivSqrtRecF64_mulAddZ31.scala 616:60] + partNegSigma0_A <= _T_838 @[DivSqrtRecF64_mulAddZ31.scala 615:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 613:34] + node _T_839 = or(cyc_A7_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:21] + node _T_840 = or(_T_839, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:36] + node _T_841 = or(_T_840, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 620:51] + node _T_842 = or(_T_841, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 620:61] + node _T_843 = or(_T_842, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 620:71] + when _T_843 : @[DivSqrtRecF64_mulAddZ31.scala 621:7] + node _T_844 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 623:40] + node _T_845 = shr(_T_844, 11) @[DivSqrtRecF64_mulAddZ31.scala 623:53] + node _T_847 = mux(cyc_A7_sqrt, _T_845, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 623:16] + node _T_848 = or(_T_847, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 623:68] + node _T_849 = bits(sigB_PA, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 625:47] + node _T_851 = mux(cyc_A4_sqrt, _T_849, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 625:16] + node _T_852 = or(_T_848, _T_851) @[DivSqrtRecF64_mulAddZ31.scala 624:68] + node _T_853 = bits(zFractB_A4_div, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 626:27] + node _T_854 = or(_T_852, _T_853) @[DivSqrtRecF64_mulAddZ31.scala 625:68] + node _T_855 = or(cyc_A5_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 627:29] + node _T_856 = bits(sigB_PA, 52, 44) @[DivSqrtRecF64_mulAddZ31.scala 627:47] + node _T_858 = mux(_T_855, _T_856, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 627:16] + node _T_859 = or(_T_854, _T_858) @[DivSqrtRecF64_mulAddZ31.scala 626:68] + node _T_860 = or(_T_859, zSigma0_A2) @[DivSqrtRecF64_mulAddZ31.scala 627:68] + nextMulAdd9A_A <= _T_860 @[DivSqrtRecF64_mulAddZ31.scala 622:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 621:7] + node _T_861 = or(cyc_A7_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:23] + node _T_862 = or(_T_861, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:38] + node _T_863 = or(_T_862, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 630:53] + node _T_864 = or(_T_863, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 630:63] + when _T_864 : @[DivSqrtRecF64_mulAddZ31.scala 630:74] + node _T_865 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 632:28] + node _T_866 = or(_T_865, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 632:73] + node _T_867 = bits(sqrR0_A5_sqrt, 9, 1) @[DivSqrtRecF64_mulAddZ31.scala 634:43] + node _T_869 = mux(cyc_A5_sqrt, _T_867, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 634:16] + node _T_870 = or(_T_866, _T_869) @[DivSqrtRecF64_mulAddZ31.scala 633:73] + node _T_871 = or(_T_870, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 634:73] + node _T_872 = bits(hiSqrR0_A_sqrt, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 636:44] + node _T_874 = mux(cyc_A4_sqrt, _T_872, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 636:16] + node _T_875 = or(_T_871, _T_874) @[DivSqrtRecF64_mulAddZ31.scala 635:73] + node _T_877 = bits(fractR0_A, 8, 1) @[DivSqrtRecF64_mulAddZ31.scala 637:55] + node _T_878 = cat(UInt<1>("h01"), _T_877) @[Cat.scala 30:58] + node _T_880 = mux(cyc_A2, _T_878, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 637:16] + node _T_881 = or(_T_875, _T_880) @[DivSqrtRecF64_mulAddZ31.scala 636:73] + nextMulAdd9B_A <= _T_881 @[DivSqrtRecF64_mulAddZ31.scala 631:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 630:74] + when cyc_A1_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 640:24] + ER1_B_sqrt <= ER1_A1_sqrt @[DivSqrtRecF64_mulAddZ31.scala 641:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 640:24] + node _T_882 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:16] + node _T_883 = or(_T_882, cyc_B6_div) @[DivSqrtRecF64_mulAddZ31.scala 647:31] + node _T_884 = or(_T_883, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 647:45] + node _T_885 = or(_T_884, cyc_B3) @[DivSqrtRecF64_mulAddZ31.scala 647:55] + node _T_886 = or(_T_885, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:65] + node _T_887 = or(_T_886, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 648:25] + node _T_888 = or(_T_887, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 648:35] + io.latchMulAddA_0 <= _T_888 @[DivSqrtRecF64_mulAddZ31.scala 646:23] + node _T_889 = shl(ER1_A1_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 650:51] + node _T_891 = mux(cyc_A1_sqrt, _T_889, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 650:12] + node _T_892 = or(cyc_B7_sqrt, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 651:25] + node _T_894 = mux(_T_892, sigB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 651:12] + node _T_895 = or(_T_891, _T_894) @[DivSqrtRecF64_mulAddZ31.scala 650:67] + node _T_897 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 652:12] + node _T_898 = or(_T_895, _T_897) @[DivSqrtRecF64_mulAddZ31.scala 651:67] + node _T_899 = bits(zSigma1_B4, 45, 12) @[DivSqrtRecF64_mulAddZ31.scala 653:19] + node _T_900 = or(_T_898, _T_899) @[DivSqrtRecF64_mulAddZ31.scala 652:67] + node _T_901 = or(cyc_B3, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 655:20] + node _T_902 = bits(sigXNU_B3_CX, 57, 12) @[DivSqrtRecF64_mulAddZ31.scala 655:48] + node _T_904 = mux(_T_901, _T_902, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 655:12] + node _T_905 = or(_T_900, _T_904) @[DivSqrtRecF64_mulAddZ31.scala 653:67] + node _T_906 = bits(sigXN_C, 57, 25) @[DivSqrtRecF64_mulAddZ31.scala 656:43] + node _T_907 = shl(_T_906, 13) @[DivSqrtRecF64_mulAddZ31.scala 656:51] + node _T_909 = mux(cyc_C4_div, _T_907, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 656:12] + node _T_910 = or(_T_905, _T_909) @[DivSqrtRecF64_mulAddZ31.scala 655:67] + node _T_911 = shl(u_C_sqrt, 15) @[DivSqrtRecF64_mulAddZ31.scala 657:44] + node _T_913 = mux(cyc_C4_sqrt, _T_911, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 657:12] + node _T_914 = or(_T_910, _T_913) @[DivSqrtRecF64_mulAddZ31.scala 656:67] + node _T_916 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 658:12] + node _T_917 = or(_T_914, _T_916) @[DivSqrtRecF64_mulAddZ31.scala 657:67] + node _T_918 = or(_T_917, zComplSigT_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 658:67] + io.mulAddA_0 <= _T_918 @[DivSqrtRecF64_mulAddZ31.scala 649:18] + node _T_919 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:16] + node _T_920 = or(_T_919, cyc_B6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:31] + node _T_921 = or(_T_920, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 661:46] + node _T_922 = or(_T_921, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:56] + node _T_923 = or(_T_922, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 662:25] + node _T_924 = or(_T_923, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 662:35] + io.latchMulAddB_0 <= _T_924 @[DivSqrtRecF64_mulAddZ31.scala 660:23] + node _T_925 = shl(r1_A1, 36) @[DivSqrtRecF64_mulAddZ31.scala 664:31] + node _T_927 = mux(cyc_A1, _T_925, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 664:12] + node _T_928 = shl(ESqrR1_B_sqrt, 19) @[DivSqrtRecF64_mulAddZ31.scala 665:39] + node _T_930 = mux(cyc_B7_sqrt, _T_928, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 665:12] + node _T_931 = or(_T_927, _T_930) @[DivSqrtRecF64_mulAddZ31.scala 664:55] + node _T_932 = shl(ER1_B_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 666:36] + node _T_934 = mux(cyc_B6_sqrt, _T_932, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 666:12] + node _T_935 = or(_T_931, _T_934) @[DivSqrtRecF64_mulAddZ31.scala 665:55] + node _T_936 = or(_T_935, zSigma1_B4) @[DivSqrtRecF64_mulAddZ31.scala 666:55] + node _T_937 = bits(sqrSigma1_C, 30, 1) @[DivSqrtRecF64_mulAddZ31.scala 668:37] + node _T_939 = mux(cyc_C6_sqrt, _T_937, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 668:12] + node _T_940 = or(_T_936, _T_939) @[DivSqrtRecF64_mulAddZ31.scala 667:55] + node _T_942 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 669:12] + node _T_943 = or(_T_940, _T_942) @[DivSqrtRecF64_mulAddZ31.scala 668:55] + node _T_944 = or(_T_943, zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 669:55] + io.mulAddB_0 <= _T_944 @[DivSqrtRecF64_mulAddZ31.scala 663:18] + node _T_945 = or(cyc_A4, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 672:20] + node _T_946 = or(_T_945, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 672:34] + node _T_947 = or(_T_946, cyc_B10_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 672:48] + node _T_948 = or(_T_947, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:30] + node _T_949 = or(_T_948, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:45] + node _T_950 = or(_T_949, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 673:60] + node _T_951 = or(_T_950, cyc_B5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:70] + node _T_952 = or(_T_951, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:29] + node _T_953 = or(_T_952, cyc_B2_div) @[DivSqrtRecF64_mulAddZ31.scala 674:44] + node _T_954 = or(_T_953, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:58] + node _T_955 = or(_T_954, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 674:73] + node _T_956 = or(cyc_A3, cyc_A2_div) @[DivSqrtRecF64_mulAddZ31.scala 676:20] + node _T_957 = or(_T_956, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 676:34] + node _T_958 = or(_T_957, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:29] + node _T_959 = or(_T_958, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 677:44] + node _T_960 = or(_T_959, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 677:54] + node _T_961 = or(_T_960, cyc_B4_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:64] + node _T_962 = or(_T_961, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:29] + node _T_963 = or(_T_962, cyc_B1_div) @[DivSqrtRecF64_mulAddZ31.scala 678:44] + node _T_964 = or(_T_963, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:58] + node _T_965 = or(_T_964, cyc_C3) @[DivSqrtRecF64_mulAddZ31.scala 678:73] + node _T_966 = or(cyc_A2, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 680:20] + node _T_967 = or(_T_966, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 680:34] + node _T_968 = or(_T_967, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:29] + node _T_969 = or(_T_968, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 681:44] + node _T_970 = or(_T_969, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 681:54] + node _T_971 = or(_T_970, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:64] + node _T_972 = or(_T_971, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 682:29] + node _T_973 = or(_T_972, cyc_C5) @[DivSqrtRecF64_mulAddZ31.scala 682:44] + node _T_974 = or(_T_973, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 682:54] + node _T_975 = or(io.latchMulAddA_0, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 684:31] + node _T_976 = or(_T_975, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 684:41] + node _T_977 = cat(_T_974, _T_976) @[Cat.scala 30:58] + node _T_978 = cat(_T_955, _T_965) @[Cat.scala 30:58] + node _T_979 = cat(_T_978, _T_977) @[Cat.scala 30:58] + io.usingMulAdd <= _T_979 @[DivSqrtRecF64_mulAddZ31.scala 671:20] + node _T_980 = shl(sigX1_B, 47) @[DivSqrtRecF64_mulAddZ31.scala 688:45] + node _T_982 = mux(cyc_B1, _T_980, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 688:12] + node _T_983 = shl(sigX1_B, 46) @[DivSqrtRecF64_mulAddZ31.scala 689:45] + node _T_985 = mux(cyc_C6_sqrt, _T_983, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 689:12] + node _T_986 = or(_T_982, _T_985) @[DivSqrtRecF64_mulAddZ31.scala 688:64] + node _T_987 = or(cyc_C4_sqrt, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 690:25] + node _T_988 = shl(sigXN_C, 47) @[DivSqrtRecF64_mulAddZ31.scala 690:45] + node _T_990 = mux(_T_987, _T_988, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 690:12] + node _T_991 = or(_T_986, _T_990) @[DivSqrtRecF64_mulAddZ31.scala 689:64] + node _T_993 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:27] + node _T_994 = and(cyc_E3_div, _T_993) @[DivSqrtRecF64_mulAddZ31.scala 691:24] + node _T_995 = shl(fractA_0_PC, 53) @[DivSqrtRecF64_mulAddZ31.scala 691:49] + node _T_997 = mux(_T_994, _T_995, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:12] + node _T_998 = or(_T_991, _T_997) @[DivSqrtRecF64_mulAddZ31.scala 690:64] + node _T_999 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 693:24] + node _T_1000 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 694:29] + node _T_1002 = cat(_T_1000, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1003 = bits(sigB_PC, 1, 1) @[DivSqrtRecF64_mulAddZ31.scala 695:29] + node _T_1004 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:42] + node _T_1005 = xor(_T_1003, _T_1004) @[DivSqrtRecF64_mulAddZ31.scala 695:33] + node _T_1006 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:54] + node _T_1007 = cat(_T_1005, _T_1006) @[Cat.scala 30:58] + node _T_1008 = mux(_T_999, _T_1002, _T_1007) @[DivSqrtRecF64_mulAddZ31.scala 693:17] + node _T_1010 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 696:22] + node _T_1012 = cat(_T_1010, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1013 = xor(_T_1008, _T_1012) @[DivSqrtRecF64_mulAddZ31.scala 696:16] + node _T_1014 = shl(_T_1013, 54) @[DivSqrtRecF64_mulAddZ31.scala 697:14] + node _T_1016 = mux(cyc_E3_sqrt, _T_1014, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 692:12] + node _T_1017 = or(_T_998, _T_1016) @[DivSqrtRecF64_mulAddZ31.scala 691:64] + io.mulAddC_2 <= _T_1017 @[DivSqrtRecF64_mulAddZ31.scala 687:18] + node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) @[DivSqrtRecF64_mulAddZ31.scala 701:43] + node _T_1018 = bits(io.mulAddResult_3, 90, 45) @[DivSqrtRecF64_mulAddZ31.scala 702:49] + node _T_1019 = not(_T_1018) @[DivSqrtRecF64_mulAddZ31.scala 702:31] + node _T_1021 = mux(cyc_B4, _T_1019, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 702:22] + zSigma1_B4 <= _T_1021 @[DivSqrtRecF64_mulAddZ31.scala 702:16] + node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) @[DivSqrtRecF64_mulAddZ31.scala 703:41] + node _T_1022 = bits(io.mulAddResult_3, 104, 47) @[DivSqrtRecF64_mulAddZ31.scala 704:38] + sigXNU_B3_CX <= _T_1022 @[DivSqrtRecF64_mulAddZ31.scala 704:18] + node _T_1023 = bits(io.mulAddResult_3, 104, 104) @[DivSqrtRecF64_mulAddZ31.scala 705:39] + node E_C1_div = eq(_T_1023, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 705:20] + node _T_1026 = eq(E_C1_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:28] + node _T_1027 = and(cyc_C1_div, _T_1026) @[DivSqrtRecF64_mulAddZ31.scala 707:25] + node _T_1028 = or(_T_1027, cyc_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 707:40] + node _T_1029 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 708:31] + node _T_1030 = not(_T_1029) @[DivSqrtRecF64_mulAddZ31.scala 708:13] + node _T_1032 = mux(_T_1028, _T_1030, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:12] + node _T_1033 = and(cyc_C1_div, E_C1_div) @[DivSqrtRecF64_mulAddZ31.scala 711:24] + node _T_1035 = bits(io.mulAddResult_3, 102, 50) @[DivSqrtRecF64_mulAddZ31.scala 712:47] + node _T_1036 = not(_T_1035) @[DivSqrtRecF64_mulAddZ31.scala 712:29] + node _T_1037 = cat(UInt<1>("h00"), _T_1036) @[Cat.scala 30:58] + node _T_1039 = mux(_T_1033, _T_1037, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 711:12] + node _T_1040 = or(_T_1032, _T_1039) @[DivSqrtRecF64_mulAddZ31.scala 710:11] + zComplSigT_C1 <= _T_1040 @[DivSqrtRecF64_mulAddZ31.scala 706:19] + node _T_1041 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 716:44] + node _T_1042 = not(_T_1041) @[DivSqrtRecF64_mulAddZ31.scala 716:26] + node _T_1044 = mux(cyc_C1_sqrt, _T_1042, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 716:12] + zComplSigT_C1_sqrt <= _T_1044 @[DivSqrtRecF64_mulAddZ31.scala 715:24] + node sigT_C1 = not(zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 720:19] + node remT_E2 = bits(io.mulAddResult_3, 55, 0) @[DivSqrtRecF64_mulAddZ31.scala 721:36] + when cyc_B8_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 723:24] + ESqrR1_B_sqrt <= ESqrR1_B8_sqrt @[DivSqrtRecF64_mulAddZ31.scala 724:23] + skip @[DivSqrtRecF64_mulAddZ31.scala 723:24] + when cyc_B3 : @[DivSqrtRecF64_mulAddZ31.scala 726:19] + sigX1_B <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 727:17] + skip @[DivSqrtRecF64_mulAddZ31.scala 726:19] + when cyc_B1 : @[DivSqrtRecF64_mulAddZ31.scala 729:19] + sqrSigma1_C <= sqrSigma1_B1 @[DivSqrtRecF64_mulAddZ31.scala 730:21] + skip @[DivSqrtRecF64_mulAddZ31.scala 729:19] + node _T_1045 = or(cyc_C6_sqrt, cyc_C5_div) @[DivSqrtRecF64_mulAddZ31.scala 733:23] + node _T_1046 = or(_T_1045, cyc_C3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 733:37] + when _T_1046 : @[DivSqrtRecF64_mulAddZ31.scala 733:53] + sigXN_C <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 734:17] + skip @[DivSqrtRecF64_mulAddZ31.scala 733:53] + when cyc_C5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 736:24] + node _T_1047 = bits(sigXNU_B3_CX, 56, 26) @[DivSqrtRecF64_mulAddZ31.scala 737:33] + u_C_sqrt <= _T_1047 @[DivSqrtRecF64_mulAddZ31.scala 737:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 736:24] + when cyc_C1 : @[DivSqrtRecF64_mulAddZ31.scala 739:19] + E_E_div <= E_C1_div @[DivSqrtRecF64_mulAddZ31.scala 740:18] + node _T_1048 = bits(sigT_C1, 53, 1) @[DivSqrtRecF64_mulAddZ31.scala 741:28] + sigT_E <= _T_1048 @[DivSqrtRecF64_mulAddZ31.scala 741:18] + node _T_1049 = bits(sigT_C1, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 742:28] + extraT_E <= _T_1049 @[DivSqrtRecF64_mulAddZ31.scala 742:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 739:19] + when cyc_E2 : @[DivSqrtRecF64_mulAddZ31.scala 745:19] + node _T_1050 = bits(remT_E2, 55, 55) @[DivSqrtRecF64_mulAddZ31.scala 746:47] + node _T_1051 = bits(remT_E2, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 746:61] + node _T_1052 = mux(sqrtOp_PC, _T_1050, _T_1051) @[DivSqrtRecF64_mulAddZ31.scala 746:27] + isNegRemT_E <= _T_1052 @[DivSqrtRecF64_mulAddZ31.scala 746:21] + node _T_1053 = bits(remT_E2, 53, 0) @[DivSqrtRecF64_mulAddZ31.scala 748:21] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 748:29] + node _T_1057 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:18] + node _T_1058 = bits(remT_E2, 55, 54) @[DivSqrtRecF64_mulAddZ31.scala 749:41] + node _T_1060 = eq(_T_1058, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:50] + node _T_1061 = or(_T_1057, _T_1060) @[DivSqrtRecF64_mulAddZ31.scala 749:30] + node _T_1062 = and(_T_1055, _T_1061) @[DivSqrtRecF64_mulAddZ31.scala 748:42] + isZeroRemT_E <= _T_1062 @[DivSqrtRecF64_mulAddZ31.scala 747:22] + skip @[DivSqrtRecF64_mulAddZ31.scala 745:19] + node _T_1064 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:13] + node _T_1065 = and(_T_1064, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 755:25] + node _T_1067 = mux(_T_1065, exp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:12] + node _T_1069 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:13] + node _T_1071 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:28] + node _T_1072 = and(_T_1069, _T_1071) @[DivSqrtRecF64_mulAddZ31.scala 756:25] + node _T_1074 = mux(_T_1072, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:12] + node _T_1075 = or(_T_1067, _T_1074) @[DivSqrtRecF64_mulAddZ31.scala 755:76] + node _T_1076 = shr(exp_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:42] + node _T_1078 = add(_T_1076, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 757:47] + node _T_1079 = tail(_T_1078, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:47] + node _T_1081 = mux(sqrtOp_PC, _T_1079, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 757:12] + node sExpX_E = or(_T_1075, _T_1081) @[DivSqrtRecF64_mulAddZ31.scala 756:76] + node posExpX_E = bits(sExpX_E, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 759:28] + node _T_1082 = not(posExpX_E) @[primitives.scala 50:21] + node _T_1083 = bits(_T_1082, 12, 12) @[primitives.scala 56:25] + node _T_1084 = bits(_T_1082, 11, 0) @[primitives.scala 57:26] + node _T_1085 = bits(_T_1084, 11, 11) @[primitives.scala 56:25] + node _T_1086 = bits(_T_1084, 10, 0) @[primitives.scala 57:26] + node _T_1087 = bits(_T_1086, 10, 10) @[primitives.scala 56:25] + node _T_1088 = bits(_T_1086, 9, 0) @[primitives.scala 57:26] + node _T_1089 = bits(_T_1088, 9, 9) @[primitives.scala 56:25] + node _T_1090 = bits(_T_1088, 8, 0) @[primitives.scala 57:26] + node _T_1092 = bits(_T_1090, 8, 8) @[primitives.scala 56:25] + node _T_1093 = bits(_T_1090, 7, 0) @[primitives.scala 57:26] + node _T_1095 = bits(_T_1093, 7, 7) @[primitives.scala 56:25] + node _T_1096 = bits(_T_1093, 6, 0) @[primitives.scala 57:26] + node _T_1098 = bits(_T_1096, 6, 6) @[primitives.scala 56:25] + node _T_1099 = bits(_T_1096, 5, 0) @[primitives.scala 57:26] + node _T_1102 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_1099) @[primitives.scala 68:52] + node _T_1103 = bits(_T_1102, 63, 14) @[primitives.scala 69:26] + node _T_1104 = bits(_T_1103, 31, 0) @[Bitwise.scala 108:18] + node _T_1107 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_1108 = xor(UInt<32>("h0ffffffff"), _T_1107) @[Bitwise.scala 101:21] + node _T_1109 = shr(_T_1104, 16) @[Bitwise.scala 102:21] + node _T_1110 = and(_T_1109, _T_1108) @[Bitwise.scala 102:31] + node _T_1111 = bits(_T_1104, 15, 0) @[Bitwise.scala 102:46] + node _T_1112 = shl(_T_1111, 16) @[Bitwise.scala 102:65] + node _T_1113 = not(_T_1108) @[Bitwise.scala 102:77] + node _T_1114 = and(_T_1112, _T_1113) @[Bitwise.scala 102:75] + node _T_1115 = or(_T_1110, _T_1114) @[Bitwise.scala 102:39] + node _T_1116 = bits(_T_1108, 23, 0) @[Bitwise.scala 101:28] + node _T_1117 = shl(_T_1116, 8) @[Bitwise.scala 101:47] + node _T_1118 = xor(_T_1108, _T_1117) @[Bitwise.scala 101:21] + node _T_1119 = shr(_T_1115, 8) @[Bitwise.scala 102:21] + node _T_1120 = and(_T_1119, _T_1118) @[Bitwise.scala 102:31] + node _T_1121 = bits(_T_1115, 23, 0) @[Bitwise.scala 102:46] + node _T_1122 = shl(_T_1121, 8) @[Bitwise.scala 102:65] + node _T_1123 = not(_T_1118) @[Bitwise.scala 102:77] + node _T_1124 = and(_T_1122, _T_1123) @[Bitwise.scala 102:75] + node _T_1125 = or(_T_1120, _T_1124) @[Bitwise.scala 102:39] + node _T_1126 = bits(_T_1118, 27, 0) @[Bitwise.scala 101:28] + node _T_1127 = shl(_T_1126, 4) @[Bitwise.scala 101:47] + node _T_1128 = xor(_T_1118, _T_1127) @[Bitwise.scala 101:21] + node _T_1129 = shr(_T_1125, 4) @[Bitwise.scala 102:21] + node _T_1130 = and(_T_1129, _T_1128) @[Bitwise.scala 102:31] + node _T_1131 = bits(_T_1125, 27, 0) @[Bitwise.scala 102:46] + node _T_1132 = shl(_T_1131, 4) @[Bitwise.scala 102:65] + node _T_1133 = not(_T_1128) @[Bitwise.scala 102:77] + node _T_1134 = and(_T_1132, _T_1133) @[Bitwise.scala 102:75] + node _T_1135 = or(_T_1130, _T_1134) @[Bitwise.scala 102:39] + node _T_1136 = bits(_T_1128, 29, 0) @[Bitwise.scala 101:28] + node _T_1137 = shl(_T_1136, 2) @[Bitwise.scala 101:47] + node _T_1138 = xor(_T_1128, _T_1137) @[Bitwise.scala 101:21] + node _T_1139 = shr(_T_1135, 2) @[Bitwise.scala 102:21] + node _T_1140 = and(_T_1139, _T_1138) @[Bitwise.scala 102:31] + node _T_1141 = bits(_T_1135, 29, 0) @[Bitwise.scala 102:46] + node _T_1142 = shl(_T_1141, 2) @[Bitwise.scala 102:65] + node _T_1143 = not(_T_1138) @[Bitwise.scala 102:77] + node _T_1144 = and(_T_1142, _T_1143) @[Bitwise.scala 102:75] + node _T_1145 = or(_T_1140, _T_1144) @[Bitwise.scala 102:39] + node _T_1146 = bits(_T_1138, 30, 0) @[Bitwise.scala 101:28] + node _T_1147 = shl(_T_1146, 1) @[Bitwise.scala 101:47] + node _T_1148 = xor(_T_1138, _T_1147) @[Bitwise.scala 101:21] + node _T_1149 = shr(_T_1145, 1) @[Bitwise.scala 102:21] + node _T_1150 = and(_T_1149, _T_1148) @[Bitwise.scala 102:31] + node _T_1151 = bits(_T_1145, 30, 0) @[Bitwise.scala 102:46] + node _T_1152 = shl(_T_1151, 1) @[Bitwise.scala 102:65] + node _T_1153 = not(_T_1148) @[Bitwise.scala 102:77] + node _T_1154 = and(_T_1152, _T_1153) @[Bitwise.scala 102:75] + node _T_1155 = or(_T_1150, _T_1154) @[Bitwise.scala 102:39] + node _T_1156 = bits(_T_1103, 49, 32) @[Bitwise.scala 108:44] + node _T_1157 = bits(_T_1156, 15, 0) @[Bitwise.scala 108:18] + node _T_1160 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_1161 = xor(UInt<16>("h0ffff"), _T_1160) @[Bitwise.scala 101:21] + node _T_1162 = shr(_T_1157, 8) @[Bitwise.scala 102:21] + node _T_1163 = and(_T_1162, _T_1161) @[Bitwise.scala 102:31] + node _T_1164 = bits(_T_1157, 7, 0) @[Bitwise.scala 102:46] + node _T_1165 = shl(_T_1164, 8) @[Bitwise.scala 102:65] + node _T_1166 = not(_T_1161) @[Bitwise.scala 102:77] + node _T_1167 = and(_T_1165, _T_1166) @[Bitwise.scala 102:75] + node _T_1168 = or(_T_1163, _T_1167) @[Bitwise.scala 102:39] + node _T_1169 = bits(_T_1161, 11, 0) @[Bitwise.scala 101:28] + node _T_1170 = shl(_T_1169, 4) @[Bitwise.scala 101:47] + node _T_1171 = xor(_T_1161, _T_1170) @[Bitwise.scala 101:21] + node _T_1172 = shr(_T_1168, 4) @[Bitwise.scala 102:21] + node _T_1173 = and(_T_1172, _T_1171) @[Bitwise.scala 102:31] + node _T_1174 = bits(_T_1168, 11, 0) @[Bitwise.scala 102:46] + node _T_1175 = shl(_T_1174, 4) @[Bitwise.scala 102:65] + node _T_1176 = not(_T_1171) @[Bitwise.scala 102:77] + node _T_1177 = and(_T_1175, _T_1176) @[Bitwise.scala 102:75] + node _T_1178 = or(_T_1173, _T_1177) @[Bitwise.scala 102:39] + node _T_1179 = bits(_T_1171, 13, 0) @[Bitwise.scala 101:28] + node _T_1180 = shl(_T_1179, 2) @[Bitwise.scala 101:47] + node _T_1181 = xor(_T_1171, _T_1180) @[Bitwise.scala 101:21] + node _T_1182 = shr(_T_1178, 2) @[Bitwise.scala 102:21] + node _T_1183 = and(_T_1182, _T_1181) @[Bitwise.scala 102:31] + node _T_1184 = bits(_T_1178, 13, 0) @[Bitwise.scala 102:46] + node _T_1185 = shl(_T_1184, 2) @[Bitwise.scala 102:65] + node _T_1186 = not(_T_1181) @[Bitwise.scala 102:77] + node _T_1187 = and(_T_1185, _T_1186) @[Bitwise.scala 102:75] + node _T_1188 = or(_T_1183, _T_1187) @[Bitwise.scala 102:39] + node _T_1189 = bits(_T_1181, 14, 0) @[Bitwise.scala 101:28] + node _T_1190 = shl(_T_1189, 1) @[Bitwise.scala 101:47] + node _T_1191 = xor(_T_1181, _T_1190) @[Bitwise.scala 101:21] + node _T_1192 = shr(_T_1188, 1) @[Bitwise.scala 102:21] + node _T_1193 = and(_T_1192, _T_1191) @[Bitwise.scala 102:31] + node _T_1194 = bits(_T_1188, 14, 0) @[Bitwise.scala 102:46] + node _T_1195 = shl(_T_1194, 1) @[Bitwise.scala 102:65] + node _T_1196 = not(_T_1191) @[Bitwise.scala 102:77] + node _T_1197 = and(_T_1195, _T_1196) @[Bitwise.scala 102:75] + node _T_1198 = or(_T_1193, _T_1197) @[Bitwise.scala 102:39] + node _T_1199 = bits(_T_1156, 17, 16) @[Bitwise.scala 108:44] + node _T_1200 = bits(_T_1199, 0, 0) @[Bitwise.scala 108:18] + node _T_1201 = bits(_T_1199, 1, 1) @[Bitwise.scala 108:44] + node _T_1202 = cat(_T_1200, _T_1201) @[Cat.scala 30:58] + node _T_1203 = cat(_T_1198, _T_1202) @[Cat.scala 30:58] + node _T_1204 = cat(_T_1155, _T_1203) @[Cat.scala 30:58] + node _T_1205 = not(_T_1204) @[primitives.scala 65:36] + node _T_1206 = mux(_T_1098, UInt<1>("h00"), _T_1205) @[primitives.scala 65:21] + node _T_1207 = not(_T_1206) @[primitives.scala 65:17] + node _T_1208 = not(_T_1207) @[primitives.scala 65:36] + node _T_1209 = mux(_T_1095, UInt<1>("h00"), _T_1208) @[primitives.scala 65:21] + node _T_1210 = not(_T_1209) @[primitives.scala 65:17] + node _T_1211 = not(_T_1210) @[primitives.scala 65:36] + node _T_1212 = mux(_T_1092, UInt<1>("h00"), _T_1211) @[primitives.scala 65:21] + node _T_1213 = not(_T_1212) @[primitives.scala 65:17] + node _T_1214 = not(_T_1213) @[primitives.scala 65:36] + node _T_1215 = mux(_T_1089, UInt<1>("h00"), _T_1214) @[primitives.scala 65:21] + node _T_1216 = not(_T_1215) @[primitives.scala 65:17] + node _T_1218 = cat(_T_1216, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_1219 = bits(_T_1088, 9, 9) @[primitives.scala 56:25] + node _T_1220 = bits(_T_1088, 8, 0) @[primitives.scala 57:26] + node _T_1221 = bits(_T_1220, 8, 8) @[primitives.scala 56:25] + node _T_1222 = bits(_T_1220, 7, 0) @[primitives.scala 57:26] + node _T_1223 = bits(_T_1222, 7, 7) @[primitives.scala 56:25] + node _T_1224 = bits(_T_1222, 6, 0) @[primitives.scala 57:26] + node _T_1225 = bits(_T_1224, 6, 6) @[primitives.scala 56:25] + node _T_1226 = bits(_T_1224, 5, 0) @[primitives.scala 57:26] + node _T_1228 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_1226) @[primitives.scala 68:52] + node _T_1229 = bits(_T_1228, 2, 0) @[primitives.scala 69:26] + node _T_1230 = bits(_T_1229, 1, 0) @[Bitwise.scala 108:18] + node _T_1231 = bits(_T_1230, 0, 0) @[Bitwise.scala 108:18] + node _T_1232 = bits(_T_1230, 1, 1) @[Bitwise.scala 108:44] + node _T_1233 = cat(_T_1231, _T_1232) @[Cat.scala 30:58] + node _T_1234 = bits(_T_1229, 2, 2) @[Bitwise.scala 108:44] + node _T_1235 = cat(_T_1233, _T_1234) @[Cat.scala 30:58] + node _T_1237 = mux(_T_1225, _T_1235, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1239 = mux(_T_1223, _T_1237, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1241 = mux(_T_1221, _T_1239, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1243 = mux(_T_1219, _T_1241, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1244 = mux(_T_1087, _T_1218, _T_1243) @[primitives.scala 61:20] + node _T_1246 = mux(_T_1085, _T_1244, UInt<1>("h00")) @[primitives.scala 59:20] + node roundMask_E = mux(_T_1083, _T_1246, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1249 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 30:58] + node _T_1250 = not(_T_1249) @[DivSqrtRecF64_mulAddZ31.scala 763:9] + node _T_1252 = cat(roundMask_E, UInt<1>("h01")) @[Cat.scala 30:58] + node incrPosMask_E = and(_T_1250, _T_1252) @[DivSqrtRecF64_mulAddZ31.scala 763:39] + node _T_1253 = shr(incrPosMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 765:51] + node _T_1254 = and(sigT_E, _T_1253) @[DivSqrtRecF64_mulAddZ31.scala 765:36] + node hiRoundPosBitT_E = neq(_T_1254, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 765:56] + node _T_1256 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 766:55] + node _T_1257 = and(sigT_E, _T_1256) @[DivSqrtRecF64_mulAddZ31.scala 766:42] + node all0sHiRoundExtraT_E = eq(_T_1257, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 766:60] + node _T_1259 = not(sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 767:34] + node _T_1260 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 767:55] + node _T_1261 = and(_T_1259, _T_1260) @[DivSqrtRecF64_mulAddZ31.scala 767:42] + node all1sHiRoundExtraT_E = eq(_T_1261, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 767:60] + node _T_1263 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 769:23] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 769:10] + node _T_1266 = or(_T_1265, hiRoundPosBitT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:27] + node all1sHiRoundT_E = and(_T_1266, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:48] + node _T_1268 = add(UInt<54>("h00"), sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 773:33] + node _T_1269 = tail(_T_1268, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:33] + node _T_1270 = add(_T_1269, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 773:42] + node sigAdjT_E = tail(_T_1270, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:42] + node _T_1272 = not(roundMask_E) @[DivSqrtRecF64_mulAddZ31.scala 774:47] + node _T_1273 = cat(UInt<1>("h01"), _T_1272) @[Cat.scala 30:58] + node sigY0_E = and(sigAdjT_E, _T_1273) @[DivSqrtRecF64_mulAddZ31.scala 774:29] + node _T_1275 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 30:58] + node _T_1276 = or(sigAdjT_E, _T_1275) @[DivSqrtRecF64_mulAddZ31.scala 775:30] + node _T_1278 = add(_T_1276, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 775:62] + node sigY1_E = tail(_T_1278, 1) @[DivSqrtRecF64_mulAddZ31.scala 775:62] + node _T_1280 = eq(isNegRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:24] + node _T_1282 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:41] + node _T_1283 = and(_T_1280, _T_1282) @[DivSqrtRecF64_mulAddZ31.scala 783:38] + node trueLtX_E1 = mux(sqrtOp_PC, _T_1283, isNegRemT_E) @[DivSqrtRecF64_mulAddZ31.scala 783:12] + node _T_1284 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 793:25] + node _T_1286 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 793:32] + node _T_1287 = and(_T_1284, _T_1286) @[DivSqrtRecF64_mulAddZ31.scala 793:29] + node _T_1288 = and(_T_1287, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:45] + node _T_1289 = and(_T_1288, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:69] + node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, _T_1289) @[DivSqrtRecF64_mulAddZ31.scala 792:26] + node _T_1291 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:28] + node _T_1293 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:44] + node _T_1294 = or(_T_1291, _T_1293) @[DivSqrtRecF64_mulAddZ31.scala 795:41] + node _T_1296 = eq(all1sHiRoundExtraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:58] + node anyRoundExtra_E1 = or(_T_1294, _T_1296) @[DivSqrtRecF64_mulAddZ31.scala 795:55] + node _T_1297 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) @[DivSqrtRecF64_mulAddZ31.scala 797:39] + node _T_1299 = eq(anyRoundExtra_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 798:17] + node _T_1300 = and(_T_1297, _T_1299) @[DivSqrtRecF64_mulAddZ31.scala 797:59] + node roundEvenMask_E1 = mux(_T_1300, incrPosMask_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 797:12] + node _T_1302 = and(roundMagDown_PC, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:30] + node _T_1304 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 804:45] + node _T_1305 = and(_T_1302, _T_1304) @[DivSqrtRecF64_mulAddZ31.scala 804:42] + node _T_1306 = and(_T_1305, all1sHiRoundT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:58] + node _T_1308 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:32] + node _T_1309 = and(extraT_E, _T_1308) @[DivSqrtRecF64_mulAddZ31.scala 806:29] + node _T_1311 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:48] + node _T_1312 = and(_T_1309, _T_1311) @[DivSqrtRecF64_mulAddZ31.scala 806:45] + node _T_1314 = eq(all1sHiRoundT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 807:23] + node _T_1315 = or(_T_1312, _T_1314) @[DivSqrtRecF64_mulAddZ31.scala 806:62] + node _T_1316 = and(roundMagUp_PC, _T_1315) @[DivSqrtRecF64_mulAddZ31.scala 805:28] + node _T_1317 = or(_T_1306, _T_1316) @[DivSqrtRecF64_mulAddZ31.scala 804:78] + node _T_1319 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:37] + node _T_1320 = or(extraT_E, _T_1319) @[DivSqrtRecF64_mulAddZ31.scala 810:34] + node _T_1321 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 810:67] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:54] + node _T_1324 = and(_T_1320, _T_1323) @[DivSqrtRecF64_mulAddZ31.scala 810:51] + node _T_1325 = or(hiRoundPosBitT_E, _T_1324) @[DivSqrtRecF64_mulAddZ31.scala 809:36] + node _T_1327 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 811:36] + node _T_1328 = and(extraT_E, _T_1327) @[DivSqrtRecF64_mulAddZ31.scala 811:33] + node _T_1329 = and(_T_1328, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 811:49] + node _T_1330 = or(_T_1325, _T_1329) @[DivSqrtRecF64_mulAddZ31.scala 810:72] + node _T_1331 = and(roundingMode_near_even_PC, _T_1330) @[DivSqrtRecF64_mulAddZ31.scala 808:40] + node _T_1332 = or(_T_1317, _T_1331) @[DivSqrtRecF64_mulAddZ31.scala 807:43] + node _T_1333 = mux(_T_1332, sigY1_E, sigY0_E) @[DivSqrtRecF64_mulAddZ31.scala 804:12] + node _T_1334 = not(roundEvenMask_E1) @[DivSqrtRecF64_mulAddZ31.scala 814:13] + node sigY_E1 = and(_T_1333, _T_1334) @[DivSqrtRecF64_mulAddZ31.scala 814:11] + node fractY_E1 = bits(sigY_E1, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 815:28] + node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) @[DivSqrtRecF64_mulAddZ31.scala 816:40] + node _T_1335 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 818:22] + node _T_1337 = eq(_T_1335, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:13] + node _T_1339 = mux(_T_1337, sExpX_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:12] + node _T_1340 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 819:20] + node _T_1342 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:28] + node _T_1343 = and(_T_1340, _T_1342) @[DivSqrtRecF64_mulAddZ31.scala 819:25] + node _T_1344 = and(_T_1343, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 819:40] + node _T_1346 = mux(_T_1344, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:12] + node _T_1347 = or(_T_1339, _T_1346) @[DivSqrtRecF64_mulAddZ31.scala 818:73] + node _T_1348 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 820:20] + node _T_1350 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:28] + node _T_1351 = and(_T_1348, _T_1350) @[DivSqrtRecF64_mulAddZ31.scala 820:25] + node _T_1353 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:43] + node _T_1354 = and(_T_1351, _T_1353) @[DivSqrtRecF64_mulAddZ31.scala 820:40] + node _T_1356 = mux(_T_1354, expP2_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:12] + node _T_1357 = or(_T_1347, _T_1356) @[DivSqrtRecF64_mulAddZ31.scala 819:73] + node _T_1358 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 821:20] + node _T_1359 = and(_T_1358, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 821:25] + node _T_1360 = shr(expP2_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:22] + node _T_1362 = add(_T_1360, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 822:27] + node _T_1363 = tail(_T_1362, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:27] + node _T_1365 = mux(_T_1359, _T_1363, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 821:12] + node sExpY_E1 = or(_T_1357, _T_1365) @[DivSqrtRecF64_mulAddZ31.scala 820:73] + node expY_E1 = bits(sExpY_E1, 11, 0) @[DivSqrtRecF64_mulAddZ31.scala 825:27] + node _T_1366 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 827:34] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 827:24] + node _T_1370 = bits(sExpY_E1, 12, 10) @[DivSqrtRecF64_mulAddZ31.scala 827:70] + node _T_1371 = leq(UInt<3>("h03"), _T_1370) @[DivSqrtRecF64_mulAddZ31.scala 827:59] + node overflowY_E1 = and(_T_1368, _T_1371) @[DivSqrtRecF64_mulAddZ31.scala 827:39] + node _T_1372 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 830:17] + node _T_1373 = bits(sExpY_E1, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 830:34] + node _T_1375 = lt(_T_1373, UInt<13>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 830:42] + node totalUnderflowY_E1 = or(_T_1372, _T_1375) @[DivSqrtRecF64_mulAddZ31.scala 830:22] + node _T_1377 = leq(posExpX_E, UInt<13>("h0401")) @[DivSqrtRecF64_mulAddZ31.scala 833:25] + node _T_1378 = and(_T_1377, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 833:56] + node underflowY_E1 = or(totalUnderflowY_E1, _T_1378) @[DivSqrtRecF64_mulAddZ31.scala 832:28] + node _T_1380 = eq(isNaNB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:13] + node _T_1382 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:28] + node _T_1383 = and(_T_1380, _T_1382) @[DivSqrtRecF64_mulAddZ31.scala 839:25] + node _T_1384 = and(_T_1383, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 839:41] + node _T_1385 = and(isZeroA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:25] + node _T_1386 = and(isInfA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:54] + node _T_1387 = or(_T_1385, _T_1386) @[DivSqrtRecF64_mulAddZ31.scala 840:40] + node notSigNaN_invalid_PC = mux(sqrtOp_PC, _T_1384, _T_1387) @[DivSqrtRecF64_mulAddZ31.scala 838:12] + node _T_1389 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 843:10] + node _T_1390 = and(_T_1389, isSigNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:22] + node _T_1391 = or(_T_1390, isSigNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:39] + node invalid_PC = or(_T_1391, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:55] + node _T_1393 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:9] + node _T_1395 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:24] + node _T_1396 = and(_T_1393, _T_1395) @[DivSqrtRecF64_mulAddZ31.scala 845:21] + node _T_1398 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:43] + node _T_1399 = and(_T_1396, _T_1398) @[DivSqrtRecF64_mulAddZ31.scala 845:40] + node infinity_PC = and(_T_1399, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 845:56] + node overflow_E1 = and(normalCase_PC, overflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 847:37] + node underflow_E1 = and(normalCase_PC, underflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 848:38] + node _T_1400 = or(overflow_E1, underflow_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:21] + node _T_1401 = and(normalCase_PC, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:55] + node inexact_E1 = or(_T_1400, _T_1401) @[DivSqrtRecF64_mulAddZ31.scala 852:37] + node _T_1402 = or(isZeroA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 857:24] + node _T_1404 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 857:63] + node _T_1405 = and(totalUnderflowY_E1, _T_1404) @[DivSqrtRecF64_mulAddZ31.scala 857:60] + node _T_1406 = or(_T_1402, _T_1405) @[DivSqrtRecF64_mulAddZ31.scala 857:37] + node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, _T_1406) @[DivSqrtRecF64_mulAddZ31.scala 855:12] + node _T_1407 = and(normalCase_PC, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 860:23] + node pegMinFiniteMagOut_E1 = and(_T_1407, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 860:45] + node _T_1409 = eq(overflowY_roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 861:48] + node pegMaxFiniteMagOut_E1 = and(overflow_E1, _T_1409) @[DivSqrtRecF64_mulAddZ31.scala 861:45] + node _T_1410 = or(isInfA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:23] + node _T_1411 = and(overflow_E1, overflowY_roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:53] + node _T_1412 = or(_T_1410, _T_1411) @[DivSqrtRecF64_mulAddZ31.scala 865:37] + node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, _T_1412) @[DivSqrtRecF64_mulAddZ31.scala 863:12] + node _T_1414 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 868:10] + node _T_1415 = and(_T_1414, isNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:22] + node _T_1416 = or(_T_1415, isNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:36] + node isNaNOut_PC = or(_T_1416, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:49] + node _T_1418 = eq(isNaNOut_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 871:9] + node _T_1419 = and(isZeroB_PC, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:52] + node _T_1420 = mux(sqrtOp_PC, _T_1419, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:29] + node signOut_PC = and(_T_1418, _T_1420) @[DivSqrtRecF64_mulAddZ31.scala 871:23] + node _T_1422 = not(UInt<12>("h01ff")) @[DivSqrtRecF64_mulAddZ31.scala 875:19] + node _T_1424 = mux(notSpecial_isZeroOut_E1, _T_1422, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 874:18] + node _T_1425 = not(_T_1424) @[DivSqrtRecF64_mulAddZ31.scala 874:14] + node _T_1426 = and(expY_E1, _T_1425) @[DivSqrtRecF64_mulAddZ31.scala 873:18] + node _T_1428 = not(UInt<12>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 879:19] + node _T_1430 = mux(pegMinFiniteMagOut_E1, _T_1428, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 878:18] + node _T_1431 = not(_T_1430) @[DivSqrtRecF64_mulAddZ31.scala 878:14] + node _T_1432 = and(_T_1426, _T_1431) @[DivSqrtRecF64_mulAddZ31.scala 877:16] + node _T_1434 = not(UInt<12>("h0bff")) @[DivSqrtRecF64_mulAddZ31.scala 883:19] + node _T_1436 = mux(pegMaxFiniteMagOut_E1, _T_1434, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 882:18] + node _T_1437 = not(_T_1436) @[DivSqrtRecF64_mulAddZ31.scala 882:14] + node _T_1438 = and(_T_1432, _T_1437) @[DivSqrtRecF64_mulAddZ31.scala 881:16] + node _T_1440 = not(UInt<12>("h0dff")) @[DivSqrtRecF64_mulAddZ31.scala 887:19] + node _T_1442 = mux(notNaN_isInfOut_E1, _T_1440, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 886:18] + node _T_1443 = not(_T_1442) @[DivSqrtRecF64_mulAddZ31.scala 886:14] + node _T_1444 = and(_T_1438, _T_1443) @[DivSqrtRecF64_mulAddZ31.scala 885:16] + node _T_1447 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 890:16] + node _T_1448 = or(_T_1444, _T_1447) @[DivSqrtRecF64_mulAddZ31.scala 889:17] + node _T_1451 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 891:16] + node _T_1452 = or(_T_1448, _T_1451) @[DivSqrtRecF64_mulAddZ31.scala 890:76] + node _T_1455 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 892:16] + node _T_1456 = or(_T_1452, _T_1455) @[DivSqrtRecF64_mulAddZ31.scala 891:76] + node _T_1459 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 893:16] + node expOut_E1 = or(_T_1456, _T_1459) @[DivSqrtRecF64_mulAddZ31.scala 892:76] + node _T_1460 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:37] + node _T_1461 = or(_T_1460, isNaNOut_PC) @[DivSqrtRecF64_mulAddZ31.scala 895:59] + node _T_1463 = shl(UInt<1>("h01"), 51) @[DivSqrtRecF64_mulAddZ31.scala 896:37] + node _T_1465 = mux(isNaNOut_PC, _T_1463, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 896:16] + node _T_1466 = mux(_T_1461, _T_1465, fractY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:12] + node _T_1467 = bits(pegMaxFiniteMagOut_E1, 0, 0) @[Bitwise.scala 71:15] + node _T_1470 = mux(_T_1467, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 71:12] + node fractOut_E1 = or(_T_1466, _T_1470) @[DivSqrtRecF64_mulAddZ31.scala 898:11] + node _T_1471 = cat(signOut_PC, expOut_E1) @[Cat.scala 30:58] + node _T_1472 = cat(_T_1471, fractOut_E1) @[Cat.scala 30:58] + io.out <= _T_1472 @[DivSqrtRecF64_mulAddZ31.scala 900:12] + node _T_1473 = cat(underflow_E1, inexact_E1) @[Cat.scala 30:58] + node _T_1474 = cat(invalid_PC, infinity_PC) @[Cat.scala 30:58] + node _T_1475 = cat(_T_1474, overflow_E1) @[Cat.scala 30:58] + node _T_1476 = cat(_T_1475, _T_1473) @[Cat.scala 30:58] + io.exceptionFlags <= _T_1476 @[DivSqrtRecF64_mulAddZ31.scala 902:23] + + module Mul54 : + input clock : Clock + input reset : UInt<1> + output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} + + io is invalid + io is invalid + reg val_s1 : UInt<1>, clock @[DivSqrtRecF64.scala 96:21] + reg val_s2 : UInt<1>, clock @[DivSqrtRecF64.scala 97:21] + reg reg_a_s1 : UInt<54>, clock @[DivSqrtRecF64.scala 98:23] + reg reg_b_s1 : UInt<54>, clock @[DivSqrtRecF64.scala 99:23] + reg reg_a_s2 : UInt<54>, clock @[DivSqrtRecF64.scala 100:23] + reg reg_b_s2 : UInt<54>, clock @[DivSqrtRecF64.scala 101:23] + reg reg_result_s3 : UInt<105>, clock @[DivSqrtRecF64.scala 102:28] + val_s1 <= io.val_s0 @[DivSqrtRecF64.scala 104:12] + val_s2 <= val_s1 @[DivSqrtRecF64.scala 105:12] + when io.val_s0 : @[DivSqrtRecF64.scala 107:22] + when io.latch_a_s0 : @[DivSqrtRecF64.scala 108:30] + reg_a_s1 <= io.a_s0 @[DivSqrtRecF64.scala 109:22] + skip @[DivSqrtRecF64.scala 108:30] + when io.latch_b_s0 : @[DivSqrtRecF64.scala 111:30] + reg_b_s1 <= io.b_s0 @[DivSqrtRecF64.scala 112:22] + skip @[DivSqrtRecF64.scala 111:30] + skip @[DivSqrtRecF64.scala 107:22] + when val_s1 : @[DivSqrtRecF64.scala 116:19] + reg_a_s2 <= reg_a_s1 @[DivSqrtRecF64.scala 117:18] + reg_b_s2 <= reg_b_s1 @[DivSqrtRecF64.scala 118:18] + skip @[DivSqrtRecF64.scala 116:19] + when val_s2 : @[DivSqrtRecF64.scala 121:19] + node _T_23 = mul(reg_a_s2, reg_b_s2) @[DivSqrtRecF64.scala 122:36] + node _T_24 = bits(_T_23, 104, 0) @[DivSqrtRecF64.scala 122:47] + node _T_25 = add(_T_24, io.c_s2) @[DivSqrtRecF64.scala 122:55] + node _T_26 = tail(_T_25, 1) @[DivSqrtRecF64.scala 122:55] + reg_result_s3 <= _T_26 @[DivSqrtRecF64.scala 122:23] + skip @[DivSqrtRecF64.scala 121:19] + io.result_s3 <= reg_result_s3 @[DivSqrtRecF64.scala 125:18] + + module DivSqrtRecF64 : + input clock : Clock + input reset : UInt<1> + output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst ds of DivSqrtRecF64_mulAddZ31 @[DivSqrtRecF64.scala 59:20] + ds.io is invalid + ds.clock <= clock + ds.reset <= reset + io.inReady_div <= ds.io.inReady_div @[DivSqrtRecF64.scala 61:20] + io.inReady_sqrt <= ds.io.inReady_sqrt @[DivSqrtRecF64.scala 62:21] + ds.io.inValid <= io.inValid @[DivSqrtRecF64.scala 63:19] + ds.io.sqrtOp <= io.sqrtOp @[DivSqrtRecF64.scala 64:18] + ds.io.a <= io.a @[DivSqrtRecF64.scala 65:13] + ds.io.b <= io.b @[DivSqrtRecF64.scala 66:13] + ds.io.roundingMode <= io.roundingMode @[DivSqrtRecF64.scala 67:24] + io.outValid_div <= ds.io.outValid_div @[DivSqrtRecF64.scala 68:21] + io.outValid_sqrt <= ds.io.outValid_sqrt @[DivSqrtRecF64.scala 69:22] + io.out <= ds.io.out @[DivSqrtRecF64.scala 70:12] + io.exceptionFlags <= ds.io.exceptionFlags @[DivSqrtRecF64.scala 71:23] + inst mul of Mul54 @[DivSqrtRecF64.scala 73:21] + mul.io is invalid + mul.clock <= clock + mul.reset <= reset + node _T_24 = bits(ds.io.usingMulAdd, 0, 0) @[DivSqrtRecF64.scala 75:39] + mul.io.val_s0 <= _T_24 @[DivSqrtRecF64.scala 75:19] + mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 @[DivSqrtRecF64.scala 76:23] + mul.io.a_s0 <= ds.io.mulAddA_0 @[DivSqrtRecF64.scala 77:17] + mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 @[DivSqrtRecF64.scala 78:23] + mul.io.b_s0 <= ds.io.mulAddB_0 @[DivSqrtRecF64.scala 79:17] + mul.io.c_s2 <= ds.io.mulAddC_2 @[DivSqrtRecF64.scala 80:17] + ds.io.mulAddResult_3 <= mul.io.result_s3 @[DivSqrtRecF64.scala 81:26] + + module RoundRawFNToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) @[RoundRawFNToRecFN.scala 88:54] + node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) @[RoundRawFNToRecFN.scala 89:54] + node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @[RoundRawFNToRecFN.scala 90:54] + node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) @[RoundRawFNToRecFN.scala 91:54] + node _T_26 = and(roundingMode_min, io.in.sign) @[RoundRawFNToRecFN.scala 94:27] + node _T_28 = eq(io.in.sign, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 94:66] + node _T_29 = and(roundingMode_max, _T_28) @[RoundRawFNToRecFN.scala 94:63] + node roundMagUp = or(_T_26, _T_29) @[RoundRawFNToRecFN.scala 94:42] + node doShiftSigDown1 = bits(io.in.sig, 26, 26) @[RoundRawFNToRecFN.scala 98:36] + node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h00"))) @[RoundRawFNToRecFN.scala 99:32] + node _T_31 = bits(isNegExp, 0, 0) @[Bitwise.scala 71:15] + node _T_34 = mux(_T_31, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_35 = bits(io.in.sExp, 8, 0) @[RoundRawFNToRecFN.scala 103:31] + node _T_36 = not(_T_35) @[primitives.scala 50:21] + node _T_37 = bits(_T_36, 8, 8) @[primitives.scala 56:25] + node _T_38 = bits(_T_36, 7, 0) @[primitives.scala 57:26] + node _T_39 = bits(_T_38, 7, 7) @[primitives.scala 56:25] + node _T_40 = bits(_T_38, 6, 0) @[primitives.scala 57:26] + node _T_41 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_42 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_45 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_42) @[primitives.scala 68:52] + node _T_46 = bits(_T_45, 63, 42) @[primitives.scala 69:26] + node _T_47 = bits(_T_46, 15, 0) @[Bitwise.scala 108:18] + node _T_50 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_51 = xor(UInt<16>("h0ffff"), _T_50) @[Bitwise.scala 101:21] + node _T_52 = shr(_T_47, 8) @[Bitwise.scala 102:21] + node _T_53 = and(_T_52, _T_51) @[Bitwise.scala 102:31] + node _T_54 = bits(_T_47, 7, 0) @[Bitwise.scala 102:46] + node _T_55 = shl(_T_54, 8) @[Bitwise.scala 102:65] + node _T_56 = not(_T_51) @[Bitwise.scala 102:77] + node _T_57 = and(_T_55, _T_56) @[Bitwise.scala 102:75] + node _T_58 = or(_T_53, _T_57) @[Bitwise.scala 102:39] + node _T_59 = bits(_T_51, 11, 0) @[Bitwise.scala 101:28] + node _T_60 = shl(_T_59, 4) @[Bitwise.scala 101:47] + node _T_61 = xor(_T_51, _T_60) @[Bitwise.scala 101:21] + node _T_62 = shr(_T_58, 4) @[Bitwise.scala 102:21] + node _T_63 = and(_T_62, _T_61) @[Bitwise.scala 102:31] + node _T_64 = bits(_T_58, 11, 0) @[Bitwise.scala 102:46] + node _T_65 = shl(_T_64, 4) @[Bitwise.scala 102:65] + node _T_66 = not(_T_61) @[Bitwise.scala 102:77] + node _T_67 = and(_T_65, _T_66) @[Bitwise.scala 102:75] + node _T_68 = or(_T_63, _T_67) @[Bitwise.scala 102:39] + node _T_69 = bits(_T_61, 13, 0) @[Bitwise.scala 101:28] + node _T_70 = shl(_T_69, 2) @[Bitwise.scala 101:47] + node _T_71 = xor(_T_61, _T_70) @[Bitwise.scala 101:21] + node _T_72 = shr(_T_68, 2) @[Bitwise.scala 102:21] + node _T_73 = and(_T_72, _T_71) @[Bitwise.scala 102:31] + node _T_74 = bits(_T_68, 13, 0) @[Bitwise.scala 102:46] + node _T_75 = shl(_T_74, 2) @[Bitwise.scala 102:65] + node _T_76 = not(_T_71) @[Bitwise.scala 102:77] + node _T_77 = and(_T_75, _T_76) @[Bitwise.scala 102:75] + node _T_78 = or(_T_73, _T_77) @[Bitwise.scala 102:39] + node _T_79 = bits(_T_71, 14, 0) @[Bitwise.scala 101:28] + node _T_80 = shl(_T_79, 1) @[Bitwise.scala 101:47] + node _T_81 = xor(_T_71, _T_80) @[Bitwise.scala 101:21] + node _T_82 = shr(_T_78, 1) @[Bitwise.scala 102:21] + node _T_83 = and(_T_82, _T_81) @[Bitwise.scala 102:31] + node _T_84 = bits(_T_78, 14, 0) @[Bitwise.scala 102:46] + node _T_85 = shl(_T_84, 1) @[Bitwise.scala 102:65] + node _T_86 = not(_T_81) @[Bitwise.scala 102:77] + node _T_87 = and(_T_85, _T_86) @[Bitwise.scala 102:75] + node _T_88 = or(_T_83, _T_87) @[Bitwise.scala 102:39] + node _T_89 = bits(_T_46, 21, 16) @[Bitwise.scala 108:44] + node _T_90 = bits(_T_89, 3, 0) @[Bitwise.scala 108:18] + node _T_91 = bits(_T_90, 1, 0) @[Bitwise.scala 108:18] + node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 108:18] + node _T_93 = bits(_T_91, 1, 1) @[Bitwise.scala 108:44] + node _T_94 = cat(_T_92, _T_93) @[Cat.scala 30:58] + node _T_95 = bits(_T_90, 3, 2) @[Bitwise.scala 108:44] + node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 108:18] + node _T_97 = bits(_T_95, 1, 1) @[Bitwise.scala 108:44] + node _T_98 = cat(_T_96, _T_97) @[Cat.scala 30:58] + node _T_99 = cat(_T_94, _T_98) @[Cat.scala 30:58] + node _T_100 = bits(_T_89, 5, 4) @[Bitwise.scala 108:44] + node _T_101 = bits(_T_100, 0, 0) @[Bitwise.scala 108:18] + node _T_102 = bits(_T_100, 1, 1) @[Bitwise.scala 108:44] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 30:58] + node _T_104 = cat(_T_99, _T_103) @[Cat.scala 30:58] + node _T_105 = cat(_T_88, _T_104) @[Cat.scala 30:58] + node _T_106 = not(_T_105) @[primitives.scala 65:36] + node _T_107 = mux(_T_41, UInt<1>("h00"), _T_106) @[primitives.scala 65:21] + node _T_108 = not(_T_107) @[primitives.scala 65:17] + node _T_110 = cat(_T_108, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_111 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_112 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_114 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_112) @[primitives.scala 68:52] + node _T_115 = bits(_T_114, 2, 0) @[primitives.scala 69:26] + node _T_116 = bits(_T_115, 1, 0) @[Bitwise.scala 108:18] + node _T_117 = bits(_T_116, 0, 0) @[Bitwise.scala 108:18] + node _T_118 = bits(_T_116, 1, 1) @[Bitwise.scala 108:44] + node _T_119 = cat(_T_117, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_115, 2, 2) @[Bitwise.scala 108:44] + node _T_121 = cat(_T_119, _T_120) @[Cat.scala 30:58] + node _T_123 = mux(_T_111, _T_121, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_124 = mux(_T_39, _T_110, _T_123) @[primitives.scala 61:20] + node _T_126 = mux(_T_37, _T_124, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_127 = or(_T_34, _T_126) @[RoundRawFNToRecFN.scala 101:42] + node _T_128 = or(_T_127, doShiftSigDown1) @[RoundRawFNToRecFN.scala 106:19] + node roundMask = cat(_T_128, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_130 = cat(isNegExp, roundMask) @[Cat.scala 30:58] + node shiftedRoundMask = shr(_T_130, 1) @[RoundRawFNToRecFN.scala 109:52] + node _T_131 = not(shiftedRoundMask) @[RoundRawFNToRecFN.scala 110:24] + node roundPosMask = and(_T_131, roundMask) @[RoundRawFNToRecFN.scala 110:42] + node _T_132 = and(io.in.sig, roundPosMask) @[RoundRawFNToRecFN.scala 111:34] + node roundPosBit = neq(_T_132, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 111:50] + node _T_134 = and(io.in.sig, shiftedRoundMask) @[RoundRawFNToRecFN.scala 112:36] + node anyRoundExtra = neq(_T_134, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 112:56] + node anyRound = or(roundPosBit, anyRoundExtra) @[RoundRawFNToRecFN.scala 113:32] + node _T_136 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 116:40] + node _T_137 = and(roundMagUp, anyRound) @[RoundRawFNToRecFN.scala 117:29] + node _T_138 = or(_T_136, _T_137) @[RoundRawFNToRecFN.scala 116:56] + node _T_139 = or(io.in.sig, roundMask) @[RoundRawFNToRecFN.scala 118:26] + node _T_140 = shr(_T_139, 2) @[RoundRawFNToRecFN.scala 118:38] + node _T_142 = add(_T_140, UInt<1>("h01")) @[RoundRawFNToRecFN.scala 118:43] + node _T_143 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 119:48] + node _T_145 = eq(anyRoundExtra, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 120:26] + node _T_146 = and(_T_143, _T_145) @[RoundRawFNToRecFN.scala 119:63] + node _T_147 = shr(roundMask, 1) @[RoundRawFNToRecFN.scala 121:31] + node _T_149 = mux(_T_146, _T_147, UInt<26>("h00")) @[RoundRawFNToRecFN.scala 119:21] + node _T_150 = not(_T_149) @[RoundRawFNToRecFN.scala 119:17] + node _T_151 = and(_T_142, _T_150) @[RoundRawFNToRecFN.scala 118:55] + node _T_152 = not(roundMask) @[RoundRawFNToRecFN.scala 124:26] + node _T_153 = and(io.in.sig, _T_152) @[RoundRawFNToRecFN.scala 124:24] + node _T_154 = shr(_T_153, 2) @[RoundRawFNToRecFN.scala 124:37] + node roundedSig = mux(_T_138, _T_151, _T_154) @[RoundRawFNToRecFN.scala 116:12] + node _T_155 = shr(roundedSig, 24) @[RoundRawFNToRecFN.scala 127:48] + node _T_156 = cvt(_T_155) @[RoundRawFNToRecFN.scala 127:60] + node sRoundedExp = add(io.in.sExp, _T_156) @[RoundRawFNToRecFN.scala 127:34] + node common_expOut = bits(sRoundedExp, 8, 0) @[RoundRawFNToRecFN.scala 129:36] + node _T_157 = bits(roundedSig, 23, 1) @[RoundRawFNToRecFN.scala 132:23] + node _T_158 = bits(roundedSig, 22, 0) @[RoundRawFNToRecFN.scala 133:23] + node common_fractOut = mux(doShiftSigDown1, _T_157, _T_158) @[RoundRawFNToRecFN.scala 131:12] + node _T_159 = shr(sRoundedExp, 7) @[RoundRawFNToRecFN.scala 136:39] + node common_overflow = geq(_T_159, asSInt(UInt<3>("h03"))) @[RoundRawFNToRecFN.scala 136:56] + node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) @[RoundRawFNToRecFN.scala 138:46] + node _T_164 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) @[RoundRawFNToRecFN.scala 142:21] + node _T_165 = lt(io.in.sExp, _T_164) @[RoundRawFNToRecFN.scala 141:25] + node common_underflow = and(anyRound, _T_165) @[RoundRawFNToRecFN.scala 140:18] + node isNaNOut = or(io.invalidExc, io.in.isNaN) @[RoundRawFNToRecFN.scala 147:34] + node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[RoundRawFNToRecFN.scala 148:49] + node _T_167 = eq(isNaNOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:22] + node _T_169 = eq(notNaN_isSpecialInfOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:36] + node _T_170 = and(_T_167, _T_169) @[RoundRawFNToRecFN.scala 149:33] + node _T_172 = eq(io.in.isZero, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:64] + node commonCase = and(_T_170, _T_172) @[RoundRawFNToRecFN.scala 149:61] + node overflow = and(commonCase, common_overflow) @[RoundRawFNToRecFN.scala 150:32] + node underflow = and(commonCase, common_underflow) @[RoundRawFNToRecFN.scala 151:32] + node _T_173 = and(commonCase, anyRound) @[RoundRawFNToRecFN.scala 152:43] + node inexact = or(overflow, _T_173) @[RoundRawFNToRecFN.scala 152:28] + node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[RoundRawFNToRecFN.scala 154:57] + node _T_174 = and(commonCase, common_totalUnderflow) @[RoundRawFNToRecFN.scala 155:42] + node pegMinNonzeroMagOut = and(_T_174, roundMagUp) @[RoundRawFNToRecFN.scala 155:67] + node _T_175 = and(commonCase, overflow) @[RoundRawFNToRecFN.scala 156:41] + node _T_177 = eq(overflow_roundMagUp, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 156:56] + node pegMaxFiniteMagOut = and(_T_175, _T_177) @[RoundRawFNToRecFN.scala 156:53] + node _T_178 = and(overflow, overflow_roundMagUp) @[RoundRawFNToRecFN.scala 158:45] + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _T_178) @[RoundRawFNToRecFN.scala 158:32] + node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) @[RoundRawFNToRecFN.scala 160:22] + node _T_180 = or(io.in.isZero, common_totalUnderflow) @[RoundRawFNToRecFN.scala 163:32] + node _T_183 = mux(_T_180, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 163:18] + node _T_184 = not(_T_183) @[RoundRawFNToRecFN.scala 163:14] + node _T_185 = and(common_expOut, _T_184) @[RoundRawFNToRecFN.scala 162:24] + node _T_187 = not(UInt<9>("h06b")) @[RoundRawFNToRecFN.scala 168:19] + node _T_189 = mux(pegMinNonzeroMagOut, _T_187, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 167:18] + node _T_190 = not(_T_189) @[RoundRawFNToRecFN.scala 167:14] + node _T_191 = and(_T_185, _T_190) @[RoundRawFNToRecFN.scala 166:17] + node _T_194 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 171:18] + node _T_195 = not(_T_194) @[RoundRawFNToRecFN.scala 171:14] + node _T_196 = and(_T_191, _T_195) @[RoundRawFNToRecFN.scala 170:17] + node _T_199 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 175:18] + node _T_200 = not(_T_199) @[RoundRawFNToRecFN.scala 175:14] + node _T_201 = and(_T_196, _T_200) @[RoundRawFNToRecFN.scala 174:17] + node _T_204 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 179:16] + node _T_205 = or(_T_201, _T_204) @[RoundRawFNToRecFN.scala 178:18] + node _T_208 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 183:16] + node _T_209 = or(_T_205, _T_208) @[RoundRawFNToRecFN.scala 182:15] + node _T_212 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 187:16] + node _T_213 = or(_T_209, _T_212) @[RoundRawFNToRecFN.scala 186:15] + node _T_216 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 188:16] + node expOut = or(_T_213, _T_216) @[RoundRawFNToRecFN.scala 187:71] + node _T_217 = or(common_totalUnderflow, isNaNOut) @[RoundRawFNToRecFN.scala 190:35] + node _T_219 = shl(UInt<1>("h01"), 22) @[RoundRawFNToRecFN.scala 191:34] + node _T_221 = mux(isNaNOut, _T_219, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 191:16] + node _T_222 = mux(_T_217, _T_221, common_fractOut) @[RoundRawFNToRecFN.scala 190:12] + node _T_223 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_226 = mux(_T_223, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_222, _T_226) @[RoundRawFNToRecFN.scala 193:11] + node _T_227 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_228 = cat(_T_227, fractOut) @[Cat.scala 30:58] + io.out <= _T_228 @[RoundRawFNToRecFN.scala 196:12] + node _T_229 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_230 = cat(io.invalidExc, io.infiniteExc) @[Cat.scala 30:58] + node _T_231 = cat(_T_230, overflow) @[Cat.scala 30:58] + node _T_232 = cat(_T_231, _T_229) @[Cat.scala 30:58] + io.exceptionFlags <= _T_232 @[RoundRawFNToRecFN.scala 197:23] - module BroadcastAcquireTracker_31 : - input clk : Clock + module RecFNToRecFN_2 : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h06") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<3>("h06") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<3>("h06") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<3>("h06") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<3>("h06") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<3>("h06") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h06") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") - skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") - skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") - skip - skip + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - module BroadcastAcquireTracker_32 : - input clk : Clock + io is invalid + io is invalid + node _T_10 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + node _T_63 = lt(_T_48, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] + node _T_64 = bits(_T_48, 12, 9) @[resizeRawFN.scala 61:33] + node _T_66 = neq(_T_64, UInt<1>("h00")) @[resizeRawFN.scala 61:65] + node _T_71 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_73 = cat(_T_71, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_74 = bits(_T_48, 8, 0) @[resizeRawFN.scala 63:33] + node _T_75 = mux(_T_66, _T_73, _T_74) @[resizeRawFN.scala 61:25] + node _T_76 = cat(_T_63, _T_75) @[Cat.scala 30:58] + node _T_77 = asSInt(_T_76) @[resizeRawFN.scala 65:20] + outRawFloat.sExp <= _T_77 @[resizeRawFN.scala 56:18] + node _T_78 = bits(_T_24.sig, 55, 30) @[resizeRawFN.scala 71:28] + node _T_79 = bits(_T_24.sig, 29, 0) @[resizeRawFN.scala 72:28] + node _T_81 = neq(_T_79, UInt<1>("h00")) @[resizeRawFN.scala 72:56] + node _T_82 = cat(_T_78, _T_81) @[Cat.scala 30:58] + outRawFloat.sig <= _T_82 @[resizeRawFN.scala 67:17] + node _T_83 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] + node _T_85 = eq(_T_83, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_85) @[RoundRawFNToRecFN.scala 61:46] + inst RoundRawFNToRecFN of RoundRawFNToRecFN_1 @[RecFNToRecFN.scala 102:19] + RoundRawFNToRecFN.io is invalid + RoundRawFNToRecFN.clock <= clock + RoundRawFNToRecFN.reset <= reset + RoundRawFNToRecFN.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] + RoundRawFNToRecFN.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] + RoundRawFNToRecFN.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] + RoundRawFNToRecFN.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] + io.out <= RoundRawFNToRecFN.io.out @[RecFNToRecFN.scala 107:16] + io.exceptionFlags <= RoundRawFNToRecFN.io.exceptionFlags @[RecFNToRecFN.scala 108:27] + + module FPU : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk - wire coh : {sharers : UInt<1>} - coh is invalid - coh.sharers <= UInt<1>("h00") - node T_303 = neq(state, UInt<1>("h00")) - node T_304 = and(T_303, xact.is_builtin_type) - wire T_309 : UInt<3>[3] - T_309[0] <= UInt<3>("h04") - T_309[1] <= UInt<3>("h05") - T_309[2] <= UInt<3>("h06") - node T_314 = eq(T_309[0], xact.a_type) - node T_315 = eq(T_309[1], xact.a_type) - node T_316 = eq(T_309[2], xact.a_type) - node T_318 = or(UInt<1>("h00"), T_314) - node T_319 = or(T_318, T_315) - node T_320 = or(T_319, T_316) - node T_321 = and(T_304, T_320) - node T_323 = eq(T_321, UInt<1>("h00")) - node T_325 = eq(reset, UInt<1>("h00")) - when T_325 : - node T_327 = eq(T_323, UInt<1>("h00")) - when T_327 : - node T_329 = eq(reset, UInt<1>("h00")) - when T_329 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_334 = bits(pending_probes, 0, 0) - wire T_336 : UInt<1>[1] - T_336[0] <= T_334 - node T_341 = asUInt(asSInt(UInt<1>("h01"))) - node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_345 = or(T_341, T_344) - node T_346 = not(T_341) - node T_347 = or(T_346, T_344) - node T_348 = not(T_347) - node mask_self = mux(UInt<1>("h00"), T_345, T_348) - node T_350 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_350) - reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_362 : UInt<3>[1] - T_362[0] <= UInt<3>("h03") - node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) - node T_367 = or(UInt<1>("h00"), T_365) - node T_368 = and(T_359, T_367) - node T_369 = and(T_356, T_368) - reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_369 : - node T_373 = eq(T_371, UInt<2>("h03")) - node T_375 = and(UInt<1>("h00"), T_373) - node T_378 = add(T_371, UInt<1>("h01")) - node T_379 = tail(T_378, 1) - node T_380 = mux(T_375, UInt<1>("h00"), T_379) - T_371 <= T_380 - skip - node T_381 = and(T_369, T_373) - node T_382 = mux(T_368, T_371, UInt<1>("h00")) - node iacq_data_done = mux(T_368, T_381, T_356) - node T_384 = and(io.inner.release.ready, io.inner.release.valid) - wire T_388 : UInt<2>[3] - T_388[0] <= UInt<1>("h00") - T_388[1] <= UInt<1>("h01") - T_388[2] <= UInt<2>("h02") - node T_393 = eq(T_388[0], io.inner.release.bits.r_type) - node T_394 = eq(T_388[1], io.inner.release.bits.r_type) - node T_395 = eq(T_388[2], io.inner.release.bits.r_type) - node T_397 = or(UInt<1>("h00"), T_393) - node T_398 = or(T_397, T_394) - node T_399 = or(T_398, T_395) - node T_400 = and(UInt<1>("h01"), T_399) - node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_401 : - node T_405 = eq(T_403, UInt<2>("h03")) - node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = add(T_403, UInt<1>("h01")) - node T_411 = tail(T_410, 1) - node T_412 = mux(T_407, UInt<1>("h00"), T_411) - T_403 <= T_412 - skip - node T_413 = and(T_401, T_405) - node T_414 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_413, T_384) - node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_421 : UInt<3>[1] - T_421[0] <= UInt<3>("h05") - node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) - node T_426 = or(UInt<1>("h00"), T_424) - wire T_428 : UInt<1>[2] - T_428[0] <= UInt<1>("h00") - T_428[1] <= UInt<1>("h01") - node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) - node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) - node T_435 = or(UInt<1>("h00"), T_432) - node T_436 = or(T_435, T_433) - node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) - node T_438 = and(UInt<1>("h01"), T_437) - node T_439 = and(T_417, T_438) - reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_439 : - node T_443 = eq(T_441, UInt<2>("h03")) - node T_445 = and(UInt<1>("h00"), T_443) - node T_448 = add(T_441, UInt<1>("h01")) - node T_449 = tail(T_448, 1) - node T_450 = mux(T_445, UInt<1>("h00"), T_449) - T_441 <= T_450 - skip - node T_451 = and(T_439, T_443) - node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) - node ignt_data_done = mux(T_438, T_451, T_417) - node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_460 : UInt<3>[1] - T_460[0] <= UInt<3>("h03") - node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) - node T_465 = or(UInt<1>("h00"), T_463) - node T_466 = and(T_457, T_465) - node T_467 = and(T_455, T_466) - reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_467 : - node T_471 = eq(T_469, UInt<2>("h03")) - node T_473 = and(UInt<1>("h00"), T_471) - node T_476 = add(T_469, UInt<1>("h01")) - node T_477 = tail(T_476, 1) - node T_478 = mux(T_473, UInt<1>("h00"), T_477) - T_469 <= T_478 - skip - node T_479 = and(T_467, T_471) - node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) - node oacq_data_done = mux(T_466, T_479, T_455) - node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_487 : UInt<3>[1] - T_487[0] <= UInt<3>("h05") - node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) - node T_492 = or(UInt<1>("h00"), T_490) - wire T_494 : UInt<1>[1] - T_494[0] <= UInt<1>("h00") - node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) - node T_499 = or(UInt<1>("h00"), T_497) - node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) - node T_501 = and(UInt<1>("h01"), T_500) - node T_502 = and(T_482, T_501) - reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_502 : - node T_506 = eq(T_504, UInt<2>("h03")) - node T_508 = and(UInt<1>("h00"), T_506) - node T_511 = add(T_504, UInt<1>("h01")) - node T_512 = tail(T_511, 1) - node T_513 = mux(T_508, UInt<1>("h00"), T_512) - T_504 <= T_513 - skip - node T_514 = and(T_502, T_506) - node T_515 = mux(T_501, T_504, UInt<1>("h00")) - node ognt_data_done = mux(T_501, T_514, T_482) - reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_523 : UInt<3>[3] - T_523[0] <= UInt<3>("h02") - T_523[1] <= UInt<3>("h03") - T_523[2] <= UInt<3>("h04") - node T_528 = eq(T_523[0], xact.a_type) - node T_529 = eq(T_523[1], xact.a_type) - node T_530 = eq(T_523[2], xact.a_type) - node T_532 = or(UInt<1>("h00"), T_528) - node T_533 = or(T_532, T_529) - node T_534 = or(T_533, T_530) - node pending_outer_write = and(xact.is_builtin_type, T_534) - wire T_540 : UInt<3>[3] - T_540[0] <= UInt<3>("h02") - T_540[1] <= UInt<3>("h03") - T_540[2] <= UInt<3>("h04") - node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) - node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) - node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) - node T_549 = or(UInt<1>("h00"), T_545) - node T_550 = or(T_549, T_546) - node T_551 = or(T_550, T_547) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) - wire T_556 : UInt<3>[2] - T_556[0] <= UInt<3>("h05") - T_556[1] <= UInt<3>("h04") - node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) - node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) - node T_563 = or(UInt<1>("h00"), T_560) - node T_564 = or(T_563, T_561) - wire T_566 : UInt<1>[2] - T_566[0] <= UInt<1>("h00") - T_566[1] <= UInt<1>("h01") - node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) - node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) - node T_573 = or(UInt<1>("h00"), T_570) - node T_574 = or(T_573, T_571) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) - node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) - node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h01"), T_595) - node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h04"), T_597) - node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h03"), T_599) - node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h03"), T_601) - node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_605 = mux(T_604, UInt<3>("h05"), T_603) - node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_607 = mux(T_606, UInt<3>("h04"), T_605) - node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) - node T_613 = mux(T_608, T_612, UInt<1>("h01")) - node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) - wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_623 is invalid - T_623.client_id <= io.inner.acquire.bits.client_id - T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_623.g_type <= T_614 - T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_623.manager_xact_id <= UInt<3>("h07") - T_623.addr_beat <= UInt<1>("h00") - T_623.data <= UInt<1>("h00") - wire T_634 : UInt<3>[2] - T_634[0] <= UInt<3>("h05") - T_634[1] <= UInt<3>("h04") - node T_638 = eq(T_634[0], T_623.g_type) - node T_639 = eq(T_634[1], T_623.g_type) - node T_641 = or(UInt<1>("h00"), T_638) - node T_642 = or(T_641, T_639) - wire T_644 : UInt<1>[2] - T_644[0] <= UInt<1>("h00") - T_644[1] <= UInt<1>("h01") - node T_648 = eq(T_644[0], T_623.g_type) - node T_649 = eq(T_644[1], T_623.g_type) - node T_651 = or(UInt<1>("h00"), T_648) - node T_652 = or(T_651, T_649) - node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) - wire T_658 : UInt<3>[3] - T_658[0] <= UInt<3>("h02") - T_658[1] <= UInt<3>("h00") - T_658[2] <= UInt<3>("h04") - node T_663 = eq(T_658[0], xact.a_type) - node T_664 = eq(T_658[1], xact.a_type) - node T_665 = eq(T_658[2], xact.a_type) - node T_667 = or(UInt<1>("h00"), T_663) - node T_668 = or(T_667, T_664) - node T_669 = or(T_668, T_665) - node subblock_type = and(xact.is_builtin_type, T_669) - node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_672 = neq(state, UInt<1>("h00")) - node T_673 = and(T_671, T_672) - node T_675 = eq(collect_iacq_data, UInt<1>("h00")) - node T_676 = and(T_673, T_675) - io.has_acquire_conflict <= T_676 - node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_678 = and(T_677, collect_iacq_data) - io.has_acquire_match <= T_678 - node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_682 = and(T_679, T_681) - node T_683 = eq(state, UInt<1>("h01")) - node T_684 = and(T_682, T_683) - io.has_release_match <= T_684 - node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_697 = cat(T_695, T_696) - node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(UInt<3>("h07"), T_699) - node T_702 = cat(T_689, UInt<1>("h01")) - node T_704 = cat(T_689, UInt<1>("h01")) - node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_708 = cat(T_706, T_707) - node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_714 = mux(T_713, T_712, UInt<1>("h00")) - node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_716 = mux(T_715, T_710, T_714) - node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_718 = mux(T_717, T_708, T_716) - node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_720 = mux(T_719, T_704, T_718) - node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_722 = mux(T_721, T_702, T_720) - node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_724 = mux(T_723, T_700, T_722) - node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_726 = mux(T_725, T_697, T_724) - wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe is invalid - oacq_probe.is_builtin_type <= UInt<1>("h01") - oacq_probe.a_type <= UInt<3>("h03") - oacq_probe.client_xact_id <= UInt<3>("h07") - oacq_probe.addr_block <= io.inner.release.bits.addr_block - oacq_probe.addr_beat <= io.inner.release.bits.addr_beat - oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_726 - node T_744 = bits(xact.union, 12, 9) - node T_745 = bits(T_744, 3, 3) - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_749 = eq(xact.a_type, UInt<3>("h04")) - node T_750 = and(xact.is_builtin_type, T_749) - node T_751 = bits(T_747, 0, 0) - node T_752 = bits(T_747, 1, 1) - wire T_754 : UInt<1>[2] - T_754[0] <= T_751 - T_754[1] <= T_752 - node T_759 = sub(UInt<8>("h00"), T_754[0]) - node T_760 = tail(T_759, 1) - node T_762 = sub(UInt<8>("h00"), T_754[1]) - node T_763 = tail(T_762, 1) - wire T_765 : UInt<8>[2] - T_765[0] <= T_760 - T_765[1] <= T_763 - node T_769 = cat(T_765[1], T_765[0]) - node T_771 = eq(xact.a_type, UInt<3>("h03")) - node T_772 = and(xact.is_builtin_type, T_771) - node T_774 = eq(xact.a_type, UInt<3>("h02")) - node T_775 = and(xact.is_builtin_type, T_774) - node T_776 = or(T_772, T_775) - node T_777 = bits(xact.union, 16, 1) - node T_779 = mux(T_776, T_777, UInt<16>("h00")) - node T_780 = mux(T_750, T_769, T_779) - node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_790 = cat(T_788, T_789) - node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_793 = cat(UInt<3>("h07"), T_792) - node T_795 = cat(T_780, UInt<1>("h01")) - node T_797 = cat(T_780, UInt<1>("h01")) - node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(T_799, T_800) - node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_807 = mux(T_806, T_805, UInt<1>("h00")) - node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_809 = mux(T_808, T_803, T_807) - node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_811 = mux(T_810, T_801, T_809) - node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_813 = mux(T_812, T_797, T_811) - node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_815 = mux(T_814, T_795, T_813) - node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_817 = mux(T_816, T_793, T_815) - node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_819 = mux(T_818, T_790, T_817) - wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat is invalid - oacq_write_beat.is_builtin_type <= UInt<1>("h01") - oacq_write_beat.a_type <= UInt<3>("h02") - oacq_write_beat.client_xact_id <= UInt<3>("h07") - oacq_write_beat.addr_block <= xact.addr_block - oacq_write_beat.addr_beat <= xact.addr_beat - oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_819 - node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_848 = cat(T_846, T_847) - node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_851 = cat(UInt<3>("h07"), T_850) - node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_859 = cat(T_857, T_858) - node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_865 = mux(T_864, T_863, UInt<1>("h00")) - node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_867 = mux(T_866, T_861, T_865) - node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_869 = mux(T_868, T_859, T_867) - node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_871 = mux(T_870, T_855, T_869) - node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_873 = mux(T_872, T_853, T_871) - node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_875 = mux(T_874, T_851, T_873) - node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_877 = mux(T_876, T_848, T_875) - wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block is invalid - oacq_write_block.is_builtin_type <= UInt<1>("h01") - oacq_write_block.a_type <= UInt<3>("h03") - oacq_write_block.client_xact_id <= UInt<3>("h07") - oacq_write_block.addr_block <= xact.addr_block - oacq_write_block.addr_beat <= oacq_data_cnt - oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_877 - node T_895 = bits(xact.union, 12, 9) - node T_896 = bits(xact.union, 8, 6) - node T_904 = cat(T_895, T_896) - node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_906 = cat(T_904, T_905) - node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_909 = cat(T_896, T_908) - node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_915 = cat(T_895, T_896) - node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_917 = cat(T_915, T_916) - node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_923 = mux(T_922, T_921, UInt<1>("h00")) - node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_925 = mux(T_924, T_919, T_923) - node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_927 = mux(T_926, T_917, T_925) - node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_929 = mux(T_928, T_913, T_927) - node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_931 = mux(T_930, T_911, T_929) - node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_933 = mux(T_932, T_909, T_931) - node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_935 = mux(T_934, T_906, T_933) - wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat is invalid - oacq_read_beat.is_builtin_type <= UInt<1>("h01") - oacq_read_beat.a_type <= UInt<3>("h00") - oacq_read_beat.client_xact_id <= UInt<3>("h07") - oacq_read_beat.addr_block <= xact.addr_block - oacq_read_beat.addr_beat <= xact.addr_beat - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_935 - node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_964 = cat(T_962, T_963) - node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_967 = cat(UInt<3>("h07"), T_966) - node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_975 = cat(T_973, T_974) - node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_981 = mux(T_980, T_979, UInt<1>("h00")) - node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_983 = mux(T_982, T_977, T_981) - node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_985 = mux(T_984, T_975, T_983) - node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_987 = mux(T_986, T_971, T_985) - node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_989 = mux(T_988, T_969, T_987) - node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_991 = mux(T_990, T_967, T_989) - node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_993 = mux(T_992, T_964, T_991) - wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block is invalid - oacq_read_block.is_builtin_type <= UInt<1>("h01") - oacq_read_block.a_type <= UInt<3>("h01") - oacq_read_block.client_xact_id <= UInt<3>("h07") - oacq_read_block.addr_block <= xact.addr_block - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_993 - io.outer.acquire.valid <= UInt<1>("h00") - node T_1011 = eq(state, UInt<1>("h01")) - node T_1012 = eq(state, UInt<2>("h03")) - node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) - node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) - node T_1029 = mux(T_1012, T_1013, T_1021) - node T_1037 = mux(T_1011, oacq_probe, T_1029) - io.outer.acquire.bits <- T_1037 - io.outer.grant.ready <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - node T_1054 = eq(UInt<3>("h04"), xact.a_type) - node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) - node T_1056 = eq(UInt<3>("h06"), xact.a_type) - node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) - node T_1058 = eq(UInt<3>("h05"), xact.a_type) - node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) - node T_1060 = eq(UInt<3>("h02"), xact.a_type) - node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) - node T_1062 = eq(UInt<3>("h00"), xact.a_type) - node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) - node T_1064 = eq(UInt<3>("h03"), xact.a_type) - node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) - node T_1066 = eq(UInt<3>("h01"), xact.a_type) - node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) - node T_1068 = eq(UInt<1>("h01"), xact.a_type) - node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) - node T_1070 = eq(UInt<1>("h00"), xact.a_type) - node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) - node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) - wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1077 is invalid - T_1077.client_id <= UInt<1>("h00") - T_1077.p_type <= T_1072 - T_1077.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1077 - io.inner.grant.valid <= UInt<1>("h00") - node T_1100 = eq(UInt<3>("h06"), xact.a_type) - node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) - node T_1102 = eq(UInt<3>("h05"), xact.a_type) - node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) - node T_1104 = eq(UInt<3>("h04"), xact.a_type) - node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) - node T_1106 = eq(UInt<3>("h03"), xact.a_type) - node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) - node T_1108 = eq(UInt<3>("h02"), xact.a_type) - node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) - node T_1110 = eq(UInt<3>("h01"), xact.a_type) - node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) - node T_1112 = eq(UInt<3>("h00"), xact.a_type) - node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) - node T_1114 = eq(xact.a_type, UInt<1>("h00")) - node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) - node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) - node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) - wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1129 is invalid - T_1129.client_id <= xact.client_id - T_1129.is_builtin_type <= xact.is_builtin_type - T_1129.g_type <= T_1120 - T_1129.client_xact_id <= xact.client_xact_id - T_1129.manager_xact_id <= UInt<3>("h07") - T_1129.addr_beat <= UInt<1>("h00") - T_1129.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1129 - io.inner.acquire.ready <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - node T_1140 = neq(state, UInt<1>("h00")) - node T_1141 = and(T_1140, collect_iacq_data) - node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1143 = and(T_1141, T_1142) - node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1145 = and(T_1143, T_1144) - node T_1147 = eq(T_1145, UInt<1>("h00")) - node T_1149 = eq(reset, UInt<1>("h00")) - when T_1149 : - node T_1151 = eq(T_1147, UInt<1>("h00")) - when T_1151 : - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1154 = neq(state, UInt<1>("h00")) - node T_1155 = and(T_1154, collect_iacq_data) - node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1157 = and(T_1155, T_1156) - node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1159 = and(T_1157, T_1158) - node T_1161 = eq(T_1159, UInt<1>("h00")) - node T_1163 = eq(reset, UInt<1>("h00")) - when T_1163 : - node T_1165 = eq(T_1161, UInt<1>("h00")) - when T_1165 : - node T_1167 = eq(reset, UInt<1>("h00")) - when T_1167 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1168 = eq(state, UInt<1>("h00")) - node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1170 = and(T_1168, T_1169) - node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1175 : UInt<3>[1] - T_1175[0] <= UInt<3>("h03") - node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) - node T_1180 = or(UInt<1>("h00"), T_1178) - node T_1181 = and(T_1172, T_1180) - node T_1182 = and(T_1170, T_1181) - node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1185 = and(T_1182, T_1184) - node T_1187 = eq(T_1185, UInt<1>("h00")) - node T_1189 = eq(reset, UInt<1>("h00")) - when T_1189 : - node T_1191 = eq(T_1187, UInt<1>("h00")) - when T_1191 : - node T_1193 = eq(reset, UInt<1>("h00")) - when T_1193 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - when collect_iacq_data : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1198 = bits(T_1197, 3, 3) - node T_1200 = dshl(UInt<1>("h01"), T_1198) - node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) - node T_1204 = bits(T_1200, 0, 0) - node T_1205 = bits(T_1200, 1, 1) - wire T_1207 : UInt<1>[2] - T_1207[0] <= T_1204 - T_1207[1] <= T_1205 - node T_1212 = sub(UInt<8>("h00"), T_1207[0]) - node T_1213 = tail(T_1212, 1) - node T_1215 = sub(UInt<8>("h00"), T_1207[1]) - node T_1216 = tail(T_1215, 1) - wire T_1218 : UInt<8>[2] - T_1218[0] <= T_1213 - T_1218[1] <= T_1216 - node T_1222 = cat(T_1218[1], T_1218[0]) - node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) - node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) - node T_1229 = or(T_1225, T_1228) - node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) - node T_1233 = mux(T_1203, T_1222, T_1232) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 - node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1237 = or(iacq_data_valid, T_1236) - node T_1238 = not(iacq_data_valid) - node T_1239 = or(T_1238, T_1236) - node T_1240 = not(T_1239) - node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) - iacq_data_valid <= T_1241 - skip - when iacq_data_done : - collect_iacq_data <= UInt<1>("h00") - skip - skip - when pending_ognt_ack : - io.outer.grant.ready <= UInt<1>("h01") - when io.outer.grant.valid : - pending_ognt_ack <= UInt<1>("h00") - skip - skip - node T_1245 = eq(UInt<1>("h00"), state) - when T_1245 : - io.inner.acquire.ready <= UInt<1>("h01") - when io.inner.acquire.valid : - xact <- io.inner.acquire.bits - xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1252 = bits(T_1251, 3, 3) - node T_1254 = dshl(UInt<1>("h01"), T_1252) - node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) - node T_1258 = bits(T_1254, 0, 0) - node T_1259 = bits(T_1254, 1, 1) - wire T_1261 : UInt<1>[2] - T_1261[0] <= T_1258 - T_1261[1] <= T_1259 - node T_1266 = sub(UInt<8>("h00"), T_1261[0]) - node T_1267 = tail(T_1266, 1) - node T_1269 = sub(UInt<8>("h00"), T_1261[1]) - node T_1270 = tail(T_1269, 1) - wire T_1272 : UInt<8>[2] - T_1272[0] <= T_1267 - T_1272[1] <= T_1270 - node T_1276 = cat(T_1272[1], T_1272[0]) - node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) - node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) - node T_1283 = or(T_1279, T_1282) - node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) - node T_1287 = mux(T_1257, T_1276, T_1286) - xact.wmask_buffer[UInt<1>("h00")] <= T_1287 - node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1292 : UInt<3>[1] - T_1292[0] <= UInt<3>("h03") - node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) - node T_1297 = or(UInt<1>("h00"), T_1295) - node T_1298 = and(T_1289, T_1297) - collect_iacq_data <= T_1298 - wire T_1303 : UInt<3>[3] - T_1303[0] <= UInt<3>("h02") - T_1303[1] <= UInt<3>("h03") - T_1303[2] <= UInt<3>("h04") - node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) - node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) - node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) - node T_1312 = or(UInt<1>("h00"), T_1308) - node T_1313 = or(T_1312, T_1309) - node T_1314 = or(T_1313, T_1310) - node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) - node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1316 - node T_1318 = neq(mask_incoherent, UInt<1>("h00")) - when T_1318 : - pending_probes <= mask_incoherent - node T_1319 = bits(mask_incoherent, 0, 0) - node T_1320 = bits(mask_incoherent, 1, 1) - node T_1321 = bits(mask_incoherent, 2, 2) - node T_1322 = bits(mask_incoherent, 3, 3) - node T_1324 = cat(UInt<1>("h00"), T_1320) - node T_1325 = add(T_1319, T_1324) - node T_1326 = tail(T_1325, 1) - node T_1329 = cat(UInt<1>("h00"), T_1322) - node T_1330 = add(T_1321, T_1329) - node T_1331 = tail(T_1330, 1) - node T_1332 = cat(UInt<1>("h00"), T_1331) - node T_1333 = add(T_1326, T_1332) - node T_1334 = tail(T_1333, 1) - release_count <= T_1334 - skip - node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) - node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) - state <= T_1337 - skip - skip - node T_1338 = eq(UInt<1>("h01"), state) - when T_1338 : - node T_1340 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1340 - when io.inner.probe.ready : - node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1343 = not(T_1342) - node T_1344 = and(pending_probes, T_1343) - pending_probes <= T_1344 - skip - wire T_1346 : UInt<2>[3] - T_1346[0] <= UInt<1>("h00") - T_1346[1] <= UInt<1>("h01") - T_1346[2] <= UInt<2>("h02") - node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) - node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) - node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) - node T_1355 = or(UInt<1>("h00"), T_1351) - node T_1356 = or(T_1355, T_1352) - node T_1357 = or(T_1356, T_1353) - node T_1359 = eq(T_1357, UInt<1>("h00")) - node T_1360 = or(T_1359, io.outer.acquire.ready) - io.inner.release.ready <= T_1360 - when io.inner.release.valid : - wire T_1362 : UInt<2>[3] - T_1362[0] <= UInt<1>("h00") - T_1362[1] <= UInt<1>("h01") - T_1362[2] <= UInt<2>("h02") - node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) - node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) - node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) - node T_1371 = or(UInt<1>("h00"), T_1367) - node T_1372 = or(T_1371, T_1368) - node T_1373 = or(T_1372, T_1369) - when T_1373 : - io.outer.acquire.valid <= UInt<1>("h01") - when io.outer.acquire.ready : - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1377 = sub(release_count, UInt<1>("h01")) - node T_1378 = tail(T_1377, 1) - release_count <= T_1378 - node T_1380 = eq(release_count, UInt<1>("h01")) - when T_1380 : - node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) - state <= T_1382 - skip - skip - skip - skip - node T_1384 = eq(T_1373, UInt<1>("h00")) - when T_1384 : - node T_1386 = sub(release_count, UInt<1>("h01")) - node T_1387 = tail(T_1386, 1) - release_count <= T_1387 - node T_1389 = eq(release_count, UInt<1>("h01")) - when T_1389 : - node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) - state <= T_1391 - skip - skip - skip - skip - node T_1392 = eq(UInt<2>("h03"), state) - when T_1392 : - node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1398 = bits(T_1397, 0, 0) - node T_1399 = or(T_1396, T_1398) - node T_1400 = and(T_1394, T_1399) - io.outer.acquire.valid <= T_1400 - when oacq_data_done : - pending_ognt_ack <= UInt<1>("h01") - node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1402 - skip - skip - node T_1403 = eq(UInt<2>("h02"), state) - when T_1403 : - node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1405 - node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1406 : - state <= UInt<3>("h05") - skip - skip - node T_1407 = eq(UInt<3>("h05"), state) - when T_1407 : - io.outer.grant.ready <= io.inner.grant.ready - io.inner.grant.valid <= io.outer.grant.valid - when ignt_data_done : - node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) - node T_1415 = eq(T_1413, UInt<1>("h00")) - node T_1416 = and(T_1410, T_1415) - node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1417 - skip - skip - node T_1418 = eq(UInt<3>("h04"), state) - when T_1418 : - io.inner.grant.valid <= UInt<1>("h01") - when io.inner.grant.ready : - node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = and(T_1422, T_1427) - node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1429 - skip - skip - node T_1430 = eq(UInt<3>("h06"), state) - when T_1430 : - io.inner.finish.ready <= UInt<1>("h01") - when io.inner.finish.valid : - state <= UInt<1>("h00") - skip - skip + output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - module LockingRRArbiter_33 : - input clk : Clock + io is invalid + io is invalid + reg ex_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 509:25] + ex_reg_valid <= io.valid @[FPU.scala 509:25] + node req_valid = or(ex_reg_valid, io.cp_req.valid) @[FPU.scala 510:32] + reg ex_reg_inst : UInt<32>, clock @[Reg.scala 34:16] + when io.valid : @[Reg.scala 35:19] + ex_reg_inst <= io.inst @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) @[Decoupled.scala 30:37] + node _T_215 = eq(io.killx, UInt<1>("h00")) @[FPU.scala 513:48] + node _T_216 = and(ex_reg_valid, _T_215) @[FPU.scala 513:45] + node _T_217 = or(_T_216, ex_cp_valid) @[FPU.scala 513:58] + reg mem_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 513:26] + mem_reg_valid <= _T_217 @[FPU.scala 513:26] + reg mem_reg_inst : UInt<32>, clock @[Reg.scala 34:16] + when ex_reg_valid : @[Reg.scala 35:19] + mem_reg_inst <= ex_reg_inst @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg mem_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 515:25] + mem_cp_valid <= ex_cp_valid @[FPU.scala 515:25] + node _T_221 = or(io.killm, io.nack_mem) @[FPU.scala 516:25] + node _T_223 = eq(mem_cp_valid, UInt<1>("h00")) @[FPU.scala 516:44] + node killm = and(_T_221, _T_223) @[FPU.scala 516:41] + node _T_225 = eq(killm, UInt<1>("h00")) @[FPU.scala 517:49] + node _T_226 = or(_T_225, mem_cp_valid) @[FPU.scala 517:56] + node _T_227 = and(mem_reg_valid, _T_226) @[FPU.scala 517:45] + reg wb_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 517:25] + wb_reg_valid <= _T_227 @[FPU.scala 517:25] + reg wb_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 518:24] + wb_cp_valid <= mem_cp_valid @[FPU.scala 518:24] + inst fp_decoder of FPUDecoder @[FPU.scala 520:26] + fp_decoder.io is invalid + fp_decoder.clock <= clock + fp_decoder.reset <= reset + fp_decoder.io.inst <= io.inst @[FPU.scala 521:22] + wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>} @[FPU.scala 523:21] + cp_ctrl is invalid @[FPU.scala 523:21] + cp_ctrl <- io.cp_req.bits @[FPU.scala 524:11] + io.cp_resp.valid <= UInt<1>("h00") @[FPU.scala 525:20] + io.cp_resp.bits.data <= UInt<1>("h00") @[FPU.scala 526:24] + reg _T_282 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when io.valid : @[Reg.scala 35:19] + _T_282 <- fp_decoder.io.sigs @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node ex_ctrl = mux(ex_cp_valid, cp_ctrl, _T_282) @[FPU.scala 529:20] + reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when req_valid : @[Reg.scala 35:19] + mem_ctrl <- ex_ctrl @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when mem_reg_valid : @[Reg.scala 35:19] + wb_ctrl <- mem_ctrl @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb : UInt<1>, clock @[FPU.scala 534:20] + load_wb <= io.dmem_resp_val @[FPU.scala 534:20] + node _T_381 = bits(io.dmem_resp_type, 0, 0) @[FPU.scala 535:52] + node _T_383 = eq(_T_381, UInt<1>("h00")) @[FPU.scala 535:34] + reg load_wb_single : UInt<1>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_single <= _T_383 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb_data : UInt<64>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_data <= io.dmem_resp_data @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb_tag : UInt<5>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_tag <= io.dmem_resp_tag @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_387 = bits(load_wb_data, 31, 31) @[recFNFromFN.scala 47:22] + node _T_388 = bits(load_wb_data, 30, 23) @[recFNFromFN.scala 48:23] + node _T_389 = bits(load_wb_data, 22, 0) @[recFNFromFN.scala 49:25] + node _T_391 = eq(_T_388, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_393 = eq(_T_389, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_394 = and(_T_391, _T_393) @[recFNFromFN.scala 53:34] + node _T_395 = shl(_T_389, 9) @[recFNFromFN.scala 56:26] + node _T_396 = bits(_T_395, 31, 16) @[CircuitMath.scala 35:17] + node _T_397 = bits(_T_395, 15, 0) @[CircuitMath.scala 36:17] + node _T_399 = neq(_T_396, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_400 = bits(_T_396, 15, 8) @[CircuitMath.scala 35:17] + node _T_401 = bits(_T_396, 7, 0) @[CircuitMath.scala 36:17] + node _T_403 = neq(_T_400, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_404 = bits(_T_400, 7, 4) @[CircuitMath.scala 35:17] + node _T_405 = bits(_T_400, 3, 0) @[CircuitMath.scala 36:17] + node _T_407 = neq(_T_404, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_408 = bits(_T_404, 3, 3) @[CircuitMath.scala 32:12] + node _T_410 = bits(_T_404, 2, 2) @[CircuitMath.scala 32:12] + node _T_412 = bits(_T_404, 1, 1) @[CircuitMath.scala 30:8] + node _T_413 = mux(_T_410, UInt<2>("h02"), _T_412) @[CircuitMath.scala 32:10] + node _T_414 = mux(_T_408, UInt<2>("h03"), _T_413) @[CircuitMath.scala 32:10] + node _T_415 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12] + node _T_417 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12] + node _T_419 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8] + node _T_420 = mux(_T_417, UInt<2>("h02"), _T_419) @[CircuitMath.scala 32:10] + node _T_421 = mux(_T_415, UInt<2>("h03"), _T_420) @[CircuitMath.scala 32:10] + node _T_422 = mux(_T_407, _T_414, _T_421) @[CircuitMath.scala 38:21] + node _T_423 = cat(_T_407, _T_422) @[Cat.scala 30:58] + node _T_424 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17] + node _T_425 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17] + node _T_427 = neq(_T_424, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_428 = bits(_T_424, 3, 3) @[CircuitMath.scala 32:12] + node _T_430 = bits(_T_424, 2, 2) @[CircuitMath.scala 32:12] + node _T_432 = bits(_T_424, 1, 1) @[CircuitMath.scala 30:8] + node _T_433 = mux(_T_430, UInt<2>("h02"), _T_432) @[CircuitMath.scala 32:10] + node _T_434 = mux(_T_428, UInt<2>("h03"), _T_433) @[CircuitMath.scala 32:10] + node _T_435 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12] + node _T_437 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12] + node _T_439 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8] + node _T_440 = mux(_T_437, UInt<2>("h02"), _T_439) @[CircuitMath.scala 32:10] + node _T_441 = mux(_T_435, UInt<2>("h03"), _T_440) @[CircuitMath.scala 32:10] + node _T_442 = mux(_T_427, _T_434, _T_441) @[CircuitMath.scala 38:21] + node _T_443 = cat(_T_427, _T_442) @[Cat.scala 30:58] + node _T_444 = mux(_T_403, _T_423, _T_443) @[CircuitMath.scala 38:21] + node _T_445 = cat(_T_403, _T_444) @[Cat.scala 30:58] + node _T_446 = bits(_T_397, 15, 8) @[CircuitMath.scala 35:17] + node _T_447 = bits(_T_397, 7, 0) @[CircuitMath.scala 36:17] + node _T_449 = neq(_T_446, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_450 = bits(_T_446, 7, 4) @[CircuitMath.scala 35:17] + node _T_451 = bits(_T_446, 3, 0) @[CircuitMath.scala 36:17] + node _T_453 = neq(_T_450, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_454 = bits(_T_450, 3, 3) @[CircuitMath.scala 32:12] + node _T_456 = bits(_T_450, 2, 2) @[CircuitMath.scala 32:12] + node _T_458 = bits(_T_450, 1, 1) @[CircuitMath.scala 30:8] + node _T_459 = mux(_T_456, UInt<2>("h02"), _T_458) @[CircuitMath.scala 32:10] + node _T_460 = mux(_T_454, UInt<2>("h03"), _T_459) @[CircuitMath.scala 32:10] + node _T_461 = bits(_T_451, 3, 3) @[CircuitMath.scala 32:12] + node _T_463 = bits(_T_451, 2, 2) @[CircuitMath.scala 32:12] + node _T_465 = bits(_T_451, 1, 1) @[CircuitMath.scala 30:8] + node _T_466 = mux(_T_463, UInt<2>("h02"), _T_465) @[CircuitMath.scala 32:10] + node _T_467 = mux(_T_461, UInt<2>("h03"), _T_466) @[CircuitMath.scala 32:10] + node _T_468 = mux(_T_453, _T_460, _T_467) @[CircuitMath.scala 38:21] + node _T_469 = cat(_T_453, _T_468) @[Cat.scala 30:58] + node _T_470 = bits(_T_447, 7, 4) @[CircuitMath.scala 35:17] + node _T_471 = bits(_T_447, 3, 0) @[CircuitMath.scala 36:17] + node _T_473 = neq(_T_470, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_474 = bits(_T_470, 3, 3) @[CircuitMath.scala 32:12] + node _T_476 = bits(_T_470, 2, 2) @[CircuitMath.scala 32:12] + node _T_478 = bits(_T_470, 1, 1) @[CircuitMath.scala 30:8] + node _T_479 = mux(_T_476, UInt<2>("h02"), _T_478) @[CircuitMath.scala 32:10] + node _T_480 = mux(_T_474, UInt<2>("h03"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = bits(_T_471, 3, 3) @[CircuitMath.scala 32:12] + node _T_483 = bits(_T_471, 2, 2) @[CircuitMath.scala 32:12] + node _T_485 = bits(_T_471, 1, 1) @[CircuitMath.scala 30:8] + node _T_486 = mux(_T_483, UInt<2>("h02"), _T_485) @[CircuitMath.scala 32:10] + node _T_487 = mux(_T_481, UInt<2>("h03"), _T_486) @[CircuitMath.scala 32:10] + node _T_488 = mux(_T_473, _T_480, _T_487) @[CircuitMath.scala 38:21] + node _T_489 = cat(_T_473, _T_488) @[Cat.scala 30:58] + node _T_490 = mux(_T_449, _T_469, _T_489) @[CircuitMath.scala 38:21] + node _T_491 = cat(_T_449, _T_490) @[Cat.scala 30:58] + node _T_492 = mux(_T_399, _T_445, _T_491) @[CircuitMath.scala 38:21] + node _T_493 = cat(_T_399, _T_492) @[Cat.scala 30:58] + node _T_494 = not(_T_493) @[recFNFromFN.scala 56:13] + node _T_495 = dshl(_T_389, _T_494) @[recFNFromFN.scala 58:25] + node _T_496 = bits(_T_495, 21, 0) @[recFNFromFN.scala 58:37] + node _T_498 = cat(_T_496, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_503 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 71:12] + node _T_504 = xor(_T_494, _T_503) @[recFNFromFN.scala 62:27] + node _T_505 = mux(_T_391, _T_504, _T_388) @[recFNFromFN.scala 61:16] + node _T_509 = mux(_T_391, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_510 = or(UInt<8>("h080"), _T_509) @[recFNFromFN.scala 64:42] + node _T_511 = add(_T_505, _T_510) @[recFNFromFN.scala 64:15] + node _T_512 = tail(_T_511, 1) @[recFNFromFN.scala 64:15] + node _T_513 = bits(_T_512, 8, 7) @[recFNFromFN.scala 67:25] + node _T_515 = eq(_T_513, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_517 = eq(_T_393, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_518 = and(_T_515, _T_517) @[recFNFromFN.scala 67:63] + node _T_519 = bits(_T_394, 0, 0) @[Bitwise.scala 71:15] + node _T_522 = mux(_T_519, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_523 = shl(_T_522, 6) @[recFNFromFN.scala 71:45] + node _T_524 = not(_T_523) @[recFNFromFN.scala 71:28] + node _T_525 = and(_T_512, _T_524) @[recFNFromFN.scala 71:26] + node _T_526 = shl(_T_518, 6) @[recFNFromFN.scala 72:22] + node _T_527 = or(_T_525, _T_526) @[recFNFromFN.scala 71:64] + node _T_528 = mux(_T_391, _T_498, _T_389) @[recFNFromFN.scala 73:27] + node _T_529 = cat(_T_387, _T_527) @[Cat.scala 30:58] + node rec_s = cat(_T_529, _T_528) @[Cat.scala 30:58] + node _T_530 = bits(load_wb_data, 63, 63) @[recFNFromFN.scala 47:22] + node _T_531 = bits(load_wb_data, 62, 52) @[recFNFromFN.scala 48:23] + node _T_532 = bits(load_wb_data, 51, 0) @[recFNFromFN.scala 49:25] + node _T_534 = eq(_T_531, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_536 = eq(_T_532, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_537 = and(_T_534, _T_536) @[recFNFromFN.scala 53:34] + node _T_538 = shl(_T_532, 12) @[recFNFromFN.scala 56:26] + node _T_539 = bits(_T_538, 63, 32) @[CircuitMath.scala 35:17] + node _T_540 = bits(_T_538, 31, 0) @[CircuitMath.scala 36:17] + node _T_542 = neq(_T_539, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_543 = bits(_T_539, 31, 16) @[CircuitMath.scala 35:17] + node _T_544 = bits(_T_539, 15, 0) @[CircuitMath.scala 36:17] + node _T_546 = neq(_T_543, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_547 = bits(_T_543, 15, 8) @[CircuitMath.scala 35:17] + node _T_548 = bits(_T_543, 7, 0) @[CircuitMath.scala 36:17] + node _T_550 = neq(_T_547, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_551 = bits(_T_547, 7, 4) @[CircuitMath.scala 35:17] + node _T_552 = bits(_T_547, 3, 0) @[CircuitMath.scala 36:17] + node _T_554 = neq(_T_551, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_555 = bits(_T_551, 3, 3) @[CircuitMath.scala 32:12] + node _T_557 = bits(_T_551, 2, 2) @[CircuitMath.scala 32:12] + node _T_559 = bits(_T_551, 1, 1) @[CircuitMath.scala 30:8] + node _T_560 = mux(_T_557, UInt<2>("h02"), _T_559) @[CircuitMath.scala 32:10] + node _T_561 = mux(_T_555, UInt<2>("h03"), _T_560) @[CircuitMath.scala 32:10] + node _T_562 = bits(_T_552, 3, 3) @[CircuitMath.scala 32:12] + node _T_564 = bits(_T_552, 2, 2) @[CircuitMath.scala 32:12] + node _T_566 = bits(_T_552, 1, 1) @[CircuitMath.scala 30:8] + node _T_567 = mux(_T_564, UInt<2>("h02"), _T_566) @[CircuitMath.scala 32:10] + node _T_568 = mux(_T_562, UInt<2>("h03"), _T_567) @[CircuitMath.scala 32:10] + node _T_569 = mux(_T_554, _T_561, _T_568) @[CircuitMath.scala 38:21] + node _T_570 = cat(_T_554, _T_569) @[Cat.scala 30:58] + node _T_571 = bits(_T_548, 7, 4) @[CircuitMath.scala 35:17] + node _T_572 = bits(_T_548, 3, 0) @[CircuitMath.scala 36:17] + node _T_574 = neq(_T_571, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_575 = bits(_T_571, 3, 3) @[CircuitMath.scala 32:12] + node _T_577 = bits(_T_571, 2, 2) @[CircuitMath.scala 32:12] + node _T_579 = bits(_T_571, 1, 1) @[CircuitMath.scala 30:8] + node _T_580 = mux(_T_577, UInt<2>("h02"), _T_579) @[CircuitMath.scala 32:10] + node _T_581 = mux(_T_575, UInt<2>("h03"), _T_580) @[CircuitMath.scala 32:10] + node _T_582 = bits(_T_572, 3, 3) @[CircuitMath.scala 32:12] + node _T_584 = bits(_T_572, 2, 2) @[CircuitMath.scala 32:12] + node _T_586 = bits(_T_572, 1, 1) @[CircuitMath.scala 30:8] + node _T_587 = mux(_T_584, UInt<2>("h02"), _T_586) @[CircuitMath.scala 32:10] + node _T_588 = mux(_T_582, UInt<2>("h03"), _T_587) @[CircuitMath.scala 32:10] + node _T_589 = mux(_T_574, _T_581, _T_588) @[CircuitMath.scala 38:21] + node _T_590 = cat(_T_574, _T_589) @[Cat.scala 30:58] + node _T_591 = mux(_T_550, _T_570, _T_590) @[CircuitMath.scala 38:21] + node _T_592 = cat(_T_550, _T_591) @[Cat.scala 30:58] + node _T_593 = bits(_T_544, 15, 8) @[CircuitMath.scala 35:17] + node _T_594 = bits(_T_544, 7, 0) @[CircuitMath.scala 36:17] + node _T_596 = neq(_T_593, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_597 = bits(_T_593, 7, 4) @[CircuitMath.scala 35:17] + node _T_598 = bits(_T_593, 3, 0) @[CircuitMath.scala 36:17] + node _T_600 = neq(_T_597, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_601 = bits(_T_597, 3, 3) @[CircuitMath.scala 32:12] + node _T_603 = bits(_T_597, 2, 2) @[CircuitMath.scala 32:12] + node _T_605 = bits(_T_597, 1, 1) @[CircuitMath.scala 30:8] + node _T_606 = mux(_T_603, UInt<2>("h02"), _T_605) @[CircuitMath.scala 32:10] + node _T_607 = mux(_T_601, UInt<2>("h03"), _T_606) @[CircuitMath.scala 32:10] + node _T_608 = bits(_T_598, 3, 3) @[CircuitMath.scala 32:12] + node _T_610 = bits(_T_598, 2, 2) @[CircuitMath.scala 32:12] + node _T_612 = bits(_T_598, 1, 1) @[CircuitMath.scala 30:8] + node _T_613 = mux(_T_610, UInt<2>("h02"), _T_612) @[CircuitMath.scala 32:10] + node _T_614 = mux(_T_608, UInt<2>("h03"), _T_613) @[CircuitMath.scala 32:10] + node _T_615 = mux(_T_600, _T_607, _T_614) @[CircuitMath.scala 38:21] + node _T_616 = cat(_T_600, _T_615) @[Cat.scala 30:58] + node _T_617 = bits(_T_594, 7, 4) @[CircuitMath.scala 35:17] + node _T_618 = bits(_T_594, 3, 0) @[CircuitMath.scala 36:17] + node _T_620 = neq(_T_617, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_621 = bits(_T_617, 3, 3) @[CircuitMath.scala 32:12] + node _T_623 = bits(_T_617, 2, 2) @[CircuitMath.scala 32:12] + node _T_625 = bits(_T_617, 1, 1) @[CircuitMath.scala 30:8] + node _T_626 = mux(_T_623, UInt<2>("h02"), _T_625) @[CircuitMath.scala 32:10] + node _T_627 = mux(_T_621, UInt<2>("h03"), _T_626) @[CircuitMath.scala 32:10] + node _T_628 = bits(_T_618, 3, 3) @[CircuitMath.scala 32:12] + node _T_630 = bits(_T_618, 2, 2) @[CircuitMath.scala 32:12] + node _T_632 = bits(_T_618, 1, 1) @[CircuitMath.scala 30:8] + node _T_633 = mux(_T_630, UInt<2>("h02"), _T_632) @[CircuitMath.scala 32:10] + node _T_634 = mux(_T_628, UInt<2>("h03"), _T_633) @[CircuitMath.scala 32:10] + node _T_635 = mux(_T_620, _T_627, _T_634) @[CircuitMath.scala 38:21] + node _T_636 = cat(_T_620, _T_635) @[Cat.scala 30:58] + node _T_637 = mux(_T_596, _T_616, _T_636) @[CircuitMath.scala 38:21] + node _T_638 = cat(_T_596, _T_637) @[Cat.scala 30:58] + node _T_639 = mux(_T_546, _T_592, _T_638) @[CircuitMath.scala 38:21] + node _T_640 = cat(_T_546, _T_639) @[Cat.scala 30:58] + node _T_641 = bits(_T_540, 31, 16) @[CircuitMath.scala 35:17] + node _T_642 = bits(_T_540, 15, 0) @[CircuitMath.scala 36:17] + node _T_644 = neq(_T_641, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_645 = bits(_T_641, 15, 8) @[CircuitMath.scala 35:17] + node _T_646 = bits(_T_641, 7, 0) @[CircuitMath.scala 36:17] + node _T_648 = neq(_T_645, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_649 = bits(_T_645, 7, 4) @[CircuitMath.scala 35:17] + node _T_650 = bits(_T_645, 3, 0) @[CircuitMath.scala 36:17] + node _T_652 = neq(_T_649, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_653 = bits(_T_649, 3, 3) @[CircuitMath.scala 32:12] + node _T_655 = bits(_T_649, 2, 2) @[CircuitMath.scala 32:12] + node _T_657 = bits(_T_649, 1, 1) @[CircuitMath.scala 30:8] + node _T_658 = mux(_T_655, UInt<2>("h02"), _T_657) @[CircuitMath.scala 32:10] + node _T_659 = mux(_T_653, UInt<2>("h03"), _T_658) @[CircuitMath.scala 32:10] + node _T_660 = bits(_T_650, 3, 3) @[CircuitMath.scala 32:12] + node _T_662 = bits(_T_650, 2, 2) @[CircuitMath.scala 32:12] + node _T_664 = bits(_T_650, 1, 1) @[CircuitMath.scala 30:8] + node _T_665 = mux(_T_662, UInt<2>("h02"), _T_664) @[CircuitMath.scala 32:10] + node _T_666 = mux(_T_660, UInt<2>("h03"), _T_665) @[CircuitMath.scala 32:10] + node _T_667 = mux(_T_652, _T_659, _T_666) @[CircuitMath.scala 38:21] + node _T_668 = cat(_T_652, _T_667) @[Cat.scala 30:58] + node _T_669 = bits(_T_646, 7, 4) @[CircuitMath.scala 35:17] + node _T_670 = bits(_T_646, 3, 0) @[CircuitMath.scala 36:17] + node _T_672 = neq(_T_669, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_673 = bits(_T_669, 3, 3) @[CircuitMath.scala 32:12] + node _T_675 = bits(_T_669, 2, 2) @[CircuitMath.scala 32:12] + node _T_677 = bits(_T_669, 1, 1) @[CircuitMath.scala 30:8] + node _T_678 = mux(_T_675, UInt<2>("h02"), _T_677) @[CircuitMath.scala 32:10] + node _T_679 = mux(_T_673, UInt<2>("h03"), _T_678) @[CircuitMath.scala 32:10] + node _T_680 = bits(_T_670, 3, 3) @[CircuitMath.scala 32:12] + node _T_682 = bits(_T_670, 2, 2) @[CircuitMath.scala 32:12] + node _T_684 = bits(_T_670, 1, 1) @[CircuitMath.scala 30:8] + node _T_685 = mux(_T_682, UInt<2>("h02"), _T_684) @[CircuitMath.scala 32:10] + node _T_686 = mux(_T_680, UInt<2>("h03"), _T_685) @[CircuitMath.scala 32:10] + node _T_687 = mux(_T_672, _T_679, _T_686) @[CircuitMath.scala 38:21] + node _T_688 = cat(_T_672, _T_687) @[Cat.scala 30:58] + node _T_689 = mux(_T_648, _T_668, _T_688) @[CircuitMath.scala 38:21] + node _T_690 = cat(_T_648, _T_689) @[Cat.scala 30:58] + node _T_691 = bits(_T_642, 15, 8) @[CircuitMath.scala 35:17] + node _T_692 = bits(_T_642, 7, 0) @[CircuitMath.scala 36:17] + node _T_694 = neq(_T_691, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_695 = bits(_T_691, 7, 4) @[CircuitMath.scala 35:17] + node _T_696 = bits(_T_691, 3, 0) @[CircuitMath.scala 36:17] + node _T_698 = neq(_T_695, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_699 = bits(_T_695, 3, 3) @[CircuitMath.scala 32:12] + node _T_701 = bits(_T_695, 2, 2) @[CircuitMath.scala 32:12] + node _T_703 = bits(_T_695, 1, 1) @[CircuitMath.scala 30:8] + node _T_704 = mux(_T_701, UInt<2>("h02"), _T_703) @[CircuitMath.scala 32:10] + node _T_705 = mux(_T_699, UInt<2>("h03"), _T_704) @[CircuitMath.scala 32:10] + node _T_706 = bits(_T_696, 3, 3) @[CircuitMath.scala 32:12] + node _T_708 = bits(_T_696, 2, 2) @[CircuitMath.scala 32:12] + node _T_710 = bits(_T_696, 1, 1) @[CircuitMath.scala 30:8] + node _T_711 = mux(_T_708, UInt<2>("h02"), _T_710) @[CircuitMath.scala 32:10] + node _T_712 = mux(_T_706, UInt<2>("h03"), _T_711) @[CircuitMath.scala 32:10] + node _T_713 = mux(_T_698, _T_705, _T_712) @[CircuitMath.scala 38:21] + node _T_714 = cat(_T_698, _T_713) @[Cat.scala 30:58] + node _T_715 = bits(_T_692, 7, 4) @[CircuitMath.scala 35:17] + node _T_716 = bits(_T_692, 3, 0) @[CircuitMath.scala 36:17] + node _T_718 = neq(_T_715, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_719 = bits(_T_715, 3, 3) @[CircuitMath.scala 32:12] + node _T_721 = bits(_T_715, 2, 2) @[CircuitMath.scala 32:12] + node _T_723 = bits(_T_715, 1, 1) @[CircuitMath.scala 30:8] + node _T_724 = mux(_T_721, UInt<2>("h02"), _T_723) @[CircuitMath.scala 32:10] + node _T_725 = mux(_T_719, UInt<2>("h03"), _T_724) @[CircuitMath.scala 32:10] + node _T_726 = bits(_T_716, 3, 3) @[CircuitMath.scala 32:12] + node _T_728 = bits(_T_716, 2, 2) @[CircuitMath.scala 32:12] + node _T_730 = bits(_T_716, 1, 1) @[CircuitMath.scala 30:8] + node _T_731 = mux(_T_728, UInt<2>("h02"), _T_730) @[CircuitMath.scala 32:10] + node _T_732 = mux(_T_726, UInt<2>("h03"), _T_731) @[CircuitMath.scala 32:10] + node _T_733 = mux(_T_718, _T_725, _T_732) @[CircuitMath.scala 38:21] + node _T_734 = cat(_T_718, _T_733) @[Cat.scala 30:58] + node _T_735 = mux(_T_694, _T_714, _T_734) @[CircuitMath.scala 38:21] + node _T_736 = cat(_T_694, _T_735) @[Cat.scala 30:58] + node _T_737 = mux(_T_644, _T_690, _T_736) @[CircuitMath.scala 38:21] + node _T_738 = cat(_T_644, _T_737) @[Cat.scala 30:58] + node _T_739 = mux(_T_542, _T_640, _T_738) @[CircuitMath.scala 38:21] + node _T_740 = cat(_T_542, _T_739) @[Cat.scala 30:58] + node _T_741 = not(_T_740) @[recFNFromFN.scala 56:13] + node _T_742 = dshl(_T_532, _T_741) @[recFNFromFN.scala 58:25] + node _T_743 = bits(_T_742, 50, 0) @[recFNFromFN.scala 58:37] + node _T_745 = cat(_T_743, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_750 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 71:12] + node _T_751 = xor(_T_741, _T_750) @[recFNFromFN.scala 62:27] + node _T_752 = mux(_T_534, _T_751, _T_531) @[recFNFromFN.scala 61:16] + node _T_756 = mux(_T_534, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_757 = or(UInt<11>("h0400"), _T_756) @[recFNFromFN.scala 64:42] + node _T_758 = add(_T_752, _T_757) @[recFNFromFN.scala 64:15] + node _T_759 = tail(_T_758, 1) @[recFNFromFN.scala 64:15] + node _T_760 = bits(_T_759, 11, 10) @[recFNFromFN.scala 67:25] + node _T_762 = eq(_T_760, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_764 = eq(_T_536, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_765 = and(_T_762, _T_764) @[recFNFromFN.scala 67:63] + node _T_766 = bits(_T_537, 0, 0) @[Bitwise.scala 71:15] + node _T_769 = mux(_T_766, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_770 = shl(_T_769, 9) @[recFNFromFN.scala 71:45] + node _T_771 = not(_T_770) @[recFNFromFN.scala 71:28] + node _T_772 = and(_T_759, _T_771) @[recFNFromFN.scala 71:26] + node _T_773 = shl(_T_765, 9) @[recFNFromFN.scala 72:22] + node _T_774 = or(_T_772, _T_773) @[recFNFromFN.scala 71:64] + node _T_775 = mux(_T_534, _T_745, _T_532) @[recFNFromFN.scala 73:27] + node _T_776 = cat(_T_530, _T_774) @[Cat.scala 30:58] + node _T_777 = cat(_T_776, _T_775) @[Cat.scala 30:58] + node _T_779 = or(rec_s, UInt<65>("h0e004000000000000")) @[FPU.scala 543:33] + node load_wb_data_recoded = mux(load_wb_single, _T_779, _T_777) @[FPU.scala 543:10] + cmem regfile : UInt<65>[32] @[FPU.scala 547:20] + when load_wb : @[FPU.scala 548:18] + infer mport _T_782 = regfile[load_wb_tag], clock + _T_782 <= load_wb_data_recoded @[FPU.scala 549:26] + skip @[FPU.scala 548:18] + reg ex_ra1 : UInt, clock @[FPU.scala 554:53] + reg ex_ra2 : UInt, clock @[FPU.scala 554:53] + reg ex_ra3 : UInt, clock @[FPU.scala 554:53] + when io.valid : @[FPU.scala 555:19] + when fp_decoder.io.sigs.ren1 : @[FPU.scala 556:25] + node _T_787 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 557:13] + when _T_787 : @[FPU.scala 557:30] + node _T_788 = bits(io.inst, 19, 15) @[FPU.scala 557:49] + ex_ra1 <= _T_788 @[FPU.scala 557:39] + skip @[FPU.scala 557:30] + when fp_decoder.io.sigs.swap12 : @[FPU.scala 558:29] + node _T_789 = bits(io.inst, 19, 15) @[FPU.scala 558:48] + ex_ra2 <= _T_789 @[FPU.scala 558:38] + skip @[FPU.scala 558:29] + skip @[FPU.scala 556:25] + when fp_decoder.io.sigs.ren2 : @[FPU.scala 560:25] + when fp_decoder.io.sigs.swap12 : @[FPU.scala 561:29] + node _T_790 = bits(io.inst, 24, 20) @[FPU.scala 561:48] + ex_ra1 <= _T_790 @[FPU.scala 561:38] + skip @[FPU.scala 561:29] + when fp_decoder.io.sigs.swap23 : @[FPU.scala 562:29] + node _T_791 = bits(io.inst, 24, 20) @[FPU.scala 562:48] + ex_ra3 <= _T_791 @[FPU.scala 562:38] + skip @[FPU.scala 562:29] + node _T_793 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 563:13] + node _T_795 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) @[FPU.scala 563:32] + node _T_796 = and(_T_793, _T_795) @[FPU.scala 563:29] + when _T_796 : @[FPU.scala 563:49] + node _T_797 = bits(io.inst, 24, 20) @[FPU.scala 563:68] + ex_ra2 <= _T_797 @[FPU.scala 563:58] + skip @[FPU.scala 563:49] + skip @[FPU.scala 560:25] + when fp_decoder.io.sigs.ren3 : @[FPU.scala 565:25] + node _T_798 = bits(io.inst, 31, 27) @[FPU.scala 565:44] + ex_ra3 <= _T_798 @[FPU.scala 565:34] + skip @[FPU.scala 565:25] + skip @[FPU.scala 555:19] + node _T_799 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:30] + node _T_801 = eq(_T_799, UInt<3>("h07")) @[FPU.scala 567:38] + node _T_802 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:74] + node ex_rm = mux(_T_801, io.fcsr_rm, _T_802) @[FPU.scala 567:18] + wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[FPU.scala 569:17] + req is invalid @[FPU.scala 569:17] + req <- ex_ctrl @[FPU.scala 570:7] + req.rm <= ex_rm @[FPU.scala 571:10] + node _T_847 = or(ex_ra1, UInt<5>("h00")) + node _T_848 = bits(_T_847, 4, 0) + infer mport _T_849 = regfile[_T_848], clock + req.in1 <= _T_849 @[FPU.scala 572:11] + node _T_851 = or(ex_ra2, UInt<5>("h00")) + node _T_852 = bits(_T_851, 4, 0) + infer mport _T_853 = regfile[_T_852], clock + req.in2 <= _T_853 @[FPU.scala 573:11] + node _T_855 = or(ex_ra3, UInt<5>("h00")) + node _T_856 = bits(_T_855, 4, 0) + infer mport _T_857 = regfile[_T_856], clock + req.in3 <= _T_857 @[FPU.scala 574:11] + node _T_858 = bits(ex_reg_inst, 21, 20) @[FPU.scala 575:25] + req.typ <= _T_858 @[FPU.scala 575:11] + when ex_cp_valid : @[FPU.scala 576:22] + req <- io.cp_req.bits @[FPU.scala 577:9] + when io.cp_req.bits.swap23 : @[FPU.scala 578:34] + req.in2 <= io.cp_req.bits.in3 @[FPU.scala 579:15] + req.in3 <= io.cp_req.bits.in2 @[FPU.scala 580:15] + skip @[FPU.scala 578:34] + skip @[FPU.scala 576:22] + inst sfma of FPUFMAPipe @[FPU.scala 584:20] + sfma.io is invalid + sfma.clock <= clock + sfma.reset <= reset + node _T_859 = and(req_valid, ex_ctrl.fma) @[FPU.scala 585:33] + node _T_860 = and(_T_859, ex_ctrl.single) @[FPU.scala 585:48] + sfma.io.in.valid <= _T_860 @[FPU.scala 585:20] + sfma.io.in.bits <- req @[FPU.scala 586:19] + inst fpiu of FPToInt @[FPU.scala 588:20] + fpiu.io is invalid + fpiu.clock <= clock + fpiu.reset <= reset + node _T_861 = or(ex_ctrl.toint, ex_ctrl.div) @[FPU.scala 589:51] + node _T_862 = or(_T_861, ex_ctrl.sqrt) @[FPU.scala 589:66] + node _T_865 = and(ex_ctrl.cmd, UInt<4>("h0d")) @[FPU.scala 589:97] + node _T_866 = eq(UInt<3>("h05"), _T_865) @[FPU.scala 589:97] + node _T_867 = or(_T_862, _T_866) @[FPU.scala 589:82] + node _T_868 = and(req_valid, _T_867) @[FPU.scala 589:33] + fpiu.io.in.valid <= _T_868 @[FPU.scala 589:20] + fpiu.io.in.bits <- req @[FPU.scala 590:19] + io.store_data <= fpiu.io.out.bits.store @[FPU.scala 591:17] + io.toint_data <= fpiu.io.out.bits.toint @[FPU.scala 592:17] + node _T_869 = and(fpiu.io.out.valid, mem_cp_valid) @[FPU.scala 593:26] + node _T_870 = and(_T_869, mem_ctrl.toint) @[FPU.scala 593:42] + when _T_870 : @[FPU.scala 593:60] + io.cp_resp.bits.data <= fpiu.io.out.bits.toint @[FPU.scala 594:26] + io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 595:22] + skip @[FPU.scala 593:60] + inst ifpu of IntToFP @[FPU.scala 598:20] + ifpu.io is invalid + ifpu.clock <= clock + ifpu.reset <= reset + node _T_872 = and(req_valid, ex_ctrl.fromint) @[FPU.scala 599:33] + ifpu.io.in.valid <= _T_872 @[FPU.scala 599:20] + ifpu.io.in.bits <- req @[FPU.scala 600:19] + node _T_873 = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) @[FPU.scala 601:29] + ifpu.io.in.bits.in1 <= _T_873 @[FPU.scala 601:23] + inst fpmu of FPToFP @[FPU.scala 603:20] + fpmu.io is invalid + fpmu.clock <= clock + fpmu.reset <= reset + node _T_874 = and(req_valid, ex_ctrl.fastpipe) @[FPU.scala 604:33] + fpmu.io.in.valid <= _T_874 @[FPU.scala 604:20] + fpmu.io.in.bits <- req @[FPU.scala 605:19] + fpmu.io.lt <= fpiu.io.out.bits.lt @[FPU.scala 606:14] + reg divSqrt_wen : UInt<1>, clock @[FPU.scala 608:24] + divSqrt_wen <= UInt<1>("h00") @[FPU.scala 608:24] + wire divSqrt_inReady : UInt<1> + divSqrt_inReady is invalid + divSqrt_inReady <= UInt<1>("h00") + reg divSqrt_waddr : UInt<5>, clock @[FPU.scala 610:26] + reg divSqrt_single : UInt<1>, clock @[FPU.scala 611:27] + wire divSqrt_wdata : UInt<65> @[FPU.scala 612:27] + divSqrt_wdata is invalid @[FPU.scala 612:27] + wire divSqrt_flags : UInt<5> @[FPU.scala 613:27] + divSqrt_flags is invalid @[FPU.scala 613:27] + reg divSqrt_in_flight : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 614:30] + reg divSqrt_killed : UInt<1>, clock @[FPU.scala 615:27] + inst FPUFMAPipe of FPUFMAPipe_1 @[FPU.scala 624:28] + FPUFMAPipe.io is invalid + FPUFMAPipe.clock <= clock + FPUFMAPipe.reset <= reset + node _T_883 = and(req_valid, ex_ctrl.fma) @[FPU.scala 625:41] + node _T_885 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 625:59] + node _T_886 = and(_T_883, _T_885) @[FPU.scala 625:56] + FPUFMAPipe.io.in.valid <= _T_886 @[FPU.scala 625:28] + FPUFMAPipe.io.in.bits <- req @[FPU.scala 626:27] + node _T_889 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_892 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_893 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_896 = mux(_T_893, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_898 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_899 = and(mem_ctrl.fma, _T_898) @[FPU.scala 627:62] + node _T_902 = mux(_T_899, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_903 = or(_T_889, _T_892) @[FPU.scala 631:78] + node _T_904 = or(_T_903, _T_896) @[FPU.scala 631:78] + node memLatencyMask = or(_T_904, _T_902) @[FPU.scala 631:78] + reg wen : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[FPU.scala 645:16] + reg wbInfo : {rd : UInt<5>, single : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clock @[FPU.scala 646:19] + node _T_966 = or(mem_ctrl.fma, mem_ctrl.fastpipe) @[FPU.scala 647:48] + node _T_967 = or(_T_966, mem_ctrl.fromint) @[FPU.scala 647:69] + node mem_wen = and(mem_reg_valid, _T_967) @[FPU.scala 647:31] + node _T_970 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_973 = mux(ex_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_974 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56] + node _T_977 = mux(_T_974, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_979 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_980 = and(ex_ctrl.fma, _T_979) @[FPU.scala 627:62] + node _T_983 = mux(_T_980, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_984 = or(_T_970, _T_973) @[FPU.scala 631:78] + node _T_985 = or(_T_984, _T_977) @[FPU.scala 631:78] + node _T_986 = or(_T_985, _T_983) @[FPU.scala 631:78] + node _T_987 = and(memLatencyMask, _T_986) @[FPU.scala 648:62] + node _T_989 = neq(_T_987, UInt<1>("h00")) @[FPU.scala 648:89] + node _T_990 = and(mem_wen, _T_989) @[FPU.scala 648:43] + node _T_993 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_996 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_997 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56] + node _T_1000 = mux(_T_997, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_1002 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1003 = and(ex_ctrl.fma, _T_1002) @[FPU.scala 627:62] + node _T_1006 = mux(_T_1003, UInt<5>("h010"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_1007 = or(_T_993, _T_996) @[FPU.scala 631:78] + node _T_1008 = or(_T_1007, _T_1000) @[FPU.scala 631:78] + node _T_1009 = or(_T_1008, _T_1006) @[FPU.scala 631:78] + node _T_1010 = and(wen, _T_1009) @[FPU.scala 648:101] + node _T_1012 = neq(_T_1010, UInt<1>("h00")) @[FPU.scala 648:128] + node _T_1013 = or(_T_990, _T_1012) @[FPU.scala 648:93] + reg write_port_busy : UInt<1>, clock @[Reg.scala 34:16] + when req_valid : @[Reg.scala 35:19] + write_port_busy <= _T_1013 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1015 = bits(wen, 1, 1) @[FPU.scala 651:14] + when _T_1015 : @[FPU.scala 651:21] + wbInfo[0] <- wbInfo[1] @[FPU.scala 651:33] + skip @[FPU.scala 651:21] + node _T_1016 = bits(wen, 2, 2) @[FPU.scala 651:14] + when _T_1016 : @[FPU.scala 651:21] + wbInfo[1] <- wbInfo[2] @[FPU.scala 651:33] + skip @[FPU.scala 651:21] + node _T_1017 = shr(wen, 1) @[FPU.scala 653:14] + wen <= _T_1017 @[FPU.scala 653:7] + when mem_wen : @[FPU.scala 654:18] + node _T_1019 = eq(killm, UInt<1>("h00")) @[FPU.scala 655:11] + when _T_1019 : @[FPU.scala 655:19] + node _T_1020 = shr(wen, 1) @[FPU.scala 656:18] + node _T_1021 = or(_T_1020, memLatencyMask) @[FPU.scala 656:23] + wen <= _T_1021 @[FPU.scala 656:11] + skip @[FPU.scala 655:19] + node _T_1023 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1024 = bits(memLatencyMask, 0, 0) @[FPU.scala 659:47] + node _T_1025 = and(_T_1023, _T_1024) @[FPU.scala 659:30] + when _T_1025 : @[FPU.scala 659:52] + wbInfo[0].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[0].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1028 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1031 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1032 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1035 = mux(_T_1032, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1037 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1038 = and(mem_ctrl.fma, _T_1037) @[FPU.scala 627:62] + node _T_1041 = mux(_T_1038, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1042 = or(_T_1028, _T_1031) @[FPU.scala 633:108] + node _T_1043 = or(_T_1042, _T_1035) @[FPU.scala 633:108] + node _T_1044 = or(_T_1043, _T_1041) @[FPU.scala 633:108] + wbInfo[0].pipeid <= _T_1044 @[FPU.scala 662:26] + node _T_1045 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[0].rd <= _T_1045 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + node _T_1047 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1048 = bits(memLatencyMask, 1, 1) @[FPU.scala 659:47] + node _T_1049 = and(_T_1047, _T_1048) @[FPU.scala 659:30] + when _T_1049 : @[FPU.scala 659:52] + wbInfo[1].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[1].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1052 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1055 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1056 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1059 = mux(_T_1056, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1061 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1062 = and(mem_ctrl.fma, _T_1061) @[FPU.scala 627:62] + node _T_1065 = mux(_T_1062, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1066 = or(_T_1052, _T_1055) @[FPU.scala 633:108] + node _T_1067 = or(_T_1066, _T_1059) @[FPU.scala 633:108] + node _T_1068 = or(_T_1067, _T_1065) @[FPU.scala 633:108] + wbInfo[1].pipeid <= _T_1068 @[FPU.scala 662:26] + node _T_1069 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[1].rd <= _T_1069 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + node _T_1071 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1072 = bits(memLatencyMask, 2, 2) @[FPU.scala 659:47] + node _T_1073 = and(_T_1071, _T_1072) @[FPU.scala 659:30] + when _T_1073 : @[FPU.scala 659:52] + wbInfo[2].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[2].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1076 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1079 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1080 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1083 = mux(_T_1080, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1085 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1086 = and(mem_ctrl.fma, _T_1085) @[FPU.scala 627:62] + node _T_1089 = mux(_T_1086, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1090 = or(_T_1076, _T_1079) @[FPU.scala 633:108] + node _T_1091 = or(_T_1090, _T_1083) @[FPU.scala 633:108] + node _T_1092 = or(_T_1091, _T_1089) @[FPU.scala 633:108] + wbInfo[2].pipeid <= _T_1092 @[FPU.scala 662:26] + node _T_1093 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[2].rd <= _T_1093 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + skip @[FPU.scala 654:18] + node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) @[FPU.scala 668:18] + node _T_1095 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1097 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1099 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1101 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1102 = mux(_T_1101, FPUFMAPipe.io.out.bits.data, sfma.io.out.bits.data) @[Package.scala 19:12] + node _T_1104 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1106 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1107 = mux(_T_1106, ifpu.io.out.bits.data, fpmu.io.out.bits.data) @[Package.scala 19:12] + node _T_1108 = mux(_T_1097, _T_1102, _T_1107) @[Package.scala 19:12] + node wdata0 = mux(divSqrt_wen, divSqrt_wdata, _T_1108) @[FPU.scala 669:19] + node wsingle = mux(divSqrt_wen, divSqrt_single, wbInfo[0].single) @[FPU.scala 670:20] + node _T_1109 = bits(wdata0, 32, 0) @[FPU.scala 673:36] + node _T_1111 = or(_T_1109, UInt<65>("h0e004000000000000")) @[FPU.scala 673:44] + node wdata = mux(wsingle, _T_1111, wdata0) @[FPU.scala 673:19] + node _T_1113 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1115 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1117 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1119 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1120 = mux(_T_1119, FPUFMAPipe.io.out.bits.exc, sfma.io.out.bits.exc) @[Package.scala 19:12] + node _T_1122 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1124 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1125 = mux(_T_1124, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) @[Package.scala 19:12] + node wexc = mux(_T_1115, _T_1120, _T_1125) @[Package.scala 19:12] + node _T_1127 = eq(wbInfo[0].cp, UInt<1>("h00")) @[FPU.scala 676:10] + node _T_1128 = bits(wen, 0, 0) @[FPU.scala 676:30] + node _T_1129 = and(_T_1127, _T_1128) @[FPU.scala 676:24] + node _T_1130 = or(_T_1129, divSqrt_wen) @[FPU.scala 676:35] + when _T_1130 : @[FPU.scala 676:51] + infer mport _T_1131 = regfile[waddr], clock + _T_1131 <= wdata @[FPU.scala 677:20] + skip @[FPU.scala 676:51] + node _T_1132 = bits(wen, 0, 0) @[FPU.scala 689:28] + node _T_1133 = and(wbInfo[0].cp, _T_1132) @[FPU.scala 689:22] + when _T_1133 : @[FPU.scala 689:33] + io.cp_resp.bits.data <= wdata @[FPU.scala 690:26] + io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 691:22] + skip @[FPU.scala 689:33] + node _T_1136 = eq(ex_reg_valid, UInt<1>("h00")) @[FPU.scala 693:22] + io.cp_req.ready <= _T_1136 @[FPU.scala 693:19] + node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 695:37] + reg wb_toint_exc : UInt<5>, clock @[Reg.scala 34:16] + when mem_ctrl.toint : @[Reg.scala 35:19] + wb_toint_exc <= fpiu.io.out.bits.exc @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1138 = or(wb_toint_valid, divSqrt_wen) @[FPU.scala 697:41] + node _T_1139 = bits(wen, 0, 0) @[FPU.scala 697:62] + node _T_1140 = or(_T_1138, _T_1139) @[FPU.scala 697:56] + io.fcsr_flags.valid <= _T_1140 @[FPU.scala 697:23] + node _T_1142 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) @[FPU.scala 699:8] + node _T_1144 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) @[FPU.scala 700:8] + node _T_1145 = or(_T_1142, _T_1144) @[FPU.scala 699:48] + node _T_1146 = bits(wen, 0, 0) @[FPU.scala 701:12] + node _T_1148 = mux(_T_1146, wexc, UInt<1>("h00")) @[FPU.scala 701:8] + node _T_1149 = or(_T_1145, _T_1148) @[FPU.scala 700:46] + io.fcsr_flags.bits <= _T_1149 @[FPU.scala 698:22] + node _T_1150 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 703:51] + node _T_1151 = and(mem_reg_valid, _T_1150) @[FPU.scala 703:34] + node _T_1153 = eq(divSqrt_inReady, UInt<1>("h00")) @[FPU.scala 703:73] + node _T_1155 = neq(wen, UInt<1>("h00")) @[FPU.scala 703:97] + node _T_1156 = or(_T_1153, _T_1155) @[FPU.scala 703:90] + node units_busy = and(_T_1151, _T_1156) @[FPU.scala 703:69] + node _T_1157 = and(ex_reg_valid, ex_ctrl.wflags) @[FPU.scala 704:33] + node _T_1158 = and(mem_reg_valid, mem_ctrl.wflags) @[FPU.scala 704:68] + node _T_1159 = or(_T_1157, _T_1158) @[FPU.scala 704:51] + node _T_1160 = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 704:103] + node _T_1161 = or(_T_1159, _T_1160) @[FPU.scala 704:87] + node _T_1163 = neq(wen, UInt<1>("h00")) @[FPU.scala 704:127] + node _T_1164 = or(_T_1161, _T_1163) @[FPU.scala 704:120] + node _T_1165 = or(_T_1164, divSqrt_in_flight) @[FPU.scala 704:131] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[FPU.scala 704:18] + io.fcsr_rdy <= _T_1167 @[FPU.scala 704:15] + node _T_1168 = or(units_busy, write_port_busy) @[FPU.scala 705:29] + node _T_1169 = or(_T_1168, divSqrt_in_flight) @[FPU.scala 705:48] + io.nack_mem <= _T_1169 @[FPU.scala 705:15] + io.dec <- fp_decoder.io.sigs @[FPU.scala 706:10] + node _T_1171 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 708:36] + node _T_1172 = and(wb_reg_valid, _T_1171) @[FPU.scala 708:33] + node _T_1174 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1175 = and(mem_ctrl.fma, _T_1174) @[FPU.scala 627:62] + node _T_1177 = or(UInt<1>("h00"), _T_1175) @[FPU.scala 707:123] + node _T_1178 = or(_T_1177, mem_ctrl.div) @[FPU.scala 708:96] + node _T_1179 = or(_T_1178, mem_ctrl.sqrt) @[FPU.scala 708:112] + reg _T_1180 : UInt<1>, clock @[FPU.scala 708:55] + _T_1180 <= _T_1179 @[FPU.scala 708:55] + node _T_1181 = and(_T_1172, _T_1180) @[FPU.scala 708:49] + io.sboard_set <= _T_1181 @[FPU.scala 708:17] + node _T_1183 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 709:20] + node _T_1184 = bits(wen, 0, 0) @[FPU.scala 709:56] + node _T_1186 = eq(wbInfo[0].pipeid, UInt<2>("h03")) @[FPU.scala 709:99] + node _T_1188 = or(UInt<1>("h00"), _T_1186) @[FPU.scala 707:123] + node _T_1189 = and(_T_1184, _T_1188) @[FPU.scala 709:60] + node _T_1190 = or(divSqrt_wen, _T_1189) @[FPU.scala 709:49] + node _T_1191 = and(_T_1183, _T_1190) @[FPU.scala 709:33] + io.sboard_clr <= _T_1191 @[FPU.scala 709:17] + io.sboard_clra <= waddr @[FPU.scala 710:18] + node _T_1192 = bits(io.inst, 14, 14) @[FPU.scala 712:27] + node _T_1193 = bits(io.inst, 13, 12) @[FPU.scala 712:43] + node _T_1195 = lt(_T_1193, UInt<2>("h03")) @[FPU.scala 712:51] + node _T_1197 = geq(io.fcsr_rm, UInt<3>("h04")) @[FPU.scala 712:69] + node _T_1198 = or(_T_1195, _T_1197) @[FPU.scala 712:55] + node _T_1199 = and(_T_1192, _T_1198) @[FPU.scala 712:32] + io.illegal_rm <= _T_1199 @[FPU.scala 712:17] + divSqrt_wdata <= UInt<1>("h00") @[FPU.scala 714:17] + divSqrt_flags <= UInt<1>("h00") @[FPU.scala 715:17] + reg _T_1203 : UInt, clock @[FPU.scala 718:25] + reg _T_1205 : UInt, clock @[FPU.scala 719:35] + reg _T_1207 : UInt, clock @[FPU.scala 720:35] + inst DivSqrtRecF64 of DivSqrtRecF64 @[FPU.scala 722:25] + DivSqrtRecF64.io is invalid + DivSqrtRecF64.clock <= clock + DivSqrtRecF64.reset <= reset + node _T_1208 = mux(DivSqrtRecF64.io.sqrtOp, DivSqrtRecF64.io.inReady_sqrt, DivSqrtRecF64.io.inReady_div) @[FPU.scala 723:27] + divSqrt_inReady <= _T_1208 @[FPU.scala 723:21] + node _T_1209 = or(DivSqrtRecF64.io.outValid_div, DivSqrtRecF64.io.outValid_sqrt) @[FPU.scala 724:52] + node _T_1210 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 725:58] + node _T_1211 = and(mem_reg_valid, _T_1210) @[FPU.scala 725:41] + node _T_1213 = eq(divSqrt_in_flight, UInt<1>("h00")) @[FPU.scala 725:79] + node _T_1214 = and(_T_1211, _T_1213) @[FPU.scala 725:76] + DivSqrtRecF64.io.inValid <= _T_1214 @[FPU.scala 725:24] + DivSqrtRecF64.io.sqrtOp <= mem_ctrl.sqrt @[FPU.scala 726:23] + DivSqrtRecF64.io.a <= fpiu.io.as_double.in1 @[FPU.scala 727:18] + DivSqrtRecF64.io.b <= fpiu.io.as_double.in2 @[FPU.scala 728:18] + DivSqrtRecF64.io.roundingMode <= fpiu.io.as_double.rm @[FPU.scala 729:29] + node _T_1215 = and(DivSqrtRecF64.io.inValid, divSqrt_inReady) @[FPU.scala 731:30] + when _T_1215 : @[FPU.scala 731:50] + divSqrt_in_flight <= UInt<1>("h01") @[FPU.scala 732:25] + divSqrt_killed <= killm @[FPU.scala 733:22] + divSqrt_single <= mem_ctrl.single @[FPU.scala 734:22] + node _T_1217 = bits(mem_reg_inst, 11, 7) @[FPU.scala 735:36] + divSqrt_waddr <= _T_1217 @[FPU.scala 735:21] + _T_1203 <= DivSqrtRecF64.io.roundingMode @[FPU.scala 736:18] + skip @[FPU.scala 731:50] + when _T_1209 : @[FPU.scala 739:29] + node _T_1219 = eq(divSqrt_killed, UInt<1>("h00")) @[FPU.scala 740:22] + divSqrt_wen <= _T_1219 @[FPU.scala 740:19] + _T_1207 <= DivSqrtRecF64.io.out @[FPU.scala 741:28] + divSqrt_in_flight <= UInt<1>("h00") @[FPU.scala 742:25] + _T_1205 <= DivSqrtRecF64.io.exceptionFlags @[FPU.scala 743:28] + skip @[FPU.scala 739:29] + inst RecFNToRecFN of RecFNToRecFN_2 @[FPU.scala 746:34] + RecFNToRecFN.io is invalid + RecFNToRecFN.clock <= clock + RecFNToRecFN.reset <= reset + RecFNToRecFN.io.in <= _T_1207 @[FPU.scala 747:28] + RecFNToRecFN.io.roundingMode <= _T_1203 @[FPU.scala 748:38] + node _T_1221 = mux(divSqrt_single, RecFNToRecFN.io.out, _T_1207) @[FPU.scala 749:25] + divSqrt_wdata <= _T_1221 @[FPU.scala 749:19] + node _T_1223 = mux(divSqrt_single, RecFNToRecFN.io.exceptionFlags, UInt<1>("h00")) @[FPU.scala 750:48] + node _T_1224 = or(_T_1205, _T_1223) @[FPU.scala 750:43] + divSqrt_flags <= _T_1224 @[FPU.scala 750:19] + + module HellaCacheArbiter : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, chosen : UInt<3>} - - io is invalid - reg T_1502 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1504 : UInt, clk with : (reset => (reset, UInt<3>("h07"))) - wire T_1506 : UInt<3> - T_1506 is invalid - io.out.valid <= io.in[T_1506].valid - io.out.bits <- io.in[T_1506].bits - io.chosen <= T_1506 - io.in[T_1506].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_1706 = gt(UInt<1>("h00"), last_grant) - node T_1707 = and(io.in[0].valid, T_1706) - node T_1709 = gt(UInt<1>("h01"), last_grant) - node T_1710 = and(io.in[1].valid, T_1709) - node T_1712 = gt(UInt<2>("h02"), last_grant) - node T_1713 = and(io.in[2].valid, T_1712) - node T_1715 = gt(UInt<2>("h03"), last_grant) - node T_1716 = and(io.in[3].valid, T_1715) - node T_1718 = gt(UInt<3>("h04"), last_grant) - node T_1719 = and(io.in[4].valid, T_1718) - node T_1721 = gt(UInt<3>("h05"), last_grant) - node T_1722 = and(io.in[5].valid, T_1721) - node T_1724 = gt(UInt<3>("h06"), last_grant) - node T_1725 = and(io.in[6].valid, T_1724) - node T_1727 = gt(UInt<3>("h07"), last_grant) - node T_1728 = and(io.in[7].valid, T_1727) - node T_1731 = or(UInt<1>("h00"), T_1707) - node T_1733 = eq(T_1731, UInt<1>("h00")) - node T_1735 = or(UInt<1>("h00"), T_1707) - node T_1736 = or(T_1735, T_1710) - node T_1738 = eq(T_1736, UInt<1>("h00")) - node T_1740 = or(UInt<1>("h00"), T_1707) - node T_1741 = or(T_1740, T_1710) - node T_1742 = or(T_1741, T_1713) - node T_1744 = eq(T_1742, UInt<1>("h00")) - node T_1746 = or(UInt<1>("h00"), T_1707) - node T_1747 = or(T_1746, T_1710) - node T_1748 = or(T_1747, T_1713) - node T_1749 = or(T_1748, T_1716) - node T_1751 = eq(T_1749, UInt<1>("h00")) - node T_1753 = or(UInt<1>("h00"), T_1707) - node T_1754 = or(T_1753, T_1710) - node T_1755 = or(T_1754, T_1713) - node T_1756 = or(T_1755, T_1716) - node T_1757 = or(T_1756, T_1719) - node T_1759 = eq(T_1757, UInt<1>("h00")) - node T_1761 = or(UInt<1>("h00"), T_1707) - node T_1762 = or(T_1761, T_1710) - node T_1763 = or(T_1762, T_1713) - node T_1764 = or(T_1763, T_1716) - node T_1765 = or(T_1764, T_1719) - node T_1766 = or(T_1765, T_1722) - node T_1768 = eq(T_1766, UInt<1>("h00")) - node T_1770 = or(UInt<1>("h00"), T_1707) - node T_1771 = or(T_1770, T_1710) - node T_1772 = or(T_1771, T_1713) - node T_1773 = or(T_1772, T_1716) - node T_1774 = or(T_1773, T_1719) - node T_1775 = or(T_1774, T_1722) - node T_1776 = or(T_1775, T_1725) - node T_1778 = eq(T_1776, UInt<1>("h00")) - node T_1780 = or(UInt<1>("h00"), T_1707) - node T_1781 = or(T_1780, T_1710) - node T_1782 = or(T_1781, T_1713) - node T_1783 = or(T_1782, T_1716) - node T_1784 = or(T_1783, T_1719) - node T_1785 = or(T_1784, T_1722) - node T_1786 = or(T_1785, T_1725) - node T_1787 = or(T_1786, T_1728) - node T_1789 = eq(T_1787, UInt<1>("h00")) - node T_1791 = or(UInt<1>("h00"), T_1707) - node T_1792 = or(T_1791, T_1710) - node T_1793 = or(T_1792, T_1713) - node T_1794 = or(T_1793, T_1716) - node T_1795 = or(T_1794, T_1719) - node T_1796 = or(T_1795, T_1722) - node T_1797 = or(T_1796, T_1725) - node T_1798 = or(T_1797, T_1728) - node T_1799 = or(T_1798, io.in[0].valid) - node T_1801 = eq(T_1799, UInt<1>("h00")) - node T_1803 = or(UInt<1>("h00"), T_1707) - node T_1804 = or(T_1803, T_1710) - node T_1805 = or(T_1804, T_1713) - node T_1806 = or(T_1805, T_1716) - node T_1807 = or(T_1806, T_1719) - node T_1808 = or(T_1807, T_1722) - node T_1809 = or(T_1808, T_1725) - node T_1810 = or(T_1809, T_1728) - node T_1811 = or(T_1810, io.in[0].valid) - node T_1812 = or(T_1811, io.in[1].valid) - node T_1814 = eq(T_1812, UInt<1>("h00")) - node T_1816 = or(UInt<1>("h00"), T_1707) - node T_1817 = or(T_1816, T_1710) - node T_1818 = or(T_1817, T_1713) - node T_1819 = or(T_1818, T_1716) - node T_1820 = or(T_1819, T_1719) - node T_1821 = or(T_1820, T_1722) - node T_1822 = or(T_1821, T_1725) - node T_1823 = or(T_1822, T_1728) - node T_1824 = or(T_1823, io.in[0].valid) - node T_1825 = or(T_1824, io.in[1].valid) - node T_1826 = or(T_1825, io.in[2].valid) - node T_1828 = eq(T_1826, UInt<1>("h00")) - node T_1830 = or(UInt<1>("h00"), T_1707) - node T_1831 = or(T_1830, T_1710) - node T_1832 = or(T_1831, T_1713) - node T_1833 = or(T_1832, T_1716) - node T_1834 = or(T_1833, T_1719) - node T_1835 = or(T_1834, T_1722) - node T_1836 = or(T_1835, T_1725) - node T_1837 = or(T_1836, T_1728) - node T_1838 = or(T_1837, io.in[0].valid) - node T_1839 = or(T_1838, io.in[1].valid) - node T_1840 = or(T_1839, io.in[2].valid) - node T_1841 = or(T_1840, io.in[3].valid) - node T_1843 = eq(T_1841, UInt<1>("h00")) - node T_1845 = or(UInt<1>("h00"), T_1707) - node T_1846 = or(T_1845, T_1710) - node T_1847 = or(T_1846, T_1713) - node T_1848 = or(T_1847, T_1716) - node T_1849 = or(T_1848, T_1719) - node T_1850 = or(T_1849, T_1722) - node T_1851 = or(T_1850, T_1725) - node T_1852 = or(T_1851, T_1728) - node T_1853 = or(T_1852, io.in[0].valid) - node T_1854 = or(T_1853, io.in[1].valid) - node T_1855 = or(T_1854, io.in[2].valid) - node T_1856 = or(T_1855, io.in[3].valid) - node T_1857 = or(T_1856, io.in[4].valid) - node T_1859 = eq(T_1857, UInt<1>("h00")) - node T_1861 = or(UInt<1>("h00"), T_1707) - node T_1862 = or(T_1861, T_1710) - node T_1863 = or(T_1862, T_1713) - node T_1864 = or(T_1863, T_1716) - node T_1865 = or(T_1864, T_1719) - node T_1866 = or(T_1865, T_1722) - node T_1867 = or(T_1866, T_1725) - node T_1868 = or(T_1867, T_1728) - node T_1869 = or(T_1868, io.in[0].valid) - node T_1870 = or(T_1869, io.in[1].valid) - node T_1871 = or(T_1870, io.in[2].valid) - node T_1872 = or(T_1871, io.in[3].valid) - node T_1873 = or(T_1872, io.in[4].valid) - node T_1874 = or(T_1873, io.in[5].valid) - node T_1876 = eq(T_1874, UInt<1>("h00")) - node T_1878 = or(UInt<1>("h00"), T_1707) - node T_1879 = or(T_1878, T_1710) - node T_1880 = or(T_1879, T_1713) - node T_1881 = or(T_1880, T_1716) - node T_1882 = or(T_1881, T_1719) - node T_1883 = or(T_1882, T_1722) - node T_1884 = or(T_1883, T_1725) - node T_1885 = or(T_1884, T_1728) - node T_1886 = or(T_1885, io.in[0].valid) - node T_1887 = or(T_1886, io.in[1].valid) - node T_1888 = or(T_1887, io.in[2].valid) - node T_1889 = or(T_1888, io.in[3].valid) - node T_1890 = or(T_1889, io.in[4].valid) - node T_1891 = or(T_1890, io.in[5].valid) - node T_1892 = or(T_1891, io.in[6].valid) - node T_1894 = eq(T_1892, UInt<1>("h00")) - node T_1896 = gt(UInt<1>("h00"), last_grant) - node T_1897 = and(UInt<1>("h01"), T_1896) - node T_1898 = or(T_1897, T_1789) - node T_1900 = gt(UInt<1>("h01"), last_grant) - node T_1901 = and(T_1733, T_1900) - node T_1902 = or(T_1901, T_1801) - node T_1904 = gt(UInt<2>("h02"), last_grant) - node T_1905 = and(T_1738, T_1904) - node T_1906 = or(T_1905, T_1814) - node T_1908 = gt(UInt<2>("h03"), last_grant) - node T_1909 = and(T_1744, T_1908) - node T_1910 = or(T_1909, T_1828) - node T_1912 = gt(UInt<3>("h04"), last_grant) - node T_1913 = and(T_1751, T_1912) - node T_1914 = or(T_1913, T_1843) - node T_1916 = gt(UInt<3>("h05"), last_grant) - node T_1917 = and(T_1759, T_1916) - node T_1918 = or(T_1917, T_1859) - node T_1920 = gt(UInt<3>("h06"), last_grant) - node T_1921 = and(T_1768, T_1920) - node T_1922 = or(T_1921, T_1876) - node T_1924 = gt(UInt<3>("h07"), last_grant) - node T_1925 = and(T_1778, T_1924) - node T_1926 = or(T_1925, T_1894) - node T_1928 = eq(T_1504, UInt<1>("h00")) - node T_1929 = mux(T_1502, T_1928, T_1898) - node T_1930 = and(T_1929, io.out.ready) - io.in[0].ready <= T_1930 - node T_1932 = eq(T_1504, UInt<1>("h01")) - node T_1933 = mux(T_1502, T_1932, T_1902) - node T_1934 = and(T_1933, io.out.ready) - io.in[1].ready <= T_1934 - node T_1936 = eq(T_1504, UInt<2>("h02")) - node T_1937 = mux(T_1502, T_1936, T_1906) - node T_1938 = and(T_1937, io.out.ready) - io.in[2].ready <= T_1938 - node T_1940 = eq(T_1504, UInt<2>("h03")) - node T_1941 = mux(T_1502, T_1940, T_1910) - node T_1942 = and(T_1941, io.out.ready) - io.in[3].ready <= T_1942 - node T_1944 = eq(T_1504, UInt<3>("h04")) - node T_1945 = mux(T_1502, T_1944, T_1914) - node T_1946 = and(T_1945, io.out.ready) - io.in[4].ready <= T_1946 - node T_1948 = eq(T_1504, UInt<3>("h05")) - node T_1949 = mux(T_1502, T_1948, T_1918) - node T_1950 = and(T_1949, io.out.ready) - io.in[5].ready <= T_1950 - node T_1952 = eq(T_1504, UInt<3>("h06")) - node T_1953 = mux(T_1502, T_1952, T_1922) - node T_1954 = and(T_1953, io.out.ready) - io.in[6].ready <= T_1954 - node T_1956 = eq(T_1504, UInt<3>("h07")) - node T_1957 = mux(T_1502, T_1956, T_1926) - node T_1958 = and(T_1957, io.out.ready) - io.in[7].ready <= T_1958 - reg T_1960 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_1962 = add(T_1960, UInt<1>("h01")) - node T_1963 = tail(T_1962, 1) - node T_1964 = and(io.out.ready, io.out.valid) - when T_1964 : - wire T_1968 : UInt<3>[1] - T_1968[0] <= UInt<3>("h05") - node T_1971 = eq(T_1968[0], io.out.bits.g_type) - node T_1973 = or(UInt<1>("h00"), T_1971) - wire T_1975 : UInt<1>[2] - T_1975[0] <= UInt<1>("h00") - T_1975[1] <= UInt<1>("h01") - node T_1979 = eq(T_1975[0], io.out.bits.g_type) - node T_1980 = eq(T_1975[1], io.out.bits.g_type) - node T_1982 = or(UInt<1>("h00"), T_1979) - node T_1983 = or(T_1982, T_1980) - node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983) - node T_1985 = and(UInt<1>("h01"), T_1984) - when T_1985 : - T_1960 <= T_1963 - node T_1987 = eq(T_1502, UInt<1>("h00")) - when T_1987 : - T_1502 <= UInt<1>("h01") - node T_1989 = and(io.in[0].ready, io.in[0].valid) - node T_1990 = and(io.in[1].ready, io.in[1].valid) - node T_1991 = and(io.in[2].ready, io.in[2].valid) - node T_1992 = and(io.in[3].ready, io.in[3].valid) - node T_1993 = and(io.in[4].ready, io.in[4].valid) - node T_1994 = and(io.in[5].ready, io.in[5].valid) - node T_1995 = and(io.in[6].ready, io.in[6].valid) - node T_1996 = and(io.in[7].ready, io.in[7].valid) - wire T_1998 : UInt<1>[8] - T_1998[0] <= T_1989 - T_1998[1] <= T_1990 - T_1998[2] <= T_1991 - T_1998[3] <= T_1992 - T_1998[4] <= T_1993 - T_1998[5] <= T_1994 - T_1998[6] <= T_1995 - T_1998[7] <= T_1996 - node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07")) - node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016) - node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017) - node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018) - node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019) - node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020) - node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021) - T_1504 <= T_2022 - skip - skip - node T_2024 = eq(T_1963, UInt<1>("h00")) - when T_2024 : - T_1502 <= UInt<1>("h00") - skip - skip - node T_2028 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_2030 = mux(io.in[5].valid, UInt<3>("h05"), T_2028) - node T_2032 = mux(io.in[4].valid, UInt<3>("h04"), T_2030) - node T_2034 = mux(io.in[3].valid, UInt<2>("h03"), T_2032) - node T_2036 = mux(io.in[2].valid, UInt<2>("h02"), T_2034) - node T_2038 = mux(io.in[1].valid, UInt<1>("h01"), T_2036) - node T_2040 = mux(io.in[0].valid, UInt<1>("h00"), T_2038) - node T_2042 = gt(UInt<3>("h07"), last_grant) - node T_2043 = and(io.in[7].valid, T_2042) - node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040) - node T_2047 = gt(UInt<3>("h06"), last_grant) - node T_2048 = and(io.in[6].valid, T_2047) - node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045) - node T_2052 = gt(UInt<3>("h05"), last_grant) - node T_2053 = and(io.in[5].valid, T_2052) - node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050) - node T_2057 = gt(UInt<3>("h04"), last_grant) - node T_2058 = and(io.in[4].valid, T_2057) - node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055) - node T_2062 = gt(UInt<2>("h03"), last_grant) - node T_2063 = and(io.in[3].valid, T_2062) - node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060) - node T_2067 = gt(UInt<2>("h02"), last_grant) - node T_2068 = and(io.in[2].valid, T_2067) - node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065) - node T_2072 = gt(UInt<1>("h01"), last_grant) - node T_2073 = and(io.in[1].valid, T_2072) - node choose = mux(T_2073, UInt<1>("h01"), T_2070) - node T_2076 = mux(T_1502, T_1504, choose) - T_1506 <= T_2076 - node T_2077 = and(io.out.ready, io.out.valid) - when T_2077 : - last_grant <= T_1506 - skip + output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} - module LockingRRArbiter_34 : - input clk : Clock + io is invalid + io is invalid + reg _T_1244 : UInt, clock @[Arbiter.scala 20:20] + reg _T_1245 : UInt, clock @[Arbiter.scala 21:20] + _T_1245 <= _T_1244 @[Arbiter.scala 21:20] + node _T_1246 = or(io.requestor[0].invalidate_lr, io.requestor[1].invalidate_lr) @[Arbiter.scala 23:71] + io.mem.invalidate_lr <= _T_1246 @[Arbiter.scala 23:26] + node _T_1247 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) @[Arbiter.scala 24:63] + io.mem.req.valid <= _T_1247 @[Arbiter.scala 24:22] + io.requestor[0].req.ready <= io.mem.req.ready @[Arbiter.scala 25:31] + node _T_1249 = eq(io.requestor[0].req.valid, UInt<1>("h00")) @[Arbiter.scala 27:67] + node _T_1250 = and(io.requestor[0].req.ready, _T_1249) @[Arbiter.scala 27:64] + io.requestor[1].req.ready <= _T_1250 @[Arbiter.scala 27:33] + io.mem.req.bits.cmd <= io.requestor[1].req.bits.cmd @[Arbiter.scala 32:29] + io.mem.req.bits.typ <= io.requestor[1].req.bits.typ @[Arbiter.scala 33:29] + io.mem.req.bits.addr <= io.requestor[1].req.bits.addr @[Arbiter.scala 34:30] + io.mem.req.bits.phys <= io.requestor[1].req.bits.phys @[Arbiter.scala 35:30] + node _T_1252 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01")) @[Cat.scala 30:58] + io.mem.req.bits.tag <= _T_1252 @[Arbiter.scala 36:29] + _T_1244 <= UInt<1>("h01") @[Arbiter.scala 37:15] + io.mem.s1_kill <= io.requestor[1].s1_kill @[Arbiter.scala 40:24] + io.mem.s1_data <= io.requestor[1].s1_data @[Arbiter.scala 41:24] + when io.requestor[0].req.valid : @[Arbiter.scala 48:26] + io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd @[Arbiter.scala 32:29] + io.mem.req.bits.typ <= io.requestor[0].req.bits.typ @[Arbiter.scala 33:29] + io.mem.req.bits.addr <= io.requestor[0].req.bits.addr @[Arbiter.scala 34:30] + io.mem.req.bits.phys <= io.requestor[0].req.bits.phys @[Arbiter.scala 35:30] + node _T_1255 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00")) @[Cat.scala 30:58] + io.mem.req.bits.tag <= _T_1255 @[Arbiter.scala 36:29] + _T_1244 <= UInt<1>("h00") @[Arbiter.scala 37:15] + skip @[Arbiter.scala 48:26] + node _T_1258 = eq(_T_1244, UInt<1>("h00")) @[Arbiter.scala 49:21] + when _T_1258 : @[Arbiter.scala 49:34] + io.mem.s1_kill <= io.requestor[0].s1_kill @[Arbiter.scala 40:24] + io.mem.s1_data <= io.requestor[0].s1_data @[Arbiter.scala 41:24] + skip @[Arbiter.scala 49:34] + node _T_1259 = bits(io.mem.resp.bits.tag, 0, 0) @[Arbiter.scala 55:41] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[Arbiter.scala 55:57] + node _T_1262 = and(io.mem.resp.valid, _T_1261) @[Arbiter.scala 56:39] + io.requestor[0].resp.valid <= _T_1262 @[Arbiter.scala 56:18] + io.requestor[0].xcpt <- io.mem.xcpt @[Arbiter.scala 57:28] + io.requestor[0].ordered <= io.mem.ordered @[Arbiter.scala 58:31] + io.requestor[0].acquire <= io.mem.acquire @[Arbiter.scala 59:31] + io.requestor[0].release <= io.mem.release @[Arbiter.scala 60:31] + node _T_1264 = eq(_T_1245, UInt<1>("h00")) @[Arbiter.scala 61:58] + node _T_1265 = and(io.mem.s2_nack, _T_1264) @[Arbiter.scala 61:49] + io.requestor[0].s2_nack <= _T_1265 @[Arbiter.scala 61:31] + io.requestor[0].resp.bits <- io.mem.resp.bits @[Arbiter.scala 62:17] + node _T_1266 = shr(io.mem.resp.bits.tag, 1) @[Arbiter.scala 63:45] + io.requestor[0].resp.bits.tag <= _T_1266 @[Arbiter.scala 63:21] + io.requestor[0].replay_next <= io.mem.replay_next @[Arbiter.scala 65:35] + node _T_1267 = bits(io.mem.resp.bits.tag, 0, 0) @[Arbiter.scala 55:41] + node _T_1269 = eq(_T_1267, UInt<1>("h01")) @[Arbiter.scala 55:57] + node _T_1270 = and(io.mem.resp.valid, _T_1269) @[Arbiter.scala 56:39] + io.requestor[1].resp.valid <= _T_1270 @[Arbiter.scala 56:18] + io.requestor[1].xcpt <- io.mem.xcpt @[Arbiter.scala 57:28] + io.requestor[1].ordered <= io.mem.ordered @[Arbiter.scala 58:31] + io.requestor[1].acquire <= io.mem.acquire @[Arbiter.scala 59:31] + io.requestor[1].release <= io.mem.release @[Arbiter.scala 60:31] + node _T_1272 = eq(_T_1245, UInt<1>("h01")) @[Arbiter.scala 61:58] + node _T_1273 = and(io.mem.s2_nack, _T_1272) @[Arbiter.scala 61:49] + io.requestor[1].s2_nack <= _T_1273 @[Arbiter.scala 61:31] + io.requestor[1].resp.bits <- io.mem.resp.bits @[Arbiter.scala 62:17] + node _T_1274 = shr(io.mem.resp.bits.tag, 1) @[Arbiter.scala 63:45] + io.requestor[1].resp.bits.tag <= _T_1274 @[Arbiter.scala 63:21] + io.requestor[1].replay_next <= io.mem.replay_next @[Arbiter.scala 65:35] + + module RRArbiter : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>} - - io is invalid - reg T_1318 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1320 : UInt, clk with : (reset => (reset, UInt<3>("h07"))) - wire T_1322 : UInt<3> - T_1322 is invalid - io.out.valid <= io.in[T_1322].valid - io.out.bits <- io.in[T_1322].bits - io.chosen <= T_1322 - io.in[T_1322].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_1498 = gt(UInt<1>("h00"), last_grant) - node T_1499 = and(io.in[0].valid, T_1498) - node T_1501 = gt(UInt<1>("h01"), last_grant) - node T_1502 = and(io.in[1].valid, T_1501) - node T_1504 = gt(UInt<2>("h02"), last_grant) - node T_1505 = and(io.in[2].valid, T_1504) - node T_1507 = gt(UInt<2>("h03"), last_grant) - node T_1508 = and(io.in[3].valid, T_1507) - node T_1510 = gt(UInt<3>("h04"), last_grant) - node T_1511 = and(io.in[4].valid, T_1510) - node T_1513 = gt(UInt<3>("h05"), last_grant) - node T_1514 = and(io.in[5].valid, T_1513) - node T_1516 = gt(UInt<3>("h06"), last_grant) - node T_1517 = and(io.in[6].valid, T_1516) - node T_1519 = gt(UInt<3>("h07"), last_grant) - node T_1520 = and(io.in[7].valid, T_1519) - node T_1523 = or(UInt<1>("h00"), T_1499) - node T_1525 = eq(T_1523, UInt<1>("h00")) - node T_1527 = or(UInt<1>("h00"), T_1499) - node T_1528 = or(T_1527, T_1502) - node T_1530 = eq(T_1528, UInt<1>("h00")) - node T_1532 = or(UInt<1>("h00"), T_1499) - node T_1533 = or(T_1532, T_1502) - node T_1534 = or(T_1533, T_1505) - node T_1536 = eq(T_1534, UInt<1>("h00")) - node T_1538 = or(UInt<1>("h00"), T_1499) - node T_1539 = or(T_1538, T_1502) - node T_1540 = or(T_1539, T_1505) - node T_1541 = or(T_1540, T_1508) - node T_1543 = eq(T_1541, UInt<1>("h00")) - node T_1545 = or(UInt<1>("h00"), T_1499) - node T_1546 = or(T_1545, T_1502) - node T_1547 = or(T_1546, T_1505) - node T_1548 = or(T_1547, T_1508) - node T_1549 = or(T_1548, T_1511) - node T_1551 = eq(T_1549, UInt<1>("h00")) - node T_1553 = or(UInt<1>("h00"), T_1499) - node T_1554 = or(T_1553, T_1502) - node T_1555 = or(T_1554, T_1505) - node T_1556 = or(T_1555, T_1508) - node T_1557 = or(T_1556, T_1511) - node T_1558 = or(T_1557, T_1514) - node T_1560 = eq(T_1558, UInt<1>("h00")) - node T_1562 = or(UInt<1>("h00"), T_1499) - node T_1563 = or(T_1562, T_1502) - node T_1564 = or(T_1563, T_1505) - node T_1565 = or(T_1564, T_1508) - node T_1566 = or(T_1565, T_1511) - node T_1567 = or(T_1566, T_1514) - node T_1568 = or(T_1567, T_1517) - node T_1570 = eq(T_1568, UInt<1>("h00")) - node T_1572 = or(UInt<1>("h00"), T_1499) - node T_1573 = or(T_1572, T_1502) - node T_1574 = or(T_1573, T_1505) - node T_1575 = or(T_1574, T_1508) - node T_1576 = or(T_1575, T_1511) - node T_1577 = or(T_1576, T_1514) - node T_1578 = or(T_1577, T_1517) - node T_1579 = or(T_1578, T_1520) - node T_1581 = eq(T_1579, UInt<1>("h00")) - node T_1583 = or(UInt<1>("h00"), T_1499) - node T_1584 = or(T_1583, T_1502) - node T_1585 = or(T_1584, T_1505) - node T_1586 = or(T_1585, T_1508) - node T_1587 = or(T_1586, T_1511) - node T_1588 = or(T_1587, T_1514) - node T_1589 = or(T_1588, T_1517) - node T_1590 = or(T_1589, T_1520) - node T_1591 = or(T_1590, io.in[0].valid) - node T_1593 = eq(T_1591, UInt<1>("h00")) - node T_1595 = or(UInt<1>("h00"), T_1499) - node T_1596 = or(T_1595, T_1502) - node T_1597 = or(T_1596, T_1505) - node T_1598 = or(T_1597, T_1508) - node T_1599 = or(T_1598, T_1511) - node T_1600 = or(T_1599, T_1514) - node T_1601 = or(T_1600, T_1517) - node T_1602 = or(T_1601, T_1520) - node T_1603 = or(T_1602, io.in[0].valid) - node T_1604 = or(T_1603, io.in[1].valid) - node T_1606 = eq(T_1604, UInt<1>("h00")) - node T_1608 = or(UInt<1>("h00"), T_1499) - node T_1609 = or(T_1608, T_1502) - node T_1610 = or(T_1609, T_1505) - node T_1611 = or(T_1610, T_1508) - node T_1612 = or(T_1611, T_1511) - node T_1613 = or(T_1612, T_1514) - node T_1614 = or(T_1613, T_1517) - node T_1615 = or(T_1614, T_1520) - node T_1616 = or(T_1615, io.in[0].valid) - node T_1617 = or(T_1616, io.in[1].valid) - node T_1618 = or(T_1617, io.in[2].valid) - node T_1620 = eq(T_1618, UInt<1>("h00")) - node T_1622 = or(UInt<1>("h00"), T_1499) - node T_1623 = or(T_1622, T_1502) - node T_1624 = or(T_1623, T_1505) - node T_1625 = or(T_1624, T_1508) - node T_1626 = or(T_1625, T_1511) - node T_1627 = or(T_1626, T_1514) - node T_1628 = or(T_1627, T_1517) - node T_1629 = or(T_1628, T_1520) - node T_1630 = or(T_1629, io.in[0].valid) - node T_1631 = or(T_1630, io.in[1].valid) - node T_1632 = or(T_1631, io.in[2].valid) - node T_1633 = or(T_1632, io.in[3].valid) - node T_1635 = eq(T_1633, UInt<1>("h00")) - node T_1637 = or(UInt<1>("h00"), T_1499) - node T_1638 = or(T_1637, T_1502) - node T_1639 = or(T_1638, T_1505) - node T_1640 = or(T_1639, T_1508) - node T_1641 = or(T_1640, T_1511) - node T_1642 = or(T_1641, T_1514) - node T_1643 = or(T_1642, T_1517) - node T_1644 = or(T_1643, T_1520) - node T_1645 = or(T_1644, io.in[0].valid) - node T_1646 = or(T_1645, io.in[1].valid) - node T_1647 = or(T_1646, io.in[2].valid) - node T_1648 = or(T_1647, io.in[3].valid) - node T_1649 = or(T_1648, io.in[4].valid) - node T_1651 = eq(T_1649, UInt<1>("h00")) - node T_1653 = or(UInt<1>("h00"), T_1499) - node T_1654 = or(T_1653, T_1502) - node T_1655 = or(T_1654, T_1505) - node T_1656 = or(T_1655, T_1508) - node T_1657 = or(T_1656, T_1511) - node T_1658 = or(T_1657, T_1514) - node T_1659 = or(T_1658, T_1517) - node T_1660 = or(T_1659, T_1520) - node T_1661 = or(T_1660, io.in[0].valid) - node T_1662 = or(T_1661, io.in[1].valid) - node T_1663 = or(T_1662, io.in[2].valid) - node T_1664 = or(T_1663, io.in[3].valid) - node T_1665 = or(T_1664, io.in[4].valid) - node T_1666 = or(T_1665, io.in[5].valid) - node T_1668 = eq(T_1666, UInt<1>("h00")) - node T_1670 = or(UInt<1>("h00"), T_1499) - node T_1671 = or(T_1670, T_1502) - node T_1672 = or(T_1671, T_1505) - node T_1673 = or(T_1672, T_1508) - node T_1674 = or(T_1673, T_1511) - node T_1675 = or(T_1674, T_1514) - node T_1676 = or(T_1675, T_1517) - node T_1677 = or(T_1676, T_1520) - node T_1678 = or(T_1677, io.in[0].valid) - node T_1679 = or(T_1678, io.in[1].valid) - node T_1680 = or(T_1679, io.in[2].valid) - node T_1681 = or(T_1680, io.in[3].valid) - node T_1682 = or(T_1681, io.in[4].valid) - node T_1683 = or(T_1682, io.in[5].valid) - node T_1684 = or(T_1683, io.in[6].valid) - node T_1686 = eq(T_1684, UInt<1>("h00")) - node T_1688 = gt(UInt<1>("h00"), last_grant) - node T_1689 = and(UInt<1>("h01"), T_1688) - node T_1690 = or(T_1689, T_1581) - node T_1692 = gt(UInt<1>("h01"), last_grant) - node T_1693 = and(T_1525, T_1692) - node T_1694 = or(T_1693, T_1593) - node T_1696 = gt(UInt<2>("h02"), last_grant) - node T_1697 = and(T_1530, T_1696) - node T_1698 = or(T_1697, T_1606) - node T_1700 = gt(UInt<2>("h03"), last_grant) - node T_1701 = and(T_1536, T_1700) - node T_1702 = or(T_1701, T_1620) - node T_1704 = gt(UInt<3>("h04"), last_grant) - node T_1705 = and(T_1543, T_1704) - node T_1706 = or(T_1705, T_1635) - node T_1708 = gt(UInt<3>("h05"), last_grant) - node T_1709 = and(T_1551, T_1708) - node T_1710 = or(T_1709, T_1651) - node T_1712 = gt(UInt<3>("h06"), last_grant) - node T_1713 = and(T_1560, T_1712) - node T_1714 = or(T_1713, T_1668) - node T_1716 = gt(UInt<3>("h07"), last_grant) - node T_1717 = and(T_1570, T_1716) - node T_1718 = or(T_1717, T_1686) - node T_1720 = eq(T_1320, UInt<1>("h00")) - node T_1721 = mux(T_1318, T_1720, T_1690) - node T_1722 = and(T_1721, io.out.ready) - io.in[0].ready <= T_1722 - node T_1724 = eq(T_1320, UInt<1>("h01")) - node T_1725 = mux(T_1318, T_1724, T_1694) - node T_1726 = and(T_1725, io.out.ready) - io.in[1].ready <= T_1726 - node T_1728 = eq(T_1320, UInt<2>("h02")) - node T_1729 = mux(T_1318, T_1728, T_1698) - node T_1730 = and(T_1729, io.out.ready) - io.in[2].ready <= T_1730 - node T_1732 = eq(T_1320, UInt<2>("h03")) - node T_1733 = mux(T_1318, T_1732, T_1702) - node T_1734 = and(T_1733, io.out.ready) - io.in[3].ready <= T_1734 - node T_1736 = eq(T_1320, UInt<3>("h04")) - node T_1737 = mux(T_1318, T_1736, T_1706) - node T_1738 = and(T_1737, io.out.ready) - io.in[4].ready <= T_1738 - node T_1740 = eq(T_1320, UInt<3>("h05")) - node T_1741 = mux(T_1318, T_1740, T_1710) - node T_1742 = and(T_1741, io.out.ready) - io.in[5].ready <= T_1742 - node T_1744 = eq(T_1320, UInt<3>("h06")) - node T_1745 = mux(T_1318, T_1744, T_1714) - node T_1746 = and(T_1745, io.out.ready) - io.in[6].ready <= T_1746 - node T_1748 = eq(T_1320, UInt<3>("h07")) - node T_1749 = mux(T_1318, T_1748, T_1718) - node T_1750 = and(T_1749, io.out.ready) - io.in[7].ready <= T_1750 - reg T_1752 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_1754 = add(T_1752, UInt<1>("h01")) - node T_1755 = tail(T_1754, 1) - node T_1756 = and(io.out.ready, io.out.valid) - when T_1756 : - when UInt<1>("h00") : - T_1752 <= T_1755 - node T_1759 = eq(T_1318, UInt<1>("h00")) - when T_1759 : - T_1318 <= UInt<1>("h01") - node T_1761 = and(io.in[0].ready, io.in[0].valid) - node T_1762 = and(io.in[1].ready, io.in[1].valid) - node T_1763 = and(io.in[2].ready, io.in[2].valid) - node T_1764 = and(io.in[3].ready, io.in[3].valid) - node T_1765 = and(io.in[4].ready, io.in[4].valid) - node T_1766 = and(io.in[5].ready, io.in[5].valid) - node T_1767 = and(io.in[6].ready, io.in[6].valid) - node T_1768 = and(io.in[7].ready, io.in[7].valid) - wire T_1770 : UInt<1>[8] - T_1770[0] <= T_1761 - T_1770[1] <= T_1762 - T_1770[2] <= T_1763 - T_1770[3] <= T_1764 - T_1770[4] <= T_1765 - T_1770[5] <= T_1766 - T_1770[6] <= T_1767 - T_1770[7] <= T_1768 - node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788) - node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789) - node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790) - node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791) - node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792) - node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793) - T_1320 <= T_1794 - skip - skip - node T_1796 = eq(T_1755, UInt<1>("h00")) - when T_1796 : - T_1318 <= UInt<1>("h00") - skip - skip - node T_1800 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_1802 = mux(io.in[5].valid, UInt<3>("h05"), T_1800) - node T_1804 = mux(io.in[4].valid, UInt<3>("h04"), T_1802) - node T_1806 = mux(io.in[3].valid, UInt<2>("h03"), T_1804) - node T_1808 = mux(io.in[2].valid, UInt<2>("h02"), T_1806) - node T_1810 = mux(io.in[1].valid, UInt<1>("h01"), T_1808) - node T_1812 = mux(io.in[0].valid, UInt<1>("h00"), T_1810) - node T_1814 = gt(UInt<3>("h07"), last_grant) - node T_1815 = and(io.in[7].valid, T_1814) - node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812) - node T_1819 = gt(UInt<3>("h06"), last_grant) - node T_1820 = and(io.in[6].valid, T_1819) - node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817) - node T_1824 = gt(UInt<3>("h05"), last_grant) - node T_1825 = and(io.in[5].valid, T_1824) - node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822) - node T_1829 = gt(UInt<3>("h04"), last_grant) - node T_1830 = and(io.in[4].valid, T_1829) - node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827) - node T_1834 = gt(UInt<2>("h03"), last_grant) - node T_1835 = and(io.in[3].valid, T_1834) - node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832) - node T_1839 = gt(UInt<2>("h02"), last_grant) - node T_1840 = and(io.in[2].valid, T_1839) - node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837) - node T_1844 = gt(UInt<1>("h01"), last_grant) - node T_1845 = and(io.in[1].valid, T_1844) - node choose = mux(T_1845, UInt<1>("h01"), T_1842) - node T_1848 = mux(T_1318, T_1320, choose) - T_1322 <= T_1848 - node T_1849 = and(io.out.ready, io.out.valid) - when T_1849 : - last_grant <= T_1322 - skip + output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} - module LockingRRArbiter_35 : - input clk : Clock + io is invalid + io is invalid + wire choice : UInt + choice is invalid + choice <= UInt<1>("h01") + io.chosen <= choice @[Arbiter.scala 40:13] + io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 41:16] + io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 42:15] + node _T_287 = and(io.out.ready, io.out.valid) @[Decoupled.scala 30:37] + reg lastGrant : UInt<1>, clock @[Reg.scala 34:16] + when _T_287 : @[Reg.scala 35:19] + lastGrant <= io.chosen @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 67:57] + node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 67:57] + node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 68:83] + node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 68:83] + node _T_291 = or(validMask_0, validMask_1) @[Arbiter.scala 31:68] + node _T_292 = or(_T_291, io.in[0].valid) @[Arbiter.scala 31:68] + node _T_294 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_296 = eq(_T_291, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_298 = eq(_T_292, UInt<1>("h00")) @[Arbiter.scala 31:78] + node _T_299 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 72:34] + node _T_300 = or(_T_299, _T_296) @[Arbiter.scala 72:50] + node _T_301 = and(_T_294, grantMask_1) @[Arbiter.scala 72:34] + node _T_302 = or(_T_301, _T_298) @[Arbiter.scala 72:50] + node _T_303 = and(_T_300, io.out.ready) @[Arbiter.scala 60:21] + io.in[0].ready <= _T_303 @[Arbiter.scala 60:16] + node _T_304 = and(_T_302, io.out.ready) @[Arbiter.scala 60:21] + io.in[1].ready <= _T_304 @[Arbiter.scala 60:16] + when io.in[0].valid : @[Arbiter.scala 77:27] + choice <= UInt<1>("h00") @[Arbiter.scala 77:36] + skip @[Arbiter.scala 77:27] + when validMask_1 : @[Arbiter.scala 79:25] + choice <= UInt<1>("h01") @[Arbiter.scala 79:34] + skip @[Arbiter.scala 79:25] + + module PTW : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, chosen : UInt<3>} - - io is invalid - reg T_444 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_446 : UInt, clk with : (reset => (reset, UInt<3>("h07"))) - wire T_448 : UInt<3> - T_448 is invalid - io.out.valid <= io.in[T_448].valid - io.out.bits <- io.in[T_448].bits - io.chosen <= T_448 - io.in[T_448].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_510 = gt(UInt<1>("h00"), last_grant) - node T_511 = and(io.in[0].valid, T_510) - node T_513 = gt(UInt<1>("h01"), last_grant) - node T_514 = and(io.in[1].valid, T_513) - node T_516 = gt(UInt<2>("h02"), last_grant) - node T_517 = and(io.in[2].valid, T_516) - node T_519 = gt(UInt<2>("h03"), last_grant) - node T_520 = and(io.in[3].valid, T_519) - node T_522 = gt(UInt<3>("h04"), last_grant) - node T_523 = and(io.in[4].valid, T_522) - node T_525 = gt(UInt<3>("h05"), last_grant) - node T_526 = and(io.in[5].valid, T_525) - node T_528 = gt(UInt<3>("h06"), last_grant) - node T_529 = and(io.in[6].valid, T_528) - node T_531 = gt(UInt<3>("h07"), last_grant) - node T_532 = and(io.in[7].valid, T_531) - node T_535 = or(UInt<1>("h00"), T_511) - node T_537 = eq(T_535, UInt<1>("h00")) - node T_539 = or(UInt<1>("h00"), T_511) - node T_540 = or(T_539, T_514) - node T_542 = eq(T_540, UInt<1>("h00")) - node T_544 = or(UInt<1>("h00"), T_511) - node T_545 = or(T_544, T_514) - node T_546 = or(T_545, T_517) - node T_548 = eq(T_546, UInt<1>("h00")) - node T_550 = or(UInt<1>("h00"), T_511) - node T_551 = or(T_550, T_514) - node T_552 = or(T_551, T_517) - node T_553 = or(T_552, T_520) - node T_555 = eq(T_553, UInt<1>("h00")) - node T_557 = or(UInt<1>("h00"), T_511) - node T_558 = or(T_557, T_514) - node T_559 = or(T_558, T_517) - node T_560 = or(T_559, T_520) - node T_561 = or(T_560, T_523) - node T_563 = eq(T_561, UInt<1>("h00")) - node T_565 = or(UInt<1>("h00"), T_511) - node T_566 = or(T_565, T_514) - node T_567 = or(T_566, T_517) - node T_568 = or(T_567, T_520) - node T_569 = or(T_568, T_523) - node T_570 = or(T_569, T_526) - node T_572 = eq(T_570, UInt<1>("h00")) - node T_574 = or(UInt<1>("h00"), T_511) - node T_575 = or(T_574, T_514) - node T_576 = or(T_575, T_517) - node T_577 = or(T_576, T_520) - node T_578 = or(T_577, T_523) - node T_579 = or(T_578, T_526) - node T_580 = or(T_579, T_529) - node T_582 = eq(T_580, UInt<1>("h00")) - node T_584 = or(UInt<1>("h00"), T_511) - node T_585 = or(T_584, T_514) - node T_586 = or(T_585, T_517) - node T_587 = or(T_586, T_520) - node T_588 = or(T_587, T_523) - node T_589 = or(T_588, T_526) - node T_590 = or(T_589, T_529) - node T_591 = or(T_590, T_532) - node T_593 = eq(T_591, UInt<1>("h00")) - node T_595 = or(UInt<1>("h00"), T_511) - node T_596 = or(T_595, T_514) - node T_597 = or(T_596, T_517) - node T_598 = or(T_597, T_520) - node T_599 = or(T_598, T_523) - node T_600 = or(T_599, T_526) - node T_601 = or(T_600, T_529) - node T_602 = or(T_601, T_532) - node T_603 = or(T_602, io.in[0].valid) - node T_605 = eq(T_603, UInt<1>("h00")) - node T_607 = or(UInt<1>("h00"), T_511) - node T_608 = or(T_607, T_514) - node T_609 = or(T_608, T_517) - node T_610 = or(T_609, T_520) - node T_611 = or(T_610, T_523) - node T_612 = or(T_611, T_526) - node T_613 = or(T_612, T_529) - node T_614 = or(T_613, T_532) - node T_615 = or(T_614, io.in[0].valid) - node T_616 = or(T_615, io.in[1].valid) - node T_618 = eq(T_616, UInt<1>("h00")) - node T_620 = or(UInt<1>("h00"), T_511) - node T_621 = or(T_620, T_514) - node T_622 = or(T_621, T_517) - node T_623 = or(T_622, T_520) - node T_624 = or(T_623, T_523) - node T_625 = or(T_624, T_526) - node T_626 = or(T_625, T_529) - node T_627 = or(T_626, T_532) - node T_628 = or(T_627, io.in[0].valid) - node T_629 = or(T_628, io.in[1].valid) - node T_630 = or(T_629, io.in[2].valid) - node T_632 = eq(T_630, UInt<1>("h00")) - node T_634 = or(UInt<1>("h00"), T_511) - node T_635 = or(T_634, T_514) - node T_636 = or(T_635, T_517) - node T_637 = or(T_636, T_520) - node T_638 = or(T_637, T_523) - node T_639 = or(T_638, T_526) - node T_640 = or(T_639, T_529) - node T_641 = or(T_640, T_532) - node T_642 = or(T_641, io.in[0].valid) - node T_643 = or(T_642, io.in[1].valid) - node T_644 = or(T_643, io.in[2].valid) - node T_645 = or(T_644, io.in[3].valid) - node T_647 = eq(T_645, UInt<1>("h00")) - node T_649 = or(UInt<1>("h00"), T_511) - node T_650 = or(T_649, T_514) - node T_651 = or(T_650, T_517) - node T_652 = or(T_651, T_520) - node T_653 = or(T_652, T_523) - node T_654 = or(T_653, T_526) - node T_655 = or(T_654, T_529) - node T_656 = or(T_655, T_532) - node T_657 = or(T_656, io.in[0].valid) - node T_658 = or(T_657, io.in[1].valid) - node T_659 = or(T_658, io.in[2].valid) - node T_660 = or(T_659, io.in[3].valid) - node T_661 = or(T_660, io.in[4].valid) - node T_663 = eq(T_661, UInt<1>("h00")) - node T_665 = or(UInt<1>("h00"), T_511) - node T_666 = or(T_665, T_514) - node T_667 = or(T_666, T_517) - node T_668 = or(T_667, T_520) - node T_669 = or(T_668, T_523) - node T_670 = or(T_669, T_526) - node T_671 = or(T_670, T_529) - node T_672 = or(T_671, T_532) - node T_673 = or(T_672, io.in[0].valid) - node T_674 = or(T_673, io.in[1].valid) - node T_675 = or(T_674, io.in[2].valid) - node T_676 = or(T_675, io.in[3].valid) - node T_677 = or(T_676, io.in[4].valid) - node T_678 = or(T_677, io.in[5].valid) - node T_680 = eq(T_678, UInt<1>("h00")) - node T_682 = or(UInt<1>("h00"), T_511) - node T_683 = or(T_682, T_514) - node T_684 = or(T_683, T_517) - node T_685 = or(T_684, T_520) - node T_686 = or(T_685, T_523) - node T_687 = or(T_686, T_526) - node T_688 = or(T_687, T_529) - node T_689 = or(T_688, T_532) - node T_690 = or(T_689, io.in[0].valid) - node T_691 = or(T_690, io.in[1].valid) - node T_692 = or(T_691, io.in[2].valid) - node T_693 = or(T_692, io.in[3].valid) - node T_694 = or(T_693, io.in[4].valid) - node T_695 = or(T_694, io.in[5].valid) - node T_696 = or(T_695, io.in[6].valid) - node T_698 = eq(T_696, UInt<1>("h00")) - node T_700 = gt(UInt<1>("h00"), last_grant) - node T_701 = and(UInt<1>("h01"), T_700) - node T_702 = or(T_701, T_593) - node T_704 = gt(UInt<1>("h01"), last_grant) - node T_705 = and(T_537, T_704) - node T_706 = or(T_705, T_605) - node T_708 = gt(UInt<2>("h02"), last_grant) - node T_709 = and(T_542, T_708) - node T_710 = or(T_709, T_618) - node T_712 = gt(UInt<2>("h03"), last_grant) - node T_713 = and(T_548, T_712) - node T_714 = or(T_713, T_632) - node T_716 = gt(UInt<3>("h04"), last_grant) - node T_717 = and(T_555, T_716) - node T_718 = or(T_717, T_647) - node T_720 = gt(UInt<3>("h05"), last_grant) - node T_721 = and(T_563, T_720) - node T_722 = or(T_721, T_663) - node T_724 = gt(UInt<3>("h06"), last_grant) - node T_725 = and(T_572, T_724) - node T_726 = or(T_725, T_680) - node T_728 = gt(UInt<3>("h07"), last_grant) - node T_729 = and(T_582, T_728) - node T_730 = or(T_729, T_698) - node T_732 = eq(T_446, UInt<1>("h00")) - node T_733 = mux(T_444, T_732, T_702) - node T_734 = and(T_733, io.out.ready) - io.in[0].ready <= T_734 - node T_736 = eq(T_446, UInt<1>("h01")) - node T_737 = mux(T_444, T_736, T_706) - node T_738 = and(T_737, io.out.ready) - io.in[1].ready <= T_738 - node T_740 = eq(T_446, UInt<2>("h02")) - node T_741 = mux(T_444, T_740, T_710) - node T_742 = and(T_741, io.out.ready) - io.in[2].ready <= T_742 - node T_744 = eq(T_446, UInt<2>("h03")) - node T_745 = mux(T_444, T_744, T_714) - node T_746 = and(T_745, io.out.ready) - io.in[3].ready <= T_746 - node T_748 = eq(T_446, UInt<3>("h04")) - node T_749 = mux(T_444, T_748, T_718) - node T_750 = and(T_749, io.out.ready) - io.in[4].ready <= T_750 - node T_752 = eq(T_446, UInt<3>("h05")) - node T_753 = mux(T_444, T_752, T_722) - node T_754 = and(T_753, io.out.ready) - io.in[5].ready <= T_754 - node T_756 = eq(T_446, UInt<3>("h06")) - node T_757 = mux(T_444, T_756, T_726) - node T_758 = and(T_757, io.out.ready) - io.in[6].ready <= T_758 - node T_760 = eq(T_446, UInt<3>("h07")) - node T_761 = mux(T_444, T_760, T_730) - node T_762 = and(T_761, io.out.ready) - io.in[7].ready <= T_762 - reg T_764 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_766 = add(T_764, UInt<1>("h01")) - node T_767 = tail(T_766, 1) - node T_768 = and(io.out.ready, io.out.valid) - when T_768 : - node T_770 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) - wire T_773 : UInt<3>[1] - T_773[0] <= UInt<3>("h03") - node T_776 = eq(T_773[0], io.out.bits.a_type) - node T_778 = or(UInt<1>("h00"), T_776) - node T_779 = and(T_770, T_778) - when T_779 : - T_764 <= T_767 - node T_781 = eq(T_444, UInt<1>("h00")) - when T_781 : - T_444 <= UInt<1>("h01") - node T_783 = and(io.in[0].ready, io.in[0].valid) - node T_784 = and(io.in[1].ready, io.in[1].valid) - node T_785 = and(io.in[2].ready, io.in[2].valid) - node T_786 = and(io.in[3].ready, io.in[3].valid) - node T_787 = and(io.in[4].ready, io.in[4].valid) - node T_788 = and(io.in[5].ready, io.in[5].valid) - node T_789 = and(io.in[6].ready, io.in[6].valid) - node T_790 = and(io.in[7].ready, io.in[7].valid) - wire T_792 : UInt<1>[8] - T_792[0] <= T_783 - T_792[1] <= T_784 - T_792[2] <= T_785 - T_792[3] <= T_786 - T_792[4] <= T_787 - T_792[5] <= T_788 - T_792[6] <= T_789 - T_792[7] <= T_790 - node T_810 = mux(T_792[6], UInt<3>("h06"), UInt<3>("h07")) - node T_811 = mux(T_792[5], UInt<3>("h05"), T_810) - node T_812 = mux(T_792[4], UInt<3>("h04"), T_811) - node T_813 = mux(T_792[3], UInt<2>("h03"), T_812) - node T_814 = mux(T_792[2], UInt<2>("h02"), T_813) - node T_815 = mux(T_792[1], UInt<1>("h01"), T_814) - node T_816 = mux(T_792[0], UInt<1>("h00"), T_815) - T_446 <= T_816 - skip - skip - node T_818 = eq(T_767, UInt<1>("h00")) - when T_818 : - T_444 <= UInt<1>("h00") - skip - skip - node T_822 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) - node T_824 = mux(io.in[5].valid, UInt<3>("h05"), T_822) - node T_826 = mux(io.in[4].valid, UInt<3>("h04"), T_824) - node T_828 = mux(io.in[3].valid, UInt<2>("h03"), T_826) - node T_830 = mux(io.in[2].valid, UInt<2>("h02"), T_828) - node T_832 = mux(io.in[1].valid, UInt<1>("h01"), T_830) - node T_834 = mux(io.in[0].valid, UInt<1>("h00"), T_832) - node T_836 = gt(UInt<3>("h07"), last_grant) - node T_837 = and(io.in[7].valid, T_836) - node T_839 = mux(T_837, UInt<3>("h07"), T_834) - node T_841 = gt(UInt<3>("h06"), last_grant) - node T_842 = and(io.in[6].valid, T_841) - node T_844 = mux(T_842, UInt<3>("h06"), T_839) - node T_846 = gt(UInt<3>("h05"), last_grant) - node T_847 = and(io.in[5].valid, T_846) - node T_849 = mux(T_847, UInt<3>("h05"), T_844) - node T_851 = gt(UInt<3>("h04"), last_grant) - node T_852 = and(io.in[4].valid, T_851) - node T_854 = mux(T_852, UInt<3>("h04"), T_849) - node T_856 = gt(UInt<2>("h03"), last_grant) - node T_857 = and(io.in[3].valid, T_856) - node T_859 = mux(T_857, UInt<2>("h03"), T_854) - node T_861 = gt(UInt<2>("h02"), last_grant) - node T_862 = and(io.in[2].valid, T_861) - node T_864 = mux(T_862, UInt<2>("h02"), T_859) - node T_866 = gt(UInt<1>("h01"), last_grant) - node T_867 = and(io.in[1].valid, T_866) - node choose = mux(T_867, UInt<1>("h01"), T_864) - node T_870 = mux(T_444, T_446, choose) - T_448 <= T_870 - node T_871 = and(io.out.ready, io.out.valid) - when T_871 : - last_grant <= T_448 - skip + output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>}}, flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} - module ClientUncachedTileLinkIOArbiter : - input clk : Clock + io is invalid + io is invalid + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[PTW.scala 75:18] + reg count : UInt<2>, clock @[PTW.scala 76:18] + reg s1_kill : UInt<1>, clock @[PTW.scala 77:20] + s1_kill <= UInt<1>("h00") @[PTW.scala 77:20] + reg resp_valid : UInt<1>, clock @[PTW.scala 78:23] + resp_valid <= UInt<1>("h00") @[PTW.scala 78:23] + reg r_req : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}, clock @[PTW.scala 80:18] + reg r_req_dest : UInt, clock @[PTW.scala 81:23] + reg r_pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock @[PTW.scala 82:18] + node _T_1881 = shr(r_req.addr, 18) @[PTW.scala 84:58] + node vpn_idxs_0 = bits(_T_1881, 8, 0) @[PTW.scala 84:88] + node _T_1882 = shr(r_req.addr, 9) @[PTW.scala 84:58] + node vpn_idxs_1 = bits(_T_1882, 8, 0) @[PTW.scala 84:88] + node _T_1883 = shr(r_req.addr, 0) @[PTW.scala 84:58] + node vpn_idxs_2 = bits(_T_1883, 8, 0) @[PTW.scala 84:88] + node _T_1885 = and(count, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1887 = geq(count, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1889 = and(_T_1885, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1891 = geq(_T_1885, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1892 = mux(_T_1891, vpn_idxs_1, vpn_idxs_0) @[Package.scala 19:12] + node vpn_idx = mux(_T_1887, vpn_idxs_2, _T_1892) @[Package.scala 19:12] + inst arb of RRArbiter @[PTW.scala 87:19] + arb.io is invalid + arb.clock <= clock + arb.reset <= reset + arb.io.in[0] <- io.requestor[0].req @[PTW.scala 88:13] + arb.io.in[1] <- io.requestor[1].req @[PTW.scala 88:13] + node _T_1900 = eq(state, UInt<2>("h00")) @[PTW.scala 89:29] + arb.io.out.ready <= _T_1900 @[PTW.scala 89:20] + wire _T_1923 : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[PTW.scala 92:33] + _T_1923 is invalid @[PTW.scala 92:33] + wire _T_1935 : UInt<64> + _T_1935 is invalid + _T_1935 <= io.mem.resp.bits.data + node _T_1936 = bits(_T_1935, 0, 0) @[PTW.scala 92:33] + _T_1923.v <= _T_1936 @[PTW.scala 92:33] + node _T_1937 = bits(_T_1935, 1, 1) @[PTW.scala 92:33] + _T_1923.r <= _T_1937 @[PTW.scala 92:33] + node _T_1938 = bits(_T_1935, 2, 2) @[PTW.scala 92:33] + _T_1923.w <= _T_1938 @[PTW.scala 92:33] + node _T_1939 = bits(_T_1935, 3, 3) @[PTW.scala 92:33] + _T_1923.x <= _T_1939 @[PTW.scala 92:33] + node _T_1940 = bits(_T_1935, 4, 4) @[PTW.scala 92:33] + _T_1923.u <= _T_1940 @[PTW.scala 92:33] + node _T_1941 = bits(_T_1935, 5, 5) @[PTW.scala 92:33] + _T_1923.g <= _T_1941 @[PTW.scala 92:33] + node _T_1942 = bits(_T_1935, 6, 6) @[PTW.scala 92:33] + _T_1923.a <= _T_1942 @[PTW.scala 92:33] + node _T_1943 = bits(_T_1935, 7, 7) @[PTW.scala 92:33] + _T_1923.d <= _T_1943 @[PTW.scala 92:33] + node _T_1944 = bits(_T_1935, 9, 8) @[PTW.scala 92:33] + _T_1923.reserved_for_software <= _T_1944 @[PTW.scala 92:33] + node _T_1945 = bits(_T_1935, 63, 10) @[PTW.scala 92:33] + _T_1923.ppn <= _T_1945 @[PTW.scala 92:33] + wire _T_1968 : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[PTW.scala 93:45] + _T_1968 is invalid @[PTW.scala 93:45] + wire _T_1980 : UInt<64> + _T_1980 is invalid + _T_1980 <= io.mem.resp.bits.data + node _T_1981 = bits(_T_1980, 0, 0) @[PTW.scala 93:45] + _T_1968.v <= _T_1981 @[PTW.scala 93:45] + node _T_1982 = bits(_T_1980, 1, 1) @[PTW.scala 93:45] + _T_1968.r <= _T_1982 @[PTW.scala 93:45] + node _T_1983 = bits(_T_1980, 2, 2) @[PTW.scala 93:45] + _T_1968.w <= _T_1983 @[PTW.scala 93:45] + node _T_1984 = bits(_T_1980, 3, 3) @[PTW.scala 93:45] + _T_1968.x <= _T_1984 @[PTW.scala 93:45] + node _T_1985 = bits(_T_1980, 4, 4) @[PTW.scala 93:45] + _T_1968.u <= _T_1985 @[PTW.scala 93:45] + node _T_1986 = bits(_T_1980, 5, 5) @[PTW.scala 93:45] + _T_1968.g <= _T_1986 @[PTW.scala 93:45] + node _T_1987 = bits(_T_1980, 6, 6) @[PTW.scala 93:45] + _T_1968.a <= _T_1987 @[PTW.scala 93:45] + node _T_1988 = bits(_T_1980, 7, 7) @[PTW.scala 93:45] + _T_1968.d <= _T_1988 @[PTW.scala 93:45] + node _T_1989 = bits(_T_1980, 9, 8) @[PTW.scala 93:45] + _T_1968.reserved_for_software <= _T_1989 @[PTW.scala 93:45] + node _T_1990 = bits(_T_1980, 63, 10) @[PTW.scala 93:45] + _T_1968.ppn <= _T_1990 @[PTW.scala 93:45] + wire pte : {ppn : UInt<54>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + pte is invalid + pte <- _T_1968 + node _T_2001 = bits(_T_1923.ppn, 19, 0) @[PTW.scala 94:23] + pte.ppn <= _T_2001 @[PTW.scala 94:13] + node _T_2002 = shr(_T_1923.ppn, 20) @[PTW.scala 95:20] + node _T_2004 = neq(_T_2002, UInt<1>("h00")) @[PTW.scala 95:32] + when _T_2004 : @[PTW.scala 95:39] + pte.v <= UInt<1>("h00") @[PTW.scala 95:47] + skip @[PTW.scala 95:39] + node _T_2006 = cat(r_pte.ppn, vpn_idx) @[Cat.scala 30:58] + node pte_addr = shl(_T_2006, 3) @[PTW.scala 98:42] + node _T_2007 = and(arb.io.out.ready, arb.io.out.valid) @[Decoupled.scala 30:37] + when _T_2007 : @[PTW.scala 100:28] + r_req <- arb.io.out.bits @[PTW.scala 101:11] + r_req_dest <= arb.io.chosen @[PTW.scala 102:16] + r_pte.ppn <= io.dpath.ptbr.ppn @[PTW.scala 103:15] + skip @[PTW.scala 100:28] + reg _T_2009 : UInt<8>, clock @[Replacement.scala 42:22] + reg _T_2011 : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[PTW.scala 109:20] + reg _T_2015 : UInt<32>[8], clock @[PTW.scala 110:19] + reg _T_2029 : UInt<20>[8], clock @[PTW.scala 111:19] + node _T_2040 = eq(_T_2015[0], pte_addr) @[PTW.scala 113:27] + node _T_2041 = eq(_T_2015[1], pte_addr) @[PTW.scala 113:27] + node _T_2042 = eq(_T_2015[2], pte_addr) @[PTW.scala 113:27] + node _T_2043 = eq(_T_2015[3], pte_addr) @[PTW.scala 113:27] + node _T_2044 = eq(_T_2015[4], pte_addr) @[PTW.scala 113:27] + node _T_2045 = eq(_T_2015[5], pte_addr) @[PTW.scala 113:27] + node _T_2046 = eq(_T_2015[6], pte_addr) @[PTW.scala 113:27] + node _T_2047 = eq(_T_2015[7], pte_addr) @[PTW.scala 113:27] + node _T_2048 = cat(_T_2041, _T_2040) @[Cat.scala 30:58] + node _T_2049 = cat(_T_2043, _T_2042) @[Cat.scala 30:58] + node _T_2050 = cat(_T_2049, _T_2048) @[Cat.scala 30:58] + node _T_2051 = cat(_T_2045, _T_2044) @[Cat.scala 30:58] + node _T_2052 = cat(_T_2047, _T_2046) @[Cat.scala 30:58] + node _T_2053 = cat(_T_2052, _T_2051) @[Cat.scala 30:58] + node _T_2054 = cat(_T_2053, _T_2050) @[Cat.scala 30:58] + node _T_2055 = and(_T_2054, _T_2011) @[PTW.scala 113:48] + node _T_2057 = neq(_T_2055, UInt<1>("h00")) @[PTW.scala 114:20] + node _T_2059 = eq(pte.r, UInt<1>("h00")) @[PTW.scala 55:36] + node _T_2060 = and(pte.v, _T_2059) @[PTW.scala 55:33] + node _T_2062 = eq(pte.w, UInt<1>("h00")) @[PTW.scala 55:42] + node _T_2063 = and(_T_2060, _T_2062) @[PTW.scala 55:39] + node _T_2065 = eq(pte.x, UInt<1>("h00")) @[PTW.scala 55:48] + node _T_2066 = and(_T_2063, _T_2065) @[PTW.scala 55:45] + node _T_2067 = and(io.mem.resp.valid, _T_2066) @[PTW.scala 115:29] + node _T_2069 = eq(_T_2057, UInt<1>("h00")) @[PTW.scala 115:47] + node _T_2070 = and(_T_2067, _T_2069) @[PTW.scala 115:44] + when _T_2070 : @[PTW.scala 115:53] + node _T_2071 = not(_T_2011) @[PTW.scala 116:25] + node _T_2073 = eq(_T_2071, UInt<1>("h00")) @[PTW.scala 116:25] + node _T_2075 = dshr(_T_2009, UInt<1>("h01")) @[Replacement.scala 60:27] + node _T_2076 = bits(_T_2075, 0, 0) @[Replacement.scala 60:27] + node _T_2077 = cat(UInt<1>("h01"), _T_2076) @[Cat.scala 30:58] + node _T_2078 = dshr(_T_2009, _T_2077) @[Replacement.scala 60:27] + node _T_2079 = bits(_T_2078, 0, 0) @[Replacement.scala 60:27] + node _T_2080 = cat(_T_2077, _T_2079) @[Cat.scala 30:58] + node _T_2081 = dshr(_T_2009, _T_2080) @[Replacement.scala 60:27] + node _T_2082 = bits(_T_2081, 0, 0) @[Replacement.scala 60:27] + node _T_2083 = cat(_T_2080, _T_2082) @[Cat.scala 30:58] + node _T_2084 = bits(_T_2083, 2, 0) @[Replacement.scala 61:8] + node _T_2085 = not(_T_2011) @[PTW.scala 116:61] + node _T_2086 = bits(_T_2085, 0, 0) @[OneHot.scala 39:40] + node _T_2087 = bits(_T_2085, 1, 1) @[OneHot.scala 39:40] + node _T_2088 = bits(_T_2085, 2, 2) @[OneHot.scala 39:40] + node _T_2089 = bits(_T_2085, 3, 3) @[OneHot.scala 39:40] + node _T_2090 = bits(_T_2085, 4, 4) @[OneHot.scala 39:40] + node _T_2091 = bits(_T_2085, 5, 5) @[OneHot.scala 39:40] + node _T_2092 = bits(_T_2085, 6, 6) @[OneHot.scala 39:40] + node _T_2093 = bits(_T_2085, 7, 7) @[OneHot.scala 39:40] + node _T_2102 = mux(_T_2092, UInt<3>("h06"), UInt<3>("h07")) @[Mux.scala 31:69] + node _T_2103 = mux(_T_2091, UInt<3>("h05"), _T_2102) @[Mux.scala 31:69] + node _T_2104 = mux(_T_2090, UInt<3>("h04"), _T_2103) @[Mux.scala 31:69] + node _T_2105 = mux(_T_2089, UInt<2>("h03"), _T_2104) @[Mux.scala 31:69] + node _T_2106 = mux(_T_2088, UInt<2>("h02"), _T_2105) @[Mux.scala 31:69] + node _T_2107 = mux(_T_2087, UInt<1>("h01"), _T_2106) @[Mux.scala 31:69] + node _T_2108 = mux(_T_2086, UInt<1>("h00"), _T_2107) @[Mux.scala 31:69] + node _T_2109 = mux(_T_2073, _T_2084, _T_2108) @[PTW.scala 116:18] + node _T_2111 = dshl(UInt<1>("h01"), _T_2109) @[OneHot.scala 47:11] + node _T_2112 = or(_T_2011, _T_2111) @[PTW.scala 117:22] + _T_2011 <= _T_2112 @[PTW.scala 117:13] + _T_2015[_T_2109] <= pte_addr @[PTW.scala 118:15] + _T_2029[_T_2109] <= pte.ppn @[PTW.scala 119:15] + skip @[PTW.scala 115:53] + node _T_2115 = eq(state, UInt<2>("h01")) @[PTW.scala 121:24] + node _T_2116 = and(_T_2057, _T_2115) @[PTW.scala 121:15] + when _T_2116 : @[PTW.scala 121:35] + node _T_2117 = bits(_T_2055, 7, 4) @[OneHot.scala 26:18] + node _T_2118 = bits(_T_2055, 3, 0) @[OneHot.scala 27:18] + node _T_2120 = neq(_T_2117, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_2121 = or(_T_2117, _T_2118) @[OneHot.scala 28:28] + node _T_2122 = bits(_T_2121, 3, 2) @[OneHot.scala 26:18] + node _T_2123 = bits(_T_2121, 1, 0) @[OneHot.scala 27:18] + node _T_2125 = neq(_T_2122, UInt<1>("h00")) @[OneHot.scala 28:14] + node _T_2126 = or(_T_2122, _T_2123) @[OneHot.scala 28:28] + node _T_2127 = bits(_T_2126, 1, 1) @[CircuitMath.scala 30:8] + node _T_2128 = cat(_T_2125, _T_2127) @[Cat.scala 30:58] + node _T_2129 = cat(_T_2120, _T_2128) @[Cat.scala 30:58] + node _T_2131 = bits(_T_2129, 2, 2) @[Replacement.scala 50:20] + node _T_2133 = eq(_T_2131, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_2135 = dshl(UInt<1>("h01"), UInt<1>("h01")) @[Replacement.scala 51:37] + node _T_2136 = or(_T_2009, _T_2135) @[Replacement.scala 51:37] + node _T_2137 = not(_T_2009) @[Replacement.scala 51:37] + node _T_2138 = or(_T_2137, _T_2135) @[Replacement.scala 51:37] + node _T_2139 = not(_T_2138) @[Replacement.scala 51:37] + node _T_2140 = mux(_T_2133, _T_2136, _T_2139) @[Replacement.scala 51:37] + node _T_2141 = cat(UInt<1>("h01"), _T_2131) @[Cat.scala 30:58] + node _T_2142 = bits(_T_2129, 1, 1) @[Replacement.scala 50:20] + node _T_2144 = eq(_T_2142, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_2146 = dshl(UInt<1>("h01"), _T_2141) @[Replacement.scala 51:37] + node _T_2147 = or(_T_2140, _T_2146) @[Replacement.scala 51:37] + node _T_2148 = not(_T_2140) @[Replacement.scala 51:37] + node _T_2149 = or(_T_2148, _T_2146) @[Replacement.scala 51:37] + node _T_2150 = not(_T_2149) @[Replacement.scala 51:37] + node _T_2151 = mux(_T_2144, _T_2147, _T_2150) @[Replacement.scala 51:37] + node _T_2152 = cat(_T_2141, _T_2142) @[Cat.scala 30:58] + node _T_2153 = bits(_T_2129, 0, 0) @[Replacement.scala 50:20] + node _T_2155 = eq(_T_2153, UInt<1>("h00")) @[Replacement.scala 51:43] + node _T_2157 = dshl(UInt<1>("h01"), _T_2152) @[Replacement.scala 51:37] + node _T_2158 = or(_T_2151, _T_2157) @[Replacement.scala 51:37] + node _T_2159 = not(_T_2151) @[Replacement.scala 51:37] + node _T_2160 = or(_T_2159, _T_2157) @[Replacement.scala 51:37] + node _T_2161 = not(_T_2160) @[Replacement.scala 51:37] + node _T_2162 = mux(_T_2155, _T_2158, _T_2161) @[Replacement.scala 51:37] + node _T_2163 = cat(_T_2152, _T_2153) @[Cat.scala 30:58] + _T_2009 <= _T_2162 @[Replacement.scala 44:15] + skip @[PTW.scala 121:35] + when io.dpath.invalidate : @[PTW.scala 122:32] + _T_2011 <= UInt<1>("h00") @[PTW.scala 122:40] + skip @[PTW.scala 122:32] + node _T_2166 = lt(count, UInt<2>("h02")) @[PTW.scala 124:19] + node pte_cache_hit = and(_T_2057, _T_2166) @[PTW.scala 124:10] + node _T_2167 = bits(_T_2055, 0, 0) @[Mux.scala 21:36] + node _T_2168 = bits(_T_2055, 1, 1) @[Mux.scala 21:36] + node _T_2169 = bits(_T_2055, 2, 2) @[Mux.scala 21:36] + node _T_2170 = bits(_T_2055, 3, 3) @[Mux.scala 21:36] + node _T_2171 = bits(_T_2055, 4, 4) @[Mux.scala 21:36] + node _T_2172 = bits(_T_2055, 5, 5) @[Mux.scala 21:36] + node _T_2173 = bits(_T_2055, 6, 6) @[Mux.scala 21:36] + node _T_2174 = bits(_T_2055, 7, 7) @[Mux.scala 21:36] + node _T_2176 = mux(_T_2167, _T_2029[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2178 = mux(_T_2168, _T_2029[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2180 = mux(_T_2169, _T_2029[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2182 = mux(_T_2170, _T_2029[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2184 = mux(_T_2171, _T_2029[4], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2186 = mux(_T_2172, _T_2029[5], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2188 = mux(_T_2173, _T_2029[6], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2190 = mux(_T_2174, _T_2029[7], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2192 = or(_T_2176, _T_2178) @[Mux.scala 19:72] + node _T_2193 = or(_T_2192, _T_2180) @[Mux.scala 19:72] + node _T_2194 = or(_T_2193, _T_2182) @[Mux.scala 19:72] + node _T_2195 = or(_T_2194, _T_2184) @[Mux.scala 19:72] + node _T_2196 = or(_T_2195, _T_2186) @[Mux.scala 19:72] + node _T_2197 = or(_T_2196, _T_2188) @[Mux.scala 19:72] + node _T_2198 = or(_T_2197, _T_2190) @[Mux.scala 19:72] + wire pte_cache_data : UInt<20> @[Mux.scala 19:72] + pte_cache_data is invalid @[Mux.scala 19:72] + pte_cache_data <= _T_2198 @[Mux.scala 19:72] + node _T_2200 = eq(state, UInt<2>("h01")) @[PTW.scala 127:33] + io.mem.req.valid <= _T_2200 @[PTW.scala 127:24] + io.mem.req.bits.phys <= UInt<1>("h01") @[PTW.scala 128:24] + io.mem.req.bits.cmd <= UInt<1>("h00") @[PTW.scala 129:24] + io.mem.req.bits.typ <= UInt<2>("h03") @[PTW.scala 130:24] + io.mem.req.bits.addr <= pte_addr @[PTW.scala 131:24] + io.mem.s1_kill <= s1_kill @[PTW.scala 132:18] + io.mem.invalidate_lr <= UInt<1>("h00") @[PTW.scala 133:24] + node _T_2206 = eq(r_req_dest, UInt<1>("h00")) @[PTW.scala 136:61] + node _T_2207 = and(resp_valid, _T_2206) @[PTW.scala 136:46] + io.requestor[0].resp.valid <= _T_2207 @[PTW.scala 136:32] + io.requestor[0].resp.bits.pte <- r_pte @[PTW.scala 137:35] + io.requestor[0].resp.bits.level <= count @[PTW.scala 138:37] + node _T_2208 = shr(pte_addr, 12) @[PTW.scala 139:51] + io.requestor[0].resp.bits.pte.ppn <= _T_2208 @[PTW.scala 139:39] + io.requestor[0].ptbr <- io.dpath.ptbr @[PTW.scala 140:26] + io.requestor[0].invalidate <= io.dpath.invalidate @[PTW.scala 141:32] + io.requestor[0].status <- io.dpath.status @[PTW.scala 142:28] + node _T_2210 = eq(r_req_dest, UInt<1>("h01")) @[PTW.scala 136:61] + node _T_2211 = and(resp_valid, _T_2210) @[PTW.scala 136:46] + io.requestor[1].resp.valid <= _T_2211 @[PTW.scala 136:32] + io.requestor[1].resp.bits.pte <- r_pte @[PTW.scala 137:35] + io.requestor[1].resp.bits.level <= count @[PTW.scala 138:37] + node _T_2212 = shr(pte_addr, 12) @[PTW.scala 139:51] + io.requestor[1].resp.bits.pte.ppn <= _T_2212 @[PTW.scala 139:39] + io.requestor[1].ptbr <- io.dpath.ptbr @[PTW.scala 140:26] + io.requestor[1].invalidate <= io.dpath.invalidate @[PTW.scala 141:32] + io.requestor[1].status <- io.dpath.status @[PTW.scala 142:28] + node _T_2213 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_2213 : @[Conditional.scala 29:59] + when arb.io.out.valid : @[PTW.scala 148:31] + state <= UInt<2>("h01") @[PTW.scala 149:15] + skip @[PTW.scala 148:31] + count <= UInt<1>("h00") @[PTW.scala 151:13] + skip @[Conditional.scala 29:59] + node _T_2215 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_2215 : @[Conditional.scala 29:59] + when pte_cache_hit : @[PTW.scala 154:28] + s1_kill <= UInt<1>("h01") @[PTW.scala 155:17] + state <= UInt<2>("h01") @[PTW.scala 156:15] + node _T_2218 = add(count, UInt<1>("h01")) @[PTW.scala 157:24] + node _T_2219 = tail(_T_2218, 1) @[PTW.scala 157:24] + count <= _T_2219 @[PTW.scala 157:15] + r_pte.ppn <= pte_cache_data @[PTW.scala 158:19] + skip @[PTW.scala 154:28] + node _T_2221 = eq(pte_cache_hit, UInt<1>("h00")) @[PTW.scala 154:28] + node _T_2222 = and(_T_2221, io.mem.req.ready) @[PTW.scala 159:37] + when _T_2222 : @[PTW.scala 159:37] + state <= UInt<2>("h02") @[PTW.scala 160:15] + skip @[PTW.scala 159:37] + skip @[Conditional.scala 29:59] + node _T_2223 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_2223 : @[Conditional.scala 29:59] + state <= UInt<2>("h03") @[PTW.scala 164:13] + when io.mem.xcpt.pf.ld : @[PTW.scala 165:32] + r_pte.v <= UInt<1>("h00") @[PTW.scala 166:17] + state <= UInt<2>("h00") @[PTW.scala 167:15] + resp_valid <= UInt<1>("h01") @[PTW.scala 168:20] + skip @[PTW.scala 165:32] + skip @[Conditional.scala 29:59] + node _T_2226 = eq(UInt<2>("h03"), state) @[Conditional.scala 29:28] + when _T_2226 : @[Conditional.scala 29:59] + when io.mem.s2_nack : @[PTW.scala 172:29] + state <= UInt<2>("h01") @[PTW.scala 173:15] + skip @[PTW.scala 172:29] + when io.mem.resp.valid : @[PTW.scala 175:32] + r_pte <- pte @[PTW.scala 176:15] + node _T_2228 = eq(pte.r, UInt<1>("h00")) @[PTW.scala 55:36] + node _T_2229 = and(pte.v, _T_2228) @[PTW.scala 55:33] + node _T_2231 = eq(pte.w, UInt<1>("h00")) @[PTW.scala 55:42] + node _T_2232 = and(_T_2229, _T_2231) @[PTW.scala 55:39] + node _T_2234 = eq(pte.x, UInt<1>("h00")) @[PTW.scala 55:48] + node _T_2235 = and(_T_2232, _T_2234) @[PTW.scala 55:45] + node _T_2237 = lt(count, UInt<2>("h02")) @[PTW.scala 177:36] + node _T_2238 = and(_T_2235, _T_2237) @[PTW.scala 177:27] + when _T_2238 : @[PTW.scala 177:50] + state <= UInt<2>("h01") @[PTW.scala 178:17] + node _T_2240 = add(count, UInt<1>("h01")) @[PTW.scala 179:26] + node _T_2241 = tail(_T_2240, 1) @[PTW.scala 179:26] + count <= _T_2241 @[PTW.scala 179:17] + skip @[PTW.scala 177:50] + node _T_2243 = eq(_T_2238, UInt<1>("h00")) @[PTW.scala 177:50] + when _T_2243 : @[PTW.scala 180:21] + state <= UInt<2>("h00") @[PTW.scala 181:17] + resp_valid <= UInt<1>("h01") @[PTW.scala 182:22] + skip @[PTW.scala 180:21] + skip @[PTW.scala 175:32] + skip @[Conditional.scala 29:59] + + module RVCExpander : + input clock : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}} - - io is invalid - inst T_1593 of LockingRRArbiter_35 - T_1593.io is invalid - T_1593.clk <= clk - T_1593.reset <= reset - T_1593.io.in[0].valid <= io.in[0].acquire.valid - T_1593.io.in[0].bits <- io.in[0].acquire.bits - node T_1595 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) - T_1593.io.in[0].bits.client_xact_id <= T_1595 - io.in[0].acquire.ready <= T_1593.io.in[0].ready - T_1593.io.in[1].valid <= io.in[1].acquire.valid - T_1593.io.in[1].bits <- io.in[1].acquire.bits - node T_1597 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) - T_1593.io.in[1].bits.client_xact_id <= T_1597 - io.in[1].acquire.ready <= T_1593.io.in[1].ready - T_1593.io.in[2].valid <= io.in[2].acquire.valid - T_1593.io.in[2].bits <- io.in[2].acquire.bits - node T_1599 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) - T_1593.io.in[2].bits.client_xact_id <= T_1599 - io.in[2].acquire.ready <= T_1593.io.in[2].ready - T_1593.io.in[3].valid <= io.in[3].acquire.valid - T_1593.io.in[3].bits <- io.in[3].acquire.bits - node T_1601 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) - T_1593.io.in[3].bits.client_xact_id <= T_1601 - io.in[3].acquire.ready <= T_1593.io.in[3].ready - T_1593.io.in[4].valid <= io.in[4].acquire.valid - T_1593.io.in[4].bits <- io.in[4].acquire.bits - node T_1603 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) - T_1593.io.in[4].bits.client_xact_id <= T_1603 - io.in[4].acquire.ready <= T_1593.io.in[4].ready - T_1593.io.in[5].valid <= io.in[5].acquire.valid - T_1593.io.in[5].bits <- io.in[5].acquire.bits - node T_1605 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) - T_1593.io.in[5].bits.client_xact_id <= T_1605 - io.in[5].acquire.ready <= T_1593.io.in[5].ready - T_1593.io.in[6].valid <= io.in[6].acquire.valid - T_1593.io.in[6].bits <- io.in[6].acquire.bits - node T_1607 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) - T_1593.io.in[6].bits.client_xact_id <= T_1607 - io.in[6].acquire.ready <= T_1593.io.in[6].ready - T_1593.io.in[7].valid <= io.in[7].acquire.valid - T_1593.io.in[7].bits <- io.in[7].acquire.bits - node T_1609 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) - T_1593.io.in[7].bits.client_xact_id <= T_1609 - io.in[7].acquire.ready <= T_1593.io.in[7].ready - io.out.acquire <- T_1593.io.out - io.out.grant.ready <= UInt<1>("h00") - io.in[0].grant.valid <= UInt<1>("h00") - node T_1612 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1614 = eq(T_1612, UInt<1>("h00")) - when T_1614 : - io.in[0].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[0].grant.ready - skip - io.in[0].grant.bits <- io.out.grant.bits - node T_1615 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[0].grant.bits.client_xact_id <= T_1615 - io.in[1].grant.valid <= UInt<1>("h00") - node T_1617 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1619 = eq(T_1617, UInt<1>("h01")) - when T_1619 : - io.in[1].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[1].grant.ready - skip - io.in[1].grant.bits <- io.out.grant.bits - node T_1620 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[1].grant.bits.client_xact_id <= T_1620 - io.in[2].grant.valid <= UInt<1>("h00") - node T_1622 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1624 = eq(T_1622, UInt<2>("h02")) - when T_1624 : - io.in[2].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[2].grant.ready - skip - io.in[2].grant.bits <- io.out.grant.bits - node T_1625 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[2].grant.bits.client_xact_id <= T_1625 - io.in[3].grant.valid <= UInt<1>("h00") - node T_1627 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1629 = eq(T_1627, UInt<2>("h03")) - when T_1629 : - io.in[3].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[3].grant.ready - skip - io.in[3].grant.bits <- io.out.grant.bits - node T_1630 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[3].grant.bits.client_xact_id <= T_1630 - io.in[4].grant.valid <= UInt<1>("h00") - node T_1632 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1634 = eq(T_1632, UInt<3>("h04")) - when T_1634 : - io.in[4].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[4].grant.ready - skip - io.in[4].grant.bits <- io.out.grant.bits - node T_1635 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[4].grant.bits.client_xact_id <= T_1635 - io.in[5].grant.valid <= UInt<1>("h00") - node T_1637 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1639 = eq(T_1637, UInt<3>("h05")) - when T_1639 : - io.in[5].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[5].grant.ready - skip - io.in[5].grant.bits <- io.out.grant.bits - node T_1640 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[5].grant.bits.client_xact_id <= T_1640 - io.in[6].grant.valid <= UInt<1>("h00") - node T_1642 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1644 = eq(T_1642, UInt<3>("h06")) - when T_1644 : - io.in[6].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[6].grant.ready - skip - io.in[6].grant.bits <- io.out.grant.bits - node T_1645 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[6].grant.bits.client_xact_id <= T_1645 - io.in[7].grant.valid <= UInt<1>("h00") - node T_1647 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1649 = eq(T_1647, UInt<3>("h07")) - when T_1649 : - io.in[7].grant.valid <= io.out.grant.valid - io.out.grant.ready <= io.in[7].grant.ready - skip - io.in[7].grant.bits <- io.out.grant.bits - node T_1650 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[7].grant.bits.client_xact_id <= T_1650 + output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>} - module L2BroadcastHub : - input clk : Clock + io is invalid + io is invalid + node _T_12 = bits(io.in, 1, 0) @[RVC.scala 162:20] + node _T_14 = neq(_T_12, UInt<2>("h03")) @[RVC.scala 162:26] + io.rvc <= _T_14 @[RVC.scala 162:12] + node _T_15 = bits(io.in, 12, 5) @[RVC.scala 53:22] + node _T_17 = neq(_T_15, UInt<1>("h00")) @[RVC.scala 53:29] + node _T_20 = mux(_T_17, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 53:20] + node _T_21 = bits(io.in, 10, 7) @[RVC.scala 34:26] + node _T_22 = bits(io.in, 12, 11) @[RVC.scala 34:35] + node _T_23 = bits(io.in, 5, 5) @[RVC.scala 34:45] + node _T_24 = bits(io.in, 6, 6) @[RVC.scala 34:51] + node _T_26 = cat(_T_24, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_27 = cat(_T_21, _T_22) @[Cat.scala 30:58] + node _T_28 = cat(_T_27, _T_23) @[Cat.scala 30:58] + node _T_29 = cat(_T_28, _T_26) @[Cat.scala 30:58] + node _T_33 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_34 = cat(UInt<2>("h01"), _T_33) @[Cat.scala 30:58] + node _T_35 = cat(_T_34, _T_20) @[Cat.scala 30:58] + node _T_36 = cat(_T_29, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_38 = cat(_T_37, _T_35) @[Cat.scala 30:58] + node _T_40 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_41 = cat(UInt<2>("h01"), _T_40) @[Cat.scala 30:58] + node _T_44 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_45 = cat(UInt<2>("h01"), _T_44) @[Cat.scala 30:58] + node _T_46 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_53 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_53 is invalid @[RVC.scala 21:19] + _T_53.bits <= _T_38 @[RVC.scala 22:14] + _T_53.rd <= _T_41 @[RVC.scala 23:12] + _T_53.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_53.rs2 <= _T_45 @[RVC.scala 25:13] + _T_53.rs3 <= _T_46 @[RVC.scala 26:13] + node _T_59 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_60 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_62 = cat(_T_59, _T_60) @[Cat.scala 30:58] + node _T_63 = cat(_T_62, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_65 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_66 = cat(UInt<2>("h01"), _T_65) @[Cat.scala 30:58] + node _T_69 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_70 = cat(UInt<2>("h01"), _T_69) @[Cat.scala 30:58] + node _T_72 = cat(_T_70, UInt<7>("h07")) @[Cat.scala 30:58] + node _T_73 = cat(_T_63, _T_66) @[Cat.scala 30:58] + node _T_74 = cat(_T_73, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_75 = cat(_T_74, _T_72) @[Cat.scala 30:58] + node _T_77 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_78 = cat(UInt<2>("h01"), _T_77) @[Cat.scala 30:58] + node _T_80 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_81 = cat(UInt<2>("h01"), _T_80) @[Cat.scala 30:58] + node _T_83 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_84 = cat(UInt<2>("h01"), _T_83) @[Cat.scala 30:58] + node _T_85 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_92 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_92 is invalid @[RVC.scala 21:19] + _T_92.bits <= _T_75 @[RVC.scala 22:14] + _T_92.rd <= _T_78 @[RVC.scala 23:12] + _T_92.rs1 <= _T_81 @[RVC.scala 24:13] + _T_92.rs2 <= _T_84 @[RVC.scala 25:13] + _T_92.rs3 <= _T_85 @[RVC.scala 26:13] + node _T_98 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_99 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_100 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_102 = cat(_T_100, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_103 = cat(_T_98, _T_99) @[Cat.scala 30:58] + node _T_104 = cat(_T_103, _T_102) @[Cat.scala 30:58] + node _T_106 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_107 = cat(UInt<2>("h01"), _T_106) @[Cat.scala 30:58] + node _T_110 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_111 = cat(UInt<2>("h01"), _T_110) @[Cat.scala 30:58] + node _T_113 = cat(_T_111, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_114 = cat(_T_104, _T_107) @[Cat.scala 30:58] + node _T_115 = cat(_T_114, UInt<3>("h02")) @[Cat.scala 30:58] + node _T_116 = cat(_T_115, _T_113) @[Cat.scala 30:58] + node _T_118 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_119 = cat(UInt<2>("h01"), _T_118) @[Cat.scala 30:58] + node _T_121 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_122 = cat(UInt<2>("h01"), _T_121) @[Cat.scala 30:58] + node _T_124 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_125 = cat(UInt<2>("h01"), _T_124) @[Cat.scala 30:58] + node _T_126 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_133 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_133 is invalid @[RVC.scala 21:19] + _T_133.bits <= _T_116 @[RVC.scala 22:14] + _T_133.rd <= _T_119 @[RVC.scala 23:12] + _T_133.rs1 <= _T_122 @[RVC.scala 24:13] + _T_133.rs2 <= _T_125 @[RVC.scala 25:13] + _T_133.rs3 <= _T_126 @[RVC.scala 26:13] + node _T_139 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_140 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_142 = cat(_T_139, _T_140) @[Cat.scala 30:58] + node _T_143 = cat(_T_142, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_145 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_146 = cat(UInt<2>("h01"), _T_145) @[Cat.scala 30:58] + node _T_149 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_150 = cat(UInt<2>("h01"), _T_149) @[Cat.scala 30:58] + node _T_152 = cat(_T_150, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_153 = cat(_T_143, _T_146) @[Cat.scala 30:58] + node _T_154 = cat(_T_153, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_155 = cat(_T_154, _T_152) @[Cat.scala 30:58] + node _T_157 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_158 = cat(UInt<2>("h01"), _T_157) @[Cat.scala 30:58] + node _T_160 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_161 = cat(UInt<2>("h01"), _T_160) @[Cat.scala 30:58] + node _T_163 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_164 = cat(UInt<2>("h01"), _T_163) @[Cat.scala 30:58] + node _T_165 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_172 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_172 is invalid @[RVC.scala 21:19] + _T_172.bits <= _T_155 @[RVC.scala 22:14] + _T_172.rd <= _T_158 @[RVC.scala 23:12] + _T_172.rs1 <= _T_161 @[RVC.scala 24:13] + _T_172.rs2 <= _T_164 @[RVC.scala 25:13] + _T_172.rs3 <= _T_165 @[RVC.scala 26:13] + node _T_178 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_179 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_180 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_182 = cat(_T_180, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_183 = cat(_T_178, _T_179) @[Cat.scala 30:58] + node _T_184 = cat(_T_183, _T_182) @[Cat.scala 30:58] + node _T_185 = shr(_T_184, 5) @[RVC.scala 63:32] + node _T_187 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_188 = cat(UInt<2>("h01"), _T_187) @[Cat.scala 30:58] + node _T_190 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_191 = cat(UInt<2>("h01"), _T_190) @[Cat.scala 30:58] + node _T_193 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_194 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_195 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_197 = cat(_T_195, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_198 = cat(_T_193, _T_194) @[Cat.scala 30:58] + node _T_199 = cat(_T_198, _T_197) @[Cat.scala 30:58] + node _T_200 = bits(_T_199, 4, 0) @[RVC.scala 63:66] + node _T_202 = cat(UInt<3>("h02"), _T_200) @[Cat.scala 30:58] + node _T_203 = cat(_T_202, UInt<7>("h02f")) @[Cat.scala 30:58] + node _T_204 = cat(_T_185, _T_188) @[Cat.scala 30:58] + node _T_205 = cat(_T_204, _T_191) @[Cat.scala 30:58] + node _T_206 = cat(_T_205, _T_203) @[Cat.scala 30:58] + node _T_208 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_209 = cat(UInt<2>("h01"), _T_208) @[Cat.scala 30:58] + node _T_211 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_212 = cat(UInt<2>("h01"), _T_211) @[Cat.scala 30:58] + node _T_214 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_215 = cat(UInt<2>("h01"), _T_214) @[Cat.scala 30:58] + node _T_216 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_223 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_223 is invalid @[RVC.scala 21:19] + _T_223.bits <= _T_206 @[RVC.scala 22:14] + _T_223.rd <= _T_209 @[RVC.scala 23:12] + _T_223.rs1 <= _T_212 @[RVC.scala 24:13] + _T_223.rs2 <= _T_215 @[RVC.scala 25:13] + _T_223.rs3 <= _T_216 @[RVC.scala 26:13] + node _T_229 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_230 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_232 = cat(_T_229, _T_230) @[Cat.scala 30:58] + node _T_233 = cat(_T_232, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_234 = shr(_T_233, 5) @[RVC.scala 66:30] + node _T_236 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_237 = cat(UInt<2>("h01"), _T_236) @[Cat.scala 30:58] + node _T_239 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_240 = cat(UInt<2>("h01"), _T_239) @[Cat.scala 30:58] + node _T_242 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_243 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_245 = cat(_T_242, _T_243) @[Cat.scala 30:58] + node _T_246 = cat(_T_245, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_247 = bits(_T_246, 4, 0) @[RVC.scala 66:64] + node _T_249 = cat(UInt<3>("h03"), _T_247) @[Cat.scala 30:58] + node _T_250 = cat(_T_249, UInt<7>("h027")) @[Cat.scala 30:58] + node _T_251 = cat(_T_234, _T_237) @[Cat.scala 30:58] + node _T_252 = cat(_T_251, _T_240) @[Cat.scala 30:58] + node _T_253 = cat(_T_252, _T_250) @[Cat.scala 30:58] + node _T_255 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_256 = cat(UInt<2>("h01"), _T_255) @[Cat.scala 30:58] + node _T_258 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_259 = cat(UInt<2>("h01"), _T_258) @[Cat.scala 30:58] + node _T_261 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_262 = cat(UInt<2>("h01"), _T_261) @[Cat.scala 30:58] + node _T_263 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_270 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_270 is invalid @[RVC.scala 21:19] + _T_270.bits <= _T_253 @[RVC.scala 22:14] + _T_270.rd <= _T_256 @[RVC.scala 23:12] + _T_270.rs1 <= _T_259 @[RVC.scala 24:13] + _T_270.rs2 <= _T_262 @[RVC.scala 25:13] + _T_270.rs3 <= _T_263 @[RVC.scala 26:13] + node _T_276 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_277 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_278 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_280 = cat(_T_278, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_281 = cat(_T_276, _T_277) @[Cat.scala 30:58] + node _T_282 = cat(_T_281, _T_280) @[Cat.scala 30:58] + node _T_283 = shr(_T_282, 5) @[RVC.scala 65:29] + node _T_285 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_286 = cat(UInt<2>("h01"), _T_285) @[Cat.scala 30:58] + node _T_288 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_289 = cat(UInt<2>("h01"), _T_288) @[Cat.scala 30:58] + node _T_291 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_292 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_293 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_295 = cat(_T_293, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_296 = cat(_T_291, _T_292) @[Cat.scala 30:58] + node _T_297 = cat(_T_296, _T_295) @[Cat.scala 30:58] + node _T_298 = bits(_T_297, 4, 0) @[RVC.scala 65:63] + node _T_300 = cat(UInt<3>("h02"), _T_298) @[Cat.scala 30:58] + node _T_301 = cat(_T_300, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_302 = cat(_T_283, _T_286) @[Cat.scala 30:58] + node _T_303 = cat(_T_302, _T_289) @[Cat.scala 30:58] + node _T_304 = cat(_T_303, _T_301) @[Cat.scala 30:58] + node _T_306 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_307 = cat(UInt<2>("h01"), _T_306) @[Cat.scala 30:58] + node _T_309 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_310 = cat(UInt<2>("h01"), _T_309) @[Cat.scala 30:58] + node _T_312 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_313 = cat(UInt<2>("h01"), _T_312) @[Cat.scala 30:58] + node _T_314 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_321 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_321 is invalid @[RVC.scala 21:19] + _T_321.bits <= _T_304 @[RVC.scala 22:14] + _T_321.rd <= _T_307 @[RVC.scala 23:12] + _T_321.rs1 <= _T_310 @[RVC.scala 24:13] + _T_321.rs2 <= _T_313 @[RVC.scala 25:13] + _T_321.rs3 <= _T_314 @[RVC.scala 26:13] + node _T_327 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_328 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_330 = cat(_T_327, _T_328) @[Cat.scala 30:58] + node _T_331 = cat(_T_330, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_332 = shr(_T_331, 5) @[RVC.scala 64:29] + node _T_334 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_335 = cat(UInt<2>("h01"), _T_334) @[Cat.scala 30:58] + node _T_337 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_338 = cat(UInt<2>("h01"), _T_337) @[Cat.scala 30:58] + node _T_340 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_341 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_343 = cat(_T_340, _T_341) @[Cat.scala 30:58] + node _T_344 = cat(_T_343, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_345 = bits(_T_344, 4, 0) @[RVC.scala 64:63] + node _T_347 = cat(UInt<3>("h03"), _T_345) @[Cat.scala 30:58] + node _T_348 = cat(_T_347, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_349 = cat(_T_332, _T_335) @[Cat.scala 30:58] + node _T_350 = cat(_T_349, _T_338) @[Cat.scala 30:58] + node _T_351 = cat(_T_350, _T_348) @[Cat.scala 30:58] + node _T_353 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_354 = cat(UInt<2>("h01"), _T_353) @[Cat.scala 30:58] + node _T_356 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_357 = cat(UInt<2>("h01"), _T_356) @[Cat.scala 30:58] + node _T_359 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_360 = cat(UInt<2>("h01"), _T_359) @[Cat.scala 30:58] + node _T_361 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_368 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_368 is invalid @[RVC.scala 21:19] + _T_368.bits <= _T_351 @[RVC.scala 22:14] + _T_368.rd <= _T_354 @[RVC.scala 23:12] + _T_368.rs1 <= _T_357 @[RVC.scala 24:13] + _T_368.rs2 <= _T_360 @[RVC.scala 25:13] + _T_368.rs3 <= _T_361 @[RVC.scala 26:13] + node _T_374 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_375 = bits(_T_374, 0, 0) @[Bitwise.scala 71:15] + node _T_378 = mux(_T_375, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_379 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_380 = cat(_T_378, _T_379) @[Cat.scala 30:58] + node _T_381 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_383 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_385 = cat(_T_383, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_386 = cat(_T_380, _T_381) @[Cat.scala 30:58] + node _T_387 = cat(_T_386, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_388 = cat(_T_387, _T_385) @[Cat.scala 30:58] + node _T_389 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_390 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_392 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_393 = cat(UInt<2>("h01"), _T_392) @[Cat.scala 30:58] + node _T_394 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_401 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_401 is invalid @[RVC.scala 21:19] + _T_401.bits <= _T_388 @[RVC.scala 22:14] + _T_401.rd <= _T_389 @[RVC.scala 23:12] + _T_401.rs1 <= _T_390 @[RVC.scala 24:13] + _T_401.rs2 <= _T_393 @[RVC.scala 25:13] + _T_401.rs3 <= _T_394 @[RVC.scala 26:13] + node _T_407 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_409 = neq(_T_407, UInt<1>("h00")) @[RVC.scala 77:24] + node _T_412 = mux(_T_409, UInt<7>("h01b"), UInt<7>("h01f")) @[RVC.scala 77:20] + node _T_413 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_414 = bits(_T_413, 0, 0) @[Bitwise.scala 71:15] + node _T_417 = mux(_T_414, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_418 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_419 = cat(_T_417, _T_418) @[Cat.scala 30:58] + node _T_420 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_422 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_423 = cat(_T_422, _T_412) @[Cat.scala 30:58] + node _T_424 = cat(_T_419, _T_420) @[Cat.scala 30:58] + node _T_425 = cat(_T_424, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_426 = cat(_T_425, _T_423) @[Cat.scala 30:58] + node _T_427 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_428 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_430 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_431 = cat(UInt<2>("h01"), _T_430) @[Cat.scala 30:58] + node _T_432 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_439 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_439 is invalid @[RVC.scala 21:19] + _T_439.bits <= _T_426 @[RVC.scala 22:14] + _T_439.rd <= _T_427 @[RVC.scala 23:12] + _T_439.rs1 <= _T_428 @[RVC.scala 24:13] + _T_439.rs2 <= _T_431 @[RVC.scala 25:13] + _T_439.rs3 <= _T_432 @[RVC.scala 26:13] + node _T_445 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_446 = bits(_T_445, 0, 0) @[Bitwise.scala 71:15] + node _T_449 = mux(_T_446, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_450 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_451 = cat(_T_449, _T_450) @[Cat.scala 30:58] + node _T_454 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_456 = cat(_T_454, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_457 = cat(_T_451, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_458 = cat(_T_457, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_459 = cat(_T_458, _T_456) @[Cat.scala 30:58] + node _T_460 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_463 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_464 = cat(UInt<2>("h01"), _T_463) @[Cat.scala 30:58] + node _T_465 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_472 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_472 is invalid @[RVC.scala 21:19] + _T_472.bits <= _T_459 @[RVC.scala 22:14] + _T_472.rd <= _T_460 @[RVC.scala 23:12] + _T_472.rs1 <= UInt<5>("h00") @[RVC.scala 24:13] + _T_472.rs2 <= _T_464 @[RVC.scala 25:13] + _T_472.rs3 <= _T_465 @[RVC.scala 26:13] + node _T_478 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 71:15] + node _T_482 = mux(_T_479, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_483 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_484 = cat(_T_482, _T_483) @[Cat.scala 30:58] + node _T_486 = neq(_T_484, UInt<1>("h00")) @[RVC.scala 90:29] + node _T_489 = mux(_T_486, UInt<7>("h037"), UInt<7>("h03f")) @[RVC.scala 90:20] + node _T_490 = bits(io.in, 12, 12) @[RVC.scala 41:30] + node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 71:15] + node _T_494 = mux(_T_491, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 71:12] + node _T_495 = bits(io.in, 6, 2) @[RVC.scala 41:38] + node _T_497 = cat(_T_494, _T_495) @[Cat.scala 30:58] + node _T_498 = cat(_T_497, UInt<12>("h00")) @[Cat.scala 30:58] + node _T_499 = bits(_T_498, 31, 12) @[RVC.scala 91:31] + node _T_500 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_501 = cat(_T_499, _T_500) @[Cat.scala 30:58] + node _T_502 = cat(_T_501, _T_489) @[Cat.scala 30:58] + node _T_503 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_504 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_506 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_507 = cat(UInt<2>("h01"), _T_506) @[Cat.scala 30:58] + node _T_508 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_515 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_515 is invalid @[RVC.scala 21:19] + _T_515.bits <= _T_502 @[RVC.scala 22:14] + _T_515.rd <= _T_503 @[RVC.scala 23:12] + _T_515.rs1 <= _T_504 @[RVC.scala 24:13] + _T_515.rs2 <= _T_507 @[RVC.scala 25:13] + _T_515.rs3 <= _T_508 @[RVC.scala 26:13] + node _T_521 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_523 = eq(_T_521, UInt<5>("h00")) @[RVC.scala 92:14] + node _T_524 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_526 = eq(_T_524, UInt<5>("h02")) @[RVC.scala 92:27] + node _T_527 = or(_T_523, _T_526) @[RVC.scala 92:21] + node _T_528 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 71:15] + node _T_532 = mux(_T_529, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_533 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_534 = cat(_T_532, _T_533) @[Cat.scala 30:58] + node _T_536 = neq(_T_534, UInt<1>("h00")) @[RVC.scala 86:29] + node _T_539 = mux(_T_536, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 86:20] + node _T_540 = bits(io.in, 12, 12) @[RVC.scala 42:34] + node _T_541 = bits(_T_540, 0, 0) @[Bitwise.scala 71:15] + node _T_544 = mux(_T_541, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_545 = bits(io.in, 4, 3) @[RVC.scala 42:42] + node _T_546 = bits(io.in, 5, 5) @[RVC.scala 42:50] + node _T_547 = bits(io.in, 2, 2) @[RVC.scala 42:56] + node _T_548 = bits(io.in, 6, 6) @[RVC.scala 42:62] + node _T_550 = cat(_T_547, _T_548) @[Cat.scala 30:58] + node _T_551 = cat(_T_550, UInt<4>("h00")) @[Cat.scala 30:58] + node _T_552 = cat(_T_544, _T_545) @[Cat.scala 30:58] + node _T_553 = cat(_T_552, _T_546) @[Cat.scala 30:58] + node _T_554 = cat(_T_553, _T_551) @[Cat.scala 30:58] + node _T_555 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_557 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_558 = cat(_T_557, _T_539) @[Cat.scala 30:58] + node _T_559 = cat(_T_554, _T_555) @[Cat.scala 30:58] + node _T_560 = cat(_T_559, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_561 = cat(_T_560, _T_558) @[Cat.scala 30:58] + node _T_562 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_563 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_565 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_566 = cat(UInt<2>("h01"), _T_565) @[Cat.scala 30:58] + node _T_567 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_574 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_574 is invalid @[RVC.scala 21:19] + _T_574.bits <= _T_561 @[RVC.scala 22:14] + _T_574.rd <= _T_562 @[RVC.scala 23:12] + _T_574.rs1 <= _T_563 @[RVC.scala 24:13] + _T_574.rs2 <= _T_566 @[RVC.scala 25:13] + _T_574.rs3 <= _T_567 @[RVC.scala 26:13] + node _T_580 = mux(_T_527, _T_574, _T_515) @[RVC.scala 92:10] + node _T_586 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_587 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_588 = cat(_T_586, _T_587) @[Cat.scala 30:58] + node _T_590 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_591 = cat(UInt<2>("h01"), _T_590) @[Cat.scala 30:58] + node _T_594 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_595 = cat(UInt<2>("h01"), _T_594) @[Cat.scala 30:58] + node _T_597 = cat(_T_595, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_598 = cat(_T_588, _T_591) @[Cat.scala 30:58] + node _T_599 = cat(_T_598, UInt<3>("h05")) @[Cat.scala 30:58] + node _T_600 = cat(_T_599, _T_597) @[Cat.scala 30:58] + node _T_601 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_602 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_603 = cat(_T_601, _T_602) @[Cat.scala 30:58] + node _T_605 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_606 = cat(UInt<2>("h01"), _T_605) @[Cat.scala 30:58] + node _T_609 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_610 = cat(UInt<2>("h01"), _T_609) @[Cat.scala 30:58] + node _T_612 = cat(_T_610, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_613 = cat(_T_603, _T_606) @[Cat.scala 30:58] + node _T_614 = cat(_T_613, UInt<3>("h05")) @[Cat.scala 30:58] + node _T_615 = cat(_T_614, _T_612) @[Cat.scala 30:58] + node _T_617 = or(_T_615, UInt<31>("h040000000")) @[RVC.scala 99:23] + node _T_618 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_619 = bits(_T_618, 0, 0) @[Bitwise.scala 71:15] + node _T_622 = mux(_T_619, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_623 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_624 = cat(_T_622, _T_623) @[Cat.scala 30:58] + node _T_626 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_627 = cat(UInt<2>("h01"), _T_626) @[Cat.scala 30:58] + node _T_630 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_631 = cat(UInt<2>("h01"), _T_630) @[Cat.scala 30:58] + node _T_633 = cat(_T_631, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_634 = cat(_T_624, _T_627) @[Cat.scala 30:58] + node _T_635 = cat(_T_634, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_636 = cat(_T_635, _T_633) @[Cat.scala 30:58] + node _T_645 = bits(io.in, 12, 12) @[RVC.scala 102:70] + node _T_646 = bits(io.in, 6, 5) @[RVC.scala 102:77] + node _T_647 = cat(_T_645, _T_646) @[Cat.scala 30:58] + node _T_649 = and(_T_647, UInt<2>("h03")) @[Package.scala 18:26] + node _T_651 = geq(_T_647, UInt<3>("h04")) @[Package.scala 19:17] + node _T_653 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26] + node _T_655 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17] + node _T_657 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26] + node _T_659 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17] + node _T_660 = mux(_T_659, UInt<2>("h03"), UInt<2>("h02")) @[Package.scala 19:12] + node _T_662 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26] + node _T_664 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17] + node _T_665 = mux(_T_664, UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 19:12] + node _T_666 = mux(_T_655, _T_660, _T_665) @[Package.scala 19:12] + node _T_668 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26] + node _T_670 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17] + node _T_672 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_674 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_675 = mux(_T_674, UInt<3>("h07"), UInt<3>("h06")) @[Package.scala 19:12] + node _T_677 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_679 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_680 = mux(_T_679, UInt<3>("h04"), UInt<1>("h00")) @[Package.scala 19:12] + node _T_681 = mux(_T_670, _T_675, _T_680) @[Package.scala 19:12] + node _T_682 = mux(_T_651, _T_666, _T_681) @[Package.scala 19:12] + node _T_683 = bits(io.in, 6, 5) @[RVC.scala 103:24] + node _T_685 = eq(_T_683, UInt<1>("h00")) @[RVC.scala 103:30] + node _T_688 = mux(_T_685, UInt<31>("h040000000"), UInt<1>("h00")) @[RVC.scala 103:22] + node _T_689 = bits(io.in, 12, 12) @[RVC.scala 104:24] + node _T_692 = mux(_T_689, UInt<7>("h03b"), UInt<7>("h033")) @[RVC.scala 104:22] + node _T_694 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_695 = cat(UInt<2>("h01"), _T_694) @[Cat.scala 30:58] + node _T_697 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_698 = cat(UInt<2>("h01"), _T_697) @[Cat.scala 30:58] + node _T_700 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_701 = cat(UInt<2>("h01"), _T_700) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_692) @[Cat.scala 30:58] + node _T_703 = cat(_T_695, _T_698) @[Cat.scala 30:58] + node _T_704 = cat(_T_703, _T_682) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_702) @[Cat.scala 30:58] + node _T_706 = or(_T_705, _T_688) @[RVC.scala 105:43] + node _T_707 = bits(io.in, 11, 10) @[RVC.scala 107:42] + node _T_709 = and(_T_707, UInt<1>("h01")) @[Package.scala 18:26] + node _T_711 = geq(_T_707, UInt<2>("h02")) @[Package.scala 19:17] + node _T_713 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26] + node _T_715 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17] + node _T_716 = mux(_T_715, _T_706, _T_636) @[Package.scala 19:12] + node _T_718 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26] + node _T_720 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17] + node _T_721 = mux(_T_720, _T_617, _T_600) @[Package.scala 19:12] + node _T_722 = mux(_T_711, _T_716, _T_721) @[Package.scala 19:12] + node _T_724 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_725 = cat(UInt<2>("h01"), _T_724) @[Cat.scala 30:58] + node _T_727 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_728 = cat(UInt<2>("h01"), _T_727) @[Cat.scala 30:58] + node _T_730 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_731 = cat(UInt<2>("h01"), _T_730) @[Cat.scala 30:58] + node _T_732 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_739 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_739 is invalid @[RVC.scala 21:19] + _T_739.bits <= _T_722 @[RVC.scala 22:14] + _T_739.rd <= _T_725 @[RVC.scala 23:12] + _T_739.rs1 <= _T_728 @[RVC.scala 24:13] + _T_739.rs2 <= _T_731 @[RVC.scala 25:13] + _T_739.rs3 <= _T_732 @[RVC.scala 26:13] + node _T_745 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_746 = bits(_T_745, 0, 0) @[Bitwise.scala 71:15] + node _T_749 = mux(_T_746, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_750 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_751 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_752 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_753 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_754 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_755 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_756 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_758 = cat(_T_756, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_759 = cat(_T_754, _T_755) @[Cat.scala 30:58] + node _T_760 = cat(_T_759, _T_758) @[Cat.scala 30:58] + node _T_761 = cat(_T_752, _T_753) @[Cat.scala 30:58] + node _T_762 = cat(_T_749, _T_750) @[Cat.scala 30:58] + node _T_763 = cat(_T_762, _T_751) @[Cat.scala 30:58] + node _T_764 = cat(_T_763, _T_761) @[Cat.scala 30:58] + node _T_765 = cat(_T_764, _T_760) @[Cat.scala 30:58] + node _T_766 = bits(_T_765, 20, 20) @[RVC.scala 94:26] + node _T_767 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_768 = bits(_T_767, 0, 0) @[Bitwise.scala 71:15] + node _T_771 = mux(_T_768, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_772 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_773 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_774 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_775 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_776 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_777 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_778 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_780 = cat(_T_778, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_781 = cat(_T_776, _T_777) @[Cat.scala 30:58] + node _T_782 = cat(_T_781, _T_780) @[Cat.scala 30:58] + node _T_783 = cat(_T_774, _T_775) @[Cat.scala 30:58] + node _T_784 = cat(_T_771, _T_772) @[Cat.scala 30:58] + node _T_785 = cat(_T_784, _T_773) @[Cat.scala 30:58] + node _T_786 = cat(_T_785, _T_783) @[Cat.scala 30:58] + node _T_787 = cat(_T_786, _T_782) @[Cat.scala 30:58] + node _T_788 = bits(_T_787, 10, 1) @[RVC.scala 94:36] + node _T_789 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_790 = bits(_T_789, 0, 0) @[Bitwise.scala 71:15] + node _T_793 = mux(_T_790, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_794 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_795 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_796 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_797 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_798 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_799 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_800 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_802 = cat(_T_800, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_803 = cat(_T_798, _T_799) @[Cat.scala 30:58] + node _T_804 = cat(_T_803, _T_802) @[Cat.scala 30:58] + node _T_805 = cat(_T_796, _T_797) @[Cat.scala 30:58] + node _T_806 = cat(_T_793, _T_794) @[Cat.scala 30:58] + node _T_807 = cat(_T_806, _T_795) @[Cat.scala 30:58] + node _T_808 = cat(_T_807, _T_805) @[Cat.scala 30:58] + node _T_809 = cat(_T_808, _T_804) @[Cat.scala 30:58] + node _T_810 = bits(_T_809, 11, 11) @[RVC.scala 94:48] + node _T_811 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_812 = bits(_T_811, 0, 0) @[Bitwise.scala 71:15] + node _T_815 = mux(_T_812, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_816 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_817 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_818 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_819 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_820 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_821 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_822 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_824 = cat(_T_822, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_825 = cat(_T_820, _T_821) @[Cat.scala 30:58] + node _T_826 = cat(_T_825, _T_824) @[Cat.scala 30:58] + node _T_827 = cat(_T_818, _T_819) @[Cat.scala 30:58] + node _T_828 = cat(_T_815, _T_816) @[Cat.scala 30:58] + node _T_829 = cat(_T_828, _T_817) @[Cat.scala 30:58] + node _T_830 = cat(_T_829, _T_827) @[Cat.scala 30:58] + node _T_831 = cat(_T_830, _T_826) @[Cat.scala 30:58] + node _T_832 = bits(_T_831, 19, 12) @[RVC.scala 94:58] + node _T_835 = cat(_T_832, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_836 = cat(_T_835, UInt<7>("h06f")) @[Cat.scala 30:58] + node _T_837 = cat(_T_766, _T_788) @[Cat.scala 30:58] + node _T_838 = cat(_T_837, _T_810) @[Cat.scala 30:58] + node _T_839 = cat(_T_838, _T_836) @[Cat.scala 30:58] + node _T_842 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_843 = cat(UInt<2>("h01"), _T_842) @[Cat.scala 30:58] + node _T_845 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_846 = cat(UInt<2>("h01"), _T_845) @[Cat.scala 30:58] + node _T_847 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_854 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_854 is invalid @[RVC.scala 21:19] + _T_854.bits <= _T_839 @[RVC.scala 22:14] + _T_854.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_854.rs1 <= _T_843 @[RVC.scala 24:13] + _T_854.rs2 <= _T_846 @[RVC.scala 25:13] + _T_854.rs3 <= _T_847 @[RVC.scala 26:13] + node _T_860 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_861 = bits(_T_860, 0, 0) @[Bitwise.scala 71:15] + node _T_864 = mux(_T_861, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_865 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_866 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_867 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_868 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_870 = cat(_T_867, _T_868) @[Cat.scala 30:58] + node _T_871 = cat(_T_870, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_872 = cat(_T_864, _T_865) @[Cat.scala 30:58] + node _T_873 = cat(_T_872, _T_866) @[Cat.scala 30:58] + node _T_874 = cat(_T_873, _T_871) @[Cat.scala 30:58] + node _T_875 = bits(_T_874, 12, 12) @[RVC.scala 95:29] + node _T_876 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_877 = bits(_T_876, 0, 0) @[Bitwise.scala 71:15] + node _T_880 = mux(_T_877, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_881 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_882 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_883 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_884 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_886 = cat(_T_883, _T_884) @[Cat.scala 30:58] + node _T_887 = cat(_T_886, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_888 = cat(_T_880, _T_881) @[Cat.scala 30:58] + node _T_889 = cat(_T_888, _T_882) @[Cat.scala 30:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 30:58] + node _T_891 = bits(_T_890, 10, 5) @[RVC.scala 95:39] + node _T_894 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_895 = cat(UInt<2>("h01"), _T_894) @[Cat.scala 30:58] + node _T_897 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_898 = bits(_T_897, 0, 0) @[Bitwise.scala 71:15] + node _T_901 = mux(_T_898, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_902 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_903 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_904 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_905 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_907 = cat(_T_904, _T_905) @[Cat.scala 30:58] + node _T_908 = cat(_T_907, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_909 = cat(_T_901, _T_902) @[Cat.scala 30:58] + node _T_910 = cat(_T_909, _T_903) @[Cat.scala 30:58] + node _T_911 = cat(_T_910, _T_908) @[Cat.scala 30:58] + node _T_912 = bits(_T_911, 4, 1) @[RVC.scala 95:72] + node _T_913 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_914 = bits(_T_913, 0, 0) @[Bitwise.scala 71:15] + node _T_917 = mux(_T_914, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_918 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_919 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_920 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_921 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_923 = cat(_T_920, _T_921) @[Cat.scala 30:58] + node _T_924 = cat(_T_923, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_925 = cat(_T_917, _T_918) @[Cat.scala 30:58] + node _T_926 = cat(_T_925, _T_919) @[Cat.scala 30:58] + node _T_927 = cat(_T_926, _T_924) @[Cat.scala 30:58] + node _T_928 = bits(_T_927, 11, 11) @[RVC.scala 95:83] + node _T_930 = cat(_T_928, UInt<7>("h063")) @[Cat.scala 30:58] + node _T_931 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 30:58] + node _T_932 = cat(_T_931, _T_930) @[Cat.scala 30:58] + node _T_933 = cat(UInt<5>("h00"), _T_895) @[Cat.scala 30:58] + node _T_934 = cat(_T_875, _T_891) @[Cat.scala 30:58] + node _T_935 = cat(_T_934, _T_933) @[Cat.scala 30:58] + node _T_936 = cat(_T_935, _T_932) @[Cat.scala 30:58] + node _T_938 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_939 = cat(UInt<2>("h01"), _T_938) @[Cat.scala 30:58] + node _T_941 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_942 = cat(UInt<2>("h01"), _T_941) @[Cat.scala 30:58] + node _T_944 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_951 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_951 is invalid @[RVC.scala 21:19] + _T_951.bits <= _T_936 @[RVC.scala 22:14] + _T_951.rd <= _T_939 @[RVC.scala 23:12] + _T_951.rs1 <= _T_942 @[RVC.scala 24:13] + _T_951.rs2 <= UInt<5>("h00") @[RVC.scala 25:13] + _T_951.rs3 <= _T_944 @[RVC.scala 26:13] + node _T_957 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_958 = bits(_T_957, 0, 0) @[Bitwise.scala 71:15] + node _T_961 = mux(_T_958, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_962 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_963 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_964 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_965 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_967 = cat(_T_964, _T_965) @[Cat.scala 30:58] + node _T_968 = cat(_T_967, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_969 = cat(_T_961, _T_962) @[Cat.scala 30:58] + node _T_970 = cat(_T_969, _T_963) @[Cat.scala 30:58] + node _T_971 = cat(_T_970, _T_968) @[Cat.scala 30:58] + node _T_972 = bits(_T_971, 12, 12) @[RVC.scala 96:29] + node _T_973 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_974 = bits(_T_973, 0, 0) @[Bitwise.scala 71:15] + node _T_977 = mux(_T_974, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_978 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_979 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_980 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_981 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_983 = cat(_T_980, _T_981) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_985 = cat(_T_977, _T_978) @[Cat.scala 30:58] + node _T_986 = cat(_T_985, _T_979) @[Cat.scala 30:58] + node _T_987 = cat(_T_986, _T_984) @[Cat.scala 30:58] + node _T_988 = bits(_T_987, 10, 5) @[RVC.scala 96:39] + node _T_991 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_992 = cat(UInt<2>("h01"), _T_991) @[Cat.scala 30:58] + node _T_994 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_995 = bits(_T_994, 0, 0) @[Bitwise.scala 71:15] + node _T_998 = mux(_T_995, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_999 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_1000 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_1001 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_1002 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_1004 = cat(_T_1001, _T_1002) @[Cat.scala 30:58] + node _T_1005 = cat(_T_1004, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1006 = cat(_T_998, _T_999) @[Cat.scala 30:58] + node _T_1007 = cat(_T_1006, _T_1000) @[Cat.scala 30:58] + node _T_1008 = cat(_T_1007, _T_1005) @[Cat.scala 30:58] + node _T_1009 = bits(_T_1008, 4, 1) @[RVC.scala 96:72] + node _T_1010 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_1011 = bits(_T_1010, 0, 0) @[Bitwise.scala 71:15] + node _T_1014 = mux(_T_1011, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_1015 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_1016 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_1017 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_1018 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_1020 = cat(_T_1017, _T_1018) @[Cat.scala 30:58] + node _T_1021 = cat(_T_1020, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1022 = cat(_T_1014, _T_1015) @[Cat.scala 30:58] + node _T_1023 = cat(_T_1022, _T_1016) @[Cat.scala 30:58] + node _T_1024 = cat(_T_1023, _T_1021) @[Cat.scala 30:58] + node _T_1025 = bits(_T_1024, 11, 11) @[RVC.scala 96:83] + node _T_1027 = cat(_T_1025, UInt<7>("h063")) @[Cat.scala 30:58] + node _T_1028 = cat(UInt<3>("h01"), _T_1009) @[Cat.scala 30:58] + node _T_1029 = cat(_T_1028, _T_1027) @[Cat.scala 30:58] + node _T_1030 = cat(UInt<5>("h00"), _T_992) @[Cat.scala 30:58] + node _T_1031 = cat(_T_972, _T_988) @[Cat.scala 30:58] + node _T_1032 = cat(_T_1031, _T_1030) @[Cat.scala 30:58] + node _T_1033 = cat(_T_1032, _T_1029) @[Cat.scala 30:58] + node _T_1036 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_1037 = cat(UInt<2>("h01"), _T_1036) @[Cat.scala 30:58] + node _T_1039 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1046 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1046 is invalid @[RVC.scala 21:19] + _T_1046.bits <= _T_1033 @[RVC.scala 22:14] + _T_1046.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_1046.rs1 <= _T_1037 @[RVC.scala 24:13] + _T_1046.rs2 <= UInt<5>("h00") @[RVC.scala 25:13] + _T_1046.rs3 <= _T_1039 @[RVC.scala 26:13] + node _T_1052 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_1053 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_1054 = cat(_T_1052, _T_1053) @[Cat.scala 30:58] + node _T_1055 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1057 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1059 = cat(_T_1057, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_1060 = cat(_T_1054, _T_1055) @[Cat.scala 30:58] + node _T_1061 = cat(_T_1060, UInt<3>("h01")) @[Cat.scala 30:58] + node _T_1062 = cat(_T_1061, _T_1059) @[Cat.scala 30:58] + node _T_1063 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1064 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1065 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1066 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1073 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1073 is invalid @[RVC.scala 21:19] + _T_1073.bits <= _T_1062 @[RVC.scala 22:14] + _T_1073.rd <= _T_1063 @[RVC.scala 23:12] + _T_1073.rs1 <= _T_1064 @[RVC.scala 24:13] + _T_1073.rs2 <= _T_1065 @[RVC.scala 25:13] + _T_1073.rs3 <= _T_1066 @[RVC.scala 26:13] + node _T_1079 = bits(io.in, 4, 2) @[RVC.scala 38:22] + node _T_1080 = bits(io.in, 12, 12) @[RVC.scala 38:30] + node _T_1081 = bits(io.in, 6, 5) @[RVC.scala 38:37] + node _T_1083 = cat(_T_1081, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1084 = cat(_T_1079, _T_1080) @[Cat.scala 30:58] + node _T_1085 = cat(_T_1084, _T_1083) @[Cat.scala 30:58] + node _T_1088 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1090 = cat(_T_1088, UInt<7>("h07")) @[Cat.scala 30:58] + node _T_1091 = cat(_T_1085, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1092 = cat(_T_1091, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_1093 = cat(_T_1092, _T_1090) @[Cat.scala 30:58] + node _T_1094 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1096 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1097 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1104 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1104 is invalid @[RVC.scala 21:19] + _T_1104.bits <= _T_1093 @[RVC.scala 22:14] + _T_1104.rd <= _T_1094 @[RVC.scala 23:12] + _T_1104.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1104.rs2 <= _T_1096 @[RVC.scala 25:13] + _T_1104.rs3 <= _T_1097 @[RVC.scala 26:13] + node _T_1110 = bits(io.in, 3, 2) @[RVC.scala 37:22] + node _T_1111 = bits(io.in, 12, 12) @[RVC.scala 37:30] + node _T_1112 = bits(io.in, 6, 4) @[RVC.scala 37:37] + node _T_1114 = cat(_T_1112, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1115 = cat(_T_1110, _T_1111) @[Cat.scala 30:58] + node _T_1116 = cat(_T_1115, _T_1114) @[Cat.scala 30:58] + node _T_1119 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1121 = cat(_T_1119, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_1122 = cat(_T_1116, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1123 = cat(_T_1122, UInt<3>("h02")) @[Cat.scala 30:58] + node _T_1124 = cat(_T_1123, _T_1121) @[Cat.scala 30:58] + node _T_1125 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1127 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1128 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1135 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1135 is invalid @[RVC.scala 21:19] + _T_1135.bits <= _T_1124 @[RVC.scala 22:14] + _T_1135.rd <= _T_1125 @[RVC.scala 23:12] + _T_1135.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1135.rs2 <= _T_1127 @[RVC.scala 25:13] + _T_1135.rs3 <= _T_1128 @[RVC.scala 26:13] + node _T_1141 = bits(io.in, 4, 2) @[RVC.scala 38:22] + node _T_1142 = bits(io.in, 12, 12) @[RVC.scala 38:30] + node _T_1143 = bits(io.in, 6, 5) @[RVC.scala 38:37] + node _T_1145 = cat(_T_1143, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1146 = cat(_T_1141, _T_1142) @[Cat.scala 30:58] + node _T_1147 = cat(_T_1146, _T_1145) @[Cat.scala 30:58] + node _T_1150 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1152 = cat(_T_1150, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_1153 = cat(_T_1147, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1154 = cat(_T_1153, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_1155 = cat(_T_1154, _T_1152) @[Cat.scala 30:58] + node _T_1156 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1158 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1159 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1166 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1166 is invalid @[RVC.scala 21:19] + _T_1166.bits <= _T_1155 @[RVC.scala 22:14] + _T_1166.rd <= _T_1156 @[RVC.scala 23:12] + _T_1166.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1166.rs2 <= _T_1158 @[RVC.scala 25:13] + _T_1166.rs3 <= _T_1159 @[RVC.scala 26:13] + node _T_1172 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1175 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1177 = cat(_T_1175, UInt<7>("h033")) @[Cat.scala 30:58] + node _T_1178 = cat(_T_1172, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_1179 = cat(_T_1178, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1180 = cat(_T_1179, _T_1177) @[Cat.scala 30:58] + node _T_1181 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1183 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1184 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1191 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1191 is invalid @[RVC.scala 21:19] + _T_1191.bits <= _T_1180 @[RVC.scala 22:14] + _T_1191.rd <= _T_1181 @[RVC.scala 23:12] + _T_1191.rs1 <= UInt<5>("h00") @[RVC.scala 24:13] + _T_1191.rs2 <= _T_1183 @[RVC.scala 25:13] + _T_1191.rs3 <= _T_1184 @[RVC.scala 26:13] + node _T_1197 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1198 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1200 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1202 = cat(_T_1200, UInt<7>("h033")) @[Cat.scala 30:58] + node _T_1203 = cat(_T_1197, _T_1198) @[Cat.scala 30:58] + node _T_1204 = cat(_T_1203, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1204, _T_1202) @[Cat.scala 30:58] + node _T_1206 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1207 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1208 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1209 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1216 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1216 is invalid @[RVC.scala 21:19] + _T_1216.bits <= _T_1205 @[RVC.scala 22:14] + _T_1216.rd <= _T_1206 @[RVC.scala 23:12] + _T_1216.rs1 <= _T_1207 @[RVC.scala 24:13] + _T_1216.rs2 <= _T_1208 @[RVC.scala 25:13] + _T_1216.rs3 <= _T_1209 @[RVC.scala 26:13] + node _T_1222 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1223 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1227 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 30:58] + node _T_1228 = cat(_T_1222, _T_1223) @[Cat.scala 30:58] + node _T_1229 = cat(_T_1228, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 30:58] + node _T_1231 = shr(_T_1230, 7) @[RVC.scala 132:29] + node _T_1233 = cat(_T_1231, UInt<7>("h01f")) @[Cat.scala 30:58] + node _T_1234 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1236 = neq(_T_1234, UInt<1>("h00")) @[RVC.scala 133:37] + node _T_1237 = mux(_T_1236, _T_1230, _T_1233) @[RVC.scala 133:33] + node _T_1239 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1240 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1241 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1248 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1248 is invalid @[RVC.scala 21:19] + _T_1248.bits <= _T_1237 @[RVC.scala 22:14] + _T_1248.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_1248.rs1 <= _T_1239 @[RVC.scala 24:13] + _T_1248.rs2 <= _T_1240 @[RVC.scala 25:13] + _T_1248.rs3 <= _T_1241 @[RVC.scala 26:13] + node _T_1254 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1256 = neq(_T_1254, UInt<1>("h00")) @[RVC.scala 134:27] + node _T_1257 = mux(_T_1256, _T_1191, _T_1248) @[RVC.scala 134:22] + node _T_1263 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1264 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1268 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 30:58] + node _T_1269 = cat(_T_1263, _T_1264) @[Cat.scala 30:58] + node _T_1270 = cat(_T_1269, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 30:58] + node _T_1272 = shr(_T_1230, 7) @[RVC.scala 136:27] + node _T_1274 = cat(_T_1272, UInt<7>("h073")) @[Cat.scala 30:58] + node _T_1276 = or(_T_1274, UInt<21>("h0100000")) @[RVC.scala 136:47] + node _T_1277 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1279 = neq(_T_1277, UInt<1>("h00")) @[RVC.scala 137:37] + node _T_1280 = mux(_T_1279, _T_1271, _T_1276) @[RVC.scala 137:33] + node _T_1282 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1283 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1284 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1291 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1291 is invalid @[RVC.scala 21:19] + _T_1291.bits <= _T_1280 @[RVC.scala 22:14] + _T_1291.rd <= UInt<5>("h01") @[RVC.scala 23:12] + _T_1291.rs1 <= _T_1282 @[RVC.scala 24:13] + _T_1291.rs2 <= _T_1283 @[RVC.scala 25:13] + _T_1291.rs3 <= _T_1284 @[RVC.scala 26:13] + node _T_1297 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1299 = neq(_T_1297, UInt<1>("h00")) @[RVC.scala 138:30] + node _T_1300 = mux(_T_1299, _T_1216, _T_1291) @[RVC.scala 138:25] + node _T_1306 = bits(io.in, 12, 12) @[RVC.scala 139:12] + node _T_1307 = mux(_T_1306, _T_1300, _T_1257) @[RVC.scala 139:10] + node _T_1313 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1314 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1316 = cat(_T_1313, _T_1314) @[Cat.scala 30:58] + node _T_1317 = cat(_T_1316, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1318 = shr(_T_1317, 5) @[RVC.scala 123:34] + node _T_1319 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1322 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1323 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1325 = cat(_T_1322, _T_1323) @[Cat.scala 30:58] + node _T_1326 = cat(_T_1325, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1327 = bits(_T_1326, 4, 0) @[RVC.scala 123:67] + node _T_1329 = cat(UInt<3>("h03"), _T_1327) @[Cat.scala 30:58] + node _T_1330 = cat(_T_1329, UInt<7>("h027")) @[Cat.scala 30:58] + node _T_1331 = cat(_T_1318, _T_1319) @[Cat.scala 30:58] + node _T_1332 = cat(_T_1331, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1333 = cat(_T_1332, _T_1330) @[Cat.scala 30:58] + node _T_1334 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1336 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1337 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1344 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1344 is invalid @[RVC.scala 21:19] + _T_1344.bits <= _T_1333 @[RVC.scala 22:14] + _T_1344.rd <= _T_1334 @[RVC.scala 23:12] + _T_1344.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1344.rs2 <= _T_1336 @[RVC.scala 25:13] + _T_1344.rs3 <= _T_1337 @[RVC.scala 26:13] + node _T_1350 = bits(io.in, 8, 7) @[RVC.scala 39:22] + node _T_1351 = bits(io.in, 12, 9) @[RVC.scala 39:30] + node _T_1353 = cat(_T_1350, _T_1351) @[Cat.scala 30:58] + node _T_1354 = cat(_T_1353, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1355 = shr(_T_1354, 5) @[RVC.scala 122:33] + node _T_1356 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1359 = bits(io.in, 8, 7) @[RVC.scala 39:22] + node _T_1360 = bits(io.in, 12, 9) @[RVC.scala 39:30] + node _T_1362 = cat(_T_1359, _T_1360) @[Cat.scala 30:58] + node _T_1363 = cat(_T_1362, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1364 = bits(_T_1363, 4, 0) @[RVC.scala 122:66] + node _T_1366 = cat(UInt<3>("h02"), _T_1364) @[Cat.scala 30:58] + node _T_1367 = cat(_T_1366, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_1368 = cat(_T_1355, _T_1356) @[Cat.scala 30:58] + node _T_1369 = cat(_T_1368, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1370 = cat(_T_1369, _T_1367) @[Cat.scala 30:58] + node _T_1371 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1373 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1374 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1381 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1381 is invalid @[RVC.scala 21:19] + _T_1381.bits <= _T_1370 @[RVC.scala 22:14] + _T_1381.rd <= _T_1371 @[RVC.scala 23:12] + _T_1381.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1381.rs2 <= _T_1373 @[RVC.scala 25:13] + _T_1381.rs3 <= _T_1374 @[RVC.scala 26:13] + node _T_1387 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1388 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1390 = cat(_T_1387, _T_1388) @[Cat.scala 30:58] + node _T_1391 = cat(_T_1390, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1392 = shr(_T_1391, 5) @[RVC.scala 121:33] + node _T_1393 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1396 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1397 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1399 = cat(_T_1396, _T_1397) @[Cat.scala 30:58] + node _T_1400 = cat(_T_1399, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1401 = bits(_T_1400, 4, 0) @[RVC.scala 121:66] + node _T_1403 = cat(UInt<3>("h03"), _T_1401) @[Cat.scala 30:58] + node _T_1404 = cat(_T_1403, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_1405 = cat(_T_1392, _T_1393) @[Cat.scala 30:58] + node _T_1406 = cat(_T_1405, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1407 = cat(_T_1406, _T_1404) @[Cat.scala 30:58] + node _T_1408 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1410 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1411 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1418 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1418 is invalid @[RVC.scala 21:19] + _T_1418.bits <= _T_1407 @[RVC.scala 22:14] + _T_1418.rd <= _T_1408 @[RVC.scala 23:12] + _T_1418.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1418.rs2 <= _T_1410 @[RVC.scala 25:13] + _T_1418.rs3 <= _T_1411 @[RVC.scala 26:13] + node _T_1424 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1425 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1426 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1427 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1434 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1434 is invalid @[RVC.scala 21:19] + _T_1434.bits <= io.in @[RVC.scala 22:14] + _T_1434.rd <= _T_1424 @[RVC.scala 23:12] + _T_1434.rs1 <= _T_1425 @[RVC.scala 24:13] + _T_1434.rs2 <= _T_1426 @[RVC.scala 25:13] + _T_1434.rs3 <= _T_1427 @[RVC.scala 26:13] + node _T_1440 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1441 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1442 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1443 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1450 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1450 is invalid @[RVC.scala 21:19] + _T_1450.bits <= io.in @[RVC.scala 22:14] + _T_1450.rd <= _T_1440 @[RVC.scala 23:12] + _T_1450.rs1 <= _T_1441 @[RVC.scala 24:13] + _T_1450.rs2 <= _T_1442 @[RVC.scala 25:13] + _T_1450.rs3 <= _T_1443 @[RVC.scala 26:13] + node _T_1456 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1457 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1458 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1459 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1466 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1466 is invalid @[RVC.scala 21:19] + _T_1466.bits <= io.in @[RVC.scala 22:14] + _T_1466.rd <= _T_1456 @[RVC.scala 23:12] + _T_1466.rs1 <= _T_1457 @[RVC.scala 24:13] + _T_1466.rs2 <= _T_1458 @[RVC.scala 25:13] + _T_1466.rs3 <= _T_1459 @[RVC.scala 26:13] + node _T_1472 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1473 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1474 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1475 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1482 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1482 is invalid @[RVC.scala 21:19] + _T_1482.bits <= io.in @[RVC.scala 22:14] + _T_1482.rd <= _T_1472 @[RVC.scala 23:12] + _T_1482.rs1 <= _T_1473 @[RVC.scala 24:13] + _T_1482.rs2 <= _T_1474 @[RVC.scala 25:13] + _T_1482.rs3 <= _T_1475 @[RVC.scala 26:13] + node _T_1488 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1489 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1490 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1491 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1498 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1498 is invalid @[RVC.scala 21:19] + _T_1498.bits <= io.in @[RVC.scala 22:14] + _T_1498.rd <= _T_1488 @[RVC.scala 23:12] + _T_1498.rs1 <= _T_1489 @[RVC.scala 24:13] + _T_1498.rs2 <= _T_1490 @[RVC.scala 25:13] + _T_1498.rs3 <= _T_1491 @[RVC.scala 26:13] + node _T_1504 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1505 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1506 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1507 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1514 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1514 is invalid @[RVC.scala 21:19] + _T_1514.bits <= io.in @[RVC.scala 22:14] + _T_1514.rd <= _T_1504 @[RVC.scala 23:12] + _T_1514.rs1 <= _T_1505 @[RVC.scala 24:13] + _T_1514.rs2 <= _T_1506 @[RVC.scala 25:13] + _T_1514.rs3 <= _T_1507 @[RVC.scala 26:13] + node _T_1520 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1521 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1522 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1523 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1530 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1530 is invalid @[RVC.scala 21:19] + _T_1530.bits <= io.in @[RVC.scala 22:14] + _T_1530.rd <= _T_1520 @[RVC.scala 23:12] + _T_1530.rs1 <= _T_1521 @[RVC.scala 24:13] + _T_1530.rs2 <= _T_1522 @[RVC.scala 25:13] + _T_1530.rs3 <= _T_1523 @[RVC.scala 26:13] + node _T_1536 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1537 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1538 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1539 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1546 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1546 is invalid @[RVC.scala 21:19] + _T_1546.bits <= io.in @[RVC.scala 22:14] + _T_1546.rd <= _T_1536 @[RVC.scala 23:12] + _T_1546.rs1 <= _T_1537 @[RVC.scala 24:13] + _T_1546.rs2 <= _T_1538 @[RVC.scala 25:13] + _T_1546.rs3 <= _T_1539 @[RVC.scala 26:13] + node _T_1552 = bits(io.in, 1, 0) @[RVC.scala 150:12] + node _T_1553 = bits(io.in, 15, 13) @[RVC.scala 150:20] + node _T_1554 = cat(_T_1552, _T_1553) @[Cat.scala 30:58] + node _T_1556 = and(_T_1554, UInt<4>("h0f")) @[Package.scala 18:26] + node _T_1558 = geq(_T_1554, UInt<5>("h010")) @[Package.scala 19:17] + node _T_1560 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26] + node _T_1562 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17] + node _T_1564 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1566 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1568 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1570 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1572 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1574 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1575 = mux(_T_1574, _T_1546, _T_1530) @[Package.scala 19:12] + node _T_1582 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1584 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1585 = mux(_T_1584, _T_1514, _T_1498) @[Package.scala 19:12] + node _T_1591 = mux(_T_1570, _T_1575, _T_1585) @[Package.scala 19:12] + node _T_1598 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1600 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1602 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1604 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1605 = mux(_T_1604, _T_1482, _T_1466) @[Package.scala 19:12] + node _T_1612 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1614 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1615 = mux(_T_1614, _T_1450, _T_1434) @[Package.scala 19:12] + node _T_1621 = mux(_T_1600, _T_1605, _T_1615) @[Package.scala 19:12] + node _T_1627 = mux(_T_1566, _T_1591, _T_1621) @[Package.scala 19:12] + node _T_1634 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1636 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1638 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1640 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1642 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1644 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1645 = mux(_T_1644, _T_1418, _T_1381) @[Package.scala 19:12] + node _T_1652 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1654 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1655 = mux(_T_1654, _T_1344, _T_1307) @[Package.scala 19:12] + node _T_1661 = mux(_T_1640, _T_1645, _T_1655) @[Package.scala 19:12] + node _T_1668 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1670 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1672 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1674 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1675 = mux(_T_1674, _T_1166, _T_1135) @[Package.scala 19:12] + node _T_1682 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1684 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1685 = mux(_T_1684, _T_1104, _T_1073) @[Package.scala 19:12] + node _T_1691 = mux(_T_1670, _T_1675, _T_1685) @[Package.scala 19:12] + node _T_1697 = mux(_T_1636, _T_1661, _T_1691) @[Package.scala 19:12] + node _T_1703 = mux(_T_1562, _T_1627, _T_1697) @[Package.scala 19:12] + node _T_1710 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26] + node _T_1712 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17] + node _T_1714 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1716 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1718 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1720 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1722 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1724 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1725 = mux(_T_1724, _T_1046, _T_951) @[Package.scala 19:12] + node _T_1732 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1734 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1735 = mux(_T_1734, _T_854, _T_739) @[Package.scala 19:12] + node _T_1741 = mux(_T_1720, _T_1725, _T_1735) @[Package.scala 19:12] + node _T_1748 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1750 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1752 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1754 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1755 = mux(_T_1754, _T_580, _T_472) @[Package.scala 19:12] + node _T_1762 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1764 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1765 = mux(_T_1764, _T_439, _T_401) @[Package.scala 19:12] + node _T_1771 = mux(_T_1750, _T_1755, _T_1765) @[Package.scala 19:12] + node _T_1777 = mux(_T_1716, _T_1741, _T_1771) @[Package.scala 19:12] + node _T_1784 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1786 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1788 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1790 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1792 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1794 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1795 = mux(_T_1794, _T_368, _T_321) @[Package.scala 19:12] + node _T_1802 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1804 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1805 = mux(_T_1804, _T_270, _T_223) @[Package.scala 19:12] + node _T_1811 = mux(_T_1790, _T_1795, _T_1805) @[Package.scala 19:12] + node _T_1818 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1820 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1822 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1824 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1825 = mux(_T_1824, _T_172, _T_133) @[Package.scala 19:12] + node _T_1832 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1834 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1835 = mux(_T_1834, _T_92, _T_53) @[Package.scala 19:12] + node _T_1841 = mux(_T_1820, _T_1825, _T_1835) @[Package.scala 19:12] + node _T_1847 = mux(_T_1786, _T_1811, _T_1841) @[Package.scala 19:12] + node _T_1853 = mux(_T_1712, _T_1777, _T_1847) @[Package.scala 19:12] + node _T_1859 = mux(_T_1558, _T_1703, _T_1853) @[Package.scala 19:12] + io.out <- _T_1859 @[RVC.scala 163:12] + + module IBuf : + input clock : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - - io is invalid - inst T_1060 of BroadcastVoluntaryReleaseTracker - T_1060.io is invalid - T_1060.clk <= clk - T_1060.reset <= reset - inst T_1061 of BroadcastAcquireTracker - T_1061.io is invalid - T_1061.clk <= clk - T_1061.reset <= reset - inst T_1062 of BroadcastAcquireTracker_27 - T_1062.io is invalid - T_1062.clk <= clk - T_1062.reset <= reset - inst T_1063 of BroadcastAcquireTracker_28 - T_1063.io is invalid - T_1063.clk <= clk - T_1063.reset <= reset - inst T_1064 of BroadcastAcquireTracker_29 - T_1064.io is invalid - T_1064.clk <= clk - T_1064.reset <= reset - inst T_1065 of BroadcastAcquireTracker_30 - T_1065.io is invalid - T_1065.clk <= clk - T_1065.reset <= reset - inst T_1066 of BroadcastAcquireTracker_31 - T_1066.io is invalid - T_1066.clk <= clk - T_1066.reset <= reset - inst T_1067 of BroadcastAcquireTracker_32 - T_1067.io is invalid - T_1067.clk <= clk - T_1067.reset <= reset - T_1060.io.incoherent <= io.incoherent - T_1061.io.incoherent <= io.incoherent - T_1062.io.incoherent <= io.incoherent - T_1063.io.incoherent <= io.incoherent - T_1064.io.incoherent <= io.incoherent - T_1065.io.incoherent <= io.incoherent - T_1066.io.incoherent <= io.incoherent - T_1067.io.incoherent <= io.incoherent - reg sdq : UInt<128>[4], clk - reg sdq_val : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - node T_1085 = not(sdq_val) - node T_1086 = bits(T_1085, 0, 0) - node T_1087 = bits(T_1085, 1, 1) - node T_1088 = bits(T_1085, 2, 2) - node T_1089 = bits(T_1085, 3, 3) - wire T_1091 : UInt<1>[4] - T_1091[0] <= T_1086 - T_1091[1] <= T_1087 - T_1091[2] <= T_1088 - T_1091[3] <= T_1089 - node T_1101 = mux(T_1091[2], UInt<2>("h02"), UInt<2>("h03")) - node T_1102 = mux(T_1091[1], UInt<1>("h01"), T_1101) - node sdq_alloc_id = mux(T_1091[0], UInt<1>("h00"), T_1102) - node T_1104 = not(sdq_val) - node T_1106 = eq(T_1104, UInt<1>("h00")) - node sdq_rdy = eq(T_1106, UInt<1>("h00")) - node T_1109 = and(io.inner.acquire.ready, io.inner.acquire.valid) - wire T_1114 : UInt<3>[3] - T_1114[0] <= UInt<3>("h02") - T_1114[1] <= UInt<3>("h03") - T_1114[2] <= UInt<3>("h04") - node T_1119 = eq(T_1114[0], io.inner.acquire.bits.a_type) - node T_1120 = eq(T_1114[1], io.inner.acquire.bits.a_type) - node T_1121 = eq(T_1114[2], io.inner.acquire.bits.a_type) - node T_1123 = or(UInt<1>("h00"), T_1119) - node T_1124 = or(T_1123, T_1120) - node T_1125 = or(T_1124, T_1121) - node T_1126 = and(io.inner.acquire.bits.is_builtin_type, T_1125) - node sdq_enq = and(T_1109, T_1126) - when sdq_enq : - sdq[sdq_alloc_id] <= io.inner.acquire.bits.data - skip - wire T_1130 : UInt<1>[8] - T_1130[0] <= T_1060.io.has_acquire_conflict - T_1130[1] <= T_1061.io.has_acquire_conflict - T_1130[2] <= T_1062.io.has_acquire_conflict - T_1130[3] <= T_1063.io.has_acquire_conflict - T_1130[4] <= T_1064.io.has_acquire_conflict - T_1130[5] <= T_1065.io.has_acquire_conflict - T_1130[6] <= T_1066.io.has_acquire_conflict - T_1130[7] <= T_1067.io.has_acquire_conflict - node T_1140 = cat(T_1130[7], T_1130[6]) - node T_1141 = cat(T_1130[5], T_1130[4]) - node T_1142 = cat(T_1140, T_1141) - node T_1143 = cat(T_1130[3], T_1130[2]) - node T_1144 = cat(T_1130[1], T_1130[0]) - node T_1145 = cat(T_1143, T_1144) - node acquireConflicts = cat(T_1142, T_1145) - wire T_1148 : UInt<1>[8] - T_1148[0] <= T_1060.io.has_acquire_match - T_1148[1] <= T_1061.io.has_acquire_match - T_1148[2] <= T_1062.io.has_acquire_match - T_1148[3] <= T_1063.io.has_acquire_match - T_1148[4] <= T_1064.io.has_acquire_match - T_1148[5] <= T_1065.io.has_acquire_match - T_1148[6] <= T_1066.io.has_acquire_match - T_1148[7] <= T_1067.io.has_acquire_match - node T_1158 = cat(T_1148[7], T_1148[6]) - node T_1159 = cat(T_1148[5], T_1148[4]) - node T_1160 = cat(T_1158, T_1159) - node T_1161 = cat(T_1148[3], T_1148[2]) - node T_1162 = cat(T_1148[1], T_1148[0]) - node T_1163 = cat(T_1161, T_1162) - node acquireMatches = cat(T_1160, T_1163) - wire T_1166 : UInt<1>[8] - T_1166[0] <= T_1060.io.inner.acquire.ready - T_1166[1] <= T_1061.io.inner.acquire.ready - T_1166[2] <= T_1062.io.inner.acquire.ready - T_1166[3] <= T_1063.io.inner.acquire.ready - T_1166[4] <= T_1064.io.inner.acquire.ready - T_1166[5] <= T_1065.io.inner.acquire.ready - T_1166[6] <= T_1066.io.inner.acquire.ready - T_1166[7] <= T_1067.io.inner.acquire.ready - node T_1176 = cat(T_1166[7], T_1166[6]) - node T_1177 = cat(T_1166[5], T_1166[4]) - node T_1178 = cat(T_1176, T_1177) - node T_1179 = cat(T_1166[3], T_1166[2]) - node T_1180 = cat(T_1166[1], T_1166[0]) - node T_1181 = cat(T_1179, T_1180) - node acquireReadys = cat(T_1178, T_1181) - node T_1184 = neq(acquireMatches, UInt<1>("h00")) - node T_1185 = bits(acquireMatches, 0, 0) - node T_1186 = bits(acquireMatches, 1, 1) - node T_1187 = bits(acquireMatches, 2, 2) - node T_1188 = bits(acquireMatches, 3, 3) - node T_1189 = bits(acquireMatches, 4, 4) - node T_1190 = bits(acquireMatches, 5, 5) - node T_1191 = bits(acquireMatches, 6, 6) - node T_1192 = bits(acquireMatches, 7, 7) - wire T_1194 : UInt<1>[8] - T_1194[0] <= T_1185 - T_1194[1] <= T_1186 - T_1194[2] <= T_1187 - T_1194[3] <= T_1188 - T_1194[4] <= T_1189 - T_1194[5] <= T_1190 - T_1194[6] <= T_1191 - T_1194[7] <= T_1192 - node T_1212 = mux(T_1194[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1213 = mux(T_1194[5], UInt<3>("h05"), T_1212) - node T_1214 = mux(T_1194[4], UInt<3>("h04"), T_1213) - node T_1215 = mux(T_1194[3], UInt<2>("h03"), T_1214) - node T_1216 = mux(T_1194[2], UInt<2>("h02"), T_1215) - node T_1217 = mux(T_1194[1], UInt<1>("h01"), T_1216) - node T_1218 = mux(T_1194[0], UInt<1>("h00"), T_1217) - node T_1219 = bits(acquireReadys, 0, 0) - node T_1220 = bits(acquireReadys, 1, 1) - node T_1221 = bits(acquireReadys, 2, 2) - node T_1222 = bits(acquireReadys, 3, 3) - node T_1223 = bits(acquireReadys, 4, 4) - node T_1224 = bits(acquireReadys, 5, 5) - node T_1225 = bits(acquireReadys, 6, 6) - node T_1226 = bits(acquireReadys, 7, 7) - wire T_1228 : UInt<1>[8] - T_1228[0] <= T_1219 - T_1228[1] <= T_1220 - T_1228[2] <= T_1221 - T_1228[3] <= T_1222 - T_1228[4] <= T_1223 - T_1228[5] <= T_1224 - T_1228[6] <= T_1225 - T_1228[7] <= T_1226 - node T_1246 = mux(T_1228[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1247 = mux(T_1228[5], UInt<3>("h05"), T_1246) - node T_1248 = mux(T_1228[4], UInt<3>("h04"), T_1247) - node T_1249 = mux(T_1228[3], UInt<2>("h03"), T_1248) - node T_1250 = mux(T_1228[2], UInt<2>("h02"), T_1249) - node T_1251 = mux(T_1228[1], UInt<1>("h01"), T_1250) - node T_1252 = mux(T_1228[0], UInt<1>("h00"), T_1251) - node acquire_idx = mux(T_1184, T_1218, T_1252) - node T_1255 = neq(acquireConflicts, UInt<1>("h00")) - node T_1257 = eq(sdq_rdy, UInt<1>("h00")) - node block_acquires = or(T_1255, T_1257) - node T_1260 = neq(acquireReadys, UInt<1>("h00")) - node T_1262 = eq(block_acquires, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - io.inner.acquire.ready <= T_1263 - T_1060.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1310 : {idx : UInt<2>, loc : UInt<2>} - T_1310 is invalid - T_1310.idx <= sdq_alloc_id - T_1310.loc <= UInt<1>("h00") - node T_1356 = cat(T_1310.idx, T_1310.loc) - T_1060.io.inner.acquire.bits.data <= T_1356 - node T_1358 = eq(block_acquires, UInt<1>("h00")) - node T_1359 = and(io.inner.acquire.valid, T_1358) - node T_1361 = eq(acquire_idx, UInt<1>("h00")) - node T_1362 = and(T_1359, T_1361) - T_1060.io.inner.acquire.valid <= T_1362 - T_1061.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1409 : {idx : UInt<2>, loc : UInt<2>} - T_1409 is invalid - T_1409.idx <= sdq_alloc_id - T_1409.loc <= UInt<1>("h00") - node T_1455 = cat(T_1409.idx, T_1409.loc) - T_1061.io.inner.acquire.bits.data <= T_1455 - node T_1457 = eq(block_acquires, UInt<1>("h00")) - node T_1458 = and(io.inner.acquire.valid, T_1457) - node T_1460 = eq(acquire_idx, UInt<1>("h01")) - node T_1461 = and(T_1458, T_1460) - T_1061.io.inner.acquire.valid <= T_1461 - T_1062.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1508 : {idx : UInt<2>, loc : UInt<2>} - T_1508 is invalid - T_1508.idx <= sdq_alloc_id - T_1508.loc <= UInt<1>("h00") - node T_1554 = cat(T_1508.idx, T_1508.loc) - T_1062.io.inner.acquire.bits.data <= T_1554 - node T_1556 = eq(block_acquires, UInt<1>("h00")) - node T_1557 = and(io.inner.acquire.valid, T_1556) - node T_1559 = eq(acquire_idx, UInt<2>("h02")) - node T_1560 = and(T_1557, T_1559) - T_1062.io.inner.acquire.valid <= T_1560 - T_1063.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1607 : {idx : UInt<2>, loc : UInt<2>} - T_1607 is invalid - T_1607.idx <= sdq_alloc_id - T_1607.loc <= UInt<1>("h00") - node T_1653 = cat(T_1607.idx, T_1607.loc) - T_1063.io.inner.acquire.bits.data <= T_1653 - node T_1655 = eq(block_acquires, UInt<1>("h00")) - node T_1656 = and(io.inner.acquire.valid, T_1655) - node T_1658 = eq(acquire_idx, UInt<2>("h03")) - node T_1659 = and(T_1656, T_1658) - T_1063.io.inner.acquire.valid <= T_1659 - T_1064.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1706 : {idx : UInt<2>, loc : UInt<2>} - T_1706 is invalid - T_1706.idx <= sdq_alloc_id - T_1706.loc <= UInt<1>("h00") - node T_1752 = cat(T_1706.idx, T_1706.loc) - T_1064.io.inner.acquire.bits.data <= T_1752 - node T_1754 = eq(block_acquires, UInt<1>("h00")) - node T_1755 = and(io.inner.acquire.valid, T_1754) - node T_1757 = eq(acquire_idx, UInt<3>("h04")) - node T_1758 = and(T_1755, T_1757) - T_1064.io.inner.acquire.valid <= T_1758 - T_1065.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1805 : {idx : UInt<2>, loc : UInt<2>} - T_1805 is invalid - T_1805.idx <= sdq_alloc_id - T_1805.loc <= UInt<1>("h00") - node T_1851 = cat(T_1805.idx, T_1805.loc) - T_1065.io.inner.acquire.bits.data <= T_1851 - node T_1853 = eq(block_acquires, UInt<1>("h00")) - node T_1854 = and(io.inner.acquire.valid, T_1853) - node T_1856 = eq(acquire_idx, UInt<3>("h05")) - node T_1857 = and(T_1854, T_1856) - T_1065.io.inner.acquire.valid <= T_1857 - T_1066.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1904 : {idx : UInt<2>, loc : UInt<2>} - T_1904 is invalid - T_1904.idx <= sdq_alloc_id - T_1904.loc <= UInt<1>("h00") - node T_1950 = cat(T_1904.idx, T_1904.loc) - T_1066.io.inner.acquire.bits.data <= T_1950 - node T_1952 = eq(block_acquires, UInt<1>("h00")) - node T_1953 = and(io.inner.acquire.valid, T_1952) - node T_1955 = eq(acquire_idx, UInt<3>("h06")) - node T_1956 = and(T_1953, T_1955) - T_1066.io.inner.acquire.valid <= T_1956 - T_1067.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_2003 : {idx : UInt<2>, loc : UInt<2>} - T_2003 is invalid - T_2003.idx <= sdq_alloc_id - T_2003.loc <= UInt<1>("h00") - node T_2049 = cat(T_2003.idx, T_2003.loc) - T_1067.io.inner.acquire.bits.data <= T_2049 - node T_2051 = eq(block_acquires, UInt<1>("h00")) - node T_2052 = and(io.inner.acquire.valid, T_2051) - node T_2054 = eq(acquire_idx, UInt<3>("h07")) - node T_2055 = and(T_2052, T_2054) - T_1067.io.inner.acquire.valid <= T_2055 - node T_2056 = and(io.inner.release.ready, io.inner.release.valid) - node T_2057 = and(T_2056, io.inner.release.bits.voluntary) - wire T_2059 : UInt<2>[3] - T_2059[0] <= UInt<1>("h00") - T_2059[1] <= UInt<1>("h01") - T_2059[2] <= UInt<2>("h02") - node T_2064 = eq(T_2059[0], io.inner.release.bits.r_type) - node T_2065 = eq(T_2059[1], io.inner.release.bits.r_type) - node T_2066 = eq(T_2059[2], io.inner.release.bits.r_type) - node T_2068 = or(UInt<1>("h00"), T_2064) - node T_2069 = or(T_2068, T_2065) - node T_2070 = or(T_2069, T_2066) - node vwbdq_enq = and(T_2057, T_2070) - reg rel_data_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when vwbdq_enq : - node T_2075 = eq(rel_data_cnt, UInt<2>("h03")) - node T_2077 = and(UInt<1>("h00"), T_2075) - node T_2080 = add(rel_data_cnt, UInt<1>("h01")) - node T_2081 = tail(T_2080, 1) - node T_2082 = mux(T_2077, UInt<1>("h00"), T_2081) - rel_data_cnt <= T_2082 - skip - node rel_data_done = and(vwbdq_enq, T_2075) - reg vwbdq : UInt<128>[4], clk - when vwbdq_enq : - vwbdq[rel_data_cnt] <= io.inner.release.bits.data - skip - wire T_2101 : UInt<1>[8] - T_2101[0] <= T_1060.io.inner.release.ready - T_2101[1] <= T_1061.io.inner.release.ready - T_2101[2] <= T_1062.io.inner.release.ready - T_2101[3] <= T_1063.io.inner.release.ready - T_2101[4] <= T_1064.io.inner.release.ready - T_2101[5] <= T_1065.io.inner.release.ready - T_2101[6] <= T_1066.io.inner.release.ready - T_2101[7] <= T_1067.io.inner.release.ready - node T_2111 = cat(T_2101[7], T_2101[6]) - node T_2112 = cat(T_2101[5], T_2101[4]) - node T_2113 = cat(T_2111, T_2112) - node T_2114 = cat(T_2101[3], T_2101[2]) - node T_2115 = cat(T_2101[1], T_2101[0]) - node T_2116 = cat(T_2114, T_2115) - node releaseReadys = cat(T_2113, T_2116) - wire T_2119 : UInt<1>[8] - T_2119[0] <= T_1060.io.has_release_match - T_2119[1] <= T_1061.io.has_release_match - T_2119[2] <= T_1062.io.has_release_match - T_2119[3] <= T_1063.io.has_release_match - T_2119[4] <= T_1064.io.has_release_match - T_2119[5] <= T_1065.io.has_release_match - T_2119[6] <= T_1066.io.has_release_match - T_2119[7] <= T_1067.io.has_release_match - node T_2129 = cat(T_2119[7], T_2119[6]) - node T_2130 = cat(T_2119[5], T_2119[4]) - node T_2131 = cat(T_2129, T_2130) - node T_2132 = cat(T_2119[3], T_2119[2]) - node T_2133 = cat(T_2119[1], T_2119[0]) - node T_2134 = cat(T_2132, T_2133) - node releaseMatches = cat(T_2131, T_2134) - node T_2136 = bits(releaseMatches, 0, 0) - node T_2137 = bits(releaseMatches, 1, 1) - node T_2138 = bits(releaseMatches, 2, 2) - node T_2139 = bits(releaseMatches, 3, 3) - node T_2140 = bits(releaseMatches, 4, 4) - node T_2141 = bits(releaseMatches, 5, 5) - node T_2142 = bits(releaseMatches, 6, 6) - node T_2143 = bits(releaseMatches, 7, 7) - wire T_2145 : UInt<1>[8] - T_2145[0] <= T_2136 - T_2145[1] <= T_2137 - T_2145[2] <= T_2138 - T_2145[3] <= T_2139 - T_2145[4] <= T_2140 - T_2145[5] <= T_2141 - T_2145[6] <= T_2142 - T_2145[7] <= T_2143 - node T_2163 = mux(T_2145[6], UInt<3>("h06"), UInt<3>("h07")) - node T_2164 = mux(T_2145[5], UInt<3>("h05"), T_2163) - node T_2165 = mux(T_2145[4], UInt<3>("h04"), T_2164) - node T_2166 = mux(T_2145[3], UInt<2>("h03"), T_2165) - node T_2167 = mux(T_2145[2], UInt<2>("h02"), T_2166) - node T_2168 = mux(T_2145[1], UInt<1>("h01"), T_2167) - node release_idx = mux(T_2145[0], UInt<1>("h00"), T_2168) - node T_2170 = dshr(releaseReadys, release_idx) - node T_2171 = bits(T_2170, 0, 0) - io.inner.release.ready <= T_2171 - node T_2173 = eq(release_idx, UInt<1>("h00")) - node T_2174 = and(io.inner.release.valid, T_2173) - T_1060.io.inner.release.valid <= T_2174 - T_1060.io.inner.release.bits <- io.inner.release.bits - wire T_2221 : {idx : UInt<2>, loc : UInt<2>} - T_2221 is invalid - T_2221.idx <= rel_data_cnt - T_2221.loc <= UInt<1>("h01") - node T_2267 = cat(T_2221.idx, T_2221.loc) - T_1060.io.inner.release.bits.data <= T_2267 - node T_2269 = eq(release_idx, UInt<1>("h01")) - node T_2270 = and(io.inner.release.valid, T_2269) - T_1061.io.inner.release.valid <= T_2270 - T_1061.io.inner.release.bits <- io.inner.release.bits - wire T_2317 : {idx : UInt<2>, loc : UInt<2>} - T_2317 is invalid - T_2317.idx <= rel_data_cnt - T_2317.loc <= UInt<2>("h02") - node T_2363 = cat(T_2317.idx, T_2317.loc) - T_1061.io.inner.release.bits.data <= T_2363 - node T_2365 = eq(release_idx, UInt<2>("h02")) - node T_2366 = and(io.inner.release.valid, T_2365) - T_1062.io.inner.release.valid <= T_2366 - T_1062.io.inner.release.bits <- io.inner.release.bits - wire T_2413 : {idx : UInt<2>, loc : UInt<2>} - T_2413 is invalid - T_2413.idx <= rel_data_cnt - T_2413.loc <= UInt<2>("h02") - node T_2459 = cat(T_2413.idx, T_2413.loc) - T_1062.io.inner.release.bits.data <= T_2459 - node T_2461 = eq(release_idx, UInt<2>("h03")) - node T_2462 = and(io.inner.release.valid, T_2461) - T_1063.io.inner.release.valid <= T_2462 - T_1063.io.inner.release.bits <- io.inner.release.bits - wire T_2509 : {idx : UInt<2>, loc : UInt<2>} - T_2509 is invalid - T_2509.idx <= rel_data_cnt - T_2509.loc <= UInt<2>("h02") - node T_2555 = cat(T_2509.idx, T_2509.loc) - T_1063.io.inner.release.bits.data <= T_2555 - node T_2557 = eq(release_idx, UInt<3>("h04")) - node T_2558 = and(io.inner.release.valid, T_2557) - T_1064.io.inner.release.valid <= T_2558 - T_1064.io.inner.release.bits <- io.inner.release.bits - wire T_2605 : {idx : UInt<2>, loc : UInt<2>} - T_2605 is invalid - T_2605.idx <= rel_data_cnt - T_2605.loc <= UInt<2>("h02") - node T_2651 = cat(T_2605.idx, T_2605.loc) - T_1064.io.inner.release.bits.data <= T_2651 - node T_2653 = eq(release_idx, UInt<3>("h05")) - node T_2654 = and(io.inner.release.valid, T_2653) - T_1065.io.inner.release.valid <= T_2654 - T_1065.io.inner.release.bits <- io.inner.release.bits - wire T_2701 : {idx : UInt<2>, loc : UInt<2>} - T_2701 is invalid - T_2701.idx <= rel_data_cnt - T_2701.loc <= UInt<2>("h02") - node T_2747 = cat(T_2701.idx, T_2701.loc) - T_1065.io.inner.release.bits.data <= T_2747 - node T_2749 = eq(release_idx, UInt<3>("h06")) - node T_2750 = and(io.inner.release.valid, T_2749) - T_1066.io.inner.release.valid <= T_2750 - T_1066.io.inner.release.bits <- io.inner.release.bits - wire T_2797 : {idx : UInt<2>, loc : UInt<2>} - T_2797 is invalid - T_2797.idx <= rel_data_cnt - T_2797.loc <= UInt<2>("h02") - node T_2843 = cat(T_2797.idx, T_2797.loc) - T_1066.io.inner.release.bits.data <= T_2843 - node T_2845 = eq(release_idx, UInt<3>("h07")) - node T_2846 = and(io.inner.release.valid, T_2845) - T_1067.io.inner.release.valid <= T_2846 - T_1067.io.inner.release.bits <- io.inner.release.bits - wire T_2893 : {idx : UInt<2>, loc : UInt<2>} - T_2893 is invalid - T_2893.idx <= rel_data_cnt - T_2893.loc <= UInt<2>("h02") - node T_2939 = cat(T_2893.idx, T_2893.loc) - T_1067.io.inner.release.bits.data <= T_2939 - node T_2941 = neq(releaseMatches, UInt<1>("h00")) - node T_2943 = eq(T_2941, UInt<1>("h00")) - node T_2944 = and(io.inner.release.valid, T_2943) - node T_2946 = eq(T_2944, UInt<1>("h00")) - node T_2948 = eq(reset, UInt<1>("h00")) - when T_2948 : - node T_2950 = eq(T_2946, UInt<1>("h00")) - when T_2950 : - node T_2952 = eq(reset, UInt<1>("h00")) - when T_2952 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - inst T_2953 of LockingRRArbiter_33 - T_2953.io is invalid - T_2953.clk <= clk - T_2953.reset <= reset - io.inner.grant <- T_2953.io.out - T_2953.io.in[0] <- T_1060.io.inner.grant - T_2953.io.in[1] <- T_1061.io.inner.grant - T_2953.io.in[2] <- T_1062.io.inner.grant - T_2953.io.in[3] <- T_1063.io.inner.grant - T_2953.io.in[4] <- T_1064.io.inner.grant - T_2953.io.in[5] <- T_1065.io.inner.grant - T_2953.io.in[6] <- T_1066.io.inner.grant - T_2953.io.in[7] <- T_1067.io.inner.grant - io.inner.grant.bits.data <= io.outer.grant.bits.data - io.inner.grant.bits.addr_beat <= io.outer.grant.bits.addr_beat - inst T_2954 of LockingRRArbiter_34 - T_2954.io is invalid - T_2954.clk <= clk - T_2954.reset <= reset - io.inner.probe <- T_2954.io.out - T_2954.io.in[0] <- T_1060.io.inner.probe - T_2954.io.in[1] <- T_1061.io.inner.probe - T_2954.io.in[2] <- T_1062.io.inner.probe - T_2954.io.in[3] <- T_1063.io.inner.probe - T_2954.io.in[4] <- T_1064.io.inner.probe - T_2954.io.in[5] <- T_1065.io.inner.probe - T_2954.io.in[6] <- T_1066.io.inner.probe - T_2954.io.in[7] <- T_1067.io.inner.probe - T_1060.io.inner.finish.bits <- io.inner.finish.bits - T_1061.io.inner.finish.bits <- io.inner.finish.bits - T_1062.io.inner.finish.bits <- io.inner.finish.bits - T_1063.io.inner.finish.bits <- io.inner.finish.bits - T_1064.io.inner.finish.bits <- io.inner.finish.bits - T_1065.io.inner.finish.bits <- io.inner.finish.bits - T_1066.io.inner.finish.bits <- io.inner.finish.bits - T_1067.io.inner.finish.bits <- io.inner.finish.bits - node T_2956 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) - node T_2957 = and(io.inner.finish.valid, T_2956) - T_1060.io.inner.finish.valid <= T_2957 - node T_2959 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) - node T_2960 = and(io.inner.finish.valid, T_2959) - T_1061.io.inner.finish.valid <= T_2960 - node T_2962 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) - node T_2963 = and(io.inner.finish.valid, T_2962) - T_1062.io.inner.finish.valid <= T_2963 - node T_2965 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) - node T_2966 = and(io.inner.finish.valid, T_2965) - T_1063.io.inner.finish.valid <= T_2966 - node T_2968 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) - node T_2969 = and(io.inner.finish.valid, T_2968) - T_1064.io.inner.finish.valid <= T_2969 - node T_2971 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) - node T_2972 = and(io.inner.finish.valid, T_2971) - T_1065.io.inner.finish.valid <= T_2972 - node T_2974 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) - node T_2975 = and(io.inner.finish.valid, T_2974) - T_1066.io.inner.finish.valid <= T_2975 - node T_2977 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) - node T_2978 = and(io.inner.finish.valid, T_2977) - T_1067.io.inner.finish.valid <= T_2978 - wire T_2980 : UInt<1>[8] - T_2980[0] <= T_1060.io.inner.finish.ready - T_2980[1] <= T_1061.io.inner.finish.ready - T_2980[2] <= T_1062.io.inner.finish.ready - T_2980[3] <= T_1063.io.inner.finish.ready - T_2980[4] <= T_1064.io.inner.finish.ready - T_2980[5] <= T_1065.io.inner.finish.ready - T_2980[6] <= T_1066.io.inner.finish.ready - T_2980[7] <= T_1067.io.inner.finish.ready - io.inner.finish.ready <= T_2980[io.inner.finish.bits.manager_xact_id] - inst outer_arb of ClientUncachedTileLinkIOArbiter - outer_arb.io is invalid - outer_arb.clk <= clk - outer_arb.reset <= reset - outer_arb.io.in[0] <- T_1060.io.outer - outer_arb.io.in[1] <- T_1061.io.outer - outer_arb.io.in[2] <- T_1062.io.outer - outer_arb.io.in[3] <- T_1063.io.outer - outer_arb.io.in[4] <- T_1064.io.outer - outer_arb.io.in[5] <- T_1065.io.outer - outer_arb.io.in[6] <- T_1066.io.outer - outer_arb.io.in[7] <- T_1067.io.outer - wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} - outer_data_ptr is invalid - node T_3130 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) - outer_data_ptr.loc <= T_3130 - node T_3131 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) - outer_data_ptr.idx <= T_3131 - node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) - node T_3133 = and(io.outer.acquire.ready, io.outer.acquire.valid) - wire T_3138 : UInt<3>[3] - T_3138[0] <= UInt<3>("h02") - T_3138[1] <= UInt<3>("h03") - T_3138[2] <= UInt<3>("h04") - node T_3143 = eq(T_3138[0], io.outer.acquire.bits.a_type) - node T_3144 = eq(T_3138[1], io.outer.acquire.bits.a_type) - node T_3145 = eq(T_3138[2], io.outer.acquire.bits.a_type) - node T_3147 = or(UInt<1>("h00"), T_3143) - node T_3148 = or(T_3147, T_3144) - node T_3149 = or(T_3148, T_3145) - node T_3150 = and(io.outer.acquire.bits.is_builtin_type, T_3149) - node T_3151 = and(T_3133, T_3150) - node T_3152 = eq(outer_data_ptr.loc, UInt<1>("h00")) - node free_sdq = and(T_3151, T_3152) - io.outer <- outer_arb.io.out - node T_3156 = eq(UInt<1>("h01"), outer_data_ptr.loc) - node T_3157 = mux(T_3156, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data) - node T_3158 = eq(UInt<1>("h00"), outer_data_ptr.loc) - node T_3159 = mux(T_3158, sdq[outer_data_ptr.idx], T_3157) - io.outer.acquire.bits.data <= T_3159 - node T_3160 = or(io.outer.acquire.valid, sdq_enq) - when T_3160 : - node T_3162 = dshl(UInt<1>("h01"), outer_data_ptr.idx) - node T_3164 = sub(UInt<4>("h00"), free_sdq) - node T_3165 = tail(T_3164, 1) - node T_3166 = and(T_3162, T_3165) - node T_3167 = not(T_3166) - node T_3168 = and(sdq_val, T_3167) - node T_3169 = bits(sdq_val, 3, 0) - node T_3170 = not(T_3169) - node T_3171 = bits(T_3170, 0, 0) - node T_3172 = bits(T_3170, 1, 1) - node T_3173 = bits(T_3170, 2, 2) - node T_3174 = bits(T_3170, 3, 3) - wire T_3180 : UInt<4>[4] - T_3180[0] <= UInt<4>("h01") - T_3180[1] <= UInt<4>("h02") - T_3180[2] <= UInt<4>("h04") - T_3180[3] <= UInt<4>("h08") - node T_3188 = mux(T_3174, T_3180[3], UInt<4>("h00")) - node T_3189 = mux(T_3173, T_3180[2], T_3188) - node T_3190 = mux(T_3172, T_3180[1], T_3189) - node T_3191 = mux(T_3171, T_3180[0], T_3190) - node T_3193 = sub(UInt<4>("h00"), sdq_enq) - node T_3194 = tail(T_3193, 1) - node T_3195 = and(T_3191, T_3194) - node T_3196 = or(T_3168, T_3195) - sdq_val <= T_3196 - skip + output io : {flip imem : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, inst : {flip ready : UInt<1>, valid : UInt<1>, bits : {pf0 : UInt<1>, pf1 : UInt<1>, replay : UInt<1>, btb_hit : UInt<1>, rvc : UInt<1>, inst : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} - module Queue_36 : - input clk : Clock + io is invalid + io is invalid + reg nBufValid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[IBuf.scala 35:47] + reg buf : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}, clock @[IBuf.scala 36:16] + reg ibufBTBHit : UInt<1>, clock @[IBuf.scala 37:23] + reg ibufBTBResp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[IBuf.scala 38:24] + node pcWordBits = bits(io.imem.bits.pc, 1, 1) @[Package.scala 44:13] + wire nReady : UInt<2> + nReady is invalid + nReady <= UInt<2>("h00") + node _T_375 = and(io.imem.bits.btb.valid, io.imem.bits.btb.bits.taken) @[IBuf.scala 43:40] + node _T_377 = add(io.imem.bits.btb.bits.bridx, UInt<1>("h01")) @[IBuf.scala 43:100] + node _T_379 = mux(_T_375, _T_377, UInt<2>("h02")) @[IBuf.scala 43:16] + node _T_380 = sub(_T_379, pcWordBits) @[IBuf.scala 43:124] + node _T_381 = asUInt(_T_380) @[IBuf.scala 43:124] + node nIC = tail(_T_381, 1) @[IBuf.scala 43:124] + node _T_382 = sub(nReady, nBufValid) @[IBuf.scala 44:25] + node _T_383 = asUInt(_T_382) @[IBuf.scala 44:25] + node nICReady = tail(_T_383, 1) @[IBuf.scala 44:25] + node _T_385 = mux(io.imem.valid, nIC, UInt<1>("h00")) @[IBuf.scala 45:19] + node _T_386 = add(_T_385, nBufValid) @[IBuf.scala 45:49] + node nValid = tail(_T_386, 1) @[IBuf.scala 45:49] + node _T_387 = geq(nReady, nBufValid) @[IBuf.scala 46:27] + node _T_388 = geq(nICReady, nIC) @[IBuf.scala 46:53] + node _T_390 = sub(nIC, nICReady) @[IBuf.scala 46:72] + node _T_391 = asUInt(_T_390) @[IBuf.scala 46:72] + node _T_392 = tail(_T_391, 1) @[IBuf.scala 46:72] + node _T_393 = geq(UInt<1>("h01"), _T_392) @[IBuf.scala 46:65] + node _T_394 = or(_T_388, _T_393) @[IBuf.scala 46:60] + node _T_395 = and(_T_387, _T_394) @[IBuf.scala 46:40] + io.imem.ready <= _T_395 @[IBuf.scala 46:17] + node _T_396 = geq(nReady, nBufValid) @[IBuf.scala 49:29] + node _T_398 = sub(nBufValid, nReady) @[IBuf.scala 49:62] + node _T_399 = asUInt(_T_398) @[IBuf.scala 49:62] + node _T_400 = tail(_T_399, 1) @[IBuf.scala 49:62] + node _T_401 = mux(_T_396, UInt<1>("h00"), _T_400) @[IBuf.scala 49:21] + nBufValid <= _T_401 @[IBuf.scala 49:15] + node _T_402 = geq(nReady, nBufValid) @[IBuf.scala 56:35] + node _T_403 = and(io.imem.valid, _T_402) @[IBuf.scala 56:25] + node _T_404 = lt(nICReady, nIC) @[IBuf.scala 56:60] + node _T_405 = and(_T_403, _T_404) @[IBuf.scala 56:48] + node _T_407 = sub(nIC, nICReady) @[IBuf.scala 56:78] + node _T_408 = asUInt(_T_407) @[IBuf.scala 56:78] + node _T_409 = tail(_T_408, 1) @[IBuf.scala 56:78] + node _T_410 = geq(UInt<1>("h01"), _T_409) @[IBuf.scala 56:71] + node _T_411 = and(_T_405, _T_410) @[IBuf.scala 56:66] + when _T_411 : @[IBuf.scala 56:90] + node _T_412 = add(pcWordBits, nICReady) @[IBuf.scala 57:30] + node _T_413 = tail(_T_412, 1) @[IBuf.scala 57:30] + node _T_414 = sub(nIC, nICReady) @[IBuf.scala 58:24] + node _T_415 = asUInt(_T_414) @[IBuf.scala 58:24] + node _T_416 = tail(_T_415, 1) @[IBuf.scala 58:24] + nBufValid <= _T_416 @[IBuf.scala 58:17] + buf <- io.imem.bits @[IBuf.scala 59:11] + node _T_417 = shr(io.imem.bits.data, 16) @[IBuf.scala 133:58] + node _T_418 = cat(_T_417, _T_417) @[Cat.scala 30:58] + node _T_419 = cat(_T_418, io.imem.bits.data) @[Cat.scala 30:58] + node _T_420 = shl(_T_413, 4) @[IBuf.scala 134:19] + node _T_421 = dshr(_T_419, _T_420) @[IBuf.scala 134:10] + node _T_422 = bits(_T_421, 15, 0) @[IBuf.scala 60:59] + buf.data <= _T_422 @[IBuf.scala 60:16] + node _T_423 = not(UInt<40>("h03")) @[IBuf.scala 61:35] + node _T_424 = and(io.imem.bits.pc, _T_423) @[IBuf.scala 61:33] + node _T_425 = shl(nICReady, 1) @[IBuf.scala 61:78] + node _T_426 = add(io.imem.bits.pc, _T_425) @[IBuf.scala 61:66] + node _T_427 = tail(_T_426, 1) @[IBuf.scala 61:66] + node _T_428 = and(_T_427, UInt<40>("h03")) @[IBuf.scala 61:107] + node _T_429 = or(_T_424, _T_428) @[IBuf.scala 61:47] + buf.pc <= _T_429 @[IBuf.scala 61:14] + ibufBTBHit <= io.imem.bits.btb.valid @[IBuf.scala 62:18] + when io.imem.bits.btb.valid : @[IBuf.scala 63:37] + ibufBTBResp <- io.imem.bits.btb.bits @[IBuf.scala 64:21] + node _T_430 = add(io.imem.bits.btb.bits.bridx, nICReady) @[IBuf.scala 65:58] + node _T_431 = tail(_T_430, 1) @[IBuf.scala 65:58] + ibufBTBResp.bridx <= _T_431 @[IBuf.scala 65:27] + skip @[IBuf.scala 63:37] + skip @[IBuf.scala 56:90] + when io.kill : @[IBuf.scala 68:20] + nBufValid <= UInt<1>("h00") @[IBuf.scala 69:17] + skip @[IBuf.scala 68:20] + node _T_434 = add(UInt<2>("h02"), nBufValid) @[IBuf.scala 73:32] + node _T_435 = tail(_T_434, 1) @[IBuf.scala 73:32] + node _T_436 = sub(_T_435, pcWordBits) @[IBuf.scala 73:44] + node _T_437 = asUInt(_T_436) @[IBuf.scala 73:44] + node _T_438 = tail(_T_437, 1) @[IBuf.scala 73:44] + node icShiftAmt = bits(_T_438, 1, 0) @[IBuf.scala 73:57] + node _T_439 = bits(io.imem.bits.data, 15, 0) @[IBuf.scala 74:87] + node _T_440 = cat(_T_439, _T_439) @[Cat.scala 30:58] + node _T_441 = cat(io.imem.bits.data, _T_440) @[Cat.scala 30:58] + node _T_442 = shr(_T_441, 48) @[IBuf.scala 126:58] + node _T_443 = cat(_T_442, _T_442) @[Cat.scala 30:58] + node _T_444 = cat(_T_443, _T_443) @[Cat.scala 30:58] + node _T_445 = cat(_T_444, _T_441) @[Cat.scala 30:58] + node _T_446 = shl(icShiftAmt, 4) @[IBuf.scala 127:19] + node _T_447 = dshl(_T_445, _T_446) @[IBuf.scala 127:10] + node icData = bits(_T_447, 95, 64) @[Package.scala 44:13] + node _T_449 = not(UInt<32>("h00")) @[IBuf.scala 76:17] + node _T_450 = shl(nBufValid, 4) @[IBuf.scala 76:65] + node _T_451 = dshl(_T_449, _T_450) @[IBuf.scala 76:51] + node icMask = bits(_T_451, 31, 0) @[IBuf.scala 76:92] + node _T_452 = and(icData, icMask) @[IBuf.scala 77:21] + node _T_453 = not(icMask) @[IBuf.scala 77:43] + node _T_454 = and(buf.data, _T_453) @[IBuf.scala 77:41] + node inst = or(_T_452, _T_454) @[IBuf.scala 77:30] + node _T_456 = dshl(UInt<1>("h01"), nValid) @[OneHot.scala 47:11] + node _T_458 = sub(_T_456, UInt<1>("h01")) @[IBuf.scala 79:33] + node _T_459 = asUInt(_T_458) @[IBuf.scala 79:33] + node _T_460 = tail(_T_459, 1) @[IBuf.scala 79:33] + node valid = bits(_T_460, 1, 0) @[IBuf.scala 79:37] + node _T_462 = dshl(UInt<1>("h01"), nBufValid) @[OneHot.scala 47:11] + node _T_464 = sub(_T_462, UInt<1>("h01")) @[IBuf.scala 80:37] + node _T_465 = asUInt(_T_464) @[IBuf.scala 80:37] + node bufMask = tail(_T_465, 1) @[IBuf.scala 80:37] + node _T_467 = mux(buf.xcpt_if, bufMask, UInt<1>("h00")) @[IBuf.scala 81:29] + node _T_468 = not(bufMask) @[IBuf.scala 81:89] + node _T_470 = mux(io.imem.bits.xcpt_if, _T_468, UInt<1>("h00")) @[IBuf.scala 81:66] + node _T_471 = or(_T_467, _T_470) @[IBuf.scala 81:61] + node xcpt_if = and(valid, _T_471) @[IBuf.scala 81:23] + node _T_473 = mux(buf.replay, bufMask, UInt<1>("h00")) @[IBuf.scala 82:31] + node _T_474 = not(bufMask) @[IBuf.scala 82:89] + node _T_476 = mux(io.imem.bits.replay, _T_474, UInt<1>("h00")) @[IBuf.scala 82:67] + node _T_477 = or(_T_473, _T_476) @[IBuf.scala 82:62] + node ic_replay = and(valid, _T_477) @[IBuf.scala 82:25] + node _T_479 = dshl(UInt<1>("h01"), ibufBTBResp.bridx) @[OneHot.scala 47:11] + node ibufBTBHitMask = mux(ibufBTBHit, _T_479, UInt<1>("h00")) @[IBuf.scala 83:27] + node _T_482 = eq(io.imem.bits.btb.valid, UInt<1>("h00")) @[IBuf.scala 84:10] + node _T_483 = geq(io.imem.bits.btb.bits.bridx, pcWordBits) @[IBuf.scala 84:65] + node _T_484 = or(_T_482, _T_483) @[IBuf.scala 84:34] + node _T_485 = or(_T_484, reset) @[IBuf.scala 84:9] + node _T_487 = eq(_T_485, UInt<1>("h00")) @[IBuf.scala 84:9] + when _T_487 : @[IBuf.scala 84:9] + printf(clock, UInt<1>(1), "Assertion failed\n at IBuf.scala:84 assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)\n") @[IBuf.scala 84:9] + stop(clock, UInt<1>(1), 1) @[IBuf.scala 84:9] + skip @[IBuf.scala 84:9] + node _T_488 = add(io.imem.bits.btb.bits.bridx, nBufValid) @[IBuf.scala 85:87] + node _T_489 = sub(_T_488, pcWordBits) @[IBuf.scala 85:100] + node _T_490 = asUInt(_T_489) @[IBuf.scala 85:100] + node _T_491 = tail(_T_490, 1) @[IBuf.scala 85:100] + node _T_493 = dshl(UInt<1>("h01"), _T_491) @[OneHot.scala 47:11] + node icBTBHitMask = mux(io.imem.bits.btb.valid, _T_493, UInt<1>("h00")) @[IBuf.scala 85:25] + node _T_495 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 86:35] + node _T_496 = not(bufMask) @[IBuf.scala 86:62] + node _T_497 = and(icBTBHitMask, _T_496) @[IBuf.scala 86:60] + node btbHitMask = or(_T_495, _T_497) @[IBuf.scala 86:45] + node _T_498 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 88:38] + node _T_500 = neq(_T_498, UInt<1>("h00")) @[IBuf.scala 88:49] + node _T_501 = mux(_T_500, ibufBTBResp, io.imem.bits.btb.bits) @[IBuf.scala 88:21] + io.btb_resp <- _T_501 @[IBuf.scala 88:15] + node _T_511 = gt(nBufValid, UInt<1>("h00")) @[IBuf.scala 89:26] + node _T_512 = mux(_T_511, buf.pc, io.imem.bits.pc) @[IBuf.scala 89:15] + io.pc <= _T_512 @[IBuf.scala 89:9] + inst RVCExpander of RVCExpander @[IBuf.scala 93:21] + RVCExpander.io is invalid + RVCExpander.clock <= clock + RVCExpander.reset <= reset + RVCExpander.io.in <= inst @[IBuf.scala 94:15] + io.inst[0].bits.inst <- RVCExpander.io.out @[IBuf.scala 95:26] + io.inst[0].bits.raw <= inst @[IBuf.scala 96:25] + node _T_514 = dshr(ic_replay, UInt<1>("h00")) @[IBuf.scala 99:29] + node _T_515 = bits(_T_514, 0, 0) @[IBuf.scala 99:29] + node _T_517 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 99:37] + node _T_518 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 99:63] + node _T_519 = bits(_T_518, 0, 0) @[IBuf.scala 99:63] + node _T_521 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 99:81] + node _T_522 = tail(_T_521, 1) @[IBuf.scala 99:81] + node _T_523 = dshr(ic_replay, _T_522) @[IBuf.scala 99:79] + node _T_524 = bits(_T_523, 0, 0) @[IBuf.scala 99:79] + node _T_525 = or(_T_519, _T_524) @[IBuf.scala 99:67] + node _T_526 = and(_T_517, _T_525) @[IBuf.scala 99:49] + node _T_527 = or(_T_515, _T_526) @[IBuf.scala 99:33] + node _T_528 = dshr(valid, UInt<1>("h00")) @[IBuf.scala 100:32] + node _T_529 = bits(_T_528, 0, 0) @[IBuf.scala 100:32] + node _T_531 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:61] + node _T_532 = tail(_T_531, 1) @[IBuf.scala 100:61] + node _T_533 = dshr(valid, _T_532) @[IBuf.scala 100:59] + node _T_534 = bits(_T_533, 0, 0) @[IBuf.scala 100:59] + node _T_535 = or(RVCExpander.io.rvc, _T_534) @[IBuf.scala 100:51] + node _T_537 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:77] + node _T_538 = tail(_T_537, 1) @[IBuf.scala 100:77] + node _T_539 = dshr(xcpt_if, _T_538) @[IBuf.scala 100:75] + node _T_540 = bits(_T_539, 0, 0) @[IBuf.scala 100:75] + node _T_541 = or(_T_535, _T_540) @[IBuf.scala 100:65] + node _T_542 = or(_T_541, _T_527) @[IBuf.scala 100:81] + node _T_543 = and(_T_529, _T_542) @[IBuf.scala 100:36] + io.inst[0].valid <= _T_543 @[IBuf.scala 100:24] + node _T_544 = dshr(xcpt_if, UInt<1>("h00")) @[IBuf.scala 101:37] + node _T_545 = bits(_T_544, 0, 0) @[IBuf.scala 101:37] + io.inst[0].bits.pf0 <= _T_545 @[IBuf.scala 101:27] + node _T_547 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 102:30] + node _T_549 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 102:54] + node _T_550 = tail(_T_549, 1) @[IBuf.scala 102:54] + node _T_551 = dshr(xcpt_if, _T_550) @[IBuf.scala 102:52] + node _T_552 = bits(_T_551, 0, 0) @[IBuf.scala 102:52] + node _T_553 = and(_T_547, _T_552) @[IBuf.scala 102:42] + io.inst[0].bits.pf1 <= _T_553 @[IBuf.scala 102:27] + io.inst[0].bits.replay <= _T_527 @[IBuf.scala 103:30] + node _T_554 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 104:44] + node _T_555 = bits(_T_554, 0, 0) @[IBuf.scala 104:44] + node _T_557 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 104:52] + node _T_559 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 104:79] + node _T_560 = tail(_T_559, 1) @[IBuf.scala 104:79] + node _T_561 = dshr(btbHitMask, _T_560) @[IBuf.scala 104:77] + node _T_562 = bits(_T_561, 0, 0) @[IBuf.scala 104:77] + node _T_563 = and(_T_557, _T_562) @[IBuf.scala 104:64] + node _T_564 = or(_T_555, _T_563) @[IBuf.scala 104:48] + io.inst[0].bits.btb_hit <= _T_564 @[IBuf.scala 104:31] + io.inst[0].bits.rvc <= RVCExpander.io.rvc @[IBuf.scala 105:27] + node _T_565 = and(io.inst[0].ready, io.inst[0].valid) @[Decoupled.scala 30:37] + when _T_565 : @[IBuf.scala 107:32] + node _T_567 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 107:61] + node _T_568 = tail(_T_567, 1) @[IBuf.scala 107:61] + node _T_570 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 107:66] + node _T_571 = tail(_T_570, 1) @[IBuf.scala 107:66] + node _T_572 = mux(RVCExpander.io.rvc, _T_568, _T_571) @[IBuf.scala 107:47] + nReady <= _T_572 @[IBuf.scala 107:41] + skip @[IBuf.scala 107:32] + node _T_574 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 109:36] + node _T_575 = tail(_T_574, 1) @[IBuf.scala 109:36] + node _T_577 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 109:41] + node _T_578 = tail(_T_577, 1) @[IBuf.scala 109:41] + node _T_579 = mux(RVCExpander.io.rvc, _T_575, _T_578) @[IBuf.scala 109:22] + node _T_580 = shr(inst, 16) @[IBuf.scala 109:70] + node _T_581 = shr(inst, 32) @[IBuf.scala 109:85] + node _T_582 = mux(RVCExpander.io.rvc, _T_580, _T_581) @[IBuf.scala 109:49] + + module CSRFile : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - - io is invalid - cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[2] - reg T_125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_127 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_125, T_127) - node T_132 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_132) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_138 = and(io.enq.ready, io.enq.valid) - node T_140 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_138, T_140) - node T_142 = and(io.deq.ready, io.deq.valid) - node T_144 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_142, T_144) - when do_enq : - infer mport T_146 = ram[T_125], clk - T_146 <- io.enq.bits - node T_159 = eq(T_125, UInt<1>("h01")) - node T_161 = and(UInt<1>("h00"), T_159) - node T_164 = add(T_125, UInt<1>("h01")) - node T_165 = tail(T_164, 1) - node T_166 = mux(T_161, UInt<1>("h00"), T_165) - T_125 <= T_166 - skip - when do_deq : - node T_168 = eq(T_127, UInt<1>("h01")) - node T_170 = and(UInt<1>("h00"), T_168) - node T_173 = add(T_127, UInt<1>("h01")) - node T_174 = tail(T_173, 1) - node T_175 = mux(T_170, UInt<1>("h00"), T_174) - T_127 <= T_175 - skip - node T_176 = neq(do_enq, do_deq) - when T_176 : - maybe_full <= do_enq - skip - node T_178 = eq(empty, UInt<1>("h00")) - node T_180 = and(UInt<1>("h00"), io.enq.valid) - node T_181 = or(T_178, T_180) - io.deq.valid <= T_181 - node T_183 = eq(full, UInt<1>("h00")) - node T_185 = and(UInt<1>("h00"), io.deq.ready) - node T_186 = or(T_183, T_185) - io.enq.ready <= T_186 - infer mport T_187 = ram[T_127], clk - node T_199 = mux(maybe_flow, io.enq.bits, T_187) - io.deq.bits <- T_199 - node T_211 = sub(T_125, T_127) - node ptr_diff = tail(T_211, 1) - node T_213 = and(maybe_full, ptr_match) - node T_214 = cat(T_213, ptr_diff) - io.count <= T_214 + output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : {flip csr : UInt<12>, fp_illegal : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>}, csr_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, flip badaddr : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], counters : {eventSel : UInt<64>, flip inc : UInt<1>}[0]} - module Queue_37 : - input clk : Clock + io is invalid + io is invalid + wire _T_347 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 194:55] + _T_347 is invalid @[CSR.scala 194:55] + wire _T_377 : UInt<99> + _T_377 is invalid + _T_377 <= UInt<1>("h00") + node _T_378 = bits(_T_377, 0, 0) @[CSR.scala 194:55] + _T_347.uie <= _T_378 @[CSR.scala 194:55] + node _T_379 = bits(_T_377, 1, 1) @[CSR.scala 194:55] + _T_347.sie <= _T_379 @[CSR.scala 194:55] + node _T_380 = bits(_T_377, 2, 2) @[CSR.scala 194:55] + _T_347.hie <= _T_380 @[CSR.scala 194:55] + node _T_381 = bits(_T_377, 3, 3) @[CSR.scala 194:55] + _T_347.mie <= _T_381 @[CSR.scala 194:55] + node _T_382 = bits(_T_377, 4, 4) @[CSR.scala 194:55] + _T_347.upie <= _T_382 @[CSR.scala 194:55] + node _T_383 = bits(_T_377, 5, 5) @[CSR.scala 194:55] + _T_347.spie <= _T_383 @[CSR.scala 194:55] + node _T_384 = bits(_T_377, 6, 6) @[CSR.scala 194:55] + _T_347.hpie <= _T_384 @[CSR.scala 194:55] + node _T_385 = bits(_T_377, 7, 7) @[CSR.scala 194:55] + _T_347.mpie <= _T_385 @[CSR.scala 194:55] + node _T_386 = bits(_T_377, 8, 8) @[CSR.scala 194:55] + _T_347.spp <= _T_386 @[CSR.scala 194:55] + node _T_387 = bits(_T_377, 10, 9) @[CSR.scala 194:55] + _T_347.hpp <= _T_387 @[CSR.scala 194:55] + node _T_388 = bits(_T_377, 12, 11) @[CSR.scala 194:55] + _T_347.mpp <= _T_388 @[CSR.scala 194:55] + node _T_389 = bits(_T_377, 14, 13) @[CSR.scala 194:55] + _T_347.fs <= _T_389 @[CSR.scala 194:55] + node _T_390 = bits(_T_377, 16, 15) @[CSR.scala 194:55] + _T_347.xs <= _T_390 @[CSR.scala 194:55] + node _T_391 = bits(_T_377, 17, 17) @[CSR.scala 194:55] + _T_347.mprv <= _T_391 @[CSR.scala 194:55] + node _T_392 = bits(_T_377, 18, 18) @[CSR.scala 194:55] + _T_347.pum <= _T_392 @[CSR.scala 194:55] + node _T_393 = bits(_T_377, 19, 19) @[CSR.scala 194:55] + _T_347.mxr <= _T_393 @[CSR.scala 194:55] + node _T_394 = bits(_T_377, 20, 20) @[CSR.scala 194:55] + _T_347.tvm <= _T_394 @[CSR.scala 194:55] + node _T_395 = bits(_T_377, 21, 21) @[CSR.scala 194:55] + _T_347.tw <= _T_395 @[CSR.scala 194:55] + node _T_396 = bits(_T_377, 22, 22) @[CSR.scala 194:55] + _T_347.tsr <= _T_396 @[CSR.scala 194:55] + node _T_397 = bits(_T_377, 30, 23) @[CSR.scala 194:55] + _T_347.zero1 <= _T_397 @[CSR.scala 194:55] + node _T_398 = bits(_T_377, 31, 31) @[CSR.scala 194:55] + _T_347.sd_rv32 <= _T_398 @[CSR.scala 194:55] + node _T_399 = bits(_T_377, 33, 32) @[CSR.scala 194:55] + _T_347.uxl <= _T_399 @[CSR.scala 194:55] + node _T_400 = bits(_T_377, 35, 34) @[CSR.scala 194:55] + _T_347.sxl <= _T_400 @[CSR.scala 194:55] + node _T_401 = bits(_T_377, 62, 36) @[CSR.scala 194:55] + _T_347.zero2 <= _T_401 @[CSR.scala 194:55] + node _T_402 = bits(_T_377, 63, 63) @[CSR.scala 194:55] + _T_347.sd <= _T_402 @[CSR.scala 194:55] + node _T_403 = bits(_T_377, 65, 64) @[CSR.scala 194:55] + _T_347.prv <= _T_403 @[CSR.scala 194:55] + node _T_404 = bits(_T_377, 97, 66) @[CSR.scala 194:55] + _T_347.isa <= _T_404 @[CSR.scala 194:55] + node _T_405 = bits(_T_377, 98, 98) @[CSR.scala 194:55] + _T_347.debug <= _T_405 @[CSR.scala 194:55] + wire reset_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + reset_mstatus is invalid + reset_mstatus <- _T_347 + reset_mstatus.mpp <= UInt<2>("h03") @[CSR.scala 195:21] + reset_mstatus.prv <= UInt<2>("h03") @[CSR.scala 196:21] + reg reg_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock with : (reset => (reset, reset_mstatus)) @[CSR.scala 197:24] + wire new_prv : UInt + new_prv is invalid + new_prv <= reg_mstatus.prv + node _T_465 = eq(new_prv, UInt<2>("h02")) @[CSR.scala 697:27] + node _T_467 = mux(_T_465, UInt<1>("h00"), new_prv) @[CSR.scala 697:21] + reg_mstatus.prv <= _T_467 @[CSR.scala 200:19] + wire _T_505 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 202:49] + _T_505 is invalid @[CSR.scala 202:49] + wire _T_524 : UInt<32> + _T_524 is invalid + _T_524 <= UInt<1>("h00") + node _T_525 = bits(_T_524, 1, 0) @[CSR.scala 202:49] + _T_505.prv <= _T_525 @[CSR.scala 202:49] + node _T_526 = bits(_T_524, 2, 2) @[CSR.scala 202:49] + _T_505.step <= _T_526 @[CSR.scala 202:49] + node _T_527 = bits(_T_524, 3, 3) @[CSR.scala 202:49] + _T_505.halt <= _T_527 @[CSR.scala 202:49] + node _T_528 = bits(_T_524, 4, 4) @[CSR.scala 202:49] + _T_505.zero1 <= _T_528 @[CSR.scala 202:49] + node _T_529 = bits(_T_524, 5, 5) @[CSR.scala 202:49] + _T_505.debugint <= _T_529 @[CSR.scala 202:49] + node _T_530 = bits(_T_524, 8, 6) @[CSR.scala 202:49] + _T_505.cause <= _T_530 @[CSR.scala 202:49] + node _T_531 = bits(_T_524, 9, 9) @[CSR.scala 202:49] + _T_505.stoptime <= _T_531 @[CSR.scala 202:49] + node _T_532 = bits(_T_524, 10, 10) @[CSR.scala 202:49] + _T_505.stopcycle <= _T_532 @[CSR.scala 202:49] + node _T_533 = bits(_T_524, 11, 11) @[CSR.scala 202:49] + _T_505.zero2 <= _T_533 @[CSR.scala 202:49] + node _T_534 = bits(_T_524, 12, 12) @[CSR.scala 202:49] + _T_505.ebreaku <= _T_534 @[CSR.scala 202:49] + node _T_535 = bits(_T_524, 13, 13) @[CSR.scala 202:49] + _T_505.ebreaks <= _T_535 @[CSR.scala 202:49] + node _T_536 = bits(_T_524, 14, 14) @[CSR.scala 202:49] + _T_505.ebreakh <= _T_536 @[CSR.scala 202:49] + node _T_537 = bits(_T_524, 15, 15) @[CSR.scala 202:49] + _T_505.ebreakm <= _T_537 @[CSR.scala 202:49] + node _T_538 = bits(_T_524, 27, 16) @[CSR.scala 202:49] + _T_505.zero3 <= _T_538 @[CSR.scala 202:49] + node _T_539 = bits(_T_524, 28, 28) @[CSR.scala 202:49] + _T_505.fullreset <= _T_539 @[CSR.scala 202:49] + node _T_540 = bits(_T_524, 29, 29) @[CSR.scala 202:49] + _T_505.ndreset <= _T_540 @[CSR.scala 202:49] + node _T_541 = bits(_T_524, 31, 30) @[CSR.scala 202:49] + _T_505.xdebugver <= _T_541 @[CSR.scala 202:49] + wire reset_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} + reset_dcsr is invalid + reset_dcsr <- _T_505 + reset_dcsr.xdebugver <= UInt<1>("h01") @[CSR.scala 203:24] + reset_dcsr.prv <= UInt<2>("h03") @[CSR.scala 204:18] + reg reg_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}, clock with : (reset => (reset, reset_dcsr)) @[CSR.scala 205:21] + wire _T_607 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 208:43] + _T_607 is invalid @[CSR.scala 208:43] + wire _T_622 : UInt<13> + _T_622 is invalid + _T_622 <= UInt<1>("h00") + node _T_623 = bits(_T_622, 0, 0) @[CSR.scala 208:43] + _T_607.usip <= _T_623 @[CSR.scala 208:43] + node _T_624 = bits(_T_622, 1, 1) @[CSR.scala 208:43] + _T_607.ssip <= _T_624 @[CSR.scala 208:43] + node _T_625 = bits(_T_622, 2, 2) @[CSR.scala 208:43] + _T_607.hsip <= _T_625 @[CSR.scala 208:43] + node _T_626 = bits(_T_622, 3, 3) @[CSR.scala 208:43] + _T_607.msip <= _T_626 @[CSR.scala 208:43] + node _T_627 = bits(_T_622, 4, 4) @[CSR.scala 208:43] + _T_607.utip <= _T_627 @[CSR.scala 208:43] + node _T_628 = bits(_T_622, 5, 5) @[CSR.scala 208:43] + _T_607.stip <= _T_628 @[CSR.scala 208:43] + node _T_629 = bits(_T_622, 6, 6) @[CSR.scala 208:43] + _T_607.htip <= _T_629 @[CSR.scala 208:43] + node _T_630 = bits(_T_622, 7, 7) @[CSR.scala 208:43] + _T_607.mtip <= _T_630 @[CSR.scala 208:43] + node _T_631 = bits(_T_622, 8, 8) @[CSR.scala 208:43] + _T_607.ueip <= _T_631 @[CSR.scala 208:43] + node _T_632 = bits(_T_622, 9, 9) @[CSR.scala 208:43] + _T_607.seip <= _T_632 @[CSR.scala 208:43] + node _T_633 = bits(_T_622, 10, 10) @[CSR.scala 208:43] + _T_607.heip <= _T_633 @[CSR.scala 208:43] + node _T_634 = bits(_T_622, 11, 11) @[CSR.scala 208:43] + _T_607.meip <= _T_634 @[CSR.scala 208:43] + node _T_635 = bits(_T_622, 12, 12) @[CSR.scala 208:43] + _T_607.rocc <= _T_635 @[CSR.scala 208:43] + wire _T_636 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + _T_636 is invalid + _T_636 <- _T_607 + _T_636.ssip <= UInt<1>("h01") @[CSR.scala 209:14] + _T_636.msip <= UInt<1>("h01") @[CSR.scala 210:14] + _T_636.stip <= UInt<1>("h01") @[CSR.scala 211:14] + _T_636.mtip <= UInt<1>("h01") @[CSR.scala 212:14] + _T_636.meip <= UInt<1>("h01") @[CSR.scala 213:14] + _T_636.seip <= UInt<1>("h01") @[CSR.scala 214:14] + _T_636.rocc <= UInt<1>("h00") @[CSR.scala 215:14] + wire _T_657 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + _T_657 is invalid + _T_657 <- _T_636 + _T_657.msip <= UInt<1>("h00") @[CSR.scala 218:14] + _T_657.mtip <= UInt<1>("h00") @[CSR.scala 219:14] + _T_657.meip <= UInt<1>("h00") @[CSR.scala 220:14] + node _T_674 = cat(_T_636.hsip, _T_636.ssip) @[CSR.scala 222:10] + node _T_675 = cat(_T_674, _T_636.usip) @[CSR.scala 222:10] + node _T_676 = cat(_T_636.stip, _T_636.utip) @[CSR.scala 222:10] + node _T_677 = cat(_T_676, _T_636.msip) @[CSR.scala 222:10] + node _T_678 = cat(_T_677, _T_675) @[CSR.scala 222:10] + node _T_679 = cat(_T_636.ueip, _T_636.mtip) @[CSR.scala 222:10] + node _T_680 = cat(_T_679, _T_636.htip) @[CSR.scala 222:10] + node _T_681 = cat(_T_636.heip, _T_636.seip) @[CSR.scala 222:10] + node _T_682 = cat(_T_636.rocc, _T_636.meip) @[CSR.scala 222:10] + node _T_683 = cat(_T_682, _T_681) @[CSR.scala 222:10] + node _T_684 = cat(_T_683, _T_680) @[CSR.scala 222:10] + node supported_interrupts = cat(_T_684, _T_678) @[CSR.scala 222:10] + node _T_685 = cat(_T_657.hsip, _T_657.ssip) @[CSR.scala 222:22] + node _T_686 = cat(_T_685, _T_657.usip) @[CSR.scala 222:22] + node _T_687 = cat(_T_657.stip, _T_657.utip) @[CSR.scala 222:22] + node _T_688 = cat(_T_687, _T_657.msip) @[CSR.scala 222:22] + node _T_689 = cat(_T_688, _T_686) @[CSR.scala 222:22] + node _T_690 = cat(_T_657.ueip, _T_657.mtip) @[CSR.scala 222:22] + node _T_691 = cat(_T_690, _T_657.htip) @[CSR.scala 222:22] + node _T_692 = cat(_T_657.heip, _T_657.seip) @[CSR.scala 222:22] + node _T_693 = cat(_T_657.rocc, _T_657.meip) @[CSR.scala 222:22] + node _T_694 = cat(_T_693, _T_692) @[CSR.scala 222:22] + node _T_695 = cat(_T_694, _T_691) @[CSR.scala 222:22] + node delegable_interrupts = cat(_T_695, _T_689) @[CSR.scala 222:22] + reg reg_debug : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 232:22] + node effective_prv = cat(reg_debug, reg_mstatus.prv) @[Cat.scala 30:58] + reg reg_dpc : UInt<40>, clock @[CSR.scala 234:20] + reg reg_dscratch : UInt<64>, clock @[CSR.scala 235:25] + reg reg_singleStepped : UInt<1>, clock @[CSR.scala 236:30] + reg reg_tselect : UInt<1>, clock @[CSR.scala 238:24] + reg reg_bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[2], clock @[CSR.scala 239:19] + reg reg_mie : UInt<64>, clock @[CSR.scala 241:20] + reg reg_mideleg : UInt<64>, clock @[CSR.scala 242:24] + reg reg_medeleg : UInt<64>, clock @[CSR.scala 243:24] + reg reg_mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock @[CSR.scala 244:20] + reg reg_mepc : UInt<40>, clock @[CSR.scala 245:21] + reg reg_mcause : UInt<64>, clock @[CSR.scala 246:23] + reg reg_mbadaddr : UInt<40>, clock @[CSR.scala 247:25] + reg reg_mscratch : UInt<64>, clock @[CSR.scala 248:25] + reg reg_mtvec : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[CSR.scala 251:27] + reg reg_mcounteren : UInt<32>, clock @[CSR.scala 254:27] + reg reg_scounteren : UInt<32>, clock @[CSR.scala 255:27] + reg reg_sepc : UInt<40>, clock @[CSR.scala 258:21] + reg reg_scause : UInt<64>, clock @[CSR.scala 259:23] + reg reg_sbadaddr : UInt<40>, clock @[CSR.scala 260:25] + reg reg_sscratch : UInt<64>, clock @[CSR.scala 261:25] + reg reg_stvec : UInt<39>, clock @[CSR.scala 262:22] + reg reg_sptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock @[CSR.scala 263:22] + reg reg_wfi : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 264:20] + reg reg_fflags : UInt<5>, clock @[CSR.scala 266:23] + reg reg_frm : UInt<3>, clock @[CSR.scala 267:20] + reg _T_931 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37] + node _T_932 = add(_T_931, io.retire) @[Counters.scala 48:33] + _T_931 <= _T_932 @[Counters.scala 49:9] + reg _T_934 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27] + node _T_935 = bits(_T_932, 6, 6) @[Counters.scala 53:20] + when _T_935 : @[Counters.scala 53:34] + node _T_937 = add(_T_934, UInt<1>("h01")) @[Counters.scala 53:43] + node _T_938 = tail(_T_937, 1) @[Counters.scala 53:43] + _T_934 <= _T_938 @[Counters.scala 53:38] + skip @[Counters.scala 53:34] + node _T_939 = cat(_T_934, _T_931) @[Cat.scala 30:58] + reg _T_942 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37] + node _T_943 = add(_T_942, UInt<1>("h01")) @[Counters.scala 48:33] + _T_942 <= _T_943 @[Counters.scala 49:9] + reg _T_945 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27] + node _T_946 = bits(_T_943, 6, 6) @[Counters.scala 53:20] + when _T_946 : @[Counters.scala 53:34] + node _T_948 = add(_T_945, UInt<1>("h01")) @[Counters.scala 53:43] + node _T_949 = tail(_T_948, 1) @[Counters.scala 53:43] + _T_945 <= _T_949 @[Counters.scala 53:38] + skip @[Counters.scala 53:34] + node _T_950 = cat(_T_945, _T_942) @[Cat.scala 30:58] + node _T_953 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 274:71] + node _T_954 = or(UInt<1>("h00"), _T_953) @[CSR.scala 274:52] + node _T_956 = mux(_T_954, UInt<3>("h07"), reg_scounteren) @[CSR.scala 274:38] + node hpm_mask = and(reg_mcounteren, _T_956) @[CSR.scala 274:33] + wire mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + mip is invalid + mip <- reg_mip + mip.rocc <= io.rocc_interrupt @[CSR.scala 277:12] + node _T_970 = cat(mip.hsip, mip.ssip) @[CSR.scala 278:22] + node _T_971 = cat(_T_970, mip.usip) @[CSR.scala 278:22] + node _T_972 = cat(mip.stip, mip.utip) @[CSR.scala 278:22] + node _T_973 = cat(_T_972, mip.msip) @[CSR.scala 278:22] + node _T_974 = cat(_T_973, _T_971) @[CSR.scala 278:22] + node _T_975 = cat(mip.ueip, mip.mtip) @[CSR.scala 278:22] + node _T_976 = cat(_T_975, mip.htip) @[CSR.scala 278:22] + node _T_977 = cat(mip.heip, mip.seip) @[CSR.scala 278:22] + node _T_978 = cat(mip.rocc, mip.meip) @[CSR.scala 278:22] + node _T_979 = cat(_T_978, _T_977) @[CSR.scala 278:22] + node _T_980 = cat(_T_979, _T_976) @[CSR.scala 278:22] + node _T_981 = cat(_T_980, _T_974) @[CSR.scala 278:22] + node read_mip = and(_T_981, supported_interrupts) @[CSR.scala 278:29] + node pending_interrupts = and(read_mip, reg_mie) @[CSR.scala 280:37] + node _T_983 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 281:42] + node _T_985 = eq(reg_mstatus.prv, UInt<2>("h03")) @[CSR.scala 281:71] + node _T_986 = and(_T_985, reg_mstatus.mie) @[CSR.scala 281:81] + node _T_987 = or(_T_983, _T_986) @[CSR.scala 281:51] + node _T_988 = not(reg_mideleg) @[CSR.scala 281:123] + node _T_989 = and(pending_interrupts, _T_988) @[CSR.scala 281:121] + node m_interrupts = mux(_T_987, _T_989, UInt<1>("h00")) @[CSR.scala 281:25] + node _T_992 = eq(m_interrupts, UInt<1>("h00")) @[CSR.scala 282:39] + node _T_994 = lt(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:65] + node _T_996 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:93] + node _T_997 = and(_T_996, reg_mstatus.sie) @[CSR.scala 282:103] + node _T_998 = or(_T_994, _T_997) @[CSR.scala 282:73] + node _T_999 = and(_T_992, _T_998) @[CSR.scala 282:45] + node _T_1000 = and(pending_interrupts, reg_mideleg) @[CSR.scala 282:144] + node s_interrupts = mux(_T_999, _T_1000, UInt<1>("h00")) @[CSR.scala 282:25] + node all_interrupts = or(m_interrupts, s_interrupts) @[CSR.scala 283:37] + node _T_1003 = bits(all_interrupts, 0, 0) @[OneHot.scala 39:40] + node _T_1004 = bits(all_interrupts, 1, 1) @[OneHot.scala 39:40] + node _T_1005 = bits(all_interrupts, 2, 2) @[OneHot.scala 39:40] + node _T_1006 = bits(all_interrupts, 3, 3) @[OneHot.scala 39:40] + node _T_1007 = bits(all_interrupts, 4, 4) @[OneHot.scala 39:40] + node _T_1008 = bits(all_interrupts, 5, 5) @[OneHot.scala 39:40] + node _T_1009 = bits(all_interrupts, 6, 6) @[OneHot.scala 39:40] + node _T_1010 = bits(all_interrupts, 7, 7) @[OneHot.scala 39:40] + node _T_1011 = bits(all_interrupts, 8, 8) @[OneHot.scala 39:40] + node _T_1012 = bits(all_interrupts, 9, 9) @[OneHot.scala 39:40] + node _T_1013 = bits(all_interrupts, 10, 10) @[OneHot.scala 39:40] + node _T_1014 = bits(all_interrupts, 11, 11) @[OneHot.scala 39:40] + node _T_1015 = bits(all_interrupts, 12, 12) @[OneHot.scala 39:40] + node _T_1016 = bits(all_interrupts, 13, 13) @[OneHot.scala 39:40] + node _T_1017 = bits(all_interrupts, 14, 14) @[OneHot.scala 39:40] + node _T_1018 = bits(all_interrupts, 15, 15) @[OneHot.scala 39:40] + node _T_1019 = bits(all_interrupts, 16, 16) @[OneHot.scala 39:40] + node _T_1020 = bits(all_interrupts, 17, 17) @[OneHot.scala 39:40] + node _T_1021 = bits(all_interrupts, 18, 18) @[OneHot.scala 39:40] + node _T_1022 = bits(all_interrupts, 19, 19) @[OneHot.scala 39:40] + node _T_1023 = bits(all_interrupts, 20, 20) @[OneHot.scala 39:40] + node _T_1024 = bits(all_interrupts, 21, 21) @[OneHot.scala 39:40] + node _T_1025 = bits(all_interrupts, 22, 22) @[OneHot.scala 39:40] + node _T_1026 = bits(all_interrupts, 23, 23) @[OneHot.scala 39:40] + node _T_1027 = bits(all_interrupts, 24, 24) @[OneHot.scala 39:40] + node _T_1028 = bits(all_interrupts, 25, 25) @[OneHot.scala 39:40] + node _T_1029 = bits(all_interrupts, 26, 26) @[OneHot.scala 39:40] + node _T_1030 = bits(all_interrupts, 27, 27) @[OneHot.scala 39:40] + node _T_1031 = bits(all_interrupts, 28, 28) @[OneHot.scala 39:40] + node _T_1032 = bits(all_interrupts, 29, 29) @[OneHot.scala 39:40] + node _T_1033 = bits(all_interrupts, 30, 30) @[OneHot.scala 39:40] + node _T_1034 = bits(all_interrupts, 31, 31) @[OneHot.scala 39:40] + node _T_1035 = bits(all_interrupts, 32, 32) @[OneHot.scala 39:40] + node _T_1036 = bits(all_interrupts, 33, 33) @[OneHot.scala 39:40] + node _T_1037 = bits(all_interrupts, 34, 34) @[OneHot.scala 39:40] + node _T_1038 = bits(all_interrupts, 35, 35) @[OneHot.scala 39:40] + node _T_1039 = bits(all_interrupts, 36, 36) @[OneHot.scala 39:40] + node _T_1040 = bits(all_interrupts, 37, 37) @[OneHot.scala 39:40] + node _T_1041 = bits(all_interrupts, 38, 38) @[OneHot.scala 39:40] + node _T_1042 = bits(all_interrupts, 39, 39) @[OneHot.scala 39:40] + node _T_1043 = bits(all_interrupts, 40, 40) @[OneHot.scala 39:40] + node _T_1044 = bits(all_interrupts, 41, 41) @[OneHot.scala 39:40] + node _T_1045 = bits(all_interrupts, 42, 42) @[OneHot.scala 39:40] + node _T_1046 = bits(all_interrupts, 43, 43) @[OneHot.scala 39:40] + node _T_1047 = bits(all_interrupts, 44, 44) @[OneHot.scala 39:40] + node _T_1048 = bits(all_interrupts, 45, 45) @[OneHot.scala 39:40] + node _T_1049 = bits(all_interrupts, 46, 46) @[OneHot.scala 39:40] + node _T_1050 = bits(all_interrupts, 47, 47) @[OneHot.scala 39:40] + node _T_1051 = bits(all_interrupts, 48, 48) @[OneHot.scala 39:40] + node _T_1052 = bits(all_interrupts, 49, 49) @[OneHot.scala 39:40] + node _T_1053 = bits(all_interrupts, 50, 50) @[OneHot.scala 39:40] + node _T_1054 = bits(all_interrupts, 51, 51) @[OneHot.scala 39:40] + node _T_1055 = bits(all_interrupts, 52, 52) @[OneHot.scala 39:40] + node _T_1056 = bits(all_interrupts, 53, 53) @[OneHot.scala 39:40] + node _T_1057 = bits(all_interrupts, 54, 54) @[OneHot.scala 39:40] + node _T_1058 = bits(all_interrupts, 55, 55) @[OneHot.scala 39:40] + node _T_1059 = bits(all_interrupts, 56, 56) @[OneHot.scala 39:40] + node _T_1060 = bits(all_interrupts, 57, 57) @[OneHot.scala 39:40] + node _T_1061 = bits(all_interrupts, 58, 58) @[OneHot.scala 39:40] + node _T_1062 = bits(all_interrupts, 59, 59) @[OneHot.scala 39:40] + node _T_1063 = bits(all_interrupts, 60, 60) @[OneHot.scala 39:40] + node _T_1064 = bits(all_interrupts, 61, 61) @[OneHot.scala 39:40] + node _T_1065 = bits(all_interrupts, 62, 62) @[OneHot.scala 39:40] + node _T_1066 = bits(all_interrupts, 63, 63) @[OneHot.scala 39:40] + node _T_1131 = mux(_T_1065, UInt<6>("h03e"), UInt<6>("h03f")) @[Mux.scala 31:69] + node _T_1132 = mux(_T_1064, UInt<6>("h03d"), _T_1131) @[Mux.scala 31:69] + node _T_1133 = mux(_T_1063, UInt<6>("h03c"), _T_1132) @[Mux.scala 31:69] + node _T_1134 = mux(_T_1062, UInt<6>("h03b"), _T_1133) @[Mux.scala 31:69] + node _T_1135 = mux(_T_1061, UInt<6>("h03a"), _T_1134) @[Mux.scala 31:69] + node _T_1136 = mux(_T_1060, UInt<6>("h039"), _T_1135) @[Mux.scala 31:69] + node _T_1137 = mux(_T_1059, UInt<6>("h038"), _T_1136) @[Mux.scala 31:69] + node _T_1138 = mux(_T_1058, UInt<6>("h037"), _T_1137) @[Mux.scala 31:69] + node _T_1139 = mux(_T_1057, UInt<6>("h036"), _T_1138) @[Mux.scala 31:69] + node _T_1140 = mux(_T_1056, UInt<6>("h035"), _T_1139) @[Mux.scala 31:69] + node _T_1141 = mux(_T_1055, UInt<6>("h034"), _T_1140) @[Mux.scala 31:69] + node _T_1142 = mux(_T_1054, UInt<6>("h033"), _T_1141) @[Mux.scala 31:69] + node _T_1143 = mux(_T_1053, UInt<6>("h032"), _T_1142) @[Mux.scala 31:69] + node _T_1144 = mux(_T_1052, UInt<6>("h031"), _T_1143) @[Mux.scala 31:69] + node _T_1145 = mux(_T_1051, UInt<6>("h030"), _T_1144) @[Mux.scala 31:69] + node _T_1146 = mux(_T_1050, UInt<6>("h02f"), _T_1145) @[Mux.scala 31:69] + node _T_1147 = mux(_T_1049, UInt<6>("h02e"), _T_1146) @[Mux.scala 31:69] + node _T_1148 = mux(_T_1048, UInt<6>("h02d"), _T_1147) @[Mux.scala 31:69] + node _T_1149 = mux(_T_1047, UInt<6>("h02c"), _T_1148) @[Mux.scala 31:69] + node _T_1150 = mux(_T_1046, UInt<6>("h02b"), _T_1149) @[Mux.scala 31:69] + node _T_1151 = mux(_T_1045, UInt<6>("h02a"), _T_1150) @[Mux.scala 31:69] + node _T_1152 = mux(_T_1044, UInt<6>("h029"), _T_1151) @[Mux.scala 31:69] + node _T_1153 = mux(_T_1043, UInt<6>("h028"), _T_1152) @[Mux.scala 31:69] + node _T_1154 = mux(_T_1042, UInt<6>("h027"), _T_1153) @[Mux.scala 31:69] + node _T_1155 = mux(_T_1041, UInt<6>("h026"), _T_1154) @[Mux.scala 31:69] + node _T_1156 = mux(_T_1040, UInt<6>("h025"), _T_1155) @[Mux.scala 31:69] + node _T_1157 = mux(_T_1039, UInt<6>("h024"), _T_1156) @[Mux.scala 31:69] + node _T_1158 = mux(_T_1038, UInt<6>("h023"), _T_1157) @[Mux.scala 31:69] + node _T_1159 = mux(_T_1037, UInt<6>("h022"), _T_1158) @[Mux.scala 31:69] + node _T_1160 = mux(_T_1036, UInt<6>("h021"), _T_1159) @[Mux.scala 31:69] + node _T_1161 = mux(_T_1035, UInt<6>("h020"), _T_1160) @[Mux.scala 31:69] + node _T_1162 = mux(_T_1034, UInt<5>("h01f"), _T_1161) @[Mux.scala 31:69] + node _T_1163 = mux(_T_1033, UInt<5>("h01e"), _T_1162) @[Mux.scala 31:69] + node _T_1164 = mux(_T_1032, UInt<5>("h01d"), _T_1163) @[Mux.scala 31:69] + node _T_1165 = mux(_T_1031, UInt<5>("h01c"), _T_1164) @[Mux.scala 31:69] + node _T_1166 = mux(_T_1030, UInt<5>("h01b"), _T_1165) @[Mux.scala 31:69] + node _T_1167 = mux(_T_1029, UInt<5>("h01a"), _T_1166) @[Mux.scala 31:69] + node _T_1168 = mux(_T_1028, UInt<5>("h019"), _T_1167) @[Mux.scala 31:69] + node _T_1169 = mux(_T_1027, UInt<5>("h018"), _T_1168) @[Mux.scala 31:69] + node _T_1170 = mux(_T_1026, UInt<5>("h017"), _T_1169) @[Mux.scala 31:69] + node _T_1171 = mux(_T_1025, UInt<5>("h016"), _T_1170) @[Mux.scala 31:69] + node _T_1172 = mux(_T_1024, UInt<5>("h015"), _T_1171) @[Mux.scala 31:69] + node _T_1173 = mux(_T_1023, UInt<5>("h014"), _T_1172) @[Mux.scala 31:69] + node _T_1174 = mux(_T_1022, UInt<5>("h013"), _T_1173) @[Mux.scala 31:69] + node _T_1175 = mux(_T_1021, UInt<5>("h012"), _T_1174) @[Mux.scala 31:69] + node _T_1176 = mux(_T_1020, UInt<5>("h011"), _T_1175) @[Mux.scala 31:69] + node _T_1177 = mux(_T_1019, UInt<5>("h010"), _T_1176) @[Mux.scala 31:69] + node _T_1178 = mux(_T_1018, UInt<4>("h0f"), _T_1177) @[Mux.scala 31:69] + node _T_1179 = mux(_T_1017, UInt<4>("h0e"), _T_1178) @[Mux.scala 31:69] + node _T_1180 = mux(_T_1016, UInt<4>("h0d"), _T_1179) @[Mux.scala 31:69] + node _T_1181 = mux(_T_1015, UInt<4>("h0c"), _T_1180) @[Mux.scala 31:69] + node _T_1182 = mux(_T_1014, UInt<4>("h0b"), _T_1181) @[Mux.scala 31:69] + node _T_1183 = mux(_T_1013, UInt<4>("h0a"), _T_1182) @[Mux.scala 31:69] + node _T_1184 = mux(_T_1012, UInt<4>("h09"), _T_1183) @[Mux.scala 31:69] + node _T_1185 = mux(_T_1011, UInt<4>("h08"), _T_1184) @[Mux.scala 31:69] + node _T_1186 = mux(_T_1010, UInt<3>("h07"), _T_1185) @[Mux.scala 31:69] + node _T_1187 = mux(_T_1009, UInt<3>("h06"), _T_1186) @[Mux.scala 31:69] + node _T_1188 = mux(_T_1008, UInt<3>("h05"), _T_1187) @[Mux.scala 31:69] + node _T_1189 = mux(_T_1007, UInt<3>("h04"), _T_1188) @[Mux.scala 31:69] + node _T_1190 = mux(_T_1006, UInt<2>("h03"), _T_1189) @[Mux.scala 31:69] + node _T_1191 = mux(_T_1005, UInt<2>("h02"), _T_1190) @[Mux.scala 31:69] + node _T_1192 = mux(_T_1004, UInt<1>("h01"), _T_1191) @[Mux.scala 31:69] + node _T_1193 = mux(_T_1003, UInt<1>("h00"), _T_1192) @[Mux.scala 31:69] + node _T_1194 = add(UInt<64>("h08000000000000000"), _T_1193) @[CSR.scala 285:43] + node interruptCause = tail(_T_1194, 1) @[CSR.scala 285:43] + node _T_1196 = neq(all_interrupts, UInt<1>("h00")) @[CSR.scala 286:34] + node _T_1198 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 286:41] + node _T_1199 = and(_T_1196, _T_1198) @[CSR.scala 286:38] + node _T_1201 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 286:55] + node _T_1202 = and(_T_1199, _T_1201) @[CSR.scala 286:52] + node _T_1203 = or(_T_1202, reg_singleStepped) @[CSR.scala 286:70] + io.interrupt <= _T_1203 @[CSR.scala 286:16] + io.interrupt_cause <= interruptCause @[CSR.scala 287:22] + io.bp[0] <- reg_bp[0] @[CSR.scala 288:9] + node _T_1205 = and(UInt<1>("h01"), reg_dcsr.debugint) @[CSR.scala 291:26] + node _T_1207 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 291:50] + node _T_1208 = and(_T_1205, _T_1207) @[CSR.scala 291:47] + when _T_1208 : @[CSR.scala 291:62] + io.interrupt <= UInt<1>("h01") @[CSR.scala 292:18] + node _T_1226 = add(UInt<64>("h08000000000000000"), UInt<4>("h0d")) @[CSR.scala 293:46] + node _T_1227 = tail(_T_1226, 1) @[CSR.scala 293:46] + io.interrupt_cause <= _T_1227 @[CSR.scala 293:24] + skip @[CSR.scala 291:62] + reg reg_misa : UInt, clock with : (reset => (reset, UInt<64>("h0800000000014112d"))) @[CSR.scala 307:21] + node _T_1229 = cat(io.status.hie, io.status.sie) @[CSR.scala 308:38] + node _T_1230 = cat(_T_1229, io.status.uie) @[CSR.scala 308:38] + node _T_1231 = cat(io.status.upie, io.status.mie) @[CSR.scala 308:38] + node _T_1232 = cat(io.status.hpie, io.status.spie) @[CSR.scala 308:38] + node _T_1233 = cat(_T_1232, _T_1231) @[CSR.scala 308:38] + node _T_1234 = cat(_T_1233, _T_1230) @[CSR.scala 308:38] + node _T_1235 = cat(io.status.hpp, io.status.spp) @[CSR.scala 308:38] + node _T_1236 = cat(_T_1235, io.status.mpie) @[CSR.scala 308:38] + node _T_1237 = cat(io.status.fs, io.status.mpp) @[CSR.scala 308:38] + node _T_1238 = cat(io.status.mprv, io.status.xs) @[CSR.scala 308:38] + node _T_1239 = cat(_T_1238, _T_1237) @[CSR.scala 308:38] + node _T_1240 = cat(_T_1239, _T_1236) @[CSR.scala 308:38] + node _T_1241 = cat(_T_1240, _T_1234) @[CSR.scala 308:38] + node _T_1242 = cat(io.status.tvm, io.status.mxr) @[CSR.scala 308:38] + node _T_1243 = cat(_T_1242, io.status.pum) @[CSR.scala 308:38] + node _T_1244 = cat(io.status.tsr, io.status.tw) @[CSR.scala 308:38] + node _T_1245 = cat(io.status.sd_rv32, io.status.zero1) @[CSR.scala 308:38] + node _T_1246 = cat(_T_1245, _T_1244) @[CSR.scala 308:38] + node _T_1247 = cat(_T_1246, _T_1243) @[CSR.scala 308:38] + node _T_1248 = cat(io.status.zero2, io.status.sxl) @[CSR.scala 308:38] + node _T_1249 = cat(_T_1248, io.status.uxl) @[CSR.scala 308:38] + node _T_1250 = cat(io.status.prv, io.status.sd) @[CSR.scala 308:38] + node _T_1251 = cat(io.status.debug, io.status.isa) @[CSR.scala 308:38] + node _T_1252 = cat(_T_1251, _T_1250) @[CSR.scala 308:38] + node _T_1253 = cat(_T_1252, _T_1249) @[CSR.scala 308:38] + node _T_1254 = cat(_T_1253, _T_1247) @[CSR.scala 308:38] + node _T_1255 = cat(_T_1254, _T_1241) @[CSR.scala 308:38] + node read_mstatus = bits(_T_1255, 63, 0) @[CSR.scala 308:40] + node _T_1291 = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) @[CSR.scala 312:48] + node _T_1292 = cat(_T_1291, reg_bp[reg_tselect].control.r) @[CSR.scala 312:48] + node _T_1293 = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) @[CSR.scala 312:48] + node _T_1294 = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) @[CSR.scala 312:48] + node _T_1295 = cat(_T_1294, _T_1293) @[CSR.scala 312:48] + node _T_1296 = cat(_T_1295, _T_1292) @[CSR.scala 312:48] + node _T_1297 = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) @[CSR.scala 312:48] + node _T_1298 = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) @[CSR.scala 312:48] + node _T_1299 = cat(_T_1298, _T_1297) @[CSR.scala 312:48] + node _T_1300 = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) @[CSR.scala 312:48] + node _T_1301 = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) @[CSR.scala 312:48] + node _T_1302 = cat(_T_1301, _T_1300) @[CSR.scala 312:48] + node _T_1303 = cat(_T_1302, _T_1299) @[CSR.scala 312:48] + node _T_1304 = cat(_T_1303, _T_1296) @[CSR.scala 312:48] + node _T_1340 = bits(reg_bp[reg_tselect].address, 38, 38) @[Package.scala 40:38] + node _T_1341 = bits(_T_1340, 0, 0) @[Bitwise.scala 71:15] + node _T_1344 = mux(_T_1341, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_1345 = cat(_T_1344, reg_bp[reg_tselect].address) @[Cat.scala 30:58] + node _T_1349 = bits(reg_mepc, 39, 39) @[Package.scala 40:38] + node _T_1350 = bits(_T_1349, 0, 0) @[Bitwise.scala 71:15] + node _T_1353 = mux(_T_1350, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1354 = cat(_T_1353, reg_mepc) @[Cat.scala 30:58] + node _T_1355 = bits(reg_mbadaddr, 39, 39) @[Package.scala 40:38] + node _T_1356 = bits(_T_1355, 0, 0) @[Bitwise.scala 71:15] + node _T_1359 = mux(_T_1356, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1360 = cat(_T_1359, reg_mbadaddr) @[Cat.scala 30:58] + node _T_1361 = cat(reg_dcsr.step, reg_dcsr.prv) @[CSR.scala 333:27] + node _T_1362 = cat(reg_dcsr.zero1, reg_dcsr.halt) @[CSR.scala 333:27] + node _T_1363 = cat(_T_1362, _T_1361) @[CSR.scala 333:27] + node _T_1364 = cat(reg_dcsr.cause, reg_dcsr.debugint) @[CSR.scala 333:27] + node _T_1365 = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) @[CSR.scala 333:27] + node _T_1366 = cat(_T_1365, _T_1364) @[CSR.scala 333:27] + node _T_1367 = cat(_T_1366, _T_1363) @[CSR.scala 333:27] + node _T_1368 = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) @[CSR.scala 333:27] + node _T_1369 = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) @[CSR.scala 333:27] + node _T_1370 = cat(_T_1369, _T_1368) @[CSR.scala 333:27] + node _T_1371 = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) @[CSR.scala 333:27] + node _T_1372 = cat(reg_dcsr.xdebugver, reg_dcsr.ndreset) @[CSR.scala 333:27] + node _T_1373 = cat(_T_1372, reg_dcsr.fullreset) @[CSR.scala 333:27] + node _T_1374 = cat(_T_1373, _T_1371) @[CSR.scala 333:27] + node _T_1375 = cat(_T_1374, _T_1370) @[CSR.scala 333:27] + node _T_1376 = cat(_T_1375, _T_1367) @[CSR.scala 333:27] + node _T_1377 = cat(reg_frm, reg_fflags) @[Cat.scala 30:58] + node _T_1380 = and(reg_mie, reg_mideleg) @[CSR.scala 360:28] + node _T_1381 = and(read_mip, reg_mideleg) @[CSR.scala 361:29] + wire _T_1382 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + _T_1382 is invalid + _T_1382 <- io.status + _T_1382.mprv <= UInt<1>("h00") @[CSR.scala 363:23] + _T_1382.mpp <= UInt<1>("h00") @[CSR.scala 364:22] + _T_1382.hpp <= UInt<1>("h00") @[CSR.scala 365:22] + _T_1382.mpie <= UInt<1>("h00") @[CSR.scala 366:23] + _T_1382.hpie <= UInt<1>("h00") @[CSR.scala 367:23] + _T_1382.mie <= UInt<1>("h00") @[CSR.scala 368:22] + _T_1382.hie <= UInt<1>("h00") @[CSR.scala 369:22] + node _T_1418 = cat(_T_1382.hie, _T_1382.sie) @[CSR.scala 371:57] + node _T_1419 = cat(_T_1418, _T_1382.uie) @[CSR.scala 371:57] + node _T_1420 = cat(_T_1382.upie, _T_1382.mie) @[CSR.scala 371:57] + node _T_1421 = cat(_T_1382.hpie, _T_1382.spie) @[CSR.scala 371:57] + node _T_1422 = cat(_T_1421, _T_1420) @[CSR.scala 371:57] + node _T_1423 = cat(_T_1422, _T_1419) @[CSR.scala 371:57] + node _T_1424 = cat(_T_1382.hpp, _T_1382.spp) @[CSR.scala 371:57] + node _T_1425 = cat(_T_1424, _T_1382.mpie) @[CSR.scala 371:57] + node _T_1426 = cat(_T_1382.fs, _T_1382.mpp) @[CSR.scala 371:57] + node _T_1427 = cat(_T_1382.mprv, _T_1382.xs) @[CSR.scala 371:57] + node _T_1428 = cat(_T_1427, _T_1426) @[CSR.scala 371:57] + node _T_1429 = cat(_T_1428, _T_1425) @[CSR.scala 371:57] + node _T_1430 = cat(_T_1429, _T_1423) @[CSR.scala 371:57] + node _T_1431 = cat(_T_1382.tvm, _T_1382.mxr) @[CSR.scala 371:57] + node _T_1432 = cat(_T_1431, _T_1382.pum) @[CSR.scala 371:57] + node _T_1433 = cat(_T_1382.tsr, _T_1382.tw) @[CSR.scala 371:57] + node _T_1434 = cat(_T_1382.sd_rv32, _T_1382.zero1) @[CSR.scala 371:57] + node _T_1435 = cat(_T_1434, _T_1433) @[CSR.scala 371:57] + node _T_1436 = cat(_T_1435, _T_1432) @[CSR.scala 371:57] + node _T_1437 = cat(_T_1382.zero2, _T_1382.sxl) @[CSR.scala 371:57] + node _T_1438 = cat(_T_1437, _T_1382.uxl) @[CSR.scala 371:57] + node _T_1439 = cat(_T_1382.prv, _T_1382.sd) @[CSR.scala 371:57] + node _T_1440 = cat(_T_1382.debug, _T_1382.isa) @[CSR.scala 371:57] + node _T_1441 = cat(_T_1440, _T_1439) @[CSR.scala 371:57] + node _T_1442 = cat(_T_1441, _T_1438) @[CSR.scala 371:57] + node _T_1443 = cat(_T_1442, _T_1436) @[CSR.scala 371:57] + node _T_1444 = cat(_T_1443, _T_1430) @[CSR.scala 371:57] + node _T_1445 = bits(_T_1444, 63, 0) @[CSR.scala 371:60] + node _T_1446 = bits(reg_sbadaddr, 39, 39) @[Package.scala 40:38] + node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 71:15] + node _T_1450 = mux(_T_1447, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1451 = cat(_T_1450, reg_sbadaddr) @[Cat.scala 30:58] + node _T_1452 = cat(reg_sptbr.mode, reg_sptbr.asid) @[CSR.scala 377:45] + node _T_1453 = cat(_T_1452, reg_sptbr.ppn) @[CSR.scala 377:45] + node _T_1454 = bits(reg_sepc, 39, 39) @[Package.scala 40:38] + node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 71:15] + node _T_1458 = mux(_T_1455, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1459 = cat(_T_1458, reg_sepc) @[Cat.scala 30:58] + node _T_1460 = bits(reg_stvec, 38, 38) @[Package.scala 40:38] + node _T_1461 = bits(_T_1460, 0, 0) @[Bitwise.scala 71:15] + node _T_1464 = mux(_T_1461, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_1465 = cat(_T_1464, reg_stvec) @[Cat.scala 30:58] + node _T_1467 = eq(io.rw.addr, UInt<11>("h07a0")) @[CSR.scala 405:73] + node _T_1469 = eq(io.rw.addr, UInt<11>("h07a1")) @[CSR.scala 405:73] + node _T_1471 = eq(io.rw.addr, UInt<11>("h07a2")) @[CSR.scala 405:73] + node _T_1473 = eq(io.rw.addr, UInt<12>("h0f13")) @[CSR.scala 405:73] + node _T_1475 = eq(io.rw.addr, UInt<12>("h0f12")) @[CSR.scala 405:73] + node _T_1477 = eq(io.rw.addr, UInt<12>("h0f11")) @[CSR.scala 405:73] + node _T_1479 = eq(io.rw.addr, UInt<12>("h0b00")) @[CSR.scala 405:73] + node _T_1481 = eq(io.rw.addr, UInt<12>("h0b02")) @[CSR.scala 405:73] + node _T_1483 = eq(io.rw.addr, UInt<10>("h0301")) @[CSR.scala 405:73] + node _T_1485 = eq(io.rw.addr, UInt<10>("h0300")) @[CSR.scala 405:73] + node _T_1487 = eq(io.rw.addr, UInt<10>("h0305")) @[CSR.scala 405:73] + node _T_1489 = eq(io.rw.addr, UInt<10>("h0344")) @[CSR.scala 405:73] + node _T_1491 = eq(io.rw.addr, UInt<10>("h0304")) @[CSR.scala 405:73] + node _T_1493 = eq(io.rw.addr, UInt<10>("h0303")) @[CSR.scala 405:73] + node _T_1495 = eq(io.rw.addr, UInt<10>("h0302")) @[CSR.scala 405:73] + node _T_1497 = eq(io.rw.addr, UInt<10>("h0340")) @[CSR.scala 405:73] + node _T_1499 = eq(io.rw.addr, UInt<10>("h0341")) @[CSR.scala 405:73] + node _T_1501 = eq(io.rw.addr, UInt<10>("h0343")) @[CSR.scala 405:73] + node _T_1503 = eq(io.rw.addr, UInt<10>("h0342")) @[CSR.scala 405:73] + node _T_1505 = eq(io.rw.addr, UInt<12>("h0f14")) @[CSR.scala 405:73] + node _T_1507 = eq(io.rw.addr, UInt<11>("h07b0")) @[CSR.scala 405:73] + node _T_1509 = eq(io.rw.addr, UInt<11>("h07b1")) @[CSR.scala 405:73] + node _T_1511 = eq(io.rw.addr, UInt<11>("h07b2")) @[CSR.scala 405:73] + node _T_1513 = eq(io.rw.addr, UInt<1>("h01")) @[CSR.scala 405:73] + node _T_1515 = eq(io.rw.addr, UInt<2>("h02")) @[CSR.scala 405:73] + node _T_1517 = eq(io.rw.addr, UInt<2>("h03")) @[CSR.scala 405:73] + node _T_1519 = eq(io.rw.addr, UInt<10>("h0323")) @[CSR.scala 405:73] + node _T_1521 = eq(io.rw.addr, UInt<12>("h0b03")) @[CSR.scala 405:73] + node _T_1523 = eq(io.rw.addr, UInt<12>("h0c03")) @[CSR.scala 405:73] + node _T_1525 = eq(io.rw.addr, UInt<10>("h0324")) @[CSR.scala 405:73] + node _T_1527 = eq(io.rw.addr, UInt<12>("h0b04")) @[CSR.scala 405:73] + node _T_1529 = eq(io.rw.addr, UInt<12>("h0c04")) @[CSR.scala 405:73] + node _T_1531 = eq(io.rw.addr, UInt<10>("h0325")) @[CSR.scala 405:73] + node _T_1533 = eq(io.rw.addr, UInt<12>("h0b05")) @[CSR.scala 405:73] + node _T_1535 = eq(io.rw.addr, UInt<12>("h0c05")) @[CSR.scala 405:73] + node _T_1537 = eq(io.rw.addr, UInt<10>("h0326")) @[CSR.scala 405:73] + node _T_1539 = eq(io.rw.addr, UInt<12>("h0b06")) @[CSR.scala 405:73] + node _T_1541 = eq(io.rw.addr, UInt<12>("h0c06")) @[CSR.scala 405:73] + node _T_1543 = eq(io.rw.addr, UInt<10>("h0327")) @[CSR.scala 405:73] + node _T_1545 = eq(io.rw.addr, UInt<12>("h0b07")) @[CSR.scala 405:73] + node _T_1547 = eq(io.rw.addr, UInt<12>("h0c07")) @[CSR.scala 405:73] + node _T_1549 = eq(io.rw.addr, UInt<10>("h0328")) @[CSR.scala 405:73] + node _T_1551 = eq(io.rw.addr, UInt<12>("h0b08")) @[CSR.scala 405:73] + node _T_1553 = eq(io.rw.addr, UInt<12>("h0c08")) @[CSR.scala 405:73] + node _T_1555 = eq(io.rw.addr, UInt<10>("h0329")) @[CSR.scala 405:73] + node _T_1557 = eq(io.rw.addr, UInt<12>("h0b09")) @[CSR.scala 405:73] + node _T_1559 = eq(io.rw.addr, UInt<12>("h0c09")) @[CSR.scala 405:73] + node _T_1561 = eq(io.rw.addr, UInt<10>("h032a")) @[CSR.scala 405:73] + node _T_1563 = eq(io.rw.addr, UInt<12>("h0b0a")) @[CSR.scala 405:73] + node _T_1565 = eq(io.rw.addr, UInt<12>("h0c0a")) @[CSR.scala 405:73] + node _T_1567 = eq(io.rw.addr, UInt<10>("h032b")) @[CSR.scala 405:73] + node _T_1569 = eq(io.rw.addr, UInt<12>("h0b0b")) @[CSR.scala 405:73] + node _T_1571 = eq(io.rw.addr, UInt<12>("h0c0b")) @[CSR.scala 405:73] + node _T_1573 = eq(io.rw.addr, UInt<10>("h032c")) @[CSR.scala 405:73] + node _T_1575 = eq(io.rw.addr, UInt<12>("h0b0c")) @[CSR.scala 405:73] + node _T_1577 = eq(io.rw.addr, UInt<12>("h0c0c")) @[CSR.scala 405:73] + node _T_1579 = eq(io.rw.addr, UInt<10>("h032d")) @[CSR.scala 405:73] + node _T_1581 = eq(io.rw.addr, UInt<12>("h0b0d")) @[CSR.scala 405:73] + node _T_1583 = eq(io.rw.addr, UInt<12>("h0c0d")) @[CSR.scala 405:73] + node _T_1585 = eq(io.rw.addr, UInt<10>("h032e")) @[CSR.scala 405:73] + node _T_1587 = eq(io.rw.addr, UInt<12>("h0b0e")) @[CSR.scala 405:73] + node _T_1589 = eq(io.rw.addr, UInt<12>("h0c0e")) @[CSR.scala 405:73] + node _T_1591 = eq(io.rw.addr, UInt<10>("h032f")) @[CSR.scala 405:73] + node _T_1593 = eq(io.rw.addr, UInt<12>("h0b0f")) @[CSR.scala 405:73] + node _T_1595 = eq(io.rw.addr, UInt<12>("h0c0f")) @[CSR.scala 405:73] + node _T_1597 = eq(io.rw.addr, UInt<10>("h0330")) @[CSR.scala 405:73] + node _T_1599 = eq(io.rw.addr, UInt<12>("h0b10")) @[CSR.scala 405:73] + node _T_1601 = eq(io.rw.addr, UInt<12>("h0c10")) @[CSR.scala 405:73] + node _T_1603 = eq(io.rw.addr, UInt<10>("h0331")) @[CSR.scala 405:73] + node _T_1605 = eq(io.rw.addr, UInt<12>("h0b11")) @[CSR.scala 405:73] + node _T_1607 = eq(io.rw.addr, UInt<12>("h0c11")) @[CSR.scala 405:73] + node _T_1609 = eq(io.rw.addr, UInt<10>("h0332")) @[CSR.scala 405:73] + node _T_1611 = eq(io.rw.addr, UInt<12>("h0b12")) @[CSR.scala 405:73] + node _T_1613 = eq(io.rw.addr, UInt<12>("h0c12")) @[CSR.scala 405:73] + node _T_1615 = eq(io.rw.addr, UInt<10>("h0333")) @[CSR.scala 405:73] + node _T_1617 = eq(io.rw.addr, UInt<12>("h0b13")) @[CSR.scala 405:73] + node _T_1619 = eq(io.rw.addr, UInt<12>("h0c13")) @[CSR.scala 405:73] + node _T_1621 = eq(io.rw.addr, UInt<10>("h0334")) @[CSR.scala 405:73] + node _T_1623 = eq(io.rw.addr, UInt<12>("h0b14")) @[CSR.scala 405:73] + node _T_1625 = eq(io.rw.addr, UInt<12>("h0c14")) @[CSR.scala 405:73] + node _T_1627 = eq(io.rw.addr, UInt<10>("h0335")) @[CSR.scala 405:73] + node _T_1629 = eq(io.rw.addr, UInt<12>("h0b15")) @[CSR.scala 405:73] + node _T_1631 = eq(io.rw.addr, UInt<12>("h0c15")) @[CSR.scala 405:73] + node _T_1633 = eq(io.rw.addr, UInt<10>("h0336")) @[CSR.scala 405:73] + node _T_1635 = eq(io.rw.addr, UInt<12>("h0b16")) @[CSR.scala 405:73] + node _T_1637 = eq(io.rw.addr, UInt<12>("h0c16")) @[CSR.scala 405:73] + node _T_1639 = eq(io.rw.addr, UInt<10>("h0337")) @[CSR.scala 405:73] + node _T_1641 = eq(io.rw.addr, UInt<12>("h0b17")) @[CSR.scala 405:73] + node _T_1643 = eq(io.rw.addr, UInt<12>("h0c17")) @[CSR.scala 405:73] + node _T_1645 = eq(io.rw.addr, UInt<10>("h0338")) @[CSR.scala 405:73] + node _T_1647 = eq(io.rw.addr, UInt<12>("h0b18")) @[CSR.scala 405:73] + node _T_1649 = eq(io.rw.addr, UInt<12>("h0c18")) @[CSR.scala 405:73] + node _T_1651 = eq(io.rw.addr, UInt<10>("h0339")) @[CSR.scala 405:73] + node _T_1653 = eq(io.rw.addr, UInt<12>("h0b19")) @[CSR.scala 405:73] + node _T_1655 = eq(io.rw.addr, UInt<12>("h0c19")) @[CSR.scala 405:73] + node _T_1657 = eq(io.rw.addr, UInt<10>("h033a")) @[CSR.scala 405:73] + node _T_1659 = eq(io.rw.addr, UInt<12>("h0b1a")) @[CSR.scala 405:73] + node _T_1661 = eq(io.rw.addr, UInt<12>("h0c1a")) @[CSR.scala 405:73] + node _T_1663 = eq(io.rw.addr, UInt<10>("h033b")) @[CSR.scala 405:73] + node _T_1665 = eq(io.rw.addr, UInt<12>("h0b1b")) @[CSR.scala 405:73] + node _T_1667 = eq(io.rw.addr, UInt<12>("h0c1b")) @[CSR.scala 405:73] + node _T_1669 = eq(io.rw.addr, UInt<10>("h033c")) @[CSR.scala 405:73] + node _T_1671 = eq(io.rw.addr, UInt<12>("h0b1c")) @[CSR.scala 405:73] + node _T_1673 = eq(io.rw.addr, UInt<12>("h0c1c")) @[CSR.scala 405:73] + node _T_1675 = eq(io.rw.addr, UInt<10>("h033d")) @[CSR.scala 405:73] + node _T_1677 = eq(io.rw.addr, UInt<12>("h0b1d")) @[CSR.scala 405:73] + node _T_1679 = eq(io.rw.addr, UInt<12>("h0c1d")) @[CSR.scala 405:73] + node _T_1681 = eq(io.rw.addr, UInt<10>("h033e")) @[CSR.scala 405:73] + node _T_1683 = eq(io.rw.addr, UInt<12>("h0b1e")) @[CSR.scala 405:73] + node _T_1685 = eq(io.rw.addr, UInt<12>("h0c1e")) @[CSR.scala 405:73] + node _T_1687 = eq(io.rw.addr, UInt<10>("h033f")) @[CSR.scala 405:73] + node _T_1689 = eq(io.rw.addr, UInt<12>("h0b1f")) @[CSR.scala 405:73] + node _T_1691 = eq(io.rw.addr, UInt<12>("h0c1f")) @[CSR.scala 405:73] + node _T_1693 = eq(io.rw.addr, UInt<9>("h0100")) @[CSR.scala 405:73] + node _T_1695 = eq(io.rw.addr, UInt<9>("h0144")) @[CSR.scala 405:73] + node _T_1697 = eq(io.rw.addr, UInt<9>("h0104")) @[CSR.scala 405:73] + node _T_1699 = eq(io.rw.addr, UInt<9>("h0140")) @[CSR.scala 405:73] + node _T_1701 = eq(io.rw.addr, UInt<9>("h0142")) @[CSR.scala 405:73] + node _T_1703 = eq(io.rw.addr, UInt<9>("h0143")) @[CSR.scala 405:73] + node _T_1705 = eq(io.rw.addr, UInt<9>("h0180")) @[CSR.scala 405:73] + node _T_1707 = eq(io.rw.addr, UInt<9>("h0141")) @[CSR.scala 405:73] + node _T_1709 = eq(io.rw.addr, UInt<9>("h0105")) @[CSR.scala 405:73] + node _T_1711 = eq(io.rw.addr, UInt<9>("h0106")) @[CSR.scala 405:73] + node _T_1713 = eq(io.rw.addr, UInt<10>("h0306")) @[CSR.scala 405:73] + node _T_1715 = eq(io.rw.addr, UInt<12>("h0c00")) @[CSR.scala 405:73] + node _T_1717 = eq(io.rw.addr, UInt<12>("h0c02")) @[CSR.scala 405:73] + node _T_1720 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47] + node _T_1721 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47] + node _T_1722 = or(_T_1720, _T_1721) @[Package.scala 7:62] + node _T_1724 = mux(_T_1722, io.rw.rdata, UInt<1>("h00")) @[CSR.scala 406:19] + node _T_1725 = or(_T_1724, io.rw.wdata) @[CSR.scala 406:75] + node _T_1727 = eq(io.rw.cmd, UInt<3>("h03")) @[CSR.scala 407:30] + node _T_1729 = mux(_T_1727, io.rw.wdata, UInt<1>("h00")) @[CSR.scala 407:19] + node _T_1730 = not(_T_1729) @[CSR.scala 407:15] + node wdata = and(_T_1725, _T_1730) @[CSR.scala 406:90] + node system_insn = eq(io.rw.cmd, UInt<3>("h04")) @[CSR.scala 409:31] + node _T_1733 = bits(io.rw.addr, 2, 0) @[CSR.scala 410:37] + node opcode = dshl(UInt<1>("h01"), _T_1733) @[CSR.scala 410:24] + node insn_rs2 = bits(io.rw.addr, 5, 5) @[CSR.scala 411:28] + node _T_1735 = eq(insn_rs2, UInt<1>("h00")) @[CSR.scala 412:34] + node _T_1736 = and(system_insn, _T_1735) @[CSR.scala 412:31] + node _T_1737 = bits(opcode, 0, 0) @[CSR.scala 412:53] + node insn_call = and(_T_1736, _T_1737) @[CSR.scala 412:44] + node _T_1738 = bits(opcode, 1, 1) @[CSR.scala 413:41] + node insn_break = and(system_insn, _T_1738) @[CSR.scala 413:32] + node _T_1739 = bits(opcode, 2, 2) @[CSR.scala 414:39] + node insn_ret = and(system_insn, _T_1739) @[CSR.scala 414:30] + node _T_1740 = bits(opcode, 5, 5) @[CSR.scala 415:39] + node insn_wfi = and(system_insn, _T_1740) @[CSR.scala 415:30] + node insn_sfence_vma = and(system_insn, insn_rs2) @[CSR.scala 416:37] + node _T_1743 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 418:51] + node _T_1744 = or(UInt<1>("h00"), _T_1743) @[CSR.scala 418:34] + node _T_1746 = eq(reg_mstatus.tw, UInt<1>("h00")) @[CSR.scala 418:62] + node allow_wfi = or(_T_1744, _T_1746) @[CSR.scala 418:59] + node _T_1749 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 419:58] + node _T_1750 = or(UInt<1>("h00"), _T_1749) @[CSR.scala 419:41] + node _T_1752 = eq(reg_mstatus.tvm, UInt<1>("h00")) @[CSR.scala 419:69] + node allow_sfence_vma = or(_T_1750, _T_1752) @[CSR.scala 419:66] + node _T_1755 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 420:52] + node _T_1756 = or(UInt<1>("h00"), _T_1755) @[CSR.scala 420:35] + node _T_1758 = eq(reg_mstatus.tsr, UInt<1>("h00")) @[CSR.scala 420:63] + node allow_sret = or(_T_1756, _T_1758) @[CSR.scala 420:60] + node _T_1760 = eq(io.status.fs, UInt<1>("h00")) @[CSR.scala 421:40] + node _T_1761 = bits(reg_misa, 5, 5) @[CSR.scala 421:58] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[CSR.scala 421:49] + node _T_1764 = or(_T_1760, _T_1763) @[CSR.scala 421:46] + io.decode.fp_illegal <= _T_1764 @[CSR.scala 421:24] + node _T_1766 = eq(io.status.xs, UInt<1>("h00")) @[CSR.scala 422:42] + node _T_1767 = bits(reg_misa, 23, 23) @[CSR.scala 422:60] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[CSR.scala 422:51] + node _T_1770 = or(_T_1766, _T_1769) @[CSR.scala 422:48] + io.decode.rocc_illegal <= _T_1770 @[CSR.scala 422:26] + node _T_1771 = bits(io.decode.csr, 9, 8) @[CSR.scala 423:58] + node _T_1772 = lt(effective_prv, _T_1771) @[CSR.scala 423:43] + node _T_1774 = eq(io.decode.csr, UInt<11>("h07a0")) @[CSR.scala 424:42] + node _T_1776 = eq(io.decode.csr, UInt<11>("h07a1")) @[CSR.scala 424:42] + node _T_1778 = eq(io.decode.csr, UInt<11>("h07a2")) @[CSR.scala 424:42] + node _T_1780 = eq(io.decode.csr, UInt<12>("h0f13")) @[CSR.scala 424:42] + node _T_1782 = eq(io.decode.csr, UInt<12>("h0f12")) @[CSR.scala 424:42] + node _T_1784 = eq(io.decode.csr, UInt<12>("h0f11")) @[CSR.scala 424:42] + node _T_1786 = eq(io.decode.csr, UInt<12>("h0b00")) @[CSR.scala 424:42] + node _T_1788 = eq(io.decode.csr, UInt<12>("h0b02")) @[CSR.scala 424:42] + node _T_1790 = eq(io.decode.csr, UInt<10>("h0301")) @[CSR.scala 424:42] + node _T_1792 = eq(io.decode.csr, UInt<10>("h0300")) @[CSR.scala 424:42] + node _T_1794 = eq(io.decode.csr, UInt<10>("h0305")) @[CSR.scala 424:42] + node _T_1796 = eq(io.decode.csr, UInt<10>("h0344")) @[CSR.scala 424:42] + node _T_1798 = eq(io.decode.csr, UInt<10>("h0304")) @[CSR.scala 424:42] + node _T_1800 = eq(io.decode.csr, UInt<10>("h0303")) @[CSR.scala 424:42] + node _T_1802 = eq(io.decode.csr, UInt<10>("h0302")) @[CSR.scala 424:42] + node _T_1804 = eq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 424:42] + node _T_1806 = eq(io.decode.csr, UInt<10>("h0341")) @[CSR.scala 424:42] + node _T_1808 = eq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 424:42] + node _T_1810 = eq(io.decode.csr, UInt<10>("h0342")) @[CSR.scala 424:42] + node _T_1812 = eq(io.decode.csr, UInt<12>("h0f14")) @[CSR.scala 424:42] + node _T_1814 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 424:42] + node _T_1816 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 424:42] + node _T_1818 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 424:42] + node _T_1820 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 424:42] + node _T_1822 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 424:42] + node _T_1824 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 424:42] + node _T_1826 = eq(io.decode.csr, UInt<10>("h0323")) @[CSR.scala 424:42] + node _T_1828 = eq(io.decode.csr, UInt<12>("h0b03")) @[CSR.scala 424:42] + node _T_1830 = eq(io.decode.csr, UInt<12>("h0c03")) @[CSR.scala 424:42] + node _T_1832 = eq(io.decode.csr, UInt<10>("h0324")) @[CSR.scala 424:42] + node _T_1834 = eq(io.decode.csr, UInt<12>("h0b04")) @[CSR.scala 424:42] + node _T_1836 = eq(io.decode.csr, UInt<12>("h0c04")) @[CSR.scala 424:42] + node _T_1838 = eq(io.decode.csr, UInt<10>("h0325")) @[CSR.scala 424:42] + node _T_1840 = eq(io.decode.csr, UInt<12>("h0b05")) @[CSR.scala 424:42] + node _T_1842 = eq(io.decode.csr, UInt<12>("h0c05")) @[CSR.scala 424:42] + node _T_1844 = eq(io.decode.csr, UInt<10>("h0326")) @[CSR.scala 424:42] + node _T_1846 = eq(io.decode.csr, UInt<12>("h0b06")) @[CSR.scala 424:42] + node _T_1848 = eq(io.decode.csr, UInt<12>("h0c06")) @[CSR.scala 424:42] + node _T_1850 = eq(io.decode.csr, UInt<10>("h0327")) @[CSR.scala 424:42] + node _T_1852 = eq(io.decode.csr, UInt<12>("h0b07")) @[CSR.scala 424:42] + node _T_1854 = eq(io.decode.csr, UInt<12>("h0c07")) @[CSR.scala 424:42] + node _T_1856 = eq(io.decode.csr, UInt<10>("h0328")) @[CSR.scala 424:42] + node _T_1858 = eq(io.decode.csr, UInt<12>("h0b08")) @[CSR.scala 424:42] + node _T_1860 = eq(io.decode.csr, UInt<12>("h0c08")) @[CSR.scala 424:42] + node _T_1862 = eq(io.decode.csr, UInt<10>("h0329")) @[CSR.scala 424:42] + node _T_1864 = eq(io.decode.csr, UInt<12>("h0b09")) @[CSR.scala 424:42] + node _T_1866 = eq(io.decode.csr, UInt<12>("h0c09")) @[CSR.scala 424:42] + node _T_1868 = eq(io.decode.csr, UInt<10>("h032a")) @[CSR.scala 424:42] + node _T_1870 = eq(io.decode.csr, UInt<12>("h0b0a")) @[CSR.scala 424:42] + node _T_1872 = eq(io.decode.csr, UInt<12>("h0c0a")) @[CSR.scala 424:42] + node _T_1874 = eq(io.decode.csr, UInt<10>("h032b")) @[CSR.scala 424:42] + node _T_1876 = eq(io.decode.csr, UInt<12>("h0b0b")) @[CSR.scala 424:42] + node _T_1878 = eq(io.decode.csr, UInt<12>("h0c0b")) @[CSR.scala 424:42] + node _T_1880 = eq(io.decode.csr, UInt<10>("h032c")) @[CSR.scala 424:42] + node _T_1882 = eq(io.decode.csr, UInt<12>("h0b0c")) @[CSR.scala 424:42] + node _T_1884 = eq(io.decode.csr, UInt<12>("h0c0c")) @[CSR.scala 424:42] + node _T_1886 = eq(io.decode.csr, UInt<10>("h032d")) @[CSR.scala 424:42] + node _T_1888 = eq(io.decode.csr, UInt<12>("h0b0d")) @[CSR.scala 424:42] + node _T_1890 = eq(io.decode.csr, UInt<12>("h0c0d")) @[CSR.scala 424:42] + node _T_1892 = eq(io.decode.csr, UInt<10>("h032e")) @[CSR.scala 424:42] + node _T_1894 = eq(io.decode.csr, UInt<12>("h0b0e")) @[CSR.scala 424:42] + node _T_1896 = eq(io.decode.csr, UInt<12>("h0c0e")) @[CSR.scala 424:42] + node _T_1898 = eq(io.decode.csr, UInt<10>("h032f")) @[CSR.scala 424:42] + node _T_1900 = eq(io.decode.csr, UInt<12>("h0b0f")) @[CSR.scala 424:42] + node _T_1902 = eq(io.decode.csr, UInt<12>("h0c0f")) @[CSR.scala 424:42] + node _T_1904 = eq(io.decode.csr, UInt<10>("h0330")) @[CSR.scala 424:42] + node _T_1906 = eq(io.decode.csr, UInt<12>("h0b10")) @[CSR.scala 424:42] + node _T_1908 = eq(io.decode.csr, UInt<12>("h0c10")) @[CSR.scala 424:42] + node _T_1910 = eq(io.decode.csr, UInt<10>("h0331")) @[CSR.scala 424:42] + node _T_1912 = eq(io.decode.csr, UInt<12>("h0b11")) @[CSR.scala 424:42] + node _T_1914 = eq(io.decode.csr, UInt<12>("h0c11")) @[CSR.scala 424:42] + node _T_1916 = eq(io.decode.csr, UInt<10>("h0332")) @[CSR.scala 424:42] + node _T_1918 = eq(io.decode.csr, UInt<12>("h0b12")) @[CSR.scala 424:42] + node _T_1920 = eq(io.decode.csr, UInt<12>("h0c12")) @[CSR.scala 424:42] + node _T_1922 = eq(io.decode.csr, UInt<10>("h0333")) @[CSR.scala 424:42] + node _T_1924 = eq(io.decode.csr, UInt<12>("h0b13")) @[CSR.scala 424:42] + node _T_1926 = eq(io.decode.csr, UInt<12>("h0c13")) @[CSR.scala 424:42] + node _T_1928 = eq(io.decode.csr, UInt<10>("h0334")) @[CSR.scala 424:42] + node _T_1930 = eq(io.decode.csr, UInt<12>("h0b14")) @[CSR.scala 424:42] + node _T_1932 = eq(io.decode.csr, UInt<12>("h0c14")) @[CSR.scala 424:42] + node _T_1934 = eq(io.decode.csr, UInt<10>("h0335")) @[CSR.scala 424:42] + node _T_1936 = eq(io.decode.csr, UInt<12>("h0b15")) @[CSR.scala 424:42] + node _T_1938 = eq(io.decode.csr, UInt<12>("h0c15")) @[CSR.scala 424:42] + node _T_1940 = eq(io.decode.csr, UInt<10>("h0336")) @[CSR.scala 424:42] + node _T_1942 = eq(io.decode.csr, UInt<12>("h0b16")) @[CSR.scala 424:42] + node _T_1944 = eq(io.decode.csr, UInt<12>("h0c16")) @[CSR.scala 424:42] + node _T_1946 = eq(io.decode.csr, UInt<10>("h0337")) @[CSR.scala 424:42] + node _T_1948 = eq(io.decode.csr, UInt<12>("h0b17")) @[CSR.scala 424:42] + node _T_1950 = eq(io.decode.csr, UInt<12>("h0c17")) @[CSR.scala 424:42] + node _T_1952 = eq(io.decode.csr, UInt<10>("h0338")) @[CSR.scala 424:42] + node _T_1954 = eq(io.decode.csr, UInt<12>("h0b18")) @[CSR.scala 424:42] + node _T_1956 = eq(io.decode.csr, UInt<12>("h0c18")) @[CSR.scala 424:42] + node _T_1958 = eq(io.decode.csr, UInt<10>("h0339")) @[CSR.scala 424:42] + node _T_1960 = eq(io.decode.csr, UInt<12>("h0b19")) @[CSR.scala 424:42] + node _T_1962 = eq(io.decode.csr, UInt<12>("h0c19")) @[CSR.scala 424:42] + node _T_1964 = eq(io.decode.csr, UInt<10>("h033a")) @[CSR.scala 424:42] + node _T_1966 = eq(io.decode.csr, UInt<12>("h0b1a")) @[CSR.scala 424:42] + node _T_1968 = eq(io.decode.csr, UInt<12>("h0c1a")) @[CSR.scala 424:42] + node _T_1970 = eq(io.decode.csr, UInt<10>("h033b")) @[CSR.scala 424:42] + node _T_1972 = eq(io.decode.csr, UInt<12>("h0b1b")) @[CSR.scala 424:42] + node _T_1974 = eq(io.decode.csr, UInt<12>("h0c1b")) @[CSR.scala 424:42] + node _T_1976 = eq(io.decode.csr, UInt<10>("h033c")) @[CSR.scala 424:42] + node _T_1978 = eq(io.decode.csr, UInt<12>("h0b1c")) @[CSR.scala 424:42] + node _T_1980 = eq(io.decode.csr, UInt<12>("h0c1c")) @[CSR.scala 424:42] + node _T_1982 = eq(io.decode.csr, UInt<10>("h033d")) @[CSR.scala 424:42] + node _T_1984 = eq(io.decode.csr, UInt<12>("h0b1d")) @[CSR.scala 424:42] + node _T_1986 = eq(io.decode.csr, UInt<12>("h0c1d")) @[CSR.scala 424:42] + node _T_1988 = eq(io.decode.csr, UInt<10>("h033e")) @[CSR.scala 424:42] + node _T_1990 = eq(io.decode.csr, UInt<12>("h0b1e")) @[CSR.scala 424:42] + node _T_1992 = eq(io.decode.csr, UInt<12>("h0c1e")) @[CSR.scala 424:42] + node _T_1994 = eq(io.decode.csr, UInt<10>("h033f")) @[CSR.scala 424:42] + node _T_1996 = eq(io.decode.csr, UInt<12>("h0b1f")) @[CSR.scala 424:42] + node _T_1998 = eq(io.decode.csr, UInt<12>("h0c1f")) @[CSR.scala 424:42] + node _T_2000 = eq(io.decode.csr, UInt<9>("h0100")) @[CSR.scala 424:42] + node _T_2002 = eq(io.decode.csr, UInt<9>("h0144")) @[CSR.scala 424:42] + node _T_2004 = eq(io.decode.csr, UInt<9>("h0104")) @[CSR.scala 424:42] + node _T_2006 = eq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 424:42] + node _T_2008 = eq(io.decode.csr, UInt<9>("h0142")) @[CSR.scala 424:42] + node _T_2010 = eq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 424:42] + node _T_2012 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 424:42] + node _T_2014 = eq(io.decode.csr, UInt<9>("h0141")) @[CSR.scala 424:42] + node _T_2016 = eq(io.decode.csr, UInt<9>("h0105")) @[CSR.scala 424:42] + node _T_2018 = eq(io.decode.csr, UInt<9>("h0106")) @[CSR.scala 424:42] + node _T_2020 = eq(io.decode.csr, UInt<10>("h0306")) @[CSR.scala 424:42] + node _T_2022 = eq(io.decode.csr, UInt<12>("h0c00")) @[CSR.scala 424:42] + node _T_2024 = eq(io.decode.csr, UInt<12>("h0c02")) @[CSR.scala 424:42] + node _T_2025 = or(_T_1952, _T_1820) @[CSR.scala 424:57] + node _T_2026 = or(_T_2025, _T_1864) @[CSR.scala 424:57] + node _T_2027 = or(_T_2026, _T_2006) @[CSR.scala 424:57] + node _T_2028 = or(_T_2027, _T_1978) @[CSR.scala 424:57] + node _T_2029 = or(_T_2028, _T_1946) @[CSR.scala 424:57] + node _T_2030 = or(_T_2029, _T_1832) @[CSR.scala 424:57] + node _T_2031 = or(_T_2030, _T_1800) @[CSR.scala 424:57] + node _T_2032 = or(_T_2031, _T_2020) @[CSR.scala 424:57] + node _T_2033 = or(_T_2032, _T_1914) @[CSR.scala 424:57] + node _T_2034 = or(_T_2033, _T_1876) @[CSR.scala 424:57] + node _T_2035 = or(_T_2034, _T_1920) @[CSR.scala 424:57] + node _T_2036 = or(_T_2035, _T_1788) @[CSR.scala 424:57] + node _T_2037 = or(_T_2036, _T_1844) @[CSR.scala 424:57] + node _T_2038 = or(_T_2037, _T_1888) @[CSR.scala 424:57] + node _T_2039 = or(_T_2038, _T_1872) @[CSR.scala 424:57] + node _T_2040 = or(_T_2039, _T_1988) @[CSR.scala 424:57] + node _T_2041 = or(_T_2040, _T_1910) @[CSR.scala 424:57] + node _T_2042 = or(_T_2041, _T_1924) @[CSR.scala 424:57] + node _T_2043 = or(_T_2042, _T_1776) @[CSR.scala 424:57] + node _T_2044 = or(_T_2043, _T_1808) @[CSR.scala 424:57] + node _T_2045 = or(_T_2044, _T_1892) @[CSR.scala 424:57] + node _T_2046 = or(_T_2045, _T_1840) @[CSR.scala 424:57] + node _T_2047 = or(_T_2046, _T_1956) @[CSR.scala 424:57] + node _T_2048 = or(_T_2047, _T_2010) @[CSR.scala 424:57] + node _T_2049 = or(_T_2048, _T_1868) @[CSR.scala 424:57] + node _T_2050 = or(_T_2049, _T_2000) @[CSR.scala 424:57] + node _T_2051 = or(_T_2050, _T_1878) @[CSR.scala 424:57] + node _T_2052 = or(_T_2051, _T_1942) @[CSR.scala 424:57] + node _T_2053 = or(_T_2052, _T_1812) @[CSR.scala 424:57] + node _T_2054 = or(_T_2053, _T_1974) @[CSR.scala 424:57] + node _T_2055 = or(_T_2054, _T_1968) @[CSR.scala 424:57] + node _T_2056 = or(_T_2055, _T_1780) @[CSR.scala 424:57] + node _T_2057 = or(_T_2056, _T_1836) @[CSR.scala 424:57] + node _T_2058 = or(_T_2057, _T_1996) @[CSR.scala 424:57] + node _T_2059 = or(_T_2058, _T_1814) @[CSR.scala 424:57] + node _T_2060 = or(_T_2059, _T_1900) @[CSR.scala 424:57] + node _T_2061 = or(_T_2060, _T_1846) @[CSR.scala 424:57] + node _T_2062 = or(_T_2061, _T_1932) @[CSR.scala 424:57] + node _T_2063 = or(_T_2062, _T_1964) @[CSR.scala 424:57] + node _T_2064 = or(_T_2063, _T_1782) @[CSR.scala 424:57] + node _T_2065 = or(_T_2064, _T_1904) @[CSR.scala 424:57] + node _T_2066 = or(_T_2065, _T_1992) @[CSR.scala 424:57] + node _T_2067 = or(_T_2066, _T_1860) @[CSR.scala 424:57] + node _T_2068 = or(_T_2067, _T_1804) @[CSR.scala 424:57] + node _T_2069 = or(_T_2068, _T_1936) @[CSR.scala 424:57] + node _T_2070 = or(_T_2069, _T_1960) @[CSR.scala 424:57] + node _T_2071 = or(_T_2070, _T_1828) @[CSR.scala 424:57] + node _T_2072 = or(_T_2071, _T_1908) @[CSR.scala 424:57] + node _T_2073 = or(_T_2072, _T_2024) @[CSR.scala 424:57] + node _T_2074 = or(_T_2073, _T_2004) @[CSR.scala 424:57] + node _T_2075 = or(_T_2074, _T_1856) @[CSR.scala 424:57] + node _T_2076 = or(_T_2075, _T_1940) @[CSR.scala 424:57] + node _T_2077 = or(_T_2076, _T_1792) @[CSR.scala 424:57] + node _T_2078 = or(_T_2077, _T_1972) @[CSR.scala 424:57] + node _T_2079 = or(_T_2078, _T_1824) @[CSR.scala 424:57] + node _T_2080 = or(_T_2079, _T_1896) @[CSR.scala 424:57] + node _T_2081 = or(_T_2080, _T_1928) @[CSR.scala 424:57] + node _T_2082 = or(_T_2081, _T_1796) @[CSR.scala 424:57] + node _T_2083 = or(_T_2082, _T_1918) @[CSR.scala 424:57] + node _T_2084 = or(_T_2083, _T_1786) @[CSR.scala 424:57] + node _T_2085 = or(_T_2084, _T_1980) @[CSR.scala 424:57] + node _T_2086 = or(_T_2085, _T_1774) @[CSR.scala 424:57] + node _T_2087 = or(_T_2086, _T_1830) @[CSR.scala 424:57] + node _T_2088 = or(_T_2087, _T_1890) @[CSR.scala 424:57] + node _T_2089 = or(_T_2088, _T_2018) @[CSR.scala 424:57] + node _T_2090 = or(_T_2089, _T_1916) @[CSR.scala 424:57] + node _T_2091 = or(_T_2090, _T_1884) @[CSR.scala 424:57] + node _T_2092 = or(_T_2091, _T_1862) @[CSR.scala 424:57] + node _T_2093 = or(_T_2092, _T_1948) @[CSR.scala 424:57] + node _T_2094 = or(_T_2093, _T_1798) @[CSR.scala 424:57] + node _T_2095 = or(_T_2094, _T_1976) @[CSR.scala 424:57] + node _T_2096 = or(_T_2095, _T_1886) @[CSR.scala 424:57] + node _T_2097 = or(_T_2096, _T_1950) @[CSR.scala 424:57] + node _T_2098 = or(_T_2097, _T_1818) @[CSR.scala 424:57] + node _T_2099 = or(_T_2098, _T_1982) @[CSR.scala 424:57] + node _T_2100 = or(_T_2099, _T_1850) @[CSR.scala 424:57] + node _T_2101 = or(_T_2100, _T_1810) @[CSR.scala 424:57] + node _T_2102 = or(_T_2101, _T_1944) @[CSR.scala 424:57] + node _T_2103 = or(_T_2102, _T_2014) @[CSR.scala 424:57] + node _T_2104 = or(_T_2103, _T_1838) @[CSR.scala 424:57] + node _T_2105 = or(_T_2104, _T_1954) @[CSR.scala 424:57] + node _T_2106 = or(_T_2105, _T_1870) @[CSR.scala 424:57] + node _T_2107 = or(_T_2106, _T_1986) @[CSR.scala 424:57] + node _T_2108 = or(_T_2107, _T_2008) @[CSR.scala 424:57] + node _T_2109 = or(_T_2108, _T_1922) @[CSR.scala 424:57] + node _T_2110 = or(_T_2109, _T_1778) @[CSR.scala 424:57] + node _T_2111 = or(_T_2110, _T_1806) @[CSR.scala 424:57] + node _T_2112 = or(_T_2111, _T_1842) @[CSR.scala 424:57] + node _T_2113 = or(_T_2112, _T_1874) @[CSR.scala 424:57] + node _T_2114 = or(_T_2113, _T_1880) @[CSR.scala 424:57] + node _T_2115 = or(_T_2114, _T_2012) @[CSR.scala 424:57] + node _T_2116 = or(_T_2115, _T_1912) @[CSR.scala 424:57] + node _T_2117 = or(_T_2116, _T_1802) @[CSR.scala 424:57] + node _T_2118 = or(_T_2117, _T_1934) @[CSR.scala 424:57] + node _T_2119 = or(_T_2118, _T_1848) @[CSR.scala 424:57] + node _T_2120 = or(_T_2119, _T_1962) @[CSR.scala 424:57] + node _T_2121 = or(_T_2120, _T_1784) @[CSR.scala 424:57] + node _T_2122 = or(_T_2121, _T_1902) @[CSR.scala 424:57] + node _T_2123 = or(_T_2122, _T_1994) @[CSR.scala 424:57] + node _T_2124 = or(_T_2123, _T_2016) @[CSR.scala 424:57] + node _T_2125 = or(_T_2124, _T_1930) @[CSR.scala 424:57] + node _T_2126 = or(_T_2125, _T_1816) @[CSR.scala 424:57] + node _T_2127 = or(_T_2126, _T_1834) @[CSR.scala 424:57] + node _T_2128 = or(_T_2127, _T_1966) @[CSR.scala 424:57] + node _T_2129 = or(_T_2128, _T_1898) @[CSR.scala 424:57] + node _T_2130 = or(_T_2129, _T_1866) @[CSR.scala 424:57] + node _T_2131 = or(_T_2130, _T_1998) @[CSR.scala 424:57] + node _T_2132 = or(_T_2131, _T_1926) @[CSR.scala 424:57] + node _T_2133 = or(_T_2132, _T_1794) @[CSR.scala 424:57] + node _T_2134 = or(_T_2133, _T_1882) @[CSR.scala 424:57] + node _T_2135 = or(_T_2134, _T_1970) @[CSR.scala 424:57] + node _T_2136 = or(_T_2135, _T_1822) @[CSR.scala 424:57] + node _T_2137 = or(_T_2136, _T_1894) @[CSR.scala 424:57] + node _T_2138 = or(_T_2137, _T_2002) @[CSR.scala 424:57] + node _T_2139 = or(_T_2138, _T_1854) @[CSR.scala 424:57] + node _T_2140 = or(_T_2139, _T_1938) @[CSR.scala 424:57] + node _T_2141 = or(_T_2140, _T_1984) @[CSR.scala 424:57] + node _T_2142 = or(_T_2141, _T_1790) @[CSR.scala 424:57] + node _T_2143 = or(_T_2142, _T_1852) @[CSR.scala 424:57] + node _T_2144 = or(_T_2143, _T_1958) @[CSR.scala 424:57] + node _T_2145 = or(_T_2144, _T_1826) @[CSR.scala 424:57] + node _T_2146 = or(_T_2145, _T_2022) @[CSR.scala 424:57] + node _T_2147 = or(_T_2146, _T_1906) @[CSR.scala 424:57] + node _T_2148 = or(_T_2147, _T_1990) @[CSR.scala 424:57] + node _T_2149 = or(_T_2148, _T_1858) @[CSR.scala 424:57] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[CSR.scala 424:5] + node _T_2152 = or(_T_1772, _T_2151) @[CSR.scala 423:64] + node _T_2154 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 425:19] + node _T_2156 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 425:37] + node _T_2157 = and(_T_2154, _T_2156) @[CSR.scala 425:34] + node _T_2158 = or(_T_2152, _T_2157) @[CSR.scala 424:62] + node _T_2161 = geq(io.decode.csr, UInt<12>("h0c00")) @[Package.scala 47:47] + node _T_2162 = lt(io.decode.csr, UInt<12>("h0c20")) @[Package.scala 47:60] + node _T_2163 = and(_T_2161, _T_2162) @[Package.scala 47:55] + node _T_2166 = geq(io.decode.csr, UInt<12>("h0c80")) @[Package.scala 47:47] + node _T_2167 = lt(io.decode.csr, UInt<12>("h0ca0")) @[Package.scala 47:60] + node _T_2168 = and(_T_2166, _T_2167) @[Package.scala 47:55] + node _T_2169 = or(_T_2163, _T_2168) @[CSR.scala 426:67] + node _T_2171 = leq(effective_prv, UInt<1>("h01")) @[CSR.scala 426:151] + node _T_2172 = and(_T_2169, _T_2171) @[CSR.scala 426:134] + node _T_2173 = bits(io.decode.csr, 11, 0) @[CSR.scala 426:185] + node _T_2174 = dshr(hpm_mask, _T_2173) @[CSR.scala 426:171] + node _T_2175 = bits(_T_2174, 0, 0) @[CSR.scala 426:171] + node _T_2176 = and(_T_2172, _T_2175) @[CSR.scala 426:160] + node _T_2177 = or(_T_2158, _T_2176) @[CSR.scala 425:55] + node _T_2180 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 427:25] + node _T_2181 = and(UInt<1>("h01"), _T_2180) @[CSR.scala 427:22] + node _T_2183 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 427:73] + node _T_2185 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 427:73] + node _T_2187 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 427:73] + node _T_2188 = or(_T_2183, _T_2185) @[CSR.scala 427:88] + node _T_2189 = or(_T_2188, _T_2187) @[CSR.scala 427:88] + node _T_2190 = and(_T_2181, _T_2189) @[CSR.scala 427:36] + node _T_2191 = or(_T_2177, _T_2190) @[CSR.scala 426:215] + node _T_2194 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 428:54] + node _T_2196 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 428:54] + node _T_2198 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 428:54] + node _T_2199 = or(_T_2194, _T_2196) @[CSR.scala 428:69] + node _T_2200 = or(_T_2199, _T_2198) @[CSR.scala 428:69] + node _T_2201 = and(UInt<1>("h01"), _T_2200) @[CSR.scala 428:20] + node _T_2202 = and(_T_2201, io.decode.fp_illegal) @[CSR.scala 428:74] + node _T_2203 = or(_T_2191, _T_2202) @[CSR.scala 427:93] + io.decode.read_illegal <= _T_2203 @[CSR.scala 423:26] + node _T_2204 = bits(io.decode.csr, 11, 10) @[CSR.scala 429:43] + node _T_2205 = not(_T_2204) @[CSR.scala 429:51] + node _T_2207 = eq(_T_2205, UInt<1>("h00")) @[CSR.scala 429:51] + io.decode.write_illegal <= _T_2207 @[CSR.scala 429:27] + node _T_2209 = geq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 430:44] + node _T_2211 = leq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 430:78] + node _T_2212 = and(_T_2209, _T_2211) @[CSR.scala 430:61] + node _T_2214 = geq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 430:112] + node _T_2216 = leq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 430:146] + node _T_2217 = and(_T_2214, _T_2216) @[CSR.scala 430:129] + node _T_2218 = or(_T_2212, _T_2217) @[CSR.scala 430:95] + node _T_2220 = eq(_T_2218, UInt<1>("h00")) @[CSR.scala 430:28] + io.decode.write_flush <= _T_2220 @[CSR.scala 430:25] + node _T_2221 = bits(io.decode.csr, 9, 8) @[CSR.scala 431:60] + node _T_2222 = lt(effective_prv, _T_2221) @[CSR.scala 431:45] + node _T_2223 = bits(io.decode.csr, 5, 5) @[CSR.scala 432:19] + node _T_2225 = eq(_T_2223, UInt<1>("h00")) @[CSR.scala 432:5] + node _T_2226 = bits(io.decode.csr, 2, 2) @[CSR.scala 432:39] + node _T_2227 = and(_T_2225, _T_2226) @[CSR.scala 432:23] + node _T_2229 = eq(allow_wfi, UInt<1>("h00")) @[CSR.scala 432:46] + node _T_2230 = and(_T_2227, _T_2229) @[CSR.scala 432:43] + node _T_2231 = or(_T_2222, _T_2230) @[CSR.scala 431:66] + node _T_2232 = bits(io.decode.csr, 5, 5) @[CSR.scala 433:19] + node _T_2234 = eq(_T_2232, UInt<1>("h00")) @[CSR.scala 433:5] + node _T_2235 = bits(io.decode.csr, 1, 1) @[CSR.scala 433:39] + node _T_2236 = and(_T_2234, _T_2235) @[CSR.scala 433:23] + node _T_2238 = eq(allow_sret, UInt<1>("h00")) @[CSR.scala 433:46] + node _T_2239 = and(_T_2236, _T_2238) @[CSR.scala 433:43] + node _T_2240 = or(_T_2231, _T_2239) @[CSR.scala 432:57] + node _T_2241 = bits(io.decode.csr, 5, 5) @[CSR.scala 434:18] + node _T_2243 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 434:25] + node _T_2244 = and(_T_2241, _T_2243) @[CSR.scala 434:22] + node _T_2245 = or(_T_2240, _T_2244) @[CSR.scala 433:58] + io.decode.system_illegal <= _T_2245 @[CSR.scala 431:28] + node _T_2247 = add(reg_mstatus.prv, UInt<4>("h08")) @[CSR.scala 437:36] + node _T_2248 = tail(_T_2247, 1) @[CSR.scala 437:36] + node _T_2250 = mux(insn_break, UInt<2>("h03"), io.cause) @[CSR.scala 438:14] + node cause = mux(insn_call, _T_2248, _T_2250) @[CSR.scala 437:8] + node cause_lsbs = bits(cause, 5, 0) @[CSR.scala 439:25] + node _T_2251 = bits(cause, 63, 63) @[CSR.scala 440:30] + node _T_2267 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 440:53] + node causeIsDebugInt = and(_T_2251, _T_2267) @[CSR.scala 440:39] + node _T_2268 = bits(cause, 63, 63) @[CSR.scala 441:35] + node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[CSR.scala 441:29] + node _T_2300 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 441:58] + node causeIsDebugTrigger = and(_T_2270, _T_2300) @[CSR.scala 441:44] + node _T_2301 = bits(cause, 63, 63) @[CSR.scala 442:33] + node _T_2303 = eq(_T_2301, UInt<1>("h00")) @[CSR.scala 442:27] + node _T_2304 = and(_T_2303, insn_break) @[CSR.scala 442:42] + node _T_2305 = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) @[Cat.scala 30:58] + node _T_2306 = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) @[Cat.scala 30:58] + node _T_2307 = cat(_T_2306, _T_2305) @[Cat.scala 30:58] + node _T_2308 = dshr(_T_2307, reg_mstatus.prv) @[CSR.scala 442:134] + node _T_2309 = bits(_T_2308, 0, 0) @[CSR.scala 442:134] + node causeIsDebugBreak = and(_T_2304, _T_2309) @[CSR.scala 442:56] + node _T_2311 = or(reg_singleStepped, causeIsDebugInt) @[CSR.scala 443:60] + node _T_2312 = or(_T_2311, causeIsDebugTrigger) @[CSR.scala 443:79] + node _T_2313 = or(_T_2312, causeIsDebugBreak) @[CSR.scala 443:102] + node _T_2314 = or(_T_2313, reg_debug) @[CSR.scala 443:123] + node trapToDebug = and(UInt<1>("h01"), _T_2314) @[CSR.scala 443:38] + node _T_2317 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 444:51] + node _T_2318 = and(UInt<1>("h01"), _T_2317) @[CSR.scala 444:32] + node _T_2319 = bits(cause, 63, 63) @[CSR.scala 444:72] + node _T_2320 = dshr(reg_mideleg, cause_lsbs) @[CSR.scala 444:93] + node _T_2321 = bits(_T_2320, 0, 0) @[CSR.scala 444:93] + node _T_2322 = dshr(reg_medeleg, cause_lsbs) @[CSR.scala 444:118] + node _T_2323 = bits(_T_2322, 0, 0) @[CSR.scala 444:118] + node _T_2324 = mux(_T_2319, _T_2321, _T_2323) @[CSR.scala 444:66] + node delegate = and(_T_2318, _T_2324) @[CSR.scala 444:60] + node debugTVec = mux(reg_debug, UInt<12>("h0808"), UInt<12>("h0800")) @[CSR.scala 445:22] + node _T_2327 = bits(reg_stvec, 38, 38) @[Package.scala 40:38] + node _T_2328 = cat(_T_2327, reg_stvec) @[Cat.scala 30:58] + node _T_2329 = mux(delegate, _T_2328, reg_mtvec) @[CSR.scala 446:45] + node tvec = mux(trapToDebug, debugTVec, _T_2329) @[CSR.scala 446:17] + io.fatc <= insn_sfence_vma @[CSR.scala 447:11] + io.evec <= tvec @[CSR.scala 448:11] + io.ptbr <- reg_sptbr @[CSR.scala 449:11] + node _T_2330 = or(insn_call, insn_break) @[CSR.scala 450:24] + node _T_2331 = or(_T_2330, insn_ret) @[CSR.scala 450:38] + io.eret <= _T_2331 @[CSR.scala 450:11] + node _T_2333 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 451:37] + node _T_2334 = and(reg_dcsr.step, _T_2333) @[CSR.scala 451:34] + io.singleStep <= _T_2334 @[CSR.scala 451:17] + io.status <- reg_mstatus @[CSR.scala 452:13] + node _T_2335 = not(io.status.fs) @[CSR.scala 453:32] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[CSR.scala 453:32] + node _T_2338 = not(io.status.xs) @[CSR.scala 453:53] + node _T_2340 = eq(_T_2338, UInt<1>("h00")) @[CSR.scala 453:53] + node _T_2341 = or(_T_2337, _T_2340) @[CSR.scala 453:37] + io.status.sd <= _T_2341 @[CSR.scala 453:16] + io.status.debug <= reg_debug @[CSR.scala 454:19] + io.status.isa <= reg_misa @[CSR.scala 455:17] + io.status.uxl <= UInt<2>("h02") @[CSR.scala 456:17] + io.status.sxl <= UInt<2>("h02") @[CSR.scala 457:17] + node _T_2344 = or(insn_call, insn_break) @[CSR.scala 461:29] + node exception = or(_T_2344, io.exception) @[CSR.scala 461:43] + node _T_2345 = add(insn_ret, insn_call) @[Bitwise.scala 48:55] + node _T_2346 = add(insn_break, io.exception) @[Bitwise.scala 48:55] + node _T_2347 = add(_T_2345, _T_2346) @[Bitwise.scala 48:55] + node _T_2349 = leq(_T_2347, UInt<1>("h01")) @[CSR.scala 462:79] + node _T_2350 = or(_T_2349, reset) @[CSR.scala 462:9] + node _T_2352 = eq(_T_2350, UInt<1>("h00")) @[CSR.scala 462:9] + when _T_2352 : @[CSR.scala 462:9] + printf(clock, UInt<1>(1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:462 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n") @[CSR.scala 462:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 462:9] + skip @[CSR.scala 462:9] + when insn_wfi : @[CSR.scala 464:19] + reg_wfi <= UInt<1>("h01") @[CSR.scala 464:29] + skip @[CSR.scala 464:19] + node _T_2355 = neq(pending_interrupts, UInt<1>("h00")) @[CSR.scala 465:28] + node _T_2356 = or(_T_2355, exception) @[CSR.scala 465:32] + when _T_2356 : @[CSR.scala 465:46] + reg_wfi <= UInt<1>("h00") @[CSR.scala 465:56] + skip @[CSR.scala 465:46] + node _T_2359 = eq(reg_wfi, UInt<1>("h00")) @[CSR.scala 466:10] + node _T_2361 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 466:32] + node _T_2362 = or(_T_2359, _T_2361) @[CSR.scala 466:19] + node _T_2363 = or(_T_2362, reset) @[CSR.scala 466:9] + node _T_2365 = eq(_T_2363, UInt<1>("h00")) @[CSR.scala 466:9] + when _T_2365 : @[CSR.scala 466:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:466 assert(!reg_wfi || io.retire === UInt(0))\n") @[CSR.scala 466:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 466:9] + skip @[CSR.scala 466:9] + node _T_2366 = bits(io.retire, 0, 0) @[CSR.scala 468:18] + when _T_2366 : @[CSR.scala 468:23] + reg_singleStepped <= UInt<1>("h01") @[CSR.scala 468:43] + skip @[CSR.scala 468:23] + node _T_2369 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 469:9] + when _T_2369 : @[CSR.scala 469:25] + reg_singleStepped <= UInt<1>("h00") @[CSR.scala 469:45] + skip @[CSR.scala 469:25] + node _T_2372 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 470:10] + node _T_2374 = leq(io.retire, UInt<1>("h01")) @[CSR.scala 470:38] + node _T_2375 = or(_T_2372, _T_2374) @[CSR.scala 470:25] + node _T_2376 = or(_T_2375, reset) @[CSR.scala 470:9] + node _T_2378 = eq(_T_2376, UInt<1>("h00")) @[CSR.scala 470:9] + when _T_2378 : @[CSR.scala 470:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:470 assert(!io.singleStep || io.retire <= UInt(1))\n") @[CSR.scala 470:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 470:9] + skip @[CSR.scala 470:9] + node _T_2380 = eq(reg_singleStepped, UInt<1>("h00")) @[CSR.scala 471:10] + node _T_2382 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 471:42] + node _T_2383 = or(_T_2380, _T_2382) @[CSR.scala 471:29] + node _T_2384 = or(_T_2383, reset) @[CSR.scala 471:9] + node _T_2386 = eq(_T_2384, UInt<1>("h00")) @[CSR.scala 471:9] + when _T_2386 : @[CSR.scala 471:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:471 assert(!reg_singleStepped || io.retire === UInt(0))\n") @[CSR.scala 471:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 471:9] + skip @[CSR.scala 471:9] + when exception : @[CSR.scala 473:20] + node _T_2387 = not(io.pc) @[CSR.scala 474:17] + node _T_2389 = or(_T_2387, UInt<1>("h01")) @[CSR.scala 474:24] + node _T_2390 = not(_T_2389) @[CSR.scala 474:15] + node _T_2391 = dshr(read_mstatus, reg_mstatus.prv) @[CSR.scala 475:27] + node _T_2392 = bits(_T_2391, 0, 0) @[CSR.scala 475:27] + node _T_2400 = eq(cause, UInt<2>("h03")) @[Package.scala 7:47] + node _T_2401 = eq(cause, UInt<3>("h04")) @[Package.scala 7:47] + node _T_2402 = eq(cause, UInt<3>("h06")) @[Package.scala 7:47] + node _T_2403 = eq(cause, UInt<1>("h00")) @[Package.scala 7:47] + node _T_2404 = eq(cause, UInt<3>("h05")) @[Package.scala 7:47] + node _T_2405 = eq(cause, UInt<3>("h07")) @[Package.scala 7:47] + node _T_2406 = eq(cause, UInt<1>("h01")) @[Package.scala 7:47] + node _T_2407 = or(_T_2400, _T_2401) @[Package.scala 7:62] + node _T_2408 = or(_T_2407, _T_2402) @[Package.scala 7:62] + node _T_2409 = or(_T_2408, _T_2403) @[Package.scala 7:62] + node _T_2410 = or(_T_2409, _T_2404) @[Package.scala 7:62] + node _T_2411 = or(_T_2410, _T_2405) @[Package.scala 7:62] + node _T_2412 = or(_T_2411, _T_2406) @[Package.scala 7:62] + when trapToDebug : @[CSR.scala 481:24] + reg_debug <= UInt<1>("h01") @[CSR.scala 482:17] + reg_dpc <= _T_2390 @[CSR.scala 483:15] + node _T_2418 = mux(causeIsDebugTrigger, UInt<2>("h02"), UInt<1>("h01")) @[CSR.scala 484:84] + node _T_2419 = mux(causeIsDebugInt, UInt<2>("h03"), _T_2418) @[CSR.scala 484:54] + node _T_2420 = mux(reg_singleStepped, UInt<3>("h04"), _T_2419) @[CSR.scala 484:28] + reg_dcsr.cause <= _T_2420 @[CSR.scala 484:22] + reg_dcsr.prv <= reg_mstatus.prv @[CSR.scala 485:20] + skip @[CSR.scala 481:24] + node _T_2422 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24] + node _T_2423 = and(_T_2422, delegate) @[CSR.scala 486:27] + when _T_2423 : @[CSR.scala 486:27] + node _T_2424 = not(_T_2390) @[CSR.scala 714:28] + node _T_2425 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_2427 = eq(_T_2425, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_2429 = cat(_T_2427, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_2430 = or(_T_2424, _T_2429) @[CSR.scala 714:31] + node _T_2431 = not(_T_2430) @[CSR.scala 714:26] + reg_sepc <= _T_2431 @[CSR.scala 487:16] + reg_scause <= cause @[CSR.scala 488:18] + when _T_2412 : @[CSR.scala 489:28] + reg_sbadaddr <= io.badaddr @[CSR.scala 489:43] + skip @[CSR.scala 489:28] + reg_mstatus.spie <= _T_2392 @[CSR.scala 490:24] + reg_mstatus.spp <= reg_mstatus.prv @[CSR.scala 491:23] + reg_mstatus.sie <= UInt<1>("h00") @[CSR.scala 492:23] + new_prv <= UInt<1>("h01") @[CSR.scala 493:15] + skip @[CSR.scala 486:27] + node _T_2435 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24] + node _T_2437 = eq(delegate, UInt<1>("h00")) @[CSR.scala 486:27] + node _T_2438 = and(_T_2435, _T_2437) @[CSR.scala 486:27] + when _T_2438 : @[CSR.scala 494:17] + node _T_2439 = not(_T_2390) @[CSR.scala 714:28] + node _T_2440 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_2442 = eq(_T_2440, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_2444 = cat(_T_2442, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_2445 = or(_T_2439, _T_2444) @[CSR.scala 714:31] + node _T_2446 = not(_T_2445) @[CSR.scala 714:26] + reg_mepc <= _T_2446 @[CSR.scala 495:16] + reg_mcause <= cause @[CSR.scala 496:18] + when _T_2412 : @[CSR.scala 497:28] + reg_mbadaddr <= io.badaddr @[CSR.scala 497:43] + skip @[CSR.scala 497:28] + reg_mstatus.mpie <= _T_2392 @[CSR.scala 498:24] + reg_mstatus.mpp <= reg_mstatus.prv @[CSR.scala 499:23] + reg_mstatus.mie <= UInt<1>("h00") @[CSR.scala 500:23] + new_prv <= UInt<2>("h03") @[CSR.scala 501:15] + skip @[CSR.scala 494:17] + skip @[CSR.scala 473:20] + when insn_ret : @[CSR.scala 505:19] + node _T_2450 = bits(io.rw.addr, 9, 9) @[CSR.scala 506:39] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[CSR.scala 506:28] + node _T_2453 = and(UInt<1>("h01"), _T_2452) @[CSR.scala 506:25] + when _T_2453 : @[CSR.scala 506:44] + node _T_2454 = bits(reg_mstatus.spp, 0, 0) @[CSR.scala 507:29] + when _T_2454 : @[CSR.scala 507:37] + reg_mstatus.sie <= reg_mstatus.spie @[CSR.scala 507:55] + skip @[CSR.scala 507:37] + reg_mstatus.spie <= UInt<1>("h01") @[CSR.scala 508:24] + reg_mstatus.spp <= UInt<1>("h00") @[CSR.scala 509:23] + new_prv <= reg_mstatus.spp @[CSR.scala 510:15] + io.evec <= reg_sepc @[CSR.scala 511:15] + skip @[CSR.scala 506:44] + node _T_2458 = bits(io.rw.addr, 10, 10) @[CSR.scala 512:47] + node _T_2459 = and(UInt<1>("h01"), _T_2458) @[CSR.scala 512:34] + node _T_2461 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44] + node _T_2462 = and(_T_2461, _T_2459) @[CSR.scala 512:53] + when _T_2462 : @[CSR.scala 512:53] + new_prv <= reg_dcsr.prv @[CSR.scala 513:15] + reg_debug <= UInt<1>("h00") @[CSR.scala 514:17] + io.evec <= reg_dpc @[CSR.scala 515:15] + skip @[CSR.scala 512:53] + node _T_2465 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44] + node _T_2467 = eq(_T_2459, UInt<1>("h00")) @[CSR.scala 512:53] + node _T_2468 = and(_T_2465, _T_2467) @[CSR.scala 512:53] + when _T_2468 : @[CSR.scala 516:17] + node _T_2469 = bits(reg_mstatus.mpp, 1, 1) @[CSR.scala 517:28] + when _T_2469 : @[CSR.scala 517:33] + reg_mstatus.mie <= reg_mstatus.mpie @[CSR.scala 517:51] + skip @[CSR.scala 517:33] + node _T_2471 = bits(reg_mstatus.mpp, 0, 0) @[CSR.scala 518:50] + node _T_2472 = and(UInt<1>("h01"), _T_2471) @[CSR.scala 518:32] + node _T_2474 = eq(_T_2469, UInt<1>("h00")) @[CSR.scala 517:33] + node _T_2475 = and(_T_2474, _T_2472) @[CSR.scala 518:55] + when _T_2475 : @[CSR.scala 518:55] + reg_mstatus.sie <= reg_mstatus.mpie @[CSR.scala 518:73] + skip @[CSR.scala 518:55] + reg_mstatus.mpie <= UInt<1>("h01") @[CSR.scala 519:24] + node _T_2479 = eq(UInt<1>("h00"), UInt<2>("h02")) @[CSR.scala 697:27] + node _T_2481 = mux(_T_2479, UInt<1>("h00"), UInt<1>("h00")) @[CSR.scala 697:21] + reg_mstatus.mpp <= _T_2481 @[CSR.scala 520:23] + new_prv <= reg_mstatus.mpp @[CSR.scala 521:15] + io.evec <= reg_mepc @[CSR.scala 522:15] + skip @[CSR.scala 516:17] + skip @[CSR.scala 505:19] + io.time <= _T_950 @[CSR.scala 526:11] + io.csr_stall <= reg_wfi @[CSR.scala 527:16] + node _T_2483 = mux(_T_1467, reg_tselect, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2485 = mux(_T_1469, _T_1304, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2487 = mux(_T_1471, _T_1345, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2489 = mux(_T_1473, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2491 = mux(_T_1475, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2493 = mux(_T_1477, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2495 = mux(_T_1479, _T_950, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2497 = mux(_T_1481, _T_939, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2499 = mux(_T_1483, reg_misa, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2501 = mux(_T_1485, read_mstatus, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2503 = mux(_T_1487, reg_mtvec, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2505 = mux(_T_1489, read_mip, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2507 = mux(_T_1491, reg_mie, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2509 = mux(_T_1493, reg_mideleg, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2511 = mux(_T_1495, reg_medeleg, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2513 = mux(_T_1497, reg_mscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2515 = mux(_T_1499, _T_1354, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2517 = mux(_T_1501, _T_1360, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2519 = mux(_T_1503, reg_mcause, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2521 = mux(_T_1505, io.hartid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2523 = mux(_T_1507, _T_1376, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2525 = mux(_T_1509, reg_dpc, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2527 = mux(_T_1511, reg_dscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2529 = mux(_T_1513, reg_fflags, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2531 = mux(_T_1515, reg_frm, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2533 = mux(_T_1517, _T_1377, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2535 = mux(_T_1519, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2537 = mux(_T_1521, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2539 = mux(_T_1523, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2541 = mux(_T_1525, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2543 = mux(_T_1527, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2545 = mux(_T_1529, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2547 = mux(_T_1531, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2549 = mux(_T_1533, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2551 = mux(_T_1535, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2553 = mux(_T_1537, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2555 = mux(_T_1539, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2557 = mux(_T_1541, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2559 = mux(_T_1543, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2561 = mux(_T_1545, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2563 = mux(_T_1547, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2565 = mux(_T_1549, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2567 = mux(_T_1551, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2569 = mux(_T_1553, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2571 = mux(_T_1555, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2573 = mux(_T_1557, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2575 = mux(_T_1559, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2577 = mux(_T_1561, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2579 = mux(_T_1563, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2581 = mux(_T_1565, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2583 = mux(_T_1567, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2585 = mux(_T_1569, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2587 = mux(_T_1571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2589 = mux(_T_1573, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2591 = mux(_T_1575, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2593 = mux(_T_1577, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2595 = mux(_T_1579, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2597 = mux(_T_1581, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2599 = mux(_T_1583, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2601 = mux(_T_1585, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2603 = mux(_T_1587, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2605 = mux(_T_1589, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2607 = mux(_T_1591, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2609 = mux(_T_1593, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2611 = mux(_T_1595, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2613 = mux(_T_1597, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2615 = mux(_T_1599, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2617 = mux(_T_1601, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2619 = mux(_T_1603, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2621 = mux(_T_1605, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2623 = mux(_T_1607, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2625 = mux(_T_1609, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2627 = mux(_T_1611, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2629 = mux(_T_1613, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2631 = mux(_T_1615, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2633 = mux(_T_1617, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2635 = mux(_T_1619, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2637 = mux(_T_1621, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2639 = mux(_T_1623, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2641 = mux(_T_1625, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2643 = mux(_T_1627, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2645 = mux(_T_1629, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2647 = mux(_T_1631, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2649 = mux(_T_1633, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2651 = mux(_T_1635, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2653 = mux(_T_1637, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2655 = mux(_T_1639, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2657 = mux(_T_1641, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2659 = mux(_T_1643, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2661 = mux(_T_1645, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2663 = mux(_T_1647, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2665 = mux(_T_1649, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2667 = mux(_T_1651, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2669 = mux(_T_1653, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2671 = mux(_T_1655, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2673 = mux(_T_1657, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2675 = mux(_T_1659, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2677 = mux(_T_1661, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2679 = mux(_T_1663, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2681 = mux(_T_1665, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2683 = mux(_T_1667, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2685 = mux(_T_1669, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2687 = mux(_T_1671, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2689 = mux(_T_1673, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2691 = mux(_T_1675, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2693 = mux(_T_1677, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2695 = mux(_T_1679, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2697 = mux(_T_1681, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2699 = mux(_T_1683, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2701 = mux(_T_1685, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2703 = mux(_T_1687, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2705 = mux(_T_1689, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2707 = mux(_T_1691, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2709 = mux(_T_1693, _T_1445, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2711 = mux(_T_1695, _T_1381, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2713 = mux(_T_1697, _T_1380, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2715 = mux(_T_1699, reg_sscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2717 = mux(_T_1701, reg_scause, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2719 = mux(_T_1703, _T_1451, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2721 = mux(_T_1705, _T_1453, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2723 = mux(_T_1707, _T_1459, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2725 = mux(_T_1709, _T_1465, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2727 = mux(_T_1711, reg_scounteren, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2729 = mux(_T_1713, reg_mcounteren, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2731 = mux(_T_1715, _T_950, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2733 = mux(_T_1717, _T_939, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2735 = or(_T_2483, _T_2485) @[Mux.scala 19:72] + node _T_2736 = or(_T_2735, _T_2487) @[Mux.scala 19:72] + node _T_2737 = or(_T_2736, _T_2489) @[Mux.scala 19:72] + node _T_2738 = or(_T_2737, _T_2491) @[Mux.scala 19:72] + node _T_2739 = or(_T_2738, _T_2493) @[Mux.scala 19:72] + node _T_2740 = or(_T_2739, _T_2495) @[Mux.scala 19:72] + node _T_2741 = or(_T_2740, _T_2497) @[Mux.scala 19:72] + node _T_2742 = or(_T_2741, _T_2499) @[Mux.scala 19:72] + node _T_2743 = or(_T_2742, _T_2501) @[Mux.scala 19:72] + node _T_2744 = or(_T_2743, _T_2503) @[Mux.scala 19:72] + node _T_2745 = or(_T_2744, _T_2505) @[Mux.scala 19:72] + node _T_2746 = or(_T_2745, _T_2507) @[Mux.scala 19:72] + node _T_2747 = or(_T_2746, _T_2509) @[Mux.scala 19:72] + node _T_2748 = or(_T_2747, _T_2511) @[Mux.scala 19:72] + node _T_2749 = or(_T_2748, _T_2513) @[Mux.scala 19:72] + node _T_2750 = or(_T_2749, _T_2515) @[Mux.scala 19:72] + node _T_2751 = or(_T_2750, _T_2517) @[Mux.scala 19:72] + node _T_2752 = or(_T_2751, _T_2519) @[Mux.scala 19:72] + node _T_2753 = or(_T_2752, _T_2521) @[Mux.scala 19:72] + node _T_2754 = or(_T_2753, _T_2523) @[Mux.scala 19:72] + node _T_2755 = or(_T_2754, _T_2525) @[Mux.scala 19:72] + node _T_2756 = or(_T_2755, _T_2527) @[Mux.scala 19:72] + node _T_2757 = or(_T_2756, _T_2529) @[Mux.scala 19:72] + node _T_2758 = or(_T_2757, _T_2531) @[Mux.scala 19:72] + node _T_2759 = or(_T_2758, _T_2533) @[Mux.scala 19:72] + node _T_2760 = or(_T_2759, _T_2535) @[Mux.scala 19:72] + node _T_2761 = or(_T_2760, _T_2537) @[Mux.scala 19:72] + node _T_2762 = or(_T_2761, _T_2539) @[Mux.scala 19:72] + node _T_2763 = or(_T_2762, _T_2541) @[Mux.scala 19:72] + node _T_2764 = or(_T_2763, _T_2543) @[Mux.scala 19:72] + node _T_2765 = or(_T_2764, _T_2545) @[Mux.scala 19:72] + node _T_2766 = or(_T_2765, _T_2547) @[Mux.scala 19:72] + node _T_2767 = or(_T_2766, _T_2549) @[Mux.scala 19:72] + node _T_2768 = or(_T_2767, _T_2551) @[Mux.scala 19:72] + node _T_2769 = or(_T_2768, _T_2553) @[Mux.scala 19:72] + node _T_2770 = or(_T_2769, _T_2555) @[Mux.scala 19:72] + node _T_2771 = or(_T_2770, _T_2557) @[Mux.scala 19:72] + node _T_2772 = or(_T_2771, _T_2559) @[Mux.scala 19:72] + node _T_2773 = or(_T_2772, _T_2561) @[Mux.scala 19:72] + node _T_2774 = or(_T_2773, _T_2563) @[Mux.scala 19:72] + node _T_2775 = or(_T_2774, _T_2565) @[Mux.scala 19:72] + node _T_2776 = or(_T_2775, _T_2567) @[Mux.scala 19:72] + node _T_2777 = or(_T_2776, _T_2569) @[Mux.scala 19:72] + node _T_2778 = or(_T_2777, _T_2571) @[Mux.scala 19:72] + node _T_2779 = or(_T_2778, _T_2573) @[Mux.scala 19:72] + node _T_2780 = or(_T_2779, _T_2575) @[Mux.scala 19:72] + node _T_2781 = or(_T_2780, _T_2577) @[Mux.scala 19:72] + node _T_2782 = or(_T_2781, _T_2579) @[Mux.scala 19:72] + node _T_2783 = or(_T_2782, _T_2581) @[Mux.scala 19:72] + node _T_2784 = or(_T_2783, _T_2583) @[Mux.scala 19:72] + node _T_2785 = or(_T_2784, _T_2585) @[Mux.scala 19:72] + node _T_2786 = or(_T_2785, _T_2587) @[Mux.scala 19:72] + node _T_2787 = or(_T_2786, _T_2589) @[Mux.scala 19:72] + node _T_2788 = or(_T_2787, _T_2591) @[Mux.scala 19:72] + node _T_2789 = or(_T_2788, _T_2593) @[Mux.scala 19:72] + node _T_2790 = or(_T_2789, _T_2595) @[Mux.scala 19:72] + node _T_2791 = or(_T_2790, _T_2597) @[Mux.scala 19:72] + node _T_2792 = or(_T_2791, _T_2599) @[Mux.scala 19:72] + node _T_2793 = or(_T_2792, _T_2601) @[Mux.scala 19:72] + node _T_2794 = or(_T_2793, _T_2603) @[Mux.scala 19:72] + node _T_2795 = or(_T_2794, _T_2605) @[Mux.scala 19:72] + node _T_2796 = or(_T_2795, _T_2607) @[Mux.scala 19:72] + node _T_2797 = or(_T_2796, _T_2609) @[Mux.scala 19:72] + node _T_2798 = or(_T_2797, _T_2611) @[Mux.scala 19:72] + node _T_2799 = or(_T_2798, _T_2613) @[Mux.scala 19:72] + node _T_2800 = or(_T_2799, _T_2615) @[Mux.scala 19:72] + node _T_2801 = or(_T_2800, _T_2617) @[Mux.scala 19:72] + node _T_2802 = or(_T_2801, _T_2619) @[Mux.scala 19:72] + node _T_2803 = or(_T_2802, _T_2621) @[Mux.scala 19:72] + node _T_2804 = or(_T_2803, _T_2623) @[Mux.scala 19:72] + node _T_2805 = or(_T_2804, _T_2625) @[Mux.scala 19:72] + node _T_2806 = or(_T_2805, _T_2627) @[Mux.scala 19:72] + node _T_2807 = or(_T_2806, _T_2629) @[Mux.scala 19:72] + node _T_2808 = or(_T_2807, _T_2631) @[Mux.scala 19:72] + node _T_2809 = or(_T_2808, _T_2633) @[Mux.scala 19:72] + node _T_2810 = or(_T_2809, _T_2635) @[Mux.scala 19:72] + node _T_2811 = or(_T_2810, _T_2637) @[Mux.scala 19:72] + node _T_2812 = or(_T_2811, _T_2639) @[Mux.scala 19:72] + node _T_2813 = or(_T_2812, _T_2641) @[Mux.scala 19:72] + node _T_2814 = or(_T_2813, _T_2643) @[Mux.scala 19:72] + node _T_2815 = or(_T_2814, _T_2645) @[Mux.scala 19:72] + node _T_2816 = or(_T_2815, _T_2647) @[Mux.scala 19:72] + node _T_2817 = or(_T_2816, _T_2649) @[Mux.scala 19:72] + node _T_2818 = or(_T_2817, _T_2651) @[Mux.scala 19:72] + node _T_2819 = or(_T_2818, _T_2653) @[Mux.scala 19:72] + node _T_2820 = or(_T_2819, _T_2655) @[Mux.scala 19:72] + node _T_2821 = or(_T_2820, _T_2657) @[Mux.scala 19:72] + node _T_2822 = or(_T_2821, _T_2659) @[Mux.scala 19:72] + node _T_2823 = or(_T_2822, _T_2661) @[Mux.scala 19:72] + node _T_2824 = or(_T_2823, _T_2663) @[Mux.scala 19:72] + node _T_2825 = or(_T_2824, _T_2665) @[Mux.scala 19:72] + node _T_2826 = or(_T_2825, _T_2667) @[Mux.scala 19:72] + node _T_2827 = or(_T_2826, _T_2669) @[Mux.scala 19:72] + node _T_2828 = or(_T_2827, _T_2671) @[Mux.scala 19:72] + node _T_2829 = or(_T_2828, _T_2673) @[Mux.scala 19:72] + node _T_2830 = or(_T_2829, _T_2675) @[Mux.scala 19:72] + node _T_2831 = or(_T_2830, _T_2677) @[Mux.scala 19:72] + node _T_2832 = or(_T_2831, _T_2679) @[Mux.scala 19:72] + node _T_2833 = or(_T_2832, _T_2681) @[Mux.scala 19:72] + node _T_2834 = or(_T_2833, _T_2683) @[Mux.scala 19:72] + node _T_2835 = or(_T_2834, _T_2685) @[Mux.scala 19:72] + node _T_2836 = or(_T_2835, _T_2687) @[Mux.scala 19:72] + node _T_2837 = or(_T_2836, _T_2689) @[Mux.scala 19:72] + node _T_2838 = or(_T_2837, _T_2691) @[Mux.scala 19:72] + node _T_2839 = or(_T_2838, _T_2693) @[Mux.scala 19:72] + node _T_2840 = or(_T_2839, _T_2695) @[Mux.scala 19:72] + node _T_2841 = or(_T_2840, _T_2697) @[Mux.scala 19:72] + node _T_2842 = or(_T_2841, _T_2699) @[Mux.scala 19:72] + node _T_2843 = or(_T_2842, _T_2701) @[Mux.scala 19:72] + node _T_2844 = or(_T_2843, _T_2703) @[Mux.scala 19:72] + node _T_2845 = or(_T_2844, _T_2705) @[Mux.scala 19:72] + node _T_2846 = or(_T_2845, _T_2707) @[Mux.scala 19:72] + node _T_2847 = or(_T_2846, _T_2709) @[Mux.scala 19:72] + node _T_2848 = or(_T_2847, _T_2711) @[Mux.scala 19:72] + node _T_2849 = or(_T_2848, _T_2713) @[Mux.scala 19:72] + node _T_2850 = or(_T_2849, _T_2715) @[Mux.scala 19:72] + node _T_2851 = or(_T_2850, _T_2717) @[Mux.scala 19:72] + node _T_2852 = or(_T_2851, _T_2719) @[Mux.scala 19:72] + node _T_2853 = or(_T_2852, _T_2721) @[Mux.scala 19:72] + node _T_2854 = or(_T_2853, _T_2723) @[Mux.scala 19:72] + node _T_2855 = or(_T_2854, _T_2725) @[Mux.scala 19:72] + node _T_2856 = or(_T_2855, _T_2727) @[Mux.scala 19:72] + node _T_2857 = or(_T_2856, _T_2729) @[Mux.scala 19:72] + node _T_2858 = or(_T_2857, _T_2731) @[Mux.scala 19:72] + node _T_2859 = or(_T_2858, _T_2733) @[Mux.scala 19:72] + wire _T_2861 : UInt @[Mux.scala 19:72] + _T_2861 is invalid @[Mux.scala 19:72] + _T_2861 <= _T_2859 @[Mux.scala 19:72] + io.rw.rdata <= _T_2861 @[CSR.scala 529:15] + io.fcsr_rm <= reg_frm @[CSR.scala 531:14] + when io.fcsr_flags.valid : @[CSR.scala 532:30] + node _T_2862 = or(reg_fflags, io.fcsr_flags.bits) @[CSR.scala 533:30] + reg_fflags <= _T_2862 @[CSR.scala 533:16] + skip @[CSR.scala 532:30] + node _T_2866 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47] + node _T_2867 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47] + node _T_2868 = eq(io.rw.cmd, UInt<3>("h01")) @[Package.scala 7:47] + node _T_2869 = or(_T_2866, _T_2867) @[Package.scala 7:62] + node _T_2870 = or(_T_2869, _T_2868) @[Package.scala 7:62] + when _T_2870 : @[CSR.scala 536:49] + when _T_1485 : @[CSR.scala 537:39] + wire _T_2929 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 538:47] + _T_2929 is invalid @[CSR.scala 538:47] + wire _T_2959 : UInt<99> + _T_2959 is invalid + _T_2959 <= wdata + node _T_2960 = bits(_T_2959, 0, 0) @[CSR.scala 538:47] + _T_2929.uie <= _T_2960 @[CSR.scala 538:47] + node _T_2961 = bits(_T_2959, 1, 1) @[CSR.scala 538:47] + _T_2929.sie <= _T_2961 @[CSR.scala 538:47] + node _T_2962 = bits(_T_2959, 2, 2) @[CSR.scala 538:47] + _T_2929.hie <= _T_2962 @[CSR.scala 538:47] + node _T_2963 = bits(_T_2959, 3, 3) @[CSR.scala 538:47] + _T_2929.mie <= _T_2963 @[CSR.scala 538:47] + node _T_2964 = bits(_T_2959, 4, 4) @[CSR.scala 538:47] + _T_2929.upie <= _T_2964 @[CSR.scala 538:47] + node _T_2965 = bits(_T_2959, 5, 5) @[CSR.scala 538:47] + _T_2929.spie <= _T_2965 @[CSR.scala 538:47] + node _T_2966 = bits(_T_2959, 6, 6) @[CSR.scala 538:47] + _T_2929.hpie <= _T_2966 @[CSR.scala 538:47] + node _T_2967 = bits(_T_2959, 7, 7) @[CSR.scala 538:47] + _T_2929.mpie <= _T_2967 @[CSR.scala 538:47] + node _T_2968 = bits(_T_2959, 8, 8) @[CSR.scala 538:47] + _T_2929.spp <= _T_2968 @[CSR.scala 538:47] + node _T_2969 = bits(_T_2959, 10, 9) @[CSR.scala 538:47] + _T_2929.hpp <= _T_2969 @[CSR.scala 538:47] + node _T_2970 = bits(_T_2959, 12, 11) @[CSR.scala 538:47] + _T_2929.mpp <= _T_2970 @[CSR.scala 538:47] + node _T_2971 = bits(_T_2959, 14, 13) @[CSR.scala 538:47] + _T_2929.fs <= _T_2971 @[CSR.scala 538:47] + node _T_2972 = bits(_T_2959, 16, 15) @[CSR.scala 538:47] + _T_2929.xs <= _T_2972 @[CSR.scala 538:47] + node _T_2973 = bits(_T_2959, 17, 17) @[CSR.scala 538:47] + _T_2929.mprv <= _T_2973 @[CSR.scala 538:47] + node _T_2974 = bits(_T_2959, 18, 18) @[CSR.scala 538:47] + _T_2929.pum <= _T_2974 @[CSR.scala 538:47] + node _T_2975 = bits(_T_2959, 19, 19) @[CSR.scala 538:47] + _T_2929.mxr <= _T_2975 @[CSR.scala 538:47] + node _T_2976 = bits(_T_2959, 20, 20) @[CSR.scala 538:47] + _T_2929.tvm <= _T_2976 @[CSR.scala 538:47] + node _T_2977 = bits(_T_2959, 21, 21) @[CSR.scala 538:47] + _T_2929.tw <= _T_2977 @[CSR.scala 538:47] + node _T_2978 = bits(_T_2959, 22, 22) @[CSR.scala 538:47] + _T_2929.tsr <= _T_2978 @[CSR.scala 538:47] + node _T_2979 = bits(_T_2959, 30, 23) @[CSR.scala 538:47] + _T_2929.zero1 <= _T_2979 @[CSR.scala 538:47] + node _T_2980 = bits(_T_2959, 31, 31) @[CSR.scala 538:47] + _T_2929.sd_rv32 <= _T_2980 @[CSR.scala 538:47] + node _T_2981 = bits(_T_2959, 33, 32) @[CSR.scala 538:47] + _T_2929.uxl <= _T_2981 @[CSR.scala 538:47] + node _T_2982 = bits(_T_2959, 35, 34) @[CSR.scala 538:47] + _T_2929.sxl <= _T_2982 @[CSR.scala 538:47] + node _T_2983 = bits(_T_2959, 62, 36) @[CSR.scala 538:47] + _T_2929.zero2 <= _T_2983 @[CSR.scala 538:47] + node _T_2984 = bits(_T_2959, 63, 63) @[CSR.scala 538:47] + _T_2929.sd <= _T_2984 @[CSR.scala 538:47] + node _T_2985 = bits(_T_2959, 65, 64) @[CSR.scala 538:47] + _T_2929.prv <= _T_2985 @[CSR.scala 538:47] + node _T_2986 = bits(_T_2959, 97, 66) @[CSR.scala 538:47] + _T_2929.isa <= _T_2986 @[CSR.scala 538:47] + node _T_2987 = bits(_T_2959, 98, 98) @[CSR.scala 538:47] + _T_2929.debug <= _T_2987 @[CSR.scala 538:47] + reg_mstatus.mie <= _T_2929.mie @[CSR.scala 539:23] + reg_mstatus.mpie <= _T_2929.mpie @[CSR.scala 540:24] + reg_mstatus.mprv <= _T_2929.mprv @[CSR.scala 543:26] + reg_mstatus.mpp <= _T_2929.mpp @[CSR.scala 544:25] + reg_mstatus.mxr <= _T_2929.mxr @[CSR.scala 545:25] + reg_mstatus.pum <= _T_2929.pum @[CSR.scala 547:27] + reg_mstatus.spp <= _T_2929.spp @[CSR.scala 548:27] + reg_mstatus.spie <= _T_2929.spie @[CSR.scala 549:28] + reg_mstatus.sie <= _T_2929.sie @[CSR.scala 550:27] + reg_mstatus.tw <= _T_2929.tw @[CSR.scala 551:26] + reg_mstatus.tvm <= _T_2929.tvm @[CSR.scala 552:27] + reg_mstatus.tsr <= _T_2929.tsr @[CSR.scala 553:27] + node _T_2989 = neq(_T_2929.fs, UInt<1>("h00")) @[CSR.scala 557:73] + node _T_2990 = bits(_T_2989, 0, 0) @[Bitwise.scala 71:15] + node _T_2993 = mux(_T_2990, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12] + reg_mstatus.fs <= _T_2993 @[CSR.scala 557:47] + skip @[CSR.scala 537:39] + when _T_1483 : @[CSR.scala 560:36] + node _T_2995 = bits(wdata, 5, 5) @[CSR.scala 562:20] + node _T_2996 = not(wdata) @[CSR.scala 563:21] + node _T_2998 = eq(_T_2995, UInt<1>("h00")) @[CSR.scala 563:31] + node _T_2999 = shl(_T_2998, 3) @[CSR.scala 563:34] + node _T_3000 = or(_T_2996, _T_2999) @[CSR.scala 563:28] + node _T_3001 = not(_T_3000) @[CSR.scala 563:19] + node _T_3002 = and(_T_3001, UInt<13>("h0102d")) @[CSR.scala 563:51] + node _T_3003 = not(UInt<13>("h0102d")) @[CSR.scala 563:71] + node _T_3004 = and(reg_misa, _T_3003) @[CSR.scala 563:69] + node _T_3005 = or(_T_3002, _T_3004) @[CSR.scala 563:58] + reg_misa <= _T_3005 @[CSR.scala 563:16] + skip @[CSR.scala 560:36] + when _T_1489 : @[CSR.scala 565:35] + wire _T_3034 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 566:39] + _T_3034 is invalid @[CSR.scala 566:39] + wire _T_3049 : UInt<13> + _T_3049 is invalid + _T_3049 <= wdata + node _T_3050 = bits(_T_3049, 0, 0) @[CSR.scala 566:39] + _T_3034.usip <= _T_3050 @[CSR.scala 566:39] + node _T_3051 = bits(_T_3049, 1, 1) @[CSR.scala 566:39] + _T_3034.ssip <= _T_3051 @[CSR.scala 566:39] + node _T_3052 = bits(_T_3049, 2, 2) @[CSR.scala 566:39] + _T_3034.hsip <= _T_3052 @[CSR.scala 566:39] + node _T_3053 = bits(_T_3049, 3, 3) @[CSR.scala 566:39] + _T_3034.msip <= _T_3053 @[CSR.scala 566:39] + node _T_3054 = bits(_T_3049, 4, 4) @[CSR.scala 566:39] + _T_3034.utip <= _T_3054 @[CSR.scala 566:39] + node _T_3055 = bits(_T_3049, 5, 5) @[CSR.scala 566:39] + _T_3034.stip <= _T_3055 @[CSR.scala 566:39] + node _T_3056 = bits(_T_3049, 6, 6) @[CSR.scala 566:39] + _T_3034.htip <= _T_3056 @[CSR.scala 566:39] + node _T_3057 = bits(_T_3049, 7, 7) @[CSR.scala 566:39] + _T_3034.mtip <= _T_3057 @[CSR.scala 566:39] + node _T_3058 = bits(_T_3049, 8, 8) @[CSR.scala 566:39] + _T_3034.ueip <= _T_3058 @[CSR.scala 566:39] + node _T_3059 = bits(_T_3049, 9, 9) @[CSR.scala 566:39] + _T_3034.seip <= _T_3059 @[CSR.scala 566:39] + node _T_3060 = bits(_T_3049, 10, 10) @[CSR.scala 566:39] + _T_3034.heip <= _T_3060 @[CSR.scala 566:39] + node _T_3061 = bits(_T_3049, 11, 11) @[CSR.scala 566:39] + _T_3034.meip <= _T_3061 @[CSR.scala 566:39] + node _T_3062 = bits(_T_3049, 12, 12) @[CSR.scala 566:39] + _T_3034.rocc <= _T_3062 @[CSR.scala 566:39] + reg_mip.ssip <= _T_3034.ssip @[CSR.scala 568:22] + reg_mip.stip <= _T_3034.stip @[CSR.scala 569:22] + skip @[CSR.scala 565:35] + when _T_1491 : @[CSR.scala 572:40] + node _T_3063 = and(wdata, supported_interrupts) @[CSR.scala 572:59] + reg_mie <= _T_3063 @[CSR.scala 572:50] + skip @[CSR.scala 572:40] + when _T_1499 : @[CSR.scala 573:40] + node _T_3064 = not(wdata) @[CSR.scala 714:28] + node _T_3065 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_3067 = eq(_T_3065, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_3069 = cat(_T_3067, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_3070 = or(_T_3064, _T_3069) @[CSR.scala 714:31] + node _T_3071 = not(_T_3070) @[CSR.scala 714:26] + reg_mepc <= _T_3071 @[CSR.scala 573:51] + skip @[CSR.scala 573:40] + when _T_1497 : @[CSR.scala 574:40] + reg_mscratch <= wdata @[CSR.scala 574:55] + skip @[CSR.scala 574:40] + when _T_1487 : @[CSR.scala 576:40] + node _T_3072 = shr(wdata, 2) @[CSR.scala 576:61] + node _T_3073 = shl(_T_3072, 2) @[CSR.scala 576:66] + reg_mtvec <= _T_3073 @[CSR.scala 576:52] + skip @[CSR.scala 576:40] + when _T_1503 : @[CSR.scala 577:40] + node _T_3075 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 577:62] + reg_mcause <= _T_3075 @[CSR.scala 577:53] + skip @[CSR.scala 577:40] + when _T_1501 : @[CSR.scala 578:40] + node _T_3076 = bits(wdata, 39, 0) @[CSR.scala 578:63] + reg_mbadaddr <= _T_3076 @[CSR.scala 578:55] + skip @[CSR.scala 578:40] + when _T_1479 : @[CSR.scala 711:31] + node _T_3077 = bits(wdata, 63, 0) @[CSR.scala 711:45] + _T_942 <= _T_3077 @[Counters.scala 67:11] + node _T_3078 = shr(_T_3077, 6) @[Counters.scala 68:28] + _T_945 <= _T_3078 @[Counters.scala 68:23] + skip @[CSR.scala 711:31] + when _T_1481 : @[CSR.scala 711:31] + node _T_3079 = bits(wdata, 63, 0) @[CSR.scala 711:45] + _T_931 <= _T_3079 @[Counters.scala 67:11] + node _T_3080 = shr(_T_3079, 6) @[Counters.scala 68:28] + _T_934 <= _T_3080 @[Counters.scala 68:23] + skip @[CSR.scala 711:31] + when _T_1513 : @[CSR.scala 588:40] + reg_fflags <= wdata @[CSR.scala 588:53] + skip @[CSR.scala 588:40] + when _T_1515 : @[CSR.scala 589:40] + reg_frm <= wdata @[CSR.scala 589:50] + skip @[CSR.scala 589:40] + when _T_1517 : @[CSR.scala 590:40] + reg_fflags <= wdata @[CSR.scala 590:53] + node _T_3081 = shr(wdata, 5) @[CSR.scala 590:80] + reg_frm <= _T_3081 @[CSR.scala 590:71] + skip @[CSR.scala 590:40] + when _T_1507 : @[CSR.scala 593:38] + wire _T_3118 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 594:43] + _T_3118 is invalid @[CSR.scala 594:43] + wire _T_3137 : UInt<32> + _T_3137 is invalid + _T_3137 <= wdata + node _T_3138 = bits(_T_3137, 1, 0) @[CSR.scala 594:43] + _T_3118.prv <= _T_3138 @[CSR.scala 594:43] + node _T_3139 = bits(_T_3137, 2, 2) @[CSR.scala 594:43] + _T_3118.step <= _T_3139 @[CSR.scala 594:43] + node _T_3140 = bits(_T_3137, 3, 3) @[CSR.scala 594:43] + _T_3118.halt <= _T_3140 @[CSR.scala 594:43] + node _T_3141 = bits(_T_3137, 4, 4) @[CSR.scala 594:43] + _T_3118.zero1 <= _T_3141 @[CSR.scala 594:43] + node _T_3142 = bits(_T_3137, 5, 5) @[CSR.scala 594:43] + _T_3118.debugint <= _T_3142 @[CSR.scala 594:43] + node _T_3143 = bits(_T_3137, 8, 6) @[CSR.scala 594:43] + _T_3118.cause <= _T_3143 @[CSR.scala 594:43] + node _T_3144 = bits(_T_3137, 9, 9) @[CSR.scala 594:43] + _T_3118.stoptime <= _T_3144 @[CSR.scala 594:43] + node _T_3145 = bits(_T_3137, 10, 10) @[CSR.scala 594:43] + _T_3118.stopcycle <= _T_3145 @[CSR.scala 594:43] + node _T_3146 = bits(_T_3137, 11, 11) @[CSR.scala 594:43] + _T_3118.zero2 <= _T_3146 @[CSR.scala 594:43] + node _T_3147 = bits(_T_3137, 12, 12) @[CSR.scala 594:43] + _T_3118.ebreaku <= _T_3147 @[CSR.scala 594:43] + node _T_3148 = bits(_T_3137, 13, 13) @[CSR.scala 594:43] + _T_3118.ebreaks <= _T_3148 @[CSR.scala 594:43] + node _T_3149 = bits(_T_3137, 14, 14) @[CSR.scala 594:43] + _T_3118.ebreakh <= _T_3149 @[CSR.scala 594:43] + node _T_3150 = bits(_T_3137, 15, 15) @[CSR.scala 594:43] + _T_3118.ebreakm <= _T_3150 @[CSR.scala 594:43] + node _T_3151 = bits(_T_3137, 27, 16) @[CSR.scala 594:43] + _T_3118.zero3 <= _T_3151 @[CSR.scala 594:43] + node _T_3152 = bits(_T_3137, 28, 28) @[CSR.scala 594:43] + _T_3118.fullreset <= _T_3152 @[CSR.scala 594:43] + node _T_3153 = bits(_T_3137, 29, 29) @[CSR.scala 594:43] + _T_3118.ndreset <= _T_3153 @[CSR.scala 594:43] + node _T_3154 = bits(_T_3137, 31, 30) @[CSR.scala 594:43] + _T_3118.xdebugver <= _T_3154 @[CSR.scala 594:43] + reg_dcsr.halt <= _T_3118.halt @[CSR.scala 595:23] + reg_dcsr.step <= _T_3118.step @[CSR.scala 596:23] + reg_dcsr.ebreakm <= _T_3118.ebreakm @[CSR.scala 597:26] + reg_dcsr.ebreaks <= _T_3118.ebreaks @[CSR.scala 598:39] + reg_dcsr.ebreaku <= _T_3118.ebreaku @[CSR.scala 599:41] + reg_dcsr.prv <= _T_3118.prv @[CSR.scala 600:37] + skip @[CSR.scala 593:38] + when _T_1509 : @[CSR.scala 602:42] + node _T_3155 = not(wdata) @[CSR.scala 602:57] + node _T_3157 = or(_T_3155, UInt<1>("h01")) @[CSR.scala 602:64] + node _T_3158 = not(_T_3157) @[CSR.scala 602:55] + reg_dpc <= _T_3158 @[CSR.scala 602:52] + skip @[CSR.scala 602:42] + when _T_1511 : @[CSR.scala 603:42] + reg_dscratch <= wdata @[CSR.scala 603:57] + skip @[CSR.scala 603:42] + when _T_1693 : @[CSR.scala 606:41] + wire _T_3217 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 607:49] + _T_3217 is invalid @[CSR.scala 607:49] + wire _T_3247 : UInt<99> + _T_3247 is invalid + _T_3247 <= wdata + node _T_3248 = bits(_T_3247, 0, 0) @[CSR.scala 607:49] + _T_3217.uie <= _T_3248 @[CSR.scala 607:49] + node _T_3249 = bits(_T_3247, 1, 1) @[CSR.scala 607:49] + _T_3217.sie <= _T_3249 @[CSR.scala 607:49] + node _T_3250 = bits(_T_3247, 2, 2) @[CSR.scala 607:49] + _T_3217.hie <= _T_3250 @[CSR.scala 607:49] + node _T_3251 = bits(_T_3247, 3, 3) @[CSR.scala 607:49] + _T_3217.mie <= _T_3251 @[CSR.scala 607:49] + node _T_3252 = bits(_T_3247, 4, 4) @[CSR.scala 607:49] + _T_3217.upie <= _T_3252 @[CSR.scala 607:49] + node _T_3253 = bits(_T_3247, 5, 5) @[CSR.scala 607:49] + _T_3217.spie <= _T_3253 @[CSR.scala 607:49] + node _T_3254 = bits(_T_3247, 6, 6) @[CSR.scala 607:49] + _T_3217.hpie <= _T_3254 @[CSR.scala 607:49] + node _T_3255 = bits(_T_3247, 7, 7) @[CSR.scala 607:49] + _T_3217.mpie <= _T_3255 @[CSR.scala 607:49] + node _T_3256 = bits(_T_3247, 8, 8) @[CSR.scala 607:49] + _T_3217.spp <= _T_3256 @[CSR.scala 607:49] + node _T_3257 = bits(_T_3247, 10, 9) @[CSR.scala 607:49] + _T_3217.hpp <= _T_3257 @[CSR.scala 607:49] + node _T_3258 = bits(_T_3247, 12, 11) @[CSR.scala 607:49] + _T_3217.mpp <= _T_3258 @[CSR.scala 607:49] + node _T_3259 = bits(_T_3247, 14, 13) @[CSR.scala 607:49] + _T_3217.fs <= _T_3259 @[CSR.scala 607:49] + node _T_3260 = bits(_T_3247, 16, 15) @[CSR.scala 607:49] + _T_3217.xs <= _T_3260 @[CSR.scala 607:49] + node _T_3261 = bits(_T_3247, 17, 17) @[CSR.scala 607:49] + _T_3217.mprv <= _T_3261 @[CSR.scala 607:49] + node _T_3262 = bits(_T_3247, 18, 18) @[CSR.scala 607:49] + _T_3217.pum <= _T_3262 @[CSR.scala 607:49] + node _T_3263 = bits(_T_3247, 19, 19) @[CSR.scala 607:49] + _T_3217.mxr <= _T_3263 @[CSR.scala 607:49] + node _T_3264 = bits(_T_3247, 20, 20) @[CSR.scala 607:49] + _T_3217.tvm <= _T_3264 @[CSR.scala 607:49] + node _T_3265 = bits(_T_3247, 21, 21) @[CSR.scala 607:49] + _T_3217.tw <= _T_3265 @[CSR.scala 607:49] + node _T_3266 = bits(_T_3247, 22, 22) @[CSR.scala 607:49] + _T_3217.tsr <= _T_3266 @[CSR.scala 607:49] + node _T_3267 = bits(_T_3247, 30, 23) @[CSR.scala 607:49] + _T_3217.zero1 <= _T_3267 @[CSR.scala 607:49] + node _T_3268 = bits(_T_3247, 31, 31) @[CSR.scala 607:49] + _T_3217.sd_rv32 <= _T_3268 @[CSR.scala 607:49] + node _T_3269 = bits(_T_3247, 33, 32) @[CSR.scala 607:49] + _T_3217.uxl <= _T_3269 @[CSR.scala 607:49] + node _T_3270 = bits(_T_3247, 35, 34) @[CSR.scala 607:49] + _T_3217.sxl <= _T_3270 @[CSR.scala 607:49] + node _T_3271 = bits(_T_3247, 62, 36) @[CSR.scala 607:49] + _T_3217.zero2 <= _T_3271 @[CSR.scala 607:49] + node _T_3272 = bits(_T_3247, 63, 63) @[CSR.scala 607:49] + _T_3217.sd <= _T_3272 @[CSR.scala 607:49] + node _T_3273 = bits(_T_3247, 65, 64) @[CSR.scala 607:49] + _T_3217.prv <= _T_3273 @[CSR.scala 607:49] + node _T_3274 = bits(_T_3247, 97, 66) @[CSR.scala 607:49] + _T_3217.isa <= _T_3274 @[CSR.scala 607:49] + node _T_3275 = bits(_T_3247, 98, 98) @[CSR.scala 607:49] + _T_3217.debug <= _T_3275 @[CSR.scala 607:49] + reg_mstatus.sie <= _T_3217.sie @[CSR.scala 608:25] + reg_mstatus.spie <= _T_3217.spie @[CSR.scala 609:26] + reg_mstatus.spp <= _T_3217.spp @[CSR.scala 610:25] + reg_mstatus.pum <= _T_3217.pum @[CSR.scala 611:25] + node _T_3277 = neq(_T_3217.fs, UInt<1>("h00")) @[CSR.scala 612:50] + node _T_3278 = bits(_T_3277, 0, 0) @[Bitwise.scala 71:15] + node _T_3281 = mux(_T_3278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12] + reg_mstatus.fs <= _T_3281 @[CSR.scala 612:24] + skip @[CSR.scala 606:41] + when _T_1695 : @[CSR.scala 615:37] + wire _T_3310 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 616:41] + _T_3310 is invalid @[CSR.scala 616:41] + wire _T_3325 : UInt<13> + _T_3325 is invalid + _T_3325 <= wdata + node _T_3326 = bits(_T_3325, 0, 0) @[CSR.scala 616:41] + _T_3310.usip <= _T_3326 @[CSR.scala 616:41] + node _T_3327 = bits(_T_3325, 1, 1) @[CSR.scala 616:41] + _T_3310.ssip <= _T_3327 @[CSR.scala 616:41] + node _T_3328 = bits(_T_3325, 2, 2) @[CSR.scala 616:41] + _T_3310.hsip <= _T_3328 @[CSR.scala 616:41] + node _T_3329 = bits(_T_3325, 3, 3) @[CSR.scala 616:41] + _T_3310.msip <= _T_3329 @[CSR.scala 616:41] + node _T_3330 = bits(_T_3325, 4, 4) @[CSR.scala 616:41] + _T_3310.utip <= _T_3330 @[CSR.scala 616:41] + node _T_3331 = bits(_T_3325, 5, 5) @[CSR.scala 616:41] + _T_3310.stip <= _T_3331 @[CSR.scala 616:41] + node _T_3332 = bits(_T_3325, 6, 6) @[CSR.scala 616:41] + _T_3310.htip <= _T_3332 @[CSR.scala 616:41] + node _T_3333 = bits(_T_3325, 7, 7) @[CSR.scala 616:41] + _T_3310.mtip <= _T_3333 @[CSR.scala 616:41] + node _T_3334 = bits(_T_3325, 8, 8) @[CSR.scala 616:41] + _T_3310.ueip <= _T_3334 @[CSR.scala 616:41] + node _T_3335 = bits(_T_3325, 9, 9) @[CSR.scala 616:41] + _T_3310.seip <= _T_3335 @[CSR.scala 616:41] + node _T_3336 = bits(_T_3325, 10, 10) @[CSR.scala 616:41] + _T_3310.heip <= _T_3336 @[CSR.scala 616:41] + node _T_3337 = bits(_T_3325, 11, 11) @[CSR.scala 616:41] + _T_3310.meip <= _T_3337 @[CSR.scala 616:41] + node _T_3338 = bits(_T_3325, 12, 12) @[CSR.scala 616:41] + _T_3310.rocc <= _T_3338 @[CSR.scala 616:41] + reg_mip.ssip <= _T_3310.ssip @[CSR.scala 617:22] + skip @[CSR.scala 615:37] + when _T_1705 : @[CSR.scala 619:39] + wire _T_3347 : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} @[CSR.scala 620:44] + _T_3347 is invalid @[CSR.scala 620:44] + wire _T_3352 : UInt<64> + _T_3352 is invalid + _T_3352 <= wdata + node _T_3353 = bits(_T_3352, 43, 0) @[CSR.scala 620:44] + _T_3347.ppn <= _T_3353 @[CSR.scala 620:44] + node _T_3354 = bits(_T_3352, 59, 44) @[CSR.scala 620:44] + _T_3347.asid <= _T_3354 @[CSR.scala 620:44] + node _T_3355 = bits(_T_3352, 63, 60) @[CSR.scala 620:44] + _T_3347.mode <= _T_3355 @[CSR.scala 620:44] + node _T_3357 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 622:30] + when _T_3357 : @[CSR.scala 622:37] + reg_sptbr.mode <= UInt<1>("h00") @[CSR.scala 622:54] + skip @[CSR.scala 622:37] + node _T_3360 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 623:30] + when _T_3360 : @[CSR.scala 623:46] + reg_sptbr.mode <= UInt<4>("h08") @[CSR.scala 623:63] + skip @[CSR.scala 623:46] + node _T_3363 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 624:30] + node _T_3365 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 624:54] + node _T_3366 = or(_T_3363, _T_3365) @[CSR.scala 624:36] + when _T_3366 : @[CSR.scala 624:70] + node _T_3367 = bits(_T_3347.ppn, 19, 0) @[CSR.scala 625:41] + reg_sptbr.ppn <= _T_3367 @[CSR.scala 625:25] + skip @[CSR.scala 624:70] + skip @[CSR.scala 619:39] + when _T_1697 : @[CSR.scala 629:42] + node _T_3368 = not(reg_mideleg) @[CSR.scala 629:66] + node _T_3369 = and(reg_mie, _T_3368) @[CSR.scala 629:64] + node _T_3370 = and(wdata, reg_mideleg) @[CSR.scala 629:89] + node _T_3371 = or(_T_3369, _T_3370) @[CSR.scala 629:80] + reg_mie <= _T_3371 @[CSR.scala 629:52] + skip @[CSR.scala 629:42] + when _T_1699 : @[CSR.scala 630:42] + reg_sscratch <= wdata @[CSR.scala 630:57] + skip @[CSR.scala 630:42] + when _T_1707 : @[CSR.scala 631:42] + node _T_3372 = not(wdata) @[CSR.scala 714:28] + node _T_3373 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_3375 = eq(_T_3373, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_3377 = cat(_T_3375, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_3378 = or(_T_3372, _T_3377) @[CSR.scala 714:31] + node _T_3379 = not(_T_3378) @[CSR.scala 714:26] + reg_sepc <= _T_3379 @[CSR.scala 631:53] + skip @[CSR.scala 631:42] + when _T_1709 : @[CSR.scala 632:42] + node _T_3380 = shr(wdata, 2) @[CSR.scala 632:63] + node _T_3381 = shl(_T_3380, 2) @[CSR.scala 632:68] + reg_stvec <= _T_3381 @[CSR.scala 632:54] + skip @[CSR.scala 632:42] + when _T_1701 : @[CSR.scala 633:42] + node _T_3383 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 633:64] + reg_scause <= _T_3383 @[CSR.scala 633:55] + skip @[CSR.scala 633:42] + when _T_1703 : @[CSR.scala 634:42] + node _T_3384 = bits(wdata, 39, 0) @[CSR.scala 634:65] + reg_sbadaddr <= _T_3384 @[CSR.scala 634:57] + skip @[CSR.scala 634:42] + when _T_1493 : @[CSR.scala 635:42] + node _T_3385 = and(wdata, delegable_interrupts) @[CSR.scala 635:65] + reg_mideleg <= _T_3385 @[CSR.scala 635:56] + skip @[CSR.scala 635:42] + when _T_1495 : @[CSR.scala 636:42] + node _T_3386 = and(wdata, UInt<9>("h01ab")) @[CSR.scala 636:65] + reg_medeleg <= _T_3386 @[CSR.scala 636:56] + skip @[CSR.scala 636:42] + when _T_1711 : @[CSR.scala 637:44] + node _T_3388 = and(wdata, UInt<3>("h07")) @[CSR.scala 637:70] + reg_scounteren <= _T_3388 @[CSR.scala 637:61] + skip @[CSR.scala 637:44] + when _T_1713 : @[CSR.scala 640:44] + node _T_3390 = and(wdata, UInt<3>("h07")) @[CSR.scala 640:70] + reg_mcounteren <= _T_3390 @[CSR.scala 640:61] + skip @[CSR.scala 640:44] + when _T_1467 : @[CSR.scala 643:41] + reg_tselect <= wdata @[CSR.scala 643:55] + skip @[CSR.scala 643:41] + node _T_3427 = eq(reg_bp[reg_tselect].control.dmode, UInt<1>("h00")) @[CSR.scala 646:13] + node _T_3428 = or(_T_3427, reg_debug) @[CSR.scala 646:31] + when _T_3428 : @[CSR.scala 646:45] + when _T_1469 : @[CSR.scala 647:42] + wire _T_3461 : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[CSR.scala 648:48] + _T_3461 is invalid @[CSR.scala 648:48] + wire _T_3478 : UInt<64> + _T_3478 is invalid + _T_3478 <= wdata + node _T_3479 = bits(_T_3478, 0, 0) @[CSR.scala 648:48] + _T_3461.r <= _T_3479 @[CSR.scala 648:48] + node _T_3480 = bits(_T_3478, 1, 1) @[CSR.scala 648:48] + _T_3461.w <= _T_3480 @[CSR.scala 648:48] + node _T_3481 = bits(_T_3478, 2, 2) @[CSR.scala 648:48] + _T_3461.x <= _T_3481 @[CSR.scala 648:48] + node _T_3482 = bits(_T_3478, 3, 3) @[CSR.scala 648:48] + _T_3461.u <= _T_3482 @[CSR.scala 648:48] + node _T_3483 = bits(_T_3478, 4, 4) @[CSR.scala 648:48] + _T_3461.s <= _T_3483 @[CSR.scala 648:48] + node _T_3484 = bits(_T_3478, 5, 5) @[CSR.scala 648:48] + _T_3461.h <= _T_3484 @[CSR.scala 648:48] + node _T_3485 = bits(_T_3478, 6, 6) @[CSR.scala 648:48] + _T_3461.m <= _T_3485 @[CSR.scala 648:48] + node _T_3486 = bits(_T_3478, 8, 7) @[CSR.scala 648:48] + _T_3461.tmatch <= _T_3486 @[CSR.scala 648:48] + node _T_3487 = bits(_T_3478, 10, 9) @[CSR.scala 648:48] + _T_3461.zero <= _T_3487 @[CSR.scala 648:48] + node _T_3488 = bits(_T_3478, 11, 11) @[CSR.scala 648:48] + _T_3461.chain <= _T_3488 @[CSR.scala 648:48] + node _T_3489 = bits(_T_3478, 12, 12) @[CSR.scala 648:48] + _T_3461.action <= _T_3489 @[CSR.scala 648:48] + node _T_3490 = bits(_T_3478, 52, 13) @[CSR.scala 648:48] + _T_3461.reserved <= _T_3490 @[CSR.scala 648:48] + node _T_3491 = bits(_T_3478, 58, 53) @[CSR.scala 648:48] + _T_3461.maskmax <= _T_3491 @[CSR.scala 648:48] + node _T_3492 = bits(_T_3478, 59, 59) @[CSR.scala 648:48] + _T_3461.dmode <= _T_3492 @[CSR.scala 648:48] + node _T_3493 = bits(_T_3478, 63, 60) @[CSR.scala 648:48] + _T_3461.ttype <= _T_3493 @[CSR.scala 648:48] + node _T_3494 = and(_T_3461.dmode, reg_debug) @[CSR.scala 649:36] + reg_bp[reg_tselect].control <- _T_3461 @[CSR.scala 650:22] + reg_bp[reg_tselect].control.dmode <= _T_3494 @[CSR.scala 651:28] + node _T_3495 = and(_T_3494, _T_3461.action) @[CSR.scala 652:38] + reg_bp[reg_tselect].control.action <= _T_3495 @[CSR.scala 652:29] + skip @[CSR.scala 647:42] + when _T_1471 : @[CSR.scala 654:42] + reg_bp[reg_tselect].address <= wdata @[CSR.scala 654:55] + skip @[CSR.scala 654:42] + skip @[CSR.scala 646:45] + skip @[CSR.scala 536:49] + reg_mip <- io.interrupts @[CSR.scala 659:11] + reg_dcsr.debugint <= io.interrupts.debug @[CSR.scala 660:21] + reg_sptbr.asid <= UInt<1>("h00") @[CSR.scala 672:18] + reg_tselect <= UInt<1>("h00") @[CSR.scala 673:38] + reg_bp[0].control.chain <= UInt<1>("h00") @[CSR.scala 675:42] + reg_bp[0].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15] + reg_bp[0].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17] + reg_bp[0].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18] + reg_bp[0].control.zero <= UInt<1>("h00") @[CSR.scala 680:14] + reg_bp[0].control.h <= UInt<1>("h00") @[CSR.scala 681:11] + when reset : @[CSR.scala 685:18] + reg_bp[0].control.action <= UInt<1>("h00") @[CSR.scala 686:18] + reg_bp[0].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17] + reg_bp[0].control.r <= UInt<1>("h00") @[CSR.scala 688:13] + reg_bp[0].control.w <= UInt<1>("h00") @[CSR.scala 689:13] + reg_bp[0].control.x <= UInt<1>("h00") @[CSR.scala 690:13] + skip @[CSR.scala 685:18] + reg_bp[1].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15] + reg_bp[1].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17] + reg_bp[1].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18] + reg_bp[1].control.zero <= UInt<1>("h00") @[CSR.scala 680:14] + reg_bp[1].control.h <= UInt<1>("h00") @[CSR.scala 681:11] + when reset : @[CSR.scala 685:18] + reg_bp[1].control.action <= UInt<1>("h00") @[CSR.scala 686:18] + reg_bp[1].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17] + reg_bp[1].control.r <= UInt<1>("h00") @[CSR.scala 688:13] + reg_bp[1].control.w <= UInt<1>("h00") @[CSR.scala 689:13] + reg_bp[1].control.x <= UInt<1>("h00") @[CSR.scala 690:13] + skip @[CSR.scala 685:18] + wire _T_3556 : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>} @[CSR.scala 694:28] + _T_3556 is invalid @[CSR.scala 694:28] + wire _T_3575 : UInt<103> + _T_3575 is invalid + _T_3575 <= UInt<1>("h00") + node _T_3576 = bits(_T_3575, 38, 0) @[CSR.scala 694:28] + _T_3556.address <= _T_3576 @[CSR.scala 694:28] + node _T_3577 = bits(_T_3575, 102, 39) @[CSR.scala 694:28] + wire _T_3579 : UInt<64> + _T_3579 is invalid + _T_3579 <= _T_3577 + node _T_3580 = bits(_T_3579, 0, 0) @[CSR.scala 694:28] + _T_3556.control.r <= _T_3580 @[CSR.scala 694:28] + node _T_3581 = bits(_T_3579, 1, 1) @[CSR.scala 694:28] + _T_3556.control.w <= _T_3581 @[CSR.scala 694:28] + node _T_3582 = bits(_T_3579, 2, 2) @[CSR.scala 694:28] + _T_3556.control.x <= _T_3582 @[CSR.scala 694:28] + node _T_3583 = bits(_T_3579, 3, 3) @[CSR.scala 694:28] + _T_3556.control.u <= _T_3583 @[CSR.scala 694:28] + node _T_3584 = bits(_T_3579, 4, 4) @[CSR.scala 694:28] + _T_3556.control.s <= _T_3584 @[CSR.scala 694:28] + node _T_3585 = bits(_T_3579, 5, 5) @[CSR.scala 694:28] + _T_3556.control.h <= _T_3585 @[CSR.scala 694:28] + node _T_3586 = bits(_T_3579, 6, 6) @[CSR.scala 694:28] + _T_3556.control.m <= _T_3586 @[CSR.scala 694:28] + node _T_3587 = bits(_T_3579, 8, 7) @[CSR.scala 694:28] + _T_3556.control.tmatch <= _T_3587 @[CSR.scala 694:28] + node _T_3588 = bits(_T_3579, 10, 9) @[CSR.scala 694:28] + _T_3556.control.zero <= _T_3588 @[CSR.scala 694:28] + node _T_3589 = bits(_T_3579, 11, 11) @[CSR.scala 694:28] + _T_3556.control.chain <= _T_3589 @[CSR.scala 694:28] + node _T_3590 = bits(_T_3579, 12, 12) @[CSR.scala 694:28] + _T_3556.control.action <= _T_3590 @[CSR.scala 694:28] + node _T_3591 = bits(_T_3579, 52, 13) @[CSR.scala 694:28] + _T_3556.control.reserved <= _T_3591 @[CSR.scala 694:28] + node _T_3592 = bits(_T_3579, 58, 53) @[CSR.scala 694:28] + _T_3556.control.maskmax <= _T_3592 @[CSR.scala 694:28] + node _T_3593 = bits(_T_3579, 59, 59) @[CSR.scala 694:28] + _T_3556.control.dmode <= _T_3593 @[CSR.scala 694:28] + node _T_3594 = bits(_T_3579, 63, 60) @[CSR.scala 694:28] + _T_3556.control.ttype <= _T_3594 @[CSR.scala 694:28] + reg_bp[1] <- _T_3556 @[CSR.scala 694:8] + + module BreakpointUnit : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, count : UInt<2>} - - io is invalid - cmem ram : UInt<5>[2] - reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_26, T_28) - node T_33 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_33) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_39 = and(io.enq.ready, io.enq.valid) - node T_41 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_39, T_41) - node T_43 = and(io.deq.ready, io.deq.valid) - node T_45 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_43, T_45) - when do_enq : - infer mport T_47 = ram[T_26], clk - T_47 <= io.enq.bits - node T_49 = eq(T_26, UInt<1>("h01")) - node T_51 = and(UInt<1>("h00"), T_49) - node T_54 = add(T_26, UInt<1>("h01")) - node T_55 = tail(T_54, 1) - node T_56 = mux(T_51, UInt<1>("h00"), T_55) - T_26 <= T_56 - skip - when do_deq : - node T_58 = eq(T_28, UInt<1>("h01")) - node T_60 = and(UInt<1>("h00"), T_58) - node T_63 = add(T_28, UInt<1>("h01")) - node T_64 = tail(T_63, 1) - node T_65 = mux(T_60, UInt<1>("h00"), T_64) - T_28 <= T_65 - skip - node T_66 = neq(do_enq, do_deq) - when T_66 : - maybe_full <= do_enq - skip - node T_68 = eq(empty, UInt<1>("h00")) - node T_70 = and(UInt<1>("h00"), io.enq.valid) - node T_71 = or(T_68, T_70) - io.deq.valid <= T_71 - node T_73 = eq(full, UInt<1>("h00")) - node T_75 = and(UInt<1>("h00"), io.deq.ready) - node T_76 = or(T_73, T_75) - io.enq.ready <= T_76 - infer mport T_77 = ram[T_28], clk - node T_78 = mux(maybe_flow, io.enq.bits, T_77) - io.deq.bits <= T_78 - node T_79 = sub(T_26, T_28) - node ptr_diff = tail(T_79, 1) - node T_81 = and(maybe_full, ptr_match) - node T_82 = cat(T_81, ptr_diff) - io.count <= T_82 - - module NastiErrorSlave : - input clk : Clock + output io : {flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip pc : UInt<39>, flip ea : UInt<39>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>} + + io is invalid + io is invalid + io.xcpt_if <= UInt<1>("h00") @[Breakpoint.scala 64:14] + io.xcpt_ld <= UInt<1>("h00") @[Breakpoint.scala 65:14] + io.xcpt_st <= UInt<1>("h00") @[Breakpoint.scala 66:14] + io.debug_if <= UInt<1>("h00") @[Breakpoint.scala 67:15] + io.debug_ld <= UInt<1>("h00") @[Breakpoint.scala 68:15] + io.debug_st <= UInt<1>("h00") @[Breakpoint.scala 69:15] + node _T_212 = eq(io.status.debug, UInt<1>("h00")) @[Breakpoint.scala 30:35] + node _T_213 = cat(io.bp[0].control.s, io.bp[0].control.u) @[Cat.scala 30:58] + node _T_214 = cat(io.bp[0].control.m, io.bp[0].control.h) @[Cat.scala 30:58] + node _T_215 = cat(_T_214, _T_213) @[Cat.scala 30:58] + node _T_216 = dshr(_T_215, io.status.prv) @[Breakpoint.scala 30:68] + node _T_217 = bits(_T_216, 0, 0) @[Breakpoint.scala 30:68] + node _T_218 = and(_T_212, _T_217) @[Breakpoint.scala 30:50] + node _T_219 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 73:16] + node _T_220 = and(_T_219, io.bp[0].control.r) @[Breakpoint.scala 73:22] + node _T_221 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_222 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_223 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_224 = xor(_T_222, _T_223) @[Breakpoint.scala 44:20] + node _T_225 = not(io.ea) @[Breakpoint.scala 41:6] + node _T_226 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_227 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_228 = and(_T_226, _T_227) @[Breakpoint.scala 38:73] + node _T_229 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_230 = and(_T_228, _T_229) @[Breakpoint.scala 38:73] + node _T_231 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_232 = and(_T_230, _T_231) @[Breakpoint.scala 38:73] + node _T_233 = cat(_T_228, _T_226) @[Cat.scala 30:58] + node _T_234 = cat(_T_232, _T_230) @[Cat.scala 30:58] + node _T_235 = cat(_T_234, _T_233) @[Cat.scala 30:58] + node _T_236 = or(_T_225, _T_235) @[Breakpoint.scala 41:9] + node _T_237 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_238 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_239 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_240 = and(_T_238, _T_239) @[Breakpoint.scala 38:73] + node _T_241 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_242 = and(_T_240, _T_241) @[Breakpoint.scala 38:73] + node _T_243 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_244 = and(_T_242, _T_243) @[Breakpoint.scala 38:73] + node _T_245 = cat(_T_240, _T_238) @[Cat.scala 30:58] + node _T_246 = cat(_T_244, _T_242) @[Cat.scala 30:58] + node _T_247 = cat(_T_246, _T_245) @[Cat.scala 30:58] + node _T_248 = or(_T_237, _T_247) @[Breakpoint.scala 41:33] + node _T_249 = eq(_T_236, _T_248) @[Breakpoint.scala 41:19] + node _T_250 = mux(_T_221, _T_224, _T_249) @[Breakpoint.scala 47:8] + node _T_251 = and(_T_220, _T_250) @[Breakpoint.scala 73:38] + node _T_252 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 74:16] + node _T_253 = and(_T_252, io.bp[0].control.w) @[Breakpoint.scala 74:22] + node _T_254 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_255 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_256 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_257 = xor(_T_255, _T_256) @[Breakpoint.scala 44:20] + node _T_258 = not(io.ea) @[Breakpoint.scala 41:6] + node _T_259 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_260 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_261 = and(_T_259, _T_260) @[Breakpoint.scala 38:73] + node _T_262 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_263 = and(_T_261, _T_262) @[Breakpoint.scala 38:73] + node _T_264 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_265 = and(_T_263, _T_264) @[Breakpoint.scala 38:73] + node _T_266 = cat(_T_261, _T_259) @[Cat.scala 30:58] + node _T_267 = cat(_T_265, _T_263) @[Cat.scala 30:58] + node _T_268 = cat(_T_267, _T_266) @[Cat.scala 30:58] + node _T_269 = or(_T_258, _T_268) @[Breakpoint.scala 41:9] + node _T_270 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_271 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_272 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_273 = and(_T_271, _T_272) @[Breakpoint.scala 38:73] + node _T_274 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_275 = and(_T_273, _T_274) @[Breakpoint.scala 38:73] + node _T_276 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_277 = and(_T_275, _T_276) @[Breakpoint.scala 38:73] + node _T_278 = cat(_T_273, _T_271) @[Cat.scala 30:58] + node _T_279 = cat(_T_277, _T_275) @[Cat.scala 30:58] + node _T_280 = cat(_T_279, _T_278) @[Cat.scala 30:58] + node _T_281 = or(_T_270, _T_280) @[Breakpoint.scala 41:33] + node _T_282 = eq(_T_269, _T_281) @[Breakpoint.scala 41:19] + node _T_283 = mux(_T_254, _T_257, _T_282) @[Breakpoint.scala 47:8] + node _T_284 = and(_T_253, _T_283) @[Breakpoint.scala 74:38] + node _T_285 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 75:16] + node _T_286 = and(_T_285, io.bp[0].control.x) @[Breakpoint.scala 75:22] + node _T_287 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_288 = geq(io.pc, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_289 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_290 = xor(_T_288, _T_289) @[Breakpoint.scala 44:20] + node _T_291 = not(io.pc) @[Breakpoint.scala 41:6] + node _T_292 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_293 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_294 = and(_T_292, _T_293) @[Breakpoint.scala 38:73] + node _T_295 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_296 = and(_T_294, _T_295) @[Breakpoint.scala 38:73] + node _T_297 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_298 = and(_T_296, _T_297) @[Breakpoint.scala 38:73] + node _T_299 = cat(_T_294, _T_292) @[Cat.scala 30:58] + node _T_300 = cat(_T_298, _T_296) @[Cat.scala 30:58] + node _T_301 = cat(_T_300, _T_299) @[Cat.scala 30:58] + node _T_302 = or(_T_291, _T_301) @[Breakpoint.scala 41:9] + node _T_303 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_304 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_305 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_306 = and(_T_304, _T_305) @[Breakpoint.scala 38:73] + node _T_307 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_308 = and(_T_306, _T_307) @[Breakpoint.scala 38:73] + node _T_309 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_310 = and(_T_308, _T_309) @[Breakpoint.scala 38:73] + node _T_311 = cat(_T_306, _T_304) @[Cat.scala 30:58] + node _T_312 = cat(_T_310, _T_308) @[Cat.scala 30:58] + node _T_313 = cat(_T_312, _T_311) @[Cat.scala 30:58] + node _T_314 = or(_T_303, _T_313) @[Breakpoint.scala 41:33] + node _T_315 = eq(_T_302, _T_314) @[Breakpoint.scala 41:19] + node _T_316 = mux(_T_287, _T_290, _T_315) @[Breakpoint.scala 47:8] + node _T_317 = and(_T_286, _T_316) @[Breakpoint.scala 75:38] + node _T_319 = eq(io.bp[0].control.chain, UInt<1>("h00")) @[Breakpoint.scala 76:15] + node _T_320 = and(_T_319, _T_251) @[Breakpoint.scala 78:15] + when _T_320 : @[Breakpoint.scala 78:21] + node _T_322 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 78:37] + io.xcpt_ld <= _T_322 @[Breakpoint.scala 78:34] + io.debug_ld <= io.bp[0].control.action @[Breakpoint.scala 78:69] + skip @[Breakpoint.scala 78:21] + node _T_323 = and(_T_319, _T_284) @[Breakpoint.scala 79:15] + when _T_323 : @[Breakpoint.scala 79:21] + node _T_325 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 79:37] + io.xcpt_st <= _T_325 @[Breakpoint.scala 79:34] + io.debug_st <= io.bp[0].control.action @[Breakpoint.scala 79:69] + skip @[Breakpoint.scala 79:21] + node _T_326 = and(_T_319, _T_317) @[Breakpoint.scala 80:15] + when _T_326 : @[Breakpoint.scala 80:21] + node _T_328 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 80:37] + io.xcpt_if <= _T_328 @[Breakpoint.scala 80:34] + io.debug_if <= io.bp[0].control.action @[Breakpoint.scala 80:69] + skip @[Breakpoint.scala 80:21] + node _T_329 = or(_T_319, _T_251) @[Breakpoint.scala 82:10] + node _T_330 = or(_T_319, _T_284) @[Breakpoint.scala 82:20] + node _T_331 = or(_T_319, _T_317) @[Breakpoint.scala 82:30] + + module ALU : + input clock : Clock input reset : UInt<1> - input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} + output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} io is invalid - node T_322 = and(io.ar.ready, io.ar.valid) - when T_322 : - node T_324 = eq(reset, UInt<1>("h00")) - when T_324 : - printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr) - skip - skip - node T_325 = and(io.aw.ready, io.aw.valid) - when T_325 : - node T_327 = eq(reset, UInt<1>("h00")) - when T_327 : - printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr) - skip - skip - inst r_queue of Queue_36 - r_queue.io is invalid - r_queue.clk <= clk - r_queue.reset <= reset - r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - node T_346 = eq(responding, UInt<1>("h00")) - node T_347 = and(T_346, r_queue.io.deq.valid) - when T_347 : - responding <= UInt<1>("h01") - beats_left <= r_queue.io.deq.bits.len - skip - node T_349 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_349 - io.r.bits.id <= r_queue.io.deq.bits.id - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<2>("h03") - node T_359 = eq(beats_left, UInt<1>("h00")) - io.r.bits.last <= T_359 - node T_360 = and(io.r.ready, io.r.valid) - node T_361 = and(T_360, io.r.bits.last) - r_queue.io.deq.ready <= T_361 - node T_362 = and(io.r.ready, io.r.valid) - when T_362 : - node T_364 = eq(beats_left, UInt<1>("h00")) - when T_364 : - responding <= UInt<1>("h00") - skip - node T_367 = eq(T_364, UInt<1>("h00")) - when T_367 : - node T_369 = sub(beats_left, UInt<1>("h01")) - node T_370 = tail(T_369, 1) - beats_left <= T_370 - skip - skip - reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - io.w.ready <= draining - node T_373 = and(io.aw.ready, io.aw.valid) - when T_373 : - draining <= UInt<1>("h01") - skip - node T_375 = and(io.w.ready, io.w.valid) - node T_376 = and(T_375, io.w.bits.last) - when T_376 : - draining <= UInt<1>("h00") - skip - inst b_queue of Queue_37 - b_queue.io is invalid - b_queue.clk <= clk - b_queue.reset <= reset - node T_381 = eq(draining, UInt<1>("h00")) - node T_382 = and(io.aw.valid, T_381) - b_queue.io.enq.valid <= T_382 - b_queue.io.enq.bits <= io.aw.bits.id - node T_384 = eq(draining, UInt<1>("h00")) - node T_385 = and(b_queue.io.enq.ready, T_384) - io.aw.ready <= T_385 - node T_387 = eq(draining, UInt<1>("h00")) - node T_388 = and(b_queue.io.deq.valid, T_387) - io.b.valid <= T_388 - io.b.bits.id <= b_queue.io.deq.bits - io.b.bits.resp <= UInt<2>("h03") - node T_391 = eq(draining, UInt<1>("h00")) - node T_392 = and(io.b.ready, T_391) - b_queue.io.deq.ready <= T_392 - - module RRArbiter_38 : - input clk : Clock + io is invalid + node _T_16 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_17 = not(io.in2) @[ALU.scala 61:35] + node in2_inv = mux(_T_16, _T_17, io.in2) @[ALU.scala 61:20] + node in1_xor_in2 = xor(io.in1, in2_inv) @[ALU.scala 62:28] + node _T_18 = add(io.in1, in2_inv) @[ALU.scala 63:26] + node _T_19 = tail(_T_18, 1) @[ALU.scala 63:26] + node _T_20 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_21 = add(_T_19, _T_20) @[ALU.scala 63:36] + node _T_22 = tail(_T_21, 1) @[ALU.scala 63:36] + io.adder_out <= _T_22 @[ALU.scala 63:16] + node _T_23 = bits(io.fn, 0, 0) @[ALU.scala 44:35] + node _T_24 = bits(io.fn, 3, 3) @[ALU.scala 45:30] + node _T_26 = eq(_T_24, UInt<1>("h00")) @[ALU.scala 45:26] + node _T_28 = eq(in1_xor_in2, UInt<1>("h00")) @[ALU.scala 67:35] + node _T_29 = bits(io.in1, 63, 63) @[ALU.scala 68:15] + node _T_30 = bits(io.in2, 63, 63) @[ALU.scala 68:34] + node _T_31 = eq(_T_29, _T_30) @[ALU.scala 68:24] + node _T_32 = bits(io.adder_out, 63, 63) @[ALU.scala 68:56] + node _T_33 = bits(io.fn, 1, 1) @[ALU.scala 43:35] + node _T_34 = bits(io.in2, 63, 63) @[ALU.scala 69:35] + node _T_35 = bits(io.in1, 63, 63) @[ALU.scala 69:51] + node _T_36 = mux(_T_33, _T_34, _T_35) @[ALU.scala 69:8] + node _T_37 = mux(_T_31, _T_32, _T_36) @[ALU.scala 68:8] + node _T_38 = mux(_T_26, _T_28, _T_37) @[ALU.scala 67:8] + node _T_39 = xor(_T_23, _T_38) @[ALU.scala 66:36] + io.cmp_out <= _T_39 @[ALU.scala 66:14] + node _T_40 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_41 = bits(io.in1, 31, 31) @[ALU.scala 76:55] + node _T_42 = and(_T_40, _T_41) @[ALU.scala 76:46] + node _T_43 = bits(_T_42, 0, 0) @[Bitwise.scala 71:15] + node _T_46 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_48 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 77:31] + node _T_49 = bits(io.in1, 63, 32) @[ALU.scala 77:48] + node _T_50 = mux(_T_48, _T_49, _T_46) @[ALU.scala 77:24] + node _T_51 = bits(io.in2, 5, 5) @[ALU.scala 78:29] + node _T_53 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 78:42] + node _T_54 = and(_T_51, _T_53) @[ALU.scala 78:33] + node _T_55 = bits(io.in2, 4, 0) @[ALU.scala 78:60] + node shamt = cat(_T_54, _T_55) @[Cat.scala 30:58] + node _T_56 = bits(io.in1, 31, 0) @[ALU.scala 79:34] + node shin_r = cat(_T_50, _T_56) @[Cat.scala 30:58] + node _T_58 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 81:24] + node _T_60 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 81:44] + node _T_61 = or(_T_58, _T_60) @[ALU.scala 81:35] + node _T_64 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47] + node _T_65 = xor(UInt<64>("h0ffffffffffffffff"), _T_64) @[Bitwise.scala 101:21] + node _T_66 = shr(shin_r, 32) @[Bitwise.scala 102:21] + node _T_67 = and(_T_66, _T_65) @[Bitwise.scala 102:31] + node _T_68 = bits(shin_r, 31, 0) @[Bitwise.scala 102:46] + node _T_69 = shl(_T_68, 32) @[Bitwise.scala 102:65] + node _T_70 = not(_T_65) @[Bitwise.scala 102:77] + node _T_71 = and(_T_69, _T_70) @[Bitwise.scala 102:75] + node _T_72 = or(_T_67, _T_71) @[Bitwise.scala 102:39] + node _T_73 = bits(_T_65, 47, 0) @[Bitwise.scala 101:28] + node _T_74 = shl(_T_73, 16) @[Bitwise.scala 101:47] + node _T_75 = xor(_T_65, _T_74) @[Bitwise.scala 101:21] + node _T_76 = shr(_T_72, 16) @[Bitwise.scala 102:21] + node _T_77 = and(_T_76, _T_75) @[Bitwise.scala 102:31] + node _T_78 = bits(_T_72, 47, 0) @[Bitwise.scala 102:46] + node _T_79 = shl(_T_78, 16) @[Bitwise.scala 102:65] + node _T_80 = not(_T_75) @[Bitwise.scala 102:77] + node _T_81 = and(_T_79, _T_80) @[Bitwise.scala 102:75] + node _T_82 = or(_T_77, _T_81) @[Bitwise.scala 102:39] + node _T_83 = bits(_T_75, 55, 0) @[Bitwise.scala 101:28] + node _T_84 = shl(_T_83, 8) @[Bitwise.scala 101:47] + node _T_85 = xor(_T_75, _T_84) @[Bitwise.scala 101:21] + node _T_86 = shr(_T_82, 8) @[Bitwise.scala 102:21] + node _T_87 = and(_T_86, _T_85) @[Bitwise.scala 102:31] + node _T_88 = bits(_T_82, 55, 0) @[Bitwise.scala 102:46] + node _T_89 = shl(_T_88, 8) @[Bitwise.scala 102:65] + node _T_90 = not(_T_85) @[Bitwise.scala 102:77] + node _T_91 = and(_T_89, _T_90) @[Bitwise.scala 102:75] + node _T_92 = or(_T_87, _T_91) @[Bitwise.scala 102:39] + node _T_93 = bits(_T_85, 59, 0) @[Bitwise.scala 101:28] + node _T_94 = shl(_T_93, 4) @[Bitwise.scala 101:47] + node _T_95 = xor(_T_85, _T_94) @[Bitwise.scala 101:21] + node _T_96 = shr(_T_92, 4) @[Bitwise.scala 102:21] + node _T_97 = and(_T_96, _T_95) @[Bitwise.scala 102:31] + node _T_98 = bits(_T_92, 59, 0) @[Bitwise.scala 102:46] + node _T_99 = shl(_T_98, 4) @[Bitwise.scala 102:65] + node _T_100 = not(_T_95) @[Bitwise.scala 102:77] + node _T_101 = and(_T_99, _T_100) @[Bitwise.scala 102:75] + node _T_102 = or(_T_97, _T_101) @[Bitwise.scala 102:39] + node _T_103 = bits(_T_95, 61, 0) @[Bitwise.scala 101:28] + node _T_104 = shl(_T_103, 2) @[Bitwise.scala 101:47] + node _T_105 = xor(_T_95, _T_104) @[Bitwise.scala 101:21] + node _T_106 = shr(_T_102, 2) @[Bitwise.scala 102:21] + node _T_107 = and(_T_106, _T_105) @[Bitwise.scala 102:31] + node _T_108 = bits(_T_102, 61, 0) @[Bitwise.scala 102:46] + node _T_109 = shl(_T_108, 2) @[Bitwise.scala 102:65] + node _T_110 = not(_T_105) @[Bitwise.scala 102:77] + node _T_111 = and(_T_109, _T_110) @[Bitwise.scala 102:75] + node _T_112 = or(_T_107, _T_111) @[Bitwise.scala 102:39] + node _T_113 = bits(_T_105, 62, 0) @[Bitwise.scala 101:28] + node _T_114 = shl(_T_113, 1) @[Bitwise.scala 101:47] + node _T_115 = xor(_T_105, _T_114) @[Bitwise.scala 101:21] + node _T_116 = shr(_T_112, 1) @[Bitwise.scala 102:21] + node _T_117 = and(_T_116, _T_115) @[Bitwise.scala 102:31] + node _T_118 = bits(_T_112, 62, 0) @[Bitwise.scala 102:46] + node _T_119 = shl(_T_118, 1) @[Bitwise.scala 102:65] + node _T_120 = not(_T_115) @[Bitwise.scala 102:77] + node _T_121 = and(_T_119, _T_120) @[Bitwise.scala 102:75] + node _T_122 = or(_T_117, _T_121) @[Bitwise.scala 102:39] + node shin = mux(_T_61, shin_r, _T_122) @[ALU.scala 81:17] + node _T_123 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_124 = bits(shin, 63, 63) @[ALU.scala 82:41] + node _T_125 = and(_T_123, _T_124) @[ALU.scala 82:35] + node _T_126 = cat(_T_125, shin) @[Cat.scala 30:58] + node _T_127 = asSInt(_T_126) @[ALU.scala 82:57] + node _T_128 = dshr(_T_127, shamt) @[ALU.scala 82:64] + node shout_r = bits(_T_128, 63, 0) @[ALU.scala 82:73] + node _T_131 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47] + node _T_132 = xor(UInt<64>("h0ffffffffffffffff"), _T_131) @[Bitwise.scala 101:21] + node _T_133 = shr(shout_r, 32) @[Bitwise.scala 102:21] + node _T_134 = and(_T_133, _T_132) @[Bitwise.scala 102:31] + node _T_135 = bits(shout_r, 31, 0) @[Bitwise.scala 102:46] + node _T_136 = shl(_T_135, 32) @[Bitwise.scala 102:65] + node _T_137 = not(_T_132) @[Bitwise.scala 102:77] + node _T_138 = and(_T_136, _T_137) @[Bitwise.scala 102:75] + node _T_139 = or(_T_134, _T_138) @[Bitwise.scala 102:39] + node _T_140 = bits(_T_132, 47, 0) @[Bitwise.scala 101:28] + node _T_141 = shl(_T_140, 16) @[Bitwise.scala 101:47] + node _T_142 = xor(_T_132, _T_141) @[Bitwise.scala 101:21] + node _T_143 = shr(_T_139, 16) @[Bitwise.scala 102:21] + node _T_144 = and(_T_143, _T_142) @[Bitwise.scala 102:31] + node _T_145 = bits(_T_139, 47, 0) @[Bitwise.scala 102:46] + node _T_146 = shl(_T_145, 16) @[Bitwise.scala 102:65] + node _T_147 = not(_T_142) @[Bitwise.scala 102:77] + node _T_148 = and(_T_146, _T_147) @[Bitwise.scala 102:75] + node _T_149 = or(_T_144, _T_148) @[Bitwise.scala 102:39] + node _T_150 = bits(_T_142, 55, 0) @[Bitwise.scala 101:28] + node _T_151 = shl(_T_150, 8) @[Bitwise.scala 101:47] + node _T_152 = xor(_T_142, _T_151) @[Bitwise.scala 101:21] + node _T_153 = shr(_T_149, 8) @[Bitwise.scala 102:21] + node _T_154 = and(_T_153, _T_152) @[Bitwise.scala 102:31] + node _T_155 = bits(_T_149, 55, 0) @[Bitwise.scala 102:46] + node _T_156 = shl(_T_155, 8) @[Bitwise.scala 102:65] + node _T_157 = not(_T_152) @[Bitwise.scala 102:77] + node _T_158 = and(_T_156, _T_157) @[Bitwise.scala 102:75] + node _T_159 = or(_T_154, _T_158) @[Bitwise.scala 102:39] + node _T_160 = bits(_T_152, 59, 0) @[Bitwise.scala 101:28] + node _T_161 = shl(_T_160, 4) @[Bitwise.scala 101:47] + node _T_162 = xor(_T_152, _T_161) @[Bitwise.scala 101:21] + node _T_163 = shr(_T_159, 4) @[Bitwise.scala 102:21] + node _T_164 = and(_T_163, _T_162) @[Bitwise.scala 102:31] + node _T_165 = bits(_T_159, 59, 0) @[Bitwise.scala 102:46] + node _T_166 = shl(_T_165, 4) @[Bitwise.scala 102:65] + node _T_167 = not(_T_162) @[Bitwise.scala 102:77] + node _T_168 = and(_T_166, _T_167) @[Bitwise.scala 102:75] + node _T_169 = or(_T_164, _T_168) @[Bitwise.scala 102:39] + node _T_170 = bits(_T_162, 61, 0) @[Bitwise.scala 101:28] + node _T_171 = shl(_T_170, 2) @[Bitwise.scala 101:47] + node _T_172 = xor(_T_162, _T_171) @[Bitwise.scala 101:21] + node _T_173 = shr(_T_169, 2) @[Bitwise.scala 102:21] + node _T_174 = and(_T_173, _T_172) @[Bitwise.scala 102:31] + node _T_175 = bits(_T_169, 61, 0) @[Bitwise.scala 102:46] + node _T_176 = shl(_T_175, 2) @[Bitwise.scala 102:65] + node _T_177 = not(_T_172) @[Bitwise.scala 102:77] + node _T_178 = and(_T_176, _T_177) @[Bitwise.scala 102:75] + node _T_179 = or(_T_174, _T_178) @[Bitwise.scala 102:39] + node _T_180 = bits(_T_172, 62, 0) @[Bitwise.scala 101:28] + node _T_181 = shl(_T_180, 1) @[Bitwise.scala 101:47] + node _T_182 = xor(_T_172, _T_181) @[Bitwise.scala 101:21] + node _T_183 = shr(_T_179, 1) @[Bitwise.scala 102:21] + node _T_184 = and(_T_183, _T_182) @[Bitwise.scala 102:31] + node _T_185 = bits(_T_179, 62, 0) @[Bitwise.scala 102:46] + node _T_186 = shl(_T_185, 1) @[Bitwise.scala 102:65] + node _T_187 = not(_T_182) @[Bitwise.scala 102:77] + node _T_188 = and(_T_186, _T_187) @[Bitwise.scala 102:75] + node shout_l = or(_T_184, _T_188) @[Bitwise.scala 102:39] + node _T_190 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 84:25] + node _T_192 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 84:44] + node _T_193 = or(_T_190, _T_192) @[ALU.scala 84:35] + node _T_195 = mux(_T_193, shout_r, UInt<1>("h00")) @[ALU.scala 84:18] + node _T_197 = eq(io.fn, UInt<1>("h01")) @[ALU.scala 85:25] + node _T_199 = mux(_T_197, shout_l, UInt<1>("h00")) @[ALU.scala 85:18] + node shout = or(_T_195, _T_199) @[ALU.scala 84:74] + node _T_201 = eq(io.fn, UInt<3>("h04")) @[ALU.scala 88:25] + node _T_203 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 88:45] + node _T_204 = or(_T_201, _T_203) @[ALU.scala 88:36] + node _T_206 = mux(_T_204, in1_xor_in2, UInt<1>("h00")) @[ALU.scala 88:18] + node _T_208 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 89:25] + node _T_210 = eq(io.fn, UInt<3>("h07")) @[ALU.scala 89:44] + node _T_211 = or(_T_208, _T_210) @[ALU.scala 89:35] + node _T_212 = and(io.in1, io.in2) @[ALU.scala 89:63] + node _T_214 = mux(_T_211, _T_212, UInt<1>("h00")) @[ALU.scala 89:18] + node logic = or(_T_206, _T_214) @[ALU.scala 88:78] + node _T_216 = eq(io.fn, UInt<2>("h02")) @[ALU.scala 42:30] + node _T_218 = eq(io.fn, UInt<2>("h03")) @[ALU.scala 42:48] + node _T_219 = or(_T_216, _T_218) @[ALU.scala 42:41] + node _T_221 = geq(io.fn, UInt<4>("h0c")) @[ALU.scala 42:66] + node _T_222 = or(_T_219, _T_221) @[ALU.scala 42:59] + node _T_223 = and(_T_222, io.cmp_out) @[ALU.scala 90:35] + node _T_224 = or(_T_223, logic) @[ALU.scala 90:50] + node shift_logic = or(_T_224, shout) @[ALU.scala 90:58] + node _T_226 = eq(io.fn, UInt<1>("h00")) @[ALU.scala 91:23] + node _T_228 = eq(io.fn, UInt<4>("h0a")) @[ALU.scala 91:43] + node _T_229 = or(_T_226, _T_228) @[ALU.scala 91:34] + node out = mux(_T_229, io.adder_out, shift_logic) @[ALU.scala 91:16] + io.out <= out @[ALU.scala 93:10] + node _T_231 = eq(io.dw, UInt<1>("h00")) @[ALU.scala 96:17] + when _T_231 : @[ALU.scala 96:28] + node _T_232 = bits(out, 31, 31) @[ALU.scala 96:56] + node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 71:15] + node _T_236 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_237 = bits(out, 31, 0) @[ALU.scala 96:66] + node _T_238 = cat(_T_236, _T_237) @[Cat.scala 30:58] + io.out <= _T_238 @[ALU.scala 96:37] + skip @[ALU.scala 96:28] + + module MulDiv : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<3>} - - io is invalid - wire T_196 : UInt<3> - T_196 is invalid - io.out.valid <= io.in[T_196].valid - io.out.bits <- io.in[T_196].bits - io.chosen <= T_196 - io.in[T_196].ready <= UInt<1>("h00") - reg T_233 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_234 = gt(UInt<1>("h00"), T_233) - node T_235 = and(io.in[0].valid, T_234) - node T_237 = gt(UInt<1>("h01"), T_233) - node T_238 = and(io.in[1].valid, T_237) - node T_240 = gt(UInt<2>("h02"), T_233) - node T_241 = and(io.in[2].valid, T_240) - node T_243 = gt(UInt<2>("h03"), T_233) - node T_244 = and(io.in[3].valid, T_243) - node T_246 = gt(UInt<3>("h04"), T_233) - node T_247 = and(io.in[4].valid, T_246) - node T_250 = or(UInt<1>("h00"), T_235) - node T_252 = eq(T_250, UInt<1>("h00")) - node T_254 = or(UInt<1>("h00"), T_235) - node T_255 = or(T_254, T_238) - node T_257 = eq(T_255, UInt<1>("h00")) - node T_259 = or(UInt<1>("h00"), T_235) - node T_260 = or(T_259, T_238) - node T_261 = or(T_260, T_241) - node T_263 = eq(T_261, UInt<1>("h00")) - node T_265 = or(UInt<1>("h00"), T_235) - node T_266 = or(T_265, T_238) - node T_267 = or(T_266, T_241) - node T_268 = or(T_267, T_244) - node T_270 = eq(T_268, UInt<1>("h00")) - node T_272 = or(UInt<1>("h00"), T_235) - node T_273 = or(T_272, T_238) - node T_274 = or(T_273, T_241) - node T_275 = or(T_274, T_244) - node T_276 = or(T_275, T_247) - node T_278 = eq(T_276, UInt<1>("h00")) - node T_280 = or(UInt<1>("h00"), T_235) - node T_281 = or(T_280, T_238) - node T_282 = or(T_281, T_241) - node T_283 = or(T_282, T_244) - node T_284 = or(T_283, T_247) - node T_285 = or(T_284, io.in[0].valid) - node T_287 = eq(T_285, UInt<1>("h00")) - node T_289 = or(UInt<1>("h00"), T_235) - node T_290 = or(T_289, T_238) - node T_291 = or(T_290, T_241) - node T_292 = or(T_291, T_244) - node T_293 = or(T_292, T_247) - node T_294 = or(T_293, io.in[0].valid) - node T_295 = or(T_294, io.in[1].valid) - node T_297 = eq(T_295, UInt<1>("h00")) - node T_299 = or(UInt<1>("h00"), T_235) - node T_300 = or(T_299, T_238) - node T_301 = or(T_300, T_241) - node T_302 = or(T_301, T_244) - node T_303 = or(T_302, T_247) - node T_304 = or(T_303, io.in[0].valid) - node T_305 = or(T_304, io.in[1].valid) - node T_306 = or(T_305, io.in[2].valid) - node T_308 = eq(T_306, UInt<1>("h00")) - node T_310 = or(UInt<1>("h00"), T_235) - node T_311 = or(T_310, T_238) - node T_312 = or(T_311, T_241) - node T_313 = or(T_312, T_244) - node T_314 = or(T_313, T_247) - node T_315 = or(T_314, io.in[0].valid) - node T_316 = or(T_315, io.in[1].valid) - node T_317 = or(T_316, io.in[2].valid) - node T_318 = or(T_317, io.in[3].valid) - node T_320 = eq(T_318, UInt<1>("h00")) - node T_322 = gt(UInt<1>("h00"), T_233) - node T_323 = and(UInt<1>("h01"), T_322) - node T_324 = or(T_323, T_278) - node T_326 = gt(UInt<1>("h01"), T_233) - node T_327 = and(T_252, T_326) - node T_328 = or(T_327, T_287) - node T_330 = gt(UInt<2>("h02"), T_233) - node T_331 = and(T_257, T_330) - node T_332 = or(T_331, T_297) - node T_334 = gt(UInt<2>("h03"), T_233) - node T_335 = and(T_263, T_334) - node T_336 = or(T_335, T_308) - node T_338 = gt(UInt<3>("h04"), T_233) - node T_339 = and(T_270, T_338) - node T_340 = or(T_339, T_320) - node T_342 = eq(UInt<3>("h04"), UInt<1>("h00")) - node T_343 = mux(UInt<1>("h00"), T_342, T_324) - node T_344 = and(T_343, io.out.ready) - io.in[0].ready <= T_344 - node T_346 = eq(UInt<3>("h04"), UInt<1>("h01")) - node T_347 = mux(UInt<1>("h00"), T_346, T_328) - node T_348 = and(T_347, io.out.ready) - io.in[1].ready <= T_348 - node T_350 = eq(UInt<3>("h04"), UInt<2>("h02")) - node T_351 = mux(UInt<1>("h00"), T_350, T_332) - node T_352 = and(T_351, io.out.ready) - io.in[2].ready <= T_352 - node T_354 = eq(UInt<3>("h04"), UInt<2>("h03")) - node T_355 = mux(UInt<1>("h00"), T_354, T_336) - node T_356 = and(T_355, io.out.ready) - io.in[3].ready <= T_356 - node T_358 = eq(UInt<3>("h04"), UInt<3>("h04")) - node T_359 = mux(UInt<1>("h00"), T_358, T_340) - node T_360 = and(T_359, io.out.ready) - io.in[4].ready <= T_360 - node T_363 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) - node T_365 = mux(io.in[2].valid, UInt<2>("h02"), T_363) - node T_367 = mux(io.in[1].valid, UInt<1>("h01"), T_365) - node T_369 = mux(io.in[0].valid, UInt<1>("h00"), T_367) - node T_371 = gt(UInt<3>("h04"), T_233) - node T_372 = and(io.in[4].valid, T_371) - node T_374 = mux(T_372, UInt<3>("h04"), T_369) - node T_376 = gt(UInt<2>("h03"), T_233) - node T_377 = and(io.in[3].valid, T_376) - node T_379 = mux(T_377, UInt<2>("h03"), T_374) - node T_381 = gt(UInt<2>("h02"), T_233) - node T_382 = and(io.in[2].valid, T_381) - node T_384 = mux(T_382, UInt<2>("h02"), T_379) - node T_386 = gt(UInt<1>("h01"), T_233) - node T_387 = and(io.in[1].valid, T_386) - node T_389 = mux(T_387, UInt<1>("h01"), T_384) - node T_390 = mux(UInt<1>("h00"), UInt<3>("h04"), T_389) - T_196 <= T_390 - node T_391 = and(io.out.ready, io.out.valid) - when T_391 : - T_233 <= T_196 - skip + output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} - module JunctionsPeekingArbiter : - input clk : Clock + io is invalid + io is invalid + reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Multiplier.scala 45:18] + reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock @[Multiplier.scala 47:16] + reg count : UInt<7>, clock @[Multiplier.scala 48:18] + reg neg_out : UInt<1>, clock @[Multiplier.scala 49:20] + reg isMul : UInt<1>, clock @[Multiplier.scala 50:18] + reg isHi : UInt<1>, clock @[Multiplier.scala 51:17] + reg divisor : UInt<65>, clock @[Multiplier.scala 52:20] + reg remainder : UInt<130>, clock @[Multiplier.scala 53:22] + node _T_79 = and(io.req.bits.fn, UInt<4>("h04")) @[Decode.scala 13:65] + node _T_81 = eq(_T_79, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_83 = and(io.req.bits.fn, UInt<4>("h08")) @[Decode.scala 13:65] + node _T_85 = eq(_T_83, UInt<4>("h08")) @[Decode.scala 13:121] + node _T_87 = or(UInt<1>("h00"), _T_81) @[Decode.scala 14:30] + node _T_88 = or(_T_87, _T_85) @[Decode.scala 14:30] + node _T_90 = and(io.req.bits.fn, UInt<4>("h05")) @[Decode.scala 13:65] + node _T_92 = eq(_T_90, UInt<4>("h01")) @[Decode.scala 13:121] + node _T_94 = and(io.req.bits.fn, UInt<4>("h02")) @[Decode.scala 13:65] + node _T_96 = eq(_T_94, UInt<4>("h02")) @[Decode.scala 13:121] + node _T_98 = or(UInt<1>("h00"), _T_92) @[Decode.scala 14:30] + node _T_99 = or(_T_98, _T_96) @[Decode.scala 14:30] + node _T_100 = or(_T_99, _T_85) @[Decode.scala 14:30] + node _T_102 = and(io.req.bits.fn, UInt<4>("h09")) @[Decode.scala 13:65] + node _T_104 = eq(_T_102, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_106 = and(io.req.bits.fn, UInt<4>("h03")) @[Decode.scala 13:65] + node _T_108 = eq(_T_106, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_111 = or(_T_110, _T_81) @[Decode.scala 14:30] + node _T_112 = or(_T_111, _T_108) @[Decode.scala 14:30] + node _T_114 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_115 = or(_T_114, _T_81) @[Decode.scala 14:30] + node cmdMul = bits(_T_88, 0, 0) @[Multiplier.scala 64:58] + node cmdHi = bits(_T_100, 0, 0) @[Multiplier.scala 64:58] + node lhsSigned = bits(_T_112, 0, 0) @[Multiplier.scala 64:58] + node rhsSigned = bits(_T_115, 0, 0) @[Multiplier.scala 64:58] + node _T_118 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_119 = and(UInt<1>("h01"), _T_118) @[Multiplier.scala 67:52] + node _T_120 = bits(io.req.bits.in1, 31, 31) @[Multiplier.scala 70:38] + node _T_121 = bits(io.req.bits.in1, 63, 63) @[Multiplier.scala 70:48] + node _T_122 = mux(_T_119, _T_120, _T_121) @[Multiplier.scala 70:29] + node lhs_sign = and(lhsSigned, _T_122) @[Multiplier.scala 70:23] + node _T_123 = bits(lhs_sign, 0, 0) @[Bitwise.scala 71:15] + node _T_126 = mux(_T_123, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_127 = bits(io.req.bits.in1, 63, 32) @[Multiplier.scala 71:43] + node _T_128 = mux(_T_119, _T_126, _T_127) @[Multiplier.scala 71:17] + node _T_129 = bits(io.req.bits.in1, 31, 0) @[Multiplier.scala 72:15] + node lhs_in = cat(_T_128, _T_129) @[Cat.scala 30:58] + node _T_132 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_133 = and(UInt<1>("h01"), _T_132) @[Multiplier.scala 67:52] + node _T_134 = bits(io.req.bits.in2, 31, 31) @[Multiplier.scala 70:38] + node _T_135 = bits(io.req.bits.in2, 63, 63) @[Multiplier.scala 70:48] + node _T_136 = mux(_T_133, _T_134, _T_135) @[Multiplier.scala 70:29] + node rhs_sign = and(rhsSigned, _T_136) @[Multiplier.scala 70:23] + node _T_137 = bits(rhs_sign, 0, 0) @[Bitwise.scala 71:15] + node _T_140 = mux(_T_137, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_141 = bits(io.req.bits.in2, 63, 32) @[Multiplier.scala 71:43] + node _T_142 = mux(_T_133, _T_140, _T_141) @[Multiplier.scala 71:17] + node _T_143 = bits(io.req.bits.in2, 31, 0) @[Multiplier.scala 72:15] + node rhs_in = cat(_T_142, _T_143) @[Cat.scala 30:58] + node _T_144 = bits(remainder, 128, 64) @[Multiplier.scala 77:29] + node _T_145 = sub(_T_144, divisor) @[Multiplier.scala 77:37] + node _T_146 = asUInt(_T_145) @[Multiplier.scala 77:37] + node subtractor = tail(_T_146, 1) @[Multiplier.scala 77:37] + node _T_147 = bits(remainder, 63, 0) @[Multiplier.scala 78:37] + node _T_149 = sub(UInt<1>("h00"), _T_147) @[Multiplier.scala 78:27] + node _T_150 = asUInt(_T_149) @[Multiplier.scala 78:27] + node negated_remainder = tail(_T_150, 1) @[Multiplier.scala 78:27] + node _T_151 = eq(state, UInt<3>("h01")) @[Multiplier.scala 80:15] + when _T_151 : @[Multiplier.scala 80:33] + node _T_152 = bits(remainder, 63, 63) @[Multiplier.scala 81:20] + node _T_153 = or(_T_152, isMul) @[Multiplier.scala 81:26] + when _T_153 : @[Multiplier.scala 81:36] + remainder <= negated_remainder @[Multiplier.scala 82:17] + skip @[Multiplier.scala 81:36] + node _T_154 = bits(divisor, 63, 63) @[Multiplier.scala 84:18] + node _T_155 = or(_T_154, isMul) @[Multiplier.scala 84:24] + when _T_155 : @[Multiplier.scala 84:34] + divisor <= subtractor @[Multiplier.scala 85:15] + skip @[Multiplier.scala 84:34] + state <= UInt<3>("h02") @[Multiplier.scala 87:11] + skip @[Multiplier.scala 80:33] + node _T_156 = eq(state, UInt<3>("h04")) @[Multiplier.scala 90:15] + when _T_156 : @[Multiplier.scala 90:33] + remainder <= negated_remainder @[Multiplier.scala 91:15] + state <= UInt<3>("h05") @[Multiplier.scala 92:11] + skip @[Multiplier.scala 90:33] + node _T_157 = eq(state, UInt<3>("h03")) @[Multiplier.scala 94:15] + when _T_157 : @[Multiplier.scala 94:31] + node _T_158 = bits(remainder, 128, 65) @[Multiplier.scala 95:27] + remainder <= _T_158 @[Multiplier.scala 95:15] + node _T_159 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 96:17] + state <= _T_159 @[Multiplier.scala 96:11] + skip @[Multiplier.scala 94:31] + node _T_160 = eq(state, UInt<3>("h02")) @[Multiplier.scala 98:15] + node _T_161 = and(_T_160, isMul) @[Multiplier.scala 98:26] + when _T_161 : @[Multiplier.scala 98:36] + node _T_162 = bits(remainder, 129, 65) @[Multiplier.scala 99:31] + node _T_163 = bits(remainder, 63, 0) @[Multiplier.scala 99:55] + node _T_164 = cat(_T_162, _T_163) @[Cat.scala 30:58] + node _T_165 = bits(_T_164, 63, 0) @[Multiplier.scala 100:24] + node _T_166 = bits(_T_164, 128, 64) @[Multiplier.scala 101:23] + node _T_167 = asSInt(_T_166) @[Multiplier.scala 101:37] + node _T_168 = asSInt(divisor) @[Multiplier.scala 102:26] + node _T_169 = bits(_T_165, 7, 0) @[Multiplier.scala 103:22] + node _T_170 = mul(_T_168, _T_169) @[Multiplier.scala 103:43] + node _T_171 = add(_T_170, _T_167) @[Multiplier.scala 103:52] + node _T_172 = tail(_T_171, 1) @[Multiplier.scala 103:52] + node _T_173 = asSInt(_T_172) @[Multiplier.scala 103:52] + node _T_174 = bits(_T_165, 63, 8) @[Multiplier.scala 104:38] + node _T_175 = asUInt(_T_173) @[Cat.scala 30:58] + node _T_176 = cat(_T_175, _T_174) @[Cat.scala 30:58] + node _T_179 = mul(count, UInt<4>("h08")) @[Multiplier.scala 106:56] + node _T_180 = bits(_T_179, 5, 0) @[Multiplier.scala 106:72] + node _T_181 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_180) @[Multiplier.scala 106:46] + node _T_182 = bits(_T_181, 63, 0) @[Multiplier.scala 106:91] + node _T_185 = neq(count, UInt<3>("h07")) @[Multiplier.scala 107:47] + node _T_186 = and(UInt<1>("h01"), _T_185) @[Multiplier.scala 107:38] + node _T_188 = neq(count, UInt<1>("h00")) @[Multiplier.scala 107:81] + node _T_189 = and(_T_186, _T_188) @[Multiplier.scala 107:72] + node _T_191 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 108:7] + node _T_192 = and(_T_189, _T_191) @[Multiplier.scala 107:87] + node _T_193 = not(_T_182) @[Multiplier.scala 108:26] + node _T_194 = and(_T_165, _T_193) @[Multiplier.scala 108:24] + node _T_196 = eq(_T_194, UInt<1>("h00")) @[Multiplier.scala 108:37] + node _T_197 = and(_T_192, _T_196) @[Multiplier.scala 108:13] + node _T_200 = mul(count, UInt<4>("h08")) @[Multiplier.scala 109:44] + node _T_201 = sub(UInt<7>("h040"), _T_200) @[Multiplier.scala 109:36] + node _T_202 = asUInt(_T_201) @[Multiplier.scala 109:36] + node _T_203 = tail(_T_202, 1) @[Multiplier.scala 109:36] + node _T_204 = bits(_T_203, 5, 0) @[Multiplier.scala 109:60] + node _T_205 = dshr(_T_164, _T_204) @[Multiplier.scala 109:27] + node _T_206 = bits(_T_176, 128, 64) @[Multiplier.scala 110:37] + node _T_207 = mux(_T_197, _T_205, _T_176) @[Multiplier.scala 110:55] + node _T_208 = bits(_T_207, 63, 0) @[Multiplier.scala 110:82] + node _T_209 = cat(_T_206, _T_208) @[Cat.scala 30:58] + node _T_210 = shr(_T_209, 64) @[Multiplier.scala 111:34] + node _T_212 = bits(_T_209, 63, 0) @[Multiplier.scala 111:64] + node _T_213 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_214 = cat(_T_213, _T_212) @[Cat.scala 30:58] + remainder <= _T_214 @[Multiplier.scala 111:15] + node _T_216 = add(count, UInt<1>("h01")) @[Multiplier.scala 113:20] + node _T_217 = tail(_T_216, 1) @[Multiplier.scala 113:20] + count <= _T_217 @[Multiplier.scala 113:11] + node _T_219 = eq(count, UInt<3>("h07")) @[Multiplier.scala 114:25] + node _T_220 = or(_T_197, _T_219) @[Multiplier.scala 114:16] + when _T_220 : @[Multiplier.scala 114:51] + node _T_221 = mux(isHi, UInt<3>("h03"), UInt<3>("h05")) @[Multiplier.scala 115:19] + state <= _T_221 @[Multiplier.scala 115:13] + skip @[Multiplier.scala 114:51] + skip @[Multiplier.scala 98:36] + node _T_222 = eq(state, UInt<3>("h02")) @[Multiplier.scala 118:15] + node _T_224 = eq(isMul, UInt<1>("h00")) @[Multiplier.scala 118:29] + node _T_225 = and(_T_222, _T_224) @[Multiplier.scala 118:26] + when _T_225 : @[Multiplier.scala 118:37] + node _T_226 = bits(subtractor, 64, 64) @[Multiplier.scala 122:28] + node _T_227 = bits(remainder, 127, 64) @[Multiplier.scala 123:24] + node _T_228 = bits(subtractor, 63, 0) @[Multiplier.scala 123:45] + node _T_229 = mux(_T_226, _T_227, _T_228) @[Multiplier.scala 123:14] + node _T_230 = bits(remainder, 63, 0) @[Multiplier.scala 123:58] + node _T_232 = eq(_T_226, UInt<1>("h00")) @[Multiplier.scala 123:67] + node _T_233 = cat(_T_229, _T_230) @[Cat.scala 30:58] + node _T_234 = cat(_T_233, _T_232) @[Cat.scala 30:58] + remainder <= _T_234 @[Multiplier.scala 126:15] + node _T_236 = eq(count, UInt<7>("h040")) @[Multiplier.scala 127:17] + when _T_236 : @[Multiplier.scala 127:38] + node _T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 128:41] + node _T_238 = mux(isHi, UInt<3>("h03"), _T_237) @[Multiplier.scala 128:19] + state <= _T_238 @[Multiplier.scala 128:13] + skip @[Multiplier.scala 127:38] + node _T_240 = add(count, UInt<1>("h01")) @[Multiplier.scala 132:20] + node _T_241 = tail(_T_240, 1) @[Multiplier.scala 132:20] + count <= _T_241 @[Multiplier.scala 132:11] + node _T_243 = eq(count, UInt<1>("h00")) @[Multiplier.scala 134:24] + node _T_244 = bits(subtractor, 64, 64) @[Multiplier.scala 134:44] + node _T_246 = eq(_T_244, UInt<1>("h00")) @[Multiplier.scala 134:33] + node _T_247 = and(_T_243, _T_246) @[Multiplier.scala 134:30] + node _T_248 = bits(divisor, 63, 0) @[Multiplier.scala 136:36] + node _T_249 = bits(_T_248, 63, 32) @[CircuitMath.scala 35:17] + node _T_250 = bits(_T_248, 31, 0) @[CircuitMath.scala 36:17] + node _T_252 = neq(_T_249, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_253 = bits(_T_249, 31, 16) @[CircuitMath.scala 35:17] + node _T_254 = bits(_T_249, 15, 0) @[CircuitMath.scala 36:17] + node _T_256 = neq(_T_253, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_257 = bits(_T_253, 15, 8) @[CircuitMath.scala 35:17] + node _T_258 = bits(_T_253, 7, 0) @[CircuitMath.scala 36:17] + node _T_260 = neq(_T_257, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_261 = bits(_T_257, 7, 4) @[CircuitMath.scala 35:17] + node _T_262 = bits(_T_257, 3, 0) @[CircuitMath.scala 36:17] + node _T_264 = neq(_T_261, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_265 = bits(_T_261, 3, 3) @[CircuitMath.scala 32:12] + node _T_267 = bits(_T_261, 2, 2) @[CircuitMath.scala 32:12] + node _T_269 = bits(_T_261, 1, 1) @[CircuitMath.scala 30:8] + node _T_270 = mux(_T_267, UInt<2>("h02"), _T_269) @[CircuitMath.scala 32:10] + node _T_271 = mux(_T_265, UInt<2>("h03"), _T_270) @[CircuitMath.scala 32:10] + node _T_272 = bits(_T_262, 3, 3) @[CircuitMath.scala 32:12] + node _T_274 = bits(_T_262, 2, 2) @[CircuitMath.scala 32:12] + node _T_276 = bits(_T_262, 1, 1) @[CircuitMath.scala 30:8] + node _T_277 = mux(_T_274, UInt<2>("h02"), _T_276) @[CircuitMath.scala 32:10] + node _T_278 = mux(_T_272, UInt<2>("h03"), _T_277) @[CircuitMath.scala 32:10] + node _T_279 = mux(_T_264, _T_271, _T_278) @[CircuitMath.scala 38:21] + node _T_280 = cat(_T_264, _T_279) @[Cat.scala 30:58] + node _T_281 = bits(_T_258, 7, 4) @[CircuitMath.scala 35:17] + node _T_282 = bits(_T_258, 3, 0) @[CircuitMath.scala 36:17] + node _T_284 = neq(_T_281, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_285 = bits(_T_281, 3, 3) @[CircuitMath.scala 32:12] + node _T_287 = bits(_T_281, 2, 2) @[CircuitMath.scala 32:12] + node _T_289 = bits(_T_281, 1, 1) @[CircuitMath.scala 30:8] + node _T_290 = mux(_T_287, UInt<2>("h02"), _T_289) @[CircuitMath.scala 32:10] + node _T_291 = mux(_T_285, UInt<2>("h03"), _T_290) @[CircuitMath.scala 32:10] + node _T_292 = bits(_T_282, 3, 3) @[CircuitMath.scala 32:12] + node _T_294 = bits(_T_282, 2, 2) @[CircuitMath.scala 32:12] + node _T_296 = bits(_T_282, 1, 1) @[CircuitMath.scala 30:8] + node _T_297 = mux(_T_294, UInt<2>("h02"), _T_296) @[CircuitMath.scala 32:10] + node _T_298 = mux(_T_292, UInt<2>("h03"), _T_297) @[CircuitMath.scala 32:10] + node _T_299 = mux(_T_284, _T_291, _T_298) @[CircuitMath.scala 38:21] + node _T_300 = cat(_T_284, _T_299) @[Cat.scala 30:58] + node _T_301 = mux(_T_260, _T_280, _T_300) @[CircuitMath.scala 38:21] + node _T_302 = cat(_T_260, _T_301) @[Cat.scala 30:58] + node _T_303 = bits(_T_254, 15, 8) @[CircuitMath.scala 35:17] + node _T_304 = bits(_T_254, 7, 0) @[CircuitMath.scala 36:17] + node _T_306 = neq(_T_303, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_307 = bits(_T_303, 7, 4) @[CircuitMath.scala 35:17] + node _T_308 = bits(_T_303, 3, 0) @[CircuitMath.scala 36:17] + node _T_310 = neq(_T_307, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_311 = bits(_T_307, 3, 3) @[CircuitMath.scala 32:12] + node _T_313 = bits(_T_307, 2, 2) @[CircuitMath.scala 32:12] + node _T_315 = bits(_T_307, 1, 1) @[CircuitMath.scala 30:8] + node _T_316 = mux(_T_313, UInt<2>("h02"), _T_315) @[CircuitMath.scala 32:10] + node _T_317 = mux(_T_311, UInt<2>("h03"), _T_316) @[CircuitMath.scala 32:10] + node _T_318 = bits(_T_308, 3, 3) @[CircuitMath.scala 32:12] + node _T_320 = bits(_T_308, 2, 2) @[CircuitMath.scala 32:12] + node _T_322 = bits(_T_308, 1, 1) @[CircuitMath.scala 30:8] + node _T_323 = mux(_T_320, UInt<2>("h02"), _T_322) @[CircuitMath.scala 32:10] + node _T_324 = mux(_T_318, UInt<2>("h03"), _T_323) @[CircuitMath.scala 32:10] + node _T_325 = mux(_T_310, _T_317, _T_324) @[CircuitMath.scala 38:21] + node _T_326 = cat(_T_310, _T_325) @[Cat.scala 30:58] + node _T_327 = bits(_T_304, 7, 4) @[CircuitMath.scala 35:17] + node _T_328 = bits(_T_304, 3, 0) @[CircuitMath.scala 36:17] + node _T_330 = neq(_T_327, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_331 = bits(_T_327, 3, 3) @[CircuitMath.scala 32:12] + node _T_333 = bits(_T_327, 2, 2) @[CircuitMath.scala 32:12] + node _T_335 = bits(_T_327, 1, 1) @[CircuitMath.scala 30:8] + node _T_336 = mux(_T_333, UInt<2>("h02"), _T_335) @[CircuitMath.scala 32:10] + node _T_337 = mux(_T_331, UInt<2>("h03"), _T_336) @[CircuitMath.scala 32:10] + node _T_338 = bits(_T_328, 3, 3) @[CircuitMath.scala 32:12] + node _T_340 = bits(_T_328, 2, 2) @[CircuitMath.scala 32:12] + node _T_342 = bits(_T_328, 1, 1) @[CircuitMath.scala 30:8] + node _T_343 = mux(_T_340, UInt<2>("h02"), _T_342) @[CircuitMath.scala 32:10] + node _T_344 = mux(_T_338, UInt<2>("h03"), _T_343) @[CircuitMath.scala 32:10] + node _T_345 = mux(_T_330, _T_337, _T_344) @[CircuitMath.scala 38:21] + node _T_346 = cat(_T_330, _T_345) @[Cat.scala 30:58] + node _T_347 = mux(_T_306, _T_326, _T_346) @[CircuitMath.scala 38:21] + node _T_348 = cat(_T_306, _T_347) @[Cat.scala 30:58] + node _T_349 = mux(_T_256, _T_302, _T_348) @[CircuitMath.scala 38:21] + node _T_350 = cat(_T_256, _T_349) @[Cat.scala 30:58] + node _T_351 = bits(_T_250, 31, 16) @[CircuitMath.scala 35:17] + node _T_352 = bits(_T_250, 15, 0) @[CircuitMath.scala 36:17] + node _T_354 = neq(_T_351, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_355 = bits(_T_351, 15, 8) @[CircuitMath.scala 35:17] + node _T_356 = bits(_T_351, 7, 0) @[CircuitMath.scala 36:17] + node _T_358 = neq(_T_355, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_359 = bits(_T_355, 7, 4) @[CircuitMath.scala 35:17] + node _T_360 = bits(_T_355, 3, 0) @[CircuitMath.scala 36:17] + node _T_362 = neq(_T_359, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_363 = bits(_T_359, 3, 3) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_359, 2, 2) @[CircuitMath.scala 32:12] + node _T_367 = bits(_T_359, 1, 1) @[CircuitMath.scala 30:8] + node _T_368 = mux(_T_365, UInt<2>("h02"), _T_367) @[CircuitMath.scala 32:10] + node _T_369 = mux(_T_363, UInt<2>("h03"), _T_368) @[CircuitMath.scala 32:10] + node _T_370 = bits(_T_360, 3, 3) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_360, 2, 2) @[CircuitMath.scala 32:12] + node _T_374 = bits(_T_360, 1, 1) @[CircuitMath.scala 30:8] + node _T_375 = mux(_T_372, UInt<2>("h02"), _T_374) @[CircuitMath.scala 32:10] + node _T_376 = mux(_T_370, UInt<2>("h03"), _T_375) @[CircuitMath.scala 32:10] + node _T_377 = mux(_T_362, _T_369, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_362, _T_377) @[Cat.scala 30:58] + node _T_379 = bits(_T_356, 7, 4) @[CircuitMath.scala 35:17] + node _T_380 = bits(_T_356, 3, 0) @[CircuitMath.scala 36:17] + node _T_382 = neq(_T_379, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_383 = bits(_T_379, 3, 3) @[CircuitMath.scala 32:12] + node _T_385 = bits(_T_379, 2, 2) @[CircuitMath.scala 32:12] + node _T_387 = bits(_T_379, 1, 1) @[CircuitMath.scala 30:8] + node _T_388 = mux(_T_385, UInt<2>("h02"), _T_387) @[CircuitMath.scala 32:10] + node _T_389 = mux(_T_383, UInt<2>("h03"), _T_388) @[CircuitMath.scala 32:10] + node _T_390 = bits(_T_380, 3, 3) @[CircuitMath.scala 32:12] + node _T_392 = bits(_T_380, 2, 2) @[CircuitMath.scala 32:12] + node _T_394 = bits(_T_380, 1, 1) @[CircuitMath.scala 30:8] + node _T_395 = mux(_T_392, UInt<2>("h02"), _T_394) @[CircuitMath.scala 32:10] + node _T_396 = mux(_T_390, UInt<2>("h03"), _T_395) @[CircuitMath.scala 32:10] + node _T_397 = mux(_T_382, _T_389, _T_396) @[CircuitMath.scala 38:21] + node _T_398 = cat(_T_382, _T_397) @[Cat.scala 30:58] + node _T_399 = mux(_T_358, _T_378, _T_398) @[CircuitMath.scala 38:21] + node _T_400 = cat(_T_358, _T_399) @[Cat.scala 30:58] + node _T_401 = bits(_T_352, 15, 8) @[CircuitMath.scala 35:17] + node _T_402 = bits(_T_352, 7, 0) @[CircuitMath.scala 36:17] + node _T_404 = neq(_T_401, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_405 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17] + node _T_406 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17] + node _T_408 = neq(_T_405, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_409 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12] + node _T_411 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12] + node _T_413 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8] + node _T_414 = mux(_T_411, UInt<2>("h02"), _T_413) @[CircuitMath.scala 32:10] + node _T_415 = mux(_T_409, UInt<2>("h03"), _T_414) @[CircuitMath.scala 32:10] + node _T_416 = bits(_T_406, 3, 3) @[CircuitMath.scala 32:12] + node _T_418 = bits(_T_406, 2, 2) @[CircuitMath.scala 32:12] + node _T_420 = bits(_T_406, 1, 1) @[CircuitMath.scala 30:8] + node _T_421 = mux(_T_418, UInt<2>("h02"), _T_420) @[CircuitMath.scala 32:10] + node _T_422 = mux(_T_416, UInt<2>("h03"), _T_421) @[CircuitMath.scala 32:10] + node _T_423 = mux(_T_408, _T_415, _T_422) @[CircuitMath.scala 38:21] + node _T_424 = cat(_T_408, _T_423) @[Cat.scala 30:58] + node _T_425 = bits(_T_402, 7, 4) @[CircuitMath.scala 35:17] + node _T_426 = bits(_T_402, 3, 0) @[CircuitMath.scala 36:17] + node _T_428 = neq(_T_425, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_429 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12] + node _T_431 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12] + node _T_433 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8] + node _T_434 = mux(_T_431, UInt<2>("h02"), _T_433) @[CircuitMath.scala 32:10] + node _T_435 = mux(_T_429, UInt<2>("h03"), _T_434) @[CircuitMath.scala 32:10] + node _T_436 = bits(_T_426, 3, 3) @[CircuitMath.scala 32:12] + node _T_438 = bits(_T_426, 2, 2) @[CircuitMath.scala 32:12] + node _T_440 = bits(_T_426, 1, 1) @[CircuitMath.scala 30:8] + node _T_441 = mux(_T_438, UInt<2>("h02"), _T_440) @[CircuitMath.scala 32:10] + node _T_442 = mux(_T_436, UInt<2>("h03"), _T_441) @[CircuitMath.scala 32:10] + node _T_443 = mux(_T_428, _T_435, _T_442) @[CircuitMath.scala 38:21] + node _T_444 = cat(_T_428, _T_443) @[Cat.scala 30:58] + node _T_445 = mux(_T_404, _T_424, _T_444) @[CircuitMath.scala 38:21] + node _T_446 = cat(_T_404, _T_445) @[Cat.scala 30:58] + node _T_447 = mux(_T_354, _T_400, _T_446) @[CircuitMath.scala 38:21] + node _T_448 = cat(_T_354, _T_447) @[Cat.scala 30:58] + node _T_449 = mux(_T_252, _T_350, _T_448) @[CircuitMath.scala 38:21] + node _T_450 = cat(_T_252, _T_449) @[Cat.scala 30:58] + node _T_451 = bits(remainder, 63, 0) @[Multiplier.scala 137:39] + node _T_452 = bits(_T_451, 63, 32) @[CircuitMath.scala 35:17] + node _T_453 = bits(_T_451, 31, 0) @[CircuitMath.scala 36:17] + node _T_455 = neq(_T_452, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_456 = bits(_T_452, 31, 16) @[CircuitMath.scala 35:17] + node _T_457 = bits(_T_452, 15, 0) @[CircuitMath.scala 36:17] + node _T_459 = neq(_T_456, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_460 = bits(_T_456, 15, 8) @[CircuitMath.scala 35:17] + node _T_461 = bits(_T_456, 7, 0) @[CircuitMath.scala 36:17] + node _T_463 = neq(_T_460, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_464 = bits(_T_460, 7, 4) @[CircuitMath.scala 35:17] + node _T_465 = bits(_T_460, 3, 0) @[CircuitMath.scala 36:17] + node _T_467 = neq(_T_464, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_468 = bits(_T_464, 3, 3) @[CircuitMath.scala 32:12] + node _T_470 = bits(_T_464, 2, 2) @[CircuitMath.scala 32:12] + node _T_472 = bits(_T_464, 1, 1) @[CircuitMath.scala 30:8] + node _T_473 = mux(_T_470, UInt<2>("h02"), _T_472) @[CircuitMath.scala 32:10] + node _T_474 = mux(_T_468, UInt<2>("h03"), _T_473) @[CircuitMath.scala 32:10] + node _T_475 = bits(_T_465, 3, 3) @[CircuitMath.scala 32:12] + node _T_477 = bits(_T_465, 2, 2) @[CircuitMath.scala 32:12] + node _T_479 = bits(_T_465, 1, 1) @[CircuitMath.scala 30:8] + node _T_480 = mux(_T_477, UInt<2>("h02"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = mux(_T_475, UInt<2>("h03"), _T_480) @[CircuitMath.scala 32:10] + node _T_482 = mux(_T_467, _T_474, _T_481) @[CircuitMath.scala 38:21] + node _T_483 = cat(_T_467, _T_482) @[Cat.scala 30:58] + node _T_484 = bits(_T_461, 7, 4) @[CircuitMath.scala 35:17] + node _T_485 = bits(_T_461, 3, 0) @[CircuitMath.scala 36:17] + node _T_487 = neq(_T_484, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_488 = bits(_T_484, 3, 3) @[CircuitMath.scala 32:12] + node _T_490 = bits(_T_484, 2, 2) @[CircuitMath.scala 32:12] + node _T_492 = bits(_T_484, 1, 1) @[CircuitMath.scala 30:8] + node _T_493 = mux(_T_490, UInt<2>("h02"), _T_492) @[CircuitMath.scala 32:10] + node _T_494 = mux(_T_488, UInt<2>("h03"), _T_493) @[CircuitMath.scala 32:10] + node _T_495 = bits(_T_485, 3, 3) @[CircuitMath.scala 32:12] + node _T_497 = bits(_T_485, 2, 2) @[CircuitMath.scala 32:12] + node _T_499 = bits(_T_485, 1, 1) @[CircuitMath.scala 30:8] + node _T_500 = mux(_T_497, UInt<2>("h02"), _T_499) @[CircuitMath.scala 32:10] + node _T_501 = mux(_T_495, UInt<2>("h03"), _T_500) @[CircuitMath.scala 32:10] + node _T_502 = mux(_T_487, _T_494, _T_501) @[CircuitMath.scala 38:21] + node _T_503 = cat(_T_487, _T_502) @[Cat.scala 30:58] + node _T_504 = mux(_T_463, _T_483, _T_503) @[CircuitMath.scala 38:21] + node _T_505 = cat(_T_463, _T_504) @[Cat.scala 30:58] + node _T_506 = bits(_T_457, 15, 8) @[CircuitMath.scala 35:17] + node _T_507 = bits(_T_457, 7, 0) @[CircuitMath.scala 36:17] + node _T_509 = neq(_T_506, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_510 = bits(_T_506, 7, 4) @[CircuitMath.scala 35:17] + node _T_511 = bits(_T_506, 3, 0) @[CircuitMath.scala 36:17] + node _T_513 = neq(_T_510, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_514 = bits(_T_510, 3, 3) @[CircuitMath.scala 32:12] + node _T_516 = bits(_T_510, 2, 2) @[CircuitMath.scala 32:12] + node _T_518 = bits(_T_510, 1, 1) @[CircuitMath.scala 30:8] + node _T_519 = mux(_T_516, UInt<2>("h02"), _T_518) @[CircuitMath.scala 32:10] + node _T_520 = mux(_T_514, UInt<2>("h03"), _T_519) @[CircuitMath.scala 32:10] + node _T_521 = bits(_T_511, 3, 3) @[CircuitMath.scala 32:12] + node _T_523 = bits(_T_511, 2, 2) @[CircuitMath.scala 32:12] + node _T_525 = bits(_T_511, 1, 1) @[CircuitMath.scala 30:8] + node _T_526 = mux(_T_523, UInt<2>("h02"), _T_525) @[CircuitMath.scala 32:10] + node _T_527 = mux(_T_521, UInt<2>("h03"), _T_526) @[CircuitMath.scala 32:10] + node _T_528 = mux(_T_513, _T_520, _T_527) @[CircuitMath.scala 38:21] + node _T_529 = cat(_T_513, _T_528) @[Cat.scala 30:58] + node _T_530 = bits(_T_507, 7, 4) @[CircuitMath.scala 35:17] + node _T_531 = bits(_T_507, 3, 0) @[CircuitMath.scala 36:17] + node _T_533 = neq(_T_530, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_534 = bits(_T_530, 3, 3) @[CircuitMath.scala 32:12] + node _T_536 = bits(_T_530, 2, 2) @[CircuitMath.scala 32:12] + node _T_538 = bits(_T_530, 1, 1) @[CircuitMath.scala 30:8] + node _T_539 = mux(_T_536, UInt<2>("h02"), _T_538) @[CircuitMath.scala 32:10] + node _T_540 = mux(_T_534, UInt<2>("h03"), _T_539) @[CircuitMath.scala 32:10] + node _T_541 = bits(_T_531, 3, 3) @[CircuitMath.scala 32:12] + node _T_543 = bits(_T_531, 2, 2) @[CircuitMath.scala 32:12] + node _T_545 = bits(_T_531, 1, 1) @[CircuitMath.scala 30:8] + node _T_546 = mux(_T_543, UInt<2>("h02"), _T_545) @[CircuitMath.scala 32:10] + node _T_547 = mux(_T_541, UInt<2>("h03"), _T_546) @[CircuitMath.scala 32:10] + node _T_548 = mux(_T_533, _T_540, _T_547) @[CircuitMath.scala 38:21] + node _T_549 = cat(_T_533, _T_548) @[Cat.scala 30:58] + node _T_550 = mux(_T_509, _T_529, _T_549) @[CircuitMath.scala 38:21] + node _T_551 = cat(_T_509, _T_550) @[Cat.scala 30:58] + node _T_552 = mux(_T_459, _T_505, _T_551) @[CircuitMath.scala 38:21] + node _T_553 = cat(_T_459, _T_552) @[Cat.scala 30:58] + node _T_554 = bits(_T_453, 31, 16) @[CircuitMath.scala 35:17] + node _T_555 = bits(_T_453, 15, 0) @[CircuitMath.scala 36:17] + node _T_557 = neq(_T_554, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_558 = bits(_T_554, 15, 8) @[CircuitMath.scala 35:17] + node _T_559 = bits(_T_554, 7, 0) @[CircuitMath.scala 36:17] + node _T_561 = neq(_T_558, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_562 = bits(_T_558, 7, 4) @[CircuitMath.scala 35:17] + node _T_563 = bits(_T_558, 3, 0) @[CircuitMath.scala 36:17] + node _T_565 = neq(_T_562, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_566 = bits(_T_562, 3, 3) @[CircuitMath.scala 32:12] + node _T_568 = bits(_T_562, 2, 2) @[CircuitMath.scala 32:12] + node _T_570 = bits(_T_562, 1, 1) @[CircuitMath.scala 30:8] + node _T_571 = mux(_T_568, UInt<2>("h02"), _T_570) @[CircuitMath.scala 32:10] + node _T_572 = mux(_T_566, UInt<2>("h03"), _T_571) @[CircuitMath.scala 32:10] + node _T_573 = bits(_T_563, 3, 3) @[CircuitMath.scala 32:12] + node _T_575 = bits(_T_563, 2, 2) @[CircuitMath.scala 32:12] + node _T_577 = bits(_T_563, 1, 1) @[CircuitMath.scala 30:8] + node _T_578 = mux(_T_575, UInt<2>("h02"), _T_577) @[CircuitMath.scala 32:10] + node _T_579 = mux(_T_573, UInt<2>("h03"), _T_578) @[CircuitMath.scala 32:10] + node _T_580 = mux(_T_565, _T_572, _T_579) @[CircuitMath.scala 38:21] + node _T_581 = cat(_T_565, _T_580) @[Cat.scala 30:58] + node _T_582 = bits(_T_559, 7, 4) @[CircuitMath.scala 35:17] + node _T_583 = bits(_T_559, 3, 0) @[CircuitMath.scala 36:17] + node _T_585 = neq(_T_582, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_586 = bits(_T_582, 3, 3) @[CircuitMath.scala 32:12] + node _T_588 = bits(_T_582, 2, 2) @[CircuitMath.scala 32:12] + node _T_590 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_591 = mux(_T_588, UInt<2>("h02"), _T_590) @[CircuitMath.scala 32:10] + node _T_592 = mux(_T_586, UInt<2>("h03"), _T_591) @[CircuitMath.scala 32:10] + node _T_593 = bits(_T_583, 3, 3) @[CircuitMath.scala 32:12] + node _T_595 = bits(_T_583, 2, 2) @[CircuitMath.scala 32:12] + node _T_597 = bits(_T_583, 1, 1) @[CircuitMath.scala 30:8] + node _T_598 = mux(_T_595, UInt<2>("h02"), _T_597) @[CircuitMath.scala 32:10] + node _T_599 = mux(_T_593, UInt<2>("h03"), _T_598) @[CircuitMath.scala 32:10] + node _T_600 = mux(_T_585, _T_592, _T_599) @[CircuitMath.scala 38:21] + node _T_601 = cat(_T_585, _T_600) @[Cat.scala 30:58] + node _T_602 = mux(_T_561, _T_581, _T_601) @[CircuitMath.scala 38:21] + node _T_603 = cat(_T_561, _T_602) @[Cat.scala 30:58] + node _T_604 = bits(_T_555, 15, 8) @[CircuitMath.scala 35:17] + node _T_605 = bits(_T_555, 7, 0) @[CircuitMath.scala 36:17] + node _T_607 = neq(_T_604, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_608 = bits(_T_604, 7, 4) @[CircuitMath.scala 35:17] + node _T_609 = bits(_T_604, 3, 0) @[CircuitMath.scala 36:17] + node _T_611 = neq(_T_608, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_612 = bits(_T_608, 3, 3) @[CircuitMath.scala 32:12] + node _T_614 = bits(_T_608, 2, 2) @[CircuitMath.scala 32:12] + node _T_616 = bits(_T_608, 1, 1) @[CircuitMath.scala 30:8] + node _T_617 = mux(_T_614, UInt<2>("h02"), _T_616) @[CircuitMath.scala 32:10] + node _T_618 = mux(_T_612, UInt<2>("h03"), _T_617) @[CircuitMath.scala 32:10] + node _T_619 = bits(_T_609, 3, 3) @[CircuitMath.scala 32:12] + node _T_621 = bits(_T_609, 2, 2) @[CircuitMath.scala 32:12] + node _T_623 = bits(_T_609, 1, 1) @[CircuitMath.scala 30:8] + node _T_624 = mux(_T_621, UInt<2>("h02"), _T_623) @[CircuitMath.scala 32:10] + node _T_625 = mux(_T_619, UInt<2>("h03"), _T_624) @[CircuitMath.scala 32:10] + node _T_626 = mux(_T_611, _T_618, _T_625) @[CircuitMath.scala 38:21] + node _T_627 = cat(_T_611, _T_626) @[Cat.scala 30:58] + node _T_628 = bits(_T_605, 7, 4) @[CircuitMath.scala 35:17] + node _T_629 = bits(_T_605, 3, 0) @[CircuitMath.scala 36:17] + node _T_631 = neq(_T_628, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_632 = bits(_T_628, 3, 3) @[CircuitMath.scala 32:12] + node _T_634 = bits(_T_628, 2, 2) @[CircuitMath.scala 32:12] + node _T_636 = bits(_T_628, 1, 1) @[CircuitMath.scala 30:8] + node _T_637 = mux(_T_634, UInt<2>("h02"), _T_636) @[CircuitMath.scala 32:10] + node _T_638 = mux(_T_632, UInt<2>("h03"), _T_637) @[CircuitMath.scala 32:10] + node _T_639 = bits(_T_629, 3, 3) @[CircuitMath.scala 32:12] + node _T_641 = bits(_T_629, 2, 2) @[CircuitMath.scala 32:12] + node _T_643 = bits(_T_629, 1, 1) @[CircuitMath.scala 30:8] + node _T_644 = mux(_T_641, UInt<2>("h02"), _T_643) @[CircuitMath.scala 32:10] + node _T_645 = mux(_T_639, UInt<2>("h03"), _T_644) @[CircuitMath.scala 32:10] + node _T_646 = mux(_T_631, _T_638, _T_645) @[CircuitMath.scala 38:21] + node _T_647 = cat(_T_631, _T_646) @[Cat.scala 30:58] + node _T_648 = mux(_T_607, _T_627, _T_647) @[CircuitMath.scala 38:21] + node _T_649 = cat(_T_607, _T_648) @[Cat.scala 30:58] + node _T_650 = mux(_T_557, _T_603, _T_649) @[CircuitMath.scala 38:21] + node _T_651 = cat(_T_557, _T_650) @[Cat.scala 30:58] + node _T_652 = mux(_T_455, _T_553, _T_651) @[CircuitMath.scala 38:21] + node _T_653 = cat(_T_455, _T_652) @[Cat.scala 30:58] + node _T_655 = add(UInt<6>("h03f"), _T_450) @[Multiplier.scala 138:31] + node _T_656 = tail(_T_655, 1) @[Multiplier.scala 138:31] + node _T_657 = sub(_T_656, _T_653) @[Multiplier.scala 138:44] + node _T_658 = asUInt(_T_657) @[Multiplier.scala 138:44] + node _T_659 = tail(_T_658, 1) @[Multiplier.scala 138:44] + node _T_660 = gt(_T_450, _T_653) @[Multiplier.scala 139:33] + node _T_662 = eq(count, UInt<1>("h00")) @[Multiplier.scala 140:24] + node _T_664 = eq(_T_247, UInt<1>("h00")) @[Multiplier.scala 140:33] + node _T_665 = and(_T_662, _T_664) @[Multiplier.scala 140:30] + node _T_667 = geq(_T_659, UInt<1>("h01")) @[Multiplier.scala 140:53] + node _T_668 = or(_T_667, _T_660) @[Multiplier.scala 140:70] + node _T_669 = and(_T_665, _T_668) @[Multiplier.scala 140:41] + when _T_669 : @[Multiplier.scala 141:19] + node _T_671 = mux(_T_660, UInt<6>("h03f"), _T_659) @[Multiplier.scala 142:22] + node _T_672 = shr(_T_671, 0) @[Multiplier.scala 142:53] + node _T_673 = shl(_T_672, 0) @[Multiplier.scala 143:25] + node _T_674 = bits(remainder, 63, 0) @[Multiplier.scala 144:31] + node _T_675 = dshl(_T_674, _T_673) @[Multiplier.scala 144:39] + remainder <= _T_675 @[Multiplier.scala 144:19] + count <= _T_672 @[Multiplier.scala 145:15] + skip @[Multiplier.scala 141:19] + node _T_677 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 148:21] + node _T_678 = and(_T_247, _T_677) @[Multiplier.scala 148:18] + when _T_678 : @[Multiplier.scala 148:28] + neg_out <= UInt<1>("h00") @[Multiplier.scala 148:38] + skip @[Multiplier.scala 148:28] + skip @[Multiplier.scala 118:37] + node _T_680 = and(io.resp.ready, io.resp.valid) @[Decoupled.scala 30:37] + node _T_681 = or(_T_680, io.kill) @[Multiplier.scala 150:24] + when _T_681 : @[Multiplier.scala 150:36] + state <= UInt<3>("h00") @[Multiplier.scala 151:11] + skip @[Multiplier.scala 150:36] + node _T_682 = and(io.req.ready, io.req.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Multiplier.scala 153:24] + node _T_684 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 154:42] + node _T_685 = and(rhs_sign, _T_684) @[Multiplier.scala 154:39] + node _T_686 = or(lhs_sign, _T_685) @[Multiplier.scala 154:27] + node _T_687 = mux(_T_686, UInt<3>("h01"), UInt<3>("h02")) @[Multiplier.scala 154:17] + state <= _T_687 @[Multiplier.scala 154:11] + isMul <= cmdMul @[Multiplier.scala 155:11] + isHi <= cmdHi @[Multiplier.scala 156:10] + count <= UInt<1>("h00") @[Multiplier.scala 157:11] + node _T_690 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 158:16] + node _T_691 = neq(lhs_sign, rhs_sign) @[Multiplier.scala 158:57] + node _T_692 = mux(cmdHi, lhs_sign, _T_691) @[Multiplier.scala 158:30] + node _T_693 = and(_T_690, _T_692) @[Multiplier.scala 158:24] + neg_out <= _T_693 @[Multiplier.scala 158:13] + node _T_694 = cat(rhs_sign, rhs_in) @[Cat.scala 30:58] + divisor <= _T_694 @[Multiplier.scala 159:13] + remainder <= lhs_in @[Multiplier.scala 160:15] + req <- io.req.bits @[Multiplier.scala 161:9] + skip @[Multiplier.scala 153:24] + io.resp.bits <- req @[Multiplier.scala 164:16] + node _T_697 = eq(req.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_698 = and(UInt<1>("h01"), _T_697) @[Multiplier.scala 67:52] + node _T_699 = bits(remainder, 31, 31) @[Multiplier.scala 165:67] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 71:15] + node _T_703 = mux(_T_700, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_704 = bits(remainder, 31, 0) @[Multiplier.scala 165:86] + node _T_705 = cat(_T_703, _T_704) @[Cat.scala 30:58] + node _T_706 = bits(remainder, 63, 0) @[Multiplier.scala 165:107] + node _T_707 = mux(_T_698, _T_705, _T_706) @[Multiplier.scala 165:27] + io.resp.bits.data <= _T_707 @[Multiplier.scala 165:21] + node _T_708 = eq(state, UInt<3>("h05")) @[Multiplier.scala 166:26] + io.resp.valid <= _T_708 @[Multiplier.scala 166:17] + node _T_709 = eq(state, UInt<3>("h00")) @[Multiplier.scala 167:25] + io.req.ready <= _T_709 @[Multiplier.scala 167:16] + + module Rocket : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - - io is invalid - reg T_273 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_275 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_277 : UInt<1>[5] - T_277[0] <= io.in[0].valid - T_277[1] <= io.in[1].valid - T_277[2] <= io.in[2].valid - T_277[3] <= io.in[3].valid - T_277[4] <= io.in[4].valid - node T_285 = add(T_273, UInt<1>("h01")) - node T_286 = tail(T_285, 1) - node T_288 = lt(T_286, UInt<3>("h05")) - node T_290 = add(UInt<1>("h00"), T_286) - node T_291 = tail(T_290, 1) - node T_294 = sub(T_286, UInt<3>("h05")) - node T_295 = tail(T_294, 1) - node T_297 = mux(T_288, T_277[T_291], T_277[T_295]) - node T_299 = lt(T_286, UInt<3>("h04")) - node T_301 = add(UInt<1>("h01"), T_286) - node T_302 = tail(T_301, 1) - node T_305 = sub(T_286, UInt<3>("h04")) - node T_306 = tail(T_305, 1) - node T_308 = mux(T_299, T_277[T_302], T_277[T_306]) - node T_310 = lt(T_286, UInt<2>("h03")) - node T_312 = add(UInt<2>("h02"), T_286) - node T_313 = tail(T_312, 1) - node T_316 = sub(T_286, UInt<2>("h03")) - node T_317 = tail(T_316, 1) - node T_319 = mux(T_310, T_277[T_313], T_277[T_317]) - node T_321 = lt(T_286, UInt<2>("h02")) - node T_323 = add(UInt<2>("h03"), T_286) - node T_324 = tail(T_323, 1) - node T_327 = sub(T_286, UInt<2>("h02")) - node T_328 = tail(T_327, 1) - node T_330 = mux(T_321, T_277[T_324], T_277[T_328]) - node T_332 = lt(T_286, UInt<1>("h01")) - node T_334 = add(UInt<3>("h04"), T_286) - node T_335 = tail(T_334, 1) - node T_338 = sub(T_286, UInt<1>("h01")) - node T_339 = tail(T_338, 1) - node T_341 = mux(T_332, T_277[T_335], T_277[T_339]) - wire T_343 : UInt<1>[5] - T_343[0] <= T_297 - T_343[1] <= T_308 - T_343[2] <= T_319 - T_343[3] <= T_330 - T_343[4] <= T_341 - wire T_356 : UInt<3>[5] - T_356[0] <= UInt<1>("h00") - T_356[1] <= UInt<1>("h01") - T_356[2] <= UInt<2>("h02") - T_356[3] <= UInt<2>("h03") - T_356[4] <= UInt<3>("h04") - node T_364 = add(T_273, UInt<1>("h01")) - node T_365 = tail(T_364, 1) - node T_367 = lt(T_365, UInt<3>("h05")) - node T_369 = add(UInt<1>("h00"), T_365) - node T_370 = tail(T_369, 1) - node T_373 = sub(T_365, UInt<3>("h05")) - node T_374 = tail(T_373, 1) - node T_376 = mux(T_367, T_356[T_370], T_356[T_374]) - node T_378 = lt(T_365, UInt<3>("h04")) - node T_380 = add(UInt<1>("h01"), T_365) - node T_381 = tail(T_380, 1) - node T_384 = sub(T_365, UInt<3>("h04")) - node T_385 = tail(T_384, 1) - node T_387 = mux(T_378, T_356[T_381], T_356[T_385]) - node T_389 = lt(T_365, UInt<2>("h03")) - node T_391 = add(UInt<2>("h02"), T_365) - node T_392 = tail(T_391, 1) - node T_395 = sub(T_365, UInt<2>("h03")) - node T_396 = tail(T_395, 1) - node T_398 = mux(T_389, T_356[T_392], T_356[T_396]) - node T_400 = lt(T_365, UInt<2>("h02")) - node T_402 = add(UInt<2>("h03"), T_365) - node T_403 = tail(T_402, 1) - node T_406 = sub(T_365, UInt<2>("h02")) - node T_407 = tail(T_406, 1) - node T_409 = mux(T_400, T_356[T_403], T_356[T_407]) - node T_411 = lt(T_365, UInt<1>("h01")) - node T_413 = add(UInt<3>("h04"), T_365) - node T_414 = tail(T_413, 1) - node T_417 = sub(T_365, UInt<1>("h01")) - node T_418 = tail(T_417, 1) - node T_420 = mux(T_411, T_356[T_414], T_356[T_418]) - wire T_422 : UInt<3>[5] - T_422[0] <= T_376 - T_422[1] <= T_387 - T_422[2] <= T_398 - T_422[3] <= T_409 - T_422[4] <= T_420 - node T_429 = mux(T_343[3], T_422[3], T_422[4]) - node T_430 = mux(T_343[2], T_422[2], T_429) - node T_431 = mux(T_343[1], T_422[1], T_430) - node T_432 = mux(T_343[0], T_422[0], T_431) - node T_433 = mux(T_275, T_273, T_432) - node T_435 = eq(T_433, UInt<1>("h00")) - node T_436 = and(io.out.ready, T_435) - io.in[0].ready <= T_436 - node T_438 = eq(T_433, UInt<1>("h01")) - node T_439 = and(io.out.ready, T_438) - io.in[1].ready <= T_439 - node T_441 = eq(T_433, UInt<2>("h02")) - node T_442 = and(io.out.ready, T_441) - io.in[2].ready <= T_442 - node T_444 = eq(T_433, UInt<2>("h03")) - node T_445 = and(io.out.ready, T_444) - io.in[3].ready <= T_445 - node T_447 = eq(T_433, UInt<3>("h04")) - node T_448 = and(io.out.ready, T_447) - io.in[4].ready <= T_448 - io.out.valid <= io.in[T_433].valid - io.out.bits <- io.in[T_433].bits - node T_479 = and(io.out.ready, io.out.valid) - when T_479 : - node T_481 = eq(T_275, UInt<1>("h00")) - node T_483 = and(T_481, UInt<1>("h01")) - when T_483 : - T_273 <= T_432 - T_275 <= UInt<1>("h01") - skip - when io.out.bits.last : - T_275 <= UInt<1>("h00") - skip - skip + output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>, flip acquire : UInt<1>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>}} - module NastiRouter : - input clk : Clock + io is invalid + io is invalid + reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 115:20] + reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 116:21] + reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 117:20] + reg ex_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 119:35] + reg ex_reg_valid : UInt<1>, clock @[Rocket.scala 120:35] + reg ex_reg_rvc : UInt<1>, clock @[Rocket.scala 121:35] + reg ex_reg_btb_hit : UInt<1>, clock @[Rocket.scala 122:35] + reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 123:35] + reg ex_reg_xcpt : UInt<1>, clock @[Rocket.scala 124:35] + reg ex_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 125:35] + reg ex_reg_load_use : UInt<1>, clock @[Rocket.scala 126:35] + reg ex_cause : UInt, clock @[Rocket.scala 127:35] + reg ex_reg_replay : UInt<1>, clock @[Rocket.scala 128:26] + reg ex_reg_pc : UInt, clock @[Rocket.scala 129:22] + reg ex_reg_inst : UInt, clock @[Rocket.scala 130:24] + reg mem_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 132:36] + reg mem_reg_valid : UInt<1>, clock @[Rocket.scala 133:36] + reg mem_reg_rvc : UInt<1>, clock @[Rocket.scala 134:36] + reg mem_reg_btb_hit : UInt<1>, clock @[Rocket.scala 135:36] + reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 136:36] + reg mem_reg_xcpt : UInt<1>, clock @[Rocket.scala 137:36] + reg mem_reg_replay : UInt<1>, clock @[Rocket.scala 138:36] + reg mem_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 139:36] + reg mem_reg_cause : UInt, clock @[Rocket.scala 140:36] + reg mem_reg_slow_bypass : UInt<1>, clock @[Rocket.scala 141:36] + reg mem_reg_load : UInt<1>, clock @[Rocket.scala 142:36] + reg mem_reg_store : UInt<1>, clock @[Rocket.scala 143:36] + reg mem_reg_pc : UInt, clock @[Rocket.scala 144:23] + reg mem_reg_inst : UInt, clock @[Rocket.scala 145:25] + reg mem_reg_wdata : UInt, clock @[Rocket.scala 146:26] + reg mem_reg_rs2 : UInt, clock @[Rocket.scala 147:24] + wire take_pc_mem : UInt<1> @[Rocket.scala 148:25] + take_pc_mem is invalid @[Rocket.scala 148:25] + reg wb_reg_valid : UInt<1>, clock @[Rocket.scala 150:35] + reg wb_reg_xcpt : UInt<1>, clock @[Rocket.scala 151:35] + reg wb_reg_replay : UInt<1>, clock @[Rocket.scala 152:35] + reg wb_reg_cause : UInt, clock @[Rocket.scala 153:35] + reg wb_reg_pc : UInt, clock @[Rocket.scala 154:22] + reg wb_reg_inst : UInt, clock @[Rocket.scala 155:24] + reg wb_reg_wdata : UInt, clock @[Rocket.scala 156:25] + reg wb_reg_rs2 : UInt, clock @[Rocket.scala 157:23] + wire take_pc_wb : UInt<1> @[Rocket.scala 158:24] + take_pc_wb is invalid @[Rocket.scala 158:24] + wire take_pc_id : UInt<1> @[Rocket.scala 160:24] + take_pc_id is invalid @[Rocket.scala 160:24] + node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[Rocket.scala 161:35] + node take_pc = or(take_pc_mem_wb, take_pc_id) @[Rocket.scala 162:32] + inst ibuf of IBuf @[Rocket.scala 165:20] + ibuf.io is invalid + ibuf.clock <= clock + ibuf.reset <= reset + ibuf.io.imem <- io.imem.resp @[Rocket.scala 168:16] + ibuf.io.kill <= take_pc @[Rocket.scala 169:16] + wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>} @[Rocket.scala 172:21] + id_ctrl is invalid @[Rocket.scala 172:21] + node _T_2603 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2605 = eq(_T_2603, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_2607 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0106f")) @[Decode.scala 13:65] + node _T_2609 = eq(_T_2607, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_2611 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0607f")) @[Decode.scala 13:65] + node _T_2613 = eq(_T_2611, UInt<32>("h0f")) @[Decode.scala 13:121] + node _T_2615 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07077")) @[Decode.scala 13:65] + node _T_2617 = eq(_T_2615, UInt<32>("h013")) @[Decode.scala 13:121] + node _T_2619 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05f")) @[Decode.scala 13:65] + node _T_2621 = eq(_T_2619, UInt<32>("h017")) @[Decode.scala 13:121] + node _T_2623 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00007f")) @[Decode.scala 13:65] + node _T_2625 = eq(_T_2623, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2627 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65] + node _T_2629 = eq(_T_2627, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2631 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000073")) @[Decode.scala 13:65] + node _T_2633 = eq(_T_2631, UInt<32>("h043")) @[Decode.scala 13:121] + node _T_2635 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e400007f")) @[Decode.scala 13:65] + node _T_2637 = eq(_T_2635, UInt<32>("h053")) @[Decode.scala 13:121] + node _T_2639 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707b")) @[Decode.scala 13:65] + node _T_2641 = eq(_T_2639, UInt<32>("h063")) @[Decode.scala 13:121] + node _T_2643 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07f")) @[Decode.scala 13:65] + node _T_2645 = eq(_T_2643, UInt<32>("h06f")) @[Decode.scala 13:121] + node _T_2647 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0ffefffff")) @[Decode.scala 13:65] + node _T_2649 = eq(_T_2647, UInt<32>("h073")) @[Decode.scala 13:121] + node _T_2651 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00305f")) @[Decode.scala 13:65] + node _T_2653 = eq(_T_2651, UInt<32>("h01013")) @[Decode.scala 13:121] + node _T_2655 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe00305f")) @[Decode.scala 13:65] + node _T_2657 = eq(_T_2655, UInt<32>("h0101b")) @[Decode.scala 13:121] + node _T_2659 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0605b")) @[Decode.scala 13:65] + node _T_2661 = eq(_T_2659, UInt<32>("h02003")) @[Decode.scala 13:121] + node _T_2663 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2665 = eq(_T_2663, UInt<32>("h02013")) @[Decode.scala 13:121] + node _T_2667 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01800607f")) @[Decode.scala 13:65] + node _T_2669 = eq(_T_2667, UInt<32>("h0202f")) @[Decode.scala 13:121] + node _T_2671 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2673 = eq(_T_2671, UInt<32>("h02073")) @[Decode.scala 13:121] + node _T_2675 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0bc00707f")) @[Decode.scala 13:65] + node _T_2677 = eq(_T_2675, UInt<32>("h05013")) @[Decode.scala 13:121] + node _T_2679 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be00705f")) @[Decode.scala 13:65] + node _T_2681 = eq(_T_2679, UInt<32>("h0501b")) @[Decode.scala 13:121] + node _T_2683 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65] + node _T_2685 = eq(_T_2683, UInt<32>("h05033")) @[Decode.scala 13:121] + node _T_2687 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe004077")) @[Decode.scala 13:65] + node _T_2689 = eq(_T_2687, UInt<32>("h02004033")) @[Decode.scala 13:121] + node _T_2691 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e800607f")) @[Decode.scala 13:65] + node _T_2693 = eq(_T_2691, UInt<32>("h0800202f")) @[Decode.scala 13:121] + node _T_2695 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f9f0607f")) @[Decode.scala 13:65] + node _T_2697 = eq(_T_2695, UInt<32>("h01000202f")) @[Decode.scala 13:121] + node _T_2699 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0dfffffff")) @[Decode.scala 13:65] + node _T_2701 = eq(_T_2699, UInt<32>("h010200073")) @[Decode.scala 13:121] + node _T_2703 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010500073")) @[Decode.scala 13:121] + node _T_2705 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe007fff")) @[Decode.scala 13:65] + node _T_2707 = eq(_T_2705, UInt<32>("h012000073")) @[Decode.scala 13:121] + node _T_2709 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f400607f")) @[Decode.scala 13:65] + node _T_2711 = eq(_T_2709, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2713 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00607f")) @[Decode.scala 13:65] + node _T_2715 = eq(_T_2713, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2717 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00507f")) @[Decode.scala 13:65] + node _T_2719 = eq(_T_2717, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2721 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65] + node _T_2723 = eq(_T_2721, UInt<32>("h040100053")) @[Decode.scala 13:121] + node _T_2725 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65] + node _T_2727 = eq(_T_2725, UInt<32>("h042000053")) @[Decode.scala 13:121] + node _T_2729 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0007f")) @[Decode.scala 13:65] + node _T_2731 = eq(_T_2729, UInt<32>("h058000053")) @[Decode.scala 13:121] + node _T_2733 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07b200073")) @[Decode.scala 13:121] + node _T_2735 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edc0007f")) @[Decode.scala 13:65] + node _T_2737 = eq(_T_2735, UInt<32>("h0c0000053")) @[Decode.scala 13:121] + node _T_2739 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0607f")) @[Decode.scala 13:65] + node _T_2741 = eq(_T_2739, UInt<32>("h0e0000053")) @[Decode.scala 13:121] + node _T_2743 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edf0707f")) @[Decode.scala 13:65] + node _T_2745 = eq(_T_2743, UInt<32>("h0e0000053")) @[Decode.scala 13:121] + node _T_2747 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0603f")) @[Decode.scala 13:65] + node _T_2749 = eq(_T_2747, UInt<32>("h023")) @[Decode.scala 13:121] + node _T_2751 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0306f")) @[Decode.scala 13:65] + node _T_2753 = eq(_T_2751, UInt<32>("h01063")) @[Decode.scala 13:121] + node _T_2755 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0407f")) @[Decode.scala 13:65] + node _T_2757 = eq(_T_2755, UInt<32>("h04063")) @[Decode.scala 13:121] + node _T_2759 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc007077")) @[Decode.scala 13:65] + node _T_2761 = eq(_T_2759, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2763 = or(UInt<1>("h00"), _T_2605) @[Decode.scala 14:30] + node _T_2764 = or(_T_2763, _T_2609) @[Decode.scala 14:30] + node _T_2765 = or(_T_2764, _T_2613) @[Decode.scala 14:30] + node _T_2766 = or(_T_2765, _T_2617) @[Decode.scala 14:30] + node _T_2767 = or(_T_2766, _T_2621) @[Decode.scala 14:30] + node _T_2768 = or(_T_2767, _T_2625) @[Decode.scala 14:30] + node _T_2769 = or(_T_2768, _T_2629) @[Decode.scala 14:30] + node _T_2770 = or(_T_2769, _T_2633) @[Decode.scala 14:30] + node _T_2771 = or(_T_2770, _T_2637) @[Decode.scala 14:30] + node _T_2772 = or(_T_2771, _T_2641) @[Decode.scala 14:30] + node _T_2773 = or(_T_2772, _T_2645) @[Decode.scala 14:30] + node _T_2774 = or(_T_2773, _T_2649) @[Decode.scala 14:30] + node _T_2775 = or(_T_2774, _T_2653) @[Decode.scala 14:30] + node _T_2776 = or(_T_2775, _T_2657) @[Decode.scala 14:30] + node _T_2777 = or(_T_2776, _T_2661) @[Decode.scala 14:30] + node _T_2778 = or(_T_2777, _T_2665) @[Decode.scala 14:30] + node _T_2779 = or(_T_2778, _T_2669) @[Decode.scala 14:30] + node _T_2780 = or(_T_2779, _T_2673) @[Decode.scala 14:30] + node _T_2781 = or(_T_2780, _T_2677) @[Decode.scala 14:30] + node _T_2782 = or(_T_2781, _T_2681) @[Decode.scala 14:30] + node _T_2783 = or(_T_2782, _T_2685) @[Decode.scala 14:30] + node _T_2784 = or(_T_2783, _T_2689) @[Decode.scala 14:30] + node _T_2785 = or(_T_2784, _T_2693) @[Decode.scala 14:30] + node _T_2786 = or(_T_2785, _T_2697) @[Decode.scala 14:30] + node _T_2787 = or(_T_2786, _T_2701) @[Decode.scala 14:30] + node _T_2788 = or(_T_2787, _T_2703) @[Decode.scala 14:30] + node _T_2789 = or(_T_2788, _T_2707) @[Decode.scala 14:30] + node _T_2790 = or(_T_2789, _T_2711) @[Decode.scala 14:30] + node _T_2791 = or(_T_2790, _T_2715) @[Decode.scala 14:30] + node _T_2792 = or(_T_2791, _T_2719) @[Decode.scala 14:30] + node _T_2793 = or(_T_2792, _T_2723) @[Decode.scala 14:30] + node _T_2794 = or(_T_2793, _T_2727) @[Decode.scala 14:30] + node _T_2795 = or(_T_2794, _T_2731) @[Decode.scala 14:30] + node _T_2796 = or(_T_2795, _T_2733) @[Decode.scala 14:30] + node _T_2797 = or(_T_2796, _T_2737) @[Decode.scala 14:30] + node _T_2798 = or(_T_2797, _T_2741) @[Decode.scala 14:30] + node _T_2799 = or(_T_2798, _T_2745) @[Decode.scala 14:30] + node _T_2800 = or(_T_2799, _T_2749) @[Decode.scala 14:30] + node _T_2801 = or(_T_2800, _T_2753) @[Decode.scala 14:30] + node _T_2802 = or(_T_2801, _T_2757) @[Decode.scala 14:30] + node _T_2803 = or(_T_2802, _T_2761) @[Decode.scala 14:30] + node _T_2805 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05c")) @[Decode.scala 13:65] + node _T_2807 = eq(_T_2805, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2809 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h060")) @[Decode.scala 13:65] + node _T_2811 = eq(_T_2809, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_2813 = or(UInt<1>("h00"), _T_2807) @[Decode.scala 14:30] + node _T_2814 = or(_T_2813, _T_2811) @[Decode.scala 14:30] + node _T_2817 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h074")) @[Decode.scala 13:65] + node _T_2819 = eq(_T_2817, UInt<32>("h060")) @[Decode.scala 13:121] + node _T_2821 = or(UInt<1>("h00"), _T_2819) @[Decode.scala 14:30] + node _T_2823 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h068")) @[Decode.scala 13:65] + node _T_2825 = eq(_T_2823, UInt<32>("h068")) @[Decode.scala 13:121] + node _T_2827 = or(UInt<1>("h00"), _T_2825) @[Decode.scala 14:30] + node _T_2829 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0203c")) @[Decode.scala 13:65] + node _T_2831 = eq(_T_2829, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_2833 = or(UInt<1>("h00"), _T_2831) @[Decode.scala 14:30] + node _T_2835 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65] + node _T_2837 = eq(_T_2835, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2839 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65] + node _T_2841 = eq(_T_2839, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2843 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02048")) @[Decode.scala 13:65] + node _T_2845 = eq(_T_2843, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_2847 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h042003024")) @[Decode.scala 13:65] + node _T_2849 = eq(_T_2847, UInt<32>("h02000020")) @[Decode.scala 13:121] + node _T_2851 = or(UInt<1>("h00"), _T_2837) @[Decode.scala 14:30] + node _T_2852 = or(_T_2851, _T_2841) @[Decode.scala 14:30] + node _T_2853 = or(_T_2852, _T_2845) @[Decode.scala 14:30] + node _T_2854 = or(_T_2853, _T_2849) @[Decode.scala 14:30] + node _T_2856 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65] + node _T_2858 = eq(_T_2856, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2860 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04024")) @[Decode.scala 13:65] + node _T_2862 = eq(_T_2860, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2864 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h038")) @[Decode.scala 13:65] + node _T_2866 = eq(_T_2864, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2868 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02050")) @[Decode.scala 13:65] + node _T_2870 = eq(_T_2868, UInt<32>("h02000")) @[Decode.scala 13:121] + node _T_2872 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000034")) @[Decode.scala 13:65] + node _T_2874 = eq(_T_2872, UInt<32>("h090000010")) @[Decode.scala 13:121] + node _T_2876 = or(UInt<1>("h00"), _T_2858) @[Decode.scala 14:30] + node _T_2877 = or(_T_2876, _T_2862) @[Decode.scala 14:30] + node _T_2878 = or(_T_2877, _T_2866) @[Decode.scala 14:30] + node _T_2879 = or(_T_2878, _T_2870) @[Decode.scala 14:30] + node _T_2880 = or(_T_2879, _T_2874) @[Decode.scala 14:30] + node _T_2882 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h058")) @[Decode.scala 13:65] + node _T_2884 = eq(_T_2882, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2886 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020")) @[Decode.scala 13:65] + node _T_2888 = eq(_T_2886, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2890 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0c")) @[Decode.scala 13:65] + node _T_2892 = eq(_T_2890, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2894 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65] + node _T_2896 = eq(_T_2894, UInt<32>("h048")) @[Decode.scala 13:121] + node _T_2898 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04050")) @[Decode.scala 13:65] + node _T_2900 = eq(_T_2898, UInt<32>("h04050")) @[Decode.scala 13:121] + node _T_2902 = or(UInt<1>("h00"), _T_2884) @[Decode.scala 14:30] + node _T_2903 = or(_T_2902, _T_2888) @[Decode.scala 14:30] + node _T_2904 = or(_T_2903, _T_2892) @[Decode.scala 14:30] + node _T_2905 = or(_T_2904, _T_2896) @[Decode.scala 14:30] + node _T_2906 = or(_T_2905, _T_2900) @[Decode.scala 14:30] + node _T_2908 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65] + node _T_2910 = eq(_T_2908, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2912 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65] + node _T_2914 = eq(_T_2912, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2916 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04008")) @[Decode.scala 13:65] + node _T_2918 = eq(_T_2916, UInt<32>("h04000")) @[Decode.scala 13:121] + node _T_2920 = or(UInt<1>("h00"), _T_2910) @[Decode.scala 14:30] + node _T_2921 = or(_T_2920, _T_2858) @[Decode.scala 14:30] + node _T_2922 = or(_T_2921, _T_2914) @[Decode.scala 14:30] + node _T_2923 = or(_T_2922, _T_2918) @[Decode.scala 14:30] + node _T_2924 = cat(_T_2923, _T_2906) @[Cat.scala 30:58] + node _T_2926 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04004")) @[Decode.scala 13:65] + node _T_2928 = eq(_T_2926, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2930 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_2932 = eq(_T_2930, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2934 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h024")) @[Decode.scala 13:65] + node _T_2936 = eq(_T_2934, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2938 = or(UInt<1>("h00"), _T_2928) @[Decode.scala 14:30] + node _T_2939 = or(_T_2938, _T_2932) @[Decode.scala 14:30] + node _T_2940 = or(_T_2939, _T_2858) @[Decode.scala 14:30] + node _T_2941 = or(_T_2940, _T_2936) @[Decode.scala 14:30] + node _T_2942 = or(_T_2941, _T_2914) @[Decode.scala 14:30] + node _T_2944 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65] + node _T_2946 = eq(_T_2944, UInt<32>("h014")) @[Decode.scala 13:121] + node _T_2948 = or(UInt<1>("h00"), _T_2946) @[Decode.scala 14:30] + node _T_2949 = or(_T_2948, _T_2896) @[Decode.scala 14:30] + node _T_2950 = cat(_T_2949, _T_2942) @[Cat.scala 30:58] + node _T_2952 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65] + node _T_2954 = eq(_T_2952, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_2956 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65] + node _T_2958 = eq(_T_2956, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_2960 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30] + node _T_2961 = or(_T_2960, _T_2958) @[Decode.scala 14:30] + node _T_2963 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65] + node _T_2965 = eq(_T_2963, UInt<32>("h014")) @[Decode.scala 13:121] + node _T_2967 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30] + node _T_2968 = or(_T_2967, _T_2965) @[Decode.scala 14:30] + node _T_2970 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h030")) @[Decode.scala 13:65] + node _T_2972 = eq(_T_2970, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2974 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0201c")) @[Decode.scala 13:65] + node _T_2976 = eq(_T_2974, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2978 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65] + node _T_2980 = eq(_T_2978, UInt<32>("h010")) @[Decode.scala 13:121] + node _T_2982 = or(UInt<1>("h00"), _T_2972) @[Decode.scala 14:30] + node _T_2983 = or(_T_2982, _T_2976) @[Decode.scala 14:30] + node _T_2984 = or(_T_2983, _T_2980) @[Decode.scala 14:30] + node _T_2985 = cat(_T_2984, _T_2968) @[Cat.scala 30:58] + node _T_2986 = cat(_T_2985, _T_2961) @[Cat.scala 30:58] + node _T_2988 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010")) @[Decode.scala 13:65] + node _T_2990 = eq(_T_2988, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2992 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08")) @[Decode.scala 13:65] + node _T_2994 = eq(_T_2992, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2996 = or(UInt<1>("h00"), _T_2990) @[Decode.scala 14:30] + node _T_2997 = or(_T_2996, _T_2994) @[Decode.scala 14:30] + node _T_2999 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65] + node _T_3001 = eq(_T_2999, UInt<32>("h01010")) @[Decode.scala 13:121] + node _T_3003 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01058")) @[Decode.scala 13:65] + node _T_3005 = eq(_T_3003, UInt<32>("h01040")) @[Decode.scala 13:121] + node _T_3007 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07044")) @[Decode.scala 13:65] + node _T_3009 = eq(_T_3007, UInt<32>("h07000")) @[Decode.scala 13:121] + node _T_3011 = or(UInt<1>("h00"), _T_3001) @[Decode.scala 14:30] + node _T_3012 = or(_T_3011, _T_3005) @[Decode.scala 14:30] + node _T_3013 = or(_T_3012, _T_3009) @[Decode.scala 14:30] + node _T_3015 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04054")) @[Decode.scala 13:65] + node _T_3017 = eq(_T_3015, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3019 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02058")) @[Decode.scala 13:65] + node _T_3021 = eq(_T_3019, UInt<32>("h02040")) @[Decode.scala 13:121] + node _T_3023 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65] + node _T_3025 = eq(_T_3023, UInt<32>("h03010")) @[Decode.scala 13:121] + node _T_3027 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65] + node _T_3029 = eq(_T_3027, UInt<32>("h06010")) @[Decode.scala 13:121] + node _T_3031 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003034")) @[Decode.scala 13:65] + node _T_3033 = eq(_T_3031, UInt<32>("h040000030")) @[Decode.scala 13:121] + node _T_3035 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040001054")) @[Decode.scala 13:65] + node _T_3037 = eq(_T_3035, UInt<32>("h040001010")) @[Decode.scala 13:121] + node _T_3039 = or(UInt<1>("h00"), _T_3017) @[Decode.scala 14:30] + node _T_3040 = or(_T_3039, _T_3021) @[Decode.scala 14:30] + node _T_3041 = or(_T_3040, _T_3025) @[Decode.scala 14:30] + node _T_3042 = or(_T_3041, _T_3029) @[Decode.scala 14:30] + node _T_3043 = or(_T_3042, _T_3033) @[Decode.scala 14:30] + node _T_3044 = or(_T_3043, _T_3037) @[Decode.scala 14:30] + node _T_3046 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02054")) @[Decode.scala 13:65] + node _T_3048 = eq(_T_3046, UInt<32>("h02010")) @[Decode.scala 13:121] + node _T_3050 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040004054")) @[Decode.scala 13:65] + node _T_3052 = eq(_T_3050, UInt<32>("h04010")) @[Decode.scala 13:121] + node _T_3054 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05054")) @[Decode.scala 13:65] + node _T_3056 = eq(_T_3054, UInt<32>("h04010")) @[Decode.scala 13:121] + node _T_3058 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04058")) @[Decode.scala 13:65] + node _T_3060 = eq(_T_3058, UInt<32>("h04040")) @[Decode.scala 13:121] + node _T_3062 = or(UInt<1>("h00"), _T_3048) @[Decode.scala 14:30] + node _T_3063 = or(_T_3062, _T_3052) @[Decode.scala 14:30] + node _T_3064 = or(_T_3063, _T_3056) @[Decode.scala 14:30] + node _T_3065 = or(_T_3064, _T_3060) @[Decode.scala 14:30] + node _T_3067 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65] + node _T_3069 = eq(_T_3067, UInt<32>("h02010")) @[Decode.scala 13:121] + node _T_3071 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003054")) @[Decode.scala 13:65] + node _T_3073 = eq(_T_3071, UInt<32>("h040001010")) @[Decode.scala 13:121] + node _T_3075 = or(UInt<1>("h00"), _T_3069) @[Decode.scala 14:30] + node _T_3076 = or(_T_3075, _T_3060) @[Decode.scala 14:30] + node _T_3077 = or(_T_3076, _T_3033) @[Decode.scala 14:30] + node _T_3078 = or(_T_3077, _T_3073) @[Decode.scala 14:30] + node _T_3079 = cat(_T_3044, _T_3013) @[Cat.scala 30:58] + node _T_3080 = cat(_T_3078, _T_3065) @[Cat.scala 30:58] + node _T_3081 = cat(_T_3080, _T_3079) @[Cat.scala 30:58] + node _T_3083 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0405f")) @[Decode.scala 13:65] + node _T_3085 = eq(_T_3083, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_3087 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0107f")) @[Decode.scala 13:65] + node _T_3089 = eq(_T_3087, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_3091 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707f")) @[Decode.scala 13:65] + node _T_3093 = eq(_T_3091, UInt<32>("h0100f")) @[Decode.scala 13:121] + node _T_3095 = or(UInt<1>("h00"), _T_3085) @[Decode.scala 14:30] + node _T_3096 = or(_T_3095, _T_2605) @[Decode.scala 14:30] + node _T_3097 = or(_T_3096, _T_3089) @[Decode.scala 14:30] + node _T_3098 = or(_T_3097, _T_3093) @[Decode.scala 14:30] + node _T_3099 = or(_T_3098, _T_2661) @[Decode.scala 14:30] + node _T_3100 = or(_T_3099, _T_2669) @[Decode.scala 14:30] + node _T_3101 = or(_T_3100, _T_2693) @[Decode.scala 14:30] + node _T_3102 = or(_T_3101, _T_2697) @[Decode.scala 14:30] + node _T_3104 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02008")) @[Decode.scala 13:65] + node _T_3106 = eq(_T_3104, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_3108 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65] + node _T_3110 = eq(_T_3108, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_3112 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018000020")) @[Decode.scala 13:65] + node _T_3114 = eq(_T_3112, UInt<32>("h018000020")) @[Decode.scala 13:121] + node _T_3116 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020000020")) @[Decode.scala 13:65] + node _T_3118 = eq(_T_3116, UInt<32>("h020000020")) @[Decode.scala 13:121] + node _T_3120 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30] + node _T_3121 = or(_T_3120, _T_3110) @[Decode.scala 14:30] + node _T_3122 = or(_T_3121, _T_3114) @[Decode.scala 14:30] + node _T_3123 = or(_T_3122, _T_3118) @[Decode.scala 14:30] + node _T_3125 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010002008")) @[Decode.scala 13:65] + node _T_3127 = eq(_T_3125, UInt<32>("h010002008")) @[Decode.scala 13:121] + node _T_3129 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040002008")) @[Decode.scala 13:65] + node _T_3131 = eq(_T_3129, UInt<32>("h040002008")) @[Decode.scala 13:121] + node _T_3133 = or(UInt<1>("h00"), _T_3127) @[Decode.scala 14:30] + node _T_3134 = or(_T_3133, _T_3131) @[Decode.scala 14:30] + node _T_3136 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08000008")) @[Decode.scala 13:65] + node _T_3138 = eq(_T_3136, UInt<32>("h08000008")) @[Decode.scala 13:121] + node _T_3140 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000008")) @[Decode.scala 13:65] + node _T_3142 = eq(_T_3140, UInt<32>("h010000008")) @[Decode.scala 13:121] + node _T_3144 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000008")) @[Decode.scala 13:65] + node _T_3146 = eq(_T_3144, UInt<32>("h080000008")) @[Decode.scala 13:121] + node _T_3148 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30] + node _T_3149 = or(_T_3148, _T_3138) @[Decode.scala 14:30] + node _T_3150 = or(_T_3149, _T_3142) @[Decode.scala 14:30] + node _T_3151 = or(_T_3150, _T_3146) @[Decode.scala 14:30] + node _T_3153 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018002008")) @[Decode.scala 13:65] + node _T_3155 = eq(_T_3153, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_3157 = or(UInt<1>("h00"), _T_3155) @[Decode.scala 14:30] + node _T_3159 = cat(_T_3134, _T_3123) @[Cat.scala 30:58] + node _T_3160 = cat(UInt<1>("h00"), _T_3157) @[Cat.scala 30:58] + node _T_3161 = cat(_T_3160, _T_3151) @[Cat.scala 30:58] + node _T_3162 = cat(_T_3161, _T_3159) @[Cat.scala 30:58] + node _T_3164 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01000")) @[Decode.scala 13:65] + node _T_3166 = eq(_T_3164, UInt<32>("h01000")) @[Decode.scala 13:121] + node _T_3168 = or(UInt<1>("h00"), _T_3166) @[Decode.scala 14:30] + node _T_3170 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000")) @[Decode.scala 13:65] + node _T_3172 = eq(_T_3170, UInt<32>("h02000")) @[Decode.scala 13:121] + node _T_3174 = or(UInt<1>("h00"), _T_3172) @[Decode.scala 14:30] + node _T_3176 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000")) @[Decode.scala 13:65] + node _T_3178 = eq(_T_3176, UInt<32>("h04000")) @[Decode.scala 13:121] + node _T_3180 = or(UInt<1>("h00"), _T_3178) @[Decode.scala 14:30] + node _T_3181 = cat(_T_3180, _T_3174) @[Cat.scala 30:58] + node _T_3182 = cat(_T_3181, _T_3168) @[Cat.scala 30:58] + node _T_3184 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000060")) @[Decode.scala 13:65] + node _T_3186 = eq(_T_3184, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3188 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65] + node _T_3190 = eq(_T_3188, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3192 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h070")) @[Decode.scala 13:65] + node _T_3194 = eq(_T_3192, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3196 = or(UInt<1>("h00"), _T_3186) @[Decode.scala 14:30] + node _T_3197 = or(_T_3196, _T_3190) @[Decode.scala 14:30] + node _T_3198 = or(_T_3197, _T_3194) @[Decode.scala 14:30] + node _T_3200 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c")) @[Decode.scala 13:65] + node _T_3202 = eq(_T_3200, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_3204 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040000060")) @[Decode.scala 13:65] + node _T_3206 = eq(_T_3204, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3208 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000060")) @[Decode.scala 13:65] + node _T_3210 = eq(_T_3208, UInt<32>("h010000040")) @[Decode.scala 13:121] + node _T_3212 = or(UInt<1>("h00"), _T_3202) @[Decode.scala 14:30] + node _T_3213 = or(_T_3212, _T_3206) @[Decode.scala 14:30] + node _T_3214 = or(_T_3213, _T_3194) @[Decode.scala 14:30] + node _T_3215 = or(_T_3214, _T_3210) @[Decode.scala 14:30] + node _T_3217 = or(UInt<1>("h00"), _T_3194) @[Decode.scala 14:30] + node _T_3219 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03c")) @[Decode.scala 13:65] + node _T_3221 = eq(_T_3219, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_3223 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65] + node _T_3225 = eq(_T_3223, UInt<32>("h010000040")) @[Decode.scala 13:121] + node _T_3227 = or(UInt<1>("h00"), _T_3221) @[Decode.scala 14:30] + node _T_3228 = or(_T_3227, _T_3186) @[Decode.scala 14:30] + node _T_3229 = or(_T_3228, _T_3194) @[Decode.scala 14:30] + node _T_3230 = or(_T_3229, _T_3225) @[Decode.scala 14:30] + node _T_3232 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000074")) @[Decode.scala 13:65] + node _T_3234 = eq(_T_3232, UInt<32>("h02000030")) @[Decode.scala 13:121] + node _T_3236 = or(UInt<1>("h00"), _T_3234) @[Decode.scala 14:30] + node _T_3238 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65] + node _T_3240 = eq(_T_3238, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_3242 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_3244 = eq(_T_3242, UInt<32>("h010")) @[Decode.scala 13:121] + node _T_3246 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02024")) @[Decode.scala 13:65] + node _T_3248 = eq(_T_3246, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_3250 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65] + node _T_3252 = eq(_T_3250, UInt<32>("h028")) @[Decode.scala 13:121] + node _T_3254 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01030")) @[Decode.scala 13:65] + node _T_3256 = eq(_T_3254, UInt<32>("h01030")) @[Decode.scala 13:121] + node _T_3258 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02030")) @[Decode.scala 13:65] + node _T_3260 = eq(_T_3258, UInt<32>("h02030")) @[Decode.scala 13:121] + node _T_3262 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_3264 = eq(_T_3262, UInt<32>("h080000010")) @[Decode.scala 13:121] + node _T_3266 = or(UInt<1>("h00"), _T_3240) @[Decode.scala 14:30] + node _T_3267 = or(_T_3266, _T_3244) @[Decode.scala 14:30] + node _T_3268 = or(_T_3267, _T_3248) @[Decode.scala 14:30] + node _T_3269 = or(_T_3268, _T_3252) @[Decode.scala 14:30] + node _T_3270 = or(_T_3269, _T_3256) @[Decode.scala 14:30] + node _T_3271 = or(_T_3270, _T_3260) @[Decode.scala 14:30] + node _T_3272 = or(_T_3271, _T_3264) @[Decode.scala 14:30] + node _T_3274 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01070")) @[Decode.scala 13:65] + node _T_3276 = eq(_T_3274, UInt<32>("h01070")) @[Decode.scala 13:121] + node _T_3278 = or(UInt<1>("h00"), _T_3276) @[Decode.scala 14:30] + node _T_3280 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02070")) @[Decode.scala 13:65] + node _T_3282 = eq(_T_3280, UInt<32>("h02070")) @[Decode.scala 13:121] + node _T_3284 = or(UInt<1>("h00"), _T_3282) @[Decode.scala 14:30] + node _T_3286 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03070")) @[Decode.scala 13:65] + node _T_3288 = eq(_T_3286, UInt<32>("h070")) @[Decode.scala 13:121] + node _T_3290 = or(UInt<1>("h00"), _T_3288) @[Decode.scala 14:30] + node _T_3291 = cat(_T_3290, _T_3284) @[Cat.scala 30:58] + node _T_3292 = cat(_T_3291, _T_3278) @[Cat.scala 30:58] + node _T_3294 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65] + node _T_3296 = eq(_T_3294, UInt<32>("h01008")) @[Decode.scala 13:121] + node _T_3298 = or(UInt<1>("h00"), _T_3296) @[Decode.scala 14:30] + node _T_3300 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65] + node _T_3302 = eq(_T_3300, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_3304 = or(UInt<1>("h00"), _T_3302) @[Decode.scala 14:30] + node _T_3306 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06048")) @[Decode.scala 13:65] + node _T_3308 = eq(_T_3306, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_3310 = or(UInt<1>("h00"), _T_3308) @[Decode.scala 14:30] + node _T_3312 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0105c")) @[Decode.scala 13:65] + node _T_3314 = eq(_T_3312, UInt<32>("h01004")) @[Decode.scala 13:121] + node _T_3316 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000060")) @[Decode.scala 13:65] + node _T_3318 = eq(_T_3316, UInt<32>("h02000040")) @[Decode.scala 13:121] + node _T_3320 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0d0000070")) @[Decode.scala 13:65] + node _T_3322 = eq(_T_3320, UInt<32>("h040000050")) @[Decode.scala 13:121] + node _T_3324 = or(UInt<1>("h00"), _T_3314) @[Decode.scala 14:30] + node _T_3325 = or(_T_3324, _T_3318) @[Decode.scala 14:30] + node _T_3326 = or(_T_3325, _T_3322) @[Decode.scala 14:30] + id_ctrl.legal <= _T_2803 @[IDecode.scala 65:42] + id_ctrl.fp <= _T_2814 @[IDecode.scala 65:42] + id_ctrl.rocc <= UInt<1>("h00") @[IDecode.scala 65:42] + id_ctrl.branch <= _T_2821 @[IDecode.scala 65:42] + id_ctrl.jal <= _T_2827 @[IDecode.scala 65:42] + id_ctrl.jalr <= _T_2833 @[IDecode.scala 65:42] + id_ctrl.rxs2 <= _T_2854 @[IDecode.scala 65:42] + id_ctrl.rxs1 <= _T_2880 @[IDecode.scala 65:42] + id_ctrl.sel_alu2 <= _T_2924 @[IDecode.scala 65:42] + id_ctrl.sel_alu1 <= _T_2950 @[IDecode.scala 65:42] + id_ctrl.sel_imm <= _T_2986 @[IDecode.scala 65:42] + id_ctrl.alu_dw <= _T_2997 @[IDecode.scala 65:42] + id_ctrl.alu_fn <= _T_3081 @[IDecode.scala 65:42] + id_ctrl.mem <= _T_3102 @[IDecode.scala 65:42] + id_ctrl.mem_cmd <= _T_3162 @[IDecode.scala 65:42] + id_ctrl.mem_type <= _T_3182 @[IDecode.scala 65:42] + id_ctrl.rfs1 <= _T_3198 @[IDecode.scala 65:42] + id_ctrl.rfs2 <= _T_3215 @[IDecode.scala 65:42] + id_ctrl.rfs3 <= _T_3217 @[IDecode.scala 65:42] + id_ctrl.wfd <= _T_3230 @[IDecode.scala 65:42] + id_ctrl.div <= _T_3236 @[IDecode.scala 65:42] + id_ctrl.wxd <= _T_3272 @[IDecode.scala 65:42] + id_ctrl.csr <= _T_3292 @[IDecode.scala 65:42] + id_ctrl.fence_i <= _T_3298 @[IDecode.scala 65:42] + id_ctrl.fence <= _T_3304 @[IDecode.scala 65:42] + id_ctrl.amo <= _T_3310 @[IDecode.scala 65:42] + id_ctrl.dp <= _T_3326 @[IDecode.scala 65:42] + wire id_load_use : UInt<1> @[Rocket.scala 177:25] + id_load_use is invalid @[Rocket.scala 177:25] + reg id_reg_fence : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Rocket.scala 178:25] + cmem _T_3331 : UInt<64>[31] @[Rocket.scala 682:23] + wire id_rs_0 : UInt @[Rocket.scala 688:26] + id_rs_0 is invalid @[Rocket.scala 688:26] + node _T_3335 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 689:45] + node _T_3336 = and(UInt<1>("h00"), _T_3335) @[Rocket.scala 689:37] + node _T_3338 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) @[Rocket.scala 683:44] + node _T_3339 = not(_T_3338) @[Rocket.scala 683:39] + infer mport _T_3340 = _T_3331[_T_3339], clock + node _T_3341 = mux(_T_3336, UInt<1>("h00"), _T_3340) @[Rocket.scala 689:25] + id_rs_0 <= _T_3341 @[Rocket.scala 689:19] + wire id_rs_1 : UInt @[Rocket.scala 688:26] + id_rs_1 is invalid @[Rocket.scala 688:26] + node _T_3345 = eq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 689:45] + node _T_3346 = and(UInt<1>("h00"), _T_3345) @[Rocket.scala 689:37] + node _T_3348 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) @[Rocket.scala 683:44] + node _T_3349 = not(_T_3348) @[Rocket.scala 683:39] + infer mport _T_3350 = _T_3331[_T_3349], clock + node _T_3351 = mux(_T_3346, UInt<1>("h00"), _T_3350) @[Rocket.scala 689:25] + id_rs_1 <= _T_3351 @[Rocket.scala 689:19] + wire ctrl_killd : UInt<1> @[Rocket.scala 183:24] + ctrl_killd is invalid @[Rocket.scala 183:24] + node _T_3353 = asSInt(ibuf.io.pc) @[Rocket.scala 184:28] + node _T_3356 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3358 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) @[Rocket.scala 704:48] + node _T_3359 = asSInt(_T_3358) @[Rocket.scala 704:53] + node _T_3360 = mux(_T_3356, asSInt(UInt<1>("h00")), _T_3359) @[Rocket.scala 704:19] + node _T_3362 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3363 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) @[Rocket.scala 705:41] + node _T_3364 = asSInt(_T_3363) @[Rocket.scala 705:49] + node _T_3365 = mux(_T_3362, _T_3364, _T_3360) @[Rocket.scala 705:21] + node _T_3367 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3369 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3370 = and(_T_3367, _T_3369) @[Rocket.scala 706:36] + node _T_3371 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) @[Rocket.scala 706:65] + node _T_3372 = asSInt(_T_3371) @[Rocket.scala 706:73] + node _T_3373 = mux(_T_3370, _T_3360, _T_3372) @[Rocket.scala 706:21] + node _T_3375 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3377 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3378 = or(_T_3375, _T_3377) @[Rocket.scala 707:33] + node _T_3381 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3382 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 708:39] + node _T_3383 = asSInt(_T_3382) @[Rocket.scala 708:44] + node _T_3385 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3386 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 709:39] + node _T_3387 = asSInt(_T_3386) @[Rocket.scala 709:43] + node _T_3388 = mux(_T_3385, _T_3387, _T_3360) @[Rocket.scala 709:18] + node _T_3389 = mux(_T_3381, _T_3383, _T_3388) @[Rocket.scala 708:18] + node _T_3390 = mux(_T_3378, asSInt(UInt<1>("h00")), _T_3389) @[Rocket.scala 707:18] + node _T_3392 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3394 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3395 = or(_T_3392, _T_3394) @[Rocket.scala 710:35] + node _T_3397 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) @[Rocket.scala 710:66] + node _T_3398 = mux(_T_3395, UInt<1>("h00"), _T_3397) @[Rocket.scala 710:20] + node _T_3400 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3403 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3405 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3406 = or(_T_3403, _T_3405) @[Rocket.scala 712:34] + node _T_3407 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) @[Rocket.scala 712:57] + node _T_3409 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3410 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) @[Rocket.scala 713:39] + node _T_3411 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) @[Rocket.scala 713:52] + node _T_3412 = mux(_T_3409, _T_3410, _T_3411) @[Rocket.scala 713:19] + node _T_3413 = mux(_T_3406, _T_3407, _T_3412) @[Rocket.scala 712:19] + node _T_3414 = mux(_T_3400, UInt<1>("h00"), _T_3413) @[Rocket.scala 711:19] + node _T_3416 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3417 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 714:37] + node _T_3419 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3420 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 715:37] + node _T_3422 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3423 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) @[Rocket.scala 716:37] + node _T_3425 = mux(_T_3422, _T_3423, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3426 = mux(_T_3419, _T_3420, _T_3425) @[Rocket.scala 715:17] + node _T_3427 = mux(_T_3416, _T_3417, _T_3426) @[Rocket.scala 714:17] + node _T_3428 = cat(_T_3398, _T_3414) @[Cat.scala 30:58] + node _T_3429 = cat(_T_3428, _T_3427) @[Cat.scala 30:58] + node _T_3430 = asUInt(_T_3390) @[Cat.scala 30:58] + node _T_3431 = asUInt(_T_3373) @[Cat.scala 30:58] + node _T_3432 = cat(_T_3431, _T_3430) @[Cat.scala 30:58] + node _T_3433 = asUInt(_T_3365) @[Cat.scala 30:58] + node _T_3434 = asUInt(_T_3360) @[Cat.scala 30:58] + node _T_3435 = cat(_T_3434, _T_3433) @[Cat.scala 30:58] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 30:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 30:58] + node _T_3438 = asSInt(_T_3437) @[Rocket.scala 718:53] + node _T_3439 = add(_T_3353, _T_3438) @[Rocket.scala 184:35] + node _T_3440 = tail(_T_3439, 1) @[Rocket.scala 184:35] + node _T_3441 = asSInt(_T_3440) @[Rocket.scala 184:35] + node id_npc = asUInt(_T_3441) @[Rocket.scala 184:65] + node _T_3444 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 185:34] + node _T_3445 = and(UInt<1>("h00"), _T_3444) @[Rocket.scala 185:31] + node _T_3446 = and(_T_3445, id_ctrl.jal) @[Rocket.scala 185:46] + take_pc_id <= _T_3446 @[Rocket.scala 185:14] + inst csr of CSRFile @[Rocket.scala 187:19] + csr.io is invalid + csr.clock <= clock + csr.reset <= reset + node _T_3450 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47] + node _T_3451 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47] + node _T_3452 = eq(id_ctrl.csr, UInt<3>("h01")) @[Package.scala 7:47] + node _T_3453 = or(_T_3450, _T_3451) @[Package.scala 7:62] + node id_csr_en = or(_T_3453, _T_3452) @[Package.scala 7:62] + node id_system_insn = geq(id_ctrl.csr, UInt<3>("h04")) @[Rocket.scala 189:36] + node _T_3457 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47] + node _T_3458 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47] + node _T_3459 = or(_T_3457, _T_3458) @[Package.scala 7:62] + node _T_3461 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 190:67] + node id_csr_ren = and(_T_3459, _T_3461) @[Rocket.scala 190:54] + node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) @[Rocket.scala 191:19] + node _T_3464 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 192:54] + node _T_3465 = and(id_csr_en, _T_3464) @[Rocket.scala 192:51] + node _T_3466 = and(_T_3465, csr.io.decode.write_flush) @[Rocket.scala 192:66] + node id_csr_flush = or(id_system_insn, _T_3466) @[Rocket.scala 192:37] + node _T_3468 = eq(id_ctrl.legal, UInt<1>("h00")) @[Rocket.scala 194:25] + node _T_3469 = bits(csr.io.status.isa, 12, 12) @[Rocket.scala 195:38] + node _T_3471 = eq(_T_3469, UInt<1>("h00")) @[Rocket.scala 195:20] + node _T_3472 = and(id_ctrl.div, _T_3471) @[Rocket.scala 195:17] + node _T_3473 = or(_T_3468, _T_3472) @[Rocket.scala 194:40] + node _T_3474 = bits(csr.io.status.isa, 0, 0) @[Rocket.scala 196:38] + node _T_3476 = eq(_T_3474, UInt<1>("h00")) @[Rocket.scala 196:20] + node _T_3477 = and(id_ctrl.amo, _T_3476) @[Rocket.scala 196:17] + node _T_3478 = or(_T_3473, _T_3477) @[Rocket.scala 195:48] + node _T_3479 = or(csr.io.decode.fp_illegal, io.fpu.illegal_rm) @[Rocket.scala 197:45] + node _T_3480 = and(id_ctrl.fp, _T_3479) @[Rocket.scala 197:16] + node _T_3481 = or(_T_3478, _T_3480) @[Rocket.scala 196:48] + node _T_3482 = bits(csr.io.status.isa, 3, 3) @[Rocket.scala 198:37] + node _T_3484 = eq(_T_3482, UInt<1>("h00")) @[Rocket.scala 198:19] + node _T_3485 = and(id_ctrl.dp, _T_3484) @[Rocket.scala 198:16] + node _T_3486 = or(_T_3481, _T_3485) @[Rocket.scala 197:67] + node _T_3487 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 199:51] + node _T_3489 = eq(_T_3487, UInt<1>("h00")) @[Rocket.scala 199:33] + node _T_3490 = and(ibuf.io.inst[0].bits.rvc, _T_3489) @[Rocket.scala 199:30] + node _T_3491 = or(_T_3486, _T_3490) @[Rocket.scala 198:47] + node _T_3492 = and(id_ctrl.rocc, csr.io.decode.rocc_illegal) @[Rocket.scala 200:18] + node _T_3493 = or(_T_3491, _T_3492) @[Rocket.scala 199:61] + node _T_3495 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 201:49] + node _T_3496 = and(_T_3495, csr.io.decode.write_illegal) @[Rocket.scala 201:61] + node _T_3497 = or(csr.io.decode.read_illegal, _T_3496) @[Rocket.scala 201:46] + node _T_3498 = and(id_csr_en, _T_3497) @[Rocket.scala 201:15] + node _T_3499 = or(_T_3493, _T_3498) @[Rocket.scala 200:48] + node _T_3500 = and(id_system_insn, csr.io.decode.system_illegal) @[Rocket.scala 202:20] + node id_illegal_insn = or(_T_3499, _T_3500) @[Rocket.scala 201:93] + node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) @[Rocket.scala 204:29] + node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) @[Rocket.scala 205:29] + node _T_3501 = and(id_ctrl.amo, id_amo_rl) @[Rocket.scala 206:52] + node id_fence_next = or(id_ctrl.fence, _T_3501) @[Rocket.scala 206:37] + node _T_3503 = eq(io.dmem.ordered, UInt<1>("h00")) @[Rocket.scala 207:21] + node id_mem_busy = or(_T_3503, io.dmem.req.valid) @[Rocket.scala 207:38] + node _T_3505 = and(ex_reg_valid, ex_ctrl.rocc) @[Rocket.scala 209:35] + node _T_3506 = or(io.rocc.busy, _T_3505) @[Rocket.scala 209:19] + node _T_3507 = and(mem_reg_valid, mem_ctrl.rocc) @[Rocket.scala 210:20] + node _T_3508 = or(_T_3506, _T_3507) @[Rocket.scala 209:51] + node _T_3509 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 210:53] + node _T_3510 = or(_T_3508, _T_3509) @[Rocket.scala 210:37] + node id_rocc_busy = and(UInt<1>("h00"), _T_3510) @[Rocket.scala 208:38] + node _T_3511 = and(id_reg_fence, id_mem_busy) @[Rocket.scala 211:49] + node _T_3512 = or(id_fence_next, _T_3511) @[Rocket.scala 211:33] + id_reg_fence <= _T_3512 @[Rocket.scala 211:16] + node _T_3513 = and(id_rocc_busy, id_ctrl.fence) @[Rocket.scala 212:34] + node _T_3514 = and(id_ctrl.amo, id_amo_aq) @[Rocket.scala 213:33] + node _T_3515 = or(_T_3514, id_ctrl.fence_i) @[Rocket.scala 213:46] + node _T_3516 = or(id_ctrl.mem, id_ctrl.rocc) @[Rocket.scala 213:97] + node _T_3517 = and(id_reg_fence, _T_3516) @[Rocket.scala 213:81] + node _T_3518 = or(_T_3515, _T_3517) @[Rocket.scala 213:65] + node _T_3519 = and(id_mem_busy, _T_3518) @[Rocket.scala 213:17] + node id_do_fence = or(_T_3513, _T_3519) @[Rocket.scala 212:51] + inst bpu of BreakpointUnit @[Rocket.scala 215:19] + bpu.io is invalid + bpu.clock <= clock + bpu.reset <= reset + bpu.io.status <- csr.io.status @[Rocket.scala 216:17] + bpu.io.bp <- csr.io.bp @[Rocket.scala 217:13] + bpu.io.pc <= ibuf.io.pc @[Rocket.scala 218:13] + bpu.io.ea <= mem_reg_wdata @[Rocket.scala 219:13] + node id_xcpt_if = or(ibuf.io.inst[0].bits.pf0, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 221:45] + node _T_3552 = or(csr.io.interrupt, bpu.io.debug_if) @[Rocket.scala 645:26] + node _T_3553 = or(_T_3552, bpu.io.xcpt_if) @[Rocket.scala 645:26] + node _T_3554 = or(_T_3553, id_xcpt_if) @[Rocket.scala 645:26] + node id_xcpt = or(_T_3554, id_illegal_insn) @[Rocket.scala 645:26] + node _T_3555 = mux(id_xcpt_if, UInt<1>("h01"), UInt<2>("h02")) @[Mux.scala 31:69] + node _T_3556 = mux(bpu.io.xcpt_if, UInt<2>("h03"), _T_3555) @[Mux.scala 31:69] + node _T_3557 = mux(bpu.io.debug_if, UInt<4>("h0d"), _T_3556) @[Mux.scala 31:69] + node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_3557) @[Mux.scala 31:69] + node ex_waddr = bits(ex_reg_inst, 11, 7) @[Rocket.scala 235:29] + node mem_waddr = bits(mem_reg_inst, 11, 7) @[Rocket.scala 236:31] + node wb_waddr = bits(wb_reg_inst, 11, 7) @[Rocket.scala 237:29] + node _T_3561 = and(ex_reg_valid, ex_ctrl.wxd) @[Rocket.scala 240:19] + node _T_3562 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 241:20] + node _T_3564 = eq(mem_ctrl.mem, UInt<1>("h00")) @[Rocket.scala 241:39] + node _T_3565 = and(_T_3562, _T_3564) @[Rocket.scala 241:36] + node _T_3566 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 242:20] + node _T_3567 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_0 = and(UInt<1>("h01"), _T_3567) @[Rocket.scala 243:74] + node _T_3568 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_1 = and(_T_3561, _T_3568) @[Rocket.scala 243:74] + node _T_3569 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_2 = and(_T_3565, _T_3569) @[Rocket.scala 243:74] + node _T_3570 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_3 = and(_T_3566, _T_3570) @[Rocket.scala 243:74] + node _T_3571 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_0 = and(UInt<1>("h01"), _T_3571) @[Rocket.scala 243:74] + node _T_3572 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_1 = and(_T_3561, _T_3572) @[Rocket.scala 243:74] + node _T_3573 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_2 = and(_T_3565, _T_3573) @[Rocket.scala 243:74] + node _T_3574 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_3 = and(_T_3566, _T_3574) @[Rocket.scala 243:74] + wire bypass_mux : UInt[4] @[Rocket.scala 246:23] + bypass_mux is invalid @[Rocket.scala 246:23] + bypass_mux[0] <= UInt<1>("h00") @[Rocket.scala 246:23] + bypass_mux[1] <= mem_reg_wdata @[Rocket.scala 246:23] + bypass_mux[2] <= wb_reg_wdata @[Rocket.scala 246:23] + bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 246:23] + reg ex_reg_rs_bypass : UInt<1>[2], clock @[Rocket.scala 247:29] + reg ex_reg_rs_lsb : UInt<2>[2], clock @[Rocket.scala 248:26] + reg ex_reg_rs_msb : UInt[2], clock @[Rocket.scala 249:26] + node _T_3605 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) @[Cat.scala 30:58] + node ex_rs_0 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], _T_3605) @[Rocket.scala 251:14] + node _T_3607 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) @[Cat.scala 30:58] + node ex_rs_1 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], _T_3607) @[Rocket.scala 251:14] + node _T_3609 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3611 = bits(ex_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3612 = asSInt(_T_3611) @[Rocket.scala 704:53] + node _T_3613 = mux(_T_3609, asSInt(UInt<1>("h00")), _T_3612) @[Rocket.scala 704:19] + node _T_3615 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3616 = bits(ex_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3617 = asSInt(_T_3616) @[Rocket.scala 705:49] + node _T_3618 = mux(_T_3615, _T_3617, _T_3613) @[Rocket.scala 705:21] + node _T_3620 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3622 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3623 = and(_T_3620, _T_3622) @[Rocket.scala 706:36] + node _T_3624 = bits(ex_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3625 = asSInt(_T_3624) @[Rocket.scala 706:73] + node _T_3626 = mux(_T_3623, _T_3613, _T_3625) @[Rocket.scala 706:21] + node _T_3628 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3630 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3631 = or(_T_3628, _T_3630) @[Rocket.scala 707:33] + node _T_3634 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3635 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3636 = asSInt(_T_3635) @[Rocket.scala 708:44] + node _T_3638 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3639 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3640 = asSInt(_T_3639) @[Rocket.scala 709:43] + node _T_3641 = mux(_T_3638, _T_3640, _T_3613) @[Rocket.scala 709:18] + node _T_3642 = mux(_T_3634, _T_3636, _T_3641) @[Rocket.scala 708:18] + node _T_3643 = mux(_T_3631, asSInt(UInt<1>("h00")), _T_3642) @[Rocket.scala 707:18] + node _T_3645 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3647 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3648 = or(_T_3645, _T_3647) @[Rocket.scala 710:35] + node _T_3650 = bits(ex_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3651 = mux(_T_3648, UInt<1>("h00"), _T_3650) @[Rocket.scala 710:20] + node _T_3653 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3656 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3658 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3659 = or(_T_3656, _T_3658) @[Rocket.scala 712:34] + node _T_3660 = bits(ex_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3662 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3663 = bits(ex_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3664 = bits(ex_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3665 = mux(_T_3662, _T_3663, _T_3664) @[Rocket.scala 713:19] + node _T_3666 = mux(_T_3659, _T_3660, _T_3665) @[Rocket.scala 712:19] + node _T_3667 = mux(_T_3653, UInt<1>("h00"), _T_3666) @[Rocket.scala 711:19] + node _T_3669 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3670 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3672 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3673 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3675 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3676 = bits(ex_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3678 = mux(_T_3675, _T_3676, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3679 = mux(_T_3672, _T_3673, _T_3678) @[Rocket.scala 715:17] + node _T_3680 = mux(_T_3669, _T_3670, _T_3679) @[Rocket.scala 714:17] + node _T_3681 = cat(_T_3651, _T_3667) @[Cat.scala 30:58] + node _T_3682 = cat(_T_3681, _T_3680) @[Cat.scala 30:58] + node _T_3683 = asUInt(_T_3643) @[Cat.scala 30:58] + node _T_3684 = asUInt(_T_3626) @[Cat.scala 30:58] + node _T_3685 = cat(_T_3684, _T_3683) @[Cat.scala 30:58] + node _T_3686 = asUInt(_T_3618) @[Cat.scala 30:58] + node _T_3687 = asUInt(_T_3613) @[Cat.scala 30:58] + node _T_3688 = cat(_T_3687, _T_3686) @[Cat.scala 30:58] + node _T_3689 = cat(_T_3688, _T_3685) @[Cat.scala 30:58] + node _T_3690 = cat(_T_3689, _T_3682) @[Cat.scala 30:58] + node ex_imm = asSInt(_T_3690) @[Rocket.scala 718:53] + node _T_3693 = asSInt(ex_rs_0) @[Rocket.scala 254:24] + node _T_3695 = asSInt(ex_reg_pc) @[Rocket.scala 255:24] + node _T_3696 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] + node _T_3697 = mux(_T_3696, _T_3695, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] + node _T_3698 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] + node ex_op1 = mux(_T_3698, _T_3693, _T_3697) @[Mux.scala 46:16] + node _T_3701 = asSInt(ex_rs_1) @[Rocket.scala 257:24] + node _T_3706 = mux(ex_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 259:19] + node _T_3707 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node _T_3708 = mux(_T_3707, _T_3706, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] + node _T_3709 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node _T_3710 = mux(_T_3709, ex_imm, _T_3708) @[Mux.scala 46:16] + node _T_3711 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node ex_op2 = mux(_T_3711, _T_3701, _T_3710) @[Mux.scala 46:16] + inst alu of ALU @[Rocket.scala 261:19] + alu.io is invalid + alu.clock <= clock + alu.reset <= reset + alu.io.dw <= ex_ctrl.alu_dw @[Rocket.scala 262:13] + alu.io.fn <= ex_ctrl.alu_fn @[Rocket.scala 263:13] + node _T_3712 = asUInt(ex_op2) @[Rocket.scala 264:24] + alu.io.in2 <= _T_3712 @[Rocket.scala 264:14] + node _T_3713 = asUInt(ex_op1) @[Rocket.scala 265:24] + alu.io.in1 <= _T_3713 @[Rocket.scala 265:14] + inst div of MulDiv @[Rocket.scala 268:19] + div.io is invalid + div.clock <= clock + div.reset <= reset + node _T_3714 = and(ex_reg_valid, ex_ctrl.div) @[Rocket.scala 269:36] + div.io.req.valid <= _T_3714 @[Rocket.scala 269:20] + div.io.req.bits.dw <= ex_ctrl.alu_dw @[Rocket.scala 270:22] + div.io.req.bits.fn <= ex_ctrl.alu_fn @[Rocket.scala 271:22] + div.io.req.bits.in1 <= ex_rs_0 @[Rocket.scala 272:23] + div.io.req.bits.in2 <= ex_rs_1 @[Rocket.scala 273:23] + div.io.req.bits.tag <= ex_waddr @[Rocket.scala 274:23] + node _T_3716 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 276:19] + ex_reg_valid <= _T_3716 @[Rocket.scala 276:16] + node _T_3718 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 277:20] + node _T_3719 = and(_T_3718, ibuf.io.inst[0].valid) @[Rocket.scala 277:29] + node _T_3720 = and(_T_3719, ibuf.io.inst[0].bits.replay) @[Rocket.scala 277:54] + ex_reg_replay <= _T_3720 @[Rocket.scala 277:17] + node _T_3722 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 278:18] + node _T_3723 = and(_T_3722, id_xcpt) @[Rocket.scala 278:30] + ex_reg_xcpt <= _T_3723 @[Rocket.scala 278:15] + node _T_3725 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 279:28] + node _T_3726 = and(_T_3725, ibuf.io.inst[0].valid) @[Rocket.scala 279:37] + node _T_3727 = and(_T_3726, csr.io.interrupt) @[Rocket.scala 279:62] + ex_reg_xcpt_interrupt <= _T_3727 @[Rocket.scala 279:25] + when id_xcpt : @[Rocket.scala 280:18] + ex_cause <= id_cause @[Rocket.scala 280:33] + skip @[Rocket.scala 280:18] + ex_reg_btb_hit <= ibuf.io.inst[0].bits.btb_hit @[Rocket.scala 281:18] + when ibuf.io.inst[0].bits.btb_hit : @[Rocket.scala 282:39] + ex_reg_btb_resp <- ibuf.io.btb_resp @[Rocket.scala 282:57] + skip @[Rocket.scala 282:39] + node _T_3729 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 284:9] + when _T_3729 : @[Rocket.scala 284:22] + ex_ctrl <- id_ctrl @[Rocket.scala 285:13] + ex_reg_rvc <= ibuf.io.inst[0].bits.rvc @[Rocket.scala 286:16] + ex_ctrl.csr <= id_csr @[Rocket.scala 287:17] + when id_xcpt : @[Rocket.scala 288:20] + ex_ctrl.alu_fn <= UInt<1>("h00") @[Rocket.scala 289:22] + ex_ctrl.alu_dw <= UInt<1>("h01") @[Rocket.scala 290:22] + ex_ctrl.sel_alu1 <= UInt<2>("h02") @[Rocket.scala 291:24] + ex_ctrl.sel_alu2 <= UInt<2>("h00") @[Rocket.scala 292:24] + node _T_3735 = eq(bpu.io.xcpt_if, UInt<1>("h00")) @[Rocket.scala 293:13] + node _T_3737 = eq(ibuf.io.inst[0].bits.pf0, UInt<1>("h00")) @[Rocket.scala 293:32] + node _T_3738 = and(_T_3735, _T_3737) @[Rocket.scala 293:29] + node _T_3739 = and(_T_3738, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 293:58] + when _T_3739 : @[Rocket.scala 293:87] + ex_ctrl.sel_alu2 <= UInt<2>("h01") @[Rocket.scala 294:26] + ex_reg_rvc <= UInt<1>("h01") @[Rocket.scala 295:20] + skip @[Rocket.scala 293:87] + skip @[Rocket.scala 288:20] + node _T_3742 = or(id_ctrl.fence_i, id_csr_flush) @[Rocket.scala 298:42] + node _T_3743 = or(_T_3742, csr.io.singleStep) @[Rocket.scala 298:58] + ex_reg_flush_pipe <= _T_3743 @[Rocket.scala 298:23] + ex_reg_load_use <= id_load_use @[Rocket.scala 299:21] + node _T_3744 = and(id_ctrl.jalr, csr.io.status.debug) @[Rocket.scala 301:24] + when _T_3744 : @[Rocket.scala 301:48] + ex_reg_flush_pipe <= UInt<1>("h01") @[Rocket.scala 302:25] + ex_ctrl.fence_i <= UInt<1>("h01") @[Rocket.scala 303:23] + skip @[Rocket.scala 301:48] + node _T_3747 = or(id_bypass_src_0_0, id_bypass_src_0_1) @[Rocket.scala 307:48] + node _T_3748 = or(_T_3747, id_bypass_src_0_2) @[Rocket.scala 307:48] + node _T_3749 = or(_T_3748, id_bypass_src_0_3) @[Rocket.scala 307:48] + node _T_3754 = mux(id_bypass_src_0_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] + node _T_3755 = mux(id_bypass_src_0_1, UInt<1>("h01"), _T_3754) @[Mux.scala 31:69] + node _T_3756 = mux(id_bypass_src_0_0, UInt<1>("h00"), _T_3755) @[Mux.scala 31:69] + ex_reg_rs_bypass[0] <= _T_3749 @[Rocket.scala 309:27] + ex_reg_rs_lsb[0] <= _T_3756 @[Rocket.scala 310:24] + node _T_3758 = eq(_T_3749, UInt<1>("h00")) @[Rocket.scala 311:26] + node _T_3759 = and(id_ctrl.rxs1, _T_3758) @[Rocket.scala 311:23] + when _T_3759 : @[Rocket.scala 311:38] + node _T_3760 = bits(id_rs_0, 1, 0) @[Rocket.scala 312:37] + ex_reg_rs_lsb[0] <= _T_3760 @[Rocket.scala 312:26] + node _T_3761 = shr(id_rs_0, 2) @[Rocket.scala 313:38] + ex_reg_rs_msb[0] <= _T_3761 @[Rocket.scala 313:26] + skip @[Rocket.scala 311:38] + node _T_3762 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[Rocket.scala 307:48] + node _T_3763 = or(_T_3762, id_bypass_src_1_2) @[Rocket.scala 307:48] + node _T_3764 = or(_T_3763, id_bypass_src_1_3) @[Rocket.scala 307:48] + node _T_3769 = mux(id_bypass_src_1_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] + node _T_3770 = mux(id_bypass_src_1_1, UInt<1>("h01"), _T_3769) @[Mux.scala 31:69] + node _T_3771 = mux(id_bypass_src_1_0, UInt<1>("h00"), _T_3770) @[Mux.scala 31:69] + ex_reg_rs_bypass[1] <= _T_3764 @[Rocket.scala 309:27] + ex_reg_rs_lsb[1] <= _T_3771 @[Rocket.scala 310:24] + node _T_3773 = eq(_T_3764, UInt<1>("h00")) @[Rocket.scala 311:26] + node _T_3774 = and(id_ctrl.rxs2, _T_3773) @[Rocket.scala 311:23] + when _T_3774 : @[Rocket.scala 311:38] + node _T_3775 = bits(id_rs_1, 1, 0) @[Rocket.scala 312:37] + ex_reg_rs_lsb[1] <= _T_3775 @[Rocket.scala 312:26] + node _T_3776 = shr(id_rs_1, 2) @[Rocket.scala 313:38] + ex_reg_rs_msb[1] <= _T_3776 @[Rocket.scala 313:26] + skip @[Rocket.scala 311:38] + skip @[Rocket.scala 284:22] + node _T_3778 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 317:9] + node _T_3779 = or(_T_3778, csr.io.interrupt) @[Rocket.scala 317:21] + node _T_3780 = or(_T_3779, ibuf.io.inst[0].bits.replay) @[Rocket.scala 317:41] + when _T_3780 : @[Rocket.scala 317:73] + ex_reg_inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 318:17] + ex_reg_pc <= ibuf.io.pc @[Rocket.scala 319:15] + skip @[Rocket.scala 317:73] + node _T_3781 = or(ex_reg_valid, ex_reg_replay) @[Rocket.scala 323:34] + node ex_pc_valid = or(_T_3781, ex_reg_xcpt_interrupt) @[Rocket.scala 323:51] + node _T_3783 = eq(io.dmem.resp.valid, UInt<1>("h00")) @[Rocket.scala 324:39] + node wb_dcache_miss = and(wb_ctrl.mem, _T_3783) @[Rocket.scala 324:36] + node _T_3785 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 325:45] + node _T_3786 = and(ex_ctrl.mem, _T_3785) @[Rocket.scala 325:42] + node _T_3788 = eq(div.io.req.ready, UInt<1>("h00")) @[Rocket.scala 326:45] + node _T_3789 = and(ex_ctrl.div, _T_3788) @[Rocket.scala 326:42] + node replay_ex_structural = or(_T_3786, _T_3789) @[Rocket.scala 325:64] + node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[Rocket.scala 327:43] + node _T_3790 = or(replay_ex_structural, replay_ex_load_use) @[Rocket.scala 328:75] + node _T_3791 = and(ex_reg_valid, _T_3790) @[Rocket.scala 328:50] + node replay_ex = or(ex_reg_replay, _T_3791) @[Rocket.scala 328:33] + node _T_3792 = or(take_pc_mem_wb, replay_ex) @[Rocket.scala 329:35] + node _T_3794 = eq(ex_reg_valid, UInt<1>("h00")) @[Rocket.scala 329:51] + node ctrl_killx = or(_T_3792, _T_3794) @[Rocket.scala 329:48] + node _T_3796 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Rocket.scala 331:40] + wire _T_3803 : UInt<3>[4] @[Rocket.scala 331:56] + _T_3803 is invalid @[Rocket.scala 331:56] + _T_3803[0] <= UInt<1>("h00") @[Rocket.scala 331:56] + _T_3803[1] <= UInt<3>("h04") @[Rocket.scala 331:56] + _T_3803[2] <= UInt<1>("h01") @[Rocket.scala 331:56] + _T_3803[3] <= UInt<3>("h05") @[Rocket.scala 331:56] + node _T_3810 = eq(_T_3803[0], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3811 = eq(_T_3803[1], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3812 = eq(_T_3803[2], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3813 = eq(_T_3803[3], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3815 = or(UInt<1>("h00"), _T_3810) @[Rocket.scala 331:91] + node _T_3816 = or(_T_3815, _T_3811) @[Rocket.scala 331:91] + node _T_3817 = or(_T_3816, _T_3812) @[Rocket.scala 331:91] + node _T_3818 = or(_T_3817, _T_3813) @[Rocket.scala 331:91] + node ex_slow_bypass = or(_T_3796, _T_3818) @[Rocket.scala 331:50] + node ex_xcpt = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[Rocket.scala 334:28] + node _T_3819 = or(mem_reg_valid, mem_reg_replay) @[Rocket.scala 337:36] + node mem_pc_valid = or(_T_3819, mem_reg_xcpt_interrupt) @[Rocket.scala 337:54] + node mem_br_taken = bits(mem_reg_wdata, 0, 0) @[Rocket.scala 338:35] + node _T_3820 = asSInt(mem_reg_pc) @[Rocket.scala 339:34] + node _T_3821 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 340:25] + node _T_3824 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3826 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3827 = asSInt(_T_3826) @[Rocket.scala 704:53] + node _T_3828 = mux(_T_3824, asSInt(UInt<1>("h00")), _T_3827) @[Rocket.scala 704:19] + node _T_3830 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3831 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3832 = asSInt(_T_3831) @[Rocket.scala 705:49] + node _T_3833 = mux(_T_3830, _T_3832, _T_3828) @[Rocket.scala 705:21] + node _T_3835 = neq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3837 = neq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3838 = and(_T_3835, _T_3837) @[Rocket.scala 706:36] + node _T_3839 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3840 = asSInt(_T_3839) @[Rocket.scala 706:73] + node _T_3841 = mux(_T_3838, _T_3828, _T_3840) @[Rocket.scala 706:21] + node _T_3843 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3845 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3846 = or(_T_3843, _T_3845) @[Rocket.scala 707:33] + node _T_3849 = eq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3850 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3851 = asSInt(_T_3850) @[Rocket.scala 708:44] + node _T_3853 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3854 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3855 = asSInt(_T_3854) @[Rocket.scala 709:43] + node _T_3856 = mux(_T_3853, _T_3855, _T_3828) @[Rocket.scala 709:18] + node _T_3857 = mux(_T_3849, _T_3851, _T_3856) @[Rocket.scala 708:18] + node _T_3858 = mux(_T_3846, asSInt(UInt<1>("h00")), _T_3857) @[Rocket.scala 707:18] + node _T_3860 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3862 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3863 = or(_T_3860, _T_3862) @[Rocket.scala 710:35] + node _T_3865 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3866 = mux(_T_3863, UInt<1>("h00"), _T_3865) @[Rocket.scala 710:20] + node _T_3868 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3871 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3873 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3874 = or(_T_3871, _T_3873) @[Rocket.scala 712:34] + node _T_3875 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3877 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3878 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3879 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3880 = mux(_T_3877, _T_3878, _T_3879) @[Rocket.scala 713:19] + node _T_3881 = mux(_T_3874, _T_3875, _T_3880) @[Rocket.scala 712:19] + node _T_3882 = mux(_T_3868, UInt<1>("h00"), _T_3881) @[Rocket.scala 711:19] + node _T_3884 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3885 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3887 = eq(UInt<3>("h01"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3888 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3890 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3891 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3893 = mux(_T_3890, _T_3891, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3894 = mux(_T_3887, _T_3888, _T_3893) @[Rocket.scala 715:17] + node _T_3895 = mux(_T_3884, _T_3885, _T_3894) @[Rocket.scala 714:17] + node _T_3896 = cat(_T_3866, _T_3882) @[Cat.scala 30:58] + node _T_3897 = cat(_T_3896, _T_3895) @[Cat.scala 30:58] + node _T_3898 = asUInt(_T_3858) @[Cat.scala 30:58] + node _T_3899 = asUInt(_T_3841) @[Cat.scala 30:58] + node _T_3900 = cat(_T_3899, _T_3898) @[Cat.scala 30:58] + node _T_3901 = asUInt(_T_3833) @[Cat.scala 30:58] + node _T_3902 = asUInt(_T_3828) @[Cat.scala 30:58] + node _T_3903 = cat(_T_3902, _T_3901) @[Cat.scala 30:58] + node _T_3904 = cat(_T_3903, _T_3900) @[Cat.scala 30:58] + node _T_3905 = cat(_T_3904, _T_3897) @[Cat.scala 30:58] + node _T_3906 = asSInt(_T_3905) @[Rocket.scala 718:53] + node _T_3908 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 341:24] + node _T_3911 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3913 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3914 = asSInt(_T_3913) @[Rocket.scala 704:53] + node _T_3915 = mux(_T_3911, asSInt(UInt<1>("h00")), _T_3914) @[Rocket.scala 704:19] + node _T_3917 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3918 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3919 = asSInt(_T_3918) @[Rocket.scala 705:49] + node _T_3920 = mux(_T_3917, _T_3919, _T_3915) @[Rocket.scala 705:21] + node _T_3922 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3924 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3925 = and(_T_3922, _T_3924) @[Rocket.scala 706:36] + node _T_3926 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3927 = asSInt(_T_3926) @[Rocket.scala 706:73] + node _T_3928 = mux(_T_3925, _T_3915, _T_3927) @[Rocket.scala 706:21] + node _T_3930 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3932 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3933 = or(_T_3930, _T_3932) @[Rocket.scala 707:33] + node _T_3936 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3937 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3938 = asSInt(_T_3937) @[Rocket.scala 708:44] + node _T_3940 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3941 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3942 = asSInt(_T_3941) @[Rocket.scala 709:43] + node _T_3943 = mux(_T_3940, _T_3942, _T_3915) @[Rocket.scala 709:18] + node _T_3944 = mux(_T_3936, _T_3938, _T_3943) @[Rocket.scala 708:18] + node _T_3945 = mux(_T_3933, asSInt(UInt<1>("h00")), _T_3944) @[Rocket.scala 707:18] + node _T_3947 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3949 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3950 = or(_T_3947, _T_3949) @[Rocket.scala 710:35] + node _T_3952 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3953 = mux(_T_3950, UInt<1>("h00"), _T_3952) @[Rocket.scala 710:20] + node _T_3955 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3958 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3960 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3961 = or(_T_3958, _T_3960) @[Rocket.scala 712:34] + node _T_3962 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3964 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3965 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3966 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3967 = mux(_T_3964, _T_3965, _T_3966) @[Rocket.scala 713:19] + node _T_3968 = mux(_T_3961, _T_3962, _T_3967) @[Rocket.scala 712:19] + node _T_3969 = mux(_T_3955, UInt<1>("h00"), _T_3968) @[Rocket.scala 711:19] + node _T_3971 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3972 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3974 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3975 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3977 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3978 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3980 = mux(_T_3977, _T_3978, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3981 = mux(_T_3974, _T_3975, _T_3980) @[Rocket.scala 715:17] + node _T_3982 = mux(_T_3971, _T_3972, _T_3981) @[Rocket.scala 714:17] + node _T_3983 = cat(_T_3953, _T_3969) @[Cat.scala 30:58] + node _T_3984 = cat(_T_3983, _T_3982) @[Cat.scala 30:58] + node _T_3985 = asUInt(_T_3945) @[Cat.scala 30:58] + node _T_3986 = asUInt(_T_3928) @[Cat.scala 30:58] + node _T_3987 = cat(_T_3986, _T_3985) @[Cat.scala 30:58] + node _T_3988 = asUInt(_T_3920) @[Cat.scala 30:58] + node _T_3989 = asUInt(_T_3915) @[Cat.scala 30:58] + node _T_3990 = cat(_T_3989, _T_3988) @[Cat.scala 30:58] + node _T_3991 = cat(_T_3990, _T_3987) @[Cat.scala 30:58] + node _T_3992 = cat(_T_3991, _T_3984) @[Cat.scala 30:58] + node _T_3993 = asSInt(_T_3992) @[Rocket.scala 718:53] + node _T_3996 = mux(mem_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 342:8] + node _T_3997 = mux(_T_3908, _T_3993, _T_3996) @[Rocket.scala 341:8] + node _T_3998 = mux(_T_3821, _T_3906, _T_3997) @[Rocket.scala 340:8] + node _T_3999 = add(_T_3820, _T_3998) @[Rocket.scala 339:41] + node _T_4000 = tail(_T_3999, 1) @[Rocket.scala 339:41] + node mem_br_target = asSInt(_T_4000) @[Rocket.scala 339:41] + node _T_4001 = shr(mem_reg_wdata, 38) @[Rocket.scala 653:16] + node _T_4002 = bits(mem_reg_wdata, 39, 38) @[Rocket.scala 654:15] + node _T_4003 = asSInt(_T_4002) @[Rocket.scala 654:39] + node _T_4005 = eq(_T_4001, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4007 = eq(_T_4001, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4008 = or(_T_4005, _T_4007) @[Rocket.scala 656:25] + node _T_4010 = neq(_T_4003, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4011 = asSInt(_T_4001) @[Rocket.scala 657:13] + node _T_4013 = eq(_T_4011, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4014 = asSInt(_T_4001) @[Rocket.scala 657:38] + node _T_4016 = eq(_T_4014, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4017 = or(_T_4013, _T_4016) @[Rocket.scala 657:33] + node _T_4019 = eq(_T_4003, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4020 = bits(_T_4003, 0, 0) @[Rocket.scala 657:76] + node _T_4021 = mux(_T_4017, _T_4019, _T_4020) @[Rocket.scala 657:10] + node _T_4022 = mux(_T_4008, _T_4010, _T_4021) @[Rocket.scala 656:10] + node _T_4023 = bits(mem_reg_wdata, 38, 0) @[Rocket.scala 658:16] + node _T_4024 = cat(_T_4022, _T_4023) @[Cat.scala 30:58] + node _T_4025 = asSInt(_T_4024) @[Rocket.scala 343:88] + node _T_4026 = mux(mem_ctrl.jalr, _T_4025, mem_br_target) @[Rocket.scala 343:21] + node _T_4028 = and(_T_4026, asSInt(UInt<2>("h02"))) @[Rocket.scala 343:111] + node _T_4029 = asSInt(_T_4028) @[Rocket.scala 343:111] + node mem_npc = asUInt(_T_4029) @[Rocket.scala 343:123] + node _T_4030 = neq(mem_npc, ex_reg_pc) @[Rocket.scala 344:48] + node _T_4031 = neq(mem_npc, ibuf.io.pc) @[Rocket.scala 344:98] + node _T_4033 = mux(ibuf.io.inst[0].valid, _T_4031, UInt<1>("h01")) @[Rocket.scala 344:66] + node mem_misprediction = mux(ex_pc_valid, _T_4030, _T_4033) @[Rocket.scala 344:26] + node _T_4034 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 345:46] + node _T_4036 = eq(_T_4034, UInt<1>("h00")) @[Rocket.scala 345:28] + node _T_4037 = bits(mem_npc, 1, 1) @[Rocket.scala 345:66] + node mem_npc_misaligned = and(_T_4036, _T_4037) @[Rocket.scala 345:56] + node _T_4039 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 346:27] + node _T_4040 = xor(mem_ctrl.jalr, mem_npc_misaligned) @[Rocket.scala 346:59] + node _T_4041 = and(_T_4039, _T_4040) @[Rocket.scala 346:41] + node _T_4042 = asSInt(mem_reg_wdata) @[Rocket.scala 346:111] + node _T_4043 = mux(_T_4041, mem_br_target, _T_4042) @[Rocket.scala 346:26] + node mem_int_wdata = asUInt(_T_4043) @[Rocket.scala 346:119] + node _T_4044 = or(mem_ctrl.branch, mem_ctrl.jalr) @[Rocket.scala 347:33] + node mem_cfi = or(_T_4044, mem_ctrl.jal) @[Rocket.scala 347:50] + node _T_4045 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 348:40] + node _T_4046 = or(_T_4045, mem_ctrl.jalr) @[Rocket.scala 348:57] + node _T_4048 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 348:93] + node mem_cfi_taken = or(_T_4046, _T_4048) @[Rocket.scala 348:74] + node _T_4049 = and(mem_reg_btb_hit, mem_ctrl.branch) @[Rocket.scala 349:53] + node _T_4050 = neq(mem_br_taken, mem_reg_btb_resp.taken) @[Rocket.scala 349:88] + node mem_direction_misprediction = and(_T_4049, _T_4050) @[Rocket.scala 349:72] + node _T_4051 = or(mem_misprediction, mem_reg_flush_pipe) @[Rocket.scala 351:54] + node _T_4052 = and(mem_reg_valid, _T_4051) @[Rocket.scala 351:32] + take_pc_mem <= _T_4052 @[Rocket.scala 351:15] + node _T_4054 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 353:20] + mem_reg_valid <= _T_4054 @[Rocket.scala 353:17] + node _T_4056 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 354:21] + node _T_4057 = and(_T_4056, replay_ex) @[Rocket.scala 354:37] + mem_reg_replay <= _T_4057 @[Rocket.scala 354:18] + node _T_4059 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 355:19] + node _T_4060 = and(_T_4059, ex_xcpt) @[Rocket.scala 355:31] + mem_reg_xcpt <= _T_4060 @[Rocket.scala 355:16] + node _T_4062 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 356:29] + node _T_4063 = and(_T_4062, ex_reg_xcpt_interrupt) @[Rocket.scala 356:45] + mem_reg_xcpt_interrupt <= _T_4063 @[Rocket.scala 356:26] + when ex_xcpt : @[Rocket.scala 357:18] + mem_reg_cause <= ex_cause @[Rocket.scala 357:34] + skip @[Rocket.scala 357:18] + when ex_pc_valid : @[Rocket.scala 359:22] + mem_ctrl <- ex_ctrl @[Rocket.scala 360:14] + mem_reg_rvc <= ex_reg_rvc @[Rocket.scala 361:17] + node _T_4065 = eq(ex_ctrl.mem_cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_4067 = eq(ex_ctrl.mem_cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_4068 = or(_T_4065, _T_4067) @[Consts.scala 35:41] + node _T_4070 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_4071 = or(_T_4068, _T_4070) @[Consts.scala 35:58] + node _T_4072 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] + node _T_4074 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_4075 = or(_T_4072, _T_4074) @[Consts.scala 33:33] + node _T_4076 = or(_T_4071, _T_4075) @[Consts.scala 35:75] + node _T_4077 = and(ex_ctrl.mem, _T_4076) @[Rocket.scala 362:33] + mem_reg_load <= _T_4077 @[Rocket.scala 362:18] + node _T_4079 = eq(ex_ctrl.mem_cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_4081 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_4082 = or(_T_4079, _T_4081) @[Consts.scala 36:42] + node _T_4083 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] + node _T_4085 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_4086 = or(_T_4083, _T_4085) @[Consts.scala 33:33] + node _T_4087 = or(_T_4082, _T_4086) @[Consts.scala 36:59] + node _T_4088 = and(ex_ctrl.mem, _T_4087) @[Rocket.scala 363:34] + mem_reg_store <= _T_4088 @[Rocket.scala 363:19] + mem_reg_btb_hit <= ex_reg_btb_hit @[Rocket.scala 364:21] + when ex_reg_btb_hit : @[Rocket.scala 365:27] + mem_reg_btb_resp <- ex_reg_btb_resp @[Rocket.scala 365:46] + skip @[Rocket.scala 365:27] + mem_reg_flush_pipe <= ex_reg_flush_pipe @[Rocket.scala 366:24] + mem_reg_slow_bypass <= ex_slow_bypass @[Rocket.scala 367:25] + mem_reg_inst <= ex_reg_inst @[Rocket.scala 369:18] + mem_reg_pc <= ex_reg_pc @[Rocket.scala 370:16] + mem_reg_wdata <= alu.io.out @[Rocket.scala 371:19] + node _T_4089 = or(ex_ctrl.mem, ex_ctrl.rocc) @[Rocket.scala 372:40] + node _T_4090 = and(ex_ctrl.rxs2, _T_4089) @[Rocket.scala 372:24] + when _T_4090 : @[Rocket.scala 372:58] + mem_reg_rs2 <= ex_rs_1 @[Rocket.scala 373:19] + skip @[Rocket.scala 372:58] + skip @[Rocket.scala 359:22] + node _T_4091 = and(mem_reg_load, bpu.io.xcpt_ld) @[Rocket.scala 377:38] + node _T_4092 = and(mem_reg_store, bpu.io.xcpt_st) @[Rocket.scala 377:75] + node mem_breakpoint = or(_T_4091, _T_4092) @[Rocket.scala 377:57] + node _T_4093 = and(mem_reg_load, bpu.io.debug_ld) @[Rocket.scala 378:44] + node _T_4094 = and(mem_reg_store, bpu.io.debug_st) @[Rocket.scala 378:82] + node mem_debug_breakpoint = or(_T_4093, _T_4094) @[Rocket.scala 378:64] + node _T_4126 = and(mem_ctrl.mem, io.dmem.xcpt.ma.st) @[Rocket.scala 383:19] + node _T_4128 = and(mem_ctrl.mem, io.dmem.xcpt.ma.ld) @[Rocket.scala 384:19] + node _T_4130 = and(mem_ctrl.mem, io.dmem.xcpt.pf.st) @[Rocket.scala 385:19] + node _T_4132 = and(mem_ctrl.mem, io.dmem.xcpt.pf.ld) @[Rocket.scala 386:19] + node _T_4134 = or(mem_debug_breakpoint, mem_breakpoint) @[Rocket.scala 645:26] + node _T_4135 = or(_T_4134, mem_npc_misaligned) @[Rocket.scala 645:26] + node _T_4136 = or(_T_4135, _T_4126) @[Rocket.scala 645:26] + node _T_4137 = or(_T_4136, _T_4128) @[Rocket.scala 645:26] + node _T_4138 = or(_T_4137, _T_4130) @[Rocket.scala 645:26] + node mem_new_xcpt = or(_T_4138, _T_4132) @[Rocket.scala 645:26] + node _T_4139 = mux(_T_4130, UInt<3>("h07"), UInt<3>("h05")) @[Mux.scala 31:69] + node _T_4140 = mux(_T_4128, UInt<3>("h04"), _T_4139) @[Mux.scala 31:69] + node _T_4141 = mux(_T_4126, UInt<3>("h06"), _T_4140) @[Mux.scala 31:69] + node _T_4142 = mux(mem_npc_misaligned, UInt<1>("h00"), _T_4141) @[Mux.scala 31:69] + node _T_4143 = mux(mem_breakpoint, UInt<2>("h03"), _T_4142) @[Mux.scala 31:69] + node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("h0d"), _T_4143) @[Mux.scala 31:69] + node _T_4144 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[Rocket.scala 389:29] + node _T_4145 = and(mem_reg_valid, mem_new_xcpt) @[Rocket.scala 390:20] + node mem_xcpt = or(_T_4144, _T_4145) @[Rocket.scala 645:26] + node mem_cause = mux(_T_4144, mem_reg_cause, mem_new_cause) @[Mux.scala 31:69] + node _T_4146 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 392:39] + node dcache_kill_mem = and(_T_4146, io.dmem.replay_next) @[Rocket.scala 392:55] + node _T_4147 = and(mem_reg_valid, mem_ctrl.fp) @[Rocket.scala 393:36] + node fpu_kill_mem = and(_T_4147, io.fpu.nack_mem) @[Rocket.scala 393:51] + node _T_4148 = or(dcache_kill_mem, mem_reg_replay) @[Rocket.scala 394:37] + node replay_mem = or(_T_4148, fpu_kill_mem) @[Rocket.scala 394:55] + node _T_4149 = or(dcache_kill_mem, take_pc_wb) @[Rocket.scala 395:38] + node _T_4150 = or(_T_4149, mem_reg_xcpt) @[Rocket.scala 395:52] + node _T_4152 = eq(mem_reg_valid, UInt<1>("h00")) @[Rocket.scala 395:71] + node killm_common = or(_T_4150, _T_4152) @[Rocket.scala 395:68] + node _T_4153 = and(div.io.req.ready, div.io.req.valid) @[Decoupled.scala 30:37] + reg _T_4154 : UInt<1>, clock @[Rocket.scala 396:37] + _T_4154 <= _T_4153 @[Rocket.scala 396:37] + node _T_4155 = and(killm_common, _T_4154) @[Rocket.scala 396:31] + div.io.kill <= _T_4155 @[Rocket.scala 396:15] + node _T_4156 = or(killm_common, mem_xcpt) @[Rocket.scala 397:33] + node ctrl_killm = or(_T_4156, fpu_kill_mem) @[Rocket.scala 397:45] + node _T_4158 = eq(ctrl_killm, UInt<1>("h00")) @[Rocket.scala 400:19] + wb_reg_valid <= _T_4158 @[Rocket.scala 400:16] + node _T_4160 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 401:34] + node _T_4161 = and(replay_mem, _T_4160) @[Rocket.scala 401:31] + wb_reg_replay <= _T_4161 @[Rocket.scala 401:17] + node _T_4163 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 402:30] + node _T_4164 = and(mem_xcpt, _T_4163) @[Rocket.scala 402:27] + wb_reg_xcpt <= _T_4164 @[Rocket.scala 402:15] + when mem_xcpt : @[Rocket.scala 403:19] + wb_reg_cause <= mem_cause @[Rocket.scala 403:34] + skip @[Rocket.scala 403:19] + when mem_pc_valid : @[Rocket.scala 404:23] + wb_ctrl <- mem_ctrl @[Rocket.scala 405:13] + node _T_4166 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 406:25] + node _T_4167 = and(_T_4166, mem_ctrl.fp) @[Rocket.scala 406:39] + node _T_4168 = and(_T_4167, mem_ctrl.wxd) @[Rocket.scala 406:54] + node _T_4169 = mux(_T_4168, io.fpu.toint_data, mem_int_wdata) @[Rocket.scala 406:24] + wb_reg_wdata <= _T_4169 @[Rocket.scala 406:18] + when mem_ctrl.rocc : @[Rocket.scala 407:26] + wb_reg_rs2 <= mem_reg_rs2 @[Rocket.scala 408:18] + skip @[Rocket.scala 407:26] + wb_reg_inst <= mem_reg_inst @[Rocket.scala 410:17] + wb_reg_pc <= mem_reg_pc @[Rocket.scala 411:15] + skip @[Rocket.scala 404:23] + node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd) @[Rocket.scala 414:29] + node _T_4170 = or(wb_ctrl.div, wb_dcache_miss) @[Rocket.scala 415:35] + node wb_set_sboard = or(_T_4170, wb_ctrl.rocc) @[Rocket.scala 415:53] + node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) @[Rocket.scala 416:42] + node _T_4171 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 417:37] + node _T_4173 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 417:56] + node replay_wb_rocc = and(_T_4171, _T_4173) @[Rocket.scala 417:53] + node replay_wb = or(replay_wb_common, replay_wb_rocc) @[Rocket.scala 418:36] + node _T_4174 = or(replay_wb, wb_reg_xcpt) @[Rocket.scala 420:27] + node _T_4175 = or(_T_4174, csr.io.eret) @[Rocket.scala 420:38] + take_pc_wb <= _T_4175 @[Rocket.scala 420:14] + node _T_4176 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 423:45] + node _T_4177 = bits(_T_4176, 0, 0) @[Rocket.scala 423:49] + node dmem_resp_xpu = eq(_T_4177, UInt<1>("h00")) @[Rocket.scala 423:23] + node _T_4179 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 424:45] + node dmem_resp_fpu = bits(_T_4179, 0, 0) @[Rocket.scala 424:49] + node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) @[Rocket.scala 425:46] + node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) @[Rocket.scala 426:44] + node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) @[Rocket.scala 427:42] + node _T_4181 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 429:24] + div.io.resp.ready <= _T_4181 @[Rocket.scala 429:21] + wire ll_wdata : UInt + ll_wdata is invalid + ll_wdata <= div.io.resp.bits.data + wire ll_waddr : UInt + ll_waddr is invalid + ll_waddr <= div.io.resp.bits.tag + node _T_4182 = and(div.io.resp.ready, div.io.resp.valid) @[Decoupled.scala 30:37] + wire ll_wen : UInt<1> + ll_wen is invalid + ll_wen <= _T_4182 + node _T_4183 = and(dmem_resp_replay, dmem_resp_xpu) @[Rocket.scala 442:26] + when _T_4183 : @[Rocket.scala 442:44] + div.io.resp.ready <= UInt<1>("h00") @[Rocket.scala 443:23] + ll_waddr <= dmem_resp_waddr @[Rocket.scala 446:14] + ll_wen <= UInt<1>("h01") @[Rocket.scala 447:12] + skip @[Rocket.scala 442:44] + node _T_4187 = eq(replay_wb, UInt<1>("h00")) @[Rocket.scala 450:34] + node _T_4188 = and(wb_reg_valid, _T_4187) @[Rocket.scala 450:31] + node _T_4190 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 450:48] + node wb_valid = and(_T_4188, _T_4190) @[Rocket.scala 450:45] + node wb_wen = and(wb_valid, wb_ctrl.wxd) @[Rocket.scala 451:25] + node rf_wen = or(wb_wen, ll_wen) @[Rocket.scala 452:23] + node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[Rocket.scala 453:21] + node _T_4191 = and(dmem_resp_valid, dmem_resp_xpu) @[Rocket.scala 454:38] + node _T_4193 = neq(wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 456:34] + node _T_4194 = mux(_T_4193, csr.io.rw.rdata, wb_reg_wdata) @[Rocket.scala 456:21] + node _T_4195 = mux(ll_wen, ll_wdata, _T_4194) @[Rocket.scala 455:21] + node rf_wdata = mux(_T_4191, io.dmem.resp.bits.data, _T_4195) @[Rocket.scala 454:21] + when rf_wen : @[Rocket.scala 458:17] + node _T_4197 = neq(rf_waddr, UInt<1>("h00")) @[Rocket.scala 694:16] + when _T_4197 : @[Rocket.scala 694:29] + node _T_4198 = bits(rf_waddr, 4, 0) @[Rocket.scala 683:44] + node _T_4199 = not(_T_4198) @[Rocket.scala 683:39] + infer mport _T_4200 = _T_3331[_T_4199], clock + _T_4200 <= rf_wdata @[Rocket.scala 695:20] + node _T_4201 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 697:20] + when _T_4201 : @[Rocket.scala 697:31] + id_rs_0 <= rf_wdata @[Rocket.scala 697:39] + skip @[Rocket.scala 697:31] + node _T_4202 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 697:20] + when _T_4202 : @[Rocket.scala 697:31] + id_rs_1 <= rf_wdata @[Rocket.scala 697:39] + skip @[Rocket.scala 697:31] + skip @[Rocket.scala 694:29] + skip @[Rocket.scala 458:17] + node _T_4203 = bits(ibuf.io.inst[0].bits.raw, 31, 20) @[Rocket.scala 461:48] + csr.io.decode.csr <= _T_4203 @[Rocket.scala 461:21] + csr.io.exception <= wb_reg_xcpt @[Rocket.scala 462:20] + csr.io.cause <= wb_reg_cause @[Rocket.scala 463:16] + csr.io.retire <= wb_valid @[Rocket.scala 464:17] + csr.io.interrupts <- io.interrupts @[Rocket.scala 465:21] + csr.io.hartid <= io.hartid @[Rocket.scala 466:17] + io.fpu.fcsr_rm <= csr.io.fcsr_rm @[Rocket.scala 467:18] + csr.io.fcsr_flags <- io.fpu.fcsr_flags @[Rocket.scala 468:21] + csr.io.rocc_interrupt <= io.rocc.interrupt @[Rocket.scala 469:25] + csr.io.pc <= wb_reg_pc @[Rocket.scala 470:13] + node _T_4204 = shr(wb_reg_wdata, 38) @[Rocket.scala 653:16] + node _T_4205 = bits(wb_reg_wdata, 39, 38) @[Rocket.scala 654:15] + node _T_4206 = asSInt(_T_4205) @[Rocket.scala 654:39] + node _T_4208 = eq(_T_4204, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4210 = eq(_T_4204, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4211 = or(_T_4208, _T_4210) @[Rocket.scala 656:25] + node _T_4213 = neq(_T_4206, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4214 = asSInt(_T_4204) @[Rocket.scala 657:13] + node _T_4216 = eq(_T_4214, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4217 = asSInt(_T_4204) @[Rocket.scala 657:38] + node _T_4219 = eq(_T_4217, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4220 = or(_T_4216, _T_4219) @[Rocket.scala 657:33] + node _T_4222 = eq(_T_4206, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4223 = bits(_T_4206, 0, 0) @[Rocket.scala 657:76] + node _T_4224 = mux(_T_4220, _T_4222, _T_4223) @[Rocket.scala 657:10] + node _T_4225 = mux(_T_4211, _T_4213, _T_4224) @[Rocket.scala 656:10] + node _T_4226 = bits(wb_reg_wdata, 38, 0) @[Rocket.scala 658:16] + node _T_4227 = cat(_T_4225, _T_4226) @[Cat.scala 30:58] + csr.io.badaddr <= _T_4227 @[Rocket.scala 471:18] + io.ptw.ptbr <- csr.io.ptbr @[Rocket.scala 472:15] + io.ptw.invalidate <= csr.io.fatc @[Rocket.scala 473:21] + io.ptw.status <- csr.io.status @[Rocket.scala 474:17] + node _T_4228 = bits(wb_reg_inst, 31, 20) @[Rocket.scala 475:32] + csr.io.rw.addr <= _T_4228 @[Rocket.scala 475:18] + node _T_4230 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 476:23] + csr.io.rw.cmd <= _T_4230 @[Rocket.scala 476:17] + csr.io.rw.wdata <= wb_reg_wdata @[Rocket.scala 477:19] + node _T_4232 = neq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 479:55] + node _T_4233 = and(id_ctrl.rxs1, _T_4232) @[Rocket.scala 479:42] + node _T_4235 = neq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 480:55] + node _T_4236 = and(id_ctrl.rxs2, _T_4235) @[Rocket.scala 480:42] + node _T_4238 = neq(ibuf.io.inst[0].bits.inst.rd, UInt<1>("h00")) @[Rocket.scala 481:55] + node _T_4239 = and(id_ctrl.wxd, _T_4238) @[Rocket.scala 481:42] + reg _T_4241 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25] + node _T_4242 = shr(_T_4241, 1) @[Rocket.scala 669:35] + node _T_4243 = shl(_T_4242, 1) @[Rocket.scala 669:40] + node _T_4246 = dshl(UInt<1>("h01"), ll_waddr) @[Rocket.scala 672:62] + node _T_4248 = mux(ll_wen, _T_4246, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4249 = not(_T_4248) @[Rocket.scala 664:64] + node _T_4250 = and(_T_4243, _T_4249) @[Rocket.scala 664:62] + node _T_4251 = or(UInt<1>("h00"), ll_wen) @[Rocket.scala 675:17] + when _T_4251 : @[Rocket.scala 676:18] + _T_4241 <= _T_4250 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4252 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35] + node _T_4253 = bits(_T_4252, 0, 0) @[Rocket.scala 665:35] + node _T_4254 = and(_T_4233, _T_4253) @[Rocket.scala 648:27] + node _T_4255 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35] + node _T_4256 = bits(_T_4255, 0, 0) @[Rocket.scala 665:35] + node _T_4257 = and(_T_4236, _T_4256) @[Rocket.scala 648:27] + node _T_4258 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35] + node _T_4259 = bits(_T_4258, 0, 0) @[Rocket.scala 665:35] + node _T_4260 = and(_T_4239, _T_4259) @[Rocket.scala 648:27] + node _T_4261 = or(_T_4254, _T_4257) @[Rocket.scala 648:50] + node id_sboard_hazard = or(_T_4261, _T_4260) @[Rocket.scala 648:50] + node _T_4262 = and(wb_set_sboard, wb_wen) @[Rocket.scala 490:28] + node _T_4264 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62] + node _T_4266 = mux(_T_4262, _T_4264, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4267 = or(_T_4250, _T_4266) @[Rocket.scala 663:60] + node _T_4268 = or(_T_4251, _T_4262) @[Rocket.scala 675:17] + when _T_4268 : @[Rocket.scala 676:18] + _T_4241 <= _T_4267 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4270 = neq(ex_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 493:38] + node _T_4271 = or(_T_4270, ex_ctrl.jalr) @[Rocket.scala 493:48] + node _T_4272 = or(_T_4271, ex_ctrl.mem) @[Rocket.scala 493:64] + node _T_4273 = or(_T_4272, ex_ctrl.div) @[Rocket.scala 493:79] + node _T_4274 = or(_T_4273, ex_ctrl.fp) @[Rocket.scala 493:94] + node ex_cannot_bypass = or(_T_4274, ex_ctrl.rocc) @[Rocket.scala 493:108] + node _T_4275 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 494:70] + node _T_4276 = and(_T_4233, _T_4275) @[Rocket.scala 648:27] + node _T_4277 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 494:70] + node _T_4278 = and(_T_4236, _T_4277) @[Rocket.scala 648:27] + node _T_4279 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 494:70] + node _T_4280 = and(_T_4239, _T_4279) @[Rocket.scala 648:27] + node _T_4281 = or(_T_4276, _T_4278) @[Rocket.scala 648:50] + node _T_4282 = or(_T_4281, _T_4280) @[Rocket.scala 648:50] + node data_hazard_ex = and(ex_ctrl.wxd, _T_4282) @[Rocket.scala 494:36] + node _T_4283 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 495:76] + node _T_4284 = and(io.fpu.dec.ren1, _T_4283) @[Rocket.scala 648:27] + node _T_4285 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 495:76] + node _T_4286 = and(io.fpu.dec.ren2, _T_4285) @[Rocket.scala 648:27] + node _T_4287 = eq(ibuf.io.inst[0].bits.inst.rs3, ex_waddr) @[Rocket.scala 495:76] + node _T_4288 = and(io.fpu.dec.ren3, _T_4287) @[Rocket.scala 648:27] + node _T_4289 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 495:76] + node _T_4290 = and(io.fpu.dec.wen, _T_4289) @[Rocket.scala 648:27] + node _T_4291 = or(_T_4284, _T_4286) @[Rocket.scala 648:50] + node _T_4292 = or(_T_4291, _T_4288) @[Rocket.scala 648:50] + node _T_4293 = or(_T_4292, _T_4290) @[Rocket.scala 648:50] + node fp_data_hazard_ex = and(ex_ctrl.wfd, _T_4293) @[Rocket.scala 495:39] + node _T_4294 = and(data_hazard_ex, ex_cannot_bypass) @[Rocket.scala 496:54] + node _T_4295 = or(_T_4294, fp_data_hazard_ex) @[Rocket.scala 496:74] + node id_ex_hazard = and(ex_reg_valid, _T_4295) @[Rocket.scala 496:35] + node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) @[Rocket.scala 500:43] + node _T_4298 = neq(mem_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 502:40] + node _T_4299 = and(mem_ctrl.mem, mem_mem_cmd_bh) @[Rocket.scala 502:66] + node _T_4300 = or(_T_4298, _T_4299) @[Rocket.scala 502:50] + node _T_4301 = or(_T_4300, mem_ctrl.div) @[Rocket.scala 502:84] + node _T_4302 = or(_T_4301, mem_ctrl.fp) @[Rocket.scala 502:100] + node mem_cannot_bypass = or(_T_4302, mem_ctrl.rocc) @[Rocket.scala 502:115] + node _T_4303 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 503:72] + node _T_4304 = and(_T_4233, _T_4303) @[Rocket.scala 648:27] + node _T_4305 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 503:72] + node _T_4306 = and(_T_4236, _T_4305) @[Rocket.scala 648:27] + node _T_4307 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 503:72] + node _T_4308 = and(_T_4239, _T_4307) @[Rocket.scala 648:27] + node _T_4309 = or(_T_4304, _T_4306) @[Rocket.scala 648:50] + node _T_4310 = or(_T_4309, _T_4308) @[Rocket.scala 648:50] + node data_hazard_mem = and(mem_ctrl.wxd, _T_4310) @[Rocket.scala 503:38] + node _T_4311 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 504:78] + node _T_4312 = and(io.fpu.dec.ren1, _T_4311) @[Rocket.scala 648:27] + node _T_4313 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 504:78] + node _T_4314 = and(io.fpu.dec.ren2, _T_4313) @[Rocket.scala 648:27] + node _T_4315 = eq(ibuf.io.inst[0].bits.inst.rs3, mem_waddr) @[Rocket.scala 504:78] + node _T_4316 = and(io.fpu.dec.ren3, _T_4315) @[Rocket.scala 648:27] + node _T_4317 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 504:78] + node _T_4318 = and(io.fpu.dec.wen, _T_4317) @[Rocket.scala 648:27] + node _T_4319 = or(_T_4312, _T_4314) @[Rocket.scala 648:50] + node _T_4320 = or(_T_4319, _T_4316) @[Rocket.scala 648:50] + node _T_4321 = or(_T_4320, _T_4318) @[Rocket.scala 648:50] + node fp_data_hazard_mem = and(mem_ctrl.wfd, _T_4321) @[Rocket.scala 504:41] + node _T_4322 = and(data_hazard_mem, mem_cannot_bypass) @[Rocket.scala 505:57] + node _T_4323 = or(_T_4322, fp_data_hazard_mem) @[Rocket.scala 505:78] + node id_mem_hazard = and(mem_reg_valid, _T_4323) @[Rocket.scala 505:37] + node _T_4324 = and(mem_reg_valid, data_hazard_mem) @[Rocket.scala 506:32] + node _T_4325 = and(_T_4324, mem_ctrl.mem) @[Rocket.scala 506:51] + id_load_use <= _T_4325 @[Rocket.scala 506:15] + node _T_4326 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 509:70] + node _T_4327 = and(_T_4233, _T_4326) @[Rocket.scala 648:27] + node _T_4328 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 509:70] + node _T_4329 = and(_T_4236, _T_4328) @[Rocket.scala 648:27] + node _T_4330 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 509:70] + node _T_4331 = and(_T_4239, _T_4330) @[Rocket.scala 648:27] + node _T_4332 = or(_T_4327, _T_4329) @[Rocket.scala 648:50] + node _T_4333 = or(_T_4332, _T_4331) @[Rocket.scala 648:50] + node data_hazard_wb = and(wb_ctrl.wxd, _T_4333) @[Rocket.scala 509:36] + node _T_4334 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 510:76] + node _T_4335 = and(io.fpu.dec.ren1, _T_4334) @[Rocket.scala 648:27] + node _T_4336 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 510:76] + node _T_4337 = and(io.fpu.dec.ren2, _T_4336) @[Rocket.scala 648:27] + node _T_4338 = eq(ibuf.io.inst[0].bits.inst.rs3, wb_waddr) @[Rocket.scala 510:76] + node _T_4339 = and(io.fpu.dec.ren3, _T_4338) @[Rocket.scala 648:27] + node _T_4340 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 510:76] + node _T_4341 = and(io.fpu.dec.wen, _T_4340) @[Rocket.scala 648:27] + node _T_4342 = or(_T_4335, _T_4337) @[Rocket.scala 648:50] + node _T_4343 = or(_T_4342, _T_4339) @[Rocket.scala 648:50] + node _T_4344 = or(_T_4343, _T_4341) @[Rocket.scala 648:50] + node fp_data_hazard_wb = and(wb_ctrl.wfd, _T_4344) @[Rocket.scala 510:39] + node _T_4345 = and(data_hazard_wb, wb_set_sboard) @[Rocket.scala 511:54] + node _T_4346 = or(_T_4345, fp_data_hazard_wb) @[Rocket.scala 511:71] + node id_wb_hazard = and(wb_reg_valid, _T_4346) @[Rocket.scala 511:35] + reg _T_4348 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25] + node _T_4350 = and(wb_dcache_miss, wb_ctrl.wfd) @[Rocket.scala 515:35] + node _T_4351 = or(_T_4350, io.fpu.sboard_set) @[Rocket.scala 515:50] + node _T_4352 = and(_T_4351, wb_valid) @[Rocket.scala 515:72] + node _T_4354 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62] + node _T_4356 = mux(_T_4352, _T_4354, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4357 = or(_T_4348, _T_4356) @[Rocket.scala 663:60] + node _T_4358 = or(UInt<1>("h00"), _T_4352) @[Rocket.scala 675:17] + when _T_4358 : @[Rocket.scala 676:18] + _T_4348 <= _T_4357 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4359 = and(dmem_resp_replay, dmem_resp_fpu) @[Rocket.scala 516:38] + node _T_4361 = dshl(UInt<1>("h01"), dmem_resp_waddr) @[Rocket.scala 672:62] + node _T_4363 = mux(_T_4359, _T_4361, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4364 = not(_T_4363) @[Rocket.scala 664:64] + node _T_4365 = and(_T_4357, _T_4364) @[Rocket.scala 664:62] + node _T_4366 = or(_T_4358, _T_4359) @[Rocket.scala 675:17] + when _T_4366 : @[Rocket.scala 676:18] + _T_4348 <= _T_4365 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4368 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) @[Rocket.scala 672:62] + node _T_4370 = mux(io.fpu.sboard_clr, _T_4368, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4371 = not(_T_4370) @[Rocket.scala 664:64] + node _T_4372 = and(_T_4365, _T_4371) @[Rocket.scala 664:62] + node _T_4373 = or(_T_4366, io.fpu.sboard_clr) @[Rocket.scala 675:17] + when _T_4373 : @[Rocket.scala 676:18] + _T_4348 <= _T_4372 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4375 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) @[Rocket.scala 519:18] + node _T_4376 = and(id_csr_en, _T_4375) @[Rocket.scala 519:15] + node _T_4377 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35] + node _T_4378 = bits(_T_4377, 0, 0) @[Rocket.scala 665:35] + node _T_4379 = and(io.fpu.dec.ren1, _T_4378) @[Rocket.scala 648:27] + node _T_4380 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35] + node _T_4381 = bits(_T_4380, 0, 0) @[Rocket.scala 665:35] + node _T_4382 = and(io.fpu.dec.ren2, _T_4381) @[Rocket.scala 648:27] + node _T_4383 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs3) @[Rocket.scala 665:35] + node _T_4384 = bits(_T_4383, 0, 0) @[Rocket.scala 665:35] + node _T_4385 = and(io.fpu.dec.ren3, _T_4384) @[Rocket.scala 648:27] + node _T_4386 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35] + node _T_4387 = bits(_T_4386, 0, 0) @[Rocket.scala 665:35] + node _T_4388 = and(io.fpu.dec.wen, _T_4387) @[Rocket.scala 648:27] + node _T_4389 = or(_T_4379, _T_4382) @[Rocket.scala 648:50] + node _T_4390 = or(_T_4389, _T_4385) @[Rocket.scala 648:50] + node _T_4391 = or(_T_4390, _T_4388) @[Rocket.scala 648:50] + node id_stall_fpu = or(_T_4376, _T_4391) @[Rocket.scala 519:35] + reg dcache_blocked : UInt<1>, clock @[Rocket.scala 522:27] + node _T_4394 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 523:21] + node _T_4395 = or(io.dmem.req.valid, dcache_blocked) @[Rocket.scala 523:62] + node _T_4396 = and(_T_4394, _T_4395) @[Rocket.scala 523:40] + dcache_blocked <= _T_4396 @[Rocket.scala 523:18] + reg rocc_blocked : UInt<1>, clock @[Rocket.scala 524:25] + node _T_4399 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 525:19] + node _T_4401 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 525:35] + node _T_4402 = and(_T_4399, _T_4401) @[Rocket.scala 525:32] + node _T_4403 = or(io.rocc.cmd.valid, rocc_blocked) @[Rocket.scala 525:76] + node _T_4404 = and(_T_4402, _T_4403) @[Rocket.scala 525:54] + rocc_blocked <= _T_4404 @[Rocket.scala 525:16] + node _T_4405 = or(id_ex_hazard, id_mem_hazard) @[Rocket.scala 528:18] + node _T_4406 = or(_T_4405, id_wb_hazard) @[Rocket.scala 528:35] + node _T_4407 = or(_T_4406, id_sboard_hazard) @[Rocket.scala 528:51] + node _T_4408 = and(id_ctrl.fp, id_stall_fpu) @[Rocket.scala 529:16] + node _T_4409 = or(_T_4407, _T_4408) @[Rocket.scala 528:71] + node _T_4410 = and(id_ctrl.mem, dcache_blocked) @[Rocket.scala 530:17] + node _T_4411 = or(_T_4409, _T_4410) @[Rocket.scala 529:32] + node _T_4412 = and(id_ctrl.rocc, rocc_blocked) @[Rocket.scala 531:18] + node _T_4413 = or(_T_4411, _T_4412) @[Rocket.scala 530:35] + node _T_4415 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 532:65] + node _T_4416 = and(div.io.resp.valid, _T_4415) @[Rocket.scala 532:62] + node _T_4417 = or(div.io.req.ready, _T_4416) @[Rocket.scala 532:40] + node _T_4419 = eq(_T_4417, UInt<1>("h00")) @[Rocket.scala 532:21] + node _T_4420 = or(_T_4419, div.io.req.valid) @[Rocket.scala 532:75] + node _T_4421 = and(id_ctrl.div, _T_4420) @[Rocket.scala 532:17] + node _T_4422 = or(_T_4413, _T_4421) @[Rocket.scala 531:34] + node _T_4423 = or(_T_4422, id_do_fence) @[Rocket.scala 532:96] + node ctrl_stalld = or(_T_4423, csr.io.csr_stall) @[Rocket.scala 533:17] + node _T_4425 = eq(ibuf.io.inst[0].valid, UInt<1>("h00")) @[Rocket.scala 535:17] + node _T_4426 = or(_T_4425, ibuf.io.inst[0].bits.replay) @[Rocket.scala 535:40] + node _T_4427 = or(_T_4426, take_pc_mem_wb) @[Rocket.scala 535:71] + node _T_4428 = or(_T_4427, ctrl_stalld) @[Rocket.scala 535:89] + node _T_4429 = or(_T_4428, csr.io.interrupt) @[Rocket.scala 535:104] + ctrl_killd <= _T_4429 @[Rocket.scala 535:14] + io.imem.req.valid <= take_pc @[Rocket.scala 537:21] + node _T_4431 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 538:35] + io.imem.req.bits.speculative <= _T_4431 @[Rocket.scala 538:32] + node _T_4432 = or(wb_reg_xcpt, csr.io.eret) @[Rocket.scala 540:17] + node _T_4434 = or(take_pc_mem, UInt<1>("h01")) @[Rocket.scala 542:21] + node _T_4435 = mux(_T_4434, mem_npc, id_npc) @[Rocket.scala 542:8] + node _T_4436 = mux(replay_wb, wb_reg_pc, _T_4435) @[Rocket.scala 541:8] + node _T_4437 = mux(_T_4432, csr.io.evec, _T_4436) @[Rocket.scala 540:8] + io.imem.req.bits.pc <= _T_4437 @[Rocket.scala 539:23] + node _T_4438 = and(wb_reg_valid, wb_ctrl.fence_i) @[Rocket.scala 544:40] + node _T_4440 = eq(io.dmem.s2_nack, UInt<1>("h00")) @[Rocket.scala 544:62] + node _T_4441 = and(_T_4438, _T_4440) @[Rocket.scala 544:59] + io.imem.flush_icache <= _T_4441 @[Rocket.scala 544:24] + io.imem.flush_tlb <= csr.io.fatc @[Rocket.scala 545:21] + node _T_4443 = eq(ctrl_stalld, UInt<1>("h00")) @[Rocket.scala 547:28] + node _T_4444 = or(_T_4443, csr.io.interrupt) @[Rocket.scala 547:41] + ibuf.io.inst[0].ready <= _T_4444 @[Rocket.scala 547:25] + node _T_4445 = and(mem_reg_replay, mem_reg_btb_hit) @[Rocket.scala 549:47] + node _T_4447 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 549:88] + node _T_4448 = and(mem_reg_valid, _T_4447) @[Rocket.scala 549:85] + node _T_4450 = eq(mem_cfi, UInt<1>("h00")) @[Rocket.scala 549:123] + node _T_4451 = or(mem_cfi_taken, _T_4450) @[Rocket.scala 549:120] + node _T_4452 = and(_T_4451, mem_misprediction) @[Rocket.scala 549:133] + node _T_4454 = and(UInt<1>("h00"), mem_ctrl.jal) @[Rocket.scala 549:169] + node _T_4456 = eq(mem_reg_btb_hit, UInt<1>("h00")) @[Rocket.scala 549:188] + node _T_4457 = and(_T_4454, _T_4456) @[Rocket.scala 549:185] + node _T_4458 = or(_T_4452, _T_4457) @[Rocket.scala 549:151] + node _T_4459 = and(_T_4448, _T_4458) @[Rocket.scala 549:100] + node _T_4460 = or(_T_4445, _T_4459) @[Rocket.scala 549:67] + io.imem.btb_update.valid <= _T_4460 @[Rocket.scala 549:28] + node _T_4462 = eq(mem_reg_replay, UInt<1>("h00")) @[Rocket.scala 550:38] + node _T_4463 = and(_T_4462, mem_cfi) @[Rocket.scala 550:54] + io.imem.btb_update.bits.isValid <= _T_4463 @[Rocket.scala 550:35] + node _T_4464 = or(mem_ctrl.jal, mem_ctrl.jalr) @[Rocket.scala 551:50] + io.imem.btb_update.bits.isJump <= _T_4464 @[Rocket.scala 551:34] + node _T_4465 = bits(mem_reg_inst, 19, 15) @[Rocket.scala 552:68] + node _T_4468 = and(_T_4465, UInt<5>("h01b")) @[Rocket.scala 552:76] + node _T_4469 = eq(UInt<1>("h01"), _T_4468) @[Rocket.scala 552:76] + node _T_4470 = and(mem_ctrl.jalr, _T_4469) @[Rocket.scala 552:53] + io.imem.btb_update.bits.isReturn <= _T_4470 @[Rocket.scala 552:36] + io.imem.btb_update.bits.target <= io.imem.req.bits.pc @[Rocket.scala 553:34] + node _T_4473 = mux(mem_reg_rvc, UInt<1>("h00"), UInt<2>("h02")) @[Rocket.scala 554:74] + node _T_4474 = add(mem_reg_pc, _T_4473) @[Rocket.scala 554:69] + node _T_4475 = tail(_T_4474, 1) @[Rocket.scala 554:69] + io.imem.btb_update.bits.br_pc <= _T_4475 @[Rocket.scala 554:33] + node _T_4476 = not(io.imem.btb_update.bits.br_pc) @[Rocket.scala 555:35] + node _T_4478 = or(_T_4476, UInt<2>("h03")) @[Rocket.scala 555:66] + node _T_4479 = not(_T_4478) @[Rocket.scala 555:33] + io.imem.btb_update.bits.pc <= _T_4479 @[Rocket.scala 555:30] + io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit @[Rocket.scala 556:44] + io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp @[Rocket.scala 557:43] + node _T_4481 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 559:48] + node _T_4482 = and(mem_reg_valid, _T_4481) @[Rocket.scala 559:45] + node _T_4483 = and(_T_4482, mem_ctrl.branch) @[Rocket.scala 559:60] + io.imem.bht_update.valid <= _T_4483 @[Rocket.scala 559:28] + io.imem.bht_update.bits.pc <= io.imem.btb_update.bits.pc @[Rocket.scala 560:30] + io.imem.bht_update.bits.taken <= mem_br_taken @[Rocket.scala 561:33] + io.imem.bht_update.bits.mispredict <= mem_misprediction @[Rocket.scala 562:38] + io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 563:38] + node _T_4485 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 565:48] + node _T_4486 = and(mem_reg_valid, _T_4485) @[Rocket.scala 565:45] + io.imem.ras_update.valid <= _T_4486 @[Rocket.scala 565:28] + io.imem.ras_update.bits.returnAddr <= mem_int_wdata @[Rocket.scala 566:38] + node _T_4487 = bits(mem_waddr, 0, 0) @[Rocket.scala 567:80] + node _T_4488 = and(io.imem.btb_update.bits.isJump, _T_4487) @[Rocket.scala 567:68] + io.imem.ras_update.bits.isCall <= _T_4488 @[Rocket.scala 567:34] + io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn @[Rocket.scala 568:36] + io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 569:38] + node _T_4490 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 571:19] + node _T_4491 = and(_T_4490, id_ctrl.fp) @[Rocket.scala 571:31] + io.fpu.valid <= _T_4491 @[Rocket.scala 571:16] + io.fpu.killx <= ctrl_killx @[Rocket.scala 572:16] + io.fpu.killm <= killm_common @[Rocket.scala 573:16] + io.fpu.inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 574:15] + io.fpu.fromint_data <= ex_rs_0 @[Rocket.scala 575:23] + node _T_4492 = and(dmem_resp_valid, dmem_resp_fpu) @[Rocket.scala 576:43] + io.fpu.dmem_resp_val <= _T_4492 @[Rocket.scala 576:24] + io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 577:25] + io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ @[Rocket.scala 578:25] + io.fpu.dmem_resp_tag <= dmem_resp_waddr @[Rocket.scala 579:24] + node _T_4493 = and(ex_reg_valid, ex_ctrl.mem) @[Rocket.scala 581:41] + io.dmem.req.valid <= _T_4493 @[Rocket.scala 581:25] + node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) @[Cat.scala 30:58] + io.dmem.req.bits.tag <= ex_dcache_tag @[Rocket.scala 584:25] + io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd @[Rocket.scala 585:25] + io.dmem.req.bits.typ <= ex_ctrl.mem_type @[Rocket.scala 586:25] + io.dmem.req.bits.phys <= UInt<1>("h00") @[Rocket.scala 587:25] + node _T_4495 = shr(ex_rs_0, 38) @[Rocket.scala 653:16] + node _T_4496 = bits(alu.io.adder_out, 39, 38) @[Rocket.scala 654:15] + node _T_4497 = asSInt(_T_4496) @[Rocket.scala 654:39] + node _T_4499 = eq(_T_4495, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4501 = eq(_T_4495, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4502 = or(_T_4499, _T_4501) @[Rocket.scala 656:25] + node _T_4504 = neq(_T_4497, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4505 = asSInt(_T_4495) @[Rocket.scala 657:13] + node _T_4507 = eq(_T_4505, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4508 = asSInt(_T_4495) @[Rocket.scala 657:38] + node _T_4510 = eq(_T_4508, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4511 = or(_T_4507, _T_4510) @[Rocket.scala 657:33] + node _T_4513 = eq(_T_4497, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4514 = bits(_T_4497, 0, 0) @[Rocket.scala 657:76] + node _T_4515 = mux(_T_4511, _T_4513, _T_4514) @[Rocket.scala 657:10] + node _T_4516 = mux(_T_4502, _T_4504, _T_4515) @[Rocket.scala 656:10] + node _T_4517 = bits(alu.io.adder_out, 38, 0) @[Rocket.scala 658:16] + node _T_4518 = cat(_T_4516, _T_4517) @[Cat.scala 30:58] + io.dmem.req.bits.addr <= _T_4518 @[Rocket.scala 588:25] + io.dmem.invalidate_lr <= wb_reg_xcpt @[Rocket.scala 589:25] + node _T_4519 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) @[Rocket.scala 590:25] + io.dmem.s1_data <= _T_4519 @[Rocket.scala 590:19] + node _T_4520 = or(killm_common, mem_breakpoint) @[Rocket.scala 591:35] + io.dmem.s1_kill <= _T_4520 @[Rocket.scala 591:19] + node _T_4521 = and(mem_ctrl.mem, mem_xcpt) @[Rocket.scala 592:22] + node _T_4523 = eq(io.dmem.s1_kill, UInt<1>("h00")) @[Rocket.scala 592:37] + node _T_4524 = and(_T_4521, _T_4523) @[Rocket.scala 592:34] + when _T_4524 : @[Rocket.scala 592:55] + node _T_4525 = cat(io.dmem.xcpt.pf.ld, io.dmem.xcpt.pf.st) @[Rocket.scala 593:25] + node _T_4526 = cat(io.dmem.xcpt.ma.ld, io.dmem.xcpt.ma.st) @[Rocket.scala 593:25] + node _T_4527 = cat(_T_4526, _T_4525) @[Rocket.scala 593:25] + node _T_4529 = neq(_T_4527, UInt<1>("h00")) @[Rocket.scala 593:32] + node _T_4530 = or(_T_4529, reset) @[Rocket.scala 593:11] + node _T_4532 = eq(_T_4530, UInt<1>("h00")) @[Rocket.scala 593:11] + when _T_4532 : @[Rocket.scala 593:11] + printf(clock, UInt<1>(1), "Assertion failed\n at Rocket.scala:593 assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive\n") @[Rocket.scala 593:11] + stop(clock, UInt<1>(1), 1) @[Rocket.scala 593:11] + skip @[Rocket.scala 593:11] + skip @[Rocket.scala 592:55] + node _T_4533 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 596:37] + node _T_4535 = eq(replay_wb_common, UInt<1>("h00")) @[Rocket.scala 596:56] + node _T_4536 = and(_T_4533, _T_4535) @[Rocket.scala 596:53] + io.rocc.cmd.valid <= _T_4536 @[Rocket.scala 596:21] + node _T_4538 = neq(csr.io.status.xs, UInt<1>("h00")) @[Rocket.scala 597:52] + node _T_4539 = and(wb_reg_xcpt, _T_4538) @[Rocket.scala 597:32] + io.rocc.exception <= _T_4539 @[Rocket.scala 597:21] + io.rocc.cmd.bits.status <- csr.io.status @[Rocket.scala 598:27] + wire _T_4558 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} @[Rocket.scala 599:58] + _T_4558 is invalid @[Rocket.scala 599:58] + wire _T_4568 : UInt<32> + _T_4568 is invalid + _T_4568 <= wb_reg_inst + node _T_4569 = bits(_T_4568, 6, 0) @[Rocket.scala 599:58] + _T_4558.opcode <= _T_4569 @[Rocket.scala 599:58] + node _T_4570 = bits(_T_4568, 11, 7) @[Rocket.scala 599:58] + _T_4558.rd <= _T_4570 @[Rocket.scala 599:58] + node _T_4571 = bits(_T_4568, 12, 12) @[Rocket.scala 599:58] + _T_4558.xs2 <= _T_4571 @[Rocket.scala 599:58] + node _T_4572 = bits(_T_4568, 13, 13) @[Rocket.scala 599:58] + _T_4558.xs1 <= _T_4572 @[Rocket.scala 599:58] + node _T_4573 = bits(_T_4568, 14, 14) @[Rocket.scala 599:58] + _T_4558.xd <= _T_4573 @[Rocket.scala 599:58] + node _T_4574 = bits(_T_4568, 19, 15) @[Rocket.scala 599:58] + _T_4558.rs1 <= _T_4574 @[Rocket.scala 599:58] + node _T_4575 = bits(_T_4568, 24, 20) @[Rocket.scala 599:58] + _T_4558.rs2 <= _T_4575 @[Rocket.scala 599:58] + node _T_4576 = bits(_T_4568, 31, 25) @[Rocket.scala 599:58] + _T_4558.funct <= _T_4576 @[Rocket.scala 599:58] + io.rocc.cmd.bits.inst <- _T_4558 @[Rocket.scala 599:25] + io.rocc.cmd.bits.rs1 <= wb_reg_wdata @[Rocket.scala 600:24] + io.rocc.cmd.bits.rs2 <= wb_reg_rs2 @[Rocket.scala 601:24] + node _T_4577 = bits(csr.io.time, 31, 0) @[Rocket.scala 637:32] + node _T_4579 = mux(rf_wen, rf_waddr, UInt<1>("h00")) @[Rocket.scala 638:13] + node _T_4580 = bits(wb_reg_inst, 19, 15) @[Rocket.scala 639:21] + reg _T_4581 : UInt, clock @[Rocket.scala 639:42] + _T_4581 <= ex_rs_0 @[Rocket.scala 639:42] + reg _T_4582 : UInt, clock @[Rocket.scala 639:33] + _T_4582 <= _T_4581 @[Rocket.scala 639:33] + node _T_4583 = bits(wb_reg_inst, 24, 20) @[Rocket.scala 640:21] + reg _T_4584 : UInt, clock @[Rocket.scala 640:42] + _T_4584 <= ex_rs_1 @[Rocket.scala 640:42] + reg _T_4585 : UInt, clock @[Rocket.scala 640:33] + _T_4585 <= _T_4584 @[Rocket.scala 640:33] + node _T_4587 = eq(reset, UInt<1>("h00")) @[Rocket.scala 636:11] + when _T_4587 : @[Rocket.scala 636:11] + printf(clock, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, _T_4577, wb_valid, wb_reg_pc, _T_4579, rf_wdata, rf_wen, _T_4580, _T_4582, _T_4583, _T_4585, wb_reg_inst, wb_reg_inst) @[Rocket.scala 636:11] + skip @[Rocket.scala 636:11] + + module RocketTile : + input clock : Clock input reset : UInt<1> - output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - - io is invalid - node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) - node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) - node T_1440 = and(T_1437, T_1439) - node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) - node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000")) - node T_1445 = and(T_1442, T_1444) - node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000")) - node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000")) - node T_1450 = and(T_1447, T_1449) - node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000")) - node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000")) - node T_1455 = and(T_1452, T_1454) - wire T_1457 : UInt<1>[4] - T_1457[0] <= T_1440 - T_1457[1] <= T_1445 - T_1457[2] <= T_1450 - T_1457[3] <= T_1455 - node T_1463 = cat(T_1457[3], T_1457[2]) - node T_1464 = cat(T_1457[1], T_1457[0]) - node ar_route = cat(T_1463, T_1464) - node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00")) - node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000")) - node T_1470 = and(T_1467, T_1469) - node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) - node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000")) - node T_1475 = and(T_1472, T_1474) - node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000")) - node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000")) - node T_1480 = and(T_1477, T_1479) - node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000")) - node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000")) - node T_1485 = and(T_1482, T_1484) - wire T_1487 : UInt<1>[4] - T_1487[0] <= T_1470 - T_1487[1] <= T_1475 - T_1487[2] <= T_1480 - T_1487[3] <= T_1485 - node T_1493 = cat(T_1487[3], T_1487[2]) - node T_1494 = cat(T_1487[1], T_1487[0]) - node aw_route = cat(T_1493, T_1494) - node T_1499 = bits(ar_route, 0, 0) - node T_1500 = and(io.master.ar.valid, T_1499) - io.slave[0].ar.valid <= T_1500 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bits(ar_route, 0, 0) - node T_1502 = and(io.slave[0].ar.ready, T_1501) - node T_1503 = or(UInt<1>("h00"), T_1502) - node T_1504 = bits(aw_route, 0, 0) - node T_1505 = and(io.master.aw.valid, T_1504) - io.slave[0].aw.valid <= T_1505 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bits(aw_route, 0, 0) - node T_1507 = and(io.slave[0].aw.ready, T_1506) - node T_1508 = or(UInt<1>("h00"), T_1507) - reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1511 : - T_1510 <= UInt<1>("h01") - skip - node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1514 = and(T_1513, io.slave[0].w.bits.last) - when T_1514 : - T_1510 <= UInt<1>("h00") - skip - node T_1516 = and(io.master.w.valid, T_1510) - io.slave[0].w.valid <= T_1516 - io.slave[0].w.bits <- io.master.w.bits - node T_1517 = and(io.slave[0].w.ready, T_1510) - node T_1518 = or(UInt<1>("h00"), T_1517) - node T_1519 = bits(ar_route, 1, 1) - node T_1520 = and(io.master.ar.valid, T_1519) - io.slave[1].ar.valid <= T_1520 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bits(ar_route, 1, 1) - node T_1522 = and(io.slave[1].ar.ready, T_1521) - node T_1523 = or(T_1503, T_1522) - node T_1524 = bits(aw_route, 1, 1) - node T_1525 = and(io.master.aw.valid, T_1524) - io.slave[1].aw.valid <= T_1525 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bits(aw_route, 1, 1) - node T_1527 = and(io.slave[1].aw.ready, T_1526) - node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1531 : - T_1530 <= UInt<1>("h01") - skip - node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1534 = and(T_1533, io.slave[1].w.bits.last) - when T_1534 : - T_1530 <= UInt<1>("h00") - skip - node T_1536 = and(io.master.w.valid, T_1530) - io.slave[1].w.valid <= T_1536 - io.slave[1].w.bits <- io.master.w.bits - node T_1537 = and(io.slave[1].w.ready, T_1530) - node T_1538 = or(T_1518, T_1537) - node T_1539 = bits(ar_route, 2, 2) - node T_1540 = and(io.master.ar.valid, T_1539) - io.slave[2].ar.valid <= T_1540 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bits(ar_route, 2, 2) - node T_1542 = and(io.slave[2].ar.ready, T_1541) - node T_1543 = or(T_1523, T_1542) - node T_1544 = bits(aw_route, 2, 2) - node T_1545 = and(io.master.aw.valid, T_1544) - io.slave[2].aw.valid <= T_1545 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bits(aw_route, 2, 2) - node T_1547 = and(io.slave[2].aw.ready, T_1546) - node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1551 : - T_1550 <= UInt<1>("h01") - skip - node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1554 = and(T_1553, io.slave[2].w.bits.last) - when T_1554 : - T_1550 <= UInt<1>("h00") - skip - node T_1556 = and(io.master.w.valid, T_1550) - io.slave[2].w.valid <= T_1556 - io.slave[2].w.bits <- io.master.w.bits - node T_1557 = and(io.slave[2].w.ready, T_1550) - node T_1558 = or(T_1538, T_1557) - node T_1559 = bits(ar_route, 3, 3) - node T_1560 = and(io.master.ar.valid, T_1559) - io.slave[3].ar.valid <= T_1560 - io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bits(ar_route, 3, 3) - node T_1562 = and(io.slave[3].ar.ready, T_1561) - node ar_ready = or(T_1543, T_1562) - node T_1564 = bits(aw_route, 3, 3) - node T_1565 = and(io.master.aw.valid, T_1564) - io.slave[3].aw.valid <= T_1565 - io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bits(aw_route, 3, 3) - node T_1567 = and(io.slave[3].aw.ready, T_1566) - node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) - when T_1571 : - T_1570 <= UInt<1>("h01") - skip - node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) - node T_1574 = and(T_1573, io.slave[3].w.bits.last) - when T_1574 : - T_1570 <= UInt<1>("h00") - skip - node T_1576 = and(io.master.w.valid, T_1570) - io.slave[3].w.valid <= T_1576 - io.slave[3].w.bits <- io.master.w.bits - node T_1577 = and(io.slave[3].w.ready, T_1570) - node w_ready = or(T_1558, T_1577) - node T_1580 = neq(ar_route, UInt<1>("h00")) - node r_invalid = eq(T_1580, UInt<1>("h00")) - node T_1584 = neq(aw_route, UInt<1>("h00")) - node w_invalid = eq(T_1584, UInt<1>("h00")) - inst err_slave of NastiErrorSlave - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1588 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1588 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1589 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1589 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1590 = and(r_invalid, err_slave.io.ar.ready) - node T_1591 = or(ar_ready, T_1590) - io.master.ar.ready <= T_1591 - node T_1592 = and(w_invalid, err_slave.io.aw.ready) - node T_1593 = or(aw_ready, T_1592) - io.master.aw.ready <= T_1593 - node T_1594 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1594 - inst b_arb of RRArbiter_38 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- io.slave[3].b - r_arb.io.in[3] <- io.slave[3].r - b_arb.io.in[4] <- err_slave.io.b - r_arb.io.in[4] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - - module NastiErrorSlave_40 : - input clk : Clock + output io : {master : {1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, flip interrupts : {0 : UInt<1>[5]}, flip hartid : UInt<64>, flip resetVector : UInt<64>, flip slave : {}} + + io is invalid + io is invalid + inst dcache of DCache_dcache @[LazyModule.scala 60:13] + dcache.io is invalid + dcache.clock <= clock + dcache.reset <= reset + inst TLMonitor of TLMonitor_31 @[LazyModule.scala 60:13] + TLMonitor.io is invalid + TLMonitor.clock <= clock + TLMonitor.reset <= reset + inst frontend of Frontend_frontend @[LazyModule.scala 60:13] + frontend.io is invalid + frontend.clock <= clock + frontend.reset <= reset + inst TLMonitor_1 of TLMonitor_33 @[LazyModule.scala 60:13] + TLMonitor_1.io is invalid + TLMonitor_1.clock <= clock + TLMonitor_1.reset <= reset + wire _T_88 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_88 is invalid @[Bundles.scala 234:19] + wire _T_185 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_185 is invalid @[Bundles.scala 214:19] + _T_185.ready <= io.master.0.a.ready @[Bundles.scala 215:15] + _T_185.valid <= dcache.io.mem.0.a.valid @[Bundles.scala 216:15] + _T_185.bits <- dcache.io.mem.0.a.bits @[Bundles.scala 217:15] + _T_88.a <- _T_185 @[Bundles.scala 235:11] + wire _T_207 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_207 is invalid @[Bundles.scala 214:19] + _T_207.ready <= dcache.io.mem.0.b.ready @[Bundles.scala 215:15] + _T_207.valid <= io.master.0.b.valid @[Bundles.scala 216:15] + _T_207.bits <- io.master.0.b.bits @[Bundles.scala 217:15] + _T_88.b <- _T_207 @[Bundles.scala 236:11] + wire _T_229 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_229 is invalid @[Bundles.scala 214:19] + _T_229.ready <= io.master.0.c.ready @[Bundles.scala 215:15] + _T_229.valid <= dcache.io.mem.0.c.valid @[Bundles.scala 216:15] + _T_229.bits <- dcache.io.mem.0.c.bits @[Bundles.scala 217:15] + _T_88.c <- _T_229 @[Bundles.scala 237:11] + wire _T_252 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_252 is invalid @[Bundles.scala 214:19] + _T_252.ready <= dcache.io.mem.0.d.ready @[Bundles.scala 215:15] + _T_252.valid <= io.master.0.d.valid @[Bundles.scala 216:15] + _T_252.bits <- io.master.0.d.bits @[Bundles.scala 217:15] + _T_88.d <- _T_252 @[Bundles.scala 238:11] + wire _T_269 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_269 is invalid @[Bundles.scala 214:19] + _T_269.ready <= io.master.0.e.ready @[Bundles.scala 215:15] + _T_269.valid <= dcache.io.mem.0.e.valid @[Bundles.scala 216:15] + _T_269.bits <- dcache.io.mem.0.e.bits @[Bundles.scala 217:15] + _T_88.e <- _T_269 @[Bundles.scala 239:11] + TLMonitor.io.in[0] <- _T_88 @[HellaCache.scala 178:14] + io.master.0 <- dcache.io.mem.0 @[HellaCache.scala 178:14] + wire _T_360 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_360 is invalid @[Bundles.scala 234:19] + wire _T_457 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_457 is invalid @[Bundles.scala 214:19] + _T_457.ready <= io.master.1.a.ready @[Bundles.scala 215:15] + _T_457.valid <= frontend.io.mem.0.a.valid @[Bundles.scala 216:15] + _T_457.bits <- frontend.io.mem.0.a.bits @[Bundles.scala 217:15] + _T_360.a <- _T_457 @[Bundles.scala 235:11] + wire _T_479 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_479 is invalid @[Bundles.scala 214:19] + _T_479.ready <= frontend.io.mem.0.b.ready @[Bundles.scala 215:15] + _T_479.valid <= io.master.1.b.valid @[Bundles.scala 216:15] + _T_479.bits <- io.master.1.b.bits @[Bundles.scala 217:15] + _T_360.b <- _T_479 @[Bundles.scala 236:11] + wire _T_501 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_501 is invalid @[Bundles.scala 214:19] + _T_501.ready <= io.master.1.c.ready @[Bundles.scala 215:15] + _T_501.valid <= frontend.io.mem.0.c.valid @[Bundles.scala 216:15] + _T_501.bits <- frontend.io.mem.0.c.bits @[Bundles.scala 217:15] + _T_360.c <- _T_501 @[Bundles.scala 237:11] + wire _T_524 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_524 is invalid @[Bundles.scala 214:19] + _T_524.ready <= frontend.io.mem.0.d.ready @[Bundles.scala 215:15] + _T_524.valid <= io.master.1.d.valid @[Bundles.scala 216:15] + _T_524.bits <- io.master.1.d.bits @[Bundles.scala 217:15] + _T_360.d <- _T_524 @[Bundles.scala 238:11] + wire _T_541 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_541 is invalid @[Bundles.scala 214:19] + _T_541.ready <= io.master.1.e.ready @[Bundles.scala 215:15] + _T_541.valid <= frontend.io.mem.0.e.valid @[Bundles.scala 216:15] + _T_541.bits <- frontend.io.mem.0.e.bits @[Bundles.scala 217:15] + _T_360.e <- _T_541 @[Bundles.scala 239:11] + TLMonitor_1.io.in[0] <- _T_360 @[Frontend.scala 165:14] + io.master.1 <- frontend.io.mem.0 @[Frontend.scala 165:14] + inst fpuOpt of FPU @[FPU.scala 761:62] + fpuOpt.io is invalid + fpuOpt.clock <= clock + fpuOpt.reset <= reset + inst dcacheArb of HellaCacheArbiter @[HellaCache.scala 189:25] + dcacheArb.io is invalid + dcacheArb.clock <= clock + dcacheArb.reset <= reset + dcache.io.cpu <- dcacheArb.io.mem @[HellaCache.scala 190:30] + inst ptwOpt of PTW @[PTW.scala 200:49] + ptwOpt.io is invalid + ptwOpt.clock <= clock + ptwOpt.reset <= reset + fpuOpt.io.cp_req.valid <= UInt<1>("h00") @[LegacyRoCC.scala 64:27] + fpuOpt.io.cp_resp.ready <= UInt<1>("h00") @[LegacyRoCC.scala 65:28] + inst core of Rocket @[Tile.scala 122:20] + core.io is invalid + core.clock <= clock + core.reset <= reset + core.io.hartid <= io.hartid @[Tile.scala 123:18] + frontend.io.cpu <- core.io.imem @[Tile.scala 124:32] + frontend.io.resetVector <= io.resetVector @[Tile.scala 125:40] + core.io.fpu <- fpuOpt.io @[Tile.scala 127:39] + core.io.ptw <- ptwOpt.io.dpath @[Tile.scala 128:39] + core.io.interrupts.debug <= io.interrupts.0[0] @[Tile.scala 138:28] + core.io.interrupts.msip <= io.interrupts.0[1] @[Tile.scala 139:28] + core.io.interrupts.mtip <= io.interrupts.0[2] @[Tile.scala 140:28] + core.io.interrupts.meip <= io.interrupts.0[3] @[Tile.scala 141:28] + core.io.interrupts.seip <= io.interrupts.0[4] @[Tile.scala 142:39] + dcacheArb.io.requestor[0] <- ptwOpt.io.mem @[Tile.scala 151:26] + dcacheArb.io.requestor[1] <- core.io.dmem @[Tile.scala 151:26] + ptwOpt.io.requestor[0] <- dcache.io.ptw @[Tile.scala 152:44] + ptwOpt.io.requestor[1] <- frontend.io.ptw @[Tile.scala 152:44] + + module Queue_36 : + input clock : Clock input reset : UInt<1> - input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} io is invalid - node T_322 = and(io.ar.ready, io.ar.valid) - when T_322 : - node T_324 = eq(reset, UInt<1>("h00")) - when T_324 : - printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr) - skip - skip - node T_325 = and(io.aw.ready, io.aw.valid) - when T_325 : - node T_327 = eq(reset, UInt<1>("h00")) - when T_327 : - printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr) - skip - skip - inst r_queue of Queue_36 - r_queue.io is invalid - r_queue.clk <= clk - r_queue.reset <= reset - r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - node T_346 = eq(responding, UInt<1>("h00")) - node T_347 = and(T_346, r_queue.io.deq.valid) - when T_347 : - responding <= UInt<1>("h01") - beats_left <= r_queue.io.deq.bits.len - skip - node T_349 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_349 - io.r.bits.id <= r_queue.io.deq.bits.id - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<2>("h03") - node T_352 = eq(beats_left, UInt<1>("h00")) - io.r.bits.last <= T_352 - node T_353 = and(io.r.ready, io.r.valid) - node T_354 = and(T_353, io.r.bits.last) - r_queue.io.deq.ready <= T_354 - node T_355 = and(io.r.ready, io.r.valid) - when T_355 : - node T_357 = eq(beats_left, UInt<1>("h00")) - when T_357 : - responding <= UInt<1>("h00") - skip - node T_360 = eq(T_357, UInt<1>("h00")) - when T_360 : - node T_362 = sub(beats_left, UInt<1>("h01")) - node T_363 = tail(T_362, 1) - beats_left <= T_363 - skip - skip - reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - io.w.ready <= draining - node T_366 = and(io.aw.ready, io.aw.valid) - when T_366 : - draining <= UInt<1>("h01") - skip - node T_368 = and(io.w.ready, io.w.valid) - node T_369 = and(T_368, io.w.bits.last) - when T_369 : - draining <= UInt<1>("h00") - skip - inst b_queue of Queue_37 - b_queue.io is invalid - b_queue.clk <= clk - b_queue.reset <= reset - node T_374 = eq(draining, UInt<1>("h00")) - node T_375 = and(io.aw.valid, T_374) - b_queue.io.enq.valid <= T_375 - b_queue.io.enq.bits <= io.aw.bits.id - node T_377 = eq(draining, UInt<1>("h00")) - node T_378 = and(b_queue.io.enq.ready, T_377) - io.aw.ready <= T_378 - node T_380 = eq(draining, UInt<1>("h00")) - node T_381 = and(b_queue.io.deq.valid, T_380) - io.b.valid <= T_381 - io.b.bits.id <= b_queue.io.deq.bits - io.b.bits.resp <= UInt<2>("h03") - node T_384 = eq(draining, UInt<1>("h00")) - node T_385 = and(io.b.ready, T_384) - b_queue.io.deq.ready <= T_385 - - module NastiRouter_39 : - input clk : Clock + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_37 : + input clock : Clock input reset : UInt<1> - output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - - io is invalid - node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) - node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) - node T_1440 = and(T_1437, T_1439) - node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) - node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000")) - node T_1445 = and(T_1442, T_1444) - node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000")) - node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000")) - node T_1450 = and(T_1447, T_1449) - node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000")) - node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000")) - node T_1455 = and(T_1452, T_1454) - wire T_1457 : UInt<1>[4] - T_1457[0] <= T_1440 - T_1457[1] <= T_1445 - T_1457[2] <= T_1450 - T_1457[3] <= T_1455 - node T_1463 = cat(T_1457[3], T_1457[2]) - node T_1464 = cat(T_1457[1], T_1457[0]) - node ar_route = cat(T_1463, T_1464) - node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00")) - node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000")) - node T_1470 = and(T_1467, T_1469) - node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) - node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000")) - node T_1475 = and(T_1472, T_1474) - node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000")) - node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000")) - node T_1480 = and(T_1477, T_1479) - node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000")) - node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000")) - node T_1485 = and(T_1482, T_1484) - wire T_1487 : UInt<1>[4] - T_1487[0] <= T_1470 - T_1487[1] <= T_1475 - T_1487[2] <= T_1480 - T_1487[3] <= T_1485 - node T_1493 = cat(T_1487[3], T_1487[2]) - node T_1494 = cat(T_1487[1], T_1487[0]) - node aw_route = cat(T_1493, T_1494) - node T_1499 = bits(ar_route, 0, 0) - node T_1500 = and(io.master.ar.valid, T_1499) - io.slave[0].ar.valid <= T_1500 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bits(ar_route, 0, 0) - node T_1502 = and(io.slave[0].ar.ready, T_1501) - node T_1503 = or(UInt<1>("h00"), T_1502) - node T_1504 = bits(aw_route, 0, 0) - node T_1505 = and(io.master.aw.valid, T_1504) - io.slave[0].aw.valid <= T_1505 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bits(aw_route, 0, 0) - node T_1507 = and(io.slave[0].aw.ready, T_1506) - node T_1508 = or(UInt<1>("h00"), T_1507) - reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1511 : - T_1510 <= UInt<1>("h01") - skip - node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1514 = and(T_1513, io.slave[0].w.bits.last) - when T_1514 : - T_1510 <= UInt<1>("h00") - skip - node T_1516 = and(io.master.w.valid, T_1510) - io.slave[0].w.valid <= T_1516 - io.slave[0].w.bits <- io.master.w.bits - node T_1517 = and(io.slave[0].w.ready, T_1510) - node T_1518 = or(UInt<1>("h00"), T_1517) - node T_1519 = bits(ar_route, 1, 1) - node T_1520 = and(io.master.ar.valid, T_1519) - io.slave[1].ar.valid <= T_1520 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bits(ar_route, 1, 1) - node T_1522 = and(io.slave[1].ar.ready, T_1521) - node T_1523 = or(T_1503, T_1522) - node T_1524 = bits(aw_route, 1, 1) - node T_1525 = and(io.master.aw.valid, T_1524) - io.slave[1].aw.valid <= T_1525 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bits(aw_route, 1, 1) - node T_1527 = and(io.slave[1].aw.ready, T_1526) - node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1531 : - T_1530 <= UInt<1>("h01") - skip - node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1534 = and(T_1533, io.slave[1].w.bits.last) - when T_1534 : - T_1530 <= UInt<1>("h00") - skip - node T_1536 = and(io.master.w.valid, T_1530) - io.slave[1].w.valid <= T_1536 - io.slave[1].w.bits <- io.master.w.bits - node T_1537 = and(io.slave[1].w.ready, T_1530) - node T_1538 = or(T_1518, T_1537) - node T_1539 = bits(ar_route, 2, 2) - node T_1540 = and(io.master.ar.valid, T_1539) - io.slave[2].ar.valid <= T_1540 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bits(ar_route, 2, 2) - node T_1542 = and(io.slave[2].ar.ready, T_1541) - node T_1543 = or(T_1523, T_1542) - node T_1544 = bits(aw_route, 2, 2) - node T_1545 = and(io.master.aw.valid, T_1544) - io.slave[2].aw.valid <= T_1545 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bits(aw_route, 2, 2) - node T_1547 = and(io.slave[2].aw.ready, T_1546) - node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1551 : - T_1550 <= UInt<1>("h01") - skip - node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1554 = and(T_1553, io.slave[2].w.bits.last) - when T_1554 : - T_1550 <= UInt<1>("h00") - skip - node T_1556 = and(io.master.w.valid, T_1550) - io.slave[2].w.valid <= T_1556 - io.slave[2].w.bits <- io.master.w.bits - node T_1557 = and(io.slave[2].w.ready, T_1550) - node T_1558 = or(T_1538, T_1557) - node T_1559 = bits(ar_route, 3, 3) - node T_1560 = and(io.master.ar.valid, T_1559) - io.slave[3].ar.valid <= T_1560 - io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bits(ar_route, 3, 3) - node T_1562 = and(io.slave[3].ar.ready, T_1561) - node ar_ready = or(T_1543, T_1562) - node T_1564 = bits(aw_route, 3, 3) - node T_1565 = and(io.master.aw.valid, T_1564) - io.slave[3].aw.valid <= T_1565 - io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bits(aw_route, 3, 3) - node T_1567 = and(io.slave[3].aw.ready, T_1566) - node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) - when T_1571 : - T_1570 <= UInt<1>("h01") - skip - node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) - node T_1574 = and(T_1573, io.slave[3].w.bits.last) - when T_1574 : - T_1570 <= UInt<1>("h00") - skip - node T_1576 = and(io.master.w.valid, T_1570) - io.slave[3].w.valid <= T_1576 - io.slave[3].w.bits <- io.master.w.bits - node T_1577 = and(io.slave[3].w.ready, T_1570) - node w_ready = or(T_1558, T_1577) - node T_1580 = neq(ar_route, UInt<1>("h00")) - node r_invalid = eq(T_1580, UInt<1>("h00")) - node T_1584 = neq(aw_route, UInt<1>("h00")) - node w_invalid = eq(T_1584, UInt<1>("h00")) - inst err_slave of NastiErrorSlave_40 - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1588 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1588 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1589 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1589 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1590 = and(r_invalid, err_slave.io.ar.ready) - node T_1591 = or(ar_ready, T_1590) - io.master.ar.ready <= T_1591 - node T_1592 = and(w_invalid, err_slave.io.aw.ready) - node T_1593 = or(aw_ready, T_1592) - io.master.aw.ready <= T_1593 - node T_1594 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1594 - inst b_arb of RRArbiter_38 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- io.slave[3].b - r_arb.io.in[3] <- io.slave[3].r - b_arb.io.in[4] <- err_slave.io.b - r_arb.io.in[4] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - - module RRArbiter_45 : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_85 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_87 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_88 = and(_T_85, _T_87) @[Decoupled.scala 188:33] + node _T_89 = and(_T_85, maybe_full) @[Decoupled.scala 189:32] + node _T_90 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_90 + node _T_91 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_91 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_92 = ram[value], clock + _T_92 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_103 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_104 = tail(_T_103, 1) @[Counter.scala 26:22] + value <= _T_104 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_107 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_108 = tail(_T_107, 1) @[Counter.scala 26:22] + value_1 <= _T_108 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_109 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_109 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_111 = eq(_T_88, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_111 @[Decoupled.scala 204:16] + node _T_113 = eq(_T_89, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_113 @[Decoupled.scala 205:16] + infer mport _T_114 = ram[value_1], clock + io.deq.bits <- _T_114 @[Decoupled.scala 206:15] + node _T_123 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_124 = asUInt(_T_123) @[Decoupled.scala 221:40] + node _T_125 = tail(_T_124, 1) @[Decoupled.scala 221:40] + node _T_126 = and(maybe_full, _T_85) @[Decoupled.scala 223:32] + node _T_127 = cat(_T_126, _T_125) @[Cat.scala 30:58] + io.count <= _T_127 @[Decoupled.scala 223:14] + + module Queue_38 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<1>} - - io is invalid - wire T_306 : UInt<1> - T_306 is invalid - io.out.valid <= io.in[T_306].valid - io.out.bits <- io.in[T_306].bits - io.chosen <= T_306 - io.in[T_306].ready <= UInt<1>("h00") - reg T_391 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_392 = gt(UInt<1>("h00"), T_391) - node T_393 = and(io.in[0].valid, T_392) - node T_395 = gt(UInt<1>("h01"), T_391) - node T_396 = and(io.in[1].valid, T_395) - node T_399 = or(UInt<1>("h00"), T_393) - node T_401 = eq(T_399, UInt<1>("h00")) - node T_403 = or(UInt<1>("h00"), T_393) - node T_404 = or(T_403, T_396) - node T_406 = eq(T_404, UInt<1>("h00")) - node T_408 = or(UInt<1>("h00"), T_393) - node T_409 = or(T_408, T_396) - node T_410 = or(T_409, io.in[0].valid) - node T_412 = eq(T_410, UInt<1>("h00")) - node T_414 = gt(UInt<1>("h00"), T_391) - node T_415 = and(UInt<1>("h01"), T_414) - node T_416 = or(T_415, T_406) - node T_418 = gt(UInt<1>("h01"), T_391) - node T_419 = and(T_401, T_418) - node T_420 = or(T_419, T_412) - node T_422 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_423 = mux(UInt<1>("h00"), T_422, T_416) - node T_424 = and(T_423, io.out.ready) - io.in[0].ready <= T_424 - node T_426 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_427 = mux(UInt<1>("h00"), T_426, T_420) - node T_428 = and(T_427, io.out.ready) - io.in[1].ready <= T_428 - node T_431 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_433 = gt(UInt<1>("h01"), T_391) - node T_434 = and(io.in[1].valid, T_433) - node T_436 = mux(T_434, UInt<1>("h01"), T_431) - node T_437 = mux(UInt<1>("h00"), UInt<1>("h01"), T_436) - T_306 <= T_437 - node T_438 = and(io.out.ready, io.out.valid) - when T_438 : - T_391 <= T_306 - skip + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} - module NastiArbiter : - input clk : Clock + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_39 : + input clock : Clock input reset : UInt<1> - output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - - io is invalid - inst T_1767 of RRArbiter_45 - T_1767.io is invalid - T_1767.clk <= clk - T_1767.reset <= reset - inst T_1780 of RRArbiter_45 - T_1780.io is invalid - T_1780.clk <= clk - T_1780.reset <= reset - node T_1781 = bits(io.slave.r.bits.id, 0, 0) - node T_1782 = bits(io.slave.b.bits.id, 0, 0) - reg T_1784 : UInt<1>, clk - reg T_1786 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - node T_1787 = and(T_1780.io.out.ready, T_1780.io.out.valid) - when T_1787 : - T_1784 <= T_1780.io.chosen - T_1786 <= UInt<1>("h00") - skip - node T_1789 = and(io.slave.w.ready, io.slave.w.valid) - node T_1790 = and(T_1789, io.slave.w.bits.last) - when T_1790 : - T_1786 <= UInt<1>("h01") - skip - T_1767.io.in[0] <- io.master[0].ar - node T_1793 = cat(io.master[0].ar.bits.id, UInt<1>("h00")) - T_1767.io.in[0].bits.id <= T_1793 - T_1780.io.in[0] <- io.master[0].aw - node T_1795 = cat(io.master[0].aw.bits.id, UInt<1>("h00")) - T_1780.io.in[0].bits.id <= T_1795 - node T_1797 = eq(T_1781, UInt<1>("h00")) - node T_1798 = and(io.slave.r.valid, T_1797) - io.master[0].r.valid <= T_1798 - io.master[0].r.bits <- io.slave.r.bits - node T_1800 = dshr(io.slave.r.bits.id, UInt<1>("h01")) - io.master[0].r.bits.id <= T_1800 - node T_1802 = eq(T_1782, UInt<1>("h00")) - node T_1803 = and(io.slave.b.valid, T_1802) - io.master[0].b.valid <= T_1803 - io.master[0].b.bits <- io.slave.b.bits - node T_1805 = dshr(io.slave.b.bits.id, UInt<1>("h01")) - io.master[0].b.bits.id <= T_1805 - node T_1807 = eq(T_1784, UInt<1>("h00")) - node T_1808 = and(io.slave.w.ready, T_1807) - node T_1810 = eq(T_1786, UInt<1>("h00")) - node T_1811 = and(T_1808, T_1810) - io.master[0].w.ready <= T_1811 - T_1767.io.in[1] <- io.master[1].ar - node T_1813 = cat(io.master[1].ar.bits.id, UInt<1>("h01")) - T_1767.io.in[1].bits.id <= T_1813 - T_1780.io.in[1] <- io.master[1].aw - node T_1815 = cat(io.master[1].aw.bits.id, UInt<1>("h01")) - T_1780.io.in[1].bits.id <= T_1815 - node T_1817 = eq(T_1781, UInt<1>("h01")) - node T_1818 = and(io.slave.r.valid, T_1817) - io.master[1].r.valid <= T_1818 - io.master[1].r.bits <- io.slave.r.bits - node T_1820 = dshr(io.slave.r.bits.id, UInt<1>("h01")) - io.master[1].r.bits.id <= T_1820 - node T_1822 = eq(T_1782, UInt<1>("h01")) - node T_1823 = and(io.slave.b.valid, T_1822) - io.master[1].b.valid <= T_1823 - io.master[1].b.bits <- io.slave.b.bits - node T_1825 = dshr(io.slave.b.bits.id, UInt<1>("h01")) - io.master[1].b.bits.id <= T_1825 - node T_1827 = eq(T_1784, UInt<1>("h01")) - node T_1828 = and(io.slave.w.ready, T_1827) - node T_1830 = eq(T_1786, UInt<1>("h00")) - node T_1831 = and(T_1828, T_1830) - io.master[1].w.ready <= T_1831 - io.slave.r.ready <= io.master[T_1781].r.ready - io.slave.b.ready <= io.master[T_1782].b.ready - io.slave.w.bits <- io.master[T_1784].w.bits - node T_2469 = eq(T_1786, UInt<1>("h00")) - node T_2470 = and(io.master[T_1784].w.valid, T_2469) - io.slave.w.valid <= T_2470 - io.slave.ar <- T_1767.io.out - io.slave.aw.bits <- T_1780.io.out.bits - node T_2471 = and(T_1780.io.out.valid, T_1786) - io.slave.aw.valid <= T_2471 - node T_2472 = and(io.slave.aw.ready, T_1786) - T_1780.io.out.ready <= T_2472 - - module NastiCrossbar : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_40 : + input clock : Clock input reset : UInt<1> - output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - - io is invalid - inst T_2710 of NastiRouter - T_2710.io is invalid - T_2710.clk <= clk - T_2710.reset <= reset - inst T_2711 of NastiRouter_39 - T_2711.io is invalid - T_2711.clk <= clk - T_2711.reset <= reset - wire T_4146 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2] - T_4146[0] <- T_2710.io - T_4146[1] <- T_2711.io - inst T_8449 of NastiArbiter - T_8449.io is invalid - T_8449.clk <= clk - T_8449.reset <= reset - inst T_8450 of NastiArbiter - T_8450.io is invalid - T_8450.clk <= clk - T_8450.reset <= reset - inst T_8451 of NastiArbiter - T_8451.io is invalid - T_8451.clk <= clk - T_8451.reset <= reset - inst T_8452 of NastiArbiter - T_8452.io is invalid - T_8452.clk <= clk - T_8452.reset <= reset - wire T_10206 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4] - T_10206[0] <- T_8449.io - T_10206[1] <- T_8450.io - T_10206[2] <- T_8451.io - T_10206[3] <- T_8452.io - T_4146[0].master <- io.masters[0] - T_4146[1].master <- io.masters[1] - wire T_19131 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_19131[0] <- T_4146[0].slave[0] - T_19131[1] <- T_4146[1].slave[0] - T_10206[0].master <= T_19131 - io.slaves[0] <- T_10206[0].slave - wire T_19768 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_19768[0] <- T_4146[0].slave[1] - T_19768[1] <- T_4146[1].slave[1] - T_10206[1].master <= T_19768 - io.slaves[1] <- T_10206[1].slave - wire T_20405 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_20405[0] <- T_4146[0].slave[2] - T_20405[1] <- T_4146[1].slave[2] - T_10206[2].master <= T_20405 - io.slaves[2] <- T_10206[2].slave - wire T_21042 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_21042[0] <- T_4146[0].slave[3] - T_21042[1] <- T_4146[1].slave[3] - T_10206[3].master <= T_21042 - io.slaves[3] <- T_10206[3].slave - - module RRArbiter_62 : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {sink : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_36 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_38 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_39 = and(_T_36, _T_38) @[Decoupled.scala 188:33] + node _T_40 = and(_T_36, maybe_full) @[Decoupled.scala 189:32] + node _T_41 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_41 + node _T_42 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_42 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_43 = ram[value], clock + _T_43 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_47 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_48 = tail(_T_47, 1) @[Counter.scala 26:22] + value <= _T_48 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_51 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_52 = tail(_T_51, 1) @[Counter.scala 26:22] + value_1 <= _T_52 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_53 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_53 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_55 = eq(_T_39, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_55 @[Decoupled.scala 204:16] + node _T_57 = eq(_T_40, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_57 @[Decoupled.scala 205:16] + infer mport _T_58 = ram[value_1], clock + io.deq.bits <- _T_58 @[Decoupled.scala 206:15] + node _T_60 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_61 = asUInt(_T_60) @[Decoupled.scala 221:40] + node _T_62 = tail(_T_61, 1) @[Decoupled.scala 221:40] + node _T_63 = and(maybe_full, _T_36) @[Decoupled.scala 223:32] + node _T_64 = cat(_T_63, _T_62) @[Cat.scala 30:58] + io.count <= _T_64 @[Decoupled.scala 223:14] + + module Queue_41 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<2>} - - io is invalid - wire T_174 : UInt<2> - T_174 is invalid - io.out.valid <= io.in[T_174].valid - io.out.bits <- io.in[T_174].bits - io.chosen <= T_174 - io.in[T_174].ready <= UInt<1>("h00") - reg T_211 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_212 = gt(UInt<1>("h00"), T_211) - node T_213 = and(io.in[0].valid, T_212) - node T_215 = gt(UInt<1>("h01"), T_211) - node T_216 = and(io.in[1].valid, T_215) - node T_218 = gt(UInt<2>("h02"), T_211) - node T_219 = and(io.in[2].valid, T_218) - node T_221 = gt(UInt<2>("h03"), T_211) - node T_222 = and(io.in[3].valid, T_221) - node T_225 = or(UInt<1>("h00"), T_213) - node T_227 = eq(T_225, UInt<1>("h00")) - node T_229 = or(UInt<1>("h00"), T_213) - node T_230 = or(T_229, T_216) - node T_232 = eq(T_230, UInt<1>("h00")) - node T_234 = or(UInt<1>("h00"), T_213) - node T_235 = or(T_234, T_216) - node T_236 = or(T_235, T_219) - node T_238 = eq(T_236, UInt<1>("h00")) - node T_240 = or(UInt<1>("h00"), T_213) - node T_241 = or(T_240, T_216) - node T_242 = or(T_241, T_219) - node T_243 = or(T_242, T_222) - node T_245 = eq(T_243, UInt<1>("h00")) - node T_247 = or(UInt<1>("h00"), T_213) - node T_248 = or(T_247, T_216) - node T_249 = or(T_248, T_219) - node T_250 = or(T_249, T_222) - node T_251 = or(T_250, io.in[0].valid) - node T_253 = eq(T_251, UInt<1>("h00")) - node T_255 = or(UInt<1>("h00"), T_213) - node T_256 = or(T_255, T_216) - node T_257 = or(T_256, T_219) - node T_258 = or(T_257, T_222) - node T_259 = or(T_258, io.in[0].valid) - node T_260 = or(T_259, io.in[1].valid) - node T_262 = eq(T_260, UInt<1>("h00")) - node T_264 = or(UInt<1>("h00"), T_213) - node T_265 = or(T_264, T_216) - node T_266 = or(T_265, T_219) - node T_267 = or(T_266, T_222) - node T_268 = or(T_267, io.in[0].valid) - node T_269 = or(T_268, io.in[1].valid) - node T_270 = or(T_269, io.in[2].valid) - node T_272 = eq(T_270, UInt<1>("h00")) - node T_274 = gt(UInt<1>("h00"), T_211) - node T_275 = and(UInt<1>("h01"), T_274) - node T_276 = or(T_275, T_245) - node T_278 = gt(UInt<1>("h01"), T_211) - node T_279 = and(T_227, T_278) - node T_280 = or(T_279, T_253) - node T_282 = gt(UInt<2>("h02"), T_211) - node T_283 = and(T_232, T_282) - node T_284 = or(T_283, T_262) - node T_286 = gt(UInt<2>("h03"), T_211) - node T_287 = and(T_238, T_286) - node T_288 = or(T_287, T_272) - node T_290 = eq(UInt<2>("h03"), UInt<1>("h00")) - node T_291 = mux(UInt<1>("h00"), T_290, T_276) - node T_292 = and(T_291, io.out.ready) - io.in[0].ready <= T_292 - node T_294 = eq(UInt<2>("h03"), UInt<1>("h01")) - node T_295 = mux(UInt<1>("h00"), T_294, T_280) - node T_296 = and(T_295, io.out.ready) - io.in[1].ready <= T_296 - node T_298 = eq(UInt<2>("h03"), UInt<2>("h02")) - node T_299 = mux(UInt<1>("h00"), T_298, T_284) - node T_300 = and(T_299, io.out.ready) - io.in[2].ready <= T_300 - node T_302 = eq(UInt<2>("h03"), UInt<2>("h03")) - node T_303 = mux(UInt<1>("h00"), T_302, T_288) - node T_304 = and(T_303, io.out.ready) - io.in[3].ready <= T_304 - node T_307 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) - node T_309 = mux(io.in[1].valid, UInt<1>("h01"), T_307) - node T_311 = mux(io.in[0].valid, UInt<1>("h00"), T_309) - node T_313 = gt(UInt<2>("h03"), T_211) - node T_314 = and(io.in[3].valid, T_313) - node T_316 = mux(T_314, UInt<2>("h03"), T_311) - node T_318 = gt(UInt<2>("h02"), T_211) - node T_319 = and(io.in[2].valid, T_318) - node T_321 = mux(T_319, UInt<2>("h02"), T_316) - node T_323 = gt(UInt<1>("h01"), T_211) - node T_324 = and(io.in[1].valid, T_323) - node T_326 = mux(T_324, UInt<1>("h01"), T_321) - node T_327 = mux(UInt<1>("h00"), UInt<2>("h03"), T_326) - T_174 <= T_327 - node T_328 = and(io.out.ready, io.out.valid) - when T_328 : - T_211 <= T_174 - skip + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, count : UInt<2>} - module JunctionsPeekingArbiter_63 : - input clk : Clock + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_78 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_80 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_81 = and(_T_78, _T_80) @[Decoupled.scala 188:33] + node _T_82 = and(_T_78, maybe_full) @[Decoupled.scala 189:32] + node _T_83 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_83 + node _T_84 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_84 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_85 = ram[value], clock + _T_85 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_95 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_96 = tail(_T_95, 1) @[Counter.scala 26:22] + value <= _T_96 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_99 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_100 = tail(_T_99, 1) @[Counter.scala 26:22] + value_1 <= _T_100 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_101 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_101 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_103 = eq(_T_81, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_103 @[Decoupled.scala 204:16] + node _T_105 = eq(_T_82, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_105 @[Decoupled.scala 205:16] + infer mport _T_106 = ram[value_1], clock + io.deq.bits <- _T_106 @[Decoupled.scala 206:15] + node _T_114 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_115 = asUInt(_T_114) @[Decoupled.scala 221:40] + node _T_116 = tail(_T_115, 1) @[Decoupled.scala 221:40] + node _T_117 = and(maybe_full, _T_78) @[Decoupled.scala 223:32] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + io.count <= _T_118 @[Decoupled.scala 223:14] + + module Queue_42 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - - io is invalid - reg T_243 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg T_245 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_247 : UInt<1>[4] - T_247[0] <= io.in[0].valid - T_247[1] <= io.in[1].valid - T_247[2] <= io.in[2].valid - T_247[3] <= io.in[3].valid - node T_254 = add(T_243, UInt<1>("h01")) - node T_255 = tail(T_254, 1) - node T_257 = lt(T_255, UInt<3>("h04")) - node T_259 = add(UInt<1>("h00"), T_255) - node T_260 = tail(T_259, 1) - node T_263 = sub(T_255, UInt<3>("h04")) - node T_264 = tail(T_263, 1) - node T_266 = mux(T_257, T_247[T_260], T_247[T_264]) - node T_268 = lt(T_255, UInt<2>("h03")) - node T_270 = add(UInt<1>("h01"), T_255) - node T_271 = tail(T_270, 1) - node T_274 = sub(T_255, UInt<2>("h03")) - node T_275 = tail(T_274, 1) - node T_277 = mux(T_268, T_247[T_271], T_247[T_275]) - node T_279 = lt(T_255, UInt<2>("h02")) - node T_281 = add(UInt<2>("h02"), T_255) - node T_282 = tail(T_281, 1) - node T_285 = sub(T_255, UInt<2>("h02")) - node T_286 = tail(T_285, 1) - node T_288 = mux(T_279, T_247[T_282], T_247[T_286]) - node T_290 = lt(T_255, UInt<1>("h01")) - node T_292 = add(UInt<2>("h03"), T_255) - node T_293 = tail(T_292, 1) - node T_296 = sub(T_255, UInt<1>("h01")) - node T_297 = tail(T_296, 1) - node T_299 = mux(T_290, T_247[T_293], T_247[T_297]) - wire T_301 : UInt<1>[4] - T_301[0] <= T_266 - T_301[1] <= T_277 - T_301[2] <= T_288 - T_301[3] <= T_299 - wire T_312 : UInt<2>[4] - T_312[0] <= UInt<1>("h00") - T_312[1] <= UInt<1>("h01") - T_312[2] <= UInt<2>("h02") - T_312[3] <= UInt<2>("h03") - node T_319 = add(T_243, UInt<1>("h01")) - node T_320 = tail(T_319, 1) - node T_322 = lt(T_320, UInt<3>("h04")) - node T_324 = add(UInt<1>("h00"), T_320) - node T_325 = tail(T_324, 1) - node T_328 = sub(T_320, UInt<3>("h04")) - node T_329 = tail(T_328, 1) - node T_331 = mux(T_322, T_312[T_325], T_312[T_329]) - node T_333 = lt(T_320, UInt<2>("h03")) - node T_335 = add(UInt<1>("h01"), T_320) - node T_336 = tail(T_335, 1) - node T_339 = sub(T_320, UInt<2>("h03")) - node T_340 = tail(T_339, 1) - node T_342 = mux(T_333, T_312[T_336], T_312[T_340]) - node T_344 = lt(T_320, UInt<2>("h02")) - node T_346 = add(UInt<2>("h02"), T_320) - node T_347 = tail(T_346, 1) - node T_350 = sub(T_320, UInt<2>("h02")) - node T_351 = tail(T_350, 1) - node T_353 = mux(T_344, T_312[T_347], T_312[T_351]) - node T_355 = lt(T_320, UInt<1>("h01")) - node T_357 = add(UInt<2>("h03"), T_320) - node T_358 = tail(T_357, 1) - node T_361 = sub(T_320, UInt<1>("h01")) - node T_362 = tail(T_361, 1) - node T_364 = mux(T_355, T_312[T_358], T_312[T_362]) - wire T_366 : UInt<2>[4] - T_366[0] <= T_331 - T_366[1] <= T_342 - T_366[2] <= T_353 - T_366[3] <= T_364 - node T_372 = mux(T_301[2], T_366[2], T_366[3]) - node T_373 = mux(T_301[1], T_366[1], T_372) - node T_374 = mux(T_301[0], T_366[0], T_373) - node T_375 = mux(T_245, T_243, T_374) - node T_377 = eq(T_375, UInt<1>("h00")) - node T_378 = and(io.out.ready, T_377) - io.in[0].ready <= T_378 - node T_380 = eq(T_375, UInt<1>("h01")) - node T_381 = and(io.out.ready, T_380) - io.in[1].ready <= T_381 - node T_383 = eq(T_375, UInt<2>("h02")) - node T_384 = and(io.out.ready, T_383) - io.in[2].ready <= T_384 - node T_386 = eq(T_375, UInt<2>("h03")) - node T_387 = and(io.out.ready, T_386) - io.in[3].ready <= T_387 - io.out.valid <= io.in[T_375].valid - io.out.bits <- io.in[T_375].bits - node T_418 = and(io.out.ready, io.out.valid) - when T_418 : - node T_420 = eq(T_245, UInt<1>("h00")) - node T_422 = and(T_420, UInt<1>("h01")) - when T_422 : - T_243 <= T_374 - T_245 <= UInt<1>("h01") - skip - when io.out.bits.last : - T_245 <= UInt<1>("h00") - skip - skip + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, count : UInt<2>} - module NastiRouter_58 : - input clk : Clock + io is invalid + io is invalid + cmem ram : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_85 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_87 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_88 = and(_T_85, _T_87) @[Decoupled.scala 188:33] + node _T_89 = and(_T_85, maybe_full) @[Decoupled.scala 189:32] + node _T_90 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_90 + node _T_91 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_91 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_92 = ram[value], clock + _T_92 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_103 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_104 = tail(_T_103, 1) @[Counter.scala 26:22] + value <= _T_104 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_107 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_108 = tail(_T_107, 1) @[Counter.scala 26:22] + value_1 <= _T_108 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_109 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_109 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_111 = eq(_T_88, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_111 @[Decoupled.scala 204:16] + node _T_113 = eq(_T_89, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_113 @[Decoupled.scala 205:16] + infer mport _T_114 = ram[value_1], clock + io.deq.bits <- _T_114 @[Decoupled.scala 206:15] + node _T_123 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_124 = asUInt(_T_123) @[Decoupled.scala 221:40] + node _T_125 = tail(_T_124, 1) @[Decoupled.scala 221:40] + node _T_126 = and(maybe_full, _T_85) @[Decoupled.scala 223:32] + node _T_127 = cat(_T_126, _T_125) @[Cat.scala 30:58] + io.count <= _T_127 @[Decoupled.scala 223:14] + + module TLBuffer : + input clock : Clock input reset : UInt<1> - output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - - io is invalid - node T_1278 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) - node T_1280 = lt(io.master.ar.bits.addr, UInt<31>("h040008000")) - node T_1281 = and(T_1278, T_1280) - node T_1283 = geq(io.master.ar.bits.addr, UInt<31>("h040008000")) - node T_1285 = lt(io.master.ar.bits.addr, UInt<31>("h040010000")) - node T_1286 = and(T_1283, T_1285) - node T_1288 = geq(io.master.ar.bits.addr, UInt<31>("h040010000")) - node T_1290 = lt(io.master.ar.bits.addr, UInt<31>("h040010200")) - node T_1291 = and(T_1288, T_1290) - wire T_1293 : UInt<1>[3] - T_1293[0] <= T_1281 - T_1293[1] <= T_1286 - T_1293[2] <= T_1291 - node T_1298 = cat(T_1293[1], T_1293[0]) - node ar_route = cat(T_1293[2], T_1298) - node T_1301 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) - node T_1303 = lt(io.master.aw.bits.addr, UInt<31>("h040008000")) - node T_1304 = and(T_1301, T_1303) - node T_1306 = geq(io.master.aw.bits.addr, UInt<31>("h040008000")) - node T_1308 = lt(io.master.aw.bits.addr, UInt<31>("h040010000")) - node T_1309 = and(T_1306, T_1308) - node T_1311 = geq(io.master.aw.bits.addr, UInt<31>("h040010000")) - node T_1313 = lt(io.master.aw.bits.addr, UInt<31>("h040010200")) - node T_1314 = and(T_1311, T_1313) - wire T_1316 : UInt<1>[3] - T_1316[0] <= T_1304 - T_1316[1] <= T_1309 - T_1316[2] <= T_1314 - node T_1321 = cat(T_1316[1], T_1316[0]) - node aw_route = cat(T_1316[2], T_1321) - node T_1326 = bits(ar_route, 0, 0) - node T_1327 = and(io.master.ar.valid, T_1326) - io.slave[0].ar.valid <= T_1327 - io.slave[0].ar.bits <- io.master.ar.bits - node T_1328 = bits(ar_route, 0, 0) - node T_1329 = and(io.slave[0].ar.ready, T_1328) - node T_1330 = or(UInt<1>("h00"), T_1329) - node T_1331 = bits(aw_route, 0, 0) - node T_1332 = and(io.master.aw.valid, T_1331) - io.slave[0].aw.valid <= T_1332 - io.slave[0].aw.bits <- io.master.aw.bits - node T_1333 = bits(aw_route, 0, 0) - node T_1334 = and(io.slave[0].aw.ready, T_1333) - node T_1335 = or(UInt<1>("h00"), T_1334) - reg T_1337 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1338 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) - when T_1338 : - T_1337 <= UInt<1>("h01") - skip - node T_1340 = and(io.slave[0].w.ready, io.slave[0].w.valid) - node T_1341 = and(T_1340, io.slave[0].w.bits.last) - when T_1341 : - T_1337 <= UInt<1>("h00") - skip - node T_1343 = and(io.master.w.valid, T_1337) - io.slave[0].w.valid <= T_1343 - io.slave[0].w.bits <- io.master.w.bits - node T_1344 = and(io.slave[0].w.ready, T_1337) - node T_1345 = or(UInt<1>("h00"), T_1344) - node T_1346 = bits(ar_route, 1, 1) - node T_1347 = and(io.master.ar.valid, T_1346) - io.slave[1].ar.valid <= T_1347 - io.slave[1].ar.bits <- io.master.ar.bits - node T_1348 = bits(ar_route, 1, 1) - node T_1349 = and(io.slave[1].ar.ready, T_1348) - node T_1350 = or(T_1330, T_1349) - node T_1351 = bits(aw_route, 1, 1) - node T_1352 = and(io.master.aw.valid, T_1351) - io.slave[1].aw.valid <= T_1352 - io.slave[1].aw.bits <- io.master.aw.bits - node T_1353 = bits(aw_route, 1, 1) - node T_1354 = and(io.slave[1].aw.ready, T_1353) - node T_1355 = or(T_1335, T_1354) - reg T_1357 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1358 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) - when T_1358 : - T_1357 <= UInt<1>("h01") - skip - node T_1360 = and(io.slave[1].w.ready, io.slave[1].w.valid) - node T_1361 = and(T_1360, io.slave[1].w.bits.last) - when T_1361 : - T_1357 <= UInt<1>("h00") - skip - node T_1363 = and(io.master.w.valid, T_1357) - io.slave[1].w.valid <= T_1363 - io.slave[1].w.bits <- io.master.w.bits - node T_1364 = and(io.slave[1].w.ready, T_1357) - node T_1365 = or(T_1345, T_1364) - node T_1366 = bits(ar_route, 2, 2) - node T_1367 = and(io.master.ar.valid, T_1366) - io.slave[2].ar.valid <= T_1367 - io.slave[2].ar.bits <- io.master.ar.bits - node T_1368 = bits(ar_route, 2, 2) - node T_1369 = and(io.slave[2].ar.ready, T_1368) - node ar_ready = or(T_1350, T_1369) - node T_1371 = bits(aw_route, 2, 2) - node T_1372 = and(io.master.aw.valid, T_1371) - io.slave[2].aw.valid <= T_1372 - io.slave[2].aw.bits <- io.master.aw.bits - node T_1373 = bits(aw_route, 2, 2) - node T_1374 = and(io.slave[2].aw.ready, T_1373) - node aw_ready = or(T_1355, T_1374) - reg T_1377 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1378 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) - when T_1378 : - T_1377 <= UInt<1>("h01") - skip - node T_1380 = and(io.slave[2].w.ready, io.slave[2].w.valid) - node T_1381 = and(T_1380, io.slave[2].w.bits.last) - when T_1381 : - T_1377 <= UInt<1>("h00") - skip - node T_1383 = and(io.master.w.valid, T_1377) - io.slave[2].w.valid <= T_1383 - io.slave[2].w.bits <- io.master.w.bits - node T_1384 = and(io.slave[2].w.ready, T_1377) - node w_ready = or(T_1365, T_1384) - node T_1387 = neq(ar_route, UInt<1>("h00")) - node r_invalid = eq(T_1387, UInt<1>("h00")) - node T_1391 = neq(aw_route, UInt<1>("h00")) - node w_invalid = eq(T_1391, UInt<1>("h00")) - inst err_slave of NastiErrorSlave_40 - err_slave.io is invalid - err_slave.clk <= clk - err_slave.reset <= reset - node T_1395 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1395 - err_slave.io.ar.bits <- io.master.ar.bits - node T_1396 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1396 - err_slave.io.aw.bits <- io.master.aw.bits - err_slave.io.w.valid <= io.master.w.valid - err_slave.io.w.bits <- io.master.w.bits - node T_1397 = and(r_invalid, err_slave.io.ar.ready) - node T_1398 = or(ar_ready, T_1397) - io.master.ar.ready <= T_1398 - node T_1399 = and(w_invalid, err_slave.io.aw.ready) - node T_1400 = or(aw_ready, T_1399) - io.master.aw.ready <= T_1400 - node T_1401 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1401 - inst b_arb of RRArbiter_62 - b_arb.io is invalid - b_arb.clk <= clk - b_arb.reset <= reset - inst r_arb of JunctionsPeekingArbiter_63 - r_arb.io is invalid - r_arb.clk <= clk - r_arb.reset <= reset - b_arb.io.in[0] <- io.slave[0].b - r_arb.io.in[0] <- io.slave[0].r - b_arb.io.in[1] <- io.slave[1].b - r_arb.io.in[1] <- io.slave[1].r - b_arb.io.in[2] <- io.slave[2].b - r_arb.io.in[2] <- io.slave[2].r - b_arb.io.in[3] <- err_slave.io.b - r_arb.io.in[3] <- err_slave.io.r - io.master.b <- b_arb.io.out - io.master.r <- r_arb.io.out - - module NastiCrossbar_57 : - input clk : Clock + output io : {flip in : {1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, out : {1 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}, 0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_36 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.a.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.a.bits @[Decoupled.scala 255:19] + io.in.0.a.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.a <- Queue.io.deq @[Buffer.scala 58:13] + inst Queue_1 of Queue_37 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.out.0.d.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.out.0.d.bits @[Decoupled.scala 255:19] + io.out.0.d.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.d <- Queue_1.io.deq @[Buffer.scala 59:13] + inst Queue_2 of Queue_38 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.b <- Queue_2.io.deq @[Buffer.scala 62:15] + inst Queue_3 of Queue_39 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.in.0.c.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.in.0.c.bits @[Decoupled.scala 255:19] + io.in.0.c.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.c <- Queue_3.io.deq @[Buffer.scala 63:15] + inst Queue_4 of Queue_40 @[Decoupled.scala 253:19] + Queue_4.io is invalid + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= io.in.0.e.valid @[Decoupled.scala 254:20] + Queue_4.io.enq.bits <- io.in.0.e.bits @[Decoupled.scala 255:19] + io.in.0.e.ready <= Queue_4.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.e <- Queue_4.io.deq @[Buffer.scala 64:15] + inst Queue_5 of Queue_41 @[Decoupled.scala 253:19] + Queue_5.io is invalid + Queue_5.clock <= clock + Queue_5.reset <= reset + Queue_5.io.enq.valid <= io.in.1.a.valid @[Decoupled.scala 254:20] + Queue_5.io.enq.bits <- io.in.1.a.bits @[Decoupled.scala 255:19] + io.in.1.a.ready <= Queue_5.io.enq.ready @[Decoupled.scala 256:15] + io.out.1.a <- Queue_5.io.deq @[Buffer.scala 58:13] + inst Queue_6 of Queue_42 @[Decoupled.scala 253:19] + Queue_6.io is invalid + Queue_6.clock <= clock + Queue_6.reset <= reset + Queue_6.io.enq.valid <= io.out.1.d.valid @[Decoupled.scala 254:20] + Queue_6.io.enq.bits <- io.out.1.d.bits @[Decoupled.scala 255:19] + io.out.1.d.ready <= Queue_6.io.enq.ready @[Decoupled.scala 256:15] + io.in.1.d <- Queue_6.io.deq @[Buffer.scala 59:13] + io.in.1.b.valid <= UInt<1>("h00") @[Buffer.scala 66:20] + io.in.1.c.ready <= UInt<1>("h01") @[Buffer.scala 67:20] + io.in.1.e.ready <= UInt<1>("h01") @[Buffer.scala 68:20] + io.out.1.b.ready <= UInt<1>("h01") @[Buffer.scala 69:21] + io.out.1.c.valid <= UInt<1>("h00") @[Buffer.scala 70:21] + io.out.1.e.valid <= UInt<1>("h00") @[Buffer.scala 71:21] + + module TLMonitor_34 : + input clock : Clock input reset : UInt<1> - output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[2]} io is invalid - inst T_2233 of NastiRouter_58 - T_2233.io is invalid - T_2233.clk <= clk - T_2233.reset <= reset - T_2233.io.master <- io.masters[0] - io.slaves <= T_2233.io.slave + io is invalid + when io.in[0].a.valid : @[RocketTiles.scala 50:21] + node _T_861 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_862 = or(_T_861, reset) @[RocketTiles.scala 50:21] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_864 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_866 = eq(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_869 : UInt<1>[1] @[Parameters.scala 228:27] + _T_869 is invalid @[Parameters.scala 228:27] + _T_869[0] <= _T_866 @[Parameters.scala 228:27] + node _T_874 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_875 = dshl(_T_874, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_876 = bits(_T_875, 7, 0) @[package.scala 19:76] + node _T_877 = not(_T_876) @[package.scala 19:40] + node _T_878 = and(io.in[0].a.bits.address, _T_877) @[Edges.scala 17:16] + node _T_880 = eq(_T_878, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_882 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_883 = dshl(UInt<1>("h01"), _T_882) @[OneHot.scala 49:12] + node _T_884 = bits(_T_883, 2, 0) @[OneHot.scala 49:37] + node _T_886 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_888 = bits(_T_884, 2, 2) @[package.scala 44:26] + node _T_889 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_891 = eq(_T_889, UInt<1>("h00")) @[package.scala 46:20] + node _T_892 = and(UInt<1>("h01"), _T_891) @[package.scala 49:27] + node _T_893 = and(_T_888, _T_892) @[package.scala 50:38] + node _T_894 = or(_T_886, _T_893) @[package.scala 50:29] + node _T_895 = and(UInt<1>("h01"), _T_889) @[package.scala 49:27] + node _T_896 = and(_T_888, _T_895) @[package.scala 50:38] + node _T_897 = or(_T_886, _T_896) @[package.scala 50:29] + node _T_898 = bits(_T_884, 1, 1) @[package.scala 44:26] + node _T_899 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[package.scala 46:20] + node _T_902 = and(_T_892, _T_901) @[package.scala 49:27] + node _T_903 = and(_T_898, _T_902) @[package.scala 50:38] + node _T_904 = or(_T_894, _T_903) @[package.scala 50:29] + node _T_905 = and(_T_892, _T_899) @[package.scala 49:27] + node _T_906 = and(_T_898, _T_905) @[package.scala 50:38] + node _T_907 = or(_T_894, _T_906) @[package.scala 50:29] + node _T_908 = and(_T_895, _T_901) @[package.scala 49:27] + node _T_909 = and(_T_898, _T_908) @[package.scala 50:38] + node _T_910 = or(_T_897, _T_909) @[package.scala 50:29] + node _T_911 = and(_T_895, _T_899) @[package.scala 49:27] + node _T_912 = and(_T_898, _T_911) @[package.scala 50:38] + node _T_913 = or(_T_897, _T_912) @[package.scala 50:29] + node _T_914 = bits(_T_884, 0, 0) @[package.scala 44:26] + node _T_915 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[package.scala 46:20] + node _T_918 = and(_T_902, _T_917) @[package.scala 49:27] + node _T_919 = and(_T_914, _T_918) @[package.scala 50:38] + node _T_920 = or(_T_904, _T_919) @[package.scala 50:29] + node _T_921 = and(_T_902, _T_915) @[package.scala 49:27] + node _T_922 = and(_T_914, _T_921) @[package.scala 50:38] + node _T_923 = or(_T_904, _T_922) @[package.scala 50:29] + node _T_924 = and(_T_905, _T_917) @[package.scala 49:27] + node _T_925 = and(_T_914, _T_924) @[package.scala 50:38] + node _T_926 = or(_T_907, _T_925) @[package.scala 50:29] + node _T_927 = and(_T_905, _T_915) @[package.scala 49:27] + node _T_928 = and(_T_914, _T_927) @[package.scala 50:38] + node _T_929 = or(_T_907, _T_928) @[package.scala 50:29] + node _T_930 = and(_T_908, _T_917) @[package.scala 49:27] + node _T_931 = and(_T_914, _T_930) @[package.scala 50:38] + node _T_932 = or(_T_910, _T_931) @[package.scala 50:29] + node _T_933 = and(_T_908, _T_915) @[package.scala 49:27] + node _T_934 = and(_T_914, _T_933) @[package.scala 50:38] + node _T_935 = or(_T_910, _T_934) @[package.scala 50:29] + node _T_936 = and(_T_911, _T_917) @[package.scala 49:27] + node _T_937 = and(_T_914, _T_936) @[package.scala 50:38] + node _T_938 = or(_T_913, _T_937) @[package.scala 50:29] + node _T_939 = and(_T_911, _T_915) @[package.scala 49:27] + node _T_940 = and(_T_914, _T_939) @[package.scala 50:38] + node _T_941 = or(_T_913, _T_940) @[package.scala 50:29] + node _T_942 = cat(_T_923, _T_920) @[Cat.scala 30:58] + node _T_943 = cat(_T_929, _T_926) @[Cat.scala 30:58] + node _T_944 = cat(_T_943, _T_942) @[Cat.scala 30:58] + node _T_945 = cat(_T_935, _T_932) @[Cat.scala 30:58] + node _T_946 = cat(_T_941, _T_938) @[Cat.scala 30:58] + node _T_947 = cat(_T_946, _T_945) @[Cat.scala 30:58] + node _T_948 = cat(_T_947, _T_944) @[Cat.scala 30:58] + node _T_950 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_950 : @[RocketTiles.scala 50:21] + node _T_953 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_955 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_956 = and(_T_953, _T_955) @[Parameters.scala 63:37] + node _T_957 = or(UInt<1>("h00"), _T_956) @[Parameters.scala 132:31] + node _T_959 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_960 = cvt(_T_959) @[Parameters.scala 117:49] + node _T_962 = and(_T_960, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_963 = asSInt(_T_962) @[Parameters.scala 117:52] + node _T_965 = eq(_T_963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_967 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_968 = cvt(_T_967) @[Parameters.scala 117:49] + node _T_970 = and(_T_968, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_971 = asSInt(_T_970) @[Parameters.scala 117:52] + node _T_973 = eq(_T_971, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = or(_T_965, _T_973) @[Parameters.scala 133:42] + node _T_975 = and(_T_957, _T_974) @[Parameters.scala 132:56] + node _T_978 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_980 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_981 = cvt(_T_980) @[Parameters.scala 117:49] + node _T_983 = and(_T_981, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_984 = asSInt(_T_983) @[Parameters.scala 117:52] + node _T_986 = eq(_T_984, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_988 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_989 = cvt(_T_988) @[Parameters.scala 117:49] + node _T_991 = and(_T_989, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_992 = asSInt(_T_991) @[Parameters.scala 117:52] + node _T_994 = eq(_T_992, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_996 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_997 = cvt(_T_996) @[Parameters.scala 117:49] + node _T_999 = and(_T_997, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1000 = asSInt(_T_999) @[Parameters.scala 117:52] + node _T_1002 = eq(_T_1000, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1004 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1005 = cvt(_T_1004) @[Parameters.scala 117:49] + node _T_1007 = and(_T_1005, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1008 = asSInt(_T_1007) @[Parameters.scala 117:52] + node _T_1010 = eq(_T_1008, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = or(_T_986, _T_994) @[Parameters.scala 133:42] + node _T_1012 = or(_T_1011, _T_1002) @[Parameters.scala 133:42] + node _T_1013 = or(_T_1012, _T_1010) @[Parameters.scala 133:42] + node _T_1014 = and(_T_978, _T_1013) @[Parameters.scala 132:56] + node _T_1016 = or(UInt<1>("h00"), _T_975) @[Parameters.scala 134:30] + node _T_1017 = or(_T_1016, _T_1014) @[Parameters.scala 134:30] + node _T_1018 = or(_T_1017, reset) @[RocketTiles.scala 50:21] + node _T_1020 = eq(_T_1018, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1020 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1021 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1023 = eq(_T_1021, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1023 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1025 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_1026 = or(_T_1025, reset) @[RocketTiles.scala 50:21] + node _T_1028 = eq(_T_1026, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1028 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1029 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1031 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1033 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_1034 = or(_T_1033, reset) @[RocketTiles.scala 50:21] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1036 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1037 = not(io.in[0].a.bits.mask) @[RocketTiles.scala 50:21] + node _T_1039 = eq(_T_1037, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1040 = or(_T_1039, reset) @[RocketTiles.scala 50:21] + node _T_1042 = eq(_T_1040, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1042 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1044 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_1044 : @[RocketTiles.scala 50:21] + node _T_1047 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1049 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1050 = and(_T_1047, _T_1049) @[Parameters.scala 63:37] + node _T_1051 = or(UInt<1>("h00"), _T_1050) @[Parameters.scala 132:31] + node _T_1053 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1054 = cvt(_T_1053) @[Parameters.scala 117:49] + node _T_1056 = and(_T_1054, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1057 = asSInt(_T_1056) @[Parameters.scala 117:52] + node _T_1059 = eq(_T_1057, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1061 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1062 = cvt(_T_1061) @[Parameters.scala 117:49] + node _T_1064 = and(_T_1062, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1065 = asSInt(_T_1064) @[Parameters.scala 117:52] + node _T_1067 = eq(_T_1065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1070 = cvt(_T_1069) @[Parameters.scala 117:49] + node _T_1072 = and(_T_1070, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1073 = asSInt(_T_1072) @[Parameters.scala 117:52] + node _T_1075 = eq(_T_1073, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1077 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1078 = cvt(_T_1077) @[Parameters.scala 117:49] + node _T_1080 = and(_T_1078, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1081 = asSInt(_T_1080) @[Parameters.scala 117:52] + node _T_1083 = eq(_T_1081, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1085 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1086 = cvt(_T_1085) @[Parameters.scala 117:49] + node _T_1088 = and(_T_1086, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1089 = asSInt(_T_1088) @[Parameters.scala 117:52] + node _T_1091 = eq(_T_1089, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1092 = or(_T_1059, _T_1067) @[Parameters.scala 133:42] + node _T_1093 = or(_T_1092, _T_1075) @[Parameters.scala 133:42] + node _T_1094 = or(_T_1093, _T_1083) @[Parameters.scala 133:42] + node _T_1095 = or(_T_1094, _T_1091) @[Parameters.scala 133:42] + node _T_1096 = and(_T_1051, _T_1095) @[Parameters.scala 132:56] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1112 = and(_T_1103, _T_1111) @[Parameters.scala 132:56] + node _T_1114 = or(UInt<1>("h00"), _T_1096) @[Parameters.scala 134:30] + node _T_1115 = or(_T_1114, _T_1112) @[Parameters.scala 134:30] + node _T_1116 = or(_T_1115, reset) @[RocketTiles.scala 50:21] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1118 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1119 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1121 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1122 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1124 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1126 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1127 = or(_T_1126, reset) @[RocketTiles.scala 50:21] + node _T_1129 = eq(_T_1127, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1129 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1130 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 50:21] + node _T_1131 = or(_T_1130, reset) @[RocketTiles.scala 50:21] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1133 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1135 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1135 : @[RocketTiles.scala 50:21] + node _T_1138 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1140 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1141 = and(_T_1138, _T_1140) @[Parameters.scala 63:37] + node _T_1142 = or(UInt<1>("h00"), _T_1141) @[Parameters.scala 132:31] + node _T_1144 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1145 = cvt(_T_1144) @[Parameters.scala 117:49] + node _T_1147 = and(_T_1145, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1148 = asSInt(_T_1147) @[Parameters.scala 117:52] + node _T_1150 = eq(_T_1148, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1152 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1153 = cvt(_T_1152) @[Parameters.scala 117:49] + node _T_1155 = and(_T_1153, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1156 = asSInt(_T_1155) @[Parameters.scala 117:52] + node _T_1158 = eq(_T_1156, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1160 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1161 = cvt(_T_1160) @[Parameters.scala 117:49] + node _T_1163 = and(_T_1161, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1164 = asSInt(_T_1163) @[Parameters.scala 117:52] + node _T_1166 = eq(_T_1164, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1168 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1169 = cvt(_T_1168) @[Parameters.scala 117:49] + node _T_1171 = and(_T_1169, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1172 = asSInt(_T_1171) @[Parameters.scala 117:52] + node _T_1174 = eq(_T_1172, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1176 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1177 = cvt(_T_1176) @[Parameters.scala 117:49] + node _T_1179 = and(_T_1177, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1180 = asSInt(_T_1179) @[Parameters.scala 117:52] + node _T_1182 = eq(_T_1180, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1183 = or(_T_1150, _T_1158) @[Parameters.scala 133:42] + node _T_1184 = or(_T_1183, _T_1166) @[Parameters.scala 133:42] + node _T_1185 = or(_T_1184, _T_1174) @[Parameters.scala 133:42] + node _T_1186 = or(_T_1185, _T_1182) @[Parameters.scala 133:42] + node _T_1187 = and(_T_1142, _T_1186) @[Parameters.scala 132:56] + node _T_1190 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1192 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1193 = and(_T_1190, _T_1192) @[Parameters.scala 63:37] + node _T_1194 = or(UInt<1>("h00"), _T_1193) @[Parameters.scala 132:31] + node _T_1196 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1197 = cvt(_T_1196) @[Parameters.scala 117:49] + node _T_1199 = and(_T_1197, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1200 = asSInt(_T_1199) @[Parameters.scala 117:52] + node _T_1202 = eq(_T_1200, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1203 = and(_T_1194, _T_1202) @[Parameters.scala 132:56] + node _T_1206 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1208 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1209 = cvt(_T_1208) @[Parameters.scala 117:49] + node _T_1211 = and(_T_1209, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1212 = asSInt(_T_1211) @[Parameters.scala 117:52] + node _T_1214 = eq(_T_1212, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1215 = and(_T_1206, _T_1214) @[Parameters.scala 132:56] + node _T_1217 = or(UInt<1>("h00"), _T_1187) @[Parameters.scala 134:30] + node _T_1218 = or(_T_1217, _T_1203) @[Parameters.scala 134:30] + node _T_1219 = or(_T_1218, _T_1215) @[Parameters.scala 134:30] + node _T_1220 = or(_T_1219, reset) @[RocketTiles.scala 50:21] + node _T_1222 = eq(_T_1220, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1222 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1223 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1225 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1226 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1228 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1230 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1231 = or(_T_1230, reset) @[RocketTiles.scala 50:21] + node _T_1233 = eq(_T_1231, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1233 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1234 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 50:21] + node _T_1235 = or(_T_1234, reset) @[RocketTiles.scala 50:21] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1237 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1239 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_1239 : @[RocketTiles.scala 50:21] + node _T_1242 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1244 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1245 = and(_T_1242, _T_1244) @[Parameters.scala 63:37] + node _T_1246 = or(UInt<1>("h00"), _T_1245) @[Parameters.scala 132:31] + node _T_1248 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1249 = cvt(_T_1248) @[Parameters.scala 117:49] + node _T_1251 = and(_T_1249, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1252 = asSInt(_T_1251) @[Parameters.scala 117:52] + node _T_1254 = eq(_T_1252, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1256 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1257 = cvt(_T_1256) @[Parameters.scala 117:49] + node _T_1259 = and(_T_1257, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1260 = asSInt(_T_1259) @[Parameters.scala 117:52] + node _T_1262 = eq(_T_1260, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1264 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1265 = cvt(_T_1264) @[Parameters.scala 117:49] + node _T_1267 = and(_T_1265, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1268 = asSInt(_T_1267) @[Parameters.scala 117:52] + node _T_1270 = eq(_T_1268, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1272 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1273 = cvt(_T_1272) @[Parameters.scala 117:49] + node _T_1275 = and(_T_1273, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1276 = asSInt(_T_1275) @[Parameters.scala 117:52] + node _T_1278 = eq(_T_1276, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1280 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1281 = cvt(_T_1280) @[Parameters.scala 117:49] + node _T_1283 = and(_T_1281, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1284 = asSInt(_T_1283) @[Parameters.scala 117:52] + node _T_1286 = eq(_T_1284, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1287 = or(_T_1254, _T_1262) @[Parameters.scala 133:42] + node _T_1288 = or(_T_1287, _T_1270) @[Parameters.scala 133:42] + node _T_1289 = or(_T_1288, _T_1278) @[Parameters.scala 133:42] + node _T_1290 = or(_T_1289, _T_1286) @[Parameters.scala 133:42] + node _T_1291 = and(_T_1246, _T_1290) @[Parameters.scala 132:56] + node _T_1294 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1296 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1297 = and(_T_1294, _T_1296) @[Parameters.scala 63:37] + node _T_1298 = or(UInt<1>("h00"), _T_1297) @[Parameters.scala 132:31] + node _T_1300 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1301 = cvt(_T_1300) @[Parameters.scala 117:49] + node _T_1303 = and(_T_1301, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1304 = asSInt(_T_1303) @[Parameters.scala 117:52] + node _T_1306 = eq(_T_1304, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1307 = and(_T_1298, _T_1306) @[Parameters.scala 132:56] + node _T_1310 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1312 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1313 = cvt(_T_1312) @[Parameters.scala 117:49] + node _T_1315 = and(_T_1313, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1316 = asSInt(_T_1315) @[Parameters.scala 117:52] + node _T_1318 = eq(_T_1316, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1319 = and(_T_1310, _T_1318) @[Parameters.scala 132:56] + node _T_1321 = or(UInt<1>("h00"), _T_1291) @[Parameters.scala 134:30] + node _T_1322 = or(_T_1321, _T_1307) @[Parameters.scala 134:30] + node _T_1323 = or(_T_1322, _T_1319) @[Parameters.scala 134:30] + node _T_1324 = or(_T_1323, reset) @[RocketTiles.scala 50:21] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1326 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1327 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1329 = eq(_T_1327, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1329 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1330 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1332 = eq(_T_1330, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1332 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1334 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1335 = or(_T_1334, reset) @[RocketTiles.scala 50:21] + node _T_1337 = eq(_T_1335, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1337 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1338 = not(_T_948) @[RocketTiles.scala 50:21] + node _T_1339 = and(io.in[0].a.bits.mask, _T_1338) @[RocketTiles.scala 50:21] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1342 = or(_T_1341, reset) @[RocketTiles.scala 50:21] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1344 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1346 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_1346 : @[RocketTiles.scala 50:21] + node _T_1349 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1351 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1352 = and(_T_1349, _T_1351) @[Parameters.scala 63:37] + node _T_1353 = or(UInt<1>("h00"), _T_1352) @[Parameters.scala 132:31] + node _T_1355 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1356 = cvt(_T_1355) @[Parameters.scala 117:49] + node _T_1358 = and(_T_1356, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1359 = asSInt(_T_1358) @[Parameters.scala 117:52] + node _T_1361 = eq(_T_1359, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1363 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1364 = cvt(_T_1363) @[Parameters.scala 117:49] + node _T_1366 = and(_T_1364, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1367 = asSInt(_T_1366) @[Parameters.scala 117:52] + node _T_1369 = eq(_T_1367, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1371 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1372 = cvt(_T_1371) @[Parameters.scala 117:49] + node _T_1374 = and(_T_1372, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1375 = asSInt(_T_1374) @[Parameters.scala 117:52] + node _T_1377 = eq(_T_1375, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1378 = or(_T_1361, _T_1369) @[Parameters.scala 133:42] + node _T_1379 = or(_T_1378, _T_1377) @[Parameters.scala 133:42] + node _T_1380 = and(_T_1353, _T_1379) @[Parameters.scala 132:56] + node _T_1383 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1385 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1386 = cvt(_T_1385) @[Parameters.scala 117:49] + node _T_1388 = and(_T_1386, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1389 = asSInt(_T_1388) @[Parameters.scala 117:52] + node _T_1391 = eq(_T_1389, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1393 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1401 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1402 = cvt(_T_1401) @[Parameters.scala 117:49] + node _T_1404 = and(_T_1402, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1405 = asSInt(_T_1404) @[Parameters.scala 117:52] + node _T_1407 = eq(_T_1405, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1409 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1410 = cvt(_T_1409) @[Parameters.scala 117:49] + node _T_1412 = and(_T_1410, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1413 = asSInt(_T_1412) @[Parameters.scala 117:52] + node _T_1415 = eq(_T_1413, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1416 = or(_T_1391, _T_1399) @[Parameters.scala 133:42] + node _T_1417 = or(_T_1416, _T_1407) @[Parameters.scala 133:42] + node _T_1418 = or(_T_1417, _T_1415) @[Parameters.scala 133:42] + node _T_1419 = and(_T_1383, _T_1418) @[Parameters.scala 132:56] + node _T_1421 = or(UInt<1>("h00"), _T_1380) @[Parameters.scala 134:30] + node _T_1422 = or(_T_1421, _T_1419) @[Parameters.scala 134:30] + node _T_1423 = or(_T_1422, reset) @[RocketTiles.scala 50:21] + node _T_1425 = eq(_T_1423, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1425 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1426 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1428 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1429 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1431 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1433 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1434 = or(_T_1433, reset) @[RocketTiles.scala 50:21] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1436 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1437 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 50:21] + node _T_1438 = or(_T_1437, reset) @[RocketTiles.scala 50:21] + node _T_1440 = eq(_T_1438, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1440 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1442 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 50:21] + when _T_1442 : @[RocketTiles.scala 50:21] + node _T_1445 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1447 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1448 = and(_T_1445, _T_1447) @[Parameters.scala 63:37] + node _T_1449 = or(UInt<1>("h00"), _T_1448) @[Parameters.scala 132:31] + node _T_1451 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1452 = cvt(_T_1451) @[Parameters.scala 117:49] + node _T_1454 = and(_T_1452, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1455 = asSInt(_T_1454) @[Parameters.scala 117:52] + node _T_1457 = eq(_T_1455, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1459 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1460 = cvt(_T_1459) @[Parameters.scala 117:49] + node _T_1462 = and(_T_1460, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1463 = asSInt(_T_1462) @[Parameters.scala 117:52] + node _T_1465 = eq(_T_1463, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1467 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1468 = cvt(_T_1467) @[Parameters.scala 117:49] + node _T_1470 = and(_T_1468, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1471 = asSInt(_T_1470) @[Parameters.scala 117:52] + node _T_1473 = eq(_T_1471, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1474 = or(_T_1457, _T_1465) @[Parameters.scala 133:42] + node _T_1475 = or(_T_1474, _T_1473) @[Parameters.scala 133:42] + node _T_1476 = and(_T_1449, _T_1475) @[Parameters.scala 132:56] + node _T_1479 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1481 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1482 = cvt(_T_1481) @[Parameters.scala 117:49] + node _T_1484 = and(_T_1482, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1485 = asSInt(_T_1484) @[Parameters.scala 117:52] + node _T_1487 = eq(_T_1485, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1489 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1490 = cvt(_T_1489) @[Parameters.scala 117:49] + node _T_1492 = and(_T_1490, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1493 = asSInt(_T_1492) @[Parameters.scala 117:52] + node _T_1495 = eq(_T_1493, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1497 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1498 = cvt(_T_1497) @[Parameters.scala 117:49] + node _T_1500 = and(_T_1498, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1501 = asSInt(_T_1500) @[Parameters.scala 117:52] + node _T_1503 = eq(_T_1501, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1505 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1506 = cvt(_T_1505) @[Parameters.scala 117:49] + node _T_1508 = and(_T_1506, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1509 = asSInt(_T_1508) @[Parameters.scala 117:52] + node _T_1511 = eq(_T_1509, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1512 = or(_T_1487, _T_1495) @[Parameters.scala 133:42] + node _T_1513 = or(_T_1512, _T_1503) @[Parameters.scala 133:42] + node _T_1514 = or(_T_1513, _T_1511) @[Parameters.scala 133:42] + node _T_1515 = and(_T_1479, _T_1514) @[Parameters.scala 132:56] + node _T_1517 = or(UInt<1>("h00"), _T_1476) @[Parameters.scala 134:30] + node _T_1518 = or(_T_1517, _T_1515) @[Parameters.scala 134:30] + node _T_1519 = or(_T_1518, reset) @[RocketTiles.scala 50:21] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1521 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1522 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1524 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1525 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1527 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1529 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1530 = or(_T_1529, reset) @[RocketTiles.scala 50:21] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1532 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1533 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 50:21] + node _T_1534 = or(_T_1533, reset) @[RocketTiles.scala 50:21] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1536 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1538 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_1538 : @[RocketTiles.scala 50:21] + node _T_1541 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1543 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1544 = cvt(_T_1543) @[Parameters.scala 117:49] + node _T_1546 = and(_T_1544, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1547 = asSInt(_T_1546) @[Parameters.scala 117:52] + node _T_1549 = eq(_T_1547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1551 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1552 = cvt(_T_1551) @[Parameters.scala 117:49] + node _T_1554 = and(_T_1552, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1555 = asSInt(_T_1554) @[Parameters.scala 117:52] + node _T_1557 = eq(_T_1555, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1559 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1560 = cvt(_T_1559) @[Parameters.scala 117:49] + node _T_1562 = and(_T_1560, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1563 = asSInt(_T_1562) @[Parameters.scala 117:52] + node _T_1565 = eq(_T_1563, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1567 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1568 = cvt(_T_1567) @[Parameters.scala 117:49] + node _T_1570 = and(_T_1568, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1571 = asSInt(_T_1570) @[Parameters.scala 117:52] + node _T_1573 = eq(_T_1571, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1575 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1576 = cvt(_T_1575) @[Parameters.scala 117:49] + node _T_1578 = and(_T_1576, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1579 = asSInt(_T_1578) @[Parameters.scala 117:52] + node _T_1581 = eq(_T_1579, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1583 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1584 = cvt(_T_1583) @[Parameters.scala 117:49] + node _T_1586 = and(_T_1584, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1587 = asSInt(_T_1586) @[Parameters.scala 117:52] + node _T_1589 = eq(_T_1587, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1590 = or(_T_1549, _T_1557) @[Parameters.scala 133:42] + node _T_1591 = or(_T_1590, _T_1565) @[Parameters.scala 133:42] + node _T_1592 = or(_T_1591, _T_1573) @[Parameters.scala 133:42] + node _T_1593 = or(_T_1592, _T_1581) @[Parameters.scala 133:42] + node _T_1594 = or(_T_1593, _T_1589) @[Parameters.scala 133:42] + node _T_1595 = and(_T_1541, _T_1594) @[Parameters.scala 132:56] + node _T_1597 = or(UInt<1>("h00"), _T_1595) @[Parameters.scala 134:30] + node _T_1598 = or(_T_1597, reset) @[RocketTiles.scala 50:21] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1600 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1601 = or(_T_869[0], reset) @[RocketTiles.scala 50:21] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1603 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1604 = or(_T_880, reset) @[RocketTiles.scala 50:21] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1606 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1607 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 50:21] + node _T_1608 = or(_T_1607, reset) @[RocketTiles.scala 50:21] + node _T_1610 = eq(_T_1608, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1610 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[0].b.valid : @[RocketTiles.scala 50:21] + node _T_1612 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1613 = or(_T_1612, reset) @[RocketTiles.scala 50:21] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1615 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1617 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1618 = cvt(_T_1617) @[Parameters.scala 117:49] + node _T_1620 = and(_T_1618, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1621 = asSInt(_T_1620) @[Parameters.scala 117:52] + node _T_1623 = eq(_T_1621, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1625 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1626 = cvt(_T_1625) @[Parameters.scala 117:49] + node _T_1628 = and(_T_1626, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1629 = asSInt(_T_1628) @[Parameters.scala 117:52] + node _T_1631 = eq(_T_1629, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1633 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1634 = cvt(_T_1633) @[Parameters.scala 117:49] + node _T_1636 = and(_T_1634, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1637 = asSInt(_T_1636) @[Parameters.scala 117:52] + node _T_1639 = eq(_T_1637, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1641 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1642 = cvt(_T_1641) @[Parameters.scala 117:49] + node _T_1644 = and(_T_1642, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1645 = asSInt(_T_1644) @[Parameters.scala 117:52] + node _T_1647 = eq(_T_1645, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1649 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1650 = cvt(_T_1649) @[Parameters.scala 117:49] + node _T_1652 = and(_T_1650, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1653 = asSInt(_T_1652) @[Parameters.scala 117:52] + node _T_1655 = eq(_T_1653, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1657 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1658 = cvt(_T_1657) @[Parameters.scala 117:49] + node _T_1660 = and(_T_1658, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1661 = asSInt(_T_1660) @[Parameters.scala 117:52] + node _T_1663 = eq(_T_1661, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1665 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1666 = cvt(_T_1665) @[Parameters.scala 117:49] + node _T_1668 = and(_T_1666, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1669 = asSInt(_T_1668) @[Parameters.scala 117:52] + node _T_1671 = eq(_T_1669, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1674 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1674 is invalid @[Parameters.scala 110:36] + _T_1674[0] <= _T_1623 @[Parameters.scala 110:36] + _T_1674[1] <= _T_1631 @[Parameters.scala 110:36] + _T_1674[2] <= _T_1639 @[Parameters.scala 110:36] + _T_1674[3] <= _T_1647 @[Parameters.scala 110:36] + _T_1674[4] <= _T_1655 @[Parameters.scala 110:36] + _T_1674[5] <= _T_1663 @[Parameters.scala 110:36] + _T_1674[6] <= _T_1671 @[Parameters.scala 110:36] + node _T_1684 = or(_T_1674[0], _T_1674[1]) @[Parameters.scala 119:64] + node _T_1685 = or(_T_1684, _T_1674[2]) @[Parameters.scala 119:64] + node _T_1686 = or(_T_1685, _T_1674[3]) @[Parameters.scala 119:64] + node _T_1687 = or(_T_1686, _T_1674[4]) @[Parameters.scala 119:64] + node _T_1688 = or(_T_1687, _T_1674[5]) @[Parameters.scala 119:64] + node _T_1689 = or(_T_1688, _T_1674[6]) @[Parameters.scala 119:64] + node _T_1691 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1692 = dshl(_T_1691, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1693 = bits(_T_1692, 7, 0) @[package.scala 19:76] + node _T_1694 = not(_T_1693) @[package.scala 19:40] + node _T_1695 = and(io.in[0].b.bits.address, _T_1694) @[Edges.scala 17:16] + node _T_1697 = eq(_T_1695, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1699 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1700 = dshl(UInt<1>("h01"), _T_1699) @[OneHot.scala 49:12] + node _T_1701 = bits(_T_1700, 2, 0) @[OneHot.scala 49:37] + node _T_1703 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1705 = bits(_T_1701, 2, 2) @[package.scala 44:26] + node _T_1706 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[package.scala 46:20] + node _T_1709 = and(UInt<1>("h01"), _T_1708) @[package.scala 49:27] + node _T_1710 = and(_T_1705, _T_1709) @[package.scala 50:38] + node _T_1711 = or(_T_1703, _T_1710) @[package.scala 50:29] + node _T_1712 = and(UInt<1>("h01"), _T_1706) @[package.scala 49:27] + node _T_1713 = and(_T_1705, _T_1712) @[package.scala 50:38] + node _T_1714 = or(_T_1703, _T_1713) @[package.scala 50:29] + node _T_1715 = bits(_T_1701, 1, 1) @[package.scala 44:26] + node _T_1716 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1718 = eq(_T_1716, UInt<1>("h00")) @[package.scala 46:20] + node _T_1719 = and(_T_1709, _T_1718) @[package.scala 49:27] + node _T_1720 = and(_T_1715, _T_1719) @[package.scala 50:38] + node _T_1721 = or(_T_1711, _T_1720) @[package.scala 50:29] + node _T_1722 = and(_T_1709, _T_1716) @[package.scala 49:27] + node _T_1723 = and(_T_1715, _T_1722) @[package.scala 50:38] + node _T_1724 = or(_T_1711, _T_1723) @[package.scala 50:29] + node _T_1725 = and(_T_1712, _T_1718) @[package.scala 49:27] + node _T_1726 = and(_T_1715, _T_1725) @[package.scala 50:38] + node _T_1727 = or(_T_1714, _T_1726) @[package.scala 50:29] + node _T_1728 = and(_T_1712, _T_1716) @[package.scala 49:27] + node _T_1729 = and(_T_1715, _T_1728) @[package.scala 50:38] + node _T_1730 = or(_T_1714, _T_1729) @[package.scala 50:29] + node _T_1731 = bits(_T_1701, 0, 0) @[package.scala 44:26] + node _T_1732 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[package.scala 46:20] + node _T_1735 = and(_T_1719, _T_1734) @[package.scala 49:27] + node _T_1736 = and(_T_1731, _T_1735) @[package.scala 50:38] + node _T_1737 = or(_T_1721, _T_1736) @[package.scala 50:29] + node _T_1738 = and(_T_1719, _T_1732) @[package.scala 49:27] + node _T_1739 = and(_T_1731, _T_1738) @[package.scala 50:38] + node _T_1740 = or(_T_1721, _T_1739) @[package.scala 50:29] + node _T_1741 = and(_T_1722, _T_1734) @[package.scala 49:27] + node _T_1742 = and(_T_1731, _T_1741) @[package.scala 50:38] + node _T_1743 = or(_T_1724, _T_1742) @[package.scala 50:29] + node _T_1744 = and(_T_1722, _T_1732) @[package.scala 49:27] + node _T_1745 = and(_T_1731, _T_1744) @[package.scala 50:38] + node _T_1746 = or(_T_1724, _T_1745) @[package.scala 50:29] + node _T_1747 = and(_T_1725, _T_1734) @[package.scala 49:27] + node _T_1748 = and(_T_1731, _T_1747) @[package.scala 50:38] + node _T_1749 = or(_T_1727, _T_1748) @[package.scala 50:29] + node _T_1750 = and(_T_1725, _T_1732) @[package.scala 49:27] + node _T_1751 = and(_T_1731, _T_1750) @[package.scala 50:38] + node _T_1752 = or(_T_1727, _T_1751) @[package.scala 50:29] + node _T_1753 = and(_T_1728, _T_1734) @[package.scala 49:27] + node _T_1754 = and(_T_1731, _T_1753) @[package.scala 50:38] + node _T_1755 = or(_T_1730, _T_1754) @[package.scala 50:29] + node _T_1756 = and(_T_1728, _T_1732) @[package.scala 49:27] + node _T_1757 = and(_T_1731, _T_1756) @[package.scala 50:38] + node _T_1758 = or(_T_1730, _T_1757) @[package.scala 50:29] + node _T_1759 = cat(_T_1740, _T_1737) @[Cat.scala 30:58] + node _T_1760 = cat(_T_1746, _T_1743) @[Cat.scala 30:58] + node _T_1761 = cat(_T_1760, _T_1759) @[Cat.scala 30:58] + node _T_1762 = cat(_T_1752, _T_1749) @[Cat.scala 30:58] + node _T_1763 = cat(_T_1758, _T_1755) @[Cat.scala 30:58] + node _T_1764 = cat(_T_1763, _T_1762) @[Cat.scala 30:58] + node _T_1765 = cat(_T_1764, _T_1761) @[Cat.scala 30:58] + node _T_1767 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_1767 : @[RocketTiles.scala 50:21] + node _T_1769 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1771 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1772 = and(_T_1769, _T_1771) @[Parameters.scala 63:37] + node _T_1773 = or(_T_1772, reset) @[RocketTiles.scala 50:21] + node _T_1775 = eq(_T_1773, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1775 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1776 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1778 = eq(_T_1776, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1778 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1780 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_1781 = or(_T_1780, reset) @[RocketTiles.scala 50:21] + node _T_1783 = eq(_T_1781, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1783 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1784 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1786 = eq(_T_1784, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1786 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1788 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1789 = or(_T_1788, reset) @[RocketTiles.scala 50:21] + node _T_1791 = eq(_T_1789, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1791 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1792 = not(io.in[0].b.bits.mask) @[RocketTiles.scala 50:21] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1795 = or(_T_1794, reset) @[RocketTiles.scala 50:21] + node _T_1797 = eq(_T_1795, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1797 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1799 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_1799 : @[RocketTiles.scala 50:21] + node _T_1801 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1803 = eq(_T_1801, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1803 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1804 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1806 = eq(_T_1804, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1806 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1807 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1809 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1811 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1812 = or(_T_1811, reset) @[RocketTiles.scala 50:21] + node _T_1814 = eq(_T_1812, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1814 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1815 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 50:21] + node _T_1816 = or(_T_1815, reset) @[RocketTiles.scala 50:21] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1818 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1820 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1820 : @[RocketTiles.scala 50:21] + node _T_1822 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1824 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1825 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1827 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1828 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1830 = eq(_T_1828, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1830 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1832 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1833 = or(_T_1832, reset) @[RocketTiles.scala 50:21] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1835 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1836 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 50:21] + node _T_1837 = or(_T_1836, reset) @[RocketTiles.scala 50:21] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1839 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1841 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_1841 : @[RocketTiles.scala 50:21] + node _T_1843 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1845 = eq(_T_1843, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1845 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1846 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1848 = eq(_T_1846, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1848 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1849 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1851 = eq(_T_1849, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1851 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1853 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1854 = or(_T_1853, reset) @[RocketTiles.scala 50:21] + node _T_1856 = eq(_T_1854, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1856 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1857 = not(_T_1765) @[RocketTiles.scala 50:21] + node _T_1858 = and(io.in[0].b.bits.mask, _T_1857) @[RocketTiles.scala 50:21] + node _T_1860 = eq(_T_1858, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_1861 = or(_T_1860, reset) @[RocketTiles.scala 50:21] + node _T_1863 = eq(_T_1861, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1863 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1865 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_1865 : @[RocketTiles.scala 50:21] + node _T_1867 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1869 = eq(_T_1867, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1869 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1870 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1872 = eq(_T_1870, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1872 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1873 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1875 = eq(_T_1873, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1875 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1877 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1878 = or(_T_1877, reset) @[RocketTiles.scala 50:21] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1880 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1881 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 50:21] + node _T_1882 = or(_T_1881, reset) @[RocketTiles.scala 50:21] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1884 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1886 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 50:21] + when _T_1886 : @[RocketTiles.scala 50:21] + node _T_1888 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1890 = eq(_T_1888, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1890 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1891 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1893 = eq(_T_1891, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1893 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1894 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1896 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1898 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1899 = or(_T_1898, reset) @[RocketTiles.scala 50:21] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1901 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1902 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 50:21] + node _T_1903 = or(_T_1902, reset) @[RocketTiles.scala 50:21] + node _T_1905 = eq(_T_1903, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1905 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1907 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_1907 : @[RocketTiles.scala 50:21] + node _T_1909 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_1911 = eq(_T_1909, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1911 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1912 = or(_T_1689, reset) @[RocketTiles.scala 50:21] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1914 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1915 = or(_T_1697, reset) @[RocketTiles.scala 50:21] + node _T_1917 = eq(_T_1915, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1917 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1918 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 50:21] + node _T_1919 = or(_T_1918, reset) @[RocketTiles.scala 50:21] + node _T_1921 = eq(_T_1919, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1921 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[0].c.valid : @[RocketTiles.scala 50:21] + node _T_1923 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1924 = or(_T_1923, reset) @[RocketTiles.scala 50:21] + node _T_1926 = eq(_T_1924, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_1926 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_1928 = eq(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1931 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1931 is invalid @[Parameters.scala 228:27] + _T_1931[0] <= _T_1928 @[Parameters.scala 228:27] + node _T_1936 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1937 = dshl(_T_1936, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1938 = bits(_T_1937, 7, 0) @[package.scala 19:76] + node _T_1939 = not(_T_1938) @[package.scala 19:40] + node _T_1940 = and(io.in[0].c.bits.address, _T_1939) @[Edges.scala 17:16] + node _T_1942 = eq(_T_1940, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1944 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1945 = cvt(_T_1944) @[Parameters.scala 117:49] + node _T_1947 = and(_T_1945, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1948 = asSInt(_T_1947) @[Parameters.scala 117:52] + node _T_1950 = eq(_T_1948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1952 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1953 = cvt(_T_1952) @[Parameters.scala 117:49] + node _T_1955 = and(_T_1953, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1956 = asSInt(_T_1955) @[Parameters.scala 117:52] + node _T_1958 = eq(_T_1956, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1960 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1961 = cvt(_T_1960) @[Parameters.scala 117:49] + node _T_1963 = and(_T_1961, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1964 = asSInt(_T_1963) @[Parameters.scala 117:52] + node _T_1966 = eq(_T_1964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1968 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1969 = cvt(_T_1968) @[Parameters.scala 117:49] + node _T_1971 = and(_T_1969, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1972 = asSInt(_T_1971) @[Parameters.scala 117:52] + node _T_1974 = eq(_T_1972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1977 = cvt(_T_1976) @[Parameters.scala 117:49] + node _T_1979 = and(_T_1977, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1980 = asSInt(_T_1979) @[Parameters.scala 117:52] + node _T_1982 = eq(_T_1980, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1984 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1985 = cvt(_T_1984) @[Parameters.scala 117:49] + node _T_1987 = and(_T_1985, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1988 = asSInt(_T_1987) @[Parameters.scala 117:52] + node _T_1990 = eq(_T_1988, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1992 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1993 = cvt(_T_1992) @[Parameters.scala 117:49] + node _T_1995 = and(_T_1993, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1996 = asSInt(_T_1995) @[Parameters.scala 117:52] + node _T_1998 = eq(_T_1996, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_2001 : UInt<1>[7] @[Parameters.scala 110:36] + _T_2001 is invalid @[Parameters.scala 110:36] + _T_2001[0] <= _T_1950 @[Parameters.scala 110:36] + _T_2001[1] <= _T_1958 @[Parameters.scala 110:36] + _T_2001[2] <= _T_1966 @[Parameters.scala 110:36] + _T_2001[3] <= _T_1974 @[Parameters.scala 110:36] + _T_2001[4] <= _T_1982 @[Parameters.scala 110:36] + _T_2001[5] <= _T_1990 @[Parameters.scala 110:36] + _T_2001[6] <= _T_1998 @[Parameters.scala 110:36] + node _T_2011 = or(_T_2001[0], _T_2001[1]) @[Parameters.scala 119:64] + node _T_2012 = or(_T_2011, _T_2001[2]) @[Parameters.scala 119:64] + node _T_2013 = or(_T_2012, _T_2001[3]) @[Parameters.scala 119:64] + node _T_2014 = or(_T_2013, _T_2001[4]) @[Parameters.scala 119:64] + node _T_2015 = or(_T_2014, _T_2001[5]) @[Parameters.scala 119:64] + node _T_2016 = or(_T_2015, _T_2001[6]) @[Parameters.scala 119:64] + node _T_2018 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_2018 : @[RocketTiles.scala 50:21] + node _T_2019 = or(_T_2016, reset) @[RocketTiles.scala 50:21] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2021 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2022 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2024 = eq(_T_2022, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2024 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2026 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2027 = or(_T_2026, reset) @[RocketTiles.scala 50:21] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2029 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2030 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2032 = eq(_T_2030, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2032 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2034 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2035 = or(_T_2034, reset) @[RocketTiles.scala 50:21] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2037 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2039 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2040 = or(_T_2039, reset) @[RocketTiles.scala 50:21] + node _T_2042 = eq(_T_2040, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2042 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2044 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_2044 : @[RocketTiles.scala 50:21] + node _T_2045 = or(_T_2016, reset) @[RocketTiles.scala 50:21] + node _T_2047 = eq(_T_2045, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2047 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2048 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2050 = eq(_T_2048, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2050 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2052 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2053 = or(_T_2052, reset) @[RocketTiles.scala 50:21] + node _T_2055 = eq(_T_2053, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2055 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2056 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2058 = eq(_T_2056, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2058 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2060 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2061 = or(_T_2060, reset) @[RocketTiles.scala 50:21] + node _T_2063 = eq(_T_2061, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2063 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2065 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2066 = or(_T_2065, reset) @[RocketTiles.scala 50:21] + node _T_2068 = eq(_T_2066, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2068 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2070 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_2070 : @[RocketTiles.scala 50:21] + node _T_2073 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2075 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2076 = and(_T_2073, _T_2075) @[Parameters.scala 63:37] + node _T_2077 = or(UInt<1>("h00"), _T_2076) @[Parameters.scala 132:31] + node _T_2079 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2080 = cvt(_T_2079) @[Parameters.scala 117:49] + node _T_2082 = and(_T_2080, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2083 = asSInt(_T_2082) @[Parameters.scala 117:52] + node _T_2085 = eq(_T_2083, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2087 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2088 = cvt(_T_2087) @[Parameters.scala 117:49] + node _T_2090 = and(_T_2088, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2091 = asSInt(_T_2090) @[Parameters.scala 117:52] + node _T_2093 = eq(_T_2091, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2094 = or(_T_2085, _T_2093) @[Parameters.scala 133:42] + node _T_2095 = and(_T_2077, _T_2094) @[Parameters.scala 132:56] + node _T_2098 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2100 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2101 = cvt(_T_2100) @[Parameters.scala 117:49] + node _T_2103 = and(_T_2101, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2104 = asSInt(_T_2103) @[Parameters.scala 117:52] + node _T_2106 = eq(_T_2104, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2108 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2109 = cvt(_T_2108) @[Parameters.scala 117:49] + node _T_2111 = and(_T_2109, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2112 = asSInt(_T_2111) @[Parameters.scala 117:52] + node _T_2114 = eq(_T_2112, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2116 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2117 = cvt(_T_2116) @[Parameters.scala 117:49] + node _T_2119 = and(_T_2117, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2120 = asSInt(_T_2119) @[Parameters.scala 117:52] + node _T_2122 = eq(_T_2120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2124 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2125 = cvt(_T_2124) @[Parameters.scala 117:49] + node _T_2127 = and(_T_2125, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2128 = asSInt(_T_2127) @[Parameters.scala 117:52] + node _T_2130 = eq(_T_2128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2131 = or(_T_2106, _T_2114) @[Parameters.scala 133:42] + node _T_2132 = or(_T_2131, _T_2122) @[Parameters.scala 133:42] + node _T_2133 = or(_T_2132, _T_2130) @[Parameters.scala 133:42] + node _T_2134 = and(_T_2098, _T_2133) @[Parameters.scala 132:56] + node _T_2136 = or(UInt<1>("h00"), _T_2095) @[Parameters.scala 134:30] + node _T_2137 = or(_T_2136, _T_2134) @[Parameters.scala 134:30] + node _T_2138 = or(_T_2137, reset) @[RocketTiles.scala 50:21] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2140 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2141 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2143 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2145 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2146 = or(_T_2145, reset) @[RocketTiles.scala 50:21] + node _T_2148 = eq(_T_2146, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2148 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2149 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2151 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2153 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2154 = or(_T_2153, reset) @[RocketTiles.scala 50:21] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2156 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2158 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2159 = or(_T_2158, reset) @[RocketTiles.scala 50:21] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2161 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2163 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RocketTiles.scala 50:21] + when _T_2163 : @[RocketTiles.scala 50:21] + node _T_2166 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2168 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2169 = and(_T_2166, _T_2168) @[Parameters.scala 63:37] + node _T_2170 = or(UInt<1>("h00"), _T_2169) @[Parameters.scala 132:31] + node _T_2172 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2173 = cvt(_T_2172) @[Parameters.scala 117:49] + node _T_2175 = and(_T_2173, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2176 = asSInt(_T_2175) @[Parameters.scala 117:52] + node _T_2178 = eq(_T_2176, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2180 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2181 = cvt(_T_2180) @[Parameters.scala 117:49] + node _T_2183 = and(_T_2181, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2184 = asSInt(_T_2183) @[Parameters.scala 117:52] + node _T_2186 = eq(_T_2184, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2187 = or(_T_2178, _T_2186) @[Parameters.scala 133:42] + node _T_2188 = and(_T_2170, _T_2187) @[Parameters.scala 132:56] + node _T_2191 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2193 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2194 = cvt(_T_2193) @[Parameters.scala 117:49] + node _T_2196 = and(_T_2194, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2197 = asSInt(_T_2196) @[Parameters.scala 117:52] + node _T_2199 = eq(_T_2197, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2201 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2202 = cvt(_T_2201) @[Parameters.scala 117:49] + node _T_2204 = and(_T_2202, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2205 = asSInt(_T_2204) @[Parameters.scala 117:52] + node _T_2207 = eq(_T_2205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2209 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2210 = cvt(_T_2209) @[Parameters.scala 117:49] + node _T_2212 = and(_T_2210, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2213 = asSInt(_T_2212) @[Parameters.scala 117:52] + node _T_2215 = eq(_T_2213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2217 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2218 = cvt(_T_2217) @[Parameters.scala 117:49] + node _T_2220 = and(_T_2218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2221 = asSInt(_T_2220) @[Parameters.scala 117:52] + node _T_2223 = eq(_T_2221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2224 = or(_T_2199, _T_2207) @[Parameters.scala 133:42] + node _T_2225 = or(_T_2224, _T_2215) @[Parameters.scala 133:42] + node _T_2226 = or(_T_2225, _T_2223) @[Parameters.scala 133:42] + node _T_2227 = and(_T_2191, _T_2226) @[Parameters.scala 132:56] + node _T_2229 = or(UInt<1>("h00"), _T_2188) @[Parameters.scala 134:30] + node _T_2230 = or(_T_2229, _T_2227) @[Parameters.scala 134:30] + node _T_2231 = or(_T_2230, reset) @[RocketTiles.scala 50:21] + node _T_2233 = eq(_T_2231, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2233 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2234 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2236 = eq(_T_2234, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2236 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2238 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2239 = or(_T_2238, reset) @[RocketTiles.scala 50:21] + node _T_2241 = eq(_T_2239, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2241 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2242 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2244 = eq(_T_2242, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2244 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2246 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2247 = or(_T_2246, reset) @[RocketTiles.scala 50:21] + node _T_2249 = eq(_T_2247, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2249 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2251 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2252 = or(_T_2251, reset) @[RocketTiles.scala 50:21] + node _T_2254 = eq(_T_2252, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2254 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2256 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2256 : @[RocketTiles.scala 50:21] + node _T_2257 = or(_T_2016, reset) @[RocketTiles.scala 50:21] + node _T_2259 = eq(_T_2257, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2259 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2260 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2262 = eq(_T_2260, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2262 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2263 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2265 = eq(_T_2263, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2265 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2267 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2268 = or(_T_2267, reset) @[RocketTiles.scala 50:21] + node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2270 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2272 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_2272 : @[RocketTiles.scala 50:21] + node _T_2273 = or(_T_2016, reset) @[RocketTiles.scala 50:21] + node _T_2275 = eq(_T_2273, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2275 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2276 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2278 = eq(_T_2276, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2278 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2279 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2281 = eq(_T_2279, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2281 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2283 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2284 = or(_T_2283, reset) @[RocketTiles.scala 50:21] + node _T_2286 = eq(_T_2284, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2286 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2288 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_2288 : @[RocketTiles.scala 50:21] + node _T_2289 = or(_T_2016, reset) @[RocketTiles.scala 50:21] + node _T_2291 = eq(_T_2289, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2291 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2292 = or(_T_1931[0], reset) @[RocketTiles.scala 50:21] + node _T_2294 = eq(_T_2292, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2294 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2295 = or(_T_1942, reset) @[RocketTiles.scala 50:21] + node _T_2297 = eq(_T_2295, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2297 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2299 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2300 = or(_T_2299, reset) @[RocketTiles.scala 50:21] + node _T_2302 = eq(_T_2300, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2302 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2304 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2305 = or(_T_2304, reset) @[RocketTiles.scala 50:21] + node _T_2307 = eq(_T_2305, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2307 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[0].d.valid : @[RocketTiles.scala 50:21] + node _T_2309 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2310 = or(_T_2309, reset) @[RocketTiles.scala 50:21] + node _T_2312 = eq(_T_2310, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2312 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2314 = eq(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_2317 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2317 is invalid @[Parameters.scala 228:27] + _T_2317[0] <= _T_2314 @[Parameters.scala 228:27] + node _T_2322 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2323 = dshl(_T_2322, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2324 = bits(_T_2323, 7, 0) @[package.scala 19:76] + node _T_2325 = not(_T_2324) @[package.scala 19:40] + node _T_2326 = and(io.in[0].d.bits.addr_lo, _T_2325) @[Edges.scala 17:16] + node _T_2328 = eq(_T_2326, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2330 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 50:21] + node _T_2332 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_2332 : @[RocketTiles.scala 50:21] + node _T_2333 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2335 = eq(_T_2333, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2335 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2336 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2338 = eq(_T_2336, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2338 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2339 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2341 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2343 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2344 = or(_T_2343, reset) @[RocketTiles.scala 50:21] + node _T_2346 = eq(_T_2344, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2346 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2348 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2349 = or(_T_2348, reset) @[RocketTiles.scala 50:21] + node _T_2351 = eq(_T_2349, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2351 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2353 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2354 = or(_T_2353, reset) @[RocketTiles.scala 50:21] + node _T_2356 = eq(_T_2354, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2356 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2358 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_2358 : @[RocketTiles.scala 50:21] + node _T_2359 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2361 = eq(_T_2359, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2361 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2362 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2364 = eq(_T_2362, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2364 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2365 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2367 = eq(_T_2365, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2367 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2369 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2370 = or(_T_2369, reset) @[RocketTiles.scala 50:21] + node _T_2372 = eq(_T_2370, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2372 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2374 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2375 = or(_T_2374, reset) @[RocketTiles.scala 50:21] + node _T_2377 = eq(_T_2375, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2377 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2379 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_2379 : @[RocketTiles.scala 50:21] + node _T_2380 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2382 = eq(_T_2380, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2382 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2383 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2385 = eq(_T_2383, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2385 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2386 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2388 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2390 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2391 = or(_T_2390, reset) @[RocketTiles.scala 50:21] + node _T_2393 = eq(_T_2391, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2393 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2395 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2396 = or(_T_2395, reset) @[RocketTiles.scala 50:21] + node _T_2398 = eq(_T_2396, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2398 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2400 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2400 : @[RocketTiles.scala 50:21] + node _T_2401 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2403 = eq(_T_2401, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2403 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2404 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2406 = eq(_T_2404, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2406 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2407 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2409 = eq(_T_2407, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2409 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2411 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2412 = or(_T_2411, reset) @[RocketTiles.scala 50:21] + node _T_2414 = eq(_T_2412, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2414 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2416 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_2416 : @[RocketTiles.scala 50:21] + node _T_2417 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2419 = eq(_T_2417, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2419 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2420 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2422 = eq(_T_2420, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2422 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2423 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2425 = eq(_T_2423, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2425 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2427 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2428 = or(_T_2427, reset) @[RocketTiles.scala 50:21] + node _T_2430 = eq(_T_2428, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2430 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2432 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_2432 : @[RocketTiles.scala 50:21] + node _T_2433 = or(_T_2317[0], reset) @[RocketTiles.scala 50:21] + node _T_2435 = eq(_T_2433, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2435 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2436 = or(_T_2328, reset) @[RocketTiles.scala 50:21] + node _T_2438 = eq(_T_2436, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2438 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2439 = or(_T_2330, reset) @[RocketTiles.scala 50:21] + node _T_2441 = eq(_T_2439, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2441 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2443 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2444 = or(_T_2443, reset) @[RocketTiles.scala 50:21] + node _T_2446 = eq(_T_2444, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2446 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2448 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2449 = or(_T_2448, reset) @[RocketTiles.scala 50:21] + node _T_2451 = eq(_T_2449, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2451 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[0].e.valid : @[RocketTiles.scala 50:21] + node _T_2453 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 50:21] + node _T_2454 = or(_T_2453, reset) @[RocketTiles.scala 50:21] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2456 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2457 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2459 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2460 = dshl(_T_2459, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2461 = bits(_T_2460, 7, 0) @[package.scala 19:76] + node _T_2462 = not(_T_2461) @[package.scala 19:40] + node _T_2463 = shr(_T_2462, 3) @[Edges.scala 198:59] + node _T_2464 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2466 = eq(_T_2464, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2468 = mux(_T_2466, _T_2463, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2470 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2472 = sub(_T_2470, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2473 = asUInt(_T_2472) @[Edges.scala 208:28] + node _T_2474 = tail(_T_2473, 1) @[Edges.scala 208:28] + node _T_2476 = eq(_T_2470, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2478 = eq(_T_2470, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2480 = eq(_T_2468, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2481 = or(_T_2478, _T_2480) @[Edges.scala 210:37] + node _T_2482 = and(_T_2481, _T_2457) @[Edges.scala 211:22] + node _T_2483 = not(_T_2474) @[Edges.scala 212:27] + node _T_2484 = and(_T_2468, _T_2483) @[Edges.scala 212:25] + when _T_2457 : @[Edges.scala 213:17] + node _T_2485 = mux(_T_2476, _T_2468, _T_2474) @[Edges.scala 214:21] + _T_2470 <= _T_2485 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2487 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2489 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2491 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2493 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2495 : UInt, clock @[RocketTiles.scala 50:21] + node _T_2497 = eq(_T_2476, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2498 = and(io.in[0].a.valid, _T_2497) @[RocketTiles.scala 50:21] + when _T_2498 : @[RocketTiles.scala 50:21] + node _T_2499 = eq(io.in[0].a.bits.opcode, _T_2487) @[RocketTiles.scala 50:21] + node _T_2500 = or(_T_2499, reset) @[RocketTiles.scala 50:21] + node _T_2502 = eq(_T_2500, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2502 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2503 = eq(io.in[0].a.bits.param, _T_2489) @[RocketTiles.scala 50:21] + node _T_2504 = or(_T_2503, reset) @[RocketTiles.scala 50:21] + node _T_2506 = eq(_T_2504, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2506 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2507 = eq(io.in[0].a.bits.size, _T_2491) @[RocketTiles.scala 50:21] + node _T_2508 = or(_T_2507, reset) @[RocketTiles.scala 50:21] + node _T_2510 = eq(_T_2508, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2510 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2511 = eq(io.in[0].a.bits.source, _T_2493) @[RocketTiles.scala 50:21] + node _T_2512 = or(_T_2511, reset) @[RocketTiles.scala 50:21] + node _T_2514 = eq(_T_2512, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2514 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2515 = eq(io.in[0].a.bits.address, _T_2495) @[RocketTiles.scala 50:21] + node _T_2516 = or(_T_2515, reset) @[RocketTiles.scala 50:21] + node _T_2518 = eq(_T_2516, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2518 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2519 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2520 = and(_T_2519, _T_2476) @[RocketTiles.scala 50:21] + when _T_2520 : @[RocketTiles.scala 50:21] + _T_2487 <= io.in[0].a.bits.opcode @[RocketTiles.scala 50:21] + _T_2489 <= io.in[0].a.bits.param @[RocketTiles.scala 50:21] + _T_2491 <= io.in[0].a.bits.size @[RocketTiles.scala 50:21] + _T_2493 <= io.in[0].a.bits.source @[RocketTiles.scala 50:21] + _T_2495 <= io.in[0].a.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2521 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2523 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2524 = dshl(_T_2523, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2525 = bits(_T_2524, 7, 0) @[package.scala 19:76] + node _T_2526 = not(_T_2525) @[package.scala 19:40] + node _T_2527 = shr(_T_2526, 3) @[Edges.scala 198:59] + node _T_2528 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2530 = eq(_T_2528, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2533 = mux(UInt<1>("h00"), _T_2527, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2535 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2537 = sub(_T_2535, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2538 = asUInt(_T_2537) @[Edges.scala 208:28] + node _T_2539 = tail(_T_2538, 1) @[Edges.scala 208:28] + node _T_2541 = eq(_T_2535, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2543 = eq(_T_2535, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2545 = eq(_T_2533, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2546 = or(_T_2543, _T_2545) @[Edges.scala 210:37] + node _T_2547 = and(_T_2546, _T_2521) @[Edges.scala 211:22] + node _T_2548 = not(_T_2539) @[Edges.scala 212:27] + node _T_2549 = and(_T_2533, _T_2548) @[Edges.scala 212:25] + when _T_2521 : @[Edges.scala 213:17] + node _T_2550 = mux(_T_2541, _T_2533, _T_2539) @[Edges.scala 214:21] + _T_2535 <= _T_2550 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2552 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2554 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2556 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2558 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2560 : UInt, clock @[RocketTiles.scala 50:21] + node _T_2562 = eq(_T_2541, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2563 = and(io.in[0].b.valid, _T_2562) @[RocketTiles.scala 50:21] + when _T_2563 : @[RocketTiles.scala 50:21] + node _T_2564 = eq(io.in[0].b.bits.opcode, _T_2552) @[RocketTiles.scala 50:21] + node _T_2565 = or(_T_2564, reset) @[RocketTiles.scala 50:21] + node _T_2567 = eq(_T_2565, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2567 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2568 = eq(io.in[0].b.bits.param, _T_2554) @[RocketTiles.scala 50:21] + node _T_2569 = or(_T_2568, reset) @[RocketTiles.scala 50:21] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2571 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2572 = eq(io.in[0].b.bits.size, _T_2556) @[RocketTiles.scala 50:21] + node _T_2573 = or(_T_2572, reset) @[RocketTiles.scala 50:21] + node _T_2575 = eq(_T_2573, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2575 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2576 = eq(io.in[0].b.bits.source, _T_2558) @[RocketTiles.scala 50:21] + node _T_2577 = or(_T_2576, reset) @[RocketTiles.scala 50:21] + node _T_2579 = eq(_T_2577, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2579 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2580 = eq(io.in[0].b.bits.address, _T_2560) @[RocketTiles.scala 50:21] + node _T_2581 = or(_T_2580, reset) @[RocketTiles.scala 50:21] + node _T_2583 = eq(_T_2581, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2583 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2584 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2585 = and(_T_2584, _T_2541) @[RocketTiles.scala 50:21] + when _T_2585 : @[RocketTiles.scala 50:21] + _T_2552 <= io.in[0].b.bits.opcode @[RocketTiles.scala 50:21] + _T_2554 <= io.in[0].b.bits.param @[RocketTiles.scala 50:21] + _T_2556 <= io.in[0].b.bits.size @[RocketTiles.scala 50:21] + _T_2558 <= io.in[0].b.bits.source @[RocketTiles.scala 50:21] + _T_2560 <= io.in[0].b.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2586 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2588 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2589 = dshl(_T_2588, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2590 = bits(_T_2589, 7, 0) @[package.scala 19:76] + node _T_2591 = not(_T_2590) @[package.scala 19:40] + node _T_2592 = shr(_T_2591, 3) @[Edges.scala 198:59] + node _T_2593 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2595 = mux(_T_2593, _T_2592, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2597 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2599 = sub(_T_2597, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2600 = asUInt(_T_2599) @[Edges.scala 208:28] + node _T_2601 = tail(_T_2600, 1) @[Edges.scala 208:28] + node _T_2603 = eq(_T_2597, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2605 = eq(_T_2597, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2607 = eq(_T_2595, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2608 = or(_T_2605, _T_2607) @[Edges.scala 210:37] + node _T_2609 = and(_T_2608, _T_2586) @[Edges.scala 211:22] + node _T_2610 = not(_T_2601) @[Edges.scala 212:27] + node _T_2611 = and(_T_2595, _T_2610) @[Edges.scala 212:25] + when _T_2586 : @[Edges.scala 213:17] + node _T_2612 = mux(_T_2603, _T_2595, _T_2601) @[Edges.scala 214:21] + _T_2597 <= _T_2612 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2614 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2616 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2618 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2620 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2622 : UInt, clock @[RocketTiles.scala 50:21] + node _T_2624 = eq(_T_2603, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2625 = and(io.in[0].c.valid, _T_2624) @[RocketTiles.scala 50:21] + when _T_2625 : @[RocketTiles.scala 50:21] + node _T_2626 = eq(io.in[0].c.bits.opcode, _T_2614) @[RocketTiles.scala 50:21] + node _T_2627 = or(_T_2626, reset) @[RocketTiles.scala 50:21] + node _T_2629 = eq(_T_2627, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2629 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2630 = eq(io.in[0].c.bits.param, _T_2616) @[RocketTiles.scala 50:21] + node _T_2631 = or(_T_2630, reset) @[RocketTiles.scala 50:21] + node _T_2633 = eq(_T_2631, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2633 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2634 = eq(io.in[0].c.bits.size, _T_2618) @[RocketTiles.scala 50:21] + node _T_2635 = or(_T_2634, reset) @[RocketTiles.scala 50:21] + node _T_2637 = eq(_T_2635, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2637 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2638 = eq(io.in[0].c.bits.source, _T_2620) @[RocketTiles.scala 50:21] + node _T_2639 = or(_T_2638, reset) @[RocketTiles.scala 50:21] + node _T_2641 = eq(_T_2639, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2641 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2642 = eq(io.in[0].c.bits.address, _T_2622) @[RocketTiles.scala 50:21] + node _T_2643 = or(_T_2642, reset) @[RocketTiles.scala 50:21] + node _T_2645 = eq(_T_2643, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2645 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2646 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2647 = and(_T_2646, _T_2603) @[RocketTiles.scala 50:21] + when _T_2647 : @[RocketTiles.scala 50:21] + _T_2614 <= io.in[0].c.bits.opcode @[RocketTiles.scala 50:21] + _T_2616 <= io.in[0].c.bits.param @[RocketTiles.scala 50:21] + _T_2618 <= io.in[0].c.bits.size @[RocketTiles.scala 50:21] + _T_2620 <= io.in[0].c.bits.source @[RocketTiles.scala 50:21] + _T_2622 <= io.in[0].c.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2648 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2650 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2651 = dshl(_T_2650, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2652 = bits(_T_2651, 7, 0) @[package.scala 19:76] + node _T_2653 = not(_T_2652) @[package.scala 19:40] + node _T_2654 = shr(_T_2653, 3) @[Edges.scala 198:59] + node _T_2655 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2657 = mux(_T_2655, _T_2654, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2659 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2661 = sub(_T_2659, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2662 = asUInt(_T_2661) @[Edges.scala 208:28] + node _T_2663 = tail(_T_2662, 1) @[Edges.scala 208:28] + node _T_2665 = eq(_T_2659, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2667 = eq(_T_2659, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2669 = eq(_T_2657, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2670 = or(_T_2667, _T_2669) @[Edges.scala 210:37] + node _T_2671 = and(_T_2670, _T_2648) @[Edges.scala 211:22] + node _T_2672 = not(_T_2663) @[Edges.scala 212:27] + node _T_2673 = and(_T_2657, _T_2672) @[Edges.scala 212:25] + when _T_2648 : @[Edges.scala 213:17] + node _T_2674 = mux(_T_2665, _T_2657, _T_2663) @[Edges.scala 214:21] + _T_2659 <= _T_2674 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2676 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2678 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2680 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2682 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2684 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_2686 : UInt, clock @[RocketTiles.scala 50:21] + node _T_2688 = eq(_T_2665, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2689 = and(io.in[0].d.valid, _T_2688) @[RocketTiles.scala 50:21] + when _T_2689 : @[RocketTiles.scala 50:21] + node _T_2690 = eq(io.in[0].d.bits.opcode, _T_2676) @[RocketTiles.scala 50:21] + node _T_2691 = or(_T_2690, reset) @[RocketTiles.scala 50:21] + node _T_2693 = eq(_T_2691, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2693 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2694 = eq(io.in[0].d.bits.param, _T_2678) @[RocketTiles.scala 50:21] + node _T_2695 = or(_T_2694, reset) @[RocketTiles.scala 50:21] + node _T_2697 = eq(_T_2695, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2697 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2698 = eq(io.in[0].d.bits.size, _T_2680) @[RocketTiles.scala 50:21] + node _T_2699 = or(_T_2698, reset) @[RocketTiles.scala 50:21] + node _T_2701 = eq(_T_2699, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2701 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2702 = eq(io.in[0].d.bits.source, _T_2682) @[RocketTiles.scala 50:21] + node _T_2703 = or(_T_2702, reset) @[RocketTiles.scala 50:21] + node _T_2705 = eq(_T_2703, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2705 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2706 = eq(io.in[0].d.bits.sink, _T_2684) @[RocketTiles.scala 50:21] + node _T_2707 = or(_T_2706, reset) @[RocketTiles.scala 50:21] + node _T_2709 = eq(_T_2707, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2709 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2710 = eq(io.in[0].d.bits.addr_lo, _T_2686) @[RocketTiles.scala 50:21] + node _T_2711 = or(_T_2710, reset) @[RocketTiles.scala 50:21] + node _T_2713 = eq(_T_2711, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2713 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2714 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2715 = and(_T_2714, _T_2665) @[RocketTiles.scala 50:21] + when _T_2715 : @[RocketTiles.scala 50:21] + _T_2676 <= io.in[0].d.bits.opcode @[RocketTiles.scala 50:21] + _T_2678 <= io.in[0].d.bits.param @[RocketTiles.scala 50:21] + _T_2680 <= io.in[0].d.bits.size @[RocketTiles.scala 50:21] + _T_2682 <= io.in[0].d.bits.source @[RocketTiles.scala 50:21] + _T_2684 <= io.in[0].d.bits.sink @[RocketTiles.scala 50:21] + _T_2686 <= io.in[0].d.bits.addr_lo @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + reg _T_2717 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_2718 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2720 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2721 = dshl(_T_2720, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2722 = bits(_T_2721, 7, 0) @[package.scala 19:76] + node _T_2723 = not(_T_2722) @[package.scala 19:40] + node _T_2724 = shr(_T_2723, 3) @[Edges.scala 198:59] + node _T_2725 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2727 = eq(_T_2725, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2729 = mux(_T_2727, _T_2724, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2731 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2733 = sub(_T_2731, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2734 = asUInt(_T_2733) @[Edges.scala 208:28] + node _T_2735 = tail(_T_2734, 1) @[Edges.scala 208:28] + node _T_2737 = eq(_T_2731, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2739 = eq(_T_2731, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2741 = eq(_T_2729, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2742 = or(_T_2739, _T_2741) @[Edges.scala 210:37] + node _T_2743 = and(_T_2742, _T_2718) @[Edges.scala 211:22] + node _T_2744 = not(_T_2735) @[Edges.scala 212:27] + node _T_2745 = and(_T_2729, _T_2744) @[Edges.scala 212:25] + when _T_2718 : @[Edges.scala 213:17] + node _T_2746 = mux(_T_2737, _T_2729, _T_2735) @[Edges.scala 214:21] + _T_2731 <= _T_2746 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2747 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2749 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2750 = dshl(_T_2749, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2751 = bits(_T_2750, 7, 0) @[package.scala 19:76] + node _T_2752 = not(_T_2751) @[package.scala 19:40] + node _T_2753 = shr(_T_2752, 3) @[Edges.scala 198:59] + node _T_2754 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2756 = mux(_T_2754, _T_2753, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2758 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2760 = sub(_T_2758, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2761 = asUInt(_T_2760) @[Edges.scala 208:28] + node _T_2762 = tail(_T_2761, 1) @[Edges.scala 208:28] + node _T_2764 = eq(_T_2758, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2766 = eq(_T_2758, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2768 = eq(_T_2756, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2769 = or(_T_2766, _T_2768) @[Edges.scala 210:37] + node _T_2770 = and(_T_2769, _T_2747) @[Edges.scala 211:22] + node _T_2771 = not(_T_2762) @[Edges.scala 212:27] + node _T_2772 = and(_T_2756, _T_2771) @[Edges.scala 212:25] + when _T_2747 : @[Edges.scala 213:17] + node _T_2773 = mux(_T_2764, _T_2756, _T_2762) @[Edges.scala 214:21] + _T_2758 <= _T_2773 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2775 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + node _T_2776 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[RocketTiles.scala 50:21] + node _T_2777 = or(_T_2775, _T_2776) @[RocketTiles.scala 50:21] + node _T_2779 = eq(io.in[0].a.valid, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2780 = or(_T_2777, _T_2779) @[RocketTiles.scala 50:21] + node _T_2782 = eq(io.in[0].d.valid, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2783 = or(_T_2780, _T_2782) @[RocketTiles.scala 50:21] + node _T_2784 = or(_T_2783, reset) @[RocketTiles.scala 50:21] + node _T_2786 = eq(_T_2784, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2786 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at RocketTiles.scala:50:21)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + wire _T_2788 : UInt<1> + _T_2788 is invalid + _T_2788 <= UInt<1>("h00") + node _T_2789 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2789 : @[RocketTiles.scala 50:21] + when _T_2742 : @[RocketTiles.scala 50:21] + node _T_2791 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2788 <= _T_2791 @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2792 = dshr(_T_2717, io.in[0].a.bits.source) @[RocketTiles.scala 50:21] + node _T_2793 = bits(_T_2792, 0, 0) @[RocketTiles.scala 50:21] + node _T_2795 = eq(_T_2793, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2796 = or(_T_2795, reset) @[RocketTiles.scala 50:21] + node _T_2798 = eq(_T_2796, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2798 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + wire _T_2800 : UInt<1> + _T_2800 is invalid + _T_2800 <= UInt<1>("h00") + node _T_2801 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2803 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + node _T_2804 = and(_T_2801, _T_2803) @[RocketTiles.scala 50:21] + when _T_2804 : @[RocketTiles.scala 50:21] + when _T_2769 : @[RocketTiles.scala 50:21] + node _T_2806 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2800 <= _T_2806 @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2807 = or(_T_2788, _T_2717) @[RocketTiles.scala 50:21] + node _T_2808 = dshr(_T_2807, io.in[0].d.bits.source) @[RocketTiles.scala 50:21] + node _T_2809 = bits(_T_2808, 0, 0) @[RocketTiles.scala 50:21] + node _T_2810 = or(_T_2809, reset) @[RocketTiles.scala 50:21] + node _T_2812 = eq(_T_2810, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2812 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketTiles.scala:50:21)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2813 = or(_T_2717, _T_2788) @[RocketTiles.scala 50:21] + node _T_2814 = not(_T_2800) @[RocketTiles.scala 50:21] + node _T_2815 = and(_T_2813, _T_2814) @[RocketTiles.scala 50:21] + _T_2717 <= _T_2815 @[RocketTiles.scala 50:21] + when io.in[1].a.valid : @[RocketTiles.scala 50:21] + node _T_2817 = leq(io.in[1].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_2818 = or(_T_2817, reset) @[RocketTiles.scala 50:21] + node _T_2820 = eq(_T_2818, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2820 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2822 = eq(UInt<1>("h00"), io.in[1].a.bits.source) @[Parameters.scala 35:39] + wire _T_2825 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2825 is invalid @[Parameters.scala 228:27] + _T_2825[0] <= _T_2822 @[Parameters.scala 228:27] + node _T_2830 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2831 = dshl(_T_2830, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_2832 = bits(_T_2831, 7, 0) @[package.scala 19:76] + node _T_2833 = not(_T_2832) @[package.scala 19:40] + node _T_2834 = and(io.in[1].a.bits.address, _T_2833) @[Edges.scala 17:16] + node _T_2836 = eq(_T_2834, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2838 = bits(io.in[1].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_2839 = dshl(UInt<1>("h01"), _T_2838) @[OneHot.scala 49:12] + node _T_2840 = bits(_T_2839, 2, 0) @[OneHot.scala 49:37] + node _T_2842 = geq(io.in[1].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2844 = bits(_T_2840, 2, 2) @[package.scala 44:26] + node _T_2845 = bits(io.in[1].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_2847 = eq(_T_2845, UInt<1>("h00")) @[package.scala 46:20] + node _T_2848 = and(UInt<1>("h01"), _T_2847) @[package.scala 49:27] + node _T_2849 = and(_T_2844, _T_2848) @[package.scala 50:38] + node _T_2850 = or(_T_2842, _T_2849) @[package.scala 50:29] + node _T_2851 = and(UInt<1>("h01"), _T_2845) @[package.scala 49:27] + node _T_2852 = and(_T_2844, _T_2851) @[package.scala 50:38] + node _T_2853 = or(_T_2842, _T_2852) @[package.scala 50:29] + node _T_2854 = bits(_T_2840, 1, 1) @[package.scala 44:26] + node _T_2855 = bits(io.in[1].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_2857 = eq(_T_2855, UInt<1>("h00")) @[package.scala 46:20] + node _T_2858 = and(_T_2848, _T_2857) @[package.scala 49:27] + node _T_2859 = and(_T_2854, _T_2858) @[package.scala 50:38] + node _T_2860 = or(_T_2850, _T_2859) @[package.scala 50:29] + node _T_2861 = and(_T_2848, _T_2855) @[package.scala 49:27] + node _T_2862 = and(_T_2854, _T_2861) @[package.scala 50:38] + node _T_2863 = or(_T_2850, _T_2862) @[package.scala 50:29] + node _T_2864 = and(_T_2851, _T_2857) @[package.scala 49:27] + node _T_2865 = and(_T_2854, _T_2864) @[package.scala 50:38] + node _T_2866 = or(_T_2853, _T_2865) @[package.scala 50:29] + node _T_2867 = and(_T_2851, _T_2855) @[package.scala 49:27] + node _T_2868 = and(_T_2854, _T_2867) @[package.scala 50:38] + node _T_2869 = or(_T_2853, _T_2868) @[package.scala 50:29] + node _T_2870 = bits(_T_2840, 0, 0) @[package.scala 44:26] + node _T_2871 = bits(io.in[1].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_2873 = eq(_T_2871, UInt<1>("h00")) @[package.scala 46:20] + node _T_2874 = and(_T_2858, _T_2873) @[package.scala 49:27] + node _T_2875 = and(_T_2870, _T_2874) @[package.scala 50:38] + node _T_2876 = or(_T_2860, _T_2875) @[package.scala 50:29] + node _T_2877 = and(_T_2858, _T_2871) @[package.scala 49:27] + node _T_2878 = and(_T_2870, _T_2877) @[package.scala 50:38] + node _T_2879 = or(_T_2860, _T_2878) @[package.scala 50:29] + node _T_2880 = and(_T_2861, _T_2873) @[package.scala 49:27] + node _T_2881 = and(_T_2870, _T_2880) @[package.scala 50:38] + node _T_2882 = or(_T_2863, _T_2881) @[package.scala 50:29] + node _T_2883 = and(_T_2861, _T_2871) @[package.scala 49:27] + node _T_2884 = and(_T_2870, _T_2883) @[package.scala 50:38] + node _T_2885 = or(_T_2863, _T_2884) @[package.scala 50:29] + node _T_2886 = and(_T_2864, _T_2873) @[package.scala 49:27] + node _T_2887 = and(_T_2870, _T_2886) @[package.scala 50:38] + node _T_2888 = or(_T_2866, _T_2887) @[package.scala 50:29] + node _T_2889 = and(_T_2864, _T_2871) @[package.scala 49:27] + node _T_2890 = and(_T_2870, _T_2889) @[package.scala 50:38] + node _T_2891 = or(_T_2866, _T_2890) @[package.scala 50:29] + node _T_2892 = and(_T_2867, _T_2873) @[package.scala 49:27] + node _T_2893 = and(_T_2870, _T_2892) @[package.scala 50:38] + node _T_2894 = or(_T_2869, _T_2893) @[package.scala 50:29] + node _T_2895 = and(_T_2867, _T_2871) @[package.scala 49:27] + node _T_2896 = and(_T_2870, _T_2895) @[package.scala 50:38] + node _T_2897 = or(_T_2869, _T_2896) @[package.scala 50:29] + node _T_2898 = cat(_T_2879, _T_2876) @[Cat.scala 30:58] + node _T_2899 = cat(_T_2885, _T_2882) @[Cat.scala 30:58] + node _T_2900 = cat(_T_2899, _T_2898) @[Cat.scala 30:58] + node _T_2901 = cat(_T_2891, _T_2888) @[Cat.scala 30:58] + node _T_2902 = cat(_T_2897, _T_2894) @[Cat.scala 30:58] + node _T_2903 = cat(_T_2902, _T_2901) @[Cat.scala 30:58] + node _T_2904 = cat(_T_2903, _T_2900) @[Cat.scala 30:58] + node _T_2906 = eq(io.in[1].a.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_2906 : @[RocketTiles.scala 50:21] + node _T_2909 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_2911 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2912 = and(_T_2909, _T_2911) @[Parameters.scala 63:37] + node _T_2913 = or(UInt<1>("h00"), _T_2912) @[Parameters.scala 132:31] + node _T_2915 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2916 = cvt(_T_2915) @[Parameters.scala 117:49] + node _T_2918 = and(_T_2916, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2919 = asSInt(_T_2918) @[Parameters.scala 117:52] + node _T_2921 = eq(_T_2919, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2923 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2924 = cvt(_T_2923) @[Parameters.scala 117:49] + node _T_2926 = and(_T_2924, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2927 = asSInt(_T_2926) @[Parameters.scala 117:52] + node _T_2929 = eq(_T_2927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2930 = or(_T_2921, _T_2929) @[Parameters.scala 133:42] + node _T_2931 = and(_T_2913, _T_2930) @[Parameters.scala 132:56] + node _T_2934 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2936 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2937 = cvt(_T_2936) @[Parameters.scala 117:49] + node _T_2939 = and(_T_2937, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2940 = asSInt(_T_2939) @[Parameters.scala 117:52] + node _T_2942 = eq(_T_2940, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2944 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2945 = cvt(_T_2944) @[Parameters.scala 117:49] + node _T_2947 = and(_T_2945, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2948 = asSInt(_T_2947) @[Parameters.scala 117:52] + node _T_2950 = eq(_T_2948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2952 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2953 = cvt(_T_2952) @[Parameters.scala 117:49] + node _T_2955 = and(_T_2953, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2956 = asSInt(_T_2955) @[Parameters.scala 117:52] + node _T_2958 = eq(_T_2956, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2960 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2961 = cvt(_T_2960) @[Parameters.scala 117:49] + node _T_2963 = and(_T_2961, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2964 = asSInt(_T_2963) @[Parameters.scala 117:52] + node _T_2966 = eq(_T_2964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2967 = or(_T_2942, _T_2950) @[Parameters.scala 133:42] + node _T_2968 = or(_T_2967, _T_2958) @[Parameters.scala 133:42] + node _T_2969 = or(_T_2968, _T_2966) @[Parameters.scala 133:42] + node _T_2970 = and(_T_2934, _T_2969) @[Parameters.scala 132:56] + node _T_2972 = or(UInt<1>("h00"), _T_2931) @[Parameters.scala 134:30] + node _T_2973 = or(_T_2972, _T_2970) @[Parameters.scala 134:30] + node _T_2974 = or(_T_2973, reset) @[RocketTiles.scala 50:21] + node _T_2976 = eq(_T_2974, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2976 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2977 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_2979 = eq(_T_2977, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2979 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2981 = geq(io.in[1].a.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_2982 = or(_T_2981, reset) @[RocketTiles.scala 50:21] + node _T_2984 = eq(_T_2982, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2984 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2985 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_2987 = eq(_T_2985, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2987 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2989 = leq(io.in[1].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_2990 = or(_T_2989, reset) @[RocketTiles.scala 50:21] + node _T_2992 = eq(_T_2990, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2992 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_2993 = not(io.in[1].a.bits.mask) @[RocketTiles.scala 50:21] + node _T_2995 = eq(_T_2993, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_2996 = or(_T_2995, reset) @[RocketTiles.scala 50:21] + node _T_2998 = eq(_T_2996, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_2998 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3000 = eq(io.in[1].a.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_3000 : @[RocketTiles.scala 50:21] + node _T_3003 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3005 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3006 = and(_T_3003, _T_3005) @[Parameters.scala 63:37] + node _T_3007 = or(UInt<1>("h00"), _T_3006) @[Parameters.scala 132:31] + node _T_3009 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3010 = cvt(_T_3009) @[Parameters.scala 117:49] + node _T_3012 = and(_T_3010, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_3013 = asSInt(_T_3012) @[Parameters.scala 117:52] + node _T_3015 = eq(_T_3013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3017 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3018 = cvt(_T_3017) @[Parameters.scala 117:49] + node _T_3020 = and(_T_3018, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3021 = asSInt(_T_3020) @[Parameters.scala 117:52] + node _T_3023 = eq(_T_3021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3025 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3026 = cvt(_T_3025) @[Parameters.scala 117:49] + node _T_3028 = and(_T_3026, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3029 = asSInt(_T_3028) @[Parameters.scala 117:52] + node _T_3031 = eq(_T_3029, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3033 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3034 = cvt(_T_3033) @[Parameters.scala 117:49] + node _T_3036 = and(_T_3034, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3037 = asSInt(_T_3036) @[Parameters.scala 117:52] + node _T_3039 = eq(_T_3037, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3041 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3042 = cvt(_T_3041) @[Parameters.scala 117:49] + node _T_3044 = and(_T_3042, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3045 = asSInt(_T_3044) @[Parameters.scala 117:52] + node _T_3047 = eq(_T_3045, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3048 = or(_T_3015, _T_3023) @[Parameters.scala 133:42] + node _T_3049 = or(_T_3048, _T_3031) @[Parameters.scala 133:42] + node _T_3050 = or(_T_3049, _T_3039) @[Parameters.scala 133:42] + node _T_3051 = or(_T_3050, _T_3047) @[Parameters.scala 133:42] + node _T_3052 = and(_T_3007, _T_3051) @[Parameters.scala 132:56] + node _T_3055 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3057 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3058 = and(_T_3055, _T_3057) @[Parameters.scala 63:37] + node _T_3059 = or(UInt<1>("h00"), _T_3058) @[Parameters.scala 132:31] + node _T_3061 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3062 = cvt(_T_3061) @[Parameters.scala 117:49] + node _T_3064 = and(_T_3062, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3065 = asSInt(_T_3064) @[Parameters.scala 117:52] + node _T_3067 = eq(_T_3065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3068 = and(_T_3059, _T_3067) @[Parameters.scala 132:56] + node _T_3070 = or(UInt<1>("h00"), _T_3052) @[Parameters.scala 134:30] + node _T_3071 = or(_T_3070, _T_3068) @[Parameters.scala 134:30] + node _T_3072 = or(_T_3071, reset) @[RocketTiles.scala 50:21] + node _T_3074 = eq(_T_3072, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3074 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3075 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3077 = eq(_T_3075, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3077 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3078 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3080 = eq(_T_3078, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3080 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3082 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3083 = or(_T_3082, reset) @[RocketTiles.scala 50:21] + node _T_3085 = eq(_T_3083, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3085 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3086 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 50:21] + node _T_3087 = or(_T_3086, reset) @[RocketTiles.scala 50:21] + node _T_3089 = eq(_T_3087, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3089 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3091 = eq(io.in[1].a.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3091 : @[RocketTiles.scala 50:21] + node _T_3094 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3096 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3097 = and(_T_3094, _T_3096) @[Parameters.scala 63:37] + node _T_3098 = or(UInt<1>("h00"), _T_3097) @[Parameters.scala 132:31] + node _T_3100 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3101 = cvt(_T_3100) @[Parameters.scala 117:49] + node _T_3103 = and(_T_3101, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3104 = asSInt(_T_3103) @[Parameters.scala 117:52] + node _T_3106 = eq(_T_3104, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3108 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3109 = cvt(_T_3108) @[Parameters.scala 117:49] + node _T_3111 = and(_T_3109, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3112 = asSInt(_T_3111) @[Parameters.scala 117:52] + node _T_3114 = eq(_T_3112, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3116 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3117 = cvt(_T_3116) @[Parameters.scala 117:49] + node _T_3119 = and(_T_3117, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3120 = asSInt(_T_3119) @[Parameters.scala 117:52] + node _T_3122 = eq(_T_3120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3124 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3125 = cvt(_T_3124) @[Parameters.scala 117:49] + node _T_3127 = and(_T_3125, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3128 = asSInt(_T_3127) @[Parameters.scala 117:52] + node _T_3130 = eq(_T_3128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3132 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3133 = cvt(_T_3132) @[Parameters.scala 117:49] + node _T_3135 = and(_T_3133, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3136 = asSInt(_T_3135) @[Parameters.scala 117:52] + node _T_3138 = eq(_T_3136, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3139 = or(_T_3106, _T_3114) @[Parameters.scala 133:42] + node _T_3140 = or(_T_3139, _T_3122) @[Parameters.scala 133:42] + node _T_3141 = or(_T_3140, _T_3130) @[Parameters.scala 133:42] + node _T_3142 = or(_T_3141, _T_3138) @[Parameters.scala 133:42] + node _T_3143 = and(_T_3098, _T_3142) @[Parameters.scala 132:56] + node _T_3146 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3148 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3149 = and(_T_3146, _T_3148) @[Parameters.scala 63:37] + node _T_3150 = or(UInt<1>("h00"), _T_3149) @[Parameters.scala 132:31] + node _T_3152 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3153 = cvt(_T_3152) @[Parameters.scala 117:49] + node _T_3155 = and(_T_3153, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3156 = asSInt(_T_3155) @[Parameters.scala 117:52] + node _T_3158 = eq(_T_3156, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3159 = and(_T_3150, _T_3158) @[Parameters.scala 132:56] + node _T_3162 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3164 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3165 = cvt(_T_3164) @[Parameters.scala 117:49] + node _T_3167 = and(_T_3165, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3168 = asSInt(_T_3167) @[Parameters.scala 117:52] + node _T_3170 = eq(_T_3168, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3171 = and(_T_3162, _T_3170) @[Parameters.scala 132:56] + node _T_3173 = or(UInt<1>("h00"), _T_3143) @[Parameters.scala 134:30] + node _T_3174 = or(_T_3173, _T_3159) @[Parameters.scala 134:30] + node _T_3175 = or(_T_3174, _T_3171) @[Parameters.scala 134:30] + node _T_3176 = or(_T_3175, reset) @[RocketTiles.scala 50:21] + node _T_3178 = eq(_T_3176, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3178 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3179 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3181 = eq(_T_3179, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3181 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3182 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3184 = eq(_T_3182, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3184 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3186 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3187 = or(_T_3186, reset) @[RocketTiles.scala 50:21] + node _T_3189 = eq(_T_3187, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3189 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3190 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 50:21] + node _T_3191 = or(_T_3190, reset) @[RocketTiles.scala 50:21] + node _T_3193 = eq(_T_3191, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3193 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3195 = eq(io.in[1].a.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_3195 : @[RocketTiles.scala 50:21] + node _T_3198 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3200 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3201 = and(_T_3198, _T_3200) @[Parameters.scala 63:37] + node _T_3202 = or(UInt<1>("h00"), _T_3201) @[Parameters.scala 132:31] + node _T_3204 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3205 = cvt(_T_3204) @[Parameters.scala 117:49] + node _T_3207 = and(_T_3205, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3208 = asSInt(_T_3207) @[Parameters.scala 117:52] + node _T_3210 = eq(_T_3208, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3212 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3213 = cvt(_T_3212) @[Parameters.scala 117:49] + node _T_3215 = and(_T_3213, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3216 = asSInt(_T_3215) @[Parameters.scala 117:52] + node _T_3218 = eq(_T_3216, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3220 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3221 = cvt(_T_3220) @[Parameters.scala 117:49] + node _T_3223 = and(_T_3221, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3224 = asSInt(_T_3223) @[Parameters.scala 117:52] + node _T_3226 = eq(_T_3224, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3228 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3229 = cvt(_T_3228) @[Parameters.scala 117:49] + node _T_3231 = and(_T_3229, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3232 = asSInt(_T_3231) @[Parameters.scala 117:52] + node _T_3234 = eq(_T_3232, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3236 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3237 = cvt(_T_3236) @[Parameters.scala 117:49] + node _T_3239 = and(_T_3237, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3240 = asSInt(_T_3239) @[Parameters.scala 117:52] + node _T_3242 = eq(_T_3240, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3243 = or(_T_3210, _T_3218) @[Parameters.scala 133:42] + node _T_3244 = or(_T_3243, _T_3226) @[Parameters.scala 133:42] + node _T_3245 = or(_T_3244, _T_3234) @[Parameters.scala 133:42] + node _T_3246 = or(_T_3245, _T_3242) @[Parameters.scala 133:42] + node _T_3247 = and(_T_3202, _T_3246) @[Parameters.scala 132:56] + node _T_3250 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3252 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3253 = and(_T_3250, _T_3252) @[Parameters.scala 63:37] + node _T_3254 = or(UInt<1>("h00"), _T_3253) @[Parameters.scala 132:31] + node _T_3256 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3257 = cvt(_T_3256) @[Parameters.scala 117:49] + node _T_3259 = and(_T_3257, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3260 = asSInt(_T_3259) @[Parameters.scala 117:52] + node _T_3262 = eq(_T_3260, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3263 = and(_T_3254, _T_3262) @[Parameters.scala 132:56] + node _T_3266 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3268 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3269 = cvt(_T_3268) @[Parameters.scala 117:49] + node _T_3271 = and(_T_3269, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3272 = asSInt(_T_3271) @[Parameters.scala 117:52] + node _T_3274 = eq(_T_3272, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3275 = and(_T_3266, _T_3274) @[Parameters.scala 132:56] + node _T_3277 = or(UInt<1>("h00"), _T_3247) @[Parameters.scala 134:30] + node _T_3278 = or(_T_3277, _T_3263) @[Parameters.scala 134:30] + node _T_3279 = or(_T_3278, _T_3275) @[Parameters.scala 134:30] + node _T_3280 = or(_T_3279, reset) @[RocketTiles.scala 50:21] + node _T_3282 = eq(_T_3280, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3282 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3283 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3285 = eq(_T_3283, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3285 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3286 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3288 = eq(_T_3286, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3288 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3290 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3291 = or(_T_3290, reset) @[RocketTiles.scala 50:21] + node _T_3293 = eq(_T_3291, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3293 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3294 = not(_T_2904) @[RocketTiles.scala 50:21] + node _T_3295 = and(io.in[1].a.bits.mask, _T_3294) @[RocketTiles.scala 50:21] + node _T_3297 = eq(_T_3295, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3298 = or(_T_3297, reset) @[RocketTiles.scala 50:21] + node _T_3300 = eq(_T_3298, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3300 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3302 = eq(io.in[1].a.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_3302 : @[RocketTiles.scala 50:21] + node _T_3305 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3307 = leq(io.in[1].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3308 = and(_T_3305, _T_3307) @[Parameters.scala 63:37] + node _T_3309 = or(UInt<1>("h00"), _T_3308) @[Parameters.scala 132:31] + node _T_3311 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3312 = cvt(_T_3311) @[Parameters.scala 117:49] + node _T_3314 = and(_T_3312, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3315 = asSInt(_T_3314) @[Parameters.scala 117:52] + node _T_3317 = eq(_T_3315, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3319 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3320 = cvt(_T_3319) @[Parameters.scala 117:49] + node _T_3322 = and(_T_3320, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3323 = asSInt(_T_3322) @[Parameters.scala 117:52] + node _T_3325 = eq(_T_3323, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3327 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3328 = cvt(_T_3327) @[Parameters.scala 117:49] + node _T_3330 = and(_T_3328, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3331 = asSInt(_T_3330) @[Parameters.scala 117:52] + node _T_3333 = eq(_T_3331, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3334 = or(_T_3317, _T_3325) @[Parameters.scala 133:42] + node _T_3335 = or(_T_3334, _T_3333) @[Parameters.scala 133:42] + node _T_3336 = and(_T_3309, _T_3335) @[Parameters.scala 132:56] + node _T_3339 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3341 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3342 = cvt(_T_3341) @[Parameters.scala 117:49] + node _T_3344 = and(_T_3342, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3345 = asSInt(_T_3344) @[Parameters.scala 117:52] + node _T_3347 = eq(_T_3345, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3349 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3350 = cvt(_T_3349) @[Parameters.scala 117:49] + node _T_3352 = and(_T_3350, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3353 = asSInt(_T_3352) @[Parameters.scala 117:52] + node _T_3355 = eq(_T_3353, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3357 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3358 = cvt(_T_3357) @[Parameters.scala 117:49] + node _T_3360 = and(_T_3358, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3361 = asSInt(_T_3360) @[Parameters.scala 117:52] + node _T_3363 = eq(_T_3361, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3365 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3366 = cvt(_T_3365) @[Parameters.scala 117:49] + node _T_3368 = and(_T_3366, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3369 = asSInt(_T_3368) @[Parameters.scala 117:52] + node _T_3371 = eq(_T_3369, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3372 = or(_T_3347, _T_3355) @[Parameters.scala 133:42] + node _T_3373 = or(_T_3372, _T_3363) @[Parameters.scala 133:42] + node _T_3374 = or(_T_3373, _T_3371) @[Parameters.scala 133:42] + node _T_3375 = and(_T_3339, _T_3374) @[Parameters.scala 132:56] + node _T_3377 = or(UInt<1>("h00"), _T_3336) @[Parameters.scala 134:30] + node _T_3378 = or(_T_3377, _T_3375) @[Parameters.scala 134:30] + node _T_3379 = or(_T_3378, reset) @[RocketTiles.scala 50:21] + node _T_3381 = eq(_T_3379, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3381 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3382 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3384 = eq(_T_3382, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3384 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3385 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3387 = eq(_T_3385, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3387 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3389 = leq(io.in[1].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_3390 = or(_T_3389, reset) @[RocketTiles.scala 50:21] + node _T_3392 = eq(_T_3390, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3392 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3393 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 50:21] + node _T_3394 = or(_T_3393, reset) @[RocketTiles.scala 50:21] + node _T_3396 = eq(_T_3394, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3396 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3398 = eq(io.in[1].a.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 50:21] + when _T_3398 : @[RocketTiles.scala 50:21] + node _T_3401 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3403 = leq(io.in[1].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3404 = and(_T_3401, _T_3403) @[Parameters.scala 63:37] + node _T_3405 = or(UInt<1>("h00"), _T_3404) @[Parameters.scala 132:31] + node _T_3407 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3408 = cvt(_T_3407) @[Parameters.scala 117:49] + node _T_3410 = and(_T_3408, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3411 = asSInt(_T_3410) @[Parameters.scala 117:52] + node _T_3413 = eq(_T_3411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3415 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3416 = cvt(_T_3415) @[Parameters.scala 117:49] + node _T_3418 = and(_T_3416, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3419 = asSInt(_T_3418) @[Parameters.scala 117:52] + node _T_3421 = eq(_T_3419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3423 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3424 = cvt(_T_3423) @[Parameters.scala 117:49] + node _T_3426 = and(_T_3424, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3427 = asSInt(_T_3426) @[Parameters.scala 117:52] + node _T_3429 = eq(_T_3427, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3430 = or(_T_3413, _T_3421) @[Parameters.scala 133:42] + node _T_3431 = or(_T_3430, _T_3429) @[Parameters.scala 133:42] + node _T_3432 = and(_T_3405, _T_3431) @[Parameters.scala 132:56] + node _T_3435 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3437 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3438 = cvt(_T_3437) @[Parameters.scala 117:49] + node _T_3440 = and(_T_3438, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3441 = asSInt(_T_3440) @[Parameters.scala 117:52] + node _T_3443 = eq(_T_3441, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3445 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3446 = cvt(_T_3445) @[Parameters.scala 117:49] + node _T_3448 = and(_T_3446, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3449 = asSInt(_T_3448) @[Parameters.scala 117:52] + node _T_3451 = eq(_T_3449, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3453 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3454 = cvt(_T_3453) @[Parameters.scala 117:49] + node _T_3456 = and(_T_3454, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3457 = asSInt(_T_3456) @[Parameters.scala 117:52] + node _T_3459 = eq(_T_3457, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3461 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3462 = cvt(_T_3461) @[Parameters.scala 117:49] + node _T_3464 = and(_T_3462, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3465 = asSInt(_T_3464) @[Parameters.scala 117:52] + node _T_3467 = eq(_T_3465, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3468 = or(_T_3443, _T_3451) @[Parameters.scala 133:42] + node _T_3469 = or(_T_3468, _T_3459) @[Parameters.scala 133:42] + node _T_3470 = or(_T_3469, _T_3467) @[Parameters.scala 133:42] + node _T_3471 = and(_T_3435, _T_3470) @[Parameters.scala 132:56] + node _T_3473 = or(UInt<1>("h00"), _T_3432) @[Parameters.scala 134:30] + node _T_3474 = or(_T_3473, _T_3471) @[Parameters.scala 134:30] + node _T_3475 = or(_T_3474, reset) @[RocketTiles.scala 50:21] + node _T_3477 = eq(_T_3475, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3477 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3478 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3480 = eq(_T_3478, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3480 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3481 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3483 = eq(_T_3481, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3483 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3485 = leq(io.in[1].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_3486 = or(_T_3485, reset) @[RocketTiles.scala 50:21] + node _T_3488 = eq(_T_3486, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3488 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3489 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 50:21] + node _T_3490 = or(_T_3489, reset) @[RocketTiles.scala 50:21] + node _T_3492 = eq(_T_3490, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3492 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3494 = eq(io.in[1].a.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_3494 : @[RocketTiles.scala 50:21] + node _T_3497 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3499 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3500 = cvt(_T_3499) @[Parameters.scala 117:49] + node _T_3502 = and(_T_3500, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_3503 = asSInt(_T_3502) @[Parameters.scala 117:52] + node _T_3505 = eq(_T_3503, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3507 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3508 = cvt(_T_3507) @[Parameters.scala 117:49] + node _T_3510 = and(_T_3508, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3511 = asSInt(_T_3510) @[Parameters.scala 117:52] + node _T_3513 = eq(_T_3511, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3515 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3516 = cvt(_T_3515) @[Parameters.scala 117:49] + node _T_3518 = and(_T_3516, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3519 = asSInt(_T_3518) @[Parameters.scala 117:52] + node _T_3521 = eq(_T_3519, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3523 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3524 = cvt(_T_3523) @[Parameters.scala 117:49] + node _T_3526 = and(_T_3524, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3527 = asSInt(_T_3526) @[Parameters.scala 117:52] + node _T_3529 = eq(_T_3527, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3531 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3532 = cvt(_T_3531) @[Parameters.scala 117:49] + node _T_3534 = and(_T_3532, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3535 = asSInt(_T_3534) @[Parameters.scala 117:52] + node _T_3537 = eq(_T_3535, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3539 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3540 = cvt(_T_3539) @[Parameters.scala 117:49] + node _T_3542 = and(_T_3540, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3543 = asSInt(_T_3542) @[Parameters.scala 117:52] + node _T_3545 = eq(_T_3543, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3546 = or(_T_3505, _T_3513) @[Parameters.scala 133:42] + node _T_3547 = or(_T_3546, _T_3521) @[Parameters.scala 133:42] + node _T_3548 = or(_T_3547, _T_3529) @[Parameters.scala 133:42] + node _T_3549 = or(_T_3548, _T_3537) @[Parameters.scala 133:42] + node _T_3550 = or(_T_3549, _T_3545) @[Parameters.scala 133:42] + node _T_3551 = and(_T_3497, _T_3550) @[Parameters.scala 132:56] + node _T_3553 = or(UInt<1>("h00"), _T_3551) @[Parameters.scala 134:30] + node _T_3554 = or(_T_3553, reset) @[RocketTiles.scala 50:21] + node _T_3556 = eq(_T_3554, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3556 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3557 = or(_T_2825[0], reset) @[RocketTiles.scala 50:21] + node _T_3559 = eq(_T_3557, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3559 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3560 = or(_T_2836, reset) @[RocketTiles.scala 50:21] + node _T_3562 = eq(_T_3560, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3562 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3563 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 50:21] + node _T_3564 = or(_T_3563, reset) @[RocketTiles.scala 50:21] + node _T_3566 = eq(_T_3564, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3566 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[1].b.valid : @[RocketTiles.scala 50:21] + node _T_3568 = leq(io.in[1].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_3569 = or(_T_3568, reset) @[RocketTiles.scala 50:21] + node _T_3571 = eq(_T_3569, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3571 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3573 = xor(io.in[1].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3574 = cvt(_T_3573) @[Parameters.scala 117:49] + node _T_3576 = and(_T_3574, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3577 = asSInt(_T_3576) @[Parameters.scala 117:52] + node _T_3579 = eq(_T_3577, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3581 = xor(io.in[1].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3582 = cvt(_T_3581) @[Parameters.scala 117:49] + node _T_3584 = and(_T_3582, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3585 = asSInt(_T_3584) @[Parameters.scala 117:52] + node _T_3587 = eq(_T_3585, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3589 = xor(io.in[1].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3590 = cvt(_T_3589) @[Parameters.scala 117:49] + node _T_3592 = and(_T_3590, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3593 = asSInt(_T_3592) @[Parameters.scala 117:52] + node _T_3595 = eq(_T_3593, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3597 = xor(io.in[1].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3598 = cvt(_T_3597) @[Parameters.scala 117:49] + node _T_3600 = and(_T_3598, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3601 = asSInt(_T_3600) @[Parameters.scala 117:52] + node _T_3603 = eq(_T_3601, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3605 = xor(io.in[1].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3606 = cvt(_T_3605) @[Parameters.scala 117:49] + node _T_3608 = and(_T_3606, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3609 = asSInt(_T_3608) @[Parameters.scala 117:52] + node _T_3611 = eq(_T_3609, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3613 = xor(io.in[1].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3614 = cvt(_T_3613) @[Parameters.scala 117:49] + node _T_3616 = and(_T_3614, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3617 = asSInt(_T_3616) @[Parameters.scala 117:52] + node _T_3619 = eq(_T_3617, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3621 = xor(io.in[1].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3622 = cvt(_T_3621) @[Parameters.scala 117:49] + node _T_3624 = and(_T_3622, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3625 = asSInt(_T_3624) @[Parameters.scala 117:52] + node _T_3627 = eq(_T_3625, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3630 : UInt<1>[7] @[Parameters.scala 110:36] + _T_3630 is invalid @[Parameters.scala 110:36] + _T_3630[0] <= _T_3579 @[Parameters.scala 110:36] + _T_3630[1] <= _T_3587 @[Parameters.scala 110:36] + _T_3630[2] <= _T_3595 @[Parameters.scala 110:36] + _T_3630[3] <= _T_3603 @[Parameters.scala 110:36] + _T_3630[4] <= _T_3611 @[Parameters.scala 110:36] + _T_3630[5] <= _T_3619 @[Parameters.scala 110:36] + _T_3630[6] <= _T_3627 @[Parameters.scala 110:36] + node _T_3640 = or(_T_3630[0], _T_3630[1]) @[Parameters.scala 119:64] + node _T_3641 = or(_T_3640, _T_3630[2]) @[Parameters.scala 119:64] + node _T_3642 = or(_T_3641, _T_3630[3]) @[Parameters.scala 119:64] + node _T_3643 = or(_T_3642, _T_3630[4]) @[Parameters.scala 119:64] + node _T_3644 = or(_T_3643, _T_3630[5]) @[Parameters.scala 119:64] + node _T_3645 = or(_T_3644, _T_3630[6]) @[Parameters.scala 119:64] + node _T_3647 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_3648 = dshl(_T_3647, io.in[1].b.bits.size) @[package.scala 19:71] + node _T_3649 = bits(_T_3648, 7, 0) @[package.scala 19:76] + node _T_3650 = not(_T_3649) @[package.scala 19:40] + node _T_3651 = and(io.in[1].b.bits.address, _T_3650) @[Edges.scala 17:16] + node _T_3653 = eq(_T_3651, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_3655 = bits(io.in[1].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_3656 = dshl(UInt<1>("h01"), _T_3655) @[OneHot.scala 49:12] + node _T_3657 = bits(_T_3656, 2, 0) @[OneHot.scala 49:37] + node _T_3659 = geq(io.in[1].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3661 = bits(_T_3657, 2, 2) @[package.scala 44:26] + node _T_3662 = bits(io.in[1].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_3664 = eq(_T_3662, UInt<1>("h00")) @[package.scala 46:20] + node _T_3665 = and(UInt<1>("h01"), _T_3664) @[package.scala 49:27] + node _T_3666 = and(_T_3661, _T_3665) @[package.scala 50:38] + node _T_3667 = or(_T_3659, _T_3666) @[package.scala 50:29] + node _T_3668 = and(UInt<1>("h01"), _T_3662) @[package.scala 49:27] + node _T_3669 = and(_T_3661, _T_3668) @[package.scala 50:38] + node _T_3670 = or(_T_3659, _T_3669) @[package.scala 50:29] + node _T_3671 = bits(_T_3657, 1, 1) @[package.scala 44:26] + node _T_3672 = bits(io.in[1].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_3674 = eq(_T_3672, UInt<1>("h00")) @[package.scala 46:20] + node _T_3675 = and(_T_3665, _T_3674) @[package.scala 49:27] + node _T_3676 = and(_T_3671, _T_3675) @[package.scala 50:38] + node _T_3677 = or(_T_3667, _T_3676) @[package.scala 50:29] + node _T_3678 = and(_T_3665, _T_3672) @[package.scala 49:27] + node _T_3679 = and(_T_3671, _T_3678) @[package.scala 50:38] + node _T_3680 = or(_T_3667, _T_3679) @[package.scala 50:29] + node _T_3681 = and(_T_3668, _T_3674) @[package.scala 49:27] + node _T_3682 = and(_T_3671, _T_3681) @[package.scala 50:38] + node _T_3683 = or(_T_3670, _T_3682) @[package.scala 50:29] + node _T_3684 = and(_T_3668, _T_3672) @[package.scala 49:27] + node _T_3685 = and(_T_3671, _T_3684) @[package.scala 50:38] + node _T_3686 = or(_T_3670, _T_3685) @[package.scala 50:29] + node _T_3687 = bits(_T_3657, 0, 0) @[package.scala 44:26] + node _T_3688 = bits(io.in[1].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_3690 = eq(_T_3688, UInt<1>("h00")) @[package.scala 46:20] + node _T_3691 = and(_T_3675, _T_3690) @[package.scala 49:27] + node _T_3692 = and(_T_3687, _T_3691) @[package.scala 50:38] + node _T_3693 = or(_T_3677, _T_3692) @[package.scala 50:29] + node _T_3694 = and(_T_3675, _T_3688) @[package.scala 49:27] + node _T_3695 = and(_T_3687, _T_3694) @[package.scala 50:38] + node _T_3696 = or(_T_3677, _T_3695) @[package.scala 50:29] + node _T_3697 = and(_T_3678, _T_3690) @[package.scala 49:27] + node _T_3698 = and(_T_3687, _T_3697) @[package.scala 50:38] + node _T_3699 = or(_T_3680, _T_3698) @[package.scala 50:29] + node _T_3700 = and(_T_3678, _T_3688) @[package.scala 49:27] + node _T_3701 = and(_T_3687, _T_3700) @[package.scala 50:38] + node _T_3702 = or(_T_3680, _T_3701) @[package.scala 50:29] + node _T_3703 = and(_T_3681, _T_3690) @[package.scala 49:27] + node _T_3704 = and(_T_3687, _T_3703) @[package.scala 50:38] + node _T_3705 = or(_T_3683, _T_3704) @[package.scala 50:29] + node _T_3706 = and(_T_3681, _T_3688) @[package.scala 49:27] + node _T_3707 = and(_T_3687, _T_3706) @[package.scala 50:38] + node _T_3708 = or(_T_3683, _T_3707) @[package.scala 50:29] + node _T_3709 = and(_T_3684, _T_3690) @[package.scala 49:27] + node _T_3710 = and(_T_3687, _T_3709) @[package.scala 50:38] + node _T_3711 = or(_T_3686, _T_3710) @[package.scala 50:29] + node _T_3712 = and(_T_3684, _T_3688) @[package.scala 49:27] + node _T_3713 = and(_T_3687, _T_3712) @[package.scala 50:38] + node _T_3714 = or(_T_3686, _T_3713) @[package.scala 50:29] + node _T_3715 = cat(_T_3696, _T_3693) @[Cat.scala 30:58] + node _T_3716 = cat(_T_3702, _T_3699) @[Cat.scala 30:58] + node _T_3717 = cat(_T_3716, _T_3715) @[Cat.scala 30:58] + node _T_3718 = cat(_T_3708, _T_3705) @[Cat.scala 30:58] + node _T_3719 = cat(_T_3714, _T_3711) @[Cat.scala 30:58] + node _T_3720 = cat(_T_3719, _T_3718) @[Cat.scala 30:58] + node _T_3721 = cat(_T_3720, _T_3717) @[Cat.scala 30:58] + node _T_3723 = eq(io.in[1].b.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_3723 : @[RocketTiles.scala 50:21] + node _T_3725 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3727 = eq(_T_3725, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3727 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3728 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3730 = eq(_T_3728, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3730 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3732 = geq(io.in[1].b.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_3733 = or(_T_3732, reset) @[RocketTiles.scala 50:21] + node _T_3735 = eq(_T_3733, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3735 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3736 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3738 = eq(_T_3736, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3738 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3740 = leq(io.in[1].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_3741 = or(_T_3740, reset) @[RocketTiles.scala 50:21] + node _T_3743 = eq(_T_3741, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3743 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3744 = not(io.in[1].b.bits.mask) @[RocketTiles.scala 50:21] + node _T_3746 = eq(_T_3744, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3747 = or(_T_3746, reset) @[RocketTiles.scala 50:21] + node _T_3749 = eq(_T_3747, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3749 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3751 = eq(io.in[1].b.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_3751 : @[RocketTiles.scala 50:21] + node _T_3753 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3755 = eq(_T_3753, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3755 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3756 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3758 = eq(_T_3756, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3758 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3759 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3761 = eq(_T_3759, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3761 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3763 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3764 = or(_T_3763, reset) @[RocketTiles.scala 50:21] + node _T_3766 = eq(_T_3764, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3766 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3767 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 50:21] + node _T_3768 = or(_T_3767, reset) @[RocketTiles.scala 50:21] + node _T_3770 = eq(_T_3768, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3770 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3772 = eq(io.in[1].b.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3772 : @[RocketTiles.scala 50:21] + node _T_3774 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3776 = eq(_T_3774, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3776 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3777 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3779 = eq(_T_3777, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3779 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3780 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3782 = eq(_T_3780, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3782 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3784 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3785 = or(_T_3784, reset) @[RocketTiles.scala 50:21] + node _T_3787 = eq(_T_3785, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3787 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3788 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 50:21] + node _T_3789 = or(_T_3788, reset) @[RocketTiles.scala 50:21] + node _T_3791 = eq(_T_3789, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3791 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3793 = eq(io.in[1].b.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_3793 : @[RocketTiles.scala 50:21] + node _T_3795 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3797 = eq(_T_3795, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3797 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3798 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3800 = eq(_T_3798, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3800 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3801 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3803 = eq(_T_3801, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3803 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3805 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3806 = or(_T_3805, reset) @[RocketTiles.scala 50:21] + node _T_3808 = eq(_T_3806, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3808 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3809 = not(_T_3721) @[RocketTiles.scala 50:21] + node _T_3810 = and(io.in[1].b.bits.mask, _T_3809) @[RocketTiles.scala 50:21] + node _T_3812 = eq(_T_3810, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3813 = or(_T_3812, reset) @[RocketTiles.scala 50:21] + node _T_3815 = eq(_T_3813, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3815 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3817 = eq(io.in[1].b.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_3817 : @[RocketTiles.scala 50:21] + node _T_3819 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3821 = eq(_T_3819, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3821 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3822 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3824 = eq(_T_3822, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3824 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3825 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3827 = eq(_T_3825, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3827 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3829 = leq(io.in[1].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_3830 = or(_T_3829, reset) @[RocketTiles.scala 50:21] + node _T_3832 = eq(_T_3830, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3832 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3833 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 50:21] + node _T_3834 = or(_T_3833, reset) @[RocketTiles.scala 50:21] + node _T_3836 = eq(_T_3834, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3836 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3838 = eq(io.in[1].b.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 50:21] + when _T_3838 : @[RocketTiles.scala 50:21] + node _T_3840 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3842 = eq(_T_3840, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3842 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3843 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3845 = eq(_T_3843, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3845 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3846 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3848 = eq(_T_3846, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3848 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3850 = leq(io.in[1].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_3851 = or(_T_3850, reset) @[RocketTiles.scala 50:21] + node _T_3853 = eq(_T_3851, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3853 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3854 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 50:21] + node _T_3855 = or(_T_3854, reset) @[RocketTiles.scala 50:21] + node _T_3857 = eq(_T_3855, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3857 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3859 = eq(io.in[1].b.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_3859 : @[RocketTiles.scala 50:21] + node _T_3861 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 50:21] + node _T_3863 = eq(_T_3861, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3863 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketTiles.scala:50:21)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3864 = or(_T_3645, reset) @[RocketTiles.scala 50:21] + node _T_3866 = eq(_T_3864, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3866 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3867 = or(_T_3653, reset) @[RocketTiles.scala 50:21] + node _T_3869 = eq(_T_3867, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3869 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3870 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 50:21] + node _T_3871 = or(_T_3870, reset) @[RocketTiles.scala 50:21] + node _T_3873 = eq(_T_3871, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3873 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketTiles.scala:50:21)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[1].c.valid : @[RocketTiles.scala 50:21] + node _T_3875 = leq(io.in[1].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_3876 = or(_T_3875, reset) @[RocketTiles.scala 50:21] + node _T_3878 = eq(_T_3876, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3878 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3880 = eq(UInt<1>("h00"), io.in[1].c.bits.source) @[Parameters.scala 35:39] + wire _T_3883 : UInt<1>[1] @[Parameters.scala 228:27] + _T_3883 is invalid @[Parameters.scala 228:27] + _T_3883[0] <= _T_3880 @[Parameters.scala 228:27] + node _T_3888 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_3889 = dshl(_T_3888, io.in[1].c.bits.size) @[package.scala 19:71] + node _T_3890 = bits(_T_3889, 7, 0) @[package.scala 19:76] + node _T_3891 = not(_T_3890) @[package.scala 19:40] + node _T_3892 = and(io.in[1].c.bits.address, _T_3891) @[Edges.scala 17:16] + node _T_3894 = eq(_T_3892, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_3896 = xor(io.in[1].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3897 = cvt(_T_3896) @[Parameters.scala 117:49] + node _T_3899 = and(_T_3897, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3900 = asSInt(_T_3899) @[Parameters.scala 117:52] + node _T_3902 = eq(_T_3900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3904 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3905 = cvt(_T_3904) @[Parameters.scala 117:49] + node _T_3907 = and(_T_3905, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3908 = asSInt(_T_3907) @[Parameters.scala 117:52] + node _T_3910 = eq(_T_3908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3912 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3913 = cvt(_T_3912) @[Parameters.scala 117:49] + node _T_3915 = and(_T_3913, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3916 = asSInt(_T_3915) @[Parameters.scala 117:52] + node _T_3918 = eq(_T_3916, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3920 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3921 = cvt(_T_3920) @[Parameters.scala 117:49] + node _T_3923 = and(_T_3921, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3924 = asSInt(_T_3923) @[Parameters.scala 117:52] + node _T_3926 = eq(_T_3924, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3928 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3929 = cvt(_T_3928) @[Parameters.scala 117:49] + node _T_3931 = and(_T_3929, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3932 = asSInt(_T_3931) @[Parameters.scala 117:52] + node _T_3934 = eq(_T_3932, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3936 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3937 = cvt(_T_3936) @[Parameters.scala 117:49] + node _T_3939 = and(_T_3937, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3940 = asSInt(_T_3939) @[Parameters.scala 117:52] + node _T_3942 = eq(_T_3940, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3944 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3945 = cvt(_T_3944) @[Parameters.scala 117:49] + node _T_3947 = and(_T_3945, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3948 = asSInt(_T_3947) @[Parameters.scala 117:52] + node _T_3950 = eq(_T_3948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3953 : UInt<1>[7] @[Parameters.scala 110:36] + _T_3953 is invalid @[Parameters.scala 110:36] + _T_3953[0] <= _T_3902 @[Parameters.scala 110:36] + _T_3953[1] <= _T_3910 @[Parameters.scala 110:36] + _T_3953[2] <= _T_3918 @[Parameters.scala 110:36] + _T_3953[3] <= _T_3926 @[Parameters.scala 110:36] + _T_3953[4] <= _T_3934 @[Parameters.scala 110:36] + _T_3953[5] <= _T_3942 @[Parameters.scala 110:36] + _T_3953[6] <= _T_3950 @[Parameters.scala 110:36] + node _T_3963 = or(_T_3953[0], _T_3953[1]) @[Parameters.scala 119:64] + node _T_3964 = or(_T_3963, _T_3953[2]) @[Parameters.scala 119:64] + node _T_3965 = or(_T_3964, _T_3953[3]) @[Parameters.scala 119:64] + node _T_3966 = or(_T_3965, _T_3953[4]) @[Parameters.scala 119:64] + node _T_3967 = or(_T_3966, _T_3953[5]) @[Parameters.scala 119:64] + node _T_3968 = or(_T_3967, _T_3953[6]) @[Parameters.scala 119:64] + node _T_3970 = eq(io.in[1].c.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_3970 : @[RocketTiles.scala 50:21] + node _T_3971 = or(_T_3968, reset) @[RocketTiles.scala 50:21] + node _T_3973 = eq(_T_3971, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3973 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3974 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_3976 = eq(_T_3974, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3976 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3978 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_3979 = or(_T_3978, reset) @[RocketTiles.scala 50:21] + node _T_3981 = eq(_T_3979, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3981 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3982 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_3984 = eq(_T_3982, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3984 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3986 = leq(io.in[1].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_3987 = or(_T_3986, reset) @[RocketTiles.scala 50:21] + node _T_3989 = eq(_T_3987, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3989 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3991 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_3992 = or(_T_3991, reset) @[RocketTiles.scala 50:21] + node _T_3994 = eq(_T_3992, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3994 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_3996 = eq(io.in[1].c.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_3996 : @[RocketTiles.scala 50:21] + node _T_3997 = or(_T_3968, reset) @[RocketTiles.scala 50:21] + node _T_3999 = eq(_T_3997, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_3999 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4000 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4002 = eq(_T_4000, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4002 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4004 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4005 = or(_T_4004, reset) @[RocketTiles.scala 50:21] + node _T_4007 = eq(_T_4005, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4007 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4008 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4010 = eq(_T_4008, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4010 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4012 = leq(io.in[1].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_4013 = or(_T_4012, reset) @[RocketTiles.scala 50:21] + node _T_4015 = eq(_T_4013, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4015 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4017 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4018 = or(_T_4017, reset) @[RocketTiles.scala 50:21] + node _T_4020 = eq(_T_4018, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4020 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4022 = eq(io.in[1].c.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_4022 : @[RocketTiles.scala 50:21] + node _T_4025 = leq(UInt<1>("h00"), io.in[1].c.bits.size) @[Parameters.scala 63:32] + node _T_4027 = leq(io.in[1].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_4028 = and(_T_4025, _T_4027) @[Parameters.scala 63:37] + node _T_4029 = or(UInt<1>("h00"), _T_4028) @[Parameters.scala 132:31] + node _T_4031 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_4032 = cvt(_T_4031) @[Parameters.scala 117:49] + node _T_4034 = and(_T_4032, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_4035 = asSInt(_T_4034) @[Parameters.scala 117:52] + node _T_4037 = eq(_T_4035, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4039 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_4040 = cvt(_T_4039) @[Parameters.scala 117:49] + node _T_4042 = and(_T_4040, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_4043 = asSInt(_T_4042) @[Parameters.scala 117:52] + node _T_4045 = eq(_T_4043, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4046 = or(_T_4037, _T_4045) @[Parameters.scala 133:42] + node _T_4047 = and(_T_4029, _T_4046) @[Parameters.scala 132:56] + node _T_4050 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_4052 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4053 = cvt(_T_4052) @[Parameters.scala 117:49] + node _T_4055 = and(_T_4053, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_4056 = asSInt(_T_4055) @[Parameters.scala 117:52] + node _T_4058 = eq(_T_4056, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4060 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4061 = cvt(_T_4060) @[Parameters.scala 117:49] + node _T_4063 = and(_T_4061, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_4064 = asSInt(_T_4063) @[Parameters.scala 117:52] + node _T_4066 = eq(_T_4064, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4068 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_4069 = cvt(_T_4068) @[Parameters.scala 117:49] + node _T_4071 = and(_T_4069, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_4072 = asSInt(_T_4071) @[Parameters.scala 117:52] + node _T_4074 = eq(_T_4072, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4076 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_4077 = cvt(_T_4076) @[Parameters.scala 117:49] + node _T_4079 = and(_T_4077, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_4080 = asSInt(_T_4079) @[Parameters.scala 117:52] + node _T_4082 = eq(_T_4080, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4083 = or(_T_4058, _T_4066) @[Parameters.scala 133:42] + node _T_4084 = or(_T_4083, _T_4074) @[Parameters.scala 133:42] + node _T_4085 = or(_T_4084, _T_4082) @[Parameters.scala 133:42] + node _T_4086 = and(_T_4050, _T_4085) @[Parameters.scala 132:56] + node _T_4088 = or(UInt<1>("h00"), _T_4047) @[Parameters.scala 134:30] + node _T_4089 = or(_T_4088, _T_4086) @[Parameters.scala 134:30] + node _T_4090 = or(_T_4089, reset) @[RocketTiles.scala 50:21] + node _T_4092 = eq(_T_4090, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4092 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4093 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4095 = eq(_T_4093, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4095 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4097 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4098 = or(_T_4097, reset) @[RocketTiles.scala 50:21] + node _T_4100 = eq(_T_4098, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4100 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4101 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4103 = eq(_T_4101, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4103 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4105 = leq(io.in[1].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_4106 = or(_T_4105, reset) @[RocketTiles.scala 50:21] + node _T_4108 = eq(_T_4106, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4108 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4110 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4111 = or(_T_4110, reset) @[RocketTiles.scala 50:21] + node _T_4113 = eq(_T_4111, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4113 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4115 = eq(io.in[1].c.bits.opcode, UInt<3>("h07")) @[RocketTiles.scala 50:21] + when _T_4115 : @[RocketTiles.scala 50:21] + node _T_4118 = leq(UInt<1>("h00"), io.in[1].c.bits.size) @[Parameters.scala 63:32] + node _T_4120 = leq(io.in[1].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_4121 = and(_T_4118, _T_4120) @[Parameters.scala 63:37] + node _T_4122 = or(UInt<1>("h00"), _T_4121) @[Parameters.scala 132:31] + node _T_4124 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_4125 = cvt(_T_4124) @[Parameters.scala 117:49] + node _T_4127 = and(_T_4125, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_4128 = asSInt(_T_4127) @[Parameters.scala 117:52] + node _T_4130 = eq(_T_4128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4132 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_4133 = cvt(_T_4132) @[Parameters.scala 117:49] + node _T_4135 = and(_T_4133, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_4136 = asSInt(_T_4135) @[Parameters.scala 117:52] + node _T_4138 = eq(_T_4136, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4139 = or(_T_4130, _T_4138) @[Parameters.scala 133:42] + node _T_4140 = and(_T_4122, _T_4139) @[Parameters.scala 132:56] + node _T_4143 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_4145 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4146 = cvt(_T_4145) @[Parameters.scala 117:49] + node _T_4148 = and(_T_4146, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_4149 = asSInt(_T_4148) @[Parameters.scala 117:52] + node _T_4151 = eq(_T_4149, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4153 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4154 = cvt(_T_4153) @[Parameters.scala 117:49] + node _T_4156 = and(_T_4154, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_4157 = asSInt(_T_4156) @[Parameters.scala 117:52] + node _T_4159 = eq(_T_4157, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4161 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_4162 = cvt(_T_4161) @[Parameters.scala 117:49] + node _T_4164 = and(_T_4162, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_4165 = asSInt(_T_4164) @[Parameters.scala 117:52] + node _T_4167 = eq(_T_4165, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4169 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_4170 = cvt(_T_4169) @[Parameters.scala 117:49] + node _T_4172 = and(_T_4170, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_4173 = asSInt(_T_4172) @[Parameters.scala 117:52] + node _T_4175 = eq(_T_4173, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4176 = or(_T_4151, _T_4159) @[Parameters.scala 133:42] + node _T_4177 = or(_T_4176, _T_4167) @[Parameters.scala 133:42] + node _T_4178 = or(_T_4177, _T_4175) @[Parameters.scala 133:42] + node _T_4179 = and(_T_4143, _T_4178) @[Parameters.scala 132:56] + node _T_4181 = or(UInt<1>("h00"), _T_4140) @[Parameters.scala 134:30] + node _T_4182 = or(_T_4181, _T_4179) @[Parameters.scala 134:30] + node _T_4183 = or(_T_4182, reset) @[RocketTiles.scala 50:21] + node _T_4185 = eq(_T_4183, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4185 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketTiles.scala:50:21)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4186 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4188 = eq(_T_4186, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4188 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4190 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4191 = or(_T_4190, reset) @[RocketTiles.scala 50:21] + node _T_4193 = eq(_T_4191, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4193 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4194 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4196 = eq(_T_4194, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4196 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4198 = leq(io.in[1].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_4199 = or(_T_4198, reset) @[RocketTiles.scala 50:21] + node _T_4201 = eq(_T_4199, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4201 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4203 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4204 = or(_T_4203, reset) @[RocketTiles.scala 50:21] + node _T_4206 = eq(_T_4204, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4206 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4208 = eq(io.in[1].c.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4208 : @[RocketTiles.scala 50:21] + node _T_4209 = or(_T_3968, reset) @[RocketTiles.scala 50:21] + node _T_4211 = eq(_T_4209, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4211 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4212 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4214 = eq(_T_4212, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4214 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4215 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4217 = eq(_T_4215, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4217 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4219 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4220 = or(_T_4219, reset) @[RocketTiles.scala 50:21] + node _T_4222 = eq(_T_4220, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4222 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4224 = eq(io.in[1].c.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_4224 : @[RocketTiles.scala 50:21] + node _T_4225 = or(_T_3968, reset) @[RocketTiles.scala 50:21] + node _T_4227 = eq(_T_4225, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4227 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4228 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4230 = eq(_T_4228, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4230 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4231 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4233 = eq(_T_4231, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4233 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4235 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4236 = or(_T_4235, reset) @[RocketTiles.scala 50:21] + node _T_4238 = eq(_T_4236, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4238 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4240 = eq(io.in[1].c.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_4240 : @[RocketTiles.scala 50:21] + node _T_4241 = or(_T_3968, reset) @[RocketTiles.scala 50:21] + node _T_4243 = eq(_T_4241, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4243 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketTiles.scala:50:21)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4244 = or(_T_3883[0], reset) @[RocketTiles.scala 50:21] + node _T_4246 = eq(_T_4244, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4246 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4247 = or(_T_3894, reset) @[RocketTiles.scala 50:21] + node _T_4249 = eq(_T_4247, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4249 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4251 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4252 = or(_T_4251, reset) @[RocketTiles.scala 50:21] + node _T_4254 = eq(_T_4252, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4254 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4256 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4257 = or(_T_4256, reset) @[RocketTiles.scala 50:21] + node _T_4259 = eq(_T_4257, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4259 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[1].d.valid : @[RocketTiles.scala 50:21] + node _T_4261 = leq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_4262 = or(_T_4261, reset) @[RocketTiles.scala 50:21] + node _T_4264 = eq(_T_4262, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4264 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketTiles.scala:50:21)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4266 = eq(UInt<1>("h00"), io.in[1].d.bits.source) @[Parameters.scala 35:39] + wire _T_4269 : UInt<1>[1] @[Parameters.scala 228:27] + _T_4269 is invalid @[Parameters.scala 228:27] + _T_4269[0] <= _T_4266 @[Parameters.scala 228:27] + node _T_4274 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4275 = dshl(_T_4274, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4276 = bits(_T_4275, 7, 0) @[package.scala 19:76] + node _T_4277 = not(_T_4276) @[package.scala 19:40] + node _T_4278 = and(io.in[1].d.bits.addr_lo, _T_4277) @[Edges.scala 17:16] + node _T_4280 = eq(_T_4278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_4282 = lt(io.in[1].d.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 50:21] + node _T_4284 = eq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + when _T_4284 : @[RocketTiles.scala 50:21] + node _T_4285 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4287 = eq(_T_4285, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4287 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4288 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4290 = eq(_T_4288, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4290 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4291 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4293 = eq(_T_4291, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4293 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4295 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4296 = or(_T_4295, reset) @[RocketTiles.scala 50:21] + node _T_4298 = eq(_T_4296, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4298 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4300 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4301 = or(_T_4300, reset) @[RocketTiles.scala 50:21] + node _T_4303 = eq(_T_4301, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4303 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4305 = eq(io.in[1].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4306 = or(_T_4305, reset) @[RocketTiles.scala 50:21] + node _T_4308 = eq(_T_4306, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4308 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4310 = eq(io.in[1].d.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 50:21] + when _T_4310 : @[RocketTiles.scala 50:21] + node _T_4311 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4313 = eq(_T_4311, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4313 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4314 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4316 = eq(_T_4314, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4316 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4317 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4319 = eq(_T_4317, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4319 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4321 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4322 = or(_T_4321, reset) @[RocketTiles.scala 50:21] + node _T_4324 = eq(_T_4322, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4324 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4326 = leq(io.in[1].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_4327 = or(_T_4326, reset) @[RocketTiles.scala 50:21] + node _T_4329 = eq(_T_4327, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4329 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4331 = eq(io.in[1].d.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 50:21] + when _T_4331 : @[RocketTiles.scala 50:21] + node _T_4332 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4334 = eq(_T_4332, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4334 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4335 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4337 = eq(_T_4335, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4337 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4338 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4340 = eq(_T_4338, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4340 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4342 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 50:21] + node _T_4343 = or(_T_4342, reset) @[RocketTiles.scala 50:21] + node _T_4345 = eq(_T_4343, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4345 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketTiles.scala:50:21)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4347 = leq(io.in[1].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_4348 = or(_T_4347, reset) @[RocketTiles.scala 50:21] + node _T_4350 = eq(_T_4348, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4350 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4352 = eq(io.in[1].d.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4352 : @[RocketTiles.scala 50:21] + node _T_4353 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4355 = eq(_T_4353, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4355 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4356 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4358 = eq(_T_4356, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4358 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4359 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4361 = eq(_T_4359, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4361 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4363 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4364 = or(_T_4363, reset) @[RocketTiles.scala 50:21] + node _T_4366 = eq(_T_4364, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4366 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4368 = eq(io.in[1].d.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 50:21] + when _T_4368 : @[RocketTiles.scala 50:21] + node _T_4369 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4371 = eq(_T_4369, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4371 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4372 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4374 = eq(_T_4372, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4374 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4375 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4377 = eq(_T_4375, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4377 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4379 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4380 = or(_T_4379, reset) @[RocketTiles.scala 50:21] + node _T_4382 = eq(_T_4380, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4382 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4384 = eq(io.in[1].d.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 50:21] + when _T_4384 : @[RocketTiles.scala 50:21] + node _T_4385 = or(_T_4269[0], reset) @[RocketTiles.scala 50:21] + node _T_4387 = eq(_T_4385, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4387 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4388 = or(_T_4280, reset) @[RocketTiles.scala 50:21] + node _T_4390 = eq(_T_4388, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4390 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketTiles.scala:50:21)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4391 = or(_T_4282, reset) @[RocketTiles.scala 50:21] + node _T_4393 = eq(_T_4391, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4393 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4395 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4396 = or(_T_4395, reset) @[RocketTiles.scala 50:21] + node _T_4398 = eq(_T_4396, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4398 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketTiles.scala:50:21)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4400 = eq(io.in[1].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4401 = or(_T_4400, reset) @[RocketTiles.scala 50:21] + node _T_4403 = eq(_T_4401, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4403 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketTiles.scala:50:21)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + when io.in[1].e.valid : @[RocketTiles.scala 50:21] + node _T_4405 = lt(io.in[1].e.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 50:21] + node _T_4406 = or(_T_4405, reset) @[RocketTiles.scala 50:21] + node _T_4408 = eq(_T_4406, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4408 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4409 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4411 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4412 = dshl(_T_4411, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_4413 = bits(_T_4412, 7, 0) @[package.scala 19:76] + node _T_4414 = not(_T_4413) @[package.scala 19:40] + node _T_4415 = shr(_T_4414, 3) @[Edges.scala 198:59] + node _T_4416 = bits(io.in[1].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4418 = eq(_T_4416, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4420 = mux(_T_4418, _T_4415, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4422 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4424 = sub(_T_4422, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4425 = asUInt(_T_4424) @[Edges.scala 208:28] + node _T_4426 = tail(_T_4425, 1) @[Edges.scala 208:28] + node _T_4428 = eq(_T_4422, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4430 = eq(_T_4422, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4432 = eq(_T_4420, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4433 = or(_T_4430, _T_4432) @[Edges.scala 210:37] + node _T_4434 = and(_T_4433, _T_4409) @[Edges.scala 211:22] + node _T_4435 = not(_T_4426) @[Edges.scala 212:27] + node _T_4436 = and(_T_4420, _T_4435) @[Edges.scala 212:25] + when _T_4409 : @[Edges.scala 213:17] + node _T_4437 = mux(_T_4428, _T_4420, _T_4426) @[Edges.scala 214:21] + _T_4422 <= _T_4437 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4439 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4441 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4443 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4445 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4447 : UInt, clock @[RocketTiles.scala 50:21] + node _T_4449 = eq(_T_4428, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4450 = and(io.in[1].a.valid, _T_4449) @[RocketTiles.scala 50:21] + when _T_4450 : @[RocketTiles.scala 50:21] + node _T_4451 = eq(io.in[1].a.bits.opcode, _T_4439) @[RocketTiles.scala 50:21] + node _T_4452 = or(_T_4451, reset) @[RocketTiles.scala 50:21] + node _T_4454 = eq(_T_4452, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4454 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4455 = eq(io.in[1].a.bits.param, _T_4441) @[RocketTiles.scala 50:21] + node _T_4456 = or(_T_4455, reset) @[RocketTiles.scala 50:21] + node _T_4458 = eq(_T_4456, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4458 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4459 = eq(io.in[1].a.bits.size, _T_4443) @[RocketTiles.scala 50:21] + node _T_4460 = or(_T_4459, reset) @[RocketTiles.scala 50:21] + node _T_4462 = eq(_T_4460, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4462 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4463 = eq(io.in[1].a.bits.source, _T_4445) @[RocketTiles.scala 50:21] + node _T_4464 = or(_T_4463, reset) @[RocketTiles.scala 50:21] + node _T_4466 = eq(_T_4464, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4466 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4467 = eq(io.in[1].a.bits.address, _T_4447) @[RocketTiles.scala 50:21] + node _T_4468 = or(_T_4467, reset) @[RocketTiles.scala 50:21] + node _T_4470 = eq(_T_4468, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4470 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4471 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4472 = and(_T_4471, _T_4428) @[RocketTiles.scala 50:21] + when _T_4472 : @[RocketTiles.scala 50:21] + _T_4439 <= io.in[1].a.bits.opcode @[RocketTiles.scala 50:21] + _T_4441 <= io.in[1].a.bits.param @[RocketTiles.scala 50:21] + _T_4443 <= io.in[1].a.bits.size @[RocketTiles.scala 50:21] + _T_4445 <= io.in[1].a.bits.source @[RocketTiles.scala 50:21] + _T_4447 <= io.in[1].a.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4473 = and(io.in[1].b.ready, io.in[1].b.valid) @[Bundles.scala 207:36] + node _T_4475 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4476 = dshl(_T_4475, io.in[1].b.bits.size) @[package.scala 19:71] + node _T_4477 = bits(_T_4476, 7, 0) @[package.scala 19:76] + node _T_4478 = not(_T_4477) @[package.scala 19:40] + node _T_4479 = shr(_T_4478, 3) @[Edges.scala 198:59] + node _T_4480 = bits(io.in[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4482 = eq(_T_4480, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4485 = mux(UInt<1>("h00"), _T_4479, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4487 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4489 = sub(_T_4487, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4490 = asUInt(_T_4489) @[Edges.scala 208:28] + node _T_4491 = tail(_T_4490, 1) @[Edges.scala 208:28] + node _T_4493 = eq(_T_4487, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4495 = eq(_T_4487, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4497 = eq(_T_4485, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4498 = or(_T_4495, _T_4497) @[Edges.scala 210:37] + node _T_4499 = and(_T_4498, _T_4473) @[Edges.scala 211:22] + node _T_4500 = not(_T_4491) @[Edges.scala 212:27] + node _T_4501 = and(_T_4485, _T_4500) @[Edges.scala 212:25] + when _T_4473 : @[Edges.scala 213:17] + node _T_4502 = mux(_T_4493, _T_4485, _T_4491) @[Edges.scala 214:21] + _T_4487 <= _T_4502 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4504 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4506 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4508 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4510 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4512 : UInt, clock @[RocketTiles.scala 50:21] + node _T_4514 = eq(_T_4493, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4515 = and(io.in[1].b.valid, _T_4514) @[RocketTiles.scala 50:21] + when _T_4515 : @[RocketTiles.scala 50:21] + node _T_4516 = eq(io.in[1].b.bits.opcode, _T_4504) @[RocketTiles.scala 50:21] + node _T_4517 = or(_T_4516, reset) @[RocketTiles.scala 50:21] + node _T_4519 = eq(_T_4517, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4519 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4520 = eq(io.in[1].b.bits.param, _T_4506) @[RocketTiles.scala 50:21] + node _T_4521 = or(_T_4520, reset) @[RocketTiles.scala 50:21] + node _T_4523 = eq(_T_4521, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4523 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4524 = eq(io.in[1].b.bits.size, _T_4508) @[RocketTiles.scala 50:21] + node _T_4525 = or(_T_4524, reset) @[RocketTiles.scala 50:21] + node _T_4527 = eq(_T_4525, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4527 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4528 = eq(io.in[1].b.bits.source, _T_4510) @[RocketTiles.scala 50:21] + node _T_4529 = or(_T_4528, reset) @[RocketTiles.scala 50:21] + node _T_4531 = eq(_T_4529, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4531 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4532 = eq(io.in[1].b.bits.address, _T_4512) @[RocketTiles.scala 50:21] + node _T_4533 = or(_T_4532, reset) @[RocketTiles.scala 50:21] + node _T_4535 = eq(_T_4533, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4535 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4536 = and(io.in[1].b.ready, io.in[1].b.valid) @[Bundles.scala 207:36] + node _T_4537 = and(_T_4536, _T_4493) @[RocketTiles.scala 50:21] + when _T_4537 : @[RocketTiles.scala 50:21] + _T_4504 <= io.in[1].b.bits.opcode @[RocketTiles.scala 50:21] + _T_4506 <= io.in[1].b.bits.param @[RocketTiles.scala 50:21] + _T_4508 <= io.in[1].b.bits.size @[RocketTiles.scala 50:21] + _T_4510 <= io.in[1].b.bits.source @[RocketTiles.scala 50:21] + _T_4512 <= io.in[1].b.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4538 = and(io.in[1].c.ready, io.in[1].c.valid) @[Bundles.scala 207:36] + node _T_4540 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4541 = dshl(_T_4540, io.in[1].c.bits.size) @[package.scala 19:71] + node _T_4542 = bits(_T_4541, 7, 0) @[package.scala 19:76] + node _T_4543 = not(_T_4542) @[package.scala 19:40] + node _T_4544 = shr(_T_4543, 3) @[Edges.scala 198:59] + node _T_4545 = bits(io.in[1].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4548 = mux(UInt<1>("h00"), _T_4544, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4550 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4552 = sub(_T_4550, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4553 = asUInt(_T_4552) @[Edges.scala 208:28] + node _T_4554 = tail(_T_4553, 1) @[Edges.scala 208:28] + node _T_4556 = eq(_T_4550, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4558 = eq(_T_4550, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4560 = eq(_T_4548, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4561 = or(_T_4558, _T_4560) @[Edges.scala 210:37] + node _T_4562 = and(_T_4561, _T_4538) @[Edges.scala 211:22] + node _T_4563 = not(_T_4554) @[Edges.scala 212:27] + node _T_4564 = and(_T_4548, _T_4563) @[Edges.scala 212:25] + when _T_4538 : @[Edges.scala 213:17] + node _T_4565 = mux(_T_4556, _T_4548, _T_4554) @[Edges.scala 214:21] + _T_4550 <= _T_4565 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4567 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4569 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4571 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4573 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4575 : UInt, clock @[RocketTiles.scala 50:21] + node _T_4577 = eq(_T_4556, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4578 = and(io.in[1].c.valid, _T_4577) @[RocketTiles.scala 50:21] + when _T_4578 : @[RocketTiles.scala 50:21] + node _T_4579 = eq(io.in[1].c.bits.opcode, _T_4567) @[RocketTiles.scala 50:21] + node _T_4580 = or(_T_4579, reset) @[RocketTiles.scala 50:21] + node _T_4582 = eq(_T_4580, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4582 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4583 = eq(io.in[1].c.bits.param, _T_4569) @[RocketTiles.scala 50:21] + node _T_4584 = or(_T_4583, reset) @[RocketTiles.scala 50:21] + node _T_4586 = eq(_T_4584, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4586 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4587 = eq(io.in[1].c.bits.size, _T_4571) @[RocketTiles.scala 50:21] + node _T_4588 = or(_T_4587, reset) @[RocketTiles.scala 50:21] + node _T_4590 = eq(_T_4588, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4590 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4591 = eq(io.in[1].c.bits.source, _T_4573) @[RocketTiles.scala 50:21] + node _T_4592 = or(_T_4591, reset) @[RocketTiles.scala 50:21] + node _T_4594 = eq(_T_4592, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4594 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4595 = eq(io.in[1].c.bits.address, _T_4575) @[RocketTiles.scala 50:21] + node _T_4596 = or(_T_4595, reset) @[RocketTiles.scala 50:21] + node _T_4598 = eq(_T_4596, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4598 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4599 = and(io.in[1].c.ready, io.in[1].c.valid) @[Bundles.scala 207:36] + node _T_4600 = and(_T_4599, _T_4556) @[RocketTiles.scala 50:21] + when _T_4600 : @[RocketTiles.scala 50:21] + _T_4567 <= io.in[1].c.bits.opcode @[RocketTiles.scala 50:21] + _T_4569 <= io.in[1].c.bits.param @[RocketTiles.scala 50:21] + _T_4571 <= io.in[1].c.bits.size @[RocketTiles.scala 50:21] + _T_4573 <= io.in[1].c.bits.source @[RocketTiles.scala 50:21] + _T_4575 <= io.in[1].c.bits.address @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4601 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4603 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4604 = dshl(_T_4603, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4605 = bits(_T_4604, 7, 0) @[package.scala 19:76] + node _T_4606 = not(_T_4605) @[package.scala 19:40] + node _T_4607 = shr(_T_4606, 3) @[Edges.scala 198:59] + node _T_4608 = bits(io.in[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4610 = mux(_T_4608, _T_4607, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4612 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4614 = sub(_T_4612, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4615 = asUInt(_T_4614) @[Edges.scala 208:28] + node _T_4616 = tail(_T_4615, 1) @[Edges.scala 208:28] + node _T_4618 = eq(_T_4612, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4620 = eq(_T_4612, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4622 = eq(_T_4610, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4623 = or(_T_4620, _T_4622) @[Edges.scala 210:37] + node _T_4624 = and(_T_4623, _T_4601) @[Edges.scala 211:22] + node _T_4625 = not(_T_4616) @[Edges.scala 212:27] + node _T_4626 = and(_T_4610, _T_4625) @[Edges.scala 212:25] + when _T_4601 : @[Edges.scala 213:17] + node _T_4627 = mux(_T_4618, _T_4610, _T_4616) @[Edges.scala 214:21] + _T_4612 <= _T_4627 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4629 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4631 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4633 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4635 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4637 : UInt, clock @[RocketTiles.scala 50:21] + reg _T_4639 : UInt, clock @[RocketTiles.scala 50:21] + node _T_4641 = eq(_T_4618, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4642 = and(io.in[1].d.valid, _T_4641) @[RocketTiles.scala 50:21] + when _T_4642 : @[RocketTiles.scala 50:21] + node _T_4643 = eq(io.in[1].d.bits.opcode, _T_4629) @[RocketTiles.scala 50:21] + node _T_4644 = or(_T_4643, reset) @[RocketTiles.scala 50:21] + node _T_4646 = eq(_T_4644, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4646 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4647 = eq(io.in[1].d.bits.param, _T_4631) @[RocketTiles.scala 50:21] + node _T_4648 = or(_T_4647, reset) @[RocketTiles.scala 50:21] + node _T_4650 = eq(_T_4648, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4650 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4651 = eq(io.in[1].d.bits.size, _T_4633) @[RocketTiles.scala 50:21] + node _T_4652 = or(_T_4651, reset) @[RocketTiles.scala 50:21] + node _T_4654 = eq(_T_4652, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4654 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4655 = eq(io.in[1].d.bits.source, _T_4635) @[RocketTiles.scala 50:21] + node _T_4656 = or(_T_4655, reset) @[RocketTiles.scala 50:21] + node _T_4658 = eq(_T_4656, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4658 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4659 = eq(io.in[1].d.bits.sink, _T_4637) @[RocketTiles.scala 50:21] + node _T_4660 = or(_T_4659, reset) @[RocketTiles.scala 50:21] + node _T_4662 = eq(_T_4660, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4662 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4663 = eq(io.in[1].d.bits.addr_lo, _T_4639) @[RocketTiles.scala 50:21] + node _T_4664 = or(_T_4663, reset) @[RocketTiles.scala 50:21] + node _T_4666 = eq(_T_4664, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4666 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketTiles.scala:50:21)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4667 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4668 = and(_T_4667, _T_4618) @[RocketTiles.scala 50:21] + when _T_4668 : @[RocketTiles.scala 50:21] + _T_4629 <= io.in[1].d.bits.opcode @[RocketTiles.scala 50:21] + _T_4631 <= io.in[1].d.bits.param @[RocketTiles.scala 50:21] + _T_4633 <= io.in[1].d.bits.size @[RocketTiles.scala 50:21] + _T_4635 <= io.in[1].d.bits.source @[RocketTiles.scala 50:21] + _T_4637 <= io.in[1].d.bits.sink @[RocketTiles.scala 50:21] + _T_4639 <= io.in[1].d.bits.addr_lo @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + reg _T_4670 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_4671 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4673 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4674 = dshl(_T_4673, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_4675 = bits(_T_4674, 7, 0) @[package.scala 19:76] + node _T_4676 = not(_T_4675) @[package.scala 19:40] + node _T_4677 = shr(_T_4676, 3) @[Edges.scala 198:59] + node _T_4678 = bits(io.in[1].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4680 = eq(_T_4678, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4682 = mux(_T_4680, _T_4677, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4684 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4686 = sub(_T_4684, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4687 = asUInt(_T_4686) @[Edges.scala 208:28] + node _T_4688 = tail(_T_4687, 1) @[Edges.scala 208:28] + node _T_4690 = eq(_T_4684, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4692 = eq(_T_4684, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4694 = eq(_T_4682, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4695 = or(_T_4692, _T_4694) @[Edges.scala 210:37] + node _T_4696 = and(_T_4695, _T_4671) @[Edges.scala 211:22] + node _T_4697 = not(_T_4688) @[Edges.scala 212:27] + node _T_4698 = and(_T_4682, _T_4697) @[Edges.scala 212:25] + when _T_4671 : @[Edges.scala 213:17] + node _T_4699 = mux(_T_4690, _T_4682, _T_4688) @[Edges.scala 214:21] + _T_4684 <= _T_4699 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_4700 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4702 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4703 = dshl(_T_4702, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4704 = bits(_T_4703, 7, 0) @[package.scala 19:76] + node _T_4705 = not(_T_4704) @[package.scala 19:40] + node _T_4706 = shr(_T_4705, 3) @[Edges.scala 198:59] + node _T_4707 = bits(io.in[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4709 = mux(_T_4707, _T_4706, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4711 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4713 = sub(_T_4711, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4714 = asUInt(_T_4713) @[Edges.scala 208:28] + node _T_4715 = tail(_T_4714, 1) @[Edges.scala 208:28] + node _T_4717 = eq(_T_4711, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4719 = eq(_T_4711, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4721 = eq(_T_4709, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4722 = or(_T_4719, _T_4721) @[Edges.scala 210:37] + node _T_4723 = and(_T_4722, _T_4700) @[Edges.scala 211:22] + node _T_4724 = not(_T_4715) @[Edges.scala 212:27] + node _T_4725 = and(_T_4709, _T_4724) @[Edges.scala 212:25] + when _T_4700 : @[Edges.scala 213:17] + node _T_4726 = mux(_T_4717, _T_4709, _T_4715) @[Edges.scala 214:21] + _T_4711 <= _T_4726 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_4728 = eq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + node _T_4729 = neq(io.in[1].a.bits.source, io.in[1].d.bits.source) @[RocketTiles.scala 50:21] + node _T_4730 = or(_T_4728, _T_4729) @[RocketTiles.scala 50:21] + node _T_4732 = eq(io.in[1].a.valid, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4733 = or(_T_4730, _T_4732) @[RocketTiles.scala 50:21] + node _T_4735 = eq(io.in[1].d.valid, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4736 = or(_T_4733, _T_4735) @[RocketTiles.scala 50:21] + node _T_4737 = or(_T_4736, reset) @[RocketTiles.scala 50:21] + node _T_4739 = eq(_T_4737, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4739 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at RocketTiles.scala:50:21)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + wire _T_4741 : UInt<1> + _T_4741 is invalid + _T_4741 <= UInt<1>("h00") + node _T_4742 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + when _T_4742 : @[RocketTiles.scala 50:21] + when _T_4695 : @[RocketTiles.scala 50:21] + node _T_4744 = dshl(UInt<1>("h01"), io.in[1].a.bits.source) @[OneHot.scala 47:11] + _T_4741 <= _T_4744 @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4745 = dshr(_T_4670, io.in[1].a.bits.source) @[RocketTiles.scala 50:21] + node _T_4746 = bits(_T_4745, 0, 0) @[RocketTiles.scala 50:21] + node _T_4748 = eq(_T_4746, UInt<1>("h00")) @[RocketTiles.scala 50:21] + node _T_4749 = or(_T_4748, reset) @[RocketTiles.scala 50:21] + node _T_4751 = eq(_T_4749, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4751 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketTiles.scala:50:21)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + wire _T_4753 : UInt<1> + _T_4753 is invalid + _T_4753 <= UInt<1>("h00") + node _T_4754 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4756 = neq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 50:21] + node _T_4757 = and(_T_4754, _T_4756) @[RocketTiles.scala 50:21] + when _T_4757 : @[RocketTiles.scala 50:21] + when _T_4722 : @[RocketTiles.scala 50:21] + node _T_4759 = dshl(UInt<1>("h01"), io.in[1].d.bits.source) @[OneHot.scala 47:11] + _T_4753 <= _T_4759 @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4760 = or(_T_4741, _T_4670) @[RocketTiles.scala 50:21] + node _T_4761 = dshr(_T_4760, io.in[1].d.bits.source) @[RocketTiles.scala 50:21] + node _T_4762 = bits(_T_4761, 0, 0) @[RocketTiles.scala 50:21] + node _T_4763 = or(_T_4762, reset) @[RocketTiles.scala 50:21] + node _T_4765 = eq(_T_4763, UInt<1>("h00")) @[RocketTiles.scala 50:21] + when _T_4765 : @[RocketTiles.scala 50:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketTiles.scala:50:21)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketTiles.scala 50:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + skip @[RocketTiles.scala 50:21] + node _T_4766 = or(_T_4670, _T_4741) @[RocketTiles.scala 50:21] + node _T_4767 = not(_T_4753) @[RocketTiles.scala 50:21] + node _T_4768 = and(_T_4766, _T_4767) @[RocketTiles.scala 50:21] + _T_4670 <= _T_4768 @[RocketTiles.scala 50:21] - module NastiRecursiveInterconnect_56 : - input clk : Clock + module TLMonitor_35 : + input clock : Clock input reset : UInt<1> - output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[2]} io is invalid - inst xbar of NastiCrossbar_57 - xbar.io is invalid - xbar.clk <= clk - xbar.reset <= reset - xbar.io.masters <= io.masters - io.slaves[0] <- xbar.io.slaves[0] - io.slaves[1] <- xbar.io.slaves[1] - io.slaves[2] <- xbar.io.slaves[2] + io is invalid + when io.in[0].a.valid : @[RocketTiles.scala 51:21] + node _T_861 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_862 = or(_T_861, reset) @[RocketTiles.scala 51:21] + node _T_864 = eq(_T_862, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_864 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_866 = eq(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_869 : UInt<1>[1] @[Parameters.scala 228:27] + _T_869 is invalid @[Parameters.scala 228:27] + _T_869[0] <= _T_866 @[Parameters.scala 228:27] + node _T_874 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_875 = dshl(_T_874, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_876 = bits(_T_875, 7, 0) @[package.scala 19:76] + node _T_877 = not(_T_876) @[package.scala 19:40] + node _T_878 = and(io.in[0].a.bits.address, _T_877) @[Edges.scala 17:16] + node _T_880 = eq(_T_878, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_882 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_883 = dshl(UInt<1>("h01"), _T_882) @[OneHot.scala 49:12] + node _T_884 = bits(_T_883, 2, 0) @[OneHot.scala 49:37] + node _T_886 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_888 = bits(_T_884, 2, 2) @[package.scala 44:26] + node _T_889 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_891 = eq(_T_889, UInt<1>("h00")) @[package.scala 46:20] + node _T_892 = and(UInt<1>("h01"), _T_891) @[package.scala 49:27] + node _T_893 = and(_T_888, _T_892) @[package.scala 50:38] + node _T_894 = or(_T_886, _T_893) @[package.scala 50:29] + node _T_895 = and(UInt<1>("h01"), _T_889) @[package.scala 49:27] + node _T_896 = and(_T_888, _T_895) @[package.scala 50:38] + node _T_897 = or(_T_886, _T_896) @[package.scala 50:29] + node _T_898 = bits(_T_884, 1, 1) @[package.scala 44:26] + node _T_899 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[package.scala 46:20] + node _T_902 = and(_T_892, _T_901) @[package.scala 49:27] + node _T_903 = and(_T_898, _T_902) @[package.scala 50:38] + node _T_904 = or(_T_894, _T_903) @[package.scala 50:29] + node _T_905 = and(_T_892, _T_899) @[package.scala 49:27] + node _T_906 = and(_T_898, _T_905) @[package.scala 50:38] + node _T_907 = or(_T_894, _T_906) @[package.scala 50:29] + node _T_908 = and(_T_895, _T_901) @[package.scala 49:27] + node _T_909 = and(_T_898, _T_908) @[package.scala 50:38] + node _T_910 = or(_T_897, _T_909) @[package.scala 50:29] + node _T_911 = and(_T_895, _T_899) @[package.scala 49:27] + node _T_912 = and(_T_898, _T_911) @[package.scala 50:38] + node _T_913 = or(_T_897, _T_912) @[package.scala 50:29] + node _T_914 = bits(_T_884, 0, 0) @[package.scala 44:26] + node _T_915 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_917 = eq(_T_915, UInt<1>("h00")) @[package.scala 46:20] + node _T_918 = and(_T_902, _T_917) @[package.scala 49:27] + node _T_919 = and(_T_914, _T_918) @[package.scala 50:38] + node _T_920 = or(_T_904, _T_919) @[package.scala 50:29] + node _T_921 = and(_T_902, _T_915) @[package.scala 49:27] + node _T_922 = and(_T_914, _T_921) @[package.scala 50:38] + node _T_923 = or(_T_904, _T_922) @[package.scala 50:29] + node _T_924 = and(_T_905, _T_917) @[package.scala 49:27] + node _T_925 = and(_T_914, _T_924) @[package.scala 50:38] + node _T_926 = or(_T_907, _T_925) @[package.scala 50:29] + node _T_927 = and(_T_905, _T_915) @[package.scala 49:27] + node _T_928 = and(_T_914, _T_927) @[package.scala 50:38] + node _T_929 = or(_T_907, _T_928) @[package.scala 50:29] + node _T_930 = and(_T_908, _T_917) @[package.scala 49:27] + node _T_931 = and(_T_914, _T_930) @[package.scala 50:38] + node _T_932 = or(_T_910, _T_931) @[package.scala 50:29] + node _T_933 = and(_T_908, _T_915) @[package.scala 49:27] + node _T_934 = and(_T_914, _T_933) @[package.scala 50:38] + node _T_935 = or(_T_910, _T_934) @[package.scala 50:29] + node _T_936 = and(_T_911, _T_917) @[package.scala 49:27] + node _T_937 = and(_T_914, _T_936) @[package.scala 50:38] + node _T_938 = or(_T_913, _T_937) @[package.scala 50:29] + node _T_939 = and(_T_911, _T_915) @[package.scala 49:27] + node _T_940 = and(_T_914, _T_939) @[package.scala 50:38] + node _T_941 = or(_T_913, _T_940) @[package.scala 50:29] + node _T_942 = cat(_T_923, _T_920) @[Cat.scala 30:58] + node _T_943 = cat(_T_929, _T_926) @[Cat.scala 30:58] + node _T_944 = cat(_T_943, _T_942) @[Cat.scala 30:58] + node _T_945 = cat(_T_935, _T_932) @[Cat.scala 30:58] + node _T_946 = cat(_T_941, _T_938) @[Cat.scala 30:58] + node _T_947 = cat(_T_946, _T_945) @[Cat.scala 30:58] + node _T_948 = cat(_T_947, _T_944) @[Cat.scala 30:58] + node _T_950 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_950 : @[RocketTiles.scala 51:21] + node _T_953 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_955 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_956 = and(_T_953, _T_955) @[Parameters.scala 63:37] + node _T_957 = or(UInt<1>("h00"), _T_956) @[Parameters.scala 132:31] + node _T_959 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_960 = cvt(_T_959) @[Parameters.scala 117:49] + node _T_962 = and(_T_960, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_963 = asSInt(_T_962) @[Parameters.scala 117:52] + node _T_965 = eq(_T_963, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_967 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_968 = cvt(_T_967) @[Parameters.scala 117:49] + node _T_970 = and(_T_968, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_971 = asSInt(_T_970) @[Parameters.scala 117:52] + node _T_973 = eq(_T_971, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = or(_T_965, _T_973) @[Parameters.scala 133:42] + node _T_975 = and(_T_957, _T_974) @[Parameters.scala 132:56] + node _T_978 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_980 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_981 = cvt(_T_980) @[Parameters.scala 117:49] + node _T_983 = and(_T_981, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_984 = asSInt(_T_983) @[Parameters.scala 117:52] + node _T_986 = eq(_T_984, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_988 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_989 = cvt(_T_988) @[Parameters.scala 117:49] + node _T_991 = and(_T_989, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_992 = asSInt(_T_991) @[Parameters.scala 117:52] + node _T_994 = eq(_T_992, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_996 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_997 = cvt(_T_996) @[Parameters.scala 117:49] + node _T_999 = and(_T_997, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1000 = asSInt(_T_999) @[Parameters.scala 117:52] + node _T_1002 = eq(_T_1000, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1004 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1005 = cvt(_T_1004) @[Parameters.scala 117:49] + node _T_1007 = and(_T_1005, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1008 = asSInt(_T_1007) @[Parameters.scala 117:52] + node _T_1010 = eq(_T_1008, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1011 = or(_T_986, _T_994) @[Parameters.scala 133:42] + node _T_1012 = or(_T_1011, _T_1002) @[Parameters.scala 133:42] + node _T_1013 = or(_T_1012, _T_1010) @[Parameters.scala 133:42] + node _T_1014 = and(_T_978, _T_1013) @[Parameters.scala 132:56] + node _T_1016 = or(UInt<1>("h00"), _T_975) @[Parameters.scala 134:30] + node _T_1017 = or(_T_1016, _T_1014) @[Parameters.scala 134:30] + node _T_1018 = or(_T_1017, reset) @[RocketTiles.scala 51:21] + node _T_1020 = eq(_T_1018, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1020 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1021 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1023 = eq(_T_1021, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1023 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1025 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_1026 = or(_T_1025, reset) @[RocketTiles.scala 51:21] + node _T_1028 = eq(_T_1026, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1028 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1029 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1031 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1033 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_1034 = or(_T_1033, reset) @[RocketTiles.scala 51:21] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1036 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1037 = not(io.in[0].a.bits.mask) @[RocketTiles.scala 51:21] + node _T_1039 = eq(_T_1037, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1040 = or(_T_1039, reset) @[RocketTiles.scala 51:21] + node _T_1042 = eq(_T_1040, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1042 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1044 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_1044 : @[RocketTiles.scala 51:21] + node _T_1047 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1049 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1050 = and(_T_1047, _T_1049) @[Parameters.scala 63:37] + node _T_1051 = or(UInt<1>("h00"), _T_1050) @[Parameters.scala 132:31] + node _T_1053 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1054 = cvt(_T_1053) @[Parameters.scala 117:49] + node _T_1056 = and(_T_1054, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1057 = asSInt(_T_1056) @[Parameters.scala 117:52] + node _T_1059 = eq(_T_1057, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1061 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1062 = cvt(_T_1061) @[Parameters.scala 117:49] + node _T_1064 = and(_T_1062, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1065 = asSInt(_T_1064) @[Parameters.scala 117:52] + node _T_1067 = eq(_T_1065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1070 = cvt(_T_1069) @[Parameters.scala 117:49] + node _T_1072 = and(_T_1070, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1073 = asSInt(_T_1072) @[Parameters.scala 117:52] + node _T_1075 = eq(_T_1073, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1077 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1078 = cvt(_T_1077) @[Parameters.scala 117:49] + node _T_1080 = and(_T_1078, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1081 = asSInt(_T_1080) @[Parameters.scala 117:52] + node _T_1083 = eq(_T_1081, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1085 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1086 = cvt(_T_1085) @[Parameters.scala 117:49] + node _T_1088 = and(_T_1086, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1089 = asSInt(_T_1088) @[Parameters.scala 117:52] + node _T_1091 = eq(_T_1089, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1092 = or(_T_1059, _T_1067) @[Parameters.scala 133:42] + node _T_1093 = or(_T_1092, _T_1075) @[Parameters.scala 133:42] + node _T_1094 = or(_T_1093, _T_1083) @[Parameters.scala 133:42] + node _T_1095 = or(_T_1094, _T_1091) @[Parameters.scala 133:42] + node _T_1096 = and(_T_1051, _T_1095) @[Parameters.scala 132:56] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1112 = and(_T_1103, _T_1111) @[Parameters.scala 132:56] + node _T_1114 = or(UInt<1>("h00"), _T_1096) @[Parameters.scala 134:30] + node _T_1115 = or(_T_1114, _T_1112) @[Parameters.scala 134:30] + node _T_1116 = or(_T_1115, reset) @[RocketTiles.scala 51:21] + node _T_1118 = eq(_T_1116, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1118 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1119 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1121 = eq(_T_1119, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1121 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1122 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1124 = eq(_T_1122, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1124 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1126 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1127 = or(_T_1126, reset) @[RocketTiles.scala 51:21] + node _T_1129 = eq(_T_1127, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1129 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1130 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 51:21] + node _T_1131 = or(_T_1130, reset) @[RocketTiles.scala 51:21] + node _T_1133 = eq(_T_1131, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1133 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1135 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1135 : @[RocketTiles.scala 51:21] + node _T_1138 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1140 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1141 = and(_T_1138, _T_1140) @[Parameters.scala 63:37] + node _T_1142 = or(UInt<1>("h00"), _T_1141) @[Parameters.scala 132:31] + node _T_1144 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1145 = cvt(_T_1144) @[Parameters.scala 117:49] + node _T_1147 = and(_T_1145, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1148 = asSInt(_T_1147) @[Parameters.scala 117:52] + node _T_1150 = eq(_T_1148, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1152 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1153 = cvt(_T_1152) @[Parameters.scala 117:49] + node _T_1155 = and(_T_1153, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1156 = asSInt(_T_1155) @[Parameters.scala 117:52] + node _T_1158 = eq(_T_1156, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1160 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1161 = cvt(_T_1160) @[Parameters.scala 117:49] + node _T_1163 = and(_T_1161, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1164 = asSInt(_T_1163) @[Parameters.scala 117:52] + node _T_1166 = eq(_T_1164, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1168 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1169 = cvt(_T_1168) @[Parameters.scala 117:49] + node _T_1171 = and(_T_1169, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1172 = asSInt(_T_1171) @[Parameters.scala 117:52] + node _T_1174 = eq(_T_1172, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1176 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1177 = cvt(_T_1176) @[Parameters.scala 117:49] + node _T_1179 = and(_T_1177, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1180 = asSInt(_T_1179) @[Parameters.scala 117:52] + node _T_1182 = eq(_T_1180, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1183 = or(_T_1150, _T_1158) @[Parameters.scala 133:42] + node _T_1184 = or(_T_1183, _T_1166) @[Parameters.scala 133:42] + node _T_1185 = or(_T_1184, _T_1174) @[Parameters.scala 133:42] + node _T_1186 = or(_T_1185, _T_1182) @[Parameters.scala 133:42] + node _T_1187 = and(_T_1142, _T_1186) @[Parameters.scala 132:56] + node _T_1190 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1192 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1193 = and(_T_1190, _T_1192) @[Parameters.scala 63:37] + node _T_1194 = or(UInt<1>("h00"), _T_1193) @[Parameters.scala 132:31] + node _T_1196 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1197 = cvt(_T_1196) @[Parameters.scala 117:49] + node _T_1199 = and(_T_1197, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1200 = asSInt(_T_1199) @[Parameters.scala 117:52] + node _T_1202 = eq(_T_1200, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1203 = and(_T_1194, _T_1202) @[Parameters.scala 132:56] + node _T_1206 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1208 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1209 = cvt(_T_1208) @[Parameters.scala 117:49] + node _T_1211 = and(_T_1209, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1212 = asSInt(_T_1211) @[Parameters.scala 117:52] + node _T_1214 = eq(_T_1212, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1215 = and(_T_1206, _T_1214) @[Parameters.scala 132:56] + node _T_1217 = or(UInt<1>("h00"), _T_1187) @[Parameters.scala 134:30] + node _T_1218 = or(_T_1217, _T_1203) @[Parameters.scala 134:30] + node _T_1219 = or(_T_1218, _T_1215) @[Parameters.scala 134:30] + node _T_1220 = or(_T_1219, reset) @[RocketTiles.scala 51:21] + node _T_1222 = eq(_T_1220, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1222 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1223 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1225 = eq(_T_1223, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1225 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1226 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1228 = eq(_T_1226, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1228 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1230 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1231 = or(_T_1230, reset) @[RocketTiles.scala 51:21] + node _T_1233 = eq(_T_1231, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1233 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1234 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 51:21] + node _T_1235 = or(_T_1234, reset) @[RocketTiles.scala 51:21] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1237 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1239 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_1239 : @[RocketTiles.scala 51:21] + node _T_1242 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1244 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1245 = and(_T_1242, _T_1244) @[Parameters.scala 63:37] + node _T_1246 = or(UInt<1>("h00"), _T_1245) @[Parameters.scala 132:31] + node _T_1248 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1249 = cvt(_T_1248) @[Parameters.scala 117:49] + node _T_1251 = and(_T_1249, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1252 = asSInt(_T_1251) @[Parameters.scala 117:52] + node _T_1254 = eq(_T_1252, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1256 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1257 = cvt(_T_1256) @[Parameters.scala 117:49] + node _T_1259 = and(_T_1257, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1260 = asSInt(_T_1259) @[Parameters.scala 117:52] + node _T_1262 = eq(_T_1260, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1264 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1265 = cvt(_T_1264) @[Parameters.scala 117:49] + node _T_1267 = and(_T_1265, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1268 = asSInt(_T_1267) @[Parameters.scala 117:52] + node _T_1270 = eq(_T_1268, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1272 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1273 = cvt(_T_1272) @[Parameters.scala 117:49] + node _T_1275 = and(_T_1273, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1276 = asSInt(_T_1275) @[Parameters.scala 117:52] + node _T_1278 = eq(_T_1276, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1280 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1281 = cvt(_T_1280) @[Parameters.scala 117:49] + node _T_1283 = and(_T_1281, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1284 = asSInt(_T_1283) @[Parameters.scala 117:52] + node _T_1286 = eq(_T_1284, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1287 = or(_T_1254, _T_1262) @[Parameters.scala 133:42] + node _T_1288 = or(_T_1287, _T_1270) @[Parameters.scala 133:42] + node _T_1289 = or(_T_1288, _T_1278) @[Parameters.scala 133:42] + node _T_1290 = or(_T_1289, _T_1286) @[Parameters.scala 133:42] + node _T_1291 = and(_T_1246, _T_1290) @[Parameters.scala 132:56] + node _T_1294 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1296 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1297 = and(_T_1294, _T_1296) @[Parameters.scala 63:37] + node _T_1298 = or(UInt<1>("h00"), _T_1297) @[Parameters.scala 132:31] + node _T_1300 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1301 = cvt(_T_1300) @[Parameters.scala 117:49] + node _T_1303 = and(_T_1301, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1304 = asSInt(_T_1303) @[Parameters.scala 117:52] + node _T_1306 = eq(_T_1304, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1307 = and(_T_1298, _T_1306) @[Parameters.scala 132:56] + node _T_1310 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1312 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1313 = cvt(_T_1312) @[Parameters.scala 117:49] + node _T_1315 = and(_T_1313, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1316 = asSInt(_T_1315) @[Parameters.scala 117:52] + node _T_1318 = eq(_T_1316, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1319 = and(_T_1310, _T_1318) @[Parameters.scala 132:56] + node _T_1321 = or(UInt<1>("h00"), _T_1291) @[Parameters.scala 134:30] + node _T_1322 = or(_T_1321, _T_1307) @[Parameters.scala 134:30] + node _T_1323 = or(_T_1322, _T_1319) @[Parameters.scala 134:30] + node _T_1324 = or(_T_1323, reset) @[RocketTiles.scala 51:21] + node _T_1326 = eq(_T_1324, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1326 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1327 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1329 = eq(_T_1327, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1329 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1330 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1332 = eq(_T_1330, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1332 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1334 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1335 = or(_T_1334, reset) @[RocketTiles.scala 51:21] + node _T_1337 = eq(_T_1335, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1337 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1338 = not(_T_948) @[RocketTiles.scala 51:21] + node _T_1339 = and(io.in[0].a.bits.mask, _T_1338) @[RocketTiles.scala 51:21] + node _T_1341 = eq(_T_1339, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1342 = or(_T_1341, reset) @[RocketTiles.scala 51:21] + node _T_1344 = eq(_T_1342, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1344 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1346 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_1346 : @[RocketTiles.scala 51:21] + node _T_1349 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1351 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1352 = and(_T_1349, _T_1351) @[Parameters.scala 63:37] + node _T_1353 = or(UInt<1>("h00"), _T_1352) @[Parameters.scala 132:31] + node _T_1355 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1356 = cvt(_T_1355) @[Parameters.scala 117:49] + node _T_1358 = and(_T_1356, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1359 = asSInt(_T_1358) @[Parameters.scala 117:52] + node _T_1361 = eq(_T_1359, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1363 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1364 = cvt(_T_1363) @[Parameters.scala 117:49] + node _T_1366 = and(_T_1364, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1367 = asSInt(_T_1366) @[Parameters.scala 117:52] + node _T_1369 = eq(_T_1367, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1371 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1372 = cvt(_T_1371) @[Parameters.scala 117:49] + node _T_1374 = and(_T_1372, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1375 = asSInt(_T_1374) @[Parameters.scala 117:52] + node _T_1377 = eq(_T_1375, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1378 = or(_T_1361, _T_1369) @[Parameters.scala 133:42] + node _T_1379 = or(_T_1378, _T_1377) @[Parameters.scala 133:42] + node _T_1380 = and(_T_1353, _T_1379) @[Parameters.scala 132:56] + node _T_1383 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1385 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1386 = cvt(_T_1385) @[Parameters.scala 117:49] + node _T_1388 = and(_T_1386, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1389 = asSInt(_T_1388) @[Parameters.scala 117:52] + node _T_1391 = eq(_T_1389, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1393 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1394 = cvt(_T_1393) @[Parameters.scala 117:49] + node _T_1396 = and(_T_1394, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1397 = asSInt(_T_1396) @[Parameters.scala 117:52] + node _T_1399 = eq(_T_1397, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1401 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1402 = cvt(_T_1401) @[Parameters.scala 117:49] + node _T_1404 = and(_T_1402, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1405 = asSInt(_T_1404) @[Parameters.scala 117:52] + node _T_1407 = eq(_T_1405, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1409 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1410 = cvt(_T_1409) @[Parameters.scala 117:49] + node _T_1412 = and(_T_1410, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1413 = asSInt(_T_1412) @[Parameters.scala 117:52] + node _T_1415 = eq(_T_1413, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1416 = or(_T_1391, _T_1399) @[Parameters.scala 133:42] + node _T_1417 = or(_T_1416, _T_1407) @[Parameters.scala 133:42] + node _T_1418 = or(_T_1417, _T_1415) @[Parameters.scala 133:42] + node _T_1419 = and(_T_1383, _T_1418) @[Parameters.scala 132:56] + node _T_1421 = or(UInt<1>("h00"), _T_1380) @[Parameters.scala 134:30] + node _T_1422 = or(_T_1421, _T_1419) @[Parameters.scala 134:30] + node _T_1423 = or(_T_1422, reset) @[RocketTiles.scala 51:21] + node _T_1425 = eq(_T_1423, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1425 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1426 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1428 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1429 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1431 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1433 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1434 = or(_T_1433, reset) @[RocketTiles.scala 51:21] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1436 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1437 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 51:21] + node _T_1438 = or(_T_1437, reset) @[RocketTiles.scala 51:21] + node _T_1440 = eq(_T_1438, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1440 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1442 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 51:21] + when _T_1442 : @[RocketTiles.scala 51:21] + node _T_1445 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1447 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1448 = and(_T_1445, _T_1447) @[Parameters.scala 63:37] + node _T_1449 = or(UInt<1>("h00"), _T_1448) @[Parameters.scala 132:31] + node _T_1451 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1452 = cvt(_T_1451) @[Parameters.scala 117:49] + node _T_1454 = and(_T_1452, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1455 = asSInt(_T_1454) @[Parameters.scala 117:52] + node _T_1457 = eq(_T_1455, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1459 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1460 = cvt(_T_1459) @[Parameters.scala 117:49] + node _T_1462 = and(_T_1460, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1463 = asSInt(_T_1462) @[Parameters.scala 117:52] + node _T_1465 = eq(_T_1463, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1467 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1468 = cvt(_T_1467) @[Parameters.scala 117:49] + node _T_1470 = and(_T_1468, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1471 = asSInt(_T_1470) @[Parameters.scala 117:52] + node _T_1473 = eq(_T_1471, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1474 = or(_T_1457, _T_1465) @[Parameters.scala 133:42] + node _T_1475 = or(_T_1474, _T_1473) @[Parameters.scala 133:42] + node _T_1476 = and(_T_1449, _T_1475) @[Parameters.scala 132:56] + node _T_1479 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1481 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1482 = cvt(_T_1481) @[Parameters.scala 117:49] + node _T_1484 = and(_T_1482, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1485 = asSInt(_T_1484) @[Parameters.scala 117:52] + node _T_1487 = eq(_T_1485, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1489 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1490 = cvt(_T_1489) @[Parameters.scala 117:49] + node _T_1492 = and(_T_1490, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1493 = asSInt(_T_1492) @[Parameters.scala 117:52] + node _T_1495 = eq(_T_1493, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1497 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1498 = cvt(_T_1497) @[Parameters.scala 117:49] + node _T_1500 = and(_T_1498, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1501 = asSInt(_T_1500) @[Parameters.scala 117:52] + node _T_1503 = eq(_T_1501, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1505 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1506 = cvt(_T_1505) @[Parameters.scala 117:49] + node _T_1508 = and(_T_1506, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1509 = asSInt(_T_1508) @[Parameters.scala 117:52] + node _T_1511 = eq(_T_1509, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1512 = or(_T_1487, _T_1495) @[Parameters.scala 133:42] + node _T_1513 = or(_T_1512, _T_1503) @[Parameters.scala 133:42] + node _T_1514 = or(_T_1513, _T_1511) @[Parameters.scala 133:42] + node _T_1515 = and(_T_1479, _T_1514) @[Parameters.scala 132:56] + node _T_1517 = or(UInt<1>("h00"), _T_1476) @[Parameters.scala 134:30] + node _T_1518 = or(_T_1517, _T_1515) @[Parameters.scala 134:30] + node _T_1519 = or(_T_1518, reset) @[RocketTiles.scala 51:21] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1521 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1522 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1524 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1525 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1527 = eq(_T_1525, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1527 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1529 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1530 = or(_T_1529, reset) @[RocketTiles.scala 51:21] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1532 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1533 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 51:21] + node _T_1534 = or(_T_1533, reset) @[RocketTiles.scala 51:21] + node _T_1536 = eq(_T_1534, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1536 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1538 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_1538 : @[RocketTiles.scala 51:21] + node _T_1541 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1543 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1544 = cvt(_T_1543) @[Parameters.scala 117:49] + node _T_1546 = and(_T_1544, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1547 = asSInt(_T_1546) @[Parameters.scala 117:52] + node _T_1549 = eq(_T_1547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1551 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1552 = cvt(_T_1551) @[Parameters.scala 117:49] + node _T_1554 = and(_T_1552, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1555 = asSInt(_T_1554) @[Parameters.scala 117:52] + node _T_1557 = eq(_T_1555, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1559 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1560 = cvt(_T_1559) @[Parameters.scala 117:49] + node _T_1562 = and(_T_1560, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1563 = asSInt(_T_1562) @[Parameters.scala 117:52] + node _T_1565 = eq(_T_1563, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1567 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1568 = cvt(_T_1567) @[Parameters.scala 117:49] + node _T_1570 = and(_T_1568, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1571 = asSInt(_T_1570) @[Parameters.scala 117:52] + node _T_1573 = eq(_T_1571, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1575 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1576 = cvt(_T_1575) @[Parameters.scala 117:49] + node _T_1578 = and(_T_1576, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1579 = asSInt(_T_1578) @[Parameters.scala 117:52] + node _T_1581 = eq(_T_1579, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1583 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1584 = cvt(_T_1583) @[Parameters.scala 117:49] + node _T_1586 = and(_T_1584, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1587 = asSInt(_T_1586) @[Parameters.scala 117:52] + node _T_1589 = eq(_T_1587, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1590 = or(_T_1549, _T_1557) @[Parameters.scala 133:42] + node _T_1591 = or(_T_1590, _T_1565) @[Parameters.scala 133:42] + node _T_1592 = or(_T_1591, _T_1573) @[Parameters.scala 133:42] + node _T_1593 = or(_T_1592, _T_1581) @[Parameters.scala 133:42] + node _T_1594 = or(_T_1593, _T_1589) @[Parameters.scala 133:42] + node _T_1595 = and(_T_1541, _T_1594) @[Parameters.scala 132:56] + node _T_1597 = or(UInt<1>("h00"), _T_1595) @[Parameters.scala 134:30] + node _T_1598 = or(_T_1597, reset) @[RocketTiles.scala 51:21] + node _T_1600 = eq(_T_1598, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1600 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1601 = or(_T_869[0], reset) @[RocketTiles.scala 51:21] + node _T_1603 = eq(_T_1601, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1603 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1604 = or(_T_880, reset) @[RocketTiles.scala 51:21] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1606 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1607 = eq(io.in[0].a.bits.mask, _T_948) @[RocketTiles.scala 51:21] + node _T_1608 = or(_T_1607, reset) @[RocketTiles.scala 51:21] + node _T_1610 = eq(_T_1608, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1610 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[0].b.valid : @[RocketTiles.scala 51:21] + node _T_1612 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1613 = or(_T_1612, reset) @[RocketTiles.scala 51:21] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1615 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1617 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1618 = cvt(_T_1617) @[Parameters.scala 117:49] + node _T_1620 = and(_T_1618, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1621 = asSInt(_T_1620) @[Parameters.scala 117:52] + node _T_1623 = eq(_T_1621, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1625 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1626 = cvt(_T_1625) @[Parameters.scala 117:49] + node _T_1628 = and(_T_1626, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1629 = asSInt(_T_1628) @[Parameters.scala 117:52] + node _T_1631 = eq(_T_1629, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1633 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1634 = cvt(_T_1633) @[Parameters.scala 117:49] + node _T_1636 = and(_T_1634, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1637 = asSInt(_T_1636) @[Parameters.scala 117:52] + node _T_1639 = eq(_T_1637, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1641 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1642 = cvt(_T_1641) @[Parameters.scala 117:49] + node _T_1644 = and(_T_1642, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1645 = asSInt(_T_1644) @[Parameters.scala 117:52] + node _T_1647 = eq(_T_1645, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1649 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1650 = cvt(_T_1649) @[Parameters.scala 117:49] + node _T_1652 = and(_T_1650, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1653 = asSInt(_T_1652) @[Parameters.scala 117:52] + node _T_1655 = eq(_T_1653, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1657 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1658 = cvt(_T_1657) @[Parameters.scala 117:49] + node _T_1660 = and(_T_1658, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1661 = asSInt(_T_1660) @[Parameters.scala 117:52] + node _T_1663 = eq(_T_1661, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1665 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1666 = cvt(_T_1665) @[Parameters.scala 117:49] + node _T_1668 = and(_T_1666, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1669 = asSInt(_T_1668) @[Parameters.scala 117:52] + node _T_1671 = eq(_T_1669, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1674 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1674 is invalid @[Parameters.scala 110:36] + _T_1674[0] <= _T_1623 @[Parameters.scala 110:36] + _T_1674[1] <= _T_1631 @[Parameters.scala 110:36] + _T_1674[2] <= _T_1639 @[Parameters.scala 110:36] + _T_1674[3] <= _T_1647 @[Parameters.scala 110:36] + _T_1674[4] <= _T_1655 @[Parameters.scala 110:36] + _T_1674[5] <= _T_1663 @[Parameters.scala 110:36] + _T_1674[6] <= _T_1671 @[Parameters.scala 110:36] + node _T_1684 = or(_T_1674[0], _T_1674[1]) @[Parameters.scala 119:64] + node _T_1685 = or(_T_1684, _T_1674[2]) @[Parameters.scala 119:64] + node _T_1686 = or(_T_1685, _T_1674[3]) @[Parameters.scala 119:64] + node _T_1687 = or(_T_1686, _T_1674[4]) @[Parameters.scala 119:64] + node _T_1688 = or(_T_1687, _T_1674[5]) @[Parameters.scala 119:64] + node _T_1689 = or(_T_1688, _T_1674[6]) @[Parameters.scala 119:64] + node _T_1691 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1692 = dshl(_T_1691, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1693 = bits(_T_1692, 7, 0) @[package.scala 19:76] + node _T_1694 = not(_T_1693) @[package.scala 19:40] + node _T_1695 = and(io.in[0].b.bits.address, _T_1694) @[Edges.scala 17:16] + node _T_1697 = eq(_T_1695, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1699 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1700 = dshl(UInt<1>("h01"), _T_1699) @[OneHot.scala 49:12] + node _T_1701 = bits(_T_1700, 2, 0) @[OneHot.scala 49:37] + node _T_1703 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1705 = bits(_T_1701, 2, 2) @[package.scala 44:26] + node _T_1706 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1708 = eq(_T_1706, UInt<1>("h00")) @[package.scala 46:20] + node _T_1709 = and(UInt<1>("h01"), _T_1708) @[package.scala 49:27] + node _T_1710 = and(_T_1705, _T_1709) @[package.scala 50:38] + node _T_1711 = or(_T_1703, _T_1710) @[package.scala 50:29] + node _T_1712 = and(UInt<1>("h01"), _T_1706) @[package.scala 49:27] + node _T_1713 = and(_T_1705, _T_1712) @[package.scala 50:38] + node _T_1714 = or(_T_1703, _T_1713) @[package.scala 50:29] + node _T_1715 = bits(_T_1701, 1, 1) @[package.scala 44:26] + node _T_1716 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1718 = eq(_T_1716, UInt<1>("h00")) @[package.scala 46:20] + node _T_1719 = and(_T_1709, _T_1718) @[package.scala 49:27] + node _T_1720 = and(_T_1715, _T_1719) @[package.scala 50:38] + node _T_1721 = or(_T_1711, _T_1720) @[package.scala 50:29] + node _T_1722 = and(_T_1709, _T_1716) @[package.scala 49:27] + node _T_1723 = and(_T_1715, _T_1722) @[package.scala 50:38] + node _T_1724 = or(_T_1711, _T_1723) @[package.scala 50:29] + node _T_1725 = and(_T_1712, _T_1718) @[package.scala 49:27] + node _T_1726 = and(_T_1715, _T_1725) @[package.scala 50:38] + node _T_1727 = or(_T_1714, _T_1726) @[package.scala 50:29] + node _T_1728 = and(_T_1712, _T_1716) @[package.scala 49:27] + node _T_1729 = and(_T_1715, _T_1728) @[package.scala 50:38] + node _T_1730 = or(_T_1714, _T_1729) @[package.scala 50:29] + node _T_1731 = bits(_T_1701, 0, 0) @[package.scala 44:26] + node _T_1732 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1734 = eq(_T_1732, UInt<1>("h00")) @[package.scala 46:20] + node _T_1735 = and(_T_1719, _T_1734) @[package.scala 49:27] + node _T_1736 = and(_T_1731, _T_1735) @[package.scala 50:38] + node _T_1737 = or(_T_1721, _T_1736) @[package.scala 50:29] + node _T_1738 = and(_T_1719, _T_1732) @[package.scala 49:27] + node _T_1739 = and(_T_1731, _T_1738) @[package.scala 50:38] + node _T_1740 = or(_T_1721, _T_1739) @[package.scala 50:29] + node _T_1741 = and(_T_1722, _T_1734) @[package.scala 49:27] + node _T_1742 = and(_T_1731, _T_1741) @[package.scala 50:38] + node _T_1743 = or(_T_1724, _T_1742) @[package.scala 50:29] + node _T_1744 = and(_T_1722, _T_1732) @[package.scala 49:27] + node _T_1745 = and(_T_1731, _T_1744) @[package.scala 50:38] + node _T_1746 = or(_T_1724, _T_1745) @[package.scala 50:29] + node _T_1747 = and(_T_1725, _T_1734) @[package.scala 49:27] + node _T_1748 = and(_T_1731, _T_1747) @[package.scala 50:38] + node _T_1749 = or(_T_1727, _T_1748) @[package.scala 50:29] + node _T_1750 = and(_T_1725, _T_1732) @[package.scala 49:27] + node _T_1751 = and(_T_1731, _T_1750) @[package.scala 50:38] + node _T_1752 = or(_T_1727, _T_1751) @[package.scala 50:29] + node _T_1753 = and(_T_1728, _T_1734) @[package.scala 49:27] + node _T_1754 = and(_T_1731, _T_1753) @[package.scala 50:38] + node _T_1755 = or(_T_1730, _T_1754) @[package.scala 50:29] + node _T_1756 = and(_T_1728, _T_1732) @[package.scala 49:27] + node _T_1757 = and(_T_1731, _T_1756) @[package.scala 50:38] + node _T_1758 = or(_T_1730, _T_1757) @[package.scala 50:29] + node _T_1759 = cat(_T_1740, _T_1737) @[Cat.scala 30:58] + node _T_1760 = cat(_T_1746, _T_1743) @[Cat.scala 30:58] + node _T_1761 = cat(_T_1760, _T_1759) @[Cat.scala 30:58] + node _T_1762 = cat(_T_1752, _T_1749) @[Cat.scala 30:58] + node _T_1763 = cat(_T_1758, _T_1755) @[Cat.scala 30:58] + node _T_1764 = cat(_T_1763, _T_1762) @[Cat.scala 30:58] + node _T_1765 = cat(_T_1764, _T_1761) @[Cat.scala 30:58] + node _T_1767 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_1767 : @[RocketTiles.scala 51:21] + node _T_1769 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1771 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1772 = and(_T_1769, _T_1771) @[Parameters.scala 63:37] + node _T_1773 = or(_T_1772, reset) @[RocketTiles.scala 51:21] + node _T_1775 = eq(_T_1773, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1775 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1776 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1778 = eq(_T_1776, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1778 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1780 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_1781 = or(_T_1780, reset) @[RocketTiles.scala 51:21] + node _T_1783 = eq(_T_1781, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1783 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1784 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1786 = eq(_T_1784, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1786 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1788 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1789 = or(_T_1788, reset) @[RocketTiles.scala 51:21] + node _T_1791 = eq(_T_1789, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1791 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1792 = not(io.in[0].b.bits.mask) @[RocketTiles.scala 51:21] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1795 = or(_T_1794, reset) @[RocketTiles.scala 51:21] + node _T_1797 = eq(_T_1795, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1797 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1799 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_1799 : @[RocketTiles.scala 51:21] + node _T_1801 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1803 = eq(_T_1801, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1803 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1804 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1806 = eq(_T_1804, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1806 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1807 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1809 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1811 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1812 = or(_T_1811, reset) @[RocketTiles.scala 51:21] + node _T_1814 = eq(_T_1812, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1814 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1815 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 51:21] + node _T_1816 = or(_T_1815, reset) @[RocketTiles.scala 51:21] + node _T_1818 = eq(_T_1816, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1818 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1820 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1820 : @[RocketTiles.scala 51:21] + node _T_1822 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1824 = eq(_T_1822, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1824 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1825 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1827 = eq(_T_1825, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1827 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1828 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1830 = eq(_T_1828, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1830 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1832 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1833 = or(_T_1832, reset) @[RocketTiles.scala 51:21] + node _T_1835 = eq(_T_1833, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1835 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1836 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 51:21] + node _T_1837 = or(_T_1836, reset) @[RocketTiles.scala 51:21] + node _T_1839 = eq(_T_1837, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1839 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1841 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_1841 : @[RocketTiles.scala 51:21] + node _T_1843 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1845 = eq(_T_1843, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1845 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1846 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1848 = eq(_T_1846, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1848 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1849 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1851 = eq(_T_1849, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1851 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1853 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1854 = or(_T_1853, reset) @[RocketTiles.scala 51:21] + node _T_1856 = eq(_T_1854, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1856 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1857 = not(_T_1765) @[RocketTiles.scala 51:21] + node _T_1858 = and(io.in[0].b.bits.mask, _T_1857) @[RocketTiles.scala 51:21] + node _T_1860 = eq(_T_1858, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_1861 = or(_T_1860, reset) @[RocketTiles.scala 51:21] + node _T_1863 = eq(_T_1861, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1863 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1865 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_1865 : @[RocketTiles.scala 51:21] + node _T_1867 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1869 = eq(_T_1867, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1869 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1870 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1872 = eq(_T_1870, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1872 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1873 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1875 = eq(_T_1873, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1875 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1877 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1878 = or(_T_1877, reset) @[RocketTiles.scala 51:21] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1880 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1881 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 51:21] + node _T_1882 = or(_T_1881, reset) @[RocketTiles.scala 51:21] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1884 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1886 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 51:21] + when _T_1886 : @[RocketTiles.scala 51:21] + node _T_1888 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1890 = eq(_T_1888, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1890 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1891 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1893 = eq(_T_1891, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1893 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1894 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1896 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1898 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1899 = or(_T_1898, reset) @[RocketTiles.scala 51:21] + node _T_1901 = eq(_T_1899, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1901 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1902 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 51:21] + node _T_1903 = or(_T_1902, reset) @[RocketTiles.scala 51:21] + node _T_1905 = eq(_T_1903, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1905 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1907 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_1907 : @[RocketTiles.scala 51:21] + node _T_1909 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_1911 = eq(_T_1909, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1911 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1912 = or(_T_1689, reset) @[RocketTiles.scala 51:21] + node _T_1914 = eq(_T_1912, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1914 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1915 = or(_T_1697, reset) @[RocketTiles.scala 51:21] + node _T_1917 = eq(_T_1915, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1917 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1918 = eq(io.in[0].b.bits.mask, _T_1765) @[RocketTiles.scala 51:21] + node _T_1919 = or(_T_1918, reset) @[RocketTiles.scala 51:21] + node _T_1921 = eq(_T_1919, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1921 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[0].c.valid : @[RocketTiles.scala 51:21] + node _T_1923 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1924 = or(_T_1923, reset) @[RocketTiles.scala 51:21] + node _T_1926 = eq(_T_1924, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_1926 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_1928 = eq(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1931 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1931 is invalid @[Parameters.scala 228:27] + _T_1931[0] <= _T_1928 @[Parameters.scala 228:27] + node _T_1936 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1937 = dshl(_T_1936, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1938 = bits(_T_1937, 7, 0) @[package.scala 19:76] + node _T_1939 = not(_T_1938) @[package.scala 19:40] + node _T_1940 = and(io.in[0].c.bits.address, _T_1939) @[Edges.scala 17:16] + node _T_1942 = eq(_T_1940, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1944 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1945 = cvt(_T_1944) @[Parameters.scala 117:49] + node _T_1947 = and(_T_1945, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1948 = asSInt(_T_1947) @[Parameters.scala 117:52] + node _T_1950 = eq(_T_1948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1952 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1953 = cvt(_T_1952) @[Parameters.scala 117:49] + node _T_1955 = and(_T_1953, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1956 = asSInt(_T_1955) @[Parameters.scala 117:52] + node _T_1958 = eq(_T_1956, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1960 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1961 = cvt(_T_1960) @[Parameters.scala 117:49] + node _T_1963 = and(_T_1961, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1964 = asSInt(_T_1963) @[Parameters.scala 117:52] + node _T_1966 = eq(_T_1964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1968 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1969 = cvt(_T_1968) @[Parameters.scala 117:49] + node _T_1971 = and(_T_1969, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1972 = asSInt(_T_1971) @[Parameters.scala 117:52] + node _T_1974 = eq(_T_1972, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1977 = cvt(_T_1976) @[Parameters.scala 117:49] + node _T_1979 = and(_T_1977, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1980 = asSInt(_T_1979) @[Parameters.scala 117:52] + node _T_1982 = eq(_T_1980, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1984 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1985 = cvt(_T_1984) @[Parameters.scala 117:49] + node _T_1987 = and(_T_1985, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1988 = asSInt(_T_1987) @[Parameters.scala 117:52] + node _T_1990 = eq(_T_1988, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1992 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1993 = cvt(_T_1992) @[Parameters.scala 117:49] + node _T_1995 = and(_T_1993, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1996 = asSInt(_T_1995) @[Parameters.scala 117:52] + node _T_1998 = eq(_T_1996, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_2001 : UInt<1>[7] @[Parameters.scala 110:36] + _T_2001 is invalid @[Parameters.scala 110:36] + _T_2001[0] <= _T_1950 @[Parameters.scala 110:36] + _T_2001[1] <= _T_1958 @[Parameters.scala 110:36] + _T_2001[2] <= _T_1966 @[Parameters.scala 110:36] + _T_2001[3] <= _T_1974 @[Parameters.scala 110:36] + _T_2001[4] <= _T_1982 @[Parameters.scala 110:36] + _T_2001[5] <= _T_1990 @[Parameters.scala 110:36] + _T_2001[6] <= _T_1998 @[Parameters.scala 110:36] + node _T_2011 = or(_T_2001[0], _T_2001[1]) @[Parameters.scala 119:64] + node _T_2012 = or(_T_2011, _T_2001[2]) @[Parameters.scala 119:64] + node _T_2013 = or(_T_2012, _T_2001[3]) @[Parameters.scala 119:64] + node _T_2014 = or(_T_2013, _T_2001[4]) @[Parameters.scala 119:64] + node _T_2015 = or(_T_2014, _T_2001[5]) @[Parameters.scala 119:64] + node _T_2016 = or(_T_2015, _T_2001[6]) @[Parameters.scala 119:64] + node _T_2018 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_2018 : @[RocketTiles.scala 51:21] + node _T_2019 = or(_T_2016, reset) @[RocketTiles.scala 51:21] + node _T_2021 = eq(_T_2019, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2021 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2022 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2024 = eq(_T_2022, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2024 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2026 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2027 = or(_T_2026, reset) @[RocketTiles.scala 51:21] + node _T_2029 = eq(_T_2027, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2029 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2030 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2032 = eq(_T_2030, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2032 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2034 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2035 = or(_T_2034, reset) @[RocketTiles.scala 51:21] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2037 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2039 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2040 = or(_T_2039, reset) @[RocketTiles.scala 51:21] + node _T_2042 = eq(_T_2040, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2042 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2044 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_2044 : @[RocketTiles.scala 51:21] + node _T_2045 = or(_T_2016, reset) @[RocketTiles.scala 51:21] + node _T_2047 = eq(_T_2045, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2047 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2048 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2050 = eq(_T_2048, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2050 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2052 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2053 = or(_T_2052, reset) @[RocketTiles.scala 51:21] + node _T_2055 = eq(_T_2053, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2055 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2056 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2058 = eq(_T_2056, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2058 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2060 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_2061 = or(_T_2060, reset) @[RocketTiles.scala 51:21] + node _T_2063 = eq(_T_2061, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2063 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2065 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2066 = or(_T_2065, reset) @[RocketTiles.scala 51:21] + node _T_2068 = eq(_T_2066, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2068 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2070 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_2070 : @[RocketTiles.scala 51:21] + node _T_2073 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2075 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2076 = and(_T_2073, _T_2075) @[Parameters.scala 63:37] + node _T_2077 = or(UInt<1>("h00"), _T_2076) @[Parameters.scala 132:31] + node _T_2079 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2080 = cvt(_T_2079) @[Parameters.scala 117:49] + node _T_2082 = and(_T_2080, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2083 = asSInt(_T_2082) @[Parameters.scala 117:52] + node _T_2085 = eq(_T_2083, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2087 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2088 = cvt(_T_2087) @[Parameters.scala 117:49] + node _T_2090 = and(_T_2088, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2091 = asSInt(_T_2090) @[Parameters.scala 117:52] + node _T_2093 = eq(_T_2091, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2094 = or(_T_2085, _T_2093) @[Parameters.scala 133:42] + node _T_2095 = and(_T_2077, _T_2094) @[Parameters.scala 132:56] + node _T_2098 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2100 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2101 = cvt(_T_2100) @[Parameters.scala 117:49] + node _T_2103 = and(_T_2101, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2104 = asSInt(_T_2103) @[Parameters.scala 117:52] + node _T_2106 = eq(_T_2104, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2108 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2109 = cvt(_T_2108) @[Parameters.scala 117:49] + node _T_2111 = and(_T_2109, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2112 = asSInt(_T_2111) @[Parameters.scala 117:52] + node _T_2114 = eq(_T_2112, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2116 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2117 = cvt(_T_2116) @[Parameters.scala 117:49] + node _T_2119 = and(_T_2117, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2120 = asSInt(_T_2119) @[Parameters.scala 117:52] + node _T_2122 = eq(_T_2120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2124 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2125 = cvt(_T_2124) @[Parameters.scala 117:49] + node _T_2127 = and(_T_2125, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2128 = asSInt(_T_2127) @[Parameters.scala 117:52] + node _T_2130 = eq(_T_2128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2131 = or(_T_2106, _T_2114) @[Parameters.scala 133:42] + node _T_2132 = or(_T_2131, _T_2122) @[Parameters.scala 133:42] + node _T_2133 = or(_T_2132, _T_2130) @[Parameters.scala 133:42] + node _T_2134 = and(_T_2098, _T_2133) @[Parameters.scala 132:56] + node _T_2136 = or(UInt<1>("h00"), _T_2095) @[Parameters.scala 134:30] + node _T_2137 = or(_T_2136, _T_2134) @[Parameters.scala 134:30] + node _T_2138 = or(_T_2137, reset) @[RocketTiles.scala 51:21] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2140 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2141 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2143 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2145 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2146 = or(_T_2145, reset) @[RocketTiles.scala 51:21] + node _T_2148 = eq(_T_2146, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2148 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2149 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2151 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2153 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2154 = or(_T_2153, reset) @[RocketTiles.scala 51:21] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2156 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2158 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2159 = or(_T_2158, reset) @[RocketTiles.scala 51:21] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2161 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2163 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RocketTiles.scala 51:21] + when _T_2163 : @[RocketTiles.scala 51:21] + node _T_2166 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_2168 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2169 = and(_T_2166, _T_2168) @[Parameters.scala 63:37] + node _T_2170 = or(UInt<1>("h00"), _T_2169) @[Parameters.scala 132:31] + node _T_2172 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2173 = cvt(_T_2172) @[Parameters.scala 117:49] + node _T_2175 = and(_T_2173, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2176 = asSInt(_T_2175) @[Parameters.scala 117:52] + node _T_2178 = eq(_T_2176, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2180 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2181 = cvt(_T_2180) @[Parameters.scala 117:49] + node _T_2183 = and(_T_2181, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2184 = asSInt(_T_2183) @[Parameters.scala 117:52] + node _T_2186 = eq(_T_2184, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2187 = or(_T_2178, _T_2186) @[Parameters.scala 133:42] + node _T_2188 = and(_T_2170, _T_2187) @[Parameters.scala 132:56] + node _T_2191 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2193 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2194 = cvt(_T_2193) @[Parameters.scala 117:49] + node _T_2196 = and(_T_2194, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2197 = asSInt(_T_2196) @[Parameters.scala 117:52] + node _T_2199 = eq(_T_2197, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2201 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2202 = cvt(_T_2201) @[Parameters.scala 117:49] + node _T_2204 = and(_T_2202, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2205 = asSInt(_T_2204) @[Parameters.scala 117:52] + node _T_2207 = eq(_T_2205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2209 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2210 = cvt(_T_2209) @[Parameters.scala 117:49] + node _T_2212 = and(_T_2210, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2213 = asSInt(_T_2212) @[Parameters.scala 117:52] + node _T_2215 = eq(_T_2213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2217 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2218 = cvt(_T_2217) @[Parameters.scala 117:49] + node _T_2220 = and(_T_2218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2221 = asSInt(_T_2220) @[Parameters.scala 117:52] + node _T_2223 = eq(_T_2221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2224 = or(_T_2199, _T_2207) @[Parameters.scala 133:42] + node _T_2225 = or(_T_2224, _T_2215) @[Parameters.scala 133:42] + node _T_2226 = or(_T_2225, _T_2223) @[Parameters.scala 133:42] + node _T_2227 = and(_T_2191, _T_2226) @[Parameters.scala 132:56] + node _T_2229 = or(UInt<1>("h00"), _T_2188) @[Parameters.scala 134:30] + node _T_2230 = or(_T_2229, _T_2227) @[Parameters.scala 134:30] + node _T_2231 = or(_T_2230, reset) @[RocketTiles.scala 51:21] + node _T_2233 = eq(_T_2231, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2233 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2234 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2236 = eq(_T_2234, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2236 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2238 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2239 = or(_T_2238, reset) @[RocketTiles.scala 51:21] + node _T_2241 = eq(_T_2239, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2241 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2242 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2244 = eq(_T_2242, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2244 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2246 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_2247 = or(_T_2246, reset) @[RocketTiles.scala 51:21] + node _T_2249 = eq(_T_2247, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2249 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2251 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2252 = or(_T_2251, reset) @[RocketTiles.scala 51:21] + node _T_2254 = eq(_T_2252, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2254 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2256 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2256 : @[RocketTiles.scala 51:21] + node _T_2257 = or(_T_2016, reset) @[RocketTiles.scala 51:21] + node _T_2259 = eq(_T_2257, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2259 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2260 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2262 = eq(_T_2260, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2262 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2263 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2265 = eq(_T_2263, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2265 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2267 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2268 = or(_T_2267, reset) @[RocketTiles.scala 51:21] + node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2270 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2272 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_2272 : @[RocketTiles.scala 51:21] + node _T_2273 = or(_T_2016, reset) @[RocketTiles.scala 51:21] + node _T_2275 = eq(_T_2273, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2275 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2276 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2278 = eq(_T_2276, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2278 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2279 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2281 = eq(_T_2279, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2281 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2283 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2284 = or(_T_2283, reset) @[RocketTiles.scala 51:21] + node _T_2286 = eq(_T_2284, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2286 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2288 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_2288 : @[RocketTiles.scala 51:21] + node _T_2289 = or(_T_2016, reset) @[RocketTiles.scala 51:21] + node _T_2291 = eq(_T_2289, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2291 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2292 = or(_T_1931[0], reset) @[RocketTiles.scala 51:21] + node _T_2294 = eq(_T_2292, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2294 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2295 = or(_T_1942, reset) @[RocketTiles.scala 51:21] + node _T_2297 = eq(_T_2295, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2297 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2299 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2300 = or(_T_2299, reset) @[RocketTiles.scala 51:21] + node _T_2302 = eq(_T_2300, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2302 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2304 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2305 = or(_T_2304, reset) @[RocketTiles.scala 51:21] + node _T_2307 = eq(_T_2305, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2307 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[0].d.valid : @[RocketTiles.scala 51:21] + node _T_2309 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2310 = or(_T_2309, reset) @[RocketTiles.scala 51:21] + node _T_2312 = eq(_T_2310, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2312 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2314 = eq(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_2317 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2317 is invalid @[Parameters.scala 228:27] + _T_2317[0] <= _T_2314 @[Parameters.scala 228:27] + node _T_2322 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2323 = dshl(_T_2322, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2324 = bits(_T_2323, 7, 0) @[package.scala 19:76] + node _T_2325 = not(_T_2324) @[package.scala 19:40] + node _T_2326 = and(io.in[0].d.bits.addr_lo, _T_2325) @[Edges.scala 17:16] + node _T_2328 = eq(_T_2326, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2330 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 51:21] + node _T_2332 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_2332 : @[RocketTiles.scala 51:21] + node _T_2333 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2335 = eq(_T_2333, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2335 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2336 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2338 = eq(_T_2336, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2338 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2339 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2341 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2343 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2344 = or(_T_2343, reset) @[RocketTiles.scala 51:21] + node _T_2346 = eq(_T_2344, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2346 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2348 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2349 = or(_T_2348, reset) @[RocketTiles.scala 51:21] + node _T_2351 = eq(_T_2349, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2351 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2353 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2354 = or(_T_2353, reset) @[RocketTiles.scala 51:21] + node _T_2356 = eq(_T_2354, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2356 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2358 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_2358 : @[RocketTiles.scala 51:21] + node _T_2359 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2361 = eq(_T_2359, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2361 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2362 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2364 = eq(_T_2362, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2364 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2365 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2367 = eq(_T_2365, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2367 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2369 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2370 = or(_T_2369, reset) @[RocketTiles.scala 51:21] + node _T_2372 = eq(_T_2370, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2372 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2374 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2375 = or(_T_2374, reset) @[RocketTiles.scala 51:21] + node _T_2377 = eq(_T_2375, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2377 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2379 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_2379 : @[RocketTiles.scala 51:21] + node _T_2380 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2382 = eq(_T_2380, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2382 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2383 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2385 = eq(_T_2383, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2385 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2386 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2388 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2390 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2391 = or(_T_2390, reset) @[RocketTiles.scala 51:21] + node _T_2393 = eq(_T_2391, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2393 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2395 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2396 = or(_T_2395, reset) @[RocketTiles.scala 51:21] + node _T_2398 = eq(_T_2396, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2398 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2400 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2400 : @[RocketTiles.scala 51:21] + node _T_2401 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2403 = eq(_T_2401, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2403 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2404 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2406 = eq(_T_2404, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2406 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2407 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2409 = eq(_T_2407, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2409 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2411 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2412 = or(_T_2411, reset) @[RocketTiles.scala 51:21] + node _T_2414 = eq(_T_2412, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2414 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2416 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_2416 : @[RocketTiles.scala 51:21] + node _T_2417 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2419 = eq(_T_2417, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2419 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2420 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2422 = eq(_T_2420, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2422 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2423 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2425 = eq(_T_2423, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2425 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2427 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2428 = or(_T_2427, reset) @[RocketTiles.scala 51:21] + node _T_2430 = eq(_T_2428, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2430 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2432 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_2432 : @[RocketTiles.scala 51:21] + node _T_2433 = or(_T_2317[0], reset) @[RocketTiles.scala 51:21] + node _T_2435 = eq(_T_2433, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2435 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2436 = or(_T_2328, reset) @[RocketTiles.scala 51:21] + node _T_2438 = eq(_T_2436, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2438 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2439 = or(_T_2330, reset) @[RocketTiles.scala 51:21] + node _T_2441 = eq(_T_2439, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2441 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2443 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2444 = or(_T_2443, reset) @[RocketTiles.scala 51:21] + node _T_2446 = eq(_T_2444, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2446 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2448 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2449 = or(_T_2448, reset) @[RocketTiles.scala 51:21] + node _T_2451 = eq(_T_2449, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2451 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[0].e.valid : @[RocketTiles.scala 51:21] + node _T_2453 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 51:21] + node _T_2454 = or(_T_2453, reset) @[RocketTiles.scala 51:21] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2456 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2457 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2459 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2460 = dshl(_T_2459, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2461 = bits(_T_2460, 7, 0) @[package.scala 19:76] + node _T_2462 = not(_T_2461) @[package.scala 19:40] + node _T_2463 = shr(_T_2462, 3) @[Edges.scala 198:59] + node _T_2464 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2466 = eq(_T_2464, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2468 = mux(_T_2466, _T_2463, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2470 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2472 = sub(_T_2470, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2473 = asUInt(_T_2472) @[Edges.scala 208:28] + node _T_2474 = tail(_T_2473, 1) @[Edges.scala 208:28] + node _T_2476 = eq(_T_2470, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2478 = eq(_T_2470, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2480 = eq(_T_2468, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2481 = or(_T_2478, _T_2480) @[Edges.scala 210:37] + node _T_2482 = and(_T_2481, _T_2457) @[Edges.scala 211:22] + node _T_2483 = not(_T_2474) @[Edges.scala 212:27] + node _T_2484 = and(_T_2468, _T_2483) @[Edges.scala 212:25] + when _T_2457 : @[Edges.scala 213:17] + node _T_2485 = mux(_T_2476, _T_2468, _T_2474) @[Edges.scala 214:21] + _T_2470 <= _T_2485 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2487 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2489 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2491 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2493 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2495 : UInt, clock @[RocketTiles.scala 51:21] + node _T_2497 = eq(_T_2476, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2498 = and(io.in[0].a.valid, _T_2497) @[RocketTiles.scala 51:21] + when _T_2498 : @[RocketTiles.scala 51:21] + node _T_2499 = eq(io.in[0].a.bits.opcode, _T_2487) @[RocketTiles.scala 51:21] + node _T_2500 = or(_T_2499, reset) @[RocketTiles.scala 51:21] + node _T_2502 = eq(_T_2500, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2502 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2503 = eq(io.in[0].a.bits.param, _T_2489) @[RocketTiles.scala 51:21] + node _T_2504 = or(_T_2503, reset) @[RocketTiles.scala 51:21] + node _T_2506 = eq(_T_2504, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2506 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2507 = eq(io.in[0].a.bits.size, _T_2491) @[RocketTiles.scala 51:21] + node _T_2508 = or(_T_2507, reset) @[RocketTiles.scala 51:21] + node _T_2510 = eq(_T_2508, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2510 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2511 = eq(io.in[0].a.bits.source, _T_2493) @[RocketTiles.scala 51:21] + node _T_2512 = or(_T_2511, reset) @[RocketTiles.scala 51:21] + node _T_2514 = eq(_T_2512, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2514 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2515 = eq(io.in[0].a.bits.address, _T_2495) @[RocketTiles.scala 51:21] + node _T_2516 = or(_T_2515, reset) @[RocketTiles.scala 51:21] + node _T_2518 = eq(_T_2516, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2518 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2519 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2520 = and(_T_2519, _T_2476) @[RocketTiles.scala 51:21] + when _T_2520 : @[RocketTiles.scala 51:21] + _T_2487 <= io.in[0].a.bits.opcode @[RocketTiles.scala 51:21] + _T_2489 <= io.in[0].a.bits.param @[RocketTiles.scala 51:21] + _T_2491 <= io.in[0].a.bits.size @[RocketTiles.scala 51:21] + _T_2493 <= io.in[0].a.bits.source @[RocketTiles.scala 51:21] + _T_2495 <= io.in[0].a.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2521 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2523 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2524 = dshl(_T_2523, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2525 = bits(_T_2524, 7, 0) @[package.scala 19:76] + node _T_2526 = not(_T_2525) @[package.scala 19:40] + node _T_2527 = shr(_T_2526, 3) @[Edges.scala 198:59] + node _T_2528 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2530 = eq(_T_2528, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2533 = mux(UInt<1>("h00"), _T_2527, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2535 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2537 = sub(_T_2535, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2538 = asUInt(_T_2537) @[Edges.scala 208:28] + node _T_2539 = tail(_T_2538, 1) @[Edges.scala 208:28] + node _T_2541 = eq(_T_2535, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2543 = eq(_T_2535, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2545 = eq(_T_2533, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2546 = or(_T_2543, _T_2545) @[Edges.scala 210:37] + node _T_2547 = and(_T_2546, _T_2521) @[Edges.scala 211:22] + node _T_2548 = not(_T_2539) @[Edges.scala 212:27] + node _T_2549 = and(_T_2533, _T_2548) @[Edges.scala 212:25] + when _T_2521 : @[Edges.scala 213:17] + node _T_2550 = mux(_T_2541, _T_2533, _T_2539) @[Edges.scala 214:21] + _T_2535 <= _T_2550 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2552 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2554 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2556 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2558 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2560 : UInt, clock @[RocketTiles.scala 51:21] + node _T_2562 = eq(_T_2541, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2563 = and(io.in[0].b.valid, _T_2562) @[RocketTiles.scala 51:21] + when _T_2563 : @[RocketTiles.scala 51:21] + node _T_2564 = eq(io.in[0].b.bits.opcode, _T_2552) @[RocketTiles.scala 51:21] + node _T_2565 = or(_T_2564, reset) @[RocketTiles.scala 51:21] + node _T_2567 = eq(_T_2565, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2567 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2568 = eq(io.in[0].b.bits.param, _T_2554) @[RocketTiles.scala 51:21] + node _T_2569 = or(_T_2568, reset) @[RocketTiles.scala 51:21] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2571 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2572 = eq(io.in[0].b.bits.size, _T_2556) @[RocketTiles.scala 51:21] + node _T_2573 = or(_T_2572, reset) @[RocketTiles.scala 51:21] + node _T_2575 = eq(_T_2573, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2575 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2576 = eq(io.in[0].b.bits.source, _T_2558) @[RocketTiles.scala 51:21] + node _T_2577 = or(_T_2576, reset) @[RocketTiles.scala 51:21] + node _T_2579 = eq(_T_2577, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2579 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2580 = eq(io.in[0].b.bits.address, _T_2560) @[RocketTiles.scala 51:21] + node _T_2581 = or(_T_2580, reset) @[RocketTiles.scala 51:21] + node _T_2583 = eq(_T_2581, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2583 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2584 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2585 = and(_T_2584, _T_2541) @[RocketTiles.scala 51:21] + when _T_2585 : @[RocketTiles.scala 51:21] + _T_2552 <= io.in[0].b.bits.opcode @[RocketTiles.scala 51:21] + _T_2554 <= io.in[0].b.bits.param @[RocketTiles.scala 51:21] + _T_2556 <= io.in[0].b.bits.size @[RocketTiles.scala 51:21] + _T_2558 <= io.in[0].b.bits.source @[RocketTiles.scala 51:21] + _T_2560 <= io.in[0].b.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2586 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2588 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2589 = dshl(_T_2588, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2590 = bits(_T_2589, 7, 0) @[package.scala 19:76] + node _T_2591 = not(_T_2590) @[package.scala 19:40] + node _T_2592 = shr(_T_2591, 3) @[Edges.scala 198:59] + node _T_2593 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2595 = mux(_T_2593, _T_2592, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2597 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2599 = sub(_T_2597, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2600 = asUInt(_T_2599) @[Edges.scala 208:28] + node _T_2601 = tail(_T_2600, 1) @[Edges.scala 208:28] + node _T_2603 = eq(_T_2597, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2605 = eq(_T_2597, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2607 = eq(_T_2595, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2608 = or(_T_2605, _T_2607) @[Edges.scala 210:37] + node _T_2609 = and(_T_2608, _T_2586) @[Edges.scala 211:22] + node _T_2610 = not(_T_2601) @[Edges.scala 212:27] + node _T_2611 = and(_T_2595, _T_2610) @[Edges.scala 212:25] + when _T_2586 : @[Edges.scala 213:17] + node _T_2612 = mux(_T_2603, _T_2595, _T_2601) @[Edges.scala 214:21] + _T_2597 <= _T_2612 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2614 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2616 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2618 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2620 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2622 : UInt, clock @[RocketTiles.scala 51:21] + node _T_2624 = eq(_T_2603, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2625 = and(io.in[0].c.valid, _T_2624) @[RocketTiles.scala 51:21] + when _T_2625 : @[RocketTiles.scala 51:21] + node _T_2626 = eq(io.in[0].c.bits.opcode, _T_2614) @[RocketTiles.scala 51:21] + node _T_2627 = or(_T_2626, reset) @[RocketTiles.scala 51:21] + node _T_2629 = eq(_T_2627, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2629 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2630 = eq(io.in[0].c.bits.param, _T_2616) @[RocketTiles.scala 51:21] + node _T_2631 = or(_T_2630, reset) @[RocketTiles.scala 51:21] + node _T_2633 = eq(_T_2631, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2633 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2634 = eq(io.in[0].c.bits.size, _T_2618) @[RocketTiles.scala 51:21] + node _T_2635 = or(_T_2634, reset) @[RocketTiles.scala 51:21] + node _T_2637 = eq(_T_2635, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2637 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2638 = eq(io.in[0].c.bits.source, _T_2620) @[RocketTiles.scala 51:21] + node _T_2639 = or(_T_2638, reset) @[RocketTiles.scala 51:21] + node _T_2641 = eq(_T_2639, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2641 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2642 = eq(io.in[0].c.bits.address, _T_2622) @[RocketTiles.scala 51:21] + node _T_2643 = or(_T_2642, reset) @[RocketTiles.scala 51:21] + node _T_2645 = eq(_T_2643, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2645 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2646 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2647 = and(_T_2646, _T_2603) @[RocketTiles.scala 51:21] + when _T_2647 : @[RocketTiles.scala 51:21] + _T_2614 <= io.in[0].c.bits.opcode @[RocketTiles.scala 51:21] + _T_2616 <= io.in[0].c.bits.param @[RocketTiles.scala 51:21] + _T_2618 <= io.in[0].c.bits.size @[RocketTiles.scala 51:21] + _T_2620 <= io.in[0].c.bits.source @[RocketTiles.scala 51:21] + _T_2622 <= io.in[0].c.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2648 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2650 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2651 = dshl(_T_2650, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2652 = bits(_T_2651, 7, 0) @[package.scala 19:76] + node _T_2653 = not(_T_2652) @[package.scala 19:40] + node _T_2654 = shr(_T_2653, 3) @[Edges.scala 198:59] + node _T_2655 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2657 = mux(_T_2655, _T_2654, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2659 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2661 = sub(_T_2659, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2662 = asUInt(_T_2661) @[Edges.scala 208:28] + node _T_2663 = tail(_T_2662, 1) @[Edges.scala 208:28] + node _T_2665 = eq(_T_2659, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2667 = eq(_T_2659, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2669 = eq(_T_2657, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2670 = or(_T_2667, _T_2669) @[Edges.scala 210:37] + node _T_2671 = and(_T_2670, _T_2648) @[Edges.scala 211:22] + node _T_2672 = not(_T_2663) @[Edges.scala 212:27] + node _T_2673 = and(_T_2657, _T_2672) @[Edges.scala 212:25] + when _T_2648 : @[Edges.scala 213:17] + node _T_2674 = mux(_T_2665, _T_2657, _T_2663) @[Edges.scala 214:21] + _T_2659 <= _T_2674 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2676 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2678 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2680 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2682 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2684 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_2686 : UInt, clock @[RocketTiles.scala 51:21] + node _T_2688 = eq(_T_2665, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2689 = and(io.in[0].d.valid, _T_2688) @[RocketTiles.scala 51:21] + when _T_2689 : @[RocketTiles.scala 51:21] + node _T_2690 = eq(io.in[0].d.bits.opcode, _T_2676) @[RocketTiles.scala 51:21] + node _T_2691 = or(_T_2690, reset) @[RocketTiles.scala 51:21] + node _T_2693 = eq(_T_2691, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2693 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2694 = eq(io.in[0].d.bits.param, _T_2678) @[RocketTiles.scala 51:21] + node _T_2695 = or(_T_2694, reset) @[RocketTiles.scala 51:21] + node _T_2697 = eq(_T_2695, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2697 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2698 = eq(io.in[0].d.bits.size, _T_2680) @[RocketTiles.scala 51:21] + node _T_2699 = or(_T_2698, reset) @[RocketTiles.scala 51:21] + node _T_2701 = eq(_T_2699, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2701 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2702 = eq(io.in[0].d.bits.source, _T_2682) @[RocketTiles.scala 51:21] + node _T_2703 = or(_T_2702, reset) @[RocketTiles.scala 51:21] + node _T_2705 = eq(_T_2703, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2705 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2706 = eq(io.in[0].d.bits.sink, _T_2684) @[RocketTiles.scala 51:21] + node _T_2707 = or(_T_2706, reset) @[RocketTiles.scala 51:21] + node _T_2709 = eq(_T_2707, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2709 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2710 = eq(io.in[0].d.bits.addr_lo, _T_2686) @[RocketTiles.scala 51:21] + node _T_2711 = or(_T_2710, reset) @[RocketTiles.scala 51:21] + node _T_2713 = eq(_T_2711, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2713 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2714 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2715 = and(_T_2714, _T_2665) @[RocketTiles.scala 51:21] + when _T_2715 : @[RocketTiles.scala 51:21] + _T_2676 <= io.in[0].d.bits.opcode @[RocketTiles.scala 51:21] + _T_2678 <= io.in[0].d.bits.param @[RocketTiles.scala 51:21] + _T_2680 <= io.in[0].d.bits.size @[RocketTiles.scala 51:21] + _T_2682 <= io.in[0].d.bits.source @[RocketTiles.scala 51:21] + _T_2684 <= io.in[0].d.bits.sink @[RocketTiles.scala 51:21] + _T_2686 <= io.in[0].d.bits.addr_lo @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + reg _T_2717 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_2718 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2720 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2721 = dshl(_T_2720, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2722 = bits(_T_2721, 7, 0) @[package.scala 19:76] + node _T_2723 = not(_T_2722) @[package.scala 19:40] + node _T_2724 = shr(_T_2723, 3) @[Edges.scala 198:59] + node _T_2725 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2727 = eq(_T_2725, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2729 = mux(_T_2727, _T_2724, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2731 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2733 = sub(_T_2731, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2734 = asUInt(_T_2733) @[Edges.scala 208:28] + node _T_2735 = tail(_T_2734, 1) @[Edges.scala 208:28] + node _T_2737 = eq(_T_2731, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2739 = eq(_T_2731, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2741 = eq(_T_2729, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2742 = or(_T_2739, _T_2741) @[Edges.scala 210:37] + node _T_2743 = and(_T_2742, _T_2718) @[Edges.scala 211:22] + node _T_2744 = not(_T_2735) @[Edges.scala 212:27] + node _T_2745 = and(_T_2729, _T_2744) @[Edges.scala 212:25] + when _T_2718 : @[Edges.scala 213:17] + node _T_2746 = mux(_T_2737, _T_2729, _T_2735) @[Edges.scala 214:21] + _T_2731 <= _T_2746 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2747 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2749 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2750 = dshl(_T_2749, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2751 = bits(_T_2750, 7, 0) @[package.scala 19:76] + node _T_2752 = not(_T_2751) @[package.scala 19:40] + node _T_2753 = shr(_T_2752, 3) @[Edges.scala 198:59] + node _T_2754 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2756 = mux(_T_2754, _T_2753, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2758 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2760 = sub(_T_2758, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2761 = asUInt(_T_2760) @[Edges.scala 208:28] + node _T_2762 = tail(_T_2761, 1) @[Edges.scala 208:28] + node _T_2764 = eq(_T_2758, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2766 = eq(_T_2758, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2768 = eq(_T_2756, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2769 = or(_T_2766, _T_2768) @[Edges.scala 210:37] + node _T_2770 = and(_T_2769, _T_2747) @[Edges.scala 211:22] + node _T_2771 = not(_T_2762) @[Edges.scala 212:27] + node _T_2772 = and(_T_2756, _T_2771) @[Edges.scala 212:25] + when _T_2747 : @[Edges.scala 213:17] + node _T_2773 = mux(_T_2764, _T_2756, _T_2762) @[Edges.scala 214:21] + _T_2758 <= _T_2773 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2775 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + node _T_2776 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[RocketTiles.scala 51:21] + node _T_2777 = or(_T_2775, _T_2776) @[RocketTiles.scala 51:21] + node _T_2779 = eq(io.in[0].a.valid, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2780 = or(_T_2777, _T_2779) @[RocketTiles.scala 51:21] + node _T_2782 = eq(io.in[0].d.valid, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2783 = or(_T_2780, _T_2782) @[RocketTiles.scala 51:21] + node _T_2784 = or(_T_2783, reset) @[RocketTiles.scala 51:21] + node _T_2786 = eq(_T_2784, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2786 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at RocketTiles.scala:51:21)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + wire _T_2788 : UInt<1> + _T_2788 is invalid + _T_2788 <= UInt<1>("h00") + node _T_2789 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2789 : @[RocketTiles.scala 51:21] + when _T_2742 : @[RocketTiles.scala 51:21] + node _T_2791 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2788 <= _T_2791 @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2792 = dshr(_T_2717, io.in[0].a.bits.source) @[RocketTiles.scala 51:21] + node _T_2793 = bits(_T_2792, 0, 0) @[RocketTiles.scala 51:21] + node _T_2795 = eq(_T_2793, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2796 = or(_T_2795, reset) @[RocketTiles.scala 51:21] + node _T_2798 = eq(_T_2796, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2798 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + wire _T_2800 : UInt<1> + _T_2800 is invalid + _T_2800 <= UInt<1>("h00") + node _T_2801 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2803 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + node _T_2804 = and(_T_2801, _T_2803) @[RocketTiles.scala 51:21] + when _T_2804 : @[RocketTiles.scala 51:21] + when _T_2769 : @[RocketTiles.scala 51:21] + node _T_2806 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2800 <= _T_2806 @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2807 = or(_T_2788, _T_2717) @[RocketTiles.scala 51:21] + node _T_2808 = dshr(_T_2807, io.in[0].d.bits.source) @[RocketTiles.scala 51:21] + node _T_2809 = bits(_T_2808, 0, 0) @[RocketTiles.scala 51:21] + node _T_2810 = or(_T_2809, reset) @[RocketTiles.scala 51:21] + node _T_2812 = eq(_T_2810, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2812 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketTiles.scala:51:21)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2813 = or(_T_2717, _T_2788) @[RocketTiles.scala 51:21] + node _T_2814 = not(_T_2800) @[RocketTiles.scala 51:21] + node _T_2815 = and(_T_2813, _T_2814) @[RocketTiles.scala 51:21] + _T_2717 <= _T_2815 @[RocketTiles.scala 51:21] + when io.in[1].a.valid : @[RocketTiles.scala 51:21] + node _T_2817 = leq(io.in[1].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_2818 = or(_T_2817, reset) @[RocketTiles.scala 51:21] + node _T_2820 = eq(_T_2818, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2820 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2822 = eq(UInt<1>("h00"), io.in[1].a.bits.source) @[Parameters.scala 35:39] + wire _T_2825 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2825 is invalid @[Parameters.scala 228:27] + _T_2825[0] <= _T_2822 @[Parameters.scala 228:27] + node _T_2830 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2831 = dshl(_T_2830, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_2832 = bits(_T_2831, 7, 0) @[package.scala 19:76] + node _T_2833 = not(_T_2832) @[package.scala 19:40] + node _T_2834 = and(io.in[1].a.bits.address, _T_2833) @[Edges.scala 17:16] + node _T_2836 = eq(_T_2834, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2838 = bits(io.in[1].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_2839 = dshl(UInt<1>("h01"), _T_2838) @[OneHot.scala 49:12] + node _T_2840 = bits(_T_2839, 2, 0) @[OneHot.scala 49:37] + node _T_2842 = geq(io.in[1].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_2844 = bits(_T_2840, 2, 2) @[package.scala 44:26] + node _T_2845 = bits(io.in[1].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_2847 = eq(_T_2845, UInt<1>("h00")) @[package.scala 46:20] + node _T_2848 = and(UInt<1>("h01"), _T_2847) @[package.scala 49:27] + node _T_2849 = and(_T_2844, _T_2848) @[package.scala 50:38] + node _T_2850 = or(_T_2842, _T_2849) @[package.scala 50:29] + node _T_2851 = and(UInt<1>("h01"), _T_2845) @[package.scala 49:27] + node _T_2852 = and(_T_2844, _T_2851) @[package.scala 50:38] + node _T_2853 = or(_T_2842, _T_2852) @[package.scala 50:29] + node _T_2854 = bits(_T_2840, 1, 1) @[package.scala 44:26] + node _T_2855 = bits(io.in[1].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_2857 = eq(_T_2855, UInt<1>("h00")) @[package.scala 46:20] + node _T_2858 = and(_T_2848, _T_2857) @[package.scala 49:27] + node _T_2859 = and(_T_2854, _T_2858) @[package.scala 50:38] + node _T_2860 = or(_T_2850, _T_2859) @[package.scala 50:29] + node _T_2861 = and(_T_2848, _T_2855) @[package.scala 49:27] + node _T_2862 = and(_T_2854, _T_2861) @[package.scala 50:38] + node _T_2863 = or(_T_2850, _T_2862) @[package.scala 50:29] + node _T_2864 = and(_T_2851, _T_2857) @[package.scala 49:27] + node _T_2865 = and(_T_2854, _T_2864) @[package.scala 50:38] + node _T_2866 = or(_T_2853, _T_2865) @[package.scala 50:29] + node _T_2867 = and(_T_2851, _T_2855) @[package.scala 49:27] + node _T_2868 = and(_T_2854, _T_2867) @[package.scala 50:38] + node _T_2869 = or(_T_2853, _T_2868) @[package.scala 50:29] + node _T_2870 = bits(_T_2840, 0, 0) @[package.scala 44:26] + node _T_2871 = bits(io.in[1].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_2873 = eq(_T_2871, UInt<1>("h00")) @[package.scala 46:20] + node _T_2874 = and(_T_2858, _T_2873) @[package.scala 49:27] + node _T_2875 = and(_T_2870, _T_2874) @[package.scala 50:38] + node _T_2876 = or(_T_2860, _T_2875) @[package.scala 50:29] + node _T_2877 = and(_T_2858, _T_2871) @[package.scala 49:27] + node _T_2878 = and(_T_2870, _T_2877) @[package.scala 50:38] + node _T_2879 = or(_T_2860, _T_2878) @[package.scala 50:29] + node _T_2880 = and(_T_2861, _T_2873) @[package.scala 49:27] + node _T_2881 = and(_T_2870, _T_2880) @[package.scala 50:38] + node _T_2882 = or(_T_2863, _T_2881) @[package.scala 50:29] + node _T_2883 = and(_T_2861, _T_2871) @[package.scala 49:27] + node _T_2884 = and(_T_2870, _T_2883) @[package.scala 50:38] + node _T_2885 = or(_T_2863, _T_2884) @[package.scala 50:29] + node _T_2886 = and(_T_2864, _T_2873) @[package.scala 49:27] + node _T_2887 = and(_T_2870, _T_2886) @[package.scala 50:38] + node _T_2888 = or(_T_2866, _T_2887) @[package.scala 50:29] + node _T_2889 = and(_T_2864, _T_2871) @[package.scala 49:27] + node _T_2890 = and(_T_2870, _T_2889) @[package.scala 50:38] + node _T_2891 = or(_T_2866, _T_2890) @[package.scala 50:29] + node _T_2892 = and(_T_2867, _T_2873) @[package.scala 49:27] + node _T_2893 = and(_T_2870, _T_2892) @[package.scala 50:38] + node _T_2894 = or(_T_2869, _T_2893) @[package.scala 50:29] + node _T_2895 = and(_T_2867, _T_2871) @[package.scala 49:27] + node _T_2896 = and(_T_2870, _T_2895) @[package.scala 50:38] + node _T_2897 = or(_T_2869, _T_2896) @[package.scala 50:29] + node _T_2898 = cat(_T_2879, _T_2876) @[Cat.scala 30:58] + node _T_2899 = cat(_T_2885, _T_2882) @[Cat.scala 30:58] + node _T_2900 = cat(_T_2899, _T_2898) @[Cat.scala 30:58] + node _T_2901 = cat(_T_2891, _T_2888) @[Cat.scala 30:58] + node _T_2902 = cat(_T_2897, _T_2894) @[Cat.scala 30:58] + node _T_2903 = cat(_T_2902, _T_2901) @[Cat.scala 30:58] + node _T_2904 = cat(_T_2903, _T_2900) @[Cat.scala 30:58] + node _T_2906 = eq(io.in[1].a.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_2906 : @[RocketTiles.scala 51:21] + node _T_2909 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_2911 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_2912 = and(_T_2909, _T_2911) @[Parameters.scala 63:37] + node _T_2913 = or(UInt<1>("h00"), _T_2912) @[Parameters.scala 132:31] + node _T_2915 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_2916 = cvt(_T_2915) @[Parameters.scala 117:49] + node _T_2918 = and(_T_2916, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_2919 = asSInt(_T_2918) @[Parameters.scala 117:52] + node _T_2921 = eq(_T_2919, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2923 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_2924 = cvt(_T_2923) @[Parameters.scala 117:49] + node _T_2926 = and(_T_2924, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_2927 = asSInt(_T_2926) @[Parameters.scala 117:52] + node _T_2929 = eq(_T_2927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2930 = or(_T_2921, _T_2929) @[Parameters.scala 133:42] + node _T_2931 = and(_T_2913, _T_2930) @[Parameters.scala 132:56] + node _T_2934 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_2936 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_2937 = cvt(_T_2936) @[Parameters.scala 117:49] + node _T_2939 = and(_T_2937, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_2940 = asSInt(_T_2939) @[Parameters.scala 117:52] + node _T_2942 = eq(_T_2940, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2944 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_2945 = cvt(_T_2944) @[Parameters.scala 117:49] + node _T_2947 = and(_T_2945, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_2948 = asSInt(_T_2947) @[Parameters.scala 117:52] + node _T_2950 = eq(_T_2948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2952 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_2953 = cvt(_T_2952) @[Parameters.scala 117:49] + node _T_2955 = and(_T_2953, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_2956 = asSInt(_T_2955) @[Parameters.scala 117:52] + node _T_2958 = eq(_T_2956, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2960 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_2961 = cvt(_T_2960) @[Parameters.scala 117:49] + node _T_2963 = and(_T_2961, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_2964 = asSInt(_T_2963) @[Parameters.scala 117:52] + node _T_2966 = eq(_T_2964, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_2967 = or(_T_2942, _T_2950) @[Parameters.scala 133:42] + node _T_2968 = or(_T_2967, _T_2958) @[Parameters.scala 133:42] + node _T_2969 = or(_T_2968, _T_2966) @[Parameters.scala 133:42] + node _T_2970 = and(_T_2934, _T_2969) @[Parameters.scala 132:56] + node _T_2972 = or(UInt<1>("h00"), _T_2931) @[Parameters.scala 134:30] + node _T_2973 = or(_T_2972, _T_2970) @[Parameters.scala 134:30] + node _T_2974 = or(_T_2973, reset) @[RocketTiles.scala 51:21] + node _T_2976 = eq(_T_2974, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2976 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2977 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_2979 = eq(_T_2977, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2979 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2981 = geq(io.in[1].a.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_2982 = or(_T_2981, reset) @[RocketTiles.scala 51:21] + node _T_2984 = eq(_T_2982, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2984 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2985 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_2987 = eq(_T_2985, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2987 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2989 = leq(io.in[1].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_2990 = or(_T_2989, reset) @[RocketTiles.scala 51:21] + node _T_2992 = eq(_T_2990, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2992 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_2993 = not(io.in[1].a.bits.mask) @[RocketTiles.scala 51:21] + node _T_2995 = eq(_T_2993, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_2996 = or(_T_2995, reset) @[RocketTiles.scala 51:21] + node _T_2998 = eq(_T_2996, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_2998 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3000 = eq(io.in[1].a.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_3000 : @[RocketTiles.scala 51:21] + node _T_3003 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3005 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3006 = and(_T_3003, _T_3005) @[Parameters.scala 63:37] + node _T_3007 = or(UInt<1>("h00"), _T_3006) @[Parameters.scala 132:31] + node _T_3009 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3010 = cvt(_T_3009) @[Parameters.scala 117:49] + node _T_3012 = and(_T_3010, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_3013 = asSInt(_T_3012) @[Parameters.scala 117:52] + node _T_3015 = eq(_T_3013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3017 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3018 = cvt(_T_3017) @[Parameters.scala 117:49] + node _T_3020 = and(_T_3018, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3021 = asSInt(_T_3020) @[Parameters.scala 117:52] + node _T_3023 = eq(_T_3021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3025 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3026 = cvt(_T_3025) @[Parameters.scala 117:49] + node _T_3028 = and(_T_3026, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3029 = asSInt(_T_3028) @[Parameters.scala 117:52] + node _T_3031 = eq(_T_3029, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3033 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3034 = cvt(_T_3033) @[Parameters.scala 117:49] + node _T_3036 = and(_T_3034, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3037 = asSInt(_T_3036) @[Parameters.scala 117:52] + node _T_3039 = eq(_T_3037, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3041 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3042 = cvt(_T_3041) @[Parameters.scala 117:49] + node _T_3044 = and(_T_3042, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3045 = asSInt(_T_3044) @[Parameters.scala 117:52] + node _T_3047 = eq(_T_3045, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3048 = or(_T_3015, _T_3023) @[Parameters.scala 133:42] + node _T_3049 = or(_T_3048, _T_3031) @[Parameters.scala 133:42] + node _T_3050 = or(_T_3049, _T_3039) @[Parameters.scala 133:42] + node _T_3051 = or(_T_3050, _T_3047) @[Parameters.scala 133:42] + node _T_3052 = and(_T_3007, _T_3051) @[Parameters.scala 132:56] + node _T_3055 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3057 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3058 = and(_T_3055, _T_3057) @[Parameters.scala 63:37] + node _T_3059 = or(UInt<1>("h00"), _T_3058) @[Parameters.scala 132:31] + node _T_3061 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3062 = cvt(_T_3061) @[Parameters.scala 117:49] + node _T_3064 = and(_T_3062, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3065 = asSInt(_T_3064) @[Parameters.scala 117:52] + node _T_3067 = eq(_T_3065, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3068 = and(_T_3059, _T_3067) @[Parameters.scala 132:56] + node _T_3070 = or(UInt<1>("h00"), _T_3052) @[Parameters.scala 134:30] + node _T_3071 = or(_T_3070, _T_3068) @[Parameters.scala 134:30] + node _T_3072 = or(_T_3071, reset) @[RocketTiles.scala 51:21] + node _T_3074 = eq(_T_3072, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3074 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3075 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3077 = eq(_T_3075, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3077 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3078 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3080 = eq(_T_3078, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3080 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3082 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3083 = or(_T_3082, reset) @[RocketTiles.scala 51:21] + node _T_3085 = eq(_T_3083, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3085 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3086 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 51:21] + node _T_3087 = or(_T_3086, reset) @[RocketTiles.scala 51:21] + node _T_3089 = eq(_T_3087, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3089 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3091 = eq(io.in[1].a.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3091 : @[RocketTiles.scala 51:21] + node _T_3094 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3096 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3097 = and(_T_3094, _T_3096) @[Parameters.scala 63:37] + node _T_3098 = or(UInt<1>("h00"), _T_3097) @[Parameters.scala 132:31] + node _T_3100 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3101 = cvt(_T_3100) @[Parameters.scala 117:49] + node _T_3103 = and(_T_3101, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3104 = asSInt(_T_3103) @[Parameters.scala 117:52] + node _T_3106 = eq(_T_3104, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3108 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3109 = cvt(_T_3108) @[Parameters.scala 117:49] + node _T_3111 = and(_T_3109, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3112 = asSInt(_T_3111) @[Parameters.scala 117:52] + node _T_3114 = eq(_T_3112, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3116 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3117 = cvt(_T_3116) @[Parameters.scala 117:49] + node _T_3119 = and(_T_3117, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3120 = asSInt(_T_3119) @[Parameters.scala 117:52] + node _T_3122 = eq(_T_3120, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3124 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3125 = cvt(_T_3124) @[Parameters.scala 117:49] + node _T_3127 = and(_T_3125, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3128 = asSInt(_T_3127) @[Parameters.scala 117:52] + node _T_3130 = eq(_T_3128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3132 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3133 = cvt(_T_3132) @[Parameters.scala 117:49] + node _T_3135 = and(_T_3133, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3136 = asSInt(_T_3135) @[Parameters.scala 117:52] + node _T_3138 = eq(_T_3136, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3139 = or(_T_3106, _T_3114) @[Parameters.scala 133:42] + node _T_3140 = or(_T_3139, _T_3122) @[Parameters.scala 133:42] + node _T_3141 = or(_T_3140, _T_3130) @[Parameters.scala 133:42] + node _T_3142 = or(_T_3141, _T_3138) @[Parameters.scala 133:42] + node _T_3143 = and(_T_3098, _T_3142) @[Parameters.scala 132:56] + node _T_3146 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3148 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3149 = and(_T_3146, _T_3148) @[Parameters.scala 63:37] + node _T_3150 = or(UInt<1>("h00"), _T_3149) @[Parameters.scala 132:31] + node _T_3152 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3153 = cvt(_T_3152) @[Parameters.scala 117:49] + node _T_3155 = and(_T_3153, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3156 = asSInt(_T_3155) @[Parameters.scala 117:52] + node _T_3158 = eq(_T_3156, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3159 = and(_T_3150, _T_3158) @[Parameters.scala 132:56] + node _T_3162 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3164 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3165 = cvt(_T_3164) @[Parameters.scala 117:49] + node _T_3167 = and(_T_3165, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3168 = asSInt(_T_3167) @[Parameters.scala 117:52] + node _T_3170 = eq(_T_3168, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3171 = and(_T_3162, _T_3170) @[Parameters.scala 132:56] + node _T_3173 = or(UInt<1>("h00"), _T_3143) @[Parameters.scala 134:30] + node _T_3174 = or(_T_3173, _T_3159) @[Parameters.scala 134:30] + node _T_3175 = or(_T_3174, _T_3171) @[Parameters.scala 134:30] + node _T_3176 = or(_T_3175, reset) @[RocketTiles.scala 51:21] + node _T_3178 = eq(_T_3176, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3178 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3179 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3181 = eq(_T_3179, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3181 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3182 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3184 = eq(_T_3182, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3184 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3186 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3187 = or(_T_3186, reset) @[RocketTiles.scala 51:21] + node _T_3189 = eq(_T_3187, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3189 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3190 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 51:21] + node _T_3191 = or(_T_3190, reset) @[RocketTiles.scala 51:21] + node _T_3193 = eq(_T_3191, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3193 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3195 = eq(io.in[1].a.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_3195 : @[RocketTiles.scala 51:21] + node _T_3198 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3200 = leq(io.in[1].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_3201 = and(_T_3198, _T_3200) @[Parameters.scala 63:37] + node _T_3202 = or(UInt<1>("h00"), _T_3201) @[Parameters.scala 132:31] + node _T_3204 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3205 = cvt(_T_3204) @[Parameters.scala 117:49] + node _T_3207 = and(_T_3205, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3208 = asSInt(_T_3207) @[Parameters.scala 117:52] + node _T_3210 = eq(_T_3208, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3212 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3213 = cvt(_T_3212) @[Parameters.scala 117:49] + node _T_3215 = and(_T_3213, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3216 = asSInt(_T_3215) @[Parameters.scala 117:52] + node _T_3218 = eq(_T_3216, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3220 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3221 = cvt(_T_3220) @[Parameters.scala 117:49] + node _T_3223 = and(_T_3221, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3224 = asSInt(_T_3223) @[Parameters.scala 117:52] + node _T_3226 = eq(_T_3224, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3228 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3229 = cvt(_T_3228) @[Parameters.scala 117:49] + node _T_3231 = and(_T_3229, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3232 = asSInt(_T_3231) @[Parameters.scala 117:52] + node _T_3234 = eq(_T_3232, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3236 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3237 = cvt(_T_3236) @[Parameters.scala 117:49] + node _T_3239 = and(_T_3237, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3240 = asSInt(_T_3239) @[Parameters.scala 117:52] + node _T_3242 = eq(_T_3240, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3243 = or(_T_3210, _T_3218) @[Parameters.scala 133:42] + node _T_3244 = or(_T_3243, _T_3226) @[Parameters.scala 133:42] + node _T_3245 = or(_T_3244, _T_3234) @[Parameters.scala 133:42] + node _T_3246 = or(_T_3245, _T_3242) @[Parameters.scala 133:42] + node _T_3247 = and(_T_3202, _T_3246) @[Parameters.scala 132:56] + node _T_3250 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3252 = leq(io.in[1].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_3253 = and(_T_3250, _T_3252) @[Parameters.scala 63:37] + node _T_3254 = or(UInt<1>("h00"), _T_3253) @[Parameters.scala 132:31] + node _T_3256 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3257 = cvt(_T_3256) @[Parameters.scala 117:49] + node _T_3259 = and(_T_3257, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3260 = asSInt(_T_3259) @[Parameters.scala 117:52] + node _T_3262 = eq(_T_3260, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3263 = and(_T_3254, _T_3262) @[Parameters.scala 132:56] + node _T_3266 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3268 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3269 = cvt(_T_3268) @[Parameters.scala 117:49] + node _T_3271 = and(_T_3269, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3272 = asSInt(_T_3271) @[Parameters.scala 117:52] + node _T_3274 = eq(_T_3272, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3275 = and(_T_3266, _T_3274) @[Parameters.scala 132:56] + node _T_3277 = or(UInt<1>("h00"), _T_3247) @[Parameters.scala 134:30] + node _T_3278 = or(_T_3277, _T_3263) @[Parameters.scala 134:30] + node _T_3279 = or(_T_3278, _T_3275) @[Parameters.scala 134:30] + node _T_3280 = or(_T_3279, reset) @[RocketTiles.scala 51:21] + node _T_3282 = eq(_T_3280, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3282 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3283 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3285 = eq(_T_3283, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3285 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3286 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3288 = eq(_T_3286, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3288 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3290 = eq(io.in[1].a.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3291 = or(_T_3290, reset) @[RocketTiles.scala 51:21] + node _T_3293 = eq(_T_3291, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3293 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3294 = not(_T_2904) @[RocketTiles.scala 51:21] + node _T_3295 = and(io.in[1].a.bits.mask, _T_3294) @[RocketTiles.scala 51:21] + node _T_3297 = eq(_T_3295, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3298 = or(_T_3297, reset) @[RocketTiles.scala 51:21] + node _T_3300 = eq(_T_3298, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3300 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3302 = eq(io.in[1].a.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_3302 : @[RocketTiles.scala 51:21] + node _T_3305 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3307 = leq(io.in[1].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3308 = and(_T_3305, _T_3307) @[Parameters.scala 63:37] + node _T_3309 = or(UInt<1>("h00"), _T_3308) @[Parameters.scala 132:31] + node _T_3311 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3312 = cvt(_T_3311) @[Parameters.scala 117:49] + node _T_3314 = and(_T_3312, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3315 = asSInt(_T_3314) @[Parameters.scala 117:52] + node _T_3317 = eq(_T_3315, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3319 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3320 = cvt(_T_3319) @[Parameters.scala 117:49] + node _T_3322 = and(_T_3320, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3323 = asSInt(_T_3322) @[Parameters.scala 117:52] + node _T_3325 = eq(_T_3323, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3327 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3328 = cvt(_T_3327) @[Parameters.scala 117:49] + node _T_3330 = and(_T_3328, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3331 = asSInt(_T_3330) @[Parameters.scala 117:52] + node _T_3333 = eq(_T_3331, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3334 = or(_T_3317, _T_3325) @[Parameters.scala 133:42] + node _T_3335 = or(_T_3334, _T_3333) @[Parameters.scala 133:42] + node _T_3336 = and(_T_3309, _T_3335) @[Parameters.scala 132:56] + node _T_3339 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3341 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3342 = cvt(_T_3341) @[Parameters.scala 117:49] + node _T_3344 = and(_T_3342, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3345 = asSInt(_T_3344) @[Parameters.scala 117:52] + node _T_3347 = eq(_T_3345, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3349 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3350 = cvt(_T_3349) @[Parameters.scala 117:49] + node _T_3352 = and(_T_3350, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3353 = asSInt(_T_3352) @[Parameters.scala 117:52] + node _T_3355 = eq(_T_3353, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3357 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3358 = cvt(_T_3357) @[Parameters.scala 117:49] + node _T_3360 = and(_T_3358, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3361 = asSInt(_T_3360) @[Parameters.scala 117:52] + node _T_3363 = eq(_T_3361, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3365 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3366 = cvt(_T_3365) @[Parameters.scala 117:49] + node _T_3368 = and(_T_3366, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3369 = asSInt(_T_3368) @[Parameters.scala 117:52] + node _T_3371 = eq(_T_3369, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3372 = or(_T_3347, _T_3355) @[Parameters.scala 133:42] + node _T_3373 = or(_T_3372, _T_3363) @[Parameters.scala 133:42] + node _T_3374 = or(_T_3373, _T_3371) @[Parameters.scala 133:42] + node _T_3375 = and(_T_3339, _T_3374) @[Parameters.scala 132:56] + node _T_3377 = or(UInt<1>("h00"), _T_3336) @[Parameters.scala 134:30] + node _T_3378 = or(_T_3377, _T_3375) @[Parameters.scala 134:30] + node _T_3379 = or(_T_3378, reset) @[RocketTiles.scala 51:21] + node _T_3381 = eq(_T_3379, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3381 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3382 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3384 = eq(_T_3382, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3384 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3385 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3387 = eq(_T_3385, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3387 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3389 = leq(io.in[1].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_3390 = or(_T_3389, reset) @[RocketTiles.scala 51:21] + node _T_3392 = eq(_T_3390, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3392 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3393 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 51:21] + node _T_3394 = or(_T_3393, reset) @[RocketTiles.scala 51:21] + node _T_3396 = eq(_T_3394, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3396 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3398 = eq(io.in[1].a.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 51:21] + when _T_3398 : @[RocketTiles.scala 51:21] + node _T_3401 = leq(UInt<1>("h00"), io.in[1].a.bits.size) @[Parameters.scala 63:32] + node _T_3403 = leq(io.in[1].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_3404 = and(_T_3401, _T_3403) @[Parameters.scala 63:37] + node _T_3405 = or(UInt<1>("h00"), _T_3404) @[Parameters.scala 132:31] + node _T_3407 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3408 = cvt(_T_3407) @[Parameters.scala 117:49] + node _T_3410 = and(_T_3408, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3411 = asSInt(_T_3410) @[Parameters.scala 117:52] + node _T_3413 = eq(_T_3411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3415 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3416 = cvt(_T_3415) @[Parameters.scala 117:49] + node _T_3418 = and(_T_3416, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3419 = asSInt(_T_3418) @[Parameters.scala 117:52] + node _T_3421 = eq(_T_3419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3423 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3424 = cvt(_T_3423) @[Parameters.scala 117:49] + node _T_3426 = and(_T_3424, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3427 = asSInt(_T_3426) @[Parameters.scala 117:52] + node _T_3429 = eq(_T_3427, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3430 = or(_T_3413, _T_3421) @[Parameters.scala 133:42] + node _T_3431 = or(_T_3430, _T_3429) @[Parameters.scala 133:42] + node _T_3432 = and(_T_3405, _T_3431) @[Parameters.scala 132:56] + node _T_3435 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3437 = xor(io.in[1].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3438 = cvt(_T_3437) @[Parameters.scala 117:49] + node _T_3440 = and(_T_3438, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3441 = asSInt(_T_3440) @[Parameters.scala 117:52] + node _T_3443 = eq(_T_3441, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3445 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3446 = cvt(_T_3445) @[Parameters.scala 117:49] + node _T_3448 = and(_T_3446, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3449 = asSInt(_T_3448) @[Parameters.scala 117:52] + node _T_3451 = eq(_T_3449, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3453 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3454 = cvt(_T_3453) @[Parameters.scala 117:49] + node _T_3456 = and(_T_3454, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3457 = asSInt(_T_3456) @[Parameters.scala 117:52] + node _T_3459 = eq(_T_3457, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3461 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3462 = cvt(_T_3461) @[Parameters.scala 117:49] + node _T_3464 = and(_T_3462, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3465 = asSInt(_T_3464) @[Parameters.scala 117:52] + node _T_3467 = eq(_T_3465, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3468 = or(_T_3443, _T_3451) @[Parameters.scala 133:42] + node _T_3469 = or(_T_3468, _T_3459) @[Parameters.scala 133:42] + node _T_3470 = or(_T_3469, _T_3467) @[Parameters.scala 133:42] + node _T_3471 = and(_T_3435, _T_3470) @[Parameters.scala 132:56] + node _T_3473 = or(UInt<1>("h00"), _T_3432) @[Parameters.scala 134:30] + node _T_3474 = or(_T_3473, _T_3471) @[Parameters.scala 134:30] + node _T_3475 = or(_T_3474, reset) @[RocketTiles.scala 51:21] + node _T_3477 = eq(_T_3475, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3477 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3478 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3480 = eq(_T_3478, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3480 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3481 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3483 = eq(_T_3481, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3483 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3485 = leq(io.in[1].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_3486 = or(_T_3485, reset) @[RocketTiles.scala 51:21] + node _T_3488 = eq(_T_3486, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3488 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3489 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 51:21] + node _T_3490 = or(_T_3489, reset) @[RocketTiles.scala 51:21] + node _T_3492 = eq(_T_3490, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3492 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3494 = eq(io.in[1].a.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_3494 : @[RocketTiles.scala 51:21] + node _T_3497 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_3499 = xor(io.in[1].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3500 = cvt(_T_3499) @[Parameters.scala 117:49] + node _T_3502 = and(_T_3500, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_3503 = asSInt(_T_3502) @[Parameters.scala 117:52] + node _T_3505 = eq(_T_3503, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3507 = xor(io.in[1].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3508 = cvt(_T_3507) @[Parameters.scala 117:49] + node _T_3510 = and(_T_3508, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3511 = asSInt(_T_3510) @[Parameters.scala 117:52] + node _T_3513 = eq(_T_3511, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3515 = xor(io.in[1].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3516 = cvt(_T_3515) @[Parameters.scala 117:49] + node _T_3518 = and(_T_3516, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3519 = asSInt(_T_3518) @[Parameters.scala 117:52] + node _T_3521 = eq(_T_3519, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3523 = xor(io.in[1].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3524 = cvt(_T_3523) @[Parameters.scala 117:49] + node _T_3526 = and(_T_3524, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3527 = asSInt(_T_3526) @[Parameters.scala 117:52] + node _T_3529 = eq(_T_3527, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3531 = xor(io.in[1].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3532 = cvt(_T_3531) @[Parameters.scala 117:49] + node _T_3534 = and(_T_3532, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3535 = asSInt(_T_3534) @[Parameters.scala 117:52] + node _T_3537 = eq(_T_3535, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3539 = xor(io.in[1].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3540 = cvt(_T_3539) @[Parameters.scala 117:49] + node _T_3542 = and(_T_3540, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3543 = asSInt(_T_3542) @[Parameters.scala 117:52] + node _T_3545 = eq(_T_3543, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3546 = or(_T_3505, _T_3513) @[Parameters.scala 133:42] + node _T_3547 = or(_T_3546, _T_3521) @[Parameters.scala 133:42] + node _T_3548 = or(_T_3547, _T_3529) @[Parameters.scala 133:42] + node _T_3549 = or(_T_3548, _T_3537) @[Parameters.scala 133:42] + node _T_3550 = or(_T_3549, _T_3545) @[Parameters.scala 133:42] + node _T_3551 = and(_T_3497, _T_3550) @[Parameters.scala 132:56] + node _T_3553 = or(UInt<1>("h00"), _T_3551) @[Parameters.scala 134:30] + node _T_3554 = or(_T_3553, reset) @[RocketTiles.scala 51:21] + node _T_3556 = eq(_T_3554, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3556 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3557 = or(_T_2825[0], reset) @[RocketTiles.scala 51:21] + node _T_3559 = eq(_T_3557, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3559 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3560 = or(_T_2836, reset) @[RocketTiles.scala 51:21] + node _T_3562 = eq(_T_3560, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3562 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3563 = eq(io.in[1].a.bits.mask, _T_2904) @[RocketTiles.scala 51:21] + node _T_3564 = or(_T_3563, reset) @[RocketTiles.scala 51:21] + node _T_3566 = eq(_T_3564, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3566 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[1].b.valid : @[RocketTiles.scala 51:21] + node _T_3568 = leq(io.in[1].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_3569 = or(_T_3568, reset) @[RocketTiles.scala 51:21] + node _T_3571 = eq(_T_3569, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3571 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3573 = xor(io.in[1].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3574 = cvt(_T_3573) @[Parameters.scala 117:49] + node _T_3576 = and(_T_3574, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3577 = asSInt(_T_3576) @[Parameters.scala 117:52] + node _T_3579 = eq(_T_3577, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3581 = xor(io.in[1].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3582 = cvt(_T_3581) @[Parameters.scala 117:49] + node _T_3584 = and(_T_3582, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3585 = asSInt(_T_3584) @[Parameters.scala 117:52] + node _T_3587 = eq(_T_3585, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3589 = xor(io.in[1].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3590 = cvt(_T_3589) @[Parameters.scala 117:49] + node _T_3592 = and(_T_3590, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3593 = asSInt(_T_3592) @[Parameters.scala 117:52] + node _T_3595 = eq(_T_3593, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3597 = xor(io.in[1].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3598 = cvt(_T_3597) @[Parameters.scala 117:49] + node _T_3600 = and(_T_3598, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3601 = asSInt(_T_3600) @[Parameters.scala 117:52] + node _T_3603 = eq(_T_3601, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3605 = xor(io.in[1].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3606 = cvt(_T_3605) @[Parameters.scala 117:49] + node _T_3608 = and(_T_3606, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3609 = asSInt(_T_3608) @[Parameters.scala 117:52] + node _T_3611 = eq(_T_3609, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3613 = xor(io.in[1].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3614 = cvt(_T_3613) @[Parameters.scala 117:49] + node _T_3616 = and(_T_3614, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3617 = asSInt(_T_3616) @[Parameters.scala 117:52] + node _T_3619 = eq(_T_3617, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3621 = xor(io.in[1].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3622 = cvt(_T_3621) @[Parameters.scala 117:49] + node _T_3624 = and(_T_3622, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3625 = asSInt(_T_3624) @[Parameters.scala 117:52] + node _T_3627 = eq(_T_3625, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3630 : UInt<1>[7] @[Parameters.scala 110:36] + _T_3630 is invalid @[Parameters.scala 110:36] + _T_3630[0] <= _T_3579 @[Parameters.scala 110:36] + _T_3630[1] <= _T_3587 @[Parameters.scala 110:36] + _T_3630[2] <= _T_3595 @[Parameters.scala 110:36] + _T_3630[3] <= _T_3603 @[Parameters.scala 110:36] + _T_3630[4] <= _T_3611 @[Parameters.scala 110:36] + _T_3630[5] <= _T_3619 @[Parameters.scala 110:36] + _T_3630[6] <= _T_3627 @[Parameters.scala 110:36] + node _T_3640 = or(_T_3630[0], _T_3630[1]) @[Parameters.scala 119:64] + node _T_3641 = or(_T_3640, _T_3630[2]) @[Parameters.scala 119:64] + node _T_3642 = or(_T_3641, _T_3630[3]) @[Parameters.scala 119:64] + node _T_3643 = or(_T_3642, _T_3630[4]) @[Parameters.scala 119:64] + node _T_3644 = or(_T_3643, _T_3630[5]) @[Parameters.scala 119:64] + node _T_3645 = or(_T_3644, _T_3630[6]) @[Parameters.scala 119:64] + node _T_3647 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_3648 = dshl(_T_3647, io.in[1].b.bits.size) @[package.scala 19:71] + node _T_3649 = bits(_T_3648, 7, 0) @[package.scala 19:76] + node _T_3650 = not(_T_3649) @[package.scala 19:40] + node _T_3651 = and(io.in[1].b.bits.address, _T_3650) @[Edges.scala 17:16] + node _T_3653 = eq(_T_3651, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_3655 = bits(io.in[1].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_3656 = dshl(UInt<1>("h01"), _T_3655) @[OneHot.scala 49:12] + node _T_3657 = bits(_T_3656, 2, 0) @[OneHot.scala 49:37] + node _T_3659 = geq(io.in[1].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_3661 = bits(_T_3657, 2, 2) @[package.scala 44:26] + node _T_3662 = bits(io.in[1].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_3664 = eq(_T_3662, UInt<1>("h00")) @[package.scala 46:20] + node _T_3665 = and(UInt<1>("h01"), _T_3664) @[package.scala 49:27] + node _T_3666 = and(_T_3661, _T_3665) @[package.scala 50:38] + node _T_3667 = or(_T_3659, _T_3666) @[package.scala 50:29] + node _T_3668 = and(UInt<1>("h01"), _T_3662) @[package.scala 49:27] + node _T_3669 = and(_T_3661, _T_3668) @[package.scala 50:38] + node _T_3670 = or(_T_3659, _T_3669) @[package.scala 50:29] + node _T_3671 = bits(_T_3657, 1, 1) @[package.scala 44:26] + node _T_3672 = bits(io.in[1].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_3674 = eq(_T_3672, UInt<1>("h00")) @[package.scala 46:20] + node _T_3675 = and(_T_3665, _T_3674) @[package.scala 49:27] + node _T_3676 = and(_T_3671, _T_3675) @[package.scala 50:38] + node _T_3677 = or(_T_3667, _T_3676) @[package.scala 50:29] + node _T_3678 = and(_T_3665, _T_3672) @[package.scala 49:27] + node _T_3679 = and(_T_3671, _T_3678) @[package.scala 50:38] + node _T_3680 = or(_T_3667, _T_3679) @[package.scala 50:29] + node _T_3681 = and(_T_3668, _T_3674) @[package.scala 49:27] + node _T_3682 = and(_T_3671, _T_3681) @[package.scala 50:38] + node _T_3683 = or(_T_3670, _T_3682) @[package.scala 50:29] + node _T_3684 = and(_T_3668, _T_3672) @[package.scala 49:27] + node _T_3685 = and(_T_3671, _T_3684) @[package.scala 50:38] + node _T_3686 = or(_T_3670, _T_3685) @[package.scala 50:29] + node _T_3687 = bits(_T_3657, 0, 0) @[package.scala 44:26] + node _T_3688 = bits(io.in[1].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_3690 = eq(_T_3688, UInt<1>("h00")) @[package.scala 46:20] + node _T_3691 = and(_T_3675, _T_3690) @[package.scala 49:27] + node _T_3692 = and(_T_3687, _T_3691) @[package.scala 50:38] + node _T_3693 = or(_T_3677, _T_3692) @[package.scala 50:29] + node _T_3694 = and(_T_3675, _T_3688) @[package.scala 49:27] + node _T_3695 = and(_T_3687, _T_3694) @[package.scala 50:38] + node _T_3696 = or(_T_3677, _T_3695) @[package.scala 50:29] + node _T_3697 = and(_T_3678, _T_3690) @[package.scala 49:27] + node _T_3698 = and(_T_3687, _T_3697) @[package.scala 50:38] + node _T_3699 = or(_T_3680, _T_3698) @[package.scala 50:29] + node _T_3700 = and(_T_3678, _T_3688) @[package.scala 49:27] + node _T_3701 = and(_T_3687, _T_3700) @[package.scala 50:38] + node _T_3702 = or(_T_3680, _T_3701) @[package.scala 50:29] + node _T_3703 = and(_T_3681, _T_3690) @[package.scala 49:27] + node _T_3704 = and(_T_3687, _T_3703) @[package.scala 50:38] + node _T_3705 = or(_T_3683, _T_3704) @[package.scala 50:29] + node _T_3706 = and(_T_3681, _T_3688) @[package.scala 49:27] + node _T_3707 = and(_T_3687, _T_3706) @[package.scala 50:38] + node _T_3708 = or(_T_3683, _T_3707) @[package.scala 50:29] + node _T_3709 = and(_T_3684, _T_3690) @[package.scala 49:27] + node _T_3710 = and(_T_3687, _T_3709) @[package.scala 50:38] + node _T_3711 = or(_T_3686, _T_3710) @[package.scala 50:29] + node _T_3712 = and(_T_3684, _T_3688) @[package.scala 49:27] + node _T_3713 = and(_T_3687, _T_3712) @[package.scala 50:38] + node _T_3714 = or(_T_3686, _T_3713) @[package.scala 50:29] + node _T_3715 = cat(_T_3696, _T_3693) @[Cat.scala 30:58] + node _T_3716 = cat(_T_3702, _T_3699) @[Cat.scala 30:58] + node _T_3717 = cat(_T_3716, _T_3715) @[Cat.scala 30:58] + node _T_3718 = cat(_T_3708, _T_3705) @[Cat.scala 30:58] + node _T_3719 = cat(_T_3714, _T_3711) @[Cat.scala 30:58] + node _T_3720 = cat(_T_3719, _T_3718) @[Cat.scala 30:58] + node _T_3721 = cat(_T_3720, _T_3717) @[Cat.scala 30:58] + node _T_3723 = eq(io.in[1].b.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_3723 : @[RocketTiles.scala 51:21] + node _T_3725 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3727 = eq(_T_3725, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3727 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3728 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3730 = eq(_T_3728, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3730 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3732 = geq(io.in[1].b.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_3733 = or(_T_3732, reset) @[RocketTiles.scala 51:21] + node _T_3735 = eq(_T_3733, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3735 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3736 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3738 = eq(_T_3736, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3738 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3740 = leq(io.in[1].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_3741 = or(_T_3740, reset) @[RocketTiles.scala 51:21] + node _T_3743 = eq(_T_3741, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3743 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3744 = not(io.in[1].b.bits.mask) @[RocketTiles.scala 51:21] + node _T_3746 = eq(_T_3744, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3747 = or(_T_3746, reset) @[RocketTiles.scala 51:21] + node _T_3749 = eq(_T_3747, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3749 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3751 = eq(io.in[1].b.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_3751 : @[RocketTiles.scala 51:21] + node _T_3753 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3755 = eq(_T_3753, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3755 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3756 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3758 = eq(_T_3756, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3758 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3759 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3761 = eq(_T_3759, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3761 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3763 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3764 = or(_T_3763, reset) @[RocketTiles.scala 51:21] + node _T_3766 = eq(_T_3764, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3766 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3767 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 51:21] + node _T_3768 = or(_T_3767, reset) @[RocketTiles.scala 51:21] + node _T_3770 = eq(_T_3768, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3770 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3772 = eq(io.in[1].b.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3772 : @[RocketTiles.scala 51:21] + node _T_3774 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3776 = eq(_T_3774, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3776 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3777 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3779 = eq(_T_3777, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3779 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3780 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3782 = eq(_T_3780, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3782 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3784 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3785 = or(_T_3784, reset) @[RocketTiles.scala 51:21] + node _T_3787 = eq(_T_3785, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3787 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3788 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 51:21] + node _T_3789 = or(_T_3788, reset) @[RocketTiles.scala 51:21] + node _T_3791 = eq(_T_3789, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3791 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3793 = eq(io.in[1].b.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_3793 : @[RocketTiles.scala 51:21] + node _T_3795 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3797 = eq(_T_3795, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3797 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3798 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3800 = eq(_T_3798, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3800 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3801 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3803 = eq(_T_3801, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3803 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3805 = eq(io.in[1].b.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3806 = or(_T_3805, reset) @[RocketTiles.scala 51:21] + node _T_3808 = eq(_T_3806, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3808 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3809 = not(_T_3721) @[RocketTiles.scala 51:21] + node _T_3810 = and(io.in[1].b.bits.mask, _T_3809) @[RocketTiles.scala 51:21] + node _T_3812 = eq(_T_3810, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3813 = or(_T_3812, reset) @[RocketTiles.scala 51:21] + node _T_3815 = eq(_T_3813, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3815 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3817 = eq(io.in[1].b.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_3817 : @[RocketTiles.scala 51:21] + node _T_3819 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3821 = eq(_T_3819, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3821 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3822 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3824 = eq(_T_3822, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3824 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3825 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3827 = eq(_T_3825, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3827 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3829 = leq(io.in[1].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_3830 = or(_T_3829, reset) @[RocketTiles.scala 51:21] + node _T_3832 = eq(_T_3830, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3832 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3833 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 51:21] + node _T_3834 = or(_T_3833, reset) @[RocketTiles.scala 51:21] + node _T_3836 = eq(_T_3834, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3836 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3838 = eq(io.in[1].b.bits.opcode, UInt<2>("h03")) @[RocketTiles.scala 51:21] + when _T_3838 : @[RocketTiles.scala 51:21] + node _T_3840 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3842 = eq(_T_3840, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3842 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3843 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3845 = eq(_T_3843, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3845 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3846 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3848 = eq(_T_3846, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3848 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3850 = leq(io.in[1].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_3851 = or(_T_3850, reset) @[RocketTiles.scala 51:21] + node _T_3853 = eq(_T_3851, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3853 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3854 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 51:21] + node _T_3855 = or(_T_3854, reset) @[RocketTiles.scala 51:21] + node _T_3857 = eq(_T_3855, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3857 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3859 = eq(io.in[1].b.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_3859 : @[RocketTiles.scala 51:21] + node _T_3861 = or(UInt<1>("h00"), reset) @[RocketTiles.scala 51:21] + node _T_3863 = eq(_T_3861, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3863 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketTiles.scala:51:21)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3864 = or(_T_3645, reset) @[RocketTiles.scala 51:21] + node _T_3866 = eq(_T_3864, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3866 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3867 = or(_T_3653, reset) @[RocketTiles.scala 51:21] + node _T_3869 = eq(_T_3867, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3869 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3870 = eq(io.in[1].b.bits.mask, _T_3721) @[RocketTiles.scala 51:21] + node _T_3871 = or(_T_3870, reset) @[RocketTiles.scala 51:21] + node _T_3873 = eq(_T_3871, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3873 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketTiles.scala:51:21)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[1].c.valid : @[RocketTiles.scala 51:21] + node _T_3875 = leq(io.in[1].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_3876 = or(_T_3875, reset) @[RocketTiles.scala 51:21] + node _T_3878 = eq(_T_3876, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3878 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3880 = eq(UInt<1>("h00"), io.in[1].c.bits.source) @[Parameters.scala 35:39] + wire _T_3883 : UInt<1>[1] @[Parameters.scala 228:27] + _T_3883 is invalid @[Parameters.scala 228:27] + _T_3883[0] <= _T_3880 @[Parameters.scala 228:27] + node _T_3888 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_3889 = dshl(_T_3888, io.in[1].c.bits.size) @[package.scala 19:71] + node _T_3890 = bits(_T_3889, 7, 0) @[package.scala 19:76] + node _T_3891 = not(_T_3890) @[package.scala 19:40] + node _T_3892 = and(io.in[1].c.bits.address, _T_3891) @[Edges.scala 17:16] + node _T_3894 = eq(_T_3892, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_3896 = xor(io.in[1].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_3897 = cvt(_T_3896) @[Parameters.scala 117:49] + node _T_3899 = and(_T_3897, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3900 = asSInt(_T_3899) @[Parameters.scala 117:52] + node _T_3902 = eq(_T_3900, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3904 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_3905 = cvt(_T_3904) @[Parameters.scala 117:49] + node _T_3907 = and(_T_3905, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_3908 = asSInt(_T_3907) @[Parameters.scala 117:52] + node _T_3910 = eq(_T_3908, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3912 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_3913 = cvt(_T_3912) @[Parameters.scala 117:49] + node _T_3915 = and(_T_3913, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_3916 = asSInt(_T_3915) @[Parameters.scala 117:52] + node _T_3918 = eq(_T_3916, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3920 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_3921 = cvt(_T_3920) @[Parameters.scala 117:49] + node _T_3923 = and(_T_3921, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_3924 = asSInt(_T_3923) @[Parameters.scala 117:52] + node _T_3926 = eq(_T_3924, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3928 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_3929 = cvt(_T_3928) @[Parameters.scala 117:49] + node _T_3931 = and(_T_3929, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_3932 = asSInt(_T_3931) @[Parameters.scala 117:52] + node _T_3934 = eq(_T_3932, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3936 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_3937 = cvt(_T_3936) @[Parameters.scala 117:49] + node _T_3939 = and(_T_3937, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_3940 = asSInt(_T_3939) @[Parameters.scala 117:52] + node _T_3942 = eq(_T_3940, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_3944 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_3945 = cvt(_T_3944) @[Parameters.scala 117:49] + node _T_3947 = and(_T_3945, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_3948 = asSInt(_T_3947) @[Parameters.scala 117:52] + node _T_3950 = eq(_T_3948, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_3953 : UInt<1>[7] @[Parameters.scala 110:36] + _T_3953 is invalid @[Parameters.scala 110:36] + _T_3953[0] <= _T_3902 @[Parameters.scala 110:36] + _T_3953[1] <= _T_3910 @[Parameters.scala 110:36] + _T_3953[2] <= _T_3918 @[Parameters.scala 110:36] + _T_3953[3] <= _T_3926 @[Parameters.scala 110:36] + _T_3953[4] <= _T_3934 @[Parameters.scala 110:36] + _T_3953[5] <= _T_3942 @[Parameters.scala 110:36] + _T_3953[6] <= _T_3950 @[Parameters.scala 110:36] + node _T_3963 = or(_T_3953[0], _T_3953[1]) @[Parameters.scala 119:64] + node _T_3964 = or(_T_3963, _T_3953[2]) @[Parameters.scala 119:64] + node _T_3965 = or(_T_3964, _T_3953[3]) @[Parameters.scala 119:64] + node _T_3966 = or(_T_3965, _T_3953[4]) @[Parameters.scala 119:64] + node _T_3967 = or(_T_3966, _T_3953[5]) @[Parameters.scala 119:64] + node _T_3968 = or(_T_3967, _T_3953[6]) @[Parameters.scala 119:64] + node _T_3970 = eq(io.in[1].c.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_3970 : @[RocketTiles.scala 51:21] + node _T_3971 = or(_T_3968, reset) @[RocketTiles.scala 51:21] + node _T_3973 = eq(_T_3971, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3973 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3974 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_3976 = eq(_T_3974, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3976 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3978 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_3979 = or(_T_3978, reset) @[RocketTiles.scala 51:21] + node _T_3981 = eq(_T_3979, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3981 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3982 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_3984 = eq(_T_3982, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3984 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3986 = leq(io.in[1].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_3987 = or(_T_3986, reset) @[RocketTiles.scala 51:21] + node _T_3989 = eq(_T_3987, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3989 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3991 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_3992 = or(_T_3991, reset) @[RocketTiles.scala 51:21] + node _T_3994 = eq(_T_3992, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3994 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_3996 = eq(io.in[1].c.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_3996 : @[RocketTiles.scala 51:21] + node _T_3997 = or(_T_3968, reset) @[RocketTiles.scala 51:21] + node _T_3999 = eq(_T_3997, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_3999 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4000 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4002 = eq(_T_4000, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4002 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4004 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4005 = or(_T_4004, reset) @[RocketTiles.scala 51:21] + node _T_4007 = eq(_T_4005, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4007 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4008 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4010 = eq(_T_4008, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4010 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4012 = leq(io.in[1].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_4013 = or(_T_4012, reset) @[RocketTiles.scala 51:21] + node _T_4015 = eq(_T_4013, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4015 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4017 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4018 = or(_T_4017, reset) @[RocketTiles.scala 51:21] + node _T_4020 = eq(_T_4018, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4020 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4022 = eq(io.in[1].c.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_4022 : @[RocketTiles.scala 51:21] + node _T_4025 = leq(UInt<1>("h00"), io.in[1].c.bits.size) @[Parameters.scala 63:32] + node _T_4027 = leq(io.in[1].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_4028 = and(_T_4025, _T_4027) @[Parameters.scala 63:37] + node _T_4029 = or(UInt<1>("h00"), _T_4028) @[Parameters.scala 132:31] + node _T_4031 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_4032 = cvt(_T_4031) @[Parameters.scala 117:49] + node _T_4034 = and(_T_4032, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_4035 = asSInt(_T_4034) @[Parameters.scala 117:52] + node _T_4037 = eq(_T_4035, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4039 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_4040 = cvt(_T_4039) @[Parameters.scala 117:49] + node _T_4042 = and(_T_4040, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_4043 = asSInt(_T_4042) @[Parameters.scala 117:52] + node _T_4045 = eq(_T_4043, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4046 = or(_T_4037, _T_4045) @[Parameters.scala 133:42] + node _T_4047 = and(_T_4029, _T_4046) @[Parameters.scala 132:56] + node _T_4050 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_4052 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4053 = cvt(_T_4052) @[Parameters.scala 117:49] + node _T_4055 = and(_T_4053, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_4056 = asSInt(_T_4055) @[Parameters.scala 117:52] + node _T_4058 = eq(_T_4056, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4060 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4061 = cvt(_T_4060) @[Parameters.scala 117:49] + node _T_4063 = and(_T_4061, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_4064 = asSInt(_T_4063) @[Parameters.scala 117:52] + node _T_4066 = eq(_T_4064, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4068 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_4069 = cvt(_T_4068) @[Parameters.scala 117:49] + node _T_4071 = and(_T_4069, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_4072 = asSInt(_T_4071) @[Parameters.scala 117:52] + node _T_4074 = eq(_T_4072, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4076 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_4077 = cvt(_T_4076) @[Parameters.scala 117:49] + node _T_4079 = and(_T_4077, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_4080 = asSInt(_T_4079) @[Parameters.scala 117:52] + node _T_4082 = eq(_T_4080, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4083 = or(_T_4058, _T_4066) @[Parameters.scala 133:42] + node _T_4084 = or(_T_4083, _T_4074) @[Parameters.scala 133:42] + node _T_4085 = or(_T_4084, _T_4082) @[Parameters.scala 133:42] + node _T_4086 = and(_T_4050, _T_4085) @[Parameters.scala 132:56] + node _T_4088 = or(UInt<1>("h00"), _T_4047) @[Parameters.scala 134:30] + node _T_4089 = or(_T_4088, _T_4086) @[Parameters.scala 134:30] + node _T_4090 = or(_T_4089, reset) @[RocketTiles.scala 51:21] + node _T_4092 = eq(_T_4090, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4092 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4093 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4095 = eq(_T_4093, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4095 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4097 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4098 = or(_T_4097, reset) @[RocketTiles.scala 51:21] + node _T_4100 = eq(_T_4098, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4100 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4101 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4103 = eq(_T_4101, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4103 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4105 = leq(io.in[1].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_4106 = or(_T_4105, reset) @[RocketTiles.scala 51:21] + node _T_4108 = eq(_T_4106, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4108 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4110 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4111 = or(_T_4110, reset) @[RocketTiles.scala 51:21] + node _T_4113 = eq(_T_4111, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4113 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4115 = eq(io.in[1].c.bits.opcode, UInt<3>("h07")) @[RocketTiles.scala 51:21] + when _T_4115 : @[RocketTiles.scala 51:21] + node _T_4118 = leq(UInt<1>("h00"), io.in[1].c.bits.size) @[Parameters.scala 63:32] + node _T_4120 = leq(io.in[1].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_4121 = and(_T_4118, _T_4120) @[Parameters.scala 63:37] + node _T_4122 = or(UInt<1>("h00"), _T_4121) @[Parameters.scala 132:31] + node _T_4124 = xor(io.in[1].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_4125 = cvt(_T_4124) @[Parameters.scala 117:49] + node _T_4127 = and(_T_4125, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_4128 = asSInt(_T_4127) @[Parameters.scala 117:52] + node _T_4130 = eq(_T_4128, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4132 = xor(io.in[1].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_4133 = cvt(_T_4132) @[Parameters.scala 117:49] + node _T_4135 = and(_T_4133, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_4136 = asSInt(_T_4135) @[Parameters.scala 117:52] + node _T_4138 = eq(_T_4136, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4139 = or(_T_4130, _T_4138) @[Parameters.scala 133:42] + node _T_4140 = and(_T_4122, _T_4139) @[Parameters.scala 132:56] + node _T_4143 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_4145 = xor(io.in[1].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_4146 = cvt(_T_4145) @[Parameters.scala 117:49] + node _T_4148 = and(_T_4146, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_4149 = asSInt(_T_4148) @[Parameters.scala 117:52] + node _T_4151 = eq(_T_4149, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4153 = xor(io.in[1].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_4154 = cvt(_T_4153) @[Parameters.scala 117:49] + node _T_4156 = and(_T_4154, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_4157 = asSInt(_T_4156) @[Parameters.scala 117:52] + node _T_4159 = eq(_T_4157, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4161 = xor(io.in[1].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_4162 = cvt(_T_4161) @[Parameters.scala 117:49] + node _T_4164 = and(_T_4162, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_4165 = asSInt(_T_4164) @[Parameters.scala 117:52] + node _T_4167 = eq(_T_4165, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4169 = xor(io.in[1].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_4170 = cvt(_T_4169) @[Parameters.scala 117:49] + node _T_4172 = and(_T_4170, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_4173 = asSInt(_T_4172) @[Parameters.scala 117:52] + node _T_4175 = eq(_T_4173, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_4176 = or(_T_4151, _T_4159) @[Parameters.scala 133:42] + node _T_4177 = or(_T_4176, _T_4167) @[Parameters.scala 133:42] + node _T_4178 = or(_T_4177, _T_4175) @[Parameters.scala 133:42] + node _T_4179 = and(_T_4143, _T_4178) @[Parameters.scala 132:56] + node _T_4181 = or(UInt<1>("h00"), _T_4140) @[Parameters.scala 134:30] + node _T_4182 = or(_T_4181, _T_4179) @[Parameters.scala 134:30] + node _T_4183 = or(_T_4182, reset) @[RocketTiles.scala 51:21] + node _T_4185 = eq(_T_4183, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4185 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketTiles.scala:51:21)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4186 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4188 = eq(_T_4186, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4188 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4190 = geq(io.in[1].c.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4191 = or(_T_4190, reset) @[RocketTiles.scala 51:21] + node _T_4193 = eq(_T_4191, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4193 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4194 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4196 = eq(_T_4194, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4196 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4198 = leq(io.in[1].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_4199 = or(_T_4198, reset) @[RocketTiles.scala 51:21] + node _T_4201 = eq(_T_4199, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4201 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4203 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4204 = or(_T_4203, reset) @[RocketTiles.scala 51:21] + node _T_4206 = eq(_T_4204, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4206 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4208 = eq(io.in[1].c.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4208 : @[RocketTiles.scala 51:21] + node _T_4209 = or(_T_3968, reset) @[RocketTiles.scala 51:21] + node _T_4211 = eq(_T_4209, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4211 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4212 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4214 = eq(_T_4212, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4214 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4215 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4217 = eq(_T_4215, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4217 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4219 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4220 = or(_T_4219, reset) @[RocketTiles.scala 51:21] + node _T_4222 = eq(_T_4220, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4222 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4224 = eq(io.in[1].c.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_4224 : @[RocketTiles.scala 51:21] + node _T_4225 = or(_T_3968, reset) @[RocketTiles.scala 51:21] + node _T_4227 = eq(_T_4225, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4227 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4228 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4230 = eq(_T_4228, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4230 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4231 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4233 = eq(_T_4231, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4233 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4235 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4236 = or(_T_4235, reset) @[RocketTiles.scala 51:21] + node _T_4238 = eq(_T_4236, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4238 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4240 = eq(io.in[1].c.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_4240 : @[RocketTiles.scala 51:21] + node _T_4241 = or(_T_3968, reset) @[RocketTiles.scala 51:21] + node _T_4243 = eq(_T_4241, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4243 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketTiles.scala:51:21)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4244 = or(_T_3883[0], reset) @[RocketTiles.scala 51:21] + node _T_4246 = eq(_T_4244, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4246 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4247 = or(_T_3894, reset) @[RocketTiles.scala 51:21] + node _T_4249 = eq(_T_4247, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4249 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4251 = eq(io.in[1].c.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4252 = or(_T_4251, reset) @[RocketTiles.scala 51:21] + node _T_4254 = eq(_T_4252, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4254 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4256 = eq(io.in[1].c.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4257 = or(_T_4256, reset) @[RocketTiles.scala 51:21] + node _T_4259 = eq(_T_4257, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4259 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[1].d.valid : @[RocketTiles.scala 51:21] + node _T_4261 = leq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_4262 = or(_T_4261, reset) @[RocketTiles.scala 51:21] + node _T_4264 = eq(_T_4262, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4264 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketTiles.scala:51:21)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4266 = eq(UInt<1>("h00"), io.in[1].d.bits.source) @[Parameters.scala 35:39] + wire _T_4269 : UInt<1>[1] @[Parameters.scala 228:27] + _T_4269 is invalid @[Parameters.scala 228:27] + _T_4269[0] <= _T_4266 @[Parameters.scala 228:27] + node _T_4274 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4275 = dshl(_T_4274, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4276 = bits(_T_4275, 7, 0) @[package.scala 19:76] + node _T_4277 = not(_T_4276) @[package.scala 19:40] + node _T_4278 = and(io.in[1].d.bits.addr_lo, _T_4277) @[Edges.scala 17:16] + node _T_4280 = eq(_T_4278, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_4282 = lt(io.in[1].d.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 51:21] + node _T_4284 = eq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + when _T_4284 : @[RocketTiles.scala 51:21] + node _T_4285 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4287 = eq(_T_4285, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4287 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4288 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4290 = eq(_T_4288, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4290 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4291 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4293 = eq(_T_4291, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4293 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4295 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4296 = or(_T_4295, reset) @[RocketTiles.scala 51:21] + node _T_4298 = eq(_T_4296, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4298 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4300 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4301 = or(_T_4300, reset) @[RocketTiles.scala 51:21] + node _T_4303 = eq(_T_4301, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4303 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4305 = eq(io.in[1].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4306 = or(_T_4305, reset) @[RocketTiles.scala 51:21] + node _T_4308 = eq(_T_4306, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4308 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4310 = eq(io.in[1].d.bits.opcode, UInt<3>("h04")) @[RocketTiles.scala 51:21] + when _T_4310 : @[RocketTiles.scala 51:21] + node _T_4311 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4313 = eq(_T_4311, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4313 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4314 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4316 = eq(_T_4314, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4316 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4317 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4319 = eq(_T_4317, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4319 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4321 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4322 = or(_T_4321, reset) @[RocketTiles.scala 51:21] + node _T_4324 = eq(_T_4322, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4324 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4326 = leq(io.in[1].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_4327 = or(_T_4326, reset) @[RocketTiles.scala 51:21] + node _T_4329 = eq(_T_4327, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4329 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4331 = eq(io.in[1].d.bits.opcode, UInt<3>("h05")) @[RocketTiles.scala 51:21] + when _T_4331 : @[RocketTiles.scala 51:21] + node _T_4332 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4334 = eq(_T_4332, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4334 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4335 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4337 = eq(_T_4335, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4337 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4338 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4340 = eq(_T_4338, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4340 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4342 = geq(io.in[1].d.bits.size, UInt<2>("h03")) @[RocketTiles.scala 51:21] + node _T_4343 = or(_T_4342, reset) @[RocketTiles.scala 51:21] + node _T_4345 = eq(_T_4343, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4345 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketTiles.scala:51:21)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4347 = leq(io.in[1].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_4348 = or(_T_4347, reset) @[RocketTiles.scala 51:21] + node _T_4350 = eq(_T_4348, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4350 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4352 = eq(io.in[1].d.bits.opcode, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4352 : @[RocketTiles.scala 51:21] + node _T_4353 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4355 = eq(_T_4353, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4355 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4356 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4358 = eq(_T_4356, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4358 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4359 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4361 = eq(_T_4359, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4361 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4363 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4364 = or(_T_4363, reset) @[RocketTiles.scala 51:21] + node _T_4366 = eq(_T_4364, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4366 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4368 = eq(io.in[1].d.bits.opcode, UInt<1>("h01")) @[RocketTiles.scala 51:21] + when _T_4368 : @[RocketTiles.scala 51:21] + node _T_4369 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4371 = eq(_T_4369, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4371 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4372 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4374 = eq(_T_4372, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4374 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4375 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4377 = eq(_T_4375, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4377 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4379 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4380 = or(_T_4379, reset) @[RocketTiles.scala 51:21] + node _T_4382 = eq(_T_4380, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4382 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4384 = eq(io.in[1].d.bits.opcode, UInt<2>("h02")) @[RocketTiles.scala 51:21] + when _T_4384 : @[RocketTiles.scala 51:21] + node _T_4385 = or(_T_4269[0], reset) @[RocketTiles.scala 51:21] + node _T_4387 = eq(_T_4385, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4387 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4388 = or(_T_4280, reset) @[RocketTiles.scala 51:21] + node _T_4390 = eq(_T_4388, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4390 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketTiles.scala:51:21)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4391 = or(_T_4282, reset) @[RocketTiles.scala 51:21] + node _T_4393 = eq(_T_4391, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4393 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4395 = eq(io.in[1].d.bits.param, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4396 = or(_T_4395, reset) @[RocketTiles.scala 51:21] + node _T_4398 = eq(_T_4396, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4398 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketTiles.scala:51:21)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4400 = eq(io.in[1].d.bits.error, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4401 = or(_T_4400, reset) @[RocketTiles.scala 51:21] + node _T_4403 = eq(_T_4401, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4403 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketTiles.scala:51:21)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + when io.in[1].e.valid : @[RocketTiles.scala 51:21] + node _T_4405 = lt(io.in[1].e.bits.sink, UInt<4>("h0a")) @[RocketTiles.scala 51:21] + node _T_4406 = or(_T_4405, reset) @[RocketTiles.scala 51:21] + node _T_4408 = eq(_T_4406, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4408 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4409 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4411 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4412 = dshl(_T_4411, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_4413 = bits(_T_4412, 7, 0) @[package.scala 19:76] + node _T_4414 = not(_T_4413) @[package.scala 19:40] + node _T_4415 = shr(_T_4414, 3) @[Edges.scala 198:59] + node _T_4416 = bits(io.in[1].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4418 = eq(_T_4416, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4420 = mux(_T_4418, _T_4415, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4422 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4424 = sub(_T_4422, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4425 = asUInt(_T_4424) @[Edges.scala 208:28] + node _T_4426 = tail(_T_4425, 1) @[Edges.scala 208:28] + node _T_4428 = eq(_T_4422, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4430 = eq(_T_4422, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4432 = eq(_T_4420, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4433 = or(_T_4430, _T_4432) @[Edges.scala 210:37] + node _T_4434 = and(_T_4433, _T_4409) @[Edges.scala 211:22] + node _T_4435 = not(_T_4426) @[Edges.scala 212:27] + node _T_4436 = and(_T_4420, _T_4435) @[Edges.scala 212:25] + when _T_4409 : @[Edges.scala 213:17] + node _T_4437 = mux(_T_4428, _T_4420, _T_4426) @[Edges.scala 214:21] + _T_4422 <= _T_4437 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4439 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4441 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4443 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4445 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4447 : UInt, clock @[RocketTiles.scala 51:21] + node _T_4449 = eq(_T_4428, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4450 = and(io.in[1].a.valid, _T_4449) @[RocketTiles.scala 51:21] + when _T_4450 : @[RocketTiles.scala 51:21] + node _T_4451 = eq(io.in[1].a.bits.opcode, _T_4439) @[RocketTiles.scala 51:21] + node _T_4452 = or(_T_4451, reset) @[RocketTiles.scala 51:21] + node _T_4454 = eq(_T_4452, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4454 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4455 = eq(io.in[1].a.bits.param, _T_4441) @[RocketTiles.scala 51:21] + node _T_4456 = or(_T_4455, reset) @[RocketTiles.scala 51:21] + node _T_4458 = eq(_T_4456, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4458 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4459 = eq(io.in[1].a.bits.size, _T_4443) @[RocketTiles.scala 51:21] + node _T_4460 = or(_T_4459, reset) @[RocketTiles.scala 51:21] + node _T_4462 = eq(_T_4460, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4462 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4463 = eq(io.in[1].a.bits.source, _T_4445) @[RocketTiles.scala 51:21] + node _T_4464 = or(_T_4463, reset) @[RocketTiles.scala 51:21] + node _T_4466 = eq(_T_4464, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4466 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4467 = eq(io.in[1].a.bits.address, _T_4447) @[RocketTiles.scala 51:21] + node _T_4468 = or(_T_4467, reset) @[RocketTiles.scala 51:21] + node _T_4470 = eq(_T_4468, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4470 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4471 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4472 = and(_T_4471, _T_4428) @[RocketTiles.scala 51:21] + when _T_4472 : @[RocketTiles.scala 51:21] + _T_4439 <= io.in[1].a.bits.opcode @[RocketTiles.scala 51:21] + _T_4441 <= io.in[1].a.bits.param @[RocketTiles.scala 51:21] + _T_4443 <= io.in[1].a.bits.size @[RocketTiles.scala 51:21] + _T_4445 <= io.in[1].a.bits.source @[RocketTiles.scala 51:21] + _T_4447 <= io.in[1].a.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4473 = and(io.in[1].b.ready, io.in[1].b.valid) @[Bundles.scala 207:36] + node _T_4475 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4476 = dshl(_T_4475, io.in[1].b.bits.size) @[package.scala 19:71] + node _T_4477 = bits(_T_4476, 7, 0) @[package.scala 19:76] + node _T_4478 = not(_T_4477) @[package.scala 19:40] + node _T_4479 = shr(_T_4478, 3) @[Edges.scala 198:59] + node _T_4480 = bits(io.in[1].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_4482 = eq(_T_4480, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_4485 = mux(UInt<1>("h00"), _T_4479, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4487 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4489 = sub(_T_4487, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4490 = asUInt(_T_4489) @[Edges.scala 208:28] + node _T_4491 = tail(_T_4490, 1) @[Edges.scala 208:28] + node _T_4493 = eq(_T_4487, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4495 = eq(_T_4487, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4497 = eq(_T_4485, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4498 = or(_T_4495, _T_4497) @[Edges.scala 210:37] + node _T_4499 = and(_T_4498, _T_4473) @[Edges.scala 211:22] + node _T_4500 = not(_T_4491) @[Edges.scala 212:27] + node _T_4501 = and(_T_4485, _T_4500) @[Edges.scala 212:25] + when _T_4473 : @[Edges.scala 213:17] + node _T_4502 = mux(_T_4493, _T_4485, _T_4491) @[Edges.scala 214:21] + _T_4487 <= _T_4502 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4504 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4506 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4508 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4510 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4512 : UInt, clock @[RocketTiles.scala 51:21] + node _T_4514 = eq(_T_4493, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4515 = and(io.in[1].b.valid, _T_4514) @[RocketTiles.scala 51:21] + when _T_4515 : @[RocketTiles.scala 51:21] + node _T_4516 = eq(io.in[1].b.bits.opcode, _T_4504) @[RocketTiles.scala 51:21] + node _T_4517 = or(_T_4516, reset) @[RocketTiles.scala 51:21] + node _T_4519 = eq(_T_4517, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4519 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4520 = eq(io.in[1].b.bits.param, _T_4506) @[RocketTiles.scala 51:21] + node _T_4521 = or(_T_4520, reset) @[RocketTiles.scala 51:21] + node _T_4523 = eq(_T_4521, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4523 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4524 = eq(io.in[1].b.bits.size, _T_4508) @[RocketTiles.scala 51:21] + node _T_4525 = or(_T_4524, reset) @[RocketTiles.scala 51:21] + node _T_4527 = eq(_T_4525, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4527 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4528 = eq(io.in[1].b.bits.source, _T_4510) @[RocketTiles.scala 51:21] + node _T_4529 = or(_T_4528, reset) @[RocketTiles.scala 51:21] + node _T_4531 = eq(_T_4529, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4531 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4532 = eq(io.in[1].b.bits.address, _T_4512) @[RocketTiles.scala 51:21] + node _T_4533 = or(_T_4532, reset) @[RocketTiles.scala 51:21] + node _T_4535 = eq(_T_4533, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4535 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4536 = and(io.in[1].b.ready, io.in[1].b.valid) @[Bundles.scala 207:36] + node _T_4537 = and(_T_4536, _T_4493) @[RocketTiles.scala 51:21] + when _T_4537 : @[RocketTiles.scala 51:21] + _T_4504 <= io.in[1].b.bits.opcode @[RocketTiles.scala 51:21] + _T_4506 <= io.in[1].b.bits.param @[RocketTiles.scala 51:21] + _T_4508 <= io.in[1].b.bits.size @[RocketTiles.scala 51:21] + _T_4510 <= io.in[1].b.bits.source @[RocketTiles.scala 51:21] + _T_4512 <= io.in[1].b.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4538 = and(io.in[1].c.ready, io.in[1].c.valid) @[Bundles.scala 207:36] + node _T_4540 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4541 = dshl(_T_4540, io.in[1].c.bits.size) @[package.scala 19:71] + node _T_4542 = bits(_T_4541, 7, 0) @[package.scala 19:76] + node _T_4543 = not(_T_4542) @[package.scala 19:40] + node _T_4544 = shr(_T_4543, 3) @[Edges.scala 198:59] + node _T_4545 = bits(io.in[1].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_4548 = mux(UInt<1>("h00"), _T_4544, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4550 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4552 = sub(_T_4550, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4553 = asUInt(_T_4552) @[Edges.scala 208:28] + node _T_4554 = tail(_T_4553, 1) @[Edges.scala 208:28] + node _T_4556 = eq(_T_4550, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4558 = eq(_T_4550, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4560 = eq(_T_4548, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4561 = or(_T_4558, _T_4560) @[Edges.scala 210:37] + node _T_4562 = and(_T_4561, _T_4538) @[Edges.scala 211:22] + node _T_4563 = not(_T_4554) @[Edges.scala 212:27] + node _T_4564 = and(_T_4548, _T_4563) @[Edges.scala 212:25] + when _T_4538 : @[Edges.scala 213:17] + node _T_4565 = mux(_T_4556, _T_4548, _T_4554) @[Edges.scala 214:21] + _T_4550 <= _T_4565 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4567 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4569 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4571 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4573 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4575 : UInt, clock @[RocketTiles.scala 51:21] + node _T_4577 = eq(_T_4556, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4578 = and(io.in[1].c.valid, _T_4577) @[RocketTiles.scala 51:21] + when _T_4578 : @[RocketTiles.scala 51:21] + node _T_4579 = eq(io.in[1].c.bits.opcode, _T_4567) @[RocketTiles.scala 51:21] + node _T_4580 = or(_T_4579, reset) @[RocketTiles.scala 51:21] + node _T_4582 = eq(_T_4580, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4582 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4583 = eq(io.in[1].c.bits.param, _T_4569) @[RocketTiles.scala 51:21] + node _T_4584 = or(_T_4583, reset) @[RocketTiles.scala 51:21] + node _T_4586 = eq(_T_4584, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4586 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4587 = eq(io.in[1].c.bits.size, _T_4571) @[RocketTiles.scala 51:21] + node _T_4588 = or(_T_4587, reset) @[RocketTiles.scala 51:21] + node _T_4590 = eq(_T_4588, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4590 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4591 = eq(io.in[1].c.bits.source, _T_4573) @[RocketTiles.scala 51:21] + node _T_4592 = or(_T_4591, reset) @[RocketTiles.scala 51:21] + node _T_4594 = eq(_T_4592, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4594 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4595 = eq(io.in[1].c.bits.address, _T_4575) @[RocketTiles.scala 51:21] + node _T_4596 = or(_T_4595, reset) @[RocketTiles.scala 51:21] + node _T_4598 = eq(_T_4596, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4598 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4599 = and(io.in[1].c.ready, io.in[1].c.valid) @[Bundles.scala 207:36] + node _T_4600 = and(_T_4599, _T_4556) @[RocketTiles.scala 51:21] + when _T_4600 : @[RocketTiles.scala 51:21] + _T_4567 <= io.in[1].c.bits.opcode @[RocketTiles.scala 51:21] + _T_4569 <= io.in[1].c.bits.param @[RocketTiles.scala 51:21] + _T_4571 <= io.in[1].c.bits.size @[RocketTiles.scala 51:21] + _T_4573 <= io.in[1].c.bits.source @[RocketTiles.scala 51:21] + _T_4575 <= io.in[1].c.bits.address @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4601 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4603 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4604 = dshl(_T_4603, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4605 = bits(_T_4604, 7, 0) @[package.scala 19:76] + node _T_4606 = not(_T_4605) @[package.scala 19:40] + node _T_4607 = shr(_T_4606, 3) @[Edges.scala 198:59] + node _T_4608 = bits(io.in[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4610 = mux(_T_4608, _T_4607, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4612 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4614 = sub(_T_4612, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4615 = asUInt(_T_4614) @[Edges.scala 208:28] + node _T_4616 = tail(_T_4615, 1) @[Edges.scala 208:28] + node _T_4618 = eq(_T_4612, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4620 = eq(_T_4612, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4622 = eq(_T_4610, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4623 = or(_T_4620, _T_4622) @[Edges.scala 210:37] + node _T_4624 = and(_T_4623, _T_4601) @[Edges.scala 211:22] + node _T_4625 = not(_T_4616) @[Edges.scala 212:27] + node _T_4626 = and(_T_4610, _T_4625) @[Edges.scala 212:25] + when _T_4601 : @[Edges.scala 213:17] + node _T_4627 = mux(_T_4618, _T_4610, _T_4616) @[Edges.scala 214:21] + _T_4612 <= _T_4627 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_4629 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4631 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4633 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4635 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4637 : UInt, clock @[RocketTiles.scala 51:21] + reg _T_4639 : UInt, clock @[RocketTiles.scala 51:21] + node _T_4641 = eq(_T_4618, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4642 = and(io.in[1].d.valid, _T_4641) @[RocketTiles.scala 51:21] + when _T_4642 : @[RocketTiles.scala 51:21] + node _T_4643 = eq(io.in[1].d.bits.opcode, _T_4629) @[RocketTiles.scala 51:21] + node _T_4644 = or(_T_4643, reset) @[RocketTiles.scala 51:21] + node _T_4646 = eq(_T_4644, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4646 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4647 = eq(io.in[1].d.bits.param, _T_4631) @[RocketTiles.scala 51:21] + node _T_4648 = or(_T_4647, reset) @[RocketTiles.scala 51:21] + node _T_4650 = eq(_T_4648, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4650 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4651 = eq(io.in[1].d.bits.size, _T_4633) @[RocketTiles.scala 51:21] + node _T_4652 = or(_T_4651, reset) @[RocketTiles.scala 51:21] + node _T_4654 = eq(_T_4652, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4654 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4655 = eq(io.in[1].d.bits.source, _T_4635) @[RocketTiles.scala 51:21] + node _T_4656 = or(_T_4655, reset) @[RocketTiles.scala 51:21] + node _T_4658 = eq(_T_4656, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4658 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4659 = eq(io.in[1].d.bits.sink, _T_4637) @[RocketTiles.scala 51:21] + node _T_4660 = or(_T_4659, reset) @[RocketTiles.scala 51:21] + node _T_4662 = eq(_T_4660, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4662 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4663 = eq(io.in[1].d.bits.addr_lo, _T_4639) @[RocketTiles.scala 51:21] + node _T_4664 = or(_T_4663, reset) @[RocketTiles.scala 51:21] + node _T_4666 = eq(_T_4664, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4666 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketTiles.scala:51:21)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4667 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4668 = and(_T_4667, _T_4618) @[RocketTiles.scala 51:21] + when _T_4668 : @[RocketTiles.scala 51:21] + _T_4629 <= io.in[1].d.bits.opcode @[RocketTiles.scala 51:21] + _T_4631 <= io.in[1].d.bits.param @[RocketTiles.scala 51:21] + _T_4633 <= io.in[1].d.bits.size @[RocketTiles.scala 51:21] + _T_4635 <= io.in[1].d.bits.source @[RocketTiles.scala 51:21] + _T_4637 <= io.in[1].d.bits.sink @[RocketTiles.scala 51:21] + _T_4639 <= io.in[1].d.bits.addr_lo @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + reg _T_4670 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + node _T_4671 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + node _T_4673 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4674 = dshl(_T_4673, io.in[1].a.bits.size) @[package.scala 19:71] + node _T_4675 = bits(_T_4674, 7, 0) @[package.scala 19:76] + node _T_4676 = not(_T_4675) @[package.scala 19:40] + node _T_4677 = shr(_T_4676, 3) @[Edges.scala 198:59] + node _T_4678 = bits(io.in[1].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_4680 = eq(_T_4678, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_4682 = mux(_T_4680, _T_4677, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4684 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4686 = sub(_T_4684, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4687 = asUInt(_T_4686) @[Edges.scala 208:28] + node _T_4688 = tail(_T_4687, 1) @[Edges.scala 208:28] + node _T_4690 = eq(_T_4684, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4692 = eq(_T_4684, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4694 = eq(_T_4682, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4695 = or(_T_4692, _T_4694) @[Edges.scala 210:37] + node _T_4696 = and(_T_4695, _T_4671) @[Edges.scala 211:22] + node _T_4697 = not(_T_4688) @[Edges.scala 212:27] + node _T_4698 = and(_T_4682, _T_4697) @[Edges.scala 212:25] + when _T_4671 : @[Edges.scala 213:17] + node _T_4699 = mux(_T_4690, _T_4682, _T_4688) @[Edges.scala 214:21] + _T_4684 <= _T_4699 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_4700 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4702 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_4703 = dshl(_T_4702, io.in[1].d.bits.size) @[package.scala 19:71] + node _T_4704 = bits(_T_4703, 7, 0) @[package.scala 19:76] + node _T_4705 = not(_T_4704) @[package.scala 19:40] + node _T_4706 = shr(_T_4705, 3) @[Edges.scala 198:59] + node _T_4707 = bits(io.in[1].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_4709 = mux(_T_4707, _T_4706, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_4711 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_4713 = sub(_T_4711, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_4714 = asUInt(_T_4713) @[Edges.scala 208:28] + node _T_4715 = tail(_T_4714, 1) @[Edges.scala 208:28] + node _T_4717 = eq(_T_4711, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_4719 = eq(_T_4711, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_4721 = eq(_T_4709, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_4722 = or(_T_4719, _T_4721) @[Edges.scala 210:37] + node _T_4723 = and(_T_4722, _T_4700) @[Edges.scala 211:22] + node _T_4724 = not(_T_4715) @[Edges.scala 212:27] + node _T_4725 = and(_T_4709, _T_4724) @[Edges.scala 212:25] + when _T_4700 : @[Edges.scala 213:17] + node _T_4726 = mux(_T_4717, _T_4709, _T_4715) @[Edges.scala 214:21] + _T_4711 <= _T_4726 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_4728 = eq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + node _T_4729 = neq(io.in[1].a.bits.source, io.in[1].d.bits.source) @[RocketTiles.scala 51:21] + node _T_4730 = or(_T_4728, _T_4729) @[RocketTiles.scala 51:21] + node _T_4732 = eq(io.in[1].a.valid, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4733 = or(_T_4730, _T_4732) @[RocketTiles.scala 51:21] + node _T_4735 = eq(io.in[1].d.valid, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4736 = or(_T_4733, _T_4735) @[RocketTiles.scala 51:21] + node _T_4737 = or(_T_4736, reset) @[RocketTiles.scala 51:21] + node _T_4739 = eq(_T_4737, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4739 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at RocketTiles.scala:51:21)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + wire _T_4741 : UInt<1> + _T_4741 is invalid + _T_4741 <= UInt<1>("h00") + node _T_4742 = and(io.in[1].a.ready, io.in[1].a.valid) @[Bundles.scala 207:36] + when _T_4742 : @[RocketTiles.scala 51:21] + when _T_4695 : @[RocketTiles.scala 51:21] + node _T_4744 = dshl(UInt<1>("h01"), io.in[1].a.bits.source) @[OneHot.scala 47:11] + _T_4741 <= _T_4744 @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4745 = dshr(_T_4670, io.in[1].a.bits.source) @[RocketTiles.scala 51:21] + node _T_4746 = bits(_T_4745, 0, 0) @[RocketTiles.scala 51:21] + node _T_4748 = eq(_T_4746, UInt<1>("h00")) @[RocketTiles.scala 51:21] + node _T_4749 = or(_T_4748, reset) @[RocketTiles.scala 51:21] + node _T_4751 = eq(_T_4749, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4751 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketTiles.scala:51:21)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + wire _T_4753 : UInt<1> + _T_4753 is invalid + _T_4753 <= UInt<1>("h00") + node _T_4754 = and(io.in[1].d.ready, io.in[1].d.valid) @[Bundles.scala 207:36] + node _T_4756 = neq(io.in[1].d.bits.opcode, UInt<3>("h06")) @[RocketTiles.scala 51:21] + node _T_4757 = and(_T_4754, _T_4756) @[RocketTiles.scala 51:21] + when _T_4757 : @[RocketTiles.scala 51:21] + when _T_4722 : @[RocketTiles.scala 51:21] + node _T_4759 = dshl(UInt<1>("h01"), io.in[1].d.bits.source) @[OneHot.scala 47:11] + _T_4753 <= _T_4759 @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4760 = or(_T_4741, _T_4670) @[RocketTiles.scala 51:21] + node _T_4761 = dshr(_T_4760, io.in[1].d.bits.source) @[RocketTiles.scala 51:21] + node _T_4762 = bits(_T_4761, 0, 0) @[RocketTiles.scala 51:21] + node _T_4763 = or(_T_4762, reset) @[RocketTiles.scala 51:21] + node _T_4765 = eq(_T_4763, UInt<1>("h00")) @[RocketTiles.scala 51:21] + when _T_4765 : @[RocketTiles.scala 51:21] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketTiles.scala:51:21)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketTiles.scala 51:21] + stop(clock, UInt<1>(1), 1) @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + skip @[RocketTiles.scala 51:21] + node _T_4766 = or(_T_4670, _T_4741) @[RocketTiles.scala 51:21] + node _T_4767 = not(_T_4753) @[RocketTiles.scala 51:21] + node _T_4768 = and(_T_4766, _T_4767) @[RocketTiles.scala 51:21] + _T_4670 <= _T_4768 @[RocketTiles.scala 51:21] - module NastiRecursiveInterconnect : - input clk : Clock + module TLMonitor_36 : + input clock : Clock input reset : UInt<1> - output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[5]} - - io is invalid - inst xbar of NastiCrossbar - xbar.io is invalid - xbar.clk <= clk - xbar.reset <= reset - xbar.io.masters <= io.masters - io.slaves[0] <- xbar.io.slaves[0] - inst T_2869 of NastiRecursiveInterconnect_56 - T_2869.io is invalid - T_2869.clk <= clk - T_2869.reset <= reset - T_2869.io.masters[0] <- xbar.io.slaves[1] - io.slaves[1] <- T_2869.io.slaves[0] - io.slaves[2] <- T_2869.io.slaves[1] - io.slaves[3] <- T_2869.io.slaves[2] - inst T_2870 of NastiErrorSlave_40 - T_2870.io is invalid - T_2870.clk <= clk - T_2870.reset <= reset - T_2870.io <- xbar.io.slaves[2] - io.slaves[4] <- xbar.io.slaves[3] - - module LockingRRArbiter_67 : + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, mask : UInt<1>, data : UInt<8>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, address : UInt<1>, mask : UInt<1>, data : UInt<8>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, data : UInt<8>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, addr_lo : UInt<1>, data : UInt<8>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[0]} + + io is invalid + io is invalid + + extmodule AsyncResetReg : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<1>} - - io is invalid - reg T_656 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_658 : UInt, clk with : (reset => (reset, UInt<1>("h01"))) - wire T_660 : UInt<1> - T_660 is invalid - io.out.valid <= io.in[T_660].valid - io.out.bits <- io.in[T_660].bits - io.chosen <= T_660 - io.in[T_660].ready <= UInt<1>("h00") - reg last_grant : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_842 = gt(UInt<1>("h00"), last_grant) - node T_843 = and(io.in[0].valid, T_842) - node T_845 = gt(UInt<1>("h01"), last_grant) - node T_846 = and(io.in[1].valid, T_845) - node T_849 = or(UInt<1>("h00"), T_843) - node T_851 = eq(T_849, UInt<1>("h00")) - node T_853 = or(UInt<1>("h00"), T_843) - node T_854 = or(T_853, T_846) - node T_856 = eq(T_854, UInt<1>("h00")) - node T_858 = or(UInt<1>("h00"), T_843) - node T_859 = or(T_858, T_846) - node T_860 = or(T_859, io.in[0].valid) - node T_862 = eq(T_860, UInt<1>("h00")) - node T_864 = gt(UInt<1>("h00"), last_grant) - node T_865 = and(UInt<1>("h01"), T_864) - node T_866 = or(T_865, T_856) - node T_868 = gt(UInt<1>("h01"), last_grant) - node T_869 = and(T_851, T_868) - node T_870 = or(T_869, T_862) - node T_872 = eq(T_658, UInt<1>("h00")) - node T_873 = mux(T_656, T_872, T_866) - node T_874 = and(T_873, io.out.ready) - io.in[0].ready <= T_874 - node T_876 = eq(T_658, UInt<1>("h01")) - node T_877 = mux(T_656, T_876, T_870) - node T_878 = and(T_877, io.out.ready) - io.in[1].ready <= T_878 - reg T_880 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_882 = add(T_880, UInt<1>("h01")) - node T_883 = tail(T_882, 1) - node T_884 = and(io.out.ready, io.out.valid) - when T_884 : - node T_886 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) - wire T_889 : UInt<3>[1] - T_889[0] <= UInt<3>("h03") - node T_892 = eq(T_889[0], io.out.bits.a_type) - node T_894 = or(UInt<1>("h00"), T_892) - node T_895 = and(T_886, T_894) - when T_895 : - T_880 <= T_883 - node T_897 = eq(T_656, UInt<1>("h00")) - when T_897 : - T_656 <= UInt<1>("h01") - node T_899 = and(io.in[0].ready, io.in[0].valid) - node T_900 = and(io.in[1].ready, io.in[1].valid) - wire T_902 : UInt<1>[2] - T_902[0] <= T_899 - T_902[1] <= T_900 - node T_908 = mux(T_902[0], UInt<1>("h00"), UInt<1>("h01")) - T_658 <= T_908 - skip - skip - node T_910 = eq(T_883, UInt<1>("h00")) - when T_910 : - T_656 <= UInt<1>("h00") - skip - skip - node T_914 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_916 = gt(UInt<1>("h01"), last_grant) - node T_917 = and(io.in[1].valid, T_916) - node choose = mux(T_917, UInt<1>("h01"), T_914) - node T_920 = mux(T_656, T_658, choose) - T_660 <= T_920 - node T_921 = and(io.out.ready, io.out.valid) - when T_921 : - last_grant <= T_660 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module ReorderQueue : + extmodule AsyncResetReg_1 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_1 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} - - io is invalid - reg roq_data : UInt<1>[9], clk - reg roq_tags : UInt<4>[9], clk - wire T_96 : UInt<1>[9] - T_96[0] <= UInt<1>("h01") - T_96[1] <= UInt<1>("h01") - T_96[2] <= UInt<1>("h01") - T_96[3] <= UInt<1>("h01") - T_96[4] <= UInt<1>("h01") - T_96[5] <= UInt<1>("h01") - T_96[6] <= UInt<1>("h01") - T_96[7] <= UInt<1>("h01") - T_96[8] <= UInt<1>("h01") - reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_96)) - node T_129 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) - node T_130 = mux(roq_free[6], UInt<3>("h06"), T_129) - node T_131 = mux(roq_free[5], UInt<3>("h05"), T_130) - node T_132 = mux(roq_free[4], UInt<3>("h04"), T_131) - node T_133 = mux(roq_free[3], UInt<2>("h03"), T_132) - node T_134 = mux(roq_free[2], UInt<2>("h02"), T_133) - node T_135 = mux(roq_free[1], UInt<1>("h01"), T_134) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_135) - node T_137 = eq(roq_tags[0], io.deq.tag) - node T_139 = eq(roq_free[0], UInt<1>("h00")) - node T_140 = and(T_137, T_139) - node T_141 = eq(roq_tags[1], io.deq.tag) - node T_143 = eq(roq_free[1], UInt<1>("h00")) - node T_144 = and(T_141, T_143) - node T_145 = eq(roq_tags[2], io.deq.tag) - node T_147 = eq(roq_free[2], UInt<1>("h00")) - node T_148 = and(T_145, T_147) - node T_149 = eq(roq_tags[3], io.deq.tag) - node T_151 = eq(roq_free[3], UInt<1>("h00")) - node T_152 = and(T_149, T_151) - node T_153 = eq(roq_tags[4], io.deq.tag) - node T_155 = eq(roq_free[4], UInt<1>("h00")) - node T_156 = and(T_153, T_155) - node T_157 = eq(roq_tags[5], io.deq.tag) - node T_159 = eq(roq_free[5], UInt<1>("h00")) - node T_160 = and(T_157, T_159) - node T_161 = eq(roq_tags[6], io.deq.tag) - node T_163 = eq(roq_free[6], UInt<1>("h00")) - node T_164 = and(T_161, T_163) - node T_165 = eq(roq_tags[7], io.deq.tag) - node T_167 = eq(roq_free[7], UInt<1>("h00")) - node T_168 = and(T_165, T_167) - node T_169 = eq(roq_tags[8], io.deq.tag) - node T_171 = eq(roq_free[8], UInt<1>("h00")) - node T_172 = and(T_169, T_171) - node T_182 = mux(T_168, UInt<3>("h07"), UInt<4>("h08")) - node T_183 = mux(T_164, UInt<3>("h06"), T_182) - node T_184 = mux(T_160, UInt<3>("h05"), T_183) - node T_185 = mux(T_156, UInt<3>("h04"), T_184) - node T_186 = mux(T_152, UInt<2>("h03"), T_185) - node T_187 = mux(T_148, UInt<2>("h02"), T_186) - node T_188 = mux(T_144, UInt<1>("h01"), T_187) - node roq_deq_addr = mux(T_140, UInt<1>("h00"), T_188) - node T_190 = or(roq_free[0], roq_free[1]) - node T_191 = or(T_190, roq_free[2]) - node T_192 = or(T_191, roq_free[3]) - node T_193 = or(T_192, roq_free[4]) - node T_194 = or(T_193, roq_free[5]) - node T_195 = or(T_194, roq_free[6]) - node T_196 = or(T_195, roq_free[7]) - node T_197 = or(T_196, roq_free[8]) - io.enq.ready <= T_197 - io.deq.data <= roq_data[roq_deq_addr] - node T_199 = or(T_140, T_144) - node T_200 = or(T_199, T_148) - node T_201 = or(T_200, T_152) - node T_202 = or(T_201, T_156) - node T_203 = or(T_202, T_160) - node T_204 = or(T_203, T_164) - node T_205 = or(T_204, T_168) - node T_206 = or(T_205, T_172) - io.deq.matches <= T_206 - node T_207 = and(io.enq.valid, io.enq.ready) - when T_207 : - roq_data[roq_enq_addr] <= io.enq.bits.data - roq_tags[roq_enq_addr] <= io.enq.bits.tag - roq_free[roq_enq_addr] <= UInt<1>("h00") - skip - when io.deq.valid : - roq_free[roq_deq_addr] <= UInt<1>("h01") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_1 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module ClientTileLinkIOUnwrapper : + extmodule AsyncResetReg_2 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_2 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - - io is invalid - inst acqArb of LockingRRArbiter_67 - acqArb.io is invalid - acqArb.clk <= clk - acqArb.reset <= reset - inst acqRoq of ReorderQueue - acqRoq.io is invalid - acqRoq.clk <= clk - acqRoq.reset <= reset - inst relRoq of ReorderQueue - relRoq.io is invalid - relRoq.clk <= clk - relRoq.reset <= reset - node T_1215 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) - wire T_1218 : UInt<3>[1] - T_1218[0] <= UInt<3>("h03") - node T_1221 = eq(T_1218[0], io.in.acquire.bits.a_type) - node T_1223 = or(UInt<1>("h00"), T_1221) - node T_1224 = and(T_1215, T_1223) - node T_1226 = eq(T_1224, UInt<1>("h00")) - node T_1228 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) - node acq_roq_enq = or(T_1226, T_1228) - wire T_1232 : UInt<2>[3] - T_1232[0] <= UInt<1>("h00") - T_1232[1] <= UInt<1>("h01") - T_1232[2] <= UInt<2>("h02") - node T_1237 = eq(T_1232[0], io.in.release.bits.r_type) - node T_1238 = eq(T_1232[1], io.in.release.bits.r_type) - node T_1239 = eq(T_1232[2], io.in.release.bits.r_type) - node T_1241 = or(UInt<1>("h00"), T_1237) - node T_1242 = or(T_1241, T_1238) - node T_1243 = or(T_1242, T_1239) - node T_1244 = and(UInt<1>("h01"), T_1243) - node T_1246 = eq(T_1244, UInt<1>("h00")) - node T_1248 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) - node rel_roq_enq = or(T_1246, T_1248) - node T_1251 = eq(acq_roq_enq, UInt<1>("h00")) - node acq_roq_ready = or(T_1251, acqRoq.io.enq.ready) - node T_1254 = eq(rel_roq_enq, UInt<1>("h00")) - node rel_roq_ready = or(T_1254, relRoq.io.enq.ready) - node T_1256 = and(io.in.acquire.valid, acqArb.io.in[0].ready) - node T_1257 = and(T_1256, acq_roq_enq) - acqRoq.io.enq.valid <= T_1257 - acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type - acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - node T_1258 = and(io.in.acquire.valid, acq_roq_ready) - acqArb.io.in[0].valid <= T_1258 - node T_1261 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) - node T_1263 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1264 = cat(UInt<3>("h07"), T_1263) - node T_1265 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1264) - wire T_1294 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1294 is invalid - T_1294.is_builtin_type <= UInt<1>("h01") - T_1294.a_type <= T_1261 - T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1294.addr_block <= io.in.acquire.bits.addr_block - T_1294.addr_beat <= io.in.acquire.bits.addr_beat - T_1294.data <= io.in.acquire.bits.data - T_1294.union <= T_1265 - acqArb.io.in[0].bits <- T_1294 - node T_1322 = and(acq_roq_ready, acqArb.io.in[0].ready) - io.in.acquire.ready <= T_1322 - node T_1323 = and(io.in.release.valid, acqArb.io.in[1].ready) - node T_1324 = and(T_1323, rel_roq_enq) - relRoq.io.enq.valid <= T_1324 - relRoq.io.enq.bits.data <= io.in.release.bits.voluntary - relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id - node T_1325 = and(io.in.release.valid, rel_roq_ready) - acqArb.io.in[1].valid <= T_1325 - node T_1347 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_1355 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1356 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1357 = cat(T_1355, T_1356) - node T_1359 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1360 = cat(UInt<3>("h07"), T_1359) - node T_1362 = cat(T_1347, UInt<1>("h01")) - node T_1364 = cat(T_1347, UInt<1>("h01")) - node T_1366 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1367 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1368 = cat(T_1366, T_1367) - node T_1370 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1372 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1373 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1374 = mux(T_1373, T_1372, UInt<1>("h00")) - node T_1375 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1376 = mux(T_1375, T_1370, T_1374) - node T_1377 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1378 = mux(T_1377, T_1368, T_1376) - node T_1379 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1380 = mux(T_1379, T_1364, T_1378) - node T_1381 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1382 = mux(T_1381, T_1362, T_1380) - node T_1383 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1384 = mux(T_1383, T_1360, T_1382) - node T_1385 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1386 = mux(T_1385, T_1357, T_1384) - wire T_1415 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1415 is invalid - T_1415.is_builtin_type <= UInt<1>("h01") - T_1415.a_type <= UInt<3>("h03") - T_1415.client_xact_id <= io.in.release.bits.client_xact_id - T_1415.addr_block <= io.in.release.bits.addr_block - T_1415.addr_beat <= io.in.release.bits.addr_beat - T_1415.data <= io.in.release.bits.data - T_1415.union <= T_1386 - acqArb.io.in[1].bits <- T_1415 - node T_1443 = and(rel_roq_ready, acqArb.io.in[1].ready) - io.in.release.ready <= T_1443 - io.out.acquire <- acqArb.io.out - node T_1444 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1448 : UInt<3>[1] - T_1448[0] <= UInt<3>("h05") - node T_1451 = eq(T_1448[0], io.out.grant.bits.g_type) - node T_1453 = or(UInt<1>("h00"), T_1451) - wire T_1455 : UInt<1>[1] - T_1455[0] <= UInt<1>("h00") - node T_1458 = eq(T_1455[0], io.out.grant.bits.g_type) - node T_1460 = or(UInt<1>("h00"), T_1458) - node T_1461 = mux(io.out.grant.bits.is_builtin_type, T_1453, T_1460) - node T_1462 = and(UInt<1>("h01"), T_1461) - node T_1464 = eq(T_1462, UInt<1>("h00")) - node T_1466 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) - node T_1467 = or(T_1464, T_1466) - node T_1468 = and(T_1444, T_1467) - acqRoq.io.deq.valid <= T_1468 - acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1469 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1473 : UInt<3>[1] - T_1473[0] <= UInt<3>("h05") - node T_1476 = eq(T_1473[0], io.out.grant.bits.g_type) - node T_1478 = or(UInt<1>("h00"), T_1476) - wire T_1480 : UInt<1>[1] - T_1480[0] <= UInt<1>("h00") - node T_1483 = eq(T_1480[0], io.out.grant.bits.g_type) - node T_1485 = or(UInt<1>("h00"), T_1483) - node T_1486 = mux(io.out.grant.bits.is_builtin_type, T_1478, T_1485) - node T_1487 = and(UInt<1>("h01"), T_1486) - node T_1489 = eq(T_1487, UInt<1>("h00")) - node T_1491 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) - node T_1492 = or(T_1489, T_1491) - node T_1493 = and(T_1469, T_1492) - relRoq.io.deq.valid <= T_1493 - relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1494 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00")) - wire acq_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - acq_grant is invalid - acq_grant.is_builtin_type <= acqRoq.io.deq.data - acq_grant.g_type <= T_1494 - acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id - acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id - acq_grant.addr_beat <= io.out.grant.bits.addr_beat - acq_grant.data <= io.out.grant.bits.data - node T_1551 = mux(relRoq.io.deq.data, UInt<3>("h00"), io.out.grant.bits.g_type) - wire rel_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - rel_grant is invalid - rel_grant.is_builtin_type <= UInt<1>("h01") - rel_grant.g_type <= T_1551 - rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id - rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id - rel_grant.addr_beat <= io.out.grant.bits.addr_beat - rel_grant.data <= io.out.grant.bits.data - io.in.grant.valid <= io.out.grant.valid - node T_1606 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant) - io.in.grant.bits <- T_1606 - io.out.grant.ready <= io.in.grant.ready - io.in.probe.valid <= UInt<1>("h00") - - module TileLinkIONarrower : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_2 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_3 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_3 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - - io is invalid - node T_815 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_817 = eq(io.in.acquire.bits.a_type, UInt<3>("h01")) - node T_819 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_821 = eq(io.in.acquire.bits.a_type, UInt<3>("h00")) - reg T_823 : UInt<128>, clk - reg T_825 : UInt<16>, clk - reg T_826 : UInt<4>, clk - reg T_827 : UInt<26>, clk - reg T_828 : UInt<2>, clk - reg T_830 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_831 = bits(io.in.acquire.bits.union, 12, 9) - node T_832 = cat(io.in.acquire.bits.addr_beat, T_831) - node T_833 = cat(io.in.acquire.bits.addr_block, T_832) - node T_834 = bits(T_833, 3, 3) - node T_835 = bits(io.in.acquire.bits.union, 12, 9) - node T_836 = cat(io.in.acquire.bits.addr_beat, T_835) - node T_837 = cat(io.in.acquire.bits.addr_block, T_836) - node T_838 = bits(T_837, 5, 3) - node T_839 = bits(io.in.acquire.bits.union, 12, 9) - node T_840 = cat(io.in.acquire.bits.addr_beat, T_839) - node T_841 = cat(io.in.acquire.bits.addr_block, T_840) - node T_842 = bits(T_841, 2, 0) - node T_843 = bits(io.in.acquire.bits.union, 12, 9) - node T_844 = bits(T_843, 3, 3) - node T_846 = dshl(UInt<1>("h01"), T_844) - node T_848 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) - node T_849 = and(io.in.acquire.bits.is_builtin_type, T_848) - node T_850 = bits(T_846, 0, 0) - node T_851 = bits(T_846, 1, 1) - wire T_853 : UInt<1>[2] - T_853[0] <= T_850 - T_853[1] <= T_851 - node T_858 = sub(UInt<8>("h00"), T_853[0]) - node T_859 = tail(T_858, 1) - node T_861 = sub(UInt<8>("h00"), T_853[1]) - node T_862 = tail(T_861, 1) - wire T_864 : UInt<8>[2] - T_864[0] <= T_859 - T_864[1] <= T_862 - node T_868 = cat(T_864[1], T_864[0]) - node T_870 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_871 = and(io.in.acquire.bits.is_builtin_type, T_870) - node T_873 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_874 = and(io.in.acquire.bits.is_builtin_type, T_873) - node T_875 = or(T_871, T_874) - node T_876 = bits(io.in.acquire.bits.union, 16, 1) - node T_878 = mux(T_875, T_876, UInt<16>("h00")) - node T_879 = mux(T_849, T_868, T_878) - node T_880 = bits(T_879, 7, 0) - node T_881 = bits(io.in.acquire.bits.union, 12, 9) - node T_882 = bits(T_881, 3, 3) - node T_884 = dshl(UInt<1>("h01"), T_882) - node T_886 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) - node T_887 = and(io.in.acquire.bits.is_builtin_type, T_886) - node T_888 = bits(T_884, 0, 0) - node T_889 = bits(T_884, 1, 1) - wire T_891 : UInt<1>[2] - T_891[0] <= T_888 - T_891[1] <= T_889 - node T_896 = sub(UInt<8>("h00"), T_891[0]) - node T_897 = tail(T_896, 1) - node T_899 = sub(UInt<8>("h00"), T_891[1]) - node T_900 = tail(T_899, 1) - wire T_902 : UInt<8>[2] - T_902[0] <= T_897 - T_902[1] <= T_900 - node T_906 = cat(T_902[1], T_902[0]) - node T_908 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_909 = and(io.in.acquire.bits.is_builtin_type, T_908) - node T_911 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_912 = and(io.in.acquire.bits.is_builtin_type, T_911) - node T_913 = or(T_909, T_912) - node T_914 = bits(io.in.acquire.bits.union, 16, 1) - node T_916 = mux(T_913, T_914, UInt<16>("h00")) - node T_917 = mux(T_887, T_906, T_916) - node T_918 = bits(T_917, 15, 8) - wire T_920 : UInt<8>[2] - T_920[0] <= T_880 - T_920[1] <= T_918 - node T_924 = bits(io.in.acquire.bits.data, 63, 0) - node T_925 = bits(io.in.acquire.bits.data, 127, 64) - wire T_927 : UInt<64>[2] - T_927[0] <= T_924 - T_927[1] <= T_925 - node T_932 = neq(T_920[0], UInt<1>("h00")) - node T_934 = neq(T_920[1], UInt<1>("h00")) - node T_935 = cat(T_934, T_932) - node T_936 = bits(T_935, 0, 0) - node T_937 = bits(T_935, 1, 1) - node T_939 = mux(T_936, T_927[0], UInt<1>("h00")) - node T_941 = mux(T_937, T_927[1], UInt<1>("h00")) - node T_943 = or(T_939, T_941) - wire T_944 : UInt<64> - T_944 is invalid - T_944 <= T_943 - node T_945 = bits(T_935, 0, 0) - node T_946 = bits(T_935, 1, 1) - node T_948 = mux(T_945, T_920[0], UInt<1>("h00")) - node T_950 = mux(T_946, T_920[1], UInt<1>("h00")) - node T_952 = or(T_948, T_950) - wire T_953 : UInt<8> - T_953 is invalid - T_953 <= T_952 - node T_954 = bits(T_935, 0, 0) - node T_955 = bits(T_935, 1, 1) - wire T_957 : UInt<1>[2] - T_957[0] <= T_954 - T_957[1] <= T_955 - node T_963 = mux(T_957[0], UInt<1>("h00"), UInt<1>("h01")) - node T_964 = cat(io.in.acquire.bits.addr_beat, T_963) - node T_966 = eq(io.in.acquire.valid, UInt<1>("h00")) - node T_968 = eq(T_819, UInt<1>("h00")) - node T_969 = or(T_966, T_968) - node T_970 = bits(T_935, 0, 0) - node T_971 = bits(T_935, 1, 1) - node T_973 = cat(UInt<1>("h00"), T_971) - node T_974 = add(T_970, T_973) - node T_975 = tail(T_974, 1) - node T_977 = leq(T_975, UInt<1>("h01")) - node T_978 = or(T_969, T_977) - node T_980 = eq(reset, UInt<1>("h00")) - when T_980 : - node T_982 = eq(T_978, UInt<1>("h00")) - when T_982 : - node T_984 = eq(reset, UInt<1>("h00")) - when T_984 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_985 = bits(io.in.acquire.bits.union, 8, 6) - node T_994 = eq(UInt<3>("h07"), T_985) - node T_995 = mux(T_994, UInt<1>("h00"), UInt<1>("h00")) - node T_996 = eq(UInt<3>("h03"), T_985) - node T_997 = mux(T_996, UInt<1>("h01"), T_995) - node T_998 = eq(UInt<3>("h02"), T_985) - node T_999 = mux(T_998, UInt<1>("h01"), T_997) - node T_1000 = eq(UInt<3>("h05"), T_985) - node T_1001 = mux(T_1000, UInt<1>("h01"), T_999) - node T_1002 = eq(UInt<3>("h01"), T_985) - node T_1003 = mux(T_1002, UInt<1>("h01"), T_1001) - node T_1004 = eq(UInt<3>("h04"), T_985) - node T_1005 = mux(T_1004, UInt<1>("h01"), T_1003) - node T_1006 = eq(UInt<3>("h00"), T_985) - node T_1007 = mux(T_1006, UInt<1>("h01"), T_1005) - node T_1009 = eq(io.in.acquire.valid, UInt<1>("h00")) - node T_1011 = eq(T_821, UInt<1>("h00")) - node T_1012 = or(T_1009, T_1011) - node T_1013 = or(T_1012, T_1007) - node T_1015 = eq(reset, UInt<1>("h00")) - when T_1015 : - node T_1017 = eq(T_1013, UInt<1>("h00")) - when T_1017 : - node T_1019 = eq(reset, UInt<1>("h00")) - when T_1019 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1020 = bits(io.in.acquire.bits.union, 0, 0) - node T_1029 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1030 = cat(UInt<5>("h00"), T_1020) - node T_1031 = cat(T_1029, T_1030) - node T_1033 = cat(UInt<5>("h00"), T_1020) - node T_1034 = cat(UInt<3>("h07"), T_1033) - node T_1036 = cat(UInt<1>("h00"), T_1020) - node T_1038 = cat(UInt<1>("h00"), T_1020) - node T_1040 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1041 = cat(UInt<5>("h00"), T_1020) - node T_1042 = cat(T_1040, T_1041) - node T_1044 = cat(UInt<5>("h00"), T_1020) - node T_1046 = cat(UInt<5>("h01"), T_1020) - node T_1047 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1048 = mux(T_1047, T_1046, UInt<1>("h00")) - node T_1049 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1050 = mux(T_1049, T_1044, T_1048) - node T_1051 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1052 = mux(T_1051, T_1042, T_1050) - node T_1053 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1054 = mux(T_1053, T_1038, T_1052) - node T_1055 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1056 = mux(T_1055, T_1036, T_1054) - node T_1057 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1058 = mux(T_1057, T_1034, T_1056) - node T_1059 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1060 = mux(T_1059, T_1031, T_1058) - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1089 is invalid - T_1089.is_builtin_type <= UInt<1>("h01") - T_1089.a_type <= UInt<3>("h01") - T_1089.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1089.addr_block <= io.in.acquire.bits.addr_block - T_1089.addr_beat <= UInt<1>("h00") - T_1089.data <= UInt<1>("h00") - T_1089.union <= T_1060 - node T_1117 = cat(T_828, T_830) - node T_1118 = bits(T_823, 63, 0) - node T_1119 = bits(T_825, 7, 0) - node T_1127 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1128 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1129 = cat(T_1127, T_1128) - node T_1131 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1132 = cat(UInt<3>("h07"), T_1131) - node T_1134 = cat(T_1119, UInt<1>("h01")) - node T_1136 = cat(T_1119, UInt<1>("h01")) - node T_1138 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1139 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1140 = cat(T_1138, T_1139) - node T_1142 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1144 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1145 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1146 = mux(T_1145, T_1144, UInt<1>("h00")) - node T_1147 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1148 = mux(T_1147, T_1142, T_1146) - node T_1149 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1150 = mux(T_1149, T_1140, T_1148) - node T_1151 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1152 = mux(T_1151, T_1136, T_1150) - node T_1153 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1154 = mux(T_1153, T_1134, T_1152) - node T_1155 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1156 = mux(T_1155, T_1132, T_1154) - node T_1157 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1158 = mux(T_1157, T_1129, T_1156) - wire T_1187 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1187 is invalid - T_1187.is_builtin_type <= UInt<1>("h01") - T_1187.a_type <= UInt<3>("h03") - T_1187.client_xact_id <= T_826 - T_1187.addr_block <= T_827 - T_1187.addr_beat <= T_1117 - T_1187.data <= T_1118 - T_1187.union <= T_1158 - node T_1215 = bits(io.in.acquire.bits.union, 8, 6) - node T_1216 = bits(io.in.acquire.bits.union, 0, 0) - node T_1223 = cat(T_842, T_1215) - node T_1224 = cat(UInt<5>("h00"), T_1216) - node T_1225 = cat(T_1223, T_1224) - node T_1227 = cat(UInt<5>("h00"), T_1216) - node T_1228 = cat(T_1215, T_1227) - node T_1230 = cat(UInt<1>("h00"), T_1216) - node T_1232 = cat(UInt<1>("h00"), T_1216) - node T_1234 = cat(T_842, T_1215) - node T_1235 = cat(UInt<5>("h00"), T_1216) - node T_1236 = cat(T_1234, T_1235) - node T_1238 = cat(UInt<5>("h00"), T_1216) - node T_1240 = cat(UInt<5>("h01"), T_1216) - node T_1241 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_1242 = mux(T_1241, T_1240, UInt<1>("h00")) - node T_1243 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_1244 = mux(T_1243, T_1238, T_1242) - node T_1245 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_1246 = mux(T_1245, T_1236, T_1244) - node T_1247 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_1248 = mux(T_1247, T_1232, T_1246) - node T_1249 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_1250 = mux(T_1249, T_1230, T_1248) - node T_1251 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_1252 = mux(T_1251, T_1228, T_1250) - node T_1253 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_1254 = mux(T_1253, T_1225, T_1252) - wire T_1283 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1283 is invalid - T_1283.is_builtin_type <= UInt<1>("h01") - T_1283.a_type <= UInt<3>("h00") - T_1283.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1283.addr_block <= io.in.acquire.bits.addr_block - T_1283.addr_beat <= T_838 - T_1283.data <= UInt<1>("h00") - T_1283.union <= T_1254 - node T_1318 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1319 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1320 = cat(T_1318, T_1319) - node T_1322 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1323 = cat(UInt<3>("h07"), T_1322) - node T_1325 = cat(T_953, UInt<1>("h01")) - node T_1327 = cat(T_953, UInt<1>("h01")) - node T_1329 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1330 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1331 = cat(T_1329, T_1330) - node T_1333 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1335 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1336 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_1337 = mux(T_1336, T_1335, UInt<1>("h00")) - node T_1338 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_1339 = mux(T_1338, T_1333, T_1337) - node T_1340 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_1341 = mux(T_1340, T_1331, T_1339) - node T_1342 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_1343 = mux(T_1342, T_1327, T_1341) - node T_1344 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_1345 = mux(T_1344, T_1325, T_1343) - node T_1346 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_1347 = mux(T_1346, T_1323, T_1345) - node T_1348 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_1349 = mux(T_1348, T_1320, T_1347) - wire T_1378 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1378 is invalid - T_1378.is_builtin_type <= UInt<1>("h01") - T_1378.a_type <= UInt<3>("h02") - T_1378.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1378.addr_block <= io.in.acquire.bits.addr_block - T_1378.addr_beat <= T_964 - T_1378.data <= T_944 - T_1378.union <= T_1349 - reg T_1407 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1409 = eq(T_815, UInt<1>("h00")) - node T_1410 = and(io.in.acquire.valid, T_1409) - node T_1412 = eq(T_821, UInt<1>("h00")) - node T_1413 = and(T_1410, T_1412) - node T_1414 = and(T_821, io.in.acquire.valid) - inst T_1415 of ReorderQueue - T_1415.io is invalid - T_1415.clk <= clk - T_1415.reset <= reset - node T_1417 = eq(T_1407, UInt<1>("h00")) - node T_1418 = and(T_1414, io.out.acquire.ready) - node T_1419 = and(T_1418, T_1417) - T_1415.io.enq.valid <= T_1419 - T_1415.io.enq.bits.data <= T_834 - T_1415.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - wire T_1420 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1420 <- io.in.acquire.bits - node T_1448 = mux(T_821, T_1283, T_1420) - node T_1476 = mux(T_819, T_1378, T_1448) - node T_1504 = mux(T_817, T_1089, T_1476) - node T_1532 = mux(T_1407, T_1187, T_1504) - io.out.acquire.bits <- T_1532 - node T_1560 = or(T_1407, T_1413) - node T_1561 = and(T_1414, T_1415.io.enq.ready) - node T_1562 = or(T_1560, T_1561) - io.out.acquire.valid <= T_1562 - node T_1564 = eq(T_1407, UInt<1>("h00")) - node T_1566 = eq(T_821, UInt<1>("h00")) - node T_1567 = and(T_1566, io.out.acquire.ready) - node T_1568 = or(T_815, T_1567) - node T_1569 = and(T_1415.io.enq.ready, io.out.acquire.ready) - node T_1570 = or(T_1568, T_1569) - node T_1571 = and(T_1564, T_1570) - io.in.acquire.ready <= T_1571 - node T_1572 = and(io.in.acquire.ready, io.in.acquire.valid) - node T_1573 = and(T_1572, T_815) - when T_1573 : - T_823 <= io.in.acquire.bits.data - node T_1574 = bits(io.in.acquire.bits.union, 12, 9) - node T_1575 = bits(T_1574, 3, 3) - node T_1577 = dshl(UInt<1>("h01"), T_1575) - node T_1579 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) - node T_1580 = and(io.in.acquire.bits.is_builtin_type, T_1579) - node T_1581 = bits(T_1577, 0, 0) - node T_1582 = bits(T_1577, 1, 1) - wire T_1584 : UInt<1>[2] - T_1584[0] <= T_1581 - T_1584[1] <= T_1582 - node T_1589 = sub(UInt<8>("h00"), T_1584[0]) - node T_1590 = tail(T_1589, 1) - node T_1592 = sub(UInt<8>("h00"), T_1584[1]) - node T_1593 = tail(T_1592, 1) - wire T_1595 : UInt<8>[2] - T_1595[0] <= T_1590 - T_1595[1] <= T_1593 - node T_1599 = cat(T_1595[1], T_1595[0]) - node T_1601 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_1602 = and(io.in.acquire.bits.is_builtin_type, T_1601) - node T_1604 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_1605 = and(io.in.acquire.bits.is_builtin_type, T_1604) - node T_1606 = or(T_1602, T_1605) - node T_1607 = bits(io.in.acquire.bits.union, 16, 1) - node T_1609 = mux(T_1606, T_1607, UInt<16>("h00")) - node T_1610 = mux(T_1580, T_1599, T_1609) - T_825 <= T_1610 - T_826 <= io.in.acquire.bits.client_xact_id - T_827 <= io.in.acquire.bits.addr_block - T_828 <= io.in.acquire.bits.addr_beat - T_1407 <= UInt<1>("h01") - skip - node T_1612 = and(T_1407, io.out.acquire.ready) - when T_1612 : - node T_1613 = shr(T_823, 64) - T_823 <= T_1613 - node T_1614 = shr(T_825, 8) - T_825 <= T_1614 - node T_1616 = eq(T_830, UInt<1>("h01")) - node T_1618 = and(UInt<1>("h00"), T_1616) - node T_1621 = add(T_830, UInt<1>("h01")) - node T_1622 = tail(T_1621, 1) - node T_1623 = mux(T_1618, UInt<1>("h00"), T_1622) - T_830 <= T_1623 - when T_1616 : - T_1407 <= UInt<1>("h00") - skip - skip - wire T_1628 : UInt<3>[1] - T_1628[0] <= UInt<3>("h05") - node T_1631 = eq(T_1628[0], io.out.grant.bits.g_type) - node T_1633 = or(UInt<1>("h00"), T_1631) - wire T_1635 : UInt<1>[1] - T_1635[0] <= UInt<1>("h00") - node T_1638 = eq(T_1635[0], io.out.grant.bits.g_type) - node T_1640 = or(UInt<1>("h00"), T_1638) - node T_1641 = mux(io.out.grant.bits.is_builtin_type, T_1633, T_1640) - node T_1642 = and(UInt<1>("h01"), T_1641) - reg T_1651 : UInt<64>[2], clk - reg T_1655 : UInt<4>, clk - reg T_1656 : UInt<1>, clk - reg T_1658 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg T_1660 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1665 = cat(T_1651[1], T_1651[0]) - wire T_1693 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1693 is invalid - T_1693.is_builtin_type <= UInt<1>("h01") - T_1693.g_type <= UInt<3>("h05") - T_1693.client_xact_id <= T_1655 - T_1693.manager_xact_id <= T_1656 - T_1693.addr_beat <= T_1658 - T_1693.data <= T_1665 - node T_1721 = eq(io.out.grant.bits.g_type, UInt<3>("h04")) - node T_1723 = cat(T_1415.io.deq.data, UInt<6>("h00")) - node T_1724 = and(io.out.grant.ready, io.out.grant.valid) - node T_1725 = and(T_1724, T_1721) - T_1415.io.deq.valid <= T_1725 - T_1415.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1729 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h01")) - node T_1730 = dshl(io.out.grant.bits.data, T_1723) - wire T_1758 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1758 is invalid - T_1758.is_builtin_type <= UInt<1>("h01") - T_1758.g_type <= UInt<3>("h04") - T_1758.client_xact_id <= io.out.grant.bits.client_xact_id - T_1758.manager_xact_id <= io.out.grant.bits.manager_xact_id - T_1758.addr_beat <= T_1729 - T_1758.data <= T_1730 - node T_1786 = eq(T_1642, UInt<1>("h00")) - node T_1787 = and(io.out.grant.valid, T_1786) - node T_1788 = or(T_1662, T_1787) - io.in.grant.valid <= T_1788 - node T_1790 = eq(T_1662, UInt<1>("h00")) - node T_1791 = or(T_1642, io.in.grant.ready) - node T_1792 = and(T_1790, T_1791) - io.out.grant.ready <= T_1792 - wire T_1793 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1793 <- io.out.grant.bits - node T_1820 = mux(T_1721, T_1758, T_1793) - node T_1847 = mux(T_1662, T_1693, T_1820) - io.in.grant.bits <- T_1847 - node T_1874 = and(io.out.grant.valid, T_1642) - node T_1876 = eq(T_1662, UInt<1>("h00")) - node T_1877 = and(T_1874, T_1876) - when T_1877 : - T_1651[T_1660] <= io.out.grant.bits.data - node T_1880 = eq(T_1660, UInt<1>("h01")) - node T_1882 = and(UInt<1>("h00"), T_1880) - node T_1885 = add(T_1660, UInt<1>("h01")) - node T_1886 = tail(T_1885, 1) - node T_1887 = mux(T_1882, UInt<1>("h00"), T_1886) - T_1660 <= T_1887 - when T_1880 : - T_1655 <= io.out.grant.bits.client_xact_id - T_1656 <= io.out.grant.bits.manager_xact_id - T_1662 <= UInt<1>("h01") - skip - skip - node T_1889 = and(io.in.grant.ready, T_1662) - when T_1889 : - node T_1891 = eq(T_1658, UInt<2>("h03")) - node T_1893 = and(UInt<1>("h00"), T_1891) - node T_1896 = add(T_1658, UInt<1>("h01")) - node T_1897 = tail(T_1896, 1) - node T_1898 = mux(T_1893, UInt<1>("h00"), T_1897) - T_1658 <= T_1898 - T_1662 <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_3 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module ReorderQueue_70 : + extmodule AsyncResetReg_4 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_4 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, tag : UInt<5>}}, deq : {flip valid : UInt<1>, flip tag : UInt<5>, data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} - - io is invalid - reg roq_data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk - reg roq_tags : UInt<5>[9], clk - wire T_832 : UInt<1>[9] - T_832[0] <= UInt<1>("h01") - T_832[1] <= UInt<1>("h01") - T_832[2] <= UInt<1>("h01") - T_832[3] <= UInt<1>("h01") - T_832[4] <= UInt<1>("h01") - T_832[5] <= UInt<1>("h01") - T_832[6] <= UInt<1>("h01") - T_832[7] <= UInt<1>("h01") - T_832[8] <= UInt<1>("h01") - reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_832)) - node T_865 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) - node T_866 = mux(roq_free[6], UInt<3>("h06"), T_865) - node T_867 = mux(roq_free[5], UInt<3>("h05"), T_866) - node T_868 = mux(roq_free[4], UInt<3>("h04"), T_867) - node T_869 = mux(roq_free[3], UInt<2>("h03"), T_868) - node T_870 = mux(roq_free[2], UInt<2>("h02"), T_869) - node T_871 = mux(roq_free[1], UInt<1>("h01"), T_870) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_871) - node T_873 = eq(roq_tags[0], io.deq.tag) - node T_875 = eq(roq_free[0], UInt<1>("h00")) - node T_876 = and(T_873, T_875) - node T_877 = eq(roq_tags[1], io.deq.tag) - node T_879 = eq(roq_free[1], UInt<1>("h00")) - node T_880 = and(T_877, T_879) - node T_881 = eq(roq_tags[2], io.deq.tag) - node T_883 = eq(roq_free[2], UInt<1>("h00")) - node T_884 = and(T_881, T_883) - node T_885 = eq(roq_tags[3], io.deq.tag) - node T_887 = eq(roq_free[3], UInt<1>("h00")) - node T_888 = and(T_885, T_887) - node T_889 = eq(roq_tags[4], io.deq.tag) - node T_891 = eq(roq_free[4], UInt<1>("h00")) - node T_892 = and(T_889, T_891) - node T_893 = eq(roq_tags[5], io.deq.tag) - node T_895 = eq(roq_free[5], UInt<1>("h00")) - node T_896 = and(T_893, T_895) - node T_897 = eq(roq_tags[6], io.deq.tag) - node T_899 = eq(roq_free[6], UInt<1>("h00")) - node T_900 = and(T_897, T_899) - node T_901 = eq(roq_tags[7], io.deq.tag) - node T_903 = eq(roq_free[7], UInt<1>("h00")) - node T_904 = and(T_901, T_903) - node T_905 = eq(roq_tags[8], io.deq.tag) - node T_907 = eq(roq_free[8], UInt<1>("h00")) - node T_908 = and(T_905, T_907) - node T_918 = mux(T_904, UInt<3>("h07"), UInt<4>("h08")) - node T_919 = mux(T_900, UInt<3>("h06"), T_918) - node T_920 = mux(T_896, UInt<3>("h05"), T_919) - node T_921 = mux(T_892, UInt<3>("h04"), T_920) - node T_922 = mux(T_888, UInt<2>("h03"), T_921) - node T_923 = mux(T_884, UInt<2>("h02"), T_922) - node T_924 = mux(T_880, UInt<1>("h01"), T_923) - node roq_deq_addr = mux(T_876, UInt<1>("h00"), T_924) - node T_926 = or(roq_free[0], roq_free[1]) - node T_927 = or(T_926, roq_free[2]) - node T_928 = or(T_927, roq_free[3]) - node T_929 = or(T_928, roq_free[4]) - node T_930 = or(T_929, roq_free[5]) - node T_931 = or(T_930, roq_free[6]) - node T_932 = or(T_931, roq_free[7]) - node T_933 = or(T_932, roq_free[8]) - io.enq.ready <= T_933 - io.deq.data <- roq_data[roq_deq_addr] - node T_958 = or(T_876, T_880) - node T_959 = or(T_958, T_884) - node T_960 = or(T_959, T_888) - node T_961 = or(T_960, T_892) - node T_962 = or(T_961, T_896) - node T_963 = or(T_962, T_900) - node T_964 = or(T_963, T_904) - node T_965 = or(T_964, T_908) - io.deq.matches <= T_965 - node T_966 = and(io.enq.valid, io.enq.ready) - when T_966 : - roq_data[roq_enq_addr] <- io.enq.bits.data - roq_tags[roq_enq_addr] <= io.enq.bits.tag - roq_free[roq_enq_addr] <= UInt<1>("h00") - skip - when io.deq.valid : - roq_free[roq_deq_addr] <= UInt<1>("h01") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module Arbiter : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_4 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_5 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_5 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} - - io is invalid - wire T_658 : UInt<1> - T_658 is invalid - io.out.valid <= io.in[T_658].valid - io.out.bits <- io.in[T_658].bits - io.chosen <= T_658 - io.in[T_658].ready <= UInt<1>("h00") - node T_839 = or(UInt<1>("h00"), io.in[0].valid) - node T_841 = eq(T_839, UInt<1>("h00")) - node T_843 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_844 = mux(UInt<1>("h00"), T_843, UInt<1>("h01")) - node T_845 = and(T_844, io.out.ready) - io.in[0].ready <= T_845 - node T_847 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_848 = mux(UInt<1>("h00"), T_847, T_841) - node T_849 = and(T_848, io.out.ready) - io.in[1].ready <= T_849 - node T_852 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_853 = mux(UInt<1>("h00"), UInt<1>("h01"), T_852) - T_658 <= T_853 - - module NastiIOTileLinkIOConverter : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_5 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_6 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_6 : + input clock : Clock input reset : UInt<1> - output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - - io is invalid - wire T_685 : UInt<3>[3] - T_685[0] <= UInt<3>("h02") - T_685[1] <= UInt<3>("h03") - T_685[2] <= UInt<3>("h04") - node T_690 = eq(T_685[0], io.tl.acquire.bits.a_type) - node T_691 = eq(T_685[1], io.tl.acquire.bits.a_type) - node T_692 = eq(T_685[2], io.tl.acquire.bits.a_type) - node T_694 = or(UInt<1>("h00"), T_690) - node T_695 = or(T_694, T_691) - node T_696 = or(T_695, T_692) - node has_data = and(io.tl.acquire.bits.is_builtin_type, T_696) - wire T_702 : UInt<3>[3] - T_702[0] <= UInt<3>("h02") - T_702[1] <= UInt<3>("h00") - T_702[2] <= UInt<3>("h04") - node T_707 = eq(T_702[0], io.tl.acquire.bits.a_type) - node T_708 = eq(T_702[1], io.tl.acquire.bits.a_type) - node T_709 = eq(T_702[2], io.tl.acquire.bits.a_type) - node T_711 = or(UInt<1>("h00"), T_707) - node T_712 = or(T_711, T_708) - node T_713 = or(T_712, T_709) - node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_713) - node T_716 = and(UInt<1>("h01"), io.tl.acquire.bits.is_builtin_type) - wire T_719 : UInt<3>[1] - T_719[0] <= UInt<3>("h03") - node T_722 = eq(T_719[0], io.tl.acquire.bits.a_type) - node T_724 = or(UInt<1>("h00"), T_722) - node is_multibeat = and(T_716, T_724) - node T_726 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_727 = and(T_726, is_multibeat) - reg tl_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_727 : - node T_731 = eq(tl_cnt_out, UInt<3>("h07")) - node T_733 = and(UInt<1>("h00"), T_731) - node T_736 = add(tl_cnt_out, UInt<1>("h01")) - node T_737 = tail(T_736, 1) - node T_738 = mux(T_733, UInt<1>("h00"), T_737) - tl_cnt_out <= T_738 - skip - node tl_wrap_out = and(T_727, T_731) - node T_741 = eq(has_data, UInt<1>("h00")) - node get_valid = and(io.tl.acquire.valid, T_741) - node put_valid = and(io.tl.acquire.valid, has_data) - inst roq of ReorderQueue_70 - roq.io is invalid - roq.clk <= clk - roq.reset <= reset - reg w_inflight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node aw_ready = or(w_inflight, io.nasti.aw.ready) - node T_772 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_774 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) - node T_775 = and(T_772, T_774) - reg nasti_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_775 : - node T_779 = eq(nasti_cnt_out, UInt<3>("h07")) - node T_781 = and(UInt<1>("h00"), T_779) - node T_784 = add(nasti_cnt_out, UInt<1>("h01")) - node T_785 = tail(T_784, 1) - node T_786 = mux(T_781, UInt<1>("h00"), T_785) - nasti_cnt_out <= T_786 - skip - node nasti_wrap_out = and(T_775, T_779) - node T_788 = and(get_valid, io.nasti.ar.ready) - roq.io.enq.valid <= T_788 - roq.io.enq.bits.tag <= io.nasti.ar.bits.id - roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat - node T_789 = bits(io.tl.acquire.bits.union, 11, 9) - roq.io.enq.bits.data.byteOff <= T_789 - roq.io.enq.bits.data.subblock <= is_subblock - node T_790 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_791 = or(nasti_wrap_out, roq.io.deq.data.subblock) - node T_792 = and(T_790, T_791) - roq.io.deq.valid <= T_792 - roq.io.deq.tag <= io.nasti.r.bits.id - node T_793 = and(get_valid, roq.io.enq.ready) - io.nasti.ar.valid <= T_793 - node T_794 = bits(io.tl.acquire.bits.union, 11, 9) - node T_795 = cat(io.tl.acquire.bits.addr_beat, T_794) - node T_796 = cat(io.tl.acquire.bits.addr_block, T_795) - node T_797 = bits(io.tl.acquire.bits.union, 8, 6) - node T_806 = eq(UInt<3>("h07"), T_797) - node T_807 = mux(T_806, UInt<2>("h03"), UInt<3>("h07")) - node T_808 = eq(UInt<3>("h03"), T_797) - node T_809 = mux(T_808, UInt<2>("h03"), T_807) - node T_810 = eq(UInt<3>("h02"), T_797) - node T_811 = mux(T_810, UInt<2>("h02"), T_809) - node T_812 = eq(UInt<3>("h05"), T_797) - node T_813 = mux(T_812, UInt<1>("h01"), T_811) - node T_814 = eq(UInt<3>("h01"), T_797) - node T_815 = mux(T_814, UInt<1>("h01"), T_813) - node T_816 = eq(UInt<3>("h04"), T_797) - node T_817 = mux(T_816, UInt<1>("h00"), T_815) - node T_818 = eq(UInt<3>("h00"), T_797) - node T_819 = mux(T_818, UInt<1>("h00"), T_817) - node T_821 = mux(is_subblock, T_819, UInt<2>("h03")) - node T_824 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07")) - wire T_837 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_837 is invalid - T_837.id <= io.tl.acquire.bits.client_xact_id - T_837.addr <= T_796 - T_837.len <= T_824 - T_837.size <= T_821 - T_837.burst <= UInt<2>("h01") - T_837.lock <= UInt<1>("h00") - T_837.cache <= UInt<1>("h00") - T_837.prot <= UInt<1>("h00") - T_837.qos <= UInt<1>("h00") - T_837.region <= UInt<1>("h00") - T_837.user <= UInt<1>("h00") - io.nasti.ar.bits <- T_837 - node T_856 = eq(w_inflight, UInt<1>("h00")) - node T_857 = and(put_valid, io.nasti.w.ready) - node T_858 = and(T_857, T_856) - io.nasti.aw.valid <= T_858 - node T_859 = bits(io.tl.acquire.bits.union, 11, 9) - node T_860 = cat(io.tl.acquire.bits.addr_beat, T_859) - node T_861 = cat(io.tl.acquire.bits.addr_block, T_860) - node T_865 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00")) - wire T_878 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_878 is invalid - T_878.id <= io.tl.acquire.bits.client_xact_id - T_878.addr <= T_861 - T_878.len <= T_865 - T_878.size <= UInt<2>("h03") - T_878.burst <= UInt<2>("h01") - T_878.lock <= UInt<1>("h00") - T_878.cache <= UInt<4>("h00") - T_878.prot <= UInt<3>("h00") - T_878.qos <= UInt<4>("h00") - T_878.region <= UInt<4>("h00") - T_878.user <= UInt<1>("h00") - io.nasti.aw.bits <- T_878 - node T_896 = and(put_valid, aw_ready) - io.nasti.w.valid <= T_896 - node T_899 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) - node T_900 = and(io.tl.acquire.bits.is_builtin_type, T_899) - wire T_903 : UInt<1>[1] - T_903[0] <= UInt<1>("h01") - node T_907 = sub(UInt<8>("h00"), T_903[0]) - node T_908 = tail(T_907, 1) - wire T_910 : UInt<8>[1] - T_910[0] <= T_908 - node T_914 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) - node T_915 = and(io.tl.acquire.bits.is_builtin_type, T_914) - node T_917 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) - node T_918 = and(io.tl.acquire.bits.is_builtin_type, T_917) - node T_919 = or(T_915, T_918) - node T_920 = bits(io.tl.acquire.bits.union, 8, 1) - node T_922 = mux(T_919, T_920, UInt<8>("h00")) - node T_923 = mux(T_900, T_910[0], T_922) - node T_924 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_925 = and(T_924, is_subblock) - node T_926 = or(tl_wrap_out, T_925) - wire T_932 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_932 is invalid - node T_938 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_939 = cat(T_938, T_938) - node T_940 = cat(T_939, T_939) - T_932.strb <= T_940 - T_932.data <= io.tl.acquire.bits.data - T_932.last <= T_926 - T_932.user <= UInt<1>("h00") - T_932.strb <= T_923 - io.nasti.w.bits <- T_932 - node T_942 = and(aw_ready, io.nasti.w.ready) - node T_943 = and(roq.io.enq.ready, io.nasti.ar.ready) - node T_944 = mux(has_data, T_942, T_943) - io.tl.acquire.ready <= T_944 - node T_946 = eq(w_inflight, UInt<1>("h00")) - node T_947 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_948 = and(T_946, T_947) - node T_949 = and(T_948, is_multibeat) - when T_949 : - w_inflight <= UInt<1>("h01") - skip - when w_inflight : - when tl_wrap_out : - w_inflight <= UInt<1>("h00") - skip - skip - node T_952 = and(io.tl.grant.ready, io.tl.grant.valid) - wire T_956 : UInt<3>[1] - T_956[0] <= UInt<3>("h05") - node T_959 = eq(T_956[0], io.tl.grant.bits.g_type) - node T_961 = or(UInt<1>("h00"), T_959) - wire T_963 : UInt<1>[1] - T_963[0] <= UInt<1>("h00") - node T_966 = eq(T_963[0], io.tl.grant.bits.g_type) - node T_968 = or(UInt<1>("h00"), T_966) - node T_969 = mux(io.tl.grant.bits.is_builtin_type, T_961, T_968) - node T_970 = and(UInt<1>("h01"), T_969) - node T_971 = and(T_952, T_970) - reg tl_cnt_in : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_971 : - node T_975 = eq(tl_cnt_in, UInt<3>("h07")) - node T_977 = and(UInt<1>("h00"), T_975) - node T_980 = add(tl_cnt_in, UInt<1>("h01")) - node T_981 = tail(T_980, 1) - node T_982 = mux(T_977, UInt<1>("h00"), T_981) - tl_cnt_in <= T_982 - skip - node tl_wrap_in = and(T_971, T_975) - inst gnt_arb of Arbiter - gnt_arb.io is invalid - gnt_arb.clk <= clk - gnt_arb.reset <= reset - io.tl.grant <- gnt_arb.io.out - node T_1014 = cat(roq.io.deq.data.byteOff, UInt<3>("h00")) - node T_1015 = dshl(io.nasti.r.bits.data, T_1014) - node r_aligned_data = mux(roq.io.deq.data.subblock, T_1015, io.nasti.r.bits.data) - gnt_arb.io.in[0].valid <= io.nasti.r.valid - io.nasti.r.ready <= gnt_arb.io.in[0].ready - node T_1020 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) - node T_1022 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) - wire T_1050 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1050 is invalid - T_1050.is_builtin_type <= UInt<1>("h01") - T_1050.g_type <= T_1020 - T_1050.client_xact_id <= io.nasti.r.bits.id - T_1050.manager_xact_id <= UInt<1>("h00") - T_1050.addr_beat <= T_1022 - T_1050.data <= r_aligned_data - gnt_arb.io.in[0].bits <- T_1050 - gnt_arb.io.in[1].valid <= io.nasti.b.valid - io.nasti.b.ready <= gnt_arb.io.in[1].ready - wire T_1109 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1109 is invalid - T_1109.is_builtin_type <= UInt<1>("h01") - T_1109.g_type <= UInt<3>("h03") - T_1109.client_xact_id <= io.nasti.b.bits.id - T_1109.manager_xact_id <= UInt<1>("h00") - T_1109.addr_beat <= UInt<1>("h00") - T_1109.data <= UInt<1>("h00") - gnt_arb.io.in[1].bits <- T_1109 - node T_1137 = eq(io.nasti.r.valid, UInt<1>("h00")) - node T_1139 = eq(io.nasti.r.bits.resp, UInt<1>("h00")) - node T_1140 = or(T_1137, T_1139) - node T_1142 = eq(reset, UInt<1>("h00")) - when T_1142 : - node T_1144 = eq(T_1140, UInt<1>("h00")) - when T_1144 : - node T_1146 = eq(reset, UInt<1>("h00")) - when T_1146 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI read error") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1148 = eq(io.nasti.b.valid, UInt<1>("h00")) - node T_1150 = eq(io.nasti.b.bits.resp, UInt<1>("h00")) - node T_1151 = or(T_1148, T_1150) - node T_1153 = eq(reset, UInt<1>("h00")) - when T_1153 : - node T_1155 = eq(T_1151, UInt<1>("h00")) - when T_1155 : - node T_1157 = eq(reset, UInt<1>("h00")) - when T_1157 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI write error") - skip - stop(clk, UInt<1>(1), 1) - skip - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_6 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module ClientTileLinkIOWrapper_71 : + extmodule AsyncResetReg_7 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_7 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - io.out.acquire <- io.in.acquire - io.in.grant <- io.out.grant - io.out.probe.ready <= UInt<1>("h01") - io.out.release.valid <= UInt<1>("h00") + io is invalid + inst reg_0 of AsyncResetReg_7 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module ClientTileLinkEnqueuer : + extmodule AsyncResetReg_8 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_8 : + input clock : Clock input reset : UInt<1> - output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - io.outer.acquire <- io.inner.acquire - io.inner.probe <- io.outer.probe - io.outer.release <- io.inner.release - io.inner.grant <- io.outer.grant + io is invalid + inst reg_0 of AsyncResetReg_8 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module Queue_74 : + extmodule AsyncResetReg_9 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_9 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, count : UInt<4>} - - io is invalid - cmem ram : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}[8] - reg T_62 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_64 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_62, T_64) - node T_69 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_69) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_75 = and(io.enq.ready, io.enq.valid) - node T_77 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_75, T_77) - node T_79 = and(io.deq.ready, io.deq.valid) - node T_81 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_79, T_81) - when do_enq : - infer mport T_83 = ram[T_62], clk - T_83 <- io.enq.bits - node T_89 = eq(T_62, UInt<3>("h07")) - node T_91 = and(UInt<1>("h00"), T_89) - node T_94 = add(T_62, UInt<1>("h01")) - node T_95 = tail(T_94, 1) - node T_96 = mux(T_91, UInt<1>("h00"), T_95) - T_62 <= T_96 - skip - when do_deq : - node T_98 = eq(T_64, UInt<3>("h07")) - node T_100 = and(UInt<1>("h00"), T_98) - node T_103 = add(T_64, UInt<1>("h01")) - node T_104 = tail(T_103, 1) - node T_105 = mux(T_100, UInt<1>("h00"), T_104) - T_64 <= T_105 - skip - node T_106 = neq(do_enq, do_deq) - when T_106 : - maybe_full <= do_enq - skip - node T_108 = eq(empty, UInt<1>("h00")) - node T_110 = and(UInt<1>("h00"), io.enq.valid) - node T_111 = or(T_108, T_110) - io.deq.valid <= T_111 - node T_113 = eq(full, UInt<1>("h00")) - node T_115 = and(UInt<1>("h00"), io.deq.ready) - node T_116 = or(T_113, T_115) - io.enq.ready <= T_116 - infer mport T_117 = ram[T_64], clk - node T_122 = mux(maybe_flow, io.enq.bits, T_117) - io.deq.bits <- T_122 - node T_127 = sub(T_62, T_64) - node ptr_diff = tail(T_127, 1) - node T_129 = and(maybe_full, ptr_match) - node T_130 = cat(T_129, ptr_diff) - io.count <= T_130 - - module Queue_75 : - input clk : Clock + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_9 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<4>} - - io is invalid - cmem ram : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}[8] - reg T_71 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_73 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_71, T_73) - node T_78 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_78) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_84 = and(io.enq.ready, io.enq.valid) - node T_86 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_84, T_86) - node T_88 = and(io.deq.ready, io.deq.valid) - node T_90 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_88, T_90) - when do_enq : - infer mport T_92 = ram[T_71], clk - T_92 <- io.enq.bits - node T_99 = eq(T_71, UInt<3>("h07")) - node T_101 = and(UInt<1>("h00"), T_99) - node T_104 = add(T_71, UInt<1>("h01")) - node T_105 = tail(T_104, 1) - node T_106 = mux(T_101, UInt<1>("h00"), T_105) - T_71 <= T_106 - skip - when do_deq : - node T_108 = eq(T_73, UInt<3>("h07")) - node T_110 = and(UInt<1>("h00"), T_108) - node T_113 = add(T_73, UInt<1>("h01")) - node T_114 = tail(T_113, 1) - node T_115 = mux(T_110, UInt<1>("h00"), T_114) - T_73 <= T_115 - skip - node T_116 = neq(do_enq, do_deq) - when T_116 : - maybe_full <= do_enq - skip - node T_118 = eq(empty, UInt<1>("h00")) - node T_120 = and(UInt<1>("h00"), io.enq.valid) - node T_121 = or(T_118, T_120) - io.deq.valid <= T_121 - node T_123 = eq(full, UInt<1>("h00")) - node T_125 = and(UInt<1>("h00"), io.deq.ready) - node T_126 = or(T_123, T_125) - io.enq.ready <= T_126 - infer mport T_127 = ram[T_73], clk - node T_133 = mux(maybe_flow, io.enq.bits, T_127) - io.deq.bits <- T_133 - node T_139 = sub(T_71, T_73) - node ptr_diff = tail(T_139, 1) - node T_141 = and(maybe_full, ptr_match) - node T_142 = cat(T_141, ptr_diff) - io.count <= T_142 - - module Queue_76 : + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst sink_valid_sync_0 of AsyncResetRegVec_6 @[AsyncQueue.scala 18:14] + sink_valid_sync_0.io is invalid + sink_valid_sync_0.clock <= clock + sink_valid_sync_0.reset <= reset + inst sink_valid_sync_1 of AsyncResetRegVec_7 @[AsyncQueue.scala 18:14] + sink_valid_sync_1.io is invalid + sink_valid_sync_1.clock <= clock + sink_valid_sync_1.reset <= reset + inst sink_valid_sync_2 of AsyncResetRegVec_8 @[AsyncQueue.scala 18:14] + sink_valid_sync_2.io is invalid + sink_valid_sync_2.clock <= clock + sink_valid_sync_2.reset <= reset + inst sink_valid_sync_3 of AsyncResetRegVec_9 @[AsyncQueue.scala 18:14] + sink_valid_sync_3.io is invalid + sink_valid_sync_3.clock <= clock + sink_valid_sync_3.reset <= reset + sink_valid_sync_3.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_valid_sync_3.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + sink_valid_sync_0.io.d <= sink_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_1.io.d <= sink_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_2.io.d <= sink_valid_sync_3.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_10 = bits(sink_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_10 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_10 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_10 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - - io is invalid - cmem ram : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}[2] - reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_53, T_55) - node T_60 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_60) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_66 = and(io.enq.ready, io.enq.valid) - node T_68 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_66, T_68) - node T_70 = and(io.deq.ready, io.deq.valid) - node T_72 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_70, T_72) - when do_enq : - infer mport T_74 = ram[T_53], clk - T_74 <- io.enq.bits - node T_79 = eq(T_53, UInt<1>("h01")) - node T_81 = and(UInt<1>("h00"), T_79) - node T_84 = add(T_53, UInt<1>("h01")) - node T_85 = tail(T_84, 1) - node T_86 = mux(T_81, UInt<1>("h00"), T_85) - T_53 <= T_86 - skip - when do_deq : - node T_88 = eq(T_55, UInt<1>("h01")) - node T_90 = and(UInt<1>("h00"), T_88) - node T_93 = add(T_55, UInt<1>("h01")) - node T_94 = tail(T_93, 1) - node T_95 = mux(T_90, UInt<1>("h00"), T_94) - T_55 <= T_95 - skip - node T_96 = neq(do_enq, do_deq) - when T_96 : - maybe_full <= do_enq - skip - node T_98 = eq(empty, UInt<1>("h00")) - node T_100 = and(UInt<1>("h00"), io.enq.valid) - node T_101 = or(T_98, T_100) - io.deq.valid <= T_101 - node T_103 = eq(full, UInt<1>("h00")) - node T_105 = and(UInt<1>("h00"), io.deq.ready) - node T_106 = or(T_103, T_105) - io.enq.ready <= T_106 - infer mport T_107 = ram[T_55], clk - node T_111 = mux(maybe_flow, io.enq.bits, T_107) - io.deq.bits <- T_111 - node T_115 = sub(T_53, T_55) - node ptr_diff = tail(T_115, 1) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - io.count <= T_118 - - module RTC : - input clk : Clock + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_10 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_1 : + input clock : Clock input reset : UInt<1> - output io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - - io is invalid - wire addrTable : UInt<31>[1] - addrTable[0] <= UInt<31>("h04000b808") - reg rtc : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) - reg T_217 : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) - node rtc_tick = eq(T_217, UInt<7>("h063")) - node T_221 = and(UInt<1>("h01"), rtc_tick) - node T_224 = add(T_217, UInt<1>("h01")) - node T_225 = tail(T_224, 1) - node T_226 = mux(T_221, UInt<1>("h00"), T_225) - T_217 <= T_226 - reg sending_addr : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sending_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_233 : UInt<1>[1] - T_233[0] <= UInt<1>("h01") - reg send_acked : UInt<1>[1], clk with : (reset => (reset, T_233)) - wire coreId : UInt<1> - coreId is invalid - when rtc_tick : - node T_244 = add(rtc, UInt<1>("h01")) - node T_245 = tail(T_244, 1) - rtc <= T_245 - wire T_248 : UInt<1>[1] - T_248[0] <= UInt<1>("h00") - send_acked <= T_248 - sending_addr <= UInt<1>("h01") - sending_data <= UInt<1>("h01") - skip - node T_253 = and(io.aw.ready, io.aw.valid) - when T_253 : - sending_addr <= UInt<1>("h00") - skip - node T_255 = and(io.w.ready, io.w.valid) - when T_255 : - sending_addr <= UInt<1>("h00") - skip - coreId <= UInt<1>("h00") - node T_258 = and(io.b.ready, io.b.valid) - when T_258 : - send_acked[io.b.bits.id] <= UInt<1>("h01") - skip - io.aw.valid <= sending_addr - wire T_276 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_276 is invalid - T_276.id <= coreId - T_276.addr <= addrTable[coreId] - T_276.len <= UInt<1>("h00") - T_276.size <= UInt<2>("h03") - T_276.burst <= UInt<2>("h01") - T_276.lock <= UInt<1>("h00") - T_276.cache <= UInt<4>("h00") - T_276.prot <= UInt<3>("h00") - T_276.qos <= UInt<4>("h00") - T_276.region <= UInt<4>("h00") - T_276.user <= UInt<1>("h00") - io.aw.bits <- T_276 - io.w.valid <= sending_data - wire T_300 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_300 is invalid - node T_306 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_307 = cat(T_306, T_306) - node T_308 = cat(T_307, T_307) - T_300.strb <= T_308 - T_300.data <= rtc - T_300.last <= UInt<1>("h01") - T_300.user <= UInt<1>("h00") - io.w.bits <- T_300 - io.b.ready <= UInt<1>("h01") - io.ar.valid <= UInt<1>("h00") - io.r.ready <= UInt<1>("h00") - node T_314 = eq(rtc_tick, UInt<1>("h00")) - node T_315 = or(T_314, send_acked[0]) - node T_317 = eq(reset, UInt<1>("h00")) - when T_317 : - node T_319 = eq(T_315, UInt<1>("h00")) - when T_319 : - node T_321 = eq(reset, UInt<1>("h00")) - when T_321 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick") - skip - stop(clk, UInt<1>(1), 1) - skip - skip + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst source_extend_sync_0 of AsyncResetRegVec_10 @[AsyncQueue.scala 18:14] + source_extend_sync_0.io is invalid + source_extend_sync_0.clock <= clock + source_extend_sync_0.reset <= reset + source_extend_sync_0.io.d <= io.in @[AsyncQueue.scala 20:21] + source_extend_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + node _T_7 = bits(source_extend_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_7 @[AsyncQueue.scala 35:10] - module SmiIONastiReadIOConverter : + extmodule AsyncResetReg_11 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_11 : + input clock : Clock input reset : UInt<1> - output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg nWords : UInt<1>, clk - reg nBeats : UInt<8>, clk - reg addr : UInt<12>, clk - reg id : UInt<5>, clk - reg byteOff : UInt<3>, clk - reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_141 : UInt<64>[1] - T_141[0] <= UInt<64>("h00") - reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141)) - node T_149 = eq(state, UInt<1>("h00")) - io.ar.ready <= T_149 - node T_150 = eq(state, UInt<1>("h01")) - node T_152 = eq(sendDone, UInt<1>("h00")) - node T_153 = and(T_150, T_152) - io.smi.req.valid <= T_153 - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.bits.addr <= addr - node T_155 = eq(state, UInt<1>("h01")) - io.smi.resp.ready <= T_155 - node T_156 = eq(state, UInt<2>("h02")) - io.r.valid <= T_156 - node T_158 = eq(nBeats, UInt<1>("h00")) - wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166 is invalid - T_166.id <= id - T_166.data <= buffer[0] - T_166.last <= T_158 - T_166.resp <= UInt<1>("h00") - T_166.user <= UInt<1>("h00") - io.r.bits <- T_166 - node T_173 = and(io.ar.ready, io.ar.valid) - when T_173 : - node T_175 = lt(io.ar.bits.size, UInt<2>("h03")) - when T_175 : - nWords <= UInt<1>("h00") - node T_177 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_177 - skip - node T_179 = eq(T_175, UInt<1>("h00")) - when T_179 : - node T_182 = sub(io.ar.bits.size, UInt<2>("h03")) - node T_183 = tail(T_182, 1) - node T_184 = dshl(UInt<1>("h01"), T_183) - node T_186 = sub(T_184, UInt<1>("h01")) - node T_187 = tail(T_186, 1) - nWords <= T_187 - byteOff <= UInt<1>("h00") - skip - nBeats <= io.ar.bits.len - node T_189 = bits(io.ar.bits.addr, 14, 3) - addr <= T_189 - id <= io.ar.bits.id - state <= UInt<1>("h01") - skip - node T_190 = and(io.smi.req.ready, io.smi.req.valid) - when T_190 : - node T_192 = add(addr, UInt<1>("h01")) - node T_193 = tail(T_192, 1) - addr <= T_193 - node T_195 = add(sendInd, UInt<1>("h01")) - node T_196 = tail(T_195, 1) - sendInd <= T_196 - node T_197 = eq(sendInd, nWords) - sendDone <= T_197 - skip - node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_198 : - node T_200 = add(recvInd, UInt<1>("h01")) - node T_201 = tail(T_200, 1) - recvInd <= T_201 - node T_204 = cat(byteOff, UInt<3>("h00")) - node T_205 = dshr(io.smi.resp.bits, T_204) - buffer[recvInd] <= T_205 - node T_206 = eq(recvInd, nWords) - when T_206 : - state <= UInt<2>("h02") - skip - skip - node T_207 = and(io.r.ready, io.r.valid) - when T_207 : - recvInd <= UInt<1>("h00") - sendInd <= UInt<1>("h00") - sendDone <= UInt<1>("h00") - buffer[0] <= UInt<1>("h00") - node T_213 = sub(nBeats, UInt<1>("h01")) - node T_214 = tail(T_213, 1) - nBeats <= T_214 - node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) - state <= T_215 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module SmiIONastiWriteIOConverter : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_11 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_12 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_12 : + input clock : Clock input reset : UInt<1> - output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - node T_144 = eq(io.aw.valid, UInt<1>("h00")) - node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) - node T_147 = or(T_144, T_146) - node T_149 = eq(reset, UInt<1>("h00")) - when T_149 : - node T_151 = eq(T_147, UInt<1>("h00")) - when T_151 : - node T_153 = eq(reset, UInt<1>("h00")) - when T_153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg id : UInt<5>, clk - reg addr : UInt<12>, clk - reg size : UInt<3>, clk - reg strb : UInt<1>, clk - reg data : UInt<64>, clk - reg last : UInt<1>, clk - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node T_173 = eq(state, UInt<1>("h00")) - io.aw.ready <= T_173 - node T_174 = eq(state, UInt<1>("h01")) - io.w.ready <= T_174 - node T_175 = eq(state, UInt<2>("h02")) - node T_176 = bits(strb, 0, 0) - node T_177 = and(T_175, T_176) - io.smi.req.valid <= T_177 - io.smi.req.bits.rw <= UInt<1>("h01") - io.smi.req.bits.addr <= addr - node T_179 = bits(data, 63, 0) - io.smi.req.bits.data <= T_179 - node T_180 = eq(state, UInt<2>("h03")) - io.smi.resp.ready <= T_180 - node T_181 = eq(state, UInt<3>("h04")) - io.b.valid <= T_181 - wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187 is invalid - T_187.id <= id - T_187.resp <= UInt<1>("h00") - T_187.user <= UInt<1>("h00") - io.b.bits <- T_187 - node T_193 = and(io.aw.ready, io.aw.valid) - when T_193 : - node T_194 = bits(io.aw.bits.addr, 14, 3) - addr <= T_194 - id <= io.aw.bits.id - size <= io.aw.bits.size - last <= UInt<1>("h00") - state <= UInt<1>("h01") - skip - node T_196 = and(io.w.ready, io.w.valid) - when T_196 : - last <= io.w.bits.last - node T_199 = dshl(UInt<1>("h01"), size) - node T_200 = dshl(UInt<1>("h01"), T_199) - node T_202 = sub(T_200, UInt<1>("h01")) - node T_203 = tail(T_202, 1) - node T_204 = and(T_203, io.w.bits.strb) - node T_205 = bits(T_204, 0, 0) - wire T_207 : UInt<1>[1] - T_207[0] <= T_205 - strb <= T_207[0] - data <= io.w.bits.data - state <= UInt<2>("h02") - skip - node T_210 = eq(state, UInt<2>("h02")) - when T_210 : - node T_212 = eq(strb, UInt<1>("h00")) - when T_212 : - node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01")) - state <= T_213 - skip - node T_214 = bits(strb, 0, 0) - node T_216 = eq(T_214, UInt<1>("h00")) - node T_217 = or(io.smi.req.ready, T_216) - node T_219 = eq(T_212, UInt<1>("h00")) - node T_220 = and(T_219, T_217) - when T_220 : - node T_221 = dshr(strb, UInt<1>("h01")) - strb <= T_221 - node T_223 = cat(UInt<1>("h01"), UInt<6>("h00")) - node T_224 = dshr(data, T_223) - data <= T_224 - node T_225 = add(addr, UInt<1>("h01")) - node T_226 = tail(T_225, 1) - addr <= T_226 - skip - skip - node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_227 : - state <= UInt<3>("h04") - skip - node T_228 = and(io.b.ready, io.b.valid) - when T_228 : - state <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_12 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module RRArbiter_77 : + extmodule AsyncResetReg_13 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_13 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>} - - io is invalid - wire T_130 : UInt<1> - T_130 is invalid - io.out.valid <= io.in[T_130].valid - io.out.bits <- io.in[T_130].bits - io.chosen <= T_130 - io.in[T_130].ready <= UInt<1>("h00") - reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_168 = gt(UInt<1>("h00"), T_167) - node T_169 = and(io.in[0].valid, T_168) - node T_171 = gt(UInt<1>("h01"), T_167) - node T_172 = and(io.in[1].valid, T_171) - node T_175 = or(UInt<1>("h00"), T_169) - node T_177 = eq(T_175, UInt<1>("h00")) - node T_179 = or(UInt<1>("h00"), T_169) - node T_180 = or(T_179, T_172) - node T_182 = eq(T_180, UInt<1>("h00")) - node T_184 = or(UInt<1>("h00"), T_169) - node T_185 = or(T_184, T_172) - node T_186 = or(T_185, io.in[0].valid) - node T_188 = eq(T_186, UInt<1>("h00")) - node T_190 = gt(UInt<1>("h00"), T_167) - node T_191 = and(UInt<1>("h01"), T_190) - node T_192 = or(T_191, T_182) - node T_194 = gt(UInt<1>("h01"), T_167) - node T_195 = and(T_177, T_194) - node T_196 = or(T_195, T_188) - node T_198 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_199 = mux(UInt<1>("h00"), T_198, T_192) - node T_200 = and(T_199, io.out.ready) - io.in[0].ready <= T_200 - node T_202 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_203 = mux(UInt<1>("h00"), T_202, T_196) - node T_204 = and(T_203, io.out.ready) - io.in[1].ready <= T_204 - node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_209 = gt(UInt<1>("h01"), T_167) - node T_210 = and(io.in[1].valid, T_209) - node T_212 = mux(T_210, UInt<1>("h01"), T_207) - node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212) - T_130 <= T_213 - node T_214 = and(io.out.ready, io.out.valid) - when T_214 : - T_167 <= T_130 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module SmiArbiter : - input clk : Clock + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_13 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_2 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg choice : UInt<1>, clk - inst req_arb of RRArbiter_77 - req_arb.io is invalid - req_arb.clk <= clk - req_arb.reset <= reset - req_arb.io.in[0] <- io.in[0].req - req_arb.io.in[1] <- io.in[1].req - node T_313 = eq(wait_resp, UInt<1>("h00")) - node T_314 = and(io.out.req.ready, T_313) - req_arb.io.out.ready <= T_314 - io.out.req.bits <- req_arb.io.out.bits - node T_316 = eq(wait_resp, UInt<1>("h00")) - node T_317 = and(req_arb.io.out.valid, T_316) - io.out.req.valid <= T_317 - node T_318 = and(io.out.req.ready, io.out.req.valid) - when T_318 : - choice <= req_arb.io.chosen - wait_resp <= UInt<1>("h01") - skip - node T_320 = and(io.out.resp.ready, io.out.resp.valid) - when T_320 : - wait_resp <= UInt<1>("h00") - skip - io.in[0].resp.bits <= io.out.resp.bits - node T_323 = eq(choice, UInt<1>("h00")) - node T_324 = and(io.out.resp.valid, T_323) - io.in[0].resp.valid <= T_324 - io.in[1].resp.bits <= io.out.resp.bits - node T_326 = eq(choice, UInt<1>("h01")) - node T_327 = and(io.out.resp.valid, T_326) - io.in[1].resp.valid <= T_327 - io.out.resp.ready <= io.in[choice].resp.ready - - module SmiIONastiIOConverter : + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst source_valid_sync_0 of AsyncResetRegVec_11 @[AsyncQueue.scala 18:14] + source_valid_sync_0.io is invalid + source_valid_sync_0.clock <= clock + source_valid_sync_0.reset <= reset + inst source_valid_sync_1 of AsyncResetRegVec_12 @[AsyncQueue.scala 18:14] + source_valid_sync_1.io is invalid + source_valid_sync_1.clock <= clock + source_valid_sync_1.reset <= reset + inst source_valid_sync_2 of AsyncResetRegVec_13 @[AsyncQueue.scala 18:14] + source_valid_sync_2.io is invalid + source_valid_sync_2.clock <= clock + source_valid_sync_2.reset <= reset + source_valid_sync_2.io.d <= io.in @[AsyncQueue.scala 20:21] + source_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + source_valid_sync_0.io.d <= source_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_1.io.d <= source_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_9 = bits(source_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_9 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_14 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_14 : + input clock : Clock input reset : UInt<1> - output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - inst reader of SmiIONastiReadIOConverter - reader.io is invalid - reader.clk <= clk - reader.reset <= reset - reader.io.ar <- io.nasti.ar - io.nasti.r <- reader.io.r - inst writer of SmiIONastiWriteIOConverter - writer.io is invalid - writer.clk <= clk - writer.reset <= reset - writer.io.aw <- io.nasti.aw - writer.io.w <- io.nasti.w - io.nasti.b <- writer.io.b - inst arb of SmiArbiter - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- reader.io.smi - arb.io.in[1] <- writer.io.smi - io.smi <- arb.io.out + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module SmiIONastiReadIOConverter_79 : - input clk : Clock + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_14 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncQueueSink : + input clock : Clock input reset : UInt<1> - output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg nWords : UInt<1>, clk - reg nBeats : UInt<8>, clk - reg addr : UInt<6>, clk - reg id : UInt<5>, clk - reg byteOff : UInt<3>, clk - reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_141 : UInt<64>[1] - T_141[0] <= UInt<64>("h00") - reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141)) - node T_149 = eq(state, UInt<1>("h00")) - io.ar.ready <= T_149 - node T_150 = eq(state, UInt<1>("h01")) - node T_152 = eq(sendDone, UInt<1>("h00")) - node T_153 = and(T_150, T_152) - io.smi.req.valid <= T_153 - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.bits.addr <= addr - node T_155 = eq(state, UInt<1>("h01")) - io.smi.resp.ready <= T_155 - node T_156 = eq(state, UInt<2>("h02")) - io.r.valid <= T_156 - node T_158 = eq(nBeats, UInt<1>("h00")) - wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166 is invalid - T_166.id <= id - T_166.data <= buffer[0] - T_166.last <= T_158 - T_166.resp <= UInt<1>("h00") - T_166.user <= UInt<1>("h00") - io.r.bits <- T_166 - node T_173 = and(io.ar.ready, io.ar.valid) - when T_173 : - node T_175 = lt(io.ar.bits.size, UInt<2>("h03")) - when T_175 : - nWords <= UInt<1>("h00") - node T_177 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_177 - skip - node T_179 = eq(T_175, UInt<1>("h00")) - when T_179 : - node T_182 = sub(io.ar.bits.size, UInt<2>("h03")) - node T_183 = tail(T_182, 1) - node T_184 = dshl(UInt<1>("h01"), T_183) - node T_186 = sub(T_184, UInt<1>("h01")) - node T_187 = tail(T_186, 1) - nWords <= T_187 - byteOff <= UInt<1>("h00") - skip - nBeats <= io.ar.bits.len - node T_189 = bits(io.ar.bits.addr, 8, 3) - addr <= T_189 - id <= io.ar.bits.id - state <= UInt<1>("h01") - skip - node T_190 = and(io.smi.req.ready, io.smi.req.valid) - when T_190 : - node T_192 = add(addr, UInt<1>("h01")) - node T_193 = tail(T_192, 1) - addr <= T_193 - node T_195 = add(sendInd, UInt<1>("h01")) - node T_196 = tail(T_195, 1) - sendInd <= T_196 - node T_197 = eq(sendInd, nWords) - sendDone <= T_197 - skip - node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_198 : - node T_200 = add(recvInd, UInt<1>("h01")) - node T_201 = tail(T_200, 1) - recvInd <= T_201 - node T_204 = cat(byteOff, UInt<3>("h00")) - node T_205 = dshr(io.smi.resp.bits, T_204) - buffer[recvInd] <= T_205 - node T_206 = eq(recvInd, nWords) - when T_206 : - state <= UInt<2>("h02") - skip - skip - node T_207 = and(io.r.ready, io.r.valid) - when T_207 : - recvInd <= UInt<1>("h00") - sendInd <= UInt<1>("h00") - sendDone <= UInt<1>("h00") - buffer[0] <= UInt<1>("h00") - node T_213 = sub(nBeats, UInt<1>("h01")) - node T_214 = tail(T_213, 1) - nBeats <= T_214 - node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) - state <= T_215 - skip + output io : {deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, ridx : UInt<1>, flip widx : UInt<1>, flip mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], flip source_reset_n : UInt<1>, ridx_valid : UInt<1>, flip widx_valid : UInt<1>} - module SmiIONastiWriteIOConverter_80 : + io is invalid + io is invalid + wire source_ready : UInt<1> + source_ready is invalid + source_ready <= UInt<1>("h01") + node _T_50 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_52 = eq(source_ready, UInt<1>("h00")) @[AsyncQueue.scala 111:49] + wire _T_54 : UInt<1> @[AsyncQueue.scala 8:27] + _T_54 is invalid @[AsyncQueue.scala 8:27] + inst ridx_bin of AsyncResetRegVec @[BlackBoxRegs.scala 89:21] + ridx_bin.io is invalid + ridx_bin.clock <= clock + ridx_bin.reset <= reset + ridx_bin.io.d <= _T_54 @[BlackBoxRegs.scala 91:14] + ridx_bin.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node _T_57 = add(ridx_bin.io.q, _T_50) @[AsyncQueue.scala 10:47] + node _T_58 = tail(_T_57, 1) @[AsyncQueue.scala 10:47] + node _T_59 = mux(_T_52, UInt<1>("h00"), _T_58) @[AsyncQueue.scala 10:23] + _T_54 <= _T_59 @[AsyncQueue.scala 10:17] + node _T_61 = dshr(_T_54, UInt<1>("h01")) @[AsyncQueue.scala 11:32] + node ridx = xor(_T_54, _T_61) @[AsyncQueue.scala 11:17] + inst widx_gray_sync_0 of AsyncResetRegVec_1 @[AsyncQueue.scala 18:14] + widx_gray_sync_0.io is invalid + widx_gray_sync_0.clock <= clock + widx_gray_sync_0.reset <= reset + inst widx_gray_sync_1 of AsyncResetRegVec_2 @[AsyncQueue.scala 18:14] + widx_gray_sync_1.io is invalid + widx_gray_sync_1.clock <= clock + widx_gray_sync_1.reset <= reset + inst widx_gray_sync_2 of AsyncResetRegVec_3 @[AsyncQueue.scala 18:14] + widx_gray_sync_2.io is invalid + widx_gray_sync_2.clock <= clock + widx_gray_sync_2.reset <= reset + widx_gray_sync_2.io.d <= io.widx @[AsyncQueue.scala 20:21] + widx_gray_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + widx_gray_sync_0.io.d <= widx_gray_sync_1.io.q @[AsyncQueue.scala 23:19] + widx_gray_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + widx_gray_sync_1.io.d <= widx_gray_sync_2.io.q @[AsyncQueue.scala 23:19] + widx_gray_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_65 = neq(ridx, widx_gray_sync_0.io.q) @[AsyncQueue.scala 113:36] + node valid = and(source_ready, _T_65) @[AsyncQueue.scala 113:28] + reg _T_78 : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_78 <- io.mem[UInt<1>("h00")] @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + io.deq.bits <- _T_78 @[AsyncQueue.scala 124:16] + inst valid_reg of AsyncResetRegVec_4 @[BlackBoxRegs.scala 89:21] + valid_reg.io is invalid + valid_reg.clock <= clock + valid_reg.reset <= reset + valid_reg.io.d <= valid @[BlackBoxRegs.scala 91:14] + valid_reg.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node valid_reg_1 = bits(valid_reg.io.q, 0, 0) @[AsyncQueue.scala 126:59] + node _T_83 = and(valid_reg_1, source_ready) @[AsyncQueue.scala 127:29] + io.deq.valid <= _T_83 @[AsyncQueue.scala 127:16] + inst ridx_gray of AsyncResetRegVec_5 @[BlackBoxRegs.scala 89:21] + ridx_gray.io is invalid + ridx_gray.clock <= clock + ridx_gray.reset <= reset + ridx_gray.io.d <= ridx @[BlackBoxRegs.scala 91:14] + ridx_gray.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + io.ridx <= ridx_gray.io.q @[AsyncQueue.scala 130:11] + io.ridx_valid <= UInt<1>("h01") @[AsyncQueue.scala 132:17] + inst AsyncValidSync of AsyncValidSync @[AsyncQueue.scala 134:31] + AsyncValidSync.io is invalid + AsyncValidSync.clock <= clock + AsyncValidSync.reset <= reset + inst AsyncValidSync_1 of AsyncValidSync_1 @[AsyncQueue.scala 135:31] + AsyncValidSync_1.io is invalid + AsyncValidSync_1.clock <= clock + AsyncValidSync_1.reset <= reset + inst AsyncValidSync_2 of AsyncValidSync_2 @[AsyncQueue.scala 136:31] + AsyncValidSync_2.io is invalid + AsyncValidSync_2.clock <= clock + AsyncValidSync_2.reset <= reset + node _T_87 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 137:37] + node _T_88 = or(reset, _T_87) @[AsyncQueue.scala 137:34] + AsyncValidSync.reset <= _T_88 @[AsyncQueue.scala 137:25] + node _T_90 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 138:37] + node _T_91 = or(reset, _T_90) @[AsyncQueue.scala 138:34] + AsyncValidSync_1.reset <= _T_91 @[AsyncQueue.scala 138:25] + AsyncValidSync.io.in <= UInt<1>("h01") @[AsyncQueue.scala 140:22] + io.ridx_valid <= AsyncValidSync.io.out @[AsyncQueue.scala 141:19] + AsyncValidSync_1.io.in <= io.widx_valid @[AsyncQueue.scala 142:25] + AsyncValidSync_2.io.in <= AsyncValidSync_1.io.out @[AsyncQueue.scala 143:24] + source_ready <= AsyncValidSync_2.io.out @[AsyncQueue.scala 144:18] + node _T_94 = eq(source_ready, UInt<1>("h00")) @[AsyncQueue.scala 146:28] + node _T_96 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 146:45] + node _T_97 = or(_T_94, _T_96) @[AsyncQueue.scala 146:42] + node _T_98 = or(_T_97, reset) @[AsyncQueue.scala 146:64] + reg _T_101 : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[AsyncQueue.scala 147:36] + _T_101 <= _T_98 @[AsyncQueue.scala 147:36] + node _T_103 = eq(_T_101, UInt<1>("h00")) @[AsyncQueue.scala 148:22] + node _T_104 = and(_T_103, _T_98) @[AsyncQueue.scala 148:45] + node _T_105 = eq(io.widx, io.ridx) @[AsyncQueue.scala 149:59] + inst AsyncResetRegVec of AsyncResetRegVec_14 @[BlackBoxRegs.scala 89:21] + AsyncResetRegVec.io is invalid + AsyncResetRegVec.clock <= clock + AsyncResetRegVec.reset <= reset + AsyncResetRegVec.io.d <= _T_105 @[BlackBoxRegs.scala 91:14] + AsyncResetRegVec.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + + extmodule AsyncResetReg_15 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_15 : + input clock : Clock input reset : UInt<1> - output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - node T_144 = eq(io.aw.valid, UInt<1>("h00")) - node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) - node T_147 = or(T_144, T_146) - node T_149 = eq(reset, UInt<1>("h00")) - when T_149 : - node T_151 = eq(T_147, UInt<1>("h00")) - when T_151 : - node T_153 = eq(reset, UInt<1>("h00")) - when T_153 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg id : UInt<5>, clk - reg addr : UInt<6>, clk - reg size : UInt<3>, clk - reg strb : UInt<1>, clk - reg data : UInt<64>, clk - reg last : UInt<1>, clk - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node T_173 = eq(state, UInt<1>("h00")) - io.aw.ready <= T_173 - node T_174 = eq(state, UInt<1>("h01")) - io.w.ready <= T_174 - node T_175 = eq(state, UInt<2>("h02")) - node T_176 = bits(strb, 0, 0) - node T_177 = and(T_175, T_176) - io.smi.req.valid <= T_177 - io.smi.req.bits.rw <= UInt<1>("h01") - io.smi.req.bits.addr <= addr - node T_179 = bits(data, 63, 0) - io.smi.req.bits.data <= T_179 - node T_180 = eq(state, UInt<2>("h03")) - io.smi.resp.ready <= T_180 - node T_181 = eq(state, UInt<3>("h04")) - io.b.valid <= T_181 - wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187 is invalid - T_187.id <= id - T_187.resp <= UInt<1>("h00") - T_187.user <= UInt<1>("h00") - io.b.bits <- T_187 - node T_193 = and(io.aw.ready, io.aw.valid) - when T_193 : - node T_194 = bits(io.aw.bits.addr, 8, 3) - addr <= T_194 - id <= io.aw.bits.id - size <= io.aw.bits.size - last <= UInt<1>("h00") - state <= UInt<1>("h01") - skip - node T_196 = and(io.w.ready, io.w.valid) - when T_196 : - last <= io.w.bits.last - node T_199 = dshl(UInt<1>("h01"), size) - node T_200 = dshl(UInt<1>("h01"), T_199) - node T_202 = sub(T_200, UInt<1>("h01")) - node T_203 = tail(T_202, 1) - node T_204 = and(T_203, io.w.bits.strb) - node T_205 = bits(T_204, 0, 0) - wire T_207 : UInt<1>[1] - T_207[0] <= T_205 - strb <= T_207[0] - data <= io.w.bits.data - state <= UInt<2>("h02") - skip - node T_210 = eq(state, UInt<2>("h02")) - when T_210 : - node T_212 = eq(strb, UInt<1>("h00")) - when T_212 : - node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01")) - state <= T_213 - skip - node T_214 = bits(strb, 0, 0) - node T_216 = eq(T_214, UInt<1>("h00")) - node T_217 = or(io.smi.req.ready, T_216) - node T_219 = eq(T_212, UInt<1>("h00")) - node T_220 = and(T_219, T_217) - when T_220 : - node T_221 = dshr(strb, UInt<1>("h01")) - strb <= T_221 - node T_223 = cat(UInt<1>("h01"), UInt<6>("h00")) - node T_224 = dshr(data, T_223) - data <= T_224 - node T_225 = add(addr, UInt<1>("h01")) - node T_226 = tail(T_225, 1) - addr <= T_226 - skip - skip - node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_227 : - state <= UInt<3>("h04") - skip - node T_228 = and(io.b.ready, io.b.valid) - when T_228 : - state <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_15 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module RRArbiter_82 : + extmodule AsyncResetReg_16 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_16 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>} - - io is invalid - wire T_130 : UInt<1> - T_130 is invalid - io.out.valid <= io.in[T_130].valid - io.out.bits <- io.in[T_130].bits - io.chosen <= T_130 - io.in[T_130].ready <= UInt<1>("h00") - reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_168 = gt(UInt<1>("h00"), T_167) - node T_169 = and(io.in[0].valid, T_168) - node T_171 = gt(UInt<1>("h01"), T_167) - node T_172 = and(io.in[1].valid, T_171) - node T_175 = or(UInt<1>("h00"), T_169) - node T_177 = eq(T_175, UInt<1>("h00")) - node T_179 = or(UInt<1>("h00"), T_169) - node T_180 = or(T_179, T_172) - node T_182 = eq(T_180, UInt<1>("h00")) - node T_184 = or(UInt<1>("h00"), T_169) - node T_185 = or(T_184, T_172) - node T_186 = or(T_185, io.in[0].valid) - node T_188 = eq(T_186, UInt<1>("h00")) - node T_190 = gt(UInt<1>("h00"), T_167) - node T_191 = and(UInt<1>("h01"), T_190) - node T_192 = or(T_191, T_182) - node T_194 = gt(UInt<1>("h01"), T_167) - node T_195 = and(T_177, T_194) - node T_196 = or(T_195, T_188) - node T_198 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_199 = mux(UInt<1>("h00"), T_198, T_192) - node T_200 = and(T_199, io.out.ready) - io.in[0].ready <= T_200 - node T_202 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_203 = mux(UInt<1>("h00"), T_202, T_196) - node T_204 = and(T_203, io.out.ready) - io.in[1].ready <= T_204 - node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_209 = gt(UInt<1>("h01"), T_167) - node T_210 = and(io.in[1].valid, T_209) - node T_212 = mux(T_210, UInt<1>("h01"), T_207) - node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212) - T_130 <= T_213 - node T_214 = and(io.out.ready, io.out.valid) - when T_214 : - T_167 <= T_130 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_16 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module SmiArbiter_81 : + extmodule AsyncResetReg_17 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_17 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg choice : UInt<1>, clk - inst req_arb of RRArbiter_82 - req_arb.io is invalid - req_arb.clk <= clk - req_arb.reset <= reset - req_arb.io.in[0] <- io.in[0].req - req_arb.io.in[1] <- io.in[1].req - node T_313 = eq(wait_resp, UInt<1>("h00")) - node T_314 = and(io.out.req.ready, T_313) - req_arb.io.out.ready <= T_314 - io.out.req.bits <- req_arb.io.out.bits - node T_316 = eq(wait_resp, UInt<1>("h00")) - node T_317 = and(req_arb.io.out.valid, T_316) - io.out.req.valid <= T_317 - node T_318 = and(io.out.req.ready, io.out.req.valid) - when T_318 : - choice <= req_arb.io.chosen - wait_resp <= UInt<1>("h01") - skip - node T_320 = and(io.out.resp.ready, io.out.resp.valid) - when T_320 : - wait_resp <= UInt<1>("h00") - skip - io.in[0].resp.bits <= io.out.resp.bits - node T_323 = eq(choice, UInt<1>("h00")) - node T_324 = and(io.out.resp.valid, T_323) - io.in[0].resp.valid <= T_324 - io.in[1].resp.bits <= io.out.resp.bits - node T_326 = eq(choice, UInt<1>("h01")) - node T_327 = and(io.out.resp.valid, T_326) - io.in[1].resp.valid <= T_327 - io.out.resp.ready <= io.in[choice].resp.ready - - module SmiIONastiIOConverter_78 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_17 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_18 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_18 : + input clock : Clock input reset : UInt<1> - output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - - io is invalid - inst reader of SmiIONastiReadIOConverter_79 - reader.io is invalid - reader.clk <= clk - reader.reset <= reset - reader.io.ar <- io.nasti.ar - io.nasti.r <- reader.io.r - inst writer of SmiIONastiWriteIOConverter_80 - writer.io is invalid - writer.clk <= clk - writer.reset <= reset - writer.io.aw <- io.nasti.aw - writer.io.w <- io.nasti.w - io.nasti.b <- writer.io.b - inst arb of SmiArbiter_81 - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- reader.io.smi - arb.io.in[1] <- writer.io.smi - io.smi <- arb.io.out + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_18 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module NastiArbiter_83 : + extmodule AsyncResetReg_19 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_19 : + input clock : Clock input reset : UInt<1> - output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - io.slave <- io.master[0] + io is invalid + inst reg_0 of AsyncResetReg_19 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module MemIONastiIOConverter : + extmodule AsyncResetReg_20 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_20 : + input clock : Clock input reset : UInt<1> - output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - node T_368 = and(io.mem.resp.ready, io.mem.resp.valid) - reg mif_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_368 : - node T_372 = eq(mif_cnt_out, UInt<3>("h07")) - node T_374 = and(UInt<1>("h00"), T_372) - node T_377 = add(mif_cnt_out, UInt<1>("h01")) - node T_378 = tail(T_377, 1) - node T_379 = mux(T_374, UInt<1>("h00"), T_378) - mif_cnt_out <= T_379 - skip - node mif_wrap_out = and(T_368, T_372) - node T_382 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_384 = eq(io.nasti.aw.bits.size, UInt<2>("h03")) - node T_385 = or(T_382, T_384) - node T_387 = eq(reset, UInt<1>("h00")) - when T_387 : - node T_389 = eq(T_385, UInt<1>("h00")) - when T_389 : - node T_391 = eq(reset, UInt<1>("h00")) - when T_391 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_393 = eq(io.nasti.ar.valid, UInt<1>("h00")) - node T_395 = eq(io.nasti.ar.bits.size, UInt<2>("h03")) - node T_396 = or(T_393, T_395) - node T_398 = eq(reset, UInt<1>("h00")) - when T_398 : - node T_400 = eq(T_396, UInt<1>("h00")) - when T_400 : - node T_402 = eq(reset, UInt<1>("h00")) - when T_402 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_404 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_406 = eq(io.nasti.aw.bits.len, UInt<3>("h07")) - node T_407 = or(T_404, T_406) - node T_409 = eq(reset, UInt<1>("h00")) - when T_409 : - node T_411 = eq(T_407, UInt<1>("h00")) - when T_411 : - node T_413 = eq(reset, UInt<1>("h00")) - when T_413 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_415 = eq(io.nasti.ar.valid, UInt<1>("h00")) - node T_417 = eq(io.nasti.ar.bits.len, UInt<3>("h07")) - node T_418 = or(T_415, T_417) - node T_420 = eq(reset, UInt<1>("h00")) - when T_420 : - node T_422 = eq(T_418, UInt<1>("h00")) - when T_422 : - node T_424 = eq(reset, UInt<1>("h00")) - when T_424 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - reg b_ok : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - node T_427 = and(io.nasti.aw.ready, io.nasti.aw.valid) - when T_427 : - b_ok <= UInt<1>("h00") - skip - node T_429 = and(io.nasti.w.ready, io.nasti.w.valid) - node T_430 = and(T_429, io.nasti.w.bits.last) - when T_430 : - b_ok <= UInt<1>("h01") - skip - inst id_q of Queue_37 - id_q.io is invalid - id_q.clk <= clk - id_q.reset <= reset - node T_434 = and(io.nasti.aw.valid, io.mem.req_cmd.ready) - id_q.io.enq.valid <= T_434 - id_q.io.enq.bits <= io.nasti.aw.bits.id - node T_435 = and(io.nasti.b.ready, b_ok) - id_q.io.deq.ready <= T_435 - node T_436 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) - node T_438 = dshr(T_436, UInt<3>("h06")) - io.mem.req_cmd.bits.addr <= T_438 - node T_439 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) - io.mem.req_cmd.bits.tag <= T_439 - io.mem.req_cmd.bits.rw <= io.nasti.aw.valid - node T_440 = and(io.nasti.aw.valid, id_q.io.enq.ready) - node T_441 = or(T_440, io.nasti.ar.valid) - io.mem.req_cmd.valid <= T_441 - node T_443 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_444 = and(io.mem.req_cmd.ready, T_443) - io.nasti.ar.ready <= T_444 - node T_445 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) - io.nasti.aw.ready <= T_445 - node T_446 = and(id_q.io.deq.valid, b_ok) - io.nasti.b.valid <= T_446 - io.nasti.b.bits.id <= id_q.io.deq.bits - io.nasti.b.bits.resp <= UInt<1>("h00") - io.nasti.w.ready <= io.mem.req_data.ready - io.mem.req_data.valid <= io.nasti.w.valid - io.mem.req_data.bits.data <= io.nasti.w.bits.data - node T_449 = eq(io.nasti.w.valid, UInt<1>("h00")) - node T_450 = not(io.nasti.w.bits.strb) - node T_452 = eq(T_450, UInt<1>("h00")) - node T_453 = or(T_449, T_452) - node T_455 = eq(reset, UInt<1>("h00")) - when T_455 : - node T_457 = eq(T_453, UInt<1>("h00")) - when T_457 : - node T_459 = eq(reset, UInt<1>("h00")) - when T_459 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): MemIO must write full cache line") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - io.nasti.r.valid <= io.mem.resp.valid - io.nasti.r.bits.data <= io.mem.resp.bits.data - io.nasti.r.bits.last <= mif_wrap_out - io.nasti.r.bits.id <= io.mem.resp.bits.tag - io.nasti.r.bits.resp <= UInt<1>("h00") - io.mem.resp.ready <= io.nasti.r.ready - - module MemSerdes : + io is invalid + inst reg_0 of AsyncResetReg_20 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_21 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_21 : + input clock : Clock input reset : UInt<1> - output io : {flip wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}, narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}} - - io is invalid - node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) - node T_113 = cat(io.wide.req_cmd.bits.addr, T_112) - reg out_buf : UInt, clk - reg in_buf : UInt, clk - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg send_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg data_send_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_130 = eq(send_cnt, UInt<1>("h01")) - node adone = and(io.narrow.req.ready, T_130) - node T_133 = eq(send_cnt, UInt<2>("h03")) - node ddone = and(io.narrow.req.ready, T_133) - node T_135 = and(io.narrow.req.valid, io.narrow.req.ready) - when T_135 : - node T_137 = add(send_cnt, UInt<1>("h01")) - node T_138 = tail(T_137, 1) - send_cnt <= T_138 - node T_140 = dshr(out_buf, UInt<5>("h010")) - out_buf <= T_140 - skip - node T_141 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) - when T_141 : - node T_142 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) - node T_143 = cat(io.wide.req_cmd.bits.addr, T_142) - out_buf <= T_143 - skip - node T_144 = and(io.wide.req_data.valid, io.wide.req_data.ready) - when T_144 : - out_buf <= io.wide.req_data.bits.data - skip - node T_145 = eq(state, UInt<1>("h00")) - io.wide.req_cmd.ready <= T_145 - node T_146 = eq(state, UInt<2>("h03")) - io.wide.req_data.ready <= T_146 - node T_147 = eq(state, UInt<1>("h01")) - node T_148 = eq(state, UInt<2>("h02")) - node T_149 = or(T_147, T_148) - node T_150 = eq(state, UInt<3>("h04")) - node T_151 = or(T_149, T_150) - io.narrow.req.valid <= T_151 - io.narrow.req.bits <= out_buf - node T_152 = eq(state, UInt<1>("h00")) - node T_153 = and(T_152, io.wide.req_cmd.valid) - when T_153 : - node T_154 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) - state <= T_154 - skip - node T_155 = eq(state, UInt<1>("h01")) - node T_156 = and(T_155, adone) - when T_156 : - state <= UInt<1>("h00") - send_cnt <= UInt<1>("h00") - skip - node T_158 = eq(state, UInt<2>("h02")) - node T_159 = and(T_158, adone) - when T_159 : - state <= UInt<2>("h03") - send_cnt <= UInt<1>("h00") - skip - node T_161 = eq(state, UInt<2>("h03")) - node T_162 = and(T_161, io.wide.req_data.valid) - when T_162 : - state <= UInt<3>("h04") - skip - node T_163 = eq(state, UInt<3>("h04")) - node T_164 = and(T_163, ddone) - when T_164 : - node T_166 = add(data_send_cnt, UInt<1>("h01")) - node T_167 = tail(T_166, 1) - data_send_cnt <= T_167 - node T_169 = eq(data_send_cnt, UInt<3>("h07")) - node T_170 = mux(T_169, UInt<1>("h00"), UInt<2>("h03")) - state <= T_170 - send_cnt <= UInt<1>("h00") - skip - reg recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg data_recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg resp_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - resp_val <= UInt<1>("h00") - when io.narrow.resp.valid : - node T_180 = add(recv_cnt, UInt<1>("h01")) - node T_181 = tail(T_180, 1) - recv_cnt <= T_181 - node T_183 = eq(recv_cnt, UInt<3>("h04")) - when T_183 : - recv_cnt <= UInt<1>("h00") - node T_186 = add(data_recv_cnt, UInt<1>("h01")) - node T_187 = tail(T_186, 1) - data_recv_cnt <= T_187 - resp_val <= UInt<1>("h01") - skip - node T_189 = bits(in_buf, 79, 16) - node T_190 = cat(io.narrow.resp.bits, T_189) - in_buf <= T_190 - skip - io.wide.resp.valid <= resp_val - wire T_194 : {data : UInt<64>, tag : UInt<5>} - T_194 is invalid - node T_197 = bits(in_buf, 4, 0) - T_194.tag <= T_197 - node T_198 = bits(in_buf, 68, 5) - T_194.data <= T_198 - io.wide.resp.bits <- T_194 - - module OuterMemorySystem : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_21 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_22 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_22 : + input clock : Clock input reset : UInt<1> - output io : {flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, flip incoherent : UInt<1>[1], mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, deviceTree : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} - - io is invalid - inst T_8064 of ClientTileLinkIOWrapper - T_8064.io is invalid - T_8064.clk <= clk - T_8064.reset <= reset - T_8064.io.in <- io.tiles_uncached[0] - inst T_8065 of ClientTileLinkIOWrapper - T_8065.io is invalid - T_8065.clk <= clk - T_8065.reset <= reset - T_8065.io.in <- io.htif_uncached - inst l1tol2net of RocketChipTileLinkArbiter - l1tol2net.io is invalid - l1tol2net.clk <= clk - l1tol2net.reset <= reset - inst T_8067 of L2BroadcastHub - T_8067.io is invalid - T_8067.clk <= clk - T_8067.reset <= reset - T_8067.io.incoherent <= io.incoherent - l1tol2net.io.clients[0] <- io.tiles_cached[0] - l1tol2net.io.clients[1] <- T_8064.io.out - l1tol2net.io.clients[2] <- T_8065.io.out - l1tol2net.io.managers[0] <- T_8067.io.inner - inst interconnect of NastiRecursiveInterconnect - interconnect.io is invalid - interconnect.clk <= clk - interconnect.reset <= reset - inst T_8069 of ClientTileLinkIOUnwrapper - T_8069.io is invalid - T_8069.clk <= clk - T_8069.reset <= reset - inst T_8070 of TileLinkIONarrower - T_8070.io is invalid - T_8070.clk <= clk - T_8070.reset <= reset - inst T_8071 of NastiIOTileLinkIOConverter - T_8071.io is invalid - T_8071.clk <= clk - T_8071.reset <= reset - inst T_8072 of ClientTileLinkIOWrapper_71 - T_8072.io is invalid - T_8072.clk <= clk - T_8072.reset <= reset - T_8072.io.in <- T_8067.io.outer - inst T_8073 of ClientTileLinkEnqueuer - T_8073.io is invalid - T_8073.clk <= clk - T_8073.reset <= reset - T_8073.io.inner <- T_8072.io.out - T_8069.io.in <- T_8073.io.outer - T_8070.io.in <- T_8069.io.out - T_8071.io.tl <- T_8070.io.out - inst T_8086 of Queue_36 - T_8086.io is invalid - T_8086.clk <= clk - T_8086.reset <= reset - T_8086.io.enq.valid <= T_8071.io.nasti.ar.valid - T_8086.io.enq.bits <- T_8071.io.nasti.ar.bits - T_8071.io.nasti.ar.ready <= T_8086.io.enq.ready - interconnect.io.masters[0].ar <- T_8086.io.deq - inst T_8099 of Queue_36 - T_8099.io is invalid - T_8099.clk <= clk - T_8099.reset <= reset - T_8099.io.enq.valid <= T_8071.io.nasti.aw.valid - T_8099.io.enq.bits <- T_8071.io.nasti.aw.bits - T_8071.io.nasti.aw.ready <= T_8099.io.enq.ready - interconnect.io.masters[0].aw <- T_8099.io.deq - inst T_8105 of Queue_74 - T_8105.io is invalid - T_8105.clk <= clk - T_8105.reset <= reset - T_8105.io.enq.valid <= T_8071.io.nasti.w.valid - T_8105.io.enq.bits <- T_8071.io.nasti.w.bits - T_8071.io.nasti.w.ready <= T_8105.io.enq.ready - interconnect.io.masters[0].w <- T_8105.io.deq - inst T_8112 of Queue_75 - T_8112.io is invalid - T_8112.clk <= clk - T_8112.reset <= reset - T_8112.io.enq.valid <= interconnect.io.masters[0].r.valid - T_8112.io.enq.bits <- interconnect.io.masters[0].r.bits - interconnect.io.masters[0].r.ready <= T_8112.io.enq.ready - T_8071.io.nasti.r <- T_8112.io.deq - inst T_8117 of Queue_76 - T_8117.io is invalid - T_8117.clk <= clk - T_8117.reset <= reset - T_8117.io.enq.valid <= interconnect.io.masters[0].b.valid - T_8117.io.enq.bits <- interconnect.io.masters[0].b.bits - interconnect.io.masters[0].b.ready <= T_8117.io.enq.ready - T_8071.io.nasti.b <- T_8117.io.deq - inst rtc of RTC - rtc.io is invalid - rtc.clk <= clk - rtc.reset <= reset - interconnect.io.masters[1] <- rtc.io - inst T_8119 of SmiIONastiIOConverter - T_8119.io is invalid - T_8119.clk <= clk - T_8119.reset <= reset - T_8119.io.nasti <- interconnect.io.slaves[2] - io.csr[0] <- T_8119.io.smi - inst src_conv of SmiIONastiIOConverter_78 - src_conv.io is invalid - src_conv.clk <= clk - src_conv.reset <= reset - src_conv.io.nasti <- interconnect.io.slaves[3] - io.scr <- src_conv.io.smi - io.mmio <- interconnect.io.slaves[4] - io.deviceTree <- interconnect.io.slaves[1] - inst T_8121 of NastiArbiter_83 - T_8121.io is invalid - T_8121.clk <= clk - T_8121.reset <= reset - inst T_8122 of MemIONastiIOConverter - T_8122.io is invalid - T_8122.clk <= clk - T_8122.reset <= reset - inst T_8123 of MemSerdes - T_8123.io is invalid - T_8123.clk <= clk - T_8123.reset <= reset - T_8122.io.nasti <- T_8121.io.slave - T_8123.io.wide <- T_8122.io.mem - io.mem_backup <- T_8123.io.narrow - node T_8124 = mux(io.mem_backup_en, T_8121.io.master[0].ar.ready, io.mem[0].ar.ready) - interconnect.io.slaves[0].ar.ready <= T_8124 - node T_8126 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8127 = and(interconnect.io.slaves[0].ar.valid, T_8126) - io.mem[0].ar.valid <= T_8127 - io.mem[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8128 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) - T_8121.io.master[0].ar.valid <= T_8128 - T_8121.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8129 = mux(io.mem_backup_en, T_8121.io.master[0].aw.ready, io.mem[0].aw.ready) - interconnect.io.slaves[0].aw.ready <= T_8129 - node T_8131 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8132 = and(interconnect.io.slaves[0].aw.valid, T_8131) - io.mem[0].aw.valid <= T_8132 - io.mem[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8133 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) - T_8121.io.master[0].aw.valid <= T_8133 - T_8121.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8134 = mux(io.mem_backup_en, T_8121.io.master[0].w.ready, io.mem[0].w.ready) - interconnect.io.slaves[0].w.ready <= T_8134 - node T_8136 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8137 = and(interconnect.io.slaves[0].w.valid, T_8136) - io.mem[0].w.valid <= T_8137 - io.mem[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8138 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) - T_8121.io.master[0].w.valid <= T_8138 - T_8121.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8139 = mux(io.mem_backup_en, T_8121.io.master[0].b.valid, io.mem[0].b.valid) - interconnect.io.slaves[0].b.valid <= T_8139 - node T_8140 = mux(io.mem_backup_en, T_8121.io.master[0].b.bits, io.mem[0].b.bits) - interconnect.io.slaves[0].b.bits <- T_8140 - node T_8145 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8146 = and(interconnect.io.slaves[0].b.ready, T_8145) - io.mem[0].b.ready <= T_8146 - node T_8147 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) - T_8121.io.master[0].b.ready <= T_8147 - node T_8148 = mux(io.mem_backup_en, T_8121.io.master[0].r.valid, io.mem[0].r.valid) - interconnect.io.slaves[0].r.valid <= T_8148 - node T_8149 = mux(io.mem_backup_en, T_8121.io.master[0].r.bits, io.mem[0].r.bits) - interconnect.io.slaves[0].r.bits <- T_8149 - node T_8156 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8157 = and(interconnect.io.slaves[0].r.ready, T_8156) - io.mem[0].r.ready <= T_8157 - node T_8158 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) - T_8121.io.master[0].r.ready <= T_8158 - - module SCRFile : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_22 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_23 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_23 : + input clock : Clock input reset : UInt<1> - output io : {flip smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}} - - io is invalid - wire scr_rdata : UInt<64>[64] - scr_rdata is invalid - scr_rdata[0] <= io.scr.rdata[0] - scr_rdata[1] <= io.scr.rdata[1] - scr_rdata[2] <= io.scr.rdata[2] - scr_rdata[3] <= io.scr.rdata[3] - scr_rdata[4] <= io.scr.rdata[4] - scr_rdata[5] <= io.scr.rdata[5] - scr_rdata[6] <= io.scr.rdata[6] - scr_rdata[7] <= io.scr.rdata[7] - scr_rdata[8] <= io.scr.rdata[8] - scr_rdata[9] <= io.scr.rdata[9] - scr_rdata[10] <= io.scr.rdata[10] - scr_rdata[11] <= io.scr.rdata[11] - scr_rdata[12] <= io.scr.rdata[12] - scr_rdata[13] <= io.scr.rdata[13] - scr_rdata[14] <= io.scr.rdata[14] - scr_rdata[15] <= io.scr.rdata[15] - scr_rdata[16] <= io.scr.rdata[16] - scr_rdata[17] <= io.scr.rdata[17] - scr_rdata[18] <= io.scr.rdata[18] - scr_rdata[19] <= io.scr.rdata[19] - scr_rdata[20] <= io.scr.rdata[20] - scr_rdata[21] <= io.scr.rdata[21] - scr_rdata[22] <= io.scr.rdata[22] - scr_rdata[23] <= io.scr.rdata[23] - scr_rdata[24] <= io.scr.rdata[24] - scr_rdata[25] <= io.scr.rdata[25] - scr_rdata[26] <= io.scr.rdata[26] - scr_rdata[27] <= io.scr.rdata[27] - scr_rdata[28] <= io.scr.rdata[28] - scr_rdata[29] <= io.scr.rdata[29] - scr_rdata[30] <= io.scr.rdata[30] - scr_rdata[31] <= io.scr.rdata[31] - scr_rdata[32] <= io.scr.rdata[32] - scr_rdata[33] <= io.scr.rdata[33] - scr_rdata[34] <= io.scr.rdata[34] - scr_rdata[35] <= io.scr.rdata[35] - scr_rdata[36] <= io.scr.rdata[36] - scr_rdata[37] <= io.scr.rdata[37] - scr_rdata[38] <= io.scr.rdata[38] - scr_rdata[39] <= io.scr.rdata[39] - scr_rdata[40] <= io.scr.rdata[40] - scr_rdata[41] <= io.scr.rdata[41] - scr_rdata[42] <= io.scr.rdata[42] - scr_rdata[43] <= io.scr.rdata[43] - scr_rdata[44] <= io.scr.rdata[44] - scr_rdata[45] <= io.scr.rdata[45] - scr_rdata[46] <= io.scr.rdata[46] - scr_rdata[47] <= io.scr.rdata[47] - scr_rdata[48] <= io.scr.rdata[48] - scr_rdata[49] <= io.scr.rdata[49] - scr_rdata[50] <= io.scr.rdata[50] - scr_rdata[51] <= io.scr.rdata[51] - scr_rdata[52] <= io.scr.rdata[52] - scr_rdata[53] <= io.scr.rdata[53] - scr_rdata[54] <= io.scr.rdata[54] - scr_rdata[55] <= io.scr.rdata[55] - scr_rdata[56] <= io.scr.rdata[56] - scr_rdata[57] <= io.scr.rdata[57] - scr_rdata[58] <= io.scr.rdata[58] - scr_rdata[59] <= io.scr.rdata[59] - scr_rdata[60] <= io.scr.rdata[60] - scr_rdata[61] <= io.scr.rdata[61] - scr_rdata[62] <= io.scr.rdata[62] - scr_rdata[63] <= io.scr.rdata[63] - scr_rdata[0] <= UInt<1>("h01") - scr_rdata[1] <= UInt<11>("h0400") - reg read_addr : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - reg resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_365 = eq(resp_valid, UInt<1>("h00")) - io.smi.req.ready <= T_365 - io.smi.resp.valid <= resp_valid - io.smi.resp.bits <= scr_rdata[read_addr] - node T_367 = and(io.smi.req.ready, io.smi.req.valid) - node T_368 = and(T_367, io.smi.req.bits.rw) - io.scr.wen <= T_368 - io.scr.wdata <= io.smi.req.bits.data - io.scr.waddr <= io.smi.req.bits.addr - node T_369 = and(io.smi.req.ready, io.smi.req.valid) - when T_369 : - read_addr <= io.smi.req.bits.addr - resp_valid <= UInt<1>("h01") - skip - node T_371 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_371 : - resp_valid <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_23 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module Queue_89 : + extmodule AsyncResetReg_24 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_24 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} - - io is invalid - cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[1] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_130 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_130) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_136 = and(io.enq.ready, io.enq.valid) - node T_138 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_136, T_138) - node T_140 = and(io.deq.ready, io.deq.valid) - node T_142 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_140, T_142) - when do_enq : - infer mport T_144 = ram[UInt<1>("h00")], clk - T_144 <- io.enq.bits - skip - when do_deq : - skip - node T_158 = neq(do_enq, do_deq) - when T_158 : - maybe_full <= do_enq - skip - node T_160 = eq(empty, UInt<1>("h00")) - node T_162 = and(UInt<1>("h00"), io.enq.valid) - node T_163 = or(T_160, T_162) - io.deq.valid <= T_163 - node T_165 = eq(full, UInt<1>("h00")) - node T_167 = and(UInt<1>("h00"), io.deq.ready) - node T_168 = or(T_165, T_167) - io.enq.ready <= T_168 - infer mport T_169 = ram[UInt<1>("h00")], clk - node T_181 = mux(maybe_flow, io.enq.bits, T_169) - io.deq.bits <- T_181 - node T_193 = sub(UInt<1>("h00"), UInt<1>("h00")) - node ptr_diff = tail(T_193, 1) - node T_195 = and(maybe_full, ptr_match) - node T_196 = cat(T_195, ptr_diff) - io.count <= T_196 - - module NastiROM : - input clk : Clock + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_24 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_3 : + input clock : Clock input reset : UInt<1> - input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - - io is invalid - inst T_334 of Queue_89 - T_334.io is invalid - T_334.clk <= clk - T_334.reset <= reset - T_334.io.enq.valid <= io.ar.valid - T_334.io.enq.bits <- io.ar.bits - io.ar.ready <= T_334.io.enq.ready - when T_334.io.deq.valid : - node T_336 = eq(T_334.io.deq.bits.len, UInt<1>("h00")) - node T_338 = eq(reset, UInt<1>("h00")) - when T_338 : - node T_340 = eq(T_336, UInt<1>("h00")) - when T_340 : - node T_342 = eq(reset, UInt<1>("h00")) - when T_342 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - skip - node T_343 = or(io.aw.valid, io.w.valid) - node T_345 = eq(T_343, UInt<1>("h00")) - node T_347 = eq(reset, UInt<1>("h00")) - when T_347 : - node T_349 = eq(T_345, UInt<1>("h00")) - when T_349 : - node T_351 = eq(reset, UInt<1>("h00")) - when T_351 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't write to NastiROM") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - io.aw.ready <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - wire rom : UInt<64>[67] - rom[0] <= UInt<60>("h0b020000edfe0dd0") - rom[1] <= UInt<64>("h0c001000038000000") - rom[2] <= UInt<61>("h01100000028000000") - rom[3] <= UInt<29>("h010000000") - rom[4] <= UInt<64>("h0880100004b000000") - rom[5] <= UInt<1>("h00") - rom[6] <= UInt<1>("h00") - rom[7] <= UInt<25>("h01000000") - rom[8] <= UInt<59>("h0400000003000000") - rom[9] <= UInt<58>("h0200000000000000") - rom[10] <= UInt<59>("h0400000003000000") - rom[11] <= UInt<58>("h020000000f000000") - rom[12] <= UInt<60>("h0c00000003000000") - rom[13] <= UInt<63>("h06b636f521b000000") - rom[14] <= UInt<55>("h0706968432d7465") - rom[15] <= UInt<63>("h06f6d656d01000000") - rom[16] <= UInt<30>("h030407972") - rom[17] <= UInt<59>("h0700000003000000") - rom[18] <= UInt<63>("h06f6d656d21000000") - rom[19] <= UInt<58>("h0300000000007972") - rom[20] <= UInt<62>("h02d00000010000000") - rom[21] <= UInt<1>("h00") - rom[22] <= UInt<39>("h04000000000") - rom[23] <= UInt<57>("h0100000002000000") - rom[24] <= UInt<31>("h073757063") - rom[25] <= UInt<59>("h0400000003000000") - rom[26] <= UInt<58>("h0200000000000000") - rom[27] <= UInt<59>("h0400000003000000") - rom[28] <= UInt<58>("h020000000f000000") - rom[29] <= UInt<63>("h04075706301000000") - rom[30] <= UInt<62>("h03030303830303034") - rom[31] <= UInt<58>("h0300000000000000") - rom[32] <= UInt<62>("h02100000004000000") - rom[33] <= UInt<58>("h0300000000757063") - rom[34] <= UInt<62>("h03100000006000000") - rom[35] <= UInt<39>("h07663736972") - rom[36] <= UInt<59>("h0500000003000000") - rom[37] <= UInt<62>("h0343676723c000000") - rom[38] <= UInt<58>("h0300000000000000") - rom[39] <= UInt<62>("h02d00000008000000") - rom[40] <= UInt<56>("h080004000000000") - rom[41] <= UInt<58>("h0200000002000000") - rom[42] <= UInt<63>("h04072637301000000") - rom[43] <= UInt<62>("h03030303031303034") - rom[44] <= UInt<58>("h0300000000000000") - rom[45] <= UInt<62>("h02100000004000000") - rom[46] <= UInt<58>("h0300000000726373") - rom[47] <= UInt<62>("h03100000006000000") - rom[48] <= UInt<39>("h07663736972") - rom[49] <= UInt<59>("h0400000003000000") - rom[50] <= UInt<58>("h0300000040000000") - rom[51] <= UInt<61>("h01000000003000000") - rom[52] <= UInt<30>("h02d000000") - rom[53] <= UInt<9>("h0140") - rom[54] <= UInt<58>("h0200000000020000") - rom[55] <= UInt<60>("h0900000002000000") - rom[56] <= UInt<63>("h07373657264646123") - rom[57] <= UInt<62>("h02300736c6c65632d") - rom[58] <= UInt<63>("h06c65632d657a6973") - rom[59] <= UInt<63>("h06c65646f6d00736c") - rom[60] <= UInt<63>("h05f65636976656400") - rom[61] <= UInt<63>("h06765720065707974") - rom[62] <= UInt<63>("h0697461706d6f6300") - rom[63] <= UInt<55>("h061736900656c62") - rom[64] <= UInt<63>("h069746365746f7270") - rom[65] <= UInt<15>("h06e6f") - rom[66] <= UInt<1>("h00") - node T_492 = bits(T_334.io.deq.bits.addr, 9, 3) - node T_495 = cat(UInt<1>("h01"), T_334.io.deq.bits.size) - node T_497 = bits(T_495, 1, 0) - node T_498 = asSInt(T_495) - node T_500 = geq(T_498, asSInt(UInt<1>("h00"))) - node T_501 = bits(T_334.io.deq.bits.addr, 2, 2) - node T_502 = bits(rom[T_492], 63, 32) - node T_503 = bits(rom[T_492], 31, 0) - node T_504 = mux(T_501, T_502, T_503) - node T_506 = and(UInt<1>("h00"), UInt<1>("h00")) - node T_508 = mux(T_506, UInt<1>("h00"), T_504) - node T_510 = eq(T_497, UInt<2>("h02")) - node T_511 = or(T_510, T_506) - node T_512 = bits(T_508, 31, 31) - node T_513 = and(T_500, T_512) - node T_515 = sub(UInt<32>("h00"), T_513) - node T_516 = tail(T_515, 1) - node T_517 = bits(rom[T_492], 63, 32) - node T_518 = mux(T_511, T_516, T_517) - node T_519 = cat(T_518, T_508) - node T_520 = bits(T_334.io.deq.bits.addr, 1, 1) - node T_521 = bits(T_519, 31, 16) - node T_522 = bits(T_519, 15, 0) - node T_523 = mux(T_520, T_521, T_522) - node T_525 = and(UInt<1>("h00"), UInt<1>("h00")) - node T_527 = mux(T_525, UInt<1>("h00"), T_523) - node T_529 = eq(T_497, UInt<1>("h01")) - node T_530 = or(T_529, T_525) - node T_531 = bits(T_527, 15, 15) - node T_532 = and(T_500, T_531) - node T_534 = sub(UInt<48>("h00"), T_532) - node T_535 = tail(T_534, 1) - node T_536 = bits(T_519, 63, 16) - node T_537 = mux(T_530, T_535, T_536) - node T_538 = cat(T_537, T_527) - node T_539 = bits(T_334.io.deq.bits.addr, 0, 0) - node T_540 = bits(T_538, 15, 8) - node T_541 = bits(T_538, 7, 0) - node T_542 = mux(T_539, T_540, T_541) - node T_544 = and(UInt<1>("h01"), UInt<1>("h00")) - node T_546 = mux(T_544, UInt<1>("h00"), T_542) - node T_548 = eq(T_497, UInt<1>("h00")) - node T_549 = or(T_548, T_544) - node T_550 = bits(T_546, 7, 7) - node T_551 = and(T_500, T_550) - node T_553 = sub(UInt<56>("h00"), T_551) - node T_554 = tail(T_553, 1) - node T_555 = bits(T_538, 63, 8) - node T_556 = mux(T_549, T_554, T_555) - node rdata = cat(T_556, T_546) - io.r <- T_334.io.deq - wire T_566 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_566 is invalid - T_566.id <= T_334.io.deq.bits.id - T_566.data <= rdata - T_566.last <= UInt<1>("h01") - T_566.resp <= UInt<1>("h00") - T_566.user <= UInt<1>("h00") - io.r.bits <- T_566 - - module Queue_90 : + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst source_valid_sync_0 of AsyncResetRegVec_21 @[AsyncQueue.scala 18:14] + source_valid_sync_0.io is invalid + source_valid_sync_0.clock <= clock + source_valid_sync_0.reset <= reset + inst source_valid_sync_1 of AsyncResetRegVec_22 @[AsyncQueue.scala 18:14] + source_valid_sync_1.io is invalid + source_valid_sync_1.clock <= clock + source_valid_sync_1.reset <= reset + inst source_valid_sync_2 of AsyncResetRegVec_23 @[AsyncQueue.scala 18:14] + source_valid_sync_2.io is invalid + source_valid_sync_2.clock <= clock + source_valid_sync_2.reset <= reset + inst source_valid_sync_3 of AsyncResetRegVec_24 @[AsyncQueue.scala 18:14] + source_valid_sync_3.io is invalid + source_valid_sync_3.clock <= clock + source_valid_sync_3.reset <= reset + source_valid_sync_3.io.d <= io.in @[AsyncQueue.scala 20:21] + source_valid_sync_3.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + source_valid_sync_0.io.d <= source_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_1.io.d <= source_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_2.io.d <= source_valid_sync_3.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_10 = bits(source_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_10 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_25 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_25 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>} - - io is invalid - cmem ram : UInt<17>[1] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_31 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_31) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_37 = and(io.enq.ready, io.enq.valid) - node T_39 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_37, T_39) - node T_41 = and(io.deq.ready, io.deq.valid) - node T_43 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_41, T_43) - when do_enq : - infer mport T_45 = ram[UInt<1>("h00")], clk - T_45 <= io.enq.bits - skip - when do_deq : - skip - node T_48 = neq(do_enq, do_deq) - when T_48 : - maybe_full <= do_enq - skip - node T_50 = eq(empty, UInt<1>("h00")) - node T_52 = and(UInt<1>("h00"), io.enq.valid) - node T_53 = or(T_50, T_52) - io.deq.valid <= T_53 - node T_55 = eq(full, UInt<1>("h00")) - node T_57 = and(UInt<1>("h00"), io.deq.ready) - node T_58 = or(T_55, T_57) - io.enq.ready <= T_58 - infer mport T_59 = ram[UInt<1>("h00")], clk - node T_60 = mux(maybe_flow, io.enq.bits, T_59) - io.deq.bits <= T_60 - node T_61 = sub(UInt<1>("h00"), UInt<1>("h00")) - node ptr_diff = tail(T_61, 1) - node T_63 = and(maybe_full, ptr_match) - node T_64 = cat(T_63, ptr_diff) - io.count <= T_64 - - module SlowIO : - input clk : Clock + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_25 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_4 : + input clock : Clock input reset : UInt<1> - output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>} + output io : {flip in : UInt<1>, out : UInt<1>} io is invalid - reg divisor : UInt, clk with : (reset => (reset, UInt<9>("h01ff"))) - reg d_shadow : UInt, clk with : (reset => (reset, UInt<9>("h01ff"))) - reg hold : UInt, clk with : (reset => (reset, UInt<7>("h07f"))) - reg h_shadow : UInt, clk with : (reset => (reset, UInt<7>("h07f"))) - when io.set_divisor.valid : - node T_57 = bits(io.set_divisor.bits, 8, 0) - d_shadow <= T_57 - node T_58 = bits(io.set_divisor.bits, 24, 16) - h_shadow <= T_58 - skip - node T_59 = shl(hold, 16) - node T_60 = or(T_59, divisor) - io.divisor <= T_60 - reg count : UInt<9>, clk - reg myclock : UInt<1>, clk - node T_66 = add(count, UInt<1>("h01")) - node T_67 = tail(T_66, 1) - count <= T_67 - node T_68 = shr(divisor, 1) - node rising = eq(count, T_68) - node falling = eq(count, divisor) - node T_71 = shr(divisor, 1) - node T_72 = add(T_71, hold) - node T_73 = tail(T_72, 1) - node held = eq(count, T_73) - when falling : - divisor <= d_shadow - hold <= h_shadow - count <= UInt<1>("h00") - myclock <= UInt<1>("h00") - skip - when rising : - myclock <= UInt<1>("h01") - skip - reg in_slow_rdy : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg out_slow_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg out_slow_bits : UInt<17>, clk - inst fromhost_q of Queue_90 - fromhost_q.io is invalid - fromhost_q.clk <= clk - fromhost_q.reset <= reset - node T_86 = and(io.in_slow.valid, in_slow_rdy) - node T_87 = or(T_86, reset) - node T_88 = and(rising, T_87) - fromhost_q.io.enq.valid <= T_88 - fromhost_q.io.enq.bits <= io.in_slow.bits - io.in_fast <- fromhost_q.io.deq - inst tohost_q of Queue_90 - tohost_q.io is invalid - tohost_q.clk <= clk - tohost_q.reset <= reset - tohost_q.io.enq <- io.out_fast - node T_91 = and(rising, io.out_slow.ready) - node T_92 = and(T_91, out_slow_val) - tohost_q.io.deq.ready <= T_92 - when held : - in_slow_rdy <= fromhost_q.io.enq.ready - out_slow_val <= tohost_q.io.deq.valid - node T_93 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) - out_slow_bits <= T_93 - skip - io.in_slow.ready <= in_slow_rdy - io.out_slow.valid <= out_slow_val - io.out_slow.bits <= out_slow_bits - io.clk_slow <= myclock + io is invalid + inst sink_extend_sync_0 of AsyncResetRegVec_25 @[AsyncQueue.scala 18:14] + sink_extend_sync_0.io is invalid + sink_extend_sync_0.clock <= clock + sink_extend_sync_0.reset <= reset + sink_extend_sync_0.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_extend_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + node _T_7 = bits(sink_extend_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_7 @[AsyncQueue.scala 35:10] - module Uncore : + extmodule AsyncResetReg_26 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_26 : + input clock : Clock input reset : UInt<1> - output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}[1]} - - io is invalid - inst htif of Htif - htif.io is invalid - htif.clk <= clk - htif.reset <= reset - inst outmemsys of OuterMemorySystem - outmemsys.io is invalid - outmemsys.clk <= clk - outmemsys.reset <= reset - outmemsys.io.incoherent[0] <= htif.io.cpu[0].reset - outmemsys.io.htif_uncached <- htif.io.mem - outmemsys.io.tiles_uncached <= io.tiles_uncached - outmemsys.io.tiles_cached <= io.tiles_cached - io.htif[0].reset <= htif.io.cpu[0].reset - io.htif[0].id <= htif.io.cpu[0].id - htif.io.cpu[0].debug_stats_csr <= io.htif[0].debug_stats_csr - inst T_8362 of SmiArbiter - T_8362.io is invalid - T_8362.clk <= clk - T_8362.reset <= reset - T_8362.io.in[0] <- htif.io.cpu[0].csr - T_8362.io.in[1] <- outmemsys.io.csr[0] - io.htif[0].csr <- T_8362.io.out - inst scrFile of SCRFile - scrFile.io is invalid - scrFile.clk <= clk - scrFile.reset <= reset - inst scrArb of SmiArbiter_81 - scrArb.io is invalid - scrArb.clk <= clk - scrArb.reset <= reset - scrArb.io.in[0] <- htif.io.scr - scrArb.io.in[1] <- outmemsys.io.scr - scrFile.io.smi <- scrArb.io.out - inst deviceTree of NastiROM - deviceTree.io is invalid - deviceTree.clk <= clk - deviceTree.reset <= reset - deviceTree.io <- outmemsys.io.deviceTree - io.host.debug_stats_csr <= htif.io.host.debug_stats_csr - io.mem <= outmemsys.io.mem - io.mmio <- outmemsys.io.mmio - outmemsys.io.mem_backup_en <= io.mem_backup_ctrl.en - inst T_8366 of SlowIO - T_8366.io is invalid - T_8366.clk <= clk - T_8366.reset <= reset - node T_8368 = eq(scrFile.io.scr.waddr, UInt<6>("h03f")) - node T_8369 = and(scrFile.io.scr.wen, T_8368) - T_8366.io.set_divisor.valid <= T_8369 - T_8366.io.set_divisor.bits <= scrFile.io.scr.wdata - scrFile.io.scr.rdata[63] <= T_8366.io.divisor - node T_8370 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) - T_8366.io.out_fast.valid <= T_8370 - node T_8371 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) - node T_8372 = cat(htif.io.host.out.valid, T_8371) - T_8366.io.out_fast.bits <= T_8372 - htif.io.host.out.ready <= T_8366.io.out_fast.ready - node T_8374 = eq(htif.io.host.out.valid, UInt<1>("h00")) - node T_8375 = and(T_8366.io.out_fast.ready, T_8374) - outmemsys.io.mem_backup.req.ready <= T_8375 - node T_8376 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8377 = and(T_8366.io.out_slow.valid, T_8376) - io.host.out.valid <= T_8377 - io.host.out.bits <= T_8366.io.out_slow.bits - node T_8378 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8380 = eq(T_8378, UInt<1>("h00")) - node T_8381 = and(T_8366.io.out_slow.valid, T_8380) - io.mem_backup_ctrl.out_valid <= T_8381 - node T_8382 = bits(T_8366.io.out_slow.bits, 16, 16) - node T_8383 = mux(T_8382, io.host.out.ready, io.mem_backup_ctrl.out_ready) - T_8366.io.out_slow.ready <= T_8383 - node T_8384 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) - node T_8385 = or(T_8384, io.host.in.valid) - T_8366.io.in_slow.valid <= T_8385 - node T_8386 = cat(T_8384, io.host.in.bits) - T_8366.io.in_slow.bits <= T_8386 - io.host.in.ready <= T_8366.io.in_slow.ready - node T_8387 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8388 = and(T_8366.io.in_fast.valid, T_8387) - outmemsys.io.mem_backup.resp.valid <= T_8388 - outmemsys.io.mem_backup.resp.bits <= T_8366.io.in_fast.bits - node T_8389 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8391 = eq(T_8389, UInt<1>("h00")) - node T_8392 = and(T_8366.io.in_fast.valid, T_8391) - htif.io.host.in.valid <= T_8392 - htif.io.host.in.bits <= T_8366.io.in_fast.bits - node T_8393 = bits(T_8366.io.in_fast.bits, 16, 16) - node T_8395 = mux(T_8393, UInt<1>("h01"), htif.io.host.in.ready) - T_8366.io.in_fast.ready <= T_8395 - io.host.clk <= T_8366.io.clk_slow - reg T_8396 : UInt<1>, clk - T_8396 <= io.host.clk - node T_8398 = eq(T_8396, UInt<1>("h00")) - node T_8399 = and(io.host.clk, T_8398) - reg T_8400 : UInt<1>, clk - T_8400 <= T_8399 - io.host.clk_edge <= T_8400 + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module CSRFile : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_26 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_27 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_27 : + input clock : Clock input reset : UInt<1> - output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}, interrupt : UInt<1>, interrupt_cause : UInt<64>} - - io is invalid - reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk - wire T_4480 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_4480 is invalid - T_4480.usip <= UInt<1>("h00") - T_4480.ssip <= UInt<1>("h00") - T_4480.hsip <= UInt<1>("h00") - T_4480.msip <= UInt<1>("h00") - T_4480.utip <= UInt<1>("h00") - T_4480.stip <= UInt<1>("h00") - T_4480.htip <= UInt<1>("h00") - T_4480.mtip <= UInt<1>("h00") - reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4480)) - wire T_4525 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_4525 is invalid - T_4525.usip <= UInt<1>("h00") - T_4525.ssip <= UInt<1>("h00") - T_4525.hsip <= UInt<1>("h00") - T_4525.msip <= UInt<1>("h00") - T_4525.utip <= UInt<1>("h00") - T_4525.stip <= UInt<1>("h00") - T_4525.htip <= UInt<1>("h00") - T_4525.mtip <= UInt<1>("h00") - reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4525)) - reg reg_mepc : UInt<40>, clk - reg reg_mcause : UInt<64>, clk - reg reg_mbadaddr : UInt<40>, clk - reg reg_mscratch : UInt<64>, clk - reg reg_sepc : UInt<40>, clk - reg reg_scause : UInt<64>, clk - reg reg_sbadaddr : UInt<40>, clk - reg reg_sscratch : UInt<64>, clk - reg reg_stvec : UInt<39>, clk - reg reg_mtimecmp : UInt<64>, clk - reg reg_sptbr : UInt<32>, clk - reg reg_wfi : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg reg_tohost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) - reg reg_fromhost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) - reg reg_stats : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg reg_time : UInt<64>, clk - reg T_4584 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4586 = neq(io.retire, UInt<1>("h00")) - node T_4588 = add(T_4584, UInt<7>("h01")) - node T_4589 = tail(T_4588, 1) - when T_4586 : - node T_4590 = bits(T_4589, 5, 0) - T_4584 <= T_4590 - skip - reg T_4592 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4593 = bits(T_4589, 6, 6) - node T_4594 = and(T_4586, T_4593) - when T_4594 : - node T_4596 = add(T_4592, UInt<1>("h01")) - node T_4597 = tail(T_4596, 1) - T_4592 <= T_4597 - skip - node T_4598 = cat(T_4592, T_4584) - reg T_4601 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4603 = neq(UInt<1>("h01"), UInt<1>("h00")) - node T_4605 = add(T_4601, UInt<7>("h01")) - node T_4606 = tail(T_4605, 1) - when T_4603 : - node T_4607 = bits(T_4606, 5, 0) - T_4601 <= T_4607 - skip - reg T_4609 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4610 = bits(T_4606, 6, 6) - node T_4611 = and(T_4603, T_4610) - when T_4611 : - node T_4613 = add(T_4609, UInt<1>("h01")) - node T_4614 = tail(T_4613, 1) - T_4609 <= T_4614 - skip - node T_4615 = cat(T_4609, T_4601) - reg T_4617 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4619 = neq(io.uarch_counters[0], UInt<1>("h00")) - node T_4621 = add(T_4617, UInt<7>("h01")) - node T_4622 = tail(T_4621, 1) - when T_4619 : - node T_4623 = bits(T_4622, 5, 0) - T_4617 <= T_4623 - skip - reg T_4625 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4626 = bits(T_4622, 6, 6) - node T_4627 = and(T_4619, T_4626) - when T_4627 : - node T_4629 = add(T_4625, UInt<1>("h01")) - node T_4630 = tail(T_4629, 1) - T_4625 <= T_4630 - skip - node T_4631 = cat(T_4625, T_4617) - reg T_4633 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4635 = neq(io.uarch_counters[1], UInt<1>("h00")) - node T_4637 = add(T_4633, UInt<7>("h01")) - node T_4638 = tail(T_4637, 1) - when T_4635 : - node T_4639 = bits(T_4638, 5, 0) - T_4633 <= T_4639 - skip - reg T_4641 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4642 = bits(T_4638, 6, 6) - node T_4643 = and(T_4635, T_4642) - when T_4643 : - node T_4645 = add(T_4641, UInt<1>("h01")) - node T_4646 = tail(T_4645, 1) - T_4641 <= T_4646 - skip - node T_4647 = cat(T_4641, T_4633) - reg T_4649 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4651 = neq(io.uarch_counters[2], UInt<1>("h00")) - node T_4653 = add(T_4649, UInt<7>("h01")) - node T_4654 = tail(T_4653, 1) - when T_4651 : - node T_4655 = bits(T_4654, 5, 0) - T_4649 <= T_4655 - skip - reg T_4657 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4658 = bits(T_4654, 6, 6) - node T_4659 = and(T_4651, T_4658) - when T_4659 : - node T_4661 = add(T_4657, UInt<1>("h01")) - node T_4662 = tail(T_4661, 1) - T_4657 <= T_4662 - skip - node T_4663 = cat(T_4657, T_4649) - reg T_4665 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4667 = neq(io.uarch_counters[3], UInt<1>("h00")) - node T_4669 = add(T_4665, UInt<7>("h01")) - node T_4670 = tail(T_4669, 1) - when T_4667 : - node T_4671 = bits(T_4670, 5, 0) - T_4665 <= T_4671 - skip - reg T_4673 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4674 = bits(T_4670, 6, 6) - node T_4675 = and(T_4667, T_4674) - when T_4675 : - node T_4677 = add(T_4673, UInt<1>("h01")) - node T_4678 = tail(T_4677, 1) - T_4673 <= T_4678 - skip - node T_4679 = cat(T_4673, T_4665) - reg T_4681 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4683 = neq(io.uarch_counters[4], UInt<1>("h00")) - node T_4685 = add(T_4681, UInt<7>("h01")) - node T_4686 = tail(T_4685, 1) - when T_4683 : - node T_4687 = bits(T_4686, 5, 0) - T_4681 <= T_4687 - skip - reg T_4689 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4690 = bits(T_4686, 6, 6) - node T_4691 = and(T_4683, T_4690) - when T_4691 : - node T_4693 = add(T_4689, UInt<1>("h01")) - node T_4694 = tail(T_4693, 1) - T_4689 <= T_4694 - skip - node T_4695 = cat(T_4689, T_4681) - reg T_4697 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4699 = neq(io.uarch_counters[5], UInt<1>("h00")) - node T_4701 = add(T_4697, UInt<7>("h01")) - node T_4702 = tail(T_4701, 1) - when T_4699 : - node T_4703 = bits(T_4702, 5, 0) - T_4697 <= T_4703 - skip - reg T_4705 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4706 = bits(T_4702, 6, 6) - node T_4707 = and(T_4699, T_4706) - when T_4707 : - node T_4709 = add(T_4705, UInt<1>("h01")) - node T_4710 = tail(T_4709, 1) - T_4705 <= T_4710 - skip - node T_4711 = cat(T_4705, T_4697) - reg T_4713 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4715 = neq(io.uarch_counters[6], UInt<1>("h00")) - node T_4717 = add(T_4713, UInt<7>("h01")) - node T_4718 = tail(T_4717, 1) - when T_4715 : - node T_4719 = bits(T_4718, 5, 0) - T_4713 <= T_4719 - skip - reg T_4721 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4722 = bits(T_4718, 6, 6) - node T_4723 = and(T_4715, T_4722) - when T_4723 : - node T_4725 = add(T_4721, UInt<1>("h01")) - node T_4726 = tail(T_4725, 1) - T_4721 <= T_4726 - skip - node T_4727 = cat(T_4721, T_4713) - reg T_4729 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4731 = neq(io.uarch_counters[7], UInt<1>("h00")) - node T_4733 = add(T_4729, UInt<7>("h01")) - node T_4734 = tail(T_4733, 1) - when T_4731 : - node T_4735 = bits(T_4734, 5, 0) - T_4729 <= T_4735 - skip - reg T_4737 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4738 = bits(T_4734, 6, 6) - node T_4739 = and(T_4731, T_4738) - when T_4739 : - node T_4741 = add(T_4737, UInt<1>("h01")) - node T_4742 = tail(T_4741, 1) - T_4737 <= T_4742 - skip - node T_4743 = cat(T_4737, T_4729) - reg T_4745 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4747 = neq(io.uarch_counters[8], UInt<1>("h00")) - node T_4749 = add(T_4745, UInt<7>("h01")) - node T_4750 = tail(T_4749, 1) - when T_4747 : - node T_4751 = bits(T_4750, 5, 0) - T_4745 <= T_4751 - skip - reg T_4753 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4754 = bits(T_4750, 6, 6) - node T_4755 = and(T_4747, T_4754) - when T_4755 : - node T_4757 = add(T_4753, UInt<1>("h01")) - node T_4758 = tail(T_4757, 1) - T_4753 <= T_4758 - skip - node T_4759 = cat(T_4753, T_4745) - reg T_4761 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4763 = neq(io.uarch_counters[9], UInt<1>("h00")) - node T_4765 = add(T_4761, UInt<7>("h01")) - node T_4766 = tail(T_4765, 1) - when T_4763 : - node T_4767 = bits(T_4766, 5, 0) - T_4761 <= T_4767 - skip - reg T_4769 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4770 = bits(T_4766, 6, 6) - node T_4771 = and(T_4763, T_4770) - when T_4771 : - node T_4773 = add(T_4769, UInt<1>("h01")) - node T_4774 = tail(T_4773, 1) - T_4769 <= T_4774 - skip - node T_4775 = cat(T_4769, T_4761) - reg T_4777 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4779 = neq(io.uarch_counters[10], UInt<1>("h00")) - node T_4781 = add(T_4777, UInt<7>("h01")) - node T_4782 = tail(T_4781, 1) - when T_4779 : - node T_4783 = bits(T_4782, 5, 0) - T_4777 <= T_4783 - skip - reg T_4785 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4786 = bits(T_4782, 6, 6) - node T_4787 = and(T_4779, T_4786) - when T_4787 : - node T_4789 = add(T_4785, UInt<1>("h01")) - node T_4790 = tail(T_4789, 1) - T_4785 <= T_4790 - skip - node T_4791 = cat(T_4785, T_4777) - reg T_4793 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4795 = neq(io.uarch_counters[11], UInt<1>("h00")) - node T_4797 = add(T_4793, UInt<7>("h01")) - node T_4798 = tail(T_4797, 1) - when T_4795 : - node T_4799 = bits(T_4798, 5, 0) - T_4793 <= T_4799 - skip - reg T_4801 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4802 = bits(T_4798, 6, 6) - node T_4803 = and(T_4795, T_4802) - when T_4803 : - node T_4805 = add(T_4801, UInt<1>("h01")) - node T_4806 = tail(T_4805, 1) - T_4801 <= T_4806 - skip - node T_4807 = cat(T_4801, T_4793) - reg T_4809 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4811 = neq(io.uarch_counters[12], UInt<1>("h00")) - node T_4813 = add(T_4809, UInt<7>("h01")) - node T_4814 = tail(T_4813, 1) - when T_4811 : - node T_4815 = bits(T_4814, 5, 0) - T_4809 <= T_4815 - skip - reg T_4817 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4818 = bits(T_4814, 6, 6) - node T_4819 = and(T_4811, T_4818) - when T_4819 : - node T_4821 = add(T_4817, UInt<1>("h01")) - node T_4822 = tail(T_4821, 1) - T_4817 <= T_4822 - skip - node T_4823 = cat(T_4817, T_4809) - reg T_4825 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4827 = neq(io.uarch_counters[13], UInt<1>("h00")) - node T_4829 = add(T_4825, UInt<7>("h01")) - node T_4830 = tail(T_4829, 1) - when T_4827 : - node T_4831 = bits(T_4830, 5, 0) - T_4825 <= T_4831 - skip - reg T_4833 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4834 = bits(T_4830, 6, 6) - node T_4835 = and(T_4827, T_4834) - when T_4835 : - node T_4837 = add(T_4833, UInt<1>("h01")) - node T_4838 = tail(T_4837, 1) - T_4833 <= T_4838 - skip - node T_4839 = cat(T_4833, T_4825) - reg T_4841 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4843 = neq(io.uarch_counters[14], UInt<1>("h00")) - node T_4845 = add(T_4841, UInt<7>("h01")) - node T_4846 = tail(T_4845, 1) - when T_4843 : - node T_4847 = bits(T_4846, 5, 0) - T_4841 <= T_4847 - skip - reg T_4849 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4850 = bits(T_4846, 6, 6) - node T_4851 = and(T_4843, T_4850) - when T_4851 : - node T_4853 = add(T_4849, UInt<1>("h01")) - node T_4854 = tail(T_4853, 1) - T_4849 <= T_4854 - skip - node T_4855 = cat(T_4849, T_4841) - reg T_4857 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_4859 = neq(io.uarch_counters[15], UInt<1>("h00")) - node T_4861 = add(T_4857, UInt<7>("h01")) - node T_4862 = tail(T_4861, 1) - when T_4859 : - node T_4863 = bits(T_4862, 5, 0) - T_4857 <= T_4863 - skip - reg T_4865 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_4866 = bits(T_4862, 6, 6) - node T_4867 = and(T_4859, T_4866) - when T_4867 : - node T_4869 = add(T_4865, UInt<1>("h01")) - node T_4870 = tail(T_4869, 1) - T_4865 <= T_4870 - skip - node T_4871 = cat(T_4865, T_4857) - reg reg_fflags : UInt<5>, clk - reg reg_frm : UInt<3>, clk - node irq_rocc = and(UInt<1>("h00"), io.rocc.interrupt) - io.interrupt_cause <= UInt<1>("h00") - node T_4879 = bits(io.interrupt_cause, 63, 63) - io.interrupt <= T_4879 - wire some_interrupt_pending : UInt<1> - some_interrupt_pending <= UInt<1>("h00") - node T_4883 = and(reg_mie.ssip, reg_mip.ssip) - node T_4884 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_4885 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_4886 = and(T_4885, reg_mstatus.ie) - node T_4887 = or(T_4884, T_4886) - node T_4888 = and(T_4883, T_4887) - when T_4888 : - io.interrupt_cause <= UInt<64>("h08000000000000000") - skip - node T_4890 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_4891 = and(T_4883, T_4890) - when T_4891 : - some_interrupt_pending <= UInt<1>("h01") - skip - node T_4894 = and(reg_mie.msip, reg_mip.msip) - node T_4895 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4896 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4897 = and(T_4896, reg_mstatus.ie) - node T_4898 = or(T_4895, T_4897) - node T_4899 = and(T_4894, T_4898) - when T_4899 : - io.interrupt_cause <= UInt<64>("h08000000000000000") - skip - node T_4901 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4902 = and(T_4894, T_4901) - when T_4902 : - some_interrupt_pending <= UInt<1>("h01") - skip - node T_4905 = and(reg_mie.stip, reg_mip.stip) - node T_4906 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_4907 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_4908 = and(T_4907, reg_mstatus.ie) - node T_4909 = or(T_4906, T_4908) - node T_4910 = and(T_4905, T_4909) - when T_4910 : - io.interrupt_cause <= UInt<64>("h08000000000000001") - skip - node T_4912 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_4913 = and(T_4905, T_4912) - when T_4913 : - some_interrupt_pending <= UInt<1>("h01") - skip - node T_4916 = and(reg_mie.mtip, reg_mip.mtip) - node T_4917 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4918 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4919 = and(T_4918, reg_mstatus.ie) - node T_4920 = or(T_4917, T_4919) - node T_4921 = and(T_4916, T_4920) - when T_4921 : - io.interrupt_cause <= UInt<64>("h08000000000000001") - skip - node T_4923 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4924 = and(T_4916, T_4923) - when T_4924 : - some_interrupt_pending <= UInt<1>("h01") - skip - node T_4928 = neq(reg_fromhost, UInt<1>("h00")) - node T_4929 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4930 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4931 = and(T_4930, reg_mstatus.ie) - node T_4932 = or(T_4929, T_4931) - node T_4933 = and(T_4928, T_4932) - when T_4933 : - io.interrupt_cause <= UInt<64>("h08000000000000002") - skip - node T_4935 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4936 = and(T_4928, T_4935) - when T_4936 : - some_interrupt_pending <= UInt<1>("h01") - skip - node T_4939 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4940 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4941 = and(T_4940, reg_mstatus.ie) - node T_4942 = or(T_4939, T_4941) - node T_4943 = and(irq_rocc, T_4942) - when T_4943 : - io.interrupt_cause <= UInt<64>("h08000000000000003") - skip - node T_4945 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4946 = and(irq_rocc, T_4945) - when T_4946 : - some_interrupt_pending <= UInt<1>("h01") - skip - node system_insn = eq(io.rw.cmd, UInt<3>("h04")) - node T_4949 = neq(io.rw.cmd, UInt<3>("h00")) - node T_4951 = eq(system_insn, UInt<1>("h00")) - node cpu_ren = and(T_4949, T_4951) - reg host_csr_req_valid : UInt<1>, clk - node T_4956 = eq(cpu_ren, UInt<1>("h00")) - node host_csr_req_fire = and(host_csr_req_valid, T_4956) - reg host_csr_rep_valid : UInt<1>, clk - reg host_csr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk - node T_4965 = eq(host_csr_req_valid, UInt<1>("h00")) - node T_4967 = eq(host_csr_rep_valid, UInt<1>("h00")) - node T_4968 = and(T_4965, T_4967) - io.host.csr.req.ready <= T_4968 - io.host.csr.resp.valid <= host_csr_rep_valid - io.host.csr.resp.bits <= host_csr_bits.data - node T_4969 = and(io.host.csr.req.ready, io.host.csr.req.valid) - when T_4969 : - host_csr_req_valid <= UInt<1>("h01") - host_csr_bits <- io.host.csr.req.bits - skip - when host_csr_req_fire : - host_csr_req_valid <= UInt<1>("h00") - host_csr_rep_valid <= UInt<1>("h01") - host_csr_bits.data <= io.rw.rdata - skip - node T_4973 = and(io.host.csr.resp.ready, io.host.csr.resp.valid) - when T_4973 : - host_csr_rep_valid <= UInt<1>("h00") - skip - io.host.debug_stats_csr <= reg_stats - node T_4975 = cat(io.status.sd, io.status.zero2) - node T_4976 = cat(io.status.sd_rv32, io.status.zero1) - node T_4977 = cat(T_4975, T_4976) - node T_4978 = cat(io.status.vm, io.status.mprv) - node T_4979 = cat(io.status.xs, io.status.fs) - node T_4980 = cat(T_4978, T_4979) - node T_4981 = cat(T_4977, T_4980) - node T_4982 = cat(io.status.prv3, io.status.ie3) - node T_4983 = cat(io.status.prv2, io.status.ie2) - node T_4984 = cat(T_4982, T_4983) - node T_4985 = cat(io.status.prv1, io.status.ie1) - node T_4986 = cat(io.status.prv, io.status.ie) - node T_4987 = cat(T_4985, T_4986) - node T_4988 = cat(T_4984, T_4987) - node read_mstatus = cat(T_4981, T_4988) - node T_4990 = cat(reg_frm, reg_fflags) - node T_4998 = cat(reg_mip.mtip, reg_mip.htip) - node T_4999 = cat(reg_mip.stip, reg_mip.utip) - node T_5000 = cat(T_4998, T_4999) - node T_5001 = cat(reg_mip.msip, reg_mip.hsip) - node T_5002 = cat(reg_mip.ssip, reg_mip.usip) - node T_5003 = cat(T_5001, T_5002) - node T_5004 = cat(T_5000, T_5003) - node T_5005 = cat(reg_mie.mtip, reg_mie.htip) - node T_5006 = cat(reg_mie.stip, reg_mie.utip) - node T_5007 = cat(T_5005, T_5006) - node T_5008 = cat(reg_mie.msip, reg_mie.hsip) - node T_5009 = cat(reg_mie.ssip, reg_mie.usip) - node T_5010 = cat(T_5008, T_5009) - node T_5011 = cat(T_5007, T_5010) - node T_5012 = bits(reg_mepc, 39, 39) - node T_5014 = sub(UInt<24>("h00"), T_5012) - node T_5015 = tail(T_5014, 1) - node T_5016 = cat(T_5015, reg_mepc) - node T_5017 = bits(reg_mbadaddr, 39, 39) - node T_5019 = sub(UInt<24>("h00"), T_5017) - node T_5020 = tail(T_5019, 1) - node T_5021 = cat(T_5020, reg_mbadaddr) - wire T_5048 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5048 is invalid - node T_5061 = bits(read_mstatus, 0, 0) - T_5048.ie <= T_5061 - node T_5062 = bits(read_mstatus, 2, 1) - T_5048.zero1 <= T_5062 - node T_5063 = bits(read_mstatus, 3, 3) - T_5048.pie <= T_5063 - node T_5064 = bits(read_mstatus, 4, 4) - T_5048.ps <= T_5064 - node T_5065 = bits(read_mstatus, 11, 5) - T_5048.zero2 <= T_5065 - node T_5066 = bits(read_mstatus, 13, 12) - T_5048.fs <= T_5066 - node T_5067 = bits(read_mstatus, 15, 14) - T_5048.xs <= T_5067 - node T_5068 = bits(read_mstatus, 16, 16) - T_5048.mprv <= T_5068 - node T_5069 = bits(read_mstatus, 30, 17) - T_5048.zero3 <= T_5069 - node T_5070 = bits(read_mstatus, 31, 31) - T_5048.sd_rv32 <= T_5070 - node T_5071 = bits(read_mstatus, 62, 32) - T_5048.zero4 <= T_5071 - node T_5072 = bits(read_mstatus, 63, 63) - T_5048.sd <= T_5072 - wire T_5073 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5073 <- T_5048 - T_5073.zero1 <= UInt<1>("h00") - T_5073.zero2 <= UInt<1>("h00") - T_5073.zero3 <= UInt<1>("h00") - T_5073.zero4 <= UInt<1>("h00") - wire T_5109 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5109 is invalid - T_5109.usip <= UInt<1>("h00") - T_5109.ssip <= UInt<1>("h00") - T_5109.hsip <= UInt<1>("h00") - T_5109.msip <= UInt<1>("h00") - T_5109.utip <= UInt<1>("h00") - T_5109.stip <= UInt<1>("h00") - T_5109.htip <= UInt<1>("h00") - T_5109.mtip <= UInt<1>("h00") - wire T_5126 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5126 <- T_5109 - T_5126.ssip <= reg_mip.ssip - T_5126.stip <= reg_mip.stip - wire T_5154 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5154 is invalid - T_5154.usip <= UInt<1>("h00") - T_5154.ssip <= UInt<1>("h00") - T_5154.hsip <= UInt<1>("h00") - T_5154.msip <= UInt<1>("h00") - T_5154.utip <= UInt<1>("h00") - T_5154.stip <= UInt<1>("h00") - T_5154.htip <= UInt<1>("h00") - T_5154.mtip <= UInt<1>("h00") - wire T_5171 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5171 <- T_5154 - T_5171.ssip <= reg_mie.ssip - T_5171.stip <= reg_mie.stip - node T_5180 = cat(T_5073.zero4, T_5073.sd_rv32) - node T_5181 = cat(T_5073.sd, T_5180) - node T_5182 = cat(T_5073.mprv, T_5073.xs) - node T_5183 = cat(T_5073.zero3, T_5182) - node T_5184 = cat(T_5181, T_5183) - node T_5185 = cat(T_5073.zero2, T_5073.ps) - node T_5186 = cat(T_5073.fs, T_5185) - node T_5187 = cat(T_5073.zero1, T_5073.ie) - node T_5188 = cat(T_5073.pie, T_5187) - node T_5189 = cat(T_5186, T_5188) - node T_5190 = cat(T_5184, T_5189) - node T_5191 = cat(T_5126.mtip, T_5126.htip) - node T_5192 = cat(T_5126.stip, T_5126.utip) - node T_5193 = cat(T_5191, T_5192) - node T_5194 = cat(T_5126.msip, T_5126.hsip) - node T_5195 = cat(T_5126.ssip, T_5126.usip) - node T_5196 = cat(T_5194, T_5195) - node T_5197 = cat(T_5193, T_5196) - node T_5198 = cat(T_5171.mtip, T_5171.htip) - node T_5199 = cat(T_5171.stip, T_5171.utip) - node T_5200 = cat(T_5198, T_5199) - node T_5201 = cat(T_5171.msip, T_5171.hsip) - node T_5202 = cat(T_5171.ssip, T_5171.usip) - node T_5203 = cat(T_5201, T_5202) - node T_5204 = cat(T_5200, T_5203) - node T_5205 = bits(reg_sbadaddr, 39, 39) - node T_5207 = sub(UInt<24>("h00"), T_5205) - node T_5208 = tail(T_5207, 1) - node T_5209 = cat(T_5208, reg_sbadaddr) - node T_5211 = bits(reg_sepc, 39, 39) - node T_5213 = sub(UInt<24>("h00"), T_5211) - node T_5214 = tail(T_5213, 1) - node T_5215 = cat(T_5214, reg_sepc) - node T_5216 = bits(reg_stvec, 38, 38) - node T_5218 = sub(UInt<25>("h00"), T_5216) - node T_5219 = tail(T_5218, 1) - node T_5220 = cat(T_5219, reg_stvec) - node addr = mux(cpu_ren, io.rw.addr, host_csr_bits.addr) - node T_5223 = eq(addr, UInt<1>("h01")) - node T_5225 = eq(addr, UInt<2>("h02")) - node T_5227 = eq(addr, UInt<2>("h03")) - node T_5229 = eq(addr, UInt<12>("h0c00")) - node T_5231 = eq(addr, UInt<12>("h0900")) - node T_5233 = eq(addr, UInt<12>("h0c01")) - node T_5235 = eq(addr, UInt<12>("h0901")) - node T_5237 = eq(addr, UInt<12>("h0d01")) - node T_5239 = eq(addr, UInt<12>("h0a01")) - node T_5241 = eq(addr, UInt<11>("h0701")) - node T_5243 = eq(addr, UInt<12>("h0f00")) - node T_5245 = eq(addr, UInt<12>("h0f01")) - node T_5247 = eq(addr, UInt<10>("h0300")) - node T_5249 = eq(addr, UInt<10>("h0302")) - node T_5251 = eq(addr, UInt<11>("h0782")) - node T_5253 = eq(addr, UInt<10>("h0301")) - node T_5255 = eq(addr, UInt<11>("h0784")) - node T_5257 = eq(addr, UInt<11>("h0783")) - node T_5259 = eq(addr, UInt<10>("h0344")) - node T_5261 = eq(addr, UInt<10>("h0304")) - node T_5263 = eq(addr, UInt<10>("h0340")) - node T_5265 = eq(addr, UInt<10>("h0341")) - node T_5267 = eq(addr, UInt<10>("h0343")) - node T_5269 = eq(addr, UInt<10>("h0342")) - node T_5271 = eq(addr, UInt<10>("h0321")) - node T_5273 = eq(addr, UInt<12>("h0f10")) - node T_5275 = eq(addr, UInt<8>("h0c0")) - node T_5277 = eq(addr, UInt<11>("h0780")) - node T_5279 = eq(addr, UInt<11>("h0781")) - node T_5281 = eq(addr, UInt<12>("h0c02")) - node T_5283 = eq(addr, UInt<12>("h0902")) - node T_5285 = eq(addr, UInt<12>("h0cc0")) - node T_5287 = eq(addr, UInt<12>("h0cc1")) - node T_5289 = eq(addr, UInt<12>("h0cc2")) - node T_5291 = eq(addr, UInt<12>("h0cc3")) - node T_5293 = eq(addr, UInt<12>("h0cc4")) - node T_5295 = eq(addr, UInt<12>("h0cc5")) - node T_5297 = eq(addr, UInt<12>("h0cc6")) - node T_5299 = eq(addr, UInt<12>("h0cc7")) - node T_5301 = eq(addr, UInt<12>("h0cc8")) - node T_5303 = eq(addr, UInt<12>("h0cc9")) - node T_5305 = eq(addr, UInt<12>("h0cca")) - node T_5307 = eq(addr, UInt<12>("h0ccb")) - node T_5309 = eq(addr, UInt<12>("h0ccc")) - node T_5311 = eq(addr, UInt<12>("h0ccd")) - node T_5313 = eq(addr, UInt<12>("h0cce")) - node T_5315 = eq(addr, UInt<12>("h0ccf")) - node T_5317 = eq(addr, UInt<9>("h0100")) - node T_5319 = eq(addr, UInt<9>("h0144")) - node T_5321 = eq(addr, UInt<9>("h0104")) - node T_5323 = eq(addr, UInt<9>("h0140")) - node T_5325 = eq(addr, UInt<12>("h0d42")) - node T_5327 = eq(addr, UInt<12>("h0d43")) - node T_5329 = eq(addr, UInt<9>("h0180")) - node T_5331 = eq(addr, UInt<9>("h0181")) - node T_5333 = eq(addr, UInt<9>("h0141")) - node T_5335 = eq(addr, UInt<9>("h0101")) - node T_5336 = or(T_5223, T_5225) - node T_5337 = or(T_5336, T_5227) - node T_5338 = or(T_5337, T_5229) - node T_5339 = or(T_5338, T_5231) - node T_5340 = or(T_5339, T_5233) - node T_5341 = or(T_5340, T_5235) - node T_5342 = or(T_5341, T_5237) - node T_5343 = or(T_5342, T_5239) - node T_5344 = or(T_5343, T_5241) - node T_5345 = or(T_5344, T_5243) - node T_5346 = or(T_5345, T_5245) - node T_5347 = or(T_5346, T_5247) - node T_5348 = or(T_5347, T_5249) - node T_5349 = or(T_5348, T_5251) - node T_5350 = or(T_5349, T_5253) - node T_5351 = or(T_5350, T_5255) - node T_5352 = or(T_5351, T_5257) - node T_5353 = or(T_5352, T_5259) - node T_5354 = or(T_5353, T_5261) - node T_5355 = or(T_5354, T_5263) - node T_5356 = or(T_5355, T_5265) - node T_5357 = or(T_5356, T_5267) - node T_5358 = or(T_5357, T_5269) - node T_5359 = or(T_5358, T_5271) - node T_5360 = or(T_5359, T_5273) - node T_5361 = or(T_5360, T_5275) - node T_5362 = or(T_5361, T_5277) - node T_5363 = or(T_5362, T_5279) - node T_5364 = or(T_5363, T_5281) - node T_5365 = or(T_5364, T_5283) - node T_5366 = or(T_5365, T_5285) - node T_5367 = or(T_5366, T_5287) - node T_5368 = or(T_5367, T_5289) - node T_5369 = or(T_5368, T_5291) - node T_5370 = or(T_5369, T_5293) - node T_5371 = or(T_5370, T_5295) - node T_5372 = or(T_5371, T_5297) - node T_5373 = or(T_5372, T_5299) - node T_5374 = or(T_5373, T_5301) - node T_5375 = or(T_5374, T_5303) - node T_5376 = or(T_5375, T_5305) - node T_5377 = or(T_5376, T_5307) - node T_5378 = or(T_5377, T_5309) - node T_5379 = or(T_5378, T_5311) - node T_5380 = or(T_5379, T_5313) - node T_5381 = or(T_5380, T_5315) - node T_5382 = or(T_5381, T_5317) - node T_5383 = or(T_5382, T_5319) - node T_5384 = or(T_5383, T_5321) - node T_5385 = or(T_5384, T_5323) - node T_5386 = or(T_5385, T_5325) - node T_5387 = or(T_5386, T_5327) - node T_5388 = or(T_5387, T_5329) - node T_5389 = or(T_5388, T_5331) - node T_5390 = or(T_5389, T_5333) - node addr_valid = or(T_5390, T_5335) - node T_5392 = or(T_5223, T_5225) - node fp_csr = or(T_5392, T_5227) - node csr_addr_priv = bits(io.rw.addr, 9, 8) - node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) - node T_5396 = bits(io.rw.addr, 11, 10) - node T_5397 = not(T_5396) - node read_only = eq(T_5397, UInt<1>("h00")) - node T_5400 = neq(io.rw.cmd, UInt<3>("h05")) - node T_5401 = and(cpu_ren, T_5400) - node cpu_wen = and(T_5401, priv_sufficient) - node T_5404 = eq(read_only, UInt<1>("h00")) - node T_5405 = and(cpu_wen, T_5404) - node T_5406 = and(host_csr_req_fire, host_csr_bits.rw) - node wen = or(T_5405, T_5406) - node T_5408 = eq(io.rw.cmd, UInt<3>("h01")) - node T_5409 = eq(io.rw.cmd, UInt<3>("h03")) - node T_5410 = not(io.rw.wdata) - node T_5411 = and(io.rw.rdata, T_5410) - node T_5412 = eq(io.rw.cmd, UInt<3>("h02")) - node T_5413 = or(io.rw.rdata, io.rw.wdata) - node T_5414 = mux(T_5412, T_5413, host_csr_bits.data) - node T_5415 = mux(T_5409, T_5411, T_5414) - node wdata = mux(T_5408, io.rw.wdata, T_5415) - node T_5417 = bits(io.rw.addr, 8, 8) - node T_5419 = eq(T_5417, UInt<1>("h00")) - node T_5420 = bits(io.rw.addr, 0, 0) - node T_5422 = eq(T_5420, UInt<1>("h00")) - node T_5423 = and(T_5419, T_5422) - node insn_call = and(T_5423, system_insn) - node T_5425 = bits(io.rw.addr, 8, 8) - node T_5427 = eq(T_5425, UInt<1>("h00")) - node T_5428 = bits(io.rw.addr, 0, 0) - node T_5429 = and(T_5427, T_5428) - node insn_break = and(T_5429, system_insn) - node T_5431 = bits(io.rw.addr, 8, 8) - node T_5432 = bits(io.rw.addr, 1, 1) - node T_5434 = eq(T_5432, UInt<1>("h00")) - node T_5435 = and(T_5431, T_5434) - node T_5436 = bits(io.rw.addr, 0, 0) - node T_5438 = eq(T_5436, UInt<1>("h00")) - node T_5439 = and(T_5435, T_5438) - node T_5440 = and(T_5439, system_insn) - node insn_ret = and(T_5440, priv_sufficient) - node T_5442 = bits(io.rw.addr, 8, 8) - node T_5443 = bits(io.rw.addr, 1, 1) - node T_5445 = eq(T_5443, UInt<1>("h00")) - node T_5446 = and(T_5442, T_5445) - node T_5447 = bits(io.rw.addr, 0, 0) - node T_5448 = and(T_5446, T_5447) - node T_5449 = and(T_5448, system_insn) - node insn_sfence_vm = and(T_5449, priv_sufficient) - node T_5451 = bits(io.rw.addr, 2, 2) - node maybe_insn_redirect_trap = and(T_5451, system_insn) - node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) - node T_5454 = bits(io.rw.addr, 8, 8) - node T_5455 = bits(io.rw.addr, 1, 1) - node T_5456 = and(T_5454, T_5455) - node T_5457 = bits(io.rw.addr, 0, 0) - node T_5459 = eq(T_5457, UInt<1>("h00")) - node T_5460 = and(T_5456, T_5459) - node T_5461 = and(T_5460, system_insn) - node insn_wfi = and(T_5461, priv_sufficient) - node T_5463 = and(cpu_wen, read_only) - node T_5465 = eq(priv_sufficient, UInt<1>("h00")) - node T_5467 = eq(addr_valid, UInt<1>("h00")) - node T_5468 = or(T_5465, T_5467) - node T_5470 = neq(io.status.fs, UInt<1>("h00")) - node T_5472 = eq(T_5470, UInt<1>("h00")) - node T_5473 = and(fp_csr, T_5472) - node T_5474 = or(T_5468, T_5473) - node T_5475 = and(cpu_ren, T_5474) - node T_5476 = or(T_5463, T_5475) - node T_5478 = eq(priv_sufficient, UInt<1>("h00")) - node T_5479 = and(system_insn, T_5478) - node T_5480 = or(T_5476, T_5479) - node T_5481 = or(T_5480, insn_call) - node csr_xcpt = or(T_5481, insn_break) - when insn_wfi : - reg_wfi <= UInt<1>("h01") - skip - when some_interrupt_pending : - reg_wfi <= UInt<1>("h00") - skip - io.fatc <= insn_sfence_vm - node T_5485 = or(io.exception, csr_xcpt) - node T_5486 = shl(reg_mstatus.prv, 6) - node T_5488 = add(T_5486, UInt<9>("h0100")) - node T_5489 = tail(T_5488, 1) - node T_5490 = bits(reg_stvec, 38, 38) - node T_5491 = cat(T_5490, reg_stvec) - node T_5492 = bits(reg_mstatus.prv, 1, 1) - node T_5494 = or(T_5492, UInt<1>("h00")) - node T_5495 = mux(T_5494, reg_mepc, reg_sepc) - node T_5496 = mux(maybe_insn_redirect_trap, T_5491, T_5495) - node T_5497 = mux(T_5485, T_5489, T_5496) - io.evec <= T_5497 - io.ptbr <= reg_sptbr - io.csr_xcpt <= csr_xcpt - node T_5498 = or(insn_ret, insn_redirect_trap) - io.eret <= T_5498 - io.status <- reg_mstatus - node T_5500 = neq(reg_mstatus.fs, UInt<1>("h00")) - node T_5502 = sub(UInt<2>("h00"), T_5500) - node T_5503 = tail(T_5502, 1) - io.status.fs <= T_5503 - node T_5505 = neq(reg_mstatus.xs, UInt<1>("h00")) - node T_5507 = sub(UInt<2>("h00"), T_5505) - node T_5508 = tail(T_5507, 1) - io.status.xs <= T_5508 - node T_5509 = not(io.status.fs) - node T_5511 = eq(T_5509, UInt<1>("h00")) - node T_5512 = not(io.status.xs) - node T_5514 = eq(T_5512, UInt<1>("h00")) - node T_5515 = or(T_5511, T_5514) - io.status.sd <= T_5515 - node T_5516 = or(io.exception, csr_xcpt) - when T_5516 : - reg_mstatus.ie <= UInt<1>("h00") - reg_mstatus.prv <= UInt<2>("h03") - reg_mstatus.mprv <= UInt<1>("h00") - reg_mstatus.prv1 <= reg_mstatus.prv - reg_mstatus.ie1 <= reg_mstatus.ie - reg_mstatus.prv2 <= reg_mstatus.prv1 - reg_mstatus.ie2 <= reg_mstatus.ie1 - node T_5520 = not(io.pc) - node T_5522 = or(T_5520, UInt<2>("h03")) - node T_5523 = not(T_5522) - reg_mepc <= T_5523 - reg_mcause <= io.cause - when csr_xcpt : - reg_mcause <= UInt<2>("h02") - when insn_break : - reg_mcause <= UInt<2>("h03") - skip - when insn_call : - node T_5527 = add(reg_mstatus.prv, UInt<4>("h08")) - node T_5528 = tail(T_5527, 1) - reg_mcause <= T_5528 - skip - skip - reg_mbadaddr <= io.pc - node T_5530 = eq(io.cause, UInt<3>("h05")) - node T_5532 = eq(io.cause, UInt<3>("h04")) - node T_5533 = or(T_5530, T_5532) - node T_5535 = eq(io.cause, UInt<3>("h07")) - node T_5536 = or(T_5533, T_5535) - node T_5538 = eq(io.cause, UInt<3>("h06")) - node T_5539 = or(T_5536, T_5538) - when T_5539 : - node T_5540 = bits(io.rw.wdata, 63, 39) - node T_5541 = bits(io.rw.wdata, 38, 0) - node T_5542 = asSInt(T_5541) - node T_5544 = lt(T_5542, asSInt(UInt<1>("h00"))) - node T_5545 = not(T_5540) - node T_5547 = eq(T_5545, UInt<1>("h00")) - node T_5549 = neq(T_5540, UInt<1>("h00")) - node T_5550 = mux(T_5544, T_5547, T_5549) - node T_5551 = cat(T_5550, T_5541) - reg_mbadaddr <= T_5551 - skip - skip - when insn_ret : - reg_mstatus.ie <= reg_mstatus.ie1 - reg_mstatus.prv <= reg_mstatus.prv1 - reg_mstatus.prv1 <= reg_mstatus.prv2 - reg_mstatus.ie1 <= reg_mstatus.ie2 - reg_mstatus.prv2 <= UInt<1>("h00") - reg_mstatus.ie2 <= UInt<1>("h01") - skip - when insn_redirect_trap : - reg_mstatus.prv <= UInt<1>("h01") - reg_sbadaddr <= reg_mbadaddr - reg_scause <= reg_mcause - reg_sepc <= reg_mepc - skip - node T_5556 = cat(UInt<1>("h00"), insn_redirect_trap) - node T_5557 = add(insn_ret, T_5556) - node T_5558 = tail(T_5557, 1) - node T_5561 = cat(UInt<1>("h00"), csr_xcpt) - node T_5562 = add(io.exception, T_5561) - node T_5563 = tail(T_5562, 1) - node T_5564 = cat(UInt<1>("h00"), T_5563) - node T_5565 = add(T_5558, T_5564) - node T_5566 = tail(T_5565, 1) - node T_5568 = leq(T_5566, UInt<1>("h01")) - node T_5570 = eq(reset, UInt<1>("h00")) - when T_5570 : - node T_5572 = eq(T_5568, UInt<1>("h00")) - when T_5572 : - node T_5574 = eq(reset, UInt<1>("h00")) - when T_5574 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_5575 = geq(reg_time, reg_mtimecmp) - when T_5575 : - reg_mip.mtip <= UInt<1>("h01") - skip - io.time <= T_4615 - io.csr_stall <= reg_wfi - node T_5578 = eq(host_csr_bits.rw, UInt<1>("h00")) - node T_5579 = and(host_csr_req_fire, T_5578) - node T_5580 = and(T_5579, T_5277) - when T_5580 : - reg_tohost <= UInt<1>("h00") - skip - node T_5583 = mux(T_5223, reg_fflags, UInt<1>("h00")) - node T_5585 = mux(T_5225, reg_frm, UInt<1>("h00")) - node T_5587 = mux(T_5227, T_4990, UInt<1>("h00")) - node T_5589 = mux(T_5229, T_4615, UInt<1>("h00")) - node T_5591 = mux(T_5231, T_4615, UInt<1>("h00")) - node T_5593 = mux(T_5233, reg_time, UInt<1>("h00")) - node T_5595 = mux(T_5235, reg_time, UInt<1>("h00")) - node T_5597 = mux(T_5237, reg_time, UInt<1>("h00")) - node T_5599 = mux(T_5239, reg_time, UInt<1>("h00")) - node T_5601 = mux(T_5241, reg_time, UInt<1>("h00")) - node T_5603 = mux(T_5243, UInt<64>("h08000000000041129"), UInt<1>("h00")) - node T_5605 = mux(T_5245, UInt<1>("h01"), UInt<1>("h00")) - node T_5607 = mux(T_5247, read_mstatus, UInt<1>("h00")) - node T_5609 = mux(T_5249, UInt<1>("h00"), UInt<1>("h00")) - node T_5611 = mux(T_5251, UInt<1>("h00"), UInt<1>("h00")) - node T_5613 = mux(T_5253, UInt<9>("h0100"), UInt<1>("h00")) - node T_5615 = mux(T_5255, UInt<31>("h040000000"), UInt<1>("h00")) - node T_5617 = mux(T_5257, UInt<1>("h00"), UInt<1>("h00")) - node T_5619 = mux(T_5259, T_5004, UInt<1>("h00")) - node T_5621 = mux(T_5261, T_5011, UInt<1>("h00")) - node T_5623 = mux(T_5263, reg_mscratch, UInt<1>("h00")) - node T_5625 = mux(T_5265, T_5016, UInt<1>("h00")) - node T_5627 = mux(T_5267, T_5021, UInt<1>("h00")) - node T_5629 = mux(T_5269, reg_mcause, UInt<1>("h00")) - node T_5631 = mux(T_5271, reg_mtimecmp, UInt<1>("h00")) - node T_5633 = mux(T_5273, io.host.id, UInt<1>("h00")) - node T_5635 = shl(reg_stats, 0) - node T_5636 = mux(T_5275, T_5635, UInt<1>("h00")) - node T_5638 = mux(T_5277, reg_tohost, UInt<1>("h00")) - node T_5640 = mux(T_5279, reg_fromhost, UInt<1>("h00")) - node T_5642 = mux(T_5281, T_4598, UInt<1>("h00")) - node T_5644 = mux(T_5283, T_4598, UInt<1>("h00")) - node T_5646 = mux(T_5285, T_4631, UInt<1>("h00")) - node T_5648 = mux(T_5287, T_4647, UInt<1>("h00")) - node T_5650 = mux(T_5289, T_4663, UInt<1>("h00")) - node T_5652 = mux(T_5291, T_4679, UInt<1>("h00")) - node T_5654 = mux(T_5293, T_4695, UInt<1>("h00")) - node T_5656 = mux(T_5295, T_4711, UInt<1>("h00")) - node T_5658 = mux(T_5297, T_4727, UInt<1>("h00")) - node T_5660 = mux(T_5299, T_4743, UInt<1>("h00")) - node T_5662 = mux(T_5301, T_4759, UInt<1>("h00")) - node T_5664 = mux(T_5303, T_4775, UInt<1>("h00")) - node T_5666 = mux(T_5305, T_4791, UInt<1>("h00")) - node T_5668 = mux(T_5307, T_4807, UInt<1>("h00")) - node T_5670 = mux(T_5309, T_4823, UInt<1>("h00")) - node T_5672 = mux(T_5311, T_4839, UInt<1>("h00")) - node T_5674 = mux(T_5313, T_4855, UInt<1>("h00")) - node T_5676 = mux(T_5315, T_4871, UInt<1>("h00")) - node T_5678 = mux(T_5317, T_5190, UInt<1>("h00")) - node T_5680 = mux(T_5319, T_5197, UInt<1>("h00")) - node T_5682 = mux(T_5321, T_5204, UInt<1>("h00")) - node T_5684 = mux(T_5323, reg_sscratch, UInt<1>("h00")) - node T_5686 = mux(T_5325, reg_scause, UInt<1>("h00")) - node T_5688 = mux(T_5327, T_5209, UInt<1>("h00")) - node T_5690 = mux(T_5329, reg_sptbr, UInt<1>("h00")) - node T_5692 = mux(T_5331, UInt<1>("h00"), UInt<1>("h00")) - node T_5694 = mux(T_5333, T_5215, UInt<1>("h00")) - node T_5696 = mux(T_5335, T_5220, UInt<1>("h00")) - node T_5698 = or(T_5583, T_5585) - node T_5699 = or(T_5698, T_5587) - node T_5700 = or(T_5699, T_5589) - node T_5701 = or(T_5700, T_5591) - node T_5702 = or(T_5701, T_5593) - node T_5703 = or(T_5702, T_5595) - node T_5704 = or(T_5703, T_5597) - node T_5705 = or(T_5704, T_5599) - node T_5706 = or(T_5705, T_5601) - node T_5707 = or(T_5706, T_5603) - node T_5708 = or(T_5707, T_5605) - node T_5709 = or(T_5708, T_5607) - node T_5710 = or(T_5709, T_5609) - node T_5711 = or(T_5710, T_5611) - node T_5712 = or(T_5711, T_5613) - node T_5713 = or(T_5712, T_5615) - node T_5714 = or(T_5713, T_5617) - node T_5715 = or(T_5714, T_5619) - node T_5716 = or(T_5715, T_5621) - node T_5717 = or(T_5716, T_5623) - node T_5718 = or(T_5717, T_5625) - node T_5719 = or(T_5718, T_5627) - node T_5720 = or(T_5719, T_5629) - node T_5721 = or(T_5720, T_5631) - node T_5722 = or(T_5721, T_5633) - node T_5723 = or(T_5722, T_5636) - node T_5724 = or(T_5723, T_5638) - node T_5725 = or(T_5724, T_5640) - node T_5726 = or(T_5725, T_5642) - node T_5727 = or(T_5726, T_5644) - node T_5728 = or(T_5727, T_5646) - node T_5729 = or(T_5728, T_5648) - node T_5730 = or(T_5729, T_5650) - node T_5731 = or(T_5730, T_5652) - node T_5732 = or(T_5731, T_5654) - node T_5733 = or(T_5732, T_5656) - node T_5734 = or(T_5733, T_5658) - node T_5735 = or(T_5734, T_5660) - node T_5736 = or(T_5735, T_5662) - node T_5737 = or(T_5736, T_5664) - node T_5738 = or(T_5737, T_5666) - node T_5739 = or(T_5738, T_5668) - node T_5740 = or(T_5739, T_5670) - node T_5741 = or(T_5740, T_5672) - node T_5742 = or(T_5741, T_5674) - node T_5743 = or(T_5742, T_5676) - node T_5744 = or(T_5743, T_5678) - node T_5745 = or(T_5744, T_5680) - node T_5746 = or(T_5745, T_5682) - node T_5747 = or(T_5746, T_5684) - node T_5748 = or(T_5747, T_5686) - node T_5749 = or(T_5748, T_5688) - node T_5750 = or(T_5749, T_5690) - node T_5751 = or(T_5750, T_5692) - node T_5752 = or(T_5751, T_5694) - node T_5753 = or(T_5752, T_5696) - wire T_5754 : UInt<64> - T_5754 is invalid - T_5754 <= T_5753 - io.rw.rdata <= T_5754 - io.fcsr_rm <= reg_frm - when io.fcsr_flags.valid : - node T_5755 = or(reg_fflags, io.fcsr_flags.bits) - reg_fflags <= T_5755 - skip - when wen : - when T_5247 : - wire T_5790 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} - T_5790 is invalid - node T_5807 = bits(wdata, 0, 0) - T_5790.ie <= T_5807 - node T_5808 = bits(wdata, 2, 1) - T_5790.prv <= T_5808 - node T_5809 = bits(wdata, 3, 3) - T_5790.ie1 <= T_5809 - node T_5810 = bits(wdata, 5, 4) - T_5790.prv1 <= T_5810 - node T_5811 = bits(wdata, 6, 6) - T_5790.ie2 <= T_5811 - node T_5812 = bits(wdata, 8, 7) - T_5790.prv2 <= T_5812 - node T_5813 = bits(wdata, 9, 9) - T_5790.ie3 <= T_5813 - node T_5814 = bits(wdata, 11, 10) - T_5790.prv3 <= T_5814 - node T_5815 = bits(wdata, 13, 12) - T_5790.fs <= T_5815 - node T_5816 = bits(wdata, 15, 14) - T_5790.xs <= T_5816 - node T_5817 = bits(wdata, 16, 16) - T_5790.mprv <= T_5817 - node T_5818 = bits(wdata, 21, 17) - T_5790.vm <= T_5818 - node T_5819 = bits(wdata, 30, 22) - T_5790.zero1 <= T_5819 - node T_5820 = bits(wdata, 31, 31) - T_5790.sd_rv32 <= T_5820 - node T_5821 = bits(wdata, 62, 32) - T_5790.zero2 <= T_5821 - node T_5822 = bits(wdata, 63, 63) - T_5790.sd <= T_5822 - reg_mstatus.ie <= T_5790.ie - reg_mstatus.ie1 <= T_5790.ie1 - wire T_5827 : UInt<2>[3] - T_5827[0] <= UInt<2>("h03") - T_5827[1] <= UInt<1>("h00") - T_5827[2] <= UInt<1>("h01") - reg_mstatus.mprv <= T_5790.mprv - node T_5832 = eq(T_5827[0], T_5790.prv) - node T_5833 = eq(T_5827[1], T_5790.prv) - node T_5834 = eq(T_5827[2], T_5790.prv) - node T_5836 = or(UInt<1>("h00"), T_5832) - node T_5837 = or(T_5836, T_5833) - node T_5838 = or(T_5837, T_5834) - when T_5838 : - reg_mstatus.prv <= T_5790.prv - skip - node T_5839 = eq(T_5827[0], T_5790.prv1) - node T_5840 = eq(T_5827[1], T_5790.prv1) - node T_5841 = eq(T_5827[2], T_5790.prv1) - node T_5843 = or(UInt<1>("h00"), T_5839) - node T_5844 = or(T_5843, T_5840) - node T_5845 = or(T_5844, T_5841) - when T_5845 : - reg_mstatus.prv1 <= T_5790.prv1 - skip - node T_5846 = eq(T_5827[0], T_5790.prv2) - node T_5847 = eq(T_5827[1], T_5790.prv2) - node T_5848 = eq(T_5827[2], T_5790.prv2) - node T_5850 = or(UInt<1>("h00"), T_5846) - node T_5851 = or(T_5850, T_5847) - node T_5852 = or(T_5851, T_5848) - when T_5852 : - reg_mstatus.prv2 <= T_5790.prv2 - skip - reg_mstatus.ie2 <= T_5790.ie2 - node T_5854 = eq(T_5790.vm, UInt<1>("h00")) - when T_5854 : - reg_mstatus.vm <= UInt<1>("h00") - skip - node T_5857 = eq(T_5790.vm, UInt<4>("h09")) - when T_5857 : - reg_mstatus.vm <= UInt<4>("h09") - skip - reg_mstatus.fs <= T_5790.fs - skip - when T_5259 : - wire T_5877 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5877 is invalid - node T_5886 = bits(wdata, 0, 0) - T_5877.usip <= T_5886 - node T_5887 = bits(wdata, 1, 1) - T_5877.ssip <= T_5887 - node T_5888 = bits(wdata, 2, 2) - T_5877.hsip <= T_5888 - node T_5889 = bits(wdata, 3, 3) - T_5877.msip <= T_5889 - node T_5890 = bits(wdata, 4, 4) - T_5877.utip <= T_5890 - node T_5891 = bits(wdata, 5, 5) - T_5877.stip <= T_5891 - node T_5892 = bits(wdata, 6, 6) - T_5877.htip <= T_5892 - node T_5893 = bits(wdata, 7, 7) - T_5877.mtip <= T_5893 - reg_mip.ssip <= T_5877.ssip - reg_mip.stip <= T_5877.stip - reg_mip.msip <= T_5877.msip - skip - when T_5257 : - node T_5894 = bits(wdata, 0, 0) - reg_mip.msip <= T_5894 - skip - when T_5261 : - wire T_5913 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5913 is invalid - node T_5922 = bits(wdata, 0, 0) - T_5913.usip <= T_5922 - node T_5923 = bits(wdata, 1, 1) - T_5913.ssip <= T_5923 - node T_5924 = bits(wdata, 2, 2) - T_5913.hsip <= T_5924 - node T_5925 = bits(wdata, 3, 3) - T_5913.msip <= T_5925 - node T_5926 = bits(wdata, 4, 4) - T_5913.utip <= T_5926 - node T_5927 = bits(wdata, 5, 5) - T_5913.stip <= T_5927 - node T_5928 = bits(wdata, 6, 6) - T_5913.htip <= T_5928 - node T_5929 = bits(wdata, 7, 7) - T_5913.mtip <= T_5929 - reg_mie.ssip <= T_5913.ssip - reg_mie.stip <= T_5913.stip - reg_mie.msip <= T_5913.msip - reg_mie.mtip <= T_5913.mtip - skip - when T_5223 : - reg_fflags <= wdata - skip - when T_5225 : - reg_frm <= wdata - skip - when T_5227 : - reg_fflags <= wdata - node T_5930 = shr(wdata, 5) - reg_frm <= T_5930 - skip - when T_5265 : - node T_5931 = not(wdata) - node T_5933 = or(T_5931, UInt<2>("h03")) - node T_5934 = not(T_5933) - reg_mepc <= T_5934 - skip - when T_5263 : - reg_mscratch <= wdata - skip - when T_5269 : - node T_5936 = and(wdata, UInt<64>("h0800000000000001f")) - reg_mcause <= T_5936 - skip - when T_5267 : - node T_5937 = bits(wdata, 39, 0) - reg_mbadaddr <= T_5937 - skip - when T_5283 : - node T_5938 = bits(wdata, 5, 0) - T_4584 <= T_5938 - node T_5939 = bits(wdata, 63, 6) - T_4592 <= T_5939 - skip - when T_5271 : - reg_mtimecmp <= wdata - reg_mip.mtip <= UInt<1>("h00") - skip - when T_5241 : - reg_time <= wdata - skip - when T_5279 : - node T_5942 = eq(reg_fromhost, UInt<1>("h00")) - node T_5944 = eq(host_csr_req_fire, UInt<1>("h00")) - node T_5945 = or(T_5942, T_5944) - when T_5945 : - reg_fromhost <= wdata - skip - skip - when T_5277 : - node T_5947 = eq(reg_tohost, UInt<1>("h00")) - node T_5948 = or(T_5947, host_csr_req_fire) - when T_5948 : - reg_tohost <= wdata - skip - skip - when T_5275 : - node T_5949 = bits(wdata, 0, 0) - reg_stats <= T_5949 - skip - when T_5317 : - wire T_5976 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5976 is invalid - node T_5989 = bits(wdata, 0, 0) - T_5976.ie <= T_5989 - node T_5990 = bits(wdata, 2, 1) - T_5976.zero1 <= T_5990 - node T_5991 = bits(wdata, 3, 3) - T_5976.pie <= T_5991 - node T_5992 = bits(wdata, 4, 4) - T_5976.ps <= T_5992 - node T_5993 = bits(wdata, 11, 5) - T_5976.zero2 <= T_5993 - node T_5994 = bits(wdata, 13, 12) - T_5976.fs <= T_5994 - node T_5995 = bits(wdata, 15, 14) - T_5976.xs <= T_5995 - node T_5996 = bits(wdata, 16, 16) - T_5976.mprv <= T_5996 - node T_5997 = bits(wdata, 30, 17) - T_5976.zero3 <= T_5997 - node T_5998 = bits(wdata, 31, 31) - T_5976.sd_rv32 <= T_5998 - node T_5999 = bits(wdata, 62, 32) - T_5976.zero4 <= T_5999 - node T_6000 = bits(wdata, 63, 63) - T_5976.sd <= T_6000 - reg_mstatus.ie <= T_5976.ie - reg_mstatus.ie1 <= T_5976.pie - node T_6003 = mux(T_5976.ps, UInt<1>("h01"), UInt<1>("h00")) - reg_mstatus.prv1 <= T_6003 - reg_mstatus.mprv <= T_5976.mprv - reg_mstatus.fs <= T_5976.fs - skip - when T_5319 : - wire T_6022 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6022 is invalid - node T_6031 = bits(wdata, 0, 0) - T_6022.usip <= T_6031 - node T_6032 = bits(wdata, 1, 1) - T_6022.ssip <= T_6032 - node T_6033 = bits(wdata, 2, 2) - T_6022.hsip <= T_6033 - node T_6034 = bits(wdata, 3, 3) - T_6022.msip <= T_6034 - node T_6035 = bits(wdata, 4, 4) - T_6022.utip <= T_6035 - node T_6036 = bits(wdata, 5, 5) - T_6022.stip <= T_6036 - node T_6037 = bits(wdata, 6, 6) - T_6022.htip <= T_6037 - node T_6038 = bits(wdata, 7, 7) - T_6022.mtip <= T_6038 - reg_mip.ssip <= T_6022.ssip - skip - when T_5321 : - wire T_6057 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6057 is invalid - node T_6066 = bits(wdata, 0, 0) - T_6057.usip <= T_6066 - node T_6067 = bits(wdata, 1, 1) - T_6057.ssip <= T_6067 - node T_6068 = bits(wdata, 2, 2) - T_6057.hsip <= T_6068 - node T_6069 = bits(wdata, 3, 3) - T_6057.msip <= T_6069 - node T_6070 = bits(wdata, 4, 4) - T_6057.utip <= T_6070 - node T_6071 = bits(wdata, 5, 5) - T_6057.stip <= T_6071 - node T_6072 = bits(wdata, 6, 6) - T_6057.htip <= T_6072 - node T_6073 = bits(wdata, 7, 7) - T_6057.mtip <= T_6073 - reg_mie.ssip <= T_6057.ssip - reg_mie.stip <= T_6057.stip - skip - when T_5323 : - reg_sscratch <= wdata - skip - when T_5329 : - node T_6074 = bits(wdata, 31, 12) - node T_6076 = cat(T_6074, UInt<12>("h00")) - reg_sptbr <= T_6076 - skip - when T_5333 : - node T_6077 = not(wdata) - node T_6079 = or(T_6077, UInt<2>("h03")) - node T_6080 = not(T_6079) - reg_sepc <= T_6080 - skip - when T_5335 : - node T_6081 = not(wdata) - node T_6083 = or(T_6081, UInt<2>("h03")) - node T_6084 = not(T_6083) - reg_stvec <= T_6084 - skip - skip - when reset : - reg_mstatus.zero1 <= UInt<1>("h00") - reg_mstatus.zero2 <= UInt<1>("h00") - reg_mstatus.ie <= UInt<1>("h00") - reg_mstatus.prv <= UInt<2>("h03") - reg_mstatus.ie1 <= UInt<1>("h00") - reg_mstatus.prv1 <= UInt<2>("h03") - reg_mstatus.ie2 <= UInt<1>("h00") - reg_mstatus.prv2 <= UInt<1>("h00") - reg_mstatus.ie3 <= UInt<1>("h00") - reg_mstatus.prv3 <= UInt<1>("h00") - reg_mstatus.mprv <= UInt<1>("h00") - reg_mstatus.vm <= UInt<1>("h00") - reg_mstatus.fs <= UInt<1>("h00") - reg_mstatus.xs <= UInt<1>("h00") - reg_mstatus.sd_rv32 <= UInt<1>("h00") - reg_mstatus.sd <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module ALU : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_27 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_28 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_28 : + input clock : Clock input reset : UInt<1> - output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - node T_11 = bits(io.fn, 3, 3) - node T_12 = not(io.in2) - node in2_inv = mux(T_11, T_12, io.in2) - node in1_xor_in2 = xor(io.in1, in2_inv) - node T_15 = add(io.in1, in2_inv) - node T_16 = tail(T_15, 1) - node T_17 = bits(io.fn, 3, 3) - node T_18 = add(T_16, T_17) - node T_19 = tail(T_18, 1) - io.adder_out <= T_19 - node T_20 = bits(io.fn, 0, 0) - node T_21 = bits(io.fn, 3, 3) - node T_23 = eq(T_21, UInt<1>("h00")) - node T_25 = eq(in1_xor_in2, UInt<1>("h00")) - node T_26 = bits(io.in1, 63, 63) - node T_27 = bits(io.in2, 63, 63) - node T_28 = eq(T_26, T_27) - node T_29 = bits(io.adder_out, 63, 63) - node T_30 = bits(io.fn, 1, 1) - node T_31 = bits(io.in2, 63, 63) - node T_32 = bits(io.in1, 63, 63) - node T_33 = mux(T_30, T_31, T_32) - node T_34 = mux(T_28, T_29, T_33) - node T_35 = mux(T_23, T_25, T_34) - node T_36 = xor(T_20, T_35) - io.cmp_out <= T_36 - node T_37 = bits(io.fn, 3, 3) - node T_38 = bits(io.in1, 31, 31) - node T_39 = and(T_37, T_38) - node T_41 = sub(UInt<32>("h00"), T_39) - node T_42 = tail(T_41, 1) - node T_45 = and(io.dw, UInt<1>("h01")) - node T_46 = eq(UInt<1>("h01"), T_45) - node T_47 = bits(io.in1, 63, 32) - node T_48 = mux(T_46, T_47, T_42) - node T_49 = bits(io.in2, 5, 5) - node T_52 = and(io.dw, UInt<1>("h01")) - node T_53 = eq(UInt<1>("h01"), T_52) - node T_54 = and(T_49, T_53) - node T_55 = bits(io.in2, 4, 0) - node shamt = cat(T_54, T_55) - node T_57 = bits(io.in1, 31, 0) - node shin_r = cat(T_48, T_57) - node T_59 = eq(io.fn, UInt<3>("h05")) - node T_60 = eq(io.fn, UInt<4>("h0b")) - node T_61 = or(T_59, T_60) - node T_64 = shl(UInt<32>("h0ffffffff"), 32) - node T_65 = xor(UInt<64>("h0ffffffffffffffff"), T_64) - node T_66 = shr(shin_r, 32) - node T_67 = and(T_66, T_65) - node T_68 = bits(shin_r, 31, 0) - node T_69 = shl(T_68, 32) - node T_70 = not(T_65) - node T_71 = and(T_69, T_70) - node T_72 = or(T_67, T_71) - node T_73 = bits(T_65, 47, 0) - node T_74 = shl(T_73, 16) - node T_75 = xor(T_65, T_74) - node T_76 = shr(T_72, 16) - node T_77 = and(T_76, T_75) - node T_78 = bits(T_72, 47, 0) - node T_79 = shl(T_78, 16) - node T_80 = not(T_75) - node T_81 = and(T_79, T_80) - node T_82 = or(T_77, T_81) - node T_83 = bits(T_75, 55, 0) - node T_84 = shl(T_83, 8) - node T_85 = xor(T_75, T_84) - node T_86 = shr(T_82, 8) - node T_87 = and(T_86, T_85) - node T_88 = bits(T_82, 55, 0) - node T_89 = shl(T_88, 8) - node T_90 = not(T_85) - node T_91 = and(T_89, T_90) - node T_92 = or(T_87, T_91) - node T_93 = bits(T_85, 59, 0) - node T_94 = shl(T_93, 4) - node T_95 = xor(T_85, T_94) - node T_96 = shr(T_92, 4) - node T_97 = and(T_96, T_95) - node T_98 = bits(T_92, 59, 0) - node T_99 = shl(T_98, 4) - node T_100 = not(T_95) - node T_101 = and(T_99, T_100) - node T_102 = or(T_97, T_101) - node T_103 = bits(T_95, 61, 0) - node T_104 = shl(T_103, 2) - node T_105 = xor(T_95, T_104) - node T_106 = shr(T_102, 2) - node T_107 = and(T_106, T_105) - node T_108 = bits(T_102, 61, 0) - node T_109 = shl(T_108, 2) - node T_110 = not(T_105) - node T_111 = and(T_109, T_110) - node T_112 = or(T_107, T_111) - node T_113 = bits(T_105, 62, 0) - node T_114 = shl(T_113, 1) - node T_115 = xor(T_105, T_114) - node T_116 = shr(T_112, 1) - node T_117 = and(T_116, T_115) - node T_118 = bits(T_112, 62, 0) - node T_119 = shl(T_118, 1) - node T_120 = not(T_115) - node T_121 = and(T_119, T_120) - node T_122 = or(T_117, T_121) - node shin = mux(T_61, shin_r, T_122) - node T_124 = bits(io.fn, 3, 3) - node T_125 = bits(shin, 63, 63) - node T_126 = and(T_124, T_125) - node T_127 = cat(T_126, shin) - node T_128 = asSInt(T_127) - node T_129 = dshr(T_128, shamt) - node shout_r = bits(T_129, 63, 0) - node T_133 = shl(UInt<32>("h0ffffffff"), 32) - node T_134 = xor(UInt<64>("h0ffffffffffffffff"), T_133) - node T_135 = shr(shout_r, 32) - node T_136 = and(T_135, T_134) - node T_137 = bits(shout_r, 31, 0) - node T_138 = shl(T_137, 32) - node T_139 = not(T_134) - node T_140 = and(T_138, T_139) - node T_141 = or(T_136, T_140) - node T_142 = bits(T_134, 47, 0) - node T_143 = shl(T_142, 16) - node T_144 = xor(T_134, T_143) - node T_145 = shr(T_141, 16) - node T_146 = and(T_145, T_144) - node T_147 = bits(T_141, 47, 0) - node T_148 = shl(T_147, 16) - node T_149 = not(T_144) - node T_150 = and(T_148, T_149) - node T_151 = or(T_146, T_150) - node T_152 = bits(T_144, 55, 0) - node T_153 = shl(T_152, 8) - node T_154 = xor(T_144, T_153) - node T_155 = shr(T_151, 8) - node T_156 = and(T_155, T_154) - node T_157 = bits(T_151, 55, 0) - node T_158 = shl(T_157, 8) - node T_159 = not(T_154) - node T_160 = and(T_158, T_159) - node T_161 = or(T_156, T_160) - node T_162 = bits(T_154, 59, 0) - node T_163 = shl(T_162, 4) - node T_164 = xor(T_154, T_163) - node T_165 = shr(T_161, 4) - node T_166 = and(T_165, T_164) - node T_167 = bits(T_161, 59, 0) - node T_168 = shl(T_167, 4) - node T_169 = not(T_164) - node T_170 = and(T_168, T_169) - node T_171 = or(T_166, T_170) - node T_172 = bits(T_164, 61, 0) - node T_173 = shl(T_172, 2) - node T_174 = xor(T_164, T_173) - node T_175 = shr(T_171, 2) - node T_176 = and(T_175, T_174) - node T_177 = bits(T_171, 61, 0) - node T_178 = shl(T_177, 2) - node T_179 = not(T_174) - node T_180 = and(T_178, T_179) - node T_181 = or(T_176, T_180) - node T_182 = bits(T_174, 62, 0) - node T_183 = shl(T_182, 1) - node T_184 = xor(T_174, T_183) - node T_185 = shr(T_181, 1) - node T_186 = and(T_185, T_184) - node T_187 = bits(T_181, 62, 0) - node T_188 = shl(T_187, 1) - node T_189 = not(T_184) - node T_190 = and(T_188, T_189) - node shout_l = or(T_186, T_190) - node T_192 = eq(io.fn, UInt<3>("h05")) - node T_193 = eq(io.fn, UInt<4>("h0b")) - node T_194 = or(T_192, T_193) - node T_196 = mux(T_194, shout_r, UInt<1>("h00")) - node T_197 = eq(io.fn, UInt<1>("h01")) - node T_199 = mux(T_197, shout_l, UInt<1>("h00")) - node shout = or(T_196, T_199) - node T_201 = eq(io.fn, UInt<3>("h04")) - node T_202 = eq(io.fn, UInt<3>("h06")) - node T_203 = or(T_201, T_202) - node T_205 = mux(T_203, in1_xor_in2, UInt<1>("h00")) - node T_206 = eq(io.fn, UInt<3>("h06")) - node T_207 = eq(io.fn, UInt<3>("h07")) - node T_208 = or(T_206, T_207) - node T_209 = and(io.in1, io.in2) - node T_211 = mux(T_208, T_209, UInt<1>("h00")) - node logic = or(T_205, T_211) - node T_213 = eq(io.fn, UInt<2>("h02")) - node T_214 = eq(io.fn, UInt<2>("h03")) - node T_215 = or(T_213, T_214) - node T_216 = geq(io.fn, UInt<4>("h0c")) - node T_217 = or(T_215, T_216) - node T_218 = and(T_217, io.cmp_out) - node T_219 = or(T_218, logic) - node shift_logic = or(T_219, shout) - node T_221 = eq(io.fn, UInt<1>("h00")) - node T_222 = eq(io.fn, UInt<4>("h0a")) - node T_223 = or(T_221, T_222) - node out = mux(T_223, io.adder_out, shift_logic) - io.out <= out - node T_227 = and(io.dw, UInt<1>("h01")) - node T_228 = eq(UInt<1>("h00"), T_227) - when T_228 : - node T_229 = bits(out, 31, 31) - node T_231 = sub(UInt<32>("h00"), T_229) - node T_232 = tail(T_231, 1) - node T_233 = bits(out, 31, 0) - node T_234 = cat(T_232, T_233) - io.out <= T_234 - skip + io is invalid + inst reg_0 of AsyncResetReg_28 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module MulDiv : - input clk : Clock + module AsyncValidSync_5 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} + output io : {flip in : UInt<1>, out : UInt<1>} io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk - reg count : UInt<7>, clk - reg neg_out : UInt<1>, clk - reg isMul : UInt<1>, clk - reg isHi : UInt<1>, clk - reg divisor : UInt<65>, clk - reg remainder : UInt<130>, clk - node T_81 = and(io.req.bits.fn, UInt<4>("h04")) - node T_83 = eq(T_81, UInt<4>("h00")) - node T_85 = and(io.req.bits.fn, UInt<4>("h08")) - node T_87 = eq(T_85, UInt<4>("h08")) - node T_89 = or(UInt<1>("h00"), T_83) - node T_90 = or(T_89, T_87) - node T_92 = and(io.req.bits.fn, UInt<4>("h05")) - node T_94 = eq(T_92, UInt<4>("h01")) - node T_96 = and(io.req.bits.fn, UInt<4>("h02")) - node T_98 = eq(T_96, UInt<4>("h02")) - node T_100 = or(UInt<1>("h00"), T_94) - node T_101 = or(T_100, T_98) - node T_102 = or(T_101, T_87) - node T_104 = and(io.req.bits.fn, UInt<4>("h09")) - node T_106 = eq(T_104, UInt<4>("h00")) - node T_108 = and(io.req.bits.fn, UInt<4>("h03")) - node T_110 = eq(T_108, UInt<4>("h00")) - node T_112 = or(UInt<1>("h00"), T_106) - node T_113 = or(T_112, T_83) - node T_114 = or(T_113, T_110) - node T_116 = or(UInt<1>("h00"), T_106) - node T_117 = or(T_116, T_83) - node cmdMul = bits(T_90, 0, 0) - node cmdHi = bits(T_102, 0, 0) - node lhsSigned = bits(T_114, 0, 0) - node rhsSigned = bits(T_117, 0, 0) - node T_124 = and(io.req.bits.dw, UInt<1>("h01")) - node T_125 = eq(UInt<1>("h01"), T_124) - node T_126 = bits(io.req.bits.in1, 63, 63) - node T_127 = bits(io.req.bits.in1, 31, 31) - node T_128 = mux(T_125, T_126, T_127) - node lhs_sign = and(lhsSigned, T_128) - node T_132 = and(io.req.bits.dw, UInt<1>("h01")) - node T_133 = eq(UInt<1>("h01"), T_132) - node T_134 = bits(io.req.bits.in1, 63, 32) - node T_136 = sub(UInt<32>("h00"), lhs_sign) - node T_137 = tail(T_136, 1) - node T_138 = mux(T_133, T_134, T_137) - node T_139 = bits(io.req.bits.in1, 31, 0) - node lhs_in = cat(T_138, T_139) - node T_143 = and(io.req.bits.dw, UInt<1>("h01")) - node T_144 = eq(UInt<1>("h01"), T_143) - node T_145 = bits(io.req.bits.in2, 63, 63) - node T_146 = bits(io.req.bits.in2, 31, 31) - node T_147 = mux(T_144, T_145, T_146) - node rhs_sign = and(rhsSigned, T_147) - node T_151 = and(io.req.bits.dw, UInt<1>("h01")) - node T_152 = eq(UInt<1>("h01"), T_151) - node T_153 = bits(io.req.bits.in2, 63, 32) - node T_155 = sub(UInt<32>("h00"), rhs_sign) - node T_156 = tail(T_155, 1) - node T_157 = mux(T_152, T_153, T_156) - node T_158 = bits(io.req.bits.in2, 31, 0) - node rhs_in = cat(T_157, T_158) - node T_160 = bits(remainder, 128, 64) - node T_161 = bits(divisor, 64, 0) - node T_162 = sub(T_160, T_161) - node subtractor = tail(T_162, 1) - node less = bits(subtractor, 64, 64) - node T_165 = bits(remainder, 63, 0) - node T_167 = sub(UInt<1>("h00"), T_165) - node negated_remainder = tail(T_167, 1) - node T_169 = eq(state, UInt<1>("h01")) - when T_169 : - node T_170 = bits(remainder, 63, 63) - node T_171 = or(T_170, isMul) - when T_171 : - remainder <= negated_remainder - skip - node T_172 = bits(divisor, 63, 63) - node T_173 = or(T_172, isMul) - when T_173 : - divisor <= subtractor - skip - state <= UInt<2>("h02") - skip - node T_174 = eq(state, UInt<3>("h04")) - when T_174 : - remainder <= negated_remainder - state <= UInt<3>("h05") - skip - node T_175 = eq(state, UInt<2>("h03")) - when T_175 : - node T_176 = bits(remainder, 128, 65) - remainder <= T_176 - node T_177 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - state <= T_177 - skip - node T_178 = eq(state, UInt<2>("h02")) - node T_179 = and(T_178, isMul) - when T_179 : - node T_180 = bits(remainder, 129, 65) - node T_181 = bits(remainder, 63, 0) - node T_182 = cat(T_180, T_181) - node T_183 = bits(T_182, 63, 0) - node T_184 = bits(T_182, 128, 64) - node T_185 = asSInt(T_184) - node T_186 = asSInt(divisor) - node T_187 = bits(T_183, 7, 0) - node T_188 = mul(T_186, T_187) - node T_189 = add(T_188, T_185) - node T_190 = tail(T_189, 1) - node T_191 = asSInt(T_190) - node T_192 = bits(T_183, 63, 8) - node T_193 = asUInt(T_191) - node T_194 = cat(T_193, T_192) - node T_197 = mul(count, UInt<4>("h08")) - node T_198 = bits(T_197, 5, 0) - node T_199 = dshr(asSInt(UInt<65>("h010000000000000000")), T_198) - node T_200 = bits(T_199, 63, 0) - node T_203 = neq(count, UInt<3>("h07")) - node T_204 = and(UInt<1>("h01"), T_203) - node T_206 = neq(count, UInt<1>("h00")) - node T_207 = and(T_204, T_206) - node T_209 = eq(isHi, UInt<1>("h00")) - node T_210 = and(T_207, T_209) - node T_211 = not(T_200) - node T_212 = and(T_183, T_211) - node T_214 = eq(T_212, UInt<1>("h00")) - node T_215 = and(T_210, T_214) - node T_218 = mul(count, UInt<4>("h08")) - node T_219 = sub(UInt<7>("h040"), T_218) - node T_220 = tail(T_219, 1) - node T_221 = bits(T_220, 5, 0) - node T_222 = dshr(T_182, T_221) - node T_223 = bits(T_194, 128, 64) - node T_224 = mux(T_215, T_222, T_194) - node T_225 = bits(T_224, 63, 0) - node T_226 = cat(T_223, T_225) - node T_227 = shr(T_226, 64) - node T_229 = bits(T_226, 63, 0) - node T_230 = cat(UInt<1>("h00"), T_229) - node T_231 = cat(T_227, T_230) - remainder <= T_231 - node T_233 = add(count, UInt<1>("h01")) - node T_234 = tail(T_233, 1) - count <= T_234 - node T_236 = eq(count, UInt<3>("h07")) - node T_237 = or(T_215, T_236) - when T_237 : - node T_238 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) - state <= T_238 - skip - skip - node T_239 = eq(state, UInt<2>("h02")) - node T_241 = eq(isMul, UInt<1>("h00")) - node T_242 = and(T_239, T_241) - when T_242 : - node T_244 = eq(count, UInt<7>("h040")) - when T_244 : - node T_245 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - node T_246 = mux(isHi, UInt<2>("h03"), T_245) - state <= T_246 - skip - node T_248 = add(count, UInt<1>("h01")) - node T_249 = tail(T_248, 1) - count <= T_249 - node T_250 = bits(remainder, 127, 64) - node T_251 = bits(subtractor, 63, 0) - node T_252 = mux(less, T_250, T_251) - node T_253 = bits(remainder, 63, 0) - node T_255 = eq(less, UInt<1>("h00")) - node T_256 = cat(T_253, T_255) - node T_257 = cat(T_252, T_256) - remainder <= T_257 - node T_258 = bits(divisor, 63, 0) - node T_259 = bits(T_258, 63, 63) - node T_261 = bits(T_258, 62, 62) - node T_263 = bits(T_258, 61, 61) - node T_265 = bits(T_258, 60, 60) - node T_267 = bits(T_258, 59, 59) - node T_269 = bits(T_258, 58, 58) - node T_271 = bits(T_258, 57, 57) - node T_273 = bits(T_258, 56, 56) - node T_275 = bits(T_258, 55, 55) - node T_277 = bits(T_258, 54, 54) - node T_279 = bits(T_258, 53, 53) - node T_281 = bits(T_258, 52, 52) - node T_283 = bits(T_258, 51, 51) - node T_285 = bits(T_258, 50, 50) - node T_287 = bits(T_258, 49, 49) - node T_289 = bits(T_258, 48, 48) - node T_291 = bits(T_258, 47, 47) - node T_293 = bits(T_258, 46, 46) - node T_295 = bits(T_258, 45, 45) - node T_297 = bits(T_258, 44, 44) - node T_299 = bits(T_258, 43, 43) - node T_301 = bits(T_258, 42, 42) - node T_303 = bits(T_258, 41, 41) - node T_305 = bits(T_258, 40, 40) - node T_307 = bits(T_258, 39, 39) - node T_309 = bits(T_258, 38, 38) - node T_311 = bits(T_258, 37, 37) - node T_313 = bits(T_258, 36, 36) - node T_315 = bits(T_258, 35, 35) - node T_317 = bits(T_258, 34, 34) - node T_319 = bits(T_258, 33, 33) - node T_321 = bits(T_258, 32, 32) - node T_323 = bits(T_258, 31, 31) - node T_325 = bits(T_258, 30, 30) - node T_327 = bits(T_258, 29, 29) - node T_329 = bits(T_258, 28, 28) - node T_331 = bits(T_258, 27, 27) - node T_333 = bits(T_258, 26, 26) - node T_335 = bits(T_258, 25, 25) - node T_337 = bits(T_258, 24, 24) - node T_339 = bits(T_258, 23, 23) - node T_341 = bits(T_258, 22, 22) - node T_343 = bits(T_258, 21, 21) - node T_345 = bits(T_258, 20, 20) - node T_347 = bits(T_258, 19, 19) - node T_349 = bits(T_258, 18, 18) - node T_351 = bits(T_258, 17, 17) - node T_353 = bits(T_258, 16, 16) - node T_355 = bits(T_258, 15, 15) - node T_357 = bits(T_258, 14, 14) - node T_359 = bits(T_258, 13, 13) - node T_361 = bits(T_258, 12, 12) - node T_363 = bits(T_258, 11, 11) - node T_365 = bits(T_258, 10, 10) - node T_367 = bits(T_258, 9, 9) - node T_369 = bits(T_258, 8, 8) - node T_371 = bits(T_258, 7, 7) - node T_373 = bits(T_258, 6, 6) - node T_375 = bits(T_258, 5, 5) - node T_377 = bits(T_258, 4, 4) - node T_379 = bits(T_258, 3, 3) - node T_381 = bits(T_258, 2, 2) - node T_383 = bits(T_258, 1, 1) - node T_384 = shl(T_383, 0) - node T_385 = mux(T_381, UInt<2>("h02"), T_384) - node T_386 = mux(T_379, UInt<2>("h03"), T_385) - node T_387 = mux(T_377, UInt<3>("h04"), T_386) - node T_388 = mux(T_375, UInt<3>("h05"), T_387) - node T_389 = mux(T_373, UInt<3>("h06"), T_388) - node T_390 = mux(T_371, UInt<3>("h07"), T_389) - node T_391 = mux(T_369, UInt<4>("h08"), T_390) - node T_392 = mux(T_367, UInt<4>("h09"), T_391) - node T_393 = mux(T_365, UInt<4>("h0a"), T_392) - node T_394 = mux(T_363, UInt<4>("h0b"), T_393) - node T_395 = mux(T_361, UInt<4>("h0c"), T_394) - node T_396 = mux(T_359, UInt<4>("h0d"), T_395) - node T_397 = mux(T_357, UInt<4>("h0e"), T_396) - node T_398 = mux(T_355, UInt<4>("h0f"), T_397) - node T_399 = mux(T_353, UInt<5>("h010"), T_398) - node T_400 = mux(T_351, UInt<5>("h011"), T_399) - node T_401 = mux(T_349, UInt<5>("h012"), T_400) - node T_402 = mux(T_347, UInt<5>("h013"), T_401) - node T_403 = mux(T_345, UInt<5>("h014"), T_402) - node T_404 = mux(T_343, UInt<5>("h015"), T_403) - node T_405 = mux(T_341, UInt<5>("h016"), T_404) - node T_406 = mux(T_339, UInt<5>("h017"), T_405) - node T_407 = mux(T_337, UInt<5>("h018"), T_406) - node T_408 = mux(T_335, UInt<5>("h019"), T_407) - node T_409 = mux(T_333, UInt<5>("h01a"), T_408) - node T_410 = mux(T_331, UInt<5>("h01b"), T_409) - node T_411 = mux(T_329, UInt<5>("h01c"), T_410) - node T_412 = mux(T_327, UInt<5>("h01d"), T_411) - node T_413 = mux(T_325, UInt<5>("h01e"), T_412) - node T_414 = mux(T_323, UInt<5>("h01f"), T_413) - node T_415 = mux(T_321, UInt<6>("h020"), T_414) - node T_416 = mux(T_319, UInt<6>("h021"), T_415) - node T_417 = mux(T_317, UInt<6>("h022"), T_416) - node T_418 = mux(T_315, UInt<6>("h023"), T_417) - node T_419 = mux(T_313, UInt<6>("h024"), T_418) - node T_420 = mux(T_311, UInt<6>("h025"), T_419) - node T_421 = mux(T_309, UInt<6>("h026"), T_420) - node T_422 = mux(T_307, UInt<6>("h027"), T_421) - node T_423 = mux(T_305, UInt<6>("h028"), T_422) - node T_424 = mux(T_303, UInt<6>("h029"), T_423) - node T_425 = mux(T_301, UInt<6>("h02a"), T_424) - node T_426 = mux(T_299, UInt<6>("h02b"), T_425) - node T_427 = mux(T_297, UInt<6>("h02c"), T_426) - node T_428 = mux(T_295, UInt<6>("h02d"), T_427) - node T_429 = mux(T_293, UInt<6>("h02e"), T_428) - node T_430 = mux(T_291, UInt<6>("h02f"), T_429) - node T_431 = mux(T_289, UInt<6>("h030"), T_430) - node T_432 = mux(T_287, UInt<6>("h031"), T_431) - node T_433 = mux(T_285, UInt<6>("h032"), T_432) - node T_434 = mux(T_283, UInt<6>("h033"), T_433) - node T_435 = mux(T_281, UInt<6>("h034"), T_434) - node T_436 = mux(T_279, UInt<6>("h035"), T_435) - node T_437 = mux(T_277, UInt<6>("h036"), T_436) - node T_438 = mux(T_275, UInt<6>("h037"), T_437) - node T_439 = mux(T_273, UInt<6>("h038"), T_438) - node T_440 = mux(T_271, UInt<6>("h039"), T_439) - node T_441 = mux(T_269, UInt<6>("h03a"), T_440) - node T_442 = mux(T_267, UInt<6>("h03b"), T_441) - node T_443 = mux(T_265, UInt<6>("h03c"), T_442) - node T_444 = mux(T_263, UInt<6>("h03d"), T_443) - node T_445 = mux(T_261, UInt<6>("h03e"), T_444) - node T_446 = mux(T_259, UInt<6>("h03f"), T_445) - node T_447 = bits(remainder, 63, 0) - node T_448 = bits(T_447, 63, 63) - node T_450 = bits(T_447, 62, 62) - node T_452 = bits(T_447, 61, 61) - node T_454 = bits(T_447, 60, 60) - node T_456 = bits(T_447, 59, 59) - node T_458 = bits(T_447, 58, 58) - node T_460 = bits(T_447, 57, 57) - node T_462 = bits(T_447, 56, 56) - node T_464 = bits(T_447, 55, 55) - node T_466 = bits(T_447, 54, 54) - node T_468 = bits(T_447, 53, 53) - node T_470 = bits(T_447, 52, 52) - node T_472 = bits(T_447, 51, 51) - node T_474 = bits(T_447, 50, 50) - node T_476 = bits(T_447, 49, 49) - node T_478 = bits(T_447, 48, 48) - node T_480 = bits(T_447, 47, 47) - node T_482 = bits(T_447, 46, 46) - node T_484 = bits(T_447, 45, 45) - node T_486 = bits(T_447, 44, 44) - node T_488 = bits(T_447, 43, 43) - node T_490 = bits(T_447, 42, 42) - node T_492 = bits(T_447, 41, 41) - node T_494 = bits(T_447, 40, 40) - node T_496 = bits(T_447, 39, 39) - node T_498 = bits(T_447, 38, 38) - node T_500 = bits(T_447, 37, 37) - node T_502 = bits(T_447, 36, 36) - node T_504 = bits(T_447, 35, 35) - node T_506 = bits(T_447, 34, 34) - node T_508 = bits(T_447, 33, 33) - node T_510 = bits(T_447, 32, 32) - node T_512 = bits(T_447, 31, 31) - node T_514 = bits(T_447, 30, 30) - node T_516 = bits(T_447, 29, 29) - node T_518 = bits(T_447, 28, 28) - node T_520 = bits(T_447, 27, 27) - node T_522 = bits(T_447, 26, 26) - node T_524 = bits(T_447, 25, 25) - node T_526 = bits(T_447, 24, 24) - node T_528 = bits(T_447, 23, 23) - node T_530 = bits(T_447, 22, 22) - node T_532 = bits(T_447, 21, 21) - node T_534 = bits(T_447, 20, 20) - node T_536 = bits(T_447, 19, 19) - node T_538 = bits(T_447, 18, 18) - node T_540 = bits(T_447, 17, 17) - node T_542 = bits(T_447, 16, 16) - node T_544 = bits(T_447, 15, 15) - node T_546 = bits(T_447, 14, 14) - node T_548 = bits(T_447, 13, 13) - node T_550 = bits(T_447, 12, 12) - node T_552 = bits(T_447, 11, 11) - node T_554 = bits(T_447, 10, 10) - node T_556 = bits(T_447, 9, 9) - node T_558 = bits(T_447, 8, 8) - node T_560 = bits(T_447, 7, 7) - node T_562 = bits(T_447, 6, 6) - node T_564 = bits(T_447, 5, 5) - node T_566 = bits(T_447, 4, 4) - node T_568 = bits(T_447, 3, 3) - node T_570 = bits(T_447, 2, 2) - node T_572 = bits(T_447, 1, 1) - node T_573 = shl(T_572, 0) - node T_574 = mux(T_570, UInt<2>("h02"), T_573) - node T_575 = mux(T_568, UInt<2>("h03"), T_574) - node T_576 = mux(T_566, UInt<3>("h04"), T_575) - node T_577 = mux(T_564, UInt<3>("h05"), T_576) - node T_578 = mux(T_562, UInt<3>("h06"), T_577) - node T_579 = mux(T_560, UInt<3>("h07"), T_578) - node T_580 = mux(T_558, UInt<4>("h08"), T_579) - node T_581 = mux(T_556, UInt<4>("h09"), T_580) - node T_582 = mux(T_554, UInt<4>("h0a"), T_581) - node T_583 = mux(T_552, UInt<4>("h0b"), T_582) - node T_584 = mux(T_550, UInt<4>("h0c"), T_583) - node T_585 = mux(T_548, UInt<4>("h0d"), T_584) - node T_586 = mux(T_546, UInt<4>("h0e"), T_585) - node T_587 = mux(T_544, UInt<4>("h0f"), T_586) - node T_588 = mux(T_542, UInt<5>("h010"), T_587) - node T_589 = mux(T_540, UInt<5>("h011"), T_588) - node T_590 = mux(T_538, UInt<5>("h012"), T_589) - node T_591 = mux(T_536, UInt<5>("h013"), T_590) - node T_592 = mux(T_534, UInt<5>("h014"), T_591) - node T_593 = mux(T_532, UInt<5>("h015"), T_592) - node T_594 = mux(T_530, UInt<5>("h016"), T_593) - node T_595 = mux(T_528, UInt<5>("h017"), T_594) - node T_596 = mux(T_526, UInt<5>("h018"), T_595) - node T_597 = mux(T_524, UInt<5>("h019"), T_596) - node T_598 = mux(T_522, UInt<5>("h01a"), T_597) - node T_599 = mux(T_520, UInt<5>("h01b"), T_598) - node T_600 = mux(T_518, UInt<5>("h01c"), T_599) - node T_601 = mux(T_516, UInt<5>("h01d"), T_600) - node T_602 = mux(T_514, UInt<5>("h01e"), T_601) - node T_603 = mux(T_512, UInt<5>("h01f"), T_602) - node T_604 = mux(T_510, UInt<6>("h020"), T_603) - node T_605 = mux(T_508, UInt<6>("h021"), T_604) - node T_606 = mux(T_506, UInt<6>("h022"), T_605) - node T_607 = mux(T_504, UInt<6>("h023"), T_606) - node T_608 = mux(T_502, UInt<6>("h024"), T_607) - node T_609 = mux(T_500, UInt<6>("h025"), T_608) - node T_610 = mux(T_498, UInt<6>("h026"), T_609) - node T_611 = mux(T_496, UInt<6>("h027"), T_610) - node T_612 = mux(T_494, UInt<6>("h028"), T_611) - node T_613 = mux(T_492, UInt<6>("h029"), T_612) - node T_614 = mux(T_490, UInt<6>("h02a"), T_613) - node T_615 = mux(T_488, UInt<6>("h02b"), T_614) - node T_616 = mux(T_486, UInt<6>("h02c"), T_615) - node T_617 = mux(T_484, UInt<6>("h02d"), T_616) - node T_618 = mux(T_482, UInt<6>("h02e"), T_617) - node T_619 = mux(T_480, UInt<6>("h02f"), T_618) - node T_620 = mux(T_478, UInt<6>("h030"), T_619) - node T_621 = mux(T_476, UInt<6>("h031"), T_620) - node T_622 = mux(T_474, UInt<6>("h032"), T_621) - node T_623 = mux(T_472, UInt<6>("h033"), T_622) - node T_624 = mux(T_470, UInt<6>("h034"), T_623) - node T_625 = mux(T_468, UInt<6>("h035"), T_624) - node T_626 = mux(T_466, UInt<6>("h036"), T_625) - node T_627 = mux(T_464, UInt<6>("h037"), T_626) - node T_628 = mux(T_462, UInt<6>("h038"), T_627) - node T_629 = mux(T_460, UInt<6>("h039"), T_628) - node T_630 = mux(T_458, UInt<6>("h03a"), T_629) - node T_631 = mux(T_456, UInt<6>("h03b"), T_630) - node T_632 = mux(T_454, UInt<6>("h03c"), T_631) - node T_633 = mux(T_452, UInt<6>("h03d"), T_632) - node T_634 = mux(T_450, UInt<6>("h03e"), T_633) - node T_635 = mux(T_448, UInt<6>("h03f"), T_634) - node T_637 = add(UInt<6>("h03f"), T_446) - node T_638 = tail(T_637, 1) - node T_639 = sub(T_638, T_635) - node T_640 = tail(T_639, 1) - node T_641 = gt(T_446, T_635) - node T_643 = eq(count, UInt<1>("h00")) - node T_644 = and(T_643, less) - node T_646 = gt(T_640, UInt<1>("h00")) - node T_647 = or(T_646, T_641) - node T_648 = and(T_644, T_647) - node T_650 = and(UInt<1>("h01"), T_648) - when T_650 : - node T_652 = bits(T_640, 5, 0) - node T_653 = mux(T_641, UInt<6>("h03f"), T_652) - node T_654 = bits(remainder, 63, 0) - node T_655 = dshl(T_654, T_653) - remainder <= T_655 - count <= T_653 - skip - node T_657 = eq(count, UInt<1>("h00")) - node T_659 = eq(less, UInt<1>("h00")) - node T_660 = and(T_657, T_659) - node T_662 = eq(isHi, UInt<1>("h00")) - node T_663 = and(T_660, T_662) - when T_663 : - neg_out <= UInt<1>("h00") - skip - skip - node T_665 = and(io.resp.ready, io.resp.valid) - node T_666 = or(T_665, io.kill) - when T_666 : - state <= UInt<1>("h00") - skip - node T_667 = and(io.req.ready, io.req.valid) - when T_667 : - node T_669 = eq(cmdMul, UInt<1>("h00")) - node T_670 = and(rhs_sign, T_669) - node T_671 = or(lhs_sign, T_670) - node T_672 = mux(T_671, UInt<1>("h01"), UInt<2>("h02")) - state <= T_672 - isMul <= cmdMul - isHi <= cmdHi - count <= UInt<1>("h00") - node T_675 = eq(cmdMul, UInt<1>("h00")) - node T_676 = neq(lhs_sign, rhs_sign) - node T_677 = mux(cmdHi, lhs_sign, T_676) - node T_678 = and(T_675, T_677) - neg_out <= T_678 - node T_679 = cat(rhs_sign, rhs_in) - divisor <= T_679 - remainder <= lhs_in - req <- io.req.bits - skip - io.resp.bits <- req - node T_682 = and(req.dw, UInt<1>("h01")) - node T_683 = eq(UInt<1>("h00"), T_682) - node T_684 = bits(remainder, 31, 31) - node T_686 = sub(UInt<32>("h00"), T_684) - node T_687 = tail(T_686, 1) - node T_688 = bits(remainder, 31, 0) - node T_689 = cat(T_687, T_688) - node T_690 = bits(remainder, 63, 0) - node T_691 = mux(T_683, T_689, T_690) - io.resp.bits.data <= T_691 - node T_692 = eq(state, UInt<3>("h05")) - io.resp.valid <= T_692 - node T_693 = eq(state, UInt<1>("h00")) - io.req.ready <= T_693 + io is invalid + inst sink_valid_sync_0 of AsyncResetRegVec_26 @[AsyncQueue.scala 18:14] + sink_valid_sync_0.io is invalid + sink_valid_sync_0.clock <= clock + sink_valid_sync_0.reset <= reset + inst sink_valid_sync_1 of AsyncResetRegVec_27 @[AsyncQueue.scala 18:14] + sink_valid_sync_1.io is invalid + sink_valid_sync_1.clock <= clock + sink_valid_sync_1.reset <= reset + inst sink_valid_sync_2 of AsyncResetRegVec_28 @[AsyncQueue.scala 18:14] + sink_valid_sync_2.io is invalid + sink_valid_sync_2.clock <= clock + sink_valid_sync_2.reset <= reset + sink_valid_sync_2.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + sink_valid_sync_0.io.d <= sink_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_1.io.d <= sink_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_9 = bits(sink_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_9 @[AsyncQueue.scala 35:10] - module Rocket : - input clk : Clock + module AsyncQueueSource : + input clock : Clock input reset : UInt<1> - output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}} - - io is invalid - reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk - reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk - reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk - reg ex_reg_xcpt_interrupt : UInt<1>, clk - reg ex_reg_valid : UInt<1>, clk - reg ex_reg_btb_hit : UInt<1>, clk - reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg ex_reg_xcpt : UInt<1>, clk - reg ex_reg_flush_pipe : UInt<1>, clk - reg ex_reg_load_use : UInt<1>, clk - reg ex_reg_cause : UInt, clk - reg ex_reg_pc : UInt, clk - reg ex_reg_inst : UInt, clk - reg mem_reg_xcpt_interrupt : UInt<1>, clk - reg mem_reg_valid : UInt<1>, clk - reg mem_reg_btb_hit : UInt<1>, clk - reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg mem_reg_xcpt : UInt<1>, clk - reg mem_reg_replay : UInt<1>, clk - reg mem_reg_flush_pipe : UInt<1>, clk - reg mem_reg_cause : UInt, clk - reg mem_reg_slow_bypass : UInt<1>, clk - reg mem_reg_pc : UInt, clk - reg mem_reg_inst : UInt, clk - reg mem_reg_wdata : UInt, clk - reg mem_reg_rs2 : UInt, clk - wire take_pc_mem : UInt<1> - take_pc_mem is invalid - reg wb_reg_valid : UInt<1>, clk - reg wb_reg_xcpt : UInt<1>, clk - reg wb_reg_replay : UInt<1>, clk - reg wb_reg_cause : UInt, clk - reg wb_reg_rocc_pending : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg wb_reg_pc : UInt, clk - reg wb_reg_inst : UInt, clk - reg wb_reg_wdata : UInt, clk - reg wb_reg_rs2 : UInt, clk - wire take_pc_wb : UInt<1> - take_pc_wb is invalid - node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) - wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} - id_ctrl is invalid - node T_6071 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6073 = eq(T_6071, UInt<32>("h03")) - node T_6075 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f")) - node T_6077 = eq(T_6075, UInt<32>("h03")) - node T_6079 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f")) - node T_6081 = eq(T_6079, UInt<32>("h0f")) - node T_6083 = and(io.imem.resp.bits.data[0], UInt<32>("h07077")) - node T_6085 = eq(T_6083, UInt<32>("h013")) - node T_6087 = and(io.imem.resp.bits.data[0], UInt<32>("h05f")) - node T_6089 = eq(T_6087, UInt<32>("h017")) - node T_6091 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f")) - node T_6093 = eq(T_6091, UInt<32>("h033")) - node T_6095 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_6097 = eq(T_6095, UInt<32>("h033")) - node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073")) - node T_6101 = eq(T_6099, UInt<32>("h043")) - node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f")) - node T_6105 = eq(T_6103, UInt<32>("h053")) - node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b")) - node T_6109 = eq(T_6107, UInt<32>("h063")) - node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h07f")) - node T_6113 = eq(T_6111, UInt<32>("h06f")) - node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff")) - node T_6117 = eq(T_6115, UInt<32>("h073")) - node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f")) - node T_6121 = eq(T_6119, UInt<32>("h01013")) - node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f")) - node T_6125 = eq(T_6123, UInt<32>("h0101b")) - node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b")) - node T_6129 = eq(T_6127, UInt<32>("h02003")) - node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6133 = eq(T_6131, UInt<32>("h02013")) - node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f")) - node T_6137 = eq(T_6135, UInt<32>("h0202f")) - node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6141 = eq(T_6139, UInt<32>("h02073")) - node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f")) - node T_6145 = eq(T_6143, UInt<32>("h05013")) - node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f")) - node T_6149 = eq(T_6147, UInt<32>("h0501b")) - node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_6153 = eq(T_6151, UInt<32>("h05033")) - node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077")) - node T_6157 = eq(T_6155, UInt<32>("h02004033")) - node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f")) - node T_6161 = eq(T_6159, UInt<32>("h0800202f")) - node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) - node T_6165 = eq(T_6163, UInt<32>("h010000073")) - node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) - node T_6169 = eq(T_6167, UInt<32>("h01000202f")) - node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff")) - node T_6173 = eq(T_6171, UInt<32>("h010100073")) - node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f")) - node T_6177 = eq(T_6175, UInt<32>("h020000053")) - node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f")) - node T_6181 = eq(T_6179, UInt<32>("h020000053")) - node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f")) - node T_6185 = eq(T_6183, UInt<32>("h020000053")) - node T_6187 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073")) - node T_6189 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_6191 = eq(T_6189, UInt<32>("h040100053")) - node T_6193 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_6195 = eq(T_6193, UInt<32>("h042000053")) - node T_6197 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) - node T_6199 = eq(T_6197, UInt<32>("h058000053")) - node T_6201 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f")) - node T_6203 = eq(T_6201, UInt<32>("h0c0000053")) - node T_6205 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) - node T_6207 = eq(T_6205, UInt<32>("h0e0000053")) - node T_6209 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f")) - node T_6211 = eq(T_6209, UInt<32>("h0e0000053")) - node T_6213 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f")) - node T_6215 = eq(T_6213, UInt<32>("h023")) - node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f")) - node T_6219 = eq(T_6217, UInt<32>("h01063")) - node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f")) - node T_6223 = eq(T_6221, UInt<32>("h04063")) - node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077")) - node T_6227 = eq(T_6225, UInt<32>("h033")) - node T_6229 = or(UInt<1>("h00"), T_6073) - node T_6230 = or(T_6229, T_6077) - node T_6231 = or(T_6230, T_6081) - node T_6232 = or(T_6231, T_6085) - node T_6233 = or(T_6232, T_6089) - node T_6234 = or(T_6233, T_6093) - node T_6235 = or(T_6234, T_6097) - node T_6236 = or(T_6235, T_6101) - node T_6237 = or(T_6236, T_6105) - node T_6238 = or(T_6237, T_6109) - node T_6239 = or(T_6238, T_6113) - node T_6240 = or(T_6239, T_6117) - node T_6241 = or(T_6240, T_6121) - node T_6242 = or(T_6241, T_6125) - node T_6243 = or(T_6242, T_6129) - node T_6244 = or(T_6243, T_6133) - node T_6245 = or(T_6244, T_6137) - node T_6246 = or(T_6245, T_6141) - node T_6247 = or(T_6246, T_6145) - node T_6248 = or(T_6247, T_6149) - node T_6249 = or(T_6248, T_6153) - node T_6250 = or(T_6249, T_6157) - node T_6251 = or(T_6250, T_6161) - node T_6252 = or(T_6251, T_6165) - node T_6253 = or(T_6252, T_6169) - node T_6254 = or(T_6253, T_6173) - node T_6255 = or(T_6254, T_6177) - node T_6256 = or(T_6255, T_6181) - node T_6257 = or(T_6256, T_6185) - node T_6258 = or(T_6257, T_6187) - node T_6259 = or(T_6258, T_6191) - node T_6260 = or(T_6259, T_6195) - node T_6261 = or(T_6260, T_6199) - node T_6262 = or(T_6261, T_6203) - node T_6263 = or(T_6262, T_6207) - node T_6264 = or(T_6263, T_6211) - node T_6265 = or(T_6264, T_6215) - node T_6266 = or(T_6265, T_6219) - node T_6267 = or(T_6266, T_6223) - node T_6268 = or(T_6267, T_6227) - node T_6270 = and(io.imem.resp.bits.data[0], UInt<32>("h05c")) - node T_6272 = eq(T_6270, UInt<32>("h04")) - node T_6274 = and(io.imem.resp.bits.data[0], UInt<32>("h060")) - node T_6276 = eq(T_6274, UInt<32>("h040")) - node T_6278 = or(UInt<1>("h00"), T_6272) - node T_6279 = or(T_6278, T_6276) - node T_6282 = and(io.imem.resp.bits.data[0], UInt<32>("h074")) - node T_6284 = eq(T_6282, UInt<32>("h060")) - node T_6286 = or(UInt<1>("h00"), T_6284) - node T_6288 = and(io.imem.resp.bits.data[0], UInt<32>("h068")) - node T_6290 = eq(T_6288, UInt<32>("h068")) - node T_6292 = or(UInt<1>("h00"), T_6290) - node T_6294 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c")) - node T_6296 = eq(T_6294, UInt<32>("h024")) - node T_6298 = or(UInt<1>("h00"), T_6296) - node T_6300 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) - node T_6302 = eq(T_6300, UInt<32>("h020")) - node T_6304 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) - node T_6306 = eq(T_6304, UInt<32>("h020")) - node T_6308 = and(io.imem.resp.bits.data[0], UInt<32>("h02048")) - node T_6310 = eq(T_6308, UInt<32>("h02008")) - node T_6312 = or(UInt<1>("h00"), T_6302) - node T_6313 = or(T_6312, T_6306) - node T_6314 = or(T_6313, T_6310) - node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) - node T_6318 = eq(T_6316, UInt<32>("h00")) - node T_6320 = and(io.imem.resp.bits.data[0], UInt<32>("h04024")) - node T_6322 = eq(T_6320, UInt<32>("h020")) - node T_6324 = and(io.imem.resp.bits.data[0], UInt<32>("h038")) - node T_6326 = eq(T_6324, UInt<32>("h020")) - node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h02050")) - node T_6330 = eq(T_6328, UInt<32>("h02000")) - node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034")) - node T_6334 = eq(T_6332, UInt<32>("h090000010")) - node T_6336 = or(UInt<1>("h00"), T_6318) - node T_6337 = or(T_6336, T_6322) - node T_6338 = or(T_6337, T_6326) - node T_6339 = or(T_6338, T_6330) - node T_6340 = or(T_6339, T_6334) - node T_6342 = and(io.imem.resp.bits.data[0], UInt<32>("h058")) - node T_6344 = eq(T_6342, UInt<32>("h00")) - node T_6346 = and(io.imem.resp.bits.data[0], UInt<32>("h020")) - node T_6348 = eq(T_6346, UInt<32>("h00")) - node T_6350 = and(io.imem.resp.bits.data[0], UInt<32>("h0c")) - node T_6352 = eq(T_6350, UInt<32>("h04")) - node T_6354 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) - node T_6356 = eq(T_6354, UInt<32>("h048")) - node T_6358 = and(io.imem.resp.bits.data[0], UInt<32>("h04050")) - node T_6360 = eq(T_6358, UInt<32>("h04050")) - node T_6362 = or(UInt<1>("h00"), T_6344) - node T_6363 = or(T_6362, T_6348) - node T_6364 = or(T_6363, T_6352) - node T_6365 = or(T_6364, T_6356) - node T_6366 = or(T_6365, T_6360) - node T_6368 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) - node T_6370 = eq(T_6368, UInt<32>("h00")) - node T_6372 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) - node T_6374 = eq(T_6372, UInt<32>("h00")) - node T_6376 = and(io.imem.resp.bits.data[0], UInt<32>("h04008")) - node T_6378 = eq(T_6376, UInt<32>("h04000")) - node T_6380 = or(UInt<1>("h00"), T_6370) - node T_6381 = or(T_6380, T_6318) - node T_6382 = or(T_6381, T_6374) - node T_6383 = or(T_6382, T_6378) - node T_6384 = cat(T_6383, T_6366) - node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h04004")) - node T_6388 = eq(T_6386, UInt<32>("h00")) - node T_6390 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) - node T_6392 = eq(T_6390, UInt<32>("h00")) - node T_6394 = and(io.imem.resp.bits.data[0], UInt<32>("h024")) - node T_6396 = eq(T_6394, UInt<32>("h00")) - node T_6398 = or(UInt<1>("h00"), T_6388) - node T_6399 = or(T_6398, T_6392) - node T_6400 = or(T_6399, T_6318) - node T_6401 = or(T_6400, T_6396) - node T_6402 = or(T_6401, T_6374) - node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) - node T_6406 = eq(T_6404, UInt<32>("h014")) - node T_6408 = or(UInt<1>("h00"), T_6406) - node T_6409 = or(T_6408, T_6356) - node T_6410 = cat(T_6409, T_6402) - node T_6412 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) - node T_6414 = eq(T_6412, UInt<32>("h08")) - node T_6416 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) - node T_6418 = eq(T_6416, UInt<32>("h040")) - node T_6420 = or(UInt<1>("h00"), T_6414) - node T_6421 = or(T_6420, T_6418) - node T_6423 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) - node T_6425 = eq(T_6423, UInt<32>("h014")) - node T_6427 = or(UInt<1>("h00"), T_6414) - node T_6428 = or(T_6427, T_6425) - node T_6430 = and(io.imem.resp.bits.data[0], UInt<32>("h030")) - node T_6432 = eq(T_6430, UInt<32>("h00")) - node T_6434 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c")) - node T_6436 = eq(T_6434, UInt<32>("h04")) - node T_6438 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) - node T_6440 = eq(T_6438, UInt<32>("h010")) - node T_6442 = or(UInt<1>("h00"), T_6432) - node T_6443 = or(T_6442, T_6436) - node T_6444 = or(T_6443, T_6440) - node T_6445 = cat(T_6428, T_6421) - node T_6446 = cat(T_6444, T_6445) - node T_6448 = and(io.imem.resp.bits.data[0], UInt<32>("h010")) - node T_6450 = eq(T_6448, UInt<32>("h00")) - node T_6452 = and(io.imem.resp.bits.data[0], UInt<32>("h08")) - node T_6454 = eq(T_6452, UInt<32>("h00")) - node T_6456 = or(UInt<1>("h00"), T_6450) - node T_6457 = or(T_6456, T_6454) - node T_6459 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) - node T_6461 = eq(T_6459, UInt<32>("h01010")) - node T_6463 = and(io.imem.resp.bits.data[0], UInt<32>("h01058")) - node T_6465 = eq(T_6463, UInt<32>("h01040")) - node T_6467 = and(io.imem.resp.bits.data[0], UInt<32>("h07044")) - node T_6469 = eq(T_6467, UInt<32>("h07000")) - node T_6471 = or(UInt<1>("h00"), T_6461) - node T_6472 = or(T_6471, T_6465) - node T_6473 = or(T_6472, T_6469) - node T_6475 = and(io.imem.resp.bits.data[0], UInt<32>("h04054")) - node T_6477 = eq(T_6475, UInt<32>("h040")) - node T_6479 = and(io.imem.resp.bits.data[0], UInt<32>("h02058")) - node T_6481 = eq(T_6479, UInt<32>("h02040")) - node T_6483 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) - node T_6485 = eq(T_6483, UInt<32>("h03010")) - node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) - node T_6489 = eq(T_6487, UInt<32>("h06010")) - node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034")) - node T_6493 = eq(T_6491, UInt<32>("h040000030")) - node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054")) - node T_6497 = eq(T_6495, UInt<32>("h040001010")) - node T_6499 = or(UInt<1>("h00"), T_6477) - node T_6500 = or(T_6499, T_6481) - node T_6501 = or(T_6500, T_6485) - node T_6502 = or(T_6501, T_6489) - node T_6503 = or(T_6502, T_6493) - node T_6504 = or(T_6503, T_6497) - node T_6506 = and(io.imem.resp.bits.data[0], UInt<32>("h02054")) - node T_6508 = eq(T_6506, UInt<32>("h02010")) - node T_6510 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054")) - node T_6512 = eq(T_6510, UInt<32>("h04010")) - node T_6514 = and(io.imem.resp.bits.data[0], UInt<32>("h05054")) - node T_6516 = eq(T_6514, UInt<32>("h04010")) - node T_6518 = and(io.imem.resp.bits.data[0], UInt<32>("h04058")) - node T_6520 = eq(T_6518, UInt<32>("h04040")) - node T_6522 = or(UInt<1>("h00"), T_6508) - node T_6523 = or(T_6522, T_6512) - node T_6524 = or(T_6523, T_6516) - node T_6525 = or(T_6524, T_6520) - node T_6527 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) - node T_6529 = eq(T_6527, UInt<32>("h02010")) - node T_6531 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054")) - node T_6533 = eq(T_6531, UInt<32>("h040001010")) - node T_6535 = or(UInt<1>("h00"), T_6529) - node T_6536 = or(T_6535, T_6520) - node T_6537 = or(T_6536, T_6493) - node T_6538 = or(T_6537, T_6533) - node T_6539 = cat(T_6504, T_6473) - node T_6540 = cat(T_6525, T_6539) - node T_6541 = cat(T_6538, T_6540) - node T_6543 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f")) - node T_6545 = eq(T_6543, UInt<32>("h03")) - node T_6547 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f")) - node T_6549 = eq(T_6547, UInt<32>("h03")) - node T_6551 = or(UInt<1>("h00"), T_6545) - node T_6552 = or(T_6551, T_6073) - node T_6553 = or(T_6552, T_6549) - node T_6554 = or(T_6553, T_6129) - node T_6555 = or(T_6554, T_6137) - node T_6556 = or(T_6555, T_6161) - node T_6557 = or(T_6556, T_6169) - node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) - node T_6561 = eq(T_6559, UInt<32>("h020")) - node T_6563 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020")) - node T_6565 = eq(T_6563, UInt<32>("h018000020")) - node T_6567 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020")) - node T_6569 = eq(T_6567, UInt<32>("h020000020")) - node T_6571 = or(UInt<1>("h00"), T_6561) - node T_6572 = or(T_6571, T_6565) - node T_6573 = or(T_6572, T_6569) - node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008")) - node T_6577 = eq(T_6575, UInt<32>("h010000008")) - node T_6579 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008")) - node T_6581 = eq(T_6579, UInt<32>("h040000008")) - node T_6583 = or(UInt<1>("h00"), T_6577) - node T_6584 = or(T_6583, T_6581) - node T_6586 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008")) - node T_6588 = eq(T_6586, UInt<32>("h08000008")) - node T_6590 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008")) - node T_6592 = eq(T_6590, UInt<32>("h080000008")) - node T_6594 = or(UInt<1>("h00"), T_6588) - node T_6595 = or(T_6594, T_6577) - node T_6596 = or(T_6595, T_6592) - node T_6598 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008")) - node T_6600 = eq(T_6598, UInt<32>("h08")) - node T_6602 = or(UInt<1>("h00"), T_6600) - node T_6604 = cat(T_6584, T_6573) - node T_6605 = cat(T_6596, T_6604) - node T_6606 = cat(T_6602, T_6605) - node T_6607 = cat(UInt<1>("h00"), T_6606) - node T_6609 = and(io.imem.resp.bits.data[0], UInt<32>("h01000")) - node T_6611 = eq(T_6609, UInt<32>("h01000")) - node T_6613 = or(UInt<1>("h00"), T_6611) - node T_6615 = and(io.imem.resp.bits.data[0], UInt<32>("h02000")) - node T_6617 = eq(T_6615, UInt<32>("h02000")) - node T_6619 = or(UInt<1>("h00"), T_6617) - node T_6621 = and(io.imem.resp.bits.data[0], UInt<32>("h04000")) - node T_6623 = eq(T_6621, UInt<32>("h04000")) - node T_6625 = or(UInt<1>("h00"), T_6623) - node T_6626 = cat(T_6619, T_6613) - node T_6627 = cat(T_6625, T_6626) - node T_6629 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060")) - node T_6631 = eq(T_6629, UInt<32>("h040")) - node T_6633 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_6635 = eq(T_6633, UInt<32>("h040")) - node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h070")) - node T_6639 = eq(T_6637, UInt<32>("h040")) - node T_6641 = or(UInt<1>("h00"), T_6631) - node T_6642 = or(T_6641, T_6635) - node T_6643 = or(T_6642, T_6639) - node T_6645 = and(io.imem.resp.bits.data[0], UInt<32>("h07c")) - node T_6647 = eq(T_6645, UInt<32>("h024")) - node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060")) - node T_6651 = eq(T_6649, UInt<32>("h040")) - node T_6653 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060")) - node T_6655 = eq(T_6653, UInt<32>("h010000040")) - node T_6657 = or(UInt<1>("h00"), T_6647) - node T_6658 = or(T_6657, T_6651) - node T_6659 = or(T_6658, T_6639) - node T_6660 = or(T_6659, T_6655) - node T_6662 = or(UInt<1>("h00"), T_6639) - node T_6664 = and(io.imem.resp.bits.data[0], UInt<32>("h03c")) - node T_6666 = eq(T_6664, UInt<32>("h04")) - node T_6668 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_6670 = eq(T_6668, UInt<32>("h010000040")) - node T_6672 = or(UInt<1>("h00"), T_6666) - node T_6673 = or(T_6672, T_6631) - node T_6674 = or(T_6673, T_6639) - node T_6675 = or(T_6674, T_6670) - node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074")) - node T_6679 = eq(T_6677, UInt<32>("h02000030")) - node T_6681 = or(UInt<1>("h00"), T_6679) - node T_6683 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) - node T_6685 = eq(T_6683, UInt<32>("h00")) - node T_6687 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) - node T_6689 = eq(T_6687, UInt<32>("h010")) - node T_6691 = and(io.imem.resp.bits.data[0], UInt<32>("h02024")) - node T_6693 = eq(T_6691, UInt<32>("h024")) - node T_6695 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) - node T_6697 = eq(T_6695, UInt<32>("h028")) - node T_6699 = and(io.imem.resp.bits.data[0], UInt<32>("h01030")) - node T_6701 = eq(T_6699, UInt<32>("h01030")) - node T_6703 = and(io.imem.resp.bits.data[0], UInt<32>("h02030")) - node T_6705 = eq(T_6703, UInt<32>("h02030")) - node T_6707 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010")) - node T_6709 = eq(T_6707, UInt<32>("h080000010")) - node T_6711 = or(UInt<1>("h00"), T_6685) - node T_6712 = or(T_6711, T_6689) - node T_6713 = or(T_6712, T_6693) - node T_6714 = or(T_6713, T_6697) - node T_6715 = or(T_6714, T_6701) - node T_6716 = or(T_6715, T_6705) - node T_6717 = or(T_6716, T_6709) - node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h01070")) - node T_6721 = eq(T_6719, UInt<32>("h01070")) - node T_6723 = or(UInt<1>("h00"), T_6721) - node T_6725 = and(io.imem.resp.bits.data[0], UInt<32>("h02070")) - node T_6727 = eq(T_6725, UInt<32>("h02070")) - node T_6729 = or(UInt<1>("h00"), T_6727) - node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h03070")) - node T_6733 = eq(T_6731, UInt<32>("h070")) - node T_6735 = or(UInt<1>("h00"), T_6733) - node T_6736 = cat(T_6729, T_6723) - node T_6737 = cat(T_6735, T_6736) - node T_6739 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) - node T_6741 = eq(T_6739, UInt<32>("h01008")) - node T_6743 = or(UInt<1>("h00"), T_6741) - node T_6745 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) - node T_6747 = eq(T_6745, UInt<32>("h08")) - node T_6749 = or(UInt<1>("h00"), T_6747) - node T_6751 = and(io.imem.resp.bits.data[0], UInt<32>("h06048")) - node T_6753 = eq(T_6751, UInt<32>("h02008")) - node T_6755 = or(UInt<1>("h00"), T_6753) - id_ctrl.legal <= T_6268 - id_ctrl.fp <= T_6279 - id_ctrl.rocc <= UInt<1>("h00") - id_ctrl.branch <= T_6286 - id_ctrl.jal <= T_6292 - id_ctrl.jalr <= T_6298 - id_ctrl.rxs2 <= T_6314 - id_ctrl.rxs1 <= T_6340 - id_ctrl.sel_alu2 <= T_6384 - id_ctrl.sel_alu1 <= T_6410 - id_ctrl.sel_imm <= T_6446 - id_ctrl.alu_dw <= T_6457 - id_ctrl.alu_fn <= T_6541 - id_ctrl.mem <= T_6557 - id_ctrl.mem_cmd <= T_6607 - id_ctrl.mem_type <= T_6627 - id_ctrl.rfs1 <= T_6643 - id_ctrl.rfs2 <= T_6660 - id_ctrl.rfs3 <= T_6662 - id_ctrl.wfd <= T_6675 - id_ctrl.div <= T_6681 - id_ctrl.wxd <= T_6717 - id_ctrl.csr <= T_6737 - id_ctrl.fence_i <= T_6743 - id_ctrl.fence <= T_6749 - id_ctrl.amo <= T_6755 - node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27) - node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20) - node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15) - node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7) - wire id_load_use : UInt<1> - id_load_use is invalid - reg id_reg_fence : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - cmem T_6766 : UInt<64>[31] - wire T_6768 : UInt - T_6768 is invalid - node T_6771 = eq(id_raddr1, UInt<1>("h00")) - node T_6772 = and(UInt<1>("h00"), T_6771) - node T_6774 = bits(id_raddr1, 4, 0) - node T_6775 = not(T_6774) - infer mport T_6776 = T_6766[T_6775], clk - node T_6777 = mux(T_6772, UInt<1>("h00"), T_6776) - T_6768 <= T_6777 - wire T_6779 : UInt - T_6779 is invalid - node T_6782 = eq(id_raddr2, UInt<1>("h00")) - node T_6783 = and(UInt<1>("h00"), T_6782) - node T_6785 = bits(id_raddr2, 4, 0) - node T_6786 = not(T_6785) - infer mport T_6787 = T_6766[T_6786], clk - node T_6788 = mux(T_6783, UInt<1>("h00"), T_6787) - T_6779 <= T_6788 - wire ctrl_killd : UInt<1> - ctrl_killd is invalid - inst csr of CSRFile - csr.io is invalid - csr.clk <= clk - csr.reset <= reset - node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) - node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) - node T_6794 = eq(id_ctrl.csr, UInt<3>("h02")) - node T_6795 = eq(id_ctrl.csr, UInt<3>("h03")) - node T_6796 = or(T_6794, T_6795) - node T_6798 = eq(id_raddr1, UInt<1>("h00")) - node id_csr_ren = and(T_6796, T_6798) - node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) - node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20) - node T_6803 = eq(id_csr_ren, UInt<1>("h00")) - node T_6804 = and(id_csr_en, T_6803) - node T_6863 = and(id_csr_addr, UInt<12>("h08c4")) - node T_6865 = eq(T_6863, UInt<12>("h040")) - node T_6867 = or(UInt<1>("h00"), T_6865) - node T_6868 = bits(T_6867, 0, 0) - node T_6870 = eq(T_6868, UInt<1>("h00")) - node T_6871 = and(T_6804, T_6870) - node id_csr_flush = or(id_system_insn, T_6871) - node T_6874 = eq(id_ctrl.legal, UInt<1>("h00")) - node T_6876 = neq(csr.io.status.fs, UInt<1>("h00")) - node T_6878 = eq(T_6876, UInt<1>("h00")) - node T_6879 = and(id_ctrl.fp, T_6878) - node T_6880 = or(T_6874, T_6879) - node T_6882 = neq(csr.io.status.xs, UInt<1>("h00")) - node T_6884 = eq(T_6882, UInt<1>("h00")) - node T_6885 = and(id_ctrl.rocc, T_6884) - node id_illegal_insn = or(T_6880, T_6885) - node id_amo_aq = bits(io.imem.resp.bits.data[0], 26, 26) - node id_amo_rl = bits(io.imem.resp.bits.data[0], 25, 25) - node T_6889 = and(id_ctrl.amo, id_amo_rl) - node id_fence_next = or(id_ctrl.fence, T_6889) - node T_6892 = eq(io.dmem.ordered, UInt<1>("h00")) - node id_mem_busy = or(T_6892, io.dmem.req.valid) - node T_6895 = and(ex_reg_valid, ex_ctrl.rocc) - node T_6896 = or(io.rocc.busy, T_6895) - node T_6897 = and(mem_reg_valid, mem_ctrl.rocc) - node T_6898 = or(T_6896, T_6897) - node T_6899 = and(wb_reg_valid, wb_ctrl.rocc) - node T_6900 = or(T_6898, T_6899) - node id_rocc_busy = and(UInt<1>("h00"), T_6900) - node T_6902 = and(id_reg_fence, id_mem_busy) - node T_6903 = or(id_fence_next, T_6902) - id_reg_fence <= T_6903 - node T_6904 = and(id_rocc_busy, id_ctrl.fence) - node T_6905 = and(id_ctrl.amo, id_amo_aq) - node T_6906 = or(T_6905, id_ctrl.fence_i) - node T_6907 = or(id_ctrl.mem, id_ctrl.rocc) - node T_6908 = and(id_reg_fence, T_6907) - node T_6909 = or(T_6906, T_6908) - node T_6910 = or(T_6909, id_csr_en) - node T_6911 = and(id_mem_busy, T_6910) - node id_do_fence = or(T_6904, T_6911) - node T_6915 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) - node id_xcpt = or(T_6915, id_illegal_insn) - node T_6917 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) - node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_6917) - node ex_waddr = bits(ex_reg_inst, 11, 7) - node mem_waddr = bits(mem_reg_inst, 11, 7) - node wb_waddr = bits(wb_reg_inst, 11, 7) - node T_6925 = and(ex_reg_valid, ex_ctrl.wxd) - node T_6926 = and(mem_reg_valid, mem_ctrl.wxd) - node T_6928 = eq(mem_ctrl.mem, UInt<1>("h00")) - node T_6929 = and(T_6926, T_6928) - node T_6930 = and(mem_reg_valid, mem_ctrl.wxd) - node T_6931 = eq(UInt<1>("h00"), id_raddr1) - node T_6932 = and(UInt<1>("h01"), T_6931) - node T_6933 = eq(ex_waddr, id_raddr1) - node T_6934 = and(T_6925, T_6933) - node T_6935 = eq(mem_waddr, id_raddr1) - node T_6936 = and(T_6929, T_6935) - node T_6937 = eq(mem_waddr, id_raddr1) - node T_6938 = and(T_6930, T_6937) - node T_6939 = eq(UInt<1>("h00"), id_raddr2) - node T_6940 = and(UInt<1>("h01"), T_6939) - node T_6941 = eq(ex_waddr, id_raddr2) - node T_6942 = and(T_6925, T_6941) - node T_6943 = eq(mem_waddr, id_raddr2) - node T_6944 = and(T_6929, T_6943) - node T_6945 = eq(mem_waddr, id_raddr2) - node T_6946 = and(T_6930, T_6945) - wire bypass_mux : UInt[4] - bypass_mux[0] <= UInt<1>("h00") - bypass_mux[1] <= mem_reg_wdata - bypass_mux[2] <= wb_reg_wdata - bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass - reg ex_reg_rs_bypass : UInt<1>[2], clk - reg ex_reg_rs_lsb : UInt[2], clk - reg ex_reg_rs_msb : UInt[2], clk - node T_6991 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) - node T_6992 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_6991) - node T_6994 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) - node T_6995 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_6994) - node T_6996 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_6998 = bits(ex_reg_inst, 31, 31) - node T_6999 = asSInt(T_6998) - node T_7000 = mux(T_6996, asSInt(UInt<1>("h00")), T_6999) - node T_7001 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7002 = bits(ex_reg_inst, 30, 20) - node T_7003 = asSInt(T_7002) - node T_7004 = mux(T_7001, T_7003, T_7000) - node T_7005 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7006 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_7007 = and(T_7005, T_7006) - node T_7008 = bits(ex_reg_inst, 19, 12) - node T_7009 = asSInt(T_7008) - node T_7010 = mux(T_7007, T_7000, T_7009) - node T_7011 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7012 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7013 = or(T_7011, T_7012) - node T_7015 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_7016 = bits(ex_reg_inst, 20, 20) - node T_7017 = asSInt(T_7016) - node T_7018 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_7019 = bits(ex_reg_inst, 7, 7) - node T_7020 = asSInt(T_7019) - node T_7021 = mux(T_7018, T_7020, T_7000) - node T_7022 = mux(T_7015, T_7017, T_7021) - node T_7023 = mux(T_7013, asSInt(UInt<1>("h00")), T_7022) - node T_7024 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7025 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7026 = or(T_7024, T_7025) - node T_7028 = bits(ex_reg_inst, 30, 25) - node T_7029 = mux(T_7026, UInt<1>("h00"), T_7028) - node T_7030 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7032 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_7033 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_7034 = or(T_7032, T_7033) - node T_7035 = bits(ex_reg_inst, 11, 8) - node T_7036 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7037 = bits(ex_reg_inst, 19, 16) - node T_7038 = bits(ex_reg_inst, 24, 21) - node T_7039 = mux(T_7036, T_7037, T_7038) - node T_7040 = mux(T_7034, T_7035, T_7039) - node T_7041 = mux(T_7030, UInt<1>("h00"), T_7040) - node T_7042 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_7043 = bits(ex_reg_inst, 7, 7) - node T_7044 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) - node T_7045 = bits(ex_reg_inst, 20, 20) - node T_7046 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7047 = bits(ex_reg_inst, 15, 15) - node T_7049 = shl(T_7047, 0) - node T_7050 = mux(T_7046, T_7049, UInt<1>("h00")) - node T_7051 = shl(T_7045, 0) - node T_7052 = mux(T_7044, T_7051, T_7050) - node T_7053 = shl(T_7043, 0) - node T_7054 = mux(T_7042, T_7053, T_7052) - node T_7055 = asUInt(T_7000) - node T_7056 = asUInt(T_7004) - node T_7057 = asUInt(T_7010) - node T_7058 = cat(T_7056, T_7057) - node T_7059 = cat(T_7055, T_7058) - node T_7060 = asUInt(T_7023) - node T_7061 = cat(T_7060, T_7029) - node T_7062 = cat(T_7041, T_7054) - node T_7063 = cat(T_7061, T_7062) - node T_7064 = cat(T_7059, T_7063) - node ex_imm = asSInt(T_7064) - node T_7067 = asSInt(T_6992) - node T_7068 = asSInt(ex_reg_pc) - node T_7069 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) - node T_7070 = mux(T_7069, T_7068, asSInt(UInt<1>("h00"))) - node T_7071 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) - node ex_op1 = mux(T_7071, T_7067, T_7070) - node T_7074 = asSInt(T_6995) - node T_7076 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) - node T_7077 = mux(T_7076, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) - node T_7078 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) - node T_7079 = mux(T_7078, ex_imm, T_7077) - node T_7080 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) - node ex_op2 = mux(T_7080, T_7074, T_7079) - inst alu of ALU - alu.io is invalid - alu.clk <= clk - alu.reset <= reset - alu.io.dw <= ex_ctrl.alu_dw - alu.io.fn <= ex_ctrl.alu_fn - node T_7083 = asUInt(ex_op2) - alu.io.in2 <= T_7083 - node T_7084 = asUInt(ex_op1) - alu.io.in1 <= T_7084 - inst div of MulDiv - div.io is invalid - div.clk <= clk - div.reset <= reset - node T_7086 = and(ex_reg_valid, ex_ctrl.div) - div.io.req.valid <= T_7086 - div.io.req.bits.dw <= ex_ctrl.alu_dw - div.io.req.bits.fn <= ex_ctrl.alu_fn - div.io.req.bits.in1 <= T_6992 - div.io.req.bits.in2 <= T_6995 - div.io.req.bits.tag <= ex_waddr - node T_7088 = eq(ctrl_killd, UInt<1>("h00")) - ex_reg_valid <= T_7088 - node T_7090 = eq(ctrl_killd, UInt<1>("h00")) - node T_7091 = and(T_7090, id_xcpt) - ex_reg_xcpt <= T_7091 - node T_7093 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7094 = and(csr.io.interrupt, T_7093) - node T_7095 = and(T_7094, io.imem.resp.valid) - ex_reg_xcpt_interrupt <= T_7095 - when id_xcpt : - ex_reg_cause <= id_cause - skip - node T_7097 = eq(ctrl_killd, UInt<1>("h00")) - when T_7097 : - ex_ctrl <- id_ctrl - ex_ctrl.csr <= id_csr - ex_reg_btb_hit <= io.imem.btb_resp.valid - when io.imem.btb_resp.valid : - ex_reg_btb_resp <- io.imem.btb_resp.bits - skip - node T_7098 = or(id_ctrl.fence_i, id_csr_flush) - ex_reg_flush_pipe <= T_7098 - ex_reg_load_use <= id_load_use - node T_7099 = or(T_6932, T_6934) - node T_7100 = or(T_7099, T_6936) - node T_7101 = or(T_7100, T_6938) - node T_7106 = mux(T_6936, UInt<2>("h02"), UInt<2>("h03")) - node T_7107 = mux(T_6934, UInt<1>("h01"), T_7106) - node T_7108 = mux(T_6932, UInt<1>("h00"), T_7107) - ex_reg_rs_bypass[0] <= T_7101 - ex_reg_rs_lsb[0] <= T_7108 - node T_7110 = eq(T_7101, UInt<1>("h00")) - node T_7111 = and(id_ctrl.rxs1, T_7110) - when T_7111 : - node T_7112 = bits(T_6768, 1, 0) - ex_reg_rs_lsb[0] <= T_7112 - node T_7113 = shr(T_6768, 2) - ex_reg_rs_msb[0] <= T_7113 - skip - node T_7114 = or(T_6940, T_6942) - node T_7115 = or(T_7114, T_6944) - node T_7116 = or(T_7115, T_6946) - node T_7121 = mux(T_6944, UInt<2>("h02"), UInt<2>("h03")) - node T_7122 = mux(T_6942, UInt<1>("h01"), T_7121) - node T_7123 = mux(T_6940, UInt<1>("h00"), T_7122) - ex_reg_rs_bypass[1] <= T_7116 - ex_reg_rs_lsb[1] <= T_7123 - node T_7125 = eq(T_7116, UInt<1>("h00")) - node T_7126 = and(id_ctrl.rxs2, T_7125) - when T_7126 : - node T_7127 = bits(T_6779, 1, 0) - ex_reg_rs_lsb[1] <= T_7127 - node T_7128 = shr(T_6779, 2) - ex_reg_rs_msb[1] <= T_7128 - skip - skip - node T_7130 = eq(ctrl_killd, UInt<1>("h00")) - node T_7131 = or(T_7130, csr.io.interrupt) - when T_7131 : - ex_reg_inst <= io.imem.resp.bits.data[0] - ex_reg_pc <= io.imem.resp.bits.pc - skip - node T_7133 = eq(io.dmem.resp.valid, UInt<1>("h00")) - node wb_dcache_miss = and(wb_ctrl.mem, T_7133) - node T_7136 = eq(io.dmem.req.ready, UInt<1>("h00")) - node T_7137 = and(ex_ctrl.mem, T_7136) - node T_7139 = eq(div.io.req.ready, UInt<1>("h00")) - node T_7140 = and(ex_ctrl.div, T_7139) - node replay_ex_structural = or(T_7137, T_7140) - node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) - node T_7143 = or(replay_ex_structural, replay_ex_load_use) - node replay_ex = and(ex_reg_valid, T_7143) - node T_7145 = or(take_pc_mem_wb, replay_ex) - node T_7147 = eq(ex_reg_valid, UInt<1>("h00")) - node ctrl_killx = or(T_7145, T_7147) - node T_7149 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) - wire T_7151 : UInt<3>[4] - T_7151[0] <= UInt<3>("h00") - T_7151[1] <= UInt<3>("h04") - T_7151[2] <= UInt<3>("h01") - T_7151[3] <= UInt<3>("h05") - node T_7157 = eq(T_7151[0], ex_ctrl.mem_type) - node T_7158 = eq(T_7151[1], ex_ctrl.mem_type) - node T_7159 = eq(T_7151[2], ex_ctrl.mem_type) - node T_7160 = eq(T_7151[3], ex_ctrl.mem_type) - node T_7162 = or(UInt<1>("h00"), T_7157) - node T_7163 = or(T_7162, T_7158) - node T_7164 = or(T_7163, T_7159) - node T_7165 = or(T_7164, T_7160) - node ex_slow_bypass = or(T_7149, T_7165) - node T_7167 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) - node T_7168 = and(ex_ctrl.fp, io.fpu.illegal_rm) - node ex_xcpt = or(T_7167, T_7168) - node ex_cause = mux(T_7167, ex_reg_cause, UInt<2>("h02")) - node mem_br_taken = bits(mem_reg_wdata, 0, 0) - node T_7173 = asSInt(mem_reg_pc) - node T_7174 = and(mem_ctrl.branch, mem_br_taken) - node T_7175 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7177 = bits(mem_reg_inst, 31, 31) - node T_7178 = asSInt(T_7177) - node T_7179 = mux(T_7175, asSInt(UInt<1>("h00")), T_7178) - node T_7180 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7181 = bits(mem_reg_inst, 30, 20) - node T_7182 = asSInt(T_7181) - node T_7183 = mux(T_7180, T_7182, T_7179) - node T_7184 = neq(UInt<3>("h01"), UInt<3>("h02")) - node T_7185 = neq(UInt<3>("h01"), UInt<3>("h03")) - node T_7186 = and(T_7184, T_7185) - node T_7187 = bits(mem_reg_inst, 19, 12) - node T_7188 = asSInt(T_7187) - node T_7189 = mux(T_7186, T_7179, T_7188) - node T_7190 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7191 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7192 = or(T_7190, T_7191) - node T_7194 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_7195 = bits(mem_reg_inst, 20, 20) - node T_7196 = asSInt(T_7195) - node T_7197 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_7198 = bits(mem_reg_inst, 7, 7) - node T_7199 = asSInt(T_7198) - node T_7200 = mux(T_7197, T_7199, T_7179) - node T_7201 = mux(T_7194, T_7196, T_7200) - node T_7202 = mux(T_7192, asSInt(UInt<1>("h00")), T_7201) - node T_7203 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7204 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7205 = or(T_7203, T_7204) - node T_7207 = bits(mem_reg_inst, 30, 25) - node T_7208 = mux(T_7205, UInt<1>("h00"), T_7207) - node T_7209 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7211 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_7212 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_7213 = or(T_7211, T_7212) - node T_7214 = bits(mem_reg_inst, 11, 8) - node T_7215 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7216 = bits(mem_reg_inst, 19, 16) - node T_7217 = bits(mem_reg_inst, 24, 21) - node T_7218 = mux(T_7215, T_7216, T_7217) - node T_7219 = mux(T_7213, T_7214, T_7218) - node T_7220 = mux(T_7209, UInt<1>("h00"), T_7219) - node T_7221 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_7222 = bits(mem_reg_inst, 7, 7) - node T_7223 = eq(UInt<3>("h01"), UInt<3>("h04")) - node T_7224 = bits(mem_reg_inst, 20, 20) - node T_7225 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7226 = bits(mem_reg_inst, 15, 15) - node T_7228 = shl(T_7226, 0) - node T_7229 = mux(T_7225, T_7228, UInt<1>("h00")) - node T_7230 = shl(T_7224, 0) - node T_7231 = mux(T_7223, T_7230, T_7229) - node T_7232 = shl(T_7222, 0) - node T_7233 = mux(T_7221, T_7232, T_7231) - node T_7234 = asUInt(T_7179) - node T_7235 = asUInt(T_7183) - node T_7236 = asUInt(T_7189) - node T_7237 = cat(T_7235, T_7236) - node T_7238 = cat(T_7234, T_7237) - node T_7239 = asUInt(T_7202) - node T_7240 = cat(T_7239, T_7208) - node T_7241 = cat(T_7220, T_7233) - node T_7242 = cat(T_7240, T_7241) - node T_7243 = cat(T_7238, T_7242) - node T_7244 = asSInt(T_7243) - node T_7245 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7247 = bits(mem_reg_inst, 31, 31) - node T_7248 = asSInt(T_7247) - node T_7249 = mux(T_7245, asSInt(UInt<1>("h00")), T_7248) - node T_7250 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7251 = bits(mem_reg_inst, 30, 20) - node T_7252 = asSInt(T_7251) - node T_7253 = mux(T_7250, T_7252, T_7249) - node T_7254 = neq(UInt<3>("h03"), UInt<3>("h02")) - node T_7255 = neq(UInt<3>("h03"), UInt<3>("h03")) - node T_7256 = and(T_7254, T_7255) - node T_7257 = bits(mem_reg_inst, 19, 12) - node T_7258 = asSInt(T_7257) - node T_7259 = mux(T_7256, T_7249, T_7258) - node T_7260 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7261 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7262 = or(T_7260, T_7261) - node T_7264 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_7265 = bits(mem_reg_inst, 20, 20) - node T_7266 = asSInt(T_7265) - node T_7267 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_7268 = bits(mem_reg_inst, 7, 7) - node T_7269 = asSInt(T_7268) - node T_7270 = mux(T_7267, T_7269, T_7249) - node T_7271 = mux(T_7264, T_7266, T_7270) - node T_7272 = mux(T_7262, asSInt(UInt<1>("h00")), T_7271) - node T_7273 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7274 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7275 = or(T_7273, T_7274) - node T_7277 = bits(mem_reg_inst, 30, 25) - node T_7278 = mux(T_7275, UInt<1>("h00"), T_7277) - node T_7279 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7281 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_7282 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_7283 = or(T_7281, T_7282) - node T_7284 = bits(mem_reg_inst, 11, 8) - node T_7285 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7286 = bits(mem_reg_inst, 19, 16) - node T_7287 = bits(mem_reg_inst, 24, 21) - node T_7288 = mux(T_7285, T_7286, T_7287) - node T_7289 = mux(T_7283, T_7284, T_7288) - node T_7290 = mux(T_7279, UInt<1>("h00"), T_7289) - node T_7291 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_7292 = bits(mem_reg_inst, 7, 7) - node T_7293 = eq(UInt<3>("h03"), UInt<3>("h04")) - node T_7294 = bits(mem_reg_inst, 20, 20) - node T_7295 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7296 = bits(mem_reg_inst, 15, 15) - node T_7298 = shl(T_7296, 0) - node T_7299 = mux(T_7295, T_7298, UInt<1>("h00")) - node T_7300 = shl(T_7294, 0) - node T_7301 = mux(T_7293, T_7300, T_7299) - node T_7302 = shl(T_7292, 0) - node T_7303 = mux(T_7291, T_7302, T_7301) - node T_7304 = asUInt(T_7249) - node T_7305 = asUInt(T_7253) - node T_7306 = asUInt(T_7259) - node T_7307 = cat(T_7305, T_7306) - node T_7308 = cat(T_7304, T_7307) - node T_7309 = asUInt(T_7272) - node T_7310 = cat(T_7309, T_7278) - node T_7311 = cat(T_7290, T_7303) - node T_7312 = cat(T_7310, T_7311) - node T_7313 = cat(T_7308, T_7312) - node T_7314 = asSInt(T_7313) - node T_7316 = mux(mem_ctrl.jal, T_7314, asSInt(UInt<4>("h04"))) - node T_7317 = mux(T_7174, T_7244, T_7316) - node T_7318 = add(T_7173, T_7317) - node T_7319 = tail(T_7318, 1) - node mem_br_target = asSInt(T_7319) - node T_7321 = asSInt(mem_reg_wdata) - node T_7322 = mux(mem_ctrl.jalr, mem_br_target, T_7321) - node mem_int_wdata = asUInt(T_7322) - node T_7324 = shr(mem_reg_wdata, 38) - node T_7325 = bits(mem_reg_wdata, 39, 38) - node T_7327 = eq(T_7324, UInt<1>("h00")) - node T_7329 = eq(T_7324, UInt<1>("h01")) - node T_7330 = or(T_7327, T_7329) - node T_7332 = neq(T_7325, UInt<1>("h00")) - node T_7333 = asSInt(T_7324) - node T_7335 = eq(T_7333, asSInt(UInt<1>("h01"))) - node T_7336 = asSInt(T_7324) - node T_7338 = eq(T_7336, asSInt(UInt<2>("h02"))) - node T_7339 = or(T_7335, T_7338) - node T_7340 = asSInt(T_7325) - node T_7342 = eq(T_7340, asSInt(UInt<1>("h01"))) - node T_7343 = bits(T_7325, 0, 0) - node T_7344 = mux(T_7339, T_7342, T_7343) - node T_7345 = mux(T_7330, T_7332, T_7344) - node T_7346 = bits(mem_reg_wdata, 38, 0) - node T_7347 = cat(T_7345, T_7346) - node T_7348 = asSInt(T_7347) - node T_7349 = mux(mem_ctrl.jalr, T_7348, mem_br_target) - node T_7351 = and(T_7349, asSInt(UInt<2>("h02"))) - node T_7352 = asSInt(T_7351) - node mem_npc = asUInt(T_7352) - node T_7354 = neq(mem_npc, ex_reg_pc) - node T_7356 = eq(ex_reg_valid, UInt<1>("h00")) - node mem_wrong_npc = or(T_7354, T_7356) - node mem_npc_misaligned = bits(mem_npc, 1, 1) - node T_7359 = and(mem_wrong_npc, mem_reg_valid) - node T_7360 = or(mem_ctrl.branch, mem_ctrl.jalr) - node T_7361 = or(T_7360, mem_ctrl.jal) - node mem_misprediction = and(T_7359, T_7361) - node T_7363 = or(mem_misprediction, mem_reg_flush_pipe) - node want_take_pc_mem = and(mem_reg_valid, T_7363) - node T_7366 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7367 = and(want_take_pc_mem, T_7366) - take_pc_mem <= T_7367 - node T_7369 = eq(ctrl_killx, UInt<1>("h00")) - mem_reg_valid <= T_7369 - node T_7371 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7372 = and(T_7371, replay_ex) - mem_reg_replay <= T_7372 - node T_7374 = eq(ctrl_killx, UInt<1>("h00")) - node T_7375 = and(T_7374, ex_xcpt) - mem_reg_xcpt <= T_7375 - node T_7377 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7378 = and(T_7377, ex_reg_xcpt_interrupt) - mem_reg_xcpt_interrupt <= T_7378 - when ex_xcpt : - mem_reg_cause <= ex_cause - skip - node T_7379 = or(ex_reg_valid, ex_reg_xcpt_interrupt) - when T_7379 : - mem_ctrl <- ex_ctrl - mem_reg_btb_hit <= ex_reg_btb_hit - when ex_reg_btb_hit : - mem_reg_btb_resp <- ex_reg_btb_resp - skip - mem_reg_flush_pipe <= ex_reg_flush_pipe - mem_reg_slow_bypass <= ex_slow_bypass - mem_reg_inst <= ex_reg_inst - mem_reg_pc <= ex_reg_pc - mem_reg_wdata <= alu.io.out - node T_7380 = or(ex_ctrl.mem, ex_ctrl.rocc) - node T_7381 = and(ex_ctrl.rxs2, T_7380) - when T_7381 : - mem_reg_rs2 <= T_6995 - skip - skip - node T_7382 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) - node T_7383 = and(want_take_pc_mem, mem_npc_misaligned) - node T_7385 = and(mem_reg_valid, mem_ctrl.mem) - node T_7386 = and(T_7385, io.dmem.xcpt.ma.st) - node T_7388 = and(mem_reg_valid, mem_ctrl.mem) - node T_7389 = and(T_7388, io.dmem.xcpt.ma.ld) - node T_7391 = and(mem_reg_valid, mem_ctrl.mem) - node T_7392 = and(T_7391, io.dmem.xcpt.pf.st) - node T_7394 = and(mem_reg_valid, mem_ctrl.mem) - node T_7395 = and(T_7394, io.dmem.xcpt.pf.ld) - node T_7397 = or(T_7382, T_7383) - node T_7398 = or(T_7397, T_7386) - node T_7399 = or(T_7398, T_7389) - node T_7400 = or(T_7399, T_7392) - node mem_xcpt = or(T_7400, T_7395) - node T_7402 = mux(T_7392, UInt<3>("h07"), UInt<3>("h05")) - node T_7403 = mux(T_7389, UInt<3>("h04"), T_7402) - node T_7404 = mux(T_7386, UInt<3>("h06"), T_7403) - node T_7405 = mux(T_7383, UInt<1>("h00"), T_7404) - node mem_cause = mux(T_7382, mem_reg_cause, T_7405) - node T_7407 = and(mem_reg_valid, mem_ctrl.wxd) - node dcache_kill_mem = and(T_7407, io.dmem.replay_next.valid) - node T_7409 = and(mem_reg_valid, mem_ctrl.fp) - node fpu_kill_mem = and(T_7409, io.fpu.nack_mem) - node T_7411 = or(dcache_kill_mem, mem_reg_replay) - node replay_mem = or(T_7411, fpu_kill_mem) - node T_7413 = or(dcache_kill_mem, take_pc_wb) - node T_7414 = or(T_7413, mem_reg_xcpt) - node T_7416 = eq(mem_reg_valid, UInt<1>("h00")) - node killm_common = or(T_7414, T_7416) - node T_7418 = and(div.io.req.ready, div.io.req.valid) - reg T_7419 : UInt<1>, clk - T_7419 <= T_7418 - node T_7420 = and(killm_common, T_7419) - div.io.kill <= T_7420 - node T_7421 = or(killm_common, mem_xcpt) - node ctrl_killm = or(T_7421, fpu_kill_mem) - node T_7424 = eq(ctrl_killm, UInt<1>("h00")) - wb_reg_valid <= T_7424 - node T_7426 = eq(take_pc_wb, UInt<1>("h00")) - node T_7427 = and(replay_mem, T_7426) - wb_reg_replay <= T_7427 - node T_7429 = eq(take_pc_wb, UInt<1>("h00")) - node T_7430 = and(mem_xcpt, T_7429) - wb_reg_xcpt <= T_7430 - when mem_xcpt : - wb_reg_cause <= mem_cause - skip - node T_7431 = or(mem_reg_valid, mem_reg_replay) - node T_7432 = or(T_7431, mem_reg_xcpt_interrupt) - when T_7432 : - wb_ctrl <- mem_ctrl - node T_7433 = and(mem_ctrl.fp, mem_ctrl.wxd) - node T_7434 = mux(T_7433, io.fpu.toint_data, mem_int_wdata) - wb_reg_wdata <= T_7434 - when mem_ctrl.rocc : - wb_reg_rs2 <= mem_reg_rs2 - skip - wb_reg_inst <= mem_reg_inst - wb_reg_pc <= mem_reg_pc - skip - node T_7435 = or(wb_ctrl.div, wb_dcache_miss) - node wb_set_sboard = or(T_7435, wb_ctrl.rocc) - node replay_wb_common = or(io.dmem.resp.bits.nack, wb_reg_replay) - node T_7438 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7440 = eq(replay_wb_common, UInt<1>("h00")) - node wb_rocc_val = and(T_7438, T_7440) - node T_7442 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7444 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - node T_7445 = and(T_7442, T_7444) - node replay_wb = or(replay_wb_common, T_7445) - node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) - node T_7448 = or(replay_wb, wb_xcpt) - node T_7449 = or(T_7448, csr.io.eret) - take_pc_wb <= T_7449 - when wb_rocc_val : - node T_7451 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - wb_reg_rocc_pending <= T_7451 - skip - when wb_reg_xcpt : - wb_reg_rocc_pending <= UInt<1>("h00") - skip - node T_7453 = bits(io.dmem.resp.bits.tag, 0, 0) - node T_7454 = bits(T_7453, 0, 0) - node dmem_resp_xpu = eq(T_7454, UInt<1>("h00")) - node T_7457 = bits(io.dmem.resp.bits.tag, 0, 0) - node dmem_resp_fpu = bits(T_7457, 0, 0) - node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) - node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) - node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data) - node T_7462 = and(wb_reg_valid, wb_ctrl.wxd) - node T_7464 = eq(T_7462, UInt<1>("h00")) - div.io.resp.ready <= T_7464 - wire ll_wdata : UInt - ll_wdata <= div.io.resp.bits.data - wire ll_waddr : UInt - ll_waddr <= div.io.resp.bits.tag - node T_7467 = and(div.io.resp.ready, div.io.resp.valid) - wire ll_wen : UInt<1> - ll_wen <= T_7467 - node T_7469 = and(dmem_resp_replay, dmem_resp_xpu) - when T_7469 : - div.io.resp.ready <= UInt<1>("h00") - ll_waddr <= dmem_resp_waddr - ll_wen <= UInt<1>("h01") - skip - node T_7473 = eq(replay_wb, UInt<1>("h00")) - node T_7474 = and(wb_reg_valid, T_7473) - node T_7476 = eq(csr.io.csr_xcpt, UInt<1>("h00")) - node wb_valid = and(T_7474, T_7476) - node wb_wen = and(wb_valid, wb_ctrl.wxd) - node rf_wen = or(wb_wen, ll_wen) - node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) - node T_7481 = and(dmem_resp_valid, dmem_resp_xpu) - node T_7482 = neq(wb_ctrl.csr, UInt<3>("h00")) - node T_7483 = mux(T_7482, csr.io.rw.rdata, wb_reg_wdata) - node T_7484 = mux(ll_wen, ll_wdata, T_7483) - node rf_wdata = mux(T_7481, io.dmem.resp.bits.data, T_7484) - when rf_wen : - node T_7487 = neq(rf_waddr, UInt<1>("h00")) - when T_7487 : - node T_7488 = bits(rf_waddr, 4, 0) - node T_7489 = not(T_7488) - infer mport T_7490 = T_6766[T_7489], clk - T_7490 <= rf_wdata - node T_7491 = eq(rf_waddr, id_raddr1) - when T_7491 : - T_6768 <= rf_wdata - skip - node T_7492 = eq(rf_waddr, id_raddr2) - when T_7492 : - T_6779 <= rf_wdata - skip - skip - skip - csr.io.exception <= wb_reg_xcpt - csr.io.cause <= wb_reg_cause - csr.io.retire <= wb_valid - io.host <- csr.io.host - io.fpu.fcsr_rm <= csr.io.fcsr_rm - csr.io.fcsr_flags <- io.fpu.fcsr_flags - csr.io.rocc <- io.rocc - csr.io.pc <= wb_reg_pc - csr.io.uarch_counters[0] <= UInt<1>("h00") - csr.io.uarch_counters[1] <= UInt<1>("h00") - csr.io.uarch_counters[2] <= UInt<1>("h00") - csr.io.uarch_counters[3] <= UInt<1>("h00") - csr.io.uarch_counters[4] <= UInt<1>("h00") - csr.io.uarch_counters[5] <= UInt<1>("h00") - csr.io.uarch_counters[6] <= UInt<1>("h00") - csr.io.uarch_counters[7] <= UInt<1>("h00") - csr.io.uarch_counters[8] <= UInt<1>("h00") - csr.io.uarch_counters[9] <= UInt<1>("h00") - csr.io.uarch_counters[10] <= UInt<1>("h00") - csr.io.uarch_counters[11] <= UInt<1>("h00") - csr.io.uarch_counters[12] <= UInt<1>("h00") - csr.io.uarch_counters[13] <= UInt<1>("h00") - csr.io.uarch_counters[14] <= UInt<1>("h00") - csr.io.uarch_counters[15] <= UInt<1>("h00") - io.ptw.ptbr <= csr.io.ptbr - io.ptw.invalidate <= csr.io.fatc - io.ptw.status <- csr.io.status - node T_7509 = bits(wb_reg_inst, 31, 20) - csr.io.rw.addr <= T_7509 - node T_7510 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) - csr.io.rw.cmd <= T_7510 - csr.io.rw.wdata <= wb_reg_wdata - node T_7512 = neq(id_raddr1, UInt<1>("h00")) - node T_7513 = and(id_ctrl.rxs1, T_7512) - node T_7515 = neq(id_raddr2, UInt<1>("h00")) - node T_7516 = and(id_ctrl.rxs2, T_7515) - node T_7518 = neq(id_waddr, UInt<1>("h00")) - node T_7519 = and(id_ctrl.wxd, T_7518) - reg T_7521 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) - node T_7524 = dshl(UInt<1>("h01"), ll_waddr) - node T_7526 = mux(ll_wen, T_7524, UInt<1>("h00")) - node T_7527 = not(T_7526) - node T_7528 = and(T_7521, T_7527) - node T_7529 = or(UInt<1>("h00"), ll_wen) - when T_7529 : - T_7521 <= T_7528 - skip - node T_7530 = dshr(T_7528, id_raddr1) - node T_7531 = bits(T_7530, 0, 0) - node T_7532 = and(T_7513, T_7531) - node T_7533 = dshr(T_7528, id_raddr2) - node T_7534 = bits(T_7533, 0, 0) - node T_7535 = and(T_7516, T_7534) - node T_7536 = dshr(T_7528, id_waddr) - node T_7537 = bits(T_7536, 0, 0) - node T_7538 = and(T_7519, T_7537) - node T_7539 = or(T_7532, T_7535) - node id_sboard_hazard = or(T_7539, T_7538) - node T_7541 = and(wb_set_sboard, wb_wen) - node T_7543 = dshl(UInt<1>("h01"), wb_waddr) - node T_7545 = mux(T_7541, T_7543, UInt<1>("h00")) - node T_7546 = or(T_7528, T_7545) - node T_7547 = or(T_7529, T_7541) - when T_7547 : - T_7521 <= T_7546 - skip - node T_7548 = neq(ex_ctrl.csr, UInt<3>("h00")) - node T_7549 = or(T_7548, ex_ctrl.jalr) - node T_7550 = or(T_7549, ex_ctrl.mem) - node T_7551 = or(T_7550, ex_ctrl.div) - node T_7552 = or(T_7551, ex_ctrl.fp) - node ex_cannot_bypass = or(T_7552, ex_ctrl.rocc) - node T_7554 = eq(id_raddr1, ex_waddr) - node T_7555 = and(T_7513, T_7554) - node T_7556 = eq(id_raddr2, ex_waddr) - node T_7557 = and(T_7516, T_7556) - node T_7558 = eq(id_waddr, ex_waddr) - node T_7559 = and(T_7519, T_7558) - node T_7560 = or(T_7555, T_7557) - node T_7561 = or(T_7560, T_7559) - node data_hazard_ex = and(ex_ctrl.wxd, T_7561) - node T_7563 = eq(id_raddr1, ex_waddr) - node T_7564 = and(io.fpu.dec.ren1, T_7563) - node T_7565 = eq(id_raddr2, ex_waddr) - node T_7566 = and(io.fpu.dec.ren2, T_7565) - node T_7567 = eq(id_raddr3, ex_waddr) - node T_7568 = and(io.fpu.dec.ren3, T_7567) - node T_7569 = eq(id_waddr, ex_waddr) - node T_7570 = and(io.fpu.dec.wen, T_7569) - node T_7571 = or(T_7564, T_7566) - node T_7572 = or(T_7571, T_7568) - node T_7573 = or(T_7572, T_7570) - node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7573) - node T_7575 = and(data_hazard_ex, ex_cannot_bypass) - node T_7576 = or(T_7575, fp_data_hazard_ex) - node id_ex_hazard = and(ex_reg_valid, T_7576) - node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) - node T_7580 = neq(mem_ctrl.csr, UInt<3>("h00")) - node T_7581 = and(mem_ctrl.mem, mem_mem_cmd_bh) - node T_7582 = or(T_7580, T_7581) - node T_7583 = or(T_7582, mem_ctrl.div) - node T_7584 = or(T_7583, mem_ctrl.fp) - node mem_cannot_bypass = or(T_7584, mem_ctrl.rocc) - node T_7586 = eq(id_raddr1, mem_waddr) - node T_7587 = and(T_7513, T_7586) - node T_7588 = eq(id_raddr2, mem_waddr) - node T_7589 = and(T_7516, T_7588) - node T_7590 = eq(id_waddr, mem_waddr) - node T_7591 = and(T_7519, T_7590) - node T_7592 = or(T_7587, T_7589) - node T_7593 = or(T_7592, T_7591) - node data_hazard_mem = and(mem_ctrl.wxd, T_7593) - node T_7595 = eq(id_raddr1, mem_waddr) - node T_7596 = and(io.fpu.dec.ren1, T_7595) - node T_7597 = eq(id_raddr2, mem_waddr) - node T_7598 = and(io.fpu.dec.ren2, T_7597) - node T_7599 = eq(id_raddr3, mem_waddr) - node T_7600 = and(io.fpu.dec.ren3, T_7599) - node T_7601 = eq(id_waddr, mem_waddr) - node T_7602 = and(io.fpu.dec.wen, T_7601) - node T_7603 = or(T_7596, T_7598) - node T_7604 = or(T_7603, T_7600) - node T_7605 = or(T_7604, T_7602) - node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7605) - node T_7607 = and(data_hazard_mem, mem_cannot_bypass) - node T_7608 = or(T_7607, fp_data_hazard_mem) - node id_mem_hazard = and(mem_reg_valid, T_7608) - node T_7610 = and(mem_reg_valid, data_hazard_mem) - node T_7611 = and(T_7610, mem_ctrl.mem) - id_load_use <= T_7611 - node T_7612 = eq(id_raddr1, wb_waddr) - node T_7613 = and(T_7513, T_7612) - node T_7614 = eq(id_raddr2, wb_waddr) - node T_7615 = and(T_7516, T_7614) - node T_7616 = eq(id_waddr, wb_waddr) - node T_7617 = and(T_7519, T_7616) - node T_7618 = or(T_7613, T_7615) - node T_7619 = or(T_7618, T_7617) - node data_hazard_wb = and(wb_ctrl.wxd, T_7619) - node T_7621 = eq(id_raddr1, wb_waddr) - node T_7622 = and(io.fpu.dec.ren1, T_7621) - node T_7623 = eq(id_raddr2, wb_waddr) - node T_7624 = and(io.fpu.dec.ren2, T_7623) - node T_7625 = eq(id_raddr3, wb_waddr) - node T_7626 = and(io.fpu.dec.ren3, T_7625) - node T_7627 = eq(id_waddr, wb_waddr) - node T_7628 = and(io.fpu.dec.wen, T_7627) - node T_7629 = or(T_7622, T_7624) - node T_7630 = or(T_7629, T_7626) - node T_7631 = or(T_7630, T_7628) - node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7631) - node T_7633 = and(data_hazard_wb, wb_set_sboard) - node T_7634 = or(T_7633, fp_data_hazard_wb) - node id_wb_hazard = and(wb_reg_valid, T_7634) - reg T_7637 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) - node T_7639 = and(wb_dcache_miss, wb_ctrl.wfd) - node T_7640 = or(T_7639, io.fpu.sboard_set) - node T_7641 = and(T_7640, wb_valid) - node T_7643 = dshl(UInt<1>("h01"), wb_waddr) - node T_7645 = mux(T_7641, T_7643, UInt<1>("h00")) - node T_7646 = or(T_7637, T_7645) - node T_7647 = or(UInt<1>("h00"), T_7641) - when T_7647 : - T_7637 <= T_7646 - skip - node T_7648 = and(dmem_resp_replay, dmem_resp_fpu) - node T_7650 = dshl(UInt<1>("h01"), dmem_resp_waddr) - node T_7652 = mux(T_7648, T_7650, UInt<1>("h00")) - node T_7653 = not(T_7652) - node T_7654 = and(T_7646, T_7653) - node T_7655 = or(T_7647, T_7648) - when T_7655 : - T_7637 <= T_7654 - skip - node T_7657 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) - node T_7659 = mux(io.fpu.sboard_clr, T_7657, UInt<1>("h00")) - node T_7660 = not(T_7659) - node T_7661 = and(T_7654, T_7660) - node T_7662 = or(T_7655, io.fpu.sboard_clr) - when T_7662 : - T_7637 <= T_7661 - skip - node T_7664 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) - node T_7665 = and(id_csr_en, T_7664) - node T_7666 = dshr(T_7637, id_raddr1) - node T_7667 = bits(T_7666, 0, 0) - node T_7668 = and(io.fpu.dec.ren1, T_7667) - node T_7669 = dshr(T_7637, id_raddr2) - node T_7670 = bits(T_7669, 0, 0) - node T_7671 = and(io.fpu.dec.ren2, T_7670) - node T_7672 = dshr(T_7637, id_raddr3) - node T_7673 = bits(T_7672, 0, 0) - node T_7674 = and(io.fpu.dec.ren3, T_7673) - node T_7675 = dshr(T_7637, id_waddr) - node T_7676 = bits(T_7675, 0, 0) - node T_7677 = and(io.fpu.dec.wen, T_7676) - node T_7678 = or(T_7668, T_7671) - node T_7679 = or(T_7678, T_7674) - node T_7680 = or(T_7679, T_7677) - node id_stall_fpu = or(T_7665, T_7680) - node T_7682 = or(id_ex_hazard, id_mem_hazard) - node T_7683 = or(T_7682, id_wb_hazard) - node T_7684 = or(T_7683, id_sboard_hazard) - node T_7685 = and(id_ctrl.fp, id_stall_fpu) - node T_7686 = or(T_7684, T_7685) - node T_7688 = eq(io.dmem.req.ready, UInt<1>("h00")) - node T_7689 = and(id_ctrl.mem, T_7688) - node T_7690 = or(T_7686, T_7689) - node T_7692 = and(UInt<1>("h00"), wb_reg_rocc_pending) - node T_7693 = and(T_7692, id_ctrl.rocc) - node T_7695 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - node T_7696 = and(T_7693, T_7695) - node T_7697 = or(T_7690, T_7696) - node T_7698 = or(T_7697, id_do_fence) - node ctrl_stalld = or(T_7698, csr.io.csr_stall) - node T_7701 = eq(io.imem.resp.valid, UInt<1>("h00")) - node T_7702 = or(T_7701, take_pc_mem_wb) - node T_7703 = or(T_7702, ctrl_stalld) - node T_7704 = or(T_7703, csr.io.interrupt) - ctrl_killd <= T_7704 - io.imem.req.valid <= take_pc_mem_wb - node T_7705 = or(wb_xcpt, csr.io.eret) - node T_7706 = mux(replay_wb, wb_reg_pc, mem_npc) - node T_7707 = mux(T_7705, csr.io.evec, T_7706) - io.imem.req.bits.pc <= T_7707 - node T_7708 = and(wb_reg_valid, wb_ctrl.fence_i) - io.imem.invalidate <= T_7708 - node T_7710 = eq(ctrl_stalld, UInt<1>("h00")) - node T_7711 = or(T_7710, csr.io.interrupt) - io.imem.resp.ready <= T_7711 - node T_7713 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7714 = and(mem_reg_valid, T_7713) - node T_7715 = and(T_7714, mem_wrong_npc) - node T_7716 = and(mem_ctrl.branch, mem_br_taken) - node T_7717 = or(T_7716, mem_ctrl.jalr) - node T_7718 = or(T_7717, mem_ctrl.jal) - node T_7719 = and(T_7715, T_7718) - node T_7721 = eq(take_pc_wb, UInt<1>("h00")) - node T_7722 = and(T_7719, T_7721) - io.imem.btb_update.valid <= T_7722 - node T_7723 = or(mem_ctrl.jal, mem_ctrl.jalr) - io.imem.btb_update.bits.isJump <= T_7723 - node T_7724 = bits(mem_reg_inst, 19, 15) - node T_7727 = and(T_7724, UInt<5>("h019")) - node T_7728 = eq(UInt<1>("h01"), T_7727) - node T_7729 = and(mem_ctrl.jalr, T_7728) - io.imem.btb_update.bits.isReturn <= T_7729 - io.imem.btb_update.bits.pc <= mem_reg_pc - io.imem.btb_update.bits.target <= io.imem.req.bits.pc - io.imem.btb_update.bits.br_pc <= mem_reg_pc - io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit - io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp - node T_7730 = and(mem_reg_valid, mem_ctrl.branch) - node T_7732 = eq(take_pc_wb, UInt<1>("h00")) - node T_7733 = and(T_7730, T_7732) - io.imem.bht_update.valid <= T_7733 - io.imem.bht_update.bits.pc <= mem_reg_pc - io.imem.bht_update.bits.taken <= mem_br_taken - io.imem.bht_update.bits.mispredict <= mem_wrong_npc - io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7734 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) - node T_7736 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7737 = and(T_7734, T_7736) - node T_7739 = eq(take_pc_wb, UInt<1>("h00")) - node T_7740 = and(T_7737, T_7739) - io.imem.ras_update.valid <= T_7740 - io.imem.ras_update.bits.returnAddr <= mem_int_wdata - node T_7741 = bits(mem_waddr, 0, 0) - node T_7742 = and(mem_ctrl.wxd, T_7741) - io.imem.ras_update.bits.isCall <= T_7742 - io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn - io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7744 = eq(ctrl_killd, UInt<1>("h00")) - node T_7745 = and(T_7744, id_ctrl.fp) - io.fpu.valid <= T_7745 - io.fpu.killx <= ctrl_killx - io.fpu.killm <= killm_common - io.fpu.inst <= io.imem.resp.bits.data[0] - io.fpu.fromint_data <= T_6992 - node T_7746 = and(dmem_resp_valid, dmem_resp_fpu) - io.fpu.dmem_resp_val <= T_7746 - io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass - io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ - io.fpu.dmem_resp_tag <= dmem_resp_waddr - node T_7747 = and(ex_reg_valid, ex_ctrl.mem) - io.dmem.req.valid <= T_7747 - node T_7748 = or(killm_common, mem_xcpt) - io.dmem.req.bits.kill <= T_7748 - io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd - io.dmem.req.bits.typ <= ex_ctrl.mem_type - io.dmem.req.bits.phys <= UInt<1>("h00") - node T_7750 = shr(T_6992, 38) - node T_7751 = bits(alu.io.adder_out, 39, 38) - node T_7753 = eq(T_7750, UInt<1>("h00")) - node T_7755 = eq(T_7750, UInt<1>("h01")) - node T_7756 = or(T_7753, T_7755) - node T_7758 = neq(T_7751, UInt<1>("h00")) - node T_7759 = asSInt(T_7750) - node T_7761 = eq(T_7759, asSInt(UInt<1>("h01"))) - node T_7762 = asSInt(T_7750) - node T_7764 = eq(T_7762, asSInt(UInt<2>("h02"))) - node T_7765 = or(T_7761, T_7764) - node T_7766 = asSInt(T_7751) - node T_7768 = eq(T_7766, asSInt(UInt<1>("h01"))) - node T_7769 = bits(T_7751, 0, 0) - node T_7770 = mux(T_7765, T_7768, T_7769) - node T_7771 = mux(T_7756, T_7758, T_7770) - node T_7772 = bits(alu.io.adder_out, 38, 0) - node T_7773 = cat(T_7771, T_7772) - io.dmem.req.bits.addr <= T_7773 - node T_7774 = cat(ex_waddr, ex_ctrl.fp) - io.dmem.req.bits.tag <= T_7774 - node T_7775 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) - io.dmem.req.bits.data <= T_7775 - io.dmem.invalidate_lr <= wb_xcpt - io.rocc.cmd.valid <= wb_rocc_val - node T_7777 = neq(csr.io.status.xs, UInt<1>("h00")) - node T_7778 = and(wb_xcpt, T_7777) - io.rocc.exception <= T_7778 - node T_7780 = neq(csr.io.status.prv, UInt<1>("h00")) - io.rocc.s <= T_7780 - wire T_7799 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} - T_7799 is invalid - node T_7808 = bits(wb_reg_inst, 6, 0) - T_7799.opcode <= T_7808 - node T_7809 = bits(wb_reg_inst, 11, 7) - T_7799.rd <= T_7809 - node T_7810 = bits(wb_reg_inst, 12, 12) - T_7799.xs2 <= T_7810 - node T_7811 = bits(wb_reg_inst, 13, 13) - T_7799.xs1 <= T_7811 - node T_7812 = bits(wb_reg_inst, 14, 14) - T_7799.xd <= T_7812 - node T_7813 = bits(wb_reg_inst, 19, 15) - T_7799.rs1 <= T_7813 - node T_7814 = bits(wb_reg_inst, 24, 20) - T_7799.rs2 <= T_7814 - node T_7815 = bits(wb_reg_inst, 31, 25) - T_7799.funct <= T_7815 - io.rocc.cmd.bits.inst <- T_7799 - io.rocc.cmd.bits.rs1 <= wb_reg_wdata - io.rocc.cmd.bits.rs2 <= wb_reg_rs2 - node T_7816 = bits(csr.io.time, 32, 0) - node T_7818 = mux(rf_wen, rf_waddr, UInt<1>("h00")) - node T_7819 = bits(wb_reg_inst, 19, 15) - reg T_7820 : UInt, clk - T_7820 <= T_6992 - reg T_7821 : UInt, clk - T_7821 <= T_7820 - node T_7822 = bits(wb_reg_inst, 24, 20) - reg T_7823 : UInt, clk - T_7823 <= T_6995 - reg T_7824 : UInt, clk - T_7824 <= T_7823 - node T_7826 = eq(reset, UInt<1>("h00")) - when T_7826 : - printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst) - skip + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}, flip ridx : UInt<1>, widx : UInt<1>, mem : {data : UInt<34>, resp : UInt<2>}[1], flip sink_reset_n : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>} + + io is invalid + io is invalid + wire sink_ready : UInt<1> + sink_ready is invalid + sink_ready <= UInt<1>("h01") + reg mem : {data : UInt<34>, resp : UInt<2>}[1], clock @[AsyncQueue.scala 54:16] + node _T_70 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_72 = eq(sink_ready, UInt<1>("h00")) @[AsyncQueue.scala 55:49] + wire _T_74 : UInt<1> @[AsyncQueue.scala 8:27] + _T_74 is invalid @[AsyncQueue.scala 8:27] + inst widx_bin of AsyncResetRegVec_15 @[BlackBoxRegs.scala 89:21] + widx_bin.io is invalid + widx_bin.clock <= clock + widx_bin.reset <= reset + widx_bin.io.d <= _T_74 @[BlackBoxRegs.scala 91:14] + widx_bin.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node _T_77 = add(widx_bin.io.q, _T_70) @[AsyncQueue.scala 10:47] + node _T_78 = tail(_T_77, 1) @[AsyncQueue.scala 10:47] + node _T_79 = mux(_T_72, UInt<1>("h00"), _T_78) @[AsyncQueue.scala 10:23] + _T_74 <= _T_79 @[AsyncQueue.scala 10:17] + node _T_81 = dshr(_T_74, UInt<1>("h01")) @[AsyncQueue.scala 11:32] + node widx = xor(_T_74, _T_81) @[AsyncQueue.scala 11:17] + inst ridx_gray_sync_0 of AsyncResetRegVec_16 @[AsyncQueue.scala 18:14] + ridx_gray_sync_0.io is invalid + ridx_gray_sync_0.clock <= clock + ridx_gray_sync_0.reset <= reset + inst ridx_gray_sync_1 of AsyncResetRegVec_17 @[AsyncQueue.scala 18:14] + ridx_gray_sync_1.io is invalid + ridx_gray_sync_1.clock <= clock + ridx_gray_sync_1.reset <= reset + inst ridx_gray_sync_2 of AsyncResetRegVec_18 @[AsyncQueue.scala 18:14] + ridx_gray_sync_2.io is invalid + ridx_gray_sync_2.clock <= clock + ridx_gray_sync_2.reset <= reset + ridx_gray_sync_2.io.d <= io.ridx @[AsyncQueue.scala 20:21] + ridx_gray_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + ridx_gray_sync_0.io.d <= ridx_gray_sync_1.io.q @[AsyncQueue.scala 23:19] + ridx_gray_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + ridx_gray_sync_1.io.d <= ridx_gray_sync_2.io.q @[AsyncQueue.scala 23:19] + ridx_gray_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_86 = xor(ridx_gray_sync_0.io.q, UInt<1>("h01")) @[AsyncQueue.scala 57:44] + node _T_87 = neq(widx, _T_86) @[AsyncQueue.scala 57:34] + node ready = and(sink_ready, _T_87) @[AsyncQueue.scala 57:26] + node _T_88 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + when _T_88 : @[AsyncQueue.scala 60:24] + mem[UInt<1>("h00")] <- io.enq.bits @[AsyncQueue.scala 60:37] + skip @[AsyncQueue.scala 60:24] + inst ready_reg of AsyncResetRegVec_19 @[BlackBoxRegs.scala 89:21] + ready_reg.io is invalid + ready_reg.clock <= clock + ready_reg.reset <= reset + ready_reg.io.d <= ready @[BlackBoxRegs.scala 91:14] + ready_reg.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node ready_reg_1 = bits(ready_reg.io.q, 0, 0) @[AsyncQueue.scala 62:59] + node _T_96 = and(ready_reg_1, sink_ready) @[AsyncQueue.scala 63:29] + io.enq.ready <= _T_96 @[AsyncQueue.scala 63:16] + inst widx_gray of AsyncResetRegVec_20 @[BlackBoxRegs.scala 89:21] + widx_gray.io is invalid + widx_gray.clock <= clock + widx_gray.reset <= reset + widx_gray.io.d <= widx @[BlackBoxRegs.scala 91:14] + widx_gray.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + io.widx <= widx_gray.io.q @[AsyncQueue.scala 66:11] + io.mem <- mem @[AsyncQueue.scala 68:10] + io.widx_valid <= UInt<1>("h01") @[AsyncQueue.scala 70:17] + inst AsyncValidSync of AsyncValidSync_3 @[AsyncQueue.scala 72:30] + AsyncValidSync.io is invalid + AsyncValidSync.clock <= clock + AsyncValidSync.reset <= reset + inst AsyncValidSync_1 of AsyncValidSync_4 @[AsyncQueue.scala 73:30] + AsyncValidSync_1.io is invalid + AsyncValidSync_1.clock <= clock + AsyncValidSync_1.reset <= reset + inst AsyncValidSync_2 of AsyncValidSync_5 @[AsyncQueue.scala 74:30] + AsyncValidSync_2.io is invalid + AsyncValidSync_2.clock <= clock + AsyncValidSync_2.reset <= reset + node _T_100 = eq(io.sink_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 75:36] + node _T_101 = or(reset, _T_100) @[AsyncQueue.scala 75:33] + AsyncValidSync.reset <= _T_101 @[AsyncQueue.scala 75:24] + node _T_103 = eq(io.sink_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 76:36] + node _T_104 = or(reset, _T_103) @[AsyncQueue.scala 76:33] + AsyncValidSync_1.reset <= _T_104 @[AsyncQueue.scala 76:24] + AsyncValidSync.io.in <= UInt<1>("h01") @[AsyncQueue.scala 78:24] + io.widx_valid <= AsyncValidSync.io.out @[AsyncQueue.scala 79:19] + AsyncValidSync_1.io.in <= io.ridx_valid @[AsyncQueue.scala 80:23] + AsyncValidSync_2.io.in <= AsyncValidSync_1.io.out @[AsyncQueue.scala 81:22] + sink_ready <= AsyncValidSync_2.io.out @[AsyncQueue.scala 82:16] - module BTB : - input clk : Clock + module DefaultCoreplex_coreplex : + input clock : Clock input reset : UInt<1> - output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>} - - io is invalid - reg idxValid : UInt<62>, clk with : (reset => (reset, UInt<62>("h00"))) - cmem idxs : UInt<12>[62] - cmem idxPages : UInt<3>[62] - cmem tgts : UInt<12>[62] - cmem tgtPages : UInt<3>[62] - cmem pages : UInt<27>[6] - reg pageValid : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - infer mport T_590 = idxPages[UInt<1>("h00")], clk - node T_592 = dshl(UInt<1>("h01"), T_590) - node T_593 = bits(T_592, 5, 0) - infer mport T_595 = idxPages[UInt<1>("h01")], clk - node T_597 = dshl(UInt<1>("h01"), T_595) - node T_598 = bits(T_597, 5, 0) - infer mport T_600 = idxPages[UInt<2>("h02")], clk - node T_602 = dshl(UInt<1>("h01"), T_600) - node T_603 = bits(T_602, 5, 0) - infer mport T_605 = idxPages[UInt<2>("h03")], clk - node T_607 = dshl(UInt<1>("h01"), T_605) - node T_608 = bits(T_607, 5, 0) - infer mport T_610 = idxPages[UInt<3>("h04")], clk - node T_612 = dshl(UInt<1>("h01"), T_610) - node T_613 = bits(T_612, 5, 0) - infer mport T_615 = idxPages[UInt<3>("h05")], clk - node T_617 = dshl(UInt<1>("h01"), T_615) - node T_618 = bits(T_617, 5, 0) - infer mport T_620 = idxPages[UInt<3>("h06")], clk - node T_622 = dshl(UInt<1>("h01"), T_620) - node T_623 = bits(T_622, 5, 0) - infer mport T_625 = idxPages[UInt<3>("h07")], clk - node T_627 = dshl(UInt<1>("h01"), T_625) - node T_628 = bits(T_627, 5, 0) - infer mport T_630 = idxPages[UInt<4>("h08")], clk - node T_632 = dshl(UInt<1>("h01"), T_630) - node T_633 = bits(T_632, 5, 0) - infer mport T_635 = idxPages[UInt<4>("h09")], clk - node T_637 = dshl(UInt<1>("h01"), T_635) - node T_638 = bits(T_637, 5, 0) - infer mport T_640 = idxPages[UInt<4>("h0a")], clk - node T_642 = dshl(UInt<1>("h01"), T_640) - node T_643 = bits(T_642, 5, 0) - infer mport T_645 = idxPages[UInt<4>("h0b")], clk - node T_647 = dshl(UInt<1>("h01"), T_645) - node T_648 = bits(T_647, 5, 0) - infer mport T_650 = idxPages[UInt<4>("h0c")], clk - node T_652 = dshl(UInt<1>("h01"), T_650) - node T_653 = bits(T_652, 5, 0) - infer mport T_655 = idxPages[UInt<4>("h0d")], clk - node T_657 = dshl(UInt<1>("h01"), T_655) - node T_658 = bits(T_657, 5, 0) - infer mport T_660 = idxPages[UInt<4>("h0e")], clk - node T_662 = dshl(UInt<1>("h01"), T_660) - node T_663 = bits(T_662, 5, 0) - infer mport T_665 = idxPages[UInt<4>("h0f")], clk - node T_667 = dshl(UInt<1>("h01"), T_665) - node T_668 = bits(T_667, 5, 0) - infer mport T_670 = idxPages[UInt<5>("h010")], clk - node T_672 = dshl(UInt<1>("h01"), T_670) - node T_673 = bits(T_672, 5, 0) - infer mport T_675 = idxPages[UInt<5>("h011")], clk - node T_677 = dshl(UInt<1>("h01"), T_675) - node T_678 = bits(T_677, 5, 0) - infer mport T_680 = idxPages[UInt<5>("h012")], clk - node T_682 = dshl(UInt<1>("h01"), T_680) - node T_683 = bits(T_682, 5, 0) - infer mport T_685 = idxPages[UInt<5>("h013")], clk - node T_687 = dshl(UInt<1>("h01"), T_685) - node T_688 = bits(T_687, 5, 0) - infer mport T_690 = idxPages[UInt<5>("h014")], clk - node T_692 = dshl(UInt<1>("h01"), T_690) - node T_693 = bits(T_692, 5, 0) - infer mport T_695 = idxPages[UInt<5>("h015")], clk - node T_697 = dshl(UInt<1>("h01"), T_695) - node T_698 = bits(T_697, 5, 0) - infer mport T_700 = idxPages[UInt<5>("h016")], clk - node T_702 = dshl(UInt<1>("h01"), T_700) - node T_703 = bits(T_702, 5, 0) - infer mport T_705 = idxPages[UInt<5>("h017")], clk - node T_707 = dshl(UInt<1>("h01"), T_705) - node T_708 = bits(T_707, 5, 0) - infer mport T_710 = idxPages[UInt<5>("h018")], clk - node T_712 = dshl(UInt<1>("h01"), T_710) - node T_713 = bits(T_712, 5, 0) - infer mport T_715 = idxPages[UInt<5>("h019")], clk - node T_717 = dshl(UInt<1>("h01"), T_715) - node T_718 = bits(T_717, 5, 0) - infer mport T_720 = idxPages[UInt<5>("h01a")], clk - node T_722 = dshl(UInt<1>("h01"), T_720) - node T_723 = bits(T_722, 5, 0) - infer mport T_725 = idxPages[UInt<5>("h01b")], clk - node T_727 = dshl(UInt<1>("h01"), T_725) - node T_728 = bits(T_727, 5, 0) - infer mport T_730 = idxPages[UInt<5>("h01c")], clk - node T_732 = dshl(UInt<1>("h01"), T_730) - node T_733 = bits(T_732, 5, 0) - infer mport T_735 = idxPages[UInt<5>("h01d")], clk - node T_737 = dshl(UInt<1>("h01"), T_735) - node T_738 = bits(T_737, 5, 0) - infer mport T_740 = idxPages[UInt<5>("h01e")], clk - node T_742 = dshl(UInt<1>("h01"), T_740) - node T_743 = bits(T_742, 5, 0) - infer mport T_745 = idxPages[UInt<5>("h01f")], clk - node T_747 = dshl(UInt<1>("h01"), T_745) - node T_748 = bits(T_747, 5, 0) - infer mport T_750 = idxPages[UInt<6>("h020")], clk - node T_752 = dshl(UInt<1>("h01"), T_750) - node T_753 = bits(T_752, 5, 0) - infer mport T_755 = idxPages[UInt<6>("h021")], clk - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_758 = bits(T_757, 5, 0) - infer mport T_760 = idxPages[UInt<6>("h022")], clk - node T_762 = dshl(UInt<1>("h01"), T_760) - node T_763 = bits(T_762, 5, 0) - infer mport T_765 = idxPages[UInt<6>("h023")], clk - node T_767 = dshl(UInt<1>("h01"), T_765) - node T_768 = bits(T_767, 5, 0) - infer mport T_770 = idxPages[UInt<6>("h024")], clk - node T_772 = dshl(UInt<1>("h01"), T_770) - node T_773 = bits(T_772, 5, 0) - infer mport T_775 = idxPages[UInt<6>("h025")], clk - node T_777 = dshl(UInt<1>("h01"), T_775) - node T_778 = bits(T_777, 5, 0) - infer mport T_780 = idxPages[UInt<6>("h026")], clk - node T_782 = dshl(UInt<1>("h01"), T_780) - node T_783 = bits(T_782, 5, 0) - infer mport T_785 = idxPages[UInt<6>("h027")], clk - node T_787 = dshl(UInt<1>("h01"), T_785) - node T_788 = bits(T_787, 5, 0) - infer mport T_790 = idxPages[UInt<6>("h028")], clk - node T_792 = dshl(UInt<1>("h01"), T_790) - node T_793 = bits(T_792, 5, 0) - infer mport T_795 = idxPages[UInt<6>("h029")], clk - node T_797 = dshl(UInt<1>("h01"), T_795) - node T_798 = bits(T_797, 5, 0) - infer mport T_800 = idxPages[UInt<6>("h02a")], clk - node T_802 = dshl(UInt<1>("h01"), T_800) - node T_803 = bits(T_802, 5, 0) - infer mport T_805 = idxPages[UInt<6>("h02b")], clk - node T_807 = dshl(UInt<1>("h01"), T_805) - node T_808 = bits(T_807, 5, 0) - infer mport T_810 = idxPages[UInt<6>("h02c")], clk - node T_812 = dshl(UInt<1>("h01"), T_810) - node T_813 = bits(T_812, 5, 0) - infer mport T_815 = idxPages[UInt<6>("h02d")], clk - node T_817 = dshl(UInt<1>("h01"), T_815) - node T_818 = bits(T_817, 5, 0) - infer mport T_820 = idxPages[UInt<6>("h02e")], clk - node T_822 = dshl(UInt<1>("h01"), T_820) - node T_823 = bits(T_822, 5, 0) - infer mport T_825 = idxPages[UInt<6>("h02f")], clk - node T_827 = dshl(UInt<1>("h01"), T_825) - node T_828 = bits(T_827, 5, 0) - infer mport T_830 = idxPages[UInt<6>("h030")], clk - node T_832 = dshl(UInt<1>("h01"), T_830) - node T_833 = bits(T_832, 5, 0) - infer mport T_835 = idxPages[UInt<6>("h031")], clk - node T_837 = dshl(UInt<1>("h01"), T_835) - node T_838 = bits(T_837, 5, 0) - infer mport T_840 = idxPages[UInt<6>("h032")], clk - node T_842 = dshl(UInt<1>("h01"), T_840) - node T_843 = bits(T_842, 5, 0) - infer mport T_845 = idxPages[UInt<6>("h033")], clk - node T_847 = dshl(UInt<1>("h01"), T_845) - node T_848 = bits(T_847, 5, 0) - infer mport T_850 = idxPages[UInt<6>("h034")], clk - node T_852 = dshl(UInt<1>("h01"), T_850) - node T_853 = bits(T_852, 5, 0) - infer mport T_855 = idxPages[UInt<6>("h035")], clk - node T_857 = dshl(UInt<1>("h01"), T_855) - node T_858 = bits(T_857, 5, 0) - infer mport T_860 = idxPages[UInt<6>("h036")], clk - node T_862 = dshl(UInt<1>("h01"), T_860) - node T_863 = bits(T_862, 5, 0) - infer mport T_865 = idxPages[UInt<6>("h037")], clk - node T_867 = dshl(UInt<1>("h01"), T_865) - node T_868 = bits(T_867, 5, 0) - infer mport T_870 = idxPages[UInt<6>("h038")], clk - node T_872 = dshl(UInt<1>("h01"), T_870) - node T_873 = bits(T_872, 5, 0) - infer mport T_875 = idxPages[UInt<6>("h039")], clk - node T_877 = dshl(UInt<1>("h01"), T_875) - node T_878 = bits(T_877, 5, 0) - infer mport T_880 = idxPages[UInt<6>("h03a")], clk - node T_882 = dshl(UInt<1>("h01"), T_880) - node T_883 = bits(T_882, 5, 0) - infer mport T_885 = idxPages[UInt<6>("h03b")], clk - node T_887 = dshl(UInt<1>("h01"), T_885) - node T_888 = bits(T_887, 5, 0) - infer mport T_890 = idxPages[UInt<6>("h03c")], clk - node T_892 = dshl(UInt<1>("h01"), T_890) - node T_893 = bits(T_892, 5, 0) - infer mport T_895 = idxPages[UInt<6>("h03d")], clk - node T_897 = dshl(UInt<1>("h01"), T_895) - node T_898 = bits(T_897, 5, 0) - infer mport T_900 = tgtPages[UInt<1>("h00")], clk - node T_902 = dshl(UInt<1>("h01"), T_900) - node T_903 = bits(T_902, 5, 0) - infer mport T_905 = tgtPages[UInt<1>("h01")], clk - node T_907 = dshl(UInt<1>("h01"), T_905) - node T_908 = bits(T_907, 5, 0) - infer mport T_910 = tgtPages[UInt<2>("h02")], clk - node T_912 = dshl(UInt<1>("h01"), T_910) - node T_913 = bits(T_912, 5, 0) - infer mport T_915 = tgtPages[UInt<2>("h03")], clk - node T_917 = dshl(UInt<1>("h01"), T_915) - node T_918 = bits(T_917, 5, 0) - infer mport T_920 = tgtPages[UInt<3>("h04")], clk - node T_922 = dshl(UInt<1>("h01"), T_920) - node T_923 = bits(T_922, 5, 0) - infer mport T_925 = tgtPages[UInt<3>("h05")], clk - node T_927 = dshl(UInt<1>("h01"), T_925) - node T_928 = bits(T_927, 5, 0) - infer mport T_930 = tgtPages[UInt<3>("h06")], clk - node T_932 = dshl(UInt<1>("h01"), T_930) - node T_933 = bits(T_932, 5, 0) - infer mport T_935 = tgtPages[UInt<3>("h07")], clk - node T_937 = dshl(UInt<1>("h01"), T_935) - node T_938 = bits(T_937, 5, 0) - infer mport T_940 = tgtPages[UInt<4>("h08")], clk - node T_942 = dshl(UInt<1>("h01"), T_940) - node T_943 = bits(T_942, 5, 0) - infer mport T_945 = tgtPages[UInt<4>("h09")], clk - node T_947 = dshl(UInt<1>("h01"), T_945) - node T_948 = bits(T_947, 5, 0) - infer mport T_950 = tgtPages[UInt<4>("h0a")], clk - node T_952 = dshl(UInt<1>("h01"), T_950) - node T_953 = bits(T_952, 5, 0) - infer mport T_955 = tgtPages[UInt<4>("h0b")], clk - node T_957 = dshl(UInt<1>("h01"), T_955) - node T_958 = bits(T_957, 5, 0) - infer mport T_960 = tgtPages[UInt<4>("h0c")], clk - node T_962 = dshl(UInt<1>("h01"), T_960) - node T_963 = bits(T_962, 5, 0) - infer mport T_965 = tgtPages[UInt<4>("h0d")], clk - node T_967 = dshl(UInt<1>("h01"), T_965) - node T_968 = bits(T_967, 5, 0) - infer mport T_970 = tgtPages[UInt<4>("h0e")], clk - node T_972 = dshl(UInt<1>("h01"), T_970) - node T_973 = bits(T_972, 5, 0) - infer mport T_975 = tgtPages[UInt<4>("h0f")], clk - node T_977 = dshl(UInt<1>("h01"), T_975) - node T_978 = bits(T_977, 5, 0) - infer mport T_980 = tgtPages[UInt<5>("h010")], clk - node T_982 = dshl(UInt<1>("h01"), T_980) - node T_983 = bits(T_982, 5, 0) - infer mport T_985 = tgtPages[UInt<5>("h011")], clk - node T_987 = dshl(UInt<1>("h01"), T_985) - node T_988 = bits(T_987, 5, 0) - infer mport T_990 = tgtPages[UInt<5>("h012")], clk - node T_992 = dshl(UInt<1>("h01"), T_990) - node T_993 = bits(T_992, 5, 0) - infer mport T_995 = tgtPages[UInt<5>("h013")], clk - node T_997 = dshl(UInt<1>("h01"), T_995) - node T_998 = bits(T_997, 5, 0) - infer mport T_1000 = tgtPages[UInt<5>("h014")], clk - node T_1002 = dshl(UInt<1>("h01"), T_1000) - node T_1003 = bits(T_1002, 5, 0) - infer mport T_1005 = tgtPages[UInt<5>("h015")], clk - node T_1007 = dshl(UInt<1>("h01"), T_1005) - node T_1008 = bits(T_1007, 5, 0) - infer mport T_1010 = tgtPages[UInt<5>("h016")], clk - node T_1012 = dshl(UInt<1>("h01"), T_1010) - node T_1013 = bits(T_1012, 5, 0) - infer mport T_1015 = tgtPages[UInt<5>("h017")], clk - node T_1017 = dshl(UInt<1>("h01"), T_1015) - node T_1018 = bits(T_1017, 5, 0) - infer mport T_1020 = tgtPages[UInt<5>("h018")], clk - node T_1022 = dshl(UInt<1>("h01"), T_1020) - node T_1023 = bits(T_1022, 5, 0) - infer mport T_1025 = tgtPages[UInt<5>("h019")], clk - node T_1027 = dshl(UInt<1>("h01"), T_1025) - node T_1028 = bits(T_1027, 5, 0) - infer mport T_1030 = tgtPages[UInt<5>("h01a")], clk - node T_1032 = dshl(UInt<1>("h01"), T_1030) - node T_1033 = bits(T_1032, 5, 0) - infer mport T_1035 = tgtPages[UInt<5>("h01b")], clk - node T_1037 = dshl(UInt<1>("h01"), T_1035) - node T_1038 = bits(T_1037, 5, 0) - infer mport T_1040 = tgtPages[UInt<5>("h01c")], clk - node T_1042 = dshl(UInt<1>("h01"), T_1040) - node T_1043 = bits(T_1042, 5, 0) - infer mport T_1045 = tgtPages[UInt<5>("h01d")], clk - node T_1047 = dshl(UInt<1>("h01"), T_1045) - node T_1048 = bits(T_1047, 5, 0) - infer mport T_1050 = tgtPages[UInt<5>("h01e")], clk - node T_1052 = dshl(UInt<1>("h01"), T_1050) - node T_1053 = bits(T_1052, 5, 0) - infer mport T_1055 = tgtPages[UInt<5>("h01f")], clk - node T_1057 = dshl(UInt<1>("h01"), T_1055) - node T_1058 = bits(T_1057, 5, 0) - infer mport T_1060 = tgtPages[UInt<6>("h020")], clk - node T_1062 = dshl(UInt<1>("h01"), T_1060) - node T_1063 = bits(T_1062, 5, 0) - infer mport T_1065 = tgtPages[UInt<6>("h021")], clk - node T_1067 = dshl(UInt<1>("h01"), T_1065) - node T_1068 = bits(T_1067, 5, 0) - infer mport T_1070 = tgtPages[UInt<6>("h022")], clk - node T_1072 = dshl(UInt<1>("h01"), T_1070) - node T_1073 = bits(T_1072, 5, 0) - infer mport T_1075 = tgtPages[UInt<6>("h023")], clk - node T_1077 = dshl(UInt<1>("h01"), T_1075) - node T_1078 = bits(T_1077, 5, 0) - infer mport T_1080 = tgtPages[UInt<6>("h024")], clk - node T_1082 = dshl(UInt<1>("h01"), T_1080) - node T_1083 = bits(T_1082, 5, 0) - infer mport T_1085 = tgtPages[UInt<6>("h025")], clk - node T_1087 = dshl(UInt<1>("h01"), T_1085) - node T_1088 = bits(T_1087, 5, 0) - infer mport T_1090 = tgtPages[UInt<6>("h026")], clk - node T_1092 = dshl(UInt<1>("h01"), T_1090) - node T_1093 = bits(T_1092, 5, 0) - infer mport T_1095 = tgtPages[UInt<6>("h027")], clk - node T_1097 = dshl(UInt<1>("h01"), T_1095) - node T_1098 = bits(T_1097, 5, 0) - infer mport T_1100 = tgtPages[UInt<6>("h028")], clk - node T_1102 = dshl(UInt<1>("h01"), T_1100) - node T_1103 = bits(T_1102, 5, 0) - infer mport T_1105 = tgtPages[UInt<6>("h029")], clk - node T_1107 = dshl(UInt<1>("h01"), T_1105) - node T_1108 = bits(T_1107, 5, 0) - infer mport T_1110 = tgtPages[UInt<6>("h02a")], clk - node T_1112 = dshl(UInt<1>("h01"), T_1110) - node T_1113 = bits(T_1112, 5, 0) - infer mport T_1115 = tgtPages[UInt<6>("h02b")], clk - node T_1117 = dshl(UInt<1>("h01"), T_1115) - node T_1118 = bits(T_1117, 5, 0) - infer mport T_1120 = tgtPages[UInt<6>("h02c")], clk - node T_1122 = dshl(UInt<1>("h01"), T_1120) - node T_1123 = bits(T_1122, 5, 0) - infer mport T_1125 = tgtPages[UInt<6>("h02d")], clk - node T_1127 = dshl(UInt<1>("h01"), T_1125) - node T_1128 = bits(T_1127, 5, 0) - infer mport T_1130 = tgtPages[UInt<6>("h02e")], clk - node T_1132 = dshl(UInt<1>("h01"), T_1130) - node T_1133 = bits(T_1132, 5, 0) - infer mport T_1135 = tgtPages[UInt<6>("h02f")], clk - node T_1137 = dshl(UInt<1>("h01"), T_1135) - node T_1138 = bits(T_1137, 5, 0) - infer mport T_1140 = tgtPages[UInt<6>("h030")], clk - node T_1142 = dshl(UInt<1>("h01"), T_1140) - node T_1143 = bits(T_1142, 5, 0) - infer mport T_1145 = tgtPages[UInt<6>("h031")], clk - node T_1147 = dshl(UInt<1>("h01"), T_1145) - node T_1148 = bits(T_1147, 5, 0) - infer mport T_1150 = tgtPages[UInt<6>("h032")], clk - node T_1152 = dshl(UInt<1>("h01"), T_1150) - node T_1153 = bits(T_1152, 5, 0) - infer mport T_1155 = tgtPages[UInt<6>("h033")], clk - node T_1157 = dshl(UInt<1>("h01"), T_1155) - node T_1158 = bits(T_1157, 5, 0) - infer mport T_1160 = tgtPages[UInt<6>("h034")], clk - node T_1162 = dshl(UInt<1>("h01"), T_1160) - node T_1163 = bits(T_1162, 5, 0) - infer mport T_1165 = tgtPages[UInt<6>("h035")], clk - node T_1167 = dshl(UInt<1>("h01"), T_1165) - node T_1168 = bits(T_1167, 5, 0) - infer mport T_1170 = tgtPages[UInt<6>("h036")], clk - node T_1172 = dshl(UInt<1>("h01"), T_1170) - node T_1173 = bits(T_1172, 5, 0) - infer mport T_1175 = tgtPages[UInt<6>("h037")], clk - node T_1177 = dshl(UInt<1>("h01"), T_1175) - node T_1178 = bits(T_1177, 5, 0) - infer mport T_1180 = tgtPages[UInt<6>("h038")], clk - node T_1182 = dshl(UInt<1>("h01"), T_1180) - node T_1183 = bits(T_1182, 5, 0) - infer mport T_1185 = tgtPages[UInt<6>("h039")], clk - node T_1187 = dshl(UInt<1>("h01"), T_1185) - node T_1188 = bits(T_1187, 5, 0) - infer mport T_1190 = tgtPages[UInt<6>("h03a")], clk - node T_1192 = dshl(UInt<1>("h01"), T_1190) - node T_1193 = bits(T_1192, 5, 0) - infer mport T_1195 = tgtPages[UInt<6>("h03b")], clk - node T_1197 = dshl(UInt<1>("h01"), T_1195) - node T_1198 = bits(T_1197, 5, 0) - infer mport T_1200 = tgtPages[UInt<6>("h03c")], clk - node T_1202 = dshl(UInt<1>("h01"), T_1200) - node T_1203 = bits(T_1202, 5, 0) - infer mport T_1205 = tgtPages[UInt<6>("h03d")], clk - node T_1207 = dshl(UInt<1>("h01"), T_1205) - node T_1208 = bits(T_1207, 5, 0) - reg useRAS : UInt<1>[62], clk - reg isJump : UInt<1>[62], clk - cmem brIdx : UInt<1>[62] - reg T_1478 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_1478 <= io.btb_update.valid - reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk - when io.btb_update.valid : - T_1479 <- io.btb_update.bits - skip - wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} - r_btb_update is invalid - r_btb_update.valid <= T_1478 - r_btb_update.bits <- T_1479 - node T_1663 = shr(io.req.bits.addr, 12) - infer mport T_1665 = pages[UInt<1>("h00")], clk - node T_1666 = eq(T_1665, T_1663) - infer mport T_1668 = pages[UInt<1>("h01")], clk - node T_1669 = eq(T_1668, T_1663) - infer mport T_1671 = pages[UInt<2>("h02")], clk - node T_1672 = eq(T_1671, T_1663) - infer mport T_1674 = pages[UInt<2>("h03")], clk - node T_1675 = eq(T_1674, T_1663) - infer mport T_1677 = pages[UInt<3>("h04")], clk - node T_1678 = eq(T_1677, T_1663) - infer mport T_1680 = pages[UInt<3>("h05")], clk - node T_1681 = eq(T_1680, T_1663) - wire T_1683 : UInt<1>[6] - T_1683[0] <= T_1666 - T_1683[1] <= T_1669 - T_1683[2] <= T_1672 - T_1683[3] <= T_1675 - T_1683[4] <= T_1678 - T_1683[5] <= T_1681 - node T_1691 = cat(T_1683[4], T_1683[3]) - node T_1692 = cat(T_1683[5], T_1691) - node T_1693 = cat(T_1683[1], T_1683[0]) - node T_1694 = cat(T_1683[2], T_1693) - node T_1695 = cat(T_1692, T_1694) - node pageHit = and(T_1695, pageValid) - node T_1697 = bits(io.req.bits.addr, 11, 0) - infer mport T_1699 = idxs[UInt<1>("h00")], clk - node T_1700 = eq(T_1699, T_1697) - infer mport T_1702 = idxs[UInt<1>("h01")], clk - node T_1703 = eq(T_1702, T_1697) - infer mport T_1705 = idxs[UInt<2>("h02")], clk - node T_1706 = eq(T_1705, T_1697) - infer mport T_1708 = idxs[UInt<2>("h03")], clk - node T_1709 = eq(T_1708, T_1697) - infer mport T_1711 = idxs[UInt<3>("h04")], clk - node T_1712 = eq(T_1711, T_1697) - infer mport T_1714 = idxs[UInt<3>("h05")], clk - node T_1715 = eq(T_1714, T_1697) - infer mport T_1717 = idxs[UInt<3>("h06")], clk - node T_1718 = eq(T_1717, T_1697) - infer mport T_1720 = idxs[UInt<3>("h07")], clk - node T_1721 = eq(T_1720, T_1697) - infer mport T_1723 = idxs[UInt<4>("h08")], clk - node T_1724 = eq(T_1723, T_1697) - infer mport T_1726 = idxs[UInt<4>("h09")], clk - node T_1727 = eq(T_1726, T_1697) - infer mport T_1729 = idxs[UInt<4>("h0a")], clk - node T_1730 = eq(T_1729, T_1697) - infer mport T_1732 = idxs[UInt<4>("h0b")], clk - node T_1733 = eq(T_1732, T_1697) - infer mport T_1735 = idxs[UInt<4>("h0c")], clk - node T_1736 = eq(T_1735, T_1697) - infer mport T_1738 = idxs[UInt<4>("h0d")], clk - node T_1739 = eq(T_1738, T_1697) - infer mport T_1741 = idxs[UInt<4>("h0e")], clk - node T_1742 = eq(T_1741, T_1697) - infer mport T_1744 = idxs[UInt<4>("h0f")], clk - node T_1745 = eq(T_1744, T_1697) - infer mport T_1747 = idxs[UInt<5>("h010")], clk - node T_1748 = eq(T_1747, T_1697) - infer mport T_1750 = idxs[UInt<5>("h011")], clk - node T_1751 = eq(T_1750, T_1697) - infer mport T_1753 = idxs[UInt<5>("h012")], clk - node T_1754 = eq(T_1753, T_1697) - infer mport T_1756 = idxs[UInt<5>("h013")], clk - node T_1757 = eq(T_1756, T_1697) - infer mport T_1759 = idxs[UInt<5>("h014")], clk - node T_1760 = eq(T_1759, T_1697) - infer mport T_1762 = idxs[UInt<5>("h015")], clk - node T_1763 = eq(T_1762, T_1697) - infer mport T_1765 = idxs[UInt<5>("h016")], clk - node T_1766 = eq(T_1765, T_1697) - infer mport T_1768 = idxs[UInt<5>("h017")], clk - node T_1769 = eq(T_1768, T_1697) - infer mport T_1771 = idxs[UInt<5>("h018")], clk - node T_1772 = eq(T_1771, T_1697) - infer mport T_1774 = idxs[UInt<5>("h019")], clk - node T_1775 = eq(T_1774, T_1697) - infer mport T_1777 = idxs[UInt<5>("h01a")], clk - node T_1778 = eq(T_1777, T_1697) - infer mport T_1780 = idxs[UInt<5>("h01b")], clk - node T_1781 = eq(T_1780, T_1697) - infer mport T_1783 = idxs[UInt<5>("h01c")], clk - node T_1784 = eq(T_1783, T_1697) - infer mport T_1786 = idxs[UInt<5>("h01d")], clk - node T_1787 = eq(T_1786, T_1697) - infer mport T_1789 = idxs[UInt<5>("h01e")], clk - node T_1790 = eq(T_1789, T_1697) - infer mport T_1792 = idxs[UInt<5>("h01f")], clk - node T_1793 = eq(T_1792, T_1697) - infer mport T_1795 = idxs[UInt<6>("h020")], clk - node T_1796 = eq(T_1795, T_1697) - infer mport T_1798 = idxs[UInt<6>("h021")], clk - node T_1799 = eq(T_1798, T_1697) - infer mport T_1801 = idxs[UInt<6>("h022")], clk - node T_1802 = eq(T_1801, T_1697) - infer mport T_1804 = idxs[UInt<6>("h023")], clk - node T_1805 = eq(T_1804, T_1697) - infer mport T_1807 = idxs[UInt<6>("h024")], clk - node T_1808 = eq(T_1807, T_1697) - infer mport T_1810 = idxs[UInt<6>("h025")], clk - node T_1811 = eq(T_1810, T_1697) - infer mport T_1813 = idxs[UInt<6>("h026")], clk - node T_1814 = eq(T_1813, T_1697) - infer mport T_1816 = idxs[UInt<6>("h027")], clk - node T_1817 = eq(T_1816, T_1697) - infer mport T_1819 = idxs[UInt<6>("h028")], clk - node T_1820 = eq(T_1819, T_1697) - infer mport T_1822 = idxs[UInt<6>("h029")], clk - node T_1823 = eq(T_1822, T_1697) - infer mport T_1825 = idxs[UInt<6>("h02a")], clk - node T_1826 = eq(T_1825, T_1697) - infer mport T_1828 = idxs[UInt<6>("h02b")], clk - node T_1829 = eq(T_1828, T_1697) - infer mport T_1831 = idxs[UInt<6>("h02c")], clk - node T_1832 = eq(T_1831, T_1697) - infer mport T_1834 = idxs[UInt<6>("h02d")], clk - node T_1835 = eq(T_1834, T_1697) - infer mport T_1837 = idxs[UInt<6>("h02e")], clk - node T_1838 = eq(T_1837, T_1697) - infer mport T_1840 = idxs[UInt<6>("h02f")], clk - node T_1841 = eq(T_1840, T_1697) - infer mport T_1843 = idxs[UInt<6>("h030")], clk - node T_1844 = eq(T_1843, T_1697) - infer mport T_1846 = idxs[UInt<6>("h031")], clk - node T_1847 = eq(T_1846, T_1697) - infer mport T_1849 = idxs[UInt<6>("h032")], clk - node T_1850 = eq(T_1849, T_1697) - infer mport T_1852 = idxs[UInt<6>("h033")], clk - node T_1853 = eq(T_1852, T_1697) - infer mport T_1855 = idxs[UInt<6>("h034")], clk - node T_1856 = eq(T_1855, T_1697) - infer mport T_1858 = idxs[UInt<6>("h035")], clk - node T_1859 = eq(T_1858, T_1697) - infer mport T_1861 = idxs[UInt<6>("h036")], clk - node T_1862 = eq(T_1861, T_1697) - infer mport T_1864 = idxs[UInt<6>("h037")], clk - node T_1865 = eq(T_1864, T_1697) - infer mport T_1867 = idxs[UInt<6>("h038")], clk - node T_1868 = eq(T_1867, T_1697) - infer mport T_1870 = idxs[UInt<6>("h039")], clk - node T_1871 = eq(T_1870, T_1697) - infer mport T_1873 = idxs[UInt<6>("h03a")], clk - node T_1874 = eq(T_1873, T_1697) - infer mport T_1876 = idxs[UInt<6>("h03b")], clk - node T_1877 = eq(T_1876, T_1697) - infer mport T_1879 = idxs[UInt<6>("h03c")], clk - node T_1880 = eq(T_1879, T_1697) - infer mport T_1882 = idxs[UInt<6>("h03d")], clk - node T_1883 = eq(T_1882, T_1697) - wire T_1885 : UInt<1>[62] - T_1885[0] <= T_1700 - T_1885[1] <= T_1703 - T_1885[2] <= T_1706 - T_1885[3] <= T_1709 - T_1885[4] <= T_1712 - T_1885[5] <= T_1715 - T_1885[6] <= T_1718 - T_1885[7] <= T_1721 - T_1885[8] <= T_1724 - T_1885[9] <= T_1727 - T_1885[10] <= T_1730 - T_1885[11] <= T_1733 - T_1885[12] <= T_1736 - T_1885[13] <= T_1739 - T_1885[14] <= T_1742 - T_1885[15] <= T_1745 - T_1885[16] <= T_1748 - T_1885[17] <= T_1751 - T_1885[18] <= T_1754 - T_1885[19] <= T_1757 - T_1885[20] <= T_1760 - T_1885[21] <= T_1763 - T_1885[22] <= T_1766 - T_1885[23] <= T_1769 - T_1885[24] <= T_1772 - T_1885[25] <= T_1775 - T_1885[26] <= T_1778 - T_1885[27] <= T_1781 - T_1885[28] <= T_1784 - T_1885[29] <= T_1787 - T_1885[30] <= T_1790 - T_1885[31] <= T_1793 - T_1885[32] <= T_1796 - T_1885[33] <= T_1799 - T_1885[34] <= T_1802 - T_1885[35] <= T_1805 - T_1885[36] <= T_1808 - T_1885[37] <= T_1811 - T_1885[38] <= T_1814 - T_1885[39] <= T_1817 - T_1885[40] <= T_1820 - T_1885[41] <= T_1823 - T_1885[42] <= T_1826 - T_1885[43] <= T_1829 - T_1885[44] <= T_1832 - T_1885[45] <= T_1835 - T_1885[46] <= T_1838 - T_1885[47] <= T_1841 - T_1885[48] <= T_1844 - T_1885[49] <= T_1847 - T_1885[50] <= T_1850 - T_1885[51] <= T_1853 - T_1885[52] <= T_1856 - T_1885[53] <= T_1859 - T_1885[54] <= T_1862 - T_1885[55] <= T_1865 - T_1885[56] <= T_1868 - T_1885[57] <= T_1871 - T_1885[58] <= T_1874 - T_1885[59] <= T_1877 - T_1885[60] <= T_1880 - T_1885[61] <= T_1883 - node T_1949 = cat(T_1885[60], T_1885[59]) - node T_1950 = cat(T_1885[61], T_1949) - node T_1951 = cat(T_1885[58], T_1885[57]) - node T_1952 = cat(T_1885[56], T_1885[55]) - node T_1953 = cat(T_1951, T_1952) - node T_1954 = cat(T_1950, T_1953) - node T_1955 = cat(T_1885[54], T_1885[53]) - node T_1956 = cat(T_1885[52], T_1885[51]) - node T_1957 = cat(T_1955, T_1956) - node T_1958 = cat(T_1885[50], T_1885[49]) - node T_1959 = cat(T_1885[48], T_1885[47]) - node T_1960 = cat(T_1958, T_1959) - node T_1961 = cat(T_1957, T_1960) - node T_1962 = cat(T_1954, T_1961) - node T_1963 = cat(T_1885[46], T_1885[45]) - node T_1964 = cat(T_1885[44], T_1885[43]) - node T_1965 = cat(T_1963, T_1964) - node T_1966 = cat(T_1885[42], T_1885[41]) - node T_1967 = cat(T_1885[40], T_1885[39]) - node T_1968 = cat(T_1966, T_1967) - node T_1969 = cat(T_1965, T_1968) - node T_1970 = cat(T_1885[38], T_1885[37]) - node T_1971 = cat(T_1885[36], T_1885[35]) - node T_1972 = cat(T_1970, T_1971) - node T_1973 = cat(T_1885[34], T_1885[33]) - node T_1974 = cat(T_1885[32], T_1885[31]) - node T_1975 = cat(T_1973, T_1974) - node T_1976 = cat(T_1972, T_1975) - node T_1977 = cat(T_1969, T_1976) - node T_1978 = cat(T_1962, T_1977) - node T_1979 = cat(T_1885[29], T_1885[28]) - node T_1980 = cat(T_1885[30], T_1979) - node T_1981 = cat(T_1885[27], T_1885[26]) - node T_1982 = cat(T_1885[25], T_1885[24]) - node T_1983 = cat(T_1981, T_1982) - node T_1984 = cat(T_1980, T_1983) - node T_1985 = cat(T_1885[23], T_1885[22]) - node T_1986 = cat(T_1885[21], T_1885[20]) - node T_1987 = cat(T_1985, T_1986) - node T_1988 = cat(T_1885[19], T_1885[18]) - node T_1989 = cat(T_1885[17], T_1885[16]) - node T_1990 = cat(T_1988, T_1989) - node T_1991 = cat(T_1987, T_1990) - node T_1992 = cat(T_1984, T_1991) - node T_1993 = cat(T_1885[15], T_1885[14]) - node T_1994 = cat(T_1885[13], T_1885[12]) - node T_1995 = cat(T_1993, T_1994) - node T_1996 = cat(T_1885[11], T_1885[10]) - node T_1997 = cat(T_1885[9], T_1885[8]) - node T_1998 = cat(T_1996, T_1997) - node T_1999 = cat(T_1995, T_1998) - node T_2000 = cat(T_1885[7], T_1885[6]) - node T_2001 = cat(T_1885[5], T_1885[4]) - node T_2002 = cat(T_2000, T_2001) - node T_2003 = cat(T_1885[3], T_1885[2]) - node T_2004 = cat(T_1885[1], T_1885[0]) - node T_2005 = cat(T_2003, T_2004) - node T_2006 = cat(T_2002, T_2005) - node T_2007 = cat(T_1999, T_2006) - node T_2008 = cat(T_1992, T_2007) - node T_2009 = cat(T_1978, T_2008) - node T_2010 = and(T_593, pageHit) - node T_2011 = and(T_598, pageHit) - node T_2012 = and(T_603, pageHit) - node T_2013 = and(T_608, pageHit) - node T_2014 = and(T_613, pageHit) - node T_2015 = and(T_618, pageHit) - node T_2016 = and(T_623, pageHit) - node T_2017 = and(T_628, pageHit) - node T_2018 = and(T_633, pageHit) - node T_2019 = and(T_638, pageHit) - node T_2020 = and(T_643, pageHit) - node T_2021 = and(T_648, pageHit) - node T_2022 = and(T_653, pageHit) - node T_2023 = and(T_658, pageHit) - node T_2024 = and(T_663, pageHit) - node T_2025 = and(T_668, pageHit) - node T_2026 = and(T_673, pageHit) - node T_2027 = and(T_678, pageHit) - node T_2028 = and(T_683, pageHit) - node T_2029 = and(T_688, pageHit) - node T_2030 = and(T_693, pageHit) - node T_2031 = and(T_698, pageHit) - node T_2032 = and(T_703, pageHit) - node T_2033 = and(T_708, pageHit) - node T_2034 = and(T_713, pageHit) - node T_2035 = and(T_718, pageHit) - node T_2036 = and(T_723, pageHit) - node T_2037 = and(T_728, pageHit) - node T_2038 = and(T_733, pageHit) - node T_2039 = and(T_738, pageHit) - node T_2040 = and(T_743, pageHit) - node T_2041 = and(T_748, pageHit) - node T_2042 = and(T_753, pageHit) - node T_2043 = and(T_758, pageHit) - node T_2044 = and(T_763, pageHit) - node T_2045 = and(T_768, pageHit) - node T_2046 = and(T_773, pageHit) - node T_2047 = and(T_778, pageHit) - node T_2048 = and(T_783, pageHit) - node T_2049 = and(T_788, pageHit) - node T_2050 = and(T_793, pageHit) - node T_2051 = and(T_798, pageHit) - node T_2052 = and(T_803, pageHit) - node T_2053 = and(T_808, pageHit) - node T_2054 = and(T_813, pageHit) - node T_2055 = and(T_818, pageHit) - node T_2056 = and(T_823, pageHit) - node T_2057 = and(T_828, pageHit) - node T_2058 = and(T_833, pageHit) - node T_2059 = and(T_838, pageHit) - node T_2060 = and(T_843, pageHit) - node T_2061 = and(T_848, pageHit) - node T_2062 = and(T_853, pageHit) - node T_2063 = and(T_858, pageHit) - node T_2064 = and(T_863, pageHit) - node T_2065 = and(T_868, pageHit) - node T_2066 = and(T_873, pageHit) - node T_2067 = and(T_878, pageHit) - node T_2068 = and(T_883, pageHit) - node T_2069 = and(T_888, pageHit) - node T_2070 = and(T_893, pageHit) - node T_2071 = and(T_898, pageHit) - node T_2073 = neq(T_2010, UInt<1>("h00")) - node T_2075 = neq(T_2011, UInt<1>("h00")) - node T_2077 = neq(T_2012, UInt<1>("h00")) - node T_2079 = neq(T_2013, UInt<1>("h00")) - node T_2081 = neq(T_2014, UInt<1>("h00")) - node T_2083 = neq(T_2015, UInt<1>("h00")) - node T_2085 = neq(T_2016, UInt<1>("h00")) - node T_2087 = neq(T_2017, UInt<1>("h00")) - node T_2089 = neq(T_2018, UInt<1>("h00")) - node T_2091 = neq(T_2019, UInt<1>("h00")) - node T_2093 = neq(T_2020, UInt<1>("h00")) - node T_2095 = neq(T_2021, UInt<1>("h00")) - node T_2097 = neq(T_2022, UInt<1>("h00")) - node T_2099 = neq(T_2023, UInt<1>("h00")) - node T_2101 = neq(T_2024, UInt<1>("h00")) - node T_2103 = neq(T_2025, UInt<1>("h00")) - node T_2105 = neq(T_2026, UInt<1>("h00")) - node T_2107 = neq(T_2027, UInt<1>("h00")) - node T_2109 = neq(T_2028, UInt<1>("h00")) - node T_2111 = neq(T_2029, UInt<1>("h00")) - node T_2113 = neq(T_2030, UInt<1>("h00")) - node T_2115 = neq(T_2031, UInt<1>("h00")) - node T_2117 = neq(T_2032, UInt<1>("h00")) - node T_2119 = neq(T_2033, UInt<1>("h00")) - node T_2121 = neq(T_2034, UInt<1>("h00")) - node T_2123 = neq(T_2035, UInt<1>("h00")) - node T_2125 = neq(T_2036, UInt<1>("h00")) - node T_2127 = neq(T_2037, UInt<1>("h00")) - node T_2129 = neq(T_2038, UInt<1>("h00")) - node T_2131 = neq(T_2039, UInt<1>("h00")) - node T_2133 = neq(T_2040, UInt<1>("h00")) - node T_2135 = neq(T_2041, UInt<1>("h00")) - node T_2137 = neq(T_2042, UInt<1>("h00")) - node T_2139 = neq(T_2043, UInt<1>("h00")) - node T_2141 = neq(T_2044, UInt<1>("h00")) - node T_2143 = neq(T_2045, UInt<1>("h00")) - node T_2145 = neq(T_2046, UInt<1>("h00")) - node T_2147 = neq(T_2047, UInt<1>("h00")) - node T_2149 = neq(T_2048, UInt<1>("h00")) - node T_2151 = neq(T_2049, UInt<1>("h00")) - node T_2153 = neq(T_2050, UInt<1>("h00")) - node T_2155 = neq(T_2051, UInt<1>("h00")) - node T_2157 = neq(T_2052, UInt<1>("h00")) - node T_2159 = neq(T_2053, UInt<1>("h00")) - node T_2161 = neq(T_2054, UInt<1>("h00")) - node T_2163 = neq(T_2055, UInt<1>("h00")) - node T_2165 = neq(T_2056, UInt<1>("h00")) - node T_2167 = neq(T_2057, UInt<1>("h00")) - node T_2169 = neq(T_2058, UInt<1>("h00")) - node T_2171 = neq(T_2059, UInt<1>("h00")) - node T_2173 = neq(T_2060, UInt<1>("h00")) - node T_2175 = neq(T_2061, UInt<1>("h00")) - node T_2177 = neq(T_2062, UInt<1>("h00")) - node T_2179 = neq(T_2063, UInt<1>("h00")) - node T_2181 = neq(T_2064, UInt<1>("h00")) - node T_2183 = neq(T_2065, UInt<1>("h00")) - node T_2185 = neq(T_2066, UInt<1>("h00")) - node T_2187 = neq(T_2067, UInt<1>("h00")) - node T_2189 = neq(T_2068, UInt<1>("h00")) - node T_2191 = neq(T_2069, UInt<1>("h00")) - node T_2193 = neq(T_2070, UInt<1>("h00")) - node T_2195 = neq(T_2071, UInt<1>("h00")) - wire T_2197 : UInt<1>[62] - T_2197[0] <= T_2073 - T_2197[1] <= T_2075 - T_2197[2] <= T_2077 - T_2197[3] <= T_2079 - T_2197[4] <= T_2081 - T_2197[5] <= T_2083 - T_2197[6] <= T_2085 - T_2197[7] <= T_2087 - T_2197[8] <= T_2089 - T_2197[9] <= T_2091 - T_2197[10] <= T_2093 - T_2197[11] <= T_2095 - T_2197[12] <= T_2097 - T_2197[13] <= T_2099 - T_2197[14] <= T_2101 - T_2197[15] <= T_2103 - T_2197[16] <= T_2105 - T_2197[17] <= T_2107 - T_2197[18] <= T_2109 - T_2197[19] <= T_2111 - T_2197[20] <= T_2113 - T_2197[21] <= T_2115 - T_2197[22] <= T_2117 - T_2197[23] <= T_2119 - T_2197[24] <= T_2121 - T_2197[25] <= T_2123 - T_2197[26] <= T_2125 - T_2197[27] <= T_2127 - T_2197[28] <= T_2129 - T_2197[29] <= T_2131 - T_2197[30] <= T_2133 - T_2197[31] <= T_2135 - T_2197[32] <= T_2137 - T_2197[33] <= T_2139 - T_2197[34] <= T_2141 - T_2197[35] <= T_2143 - T_2197[36] <= T_2145 - T_2197[37] <= T_2147 - T_2197[38] <= T_2149 - T_2197[39] <= T_2151 - T_2197[40] <= T_2153 - T_2197[41] <= T_2155 - T_2197[42] <= T_2157 - T_2197[43] <= T_2159 - T_2197[44] <= T_2161 - T_2197[45] <= T_2163 - T_2197[46] <= T_2165 - T_2197[47] <= T_2167 - T_2197[48] <= T_2169 - T_2197[49] <= T_2171 - T_2197[50] <= T_2173 - T_2197[51] <= T_2175 - T_2197[52] <= T_2177 - T_2197[53] <= T_2179 - T_2197[54] <= T_2181 - T_2197[55] <= T_2183 - T_2197[56] <= T_2185 - T_2197[57] <= T_2187 - T_2197[58] <= T_2189 - T_2197[59] <= T_2191 - T_2197[60] <= T_2193 - T_2197[61] <= T_2195 - node T_2261 = cat(T_2197[60], T_2197[59]) - node T_2262 = cat(T_2197[61], T_2261) - node T_2263 = cat(T_2197[58], T_2197[57]) - node T_2264 = cat(T_2197[56], T_2197[55]) - node T_2265 = cat(T_2263, T_2264) - node T_2266 = cat(T_2262, T_2265) - node T_2267 = cat(T_2197[54], T_2197[53]) - node T_2268 = cat(T_2197[52], T_2197[51]) - node T_2269 = cat(T_2267, T_2268) - node T_2270 = cat(T_2197[50], T_2197[49]) - node T_2271 = cat(T_2197[48], T_2197[47]) - node T_2272 = cat(T_2270, T_2271) - node T_2273 = cat(T_2269, T_2272) - node T_2274 = cat(T_2266, T_2273) - node T_2275 = cat(T_2197[46], T_2197[45]) - node T_2276 = cat(T_2197[44], T_2197[43]) - node T_2277 = cat(T_2275, T_2276) - node T_2278 = cat(T_2197[42], T_2197[41]) - node T_2279 = cat(T_2197[40], T_2197[39]) - node T_2280 = cat(T_2278, T_2279) - node T_2281 = cat(T_2277, T_2280) - node T_2282 = cat(T_2197[38], T_2197[37]) - node T_2283 = cat(T_2197[36], T_2197[35]) - node T_2284 = cat(T_2282, T_2283) - node T_2285 = cat(T_2197[34], T_2197[33]) - node T_2286 = cat(T_2197[32], T_2197[31]) - node T_2287 = cat(T_2285, T_2286) - node T_2288 = cat(T_2284, T_2287) - node T_2289 = cat(T_2281, T_2288) - node T_2290 = cat(T_2274, T_2289) - node T_2291 = cat(T_2197[29], T_2197[28]) - node T_2292 = cat(T_2197[30], T_2291) - node T_2293 = cat(T_2197[27], T_2197[26]) - node T_2294 = cat(T_2197[25], T_2197[24]) - node T_2295 = cat(T_2293, T_2294) - node T_2296 = cat(T_2292, T_2295) - node T_2297 = cat(T_2197[23], T_2197[22]) - node T_2298 = cat(T_2197[21], T_2197[20]) - node T_2299 = cat(T_2297, T_2298) - node T_2300 = cat(T_2197[19], T_2197[18]) - node T_2301 = cat(T_2197[17], T_2197[16]) - node T_2302 = cat(T_2300, T_2301) - node T_2303 = cat(T_2299, T_2302) - node T_2304 = cat(T_2296, T_2303) - node T_2305 = cat(T_2197[15], T_2197[14]) - node T_2306 = cat(T_2197[13], T_2197[12]) - node T_2307 = cat(T_2305, T_2306) - node T_2308 = cat(T_2197[11], T_2197[10]) - node T_2309 = cat(T_2197[9], T_2197[8]) - node T_2310 = cat(T_2308, T_2309) - node T_2311 = cat(T_2307, T_2310) - node T_2312 = cat(T_2197[7], T_2197[6]) - node T_2313 = cat(T_2197[5], T_2197[4]) - node T_2314 = cat(T_2312, T_2313) - node T_2315 = cat(T_2197[3], T_2197[2]) - node T_2316 = cat(T_2197[1], T_2197[0]) - node T_2317 = cat(T_2315, T_2316) - node T_2318 = cat(T_2314, T_2317) - node T_2319 = cat(T_2311, T_2318) - node T_2320 = cat(T_2304, T_2319) - node T_2321 = cat(T_2290, T_2320) - node T_2322 = and(idxValid, T_2009) - node hits = and(T_2322, T_2321) - node T_2324 = shr(r_btb_update.bits.pc, 12) - infer mport T_2326 = pages[UInt<1>("h00")], clk - node T_2327 = eq(T_2326, T_2324) - infer mport T_2329 = pages[UInt<1>("h01")], clk - node T_2330 = eq(T_2329, T_2324) - infer mport T_2332 = pages[UInt<2>("h02")], clk - node T_2333 = eq(T_2332, T_2324) - infer mport T_2335 = pages[UInt<2>("h03")], clk - node T_2336 = eq(T_2335, T_2324) - infer mport T_2338 = pages[UInt<3>("h04")], clk - node T_2339 = eq(T_2338, T_2324) - infer mport T_2341 = pages[UInt<3>("h05")], clk - node T_2342 = eq(T_2341, T_2324) - wire T_2344 : UInt<1>[6] - T_2344[0] <= T_2327 - T_2344[1] <= T_2330 - T_2344[2] <= T_2333 - T_2344[3] <= T_2336 - T_2344[4] <= T_2339 - T_2344[5] <= T_2342 - node T_2352 = cat(T_2344[4], T_2344[3]) - node T_2353 = cat(T_2344[5], T_2352) - node T_2354 = cat(T_2344[1], T_2344[0]) - node T_2355 = cat(T_2344[2], T_2354) - node T_2356 = cat(T_2353, T_2355) - node updatePageHit = and(T_2356, pageValid) - node T_2358 = bits(r_btb_update.bits.pc, 11, 0) - infer mport T_2360 = idxs[UInt<1>("h00")], clk - node T_2361 = eq(T_2360, T_2358) - infer mport T_2363 = idxs[UInt<1>("h01")], clk - node T_2364 = eq(T_2363, T_2358) - infer mport T_2366 = idxs[UInt<2>("h02")], clk - node T_2367 = eq(T_2366, T_2358) - infer mport T_2369 = idxs[UInt<2>("h03")], clk - node T_2370 = eq(T_2369, T_2358) - infer mport T_2372 = idxs[UInt<3>("h04")], clk - node T_2373 = eq(T_2372, T_2358) - infer mport T_2375 = idxs[UInt<3>("h05")], clk - node T_2376 = eq(T_2375, T_2358) - infer mport T_2378 = idxs[UInt<3>("h06")], clk - node T_2379 = eq(T_2378, T_2358) - infer mport T_2381 = idxs[UInt<3>("h07")], clk - node T_2382 = eq(T_2381, T_2358) - infer mport T_2384 = idxs[UInt<4>("h08")], clk - node T_2385 = eq(T_2384, T_2358) - infer mport T_2387 = idxs[UInt<4>("h09")], clk - node T_2388 = eq(T_2387, T_2358) - infer mport T_2390 = idxs[UInt<4>("h0a")], clk - node T_2391 = eq(T_2390, T_2358) - infer mport T_2393 = idxs[UInt<4>("h0b")], clk - node T_2394 = eq(T_2393, T_2358) - infer mport T_2396 = idxs[UInt<4>("h0c")], clk - node T_2397 = eq(T_2396, T_2358) - infer mport T_2399 = idxs[UInt<4>("h0d")], clk - node T_2400 = eq(T_2399, T_2358) - infer mport T_2402 = idxs[UInt<4>("h0e")], clk - node T_2403 = eq(T_2402, T_2358) - infer mport T_2405 = idxs[UInt<4>("h0f")], clk - node T_2406 = eq(T_2405, T_2358) - infer mport T_2408 = idxs[UInt<5>("h010")], clk - node T_2409 = eq(T_2408, T_2358) - infer mport T_2411 = idxs[UInt<5>("h011")], clk - node T_2412 = eq(T_2411, T_2358) - infer mport T_2414 = idxs[UInt<5>("h012")], clk - node T_2415 = eq(T_2414, T_2358) - infer mport T_2417 = idxs[UInt<5>("h013")], clk - node T_2418 = eq(T_2417, T_2358) - infer mport T_2420 = idxs[UInt<5>("h014")], clk - node T_2421 = eq(T_2420, T_2358) - infer mport T_2423 = idxs[UInt<5>("h015")], clk - node T_2424 = eq(T_2423, T_2358) - infer mport T_2426 = idxs[UInt<5>("h016")], clk - node T_2427 = eq(T_2426, T_2358) - infer mport T_2429 = idxs[UInt<5>("h017")], clk - node T_2430 = eq(T_2429, T_2358) - infer mport T_2432 = idxs[UInt<5>("h018")], clk - node T_2433 = eq(T_2432, T_2358) - infer mport T_2435 = idxs[UInt<5>("h019")], clk - node T_2436 = eq(T_2435, T_2358) - infer mport T_2438 = idxs[UInt<5>("h01a")], clk - node T_2439 = eq(T_2438, T_2358) - infer mport T_2441 = idxs[UInt<5>("h01b")], clk - node T_2442 = eq(T_2441, T_2358) - infer mport T_2444 = idxs[UInt<5>("h01c")], clk - node T_2445 = eq(T_2444, T_2358) - infer mport T_2447 = idxs[UInt<5>("h01d")], clk - node T_2448 = eq(T_2447, T_2358) - infer mport T_2450 = idxs[UInt<5>("h01e")], clk - node T_2451 = eq(T_2450, T_2358) - infer mport T_2453 = idxs[UInt<5>("h01f")], clk - node T_2454 = eq(T_2453, T_2358) - infer mport T_2456 = idxs[UInt<6>("h020")], clk - node T_2457 = eq(T_2456, T_2358) - infer mport T_2459 = idxs[UInt<6>("h021")], clk - node T_2460 = eq(T_2459, T_2358) - infer mport T_2462 = idxs[UInt<6>("h022")], clk - node T_2463 = eq(T_2462, T_2358) - infer mport T_2465 = idxs[UInt<6>("h023")], clk - node T_2466 = eq(T_2465, T_2358) - infer mport T_2468 = idxs[UInt<6>("h024")], clk - node T_2469 = eq(T_2468, T_2358) - infer mport T_2471 = idxs[UInt<6>("h025")], clk - node T_2472 = eq(T_2471, T_2358) - infer mport T_2474 = idxs[UInt<6>("h026")], clk - node T_2475 = eq(T_2474, T_2358) - infer mport T_2477 = idxs[UInt<6>("h027")], clk - node T_2478 = eq(T_2477, T_2358) - infer mport T_2480 = idxs[UInt<6>("h028")], clk - node T_2481 = eq(T_2480, T_2358) - infer mport T_2483 = idxs[UInt<6>("h029")], clk - node T_2484 = eq(T_2483, T_2358) - infer mport T_2486 = idxs[UInt<6>("h02a")], clk - node T_2487 = eq(T_2486, T_2358) - infer mport T_2489 = idxs[UInt<6>("h02b")], clk - node T_2490 = eq(T_2489, T_2358) - infer mport T_2492 = idxs[UInt<6>("h02c")], clk - node T_2493 = eq(T_2492, T_2358) - infer mport T_2495 = idxs[UInt<6>("h02d")], clk - node T_2496 = eq(T_2495, T_2358) - infer mport T_2498 = idxs[UInt<6>("h02e")], clk - node T_2499 = eq(T_2498, T_2358) - infer mport T_2501 = idxs[UInt<6>("h02f")], clk - node T_2502 = eq(T_2501, T_2358) - infer mport T_2504 = idxs[UInt<6>("h030")], clk - node T_2505 = eq(T_2504, T_2358) - infer mport T_2507 = idxs[UInt<6>("h031")], clk - node T_2508 = eq(T_2507, T_2358) - infer mport T_2510 = idxs[UInt<6>("h032")], clk - node T_2511 = eq(T_2510, T_2358) - infer mport T_2513 = idxs[UInt<6>("h033")], clk - node T_2514 = eq(T_2513, T_2358) - infer mport T_2516 = idxs[UInt<6>("h034")], clk - node T_2517 = eq(T_2516, T_2358) - infer mport T_2519 = idxs[UInt<6>("h035")], clk - node T_2520 = eq(T_2519, T_2358) - infer mport T_2522 = idxs[UInt<6>("h036")], clk - node T_2523 = eq(T_2522, T_2358) - infer mport T_2525 = idxs[UInt<6>("h037")], clk - node T_2526 = eq(T_2525, T_2358) - infer mport T_2528 = idxs[UInt<6>("h038")], clk - node T_2529 = eq(T_2528, T_2358) - infer mport T_2531 = idxs[UInt<6>("h039")], clk - node T_2532 = eq(T_2531, T_2358) - infer mport T_2534 = idxs[UInt<6>("h03a")], clk - node T_2535 = eq(T_2534, T_2358) - infer mport T_2537 = idxs[UInt<6>("h03b")], clk - node T_2538 = eq(T_2537, T_2358) - infer mport T_2540 = idxs[UInt<6>("h03c")], clk - node T_2541 = eq(T_2540, T_2358) - infer mport T_2543 = idxs[UInt<6>("h03d")], clk - node T_2544 = eq(T_2543, T_2358) - wire T_2546 : UInt<1>[62] - T_2546[0] <= T_2361 - T_2546[1] <= T_2364 - T_2546[2] <= T_2367 - T_2546[3] <= T_2370 - T_2546[4] <= T_2373 - T_2546[5] <= T_2376 - T_2546[6] <= T_2379 - T_2546[7] <= T_2382 - T_2546[8] <= T_2385 - T_2546[9] <= T_2388 - T_2546[10] <= T_2391 - T_2546[11] <= T_2394 - T_2546[12] <= T_2397 - T_2546[13] <= T_2400 - T_2546[14] <= T_2403 - T_2546[15] <= T_2406 - T_2546[16] <= T_2409 - T_2546[17] <= T_2412 - T_2546[18] <= T_2415 - T_2546[19] <= T_2418 - T_2546[20] <= T_2421 - T_2546[21] <= T_2424 - T_2546[22] <= T_2427 - T_2546[23] <= T_2430 - T_2546[24] <= T_2433 - T_2546[25] <= T_2436 - T_2546[26] <= T_2439 - T_2546[27] <= T_2442 - T_2546[28] <= T_2445 - T_2546[29] <= T_2448 - T_2546[30] <= T_2451 - T_2546[31] <= T_2454 - T_2546[32] <= T_2457 - T_2546[33] <= T_2460 - T_2546[34] <= T_2463 - T_2546[35] <= T_2466 - T_2546[36] <= T_2469 - T_2546[37] <= T_2472 - T_2546[38] <= T_2475 - T_2546[39] <= T_2478 - T_2546[40] <= T_2481 - T_2546[41] <= T_2484 - T_2546[42] <= T_2487 - T_2546[43] <= T_2490 - T_2546[44] <= T_2493 - T_2546[45] <= T_2496 - T_2546[46] <= T_2499 - T_2546[47] <= T_2502 - T_2546[48] <= T_2505 - T_2546[49] <= T_2508 - T_2546[50] <= T_2511 - T_2546[51] <= T_2514 - T_2546[52] <= T_2517 - T_2546[53] <= T_2520 - T_2546[54] <= T_2523 - T_2546[55] <= T_2526 - T_2546[56] <= T_2529 - T_2546[57] <= T_2532 - T_2546[58] <= T_2535 - T_2546[59] <= T_2538 - T_2546[60] <= T_2541 - T_2546[61] <= T_2544 - node T_2610 = cat(T_2546[60], T_2546[59]) - node T_2611 = cat(T_2546[61], T_2610) - node T_2612 = cat(T_2546[58], T_2546[57]) - node T_2613 = cat(T_2546[56], T_2546[55]) - node T_2614 = cat(T_2612, T_2613) - node T_2615 = cat(T_2611, T_2614) - node T_2616 = cat(T_2546[54], T_2546[53]) - node T_2617 = cat(T_2546[52], T_2546[51]) - node T_2618 = cat(T_2616, T_2617) - node T_2619 = cat(T_2546[50], T_2546[49]) - node T_2620 = cat(T_2546[48], T_2546[47]) - node T_2621 = cat(T_2619, T_2620) - node T_2622 = cat(T_2618, T_2621) - node T_2623 = cat(T_2615, T_2622) - node T_2624 = cat(T_2546[46], T_2546[45]) - node T_2625 = cat(T_2546[44], T_2546[43]) - node T_2626 = cat(T_2624, T_2625) - node T_2627 = cat(T_2546[42], T_2546[41]) - node T_2628 = cat(T_2546[40], T_2546[39]) - node T_2629 = cat(T_2627, T_2628) - node T_2630 = cat(T_2626, T_2629) - node T_2631 = cat(T_2546[38], T_2546[37]) - node T_2632 = cat(T_2546[36], T_2546[35]) - node T_2633 = cat(T_2631, T_2632) - node T_2634 = cat(T_2546[34], T_2546[33]) - node T_2635 = cat(T_2546[32], T_2546[31]) - node T_2636 = cat(T_2634, T_2635) - node T_2637 = cat(T_2633, T_2636) - node T_2638 = cat(T_2630, T_2637) - node T_2639 = cat(T_2623, T_2638) - node T_2640 = cat(T_2546[29], T_2546[28]) - node T_2641 = cat(T_2546[30], T_2640) - node T_2642 = cat(T_2546[27], T_2546[26]) - node T_2643 = cat(T_2546[25], T_2546[24]) - node T_2644 = cat(T_2642, T_2643) - node T_2645 = cat(T_2641, T_2644) - node T_2646 = cat(T_2546[23], T_2546[22]) - node T_2647 = cat(T_2546[21], T_2546[20]) - node T_2648 = cat(T_2646, T_2647) - node T_2649 = cat(T_2546[19], T_2546[18]) - node T_2650 = cat(T_2546[17], T_2546[16]) - node T_2651 = cat(T_2649, T_2650) - node T_2652 = cat(T_2648, T_2651) - node T_2653 = cat(T_2645, T_2652) - node T_2654 = cat(T_2546[15], T_2546[14]) - node T_2655 = cat(T_2546[13], T_2546[12]) - node T_2656 = cat(T_2654, T_2655) - node T_2657 = cat(T_2546[11], T_2546[10]) - node T_2658 = cat(T_2546[9], T_2546[8]) - node T_2659 = cat(T_2657, T_2658) - node T_2660 = cat(T_2656, T_2659) - node T_2661 = cat(T_2546[7], T_2546[6]) - node T_2662 = cat(T_2546[5], T_2546[4]) - node T_2663 = cat(T_2661, T_2662) - node T_2664 = cat(T_2546[3], T_2546[2]) - node T_2665 = cat(T_2546[1], T_2546[0]) - node T_2666 = cat(T_2664, T_2665) - node T_2667 = cat(T_2663, T_2666) - node T_2668 = cat(T_2660, T_2667) - node T_2669 = cat(T_2653, T_2668) - node T_2670 = cat(T_2639, T_2669) - node T_2671 = and(T_593, updatePageHit) - node T_2672 = and(T_598, updatePageHit) - node T_2673 = and(T_603, updatePageHit) - node T_2674 = and(T_608, updatePageHit) - node T_2675 = and(T_613, updatePageHit) - node T_2676 = and(T_618, updatePageHit) - node T_2677 = and(T_623, updatePageHit) - node T_2678 = and(T_628, updatePageHit) - node T_2679 = and(T_633, updatePageHit) - node T_2680 = and(T_638, updatePageHit) - node T_2681 = and(T_643, updatePageHit) - node T_2682 = and(T_648, updatePageHit) - node T_2683 = and(T_653, updatePageHit) - node T_2684 = and(T_658, updatePageHit) - node T_2685 = and(T_663, updatePageHit) - node T_2686 = and(T_668, updatePageHit) - node T_2687 = and(T_673, updatePageHit) - node T_2688 = and(T_678, updatePageHit) - node T_2689 = and(T_683, updatePageHit) - node T_2690 = and(T_688, updatePageHit) - node T_2691 = and(T_693, updatePageHit) - node T_2692 = and(T_698, updatePageHit) - node T_2693 = and(T_703, updatePageHit) - node T_2694 = and(T_708, updatePageHit) - node T_2695 = and(T_713, updatePageHit) - node T_2696 = and(T_718, updatePageHit) - node T_2697 = and(T_723, updatePageHit) - node T_2698 = and(T_728, updatePageHit) - node T_2699 = and(T_733, updatePageHit) - node T_2700 = and(T_738, updatePageHit) - node T_2701 = and(T_743, updatePageHit) - node T_2702 = and(T_748, updatePageHit) - node T_2703 = and(T_753, updatePageHit) - node T_2704 = and(T_758, updatePageHit) - node T_2705 = and(T_763, updatePageHit) - node T_2706 = and(T_768, updatePageHit) - node T_2707 = and(T_773, updatePageHit) - node T_2708 = and(T_778, updatePageHit) - node T_2709 = and(T_783, updatePageHit) - node T_2710 = and(T_788, updatePageHit) - node T_2711 = and(T_793, updatePageHit) - node T_2712 = and(T_798, updatePageHit) - node T_2713 = and(T_803, updatePageHit) - node T_2714 = and(T_808, updatePageHit) - node T_2715 = and(T_813, updatePageHit) - node T_2716 = and(T_818, updatePageHit) - node T_2717 = and(T_823, updatePageHit) - node T_2718 = and(T_828, updatePageHit) - node T_2719 = and(T_833, updatePageHit) - node T_2720 = and(T_838, updatePageHit) - node T_2721 = and(T_843, updatePageHit) - node T_2722 = and(T_848, updatePageHit) - node T_2723 = and(T_853, updatePageHit) - node T_2724 = and(T_858, updatePageHit) - node T_2725 = and(T_863, updatePageHit) - node T_2726 = and(T_868, updatePageHit) - node T_2727 = and(T_873, updatePageHit) - node T_2728 = and(T_878, updatePageHit) - node T_2729 = and(T_883, updatePageHit) - node T_2730 = and(T_888, updatePageHit) - node T_2731 = and(T_893, updatePageHit) - node T_2732 = and(T_898, updatePageHit) - node T_2734 = neq(T_2671, UInt<1>("h00")) - node T_2736 = neq(T_2672, UInt<1>("h00")) - node T_2738 = neq(T_2673, UInt<1>("h00")) - node T_2740 = neq(T_2674, UInt<1>("h00")) - node T_2742 = neq(T_2675, UInt<1>("h00")) - node T_2744 = neq(T_2676, UInt<1>("h00")) - node T_2746 = neq(T_2677, UInt<1>("h00")) - node T_2748 = neq(T_2678, UInt<1>("h00")) - node T_2750 = neq(T_2679, UInt<1>("h00")) - node T_2752 = neq(T_2680, UInt<1>("h00")) - node T_2754 = neq(T_2681, UInt<1>("h00")) - node T_2756 = neq(T_2682, UInt<1>("h00")) - node T_2758 = neq(T_2683, UInt<1>("h00")) - node T_2760 = neq(T_2684, UInt<1>("h00")) - node T_2762 = neq(T_2685, UInt<1>("h00")) - node T_2764 = neq(T_2686, UInt<1>("h00")) - node T_2766 = neq(T_2687, UInt<1>("h00")) - node T_2768 = neq(T_2688, UInt<1>("h00")) - node T_2770 = neq(T_2689, UInt<1>("h00")) - node T_2772 = neq(T_2690, UInt<1>("h00")) - node T_2774 = neq(T_2691, UInt<1>("h00")) - node T_2776 = neq(T_2692, UInt<1>("h00")) - node T_2778 = neq(T_2693, UInt<1>("h00")) - node T_2780 = neq(T_2694, UInt<1>("h00")) - node T_2782 = neq(T_2695, UInt<1>("h00")) - node T_2784 = neq(T_2696, UInt<1>("h00")) - node T_2786 = neq(T_2697, UInt<1>("h00")) - node T_2788 = neq(T_2698, UInt<1>("h00")) - node T_2790 = neq(T_2699, UInt<1>("h00")) - node T_2792 = neq(T_2700, UInt<1>("h00")) - node T_2794 = neq(T_2701, UInt<1>("h00")) - node T_2796 = neq(T_2702, UInt<1>("h00")) - node T_2798 = neq(T_2703, UInt<1>("h00")) - node T_2800 = neq(T_2704, UInt<1>("h00")) - node T_2802 = neq(T_2705, UInt<1>("h00")) - node T_2804 = neq(T_2706, UInt<1>("h00")) - node T_2806 = neq(T_2707, UInt<1>("h00")) - node T_2808 = neq(T_2708, UInt<1>("h00")) - node T_2810 = neq(T_2709, UInt<1>("h00")) - node T_2812 = neq(T_2710, UInt<1>("h00")) - node T_2814 = neq(T_2711, UInt<1>("h00")) - node T_2816 = neq(T_2712, UInt<1>("h00")) - node T_2818 = neq(T_2713, UInt<1>("h00")) - node T_2820 = neq(T_2714, UInt<1>("h00")) - node T_2822 = neq(T_2715, UInt<1>("h00")) - node T_2824 = neq(T_2716, UInt<1>("h00")) - node T_2826 = neq(T_2717, UInt<1>("h00")) - node T_2828 = neq(T_2718, UInt<1>("h00")) - node T_2830 = neq(T_2719, UInt<1>("h00")) - node T_2832 = neq(T_2720, UInt<1>("h00")) - node T_2834 = neq(T_2721, UInt<1>("h00")) - node T_2836 = neq(T_2722, UInt<1>("h00")) - node T_2838 = neq(T_2723, UInt<1>("h00")) - node T_2840 = neq(T_2724, UInt<1>("h00")) - node T_2842 = neq(T_2725, UInt<1>("h00")) - node T_2844 = neq(T_2726, UInt<1>("h00")) - node T_2846 = neq(T_2727, UInt<1>("h00")) - node T_2848 = neq(T_2728, UInt<1>("h00")) - node T_2850 = neq(T_2729, UInt<1>("h00")) - node T_2852 = neq(T_2730, UInt<1>("h00")) - node T_2854 = neq(T_2731, UInt<1>("h00")) - node T_2856 = neq(T_2732, UInt<1>("h00")) - wire T_2858 : UInt<1>[62] - T_2858[0] <= T_2734 - T_2858[1] <= T_2736 - T_2858[2] <= T_2738 - T_2858[3] <= T_2740 - T_2858[4] <= T_2742 - T_2858[5] <= T_2744 - T_2858[6] <= T_2746 - T_2858[7] <= T_2748 - T_2858[8] <= T_2750 - T_2858[9] <= T_2752 - T_2858[10] <= T_2754 - T_2858[11] <= T_2756 - T_2858[12] <= T_2758 - T_2858[13] <= T_2760 - T_2858[14] <= T_2762 - T_2858[15] <= T_2764 - T_2858[16] <= T_2766 - T_2858[17] <= T_2768 - T_2858[18] <= T_2770 - T_2858[19] <= T_2772 - T_2858[20] <= T_2774 - T_2858[21] <= T_2776 - T_2858[22] <= T_2778 - T_2858[23] <= T_2780 - T_2858[24] <= T_2782 - T_2858[25] <= T_2784 - T_2858[26] <= T_2786 - T_2858[27] <= T_2788 - T_2858[28] <= T_2790 - T_2858[29] <= T_2792 - T_2858[30] <= T_2794 - T_2858[31] <= T_2796 - T_2858[32] <= T_2798 - T_2858[33] <= T_2800 - T_2858[34] <= T_2802 - T_2858[35] <= T_2804 - T_2858[36] <= T_2806 - T_2858[37] <= T_2808 - T_2858[38] <= T_2810 - T_2858[39] <= T_2812 - T_2858[40] <= T_2814 - T_2858[41] <= T_2816 - T_2858[42] <= T_2818 - T_2858[43] <= T_2820 - T_2858[44] <= T_2822 - T_2858[45] <= T_2824 - T_2858[46] <= T_2826 - T_2858[47] <= T_2828 - T_2858[48] <= T_2830 - T_2858[49] <= T_2832 - T_2858[50] <= T_2834 - T_2858[51] <= T_2836 - T_2858[52] <= T_2838 - T_2858[53] <= T_2840 - T_2858[54] <= T_2842 - T_2858[55] <= T_2844 - T_2858[56] <= T_2846 - T_2858[57] <= T_2848 - T_2858[58] <= T_2850 - T_2858[59] <= T_2852 - T_2858[60] <= T_2854 - T_2858[61] <= T_2856 - node T_2922 = cat(T_2858[60], T_2858[59]) - node T_2923 = cat(T_2858[61], T_2922) - node T_2924 = cat(T_2858[58], T_2858[57]) - node T_2925 = cat(T_2858[56], T_2858[55]) - node T_2926 = cat(T_2924, T_2925) - node T_2927 = cat(T_2923, T_2926) - node T_2928 = cat(T_2858[54], T_2858[53]) - node T_2929 = cat(T_2858[52], T_2858[51]) - node T_2930 = cat(T_2928, T_2929) - node T_2931 = cat(T_2858[50], T_2858[49]) - node T_2932 = cat(T_2858[48], T_2858[47]) - node T_2933 = cat(T_2931, T_2932) - node T_2934 = cat(T_2930, T_2933) - node T_2935 = cat(T_2927, T_2934) - node T_2936 = cat(T_2858[46], T_2858[45]) - node T_2937 = cat(T_2858[44], T_2858[43]) - node T_2938 = cat(T_2936, T_2937) - node T_2939 = cat(T_2858[42], T_2858[41]) - node T_2940 = cat(T_2858[40], T_2858[39]) - node T_2941 = cat(T_2939, T_2940) - node T_2942 = cat(T_2938, T_2941) - node T_2943 = cat(T_2858[38], T_2858[37]) - node T_2944 = cat(T_2858[36], T_2858[35]) - node T_2945 = cat(T_2943, T_2944) - node T_2946 = cat(T_2858[34], T_2858[33]) - node T_2947 = cat(T_2858[32], T_2858[31]) - node T_2948 = cat(T_2946, T_2947) - node T_2949 = cat(T_2945, T_2948) - node T_2950 = cat(T_2942, T_2949) - node T_2951 = cat(T_2935, T_2950) - node T_2952 = cat(T_2858[29], T_2858[28]) - node T_2953 = cat(T_2858[30], T_2952) - node T_2954 = cat(T_2858[27], T_2858[26]) - node T_2955 = cat(T_2858[25], T_2858[24]) - node T_2956 = cat(T_2954, T_2955) - node T_2957 = cat(T_2953, T_2956) - node T_2958 = cat(T_2858[23], T_2858[22]) - node T_2959 = cat(T_2858[21], T_2858[20]) - node T_2960 = cat(T_2958, T_2959) - node T_2961 = cat(T_2858[19], T_2858[18]) - node T_2962 = cat(T_2858[17], T_2858[16]) - node T_2963 = cat(T_2961, T_2962) - node T_2964 = cat(T_2960, T_2963) - node T_2965 = cat(T_2957, T_2964) - node T_2966 = cat(T_2858[15], T_2858[14]) - node T_2967 = cat(T_2858[13], T_2858[12]) - node T_2968 = cat(T_2966, T_2967) - node T_2969 = cat(T_2858[11], T_2858[10]) - node T_2970 = cat(T_2858[9], T_2858[8]) - node T_2971 = cat(T_2969, T_2970) - node T_2972 = cat(T_2968, T_2971) - node T_2973 = cat(T_2858[7], T_2858[6]) - node T_2974 = cat(T_2858[5], T_2858[4]) - node T_2975 = cat(T_2973, T_2974) - node T_2976 = cat(T_2858[3], T_2858[2]) - node T_2977 = cat(T_2858[1], T_2858[0]) - node T_2978 = cat(T_2976, T_2977) - node T_2979 = cat(T_2975, T_2978) - node T_2980 = cat(T_2972, T_2979) - node T_2981 = cat(T_2965, T_2980) - node T_2982 = cat(T_2951, T_2981) - node T_2983 = and(idxValid, T_2670) - node updateHits = and(T_2983, T_2982) - reg T_2986 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) - when r_btb_update.valid : - node T_2987 = bits(T_2986, 0, 0) - node T_2988 = bits(T_2986, 2, 2) - node T_2989 = xor(T_2987, T_2988) - node T_2990 = bits(T_2986, 3, 3) - node T_2991 = xor(T_2989, T_2990) - node T_2992 = bits(T_2986, 5, 5) - node T_2993 = xor(T_2991, T_2992) - node T_2994 = bits(T_2986, 15, 1) - node T_2995 = cat(T_2993, T_2994) - T_2986 <= T_2995 - skip - node T_2997 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) - node T_2998 = and(r_btb_update.valid, T_2997) - reg nextRepl : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - when T_2998 : - node T_3002 = eq(nextRepl, UInt<6>("h03d")) - node T_3004 = and(UInt<1>("h01"), T_3002) - node T_3007 = add(nextRepl, UInt<1>("h01")) - node T_3008 = tail(T_3007, 1) - node T_3009 = mux(T_3004, UInt<1>("h00"), T_3008) - nextRepl <= T_3009 - skip - node T_3010 = and(T_2998, T_3002) - node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) - node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) - wire idxPageRepl : UInt<6> - idxPageRepl is invalid - node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) - node T_3018 = bits(idxPageUpdateOH, 5, 4) - node T_3019 = bits(idxPageUpdateOH, 3, 0) - node T_3021 = neq(T_3018, UInt<1>("h00")) - node T_3022 = or(T_3018, T_3019) - node T_3023 = bits(T_3022, 3, 2) - node T_3024 = bits(T_3022, 1, 0) - node T_3026 = neq(T_3023, UInt<1>("h00")) - node T_3027 = or(T_3023, T_3024) - node T_3028 = bits(T_3027, 1, 1) - node T_3029 = cat(T_3026, T_3028) - node idxPageUpdate = cat(T_3021, T_3029) - node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) - node T_3033 = shr(r_btb_update.bits.pc, 12) - node T_3034 = shr(io.req.bits.addr, 12) - node samePage = eq(T_3033, T_3034) - node T_3036 = not(idxPageReplEn) - node T_3037 = and(pageHit, T_3036) - node usePageHit = neq(T_3037, UInt<1>("h00")) - node T_3041 = eq(samePage, UInt<1>("h00")) - node T_3043 = eq(usePageHit, UInt<1>("h00")) - node doTgtPageRepl = and(T_3041, T_3043) - node T_3045 = bits(idxPageUpdateOH, 4, 0) - node T_3046 = shl(T_3045, 1) - node T_3047 = bits(idxPageUpdateOH, 5, 5) - node T_3048 = or(T_3046, T_3047) - node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048) - node T_3050 = mux(usePageHit, pageHit, tgtPageRepl) - node T_3051 = bits(T_3050, 5, 4) - node T_3052 = bits(T_3050, 3, 0) - node T_3054 = neq(T_3051, UInt<1>("h00")) - node T_3055 = or(T_3051, T_3052) - node T_3056 = bits(T_3055, 3, 2) - node T_3057 = bits(T_3055, 1, 0) - node T_3059 = neq(T_3056, UInt<1>("h00")) - node T_3060 = or(T_3056, T_3057) - node T_3061 = bits(T_3060, 1, 1) - node T_3062 = cat(T_3059, T_3061) - node tgtPageUpdate = cat(T_3054, T_3062) - node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) - node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) - node pageReplEn = or(idxPageReplEn, tgtPageReplEn) - node T_3068 = and(r_btb_update.valid, doPageRepl) - reg T_3070 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3068 : - node T_3072 = eq(T_3070, UInt<3>("h05")) - node T_3074 = and(UInt<1>("h01"), T_3072) - node T_3077 = add(T_3070, UInt<1>("h01")) - node T_3078 = tail(T_3077, 1) - node T_3079 = mux(T_3074, UInt<1>("h00"), T_3078) - T_3070 <= T_3079 - skip - node T_3080 = and(T_3068, T_3072) - node T_3082 = dshl(UInt<1>("h01"), T_3070) - idxPageRepl <= T_3082 - when r_btb_update.valid : - node T_3083 = eq(io.req.bits.addr, r_btb_update.bits.target) - node T_3085 = eq(reset, UInt<1>("h00")) - when T_3085 : - node T_3087 = eq(T_3083, UInt<1>("h00")) - when T_3087 : - node T_3089 = eq(reset, UInt<1>("h00")) - when T_3089 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): BTB request != I$ target") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_3090 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) - node T_3091 = or(T_593, T_903) - node T_3092 = and(pageReplEn, T_3091) - node T_3094 = neq(T_3092, UInt<1>("h00")) - node T_3095 = or(T_598, T_908) - node T_3096 = and(pageReplEn, T_3095) - node T_3098 = neq(T_3096, UInt<1>("h00")) - node T_3099 = or(T_603, T_913) - node T_3100 = and(pageReplEn, T_3099) - node T_3102 = neq(T_3100, UInt<1>("h00")) - node T_3103 = or(T_608, T_918) - node T_3104 = and(pageReplEn, T_3103) - node T_3106 = neq(T_3104, UInt<1>("h00")) - node T_3107 = or(T_613, T_923) - node T_3108 = and(pageReplEn, T_3107) - node T_3110 = neq(T_3108, UInt<1>("h00")) - node T_3111 = or(T_618, T_928) - node T_3112 = and(pageReplEn, T_3111) - node T_3114 = neq(T_3112, UInt<1>("h00")) - node T_3115 = or(T_623, T_933) - node T_3116 = and(pageReplEn, T_3115) - node T_3118 = neq(T_3116, UInt<1>("h00")) - node T_3119 = or(T_628, T_938) - node T_3120 = and(pageReplEn, T_3119) - node T_3122 = neq(T_3120, UInt<1>("h00")) - node T_3123 = or(T_633, T_943) - node T_3124 = and(pageReplEn, T_3123) - node T_3126 = neq(T_3124, UInt<1>("h00")) - node T_3127 = or(T_638, T_948) - node T_3128 = and(pageReplEn, T_3127) - node T_3130 = neq(T_3128, UInt<1>("h00")) - node T_3131 = or(T_643, T_953) - node T_3132 = and(pageReplEn, T_3131) - node T_3134 = neq(T_3132, UInt<1>("h00")) - node T_3135 = or(T_648, T_958) - node T_3136 = and(pageReplEn, T_3135) - node T_3138 = neq(T_3136, UInt<1>("h00")) - node T_3139 = or(T_653, T_963) - node T_3140 = and(pageReplEn, T_3139) - node T_3142 = neq(T_3140, UInt<1>("h00")) - node T_3143 = or(T_658, T_968) - node T_3144 = and(pageReplEn, T_3143) - node T_3146 = neq(T_3144, UInt<1>("h00")) - node T_3147 = or(T_663, T_973) - node T_3148 = and(pageReplEn, T_3147) - node T_3150 = neq(T_3148, UInt<1>("h00")) - node T_3151 = or(T_668, T_978) - node T_3152 = and(pageReplEn, T_3151) - node T_3154 = neq(T_3152, UInt<1>("h00")) - node T_3155 = or(T_673, T_983) - node T_3156 = and(pageReplEn, T_3155) - node T_3158 = neq(T_3156, UInt<1>("h00")) - node T_3159 = or(T_678, T_988) - node T_3160 = and(pageReplEn, T_3159) - node T_3162 = neq(T_3160, UInt<1>("h00")) - node T_3163 = or(T_683, T_993) - node T_3164 = and(pageReplEn, T_3163) - node T_3166 = neq(T_3164, UInt<1>("h00")) - node T_3167 = or(T_688, T_998) - node T_3168 = and(pageReplEn, T_3167) - node T_3170 = neq(T_3168, UInt<1>("h00")) - node T_3171 = or(T_693, T_1003) - node T_3172 = and(pageReplEn, T_3171) - node T_3174 = neq(T_3172, UInt<1>("h00")) - node T_3175 = or(T_698, T_1008) - node T_3176 = and(pageReplEn, T_3175) - node T_3178 = neq(T_3176, UInt<1>("h00")) - node T_3179 = or(T_703, T_1013) - node T_3180 = and(pageReplEn, T_3179) - node T_3182 = neq(T_3180, UInt<1>("h00")) - node T_3183 = or(T_708, T_1018) - node T_3184 = and(pageReplEn, T_3183) - node T_3186 = neq(T_3184, UInt<1>("h00")) - node T_3187 = or(T_713, T_1023) - node T_3188 = and(pageReplEn, T_3187) - node T_3190 = neq(T_3188, UInt<1>("h00")) - node T_3191 = or(T_718, T_1028) - node T_3192 = and(pageReplEn, T_3191) - node T_3194 = neq(T_3192, UInt<1>("h00")) - node T_3195 = or(T_723, T_1033) - node T_3196 = and(pageReplEn, T_3195) - node T_3198 = neq(T_3196, UInt<1>("h00")) - node T_3199 = or(T_728, T_1038) - node T_3200 = and(pageReplEn, T_3199) - node T_3202 = neq(T_3200, UInt<1>("h00")) - node T_3203 = or(T_733, T_1043) - node T_3204 = and(pageReplEn, T_3203) - node T_3206 = neq(T_3204, UInt<1>("h00")) - node T_3207 = or(T_738, T_1048) - node T_3208 = and(pageReplEn, T_3207) - node T_3210 = neq(T_3208, UInt<1>("h00")) - node T_3211 = or(T_743, T_1053) - node T_3212 = and(pageReplEn, T_3211) - node T_3214 = neq(T_3212, UInt<1>("h00")) - node T_3215 = or(T_748, T_1058) - node T_3216 = and(pageReplEn, T_3215) - node T_3218 = neq(T_3216, UInt<1>("h00")) - node T_3219 = or(T_753, T_1063) - node T_3220 = and(pageReplEn, T_3219) - node T_3222 = neq(T_3220, UInt<1>("h00")) - node T_3223 = or(T_758, T_1068) - node T_3224 = and(pageReplEn, T_3223) - node T_3226 = neq(T_3224, UInt<1>("h00")) - node T_3227 = or(T_763, T_1073) - node T_3228 = and(pageReplEn, T_3227) - node T_3230 = neq(T_3228, UInt<1>("h00")) - node T_3231 = or(T_768, T_1078) - node T_3232 = and(pageReplEn, T_3231) - node T_3234 = neq(T_3232, UInt<1>("h00")) - node T_3235 = or(T_773, T_1083) - node T_3236 = and(pageReplEn, T_3235) - node T_3238 = neq(T_3236, UInt<1>("h00")) - node T_3239 = or(T_778, T_1088) - node T_3240 = and(pageReplEn, T_3239) - node T_3242 = neq(T_3240, UInt<1>("h00")) - node T_3243 = or(T_783, T_1093) - node T_3244 = and(pageReplEn, T_3243) - node T_3246 = neq(T_3244, UInt<1>("h00")) - node T_3247 = or(T_788, T_1098) - node T_3248 = and(pageReplEn, T_3247) - node T_3250 = neq(T_3248, UInt<1>("h00")) - node T_3251 = or(T_793, T_1103) - node T_3252 = and(pageReplEn, T_3251) - node T_3254 = neq(T_3252, UInt<1>("h00")) - node T_3255 = or(T_798, T_1108) - node T_3256 = and(pageReplEn, T_3255) - node T_3258 = neq(T_3256, UInt<1>("h00")) - node T_3259 = or(T_803, T_1113) - node T_3260 = and(pageReplEn, T_3259) - node T_3262 = neq(T_3260, UInt<1>("h00")) - node T_3263 = or(T_808, T_1118) - node T_3264 = and(pageReplEn, T_3263) - node T_3266 = neq(T_3264, UInt<1>("h00")) - node T_3267 = or(T_813, T_1123) - node T_3268 = and(pageReplEn, T_3267) - node T_3270 = neq(T_3268, UInt<1>("h00")) - node T_3271 = or(T_818, T_1128) - node T_3272 = and(pageReplEn, T_3271) - node T_3274 = neq(T_3272, UInt<1>("h00")) - node T_3275 = or(T_823, T_1133) - node T_3276 = and(pageReplEn, T_3275) - node T_3278 = neq(T_3276, UInt<1>("h00")) - node T_3279 = or(T_828, T_1138) - node T_3280 = and(pageReplEn, T_3279) - node T_3282 = neq(T_3280, UInt<1>("h00")) - node T_3283 = or(T_833, T_1143) - node T_3284 = and(pageReplEn, T_3283) - node T_3286 = neq(T_3284, UInt<1>("h00")) - node T_3287 = or(T_838, T_1148) - node T_3288 = and(pageReplEn, T_3287) - node T_3290 = neq(T_3288, UInt<1>("h00")) - node T_3291 = or(T_843, T_1153) - node T_3292 = and(pageReplEn, T_3291) - node T_3294 = neq(T_3292, UInt<1>("h00")) - node T_3295 = or(T_848, T_1158) - node T_3296 = and(pageReplEn, T_3295) - node T_3298 = neq(T_3296, UInt<1>("h00")) - node T_3299 = or(T_853, T_1163) - node T_3300 = and(pageReplEn, T_3299) - node T_3302 = neq(T_3300, UInt<1>("h00")) - node T_3303 = or(T_858, T_1168) - node T_3304 = and(pageReplEn, T_3303) - node T_3306 = neq(T_3304, UInt<1>("h00")) - node T_3307 = or(T_863, T_1173) - node T_3308 = and(pageReplEn, T_3307) - node T_3310 = neq(T_3308, UInt<1>("h00")) - node T_3311 = or(T_868, T_1178) - node T_3312 = and(pageReplEn, T_3311) - node T_3314 = neq(T_3312, UInt<1>("h00")) - node T_3315 = or(T_873, T_1183) - node T_3316 = and(pageReplEn, T_3315) - node T_3318 = neq(T_3316, UInt<1>("h00")) - node T_3319 = or(T_878, T_1188) - node T_3320 = and(pageReplEn, T_3319) - node T_3322 = neq(T_3320, UInt<1>("h00")) - node T_3323 = or(T_883, T_1193) - node T_3324 = and(pageReplEn, T_3323) - node T_3326 = neq(T_3324, UInt<1>("h00")) - node T_3327 = or(T_888, T_1198) - node T_3328 = and(pageReplEn, T_3327) - node T_3330 = neq(T_3328, UInt<1>("h00")) - node T_3331 = or(T_893, T_1203) - node T_3332 = and(pageReplEn, T_3331) - node T_3334 = neq(T_3332, UInt<1>("h00")) - node T_3335 = or(T_898, T_1208) - node T_3336 = and(pageReplEn, T_3335) - node T_3338 = neq(T_3336, UInt<1>("h00")) - wire T_3340 : UInt<1>[62] - T_3340[0] <= T_3094 - T_3340[1] <= T_3098 - T_3340[2] <= T_3102 - T_3340[3] <= T_3106 - T_3340[4] <= T_3110 - T_3340[5] <= T_3114 - T_3340[6] <= T_3118 - T_3340[7] <= T_3122 - T_3340[8] <= T_3126 - T_3340[9] <= T_3130 - T_3340[10] <= T_3134 - T_3340[11] <= T_3138 - T_3340[12] <= T_3142 - T_3340[13] <= T_3146 - T_3340[14] <= T_3150 - T_3340[15] <= T_3154 - T_3340[16] <= T_3158 - T_3340[17] <= T_3162 - T_3340[18] <= T_3166 - T_3340[19] <= T_3170 - T_3340[20] <= T_3174 - T_3340[21] <= T_3178 - T_3340[22] <= T_3182 - T_3340[23] <= T_3186 - T_3340[24] <= T_3190 - T_3340[25] <= T_3194 - T_3340[26] <= T_3198 - T_3340[27] <= T_3202 - T_3340[28] <= T_3206 - T_3340[29] <= T_3210 - T_3340[30] <= T_3214 - T_3340[31] <= T_3218 - T_3340[32] <= T_3222 - T_3340[33] <= T_3226 - T_3340[34] <= T_3230 - T_3340[35] <= T_3234 - T_3340[36] <= T_3238 - T_3340[37] <= T_3242 - T_3340[38] <= T_3246 - T_3340[39] <= T_3250 - T_3340[40] <= T_3254 - T_3340[41] <= T_3258 - T_3340[42] <= T_3262 - T_3340[43] <= T_3266 - T_3340[44] <= T_3270 - T_3340[45] <= T_3274 - T_3340[46] <= T_3278 - T_3340[47] <= T_3282 - T_3340[48] <= T_3286 - T_3340[49] <= T_3290 - T_3340[50] <= T_3294 - T_3340[51] <= T_3298 - T_3340[52] <= T_3302 - T_3340[53] <= T_3306 - T_3340[54] <= T_3310 - T_3340[55] <= T_3314 - T_3340[56] <= T_3318 - T_3340[57] <= T_3322 - T_3340[58] <= T_3326 - T_3340[59] <= T_3330 - T_3340[60] <= T_3334 - T_3340[61] <= T_3338 - node T_3404 = cat(T_3340[60], T_3340[59]) - node T_3405 = cat(T_3340[61], T_3404) - node T_3406 = cat(T_3340[58], T_3340[57]) - node T_3407 = cat(T_3340[56], T_3340[55]) - node T_3408 = cat(T_3406, T_3407) - node T_3409 = cat(T_3405, T_3408) - node T_3410 = cat(T_3340[54], T_3340[53]) - node T_3411 = cat(T_3340[52], T_3340[51]) - node T_3412 = cat(T_3410, T_3411) - node T_3413 = cat(T_3340[50], T_3340[49]) - node T_3414 = cat(T_3340[48], T_3340[47]) - node T_3415 = cat(T_3413, T_3414) - node T_3416 = cat(T_3412, T_3415) - node T_3417 = cat(T_3409, T_3416) - node T_3418 = cat(T_3340[46], T_3340[45]) - node T_3419 = cat(T_3340[44], T_3340[43]) - node T_3420 = cat(T_3418, T_3419) - node T_3421 = cat(T_3340[42], T_3340[41]) - node T_3422 = cat(T_3340[40], T_3340[39]) - node T_3423 = cat(T_3421, T_3422) - node T_3424 = cat(T_3420, T_3423) - node T_3425 = cat(T_3340[38], T_3340[37]) - node T_3426 = cat(T_3340[36], T_3340[35]) - node T_3427 = cat(T_3425, T_3426) - node T_3428 = cat(T_3340[34], T_3340[33]) - node T_3429 = cat(T_3340[32], T_3340[31]) - node T_3430 = cat(T_3428, T_3429) - node T_3431 = cat(T_3427, T_3430) - node T_3432 = cat(T_3424, T_3431) - node T_3433 = cat(T_3417, T_3432) - node T_3434 = cat(T_3340[29], T_3340[28]) - node T_3435 = cat(T_3340[30], T_3434) - node T_3436 = cat(T_3340[27], T_3340[26]) - node T_3437 = cat(T_3340[25], T_3340[24]) - node T_3438 = cat(T_3436, T_3437) - node T_3439 = cat(T_3435, T_3438) - node T_3440 = cat(T_3340[23], T_3340[22]) - node T_3441 = cat(T_3340[21], T_3340[20]) - node T_3442 = cat(T_3440, T_3441) - node T_3443 = cat(T_3340[19], T_3340[18]) - node T_3444 = cat(T_3340[17], T_3340[16]) - node T_3445 = cat(T_3443, T_3444) - node T_3446 = cat(T_3442, T_3445) - node T_3447 = cat(T_3439, T_3446) - node T_3448 = cat(T_3340[15], T_3340[14]) - node T_3449 = cat(T_3340[13], T_3340[12]) - node T_3450 = cat(T_3448, T_3449) - node T_3451 = cat(T_3340[11], T_3340[10]) - node T_3452 = cat(T_3340[9], T_3340[8]) - node T_3453 = cat(T_3451, T_3452) - node T_3454 = cat(T_3450, T_3453) - node T_3455 = cat(T_3340[7], T_3340[6]) - node T_3456 = cat(T_3340[5], T_3340[4]) - node T_3457 = cat(T_3455, T_3456) - node T_3458 = cat(T_3340[3], T_3340[2]) - node T_3459 = cat(T_3340[1], T_3340[0]) - node T_3460 = cat(T_3458, T_3459) - node T_3461 = cat(T_3457, T_3460) - node T_3462 = cat(T_3454, T_3461) - node T_3463 = cat(T_3447, T_3462) - node T_3464 = cat(T_3433, T_3463) - node T_3466 = dshl(UInt<1>("h01"), T_3090) - node T_3467 = not(T_3464) - node T_3468 = and(idxValid, T_3467) - node T_3469 = or(T_3468, T_3466) - idxValid <= T_3469 - infer mport T_3470 = idxs[T_3090], clk - T_3470 <= r_btb_update.bits.pc - infer mport T_3471 = tgts[T_3090], clk - T_3471 <= io.req.bits.addr - infer mport T_3472 = idxPages[T_3090], clk - T_3472 <= idxPageUpdate - infer mport T_3473 = tgtPages[T_3090], clk - T_3473 <= tgtPageUpdate - useRAS[T_3090] <= r_btb_update.bits.isReturn - isJump[T_3090] <= r_btb_update.bits.isJump - infer mport T_3476 = brIdx[T_3090], clk - T_3476 <= UInt<1>("h00") - node T_3479 = cat(UInt<2>("h01"), UInt<2>("h01")) - node T_3480 = cat(UInt<2>("h01"), T_3479) - node T_3481 = and(idxPageUpdateOH, T_3480) - node T_3483 = neq(T_3481, UInt<1>("h00")) - node T_3484 = mux(T_3483, doIdxPageRepl, doTgtPageRepl) - node T_3485 = shr(r_btb_update.bits.pc, 12) - node T_3486 = shr(io.req.bits.addr, 12) - node T_3487 = mux(T_3483, T_3485, T_3486) - node T_3488 = bits(pageReplEn, 0, 0) - node T_3489 = and(T_3484, T_3488) - when T_3489 : - infer mport T_3491 = pages[UInt<1>("h00")], clk - T_3491 <= T_3487 - skip - node T_3492 = bits(pageReplEn, 2, 2) - node T_3493 = and(T_3484, T_3492) - when T_3493 : - infer mport T_3495 = pages[UInt<2>("h02")], clk - T_3495 <= T_3487 - skip - node T_3496 = bits(pageReplEn, 4, 4) - node T_3497 = and(T_3484, T_3496) - when T_3497 : - infer mport T_3499 = pages[UInt<3>("h04")], clk - T_3499 <= T_3487 - skip - node T_3500 = mux(T_3483, doTgtPageRepl, doIdxPageRepl) - node T_3501 = shr(io.req.bits.addr, 12) - node T_3502 = shr(r_btb_update.bits.pc, 12) - node T_3503 = mux(T_3483, T_3501, T_3502) - node T_3504 = bits(pageReplEn, 1, 1) - node T_3505 = and(T_3500, T_3504) - when T_3505 : - infer mport T_3507 = pages[UInt<1>("h01")], clk - T_3507 <= T_3503 - skip - node T_3508 = bits(pageReplEn, 3, 3) - node T_3509 = and(T_3500, T_3508) - when T_3509 : - infer mport T_3511 = pages[UInt<2>("h03")], clk - T_3511 <= T_3503 - skip - node T_3512 = bits(pageReplEn, 5, 5) - node T_3513 = and(T_3500, T_3512) - when T_3513 : - infer mport T_3515 = pages[UInt<3>("h05")], clk - T_3515 <= T_3503 - skip - when doPageRepl : - node T_3516 = or(pageValid, pageReplEn) - pageValid <= T_3516 - skip - skip - when io.invalidate : - idxValid <= UInt<1>("h00") - pageValid <= UInt<1>("h00") - skip - node T_3520 = neq(hits, UInt<1>("h00")) - io.resp.valid <= T_3520 - io.resp.bits.taken <= io.resp.valid - node T_3521 = bits(hits, 0, 0) - node T_3522 = bits(hits, 1, 1) - node T_3523 = bits(hits, 2, 2) - node T_3524 = bits(hits, 3, 3) - node T_3525 = bits(hits, 4, 4) - node T_3526 = bits(hits, 5, 5) - node T_3527 = bits(hits, 6, 6) - node T_3528 = bits(hits, 7, 7) - node T_3529 = bits(hits, 8, 8) - node T_3530 = bits(hits, 9, 9) - node T_3531 = bits(hits, 10, 10) - node T_3532 = bits(hits, 11, 11) - node T_3533 = bits(hits, 12, 12) - node T_3534 = bits(hits, 13, 13) - node T_3535 = bits(hits, 14, 14) - node T_3536 = bits(hits, 15, 15) - node T_3537 = bits(hits, 16, 16) - node T_3538 = bits(hits, 17, 17) - node T_3539 = bits(hits, 18, 18) - node T_3540 = bits(hits, 19, 19) - node T_3541 = bits(hits, 20, 20) - node T_3542 = bits(hits, 21, 21) - node T_3543 = bits(hits, 22, 22) - node T_3544 = bits(hits, 23, 23) - node T_3545 = bits(hits, 24, 24) - node T_3546 = bits(hits, 25, 25) - node T_3547 = bits(hits, 26, 26) - node T_3548 = bits(hits, 27, 27) - node T_3549 = bits(hits, 28, 28) - node T_3550 = bits(hits, 29, 29) - node T_3551 = bits(hits, 30, 30) - node T_3552 = bits(hits, 31, 31) - node T_3553 = bits(hits, 32, 32) - node T_3554 = bits(hits, 33, 33) - node T_3555 = bits(hits, 34, 34) - node T_3556 = bits(hits, 35, 35) - node T_3557 = bits(hits, 36, 36) - node T_3558 = bits(hits, 37, 37) - node T_3559 = bits(hits, 38, 38) - node T_3560 = bits(hits, 39, 39) - node T_3561 = bits(hits, 40, 40) - node T_3562 = bits(hits, 41, 41) - node T_3563 = bits(hits, 42, 42) - node T_3564 = bits(hits, 43, 43) - node T_3565 = bits(hits, 44, 44) - node T_3566 = bits(hits, 45, 45) - node T_3567 = bits(hits, 46, 46) - node T_3568 = bits(hits, 47, 47) - node T_3569 = bits(hits, 48, 48) - node T_3570 = bits(hits, 49, 49) - node T_3571 = bits(hits, 50, 50) - node T_3572 = bits(hits, 51, 51) - node T_3573 = bits(hits, 52, 52) - node T_3574 = bits(hits, 53, 53) - node T_3575 = bits(hits, 54, 54) - node T_3576 = bits(hits, 55, 55) - node T_3577 = bits(hits, 56, 56) - node T_3578 = bits(hits, 57, 57) - node T_3579 = bits(hits, 58, 58) - node T_3580 = bits(hits, 59, 59) - node T_3581 = bits(hits, 60, 60) - node T_3582 = bits(hits, 61, 61) - node T_3584 = mux(T_3521, T_903, UInt<1>("h00")) - node T_3586 = mux(T_3522, T_908, UInt<1>("h00")) - node T_3588 = mux(T_3523, T_913, UInt<1>("h00")) - node T_3590 = mux(T_3524, T_918, UInt<1>("h00")) - node T_3592 = mux(T_3525, T_923, UInt<1>("h00")) - node T_3594 = mux(T_3526, T_928, UInt<1>("h00")) - node T_3596 = mux(T_3527, T_933, UInt<1>("h00")) - node T_3598 = mux(T_3528, T_938, UInt<1>("h00")) - node T_3600 = mux(T_3529, T_943, UInt<1>("h00")) - node T_3602 = mux(T_3530, T_948, UInt<1>("h00")) - node T_3604 = mux(T_3531, T_953, UInt<1>("h00")) - node T_3606 = mux(T_3532, T_958, UInt<1>("h00")) - node T_3608 = mux(T_3533, T_963, UInt<1>("h00")) - node T_3610 = mux(T_3534, T_968, UInt<1>("h00")) - node T_3612 = mux(T_3535, T_973, UInt<1>("h00")) - node T_3614 = mux(T_3536, T_978, UInt<1>("h00")) - node T_3616 = mux(T_3537, T_983, UInt<1>("h00")) - node T_3618 = mux(T_3538, T_988, UInt<1>("h00")) - node T_3620 = mux(T_3539, T_993, UInt<1>("h00")) - node T_3622 = mux(T_3540, T_998, UInt<1>("h00")) - node T_3624 = mux(T_3541, T_1003, UInt<1>("h00")) - node T_3626 = mux(T_3542, T_1008, UInt<1>("h00")) - node T_3628 = mux(T_3543, T_1013, UInt<1>("h00")) - node T_3630 = mux(T_3544, T_1018, UInt<1>("h00")) - node T_3632 = mux(T_3545, T_1023, UInt<1>("h00")) - node T_3634 = mux(T_3546, T_1028, UInt<1>("h00")) - node T_3636 = mux(T_3547, T_1033, UInt<1>("h00")) - node T_3638 = mux(T_3548, T_1038, UInt<1>("h00")) - node T_3640 = mux(T_3549, T_1043, UInt<1>("h00")) - node T_3642 = mux(T_3550, T_1048, UInt<1>("h00")) - node T_3644 = mux(T_3551, T_1053, UInt<1>("h00")) - node T_3646 = mux(T_3552, T_1058, UInt<1>("h00")) - node T_3648 = mux(T_3553, T_1063, UInt<1>("h00")) - node T_3650 = mux(T_3554, T_1068, UInt<1>("h00")) - node T_3652 = mux(T_3555, T_1073, UInt<1>("h00")) - node T_3654 = mux(T_3556, T_1078, UInt<1>("h00")) - node T_3656 = mux(T_3557, T_1083, UInt<1>("h00")) - node T_3658 = mux(T_3558, T_1088, UInt<1>("h00")) - node T_3660 = mux(T_3559, T_1093, UInt<1>("h00")) - node T_3662 = mux(T_3560, T_1098, UInt<1>("h00")) - node T_3664 = mux(T_3561, T_1103, UInt<1>("h00")) - node T_3666 = mux(T_3562, T_1108, UInt<1>("h00")) - node T_3668 = mux(T_3563, T_1113, UInt<1>("h00")) - node T_3670 = mux(T_3564, T_1118, UInt<1>("h00")) - node T_3672 = mux(T_3565, T_1123, UInt<1>("h00")) - node T_3674 = mux(T_3566, T_1128, UInt<1>("h00")) - node T_3676 = mux(T_3567, T_1133, UInt<1>("h00")) - node T_3678 = mux(T_3568, T_1138, UInt<1>("h00")) - node T_3680 = mux(T_3569, T_1143, UInt<1>("h00")) - node T_3682 = mux(T_3570, T_1148, UInt<1>("h00")) - node T_3684 = mux(T_3571, T_1153, UInt<1>("h00")) - node T_3686 = mux(T_3572, T_1158, UInt<1>("h00")) - node T_3688 = mux(T_3573, T_1163, UInt<1>("h00")) - node T_3690 = mux(T_3574, T_1168, UInt<1>("h00")) - node T_3692 = mux(T_3575, T_1173, UInt<1>("h00")) - node T_3694 = mux(T_3576, T_1178, UInt<1>("h00")) - node T_3696 = mux(T_3577, T_1183, UInt<1>("h00")) - node T_3698 = mux(T_3578, T_1188, UInt<1>("h00")) - node T_3700 = mux(T_3579, T_1193, UInt<1>("h00")) - node T_3702 = mux(T_3580, T_1198, UInt<1>("h00")) - node T_3704 = mux(T_3581, T_1203, UInt<1>("h00")) - node T_3706 = mux(T_3582, T_1208, UInt<1>("h00")) - node T_3708 = or(T_3584, T_3586) - node T_3709 = or(T_3708, T_3588) - node T_3710 = or(T_3709, T_3590) - node T_3711 = or(T_3710, T_3592) - node T_3712 = or(T_3711, T_3594) - node T_3713 = or(T_3712, T_3596) - node T_3714 = or(T_3713, T_3598) - node T_3715 = or(T_3714, T_3600) - node T_3716 = or(T_3715, T_3602) - node T_3717 = or(T_3716, T_3604) - node T_3718 = or(T_3717, T_3606) - node T_3719 = or(T_3718, T_3608) - node T_3720 = or(T_3719, T_3610) - node T_3721 = or(T_3720, T_3612) - node T_3722 = or(T_3721, T_3614) - node T_3723 = or(T_3722, T_3616) - node T_3724 = or(T_3723, T_3618) - node T_3725 = or(T_3724, T_3620) - node T_3726 = or(T_3725, T_3622) - node T_3727 = or(T_3726, T_3624) - node T_3728 = or(T_3727, T_3626) - node T_3729 = or(T_3728, T_3628) - node T_3730 = or(T_3729, T_3630) - node T_3731 = or(T_3730, T_3632) - node T_3732 = or(T_3731, T_3634) - node T_3733 = or(T_3732, T_3636) - node T_3734 = or(T_3733, T_3638) - node T_3735 = or(T_3734, T_3640) - node T_3736 = or(T_3735, T_3642) - node T_3737 = or(T_3736, T_3644) - node T_3738 = or(T_3737, T_3646) - node T_3739 = or(T_3738, T_3648) - node T_3740 = or(T_3739, T_3650) - node T_3741 = or(T_3740, T_3652) - node T_3742 = or(T_3741, T_3654) - node T_3743 = or(T_3742, T_3656) - node T_3744 = or(T_3743, T_3658) - node T_3745 = or(T_3744, T_3660) - node T_3746 = or(T_3745, T_3662) - node T_3747 = or(T_3746, T_3664) - node T_3748 = or(T_3747, T_3666) - node T_3749 = or(T_3748, T_3668) - node T_3750 = or(T_3749, T_3670) - node T_3751 = or(T_3750, T_3672) - node T_3752 = or(T_3751, T_3674) - node T_3753 = or(T_3752, T_3676) - node T_3754 = or(T_3753, T_3678) - node T_3755 = or(T_3754, T_3680) - node T_3756 = or(T_3755, T_3682) - node T_3757 = or(T_3756, T_3684) - node T_3758 = or(T_3757, T_3686) - node T_3759 = or(T_3758, T_3688) - node T_3760 = or(T_3759, T_3690) - node T_3761 = or(T_3760, T_3692) - node T_3762 = or(T_3761, T_3694) - node T_3763 = or(T_3762, T_3696) - node T_3764 = or(T_3763, T_3698) - node T_3765 = or(T_3764, T_3700) - node T_3766 = or(T_3765, T_3702) - node T_3767 = or(T_3766, T_3704) - node T_3768 = or(T_3767, T_3706) - wire T_3769 : UInt<6> - T_3769 is invalid - T_3769 <= T_3768 - node T_3770 = bits(T_3769, 0, 0) - node T_3771 = bits(T_3769, 1, 1) - node T_3772 = bits(T_3769, 2, 2) - node T_3773 = bits(T_3769, 3, 3) - node T_3774 = bits(T_3769, 4, 4) - node T_3775 = bits(T_3769, 5, 5) - infer mport T_3777 = pages[UInt<1>("h00")], clk - infer mport T_3779 = pages[UInt<1>("h01")], clk - infer mport T_3781 = pages[UInt<2>("h02")], clk - infer mport T_3783 = pages[UInt<2>("h03")], clk - infer mport T_3785 = pages[UInt<3>("h04")], clk - infer mport T_3787 = pages[UInt<3>("h05")], clk - node T_3789 = mux(T_3770, T_3777, UInt<1>("h00")) - node T_3791 = mux(T_3771, T_3779, UInt<1>("h00")) - node T_3793 = mux(T_3772, T_3781, UInt<1>("h00")) - node T_3795 = mux(T_3773, T_3783, UInt<1>("h00")) - node T_3797 = mux(T_3774, T_3785, UInt<1>("h00")) - node T_3799 = mux(T_3775, T_3787, UInt<1>("h00")) - node T_3801 = or(T_3789, T_3791) - node T_3802 = or(T_3801, T_3793) - node T_3803 = or(T_3802, T_3795) - node T_3804 = or(T_3803, T_3797) - node T_3805 = or(T_3804, T_3799) - wire T_3806 : UInt<27> - T_3806 is invalid - T_3806 <= T_3805 - node T_3807 = bits(hits, 0, 0) - node T_3808 = bits(hits, 1, 1) - node T_3809 = bits(hits, 2, 2) - node T_3810 = bits(hits, 3, 3) - node T_3811 = bits(hits, 4, 4) - node T_3812 = bits(hits, 5, 5) - node T_3813 = bits(hits, 6, 6) - node T_3814 = bits(hits, 7, 7) - node T_3815 = bits(hits, 8, 8) - node T_3816 = bits(hits, 9, 9) - node T_3817 = bits(hits, 10, 10) - node T_3818 = bits(hits, 11, 11) - node T_3819 = bits(hits, 12, 12) - node T_3820 = bits(hits, 13, 13) - node T_3821 = bits(hits, 14, 14) - node T_3822 = bits(hits, 15, 15) - node T_3823 = bits(hits, 16, 16) - node T_3824 = bits(hits, 17, 17) - node T_3825 = bits(hits, 18, 18) - node T_3826 = bits(hits, 19, 19) - node T_3827 = bits(hits, 20, 20) - node T_3828 = bits(hits, 21, 21) - node T_3829 = bits(hits, 22, 22) - node T_3830 = bits(hits, 23, 23) - node T_3831 = bits(hits, 24, 24) - node T_3832 = bits(hits, 25, 25) - node T_3833 = bits(hits, 26, 26) - node T_3834 = bits(hits, 27, 27) - node T_3835 = bits(hits, 28, 28) - node T_3836 = bits(hits, 29, 29) - node T_3837 = bits(hits, 30, 30) - node T_3838 = bits(hits, 31, 31) - node T_3839 = bits(hits, 32, 32) - node T_3840 = bits(hits, 33, 33) - node T_3841 = bits(hits, 34, 34) - node T_3842 = bits(hits, 35, 35) - node T_3843 = bits(hits, 36, 36) - node T_3844 = bits(hits, 37, 37) - node T_3845 = bits(hits, 38, 38) - node T_3846 = bits(hits, 39, 39) - node T_3847 = bits(hits, 40, 40) - node T_3848 = bits(hits, 41, 41) - node T_3849 = bits(hits, 42, 42) - node T_3850 = bits(hits, 43, 43) - node T_3851 = bits(hits, 44, 44) - node T_3852 = bits(hits, 45, 45) - node T_3853 = bits(hits, 46, 46) - node T_3854 = bits(hits, 47, 47) - node T_3855 = bits(hits, 48, 48) - node T_3856 = bits(hits, 49, 49) - node T_3857 = bits(hits, 50, 50) - node T_3858 = bits(hits, 51, 51) - node T_3859 = bits(hits, 52, 52) - node T_3860 = bits(hits, 53, 53) - node T_3861 = bits(hits, 54, 54) - node T_3862 = bits(hits, 55, 55) - node T_3863 = bits(hits, 56, 56) - node T_3864 = bits(hits, 57, 57) - node T_3865 = bits(hits, 58, 58) - node T_3866 = bits(hits, 59, 59) - node T_3867 = bits(hits, 60, 60) - node T_3868 = bits(hits, 61, 61) - infer mport T_3870 = tgts[UInt<1>("h00")], clk - infer mport T_3872 = tgts[UInt<1>("h01")], clk - infer mport T_3874 = tgts[UInt<2>("h02")], clk - infer mport T_3876 = tgts[UInt<2>("h03")], clk - infer mport T_3878 = tgts[UInt<3>("h04")], clk - infer mport T_3880 = tgts[UInt<3>("h05")], clk - infer mport T_3882 = tgts[UInt<3>("h06")], clk - infer mport T_3884 = tgts[UInt<3>("h07")], clk - infer mport T_3886 = tgts[UInt<4>("h08")], clk - infer mport T_3888 = tgts[UInt<4>("h09")], clk - infer mport T_3890 = tgts[UInt<4>("h0a")], clk - infer mport T_3892 = tgts[UInt<4>("h0b")], clk - infer mport T_3894 = tgts[UInt<4>("h0c")], clk - infer mport T_3896 = tgts[UInt<4>("h0d")], clk - infer mport T_3898 = tgts[UInt<4>("h0e")], clk - infer mport T_3900 = tgts[UInt<4>("h0f")], clk - infer mport T_3902 = tgts[UInt<5>("h010")], clk - infer mport T_3904 = tgts[UInt<5>("h011")], clk - infer mport T_3906 = tgts[UInt<5>("h012")], clk - infer mport T_3908 = tgts[UInt<5>("h013")], clk - infer mport T_3910 = tgts[UInt<5>("h014")], clk - infer mport T_3912 = tgts[UInt<5>("h015")], clk - infer mport T_3914 = tgts[UInt<5>("h016")], clk - infer mport T_3916 = tgts[UInt<5>("h017")], clk - infer mport T_3918 = tgts[UInt<5>("h018")], clk - infer mport T_3920 = tgts[UInt<5>("h019")], clk - infer mport T_3922 = tgts[UInt<5>("h01a")], clk - infer mport T_3924 = tgts[UInt<5>("h01b")], clk - infer mport T_3926 = tgts[UInt<5>("h01c")], clk - infer mport T_3928 = tgts[UInt<5>("h01d")], clk - infer mport T_3930 = tgts[UInt<5>("h01e")], clk - infer mport T_3932 = tgts[UInt<5>("h01f")], clk - infer mport T_3934 = tgts[UInt<6>("h020")], clk - infer mport T_3936 = tgts[UInt<6>("h021")], clk - infer mport T_3938 = tgts[UInt<6>("h022")], clk - infer mport T_3940 = tgts[UInt<6>("h023")], clk - infer mport T_3942 = tgts[UInt<6>("h024")], clk - infer mport T_3944 = tgts[UInt<6>("h025")], clk - infer mport T_3946 = tgts[UInt<6>("h026")], clk - infer mport T_3948 = tgts[UInt<6>("h027")], clk - infer mport T_3950 = tgts[UInt<6>("h028")], clk - infer mport T_3952 = tgts[UInt<6>("h029")], clk - infer mport T_3954 = tgts[UInt<6>("h02a")], clk - infer mport T_3956 = tgts[UInt<6>("h02b")], clk - infer mport T_3958 = tgts[UInt<6>("h02c")], clk - infer mport T_3960 = tgts[UInt<6>("h02d")], clk - infer mport T_3962 = tgts[UInt<6>("h02e")], clk - infer mport T_3964 = tgts[UInt<6>("h02f")], clk - infer mport T_3966 = tgts[UInt<6>("h030")], clk - infer mport T_3968 = tgts[UInt<6>("h031")], clk - infer mport T_3970 = tgts[UInt<6>("h032")], clk - infer mport T_3972 = tgts[UInt<6>("h033")], clk - infer mport T_3974 = tgts[UInt<6>("h034")], clk - infer mport T_3976 = tgts[UInt<6>("h035")], clk - infer mport T_3978 = tgts[UInt<6>("h036")], clk - infer mport T_3980 = tgts[UInt<6>("h037")], clk - infer mport T_3982 = tgts[UInt<6>("h038")], clk - infer mport T_3984 = tgts[UInt<6>("h039")], clk - infer mport T_3986 = tgts[UInt<6>("h03a")], clk - infer mport T_3988 = tgts[UInt<6>("h03b")], clk - infer mport T_3990 = tgts[UInt<6>("h03c")], clk - infer mport T_3992 = tgts[UInt<6>("h03d")], clk - node T_3994 = mux(T_3807, T_3870, UInt<1>("h00")) - node T_3996 = mux(T_3808, T_3872, UInt<1>("h00")) - node T_3998 = mux(T_3809, T_3874, UInt<1>("h00")) - node T_4000 = mux(T_3810, T_3876, UInt<1>("h00")) - node T_4002 = mux(T_3811, T_3878, UInt<1>("h00")) - node T_4004 = mux(T_3812, T_3880, UInt<1>("h00")) - node T_4006 = mux(T_3813, T_3882, UInt<1>("h00")) - node T_4008 = mux(T_3814, T_3884, UInt<1>("h00")) - node T_4010 = mux(T_3815, T_3886, UInt<1>("h00")) - node T_4012 = mux(T_3816, T_3888, UInt<1>("h00")) - node T_4014 = mux(T_3817, T_3890, UInt<1>("h00")) - node T_4016 = mux(T_3818, T_3892, UInt<1>("h00")) - node T_4018 = mux(T_3819, T_3894, UInt<1>("h00")) - node T_4020 = mux(T_3820, T_3896, UInt<1>("h00")) - node T_4022 = mux(T_3821, T_3898, UInt<1>("h00")) - node T_4024 = mux(T_3822, T_3900, UInt<1>("h00")) - node T_4026 = mux(T_3823, T_3902, UInt<1>("h00")) - node T_4028 = mux(T_3824, T_3904, UInt<1>("h00")) - node T_4030 = mux(T_3825, T_3906, UInt<1>("h00")) - node T_4032 = mux(T_3826, T_3908, UInt<1>("h00")) - node T_4034 = mux(T_3827, T_3910, UInt<1>("h00")) - node T_4036 = mux(T_3828, T_3912, UInt<1>("h00")) - node T_4038 = mux(T_3829, T_3914, UInt<1>("h00")) - node T_4040 = mux(T_3830, T_3916, UInt<1>("h00")) - node T_4042 = mux(T_3831, T_3918, UInt<1>("h00")) - node T_4044 = mux(T_3832, T_3920, UInt<1>("h00")) - node T_4046 = mux(T_3833, T_3922, UInt<1>("h00")) - node T_4048 = mux(T_3834, T_3924, UInt<1>("h00")) - node T_4050 = mux(T_3835, T_3926, UInt<1>("h00")) - node T_4052 = mux(T_3836, T_3928, UInt<1>("h00")) - node T_4054 = mux(T_3837, T_3930, UInt<1>("h00")) - node T_4056 = mux(T_3838, T_3932, UInt<1>("h00")) - node T_4058 = mux(T_3839, T_3934, UInt<1>("h00")) - node T_4060 = mux(T_3840, T_3936, UInt<1>("h00")) - node T_4062 = mux(T_3841, T_3938, UInt<1>("h00")) - node T_4064 = mux(T_3842, T_3940, UInt<1>("h00")) - node T_4066 = mux(T_3843, T_3942, UInt<1>("h00")) - node T_4068 = mux(T_3844, T_3944, UInt<1>("h00")) - node T_4070 = mux(T_3845, T_3946, UInt<1>("h00")) - node T_4072 = mux(T_3846, T_3948, UInt<1>("h00")) - node T_4074 = mux(T_3847, T_3950, UInt<1>("h00")) - node T_4076 = mux(T_3848, T_3952, UInt<1>("h00")) - node T_4078 = mux(T_3849, T_3954, UInt<1>("h00")) - node T_4080 = mux(T_3850, T_3956, UInt<1>("h00")) - node T_4082 = mux(T_3851, T_3958, UInt<1>("h00")) - node T_4084 = mux(T_3852, T_3960, UInt<1>("h00")) - node T_4086 = mux(T_3853, T_3962, UInt<1>("h00")) - node T_4088 = mux(T_3854, T_3964, UInt<1>("h00")) - node T_4090 = mux(T_3855, T_3966, UInt<1>("h00")) - node T_4092 = mux(T_3856, T_3968, UInt<1>("h00")) - node T_4094 = mux(T_3857, T_3970, UInt<1>("h00")) - node T_4096 = mux(T_3858, T_3972, UInt<1>("h00")) - node T_4098 = mux(T_3859, T_3974, UInt<1>("h00")) - node T_4100 = mux(T_3860, T_3976, UInt<1>("h00")) - node T_4102 = mux(T_3861, T_3978, UInt<1>("h00")) - node T_4104 = mux(T_3862, T_3980, UInt<1>("h00")) - node T_4106 = mux(T_3863, T_3982, UInt<1>("h00")) - node T_4108 = mux(T_3864, T_3984, UInt<1>("h00")) - node T_4110 = mux(T_3865, T_3986, UInt<1>("h00")) - node T_4112 = mux(T_3866, T_3988, UInt<1>("h00")) - node T_4114 = mux(T_3867, T_3990, UInt<1>("h00")) - node T_4116 = mux(T_3868, T_3992, UInt<1>("h00")) - node T_4118 = or(T_3994, T_3996) - node T_4119 = or(T_4118, T_3998) - node T_4120 = or(T_4119, T_4000) - node T_4121 = or(T_4120, T_4002) - node T_4122 = or(T_4121, T_4004) - node T_4123 = or(T_4122, T_4006) - node T_4124 = or(T_4123, T_4008) - node T_4125 = or(T_4124, T_4010) - node T_4126 = or(T_4125, T_4012) - node T_4127 = or(T_4126, T_4014) - node T_4128 = or(T_4127, T_4016) - node T_4129 = or(T_4128, T_4018) - node T_4130 = or(T_4129, T_4020) - node T_4131 = or(T_4130, T_4022) - node T_4132 = or(T_4131, T_4024) - node T_4133 = or(T_4132, T_4026) - node T_4134 = or(T_4133, T_4028) - node T_4135 = or(T_4134, T_4030) - node T_4136 = or(T_4135, T_4032) - node T_4137 = or(T_4136, T_4034) - node T_4138 = or(T_4137, T_4036) - node T_4139 = or(T_4138, T_4038) - node T_4140 = or(T_4139, T_4040) - node T_4141 = or(T_4140, T_4042) - node T_4142 = or(T_4141, T_4044) - node T_4143 = or(T_4142, T_4046) - node T_4144 = or(T_4143, T_4048) - node T_4145 = or(T_4144, T_4050) - node T_4146 = or(T_4145, T_4052) - node T_4147 = or(T_4146, T_4054) - node T_4148 = or(T_4147, T_4056) - node T_4149 = or(T_4148, T_4058) - node T_4150 = or(T_4149, T_4060) - node T_4151 = or(T_4150, T_4062) - node T_4152 = or(T_4151, T_4064) - node T_4153 = or(T_4152, T_4066) - node T_4154 = or(T_4153, T_4068) - node T_4155 = or(T_4154, T_4070) - node T_4156 = or(T_4155, T_4072) - node T_4157 = or(T_4156, T_4074) - node T_4158 = or(T_4157, T_4076) - node T_4159 = or(T_4158, T_4078) - node T_4160 = or(T_4159, T_4080) - node T_4161 = or(T_4160, T_4082) - node T_4162 = or(T_4161, T_4084) - node T_4163 = or(T_4162, T_4086) - node T_4164 = or(T_4163, T_4088) - node T_4165 = or(T_4164, T_4090) - node T_4166 = or(T_4165, T_4092) - node T_4167 = or(T_4166, T_4094) - node T_4168 = or(T_4167, T_4096) - node T_4169 = or(T_4168, T_4098) - node T_4170 = or(T_4169, T_4100) - node T_4171 = or(T_4170, T_4102) - node T_4172 = or(T_4171, T_4104) - node T_4173 = or(T_4172, T_4106) - node T_4174 = or(T_4173, T_4108) - node T_4175 = or(T_4174, T_4110) - node T_4176 = or(T_4175, T_4112) - node T_4177 = or(T_4176, T_4114) - node T_4178 = or(T_4177, T_4116) - wire T_4179 : UInt<12> - T_4179 is invalid - T_4179 <= T_4178 - node T_4180 = cat(T_3806, T_4179) - io.resp.bits.target <= T_4180 - node T_4181 = bits(hits, 61, 32) - node T_4182 = bits(hits, 31, 0) - node T_4184 = neq(T_4181, UInt<1>("h00")) - node T_4185 = or(T_4181, T_4182) - node T_4186 = bits(T_4185, 31, 16) - node T_4187 = bits(T_4185, 15, 0) - node T_4189 = neq(T_4186, UInt<1>("h00")) - node T_4190 = or(T_4186, T_4187) - node T_4191 = bits(T_4190, 15, 8) - node T_4192 = bits(T_4190, 7, 0) - node T_4194 = neq(T_4191, UInt<1>("h00")) - node T_4195 = or(T_4191, T_4192) - node T_4196 = bits(T_4195, 7, 4) - node T_4197 = bits(T_4195, 3, 0) - node T_4199 = neq(T_4196, UInt<1>("h00")) - node T_4200 = or(T_4196, T_4197) - node T_4201 = bits(T_4200, 3, 2) - node T_4202 = bits(T_4200, 1, 0) - node T_4204 = neq(T_4201, UInt<1>("h00")) - node T_4205 = or(T_4201, T_4202) - node T_4206 = bits(T_4205, 1, 1) - node T_4207 = cat(T_4204, T_4206) - node T_4208 = cat(T_4199, T_4207) - node T_4209 = cat(T_4194, T_4208) - node T_4210 = cat(T_4189, T_4209) - node T_4211 = cat(T_4184, T_4210) - io.resp.bits.entry <= T_4211 - infer mport T_4212 = brIdx[io.resp.bits.entry], clk - io.resp.bits.bridx <= T_4212 - io.resp.bits.mask <= UInt<1>("h01") - cmem T_4216 : UInt<2>[128] - reg T_4218 : UInt<7>, clk - node T_4219 = bits(hits, 0, 0) - node T_4220 = bits(hits, 1, 1) - node T_4221 = bits(hits, 2, 2) - node T_4222 = bits(hits, 3, 3) - node T_4223 = bits(hits, 4, 4) - node T_4224 = bits(hits, 5, 5) - node T_4225 = bits(hits, 6, 6) - node T_4226 = bits(hits, 7, 7) - node T_4227 = bits(hits, 8, 8) - node T_4228 = bits(hits, 9, 9) - node T_4229 = bits(hits, 10, 10) - node T_4230 = bits(hits, 11, 11) - node T_4231 = bits(hits, 12, 12) - node T_4232 = bits(hits, 13, 13) - node T_4233 = bits(hits, 14, 14) - node T_4234 = bits(hits, 15, 15) - node T_4235 = bits(hits, 16, 16) - node T_4236 = bits(hits, 17, 17) - node T_4237 = bits(hits, 18, 18) - node T_4238 = bits(hits, 19, 19) - node T_4239 = bits(hits, 20, 20) - node T_4240 = bits(hits, 21, 21) - node T_4241 = bits(hits, 22, 22) - node T_4242 = bits(hits, 23, 23) - node T_4243 = bits(hits, 24, 24) - node T_4244 = bits(hits, 25, 25) - node T_4245 = bits(hits, 26, 26) - node T_4246 = bits(hits, 27, 27) - node T_4247 = bits(hits, 28, 28) - node T_4248 = bits(hits, 29, 29) - node T_4249 = bits(hits, 30, 30) - node T_4250 = bits(hits, 31, 31) - node T_4251 = bits(hits, 32, 32) - node T_4252 = bits(hits, 33, 33) - node T_4253 = bits(hits, 34, 34) - node T_4254 = bits(hits, 35, 35) - node T_4255 = bits(hits, 36, 36) - node T_4256 = bits(hits, 37, 37) - node T_4257 = bits(hits, 38, 38) - node T_4258 = bits(hits, 39, 39) - node T_4259 = bits(hits, 40, 40) - node T_4260 = bits(hits, 41, 41) - node T_4261 = bits(hits, 42, 42) - node T_4262 = bits(hits, 43, 43) - node T_4263 = bits(hits, 44, 44) - node T_4264 = bits(hits, 45, 45) - node T_4265 = bits(hits, 46, 46) - node T_4266 = bits(hits, 47, 47) - node T_4267 = bits(hits, 48, 48) - node T_4268 = bits(hits, 49, 49) - node T_4269 = bits(hits, 50, 50) - node T_4270 = bits(hits, 51, 51) - node T_4271 = bits(hits, 52, 52) - node T_4272 = bits(hits, 53, 53) - node T_4273 = bits(hits, 54, 54) - node T_4274 = bits(hits, 55, 55) - node T_4275 = bits(hits, 56, 56) - node T_4276 = bits(hits, 57, 57) - node T_4277 = bits(hits, 58, 58) - node T_4278 = bits(hits, 59, 59) - node T_4279 = bits(hits, 60, 60) - node T_4280 = bits(hits, 61, 61) - node T_4282 = shl(isJump[0], 0) - node T_4283 = mux(T_4219, T_4282, UInt<1>("h00")) - node T_4285 = shl(isJump[1], 0) - node T_4286 = mux(T_4220, T_4285, UInt<1>("h00")) - node T_4288 = shl(isJump[2], 0) - node T_4289 = mux(T_4221, T_4288, UInt<1>("h00")) - node T_4291 = shl(isJump[3], 0) - node T_4292 = mux(T_4222, T_4291, UInt<1>("h00")) - node T_4294 = shl(isJump[4], 0) - node T_4295 = mux(T_4223, T_4294, UInt<1>("h00")) - node T_4297 = shl(isJump[5], 0) - node T_4298 = mux(T_4224, T_4297, UInt<1>("h00")) - node T_4300 = shl(isJump[6], 0) - node T_4301 = mux(T_4225, T_4300, UInt<1>("h00")) - node T_4303 = shl(isJump[7], 0) - node T_4304 = mux(T_4226, T_4303, UInt<1>("h00")) - node T_4306 = shl(isJump[8], 0) - node T_4307 = mux(T_4227, T_4306, UInt<1>("h00")) - node T_4309 = shl(isJump[9], 0) - node T_4310 = mux(T_4228, T_4309, UInt<1>("h00")) - node T_4312 = shl(isJump[10], 0) - node T_4313 = mux(T_4229, T_4312, UInt<1>("h00")) - node T_4315 = shl(isJump[11], 0) - node T_4316 = mux(T_4230, T_4315, UInt<1>("h00")) - node T_4318 = shl(isJump[12], 0) - node T_4319 = mux(T_4231, T_4318, UInt<1>("h00")) - node T_4321 = shl(isJump[13], 0) - node T_4322 = mux(T_4232, T_4321, UInt<1>("h00")) - node T_4324 = shl(isJump[14], 0) - node T_4325 = mux(T_4233, T_4324, UInt<1>("h00")) - node T_4327 = shl(isJump[15], 0) - node T_4328 = mux(T_4234, T_4327, UInt<1>("h00")) - node T_4330 = shl(isJump[16], 0) - node T_4331 = mux(T_4235, T_4330, UInt<1>("h00")) - node T_4333 = shl(isJump[17], 0) - node T_4334 = mux(T_4236, T_4333, UInt<1>("h00")) - node T_4336 = shl(isJump[18], 0) - node T_4337 = mux(T_4237, T_4336, UInt<1>("h00")) - node T_4339 = shl(isJump[19], 0) - node T_4340 = mux(T_4238, T_4339, UInt<1>("h00")) - node T_4342 = shl(isJump[20], 0) - node T_4343 = mux(T_4239, T_4342, UInt<1>("h00")) - node T_4345 = shl(isJump[21], 0) - node T_4346 = mux(T_4240, T_4345, UInt<1>("h00")) - node T_4348 = shl(isJump[22], 0) - node T_4349 = mux(T_4241, T_4348, UInt<1>("h00")) - node T_4351 = shl(isJump[23], 0) - node T_4352 = mux(T_4242, T_4351, UInt<1>("h00")) - node T_4354 = shl(isJump[24], 0) - node T_4355 = mux(T_4243, T_4354, UInt<1>("h00")) - node T_4357 = shl(isJump[25], 0) - node T_4358 = mux(T_4244, T_4357, UInt<1>("h00")) - node T_4360 = shl(isJump[26], 0) - node T_4361 = mux(T_4245, T_4360, UInt<1>("h00")) - node T_4363 = shl(isJump[27], 0) - node T_4364 = mux(T_4246, T_4363, UInt<1>("h00")) - node T_4366 = shl(isJump[28], 0) - node T_4367 = mux(T_4247, T_4366, UInt<1>("h00")) - node T_4369 = shl(isJump[29], 0) - node T_4370 = mux(T_4248, T_4369, UInt<1>("h00")) - node T_4372 = shl(isJump[30], 0) - node T_4373 = mux(T_4249, T_4372, UInt<1>("h00")) - node T_4375 = shl(isJump[31], 0) - node T_4376 = mux(T_4250, T_4375, UInt<1>("h00")) - node T_4378 = shl(isJump[32], 0) - node T_4379 = mux(T_4251, T_4378, UInt<1>("h00")) - node T_4381 = shl(isJump[33], 0) - node T_4382 = mux(T_4252, T_4381, UInt<1>("h00")) - node T_4384 = shl(isJump[34], 0) - node T_4385 = mux(T_4253, T_4384, UInt<1>("h00")) - node T_4387 = shl(isJump[35], 0) - node T_4388 = mux(T_4254, T_4387, UInt<1>("h00")) - node T_4390 = shl(isJump[36], 0) - node T_4391 = mux(T_4255, T_4390, UInt<1>("h00")) - node T_4393 = shl(isJump[37], 0) - node T_4394 = mux(T_4256, T_4393, UInt<1>("h00")) - node T_4396 = shl(isJump[38], 0) - node T_4397 = mux(T_4257, T_4396, UInt<1>("h00")) - node T_4399 = shl(isJump[39], 0) - node T_4400 = mux(T_4258, T_4399, UInt<1>("h00")) - node T_4402 = shl(isJump[40], 0) - node T_4403 = mux(T_4259, T_4402, UInt<1>("h00")) - node T_4405 = shl(isJump[41], 0) - node T_4406 = mux(T_4260, T_4405, UInt<1>("h00")) - node T_4408 = shl(isJump[42], 0) - node T_4409 = mux(T_4261, T_4408, UInt<1>("h00")) - node T_4411 = shl(isJump[43], 0) - node T_4412 = mux(T_4262, T_4411, UInt<1>("h00")) - node T_4414 = shl(isJump[44], 0) - node T_4415 = mux(T_4263, T_4414, UInt<1>("h00")) - node T_4417 = shl(isJump[45], 0) - node T_4418 = mux(T_4264, T_4417, UInt<1>("h00")) - node T_4420 = shl(isJump[46], 0) - node T_4421 = mux(T_4265, T_4420, UInt<1>("h00")) - node T_4423 = shl(isJump[47], 0) - node T_4424 = mux(T_4266, T_4423, UInt<1>("h00")) - node T_4426 = shl(isJump[48], 0) - node T_4427 = mux(T_4267, T_4426, UInt<1>("h00")) - node T_4429 = shl(isJump[49], 0) - node T_4430 = mux(T_4268, T_4429, UInt<1>("h00")) - node T_4432 = shl(isJump[50], 0) - node T_4433 = mux(T_4269, T_4432, UInt<1>("h00")) - node T_4435 = shl(isJump[51], 0) - node T_4436 = mux(T_4270, T_4435, UInt<1>("h00")) - node T_4438 = shl(isJump[52], 0) - node T_4439 = mux(T_4271, T_4438, UInt<1>("h00")) - node T_4441 = shl(isJump[53], 0) - node T_4442 = mux(T_4272, T_4441, UInt<1>("h00")) - node T_4444 = shl(isJump[54], 0) - node T_4445 = mux(T_4273, T_4444, UInt<1>("h00")) - node T_4447 = shl(isJump[55], 0) - node T_4448 = mux(T_4274, T_4447, UInt<1>("h00")) - node T_4450 = shl(isJump[56], 0) - node T_4451 = mux(T_4275, T_4450, UInt<1>("h00")) - node T_4453 = shl(isJump[57], 0) - node T_4454 = mux(T_4276, T_4453, UInt<1>("h00")) - node T_4456 = shl(isJump[58], 0) - node T_4457 = mux(T_4277, T_4456, UInt<1>("h00")) - node T_4459 = shl(isJump[59], 0) - node T_4460 = mux(T_4278, T_4459, UInt<1>("h00")) - node T_4462 = shl(isJump[60], 0) - node T_4463 = mux(T_4279, T_4462, UInt<1>("h00")) - node T_4465 = shl(isJump[61], 0) - node T_4466 = mux(T_4280, T_4465, UInt<1>("h00")) - node T_4468 = or(T_4283, T_4286) - node T_4469 = or(T_4468, T_4289) - node T_4470 = or(T_4469, T_4292) - node T_4471 = or(T_4470, T_4295) - node T_4472 = or(T_4471, T_4298) - node T_4473 = or(T_4472, T_4301) - node T_4474 = or(T_4473, T_4304) - node T_4475 = or(T_4474, T_4307) - node T_4476 = or(T_4475, T_4310) - node T_4477 = or(T_4476, T_4313) - node T_4478 = or(T_4477, T_4316) - node T_4479 = or(T_4478, T_4319) - node T_4480 = or(T_4479, T_4322) - node T_4481 = or(T_4480, T_4325) - node T_4482 = or(T_4481, T_4328) - node T_4483 = or(T_4482, T_4331) - node T_4484 = or(T_4483, T_4334) - node T_4485 = or(T_4484, T_4337) - node T_4486 = or(T_4485, T_4340) - node T_4487 = or(T_4486, T_4343) - node T_4488 = or(T_4487, T_4346) - node T_4489 = or(T_4488, T_4349) - node T_4490 = or(T_4489, T_4352) - node T_4491 = or(T_4490, T_4355) - node T_4492 = or(T_4491, T_4358) - node T_4493 = or(T_4492, T_4361) - node T_4494 = or(T_4493, T_4364) - node T_4495 = or(T_4494, T_4367) - node T_4496 = or(T_4495, T_4370) - node T_4497 = or(T_4496, T_4373) - node T_4498 = or(T_4497, T_4376) - node T_4499 = or(T_4498, T_4379) - node T_4500 = or(T_4499, T_4382) - node T_4501 = or(T_4500, T_4385) - node T_4502 = or(T_4501, T_4388) - node T_4503 = or(T_4502, T_4391) - node T_4504 = or(T_4503, T_4394) - node T_4505 = or(T_4504, T_4397) - node T_4506 = or(T_4505, T_4400) - node T_4507 = or(T_4506, T_4403) - node T_4508 = or(T_4507, T_4406) - node T_4509 = or(T_4508, T_4409) - node T_4510 = or(T_4509, T_4412) - node T_4511 = or(T_4510, T_4415) - node T_4512 = or(T_4511, T_4418) - node T_4513 = or(T_4512, T_4421) - node T_4514 = or(T_4513, T_4424) - node T_4515 = or(T_4514, T_4427) - node T_4516 = or(T_4515, T_4430) - node T_4517 = or(T_4516, T_4433) - node T_4518 = or(T_4517, T_4436) - node T_4519 = or(T_4518, T_4439) - node T_4520 = or(T_4519, T_4442) - node T_4521 = or(T_4520, T_4445) - node T_4522 = or(T_4521, T_4448) - node T_4523 = or(T_4522, T_4451) - node T_4524 = or(T_4523, T_4454) - node T_4525 = or(T_4524, T_4457) - node T_4526 = or(T_4525, T_4460) - node T_4527 = or(T_4526, T_4463) - node T_4528 = or(T_4527, T_4466) - wire T_4529 : UInt<1> - T_4529 is invalid - T_4529 <= T_4528 - node T_4531 = eq(T_4529, UInt<1>("h00")) - node T_4532 = and(io.req.valid, io.resp.valid) - node T_4533 = and(T_4532, T_4531) - wire T_4537 : {history : UInt<7>, value : UInt<2>} - T_4537 is invalid - node T_4540 = bits(io.req.bits.addr, 8, 2) - node T_4541 = xor(T_4540, T_4218) - infer mport T_4542 = T_4216[T_4541], clk - T_4537.value <= T_4542 - T_4537.history <= T_4218 - node T_4543 = bits(T_4537.value, 0, 0) - when T_4533 : - node T_4544 = bits(T_4218, 6, 1) - node T_4545 = cat(T_4543, T_4544) - T_4218 <= T_4545 - skip - node T_4546 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) - when T_4546 : - node T_4547 = bits(io.bht_update.bits.pc, 8, 2) - node T_4548 = xor(T_4547, io.bht_update.bits.prediction.bits.bht.history) - infer mport T_4549 = T_4216[T_4548], clk - node T_4550 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) - node T_4551 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) - node T_4552 = and(T_4550, T_4551) - node T_4553 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) - node T_4554 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) - node T_4555 = or(T_4553, T_4554) - node T_4556 = and(T_4555, io.bht_update.bits.taken) - node T_4557 = or(T_4552, T_4556) - node T_4558 = cat(io.bht_update.bits.taken, T_4557) - T_4549 <= T_4558 - when io.bht_update.bits.mispredict : - node T_4559 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) - node T_4560 = cat(io.bht_update.bits.taken, T_4559) - T_4218 <= T_4560 - skip - skip - node T_4561 = bits(T_4537.value, 0, 0) - node T_4563 = eq(T_4561, UInt<1>("h00")) - node T_4564 = and(T_4563, T_4531) - when T_4564 : - io.resp.bits.taken <= UInt<1>("h00") - skip - io.resp.bits.bht <- T_4537 - reg T_4567 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg T_4569 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_4578 : UInt[2], clk - node T_4582 = bits(hits, 0, 0) - node T_4583 = bits(hits, 1, 1) - node T_4584 = bits(hits, 2, 2) - node T_4585 = bits(hits, 3, 3) - node T_4586 = bits(hits, 4, 4) - node T_4587 = bits(hits, 5, 5) - node T_4588 = bits(hits, 6, 6) - node T_4589 = bits(hits, 7, 7) - node T_4590 = bits(hits, 8, 8) - node T_4591 = bits(hits, 9, 9) - node T_4592 = bits(hits, 10, 10) - node T_4593 = bits(hits, 11, 11) - node T_4594 = bits(hits, 12, 12) - node T_4595 = bits(hits, 13, 13) - node T_4596 = bits(hits, 14, 14) - node T_4597 = bits(hits, 15, 15) - node T_4598 = bits(hits, 16, 16) - node T_4599 = bits(hits, 17, 17) - node T_4600 = bits(hits, 18, 18) - node T_4601 = bits(hits, 19, 19) - node T_4602 = bits(hits, 20, 20) - node T_4603 = bits(hits, 21, 21) - node T_4604 = bits(hits, 22, 22) - node T_4605 = bits(hits, 23, 23) - node T_4606 = bits(hits, 24, 24) - node T_4607 = bits(hits, 25, 25) - node T_4608 = bits(hits, 26, 26) - node T_4609 = bits(hits, 27, 27) - node T_4610 = bits(hits, 28, 28) - node T_4611 = bits(hits, 29, 29) - node T_4612 = bits(hits, 30, 30) - node T_4613 = bits(hits, 31, 31) - node T_4614 = bits(hits, 32, 32) - node T_4615 = bits(hits, 33, 33) - node T_4616 = bits(hits, 34, 34) - node T_4617 = bits(hits, 35, 35) - node T_4618 = bits(hits, 36, 36) - node T_4619 = bits(hits, 37, 37) - node T_4620 = bits(hits, 38, 38) - node T_4621 = bits(hits, 39, 39) - node T_4622 = bits(hits, 40, 40) - node T_4623 = bits(hits, 41, 41) - node T_4624 = bits(hits, 42, 42) - node T_4625 = bits(hits, 43, 43) - node T_4626 = bits(hits, 44, 44) - node T_4627 = bits(hits, 45, 45) - node T_4628 = bits(hits, 46, 46) - node T_4629 = bits(hits, 47, 47) - node T_4630 = bits(hits, 48, 48) - node T_4631 = bits(hits, 49, 49) - node T_4632 = bits(hits, 50, 50) - node T_4633 = bits(hits, 51, 51) - node T_4634 = bits(hits, 52, 52) - node T_4635 = bits(hits, 53, 53) - node T_4636 = bits(hits, 54, 54) - node T_4637 = bits(hits, 55, 55) - node T_4638 = bits(hits, 56, 56) - node T_4639 = bits(hits, 57, 57) - node T_4640 = bits(hits, 58, 58) - node T_4641 = bits(hits, 59, 59) - node T_4642 = bits(hits, 60, 60) - node T_4643 = bits(hits, 61, 61) - node T_4645 = shl(useRAS[0], 0) - node T_4646 = mux(T_4582, T_4645, UInt<1>("h00")) - node T_4648 = shl(useRAS[1], 0) - node T_4649 = mux(T_4583, T_4648, UInt<1>("h00")) - node T_4651 = shl(useRAS[2], 0) - node T_4652 = mux(T_4584, T_4651, UInt<1>("h00")) - node T_4654 = shl(useRAS[3], 0) - node T_4655 = mux(T_4585, T_4654, UInt<1>("h00")) - node T_4657 = shl(useRAS[4], 0) - node T_4658 = mux(T_4586, T_4657, UInt<1>("h00")) - node T_4660 = shl(useRAS[5], 0) - node T_4661 = mux(T_4587, T_4660, UInt<1>("h00")) - node T_4663 = shl(useRAS[6], 0) - node T_4664 = mux(T_4588, T_4663, UInt<1>("h00")) - node T_4666 = shl(useRAS[7], 0) - node T_4667 = mux(T_4589, T_4666, UInt<1>("h00")) - node T_4669 = shl(useRAS[8], 0) - node T_4670 = mux(T_4590, T_4669, UInt<1>("h00")) - node T_4672 = shl(useRAS[9], 0) - node T_4673 = mux(T_4591, T_4672, UInt<1>("h00")) - node T_4675 = shl(useRAS[10], 0) - node T_4676 = mux(T_4592, T_4675, UInt<1>("h00")) - node T_4678 = shl(useRAS[11], 0) - node T_4679 = mux(T_4593, T_4678, UInt<1>("h00")) - node T_4681 = shl(useRAS[12], 0) - node T_4682 = mux(T_4594, T_4681, UInt<1>("h00")) - node T_4684 = shl(useRAS[13], 0) - node T_4685 = mux(T_4595, T_4684, UInt<1>("h00")) - node T_4687 = shl(useRAS[14], 0) - node T_4688 = mux(T_4596, T_4687, UInt<1>("h00")) - node T_4690 = shl(useRAS[15], 0) - node T_4691 = mux(T_4597, T_4690, UInt<1>("h00")) - node T_4693 = shl(useRAS[16], 0) - node T_4694 = mux(T_4598, T_4693, UInt<1>("h00")) - node T_4696 = shl(useRAS[17], 0) - node T_4697 = mux(T_4599, T_4696, UInt<1>("h00")) - node T_4699 = shl(useRAS[18], 0) - node T_4700 = mux(T_4600, T_4699, UInt<1>("h00")) - node T_4702 = shl(useRAS[19], 0) - node T_4703 = mux(T_4601, T_4702, UInt<1>("h00")) - node T_4705 = shl(useRAS[20], 0) - node T_4706 = mux(T_4602, T_4705, UInt<1>("h00")) - node T_4708 = shl(useRAS[21], 0) - node T_4709 = mux(T_4603, T_4708, UInt<1>("h00")) - node T_4711 = shl(useRAS[22], 0) - node T_4712 = mux(T_4604, T_4711, UInt<1>("h00")) - node T_4714 = shl(useRAS[23], 0) - node T_4715 = mux(T_4605, T_4714, UInt<1>("h00")) - node T_4717 = shl(useRAS[24], 0) - node T_4718 = mux(T_4606, T_4717, UInt<1>("h00")) - node T_4720 = shl(useRAS[25], 0) - node T_4721 = mux(T_4607, T_4720, UInt<1>("h00")) - node T_4723 = shl(useRAS[26], 0) - node T_4724 = mux(T_4608, T_4723, UInt<1>("h00")) - node T_4726 = shl(useRAS[27], 0) - node T_4727 = mux(T_4609, T_4726, UInt<1>("h00")) - node T_4729 = shl(useRAS[28], 0) - node T_4730 = mux(T_4610, T_4729, UInt<1>("h00")) - node T_4732 = shl(useRAS[29], 0) - node T_4733 = mux(T_4611, T_4732, UInt<1>("h00")) - node T_4735 = shl(useRAS[30], 0) - node T_4736 = mux(T_4612, T_4735, UInt<1>("h00")) - node T_4738 = shl(useRAS[31], 0) - node T_4739 = mux(T_4613, T_4738, UInt<1>("h00")) - node T_4741 = shl(useRAS[32], 0) - node T_4742 = mux(T_4614, T_4741, UInt<1>("h00")) - node T_4744 = shl(useRAS[33], 0) - node T_4745 = mux(T_4615, T_4744, UInt<1>("h00")) - node T_4747 = shl(useRAS[34], 0) - node T_4748 = mux(T_4616, T_4747, UInt<1>("h00")) - node T_4750 = shl(useRAS[35], 0) - node T_4751 = mux(T_4617, T_4750, UInt<1>("h00")) - node T_4753 = shl(useRAS[36], 0) - node T_4754 = mux(T_4618, T_4753, UInt<1>("h00")) - node T_4756 = shl(useRAS[37], 0) - node T_4757 = mux(T_4619, T_4756, UInt<1>("h00")) - node T_4759 = shl(useRAS[38], 0) - node T_4760 = mux(T_4620, T_4759, UInt<1>("h00")) - node T_4762 = shl(useRAS[39], 0) - node T_4763 = mux(T_4621, T_4762, UInt<1>("h00")) - node T_4765 = shl(useRAS[40], 0) - node T_4766 = mux(T_4622, T_4765, UInt<1>("h00")) - node T_4768 = shl(useRAS[41], 0) - node T_4769 = mux(T_4623, T_4768, UInt<1>("h00")) - node T_4771 = shl(useRAS[42], 0) - node T_4772 = mux(T_4624, T_4771, UInt<1>("h00")) - node T_4774 = shl(useRAS[43], 0) - node T_4775 = mux(T_4625, T_4774, UInt<1>("h00")) - node T_4777 = shl(useRAS[44], 0) - node T_4778 = mux(T_4626, T_4777, UInt<1>("h00")) - node T_4780 = shl(useRAS[45], 0) - node T_4781 = mux(T_4627, T_4780, UInt<1>("h00")) - node T_4783 = shl(useRAS[46], 0) - node T_4784 = mux(T_4628, T_4783, UInt<1>("h00")) - node T_4786 = shl(useRAS[47], 0) - node T_4787 = mux(T_4629, T_4786, UInt<1>("h00")) - node T_4789 = shl(useRAS[48], 0) - node T_4790 = mux(T_4630, T_4789, UInt<1>("h00")) - node T_4792 = shl(useRAS[49], 0) - node T_4793 = mux(T_4631, T_4792, UInt<1>("h00")) - node T_4795 = shl(useRAS[50], 0) - node T_4796 = mux(T_4632, T_4795, UInt<1>("h00")) - node T_4798 = shl(useRAS[51], 0) - node T_4799 = mux(T_4633, T_4798, UInt<1>("h00")) - node T_4801 = shl(useRAS[52], 0) - node T_4802 = mux(T_4634, T_4801, UInt<1>("h00")) - node T_4804 = shl(useRAS[53], 0) - node T_4805 = mux(T_4635, T_4804, UInt<1>("h00")) - node T_4807 = shl(useRAS[54], 0) - node T_4808 = mux(T_4636, T_4807, UInt<1>("h00")) - node T_4810 = shl(useRAS[55], 0) - node T_4811 = mux(T_4637, T_4810, UInt<1>("h00")) - node T_4813 = shl(useRAS[56], 0) - node T_4814 = mux(T_4638, T_4813, UInt<1>("h00")) - node T_4816 = shl(useRAS[57], 0) - node T_4817 = mux(T_4639, T_4816, UInt<1>("h00")) - node T_4819 = shl(useRAS[58], 0) - node T_4820 = mux(T_4640, T_4819, UInt<1>("h00")) - node T_4822 = shl(useRAS[59], 0) - node T_4823 = mux(T_4641, T_4822, UInt<1>("h00")) - node T_4825 = shl(useRAS[60], 0) - node T_4826 = mux(T_4642, T_4825, UInt<1>("h00")) - node T_4828 = shl(useRAS[61], 0) - node T_4829 = mux(T_4643, T_4828, UInt<1>("h00")) - node T_4831 = or(T_4646, T_4649) - node T_4832 = or(T_4831, T_4652) - node T_4833 = or(T_4832, T_4655) - node T_4834 = or(T_4833, T_4658) - node T_4835 = or(T_4834, T_4661) - node T_4836 = or(T_4835, T_4664) - node T_4837 = or(T_4836, T_4667) - node T_4838 = or(T_4837, T_4670) - node T_4839 = or(T_4838, T_4673) - node T_4840 = or(T_4839, T_4676) - node T_4841 = or(T_4840, T_4679) - node T_4842 = or(T_4841, T_4682) - node T_4843 = or(T_4842, T_4685) - node T_4844 = or(T_4843, T_4688) - node T_4845 = or(T_4844, T_4691) - node T_4846 = or(T_4845, T_4694) - node T_4847 = or(T_4846, T_4697) - node T_4848 = or(T_4847, T_4700) - node T_4849 = or(T_4848, T_4703) - node T_4850 = or(T_4849, T_4706) - node T_4851 = or(T_4850, T_4709) - node T_4852 = or(T_4851, T_4712) - node T_4853 = or(T_4852, T_4715) - node T_4854 = or(T_4853, T_4718) - node T_4855 = or(T_4854, T_4721) - node T_4856 = or(T_4855, T_4724) - node T_4857 = or(T_4856, T_4727) - node T_4858 = or(T_4857, T_4730) - node T_4859 = or(T_4858, T_4733) - node T_4860 = or(T_4859, T_4736) - node T_4861 = or(T_4860, T_4739) - node T_4862 = or(T_4861, T_4742) - node T_4863 = or(T_4862, T_4745) - node T_4864 = or(T_4863, T_4748) - node T_4865 = or(T_4864, T_4751) - node T_4866 = or(T_4865, T_4754) - node T_4867 = or(T_4866, T_4757) - node T_4868 = or(T_4867, T_4760) - node T_4869 = or(T_4868, T_4763) - node T_4870 = or(T_4869, T_4766) - node T_4871 = or(T_4870, T_4769) - node T_4872 = or(T_4871, T_4772) - node T_4873 = or(T_4872, T_4775) - node T_4874 = or(T_4873, T_4778) - node T_4875 = or(T_4874, T_4781) - node T_4876 = or(T_4875, T_4784) - node T_4877 = or(T_4876, T_4787) - node T_4878 = or(T_4877, T_4790) - node T_4879 = or(T_4878, T_4793) - node T_4880 = or(T_4879, T_4796) - node T_4881 = or(T_4880, T_4799) - node T_4882 = or(T_4881, T_4802) - node T_4883 = or(T_4882, T_4805) - node T_4884 = or(T_4883, T_4808) - node T_4885 = or(T_4884, T_4811) - node T_4886 = or(T_4885, T_4814) - node T_4887 = or(T_4886, T_4817) - node T_4888 = or(T_4887, T_4820) - node T_4889 = or(T_4888, T_4823) - node T_4890 = or(T_4889, T_4826) - node T_4891 = or(T_4890, T_4829) - wire T_4892 : UInt<1> - T_4892 is invalid - T_4892 <= T_4891 - node T_4894 = eq(T_4567, UInt<1>("h00")) - node T_4896 = eq(T_4894, UInt<1>("h00")) - node T_4897 = and(T_4896, T_4892) - when T_4897 : - io.resp.bits.target <= T_4578[T_4569] - skip - when io.ras_update.valid : - when io.ras_update.bits.isCall : - node T_4900 = lt(T_4567, UInt<2>("h02")) - when T_4900 : - node T_4902 = add(T_4567, UInt<1>("h01")) - node T_4903 = tail(T_4902, 1) - T_4567 <= T_4903 - skip - node T_4906 = lt(T_4569, UInt<1>("h01")) - node T_4907 = or(UInt<1>("h01"), T_4906) - node T_4909 = add(T_4569, UInt<1>("h01")) - node T_4910 = tail(T_4909, 1) - node T_4912 = mux(T_4907, T_4910, UInt<1>("h00")) - T_4578[T_4912] <= io.ras_update.bits.returnAddr - T_4569 <= T_4912 - when T_4892 : - io.resp.bits.target <= io.ras_update.bits.returnAddr - skip - skip - node T_4914 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) - node T_4916 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) - node T_4917 = and(T_4916, T_4914) - when T_4917 : - node T_4919 = eq(T_4567, UInt<1>("h00")) - node T_4921 = eq(T_4919, UInt<1>("h00")) - when T_4921 : - node T_4923 = sub(T_4567, UInt<1>("h01")) - node T_4924 = tail(T_4923, 1) - T_4567 <= T_4924 - node T_4927 = gt(T_4569, UInt<1>("h00")) - node T_4928 = or(UInt<1>("h01"), T_4927) - node T_4930 = sub(T_4569, UInt<1>("h01")) - node T_4931 = tail(T_4930, 1) - node T_4933 = mux(T_4928, T_4931, UInt<1>("h01")) - T_4569 <= T_4933 - skip - skip - skip - when io.invalidate : - T_4567 <= UInt<1>("h00") - skip + output io : {flip l2in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}, mmio : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, flip interrupts : {0 : UInt<1>[2]}, mem : {0 : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}}, flip debug : {req : {mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}, flip resp : {mem : {data : UInt<34>, resp : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip rtcToggle : UInt<1>, flip resetVector : UInt<64>, tcrs : {flip clock : Clock, flip reset : UInt<1>}[1]} - module FlowThroughSerializer : - input clk : Clock + io is invalid + io is invalid + inst l1tol2 of TLXbar_l1tol2 @[LazyModule.scala 60:13] + l1tol2.io is invalid + l1tol2.clock <= clock + l1tol2.reset <= reset + inst cbus of TLXbar_cbus @[LazyModule.scala 60:13] + cbus.io is invalid + cbus.clock <= clock + cbus.reset <= reset + inst intBar of IntXbar_intBar @[LazyModule.scala 60:13] + intBar.io is invalid + intBar.clock <= clock + intBar.reset <= reset + inst TLMonitor of TLMonitor_14 @[LazyModule.scala 60:13] + TLMonitor.io is invalid + TLMonitor.clock <= clock + TLMonitor.reset <= reset + inst cbus_TLWidthWidget of TLWidthWidget_cbus @[LazyModule.scala 60:13] + cbus_TLWidthWidget.io is invalid + cbus_TLWidthWidget.clock <= clock + cbus_TLWidthWidget.reset <= reset + inst TLMonitor_1 of TLMonitor_15 @[LazyModule.scala 60:13] + TLMonitor_1.io is invalid + TLMonitor_1.clock <= clock + TLMonitor_1.reset <= reset + inst cbus_TLAtomicAutomata of TLAtomicAutomata_cbus @[LazyModule.scala 60:13] + cbus_TLAtomicAutomata.io is invalid + cbus_TLAtomicAutomata.clock <= clock + cbus_TLAtomicAutomata.reset <= reset + inst TLMonitor_2 of TLMonitor_16 @[LazyModule.scala 60:13] + TLMonitor_2.io is invalid + TLMonitor_2.clock <= clock + TLMonitor_2.reset <= reset + inst cbus_TLBuffer of TLBuffer_cbus @[LazyModule.scala 60:13] + cbus_TLBuffer.io is invalid + cbus_TLBuffer.clock <= clock + cbus_TLBuffer.reset <= reset + inst TLMonitor_3 of TLMonitor_17 @[LazyModule.scala 60:13] + TLMonitor_3.io is invalid + TLMonitor_3.clock <= clock + TLMonitor_3.reset <= reset + inst TLMonitor_4 of TLMonitor_18 @[LazyModule.scala 60:13] + TLMonitor_4.io is invalid + TLMonitor_4.clock <= clock + TLMonitor_4.reset <= reset + inst socBus_TLWidthWidget of TLWidthWidget_socBus @[LazyModule.scala 60:13] + socBus_TLWidthWidget.io is invalid + socBus_TLWidthWidget.clock <= clock + socBus_TLWidthWidget.reset <= reset + inst TLMonitor_5 of TLMonitor_19 @[LazyModule.scala 60:13] + TLMonitor_5.io is invalid + TLMonitor_5.clock <= clock + TLMonitor_5.reset <= reset + inst TLMonitor_6 of TLMonitor_20 @[LazyModule.scala 60:13] + TLMonitor_6.io is invalid + TLMonitor_6.clock <= clock + TLMonitor_6.reset <= reset + inst mem_0_TLBroadcast of TLBroadcast_mem_0 @[LazyModule.scala 60:13] + mem_0_TLBroadcast.io is invalid + mem_0_TLBroadcast.clock <= clock + mem_0_TLBroadcast.reset <= reset + inst mem_0_TLWidthWidget of TLWidthWidget_mem_0 @[LazyModule.scala 60:13] + mem_0_TLWidthWidget.io is invalid + mem_0_TLWidthWidget.clock <= clock + mem_0_TLWidthWidget.reset <= reset + inst TLMonitor_7 of TLMonitor_21 @[LazyModule.scala 60:13] + TLMonitor_7.io is invalid + TLMonitor_7.clock <= clock + TLMonitor_7.reset <= reset + inst TLMonitor_8 of TLMonitor_22 @[LazyModule.scala 60:13] + TLMonitor_8.io is invalid + TLMonitor_8.clock <= clock + TLMonitor_8.reset <= reset + inst mem_0_TLFilter of TLFilter_mem_0 @[LazyModule.scala 60:13] + mem_0_TLFilter.io is invalid + mem_0_TLFilter.clock <= clock + mem_0_TLFilter.reset <= reset + inst TLMonitor_9 of TLMonitor_23 @[LazyModule.scala 60:13] + TLMonitor_9.io is invalid + TLMonitor_9.clock <= clock + TLMonitor_9.reset <= reset + inst TLMonitor_10 of TLMonitor_24 @[LazyModule.scala 60:13] + TLMonitor_10.io is invalid + TLMonitor_10.clock <= clock + TLMonitor_10.reset <= reset + inst debug of TLDebugModule_debug @[LazyModule.scala 60:13] + debug.io is invalid + debug.clock <= clock + debug.reset <= reset + inst plic of TLPLIC_plic @[LazyModule.scala 60:13] + plic.io is invalid + plic.clock <= clock + plic.reset <= reset + inst clint of CoreplexLocalInterrupter_clint @[LazyModule.scala 60:13] + clint.io is invalid + clint.clock <= clock + clint.reset <= reset + inst debug_TLFragmenter of TLFragmenter_debug @[LazyModule.scala 60:13] + debug_TLFragmenter.io is invalid + debug_TLFragmenter.clock <= clock + debug_TLFragmenter.reset <= reset + inst TLMonitor_11 of TLMonitor_25 @[LazyModule.scala 60:13] + TLMonitor_11.io is invalid + TLMonitor_11.clock <= clock + TLMonitor_11.reset <= reset + inst TLMonitor_12 of TLMonitor_26 @[LazyModule.scala 60:13] + TLMonitor_12.io is invalid + TLMonitor_12.clock <= clock + TLMonitor_12.reset <= reset + inst plic_TLFragmenter of TLFragmenter_plic @[LazyModule.scala 60:13] + plic_TLFragmenter.io is invalid + plic_TLFragmenter.clock <= clock + plic_TLFragmenter.reset <= reset + inst TLMonitor_13 of TLMonitor_27 @[LazyModule.scala 60:13] + TLMonitor_13.io is invalid + TLMonitor_13.clock <= clock + TLMonitor_13.reset <= reset + inst TLMonitor_14 of TLMonitor_28 @[LazyModule.scala 60:13] + TLMonitor_14.io is invalid + TLMonitor_14.clock <= clock + TLMonitor_14.reset <= reset + inst clint_TLFragmenter of TLFragmenter_clint @[LazyModule.scala 60:13] + clint_TLFragmenter.io is invalid + clint_TLFragmenter.clock <= clock + clint_TLFragmenter.reset <= reset + inst TLMonitor_15 of TLMonitor_29 @[LazyModule.scala 60:13] + TLMonitor_15.io is invalid + TLMonitor_15.clock <= clock + TLMonitor_15.reset <= reset + inst TLMonitor_16 of TLMonitor_30 @[LazyModule.scala 60:13] + TLMonitor_16.io is invalid + TLMonitor_16.clock <= clock + TLMonitor_16.reset <= reset + inst IntXbar of IntXbar @[LazyModule.scala 60:13] + IntXbar.io is invalid + IntXbar.clock <= clock + IntXbar.reset <= reset + inst RocketTile of RocketTile @[LazyModule.scala 60:13] + RocketTile.io is invalid + RocketTile.clock <= clock + RocketTile.reset <= reset + inst TLBuffer of TLBuffer @[LazyModule.scala 60:13] + TLBuffer.io is invalid + TLBuffer.clock <= clock + TLBuffer.reset <= reset + inst TLMonitor_17 of TLMonitor_34 @[LazyModule.scala 60:13] + TLMonitor_17.io is invalid + TLMonitor_17.clock <= clock + TLMonitor_17.reset <= reset + inst TLMonitor_18 of TLMonitor_35 @[LazyModule.scala 60:13] + TLMonitor_18.io is invalid + TLMonitor_18.clock <= clock + TLMonitor_18.reset <= reset + inst TLMonitor_19 of TLMonitor_36 @[LazyModule.scala 60:13] + TLMonitor_19.io is invalid + TLMonitor_19.clock <= clock + TLMonitor_19.reset <= reset + intBar.io.in.0 <- io.interrupts.0 @[CoreplexNetwork.scala 30:18] + wire _T_98 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_98 is invalid @[Bundles.scala 234:19] + wire _T_195 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_195 is invalid @[Bundles.scala 214:19] + _T_195.ready <= l1tol2.io.in.0.a.ready @[Bundles.scala 215:15] + _T_195.valid <= io.l2in.0.a.valid @[Bundles.scala 216:15] + _T_195.bits <- io.l2in.0.a.bits @[Bundles.scala 217:15] + _T_98.a <- _T_195 @[Bundles.scala 235:11] + wire _T_217 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_217 is invalid @[Bundles.scala 214:19] + _T_217.ready <= io.l2in.0.b.ready @[Bundles.scala 215:15] + _T_217.valid <= l1tol2.io.in.0.b.valid @[Bundles.scala 216:15] + _T_217.bits <- l1tol2.io.in.0.b.bits @[Bundles.scala 217:15] + _T_98.b <- _T_217 @[Bundles.scala 236:11] + wire _T_239 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_239 is invalid @[Bundles.scala 214:19] + _T_239.ready <= l1tol2.io.in.0.c.ready @[Bundles.scala 215:15] + _T_239.valid <= io.l2in.0.c.valid @[Bundles.scala 216:15] + _T_239.bits <- io.l2in.0.c.bits @[Bundles.scala 217:15] + _T_98.c <- _T_239 @[Bundles.scala 237:11] + wire _T_262 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_262 is invalid @[Bundles.scala 214:19] + _T_262.ready <= io.l2in.0.d.ready @[Bundles.scala 215:15] + _T_262.valid <= l1tol2.io.in.0.d.valid @[Bundles.scala 216:15] + _T_262.bits <- l1tol2.io.in.0.d.bits @[Bundles.scala 217:15] + _T_98.d <- _T_262 @[Bundles.scala 238:11] + wire _T_279 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_279 is invalid @[Bundles.scala 214:19] + _T_279.ready <= l1tol2.io.in.0.e.ready @[Bundles.scala 215:15] + _T_279.valid <= io.l2in.0.e.valid @[Bundles.scala 216:15] + _T_279.bits <- io.l2in.0.e.bits @[Bundles.scala 217:15] + _T_98.e <- _T_279 @[Bundles.scala 239:11] + TLMonitor.io.in[0] <- _T_98 @[CoreplexNetwork.scala 33:15] + l1tol2.io.in.0 <- io.l2in.0 @[CoreplexNetwork.scala 33:15] + wire _T_370 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}} @[Bundles.scala 234:19] + _T_370 is invalid @[Bundles.scala 234:19] + wire _T_467 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_467 is invalid @[Bundles.scala 214:19] + _T_467.ready <= cbus_TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_467.valid <= l1tol2.io.out.0.a.valid @[Bundles.scala 216:15] + _T_467.bits <- l1tol2.io.out.0.a.bits @[Bundles.scala 217:15] + _T_370.a <- _T_467 @[Bundles.scala 235:11] + wire _T_489 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_489 is invalid @[Bundles.scala 214:19] + _T_489.ready <= l1tol2.io.out.0.b.ready @[Bundles.scala 215:15] + _T_489.valid <= cbus_TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_489.bits <- cbus_TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_370.b <- _T_489 @[Bundles.scala 236:11] + wire _T_511 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_511 is invalid @[Bundles.scala 214:19] + _T_511.ready <= cbus_TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_511.valid <= l1tol2.io.out.0.c.valid @[Bundles.scala 216:15] + _T_511.bits <- l1tol2.io.out.0.c.bits @[Bundles.scala 217:15] + _T_370.c <- _T_511 @[Bundles.scala 237:11] + wire _T_534 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_534 is invalid @[Bundles.scala 214:19] + _T_534.ready <= l1tol2.io.out.0.d.ready @[Bundles.scala 215:15] + _T_534.valid <= cbus_TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_534.bits <- cbus_TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_370.d <- _T_534 @[Bundles.scala 238:11] + wire _T_551 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}} @[Bundles.scala 214:19] + _T_551 is invalid @[Bundles.scala 214:19] + _T_551.ready <= cbus_TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_551.valid <= l1tol2.io.out.0.e.valid @[Bundles.scala 216:15] + _T_551.bits <- l1tol2.io.out.0.e.bits @[Bundles.scala 217:15] + _T_370.e <- _T_551 @[Bundles.scala 239:11] + TLMonitor_1.io.in[0] <- _T_370 @[CoreplexNetwork.scala 38:36] + cbus_TLWidthWidget.io.in.0 <- l1tol2.io.out.0 @[CoreplexNetwork.scala 38:36] + wire _T_642 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}} @[Bundles.scala 234:19] + _T_642 is invalid @[Bundles.scala 234:19] + wire _T_739 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_739 is invalid @[Bundles.scala 214:19] + _T_739.ready <= cbus_TLAtomicAutomata.io.in.0.a.ready @[Bundles.scala 215:15] + _T_739.valid <= cbus_TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_739.bits <- cbus_TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_642.a <- _T_739 @[Bundles.scala 235:11] + wire _T_761 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_761 is invalid @[Bundles.scala 214:19] + _T_761.ready <= cbus_TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_761.valid <= cbus_TLAtomicAutomata.io.in.0.b.valid @[Bundles.scala 216:15] + _T_761.bits <- cbus_TLAtomicAutomata.io.in.0.b.bits @[Bundles.scala 217:15] + _T_642.b <- _T_761 @[Bundles.scala 236:11] + wire _T_783 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_783 is invalid @[Bundles.scala 214:19] + _T_783.ready <= cbus_TLAtomicAutomata.io.in.0.c.ready @[Bundles.scala 215:15] + _T_783.valid <= cbus_TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_783.bits <- cbus_TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_642.c <- _T_783 @[Bundles.scala 237:11] + wire _T_806 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_806 is invalid @[Bundles.scala 214:19] + _T_806.ready <= cbus_TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_806.valid <= cbus_TLAtomicAutomata.io.in.0.d.valid @[Bundles.scala 216:15] + _T_806.bits <- cbus_TLAtomicAutomata.io.in.0.d.bits @[Bundles.scala 217:15] + _T_642.d <- _T_806 @[Bundles.scala 238:11] + wire _T_823 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}} @[Bundles.scala 214:19] + _T_823 is invalid @[Bundles.scala 214:19] + _T_823.ready <= cbus_TLAtomicAutomata.io.in.0.e.ready @[Bundles.scala 215:15] + _T_823.valid <= cbus_TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_823.bits <- cbus_TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_642.e <- _T_823 @[Bundles.scala 239:11] + TLMonitor_2.io.in[0] <- _T_642 @[CoreplexNetwork.scala 37:40] + cbus_TLAtomicAutomata.io.in.0 <- cbus_TLWidthWidget.io.out.0 @[CoreplexNetwork.scala 37:40] + wire _T_914 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}} @[Bundles.scala 234:19] + _T_914 is invalid @[Bundles.scala 234:19] + wire _T_1011 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1011 is invalid @[Bundles.scala 214:19] + _T_1011.ready <= cbus_TLBuffer.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1011.valid <= cbus_TLAtomicAutomata.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1011.bits <- cbus_TLAtomicAutomata.io.out.0.a.bits @[Bundles.scala 217:15] + _T_914.a <- _T_1011 @[Bundles.scala 235:11] + wire _T_1033 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1033 is invalid @[Bundles.scala 214:19] + _T_1033.ready <= cbus_TLAtomicAutomata.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1033.valid <= cbus_TLBuffer.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1033.bits <- cbus_TLBuffer.io.in.0.b.bits @[Bundles.scala 217:15] + _T_914.b <- _T_1033 @[Bundles.scala 236:11] + wire _T_1055 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1055 is invalid @[Bundles.scala 214:19] + _T_1055.ready <= cbus_TLBuffer.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1055.valid <= cbus_TLAtomicAutomata.io.out.0.c.valid @[Bundles.scala 216:15] + _T_1055.bits <- cbus_TLAtomicAutomata.io.out.0.c.bits @[Bundles.scala 217:15] + _T_914.c <- _T_1055 @[Bundles.scala 237:11] + wire _T_1078 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1078 is invalid @[Bundles.scala 214:19] + _T_1078.ready <= cbus_TLAtomicAutomata.io.out.0.d.ready @[Bundles.scala 215:15] + _T_1078.valid <= cbus_TLBuffer.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1078.bits <- cbus_TLBuffer.io.in.0.d.bits @[Bundles.scala 217:15] + _T_914.d <- _T_1078 @[Bundles.scala 238:11] + wire _T_1095 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}} @[Bundles.scala 214:19] + _T_1095 is invalid @[Bundles.scala 214:19] + _T_1095.ready <= cbus_TLBuffer.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1095.valid <= cbus_TLAtomicAutomata.io.out.0.e.valid @[Bundles.scala 216:15] + _T_1095.bits <- cbus_TLAtomicAutomata.io.out.0.e.bits @[Bundles.scala 217:15] + _T_914.e <- _T_1095 @[Bundles.scala 239:11] + TLMonitor_3.io.in[0] <- _T_914 @[CoreplexNetwork.scala 36:15] + cbus_TLBuffer.io.in.0 <- cbus_TLAtomicAutomata.io.out.0 @[CoreplexNetwork.scala 36:15] + wire _T_1186 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}} @[Bundles.scala 234:19] + _T_1186 is invalid @[Bundles.scala 234:19] + wire _T_1283 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1283 is invalid @[Bundles.scala 214:19] + _T_1283.ready <= cbus.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1283.valid <= cbus_TLBuffer.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1283.bits <- cbus_TLBuffer.io.out.0.a.bits @[Bundles.scala 217:15] + _T_1186.a <- _T_1283 @[Bundles.scala 235:11] + wire _T_1305 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1305 is invalid @[Bundles.scala 214:19] + _T_1305.ready <= cbus_TLBuffer.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1305.valid <= cbus.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1305.bits <- cbus.io.in.0.b.bits @[Bundles.scala 217:15] + _T_1186.b <- _T_1305 @[Bundles.scala 236:11] + wire _T_1327 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1327 is invalid @[Bundles.scala 214:19] + _T_1327.ready <= cbus.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1327.valid <= cbus_TLBuffer.io.out.0.c.valid @[Bundles.scala 216:15] + _T_1327.bits <- cbus_TLBuffer.io.out.0.c.bits @[Bundles.scala 217:15] + _T_1186.c <- _T_1327 @[Bundles.scala 237:11] + wire _T_1350 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1350 is invalid @[Bundles.scala 214:19] + _T_1350.ready <= cbus_TLBuffer.io.out.0.d.ready @[Bundles.scala 215:15] + _T_1350.valid <= cbus.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1350.bits <- cbus.io.in.0.d.bits @[Bundles.scala 217:15] + _T_1186.d <- _T_1350 @[Bundles.scala 238:11] + wire _T_1367 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}} @[Bundles.scala 214:19] + _T_1367 is invalid @[Bundles.scala 214:19] + _T_1367.ready <= cbus.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1367.valid <= cbus_TLBuffer.io.out.0.e.valid @[Bundles.scala 216:15] + _T_1367.bits <- cbus_TLBuffer.io.out.0.e.bits @[Bundles.scala 217:15] + _T_1186.e <- _T_1367 @[Bundles.scala 239:11] + TLMonitor_4.io.in[0] <- _T_1186 @[CoreplexNetwork.scala 35:13] + cbus.io.in.0 <- cbus_TLBuffer.io.out.0 @[CoreplexNetwork.scala 35:13] + wire _T_1458 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_1458 is invalid @[Bundles.scala 234:19] + wire _T_1555 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1555 is invalid @[Bundles.scala 214:19] + _T_1555.ready <= socBus_TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1555.valid <= l1tol2.io.out.1.a.valid @[Bundles.scala 216:15] + _T_1555.bits <- l1tol2.io.out.1.a.bits @[Bundles.scala 217:15] + _T_1458.a <- _T_1555 @[Bundles.scala 235:11] + wire _T_1577 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1577 is invalid @[Bundles.scala 214:19] + _T_1577.ready <= l1tol2.io.out.1.b.ready @[Bundles.scala 215:15] + _T_1577.valid <= socBus_TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1577.bits <- socBus_TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_1458.b <- _T_1577 @[Bundles.scala 236:11] + wire _T_1599 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1599 is invalid @[Bundles.scala 214:19] + _T_1599.ready <= socBus_TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1599.valid <= l1tol2.io.out.1.c.valid @[Bundles.scala 216:15] + _T_1599.bits <- l1tol2.io.out.1.c.bits @[Bundles.scala 217:15] + _T_1458.c <- _T_1599 @[Bundles.scala 237:11] + wire _T_1622 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1622 is invalid @[Bundles.scala 214:19] + _T_1622.ready <= l1tol2.io.out.1.d.ready @[Bundles.scala 215:15] + _T_1622.valid <= socBus_TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1622.bits <- socBus_TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_1458.d <- _T_1622 @[Bundles.scala 238:11] + wire _T_1639 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_1639 is invalid @[Bundles.scala 214:19] + _T_1639.ready <= socBus_TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1639.valid <= l1tol2.io.out.1.e.valid @[Bundles.scala 216:15] + _T_1639.bits <- l1tol2.io.out.1.e.bits @[Bundles.scala 217:15] + _T_1458.e <- _T_1639 @[Bundles.scala 239:11] + TLMonitor_5.io.in[0] <- _T_1458 @[CoreplexNetwork.scala 42:36] + socBus_TLWidthWidget.io.in.0 <- l1tol2.io.out.1 @[CoreplexNetwork.scala 42:36] + wire _T_1730 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_1730 is invalid @[Bundles.scala 234:19] + wire _T_1827 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1827 is invalid @[Bundles.scala 214:19] + _T_1827.ready <= io.mmio.0.a.ready @[Bundles.scala 215:15] + _T_1827.valid <= socBus_TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1827.bits <- socBus_TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_1730.a <- _T_1827 @[Bundles.scala 235:11] + wire _T_1849 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1849 is invalid @[Bundles.scala 214:19] + _T_1849.ready <= socBus_TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1849.valid <= io.mmio.0.b.valid @[Bundles.scala 216:15] + _T_1849.bits <- io.mmio.0.b.bits @[Bundles.scala 217:15] + _T_1730.b <- _T_1849 @[Bundles.scala 236:11] + wire _T_1871 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1871 is invalid @[Bundles.scala 214:19] + _T_1871.ready <= io.mmio.0.c.ready @[Bundles.scala 215:15] + _T_1871.valid <= socBus_TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_1871.bits <- socBus_TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_1730.c <- _T_1871 @[Bundles.scala 237:11] + wire _T_1894 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1894 is invalid @[Bundles.scala 214:19] + _T_1894.ready <= socBus_TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_1894.valid <= io.mmio.0.d.valid @[Bundles.scala 216:15] + _T_1894.bits <- io.mmio.0.d.bits @[Bundles.scala 217:15] + _T_1730.d <- _T_1894 @[Bundles.scala 238:11] + wire _T_1911 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_1911 is invalid @[Bundles.scala 214:19] + _T_1911.ready <= io.mmio.0.e.ready @[Bundles.scala 215:15] + _T_1911.valid <= socBus_TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_1911.bits <- socBus_TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_1730.e <- _T_1911 @[Bundles.scala 239:11] + TLMonitor_6.io.in[0] <- _T_1730 @[CoreplexNetwork.scala 41:8] + io.mmio.0 <- socBus_TLWidthWidget.io.out.0 @[CoreplexNetwork.scala 41:8] + wire _T_2002 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_2002 is invalid @[Bundles.scala 234:19] + wire _T_2099 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2099 is invalid @[Bundles.scala 214:19] + _T_2099.ready <= mem_0_TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_2099.valid <= mem_0_TLBroadcast.io.out.0.a.valid @[Bundles.scala 216:15] + _T_2099.bits <- mem_0_TLBroadcast.io.out.0.a.bits @[Bundles.scala 217:15] + _T_2002.a <- _T_2099 @[Bundles.scala 235:11] + wire _T_2121 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2121 is invalid @[Bundles.scala 214:19] + _T_2121.ready <= mem_0_TLBroadcast.io.out.0.b.ready @[Bundles.scala 215:15] + _T_2121.valid <= mem_0_TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_2121.bits <- mem_0_TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_2002.b <- _T_2121 @[Bundles.scala 236:11] + wire _T_2143 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2143 is invalid @[Bundles.scala 214:19] + _T_2143.ready <= mem_0_TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_2143.valid <= mem_0_TLBroadcast.io.out.0.c.valid @[Bundles.scala 216:15] + _T_2143.bits <- mem_0_TLBroadcast.io.out.0.c.bits @[Bundles.scala 217:15] + _T_2002.c <- _T_2143 @[Bundles.scala 237:11] + wire _T_2166 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2166 is invalid @[Bundles.scala 214:19] + _T_2166.ready <= mem_0_TLBroadcast.io.out.0.d.ready @[Bundles.scala 215:15] + _T_2166.valid <= mem_0_TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_2166.bits <- mem_0_TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_2002.d <- _T_2166 @[Bundles.scala 238:11] + wire _T_2183 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_2183 is invalid @[Bundles.scala 214:19] + _T_2183.ready <= mem_0_TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_2183.valid <= mem_0_TLBroadcast.io.out.0.e.valid @[Bundles.scala 216:15] + _T_2183.bits <- mem_0_TLBroadcast.io.out.0.e.bits @[Bundles.scala 217:15] + _T_2002.e <- _T_2183 @[Bundles.scala 239:11] + TLMonitor_7.io.in[0] <- _T_2002 @[BaseCoreplex.scala 36:13] + mem_0_TLWidthWidget.io.in.0 <- mem_0_TLBroadcast.io.out.0 @[BaseCoreplex.scala 36:13] + wire _T_2274 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}}} @[Bundles.scala 234:19] + _T_2274 is invalid @[Bundles.scala 234:19] + wire _T_2371 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2371 is invalid @[Bundles.scala 214:19] + _T_2371.ready <= mem_0_TLBroadcast.io.in.0.a.ready @[Bundles.scala 215:15] + _T_2371.valid <= l1tol2.io.out.2.a.valid @[Bundles.scala 216:15] + _T_2371.bits <- l1tol2.io.out.2.a.bits @[Bundles.scala 217:15] + _T_2274.a <- _T_2371 @[Bundles.scala 235:11] + wire _T_2393 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2393 is invalid @[Bundles.scala 214:19] + _T_2393.ready <= l1tol2.io.out.2.b.ready @[Bundles.scala 215:15] + _T_2393.valid <= mem_0_TLBroadcast.io.in.0.b.valid @[Bundles.scala 216:15] + _T_2393.bits <- mem_0_TLBroadcast.io.in.0.b.bits @[Bundles.scala 217:15] + _T_2274.b <- _T_2393 @[Bundles.scala 236:11] + wire _T_2415 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2415 is invalid @[Bundles.scala 214:19] + _T_2415.ready <= mem_0_TLBroadcast.io.in.0.c.ready @[Bundles.scala 215:15] + _T_2415.valid <= l1tol2.io.out.2.c.valid @[Bundles.scala 216:15] + _T_2415.bits <- l1tol2.io.out.2.c.bits @[Bundles.scala 217:15] + _T_2274.c <- _T_2415 @[Bundles.scala 237:11] + wire _T_2438 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<2>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2438 is invalid @[Bundles.scala 214:19] + _T_2438.ready <= l1tol2.io.out.2.d.ready @[Bundles.scala 215:15] + _T_2438.valid <= mem_0_TLBroadcast.io.in.0.d.valid @[Bundles.scala 216:15] + _T_2438.bits <- mem_0_TLBroadcast.io.in.0.d.bits @[Bundles.scala 217:15] + _T_2274.d <- _T_2438 @[Bundles.scala 238:11] + wire _T_2455 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<2>}} @[Bundles.scala 214:19] + _T_2455 is invalid @[Bundles.scala 214:19] + _T_2455.ready <= mem_0_TLBroadcast.io.in.0.e.ready @[Bundles.scala 215:15] + _T_2455.valid <= l1tol2.io.out.2.e.valid @[Bundles.scala 216:15] + _T_2455.bits <- l1tol2.io.out.2.e.bits @[Bundles.scala 217:15] + _T_2274.e <- _T_2455 @[Bundles.scala 239:11] + TLMonitor_8.io.in[0] <- _T_2274 @[CoreplexNetwork.scala 133:10] + mem_0_TLBroadcast.io.in.0 <- l1tol2.io.out.2 @[CoreplexNetwork.scala 133:10] + wire _T_2546 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_2546 is invalid @[Bundles.scala 234:19] + wire _T_2643 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2643 is invalid @[Bundles.scala 214:19] + _T_2643.ready <= mem_0_TLFilter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_2643.valid <= mem_0_TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_2643.bits <- mem_0_TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_2546.a <- _T_2643 @[Bundles.scala 235:11] + wire _T_2665 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2665 is invalid @[Bundles.scala 214:19] + _T_2665.ready <= mem_0_TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_2665.valid <= mem_0_TLFilter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_2665.bits <- mem_0_TLFilter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_2546.b <- _T_2665 @[Bundles.scala 236:11] + wire _T_2687 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2687 is invalid @[Bundles.scala 214:19] + _T_2687.ready <= mem_0_TLFilter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_2687.valid <= mem_0_TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_2687.bits <- mem_0_TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_2546.c <- _T_2687 @[Bundles.scala 237:11] + wire _T_2710 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2710 is invalid @[Bundles.scala 214:19] + _T_2710.ready <= mem_0_TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_2710.valid <= mem_0_TLFilter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_2710.bits <- mem_0_TLFilter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_2546.d <- _T_2710 @[Bundles.scala 238:11] + wire _T_2727 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_2727 is invalid @[Bundles.scala 214:19] + _T_2727.ready <= mem_0_TLFilter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_2727.valid <= mem_0_TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_2727.bits <- mem_0_TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_2546.e <- _T_2727 @[Bundles.scala 239:11] + TLMonitor_9.io.in[0] <- _T_2546 @[CoreplexNetwork.scala 134:68] + mem_0_TLFilter.io.in.0 <- mem_0_TLWidthWidget.io.out.0 @[CoreplexNetwork.scala 134:68] + wire _T_2818 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_2818 is invalid @[Bundles.scala 234:19] + wire _T_2915 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2915 is invalid @[Bundles.scala 214:19] + _T_2915.ready <= io.mem.0.0.a.ready @[Bundles.scala 215:15] + _T_2915.valid <= mem_0_TLFilter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_2915.bits <- mem_0_TLFilter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_2818.a <- _T_2915 @[Bundles.scala 235:11] + wire _T_2937 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2937 is invalid @[Bundles.scala 214:19] + _T_2937.ready <= mem_0_TLFilter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_2937.valid <= io.mem.0.0.b.valid @[Bundles.scala 216:15] + _T_2937.bits <- io.mem.0.0.b.bits @[Bundles.scala 217:15] + _T_2818.b <- _T_2937 @[Bundles.scala 236:11] + wire _T_2959 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2959 is invalid @[Bundles.scala 214:19] + _T_2959.ready <= io.mem.0.0.c.ready @[Bundles.scala 215:15] + _T_2959.valid <= mem_0_TLFilter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_2959.bits <- mem_0_TLFilter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_2818.c <- _T_2959 @[Bundles.scala 237:11] + wire _T_2982 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2982 is invalid @[Bundles.scala 214:19] + _T_2982.ready <= mem_0_TLFilter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_2982.valid <= io.mem.0.0.d.valid @[Bundles.scala 216:15] + _T_2982.bits <- io.mem.0.0.d.bits @[Bundles.scala 217:15] + _T_2818.d <- _T_2982 @[Bundles.scala 238:11] + wire _T_2999 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_2999 is invalid @[Bundles.scala 214:19] + _T_2999.ready <= io.mem.0.0.e.ready @[Bundles.scala 215:15] + _T_2999.valid <= mem_0_TLFilter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_2999.bits <- mem_0_TLFilter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_2818.e <- _T_2999 @[Bundles.scala 239:11] + TLMonitor_10.io.in[0] <- _T_2818 @[CoreplexNetwork.scala 134:12] + io.mem.0.0 <- mem_0_TLFilter.io.out.0 @[CoreplexNetwork.scala 134:12] + wire _T_3090 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3090 is invalid @[Bundles.scala 234:19] + wire _T_3187 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3187 is invalid @[Bundles.scala 214:19] + _T_3187.ready <= debug_TLFragmenter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3187.valid <= cbus.io.out.0.a.valid @[Bundles.scala 216:15] + _T_3187.bits <- cbus.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3090.a <- _T_3187 @[Bundles.scala 235:11] + wire _T_3209 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3209 is invalid @[Bundles.scala 214:19] + _T_3209.ready <= cbus.io.out.0.b.ready @[Bundles.scala 215:15] + _T_3209.valid <= debug_TLFragmenter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3209.bits <- debug_TLFragmenter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3090.b <- _T_3209 @[Bundles.scala 236:11] + wire _T_3231 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<12>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3231 is invalid @[Bundles.scala 214:19] + _T_3231.ready <= debug_TLFragmenter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3231.valid <= cbus.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3231.bits <- cbus.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3090.c <- _T_3231 @[Bundles.scala 237:11] + wire _T_3254 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3254 is invalid @[Bundles.scala 214:19] + _T_3254.ready <= cbus.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3254.valid <= debug_TLFragmenter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3254.bits <- debug_TLFragmenter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3090.d <- _T_3254 @[Bundles.scala 238:11] + wire _T_3271 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_3271 is invalid @[Bundles.scala 214:19] + _T_3271.ready <= debug_TLFragmenter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3271.valid <= cbus.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3271.bits <- cbus.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3090.e <- _T_3271 @[Bundles.scala 239:11] + TLMonitor_11.io.in[0] <- _T_3090 @[RISCVPlatform.scala 21:61] + debug_TLFragmenter.io.in.0 <- cbus.io.out.0 @[RISCVPlatform.scala 21:61] + wire _T_3362 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3362 is invalid @[Bundles.scala 234:19] + wire _T_3459 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3459 is invalid @[Bundles.scala 214:19] + _T_3459.ready <= debug.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3459.valid <= debug_TLFragmenter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_3459.bits <- debug_TLFragmenter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3362.a <- _T_3459 @[Bundles.scala 235:11] + wire _T_3481 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3481 is invalid @[Bundles.scala 214:19] + _T_3481.ready <= debug_TLFragmenter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_3481.valid <= debug.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3481.bits <- debug.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3362.b <- _T_3481 @[Bundles.scala 236:11] + wire _T_3503 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<12>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3503 is invalid @[Bundles.scala 214:19] + _T_3503.ready <= debug.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3503.valid <= debug_TLFragmenter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3503.bits <- debug_TLFragmenter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3362.c <- _T_3503 @[Bundles.scala 237:11] + wire _T_3526 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3526 is invalid @[Bundles.scala 214:19] + _T_3526.ready <= debug_TLFragmenter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3526.valid <= debug.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3526.bits <- debug.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3362.d <- _T_3526 @[Bundles.scala 238:11] + wire _T_3543 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_3543 is invalid @[Bundles.scala 214:19] + _T_3543.ready <= debug.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3543.valid <= debug_TLFragmenter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3543.bits <- debug_TLFragmenter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3362.e <- _T_3543 @[Bundles.scala 239:11] + TLMonitor_12.io.in[0] <- _T_3362 @[RISCVPlatform.scala 21:14] + debug.io.in.0 <- debug_TLFragmenter.io.out.0 @[RISCVPlatform.scala 21:14] + wire _T_3634 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3634 is invalid @[Bundles.scala 234:19] + wire _T_3731 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3731 is invalid @[Bundles.scala 214:19] + _T_3731.ready <= plic_TLFragmenter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3731.valid <= cbus.io.out.1.a.valid @[Bundles.scala 216:15] + _T_3731.bits <- cbus.io.out.1.a.bits @[Bundles.scala 217:15] + _T_3634.a <- _T_3731 @[Bundles.scala 235:11] + wire _T_3753 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3753 is invalid @[Bundles.scala 214:19] + _T_3753.ready <= cbus.io.out.1.b.ready @[Bundles.scala 215:15] + _T_3753.valid <= plic_TLFragmenter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3753.bits <- plic_TLFragmenter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3634.b <- _T_3753 @[Bundles.scala 236:11] + wire _T_3775 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3775 is invalid @[Bundles.scala 214:19] + _T_3775.ready <= plic_TLFragmenter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3775.valid <= cbus.io.out.1.c.valid @[Bundles.scala 216:15] + _T_3775.bits <- cbus.io.out.1.c.bits @[Bundles.scala 217:15] + _T_3634.c <- _T_3775 @[Bundles.scala 237:11] + wire _T_3798 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3798 is invalid @[Bundles.scala 214:19] + _T_3798.ready <= cbus.io.out.1.d.ready @[Bundles.scala 215:15] + _T_3798.valid <= plic_TLFragmenter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3798.bits <- plic_TLFragmenter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3634.d <- _T_3798 @[Bundles.scala 238:11] + wire _T_3815 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_3815 is invalid @[Bundles.scala 214:19] + _T_3815.ready <= plic_TLFragmenter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3815.valid <= cbus.io.out.1.e.valid @[Bundles.scala 216:15] + _T_3815.bits <- cbus.io.out.1.e.bits @[Bundles.scala 217:15] + _T_3634.e <- _T_3815 @[Bundles.scala 239:11] + TLMonitor_13.io.in[0] <- _T_3634 @[RISCVPlatform.scala 22:61] + plic_TLFragmenter.io.in.0 <- cbus.io.out.1 @[RISCVPlatform.scala 22:61] + wire _T_3906 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3906 is invalid @[Bundles.scala 234:19] + wire _T_4003 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4003 is invalid @[Bundles.scala 214:19] + _T_4003.ready <= plic.io.tl_in.0.a.ready @[Bundles.scala 215:15] + _T_4003.valid <= plic_TLFragmenter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_4003.bits <- plic_TLFragmenter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3906.a <- _T_4003 @[Bundles.scala 235:11] + wire _T_4025 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4025 is invalid @[Bundles.scala 214:19] + _T_4025.ready <= plic_TLFragmenter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_4025.valid <= plic.io.tl_in.0.b.valid @[Bundles.scala 216:15] + _T_4025.bits <- plic.io.tl_in.0.b.bits @[Bundles.scala 217:15] + _T_3906.b <- _T_4025 @[Bundles.scala 236:11] + wire _T_4047 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4047 is invalid @[Bundles.scala 214:19] + _T_4047.ready <= plic.io.tl_in.0.c.ready @[Bundles.scala 215:15] + _T_4047.valid <= plic_TLFragmenter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_4047.bits <- plic_TLFragmenter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3906.c <- _T_4047 @[Bundles.scala 237:11] + wire _T_4070 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4070 is invalid @[Bundles.scala 214:19] + _T_4070.ready <= plic_TLFragmenter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_4070.valid <= plic.io.tl_in.0.d.valid @[Bundles.scala 216:15] + _T_4070.bits <- plic.io.tl_in.0.d.bits @[Bundles.scala 217:15] + _T_3906.d <- _T_4070 @[Bundles.scala 238:11] + wire _T_4087 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4087 is invalid @[Bundles.scala 214:19] + _T_4087.ready <= plic.io.tl_in.0.e.ready @[Bundles.scala 215:15] + _T_4087.valid <= plic_TLFragmenter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_4087.bits <- plic_TLFragmenter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3906.e <- _T_4087 @[Bundles.scala 239:11] + TLMonitor_14.io.in[0] <- _T_3906 @[RISCVPlatform.scala 22:14] + plic.io.tl_in.0 <- plic_TLFragmenter.io.out.0 @[RISCVPlatform.scala 22:14] + wire _T_4178 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_4178 is invalid @[Bundles.scala 234:19] + wire _T_4275 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4275 is invalid @[Bundles.scala 214:19] + _T_4275.ready <= clint_TLFragmenter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4275.valid <= cbus.io.out.2.a.valid @[Bundles.scala 216:15] + _T_4275.bits <- cbus.io.out.2.a.bits @[Bundles.scala 217:15] + _T_4178.a <- _T_4275 @[Bundles.scala 235:11] + wire _T_4297 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4297 is invalid @[Bundles.scala 214:19] + _T_4297.ready <= cbus.io.out.2.b.ready @[Bundles.scala 215:15] + _T_4297.valid <= clint_TLFragmenter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4297.bits <- clint_TLFragmenter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_4178.b <- _T_4297 @[Bundles.scala 236:11] + wire _T_4319 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<26>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4319 is invalid @[Bundles.scala 214:19] + _T_4319.ready <= clint_TLFragmenter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4319.valid <= cbus.io.out.2.c.valid @[Bundles.scala 216:15] + _T_4319.bits <- cbus.io.out.2.c.bits @[Bundles.scala 217:15] + _T_4178.c <- _T_4319 @[Bundles.scala 237:11] + wire _T_4342 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4342 is invalid @[Bundles.scala 214:19] + _T_4342.ready <= cbus.io.out.2.d.ready @[Bundles.scala 215:15] + _T_4342.valid <= clint_TLFragmenter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4342.bits <- clint_TLFragmenter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_4178.d <- _T_4342 @[Bundles.scala 238:11] + wire _T_4359 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4359 is invalid @[Bundles.scala 214:19] + _T_4359.ready <= clint_TLFragmenter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4359.valid <= cbus.io.out.2.e.valid @[Bundles.scala 216:15] + _T_4359.bits <- cbus.io.out.2.e.bits @[Bundles.scala 217:15] + _T_4178.e <- _T_4359 @[Bundles.scala 239:11] + TLMonitor_15.io.in[0] <- _T_4178 @[RISCVPlatform.scala 23:61] + clint_TLFragmenter.io.in.0 <- cbus.io.out.2 @[RISCVPlatform.scala 23:61] + wire _T_4450 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_4450 is invalid @[Bundles.scala 234:19] + wire _T_4547 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4547 is invalid @[Bundles.scala 214:19] + _T_4547.ready <= clint.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4547.valid <= clint_TLFragmenter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_4547.bits <- clint_TLFragmenter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_4450.a <- _T_4547 @[Bundles.scala 235:11] + wire _T_4569 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4569 is invalid @[Bundles.scala 214:19] + _T_4569.ready <= clint_TLFragmenter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_4569.valid <= clint.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4569.bits <- clint.io.in.0.b.bits @[Bundles.scala 217:15] + _T_4450.b <- _T_4569 @[Bundles.scala 236:11] + wire _T_4591 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<26>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4591 is invalid @[Bundles.scala 214:19] + _T_4591.ready <= clint.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4591.valid <= clint_TLFragmenter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_4591.bits <- clint_TLFragmenter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_4450.c <- _T_4591 @[Bundles.scala 237:11] + wire _T_4614 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4614 is invalid @[Bundles.scala 214:19] + _T_4614.ready <= clint_TLFragmenter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_4614.valid <= clint.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4614.bits <- clint.io.in.0.d.bits @[Bundles.scala 217:15] + _T_4450.d <- _T_4614 @[Bundles.scala 238:11] + wire _T_4631 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4631 is invalid @[Bundles.scala 214:19] + _T_4631.ready <= clint.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4631.valid <= clint_TLFragmenter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_4631.bits <- clint_TLFragmenter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_4450.e <- _T_4631 @[Bundles.scala 239:11] + TLMonitor_16.io.in[0] <- _T_4450 @[RISCVPlatform.scala 23:14] + clint.io.in.0 <- clint_TLFragmenter.io.out.0 @[RISCVPlatform.scala 23:14] + plic.io.devices.0 <- intBar.io.out.0 @[RISCVPlatform.scala 25:16] + wire _T_4644 : {0 : UInt<1>[1]} @[Nodes.scala 225:62] + _T_4644 is invalid @[Nodes.scala 225:62] + IntXbar.io.in.0 <- _T_4644.0 @[RocketTiles.scala 41:20] + IntXbar.io.in.1 <- clint.io.int.0 @[RocketTiles.scala 42:20] + IntXbar.io.in.2 <- plic.io.harts.0 @[RocketTiles.scala 43:20] + IntXbar.io.in.3 <- plic.io.harts.1 @[RocketTiles.scala 44:38] + wire _T_4731 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_4731 is invalid @[Bundles.scala 234:19] + wire _T_4828 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4828 is invalid @[Bundles.scala 214:19] + _T_4828.ready <= TLBuffer.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4828.valid <= RocketTile.io.master.0.a.valid @[Bundles.scala 216:15] + _T_4828.bits <- RocketTile.io.master.0.a.bits @[Bundles.scala 217:15] + _T_4731.a <- _T_4828 @[Bundles.scala 235:11] + wire _T_4850 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4850 is invalid @[Bundles.scala 214:19] + _T_4850.ready <= RocketTile.io.master.0.b.ready @[Bundles.scala 215:15] + _T_4850.valid <= TLBuffer.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4850.bits <- TLBuffer.io.in.0.b.bits @[Bundles.scala 217:15] + _T_4731.b <- _T_4850 @[Bundles.scala 236:11] + wire _T_4872 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4872 is invalid @[Bundles.scala 214:19] + _T_4872.ready <= TLBuffer.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4872.valid <= RocketTile.io.master.0.c.valid @[Bundles.scala 216:15] + _T_4872.bits <- RocketTile.io.master.0.c.bits @[Bundles.scala 217:15] + _T_4731.c <- _T_4872 @[Bundles.scala 237:11] + wire _T_4895 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4895 is invalid @[Bundles.scala 214:19] + _T_4895.ready <= RocketTile.io.master.0.d.ready @[Bundles.scala 215:15] + _T_4895.valid <= TLBuffer.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4895.bits <- TLBuffer.io.in.0.d.bits @[Bundles.scala 217:15] + _T_4731.d <- _T_4895 @[Bundles.scala 238:11] + wire _T_4912 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_4912 is invalid @[Bundles.scala 214:19] + _T_4912.ready <= TLBuffer.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4912.valid <= RocketTile.io.master.0.e.valid @[Bundles.scala 216:15] + _T_4912.bits <- RocketTile.io.master.0.e.bits @[Bundles.scala 217:15] + _T_4731.e <- _T_4912 @[Bundles.scala 239:11] + TLMonitor_17.io.in[0] <- _T_4731 @[RocketTiles.scala 50:21] + wire _T_5003 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_5003 is invalid @[Bundles.scala 234:19] + wire _T_5100 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5100 is invalid @[Bundles.scala 214:19] + _T_5100.ready <= TLBuffer.io.in.1.a.ready @[Bundles.scala 215:15] + _T_5100.valid <= RocketTile.io.master.1.a.valid @[Bundles.scala 216:15] + _T_5100.bits <- RocketTile.io.master.1.a.bits @[Bundles.scala 217:15] + _T_5003.a <- _T_5100 @[Bundles.scala 235:11] + wire _T_5122 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5122 is invalid @[Bundles.scala 214:19] + _T_5122.ready <= RocketTile.io.master.1.b.ready @[Bundles.scala 215:15] + _T_5122.valid <= TLBuffer.io.in.1.b.valid @[Bundles.scala 216:15] + _T_5122.bits <- TLBuffer.io.in.1.b.bits @[Bundles.scala 217:15] + _T_5003.b <- _T_5122 @[Bundles.scala 236:11] + wire _T_5144 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5144 is invalid @[Bundles.scala 214:19] + _T_5144.ready <= TLBuffer.io.in.1.c.ready @[Bundles.scala 215:15] + _T_5144.valid <= RocketTile.io.master.1.c.valid @[Bundles.scala 216:15] + _T_5144.bits <- RocketTile.io.master.1.c.bits @[Bundles.scala 217:15] + _T_5003.c <- _T_5144 @[Bundles.scala 237:11] + wire _T_5167 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5167 is invalid @[Bundles.scala 214:19] + _T_5167.ready <= RocketTile.io.master.1.d.ready @[Bundles.scala 215:15] + _T_5167.valid <= TLBuffer.io.in.1.d.valid @[Bundles.scala 216:15] + _T_5167.bits <- TLBuffer.io.in.1.d.bits @[Bundles.scala 217:15] + _T_5003.d <- _T_5167 @[Bundles.scala 238:11] + wire _T_5184 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_5184 is invalid @[Bundles.scala 214:19] + _T_5184.ready <= TLBuffer.io.in.1.e.ready @[Bundles.scala 215:15] + _T_5184.valid <= RocketTile.io.master.1.e.valid @[Bundles.scala 216:15] + _T_5184.bits <- RocketTile.io.master.1.e.bits @[Bundles.scala 217:15] + _T_5003.e <- _T_5184 @[Bundles.scala 239:11] + TLMonitor_17.io.in[1] <- _T_5003 @[RocketTiles.scala 50:21] + TLBuffer.io.in.0 <- RocketTile.io.master.0 @[RocketTiles.scala 50:21] + TLBuffer.io.in.1 <- RocketTile.io.master.1 @[RocketTiles.scala 50:21] + wire _T_5275 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_5275 is invalid @[Bundles.scala 234:19] + wire _T_5372 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5372 is invalid @[Bundles.scala 214:19] + _T_5372.ready <= l1tol2.io.in.1.a.ready @[Bundles.scala 215:15] + _T_5372.valid <= TLBuffer.io.out.0.a.valid @[Bundles.scala 216:15] + _T_5372.bits <- TLBuffer.io.out.0.a.bits @[Bundles.scala 217:15] + _T_5275.a <- _T_5372 @[Bundles.scala 235:11] + wire _T_5394 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5394 is invalid @[Bundles.scala 214:19] + _T_5394.ready <= TLBuffer.io.out.0.b.ready @[Bundles.scala 215:15] + _T_5394.valid <= l1tol2.io.in.1.b.valid @[Bundles.scala 216:15] + _T_5394.bits <- l1tol2.io.in.1.b.bits @[Bundles.scala 217:15] + _T_5275.b <- _T_5394 @[Bundles.scala 236:11] + wire _T_5416 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5416 is invalid @[Bundles.scala 214:19] + _T_5416.ready <= l1tol2.io.in.1.c.ready @[Bundles.scala 215:15] + _T_5416.valid <= TLBuffer.io.out.0.c.valid @[Bundles.scala 216:15] + _T_5416.bits <- TLBuffer.io.out.0.c.bits @[Bundles.scala 217:15] + _T_5275.c <- _T_5416 @[Bundles.scala 237:11] + wire _T_5439 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5439 is invalid @[Bundles.scala 214:19] + _T_5439.ready <= TLBuffer.io.out.0.d.ready @[Bundles.scala 215:15] + _T_5439.valid <= l1tol2.io.in.1.d.valid @[Bundles.scala 216:15] + _T_5439.bits <- l1tol2.io.in.1.d.bits @[Bundles.scala 217:15] + _T_5275.d <- _T_5439 @[Bundles.scala 238:11] + wire _T_5456 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_5456 is invalid @[Bundles.scala 214:19] + _T_5456.ready <= l1tol2.io.in.1.e.ready @[Bundles.scala 215:15] + _T_5456.valid <= TLBuffer.io.out.0.e.valid @[Bundles.scala 216:15] + _T_5456.bits <- TLBuffer.io.out.0.e.bits @[Bundles.scala 217:15] + _T_5275.e <- _T_5456 @[Bundles.scala 239:11] + TLMonitor_18.io.in[0] <- _T_5275 @[RocketTiles.scala 51:21] + wire _T_5547 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_5547 is invalid @[Bundles.scala 234:19] + wire _T_5644 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5644 is invalid @[Bundles.scala 214:19] + _T_5644.ready <= l1tol2.io.in.2.a.ready @[Bundles.scala 215:15] + _T_5644.valid <= TLBuffer.io.out.1.a.valid @[Bundles.scala 216:15] + _T_5644.bits <- TLBuffer.io.out.1.a.bits @[Bundles.scala 217:15] + _T_5547.a <- _T_5644 @[Bundles.scala 235:11] + wire _T_5666 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5666 is invalid @[Bundles.scala 214:19] + _T_5666.ready <= TLBuffer.io.out.1.b.ready @[Bundles.scala 215:15] + _T_5666.valid <= l1tol2.io.in.2.b.valid @[Bundles.scala 216:15] + _T_5666.bits <- l1tol2.io.in.2.b.bits @[Bundles.scala 217:15] + _T_5547.b <- _T_5666 @[Bundles.scala 236:11] + wire _T_5688 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5688 is invalid @[Bundles.scala 214:19] + _T_5688.ready <= l1tol2.io.in.2.c.ready @[Bundles.scala 215:15] + _T_5688.valid <= TLBuffer.io.out.1.c.valid @[Bundles.scala 216:15] + _T_5688.bits <- TLBuffer.io.out.1.c.bits @[Bundles.scala 217:15] + _T_5547.c <- _T_5688 @[Bundles.scala 237:11] + wire _T_5711 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5711 is invalid @[Bundles.scala 214:19] + _T_5711.ready <= TLBuffer.io.out.1.d.ready @[Bundles.scala 215:15] + _T_5711.valid <= l1tol2.io.in.2.d.valid @[Bundles.scala 216:15] + _T_5711.bits <- l1tol2.io.in.2.d.bits @[Bundles.scala 217:15] + _T_5547.d <- _T_5711 @[Bundles.scala 238:11] + wire _T_5728 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_5728 is invalid @[Bundles.scala 214:19] + _T_5728.ready <= l1tol2.io.in.2.e.ready @[Bundles.scala 215:15] + _T_5728.valid <= TLBuffer.io.out.1.e.valid @[Bundles.scala 216:15] + _T_5728.bits <- TLBuffer.io.out.1.e.bits @[Bundles.scala 217:15] + _T_5547.e <- _T_5728 @[Bundles.scala 239:11] + TLMonitor_18.io.in[1] <- _T_5547 @[RocketTiles.scala 51:21] + l1tol2.io.in.1 <- TLBuffer.io.out.0 @[RocketTiles.scala 51:21] + l1tol2.io.in.2 <- TLBuffer.io.out.1 @[RocketTiles.scala 51:21] + RocketTile.io.interrupts.0 <- IntXbar.io.out.0 @[RocketTiles.scala 53:22] + wire _T_5912 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}} @[Debug.scala 318:19] + _T_5912 is invalid @[Debug.scala 318:19] + inst AsyncQueueSink of AsyncQueueSink @[AsyncBundle.scala 25:22] + AsyncQueueSink.io is invalid + AsyncQueueSink.clock <= clock + AsyncQueueSink.reset <= reset + io.debug.req.ridx <= AsyncQueueSink.io.ridx @[AsyncBundle.scala 26:12] + io.debug.req.ridx_valid <= AsyncQueueSink.io.ridx_valid @[AsyncBundle.scala 27:18] + AsyncQueueSink.io.widx <= io.debug.req.widx @[AsyncBundle.scala 28:18] + AsyncQueueSink.io.widx_valid <= io.debug.req.widx_valid @[AsyncBundle.scala 29:24] + AsyncQueueSink.io.mem <- io.debug.req.mem @[AsyncBundle.scala 30:18] + AsyncQueueSink.io.source_reset_n <= io.debug.req.source_reset_n @[AsyncBundle.scala 31:28] + node _T_5956 = eq(AsyncQueueSink.reset, UInt<1>("h00")) @[AsyncBundle.scala 32:23] + io.debug.req.sink_reset_n <= _T_5956 @[AsyncBundle.scala 32:20] + wire _T_5970 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}} @[AsyncBundle.scala 33:19] + _T_5970 is invalid @[AsyncBundle.scala 33:19] + _T_5970.valid <= AsyncQueueSink.io.deq.valid @[AsyncBundle.scala 34:15] + _T_5970.bits <- AsyncQueueSink.io.deq.bits @[AsyncBundle.scala 35:14] + AsyncQueueSink.io.deq.ready <= _T_5970.ready @[AsyncBundle.scala 36:23] + _T_5912.req <- _T_5970 @[Debug.scala 319:13] + inst AsyncQueueSource of AsyncQueueSource @[AsyncBundle.scala 44:24] + AsyncQueueSource.io is invalid + AsyncQueueSource.clock <= clock + AsyncQueueSource.reset <= reset + AsyncQueueSource.io.enq.valid <= _T_5912.resp.valid @[AsyncBundle.scala 45:25] + AsyncQueueSource.io.enq.bits <- _T_5912.resp.bits @[AsyncBundle.scala 46:24] + _T_5912.resp.ready <= AsyncQueueSource.io.enq.ready @[AsyncBundle.scala 47:13] + wire _T_5999 : {mem : {data : UInt<34>, resp : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>} @[AsyncBundle.scala 48:19] + _T_5999 is invalid @[AsyncBundle.scala 48:19] + AsyncQueueSource.io.ridx <= _T_5999.ridx @[AsyncBundle.scala 49:20] + AsyncQueueSource.io.ridx_valid <= _T_5999.ridx_valid @[AsyncBundle.scala 50:26] + _T_5999.mem <- AsyncQueueSource.io.mem @[AsyncBundle.scala 51:13] + _T_5999.widx <= AsyncQueueSource.io.widx @[AsyncBundle.scala 52:14] + _T_5999.widx_valid <= AsyncQueueSource.io.widx_valid @[AsyncBundle.scala 53:20] + AsyncQueueSource.io.sink_reset_n <= _T_5999.sink_reset_n @[AsyncBundle.scala 54:28] + node _T_6016 = eq(AsyncQueueSource.reset, UInt<1>("h00")) @[AsyncBundle.scala 55:27] + _T_5999.source_reset_n <= _T_6016 @[AsyncBundle.scala 55:24] + io.debug.resp <- _T_5999 @[Debug.scala 320:12] + debug.io.db <- _T_5912 @[RISCVPlatform.scala 44:28] + reg _T_6019 : UInt<1>, clock @[Reg.scala 34:16] + when UInt<1>("h01") : @[Reg.scala 35:19] + _T_6019 <= io.rtcToggle @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_6021 : UInt<1>, clock @[Reg.scala 34:16] + when UInt<1>("h01") : @[Reg.scala 35:19] + _T_6021 <= _T_6019 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg rtcSync : UInt<1>, clock @[Reg.scala 34:16] + when UInt<1>("h01") : @[Reg.scala 35:19] + rtcSync <= _T_6021 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg rtcLast : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[RISCVPlatform.scala 48:20] + rtcLast <= rtcSync @[RISCVPlatform.scala 48:20] + node _T_6025 = not(rtcLast) @[RISCVPlatform.scala 49:77] + node _T_6026 = and(rtcSync, _T_6025) @[RISCVPlatform.scala 49:74] + reg _T_6027 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[RISCVPlatform.scala 49:39] + _T_6027 <= _T_6026 @[RISCVPlatform.scala 49:39] + clint.io.rtcTick <= _T_6027 @[RISCVPlatform.scala 49:33] + RocketTile.io.hartid <= UInt<1>("h00") @[RocketTiles.scala 56:33] + RocketTile.io.resetVector <= io.resetVector @[RocketTiles.scala 57:38] + _T_4644.0[0] <= debug.io.debugInterrupts[0] @[RocketTiles.scala 58:37] + + module TLMonitor_37 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RocketPlexMaster.scala 18:17] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RocketPlexMaster.scala 18:17] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_608 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + when _T_700 : @[RocketPlexMaster.scala 18:17] + node _T_703 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_705 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_706 = and(_T_703, _T_705) @[Parameters.scala 63:37] + node _T_707 = or(UInt<1>("h00"), _T_706) @[Parameters.scala 132:31] + node _T_709 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_710 = cvt(_T_709) @[Parameters.scala 117:49] + node _T_712 = and(_T_710, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_713 = asSInt(_T_712) @[Parameters.scala 117:52] + node _T_715 = eq(_T_713, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_717 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_718 = cvt(_T_717) @[Parameters.scala 117:49] + node _T_720 = and(_T_718, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_721 = asSInt(_T_720) @[Parameters.scala 117:52] + node _T_723 = eq(_T_721, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_724 = or(_T_715, _T_723) @[Parameters.scala 133:42] + node _T_725 = and(_T_707, _T_724) @[Parameters.scala 132:56] + node _T_728 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_730 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_731 = cvt(_T_730) @[Parameters.scala 117:49] + node _T_733 = and(_T_731, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_734 = asSInt(_T_733) @[Parameters.scala 117:52] + node _T_736 = eq(_T_734, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_738 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_739 = cvt(_T_738) @[Parameters.scala 117:49] + node _T_741 = and(_T_739, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_742 = asSInt(_T_741) @[Parameters.scala 117:52] + node _T_744 = eq(_T_742, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_746 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_747 = cvt(_T_746) @[Parameters.scala 117:49] + node _T_749 = and(_T_747, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_750 = asSInt(_T_749) @[Parameters.scala 117:52] + node _T_752 = eq(_T_750, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_754 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_755 = cvt(_T_754) @[Parameters.scala 117:49] + node _T_757 = and(_T_755, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_758 = asSInt(_T_757) @[Parameters.scala 117:52] + node _T_760 = eq(_T_758, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_761 = or(_T_736, _T_744) @[Parameters.scala 133:42] + node _T_762 = or(_T_761, _T_752) @[Parameters.scala 133:42] + node _T_763 = or(_T_762, _T_760) @[Parameters.scala 133:42] + node _T_764 = and(_T_728, _T_763) @[Parameters.scala 132:56] + node _T_766 = or(UInt<1>("h00"), _T_725) @[Parameters.scala 134:30] + node _T_767 = or(_T_766, _T_764) @[Parameters.scala 134:30] + node _T_768 = or(_T_767, reset) @[RocketPlexMaster.scala 18:17] + node _T_770 = eq(_T_768, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_770 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_771 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_773 = eq(_T_771, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_773 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_775 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_776 = or(_T_775, reset) @[RocketPlexMaster.scala 18:17] + node _T_778 = eq(_T_776, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_778 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_779 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_781 = eq(_T_779, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_781 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_783 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_784 = or(_T_783, reset) @[RocketPlexMaster.scala 18:17] + node _T_786 = eq(_T_784, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_786 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_787 = not(io.in[0].a.bits.mask) @[RocketPlexMaster.scala 18:17] + node _T_789 = eq(_T_787, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_790 = or(_T_789, reset) @[RocketPlexMaster.scala 18:17] + node _T_792 = eq(_T_790, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_792 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_794 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 18:17] + when _T_794 : @[RocketPlexMaster.scala 18:17] + node _T_797 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_799 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_800 = and(_T_797, _T_799) @[Parameters.scala 63:37] + node _T_801 = or(UInt<1>("h00"), _T_800) @[Parameters.scala 132:31] + node _T_803 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_804 = cvt(_T_803) @[Parameters.scala 117:49] + node _T_806 = and(_T_804, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_807 = asSInt(_T_806) @[Parameters.scala 117:52] + node _T_809 = eq(_T_807, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_811 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_812 = cvt(_T_811) @[Parameters.scala 117:49] + node _T_814 = and(_T_812, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_815 = asSInt(_T_814) @[Parameters.scala 117:52] + node _T_817 = eq(_T_815, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_819 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_820 = cvt(_T_819) @[Parameters.scala 117:49] + node _T_822 = and(_T_820, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_823 = asSInt(_T_822) @[Parameters.scala 117:52] + node _T_825 = eq(_T_823, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_827 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_828 = cvt(_T_827) @[Parameters.scala 117:49] + node _T_830 = and(_T_828, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_831 = asSInt(_T_830) @[Parameters.scala 117:52] + node _T_833 = eq(_T_831, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_835 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_836 = cvt(_T_835) @[Parameters.scala 117:49] + node _T_838 = and(_T_836, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_839 = asSInt(_T_838) @[Parameters.scala 117:52] + node _T_841 = eq(_T_839, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_842 = or(_T_809, _T_817) @[Parameters.scala 133:42] + node _T_843 = or(_T_842, _T_825) @[Parameters.scala 133:42] + node _T_844 = or(_T_843, _T_833) @[Parameters.scala 133:42] + node _T_845 = or(_T_844, _T_841) @[Parameters.scala 133:42] + node _T_846 = and(_T_801, _T_845) @[Parameters.scala 132:56] + node _T_849 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_851 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_852 = and(_T_849, _T_851) @[Parameters.scala 63:37] + node _T_853 = or(UInt<1>("h00"), _T_852) @[Parameters.scala 132:31] + node _T_855 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_856 = cvt(_T_855) @[Parameters.scala 117:49] + node _T_858 = and(_T_856, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_859 = asSInt(_T_858) @[Parameters.scala 117:52] + node _T_861 = eq(_T_859, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_862 = and(_T_853, _T_861) @[Parameters.scala 132:56] + node _T_864 = or(UInt<1>("h00"), _T_846) @[Parameters.scala 134:30] + node _T_865 = or(_T_864, _T_862) @[Parameters.scala 134:30] + node _T_866 = or(_T_865, reset) @[RocketPlexMaster.scala 18:17] + node _T_868 = eq(_T_866, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_868 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_869 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_871 = eq(_T_869, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_871 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_872 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_874 = eq(_T_872, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_874 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_876 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_877 = or(_T_876, reset) @[RocketPlexMaster.scala 18:17] + node _T_879 = eq(_T_877, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_879 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_880 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 18:17] + node _T_881 = or(_T_880, reset) @[RocketPlexMaster.scala 18:17] + node _T_883 = eq(_T_881, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_883 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_885 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_885 : @[RocketPlexMaster.scala 18:17] + node _T_888 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_890 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_891 = and(_T_888, _T_890) @[Parameters.scala 63:37] + node _T_892 = or(UInt<1>("h00"), _T_891) @[Parameters.scala 132:31] + node _T_894 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_895 = cvt(_T_894) @[Parameters.scala 117:49] + node _T_897 = and(_T_895, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_898 = asSInt(_T_897) @[Parameters.scala 117:52] + node _T_900 = eq(_T_898, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_902 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_903 = cvt(_T_902) @[Parameters.scala 117:49] + node _T_905 = and(_T_903, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_906 = asSInt(_T_905) @[Parameters.scala 117:52] + node _T_908 = eq(_T_906, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_910 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_911 = cvt(_T_910) @[Parameters.scala 117:49] + node _T_913 = and(_T_911, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_914 = asSInt(_T_913) @[Parameters.scala 117:52] + node _T_916 = eq(_T_914, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_918 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_919 = cvt(_T_918) @[Parameters.scala 117:49] + node _T_921 = and(_T_919, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_922 = asSInt(_T_921) @[Parameters.scala 117:52] + node _T_924 = eq(_T_922, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_926 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_927 = cvt(_T_926) @[Parameters.scala 117:49] + node _T_929 = and(_T_927, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_930 = asSInt(_T_929) @[Parameters.scala 117:52] + node _T_932 = eq(_T_930, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_933 = or(_T_900, _T_908) @[Parameters.scala 133:42] + node _T_934 = or(_T_933, _T_916) @[Parameters.scala 133:42] + node _T_935 = or(_T_934, _T_924) @[Parameters.scala 133:42] + node _T_936 = or(_T_935, _T_932) @[Parameters.scala 133:42] + node _T_937 = and(_T_892, _T_936) @[Parameters.scala 132:56] + node _T_940 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_942 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_943 = and(_T_940, _T_942) @[Parameters.scala 63:37] + node _T_944 = or(UInt<1>("h00"), _T_943) @[Parameters.scala 132:31] + node _T_946 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_947 = cvt(_T_946) @[Parameters.scala 117:49] + node _T_949 = and(_T_947, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_950 = asSInt(_T_949) @[Parameters.scala 117:52] + node _T_952 = eq(_T_950, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_953 = and(_T_944, _T_952) @[Parameters.scala 132:56] + node _T_956 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_958 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_959 = cvt(_T_958) @[Parameters.scala 117:49] + node _T_961 = and(_T_959, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_962 = asSInt(_T_961) @[Parameters.scala 117:52] + node _T_964 = eq(_T_962, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_965 = and(_T_956, _T_964) @[Parameters.scala 132:56] + node _T_967 = or(UInt<1>("h00"), _T_937) @[Parameters.scala 134:30] + node _T_968 = or(_T_967, _T_953) @[Parameters.scala 134:30] + node _T_969 = or(_T_968, _T_965) @[Parameters.scala 134:30] + node _T_970 = or(_T_969, reset) @[RocketPlexMaster.scala 18:17] + node _T_972 = eq(_T_970, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_972 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_973 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_975 = eq(_T_973, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_975 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_976 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_978 = eq(_T_976, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_978 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_980 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_981 = or(_T_980, reset) @[RocketPlexMaster.scala 18:17] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_983 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_984 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 18:17] + node _T_985 = or(_T_984, reset) @[RocketPlexMaster.scala 18:17] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_987 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_989 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 18:17] + when _T_989 : @[RocketPlexMaster.scala 18:17] + node _T_992 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_994 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_995 = and(_T_992, _T_994) @[Parameters.scala 63:37] + node _T_996 = or(UInt<1>("h00"), _T_995) @[Parameters.scala 132:31] + node _T_998 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_999 = cvt(_T_998) @[Parameters.scala 117:49] + node _T_1001 = and(_T_999, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1002 = asSInt(_T_1001) @[Parameters.scala 117:52] + node _T_1004 = eq(_T_1002, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1006 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1007 = cvt(_T_1006) @[Parameters.scala 117:49] + node _T_1009 = and(_T_1007, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1010 = asSInt(_T_1009) @[Parameters.scala 117:52] + node _T_1012 = eq(_T_1010, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1014 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1015 = cvt(_T_1014) @[Parameters.scala 117:49] + node _T_1017 = and(_T_1015, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1018 = asSInt(_T_1017) @[Parameters.scala 117:52] + node _T_1020 = eq(_T_1018, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1022 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1023 = cvt(_T_1022) @[Parameters.scala 117:49] + node _T_1025 = and(_T_1023, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1026 = asSInt(_T_1025) @[Parameters.scala 117:52] + node _T_1028 = eq(_T_1026, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1030 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1031 = cvt(_T_1030) @[Parameters.scala 117:49] + node _T_1033 = and(_T_1031, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1034 = asSInt(_T_1033) @[Parameters.scala 117:52] + node _T_1036 = eq(_T_1034, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1037 = or(_T_1004, _T_1012) @[Parameters.scala 133:42] + node _T_1038 = or(_T_1037, _T_1020) @[Parameters.scala 133:42] + node _T_1039 = or(_T_1038, _T_1028) @[Parameters.scala 133:42] + node _T_1040 = or(_T_1039, _T_1036) @[Parameters.scala 133:42] + node _T_1041 = and(_T_996, _T_1040) @[Parameters.scala 132:56] + node _T_1044 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1046 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_1047 = and(_T_1044, _T_1046) @[Parameters.scala 63:37] + node _T_1048 = or(UInt<1>("h00"), _T_1047) @[Parameters.scala 132:31] + node _T_1050 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1051 = cvt(_T_1050) @[Parameters.scala 117:49] + node _T_1053 = and(_T_1051, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1054 = asSInt(_T_1053) @[Parameters.scala 117:52] + node _T_1056 = eq(_T_1054, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1057 = and(_T_1048, _T_1056) @[Parameters.scala 132:56] + node _T_1060 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1062 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1063 = cvt(_T_1062) @[Parameters.scala 117:49] + node _T_1065 = and(_T_1063, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1066 = asSInt(_T_1065) @[Parameters.scala 117:52] + node _T_1068 = eq(_T_1066, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1069 = and(_T_1060, _T_1068) @[Parameters.scala 132:56] + node _T_1071 = or(UInt<1>("h00"), _T_1041) @[Parameters.scala 134:30] + node _T_1072 = or(_T_1071, _T_1057) @[Parameters.scala 134:30] + node _T_1073 = or(_T_1072, _T_1069) @[Parameters.scala 134:30] + node _T_1074 = or(_T_1073, reset) @[RocketPlexMaster.scala 18:17] + node _T_1076 = eq(_T_1074, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1076 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1077 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1079 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1080 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_1082 = eq(_T_1080, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1082 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1084 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1085 = or(_T_1084, reset) @[RocketPlexMaster.scala 18:17] + node _T_1087 = eq(_T_1085, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1087 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1088 = not(_T_698) @[RocketPlexMaster.scala 18:17] + node _T_1089 = and(io.in[0].a.bits.mask, _T_1088) @[RocketPlexMaster.scala 18:17] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1092 = or(_T_1091, reset) @[RocketPlexMaster.scala 18:17] + node _T_1094 = eq(_T_1092, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1094 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1096 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 18:17] + when _T_1096 : @[RocketPlexMaster.scala 18:17] + node _T_1099 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1101 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1102 = and(_T_1099, _T_1101) @[Parameters.scala 63:37] + node _T_1103 = or(UInt<1>("h00"), _T_1102) @[Parameters.scala 132:31] + node _T_1105 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1106 = cvt(_T_1105) @[Parameters.scala 117:49] + node _T_1108 = and(_T_1106, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1109 = asSInt(_T_1108) @[Parameters.scala 117:52] + node _T_1111 = eq(_T_1109, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1113 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1114 = cvt(_T_1113) @[Parameters.scala 117:49] + node _T_1116 = and(_T_1114, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1117 = asSInt(_T_1116) @[Parameters.scala 117:52] + node _T_1119 = eq(_T_1117, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1121 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1122 = cvt(_T_1121) @[Parameters.scala 117:49] + node _T_1124 = and(_T_1122, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1125 = asSInt(_T_1124) @[Parameters.scala 117:52] + node _T_1127 = eq(_T_1125, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1128 = or(_T_1111, _T_1119) @[Parameters.scala 133:42] + node _T_1129 = or(_T_1128, _T_1127) @[Parameters.scala 133:42] + node _T_1130 = and(_T_1103, _T_1129) @[Parameters.scala 132:56] + node _T_1133 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1135 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1136 = cvt(_T_1135) @[Parameters.scala 117:49] + node _T_1138 = and(_T_1136, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1139 = asSInt(_T_1138) @[Parameters.scala 117:52] + node _T_1141 = eq(_T_1139, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1143 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1144 = cvt(_T_1143) @[Parameters.scala 117:49] + node _T_1146 = and(_T_1144, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1147 = asSInt(_T_1146) @[Parameters.scala 117:52] + node _T_1149 = eq(_T_1147, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1151 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1152 = cvt(_T_1151) @[Parameters.scala 117:49] + node _T_1154 = and(_T_1152, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1155 = asSInt(_T_1154) @[Parameters.scala 117:52] + node _T_1157 = eq(_T_1155, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1159 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1160 = cvt(_T_1159) @[Parameters.scala 117:49] + node _T_1162 = and(_T_1160, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1163 = asSInt(_T_1162) @[Parameters.scala 117:52] + node _T_1165 = eq(_T_1163, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1166 = or(_T_1141, _T_1149) @[Parameters.scala 133:42] + node _T_1167 = or(_T_1166, _T_1157) @[Parameters.scala 133:42] + node _T_1168 = or(_T_1167, _T_1165) @[Parameters.scala 133:42] + node _T_1169 = and(_T_1133, _T_1168) @[Parameters.scala 132:56] + node _T_1171 = or(UInt<1>("h00"), _T_1130) @[Parameters.scala 134:30] + node _T_1172 = or(_T_1171, _T_1169) @[Parameters.scala 134:30] + node _T_1173 = or(_T_1172, reset) @[RocketPlexMaster.scala 18:17] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1175 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1176 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1178 = eq(_T_1176, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1178 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1179 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_1181 = eq(_T_1179, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1181 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1183 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1184 = or(_T_1183, reset) @[RocketPlexMaster.scala 18:17] + node _T_1186 = eq(_T_1184, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1186 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1187 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 18:17] + node _T_1188 = or(_T_1187, reset) @[RocketPlexMaster.scala 18:17] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1190 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1192 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + when _T_1192 : @[RocketPlexMaster.scala 18:17] + node _T_1195 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_1197 = leq(io.in[0].a.bits.size, UInt<2>("h03")) @[Parameters.scala 63:42] + node _T_1198 = and(_T_1195, _T_1197) @[Parameters.scala 63:37] + node _T_1199 = or(UInt<1>("h00"), _T_1198) @[Parameters.scala 132:31] + node _T_1201 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1202 = cvt(_T_1201) @[Parameters.scala 117:49] + node _T_1204 = and(_T_1202, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1205 = asSInt(_T_1204) @[Parameters.scala 117:52] + node _T_1207 = eq(_T_1205, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1209 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1210 = cvt(_T_1209) @[Parameters.scala 117:49] + node _T_1212 = and(_T_1210, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1213 = asSInt(_T_1212) @[Parameters.scala 117:52] + node _T_1215 = eq(_T_1213, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1217 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1218 = cvt(_T_1217) @[Parameters.scala 117:49] + node _T_1220 = and(_T_1218, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1221 = asSInt(_T_1220) @[Parameters.scala 117:52] + node _T_1223 = eq(_T_1221, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1224 = or(_T_1207, _T_1215) @[Parameters.scala 133:42] + node _T_1225 = or(_T_1224, _T_1223) @[Parameters.scala 133:42] + node _T_1226 = and(_T_1199, _T_1225) @[Parameters.scala 132:56] + node _T_1229 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1231 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1232 = cvt(_T_1231) @[Parameters.scala 117:49] + node _T_1234 = and(_T_1232, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1235 = asSInt(_T_1234) @[Parameters.scala 117:52] + node _T_1237 = eq(_T_1235, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1239 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1240 = cvt(_T_1239) @[Parameters.scala 117:49] + node _T_1242 = and(_T_1240, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1243 = asSInt(_T_1242) @[Parameters.scala 117:52] + node _T_1245 = eq(_T_1243, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1247 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1248 = cvt(_T_1247) @[Parameters.scala 117:49] + node _T_1250 = and(_T_1248, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1251 = asSInt(_T_1250) @[Parameters.scala 117:52] + node _T_1253 = eq(_T_1251, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1255 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1256 = cvt(_T_1255) @[Parameters.scala 117:49] + node _T_1258 = and(_T_1256, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1259 = asSInt(_T_1258) @[Parameters.scala 117:52] + node _T_1261 = eq(_T_1259, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1262 = or(_T_1237, _T_1245) @[Parameters.scala 133:42] + node _T_1263 = or(_T_1262, _T_1253) @[Parameters.scala 133:42] + node _T_1264 = or(_T_1263, _T_1261) @[Parameters.scala 133:42] + node _T_1265 = and(_T_1229, _T_1264) @[Parameters.scala 132:56] + node _T_1267 = or(UInt<1>("h00"), _T_1226) @[Parameters.scala 134:30] + node _T_1268 = or(_T_1267, _T_1265) @[Parameters.scala 134:30] + node _T_1269 = or(_T_1268, reset) @[RocketPlexMaster.scala 18:17] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1271 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1272 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1274 = eq(_T_1272, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1274 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1275 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1277 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1279 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1280 = or(_T_1279, reset) @[RocketPlexMaster.scala 18:17] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1282 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1283 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 18:17] + node _T_1284 = or(_T_1283, reset) @[RocketPlexMaster.scala 18:17] + node _T_1286 = eq(_T_1284, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1286 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1288 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 18:17] + when _T_1288 : @[RocketPlexMaster.scala 18:17] + node _T_1291 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1293 = xor(io.in[0].a.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1294 = cvt(_T_1293) @[Parameters.scala 117:49] + node _T_1296 = and(_T_1294, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1297 = asSInt(_T_1296) @[Parameters.scala 117:52] + node _T_1299 = eq(_T_1297, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1301 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1302 = cvt(_T_1301) @[Parameters.scala 117:49] + node _T_1304 = and(_T_1302, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1305 = asSInt(_T_1304) @[Parameters.scala 117:52] + node _T_1307 = eq(_T_1305, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1309 = xor(io.in[0].a.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1310 = cvt(_T_1309) @[Parameters.scala 117:49] + node _T_1312 = and(_T_1310, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1313 = asSInt(_T_1312) @[Parameters.scala 117:52] + node _T_1315 = eq(_T_1313, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1317 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1318 = cvt(_T_1317) @[Parameters.scala 117:49] + node _T_1320 = and(_T_1318, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1321 = asSInt(_T_1320) @[Parameters.scala 117:52] + node _T_1323 = eq(_T_1321, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1325 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1326 = cvt(_T_1325) @[Parameters.scala 117:49] + node _T_1328 = and(_T_1326, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1329 = asSInt(_T_1328) @[Parameters.scala 117:52] + node _T_1331 = eq(_T_1329, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1333 = xor(io.in[0].a.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1334 = cvt(_T_1333) @[Parameters.scala 117:49] + node _T_1336 = and(_T_1334, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1337 = asSInt(_T_1336) @[Parameters.scala 117:52] + node _T_1339 = eq(_T_1337, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1340 = or(_T_1299, _T_1307) @[Parameters.scala 133:42] + node _T_1341 = or(_T_1340, _T_1315) @[Parameters.scala 133:42] + node _T_1342 = or(_T_1341, _T_1323) @[Parameters.scala 133:42] + node _T_1343 = or(_T_1342, _T_1331) @[Parameters.scala 133:42] + node _T_1344 = or(_T_1343, _T_1339) @[Parameters.scala 133:42] + node _T_1345 = and(_T_1291, _T_1344) @[Parameters.scala 132:56] + node _T_1347 = or(UInt<1>("h00"), _T_1345) @[Parameters.scala 134:30] + node _T_1348 = or(_T_1347, reset) @[RocketPlexMaster.scala 18:17] + node _T_1350 = eq(_T_1348, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1350 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1351 = or(_T_619[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1353 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1354 = or(_T_630, reset) @[RocketPlexMaster.scala 18:17] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1356 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1357 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 18:17] + node _T_1358 = or(_T_1357, reset) @[RocketPlexMaster.scala 18:17] + node _T_1360 = eq(_T_1358, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1360 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + when io.in[0].b.valid : @[RocketPlexMaster.scala 18:17] + node _T_1362 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1363 = or(_T_1362, reset) @[RocketPlexMaster.scala 18:17] + node _T_1365 = eq(_T_1363, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1365 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1367 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1368 = cvt(_T_1367) @[Parameters.scala 117:49] + node _T_1370 = and(_T_1368, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1371 = asSInt(_T_1370) @[Parameters.scala 117:52] + node _T_1373 = eq(_T_1371, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1375 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1376 = cvt(_T_1375) @[Parameters.scala 117:49] + node _T_1378 = and(_T_1376, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1379 = asSInt(_T_1378) @[Parameters.scala 117:52] + node _T_1381 = eq(_T_1379, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1383 = xor(io.in[0].b.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1384 = cvt(_T_1383) @[Parameters.scala 117:49] + node _T_1386 = and(_T_1384, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1387 = asSInt(_T_1386) @[Parameters.scala 117:52] + node _T_1389 = eq(_T_1387, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1391 = xor(io.in[0].b.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1392 = cvt(_T_1391) @[Parameters.scala 117:49] + node _T_1394 = and(_T_1392, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1395 = asSInt(_T_1394) @[Parameters.scala 117:52] + node _T_1397 = eq(_T_1395, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1399 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1400 = cvt(_T_1399) @[Parameters.scala 117:49] + node _T_1402 = and(_T_1400, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1403 = asSInt(_T_1402) @[Parameters.scala 117:52] + node _T_1405 = eq(_T_1403, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1407 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].b.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1424 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1424 is invalid @[Parameters.scala 110:36] + _T_1424[0] <= _T_1373 @[Parameters.scala 110:36] + _T_1424[1] <= _T_1381 @[Parameters.scala 110:36] + _T_1424[2] <= _T_1389 @[Parameters.scala 110:36] + _T_1424[3] <= _T_1397 @[Parameters.scala 110:36] + _T_1424[4] <= _T_1405 @[Parameters.scala 110:36] + _T_1424[5] <= _T_1413 @[Parameters.scala 110:36] + _T_1424[6] <= _T_1421 @[Parameters.scala 110:36] + node _T_1434 = or(_T_1424[0], _T_1424[1]) @[Parameters.scala 119:64] + node _T_1435 = or(_T_1434, _T_1424[2]) @[Parameters.scala 119:64] + node _T_1436 = or(_T_1435, _T_1424[3]) @[Parameters.scala 119:64] + node _T_1437 = or(_T_1436, _T_1424[4]) @[Parameters.scala 119:64] + node _T_1438 = or(_T_1437, _T_1424[5]) @[Parameters.scala 119:64] + node _T_1439 = or(_T_1438, _T_1424[6]) @[Parameters.scala 119:64] + node _T_1441 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1442 = dshl(_T_1441, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1443 = bits(_T_1442, 7, 0) @[package.scala 19:76] + node _T_1444 = not(_T_1443) @[package.scala 19:40] + node _T_1445 = and(io.in[0].b.bits.address, _T_1444) @[Edges.scala 17:16] + node _T_1447 = eq(_T_1445, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1449 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1450 = dshl(UInt<1>("h01"), _T_1449) @[OneHot.scala 49:12] + node _T_1451 = bits(_T_1450, 2, 0) @[OneHot.scala 49:37] + node _T_1453 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1455 = bits(_T_1451, 2, 2) @[package.scala 44:26] + node _T_1456 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1458 = eq(_T_1456, UInt<1>("h00")) @[package.scala 46:20] + node _T_1459 = and(UInt<1>("h01"), _T_1458) @[package.scala 49:27] + node _T_1460 = and(_T_1455, _T_1459) @[package.scala 50:38] + node _T_1461 = or(_T_1453, _T_1460) @[package.scala 50:29] + node _T_1462 = and(UInt<1>("h01"), _T_1456) @[package.scala 49:27] + node _T_1463 = and(_T_1455, _T_1462) @[package.scala 50:38] + node _T_1464 = or(_T_1453, _T_1463) @[package.scala 50:29] + node _T_1465 = bits(_T_1451, 1, 1) @[package.scala 44:26] + node _T_1466 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1468 = eq(_T_1466, UInt<1>("h00")) @[package.scala 46:20] + node _T_1469 = and(_T_1459, _T_1468) @[package.scala 49:27] + node _T_1470 = and(_T_1465, _T_1469) @[package.scala 50:38] + node _T_1471 = or(_T_1461, _T_1470) @[package.scala 50:29] + node _T_1472 = and(_T_1459, _T_1466) @[package.scala 49:27] + node _T_1473 = and(_T_1465, _T_1472) @[package.scala 50:38] + node _T_1474 = or(_T_1461, _T_1473) @[package.scala 50:29] + node _T_1475 = and(_T_1462, _T_1468) @[package.scala 49:27] + node _T_1476 = and(_T_1465, _T_1475) @[package.scala 50:38] + node _T_1477 = or(_T_1464, _T_1476) @[package.scala 50:29] + node _T_1478 = and(_T_1462, _T_1466) @[package.scala 49:27] + node _T_1479 = and(_T_1465, _T_1478) @[package.scala 50:38] + node _T_1480 = or(_T_1464, _T_1479) @[package.scala 50:29] + node _T_1481 = bits(_T_1451, 0, 0) @[package.scala 44:26] + node _T_1482 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[package.scala 46:20] + node _T_1485 = and(_T_1469, _T_1484) @[package.scala 49:27] + node _T_1486 = and(_T_1481, _T_1485) @[package.scala 50:38] + node _T_1487 = or(_T_1471, _T_1486) @[package.scala 50:29] + node _T_1488 = and(_T_1469, _T_1482) @[package.scala 49:27] + node _T_1489 = and(_T_1481, _T_1488) @[package.scala 50:38] + node _T_1490 = or(_T_1471, _T_1489) @[package.scala 50:29] + node _T_1491 = and(_T_1472, _T_1484) @[package.scala 49:27] + node _T_1492 = and(_T_1481, _T_1491) @[package.scala 50:38] + node _T_1493 = or(_T_1474, _T_1492) @[package.scala 50:29] + node _T_1494 = and(_T_1472, _T_1482) @[package.scala 49:27] + node _T_1495 = and(_T_1481, _T_1494) @[package.scala 50:38] + node _T_1496 = or(_T_1474, _T_1495) @[package.scala 50:29] + node _T_1497 = and(_T_1475, _T_1484) @[package.scala 49:27] + node _T_1498 = and(_T_1481, _T_1497) @[package.scala 50:38] + node _T_1499 = or(_T_1477, _T_1498) @[package.scala 50:29] + node _T_1500 = and(_T_1475, _T_1482) @[package.scala 49:27] + node _T_1501 = and(_T_1481, _T_1500) @[package.scala 50:38] + node _T_1502 = or(_T_1477, _T_1501) @[package.scala 50:29] + node _T_1503 = and(_T_1478, _T_1484) @[package.scala 49:27] + node _T_1504 = and(_T_1481, _T_1503) @[package.scala 50:38] + node _T_1505 = or(_T_1480, _T_1504) @[package.scala 50:29] + node _T_1506 = and(_T_1478, _T_1482) @[package.scala 49:27] + node _T_1507 = and(_T_1481, _T_1506) @[package.scala 50:38] + node _T_1508 = or(_T_1480, _T_1507) @[package.scala 50:29] + node _T_1509 = cat(_T_1490, _T_1487) @[Cat.scala 30:58] + node _T_1510 = cat(_T_1496, _T_1493) @[Cat.scala 30:58] + node _T_1511 = cat(_T_1510, _T_1509) @[Cat.scala 30:58] + node _T_1512 = cat(_T_1502, _T_1499) @[Cat.scala 30:58] + node _T_1513 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1514 = cat(_T_1513, _T_1512) @[Cat.scala 30:58] + node _T_1515 = cat(_T_1514, _T_1511) @[Cat.scala 30:58] + node _T_1517 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + when _T_1517 : @[RocketPlexMaster.scala 18:17] + node _T_1519 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1521 = eq(_T_1519, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1521 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1522 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1524 = eq(_T_1522, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1524 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1526 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_1527 = or(_T_1526, reset) @[RocketPlexMaster.scala 18:17] + node _T_1529 = eq(_T_1527, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1529 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1530 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1532 = eq(_T_1530, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1532 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1534 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1535 = or(_T_1534, reset) @[RocketPlexMaster.scala 18:17] + node _T_1537 = eq(_T_1535, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1537 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1538 = not(io.in[0].b.bits.mask) @[RocketPlexMaster.scala 18:17] + node _T_1540 = eq(_T_1538, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1541 = or(_T_1540, reset) @[RocketPlexMaster.scala 18:17] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1543 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1545 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 18:17] + when _T_1545 : @[RocketPlexMaster.scala 18:17] + node _T_1547 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1549 = eq(_T_1547, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1549 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1550 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1552 = eq(_T_1550, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1552 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1553 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1555 = eq(_T_1553, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1555 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1557 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1558 = or(_T_1557, reset) @[RocketPlexMaster.scala 18:17] + node _T_1560 = eq(_T_1558, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1560 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1561 = eq(io.in[0].b.bits.mask, _T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1562 = or(_T_1561, reset) @[RocketPlexMaster.scala 18:17] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1564 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1566 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1566 : @[RocketPlexMaster.scala 18:17] + node _T_1568 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1570 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1571 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1573 = eq(_T_1571, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1573 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1574 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1576 = eq(_T_1574, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1576 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1578 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1579 = or(_T_1578, reset) @[RocketPlexMaster.scala 18:17] + node _T_1581 = eq(_T_1579, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1581 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1582 = eq(io.in[0].b.bits.mask, _T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1583 = or(_T_1582, reset) @[RocketPlexMaster.scala 18:17] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1585 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1587 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 18:17] + when _T_1587 : @[RocketPlexMaster.scala 18:17] + node _T_1589 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1591 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1592 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1594 = eq(_T_1592, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1594 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1595 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1597 = eq(_T_1595, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1597 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1599 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1600 = or(_T_1599, reset) @[RocketPlexMaster.scala 18:17] + node _T_1602 = eq(_T_1600, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1602 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1603 = not(_T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1604 = and(io.in[0].b.bits.mask, _T_1603) @[RocketPlexMaster.scala 18:17] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1607 = or(_T_1606, reset) @[RocketPlexMaster.scala 18:17] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1609 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1611 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 18:17] + when _T_1611 : @[RocketPlexMaster.scala 18:17] + node _T_1613 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1615 = eq(_T_1613, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1615 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1616 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1618 = eq(_T_1616, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1618 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1619 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1621 = eq(_T_1619, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1621 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1623 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1624 = or(_T_1623, reset) @[RocketPlexMaster.scala 18:17] + node _T_1626 = eq(_T_1624, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1626 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1627 = eq(io.in[0].b.bits.mask, _T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1628 = or(_T_1627, reset) @[RocketPlexMaster.scala 18:17] + node _T_1630 = eq(_T_1628, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1630 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1632 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + when _T_1632 : @[RocketPlexMaster.scala 18:17] + node _T_1634 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1636 = eq(_T_1634, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1636 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1637 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1639 = eq(_T_1637, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1639 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1640 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1642 = eq(_T_1640, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1642 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1644 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1645 = or(_T_1644, reset) @[RocketPlexMaster.scala 18:17] + node _T_1647 = eq(_T_1645, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1647 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1648 = eq(io.in[0].b.bits.mask, _T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1649 = or(_T_1648, reset) @[RocketPlexMaster.scala 18:17] + node _T_1651 = eq(_T_1649, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1651 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1653 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 18:17] + when _T_1653 : @[RocketPlexMaster.scala 18:17] + node _T_1655 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 18:17] + node _T_1657 = eq(_T_1655, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1657 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1658 = or(_T_1439, reset) @[RocketPlexMaster.scala 18:17] + node _T_1660 = eq(_T_1658, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1660 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1661 = or(_T_1447, reset) @[RocketPlexMaster.scala 18:17] + node _T_1663 = eq(_T_1661, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1663 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1664 = eq(io.in[0].b.bits.mask, _T_1515) @[RocketPlexMaster.scala 18:17] + node _T_1665 = or(_T_1664, reset) @[RocketPlexMaster.scala 18:17] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1667 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + when io.in[0].c.valid : @[RocketPlexMaster.scala 18:17] + node _T_1669 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1670 = or(_T_1669, reset) @[RocketPlexMaster.scala 18:17] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1672 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1674 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1675 = not(_T_1674) @[Parameters.scala 37:9] + node _T_1677 = or(_T_1675, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1678 = not(_T_1677) @[Parameters.scala 37:7] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1683 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1683 is invalid @[Parameters.scala 228:27] + _T_1683[0] <= _T_1680 @[Parameters.scala 228:27] + node _T_1688 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1689 = dshl(_T_1688, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1690 = bits(_T_1689, 7, 0) @[package.scala 19:76] + node _T_1691 = not(_T_1690) @[package.scala 19:40] + node _T_1692 = and(io.in[0].c.bits.address, _T_1691) @[Edges.scala 17:16] + node _T_1694 = eq(_T_1692, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1696 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1697 = cvt(_T_1696) @[Parameters.scala 117:49] + node _T_1699 = and(_T_1697, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1700 = asSInt(_T_1699) @[Parameters.scala 117:52] + node _T_1702 = eq(_T_1700, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1704 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1705 = cvt(_T_1704) @[Parameters.scala 117:49] + node _T_1707 = and(_T_1705, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1708 = asSInt(_T_1707) @[Parameters.scala 117:52] + node _T_1710 = eq(_T_1708, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1712 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1713 = cvt(_T_1712) @[Parameters.scala 117:49] + node _T_1715 = and(_T_1713, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1716 = asSInt(_T_1715) @[Parameters.scala 117:52] + node _T_1718 = eq(_T_1716, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1720 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1721 = cvt(_T_1720) @[Parameters.scala 117:49] + node _T_1723 = and(_T_1721, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1724 = asSInt(_T_1723) @[Parameters.scala 117:52] + node _T_1726 = eq(_T_1724, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1728 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1729 = cvt(_T_1728) @[Parameters.scala 117:49] + node _T_1731 = and(_T_1729, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1732 = asSInt(_T_1731) @[Parameters.scala 117:52] + node _T_1734 = eq(_T_1732, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1736 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1737 = cvt(_T_1736) @[Parameters.scala 117:49] + node _T_1739 = and(_T_1737, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1740 = asSInt(_T_1739) @[Parameters.scala 117:52] + node _T_1742 = eq(_T_1740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1744 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1745 = cvt(_T_1744) @[Parameters.scala 117:49] + node _T_1747 = and(_T_1745, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1748 = asSInt(_T_1747) @[Parameters.scala 117:52] + node _T_1750 = eq(_T_1748, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1753 : UInt<1>[7] @[Parameters.scala 110:36] + _T_1753 is invalid @[Parameters.scala 110:36] + _T_1753[0] <= _T_1702 @[Parameters.scala 110:36] + _T_1753[1] <= _T_1710 @[Parameters.scala 110:36] + _T_1753[2] <= _T_1718 @[Parameters.scala 110:36] + _T_1753[3] <= _T_1726 @[Parameters.scala 110:36] + _T_1753[4] <= _T_1734 @[Parameters.scala 110:36] + _T_1753[5] <= _T_1742 @[Parameters.scala 110:36] + _T_1753[6] <= _T_1750 @[Parameters.scala 110:36] + node _T_1763 = or(_T_1753[0], _T_1753[1]) @[Parameters.scala 119:64] + node _T_1764 = or(_T_1763, _T_1753[2]) @[Parameters.scala 119:64] + node _T_1765 = or(_T_1764, _T_1753[3]) @[Parameters.scala 119:64] + node _T_1766 = or(_T_1765, _T_1753[4]) @[Parameters.scala 119:64] + node _T_1767 = or(_T_1766, _T_1753[5]) @[Parameters.scala 119:64] + node _T_1768 = or(_T_1767, _T_1753[6]) @[Parameters.scala 119:64] + node _T_1770 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 18:17] + when _T_1770 : @[RocketPlexMaster.scala 18:17] + node _T_1771 = or(_T_1768, reset) @[RocketPlexMaster.scala 18:17] + node _T_1773 = eq(_T_1771, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1773 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1774 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1776 = eq(_T_1774, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1776 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1778 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_1779 = or(_T_1778, reset) @[RocketPlexMaster.scala 18:17] + node _T_1781 = eq(_T_1779, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1781 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1782 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_1784 = eq(_T_1782, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1784 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1786 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1787 = or(_T_1786, reset) @[RocketPlexMaster.scala 18:17] + node _T_1789 = eq(_T_1787, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1789 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1791 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1792 = or(_T_1791, reset) @[RocketPlexMaster.scala 18:17] + node _T_1794 = eq(_T_1792, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1794 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1796 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 18:17] + when _T_1796 : @[RocketPlexMaster.scala 18:17] + node _T_1797 = or(_T_1768, reset) @[RocketPlexMaster.scala 18:17] + node _T_1799 = eq(_T_1797, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1799 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1800 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1802 = eq(_T_1800, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1802 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1804 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_1805 = or(_T_1804, reset) @[RocketPlexMaster.scala 18:17] + node _T_1807 = eq(_T_1805, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1807 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1808 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_1810 = eq(_T_1808, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1810 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1812 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1813 = or(_T_1812, reset) @[RocketPlexMaster.scala 18:17] + node _T_1815 = eq(_T_1813, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1815 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1817 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1818 = or(_T_1817, reset) @[RocketPlexMaster.scala 18:17] + node _T_1820 = eq(_T_1818, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1820 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1822 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + when _T_1822 : @[RocketPlexMaster.scala 18:17] + node _T_1825 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1827 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1828 = and(_T_1825, _T_1827) @[Parameters.scala 63:37] + node _T_1829 = or(UInt<1>("h00"), _T_1828) @[Parameters.scala 132:31] + node _T_1831 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1832 = cvt(_T_1831) @[Parameters.scala 117:49] + node _T_1834 = and(_T_1832, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1835 = asSInt(_T_1834) @[Parameters.scala 117:52] + node _T_1837 = eq(_T_1835, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1839 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1840 = cvt(_T_1839) @[Parameters.scala 117:49] + node _T_1842 = and(_T_1840, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1843 = asSInt(_T_1842) @[Parameters.scala 117:52] + node _T_1845 = eq(_T_1843, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1846 = or(_T_1837, _T_1845) @[Parameters.scala 133:42] + node _T_1847 = and(_T_1829, _T_1846) @[Parameters.scala 132:56] + node _T_1850 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1852 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1853 = cvt(_T_1852) @[Parameters.scala 117:49] + node _T_1855 = and(_T_1853, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1856 = asSInt(_T_1855) @[Parameters.scala 117:52] + node _T_1858 = eq(_T_1856, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1860 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1861 = cvt(_T_1860) @[Parameters.scala 117:49] + node _T_1863 = and(_T_1861, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1864 = asSInt(_T_1863) @[Parameters.scala 117:52] + node _T_1866 = eq(_T_1864, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1868 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1869 = cvt(_T_1868) @[Parameters.scala 117:49] + node _T_1871 = and(_T_1869, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1872 = asSInt(_T_1871) @[Parameters.scala 117:52] + node _T_1874 = eq(_T_1872, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1876 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1877 = cvt(_T_1876) @[Parameters.scala 117:49] + node _T_1879 = and(_T_1877, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1880 = asSInt(_T_1879) @[Parameters.scala 117:52] + node _T_1882 = eq(_T_1880, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1883 = or(_T_1858, _T_1866) @[Parameters.scala 133:42] + node _T_1884 = or(_T_1883, _T_1874) @[Parameters.scala 133:42] + node _T_1885 = or(_T_1884, _T_1882) @[Parameters.scala 133:42] + node _T_1886 = and(_T_1850, _T_1885) @[Parameters.scala 132:56] + node _T_1888 = or(UInt<1>("h00"), _T_1847) @[Parameters.scala 134:30] + node _T_1889 = or(_T_1888, _T_1886) @[Parameters.scala 134:30] + node _T_1890 = or(_T_1889, reset) @[RocketPlexMaster.scala 18:17] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1892 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1893 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1895 = eq(_T_1893, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1895 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1897 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_1898 = or(_T_1897, reset) @[RocketPlexMaster.scala 18:17] + node _T_1900 = eq(_T_1898, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1900 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1901 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_1903 = eq(_T_1901, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1903 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1905 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1906 = or(_T_1905, reset) @[RocketPlexMaster.scala 18:17] + node _T_1908 = eq(_T_1906, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1908 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1910 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_1911 = or(_T_1910, reset) @[RocketPlexMaster.scala 18:17] + node _T_1913 = eq(_T_1911, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1913 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1915 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RocketPlexMaster.scala 18:17] + when _T_1915 : @[RocketPlexMaster.scala 18:17] + node _T_1918 = leq(UInt<1>("h00"), io.in[0].c.bits.size) @[Parameters.scala 63:32] + node _T_1920 = leq(io.in[0].c.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1921 = and(_T_1918, _T_1920) @[Parameters.scala 63:37] + node _T_1922 = or(UInt<1>("h00"), _T_1921) @[Parameters.scala 132:31] + node _T_1924 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1925 = cvt(_T_1924) @[Parameters.scala 117:49] + node _T_1927 = and(_T_1925, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1928 = asSInt(_T_1927) @[Parameters.scala 117:52] + node _T_1930 = eq(_T_1928, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1932 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1933 = cvt(_T_1932) @[Parameters.scala 117:49] + node _T_1935 = and(_T_1933, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1936 = asSInt(_T_1935) @[Parameters.scala 117:52] + node _T_1938 = eq(_T_1936, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1939 = or(_T_1930, _T_1938) @[Parameters.scala 133:42] + node _T_1940 = and(_T_1922, _T_1939) @[Parameters.scala 132:56] + node _T_1943 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1945 = xor(io.in[0].c.bits.address, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_1946 = cvt(_T_1945) @[Parameters.scala 117:49] + node _T_1948 = and(_T_1946, asSInt(UInt<14>("h02000"))) @[Parameters.scala 117:52] + node _T_1949 = asSInt(_T_1948) @[Parameters.scala 117:52] + node _T_1951 = eq(_T_1949, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1953 = xor(io.in[0].c.bits.address, UInt<26>("h02000000")) @[Parameters.scala 117:31] + node _T_1954 = cvt(_T_1953) @[Parameters.scala 117:49] + node _T_1956 = and(_T_1954, asSInt(UInt<17>("h010000"))) @[Parameters.scala 117:52] + node _T_1957 = asSInt(_T_1956) @[Parameters.scala 117:52] + node _T_1959 = eq(_T_1957, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1961 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1962 = cvt(_T_1961) @[Parameters.scala 117:49] + node _T_1964 = and(_T_1962, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1965 = asSInt(_T_1964) @[Parameters.scala 117:52] + node _T_1967 = eq(_T_1965, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1969 = xor(io.in[0].c.bits.address, UInt<28>("h0c000000")) @[Parameters.scala 117:31] + node _T_1970 = cvt(_T_1969) @[Parameters.scala 117:49] + node _T_1972 = and(_T_1970, asSInt(UInt<27>("h04000000"))) @[Parameters.scala 117:52] + node _T_1973 = asSInt(_T_1972) @[Parameters.scala 117:52] + node _T_1975 = eq(_T_1973, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1976 = or(_T_1951, _T_1959) @[Parameters.scala 133:42] + node _T_1977 = or(_T_1976, _T_1967) @[Parameters.scala 133:42] + node _T_1978 = or(_T_1977, _T_1975) @[Parameters.scala 133:42] + node _T_1979 = and(_T_1943, _T_1978) @[Parameters.scala 132:56] + node _T_1981 = or(UInt<1>("h00"), _T_1940) @[Parameters.scala 134:30] + node _T_1982 = or(_T_1981, _T_1979) @[Parameters.scala 134:30] + node _T_1983 = or(_T_1982, reset) @[RocketPlexMaster.scala 18:17] + node _T_1985 = eq(_T_1983, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1985 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1986 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_1988 = eq(_T_1986, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1988 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1990 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_1991 = or(_T_1990, reset) @[RocketPlexMaster.scala 18:17] + node _T_1993 = eq(_T_1991, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1993 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1994 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_1996 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_1998 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1999 = or(_T_1998, reset) @[RocketPlexMaster.scala 18:17] + node _T_2001 = eq(_T_1999, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2001 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2003 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2004 = or(_T_2003, reset) @[RocketPlexMaster.scala 18:17] + node _T_2006 = eq(_T_2004, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2006 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2008 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2008 : @[RocketPlexMaster.scala 18:17] + node _T_2009 = or(_T_1768, reset) @[RocketPlexMaster.scala 18:17] + node _T_2011 = eq(_T_2009, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2011 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2012 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2014 = eq(_T_2012, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2014 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2015 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_2017 = eq(_T_2015, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2017 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2019 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2020 = or(_T_2019, reset) @[RocketPlexMaster.scala 18:17] + node _T_2022 = eq(_T_2020, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2022 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2024 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 18:17] + when _T_2024 : @[RocketPlexMaster.scala 18:17] + node _T_2025 = or(_T_1768, reset) @[RocketPlexMaster.scala 18:17] + node _T_2027 = eq(_T_2025, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2027 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2028 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2030 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2031 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_2033 = eq(_T_2031, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2033 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2035 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2036 = or(_T_2035, reset) @[RocketPlexMaster.scala 18:17] + node _T_2038 = eq(_T_2036, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2038 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2040 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 18:17] + when _T_2040 : @[RocketPlexMaster.scala 18:17] + node _T_2041 = or(_T_1768, reset) @[RocketPlexMaster.scala 18:17] + node _T_2043 = eq(_T_2041, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2043 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2044 = or(_T_1683[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2046 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2047 = or(_T_1694, reset) @[RocketPlexMaster.scala 18:17] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2049 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2051 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2052 = or(_T_2051, reset) @[RocketPlexMaster.scala 18:17] + node _T_2054 = eq(_T_2052, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2054 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2056 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2057 = or(_T_2056, reset) @[RocketPlexMaster.scala 18:17] + node _T_2059 = eq(_T_2057, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2059 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + when io.in[0].d.valid : @[RocketPlexMaster.scala 18:17] + node _T_2061 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_2062 = or(_T_2061, reset) @[RocketPlexMaster.scala 18:17] + node _T_2064 = eq(_T_2062, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2064 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2066 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_2067 = not(_T_2066) @[Parameters.scala 37:9] + node _T_2069 = or(_T_2067, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_2070 = not(_T_2069) @[Parameters.scala 37:7] + node _T_2072 = eq(_T_2070, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_2075 : UInt<1>[1] @[Parameters.scala 228:27] + _T_2075 is invalid @[Parameters.scala 228:27] + _T_2075[0] <= _T_2072 @[Parameters.scala 228:27] + node _T_2080 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2081 = dshl(_T_2080, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2082 = bits(_T_2081, 7, 0) @[package.scala 19:76] + node _T_2083 = not(_T_2082) @[package.scala 19:40] + node _T_2084 = and(io.in[0].d.bits.addr_lo, _T_2083) @[Edges.scala 17:16] + node _T_2086 = eq(_T_2084, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_2088 = lt(io.in[0].d.bits.sink, UInt<4>("h0a")) @[RocketPlexMaster.scala 18:17] + node _T_2090 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + when _T_2090 : @[RocketPlexMaster.scala 18:17] + node _T_2091 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2093 = eq(_T_2091, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2093 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2094 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2096 = eq(_T_2094, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2096 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2097 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2099 = eq(_T_2097, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2099 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2101 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_2102 = or(_T_2101, reset) @[RocketPlexMaster.scala 18:17] + node _T_2104 = eq(_T_2102, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2104 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2106 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2107 = or(_T_2106, reset) @[RocketPlexMaster.scala 18:17] + node _T_2109 = eq(_T_2107, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2109 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2111 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2112 = or(_T_2111, reset) @[RocketPlexMaster.scala 18:17] + node _T_2114 = eq(_T_2112, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2114 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2116 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 18:17] + when _T_2116 : @[RocketPlexMaster.scala 18:17] + node _T_2117 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2119 = eq(_T_2117, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2119 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2120 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2122 = eq(_T_2120, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2122 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2123 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2125 = eq(_T_2123, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2125 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2127 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_2128 = or(_T_2127, reset) @[RocketPlexMaster.scala 18:17] + node _T_2130 = eq(_T_2128, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2130 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2132 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2133 = or(_T_2132, reset) @[RocketPlexMaster.scala 18:17] + node _T_2135 = eq(_T_2133, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2135 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2137 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 18:17] + when _T_2137 : @[RocketPlexMaster.scala 18:17] + node _T_2138 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2140 = eq(_T_2138, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2140 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2141 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2143 = eq(_T_2141, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2143 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2144 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2146 = eq(_T_2144, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2146 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2148 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 18:17] + node _T_2149 = or(_T_2148, reset) @[RocketPlexMaster.scala 18:17] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2151 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2153 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_2154 = or(_T_2153, reset) @[RocketPlexMaster.scala 18:17] + node _T_2156 = eq(_T_2154, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2156 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2158 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2158 : @[RocketPlexMaster.scala 18:17] + node _T_2159 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2161 = eq(_T_2159, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2161 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2162 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2164 = eq(_T_2162, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2164 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2165 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2167 = eq(_T_2165, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2167 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2169 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2170 = or(_T_2169, reset) @[RocketPlexMaster.scala 18:17] + node _T_2172 = eq(_T_2170, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2172 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2174 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 18:17] + when _T_2174 : @[RocketPlexMaster.scala 18:17] + node _T_2175 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2177 = eq(_T_2175, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2177 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2178 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2180 = eq(_T_2178, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2180 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2181 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2183 = eq(_T_2181, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2183 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2185 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2186 = or(_T_2185, reset) @[RocketPlexMaster.scala 18:17] + node _T_2188 = eq(_T_2186, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2188 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2190 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 18:17] + when _T_2190 : @[RocketPlexMaster.scala 18:17] + node _T_2191 = or(_T_2075[0], reset) @[RocketPlexMaster.scala 18:17] + node _T_2193 = eq(_T_2191, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2193 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2194 = or(_T_2086, reset) @[RocketPlexMaster.scala 18:17] + node _T_2196 = eq(_T_2194, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2196 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2197 = or(_T_2088, reset) @[RocketPlexMaster.scala 18:17] + node _T_2199 = eq(_T_2197, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2199 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2201 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2202 = or(_T_2201, reset) @[RocketPlexMaster.scala 18:17] + node _T_2204 = eq(_T_2202, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2204 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2206 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2207 = or(_T_2206, reset) @[RocketPlexMaster.scala 18:17] + node _T_2209 = eq(_T_2207, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2209 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + when io.in[0].e.valid : @[RocketPlexMaster.scala 18:17] + node _T_2211 = lt(io.in[0].e.bits.sink, UInt<4>("h0a")) @[RocketPlexMaster.scala 18:17] + node _T_2212 = or(_T_2211, reset) @[RocketPlexMaster.scala 18:17] + node _T_2214 = eq(_T_2212, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2214 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2215 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2217 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2218 = dshl(_T_2217, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2219 = bits(_T_2218, 7, 0) @[package.scala 19:76] + node _T_2220 = not(_T_2219) @[package.scala 19:40] + node _T_2221 = shr(_T_2220, 3) @[Edges.scala 198:59] + node _T_2222 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2224 = eq(_T_2222, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2226 = mux(_T_2224, _T_2221, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2228 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2230 = sub(_T_2228, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2231 = asUInt(_T_2230) @[Edges.scala 208:28] + node _T_2232 = tail(_T_2231, 1) @[Edges.scala 208:28] + node _T_2234 = eq(_T_2228, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2236 = eq(_T_2228, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2238 = eq(_T_2226, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2239 = or(_T_2236, _T_2238) @[Edges.scala 210:37] + node _T_2240 = and(_T_2239, _T_2215) @[Edges.scala 211:22] + node _T_2241 = not(_T_2232) @[Edges.scala 212:27] + node _T_2242 = and(_T_2226, _T_2241) @[Edges.scala 212:25] + when _T_2215 : @[Edges.scala 213:17] + node _T_2243 = mux(_T_2234, _T_2226, _T_2232) @[Edges.scala 214:21] + _T_2228 <= _T_2243 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2245 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2247 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2249 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2251 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2253 : UInt, clock @[RocketPlexMaster.scala 18:17] + node _T_2255 = eq(_T_2234, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2256 = and(io.in[0].a.valid, _T_2255) @[RocketPlexMaster.scala 18:17] + when _T_2256 : @[RocketPlexMaster.scala 18:17] + node _T_2257 = eq(io.in[0].a.bits.opcode, _T_2245) @[RocketPlexMaster.scala 18:17] + node _T_2258 = or(_T_2257, reset) @[RocketPlexMaster.scala 18:17] + node _T_2260 = eq(_T_2258, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2260 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2261 = eq(io.in[0].a.bits.param, _T_2247) @[RocketPlexMaster.scala 18:17] + node _T_2262 = or(_T_2261, reset) @[RocketPlexMaster.scala 18:17] + node _T_2264 = eq(_T_2262, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2264 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2265 = eq(io.in[0].a.bits.size, _T_2249) @[RocketPlexMaster.scala 18:17] + node _T_2266 = or(_T_2265, reset) @[RocketPlexMaster.scala 18:17] + node _T_2268 = eq(_T_2266, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2268 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2269 = eq(io.in[0].a.bits.source, _T_2251) @[RocketPlexMaster.scala 18:17] + node _T_2270 = or(_T_2269, reset) @[RocketPlexMaster.scala 18:17] + node _T_2272 = eq(_T_2270, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2272 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2273 = eq(io.in[0].a.bits.address, _T_2253) @[RocketPlexMaster.scala 18:17] + node _T_2274 = or(_T_2273, reset) @[RocketPlexMaster.scala 18:17] + node _T_2276 = eq(_T_2274, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2276 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2277 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2278 = and(_T_2277, _T_2234) @[RocketPlexMaster.scala 18:17] + when _T_2278 : @[RocketPlexMaster.scala 18:17] + _T_2245 <= io.in[0].a.bits.opcode @[RocketPlexMaster.scala 18:17] + _T_2247 <= io.in[0].a.bits.param @[RocketPlexMaster.scala 18:17] + _T_2249 <= io.in[0].a.bits.size @[RocketPlexMaster.scala 18:17] + _T_2251 <= io.in[0].a.bits.source @[RocketPlexMaster.scala 18:17] + _T_2253 <= io.in[0].a.bits.address @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2279 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2281 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2282 = dshl(_T_2281, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_2283 = bits(_T_2282, 7, 0) @[package.scala 19:76] + node _T_2284 = not(_T_2283) @[package.scala 19:40] + node _T_2285 = shr(_T_2284, 3) @[Edges.scala 198:59] + node _T_2286 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_2288 = eq(_T_2286, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_2291 = mux(UInt<1>("h00"), _T_2285, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2293 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2295 = sub(_T_2293, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2296 = asUInt(_T_2295) @[Edges.scala 208:28] + node _T_2297 = tail(_T_2296, 1) @[Edges.scala 208:28] + node _T_2299 = eq(_T_2293, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2301 = eq(_T_2293, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2303 = eq(_T_2291, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2304 = or(_T_2301, _T_2303) @[Edges.scala 210:37] + node _T_2305 = and(_T_2304, _T_2279) @[Edges.scala 211:22] + node _T_2306 = not(_T_2297) @[Edges.scala 212:27] + node _T_2307 = and(_T_2291, _T_2306) @[Edges.scala 212:25] + when _T_2279 : @[Edges.scala 213:17] + node _T_2308 = mux(_T_2299, _T_2291, _T_2297) @[Edges.scala 214:21] + _T_2293 <= _T_2308 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2310 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2312 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2314 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2316 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2318 : UInt, clock @[RocketPlexMaster.scala 18:17] + node _T_2320 = eq(_T_2299, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2321 = and(io.in[0].b.valid, _T_2320) @[RocketPlexMaster.scala 18:17] + when _T_2321 : @[RocketPlexMaster.scala 18:17] + node _T_2322 = eq(io.in[0].b.bits.opcode, _T_2310) @[RocketPlexMaster.scala 18:17] + node _T_2323 = or(_T_2322, reset) @[RocketPlexMaster.scala 18:17] + node _T_2325 = eq(_T_2323, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2325 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2326 = eq(io.in[0].b.bits.param, _T_2312) @[RocketPlexMaster.scala 18:17] + node _T_2327 = or(_T_2326, reset) @[RocketPlexMaster.scala 18:17] + node _T_2329 = eq(_T_2327, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2329 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2330 = eq(io.in[0].b.bits.size, _T_2314) @[RocketPlexMaster.scala 18:17] + node _T_2331 = or(_T_2330, reset) @[RocketPlexMaster.scala 18:17] + node _T_2333 = eq(_T_2331, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2333 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2334 = eq(io.in[0].b.bits.source, _T_2316) @[RocketPlexMaster.scala 18:17] + node _T_2335 = or(_T_2334, reset) @[RocketPlexMaster.scala 18:17] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2337 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2338 = eq(io.in[0].b.bits.address, _T_2318) @[RocketPlexMaster.scala 18:17] + node _T_2339 = or(_T_2338, reset) @[RocketPlexMaster.scala 18:17] + node _T_2341 = eq(_T_2339, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2341 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2342 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_2343 = and(_T_2342, _T_2299) @[RocketPlexMaster.scala 18:17] + when _T_2343 : @[RocketPlexMaster.scala 18:17] + _T_2310 <= io.in[0].b.bits.opcode @[RocketPlexMaster.scala 18:17] + _T_2312 <= io.in[0].b.bits.param @[RocketPlexMaster.scala 18:17] + _T_2314 <= io.in[0].b.bits.size @[RocketPlexMaster.scala 18:17] + _T_2316 <= io.in[0].b.bits.source @[RocketPlexMaster.scala 18:17] + _T_2318 <= io.in[0].b.bits.address @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2344 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2346 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2347 = dshl(_T_2346, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_2348 = bits(_T_2347, 7, 0) @[package.scala 19:76] + node _T_2349 = not(_T_2348) @[package.scala 19:40] + node _T_2350 = shr(_T_2349, 3) @[Edges.scala 198:59] + node _T_2351 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_2354 = mux(UInt<1>("h00"), _T_2350, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2356 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2358 = sub(_T_2356, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2359 = asUInt(_T_2358) @[Edges.scala 208:28] + node _T_2360 = tail(_T_2359, 1) @[Edges.scala 208:28] + node _T_2362 = eq(_T_2356, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2364 = eq(_T_2356, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2366 = eq(_T_2354, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2367 = or(_T_2364, _T_2366) @[Edges.scala 210:37] + node _T_2368 = and(_T_2367, _T_2344) @[Edges.scala 211:22] + node _T_2369 = not(_T_2360) @[Edges.scala 212:27] + node _T_2370 = and(_T_2354, _T_2369) @[Edges.scala 212:25] + when _T_2344 : @[Edges.scala 213:17] + node _T_2371 = mux(_T_2362, _T_2354, _T_2360) @[Edges.scala 214:21] + _T_2356 <= _T_2371 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2373 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2375 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2377 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2379 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2381 : UInt, clock @[RocketPlexMaster.scala 18:17] + node _T_2383 = eq(_T_2362, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2384 = and(io.in[0].c.valid, _T_2383) @[RocketPlexMaster.scala 18:17] + when _T_2384 : @[RocketPlexMaster.scala 18:17] + node _T_2385 = eq(io.in[0].c.bits.opcode, _T_2373) @[RocketPlexMaster.scala 18:17] + node _T_2386 = or(_T_2385, reset) @[RocketPlexMaster.scala 18:17] + node _T_2388 = eq(_T_2386, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2388 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2389 = eq(io.in[0].c.bits.param, _T_2375) @[RocketPlexMaster.scala 18:17] + node _T_2390 = or(_T_2389, reset) @[RocketPlexMaster.scala 18:17] + node _T_2392 = eq(_T_2390, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2392 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2393 = eq(io.in[0].c.bits.size, _T_2377) @[RocketPlexMaster.scala 18:17] + node _T_2394 = or(_T_2393, reset) @[RocketPlexMaster.scala 18:17] + node _T_2396 = eq(_T_2394, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2396 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2397 = eq(io.in[0].c.bits.source, _T_2379) @[RocketPlexMaster.scala 18:17] + node _T_2398 = or(_T_2397, reset) @[RocketPlexMaster.scala 18:17] + node _T_2400 = eq(_T_2398, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2400 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2401 = eq(io.in[0].c.bits.address, _T_2381) @[RocketPlexMaster.scala 18:17] + node _T_2402 = or(_T_2401, reset) @[RocketPlexMaster.scala 18:17] + node _T_2404 = eq(_T_2402, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2404 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2405 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_2406 = and(_T_2405, _T_2362) @[RocketPlexMaster.scala 18:17] + when _T_2406 : @[RocketPlexMaster.scala 18:17] + _T_2373 <= io.in[0].c.bits.opcode @[RocketPlexMaster.scala 18:17] + _T_2375 <= io.in[0].c.bits.param @[RocketPlexMaster.scala 18:17] + _T_2377 <= io.in[0].c.bits.size @[RocketPlexMaster.scala 18:17] + _T_2379 <= io.in[0].c.bits.source @[RocketPlexMaster.scala 18:17] + _T_2381 <= io.in[0].c.bits.address @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2407 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2409 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2410 = dshl(_T_2409, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2411 = bits(_T_2410, 7, 0) @[package.scala 19:76] + node _T_2412 = not(_T_2411) @[package.scala 19:40] + node _T_2413 = shr(_T_2412, 3) @[Edges.scala 198:59] + node _T_2414 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2416 = mux(_T_2414, _T_2413, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2418 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2420 = sub(_T_2418, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2421 = asUInt(_T_2420) @[Edges.scala 208:28] + node _T_2422 = tail(_T_2421, 1) @[Edges.scala 208:28] + node _T_2424 = eq(_T_2418, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2426 = eq(_T_2418, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2428 = eq(_T_2416, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2429 = or(_T_2426, _T_2428) @[Edges.scala 210:37] + node _T_2430 = and(_T_2429, _T_2407) @[Edges.scala 211:22] + node _T_2431 = not(_T_2422) @[Edges.scala 212:27] + node _T_2432 = and(_T_2416, _T_2431) @[Edges.scala 212:25] + when _T_2407 : @[Edges.scala 213:17] + node _T_2433 = mux(_T_2424, _T_2416, _T_2422) @[Edges.scala 214:21] + _T_2418 <= _T_2433 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_2435 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2437 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2439 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2441 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2443 : UInt, clock @[RocketPlexMaster.scala 18:17] + reg _T_2445 : UInt, clock @[RocketPlexMaster.scala 18:17] + node _T_2447 = eq(_T_2424, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2448 = and(io.in[0].d.valid, _T_2447) @[RocketPlexMaster.scala 18:17] + when _T_2448 : @[RocketPlexMaster.scala 18:17] + node _T_2449 = eq(io.in[0].d.bits.opcode, _T_2435) @[RocketPlexMaster.scala 18:17] + node _T_2450 = or(_T_2449, reset) @[RocketPlexMaster.scala 18:17] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2452 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2453 = eq(io.in[0].d.bits.param, _T_2437) @[RocketPlexMaster.scala 18:17] + node _T_2454 = or(_T_2453, reset) @[RocketPlexMaster.scala 18:17] + node _T_2456 = eq(_T_2454, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2456 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2457 = eq(io.in[0].d.bits.size, _T_2439) @[RocketPlexMaster.scala 18:17] + node _T_2458 = or(_T_2457, reset) @[RocketPlexMaster.scala 18:17] + node _T_2460 = eq(_T_2458, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2460 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2461 = eq(io.in[0].d.bits.source, _T_2441) @[RocketPlexMaster.scala 18:17] + node _T_2462 = or(_T_2461, reset) @[RocketPlexMaster.scala 18:17] + node _T_2464 = eq(_T_2462, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2464 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2465 = eq(io.in[0].d.bits.sink, _T_2443) @[RocketPlexMaster.scala 18:17] + node _T_2466 = or(_T_2465, reset) @[RocketPlexMaster.scala 18:17] + node _T_2468 = eq(_T_2466, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2468 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2469 = eq(io.in[0].d.bits.addr_lo, _T_2445) @[RocketPlexMaster.scala 18:17] + node _T_2470 = or(_T_2469, reset) @[RocketPlexMaster.scala 18:17] + node _T_2472 = eq(_T_2470, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2472 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2473 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2474 = and(_T_2473, _T_2424) @[RocketPlexMaster.scala 18:17] + when _T_2474 : @[RocketPlexMaster.scala 18:17] + _T_2435 <= io.in[0].d.bits.opcode @[RocketPlexMaster.scala 18:17] + _T_2437 <= io.in[0].d.bits.param @[RocketPlexMaster.scala 18:17] + _T_2439 <= io.in[0].d.bits.size @[RocketPlexMaster.scala 18:17] + _T_2441 <= io.in[0].d.bits.source @[RocketPlexMaster.scala 18:17] + _T_2443 <= io.in[0].d.bits.sink @[RocketPlexMaster.scala 18:17] + _T_2445 <= io.in[0].d.bits.addr_lo @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + reg _T_2476 : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[Reg.scala 26:44] + node _T_2477 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2479 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2480 = dshl(_T_2479, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2481 = bits(_T_2480, 7, 0) @[package.scala 19:76] + node _T_2482 = not(_T_2481) @[package.scala 19:40] + node _T_2483 = shr(_T_2482, 3) @[Edges.scala 198:59] + node _T_2484 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2486 = eq(_T_2484, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2488 = mux(_T_2486, _T_2483, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2490 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2492 = sub(_T_2490, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2493 = asUInt(_T_2492) @[Edges.scala 208:28] + node _T_2494 = tail(_T_2493, 1) @[Edges.scala 208:28] + node _T_2496 = eq(_T_2490, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2498 = eq(_T_2490, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2500 = eq(_T_2488, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2501 = or(_T_2498, _T_2500) @[Edges.scala 210:37] + node _T_2502 = and(_T_2501, _T_2477) @[Edges.scala 211:22] + node _T_2503 = not(_T_2494) @[Edges.scala 212:27] + node _T_2504 = and(_T_2488, _T_2503) @[Edges.scala 212:25] + when _T_2477 : @[Edges.scala 213:17] + node _T_2505 = mux(_T_2496, _T_2488, _T_2494) @[Edges.scala 214:21] + _T_2490 <= _T_2505 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2506 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2508 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2509 = dshl(_T_2508, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2510 = bits(_T_2509, 7, 0) @[package.scala 19:76] + node _T_2511 = not(_T_2510) @[package.scala 19:40] + node _T_2512 = shr(_T_2511, 3) @[Edges.scala 198:59] + node _T_2513 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2515 = mux(_T_2513, _T_2512, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2517 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2519 = sub(_T_2517, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2520 = asUInt(_T_2519) @[Edges.scala 208:28] + node _T_2521 = tail(_T_2520, 1) @[Edges.scala 208:28] + node _T_2523 = eq(_T_2517, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2525 = eq(_T_2517, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2527 = eq(_T_2515, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2528 = or(_T_2525, _T_2527) @[Edges.scala 210:37] + node _T_2529 = and(_T_2528, _T_2506) @[Edges.scala 211:22] + node _T_2530 = not(_T_2521) @[Edges.scala 212:27] + node _T_2531 = and(_T_2515, _T_2530) @[Edges.scala 212:25] + when _T_2506 : @[Edges.scala 213:17] + node _T_2532 = mux(_T_2523, _T_2515, _T_2521) @[Edges.scala 214:21] + _T_2517 <= _T_2532 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2534 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + node _T_2535 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[RocketPlexMaster.scala 18:17] + node _T_2536 = or(_T_2534, _T_2535) @[RocketPlexMaster.scala 18:17] + node _T_2538 = eq(io.in[0].a.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2539 = or(_T_2536, _T_2538) @[RocketPlexMaster.scala 18:17] + node _T_2541 = eq(io.in[0].d.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2542 = or(_T_2539, _T_2541) @[RocketPlexMaster.scala 18:17] + node _T_2543 = or(_T_2542, reset) @[RocketPlexMaster.scala 18:17] + node _T_2545 = eq(_T_2543, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2545 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + wire _T_2547 : UInt<4> + _T_2547 is invalid + _T_2547 <= UInt<4>("h00") + node _T_2548 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2548 : @[RocketPlexMaster.scala 18:17] + when _T_2501 : @[RocketPlexMaster.scala 18:17] + node _T_2550 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2547 <= _T_2550 @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2551 = dshr(_T_2476, io.in[0].a.bits.source) @[RocketPlexMaster.scala 18:17] + node _T_2552 = bits(_T_2551, 0, 0) @[RocketPlexMaster.scala 18:17] + node _T_2554 = eq(_T_2552, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + node _T_2555 = or(_T_2554, reset) @[RocketPlexMaster.scala 18:17] + node _T_2557 = eq(_T_2555, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2557 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + wire _T_2559 : UInt<4> + _T_2559 is invalid + _T_2559 <= UInt<4>("h00") + node _T_2560 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2562 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 18:17] + node _T_2563 = and(_T_2560, _T_2562) @[RocketPlexMaster.scala 18:17] + when _T_2563 : @[RocketPlexMaster.scala 18:17] + when _T_2528 : @[RocketPlexMaster.scala 18:17] + node _T_2565 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2559 <= _T_2565 @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2566 = or(_T_2547, _T_2476) @[RocketPlexMaster.scala 18:17] + node _T_2567 = dshr(_T_2566, io.in[0].d.bits.source) @[RocketPlexMaster.scala 18:17] + node _T_2568 = bits(_T_2567, 0, 0) @[RocketPlexMaster.scala 18:17] + node _T_2569 = or(_T_2568, reset) @[RocketPlexMaster.scala 18:17] + node _T_2571 = eq(_T_2569, UInt<1>("h00")) @[RocketPlexMaster.scala 18:17] + when _T_2571 : @[RocketPlexMaster.scala 18:17] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketPlexMaster.scala:18:17)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketPlexMaster.scala 18:17] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + skip @[RocketPlexMaster.scala 18:17] + node _T_2572 = or(_T_2476, _T_2547) @[RocketPlexMaster.scala 18:17] + node _T_2573 = not(_T_2559) @[RocketPlexMaster.scala 18:17] + node _T_2574 = and(_T_2572, _T_2573) @[RocketPlexMaster.scala 18:17] + _T_2476 <= _T_2574 @[RocketPlexMaster.scala 18:17] + + module TLMonitor_38 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} + + io is invalid + io is invalid + when io.in[0].a.valid : @[RocketPlexMaster.scala 19:15] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RocketPlexMaster.scala 19:15] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_608 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_618 = eq(UInt<3>("h05"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + node _T_620 = eq(UInt<3>("h04"), io.in[0].a.bits.source) @[Parameters.scala 35:39] + wire _T_623 : UInt<1>[3] @[Parameters.scala 228:27] + _T_623 is invalid @[Parameters.scala 228:27] + _T_623[0] <= _T_616 @[Parameters.scala 228:27] + _T_623[1] <= _T_618 @[Parameters.scala 228:27] + _T_623[2] <= _T_620 @[Parameters.scala 228:27] + node _T_629 = or(_T_623[0], _T_623[1]) @[Parameters.scala 229:46] + node _T_630 = or(_T_629, _T_623[2]) @[Parameters.scala 229:46] + node _T_632 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_633 = dshl(_T_632, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_634 = bits(_T_633, 7, 0) @[package.scala 19:76] + node _T_635 = not(_T_634) @[package.scala 19:40] + node _T_636 = and(io.in[0].a.bits.address, _T_635) @[Edges.scala 17:16] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_640 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_641 = dshl(UInt<1>("h01"), _T_640) @[OneHot.scala 49:12] + node _T_642 = bits(_T_641, 2, 0) @[OneHot.scala 49:37] + node _T_644 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_646 = bits(_T_642, 2, 2) @[package.scala 44:26] + node _T_647 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_649 = eq(_T_647, UInt<1>("h00")) @[package.scala 46:20] + node _T_650 = and(UInt<1>("h01"), _T_649) @[package.scala 49:27] + node _T_651 = and(_T_646, _T_650) @[package.scala 50:38] + node _T_652 = or(_T_644, _T_651) @[package.scala 50:29] + node _T_653 = and(UInt<1>("h01"), _T_647) @[package.scala 49:27] + node _T_654 = and(_T_646, _T_653) @[package.scala 50:38] + node _T_655 = or(_T_644, _T_654) @[package.scala 50:29] + node _T_656 = bits(_T_642, 1, 1) @[package.scala 44:26] + node _T_657 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_659 = eq(_T_657, UInt<1>("h00")) @[package.scala 46:20] + node _T_660 = and(_T_650, _T_659) @[package.scala 49:27] + node _T_661 = and(_T_656, _T_660) @[package.scala 50:38] + node _T_662 = or(_T_652, _T_661) @[package.scala 50:29] + node _T_663 = and(_T_650, _T_657) @[package.scala 49:27] + node _T_664 = and(_T_656, _T_663) @[package.scala 50:38] + node _T_665 = or(_T_652, _T_664) @[package.scala 50:29] + node _T_666 = and(_T_653, _T_659) @[package.scala 49:27] + node _T_667 = and(_T_656, _T_666) @[package.scala 50:38] + node _T_668 = or(_T_655, _T_667) @[package.scala 50:29] + node _T_669 = and(_T_653, _T_657) @[package.scala 49:27] + node _T_670 = and(_T_656, _T_669) @[package.scala 50:38] + node _T_671 = or(_T_655, _T_670) @[package.scala 50:29] + node _T_672 = bits(_T_642, 0, 0) @[package.scala 44:26] + node _T_673 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[package.scala 46:20] + node _T_676 = and(_T_660, _T_675) @[package.scala 49:27] + node _T_677 = and(_T_672, _T_676) @[package.scala 50:38] + node _T_678 = or(_T_662, _T_677) @[package.scala 50:29] + node _T_679 = and(_T_660, _T_673) @[package.scala 49:27] + node _T_680 = and(_T_672, _T_679) @[package.scala 50:38] + node _T_681 = or(_T_662, _T_680) @[package.scala 50:29] + node _T_682 = and(_T_663, _T_675) @[package.scala 49:27] + node _T_683 = and(_T_672, _T_682) @[package.scala 50:38] + node _T_684 = or(_T_665, _T_683) @[package.scala 50:29] + node _T_685 = and(_T_663, _T_673) @[package.scala 49:27] + node _T_686 = and(_T_672, _T_685) @[package.scala 50:38] + node _T_687 = or(_T_665, _T_686) @[package.scala 50:29] + node _T_688 = and(_T_666, _T_675) @[package.scala 49:27] + node _T_689 = and(_T_672, _T_688) @[package.scala 50:38] + node _T_690 = or(_T_668, _T_689) @[package.scala 50:29] + node _T_691 = and(_T_666, _T_673) @[package.scala 49:27] + node _T_692 = and(_T_672, _T_691) @[package.scala 50:38] + node _T_693 = or(_T_668, _T_692) @[package.scala 50:29] + node _T_694 = and(_T_669, _T_675) @[package.scala 49:27] + node _T_695 = and(_T_672, _T_694) @[package.scala 50:38] + node _T_696 = or(_T_671, _T_695) @[package.scala 50:29] + node _T_697 = and(_T_669, _T_673) @[package.scala 49:27] + node _T_698 = and(_T_672, _T_697) @[package.scala 50:38] + node _T_699 = or(_T_671, _T_698) @[package.scala 50:29] + node _T_700 = cat(_T_681, _T_678) @[Cat.scala 30:58] + node _T_701 = cat(_T_687, _T_684) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(_T_693, _T_690) @[Cat.scala 30:58] + node _T_704 = cat(_T_699, _T_696) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_708 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + when _T_708 : @[RocketPlexMaster.scala 19:15] + node _T_711 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_713 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_721 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_722 = cvt(_T_721) @[Parameters.scala 117:49] + node _T_724 = and(_T_722, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_725 = asSInt(_T_724) @[Parameters.scala 117:52] + node _T_727 = eq(_T_725, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_728 = or(_T_719, _T_727) @[Parameters.scala 133:42] + node _T_729 = and(_T_711, _T_728) @[Parameters.scala 132:56] + node _T_731 = or(UInt<1>("h00"), _T_729) @[Parameters.scala 134:30] + node _T_732 = or(_T_731, reset) @[RocketPlexMaster.scala 19:15] + node _T_734 = eq(_T_732, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_734 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_735 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_737 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_739 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_740 = or(_T_739, reset) @[RocketPlexMaster.scala 19:15] + node _T_742 = eq(_T_740, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_742 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_743 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_745 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_747 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_748 = or(_T_747, reset) @[RocketPlexMaster.scala 19:15] + node _T_750 = eq(_T_748, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_750 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_751 = not(io.in[0].a.bits.mask) @[RocketPlexMaster.scala 19:15] + node _T_753 = eq(_T_751, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_754 = or(_T_753, reset) @[RocketPlexMaster.scala 19:15] + node _T_756 = eq(_T_754, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_756 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_758 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 19:15] + when _T_758 : @[RocketPlexMaster.scala 19:15] + node _T_761 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_763 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_764 = and(_T_761, _T_763) @[Parameters.scala 63:37] + node _T_765 = or(UInt<1>("h00"), _T_764) @[Parameters.scala 132:31] + node _T_767 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_768 = cvt(_T_767) @[Parameters.scala 117:49] + node _T_770 = and(_T_768, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_771 = asSInt(_T_770) @[Parameters.scala 117:52] + node _T_773 = eq(_T_771, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_774 = and(_T_765, _T_773) @[Parameters.scala 132:56] + node _T_777 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_779 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_780 = and(_T_777, _T_779) @[Parameters.scala 63:37] + node _T_781 = or(UInt<1>("h00"), _T_780) @[Parameters.scala 132:31] + node _T_783 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_784 = cvt(_T_783) @[Parameters.scala 117:49] + node _T_786 = and(_T_784, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_787 = asSInt(_T_786) @[Parameters.scala 117:52] + node _T_789 = eq(_T_787, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_790 = and(_T_781, _T_789) @[Parameters.scala 132:56] + node _T_792 = or(UInt<1>("h00"), _T_774) @[Parameters.scala 134:30] + node _T_793 = or(_T_792, _T_790) @[Parameters.scala 134:30] + node _T_794 = or(_T_793, reset) @[RocketPlexMaster.scala 19:15] + node _T_796 = eq(_T_794, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_796 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_797 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_799 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_800 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_802 = eq(_T_800, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_802 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_804 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_805 = or(_T_804, reset) @[RocketPlexMaster.scala 19:15] + node _T_807 = eq(_T_805, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_807 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_808 = eq(io.in[0].a.bits.mask, _T_706) @[RocketPlexMaster.scala 19:15] + node _T_809 = or(_T_808, reset) @[RocketPlexMaster.scala 19:15] + node _T_811 = eq(_T_809, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_811 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_813 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_813 : @[RocketPlexMaster.scala 19:15] + node _T_816 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_818 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_819 = and(_T_816, _T_818) @[Parameters.scala 63:37] + node _T_820 = or(UInt<1>("h00"), _T_819) @[Parameters.scala 132:31] + node _T_822 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_823 = cvt(_T_822) @[Parameters.scala 117:49] + node _T_825 = and(_T_823, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_826 = asSInt(_T_825) @[Parameters.scala 117:52] + node _T_828 = eq(_T_826, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_829 = and(_T_820, _T_828) @[Parameters.scala 132:56] + node _T_832 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_834 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_835 = cvt(_T_834) @[Parameters.scala 117:49] + node _T_837 = and(_T_835, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_838 = asSInt(_T_837) @[Parameters.scala 117:52] + node _T_840 = eq(_T_838, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_841 = and(_T_832, _T_840) @[Parameters.scala 132:56] + node _T_843 = or(UInt<1>("h00"), _T_829) @[Parameters.scala 134:30] + node _T_844 = or(_T_843, _T_841) @[Parameters.scala 134:30] + node _T_845 = or(_T_844, reset) @[RocketPlexMaster.scala 19:15] + node _T_847 = eq(_T_845, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_847 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_848 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_850 = eq(_T_848, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_850 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_851 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_853 = eq(_T_851, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_853 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_855 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_856 = or(_T_855, reset) @[RocketPlexMaster.scala 19:15] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_858 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_859 = eq(io.in[0].a.bits.mask, _T_706) @[RocketPlexMaster.scala 19:15] + node _T_860 = or(_T_859, reset) @[RocketPlexMaster.scala 19:15] + node _T_862 = eq(_T_860, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_862 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_864 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 19:15] + when _T_864 : @[RocketPlexMaster.scala 19:15] + node _T_867 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_869 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_870 = and(_T_867, _T_869) @[Parameters.scala 63:37] + node _T_871 = or(UInt<1>("h00"), _T_870) @[Parameters.scala 132:31] + node _T_873 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_874 = cvt(_T_873) @[Parameters.scala 117:49] + node _T_876 = and(_T_874, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_877 = asSInt(_T_876) @[Parameters.scala 117:52] + node _T_879 = eq(_T_877, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_880 = and(_T_871, _T_879) @[Parameters.scala 132:56] + node _T_883 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_885 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_892 = and(_T_883, _T_891) @[Parameters.scala 132:56] + node _T_894 = or(UInt<1>("h00"), _T_880) @[Parameters.scala 134:30] + node _T_895 = or(_T_894, _T_892) @[Parameters.scala 134:30] + node _T_896 = or(_T_895, reset) @[RocketPlexMaster.scala 19:15] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_898 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_899 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_901 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_902 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_904 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_906 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_907 = or(_T_906, reset) @[RocketPlexMaster.scala 19:15] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_909 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_910 = not(_T_706) @[RocketPlexMaster.scala 19:15] + node _T_911 = and(io.in[0].a.bits.mask, _T_910) @[RocketPlexMaster.scala 19:15] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_914 = or(_T_913, reset) @[RocketPlexMaster.scala 19:15] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_916 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_918 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + when _T_918 : @[RocketPlexMaster.scala 19:15] + node _T_921 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_923 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_924 = cvt(_T_923) @[Parameters.scala 117:49] + node _T_926 = and(_T_924, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_927 = asSInt(_T_926) @[Parameters.scala 117:52] + node _T_929 = eq(_T_927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = or(_T_929, _T_937) @[Parameters.scala 133:42] + node _T_939 = and(_T_921, _T_938) @[Parameters.scala 132:56] + node _T_941 = or(UInt<1>("h00"), _T_939) @[Parameters.scala 134:30] + node _T_942 = or(_T_941, reset) @[RocketPlexMaster.scala 19:15] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_944 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_945 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_947 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_948 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_950 = eq(_T_948, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_950 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_952 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_953 = or(_T_952, reset) @[RocketPlexMaster.scala 19:15] + node _T_955 = eq(_T_953, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_955 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_956 = eq(io.in[0].a.bits.mask, _T_706) @[RocketPlexMaster.scala 19:15] + node _T_957 = or(_T_956, reset) @[RocketPlexMaster.scala 19:15] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_959 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_961 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + when _T_961 : @[RocketPlexMaster.scala 19:15] + node _T_964 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_966 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_967 = cvt(_T_966) @[Parameters.scala 117:49] + node _T_969 = and(_T_967, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_970 = asSInt(_T_969) @[Parameters.scala 117:52] + node _T_972 = eq(_T_970, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_975 = cvt(_T_974) @[Parameters.scala 117:49] + node _T_977 = and(_T_975, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_978 = asSInt(_T_977) @[Parameters.scala 117:52] + node _T_980 = eq(_T_978, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = or(_T_972, _T_980) @[Parameters.scala 133:42] + node _T_982 = and(_T_964, _T_981) @[Parameters.scala 132:56] + node _T_984 = or(UInt<1>("h00"), _T_982) @[Parameters.scala 134:30] + node _T_985 = or(_T_984, reset) @[RocketPlexMaster.scala 19:15] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_987 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_988 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_990 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_991 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_993 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_995 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_996 = or(_T_995, reset) @[RocketPlexMaster.scala 19:15] + node _T_998 = eq(_T_996, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_998 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_999 = eq(io.in[0].a.bits.mask, _T_706) @[RocketPlexMaster.scala 19:15] + node _T_1000 = or(_T_999, reset) @[RocketPlexMaster.scala 19:15] + node _T_1002 = eq(_T_1000, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1002 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1004 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 19:15] + when _T_1004 : @[RocketPlexMaster.scala 19:15] + node _T_1007 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1009 = xor(io.in[0].a.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1010 = cvt(_T_1009) @[Parameters.scala 117:49] + node _T_1012 = and(_T_1010, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1013 = asSInt(_T_1012) @[Parameters.scala 117:52] + node _T_1015 = eq(_T_1013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = xor(io.in[0].a.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1018 = cvt(_T_1017) @[Parameters.scala 117:49] + node _T_1020 = and(_T_1018, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1021 = asSInt(_T_1020) @[Parameters.scala 117:52] + node _T_1023 = eq(_T_1021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = or(_T_1015, _T_1023) @[Parameters.scala 133:42] + node _T_1025 = and(_T_1007, _T_1024) @[Parameters.scala 132:56] + node _T_1027 = or(UInt<1>("h00"), _T_1025) @[Parameters.scala 134:30] + node _T_1028 = or(_T_1027, reset) @[RocketPlexMaster.scala 19:15] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1030 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1031 = or(_T_630, reset) @[RocketPlexMaster.scala 19:15] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1033 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1034 = or(_T_638, reset) @[RocketPlexMaster.scala 19:15] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1036 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_706) @[RocketPlexMaster.scala 19:15] + node _T_1038 = or(_T_1037, reset) @[RocketPlexMaster.scala 19:15] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1040 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + when io.in[0].b.valid : @[RocketPlexMaster.scala 19:15] + node _T_1042 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1043 = or(_T_1042, reset) @[RocketPlexMaster.scala 19:15] + node _T_1045 = eq(_T_1043, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1045 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1047 = xor(io.in[0].b.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].b.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1064 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1064 is invalid @[Parameters.scala 110:36] + _T_1064[0] <= _T_1053 @[Parameters.scala 110:36] + _T_1064[1] <= _T_1061 @[Parameters.scala 110:36] + node _T_1069 = or(_T_1064[0], _T_1064[1]) @[Parameters.scala 119:64] + node _T_1071 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1072 = dshl(_T_1071, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1073 = bits(_T_1072, 7, 0) @[package.scala 19:76] + node _T_1074 = not(_T_1073) @[package.scala 19:40] + node _T_1075 = and(io.in[0].b.bits.address, _T_1074) @[Edges.scala 17:16] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1079 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1080 = dshl(UInt<1>("h01"), _T_1079) @[OneHot.scala 49:12] + node _T_1081 = bits(_T_1080, 2, 0) @[OneHot.scala 49:37] + node _T_1083 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1085 = bits(_T_1081, 2, 2) @[package.scala 44:26] + node _T_1086 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[package.scala 46:20] + node _T_1089 = and(UInt<1>("h01"), _T_1088) @[package.scala 49:27] + node _T_1090 = and(_T_1085, _T_1089) @[package.scala 50:38] + node _T_1091 = or(_T_1083, _T_1090) @[package.scala 50:29] + node _T_1092 = and(UInt<1>("h01"), _T_1086) @[package.scala 49:27] + node _T_1093 = and(_T_1085, _T_1092) @[package.scala 50:38] + node _T_1094 = or(_T_1083, _T_1093) @[package.scala 50:29] + node _T_1095 = bits(_T_1081, 1, 1) @[package.scala 44:26] + node _T_1096 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1098 = eq(_T_1096, UInt<1>("h00")) @[package.scala 46:20] + node _T_1099 = and(_T_1089, _T_1098) @[package.scala 49:27] + node _T_1100 = and(_T_1095, _T_1099) @[package.scala 50:38] + node _T_1101 = or(_T_1091, _T_1100) @[package.scala 50:29] + node _T_1102 = and(_T_1089, _T_1096) @[package.scala 49:27] + node _T_1103 = and(_T_1095, _T_1102) @[package.scala 50:38] + node _T_1104 = or(_T_1091, _T_1103) @[package.scala 50:29] + node _T_1105 = and(_T_1092, _T_1098) @[package.scala 49:27] + node _T_1106 = and(_T_1095, _T_1105) @[package.scala 50:38] + node _T_1107 = or(_T_1094, _T_1106) @[package.scala 50:29] + node _T_1108 = and(_T_1092, _T_1096) @[package.scala 49:27] + node _T_1109 = and(_T_1095, _T_1108) @[package.scala 50:38] + node _T_1110 = or(_T_1094, _T_1109) @[package.scala 50:29] + node _T_1111 = bits(_T_1081, 0, 0) @[package.scala 44:26] + node _T_1112 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[package.scala 46:20] + node _T_1115 = and(_T_1099, _T_1114) @[package.scala 49:27] + node _T_1116 = and(_T_1111, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1101, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1099, _T_1112) @[package.scala 49:27] + node _T_1119 = and(_T_1111, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1101, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1102, _T_1114) @[package.scala 49:27] + node _T_1122 = and(_T_1111, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1104, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1102, _T_1112) @[package.scala 49:27] + node _T_1125 = and(_T_1111, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1104, _T_1125) @[package.scala 50:29] + node _T_1127 = and(_T_1105, _T_1114) @[package.scala 49:27] + node _T_1128 = and(_T_1111, _T_1127) @[package.scala 50:38] + node _T_1129 = or(_T_1107, _T_1128) @[package.scala 50:29] + node _T_1130 = and(_T_1105, _T_1112) @[package.scala 49:27] + node _T_1131 = and(_T_1111, _T_1130) @[package.scala 50:38] + node _T_1132 = or(_T_1107, _T_1131) @[package.scala 50:29] + node _T_1133 = and(_T_1108, _T_1114) @[package.scala 49:27] + node _T_1134 = and(_T_1111, _T_1133) @[package.scala 50:38] + node _T_1135 = or(_T_1110, _T_1134) @[package.scala 50:29] + node _T_1136 = and(_T_1108, _T_1112) @[package.scala 49:27] + node _T_1137 = and(_T_1111, _T_1136) @[package.scala 50:38] + node _T_1138 = or(_T_1110, _T_1137) @[package.scala 50:29] + node _T_1139 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + when _T_1147 : @[RocketPlexMaster.scala 19:15] + node _T_1149 = xor(UInt<1>("h00"), io.in[0].b.bits.source) @[Parameters.scala 37:23] + node _T_1150 = not(_T_1149) @[Parameters.scala 37:9] + node _T_1152 = or(_T_1150, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1153 = not(_T_1152) @[Parameters.scala 37:7] + node _T_1155 = eq(_T_1153, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1157 = eq(UInt<3>("h05"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + node _T_1159 = eq(UInt<3>("h04"), io.in[0].b.bits.source) @[Parameters.scala 35:39] + wire _T_1162 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1162 is invalid @[Parameters.scala 228:27] + _T_1162[0] <= _T_1155 @[Parameters.scala 228:27] + _T_1162[1] <= _T_1157 @[Parameters.scala 228:27] + _T_1162[2] <= _T_1159 @[Parameters.scala 228:27] + node _T_1170 = leq(UInt<1>("h00"), io.in[0].b.bits.size) @[Parameters.scala 63:32] + node _T_1172 = leq(io.in[0].b.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_1173 = and(_T_1170, _T_1172) @[Parameters.scala 63:37] + node _T_1176 = mux(_T_1162[0], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1178 = mux(_T_1162[1], _T_1173, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1180 = mux(_T_1162[2], UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_1182 = or(_T_1176, _T_1178) @[Mux.scala 19:72] + node _T_1183 = or(_T_1182, _T_1180) @[Mux.scala 19:72] + wire _T_1185 : UInt<1> @[Mux.scala 19:72] + _T_1185 is invalid @[Mux.scala 19:72] + _T_1185 <= _T_1183 @[Mux.scala 19:72] + node _T_1186 = or(_T_1185, reset) @[RocketPlexMaster.scala 19:15] + node _T_1188 = eq(_T_1186, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1188 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1189 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1191 = eq(_T_1189, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1191 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1193 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1194 = or(_T_1193, reset) @[RocketPlexMaster.scala 19:15] + node _T_1196 = eq(_T_1194, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1196 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1197 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1199 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1201 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1202 = or(_T_1201, reset) @[RocketPlexMaster.scala 19:15] + node _T_1204 = eq(_T_1202, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1204 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1205 = not(io.in[0].b.bits.mask) @[RocketPlexMaster.scala 19:15] + node _T_1207 = eq(_T_1205, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1208 = or(_T_1207, reset) @[RocketPlexMaster.scala 19:15] + node _T_1210 = eq(_T_1208, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1210 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1212 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 19:15] + when _T_1212 : @[RocketPlexMaster.scala 19:15] + node _T_1214 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1216 = eq(_T_1214, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1216 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1217 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1219 = eq(_T_1217, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1219 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1220 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1222 = eq(_T_1220, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1222 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1224 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1225 = or(_T_1224, reset) @[RocketPlexMaster.scala 19:15] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1227 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1228 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1229 = or(_T_1228, reset) @[RocketPlexMaster.scala 19:15] + node _T_1231 = eq(_T_1229, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1231 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1233 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1233 : @[RocketPlexMaster.scala 19:15] + node _T_1235 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1237 = eq(_T_1235, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1237 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1238 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1240 = eq(_T_1238, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1240 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1241 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1243 = eq(_T_1241, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1243 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1245 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1246 = or(_T_1245, reset) @[RocketPlexMaster.scala 19:15] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1248 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1249 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1250 = or(_T_1249, reset) @[RocketPlexMaster.scala 19:15] + node _T_1252 = eq(_T_1250, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1252 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1254 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 19:15] + when _T_1254 : @[RocketPlexMaster.scala 19:15] + node _T_1256 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1258 = eq(_T_1256, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1258 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1259 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1261 = eq(_T_1259, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1261 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1262 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1264 = eq(_T_1262, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1264 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1266 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1267 = or(_T_1266, reset) @[RocketPlexMaster.scala 19:15] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1269 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1270 = not(_T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1271 = and(io.in[0].b.bits.mask, _T_1270) @[RocketPlexMaster.scala 19:15] + node _T_1273 = eq(_T_1271, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1274 = or(_T_1273, reset) @[RocketPlexMaster.scala 19:15] + node _T_1276 = eq(_T_1274, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1276 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1278 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + when _T_1278 : @[RocketPlexMaster.scala 19:15] + node _T_1280 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1282 = eq(_T_1280, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1282 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1283 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1285 = eq(_T_1283, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1285 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1286 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1288 = eq(_T_1286, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1288 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1290 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1291 = or(_T_1290, reset) @[RocketPlexMaster.scala 19:15] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1293 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1294 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1295 = or(_T_1294, reset) @[RocketPlexMaster.scala 19:15] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1297 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1299 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + when _T_1299 : @[RocketPlexMaster.scala 19:15] + node _T_1301 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1303 = eq(_T_1301, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1303 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1304 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1306 = eq(_T_1304, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1306 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1307 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1309 = eq(_T_1307, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1309 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1311 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1312 = or(_T_1311, reset) @[RocketPlexMaster.scala 19:15] + node _T_1314 = eq(_T_1312, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1314 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1315 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1316 = or(_T_1315, reset) @[RocketPlexMaster.scala 19:15] + node _T_1318 = eq(_T_1316, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1318 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1320 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 19:15] + when _T_1320 : @[RocketPlexMaster.scala 19:15] + node _T_1322 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 19:15] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1324 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1325 = or(_T_1069, reset) @[RocketPlexMaster.scala 19:15] + node _T_1327 = eq(_T_1325, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1327 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1328 = or(_T_1077, reset) @[RocketPlexMaster.scala 19:15] + node _T_1330 = eq(_T_1328, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1330 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1331 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 19:15] + node _T_1332 = or(_T_1331, reset) @[RocketPlexMaster.scala 19:15] + node _T_1334 = eq(_T_1332, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1334 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + when io.in[0].c.valid : @[RocketPlexMaster.scala 19:15] + node _T_1336 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1337 = or(_T_1336, reset) @[RocketPlexMaster.scala 19:15] + node _T_1339 = eq(_T_1337, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1339 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1341 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1342 = not(_T_1341) @[Parameters.scala 37:9] + node _T_1344 = or(_T_1342, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1345 = not(_T_1344) @[Parameters.scala 37:7] + node _T_1347 = eq(_T_1345, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1349 = eq(UInt<3>("h05"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + node _T_1351 = eq(UInt<3>("h04"), io.in[0].c.bits.source) @[Parameters.scala 35:39] + wire _T_1354 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1354 is invalid @[Parameters.scala 228:27] + _T_1354[0] <= _T_1347 @[Parameters.scala 228:27] + _T_1354[1] <= _T_1349 @[Parameters.scala 228:27] + _T_1354[2] <= _T_1351 @[Parameters.scala 228:27] + node _T_1360 = or(_T_1354[0], _T_1354[1]) @[Parameters.scala 229:46] + node _T_1361 = or(_T_1360, _T_1354[2]) @[Parameters.scala 229:46] + node _T_1363 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1364 = dshl(_T_1363, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1365 = bits(_T_1364, 7, 0) @[package.scala 19:76] + node _T_1366 = not(_T_1365) @[package.scala 19:40] + node _T_1367 = and(io.in[0].c.bits.address, _T_1366) @[Edges.scala 17:16] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1371 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1372 = cvt(_T_1371) @[Parameters.scala 117:49] + node _T_1374 = and(_T_1372, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1375 = asSInt(_T_1374) @[Parameters.scala 117:52] + node _T_1377 = eq(_T_1375, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1379 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1380 = cvt(_T_1379) @[Parameters.scala 117:49] + node _T_1382 = and(_T_1380, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1383 = asSInt(_T_1382) @[Parameters.scala 117:52] + node _T_1385 = eq(_T_1383, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1388 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1388 is invalid @[Parameters.scala 110:36] + _T_1388[0] <= _T_1377 @[Parameters.scala 110:36] + _T_1388[1] <= _T_1385 @[Parameters.scala 110:36] + node _T_1393 = or(_T_1388[0], _T_1388[1]) @[Parameters.scala 119:64] + node _T_1395 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 19:15] + when _T_1395 : @[RocketPlexMaster.scala 19:15] + node _T_1396 = or(_T_1393, reset) @[RocketPlexMaster.scala 19:15] + node _T_1398 = eq(_T_1396, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1398 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1399 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1401 = eq(_T_1399, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1401 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1403 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1404 = or(_T_1403, reset) @[RocketPlexMaster.scala 19:15] + node _T_1406 = eq(_T_1404, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1406 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1407 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1409 = eq(_T_1407, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1409 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1411 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1412 = or(_T_1411, reset) @[RocketPlexMaster.scala 19:15] + node _T_1414 = eq(_T_1412, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1414 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1416 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1417 = or(_T_1416, reset) @[RocketPlexMaster.scala 19:15] + node _T_1419 = eq(_T_1417, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1419 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1421 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 19:15] + when _T_1421 : @[RocketPlexMaster.scala 19:15] + node _T_1422 = or(_T_1393, reset) @[RocketPlexMaster.scala 19:15] + node _T_1424 = eq(_T_1422, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1424 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1425 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1427 = eq(_T_1425, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1427 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1429 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1430 = or(_T_1429, reset) @[RocketPlexMaster.scala 19:15] + node _T_1432 = eq(_T_1430, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1432 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1433 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1435 = eq(_T_1433, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1435 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1437 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1438 = or(_T_1437, reset) @[RocketPlexMaster.scala 19:15] + node _T_1440 = eq(_T_1438, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1440 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1442 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1443 = or(_T_1442, reset) @[RocketPlexMaster.scala 19:15] + node _T_1445 = eq(_T_1443, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1445 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1447 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + when _T_1447 : @[RocketPlexMaster.scala 19:15] + node _T_1450 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1452 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1453 = cvt(_T_1452) @[Parameters.scala 117:49] + node _T_1455 = and(_T_1453, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1456 = asSInt(_T_1455) @[Parameters.scala 117:52] + node _T_1458 = eq(_T_1456, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1460 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1461 = cvt(_T_1460) @[Parameters.scala 117:49] + node _T_1463 = and(_T_1461, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1464 = asSInt(_T_1463) @[Parameters.scala 117:52] + node _T_1466 = eq(_T_1464, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1467 = or(_T_1458, _T_1466) @[Parameters.scala 133:42] + node _T_1468 = and(_T_1450, _T_1467) @[Parameters.scala 132:56] + node _T_1470 = or(UInt<1>("h00"), _T_1468) @[Parameters.scala 134:30] + node _T_1471 = or(_T_1470, reset) @[RocketPlexMaster.scala 19:15] + node _T_1473 = eq(_T_1471, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1473 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1474 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1476 = eq(_T_1474, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1476 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1478 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1479 = or(_T_1478, reset) @[RocketPlexMaster.scala 19:15] + node _T_1481 = eq(_T_1479, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1481 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1482 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1484 = eq(_T_1482, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1484 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1486 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1487 = or(_T_1486, reset) @[RocketPlexMaster.scala 19:15] + node _T_1489 = eq(_T_1487, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1489 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1491 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1492 = or(_T_1491, reset) @[RocketPlexMaster.scala 19:15] + node _T_1494 = eq(_T_1492, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1494 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1496 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RocketPlexMaster.scala 19:15] + when _T_1496 : @[RocketPlexMaster.scala 19:15] + node _T_1499 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1501 = xor(io.in[0].c.bits.address, UInt<13>("h01000")) @[Parameters.scala 117:31] + node _T_1502 = cvt(_T_1501) @[Parameters.scala 117:49] + node _T_1504 = and(_T_1502, asSInt(UInt<13>("h01000"))) @[Parameters.scala 117:52] + node _T_1505 = asSInt(_T_1504) @[Parameters.scala 117:52] + node _T_1507 = eq(_T_1505, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1509 = xor(io.in[0].c.bits.address, UInt<31>("h060000000")) @[Parameters.scala 117:31] + node _T_1510 = cvt(_T_1509) @[Parameters.scala 117:49] + node _T_1512 = and(_T_1510, asSInt(UInt<30>("h020000000"))) @[Parameters.scala 117:52] + node _T_1513 = asSInt(_T_1512) @[Parameters.scala 117:52] + node _T_1515 = eq(_T_1513, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1516 = or(_T_1507, _T_1515) @[Parameters.scala 133:42] + node _T_1517 = and(_T_1499, _T_1516) @[Parameters.scala 132:56] + node _T_1519 = or(UInt<1>("h00"), _T_1517) @[Parameters.scala 134:30] + node _T_1520 = or(_T_1519, reset) @[RocketPlexMaster.scala 19:15] + node _T_1522 = eq(_T_1520, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1522 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1523 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1525 = eq(_T_1523, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1525 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1527 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1528 = or(_T_1527, reset) @[RocketPlexMaster.scala 19:15] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1530 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1531 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1533 = eq(_T_1531, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1533 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1535 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1536 = or(_T_1535, reset) @[RocketPlexMaster.scala 19:15] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1538 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1540 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1541 = or(_T_1540, reset) @[RocketPlexMaster.scala 19:15] + node _T_1543 = eq(_T_1541, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1543 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1545 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1545 : @[RocketPlexMaster.scala 19:15] + node _T_1546 = or(_T_1393, reset) @[RocketPlexMaster.scala 19:15] + node _T_1548 = eq(_T_1546, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1548 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1549 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1551 = eq(_T_1549, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1551 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1552 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1554 = eq(_T_1552, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1554 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1556 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1557 = or(_T_1556, reset) @[RocketPlexMaster.scala 19:15] + node _T_1559 = eq(_T_1557, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1559 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1561 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 19:15] + when _T_1561 : @[RocketPlexMaster.scala 19:15] + node _T_1562 = or(_T_1393, reset) @[RocketPlexMaster.scala 19:15] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1564 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1565 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1567 = eq(_T_1565, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1567 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1568 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1570 = eq(_T_1568, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1570 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1572 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1573 = or(_T_1572, reset) @[RocketPlexMaster.scala 19:15] + node _T_1575 = eq(_T_1573, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1575 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1577 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + when _T_1577 : @[RocketPlexMaster.scala 19:15] + node _T_1578 = or(_T_1393, reset) @[RocketPlexMaster.scala 19:15] + node _T_1580 = eq(_T_1578, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1580 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1581 = or(_T_1361, reset) @[RocketPlexMaster.scala 19:15] + node _T_1583 = eq(_T_1581, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1583 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1584 = or(_T_1369, reset) @[RocketPlexMaster.scala 19:15] + node _T_1586 = eq(_T_1584, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1586 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1588 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1589 = or(_T_1588, reset) @[RocketPlexMaster.scala 19:15] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1591 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1593 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1594 = or(_T_1593, reset) @[RocketPlexMaster.scala 19:15] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1596 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + when io.in[0].d.valid : @[RocketPlexMaster.scala 19:15] + node _T_1598 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1599 = or(_T_1598, reset) @[RocketPlexMaster.scala 19:15] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1601 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1603 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1604 = not(_T_1603) @[Parameters.scala 37:9] + node _T_1606 = or(_T_1604, UInt<2>("h03")) @[Parameters.scala 37:28] + node _T_1607 = not(_T_1606) @[Parameters.scala 37:7] + node _T_1609 = eq(_T_1607, UInt<1>("h00")) @[Parameters.scala 37:49] + node _T_1611 = eq(UInt<3>("h05"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + node _T_1613 = eq(UInt<3>("h04"), io.in[0].d.bits.source) @[Parameters.scala 35:39] + wire _T_1616 : UInt<1>[3] @[Parameters.scala 228:27] + _T_1616 is invalid @[Parameters.scala 228:27] + _T_1616[0] <= _T_1609 @[Parameters.scala 228:27] + _T_1616[1] <= _T_1611 @[Parameters.scala 228:27] + _T_1616[2] <= _T_1613 @[Parameters.scala 228:27] + node _T_1622 = or(_T_1616[0], _T_1616[1]) @[Parameters.scala 229:46] + node _T_1623 = or(_T_1622, _T_1616[2]) @[Parameters.scala 229:46] + node _T_1625 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1626 = dshl(_T_1625, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1627 = bits(_T_1626, 7, 0) @[package.scala 19:76] + node _T_1628 = not(_T_1627) @[package.scala 19:40] + node _T_1629 = and(io.in[0].d.bits.addr_lo, _T_1628) @[Edges.scala 17:16] + node _T_1631 = eq(_T_1629, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1633 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + node _T_1635 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + when _T_1635 : @[RocketPlexMaster.scala 19:15] + node _T_1636 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1638 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1639 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1641 = eq(_T_1639, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1641 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1642 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1644 = eq(_T_1642, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1644 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1646 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1647 = or(_T_1646, reset) @[RocketPlexMaster.scala 19:15] + node _T_1649 = eq(_T_1647, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1649 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1651 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1652 = or(_T_1651, reset) @[RocketPlexMaster.scala 19:15] + node _T_1654 = eq(_T_1652, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1654 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1656 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1657 = or(_T_1656, reset) @[RocketPlexMaster.scala 19:15] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1659 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1661 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 19:15] + when _T_1661 : @[RocketPlexMaster.scala 19:15] + node _T_1662 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1664 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1665 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1667 = eq(_T_1665, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1667 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1668 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1670 = eq(_T_1668, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1670 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1672 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1673 = or(_T_1672, reset) @[RocketPlexMaster.scala 19:15] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1675 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1677 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1678 = or(_T_1677, reset) @[RocketPlexMaster.scala 19:15] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1680 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1682 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 19:15] + when _T_1682 : @[RocketPlexMaster.scala 19:15] + node _T_1683 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1685 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1686 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1688 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1689 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1691 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1693 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 19:15] + node _T_1694 = or(_T_1693, reset) @[RocketPlexMaster.scala 19:15] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1696 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1698 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1699 = or(_T_1698, reset) @[RocketPlexMaster.scala 19:15] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1701 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1703 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1703 : @[RocketPlexMaster.scala 19:15] + node _T_1704 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1706 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1707 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1709 = eq(_T_1707, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1709 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1710 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1712 = eq(_T_1710, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1712 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1714 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1715 = or(_T_1714, reset) @[RocketPlexMaster.scala 19:15] + node _T_1717 = eq(_T_1715, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1717 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1719 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 19:15] + when _T_1719 : @[RocketPlexMaster.scala 19:15] + node _T_1720 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1722 = eq(_T_1720, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1722 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1723 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1725 = eq(_T_1723, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1725 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1726 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1728 = eq(_T_1726, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1728 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1730 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1731 = or(_T_1730, reset) @[RocketPlexMaster.scala 19:15] + node _T_1733 = eq(_T_1731, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1733 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1735 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + when _T_1735 : @[RocketPlexMaster.scala 19:15] + node _T_1736 = or(_T_1623, reset) @[RocketPlexMaster.scala 19:15] + node _T_1738 = eq(_T_1736, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1738 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1739 = or(_T_1631, reset) @[RocketPlexMaster.scala 19:15] + node _T_1741 = eq(_T_1739, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1741 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1742 = or(_T_1633, reset) @[RocketPlexMaster.scala 19:15] + node _T_1744 = eq(_T_1742, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1744 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1746 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1747 = or(_T_1746, reset) @[RocketPlexMaster.scala 19:15] + node _T_1749 = eq(_T_1747, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1749 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1751 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1752 = or(_T_1751, reset) @[RocketPlexMaster.scala 19:15] + node _T_1754 = eq(_T_1752, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1754 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + when io.in[0].e.valid : @[RocketPlexMaster.scala 19:15] + node _T_1756 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[RocketPlexMaster.scala 19:15] + node _T_1757 = or(_T_1756, reset) @[RocketPlexMaster.scala 19:15] + node _T_1759 = eq(_T_1757, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1759 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1760 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1762 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1763 = dshl(_T_1762, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1764 = bits(_T_1763, 7, 0) @[package.scala 19:76] + node _T_1765 = not(_T_1764) @[package.scala 19:40] + node _T_1766 = shr(_T_1765, 3) @[Edges.scala 198:59] + node _T_1767 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1771 = mux(_T_1769, _T_1766, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1773 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1775 = sub(_T_1773, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1776 = asUInt(_T_1775) @[Edges.scala 208:28] + node _T_1777 = tail(_T_1776, 1) @[Edges.scala 208:28] + node _T_1779 = eq(_T_1773, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1781 = eq(_T_1773, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1783 = eq(_T_1771, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1784 = or(_T_1781, _T_1783) @[Edges.scala 210:37] + node _T_1785 = and(_T_1784, _T_1760) @[Edges.scala 211:22] + node _T_1786 = not(_T_1777) @[Edges.scala 212:27] + node _T_1787 = and(_T_1771, _T_1786) @[Edges.scala 212:25] + when _T_1760 : @[Edges.scala 213:17] + node _T_1788 = mux(_T_1779, _T_1771, _T_1777) @[Edges.scala 214:21] + _T_1773 <= _T_1788 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1790 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1792 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1794 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1796 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1798 : UInt, clock @[RocketPlexMaster.scala 19:15] + node _T_1800 = eq(_T_1779, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1801 = and(io.in[0].a.valid, _T_1800) @[RocketPlexMaster.scala 19:15] + when _T_1801 : @[RocketPlexMaster.scala 19:15] + node _T_1802 = eq(io.in[0].a.bits.opcode, _T_1790) @[RocketPlexMaster.scala 19:15] + node _T_1803 = or(_T_1802, reset) @[RocketPlexMaster.scala 19:15] + node _T_1805 = eq(_T_1803, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1805 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1806 = eq(io.in[0].a.bits.param, _T_1792) @[RocketPlexMaster.scala 19:15] + node _T_1807 = or(_T_1806, reset) @[RocketPlexMaster.scala 19:15] + node _T_1809 = eq(_T_1807, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1809 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1810 = eq(io.in[0].a.bits.size, _T_1794) @[RocketPlexMaster.scala 19:15] + node _T_1811 = or(_T_1810, reset) @[RocketPlexMaster.scala 19:15] + node _T_1813 = eq(_T_1811, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1813 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1814 = eq(io.in[0].a.bits.source, _T_1796) @[RocketPlexMaster.scala 19:15] + node _T_1815 = or(_T_1814, reset) @[RocketPlexMaster.scala 19:15] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1817 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1818 = eq(io.in[0].a.bits.address, _T_1798) @[RocketPlexMaster.scala 19:15] + node _T_1819 = or(_T_1818, reset) @[RocketPlexMaster.scala 19:15] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1821 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1822 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1823 = and(_T_1822, _T_1779) @[RocketPlexMaster.scala 19:15] + when _T_1823 : @[RocketPlexMaster.scala 19:15] + _T_1790 <= io.in[0].a.bits.opcode @[RocketPlexMaster.scala 19:15] + _T_1792 <= io.in[0].a.bits.param @[RocketPlexMaster.scala 19:15] + _T_1794 <= io.in[0].a.bits.size @[RocketPlexMaster.scala 19:15] + _T_1796 <= io.in[0].a.bits.source @[RocketPlexMaster.scala 19:15] + _T_1798 <= io.in[0].a.bits.address @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1824 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1826 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1827 = dshl(_T_1826, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1828 = bits(_T_1827, 7, 0) @[package.scala 19:76] + node _T_1829 = not(_T_1828) @[package.scala 19:40] + node _T_1830 = shr(_T_1829, 3) @[Edges.scala 198:59] + node _T_1831 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1836 = mux(UInt<1>("h00"), _T_1830, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1838 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1840 = sub(_T_1838, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1841 = asUInt(_T_1840) @[Edges.scala 208:28] + node _T_1842 = tail(_T_1841, 1) @[Edges.scala 208:28] + node _T_1844 = eq(_T_1838, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1846 = eq(_T_1838, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1848 = eq(_T_1836, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1849 = or(_T_1846, _T_1848) @[Edges.scala 210:37] + node _T_1850 = and(_T_1849, _T_1824) @[Edges.scala 211:22] + node _T_1851 = not(_T_1842) @[Edges.scala 212:27] + node _T_1852 = and(_T_1836, _T_1851) @[Edges.scala 212:25] + when _T_1824 : @[Edges.scala 213:17] + node _T_1853 = mux(_T_1844, _T_1836, _T_1842) @[Edges.scala 214:21] + _T_1838 <= _T_1853 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1855 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1857 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1859 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1861 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1863 : UInt, clock @[RocketPlexMaster.scala 19:15] + node _T_1865 = eq(_T_1844, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1866 = and(io.in[0].b.valid, _T_1865) @[RocketPlexMaster.scala 19:15] + when _T_1866 : @[RocketPlexMaster.scala 19:15] + node _T_1867 = eq(io.in[0].b.bits.opcode, _T_1855) @[RocketPlexMaster.scala 19:15] + node _T_1868 = or(_T_1867, reset) @[RocketPlexMaster.scala 19:15] + node _T_1870 = eq(_T_1868, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1870 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1871 = eq(io.in[0].b.bits.param, _T_1857) @[RocketPlexMaster.scala 19:15] + node _T_1872 = or(_T_1871, reset) @[RocketPlexMaster.scala 19:15] + node _T_1874 = eq(_T_1872, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1874 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1875 = eq(io.in[0].b.bits.size, _T_1859) @[RocketPlexMaster.scala 19:15] + node _T_1876 = or(_T_1875, reset) @[RocketPlexMaster.scala 19:15] + node _T_1878 = eq(_T_1876, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1878 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1879 = eq(io.in[0].b.bits.source, _T_1861) @[RocketPlexMaster.scala 19:15] + node _T_1880 = or(_T_1879, reset) @[RocketPlexMaster.scala 19:15] + node _T_1882 = eq(_T_1880, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1882 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1883 = eq(io.in[0].b.bits.address, _T_1863) @[RocketPlexMaster.scala 19:15] + node _T_1884 = or(_T_1883, reset) @[RocketPlexMaster.scala 19:15] + node _T_1886 = eq(_T_1884, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1886 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1887 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1888 = and(_T_1887, _T_1844) @[RocketPlexMaster.scala 19:15] + when _T_1888 : @[RocketPlexMaster.scala 19:15] + _T_1855 <= io.in[0].b.bits.opcode @[RocketPlexMaster.scala 19:15] + _T_1857 <= io.in[0].b.bits.param @[RocketPlexMaster.scala 19:15] + _T_1859 <= io.in[0].b.bits.size @[RocketPlexMaster.scala 19:15] + _T_1861 <= io.in[0].b.bits.source @[RocketPlexMaster.scala 19:15] + _T_1863 <= io.in[0].b.bits.address @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1889 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1891 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1892 = dshl(_T_1891, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1893 = bits(_T_1892, 7, 0) @[package.scala 19:76] + node _T_1894 = not(_T_1893) @[package.scala 19:40] + node _T_1895 = shr(_T_1894, 3) @[Edges.scala 198:59] + node _T_1896 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1898 = mux(_T_1896, _T_1895, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1900 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1902 = sub(_T_1900, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1903 = asUInt(_T_1902) @[Edges.scala 208:28] + node _T_1904 = tail(_T_1903, 1) @[Edges.scala 208:28] + node _T_1906 = eq(_T_1900, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1908 = eq(_T_1900, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1910 = eq(_T_1898, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1911 = or(_T_1908, _T_1910) @[Edges.scala 210:37] + node _T_1912 = and(_T_1911, _T_1889) @[Edges.scala 211:22] + node _T_1913 = not(_T_1904) @[Edges.scala 212:27] + node _T_1914 = and(_T_1898, _T_1913) @[Edges.scala 212:25] + when _T_1889 : @[Edges.scala 213:17] + node _T_1915 = mux(_T_1906, _T_1898, _T_1904) @[Edges.scala 214:21] + _T_1900 <= _T_1915 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1917 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1919 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1921 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1923 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1925 : UInt, clock @[RocketPlexMaster.scala 19:15] + node _T_1927 = eq(_T_1906, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1928 = and(io.in[0].c.valid, _T_1927) @[RocketPlexMaster.scala 19:15] + when _T_1928 : @[RocketPlexMaster.scala 19:15] + node _T_1929 = eq(io.in[0].c.bits.opcode, _T_1917) @[RocketPlexMaster.scala 19:15] + node _T_1930 = or(_T_1929, reset) @[RocketPlexMaster.scala 19:15] + node _T_1932 = eq(_T_1930, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1932 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1933 = eq(io.in[0].c.bits.param, _T_1919) @[RocketPlexMaster.scala 19:15] + node _T_1934 = or(_T_1933, reset) @[RocketPlexMaster.scala 19:15] + node _T_1936 = eq(_T_1934, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1936 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1937 = eq(io.in[0].c.bits.size, _T_1921) @[RocketPlexMaster.scala 19:15] + node _T_1938 = or(_T_1937, reset) @[RocketPlexMaster.scala 19:15] + node _T_1940 = eq(_T_1938, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1940 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1941 = eq(io.in[0].c.bits.source, _T_1923) @[RocketPlexMaster.scala 19:15] + node _T_1942 = or(_T_1941, reset) @[RocketPlexMaster.scala 19:15] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1944 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1945 = eq(io.in[0].c.bits.address, _T_1925) @[RocketPlexMaster.scala 19:15] + node _T_1946 = or(_T_1945, reset) @[RocketPlexMaster.scala 19:15] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1948 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1949 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1950 = and(_T_1949, _T_1906) @[RocketPlexMaster.scala 19:15] + when _T_1950 : @[RocketPlexMaster.scala 19:15] + _T_1917 <= io.in[0].c.bits.opcode @[RocketPlexMaster.scala 19:15] + _T_1919 <= io.in[0].c.bits.param @[RocketPlexMaster.scala 19:15] + _T_1921 <= io.in[0].c.bits.size @[RocketPlexMaster.scala 19:15] + _T_1923 <= io.in[0].c.bits.source @[RocketPlexMaster.scala 19:15] + _T_1925 <= io.in[0].c.bits.address @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1951 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1953 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1954 = dshl(_T_1953, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1955 = bits(_T_1954, 7, 0) @[package.scala 19:76] + node _T_1956 = not(_T_1955) @[package.scala 19:40] + node _T_1957 = shr(_T_1956, 3) @[Edges.scala 198:59] + node _T_1958 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1960 = mux(_T_1958, _T_1957, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1962 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1964 = sub(_T_1962, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1965 = asUInt(_T_1964) @[Edges.scala 208:28] + node _T_1966 = tail(_T_1965, 1) @[Edges.scala 208:28] + node _T_1968 = eq(_T_1962, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1970 = eq(_T_1962, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1972 = eq(_T_1960, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1973 = or(_T_1970, _T_1972) @[Edges.scala 210:37] + node _T_1974 = and(_T_1973, _T_1951) @[Edges.scala 211:22] + node _T_1975 = not(_T_1966) @[Edges.scala 212:27] + node _T_1976 = and(_T_1960, _T_1975) @[Edges.scala 212:25] + when _T_1951 : @[Edges.scala 213:17] + node _T_1977 = mux(_T_1968, _T_1960, _T_1966) @[Edges.scala 214:21] + _T_1962 <= _T_1977 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1979 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1981 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1983 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1985 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1987 : UInt, clock @[RocketPlexMaster.scala 19:15] + reg _T_1989 : UInt, clock @[RocketPlexMaster.scala 19:15] + node _T_1991 = eq(_T_1968, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_1992 = and(io.in[0].d.valid, _T_1991) @[RocketPlexMaster.scala 19:15] + when _T_1992 : @[RocketPlexMaster.scala 19:15] + node _T_1993 = eq(io.in[0].d.bits.opcode, _T_1979) @[RocketPlexMaster.scala 19:15] + node _T_1994 = or(_T_1993, reset) @[RocketPlexMaster.scala 19:15] + node _T_1996 = eq(_T_1994, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_1996 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_1997 = eq(io.in[0].d.bits.param, _T_1981) @[RocketPlexMaster.scala 19:15] + node _T_1998 = or(_T_1997, reset) @[RocketPlexMaster.scala 19:15] + node _T_2000 = eq(_T_1998, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2000 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2001 = eq(io.in[0].d.bits.size, _T_1983) @[RocketPlexMaster.scala 19:15] + node _T_2002 = or(_T_2001, reset) @[RocketPlexMaster.scala 19:15] + node _T_2004 = eq(_T_2002, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2004 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2005 = eq(io.in[0].d.bits.source, _T_1985) @[RocketPlexMaster.scala 19:15] + node _T_2006 = or(_T_2005, reset) @[RocketPlexMaster.scala 19:15] + node _T_2008 = eq(_T_2006, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2008 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2009 = eq(io.in[0].d.bits.sink, _T_1987) @[RocketPlexMaster.scala 19:15] + node _T_2010 = or(_T_2009, reset) @[RocketPlexMaster.scala 19:15] + node _T_2012 = eq(_T_2010, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2012 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2013 = eq(io.in[0].d.bits.addr_lo, _T_1989) @[RocketPlexMaster.scala 19:15] + node _T_2014 = or(_T_2013, reset) @[RocketPlexMaster.scala 19:15] + node _T_2016 = eq(_T_2014, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2016 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2017 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2018 = and(_T_2017, _T_1968) @[RocketPlexMaster.scala 19:15] + when _T_2018 : @[RocketPlexMaster.scala 19:15] + _T_1979 <= io.in[0].d.bits.opcode @[RocketPlexMaster.scala 19:15] + _T_1981 <= io.in[0].d.bits.param @[RocketPlexMaster.scala 19:15] + _T_1983 <= io.in[0].d.bits.size @[RocketPlexMaster.scala 19:15] + _T_1985 <= io.in[0].d.bits.source @[RocketPlexMaster.scala 19:15] + _T_1987 <= io.in[0].d.bits.sink @[RocketPlexMaster.scala 19:15] + _T_1989 <= io.in[0].d.bits.addr_lo @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + reg _T_2020 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Reg.scala 26:44] + node _T_2021 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_2023 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2024 = dshl(_T_2023, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_2025 = bits(_T_2024, 7, 0) @[package.scala 19:76] + node _T_2026 = not(_T_2025) @[package.scala 19:40] + node _T_2027 = shr(_T_2026, 3) @[Edges.scala 198:59] + node _T_2028 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_2030 = eq(_T_2028, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_2032 = mux(_T_2030, _T_2027, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2034 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2036 = sub(_T_2034, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2037 = asUInt(_T_2036) @[Edges.scala 208:28] + node _T_2038 = tail(_T_2037, 1) @[Edges.scala 208:28] + node _T_2040 = eq(_T_2034, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2042 = eq(_T_2034, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2044 = eq(_T_2032, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2045 = or(_T_2042, _T_2044) @[Edges.scala 210:37] + node _T_2046 = and(_T_2045, _T_2021) @[Edges.scala 211:22] + node _T_2047 = not(_T_2038) @[Edges.scala 212:27] + node _T_2048 = and(_T_2032, _T_2047) @[Edges.scala 212:25] + when _T_2021 : @[Edges.scala 213:17] + node _T_2049 = mux(_T_2040, _T_2032, _T_2038) @[Edges.scala 214:21] + _T_2034 <= _T_2049 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2050 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2052 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2053 = dshl(_T_2052, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2054 = bits(_T_2053, 7, 0) @[package.scala 19:76] + node _T_2055 = not(_T_2054) @[package.scala 19:40] + node _T_2056 = shr(_T_2055, 3) @[Edges.scala 198:59] + node _T_2057 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2059 = mux(_T_2057, _T_2056, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2061 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2063 = sub(_T_2061, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2064 = asUInt(_T_2063) @[Edges.scala 208:28] + node _T_2065 = tail(_T_2064, 1) @[Edges.scala 208:28] + node _T_2067 = eq(_T_2061, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2069 = eq(_T_2061, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2071 = eq(_T_2059, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2072 = or(_T_2069, _T_2071) @[Edges.scala 210:37] + node _T_2073 = and(_T_2072, _T_2050) @[Edges.scala 211:22] + node _T_2074 = not(_T_2065) @[Edges.scala 212:27] + node _T_2075 = and(_T_2059, _T_2074) @[Edges.scala 212:25] + when _T_2050 : @[Edges.scala 213:17] + node _T_2076 = mux(_T_2067, _T_2059, _T_2065) @[Edges.scala 214:21] + _T_2061 <= _T_2076 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2078 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + node _T_2079 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[RocketPlexMaster.scala 19:15] + node _T_2080 = or(_T_2078, _T_2079) @[RocketPlexMaster.scala 19:15] + node _T_2082 = eq(io.in[0].a.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_2083 = or(_T_2080, _T_2082) @[RocketPlexMaster.scala 19:15] + node _T_2085 = eq(io.in[0].d.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_2086 = or(_T_2083, _T_2085) @[RocketPlexMaster.scala 19:15] + node _T_2087 = or(_T_2086, reset) @[RocketPlexMaster.scala 19:15] + node _T_2089 = eq(_T_2087, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2089 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + wire _T_2091 : UInt<6> + _T_2091 is invalid + _T_2091 <= UInt<6>("h00") + node _T_2092 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2092 : @[RocketPlexMaster.scala 19:15] + when _T_2045 : @[RocketPlexMaster.scala 19:15] + node _T_2094 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2091 <= _T_2094 @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2095 = dshr(_T_2020, io.in[0].a.bits.source) @[RocketPlexMaster.scala 19:15] + node _T_2096 = bits(_T_2095, 0, 0) @[RocketPlexMaster.scala 19:15] + node _T_2098 = eq(_T_2096, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + node _T_2099 = or(_T_2098, reset) @[RocketPlexMaster.scala 19:15] + node _T_2101 = eq(_T_2099, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2101 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + wire _T_2103 : UInt<6> + _T_2103 is invalid + _T_2103 <= UInt<6>("h00") + node _T_2104 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2106 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 19:15] + node _T_2107 = and(_T_2104, _T_2106) @[RocketPlexMaster.scala 19:15] + when _T_2107 : @[RocketPlexMaster.scala 19:15] + when _T_2072 : @[RocketPlexMaster.scala 19:15] + node _T_2109 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2103 <= _T_2109 @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2110 = or(_T_2091, _T_2020) @[RocketPlexMaster.scala 19:15] + node _T_2111 = dshr(_T_2110, io.in[0].d.bits.source) @[RocketPlexMaster.scala 19:15] + node _T_2112 = bits(_T_2111, 0, 0) @[RocketPlexMaster.scala 19:15] + node _T_2113 = or(_T_2112, reset) @[RocketPlexMaster.scala 19:15] + node _T_2115 = eq(_T_2113, UInt<1>("h00")) @[RocketPlexMaster.scala 19:15] + when _T_2115 : @[RocketPlexMaster.scala 19:15] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketPlexMaster.scala:19:15)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketPlexMaster.scala 19:15] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + skip @[RocketPlexMaster.scala 19:15] + node _T_2116 = or(_T_2020, _T_2091) @[RocketPlexMaster.scala 19:15] + node _T_2117 = not(_T_2103) @[RocketPlexMaster.scala 19:15] + node _T_2118 = and(_T_2116, _T_2117) @[RocketPlexMaster.scala 19:15] + _T_2020 <= _T_2118 @[RocketPlexMaster.scala 19:15] + + module TLMonitor_39 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, cnt : UInt<1>, done : UInt<1>} + output io : {flip in : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}[1]} io is invalid - io.out <- io.in - io.cnt <= UInt<1>("h00") - io.done <= UInt<1>("h01") + io is invalid + when io.in[0].a.valid : @[RocketPlexMaster.scala 23:70] + node _T_605 = leq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[Bundles.scala 39:24] + node _T_606 = or(_T_605, reset) @[RocketPlexMaster.scala 23:70] + node _T_608 = eq(_T_606, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_608 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel has invalid opcode (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:38 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_610 = xor(UInt<1>("h00"), io.in[0].a.bits.source) @[Parameters.scala 37:23] + node _T_611 = not(_T_610) @[Parameters.scala 37:9] + node _T_613 = or(_T_611, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_614 = not(_T_613) @[Parameters.scala 37:7] + node _T_616 = eq(_T_614, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_619 : UInt<1>[1] @[Parameters.scala 228:27] + _T_619 is invalid @[Parameters.scala 228:27] + _T_619[0] <= _T_616 @[Parameters.scala 228:27] + node _T_624 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_625 = dshl(_T_624, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_626 = bits(_T_625, 7, 0) @[package.scala 19:76] + node _T_627 = not(_T_626) @[package.scala 19:40] + node _T_628 = and(io.in[0].a.bits.address, _T_627) @[Edges.scala 17:16] + node _T_630 = eq(_T_628, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_632 = bits(io.in[0].a.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_633 = dshl(UInt<1>("h01"), _T_632) @[OneHot.scala 49:12] + node _T_634 = bits(_T_633, 2, 0) @[OneHot.scala 49:37] + node _T_636 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_638 = bits(_T_634, 2, 2) @[package.scala 44:26] + node _T_639 = bits(io.in[0].a.bits.address, 2, 2) @[package.scala 45:26] + node _T_641 = eq(_T_639, UInt<1>("h00")) @[package.scala 46:20] + node _T_642 = and(UInt<1>("h01"), _T_641) @[package.scala 49:27] + node _T_643 = and(_T_638, _T_642) @[package.scala 50:38] + node _T_644 = or(_T_636, _T_643) @[package.scala 50:29] + node _T_645 = and(UInt<1>("h01"), _T_639) @[package.scala 49:27] + node _T_646 = and(_T_638, _T_645) @[package.scala 50:38] + node _T_647 = or(_T_636, _T_646) @[package.scala 50:29] + node _T_648 = bits(_T_634, 1, 1) @[package.scala 44:26] + node _T_649 = bits(io.in[0].a.bits.address, 1, 1) @[package.scala 45:26] + node _T_651 = eq(_T_649, UInt<1>("h00")) @[package.scala 46:20] + node _T_652 = and(_T_642, _T_651) @[package.scala 49:27] + node _T_653 = and(_T_648, _T_652) @[package.scala 50:38] + node _T_654 = or(_T_644, _T_653) @[package.scala 50:29] + node _T_655 = and(_T_642, _T_649) @[package.scala 49:27] + node _T_656 = and(_T_648, _T_655) @[package.scala 50:38] + node _T_657 = or(_T_644, _T_656) @[package.scala 50:29] + node _T_658 = and(_T_645, _T_651) @[package.scala 49:27] + node _T_659 = and(_T_648, _T_658) @[package.scala 50:38] + node _T_660 = or(_T_647, _T_659) @[package.scala 50:29] + node _T_661 = and(_T_645, _T_649) @[package.scala 49:27] + node _T_662 = and(_T_648, _T_661) @[package.scala 50:38] + node _T_663 = or(_T_647, _T_662) @[package.scala 50:29] + node _T_664 = bits(_T_634, 0, 0) @[package.scala 44:26] + node _T_665 = bits(io.in[0].a.bits.address, 0, 0) @[package.scala 45:26] + node _T_667 = eq(_T_665, UInt<1>("h00")) @[package.scala 46:20] + node _T_668 = and(_T_652, _T_667) @[package.scala 49:27] + node _T_669 = and(_T_664, _T_668) @[package.scala 50:38] + node _T_670 = or(_T_654, _T_669) @[package.scala 50:29] + node _T_671 = and(_T_652, _T_665) @[package.scala 49:27] + node _T_672 = and(_T_664, _T_671) @[package.scala 50:38] + node _T_673 = or(_T_654, _T_672) @[package.scala 50:29] + node _T_674 = and(_T_655, _T_667) @[package.scala 49:27] + node _T_675 = and(_T_664, _T_674) @[package.scala 50:38] + node _T_676 = or(_T_657, _T_675) @[package.scala 50:29] + node _T_677 = and(_T_655, _T_665) @[package.scala 49:27] + node _T_678 = and(_T_664, _T_677) @[package.scala 50:38] + node _T_679 = or(_T_657, _T_678) @[package.scala 50:29] + node _T_680 = and(_T_658, _T_667) @[package.scala 49:27] + node _T_681 = and(_T_664, _T_680) @[package.scala 50:38] + node _T_682 = or(_T_660, _T_681) @[package.scala 50:29] + node _T_683 = and(_T_658, _T_665) @[package.scala 49:27] + node _T_684 = and(_T_664, _T_683) @[package.scala 50:38] + node _T_685 = or(_T_660, _T_684) @[package.scala 50:29] + node _T_686 = and(_T_661, _T_667) @[package.scala 49:27] + node _T_687 = and(_T_664, _T_686) @[package.scala 50:38] + node _T_688 = or(_T_663, _T_687) @[package.scala 50:29] + node _T_689 = and(_T_661, _T_665) @[package.scala 49:27] + node _T_690 = and(_T_664, _T_689) @[package.scala 50:38] + node _T_691 = or(_T_663, _T_690) @[package.scala 50:29] + node _T_692 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_693 = cat(_T_679, _T_676) @[Cat.scala 30:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 30:58] + node _T_695 = cat(_T_685, _T_682) @[Cat.scala 30:58] + node _T_696 = cat(_T_691, _T_688) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_694) @[Cat.scala 30:58] + node _T_700 = eq(io.in[0].a.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + when _T_700 : @[RocketPlexMaster.scala 23:70] + node _T_703 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_705 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_706 = cvt(_T_705) @[Parameters.scala 117:49] + node _T_708 = and(_T_706, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_709 = asSInt(_T_708) @[Parameters.scala 117:52] + node _T_711 = eq(_T_709, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_713 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_714 = cvt(_T_713) @[Parameters.scala 117:49] + node _T_716 = and(_T_714, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_717 = asSInt(_T_716) @[Parameters.scala 117:52] + node _T_719 = eq(_T_717, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_720 = or(_T_711, _T_719) @[Parameters.scala 133:42] + node _T_721 = and(_T_703, _T_720) @[Parameters.scala 132:56] + node _T_723 = or(UInt<1>("h00"), _T_721) @[Parameters.scala 134:30] + node _T_724 = or(_T_723, reset) @[RocketPlexMaster.scala 23:70] + node _T_726 = eq(_T_724, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_726 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Acquire type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:46 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries Acquire type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_727 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_729 = eq(_T_727, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_729 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:47 assert (source_ok, \"'A' channel Acquire carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_731 = geq(io.in[0].a.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_732 = or(_T_731, reset) @[RocketPlexMaster.scala 23:70] + node _T_734 = eq(_T_732, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_734 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:48 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel Acquire smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_735 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_737 = eq(_T_735, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_737 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:49 assert (is_aligned, \"'A' channel Acquire address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_739 = leq(io.in[0].a.bits.param, UInt<2>("h02")) @[Bundles.scala 70:27] + node _T_740 = or(_T_739, reset) @[RocketPlexMaster.scala 23:70] + node _T_742 = eq(_T_740, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_742 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire carries invalid grow param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:50 assert (TLPermissions.isGrow(bundle.param), \"'A' channel Acquire carries invalid grow param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_743 = not(io.in[0].a.bits.mask) @[RocketPlexMaster.scala 23:70] + node _T_745 = eq(_T_743, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_746 = or(_T_745, reset) @[RocketPlexMaster.scala 23:70] + node _T_748 = eq(_T_746, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_748 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Acquire contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:51 assert (~bundle.mask === UInt(0), \"'A' channel Acquire contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_750 = eq(io.in[0].a.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 23:70] + when _T_750 : @[RocketPlexMaster.scala 23:70] + node _T_753 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_755 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_756 = and(_T_753, _T_755) @[Parameters.scala 63:37] + node _T_757 = or(UInt<1>("h00"), _T_756) @[Parameters.scala 132:31] + node _T_759 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_760 = cvt(_T_759) @[Parameters.scala 117:49] + node _T_762 = and(_T_760, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_763 = asSInt(_T_762) @[Parameters.scala 117:52] + node _T_765 = eq(_T_763, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_766 = and(_T_757, _T_765) @[Parameters.scala 132:56] + node _T_769 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_771 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_772 = and(_T_769, _T_771) @[Parameters.scala 63:37] + node _T_773 = or(UInt<1>("h00"), _T_772) @[Parameters.scala 132:31] + node _T_775 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_776 = cvt(_T_775) @[Parameters.scala 117:49] + node _T_778 = and(_T_776, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_779 = asSInt(_T_778) @[Parameters.scala 117:52] + node _T_781 = eq(_T_779, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_782 = and(_T_773, _T_781) @[Parameters.scala 132:56] + node _T_784 = or(UInt<1>("h00"), _T_766) @[Parameters.scala 134:30] + node _T_785 = or(_T_784, _T_782) @[Parameters.scala 134:30] + node _T_786 = or(_T_785, reset) @[RocketPlexMaster.scala 23:70] + node _T_788 = eq(_T_786, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_788 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Get type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:55 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_789 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_791 = eq(_T_789, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_791 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:56 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_792 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_794 = eq(_T_792, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_794 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:57 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_796 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_797 = or(_T_796, reset) @[RocketPlexMaster.scala 23:70] + node _T_799 = eq(_T_797, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_799 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:58 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_800 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 23:70] + node _T_801 = or(_T_800, reset) @[RocketPlexMaster.scala 23:70] + node _T_803 = eq(_T_801, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_803 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Get contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:59 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_805 = eq(io.in[0].a.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_805 : @[RocketPlexMaster.scala 23:70] + node _T_808 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_810 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_811 = and(_T_808, _T_810) @[Parameters.scala 63:37] + node _T_812 = or(UInt<1>("h00"), _T_811) @[Parameters.scala 132:31] + node _T_814 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_815 = cvt(_T_814) @[Parameters.scala 117:49] + node _T_817 = and(_T_815, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_818 = asSInt(_T_817) @[Parameters.scala 117:52] + node _T_820 = eq(_T_818, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_821 = and(_T_812, _T_820) @[Parameters.scala 132:56] + node _T_824 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_826 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_827 = and(_T_824, _T_826) @[Parameters.scala 63:37] + node _T_828 = or(UInt<1>("h00"), _T_827) @[Parameters.scala 132:31] + node _T_830 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_831 = cvt(_T_830) @[Parameters.scala 117:49] + node _T_833 = and(_T_831, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_834 = asSInt(_T_833) @[Parameters.scala 117:52] + node _T_836 = eq(_T_834, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_837 = and(_T_828, _T_836) @[Parameters.scala 132:56] + node _T_839 = or(UInt<1>("h00"), _T_821) @[Parameters.scala 134:30] + node _T_840 = or(_T_839, _T_837) @[Parameters.scala 134:30] + node _T_841 = or(_T_840, reset) @[RocketPlexMaster.scala 23:70] + node _T_843 = eq(_T_841, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_843 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:63 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_844 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_846 = eq(_T_844, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_846 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:64 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_847 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_849 = eq(_T_847, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_849 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:65 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_851 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_852 = or(_T_851, reset) @[RocketPlexMaster.scala 23:70] + node _T_854 = eq(_T_852, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_854 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:66 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_855 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 23:70] + node _T_856 = or(_T_855, reset) @[RocketPlexMaster.scala 23:70] + node _T_858 = eq(_T_856, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_858 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:67 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_860 = eq(io.in[0].a.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 23:70] + when _T_860 : @[RocketPlexMaster.scala 23:70] + node _T_863 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_865 = leq(io.in[0].a.bits.size, UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_866 = and(_T_863, _T_865) @[Parameters.scala 63:37] + node _T_867 = or(UInt<1>("h00"), _T_866) @[Parameters.scala 132:31] + node _T_869 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_870 = cvt(_T_869) @[Parameters.scala 117:49] + node _T_872 = and(_T_870, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_873 = asSInt(_T_872) @[Parameters.scala 117:52] + node _T_875 = eq(_T_873, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_876 = and(_T_867, _T_875) @[Parameters.scala 132:56] + node _T_879 = leq(UInt<1>("h00"), io.in[0].a.bits.size) @[Parameters.scala 63:32] + node _T_881 = leq(io.in[0].a.bits.size, UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_882 = and(_T_879, _T_881) @[Parameters.scala 63:37] + node _T_883 = or(UInt<1>("h00"), _T_882) @[Parameters.scala 132:31] + node _T_885 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_886 = cvt(_T_885) @[Parameters.scala 117:49] + node _T_888 = and(_T_886, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_889 = asSInt(_T_888) @[Parameters.scala 117:52] + node _T_891 = eq(_T_889, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_892 = and(_T_883, _T_891) @[Parameters.scala 132:56] + node _T_894 = or(UInt<1>("h00"), _T_876) @[Parameters.scala 134:30] + node _T_895 = or(_T_894, _T_892) @[Parameters.scala 134:30] + node _T_896 = or(_T_895, reset) @[RocketPlexMaster.scala 23:70] + node _T_898 = eq(_T_896, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_898 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:71 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_899 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_901 = eq(_T_899, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_901 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:72 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_902 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_904 = eq(_T_902, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_904 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:73 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_906 = eq(io.in[0].a.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_907 = or(_T_906, reset) @[RocketPlexMaster.scala 23:70] + node _T_909 = eq(_T_907, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_909 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:74 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_910 = not(_T_698) @[RocketPlexMaster.scala 23:70] + node _T_911 = and(io.in[0].a.bits.mask, _T_910) @[RocketPlexMaster.scala 23:70] + node _T_913 = eq(_T_911, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_914 = or(_T_913, reset) @[RocketPlexMaster.scala 23:70] + node _T_916 = eq(_T_914, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_916 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:75 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_918 = eq(io.in[0].a.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + when _T_918 : @[RocketPlexMaster.scala 23:70] + node _T_921 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_923 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_924 = cvt(_T_923) @[Parameters.scala 117:49] + node _T_926 = and(_T_924, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_927 = asSInt(_T_926) @[Parameters.scala 117:52] + node _T_929 = eq(_T_927, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_931 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_932 = cvt(_T_931) @[Parameters.scala 117:49] + node _T_934 = and(_T_932, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_935 = asSInt(_T_934) @[Parameters.scala 117:52] + node _T_937 = eq(_T_935, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_938 = or(_T_929, _T_937) @[Parameters.scala 133:42] + node _T_939 = and(_T_921, _T_938) @[Parameters.scala 132:56] + node _T_941 = or(UInt<1>("h00"), _T_939) @[Parameters.scala 134:30] + node _T_942 = or(_T_941, reset) @[RocketPlexMaster.scala 23:70] + node _T_944 = eq(_T_942, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_944 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:79 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_945 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_947 = eq(_T_945, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_947 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:80 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_948 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_950 = eq(_T_948, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_950 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:81 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_952 = leq(io.in[0].a.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_953 = or(_T_952, reset) @[RocketPlexMaster.scala 23:70] + node _T_955 = eq(_T_953, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_955 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:82 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_956 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 23:70] + node _T_957 = or(_T_956, reset) @[RocketPlexMaster.scala 23:70] + node _T_959 = eq(_T_957, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_959 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:83 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_961 = eq(io.in[0].a.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + when _T_961 : @[RocketPlexMaster.scala 23:70] + node _T_964 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_966 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_967 = cvt(_T_966) @[Parameters.scala 117:49] + node _T_969 = and(_T_967, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_970 = asSInt(_T_969) @[Parameters.scala 117:52] + node _T_972 = eq(_T_970, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_974 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_975 = cvt(_T_974) @[Parameters.scala 117:49] + node _T_977 = and(_T_975, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_978 = asSInt(_T_977) @[Parameters.scala 117:52] + node _T_980 = eq(_T_978, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_981 = or(_T_972, _T_980) @[Parameters.scala 133:42] + node _T_982 = and(_T_964, _T_981) @[Parameters.scala 132:56] + node _T_984 = or(UInt<1>("h00"), _T_982) @[Parameters.scala 134:30] + node _T_985 = or(_T_984, reset) @[RocketPlexMaster.scala 23:70] + node _T_987 = eq(_T_985, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_987 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:87 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_988 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_990 = eq(_T_988, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_990 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:88 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_991 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_993 = eq(_T_991, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_993 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:89 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_995 = leq(io.in[0].a.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_996 = or(_T_995, reset) @[RocketPlexMaster.scala 23:70] + node _T_998 = eq(_T_996, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_998 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:90 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_999 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 23:70] + node _T_1000 = or(_T_999, reset) @[RocketPlexMaster.scala 23:70] + node _T_1002 = eq(_T_1000, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1002 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:91 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1004 = eq(io.in[0].a.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 23:70] + when _T_1004 : @[RocketPlexMaster.scala 23:70] + node _T_1007 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1009 = xor(io.in[0].a.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1010 = cvt(_T_1009) @[Parameters.scala 117:49] + node _T_1012 = and(_T_1010, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1013 = asSInt(_T_1012) @[Parameters.scala 117:52] + node _T_1015 = eq(_T_1013, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1017 = xor(io.in[0].a.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1018 = cvt(_T_1017) @[Parameters.scala 117:49] + node _T_1020 = and(_T_1018, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1021 = asSInt(_T_1020) @[Parameters.scala 117:52] + node _T_1023 = eq(_T_1021, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1024 = or(_T_1015, _T_1023) @[Parameters.scala 133:42] + node _T_1025 = and(_T_1007, _T_1024) @[Parameters.scala 132:56] + node _T_1027 = or(UInt<1>("h00"), _T_1025) @[Parameters.scala 134:30] + node _T_1028 = or(_T_1027, reset) @[RocketPlexMaster.scala 23:70] + node _T_1030 = eq(_T_1028, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1030 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:95 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1031 = or(_T_619[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1033 = eq(_T_1031, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1033 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:96 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1034 = or(_T_630, reset) @[RocketPlexMaster.scala 23:70] + node _T_1036 = eq(_T_1034, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1036 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:97 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1037 = eq(io.in[0].a.bits.mask, _T_698) @[RocketPlexMaster.scala 23:70] + node _T_1038 = or(_T_1037, reset) @[RocketPlexMaster.scala 23:70] + node _T_1040 = eq(_T_1038, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1040 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:98 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + when io.in[0].b.valid : @[RocketPlexMaster.scala 23:70] + node _T_1042 = leq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[Bundles.scala 40:24] + node _T_1043 = or(_T_1042, reset) @[RocketPlexMaster.scala 23:70] + node _T_1045 = eq(_T_1043, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1045 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel has invalid opcode (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:103 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1047 = xor(io.in[0].b.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1048 = cvt(_T_1047) @[Parameters.scala 117:49] + node _T_1050 = and(_T_1048, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1051 = asSInt(_T_1050) @[Parameters.scala 117:52] + node _T_1053 = eq(_T_1051, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1055 = xor(io.in[0].b.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1056 = cvt(_T_1055) @[Parameters.scala 117:49] + node _T_1058 = and(_T_1056, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1059 = asSInt(_T_1058) @[Parameters.scala 117:52] + node _T_1061 = eq(_T_1059, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1064 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1064 is invalid @[Parameters.scala 110:36] + _T_1064[0] <= _T_1053 @[Parameters.scala 110:36] + _T_1064[1] <= _T_1061 @[Parameters.scala 110:36] + node _T_1069 = or(_T_1064[0], _T_1064[1]) @[Parameters.scala 119:64] + node _T_1071 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1072 = dshl(_T_1071, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1073 = bits(_T_1072, 7, 0) @[package.scala 19:76] + node _T_1074 = not(_T_1073) @[package.scala 19:40] + node _T_1075 = and(io.in[0].b.bits.address, _T_1074) @[Edges.scala 17:16] + node _T_1077 = eq(_T_1075, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1079 = bits(io.in[0].b.bits.size, 1, 0) @[OneHot.scala 49:17] + node _T_1080 = dshl(UInt<1>("h01"), _T_1079) @[OneHot.scala 49:12] + node _T_1081 = bits(_T_1080, 2, 0) @[OneHot.scala 49:37] + node _T_1083 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[package.scala 41:21] + node _T_1085 = bits(_T_1081, 2, 2) @[package.scala 44:26] + node _T_1086 = bits(io.in[0].b.bits.address, 2, 2) @[package.scala 45:26] + node _T_1088 = eq(_T_1086, UInt<1>("h00")) @[package.scala 46:20] + node _T_1089 = and(UInt<1>("h01"), _T_1088) @[package.scala 49:27] + node _T_1090 = and(_T_1085, _T_1089) @[package.scala 50:38] + node _T_1091 = or(_T_1083, _T_1090) @[package.scala 50:29] + node _T_1092 = and(UInt<1>("h01"), _T_1086) @[package.scala 49:27] + node _T_1093 = and(_T_1085, _T_1092) @[package.scala 50:38] + node _T_1094 = or(_T_1083, _T_1093) @[package.scala 50:29] + node _T_1095 = bits(_T_1081, 1, 1) @[package.scala 44:26] + node _T_1096 = bits(io.in[0].b.bits.address, 1, 1) @[package.scala 45:26] + node _T_1098 = eq(_T_1096, UInt<1>("h00")) @[package.scala 46:20] + node _T_1099 = and(_T_1089, _T_1098) @[package.scala 49:27] + node _T_1100 = and(_T_1095, _T_1099) @[package.scala 50:38] + node _T_1101 = or(_T_1091, _T_1100) @[package.scala 50:29] + node _T_1102 = and(_T_1089, _T_1096) @[package.scala 49:27] + node _T_1103 = and(_T_1095, _T_1102) @[package.scala 50:38] + node _T_1104 = or(_T_1091, _T_1103) @[package.scala 50:29] + node _T_1105 = and(_T_1092, _T_1098) @[package.scala 49:27] + node _T_1106 = and(_T_1095, _T_1105) @[package.scala 50:38] + node _T_1107 = or(_T_1094, _T_1106) @[package.scala 50:29] + node _T_1108 = and(_T_1092, _T_1096) @[package.scala 49:27] + node _T_1109 = and(_T_1095, _T_1108) @[package.scala 50:38] + node _T_1110 = or(_T_1094, _T_1109) @[package.scala 50:29] + node _T_1111 = bits(_T_1081, 0, 0) @[package.scala 44:26] + node _T_1112 = bits(io.in[0].b.bits.address, 0, 0) @[package.scala 45:26] + node _T_1114 = eq(_T_1112, UInt<1>("h00")) @[package.scala 46:20] + node _T_1115 = and(_T_1099, _T_1114) @[package.scala 49:27] + node _T_1116 = and(_T_1111, _T_1115) @[package.scala 50:38] + node _T_1117 = or(_T_1101, _T_1116) @[package.scala 50:29] + node _T_1118 = and(_T_1099, _T_1112) @[package.scala 49:27] + node _T_1119 = and(_T_1111, _T_1118) @[package.scala 50:38] + node _T_1120 = or(_T_1101, _T_1119) @[package.scala 50:29] + node _T_1121 = and(_T_1102, _T_1114) @[package.scala 49:27] + node _T_1122 = and(_T_1111, _T_1121) @[package.scala 50:38] + node _T_1123 = or(_T_1104, _T_1122) @[package.scala 50:29] + node _T_1124 = and(_T_1102, _T_1112) @[package.scala 49:27] + node _T_1125 = and(_T_1111, _T_1124) @[package.scala 50:38] + node _T_1126 = or(_T_1104, _T_1125) @[package.scala 50:29] + node _T_1127 = and(_T_1105, _T_1114) @[package.scala 49:27] + node _T_1128 = and(_T_1111, _T_1127) @[package.scala 50:38] + node _T_1129 = or(_T_1107, _T_1128) @[package.scala 50:29] + node _T_1130 = and(_T_1105, _T_1112) @[package.scala 49:27] + node _T_1131 = and(_T_1111, _T_1130) @[package.scala 50:38] + node _T_1132 = or(_T_1107, _T_1131) @[package.scala 50:29] + node _T_1133 = and(_T_1108, _T_1114) @[package.scala 49:27] + node _T_1134 = and(_T_1111, _T_1133) @[package.scala 50:38] + node _T_1135 = or(_T_1110, _T_1134) @[package.scala 50:29] + node _T_1136 = and(_T_1108, _T_1112) @[package.scala 49:27] + node _T_1137 = and(_T_1111, _T_1136) @[package.scala 50:38] + node _T_1138 = or(_T_1110, _T_1137) @[package.scala 50:29] + node _T_1139 = cat(_T_1120, _T_1117) @[Cat.scala 30:58] + node _T_1140 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1132, _T_1129) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1138, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1142) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1141) @[Cat.scala 30:58] + node _T_1147 = eq(io.in[0].b.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + when _T_1147 : @[RocketPlexMaster.scala 23:70] + node _T_1149 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1151 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Probe type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:111 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1152 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1154 = eq(_T_1152, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1154 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:112 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1156 = geq(io.in[0].b.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1157 = or(_T_1156, reset) @[RocketPlexMaster.scala 23:70] + node _T_1159 = eq(_T_1157, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1159 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:113 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'B' channel Probe smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1160 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1162 = eq(_T_1160, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1162 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:114 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1164 = leq(io.in[0].b.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1165 = or(_T_1164, reset) @[RocketPlexMaster.scala 23:70] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1167 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:115 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1168 = not(io.in[0].b.bits.mask) @[RocketPlexMaster.scala 23:70] + node _T_1170 = eq(_T_1168, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1171 = or(_T_1170, reset) @[RocketPlexMaster.scala 23:70] + node _T_1173 = eq(_T_1171, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1173 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:116 assert (~bundle.mask === UInt(0), \"'B' channel Probe contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1175 = eq(io.in[0].b.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 23:70] + when _T_1175 : @[RocketPlexMaster.scala 23:70] + node _T_1177 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1179 = eq(_T_1177, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1179 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Get type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:120 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1180 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1182 = eq(_T_1180, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1182 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:121 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1183 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1185 = eq(_T_1183, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1185 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:122 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1187 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1188 = or(_T_1187, reset) @[RocketPlexMaster.scala 23:70] + node _T_1190 = eq(_T_1188, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1190 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:123 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1191 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1192 = or(_T_1191, reset) @[RocketPlexMaster.scala 23:70] + node _T_1194 = eq(_T_1192, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1194 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Get contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:124 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1196 = eq(io.in[0].b.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1196 : @[RocketPlexMaster.scala 23:70] + node _T_1198 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1200 = eq(_T_1198, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1200 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:128 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1201 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1203 = eq(_T_1201, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1203 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:129 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1204 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1206 = eq(_T_1204, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1206 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:130 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1208 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1209 = or(_T_1208, reset) @[RocketPlexMaster.scala 23:70] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1211 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:131 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1212 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1213 = or(_T_1212, reset) @[RocketPlexMaster.scala 23:70] + node _T_1215 = eq(_T_1213, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1215 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:132 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1217 = eq(io.in[0].b.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 23:70] + when _T_1217 : @[RocketPlexMaster.scala 23:70] + node _T_1219 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1221 = eq(_T_1219, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1221 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:136 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1222 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1224 = eq(_T_1222, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1224 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:137 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1225 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1227 = eq(_T_1225, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1227 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:138 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1229 = eq(io.in[0].b.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1230 = or(_T_1229, reset) @[RocketPlexMaster.scala 23:70] + node _T_1232 = eq(_T_1230, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1232 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:139 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1233 = not(_T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1234 = and(io.in[0].b.bits.mask, _T_1233) @[RocketPlexMaster.scala 23:70] + node _T_1236 = eq(_T_1234, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1237 = or(_T_1236, reset) @[RocketPlexMaster.scala 23:70] + node _T_1239 = eq(_T_1237, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1239 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:140 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1241 = eq(io.in[0].b.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + when _T_1241 : @[RocketPlexMaster.scala 23:70] + node _T_1243 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1245 = eq(_T_1243, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1245 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:144 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1246 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1248 = eq(_T_1246, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1248 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:145 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1249 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1251 = eq(_T_1249, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1251 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1253 = leq(io.in[0].b.bits.param, UInt<3>("h04")) @[Bundles.scala 95:33] + node _T_1254 = or(_T_1253, reset) @[RocketPlexMaster.scala 23:70] + node _T_1256 = eq(_T_1254, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1256 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:147 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1257 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1258 = or(_T_1257, reset) @[RocketPlexMaster.scala 23:70] + node _T_1260 = eq(_T_1258, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1260 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1262 = eq(io.in[0].b.bits.opcode, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + when _T_1262 : @[RocketPlexMaster.scala 23:70] + node _T_1264 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1266 = eq(_T_1264, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1266 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:152 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1267 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1269 = eq(_T_1267, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1269 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:153 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1270 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1272 = eq(_T_1270, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1272 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:154 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1274 = leq(io.in[0].b.bits.param, UInt<3>("h03")) @[Bundles.scala 102:30] + node _T_1275 = or(_T_1274, reset) @[RocketPlexMaster.scala 23:70] + node _T_1277 = eq(_T_1275, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1277 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:155 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1278 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1279 = or(_T_1278, reset) @[RocketPlexMaster.scala 23:70] + node _T_1281 = eq(_T_1279, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1281 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:156 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1283 = eq(io.in[0].b.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 23:70] + when _T_1283 : @[RocketPlexMaster.scala 23:70] + node _T_1285 = or(UInt<1>("h00"), reset) @[RocketPlexMaster.scala 23:70] + node _T_1287 = eq(_T_1285, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1287 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:160 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1288 = or(_T_1069, reset) @[RocketPlexMaster.scala 23:70] + node _T_1290 = eq(_T_1288, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1290 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:161 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1291 = or(_T_1077, reset) @[RocketPlexMaster.scala 23:70] + node _T_1293 = eq(_T_1291, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1293 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:162 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1294 = eq(io.in[0].b.bits.mask, _T_1145) @[RocketPlexMaster.scala 23:70] + node _T_1295 = or(_T_1294, reset) @[RocketPlexMaster.scala 23:70] + node _T_1297 = eq(_T_1295, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1297 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:163 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + when io.in[0].c.valid : @[RocketPlexMaster.scala 23:70] + node _T_1299 = leq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[Bundles.scala 41:24] + node _T_1300 = or(_T_1299, reset) @[RocketPlexMaster.scala 23:70] + node _T_1302 = eq(_T_1300, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1302 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel has invalid opcode (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:168 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1304 = xor(UInt<1>("h00"), io.in[0].c.bits.source) @[Parameters.scala 37:23] + node _T_1305 = not(_T_1304) @[Parameters.scala 37:9] + node _T_1307 = or(_T_1305, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1308 = not(_T_1307) @[Parameters.scala 37:7] + node _T_1310 = eq(_T_1308, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1313 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1313 is invalid @[Parameters.scala 228:27] + _T_1313[0] <= _T_1310 @[Parameters.scala 228:27] + node _T_1318 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1319 = dshl(_T_1318, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1320 = bits(_T_1319, 7, 0) @[package.scala 19:76] + node _T_1321 = not(_T_1320) @[package.scala 19:40] + node _T_1322 = and(io.in[0].c.bits.address, _T_1321) @[Edges.scala 17:16] + node _T_1324 = eq(_T_1322, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1326 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1327 = cvt(_T_1326) @[Parameters.scala 117:49] + node _T_1329 = and(_T_1327, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1330 = asSInt(_T_1329) @[Parameters.scala 117:52] + node _T_1332 = eq(_T_1330, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1334 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1335 = cvt(_T_1334) @[Parameters.scala 117:49] + node _T_1337 = and(_T_1335, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1338 = asSInt(_T_1337) @[Parameters.scala 117:52] + node _T_1340 = eq(_T_1338, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_1343 : UInt<1>[2] @[Parameters.scala 110:36] + _T_1343 is invalid @[Parameters.scala 110:36] + _T_1343[0] <= _T_1332 @[Parameters.scala 110:36] + _T_1343[1] <= _T_1340 @[Parameters.scala 110:36] + node _T_1348 = or(_T_1343[0], _T_1343[1]) @[Parameters.scala 119:64] + node _T_1350 = eq(io.in[0].c.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 23:70] + when _T_1350 : @[RocketPlexMaster.scala 23:70] + node _T_1351 = or(_T_1348, reset) @[RocketPlexMaster.scala 23:70] + node _T_1353 = eq(_T_1351, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1353 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:175 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1354 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1356 = eq(_T_1354, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1356 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:176 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1358 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1359 = or(_T_1358, reset) @[RocketPlexMaster.scala 23:70] + node _T_1361 = eq(_T_1359, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1361 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:177 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1362 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1364 = eq(_T_1362, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1364 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:178 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1366 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1367 = or(_T_1366, reset) @[RocketPlexMaster.scala 23:70] + node _T_1369 = eq(_T_1367, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1369 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:179 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1371 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1372 = or(_T_1371, reset) @[RocketPlexMaster.scala 23:70] + node _T_1374 = eq(_T_1372, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1374 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Probe carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:180 assert (!bundle.error, \"'C' channel Probe carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1376 = eq(io.in[0].c.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 23:70] + when _T_1376 : @[RocketPlexMaster.scala 23:70] + node _T_1377 = or(_T_1348, reset) @[RocketPlexMaster.scala 23:70] + node _T_1379 = eq(_T_1377, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1379 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:184 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1380 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1382 = eq(_T_1380, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1382 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:185 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1384 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1385 = or(_T_1384, reset) @[RocketPlexMaster.scala 23:70] + node _T_1387 = eq(_T_1385, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1387 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:186 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1388 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1390 = eq(_T_1388, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1390 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:187 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1392 = leq(io.in[0].c.bits.param, UInt<3>("h05")) @[Bundles.scala 82:29] + node _T_1393 = or(_T_1392, reset) @[RocketPlexMaster.scala 23:70] + node _T_1395 = eq(_T_1393, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1395 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:188 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1397 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1398 = or(_T_1397, reset) @[RocketPlexMaster.scala 23:70] + node _T_1400 = eq(_T_1398, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1400 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ProbeData carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:189 assert (!bundle.error, \"'C' channel ProbeData carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1402 = eq(io.in[0].c.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + when _T_1402 : @[RocketPlexMaster.scala 23:70] + node _T_1405 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1407 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1408 = cvt(_T_1407) @[Parameters.scala 117:49] + node _T_1410 = and(_T_1408, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1411 = asSInt(_T_1410) @[Parameters.scala 117:52] + node _T_1413 = eq(_T_1411, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1415 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1416 = cvt(_T_1415) @[Parameters.scala 117:49] + node _T_1418 = and(_T_1416, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1419 = asSInt(_T_1418) @[Parameters.scala 117:52] + node _T_1421 = eq(_T_1419, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1422 = or(_T_1413, _T_1421) @[Parameters.scala 133:42] + node _T_1423 = and(_T_1405, _T_1422) @[Parameters.scala 132:56] + node _T_1425 = or(UInt<1>("h00"), _T_1423) @[Parameters.scala 134:30] + node _T_1426 = or(_T_1425, reset) @[RocketPlexMaster.scala 23:70] + node _T_1428 = eq(_T_1426, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1428 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:193 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1429 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1431 = eq(_T_1429, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1431 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:194 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1433 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1434 = or(_T_1433, reset) @[RocketPlexMaster.scala 23:70] + node _T_1436 = eq(_T_1434, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1436 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:195 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1437 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1439 = eq(_T_1437, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1439 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:196 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1441 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1442 = or(_T_1441, reset) @[RocketPlexMaster.scala 23:70] + node _T_1444 = eq(_T_1442, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1444 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries invalid shrink param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:197 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1446 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1447 = or(_T_1446, reset) @[RocketPlexMaster.scala 23:70] + node _T_1449 = eq(_T_1447, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1449 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel Release carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:198 assert (!bundle.error, \"'C' channel Release carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1451 = eq(io.in[0].c.bits.opcode, UInt<3>("h07")) @[RocketPlexMaster.scala 23:70] + when _T_1451 : @[RocketPlexMaster.scala 23:70] + node _T_1454 = or(UInt<1>("h00"), UInt<1>("h00")) @[Parameters.scala 132:31] + node _T_1456 = xor(io.in[0].c.bits.address, UInt<32>("h080000000")) @[Parameters.scala 117:31] + node _T_1457 = cvt(_T_1456) @[Parameters.scala 117:49] + node _T_1459 = and(_T_1457, asSInt(UInt<29>("h010000000"))) @[Parameters.scala 117:52] + node _T_1460 = asSInt(_T_1459) @[Parameters.scala 117:52] + node _T_1462 = eq(_T_1460, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1464 = xor(io.in[0].c.bits.address, UInt<28>("h0a000000")) @[Parameters.scala 117:31] + node _T_1465 = cvt(_T_1464) @[Parameters.scala 117:49] + node _T_1467 = and(_T_1465, asSInt(UInt<26>("h02000000"))) @[Parameters.scala 117:52] + node _T_1468 = asSInt(_T_1467) @[Parameters.scala 117:52] + node _T_1470 = eq(_T_1468, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_1471 = or(_T_1462, _T_1470) @[Parameters.scala 133:42] + node _T_1472 = and(_T_1454, _T_1471) @[Parameters.scala 132:56] + node _T_1474 = or(UInt<1>("h00"), _T_1472) @[Parameters.scala 134:30] + node _T_1475 = or(_T_1474, reset) @[RocketPlexMaster.scala 23:70] + node _T_1477 = eq(_T_1475, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1477 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:202 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1478 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1480 = eq(_T_1478, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1480 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:203 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1482 = geq(io.in[0].c.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1483 = or(_T_1482, reset) @[RocketPlexMaster.scala 23:70] + node _T_1485 = eq(_T_1483, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1485 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:204 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1486 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1488 = eq(_T_1486, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1488 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:205 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1490 = leq(io.in[0].c.bits.param, UInt<3>("h02")) @[Bundles.scala 76:29] + node _T_1491 = or(_T_1490, reset) @[RocketPlexMaster.scala 23:70] + node _T_1493 = eq(_T_1491, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1493 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:206 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1495 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1496 = or(_T_1495, reset) @[RocketPlexMaster.scala 23:70] + node _T_1498 = eq(_T_1496, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1498 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel ReleaseData carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:207 assert (!bundle.error, \"'C' channel ReleaseData carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1500 = eq(io.in[0].c.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1500 : @[RocketPlexMaster.scala 23:70] + node _T_1501 = or(_T_1348, reset) @[RocketPlexMaster.scala 23:70] + node _T_1503 = eq(_T_1501, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1503 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:211 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1504 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1506 = eq(_T_1504, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1506 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:212 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1507 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1509 = eq(_T_1507, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1509 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:213 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1511 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1512 = or(_T_1511, reset) @[RocketPlexMaster.scala 23:70] + node _T_1514 = eq(_T_1512, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1514 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:214 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1516 = eq(io.in[0].c.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 23:70] + when _T_1516 : @[RocketPlexMaster.scala 23:70] + node _T_1517 = or(_T_1348, reset) @[RocketPlexMaster.scala 23:70] + node _T_1519 = eq(_T_1517, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1519 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:218 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1520 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1522 = eq(_T_1520, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1522 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:219 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1523 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1525 = eq(_T_1523, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1525 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1527 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1528 = or(_T_1527, reset) @[RocketPlexMaster.scala 23:70] + node _T_1530 = eq(_T_1528, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1530 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:221 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1532 = eq(io.in[0].c.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + when _T_1532 : @[RocketPlexMaster.scala 23:70] + node _T_1533 = or(_T_1348, reset) @[RocketPlexMaster.scala 23:70] + node _T_1535 = eq(_T_1533, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1535 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:225 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1536 = or(_T_1313[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1538 = eq(_T_1536, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1538 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:226 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1539 = or(_T_1324, reset) @[RocketPlexMaster.scala 23:70] + node _T_1541 = eq(_T_1539, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1541 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:227 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1543 = eq(io.in[0].c.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1544 = or(_T_1543, reset) @[RocketPlexMaster.scala 23:70] + node _T_1546 = eq(_T_1544, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1546 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:228 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1548 = eq(io.in[0].c.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1549 = or(_T_1548, reset) @[RocketPlexMaster.scala 23:70] + node _T_1551 = eq(_T_1549, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1551 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel HintAck carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:229 assert (!bundle.error, \"'C' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + when io.in[0].d.valid : @[RocketPlexMaster.scala 23:70] + node _T_1553 = leq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[Bundles.scala 42:24] + node _T_1554 = or(_T_1553, reset) @[RocketPlexMaster.scala 23:70] + node _T_1556 = eq(_T_1554, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1556 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel has invalid opcode (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:234 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1558 = xor(UInt<1>("h00"), io.in[0].d.bits.source) @[Parameters.scala 37:23] + node _T_1559 = not(_T_1558) @[Parameters.scala 37:9] + node _T_1561 = or(_T_1559, UInt<5>("h01f")) @[Parameters.scala 37:28] + node _T_1562 = not(_T_1561) @[Parameters.scala 37:7] + node _T_1564 = eq(_T_1562, UInt<1>("h00")) @[Parameters.scala 37:49] + wire _T_1567 : UInt<1>[1] @[Parameters.scala 228:27] + _T_1567 is invalid @[Parameters.scala 228:27] + _T_1567[0] <= _T_1564 @[Parameters.scala 228:27] + node _T_1572 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1573 = dshl(_T_1572, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1574 = bits(_T_1573, 7, 0) @[package.scala 19:76] + node _T_1575 = not(_T_1574) @[package.scala 19:40] + node _T_1576 = and(io.in[0].d.bits.addr_lo, _T_1575) @[Edges.scala 17:16] + node _T_1578 = eq(_T_1576, UInt<1>("h00")) @[Edges.scala 17:24] + node _T_1580 = lt(io.in[0].d.bits.sink, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + node _T_1582 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + when _T_1582 : @[RocketPlexMaster.scala 23:70] + node _T_1583 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1585 = eq(_T_1583, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1585 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:241 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1586 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1588 = eq(_T_1586, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1588 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:242 assert (is_aligned, \"'D' channel ReleaseAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1589 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1591 = eq(_T_1589, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1591 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:243 assert (sink_ok, \"'D' channel ReleaseAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1593 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1594 = or(_T_1593, reset) @[RocketPlexMaster.scala 23:70] + node _T_1596 = eq(_T_1594, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1596 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:244 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1598 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1599 = or(_T_1598, reset) @[RocketPlexMaster.scala 23:70] + node _T_1601 = eq(_T_1599, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1601 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:245 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1603 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1604 = or(_T_1603, reset) @[RocketPlexMaster.scala 23:70] + node _T_1606 = eq(_T_1604, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1606 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel ReleaseAck carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:246 assert (!bundle.error, \"'D' channel ReleaseAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1608 = eq(io.in[0].d.bits.opcode, UInt<3>("h04")) @[RocketPlexMaster.scala 23:70] + when _T_1608 : @[RocketPlexMaster.scala 23:70] + node _T_1609 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1611 = eq(_T_1609, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1611 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:250 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1612 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1614 = eq(_T_1612, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1614 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:251 assert (is_aligned, \"'D' channel Grant address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1615 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1617 = eq(_T_1615, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1617 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:252 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1619 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1620 = or(_T_1619, reset) @[RocketPlexMaster.scala 23:70] + node _T_1622 = eq(_T_1620, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1622 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:253 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1624 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1625 = or(_T_1624, reset) @[RocketPlexMaster.scala 23:70] + node _T_1627 = eq(_T_1625, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1627 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:254 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1629 = eq(io.in[0].d.bits.opcode, UInt<3>("h05")) @[RocketPlexMaster.scala 23:70] + when _T_1629 : @[RocketPlexMaster.scala 23:70] + node _T_1630 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1632 = eq(_T_1630, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1632 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:258 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1633 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1635 = eq(_T_1633, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1635 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:259 assert (is_aligned, \"'D' channel GrantData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1636 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1638 = eq(_T_1636, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1638 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:260 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1640 = geq(io.in[0].d.bits.size, UInt<2>("h03")) @[RocketPlexMaster.scala 23:70] + node _T_1641 = or(_T_1640, reset) @[RocketPlexMaster.scala 23:70] + node _T_1643 = eq(_T_1641, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1643 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:261 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1645 = leq(io.in[0].d.bits.param, UInt<2>("h02")) @[Bundles.scala 64:26] + node _T_1646 = or(_T_1645, reset) @[RocketPlexMaster.scala 23:70] + node _T_1648 = eq(_T_1646, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1648 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:262 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1650 = eq(io.in[0].d.bits.opcode, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1650 : @[RocketPlexMaster.scala 23:70] + node _T_1651 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1653 = eq(_T_1651, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1653 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:266 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1654 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1656 = eq(_T_1654, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1656 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:267 assert (is_aligned, \"'D' channel AccessAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1657 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1659 = eq(_T_1657, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1659 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:268 assert (sink_ok, \"'D' channel AccessAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1661 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1662 = or(_T_1661, reset) @[RocketPlexMaster.scala 23:70] + node _T_1664 = eq(_T_1662, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1664 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:270 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1666 = eq(io.in[0].d.bits.opcode, UInt<1>("h01")) @[RocketPlexMaster.scala 23:70] + when _T_1666 : @[RocketPlexMaster.scala 23:70] + node _T_1667 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1669 = eq(_T_1667, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1669 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:274 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1670 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1672 = eq(_T_1670, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1672 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:275 assert (is_aligned, \"'D' channel AccessAckData address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1673 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1675 = eq(_T_1673, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1675 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:276 assert (sink_ok, \"'D' channel AccessAckData carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1677 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1678 = or(_T_1677, reset) @[RocketPlexMaster.scala 23:70] + node _T_1680 = eq(_T_1678, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1680 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1682 = eq(io.in[0].d.bits.opcode, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + when _T_1682 : @[RocketPlexMaster.scala 23:70] + node _T_1683 = or(_T_1567[0], reset) @[RocketPlexMaster.scala 23:70] + node _T_1685 = eq(_T_1683, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1685 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:282 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1686 = or(_T_1578, reset) @[RocketPlexMaster.scala 23:70] + node _T_1688 = eq(_T_1686, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1688 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck address not aligned to size (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:283 assert (is_aligned, \"'D' channel HintAck address not aligned to size\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1689 = or(_T_1580, reset) @[RocketPlexMaster.scala 23:70] + node _T_1691 = eq(_T_1689, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1691 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:284 assert (sink_ok, \"'D' channel HintAck carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1693 = eq(io.in[0].d.bits.param, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1694 = or(_T_1693, reset) @[RocketPlexMaster.scala 23:70] + node _T_1696 = eq(_T_1694, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1696 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:286 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1698 = eq(io.in[0].d.bits.error, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1699 = or(_T_1698, reset) @[RocketPlexMaster.scala 23:70] + node _T_1701 = eq(_T_1699, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1701 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel HintAck carries an error (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:287 assert (!bundle.error, \"'D' channel HintAck carries an error\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + when io.in[0].e.valid : @[RocketPlexMaster.scala 23:70] + node _T_1703 = lt(io.in[0].e.bits.sink, UInt<2>("h02")) @[RocketPlexMaster.scala 23:70] + node _T_1704 = or(_T_1703, reset) @[RocketPlexMaster.scala 23:70] + node _T_1706 = eq(_T_1704, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1706 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'E' channels carries invalid sink ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:293 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1707 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1709 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1710 = dshl(_T_1709, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1711 = bits(_T_1710, 7, 0) @[package.scala 19:76] + node _T_1712 = not(_T_1711) @[package.scala 19:40] + node _T_1713 = shr(_T_1712, 3) @[Edges.scala 198:59] + node _T_1714 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1716 = eq(_T_1714, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1718 = mux(_T_1716, _T_1713, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1720 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1722 = sub(_T_1720, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1723 = asUInt(_T_1722) @[Edges.scala 208:28] + node _T_1724 = tail(_T_1723, 1) @[Edges.scala 208:28] + node _T_1726 = eq(_T_1720, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1728 = eq(_T_1720, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1730 = eq(_T_1718, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1731 = or(_T_1728, _T_1730) @[Edges.scala 210:37] + node _T_1732 = and(_T_1731, _T_1707) @[Edges.scala 211:22] + node _T_1733 = not(_T_1724) @[Edges.scala 212:27] + node _T_1734 = and(_T_1718, _T_1733) @[Edges.scala 212:25] + when _T_1707 : @[Edges.scala 213:17] + node _T_1735 = mux(_T_1726, _T_1718, _T_1724) @[Edges.scala 214:21] + _T_1720 <= _T_1735 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1737 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1739 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1741 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1743 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1745 : UInt, clock @[RocketPlexMaster.scala 23:70] + node _T_1747 = eq(_T_1726, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1748 = and(io.in[0].a.valid, _T_1747) @[RocketPlexMaster.scala 23:70] + when _T_1748 : @[RocketPlexMaster.scala 23:70] + node _T_1749 = eq(io.in[0].a.bits.opcode, _T_1737) @[RocketPlexMaster.scala 23:70] + node _T_1750 = or(_T_1749, reset) @[RocketPlexMaster.scala 23:70] + node _T_1752 = eq(_T_1750, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1752 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:312 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1753 = eq(io.in[0].a.bits.param, _T_1739) @[RocketPlexMaster.scala 23:70] + node _T_1754 = or(_T_1753, reset) @[RocketPlexMaster.scala 23:70] + node _T_1756 = eq(_T_1754, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1756 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:313 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1757 = eq(io.in[0].a.bits.size, _T_1741) @[RocketPlexMaster.scala 23:70] + node _T_1758 = or(_T_1757, reset) @[RocketPlexMaster.scala 23:70] + node _T_1760 = eq(_T_1758, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1760 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:314 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1761 = eq(io.in[0].a.bits.source, _T_1743) @[RocketPlexMaster.scala 23:70] + node _T_1762 = or(_T_1761, reset) @[RocketPlexMaster.scala 23:70] + node _T_1764 = eq(_T_1762, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1764 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:315 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1765 = eq(io.in[0].a.bits.address, _T_1745) @[RocketPlexMaster.scala 23:70] + node _T_1766 = or(_T_1765, reset) @[RocketPlexMaster.scala 23:70] + node _T_1768 = eq(_T_1766, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1768 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:316 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1769 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1770 = and(_T_1769, _T_1726) @[RocketPlexMaster.scala 23:70] + when _T_1770 : @[RocketPlexMaster.scala 23:70] + _T_1737 <= io.in[0].a.bits.opcode @[RocketPlexMaster.scala 23:70] + _T_1739 <= io.in[0].a.bits.param @[RocketPlexMaster.scala 23:70] + _T_1741 <= io.in[0].a.bits.size @[RocketPlexMaster.scala 23:70] + _T_1743 <= io.in[0].a.bits.source @[RocketPlexMaster.scala 23:70] + _T_1745 <= io.in[0].a.bits.address @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1771 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1773 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1774 = dshl(_T_1773, io.in[0].b.bits.size) @[package.scala 19:71] + node _T_1775 = bits(_T_1774, 7, 0) @[package.scala 19:76] + node _T_1776 = not(_T_1775) @[package.scala 19:40] + node _T_1777 = shr(_T_1776, 3) @[Edges.scala 198:59] + node _T_1778 = bits(io.in[0].b.bits.opcode, 2, 2) @[Edges.scala 81:37] + node _T_1780 = eq(_T_1778, UInt<1>("h00")) @[Edges.scala 81:28] + node _T_1783 = mux(UInt<1>("h00"), _T_1777, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1785 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1787 = sub(_T_1785, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1788 = asUInt(_T_1787) @[Edges.scala 208:28] + node _T_1789 = tail(_T_1788, 1) @[Edges.scala 208:28] + node _T_1791 = eq(_T_1785, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1793 = eq(_T_1785, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1795 = eq(_T_1783, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1796 = or(_T_1793, _T_1795) @[Edges.scala 210:37] + node _T_1797 = and(_T_1796, _T_1771) @[Edges.scala 211:22] + node _T_1798 = not(_T_1789) @[Edges.scala 212:27] + node _T_1799 = and(_T_1783, _T_1798) @[Edges.scala 212:25] + when _T_1771 : @[Edges.scala 213:17] + node _T_1800 = mux(_T_1791, _T_1783, _T_1789) @[Edges.scala 214:21] + _T_1785 <= _T_1800 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1802 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1804 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1806 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1808 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1810 : UInt, clock @[RocketPlexMaster.scala 23:70] + node _T_1812 = eq(_T_1791, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1813 = and(io.in[0].b.valid, _T_1812) @[RocketPlexMaster.scala 23:70] + when _T_1813 : @[RocketPlexMaster.scala 23:70] + node _T_1814 = eq(io.in[0].b.bits.opcode, _T_1802) @[RocketPlexMaster.scala 23:70] + node _T_1815 = or(_T_1814, reset) @[RocketPlexMaster.scala 23:70] + node _T_1817 = eq(_T_1815, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1817 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:335 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1818 = eq(io.in[0].b.bits.param, _T_1804) @[RocketPlexMaster.scala 23:70] + node _T_1819 = or(_T_1818, reset) @[RocketPlexMaster.scala 23:70] + node _T_1821 = eq(_T_1819, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1821 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:336 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1822 = eq(io.in[0].b.bits.size, _T_1806) @[RocketPlexMaster.scala 23:70] + node _T_1823 = or(_T_1822, reset) @[RocketPlexMaster.scala 23:70] + node _T_1825 = eq(_T_1823, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1825 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:337 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1826 = eq(io.in[0].b.bits.source, _T_1808) @[RocketPlexMaster.scala 23:70] + node _T_1827 = or(_T_1826, reset) @[RocketPlexMaster.scala 23:70] + node _T_1829 = eq(_T_1827, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1829 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:338 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1830 = eq(io.in[0].b.bits.address, _T_1810) @[RocketPlexMaster.scala 23:70] + node _T_1831 = or(_T_1830, reset) @[RocketPlexMaster.scala 23:70] + node _T_1833 = eq(_T_1831, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1833 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:339 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1834 = and(io.in[0].b.ready, io.in[0].b.valid) @[Bundles.scala 207:36] + node _T_1835 = and(_T_1834, _T_1791) @[RocketPlexMaster.scala 23:70] + when _T_1835 : @[RocketPlexMaster.scala 23:70] + _T_1802 <= io.in[0].b.bits.opcode @[RocketPlexMaster.scala 23:70] + _T_1804 <= io.in[0].b.bits.param @[RocketPlexMaster.scala 23:70] + _T_1806 <= io.in[0].b.bits.size @[RocketPlexMaster.scala 23:70] + _T_1808 <= io.in[0].b.bits.source @[RocketPlexMaster.scala 23:70] + _T_1810 <= io.in[0].b.bits.address @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1836 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1838 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1839 = dshl(_T_1838, io.in[0].c.bits.size) @[package.scala 19:71] + node _T_1840 = bits(_T_1839, 7, 0) @[package.scala 19:76] + node _T_1841 = not(_T_1840) @[package.scala 19:40] + node _T_1842 = shr(_T_1841, 3) @[Edges.scala 198:59] + node _T_1843 = bits(io.in[0].c.bits.opcode, 0, 0) @[Edges.scala 86:36] + node _T_1846 = mux(UInt<1>("h00"), _T_1842, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1848 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1850 = sub(_T_1848, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1851 = asUInt(_T_1850) @[Edges.scala 208:28] + node _T_1852 = tail(_T_1851, 1) @[Edges.scala 208:28] + node _T_1854 = eq(_T_1848, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1856 = eq(_T_1848, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1858 = eq(_T_1846, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1859 = or(_T_1856, _T_1858) @[Edges.scala 210:37] + node _T_1860 = and(_T_1859, _T_1836) @[Edges.scala 211:22] + node _T_1861 = not(_T_1852) @[Edges.scala 212:27] + node _T_1862 = and(_T_1846, _T_1861) @[Edges.scala 212:25] + when _T_1836 : @[Edges.scala 213:17] + node _T_1863 = mux(_T_1854, _T_1846, _T_1852) @[Edges.scala 214:21] + _T_1848 <= _T_1863 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1865 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1867 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1869 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1871 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1873 : UInt, clock @[RocketPlexMaster.scala 23:70] + node _T_1875 = eq(_T_1854, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1876 = and(io.in[0].c.valid, _T_1875) @[RocketPlexMaster.scala 23:70] + when _T_1876 : @[RocketPlexMaster.scala 23:70] + node _T_1877 = eq(io.in[0].c.bits.opcode, _T_1865) @[RocketPlexMaster.scala 23:70] + node _T_1878 = or(_T_1877, reset) @[RocketPlexMaster.scala 23:70] + node _T_1880 = eq(_T_1878, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1880 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:358 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1881 = eq(io.in[0].c.bits.param, _T_1867) @[RocketPlexMaster.scala 23:70] + node _T_1882 = or(_T_1881, reset) @[RocketPlexMaster.scala 23:70] + node _T_1884 = eq(_T_1882, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1884 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:359 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1885 = eq(io.in[0].c.bits.size, _T_1869) @[RocketPlexMaster.scala 23:70] + node _T_1886 = or(_T_1885, reset) @[RocketPlexMaster.scala 23:70] + node _T_1888 = eq(_T_1886, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1888 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:360 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1889 = eq(io.in[0].c.bits.source, _T_1871) @[RocketPlexMaster.scala 23:70] + node _T_1890 = or(_T_1889, reset) @[RocketPlexMaster.scala 23:70] + node _T_1892 = eq(_T_1890, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1892 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:361 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1893 = eq(io.in[0].c.bits.address, _T_1873) @[RocketPlexMaster.scala 23:70] + node _T_1894 = or(_T_1893, reset) @[RocketPlexMaster.scala 23:70] + node _T_1896 = eq(_T_1894, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1896 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:362 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1897 = and(io.in[0].c.ready, io.in[0].c.valid) @[Bundles.scala 207:36] + node _T_1898 = and(_T_1897, _T_1854) @[RocketPlexMaster.scala 23:70] + when _T_1898 : @[RocketPlexMaster.scala 23:70] + _T_1865 <= io.in[0].c.bits.opcode @[RocketPlexMaster.scala 23:70] + _T_1867 <= io.in[0].c.bits.param @[RocketPlexMaster.scala 23:70] + _T_1869 <= io.in[0].c.bits.size @[RocketPlexMaster.scala 23:70] + _T_1871 <= io.in[0].c.bits.source @[RocketPlexMaster.scala 23:70] + _T_1873 <= io.in[0].c.bits.address @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1899 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1901 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1902 = dshl(_T_1901, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_1903 = bits(_T_1902, 7, 0) @[package.scala 19:76] + node _T_1904 = not(_T_1903) @[package.scala 19:40] + node _T_1905 = shr(_T_1904, 3) @[Edges.scala 198:59] + node _T_1906 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_1908 = mux(_T_1906, _T_1905, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1910 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1912 = sub(_T_1910, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1913 = asUInt(_T_1912) @[Edges.scala 208:28] + node _T_1914 = tail(_T_1913, 1) @[Edges.scala 208:28] + node _T_1916 = eq(_T_1910, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1918 = eq(_T_1910, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1920 = eq(_T_1908, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1921 = or(_T_1918, _T_1920) @[Edges.scala 210:37] + node _T_1922 = and(_T_1921, _T_1899) @[Edges.scala 211:22] + node _T_1923 = not(_T_1914) @[Edges.scala 212:27] + node _T_1924 = and(_T_1908, _T_1923) @[Edges.scala 212:25] + when _T_1899 : @[Edges.scala 213:17] + node _T_1925 = mux(_T_1916, _T_1908, _T_1914) @[Edges.scala 214:21] + _T_1910 <= _T_1925 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + reg _T_1927 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1929 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1931 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1933 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1935 : UInt, clock @[RocketPlexMaster.scala 23:70] + reg _T_1937 : UInt, clock @[RocketPlexMaster.scala 23:70] + node _T_1939 = eq(_T_1916, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_1940 = and(io.in[0].d.valid, _T_1939) @[RocketPlexMaster.scala 23:70] + when _T_1940 : @[RocketPlexMaster.scala 23:70] + node _T_1941 = eq(io.in[0].d.bits.opcode, _T_1927) @[RocketPlexMaster.scala 23:70] + node _T_1942 = or(_T_1941, reset) @[RocketPlexMaster.scala 23:70] + node _T_1944 = eq(_T_1942, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1944 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:382 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1945 = eq(io.in[0].d.bits.param, _T_1929) @[RocketPlexMaster.scala 23:70] + node _T_1946 = or(_T_1945, reset) @[RocketPlexMaster.scala 23:70] + node _T_1948 = eq(_T_1946, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1948 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:383 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1949 = eq(io.in[0].d.bits.size, _T_1931) @[RocketPlexMaster.scala 23:70] + node _T_1950 = or(_T_1949, reset) @[RocketPlexMaster.scala 23:70] + node _T_1952 = eq(_T_1950, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1952 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:384 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1953 = eq(io.in[0].d.bits.source, _T_1933) @[RocketPlexMaster.scala 23:70] + node _T_1954 = or(_T_1953, reset) @[RocketPlexMaster.scala 23:70] + node _T_1956 = eq(_T_1954, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1956 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:385 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1957 = eq(io.in[0].d.bits.sink, _T_1935) @[RocketPlexMaster.scala 23:70] + node _T_1958 = or(_T_1957, reset) @[RocketPlexMaster.scala 23:70] + node _T_1960 = eq(_T_1958, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1960 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:386 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1961 = eq(io.in[0].d.bits.addr_lo, _T_1937) @[RocketPlexMaster.scala 23:70] + node _T_1962 = or(_T_1961, reset) @[RocketPlexMaster.scala 23:70] + node _T_1964 = eq(_T_1962, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_1964 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel addr_lo changed with multibeat operation (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:387 assert (d.bits.addr_lo=== addr_lo,\"'D' channel addr_lo changed with multibeat operation\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_1965 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_1966 = and(_T_1965, _T_1916) @[RocketPlexMaster.scala 23:70] + when _T_1966 : @[RocketPlexMaster.scala 23:70] + _T_1927 <= io.in[0].d.bits.opcode @[RocketPlexMaster.scala 23:70] + _T_1929 <= io.in[0].d.bits.param @[RocketPlexMaster.scala 23:70] + _T_1931 <= io.in[0].d.bits.size @[RocketPlexMaster.scala 23:70] + _T_1933 <= io.in[0].d.bits.source @[RocketPlexMaster.scala 23:70] + _T_1935 <= io.in[0].d.bits.sink @[RocketPlexMaster.scala 23:70] + _T_1937 <= io.in[0].d.bits.addr_lo @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + reg _T_1968 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44] + node _T_1969 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + node _T_1971 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_1972 = dshl(_T_1971, io.in[0].a.bits.size) @[package.scala 19:71] + node _T_1973 = bits(_T_1972, 7, 0) @[package.scala 19:76] + node _T_1974 = not(_T_1973) @[package.scala 19:40] + node _T_1975 = shr(_T_1974, 3) @[Edges.scala 198:59] + node _T_1976 = bits(io.in[0].a.bits.opcode, 2, 2) @[Edges.scala 76:37] + node _T_1978 = eq(_T_1976, UInt<1>("h00")) @[Edges.scala 76:28] + node _T_1980 = mux(_T_1978, _T_1975, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_1982 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_1984 = sub(_T_1982, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_1985 = asUInt(_T_1984) @[Edges.scala 208:28] + node _T_1986 = tail(_T_1985, 1) @[Edges.scala 208:28] + node _T_1988 = eq(_T_1982, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_1990 = eq(_T_1982, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_1992 = eq(_T_1980, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_1993 = or(_T_1990, _T_1992) @[Edges.scala 210:37] + node _T_1994 = and(_T_1993, _T_1969) @[Edges.scala 211:22] + node _T_1995 = not(_T_1986) @[Edges.scala 212:27] + node _T_1996 = and(_T_1980, _T_1995) @[Edges.scala 212:25] + when _T_1969 : @[Edges.scala 213:17] + node _T_1997 = mux(_T_1988, _T_1980, _T_1986) @[Edges.scala 214:21] + _T_1982 <= _T_1997 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_1998 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2000 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_2001 = dshl(_T_2000, io.in[0].d.bits.size) @[package.scala 19:71] + node _T_2002 = bits(_T_2001, 7, 0) @[package.scala 19:76] + node _T_2003 = not(_T_2002) @[package.scala 19:40] + node _T_2004 = shr(_T_2003, 3) @[Edges.scala 198:59] + node _T_2005 = bits(io.in[0].d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_2007 = mux(_T_2005, _T_2004, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_2009 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_2011 = sub(_T_2009, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_2012 = asUInt(_T_2011) @[Edges.scala 208:28] + node _T_2013 = tail(_T_2012, 1) @[Edges.scala 208:28] + node _T_2015 = eq(_T_2009, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_2017 = eq(_T_2009, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_2019 = eq(_T_2007, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_2020 = or(_T_2017, _T_2019) @[Edges.scala 210:37] + node _T_2021 = and(_T_2020, _T_1998) @[Edges.scala 211:22] + node _T_2022 = not(_T_2013) @[Edges.scala 212:27] + node _T_2023 = and(_T_2007, _T_2022) @[Edges.scala 212:25] + when _T_1998 : @[Edges.scala 213:17] + node _T_2024 = mux(_T_2015, _T_2007, _T_2013) @[Edges.scala 214:21] + _T_2009 <= _T_2024 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + node _T_2026 = eq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + node _T_2027 = neq(io.in[0].a.bits.source, io.in[0].d.bits.source) @[RocketPlexMaster.scala 23:70] + node _T_2028 = or(_T_2026, _T_2027) @[RocketPlexMaster.scala 23:70] + node _T_2030 = eq(io.in[0].a.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_2031 = or(_T_2028, _T_2030) @[RocketPlexMaster.scala 23:70] + node _T_2033 = eq(io.in[0].d.valid, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_2034 = or(_T_2031, _T_2033) @[RocketPlexMaster.scala 23:70] + node _T_2035 = or(_T_2034, reset) @[RocketPlexMaster.scala 23:70] + node _T_2037 = eq(_T_2035, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_2037 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:413 assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + wire _T_2039 : UInt<32> + _T_2039 is invalid + _T_2039 <= UInt<32>("h00") + node _T_2040 = and(io.in[0].a.ready, io.in[0].a.valid) @[Bundles.scala 207:36] + when _T_2040 : @[RocketPlexMaster.scala 23:70] + when _T_1993 : @[RocketPlexMaster.scala 23:70] + node _T_2042 = dshl(UInt<1>("h01"), io.in[0].a.bits.source) @[OneHot.scala 47:11] + _T_2039 <= _T_2042 @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_2043 = dshr(_T_1968, io.in[0].a.bits.source) @[RocketPlexMaster.scala 23:70] + node _T_2044 = bits(_T_2043, 0, 0) @[RocketPlexMaster.scala 23:70] + node _T_2046 = eq(_T_2044, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + node _T_2047 = or(_T_2046, reset) @[RocketPlexMaster.scala 23:70] + node _T_2049 = eq(_T_2047, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_2049 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'A' channel re-used a source ID (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:419 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + wire _T_2051 : UInt<32> + _T_2051 is invalid + _T_2051 <= UInt<32>("h00") + node _T_2052 = and(io.in[0].d.ready, io.in[0].d.valid) @[Bundles.scala 207:36] + node _T_2054 = neq(io.in[0].d.bits.opcode, UInt<3>("h06")) @[RocketPlexMaster.scala 23:70] + node _T_2055 = and(_T_2052, _T_2054) @[RocketPlexMaster.scala 23:70] + when _T_2055 : @[RocketPlexMaster.scala 23:70] + when _T_2020 : @[RocketPlexMaster.scala 23:70] + node _T_2057 = dshl(UInt<1>("h01"), io.in[0].d.bits.source) @[OneHot.scala 47:11] + _T_2051 <= _T_2057 @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_2058 = or(_T_2039, _T_1968) @[RocketPlexMaster.scala 23:70] + node _T_2059 = dshr(_T_2058, io.in[0].d.bits.source) @[RocketPlexMaster.scala 23:70] + node _T_2060 = bits(_T_2059, 0, 0) @[RocketPlexMaster.scala 23:70] + node _T_2061 = or(_T_2060, reset) @[RocketPlexMaster.scala 23:70] + node _T_2063 = eq(_T_2061, UInt<1>("h00")) @[RocketPlexMaster.scala 23:70] + when _T_2063 : @[RocketPlexMaster.scala 23:70] + printf(clock, UInt<1>(1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at RocketPlexMaster.scala:23:70)\n at Monitor.scala:425 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n") @[RocketPlexMaster.scala 23:70] + stop(clock, UInt<1>(1), 1) @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + skip @[RocketPlexMaster.scala 23:70] + node _T_2064 = or(_T_1968, _T_2039) @[RocketPlexMaster.scala 23:70] + node _T_2065 = not(_T_2051) @[RocketPlexMaster.scala 23:70] + node _T_2066 = and(_T_2064, _T_2065) @[RocketPlexMaster.scala 23:70] + _T_1968 <= _T_2066 @[RocketPlexMaster.scala 23:70] - module ICache : + extmodule AsyncResetReg_29 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_29 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg invalidated : UInt<1>, clk - node stall = eq(io.resp.ready, UInt<1>("h00")) - wire rdy : UInt<1> - rdy is invalid - reg refill_addr : UInt<32>, clk - wire s1_any_tag_hit : UInt<1> - s1_any_tag_hit is invalid - reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s1_pgoff : UInt<12>, clk - node s1_addr = cat(io.req.bits.ppn, s1_pgoff) - node s1_tag = bits(s1_addr, 31, 12) - node T_523 = and(s1_valid, stall) - node s0_valid = or(io.req.valid, T_523) - node T_525 = and(s1_valid, stall) - node s0_pgoff = mux(T_525, s1_pgoff, io.req.bits.idx) - node T_527 = and(io.req.valid, rdy) - node T_528 = and(s1_valid, stall) - node T_530 = eq(io.req.bits.kill, UInt<1>("h00")) - node T_531 = and(T_528, T_530) - node T_532 = or(T_527, T_531) - s1_valid <= T_532 - node T_533 = and(io.req.valid, rdy) - when T_533 : - s1_pgoff <= io.req.bits.idx - skip - node T_535 = eq(io.req.bits.kill, UInt<1>("h00")) - node T_536 = and(s1_valid, T_535) - node T_537 = eq(state, UInt<1>("h00")) - node out_valid = and(T_536, T_537) - node s1_idx = bits(s1_addr, 11, 6) - node s1_offset = bits(s1_addr, 5, 0) - node s1_hit = and(out_valid, s1_any_tag_hit) - node T_543 = eq(s1_any_tag_hit, UInt<1>("h00")) - node s1_miss = and(out_valid, T_543) - node T_545 = eq(state, UInt<1>("h00")) - node T_547 = eq(s1_miss, UInt<1>("h00")) - node T_548 = and(T_545, T_547) - rdy <= T_548 - node T_549 = eq(state, UInt<1>("h00")) - node T_550 = and(s1_valid, T_549) - node T_551 = and(T_550, s1_miss) - when T_551 : - refill_addr <= s1_addr - skip - node refill_tag = bits(refill_addr, 31, 12) - inst T_553 of FlowThroughSerializer - T_553.io is invalid - T_553.clk <= clk - T_553.reset <= reset - T_553.io.in.valid <= io.mem.grant.valid - T_553.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_553.io.in.ready - node T_554 = and(T_553.io.out.ready, T_553.io.out.valid) - reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_554 : - node T_558 = eq(refill_cnt, UInt<2>("h03")) - node T_560 = and(UInt<1>("h00"), T_558) - node T_563 = add(refill_cnt, UInt<1>("h01")) - node T_564 = tail(T_563, 1) - node T_565 = mux(T_560, UInt<1>("h00"), T_564) - refill_cnt <= T_565 - skip - node refill_wrap = and(T_554, T_558) - node T_567 = eq(state, UInt<2>("h03")) - node refill_done = and(T_567, refill_wrap) - T_553.io.out.ready <= UInt<1>("h01") - reg T_571 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) - when s1_miss : - node T_572 = bits(T_571, 0, 0) - node T_573 = bits(T_571, 2, 2) - node T_574 = xor(T_572, T_573) - node T_575 = bits(T_571, 3, 3) - node T_576 = xor(T_574, T_575) - node T_577 = bits(T_571, 5, 5) - node T_578 = xor(T_576, T_577) - node T_579 = bits(T_571, 15, 1) - node T_580 = cat(T_578, T_579) - T_571 <= T_580 - skip - node repl_way = bits(T_571, 1, 0) - smem tag_array : UInt<20>[4][64] - node T_599 = bits(s0_pgoff, 11, 6) - node T_601 = eq(refill_done, UInt<1>("h00")) - node T_602 = and(T_601, s0_valid) - wire T_604 : UInt - T_604 is invalid - when T_602 : - T_604 <= T_599 - skip - read mport tag_rdata = tag_array[T_604], clk - when refill_done : - wire T_614 : UInt<20>[4] - T_614[0] <= refill_tag - T_614[1] <= refill_tag - T_614[2] <= refill_tag - T_614[3] <= refill_tag - node T_621 = eq(repl_way, UInt<1>("h00")) - node T_623 = eq(repl_way, UInt<1>("h01")) - node T_625 = eq(repl_way, UInt<2>("h02")) - node T_627 = eq(repl_way, UInt<2>("h03")) - wire T_629 : UInt<1>[4] - T_629[0] <= T_621 - T_629[1] <= T_623 - T_629[2] <= T_625 - T_629[3] <= T_627 - write mport T_637 = tag_array[s1_idx], clk - when T_629[0] : - T_637[0] <= T_614[0] - skip - when T_629[1] : - T_637[1] <= T_614[1] - skip - when T_629[2] : - T_637[2] <= T_614[2] - skip - when T_629[3] : - T_637[3] <= T_614[3] - skip - skip - reg vb_array : UInt<256>, clk with : (reset => (reset, UInt<256>("h00"))) - node T_646 = eq(invalidated, UInt<1>("h00")) - node T_647 = and(refill_done, T_646) - when T_647 : - node T_648 = cat(repl_way, s1_idx) - node T_651 = dshl(UInt<1>("h01"), T_648) - node T_652 = or(vb_array, T_651) - node T_653 = not(vb_array) - node T_654 = or(T_653, T_651) - node T_655 = not(T_654) - node T_656 = mux(UInt<1>("h01"), T_652, T_655) - vb_array <= T_656 - skip - when io.invalidate : - vb_array <= UInt<1>("h00") - invalidated <= UInt<1>("h01") - skip - wire s1_disparity : UInt<1>[4] - s1_disparity is invalid - node T_675 = and(s1_valid, s1_disparity[0]) - when T_675 : - node T_677 = cat(UInt<1>("h00"), s1_idx) - node T_680 = dshl(UInt<1>("h01"), T_677) - node T_681 = or(vb_array, T_680) - node T_682 = not(vb_array) - node T_683 = or(T_682, T_680) - node T_684 = not(T_683) - node T_685 = mux(UInt<1>("h00"), T_681, T_684) - vb_array <= T_685 - skip - node T_686 = and(s1_valid, s1_disparity[1]) - when T_686 : - node T_688 = cat(UInt<1>("h01"), s1_idx) - node T_691 = dshl(UInt<1>("h01"), T_688) - node T_692 = or(vb_array, T_691) - node T_693 = not(vb_array) - node T_694 = or(T_693, T_691) - node T_695 = not(T_694) - node T_696 = mux(UInt<1>("h00"), T_692, T_695) - vb_array <= T_696 - skip - node T_697 = and(s1_valid, s1_disparity[2]) - when T_697 : - node T_699 = cat(UInt<2>("h02"), s1_idx) - node T_702 = dshl(UInt<1>("h01"), T_699) - node T_703 = or(vb_array, T_702) - node T_704 = not(vb_array) - node T_705 = or(T_704, T_702) - node T_706 = not(T_705) - node T_707 = mux(UInt<1>("h00"), T_703, T_706) - vb_array <= T_707 - skip - node T_708 = and(s1_valid, s1_disparity[3]) - when T_708 : - node T_710 = cat(UInt<2>("h03"), s1_idx) - node T_713 = dshl(UInt<1>("h01"), T_710) - node T_714 = or(vb_array, T_713) - node T_715 = not(vb_array) - node T_716 = or(T_715, T_713) - node T_717 = not(T_716) - node T_718 = mux(UInt<1>("h00"), T_714, T_717) - vb_array <= T_718 - skip - wire s1_tag_match : UInt<1>[4] - s1_tag_match is invalid - wire s1_tag_hit : UInt<1>[4] - s1_tag_hit is invalid - wire s1_dout : UInt<128>[4] - s1_dout is invalid - node T_768 = eq(io.invalidate, UInt<1>("h00")) - node T_770 = bits(s1_pgoff, 11, 6) - node T_771 = cat(UInt<1>("h00"), T_770) - node T_772 = dshr(vb_array, T_771) - node T_773 = bits(T_772, 0, 0) - node T_774 = bits(T_773, 0, 0) - node T_775 = and(T_768, T_774) - node T_778 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_779 = and(s1_valid, rdy) - node T_781 = eq(stall, UInt<1>("h00")) - node T_782 = and(T_779, T_781) - when T_782 : - skip - node T_783 = bits(tag_rdata[0], 19, 0) - node T_784 = eq(T_783, s1_tag) - s1_tag_match[0] <= T_784 - node T_785 = and(T_775, s1_tag_match[0]) - s1_tag_hit[0] <= T_785 - node T_788 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_789 = or(T_778, T_788) - node T_790 = and(T_775, T_789) - s1_disparity[0] <= T_790 - node T_792 = eq(io.invalidate, UInt<1>("h00")) - node T_794 = bits(s1_pgoff, 11, 6) - node T_795 = cat(UInt<1>("h01"), T_794) - node T_796 = dshr(vb_array, T_795) - node T_797 = bits(T_796, 0, 0) - node T_798 = bits(T_797, 0, 0) - node T_799 = and(T_792, T_798) - node T_802 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_803 = and(s1_valid, rdy) - node T_805 = eq(stall, UInt<1>("h00")) - node T_806 = and(T_803, T_805) - when T_806 : - skip - node T_807 = bits(tag_rdata[1], 19, 0) - node T_808 = eq(T_807, s1_tag) - s1_tag_match[1] <= T_808 - node T_809 = and(T_799, s1_tag_match[1]) - s1_tag_hit[1] <= T_809 - node T_812 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_813 = or(T_802, T_812) - node T_814 = and(T_799, T_813) - s1_disparity[1] <= T_814 - node T_816 = eq(io.invalidate, UInt<1>("h00")) - node T_818 = bits(s1_pgoff, 11, 6) - node T_819 = cat(UInt<2>("h02"), T_818) - node T_820 = dshr(vb_array, T_819) - node T_821 = bits(T_820, 0, 0) - node T_822 = bits(T_821, 0, 0) - node T_823 = and(T_816, T_822) - node T_826 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_827 = and(s1_valid, rdy) - node T_829 = eq(stall, UInt<1>("h00")) - node T_830 = and(T_827, T_829) - when T_830 : - skip - node T_831 = bits(tag_rdata[2], 19, 0) - node T_832 = eq(T_831, s1_tag) - s1_tag_match[2] <= T_832 - node T_833 = and(T_823, s1_tag_match[2]) - s1_tag_hit[2] <= T_833 - node T_836 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_837 = or(T_826, T_836) - node T_838 = and(T_823, T_837) - s1_disparity[2] <= T_838 - node T_840 = eq(io.invalidate, UInt<1>("h00")) - node T_842 = bits(s1_pgoff, 11, 6) - node T_843 = cat(UInt<2>("h03"), T_842) - node T_844 = dshr(vb_array, T_843) - node T_845 = bits(T_844, 0, 0) - node T_846 = bits(T_845, 0, 0) - node T_847 = and(T_840, T_846) - node T_850 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_851 = and(s1_valid, rdy) - node T_853 = eq(stall, UInt<1>("h00")) - node T_854 = and(T_851, T_853) - when T_854 : - skip - node T_855 = bits(tag_rdata[3], 19, 0) - node T_856 = eq(T_855, s1_tag) - s1_tag_match[3] <= T_856 - node T_857 = and(T_847, s1_tag_match[3]) - s1_tag_hit[3] <= T_857 - node T_860 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_861 = or(T_850, T_860) - node T_862 = and(T_847, T_861) - s1_disparity[3] <= T_862 - node T_863 = or(s1_tag_hit[0], s1_tag_hit[1]) - node T_864 = or(T_863, s1_tag_hit[2]) - node T_865 = or(T_864, s1_tag_hit[3]) - node T_866 = or(s1_disparity[0], s1_disparity[1]) - node T_867 = or(T_866, s1_disparity[2]) - node T_868 = or(T_867, s1_disparity[3]) - node T_870 = eq(T_868, UInt<1>("h00")) - node T_871 = and(T_865, T_870) - s1_any_tag_hit <= T_871 - smem T_874 : UInt<128>[256] - node T_876 = eq(repl_way, UInt<1>("h00")) - node T_877 = and(T_553.io.out.valid, T_876) - when T_877 : - node T_878 = cat(s1_idx, refill_cnt) - write mport T_879 = T_874[T_878], clk - T_879 <= T_553.io.out.bits.data - skip - node T_880 = bits(s0_pgoff, 11, 4) - node T_882 = eq(T_877, UInt<1>("h00")) - node T_883 = and(T_882, s0_valid) - wire T_885 : UInt - T_885 is invalid - when T_883 : - T_885 <= T_880 - skip - read mport T_886 = T_874[T_885], clk - s1_dout[0] <= T_886 - smem T_889 : UInt<128>[256] - node T_891 = eq(repl_way, UInt<1>("h01")) - node T_892 = and(T_553.io.out.valid, T_891) - when T_892 : - node T_893 = cat(s1_idx, refill_cnt) - write mport T_894 = T_889[T_893], clk - T_894 <= T_553.io.out.bits.data - skip - node T_895 = bits(s0_pgoff, 11, 4) - node T_897 = eq(T_892, UInt<1>("h00")) - node T_898 = and(T_897, s0_valid) - wire T_900 : UInt - T_900 is invalid - when T_898 : - T_900 <= T_895 - skip - read mport T_901 = T_889[T_900], clk - s1_dout[1] <= T_901 - smem T_904 : UInt<128>[256] - node T_906 = eq(repl_way, UInt<2>("h02")) - node T_907 = and(T_553.io.out.valid, T_906) - when T_907 : - node T_908 = cat(s1_idx, refill_cnt) - write mport T_909 = T_904[T_908], clk - T_909 <= T_553.io.out.bits.data - skip - node T_910 = bits(s0_pgoff, 11, 4) - node T_912 = eq(T_907, UInt<1>("h00")) - node T_913 = and(T_912, s0_valid) - wire T_915 : UInt - T_915 is invalid - when T_913 : - T_915 <= T_910 - skip - read mport T_916 = T_904[T_915], clk - s1_dout[2] <= T_916 - smem T_919 : UInt<128>[256] - node T_921 = eq(repl_way, UInt<2>("h03")) - node T_922 = and(T_553.io.out.valid, T_921) - when T_922 : - node T_923 = cat(s1_idx, refill_cnt) - write mport T_924 = T_919[T_923], clk - T_924 <= T_553.io.out.bits.data - skip - node T_925 = bits(s0_pgoff, 11, 4) - node T_927 = eq(T_922, UInt<1>("h00")) - node T_928 = and(T_927, s0_valid) - wire T_930 : UInt - T_930 is invalid - when T_928 : - T_930 <= T_925 - skip - read mport T_931 = T_919[T_930], clk - s1_dout[3] <= T_931 - node T_933 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h00")) - node T_935 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h00")) - node T_937 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h00")) - node T_939 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h00")) - node T_941 = or(T_933, T_935) - node T_942 = or(T_941, T_937) - node T_943 = or(T_942, T_939) - wire T_944 : UInt<128> - T_944 is invalid - T_944 <= T_943 - io.resp.bits.datablock <= T_944 - io.resp.valid <= s1_hit - node T_945 = eq(state, UInt<1>("h01")) - io.mem.acquire.valid <= T_945 - node T_946 = shr(refill_addr, 6) - node T_957 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_958 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_959 = cat(T_957, T_958) - node T_961 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_962 = cat(UInt<3>("h07"), T_961) - node T_964 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_966 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_968 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_969 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_970 = cat(T_968, T_969) - node T_972 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_974 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_975 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_976 = mux(T_975, T_974, UInt<1>("h00")) - node T_977 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_978 = mux(T_977, T_972, T_976) - node T_979 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_980 = mux(T_979, T_970, T_978) - node T_981 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_982 = mux(T_981, T_966, T_980) - node T_983 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_984 = mux(T_983, T_964, T_982) - node T_985 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_986 = mux(T_985, T_962, T_984) - node T_987 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_988 = mux(T_987, T_959, T_986) - wire T_1020 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1020 is invalid - T_1020.is_builtin_type <= UInt<1>("h01") - T_1020.a_type <= UInt<3>("h01") - T_1020.client_xact_id <= UInt<1>("h00") - T_1020.addr_block <= T_946 - T_1020.addr_beat <= UInt<1>("h00") - T_1020.data <= UInt<1>("h00") - T_1020.union <= T_988 - io.mem.acquire.bits <- T_1020 - node T_1051 = eq(UInt<1>("h00"), state) - when T_1051 : - when s1_miss : - state <= UInt<1>("h01") - skip - invalidated <= UInt<1>("h00") - skip - node T_1053 = eq(UInt<1>("h01"), state) - when T_1053 : - when io.mem.acquire.ready : - state <= UInt<2>("h02") - skip - skip - node T_1054 = eq(UInt<2>("h02"), state) - when T_1054 : - when io.mem.grant.valid : - state <= UInt<2>("h03") - skip - skip - node T_1055 = eq(UInt<2>("h03"), state) - when T_1055 : - when refill_done : - state <= UInt<1>("h00") - skip - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module RocketCAM : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_29 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_30 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_30 : + input clock : Clock input reset : UInt<1> - output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>} - - io is invalid - cmem cam_tags : UInt<34>[8] - reg vb_array : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - when io.write : - node T_21 = dshl(UInt<1>("h01"), io.write_addr) - node T_22 = or(vb_array, T_21) - node T_23 = not(vb_array) - node T_24 = or(T_23, T_21) - node T_25 = not(T_24) - node T_26 = mux(UInt<1>("h01"), T_22, T_25) - vb_array <= T_26 - infer mport T_27 = cam_tags[io.write_addr], clk - T_27 <= io.write_tag - skip - when io.clear : - node T_28 = not(io.clear_mask) - node T_29 = and(vb_array, T_28) - vb_array <= T_29 - skip - node T_30 = bits(vb_array, 0, 0) - infer mport T_32 = cam_tags[UInt<1>("h00")], clk - node T_33 = eq(T_32, io.tag) - node T_34 = and(T_30, T_33) - node T_35 = bits(vb_array, 1, 1) - infer mport T_37 = cam_tags[UInt<1>("h01")], clk - node T_38 = eq(T_37, io.tag) - node T_39 = and(T_35, T_38) - node T_40 = bits(vb_array, 2, 2) - infer mport T_42 = cam_tags[UInt<2>("h02")], clk - node T_43 = eq(T_42, io.tag) - node T_44 = and(T_40, T_43) - node T_45 = bits(vb_array, 3, 3) - infer mport T_47 = cam_tags[UInt<2>("h03")], clk - node T_48 = eq(T_47, io.tag) - node T_49 = and(T_45, T_48) - node T_50 = bits(vb_array, 4, 4) - infer mport T_52 = cam_tags[UInt<3>("h04")], clk - node T_53 = eq(T_52, io.tag) - node T_54 = and(T_50, T_53) - node T_55 = bits(vb_array, 5, 5) - infer mport T_57 = cam_tags[UInt<3>("h05")], clk - node T_58 = eq(T_57, io.tag) - node T_59 = and(T_55, T_58) - node T_60 = bits(vb_array, 6, 6) - infer mport T_62 = cam_tags[UInt<3>("h06")], clk - node T_63 = eq(T_62, io.tag) - node T_64 = and(T_60, T_63) - node T_65 = bits(vb_array, 7, 7) - infer mport T_67 = cam_tags[UInt<3>("h07")], clk - node T_68 = eq(T_67, io.tag) - node T_69 = and(T_65, T_68) - io.valid_bits <= vb_array - wire T_71 : UInt<1>[8] - T_71[0] <= T_34 - T_71[1] <= T_39 - T_71[2] <= T_44 - T_71[3] <= T_49 - T_71[4] <= T_54 - T_71[5] <= T_59 - T_71[6] <= T_64 - T_71[7] <= T_69 - node T_81 = cat(T_71[7], T_71[6]) - node T_82 = cat(T_71[5], T_71[4]) - node T_83 = cat(T_81, T_82) - node T_84 = cat(T_71[3], T_71[2]) - node T_85 = cat(T_71[1], T_71[0]) - node T_86 = cat(T_84, T_85) - node T_87 = cat(T_83, T_86) - io.hits <= T_87 - node T_89 = neq(io.hits, UInt<1>("h00")) - io.hit <= T_89 + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module TLB : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_30 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_31 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_31 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg r_refill_tag : UInt, clk - reg r_refill_waddr : UInt, clk - reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk - inst tag_cam of RocketCAM - tag_cam.io is invalid - tag_cam.clk <= clk - tag_cam.reset <= reset - cmem tag_ram : UInt<20>[8] - node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) - tag_cam.io.tag <= lookup_tag - node T_176 = eq(state, UInt<2>("h02")) - node T_177 = and(T_176, io.ptw.resp.valid) - tag_cam.io.write <= T_177 - tag_cam.io.write_tag <= r_refill_tag - tag_cam.io.write_addr <= r_refill_waddr - node T_178 = bits(tag_cam.io.hits, 7, 4) - node T_179 = bits(tag_cam.io.hits, 3, 0) - node T_181 = neq(T_178, UInt<1>("h00")) - node T_182 = or(T_178, T_179) - node T_183 = bits(T_182, 3, 2) - node T_184 = bits(T_182, 1, 0) - node T_186 = neq(T_183, UInt<1>("h00")) - node T_187 = or(T_183, T_184) - node T_188 = bits(T_187, 1, 1) - node T_189 = cat(T_186, T_188) - node tag_hit_addr = cat(T_181, T_189) - reg valid_array : UInt<1>[8], clk - reg ur_array : UInt<1>[8], clk - reg uw_array : UInt<1>[8], clk - reg ux_array : UInt<1>[8], clk - reg sr_array : UInt<1>[8], clk - reg sw_array : UInt<1>[8], clk - reg sx_array : UInt<1>[8], clk - reg dirty_array : UInt<1>[8], clk - when io.ptw.resp.valid : - infer mport T_383 = tag_ram[r_refill_waddr], clk - T_383 <= io.ptw.resp.bits.pte.ppn - node T_386 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - valid_array[r_refill_waddr] <= T_386 - node T_389 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_390 = and(io.ptw.resp.bits.pte.v, T_389) - node T_392 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_393 = and(T_390, T_392) - node T_395 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_396 = and(T_393, T_395) - ur_array[r_refill_waddr] <= T_396 - node T_399 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_400 = and(io.ptw.resp.bits.pte.v, T_399) - node T_402 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_403 = and(T_400, T_402) - node T_404 = bits(io.ptw.resp.bits.pte.typ, 0, 0) - node T_405 = and(T_403, T_404) - node T_407 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_408 = and(T_405, T_407) - uw_array[r_refill_waddr] <= T_408 - node T_411 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_412 = and(io.ptw.resp.bits.pte.v, T_411) - node T_414 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_415 = and(T_412, T_414) - node T_416 = bits(io.ptw.resp.bits.pte.typ, 1, 1) - node T_417 = and(T_415, T_416) - node T_419 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_420 = and(T_417, T_419) - ux_array[r_refill_waddr] <= T_420 - node T_423 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_424 = and(io.ptw.resp.bits.pte.v, T_423) - node T_426 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_427 = and(T_424, T_426) - sr_array[r_refill_waddr] <= T_427 - node T_430 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_431 = and(io.ptw.resp.bits.pte.v, T_430) - node T_432 = bits(io.ptw.resp.bits.pte.typ, 0, 0) - node T_433 = and(T_431, T_432) - node T_435 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_436 = and(T_433, T_435) - sw_array[r_refill_waddr] <= T_436 - node T_439 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) - node T_440 = and(io.ptw.resp.bits.pte.v, T_439) - node T_441 = bits(io.ptw.resp.bits.pte.typ, 1, 1) - node T_442 = and(T_440, T_441) - node T_444 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_445 = and(T_442, T_444) - sx_array[r_refill_waddr] <= T_445 - dirty_array[r_refill_waddr] <= io.ptw.resp.bits.pte.d - skip - node T_447 = not(tag_cam.io.valid_bits) - node T_449 = eq(T_447, UInt<1>("h00")) - node has_invalid_entry = eq(T_449, UInt<1>("h00")) - node T_452 = not(tag_cam.io.valid_bits) - node T_453 = bits(T_452, 0, 0) - node T_454 = bits(T_452, 1, 1) - node T_455 = bits(T_452, 2, 2) - node T_456 = bits(T_452, 3, 3) - node T_457 = bits(T_452, 4, 4) - node T_458 = bits(T_452, 5, 5) - node T_459 = bits(T_452, 6, 6) - node T_460 = bits(T_452, 7, 7) - wire T_462 : UInt<1>[8] - T_462[0] <= T_453 - T_462[1] <= T_454 - T_462[2] <= T_455 - T_462[3] <= T_456 - T_462[4] <= T_457 - T_462[5] <= T_458 - T_462[6] <= T_459 - T_462[7] <= T_460 - node T_480 = mux(T_462[6], UInt<3>("h06"), UInt<3>("h07")) - node T_481 = mux(T_462[5], UInt<3>("h05"), T_480) - node T_482 = mux(T_462[4], UInt<3>("h04"), T_481) - node T_483 = mux(T_462[3], UInt<2>("h03"), T_482) - node T_484 = mux(T_462[2], UInt<2>("h02"), T_483) - node T_485 = mux(T_462[1], UInt<1>("h01"), T_484) - node invalid_entry = mux(T_462[0], UInt<1>("h00"), T_485) - reg T_488 : UInt<8>, clk - node T_490 = dshr(T_488, UInt<1>("h01")) - node T_491 = bits(T_490, 0, 0) - node T_492 = cat(UInt<1>("h01"), T_491) - node T_493 = dshr(T_488, T_492) - node T_494 = bits(T_493, 0, 0) - node T_495 = cat(T_492, T_494) - node T_496 = dshr(T_488, T_495) - node T_497 = bits(T_496, 0, 0) - node T_498 = cat(T_495, T_497) - node T_499 = bits(T_498, 2, 0) - node repl_waddr = mux(has_invalid_entry, invalid_entry, T_499) - node T_502 = eq(io.req.bits.instruction, UInt<1>("h00")) - node T_503 = and(io.ptw.status.mprv, T_502) - node priv = mux(T_503, io.ptw.status.prv1, io.ptw.status.prv) - node priv_s = eq(priv, UInt<1>("h01")) - node priv_uses_vm = leq(priv, UInt<1>("h01")) - node T_510 = eq(r_req.store, UInt<1>("h00")) - node T_511 = or(r_req.instruction, r_req.store) - node T_513 = eq(T_511, UInt<1>("h00")) - node T_514 = cat(r_req.store, T_513) - node req_xwr = cat(T_510, T_514) - node T_516 = cat(sr_array[7], sr_array[6]) - node T_517 = cat(sr_array[5], sr_array[4]) - node T_518 = cat(T_516, T_517) - node T_519 = cat(sr_array[3], sr_array[2]) - node T_520 = cat(sr_array[1], sr_array[0]) - node T_521 = cat(T_519, T_520) - node T_522 = cat(T_518, T_521) - node T_523 = cat(ur_array[7], ur_array[6]) - node T_524 = cat(ur_array[5], ur_array[4]) - node T_525 = cat(T_523, T_524) - node T_526 = cat(ur_array[3], ur_array[2]) - node T_527 = cat(ur_array[1], ur_array[0]) - node T_528 = cat(T_526, T_527) - node T_529 = cat(T_525, T_528) - node r_array = mux(priv_s, T_522, T_529) - node T_531 = cat(sw_array[7], sw_array[6]) - node T_532 = cat(sw_array[5], sw_array[4]) - node T_533 = cat(T_531, T_532) - node T_534 = cat(sw_array[3], sw_array[2]) - node T_535 = cat(sw_array[1], sw_array[0]) - node T_536 = cat(T_534, T_535) - node T_537 = cat(T_533, T_536) - node T_538 = cat(uw_array[7], uw_array[6]) - node T_539 = cat(uw_array[5], uw_array[4]) - node T_540 = cat(T_538, T_539) - node T_541 = cat(uw_array[3], uw_array[2]) - node T_542 = cat(uw_array[1], uw_array[0]) - node T_543 = cat(T_541, T_542) - node T_544 = cat(T_540, T_543) - node w_array = mux(priv_s, T_537, T_544) - node T_546 = cat(sx_array[7], sx_array[6]) - node T_547 = cat(sx_array[5], sx_array[4]) - node T_548 = cat(T_546, T_547) - node T_549 = cat(sx_array[3], sx_array[2]) - node T_550 = cat(sx_array[1], sx_array[0]) - node T_551 = cat(T_549, T_550) - node T_552 = cat(T_548, T_551) - node T_553 = cat(ux_array[7], ux_array[6]) - node T_554 = cat(ux_array[5], ux_array[4]) - node T_555 = cat(T_553, T_554) - node T_556 = cat(ux_array[3], ux_array[2]) - node T_557 = cat(ux_array[1], ux_array[0]) - node T_558 = cat(T_556, T_557) - node T_559 = cat(T_555, T_558) - node x_array = mux(priv_s, T_552, T_559) - node T_561 = bits(io.ptw.status.vm, 3, 3) - node T_562 = and(T_561, priv_uses_vm) - node T_564 = eq(io.req.bits.passthrough, UInt<1>("h00")) - node vm_enabled = and(T_562, T_564) - node T_566 = bits(io.req.bits.vpn, 27, 27) - node T_567 = bits(io.req.bits.vpn, 26, 26) - node bad_va = neq(T_566, T_567) - node T_569 = cat(dirty_array[7], dirty_array[6]) - node T_570 = cat(dirty_array[5], dirty_array[4]) - node T_571 = cat(T_569, T_570) - node T_572 = cat(dirty_array[3], dirty_array[2]) - node T_573 = cat(dirty_array[1], dirty_array[0]) - node T_574 = cat(T_572, T_573) - node T_575 = cat(T_571, T_574) - node T_577 = mux(io.req.bits.store, w_array, UInt<1>("h00")) - node T_578 = not(T_577) - node T_579 = or(T_575, T_578) - node tag_hits = and(tag_cam.io.hits, T_579) - node tag_hit = neq(tag_hits, UInt<1>("h00")) - node tlb_hit = and(vm_enabled, tag_hit) - node T_585 = eq(tag_hit, UInt<1>("h00")) - node T_586 = and(vm_enabled, T_585) - node T_588 = eq(bad_va, UInt<1>("h00")) - node tlb_miss = and(T_586, T_588) - node T_590 = and(io.req.valid, tlb_hit) - when T_590 : - node T_591 = bits(tag_cam.io.hits, 7, 4) - node T_592 = bits(tag_cam.io.hits, 3, 0) - node T_594 = neq(T_591, UInt<1>("h00")) - node T_595 = or(T_591, T_592) - node T_596 = bits(T_595, 3, 2) - node T_597 = bits(T_595, 1, 0) - node T_599 = neq(T_596, UInt<1>("h00")) - node T_600 = or(T_596, T_597) - node T_601 = bits(T_600, 1, 1) - node T_602 = cat(T_599, T_601) - node T_603 = cat(T_594, T_602) - node T_605 = bits(T_603, 2, 2) - node T_607 = dshl(UInt<8>("h01"), UInt<1>("h01")) - node T_608 = bits(T_607, 7, 0) - node T_609 = not(T_608) - node T_610 = and(T_488, T_609) - node T_612 = mux(T_605, UInt<1>("h00"), T_608) - node T_613 = or(T_610, T_612) - node T_614 = cat(UInt<1>("h01"), T_605) - node T_615 = bits(T_603, 1, 1) - node T_617 = dshl(UInt<8>("h01"), T_614) - node T_618 = bits(T_617, 7, 0) - node T_619 = not(T_618) - node T_620 = and(T_613, T_619) - node T_622 = mux(T_615, UInt<1>("h00"), T_618) - node T_623 = or(T_620, T_622) - node T_624 = cat(T_614, T_615) - node T_625 = bits(T_603, 0, 0) - node T_627 = dshl(UInt<8>("h01"), T_624) - node T_628 = bits(T_627, 7, 0) - node T_629 = not(T_628) - node T_630 = and(T_623, T_629) - node T_632 = mux(T_625, UInt<1>("h00"), T_628) - node T_633 = or(T_630, T_632) - node T_634 = cat(T_624, T_625) - T_488 <= T_633 - skip - node paddr = cat(io.resp.ppn, UInt<12>("h00")) - node T_638 = geq(paddr, UInt<1>("h00")) - node T_640 = lt(paddr, UInt<31>("h040000000")) - node T_641 = and(T_638, T_640) - node T_643 = geq(paddr, UInt<31>("h040000000")) - node T_645 = lt(paddr, UInt<31>("h040008000")) - node T_646 = and(T_643, T_645) - node T_648 = geq(paddr, UInt<31>("h040008000")) - node T_650 = lt(paddr, UInt<31>("h040010000")) - node T_651 = and(T_648, T_650) - node T_653 = geq(paddr, UInt<31>("h040010000")) - node T_655 = lt(paddr, UInt<31>("h040010200")) - node T_656 = and(T_653, T_655) - node T_658 = geq(paddr, UInt<32>("h080000000")) - node T_660 = lt(paddr, UInt<33>("h0100000000")) - node T_661 = and(T_658, T_660) - node T_662 = or(T_641, T_646) - node T_663 = or(T_662, T_651) - node T_664 = or(T_663, T_656) - node addr_ok = or(T_664, T_661) - node T_667 = geq(paddr, UInt<1>("h00")) - node T_669 = lt(paddr, UInt<31>("h040000000")) - node T_670 = and(T_667, T_669) - wire T_680 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_680 is invalid - T_680.r <= UInt<1>("h01") - T_680.w <= UInt<1>("h01") - T_680.x <= UInt<1>("h01") - node T_688 = geq(paddr, UInt<31>("h040000000")) - node T_690 = lt(paddr, UInt<31>("h040008000")) - node T_691 = and(T_688, T_690) - wire T_701 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_701 is invalid - T_701.r <= UInt<1>("h01") - T_701.w <= UInt<1>("h00") - T_701.x <= UInt<1>("h00") - node T_709 = geq(paddr, UInt<31>("h040008000")) - node T_711 = lt(paddr, UInt<31>("h040010000")) - node T_712 = and(T_709, T_711) - wire T_722 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_722 is invalid - T_722.r <= UInt<1>("h01") - T_722.w <= UInt<1>("h01") - T_722.x <= UInt<1>("h00") - node T_730 = geq(paddr, UInt<31>("h040010000")) - node T_732 = lt(paddr, UInt<31>("h040010200")) - node T_733 = and(T_730, T_732) - wire T_743 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_743 is invalid - T_743.r <= UInt<1>("h01") - T_743.w <= UInt<1>("h01") - T_743.x <= UInt<1>("h00") - node T_751 = geq(paddr, UInt<32>("h080000000")) - node T_753 = lt(paddr, UInt<33>("h0100000000")) - node T_754 = and(T_751, T_753) - wire T_764 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_764 is invalid - T_764.r <= UInt<1>("h01") - T_764.w <= UInt<1>("h01") - T_764.x <= UInt<1>("h00") - node T_771 = cat(T_680.w, T_680.r) - node T_772 = cat(T_680.x, T_771) - node T_774 = mux(T_670, T_772, UInt<1>("h00")) - node T_775 = cat(T_701.w, T_701.r) - node T_776 = cat(T_701.x, T_775) - node T_778 = mux(T_691, T_776, UInt<1>("h00")) - node T_779 = cat(T_722.w, T_722.r) - node T_780 = cat(T_722.x, T_779) - node T_782 = mux(T_712, T_780, UInt<1>("h00")) - node T_783 = cat(T_743.w, T_743.r) - node T_784 = cat(T_743.x, T_783) - node T_786 = mux(T_733, T_784, UInt<1>("h00")) - node T_787 = cat(T_764.w, T_764.r) - node T_788 = cat(T_764.x, T_787) - node T_790 = mux(T_754, T_788, UInt<1>("h00")) - node T_795 = or(T_774, T_778) - node T_796 = or(T_795, T_782) - node T_797 = or(T_796, T_786) - node T_798 = or(T_797, T_790) - wire addr_prot : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - addr_prot is invalid - node T_807 = bits(T_798, 0, 0) - addr_prot.r <= T_807 - node T_808 = bits(T_798, 1, 1) - addr_prot.w <= T_808 - node T_809 = bits(T_798, 2, 2) - addr_prot.x <= T_809 - node T_810 = eq(state, UInt<1>("h00")) - io.req.ready <= T_810 - node T_812 = eq(addr_ok, UInt<1>("h00")) - node T_814 = eq(addr_prot.r, UInt<1>("h00")) - node T_815 = or(T_812, T_814) - node T_816 = or(T_815, bad_va) - node T_817 = and(r_array, tag_cam.io.hits) - node T_819 = neq(T_817, UInt<1>("h00")) - node T_821 = eq(T_819, UInt<1>("h00")) - node T_822 = and(tlb_hit, T_821) - node T_823 = or(T_816, T_822) - io.resp.xcpt_ld <= T_823 - node T_825 = eq(addr_ok, UInt<1>("h00")) - node T_827 = eq(addr_prot.w, UInt<1>("h00")) - node T_828 = or(T_825, T_827) - node T_829 = or(T_828, bad_va) - node T_830 = and(w_array, tag_cam.io.hits) - node T_832 = neq(T_830, UInt<1>("h00")) - node T_834 = eq(T_832, UInt<1>("h00")) - node T_835 = and(tlb_hit, T_834) - node T_836 = or(T_829, T_835) - io.resp.xcpt_st <= T_836 - node T_838 = eq(addr_ok, UInt<1>("h00")) - node T_840 = eq(addr_prot.x, UInt<1>("h00")) - node T_841 = or(T_838, T_840) - node T_842 = or(T_841, bad_va) - node T_843 = and(x_array, tag_cam.io.hits) - node T_845 = neq(T_843, UInt<1>("h00")) - node T_847 = eq(T_845, UInt<1>("h00")) - node T_848 = and(tlb_hit, T_847) - node T_849 = or(T_842, T_848) - io.resp.xcpt_if <= T_849 - io.resp.miss <= tlb_miss - node T_850 = bits(tag_cam.io.hits, 0, 0) - node T_851 = bits(tag_cam.io.hits, 1, 1) - node T_852 = bits(tag_cam.io.hits, 2, 2) - node T_853 = bits(tag_cam.io.hits, 3, 3) - node T_854 = bits(tag_cam.io.hits, 4, 4) - node T_855 = bits(tag_cam.io.hits, 5, 5) - node T_856 = bits(tag_cam.io.hits, 6, 6) - node T_857 = bits(tag_cam.io.hits, 7, 7) - infer mport T_859 = tag_ram[UInt<1>("h00")], clk - infer mport T_861 = tag_ram[UInt<1>("h01")], clk - infer mport T_863 = tag_ram[UInt<2>("h02")], clk - infer mport T_865 = tag_ram[UInt<2>("h03")], clk - infer mport T_867 = tag_ram[UInt<3>("h04")], clk - infer mport T_869 = tag_ram[UInt<3>("h05")], clk - infer mport T_871 = tag_ram[UInt<3>("h06")], clk - infer mport T_873 = tag_ram[UInt<3>("h07")], clk - node T_875 = mux(T_850, T_859, UInt<1>("h00")) - node T_877 = mux(T_851, T_861, UInt<1>("h00")) - node T_879 = mux(T_852, T_863, UInt<1>("h00")) - node T_881 = mux(T_853, T_865, UInt<1>("h00")) - node T_883 = mux(T_854, T_867, UInt<1>("h00")) - node T_885 = mux(T_855, T_869, UInt<1>("h00")) - node T_887 = mux(T_856, T_871, UInt<1>("h00")) - node T_889 = mux(T_857, T_873, UInt<1>("h00")) - node T_891 = or(T_875, T_877) - node T_892 = or(T_891, T_879) - node T_893 = or(T_892, T_881) - node T_894 = or(T_893, T_883) - node T_895 = or(T_894, T_885) - node T_896 = or(T_895, T_887) - node T_897 = or(T_896, T_889) - wire T_898 : UInt<20> - T_898 is invalid - T_898 <= T_897 - node T_899 = bits(io.req.bits.vpn, 19, 0) - node T_900 = mux(vm_enabled, T_898, T_899) - io.resp.ppn <= T_900 - io.resp.hit_idx <= tag_cam.io.hits - node T_901 = and(io.req.ready, io.req.valid) - node T_902 = or(io.ptw.invalidate, T_901) - tag_cam.io.clear <= T_902 - node T_903 = cat(valid_array[7], valid_array[6]) - node T_904 = cat(valid_array[5], valid_array[4]) - node T_905 = cat(T_903, T_904) - node T_906 = cat(valid_array[3], valid_array[2]) - node T_907 = cat(valid_array[1], valid_array[0]) - node T_908 = cat(T_906, T_907) - node T_909 = cat(T_905, T_908) - node T_910 = not(T_909) - node T_911 = not(tag_hits) - node T_912 = and(tag_cam.io.hits, T_911) - node T_913 = or(T_910, T_912) - tag_cam.io.clear_mask <= T_913 - when io.ptw.invalidate : - node T_915 = not(UInt<8>("h00")) - tag_cam.io.clear_mask <= T_915 - skip - node T_916 = eq(state, UInt<1>("h01")) - io.ptw.req.valid <= T_916 - io.ptw.req.bits.addr <= r_refill_tag - io.ptw.req.bits.prv <= io.ptw.status.prv - io.ptw.req.bits.store <= r_req.store - io.ptw.req.bits.fetch <= r_req.instruction - node T_917 = and(io.req.ready, io.req.valid) - node T_918 = and(T_917, tlb_miss) - when T_918 : - state <= UInt<1>("h01") - r_refill_tag <= lookup_tag - r_refill_waddr <= repl_waddr - r_req <- io.req.bits - skip - node T_919 = eq(state, UInt<1>("h01")) - when T_919 : - when io.ptw.invalidate : - state <= UInt<1>("h00") - skip - when io.ptw.req.ready : - state <= UInt<2>("h02") - when io.ptw.invalidate : - state <= UInt<2>("h03") - skip - skip - skip - node T_920 = eq(state, UInt<2>("h02")) - node T_921 = and(T_920, io.ptw.invalidate) - when T_921 : - state <= UInt<2>("h03") - skip - when io.ptw.resp.valid : - state <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module Queue_92 : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_31 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_32 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_32 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, count : UInt<1>} - - io is invalid - cmem ram : {data : UInt<32>, datablock : UInt<128>}[1] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_463 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_463) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_469 = and(io.enq.ready, io.enq.valid) - node T_471 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_469, T_471) - node T_473 = and(io.deq.ready, io.deq.valid) - node T_475 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_473, T_475) - when do_enq : - infer mport T_477 = ram[UInt<1>("h00")], clk - T_477 <- io.enq.bits - skip - when do_deq : - skip - node T_528 = neq(do_enq, do_deq) - when T_528 : - maybe_full <= do_enq - skip - node T_530 = eq(empty, UInt<1>("h00")) - node T_532 = and(UInt<1>("h00"), io.enq.valid) - node T_533 = or(T_530, T_532) - io.deq.valid <= T_533 - node T_535 = eq(full, UInt<1>("h00")) - node T_537 = and(UInt<1>("h01"), io.deq.ready) - node T_538 = or(T_535, T_537) - io.enq.ready <= T_538 - infer mport T_539 = ram[UInt<1>("h00")], clk - node T_588 = mux(maybe_flow, io.enq.bits, T_539) - io.deq.bits <- T_588 - node T_637 = sub(UInt<1>("h00"), UInt<1>("h00")) - node ptr_diff = tail(T_637, 1) - node T_639 = and(maybe_full, ptr_match) - node T_640 = cat(T_639, ptr_diff) - io.count <= T_640 - - module Frontend : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_32 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_33 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_33 : + input clock : Clock input reset : UInt<1> - output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - inst btb of BTB - btb.io is invalid - btb.clk <= clk - btb.reset <= reset - inst icache of ICache - icache.io is invalid - icache.clk <= clk - icache.reset <= reset - inst tlb of TLB - tlb.io is invalid - tlb.clk <= clk - tlb.reset <= reset - reg s1_pc_ : UInt, clk - node T_1280 = not(s1_pc_) - node T_1282 = or(T_1280, UInt<2>("h03")) - node s1_pc = not(T_1282) - reg s1_same_block : UInt<1>, clk - reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - reg s2_pc : UInt, clk with : (reset => (reset, UInt<10>("h0200"))) - reg s2_btb_resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg s2_xcpt_if : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire s2_resp_valid : UInt<1> - s2_resp_valid <= UInt<1>("h00") - wire s2_resp_data : UInt<128> - s2_resp_data is invalid - node T_1307 = bits(btb.io.resp.bits.target, 38, 38) - node btbTarget = cat(T_1307, btb.io.resp.bits.target) - node T_1310 = add(s1_pc, UInt<3>("h04")) - node ntpc_0 = tail(T_1310, 1) - node T_1312 = bits(s1_pc, 38, 38) - node T_1313 = bits(ntpc_0, 38, 38) - node T_1314 = and(T_1312, T_1313) - node T_1315 = bits(ntpc_0, 38, 2) - node T_1317 = cat(T_1315, UInt<2>("h00")) - node ntpc = cat(T_1314, T_1317) - node T_1320 = eq(s2_resp_valid, UInt<1>("h00")) - node icmiss = and(s2_valid, T_1320) - node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc) - node npc = mux(icmiss, s2_pc, predicted_npc) - node T_1325 = eq(icmiss, UInt<1>("h00")) - node T_1327 = eq(io.cpu.req.valid, UInt<1>("h00")) - node T_1328 = and(T_1325, T_1327) - node T_1330 = eq(btb.io.resp.bits.taken, UInt<1>("h00")) - node T_1331 = and(T_1328, T_1330) - node T_1333 = and(ntpc, UInt<5>("h010")) - node T_1335 = and(s1_pc, UInt<5>("h010")) - node T_1336 = eq(T_1333, T_1335) - node s0_same_block = and(T_1331, T_1336) - node T_1339 = eq(io.cpu.resp.ready, UInt<1>("h00")) - node stall = and(io.cpu.resp.valid, T_1339) - node T_1342 = eq(stall, UInt<1>("h00")) - when T_1342 : - node T_1344 = eq(tlb.io.resp.miss, UInt<1>("h00")) - node T_1345 = and(s0_same_block, T_1344) - s1_same_block <= T_1345 - s1_pc_ <= npc - node T_1347 = eq(icmiss, UInt<1>("h00")) - s2_valid <= T_1347 - node T_1349 = eq(icmiss, UInt<1>("h00")) - when T_1349 : - s2_pc <= s1_pc - s2_btb_resp_valid <= btb.io.resp.valid - when btb.io.resp.valid : - s2_btb_resp_bits <- btb.io.resp.bits - skip - s2_xcpt_if <= tlb.io.resp.xcpt_if - skip - skip - when io.cpu.req.valid : - s1_same_block <= UInt<1>("h00") - s1_pc_ <= io.cpu.req.bits.pc - s2_valid <= UInt<1>("h00") - skip - node T_1353 = eq(stall, UInt<1>("h00")) - node T_1355 = eq(icmiss, UInt<1>("h00")) - node T_1356 = and(T_1353, T_1355) - btb.io.req.valid <= T_1356 - btb.io.req.bits.addr <= s1_pc - btb.io.btb_update <- io.cpu.btb_update - btb.io.bht_update <- io.cpu.bht_update - btb.io.ras_update <- io.cpu.ras_update - node T_1357 = or(io.cpu.invalidate, io.ptw.invalidate) - btb.io.invalidate <= T_1357 - io.ptw <- tlb.io.ptw - node T_1359 = eq(stall, UInt<1>("h00")) - node T_1361 = eq(icmiss, UInt<1>("h00")) - node T_1362 = and(T_1359, T_1361) - tlb.io.req.valid <= T_1362 - node T_1363 = shr(s1_pc, 12) - tlb.io.req.bits.vpn <= T_1363 - tlb.io.req.bits.asid <= UInt<1>("h00") - tlb.io.req.bits.passthrough <= UInt<1>("h00") - tlb.io.req.bits.instruction <= UInt<1>("h01") - tlb.io.req.bits.store <= UInt<1>("h00") - io.mem <- icache.io.mem - node T_1369 = eq(stall, UInt<1>("h00")) - node T_1371 = eq(s0_same_block, UInt<1>("h00")) - node T_1372 = and(T_1369, T_1371) - icache.io.req.valid <= T_1372 - icache.io.req.bits.idx <= io.cpu.npc - icache.io.invalidate <= io.cpu.invalidate - icache.io.req.bits.ppn <= tlb.io.resp.ppn - node T_1373 = or(io.cpu.req.valid, tlb.io.resp.miss) - node T_1374 = or(T_1373, tlb.io.resp.xcpt_if) - node T_1375 = or(T_1374, icmiss) - node T_1376 = or(T_1375, io.ptw.invalidate) - icache.io.req.bits.kill <= T_1376 - node T_1377 = or(s2_xcpt_if, s2_resp_valid) - node T_1378 = and(s2_valid, T_1377) - io.cpu.resp.valid <= T_1378 - io.cpu.resp.bits.pc <= s2_pc - node T_1379 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) - io.cpu.npc <= T_1379 - inst T_1429 of Queue_92 - T_1429.io is invalid - T_1429.clk <= clk - T_1429.reset <= reset - T_1429.io.enq <- icache.io.resp - node T_1431 = eq(stall, UInt<1>("h00")) - node T_1433 = eq(s1_same_block, UInt<1>("h00")) - node T_1434 = and(T_1431, T_1433) - T_1429.io.deq.ready <= T_1434 - s2_resp_valid <= T_1429.io.deq.valid - s2_resp_data <= T_1429.io.deq.bits.datablock - node T_1435 = bits(s2_pc, 3, 2) - node T_1436 = shl(T_1435, 5) - node fetch_data = dshr(s2_resp_data, T_1436) - node T_1438 = bits(fetch_data, 31, 0) - io.cpu.resp.bits.data[0] <= T_1438 - node T_1440 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) - node T_1441 = mux(s2_btb_resp_valid, T_1440, UInt<2>("h03")) - io.cpu.resp.bits.mask <= T_1441 - io.cpu.resp.bits.xcpt_if <= s2_xcpt_if - io.cpu.btb_resp.valid <= s2_btb_resp_valid - io.cpu.btb_resp.bits <- s2_btb_resp_bits - - module WritebackUnit : + io is invalid + inst reg_0 of AsyncResetReg_33 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_34 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_34 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - - io is invalid - reg active : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg r1_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg r2_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg data_req_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - node T_476 = not(UInt<1>("h01")) - node beat_done = eq(T_476, UInt<1>("h00")) - node T_479 = and(io.release.ready, io.release.valid) - reg beat_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_479 : - node T_483 = eq(beat_cnt, UInt<2>("h03")) - node T_485 = and(UInt<1>("h00"), T_483) - node T_488 = add(beat_cnt, UInt<1>("h01")) - node T_489 = tail(T_488, 1) - node T_490 = mux(T_485, UInt<1>("h00"), T_489) - beat_cnt <= T_490 - skip - node all_beats_done = and(T_479, T_483) - reg req : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk - io.release.valid <= UInt<1>("h00") - when active : - r1_data_req_fired <= UInt<1>("h00") - r2_data_req_fired <= r1_data_req_fired - node T_556 = and(io.data_req.ready, io.data_req.valid) - node T_557 = and(io.meta_read.ready, io.meta_read.valid) - node T_558 = and(T_556, T_557) - when T_558 : - r1_data_req_fired <= UInt<1>("h01") - node T_561 = add(data_req_cnt, UInt<1>("h01")) - node T_562 = tail(T_561, 1) - data_req_cnt <= T_562 - skip - when r2_data_req_fired : - io.release.valid <= beat_done - when beat_done : - node T_564 = eq(io.release.ready, UInt<1>("h00")) - when T_564 : - r1_data_req_fired <= UInt<1>("h00") - r2_data_req_fired <= UInt<1>("h00") - node T_568 = and(UInt<1>("h01"), r1_data_req_fired) - node T_571 = mux(T_568, UInt<2>("h02"), UInt<1>("h01")) - node T_572 = sub(data_req_cnt, T_571) - node T_573 = tail(T_572, 1) - data_req_cnt <= T_573 - skip - node T_575 = eq(T_564, UInt<1>("h00")) - when T_575 : - skip - skip - node T_577 = eq(r1_data_req_fired, UInt<1>("h00")) - when T_577 : - node T_579 = lt(data_req_cnt, UInt<3>("h04")) - node T_581 = eq(io.release.ready, UInt<1>("h00")) - node T_582 = or(T_579, T_581) - active <= T_582 - skip - skip - skip - node T_583 = and(io.req.ready, io.req.valid) - when T_583 : - active <= UInt<1>("h01") - data_req_cnt <= UInt<1>("h00") - req <- io.req.bits - skip - node T_587 = eq(active, UInt<1>("h00")) - io.req.ready <= T_587 - node req_idx = bits(req.addr_block, 5, 0) - node T_590 = lt(data_req_cnt, UInt<3>("h04")) - node fire = and(active, T_590) - io.meta_read.valid <= fire - io.meta_read.bits.idx <= req_idx - node T_592 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_592 - io.data_req.valid <= fire - io.data_req.bits.way_en <= req.way_en - node T_593 = bits(data_req_cnt, 1, 0) - node T_594 = cat(req_idx, T_593) - node T_595 = shl(T_594, 4) - io.data_req.bits.addr <= T_595 - io.release.bits <- req - io.release.bits.addr_beat <= beat_cnt - io.release.bits.data <= io.data_resp - - module ProbeUnit : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_34 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_35 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_35 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg old_coh : {state : UInt<2>}, clk - reg way_en : UInt, clk - reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk - node tag_matches = neq(way_en, UInt<1>("h00")) - wire miss_coh : {state : UInt<2>} - miss_coh is invalid - miss_coh.state <= UInt<1>("h00") - node reply_coh = mux(tag_matches, old_coh, miss_coh) - wire T_947 : UInt<2>[1] - T_947[0] <= UInt<2>("h03") - node T_950 = eq(T_947[0], reply_coh.state) - node T_952 = or(UInt<1>("h00"), T_950) - node T_953 = mux(T_952, UInt<1>("h00"), UInt<2>("h03")) - node T_954 = mux(T_952, UInt<1>("h01"), UInt<3>("h04")) - node T_955 = mux(T_952, UInt<2>("h02"), UInt<3>("h05")) - node T_956 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_957 = mux(T_956, T_955, UInt<3>("h05")) - node T_958 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_959 = mux(T_958, T_954, T_957) - node T_960 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_961 = mux(T_960, T_953, T_959) - wire T_963 : UInt<2>[1] - T_963[0] <= UInt<2>("h03") - node T_966 = eq(T_963[0], reply_coh.state) - node T_968 = or(UInt<1>("h00"), T_966) - node T_969 = mux(T_968, UInt<1>("h00"), UInt<2>("h03")) - node T_970 = mux(T_968, UInt<1>("h01"), UInt<3>("h04")) - node T_971 = mux(T_968, UInt<2>("h02"), UInt<3>("h05")) - node T_972 = eq(UInt<5>("h013"), UInt<5>("h011")) - node T_973 = mux(T_972, T_971, UInt<3>("h05")) - node T_974 = eq(UInt<5>("h011"), UInt<5>("h011")) - node T_975 = mux(T_974, T_970, T_973) - node T_976 = eq(UInt<5>("h010"), UInt<5>("h011")) - node T_977 = mux(T_976, T_969, T_975) - wire T_979 : UInt<2>[1] - T_979[0] <= UInt<2>("h03") - node T_982 = eq(T_979[0], reply_coh.state) - node T_984 = or(UInt<1>("h00"), T_982) - node T_985 = mux(T_984, UInt<1>("h00"), UInt<2>("h03")) - node T_986 = mux(T_984, UInt<1>("h01"), UInt<3>("h04")) - node T_987 = mux(T_984, UInt<2>("h02"), UInt<3>("h05")) - node T_988 = eq(UInt<5>("h013"), UInt<5>("h013")) - node T_989 = mux(T_988, T_987, UInt<3>("h05")) - node T_990 = eq(UInt<5>("h011"), UInt<5>("h013")) - node T_991 = mux(T_990, T_986, T_989) - node T_992 = eq(UInt<5>("h010"), UInt<5>("h013")) - node T_993 = mux(T_992, T_985, T_991) - node T_994 = eq(UInt<2>("h02"), req.p_type) - node T_995 = mux(T_994, T_993, UInt<2>("h03")) - node T_996 = eq(UInt<1>("h01"), req.p_type) - node T_997 = mux(T_996, T_977, T_995) - node T_998 = eq(UInt<1>("h00"), req.p_type) - node T_999 = mux(T_998, T_961, T_997) - wire reply : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - reply is invalid - reply.r_type <= T_999 - reply.client_xact_id <= UInt<1>("h00") - reply.addr_block <= req.addr_block - reply.addr_beat <= UInt<1>("h00") - reply.data <= UInt<1>("h00") - reply.voluntary <= UInt<1>("h00") - node T_1061 = eq(state, UInt<1>("h00")) - io.req.ready <= T_1061 - node T_1062 = eq(state, UInt<3>("h05")) - io.rep.valid <= T_1062 - io.rep.bits <- reply - node T_1064 = eq(io.rep.valid, UInt<1>("h00")) - wire T_1066 : UInt<2>[3] - T_1066[0] <= UInt<1>("h00") - T_1066[1] <= UInt<1>("h01") - T_1066[2] <= UInt<2>("h02") - node T_1071 = eq(T_1066[0], io.rep.bits.r_type) - node T_1072 = eq(T_1066[1], io.rep.bits.r_type) - node T_1073 = eq(T_1066[2], io.rep.bits.r_type) - node T_1075 = or(UInt<1>("h00"), T_1071) - node T_1076 = or(T_1075, T_1072) - node T_1077 = or(T_1076, T_1073) - node T_1079 = eq(T_1077, UInt<1>("h00")) - node T_1080 = or(T_1064, T_1079) - node T_1082 = eq(reset, UInt<1>("h00")) - when T_1082 : - node T_1084 = eq(T_1080, UInt<1>("h00")) - when T_1084 : - node T_1086 = eq(reset, UInt<1>("h00")) - when T_1086 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1087 = eq(state, UInt<1>("h01")) - io.meta_read.valid <= T_1087 - io.meta_read.bits.idx <= req.addr_block - node T_1088 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_1088 - node T_1089 = eq(state, UInt<4>("h08")) - io.meta_write.valid <= T_1089 - io.meta_write.bits.way_en <= way_en - io.meta_write.bits.idx <= req.addr_block - node T_1090 = shr(req.addr_block, 6) - io.meta_write.bits.data.tag <= T_1090 - node T_1091 = eq(UInt<2>("h02"), req.p_type) - node T_1092 = mux(T_1091, old_coh.state, old_coh.state) - node T_1093 = eq(UInt<1>("h01"), req.p_type) - node T_1094 = mux(T_1093, UInt<1>("h01"), T_1092) - node T_1095 = eq(UInt<1>("h00"), req.p_type) - node T_1096 = mux(T_1095, UInt<1>("h00"), T_1094) - wire T_1122 : {state : UInt<2>} - T_1122 is invalid - T_1122.state <= T_1096 - io.meta_write.bits.data.coh <- T_1122 - node T_1147 = eq(state, UInt<3>("h06")) - io.wb_req.valid <= T_1147 - io.wb_req.bits <- reply - io.wb_req.bits.way_en <= way_en - node T_1148 = and(io.req.ready, io.req.valid) - when T_1148 : - state <= UInt<1>("h01") - req <- io.req.bits - skip - node T_1149 = and(io.meta_read.ready, io.meta_read.valid) - when T_1149 : - state <= UInt<2>("h02") - skip - node T_1150 = eq(state, UInt<2>("h02")) - when T_1150 : - state <= UInt<2>("h03") - skip - node T_1151 = eq(state, UInt<2>("h03")) - when T_1151 : - state <= UInt<3>("h04") - old_coh <- io.block_state - way_en <= io.way_en - node T_1153 = eq(io.mshr_rdy, UInt<1>("h00")) - when T_1153 : - state <= UInt<1>("h01") - skip - skip - node T_1154 = eq(state, UInt<3>("h04")) - when T_1154 : - wire T_1156 : UInt<2>[1] - T_1156[0] <= UInt<2>("h03") - node T_1159 = eq(T_1156[0], old_coh.state) - node T_1161 = or(UInt<1>("h00"), T_1159) - node T_1162 = and(tag_matches, T_1161) - node T_1163 = mux(T_1162, UInt<3>("h06"), UInt<3>("h05")) - state <= T_1163 - skip - node T_1164 = eq(state, UInt<3>("h05")) - node T_1165 = and(T_1164, io.rep.ready) - when T_1165 : - node T_1166 = mux(tag_matches, UInt<4>("h08"), UInt<1>("h00")) - state <= T_1166 - skip - node T_1167 = and(io.wb_req.ready, io.wb_req.valid) - when T_1167 : - state <= UInt<3>("h07") - skip - node T_1168 = eq(state, UInt<3>("h07")) - node T_1169 = and(T_1168, io.wb_req.ready) - when T_1169 : - state <= UInt<4>("h08") - skip - node T_1170 = and(io.meta_write.ready, io.meta_write.valid) - when T_1170 : - state <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module Arbiter_93 : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_35 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_36 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_36 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>} - - io is invalid - wire T_108 : UInt<1> - T_108 is invalid - io.out.valid <= io.in[T_108].valid - io.out.bits <- io.in[T_108].bits - io.chosen <= T_108 - io.in[T_108].ready <= UInt<1>("h00") - node T_139 = or(UInt<1>("h00"), io.in[0].valid) - node T_141 = eq(T_139, UInt<1>("h00")) - node T_143 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_144 = mux(UInt<1>("h00"), T_143, UInt<1>("h01")) - node T_145 = and(T_144, io.out.ready) - io.in[0].ready <= T_145 - node T_147 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_148 = mux(UInt<1>("h00"), T_147, T_141) - node T_149 = and(T_148, io.out.ready) - io.in[1].ready <= T_149 - node T_152 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_153 = mux(UInt<1>("h00"), UInt<1>("h01"), T_152) - T_108 <= T_153 - - module Arbiter_94 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_36 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_37 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_37 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<1>} - - io is invalid - wire T_1714 : UInt<1> - T_1714 is invalid - io.out.valid <= io.in[T_1714].valid - io.out.bits <- io.in[T_1714].bits - io.chosen <= T_1714 - io.in[T_1714].ready <= UInt<1>("h00") - node T_2183 = or(UInt<1>("h00"), io.in[0].valid) - node T_2185 = eq(T_2183, UInt<1>("h00")) - node T_2187 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2188 = mux(UInt<1>("h00"), T_2187, UInt<1>("h01")) - node T_2189 = and(T_2188, io.out.ready) - io.in[0].ready <= T_2189 - node T_2191 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_2192 = mux(UInt<1>("h00"), T_2191, T_2185) - node T_2193 = and(T_2192, io.out.ready) - io.in[1].ready <= T_2193 - node T_2196 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_2197 = mux(UInt<1>("h00"), UInt<1>("h01"), T_2196) - T_1714 <= T_2197 - - module LockingArbiter : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_37 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_38 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_38 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<2>} - - io is invalid - reg T_852 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_854 : UInt, clk with : (reset => (reset, UInt<2>("h02"))) - wire T_856 : UInt<2> - T_856 is invalid - io.out.valid <= io.in[T_856].valid - io.out.bits <- io.in[T_856].bits - io.chosen <= T_856 - io.in[T_856].ready <= UInt<1>("h00") - node T_1055 = or(UInt<1>("h00"), io.in[0].valid) - node T_1057 = eq(T_1055, UInt<1>("h00")) - node T_1059 = or(UInt<1>("h00"), io.in[0].valid) - node T_1060 = or(T_1059, io.in[1].valid) - node T_1062 = eq(T_1060, UInt<1>("h00")) - node T_1064 = eq(T_854, UInt<1>("h00")) - node T_1065 = mux(T_852, T_1064, UInt<1>("h01")) - node T_1066 = and(T_1065, io.out.ready) - io.in[0].ready <= T_1066 - node T_1068 = eq(T_854, UInt<1>("h01")) - node T_1069 = mux(T_852, T_1068, T_1057) - node T_1070 = and(T_1069, io.out.ready) - io.in[1].ready <= T_1070 - node T_1072 = eq(T_854, UInt<2>("h02")) - node T_1073 = mux(T_852, T_1072, T_1062) - node T_1074 = and(T_1073, io.out.ready) - io.in[2].ready <= T_1074 - reg T_1076 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_1078 = add(T_1076, UInt<1>("h01")) - node T_1079 = tail(T_1078, 1) - node T_1080 = and(io.out.ready, io.out.valid) - when T_1080 : - node T_1082 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) - wire T_1085 : UInt<3>[1] - T_1085[0] <= UInt<3>("h03") - node T_1088 = eq(T_1085[0], io.out.bits.a_type) - node T_1090 = or(UInt<1>("h00"), T_1088) - node T_1091 = and(T_1082, T_1090) - when T_1091 : - T_1076 <= T_1079 - node T_1093 = eq(T_852, UInt<1>("h00")) - when T_1093 : - T_852 <= UInt<1>("h01") - node T_1095 = and(io.in[0].ready, io.in[0].valid) - node T_1096 = and(io.in[1].ready, io.in[1].valid) - node T_1097 = and(io.in[2].ready, io.in[2].valid) - wire T_1099 : UInt<1>[3] - T_1099[0] <= T_1095 - T_1099[1] <= T_1096 - T_1099[2] <= T_1097 - node T_1107 = mux(T_1099[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1108 = mux(T_1099[0], UInt<1>("h00"), T_1107) - T_854 <= T_1108 - skip - skip - node T_1110 = eq(T_1079, UInt<1>("h00")) - when T_1110 : - T_852 <= UInt<1>("h00") - skip - skip - node T_1114 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node choose = mux(io.in[0].valid, UInt<1>("h00"), T_1114) - node T_1117 = mux(T_852, T_854, choose) - T_856 <= T_1117 + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_38 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_6 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<1>, out : UInt<1>} - module Arbiter_95 : + io is invalid + io is invalid + inst source_valid_sync_0 of AsyncResetRegVec_35 @[AsyncQueue.scala 18:14] + source_valid_sync_0.io is invalid + source_valid_sync_0.clock <= clock + source_valid_sync_0.reset <= reset + inst source_valid_sync_1 of AsyncResetRegVec_36 @[AsyncQueue.scala 18:14] + source_valid_sync_1.io is invalid + source_valid_sync_1.clock <= clock + source_valid_sync_1.reset <= reset + inst source_valid_sync_2 of AsyncResetRegVec_37 @[AsyncQueue.scala 18:14] + source_valid_sync_2.io is invalid + source_valid_sync_2.clock <= clock + source_valid_sync_2.reset <= reset + inst source_valid_sync_3 of AsyncResetRegVec_38 @[AsyncQueue.scala 18:14] + source_valid_sync_3.io is invalid + source_valid_sync_3.clock <= clock + source_valid_sync_3.reset <= reset + source_valid_sync_3.io.d <= io.in @[AsyncQueue.scala 20:21] + source_valid_sync_3.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + source_valid_sync_0.io.d <= source_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_1.io.d <= source_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_2.io.d <= source_valid_sync_3.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_10 = bits(source_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_10 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_39 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_39 : + input clock : Clock + input reset : UInt<1> + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_39 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_7 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, chosen : UInt<1>} - - io is invalid - wire T_724 : UInt<1> - T_724 is invalid - io.out.valid <= io.in[T_724].valid - io.out.bits <- io.in[T_724].bits - io.chosen <= T_724 - io.in[T_724].ready <= UInt<1>("h00") - node T_923 = or(UInt<1>("h00"), io.in[0].valid) - node T_925 = eq(T_923, UInt<1>("h00")) - node T_927 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_928 = mux(UInt<1>("h00"), T_927, UInt<1>("h01")) - node T_929 = and(T_928, io.out.ready) - io.in[0].ready <= T_929 - node T_931 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_932 = mux(UInt<1>("h00"), T_931, T_925) - node T_933 = and(T_932, io.out.ready) - io.in[1].ready <= T_933 - node T_936 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_937 = mux(UInt<1>("h00"), UInt<1>("h01"), T_936) - T_724 <= T_937 - - module Arbiter_96 : + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst sink_extend_sync_0 of AsyncResetRegVec_39 @[AsyncQueue.scala 18:14] + sink_extend_sync_0.io is invalid + sink_extend_sync_0.clock <= clock + sink_extend_sync_0.reset <= reset + sink_extend_sync_0.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_extend_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + node _T_7 = bits(sink_extend_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_7 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_40 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_40 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>} - - io is invalid - wire T_1230 : UInt<1> - T_1230 is invalid - io.out.valid <= io.in[T_1230].valid - io.out.bits <- io.in[T_1230].bits - io.chosen <= T_1230 - io.in[T_1230].ready <= UInt<1>("h00") - node T_1567 = or(UInt<1>("h00"), io.in[0].valid) - node T_1569 = eq(T_1567, UInt<1>("h00")) - node T_1571 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1572 = mux(UInt<1>("h00"), T_1571, UInt<1>("h01")) - node T_1573 = and(T_1572, io.out.ready) - io.in[0].ready <= T_1573 - node T_1575 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_1576 = mux(UInt<1>("h00"), T_1575, T_1569) - node T_1577 = and(T_1576, io.out.ready) - io.in[1].ready <= T_1577 - node T_1580 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_1581 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1580) - T_1230 <= T_1581 - - module Arbiter_97 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_40 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_41 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_41 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} - - io is invalid - wire T_64 : UInt<1> - T_64 is invalid - io.out.valid <= io.in[T_64].valid - io.out.bits <= io.in[T_64].bits - io.chosen <= T_64 - io.in[T_64].ready <= UInt<1>("h00") - node T_83 = or(UInt<1>("h00"), io.in[0].valid) - node T_85 = eq(T_83, UInt<1>("h00")) - node T_87 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_88 = mux(UInt<1>("h00"), T_87, UInt<1>("h01")) - node T_89 = and(T_88, io.out.ready) - io.in[0].ready <= T_89 - node T_91 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_92 = mux(UInt<1>("h00"), T_91, T_85) - node T_93 = and(T_92, io.out.ready) - io.in[1].ready <= T_93 - node T_96 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_97 = mux(UInt<1>("h00"), UInt<1>("h01"), T_96) - T_64 <= T_97 - - module Queue_98 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_41 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_42 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_42 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>} - - io is invalid - cmem ram : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16] - reg T_503 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg T_505 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_503, T_505) - node T_510 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_510) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_516 = and(io.enq.ready, io.enq.valid) - node T_518 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_516, T_518) - node T_520 = and(io.deq.ready, io.deq.valid) - node T_522 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_520, T_522) - when do_enq : - infer mport T_524 = ram[T_503], clk - T_524 <- io.enq.bits - node T_579 = eq(T_503, UInt<4>("h0f")) - node T_581 = and(UInt<1>("h00"), T_579) - node T_584 = add(T_503, UInt<1>("h01")) - node T_585 = tail(T_584, 1) - node T_586 = mux(T_581, UInt<1>("h00"), T_585) - T_503 <= T_586 - skip - when do_deq : - node T_588 = eq(T_505, UInt<4>("h0f")) - node T_590 = and(UInt<1>("h00"), T_588) - node T_593 = add(T_505, UInt<1>("h01")) - node T_594 = tail(T_593, 1) - node T_595 = mux(T_590, UInt<1>("h00"), T_594) - T_505 <= T_595 - skip - node T_596 = neq(do_enq, do_deq) - when T_596 : - maybe_full <= do_enq - skip - node T_598 = eq(empty, UInt<1>("h00")) - node T_600 = and(UInt<1>("h00"), io.enq.valid) - node T_601 = or(T_598, T_600) - io.deq.valid <= T_601 - node T_603 = eq(full, UInt<1>("h00")) - node T_605 = and(UInt<1>("h00"), io.deq.ready) - node T_606 = or(T_603, T_605) - io.enq.ready <= T_606 - infer mport T_607 = ram[T_505], clk - node T_661 = mux(maybe_flow, io.enq.bits, T_607) - io.deq.bits <- T_661 - node T_715 = sub(T_503, T_505) - node ptr_diff = tail(T_715, 1) - node T_717 = and(maybe_full, ptr_match) - node T_718 = cat(T_717, ptr_diff) - io.count <= T_718 - - module MSHR : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_42 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_8 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst sink_valid_sync_0 of AsyncResetRegVec_40 @[AsyncQueue.scala 18:14] + sink_valid_sync_0.io is invalid + sink_valid_sync_0.clock <= clock + sink_valid_sync_0.reset <= reset + inst sink_valid_sync_1 of AsyncResetRegVec_41 @[AsyncQueue.scala 18:14] + sink_valid_sync_1.io is invalid + sink_valid_sync_1.clock <= clock + sink_valid_sync_1.reset <= reset + inst sink_valid_sync_2 of AsyncResetRegVec_42 @[AsyncQueue.scala 18:14] + sink_valid_sync_2.io is invalid + sink_valid_sync_2.clock <= clock + sink_valid_sync_2.reset <= reset + sink_valid_sync_2.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + sink_valid_sync_0.io.d <= sink_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_1.io.d <= sink_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_9 = bits(sink_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_9 @[AsyncQueue.scala 35:10] + + module AsyncQueueSource_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip ridx : UInt<1>, widx : UInt<1>, mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], flip sink_reset_n : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>} + + io is invalid + io is invalid + wire sink_ready : UInt<1> + sink_ready is invalid + sink_ready <= UInt<1>("h01") + reg mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], clock @[AsyncQueue.scala 54:16] + node _T_86 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_88 = eq(sink_ready, UInt<1>("h00")) @[AsyncQueue.scala 55:49] + wire _T_90 : UInt<1> @[AsyncQueue.scala 8:27] + _T_90 is invalid @[AsyncQueue.scala 8:27] + inst widx_bin of AsyncResetRegVec_29 @[BlackBoxRegs.scala 89:21] + widx_bin.io is invalid + widx_bin.clock <= clock + widx_bin.reset <= reset + widx_bin.io.d <= _T_90 @[BlackBoxRegs.scala 91:14] + widx_bin.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node _T_93 = add(widx_bin.io.q, _T_86) @[AsyncQueue.scala 10:47] + node _T_94 = tail(_T_93, 1) @[AsyncQueue.scala 10:47] + node _T_95 = mux(_T_88, UInt<1>("h00"), _T_94) @[AsyncQueue.scala 10:23] + _T_90 <= _T_95 @[AsyncQueue.scala 10:17] + node _T_97 = dshr(_T_90, UInt<1>("h01")) @[AsyncQueue.scala 11:32] + node widx = xor(_T_90, _T_97) @[AsyncQueue.scala 11:17] + inst ridx_gray_sync_0 of AsyncResetRegVec_30 @[AsyncQueue.scala 18:14] + ridx_gray_sync_0.io is invalid + ridx_gray_sync_0.clock <= clock + ridx_gray_sync_0.reset <= reset + inst ridx_gray_sync_1 of AsyncResetRegVec_31 @[AsyncQueue.scala 18:14] + ridx_gray_sync_1.io is invalid + ridx_gray_sync_1.clock <= clock + ridx_gray_sync_1.reset <= reset + inst ridx_gray_sync_2 of AsyncResetRegVec_32 @[AsyncQueue.scala 18:14] + ridx_gray_sync_2.io is invalid + ridx_gray_sync_2.clock <= clock + ridx_gray_sync_2.reset <= reset + ridx_gray_sync_2.io.d <= io.ridx @[AsyncQueue.scala 20:21] + ridx_gray_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + ridx_gray_sync_0.io.d <= ridx_gray_sync_1.io.q @[AsyncQueue.scala 23:19] + ridx_gray_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + ridx_gray_sync_1.io.d <= ridx_gray_sync_2.io.q @[AsyncQueue.scala 23:19] + ridx_gray_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_102 = xor(ridx_gray_sync_0.io.q, UInt<1>("h01")) @[AsyncQueue.scala 57:44] + node _T_103 = neq(widx, _T_102) @[AsyncQueue.scala 57:34] + node ready = and(sink_ready, _T_103) @[AsyncQueue.scala 57:26] + node _T_104 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + when _T_104 : @[AsyncQueue.scala 60:24] + mem[UInt<1>("h00")] <- io.enq.bits @[AsyncQueue.scala 60:37] + skip @[AsyncQueue.scala 60:24] + inst ready_reg of AsyncResetRegVec_33 @[BlackBoxRegs.scala 89:21] + ready_reg.io is invalid + ready_reg.clock <= clock + ready_reg.reset <= reset + ready_reg.io.d <= ready @[BlackBoxRegs.scala 91:14] + ready_reg.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node ready_reg_1 = bits(ready_reg.io.q, 0, 0) @[AsyncQueue.scala 62:59] + node _T_114 = and(ready_reg_1, sink_ready) @[AsyncQueue.scala 63:29] + io.enq.ready <= _T_114 @[AsyncQueue.scala 63:16] + inst widx_gray of AsyncResetRegVec_34 @[BlackBoxRegs.scala 89:21] + widx_gray.io is invalid + widx_gray.clock <= clock + widx_gray.reset <= reset + widx_gray.io.d <= widx @[BlackBoxRegs.scala 91:14] + widx_gray.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + io.widx <= widx_gray.io.q @[AsyncQueue.scala 66:11] + io.mem <- mem @[AsyncQueue.scala 68:10] + io.widx_valid <= UInt<1>("h01") @[AsyncQueue.scala 70:17] + inst AsyncValidSync of AsyncValidSync_6 @[AsyncQueue.scala 72:30] + AsyncValidSync.io is invalid + AsyncValidSync.clock <= clock + AsyncValidSync.reset <= reset + inst AsyncValidSync_1 of AsyncValidSync_7 @[AsyncQueue.scala 73:30] + AsyncValidSync_1.io is invalid + AsyncValidSync_1.clock <= clock + AsyncValidSync_1.reset <= reset + inst AsyncValidSync_2 of AsyncValidSync_8 @[AsyncQueue.scala 74:30] + AsyncValidSync_2.io is invalid + AsyncValidSync_2.clock <= clock + AsyncValidSync_2.reset <= reset + node _T_118 = eq(io.sink_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 75:36] + node _T_119 = or(reset, _T_118) @[AsyncQueue.scala 75:33] + AsyncValidSync.reset <= _T_119 @[AsyncQueue.scala 75:24] + node _T_121 = eq(io.sink_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 76:36] + node _T_122 = or(reset, _T_121) @[AsyncQueue.scala 76:33] + AsyncValidSync_1.reset <= _T_122 @[AsyncQueue.scala 76:24] + AsyncValidSync.io.in <= UInt<1>("h01") @[AsyncQueue.scala 78:24] + io.widx_valid <= AsyncValidSync.io.out @[AsyncQueue.scala 79:19] + AsyncValidSync_1.io.in <= io.ridx_valid @[AsyncQueue.scala 80:23] + AsyncValidSync_2.io.in <= AsyncValidSync_1.io.out @[AsyncQueue.scala 81:22] + sink_ready <= AsyncValidSync_2.io.out @[AsyncQueue.scala 82:16] + + extmodule AsyncResetReg_43 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_43 : + input clock : Clock input reset : UInt<1> - output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_1277 : {state : UInt<2>} - T_1277 is invalid - T_1277.state <= UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277)) - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk - node req_idx = bits(req.addr, 11, 6) - node T_1586 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1586) - node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1590 = or(T_1588, T_1589) - node T_1591 = bits(io.req_bits.cmd, 3, 3) - node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1593 = or(T_1591, T_1592) - node T_1594 = or(T_1590, T_1593) - node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1596 = or(T_1594, T_1595) - node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1598 = or(T_1596, T_1597) - node T_1599 = eq(req.cmd, UInt<5>("h01")) - node T_1600 = eq(req.cmd, UInt<5>("h07")) - node T_1601 = or(T_1599, T_1600) - node T_1602 = bits(req.cmd, 3, 3) - node T_1603 = eq(req.cmd, UInt<5>("h04")) - node T_1604 = or(T_1602, T_1603) - node T_1605 = or(T_1601, T_1604) - node T_1606 = eq(req.cmd, UInt<5>("h03")) - node T_1607 = or(T_1605, T_1606) - node T_1608 = eq(req.cmd, UInt<5>("h06")) - node T_1609 = or(T_1607, T_1608) - node T_1611 = eq(T_1609, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_1598, T_1611) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] <= UInt<1>("h01") - states_before_refill[1] <= UInt<2>("h02") - states_before_refill[2] <= UInt<2>("h03") - node T_1619 = eq(states_before_refill[0], state) - node T_1620 = eq(states_before_refill[1], state) - node T_1621 = eq(states_before_refill[2], state) - node T_1623 = or(UInt<1>("h00"), T_1619) - node T_1624 = or(T_1623, T_1620) - node T_1625 = or(T_1624, T_1621) - wire T_1627 : UInt<3>[2] - T_1627[0] <= UInt<3>("h04") - T_1627[1] <= UInt<3>("h05") - node T_1631 = eq(T_1627[0], state) - node T_1632 = eq(T_1627[1], state) - node T_1634 = or(UInt<1>("h00"), T_1631) - node T_1635 = or(T_1634, T_1632) - node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_1638 = and(T_1635, T_1637) - node T_1639 = or(T_1625, T_1638) - node sec_rdy = and(idx_match, T_1639) - wire T_1644 : UInt<3>[1] - T_1644[0] <= UInt<3>("h05") - node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) - node T_1649 = or(UInt<1>("h00"), T_1647) - wire T_1651 : UInt<1>[2] - T_1651[0] <= UInt<1>("h00") - T_1651[1] <= UInt<1>("h01") - node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) - node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) - node T_1658 = or(UInt<1>("h00"), T_1655) - node T_1659 = or(T_1658, T_1656) - node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) - node gnt_multi_data = and(UInt<1>("h01"), T_1660) - node T_1662 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1662 : - node T_1666 = eq(refill_cnt, UInt<2>("h03")) - node T_1668 = and(UInt<1>("h00"), T_1666) - node T_1671 = add(refill_cnt, UInt<1>("h01")) - node T_1672 = tail(T_1671, 1) - node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672) - refill_cnt <= T_1673 - skip - node refill_count_done = and(T_1662, T_1666) - node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) - node T_1677 = or(T_1676, refill_count_done) - node refill_done = and(io.mem_grant.valid, T_1677) - inst rpq of Queue_98 - rpq.io is invalid - rpq.clk <= clk - rpq.reset <= reset - node T_1734 = and(io.req_pri_val, io.req_pri_rdy) - node T_1735 = and(io.req_sec_val, sec_rdy) - node T_1736 = or(T_1734, T_1735) - node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02")) - node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1739 = or(T_1737, T_1738) - node T_1741 = eq(T_1739, UInt<1>("h00")) - node T_1742 = and(T_1736, T_1741) - rpq.io.enq.valid <= T_1742 - rpq.io.enq.bits <- io.req_bits - node T_1743 = eq(state, UInt<4>("h08")) - node T_1744 = and(io.replay.ready, T_1743) - node T_1745 = eq(state, UInt<1>("h00")) - node T_1746 = or(T_1744, T_1745) - rpq.io.deq.ready <= T_1746 - node T_1747 = eq(req.cmd, UInt<5>("h01")) - node T_1748 = eq(req.cmd, UInt<5>("h07")) - node T_1749 = or(T_1747, T_1748) - node T_1750 = bits(req.cmd, 3, 3) - node T_1751 = eq(req.cmd, UInt<5>("h04")) - node T_1752 = or(T_1750, T_1751) - node T_1753 = or(T_1749, T_1752) - node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02")) - node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) - node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00")) - node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) - node T_1758 = mux(T_1757, T_1754, T_1756) - node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) - node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758) - node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760) - wire coh_on_grant : {state : UInt<2>} - coh_on_grant is invalid - coh_on_grant.state <= T_1761 - node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = bits(io.req_bits.cmd, 3, 3) - node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1817 = or(T_1815, T_1816) - node T_1818 = or(T_1814, T_1817) - node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state) - wire coh_on_hit : {state : UInt<2>} - coh_on_hit is invalid - coh_on_hit.state <= T_1819 - node T_1870 = eq(state, UInt<4>("h08")) - node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00")) - node T_1873 = and(T_1870, T_1872) - when T_1873 : - state <= UInt<1>("h00") - skip - node T_1874 = eq(state, UInt<3>("h07")) - when T_1874 : - state <= UInt<4>("h08") - skip - node T_1875 = eq(state, UInt<3>("h06")) - node T_1876 = and(T_1875, io.meta_write.ready) - when T_1876 : - state <= UInt<3>("h07") - skip - node T_1877 = eq(state, UInt<3>("h05")) - when T_1877 : - when io.mem_grant.valid : - new_coh_state <- coh_on_grant - skip - when refill_done : - state <= UInt<3>("h06") - skip - skip - node T_1878 = and(io.mem_req.ready, io.mem_req.valid) - when T_1878 : - state <= UInt<3>("h05") - skip - node T_1879 = eq(state, UInt<2>("h03")) - node T_1880 = and(T_1879, io.meta_write.ready) - when T_1880 : - state <= UInt<3>("h04") - skip - node T_1881 = eq(state, UInt<2>("h02")) - node T_1882 = and(T_1881, io.mem_grant.valid) - when T_1882 : - state <= UInt<2>("h03") - skip - node T_1883 = and(io.wb_req.ready, io.wb_req.valid) - when T_1883 : - node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03")) - state <= T_1887 - skip - node T_1888 = and(io.req_sec_val, io.req_sec_rdy) - when T_1888 : - when cmd_requires_second_acquire : - req.cmd <= io.req_bits.cmd - skip - skip - node T_1889 = and(io.req_pri_val, io.req_pri_rdy) - when T_1889 : - req <- io.req_bits - when io.req_bits.tag_match : - node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1892 = or(T_1890, T_1891) - node T_1893 = bits(io.req_bits.cmd, 3, 3) - node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1895 = or(T_1893, T_1894) - node T_1896 = or(T_1892, T_1895) - node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1898 = or(T_1896, T_1897) - node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1900 = or(T_1898, T_1899) - wire T_1902 : UInt<2>[2] - T_1902[0] <= UInt<2>("h02") - T_1902[1] <= UInt<2>("h03") - node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) - node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) - node T_1909 = or(UInt<1>("h00"), T_1906) - node T_1910 = or(T_1909, T_1907) - wire T_1912 : UInt<2>[3] - T_1912[0] <= UInt<1>("h01") - T_1912[1] <= UInt<2>("h02") - T_1912[2] <= UInt<2>("h03") - node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) - node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) - node T_1921 = or(UInt<1>("h00"), T_1917) - node T_1922 = or(T_1921, T_1918) - node T_1923 = or(T_1922, T_1919) - node T_1924 = mux(T_1900, T_1910, T_1923) - when T_1924 : - state <= UInt<3>("h06") - new_coh_state <- coh_on_hit - skip - node T_1926 = eq(T_1924, UInt<1>("h00")) - when T_1926 : - state <= UInt<3>("h04") - skip - skip - node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00")) - when T_1928 : - wire T_1930 : UInt<2>[1] - T_1930[0] <= UInt<2>("h03") - node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) - node T_1935 = or(UInt<1>("h00"), T_1933) - node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03")) - state <= T_1936 - skip - skip - node T_1937 = neq(state, UInt<1>("h00")) - node T_1938 = and(T_1937, idx_match) - io.idx_match <= T_1938 - io.refill.way_en <= req.way_en - node T_1939 = cat(req_idx, refill_cnt) - node T_1940 = shl(T_1939, 4) - io.refill.addr <= T_1940 - node T_1941 = shr(req.addr, 12) - io.tag <= T_1941 - node T_1942 = eq(state, UInt<1>("h00")) - io.req_pri_rdy <= T_1942 - node T_1943 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1943 - reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_1947 = neq(meta_hazard, UInt<1>("h00")) - when T_1947 : - node T_1949 = add(meta_hazard, UInt<1>("h01")) - node T_1950 = tail(T_1949, 1) - meta_hazard <= T_1950 - skip - node T_1951 = and(io.meta_write.ready, io.meta_write.valid) - when T_1951 : - meta_hazard <= UInt<1>("h01") - skip - node T_1954 = eq(idx_match, UInt<1>("h00")) - node T_1955 = eq(states_before_refill[0], state) - node T_1956 = eq(states_before_refill[1], state) - node T_1957 = eq(states_before_refill[2], state) - node T_1959 = or(UInt<1>("h00"), T_1955) - node T_1960 = or(T_1959, T_1956) - node T_1961 = or(T_1960, T_1957) - node T_1963 = eq(T_1961, UInt<1>("h00")) - node T_1965 = eq(meta_hazard, UInt<1>("h00")) - node T_1966 = and(T_1963, T_1965) - node T_1967 = or(T_1954, T_1966) - io.probe_rdy <= T_1967 - node T_1968 = eq(state, UInt<3>("h06")) - node T_1969 = eq(state, UInt<2>("h03")) - node T_1970 = or(T_1968, T_1969) - io.meta_write.valid <= T_1970 - io.meta_write.bits.idx <= req_idx - node T_1971 = eq(state, UInt<2>("h03")) - wire T_1973 : UInt<2>[2] - T_1973[0] <= UInt<2>("h02") - T_1973[1] <= UInt<2>("h03") - node T_1977 = eq(T_1973[0], req.old_meta.coh.state) - node T_1978 = eq(T_1973[1], req.old_meta.coh.state) - node T_1980 = or(UInt<1>("h00"), T_1977) - node T_1981 = or(T_1980, T_1978) - node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state) - node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state) - node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) - node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1988 = mux(T_1987, T_1982, T_1986) - node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988) - wire T_2016 : {state : UInt<2>} - T_2016 is invalid - T_2016.state <= T_1990 - node T_2041 = mux(T_1971, T_2016, new_coh_state) - io.meta_write.bits.data.coh <- T_2041 - io.meta_write.bits.data.tag <= io.tag - io.meta_write.bits.way_en <= req.way_en - node T_2066 = eq(state, UInt<1>("h01")) - io.wb_req.valid <= T_2066 - node T_2068 = cat(req.old_meta.tag, req_idx) - wire T_2073 : UInt<2>[1] - T_2073[0] <= UInt<2>("h03") - node T_2076 = eq(T_2073[0], req.old_meta.coh.state) - node T_2078 = or(UInt<1>("h00"), T_2076) - node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03")) - node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04")) - node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05")) - node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_2083 = mux(T_2082, T_2081, UInt<3>("h05")) - node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_2085 = mux(T_2084, T_2080, T_2083) - node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2087 = mux(T_2086, T_2079, T_2085) - wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2118 is invalid - T_2118.r_type <= T_2087 - T_2118.client_xact_id <= UInt<1>("h00") - T_2118.addr_block <= T_2068 - T_2118.addr_beat <= UInt<1>("h00") - T_2118.data <= UInt<1>("h00") - T_2118.voluntary <= UInt<1>("h01") - io.wb_req.bits <- T_2118 - io.wb_req.bits.way_en <= req.way_en - node T_2148 = eq(state, UInt<3>("h04")) - io.mem_req.valid <= T_2148 - node T_2149 = cat(io.tag, req_idx) - node T_2152 = eq(req.cmd, UInt<5>("h01")) - node T_2153 = eq(req.cmd, UInt<5>("h07")) - node T_2154 = or(T_2152, T_2153) - node T_2155 = bits(req.cmd, 3, 3) - node T_2156 = eq(req.cmd, UInt<5>("h04")) - node T_2157 = or(T_2155, T_2156) - node T_2158 = or(T_2154, T_2157) - node T_2159 = eq(req.cmd, UInt<5>("h03")) - node T_2160 = or(T_2158, T_2159) - node T_2161 = eq(req.cmd, UInt<5>("h06")) - node T_2162 = or(T_2160, T_2161) - node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00")) - node T_2165 = cat(req.cmd, UInt<1>("h01")) - wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2199 is invalid - T_2199.is_builtin_type <= UInt<1>("h00") - T_2199.a_type <= T_2163 - T_2199.client_xact_id <= UInt<1>("h00") - T_2199.addr_block <= T_2149 - T_2199.addr_beat <= UInt<1>("h00") - T_2199.data <= UInt<1>("h00") - T_2199.union <= T_2165 - io.mem_req.bits <- T_2199 - node T_2230 = eq(state, UInt<4>("h08")) - io.meta_read.valid <= T_2230 - io.meta_read.bits.idx <= req_idx - io.meta_read.bits.tag <= io.tag - node T_2231 = eq(state, UInt<4>("h08")) - node T_2232 = and(T_2231, rpq.io.deq.valid) - io.replay.valid <= T_2232 - io.replay.bits <- rpq.io.deq.bits - io.replay.bits.phys <= UInt<1>("h01") - node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2235 = cat(req_idx, T_2234) - node T_2236 = cat(io.tag, T_2235) - io.replay.bits.addr <= T_2236 - node T_2238 = eq(io.meta_read.ready, UInt<1>("h00")) - when T_2238 : - rpq.io.deq.ready <= UInt<1>("h00") - io.replay.bits.cmd <= UInt<5>("h05") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_43 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module MSHR_99 : + extmodule AsyncResetReg_44 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_44 : + input clock : Clock input reset : UInt<1> - output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_1277 : {state : UInt<2>} - T_1277 is invalid - T_1277.state <= UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277)) - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk - node req_idx = bits(req.addr, 11, 6) - node T_1586 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1586) - node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1590 = or(T_1588, T_1589) - node T_1591 = bits(io.req_bits.cmd, 3, 3) - node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1593 = or(T_1591, T_1592) - node T_1594 = or(T_1590, T_1593) - node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1596 = or(T_1594, T_1595) - node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1598 = or(T_1596, T_1597) - node T_1599 = eq(req.cmd, UInt<5>("h01")) - node T_1600 = eq(req.cmd, UInt<5>("h07")) - node T_1601 = or(T_1599, T_1600) - node T_1602 = bits(req.cmd, 3, 3) - node T_1603 = eq(req.cmd, UInt<5>("h04")) - node T_1604 = or(T_1602, T_1603) - node T_1605 = or(T_1601, T_1604) - node T_1606 = eq(req.cmd, UInt<5>("h03")) - node T_1607 = or(T_1605, T_1606) - node T_1608 = eq(req.cmd, UInt<5>("h06")) - node T_1609 = or(T_1607, T_1608) - node T_1611 = eq(T_1609, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_1598, T_1611) - wire states_before_refill : UInt<2>[3] - states_before_refill[0] <= UInt<1>("h01") - states_before_refill[1] <= UInt<2>("h02") - states_before_refill[2] <= UInt<2>("h03") - node T_1619 = eq(states_before_refill[0], state) - node T_1620 = eq(states_before_refill[1], state) - node T_1621 = eq(states_before_refill[2], state) - node T_1623 = or(UInt<1>("h00"), T_1619) - node T_1624 = or(T_1623, T_1620) - node T_1625 = or(T_1624, T_1621) - wire T_1627 : UInt<3>[2] - T_1627[0] <= UInt<3>("h04") - T_1627[1] <= UInt<3>("h05") - node T_1631 = eq(T_1627[0], state) - node T_1632 = eq(T_1627[1], state) - node T_1634 = or(UInt<1>("h00"), T_1631) - node T_1635 = or(T_1634, T_1632) - node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_1638 = and(T_1635, T_1637) - node T_1639 = or(T_1625, T_1638) - node sec_rdy = and(idx_match, T_1639) - wire T_1644 : UInt<3>[1] - T_1644[0] <= UInt<3>("h05") - node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) - node T_1649 = or(UInt<1>("h00"), T_1647) - wire T_1651 : UInt<1>[2] - T_1651[0] <= UInt<1>("h00") - T_1651[1] <= UInt<1>("h01") - node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) - node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) - node T_1658 = or(UInt<1>("h00"), T_1655) - node T_1659 = or(T_1658, T_1656) - node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) - node gnt_multi_data = and(UInt<1>("h01"), T_1660) - node T_1662 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - when T_1662 : - node T_1666 = eq(refill_cnt, UInt<2>("h03")) - node T_1668 = and(UInt<1>("h00"), T_1666) - node T_1671 = add(refill_cnt, UInt<1>("h01")) - node T_1672 = tail(T_1671, 1) - node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672) - refill_cnt <= T_1673 - skip - node refill_count_done = and(T_1662, T_1666) - node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) - node T_1677 = or(T_1676, refill_count_done) - node refill_done = and(io.mem_grant.valid, T_1677) - inst rpq of Queue_98 - rpq.io is invalid - rpq.clk <= clk - rpq.reset <= reset - node T_1734 = and(io.req_pri_val, io.req_pri_rdy) - node T_1735 = and(io.req_sec_val, sec_rdy) - node T_1736 = or(T_1734, T_1735) - node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02")) - node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1739 = or(T_1737, T_1738) - node T_1741 = eq(T_1739, UInt<1>("h00")) - node T_1742 = and(T_1736, T_1741) - rpq.io.enq.valid <= T_1742 - rpq.io.enq.bits <- io.req_bits - node T_1743 = eq(state, UInt<4>("h08")) - node T_1744 = and(io.replay.ready, T_1743) - node T_1745 = eq(state, UInt<1>("h00")) - node T_1746 = or(T_1744, T_1745) - rpq.io.deq.ready <= T_1746 - node T_1747 = eq(req.cmd, UInt<5>("h01")) - node T_1748 = eq(req.cmd, UInt<5>("h07")) - node T_1749 = or(T_1747, T_1748) - node T_1750 = bits(req.cmd, 3, 3) - node T_1751 = eq(req.cmd, UInt<5>("h04")) - node T_1752 = or(T_1750, T_1751) - node T_1753 = or(T_1749, T_1752) - node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02")) - node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) - node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00")) - node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) - node T_1758 = mux(T_1757, T_1754, T_1756) - node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) - node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758) - node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760) - wire coh_on_grant : {state : UInt<2>} - coh_on_grant is invalid - coh_on_grant.state <= T_1761 - node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = bits(io.req_bits.cmd, 3, 3) - node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1817 = or(T_1815, T_1816) - node T_1818 = or(T_1814, T_1817) - node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state) - wire coh_on_hit : {state : UInt<2>} - coh_on_hit is invalid - coh_on_hit.state <= T_1819 - node T_1870 = eq(state, UInt<4>("h08")) - node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00")) - node T_1873 = and(T_1870, T_1872) - when T_1873 : - state <= UInt<1>("h00") - skip - node T_1874 = eq(state, UInt<3>("h07")) - when T_1874 : - state <= UInt<4>("h08") - skip - node T_1875 = eq(state, UInt<3>("h06")) - node T_1876 = and(T_1875, io.meta_write.ready) - when T_1876 : - state <= UInt<3>("h07") - skip - node T_1877 = eq(state, UInt<3>("h05")) - when T_1877 : - when io.mem_grant.valid : - new_coh_state <- coh_on_grant - skip - when refill_done : - state <= UInt<3>("h06") - skip - skip - node T_1878 = and(io.mem_req.ready, io.mem_req.valid) - when T_1878 : - state <= UInt<3>("h05") - skip - node T_1879 = eq(state, UInt<2>("h03")) - node T_1880 = and(T_1879, io.meta_write.ready) - when T_1880 : - state <= UInt<3>("h04") - skip - node T_1881 = eq(state, UInt<2>("h02")) - node T_1882 = and(T_1881, io.mem_grant.valid) - when T_1882 : - state <= UInt<2>("h03") - skip - node T_1883 = and(io.wb_req.ready, io.wb_req.valid) - when T_1883 : - node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03")) - state <= T_1887 - skip - node T_1888 = and(io.req_sec_val, io.req_sec_rdy) - when T_1888 : - when cmd_requires_second_acquire : - req.cmd <= io.req_bits.cmd - skip - skip - node T_1889 = and(io.req_pri_val, io.req_pri_rdy) - when T_1889 : - req <- io.req_bits - when io.req_bits.tag_match : - node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1892 = or(T_1890, T_1891) - node T_1893 = bits(io.req_bits.cmd, 3, 3) - node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1895 = or(T_1893, T_1894) - node T_1896 = or(T_1892, T_1895) - node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1898 = or(T_1896, T_1897) - node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1900 = or(T_1898, T_1899) - wire T_1902 : UInt<2>[2] - T_1902[0] <= UInt<2>("h02") - T_1902[1] <= UInt<2>("h03") - node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) - node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) - node T_1909 = or(UInt<1>("h00"), T_1906) - node T_1910 = or(T_1909, T_1907) - wire T_1912 : UInt<2>[3] - T_1912[0] <= UInt<1>("h01") - T_1912[1] <= UInt<2>("h02") - T_1912[2] <= UInt<2>("h03") - node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) - node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) - node T_1921 = or(UInt<1>("h00"), T_1917) - node T_1922 = or(T_1921, T_1918) - node T_1923 = or(T_1922, T_1919) - node T_1924 = mux(T_1900, T_1910, T_1923) - when T_1924 : - state <= UInt<3>("h06") - new_coh_state <- coh_on_hit - skip - node T_1926 = eq(T_1924, UInt<1>("h00")) - when T_1926 : - state <= UInt<3>("h04") - skip - skip - node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00")) - when T_1928 : - wire T_1930 : UInt<2>[1] - T_1930[0] <= UInt<2>("h03") - node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) - node T_1935 = or(UInt<1>("h00"), T_1933) - node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03")) - state <= T_1936 - skip - skip - node T_1937 = neq(state, UInt<1>("h00")) - node T_1938 = and(T_1937, idx_match) - io.idx_match <= T_1938 - io.refill.way_en <= req.way_en - node T_1939 = cat(req_idx, refill_cnt) - node T_1940 = shl(T_1939, 4) - io.refill.addr <= T_1940 - node T_1941 = shr(req.addr, 12) - io.tag <= T_1941 - node T_1942 = eq(state, UInt<1>("h00")) - io.req_pri_rdy <= T_1942 - node T_1943 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1943 - reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_1947 = neq(meta_hazard, UInt<1>("h00")) - when T_1947 : - node T_1949 = add(meta_hazard, UInt<1>("h01")) - node T_1950 = tail(T_1949, 1) - meta_hazard <= T_1950 - skip - node T_1951 = and(io.meta_write.ready, io.meta_write.valid) - when T_1951 : - meta_hazard <= UInt<1>("h01") - skip - node T_1954 = eq(idx_match, UInt<1>("h00")) - node T_1955 = eq(states_before_refill[0], state) - node T_1956 = eq(states_before_refill[1], state) - node T_1957 = eq(states_before_refill[2], state) - node T_1959 = or(UInt<1>("h00"), T_1955) - node T_1960 = or(T_1959, T_1956) - node T_1961 = or(T_1960, T_1957) - node T_1963 = eq(T_1961, UInt<1>("h00")) - node T_1965 = eq(meta_hazard, UInt<1>("h00")) - node T_1966 = and(T_1963, T_1965) - node T_1967 = or(T_1954, T_1966) - io.probe_rdy <= T_1967 - node T_1968 = eq(state, UInt<3>("h06")) - node T_1969 = eq(state, UInt<2>("h03")) - node T_1970 = or(T_1968, T_1969) - io.meta_write.valid <= T_1970 - io.meta_write.bits.idx <= req_idx - node T_1971 = eq(state, UInt<2>("h03")) - wire T_1973 : UInt<2>[2] - T_1973[0] <= UInt<2>("h02") - T_1973[1] <= UInt<2>("h03") - node T_1977 = eq(T_1973[0], req.old_meta.coh.state) - node T_1978 = eq(T_1973[1], req.old_meta.coh.state) - node T_1980 = or(UInt<1>("h00"), T_1977) - node T_1981 = or(T_1980, T_1978) - node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state) - node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state) - node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) - node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1988 = mux(T_1987, T_1982, T_1986) - node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988) - wire T_2016 : {state : UInt<2>} - T_2016 is invalid - T_2016.state <= T_1990 - node T_2041 = mux(T_1971, T_2016, new_coh_state) - io.meta_write.bits.data.coh <- T_2041 - io.meta_write.bits.data.tag <= io.tag - io.meta_write.bits.way_en <= req.way_en - node T_2066 = eq(state, UInt<1>("h01")) - io.wb_req.valid <= T_2066 - node T_2068 = cat(req.old_meta.tag, req_idx) - wire T_2073 : UInt<2>[1] - T_2073[0] <= UInt<2>("h03") - node T_2076 = eq(T_2073[0], req.old_meta.coh.state) - node T_2078 = or(UInt<1>("h00"), T_2076) - node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03")) - node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04")) - node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05")) - node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_2083 = mux(T_2082, T_2081, UInt<3>("h05")) - node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_2085 = mux(T_2084, T_2080, T_2083) - node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2087 = mux(T_2086, T_2079, T_2085) - wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2118 is invalid - T_2118.r_type <= T_2087 - T_2118.client_xact_id <= UInt<1>("h01") - T_2118.addr_block <= T_2068 - T_2118.addr_beat <= UInt<1>("h00") - T_2118.data <= UInt<1>("h00") - T_2118.voluntary <= UInt<1>("h01") - io.wb_req.bits <- T_2118 - io.wb_req.bits.way_en <= req.way_en - node T_2148 = eq(state, UInt<3>("h04")) - io.mem_req.valid <= T_2148 - node T_2149 = cat(io.tag, req_idx) - node T_2152 = eq(req.cmd, UInt<5>("h01")) - node T_2153 = eq(req.cmd, UInt<5>("h07")) - node T_2154 = or(T_2152, T_2153) - node T_2155 = bits(req.cmd, 3, 3) - node T_2156 = eq(req.cmd, UInt<5>("h04")) - node T_2157 = or(T_2155, T_2156) - node T_2158 = or(T_2154, T_2157) - node T_2159 = eq(req.cmd, UInt<5>("h03")) - node T_2160 = or(T_2158, T_2159) - node T_2161 = eq(req.cmd, UInt<5>("h06")) - node T_2162 = or(T_2160, T_2161) - node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00")) - node T_2165 = cat(req.cmd, UInt<1>("h01")) - wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2199 is invalid - T_2199.is_builtin_type <= UInt<1>("h00") - T_2199.a_type <= T_2163 - T_2199.client_xact_id <= UInt<1>("h01") - T_2199.addr_block <= T_2149 - T_2199.addr_beat <= UInt<1>("h00") - T_2199.data <= UInt<1>("h00") - T_2199.union <= T_2165 - io.mem_req.bits <- T_2199 - node T_2230 = eq(state, UInt<4>("h08")) - io.meta_read.valid <= T_2230 - io.meta_read.bits.idx <= req_idx - io.meta_read.bits.tag <= io.tag - node T_2231 = eq(state, UInt<4>("h08")) - node T_2232 = and(T_2231, rpq.io.deq.valid) - io.replay.valid <= T_2232 - io.replay.bits <- rpq.io.deq.bits - io.replay.bits.phys <= UInt<1>("h01") - node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2235 = cat(req_idx, T_2234) - node T_2236 = cat(io.tag, T_2235) - io.replay.bits.addr <= T_2236 - node T_2238 = eq(io.meta_read.ready, UInt<1>("h00")) - when T_2238 : - rpq.io.deq.ready <= UInt<1>("h00") - io.replay.bits.cmd <= UInt<5>("h05") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module Arbiter_101 : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_44 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_45 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_45 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - wire T_54 : UInt<1> - T_54 is invalid - io.out.valid <= io.in[T_54].valid - io.out.bits <= io.in[T_54].bits - io.chosen <= T_54 - io.in[T_54].ready <= UInt<1>("h00") - node T_73 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_74 = mux(UInt<1>("h00"), T_73, UInt<1>("h01")) - node T_75 = and(T_74, io.out.ready) - io.in[0].ready <= T_75 - node T_77 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) - T_54 <= T_77 + io is invalid + inst reg_0 of AsyncResetReg_45 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module Arbiter_102 : + extmodule AsyncResetReg_46 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_46 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - wire T_1062 : UInt<1> - T_1062 is invalid - io.out.valid <= io.in[T_1062].valid - io.out.bits <- io.in[T_1062].bits - io.chosen <= T_1062 - io.in[T_1062].ready <= UInt<1>("h00") - node T_1417 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1418 = mux(UInt<1>("h00"), T_1417, UInt<1>("h01")) - node T_1419 = and(T_1418, io.out.ready) - io.in[0].ready <= T_1419 - node T_1421 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) - T_1062 <= T_1421 + io is invalid + inst reg_0 of AsyncResetReg_46 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module IOMSHR : + extmodule AsyncResetReg_47 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_47 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}} - - io is invalid - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk - node req_cmd_sc = eq(req.cmd, UInt<5>("h07")) - reg grant_word : UInt<64>, clk - node T_861 = bits(req.typ, 1, 0) - node T_862 = bits(req.typ, 1, 0) - node T_863 = asSInt(req.typ) - node T_865 = geq(T_863, asSInt(UInt<1>("h00"))) - node beat_offset = bits(req.addr, 3, 3) - node T_868 = bits(req.addr, 0, 0) - node T_870 = mux(T_868, UInt<1>("h01"), UInt<1>("h00")) - node T_872 = geq(T_861, UInt<1>("h01")) - node T_875 = mux(T_872, UInt<1>("h01"), UInt<1>("h00")) - node T_876 = or(T_870, T_875) - node T_877 = bits(req.addr, 0, 0) - node T_879 = mux(T_877, UInt<1>("h00"), UInt<1>("h01")) - node T_880 = cat(T_876, T_879) - node T_881 = bits(req.addr, 1, 1) - node T_883 = mux(T_881, T_880, UInt<1>("h00")) - node T_885 = geq(T_861, UInt<2>("h02")) - node T_888 = mux(T_885, UInt<2>("h03"), UInt<1>("h00")) - node T_889 = or(T_883, T_888) - node T_890 = bits(req.addr, 1, 1) - node T_892 = mux(T_890, UInt<1>("h00"), T_880) - node T_893 = cat(T_889, T_892) - node T_894 = bits(req.addr, 2, 2) - node T_896 = mux(T_894, T_893, UInt<1>("h00")) - node T_898 = geq(T_861, UInt<2>("h03")) - node T_901 = mux(T_898, UInt<4>("h0f"), UInt<1>("h00")) - node T_902 = or(T_896, T_901) - node T_903 = bits(req.addr, 2, 2) - node T_905 = mux(T_903, UInt<1>("h00"), T_893) - node T_906 = cat(T_902, T_905) - node T_908 = cat(beat_offset, UInt<3>("h00")) - node beat_mask = dshl(T_906, T_908) - node T_911 = eq(T_861, UInt<1>("h00")) - node T_912 = bits(req.data, 7, 0) - node T_913 = cat(T_912, T_912) - node T_914 = cat(T_913, T_913) - node T_915 = cat(T_914, T_914) - node T_917 = eq(T_861, UInt<1>("h01")) - node T_918 = bits(req.data, 15, 0) - node T_919 = cat(T_918, T_918) - node T_920 = cat(T_919, T_919) - node T_922 = eq(T_861, UInt<2>("h02")) - node T_923 = bits(req.data, 31, 0) - node T_924 = cat(T_923, T_923) - node T_925 = mux(T_922, T_924, req.data) - node T_926 = mux(T_917, T_920, T_925) - node T_927 = mux(T_911, T_915, T_926) - node beat_data = cat(T_927, T_927) - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node T_935 = eq(state, UInt<1>("h00")) - io.req.ready <= T_935 - node addr_block = bits(req.addr, 31, 6) - node addr_beat = bits(req.addr, 5, 4) - node addr_byte = bits(req.addr, 3, 0) - node T_947 = cat(addr_byte, req.typ) - node T_948 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_949 = cat(T_947, T_948) - node T_951 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_952 = cat(req.typ, T_951) - node T_954 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_956 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_958 = cat(addr_byte, req.typ) - node T_959 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_960 = cat(T_958, T_959) - node T_962 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_964 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_965 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_966 = mux(T_965, T_964, UInt<1>("h00")) - node T_967 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_968 = mux(T_967, T_962, T_966) - node T_969 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_970 = mux(T_969, T_960, T_968) - node T_971 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_972 = mux(T_971, T_956, T_970) - node T_973 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_974 = mux(T_973, T_954, T_972) - node T_975 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_976 = mux(T_975, T_952, T_974) - node T_977 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_978 = mux(T_977, T_949, T_976) - wire get_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - get_acquire is invalid - get_acquire.is_builtin_type <= UInt<1>("h01") - get_acquire.a_type <= UInt<3>("h00") - get_acquire.client_xact_id <= UInt<2>("h02") - get_acquire.addr_block <= addr_block - get_acquire.addr_beat <= addr_beat - get_acquire.data <= UInt<1>("h00") - get_acquire.union <= T_978 - node T_1049 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1050 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1051 = cat(T_1049, T_1050) - node T_1053 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1054 = cat(UInt<3>("h07"), T_1053) - node T_1056 = cat(beat_mask, UInt<1>("h00")) - node T_1058 = cat(beat_mask, UInt<1>("h00")) - node T_1060 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1061 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1062 = cat(T_1060, T_1061) - node T_1064 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_1066 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_1067 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_1068 = mux(T_1067, T_1066, UInt<1>("h00")) - node T_1069 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_1070 = mux(T_1069, T_1064, T_1068) - node T_1071 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_1072 = mux(T_1071, T_1062, T_1070) - node T_1073 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_1074 = mux(T_1073, T_1058, T_1072) - node T_1075 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_1076 = mux(T_1075, T_1056, T_1074) - node T_1077 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_1078 = mux(T_1077, T_1054, T_1076) - node T_1079 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_1080 = mux(T_1079, T_1051, T_1078) - wire put_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - put_acquire is invalid - put_acquire.is_builtin_type <= UInt<1>("h01") - put_acquire.a_type <= UInt<3>("h02") - put_acquire.client_xact_id <= UInt<2>("h02") - put_acquire.addr_block <= addr_block - put_acquire.addr_beat <= addr_beat - put_acquire.data <= beat_data - put_acquire.union <= T_1080 - node T_1143 = eq(state, UInt<1>("h01")) - io.acquire.valid <= T_1143 - node T_1144 = eq(req.cmd, UInt<5>("h00")) - node T_1145 = eq(req.cmd, UInt<5>("h06")) - node T_1146 = or(T_1144, T_1145) - node T_1147 = eq(req.cmd, UInt<5>("h07")) - node T_1148 = or(T_1146, T_1147) - node T_1149 = bits(req.cmd, 3, 3) - node T_1150 = eq(req.cmd, UInt<5>("h04")) - node T_1151 = or(T_1149, T_1150) - node T_1152 = or(T_1148, T_1151) - node T_1153 = mux(T_1152, get_acquire, put_acquire) - io.acquire.bits <- T_1153 - node T_1184 = eq(state, UInt<2>("h03")) - io.resp.valid <= T_1184 - io.resp.bits <- req - node T_1185 = eq(req.cmd, UInt<5>("h00")) - node T_1186 = eq(req.cmd, UInt<5>("h06")) - node T_1187 = or(T_1185, T_1186) - node T_1188 = eq(req.cmd, UInt<5>("h07")) - node T_1189 = or(T_1187, T_1188) - node T_1190 = bits(req.cmd, 3, 3) - node T_1191 = eq(req.cmd, UInt<5>("h04")) - node T_1192 = or(T_1190, T_1191) - node T_1193 = or(T_1189, T_1192) - io.resp.bits.has_data <= T_1193 - node T_1194 = bits(req.addr, 2, 2) - node T_1195 = bits(grant_word, 63, 32) - node T_1196 = bits(grant_word, 31, 0) - node T_1197 = mux(T_1194, T_1195, T_1196) - node T_1199 = and(UInt<1>("h00"), req_cmd_sc) - node T_1201 = mux(T_1199, UInt<1>("h00"), T_1197) - node T_1203 = eq(T_862, UInt<2>("h02")) - node T_1204 = or(T_1203, T_1199) - node T_1205 = bits(T_1201, 31, 31) - node T_1206 = and(T_865, T_1205) - node T_1208 = sub(UInt<32>("h00"), T_1206) - node T_1209 = tail(T_1208, 1) - node T_1210 = bits(grant_word, 63, 32) - node T_1211 = mux(T_1204, T_1209, T_1210) - node T_1212 = cat(T_1211, T_1201) - node T_1213 = bits(req.addr, 1, 1) - node T_1214 = bits(T_1212, 31, 16) - node T_1215 = bits(T_1212, 15, 0) - node T_1216 = mux(T_1213, T_1214, T_1215) - node T_1218 = and(UInt<1>("h00"), req_cmd_sc) - node T_1220 = mux(T_1218, UInt<1>("h00"), T_1216) - node T_1222 = eq(T_862, UInt<1>("h01")) - node T_1223 = or(T_1222, T_1218) - node T_1224 = bits(T_1220, 15, 15) - node T_1225 = and(T_865, T_1224) - node T_1227 = sub(UInt<48>("h00"), T_1225) - node T_1228 = tail(T_1227, 1) - node T_1229 = bits(T_1212, 63, 16) - node T_1230 = mux(T_1223, T_1228, T_1229) - node T_1231 = cat(T_1230, T_1220) - node T_1232 = bits(req.addr, 0, 0) - node T_1233 = bits(T_1231, 15, 8) - node T_1234 = bits(T_1231, 7, 0) - node T_1235 = mux(T_1232, T_1233, T_1234) - node T_1237 = and(UInt<1>("h01"), req_cmd_sc) - node T_1239 = mux(T_1237, UInt<1>("h00"), T_1235) - node T_1241 = eq(T_862, UInt<1>("h00")) - node T_1242 = or(T_1241, T_1237) - node T_1243 = bits(T_1239, 7, 7) - node T_1244 = and(T_865, T_1243) - node T_1246 = sub(UInt<56>("h00"), T_1244) - node T_1247 = tail(T_1246, 1) - node T_1248 = bits(T_1231, 63, 8) - node T_1249 = mux(T_1242, T_1247, T_1248) - node T_1250 = cat(T_1249, T_1239) - node T_1251 = or(T_1250, req_cmd_sc) - io.resp.bits.data <= T_1251 - io.resp.bits.store_data <= req.data - io.resp.bits.nack <= UInt<1>("h00") - io.resp.bits.replay <= io.resp.valid - node T_1253 = and(io.req.ready, io.req.valid) - when T_1253 : - req <- io.req.bits - state <= UInt<1>("h01") - skip - node T_1254 = and(io.acquire.ready, io.acquire.valid) - when T_1254 : - state <= UInt<2>("h02") - skip - node T_1255 = eq(state, UInt<2>("h02")) - node T_1256 = and(T_1255, io.grant.valid) - when T_1256 : - node T_1257 = eq(req.cmd, UInt<5>("h00")) - node T_1258 = eq(req.cmd, UInt<5>("h06")) - node T_1259 = or(T_1257, T_1258) - node T_1260 = eq(req.cmd, UInt<5>("h07")) - node T_1261 = or(T_1259, T_1260) - node T_1262 = bits(req.cmd, 3, 3) - node T_1263 = eq(req.cmd, UInt<5>("h04")) - node T_1264 = or(T_1262, T_1263) - node T_1265 = or(T_1261, T_1264) - when T_1265 : - node T_1266 = bits(req.addr, 3, 3) - node T_1268 = cat(T_1266, UInt<6>("h00")) - node T_1269 = dshr(io.grant.bits.data, T_1268) - node T_1270 = bits(T_1269, 63, 0) - grant_word <= T_1270 - state <= UInt<2>("h03") - skip - node T_1272 = eq(T_1265, UInt<1>("h00")) - when T_1272 : - state <= UInt<1>("h00") - skip - skip - node T_1273 = and(io.resp.ready, io.resp.valid) - when T_1273 : - state <= UInt<1>("h00") - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module MSHRFile : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_47 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_48 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_48 : + input clock : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>} - - io is invalid - node cacheable = lt(io.req.bits.addr, UInt<31>("h040000000")) - reg sdq_val : UInt<17>, clk with : (reset => (reset, UInt<17>("h00"))) - node T_1807 = bits(sdq_val, 16, 0) - node T_1808 = not(T_1807) - node T_1809 = bits(T_1808, 0, 0) - node T_1810 = bits(T_1808, 1, 1) - node T_1811 = bits(T_1808, 2, 2) - node T_1812 = bits(T_1808, 3, 3) - node T_1813 = bits(T_1808, 4, 4) - node T_1814 = bits(T_1808, 5, 5) - node T_1815 = bits(T_1808, 6, 6) - node T_1816 = bits(T_1808, 7, 7) - node T_1817 = bits(T_1808, 8, 8) - node T_1818 = bits(T_1808, 9, 9) - node T_1819 = bits(T_1808, 10, 10) - node T_1820 = bits(T_1808, 11, 11) - node T_1821 = bits(T_1808, 12, 12) - node T_1822 = bits(T_1808, 13, 13) - node T_1823 = bits(T_1808, 14, 14) - node T_1824 = bits(T_1808, 15, 15) - node T_1825 = bits(T_1808, 16, 16) - wire T_1827 : UInt<1>[17] - T_1827[0] <= T_1809 - T_1827[1] <= T_1810 - T_1827[2] <= T_1811 - T_1827[3] <= T_1812 - T_1827[4] <= T_1813 - T_1827[5] <= T_1814 - T_1827[6] <= T_1815 - T_1827[7] <= T_1816 - T_1827[8] <= T_1817 - T_1827[9] <= T_1818 - T_1827[10] <= T_1819 - T_1827[11] <= T_1820 - T_1827[12] <= T_1821 - T_1827[13] <= T_1822 - T_1827[14] <= T_1823 - T_1827[15] <= T_1824 - T_1827[16] <= T_1825 - node T_1863 = mux(T_1827[15], UInt<4>("h0f"), UInt<5>("h010")) - node T_1864 = mux(T_1827[14], UInt<4>("h0e"), T_1863) - node T_1865 = mux(T_1827[13], UInt<4>("h0d"), T_1864) - node T_1866 = mux(T_1827[12], UInt<4>("h0c"), T_1865) - node T_1867 = mux(T_1827[11], UInt<4>("h0b"), T_1866) - node T_1868 = mux(T_1827[10], UInt<4>("h0a"), T_1867) - node T_1869 = mux(T_1827[9], UInt<4>("h09"), T_1868) - node T_1870 = mux(T_1827[8], UInt<4>("h08"), T_1869) - node T_1871 = mux(T_1827[7], UInt<3>("h07"), T_1870) - node T_1872 = mux(T_1827[6], UInt<3>("h06"), T_1871) - node T_1873 = mux(T_1827[5], UInt<3>("h05"), T_1872) - node T_1874 = mux(T_1827[4], UInt<3>("h04"), T_1873) - node T_1875 = mux(T_1827[3], UInt<2>("h03"), T_1874) - node T_1876 = mux(T_1827[2], UInt<2>("h02"), T_1875) - node T_1877 = mux(T_1827[1], UInt<1>("h01"), T_1876) - node sdq_alloc_id = mux(T_1827[0], UInt<1>("h00"), T_1877) - node T_1879 = not(sdq_val) - node T_1881 = eq(T_1879, UInt<1>("h00")) - node sdq_rdy = eq(T_1881, UInt<1>("h00")) - node T_1884 = and(io.req.valid, io.req.ready) - node T_1885 = and(T_1884, cacheable) - node T_1886 = eq(io.req.bits.cmd, UInt<5>("h01")) - node T_1887 = eq(io.req.bits.cmd, UInt<5>("h07")) - node T_1888 = or(T_1886, T_1887) - node T_1889 = bits(io.req.bits.cmd, 3, 3) - node T_1890 = eq(io.req.bits.cmd, UInt<5>("h04")) - node T_1891 = or(T_1889, T_1890) - node T_1892 = or(T_1888, T_1891) - node sdq_enq = and(T_1885, T_1892) - cmem sdq : UInt<64>[17] - when sdq_enq : - infer mport T_1896 = sdq[sdq_alloc_id], clk - T_1896 <= io.req.bits.data - skip - wire idxMatch : UInt<1>[2] - idxMatch is invalid - wire tagList : UInt<20>[2] - tagList is invalid - node T_1922 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) - node T_1924 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) - node T_1926 = or(T_1922, T_1924) - wire T_1927 : UInt<20> - T_1927 is invalid - T_1927 <= T_1926 - node T_1928 = shr(io.req.bits.addr, 12) - node tag_match = eq(T_1927, T_1928) - wire wbTagList : UInt[2] - wbTagList is invalid - wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] - refillMux is invalid - inst meta_read_arb of Arbiter_93 - meta_read_arb.io is invalid - meta_read_arb.clk <= clk - meta_read_arb.reset <= reset - inst meta_write_arb of Arbiter_94 - meta_write_arb.io is invalid - meta_write_arb.clk <= clk - meta_write_arb.reset <= reset - inst mem_req_arb of LockingArbiter - mem_req_arb.io is invalid - mem_req_arb.clk <= clk - mem_req_arb.reset <= reset - inst wb_req_arb of Arbiter_95 - wb_req_arb.io is invalid - wb_req_arb.clk <= clk - wb_req_arb.reset <= reset - inst replay_arb of Arbiter_96 - replay_arb.io is invalid - replay_arb.clk <= clk - replay_arb.reset <= reset - inst alloc_arb of Arbiter_97 - alloc_arb.io is invalid - alloc_arb.clk <= clk - alloc_arb.reset <= reset - io.fence_rdy <= UInt<1>("h01") - io.probe_rdy <= UInt<1>("h01") - inst T_2714 of MSHR - T_2714.io is invalid - T_2714.clk <= clk - T_2714.reset <= reset - idxMatch[0] <= T_2714.io.idx_match - tagList[0] <= T_2714.io.tag - node T_2715 = shr(T_2714.io.wb_req.bits.addr_block, 6) - wbTagList[0] <= T_2715 - alloc_arb.io.in[0].valid <= T_2714.io.req_pri_rdy - T_2714.io.req_pri_val <= alloc_arb.io.in[0].ready - node T_2716 = and(io.req.valid, sdq_rdy) - node T_2717 = and(T_2716, tag_match) - T_2714.io.req_sec_val <= T_2717 - T_2714.io.req_bits <- io.req.bits - T_2714.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[0] <- T_2714.io.meta_read - meta_write_arb.io.in[0] <- T_2714.io.meta_write - mem_req_arb.io.in[0] <- T_2714.io.mem_req - wb_req_arb.io.in[0] <- T_2714.io.wb_req - replay_arb.io.in[0] <- T_2714.io.replay - node T_2719 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00")) - node T_2720 = and(io.mem_grant.valid, T_2719) - T_2714.io.mem_grant.valid <= T_2720 - T_2714.io.mem_grant.bits <- io.mem_grant.bits - refillMux[0] <- T_2714.io.refill - node T_2721 = or(UInt<1>("h00"), T_2714.io.req_pri_rdy) - node T_2722 = or(UInt<1>("h00"), T_2714.io.req_sec_rdy) - node T_2723 = or(UInt<1>("h00"), T_2714.io.idx_match) - node T_2725 = eq(T_2714.io.req_pri_rdy, UInt<1>("h00")) - when T_2725 : - io.fence_rdy <= UInt<1>("h00") - skip - node T_2728 = eq(T_2714.io.probe_rdy, UInt<1>("h00")) - when T_2728 : - io.probe_rdy <= UInt<1>("h00") - skip - inst T_2730 of MSHR_99 - T_2730.io is invalid - T_2730.clk <= clk - T_2730.reset <= reset - idxMatch[1] <= T_2730.io.idx_match - tagList[1] <= T_2730.io.tag - node T_2731 = shr(T_2730.io.wb_req.bits.addr_block, 6) - wbTagList[1] <= T_2731 - alloc_arb.io.in[1].valid <= T_2730.io.req_pri_rdy - T_2730.io.req_pri_val <= alloc_arb.io.in[1].ready - node T_2732 = and(io.req.valid, sdq_rdy) - node T_2733 = and(T_2732, tag_match) - T_2730.io.req_sec_val <= T_2733 - T_2730.io.req_bits <- io.req.bits - T_2730.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[1] <- T_2730.io.meta_read - meta_write_arb.io.in[1] <- T_2730.io.meta_write - mem_req_arb.io.in[1] <- T_2730.io.mem_req - wb_req_arb.io.in[1] <- T_2730.io.wb_req - replay_arb.io.in[1] <- T_2730.io.replay - node T_2735 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01")) - node T_2736 = and(io.mem_grant.valid, T_2735) - T_2730.io.mem_grant.valid <= T_2736 - T_2730.io.mem_grant.bits <- io.mem_grant.bits - refillMux[1] <- T_2730.io.refill - node pri_rdy = or(T_2721, T_2730.io.req_pri_rdy) - node sec_rdy = or(T_2722, T_2730.io.req_sec_rdy) - node idx_match = or(T_2723, T_2730.io.idx_match) - node T_2741 = eq(T_2730.io.req_pri_rdy, UInt<1>("h00")) - when T_2741 : - io.fence_rdy <= UInt<1>("h00") - skip - node T_2744 = eq(T_2730.io.probe_rdy, UInt<1>("h00")) - when T_2744 : - io.probe_rdy <= UInt<1>("h00") - skip - node T_2746 = and(io.req.valid, sdq_rdy) - node T_2747 = and(T_2746, cacheable) - node T_2749 = eq(idx_match, UInt<1>("h00")) - node T_2750 = and(T_2747, T_2749) - alloc_arb.io.out.ready <= T_2750 - io.meta_read <- meta_read_arb.io.out - io.meta_write <- meta_write_arb.io.out - io.mem_req <- mem_req_arb.io.out - io.wb_req <- wb_req_arb.io.out - inst mmio_alloc_arb of Arbiter_101 - mmio_alloc_arb.io is invalid - mmio_alloc_arb.clk <= clk - mmio_alloc_arb.reset <= reset - inst resp_arb of Arbiter_102 - resp_arb.io is invalid - resp_arb.clk <= clk - resp_arb.reset <= reset - inst T_2812 of IOMSHR - T_2812.io is invalid - T_2812.clk <= clk - T_2812.reset <= reset - mmio_alloc_arb.io.in[0].valid <= T_2812.io.req.ready - T_2812.io.req.valid <= mmio_alloc_arb.io.in[0].ready - T_2812.io.req.bits <- io.req.bits - node mmio_rdy = or(UInt<1>("h00"), T_2812.io.req.ready) - mem_req_arb.io.in[2] <- T_2812.io.acquire - T_2812.io.grant.bits <- io.mem_grant.bits - node T_2815 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02")) - node T_2816 = and(io.mem_grant.valid, T_2815) - T_2812.io.grant.valid <= T_2816 - resp_arb.io.in[0] <- T_2812.io.resp - node T_2818 = eq(T_2812.io.req.ready, UInt<1>("h00")) - when T_2818 : - io.fence_rdy <= UInt<1>("h00") - skip - node T_2821 = eq(cacheable, UInt<1>("h00")) - node T_2822 = and(io.req.valid, T_2821) - mmio_alloc_arb.io.out.ready <= T_2822 - io.resp <- resp_arb.io.out - node T_2824 = eq(cacheable, UInt<1>("h00")) - node T_2825 = and(tag_match, sec_rdy) - node T_2826 = mux(idx_match, T_2825, pri_rdy) - node T_2827 = and(T_2826, sdq_rdy) - node T_2828 = mux(T_2824, mmio_rdy, T_2827) - io.req.ready <= T_2828 - io.secondary_miss <= idx_match - io.refill <- refillMux[io.mem_grant.bits.client_xact_id] - node T_2878 = and(io.replay.ready, io.replay.valid) - node T_2879 = eq(io.replay.bits.cmd, UInt<5>("h01")) - node T_2880 = eq(io.replay.bits.cmd, UInt<5>("h07")) - node T_2881 = or(T_2879, T_2880) - node T_2882 = bits(io.replay.bits.cmd, 3, 3) - node T_2883 = eq(io.replay.bits.cmd, UInt<5>("h04")) - node T_2884 = or(T_2882, T_2883) - node T_2885 = or(T_2881, T_2884) - node free_sdq = and(T_2878, T_2885) - reg T_2887 : UInt<5>, clk - when free_sdq : - T_2887 <= replay_arb.io.out.bits.sdq_id - skip - infer mport T_2888 = sdq[T_2887], clk - io.replay.bits.data <= T_2888 - io.replay <- replay_arb.io.out - node T_2889 = or(io.replay.valid, sdq_enq) - when T_2889 : - node T_2891 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id) - node T_2893 = sub(UInt<17>("h00"), free_sdq) - node T_2894 = tail(T_2893, 1) - node T_2895 = and(T_2891, T_2894) - node T_2896 = not(T_2895) - node T_2897 = and(sdq_val, T_2896) - node T_2898 = bits(sdq_val, 16, 0) - node T_2899 = not(T_2898) - node T_2900 = bits(T_2899, 0, 0) - node T_2901 = bits(T_2899, 1, 1) - node T_2902 = bits(T_2899, 2, 2) - node T_2903 = bits(T_2899, 3, 3) - node T_2904 = bits(T_2899, 4, 4) - node T_2905 = bits(T_2899, 5, 5) - node T_2906 = bits(T_2899, 6, 6) - node T_2907 = bits(T_2899, 7, 7) - node T_2908 = bits(T_2899, 8, 8) - node T_2909 = bits(T_2899, 9, 9) - node T_2910 = bits(T_2899, 10, 10) - node T_2911 = bits(T_2899, 11, 11) - node T_2912 = bits(T_2899, 12, 12) - node T_2913 = bits(T_2899, 13, 13) - node T_2914 = bits(T_2899, 14, 14) - node T_2915 = bits(T_2899, 15, 15) - node T_2916 = bits(T_2899, 16, 16) - wire T_2935 : UInt<17>[17] - T_2935[0] <= UInt<17>("h01") - T_2935[1] <= UInt<17>("h02") - T_2935[2] <= UInt<17>("h04") - T_2935[3] <= UInt<17>("h08") - T_2935[4] <= UInt<17>("h010") - T_2935[5] <= UInt<17>("h020") - T_2935[6] <= UInt<17>("h040") - T_2935[7] <= UInt<17>("h080") - T_2935[8] <= UInt<17>("h0100") - T_2935[9] <= UInt<17>("h0200") - T_2935[10] <= UInt<17>("h0400") - T_2935[11] <= UInt<17>("h0800") - T_2935[12] <= UInt<17>("h01000") - T_2935[13] <= UInt<17>("h02000") - T_2935[14] <= UInt<17>("h04000") - T_2935[15] <= UInt<17>("h08000") - T_2935[16] <= UInt<17>("h010000") - node T_2956 = mux(T_2916, T_2935[16], UInt<17>("h00")) - node T_2957 = mux(T_2915, T_2935[15], T_2956) - node T_2958 = mux(T_2914, T_2935[14], T_2957) - node T_2959 = mux(T_2913, T_2935[13], T_2958) - node T_2960 = mux(T_2912, T_2935[12], T_2959) - node T_2961 = mux(T_2911, T_2935[11], T_2960) - node T_2962 = mux(T_2910, T_2935[10], T_2961) - node T_2963 = mux(T_2909, T_2935[9], T_2962) - node T_2964 = mux(T_2908, T_2935[8], T_2963) - node T_2965 = mux(T_2907, T_2935[7], T_2964) - node T_2966 = mux(T_2906, T_2935[6], T_2965) - node T_2967 = mux(T_2905, T_2935[5], T_2966) - node T_2968 = mux(T_2904, T_2935[4], T_2967) - node T_2969 = mux(T_2903, T_2935[3], T_2968) - node T_2970 = mux(T_2902, T_2935[2], T_2969) - node T_2971 = mux(T_2901, T_2935[1], T_2970) - node T_2972 = mux(T_2900, T_2935[0], T_2971) - node T_2974 = sub(UInt<17>("h00"), sdq_enq) - node T_2975 = tail(T_2974, 1) - node T_2976 = and(T_2972, T_2975) - node T_2977 = or(T_2897, T_2976) - sdq_val <= T_2977 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_48 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module MetadataArray : + extmodule AsyncResetReg_49 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_49 : + input clock : Clock input reset : UInt<1> - output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]} - - io is invalid - wire T_30 : {state : UInt<2>} - T_30 is invalid - T_30.state <= UInt<1>("h00") - wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} - rstVal is invalid - rstVal.tag <= UInt<1>("h00") - rstVal.coh <- T_30 - reg rst_cnt : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) - node rst = lt(rst_cnt, UInt<7>("h040")) - node waddr = mux(rst, rst_cnt, io.write.bits.idx) - node T_1633 = mux(rst, rstVal, io.write.bits.data) - node wdata = cat(T_1633.tag, T_1633.coh.state) - node T_1708 = asSInt(io.write.bits.way_en) - node T_1709 = mux(rst, asSInt(UInt<1>("h01")), T_1708) - node T_1710 = bits(T_1709, 0, 0) - node T_1711 = bits(T_1709, 1, 1) - node T_1712 = bits(T_1709, 2, 2) - node T_1713 = bits(T_1709, 3, 3) - wire wmask : UInt<1>[4] - wmask[0] <= T_1710 - wmask[1] <= T_1711 - wmask[2] <= T_1712 - wmask[3] <= T_1713 - when rst : - node T_1722 = add(rst_cnt, UInt<1>("h01")) - node T_1723 = tail(T_1722, 1) - rst_cnt <= T_1723 - skip - smem tag_arr : UInt<22>[4][64] - node T_1741 = or(rst, io.write.valid) - when T_1741 : - wire T_1743 : UInt<22>[4] - T_1743[0] <= wdata - T_1743[1] <= wdata - T_1743[2] <= wdata - T_1743[3] <= wdata - write mport T_1751 = tag_arr[waddr], clk - when wmask[0] : - T_1751[0] <= T_1743[0] - skip - when wmask[1] : - T_1751[1] <= T_1743[1] - skip - when wmask[2] : - T_1751[2] <= T_1743[2] - skip - when wmask[3] : - T_1751[3] <= T_1743[3] - skip - skip - wire T_1758 : UInt - T_1758 is invalid - when io.read.valid : - T_1758 <= io.read.bits.idx - skip - read mport T_1761 = tag_arr[T_1758], clk - node T_1767 = cat(T_1761[3], T_1761[2]) - node T_1768 = cat(T_1761[1], T_1761[0]) - node tags = cat(T_1767, T_1768) - wire T_2428 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_2428 is invalid - node T_2794 = bits(tags, 1, 0) - T_2428[0].coh.state <= T_2794 - node T_2795 = bits(tags, 21, 2) - T_2428[0].tag <= T_2795 - node T_2796 = bits(tags, 23, 22) - T_2428[1].coh.state <= T_2796 - node T_2797 = bits(tags, 43, 24) - T_2428[1].tag <= T_2797 - node T_2798 = bits(tags, 45, 44) - T_2428[2].coh.state <= T_2798 - node T_2799 = bits(tags, 65, 46) - T_2428[2].tag <= T_2799 - node T_2800 = bits(tags, 67, 66) - T_2428[3].coh.state <= T_2800 - node T_2801 = bits(tags, 87, 68) - T_2428[3].tag <= T_2801 - io.resp <= T_2428 - node T_2803 = eq(rst, UInt<1>("h00")) - node T_2805 = eq(io.write.valid, UInt<1>("h00")) - node T_2806 = and(T_2803, T_2805) - io.read.ready <= T_2806 - node T_2808 = eq(rst, UInt<1>("h00")) - io.write.ready <= T_2808 - - module Arbiter_105 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_49 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_50 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_50 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, chosen : UInt<3>} - - io is invalid - wire T_128 : UInt<3> - T_128 is invalid - io.out.valid <= io.in[T_128].valid - io.out.bits <- io.in[T_128].bits - io.chosen <= T_128 - io.in[T_128].ready <= UInt<1>("h00") - node T_153 = or(UInt<1>("h00"), io.in[0].valid) - node T_155 = eq(T_153, UInt<1>("h00")) - node T_157 = or(UInt<1>("h00"), io.in[0].valid) - node T_158 = or(T_157, io.in[1].valid) - node T_160 = eq(T_158, UInt<1>("h00")) - node T_162 = or(UInt<1>("h00"), io.in[0].valid) - node T_163 = or(T_162, io.in[1].valid) - node T_164 = or(T_163, io.in[2].valid) - node T_166 = eq(T_164, UInt<1>("h00")) - node T_168 = or(UInt<1>("h00"), io.in[0].valid) - node T_169 = or(T_168, io.in[1].valid) - node T_170 = or(T_169, io.in[2].valid) - node T_171 = or(T_170, io.in[3].valid) - node T_173 = eq(T_171, UInt<1>("h00")) - node T_175 = eq(UInt<3>("h04"), UInt<1>("h00")) - node T_176 = mux(UInt<1>("h00"), T_175, UInt<1>("h01")) - node T_177 = and(T_176, io.out.ready) - io.in[0].ready <= T_177 - node T_179 = eq(UInt<3>("h04"), UInt<1>("h01")) - node T_180 = mux(UInt<1>("h00"), T_179, T_155) - node T_181 = and(T_180, io.out.ready) - io.in[1].ready <= T_181 - node T_183 = eq(UInt<3>("h04"), UInt<2>("h02")) - node T_184 = mux(UInt<1>("h00"), T_183, T_160) - node T_185 = and(T_184, io.out.ready) - io.in[2].ready <= T_185 - node T_187 = eq(UInt<3>("h04"), UInt<2>("h03")) - node T_188 = mux(UInt<1>("h00"), T_187, T_166) - node T_189 = and(T_188, io.out.ready) - io.in[3].ready <= T_189 - node T_191 = eq(UInt<3>("h04"), UInt<3>("h04")) - node T_192 = mux(UInt<1>("h00"), T_191, T_173) - node T_193 = and(T_192, io.out.ready) - io.in[4].ready <= T_193 - node T_196 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) - node T_198 = mux(io.in[2].valid, UInt<2>("h02"), T_196) - node T_200 = mux(io.in[1].valid, UInt<1>("h01"), T_198) - node T_202 = mux(io.in[0].valid, UInt<1>("h00"), T_200) - node T_203 = mux(UInt<1>("h00"), UInt<3>("h04"), T_202) - T_128 <= T_203 - - module DataArray : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_50 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_51 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_51 : + input clock : Clock input reset : UInt<1> - output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]} + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} io is invalid - node waddr = shr(io.write.bits.addr, 4) - node raddr = shr(io.read.bits.addr, 4) - node T_572 = bits(io.write.bits.way_en, 1, 0) - node T_573 = bits(io.read.bits.way_en, 1, 0) - wire T_582 : UInt<128>[2] - T_582 is invalid - reg T_586 : UInt<12>, clk - when io.read.valid : - T_586 <= io.read.bits.addr - skip - smem T_599 : UInt<64>[2][256] - node T_601 = neq(T_572, UInt<1>("h00")) - node T_602 = and(T_601, io.write.valid) - node T_603 = bits(io.write.bits.wmask, 0, 0) - node T_604 = and(T_602, T_603) - when T_604 : - node T_605 = bits(io.write.bits.data, 63, 0) - node T_606 = bits(io.write.bits.data, 63, 0) - wire T_608 : UInt<64>[2] - T_608[0] <= T_605 - T_608[1] <= T_606 - node T_612 = bits(T_572, 0, 0) - node T_613 = bits(T_572, 1, 1) - wire T_615 : UInt<1>[2] - T_615[0] <= T_612 - T_615[1] <= T_613 - write mport T_621 = T_599[waddr], clk - when T_615[0] : - T_621[0] <= T_608[0] - skip - when T_615[1] : - T_621[1] <= T_608[1] - skip - skip - node T_626 = neq(T_573, UInt<1>("h00")) - node T_627 = and(T_626, io.read.valid) - wire T_629 : UInt - T_629 is invalid - when T_627 : - T_629 <= raddr - skip - read mport T_632 = T_599[T_629], clk - node T_636 = cat(T_632[1], T_632[0]) - T_582[0] <= T_636 - smem T_649 : UInt<64>[2][256] - node T_651 = neq(T_572, UInt<1>("h00")) - node T_652 = and(T_651, io.write.valid) - node T_653 = bits(io.write.bits.wmask, 1, 1) - node T_654 = and(T_652, T_653) - when T_654 : - node T_655 = bits(io.write.bits.data, 127, 64) - node T_656 = bits(io.write.bits.data, 127, 64) - wire T_658 : UInt<64>[2] - T_658[0] <= T_655 - T_658[1] <= T_656 - node T_662 = bits(T_572, 0, 0) - node T_663 = bits(T_572, 1, 1) - wire T_665 : UInt<1>[2] - T_665[0] <= T_662 - T_665[1] <= T_663 - write mport T_671 = T_649[waddr], clk - when T_665[0] : - T_671[0] <= T_658[0] - skip - when T_665[1] : - T_671[1] <= T_658[1] - skip - skip - node T_676 = neq(T_573, UInt<1>("h00")) - node T_677 = and(T_676, io.read.valid) - wire T_679 : UInt - T_679 is invalid - when T_677 : - T_679 <= raddr - skip - read mport T_682 = T_649[T_679], clk - node T_686 = cat(T_682[1], T_682[0]) - T_582[1] <= T_686 - node T_687 = bits(T_582[0], 63, 0) - node T_688 = bits(T_582[1], 63, 0) - wire T_690 : UInt<64>[2] - T_690[0] <= T_687 - T_690[1] <= T_688 - node T_694 = bits(T_586, 3, 3) - wire T_697 : UInt<64>[2] - T_697[0] <= T_690[T_694] - T_697[1] <= T_690[1] - node T_701 = cat(T_697[1], T_697[0]) - io.resp[0] <= T_701 - node T_702 = bits(T_582[0], 127, 64) - node T_703 = bits(T_582[1], 127, 64) - wire T_705 : UInt<64>[2] - T_705[0] <= T_702 - T_705[1] <= T_703 - node T_709 = bits(T_586, 3, 3) - wire T_712 : UInt<64>[2] - T_712[0] <= T_705[T_709] - T_712[1] <= T_705[1] - node T_716 = cat(T_712[1], T_712[0]) - io.resp[1] <= T_716 - node T_717 = bits(io.write.bits.way_en, 3, 2) - node T_718 = bits(io.read.bits.way_en, 3, 2) - wire T_727 : UInt<128>[2] - T_727 is invalid - reg T_731 : UInt<12>, clk - when io.read.valid : - T_731 <= io.read.bits.addr - skip - smem T_744 : UInt<64>[2][256] - node T_746 = neq(T_717, UInt<1>("h00")) - node T_747 = and(T_746, io.write.valid) - node T_748 = bits(io.write.bits.wmask, 0, 0) - node T_749 = and(T_747, T_748) - when T_749 : - node T_750 = bits(io.write.bits.data, 63, 0) - node T_751 = bits(io.write.bits.data, 63, 0) - wire T_753 : UInt<64>[2] - T_753[0] <= T_750 - T_753[1] <= T_751 - node T_757 = bits(T_717, 0, 0) - node T_758 = bits(T_717, 1, 1) - wire T_760 : UInt<1>[2] - T_760[0] <= T_757 - T_760[1] <= T_758 - write mport T_766 = T_744[waddr], clk - when T_760[0] : - T_766[0] <= T_753[0] - skip - when T_760[1] : - T_766[1] <= T_753[1] - skip - skip - node T_771 = neq(T_718, UInt<1>("h00")) - node T_772 = and(T_771, io.read.valid) - wire T_774 : UInt - T_774 is invalid - when T_772 : - T_774 <= raddr - skip - read mport T_777 = T_744[T_774], clk - node T_781 = cat(T_777[1], T_777[0]) - T_727[0] <= T_781 - smem T_794 : UInt<64>[2][256] - node T_796 = neq(T_717, UInt<1>("h00")) - node T_797 = and(T_796, io.write.valid) - node T_798 = bits(io.write.bits.wmask, 1, 1) - node T_799 = and(T_797, T_798) - when T_799 : - node T_800 = bits(io.write.bits.data, 127, 64) - node T_801 = bits(io.write.bits.data, 127, 64) - wire T_803 : UInt<64>[2] - T_803[0] <= T_800 - T_803[1] <= T_801 - node T_807 = bits(T_717, 0, 0) - node T_808 = bits(T_717, 1, 1) - wire T_810 : UInt<1>[2] - T_810[0] <= T_807 - T_810[1] <= T_808 - write mport T_816 = T_794[waddr], clk - when T_810[0] : - T_816[0] <= T_803[0] - skip - when T_810[1] : - T_816[1] <= T_803[1] - skip - skip - node T_821 = neq(T_718, UInt<1>("h00")) - node T_822 = and(T_821, io.read.valid) - wire T_824 : UInt - T_824 is invalid - when T_822 : - T_824 <= raddr - skip - read mport T_827 = T_794[T_824], clk - node T_831 = cat(T_827[1], T_827[0]) - T_727[1] <= T_831 - node T_832 = bits(T_727[0], 63, 0) - node T_833 = bits(T_727[1], 63, 0) - wire T_835 : UInt<64>[2] - T_835[0] <= T_832 - T_835[1] <= T_833 - node T_839 = bits(T_731, 3, 3) - wire T_842 : UInt<64>[2] - T_842[0] <= T_835[T_839] - T_842[1] <= T_835[1] - node T_846 = cat(T_842[1], T_842[0]) - io.resp[2] <= T_846 - node T_847 = bits(T_727[0], 127, 64) - node T_848 = bits(T_727[1], 127, 64) - wire T_850 : UInt<64>[2] - T_850[0] <= T_847 - T_850[1] <= T_848 - node T_854 = bits(T_731, 3, 3) - wire T_857 : UInt<64>[2] - T_857[0] <= T_850[T_854] - T_857[1] <= T_850[1] - node T_861 = cat(T_857[1], T_857[0]) - io.resp[3] <= T_861 - io.read.ready <= UInt<1>("h01") - io.write.ready <= UInt<1>("h01") - - module Arbiter_107 : + io is invalid + inst reg_0 of AsyncResetReg_51 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_52 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_52 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>} - - io is invalid - wire T_1524 : UInt<2> - T_1524 is invalid - io.out.valid <= io.in[T_1524].valid - io.out.bits <- io.in[T_1524].bits - io.chosen <= T_1524 - io.in[T_1524].ready <= UInt<1>("h00") - node T_1831 = or(UInt<1>("h00"), io.in[0].valid) - node T_1833 = eq(T_1831, UInt<1>("h00")) - node T_1835 = or(UInt<1>("h00"), io.in[0].valid) - node T_1836 = or(T_1835, io.in[1].valid) - node T_1838 = eq(T_1836, UInt<1>("h00")) - node T_1840 = or(UInt<1>("h00"), io.in[0].valid) - node T_1841 = or(T_1840, io.in[1].valid) - node T_1842 = or(T_1841, io.in[2].valid) - node T_1844 = eq(T_1842, UInt<1>("h00")) - node T_1846 = eq(UInt<2>("h03"), UInt<1>("h00")) - node T_1847 = mux(UInt<1>("h00"), T_1846, UInt<1>("h01")) - node T_1848 = and(T_1847, io.out.ready) - io.in[0].ready <= T_1848 - node T_1850 = eq(UInt<2>("h03"), UInt<1>("h01")) - node T_1851 = mux(UInt<1>("h00"), T_1850, T_1833) - node T_1852 = and(T_1851, io.out.ready) - io.in[1].ready <= T_1852 - node T_1854 = eq(UInt<2>("h03"), UInt<2>("h02")) - node T_1855 = mux(UInt<1>("h00"), T_1854, T_1838) - node T_1856 = and(T_1855, io.out.ready) - io.in[2].ready <= T_1856 - node T_1858 = eq(UInt<2>("h03"), UInt<2>("h03")) - node T_1859 = mux(UInt<1>("h00"), T_1858, T_1844) - node T_1860 = and(T_1859, io.out.ready) - io.in[3].ready <= T_1860 - node T_1863 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) - node T_1865 = mux(io.in[1].valid, UInt<1>("h01"), T_1863) - node T_1867 = mux(io.in[0].valid, UInt<1>("h00"), T_1865) - node T_1868 = mux(UInt<1>("h00"), UInt<2>("h03"), T_1867) - T_1524 <= T_1868 - - module Arbiter_108 : - input clk : Clock + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_52 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_9 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>} - - io is invalid - wire T_1164 : UInt<1> - T_1164 is invalid - io.out.valid <= io.in[T_1164].valid - io.out.bits <- io.in[T_1164].bits - io.chosen <= T_1164 - io.in[T_1164].ready <= UInt<1>("h00") - node T_1483 = or(UInt<1>("h00"), io.in[0].valid) - node T_1485 = eq(T_1483, UInt<1>("h00")) - node T_1487 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1488 = mux(UInt<1>("h00"), T_1487, UInt<1>("h01")) - node T_1489 = and(T_1488, io.out.ready) - io.in[0].ready <= T_1489 - node T_1491 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_1492 = mux(UInt<1>("h00"), T_1491, T_1485) - node T_1493 = and(T_1492, io.out.ready) - io.in[1].ready <= T_1493 - node T_1496 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_1497 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1496) - T_1164 <= T_1497 + output io : {flip in : UInt<1>, out : UInt<1>} - module AMOALU : + io is invalid + io is invalid + inst sink_valid_sync_0 of AsyncResetRegVec_49 @[AsyncQueue.scala 18:14] + sink_valid_sync_0.io is invalid + sink_valid_sync_0.clock <= clock + sink_valid_sync_0.reset <= reset + inst sink_valid_sync_1 of AsyncResetRegVec_50 @[AsyncQueue.scala 18:14] + sink_valid_sync_1.io is invalid + sink_valid_sync_1.clock <= clock + sink_valid_sync_1.reset <= reset + inst sink_valid_sync_2 of AsyncResetRegVec_51 @[AsyncQueue.scala 18:14] + sink_valid_sync_2.io is invalid + sink_valid_sync_2.clock <= clock + sink_valid_sync_2.reset <= reset + inst sink_valid_sync_3 of AsyncResetRegVec_52 @[AsyncQueue.scala 18:14] + sink_valid_sync_3.io is invalid + sink_valid_sync_3.clock <= clock + sink_valid_sync_3.reset <= reset + sink_valid_sync_3.io.d <= io.in @[AsyncQueue.scala 20:21] + sink_valid_sync_3.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + sink_valid_sync_0.io.d <= sink_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_1.io.d <= sink_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + sink_valid_sync_2.io.d <= sink_valid_sync_3.io.q @[AsyncQueue.scala 23:19] + sink_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_10 = bits(sink_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_10 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_53 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_53 : + input clock : Clock + input reset : UInt<1> + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_53 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_10 : + input clock : Clock input reset : UInt<1> - output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} - - io is invalid - node T_10 = bits(io.typ, 1, 0) - node T_12 = eq(T_10, UInt<2>("h02")) - node T_13 = bits(io.rhs, 31, 0) - node T_14 = cat(T_13, T_13) - node rhs = mux(T_12, T_14, io.rhs) - node T_16 = eq(io.cmd, UInt<5>("h0c")) - node T_17 = eq(io.cmd, UInt<5>("h0d")) - node sgned = or(T_16, T_17) - node T_19 = eq(io.cmd, UInt<5>("h0d")) - node T_20 = eq(io.cmd, UInt<5>("h0f")) - node max = or(T_19, T_20) - node T_22 = eq(io.cmd, UInt<5>("h0c")) - node T_23 = eq(io.cmd, UInt<5>("h0e")) - node min = or(T_22, T_23) - node T_25 = eq(io.typ, UInt<3>("h02")) - node T_26 = eq(io.typ, UInt<3>("h06")) - node T_27 = or(T_25, T_26) - node T_28 = eq(io.typ, UInt<3>("h00")) - node T_29 = or(T_27, T_28) - node T_30 = eq(io.typ, UInt<3>("h04")) - node word = or(T_29, T_30) - node T_33 = not(UInt<64>("h00")) - node T_34 = bits(io.addr, 2, 2) - node T_35 = shl(T_34, 31) - node mask = xor(T_33, T_35) - node T_37 = and(io.lhs, mask) - node T_38 = and(rhs, mask) - node T_39 = add(T_37, T_38) - node adder_out = tail(T_39, 1) - node T_41 = bits(io.addr, 2, 2) - node T_43 = eq(T_41, UInt<1>("h00")) - node T_44 = and(word, T_43) - node T_45 = bits(io.lhs, 31, 31) - node T_46 = bits(io.lhs, 63, 63) - node cmp_lhs = mux(T_44, T_45, T_46) - node T_48 = bits(io.addr, 2, 2) - node T_50 = eq(T_48, UInt<1>("h00")) - node T_51 = and(word, T_50) - node T_52 = bits(rhs, 31, 31) - node T_53 = bits(rhs, 63, 63) - node cmp_rhs = mux(T_51, T_52, T_53) - node T_55 = bits(io.lhs, 31, 0) - node T_56 = bits(rhs, 31, 0) - node lt_lo = lt(T_55, T_56) - node T_58 = bits(io.lhs, 63, 32) - node T_59 = bits(rhs, 63, 32) - node lt_hi = lt(T_58, T_59) - node T_61 = bits(io.lhs, 63, 32) - node T_62 = bits(rhs, 63, 32) - node eq_hi = eq(T_61, T_62) - node T_64 = bits(io.addr, 2, 2) - node T_65 = mux(T_64, lt_hi, lt_lo) - node T_66 = and(eq_hi, lt_lo) - node T_67 = or(lt_hi, T_66) - node lt = mux(word, T_65, T_67) - node T_69 = eq(cmp_lhs, cmp_rhs) - node T_70 = mux(sgned, cmp_lhs, cmp_rhs) - node less = mux(T_69, lt, T_70) - node T_72 = eq(io.cmd, UInt<5>("h08")) - node T_73 = eq(io.cmd, UInt<5>("h0b")) - node T_74 = and(io.lhs, rhs) - node T_75 = eq(io.cmd, UInt<5>("h0a")) - node T_76 = or(io.lhs, rhs) - node T_77 = eq(io.cmd, UInt<5>("h09")) - node T_78 = xor(io.lhs, rhs) - node T_79 = mux(less, min, max) - node T_81 = eq(T_10, UInt<1>("h00")) - node T_82 = bits(io.rhs, 7, 0) - node T_83 = cat(T_82, T_82) - node T_84 = cat(T_83, T_83) - node T_85 = cat(T_84, T_84) - node T_87 = eq(T_10, UInt<1>("h01")) - node T_88 = bits(io.rhs, 15, 0) - node T_89 = cat(T_88, T_88) - node T_90 = cat(T_89, T_89) - node T_92 = eq(T_10, UInt<2>("h02")) - node T_93 = bits(io.rhs, 31, 0) - node T_94 = cat(T_93, T_93) - node T_95 = mux(T_92, T_94, io.rhs) - node T_96 = mux(T_87, T_90, T_95) - node T_97 = mux(T_81, T_85, T_96) - node T_98 = mux(T_79, io.lhs, T_97) - node T_99 = mux(T_77, T_78, T_98) - node T_100 = mux(T_75, T_76, T_99) - node T_101 = mux(T_73, T_74, T_100) - node out = mux(T_72, adder_out, T_101) - node T_104 = bits(io.addr, 0, 0) - node T_106 = mux(T_104, UInt<1>("h01"), UInt<1>("h00")) - node T_108 = geq(T_10, UInt<1>("h01")) - node T_111 = mux(T_108, UInt<1>("h01"), UInt<1>("h00")) - node T_112 = or(T_106, T_111) - node T_113 = bits(io.addr, 0, 0) - node T_115 = mux(T_113, UInt<1>("h00"), UInt<1>("h01")) - node T_116 = cat(T_112, T_115) - node T_117 = bits(io.addr, 1, 1) - node T_119 = mux(T_117, T_116, UInt<1>("h00")) - node T_121 = geq(T_10, UInt<2>("h02")) - node T_124 = mux(T_121, UInt<2>("h03"), UInt<1>("h00")) - node T_125 = or(T_119, T_124) - node T_126 = bits(io.addr, 1, 1) - node T_128 = mux(T_126, UInt<1>("h00"), T_116) - node T_129 = cat(T_125, T_128) - node T_130 = bits(io.addr, 2, 2) - node T_132 = mux(T_130, T_129, UInt<1>("h00")) - node T_134 = geq(T_10, UInt<2>("h03")) - node T_137 = mux(T_134, UInt<4>("h0f"), UInt<1>("h00")) - node T_138 = or(T_132, T_137) - node T_139 = bits(io.addr, 2, 2) - node T_141 = mux(T_139, UInt<1>("h00"), T_129) - node T_142 = cat(T_138, T_141) - node T_143 = bits(T_142, 0, 0) - node T_144 = bits(T_142, 1, 1) - node T_145 = bits(T_142, 2, 2) - node T_146 = bits(T_142, 3, 3) - node T_147 = bits(T_142, 4, 4) - node T_148 = bits(T_142, 5, 5) - node T_149 = bits(T_142, 6, 6) - node T_150 = bits(T_142, 7, 7) - wire T_152 : UInt<1>[8] - T_152[0] <= T_143 - T_152[1] <= T_144 - T_152[2] <= T_145 - T_152[3] <= T_146 - T_152[4] <= T_147 - T_152[5] <= T_148 - T_152[6] <= T_149 - T_152[7] <= T_150 - node T_163 = sub(UInt<8>("h00"), T_152[0]) - node T_164 = tail(T_163, 1) - node T_166 = sub(UInt<8>("h00"), T_152[1]) - node T_167 = tail(T_166, 1) - node T_169 = sub(UInt<8>("h00"), T_152[2]) - node T_170 = tail(T_169, 1) - node T_172 = sub(UInt<8>("h00"), T_152[3]) - node T_173 = tail(T_172, 1) - node T_175 = sub(UInt<8>("h00"), T_152[4]) - node T_176 = tail(T_175, 1) - node T_178 = sub(UInt<8>("h00"), T_152[5]) - node T_179 = tail(T_178, 1) - node T_181 = sub(UInt<8>("h00"), T_152[6]) - node T_182 = tail(T_181, 1) - node T_184 = sub(UInt<8>("h00"), T_152[7]) - node T_185 = tail(T_184, 1) - wire T_187 : UInt<8>[8] - T_187[0] <= T_164 - T_187[1] <= T_167 - T_187[2] <= T_170 - T_187[3] <= T_173 - T_187[4] <= T_176 - T_187[5] <= T_179 - T_187[6] <= T_182 - T_187[7] <= T_185 - node T_197 = cat(T_187[7], T_187[6]) - node T_198 = cat(T_187[5], T_187[4]) - node T_199 = cat(T_197, T_198) - node T_200 = cat(T_187[3], T_187[2]) - node T_201 = cat(T_187[1], T_187[0]) - node T_202 = cat(T_200, T_201) - node wmask = cat(T_199, T_202) - node T_204 = and(wmask, out) - node T_205 = not(wmask) - node T_206 = and(T_205, io.lhs) - node T_207 = or(T_204, T_206) - io.out <= T_207 - - module LockingArbiter_109 : + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst source_extend_sync_0 of AsyncResetRegVec_53 @[AsyncQueue.scala 18:14] + source_extend_sync_0.io is invalid + source_extend_sync_0.clock <= clock + source_extend_sync_0.reset <= reset + source_extend_sync_0.io.d <= io.in @[AsyncQueue.scala 20:21] + source_extend_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + node _T_7 = bits(source_extend_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_7 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_54 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_54 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, chosen : UInt<1>} - - io is invalid - reg T_700 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_702 : UInt, clk with : (reset => (reset, UInt<1>("h01"))) - wire T_704 : UInt<1> - T_704 is invalid - io.out.valid <= io.in[T_704].valid - io.out.bits <- io.in[T_704].bits - io.chosen <= T_704 - io.in[T_704].ready <= UInt<1>("h00") - node T_897 = or(UInt<1>("h00"), io.in[0].valid) - node T_899 = eq(T_897, UInt<1>("h00")) - node T_901 = eq(T_702, UInt<1>("h00")) - node T_902 = mux(T_700, T_901, UInt<1>("h01")) - node T_903 = and(T_902, io.out.ready) - io.in[0].ready <= T_903 - node T_905 = eq(T_702, UInt<1>("h01")) - node T_906 = mux(T_700, T_905, T_899) - node T_907 = and(T_906, io.out.ready) - io.in[1].ready <= T_907 - reg T_909 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - node T_911 = add(T_909, UInt<1>("h01")) - node T_912 = tail(T_911, 1) - node T_913 = and(io.out.ready, io.out.valid) - when T_913 : - wire T_916 : UInt<2>[3] - T_916[0] <= UInt<1>("h00") - T_916[1] <= UInt<1>("h01") - T_916[2] <= UInt<2>("h02") - node T_921 = eq(T_916[0], io.out.bits.r_type) - node T_922 = eq(T_916[1], io.out.bits.r_type) - node T_923 = eq(T_916[2], io.out.bits.r_type) - node T_925 = or(UInt<1>("h00"), T_921) - node T_926 = or(T_925, T_922) - node T_927 = or(T_926, T_923) - node T_928 = and(UInt<1>("h01"), T_927) - when T_928 : - T_909 <= T_912 - node T_930 = eq(T_700, UInt<1>("h00")) - when T_930 : - T_700 <= UInt<1>("h01") - node T_932 = and(io.in[0].ready, io.in[0].valid) - node T_933 = and(io.in[1].ready, io.in[1].valid) - wire T_935 : UInt<1>[2] - T_935[0] <= T_932 - T_935[1] <= T_933 - node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01")) - T_702 <= T_941 - skip - skip - node T_943 = eq(T_912, UInt<1>("h00")) - when T_943 : - T_700 <= UInt<1>("h00") - skip - skip - node choose = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_948 = mux(T_700, T_702, choose) - T_704 <= T_948 + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_54 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] - module HellaCache : + extmodule AsyncResetReg_55 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_55 : + input clock : Clock input reset : UInt<1> - output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - - io is invalid - inst wb of WritebackUnit - wb.io is invalid - wb.clk <= clk - wb.reset <= reset - inst prober of ProbeUnit - prober.io is invalid - prober.clk <= clk - prober.reset <= reset - inst mshrs of MSHRFile - mshrs.io is invalid - mshrs.clk <= clk - mshrs.reset <= reset - io.cpu.req.ready <= UInt<1>("h01") - node T_1622 = and(io.cpu.req.ready, io.cpu.req.valid) - reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - s1_valid <= T_1622 - reg s1_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk - node T_1680 = eq(io.cpu.req.bits.kill, UInt<1>("h00")) - node s1_valid_masked = and(s1_valid, T_1680) - reg s1_replay : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s1_clk_en : UInt<1>, clk - reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - s2_valid <= s1_valid_masked - node T_1688 = and(s1_valid, io.cpu.req.bits.kill) - reg s2_killed : UInt<1>, clk - s2_killed <= T_1688 - reg s2_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk - reg T_1745 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_1745 <= s1_replay - node T_1746 = neq(s2_req.cmd, UInt<5>("h05")) - node s2_replay = and(T_1745, T_1746) - wire s2_recycle : UInt<1> - s2_recycle is invalid - wire s2_valid_masked : UInt<1> - s2_valid_masked is invalid - reg s3_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk - reg s3_way : UInt, clk - reg s1_recycled : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - when s1_clk_en : - s1_recycled <= s2_recycle - skip - node T_1812 = eq(s1_req.cmd, UInt<5>("h00")) - node T_1813 = eq(s1_req.cmd, UInt<5>("h06")) - node T_1814 = or(T_1812, T_1813) - node T_1815 = eq(s1_req.cmd, UInt<5>("h07")) - node T_1816 = or(T_1814, T_1815) - node T_1817 = bits(s1_req.cmd, 3, 3) - node T_1818 = eq(s1_req.cmd, UInt<5>("h04")) - node T_1819 = or(T_1817, T_1818) - node s1_read = or(T_1816, T_1819) - node T_1821 = eq(s1_req.cmd, UInt<5>("h01")) - node T_1822 = eq(s1_req.cmd, UInt<5>("h07")) - node T_1823 = or(T_1821, T_1822) - node T_1824 = bits(s1_req.cmd, 3, 3) - node T_1825 = eq(s1_req.cmd, UInt<5>("h04")) - node T_1826 = or(T_1824, T_1825) - node s1_write = or(T_1823, T_1826) - node T_1828 = or(s1_read, s1_write) - node T_1829 = eq(s1_req.cmd, UInt<5>("h02")) - node T_1830 = eq(s1_req.cmd, UInt<5>("h03")) - node T_1831 = or(T_1829, T_1830) - node s1_readwrite = or(T_1828, T_1831) - inst dtlb of TLB - dtlb.io is invalid - dtlb.clk <= clk - dtlb.reset <= reset - io.ptw <- dtlb.io.ptw - node T_1834 = and(s1_valid_masked, s1_readwrite) - node T_1836 = eq(s1_req.phys, UInt<1>("h00")) - node T_1837 = and(T_1834, T_1836) - dtlb.io.req.valid <= T_1837 - dtlb.io.req.bits.passthrough <= s1_req.phys - dtlb.io.req.bits.asid <= UInt<1>("h00") - node T_1839 = shr(s1_req.addr, 12) - dtlb.io.req.bits.vpn <= T_1839 - dtlb.io.req.bits.instruction <= UInt<1>("h00") - dtlb.io.req.bits.store <= s1_write - node T_1842 = eq(dtlb.io.req.ready, UInt<1>("h00")) - node T_1844 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) - node T_1845 = and(T_1842, T_1844) - when T_1845 : - io.cpu.req.ready <= UInt<1>("h00") - skip - when io.cpu.req.valid : - s1_req <- io.cpu.req.bits - skip - when wb.io.meta_read.valid : - node T_1847 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) - node T_1848 = shl(T_1847, 6) - s1_req.addr <= T_1848 - s1_req.phys <= UInt<1>("h01") - skip - when prober.io.meta_read.valid : - node T_1850 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) - node T_1851 = shl(T_1850, 6) - s1_req.addr <= T_1851 - s1_req.phys <= UInt<1>("h01") - skip - when mshrs.io.replay.valid : - s1_req <- mshrs.io.replay.bits - skip - when s2_recycle : - s1_req <- s2_req - skip - node T_1853 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.io.resp.ppn, T_1853) - when s1_clk_en : - s2_req.kill <= s1_req.kill - s2_req.typ <= s1_req.typ - s2_req.phys <= s1_req.phys - s2_req.addr <= s1_addr - when s1_write : - node T_1855 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) - s2_req.data <= T_1855 - skip - when s1_recycled : - s2_req.data <= s1_req.data - skip - s2_req.tag <= s1_req.tag - s2_req.cmd <= s1_req.cmd - skip - node T_1857 = bits(s1_req.typ, 1, 0) - node T_1859 = dshl(UInt<1>("h01"), T_1857) - node T_1861 = sub(T_1859, UInt<1>("h01")) - node T_1862 = tail(T_1861, 1) - node T_1863 = bits(T_1862, 2, 0) - node T_1864 = and(s1_req.addr, T_1863) - node misaligned = neq(T_1864, UInt<1>("h00")) - node T_1867 = and(s1_read, misaligned) - io.cpu.xcpt.ma.ld <= T_1867 - node T_1868 = and(s1_write, misaligned) - io.cpu.xcpt.ma.st <= T_1868 - node T_1869 = and(s1_read, dtlb.io.resp.xcpt_ld) - io.cpu.xcpt.pf.ld <= T_1869 - node T_1870 = and(s1_write, dtlb.io.resp.xcpt_st) - io.cpu.xcpt.pf.st <= T_1870 - node T_1871 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) - node T_1872 = or(T_1871, io.cpu.xcpt.pf.ld) - node T_1873 = or(T_1872, io.cpu.xcpt.pf.st) - reg T_1874 : UInt<1>, clk - T_1874 <= T_1873 - node T_1875 = and(T_1874, io.cpu.resp.valid) - node T_1877 = eq(T_1875, UInt<1>("h00")) - node T_1879 = eq(reset, UInt<1>("h00")) - when T_1879 : - node T_1881 = eq(T_1877, UInt<1>("h00")) - when T_1881 : - node T_1883 = eq(reset, UInt<1>("h00")) - when T_1883 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - inst meta of MetadataArray - meta.io is invalid - meta.clk <= clk - meta.reset <= reset - inst metaReadArb of Arbiter_105 - metaReadArb.io is invalid - metaReadArb.clk <= clk - metaReadArb.reset <= reset - inst metaWriteArb of Arbiter_94 - metaWriteArb.io is invalid - metaWriteArb.clk <= clk - metaWriteArb.reset <= reset - meta.io.read <- metaReadArb.io.out - meta.io.write <- metaWriteArb.io.out - inst data of DataArray - data.io is invalid - data.clk <= clk - data.reset <= reset - inst readArb of Arbiter_107 - readArb.io is invalid - readArb.clk <= clk - readArb.reset <= reset - inst writeArb of Arbiter_108 - writeArb.io is invalid - writeArb.clk <= clk - writeArb.reset <= reset - data.io.write.valid <= writeArb.io.out.valid - writeArb.io.out.ready <= data.io.write.ready - data.io.write.bits <- writeArb.io.out.bits - node T_2141 = bits(writeArb.io.out.bits.data, 63, 0) - node T_2142 = bits(writeArb.io.out.bits.data, 127, 64) - wire T_2144 : UInt<64>[2] - T_2144[0] <= T_2141 - T_2144[1] <= T_2142 - node T_2148 = cat(T_2144[1], T_2144[0]) - data.io.write.bits.data <= T_2148 - metaReadArb.io.in[4].valid <= io.cpu.req.valid - node T_2149 = shr(io.cpu.req.bits.addr, 6) - metaReadArb.io.in[4].bits.idx <= T_2149 - node T_2151 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00")) - when T_2151 : - io.cpu.req.ready <= UInt<1>("h00") - skip - readArb.io.in[3].valid <= io.cpu.req.valid - readArb.io.in[3].bits.addr <= io.cpu.req.bits.addr - node T_2154 = not(UInt<4>("h00")) - readArb.io.in[3].bits.way_en <= T_2154 - node T_2156 = eq(readArb.io.in[3].ready, UInt<1>("h00")) - when T_2156 : - io.cpu.req.ready <= UInt<1>("h00") - skip - metaReadArb.io.in[0].valid <= s2_recycle - node T_2158 = shr(s2_req.addr, 6) - metaReadArb.io.in[0].bits.idx <= T_2158 - readArb.io.in[0].valid <= s2_recycle - readArb.io.in[0].bits.addr <= s2_req.addr - node T_2160 = not(UInt<4>("h00")) - readArb.io.in[0].bits.way_en <= T_2160 - node T_2161 = shr(s1_addr, 12) - node T_2162 = eq(meta.io.resp[0].tag, T_2161) - node T_2163 = shr(s1_addr, 12) - node T_2164 = eq(meta.io.resp[1].tag, T_2163) - node T_2165 = shr(s1_addr, 12) - node T_2166 = eq(meta.io.resp[2].tag, T_2165) - node T_2167 = shr(s1_addr, 12) - node T_2168 = eq(meta.io.resp[3].tag, T_2167) - wire T_2170 : UInt<1>[4] - T_2170[0] <= T_2162 - T_2170[1] <= T_2164 - T_2170[2] <= T_2166 - T_2170[3] <= T_2168 - node T_2176 = cat(T_2170[3], T_2170[2]) - node T_2177 = cat(T_2170[1], T_2170[0]) - node s1_tag_eq_way = cat(T_2176, T_2177) - node T_2179 = bits(s1_tag_eq_way, 0, 0) - node T_2180 = neq(meta.io.resp[0].coh.state, UInt<1>("h00")) - node T_2181 = and(T_2179, T_2180) - node T_2182 = bits(s1_tag_eq_way, 1, 1) - node T_2183 = neq(meta.io.resp[1].coh.state, UInt<1>("h00")) - node T_2184 = and(T_2182, T_2183) - node T_2185 = bits(s1_tag_eq_way, 2, 2) - node T_2186 = neq(meta.io.resp[2].coh.state, UInt<1>("h00")) - node T_2187 = and(T_2185, T_2186) - node T_2188 = bits(s1_tag_eq_way, 3, 3) - node T_2189 = neq(meta.io.resp[3].coh.state, UInt<1>("h00")) - node T_2190 = and(T_2188, T_2189) - wire T_2192 : UInt<1>[4] - T_2192[0] <= T_2181 - T_2192[1] <= T_2184 - T_2192[2] <= T_2187 - T_2192[3] <= T_2190 - node T_2198 = cat(T_2192[3], T_2192[2]) - node T_2199 = cat(T_2192[1], T_2192[0]) - node s1_tag_match_way = cat(T_2198, T_2199) - s1_clk_en <= metaReadArb.io.out.valid - node T_2202 = eq(s1_valid, UInt<1>("h00")) - node T_2203 = and(s1_clk_en, T_2202) - node T_2205 = eq(s1_replay, UInt<1>("h00")) - node s1_writeback = and(T_2203, T_2205) - reg s2_tag_match_way : UInt<4>, clk - when s1_clk_en : - s2_tag_match_way <= s1_tag_match_way - skip - node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) - reg T_2210 : {state : UInt<2>}, clk - when s1_clk_en : - T_2210 <- meta.io.resp[0].coh - skip - reg T_2235 : {state : UInt<2>}, clk - when s1_clk_en : - T_2235 <- meta.io.resp[1].coh - skip - reg T_2260 : {state : UInt<2>}, clk - when s1_clk_en : - T_2260 <- meta.io.resp[2].coh - skip - reg T_2285 : {state : UInt<2>}, clk - when s1_clk_en : - T_2285 <- meta.io.resp[3].coh - skip - wire T_2335 : {state : UInt<2>}[4] - T_2335[0] <- T_2210 - T_2335[1] <- T_2235 - T_2335[2] <- T_2260 - T_2335[3] <- T_2285 - node T_2461 = bits(s2_tag_match_way, 0, 0) - node T_2462 = bits(s2_tag_match_way, 1, 1) - node T_2463 = bits(s2_tag_match_way, 2, 2) - node T_2464 = bits(s2_tag_match_way, 3, 3) - node T_2466 = mux(T_2461, T_2335[0].state, UInt<1>("h00")) - node T_2468 = mux(T_2462, T_2335[1].state, UInt<1>("h00")) - node T_2470 = mux(T_2463, T_2335[2].state, UInt<1>("h00")) - node T_2472 = mux(T_2464, T_2335[3].state, UInt<1>("h00")) - node T_2498 = or(T_2466, T_2468) - node T_2499 = or(T_2498, T_2470) - node T_2500 = or(T_2499, T_2472) - wire s2_hit_state : {state : UInt<2>} - s2_hit_state is invalid - node T_2551 = bits(T_2500, 1, 0) - s2_hit_state.state <= T_2551 - node T_2552 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2553 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2554 = or(T_2552, T_2553) - node T_2555 = bits(s2_req.cmd, 3, 3) - node T_2556 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2557 = or(T_2555, T_2556) - node T_2558 = or(T_2554, T_2557) - node T_2559 = eq(s2_req.cmd, UInt<5>("h03")) - node T_2560 = or(T_2558, T_2559) - node T_2561 = eq(s2_req.cmd, UInt<5>("h06")) - node T_2562 = or(T_2560, T_2561) - wire T_2564 : UInt<2>[2] - T_2564[0] <= UInt<2>("h02") - T_2564[1] <= UInt<2>("h03") - node T_2568 = eq(T_2564[0], s2_hit_state.state) - node T_2569 = eq(T_2564[1], s2_hit_state.state) - node T_2571 = or(UInt<1>("h00"), T_2568) - node T_2572 = or(T_2571, T_2569) - wire T_2574 : UInt<2>[3] - T_2574[0] <= UInt<1>("h01") - T_2574[1] <= UInt<2>("h02") - T_2574[2] <= UInt<2>("h03") - node T_2579 = eq(T_2574[0], s2_hit_state.state) - node T_2580 = eq(T_2574[1], s2_hit_state.state) - node T_2581 = eq(T_2574[2], s2_hit_state.state) - node T_2583 = or(UInt<1>("h00"), T_2579) - node T_2584 = or(T_2583, T_2580) - node T_2585 = or(T_2584, T_2581) - node T_2586 = mux(T_2562, T_2572, T_2585) - node T_2587 = and(s2_tag_match, T_2586) - node T_2588 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2589 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2590 = or(T_2588, T_2589) - node T_2591 = bits(s2_req.cmd, 3, 3) - node T_2592 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2593 = or(T_2591, T_2592) - node T_2594 = or(T_2590, T_2593) - node T_2595 = mux(T_2594, UInt<2>("h03"), s2_hit_state.state) - wire T_2621 : {state : UInt<2>} - T_2621 is invalid - T_2621.state <= T_2595 - node T_2646 = eq(s2_hit_state.state, T_2621.state) - node s2_hit = and(T_2587, T_2646) - reg lrsc_count : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) - reg lrsc_addr : UInt, clk - node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) - node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) - node T_2656 = shr(s2_req.addr, 6) - node T_2657 = eq(lrsc_addr, T_2656) - node s2_lrsc_addr_match = and(lrsc_valid, T_2657) - node T_2660 = eq(s2_lrsc_addr_match, UInt<1>("h00")) - node s2_sc_fail = and(s2_sc, T_2660) - when lrsc_valid : - node T_2663 = sub(lrsc_count, UInt<1>("h01")) - node T_2664 = tail(T_2663, 1) - lrsc_count <= T_2664 - skip - node T_2665 = and(s2_valid_masked, s2_hit) - node T_2666 = or(T_2665, s2_replay) - when T_2666 : - when s2_lr : - node T_2668 = eq(lrsc_valid, UInt<1>("h00")) - when T_2668 : - lrsc_count <= UInt<5>("h01f") - skip - node T_2670 = shr(s2_req.addr, 6) - lrsc_addr <= T_2670 - skip - when s2_sc : - lrsc_count <= UInt<1>("h00") - skip - skip - when io.cpu.invalidate_lr : - lrsc_count <= UInt<1>("h00") - skip - wire s2_data : UInt<128>[4] - s2_data is invalid - reg T_2697 : UInt<64>[2], clk - node T_2701 = bits(s1_tag_eq_way, 0, 0) - node T_2702 = and(s1_clk_en, T_2701) - node T_2706 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2707 = or(UInt<1>("h01"), T_2706) - node T_2708 = or(T_2707, s1_writeback) - node T_2709 = and(T_2702, T_2708) - when T_2709 : - node T_2710 = shr(data.io.resp[0], 0) - T_2697[0] <= T_2710 - skip - node T_2714 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2715 = or(UInt<1>("h00"), T_2714) - node T_2716 = or(T_2715, s1_writeback) - node T_2717 = and(T_2702, T_2716) - when T_2717 : - node T_2718 = shr(data.io.resp[0], 64) - T_2697[1] <= T_2718 - skip - node T_2719 = cat(T_2697[1], T_2697[0]) - s2_data[0] <= T_2719 - reg T_2728 : UInt<64>[2], clk - node T_2732 = bits(s1_tag_eq_way, 1, 1) - node T_2733 = and(s1_clk_en, T_2732) - node T_2737 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2738 = or(UInt<1>("h01"), T_2737) - node T_2739 = or(T_2738, s1_writeback) - node T_2740 = and(T_2733, T_2739) - when T_2740 : - node T_2741 = shr(data.io.resp[1], 0) - T_2728[0] <= T_2741 - skip - node T_2745 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2746 = or(UInt<1>("h00"), T_2745) - node T_2747 = or(T_2746, s1_writeback) - node T_2748 = and(T_2733, T_2747) - when T_2748 : - node T_2749 = shr(data.io.resp[1], 64) - T_2728[1] <= T_2749 - skip - node T_2750 = cat(T_2728[1], T_2728[0]) - s2_data[1] <= T_2750 - reg T_2759 : UInt<64>[2], clk - node T_2763 = bits(s1_tag_eq_way, 2, 2) - node T_2764 = and(s1_clk_en, T_2763) - node T_2768 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2769 = or(UInt<1>("h01"), T_2768) - node T_2770 = or(T_2769, s1_writeback) - node T_2771 = and(T_2764, T_2770) - when T_2771 : - node T_2772 = shr(data.io.resp[2], 0) - T_2759[0] <= T_2772 - skip - node T_2776 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2777 = or(UInt<1>("h00"), T_2776) - node T_2778 = or(T_2777, s1_writeback) - node T_2779 = and(T_2764, T_2778) - when T_2779 : - node T_2780 = shr(data.io.resp[2], 64) - T_2759[1] <= T_2780 - skip - node T_2781 = cat(T_2759[1], T_2759[0]) - s2_data[2] <= T_2781 - reg T_2790 : UInt<64>[2], clk - node T_2794 = bits(s1_tag_eq_way, 3, 3) - node T_2795 = and(s1_clk_en, T_2794) - node T_2799 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2800 = or(UInt<1>("h01"), T_2799) - node T_2801 = or(T_2800, s1_writeback) - node T_2802 = and(T_2795, T_2801) - when T_2802 : - node T_2803 = shr(data.io.resp[3], 0) - T_2790[0] <= T_2803 - skip - node T_2807 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2808 = or(UInt<1>("h00"), T_2807) - node T_2809 = or(T_2808, s1_writeback) - node T_2810 = and(T_2795, T_2809) - when T_2810 : - node T_2811 = shr(data.io.resp[3], 64) - T_2790[1] <= T_2811 - skip - node T_2812 = cat(T_2790[1], T_2790[0]) - s2_data[3] <= T_2812 - node T_2813 = bits(s2_tag_match_way, 0, 0) - node T_2814 = bits(s2_tag_match_way, 1, 1) - node T_2815 = bits(s2_tag_match_way, 2, 2) - node T_2816 = bits(s2_tag_match_way, 3, 3) - node T_2818 = mux(T_2813, s2_data[0], UInt<1>("h00")) - node T_2820 = mux(T_2814, s2_data[1], UInt<1>("h00")) - node T_2822 = mux(T_2815, s2_data[2], UInt<1>("h00")) - node T_2824 = mux(T_2816, s2_data[3], UInt<1>("h00")) - node T_2826 = or(T_2818, T_2820) - node T_2827 = or(T_2826, T_2822) - node T_2828 = or(T_2827, T_2824) - wire s2_data_muxed : UInt<128> - s2_data_muxed is invalid - s2_data_muxed <= T_2828 - node T_2830 = bits(s2_data_muxed, 63, 0) - node T_2831 = bits(s2_data_muxed, 127, 64) - wire T_2833 : UInt<64>[2] - T_2833[0] <= T_2830 - T_2833[1] <= T_2831 - node s2_data_corrected = cat(T_2833[1], T_2833[0]) - wire T_2839 : UInt<64>[2] - T_2839[0] <= T_2830 - T_2839[1] <= T_2831 - node s2_data_uncorrected = cat(T_2839[1], T_2839[0]) - wire T_2848 : UInt<1>[2] - T_2848[0] <= UInt<1>("h00") - T_2848[1] <= UInt<1>("h00") - node T_2852 = cat(T_2848[1], T_2848[0]) - node T_2853 = dshr(T_2852, UInt<1>("h00")) - node s2_data_correctable = bits(T_2853, 0, 0) - node T_2855 = and(s2_valid_masked, s2_hit) - node T_2856 = or(T_2855, s2_replay) - node T_2858 = eq(s2_sc_fail, UInt<1>("h00")) - node T_2859 = and(T_2856, T_2858) - node T_2860 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2861 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2862 = or(T_2860, T_2861) - node T_2863 = bits(s2_req.cmd, 3, 3) - node T_2864 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2865 = or(T_2863, T_2864) - node T_2866 = or(T_2862, T_2865) - node T_2867 = and(T_2859, T_2866) - s3_valid <= T_2867 - inst amoalu of AMOALU - amoalu.io is invalid - amoalu.clk <= clk - amoalu.reset <= reset - node T_2869 = or(s2_valid, s2_replay) - node T_2870 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2871 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2872 = or(T_2870, T_2871) - node T_2873 = bits(s2_req.cmd, 3, 3) - node T_2874 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2875 = or(T_2873, T_2874) - node T_2876 = or(T_2872, T_2875) - node T_2877 = or(T_2876, s2_data_correctable) - node T_2878 = and(T_2869, T_2877) - when T_2878 : - s3_req <- s2_req - node T_2879 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) - s3_req.data <= T_2879 - s3_way <= s2_tag_match_way - skip - writeArb.io.in[0].bits.addr <= s3_req.addr - node rowIdx = bits(s3_req.addr, 3, 3) - node rowWMask = dshl(UInt<1>("h01"), rowIdx) - writeArb.io.in[0].bits.wmask <= rowWMask - node T_2883 = cat(s3_req.data, s3_req.data) - writeArb.io.in[0].bits.data <= T_2883 - writeArb.io.in[0].valid <= s3_valid - writeArb.io.in[0].bits.way_en <= s3_way - wire T_2885 : UInt<1> - T_2885 is invalid - T_2885 <= UInt<1>("h00") - reg T_2888 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) - when T_2885 : - node T_2889 = bits(T_2888, 0, 0) - node T_2890 = bits(T_2888, 2, 2) - node T_2891 = xor(T_2889, T_2890) - node T_2892 = bits(T_2888, 3, 3) - node T_2893 = xor(T_2891, T_2892) - node T_2894 = bits(T_2888, 5, 5) - node T_2895 = xor(T_2893, T_2894) - node T_2896 = bits(T_2888, 15, 1) - node T_2897 = cat(T_2895, T_2896) - T_2888 <= T_2897 - skip - node T_2898 = bits(T_2888, 1, 0) - node s1_replaced_way_en = dshl(UInt<1>("h01"), T_2898) - node T_2901 = bits(T_2888, 1, 0) - reg T_2902 : UInt<2>, clk - when s1_clk_en : - T_2902 <= T_2901 - skip - node s2_replaced_way_en = dshl(UInt<1>("h01"), T_2902) - node T_2905 = bits(s1_replaced_way_en, 0, 0) - node T_2906 = and(s1_clk_en, T_2905) - reg T_2907 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk - when T_2906 : - T_2907 <- meta.io.resp[0] - skip - node T_2980 = bits(s1_replaced_way_en, 1, 1) - node T_2981 = and(s1_clk_en, T_2980) - reg T_2982 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk - when T_2981 : - T_2982 <- meta.io.resp[1] - skip - node T_3055 = bits(s1_replaced_way_en, 2, 2) - node T_3056 = and(s1_clk_en, T_3055) - reg T_3057 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk - when T_3056 : - T_3057 <- meta.io.resp[2] - skip - node T_3130 = bits(s1_replaced_way_en, 3, 3) - node T_3131 = and(s1_clk_en, T_3130) - reg T_3132 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk - when T_3131 : - T_3132 <- meta.io.resp[3] - skip - wire T_3278 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_3278[0] <- T_2907 - T_3278[1] <- T_2982 - T_3278[2] <- T_3057 - T_3278[3] <- T_3132 - node T_3644 = bits(s2_replaced_way_en, 0, 0) - node T_3645 = bits(s2_replaced_way_en, 1, 1) - node T_3646 = bits(s2_replaced_way_en, 2, 2) - node T_3647 = bits(s2_replaced_way_en, 3, 3) - node T_3648 = cat(T_3278[0].tag, T_3278[0].coh.state) - node T_3650 = mux(T_3644, T_3648, UInt<1>("h00")) - node T_3651 = cat(T_3278[1].tag, T_3278[1].coh.state) - node T_3653 = mux(T_3645, T_3651, UInt<1>("h00")) - node T_3654 = cat(T_3278[2].tag, T_3278[2].coh.state) - node T_3656 = mux(T_3646, T_3654, UInt<1>("h00")) - node T_3657 = cat(T_3278[3].tag, T_3278[3].coh.state) - node T_3659 = mux(T_3647, T_3657, UInt<1>("h00")) - node T_3733 = or(T_3650, T_3653) - node T_3734 = or(T_3733, T_3656) - node T_3735 = or(T_3734, T_3659) - wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} - s2_repl_meta is invalid - node T_3882 = bits(T_3735, 1, 0) - s2_repl_meta.coh.state <= T_3882 - node T_3883 = bits(T_3735, 21, 2) - s2_repl_meta.tag <= T_3883 - node T_3885 = eq(s2_hit, UInt<1>("h00")) - node T_3886 = and(s2_valid_masked, T_3885) - node T_3887 = eq(s2_req.cmd, UInt<5>("h02")) - node T_3888 = eq(s2_req.cmd, UInt<5>("h03")) - node T_3889 = or(T_3887, T_3888) - node T_3890 = eq(s2_req.cmd, UInt<5>("h00")) - node T_3891 = eq(s2_req.cmd, UInt<5>("h06")) - node T_3892 = or(T_3890, T_3891) - node T_3893 = eq(s2_req.cmd, UInt<5>("h07")) - node T_3894 = or(T_3892, T_3893) - node T_3895 = bits(s2_req.cmd, 3, 3) - node T_3896 = eq(s2_req.cmd, UInt<5>("h04")) - node T_3897 = or(T_3895, T_3896) - node T_3898 = or(T_3894, T_3897) - node T_3899 = or(T_3889, T_3898) - node T_3900 = eq(s2_req.cmd, UInt<5>("h01")) - node T_3901 = eq(s2_req.cmd, UInt<5>("h07")) - node T_3902 = or(T_3900, T_3901) - node T_3903 = bits(s2_req.cmd, 3, 3) - node T_3904 = eq(s2_req.cmd, UInt<5>("h04")) - node T_3905 = or(T_3903, T_3904) - node T_3906 = or(T_3902, T_3905) - node T_3907 = or(T_3899, T_3906) - node T_3908 = and(T_3886, T_3907) - mshrs.io.req.valid <= T_3908 - mshrs.io.req.bits <- s2_req - mshrs.io.req.bits.tag_match <= s2_tag_match - wire T_3982 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_3982 is invalid - T_3982.tag <= s2_repl_meta.tag - T_3982.coh <- s2_hit_state - node T_4055 = mux(s2_tag_match, T_3982, s2_repl_meta) - mshrs.io.req.bits.old_meta <- T_4055 - node T_4128 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) - mshrs.io.req.bits.way_en <= T_4128 - mshrs.io.req.bits.data <= s2_req.data - node T_4129 = and(mshrs.io.req.ready, mshrs.io.req.valid) - when T_4129 : - T_2885 <= UInt<1>("h01") - skip - io.mem.acquire <- mshrs.io.mem_req - readArb.io.in[1].valid <= mshrs.io.replay.valid - readArb.io.in[1].bits <- mshrs.io.replay.bits - node T_4132 = not(UInt<4>("h00")) - readArb.io.in[1].bits.way_en <= T_4132 - mshrs.io.replay.ready <= readArb.io.in[1].ready - node T_4133 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) - s1_replay <= T_4133 - metaReadArb.io.in[1] <- mshrs.io.meta_read - metaWriteArb.io.in[0] <- mshrs.io.meta_write - inst releaseArb of LockingArbiter_109 - releaseArb.io is invalid - releaseArb.clk <= clk - releaseArb.reset <= reset - io.mem.release <- releaseArb.io.out - node T_4166 = eq(lrsc_valid, UInt<1>("h00")) - node T_4167 = and(io.mem.probe.valid, T_4166) - prober.io.req.valid <= T_4167 - node T_4169 = eq(lrsc_valid, UInt<1>("h00")) - node T_4170 = and(prober.io.req.ready, T_4169) - io.mem.probe.ready <= T_4170 - prober.io.req.bits <- io.mem.probe.bits - releaseArb.io.in[1] <- prober.io.rep - prober.io.way_en <= s2_tag_match_way - prober.io.block_state <- s2_hit_state - metaReadArb.io.in[2] <- prober.io.meta_read - metaWriteArb.io.in[1] <- prober.io.meta_write - prober.io.mshr_rdy <= mshrs.io.probe_rdy - inst T_4171 of FlowThroughSerializer - T_4171.io is invalid - T_4171.clk <= clk - T_4171.reset <= reset - T_4171.io.in.valid <= io.mem.grant.valid - T_4171.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_4171.io.in.ready - node T_4172 = and(T_4171.io.out.ready, T_4171.io.out.valid) - mshrs.io.mem_grant.valid <= T_4172 - mshrs.io.mem_grant.bits <- T_4171.io.out.bits - wire T_4176 : UInt<3>[2] - T_4176[0] <= UInt<3>("h05") - T_4176[1] <= UInt<3>("h04") - node T_4180 = eq(T_4176[0], T_4171.io.out.bits.g_type) - node T_4181 = eq(T_4176[1], T_4171.io.out.bits.g_type) - node T_4183 = or(UInt<1>("h00"), T_4180) - node T_4184 = or(T_4183, T_4181) - wire T_4186 : UInt<1>[2] - T_4186[0] <= UInt<1>("h00") - T_4186[1] <= UInt<1>("h01") - node T_4190 = eq(T_4186[0], T_4171.io.out.bits.g_type) - node T_4191 = eq(T_4186[1], T_4171.io.out.bits.g_type) - node T_4193 = or(UInt<1>("h00"), T_4190) - node T_4194 = or(T_4193, T_4191) - node T_4195 = mux(T_4171.io.out.bits.is_builtin_type, T_4184, T_4194) - node T_4197 = eq(T_4195, UInt<1>("h00")) - node T_4198 = or(writeArb.io.in[1].ready, T_4197) - T_4171.io.out.ready <= T_4198 - wire T_4202 : UInt<3>[2] - T_4202[0] <= UInt<3>("h05") - T_4202[1] <= UInt<3>("h04") - node T_4206 = eq(T_4202[0], T_4171.io.out.bits.g_type) - node T_4207 = eq(T_4202[1], T_4171.io.out.bits.g_type) - node T_4209 = or(UInt<1>("h00"), T_4206) - node T_4210 = or(T_4209, T_4207) - wire T_4212 : UInt<1>[2] - T_4212[0] <= UInt<1>("h00") - T_4212[1] <= UInt<1>("h01") - node T_4216 = eq(T_4212[0], T_4171.io.out.bits.g_type) - node T_4217 = eq(T_4212[1], T_4171.io.out.bits.g_type) - node T_4219 = or(UInt<1>("h00"), T_4216) - node T_4220 = or(T_4219, T_4217) - node T_4221 = mux(T_4171.io.out.bits.is_builtin_type, T_4210, T_4220) - node T_4222 = and(T_4171.io.out.valid, T_4221) - node T_4224 = lt(T_4171.io.out.bits.client_xact_id, UInt<2>("h02")) - node T_4225 = and(T_4222, T_4224) - writeArb.io.in[1].valid <= T_4225 - writeArb.io.in[1].bits.addr <= mshrs.io.refill.addr - writeArb.io.in[1].bits.way_en <= mshrs.io.refill.way_en - node T_4227 = not(UInt<2>("h00")) - writeArb.io.in[1].bits.wmask <= T_4227 - node T_4228 = bits(T_4171.io.out.bits.data, 127, 0) - writeArb.io.in[1].bits.data <= T_4228 - data.io.read <- readArb.io.out - node T_4230 = eq(T_4171.io.out.valid, UInt<1>("h00")) - node T_4231 = or(T_4230, T_4171.io.out.ready) - readArb.io.out.ready <= T_4231 - inst wbArb of Arbiter_95 - wbArb.io is invalid - wbArb.clk <= clk - wbArb.reset <= reset - wbArb.io.in[0] <- prober.io.wb_req - wbArb.io.in[1] <- mshrs.io.wb_req - wb.io.req <- wbArb.io.out - metaReadArb.io.in[3] <- wb.io.meta_read - readArb.io.in[2] <- wb.io.data_req - wb.io.data_resp <= s2_data_corrected - releaseArb.io.in[0] <- wb.io.release - reg s4_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - s4_valid <= s3_valid - node T_4266 = and(s3_valid, metaReadArb.io.out.valid) - reg s4_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk - when T_4266 : - s4_req <- s3_req - skip - node T_4321 = or(s2_valid_masked, s2_replay) - node T_4323 = eq(s2_sc_fail, UInt<1>("h00")) - node T_4324 = and(T_4321, T_4323) - node T_4325 = shr(s1_addr, 3) - node T_4326 = shr(s2_req.addr, 3) - node T_4327 = eq(T_4325, T_4326) - node T_4328 = and(T_4324, T_4327) - node T_4329 = eq(s2_req.cmd, UInt<5>("h01")) - node T_4330 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4331 = or(T_4329, T_4330) - node T_4332 = bits(s2_req.cmd, 3, 3) - node T_4333 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4334 = or(T_4332, T_4333) - node T_4335 = or(T_4331, T_4334) - node T_4336 = and(T_4328, T_4335) - node T_4337 = shr(s1_addr, 3) - node T_4338 = shr(s3_req.addr, 3) - node T_4339 = eq(T_4337, T_4338) - node T_4340 = and(s3_valid, T_4339) - node T_4341 = eq(s3_req.cmd, UInt<5>("h01")) - node T_4342 = eq(s3_req.cmd, UInt<5>("h07")) - node T_4343 = or(T_4341, T_4342) - node T_4344 = bits(s3_req.cmd, 3, 3) - node T_4345 = eq(s3_req.cmd, UInt<5>("h04")) - node T_4346 = or(T_4344, T_4345) - node T_4347 = or(T_4343, T_4346) - node T_4348 = and(T_4340, T_4347) - node T_4349 = shr(s1_addr, 3) - node T_4350 = shr(s4_req.addr, 3) - node T_4351 = eq(T_4349, T_4350) - node T_4352 = and(s4_valid, T_4351) - node T_4353 = eq(s4_req.cmd, UInt<5>("h01")) - node T_4354 = eq(s4_req.cmd, UInt<5>("h07")) - node T_4355 = or(T_4353, T_4354) - node T_4356 = bits(s4_req.cmd, 3, 3) - node T_4357 = eq(s4_req.cmd, UInt<5>("h04")) - node T_4358 = or(T_4356, T_4357) - node T_4359 = or(T_4355, T_4358) - node T_4360 = and(T_4352, T_4359) - reg s2_store_bypass_data : UInt<64>, clk - reg s2_store_bypass : UInt<1>, clk - when s1_clk_en : - s2_store_bypass <= UInt<1>("h00") - node T_4366 = or(T_4336, T_4348) - node T_4367 = or(T_4366, T_4360) - when T_4367 : - node T_4368 = mux(T_4348, s3_req.data, s4_req.data) - node T_4369 = mux(T_4336, amoalu.io.out, T_4368) - s2_store_bypass_data <= T_4369 - s2_store_bypass <= UInt<1>("h01") - skip - skip - node T_4372 = cat(UInt<1>("h00"), UInt<6>("h00")) - node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4372) - node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) - node T_4375 = bits(s2_req.typ, 1, 0) - node T_4376 = asSInt(s2_req.typ) - node T_4378 = geq(T_4376, asSInt(UInt<1>("h00"))) - amoalu.io.addr <= s2_req.addr - amoalu.io.cmd <= s2_req.cmd - amoalu.io.typ <= s2_req.typ - amoalu.io.lhs <= s2_data_word - amoalu.io.rhs <= s2_req.data - node T_4379 = and(dtlb.io.req.valid, dtlb.io.resp.miss) - node T_4380 = bits(s1_req.addr, 11, 6) - node T_4381 = eq(T_4380, prober.io.meta_write.bits.idx) - node T_4383 = eq(prober.io.req.ready, UInt<1>("h00")) - node T_4384 = and(T_4381, T_4383) - node s1_nack = or(T_4379, T_4384) - node T_4386 = or(s1_valid, s1_replay) - reg s2_nack_hit : UInt<1>, clk - when T_4386 : - s2_nack_hit <= s1_nack - skip - when s2_nack_hit : - mshrs.io.req.valid <= UInt<1>("h00") - skip - node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss) - node T_4391 = eq(s2_hit, UInt<1>("h00")) - node T_4393 = eq(mshrs.io.req.ready, UInt<1>("h00")) - node s2_nack_miss = and(T_4391, T_4393) - node T_4395 = or(s2_nack_hit, s2_nack_victim) - node s2_nack = or(T_4395, s2_nack_miss) - node T_4398 = eq(s2_nack, UInt<1>("h00")) - node T_4399 = and(s2_valid, T_4398) - s2_valid_masked <= T_4399 - node T_4400 = or(s2_valid, s2_replay) - node T_4401 = and(T_4400, s2_hit) - node s2_recycle_ecc = and(T_4401, s2_data_correctable) - reg s2_recycle_next : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_4405 = or(s1_valid, s1_replay) - when T_4405 : - s2_recycle_next <= s2_recycle_ecc - skip - node T_4406 = or(s2_recycle_ecc, s2_recycle_next) - s2_recycle <= T_4406 - reg block_miss : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_4409 = or(s2_valid, block_miss) - node T_4410 = and(T_4409, s2_nack_miss) - block_miss <= T_4410 - when block_miss : - io.cpu.req.ready <= UInt<1>("h00") - skip - wire cache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - cache_resp is invalid - node T_4701 = and(s2_valid_masked, s2_hit) - node T_4702 = or(s2_replay, T_4701) - node T_4704 = eq(s2_data_correctable, UInt<1>("h00")) - node T_4705 = and(T_4702, T_4704) - cache_resp.valid <= T_4705 - cache_resp.bits <- s2_req - node T_4706 = eq(s2_req.cmd, UInt<5>("h00")) - node T_4707 = eq(s2_req.cmd, UInt<5>("h06")) - node T_4708 = or(T_4706, T_4707) - node T_4709 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4710 = or(T_4708, T_4709) - node T_4711 = bits(s2_req.cmd, 3, 3) - node T_4712 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4713 = or(T_4711, T_4712) - node T_4714 = or(T_4710, T_4713) - cache_resp.bits.has_data <= T_4714 - node T_4715 = bits(s2_req.addr, 2, 2) - node T_4716 = bits(s2_data_word, 63, 32) - node T_4717 = bits(s2_data_word, 31, 0) - node T_4718 = mux(T_4715, T_4716, T_4717) - node T_4720 = and(UInt<1>("h00"), s2_sc) - node T_4722 = mux(T_4720, UInt<1>("h00"), T_4718) - node T_4724 = eq(T_4375, UInt<2>("h02")) - node T_4725 = or(T_4724, T_4720) - node T_4726 = bits(T_4722, 31, 31) - node T_4727 = and(T_4378, T_4726) - node T_4729 = sub(UInt<32>("h00"), T_4727) - node T_4730 = tail(T_4729, 1) - node T_4731 = bits(s2_data_word, 63, 32) - node T_4732 = mux(T_4725, T_4730, T_4731) - node T_4733 = cat(T_4732, T_4722) - node T_4734 = bits(s2_req.addr, 1, 1) - node T_4735 = bits(T_4733, 31, 16) - node T_4736 = bits(T_4733, 15, 0) - node T_4737 = mux(T_4734, T_4735, T_4736) - node T_4739 = and(UInt<1>("h00"), s2_sc) - node T_4741 = mux(T_4739, UInt<1>("h00"), T_4737) - node T_4743 = eq(T_4375, UInt<1>("h01")) - node T_4744 = or(T_4743, T_4739) - node T_4745 = bits(T_4741, 15, 15) - node T_4746 = and(T_4378, T_4745) - node T_4748 = sub(UInt<48>("h00"), T_4746) - node T_4749 = tail(T_4748, 1) - node T_4750 = bits(T_4733, 63, 16) - node T_4751 = mux(T_4744, T_4749, T_4750) - node T_4752 = cat(T_4751, T_4741) - node T_4753 = bits(s2_req.addr, 0, 0) - node T_4754 = bits(T_4752, 15, 8) - node T_4755 = bits(T_4752, 7, 0) - node T_4756 = mux(T_4753, T_4754, T_4755) - node T_4758 = and(UInt<1>("h01"), s2_sc) - node T_4760 = mux(T_4758, UInt<1>("h00"), T_4756) - node T_4762 = eq(T_4375, UInt<1>("h00")) - node T_4763 = or(T_4762, T_4758) - node T_4764 = bits(T_4760, 7, 7) - node T_4765 = and(T_4378, T_4764) - node T_4767 = sub(UInt<56>("h00"), T_4765) - node T_4768 = tail(T_4767, 1) - node T_4769 = bits(T_4752, 63, 8) - node T_4770 = mux(T_4763, T_4768, T_4769) - node T_4771 = cat(T_4770, T_4760) - node T_4772 = or(T_4771, s2_sc_fail) - cache_resp.bits.data <= T_4772 - cache_resp.bits.store_data <= s2_req.data - node T_4773 = and(s2_valid, s2_nack) - cache_resp.bits.nack <= T_4773 - cache_resp.bits.replay <= s2_replay - wire uncache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - uncache_resp is invalid - uncache_resp.bits <- mshrs.io.resp.bits - uncache_resp.valid <= mshrs.io.resp.valid - node T_5063 = or(s2_valid, s2_killed) - node cache_pass = or(T_5063, s2_replay) - node T_5066 = eq(cache_pass, UInt<1>("h00")) - mshrs.io.resp.ready <= T_5066 - node T_5067 = mux(cache_pass, cache_resp, uncache_resp) - io.cpu.resp <- T_5067 - node T_5183 = bits(s2_req.addr, 2, 2) - node T_5184 = bits(s2_data_word, 63, 32) - node T_5185 = bits(s2_data_word, 31, 0) - node T_5186 = mux(T_5183, T_5184, T_5185) - node T_5188 = and(UInt<1>("h00"), s2_sc) - node T_5190 = mux(T_5188, UInt<1>("h00"), T_5186) - node T_5192 = eq(T_4375, UInt<2>("h02")) - node T_5193 = or(T_5192, T_5188) - node T_5194 = bits(T_5190, 31, 31) - node T_5195 = and(T_4378, T_5194) - node T_5197 = sub(UInt<32>("h00"), T_5195) - node T_5198 = tail(T_5197, 1) - node T_5199 = bits(s2_data_word, 63, 32) - node T_5200 = mux(T_5193, T_5198, T_5199) - node T_5201 = cat(T_5200, T_5190) - io.cpu.resp.bits.data_word_bypass <= T_5201 - node T_5203 = eq(s1_valid, UInt<1>("h00")) - node T_5204 = and(mshrs.io.fence_rdy, T_5203) - node T_5206 = eq(s2_valid, UInt<1>("h00")) - node T_5207 = and(T_5204, T_5206) - io.cpu.ordered <= T_5207 - node T_5208 = and(s1_replay, s1_read) - io.cpu.replay_next.valid <= T_5208 - io.cpu.replay_next.bits <= s1_req.tag - - module RRArbiter_112 : + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_55 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + extmodule AsyncResetReg_56 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_56 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} - - io is invalid - wire T_152 : UInt<1> - T_152 is invalid - io.out.valid <= io.in[T_152].valid - io.out.bits <- io.in[T_152].bits - io.chosen <= T_152 - io.in[T_152].ready <= UInt<1>("h00") - reg T_195 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_196 = gt(UInt<1>("h00"), T_195) - node T_197 = and(io.in[0].valid, T_196) - node T_199 = gt(UInt<1>("h01"), T_195) - node T_200 = and(io.in[1].valid, T_199) - node T_203 = or(UInt<1>("h00"), T_197) - node T_205 = eq(T_203, UInt<1>("h00")) - node T_207 = or(UInt<1>("h00"), T_197) - node T_208 = or(T_207, T_200) - node T_210 = eq(T_208, UInt<1>("h00")) - node T_212 = or(UInt<1>("h00"), T_197) - node T_213 = or(T_212, T_200) - node T_214 = or(T_213, io.in[0].valid) - node T_216 = eq(T_214, UInt<1>("h00")) - node T_218 = gt(UInt<1>("h00"), T_195) - node T_219 = and(UInt<1>("h01"), T_218) - node T_220 = or(T_219, T_210) - node T_222 = gt(UInt<1>("h01"), T_195) - node T_223 = and(T_205, T_222) - node T_224 = or(T_223, T_216) - node T_226 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_227 = mux(UInt<1>("h00"), T_226, T_220) - node T_228 = and(T_227, io.out.ready) - io.in[0].ready <= T_228 - node T_230 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_231 = mux(UInt<1>("h00"), T_230, T_224) - node T_232 = and(T_231, io.out.ready) - io.in[1].ready <= T_232 - node T_235 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_237 = gt(UInt<1>("h01"), T_195) - node T_238 = and(io.in[1].valid, T_237) - node T_240 = mux(T_238, UInt<1>("h01"), T_235) - node T_241 = mux(UInt<1>("h00"), UInt<1>("h01"), T_240) - T_152 <= T_241 - node T_242 = and(io.out.ready, io.out.valid) - when T_242 : - T_195 <= T_152 - skip + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} - module PTW : + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_56 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncValidSync_11 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<1>, out : UInt<1>} + + io is invalid + io is invalid + inst source_valid_sync_0 of AsyncResetRegVec_54 @[AsyncQueue.scala 18:14] + source_valid_sync_0.io is invalid + source_valid_sync_0.clock <= clock + source_valid_sync_0.reset <= reset + inst source_valid_sync_1 of AsyncResetRegVec_55 @[AsyncQueue.scala 18:14] + source_valid_sync_1.io is invalid + source_valid_sync_1.clock <= clock + source_valid_sync_1.reset <= reset + inst source_valid_sync_2 of AsyncResetRegVec_56 @[AsyncQueue.scala 18:14] + source_valid_sync_2.io is invalid + source_valid_sync_2.clock <= clock + source_valid_sync_2.reset <= reset + source_valid_sync_2.io.d <= io.in @[AsyncQueue.scala 20:21] + source_valid_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + source_valid_sync_0.io.d <= source_valid_sync_1.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + source_valid_sync_1.io.d <= source_valid_sync_2.io.q @[AsyncQueue.scala 23:19] + source_valid_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_9 = bits(source_valid_sync_0.io.q, 0, 0) @[AsyncQueue.scala 35:52] + io.out <= _T_9 @[AsyncQueue.scala 35:10] + + extmodule AsyncResetReg_57 : + input rst : UInt<1> input clk : Clock + input en : UInt<1> + output q : UInt<1> + input d : UInt<1> + + defname = AsyncResetReg + + + module AsyncResetRegVec_57 : + input clock : Clock input reset : UInt<1> - output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}} - - io is invalid - reg state : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - reg count : UInt<2>, clk - reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk - reg r_req_dest : UInt, clk - reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk - node T_1590 = shr(r_req.addr, 18) - node T_1591 = bits(T_1590, 8, 0) - node T_1592 = shr(r_req.addr, 9) - node T_1593 = bits(T_1592, 8, 0) - node T_1594 = shr(r_req.addr, 0) - node T_1595 = bits(T_1594, 8, 0) - wire T_1597 : UInt<9>[3] - T_1597[0] <= T_1591 - T_1597[1] <= T_1593 - T_1597[2] <= T_1595 - inst arb of RRArbiter_112 - arb.io is invalid - arb.clk <= clk - arb.reset <= reset - arb.io.in[0] <- io.requestor[0].req - arb.io.in[1] <- io.requestor[1].req - node T_1609 = eq(state, UInt<1>("h00")) - arb.io.out.ready <= T_1609 - wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte is invalid - node T_1631 = bits(io.mem.resp.bits.data, 0, 0) - pte.v <= T_1631 - node T_1632 = bits(io.mem.resp.bits.data, 4, 1) - pte.typ <= T_1632 - node T_1633 = bits(io.mem.resp.bits.data, 5, 5) - pte.r <= T_1633 - node T_1634 = bits(io.mem.resp.bits.data, 6, 6) - pte.d <= T_1634 - node T_1635 = bits(io.mem.resp.bits.data, 9, 7) - pte.reserved_for_software <= T_1635 - node T_1636 = bits(io.mem.resp.bits.data, 29, 10) - pte.ppn <= T_1636 - node T_1637 = cat(r_pte.ppn, T_1597[count]) - node pte_addr = shl(T_1637, 3) - node T_1639 = and(arb.io.out.ready, arb.io.out.valid) - when T_1639 : - r_req <- arb.io.out.bits - r_req_dest <= arb.io.chosen - node T_1640 = bits(io.dpath.ptbr, 31, 12) - r_pte.ppn <= T_1640 - skip - reg T_1642 : UInt<3>, clk - reg T_1652 : UInt<1>[3], clk - node T_1657 = cat(T_1652[1], T_1652[0]) - node T_1658 = cat(T_1652[2], T_1657) - cmem T_1661 : UInt<32>[3] - cmem T_1664 : UInt<20>[3] - infer mport T_1666 = T_1661[UInt<1>("h00")], clk - node T_1667 = eq(T_1666, pte_addr) - infer mport T_1669 = T_1661[UInt<1>("h01")], clk - node T_1670 = eq(T_1669, pte_addr) - infer mport T_1672 = T_1661[UInt<2>("h02")], clk - node T_1673 = eq(T_1672, pte_addr) - wire T_1675 : UInt<1>[3] - T_1675[0] <= T_1667 - T_1675[1] <= T_1670 - T_1675[2] <= T_1673 - node T_1680 = cat(T_1675[1], T_1675[0]) - node T_1681 = cat(T_1675[2], T_1680) - node T_1682 = and(T_1681, T_1658) - node pte_cache_hit = neq(T_1682, UInt<1>("h00")) - node T_1686 = lt(pte.typ, UInt<2>("h02")) - node T_1687 = and(pte.v, T_1686) - node T_1688 = and(io.mem.resp.valid, T_1687) - node T_1690 = eq(pte_cache_hit, UInt<1>("h00")) - node T_1691 = and(T_1688, T_1690) - when T_1691 : - node T_1692 = not(T_1658) - node T_1694 = eq(T_1692, UInt<1>("h00")) - node T_1696 = dshr(T_1642, UInt<1>("h01")) - node T_1697 = bits(T_1696, 0, 0) - node T_1698 = cat(UInt<1>("h01"), T_1697) - node T_1699 = dshr(T_1642, T_1698) - node T_1700 = bits(T_1699, 0, 0) - node T_1701 = cat(T_1698, T_1700) - node T_1702 = bits(T_1701, 1, 0) - node T_1703 = not(T_1658) - node T_1704 = bits(T_1703, 0, 0) - node T_1705 = bits(T_1703, 1, 1) - node T_1706 = bits(T_1703, 2, 2) - wire T_1708 : UInt<1>[3] - T_1708[0] <= T_1704 - T_1708[1] <= T_1705 - T_1708[2] <= T_1706 - node T_1716 = mux(T_1708[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1717 = mux(T_1708[0], UInt<1>("h00"), T_1716) - node T_1718 = mux(T_1694, T_1702, T_1717) - T_1652[T_1718] <= UInt<1>("h01") - infer mport T_1721 = T_1661[T_1718], clk - T_1721 <= pte_addr - infer mport T_1722 = T_1664[T_1718], clk - T_1722 <= pte.ppn - skip - node T_1723 = eq(state, UInt<1>("h01")) - node T_1724 = and(pte_cache_hit, T_1723) - when T_1724 : - node T_1725 = bits(T_1682, 2, 2) - node T_1726 = bits(T_1682, 1, 0) - node T_1728 = neq(T_1725, UInt<1>("h00")) - node T_1729 = or(T_1725, T_1726) - node T_1730 = bits(T_1729, 1, 1) - node T_1731 = cat(T_1728, T_1730) - node T_1733 = bits(T_1731, 1, 1) - node T_1735 = dshl(UInt<3>("h01"), UInt<1>("h01")) - node T_1736 = bits(T_1735, 2, 0) - node T_1737 = not(T_1736) - node T_1738 = and(T_1642, T_1737) - node T_1740 = mux(T_1733, UInt<1>("h00"), T_1736) - node T_1741 = or(T_1738, T_1740) - node T_1742 = cat(UInt<1>("h01"), T_1733) - node T_1743 = bits(T_1731, 0, 0) - node T_1745 = dshl(UInt<3>("h01"), T_1742) - node T_1746 = bits(T_1745, 2, 0) - node T_1747 = not(T_1746) - node T_1748 = and(T_1741, T_1747) - node T_1750 = mux(T_1743, UInt<1>("h00"), T_1746) - node T_1751 = or(T_1748, T_1750) - node T_1752 = cat(T_1742, T_1743) - T_1642 <= T_1751 - skip - node T_1753 = or(reset, io.dpath.invalidate) - when T_1753 : - T_1652[0] <= UInt<1>("h00") - T_1652[1] <= UInt<1>("h00") - T_1652[2] <= UInt<1>("h00") - skip - node T_1757 = bits(T_1682, 0, 0) - node T_1758 = bits(T_1682, 1, 1) - node T_1759 = bits(T_1682, 2, 2) - infer mport T_1761 = T_1664[UInt<1>("h00")], clk - infer mport T_1763 = T_1664[UInt<1>("h01")], clk - infer mport T_1765 = T_1664[UInt<2>("h02")], clk - node T_1767 = mux(T_1757, T_1761, UInt<1>("h00")) - node T_1769 = mux(T_1758, T_1763, UInt<1>("h00")) - node T_1771 = mux(T_1759, T_1765, UInt<1>("h00")) - node T_1773 = or(T_1767, T_1769) - node T_1774 = or(T_1773, T_1771) - wire pte_cache_data : UInt<20> - pte_cache_data is invalid - pte_cache_data <= T_1774 - node T_1776 = bits(r_req.prv, 0, 0) - node T_1778 = geq(pte.typ, UInt<3>("h04")) - node T_1779 = and(pte.v, T_1778) - node T_1780 = bits(pte.typ, 1, 1) - node T_1781 = and(T_1779, T_1780) - node T_1783 = geq(pte.typ, UInt<2>("h02")) - node T_1784 = and(pte.v, T_1783) - node T_1785 = bits(pte.typ, 0, 0) - node T_1786 = and(T_1784, T_1785) - node T_1788 = geq(pte.typ, UInt<2>("h02")) - node T_1789 = and(pte.v, T_1788) - node T_1790 = mux(r_req.store, T_1786, T_1789) - node T_1791 = mux(r_req.fetch, T_1781, T_1790) - node T_1793 = geq(pte.typ, UInt<2>("h02")) - node T_1794 = and(pte.v, T_1793) - node T_1796 = lt(pte.typ, UInt<4>("h08")) - node T_1797 = and(T_1794, T_1796) - node T_1798 = bits(pte.typ, 1, 1) - node T_1799 = and(T_1797, T_1798) - node T_1801 = geq(pte.typ, UInt<2>("h02")) - node T_1802 = and(pte.v, T_1801) - node T_1804 = lt(pte.typ, UInt<4>("h08")) - node T_1805 = and(T_1802, T_1804) - node T_1806 = bits(pte.typ, 0, 0) - node T_1807 = and(T_1805, T_1806) - node T_1809 = geq(pte.typ, UInt<2>("h02")) - node T_1810 = and(pte.v, T_1809) - node T_1812 = lt(pte.typ, UInt<4>("h08")) - node T_1813 = and(T_1810, T_1812) - node T_1814 = mux(r_req.store, T_1807, T_1813) - node T_1815 = mux(r_req.fetch, T_1799, T_1814) - node perm_ok = mux(T_1776, T_1791, T_1815) - node T_1818 = eq(pte.r, UInt<1>("h00")) - node T_1820 = eq(pte.d, UInt<1>("h00")) - node T_1821 = and(r_req.store, T_1820) - node T_1822 = or(T_1818, T_1821) - node set_dirty_bit = and(perm_ok, T_1822) - node T_1824 = eq(state, UInt<2>("h02")) - node T_1825 = and(io.mem.resp.valid, T_1824) - node T_1827 = eq(set_dirty_bit, UInt<1>("h00")) - node T_1828 = and(T_1825, T_1827) - when T_1828 : - r_pte <- pte - skip - wire T_1844 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - T_1844 is invalid - T_1844.v <= UInt<1>("h00") - T_1844.typ <= UInt<4>("h00") - T_1844.r <= UInt<1>("h00") - T_1844.d <= UInt<1>("h00") - T_1844.reserved_for_software <= UInt<3>("h00") - T_1844.ppn <= UInt<20>("h00") - wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte_wdata <- T_1844 - pte_wdata.r <= UInt<1>("h01") - pte_wdata.d <= r_req.store - node T_1865 = eq(state, UInt<1>("h01")) - node T_1866 = eq(state, UInt<2>("h03")) - node T_1867 = or(T_1865, T_1866) - io.mem.req.valid <= T_1867 - io.mem.req.bits.phys <= UInt<1>("h01") - node T_1869 = eq(state, UInt<2>("h03")) - node T_1870 = mux(T_1869, UInt<5>("h0a"), UInt<5>("h00")) - io.mem.req.bits.cmd <= T_1870 - io.mem.req.bits.typ <= UInt<3>("h03") - io.mem.req.bits.addr <= pte_addr - io.mem.req.bits.kill <= UInt<1>("h00") - node T_1872 = cat(pte_wdata.reserved_for_software, pte_wdata.d) - node T_1873 = cat(pte_wdata.ppn, T_1872) - node T_1874 = cat(pte_wdata.typ, pte_wdata.v) - node T_1875 = cat(pte_wdata.r, T_1874) - node T_1876 = cat(T_1873, T_1875) - io.mem.req.bits.data <= T_1876 - node resp_err = eq(state, UInt<3>("h06")) - node T_1878 = eq(state, UInt<3>("h05")) - node resp_val = or(T_1878, resp_err) - node r_resp_ppn = shr(io.mem.req.bits.addr, 12) - node T_1881 = shr(r_resp_ppn, 18) - node T_1882 = bits(r_req.addr, 17, 0) - node T_1883 = cat(T_1881, T_1882) - node T_1884 = shr(r_resp_ppn, 9) - node T_1885 = bits(r_req.addr, 8, 0) - node T_1886 = cat(T_1884, T_1885) - wire T_1888 : UInt<28>[3] - T_1888[0] <= T_1883 - T_1888[1] <= T_1886 - T_1888[2] <= r_resp_ppn - node T_1895 = eq(r_req_dest, UInt<1>("h00")) - node T_1896 = and(resp_val, T_1895) - io.requestor[0].resp.valid <= T_1896 - io.requestor[0].resp.bits.error <= resp_err - io.requestor[0].resp.bits.pte <- r_pte - io.requestor[0].resp.bits.pte.ppn <= T_1888[count] - io.requestor[0].invalidate <= io.dpath.invalidate - io.requestor[0].status <- io.dpath.status - node T_1898 = eq(r_req_dest, UInt<1>("h01")) - node T_1899 = and(resp_val, T_1898) - io.requestor[1].resp.valid <= T_1899 - io.requestor[1].resp.bits.error <= resp_err - io.requestor[1].resp.bits.pte <- r_pte - io.requestor[1].resp.bits.pte.ppn <= T_1888[count] - io.requestor[1].invalidate <= io.dpath.invalidate - io.requestor[1].status <- io.dpath.status - node T_1900 = eq(UInt<1>("h00"), state) - when T_1900 : - when arb.io.out.valid : - state <= UInt<1>("h01") + output io : {flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} + + io is invalid + io is invalid + inst reg_0 of AsyncResetReg_57 @[BlackBoxRegs.scala 55:39] + reg_0.rst is invalid + reg_0.clk is invalid + reg_0.en is invalid + reg_0.q is invalid + reg_0.d is invalid + reg_0.clk <= clock @[BlackBoxRegs.scala 59:16] + reg_0.rst <= reset @[BlackBoxRegs.scala 60:16] + node _T_8 = bits(io.d, 0, 0) @[BlackBoxRegs.scala 61:35] + reg_0.d <= _T_8 @[BlackBoxRegs.scala 61:16] + reg_0.en <= io.en @[BlackBoxRegs.scala 62:16] + io.q <= reg_0.q @[BlackBoxRegs.scala 67:8] + + module AsyncQueueSink_1 : + input clock : Clock + input reset : UInt<1> + output io : {deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}, ridx : UInt<1>, flip widx : UInt<1>, flip mem : {data : UInt<34>, resp : UInt<2>}[1], flip source_reset_n : UInt<1>, ridx_valid : UInt<1>, flip widx_valid : UInt<1>} + + io is invalid + io is invalid + wire source_ready : UInt<1> + source_ready is invalid + source_ready <= UInt<1>("h01") + node _T_42 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_44 = eq(source_ready, UInt<1>("h00")) @[AsyncQueue.scala 111:49] + wire _T_46 : UInt<1> @[AsyncQueue.scala 8:27] + _T_46 is invalid @[AsyncQueue.scala 8:27] + inst ridx_bin of AsyncResetRegVec_43 @[BlackBoxRegs.scala 89:21] + ridx_bin.io is invalid + ridx_bin.clock <= clock + ridx_bin.reset <= reset + ridx_bin.io.d <= _T_46 @[BlackBoxRegs.scala 91:14] + ridx_bin.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node _T_49 = add(ridx_bin.io.q, _T_42) @[AsyncQueue.scala 10:47] + node _T_50 = tail(_T_49, 1) @[AsyncQueue.scala 10:47] + node _T_51 = mux(_T_44, UInt<1>("h00"), _T_50) @[AsyncQueue.scala 10:23] + _T_46 <= _T_51 @[AsyncQueue.scala 10:17] + node _T_53 = dshr(_T_46, UInt<1>("h01")) @[AsyncQueue.scala 11:32] + node ridx = xor(_T_46, _T_53) @[AsyncQueue.scala 11:17] + inst widx_gray_sync_0 of AsyncResetRegVec_44 @[AsyncQueue.scala 18:14] + widx_gray_sync_0.io is invalid + widx_gray_sync_0.clock <= clock + widx_gray_sync_0.reset <= reset + inst widx_gray_sync_1 of AsyncResetRegVec_45 @[AsyncQueue.scala 18:14] + widx_gray_sync_1.io is invalid + widx_gray_sync_1.clock <= clock + widx_gray_sync_1.reset <= reset + inst widx_gray_sync_2 of AsyncResetRegVec_46 @[AsyncQueue.scala 18:14] + widx_gray_sync_2.io is invalid + widx_gray_sync_2.clock <= clock + widx_gray_sync_2.reset <= reset + widx_gray_sync_2.io.d <= io.widx @[AsyncQueue.scala 20:21] + widx_gray_sync_2.io.en <= UInt<1>("h01") @[AsyncQueue.scala 21:22] + widx_gray_sync_0.io.d <= widx_gray_sync_1.io.q @[AsyncQueue.scala 23:19] + widx_gray_sync_0.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + widx_gray_sync_1.io.d <= widx_gray_sync_2.io.q @[AsyncQueue.scala 23:19] + widx_gray_sync_1.io.en <= UInt<1>("h01") @[AsyncQueue.scala 24:20] + node _T_57 = neq(ridx, widx_gray_sync_0.io.q) @[AsyncQueue.scala 113:36] + node valid = and(source_ready, _T_57) @[AsyncQueue.scala 113:28] + reg _T_67 : {data : UInt<34>, resp : UInt<2>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_67 <- io.mem[UInt<1>("h00")] @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + io.deq.bits <- _T_67 @[AsyncQueue.scala 124:16] + inst valid_reg of AsyncResetRegVec_47 @[BlackBoxRegs.scala 89:21] + valid_reg.io is invalid + valid_reg.clock <= clock + valid_reg.reset <= reset + valid_reg.io.d <= valid @[BlackBoxRegs.scala 91:14] + valid_reg.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + node valid_reg_1 = bits(valid_reg.io.q, 0, 0) @[AsyncQueue.scala 126:59] + node _T_71 = and(valid_reg_1, source_ready) @[AsyncQueue.scala 127:29] + io.deq.valid <= _T_71 @[AsyncQueue.scala 127:16] + inst ridx_gray of AsyncResetRegVec_48 @[BlackBoxRegs.scala 89:21] + ridx_gray.io is invalid + ridx_gray.clock <= clock + ridx_gray.reset <= reset + ridx_gray.io.d <= ridx @[BlackBoxRegs.scala 91:14] + ridx_gray.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + io.ridx <= ridx_gray.io.q @[AsyncQueue.scala 130:11] + io.ridx_valid <= UInt<1>("h01") @[AsyncQueue.scala 132:17] + inst AsyncValidSync of AsyncValidSync_9 @[AsyncQueue.scala 134:31] + AsyncValidSync.io is invalid + AsyncValidSync.clock <= clock + AsyncValidSync.reset <= reset + inst AsyncValidSync_1 of AsyncValidSync_10 @[AsyncQueue.scala 135:31] + AsyncValidSync_1.io is invalid + AsyncValidSync_1.clock <= clock + AsyncValidSync_1.reset <= reset + inst AsyncValidSync_2 of AsyncValidSync_11 @[AsyncQueue.scala 136:31] + AsyncValidSync_2.io is invalid + AsyncValidSync_2.clock <= clock + AsyncValidSync_2.reset <= reset + node _T_75 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 137:37] + node _T_76 = or(reset, _T_75) @[AsyncQueue.scala 137:34] + AsyncValidSync.reset <= _T_76 @[AsyncQueue.scala 137:25] + node _T_78 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 138:37] + node _T_79 = or(reset, _T_78) @[AsyncQueue.scala 138:34] + AsyncValidSync_1.reset <= _T_79 @[AsyncQueue.scala 138:25] + AsyncValidSync.io.in <= UInt<1>("h01") @[AsyncQueue.scala 140:22] + io.ridx_valid <= AsyncValidSync.io.out @[AsyncQueue.scala 141:19] + AsyncValidSync_1.io.in <= io.widx_valid @[AsyncQueue.scala 142:25] + AsyncValidSync_2.io.in <= AsyncValidSync_1.io.out @[AsyncQueue.scala 143:24] + source_ready <= AsyncValidSync_2.io.out @[AsyncQueue.scala 144:18] + node _T_82 = eq(source_ready, UInt<1>("h00")) @[AsyncQueue.scala 146:28] + node _T_84 = eq(io.source_reset_n, UInt<1>("h00")) @[AsyncQueue.scala 146:45] + node _T_85 = or(_T_82, _T_84) @[AsyncQueue.scala 146:42] + node _T_86 = or(_T_85, reset) @[AsyncQueue.scala 146:64] + reg _T_89 : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[AsyncQueue.scala 147:36] + _T_89 <= _T_86 @[AsyncQueue.scala 147:36] + node _T_91 = eq(_T_89, UInt<1>("h00")) @[AsyncQueue.scala 148:22] + node _T_92 = and(_T_91, _T_86) @[AsyncQueue.scala 148:45] + node _T_93 = eq(io.widx, io.ridx) @[AsyncQueue.scala 149:59] + inst AsyncResetRegVec of AsyncResetRegVec_57 @[BlackBoxRegs.scala 89:21] + AsyncResetRegVec.io is invalid + AsyncResetRegVec.clock <= clock + AsyncResetRegVec.reset <= reset + AsyncResetRegVec.io.d <= _T_93 @[BlackBoxRegs.scala 91:14] + AsyncResetRegVec.io.en <= UInt<1>("h01") @[BlackBoxRegs.scala 92:15] + + module ExampleRocketTop : + input clock : Clock + input reset : UInt<1> + output io : {mem_axi4 : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, mmio_axi4 : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, flip l2_frontend_bus_axi4 : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<8>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, flip interrupts : UInt<2>, flip debug : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}}} + + io is invalid + io is invalid + inst socBus of TLXbar_socBus @[LazyModule.scala 60:13] + socBus.io is invalid + socBus.clock <= clock + socBus.reset <= reset + inst peripheryBus of TLXbar_peripheryBus @[LazyModule.scala 60:13] + peripheryBus.io is invalid + peripheryBus.clock <= clock + peripheryBus.reset <= reset + inst intBus of IntXbar_intBus @[LazyModule.scala 60:13] + intBus.io is invalid + intBus.clock <= clock + intBus.reset <= reset + inst l2FrontendBus of TLBuffer_l2FrontendBus @[LazyModule.scala 60:13] + l2FrontendBus.io is invalid + l2FrontendBus.clock <= clock + l2FrontendBus.reset <= reset + inst mem_0 of TLXbar_mem_0 @[LazyModule.scala 60:13] + mem_0.io is invalid + mem_0.clock <= clock + mem_0.reset <= reset + inst bootrom_TLAtomicAutomata of TLAtomicAutomata_bootrom @[LazyModule.scala 60:13] + bootrom_TLAtomicAutomata.io is invalid + bootrom_TLAtomicAutomata.clock <= clock + bootrom_TLAtomicAutomata.reset <= reset + inst TLMonitor of TLMonitor @[LazyModule.scala 60:13] + TLMonitor.io is invalid + TLMonitor.clock <= clock + TLMonitor.reset <= reset + inst bootrom_TLWidthWidget of TLWidthWidget_bootrom @[LazyModule.scala 60:13] + bootrom_TLWidthWidget.io is invalid + bootrom_TLWidthWidget.clock <= clock + bootrom_TLWidthWidget.reset <= reset + inst TLMonitor_1 of TLMonitor_1 @[LazyModule.scala 60:13] + TLMonitor_1.io is invalid + TLMonitor_1.clock <= clock + TLMonitor_1.reset <= reset + inst bootrom_TLBuffer of TLBuffer_bootrom @[LazyModule.scala 60:13] + bootrom_TLBuffer.io is invalid + bootrom_TLBuffer.clock <= clock + bootrom_TLBuffer.reset <= reset + inst TLMonitor_2 of TLMonitor_2 @[LazyModule.scala 60:13] + TLMonitor_2.io is invalid + TLMonitor_2.clock <= clock + TLMonitor_2.reset <= reset + inst TLMonitor_3 of TLMonitor_3 @[LazyModule.scala 60:13] + TLMonitor_3.io is invalid + TLMonitor_3.clock <= clock + TLMonitor_3.reset <= reset + inst IntXing of IntXing @[LazyModule.scala 60:13] + IntXing.io is invalid + IntXing.clock <= clock + IntXing.reset <= reset + inst rocketchipPeripheryMasterAXI4Memconverter of TLToAXI4_rocketchipPeripheryMasterAXI4Memconverter @[LazyModule.scala 60:13] + rocketchipPeripheryMasterAXI4Memconverter.io is invalid + rocketchipPeripheryMasterAXI4Memconverter.clock <= clock + rocketchipPeripheryMasterAXI4Memconverter.reset <= reset + inst rocketchipPeripheryMasterAXI4Membuffer of AXI4Buffer_rocketchipPeripheryMasterAXI4Membuffer @[LazyModule.scala 60:13] + rocketchipPeripheryMasterAXI4Membuffer.io is invalid + rocketchipPeripheryMasterAXI4Membuffer.clock <= clock + rocketchipPeripheryMasterAXI4Membuffer.reset <= reset + inst TLMonitor_4 of TLMonitor_4 @[LazyModule.scala 60:13] + TLMonitor_4.io is invalid + TLMonitor_4.clock <= clock + TLMonitor_4.reset <= reset + inst TLWidthWidget of TLWidthWidget @[LazyModule.scala 60:13] + TLWidthWidget.io is invalid + TLWidthWidget.clock <= clock + TLWidthWidget.reset <= reset + inst TLMonitor_5 of TLMonitor_5 @[LazyModule.scala 60:13] + TLMonitor_5.io is invalid + TLMonitor_5.clock <= clock + TLMonitor_5.reset <= reset + inst TLToAXI4 of TLToAXI4 @[LazyModule.scala 60:13] + TLToAXI4.io is invalid + TLToAXI4.clock <= clock + TLToAXI4.reset <= reset + inst TLMonitor_6 of TLMonitor_6 @[LazyModule.scala 60:13] + TLMonitor_6.io is invalid + TLMonitor_6.clock <= clock + TLMonitor_6.reset <= reset + inst AXI4Buffer of AXI4Buffer @[LazyModule.scala 60:13] + AXI4Buffer.io is invalid + AXI4Buffer.clock <= clock + AXI4Buffer.reset <= reset + inst AXI4Fragmenter of AXI4Fragmenter @[LazyModule.scala 60:13] + AXI4Fragmenter.io is invalid + AXI4Fragmenter.clock <= clock + AXI4Fragmenter.reset <= reset + inst AXI4ToTL of AXI4ToTL @[LazyModule.scala 60:13] + AXI4ToTL.io is invalid + AXI4ToTL.clock <= clock + AXI4ToTL.reset <= reset + inst l1tol2_TLWidthWidget of TLWidthWidget_l1tol2 @[LazyModule.scala 60:13] + l1tol2_TLWidthWidget.io is invalid + l1tol2_TLWidthWidget.clock <= clock + l1tol2_TLWidthWidget.reset <= reset + inst TLMonitor_7 of TLMonitor_7 @[LazyModule.scala 60:13] + TLMonitor_7.io is invalid + TLMonitor_7.clock <= clock + TLMonitor_7.reset <= reset + inst l1tol2_TLSourceShrinker of TLSourceShrinker_l1tol2 @[LazyModule.scala 60:13] + l1tol2_TLSourceShrinker.io is invalid + l1tol2_TLSourceShrinker.clock <= clock + l1tol2_TLSourceShrinker.reset <= reset + inst TLMonitor_8 of TLMonitor_8 @[LazyModule.scala 60:13] + TLMonitor_8.io is invalid + TLMonitor_8.clock <= clock + TLMonitor_8.reset <= reset + inst TLMonitor_9 of TLMonitor_9 @[LazyModule.scala 60:13] + TLMonitor_9.io is invalid + TLMonitor_9.clock <= clock + TLMonitor_9.reset <= reset + inst bootrom of TLROM_bootrom @[LazyModule.scala 60:13] + bootrom.io is invalid + bootrom.clock <= clock + bootrom.reset <= reset + inst bootrom_TLFragmenter of TLFragmenter_bootrom @[LazyModule.scala 60:13] + bootrom_TLFragmenter.io is invalid + bootrom_TLFragmenter.clock <= clock + bootrom_TLFragmenter.reset <= reset + inst TLMonitor_10 of TLMonitor_10 @[LazyModule.scala 60:13] + TLMonitor_10.io is invalid + TLMonitor_10.clock <= clock + TLMonitor_10.reset <= reset + inst TLMonitor_11 of TLMonitor_11 @[LazyModule.scala 60:13] + TLMonitor_11.io is invalid + TLMonitor_11.clock <= clock + TLMonitor_11.reset <= reset + inst zeros_0 of TLZero_zeros_0 @[LazyModule.scala 60:13] + zeros_0.io is invalid + zeros_0.clock <= clock + zeros_0.reset <= reset + inst zeros_0_TLFragmenter of TLFragmenter_zeros_0 @[LazyModule.scala 60:13] + zeros_0_TLFragmenter.io is invalid + zeros_0_TLFragmenter.clock <= clock + zeros_0_TLFragmenter.reset <= reset + inst TLMonitor_12 of TLMonitor_12 @[LazyModule.scala 60:13] + TLMonitor_12.io is invalid + TLMonitor_12.clock <= clock + TLMonitor_12.reset <= reset + inst TLMonitor_13 of TLMonitor_13 @[LazyModule.scala 60:13] + TLMonitor_13.io is invalid + TLMonitor_13.clock <= clock + TLMonitor_13.reset <= reset + inst coreplex of DefaultCoreplex_coreplex @[LazyModule.scala 60:13] + coreplex.io is invalid + coreplex.clock <= clock + coreplex.reset <= reset + inst TLMonitor_14 of TLMonitor_37 @[LazyModule.scala 60:13] + TLMonitor_14.io is invalid + TLMonitor_14.clock <= clock + TLMonitor_14.reset <= reset + inst TLMonitor_15 of TLMonitor_38 @[LazyModule.scala 60:13] + TLMonitor_15.io is invalid + TLMonitor_15.clock <= clock + TLMonitor_15.reset <= reset + inst TLMonitor_16 of TLMonitor_39 @[LazyModule.scala 60:13] + TLMonitor_16.io is invalid + TLMonitor_16.clock <= clock + TLMonitor_16.reset <= reset + wire _T_88 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_88 is invalid @[Bundles.scala 234:19] + wire _T_185 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_185 is invalid @[Bundles.scala 214:19] + _T_185.ready <= bootrom_TLAtomicAutomata.io.in.0.a.ready @[Bundles.scala 215:15] + _T_185.valid <= socBus.io.out.0.a.valid @[Bundles.scala 216:15] + _T_185.bits <- socBus.io.out.0.a.bits @[Bundles.scala 217:15] + _T_88.a <- _T_185 @[Bundles.scala 235:11] + wire _T_207 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_207 is invalid @[Bundles.scala 214:19] + _T_207.ready <= socBus.io.out.0.b.ready @[Bundles.scala 215:15] + _T_207.valid <= bootrom_TLAtomicAutomata.io.in.0.b.valid @[Bundles.scala 216:15] + _T_207.bits <- bootrom_TLAtomicAutomata.io.in.0.b.bits @[Bundles.scala 217:15] + _T_88.b <- _T_207 @[Bundles.scala 236:11] + wire _T_229 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_229 is invalid @[Bundles.scala 214:19] + _T_229.ready <= bootrom_TLAtomicAutomata.io.in.0.c.ready @[Bundles.scala 215:15] + _T_229.valid <= socBus.io.out.0.c.valid @[Bundles.scala 216:15] + _T_229.bits <- socBus.io.out.0.c.bits @[Bundles.scala 217:15] + _T_88.c <- _T_229 @[Bundles.scala 237:11] + wire _T_252 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_252 is invalid @[Bundles.scala 214:19] + _T_252.ready <= socBus.io.out.0.d.ready @[Bundles.scala 215:15] + _T_252.valid <= bootrom_TLAtomicAutomata.io.in.0.d.valid @[Bundles.scala 216:15] + _T_252.bits <- bootrom_TLAtomicAutomata.io.in.0.d.bits @[Bundles.scala 217:15] + _T_88.d <- _T_252 @[Bundles.scala 238:11] + wire _T_269 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_269 is invalid @[Bundles.scala 214:19] + _T_269.ready <= bootrom_TLAtomicAutomata.io.in.0.e.ready @[Bundles.scala 215:15] + _T_269.valid <= socBus.io.out.0.e.valid @[Bundles.scala 216:15] + _T_269.bits <- socBus.io.out.0.e.bits @[Bundles.scala 217:15] + _T_88.e <- _T_269 @[Bundles.scala 239:11] + TLMonitor.io.in[0] <- _T_88 @[BaseTop.scala 47:58] + bootrom_TLAtomicAutomata.io.in.0 <- socBus.io.out.0 @[BaseTop.scala 47:58] + wire _T_360 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_360 is invalid @[Bundles.scala 234:19] + wire _T_457 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_457 is invalid @[Bundles.scala 214:19] + _T_457.ready <= bootrom_TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_457.valid <= bootrom_TLAtomicAutomata.io.out.0.a.valid @[Bundles.scala 216:15] + _T_457.bits <- bootrom_TLAtomicAutomata.io.out.0.a.bits @[Bundles.scala 217:15] + _T_360.a <- _T_457 @[Bundles.scala 235:11] + wire _T_479 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_479 is invalid @[Bundles.scala 214:19] + _T_479.ready <= bootrom_TLAtomicAutomata.io.out.0.b.ready @[Bundles.scala 215:15] + _T_479.valid <= bootrom_TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_479.bits <- bootrom_TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_360.b <- _T_479 @[Bundles.scala 236:11] + wire _T_501 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_501 is invalid @[Bundles.scala 214:19] + _T_501.ready <= bootrom_TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_501.valid <= bootrom_TLAtomicAutomata.io.out.0.c.valid @[Bundles.scala 216:15] + _T_501.bits <- bootrom_TLAtomicAutomata.io.out.0.c.bits @[Bundles.scala 217:15] + _T_360.c <- _T_501 @[Bundles.scala 237:11] + wire _T_524 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_524 is invalid @[Bundles.scala 214:19] + _T_524.ready <= bootrom_TLAtomicAutomata.io.out.0.d.ready @[Bundles.scala 215:15] + _T_524.valid <= bootrom_TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_524.bits <- bootrom_TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_360.d <- _T_524 @[Bundles.scala 238:11] + wire _T_541 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_541 is invalid @[Bundles.scala 214:19] + _T_541.ready <= bootrom_TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_541.valid <= bootrom_TLAtomicAutomata.io.out.0.e.valid @[Bundles.scala 216:15] + _T_541.bits <- bootrom_TLAtomicAutomata.io.out.0.e.bits @[Bundles.scala 217:15] + _T_360.e <- _T_541 @[Bundles.scala 239:11] + TLMonitor_1.io.in[0] <- _T_360 @[BaseTop.scala 46:42] + bootrom_TLWidthWidget.io.in.0 <- bootrom_TLAtomicAutomata.io.out.0 @[BaseTop.scala 46:42] + wire _T_632 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_632 is invalid @[Bundles.scala 234:19] + wire _T_729 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_729 is invalid @[Bundles.scala 214:19] + _T_729.ready <= bootrom_TLBuffer.io.in.0.a.ready @[Bundles.scala 215:15] + _T_729.valid <= bootrom_TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_729.bits <- bootrom_TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_632.a <- _T_729 @[Bundles.scala 235:11] + wire _T_751 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_751 is invalid @[Bundles.scala 214:19] + _T_751.ready <= bootrom_TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_751.valid <= bootrom_TLBuffer.io.in.0.b.valid @[Bundles.scala 216:15] + _T_751.bits <- bootrom_TLBuffer.io.in.0.b.bits @[Bundles.scala 217:15] + _T_632.b <- _T_751 @[Bundles.scala 236:11] + wire _T_773 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_773 is invalid @[Bundles.scala 214:19] + _T_773.ready <= bootrom_TLBuffer.io.in.0.c.ready @[Bundles.scala 215:15] + _T_773.valid <= bootrom_TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_773.bits <- bootrom_TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_632.c <- _T_773 @[Bundles.scala 237:11] + wire _T_796 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_796 is invalid @[Bundles.scala 214:19] + _T_796.ready <= bootrom_TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_796.valid <= bootrom_TLBuffer.io.in.0.d.valid @[Bundles.scala 216:15] + _T_796.bits <- bootrom_TLBuffer.io.in.0.d.bits @[Bundles.scala 217:15] + _T_632.d <- _T_796 @[Bundles.scala 238:11] + wire _T_813 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_813 is invalid @[Bundles.scala 214:19] + _T_813.ready <= bootrom_TLBuffer.io.in.0.e.ready @[Bundles.scala 215:15] + _T_813.valid <= bootrom_TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_813.bits <- bootrom_TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_632.e <- _T_813 @[Bundles.scala 239:11] + TLMonitor_2.io.in[0] <- _T_632 @[BaseTop.scala 45:15] + bootrom_TLBuffer.io.in.0 <- bootrom_TLWidthWidget.io.out.0 @[BaseTop.scala 45:15] + wire _T_904 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_904 is invalid @[Bundles.scala 234:19] + wire _T_1001 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_1001 is invalid @[Bundles.scala 214:19] + _T_1001.ready <= peripheryBus.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1001.valid <= bootrom_TLBuffer.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1001.bits <- bootrom_TLBuffer.io.out.0.a.bits @[Bundles.scala 217:15] + _T_904.a <- _T_1001 @[Bundles.scala 235:11] + wire _T_1023 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_1023 is invalid @[Bundles.scala 214:19] + _T_1023.ready <= bootrom_TLBuffer.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1023.valid <= peripheryBus.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1023.bits <- peripheryBus.io.in.0.b.bits @[Bundles.scala 217:15] + _T_904.b <- _T_1023 @[Bundles.scala 236:11] + wire _T_1045 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1045 is invalid @[Bundles.scala 214:19] + _T_1045.ready <= peripheryBus.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1045.valid <= bootrom_TLBuffer.io.out.0.c.valid @[Bundles.scala 216:15] + _T_1045.bits <- bootrom_TLBuffer.io.out.0.c.bits @[Bundles.scala 217:15] + _T_904.c <- _T_1045 @[Bundles.scala 237:11] + wire _T_1068 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1068 is invalid @[Bundles.scala 214:19] + _T_1068.ready <= bootrom_TLBuffer.io.out.0.d.ready @[Bundles.scala 215:15] + _T_1068.valid <= peripheryBus.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1068.bits <- peripheryBus.io.in.0.d.bits @[Bundles.scala 217:15] + _T_904.d <- _T_1068 @[Bundles.scala 238:11] + wire _T_1085 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_1085 is invalid @[Bundles.scala 214:19] + _T_1085.ready <= peripheryBus.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1085.valid <= bootrom_TLBuffer.io.out.0.e.valid @[Bundles.scala 216:15] + _T_1085.bits <- bootrom_TLBuffer.io.out.0.e.bits @[Bundles.scala 217:15] + _T_904.e <- _T_1085 @[Bundles.scala 239:11] + TLMonitor_3.io.in[0] <- _T_904 @[BaseTop.scala 44:21] + peripheryBus.io.in.0 <- bootrom_TLBuffer.io.out.0 @[BaseTop.scala 44:21] + intBus.io.in.0 <- IntXing.io.out.0 @[Periphery.scala 65:20] + wire _T_1099 : {0 : UInt<1>[2]} @[Nodes.scala 225:62] + _T_1099 is invalid @[Nodes.scala 225:62] + IntXing.io.in.0 <- _T_1099.0 @[Periphery.scala 66:30] + wire _T_1186 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_1186 is invalid @[Bundles.scala 234:19] + wire _T_1283 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1283 is invalid @[Bundles.scala 214:19] + _T_1283.ready <= rocketchipPeripheryMasterAXI4Memconverter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1283.valid <= mem_0.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1283.bits <- mem_0.io.out.0.a.bits @[Bundles.scala 217:15] + _T_1186.a <- _T_1283 @[Bundles.scala 235:11] + wire _T_1305 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1305 is invalid @[Bundles.scala 214:19] + _T_1305.ready <= mem_0.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1305.valid <= rocketchipPeripheryMasterAXI4Memconverter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1305.bits <- rocketchipPeripheryMasterAXI4Memconverter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_1186.b <- _T_1305 @[Bundles.scala 236:11] + wire _T_1327 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1327 is invalid @[Bundles.scala 214:19] + _T_1327.ready <= rocketchipPeripheryMasterAXI4Memconverter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1327.valid <= mem_0.io.out.0.c.valid @[Bundles.scala 216:15] + _T_1327.bits <- mem_0.io.out.0.c.bits @[Bundles.scala 217:15] + _T_1186.c <- _T_1327 @[Bundles.scala 237:11] + wire _T_1350 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1350 is invalid @[Bundles.scala 214:19] + _T_1350.ready <= mem_0.io.out.0.d.ready @[Bundles.scala 215:15] + _T_1350.valid <= rocketchipPeripheryMasterAXI4Memconverter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1350.bits <- rocketchipPeripheryMasterAXI4Memconverter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_1186.d <- _T_1350 @[Bundles.scala 238:11] + wire _T_1367 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_1367 is invalid @[Bundles.scala 214:19] + _T_1367.ready <= rocketchipPeripheryMasterAXI4Memconverter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1367.valid <= mem_0.io.out.0.e.valid @[Bundles.scala 216:15] + _T_1367.bits <- mem_0.io.out.0.e.bits @[Bundles.scala 217:15] + _T_1186.e <- _T_1367 @[Bundles.scala 239:11] + TLMonitor_4.io.in[0] <- _T_1186 @[Periphery.scala 117:20] + rocketchipPeripheryMasterAXI4Memconverter.io.in.0 <- mem_0.io.out.0 @[Periphery.scala 117:20] + rocketchipPeripheryMasterAXI4Membuffer.io.in.0 <- rocketchipPeripheryMasterAXI4Memconverter.io.out.0 @[Periphery.scala 118:17] + io.mem_axi4.0 <- rocketchipPeripheryMasterAXI4Membuffer.io.out.0 @[Periphery.scala 119:14] + wire _T_1607 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_1607 is invalid @[Bundles.scala 234:19] + wire _T_1704 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1704 is invalid @[Bundles.scala 214:19] + _T_1704.ready <= TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1704.valid <= socBus.io.out.1.a.valid @[Bundles.scala 216:15] + _T_1704.bits <- socBus.io.out.1.a.bits @[Bundles.scala 217:15] + _T_1607.a <- _T_1704 @[Bundles.scala 235:11] + wire _T_1726 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1726 is invalid @[Bundles.scala 214:19] + _T_1726.ready <= socBus.io.out.1.b.ready @[Bundles.scala 215:15] + _T_1726.valid <= TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1726.bits <- TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_1607.b <- _T_1726 @[Bundles.scala 236:11] + wire _T_1748 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1748 is invalid @[Bundles.scala 214:19] + _T_1748.ready <= TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_1748.valid <= socBus.io.out.1.c.valid @[Bundles.scala 216:15] + _T_1748.bits <- socBus.io.out.1.c.bits @[Bundles.scala 217:15] + _T_1607.c <- _T_1748 @[Bundles.scala 237:11] + wire _T_1771 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_1771 is invalid @[Bundles.scala 214:19] + _T_1771.ready <= socBus.io.out.1.d.ready @[Bundles.scala 215:15] + _T_1771.valid <= TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_1771.bits <- TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_1607.d <- _T_1771 @[Bundles.scala 238:11] + wire _T_1788 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_1788 is invalid @[Bundles.scala 214:19] + _T_1788.ready <= TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_1788.valid <= socBus.io.out.1.e.valid @[Bundles.scala 216:15] + _T_1788.bits <- socBus.io.out.1.e.bits @[Bundles.scala 217:15] + _T_1607.e <- _T_1788 @[Bundles.scala 239:11] + TLMonitor_5.io.in[0] <- _T_1607 @[Periphery.scala 189:42] + TLWidthWidget.io.in.0 <- socBus.io.out.1 @[Periphery.scala 189:42] + wire _T_1879 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_1879 is invalid @[Bundles.scala 234:19] + wire _T_1976 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1976 is invalid @[Bundles.scala 214:19] + _T_1976.ready <= TLToAXI4.io.in.0.a.ready @[Bundles.scala 215:15] + _T_1976.valid <= TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_1976.bits <- TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_1879.a <- _T_1976 @[Bundles.scala 235:11] + wire _T_1998 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_1998 is invalid @[Bundles.scala 214:19] + _T_1998.ready <= TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_1998.valid <= TLToAXI4.io.in.0.b.valid @[Bundles.scala 216:15] + _T_1998.bits <- TLToAXI4.io.in.0.b.bits @[Bundles.scala 217:15] + _T_1879.b <- _T_1998 @[Bundles.scala 236:11] + wire _T_2020 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2020 is invalid @[Bundles.scala 214:19] + _T_2020.ready <= TLToAXI4.io.in.0.c.ready @[Bundles.scala 215:15] + _T_2020.valid <= TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_2020.bits <- TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_1879.c <- _T_2020 @[Bundles.scala 237:11] + wire _T_2043 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2043 is invalid @[Bundles.scala 214:19] + _T_2043.ready <= TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_2043.valid <= TLToAXI4.io.in.0.d.valid @[Bundles.scala 216:15] + _T_2043.bits <- TLToAXI4.io.in.0.d.bits @[Bundles.scala 217:15] + _T_1879.d <- _T_2043 @[Bundles.scala 238:11] + wire _T_2060 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_2060 is invalid @[Bundles.scala 214:19] + _T_2060.ready <= TLToAXI4.io.in.0.e.ready @[Bundles.scala 215:15] + _T_2060.valid <= TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_2060.bits <- TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_1879.e <- _T_2060 @[Bundles.scala 239:11] + TLMonitor_6.io.in[0] <- _T_1879 @[Periphery.scala 188:37] + TLToAXI4.io.in.0 <- TLWidthWidget.io.out.0 @[Periphery.scala 188:37] + AXI4Buffer.io.in.0 <- TLToAXI4.io.out.0 @[Periphery.scala 186:17] + io.mmio_axi4.0 <- AXI4Buffer.io.out.0 @[Periphery.scala 185:13] + AXI4Fragmenter.io.in.0 <- io.l2_frontend_bus_axi4.0 @[Periphery.scala 221:21] + AXI4ToTL.io.in.0 <- AXI4Fragmenter.io.out.0 @[Periphery.scala 220:15] + wire _T_2598 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_2598 is invalid @[Bundles.scala 234:19] + wire _T_2695 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2695 is invalid @[Bundles.scala 214:19] + _T_2695.ready <= l1tol2_TLWidthWidget.io.in.0.a.ready @[Bundles.scala 215:15] + _T_2695.valid <= AXI4ToTL.io.out.0.a.valid @[Bundles.scala 216:15] + _T_2695.bits <- AXI4ToTL.io.out.0.a.bits @[Bundles.scala 217:15] + _T_2598.a <- _T_2695 @[Bundles.scala 235:11] + wire _T_2717 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2717 is invalid @[Bundles.scala 214:19] + _T_2717.ready <= AXI4ToTL.io.out.0.b.ready @[Bundles.scala 215:15] + _T_2717.valid <= l1tol2_TLWidthWidget.io.in.0.b.valid @[Bundles.scala 216:15] + _T_2717.bits <- l1tol2_TLWidthWidget.io.in.0.b.bits @[Bundles.scala 217:15] + _T_2598.b <- _T_2717 @[Bundles.scala 236:11] + wire _T_2739 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2739 is invalid @[Bundles.scala 214:19] + _T_2739.ready <= l1tol2_TLWidthWidget.io.in.0.c.ready @[Bundles.scala 215:15] + _T_2739.valid <= AXI4ToTL.io.out.0.c.valid @[Bundles.scala 216:15] + _T_2739.bits <- AXI4ToTL.io.out.0.c.bits @[Bundles.scala 217:15] + _T_2598.c <- _T_2739 @[Bundles.scala 237:11] + wire _T_2762 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_2762 is invalid @[Bundles.scala 214:19] + _T_2762.ready <= AXI4ToTL.io.out.0.d.ready @[Bundles.scala 215:15] + _T_2762.valid <= l1tol2_TLWidthWidget.io.in.0.d.valid @[Bundles.scala 216:15] + _T_2762.bits <- l1tol2_TLWidthWidget.io.in.0.d.bits @[Bundles.scala 217:15] + _T_2598.d <- _T_2762 @[Bundles.scala 238:11] + wire _T_2779 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_2779 is invalid @[Bundles.scala 214:19] + _T_2779.ready <= l1tol2_TLWidthWidget.io.in.0.e.ready @[Bundles.scala 215:15] + _T_2779.valid <= AXI4ToTL.io.out.0.e.valid @[Bundles.scala 216:15] + _T_2779.bits <- AXI4ToTL.io.out.0.e.bits @[Bundles.scala 217:15] + _T_2598.e <- _T_2779 @[Bundles.scala 239:11] + TLMonitor_7.io.in[0] <- _T_2598 @[Periphery.scala 219:36] + l1tol2_TLWidthWidget.io.in.0 <- AXI4ToTL.io.out.0 @[Periphery.scala 219:36] + wire _T_2870 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_2870 is invalid @[Bundles.scala 234:19] + wire _T_2967 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2967 is invalid @[Bundles.scala 214:19] + _T_2967.ready <= l1tol2_TLSourceShrinker.io.in.0.a.ready @[Bundles.scala 215:15] + _T_2967.valid <= l1tol2_TLWidthWidget.io.out.0.a.valid @[Bundles.scala 216:15] + _T_2967.bits <- l1tol2_TLWidthWidget.io.out.0.a.bits @[Bundles.scala 217:15] + _T_2870.a <- _T_2967 @[Bundles.scala 235:11] + wire _T_2989 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_2989 is invalid @[Bundles.scala 214:19] + _T_2989.ready <= l1tol2_TLWidthWidget.io.out.0.b.ready @[Bundles.scala 215:15] + _T_2989.valid <= l1tol2_TLSourceShrinker.io.in.0.b.valid @[Bundles.scala 216:15] + _T_2989.bits <- l1tol2_TLSourceShrinker.io.in.0.b.bits @[Bundles.scala 217:15] + _T_2870.b <- _T_2989 @[Bundles.scala 236:11] + wire _T_3011 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3011 is invalid @[Bundles.scala 214:19] + _T_3011.ready <= l1tol2_TLSourceShrinker.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3011.valid <= l1tol2_TLWidthWidget.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3011.bits <- l1tol2_TLWidthWidget.io.out.0.c.bits @[Bundles.scala 217:15] + _T_2870.c <- _T_3011 @[Bundles.scala 237:11] + wire _T_3034 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3034 is invalid @[Bundles.scala 214:19] + _T_3034.ready <= l1tol2_TLWidthWidget.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3034.valid <= l1tol2_TLSourceShrinker.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3034.bits <- l1tol2_TLSourceShrinker.io.in.0.d.bits @[Bundles.scala 217:15] + _T_2870.d <- _T_3034 @[Bundles.scala 238:11] + wire _T_3051 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_3051 is invalid @[Bundles.scala 214:19] + _T_3051.ready <= l1tol2_TLSourceShrinker.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3051.valid <= l1tol2_TLWidthWidget.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3051.bits <- l1tol2_TLWidthWidget.io.out.0.e.bits @[Bundles.scala 217:15] + _T_2870.e <- _T_3051 @[Bundles.scala 239:11] + TLMonitor_8.io.in[0] <- _T_2870 @[Periphery.scala 218:45] + l1tol2_TLSourceShrinker.io.in.0 <- l1tol2_TLWidthWidget.io.out.0 @[Periphery.scala 218:45] + wire _T_3142 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_3142 is invalid @[Bundles.scala 234:19] + wire _T_3239 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3239 is invalid @[Bundles.scala 214:19] + _T_3239.ready <= l2FrontendBus.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3239.valid <= l1tol2_TLSourceShrinker.io.out.0.a.valid @[Bundles.scala 216:15] + _T_3239.bits <- l1tol2_TLSourceShrinker.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3142.a <- _T_3239 @[Bundles.scala 235:11] + wire _T_3261 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_3261 is invalid @[Bundles.scala 214:19] + _T_3261.ready <= l1tol2_TLSourceShrinker.io.out.0.b.ready @[Bundles.scala 215:15] + _T_3261.valid <= l2FrontendBus.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3261.bits <- l2FrontendBus.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3142.b <- _T_3261 @[Bundles.scala 236:11] + wire _T_3283 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3283 is invalid @[Bundles.scala 214:19] + _T_3283.ready <= l2FrontendBus.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3283.valid <= l1tol2_TLSourceShrinker.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3283.bits <- l1tol2_TLSourceShrinker.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3142.c <- _T_3283 @[Bundles.scala 237:11] + wire _T_3306 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3306 is invalid @[Bundles.scala 214:19] + _T_3306.ready <= l1tol2_TLSourceShrinker.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3306.valid <= l2FrontendBus.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3306.bits <- l2FrontendBus.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3142.d <- _T_3306 @[Bundles.scala 238:11] + wire _T_3323 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_3323 is invalid @[Bundles.scala 214:19] + _T_3323.ready <= l2FrontendBus.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3323.valid <= l1tol2_TLSourceShrinker.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3323.bits <- l1tol2_TLSourceShrinker.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3142.e <- _T_3323 @[Bundles.scala 239:11] + TLMonitor_9.io.in[0] <- _T_3142 @[Periphery.scala 217:22] + l2FrontendBus.io.in.0 <- l1tol2_TLSourceShrinker.io.out.0 @[Periphery.scala 217:22] + wire _T_3414 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3414 is invalid @[Bundles.scala 234:19] + wire _T_3511 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_3511 is invalid @[Bundles.scala 214:19] + _T_3511.ready <= bootrom_TLFragmenter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3511.valid <= peripheryBus.io.out.0.a.valid @[Bundles.scala 216:15] + _T_3511.bits <- peripheryBus.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3414.a <- _T_3511 @[Bundles.scala 235:11] + wire _T_3533 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_3533 is invalid @[Bundles.scala 214:19] + _T_3533.ready <= peripheryBus.io.out.0.b.ready @[Bundles.scala 215:15] + _T_3533.valid <= bootrom_TLFragmenter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3533.bits <- bootrom_TLFragmenter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3414.b <- _T_3533 @[Bundles.scala 236:11] + wire _T_3555 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<13>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3555 is invalid @[Bundles.scala 214:19] + _T_3555.ready <= bootrom_TLFragmenter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3555.valid <= peripheryBus.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3555.bits <- peripheryBus.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3414.c <- _T_3555 @[Bundles.scala 237:11] + wire _T_3578 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3578 is invalid @[Bundles.scala 214:19] + _T_3578.ready <= peripheryBus.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3578.valid <= bootrom_TLFragmenter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3578.bits <- bootrom_TLFragmenter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3414.d <- _T_3578 @[Bundles.scala 238:11] + wire _T_3595 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_3595 is invalid @[Bundles.scala 214:19] + _T_3595.ready <= bootrom_TLFragmenter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3595.valid <= peripheryBus.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3595.bits <- peripheryBus.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3414.e <- _T_3595 @[Bundles.scala 239:11] + TLMonitor_10.io.in[0] <- _T_3414 @[Periphery.scala 312:78] + bootrom_TLFragmenter.io.in.0 <- peripheryBus.io.out.0 @[Periphery.scala 312:78] + wire _T_3686 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, data : UInt<32>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3686 is invalid @[Bundles.scala 234:19] + wire _T_3783 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_3783 is invalid @[Bundles.scala 214:19] + _T_3783.ready <= bootrom.io.in.0.a.ready @[Bundles.scala 215:15] + _T_3783.valid <= bootrom_TLFragmenter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_3783.bits <- bootrom_TLFragmenter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_3686.a <- _T_3783 @[Bundles.scala 235:11] + wire _T_3805 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<4>, data : UInt<32>}} @[Bundles.scala 214:19] + _T_3805 is invalid @[Bundles.scala 214:19] + _T_3805.ready <= bootrom_TLFragmenter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_3805.valid <= bootrom.io.in.0.b.valid @[Bundles.scala 216:15] + _T_3805.bits <- bootrom.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3686.b <- _T_3805 @[Bundles.scala 236:11] + wire _T_3827 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3827 is invalid @[Bundles.scala 214:19] + _T_3827.ready <= bootrom.io.in.0.c.ready @[Bundles.scala 215:15] + _T_3827.valid <= bootrom_TLFragmenter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_3827.bits <- bootrom_TLFragmenter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_3686.c <- _T_3827 @[Bundles.scala 237:11] + wire _T_3850 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_3850 is invalid @[Bundles.scala 214:19] + _T_3850.ready <= bootrom_TLFragmenter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_3850.valid <= bootrom.io.in.0.d.valid @[Bundles.scala 216:15] + _T_3850.bits <- bootrom.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3686.d <- _T_3850 @[Bundles.scala 238:11] + wire _T_3867 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_3867 is invalid @[Bundles.scala 214:19] + _T_3867.ready <= bootrom.io.in.0.e.ready @[Bundles.scala 215:15] + _T_3867.valid <= bootrom_TLFragmenter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_3867.bits <- bootrom_TLFragmenter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_3686.e <- _T_3867 @[Bundles.scala 239:11] + TLMonitor_11.io.in[0] <- _T_3686 @[Periphery.scala 312:16] + bootrom.io.in.0 <- bootrom_TLFragmenter.io.out.0 @[Periphery.scala 312:16] + wire _T_3958 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_3958 is invalid @[Bundles.scala 234:19] + wire _T_4055 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4055 is invalid @[Bundles.scala 214:19] + _T_4055.ready <= zeros_0_TLFragmenter.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4055.valid <= mem_0.io.out.1.a.valid @[Bundles.scala 216:15] + _T_4055.bits <- mem_0.io.out.1.a.bits @[Bundles.scala 217:15] + _T_3958.a <- _T_4055 @[Bundles.scala 235:11] + wire _T_4077 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4077 is invalid @[Bundles.scala 214:19] + _T_4077.ready <= mem_0.io.out.1.b.ready @[Bundles.scala 215:15] + _T_4077.valid <= zeros_0_TLFragmenter.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4077.bits <- zeros_0_TLFragmenter.io.in.0.b.bits @[Bundles.scala 217:15] + _T_3958.b <- _T_4077 @[Bundles.scala 236:11] + wire _T_4099 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4099 is invalid @[Bundles.scala 214:19] + _T_4099.ready <= zeros_0_TLFragmenter.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4099.valid <= mem_0.io.out.1.c.valid @[Bundles.scala 216:15] + _T_4099.bits <- mem_0.io.out.1.c.bits @[Bundles.scala 217:15] + _T_3958.c <- _T_4099 @[Bundles.scala 237:11] + wire _T_4122 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4122 is invalid @[Bundles.scala 214:19] + _T_4122.ready <= mem_0.io.out.1.d.ready @[Bundles.scala 215:15] + _T_4122.valid <= zeros_0_TLFragmenter.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4122.bits <- zeros_0_TLFragmenter.io.in.0.d.bits @[Bundles.scala 217:15] + _T_3958.d <- _T_4122 @[Bundles.scala 238:11] + wire _T_4139 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4139 is invalid @[Bundles.scala 214:19] + _T_4139.ready <= zeros_0_TLFragmenter.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4139.valid <= mem_0.io.out.1.e.valid @[Bundles.scala 216:15] + _T_4139.bits <- mem_0.io.out.1.e.bits @[Bundles.scala 217:15] + _T_3958.e <- _T_4139 @[Bundles.scala 239:11] + TLMonitor_12.io.in[0] <- _T_3958 @[Periphery.scala 149:59] + zeros_0_TLFragmenter.io.in.0 <- mem_0.io.out.1 @[Periphery.scala 149:59] + wire _T_4230 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_4230 is invalid @[Bundles.scala 234:19] + wire _T_4327 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4327 is invalid @[Bundles.scala 214:19] + _T_4327.ready <= zeros_0.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4327.valid <= zeros_0_TLFragmenter.io.out.0.a.valid @[Bundles.scala 216:15] + _T_4327.bits <- zeros_0_TLFragmenter.io.out.0.a.bits @[Bundles.scala 217:15] + _T_4230.a <- _T_4327 @[Bundles.scala 235:11] + wire _T_4349 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4349 is invalid @[Bundles.scala 214:19] + _T_4349.ready <= zeros_0_TLFragmenter.io.out.0.b.ready @[Bundles.scala 215:15] + _T_4349.valid <= zeros_0.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4349.bits <- zeros_0.io.in.0.b.bits @[Bundles.scala 217:15] + _T_4230.b <- _T_4349 @[Bundles.scala 236:11] + wire _T_4371 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4371 is invalid @[Bundles.scala 214:19] + _T_4371.ready <= zeros_0.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4371.valid <= zeros_0_TLFragmenter.io.out.0.c.valid @[Bundles.scala 216:15] + _T_4371.bits <- zeros_0_TLFragmenter.io.out.0.c.bits @[Bundles.scala 217:15] + _T_4230.c <- _T_4371 @[Bundles.scala 237:11] + wire _T_4394 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4394 is invalid @[Bundles.scala 214:19] + _T_4394.ready <= zeros_0_TLFragmenter.io.out.0.d.ready @[Bundles.scala 215:15] + _T_4394.valid <= zeros_0.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4394.bits <- zeros_0.io.in.0.d.bits @[Bundles.scala 217:15] + _T_4230.d <- _T_4394 @[Bundles.scala 238:11] + wire _T_4411 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4411 is invalid @[Bundles.scala 214:19] + _T_4411.ready <= zeros_0.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4411.valid <= zeros_0_TLFragmenter.io.out.0.e.valid @[Bundles.scala 216:15] + _T_4411.bits <- zeros_0_TLFragmenter.io.out.0.e.bits @[Bundles.scala 217:15] + _T_4230.e <- _T_4411 @[Bundles.scala 239:11] + TLMonitor_13.io.in[0] <- _T_4230 @[Periphery.scala 149:15] + zeros_0.io.in.0 <- zeros_0_TLFragmenter.io.out.0 @[Periphery.scala 149:15] + wire _T_4502 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}} @[Bundles.scala 234:19] + _T_4502 is invalid @[Bundles.scala 234:19] + wire _T_4599 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4599 is invalid @[Bundles.scala 214:19] + _T_4599.ready <= coreplex.io.l2in.0.a.ready @[Bundles.scala 215:15] + _T_4599.valid <= l2FrontendBus.io.out.0.a.valid @[Bundles.scala 216:15] + _T_4599.bits <- l2FrontendBus.io.out.0.a.bits @[Bundles.scala 217:15] + _T_4502.a <- _T_4599 @[Bundles.scala 235:11] + wire _T_4621 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4621 is invalid @[Bundles.scala 214:19] + _T_4621.ready <= l2FrontendBus.io.out.0.b.ready @[Bundles.scala 215:15] + _T_4621.valid <= coreplex.io.l2in.0.b.valid @[Bundles.scala 216:15] + _T_4621.bits <- coreplex.io.l2in.0.b.bits @[Bundles.scala 217:15] + _T_4502.b <- _T_4621 @[Bundles.scala 236:11] + wire _T_4643 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4643 is invalid @[Bundles.scala 214:19] + _T_4643.ready <= coreplex.io.l2in.0.c.ready @[Bundles.scala 215:15] + _T_4643.valid <= l2FrontendBus.io.out.0.c.valid @[Bundles.scala 216:15] + _T_4643.bits <- l2FrontendBus.io.out.0.c.bits @[Bundles.scala 217:15] + _T_4502.c <- _T_4643 @[Bundles.scala 237:11] + wire _T_4666 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4666 is invalid @[Bundles.scala 214:19] + _T_4666.ready <= l2FrontendBus.io.out.0.d.ready @[Bundles.scala 215:15] + _T_4666.valid <= coreplex.io.l2in.0.d.valid @[Bundles.scala 216:15] + _T_4666.bits <- coreplex.io.l2in.0.d.bits @[Bundles.scala 217:15] + _T_4502.d <- _T_4666 @[Bundles.scala 238:11] + wire _T_4683 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}} @[Bundles.scala 214:19] + _T_4683 is invalid @[Bundles.scala 214:19] + _T_4683.ready <= coreplex.io.l2in.0.e.ready @[Bundles.scala 215:15] + _T_4683.valid <= l2FrontendBus.io.out.0.e.valid @[Bundles.scala 216:15] + _T_4683.bits <- l2FrontendBus.io.out.0.e.bits @[Bundles.scala 217:15] + _T_4502.e <- _T_4683 @[Bundles.scala 239:11] + TLMonitor_14.io.in[0] <- _T_4502 @[RocketPlexMaster.scala 18:17] + coreplex.io.l2in.0 <- l2FrontendBus.io.out.0 @[RocketPlexMaster.scala 18:17] + wire _T_4774 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_4774 is invalid @[Bundles.scala 234:19] + wire _T_4871 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4871 is invalid @[Bundles.scala 214:19] + _T_4871.ready <= socBus.io.in.0.a.ready @[Bundles.scala 215:15] + _T_4871.valid <= coreplex.io.mmio.0.a.valid @[Bundles.scala 216:15] + _T_4871.bits <- coreplex.io.mmio.0.a.bits @[Bundles.scala 217:15] + _T_4774.a <- _T_4871 @[Bundles.scala 235:11] + wire _T_4893 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<31>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_4893 is invalid @[Bundles.scala 214:19] + _T_4893.ready <= coreplex.io.mmio.0.b.ready @[Bundles.scala 215:15] + _T_4893.valid <= socBus.io.in.0.b.valid @[Bundles.scala 216:15] + _T_4893.bits <- socBus.io.in.0.b.bits @[Bundles.scala 217:15] + _T_4774.b <- _T_4893 @[Bundles.scala 236:11] + wire _T_4915 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<31>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4915 is invalid @[Bundles.scala 214:19] + _T_4915.ready <= socBus.io.in.0.c.ready @[Bundles.scala 215:15] + _T_4915.valid <= coreplex.io.mmio.0.c.valid @[Bundles.scala 216:15] + _T_4915.bits <- coreplex.io.mmio.0.c.bits @[Bundles.scala 217:15] + _T_4774.c <- _T_4915 @[Bundles.scala 237:11] + wire _T_4938 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_4938 is invalid @[Bundles.scala 214:19] + _T_4938.ready <= coreplex.io.mmio.0.d.ready @[Bundles.scala 215:15] + _T_4938.valid <= socBus.io.in.0.d.valid @[Bundles.scala 216:15] + _T_4938.bits <- socBus.io.in.0.d.bits @[Bundles.scala 217:15] + _T_4774.d <- _T_4938 @[Bundles.scala 238:11] + wire _T_4955 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_4955 is invalid @[Bundles.scala 214:19] + _T_4955.ready <= socBus.io.in.0.e.ready @[Bundles.scala 215:15] + _T_4955.valid <= coreplex.io.mmio.0.e.valid @[Bundles.scala 216:15] + _T_4955.bits <- coreplex.io.mmio.0.e.bits @[Bundles.scala 217:15] + _T_4774.e <- _T_4955 @[Bundles.scala 239:11] + TLMonitor_15.io.in[0] <- _T_4774 @[RocketPlexMaster.scala 19:15] + socBus.io.in.0 <- coreplex.io.mmio.0 @[RocketPlexMaster.scala 19:15] + coreplex.io.interrupts.0 <- intBus.io.out.0 @[RocketPlexMaster.scala 20:20] + wire _T_5046 : {a : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, b : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, d : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}} @[Bundles.scala 234:19] + _T_5046 is invalid @[Bundles.scala 234:19] + wire _T_5143 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5143 is invalid @[Bundles.scala 214:19] + _T_5143.ready <= mem_0.io.in.0.a.ready @[Bundles.scala 215:15] + _T_5143.valid <= coreplex.io.mem.0.0.a.valid @[Bundles.scala 216:15] + _T_5143.bits <- coreplex.io.mem.0.0.a.bits @[Bundles.scala 217:15] + _T_5046.a <- _T_5143 @[Bundles.scala 235:11] + wire _T_5165 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}} @[Bundles.scala 214:19] + _T_5165 is invalid @[Bundles.scala 214:19] + _T_5165.ready <= coreplex.io.mem.0.0.b.ready @[Bundles.scala 215:15] + _T_5165.valid <= mem_0.io.in.0.b.valid @[Bundles.scala 216:15] + _T_5165.bits <- mem_0.io.in.0.b.bits @[Bundles.scala 217:15] + _T_5046.b <- _T_5165 @[Bundles.scala 236:11] + wire _T_5187 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5187 is invalid @[Bundles.scala 214:19] + _T_5187.ready <= mem_0.io.in.0.c.ready @[Bundles.scala 215:15] + _T_5187.valid <= coreplex.io.mem.0.0.c.valid @[Bundles.scala 216:15] + _T_5187.bits <- coreplex.io.mem.0.0.c.bits @[Bundles.scala 217:15] + _T_5046.c <- _T_5187 @[Bundles.scala 237:11] + wire _T_5210 : {ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}} @[Bundles.scala 214:19] + _T_5210 is invalid @[Bundles.scala 214:19] + _T_5210.ready <= coreplex.io.mem.0.0.d.ready @[Bundles.scala 215:15] + _T_5210.valid <= mem_0.io.in.0.d.valid @[Bundles.scala 216:15] + _T_5210.bits <- mem_0.io.in.0.d.bits @[Bundles.scala 217:15] + _T_5046.d <- _T_5210 @[Bundles.scala 238:11] + wire _T_5227 : {ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}} @[Bundles.scala 214:19] + _T_5227 is invalid @[Bundles.scala 214:19] + _T_5227.ready <= mem_0.io.in.0.e.ready @[Bundles.scala 215:15] + _T_5227.valid <= coreplex.io.mem.0.0.e.valid @[Bundles.scala 216:15] + _T_5227.bits <- coreplex.io.mem.0.0.e.bits @[Bundles.scala 217:15] + _T_5046.e <- _T_5227 @[Bundles.scala 239:11] + TLMonitor_16.io.in[0] <- _T_5046 @[RocketPlexMaster.scala 23:70] + mem_0.io.in.0 <- coreplex.io.mem.0.0 @[RocketPlexMaster.scala 23:70] + node _T_5320 = bits(io.interrupts, 0, 0) @[Periphery.scala 82:95] + _T_1099.0[0] <= _T_5320 @[Periphery.scala 82:79] + node _T_5321 = bits(io.interrupts, 1, 1) @[Periphery.scala 82:95] + _T_1099.0[1] <= _T_5321 @[Periphery.scala 82:79] + wire _T_5380 : {req : {mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}, flip resp : {mem : {data : UInt<34>, resp : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}} @[Debug.scala 328:19] + _T_5380 is invalid @[Debug.scala 328:19] + inst AsyncQueueSource of AsyncQueueSource_1 @[AsyncBundle.scala 44:24] + AsyncQueueSource.io is invalid + AsyncQueueSource.clock <= clock + AsyncQueueSource.reset <= reset + AsyncQueueSource.io.enq.valid <= io.debug.req.valid @[AsyncBundle.scala 45:25] + AsyncQueueSource.io.enq.bits <- io.debug.req.bits @[AsyncBundle.scala 46:24] + io.debug.req.ready <= AsyncQueueSource.io.enq.ready @[AsyncBundle.scala 47:13] + wire _T_5456 : {mem : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}[1], flip ridx : UInt<1>, widx : UInt<1>, flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>} @[AsyncBundle.scala 48:19] + _T_5456 is invalid @[AsyncBundle.scala 48:19] + AsyncQueueSource.io.ridx <= _T_5456.ridx @[AsyncBundle.scala 49:20] + AsyncQueueSource.io.ridx_valid <= _T_5456.ridx_valid @[AsyncBundle.scala 50:26] + _T_5456.mem <- AsyncQueueSource.io.mem @[AsyncBundle.scala 51:13] + _T_5456.widx <= AsyncQueueSource.io.widx @[AsyncBundle.scala 52:14] + _T_5456.widx_valid <= AsyncQueueSource.io.widx_valid @[AsyncBundle.scala 53:20] + AsyncQueueSource.io.sink_reset_n <= _T_5456.sink_reset_n @[AsyncBundle.scala 54:28] + node _T_5475 = eq(AsyncQueueSource.reset, UInt<1>("h00")) @[AsyncBundle.scala 55:27] + _T_5456.source_reset_n <= _T_5475 @[AsyncBundle.scala 55:24] + _T_5380.req <- _T_5456 @[Debug.scala 329:13] + inst AsyncQueueSink of AsyncQueueSink_1 @[AsyncBundle.scala 25:22] + AsyncQueueSink.io is invalid + AsyncQueueSink.clock <= clock + AsyncQueueSink.reset <= reset + _T_5380.resp.ridx <= AsyncQueueSink.io.ridx @[AsyncBundle.scala 26:12] + _T_5380.resp.ridx_valid <= AsyncQueueSink.io.ridx_valid @[AsyncBundle.scala 27:18] + AsyncQueueSink.io.widx <= _T_5380.resp.widx @[AsyncBundle.scala 28:18] + AsyncQueueSink.io.widx_valid <= _T_5380.resp.widx_valid @[AsyncBundle.scala 29:24] + AsyncQueueSink.io.mem <- _T_5380.resp.mem @[AsyncBundle.scala 30:18] + AsyncQueueSink.io.source_reset_n <= _T_5380.resp.source_reset_n @[AsyncBundle.scala 31:28] + node _T_5477 = eq(AsyncQueueSink.reset, UInt<1>("h00")) @[AsyncBundle.scala 32:23] + _T_5380.resp.sink_reset_n <= _T_5477 @[AsyncBundle.scala 32:20] + wire _T_5489 : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}} @[AsyncBundle.scala 33:19] + _T_5489 is invalid @[AsyncBundle.scala 33:19] + _T_5489.valid <= AsyncQueueSink.io.deq.valid @[AsyncBundle.scala 34:15] + _T_5489.bits <- AsyncQueueSink.io.deq.bits @[AsyncBundle.scala 35:14] + AsyncQueueSink.io.deq.ready <= _T_5489.ready @[AsyncBundle.scala 36:23] + io.debug.resp <- _T_5489 @[Debug.scala 330:12] + coreplex.io.debug <- _T_5380 @[RISCVPlatform.scala 77:60] + reg _T_5501 : UInt<7>, clock with : (reset => (reset, UInt<7>("h00"))) @[Reg.scala 26:44] + node _T_5503 = eq(_T_5501, UInt<7>("h063")) @[RISCVPlatform.scala 105:30] + node _T_5506 = add(_T_5501, UInt<1>("h01")) @[RISCVPlatform.scala 106:52] + node _T_5507 = tail(_T_5506, 1) @[RISCVPlatform.scala 106:52] + node _T_5508 = mux(_T_5503, UInt<1>("h00"), _T_5507) @[RISCVPlatform.scala 106:22] + _T_5501 <= _T_5508 @[RISCVPlatform.scala 106:16] + node _T_5509 = bits(_T_5501, 6, 6) @[RISCVPlatform.scala 108:53] + coreplex.io.rtcToggle <= _T_5509 @[RISCVPlatform.scala 108:40] + coreplex.io.resetVector <= UInt<13>("h01000") @[RISCVPlatform.scala 127:40] + coreplex.io.tcrs[0].clock <= clock @[RocketPlexMaster.scala 37:15] + coreplex.io.tcrs[0].reset <= reset @[RocketPlexMaster.scala 38:15] + + module AXI4RAM : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + smem mem : UInt<8>[8][33554432] @[SRAM.scala 36:21] + node _T_313 = shr(io.in.0.ar.bits.addr, 3) @[SRAM.scala 38:49] + node _T_314 = bits(_T_313, 0, 0) @[SRAM.scala 38:73] + node _T_315 = bits(_T_313, 1, 1) @[SRAM.scala 38:73] + node _T_316 = bits(_T_313, 2, 2) @[SRAM.scala 38:73] + node _T_317 = bits(_T_313, 3, 3) @[SRAM.scala 38:73] + node _T_318 = bits(_T_313, 4, 4) @[SRAM.scala 38:73] + node _T_319 = bits(_T_313, 5, 5) @[SRAM.scala 38:73] + node _T_320 = bits(_T_313, 6, 6) @[SRAM.scala 38:73] + node _T_321 = bits(_T_313, 7, 7) @[SRAM.scala 38:73] + node _T_322 = bits(_T_313, 8, 8) @[SRAM.scala 38:73] + node _T_323 = bits(_T_313, 9, 9) @[SRAM.scala 38:73] + node _T_324 = bits(_T_313, 10, 10) @[SRAM.scala 38:73] + node _T_325 = bits(_T_313, 11, 11) @[SRAM.scala 38:73] + node _T_326 = bits(_T_313, 12, 12) @[SRAM.scala 38:73] + node _T_327 = bits(_T_313, 13, 13) @[SRAM.scala 38:73] + node _T_328 = bits(_T_313, 14, 14) @[SRAM.scala 38:73] + node _T_329 = bits(_T_313, 15, 15) @[SRAM.scala 38:73] + node _T_330 = bits(_T_313, 16, 16) @[SRAM.scala 38:73] + node _T_331 = bits(_T_313, 17, 17) @[SRAM.scala 38:73] + node _T_332 = bits(_T_313, 18, 18) @[SRAM.scala 38:73] + node _T_333 = bits(_T_313, 19, 19) @[SRAM.scala 38:73] + node _T_334 = bits(_T_313, 20, 20) @[SRAM.scala 38:73] + node _T_335 = bits(_T_313, 21, 21) @[SRAM.scala 38:73] + node _T_336 = bits(_T_313, 22, 22) @[SRAM.scala 38:73] + node _T_337 = bits(_T_313, 23, 23) @[SRAM.scala 38:73] + node _T_338 = bits(_T_313, 24, 24) @[SRAM.scala 38:73] + node _T_339 = cat(_T_316, _T_315) @[Cat.scala 30:58] + node _T_340 = cat(_T_339, _T_314) @[Cat.scala 30:58] + node _T_341 = cat(_T_319, _T_318) @[Cat.scala 30:58] + node _T_342 = cat(_T_341, _T_317) @[Cat.scala 30:58] + node _T_343 = cat(_T_342, _T_340) @[Cat.scala 30:58] + node _T_344 = cat(_T_322, _T_321) @[Cat.scala 30:58] + node _T_345 = cat(_T_344, _T_320) @[Cat.scala 30:58] + node _T_346 = cat(_T_325, _T_324) @[Cat.scala 30:58] + node _T_347 = cat(_T_346, _T_323) @[Cat.scala 30:58] + node _T_348 = cat(_T_347, _T_345) @[Cat.scala 30:58] + node _T_349 = cat(_T_348, _T_343) @[Cat.scala 30:58] + node _T_350 = cat(_T_328, _T_327) @[Cat.scala 30:58] + node _T_351 = cat(_T_350, _T_326) @[Cat.scala 30:58] + node _T_352 = cat(_T_331, _T_330) @[Cat.scala 30:58] + node _T_353 = cat(_T_352, _T_329) @[Cat.scala 30:58] + node _T_354 = cat(_T_353, _T_351) @[Cat.scala 30:58] + node _T_355 = cat(_T_334, _T_333) @[Cat.scala 30:58] + node _T_356 = cat(_T_355, _T_332) @[Cat.scala 30:58] + node _T_357 = cat(_T_336, _T_335) @[Cat.scala 30:58] + node _T_358 = cat(_T_338, _T_337) @[Cat.scala 30:58] + node _T_359 = cat(_T_358, _T_357) @[Cat.scala 30:58] + node _T_360 = cat(_T_359, _T_356) @[Cat.scala 30:58] + node _T_361 = cat(_T_360, _T_354) @[Cat.scala 30:58] + node r_addr = cat(_T_361, _T_349) @[Cat.scala 30:58] + node _T_362 = shr(io.in.0.aw.bits.addr, 3) @[SRAM.scala 39:49] + node _T_363 = bits(_T_362, 0, 0) @[SRAM.scala 39:73] + node _T_364 = bits(_T_362, 1, 1) @[SRAM.scala 39:73] + node _T_365 = bits(_T_362, 2, 2) @[SRAM.scala 39:73] + node _T_366 = bits(_T_362, 3, 3) @[SRAM.scala 39:73] + node _T_367 = bits(_T_362, 4, 4) @[SRAM.scala 39:73] + node _T_368 = bits(_T_362, 5, 5) @[SRAM.scala 39:73] + node _T_369 = bits(_T_362, 6, 6) @[SRAM.scala 39:73] + node _T_370 = bits(_T_362, 7, 7) @[SRAM.scala 39:73] + node _T_371 = bits(_T_362, 8, 8) @[SRAM.scala 39:73] + node _T_372 = bits(_T_362, 9, 9) @[SRAM.scala 39:73] + node _T_373 = bits(_T_362, 10, 10) @[SRAM.scala 39:73] + node _T_374 = bits(_T_362, 11, 11) @[SRAM.scala 39:73] + node _T_375 = bits(_T_362, 12, 12) @[SRAM.scala 39:73] + node _T_376 = bits(_T_362, 13, 13) @[SRAM.scala 39:73] + node _T_377 = bits(_T_362, 14, 14) @[SRAM.scala 39:73] + node _T_378 = bits(_T_362, 15, 15) @[SRAM.scala 39:73] + node _T_379 = bits(_T_362, 16, 16) @[SRAM.scala 39:73] + node _T_380 = bits(_T_362, 17, 17) @[SRAM.scala 39:73] + node _T_381 = bits(_T_362, 18, 18) @[SRAM.scala 39:73] + node _T_382 = bits(_T_362, 19, 19) @[SRAM.scala 39:73] + node _T_383 = bits(_T_362, 20, 20) @[SRAM.scala 39:73] + node _T_384 = bits(_T_362, 21, 21) @[SRAM.scala 39:73] + node _T_385 = bits(_T_362, 22, 22) @[SRAM.scala 39:73] + node _T_386 = bits(_T_362, 23, 23) @[SRAM.scala 39:73] + node _T_387 = bits(_T_362, 24, 24) @[SRAM.scala 39:73] + node _T_388 = cat(_T_365, _T_364) @[Cat.scala 30:58] + node _T_389 = cat(_T_388, _T_363) @[Cat.scala 30:58] + node _T_390 = cat(_T_368, _T_367) @[Cat.scala 30:58] + node _T_391 = cat(_T_390, _T_366) @[Cat.scala 30:58] + node _T_392 = cat(_T_391, _T_389) @[Cat.scala 30:58] + node _T_393 = cat(_T_371, _T_370) @[Cat.scala 30:58] + node _T_394 = cat(_T_393, _T_369) @[Cat.scala 30:58] + node _T_395 = cat(_T_374, _T_373) @[Cat.scala 30:58] + node _T_396 = cat(_T_395, _T_372) @[Cat.scala 30:58] + node _T_397 = cat(_T_396, _T_394) @[Cat.scala 30:58] + node _T_398 = cat(_T_397, _T_392) @[Cat.scala 30:58] + node _T_399 = cat(_T_377, _T_376) @[Cat.scala 30:58] + node _T_400 = cat(_T_399, _T_375) @[Cat.scala 30:58] + node _T_401 = cat(_T_380, _T_379) @[Cat.scala 30:58] + node _T_402 = cat(_T_401, _T_378) @[Cat.scala 30:58] + node _T_403 = cat(_T_402, _T_400) @[Cat.scala 30:58] + node _T_404 = cat(_T_383, _T_382) @[Cat.scala 30:58] + node _T_405 = cat(_T_404, _T_381) @[Cat.scala 30:58] + node _T_406 = cat(_T_385, _T_384) @[Cat.scala 30:58] + node _T_407 = cat(_T_387, _T_386) @[Cat.scala 30:58] + node _T_408 = cat(_T_407, _T_406) @[Cat.scala 30:58] + node _T_409 = cat(_T_408, _T_405) @[Cat.scala 30:58] + node _T_410 = cat(_T_409, _T_403) @[Cat.scala 30:58] + node w_addr = cat(_T_410, _T_398) @[Cat.scala 30:58] + node _T_411 = and(io.in.0.w.valid, io.in.0.b.ready) @[SRAM.scala 41:32] + io.in.0.aw.ready <= _T_411 @[SRAM.scala 41:17] + node _T_412 = and(io.in.0.aw.valid, io.in.0.b.ready) @[SRAM.scala 42:32] + io.in.0.w.ready <= _T_412 @[SRAM.scala 42:17] + node _T_413 = and(io.in.0.w.valid, io.in.0.aw.valid) @[SRAM.scala 43:31] + io.in.0.b.valid <= _T_413 @[SRAM.scala 43:17] + io.in.0.b.bits.id <= io.in.0.aw.bits.id @[SRAM.scala 45:20] + io.in.0.b.bits.resp <= UInt<2>("h00") @[SRAM.scala 46:20] + node _T_415 = bits(io.in.0.w.bits.data, 7, 0) @[SRAM.scala 47:62] + node _T_416 = bits(io.in.0.w.bits.data, 15, 8) @[SRAM.scala 47:62] + node _T_417 = bits(io.in.0.w.bits.data, 23, 16) @[SRAM.scala 47:62] + node _T_418 = bits(io.in.0.w.bits.data, 31, 24) @[SRAM.scala 47:62] + node _T_419 = bits(io.in.0.w.bits.data, 39, 32) @[SRAM.scala 47:62] + node _T_420 = bits(io.in.0.w.bits.data, 47, 40) @[SRAM.scala 47:62] + node _T_421 = bits(io.in.0.w.bits.data, 55, 48) @[SRAM.scala 47:62] + node _T_422 = bits(io.in.0.w.bits.data, 63, 56) @[SRAM.scala 47:62] + wire wdata : UInt<8>[8] @[SRAM.scala 47:41] + wdata is invalid @[SRAM.scala 47:41] + wdata[0] <= _T_415 @[SRAM.scala 47:41] + wdata[1] <= _T_416 @[SRAM.scala 47:41] + wdata[2] <= _T_417 @[SRAM.scala 47:41] + wdata[3] <= _T_418 @[SRAM.scala 47:41] + wdata[4] <= _T_419 @[SRAM.scala 47:41] + wdata[5] <= _T_420 @[SRAM.scala 47:41] + wdata[6] <= _T_421 @[SRAM.scala 47:41] + wdata[7] <= _T_422 @[SRAM.scala 47:41] + node _T_435 = and(io.in.0.b.ready, io.in.0.b.valid) @[Decoupled.scala 30:37] + when _T_435 : @[SRAM.scala 48:24] + node _T_436 = bits(io.in.0.w.bits.strb, 0, 0) @[SRAM.scala 49:47] + node _T_437 = bits(io.in.0.w.bits.strb, 1, 1) @[SRAM.scala 49:47] + node _T_438 = bits(io.in.0.w.bits.strb, 2, 2) @[SRAM.scala 49:47] + node _T_439 = bits(io.in.0.w.bits.strb, 3, 3) @[SRAM.scala 49:47] + node _T_440 = bits(io.in.0.w.bits.strb, 4, 4) @[SRAM.scala 49:47] + node _T_441 = bits(io.in.0.w.bits.strb, 5, 5) @[SRAM.scala 49:47] + node _T_442 = bits(io.in.0.w.bits.strb, 6, 6) @[SRAM.scala 49:47] + node _T_443 = bits(io.in.0.w.bits.strb, 7, 7) @[SRAM.scala 49:47] + write mport _T_444 = mem[w_addr], clock + when _T_436 : + _T_444[0] <= wdata[0] skip - count <= UInt<1>("h00") - skip - node T_1902 = eq(UInt<1>("h01"), state) - when T_1902 : - node T_1904 = lt(count, UInt<2>("h02")) - node T_1905 = and(pte_cache_hit, T_1904) - when T_1905 : - io.mem.req.valid <= UInt<1>("h00") - state <= UInt<1>("h01") - node T_1908 = add(count, UInt<1>("h01")) - node T_1909 = tail(T_1908, 1) - count <= T_1909 - r_pte.ppn <= pte_cache_data + when _T_437 : + _T_444[1] <= wdata[1] skip - node T_1911 = eq(T_1905, UInt<1>("h00")) - node T_1912 = and(T_1911, io.mem.req.ready) - when T_1912 : - state <= UInt<2>("h02") + when _T_438 : + _T_444[2] <= wdata[2] skip - skip - node T_1913 = eq(UInt<2>("h02"), state) - when T_1913 : - when io.mem.resp.bits.nack : - state <= UInt<1>("h01") + when _T_439 : + _T_444[3] <= wdata[3] skip - when io.mem.resp.valid : - state <= UInt<3>("h06") - node T_1915 = lt(pte.typ, UInt<2>("h02")) - node T_1916 = and(pte.v, T_1915) - node T_1918 = lt(count, UInt<2>("h02")) - node T_1919 = and(T_1916, T_1918) - when T_1919 : - state <= UInt<1>("h01") - node T_1921 = add(count, UInt<1>("h01")) - node T_1922 = tail(T_1921, 1) - count <= T_1922 - skip - node T_1924 = geq(pte.typ, UInt<2>("h02")) - node T_1925 = and(pte.v, T_1924) - when T_1925 : - node T_1926 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) - state <= T_1926 - skip + when _T_440 : + _T_444[4] <= wdata[4] skip - skip - node T_1927 = eq(UInt<2>("h03"), state) - when T_1927 : - when io.mem.req.ready : - state <= UInt<3>("h04") + when _T_441 : + _T_444[5] <= wdata[5] skip - skip - node T_1928 = eq(UInt<3>("h04"), state) - when T_1928 : - when io.mem.resp.bits.nack : - state <= UInt<2>("h03") + when _T_442 : + _T_444[6] <= wdata[6] skip - when io.mem.resp.valid : - state <= UInt<1>("h01") + when _T_443 : + _T_444[7] <= wdata[7] skip - skip - node T_1929 = eq(UInt<3>("h05"), state) - when T_1929 : - state <= UInt<1>("h00") - skip - node T_1930 = eq(UInt<3>("h06"), state) - when T_1930 : - state <= UInt<1>("h00") - skip + skip @[SRAM.scala 48:24] + reg r_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg r_id : UInt, clock @[SRAM.scala 53:21] + node _T_466 = and(io.in.0.r.ready, io.in.0.r.valid) @[Decoupled.scala 30:37] + when _T_466 : @[SRAM.scala 55:25] + r_full <= UInt<1>("h00") @[SRAM.scala 55:34] + skip @[SRAM.scala 55:25] + node _T_468 = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + when _T_468 : @[SRAM.scala 56:25] + r_full <= UInt<1>("h01") @[SRAM.scala 56:34] + skip @[SRAM.scala 56:25] + io.in.0.r.valid <= r_full @[SRAM.scala 58:17] + node _T_471 = eq(r_full, UInt<1>("h00")) @[SRAM.scala 59:34] + node _T_472 = or(io.in.0.r.ready, _T_471) @[SRAM.scala 59:31] + io.in.0.ar.ready <= _T_472 @[SRAM.scala 59:17] + node _T_473 = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + when _T_473 : @[SRAM.scala 61:25] + r_id <= io.in.0.ar.bits.id @[SRAM.scala 62:12] + skip @[SRAM.scala 61:25] + node ren = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + wire _T_475 : UInt + _T_475 is invalid + when ren : + _T_475 <= r_addr + node _T_477 = or(_T_475, UInt<25>("h00")) + node _T_478 = bits(_T_477, 24, 0) + read mport _T_479 = mem[_T_478], clock + skip + reg _T_499 : UInt<1>, clock @[Reg.scala 14:44] + _T_499 <= ren @[Reg.scala 14:44] + reg _T_529 : UInt<8>[8], clock @[Reg.scala 34:16] + when _T_499 : @[Reg.scala 35:19] + _T_529 <- _T_479 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node rdata = mux(_T_499, _T_479, _T_529) @[Package.scala 27:42] + io.in.0.r.bits.id <= r_id @[SRAM.scala 68:20] + io.in.0.r.bits.resp <= UInt<2>("h00") @[SRAM.scala 69:20] + node _T_596 = cat(rdata[1], rdata[0]) @[Cat.scala 30:58] + node _T_597 = cat(rdata[3], rdata[2]) @[Cat.scala 30:58] + node _T_598 = cat(_T_597, _T_596) @[Cat.scala 30:58] + node _T_599 = cat(rdata[5], rdata[4]) @[Cat.scala 30:58] + node _T_600 = cat(rdata[7], rdata[6]) @[Cat.scala 30:58] + node _T_601 = cat(_T_600, _T_599) @[Cat.scala 30:58] + node _T_602 = cat(_T_601, _T_598) @[Cat.scala 30:58] + io.in.0.r.bits.data <= _T_602 @[SRAM.scala 70:20] + io.in.0.r.bits.last <= UInt<1>("h01") @[SRAM.scala 71:20] - module HellaCacheArbiter : - input clk : Clock + module Queue_43 : + input clock : Clock input reset : UInt<1> - output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} - - io is invalid - reg T_5286 : UInt<1>, clk - T_5286 <= io.requestor[0].req.valid - reg T_5287 : UInt<1>, clk - T_5287 <= io.requestor[1].req.valid - node T_5288 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) - io.mem.req.valid <= T_5288 - io.requestor[0].req.ready <= io.mem.req.ready - node T_5290 = eq(io.requestor[0].req.valid, UInt<1>("h00")) - node T_5291 = and(io.requestor[0].req.ready, T_5290) - io.requestor[1].req.ready <= T_5291 - io.mem.req.bits <- io.requestor[1].req.bits - node T_5293 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01")) - io.mem.req.bits.tag <= T_5293 - when io.requestor[0].req.valid : - io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd - io.mem.req.bits.typ <= io.requestor[0].req.bits.typ - io.mem.req.bits.addr <= io.requestor[0].req.bits.addr - io.mem.req.bits.phys <= io.requestor[0].req.bits.phys - node T_5295 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00")) - io.mem.req.bits.tag <= T_5295 - skip - when T_5286 : - io.mem.req.bits.kill <= io.requestor[0].req.bits.kill - io.mem.req.bits.data <= io.requestor[0].req.bits.data - skip - node T_5296 = bits(io.mem.resp.bits.tag, 0, 0) - node T_5298 = eq(T_5296, UInt<1>("h00")) - node T_5299 = and(io.mem.resp.valid, T_5298) - io.requestor[0].resp.valid <= T_5299 - io.requestor[0].xcpt <- io.mem.xcpt - io.requestor[0].ordered <= io.mem.ordered - io.requestor[0].resp.bits <- io.mem.resp.bits - node T_5300 = shr(io.mem.resp.bits.tag, 1) - io.requestor[0].resp.bits.tag <= T_5300 - node T_5301 = and(io.mem.resp.bits.nack, T_5298) - io.requestor[0].resp.bits.nack <= T_5301 - node T_5302 = and(io.mem.resp.bits.replay, T_5298) - io.requestor[0].resp.bits.replay <= T_5302 - node T_5303 = bits(io.mem.replay_next.bits, 0, 0) - node T_5305 = eq(T_5303, UInt<1>("h00")) - node T_5306 = and(io.mem.replay_next.valid, T_5305) - io.requestor[0].replay_next.valid <= T_5306 - node T_5307 = shr(io.mem.replay_next.bits, 1) - io.requestor[0].replay_next.bits <= T_5307 - node T_5308 = bits(io.mem.resp.bits.tag, 0, 0) - node T_5310 = eq(T_5308, UInt<1>("h01")) - node T_5311 = and(io.mem.resp.valid, T_5310) - io.requestor[1].resp.valid <= T_5311 - io.requestor[1].xcpt <- io.mem.xcpt - io.requestor[1].ordered <= io.mem.ordered - io.requestor[1].resp.bits <- io.mem.resp.bits - node T_5312 = shr(io.mem.resp.bits.tag, 1) - io.requestor[1].resp.bits.tag <= T_5312 - node T_5313 = and(io.mem.resp.bits.nack, T_5310) - io.requestor[1].resp.bits.nack <= T_5313 - node T_5314 = and(io.mem.resp.bits.replay, T_5310) - io.requestor[1].resp.bits.replay <= T_5314 - node T_5315 = bits(io.mem.replay_next.bits, 0, 0) - node T_5317 = eq(T_5315, UInt<1>("h01")) - node T_5318 = and(io.mem.replay_next.valid, T_5317) - io.requestor[1].replay_next.valid <= T_5318 - node T_5319 = shr(io.mem.replay_next.bits, 1) - io.requestor[1].replay_next.bits <= T_5319 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] - module FPUDecoder : - input clk : Clock + module Queue_44 : + input clock : Clock input reset : UInt<1> - output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} - - io is invalid - node T_42 = and(io.inst, UInt<32>("h04")) - node T_44 = eq(T_42, UInt<32>("h04")) - node T_46 = and(io.inst, UInt<32>("h08000010")) - node T_48 = eq(T_46, UInt<32>("h08000010")) - node T_50 = or(UInt<1>("h00"), T_44) - node T_51 = or(T_50, T_48) - node T_53 = and(io.inst, UInt<32>("h08")) - node T_55 = eq(T_53, UInt<32>("h08")) - node T_57 = and(io.inst, UInt<32>("h010000010")) - node T_59 = eq(T_57, UInt<32>("h010000010")) - node T_61 = or(UInt<1>("h00"), T_55) - node T_62 = or(T_61, T_59) - node T_64 = and(io.inst, UInt<32>("h040")) - node T_66 = eq(T_64, UInt<32>("h00")) - node T_68 = and(io.inst, UInt<32>("h020000000")) - node T_70 = eq(T_68, UInt<32>("h020000000")) - node T_72 = or(UInt<1>("h00"), T_66) - node T_73 = or(T_72, T_70) - node T_75 = and(io.inst, UInt<32>("h040000000")) - node T_77 = eq(T_75, UInt<32>("h040000000")) - node T_79 = or(UInt<1>("h00"), T_66) - node T_80 = or(T_79, T_77) - node T_82 = and(io.inst, UInt<32>("h010")) - node T_84 = eq(T_82, UInt<32>("h00")) - node T_86 = or(UInt<1>("h00"), T_84) - node T_87 = cat(T_62, T_51) - node T_88 = cat(T_73, T_87) - node T_89 = cat(T_80, T_88) - node T_90 = cat(T_86, T_89) - node T_92 = or(UInt<1>("h00"), T_66) - node T_94 = and(io.inst, UInt<32>("h080000020")) - node T_96 = eq(T_94, UInt<32>("h00")) - node T_98 = and(io.inst, UInt<32>("h030")) - node T_100 = eq(T_98, UInt<32>("h00")) - node T_102 = and(io.inst, UInt<32>("h010000020")) - node T_104 = eq(T_102, UInt<32>("h010000000")) - node T_106 = or(UInt<1>("h00"), T_96) - node T_107 = or(T_106, T_100) - node T_108 = or(T_107, T_104) - node T_110 = and(io.inst, UInt<32>("h080000004")) - node T_112 = eq(T_110, UInt<32>("h00")) - node T_114 = and(io.inst, UInt<32>("h010000004")) - node T_116 = eq(T_114, UInt<32>("h00")) - node T_118 = and(io.inst, UInt<32>("h050")) - node T_120 = eq(T_118, UInt<32>("h040")) - node T_122 = or(UInt<1>("h00"), T_112) - node T_123 = or(T_122, T_116) - node T_124 = or(T_123, T_120) - node T_126 = and(io.inst, UInt<32>("h040000004")) - node T_128 = eq(T_126, UInt<32>("h00")) - node T_130 = and(io.inst, UInt<32>("h020")) - node T_132 = eq(T_130, UInt<32>("h020")) - node T_134 = or(UInt<1>("h00"), T_128) - node T_135 = or(T_134, T_132) - node T_136 = or(T_135, T_120) - node T_138 = or(UInt<1>("h00"), T_120) - node T_140 = and(io.inst, UInt<32>("h050000010")) - node T_142 = eq(T_140, UInt<32>("h050000010")) - node T_144 = or(UInt<1>("h00"), T_66) - node T_145 = or(T_144, T_142) - node T_147 = and(io.inst, UInt<32>("h030000010")) - node T_149 = eq(T_147, UInt<32>("h010")) - node T_151 = or(UInt<1>("h00"), T_149) - node T_153 = and(io.inst, UInt<32>("h01040")) - node T_155 = eq(T_153, UInt<32>("h00")) - node T_157 = and(io.inst, UInt<32>("h02000040")) - node T_159 = eq(T_157, UInt<32>("h040")) - node T_161 = or(UInt<1>("h00"), T_155) - node T_162 = or(T_161, T_159) - node T_164 = and(io.inst, UInt<32>("h090000010")) - node T_166 = eq(T_164, UInt<32>("h090000010")) - node T_168 = or(UInt<1>("h00"), T_166) - node T_170 = and(io.inst, UInt<32>("h090000010")) - node T_172 = eq(T_170, UInt<32>("h080000010")) - node T_174 = or(UInt<1>("h00"), T_132) - node T_175 = or(T_174, T_172) - node T_177 = and(io.inst, UInt<32>("h0a0000010")) - node T_179 = eq(T_177, UInt<32>("h020000010")) - node T_181 = and(io.inst, UInt<32>("h0d0000010")) - node T_183 = eq(T_181, UInt<32>("h040000010")) - node T_185 = or(UInt<1>("h00"), T_179) - node T_186 = or(T_185, T_183) - node T_188 = and(io.inst, UInt<32>("h070000004")) - node T_190 = eq(T_188, UInt<32>("h00")) - node T_192 = and(io.inst, UInt<32>("h068000004")) - node T_194 = eq(T_192, UInt<32>("h00")) - node T_196 = or(UInt<1>("h00"), T_190) - node T_197 = or(T_196, T_194) - node T_198 = or(T_197, T_120) - node T_200 = and(io.inst, UInt<32>("h058000010")) - node T_202 = eq(T_200, UInt<32>("h018000010")) - node T_204 = or(UInt<1>("h00"), T_202) - node T_206 = and(io.inst, UInt<32>("h0d0000010")) - node T_208 = eq(T_206, UInt<32>("h050000010")) - node T_210 = or(UInt<1>("h00"), T_208) - node T_212 = and(io.inst, UInt<32>("h020000004")) - node T_214 = eq(T_212, UInt<32>("h00")) - node T_216 = and(io.inst, UInt<32>("h040002000")) - node T_218 = eq(T_216, UInt<32>("h040000000")) - node T_220 = or(UInt<1>("h00"), T_214) - node T_221 = or(T_220, T_120) - node T_222 = or(T_221, T_218) - node T_224 = and(io.inst, UInt<32>("h08002000")) - node T_226 = eq(T_224, UInt<32>("h08000000")) - node T_228 = and(io.inst, UInt<32>("h0c0000004")) - node T_230 = eq(T_228, UInt<32>("h080000000")) - node T_232 = or(UInt<1>("h00"), T_214) - node T_233 = or(T_232, T_120) - node T_234 = or(T_233, T_226) - node T_235 = or(T_234, T_230) - io.sigs.cmd <= T_90 - io.sigs.ldst <= T_92 - io.sigs.wen <= T_108 - io.sigs.ren1 <= T_124 - io.sigs.ren2 <= T_136 - io.sigs.ren3 <= T_138 - io.sigs.swap12 <= T_145 - io.sigs.swap23 <= T_151 - io.sigs.single <= T_162 - io.sigs.fromint <= T_168 - io.sigs.toint <= T_175 - io.sigs.fastpipe <= T_186 - io.sigs.fma <= T_198 - io.sigs.div <= T_204 - io.sigs.sqrt <= T_210 - io.sigs.round <= T_222 - io.sigs.wflags <= T_235 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} - module MulAddRecFN_preMul : - input clk : Clock + io is invalid + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] + + module Queue_45 : + input clock : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} io is invalid - node signA = bits(io.a, 32, 32) - node expA = bits(io.a, 31, 23) - node fractA = bits(io.a, 22, 0) - node T_50 = bits(expA, 8, 6) - node isZeroA = eq(T_50, UInt<1>("h00")) - node T_54 = eq(isZeroA, UInt<1>("h00")) - node sigA = cat(T_54, fractA) - node signB = bits(io.b, 32, 32) - node expB = bits(io.b, 31, 23) - node fractB = bits(io.b, 22, 0) - node T_59 = bits(expB, 8, 6) - node isZeroB = eq(T_59, UInt<1>("h00")) - node T_63 = eq(isZeroB, UInt<1>("h00")) - node sigB = cat(T_63, fractB) - node T_65 = bits(io.c, 32, 32) - node T_66 = bits(io.op, 0, 0) - node opSignC = xor(T_65, T_66) - node expC = bits(io.c, 31, 23) - node fractC = bits(io.c, 22, 0) - node T_70 = bits(expC, 8, 6) - node isZeroC = eq(T_70, UInt<1>("h00")) - node T_74 = eq(isZeroC, UInt<1>("h00")) - node sigC = cat(T_74, fractC) - node T_76 = xor(signA, signB) - node T_77 = bits(io.op, 1, 1) - node signProd = xor(T_76, T_77) - node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bits(expB, 8, 8) - node T_82 = eq(T_80, UInt<1>("h00")) - node T_84 = sub(UInt<3>("h00"), T_82) - node T_85 = tail(T_84, 1) - node T_86 = bits(expB, 7, 0) - node T_87 = cat(T_85, T_86) - node T_88 = add(expA, T_87) - node T_89 = tail(T_88, 1) - node T_91 = add(T_89, UInt<5>("h01b")) - node sExpAlignedProd = tail(T_91, 1) - node doSubMags = xor(signProd, opSignC) - node T_94 = sub(sExpAlignedProd, expC) - node sNatCAlignDist = tail(T_94, 1) - node T_96 = bits(sNatCAlignDist, 10, 10) - node CAlignDist_floor = or(isZeroProd, T_96) - node T_98 = bits(sNatCAlignDist, 9, 0) - node T_100 = eq(T_98, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_100) - node T_103 = eq(isZeroC, UInt<1>("h00")) - node T_104 = bits(sNatCAlignDist, 9, 0) - node T_106 = lt(T_104, UInt<5>("h019")) - node T_107 = or(CAlignDist_floor, T_106) - node isCDominant = and(T_103, T_107) - node T_110 = bits(sNatCAlignDist, 9, 0) - node T_112 = lt(T_110, UInt<7>("h04a")) - node T_113 = bits(sNatCAlignDist, 6, 0) - node T_115 = mux(T_112, T_113, UInt<7>("h04a")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_119 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) - node T_120 = bits(T_119, 77, 54) - node T_121 = bits(T_120, 15, 0) - node T_124 = shl(UInt<8>("h0ff"), 8) - node T_125 = xor(UInt<16>("h0ffff"), T_124) - node T_126 = shr(T_121, 8) - node T_127 = and(T_126, T_125) - node T_128 = bits(T_121, 7, 0) - node T_129 = shl(T_128, 8) - node T_130 = not(T_125) - node T_131 = and(T_129, T_130) - node T_132 = or(T_127, T_131) - node T_133 = bits(T_125, 11, 0) - node T_134 = shl(T_133, 4) - node T_135 = xor(T_125, T_134) - node T_136 = shr(T_132, 4) - node T_137 = and(T_136, T_135) - node T_138 = bits(T_132, 11, 0) - node T_139 = shl(T_138, 4) - node T_140 = not(T_135) - node T_141 = and(T_139, T_140) - node T_142 = or(T_137, T_141) - node T_143 = bits(T_135, 13, 0) - node T_144 = shl(T_143, 2) - node T_145 = xor(T_135, T_144) - node T_146 = shr(T_142, 2) - node T_147 = and(T_146, T_145) - node T_148 = bits(T_142, 13, 0) - node T_149 = shl(T_148, 2) - node T_150 = not(T_145) - node T_151 = and(T_149, T_150) - node T_152 = or(T_147, T_151) - node T_153 = bits(T_145, 14, 0) - node T_154 = shl(T_153, 1) - node T_155 = xor(T_145, T_154) - node T_156 = shr(T_152, 1) - node T_157 = and(T_156, T_155) - node T_158 = bits(T_152, 14, 0) - node T_159 = shl(T_158, 1) - node T_160 = not(T_155) - node T_161 = and(T_159, T_160) - node T_162 = or(T_157, T_161) - node T_163 = bits(T_120, 23, 16) - node T_166 = shl(UInt<4>("h0f"), 4) - node T_167 = xor(UInt<8>("h0ff"), T_166) - node T_168 = shr(T_163, 4) - node T_169 = and(T_168, T_167) - node T_170 = bits(T_163, 3, 0) - node T_171 = shl(T_170, 4) - node T_172 = not(T_167) - node T_173 = and(T_171, T_172) - node T_174 = or(T_169, T_173) - node T_175 = bits(T_167, 5, 0) - node T_176 = shl(T_175, 2) - node T_177 = xor(T_167, T_176) - node T_178 = shr(T_174, 2) - node T_179 = and(T_178, T_177) - node T_180 = bits(T_174, 5, 0) - node T_181 = shl(T_180, 2) - node T_182 = not(T_177) - node T_183 = and(T_181, T_182) - node T_184 = or(T_179, T_183) - node T_185 = bits(T_177, 6, 0) - node T_186 = shl(T_185, 1) - node T_187 = xor(T_177, T_186) - node T_188 = shr(T_184, 1) - node T_189 = and(T_188, T_187) - node T_190 = bits(T_184, 6, 0) - node T_191 = shl(T_190, 1) - node T_192 = not(T_187) - node T_193 = and(T_191, T_192) - node T_194 = or(T_189, T_193) - node CExtraMask = cat(T_162, T_194) - node T_196 = not(sigC) - node negSigC = mux(doSubMags, T_196, sigC) - node T_199 = sub(UInt<50>("h00"), doSubMags) - node T_200 = tail(T_199, 1) - node T_201 = cat(negSigC, T_200) - node T_202 = cat(doSubMags, T_201) - node T_203 = asSInt(T_202) - node T_204 = dshr(T_203, CAlignDist) - node T_205 = and(sigC, CExtraMask) - node T_207 = neq(T_205, UInt<1>("h00")) - node T_208 = xor(T_207, doSubMags) - node T_209 = asUInt(T_204) - node T_210 = cat(T_209, T_208) - node alignedNegSigC = bits(T_210, 74, 0) - io.mulAddA <= sigA - io.mulAddB <= sigB - node T_212 = bits(alignedNegSigC, 48, 1) - io.mulAddC <= T_212 - node T_213 = bits(expA, 8, 6) - io.toPostMul.highExpA <= T_213 - node T_214 = bits(fractA, 22, 22) - io.toPostMul.isNaN_isQuietNaNA <= T_214 - node T_215 = bits(expB, 8, 6) - io.toPostMul.highExpB <= T_215 - node T_216 = bits(fractB, 22, 22) - io.toPostMul.isNaN_isQuietNaNB <= T_216 - io.toPostMul.signProd <= signProd - io.toPostMul.isZeroProd <= isZeroProd - io.toPostMul.opSignC <= opSignC - node T_217 = bits(expC, 8, 6) - io.toPostMul.highExpC <= T_217 - node T_218 = bits(fractC, 22, 22) - io.toPostMul.isNaN_isQuietNaNC <= T_218 - io.toPostMul.isCDominant <= isCDominant - io.toPostMul.CAlignDist_0 <= CAlignDist_0 - io.toPostMul.CAlignDist <= CAlignDist - node T_219 = bits(alignedNegSigC, 0, 0) - io.toPostMul.bit0AlignedNegSigC <= T_219 - node T_220 = bits(alignedNegSigC, 74, 49) - io.toPostMul.highAlignedNegSigC <= T_220 - io.toPostMul.sExpSum <= sExpSum - io.toPostMul.roundingMode <= io.roundingMode + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] - module MulAddRecFN_postMul : - input clk : Clock + module Queue_46 : + input clock : Clock input reset : UInt<1> - output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<1>} io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) - node T_44 = bits(io.fromPreMul.highExpA, 2, 1) - node isSpecialA = eq(T_44, UInt<2>("h03")) - node T_47 = bits(io.fromPreMul.highExpA, 0, 0) - node T_49 = eq(T_47, UInt<1>("h00")) - node isInfA = and(isSpecialA, T_49) - node T_51 = bits(io.fromPreMul.highExpA, 0, 0) - node isNaNA = and(isSpecialA, T_51) - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) - node isSigNaNA = and(isNaNA, T_54) - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) - node T_58 = bits(io.fromPreMul.highExpB, 2, 1) - node isSpecialB = eq(T_58, UInt<2>("h03")) - node T_61 = bits(io.fromPreMul.highExpB, 0, 0) - node T_63 = eq(T_61, UInt<1>("h00")) - node isInfB = and(isSpecialB, T_63) - node T_65 = bits(io.fromPreMul.highExpB, 0, 0) - node isNaNB = and(isSpecialB, T_65) - node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) - node isSigNaNB = and(isNaNB, T_68) - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) - node T_72 = bits(io.fromPreMul.highExpC, 2, 1) - node isSpecialC = eq(T_72, UInt<2>("h03")) - node T_75 = bits(io.fromPreMul.highExpC, 0, 0) - node T_77 = eq(T_75, UInt<1>("h00")) - node isInfC = and(isSpecialC, T_77) - node T_79 = bits(io.fromPreMul.highExpC, 0, 0) - node isNaNC = and(isSpecialC, T_79) - node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) - node isSigNaNC = and(isNaNC, T_82) - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_96 = bits(io.mulAddResult, 48, 48) - node T_98 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) - node T_99 = tail(T_98, 1) - node T_100 = mux(T_96, T_99, io.fromPreMul.highAlignedNegSigC) - node T_101 = bits(io.mulAddResult, 47, 0) - node T_102 = cat(T_101, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_100, T_102) - node T_105 = bits(sigSum, 50, 1) - node T_106 = xor(UInt<50>("h00"), T_105) - node T_107 = or(UInt<50>("h00"), T_105) - node T_108 = shl(T_107, 1) - node T_109 = xor(T_106, T_108) - node T_111 = bits(T_109, 49, 0) - node T_112 = bits(T_111, 49, 49) - node T_114 = bits(T_111, 48, 48) - node T_116 = bits(T_111, 47, 47) - node T_118 = bits(T_111, 46, 46) - node T_120 = bits(T_111, 45, 45) - node T_122 = bits(T_111, 44, 44) - node T_124 = bits(T_111, 43, 43) - node T_126 = bits(T_111, 42, 42) - node T_128 = bits(T_111, 41, 41) - node T_130 = bits(T_111, 40, 40) - node T_132 = bits(T_111, 39, 39) - node T_134 = bits(T_111, 38, 38) - node T_136 = bits(T_111, 37, 37) - node T_138 = bits(T_111, 36, 36) - node T_140 = bits(T_111, 35, 35) - node T_142 = bits(T_111, 34, 34) - node T_144 = bits(T_111, 33, 33) - node T_146 = bits(T_111, 32, 32) - node T_148 = bits(T_111, 31, 31) - node T_150 = bits(T_111, 30, 30) - node T_152 = bits(T_111, 29, 29) - node T_154 = bits(T_111, 28, 28) - node T_156 = bits(T_111, 27, 27) - node T_158 = bits(T_111, 26, 26) - node T_160 = bits(T_111, 25, 25) - node T_162 = bits(T_111, 24, 24) - node T_164 = bits(T_111, 23, 23) - node T_166 = bits(T_111, 22, 22) - node T_168 = bits(T_111, 21, 21) - node T_170 = bits(T_111, 20, 20) - node T_172 = bits(T_111, 19, 19) - node T_174 = bits(T_111, 18, 18) - node T_176 = bits(T_111, 17, 17) - node T_178 = bits(T_111, 16, 16) - node T_180 = bits(T_111, 15, 15) - node T_182 = bits(T_111, 14, 14) - node T_184 = bits(T_111, 13, 13) - node T_186 = bits(T_111, 12, 12) - node T_188 = bits(T_111, 11, 11) - node T_190 = bits(T_111, 10, 10) - node T_192 = bits(T_111, 9, 9) - node T_194 = bits(T_111, 8, 8) - node T_196 = bits(T_111, 7, 7) - node T_198 = bits(T_111, 6, 6) - node T_200 = bits(T_111, 5, 5) - node T_202 = bits(T_111, 4, 4) - node T_204 = bits(T_111, 3, 3) - node T_206 = bits(T_111, 2, 2) - node T_208 = bits(T_111, 1, 1) - node T_209 = shl(T_208, 0) - node T_210 = mux(T_206, UInt<2>("h02"), T_209) - node T_211 = mux(T_204, UInt<2>("h03"), T_210) - node T_212 = mux(T_202, UInt<3>("h04"), T_211) - node T_213 = mux(T_200, UInt<3>("h05"), T_212) - node T_214 = mux(T_198, UInt<3>("h06"), T_213) - node T_215 = mux(T_196, UInt<3>("h07"), T_214) - node T_216 = mux(T_194, UInt<4>("h08"), T_215) - node T_217 = mux(T_192, UInt<4>("h09"), T_216) - node T_218 = mux(T_190, UInt<4>("h0a"), T_217) - node T_219 = mux(T_188, UInt<4>("h0b"), T_218) - node T_220 = mux(T_186, UInt<4>("h0c"), T_219) - node T_221 = mux(T_184, UInt<4>("h0d"), T_220) - node T_222 = mux(T_182, UInt<4>("h0e"), T_221) - node T_223 = mux(T_180, UInt<4>("h0f"), T_222) - node T_224 = mux(T_178, UInt<5>("h010"), T_223) - node T_225 = mux(T_176, UInt<5>("h011"), T_224) - node T_226 = mux(T_174, UInt<5>("h012"), T_225) - node T_227 = mux(T_172, UInt<5>("h013"), T_226) - node T_228 = mux(T_170, UInt<5>("h014"), T_227) - node T_229 = mux(T_168, UInt<5>("h015"), T_228) - node T_230 = mux(T_166, UInt<5>("h016"), T_229) - node T_231 = mux(T_164, UInt<5>("h017"), T_230) - node T_232 = mux(T_162, UInt<5>("h018"), T_231) - node T_233 = mux(T_160, UInt<5>("h019"), T_232) - node T_234 = mux(T_158, UInt<5>("h01a"), T_233) - node T_235 = mux(T_156, UInt<5>("h01b"), T_234) - node T_236 = mux(T_154, UInt<5>("h01c"), T_235) - node T_237 = mux(T_152, UInt<5>("h01d"), T_236) - node T_238 = mux(T_150, UInt<5>("h01e"), T_237) - node T_239 = mux(T_148, UInt<5>("h01f"), T_238) - node T_240 = mux(T_146, UInt<6>("h020"), T_239) - node T_241 = mux(T_144, UInt<6>("h021"), T_240) - node T_242 = mux(T_142, UInt<6>("h022"), T_241) - node T_243 = mux(T_140, UInt<6>("h023"), T_242) - node T_244 = mux(T_138, UInt<6>("h024"), T_243) - node T_245 = mux(T_136, UInt<6>("h025"), T_244) - node T_246 = mux(T_134, UInt<6>("h026"), T_245) - node T_247 = mux(T_132, UInt<6>("h027"), T_246) - node T_248 = mux(T_130, UInt<6>("h028"), T_247) - node T_249 = mux(T_128, UInt<6>("h029"), T_248) - node T_250 = mux(T_126, UInt<6>("h02a"), T_249) - node T_251 = mux(T_124, UInt<6>("h02b"), T_250) - node T_252 = mux(T_122, UInt<6>("h02c"), T_251) - node T_253 = mux(T_120, UInt<6>("h02d"), T_252) - node T_254 = mux(T_118, UInt<6>("h02e"), T_253) - node T_255 = mux(T_116, UInt<6>("h02f"), T_254) - node T_256 = mux(T_114, UInt<6>("h030"), T_255) - node T_257 = mux(T_112, UInt<6>("h031"), T_256) - node T_258 = sub(UInt<7>("h049"), T_257) - node estNormPos_dist = tail(T_258, 1) - node T_260 = bits(sigSum, 33, 18) - node T_262 = neq(T_260, UInt<1>("h00")) - node T_263 = bits(sigSum, 17, 0) - node T_265 = neq(T_263, UInt<1>("h00")) - node firstReduceSigSum = cat(T_262, T_265) - node notSigSum = not(sigSum) - node T_268 = bits(notSigSum, 33, 18) - node T_270 = neq(T_268, UInt<1>("h00")) - node T_271 = bits(notSigSum, 17, 0) - node T_273 = neq(T_271, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_270, T_273) - node T_275 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_277 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) - node T_278 = tail(T_277, 1) - node T_279 = bits(T_278, 4, 0) - node CDom_estNormDist = mux(T_275, io.fromPreMul.CAlignDist, T_279) - node T_281 = not(doSubMags) - node T_282 = bits(CDom_estNormDist, 4, 4) - node T_283 = not(T_282) - node T_284 = and(T_281, T_283) - node T_285 = asSInt(T_284) - node T_286 = bits(sigSum, 74, 34) - node T_288 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_289 = cat(T_286, T_288) - node T_290 = asSInt(T_289) - node T_291 = and(T_285, T_290) - node T_292 = asSInt(T_291) - node T_293 = not(doSubMags) - node T_294 = bits(CDom_estNormDist, 4, 4) - node T_295 = and(T_293, T_294) - node T_296 = asSInt(T_295) - node T_297 = bits(sigSum, 58, 18) - node T_298 = bits(firstReduceSigSum, 0, 0) - node T_299 = cat(T_297, T_298) - node T_300 = asSInt(T_299) - node T_301 = and(T_296, T_300) - node T_302 = asSInt(T_301) - node T_303 = or(T_292, T_302) - node T_304 = asSInt(T_303) - node T_305 = bits(CDom_estNormDist, 4, 4) - node T_306 = not(T_305) - node T_307 = and(doSubMags, T_306) - node T_308 = asSInt(T_307) - node T_309 = bits(notSigSum, 74, 34) - node T_311 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_312 = cat(T_309, T_311) - node T_313 = asSInt(T_312) - node T_314 = and(T_308, T_313) - node T_315 = asSInt(T_314) - node T_316 = or(T_304, T_315) - node T_317 = asSInt(T_316) - node T_318 = bits(CDom_estNormDist, 4, 4) - node T_319 = and(doSubMags, T_318) - node T_320 = asSInt(T_319) - node T_321 = bits(notSigSum, 58, 18) - node T_322 = bits(firstReduceNotSigSum, 0, 0) - node T_323 = cat(T_321, T_322) - node T_324 = asSInt(T_323) - node T_325 = and(T_320, T_324) - node T_326 = asSInt(T_325) - node T_327 = or(T_317, T_326) - node T_328 = asSInt(T_327) - node CDom_firstNormAbsSigSum = asUInt(T_328) - node T_330 = bits(sigSum, 50, 18) - node T_331 = bits(firstReduceNotSigSum, 0, 0) - node T_332 = not(T_331) - node T_333 = bits(firstReduceSigSum, 0, 0) - node T_334 = mux(doSubMags, T_332, T_333) - node T_335 = cat(T_330, T_334) - node T_336 = bits(sigSum, 42, 1) - node T_337 = bits(estNormPos_dist, 5, 5) - node T_338 = bits(estNormPos_dist, 4, 4) - node T_339 = bits(sigSum, 26, 1) - node T_341 = sub(UInt<16>("h00"), doSubMags) - node T_342 = tail(T_341, 1) - node T_343 = cat(T_339, T_342) - node T_344 = mux(T_338, T_343, T_336) - node T_345 = bits(estNormPos_dist, 4, 4) - node T_346 = bits(sigSum, 10, 1) - node T_348 = sub(UInt<32>("h00"), doSubMags) - node T_349 = tail(T_348, 1) - node T_350 = cat(T_346, T_349) - node T_351 = mux(T_345, T_335, T_350) - node notCDom_pos_firstNormAbsSigSum = mux(T_337, T_344, T_351) - node T_353 = bits(notSigSum, 49, 18) - node T_354 = bits(firstReduceNotSigSum, 0, 0) - node T_355 = cat(T_353, T_354) - node T_356 = bits(notSigSum, 42, 1) - node T_357 = bits(estNormPos_dist, 5, 5) - node T_358 = bits(estNormPos_dist, 4, 4) - node T_359 = bits(notSigSum, 27, 1) - node T_361 = dshl(T_359, UInt<5>("h010")) - node T_362 = mux(T_358, T_361, T_356) - node T_363 = bits(estNormPos_dist, 4, 4) - node T_364 = bits(notSigSum, 11, 1) - node T_366 = dshl(T_364, UInt<6>("h020")) - node T_367 = mux(T_363, T_355, T_366) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_357, T_362, T_367) - node notCDom_signSigSum = bits(sigSum, 51, 51) - node T_370 = not(isZeroC) - node T_371 = and(doSubMags, T_370) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_371, notCDom_signSigSum) - node T_373 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_373) - node T_375 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_376 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_375, T_376) - node T_378 = not(io.fromPreMul.isCDominant) - node T_379 = not(notCDom_signSigSum) - node T_380 = and(T_378, T_379) - node doIncrSig = and(T_380, doSubMags) - node estNormDist_5 = bits(estNormDist, 3, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_385 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) - node T_386 = bits(T_385, 15, 1) - node T_387 = bits(T_386, 7, 0) - node T_390 = shl(UInt<4>("h0f"), 4) - node T_391 = xor(UInt<8>("h0ff"), T_390) - node T_392 = shr(T_387, 4) - node T_393 = and(T_392, T_391) - node T_394 = bits(T_387, 3, 0) - node T_395 = shl(T_394, 4) - node T_396 = not(T_391) - node T_397 = and(T_395, T_396) - node T_398 = or(T_393, T_397) - node T_399 = bits(T_391, 5, 0) - node T_400 = shl(T_399, 2) - node T_401 = xor(T_391, T_400) - node T_402 = shr(T_398, 2) - node T_403 = and(T_402, T_401) - node T_404 = bits(T_398, 5, 0) - node T_405 = shl(T_404, 2) - node T_406 = not(T_401) - node T_407 = and(T_405, T_406) - node T_408 = or(T_403, T_407) - node T_409 = bits(T_401, 6, 0) - node T_410 = shl(T_409, 1) - node T_411 = xor(T_401, T_410) - node T_412 = shr(T_408, 1) - node T_413 = and(T_412, T_411) - node T_414 = bits(T_408, 6, 0) - node T_415 = shl(T_414, 1) - node T_416 = not(T_411) - node T_417 = and(T_415, T_416) - node T_418 = or(T_413, T_417) - node T_419 = bits(T_386, 14, 8) - node T_420 = bits(T_419, 3, 0) - node T_421 = bits(T_420, 1, 0) - node T_422 = bits(T_421, 0, 0) - node T_423 = bits(T_421, 1, 1) - node T_424 = cat(T_422, T_423) - node T_425 = bits(T_420, 3, 2) - node T_426 = bits(T_425, 0, 0) - node T_427 = bits(T_425, 1, 1) - node T_428 = cat(T_426, T_427) - node T_429 = cat(T_424, T_428) - node T_430 = bits(T_419, 6, 4) - node T_431 = bits(T_430, 1, 0) - node T_432 = bits(T_431, 0, 0) - node T_433 = bits(T_431, 1, 1) - node T_434 = cat(T_432, T_433) - node T_435 = bits(T_430, 2, 2) - node T_436 = cat(T_434, T_435) - node T_437 = cat(T_429, T_436) - node T_438 = cat(T_418, T_437) - node absSigSumExtraMask = cat(T_438, UInt<1>("h01")) - node T_441 = bits(cFirstNormAbsSigSum, 42, 1) - node T_442 = dshr(T_441, normTo2ShiftDist) - node T_443 = bits(cFirstNormAbsSigSum, 15, 0) - node T_444 = not(T_443) - node T_445 = and(T_444, absSigSumExtraMask) - node T_447 = eq(T_445, UInt<1>("h00")) - node T_448 = bits(cFirstNormAbsSigSum, 15, 0) - node T_449 = and(T_448, absSigSumExtraMask) - node T_451 = neq(T_449, UInt<1>("h00")) - node T_452 = mux(doIncrSig, T_447, T_451) - node T_453 = cat(T_442, T_452) - node sigX3 = bits(T_453, 27, 0) - node T_455 = bits(sigX3, 27, 26) - node sigX3Shift1 = eq(T_455, UInt<1>("h00")) - node T_458 = sub(io.fromPreMul.sExpSum, estNormDist) - node sExpX3 = tail(T_458, 1) - node T_460 = bits(sigX3, 27, 25) - node isZeroY = eq(T_460, UInt<1>("h00")) - node T_463 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_463) - node sExpX3_13 = bits(sExpX3, 9, 0) - node T_466 = bits(sExpX3, 10, 10) - node T_468 = sub(UInt<27>("h00"), T_466) - node T_469 = tail(T_468, 1) - node T_470 = not(sExpX3_13) - node T_472 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_470) - node T_473 = bits(T_472, 131, 107) - node T_474 = bits(T_473, 15, 0) - node T_477 = shl(UInt<8>("h0ff"), 8) - node T_478 = xor(UInt<16>("h0ffff"), T_477) - node T_479 = shr(T_474, 8) - node T_480 = and(T_479, T_478) - node T_481 = bits(T_474, 7, 0) - node T_482 = shl(T_481, 8) - node T_483 = not(T_478) - node T_484 = and(T_482, T_483) - node T_485 = or(T_480, T_484) - node T_486 = bits(T_478, 11, 0) - node T_487 = shl(T_486, 4) - node T_488 = xor(T_478, T_487) - node T_489 = shr(T_485, 4) - node T_490 = and(T_489, T_488) - node T_491 = bits(T_485, 11, 0) - node T_492 = shl(T_491, 4) - node T_493 = not(T_488) - node T_494 = and(T_492, T_493) - node T_495 = or(T_490, T_494) - node T_496 = bits(T_488, 13, 0) - node T_497 = shl(T_496, 2) - node T_498 = xor(T_488, T_497) - node T_499 = shr(T_495, 2) - node T_500 = and(T_499, T_498) - node T_501 = bits(T_495, 13, 0) - node T_502 = shl(T_501, 2) - node T_503 = not(T_498) - node T_504 = and(T_502, T_503) - node T_505 = or(T_500, T_504) - node T_506 = bits(T_498, 14, 0) - node T_507 = shl(T_506, 1) - node T_508 = xor(T_498, T_507) - node T_509 = shr(T_505, 1) - node T_510 = and(T_509, T_508) - node T_511 = bits(T_505, 14, 0) - node T_512 = shl(T_511, 1) - node T_513 = not(T_508) - node T_514 = and(T_512, T_513) - node T_515 = or(T_510, T_514) - node T_516 = bits(T_473, 24, 16) - node T_517 = bits(T_516, 7, 0) - node T_520 = shl(UInt<4>("h0f"), 4) - node T_521 = xor(UInt<8>("h0ff"), T_520) - node T_522 = shr(T_517, 4) - node T_523 = and(T_522, T_521) - node T_524 = bits(T_517, 3, 0) - node T_525 = shl(T_524, 4) - node T_526 = not(T_521) - node T_527 = and(T_525, T_526) - node T_528 = or(T_523, T_527) - node T_529 = bits(T_521, 5, 0) - node T_530 = shl(T_529, 2) - node T_531 = xor(T_521, T_530) - node T_532 = shr(T_528, 2) - node T_533 = and(T_532, T_531) - node T_534 = bits(T_528, 5, 0) - node T_535 = shl(T_534, 2) - node T_536 = not(T_531) - node T_537 = and(T_535, T_536) - node T_538 = or(T_533, T_537) - node T_539 = bits(T_531, 6, 0) - node T_540 = shl(T_539, 1) - node T_541 = xor(T_531, T_540) - node T_542 = shr(T_538, 1) - node T_543 = and(T_542, T_541) - node T_544 = bits(T_538, 6, 0) - node T_545 = shl(T_544, 1) - node T_546 = not(T_541) - node T_547 = and(T_545, T_546) - node T_548 = or(T_543, T_547) - node T_549 = bits(T_516, 8, 8) - node T_550 = cat(T_548, T_549) - node T_551 = cat(T_515, T_550) - node T_552 = bits(sigX3, 26, 26) - node T_553 = or(T_551, T_552) - node T_555 = cat(T_553, UInt<2>("h03")) - node roundMask = or(T_469, T_555) - node T_557 = shr(roundMask, 1) - node T_558 = not(T_557) - node roundPosMask = and(T_558, roundMask) - node T_560 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_560, UInt<1>("h00")) - node T_563 = shr(roundMask, 1) - node T_564 = and(sigX3, T_563) - node anyRoundExtra = neq(T_564, UInt<1>("h00")) - node T_567 = not(sigX3) - node T_568 = shr(roundMask, 1) - node T_569 = and(T_567, T_568) - node allRoundExtra = eq(T_569, UInt<1>("h00")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_575 = not(doIncrSig) - node T_576 = and(T_575, roundingMode_nearest_even) - node T_577 = and(T_576, roundPosBit) - node T_578 = and(T_577, anyRoundExtra) - node T_579 = not(doIncrSig) - node T_580 = and(T_579, roundDirectUp) - node T_581 = and(T_580, anyRound) - node T_582 = or(T_578, T_581) - node T_583 = and(doIncrSig, allRound) - node T_584 = or(T_582, T_583) - node T_585 = and(doIncrSig, roundingMode_nearest_even) - node T_586 = and(T_585, roundPosBit) - node T_587 = or(T_584, T_586) - node T_588 = and(doIncrSig, roundDirectUp) - node T_590 = and(T_588, UInt<1>("h01")) - node roundUp = or(T_587, T_590) - node T_592 = not(roundPosBit) - node T_593 = and(roundingMode_nearest_even, T_592) - node T_594 = and(T_593, allRoundExtra) - node T_595 = and(roundingMode_nearest_even, roundPosBit) - node T_596 = not(anyRoundExtra) - node T_597 = and(T_595, T_596) - node roundEven = mux(doIncrSig, T_594, T_597) - node T_599 = not(allRound) - node roundInexact = mux(doIncrSig, T_599, anyRound) - node T_601 = or(sigX3, roundMask) - node T_602 = shr(T_601, 2) - node T_604 = add(T_602, UInt<1>("h01")) - node T_605 = tail(T_604, 1) - node roundUp_sigY3 = bits(T_605, 25, 0) - node T_607 = not(roundUp) - node T_608 = not(roundEven) - node T_609 = and(T_607, T_608) - node T_610 = bits(T_609, 0, 0) - node T_611 = not(roundMask) - node T_612 = and(sigX3, T_611) - node T_613 = shr(T_612, 2) - node T_615 = mux(T_610, T_613, UInt<1>("h00")) - node T_616 = bits(roundUp, 0, 0) - node T_618 = mux(T_616, roundUp_sigY3, UInt<1>("h00")) - node T_619 = or(T_615, T_618) - node T_620 = shr(roundMask, 1) - node T_621 = not(T_620) - node T_622 = and(roundUp_sigY3, T_621) - node T_624 = mux(roundEven, T_622, UInt<1>("h00")) - node sigY3 = or(T_619, T_624) - node T_626 = bits(sigY3, 25, 25) - node T_628 = add(sExpX3, UInt<1>("h01")) - node T_629 = tail(T_628, 1) - node T_631 = mux(T_626, T_629, UInt<1>("h00")) - node T_632 = bits(sigY3, 24, 24) - node T_634 = mux(T_632, sExpX3, UInt<1>("h00")) - node T_635 = or(T_631, T_634) - node T_636 = bits(sigY3, 25, 24) - node T_638 = eq(T_636, UInt<1>("h00")) - node T_640 = sub(sExpX3, UInt<1>("h01")) - node T_641 = tail(T_640, 1) - node T_643 = mux(T_638, T_641, UInt<1>("h00")) - node sExpY = or(T_635, T_643) - node expY = bits(sExpY, 8, 0) - node T_646 = bits(sigY3, 22, 0) - node T_647 = bits(sigY3, 23, 1) - node fractY = mux(sigX3Shift1, T_646, T_647) - node T_649 = bits(sExpY, 9, 7) - node overflowY = eq(T_649, UInt<2>("h03")) - node T_652 = not(isZeroY) - node T_653 = bits(sExpY, 9, 9) - node T_654 = bits(sExpY, 8, 0) - node T_656 = lt(T_654, UInt<7>("h06b")) - node T_657 = or(T_653, T_656) - node totalUnderflowY = and(T_652, T_657) - node T_659 = bits(sExpX3, 10, 10) - node T_662 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) - node T_663 = leq(sExpX3_13, T_662) - node T_664 = or(T_659, T_663) - node underflowY = and(roundInexact, T_664) - node T_666 = and(roundingMode_min, signY) - node T_667 = not(signY) - node T_668 = and(roundingMode_max, T_667) - node roundMagUp = or(T_666, T_668) - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_674 = not(addSpecial) - node T_675 = not(notSpecial_addZeros) - node commonCase = and(T_674, T_675) - node T_677 = and(isInfA, isZeroB) - node T_678 = and(isZeroA, isInfB) - node T_679 = or(T_677, T_678) - node T_680 = not(isNaNA) - node T_681 = not(isNaNB) - node T_682 = and(T_680, T_681) - node T_683 = or(isInfA, isInfB) - node T_684 = and(T_682, T_683) - node T_685 = and(T_684, isInfC) - node T_686 = and(T_685, doSubMags) - node notSigNaN_invalid = or(T_679, T_686) - node T_688 = or(isSigNaNA, isSigNaNB) - node T_689 = or(T_688, isSigNaNC) - node invalid = or(T_689, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_693 = and(commonCase, roundInexact) - node inexact = or(overflow, T_693) - node T_695 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_695, totalUnderflowY) - node T_697 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_697, roundMagUp) - node T_699 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_699) - node T_701 = or(isInfA, isInfB) - node T_702 = or(T_701, isInfC) - node T_703 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_702, T_703) - node T_705 = or(isNaNA, isNaNB) - node T_706 = or(T_705, isNaNC) - node isNaNOut = or(T_706, notSigNaN_invalid) - node T_709 = eq(doSubMags, UInt<1>("h00")) - node T_710 = and(T_709, io.fromPreMul.opSignC) - node T_712 = eq(isSpecialC, UInt<1>("h00")) - node T_713 = and(mulSpecial, T_712) - node T_714 = and(T_713, io.fromPreMul.signProd) - node T_715 = or(T_710, T_714) - node T_717 = eq(mulSpecial, UInt<1>("h00")) - node T_718 = and(T_717, isSpecialC) - node T_719 = and(T_718, io.fromPreMul.opSignC) - node T_720 = or(T_715, T_719) - node T_722 = eq(mulSpecial, UInt<1>("h00")) - node T_723 = and(T_722, notSpecial_addZeros) - node T_724 = and(T_723, doSubMags) - node T_725 = and(T_724, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_720, T_725) - node T_728 = eq(isNaNOut, UInt<1>("h00")) - node T_729 = and(T_728, uncommonCaseSignOut) - node T_730 = and(commonCase, signY) - node signOut = or(T_729, T_730) - node T_734 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) - node T_735 = not(T_734) - node T_736 = and(expY, T_735) - node T_738 = not(UInt<9>("h06b")) - node T_740 = mux(pegMinFiniteMagOut, T_738, UInt<9>("h00")) - node T_741 = not(T_740) - node T_742 = and(T_736, T_741) - node T_745 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) - node T_746 = not(T_745) - node T_747 = and(T_742, T_746) - node T_750 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) - node T_751 = not(T_750) - node T_752 = and(T_747, T_751) - node T_755 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) - node T_756 = or(T_752, T_755) - node T_759 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) - node T_760 = or(T_756, T_759) - node T_763 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) - node T_764 = or(T_760, T_763) - node T_767 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) - node expOut = or(T_764, T_767) - node T_769 = and(totalUnderflowY, roundMagUp) - node T_770 = or(T_769, isNaNOut) - node T_772 = mux(T_770, UInt<1>("h00"), fractY) - node T_773 = shl(isNaNOut, 22) - node T_774 = or(T_772, T_773) - node T_776 = sub(UInt<23>("h00"), pegMaxFiniteMagOut) - node T_777 = tail(T_776, 1) - node fractOut = or(T_774, T_777) - node T_779 = cat(expOut, fractOut) - node T_780 = cat(signOut, T_779) - io.out <= T_780 - node T_782 = cat(invalid, UInt<1>("h00")) - node T_783 = cat(underflow, inexact) - node T_784 = cat(overflow, T_783) - node T_785 = cat(T_782, T_784) - io.exceptionFlags <= T_785 + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_43 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_44 = and(_T_41, _T_43) @[Decoupled.scala 188:33] + node _T_45 = and(_T_41, maybe_full) @[Decoupled.scala 189:32] + node _T_46 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_46 + node _T_47 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_47 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_49 = ram[UInt<1>("h00")], clock + _T_49 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_54 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_54 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_56 = eq(_T_44, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_56 @[Decoupled.scala 204:16] + node _T_58 = eq(_T_45, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_58 @[Decoupled.scala 205:16] + infer mport _T_60 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_60 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_44 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_66 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_67 = asUInt(_T_66) @[Decoupled.scala 221:40] + node _T_68 = tail(_T_67, 1) @[Decoupled.scala 221:40] + node _T_69 = and(maybe_full, _T_41) @[Decoupled.scala 223:32] + node _T_70 = cat(_T_69, _T_68) @[Cat.scala 30:58] + io.count <= _T_70 @[Decoupled.scala 223:14] - module MulAddRecFN : - input clk : Clock + module AXI4FragmenterAXI4FragmenterSideband_2 : + input clock : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<3>} io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul - mulAddRecFN_preMul.io is invalid - mulAddRecFN_preMul.clk <= clk - mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul - mulAddRecFN_postMul.io is invalid - mulAddRecFN_postMul.clk <= clk - mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op - mulAddRecFN_preMul.io.a <= io.a - mulAddRecFN_preMul.io.b <= io.b - mulAddRecFN_preMul.io.c <= io.c - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) - node T_17 = add(T_14, T_16) - node T_18 = tail(T_17, 1) - mulAddRecFN_postMul.io.mulAddResult <= T_18 - io.out <= mulAddRecFN_postMul.io.out - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<2>("h03")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] - module FPUFMAPipe : - input clk : Clock + module AXI4FragmenterAXI4FragmenterSideband_3 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - - io is invalid - node one = shl(UInt<1>("h01"), 31) - node T_136 = bits(io.in.bits.in1, 32, 32) - node T_137 = bits(io.in.bits.in2, 32, 32) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 32) - reg valid : UInt<1>, clk - valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : - in <- io.in.bits - node T_187 = bits(io.in.bits.cmd, 1, 1) - node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bits(io.in.bits.cmd, 0, 0) - node T_191 = cat(T_189, T_190) - in.cmd <= T_191 - when io.in.bits.swap23 : - in.in2 <= one - skip - node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h00")) - when T_194 : - in.in3 <= zero - skip - skip - inst fma of MulAddRecFN - fma.io is invalid - fma.clk <= clk - fma.reset <= reset - fma.io.op <= in.cmd - fma.io.roundingMode <= in.rm - fma.io.a <= in.in1 - fma.io.b <= in.in2 - fma.io.c <= in.in3 - wire res : {data : UInt<65>, exc : UInt<5>} - res is invalid - node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_204 = cat(T_203, fma.io.out) - res.data <= T_204 - res.exc <= fma.io.exceptionFlags - reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_207 <= valid - reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk - when valid : - T_208 <- res - skip - wire T_219 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_219 is invalid - T_219.valid <= T_207 - T_219.bits <- T_208 - io.out <- T_219 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<3>} - module MulAddRecFN_preMul_115 : - input clk : Clock + io is invalid + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<2>("h03")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] + + module AXI4Fragmenter_1 : + input clock : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} io is invalid - node signA = bits(io.a, 64, 64) - node expA = bits(io.a, 63, 52) - node fractA = bits(io.a, 51, 0) - node T_50 = bits(expA, 11, 9) - node isZeroA = eq(T_50, UInt<1>("h00")) - node T_54 = eq(isZeroA, UInt<1>("h00")) - node sigA = cat(T_54, fractA) - node signB = bits(io.b, 64, 64) - node expB = bits(io.b, 63, 52) - node fractB = bits(io.b, 51, 0) - node T_59 = bits(expB, 11, 9) - node isZeroB = eq(T_59, UInt<1>("h00")) - node T_63 = eq(isZeroB, UInt<1>("h00")) - node sigB = cat(T_63, fractB) - node T_65 = bits(io.c, 64, 64) - node T_66 = bits(io.op, 0, 0) - node opSignC = xor(T_65, T_66) - node expC = bits(io.c, 63, 52) - node fractC = bits(io.c, 51, 0) - node T_70 = bits(expC, 11, 9) - node isZeroC = eq(T_70, UInt<1>("h00")) - node T_74 = eq(isZeroC, UInt<1>("h00")) - node sigC = cat(T_74, fractC) - node T_76 = xor(signA, signB) - node T_77 = bits(io.op, 1, 1) - node signProd = xor(T_76, T_77) - node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bits(expB, 11, 11) - node T_82 = eq(T_80, UInt<1>("h00")) - node T_84 = sub(UInt<3>("h00"), T_82) - node T_85 = tail(T_84, 1) - node T_86 = bits(expB, 10, 0) - node T_87 = cat(T_85, T_86) - node T_88 = add(expA, T_87) - node T_89 = tail(T_88, 1) - node T_91 = add(T_89, UInt<6>("h038")) - node sExpAlignedProd = tail(T_91, 1) - node doSubMags = xor(signProd, opSignC) - node T_94 = sub(sExpAlignedProd, expC) - node sNatCAlignDist = tail(T_94, 1) - node T_96 = bits(sNatCAlignDist, 13, 13) - node CAlignDist_floor = or(isZeroProd, T_96) - node T_98 = bits(sNatCAlignDist, 12, 0) - node T_100 = eq(T_98, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_100) - node T_103 = eq(isZeroC, UInt<1>("h00")) - node T_104 = bits(sNatCAlignDist, 12, 0) - node T_106 = lt(T_104, UInt<6>("h036")) - node T_107 = or(CAlignDist_floor, T_106) - node isCDominant = and(T_103, T_107) - node T_110 = bits(sNatCAlignDist, 12, 0) - node T_112 = lt(T_110, UInt<8>("h0a1")) - node T_113 = bits(sNatCAlignDist, 7, 0) - node T_115 = mux(T_112, T_113, UInt<8>("h0a1")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115) - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_119 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) - node T_120 = bits(T_119, 147, 95) - node T_121 = bits(T_120, 31, 0) - node T_124 = shl(UInt<16>("h0ffff"), 16) - node T_125 = xor(UInt<32>("h0ffffffff"), T_124) - node T_126 = shr(T_121, 16) - node T_127 = and(T_126, T_125) - node T_128 = bits(T_121, 15, 0) - node T_129 = shl(T_128, 16) - node T_130 = not(T_125) - node T_131 = and(T_129, T_130) - node T_132 = or(T_127, T_131) - node T_133 = bits(T_125, 23, 0) - node T_134 = shl(T_133, 8) - node T_135 = xor(T_125, T_134) - node T_136 = shr(T_132, 8) - node T_137 = and(T_136, T_135) - node T_138 = bits(T_132, 23, 0) - node T_139 = shl(T_138, 8) - node T_140 = not(T_135) - node T_141 = and(T_139, T_140) - node T_142 = or(T_137, T_141) - node T_143 = bits(T_135, 27, 0) - node T_144 = shl(T_143, 4) - node T_145 = xor(T_135, T_144) - node T_146 = shr(T_142, 4) - node T_147 = and(T_146, T_145) - node T_148 = bits(T_142, 27, 0) - node T_149 = shl(T_148, 4) - node T_150 = not(T_145) - node T_151 = and(T_149, T_150) - node T_152 = or(T_147, T_151) - node T_153 = bits(T_145, 29, 0) - node T_154 = shl(T_153, 2) - node T_155 = xor(T_145, T_154) - node T_156 = shr(T_152, 2) - node T_157 = and(T_156, T_155) - node T_158 = bits(T_152, 29, 0) - node T_159 = shl(T_158, 2) - node T_160 = not(T_155) - node T_161 = and(T_159, T_160) - node T_162 = or(T_157, T_161) - node T_163 = bits(T_155, 30, 0) - node T_164 = shl(T_163, 1) - node T_165 = xor(T_155, T_164) - node T_166 = shr(T_162, 1) - node T_167 = and(T_166, T_165) - node T_168 = bits(T_162, 30, 0) - node T_169 = shl(T_168, 1) - node T_170 = not(T_165) - node T_171 = and(T_169, T_170) - node T_172 = or(T_167, T_171) - node T_173 = bits(T_120, 52, 32) - node T_174 = bits(T_173, 15, 0) - node T_177 = shl(UInt<8>("h0ff"), 8) - node T_178 = xor(UInt<16>("h0ffff"), T_177) - node T_179 = shr(T_174, 8) - node T_180 = and(T_179, T_178) - node T_181 = bits(T_174, 7, 0) - node T_182 = shl(T_181, 8) - node T_183 = not(T_178) - node T_184 = and(T_182, T_183) - node T_185 = or(T_180, T_184) - node T_186 = bits(T_178, 11, 0) - node T_187 = shl(T_186, 4) - node T_188 = xor(T_178, T_187) - node T_189 = shr(T_185, 4) - node T_190 = and(T_189, T_188) - node T_191 = bits(T_185, 11, 0) - node T_192 = shl(T_191, 4) - node T_193 = not(T_188) - node T_194 = and(T_192, T_193) - node T_195 = or(T_190, T_194) - node T_196 = bits(T_188, 13, 0) - node T_197 = shl(T_196, 2) - node T_198 = xor(T_188, T_197) - node T_199 = shr(T_195, 2) - node T_200 = and(T_199, T_198) - node T_201 = bits(T_195, 13, 0) - node T_202 = shl(T_201, 2) - node T_203 = not(T_198) - node T_204 = and(T_202, T_203) - node T_205 = or(T_200, T_204) - node T_206 = bits(T_198, 14, 0) - node T_207 = shl(T_206, 1) - node T_208 = xor(T_198, T_207) - node T_209 = shr(T_205, 1) - node T_210 = and(T_209, T_208) - node T_211 = bits(T_205, 14, 0) - node T_212 = shl(T_211, 1) - node T_213 = not(T_208) - node T_214 = and(T_212, T_213) - node T_215 = or(T_210, T_214) - node T_216 = bits(T_173, 20, 16) - node T_217 = bits(T_216, 3, 0) - node T_218 = bits(T_217, 1, 0) - node T_219 = bits(T_218, 0, 0) - node T_220 = bits(T_218, 1, 1) - node T_221 = cat(T_219, T_220) - node T_222 = bits(T_217, 3, 2) - node T_223 = bits(T_222, 0, 0) - node T_224 = bits(T_222, 1, 1) - node T_225 = cat(T_223, T_224) - node T_226 = cat(T_221, T_225) - node T_227 = bits(T_216, 4, 4) - node T_228 = cat(T_226, T_227) - node T_229 = cat(T_215, T_228) - node CExtraMask = cat(T_172, T_229) - node T_231 = not(sigC) - node negSigC = mux(doSubMags, T_231, sigC) - node T_234 = sub(UInt<108>("h00"), doSubMags) - node T_235 = tail(T_234, 1) - node T_236 = cat(negSigC, T_235) - node T_237 = cat(doSubMags, T_236) - node T_238 = asSInt(T_237) - node T_239 = dshr(T_238, CAlignDist) - node T_240 = and(sigC, CExtraMask) - node T_242 = neq(T_240, UInt<1>("h00")) - node T_243 = xor(T_242, doSubMags) - node T_244 = asUInt(T_239) - node T_245 = cat(T_244, T_243) - node alignedNegSigC = bits(T_245, 161, 0) - io.mulAddA <= sigA - io.mulAddB <= sigB - node T_247 = bits(alignedNegSigC, 106, 1) - io.mulAddC <= T_247 - node T_248 = bits(expA, 11, 9) - io.toPostMul.highExpA <= T_248 - node T_249 = bits(fractA, 51, 51) - io.toPostMul.isNaN_isQuietNaNA <= T_249 - node T_250 = bits(expB, 11, 9) - io.toPostMul.highExpB <= T_250 - node T_251 = bits(fractB, 51, 51) - io.toPostMul.isNaN_isQuietNaNB <= T_251 - io.toPostMul.signProd <= signProd - io.toPostMul.isZeroProd <= isZeroProd - io.toPostMul.opSignC <= opSignC - node T_252 = bits(expC, 11, 9) - io.toPostMul.highExpC <= T_252 - node T_253 = bits(fractC, 51, 51) - io.toPostMul.isNaN_isQuietNaNC <= T_253 - io.toPostMul.isCDominant <= isCDominant - io.toPostMul.CAlignDist_0 <= CAlignDist_0 - io.toPostMul.CAlignDist <= CAlignDist - node T_254 = bits(alignedNegSigC, 0, 0) - io.toPostMul.bit0AlignedNegSigC <= T_254 - node T_255 = bits(alignedNegSigC, 161, 107) - io.toPostMul.highAlignedNegSigC <= T_255 - io.toPostMul.sExpSum <= sExpSum - io.toPostMul.roundingMode <= io.roundingMode - - module MulAddRecFN_postMul_116 : - input clk : Clock + io is invalid + inst Queue of Queue_43 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + wire _T_484 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_484 is invalid @[Decoupled.scala 272:19] + _T_484.bits <- Queue.io.deq.bits @[Decoupled.scala 273:14] + _T_484.valid <= Queue.io.deq.valid @[Decoupled.scala 274:15] + Queue.io.deq.ready <= _T_484.ready @[Decoupled.scala 275:15] + wire _T_509 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_509 is invalid @[Fragmenter.scala 66:23] + reg _T_535 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_537 : UInt<28>, clock @[Fragmenter.scala 69:25] + reg _T_539 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_540 = mux(_T_535, _T_539, _T_484.bits.len) @[Fragmenter.scala 72:23] + node _T_541 = mux(_T_535, _T_537, _T_484.bits.addr) @[Fragmenter.scala 73:23] + node _T_542 = bits(_T_541, 2, 0) @[Fragmenter.scala 75:53] + node _T_543 = shr(_T_541, 3) @[Fragmenter.scala 76:23] + node _T_544 = bits(_T_543, 7, 0) @[Fragmenter.scala 77:27] + node _T_546 = xor(_T_541, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_547 = cvt(_T_546) @[Parameters.scala 117:49] + node _T_549 = and(_T_547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_550 = asSInt(_T_549) @[Parameters.scala 117:52] + node _T_552 = eq(_T_550, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_555 : UInt<1>[1] @[Parameters.scala 50:36] + _T_555 is invalid @[Parameters.scala 50:36] + _T_555[0] <= _T_552 @[Parameters.scala 50:36] + node _T_561 = shr(_T_540, 1) @[package.scala 32:45] + node _T_562 = or(_T_540, _T_561) @[package.scala 32:40] + node _T_563 = shr(_T_562, 2) @[package.scala 32:45] + node _T_564 = or(_T_562, _T_563) @[package.scala 32:40] + node _T_565 = shr(_T_564, 4) @[package.scala 32:45] + node _T_566 = or(_T_564, _T_565) @[package.scala 32:40] + node _T_567 = shr(_T_566, 1) @[Fragmenter.scala 89:37] + node _T_568 = not(_T_540) @[Fragmenter.scala 90:32] + node _T_569 = shl(_T_568, 1) @[package.scala 25:45] + node _T_570 = bits(_T_569, 7, 0) @[package.scala 25:50] + node _T_571 = or(_T_568, _T_570) @[package.scala 25:40] + node _T_572 = shl(_T_571, 2) @[package.scala 25:45] + node _T_573 = bits(_T_572, 7, 0) @[package.scala 25:50] + node _T_574 = or(_T_571, _T_573) @[package.scala 25:40] + node _T_575 = shl(_T_574, 4) @[package.scala 25:45] + node _T_576 = bits(_T_575, 7, 0) @[package.scala 25:50] + node _T_577 = or(_T_574, _T_576) @[package.scala 25:40] + node _T_578 = not(_T_577) @[Fragmenter.scala 90:24] + node _T_579 = or(_T_567, _T_578) @[Fragmenter.scala 91:32] + node _T_580 = shl(_T_544, 1) @[package.scala 25:45] + node _T_581 = bits(_T_580, 7, 0) @[package.scala 25:50] + node _T_582 = or(_T_544, _T_581) @[package.scala 25:40] + node _T_583 = shl(_T_582, 2) @[package.scala 25:45] + node _T_584 = bits(_T_583, 7, 0) @[package.scala 25:50] + node _T_585 = or(_T_582, _T_584) @[package.scala 25:40] + node _T_586 = shl(_T_585, 4) @[package.scala 25:45] + node _T_587 = bits(_T_586, 7, 0) @[package.scala 25:50] + node _T_588 = or(_T_585, _T_587) @[package.scala 25:40] + node _T_589 = not(_T_588) @[Fragmenter.scala 92:24] + node _T_590 = and(_T_579, _T_589) @[Fragmenter.scala 94:37] + node _T_591 = and(_T_590, UInt<1>("h00")) @[Fragmenter.scala 94:46] + node _T_593 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_595 = neq(_T_484.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_596 = or(_T_593, _T_595) @[Fragmenter.scala 99:25] + node _T_598 = mux(_T_596, UInt<1>("h00"), _T_591) @[Fragmenter.scala 102:25] + node _T_599 = shl(_T_598, 1) @[package.scala 17:29] + node _T_601 = or(_T_599, UInt<1>("h01")) @[package.scala 17:34] + node _T_603 = cat(UInt<1>("h00"), _T_598) @[Cat.scala 30:58] + node _T_604 = not(_T_603) @[package.scala 17:47] + node _T_605 = and(_T_601, _T_604) @[package.scala 17:45] + node _T_606 = dshl(_T_605, _T_484.bits.size) @[Fragmenter.scala 105:38] + node _T_607 = add(_T_541, _T_606) @[Fragmenter.scala 105:29] + node _T_608 = tail(_T_607, 1) @[Fragmenter.scala 105:29] + node _T_610 = cat(_T_484.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_611 = dshl(_T_610, _T_484.bits.size) @[Bundles.scala 28:21] + node _T_612 = shr(_T_611, 8) @[Bundles.scala 28:30] + wire _T_613 : UInt + _T_613 is invalid + _T_613 <= _T_608 + node _T_615 = eq(_T_484.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_615 : @[Fragmenter.scala 108:59] + node _T_616 = and(_T_608, _T_612) @[Fragmenter.scala 109:33] + node _T_617 = not(_T_484.bits.addr) @[Fragmenter.scala 109:49] + node _T_618 = or(_T_617, _T_612) @[Fragmenter.scala 109:62] + node _T_619 = not(_T_618) @[Fragmenter.scala 109:47] + node _T_620 = or(_T_616, _T_619) @[Fragmenter.scala 109:45] + _T_613 <= _T_620 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_622 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_622 : @[Fragmenter.scala 111:60] + _T_613 <= _T_484.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_623 = eq(_T_598, _T_540) @[Fragmenter.scala 115:27] + node _T_624 = and(_T_509.ready, _T_623) @[Fragmenter.scala 116:30] + _T_484.ready <= _T_624 @[Fragmenter.scala 116:17] + _T_509.valid <= _T_484.valid @[Fragmenter.scala 117:19] + _T_509.bits <- _T_484.bits @[Fragmenter.scala 119:18] + _T_509.bits.len <= _T_598 @[Fragmenter.scala 120:22] + node _T_625 = not(_T_541) @[Fragmenter.scala 127:28] + node _T_627 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_628 = dshl(_T_627, _T_484.bits.size) @[package.scala 19:71] + node _T_629 = bits(_T_628, 2, 0) @[package.scala 19:76] + node _T_630 = not(_T_629) @[package.scala 19:40] + node _T_631 = or(_T_625, _T_630) @[Fragmenter.scala 127:34] + node _T_632 = not(_T_631) @[Fragmenter.scala 127:26] + _T_509.bits.addr <= _T_632 @[Fragmenter.scala 127:23] + node _T_633 = and(_T_509.ready, _T_509.valid) @[Decoupled.scala 30:37] + when _T_633 : @[Fragmenter.scala 129:27] + node _T_635 = eq(_T_623, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_535 <= _T_635 @[Fragmenter.scala 130:16] + _T_537 <= _T_613 @[Fragmenter.scala 131:18] + node _T_636 = sub(_T_540, _T_605) @[Fragmenter.scala 132:25] + node _T_637 = asUInt(_T_636) @[Fragmenter.scala 132:25] + node _T_638 = tail(_T_637, 1) @[Fragmenter.scala 132:25] + _T_539 <= _T_638 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + inst Queue_1 of Queue_44 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + wire _T_674 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_674 is invalid @[Decoupled.scala 272:19] + _T_674.bits <- Queue_1.io.deq.bits @[Decoupled.scala 273:14] + _T_674.valid <= Queue_1.io.deq.valid @[Decoupled.scala 274:15] + Queue_1.io.deq.ready <= _T_674.ready @[Decoupled.scala 275:15] + wire _T_699 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_699 is invalid @[Fragmenter.scala 66:23] + reg _T_725 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_727 : UInt<28>, clock @[Fragmenter.scala 69:25] + reg _T_729 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_730 = mux(_T_725, _T_729, _T_674.bits.len) @[Fragmenter.scala 72:23] + node _T_731 = mux(_T_725, _T_727, _T_674.bits.addr) @[Fragmenter.scala 73:23] + node _T_732 = bits(_T_731, 2, 0) @[Fragmenter.scala 75:53] + node _T_733 = shr(_T_731, 3) @[Fragmenter.scala 76:23] + node _T_734 = bits(_T_733, 7, 0) @[Fragmenter.scala 77:27] + node _T_736 = xor(_T_731, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_737 = cvt(_T_736) @[Parameters.scala 117:49] + node _T_739 = and(_T_737, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_740 = asSInt(_T_739) @[Parameters.scala 117:52] + node _T_742 = eq(_T_740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_745 : UInt<1>[1] @[Parameters.scala 50:36] + _T_745 is invalid @[Parameters.scala 50:36] + _T_745[0] <= _T_742 @[Parameters.scala 50:36] + node _T_751 = shr(_T_730, 1) @[package.scala 32:45] + node _T_752 = or(_T_730, _T_751) @[package.scala 32:40] + node _T_753 = shr(_T_752, 2) @[package.scala 32:45] + node _T_754 = or(_T_752, _T_753) @[package.scala 32:40] + node _T_755 = shr(_T_754, 4) @[package.scala 32:45] + node _T_756 = or(_T_754, _T_755) @[package.scala 32:40] + node _T_757 = shr(_T_756, 1) @[Fragmenter.scala 89:37] + node _T_758 = not(_T_730) @[Fragmenter.scala 90:32] + node _T_759 = shl(_T_758, 1) @[package.scala 25:45] + node _T_760 = bits(_T_759, 7, 0) @[package.scala 25:50] + node _T_761 = or(_T_758, _T_760) @[package.scala 25:40] + node _T_762 = shl(_T_761, 2) @[package.scala 25:45] + node _T_763 = bits(_T_762, 7, 0) @[package.scala 25:50] + node _T_764 = or(_T_761, _T_763) @[package.scala 25:40] + node _T_765 = shl(_T_764, 4) @[package.scala 25:45] + node _T_766 = bits(_T_765, 7, 0) @[package.scala 25:50] + node _T_767 = or(_T_764, _T_766) @[package.scala 25:40] + node _T_768 = not(_T_767) @[Fragmenter.scala 90:24] + node _T_769 = or(_T_757, _T_768) @[Fragmenter.scala 91:32] + node _T_770 = shl(_T_734, 1) @[package.scala 25:45] + node _T_771 = bits(_T_770, 7, 0) @[package.scala 25:50] + node _T_772 = or(_T_734, _T_771) @[package.scala 25:40] + node _T_773 = shl(_T_772, 2) @[package.scala 25:45] + node _T_774 = bits(_T_773, 7, 0) @[package.scala 25:50] + node _T_775 = or(_T_772, _T_774) @[package.scala 25:40] + node _T_776 = shl(_T_775, 4) @[package.scala 25:45] + node _T_777 = bits(_T_776, 7, 0) @[package.scala 25:50] + node _T_778 = or(_T_775, _T_777) @[package.scala 25:40] + node _T_779 = not(_T_778) @[Fragmenter.scala 92:24] + node _T_780 = and(_T_769, _T_779) @[Fragmenter.scala 94:37] + node _T_781 = and(_T_780, UInt<1>("h00")) @[Fragmenter.scala 94:46] + node _T_783 = eq(_T_674.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_785 = neq(_T_674.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_786 = or(_T_783, _T_785) @[Fragmenter.scala 99:25] + node _T_788 = mux(_T_786, UInt<1>("h00"), _T_781) @[Fragmenter.scala 102:25] + node _T_789 = shl(_T_788, 1) @[package.scala 17:29] + node _T_791 = or(_T_789, UInt<1>("h01")) @[package.scala 17:34] + node _T_793 = cat(UInt<1>("h00"), _T_788) @[Cat.scala 30:58] + node _T_794 = not(_T_793) @[package.scala 17:47] + node _T_795 = and(_T_791, _T_794) @[package.scala 17:45] + node _T_796 = dshl(_T_795, _T_674.bits.size) @[Fragmenter.scala 105:38] + node _T_797 = add(_T_731, _T_796) @[Fragmenter.scala 105:29] + node _T_798 = tail(_T_797, 1) @[Fragmenter.scala 105:29] + node _T_800 = cat(_T_674.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_801 = dshl(_T_800, _T_674.bits.size) @[Bundles.scala 28:21] + node _T_802 = shr(_T_801, 8) @[Bundles.scala 28:30] + wire _T_803 : UInt + _T_803 is invalid + _T_803 <= _T_798 + node _T_805 = eq(_T_674.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_805 : @[Fragmenter.scala 108:59] + node _T_806 = and(_T_798, _T_802) @[Fragmenter.scala 109:33] + node _T_807 = not(_T_674.bits.addr) @[Fragmenter.scala 109:49] + node _T_808 = or(_T_807, _T_802) @[Fragmenter.scala 109:62] + node _T_809 = not(_T_808) @[Fragmenter.scala 109:47] + node _T_810 = or(_T_806, _T_809) @[Fragmenter.scala 109:45] + _T_803 <= _T_810 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_812 = eq(_T_674.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_812 : @[Fragmenter.scala 111:60] + _T_803 <= _T_674.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_813 = eq(_T_788, _T_730) @[Fragmenter.scala 115:27] + node _T_814 = and(_T_699.ready, _T_813) @[Fragmenter.scala 116:30] + _T_674.ready <= _T_814 @[Fragmenter.scala 116:17] + _T_699.valid <= _T_674.valid @[Fragmenter.scala 117:19] + _T_699.bits <- _T_674.bits @[Fragmenter.scala 119:18] + _T_699.bits.len <= _T_788 @[Fragmenter.scala 120:22] + node _T_815 = not(_T_731) @[Fragmenter.scala 127:28] + node _T_817 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_818 = dshl(_T_817, _T_674.bits.size) @[package.scala 19:71] + node _T_819 = bits(_T_818, 2, 0) @[package.scala 19:76] + node _T_820 = not(_T_819) @[package.scala 19:40] + node _T_821 = or(_T_815, _T_820) @[Fragmenter.scala 127:34] + node _T_822 = not(_T_821) @[Fragmenter.scala 127:26] + _T_699.bits.addr <= _T_822 @[Fragmenter.scala 127:23] + node _T_823 = and(_T_699.ready, _T_699.valid) @[Decoupled.scala 30:37] + when _T_823 : @[Fragmenter.scala 129:27] + node _T_825 = eq(_T_813, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_725 <= _T_825 @[Fragmenter.scala 130:16] + _T_727 <= _T_803 @[Fragmenter.scala 131:18] + node _T_826 = sub(_T_730, _T_795) @[Fragmenter.scala 132:25] + node _T_827 = asUInt(_T_826) @[Fragmenter.scala 132:25] + node _T_828 = tail(_T_827, 1) @[Fragmenter.scala 132:25] + _T_729 <= _T_828 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + wire _T_829 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 148:24] + _T_829 is invalid @[Fragmenter.scala 148:24] + wire _T_854 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[Fragmenter.scala 151:23] + _T_854 is invalid @[Fragmenter.scala 151:23] + wire _T_869 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}} @[Fragmenter.scala 152:23] + _T_869 is invalid @[Fragmenter.scala 152:23] + inst Queue_2 of Queue_45 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_829.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_829.bits @[Decoupled.scala 255:19] + _T_829.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_2.io.deq @[Fragmenter.scala 158:16] + _T_854 <- io.out.0.r @[Fragmenter.scala 159:15] + inst Queue_3 of Queue_46 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + _T_869 <- Queue_3.io.deq @[Fragmenter.scala 165:13] + inst AXI4FragmenterAXI4FragmenterSideband of AXI4FragmenterAXI4FragmenterSideband_2 @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband.io is invalid + AXI4FragmenterAXI4FragmenterSideband.clock <= clock + AXI4FragmenterAXI4FragmenterSideband.reset <= reset + inst AXI4FragmenterAXI4FragmenterSideband_1 of AXI4FragmenterAXI4FragmenterSideband_3 @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband_1.io is invalid + AXI4FragmenterAXI4FragmenterSideband_1.clock <= clock + AXI4FragmenterAXI4FragmenterSideband_1.reset <= reset + node _T_893 = and(_T_509.valid, AXI4FragmenterAXI4FragmenterSideband.io.enq.ready) @[Fragmenter.scala 177:35] + _T_829.valid <= _T_893 @[Fragmenter.scala 177:20] + node _T_894 = and(AXI4FragmenterAXI4FragmenterSideband.io.enq.ready, _T_829.ready) @[Fragmenter.scala 178:46] + _T_509.ready <= _T_894 @[Fragmenter.scala 178:19] + node _T_895 = and(_T_509.valid, _T_829.ready) @[Fragmenter.scala 179:46] + AXI4FragmenterAXI4FragmenterSideband.io.enq.valid <= _T_895 @[Fragmenter.scala 179:31] + _T_829.bits <- _T_509.bits @[Fragmenter.scala 180:19] + AXI4FragmenterAXI4FragmenterSideband.io.enq.bits <= _T_623 @[Fragmenter.scala 181:30] + reg _T_897 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + wire _T_899 : UInt<1> @[Fragmenter.scala 185:30] + _T_899 is invalid @[Fragmenter.scala 185:30] + wire _T_901 : UInt<1> @[Fragmenter.scala 186:30] + _T_901 is invalid @[Fragmenter.scala 186:30] + node _T_902 = and(_T_901, _T_899) @[Fragmenter.scala 187:26] + when _T_902 : @[Fragmenter.scala 187:43] + _T_897 <= UInt<1>("h01") @[Fragmenter.scala 187:60] + skip @[Fragmenter.scala 187:43] + node _T_904 = and(io.out.0.aw.ready, io.out.0.aw.valid) @[Decoupled.scala 30:37] + when _T_904 : @[Fragmenter.scala 188:28] + _T_897 <= UInt<1>("h00") @[Fragmenter.scala 188:45] + skip @[Fragmenter.scala 188:28] + node _T_906 = and(_T_699.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready) @[Fragmenter.scala 191:35] + node _T_907 = or(_T_899, _T_897) @[Fragmenter.scala 191:79] + node _T_908 = and(_T_906, _T_907) @[Fragmenter.scala 191:62] + io.out.0.aw.valid <= _T_908 @[Fragmenter.scala 191:20] + node _T_909 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready, io.out.0.aw.ready) @[Fragmenter.scala 192:46] + node _T_910 = or(_T_899, _T_897) @[Fragmenter.scala 192:79] + node _T_911 = and(_T_909, _T_910) @[Fragmenter.scala 192:62] + _T_699.ready <= _T_911 @[Fragmenter.scala 192:19] + node _T_912 = and(_T_699.valid, io.out.0.aw.ready) @[Fragmenter.scala 193:46] + node _T_913 = or(_T_899, _T_897) @[Fragmenter.scala 193:79] + node _T_914 = and(_T_912, _T_913) @[Fragmenter.scala 193:62] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.valid <= _T_914 @[Fragmenter.scala 193:31] + node _T_916 = eq(_T_897, UInt<1>("h00")) @[Fragmenter.scala 194:38] + node _T_917 = and(_T_699.valid, _T_916) @[Fragmenter.scala 194:35] + _T_901 <= _T_917 @[Fragmenter.scala 194:20] + io.out.0.aw.bits <- _T_699.bits @[Fragmenter.scala 195:19] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.bits <= _T_813 @[Fragmenter.scala 196:30] + reg _T_919 : UInt<9>, clock with : (reset => (reset, UInt<9>("h00"))) @[Reg.scala 26:44] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[Fragmenter.scala 200:30] + node _T_923 = mux(_T_901, _T_795, UInt<1>("h00")) @[Fragmenter.scala 201:35] + node _T_924 = mux(_T_921, _T_923, _T_919) @[Fragmenter.scala 201:23] + node _T_926 = eq(_T_924, UInt<1>("h01")) @[Fragmenter.scala 202:27] + node _T_927 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_928 = sub(_T_924, _T_927) @[Fragmenter.scala 203:27] + node _T_929 = asUInt(_T_928) @[Fragmenter.scala 203:27] + node _T_930 = tail(_T_929, 1) @[Fragmenter.scala 203:27] + _T_919 <= _T_930 @[Fragmenter.scala 203:17] + node _T_931 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[Fragmenter.scala 204:15] + node _T_935 = neq(_T_924, UInt<1>("h00")) @[Fragmenter.scala 204:39] + node _T_936 = or(_T_933, _T_935) @[Fragmenter.scala 204:29] + node _T_937 = or(_T_936, reset) @[Fragmenter.scala 204:14] + node _T_939 = eq(_T_937, UInt<1>("h00")) @[Fragmenter.scala 204:14] + when _T_939 : @[Fragmenter.scala 204:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:204 assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible\n") @[Fragmenter.scala 204:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 204:14] + skip @[Fragmenter.scala 204:14] + _T_899 <= _T_921 @[Fragmenter.scala 207:20] + node _T_941 = eq(_T_899, UInt<1>("h00")) @[Fragmenter.scala 208:37] + node _T_942 = or(_T_941, _T_901) @[Fragmenter.scala 208:51] + node _T_943 = and(io.in.0.w.valid, _T_942) @[Fragmenter.scala 208:33] + io.out.0.w.valid <= _T_943 @[Fragmenter.scala 208:19] + node _T_945 = eq(_T_899, UInt<1>("h00")) @[Fragmenter.scala 209:37] + node _T_946 = or(_T_945, _T_901) @[Fragmenter.scala 209:51] + node _T_947 = and(io.out.0.w.ready, _T_946) @[Fragmenter.scala 209:33] + io.in.0.w.ready <= _T_947 @[Fragmenter.scala 209:18] + io.out.0.w.bits <- io.in.0.w.bits @[Fragmenter.scala 210:18] + io.out.0.w.bits.last <= _T_926 @[Fragmenter.scala 211:23] + node _T_949 = eq(io.out.0.w.valid, UInt<1>("h00")) @[Fragmenter.scala 213:15] + node _T_951 = eq(io.in.0.w.bits.last, UInt<1>("h00")) @[Fragmenter.scala 213:31] + node _T_952 = or(_T_949, _T_951) @[Fragmenter.scala 213:28] + node _T_953 = or(_T_952, _T_926) @[Fragmenter.scala 213:47] + node _T_954 = or(_T_953, reset) @[Fragmenter.scala 213:14] + node _T_956 = eq(_T_954, UInt<1>("h00")) @[Fragmenter.scala 213:14] + when _T_956 : @[Fragmenter.scala 213:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:213 assert (!out_w.valid || !in_w.bits.last || w_last)\n") @[Fragmenter.scala 213:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 213:14] + skip @[Fragmenter.scala 213:14] + node _T_958 = eq(_T_854.bits.last, UInt<1>("h00")) @[Fragmenter.scala 217:37] + node _T_959 = or(_T_958, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 217:45] + node _T_960 = and(_T_854.valid, _T_959) @[Fragmenter.scala 217:33] + io.in.0.r.valid <= _T_960 @[Fragmenter.scala 217:18] + node _T_962 = eq(_T_854.bits.last, UInt<1>("h00")) @[Fragmenter.scala 218:37] + node _T_963 = or(_T_962, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 218:45] + node _T_964 = and(io.in.0.r.ready, _T_963) @[Fragmenter.scala 218:33] + _T_854.ready <= _T_964 @[Fragmenter.scala 218:19] + node _T_965 = and(_T_854.bits.last, _T_854.valid) @[Fragmenter.scala 219:41] + node _T_966 = and(_T_965, io.in.0.r.ready) @[Fragmenter.scala 219:56] + AXI4FragmenterAXI4FragmenterSideband.io.deq.ready <= _T_966 @[Fragmenter.scala 219:31] + io.in.0.r.bits <- _T_854.bits @[Fragmenter.scala 220:17] + node _T_967 = and(_T_854.bits.last, AXI4FragmenterAXI4FragmenterSideband.io.deq.bits) @[Fragmenter.scala 221:32] + io.in.0.r.bits.last <= _T_967 @[Fragmenter.scala 221:22] + node _T_968 = and(_T_869.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid) @[Fragmenter.scala 225:33] + node _T_969 = and(_T_968, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits) @[Fragmenter.scala 225:60] + io.in.0.b.valid <= _T_969 @[Fragmenter.scala 225:18] + node _T_971 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 226:50] + node _T_972 = or(_T_971, io.in.0.b.ready) @[Fragmenter.scala 226:58] + node _T_973 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid, _T_972) @[Fragmenter.scala 226:46] + _T_869.ready <= _T_973 @[Fragmenter.scala 226:19] + node _T_975 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 227:50] + node _T_976 = or(_T_975, io.in.0.b.ready) @[Fragmenter.scala 227:58] + node _T_977 = and(_T_869.valid, _T_976) @[Fragmenter.scala 227:46] + AXI4FragmenterAXI4FragmenterSideband_1.io.deq.ready <= _T_977 @[Fragmenter.scala 227:31] + io.in.0.b.bits <- _T_869.bits @[Fragmenter.scala 228:17] + reg _T_979 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node _T_980 = or(_T_869.bits.resp, _T_979) @[Fragmenter.scala 232:34] + node _T_981 = and(_T_869.ready, _T_869.valid) @[Decoupled.scala 30:37] + when _T_981 : @[Fragmenter.scala 233:27] + node _T_983 = mux(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00"), _T_980) @[Fragmenter.scala 233:42] + _T_979 <= _T_983 @[Fragmenter.scala 233:36] + skip @[Fragmenter.scala 233:27] + io.in.0.b.bits.resp <= _T_980 @[Fragmenter.scala 234:22] + + module Queue_47 : + input clock : Clock input reset : UInt<1> - output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) - node T_44 = bits(io.fromPreMul.highExpA, 2, 1) - node isSpecialA = eq(T_44, UInt<2>("h03")) - node T_47 = bits(io.fromPreMul.highExpA, 0, 0) - node T_49 = eq(T_47, UInt<1>("h00")) - node isInfA = and(isSpecialA, T_49) - node T_51 = bits(io.fromPreMul.highExpA, 0, 0) - node isNaNA = and(isSpecialA, T_51) - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) - node isSigNaNA = and(isNaNA, T_54) - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) - node T_58 = bits(io.fromPreMul.highExpB, 2, 1) - node isSpecialB = eq(T_58, UInt<2>("h03")) - node T_61 = bits(io.fromPreMul.highExpB, 0, 0) - node T_63 = eq(T_61, UInt<1>("h00")) - node isInfB = and(isSpecialB, T_63) - node T_65 = bits(io.fromPreMul.highExpB, 0, 0) - node isNaNB = and(isSpecialB, T_65) - node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) - node isSigNaNB = and(isNaNB, T_68) - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) - node T_72 = bits(io.fromPreMul.highExpC, 2, 1) - node isSpecialC = eq(T_72, UInt<2>("h03")) - node T_75 = bits(io.fromPreMul.highExpC, 0, 0) - node T_77 = eq(T_75, UInt<1>("h00")) - node isInfC = and(isSpecialC, T_77) - node T_79 = bits(io.fromPreMul.highExpC, 0, 0) - node isNaNC = and(isSpecialC, T_79) - node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) - node isSigNaNC = and(isNaNC, T_82) - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_92 = bits(io.mulAddResult, 106, 106) - node T_94 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) - node T_95 = tail(T_94, 1) - node T_96 = mux(T_92, T_95, io.fromPreMul.highAlignedNegSigC) - node T_97 = bits(io.mulAddResult, 105, 0) - node T_98 = cat(T_97, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_96, T_98) - node T_101 = bits(sigSum, 108, 1) - node T_102 = xor(UInt<108>("h00"), T_101) - node T_103 = or(UInt<108>("h00"), T_101) - node T_104 = shl(T_103, 1) - node T_105 = xor(T_102, T_104) - node T_107 = bits(T_105, 107, 0) - node T_108 = bits(T_107, 107, 107) - node T_110 = bits(T_107, 106, 106) - node T_112 = bits(T_107, 105, 105) - node T_114 = bits(T_107, 104, 104) - node T_116 = bits(T_107, 103, 103) - node T_118 = bits(T_107, 102, 102) - node T_120 = bits(T_107, 101, 101) - node T_122 = bits(T_107, 100, 100) - node T_124 = bits(T_107, 99, 99) - node T_126 = bits(T_107, 98, 98) - node T_128 = bits(T_107, 97, 97) - node T_130 = bits(T_107, 96, 96) - node T_132 = bits(T_107, 95, 95) - node T_134 = bits(T_107, 94, 94) - node T_136 = bits(T_107, 93, 93) - node T_138 = bits(T_107, 92, 92) - node T_140 = bits(T_107, 91, 91) - node T_142 = bits(T_107, 90, 90) - node T_144 = bits(T_107, 89, 89) - node T_146 = bits(T_107, 88, 88) - node T_148 = bits(T_107, 87, 87) - node T_150 = bits(T_107, 86, 86) - node T_152 = bits(T_107, 85, 85) - node T_154 = bits(T_107, 84, 84) - node T_156 = bits(T_107, 83, 83) - node T_158 = bits(T_107, 82, 82) - node T_160 = bits(T_107, 81, 81) - node T_162 = bits(T_107, 80, 80) - node T_164 = bits(T_107, 79, 79) - node T_166 = bits(T_107, 78, 78) - node T_168 = bits(T_107, 77, 77) - node T_170 = bits(T_107, 76, 76) - node T_172 = bits(T_107, 75, 75) - node T_174 = bits(T_107, 74, 74) - node T_176 = bits(T_107, 73, 73) - node T_178 = bits(T_107, 72, 72) - node T_180 = bits(T_107, 71, 71) - node T_182 = bits(T_107, 70, 70) - node T_184 = bits(T_107, 69, 69) - node T_186 = bits(T_107, 68, 68) - node T_188 = bits(T_107, 67, 67) - node T_190 = bits(T_107, 66, 66) - node T_192 = bits(T_107, 65, 65) - node T_194 = bits(T_107, 64, 64) - node T_196 = bits(T_107, 63, 63) - node T_198 = bits(T_107, 62, 62) - node T_200 = bits(T_107, 61, 61) - node T_202 = bits(T_107, 60, 60) - node T_204 = bits(T_107, 59, 59) - node T_206 = bits(T_107, 58, 58) - node T_208 = bits(T_107, 57, 57) - node T_210 = bits(T_107, 56, 56) - node T_212 = bits(T_107, 55, 55) - node T_214 = bits(T_107, 54, 54) - node T_216 = bits(T_107, 53, 53) - node T_218 = bits(T_107, 52, 52) - node T_220 = bits(T_107, 51, 51) - node T_222 = bits(T_107, 50, 50) - node T_224 = bits(T_107, 49, 49) - node T_226 = bits(T_107, 48, 48) - node T_228 = bits(T_107, 47, 47) - node T_230 = bits(T_107, 46, 46) - node T_232 = bits(T_107, 45, 45) - node T_234 = bits(T_107, 44, 44) - node T_236 = bits(T_107, 43, 43) - node T_238 = bits(T_107, 42, 42) - node T_240 = bits(T_107, 41, 41) - node T_242 = bits(T_107, 40, 40) - node T_244 = bits(T_107, 39, 39) - node T_246 = bits(T_107, 38, 38) - node T_248 = bits(T_107, 37, 37) - node T_250 = bits(T_107, 36, 36) - node T_252 = bits(T_107, 35, 35) - node T_254 = bits(T_107, 34, 34) - node T_256 = bits(T_107, 33, 33) - node T_258 = bits(T_107, 32, 32) - node T_260 = bits(T_107, 31, 31) - node T_262 = bits(T_107, 30, 30) - node T_264 = bits(T_107, 29, 29) - node T_266 = bits(T_107, 28, 28) - node T_268 = bits(T_107, 27, 27) - node T_270 = bits(T_107, 26, 26) - node T_272 = bits(T_107, 25, 25) - node T_274 = bits(T_107, 24, 24) - node T_276 = bits(T_107, 23, 23) - node T_278 = bits(T_107, 22, 22) - node T_280 = bits(T_107, 21, 21) - node T_282 = bits(T_107, 20, 20) - node T_284 = bits(T_107, 19, 19) - node T_286 = bits(T_107, 18, 18) - node T_288 = bits(T_107, 17, 17) - node T_290 = bits(T_107, 16, 16) - node T_292 = bits(T_107, 15, 15) - node T_294 = bits(T_107, 14, 14) - node T_296 = bits(T_107, 13, 13) - node T_298 = bits(T_107, 12, 12) - node T_300 = bits(T_107, 11, 11) - node T_302 = bits(T_107, 10, 10) - node T_304 = bits(T_107, 9, 9) - node T_306 = bits(T_107, 8, 8) - node T_308 = bits(T_107, 7, 7) - node T_310 = bits(T_107, 6, 6) - node T_312 = bits(T_107, 5, 5) - node T_314 = bits(T_107, 4, 4) - node T_316 = bits(T_107, 3, 3) - node T_318 = bits(T_107, 2, 2) - node T_320 = bits(T_107, 1, 1) - node T_321 = shl(T_320, 0) - node T_322 = mux(T_318, UInt<2>("h02"), T_321) - node T_323 = mux(T_316, UInt<2>("h03"), T_322) - node T_324 = mux(T_314, UInt<3>("h04"), T_323) - node T_325 = mux(T_312, UInt<3>("h05"), T_324) - node T_326 = mux(T_310, UInt<3>("h06"), T_325) - node T_327 = mux(T_308, UInt<3>("h07"), T_326) - node T_328 = mux(T_306, UInt<4>("h08"), T_327) - node T_329 = mux(T_304, UInt<4>("h09"), T_328) - node T_330 = mux(T_302, UInt<4>("h0a"), T_329) - node T_331 = mux(T_300, UInt<4>("h0b"), T_330) - node T_332 = mux(T_298, UInt<4>("h0c"), T_331) - node T_333 = mux(T_296, UInt<4>("h0d"), T_332) - node T_334 = mux(T_294, UInt<4>("h0e"), T_333) - node T_335 = mux(T_292, UInt<4>("h0f"), T_334) - node T_336 = mux(T_290, UInt<5>("h010"), T_335) - node T_337 = mux(T_288, UInt<5>("h011"), T_336) - node T_338 = mux(T_286, UInt<5>("h012"), T_337) - node T_339 = mux(T_284, UInt<5>("h013"), T_338) - node T_340 = mux(T_282, UInt<5>("h014"), T_339) - node T_341 = mux(T_280, UInt<5>("h015"), T_340) - node T_342 = mux(T_278, UInt<5>("h016"), T_341) - node T_343 = mux(T_276, UInt<5>("h017"), T_342) - node T_344 = mux(T_274, UInt<5>("h018"), T_343) - node T_345 = mux(T_272, UInt<5>("h019"), T_344) - node T_346 = mux(T_270, UInt<5>("h01a"), T_345) - node T_347 = mux(T_268, UInt<5>("h01b"), T_346) - node T_348 = mux(T_266, UInt<5>("h01c"), T_347) - node T_349 = mux(T_264, UInt<5>("h01d"), T_348) - node T_350 = mux(T_262, UInt<5>("h01e"), T_349) - node T_351 = mux(T_260, UInt<5>("h01f"), T_350) - node T_352 = mux(T_258, UInt<6>("h020"), T_351) - node T_353 = mux(T_256, UInt<6>("h021"), T_352) - node T_354 = mux(T_254, UInt<6>("h022"), T_353) - node T_355 = mux(T_252, UInt<6>("h023"), T_354) - node T_356 = mux(T_250, UInt<6>("h024"), T_355) - node T_357 = mux(T_248, UInt<6>("h025"), T_356) - node T_358 = mux(T_246, UInt<6>("h026"), T_357) - node T_359 = mux(T_244, UInt<6>("h027"), T_358) - node T_360 = mux(T_242, UInt<6>("h028"), T_359) - node T_361 = mux(T_240, UInt<6>("h029"), T_360) - node T_362 = mux(T_238, UInt<6>("h02a"), T_361) - node T_363 = mux(T_236, UInt<6>("h02b"), T_362) - node T_364 = mux(T_234, UInt<6>("h02c"), T_363) - node T_365 = mux(T_232, UInt<6>("h02d"), T_364) - node T_366 = mux(T_230, UInt<6>("h02e"), T_365) - node T_367 = mux(T_228, UInt<6>("h02f"), T_366) - node T_368 = mux(T_226, UInt<6>("h030"), T_367) - node T_369 = mux(T_224, UInt<6>("h031"), T_368) - node T_370 = mux(T_222, UInt<6>("h032"), T_369) - node T_371 = mux(T_220, UInt<6>("h033"), T_370) - node T_372 = mux(T_218, UInt<6>("h034"), T_371) - node T_373 = mux(T_216, UInt<6>("h035"), T_372) - node T_374 = mux(T_214, UInt<6>("h036"), T_373) - node T_375 = mux(T_212, UInt<6>("h037"), T_374) - node T_376 = mux(T_210, UInt<6>("h038"), T_375) - node T_377 = mux(T_208, UInt<6>("h039"), T_376) - node T_378 = mux(T_206, UInt<6>("h03a"), T_377) - node T_379 = mux(T_204, UInt<6>("h03b"), T_378) - node T_380 = mux(T_202, UInt<6>("h03c"), T_379) - node T_381 = mux(T_200, UInt<6>("h03d"), T_380) - node T_382 = mux(T_198, UInt<6>("h03e"), T_381) - node T_383 = mux(T_196, UInt<6>("h03f"), T_382) - node T_384 = mux(T_194, UInt<7>("h040"), T_383) - node T_385 = mux(T_192, UInt<7>("h041"), T_384) - node T_386 = mux(T_190, UInt<7>("h042"), T_385) - node T_387 = mux(T_188, UInt<7>("h043"), T_386) - node T_388 = mux(T_186, UInt<7>("h044"), T_387) - node T_389 = mux(T_184, UInt<7>("h045"), T_388) - node T_390 = mux(T_182, UInt<7>("h046"), T_389) - node T_391 = mux(T_180, UInt<7>("h047"), T_390) - node T_392 = mux(T_178, UInt<7>("h048"), T_391) - node T_393 = mux(T_176, UInt<7>("h049"), T_392) - node T_394 = mux(T_174, UInt<7>("h04a"), T_393) - node T_395 = mux(T_172, UInt<7>("h04b"), T_394) - node T_396 = mux(T_170, UInt<7>("h04c"), T_395) - node T_397 = mux(T_168, UInt<7>("h04d"), T_396) - node T_398 = mux(T_166, UInt<7>("h04e"), T_397) - node T_399 = mux(T_164, UInt<7>("h04f"), T_398) - node T_400 = mux(T_162, UInt<7>("h050"), T_399) - node T_401 = mux(T_160, UInt<7>("h051"), T_400) - node T_402 = mux(T_158, UInt<7>("h052"), T_401) - node T_403 = mux(T_156, UInt<7>("h053"), T_402) - node T_404 = mux(T_154, UInt<7>("h054"), T_403) - node T_405 = mux(T_152, UInt<7>("h055"), T_404) - node T_406 = mux(T_150, UInt<7>("h056"), T_405) - node T_407 = mux(T_148, UInt<7>("h057"), T_406) - node T_408 = mux(T_146, UInt<7>("h058"), T_407) - node T_409 = mux(T_144, UInt<7>("h059"), T_408) - node T_410 = mux(T_142, UInt<7>("h05a"), T_409) - node T_411 = mux(T_140, UInt<7>("h05b"), T_410) - node T_412 = mux(T_138, UInt<7>("h05c"), T_411) - node T_413 = mux(T_136, UInt<7>("h05d"), T_412) - node T_414 = mux(T_134, UInt<7>("h05e"), T_413) - node T_415 = mux(T_132, UInt<7>("h05f"), T_414) - node T_416 = mux(T_130, UInt<7>("h060"), T_415) - node T_417 = mux(T_128, UInt<7>("h061"), T_416) - node T_418 = mux(T_126, UInt<7>("h062"), T_417) - node T_419 = mux(T_124, UInt<7>("h063"), T_418) - node T_420 = mux(T_122, UInt<7>("h064"), T_419) - node T_421 = mux(T_120, UInt<7>("h065"), T_420) - node T_422 = mux(T_118, UInt<7>("h066"), T_421) - node T_423 = mux(T_116, UInt<7>("h067"), T_422) - node T_424 = mux(T_114, UInt<7>("h068"), T_423) - node T_425 = mux(T_112, UInt<7>("h069"), T_424) - node T_426 = mux(T_110, UInt<7>("h06a"), T_425) - node T_427 = mux(T_108, UInt<7>("h06b"), T_426) - node T_428 = sub(UInt<8>("h0a0"), T_427) - node estNormPos_dist = tail(T_428, 1) - node T_430 = bits(sigSum, 75, 44) - node T_432 = neq(T_430, UInt<1>("h00")) - node T_433 = bits(sigSum, 43, 0) - node T_435 = neq(T_433, UInt<1>("h00")) - node firstReduceSigSum = cat(T_432, T_435) - node notSigSum = not(sigSum) - node T_438 = bits(notSigSum, 75, 44) - node T_440 = neq(T_438, UInt<1>("h00")) - node T_441 = bits(notSigSum, 43, 0) - node T_443 = neq(T_441, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_440, T_443) - node T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) - node T_448 = tail(T_447, 1) - node T_449 = bits(T_448, 5, 0) - node CDom_estNormDist = mux(T_445, io.fromPreMul.CAlignDist, T_449) - node T_451 = not(doSubMags) - node T_452 = bits(CDom_estNormDist, 5, 5) - node T_453 = not(T_452) - node T_454 = and(T_451, T_453) - node T_455 = asSInt(T_454) - node T_456 = bits(sigSum, 161, 76) - node T_458 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_459 = cat(T_456, T_458) - node T_460 = asSInt(T_459) - node T_461 = and(T_455, T_460) - node T_462 = asSInt(T_461) - node T_463 = not(doSubMags) - node T_464 = bits(CDom_estNormDist, 5, 5) - node T_465 = and(T_463, T_464) - node T_466 = asSInt(T_465) - node T_467 = bits(sigSum, 129, 44) - node T_468 = bits(firstReduceSigSum, 0, 0) - node T_469 = cat(T_467, T_468) - node T_470 = asSInt(T_469) - node T_471 = and(T_466, T_470) - node T_472 = asSInt(T_471) - node T_473 = or(T_462, T_472) - node T_474 = asSInt(T_473) - node T_475 = bits(CDom_estNormDist, 5, 5) - node T_476 = not(T_475) - node T_477 = and(doSubMags, T_476) - node T_478 = asSInt(T_477) - node T_479 = bits(notSigSum, 161, 76) - node T_481 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_482 = cat(T_479, T_481) - node T_483 = asSInt(T_482) - node T_484 = and(T_478, T_483) - node T_485 = asSInt(T_484) - node T_486 = or(T_474, T_485) - node T_487 = asSInt(T_486) - node T_488 = bits(CDom_estNormDist, 5, 5) - node T_489 = and(doSubMags, T_488) - node T_490 = asSInt(T_489) - node T_491 = bits(notSigSum, 129, 44) - node T_492 = bits(firstReduceNotSigSum, 0, 0) - node T_493 = cat(T_491, T_492) - node T_494 = asSInt(T_493) - node T_495 = and(T_490, T_494) - node T_496 = asSInt(T_495) - node T_497 = or(T_487, T_496) - node T_498 = asSInt(T_497) - node CDom_firstNormAbsSigSum = asUInt(T_498) - node T_500 = bits(sigSum, 108, 44) - node T_501 = bits(firstReduceNotSigSum, 0, 0) - node T_502 = not(T_501) - node T_503 = bits(firstReduceSigSum, 0, 0) - node T_504 = mux(doSubMags, T_502, T_503) - node T_505 = cat(T_500, T_504) - node T_506 = bits(sigSum, 97, 1) - node T_507 = bits(estNormPos_dist, 4, 4) - node T_508 = bits(sigSum, 1, 1) - node T_510 = sub(UInt<86>("h00"), doSubMags) - node T_511 = tail(T_510, 1) - node T_512 = cat(T_508, T_511) - node T_513 = mux(T_507, T_505, T_512) - node T_514 = bits(sigSum, 97, 12) - node T_515 = bits(notSigSum, 11, 1) - node T_517 = eq(T_515, UInt<1>("h00")) - node T_518 = bits(sigSum, 11, 1) - node T_520 = neq(T_518, UInt<1>("h00")) - node T_521 = mux(doSubMags, T_517, T_520) - node T_522 = cat(T_514, T_521) - node T_523 = bits(estNormPos_dist, 6, 6) - node T_524 = bits(estNormPos_dist, 5, 5) - node T_525 = bits(sigSum, 65, 1) - node T_527 = sub(UInt<22>("h00"), doSubMags) - node T_528 = tail(T_527, 1) - node T_529 = cat(T_525, T_528) - node T_530 = mux(T_524, T_529, T_522) - node T_531 = bits(estNormPos_dist, 5, 5) - node T_532 = bits(sigSum, 33, 1) - node T_534 = sub(UInt<54>("h00"), doSubMags) - node T_535 = tail(T_534, 1) - node T_536 = cat(T_532, T_535) - node T_537 = mux(T_531, T_513, T_536) - node notCDom_pos_firstNormAbsSigSum = mux(T_523, T_530, T_537) - node T_539 = bits(notSigSum, 107, 44) - node T_540 = bits(firstReduceNotSigSum, 0, 0) - node T_541 = cat(T_539, T_540) - node T_542 = bits(notSigSum, 97, 1) - node T_543 = bits(estNormPos_dist, 4, 4) - node T_544 = bits(notSigSum, 2, 1) - node T_546 = dshl(T_544, UInt<7>("h056")) - node T_547 = mux(T_543, T_541, T_546) - node T_548 = bits(notSigSum, 98, 12) - node T_549 = bits(notSigSum, 11, 1) - node T_551 = neq(T_549, UInt<1>("h00")) - node T_552 = cat(T_548, T_551) - node T_553 = bits(estNormPos_dist, 6, 6) - node T_554 = bits(estNormPos_dist, 5, 5) - node T_555 = bits(notSigSum, 66, 1) - node T_557 = dshl(T_555, UInt<5>("h016")) - node T_558 = mux(T_554, T_557, T_552) - node T_559 = bits(estNormPos_dist, 5, 5) - node T_560 = bits(notSigSum, 34, 1) - node T_562 = dshl(T_560, UInt<6>("h036")) - node T_563 = mux(T_559, T_547, T_562) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_553, T_558, T_563) - node notCDom_signSigSum = bits(sigSum, 109, 109) - node T_566 = not(isZeroC) - node T_567 = and(doSubMags, T_566) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_567, notCDom_signSigSum) - node T_569 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_569) - node T_571 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_572 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_571, T_572) - node T_574 = not(io.fromPreMul.isCDominant) - node T_575 = not(notCDom_signSigSum) - node T_576 = and(T_574, T_575) - node doIncrSig = and(T_576, doSubMags) - node estNormDist_5 = bits(estNormDist, 4, 0) - node normTo2ShiftDist = not(estNormDist_5) - node T_581 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) - node T_582 = bits(T_581, 31, 1) - node T_583 = bits(T_582, 15, 0) - node T_586 = shl(UInt<8>("h0ff"), 8) - node T_587 = xor(UInt<16>("h0ffff"), T_586) - node T_588 = shr(T_583, 8) - node T_589 = and(T_588, T_587) - node T_590 = bits(T_583, 7, 0) - node T_591 = shl(T_590, 8) - node T_592 = not(T_587) - node T_593 = and(T_591, T_592) - node T_594 = or(T_589, T_593) - node T_595 = bits(T_587, 11, 0) - node T_596 = shl(T_595, 4) - node T_597 = xor(T_587, T_596) - node T_598 = shr(T_594, 4) - node T_599 = and(T_598, T_597) - node T_600 = bits(T_594, 11, 0) - node T_601 = shl(T_600, 4) - node T_602 = not(T_597) - node T_603 = and(T_601, T_602) - node T_604 = or(T_599, T_603) - node T_605 = bits(T_597, 13, 0) - node T_606 = shl(T_605, 2) - node T_607 = xor(T_597, T_606) - node T_608 = shr(T_604, 2) - node T_609 = and(T_608, T_607) - node T_610 = bits(T_604, 13, 0) - node T_611 = shl(T_610, 2) - node T_612 = not(T_607) - node T_613 = and(T_611, T_612) - node T_614 = or(T_609, T_613) - node T_615 = bits(T_607, 14, 0) - node T_616 = shl(T_615, 1) - node T_617 = xor(T_607, T_616) - node T_618 = shr(T_614, 1) - node T_619 = and(T_618, T_617) - node T_620 = bits(T_614, 14, 0) - node T_621 = shl(T_620, 1) - node T_622 = not(T_617) - node T_623 = and(T_621, T_622) - node T_624 = or(T_619, T_623) - node T_625 = bits(T_582, 30, 16) - node T_626 = bits(T_625, 7, 0) - node T_629 = shl(UInt<4>("h0f"), 4) - node T_630 = xor(UInt<8>("h0ff"), T_629) - node T_631 = shr(T_626, 4) - node T_632 = and(T_631, T_630) - node T_633 = bits(T_626, 3, 0) - node T_634 = shl(T_633, 4) - node T_635 = not(T_630) - node T_636 = and(T_634, T_635) - node T_637 = or(T_632, T_636) - node T_638 = bits(T_630, 5, 0) - node T_639 = shl(T_638, 2) - node T_640 = xor(T_630, T_639) - node T_641 = shr(T_637, 2) - node T_642 = and(T_641, T_640) - node T_643 = bits(T_637, 5, 0) - node T_644 = shl(T_643, 2) - node T_645 = not(T_640) - node T_646 = and(T_644, T_645) - node T_647 = or(T_642, T_646) - node T_648 = bits(T_640, 6, 0) - node T_649 = shl(T_648, 1) - node T_650 = xor(T_640, T_649) - node T_651 = shr(T_647, 1) - node T_652 = and(T_651, T_650) - node T_653 = bits(T_647, 6, 0) - node T_654 = shl(T_653, 1) - node T_655 = not(T_650) - node T_656 = and(T_654, T_655) - node T_657 = or(T_652, T_656) - node T_658 = bits(T_625, 14, 8) - node T_659 = bits(T_658, 3, 0) - node T_660 = bits(T_659, 1, 0) - node T_661 = bits(T_660, 0, 0) - node T_662 = bits(T_660, 1, 1) - node T_663 = cat(T_661, T_662) - node T_664 = bits(T_659, 3, 2) - node T_665 = bits(T_664, 0, 0) - node T_666 = bits(T_664, 1, 1) - node T_667 = cat(T_665, T_666) - node T_668 = cat(T_663, T_667) - node T_669 = bits(T_658, 6, 4) - node T_670 = bits(T_669, 1, 0) - node T_671 = bits(T_670, 0, 0) - node T_672 = bits(T_670, 1, 1) - node T_673 = cat(T_671, T_672) - node T_674 = bits(T_669, 2, 2) - node T_675 = cat(T_673, T_674) - node T_676 = cat(T_668, T_675) - node T_677 = cat(T_657, T_676) - node T_678 = cat(T_624, T_677) - node absSigSumExtraMask = cat(T_678, UInt<1>("h01")) - node T_681 = bits(cFirstNormAbsSigSum, 87, 1) - node T_682 = dshr(T_681, normTo2ShiftDist) - node T_683 = bits(cFirstNormAbsSigSum, 31, 0) - node T_684 = not(T_683) - node T_685 = and(T_684, absSigSumExtraMask) - node T_687 = eq(T_685, UInt<1>("h00")) - node T_688 = bits(cFirstNormAbsSigSum, 31, 0) - node T_689 = and(T_688, absSigSumExtraMask) - node T_691 = neq(T_689, UInt<1>("h00")) - node T_692 = mux(doIncrSig, T_687, T_691) - node T_693 = cat(T_682, T_692) - node sigX3 = bits(T_693, 56, 0) - node T_695 = bits(sigX3, 56, 55) - node sigX3Shift1 = eq(T_695, UInt<1>("h00")) - node T_698 = sub(io.fromPreMul.sExpSum, estNormDist) - node sExpX3 = tail(T_698, 1) - node T_700 = bits(sigX3, 56, 54) - node isZeroY = eq(T_700, UInt<1>("h00")) - node T_703 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_703) - node sExpX3_13 = bits(sExpX3, 12, 0) - node T_706 = bits(sExpX3, 13, 13) - node T_708 = sub(UInt<56>("h00"), T_706) - node T_709 = tail(T_708, 1) - node T_710 = not(sExpX3_13) - node T_712 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_710) - node T_713 = bits(T_712, 1027, 974) - node T_714 = bits(T_713, 31, 0) - node T_717 = shl(UInt<16>("h0ffff"), 16) - node T_718 = xor(UInt<32>("h0ffffffff"), T_717) - node T_719 = shr(T_714, 16) - node T_720 = and(T_719, T_718) - node T_721 = bits(T_714, 15, 0) - node T_722 = shl(T_721, 16) - node T_723 = not(T_718) - node T_724 = and(T_722, T_723) - node T_725 = or(T_720, T_724) - node T_726 = bits(T_718, 23, 0) - node T_727 = shl(T_726, 8) - node T_728 = xor(T_718, T_727) - node T_729 = shr(T_725, 8) - node T_730 = and(T_729, T_728) - node T_731 = bits(T_725, 23, 0) - node T_732 = shl(T_731, 8) - node T_733 = not(T_728) - node T_734 = and(T_732, T_733) - node T_735 = or(T_730, T_734) - node T_736 = bits(T_728, 27, 0) - node T_737 = shl(T_736, 4) - node T_738 = xor(T_728, T_737) - node T_739 = shr(T_735, 4) - node T_740 = and(T_739, T_738) - node T_741 = bits(T_735, 27, 0) - node T_742 = shl(T_741, 4) - node T_743 = not(T_738) - node T_744 = and(T_742, T_743) - node T_745 = or(T_740, T_744) - node T_746 = bits(T_738, 29, 0) - node T_747 = shl(T_746, 2) - node T_748 = xor(T_738, T_747) - node T_749 = shr(T_745, 2) - node T_750 = and(T_749, T_748) - node T_751 = bits(T_745, 29, 0) - node T_752 = shl(T_751, 2) - node T_753 = not(T_748) - node T_754 = and(T_752, T_753) - node T_755 = or(T_750, T_754) - node T_756 = bits(T_748, 30, 0) - node T_757 = shl(T_756, 1) - node T_758 = xor(T_748, T_757) - node T_759 = shr(T_755, 1) - node T_760 = and(T_759, T_758) - node T_761 = bits(T_755, 30, 0) - node T_762 = shl(T_761, 1) - node T_763 = not(T_758) - node T_764 = and(T_762, T_763) - node T_765 = or(T_760, T_764) - node T_766 = bits(T_713, 53, 32) - node T_767 = bits(T_766, 15, 0) - node T_770 = shl(UInt<8>("h0ff"), 8) - node T_771 = xor(UInt<16>("h0ffff"), T_770) - node T_772 = shr(T_767, 8) - node T_773 = and(T_772, T_771) - node T_774 = bits(T_767, 7, 0) - node T_775 = shl(T_774, 8) - node T_776 = not(T_771) - node T_777 = and(T_775, T_776) - node T_778 = or(T_773, T_777) - node T_779 = bits(T_771, 11, 0) - node T_780 = shl(T_779, 4) - node T_781 = xor(T_771, T_780) - node T_782 = shr(T_778, 4) - node T_783 = and(T_782, T_781) - node T_784 = bits(T_778, 11, 0) - node T_785 = shl(T_784, 4) - node T_786 = not(T_781) - node T_787 = and(T_785, T_786) - node T_788 = or(T_783, T_787) - node T_789 = bits(T_781, 13, 0) - node T_790 = shl(T_789, 2) - node T_791 = xor(T_781, T_790) - node T_792 = shr(T_788, 2) - node T_793 = and(T_792, T_791) - node T_794 = bits(T_788, 13, 0) - node T_795 = shl(T_794, 2) - node T_796 = not(T_791) - node T_797 = and(T_795, T_796) - node T_798 = or(T_793, T_797) - node T_799 = bits(T_791, 14, 0) - node T_800 = shl(T_799, 1) - node T_801 = xor(T_791, T_800) - node T_802 = shr(T_798, 1) - node T_803 = and(T_802, T_801) - node T_804 = bits(T_798, 14, 0) - node T_805 = shl(T_804, 1) - node T_806 = not(T_801) - node T_807 = and(T_805, T_806) - node T_808 = or(T_803, T_807) - node T_809 = bits(T_766, 21, 16) - node T_810 = bits(T_809, 3, 0) - node T_811 = bits(T_810, 1, 0) - node T_812 = bits(T_811, 0, 0) - node T_813 = bits(T_811, 1, 1) - node T_814 = cat(T_812, T_813) - node T_815 = bits(T_810, 3, 2) - node T_816 = bits(T_815, 0, 0) - node T_817 = bits(T_815, 1, 1) - node T_818 = cat(T_816, T_817) - node T_819 = cat(T_814, T_818) - node T_820 = bits(T_809, 5, 4) - node T_821 = bits(T_820, 0, 0) - node T_822 = bits(T_820, 1, 1) - node T_823 = cat(T_821, T_822) - node T_824 = cat(T_819, T_823) - node T_825 = cat(T_808, T_824) - node T_826 = cat(T_765, T_825) - node T_827 = bits(sigX3, 55, 55) - node T_828 = or(T_826, T_827) - node T_830 = cat(T_828, UInt<2>("h03")) - node roundMask = or(T_709, T_830) - node T_832 = shr(roundMask, 1) - node T_833 = not(T_832) - node roundPosMask = and(T_833, roundMask) - node T_835 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_835, UInt<1>("h00")) - node T_838 = shr(roundMask, 1) - node T_839 = and(sigX3, T_838) - node anyRoundExtra = neq(T_839, UInt<1>("h00")) - node T_842 = not(sigX3) - node T_843 = shr(roundMask, 1) - node T_844 = and(T_842, T_843) - node allRoundExtra = eq(T_844, UInt<1>("h00")) - node anyRound = or(roundPosBit, anyRoundExtra) - node allRound = and(roundPosBit, allRoundExtra) - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_850 = not(doIncrSig) - node T_851 = and(T_850, roundingMode_nearest_even) - node T_852 = and(T_851, roundPosBit) - node T_853 = and(T_852, anyRoundExtra) - node T_854 = not(doIncrSig) - node T_855 = and(T_854, roundDirectUp) - node T_856 = and(T_855, anyRound) - node T_857 = or(T_853, T_856) - node T_858 = and(doIncrSig, allRound) - node T_859 = or(T_857, T_858) - node T_860 = and(doIncrSig, roundingMode_nearest_even) - node T_861 = and(T_860, roundPosBit) - node T_862 = or(T_859, T_861) - node T_863 = and(doIncrSig, roundDirectUp) - node T_865 = and(T_863, UInt<1>("h01")) - node roundUp = or(T_862, T_865) - node T_867 = not(roundPosBit) - node T_868 = and(roundingMode_nearest_even, T_867) - node T_869 = and(T_868, allRoundExtra) - node T_870 = and(roundingMode_nearest_even, roundPosBit) - node T_871 = not(anyRoundExtra) - node T_872 = and(T_870, T_871) - node roundEven = mux(doIncrSig, T_869, T_872) - node T_874 = not(allRound) - node roundInexact = mux(doIncrSig, T_874, anyRound) - node T_876 = or(sigX3, roundMask) - node T_877 = shr(T_876, 2) - node T_879 = add(T_877, UInt<1>("h01")) - node T_880 = tail(T_879, 1) - node roundUp_sigY3 = bits(T_880, 54, 0) - node T_882 = not(roundUp) - node T_883 = not(roundEven) - node T_884 = and(T_882, T_883) - node T_885 = bits(T_884, 0, 0) - node T_886 = not(roundMask) - node T_887 = and(sigX3, T_886) - node T_888 = shr(T_887, 2) - node T_890 = mux(T_885, T_888, UInt<1>("h00")) - node T_891 = bits(roundUp, 0, 0) - node T_893 = mux(T_891, roundUp_sigY3, UInt<1>("h00")) - node T_894 = or(T_890, T_893) - node T_895 = shr(roundMask, 1) - node T_896 = not(T_895) - node T_897 = and(roundUp_sigY3, T_896) - node T_899 = mux(roundEven, T_897, UInt<1>("h00")) - node sigY3 = or(T_894, T_899) - node T_901 = bits(sigY3, 54, 54) - node T_903 = add(sExpX3, UInt<1>("h01")) - node T_904 = tail(T_903, 1) - node T_906 = mux(T_901, T_904, UInt<1>("h00")) - node T_907 = bits(sigY3, 53, 53) - node T_909 = mux(T_907, sExpX3, UInt<1>("h00")) - node T_910 = or(T_906, T_909) - node T_911 = bits(sigY3, 54, 53) - node T_913 = eq(T_911, UInt<1>("h00")) - node T_915 = sub(sExpX3, UInt<1>("h01")) - node T_916 = tail(T_915, 1) - node T_918 = mux(T_913, T_916, UInt<1>("h00")) - node sExpY = or(T_910, T_918) - node expY = bits(sExpY, 11, 0) - node T_921 = bits(sigY3, 51, 0) - node T_922 = bits(sigY3, 52, 1) - node fractY = mux(sigX3Shift1, T_921, T_922) - node T_924 = bits(sExpY, 12, 10) - node overflowY = eq(T_924, UInt<2>("h03")) - node T_927 = not(isZeroY) - node T_928 = bits(sExpY, 12, 12) - node T_929 = bits(sExpY, 11, 0) - node T_931 = lt(T_929, UInt<10>("h03ce")) - node T_932 = or(T_928, T_931) - node totalUnderflowY = and(T_927, T_932) - node T_934 = bits(sExpX3, 13, 13) - node T_937 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) - node T_938 = leq(sExpX3_13, T_937) - node T_939 = or(T_934, T_938) - node underflowY = and(roundInexact, T_939) - node T_941 = and(roundingMode_min, signY) - node T_942 = not(signY) - node T_943 = and(roundingMode_max, T_942) - node roundMagUp = or(T_941, T_943) - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node mulSpecial = or(isSpecialA, isSpecialB) - node addSpecial = or(mulSpecial, isSpecialC) - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_949 = not(addSpecial) - node T_950 = not(notSpecial_addZeros) - node commonCase = and(T_949, T_950) - node T_952 = and(isInfA, isZeroB) - node T_953 = and(isZeroA, isInfB) - node T_954 = or(T_952, T_953) - node T_955 = not(isNaNA) - node T_956 = not(isNaNB) - node T_957 = and(T_955, T_956) - node T_958 = or(isInfA, isInfB) - node T_959 = and(T_957, T_958) - node T_960 = and(T_959, isInfC) - node T_961 = and(T_960, doSubMags) - node notSigNaN_invalid = or(T_954, T_961) - node T_963 = or(isSigNaNA, isSigNaNB) - node T_964 = or(T_963, isSigNaNC) - node invalid = or(T_964, notSigNaN_invalid) - node overflow = and(commonCase, overflowY) - node underflow = and(commonCase, underflowY) - node T_968 = and(commonCase, roundInexact) - node inexact = or(overflow, T_968) - node T_970 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_970, totalUnderflowY) - node T_972 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_972, roundMagUp) - node T_974 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_974) - node T_976 = or(isInfA, isInfB) - node T_977 = or(T_976, isInfC) - node T_978 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_977, T_978) - node T_980 = or(isNaNA, isNaNB) - node T_981 = or(T_980, isNaNC) - node isNaNOut = or(T_981, notSigNaN_invalid) - node T_984 = eq(doSubMags, UInt<1>("h00")) - node T_985 = and(T_984, io.fromPreMul.opSignC) - node T_987 = eq(isSpecialC, UInt<1>("h00")) - node T_988 = and(mulSpecial, T_987) - node T_989 = and(T_988, io.fromPreMul.signProd) - node T_990 = or(T_985, T_989) - node T_992 = eq(mulSpecial, UInt<1>("h00")) - node T_993 = and(T_992, isSpecialC) - node T_994 = and(T_993, io.fromPreMul.opSignC) - node T_995 = or(T_990, T_994) - node T_997 = eq(mulSpecial, UInt<1>("h00")) - node T_998 = and(T_997, notSpecial_addZeros) - node T_999 = and(T_998, doSubMags) - node T_1000 = and(T_999, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_995, T_1000) - node T_1003 = eq(isNaNOut, UInt<1>("h00")) - node T_1004 = and(T_1003, uncommonCaseSignOut) - node T_1005 = and(commonCase, signY) - node signOut = or(T_1004, T_1005) - node T_1009 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) - node T_1010 = not(T_1009) - node T_1011 = and(expY, T_1010) - node T_1013 = not(UInt<12>("h03ce")) - node T_1015 = mux(pegMinFiniteMagOut, T_1013, UInt<12>("h00")) - node T_1016 = not(T_1015) - node T_1017 = and(T_1011, T_1016) - node T_1020 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) - node T_1021 = not(T_1020) - node T_1022 = and(T_1017, T_1021) - node T_1025 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) - node T_1026 = not(T_1025) - node T_1027 = and(T_1022, T_1026) - node T_1030 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) - node T_1031 = or(T_1027, T_1030) - node T_1034 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) - node T_1035 = or(T_1031, T_1034) - node T_1038 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) - node T_1039 = or(T_1035, T_1038) - node T_1042 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) - node expOut = or(T_1039, T_1042) - node T_1044 = and(totalUnderflowY, roundMagUp) - node T_1045 = or(T_1044, isNaNOut) - node T_1047 = mux(T_1045, UInt<1>("h00"), fractY) - node T_1048 = shl(isNaNOut, 51) - node T_1049 = or(T_1047, T_1048) - node T_1051 = sub(UInt<52>("h00"), pegMaxFiniteMagOut) - node T_1052 = tail(T_1051, 1) - node fractOut = or(T_1049, T_1052) - node T_1054 = cat(expOut, fractOut) - node T_1055 = cat(signOut, T_1054) - io.out <= T_1055 - node T_1057 = cat(invalid, UInt<1>("h00")) - node T_1058 = cat(underflow, inexact) - node T_1059 = cat(overflow, T_1058) - node T_1060 = cat(T_1057, T_1059) - io.exceptionFlags <= T_1060 - - module MulAddRecFN_114 : - input clk : Clock + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_48 : + input clock : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<2>} io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul_115 - mulAddRecFN_preMul.io is invalid - mulAddRecFN_preMul.clk <= clk - mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul_116 - mulAddRecFN_postMul.io is invalid - mulAddRecFN_postMul.clk <= clk - mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op - mulAddRecFN_preMul.io.a <= io.a - mulAddRecFN_preMul.io.b <= io.b - mulAddRecFN_preMul.io.c <= io.c - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) - node T_17 = add(T_14, T_16) - node T_18 = tail(T_17, 1) - mulAddRecFN_postMul.io.mulAddResult <= T_18 - io.out <= mulAddRecFN_postMul.io.out - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags - - module FPUFMAPipe_113 : - input clk : Clock + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_50 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_52 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_53 = and(_T_50, _T_52) @[Decoupled.scala 188:33] + node _T_54 = and(_T_50, maybe_full) @[Decoupled.scala 189:32] + node _T_55 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_55 + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_56 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_57 = ram[value], clock + _T_57 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_63 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_64 = tail(_T_63, 1) @[Counter.scala 26:22] + value <= _T_64 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_67 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_68 = tail(_T_67, 1) @[Counter.scala 26:22] + value_1 <= _T_68 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_69 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_69 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_71 = eq(_T_53, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_71 @[Decoupled.scala 204:16] + node _T_73 = eq(_T_54, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_73 @[Decoupled.scala 205:16] + infer mport _T_74 = ram[value_1], clock + io.deq.bits <- _T_74 @[Decoupled.scala 206:15] + node _T_78 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_79 = asUInt(_T_78) @[Decoupled.scala 221:40] + node _T_80 = tail(_T_79, 1) @[Decoupled.scala 221:40] + node _T_81 = and(maybe_full, _T_50) @[Decoupled.scala 223:32] + node _T_82 = cat(_T_81, _T_80) @[Cat.scala 30:58] + io.count <= _T_82 @[Decoupled.scala 223:14] + + module Queue_49 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - - io is invalid - node one = shl(UInt<1>("h01"), 63) - node T_136 = bits(io.in.bits.in1, 64, 64) - node T_137 = bits(io.in.bits.in2, 64, 64) - node T_138 = xor(T_136, T_137) - node zero = shl(T_138, 64) - reg valid : UInt<1>, clk - valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : - in <- io.in.bits - node T_187 = bits(io.in.bits.cmd, 1, 1) - node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_189 = and(T_187, T_188) - node T_190 = bits(io.in.bits.cmd, 0, 0) - node T_191 = cat(T_189, T_190) - in.cmd <= T_191 - when io.in.bits.swap23 : - in.in2 <= one - skip - node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) - node T_194 = eq(T_192, UInt<1>("h00")) - when T_194 : - in.in3 <= zero - skip - skip - inst fma of MulAddRecFN_114 - fma.io is invalid - fma.clk <= clk - fma.reset <= reset - fma.io.op <= in.cmd - fma.io.roundingMode <= in.rm - fma.io.a <= in.in1 - fma.io.b <= in.in2 - fma.io.c <= in.in3 - wire res : {data : UInt<65>, exc : UInt<5>} - res is invalid - node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_204 = cat(T_203, fma.io.out) - res.data <= T_204 - res.exc <= fma.io.exceptionFlags - reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_207 <= valid - reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk - when valid : - T_208 <- res - skip - reg T_213 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_213 <= T_207 - reg T_214 : {data : UInt<65>, exc : UInt<5>}, clk - when T_207 : - T_214 <- T_208 - skip - wire T_225 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_225 is invalid - T_225.valid <= T_213 - T_225.bits <- T_214 - io.out <- T_225 + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<2>} - module RecFNToRecFN : - input clk : Clock + io is invalid + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] + + module Queue_50 : + input clock : Clock input reset : UInt<1> - output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} io is invalid - node T_8 = bits(io.in, 31, 23) - node T_9 = bits(T_8, 8, 7) - node T_11 = eq(T_9, UInt<2>("h03")) - wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - T_19 is invalid - node T_26 = bits(io.in, 32, 32) - T_19.sign <= T_26 - node T_27 = bits(T_8, 6, 6) - node T_28 = and(T_11, T_27) - T_19.isNaN <= T_28 - node T_29 = bits(T_8, 6, 6) - node T_31 = eq(T_29, UInt<1>("h00")) - node T_32 = and(T_11, T_31) - T_19.isInf <= T_32 - node T_33 = bits(T_8, 8, 6) - node T_35 = eq(T_33, UInt<1>("h00")) - T_19.isZero <= T_35 - node T_36 = cvt(T_8) - T_19.sExp <= T_36 - node T_38 = bits(io.in, 22, 0) - node T_40 = cat(T_38, UInt<2>("h00")) - node T_41 = cat(UInt<2>("h01"), T_40) - T_19.sig <= T_41 - node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0700"))) - node T_44 = tail(T_43, 1) - node T_45 = asSInt(T_44) - wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - outRawFloat is invalid - outRawFloat.sign <= T_19.sign - outRawFloat.isNaN <= T_19.isNaN - outRawFloat.isInf <= T_19.isInf - outRawFloat.isZero <= T_19.isZero - outRawFloat.sExp <= T_45 - node T_60 = shl(T_19.sig, 29) - outRawFloat.sig <= T_60 - node T_61 = bits(outRawFloat.sig, 53, 53) - node T_63 = eq(T_61, UInt<1>("h00")) - node invalidExc = and(outRawFloat.isNaN, T_63) - node T_65 = not(outRawFloat.isNaN) - node T_66 = and(outRawFloat.sign, T_65) - node T_67 = bits(outRawFloat.sExp, 11, 0) - node T_70 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) - node T_71 = not(T_70) - node T_72 = and(T_67, T_71) - node T_73 = or(outRawFloat.isZero, outRawFloat.isInf) - node T_76 = mux(T_73, UInt<12>("h0200"), UInt<1>("h00")) - node T_77 = not(T_76) - node T_78 = and(T_72, T_77) - node T_81 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) - node T_82 = or(T_78, T_81) - node T_85 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) - node T_86 = or(T_82, T_85) - node T_88 = bits(outRawFloat.sig, 53, 2) - node T_89 = mux(outRawFloat.isNaN, UInt<52>("h08000000000000"), T_88) - node T_90 = cat(T_86, T_89) - node T_91 = cat(T_66, T_90) - io.out <= T_91 - node T_93 = cat(invalidExc, UInt<4>("h00")) - io.exceptionFlags <= T_93 + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] - module CompareRecFN : - input clk : Clock + module Queue_51 : + input clock : Clock input reset : UInt<1> - output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, count : UInt<2>} io is invalid - node T_11 = bits(io.a, 63, 52) - node T_12 = bits(T_11, 11, 10) - node T_14 = eq(T_12, UInt<2>("h03")) - wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawA is invalid - node T_29 = bits(io.a, 64, 64) - rawA.sign <= T_29 - node T_30 = bits(T_11, 9, 9) - node T_31 = and(T_14, T_30) - rawA.isNaN <= T_31 - node T_32 = bits(T_11, 9, 9) - node T_34 = eq(T_32, UInt<1>("h00")) - node T_35 = and(T_14, T_34) - rawA.isInf <= T_35 - node T_36 = bits(T_11, 11, 9) - node T_38 = eq(T_36, UInt<1>("h00")) - rawA.isZero <= T_38 - node T_39 = cvt(T_11) - rawA.sExp <= T_39 - node T_41 = bits(io.a, 51, 0) - node T_43 = cat(T_41, UInt<2>("h00")) - node T_44 = cat(UInt<2>("h01"), T_43) - rawA.sig <= T_44 - node T_45 = bits(io.b, 63, 52) - node T_46 = bits(T_45, 11, 10) - node T_48 = eq(T_46, UInt<2>("h03")) - wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawB is invalid - node T_63 = bits(io.b, 64, 64) - rawB.sign <= T_63 - node T_64 = bits(T_45, 9, 9) - node T_65 = and(T_48, T_64) - rawB.isNaN <= T_65 - node T_66 = bits(T_45, 9, 9) - node T_68 = eq(T_66, UInt<1>("h00")) - node T_69 = and(T_48, T_68) - rawB.isInf <= T_69 - node T_70 = bits(T_45, 11, 9) - node T_72 = eq(T_70, UInt<1>("h00")) - rawB.isZero <= T_72 - node T_73 = cvt(T_45) - rawB.sExp <= T_73 - node T_75 = bits(io.b, 51, 0) - node T_77 = cat(T_75, UInt<2>("h00")) - node T_78 = cat(UInt<2>("h01"), T_77) - rawB.sig <= T_78 - node T_79 = not(rawA.isNaN) - node T_80 = not(rawB.isNaN) - node ordered = and(T_79, T_80) - node bothInfs = and(rawA.isInf, rawB.isInf) - node bothZeros = and(rawA.isZero, rawB.isZero) - node eqExps = eq(rawA.sExp, rawB.sExp) - node T_85 = lt(rawA.sExp, rawB.sExp) - node T_86 = lt(rawA.sig, rawB.sig) - node T_87 = and(eqExps, T_86) - node common_ltMags = or(T_85, T_87) - node T_89 = eq(rawA.sig, rawB.sig) - node common_eqMags = and(eqExps, T_89) - node T_91 = not(bothZeros) - node T_92 = not(rawB.sign) - node T_93 = and(rawA.sign, T_92) - node T_94 = not(bothInfs) - node T_95 = not(common_ltMags) - node T_96 = and(rawA.sign, T_95) - node T_97 = not(common_eqMags) - node T_98 = and(T_96, T_97) - node T_99 = not(rawB.sign) - node T_100 = and(T_99, common_ltMags) - node T_101 = or(T_98, T_100) - node T_102 = and(T_94, T_101) - node T_103 = or(T_93, T_102) - node ordered_lt = and(T_91, T_103) - node T_105 = eq(rawA.sign, rawB.sign) - node T_106 = or(bothInfs, common_eqMags) - node T_107 = and(T_105, T_106) - node ordered_eq = or(bothZeros, T_107) - node T_109 = bits(rawA.sig, 53, 53) - node T_111 = eq(T_109, UInt<1>("h00")) - node T_112 = and(rawA.isNaN, T_111) - node T_113 = bits(rawB.sig, 53, 53) - node T_115 = eq(T_113, UInt<1>("h00")) - node T_116 = and(rawB.isNaN, T_115) - node T_117 = or(T_112, T_116) - node T_118 = not(ordered) - node T_119 = and(io.signaling, T_118) - node invalid = or(T_117, T_119) - node T_121 = and(ordered, ordered_lt) - io.lt <= T_121 - node T_122 = and(ordered, ordered_eq) - io.eq <= T_122 - node T_123 = not(ordered_lt) - node T_124 = and(ordered, T_123) - node T_125 = not(ordered_eq) - node T_126 = and(T_124, T_125) - io.gt <= T_126 - node T_128 = cat(invalid, UInt<4>("h00")) - io.exceptionFlags <= T_128 + io is invalid + cmem ram : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_57 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_59 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_60 = and(_T_57, _T_59) @[Decoupled.scala 188:33] + node _T_61 = and(_T_57, maybe_full) @[Decoupled.scala 189:32] + node _T_62 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_62 + node _T_63 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_63 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_64 = ram[value], clock + _T_64 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_71 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_72 = tail(_T_71, 1) @[Counter.scala 26:22] + value <= _T_72 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_75 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_76 = tail(_T_75, 1) @[Counter.scala 26:22] + value_1 <= _T_76 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_77 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_77 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_79 = eq(_T_60, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_79 @[Decoupled.scala 204:16] + node _T_81 = eq(_T_61, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_81 @[Decoupled.scala 205:16] + infer mport _T_82 = ram[value_1], clock + io.deq.bits <- _T_82 @[Decoupled.scala 206:15] + node _T_87 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_88 = asUInt(_T_87) @[Decoupled.scala 221:40] + node _T_89 = tail(_T_88, 1) @[Decoupled.scala 221:40] + node _T_90 = and(maybe_full, _T_57) @[Decoupled.scala 223:32] + node _T_91 = cat(_T_90, _T_89) @[Cat.scala 30:58] + io.count <= _T_91 @[Decoupled.scala 223:14] - module RecFNToIN : - input clk : Clock + module AXI4Buffer_1 : + input clock : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} io is invalid - node sign = bits(io.in, 64, 64) - node exp = bits(io.in, 63, 52) - node fract = bits(io.in, 51, 0) - node T_12 = bits(exp, 11, 9) - node isZero = eq(T_12, UInt<1>("h00")) - node T_15 = bits(exp, 11, 10) - node T_16 = not(T_15) - node isSpecial = eq(T_16, UInt<1>("h00")) - node T_19 = bits(exp, 9, 9) - node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bits(exp, 11, 11) - node T_22 = cat(notSpecial_magGeOne, fract) - node T_23 = bits(exp, 5, 0) - node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) - node shiftedSig = dshl(T_22, T_25) - node unroundedInt = bits(shiftedSig, 115, 52) - node T_28 = bits(shiftedSig, 52, 51) - node T_29 = bits(shiftedSig, 50, 0) - node T_31 = neq(T_29, UInt<1>("h00")) - node roundBits = cat(T_28, T_31) - node T_33 = bits(roundBits, 1, 0) - node T_35 = neq(T_33, UInt<1>("h00")) - node T_37 = eq(isZero, UInt<1>("h00")) - node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) - node T_39 = bits(roundBits, 2, 1) - node T_40 = not(T_39) - node T_42 = eq(T_40, UInt<1>("h00")) - node T_43 = bits(roundBits, 1, 0) - node T_44 = not(T_43) - node T_46 = eq(T_44, UInt<1>("h00")) - node T_47 = or(T_42, T_46) - node T_48 = bits(exp, 10, 0) - node T_49 = not(T_48) - node T_51 = eq(T_49, UInt<1>("h00")) - node T_52 = bits(roundBits, 1, 0) - node T_54 = neq(T_52, UInt<1>("h00")) - node T_56 = mux(T_51, T_54, UInt<1>("h00")) - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) - node T_58 = eq(io.roundingMode, UInt<2>("h00")) - node T_59 = and(T_58, roundIncr_nearestEven) - node T_60 = eq(io.roundingMode, UInt<2>("h02")) - node T_61 = and(sign, roundInexact) - node T_62 = and(T_60, T_61) - node T_63 = or(T_59, T_62) - node T_64 = eq(io.roundingMode, UInt<2>("h03")) - node T_66 = eq(sign, UInt<1>("h00")) - node T_67 = and(T_66, roundInexact) - node T_68 = and(T_64, T_67) - node roundIncr = or(T_63, T_68) - node T_70 = not(unroundedInt) - node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) - node T_72 = xor(roundIncr, sign) - node T_74 = add(onesCompUnroundedInt, UInt<1>("h01")) - node T_75 = tail(T_74, 1) - node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) - node T_77 = bits(unroundedInt, 61, 0) - node T_78 = not(T_77) - node T_80 = eq(T_78, UInt<1>("h00")) - node roundCarryBut2 = and(T_80, roundIncr) - node posExp = bits(exp, 10, 0) - node T_84 = geq(posExp, UInt<7>("h040")) - node T_86 = eq(posExp, UInt<6>("h03f")) - node T_88 = eq(sign, UInt<1>("h00")) - node T_89 = bits(unroundedInt, 62, 0) - node T_91 = neq(T_89, UInt<1>("h00")) - node T_92 = or(T_88, T_91) - node T_93 = or(T_92, roundIncr) - node T_94 = and(T_86, T_93) - node T_95 = or(T_84, T_94) - node T_97 = eq(sign, UInt<1>("h00")) - node T_99 = eq(posExp, UInt<6>("h03e")) - node T_100 = and(T_97, T_99) - node T_101 = and(T_100, roundCarryBut2) - node T_102 = or(T_95, T_101) - node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00")) - node T_106 = geq(posExp, UInt<7>("h040")) - node T_107 = or(sign, T_106) - node T_109 = eq(posExp, UInt<6>("h03f")) - node T_110 = bits(unroundedInt, 62, 62) - node T_111 = and(T_109, T_110) - node T_112 = and(T_111, roundCarryBut2) - node T_113 = or(T_107, T_112) - node T_114 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_118 = eq(isNaN, UInt<1>("h00")) - node excSign = and(sign, T_118) - node T_120 = and(io.signedOut, excSign) - node T_123 = mux(T_120, UInt<64>("h08000000000000000"), UInt<1>("h00")) - node T_125 = eq(excSign, UInt<1>("h00")) - node T_126 = and(io.signedOut, T_125) - node T_129 = mux(T_126, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) - node T_130 = or(T_123, T_129) - node T_132 = eq(io.signedOut, UInt<1>("h00")) - node T_135 = mux(T_132, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) - node excValue = or(T_130, T_135) - node T_138 = eq(isSpecial, UInt<1>("h00")) - node T_139 = and(roundInexact, T_138) - node T_141 = eq(overflow, UInt<1>("h00")) - node inexact = and(T_139, T_141) - node T_143 = or(isSpecial, overflow) - node T_144 = mux(T_143, excValue, roundedInt) - io.out <= T_144 - node T_145 = cat(overflow, inexact) - node T_146 = cat(isSpecial, T_145) - io.intExceptionFlags <= T_146 - - module RecFNToIN_118 : - input clk : Clock + io is invalid + inst Queue of Queue_47 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.aw <- Queue.io.deq @[Buffer.scala 31:26] + inst Queue_1 of Queue_48 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.w.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.w.bits @[Decoupled.scala 255:19] + io.in.0.w.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.w <- Queue_1.io.deq @[Buffer.scala 32:26] + inst Queue_2 of Queue_49 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.b <- Queue_2.io.deq @[Buffer.scala 33:26] + inst Queue_3 of Queue_50 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_3.io.deq @[Buffer.scala 34:26] + inst Queue_4 of Queue_51 @[Decoupled.scala 253:19] + Queue_4.io is invalid + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= io.out.0.r.valid @[Decoupled.scala 254:20] + Queue_4.io.enq.bits <- io.out.0.r.bits @[Decoupled.scala 255:19] + io.out.0.r.ready <= Queue_4.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.r <- Queue_4.io.deq @[Buffer.scala 35:26] + + module SimAXIMem : + input clock : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} + output io : {flip axi4 : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<28>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} io is invalid - node sign = bits(io.in, 64, 64) - node exp = bits(io.in, 63, 52) - node fract = bits(io.in, 51, 0) - node T_12 = bits(exp, 11, 9) - node isZero = eq(T_12, UInt<1>("h00")) - node T_15 = bits(exp, 11, 10) - node T_16 = not(T_15) - node isSpecial = eq(T_16, UInt<1>("h00")) - node T_19 = bits(exp, 9, 9) - node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bits(exp, 11, 11) - node T_22 = cat(notSpecial_magGeOne, fract) - node T_23 = bits(exp, 4, 0) - node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) - node shiftedSig = dshl(T_22, T_25) - node unroundedInt = bits(shiftedSig, 83, 52) - node T_28 = bits(shiftedSig, 52, 51) - node T_29 = bits(shiftedSig, 50, 0) - node T_31 = neq(T_29, UInt<1>("h00")) - node roundBits = cat(T_28, T_31) - node T_33 = bits(roundBits, 1, 0) - node T_35 = neq(T_33, UInt<1>("h00")) - node T_37 = eq(isZero, UInt<1>("h00")) - node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) - node T_39 = bits(roundBits, 2, 1) - node T_40 = not(T_39) - node T_42 = eq(T_40, UInt<1>("h00")) - node T_43 = bits(roundBits, 1, 0) - node T_44 = not(T_43) - node T_46 = eq(T_44, UInt<1>("h00")) - node T_47 = or(T_42, T_46) - node T_48 = bits(exp, 10, 0) - node T_49 = not(T_48) - node T_51 = eq(T_49, UInt<1>("h00")) - node T_52 = bits(roundBits, 1, 0) - node T_54 = neq(T_52, UInt<1>("h00")) - node T_56 = mux(T_51, T_54, UInt<1>("h00")) - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) - node T_58 = eq(io.roundingMode, UInt<2>("h00")) - node T_59 = and(T_58, roundIncr_nearestEven) - node T_60 = eq(io.roundingMode, UInt<2>("h02")) - node T_61 = and(sign, roundInexact) - node T_62 = and(T_60, T_61) - node T_63 = or(T_59, T_62) - node T_64 = eq(io.roundingMode, UInt<2>("h03")) - node T_66 = eq(sign, UInt<1>("h00")) - node T_67 = and(T_66, roundInexact) - node T_68 = and(T_64, T_67) - node roundIncr = or(T_63, T_68) - node T_70 = not(unroundedInt) - node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) - node T_72 = xor(roundIncr, sign) - node T_74 = add(onesCompUnroundedInt, UInt<1>("h01")) - node T_75 = tail(T_74, 1) - node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) - node T_77 = bits(unroundedInt, 29, 0) - node T_78 = not(T_77) - node T_80 = eq(T_78, UInt<1>("h00")) - node roundCarryBut2 = and(T_80, roundIncr) - node posExp = bits(exp, 10, 0) - node T_84 = geq(posExp, UInt<6>("h020")) - node T_86 = eq(posExp, UInt<5>("h01f")) - node T_88 = eq(sign, UInt<1>("h00")) - node T_89 = bits(unroundedInt, 30, 0) - node T_91 = neq(T_89, UInt<1>("h00")) - node T_92 = or(T_88, T_91) - node T_93 = or(T_92, roundIncr) - node T_94 = and(T_86, T_93) - node T_95 = or(T_84, T_94) - node T_97 = eq(sign, UInt<1>("h00")) - node T_99 = eq(posExp, UInt<5>("h01e")) - node T_100 = and(T_97, T_99) - node T_101 = and(T_100, roundCarryBut2) - node T_102 = or(T_95, T_101) - node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00")) - node T_106 = geq(posExp, UInt<6>("h020")) - node T_107 = or(sign, T_106) - node T_109 = eq(posExp, UInt<5>("h01f")) - node T_110 = bits(unroundedInt, 30, 30) - node T_111 = and(T_109, T_110) - node T_112 = and(T_111, roundCarryBut2) - node T_113 = or(T_107, T_112) - node T_114 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_118 = eq(isNaN, UInt<1>("h00")) - node excSign = and(sign, T_118) - node T_120 = and(io.signedOut, excSign) - node T_123 = mux(T_120, UInt<32>("h080000000"), UInt<1>("h00")) - node T_125 = eq(excSign, UInt<1>("h00")) - node T_126 = and(io.signedOut, T_125) - node T_129 = mux(T_126, UInt<31>("h07fffffff"), UInt<1>("h00")) - node T_130 = or(T_123, T_129) - node T_132 = eq(io.signedOut, UInt<1>("h00")) - node T_135 = mux(T_132, UInt<32>("h0ffffffff"), UInt<1>("h00")) - node excValue = or(T_130, T_135) - node T_138 = eq(isSpecial, UInt<1>("h00")) - node T_139 = and(roundInexact, T_138) - node T_141 = eq(overflow, UInt<1>("h00")) - node inexact = and(T_139, T_141) - node T_143 = or(isSpecial, overflow) - node T_144 = mux(T_143, excValue, roundedInt) - io.out <= T_144 - node T_145 = cat(overflow, inexact) - node T_146 = cat(isSpecial, T_145) - io.intExceptionFlags <= T_146 + io is invalid + inst AXI4RAM of AXI4RAM @[LazyModule.scala 60:13] + AXI4RAM.io is invalid + AXI4RAM.clock <= clock + AXI4RAM.reset <= reset + inst AXI4Fragmenter of AXI4Fragmenter_1 @[LazyModule.scala 60:13] + AXI4Fragmenter.io is invalid + AXI4Fragmenter.clock <= clock + AXI4Fragmenter.reset <= reset + inst AXI4Buffer of AXI4Buffer_1 @[LazyModule.scala 60:13] + AXI4Buffer.io is invalid + AXI4Buffer.clock <= clock + AXI4Buffer.reset <= reset + AXI4Fragmenter.io.in.0 <- io.axi4.0 @[TestHarness.scala 51:62] + AXI4Buffer.io.in.0 <- AXI4Fragmenter.io.out.0 @[TestHarness.scala 51:30] + AXI4RAM.io.in.0 <- AXI4Buffer.io.out.0 @[TestHarness.scala 51:15] - module FPToInt : + extmodule SimDTM : + output exit : UInt<32> + output debug : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}} + input reset : UInt<1> input clk : Clock + + defname = SimDTM + + + module AXI4RAM_1 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} - - io is invalid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - reg valid : UInt<1>, clk - valid <= io.in.valid - inst T_233 of RecFNToRecFN - T_233.io is invalid - T_233.clk <= clk - T_233.reset <= reset - T_233.io.in <= io.in.bits.in1 - T_233.io.roundingMode <= UInt<1>("h00") - inst T_235 of RecFNToRecFN - T_235.io is invalid - T_235.clk <= clk - T_235.reset <= reset - T_235.io.in <= io.in.bits.in2 - T_235.io.roundingMode <= UInt<1>("h00") - when io.in.valid : - in <- io.in.bits - node T_238 = eq(io.in.bits.ldst, UInt<1>("h00")) - node T_239 = and(io.in.bits.single, T_238) - node T_242 = and(io.in.bits.cmd, UInt<4>("h0c")) - node T_243 = eq(UInt<4>("h0c"), T_242) - node T_245 = eq(T_243, UInt<1>("h00")) - node T_246 = and(T_239, T_245) - when T_246 : - in.in1 <= T_233.io.out - in.in2 <= T_235.io.out + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + smem mem : UInt<8>[8][512] @[SRAM.scala 36:21] + node _T_313 = shr(io.in.0.ar.bits.addr, 3) @[SRAM.scala 38:49] + node _T_314 = bits(_T_313, 0, 0) @[SRAM.scala 38:73] + node _T_315 = bits(_T_313, 1, 1) @[SRAM.scala 38:73] + node _T_316 = bits(_T_313, 2, 2) @[SRAM.scala 38:73] + node _T_317 = bits(_T_313, 3, 3) @[SRAM.scala 38:73] + node _T_318 = bits(_T_313, 4, 4) @[SRAM.scala 38:73] + node _T_319 = bits(_T_313, 5, 5) @[SRAM.scala 38:73] + node _T_320 = bits(_T_313, 6, 6) @[SRAM.scala 38:73] + node _T_321 = bits(_T_313, 7, 7) @[SRAM.scala 38:73] + node _T_322 = bits(_T_313, 8, 8) @[SRAM.scala 38:73] + node _T_323 = cat(_T_315, _T_314) @[Cat.scala 30:58] + node _T_324 = cat(_T_317, _T_316) @[Cat.scala 30:58] + node _T_325 = cat(_T_324, _T_323) @[Cat.scala 30:58] + node _T_326 = cat(_T_319, _T_318) @[Cat.scala 30:58] + node _T_327 = cat(_T_322, _T_321) @[Cat.scala 30:58] + node _T_328 = cat(_T_327, _T_320) @[Cat.scala 30:58] + node _T_329 = cat(_T_328, _T_326) @[Cat.scala 30:58] + node r_addr = cat(_T_329, _T_325) @[Cat.scala 30:58] + node _T_330 = shr(io.in.0.aw.bits.addr, 3) @[SRAM.scala 39:49] + node _T_331 = bits(_T_330, 0, 0) @[SRAM.scala 39:73] + node _T_332 = bits(_T_330, 1, 1) @[SRAM.scala 39:73] + node _T_333 = bits(_T_330, 2, 2) @[SRAM.scala 39:73] + node _T_334 = bits(_T_330, 3, 3) @[SRAM.scala 39:73] + node _T_335 = bits(_T_330, 4, 4) @[SRAM.scala 39:73] + node _T_336 = bits(_T_330, 5, 5) @[SRAM.scala 39:73] + node _T_337 = bits(_T_330, 6, 6) @[SRAM.scala 39:73] + node _T_338 = bits(_T_330, 7, 7) @[SRAM.scala 39:73] + node _T_339 = bits(_T_330, 8, 8) @[SRAM.scala 39:73] + node _T_340 = cat(_T_332, _T_331) @[Cat.scala 30:58] + node _T_341 = cat(_T_334, _T_333) @[Cat.scala 30:58] + node _T_342 = cat(_T_341, _T_340) @[Cat.scala 30:58] + node _T_343 = cat(_T_336, _T_335) @[Cat.scala 30:58] + node _T_344 = cat(_T_339, _T_338) @[Cat.scala 30:58] + node _T_345 = cat(_T_344, _T_337) @[Cat.scala 30:58] + node _T_346 = cat(_T_345, _T_343) @[Cat.scala 30:58] + node w_addr = cat(_T_346, _T_342) @[Cat.scala 30:58] + node _T_347 = and(io.in.0.w.valid, io.in.0.b.ready) @[SRAM.scala 41:32] + io.in.0.aw.ready <= _T_347 @[SRAM.scala 41:17] + node _T_348 = and(io.in.0.aw.valid, io.in.0.b.ready) @[SRAM.scala 42:32] + io.in.0.w.ready <= _T_348 @[SRAM.scala 42:17] + node _T_349 = and(io.in.0.w.valid, io.in.0.aw.valid) @[SRAM.scala 43:31] + io.in.0.b.valid <= _T_349 @[SRAM.scala 43:17] + io.in.0.b.bits.id <= io.in.0.aw.bits.id @[SRAM.scala 45:20] + io.in.0.b.bits.resp <= UInt<2>("h00") @[SRAM.scala 46:20] + node _T_351 = bits(io.in.0.w.bits.data, 7, 0) @[SRAM.scala 47:62] + node _T_352 = bits(io.in.0.w.bits.data, 15, 8) @[SRAM.scala 47:62] + node _T_353 = bits(io.in.0.w.bits.data, 23, 16) @[SRAM.scala 47:62] + node _T_354 = bits(io.in.0.w.bits.data, 31, 24) @[SRAM.scala 47:62] + node _T_355 = bits(io.in.0.w.bits.data, 39, 32) @[SRAM.scala 47:62] + node _T_356 = bits(io.in.0.w.bits.data, 47, 40) @[SRAM.scala 47:62] + node _T_357 = bits(io.in.0.w.bits.data, 55, 48) @[SRAM.scala 47:62] + node _T_358 = bits(io.in.0.w.bits.data, 63, 56) @[SRAM.scala 47:62] + wire wdata : UInt<8>[8] @[SRAM.scala 47:41] + wdata is invalid @[SRAM.scala 47:41] + wdata[0] <= _T_351 @[SRAM.scala 47:41] + wdata[1] <= _T_352 @[SRAM.scala 47:41] + wdata[2] <= _T_353 @[SRAM.scala 47:41] + wdata[3] <= _T_354 @[SRAM.scala 47:41] + wdata[4] <= _T_355 @[SRAM.scala 47:41] + wdata[5] <= _T_356 @[SRAM.scala 47:41] + wdata[6] <= _T_357 @[SRAM.scala 47:41] + wdata[7] <= _T_358 @[SRAM.scala 47:41] + node _T_371 = and(io.in.0.b.ready, io.in.0.b.valid) @[Decoupled.scala 30:37] + when _T_371 : @[SRAM.scala 48:24] + node _T_372 = bits(io.in.0.w.bits.strb, 0, 0) @[SRAM.scala 49:47] + node _T_373 = bits(io.in.0.w.bits.strb, 1, 1) @[SRAM.scala 49:47] + node _T_374 = bits(io.in.0.w.bits.strb, 2, 2) @[SRAM.scala 49:47] + node _T_375 = bits(io.in.0.w.bits.strb, 3, 3) @[SRAM.scala 49:47] + node _T_376 = bits(io.in.0.w.bits.strb, 4, 4) @[SRAM.scala 49:47] + node _T_377 = bits(io.in.0.w.bits.strb, 5, 5) @[SRAM.scala 49:47] + node _T_378 = bits(io.in.0.w.bits.strb, 6, 6) @[SRAM.scala 49:47] + node _T_379 = bits(io.in.0.w.bits.strb, 7, 7) @[SRAM.scala 49:47] + write mport _T_380 = mem[w_addr], clock + when _T_372 : + _T_380[0] <= wdata[0] skip - skip - node T_247 = bits(in.in1, 32, 32) - node T_248 = bits(in.in1, 31, 23) - node T_249 = bits(in.in1, 22, 0) - node T_250 = bits(T_248, 6, 0) - node T_252 = lt(T_250, UInt<2>("h02")) - node T_253 = bits(T_248, 8, 6) - node T_255 = eq(T_253, UInt<1>("h01")) - node T_256 = bits(T_248, 8, 7) - node T_258 = eq(T_256, UInt<1>("h01")) - node T_259 = and(T_258, T_252) - node T_260 = or(T_255, T_259) - node T_261 = bits(T_248, 8, 7) - node T_263 = eq(T_261, UInt<1>("h01")) - node T_265 = eq(T_252, UInt<1>("h00")) - node T_266 = and(T_263, T_265) - node T_267 = bits(T_248, 8, 7) - node T_269 = eq(T_267, UInt<2>("h02")) - node T_270 = or(T_266, T_269) - node T_271 = bits(T_248, 8, 7) - node T_273 = eq(T_271, UInt<2>("h03")) - node T_274 = bits(T_248, 6, 6) - node T_275 = and(T_273, T_274) - node T_277 = bits(T_248, 4, 0) - node T_278 = sub(UInt<2>("h02"), T_277) - node T_279 = tail(T_278, 1) - node T_281 = cat(UInt<1>("h01"), T_249) - node T_282 = dshr(T_281, T_279) - node T_283 = bits(T_282, 22, 0) - node T_284 = bits(T_248, 7, 0) - node T_286 = sub(T_284, UInt<8>("h081")) - node T_287 = tail(T_286, 1) - node T_289 = sub(UInt<8>("h00"), T_273) - node T_290 = tail(T_289, 1) - node T_291 = mux(T_270, T_287, T_290) - node T_292 = or(T_270, T_275) - node T_294 = mux(T_260, T_283, UInt<1>("h00")) - node T_295 = mux(T_292, T_249, T_294) - node T_296 = cat(T_291, T_295) - node unrec_s = cat(T_247, T_296) - node T_298 = bits(in.in1, 64, 64) - node T_299 = bits(in.in1, 63, 52) - node T_300 = bits(in.in1, 51, 0) - node T_301 = bits(T_299, 9, 0) - node T_303 = lt(T_301, UInt<2>("h02")) - node T_304 = bits(T_299, 11, 9) - node T_306 = eq(T_304, UInt<1>("h01")) - node T_307 = bits(T_299, 11, 10) - node T_309 = eq(T_307, UInt<1>("h01")) - node T_310 = and(T_309, T_303) - node T_311 = or(T_306, T_310) - node T_312 = bits(T_299, 11, 10) - node T_314 = eq(T_312, UInt<1>("h01")) - node T_316 = eq(T_303, UInt<1>("h00")) - node T_317 = and(T_314, T_316) - node T_318 = bits(T_299, 11, 10) - node T_320 = eq(T_318, UInt<2>("h02")) - node T_321 = or(T_317, T_320) - node T_322 = bits(T_299, 11, 10) - node T_324 = eq(T_322, UInt<2>("h03")) - node T_325 = bits(T_299, 9, 9) - node T_326 = and(T_324, T_325) - node T_328 = bits(T_299, 5, 0) - node T_329 = sub(UInt<2>("h02"), T_328) - node T_330 = tail(T_329, 1) - node T_332 = cat(UInt<1>("h01"), T_300) - node T_333 = dshr(T_332, T_330) - node T_334 = bits(T_333, 51, 0) - node T_335 = bits(T_299, 10, 0) - node T_337 = sub(T_335, UInt<11>("h0401")) - node T_338 = tail(T_337, 1) - node T_340 = sub(UInt<11>("h00"), T_324) - node T_341 = tail(T_340, 1) - node T_342 = mux(T_321, T_338, T_341) - node T_343 = or(T_321, T_326) - node T_345 = mux(T_311, T_334, UInt<1>("h00")) - node T_346 = mux(T_343, T_300, T_345) - node T_347 = cat(T_342, T_346) - node unrec_d = cat(T_298, T_347) - node T_349 = bits(unrec_s, 31, 31) - node T_351 = sub(UInt<32>("h00"), T_349) - node T_352 = tail(T_351, 1) - node T_353 = cat(T_352, unrec_s) - node unrec_out = mux(in.single, T_353, unrec_d) - node T_355 = bits(in.in1, 32, 32) - node T_356 = bits(in.in1, 31, 23) - node T_357 = bits(in.in1, 22, 0) - node T_358 = bits(T_356, 8, 6) - node T_359 = bits(T_358, 2, 1) - node T_361 = eq(T_359, UInt<2>("h03")) - node T_362 = bits(T_356, 6, 0) - node T_364 = lt(T_362, UInt<2>("h02")) - node T_366 = eq(T_358, UInt<1>("h01")) - node T_368 = eq(T_359, UInt<1>("h01")) - node T_369 = and(T_368, T_364) - node T_370 = or(T_366, T_369) - node T_372 = eq(T_359, UInt<1>("h01")) - node T_374 = eq(T_364, UInt<1>("h00")) - node T_375 = and(T_372, T_374) - node T_377 = eq(T_359, UInt<2>("h02")) - node T_378 = or(T_375, T_377) - node T_380 = eq(T_358, UInt<1>("h00")) - node T_381 = bits(T_356, 6, 6) - node T_383 = eq(T_381, UInt<1>("h00")) - node T_384 = and(T_361, T_383) - node T_385 = not(T_358) - node T_387 = eq(T_385, UInt<1>("h00")) - node T_388 = bits(T_357, 22, 22) - node T_390 = eq(T_388, UInt<1>("h00")) - node T_391 = and(T_387, T_390) - node T_392 = bits(T_357, 22, 22) - node T_393 = and(T_387, T_392) - node T_395 = eq(T_355, UInt<1>("h00")) - node T_396 = and(T_384, T_395) - node T_398 = eq(T_355, UInt<1>("h00")) - node T_399 = and(T_378, T_398) - node T_401 = eq(T_355, UInt<1>("h00")) - node T_402 = and(T_370, T_401) - node T_404 = eq(T_355, UInt<1>("h00")) - node T_405 = and(T_380, T_404) - node T_406 = and(T_380, T_355) - node T_407 = and(T_370, T_355) - node T_408 = and(T_378, T_355) - node T_409 = and(T_384, T_355) - node T_410 = cat(T_393, T_391) - node T_411 = cat(T_399, T_402) - node T_412 = cat(T_396, T_411) - node T_413 = cat(T_410, T_412) - node T_414 = cat(T_405, T_406) - node T_415 = cat(T_408, T_409) - node T_416 = cat(T_407, T_415) - node T_417 = cat(T_414, T_416) - node classify_s = cat(T_413, T_417) - node T_419 = bits(in.in1, 64, 64) - node T_420 = bits(in.in1, 63, 52) - node T_421 = bits(in.in1, 51, 0) - node T_422 = bits(T_420, 11, 9) - node T_423 = bits(T_422, 2, 1) - node T_425 = eq(T_423, UInt<2>("h03")) - node T_426 = bits(T_420, 9, 0) - node T_428 = lt(T_426, UInt<2>("h02")) - node T_430 = eq(T_422, UInt<1>("h01")) - node T_432 = eq(T_423, UInt<1>("h01")) - node T_433 = and(T_432, T_428) - node T_434 = or(T_430, T_433) - node T_436 = eq(T_423, UInt<1>("h01")) - node T_438 = eq(T_428, UInt<1>("h00")) - node T_439 = and(T_436, T_438) - node T_441 = eq(T_423, UInt<2>("h02")) - node T_442 = or(T_439, T_441) - node T_444 = eq(T_422, UInt<1>("h00")) - node T_445 = bits(T_420, 9, 9) - node T_447 = eq(T_445, UInt<1>("h00")) - node T_448 = and(T_425, T_447) - node T_449 = not(T_422) - node T_451 = eq(T_449, UInt<1>("h00")) - node T_452 = bits(T_421, 51, 51) - node T_454 = eq(T_452, UInt<1>("h00")) - node T_455 = and(T_451, T_454) - node T_456 = bits(T_421, 51, 51) - node T_457 = and(T_451, T_456) - node T_459 = eq(T_419, UInt<1>("h00")) - node T_460 = and(T_448, T_459) - node T_462 = eq(T_419, UInt<1>("h00")) - node T_463 = and(T_442, T_462) - node T_465 = eq(T_419, UInt<1>("h00")) - node T_466 = and(T_434, T_465) - node T_468 = eq(T_419, UInt<1>("h00")) - node T_469 = and(T_444, T_468) - node T_470 = and(T_444, T_419) - node T_471 = and(T_434, T_419) - node T_472 = and(T_442, T_419) - node T_473 = and(T_448, T_419) - node T_474 = cat(T_457, T_455) - node T_475 = cat(T_463, T_466) - node T_476 = cat(T_460, T_475) - node T_477 = cat(T_474, T_476) - node T_478 = cat(T_469, T_470) - node T_479 = cat(T_472, T_473) - node T_480 = cat(T_471, T_479) - node T_481 = cat(T_478, T_480) - node classify_d = cat(T_477, T_481) - node classify_out = mux(in.single, classify_s, classify_d) - inst dcmp of CompareRecFN - dcmp.io is invalid - dcmp.clk <= clk - dcmp.reset <= reset - dcmp.io.a <= in.in1 - dcmp.io.b <= in.in2 - dcmp.io.signaling <= UInt<1>("h01") - node T_486 = not(in.rm) - node T_487 = cat(dcmp.io.lt, dcmp.io.eq) - node T_488 = and(T_486, T_487) - node dcmp_out = neq(T_488, UInt<1>("h00")) - inst d2l of RecFNToIN - d2l.io is invalid - d2l.clk <= clk - d2l.reset <= reset - inst d2w of RecFNToIN_118 - d2w.io is invalid - d2w.clk <= clk - d2w.reset <= reset - d2l.io.in <= in.in1 - d2l.io.roundingMode <= in.rm - node T_493 = bits(in.typ, 0, 0) - node T_494 = not(T_493) - d2l.io.signedOut <= T_494 - d2w.io.in <= in.in1 - d2w.io.roundingMode <= in.rm - node T_495 = bits(in.typ, 0, 0) - node T_496 = not(T_495) - d2w.io.signedOut <= T_496 - node T_497 = bits(in.rm, 0, 0) - node T_498 = mux(T_497, classify_out, unrec_out) - io.out.bits.toint <= T_498 - io.out.bits.store <= unrec_out - io.out.bits.exc <= UInt<1>("h00") - node T_502 = and(in.cmd, UInt<4>("h0c")) - node T_503 = eq(UInt<3>("h04"), T_502) - when T_503 : - io.out.bits.toint <= dcmp_out - io.out.bits.exc <= dcmp.io.exceptionFlags - skip - node T_506 = and(in.cmd, UInt<4>("h0c")) - node T_507 = eq(UInt<4>("h08"), T_506) - when T_507 : - node T_508 = bits(in.typ, 1, 1) - node T_509 = asSInt(d2l.io.out) - node T_510 = asSInt(d2w.io.out) - node T_511 = mux(T_508, T_509, T_510) - node T_512 = asUInt(T_511) - io.out.bits.toint <= T_512 - node T_513 = bits(in.typ, 1, 1) - node T_514 = mux(T_513, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags) - node T_515 = bits(T_514, 2, 1) - node T_517 = neq(T_515, UInt<1>("h00")) - node T_519 = bits(T_514, 0, 0) - node T_520 = cat(UInt<3>("h00"), T_519) - node T_521 = cat(T_517, T_520) - io.out.bits.exc <= T_521 - skip - io.out.valid <= valid - io.out.bits.lt <= dcmp.io.lt - io.as_double <- in + when _T_373 : + _T_380[1] <= wdata[1] + skip + when _T_374 : + _T_380[2] <= wdata[2] + skip + when _T_375 : + _T_380[3] <= wdata[3] + skip + when _T_376 : + _T_380[4] <= wdata[4] + skip + when _T_377 : + _T_380[5] <= wdata[5] + skip + when _T_378 : + _T_380[6] <= wdata[6] + skip + when _T_379 : + _T_380[7] <= wdata[7] + skip + skip @[SRAM.scala 48:24] + reg r_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg r_id : UInt, clock @[SRAM.scala 53:21] + node _T_402 = and(io.in.0.r.ready, io.in.0.r.valid) @[Decoupled.scala 30:37] + when _T_402 : @[SRAM.scala 55:25] + r_full <= UInt<1>("h00") @[SRAM.scala 55:34] + skip @[SRAM.scala 55:25] + node _T_404 = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + when _T_404 : @[SRAM.scala 56:25] + r_full <= UInt<1>("h01") @[SRAM.scala 56:34] + skip @[SRAM.scala 56:25] + io.in.0.r.valid <= r_full @[SRAM.scala 58:17] + node _T_407 = eq(r_full, UInt<1>("h00")) @[SRAM.scala 59:34] + node _T_408 = or(io.in.0.r.ready, _T_407) @[SRAM.scala 59:31] + io.in.0.ar.ready <= _T_408 @[SRAM.scala 59:17] + node _T_409 = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + when _T_409 : @[SRAM.scala 61:25] + r_id <= io.in.0.ar.bits.id @[SRAM.scala 62:12] + skip @[SRAM.scala 61:25] + node ren = and(io.in.0.ar.ready, io.in.0.ar.valid) @[Decoupled.scala 30:37] + wire _T_411 : UInt + _T_411 is invalid + when ren : + _T_411 <= r_addr + node _T_413 = or(_T_411, UInt<9>("h00")) + node _T_414 = bits(_T_413, 8, 0) + read mport _T_415 = mem[_T_414], clock + skip + reg _T_435 : UInt<1>, clock @[Reg.scala 14:44] + _T_435 <= ren @[Reg.scala 14:44] + reg _T_465 : UInt<8>[8], clock @[Reg.scala 34:16] + when _T_435 : @[Reg.scala 35:19] + _T_465 <- _T_415 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node rdata = mux(_T_435, _T_415, _T_465) @[Package.scala 27:42] + io.in.0.r.bits.id <= r_id @[SRAM.scala 68:20] + io.in.0.r.bits.resp <= UInt<2>("h00") @[SRAM.scala 69:20] + node _T_532 = cat(rdata[1], rdata[0]) @[Cat.scala 30:58] + node _T_533 = cat(rdata[3], rdata[2]) @[Cat.scala 30:58] + node _T_534 = cat(_T_533, _T_532) @[Cat.scala 30:58] + node _T_535 = cat(rdata[5], rdata[4]) @[Cat.scala 30:58] + node _T_536 = cat(rdata[7], rdata[6]) @[Cat.scala 30:58] + node _T_537 = cat(_T_536, _T_535) @[Cat.scala 30:58] + node _T_538 = cat(_T_537, _T_534) @[Cat.scala 30:58] + io.in.0.r.bits.data <= _T_538 @[SRAM.scala 70:20] + io.in.0.r.bits.last <= UInt<1>("h01") @[SRAM.scala 71:20] - module INToRecFN : - input clk : Clock + module Queue_52 : + input clock : Clock input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} io is invalid - node T_9 = bits(io.in, 63, 63) - node sign = and(io.signedIn, T_9) - node T_12 = sub(UInt<1>("h00"), io.in) - node T_13 = tail(T_12, 1) - node absIn = mux(sign, T_13, io.in) - node T_15 = shl(absIn, 0) - node T_16 = bits(T_15, 63, 63) - node T_18 = bits(T_15, 62, 62) - node T_20 = bits(T_15, 61, 61) - node T_22 = bits(T_15, 60, 60) - node T_24 = bits(T_15, 59, 59) - node T_26 = bits(T_15, 58, 58) - node T_28 = bits(T_15, 57, 57) - node T_30 = bits(T_15, 56, 56) - node T_32 = bits(T_15, 55, 55) - node T_34 = bits(T_15, 54, 54) - node T_36 = bits(T_15, 53, 53) - node T_38 = bits(T_15, 52, 52) - node T_40 = bits(T_15, 51, 51) - node T_42 = bits(T_15, 50, 50) - node T_44 = bits(T_15, 49, 49) - node T_46 = bits(T_15, 48, 48) - node T_48 = bits(T_15, 47, 47) - node T_50 = bits(T_15, 46, 46) - node T_52 = bits(T_15, 45, 45) - node T_54 = bits(T_15, 44, 44) - node T_56 = bits(T_15, 43, 43) - node T_58 = bits(T_15, 42, 42) - node T_60 = bits(T_15, 41, 41) - node T_62 = bits(T_15, 40, 40) - node T_64 = bits(T_15, 39, 39) - node T_66 = bits(T_15, 38, 38) - node T_68 = bits(T_15, 37, 37) - node T_70 = bits(T_15, 36, 36) - node T_72 = bits(T_15, 35, 35) - node T_74 = bits(T_15, 34, 34) - node T_76 = bits(T_15, 33, 33) - node T_78 = bits(T_15, 32, 32) - node T_80 = bits(T_15, 31, 31) - node T_82 = bits(T_15, 30, 30) - node T_84 = bits(T_15, 29, 29) - node T_86 = bits(T_15, 28, 28) - node T_88 = bits(T_15, 27, 27) - node T_90 = bits(T_15, 26, 26) - node T_92 = bits(T_15, 25, 25) - node T_94 = bits(T_15, 24, 24) - node T_96 = bits(T_15, 23, 23) - node T_98 = bits(T_15, 22, 22) - node T_100 = bits(T_15, 21, 21) - node T_102 = bits(T_15, 20, 20) - node T_104 = bits(T_15, 19, 19) - node T_106 = bits(T_15, 18, 18) - node T_108 = bits(T_15, 17, 17) - node T_110 = bits(T_15, 16, 16) - node T_112 = bits(T_15, 15, 15) - node T_114 = bits(T_15, 14, 14) - node T_116 = bits(T_15, 13, 13) - node T_118 = bits(T_15, 12, 12) - node T_120 = bits(T_15, 11, 11) - node T_122 = bits(T_15, 10, 10) - node T_124 = bits(T_15, 9, 9) - node T_126 = bits(T_15, 8, 8) - node T_128 = bits(T_15, 7, 7) - node T_130 = bits(T_15, 6, 6) - node T_132 = bits(T_15, 5, 5) - node T_134 = bits(T_15, 4, 4) - node T_136 = bits(T_15, 3, 3) - node T_138 = bits(T_15, 2, 2) - node T_140 = bits(T_15, 1, 1) - node T_141 = shl(T_140, 0) - node T_142 = mux(T_138, UInt<2>("h02"), T_141) - node T_143 = mux(T_136, UInt<2>("h03"), T_142) - node T_144 = mux(T_134, UInt<3>("h04"), T_143) - node T_145 = mux(T_132, UInt<3>("h05"), T_144) - node T_146 = mux(T_130, UInt<3>("h06"), T_145) - node T_147 = mux(T_128, UInt<3>("h07"), T_146) - node T_148 = mux(T_126, UInt<4>("h08"), T_147) - node T_149 = mux(T_124, UInt<4>("h09"), T_148) - node T_150 = mux(T_122, UInt<4>("h0a"), T_149) - node T_151 = mux(T_120, UInt<4>("h0b"), T_150) - node T_152 = mux(T_118, UInt<4>("h0c"), T_151) - node T_153 = mux(T_116, UInt<4>("h0d"), T_152) - node T_154 = mux(T_114, UInt<4>("h0e"), T_153) - node T_155 = mux(T_112, UInt<4>("h0f"), T_154) - node T_156 = mux(T_110, UInt<5>("h010"), T_155) - node T_157 = mux(T_108, UInt<5>("h011"), T_156) - node T_158 = mux(T_106, UInt<5>("h012"), T_157) - node T_159 = mux(T_104, UInt<5>("h013"), T_158) - node T_160 = mux(T_102, UInt<5>("h014"), T_159) - node T_161 = mux(T_100, UInt<5>("h015"), T_160) - node T_162 = mux(T_98, UInt<5>("h016"), T_161) - node T_163 = mux(T_96, UInt<5>("h017"), T_162) - node T_164 = mux(T_94, UInt<5>("h018"), T_163) - node T_165 = mux(T_92, UInt<5>("h019"), T_164) - node T_166 = mux(T_90, UInt<5>("h01a"), T_165) - node T_167 = mux(T_88, UInt<5>("h01b"), T_166) - node T_168 = mux(T_86, UInt<5>("h01c"), T_167) - node T_169 = mux(T_84, UInt<5>("h01d"), T_168) - node T_170 = mux(T_82, UInt<5>("h01e"), T_169) - node T_171 = mux(T_80, UInt<5>("h01f"), T_170) - node T_172 = mux(T_78, UInt<6>("h020"), T_171) - node T_173 = mux(T_76, UInt<6>("h021"), T_172) - node T_174 = mux(T_74, UInt<6>("h022"), T_173) - node T_175 = mux(T_72, UInt<6>("h023"), T_174) - node T_176 = mux(T_70, UInt<6>("h024"), T_175) - node T_177 = mux(T_68, UInt<6>("h025"), T_176) - node T_178 = mux(T_66, UInt<6>("h026"), T_177) - node T_179 = mux(T_64, UInt<6>("h027"), T_178) - node T_180 = mux(T_62, UInt<6>("h028"), T_179) - node T_181 = mux(T_60, UInt<6>("h029"), T_180) - node T_182 = mux(T_58, UInt<6>("h02a"), T_181) - node T_183 = mux(T_56, UInt<6>("h02b"), T_182) - node T_184 = mux(T_54, UInt<6>("h02c"), T_183) - node T_185 = mux(T_52, UInt<6>("h02d"), T_184) - node T_186 = mux(T_50, UInt<6>("h02e"), T_185) - node T_187 = mux(T_48, UInt<6>("h02f"), T_186) - node T_188 = mux(T_46, UInt<6>("h030"), T_187) - node T_189 = mux(T_44, UInt<6>("h031"), T_188) - node T_190 = mux(T_42, UInt<6>("h032"), T_189) - node T_191 = mux(T_40, UInt<6>("h033"), T_190) - node T_192 = mux(T_38, UInt<6>("h034"), T_191) - node T_193 = mux(T_36, UInt<6>("h035"), T_192) - node T_194 = mux(T_34, UInt<6>("h036"), T_193) - node T_195 = mux(T_32, UInt<6>("h037"), T_194) - node T_196 = mux(T_30, UInt<6>("h038"), T_195) - node T_197 = mux(T_28, UInt<6>("h039"), T_196) - node T_198 = mux(T_26, UInt<6>("h03a"), T_197) - node T_199 = mux(T_24, UInt<6>("h03b"), T_198) - node T_200 = mux(T_22, UInt<6>("h03c"), T_199) - node T_201 = mux(T_20, UInt<6>("h03d"), T_200) - node T_202 = mux(T_18, UInt<6>("h03e"), T_201) - node T_203 = mux(T_16, UInt<6>("h03f"), T_202) - node normCount = not(T_203) - node T_205 = dshl(absIn, normCount) - node normAbsIn = bits(T_205, 63, 0) - node T_208 = bits(normAbsIn, 40, 39) - node T_209 = bits(normAbsIn, 38, 0) - node T_211 = neq(T_209, UInt<1>("h00")) - node roundBits = cat(T_208, T_211) - node T_213 = bits(roundBits, 1, 0) - node roundInexact = neq(T_213, UInt<1>("h00")) - node T_216 = eq(io.roundingMode, UInt<2>("h00")) - node T_217 = bits(roundBits, 2, 1) - node T_218 = not(T_217) - node T_220 = eq(T_218, UInt<1>("h00")) - node T_221 = bits(roundBits, 1, 0) - node T_222 = not(T_221) - node T_224 = eq(T_222, UInt<1>("h00")) - node T_225 = or(T_220, T_224) - node T_227 = mux(T_216, T_225, UInt<1>("h00")) - node T_228 = eq(io.roundingMode, UInt<2>("h02")) - node T_229 = and(sign, roundInexact) - node T_231 = mux(T_228, T_229, UInt<1>("h00")) - node T_232 = or(T_227, T_231) - node T_233 = eq(io.roundingMode, UInt<2>("h03")) - node T_235 = eq(sign, UInt<1>("h00")) - node T_236 = and(T_235, roundInexact) - node T_238 = mux(T_233, T_236, UInt<1>("h00")) - node round = or(T_232, T_238) - node T_241 = bits(normAbsIn, 63, 40) - node unroundedNorm = cat(UInt<1>("h00"), T_241) - node T_245 = add(unroundedNorm, UInt<1>("h01")) - node T_246 = tail(T_245, 1) - node roundedNorm = mux(round, T_246, unroundedNorm) - node T_249 = not(normCount) - node unroundedExp = cat(UInt<1>("h00"), T_249) - node T_253 = cat(UInt<1>("h00"), unroundedExp) - node T_254 = bits(roundedNorm, 24, 24) - node T_255 = add(T_253, T_254) - node roundedExp = tail(T_255, 1) - node T_258 = bits(normAbsIn, 63, 63) - node T_260 = bits(roundedExp, 7, 0) - node T_261 = mux(UInt<1>("h00"), UInt<8>("h080"), T_260) - node expOut = cat(T_258, T_261) - node overflow = or(UInt<1>("h00"), UInt<1>("h00")) - node inexact = or(roundInexact, overflow) - node T_265 = bits(roundedNorm, 22, 0) - node T_266 = cat(expOut, T_265) - node T_267 = cat(sign, T_266) - io.out <= T_267 - node T_270 = cat(UInt<2>("h00"), overflow) - node T_271 = cat(UInt<1>("h00"), inexact) - node T_272 = cat(T_270, T_271) - io.exceptionFlags <= T_272 - - module INToRecFN_119 : - input clk : Clock + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] + + module Queue_53 : + input clock : Clock input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} io is invalid - node T_9 = bits(io.in, 63, 63) - node sign = and(io.signedIn, T_9) - node T_12 = sub(UInt<1>("h00"), io.in) - node T_13 = tail(T_12, 1) - node absIn = mux(sign, T_13, io.in) - node T_15 = shl(absIn, 0) - node T_16 = bits(T_15, 63, 63) - node T_18 = bits(T_15, 62, 62) - node T_20 = bits(T_15, 61, 61) - node T_22 = bits(T_15, 60, 60) - node T_24 = bits(T_15, 59, 59) - node T_26 = bits(T_15, 58, 58) - node T_28 = bits(T_15, 57, 57) - node T_30 = bits(T_15, 56, 56) - node T_32 = bits(T_15, 55, 55) - node T_34 = bits(T_15, 54, 54) - node T_36 = bits(T_15, 53, 53) - node T_38 = bits(T_15, 52, 52) - node T_40 = bits(T_15, 51, 51) - node T_42 = bits(T_15, 50, 50) - node T_44 = bits(T_15, 49, 49) - node T_46 = bits(T_15, 48, 48) - node T_48 = bits(T_15, 47, 47) - node T_50 = bits(T_15, 46, 46) - node T_52 = bits(T_15, 45, 45) - node T_54 = bits(T_15, 44, 44) - node T_56 = bits(T_15, 43, 43) - node T_58 = bits(T_15, 42, 42) - node T_60 = bits(T_15, 41, 41) - node T_62 = bits(T_15, 40, 40) - node T_64 = bits(T_15, 39, 39) - node T_66 = bits(T_15, 38, 38) - node T_68 = bits(T_15, 37, 37) - node T_70 = bits(T_15, 36, 36) - node T_72 = bits(T_15, 35, 35) - node T_74 = bits(T_15, 34, 34) - node T_76 = bits(T_15, 33, 33) - node T_78 = bits(T_15, 32, 32) - node T_80 = bits(T_15, 31, 31) - node T_82 = bits(T_15, 30, 30) - node T_84 = bits(T_15, 29, 29) - node T_86 = bits(T_15, 28, 28) - node T_88 = bits(T_15, 27, 27) - node T_90 = bits(T_15, 26, 26) - node T_92 = bits(T_15, 25, 25) - node T_94 = bits(T_15, 24, 24) - node T_96 = bits(T_15, 23, 23) - node T_98 = bits(T_15, 22, 22) - node T_100 = bits(T_15, 21, 21) - node T_102 = bits(T_15, 20, 20) - node T_104 = bits(T_15, 19, 19) - node T_106 = bits(T_15, 18, 18) - node T_108 = bits(T_15, 17, 17) - node T_110 = bits(T_15, 16, 16) - node T_112 = bits(T_15, 15, 15) - node T_114 = bits(T_15, 14, 14) - node T_116 = bits(T_15, 13, 13) - node T_118 = bits(T_15, 12, 12) - node T_120 = bits(T_15, 11, 11) - node T_122 = bits(T_15, 10, 10) - node T_124 = bits(T_15, 9, 9) - node T_126 = bits(T_15, 8, 8) - node T_128 = bits(T_15, 7, 7) - node T_130 = bits(T_15, 6, 6) - node T_132 = bits(T_15, 5, 5) - node T_134 = bits(T_15, 4, 4) - node T_136 = bits(T_15, 3, 3) - node T_138 = bits(T_15, 2, 2) - node T_140 = bits(T_15, 1, 1) - node T_141 = shl(T_140, 0) - node T_142 = mux(T_138, UInt<2>("h02"), T_141) - node T_143 = mux(T_136, UInt<2>("h03"), T_142) - node T_144 = mux(T_134, UInt<3>("h04"), T_143) - node T_145 = mux(T_132, UInt<3>("h05"), T_144) - node T_146 = mux(T_130, UInt<3>("h06"), T_145) - node T_147 = mux(T_128, UInt<3>("h07"), T_146) - node T_148 = mux(T_126, UInt<4>("h08"), T_147) - node T_149 = mux(T_124, UInt<4>("h09"), T_148) - node T_150 = mux(T_122, UInt<4>("h0a"), T_149) - node T_151 = mux(T_120, UInt<4>("h0b"), T_150) - node T_152 = mux(T_118, UInt<4>("h0c"), T_151) - node T_153 = mux(T_116, UInt<4>("h0d"), T_152) - node T_154 = mux(T_114, UInt<4>("h0e"), T_153) - node T_155 = mux(T_112, UInt<4>("h0f"), T_154) - node T_156 = mux(T_110, UInt<5>("h010"), T_155) - node T_157 = mux(T_108, UInt<5>("h011"), T_156) - node T_158 = mux(T_106, UInt<5>("h012"), T_157) - node T_159 = mux(T_104, UInt<5>("h013"), T_158) - node T_160 = mux(T_102, UInt<5>("h014"), T_159) - node T_161 = mux(T_100, UInt<5>("h015"), T_160) - node T_162 = mux(T_98, UInt<5>("h016"), T_161) - node T_163 = mux(T_96, UInt<5>("h017"), T_162) - node T_164 = mux(T_94, UInt<5>("h018"), T_163) - node T_165 = mux(T_92, UInt<5>("h019"), T_164) - node T_166 = mux(T_90, UInt<5>("h01a"), T_165) - node T_167 = mux(T_88, UInt<5>("h01b"), T_166) - node T_168 = mux(T_86, UInt<5>("h01c"), T_167) - node T_169 = mux(T_84, UInt<5>("h01d"), T_168) - node T_170 = mux(T_82, UInt<5>("h01e"), T_169) - node T_171 = mux(T_80, UInt<5>("h01f"), T_170) - node T_172 = mux(T_78, UInt<6>("h020"), T_171) - node T_173 = mux(T_76, UInt<6>("h021"), T_172) - node T_174 = mux(T_74, UInt<6>("h022"), T_173) - node T_175 = mux(T_72, UInt<6>("h023"), T_174) - node T_176 = mux(T_70, UInt<6>("h024"), T_175) - node T_177 = mux(T_68, UInt<6>("h025"), T_176) - node T_178 = mux(T_66, UInt<6>("h026"), T_177) - node T_179 = mux(T_64, UInt<6>("h027"), T_178) - node T_180 = mux(T_62, UInt<6>("h028"), T_179) - node T_181 = mux(T_60, UInt<6>("h029"), T_180) - node T_182 = mux(T_58, UInt<6>("h02a"), T_181) - node T_183 = mux(T_56, UInt<6>("h02b"), T_182) - node T_184 = mux(T_54, UInt<6>("h02c"), T_183) - node T_185 = mux(T_52, UInt<6>("h02d"), T_184) - node T_186 = mux(T_50, UInt<6>("h02e"), T_185) - node T_187 = mux(T_48, UInt<6>("h02f"), T_186) - node T_188 = mux(T_46, UInt<6>("h030"), T_187) - node T_189 = mux(T_44, UInt<6>("h031"), T_188) - node T_190 = mux(T_42, UInt<6>("h032"), T_189) - node T_191 = mux(T_40, UInt<6>("h033"), T_190) - node T_192 = mux(T_38, UInt<6>("h034"), T_191) - node T_193 = mux(T_36, UInt<6>("h035"), T_192) - node T_194 = mux(T_34, UInt<6>("h036"), T_193) - node T_195 = mux(T_32, UInt<6>("h037"), T_194) - node T_196 = mux(T_30, UInt<6>("h038"), T_195) - node T_197 = mux(T_28, UInt<6>("h039"), T_196) - node T_198 = mux(T_26, UInt<6>("h03a"), T_197) - node T_199 = mux(T_24, UInt<6>("h03b"), T_198) - node T_200 = mux(T_22, UInt<6>("h03c"), T_199) - node T_201 = mux(T_20, UInt<6>("h03d"), T_200) - node T_202 = mux(T_18, UInt<6>("h03e"), T_201) - node T_203 = mux(T_16, UInt<6>("h03f"), T_202) - node normCount = not(T_203) - node T_205 = dshl(absIn, normCount) - node normAbsIn = bits(T_205, 63, 0) - node T_208 = bits(normAbsIn, 11, 10) - node T_209 = bits(normAbsIn, 9, 0) - node T_211 = neq(T_209, UInt<1>("h00")) - node roundBits = cat(T_208, T_211) - node T_213 = bits(roundBits, 1, 0) - node roundInexact = neq(T_213, UInt<1>("h00")) - node T_216 = eq(io.roundingMode, UInt<2>("h00")) - node T_217 = bits(roundBits, 2, 1) - node T_218 = not(T_217) - node T_220 = eq(T_218, UInt<1>("h00")) - node T_221 = bits(roundBits, 1, 0) - node T_222 = not(T_221) - node T_224 = eq(T_222, UInt<1>("h00")) - node T_225 = or(T_220, T_224) - node T_227 = mux(T_216, T_225, UInt<1>("h00")) - node T_228 = eq(io.roundingMode, UInt<2>("h02")) - node T_229 = and(sign, roundInexact) - node T_231 = mux(T_228, T_229, UInt<1>("h00")) - node T_232 = or(T_227, T_231) - node T_233 = eq(io.roundingMode, UInt<2>("h03")) - node T_235 = eq(sign, UInt<1>("h00")) - node T_236 = and(T_235, roundInexact) - node T_238 = mux(T_233, T_236, UInt<1>("h00")) - node round = or(T_232, T_238) - node T_241 = bits(normAbsIn, 63, 11) - node unroundedNorm = cat(UInt<1>("h00"), T_241) - node T_245 = add(unroundedNorm, UInt<1>("h01")) - node T_246 = tail(T_245, 1) - node roundedNorm = mux(round, T_246, unroundedNorm) - node T_249 = not(normCount) - node unroundedExp = cat(UInt<4>("h00"), T_249) - node T_253 = cat(UInt<1>("h00"), unroundedExp) - node T_254 = bits(roundedNorm, 53, 53) - node T_255 = add(T_253, T_254) - node roundedExp = tail(T_255, 1) - node T_258 = bits(normAbsIn, 63, 63) - node T_260 = bits(roundedExp, 10, 0) - node T_261 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_260) - node expOut = cat(T_258, T_261) - node overflow = or(UInt<1>("h00"), UInt<1>("h00")) - node inexact = or(roundInexact, overflow) - node T_265 = bits(roundedNorm, 51, 0) - node T_266 = cat(expOut, T_265) - node T_267 = cat(sign, T_266) - io.out <= T_267 - node T_270 = cat(UInt<2>("h00"), overflow) - node T_271 = cat(UInt<1>("h00"), inexact) - node T_272 = cat(T_270, T_271) - io.exceptionFlags <= T_272 + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] - module IntToFP : - input clk : Clock + module Queue_54 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<1>} io is invalid - reg T_136 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_136 <= io.in.valid - reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : - T_137 <- io.in.bits - skip - wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in is invalid - in.valid <= T_136 - in.bits <- T_137 - wire mux : {data : UInt<65>, exc : UInt<5>} - mux is invalid - mux.exc <= UInt<1>("h00") - node T_263 = bits(in.bits.in1, 63, 63) - node T_264 = bits(in.bits.in1, 62, 52) - node T_265 = bits(in.bits.in1, 51, 0) - node T_267 = eq(T_264, UInt<1>("h00")) - node T_269 = eq(T_265, UInt<1>("h00")) - node T_270 = and(T_267, T_269) - node T_271 = shl(T_265, 12) - node T_272 = bits(T_271, 63, 63) - node T_274 = bits(T_271, 62, 62) - node T_276 = bits(T_271, 61, 61) - node T_278 = bits(T_271, 60, 60) - node T_280 = bits(T_271, 59, 59) - node T_282 = bits(T_271, 58, 58) - node T_284 = bits(T_271, 57, 57) - node T_286 = bits(T_271, 56, 56) - node T_288 = bits(T_271, 55, 55) - node T_290 = bits(T_271, 54, 54) - node T_292 = bits(T_271, 53, 53) - node T_294 = bits(T_271, 52, 52) - node T_296 = bits(T_271, 51, 51) - node T_298 = bits(T_271, 50, 50) - node T_300 = bits(T_271, 49, 49) - node T_302 = bits(T_271, 48, 48) - node T_304 = bits(T_271, 47, 47) - node T_306 = bits(T_271, 46, 46) - node T_308 = bits(T_271, 45, 45) - node T_310 = bits(T_271, 44, 44) - node T_312 = bits(T_271, 43, 43) - node T_314 = bits(T_271, 42, 42) - node T_316 = bits(T_271, 41, 41) - node T_318 = bits(T_271, 40, 40) - node T_320 = bits(T_271, 39, 39) - node T_322 = bits(T_271, 38, 38) - node T_324 = bits(T_271, 37, 37) - node T_326 = bits(T_271, 36, 36) - node T_328 = bits(T_271, 35, 35) - node T_330 = bits(T_271, 34, 34) - node T_332 = bits(T_271, 33, 33) - node T_334 = bits(T_271, 32, 32) - node T_336 = bits(T_271, 31, 31) - node T_338 = bits(T_271, 30, 30) - node T_340 = bits(T_271, 29, 29) - node T_342 = bits(T_271, 28, 28) - node T_344 = bits(T_271, 27, 27) - node T_346 = bits(T_271, 26, 26) - node T_348 = bits(T_271, 25, 25) - node T_350 = bits(T_271, 24, 24) - node T_352 = bits(T_271, 23, 23) - node T_354 = bits(T_271, 22, 22) - node T_356 = bits(T_271, 21, 21) - node T_358 = bits(T_271, 20, 20) - node T_360 = bits(T_271, 19, 19) - node T_362 = bits(T_271, 18, 18) - node T_364 = bits(T_271, 17, 17) - node T_366 = bits(T_271, 16, 16) - node T_368 = bits(T_271, 15, 15) - node T_370 = bits(T_271, 14, 14) - node T_372 = bits(T_271, 13, 13) - node T_374 = bits(T_271, 12, 12) - node T_376 = bits(T_271, 11, 11) - node T_378 = bits(T_271, 10, 10) - node T_380 = bits(T_271, 9, 9) - node T_382 = bits(T_271, 8, 8) - node T_384 = bits(T_271, 7, 7) - node T_386 = bits(T_271, 6, 6) - node T_388 = bits(T_271, 5, 5) - node T_390 = bits(T_271, 4, 4) - node T_392 = bits(T_271, 3, 3) - node T_394 = bits(T_271, 2, 2) - node T_396 = bits(T_271, 1, 1) - node T_397 = shl(T_396, 0) - node T_398 = mux(T_394, UInt<2>("h02"), T_397) - node T_399 = mux(T_392, UInt<2>("h03"), T_398) - node T_400 = mux(T_390, UInt<3>("h04"), T_399) - node T_401 = mux(T_388, UInt<3>("h05"), T_400) - node T_402 = mux(T_386, UInt<3>("h06"), T_401) - node T_403 = mux(T_384, UInt<3>("h07"), T_402) - node T_404 = mux(T_382, UInt<4>("h08"), T_403) - node T_405 = mux(T_380, UInt<4>("h09"), T_404) - node T_406 = mux(T_378, UInt<4>("h0a"), T_405) - node T_407 = mux(T_376, UInt<4>("h0b"), T_406) - node T_408 = mux(T_374, UInt<4>("h0c"), T_407) - node T_409 = mux(T_372, UInt<4>("h0d"), T_408) - node T_410 = mux(T_370, UInt<4>("h0e"), T_409) - node T_411 = mux(T_368, UInt<4>("h0f"), T_410) - node T_412 = mux(T_366, UInt<5>("h010"), T_411) - node T_413 = mux(T_364, UInt<5>("h011"), T_412) - node T_414 = mux(T_362, UInt<5>("h012"), T_413) - node T_415 = mux(T_360, UInt<5>("h013"), T_414) - node T_416 = mux(T_358, UInt<5>("h014"), T_415) - node T_417 = mux(T_356, UInt<5>("h015"), T_416) - node T_418 = mux(T_354, UInt<5>("h016"), T_417) - node T_419 = mux(T_352, UInt<5>("h017"), T_418) - node T_420 = mux(T_350, UInt<5>("h018"), T_419) - node T_421 = mux(T_348, UInt<5>("h019"), T_420) - node T_422 = mux(T_346, UInt<5>("h01a"), T_421) - node T_423 = mux(T_344, UInt<5>("h01b"), T_422) - node T_424 = mux(T_342, UInt<5>("h01c"), T_423) - node T_425 = mux(T_340, UInt<5>("h01d"), T_424) - node T_426 = mux(T_338, UInt<5>("h01e"), T_425) - node T_427 = mux(T_336, UInt<5>("h01f"), T_426) - node T_428 = mux(T_334, UInt<6>("h020"), T_427) - node T_429 = mux(T_332, UInt<6>("h021"), T_428) - node T_430 = mux(T_330, UInt<6>("h022"), T_429) - node T_431 = mux(T_328, UInt<6>("h023"), T_430) - node T_432 = mux(T_326, UInt<6>("h024"), T_431) - node T_433 = mux(T_324, UInt<6>("h025"), T_432) - node T_434 = mux(T_322, UInt<6>("h026"), T_433) - node T_435 = mux(T_320, UInt<6>("h027"), T_434) - node T_436 = mux(T_318, UInt<6>("h028"), T_435) - node T_437 = mux(T_316, UInt<6>("h029"), T_436) - node T_438 = mux(T_314, UInt<6>("h02a"), T_437) - node T_439 = mux(T_312, UInt<6>("h02b"), T_438) - node T_440 = mux(T_310, UInt<6>("h02c"), T_439) - node T_441 = mux(T_308, UInt<6>("h02d"), T_440) - node T_442 = mux(T_306, UInt<6>("h02e"), T_441) - node T_443 = mux(T_304, UInt<6>("h02f"), T_442) - node T_444 = mux(T_302, UInt<6>("h030"), T_443) - node T_445 = mux(T_300, UInt<6>("h031"), T_444) - node T_446 = mux(T_298, UInt<6>("h032"), T_445) - node T_447 = mux(T_296, UInt<6>("h033"), T_446) - node T_448 = mux(T_294, UInt<6>("h034"), T_447) - node T_449 = mux(T_292, UInt<6>("h035"), T_448) - node T_450 = mux(T_290, UInt<6>("h036"), T_449) - node T_451 = mux(T_288, UInt<6>("h037"), T_450) - node T_452 = mux(T_286, UInt<6>("h038"), T_451) - node T_453 = mux(T_284, UInt<6>("h039"), T_452) - node T_454 = mux(T_282, UInt<6>("h03a"), T_453) - node T_455 = mux(T_280, UInt<6>("h03b"), T_454) - node T_456 = mux(T_278, UInt<6>("h03c"), T_455) - node T_457 = mux(T_276, UInt<6>("h03d"), T_456) - node T_458 = mux(T_274, UInt<6>("h03e"), T_457) - node T_459 = mux(T_272, UInt<6>("h03f"), T_458) - node T_460 = not(T_459) - node T_461 = dshl(T_265, T_460) - node T_462 = bits(T_461, 50, 0) - node T_464 = cat(T_462, UInt<1>("h00")) - node T_467 = sub(UInt<12>("h00"), UInt<1>("h01")) - node T_468 = tail(T_467, 1) - node T_469 = xor(T_460, T_468) - node T_470 = mux(T_267, T_469, T_264) - node T_474 = mux(T_267, UInt<2>("h02"), UInt<1>("h01")) - node T_475 = or(UInt<11>("h0400"), T_474) - node T_476 = add(T_470, T_475) - node T_477 = tail(T_476, 1) - node T_478 = bits(T_477, 11, 10) - node T_480 = eq(T_478, UInt<2>("h03")) - node T_482 = eq(T_269, UInt<1>("h00")) - node T_483 = and(T_480, T_482) - node T_485 = sub(UInt<3>("h00"), T_270) - node T_486 = tail(T_485, 1) - node T_487 = shl(T_486, 9) - node T_488 = not(T_487) - node T_489 = and(T_477, T_488) - node T_490 = shl(T_483, 9) - node T_491 = or(T_489, T_490) - node T_492 = mux(T_267, T_464, T_265) - node T_493 = cat(T_491, T_492) - node T_494 = cat(T_263, T_493) - mux.data <= T_494 - when in.bits.single : - node T_496 = bits(in.bits.in1, 31, 31) - node T_497 = bits(in.bits.in1, 30, 23) - node T_498 = bits(in.bits.in1, 22, 0) - node T_500 = eq(T_497, UInt<1>("h00")) - node T_502 = eq(T_498, UInt<1>("h00")) - node T_503 = and(T_500, T_502) - node T_504 = shl(T_498, 9) - node T_505 = bits(T_504, 31, 31) - node T_507 = bits(T_504, 30, 30) - node T_509 = bits(T_504, 29, 29) - node T_511 = bits(T_504, 28, 28) - node T_513 = bits(T_504, 27, 27) - node T_515 = bits(T_504, 26, 26) - node T_517 = bits(T_504, 25, 25) - node T_519 = bits(T_504, 24, 24) - node T_521 = bits(T_504, 23, 23) - node T_523 = bits(T_504, 22, 22) - node T_525 = bits(T_504, 21, 21) - node T_527 = bits(T_504, 20, 20) - node T_529 = bits(T_504, 19, 19) - node T_531 = bits(T_504, 18, 18) - node T_533 = bits(T_504, 17, 17) - node T_535 = bits(T_504, 16, 16) - node T_537 = bits(T_504, 15, 15) - node T_539 = bits(T_504, 14, 14) - node T_541 = bits(T_504, 13, 13) - node T_543 = bits(T_504, 12, 12) - node T_545 = bits(T_504, 11, 11) - node T_547 = bits(T_504, 10, 10) - node T_549 = bits(T_504, 9, 9) - node T_551 = bits(T_504, 8, 8) - node T_553 = bits(T_504, 7, 7) - node T_555 = bits(T_504, 6, 6) - node T_557 = bits(T_504, 5, 5) - node T_559 = bits(T_504, 4, 4) - node T_561 = bits(T_504, 3, 3) - node T_563 = bits(T_504, 2, 2) - node T_565 = bits(T_504, 1, 1) - node T_566 = shl(T_565, 0) - node T_567 = mux(T_563, UInt<2>("h02"), T_566) - node T_568 = mux(T_561, UInt<2>("h03"), T_567) - node T_569 = mux(T_559, UInt<3>("h04"), T_568) - node T_570 = mux(T_557, UInt<3>("h05"), T_569) - node T_571 = mux(T_555, UInt<3>("h06"), T_570) - node T_572 = mux(T_553, UInt<3>("h07"), T_571) - node T_573 = mux(T_551, UInt<4>("h08"), T_572) - node T_574 = mux(T_549, UInt<4>("h09"), T_573) - node T_575 = mux(T_547, UInt<4>("h0a"), T_574) - node T_576 = mux(T_545, UInt<4>("h0b"), T_575) - node T_577 = mux(T_543, UInt<4>("h0c"), T_576) - node T_578 = mux(T_541, UInt<4>("h0d"), T_577) - node T_579 = mux(T_539, UInt<4>("h0e"), T_578) - node T_580 = mux(T_537, UInt<4>("h0f"), T_579) - node T_581 = mux(T_535, UInt<5>("h010"), T_580) - node T_582 = mux(T_533, UInt<5>("h011"), T_581) - node T_583 = mux(T_531, UInt<5>("h012"), T_582) - node T_584 = mux(T_529, UInt<5>("h013"), T_583) - node T_585 = mux(T_527, UInt<5>("h014"), T_584) - node T_586 = mux(T_525, UInt<5>("h015"), T_585) - node T_587 = mux(T_523, UInt<5>("h016"), T_586) - node T_588 = mux(T_521, UInt<5>("h017"), T_587) - node T_589 = mux(T_519, UInt<5>("h018"), T_588) - node T_590 = mux(T_517, UInt<5>("h019"), T_589) - node T_591 = mux(T_515, UInt<5>("h01a"), T_590) - node T_592 = mux(T_513, UInt<5>("h01b"), T_591) - node T_593 = mux(T_511, UInt<5>("h01c"), T_592) - node T_594 = mux(T_509, UInt<5>("h01d"), T_593) - node T_595 = mux(T_507, UInt<5>("h01e"), T_594) - node T_596 = mux(T_505, UInt<5>("h01f"), T_595) - node T_597 = not(T_596) - node T_598 = dshl(T_498, T_597) - node T_599 = bits(T_598, 21, 0) - node T_601 = cat(T_599, UInt<1>("h00")) - node T_604 = sub(UInt<9>("h00"), UInt<1>("h01")) - node T_605 = tail(T_604, 1) - node T_606 = xor(T_597, T_605) - node T_607 = mux(T_500, T_606, T_497) - node T_611 = mux(T_500, UInt<2>("h02"), UInt<1>("h01")) - node T_612 = or(UInt<8>("h080"), T_611) - node T_613 = add(T_607, T_612) - node T_614 = tail(T_613, 1) - node T_615 = bits(T_614, 8, 7) - node T_617 = eq(T_615, UInt<2>("h03")) - node T_619 = eq(T_502, UInt<1>("h00")) - node T_620 = and(T_617, T_619) - node T_622 = sub(UInt<3>("h00"), T_503) - node T_623 = tail(T_622, 1) - node T_624 = shl(T_623, 6) - node T_625 = not(T_624) - node T_626 = and(T_614, T_625) - node T_627 = shl(T_620, 6) - node T_628 = or(T_626, T_627) - node T_629 = mux(T_500, T_601, T_498) - node T_630 = cat(T_628, T_629) - node T_631 = cat(T_496, T_630) - node T_632 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_633 = cat(T_632, T_631) - mux.data <= T_633 - skip - node T_634 = bits(in.bits.typ, 1, 1) - node T_635 = asSInt(in.bits.in1) - node T_636 = bits(in.bits.typ, 0, 0) - node T_637 = bits(in.bits.in1, 31, 0) - node T_638 = cvt(T_637) - node T_639 = bits(in.bits.in1, 31, 0) - node T_640 = asSInt(T_639) - node T_641 = mux(T_636, T_638, T_640) - node longValue = mux(T_634, T_635, T_641) - inst l2s of INToRecFN - l2s.io is invalid - l2s.clk <= clk - l2s.reset <= reset - node T_644 = bits(in.bits.typ, 0, 0) - node T_645 = not(T_644) - l2s.io.signedIn <= T_645 - node T_646 = asUInt(longValue) - l2s.io.in <= T_646 - l2s.io.roundingMode <= in.bits.rm - inst l2d of INToRecFN_119 - l2d.io is invalid - l2d.clk <= clk - l2d.reset <= reset - node T_648 = bits(in.bits.typ, 0, 0) - node T_649 = not(T_648) - l2d.io.signedIn <= T_649 - node T_650 = asUInt(longValue) - l2d.io.in <= T_650 - l2d.io.roundingMode <= in.bits.rm - node T_653 = and(in.bits.cmd, UInt<3>("h04")) - node T_654 = eq(UInt<1>("h00"), T_653) - when T_654 : - when in.bits.single : - node T_656 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_657 = cat(T_656, l2s.io.out) - mux.data <= T_657 - mux.exc <= l2s.io.exceptionFlags - skip - node T_659 = eq(in.bits.single, UInt<1>("h00")) - when T_659 : - mux.data <= l2d.io.out - mux.exc <= l2d.io.exceptionFlags - skip - skip - reg T_662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_662 <= in.valid - reg T_663 : {data : UInt<65>, exc : UInt<5>}, clk - when in.valid : - T_663 <- mux - skip - reg T_668 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_668 <= T_662 - reg T_669 : {data : UInt<65>, exc : UInt<5>}, clk - when T_662 : - T_669 <- T_663 - skip - wire T_680 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_680 is invalid - T_680.valid <= T_668 - T_680.bits <- T_669 - io.out <- T_680 + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_90 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_92 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_93 = and(_T_90, _T_92) @[Decoupled.scala 188:33] + node _T_94 = and(_T_90, maybe_full) @[Decoupled.scala 189:32] + node _T_95 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_95 + node _T_96 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_96 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_98 = ram[UInt<1>("h00")], clock + _T_98 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_110 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_110 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_112 = eq(_T_93, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_112 @[Decoupled.scala 204:16] + node _T_114 = eq(_T_94, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_114 @[Decoupled.scala 205:16] + infer mport _T_116 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_116 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_93 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_129 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_130 = asUInt(_T_129) @[Decoupled.scala 221:40] + node _T_131 = tail(_T_130, 1) @[Decoupled.scala 221:40] + node _T_132 = and(maybe_full, _T_90) @[Decoupled.scala 223:32] + node _T_133 = cat(_T_132, _T_131) @[Cat.scala 30:58] + io.count <= _T_133 @[Decoupled.scala 223:14] - module RoundRawFNToRecFN : - input clk : Clock + module Queue_55 : + input clock : Clock input reset : UInt<1> - output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<1>} io is invalid - node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) - node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) - node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) - node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) - node T_27 = and(roundingMode_min, io.in.sign) - node T_28 = not(io.in.sign) - node T_29 = and(roundingMode_max, T_28) - node roundMagUp = or(T_27, T_29) - node doShiftSigDown1 = bits(io.in.sig, 26, 26) - node T_33 = lt(io.in.sExp, asSInt(UInt<1>("h00"))) - node T_35 = sub(UInt<25>("h00"), T_33) - node T_36 = tail(T_35, 1) - node T_37 = bits(io.in.sExp, 8, 0) - node T_38 = not(T_37) - node T_40 = dshr(asSInt(UInt<513>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_38) - node T_41 = bits(T_40, 130, 106) - node T_42 = bits(T_41, 15, 0) - node T_45 = shl(UInt<8>("h0ff"), 8) - node T_46 = xor(UInt<16>("h0ffff"), T_45) - node T_47 = shr(T_42, 8) - node T_48 = and(T_47, T_46) - node T_49 = bits(T_42, 7, 0) - node T_50 = shl(T_49, 8) - node T_51 = not(T_46) - node T_52 = and(T_50, T_51) - node T_53 = or(T_48, T_52) - node T_54 = bits(T_46, 11, 0) - node T_55 = shl(T_54, 4) - node T_56 = xor(T_46, T_55) - node T_57 = shr(T_53, 4) - node T_58 = and(T_57, T_56) - node T_59 = bits(T_53, 11, 0) - node T_60 = shl(T_59, 4) - node T_61 = not(T_56) - node T_62 = and(T_60, T_61) - node T_63 = or(T_58, T_62) - node T_64 = bits(T_56, 13, 0) - node T_65 = shl(T_64, 2) - node T_66 = xor(T_56, T_65) - node T_67 = shr(T_63, 2) - node T_68 = and(T_67, T_66) - node T_69 = bits(T_63, 13, 0) - node T_70 = shl(T_69, 2) - node T_71 = not(T_66) - node T_72 = and(T_70, T_71) - node T_73 = or(T_68, T_72) - node T_74 = bits(T_66, 14, 0) - node T_75 = shl(T_74, 1) - node T_76 = xor(T_66, T_75) - node T_77 = shr(T_73, 1) - node T_78 = and(T_77, T_76) - node T_79 = bits(T_73, 14, 0) - node T_80 = shl(T_79, 1) - node T_81 = not(T_76) - node T_82 = and(T_80, T_81) - node T_83 = or(T_78, T_82) - node T_84 = bits(T_41, 24, 16) - node T_85 = bits(T_84, 7, 0) - node T_88 = shl(UInt<4>("h0f"), 4) - node T_89 = xor(UInt<8>("h0ff"), T_88) - node T_90 = shr(T_85, 4) - node T_91 = and(T_90, T_89) - node T_92 = bits(T_85, 3, 0) - node T_93 = shl(T_92, 4) - node T_94 = not(T_89) - node T_95 = and(T_93, T_94) - node T_96 = or(T_91, T_95) - node T_97 = bits(T_89, 5, 0) - node T_98 = shl(T_97, 2) - node T_99 = xor(T_89, T_98) - node T_100 = shr(T_96, 2) - node T_101 = and(T_100, T_99) - node T_102 = bits(T_96, 5, 0) - node T_103 = shl(T_102, 2) - node T_104 = not(T_99) - node T_105 = and(T_103, T_104) - node T_106 = or(T_101, T_105) - node T_107 = bits(T_99, 6, 0) - node T_108 = shl(T_107, 1) - node T_109 = xor(T_99, T_108) - node T_110 = shr(T_106, 1) - node T_111 = and(T_110, T_109) - node T_112 = bits(T_106, 6, 0) - node T_113 = shl(T_112, 1) - node T_114 = not(T_109) - node T_115 = and(T_113, T_114) - node T_116 = or(T_111, T_115) - node T_117 = bits(T_84, 8, 8) - node T_118 = cat(T_116, T_117) - node T_119 = cat(T_83, T_118) - node T_120 = or(T_36, T_119) - node T_121 = or(T_120, doShiftSigDown1) - node roundMask = cat(T_121, UInt<2>("h03")) - node T_124 = shr(roundMask, 1) - node T_125 = not(T_124) - node roundPosMask = and(T_125, roundMask) - node T_127 = and(io.in.sig, roundPosMask) - node roundPosBit = neq(T_127, UInt<1>("h00")) - node T_130 = shr(roundMask, 1) - node T_131 = and(io.in.sig, T_130) - node anyRoundExtra = neq(T_131, UInt<1>("h00")) - node common_inexact = or(roundPosBit, anyRoundExtra) - node T_135 = and(roundingMode_nearest_even, roundPosBit) - node T_136 = and(roundMagUp, common_inexact) - node T_137 = or(T_135, T_136) - node T_138 = or(io.in.sig, roundMask) - node T_139 = shr(T_138, 2) - node T_141 = add(T_139, UInt<1>("h01")) - node T_142 = tail(T_141, 1) - node T_143 = and(roundingMode_nearest_even, roundPosBit) - node T_144 = not(anyRoundExtra) - node T_145 = and(T_143, T_144) - node T_146 = shr(roundMask, 1) - node T_148 = mux(T_145, T_146, UInt<26>("h00")) - node T_149 = not(T_148) - node T_150 = and(T_142, T_149) - node T_151 = not(roundMask) - node T_152 = and(io.in.sig, T_151) - node T_153 = shr(T_152, 2) - node roundedSig = mux(T_137, T_150, T_153) - node T_155 = shr(roundedSig, 24) - node T_156 = cvt(T_155) - node T_157 = add(io.in.sExp, T_156) - node T_158 = tail(T_157, 1) - node sRoundedExp = asSInt(T_158) - node common_expOut = bits(sRoundedExp, 8, 0) - node T_161 = bits(roundedSig, 23, 1) - node T_162 = bits(roundedSig, 22, 0) - node common_fractOut = mux(doShiftSigDown1, T_161, T_162) - node T_164 = shr(sRoundedExp, 7) - node common_overflow = geq(T_164, asSInt(UInt<3>("h03"))) - node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) - node T_171 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) - node T_172 = lt(io.in.sExp, T_171) - node common_underflow = and(common_inexact, T_172) - node isNaNOut = or(io.invalidExc, io.in.isNaN) - node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) - node T_176 = not(isNaNOut) - node T_177 = not(notNaN_isSpecialInfOut) - node T_178 = and(T_176, T_177) - node T_179 = not(io.in.isZero) - node commonCase = and(T_178, T_179) - node overflow = and(commonCase, common_overflow) - node underflow = and(commonCase, common_underflow) - node T_183 = and(commonCase, common_inexact) - node inexact = or(overflow, T_183) - node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node T_186 = and(commonCase, common_totalUnderflow) - node pegMinNonzeroMagOut = and(T_186, roundMagUp) - node T_188 = and(commonCase, overflow) - node T_189 = not(overflow_roundMagUp) - node pegMaxFiniteMagOut = and(T_188, T_189) - node T_191 = and(overflow, overflow_roundMagUp) - node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_191) - node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) - node T_195 = or(io.in.isZero, common_totalUnderflow) - node T_198 = mux(T_195, UInt<9>("h01c0"), UInt<1>("h00")) - node T_199 = not(T_198) - node T_200 = and(common_expOut, T_199) - node T_202 = not(UInt<9>("h06b")) - node T_204 = mux(pegMinNonzeroMagOut, T_202, UInt<1>("h00")) - node T_205 = not(T_204) - node T_206 = and(T_200, T_205) - node T_209 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) - node T_210 = not(T_209) - node T_211 = and(T_206, T_210) - node T_214 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) - node T_215 = not(T_214) - node T_216 = and(T_211, T_215) - node T_219 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) - node T_220 = or(T_216, T_219) - node T_223 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) - node T_224 = or(T_220, T_223) - node T_227 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) - node T_228 = or(T_224, T_227) - node T_231 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) - node expOut = or(T_228, T_231) - node T_233 = and(common_totalUnderflow, roundMagUp) - node T_234 = or(T_233, isNaNOut) - node T_236 = mux(T_234, UInt<1>("h00"), common_fractOut) - node T_238 = sub(UInt<23>("h00"), pegMaxFiniteMagOut) - node T_239 = tail(T_238, 1) - node T_240 = or(T_236, T_239) - node T_241 = shl(isNaNOut, 22) - node fractOut = or(T_240, T_241) - node T_243 = cat(expOut, fractOut) - node T_244 = cat(signOut, T_243) - io.out <= T_244 - node T_245 = cat(io.invalidExc, io.infiniteExc) - node T_246 = cat(underflow, inexact) - node T_247 = cat(overflow, T_246) - node T_248 = cat(T_245, T_247) - io.exceptionFlags <= T_248 - - module RecFNToRecFN_121 : - input clk : Clock + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[1] @[Decoupled.scala 182:24] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 187:41] + node _T_43 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_44 = and(_T_41, _T_43) @[Decoupled.scala 188:33] + node _T_45 = and(_T_41, maybe_full) @[Decoupled.scala 189:32] + node _T_46 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_46 + node _T_47 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_47 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_49 = ram[UInt<1>("h00")], clock + _T_49 <- io.enq.bits @[Decoupled.scala 194:24] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + skip @[Decoupled.scala 197:17] + node _T_54 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_54 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_56 = eq(_T_44, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_56 @[Decoupled.scala 204:16] + node _T_58 = eq(_T_45, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_58 @[Decoupled.scala 205:16] + infer mport _T_60 = ram[UInt<1>("h00")], clock + io.deq.bits <- _T_60 @[Decoupled.scala 206:15] + when io.enq.valid : @[Decoupled.scala 209:25] + io.deq.valid <= UInt<1>("h01") @[Decoupled.scala 209:40] + skip @[Decoupled.scala 209:25] + when _T_44 : @[Decoupled.scala 210:18] + io.deq.bits <- io.enq.bits @[Decoupled.scala 211:19] + do_deq <= UInt<1>("h00") @[Decoupled.scala 212:14] + when io.deq.ready : @[Decoupled.scala 213:27] + do_enq <= UInt<1>("h00") @[Decoupled.scala 213:36] + skip @[Decoupled.scala 213:27] + skip @[Decoupled.scala 210:18] + node _T_66 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 221:40] + node _T_67 = asUInt(_T_66) @[Decoupled.scala 221:40] + node _T_68 = tail(_T_67, 1) @[Decoupled.scala 221:40] + node _T_69 = and(maybe_full, _T_41) @[Decoupled.scala 223:32] + node _T_70 = cat(_T_69, _T_68) @[Cat.scala 30:58] + io.count <= _T_70 @[Decoupled.scala 223:14] + + module AXI4FragmenterAXI4FragmenterSideband_4 : + input clock : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<3>} io is invalid - node T_8 = bits(io.in, 63, 52) - node T_9 = bits(T_8, 11, 10) - node T_11 = eq(T_9, UInt<2>("h03")) - wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - T_19 is invalid - node T_26 = bits(io.in, 64, 64) - T_19.sign <= T_26 - node T_27 = bits(T_8, 9, 9) - node T_28 = and(T_11, T_27) - T_19.isNaN <= T_28 - node T_29 = bits(T_8, 9, 9) - node T_31 = eq(T_29, UInt<1>("h00")) - node T_32 = and(T_11, T_31) - T_19.isInf <= T_32 - node T_33 = bits(T_8, 11, 9) - node T_35 = eq(T_33, UInt<1>("h00")) - T_19.isZero <= T_35 - node T_36 = cvt(T_8) - T_19.sExp <= T_36 - node T_38 = bits(io.in, 51, 0) - node T_40 = cat(T_38, UInt<2>("h00")) - node T_41 = cat(UInt<2>("h01"), T_40) - T_19.sig <= T_41 - node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0900"))) - node T_44 = tail(T_43, 1) - node T_45 = asSInt(T_44) - wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - outRawFloat is invalid - outRawFloat.sign <= T_19.sign - outRawFloat.isNaN <= T_19.isNaN - outRawFloat.isInf <= T_19.isInf - outRawFloat.isZero <= T_19.isZero - node T_61 = lt(T_45, asSInt(UInt<1>("h00"))) - node T_62 = bits(T_45, 11, 9) - node T_64 = neq(T_62, UInt<1>("h00")) - node T_66 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_67 = cat(T_66, T_66) - node T_68 = cat(T_66, T_67) - node T_69 = cat(UInt<1>("h01"), T_68) - node T_71 = cat(T_69, UInt<2>("h00")) - node T_72 = bits(T_45, 8, 0) - node T_73 = mux(T_64, T_71, T_72) - node T_74 = cat(T_61, T_73) - node T_75 = asSInt(T_74) - outRawFloat.sExp <= T_75 - node T_76 = bits(T_19.sig, 55, 30) - node T_77 = bits(T_19.sig, 29, 0) - node T_79 = neq(T_77, UInt<1>("h00")) - node T_80 = cat(T_76, T_79) - outRawFloat.sig <= T_80 - node T_81 = bits(outRawFloat.sig, 24, 24) - node T_83 = eq(T_81, UInt<1>("h00")) - node invalidExc = and(outRawFloat.isNaN, T_83) - inst T_85 of RoundRawFNToRecFN - T_85.io is invalid - T_85.clk <= clk - T_85.reset <= reset - T_85.io.invalidExc <= invalidExc - T_85.io.infiniteExc <= UInt<1>("h00") - T_85.io.in <- outRawFloat - T_85.io.roundingMode <= io.roundingMode - io.out <= T_85.io.out - io.exceptionFlags <= T_85.io.exceptionFlags + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<2>("h03")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] - module FPToFP : - input clk : Clock + module AXI4FragmenterAXI4FragmenterSideband_5 : + input clock : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<3>} io is invalid - reg T_137 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_137 <= io.in.valid - reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : - T_138 <- io.in.bits - skip - wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in is invalid - in.valid <= T_137 - in.bits <- T_138 - node T_259 = and(in.bits.cmd, UInt<3>("h05")) - node isSgnj = eq(UInt<3>("h04"), T_259) - node T_261 = and(in.bits.single, isSgnj) - node T_262 = bits(in.bits.rm, 1, 1) - node T_264 = eq(T_261, UInt<1>("h00")) - node T_265 = or(T_262, T_264) - node T_266 = bits(in.bits.in1, 32, 32) - node T_267 = bits(in.bits.rm, 0, 0) - node T_268 = mux(T_265, T_266, T_267) - node T_269 = bits(in.bits.in2, 32, 32) - node T_270 = and(T_261, T_269) - node sign_s = xor(T_268, T_270) - node T_273 = eq(in.bits.single, UInt<1>("h00")) - node T_274 = and(T_273, isSgnj) - node T_275 = bits(in.bits.rm, 1, 1) - node T_277 = eq(T_274, UInt<1>("h00")) - node T_278 = or(T_275, T_277) - node T_279 = bits(in.bits.in1, 64, 64) - node T_280 = bits(in.bits.rm, 0, 0) - node T_281 = mux(T_278, T_279, T_280) - node T_282 = bits(in.bits.in2, 64, 64) - node T_283 = and(T_274, T_282) - node sign_d = xor(T_281, T_283) - node T_285 = bits(in.bits.in1, 63, 33) - node T_286 = bits(in.bits.in1, 31, 0) - node T_287 = cat(sign_d, T_285) - node T_288 = cat(sign_s, T_286) - node fsgnj = cat(T_287, T_288) - inst s2d of RecFNToRecFN - s2d.io is invalid - s2d.clk <= clk - s2d.reset <= reset - inst d2s of RecFNToRecFN_121 - d2s.io is invalid - d2s.clk <= clk - d2s.reset <= reset - s2d.io.in <= in.bits.in1 - s2d.io.roundingMode <= in.bits.rm - d2s.io.in <= in.bits.in1 - d2s.io.roundingMode <= in.bits.rm - node T_292 = bits(in.bits.in1, 31, 29) - node T_293 = not(T_292) - node T_295 = eq(T_293, UInt<1>("h00")) - node T_296 = bits(in.bits.in1, 63, 61) - node T_297 = not(T_296) - node T_299 = eq(T_297, UInt<1>("h00")) - node isnan1 = mux(in.bits.single, T_295, T_299) - node T_301 = bits(in.bits.in2, 31, 29) - node T_302 = not(T_301) - node T_304 = eq(T_302, UInt<1>("h00")) - node T_305 = bits(in.bits.in2, 63, 61) - node T_306 = not(T_305) - node T_308 = eq(T_306, UInt<1>("h00")) - node isnan2 = mux(in.bits.single, T_304, T_308) - node T_310 = bits(in.bits.in1, 22, 22) - node T_311 = bits(in.bits.in1, 51, 51) - node T_312 = mux(in.bits.single, T_310, T_311) - node T_313 = not(T_312) - node issnan1 = and(isnan1, T_313) - node T_315 = bits(in.bits.in2, 22, 22) - node T_316 = bits(in.bits.in2, 51, 51) - node T_317 = mux(in.bits.single, T_315, T_316) - node T_318 = not(T_317) - node issnan2 = and(isnan2, T_318) - node T_320 = or(issnan1, issnan2) - node minmax_exc = cat(T_320, UInt<4>("h00")) - node isMax = bits(in.bits.rm, 0, 0) - node T_324 = neq(isMax, io.lt) - node T_326 = eq(isnan1, UInt<1>("h00")) - node T_327 = and(T_324, T_326) - node isLHS = or(isnan2, T_327) - wire mux : {data : UInt<65>, exc : UInt<5>} - mux is invalid - mux.exc <= minmax_exc - mux.data <= in.bits.in2 - when isSgnj : - mux.exc <= UInt<1>("h00") - skip - node T_336 = or(isSgnj, isLHS) - when T_336 : - mux.data <= fsgnj - skip - node T_339 = and(in.bits.cmd, UInt<3>("h04")) - node T_340 = eq(UInt<1>("h00"), T_339) - when T_340 : - when in.bits.single : - node T_342 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_343 = cat(T_342, d2s.io.out) - mux.data <= T_343 - mux.exc <= d2s.io.exceptionFlags - skip - node T_345 = eq(in.bits.single, UInt<1>("h00")) - when T_345 : - mux.data <= s2d.io.out - mux.exc <= s2d.io.exceptionFlags - skip - skip - reg T_348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - T_348 <= in.valid - reg T_349 : {data : UInt<65>, exc : UInt<5>}, clk - when in.valid : - T_349 <- mux - skip - wire T_360 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_360 is invalid - T_360.valid <= T_348 - T_360.bits <- T_349 - io.out <- T_360 + io is invalid + io.count <= UInt<1>("h00") @[Fragmenter.scala 249:14] + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h02"))) @[Reg.scala 26:44] + reg count : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node full = eq(count, UInt<2>("h03")) @[Fragmenter.scala 257:23] + node empty = eq(count, UInt<1>("h00")) @[Fragmenter.scala 258:23] + node last = eq(count, UInt<1>("h01")) @[Fragmenter.scala 259:23] + node _T_31 = bits(state, 1, 1) @[Fragmenter.scala 261:25] + node _T_32 = bits(state, 0, 0) @[Fragmenter.scala 261:46] + node _T_33 = and(last, _T_32) @[Fragmenter.scala 261:38] + node _T_34 = or(_T_31, _T_33) @[Fragmenter.scala 261:29] + io.deq.bits <= _T_34 @[Fragmenter.scala 261:17] + node _T_36 = eq(empty, UInt<1>("h00")) @[Fragmenter.scala 262:21] + io.deq.valid <= _T_36 @[Fragmenter.scala 262:18] + node _T_38 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 264:21] + node _T_39 = eq(state, UInt<2>("h00")) @[Fragmenter.scala 264:47] + node _T_40 = or(empty, _T_39) @[Fragmenter.scala 264:37] + node _T_41 = eq(state, UInt<2>("h02")) @[Fragmenter.scala 264:67] + node _T_42 = and(_T_41, io.enq.bits) @[Fragmenter.scala 264:76] + node _T_43 = or(_T_40, _T_42) @[Fragmenter.scala 264:57] + node _T_44 = and(_T_38, _T_43) @[Fragmenter.scala 264:27] + io.enq.ready <= _T_44 @[Fragmenter.scala 264:18] + node _T_45 = neq(state, UInt<2>("h01")) @[Fragmenter.scala 267:19] + node _T_47 = neq(count, UInt<1>("h00")) @[Fragmenter.scala 267:37] + node _T_48 = or(_T_45, _T_47) @[Fragmenter.scala 267:28] + node _T_49 = or(_T_48, reset) @[Fragmenter.scala 267:12] + node _T_51 = eq(_T_49, UInt<1>("h00")) @[Fragmenter.scala 267:12] + when _T_51 : @[Fragmenter.scala 267:12] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:267 assert (state =/= WAIT || count =/= UInt(0))\n") @[Fragmenter.scala 267:12] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 267:12] + skip @[Fragmenter.scala 267:12] + when io.enq.valid : @[Fragmenter.scala 270:27] + io.deq.valid <= UInt<1>("h01") @[Fragmenter.scala 271:22] + when empty : @[Fragmenter.scala 272:22] + io.deq.bits <= io.enq.bits @[Fragmenter.scala 272:36] + skip @[Fragmenter.scala 272:22] + skip @[Fragmenter.scala 270:27] + node _T_53 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + node _T_54 = add(count, _T_53) @[Fragmenter.scala 276:20] + node _T_55 = tail(_T_54, 1) @[Fragmenter.scala 276:20] + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + node _T_57 = sub(_T_55, _T_56) @[Fragmenter.scala 276:36] + node _T_58 = asUInt(_T_57) @[Fragmenter.scala 276:36] + node _T_59 = tail(_T_58, 1) @[Fragmenter.scala 276:36] + count <= _T_59 @[Fragmenter.scala 276:11] + node _T_60 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_60 : @[Conditional.scala 29:59] + node _T_62 = eq(io.enq.bits, UInt<1>("h00")) @[Fragmenter.scala 278:40] + node _T_63 = and(io.enq.valid, _T_62) @[Fragmenter.scala 278:37] + node _T_64 = and(_T_63, empty) @[Fragmenter.scala 278:53] + when _T_64 : @[Fragmenter.scala 278:63] + state <= UInt<2>("h00") @[Fragmenter.scala 278:71] + skip @[Fragmenter.scala 278:63] + skip @[Conditional.scala 29:59] + node _T_65 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_65 : @[Conditional.scala 29:59] + node _T_66 = and(io.enq.valid, io.enq.bits) @[Fragmenter.scala 279:37] + node _T_68 = eq(full, UInt<1>("h00")) @[Fragmenter.scala 279:56] + node _T_69 = and(_T_66, _T_68) @[Fragmenter.scala 279:53] + when _T_69 : @[Fragmenter.scala 279:63] + node _T_70 = mux(empty, UInt<2>("h02"), UInt<2>("h01")) @[Fragmenter.scala 279:77] + state <= _T_70 @[Fragmenter.scala 279:71] + skip @[Fragmenter.scala 279:63] + skip @[Conditional.scala 29:59] + node _T_71 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_71 : @[Conditional.scala 29:59] + node _T_72 = and(last, io.deq.ready) @[Fragmenter.scala 280:29] + when _T_72 : @[Fragmenter.scala 280:63] + state <= UInt<2>("h02") @[Fragmenter.scala 280:71] + skip @[Fragmenter.scala 280:63] + skip @[Conditional.scala 29:59] - module DivSqrtRecF64_mulAddZ31 : - input clk : Clock + module AXI4Fragmenter_2 : + input clock : Clock input reset : UInt<1> - output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} io is invalid - reg valid_PA : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PA : UInt<1>, clk - reg sign_PA : UInt<1>, clk - reg specialCodeB_PA : UInt<3>, clk - reg fractB_51_PA : UInt<1>, clk - reg roundingMode_PA : UInt<2>, clk - reg specialCodeA_PA : UInt<3>, clk - reg fractA_51_PA : UInt<1>, clk - reg exp_PA : UInt<14>, clk - reg fractB_other_PA : UInt<51>, clk - reg fractA_other_PA : UInt<51>, clk - reg valid_PB : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PB : UInt<1>, clk - reg sign_PB : UInt<1>, clk - reg specialCodeA_PB : UInt<3>, clk - reg fractA_51_PB : UInt<1>, clk - reg specialCodeB_PB : UInt<3>, clk - reg fractB_51_PB : UInt<1>, clk - reg roundingMode_PB : UInt<2>, clk - reg exp_PB : UInt<14>, clk - reg fractA_0_PB : UInt<1>, clk - reg fractB_other_PB : UInt<51>, clk - reg valid_PC : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PC : UInt<1>, clk - reg sign_PC : UInt<1>, clk - reg specialCodeA_PC : UInt<3>, clk - reg fractA_51_PC : UInt<1>, clk - reg specialCodeB_PC : UInt<3>, clk - reg fractB_51_PC : UInt<1>, clk - reg roundingMode_PC : UInt<2>, clk - reg exp_PC : UInt<14>, clk - reg fractA_0_PC : UInt<1>, clk - reg fractB_other_PC : UInt<51>, clk - reg cycleNum_A : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg cycleNum_B : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg cycleNum_C : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg cycleNum_E : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg fractR0_A : UInt<9>, clk - reg hiSqrR0_A_sqrt : UInt<10>, clk - reg partNegSigma0_A : UInt<21>, clk - reg nextMulAdd9A_A : UInt<9>, clk - reg nextMulAdd9B_A : UInt<9>, clk - reg ER1_B_sqrt : UInt<17>, clk - reg ESqrR1_B_sqrt : UInt<32>, clk - reg sigX1_B : UInt<58>, clk - reg sqrSigma1_C : UInt<33>, clk - reg sigXN_C : UInt<58>, clk - reg u_C_sqrt : UInt<31>, clk - reg E_E_div : UInt<1>, clk - reg sigT_E : UInt<53>, clk - reg extraT_E : UInt<1>, clk - reg isNegRemT_E : UInt<1>, clk - reg trueEqX_E1 : UInt<1>, clk - wire ready_PA : UInt<1> - ready_PA is invalid - wire ready_PB : UInt<1> - ready_PB is invalid - wire ready_PC : UInt<1> - ready_PC is invalid - wire leaving_PA : UInt<1> - leaving_PA is invalid - wire leaving_PB : UInt<1> - leaving_PB is invalid - wire leaving_PC : UInt<1> - leaving_PC is invalid - wire cyc_B10_sqrt : UInt<1> - cyc_B10_sqrt is invalid - wire cyc_B9_sqrt : UInt<1> - cyc_B9_sqrt is invalid - wire cyc_B8_sqrt : UInt<1> - cyc_B8_sqrt is invalid - wire cyc_B7_sqrt : UInt<1> - cyc_B7_sqrt is invalid - wire cyc_B6 : UInt<1> - cyc_B6 is invalid - wire cyc_B5 : UInt<1> - cyc_B5 is invalid - wire cyc_B4 : UInt<1> - cyc_B4 is invalid - wire cyc_B3 : UInt<1> - cyc_B3 is invalid - wire cyc_B2 : UInt<1> - cyc_B2 is invalid - wire cyc_B1 : UInt<1> - cyc_B1 is invalid - wire cyc_B6_div : UInt<1> - cyc_B6_div is invalid - wire cyc_B5_div : UInt<1> - cyc_B5_div is invalid - wire cyc_B4_div : UInt<1> - cyc_B4_div is invalid - wire cyc_B3_div : UInt<1> - cyc_B3_div is invalid - wire cyc_B2_div : UInt<1> - cyc_B2_div is invalid - wire cyc_B1_div : UInt<1> - cyc_B1_div is invalid - wire cyc_B6_sqrt : UInt<1> - cyc_B6_sqrt is invalid - wire cyc_B5_sqrt : UInt<1> - cyc_B5_sqrt is invalid - wire cyc_B4_sqrt : UInt<1> - cyc_B4_sqrt is invalid - wire cyc_B3_sqrt : UInt<1> - cyc_B3_sqrt is invalid - wire cyc_B2_sqrt : UInt<1> - cyc_B2_sqrt is invalid - wire cyc_B1_sqrt : UInt<1> - cyc_B1_sqrt is invalid - wire cyc_C5 : UInt<1> - cyc_C5 is invalid - wire cyc_C4 : UInt<1> - cyc_C4 is invalid - wire valid_normalCase_leaving_PB : UInt<1> - valid_normalCase_leaving_PB is invalid - wire cyc_C2 : UInt<1> - cyc_C2 is invalid - wire cyc_C1 : UInt<1> - cyc_C1 is invalid - wire cyc_E4 : UInt<1> - cyc_E4 is invalid - wire cyc_E3 : UInt<1> - cyc_E3 is invalid - wire cyc_E2 : UInt<1> - cyc_E2 is invalid - wire cyc_E1 : UInt<1> - cyc_E1 is invalid - wire zSigma1_B4 : UInt - zSigma1_B4 is invalid - wire sigXNU_B3_CX : UInt - sigXNU_B3_CX is invalid - wire zComplSigT_C1_sqrt : UInt - zComplSigT_C1_sqrt is invalid - wire zComplSigT_C1 : UInt - zComplSigT_C1 is invalid - node T_210 = not(cyc_B7_sqrt) - node T_211 = and(ready_PA, T_210) - node T_212 = not(cyc_B6_sqrt) - node T_213 = and(T_211, T_212) - node T_214 = not(cyc_B5_sqrt) - node T_215 = and(T_213, T_214) - node T_216 = not(cyc_B4_sqrt) - node T_217 = and(T_215, T_216) - node T_218 = not(cyc_B3) - node T_219 = and(T_217, T_218) - node T_220 = not(cyc_B2) - node T_221 = and(T_219, T_220) - node T_222 = not(cyc_B1_sqrt) - node T_223 = and(T_221, T_222) - node T_224 = not(cyc_C5) - node T_225 = and(T_223, T_224) - node T_226 = not(cyc_C4) - node T_227 = and(T_225, T_226) - io.inReady_div <= T_227 - node T_228 = not(cyc_B6_sqrt) - node T_229 = and(ready_PA, T_228) - node T_230 = not(cyc_B5_sqrt) - node T_231 = and(T_229, T_230) - node T_232 = not(cyc_B4_sqrt) - node T_233 = and(T_231, T_232) - node T_234 = not(cyc_B2_div) - node T_235 = and(T_233, T_234) - node T_236 = not(cyc_B1_sqrt) - node T_237 = and(T_235, T_236) - io.inReady_sqrt <= T_237 - node T_238 = and(io.inReady_div, io.inValid) - node T_239 = not(io.sqrtOp) - node cyc_S_div = and(T_238, T_239) - node T_241 = and(io.inReady_sqrt, io.inValid) - node cyc_S_sqrt = and(T_241, io.sqrtOp) - node cyc_S = or(cyc_S_div, cyc_S_sqrt) - node signA_S = bits(io.a, 64, 64) - node expA_S = bits(io.a, 63, 52) - node fractA_S = bits(io.a, 51, 0) - node specialCodeA_S = bits(expA_S, 11, 9) - node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) - node T_250 = bits(specialCodeA_S, 2, 1) - node isSpecialA_S = eq(T_250, UInt<2>("h03")) - node signB_S = bits(io.b, 64, 64) - node expB_S = bits(io.b, 63, 52) - node fractB_S = bits(io.b, 51, 0) - node specialCodeB_S = bits(expB_S, 11, 9) - node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) - node T_259 = bits(specialCodeB_S, 2, 1) - node isSpecialB_S = eq(T_259, UInt<2>("h03")) - node T_262 = xor(signA_S, signB_S) - node sign_S = mux(io.sqrtOp, signB_S, T_262) - node T_264 = not(isSpecialA_S) - node T_265 = not(isSpecialB_S) - node T_266 = and(T_264, T_265) - node T_267 = not(isZeroA_S) - node T_268 = and(T_266, T_267) - node T_269 = not(isZeroB_S) - node normalCase_S_div = and(T_268, T_269) - node T_271 = not(isSpecialB_S) - node T_272 = not(isZeroB_S) - node T_273 = and(T_271, T_272) - node T_274 = not(signB_S) - node normalCase_S_sqrt = and(T_273, T_274) - node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) - node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) - node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) - node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) - node T_280 = not(ready_PB) - node T_281 = or(valid_PA, T_280) - node T_282 = and(cyc_S, T_281) - node entering_PA = or(entering_PA_normalCase, T_282) - node T_284 = not(normalCase_S) - node T_285 = and(cyc_S, T_284) - node T_286 = not(valid_PA) - node T_287 = and(T_285, T_286) - node T_288 = not(valid_PB) - node T_289 = not(ready_PC) - node T_290 = and(T_288, T_289) - node T_291 = or(leaving_PB, T_290) - node entering_PB_S = and(T_287, T_291) - node T_293 = not(normalCase_S) - node T_294 = and(cyc_S, T_293) - node T_295 = not(valid_PA) - node T_296 = and(T_294, T_295) - node T_297 = not(valid_PB) - node T_298 = and(T_296, T_297) - node entering_PC_S = and(T_298, ready_PC) - node T_300 = or(entering_PA, leaving_PA) - when T_300 : - valid_PA <= entering_PA - skip - when entering_PA : - sqrtOp_PA <= io.sqrtOp - sign_PA <= sign_S - specialCodeB_PA <= specialCodeB_S - node T_301 = bits(fractB_S, 51, 51) - fractB_51_PA <= T_301 - roundingMode_PA <= io.roundingMode - skip - node T_302 = not(io.sqrtOp) - node T_303 = and(entering_PA, T_302) - when T_303 : - specialCodeA_PA <= specialCodeA_S - node T_304 = bits(fractA_S, 51, 51) - fractA_51_PA <= T_304 - skip - when entering_PA_normalCase : - node T_305 = bits(expB_S, 11, 11) - node T_307 = sub(UInt<3>("h00"), T_305) - node T_308 = tail(T_307, 1) - node T_309 = bits(expB_S, 10, 0) - node T_310 = not(T_309) - node T_311 = cat(T_308, T_310) - node T_312 = add(expA_S, T_311) - node T_313 = tail(T_312, 1) - node T_314 = mux(io.sqrtOp, expB_S, T_313) - exp_PA <= T_314 - node T_315 = bits(fractB_S, 50, 0) - fractB_other_PA <= T_315 - skip - when entering_PA_normalCase_div : - node T_316 = bits(fractA_S, 50, 0) - fractA_other_PA <= T_316 - skip - node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) - node T_319 = bits(specialCodeA_PA, 2, 1) - node isSpecialA_PA = eq(T_319, UInt<2>("h03")) - node T_323 = cat(fractA_51_PA, fractA_other_PA) - node sigA_PA = cat(UInt<1>("h01"), T_323) - node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) - node T_327 = bits(specialCodeB_PA, 2, 1) - node isSpecialB_PA = eq(T_327, UInt<2>("h03")) - node T_331 = cat(fractB_51_PA, fractB_other_PA) - node sigB_PA = cat(UInt<1>("h01"), T_331) - node T_333 = not(isSpecialB_PA) - node T_334 = not(isZeroB_PA) - node T_335 = and(T_333, T_334) - node T_336 = not(sign_PA) - node T_337 = and(T_335, T_336) - node T_338 = not(isSpecialA_PA) - node T_339 = not(isSpecialB_PA) - node T_340 = and(T_338, T_339) - node T_341 = not(isZeroA_PA) - node T_342 = and(T_340, T_341) - node T_343 = not(isZeroB_PA) - node T_344 = and(T_342, T_343) - node normalCase_PA = mux(sqrtOp_PA, T_337, T_344) - node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) - node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) - node T_348 = and(valid_PA, valid_leaving_PA) - leaving_PA <= T_348 - node T_349 = not(valid_PA) - node T_350 = or(T_349, valid_leaving_PA) - ready_PA <= T_350 - node T_351 = and(valid_PA, normalCase_PA) - node entering_PB_normalCase = and(T_351, valid_normalCase_leaving_PA) - node entering_PB = or(entering_PB_S, leaving_PA) - node T_354 = or(entering_PB, leaving_PB) - when T_354 : - valid_PB <= entering_PB - skip - when entering_PB : - node T_355 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) - sqrtOp_PB <= T_355 - node T_356 = mux(valid_PA, sign_PA, sign_S) - sign_PB <= T_356 - node T_357 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) - specialCodeA_PB <= T_357 - node T_358 = bits(fractA_S, 51, 51) - node T_359 = mux(valid_PA, fractA_51_PA, T_358) - fractA_51_PB <= T_359 - node T_360 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) - specialCodeB_PB <= T_360 - node T_361 = bits(fractB_S, 51, 51) - node T_362 = mux(valid_PA, fractB_51_PA, T_361) - fractB_51_PB <= T_362 - node T_363 = mux(valid_PA, roundingMode_PA, io.roundingMode) - roundingMode_PB <= T_363 - skip - when entering_PB_normalCase : - exp_PB <= exp_PA - node T_364 = bits(fractA_other_PA, 0, 0) - fractA_0_PB <= T_364 - fractB_other_PB <= fractB_other_PA - skip - node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) - node T_367 = bits(specialCodeA_PB, 2, 1) - node isSpecialA_PB = eq(T_367, UInt<2>("h03")) - node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) - node T_372 = bits(specialCodeB_PB, 2, 1) - node isSpecialB_PB = eq(T_372, UInt<2>("h03")) - node T_375 = not(isSpecialB_PB) - node T_376 = not(isZeroB_PB) - node T_377 = and(T_375, T_376) - node T_378 = not(sign_PB) - node T_379 = and(T_377, T_378) - node T_380 = not(isSpecialA_PB) - node T_381 = not(isSpecialB_PB) - node T_382 = and(T_380, T_381) - node T_383 = not(isZeroA_PB) - node T_384 = and(T_382, T_383) - node T_385 = not(isZeroB_PB) - node T_386 = and(T_384, T_385) - node normalCase_PB = mux(sqrtOp_PB, T_379, T_386) - node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) - node T_389 = and(valid_PB, valid_leaving_PB) - leaving_PB <= T_389 - node T_390 = not(valid_PB) - node T_391 = or(T_390, valid_leaving_PB) - ready_PB <= T_391 - node T_392 = and(valid_PB, normalCase_PB) - node entering_PC_normalCase = and(T_392, valid_normalCase_leaving_PB) - node entering_PC = or(entering_PC_S, leaving_PB) - node T_395 = or(entering_PC, leaving_PC) - when T_395 : - valid_PC <= entering_PC - skip - when entering_PC : - node T_396 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) - sqrtOp_PC <= T_396 - node T_397 = mux(valid_PB, sign_PB, sign_S) - sign_PC <= T_397 - node T_398 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) - specialCodeA_PC <= T_398 - node T_399 = bits(fractA_S, 51, 51) - node T_400 = mux(valid_PB, fractA_51_PB, T_399) - fractA_51_PC <= T_400 - node T_401 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) - specialCodeB_PC <= T_401 - node T_402 = bits(fractB_S, 51, 51) - node T_403 = mux(valid_PB, fractB_51_PB, T_402) - fractB_51_PC <= T_403 - node T_404 = mux(valid_PB, roundingMode_PB, io.roundingMode) - roundingMode_PC <= T_404 - skip - when entering_PC_normalCase : - exp_PC <= exp_PB - fractA_0_PC <= fractA_0_PB - fractB_other_PC <= fractB_other_PB - skip - node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) - node T_407 = bits(specialCodeA_PC, 2, 1) - node isSpecialA_PC = eq(T_407, UInt<2>("h03")) - node T_410 = bits(specialCodeA_PC, 0, 0) - node T_411 = not(T_410) - node isInfA_PC = and(isSpecialA_PC, T_411) - node T_413 = bits(specialCodeA_PC, 0, 0) - node isNaNA_PC = and(isSpecialA_PC, T_413) - node T_415 = not(fractA_51_PC) - node isSigNaNA_PC = and(isNaNA_PC, T_415) - node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) - node T_419 = bits(specialCodeB_PC, 2, 1) - node isSpecialB_PC = eq(T_419, UInt<2>("h03")) - node T_422 = bits(specialCodeB_PC, 0, 0) - node T_423 = not(T_422) - node isInfB_PC = and(isSpecialB_PC, T_423) - node T_425 = bits(specialCodeB_PC, 0, 0) - node isNaNB_PC = and(isSpecialB_PC, T_425) - node T_427 = not(fractB_51_PC) - node isSigNaNB_PC = and(isNaNB_PC, T_427) - node T_430 = cat(fractB_51_PC, fractB_other_PC) - node sigB_PC = cat(UInt<1>("h01"), T_430) - node T_432 = not(isSpecialB_PC) - node T_433 = not(isZeroB_PC) - node T_434 = and(T_432, T_433) - node T_435 = not(sign_PC) - node T_436 = and(T_434, T_435) - node T_437 = not(isSpecialA_PC) - node T_438 = not(isSpecialB_PC) - node T_439 = and(T_437, T_438) - node T_440 = not(isZeroA_PC) - node T_441 = and(T_439, T_440) - node T_442 = not(isZeroB_PC) - node T_443 = and(T_441, T_442) - node normalCase_PC = mux(sqrtOp_PC, T_436, T_443) - node T_446 = add(exp_PC, UInt<2>("h02")) - node expP2_PC = tail(T_446, 1) - node T_448 = bits(exp_PC, 0, 0) - node T_449 = bits(expP2_PC, 13, 1) - node T_451 = cat(T_449, UInt<1>("h00")) - node T_452 = bits(exp_PC, 13, 1) - node T_454 = cat(T_452, UInt<1>("h01")) - node expP1_PC = mux(T_448, T_451, T_454) - node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) - node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) - node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) - node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) - node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) - node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) - node T_462 = not(roundMagUp_PC) - node T_463 = not(roundingMode_near_even_PC) - node roundMagDown_PC = and(T_462, T_463) - node T_465 = not(normalCase_PC) - node valid_leaving_PC = or(T_465, cyc_E1) - node T_467 = and(valid_PC, valid_leaving_PC) - leaving_PC <= T_467 - node T_468 = not(valid_PC) - node T_469 = or(T_468, valid_leaving_PC) - ready_PC <= T_469 - node T_470 = not(sqrtOp_PC) - node T_471 = and(leaving_PC, T_470) - io.outValid_div <= T_471 - node T_472 = and(leaving_PC, sqrtOp_PC) - io.outValid_sqrt <= T_472 - node T_474 = neq(cycleNum_A, UInt<1>("h00")) - node T_475 = or(entering_PA_normalCase, T_474) - when T_475 : - node T_478 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) - node T_481 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) - node T_482 = or(T_478, T_481) - node T_483 = not(entering_PA_normalCase) - node T_485 = sub(cycleNum_A, UInt<1>("h01")) - node T_486 = tail(T_485, 1) - node T_488 = mux(T_483, T_486, UInt<1>("h00")) - node T_489 = or(T_482, T_488) - cycleNum_A <= T_489 - skip - node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) - node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) - node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) - node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) - node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) - node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) - node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) - node T_503 = not(sqrtOp_PA) - node cyc_A3_div = and(cyc_A3, T_503) - node T_505 = not(sqrtOp_PA) - node cyc_A2_div = and(cyc_A2, T_505) - node T_507 = not(sqrtOp_PA) - node cyc_A1_div = and(cyc_A1, T_507) - node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) - node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) - node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) - node T_513 = neq(cycleNum_B, UInt<1>("h00")) - node T_514 = or(cyc_A1, T_513) - when T_514 : - node T_517 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) - node T_519 = sub(cycleNum_B, UInt<1>("h01")) - node T_520 = tail(T_519, 1) - node T_521 = mux(cyc_A1, T_517, T_520) - cycleNum_B <= T_521 - skip - node T_523 = eq(cycleNum_B, UInt<4>("h0a")) - cyc_B10_sqrt <= T_523 - node T_525 = eq(cycleNum_B, UInt<4>("h09")) - cyc_B9_sqrt <= T_525 - node T_527 = eq(cycleNum_B, UInt<4>("h08")) - cyc_B8_sqrt <= T_527 - node T_529 = eq(cycleNum_B, UInt<3>("h07")) - cyc_B7_sqrt <= T_529 - node T_531 = eq(cycleNum_B, UInt<3>("h06")) - cyc_B6 <= T_531 - node T_533 = eq(cycleNum_B, UInt<3>("h05")) - cyc_B5 <= T_533 - node T_535 = eq(cycleNum_B, UInt<3>("h04")) - cyc_B4 <= T_535 - node T_537 = eq(cycleNum_B, UInt<2>("h03")) - cyc_B3 <= T_537 - node T_539 = eq(cycleNum_B, UInt<2>("h02")) - cyc_B2 <= T_539 - node T_541 = eq(cycleNum_B, UInt<1>("h01")) - cyc_B1 <= T_541 - node T_542 = and(cyc_B6, valid_PA) - node T_543 = not(sqrtOp_PA) - node T_544 = and(T_542, T_543) - cyc_B6_div <= T_544 - node T_545 = and(cyc_B5, valid_PA) - node T_546 = not(sqrtOp_PA) - node T_547 = and(T_545, T_546) - cyc_B5_div <= T_547 - node T_548 = and(cyc_B4, valid_PA) - node T_549 = not(sqrtOp_PA) - node T_550 = and(T_548, T_549) - cyc_B4_div <= T_550 - node T_551 = not(sqrtOp_PB) - node T_552 = and(cyc_B3, T_551) - cyc_B3_div <= T_552 - node T_553 = not(sqrtOp_PB) - node T_554 = and(cyc_B2, T_553) - cyc_B2_div <= T_554 - node T_555 = not(sqrtOp_PB) - node T_556 = and(cyc_B1, T_555) - cyc_B1_div <= T_556 - node T_557 = and(cyc_B6, valid_PB) - node T_558 = and(T_557, sqrtOp_PB) - cyc_B6_sqrt <= T_558 - node T_559 = and(cyc_B5, valid_PB) - node T_560 = and(T_559, sqrtOp_PB) - cyc_B5_sqrt <= T_560 - node T_561 = and(cyc_B4, valid_PB) - node T_562 = and(T_561, sqrtOp_PB) - cyc_B4_sqrt <= T_562 - node T_563 = and(cyc_B3, sqrtOp_PB) - cyc_B3_sqrt <= T_563 - node T_564 = and(cyc_B2, sqrtOp_PB) - cyc_B2_sqrt <= T_564 - node T_565 = and(cyc_B1, sqrtOp_PB) - cyc_B1_sqrt <= T_565 - node T_567 = neq(cycleNum_C, UInt<1>("h00")) - node T_568 = or(cyc_B1, T_567) - when T_568 : - node T_571 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) - node T_573 = sub(cycleNum_C, UInt<1>("h01")) - node T_574 = tail(T_573, 1) - node T_575 = mux(cyc_B1, T_571, T_574) - cycleNum_C <= T_575 - skip - node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) - node T_579 = eq(cycleNum_C, UInt<3>("h05")) - cyc_C5 <= T_579 - node T_581 = eq(cycleNum_C, UInt<3>("h04")) - cyc_C4 <= T_581 - node T_583 = eq(cycleNum_C, UInt<2>("h03")) - valid_normalCase_leaving_PB <= T_583 - node T_585 = eq(cycleNum_C, UInt<2>("h02")) - cyc_C2 <= T_585 - node T_587 = eq(cycleNum_C, UInt<1>("h01")) - cyc_C1 <= T_587 - node T_588 = not(sqrtOp_PB) - node cyc_C5_div = and(cyc_C5, T_588) - node T_590 = not(sqrtOp_PB) - node cyc_C4_div = and(cyc_C4, T_590) - node T_592 = not(sqrtOp_PB) - node cyc_C3_div = and(valid_normalCase_leaving_PB, T_592) - node T_594 = not(sqrtOp_PC) - node cyc_C2_div = and(cyc_C2, T_594) - node T_596 = not(sqrtOp_PC) - node cyc_C1_div = and(cyc_C1, T_596) - node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) - node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) - node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) - node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) - node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) - node T_604 = neq(cycleNum_E, UInt<1>("h00")) - node T_605 = or(cyc_C1, T_604) - when T_605 : - node T_608 = sub(cycleNum_E, UInt<1>("h01")) - node T_609 = tail(T_608, 1) - node T_610 = mux(cyc_C1, UInt<3>("h04"), T_609) - cycleNum_E <= T_610 - skip - node T_612 = eq(cycleNum_E, UInt<3>("h04")) - cyc_E4 <= T_612 - node T_614 = eq(cycleNum_E, UInt<2>("h03")) - cyc_E3 <= T_614 - node T_616 = eq(cycleNum_E, UInt<2>("h02")) - cyc_E2 <= T_616 - node T_618 = eq(cycleNum_E, UInt<1>("h01")) - cyc_E1 <= T_618 - node T_619 = not(sqrtOp_PC) - node cyc_E4_div = and(cyc_E4, T_619) - node T_621 = not(sqrtOp_PC) - node cyc_E3_div = and(cyc_E3, T_621) - node T_623 = not(sqrtOp_PC) - node cyc_E2_div = and(cyc_E2, T_623) - node T_625 = not(sqrtOp_PC) - node cyc_E1_div = and(cyc_E1, T_625) - node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) - node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) - node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) - node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) - node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) - node T_633 = bits(fractB_S, 51, 49) - node T_635 = eq(T_633, UInt<1>("h00")) - node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_635) - node T_637 = bits(fractB_S, 51, 49) - node T_639 = eq(T_637, UInt<1>("h01")) - node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_639) - node T_641 = bits(fractB_S, 51, 49) - node T_643 = eq(T_641, UInt<2>("h02")) - node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_643) - node T_645 = bits(fractB_S, 51, 49) - node T_647 = eq(T_645, UInt<2>("h03")) - node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_647) - node T_649 = bits(fractB_S, 51, 49) - node T_651 = eq(T_649, UInt<3>("h04")) - node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_651) - node T_653 = bits(fractB_S, 51, 49) - node T_655 = eq(T_653, UInt<3>("h05")) - node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_655) - node T_657 = bits(fractB_S, 51, 49) - node T_659 = eq(T_657, UInt<3>("h06")) - node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_659) - node T_661 = bits(fractB_S, 51, 49) - node T_663 = eq(T_661, UInt<3>("h07")) - node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_663) - node T_667 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) - node T_670 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) - node T_671 = or(T_667, T_670) - node T_674 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) - node T_675 = or(T_671, T_674) - node T_678 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) - node T_679 = or(T_675, T_678) - node T_682 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) - node T_683 = or(T_679, T_682) - node T_686 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) - node T_687 = or(T_683, T_686) - node T_690 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) - node T_691 = or(T_687, T_690) - node T_694 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) - node zK1_A4_div = or(T_691, T_694) - node T_697 = not(UInt<12>("h0fe3")) - node T_699 = mux(zLinPiece_0_A4_div, T_697, UInt<1>("h00")) - node T_701 = not(UInt<12>("h0c5d")) - node T_703 = mux(zLinPiece_1_A4_div, T_701, UInt<1>("h00")) - node T_704 = or(T_699, T_703) - node T_706 = not(UInt<12>("h098a")) - node T_708 = mux(zLinPiece_2_A4_div, T_706, UInt<1>("h00")) - node T_709 = or(T_704, T_708) - node T_711 = not(UInt<12>("h0739")) - node T_713 = mux(zLinPiece_3_A4_div, T_711, UInt<1>("h00")) - node T_714 = or(T_709, T_713) - node T_716 = not(UInt<12>("h054b")) - node T_718 = mux(zLinPiece_4_A4_div, T_716, UInt<1>("h00")) - node T_719 = or(T_714, T_718) - node T_721 = not(UInt<12>("h03a9")) - node T_723 = mux(zLinPiece_5_A4_div, T_721, UInt<1>("h00")) - node T_724 = or(T_719, T_723) - node T_726 = not(UInt<12>("h0242")) - node T_728 = mux(zLinPiece_6_A4_div, T_726, UInt<1>("h00")) - node T_729 = or(T_724, T_728) - node T_731 = not(UInt<12>("h010b")) - node T_733 = mux(zLinPiece_7_A4_div, T_731, UInt<1>("h00")) - node zComplFractK0_A4_div = or(T_729, T_733) - node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) - node T_737 = bits(expB_S, 0, 0) - node T_738 = not(T_737) - node T_739 = and(entering_PA_normalCase_sqrt, T_738) - node T_740 = bits(fractB_S, 51, 51) - node T_741 = not(T_740) - node zQuadPiece_0_A7_sqrt = and(T_739, T_741) - node T_743 = bits(expB_S, 0, 0) - node T_744 = not(T_743) - node T_745 = and(entering_PA_normalCase_sqrt, T_744) - node T_746 = bits(fractB_S, 51, 51) - node zQuadPiece_1_A7_sqrt = and(T_745, T_746) - node T_748 = bits(expB_S, 0, 0) - node T_749 = and(entering_PA_normalCase_sqrt, T_748) - node T_750 = bits(fractB_S, 51, 51) - node T_751 = not(T_750) - node zQuadPiece_2_A7_sqrt = and(T_749, T_751) - node T_753 = bits(expB_S, 0, 0) - node T_754 = and(entering_PA_normalCase_sqrt, T_753) - node T_755 = bits(fractB_S, 51, 51) - node zQuadPiece_3_A7_sqrt = and(T_754, T_755) - node T_759 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) - node T_762 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) - node T_763 = or(T_759, T_762) - node T_766 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) - node T_767 = or(T_763, T_766) - node T_770 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) - node zK2_A7_sqrt = or(T_767, T_770) - node T_773 = not(UInt<10>("h03d0")) - node T_775 = mux(zQuadPiece_0_A7_sqrt, T_773, UInt<1>("h00")) - node T_777 = not(UInt<10>("h0220")) - node T_779 = mux(zQuadPiece_1_A7_sqrt, T_777, UInt<1>("h00")) - node T_780 = or(T_775, T_779) - node T_782 = not(UInt<10>("h02b2")) - node T_784 = mux(zQuadPiece_2_A7_sqrt, T_782, UInt<1>("h00")) - node T_785 = or(T_780, T_784) - node T_787 = not(UInt<10>("h0181")) - node T_789 = mux(zQuadPiece_3_A7_sqrt, T_787, UInt<1>("h00")) - node zComplK1_A7_sqrt = or(T_785, T_789) - node T_791 = bits(exp_PA, 0, 0) - node T_792 = not(T_791) - node T_793 = and(cyc_A6_sqrt, T_792) - node T_794 = bits(sigB_PA, 51, 51) - node T_795 = not(T_794) - node zQuadPiece_0_A6_sqrt = and(T_793, T_795) - node T_797 = bits(exp_PA, 0, 0) - node T_798 = not(T_797) - node T_799 = and(cyc_A6_sqrt, T_798) - node T_800 = bits(sigB_PA, 51, 51) - node zQuadPiece_1_A6_sqrt = and(T_799, T_800) - node T_802 = bits(exp_PA, 0, 0) - node T_803 = and(cyc_A6_sqrt, T_802) - node T_804 = bits(sigB_PA, 51, 51) - node T_805 = not(T_804) - node zQuadPiece_2_A6_sqrt = and(T_803, T_805) - node T_807 = bits(exp_PA, 0, 0) - node T_808 = and(cyc_A6_sqrt, T_807) - node T_809 = bits(sigB_PA, 51, 51) - node zQuadPiece_3_A6_sqrt = and(T_808, T_809) - node T_812 = not(UInt<13>("h01fe5")) - node T_814 = mux(zQuadPiece_0_A6_sqrt, T_812, UInt<1>("h00")) - node T_816 = not(UInt<13>("h01435")) - node T_818 = mux(zQuadPiece_1_A6_sqrt, T_816, UInt<1>("h00")) - node T_819 = or(T_814, T_818) - node T_821 = not(UInt<13>("h0d2c")) - node T_823 = mux(zQuadPiece_2_A6_sqrt, T_821, UInt<1>("h00")) - node T_824 = or(T_819, T_823) - node T_826 = not(UInt<13>("h04e8")) - node T_828 = mux(zQuadPiece_3_A6_sqrt, T_826, UInt<1>("h00")) - node zComplFractK0_A6_sqrt = or(T_824, T_828) - node T_830 = bits(zFractB_A4_div, 48, 40) - node T_831 = or(T_830, zK2_A7_sqrt) - node T_832 = not(cyc_S) - node T_834 = mux(T_832, nextMulAdd9A_A, UInt<1>("h00")) - node mulAdd9A_A = or(T_831, T_834) - node T_836 = bits(zFractB_A7_sqrt, 50, 42) - node T_837 = or(zK1_A4_div, T_836) - node T_838 = not(cyc_S) - node T_840 = mux(T_838, nextMulAdd9B_A, UInt<1>("h00")) - node mulAdd9B_A = or(T_837, T_840) - node T_842 = shl(zComplK1_A7_sqrt, 10) - node T_844 = sub(UInt<6>("h00"), cyc_A6_sqrt) - node T_845 = tail(T_844, 1) - node T_846 = cat(zComplFractK0_A6_sqrt, T_845) - node T_847 = cat(cyc_A6_sqrt, T_846) - node T_848 = or(T_842, T_847) - node T_850 = sub(UInt<8>("h00"), entering_PA_normalCase_div) - node T_851 = tail(T_850, 1) - node T_852 = cat(zComplFractK0_A4_div, T_851) - node T_853 = cat(entering_PA_normalCase_div, T_852) - node T_854 = or(T_848, T_853) - node T_856 = shl(fractR0_A, 10) - node T_857 = add(UInt<20>("h040000"), T_856) - node T_858 = tail(T_857, 1) - node T_860 = mux(cyc_A5_sqrt, T_858, UInt<1>("h00")) - node T_861 = or(T_854, T_860) - node T_862 = bits(hiSqrR0_A_sqrt, 9, 9) - node T_863 = not(T_862) - node T_864 = and(cyc_A4_sqrt, T_863) - node T_867 = mux(T_864, UInt<11>("h0400"), UInt<1>("h00")) - node T_868 = or(T_861, T_867) - node T_869 = bits(hiSqrR0_A_sqrt, 9, 9) - node T_870 = and(cyc_A4_sqrt, T_869) - node T_871 = or(T_870, cyc_A3_div) - node T_872 = bits(sigB_PA, 46, 26) - node T_874 = add(T_872, UInt<11>("h0400")) - node T_875 = tail(T_874, 1) - node T_877 = mux(T_871, T_875, UInt<1>("h00")) - node T_878 = or(T_868, T_877) - node T_879 = or(cyc_A3_sqrt, cyc_A2) - node T_881 = mux(T_879, partNegSigma0_A, UInt<1>("h00")) - node T_882 = or(T_878, T_881) - node T_883 = shl(fractR0_A, 16) - node T_885 = mux(cyc_A1_sqrt, T_883, UInt<1>("h00")) - node T_886 = or(T_882, T_885) - node T_887 = shl(fractR0_A, 15) - node T_889 = mux(cyc_A1_div, T_887, UInt<1>("h00")) - node mulAdd9C_A = or(T_886, T_889) - node T_891 = mul(mulAdd9A_A, mulAdd9B_A) - node T_893 = bits(mulAdd9C_A, 17, 0) - node T_894 = cat(UInt<1>("h00"), T_893) - node T_895 = add(T_891, T_894) - node loMulAdd9Out_A = tail(T_895, 1) - node T_897 = bits(loMulAdd9Out_A, 18, 18) - node T_898 = bits(mulAdd9C_A, 24, 18) - node T_900 = add(T_898, UInt<1>("h01")) - node T_901 = tail(T_900, 1) - node T_902 = bits(mulAdd9C_A, 24, 18) - node T_903 = mux(T_897, T_901, T_902) - node T_904 = bits(loMulAdd9Out_A, 17, 0) - node mulAdd9Out_A = cat(T_903, T_904) - node T_906 = bits(mulAdd9Out_A, 19, 19) - node T_907 = and(cyc_A6_sqrt, T_906) - node T_908 = not(mulAdd9Out_A) - node T_909 = shr(T_908, 10) - node T_911 = mux(T_907, T_909, UInt<1>("h00")) - node zFractR0_A6_sqrt = bits(T_911, 8, 0) - node T_913 = bits(exp_PA, 0, 0) - node T_914 = shl(mulAdd9Out_A, 1) - node sqrR0_A5_sqrt = mux(T_913, T_914, mulAdd9Out_A) - node T_916 = bits(mulAdd9Out_A, 20, 20) - node T_917 = and(entering_PA_normalCase_div, T_916) - node T_918 = not(mulAdd9Out_A) - node T_919 = shr(T_918, 11) - node T_921 = mux(T_917, T_919, UInt<1>("h00")) - node zFractR0_A4_div = bits(T_921, 8, 0) - node T_923 = bits(mulAdd9Out_A, 11, 11) - node T_924 = and(cyc_A2, T_923) - node T_925 = not(mulAdd9Out_A) - node T_926 = shr(T_925, 2) - node T_928 = mux(T_924, T_926, UInt<1>("h00")) - node zSigma0_A2 = bits(T_928, 8, 0) - node T_930 = shr(mulAdd9Out_A, 10) - node T_931 = shr(mulAdd9Out_A, 9) - node T_932 = mux(sqrtOp_PA, T_930, T_931) - node fractR1_A1 = bits(T_932, 14, 0) - node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) - node T_936 = bits(exp_PA, 0, 0) - node T_937 = shl(r1_A1, 1) - node ER1_A1_sqrt = mux(T_936, T_937, r1_A1) - node T_939 = or(cyc_A6_sqrt, entering_PA_normalCase_div) - when T_939 : - node T_940 = or(zFractR0_A6_sqrt, zFractR0_A4_div) - fractR0_A <= T_940 - skip - when cyc_A5_sqrt : - node T_941 = shr(sqrR0_A5_sqrt, 10) - hiSqrR0_A_sqrt <= T_941 - skip - node T_942 = or(cyc_A4_sqrt, cyc_A3) - when T_942 : - node T_943 = shr(mulAdd9Out_A, 9) - node T_944 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_943) - node T_945 = bits(T_944, 20, 0) - partNegSigma0_A <= T_945 - skip - node T_946 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_947 = or(T_946, cyc_A5_sqrt) - node T_948 = or(T_947, cyc_A4) - node T_949 = or(T_948, cyc_A3) - node T_950 = or(T_949, cyc_A2) - when T_950 : - node T_951 = not(mulAdd9Out_A) - node T_952 = shr(T_951, 11) - node T_954 = mux(entering_PA_normalCase_sqrt, T_952, UInt<1>("h00")) - node T_955 = or(T_954, zFractR0_A6_sqrt) - node T_956 = bits(sigB_PA, 43, 35) - node T_958 = mux(cyc_A4_sqrt, T_956, UInt<1>("h00")) - node T_959 = or(T_955, T_958) - node T_960 = bits(zFractB_A4_div, 43, 35) - node T_961 = or(T_959, T_960) - node T_962 = or(cyc_A5_sqrt, cyc_A3) - node T_963 = bits(sigB_PA, 52, 44) - node T_965 = mux(T_962, T_963, UInt<1>("h00")) - node T_966 = or(T_961, T_965) - node T_967 = or(T_966, zSigma0_A2) - nextMulAdd9A_A <= T_967 - skip - node T_968 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_969 = or(T_968, cyc_A5_sqrt) - node T_970 = or(T_969, cyc_A4) - node T_971 = or(T_970, cyc_A2) - when T_971 : - node T_972 = bits(zFractB_A7_sqrt, 50, 42) - node T_973 = or(T_972, zFractR0_A6_sqrt) - node T_974 = bits(sqrR0_A5_sqrt, 9, 1) - node T_976 = mux(cyc_A5_sqrt, T_974, UInt<1>("h00")) - node T_977 = or(T_973, T_976) - node T_978 = or(T_977, zFractR0_A4_div) - node T_979 = bits(hiSqrR0_A_sqrt, 8, 0) - node T_981 = mux(cyc_A4_sqrt, T_979, UInt<1>("h00")) - node T_982 = or(T_978, T_981) - node T_984 = bits(fractR0_A, 8, 1) - node T_985 = cat(UInt<1>("h01"), T_984) - node T_987 = mux(cyc_A2, T_985, UInt<1>("h00")) - node T_988 = or(T_982, T_987) - nextMulAdd9B_A <= T_988 - skip - when cyc_A1_sqrt : - ER1_B_sqrt <= ER1_A1_sqrt - skip - node T_989 = or(cyc_A1, cyc_B7_sqrt) - node T_990 = or(T_989, cyc_B6_div) - node T_991 = or(T_990, cyc_B4) - node T_992 = or(T_991, cyc_B3) - node T_993 = or(T_992, cyc_C6_sqrt) - node T_994 = or(T_993, cyc_C4) - node T_995 = or(T_994, cyc_C1) - io.latchMulAddA_0 <= T_995 - node T_996 = shl(ER1_A1_sqrt, 36) - node T_998 = mux(cyc_A1_sqrt, T_996, UInt<1>("h00")) - node T_999 = or(cyc_B7_sqrt, cyc_A1_div) - node T_1001 = mux(T_999, sigB_PA, UInt<1>("h00")) - node T_1002 = or(T_998, T_1001) - node T_1004 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) - node T_1005 = or(T_1002, T_1004) - node T_1006 = bits(zSigma1_B4, 45, 12) - node T_1007 = or(T_1005, T_1006) - node T_1008 = or(cyc_B3, cyc_C6_sqrt) - node T_1009 = bits(sigXNU_B3_CX, 57, 12) - node T_1011 = mux(T_1008, T_1009, UInt<1>("h00")) - node T_1012 = or(T_1007, T_1011) - node T_1013 = bits(sigXN_C, 57, 25) - node T_1014 = shl(T_1013, 13) - node T_1016 = mux(cyc_C4_div, T_1014, UInt<1>("h00")) - node T_1017 = or(T_1012, T_1016) - node T_1018 = shl(u_C_sqrt, 15) - node T_1020 = mux(cyc_C4_sqrt, T_1018, UInt<1>("h00")) - node T_1021 = or(T_1017, T_1020) - node T_1023 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) - node T_1024 = or(T_1021, T_1023) - node T_1025 = or(T_1024, zComplSigT_C1_sqrt) - io.mulAddA_0 <= T_1025 - node T_1026 = or(cyc_A1, cyc_B7_sqrt) - node T_1027 = or(T_1026, cyc_B6_sqrt) - node T_1028 = or(T_1027, cyc_B4) - node T_1029 = or(T_1028, cyc_C6_sqrt) - node T_1030 = or(T_1029, cyc_C4) - node T_1031 = or(T_1030, cyc_C1) - io.latchMulAddB_0 <= T_1031 - node T_1032 = shl(r1_A1, 36) - node T_1034 = mux(cyc_A1, T_1032, UInt<1>("h00")) - node T_1035 = shl(ESqrR1_B_sqrt, 19) - node T_1037 = mux(cyc_B7_sqrt, T_1035, UInt<1>("h00")) - node T_1038 = or(T_1034, T_1037) - node T_1039 = shl(ER1_B_sqrt, 36) - node T_1041 = mux(cyc_B6_sqrt, T_1039, UInt<1>("h00")) - node T_1042 = or(T_1038, T_1041) - node T_1043 = or(T_1042, zSigma1_B4) - node T_1044 = bits(sqrSigma1_C, 30, 1) - node T_1046 = mux(cyc_C6_sqrt, T_1044, UInt<1>("h00")) - node T_1047 = or(T_1043, T_1046) - node T_1049 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) - node T_1050 = or(T_1047, T_1049) - node T_1051 = or(T_1050, zComplSigT_C1) - io.mulAddB_0 <= T_1051 - node T_1052 = or(cyc_A4, cyc_A3_div) - node T_1053 = or(T_1052, cyc_A1_div) - node T_1054 = or(T_1053, cyc_B10_sqrt) - node T_1055 = or(T_1054, cyc_B9_sqrt) - node T_1056 = or(T_1055, cyc_B7_sqrt) - node T_1057 = or(T_1056, cyc_B6) - node T_1058 = or(T_1057, cyc_B5_sqrt) - node T_1059 = or(T_1058, cyc_B3_sqrt) - node T_1060 = or(T_1059, cyc_B2_div) - node T_1061 = or(T_1060, cyc_B1_sqrt) - node T_1062 = or(T_1061, cyc_C4) - node T_1063 = or(cyc_A3, cyc_A2_div) - node T_1064 = or(T_1063, cyc_B9_sqrt) - node T_1065 = or(T_1064, cyc_B8_sqrt) - node T_1066 = or(T_1065, cyc_B6) - node T_1067 = or(T_1066, cyc_B5) - node T_1068 = or(T_1067, cyc_B4_sqrt) - node T_1069 = or(T_1068, cyc_B2_sqrt) - node T_1070 = or(T_1069, cyc_B1_div) - node T_1071 = or(T_1070, cyc_C6_sqrt) - node T_1072 = or(T_1071, valid_normalCase_leaving_PB) - node T_1073 = or(cyc_A2, cyc_A1_div) - node T_1074 = or(T_1073, cyc_B8_sqrt) - node T_1075 = or(T_1074, cyc_B7_sqrt) - node T_1076 = or(T_1075, cyc_B5) - node T_1077 = or(T_1076, cyc_B4) - node T_1078 = or(T_1077, cyc_B3_sqrt) - node T_1079 = or(T_1078, cyc_B1_sqrt) - node T_1080 = or(T_1079, cyc_C5) - node T_1081 = or(T_1080, cyc_C2) - node T_1082 = or(io.latchMulAddA_0, cyc_B6) - node T_1083 = or(T_1082, cyc_B2_sqrt) - node T_1084 = cat(T_1062, T_1072) - node T_1085 = cat(T_1081, T_1083) - node T_1086 = cat(T_1084, T_1085) - io.usingMulAdd <= T_1086 - node T_1087 = shl(sigX1_B, 47) - node T_1089 = mux(cyc_B1, T_1087, UInt<1>("h00")) - node T_1090 = shl(sigX1_B, 46) - node T_1092 = mux(cyc_C6_sqrt, T_1090, UInt<1>("h00")) - node T_1093 = or(T_1089, T_1092) - node T_1094 = or(cyc_C4_sqrt, cyc_C2) - node T_1095 = shl(sigXN_C, 47) - node T_1097 = mux(T_1094, T_1095, UInt<1>("h00")) - node T_1098 = or(T_1093, T_1097) - node T_1099 = not(E_E_div) - node T_1100 = and(cyc_E3_div, T_1099) - node T_1101 = shl(fractA_0_PC, 53) - node T_1103 = mux(T_1100, T_1101, UInt<1>("h00")) - node T_1104 = or(T_1098, T_1103) - node T_1105 = bits(exp_PC, 0, 0) - node T_1106 = bits(sigB_PC, 0, 0) - node T_1108 = cat(T_1106, UInt<1>("h00")) - node T_1109 = bits(sigB_PC, 1, 1) - node T_1110 = bits(sigB_PC, 0, 0) - node T_1111 = xor(T_1109, T_1110) - node T_1112 = bits(sigB_PC, 0, 0) - node T_1113 = cat(T_1111, T_1112) - node T_1114 = mux(T_1105, T_1108, T_1113) - node T_1115 = not(extraT_E) - node T_1117 = cat(T_1115, UInt<1>("h00")) - node T_1118 = xor(T_1114, T_1117) - node T_1119 = shl(T_1118, 54) - node T_1121 = mux(cyc_E3_sqrt, T_1119, UInt<1>("h00")) - node T_1122 = or(T_1104, T_1121) - io.mulAddC_2 <= T_1122 - node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) - node T_1124 = bits(io.mulAddResult_3, 90, 45) - node T_1125 = not(T_1124) - node T_1127 = mux(cyc_B4, T_1125, UInt<1>("h00")) - zSigma1_B4 <= T_1127 - node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) - node T_1129 = bits(io.mulAddResult_3, 104, 47) - sigXNU_B3_CX <= T_1129 - node T_1130 = bits(io.mulAddResult_3, 104, 104) - node E_C1_div = not(T_1130) - node T_1132 = not(E_C1_div) - node T_1133 = and(cyc_C1_div, T_1132) - node T_1134 = or(T_1133, cyc_C1_sqrt) - node T_1135 = bits(io.mulAddResult_3, 104, 51) - node T_1136 = not(T_1135) - node T_1138 = mux(T_1134, T_1136, UInt<1>("h00")) - node T_1139 = and(cyc_C1_div, E_C1_div) - node T_1141 = bits(io.mulAddResult_3, 102, 50) - node T_1142 = not(T_1141) - node T_1143 = cat(UInt<1>("h00"), T_1142) - node T_1145 = mux(T_1139, T_1143, UInt<1>("h00")) - node T_1146 = or(T_1138, T_1145) - zComplSigT_C1 <= T_1146 - node T_1147 = bits(io.mulAddResult_3, 104, 51) - node T_1148 = not(T_1147) - node T_1150 = mux(cyc_C1_sqrt, T_1148, UInt<1>("h00")) - zComplSigT_C1_sqrt <= T_1150 - node sigT_C1 = not(zComplSigT_C1) - node remT_E2 = bits(io.mulAddResult_3, 55, 0) - when cyc_B8_sqrt : - ESqrR1_B_sqrt <= ESqrR1_B8_sqrt - skip - when cyc_B3 : - sigX1_B <= sigXNU_B3_CX - skip - when cyc_B1 : - sqrSigma1_C <= sqrSigma1_B1 - skip - node T_1153 = or(cyc_C6_sqrt, cyc_C5_div) - node T_1154 = or(T_1153, cyc_C3_sqrt) - when T_1154 : - sigXN_C <= sigXNU_B3_CX - skip - when cyc_C5_sqrt : - node T_1155 = bits(sigXNU_B3_CX, 56, 26) - u_C_sqrt <= T_1155 - skip - when cyc_C1 : - E_E_div <= E_C1_div - node T_1156 = bits(sigT_C1, 53, 1) - sigT_E <= T_1156 - node T_1157 = bits(sigT_C1, 0, 0) - extraT_E <= T_1157 - skip - when cyc_E2 : - node T_1158 = bits(remT_E2, 55, 55) - node T_1159 = bits(remT_E2, 53, 53) - node T_1160 = mux(sqrtOp_PC, T_1158, T_1159) - isNegRemT_E <= T_1160 - node T_1161 = bits(remT_E2, 53, 0) - node T_1163 = eq(T_1161, UInt<1>("h00")) - node T_1164 = not(sqrtOp_PC) - node T_1165 = bits(remT_E2, 55, 54) - node T_1167 = eq(T_1165, UInt<1>("h00")) - node T_1168 = or(T_1164, T_1167) - node T_1169 = and(T_1163, T_1168) - trueEqX_E1 <= T_1169 - skip - node T_1170 = not(sqrtOp_PC) - node T_1171 = and(T_1170, E_E_div) - node T_1173 = mux(T_1171, exp_PC, UInt<1>("h00")) - node T_1174 = not(sqrtOp_PC) - node T_1175 = not(E_E_div) - node T_1176 = and(T_1174, T_1175) - node T_1178 = mux(T_1176, expP1_PC, UInt<1>("h00")) - node T_1179 = or(T_1173, T_1178) - node T_1180 = shr(exp_PC, 1) - node T_1182 = add(T_1180, UInt<12>("h0400")) - node T_1183 = tail(T_1182, 1) - node T_1185 = mux(sqrtOp_PC, T_1183, UInt<1>("h00")) - node sExpX_E = or(T_1179, T_1185) - node posExpX_E = bits(sExpX_E, 12, 0) - node T_1188 = not(posExpX_E) - node T_1190 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1188) - node T_1191 = bits(T_1190, 1026, 974) - node T_1192 = bits(T_1191, 31, 0) - node T_1195 = shl(UInt<16>("h0ffff"), 16) - node T_1196 = xor(UInt<32>("h0ffffffff"), T_1195) - node T_1197 = shr(T_1192, 16) - node T_1198 = and(T_1197, T_1196) - node T_1199 = bits(T_1192, 15, 0) - node T_1200 = shl(T_1199, 16) - node T_1201 = not(T_1196) - node T_1202 = and(T_1200, T_1201) - node T_1203 = or(T_1198, T_1202) - node T_1204 = bits(T_1196, 23, 0) - node T_1205 = shl(T_1204, 8) - node T_1206 = xor(T_1196, T_1205) - node T_1207 = shr(T_1203, 8) - node T_1208 = and(T_1207, T_1206) - node T_1209 = bits(T_1203, 23, 0) - node T_1210 = shl(T_1209, 8) - node T_1211 = not(T_1206) - node T_1212 = and(T_1210, T_1211) - node T_1213 = or(T_1208, T_1212) - node T_1214 = bits(T_1206, 27, 0) - node T_1215 = shl(T_1214, 4) - node T_1216 = xor(T_1206, T_1215) - node T_1217 = shr(T_1213, 4) - node T_1218 = and(T_1217, T_1216) - node T_1219 = bits(T_1213, 27, 0) - node T_1220 = shl(T_1219, 4) - node T_1221 = not(T_1216) - node T_1222 = and(T_1220, T_1221) - node T_1223 = or(T_1218, T_1222) - node T_1224 = bits(T_1216, 29, 0) - node T_1225 = shl(T_1224, 2) - node T_1226 = xor(T_1216, T_1225) - node T_1227 = shr(T_1223, 2) - node T_1228 = and(T_1227, T_1226) - node T_1229 = bits(T_1223, 29, 0) - node T_1230 = shl(T_1229, 2) - node T_1231 = not(T_1226) - node T_1232 = and(T_1230, T_1231) - node T_1233 = or(T_1228, T_1232) - node T_1234 = bits(T_1226, 30, 0) - node T_1235 = shl(T_1234, 1) - node T_1236 = xor(T_1226, T_1235) - node T_1237 = shr(T_1233, 1) - node T_1238 = and(T_1237, T_1236) - node T_1239 = bits(T_1233, 30, 0) - node T_1240 = shl(T_1239, 1) - node T_1241 = not(T_1236) - node T_1242 = and(T_1240, T_1241) - node T_1243 = or(T_1238, T_1242) - node T_1244 = bits(T_1191, 52, 32) - node T_1245 = bits(T_1244, 15, 0) - node T_1248 = shl(UInt<8>("h0ff"), 8) - node T_1249 = xor(UInt<16>("h0ffff"), T_1248) - node T_1250 = shr(T_1245, 8) - node T_1251 = and(T_1250, T_1249) - node T_1252 = bits(T_1245, 7, 0) - node T_1253 = shl(T_1252, 8) - node T_1254 = not(T_1249) - node T_1255 = and(T_1253, T_1254) - node T_1256 = or(T_1251, T_1255) - node T_1257 = bits(T_1249, 11, 0) - node T_1258 = shl(T_1257, 4) - node T_1259 = xor(T_1249, T_1258) - node T_1260 = shr(T_1256, 4) - node T_1261 = and(T_1260, T_1259) - node T_1262 = bits(T_1256, 11, 0) - node T_1263 = shl(T_1262, 4) - node T_1264 = not(T_1259) - node T_1265 = and(T_1263, T_1264) - node T_1266 = or(T_1261, T_1265) - node T_1267 = bits(T_1259, 13, 0) - node T_1268 = shl(T_1267, 2) - node T_1269 = xor(T_1259, T_1268) - node T_1270 = shr(T_1266, 2) - node T_1271 = and(T_1270, T_1269) - node T_1272 = bits(T_1266, 13, 0) - node T_1273 = shl(T_1272, 2) - node T_1274 = not(T_1269) - node T_1275 = and(T_1273, T_1274) - node T_1276 = or(T_1271, T_1275) - node T_1277 = bits(T_1269, 14, 0) - node T_1278 = shl(T_1277, 1) - node T_1279 = xor(T_1269, T_1278) - node T_1280 = shr(T_1276, 1) - node T_1281 = and(T_1280, T_1279) - node T_1282 = bits(T_1276, 14, 0) - node T_1283 = shl(T_1282, 1) - node T_1284 = not(T_1279) - node T_1285 = and(T_1283, T_1284) - node T_1286 = or(T_1281, T_1285) - node T_1287 = bits(T_1244, 20, 16) - node T_1288 = bits(T_1287, 3, 0) - node T_1289 = bits(T_1288, 1, 0) - node T_1290 = bits(T_1289, 0, 0) - node T_1291 = bits(T_1289, 1, 1) - node T_1292 = cat(T_1290, T_1291) - node T_1293 = bits(T_1288, 3, 2) - node T_1294 = bits(T_1293, 0, 0) - node T_1295 = bits(T_1293, 1, 1) - node T_1296 = cat(T_1294, T_1295) - node T_1297 = cat(T_1292, T_1296) - node T_1298 = bits(T_1287, 4, 4) - node T_1299 = cat(T_1297, T_1298) - node T_1300 = cat(T_1286, T_1299) - node roundMask_E = cat(T_1243, T_1300) - node T_1303 = cat(UInt<1>("h00"), roundMask_E) - node T_1304 = not(T_1303) - node T_1306 = cat(roundMask_E, UInt<1>("h01")) - node incrPosMask_E = and(T_1304, T_1306) - node T_1308 = shr(incrPosMask_E, 1) - node T_1309 = and(sigT_E, T_1308) - node hiRoundPosBitT_E = neq(T_1309, UInt<1>("h00")) - node T_1312 = shr(roundMask_E, 1) - node T_1313 = and(sigT_E, T_1312) - node all0sHiRoundExtraT_E = eq(T_1313, UInt<1>("h00")) - node T_1316 = not(sigT_E) - node T_1317 = shr(roundMask_E, 1) - node T_1318 = and(T_1316, T_1317) - node all1sHiRoundExtraT_E = eq(T_1318, UInt<1>("h00")) - node T_1321 = bits(roundMask_E, 0, 0) - node T_1322 = not(T_1321) - node T_1323 = or(T_1322, hiRoundPosBitT_E) - node all1sHiRoundT_E = and(T_1323, all1sHiRoundExtraT_E) - node T_1326 = add(UInt<54>("h00"), sigT_E) - node T_1327 = tail(T_1326, 1) - node T_1328 = add(T_1327, roundMagUp_PC) - node sigAdjT_E = tail(T_1328, 1) - node T_1331 = not(roundMask_E) - node T_1332 = cat(UInt<1>("h01"), T_1331) - node sigY0_E = and(sigAdjT_E, T_1332) - node T_1335 = cat(UInt<1>("h00"), roundMask_E) - node T_1336 = or(sigAdjT_E, T_1335) - node T_1338 = add(T_1336, UInt<1>("h01")) - node sigY1_E = tail(T_1338, 1) - node T_1340 = not(isNegRemT_E) - node T_1341 = not(trueEqX_E1) - node T_1342 = and(T_1340, T_1341) - node trueLtX_E1 = mux(sqrtOp_PC, T_1342, isNegRemT_E) - node T_1344 = bits(roundMask_E, 0, 0) - node T_1345 = not(trueLtX_E1) - node T_1346 = and(T_1344, T_1345) - node T_1347 = and(T_1346, all1sHiRoundExtraT_E) - node T_1348 = and(T_1347, extraT_E) - node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1348) - node T_1350 = not(trueEqX_E1) - node T_1351 = not(extraT_E) - node T_1352 = or(T_1350, T_1351) - node T_1353 = not(all1sHiRoundExtraT_E) - node anyRoundExtra_E1 = or(T_1352, T_1353) - node T_1355 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) - node T_1356 = not(anyRoundExtra_E1) - node T_1357 = and(T_1355, T_1356) - node roundEvenMask_E1 = mux(T_1357, incrPosMask_E, UInt<1>("h00")) - node T_1360 = and(roundMagDown_PC, extraT_E) - node T_1361 = not(trueLtX_E1) - node T_1362 = and(T_1360, T_1361) - node T_1363 = and(T_1362, all1sHiRoundT_E) - node T_1364 = not(trueLtX_E1) - node T_1365 = and(extraT_E, T_1364) - node T_1366 = not(trueEqX_E1) - node T_1367 = and(T_1365, T_1366) - node T_1368 = not(all1sHiRoundT_E) - node T_1369 = or(T_1367, T_1368) - node T_1370 = and(roundMagUp_PC, T_1369) - node T_1371 = or(T_1363, T_1370) - node T_1372 = not(trueLtX_E1) - node T_1373 = or(extraT_E, T_1372) - node T_1374 = bits(roundMask_E, 0, 0) - node T_1375 = not(T_1374) - node T_1376 = and(T_1373, T_1375) - node T_1377 = or(hiRoundPosBitT_E, T_1376) - node T_1378 = not(trueLtX_E1) - node T_1379 = and(extraT_E, T_1378) - node T_1380 = and(T_1379, all1sHiRoundExtraT_E) - node T_1381 = or(T_1377, T_1380) - node T_1382 = and(roundingMode_near_even_PC, T_1381) - node T_1383 = or(T_1371, T_1382) - node T_1384 = mux(T_1383, sigY1_E, sigY0_E) - node T_1385 = not(roundEvenMask_E1) - node sigY_E1 = and(T_1384, T_1385) - node fractY_E1 = bits(sigY_E1, 51, 0) - node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) - node T_1389 = bits(sigY_E1, 53, 53) - node T_1390 = not(T_1389) - node T_1392 = mux(T_1390, sExpX_E, UInt<1>("h00")) - node T_1393 = bits(sigY_E1, 53, 53) - node T_1394 = not(sqrtOp_PC) - node T_1395 = and(T_1393, T_1394) - node T_1396 = and(T_1395, E_E_div) - node T_1398 = mux(T_1396, expP1_PC, UInt<1>("h00")) - node T_1399 = or(T_1392, T_1398) - node T_1400 = bits(sigY_E1, 53, 53) - node T_1401 = not(sqrtOp_PC) - node T_1402 = and(T_1400, T_1401) - node T_1403 = not(E_E_div) - node T_1404 = and(T_1402, T_1403) - node T_1406 = mux(T_1404, expP2_PC, UInt<1>("h00")) - node T_1407 = or(T_1399, T_1406) - node T_1408 = bits(sigY_E1, 53, 53) - node T_1409 = and(T_1408, sqrtOp_PC) - node T_1410 = shr(expP2_PC, 1) - node T_1412 = add(T_1410, UInt<12>("h0400")) - node T_1413 = tail(T_1412, 1) - node T_1415 = mux(T_1409, T_1413, UInt<1>("h00")) - node sExpY_E1 = or(T_1407, T_1415) - node expY_E1 = bits(sExpY_E1, 11, 0) - node T_1418 = bits(sExpY_E1, 13, 13) - node T_1419 = not(T_1418) - node T_1421 = bits(sExpY_E1, 12, 10) - node T_1422 = leq(UInt<3>("h03"), T_1421) - node overflowY_E1 = and(T_1419, T_1422) - node T_1424 = bits(sExpY_E1, 13, 13) - node T_1425 = bits(sExpY_E1, 12, 0) - node T_1427 = lt(T_1425, UInt<13>("h03ce")) - node totalUnderflowY_E1 = or(T_1424, T_1427) - node T_1430 = leq(posExpX_E, UInt<13>("h0401")) - node T_1431 = and(T_1430, inexactY_E1) - node underflowY_E1 = or(totalUnderflowY_E1, T_1431) - node T_1433 = not(isNaNB_PC) - node T_1434 = not(isZeroB_PC) - node T_1435 = and(T_1433, T_1434) - node T_1436 = and(T_1435, sign_PC) - node T_1437 = and(isZeroA_PC, isZeroB_PC) - node T_1438 = and(isInfA_PC, isInfB_PC) - node T_1439 = or(T_1437, T_1438) - node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1436, T_1439) - node T_1441 = not(sqrtOp_PC) - node T_1442 = and(T_1441, isSigNaNA_PC) - node T_1443 = or(T_1442, isSigNaNB_PC) - node invalid_PC = or(T_1443, notSigNaN_invalid_PC) - node T_1445 = not(sqrtOp_PC) - node T_1446 = not(isSpecialA_PC) - node T_1447 = and(T_1445, T_1446) - node T_1448 = not(isZeroA_PC) - node T_1449 = and(T_1447, T_1448) - node infinity_PC = and(T_1449, isZeroB_PC) - node overflow_E1 = and(normalCase_PC, overflowY_E1) - node underflow_E1 = and(normalCase_PC, underflowY_E1) - node T_1453 = or(overflow_E1, underflow_E1) - node T_1454 = and(normalCase_PC, inexactY_E1) - node inexact_E1 = or(T_1453, T_1454) - node T_1456 = or(isZeroA_PC, isInfB_PC) - node T_1457 = not(roundMagUp_PC) - node T_1458 = and(totalUnderflowY_E1, T_1457) - node T_1459 = or(T_1456, T_1458) - node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1459) - node T_1461 = and(normalCase_PC, totalUnderflowY_E1) - node pegMinFiniteMagOut_E1 = and(T_1461, roundMagUp_PC) - node T_1463 = not(overflowY_roundMagUp_PC) - node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1463) - node T_1465 = or(isInfA_PC, isZeroB_PC) - node T_1466 = and(overflow_E1, overflowY_roundMagUp_PC) - node T_1467 = or(T_1465, T_1466) - node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1467) - node T_1469 = not(sqrtOp_PC) - node T_1470 = and(T_1469, isNaNA_PC) - node T_1471 = or(T_1470, isNaNB_PC) - node isNaNOut_PC = or(T_1471, notSigNaN_invalid_PC) - node T_1473 = not(isNaNOut_PC) - node T_1474 = and(isZeroB_PC, sign_PC) - node T_1475 = mux(sqrtOp_PC, T_1474, sign_PC) - node signOut_PC = and(T_1473, T_1475) - node T_1478 = not(UInt<12>("h01ff")) - node T_1480 = mux(notSpecial_isZeroOut_E1, T_1478, UInt<1>("h00")) - node T_1481 = not(T_1480) - node T_1482 = and(expY_E1, T_1481) - node T_1484 = not(UInt<12>("h03ce")) - node T_1486 = mux(pegMinFiniteMagOut_E1, T_1484, UInt<1>("h00")) - node T_1487 = not(T_1486) - node T_1488 = and(T_1482, T_1487) - node T_1490 = not(UInt<12>("h0bff")) - node T_1492 = mux(pegMaxFiniteMagOut_E1, T_1490, UInt<1>("h00")) - node T_1493 = not(T_1492) - node T_1494 = and(T_1488, T_1493) - node T_1496 = not(UInt<12>("h0dff")) - node T_1498 = mux(notNaN_isInfOut_E1, T_1496, UInt<1>("h00")) - node T_1499 = not(T_1498) - node T_1500 = and(T_1494, T_1499) - node T_1503 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) - node T_1504 = or(T_1500, T_1503) - node T_1507 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) - node T_1508 = or(T_1504, T_1507) - node T_1511 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) - node T_1512 = or(T_1508, T_1511) - node T_1515 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) - node expOut_E1 = or(T_1512, T_1515) - node T_1517 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) - node T_1518 = or(T_1517, isNaNOut_PC) - node T_1520 = mux(T_1518, UInt<1>("h00"), fractY_E1) - node T_1522 = sub(UInt<52>("h00"), pegMaxFiniteMagOut_E1) - node T_1523 = tail(T_1522, 1) - node T_1524 = or(T_1520, T_1523) - node T_1525 = shl(isNaNOut_PC, 51) - node fractOut_E1 = or(T_1524, T_1525) - node T_1527 = cat(expOut_E1, fractOut_E1) - node T_1528 = cat(signOut_PC, T_1527) - io.out <= T_1528 - node T_1529 = cat(invalid_PC, infinity_PC) - node T_1530 = cat(underflow_E1, inexact_E1) - node T_1531 = cat(overflow_E1, T_1530) - node T_1532 = cat(T_1529, T_1531) - io.exceptionFlags <= T_1532 + io is invalid + inst Queue of Queue_52 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + wire _T_484 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_484 is invalid @[Decoupled.scala 272:19] + _T_484.bits <- Queue.io.deq.bits @[Decoupled.scala 273:14] + _T_484.valid <= Queue.io.deq.valid @[Decoupled.scala 274:15] + Queue.io.deq.ready <= _T_484.ready @[Decoupled.scala 275:15] + wire _T_509 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_509 is invalid @[Fragmenter.scala 66:23] + reg _T_535 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_537 : UInt<12>, clock @[Fragmenter.scala 69:25] + reg _T_539 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_540 = mux(_T_535, _T_539, _T_484.bits.len) @[Fragmenter.scala 72:23] + node _T_541 = mux(_T_535, _T_537, _T_484.bits.addr) @[Fragmenter.scala 73:23] + node _T_542 = bits(_T_541, 2, 0) @[Fragmenter.scala 75:53] + node _T_543 = shr(_T_541, 3) @[Fragmenter.scala 76:23] + node _T_544 = bits(_T_543, 7, 0) @[Fragmenter.scala 77:27] + node _T_546 = xor(_T_541, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_547 = cvt(_T_546) @[Parameters.scala 117:49] + node _T_549 = and(_T_547, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_550 = asSInt(_T_549) @[Parameters.scala 117:52] + node _T_552 = eq(_T_550, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_555 : UInt<1>[1] @[Parameters.scala 50:36] + _T_555 is invalid @[Parameters.scala 50:36] + _T_555[0] <= _T_552 @[Parameters.scala 50:36] + node _T_561 = shr(_T_540, 1) @[package.scala 32:45] + node _T_562 = or(_T_540, _T_561) @[package.scala 32:40] + node _T_563 = shr(_T_562, 2) @[package.scala 32:45] + node _T_564 = or(_T_562, _T_563) @[package.scala 32:40] + node _T_565 = shr(_T_564, 4) @[package.scala 32:45] + node _T_566 = or(_T_564, _T_565) @[package.scala 32:40] + node _T_567 = shr(_T_566, 1) @[Fragmenter.scala 89:37] + node _T_568 = not(_T_540) @[Fragmenter.scala 90:32] + node _T_569 = shl(_T_568, 1) @[package.scala 25:45] + node _T_570 = bits(_T_569, 7, 0) @[package.scala 25:50] + node _T_571 = or(_T_568, _T_570) @[package.scala 25:40] + node _T_572 = shl(_T_571, 2) @[package.scala 25:45] + node _T_573 = bits(_T_572, 7, 0) @[package.scala 25:50] + node _T_574 = or(_T_571, _T_573) @[package.scala 25:40] + node _T_575 = shl(_T_574, 4) @[package.scala 25:45] + node _T_576 = bits(_T_575, 7, 0) @[package.scala 25:50] + node _T_577 = or(_T_574, _T_576) @[package.scala 25:40] + node _T_578 = not(_T_577) @[Fragmenter.scala 90:24] + node _T_579 = or(_T_567, _T_578) @[Fragmenter.scala 91:32] + node _T_580 = shl(_T_544, 1) @[package.scala 25:45] + node _T_581 = bits(_T_580, 7, 0) @[package.scala 25:50] + node _T_582 = or(_T_544, _T_581) @[package.scala 25:40] + node _T_583 = shl(_T_582, 2) @[package.scala 25:45] + node _T_584 = bits(_T_583, 7, 0) @[package.scala 25:50] + node _T_585 = or(_T_582, _T_584) @[package.scala 25:40] + node _T_586 = shl(_T_585, 4) @[package.scala 25:45] + node _T_587 = bits(_T_586, 7, 0) @[package.scala 25:50] + node _T_588 = or(_T_585, _T_587) @[package.scala 25:40] + node _T_589 = not(_T_588) @[Fragmenter.scala 92:24] + node _T_590 = and(_T_579, _T_589) @[Fragmenter.scala 94:37] + node _T_591 = and(_T_590, UInt<1>("h00")) @[Fragmenter.scala 94:46] + node _T_593 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_595 = neq(_T_484.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_596 = or(_T_593, _T_595) @[Fragmenter.scala 99:25] + node _T_598 = mux(_T_596, UInt<1>("h00"), _T_591) @[Fragmenter.scala 102:25] + node _T_599 = shl(_T_598, 1) @[package.scala 17:29] + node _T_601 = or(_T_599, UInt<1>("h01")) @[package.scala 17:34] + node _T_603 = cat(UInt<1>("h00"), _T_598) @[Cat.scala 30:58] + node _T_604 = not(_T_603) @[package.scala 17:47] + node _T_605 = and(_T_601, _T_604) @[package.scala 17:45] + node _T_606 = dshl(_T_605, _T_484.bits.size) @[Fragmenter.scala 105:38] + node _T_607 = add(_T_541, _T_606) @[Fragmenter.scala 105:29] + node _T_608 = tail(_T_607, 1) @[Fragmenter.scala 105:29] + node _T_610 = cat(_T_484.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_611 = dshl(_T_610, _T_484.bits.size) @[Bundles.scala 28:21] + node _T_612 = shr(_T_611, 8) @[Bundles.scala 28:30] + wire _T_613 : UInt + _T_613 is invalid + _T_613 <= _T_608 + node _T_615 = eq(_T_484.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_615 : @[Fragmenter.scala 108:59] + node _T_616 = and(_T_608, _T_612) @[Fragmenter.scala 109:33] + node _T_617 = not(_T_484.bits.addr) @[Fragmenter.scala 109:49] + node _T_618 = or(_T_617, _T_612) @[Fragmenter.scala 109:62] + node _T_619 = not(_T_618) @[Fragmenter.scala 109:47] + node _T_620 = or(_T_616, _T_619) @[Fragmenter.scala 109:45] + _T_613 <= _T_620 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_622 = eq(_T_484.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_622 : @[Fragmenter.scala 111:60] + _T_613 <= _T_484.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_623 = eq(_T_598, _T_540) @[Fragmenter.scala 115:27] + node _T_624 = and(_T_509.ready, _T_623) @[Fragmenter.scala 116:30] + _T_484.ready <= _T_624 @[Fragmenter.scala 116:17] + _T_509.valid <= _T_484.valid @[Fragmenter.scala 117:19] + _T_509.bits <- _T_484.bits @[Fragmenter.scala 119:18] + _T_509.bits.len <= _T_598 @[Fragmenter.scala 120:22] + node _T_625 = not(_T_541) @[Fragmenter.scala 127:28] + node _T_627 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_628 = dshl(_T_627, _T_484.bits.size) @[package.scala 19:71] + node _T_629 = bits(_T_628, 2, 0) @[package.scala 19:76] + node _T_630 = not(_T_629) @[package.scala 19:40] + node _T_631 = or(_T_625, _T_630) @[Fragmenter.scala 127:34] + node _T_632 = not(_T_631) @[Fragmenter.scala 127:26] + _T_509.bits.addr <= _T_632 @[Fragmenter.scala 127:23] + node _T_633 = and(_T_509.ready, _T_509.valid) @[Decoupled.scala 30:37] + when _T_633 : @[Fragmenter.scala 129:27] + node _T_635 = eq(_T_623, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_535 <= _T_635 @[Fragmenter.scala 130:16] + _T_537 <= _T_613 @[Fragmenter.scala 131:18] + node _T_636 = sub(_T_540, _T_605) @[Fragmenter.scala 132:25] + node _T_637 = asUInt(_T_636) @[Fragmenter.scala 132:25] + node _T_638 = tail(_T_637, 1) @[Fragmenter.scala 132:25] + _T_539 <= _T_638 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + inst Queue_1 of Queue_53 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + wire _T_674 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Decoupled.scala 272:19] + _T_674 is invalid @[Decoupled.scala 272:19] + _T_674.bits <- Queue_1.io.deq.bits @[Decoupled.scala 273:14] + _T_674.valid <= Queue_1.io.deq.valid @[Decoupled.scala 274:15] + Queue_1.io.deq.ready <= _T_674.ready @[Decoupled.scala 275:15] + wire _T_699 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 66:23] + _T_699 is invalid @[Fragmenter.scala 66:23] + reg _T_725 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + reg _T_727 : UInt<12>, clock @[Fragmenter.scala 69:25] + reg _T_729 : UInt<8>, clock @[Fragmenter.scala 70:25] + node _T_730 = mux(_T_725, _T_729, _T_674.bits.len) @[Fragmenter.scala 72:23] + node _T_731 = mux(_T_725, _T_727, _T_674.bits.addr) @[Fragmenter.scala 73:23] + node _T_732 = bits(_T_731, 2, 0) @[Fragmenter.scala 75:53] + node _T_733 = shr(_T_731, 3) @[Fragmenter.scala 76:23] + node _T_734 = bits(_T_733, 7, 0) @[Fragmenter.scala 77:27] + node _T_736 = xor(_T_731, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_737 = cvt(_T_736) @[Parameters.scala 117:49] + node _T_739 = and(_T_737, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:52] + node _T_740 = asSInt(_T_739) @[Parameters.scala 117:52] + node _T_742 = eq(_T_740, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + wire _T_745 : UInt<1>[1] @[Parameters.scala 50:36] + _T_745 is invalid @[Parameters.scala 50:36] + _T_745[0] <= _T_742 @[Parameters.scala 50:36] + node _T_751 = shr(_T_730, 1) @[package.scala 32:45] + node _T_752 = or(_T_730, _T_751) @[package.scala 32:40] + node _T_753 = shr(_T_752, 2) @[package.scala 32:45] + node _T_754 = or(_T_752, _T_753) @[package.scala 32:40] + node _T_755 = shr(_T_754, 4) @[package.scala 32:45] + node _T_756 = or(_T_754, _T_755) @[package.scala 32:40] + node _T_757 = shr(_T_756, 1) @[Fragmenter.scala 89:37] + node _T_758 = not(_T_730) @[Fragmenter.scala 90:32] + node _T_759 = shl(_T_758, 1) @[package.scala 25:45] + node _T_760 = bits(_T_759, 7, 0) @[package.scala 25:50] + node _T_761 = or(_T_758, _T_760) @[package.scala 25:40] + node _T_762 = shl(_T_761, 2) @[package.scala 25:45] + node _T_763 = bits(_T_762, 7, 0) @[package.scala 25:50] + node _T_764 = or(_T_761, _T_763) @[package.scala 25:40] + node _T_765 = shl(_T_764, 4) @[package.scala 25:45] + node _T_766 = bits(_T_765, 7, 0) @[package.scala 25:50] + node _T_767 = or(_T_764, _T_766) @[package.scala 25:40] + node _T_768 = not(_T_767) @[Fragmenter.scala 90:24] + node _T_769 = or(_T_757, _T_768) @[Fragmenter.scala 91:32] + node _T_770 = shl(_T_734, 1) @[package.scala 25:45] + node _T_771 = bits(_T_770, 7, 0) @[package.scala 25:50] + node _T_772 = or(_T_734, _T_771) @[package.scala 25:40] + node _T_773 = shl(_T_772, 2) @[package.scala 25:45] + node _T_774 = bits(_T_773, 7, 0) @[package.scala 25:50] + node _T_775 = or(_T_772, _T_774) @[package.scala 25:40] + node _T_776 = shl(_T_775, 4) @[package.scala 25:45] + node _T_777 = bits(_T_776, 7, 0) @[package.scala 25:50] + node _T_778 = or(_T_775, _T_777) @[package.scala 25:40] + node _T_779 = not(_T_778) @[Fragmenter.scala 92:24] + node _T_780 = and(_T_769, _T_779) @[Fragmenter.scala 94:37] + node _T_781 = and(_T_780, UInt<1>("h00")) @[Fragmenter.scala 94:46] + node _T_783 = eq(_T_674.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 97:34] + node _T_785 = neq(_T_674.bits.size, UInt<2>("h03")) @[Fragmenter.scala 98:34] + node _T_786 = or(_T_783, _T_785) @[Fragmenter.scala 99:25] + node _T_788 = mux(_T_786, UInt<1>("h00"), _T_781) @[Fragmenter.scala 102:25] + node _T_789 = shl(_T_788, 1) @[package.scala 17:29] + node _T_791 = or(_T_789, UInt<1>("h01")) @[package.scala 17:34] + node _T_793 = cat(UInt<1>("h00"), _T_788) @[Cat.scala 30:58] + node _T_794 = not(_T_793) @[package.scala 17:47] + node _T_795 = and(_T_791, _T_794) @[package.scala 17:45] + node _T_796 = dshl(_T_795, _T_674.bits.size) @[Fragmenter.scala 105:38] + node _T_797 = add(_T_731, _T_796) @[Fragmenter.scala 105:29] + node _T_798 = tail(_T_797, 1) @[Fragmenter.scala 105:29] + node _T_800 = cat(_T_674.bits.len, UInt<8>("h0ff")) @[Cat.scala 30:58] + node _T_801 = dshl(_T_800, _T_674.bits.size) @[Bundles.scala 28:21] + node _T_802 = shr(_T_801, 8) @[Bundles.scala 28:30] + wire _T_803 : UInt + _T_803 is invalid + _T_803 <= _T_798 + node _T_805 = eq(_T_674.bits.burst, UInt<2>("h02")) @[Fragmenter.scala 108:28] + when _T_805 : @[Fragmenter.scala 108:59] + node _T_806 = and(_T_798, _T_802) @[Fragmenter.scala 109:33] + node _T_807 = not(_T_674.bits.addr) @[Fragmenter.scala 109:49] + node _T_808 = or(_T_807, _T_802) @[Fragmenter.scala 109:62] + node _T_809 = not(_T_808) @[Fragmenter.scala 109:47] + node _T_810 = or(_T_806, _T_809) @[Fragmenter.scala 109:45] + _T_803 <= _T_810 @[Fragmenter.scala 109:20] + skip @[Fragmenter.scala 108:59] + node _T_812 = eq(_T_674.bits.burst, UInt<2>("h00")) @[Fragmenter.scala 111:28] + when _T_812 : @[Fragmenter.scala 111:60] + _T_803 <= _T_674.bits.addr @[Fragmenter.scala 112:20] + skip @[Fragmenter.scala 111:60] + node _T_813 = eq(_T_788, _T_730) @[Fragmenter.scala 115:27] + node _T_814 = and(_T_699.ready, _T_813) @[Fragmenter.scala 116:30] + _T_674.ready <= _T_814 @[Fragmenter.scala 116:17] + _T_699.valid <= _T_674.valid @[Fragmenter.scala 117:19] + _T_699.bits <- _T_674.bits @[Fragmenter.scala 119:18] + _T_699.bits.len <= _T_788 @[Fragmenter.scala 120:22] + node _T_815 = not(_T_731) @[Fragmenter.scala 127:28] + node _T_817 = asUInt(asSInt(UInt<3>("h07"))) @[package.scala 19:64] + node _T_818 = dshl(_T_817, _T_674.bits.size) @[package.scala 19:71] + node _T_819 = bits(_T_818, 2, 0) @[package.scala 19:76] + node _T_820 = not(_T_819) @[package.scala 19:40] + node _T_821 = or(_T_815, _T_820) @[Fragmenter.scala 127:34] + node _T_822 = not(_T_821) @[Fragmenter.scala 127:26] + _T_699.bits.addr <= _T_822 @[Fragmenter.scala 127:23] + node _T_823 = and(_T_699.ready, _T_699.valid) @[Decoupled.scala 30:37] + when _T_823 : @[Fragmenter.scala 129:27] + node _T_825 = eq(_T_813, UInt<1>("h00")) @[Fragmenter.scala 130:19] + _T_725 <= _T_825 @[Fragmenter.scala 130:16] + _T_727 <= _T_803 @[Fragmenter.scala 131:18] + node _T_826 = sub(_T_730, _T_795) @[Fragmenter.scala 132:25] + node _T_827 = asUInt(_T_826) @[Fragmenter.scala 132:25] + node _T_828 = tail(_T_827, 1) @[Fragmenter.scala 132:25] + _T_729 <= _T_828 @[Fragmenter.scala 132:18] + skip @[Fragmenter.scala 129:27] + wire _T_829 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}} @[Fragmenter.scala 148:24] + _T_829 is invalid @[Fragmenter.scala 148:24] + wire _T_854 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}} @[Fragmenter.scala 151:23] + _T_854 is invalid @[Fragmenter.scala 151:23] + wire _T_869 : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}} @[Fragmenter.scala 152:23] + _T_869 is invalid @[Fragmenter.scala 152:23] + inst Queue_2 of Queue_54 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= _T_829.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- _T_829.bits @[Decoupled.scala 255:19] + _T_829.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_2.io.deq @[Fragmenter.scala 158:16] + _T_854 <- io.out.0.r @[Fragmenter.scala 159:15] + inst Queue_3 of Queue_55 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + _T_869 <- Queue_3.io.deq @[Fragmenter.scala 165:13] + inst AXI4FragmenterAXI4FragmenterSideband of AXI4FragmenterAXI4FragmenterSideband_4 @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband.io is invalid + AXI4FragmenterAXI4FragmenterSideband.clock <= clock + AXI4FragmenterAXI4FragmenterSideband.reset <= reset + inst AXI4FragmenterAXI4FragmenterSideband_1 of AXI4FragmenterAXI4FragmenterSideband_5 @[Fragmenter.scala 171:15] + AXI4FragmenterAXI4FragmenterSideband_1.io is invalid + AXI4FragmenterAXI4FragmenterSideband_1.clock <= clock + AXI4FragmenterAXI4FragmenterSideband_1.reset <= reset + node _T_893 = and(_T_509.valid, AXI4FragmenterAXI4FragmenterSideband.io.enq.ready) @[Fragmenter.scala 177:35] + _T_829.valid <= _T_893 @[Fragmenter.scala 177:20] + node _T_894 = and(AXI4FragmenterAXI4FragmenterSideband.io.enq.ready, _T_829.ready) @[Fragmenter.scala 178:46] + _T_509.ready <= _T_894 @[Fragmenter.scala 178:19] + node _T_895 = and(_T_509.valid, _T_829.ready) @[Fragmenter.scala 179:46] + AXI4FragmenterAXI4FragmenterSideband.io.enq.valid <= _T_895 @[Fragmenter.scala 179:31] + _T_829.bits <- _T_509.bits @[Fragmenter.scala 180:19] + AXI4FragmenterAXI4FragmenterSideband.io.enq.bits <= _T_623 @[Fragmenter.scala 181:30] + reg _T_897 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + wire _T_899 : UInt<1> @[Fragmenter.scala 185:30] + _T_899 is invalid @[Fragmenter.scala 185:30] + wire _T_901 : UInt<1> @[Fragmenter.scala 186:30] + _T_901 is invalid @[Fragmenter.scala 186:30] + node _T_902 = and(_T_901, _T_899) @[Fragmenter.scala 187:26] + when _T_902 : @[Fragmenter.scala 187:43] + _T_897 <= UInt<1>("h01") @[Fragmenter.scala 187:60] + skip @[Fragmenter.scala 187:43] + node _T_904 = and(io.out.0.aw.ready, io.out.0.aw.valid) @[Decoupled.scala 30:37] + when _T_904 : @[Fragmenter.scala 188:28] + _T_897 <= UInt<1>("h00") @[Fragmenter.scala 188:45] + skip @[Fragmenter.scala 188:28] + node _T_906 = and(_T_699.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready) @[Fragmenter.scala 191:35] + node _T_907 = or(_T_899, _T_897) @[Fragmenter.scala 191:79] + node _T_908 = and(_T_906, _T_907) @[Fragmenter.scala 191:62] + io.out.0.aw.valid <= _T_908 @[Fragmenter.scala 191:20] + node _T_909 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.enq.ready, io.out.0.aw.ready) @[Fragmenter.scala 192:46] + node _T_910 = or(_T_899, _T_897) @[Fragmenter.scala 192:79] + node _T_911 = and(_T_909, _T_910) @[Fragmenter.scala 192:62] + _T_699.ready <= _T_911 @[Fragmenter.scala 192:19] + node _T_912 = and(_T_699.valid, io.out.0.aw.ready) @[Fragmenter.scala 193:46] + node _T_913 = or(_T_899, _T_897) @[Fragmenter.scala 193:79] + node _T_914 = and(_T_912, _T_913) @[Fragmenter.scala 193:62] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.valid <= _T_914 @[Fragmenter.scala 193:31] + node _T_916 = eq(_T_897, UInt<1>("h00")) @[Fragmenter.scala 194:38] + node _T_917 = and(_T_699.valid, _T_916) @[Fragmenter.scala 194:35] + _T_901 <= _T_917 @[Fragmenter.scala 194:20] + io.out.0.aw.bits <- _T_699.bits @[Fragmenter.scala 195:19] + AXI4FragmenterAXI4FragmenterSideband_1.io.enq.bits <= _T_813 @[Fragmenter.scala 196:30] + reg _T_919 : UInt<9>, clock with : (reset => (reset, UInt<9>("h00"))) @[Reg.scala 26:44] + node _T_921 = eq(_T_919, UInt<1>("h00")) @[Fragmenter.scala 200:30] + node _T_923 = mux(_T_901, _T_795, UInt<1>("h00")) @[Fragmenter.scala 201:35] + node _T_924 = mux(_T_921, _T_923, _T_919) @[Fragmenter.scala 201:23] + node _T_926 = eq(_T_924, UInt<1>("h01")) @[Fragmenter.scala 202:27] + node _T_927 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_928 = sub(_T_924, _T_927) @[Fragmenter.scala 203:27] + node _T_929 = asUInt(_T_928) @[Fragmenter.scala 203:27] + node _T_930 = tail(_T_929, 1) @[Fragmenter.scala 203:27] + _T_919 <= _T_930 @[Fragmenter.scala 203:17] + node _T_931 = and(io.out.0.w.ready, io.out.0.w.valid) @[Decoupled.scala 30:37] + node _T_933 = eq(_T_931, UInt<1>("h00")) @[Fragmenter.scala 204:15] + node _T_935 = neq(_T_924, UInt<1>("h00")) @[Fragmenter.scala 204:39] + node _T_936 = or(_T_933, _T_935) @[Fragmenter.scala 204:29] + node _T_937 = or(_T_936, reset) @[Fragmenter.scala 204:14] + node _T_939 = eq(_T_937, UInt<1>("h00")) @[Fragmenter.scala 204:14] + when _T_939 : @[Fragmenter.scala 204:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:204 assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible\n") @[Fragmenter.scala 204:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 204:14] + skip @[Fragmenter.scala 204:14] + _T_899 <= _T_921 @[Fragmenter.scala 207:20] + node _T_941 = eq(_T_899, UInt<1>("h00")) @[Fragmenter.scala 208:37] + node _T_942 = or(_T_941, _T_901) @[Fragmenter.scala 208:51] + node _T_943 = and(io.in.0.w.valid, _T_942) @[Fragmenter.scala 208:33] + io.out.0.w.valid <= _T_943 @[Fragmenter.scala 208:19] + node _T_945 = eq(_T_899, UInt<1>("h00")) @[Fragmenter.scala 209:37] + node _T_946 = or(_T_945, _T_901) @[Fragmenter.scala 209:51] + node _T_947 = and(io.out.0.w.ready, _T_946) @[Fragmenter.scala 209:33] + io.in.0.w.ready <= _T_947 @[Fragmenter.scala 209:18] + io.out.0.w.bits <- io.in.0.w.bits @[Fragmenter.scala 210:18] + io.out.0.w.bits.last <= _T_926 @[Fragmenter.scala 211:23] + node _T_949 = eq(io.out.0.w.valid, UInt<1>("h00")) @[Fragmenter.scala 213:15] + node _T_951 = eq(io.in.0.w.bits.last, UInt<1>("h00")) @[Fragmenter.scala 213:31] + node _T_952 = or(_T_949, _T_951) @[Fragmenter.scala 213:28] + node _T_953 = or(_T_952, _T_926) @[Fragmenter.scala 213:47] + node _T_954 = or(_T_953, reset) @[Fragmenter.scala 213:14] + node _T_956 = eq(_T_954, UInt<1>("h00")) @[Fragmenter.scala 213:14] + when _T_956 : @[Fragmenter.scala 213:14] + printf(clock, UInt<1>(1), "Assertion failed\n at Fragmenter.scala:213 assert (!out_w.valid || !in_w.bits.last || w_last)\n") @[Fragmenter.scala 213:14] + stop(clock, UInt<1>(1), 1) @[Fragmenter.scala 213:14] + skip @[Fragmenter.scala 213:14] + node _T_958 = eq(_T_854.bits.last, UInt<1>("h00")) @[Fragmenter.scala 217:37] + node _T_959 = or(_T_958, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 217:45] + node _T_960 = and(_T_854.valid, _T_959) @[Fragmenter.scala 217:33] + io.in.0.r.valid <= _T_960 @[Fragmenter.scala 217:18] + node _T_962 = eq(_T_854.bits.last, UInt<1>("h00")) @[Fragmenter.scala 218:37] + node _T_963 = or(_T_962, AXI4FragmenterAXI4FragmenterSideband.io.deq.valid) @[Fragmenter.scala 218:45] + node _T_964 = and(io.in.0.r.ready, _T_963) @[Fragmenter.scala 218:33] + _T_854.ready <= _T_964 @[Fragmenter.scala 218:19] + node _T_965 = and(_T_854.bits.last, _T_854.valid) @[Fragmenter.scala 219:41] + node _T_966 = and(_T_965, io.in.0.r.ready) @[Fragmenter.scala 219:56] + AXI4FragmenterAXI4FragmenterSideband.io.deq.ready <= _T_966 @[Fragmenter.scala 219:31] + io.in.0.r.bits <- _T_854.bits @[Fragmenter.scala 220:17] + node _T_967 = and(_T_854.bits.last, AXI4FragmenterAXI4FragmenterSideband.io.deq.bits) @[Fragmenter.scala 221:32] + io.in.0.r.bits.last <= _T_967 @[Fragmenter.scala 221:22] + node _T_968 = and(_T_869.valid, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid) @[Fragmenter.scala 225:33] + node _T_969 = and(_T_968, AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits) @[Fragmenter.scala 225:60] + io.in.0.b.valid <= _T_969 @[Fragmenter.scala 225:18] + node _T_971 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 226:50] + node _T_972 = or(_T_971, io.in.0.b.ready) @[Fragmenter.scala 226:58] + node _T_973 = and(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.valid, _T_972) @[Fragmenter.scala 226:46] + _T_869.ready <= _T_973 @[Fragmenter.scala 226:19] + node _T_975 = eq(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00")) @[Fragmenter.scala 227:50] + node _T_976 = or(_T_975, io.in.0.b.ready) @[Fragmenter.scala 227:58] + node _T_977 = and(_T_869.valid, _T_976) @[Fragmenter.scala 227:46] + AXI4FragmenterAXI4FragmenterSideband_1.io.deq.ready <= _T_977 @[Fragmenter.scala 227:31] + io.in.0.b.bits <- _T_869.bits @[Fragmenter.scala 228:17] + reg _T_979 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[Reg.scala 26:44] + node _T_980 = or(_T_869.bits.resp, _T_979) @[Fragmenter.scala 232:34] + node _T_981 = and(_T_869.ready, _T_869.valid) @[Decoupled.scala 30:37] + when _T_981 : @[Fragmenter.scala 233:27] + node _T_983 = mux(AXI4FragmenterAXI4FragmenterSideband_1.io.deq.bits, UInt<1>("h00"), _T_980) @[Fragmenter.scala 233:42] + _T_979 <= _T_983 @[Fragmenter.scala 233:36] + skip @[Fragmenter.scala 233:27] + io.in.0.b.bits.resp <= _T_980 @[Fragmenter.scala 234:22] - module Mul54 : - input clk : Clock + module Queue_56 : + input clock : Clock input reset : UInt<1> - output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} io is invalid - reg val_s1 : UInt<1>, clk - reg val_s2 : UInt<1>, clk - reg reg_a_s1 : UInt<54>, clk - reg reg_b_s1 : UInt<54>, clk - reg reg_a_s2 : UInt<54>, clk - reg reg_b_s2 : UInt<54>, clk - reg reg_result_s3 : UInt<105>, clk - val_s1 <= io.val_s0 - val_s2 <= val_s1 - when io.val_s0 : - when io.latch_a_s0 : - reg_a_s1 <= io.a_s0 - skip - when io.latch_b_s0 : - reg_b_s1 <= io.b_s0 - skip - skip - when val_s1 : - reg_a_s2 <= reg_a_s1 - reg_b_s2 <= reg_b_s1 - skip - when val_s2 : - node T_25 = mul(reg_a_s2, reg_b_s2) - node T_26 = bits(T_25, 104, 0) - node T_27 = add(T_26, io.c_s2) - node T_28 = tail(T_27, 1) - reg_result_s3 <= T_28 - skip - io.result_s3 <= reg_result_s3 + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] - module DivSqrtRecF64 : - input clk : Clock + module Queue_57 : + input clock : Clock input reset : UInt<1> - output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, count : UInt<2>} io is invalid - inst ds of DivSqrtRecF64_mulAddZ31 - ds.io is invalid - ds.clk <= clk - ds.reset <= reset - io.inReady_div <= ds.io.inReady_div - io.inReady_sqrt <= ds.io.inReady_sqrt - ds.io.inValid <= io.inValid - ds.io.sqrtOp <= io.sqrtOp - ds.io.a <= io.a - ds.io.b <= io.b - ds.io.roundingMode <= io.roundingMode - io.outValid_div <= ds.io.outValid_div - io.outValid_sqrt <= ds.io.outValid_sqrt - io.out <= ds.io.out - io.exceptionFlags <= ds.io.exceptionFlags - inst mul of Mul54 - mul.io is invalid - mul.clk <= clk - mul.reset <= reset - node T_17 = bits(ds.io.usingMulAdd, 0, 0) - mul.io.val_s0 <= T_17 - mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 - mul.io.a_s0 <= ds.io.mulAddA_0 - mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 - mul.io.b_s0 <= ds.io.mulAddB_0 - mul.io.c_s2 <= ds.io.mulAddC_2 - ds.io.mulAddResult_3 <= mul.io.result_s3 + io is invalid + cmem ram : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_50 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_52 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_53 = and(_T_50, _T_52) @[Decoupled.scala 188:33] + node _T_54 = and(_T_50, maybe_full) @[Decoupled.scala 189:32] + node _T_55 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_55 + node _T_56 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_56 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_57 = ram[value], clock + _T_57 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_63 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_64 = tail(_T_63, 1) @[Counter.scala 26:22] + value <= _T_64 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_67 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_68 = tail(_T_67, 1) @[Counter.scala 26:22] + value_1 <= _T_68 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_69 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_69 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_71 = eq(_T_53, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_71 @[Decoupled.scala 204:16] + node _T_73 = eq(_T_54, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_73 @[Decoupled.scala 205:16] + infer mport _T_74 = ram[value_1], clock + io.deq.bits <- _T_74 @[Decoupled.scala 206:15] + node _T_78 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_79 = asUInt(_T_78) @[Decoupled.scala 221:40] + node _T_80 = tail(_T_79, 1) @[Decoupled.scala 221:40] + node _T_81 = and(maybe_full, _T_50) @[Decoupled.scala 223:32] + node _T_82 = cat(_T_81, _T_80) @[Cat.scala 30:58] + io.count <= _T_82 @[Decoupled.scala 223:14] - module FPU : - input clk : Clock + module Queue_58 : + input clock : Clock input reset : UInt<1> - output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, count : UInt<2>} io is invalid - reg ex_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - ex_reg_valid <= io.valid - node req_valid = or(ex_reg_valid, io.cp_req.valid) - reg ex_reg_inst : UInt<32>, clk - when io.valid : - ex_reg_inst <= io.inst - skip - node T_202 = eq(ex_reg_valid, UInt<1>("h00")) - node ex_cp_valid = and(io.cp_req.valid, T_202) - node T_205 = eq(io.killx, UInt<1>("h00")) - node T_206 = and(ex_reg_valid, T_205) - node T_207 = or(T_206, ex_cp_valid) - reg mem_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - mem_reg_valid <= T_207 - reg mem_reg_inst : UInt<32>, clk - when ex_reg_valid : - mem_reg_inst <= ex_reg_inst - skip - reg mem_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - mem_cp_valid <= ex_cp_valid - node T_213 = or(io.killm, io.nack_mem) - node T_215 = eq(mem_cp_valid, UInt<1>("h00")) - node killm = and(T_213, T_215) - node T_218 = eq(killm, UInt<1>("h00")) - node T_219 = or(T_218, mem_cp_valid) - node T_220 = and(mem_reg_valid, T_219) - reg wb_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wb_reg_valid <= T_220 - reg wb_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wb_cp_valid <= mem_cp_valid - inst fp_decoder of FPUDecoder - fp_decoder.io is invalid - fp_decoder.clk <= clk - fp_decoder.reset <= reset - fp_decoder.io.inst <= io.inst - wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - cp_ctrl is invalid - cp_ctrl <- io.cp_req.bits - io.cp_resp.valid <= UInt<1>("h00") - io.cp_resp.bits.data <= UInt<1>("h00") - reg T_264 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when io.valid : - T_264 <- fp_decoder.io.sigs - skip - node ex_ctrl = mux(ex_reg_valid, T_264, cp_ctrl) - reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when req_valid : - mem_ctrl <- ex_ctrl - skip - reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when mem_reg_valid : - wb_ctrl <- mem_ctrl - skip - reg load_wb : UInt<1>, clk - load_wb <= io.dmem_resp_val - node T_337 = eq(io.dmem_resp_type, UInt<3>("h02")) - node T_338 = eq(io.dmem_resp_type, UInt<3>("h06")) - node T_339 = or(T_337, T_338) - reg load_wb_single : UInt<1>, clk - when io.dmem_resp_val : - load_wb_single <= T_339 - skip - reg load_wb_data : UInt<64>, clk - when io.dmem_resp_val : - load_wb_data <= io.dmem_resp_data - skip - reg load_wb_tag : UInt<5>, clk - when io.dmem_resp_val : - load_wb_tag <= io.dmem_resp_tag - skip - node T_343 = bits(load_wb_data, 31, 31) - node T_344 = bits(load_wb_data, 30, 23) - node T_345 = bits(load_wb_data, 22, 0) - node T_347 = eq(T_344, UInt<1>("h00")) - node T_349 = eq(T_345, UInt<1>("h00")) - node T_350 = and(T_347, T_349) - node T_351 = shl(T_345, 9) - node T_352 = bits(T_351, 31, 31) - node T_354 = bits(T_351, 30, 30) - node T_356 = bits(T_351, 29, 29) - node T_358 = bits(T_351, 28, 28) - node T_360 = bits(T_351, 27, 27) - node T_362 = bits(T_351, 26, 26) - node T_364 = bits(T_351, 25, 25) - node T_366 = bits(T_351, 24, 24) - node T_368 = bits(T_351, 23, 23) - node T_370 = bits(T_351, 22, 22) - node T_372 = bits(T_351, 21, 21) - node T_374 = bits(T_351, 20, 20) - node T_376 = bits(T_351, 19, 19) - node T_378 = bits(T_351, 18, 18) - node T_380 = bits(T_351, 17, 17) - node T_382 = bits(T_351, 16, 16) - node T_384 = bits(T_351, 15, 15) - node T_386 = bits(T_351, 14, 14) - node T_388 = bits(T_351, 13, 13) - node T_390 = bits(T_351, 12, 12) - node T_392 = bits(T_351, 11, 11) - node T_394 = bits(T_351, 10, 10) - node T_396 = bits(T_351, 9, 9) - node T_398 = bits(T_351, 8, 8) - node T_400 = bits(T_351, 7, 7) - node T_402 = bits(T_351, 6, 6) - node T_404 = bits(T_351, 5, 5) - node T_406 = bits(T_351, 4, 4) - node T_408 = bits(T_351, 3, 3) - node T_410 = bits(T_351, 2, 2) - node T_412 = bits(T_351, 1, 1) - node T_413 = shl(T_412, 0) - node T_414 = mux(T_410, UInt<2>("h02"), T_413) - node T_415 = mux(T_408, UInt<2>("h03"), T_414) - node T_416 = mux(T_406, UInt<3>("h04"), T_415) - node T_417 = mux(T_404, UInt<3>("h05"), T_416) - node T_418 = mux(T_402, UInt<3>("h06"), T_417) - node T_419 = mux(T_400, UInt<3>("h07"), T_418) - node T_420 = mux(T_398, UInt<4>("h08"), T_419) - node T_421 = mux(T_396, UInt<4>("h09"), T_420) - node T_422 = mux(T_394, UInt<4>("h0a"), T_421) - node T_423 = mux(T_392, UInt<4>("h0b"), T_422) - node T_424 = mux(T_390, UInt<4>("h0c"), T_423) - node T_425 = mux(T_388, UInt<4>("h0d"), T_424) - node T_426 = mux(T_386, UInt<4>("h0e"), T_425) - node T_427 = mux(T_384, UInt<4>("h0f"), T_426) - node T_428 = mux(T_382, UInt<5>("h010"), T_427) - node T_429 = mux(T_380, UInt<5>("h011"), T_428) - node T_430 = mux(T_378, UInt<5>("h012"), T_429) - node T_431 = mux(T_376, UInt<5>("h013"), T_430) - node T_432 = mux(T_374, UInt<5>("h014"), T_431) - node T_433 = mux(T_372, UInt<5>("h015"), T_432) - node T_434 = mux(T_370, UInt<5>("h016"), T_433) - node T_435 = mux(T_368, UInt<5>("h017"), T_434) - node T_436 = mux(T_366, UInt<5>("h018"), T_435) - node T_437 = mux(T_364, UInt<5>("h019"), T_436) - node T_438 = mux(T_362, UInt<5>("h01a"), T_437) - node T_439 = mux(T_360, UInt<5>("h01b"), T_438) - node T_440 = mux(T_358, UInt<5>("h01c"), T_439) - node T_441 = mux(T_356, UInt<5>("h01d"), T_440) - node T_442 = mux(T_354, UInt<5>("h01e"), T_441) - node T_443 = mux(T_352, UInt<5>("h01f"), T_442) - node T_444 = not(T_443) - node T_445 = dshl(T_345, T_444) - node T_446 = bits(T_445, 21, 0) - node T_448 = cat(T_446, UInt<1>("h00")) - node T_451 = sub(UInt<9>("h00"), UInt<1>("h01")) - node T_452 = tail(T_451, 1) - node T_453 = xor(T_444, T_452) - node T_454 = mux(T_347, T_453, T_344) - node T_458 = mux(T_347, UInt<2>("h02"), UInt<1>("h01")) - node T_459 = or(UInt<8>("h080"), T_458) - node T_460 = add(T_454, T_459) - node T_461 = tail(T_460, 1) - node T_462 = bits(T_461, 8, 7) - node T_464 = eq(T_462, UInt<2>("h03")) - node T_466 = eq(T_349, UInt<1>("h00")) - node T_467 = and(T_464, T_466) - node T_469 = sub(UInt<3>("h00"), T_350) - node T_470 = tail(T_469, 1) - node T_471 = shl(T_470, 6) - node T_472 = not(T_471) - node T_473 = and(T_461, T_472) - node T_474 = shl(T_467, 6) - node T_475 = or(T_473, T_474) - node T_476 = mux(T_347, T_448, T_345) - node T_477 = cat(T_475, T_476) - node rec_s = cat(T_343, T_477) - node T_479 = bits(load_wb_data, 63, 63) - node T_480 = bits(load_wb_data, 62, 52) - node T_481 = bits(load_wb_data, 51, 0) - node T_483 = eq(T_480, UInt<1>("h00")) - node T_485 = eq(T_481, UInt<1>("h00")) - node T_486 = and(T_483, T_485) - node T_487 = shl(T_481, 12) - node T_488 = bits(T_487, 63, 63) - node T_490 = bits(T_487, 62, 62) - node T_492 = bits(T_487, 61, 61) - node T_494 = bits(T_487, 60, 60) - node T_496 = bits(T_487, 59, 59) - node T_498 = bits(T_487, 58, 58) - node T_500 = bits(T_487, 57, 57) - node T_502 = bits(T_487, 56, 56) - node T_504 = bits(T_487, 55, 55) - node T_506 = bits(T_487, 54, 54) - node T_508 = bits(T_487, 53, 53) - node T_510 = bits(T_487, 52, 52) - node T_512 = bits(T_487, 51, 51) - node T_514 = bits(T_487, 50, 50) - node T_516 = bits(T_487, 49, 49) - node T_518 = bits(T_487, 48, 48) - node T_520 = bits(T_487, 47, 47) - node T_522 = bits(T_487, 46, 46) - node T_524 = bits(T_487, 45, 45) - node T_526 = bits(T_487, 44, 44) - node T_528 = bits(T_487, 43, 43) - node T_530 = bits(T_487, 42, 42) - node T_532 = bits(T_487, 41, 41) - node T_534 = bits(T_487, 40, 40) - node T_536 = bits(T_487, 39, 39) - node T_538 = bits(T_487, 38, 38) - node T_540 = bits(T_487, 37, 37) - node T_542 = bits(T_487, 36, 36) - node T_544 = bits(T_487, 35, 35) - node T_546 = bits(T_487, 34, 34) - node T_548 = bits(T_487, 33, 33) - node T_550 = bits(T_487, 32, 32) - node T_552 = bits(T_487, 31, 31) - node T_554 = bits(T_487, 30, 30) - node T_556 = bits(T_487, 29, 29) - node T_558 = bits(T_487, 28, 28) - node T_560 = bits(T_487, 27, 27) - node T_562 = bits(T_487, 26, 26) - node T_564 = bits(T_487, 25, 25) - node T_566 = bits(T_487, 24, 24) - node T_568 = bits(T_487, 23, 23) - node T_570 = bits(T_487, 22, 22) - node T_572 = bits(T_487, 21, 21) - node T_574 = bits(T_487, 20, 20) - node T_576 = bits(T_487, 19, 19) - node T_578 = bits(T_487, 18, 18) - node T_580 = bits(T_487, 17, 17) - node T_582 = bits(T_487, 16, 16) - node T_584 = bits(T_487, 15, 15) - node T_586 = bits(T_487, 14, 14) - node T_588 = bits(T_487, 13, 13) - node T_590 = bits(T_487, 12, 12) - node T_592 = bits(T_487, 11, 11) - node T_594 = bits(T_487, 10, 10) - node T_596 = bits(T_487, 9, 9) - node T_598 = bits(T_487, 8, 8) - node T_600 = bits(T_487, 7, 7) - node T_602 = bits(T_487, 6, 6) - node T_604 = bits(T_487, 5, 5) - node T_606 = bits(T_487, 4, 4) - node T_608 = bits(T_487, 3, 3) - node T_610 = bits(T_487, 2, 2) - node T_612 = bits(T_487, 1, 1) - node T_613 = shl(T_612, 0) - node T_614 = mux(T_610, UInt<2>("h02"), T_613) - node T_615 = mux(T_608, UInt<2>("h03"), T_614) - node T_616 = mux(T_606, UInt<3>("h04"), T_615) - node T_617 = mux(T_604, UInt<3>("h05"), T_616) - node T_618 = mux(T_602, UInt<3>("h06"), T_617) - node T_619 = mux(T_600, UInt<3>("h07"), T_618) - node T_620 = mux(T_598, UInt<4>("h08"), T_619) - node T_621 = mux(T_596, UInt<4>("h09"), T_620) - node T_622 = mux(T_594, UInt<4>("h0a"), T_621) - node T_623 = mux(T_592, UInt<4>("h0b"), T_622) - node T_624 = mux(T_590, UInt<4>("h0c"), T_623) - node T_625 = mux(T_588, UInt<4>("h0d"), T_624) - node T_626 = mux(T_586, UInt<4>("h0e"), T_625) - node T_627 = mux(T_584, UInt<4>("h0f"), T_626) - node T_628 = mux(T_582, UInt<5>("h010"), T_627) - node T_629 = mux(T_580, UInt<5>("h011"), T_628) - node T_630 = mux(T_578, UInt<5>("h012"), T_629) - node T_631 = mux(T_576, UInt<5>("h013"), T_630) - node T_632 = mux(T_574, UInt<5>("h014"), T_631) - node T_633 = mux(T_572, UInt<5>("h015"), T_632) - node T_634 = mux(T_570, UInt<5>("h016"), T_633) - node T_635 = mux(T_568, UInt<5>("h017"), T_634) - node T_636 = mux(T_566, UInt<5>("h018"), T_635) - node T_637 = mux(T_564, UInt<5>("h019"), T_636) - node T_638 = mux(T_562, UInt<5>("h01a"), T_637) - node T_639 = mux(T_560, UInt<5>("h01b"), T_638) - node T_640 = mux(T_558, UInt<5>("h01c"), T_639) - node T_641 = mux(T_556, UInt<5>("h01d"), T_640) - node T_642 = mux(T_554, UInt<5>("h01e"), T_641) - node T_643 = mux(T_552, UInt<5>("h01f"), T_642) - node T_644 = mux(T_550, UInt<6>("h020"), T_643) - node T_645 = mux(T_548, UInt<6>("h021"), T_644) - node T_646 = mux(T_546, UInt<6>("h022"), T_645) - node T_647 = mux(T_544, UInt<6>("h023"), T_646) - node T_648 = mux(T_542, UInt<6>("h024"), T_647) - node T_649 = mux(T_540, UInt<6>("h025"), T_648) - node T_650 = mux(T_538, UInt<6>("h026"), T_649) - node T_651 = mux(T_536, UInt<6>("h027"), T_650) - node T_652 = mux(T_534, UInt<6>("h028"), T_651) - node T_653 = mux(T_532, UInt<6>("h029"), T_652) - node T_654 = mux(T_530, UInt<6>("h02a"), T_653) - node T_655 = mux(T_528, UInt<6>("h02b"), T_654) - node T_656 = mux(T_526, UInt<6>("h02c"), T_655) - node T_657 = mux(T_524, UInt<6>("h02d"), T_656) - node T_658 = mux(T_522, UInt<6>("h02e"), T_657) - node T_659 = mux(T_520, UInt<6>("h02f"), T_658) - node T_660 = mux(T_518, UInt<6>("h030"), T_659) - node T_661 = mux(T_516, UInt<6>("h031"), T_660) - node T_662 = mux(T_514, UInt<6>("h032"), T_661) - node T_663 = mux(T_512, UInt<6>("h033"), T_662) - node T_664 = mux(T_510, UInt<6>("h034"), T_663) - node T_665 = mux(T_508, UInt<6>("h035"), T_664) - node T_666 = mux(T_506, UInt<6>("h036"), T_665) - node T_667 = mux(T_504, UInt<6>("h037"), T_666) - node T_668 = mux(T_502, UInt<6>("h038"), T_667) - node T_669 = mux(T_500, UInt<6>("h039"), T_668) - node T_670 = mux(T_498, UInt<6>("h03a"), T_669) - node T_671 = mux(T_496, UInt<6>("h03b"), T_670) - node T_672 = mux(T_494, UInt<6>("h03c"), T_671) - node T_673 = mux(T_492, UInt<6>("h03d"), T_672) - node T_674 = mux(T_490, UInt<6>("h03e"), T_673) - node T_675 = mux(T_488, UInt<6>("h03f"), T_674) - node T_676 = not(T_675) - node T_677 = dshl(T_481, T_676) - node T_678 = bits(T_677, 50, 0) - node T_680 = cat(T_678, UInt<1>("h00")) - node T_683 = sub(UInt<12>("h00"), UInt<1>("h01")) - node T_684 = tail(T_683, 1) - node T_685 = xor(T_676, T_684) - node T_686 = mux(T_483, T_685, T_480) - node T_690 = mux(T_483, UInt<2>("h02"), UInt<1>("h01")) - node T_691 = or(UInt<11>("h0400"), T_690) - node T_692 = add(T_686, T_691) - node T_693 = tail(T_692, 1) - node T_694 = bits(T_693, 11, 10) - node T_696 = eq(T_694, UInt<2>("h03")) - node T_698 = eq(T_485, UInt<1>("h00")) - node T_699 = and(T_696, T_698) - node T_701 = sub(UInt<3>("h00"), T_486) - node T_702 = tail(T_701, 1) - node T_703 = shl(T_702, 9) - node T_704 = not(T_703) - node T_705 = and(T_693, T_704) - node T_706 = shl(T_699, 9) - node T_707 = or(T_705, T_706) - node T_708 = mux(T_483, T_680, T_481) - node T_709 = cat(T_707, T_708) - node rec_d = cat(T_479, T_709) - node T_712 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_713 = cat(T_712, rec_s) - node load_wb_data_recoded = mux(load_wb_single, T_713, rec_d) - cmem regfile : UInt<65>[32] - when load_wb : - infer mport T_718 = regfile[load_wb_tag], clk - T_718 <= load_wb_data_recoded - skip - reg ex_ra1 : UInt, clk - reg ex_ra2 : UInt, clk - reg ex_ra3 : UInt, clk - when io.valid : - when fp_decoder.io.sigs.ren1 : - node T_726 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) - when T_726 : - node T_727 = bits(io.inst, 19, 15) - ex_ra1 <= T_727 - skip - when fp_decoder.io.sigs.swap12 : - node T_728 = bits(io.inst, 19, 15) - ex_ra2 <= T_728 - skip - skip - when fp_decoder.io.sigs.ren2 : - when fp_decoder.io.sigs.swap12 : - node T_729 = bits(io.inst, 24, 20) - ex_ra1 <= T_729 - skip - when fp_decoder.io.sigs.swap23 : - node T_730 = bits(io.inst, 24, 20) - ex_ra3 <= T_730 - skip - node T_732 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) - node T_734 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) - node T_735 = and(T_732, T_734) - when T_735 : - node T_736 = bits(io.inst, 24, 20) - ex_ra2 <= T_736 - skip - skip - when fp_decoder.io.sigs.ren3 : - node T_737 = bits(io.inst, 31, 27) - ex_ra3 <= T_737 - skip - skip - infer mport ex_rs1 = regfile[ex_ra1], clk - infer mport ex_rs2 = regfile[ex_ra2], clk - infer mport ex_rs3 = regfile[ex_ra3], clk - node T_741 = bits(ex_reg_inst, 14, 12) - node T_743 = eq(T_741, UInt<3>("h07")) - node T_744 = bits(ex_reg_inst, 14, 12) - node ex_rm = mux(T_743, io.fcsr_rm, T_744) - node cp_rs2 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in3, io.cp_req.bits.in2) - node cp_rs3 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in2, io.cp_req.bits.in3) - wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} - req is invalid - req <- ex_ctrl - node T_794 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm) - req.rm <= T_794 - node T_795 = mux(ex_reg_valid, ex_rs1, io.cp_req.bits.in1) - req.in1 <= T_795 - node T_796 = mux(ex_reg_valid, ex_rs2, cp_rs2) - req.in2 <= T_796 - node T_797 = mux(ex_reg_valid, ex_rs3, cp_rs3) - req.in3 <= T_797 - node T_798 = bits(ex_reg_inst, 21, 20) - node T_799 = mux(ex_reg_valid, T_798, io.cp_req.bits.typ) - req.typ <= T_799 - inst sfma of FPUFMAPipe - sfma.io is invalid - sfma.clk <= clk - sfma.reset <= reset - node T_801 = and(req_valid, ex_ctrl.fma) - node T_802 = and(T_801, ex_ctrl.single) - sfma.io.in.valid <= T_802 - sfma.io.in.bits <- req - inst dfma of FPUFMAPipe_113 - dfma.io is invalid - dfma.clk <= clk - dfma.reset <= reset - node T_804 = and(req_valid, ex_ctrl.fma) - node T_806 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_807 = and(T_804, T_806) - dfma.io.in.valid <= T_807 - dfma.io.in.bits <- req - inst fpiu of FPToInt - fpiu.io is invalid - fpiu.clk <= clk - fpiu.reset <= reset - node T_809 = or(ex_ctrl.toint, ex_ctrl.div) - node T_810 = or(T_809, ex_ctrl.sqrt) - node T_813 = and(ex_ctrl.cmd, UInt<4>("h0d")) - node T_814 = eq(UInt<3>("h05"), T_813) - node T_815 = or(T_810, T_814) - node T_816 = and(req_valid, T_815) - fpiu.io.in.valid <= T_816 - fpiu.io.in.bits <- req - io.store_data <= fpiu.io.out.bits.store - io.toint_data <= fpiu.io.out.bits.toint - node T_817 = and(fpiu.io.out.valid, mem_cp_valid) - node T_818 = and(T_817, mem_ctrl.toint) - when T_818 : - io.cp_resp.bits.data <= fpiu.io.out.bits.toint - io.cp_resp.valid <= UInt<1>("h01") - skip - inst ifpu of IntToFP - ifpu.io is invalid - ifpu.clk <= clk - ifpu.reset <= reset - node T_821 = and(req_valid, ex_ctrl.fromint) - ifpu.io.in.valid <= T_821 - ifpu.io.in.bits <- req - node T_822 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1) - ifpu.io.in.bits.in1 <= T_822 - inst fpmu of FPToFP - fpmu.io is invalid - fpmu.clk <= clk - fpmu.reset <= reset - node T_824 = and(req_valid, ex_ctrl.fastpipe) - fpmu.io.in.valid <= T_824 - fpmu.io.in.bits <- req - fpmu.io.lt <= fpiu.io.out.bits.lt - reg divSqrt_wen : UInt<1>, clk - divSqrt_wen <= UInt<1>("h00") - wire divSqrt_inReady : UInt<1> - divSqrt_inReady <= UInt<1>("h00") - reg divSqrt_waddr : UInt, clk - wire divSqrt_wdata : UInt - divSqrt_wdata is invalid - wire divSqrt_flags : UInt - divSqrt_flags is invalid - reg divSqrt_in_flight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg divSqrt_killed : UInt<1>, clk - node T_841 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) - node T_844 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) - node T_845 = and(mem_ctrl.fma, mem_ctrl.single) - node T_848 = mux(T_845, UInt<1>("h01"), UInt<1>("h00")) - node T_850 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_851 = and(mem_ctrl.fma, T_850) - node T_854 = mux(T_851, UInt<2>("h02"), UInt<1>("h00")) - node T_855 = or(T_841, T_844) - node T_856 = or(T_855, T_848) - node memLatencyMask = or(T_856, T_854) - reg wen : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg winfo : UInt[2], clk - node T_872 = or(mem_ctrl.fma, mem_ctrl.fastpipe) - node T_873 = or(T_872, mem_ctrl.fromint) - node mem_wen = and(mem_reg_valid, T_873) - node T_877 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) - node T_880 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) - node T_881 = and(ex_ctrl.fma, ex_ctrl.single) - node T_884 = mux(T_881, UInt<2>("h02"), UInt<1>("h00")) - node T_886 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_887 = and(ex_ctrl.fma, T_886) - node T_890 = mux(T_887, UInt<3>("h04"), UInt<1>("h00")) - node T_891 = or(T_877, T_880) - node T_892 = or(T_891, T_884) - node T_893 = or(T_892, T_890) - node T_894 = and(memLatencyMask, T_893) - node T_896 = neq(T_894, UInt<1>("h00")) - node T_897 = and(mem_wen, T_896) - node T_900 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) - node T_903 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) - node T_904 = and(ex_ctrl.fma, ex_ctrl.single) - node T_907 = mux(T_904, UInt<3>("h04"), UInt<1>("h00")) - node T_909 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_910 = and(ex_ctrl.fma, T_909) - node T_913 = mux(T_910, UInt<4>("h08"), UInt<1>("h00")) - node T_914 = or(T_900, T_903) - node T_915 = or(T_914, T_907) - node T_916 = or(T_915, T_913) - node T_917 = and(wen, T_916) - node T_919 = neq(T_917, UInt<1>("h00")) - node T_920 = or(T_897, T_919) - reg write_port_busy : UInt<1>, clk - when req_valid : - write_port_busy <= T_920 - skip - node T_924 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) - node T_927 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) - node T_928 = and(mem_ctrl.fma, mem_ctrl.single) - node T_931 = mux(T_928, UInt<2>("h02"), UInt<1>("h00")) - node T_933 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_934 = and(mem_ctrl.fma, T_933) - node T_937 = mux(T_934, UInt<2>("h03"), UInt<1>("h00")) - node T_938 = or(T_924, T_927) - node T_939 = or(T_938, T_931) - node T_940 = or(T_939, T_937) - node T_941 = bits(mem_reg_inst, 11, 7) - node T_942 = cat(mem_cp_valid, T_940) - node T_943 = cat(mem_ctrl.single, T_941) - node mem_winfo = cat(T_942, T_943) - node T_945 = bits(wen, 1, 1) - when T_945 : - winfo[0] <= winfo[1] - skip - node T_946 = shr(wen, 1) - wen <= T_946 - when mem_wen : - node T_948 = eq(killm, UInt<1>("h00")) - when T_948 : - node T_949 = shr(wen, 1) - node T_950 = or(T_949, memLatencyMask) - wen <= T_950 - skip - node T_952 = eq(write_port_busy, UInt<1>("h00")) - node T_953 = bits(memLatencyMask, 0, 0) - node T_954 = and(T_952, T_953) - when T_954 : - winfo[0] <= mem_winfo - skip - node T_956 = eq(write_port_busy, UInt<1>("h00")) - node T_957 = bits(memLatencyMask, 1, 1) - node T_958 = and(T_956, T_957) - when T_958 : - winfo[1] <= mem_winfo - skip - skip - node T_959 = bits(winfo[0], 4, 0) - node waddr = mux(divSqrt_wen, divSqrt_waddr, T_959) - node wsrc = shr(winfo[0], 6) - node wcp = bits(winfo[0], 8, 8) - wire T_964 : UInt<65>[4] - T_964[0] <= fpmu.io.out.bits.data - T_964[1] <= ifpu.io.out.bits.data - T_964[2] <= sfma.io.out.bits.data - T_964[3] <= dfma.io.out.bits.data - node wdata = mux(divSqrt_wen, divSqrt_wdata, T_964[wsrc]) - wire T_973 : UInt<5>[4] - T_973[0] <= fpmu.io.out.bits.exc - T_973[1] <= ifpu.io.out.bits.exc - T_973[2] <= sfma.io.out.bits.exc - T_973[3] <= dfma.io.out.bits.exc - node T_981 = eq(wcp, UInt<1>("h00")) - node T_982 = bits(wen, 0, 0) - node T_983 = and(T_981, T_982) - node T_984 = or(T_983, divSqrt_wen) - when T_984 : - infer mport T_985 = regfile[waddr], clk - T_985 <= wdata - skip - node T_986 = bits(wen, 0, 0) - node T_987 = and(wcp, T_986) - when T_987 : - io.cp_resp.bits.data <= wdata - io.cp_resp.valid <= UInt<1>("h01") - skip - node T_990 = eq(ex_reg_valid, UInt<1>("h00")) - io.cp_req.ready <= T_990 - node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) - reg wb_toint_exc : UInt<5>, clk - when mem_ctrl.toint : - wb_toint_exc <= fpiu.io.out.bits.exc - skip - node T_993 = or(wb_toint_valid, divSqrt_wen) - node T_994 = bits(wen, 0, 0) - node T_995 = or(T_993, T_994) - io.fcsr_flags.valid <= T_995 - node T_997 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) - node T_999 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) - node T_1000 = or(T_997, T_999) - node T_1001 = bits(wen, 0, 0) - node T_1003 = mux(T_1001, T_973[wsrc], UInt<1>("h00")) - node T_1004 = or(T_1000, T_1003) - io.fcsr_flags.bits <= T_1004 - node T_1005 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1006 = and(mem_reg_valid, T_1005) - node T_1008 = eq(divSqrt_inReady, UInt<1>("h00")) - node T_1010 = neq(wen, UInt<1>("h00")) - node T_1011 = or(T_1008, T_1010) - node units_busy = and(T_1006, T_1011) - node T_1013 = and(ex_reg_valid, ex_ctrl.wflags) - node T_1014 = and(mem_reg_valid, mem_ctrl.wflags) - node T_1015 = or(T_1013, T_1014) - node T_1016 = and(wb_reg_valid, wb_ctrl.toint) - node T_1017 = or(T_1015, T_1016) - node T_1019 = neq(wen, UInt<1>("h00")) - node T_1020 = or(T_1017, T_1019) - node T_1021 = or(T_1020, divSqrt_in_flight) - node T_1023 = eq(T_1021, UInt<1>("h00")) - io.fcsr_rdy <= T_1023 - node T_1024 = or(units_busy, write_port_busy) - node T_1025 = or(T_1024, divSqrt_in_flight) - io.nack_mem <= T_1025 - io.dec <- fp_decoder.io.sigs - node T_1027 = eq(wb_cp_valid, UInt<1>("h00")) - node T_1028 = and(wb_reg_valid, T_1027) - node T_1030 = or(UInt<1>("h00"), mem_ctrl.div) - node T_1031 = or(T_1030, mem_ctrl.sqrt) - reg T_1032 : UInt<1>, clk - T_1032 <= T_1031 - node T_1033 = and(T_1028, T_1032) - io.sboard_set <= T_1033 - node T_1035 = eq(wb_cp_valid, UInt<1>("h00")) - node T_1036 = bits(wen, 0, 0) - node T_1038 = and(T_1036, UInt<1>("h00")) - node T_1039 = or(divSqrt_wen, T_1038) - node T_1040 = and(T_1035, T_1039) - io.sboard_clr <= T_1040 - io.sboard_clra <= waddr - node T_1041 = bits(ex_rm, 2, 2) - node T_1042 = and(T_1041, ex_ctrl.round) - io.illegal_rm <= T_1042 - divSqrt_wdata <= UInt<1>("h00") - divSqrt_flags <= UInt<1>("h00") - reg T_1046 : UInt<1>, clk - reg T_1048 : UInt, clk - reg T_1050 : UInt, clk - reg T_1052 : UInt, clk - inst T_1053 of DivSqrtRecF64 - T_1053.io is invalid - T_1053.clk <= clk - T_1053.reset <= reset - node T_1054 = mux(T_1053.io.sqrtOp, T_1053.io.inReady_sqrt, T_1053.io.inReady_div) - divSqrt_inReady <= T_1054 - node T_1055 = or(T_1053.io.outValid_div, T_1053.io.outValid_sqrt) - node T_1056 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1057 = and(mem_reg_valid, T_1056) - node T_1059 = eq(divSqrt_in_flight, UInt<1>("h00")) - node T_1060 = and(T_1057, T_1059) - T_1053.io.inValid <= T_1060 - T_1053.io.sqrtOp <= mem_ctrl.sqrt - T_1053.io.a <= fpiu.io.as_double.in1 - T_1053.io.b <= fpiu.io.as_double.in2 - T_1053.io.roundingMode <= fpiu.io.as_double.rm - node T_1061 = and(T_1053.io.inValid, divSqrt_inReady) - when T_1061 : - divSqrt_in_flight <= UInt<1>("h01") - divSqrt_killed <= killm - T_1046 <= mem_ctrl.single - node T_1063 = bits(mem_reg_inst, 11, 7) - divSqrt_waddr <= T_1063 - T_1048 <= T_1053.io.roundingMode - skip - when T_1055 : - node T_1065 = eq(divSqrt_killed, UInt<1>("h00")) - divSqrt_wen <= T_1065 - T_1052 <= T_1053.io.out - divSqrt_in_flight <= UInt<1>("h00") - T_1050 <= T_1053.io.exceptionFlags - skip - inst T_1067 of RecFNToRecFN_121 - T_1067.io is invalid - T_1067.clk <= clk - T_1067.reset <= reset - T_1067.io.in <= T_1052 - T_1067.io.roundingMode <= ex_rm - node T_1068 = mux(T_1046, T_1067.io.out, T_1052) - divSqrt_wdata <= T_1068 - node T_1070 = mux(T_1046, T_1067.io.exceptionFlags, UInt<1>("h00")) - node T_1071 = or(T_1050, T_1070) - divSqrt_flags <= T_1071 + io is invalid + cmem ram : {id : UInt<4>, resp : UInt<2>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_43 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_45 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_46 = and(_T_43, _T_45) @[Decoupled.scala 188:33] + node _T_47 = and(_T_43, maybe_full) @[Decoupled.scala 189:32] + node _T_48 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_48 + node _T_49 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_49 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_50 = ram[value], clock + _T_50 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_55 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_56 = tail(_T_55, 1) @[Counter.scala 26:22] + value <= _T_56 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_59 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_60 = tail(_T_59, 1) @[Counter.scala 26:22] + value_1 <= _T_60 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_61 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_61 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_63 = eq(_T_46, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_63 @[Decoupled.scala 204:16] + node _T_65 = eq(_T_47, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_65 @[Decoupled.scala 205:16] + infer mport _T_66 = ram[value_1], clock + io.deq.bits <- _T_66 @[Decoupled.scala 206:15] + node _T_69 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_70 = asUInt(_T_69) @[Decoupled.scala 221:40] + node _T_71 = tail(_T_70, 1) @[Decoupled.scala 221:40] + node _T_72 = and(maybe_full, _T_43) @[Decoupled.scala 223:32] + node _T_73 = cat(_T_72, _T_71) @[Cat.scala 30:58] + io.count <= _T_73 @[Decoupled.scala 223:14] - module RocketTile : - input clk : Clock + module Queue_59 : + input clock : Clock input reset : UInt<1> - output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, count : UInt<2>} io is invalid - inst core of Rocket - core.io is invalid - core.clk <= clk - core.reset <= reset - inst icache of Frontend - icache.io is invalid - icache.clk <= clk - icache.reset <= reset - inst dcache of HellaCache - dcache.io is invalid - dcache.clk <= clk - dcache.reset <= reset - inst ptw of PTW - ptw.io is invalid - ptw.clk <= clk - ptw.reset <= reset - dcache.io.cpu.invalidate_lr <= core.io.dmem.invalidate_lr - inst dcArb of HellaCacheArbiter - dcArb.io is invalid - dcArb.clk <= clk - dcArb.reset <= reset - dcArb.io.requestor[0] <- ptw.io.mem - dcArb.io.requestor[1] <- core.io.dmem - dcache.io.cpu <- dcArb.io.mem - ptw.io.requestor[0] <- icache.io.ptw - ptw.io.requestor[1] <- dcache.io.ptw - io.host <- core.io.host - icache.io.cpu <- core.io.imem - core.io.ptw <- ptw.io.dpath - inst T_3284 of FPU - T_3284.io is invalid - T_3284.clk <= clk - T_3284.reset <= reset - core.io.fpu <- T_3284.io - io.cached[0] <- dcache.io.mem - io.uncached[0] <- icache.io.mem - T_3284.io.cp_req.valid <= UInt<1>("h00") - T_3284.io.cp_resp.ready <= UInt<1>("h00") - io.dma.req.valid <= UInt<1>("h00") - io.dma.resp.ready <= UInt<1>("h00") - - module Queue_124 : - input clk : Clock + io is invalid + cmem ram : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_92 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_94 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_95 = and(_T_92, _T_94) @[Decoupled.scala 188:33] + node _T_96 = and(_T_92, maybe_full) @[Decoupled.scala 189:32] + node _T_97 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_97 + node _T_98 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_98 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_99 = ram[value], clock + _T_99 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_111 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_112 = tail(_T_111, 1) @[Counter.scala 26:22] + value <= _T_112 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_115 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_116 = tail(_T_115, 1) @[Counter.scala 26:22] + value_1 <= _T_116 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_117 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_117 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_119 = eq(_T_95, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_119 @[Decoupled.scala 204:16] + node _T_121 = eq(_T_96, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_121 @[Decoupled.scala 205:16] + infer mport _T_122 = ram[value_1], clock + io.deq.bits <- _T_122 @[Decoupled.scala 206:15] + node _T_132 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_133 = asUInt(_T_132) @[Decoupled.scala 221:40] + node _T_134 = tail(_T_133, 1) @[Decoupled.scala 221:40] + node _T_135 = and(maybe_full, _T_92) @[Decoupled.scala 223:32] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + io.count <= _T_136 @[Decoupled.scala 223:14] + + module Queue_60 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>} - - io is invalid - cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2] - reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_53, T_55) - node T_60 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_60) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_66 = and(io.enq.ready, io.enq.valid) - node T_68 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_66, T_68) - node T_70 = and(io.deq.ready, io.deq.valid) - node T_72 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_70, T_72) - when do_enq : - infer mport T_74 = ram[T_53], clk - T_74 <- io.enq.bits - node T_79 = eq(T_53, UInt<1>("h01")) - node T_81 = and(UInt<1>("h00"), T_79) - node T_84 = add(T_53, UInt<1>("h01")) - node T_85 = tail(T_84, 1) - node T_86 = mux(T_81, UInt<1>("h00"), T_85) - T_53 <= T_86 - skip - when do_deq : - node T_88 = eq(T_55, UInt<1>("h01")) - node T_90 = and(UInt<1>("h00"), T_88) - node T_93 = add(T_55, UInt<1>("h01")) - node T_94 = tail(T_93, 1) - node T_95 = mux(T_90, UInt<1>("h00"), T_94) - T_55 <= T_95 - skip - node T_96 = neq(do_enq, do_deq) - when T_96 : - maybe_full <= do_enq - skip - node T_98 = eq(empty, UInt<1>("h00")) - node T_100 = and(UInt<1>("h00"), io.enq.valid) - node T_101 = or(T_98, T_100) - io.deq.valid <= T_101 - node T_103 = eq(full, UInt<1>("h00")) - node T_105 = and(UInt<1>("h00"), io.deq.ready) - node T_106 = or(T_103, T_105) - io.enq.ready <= T_106 - infer mport T_107 = ram[T_55], clk - node T_111 = mux(maybe_flow, io.enq.bits, T_107) - io.deq.bits <- T_111 - node T_115 = sub(T_53, T_55) - node ptr_diff = tail(T_115, 1) - node T_117 = and(maybe_full, ptr_match) - node T_118 = cat(T_117, ptr_diff) - io.count <= T_118 - - module Queue_125 : - input clk : Clock + output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}, count : UInt<2>} + + io is invalid + io is invalid + cmem ram : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}[2] @[Decoupled.scala 182:24] + reg value : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg value_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 17:29] + reg maybe_full : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Decoupled.scala 185:31] + node _T_57 = eq(value, value_1) @[Decoupled.scala 187:41] + node _T_59 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 188:36] + node _T_60 = and(_T_57, _T_59) @[Decoupled.scala 188:33] + node _T_61 = and(_T_57, maybe_full) @[Decoupled.scala 189:32] + node _T_62 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 30:37] + wire do_enq : UInt<1> + do_enq is invalid + do_enq <= _T_62 + node _T_63 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 30:37] + wire do_deq : UInt<1> + do_deq is invalid + do_deq <= _T_63 + when do_enq : @[Decoupled.scala 193:17] + infer mport _T_64 = ram[value], clock + _T_64 <- io.enq.bits @[Decoupled.scala 194:24] + node wrap = eq(value, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_71 = add(value, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_72 = tail(_T_71, 1) @[Counter.scala 26:22] + value <= _T_72 @[Counter.scala 26:13] + skip @[Decoupled.scala 193:17] + when do_deq : @[Decoupled.scala 197:17] + node wrap_1 = eq(value_1, UInt<1>("h01")) @[Counter.scala 25:24] + node _T_75 = add(value_1, UInt<1>("h01")) @[Counter.scala 26:22] + node _T_76 = tail(_T_75, 1) @[Counter.scala 26:22] + value_1 <= _T_76 @[Counter.scala 26:13] + skip @[Decoupled.scala 197:17] + node _T_77 = neq(do_enq, do_deq) @[Decoupled.scala 200:16] + when _T_77 : @[Decoupled.scala 200:27] + maybe_full <= do_enq @[Decoupled.scala 201:16] + skip @[Decoupled.scala 200:27] + node _T_79 = eq(_T_60, UInt<1>("h00")) @[Decoupled.scala 204:19] + io.deq.valid <= _T_79 @[Decoupled.scala 204:16] + node _T_81 = eq(_T_61, UInt<1>("h00")) @[Decoupled.scala 205:19] + io.enq.ready <= _T_81 @[Decoupled.scala 205:16] + infer mport _T_82 = ram[value_1], clock + io.deq.bits <- _T_82 @[Decoupled.scala 206:15] + node _T_87 = sub(value, value_1) @[Decoupled.scala 221:40] + node _T_88 = asUInt(_T_87) @[Decoupled.scala 221:40] + node _T_89 = tail(_T_88, 1) @[Decoupled.scala 221:40] + node _T_90 = and(maybe_full, _T_57) @[Decoupled.scala 223:32] + node _T_91 = cat(_T_90, _T_89) @[Cat.scala 30:58] + io.count <= _T_91 @[Decoupled.scala 223:14] + + module AXI4Buffer_2 : + input clock : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>} - - io is invalid - cmem ram : UInt<64>[2] - reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_26, T_28) - node T_33 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_33) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, io.deq.ready) - node T_39 = and(io.enq.ready, io.enq.valid) - node T_41 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_39, T_41) - node T_43 = and(io.deq.ready, io.deq.valid) - node T_45 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_43, T_45) - when do_enq : - infer mport T_47 = ram[T_26], clk - T_47 <= io.enq.bits - node T_49 = eq(T_26, UInt<1>("h01")) - node T_51 = and(UInt<1>("h00"), T_49) - node T_54 = add(T_26, UInt<1>("h01")) - node T_55 = tail(T_54, 1) - node T_56 = mux(T_51, UInt<1>("h00"), T_55) - T_26 <= T_56 - skip - when do_deq : - node T_58 = eq(T_28, UInt<1>("h01")) - node T_60 = and(UInt<1>("h00"), T_58) - node T_63 = add(T_28, UInt<1>("h01")) - node T_64 = tail(T_63, 1) - node T_65 = mux(T_60, UInt<1>("h00"), T_64) - T_28 <= T_65 - skip - node T_66 = neq(do_enq, do_deq) - when T_66 : - maybe_full <= do_enq - skip - node T_68 = eq(empty, UInt<1>("h00")) - node T_70 = and(UInt<1>("h00"), io.enq.valid) - node T_71 = or(T_68, T_70) - io.deq.valid <= T_71 - node T_73 = eq(full, UInt<1>("h00")) - node T_75 = and(UInt<1>("h00"), io.deq.ready) - node T_76 = or(T_73, T_75) - io.enq.ready <= T_76 - infer mport T_77 = ram[T_28], clk - node T_78 = mux(maybe_flow, io.enq.bits, T_77) - io.deq.bits <= T_78 - node T_79 = sub(T_26, T_28) - node ptr_diff = tail(T_79, 1) - node T_81 = and(maybe_full, ptr_match) - node T_82 = cat(T_81, ptr_diff) - io.count <= T_82 - - module Top : - input clk : Clock + output io : {flip in : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}, out : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst Queue of Queue_56 @[Decoupled.scala 253:19] + Queue.io is invalid + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.0.aw.valid @[Decoupled.scala 254:20] + Queue.io.enq.bits <- io.in.0.aw.bits @[Decoupled.scala 255:19] + io.in.0.aw.ready <= Queue.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.aw <- Queue.io.deq @[Buffer.scala 31:26] + inst Queue_1 of Queue_57 @[Decoupled.scala 253:19] + Queue_1.io is invalid + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= io.in.0.w.valid @[Decoupled.scala 254:20] + Queue_1.io.enq.bits <- io.in.0.w.bits @[Decoupled.scala 255:19] + io.in.0.w.ready <= Queue_1.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.w <- Queue_1.io.deq @[Buffer.scala 32:26] + inst Queue_2 of Queue_58 @[Decoupled.scala 253:19] + Queue_2.io is invalid + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= io.out.0.b.valid @[Decoupled.scala 254:20] + Queue_2.io.enq.bits <- io.out.0.b.bits @[Decoupled.scala 255:19] + io.out.0.b.ready <= Queue_2.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.b <- Queue_2.io.deq @[Buffer.scala 33:26] + inst Queue_3 of Queue_59 @[Decoupled.scala 253:19] + Queue_3.io is invalid + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= io.in.0.ar.valid @[Decoupled.scala 254:20] + Queue_3.io.enq.bits <- io.in.0.ar.bits @[Decoupled.scala 255:19] + io.in.0.ar.ready <= Queue_3.io.enq.ready @[Decoupled.scala 256:15] + io.out.0.ar <- Queue_3.io.deq @[Buffer.scala 34:26] + inst Queue_4 of Queue_60 @[Decoupled.scala 253:19] + Queue_4.io is invalid + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= io.out.0.r.valid @[Decoupled.scala 254:20] + Queue_4.io.enq.bits <- io.out.0.r.bits @[Decoupled.scala 255:19] + io.out.0.r.ready <= Queue_4.io.enq.ready @[Decoupled.scala 256:15] + io.in.0.r <- Queue_4.io.deq @[Buffer.scala 35:26] + + module SimAXIMem_1 : + input clock : Clock input reset : UInt<1> - output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1]} - - io is invalid - inst uncore of Uncore - uncore.io is invalid - uncore.clk <= clk - uncore.reset <= reset - inst T_669 of RocketTile - T_669.io is invalid - T_669.clk <= clk - T_669.reset <= uncore.io.htif[0].reset - T_669.io.host.id <= UInt<1>("h00") - reg T_671 : UInt<1>, clk - T_671 <= uncore.io.htif[0].reset - reg T_672 : UInt<1>, clk - T_672 <= T_671 - T_669.io.host.reset <= T_672 - inst T_677 of Queue_124 - T_677.io is invalid - T_677.clk <= clk - T_677.reset <= reset - T_677.io.enq.valid <= uncore.io.htif[0].csr.req.valid - T_677.io.enq.bits <- uncore.io.htif[0].csr.req.bits - uncore.io.htif[0].csr.req.ready <= T_677.io.enq.ready - T_669.io.host.csr.req <- T_677.io.deq - inst T_679 of Queue_125 - T_679.io is invalid - T_679.clk <= clk - T_679.reset <= reset - T_679.io.enq.valid <= T_669.io.host.csr.resp.valid - T_679.io.enq.bits <= T_669.io.host.csr.resp.bits - T_669.io.host.csr.resp.ready <= T_679.io.enq.ready - uncore.io.htif[0].csr.resp <- T_679.io.deq - uncore.io.htif[0].debug_stats_csr <= T_669.io.host.debug_stats_csr - uncore.io.tiles_cached[0] <- T_669.io.cached[0] - uncore.io.tiles_uncached[0] <- T_669.io.uncached[0] - io.host <- uncore.io.host - io.mem_backup_ctrl <- uncore.io.mem_backup_ctrl - inst T_692 of Queue_36 - T_692.io is invalid - T_692.clk <= clk - T_692.reset <= reset - T_692.io.enq.valid <= uncore.io.mem[0].ar.valid - T_692.io.enq.bits <- uncore.io.mem[0].ar.bits - uncore.io.mem[0].ar.ready <= T_692.io.enq.ready - io.mem[0].ar <- T_692.io.deq - inst T_705 of Queue_36 - T_705.io is invalid - T_705.clk <= clk - T_705.reset <= reset - T_705.io.enq.valid <= uncore.io.mem[0].aw.valid - T_705.io.enq.bits <- uncore.io.mem[0].aw.bits - uncore.io.mem[0].aw.ready <= T_705.io.enq.ready - io.mem[0].aw <- T_705.io.deq - inst T_711 of Queue_74 - T_711.io is invalid - T_711.clk <= clk - T_711.reset <= reset - T_711.io.enq.valid <= uncore.io.mem[0].w.valid - T_711.io.enq.bits <- uncore.io.mem[0].w.bits - uncore.io.mem[0].w.ready <= T_711.io.enq.ready - io.mem[0].w <- T_711.io.deq - inst T_718 of Queue_75 - T_718.io is invalid - T_718.clk <= clk - T_718.reset <= reset - T_718.io.enq.valid <= io.mem[0].r.valid - T_718.io.enq.bits <- io.mem[0].r.bits - io.mem[0].r.ready <= T_718.io.enq.ready - uncore.io.mem[0].r <- T_718.io.deq - inst T_723 of Queue_76 - T_723.io is invalid - T_723.clk <= clk - T_723.reset <= reset - T_723.io.enq.valid <= io.mem[0].b.valid - T_723.io.enq.bits <- io.mem[0].b.bits - io.mem[0].b.ready <= T_723.io.enq.ready - uncore.io.mem[0].b <- T_723.io.deq - io.mem[0].ar.bits.cache <= UInt<4>("h03") - io.mem[0].aw.bits.cache <= UInt<4>("h03") - inst errslave of NastiErrorSlave_40 - errslave.io is invalid - errslave.clk <= clk - errslave.reset <= reset - errslave.io <- uncore.io.mmio + output io : {flip axi4 : {0 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, resp : UInt<2>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, addr : UInt<12>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<4>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}}} + + io is invalid + io is invalid + inst AXI4RAM of AXI4RAM_1 @[LazyModule.scala 60:13] + AXI4RAM.io is invalid + AXI4RAM.clock <= clock + AXI4RAM.reset <= reset + inst AXI4Fragmenter of AXI4Fragmenter_2 @[LazyModule.scala 60:13] + AXI4Fragmenter.io is invalid + AXI4Fragmenter.clock <= clock + AXI4Fragmenter.reset <= reset + inst AXI4Buffer of AXI4Buffer_2 @[LazyModule.scala 60:13] + AXI4Buffer.io is invalid + AXI4Buffer.clock <= clock + AXI4Buffer.reset <= reset + AXI4Fragmenter.io.in.0 <- io.axi4.0 @[TestHarness.scala 51:62] + AXI4Buffer.io.in.0 <- AXI4Fragmenter.io.out.0 @[TestHarness.scala 51:30] + AXI4RAM.io.in.0 <- AXI4Buffer.io.out.0 @[TestHarness.scala 51:15] + + module TestHarness : + input clock : Clock + input reset : UInt<1> + output io : {success : UInt<1>} + + io is invalid + io is invalid + inst ExampleRocketTop of ExampleRocketTop @[TestHarness.scala 16:19] + ExampleRocketTop.io is invalid + ExampleRocketTop.clock <= clock + ExampleRocketTop.reset <= reset + ExampleRocketTop.io.interrupts <= UInt<1>("h00") @[TestHarness.scala 18:21] + inst SimAXIMem of SimAXIMem @[TestHarness.scala 21:27] + SimAXIMem.io is invalid + SimAXIMem.clock <= clock + SimAXIMem.reset <= reset + SimAXIMem.io.axi4 <- ExampleRocketTop.io.mem_axi4 @[TestHarness.scala 21:80] + inst SimDTM of SimDTM @[TestHarness.scala 24:21] + SimDTM.exit is invalid + SimDTM.debug is invalid + SimDTM.reset is invalid + SimDTM.clk is invalid + SimDTM.clk <= clock @[TestHarness.scala 70:12] + SimDTM.reset <= reset @[TestHarness.scala 71:14] + ExampleRocketTop.io.debug <- SimDTM.debug @[TestHarness.scala 72:11] + node _T_10 = eq(SimDTM.exit, UInt<1>("h01")) @[TestHarness.scala 74:26] + io.success <= _T_10 @[TestHarness.scala 74:15] + node _T_12 = geq(SimDTM.exit, UInt<2>("h02")) @[TestHarness.scala 75:19] + when _T_12 : @[TestHarness.scala 75:31] + node _T_14 = dshr(SimDTM.exit, UInt<1>("h01")) @[TestHarness.scala 76:59] + node _T_16 = eq(reset, UInt<1>("h00")) @[TestHarness.scala 76:13] + when _T_16 : @[TestHarness.scala 76:13] + printf(clock, UInt<1>(1), "*** FAILED *** (exit code = %d)\n", _T_14) @[TestHarness.scala 76:13] + skip @[TestHarness.scala 76:13] + node _T_18 = eq(reset, UInt<1>("h00")) @[TestHarness.scala 77:11] + when _T_18 : @[TestHarness.scala 77:11] + stop(clock, UInt<1>(1), 1) @[TestHarness.scala 77:11] + skip @[TestHarness.scala 77:11] + skip @[TestHarness.scala 75:31] + inst SimAXIMem_1 of SimAXIMem_1 @[TestHarness.scala 29:24] + SimAXIMem_1.io is invalid + SimAXIMem_1.clock <= clock + SimAXIMem_1.reset <= reset + SimAXIMem_1.io.axi4 <- ExampleRocketTop.io.mmio_axi4 @[TestHarness.scala 30:20] + ExampleRocketTop.io.l2_frontend_bus_axi4.0.ar.valid <= UInt<1>("h00") @[TestHarness.scala 33:20] + ExampleRocketTop.io.l2_frontend_bus_axi4.0.aw.valid <= UInt<1>("h00") @[TestHarness.scala 34:20] + ExampleRocketTop.io.l2_frontend_bus_axi4.0.w.valid <= UInt<1>("h00") @[TestHarness.scala 35:20] + ExampleRocketTop.io.l2_frontend_bus_axi4.0.r.ready <= UInt<1>("h01") @[TestHarness.scala 36:20] + ExampleRocketTop.io.l2_frontend_bus_axi4.0.b.ready <= UInt<1>("h01") @[TestHarness.scala 37:20] -- cgit v1.2.3